1560 files changed, 267430 insertions, 16185 deletions

diff --git a/Kconfig b/Kconfig
index 9dd9ec7f6df..da1444fc7bb 100644
--- a/Kconfig
+++ b/Kconfig
@@ -403,7 +403,7 @@ config SYS_LOAD_ADDR
 	default 0x22000000 if MACH_SUN9I
 	default 0x42000000 if ARCH_SUNXI
 	default 0x82000000 if ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
-	default 0x82000000 if ARCH_MX6 && (MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
+	default 0x80800000 if ARCH_MX6 && (MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
 	default 0x12000000 if ARCH_MX6 && !(MX6SL || MX6SLL  || MX6SX || MX6UL || MX6ULL)
 	default 0x80800000 if ARCH_MX7
 	default 0x90000000 if FSL_LSCH2 || FSL_LSCH3
diff --git a/MAINTAINERS b/MAINTAINERS
index 96582fc6777..404a8e96531 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1376,3 +1376,9 @@ T:	git https://source.denx.de/u-boot/u-boot.git
 F:	configs/tools-only_defconfig
 F:	*
 F:	*/
+
+CAAM
+M:	Gaurav Jain <gaurav.jain@nxp.com>
+S:	Maintained
+F:	drivers/crypto/fsl/
+F:	include/fsl_sec.h
diff --git a/Makefile b/Makefile
index ad83d60dc39..33615b8706c 100644
--- a/Makefile
+++ b/Makefile
@@ -823,6 +823,7 @@ libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
 libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/
 libs-$(CONFIG_$(SPL_)ALTERA_SDRAM) += drivers/ddr/altera/
 libs-y += drivers/usb/cdns3/
+libs-y += drivers/usb/imx/
 libs-y += drivers/usb/dwc3/
 libs-y += drivers/usb/common/
 libs-y += drivers/usb/emul/
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4567c183fb8..4e07fc88f67 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -806,6 +806,9 @@ config ARCH_LPC32XX
 config ARCH_IMX8
 	bool "NXP i.MX8 platform"
 	select ARM64
+	select SYS_FSL_HAS_SEC
+	select SYS_FSL_SEC_COMPAT_4
+	select SYS_FSL_SEC_LE
 	select DM
 	select GPIO_EXTRA_HEADER
 	select MACH_IMX
@@ -817,7 +820,7 @@ config ARCH_IMX8M
 	select ARM64
 	select GPIO_EXTRA_HEADER
 	select MACH_IMX
-	select SYS_FSL_HAS_SEC if IMX_HAB
+	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
 	select SYS_I2C_MXC
@@ -833,6 +836,22 @@ config ARCH_IMX8ULP
 	select OF_CONTROL
 	select SUPPORT_SPL
 	select GPIO_EXTRA_HEADER
+	select SYS_FSL_HAS_SEC
+	select SYS_FSL_SEC_LE
+	select SYS_FSL_SEC_COMPAT_4
+	select MISC
+	select IMX_SENTINEL
+	imply CMD_DM
+
+config ARCH_IMX9
+	bool "NXP i.MX9 platform"
+	select ARM64
+	select DM
+	select MACH_IMX
+	select SUPPORT_SPL
+	select GPIO_EXTRA_HEADER
+	select MISC
+	select IMX_SENTINEL
 	imply CMD_DM
 
 config ARCH_IMXRT
@@ -872,7 +891,7 @@ config ARCH_MX7ULP
 	select CPU_V7A
 	select GPIO_EXTRA_HEADER
 	select MACH_IMX
-	select SYS_FSL_HAS_SEC if IMX_HAB
+	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
 	select ROM_UNIFIED_SECTIONS
@@ -885,7 +904,7 @@ config ARCH_MX7
 	select CPU_V7A
 	select GPIO_EXTRA_HEADER
 	select MACH_IMX
-	select SYS_FSL_HAS_SEC if IMX_HAB
+	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_4
 	select SYS_FSL_SEC_LE
 	imply BOARD_EARLY_INIT_F
@@ -2136,6 +2155,8 @@ source "arch/arm/mach-imx/imx8m/Kconfig"
 
 source "arch/arm/mach-imx/imx8ulp/Kconfig"
 
+source "arch/arm/mach-imx/imx9/Kconfig"
+
 source "arch/arm/mach-imx/imxrt/Kconfig"
 
 source "arch/arm/mach-imx/mxs/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ad757e982e3..5bfc30861b3 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -32,6 +32,10 @@ else
 arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH)
 endif
 
+ifneq ($(CONFIG_ARCH_IMX8)$(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8ULP)$(CONFIG_ARCH_IMX9),)
+arch-y += -mgeneral-regs-only
+endif
+
 # Evaluate arch cc-option calls now
 arch-y := $(arch-y)
 
@@ -112,11 +116,11 @@ libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/
 
 ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imx9 imxrt))
 libs-y += arch/arm/mach-imx/
 endif
 else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imx8ulp imxrt vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imx8ulp imx9 imxrt vf610))
 libs-y += arch/arm/mach-imx/
 endif
 endif
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index b107b1af27a..3c01e8ac25b 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -160,6 +160,10 @@ OBJCOPYFLAGS += -j .efi_runtime -j .efi_runtime_rel
 endif
 
 ifdef CONFIG_MACH_IMX
+ifdef CONFIG_IMX_M4_BIND
+OBJCOPYFLAGS += -j .firmware_image
+endif
+
 ifneq ($(CONFIG_IMX_CONFIG),"")
 ifdef CONFIG_SPL
 ifndef CONFIG_SPL_BUILD
diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c
index 4e1cf3a1e32..6a77de64db9 100644
--- a/arch/arm/cpu/arm926ejs/mxs/clock.c
+++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -7,6 +7,8 @@
  *
  * Based on code from LTIB:
  * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
+ *
  */
 
 #include <common.h>
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index d863c9625aa..0b3e3b20641 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -20,6 +21,7 @@
 #include <config.h>
 #include <fsl_wdog.h>
 #include <linux/delay.h>
+#include <dm.h>
 
 #include "fsl_epu.h"
 
@@ -397,3 +399,19 @@ void arch_preboot_os(void)
 	ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
 	asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
 }
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+		struct udevice *dev;
+		int ret;
+
+		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+		if (ret)
+			printf("Failed to initialize caam_jr: %d\n", ret);
+	}
+
+	return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 2ded3e4efc9..16650526e7d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2017-2020 NXP
+ * Copyright 2017-2021 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  */
 
@@ -49,6 +49,7 @@
 #endif
 #endif
 #include <linux/mii.h>
+#include <dm.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -1650,6 +1651,14 @@ __weak int serdes_misc_init(void)
 
 int arch_misc_init(void)
 {
+	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+		struct udevice *dev;
+		int ret;
+
+		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+		if (ret)
+			printf("Failed to initialize caam_jr: %d\n", ret);
+	}
 	serdes_misc_init();
 
 	return 0;
diff --git a/arch/arm/cpu/armv8/xen/Makefile b/arch/arm/cpu/armv8/xen/Makefile
index e3b4ae2bd40..fc27329f49b 100644
--- a/arch/arm/cpu/armv8/xen/Makefile
+++ b/arch/arm/cpu/armv8/xen/Makefile
@@ -3,4 +3,4 @@
 # (C) 2018 NXP
 # (C) 2020 EPAM Systems Inc.
 
-obj-y += lowlevel_init.o hypercall.o
+obj-y += lowlevel_init.o hypercall.o print.o
diff --git a/arch/arm/cpu/armv8/xen/print.c b/arch/arm/cpu/armv8/xen/print.c
new file mode 100644
index 00000000000..1a2c7a68a6a
--- /dev/null
+++ b/arch/arm/cpu/armv8/xen/print.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <asm/xen/hypercall.h>
+#include <xen/interface/xen.h>
+
+/*
+ * To non privileged domain, need CONFIG_VERBOSE_DEBUG in XEN to 
+ * get output.
+ */
+void xenprintf(char *buf)
+{
+	(void)HYPERVISOR_console_io(CONSOLEIO_write, strlen(buf), buf);
+	return;
+}
+
+void xenprintc(char c)
+{
+	(void)HYPERVISOR_console_io(CONSOLEIO_write, 1, &c);
+	return;
+}
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 0eb164d2e69..76f45d2a085 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -177,6 +177,22 @@ SECTIONS
 		*(.__image_copy_end)
 	}
 
+#ifdef CONFIG_IMX_M4_BIND
+	.firmware_image_start : {
+                *(.__firmware_image_start)
+        }
+
+	.firmware_image : {
+		KEEP(*(.firmware_image))
+        }
+
+	.firmware_image_end : {
+                *(.__firmware_image_end)
+        }
+
+	. = ALIGN(4);
+#endif
+
 	.rel_dyn_start :
 	{
 		*(.__rel_dyn_start)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b8017fdbf6b..d596915747d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -762,12 +762,14 @@ dtb-y += \
 	imx6dl-udoo.dtb \
 	imx6dl-riotboard.dtb \
 	imx6dl-sabreauto.dtb \
+	imx6dl-sabreauto-ecspi.dtb \
+	imx6dl-sabreauto-gpmi-weim.dtb \
 	imx6dl-sabresd.dtb \
 	imx6dl-wandboard-revd1.dtb \
 
 endif
 
-ifneq ($(CONFIG_MX6Q)$(CONFIG_MX6QDL),)
+ifneq ($(CONFIG_MX6Q)$(CONFIG_MX6QDL)$(CONFIG_MX6QP),)
 dtb-y += \
 	imx6-apalis.dtb \
 	imx6q-cm-fx6.dtb \
@@ -811,11 +813,15 @@ dtb-y += \
 	imx6q-phytec-mira-rdk-nand.dtb \
 	imx6q-udoo.dtb \
 	imx6q-sabreauto.dtb \
+	imx6q-sabreauto-ecspi.dtb \
+	imx6q-sabreauto-gpmi-weim.dtb \
 	imx6q-sabrelite.dtb \
 	imx6q-sabresd.dtb \
 	imx6q-tbs2910.dtb \
 	imx6q-wandboard-revd1.dtb \
 	imx6qp-sabreauto.dtb \
+	imx6qp-sabreauto-ecspi.dtb \
+	imx6qp-sabreauto-gpmi-weim.dtb \
 	imx6qp-sabresd.dtb \
 	imx6qp-wandboard-revd1.dtb \
 
@@ -823,11 +829,22 @@ endif
 
 dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb
 
-dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb
+dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb \
+	imx6sll-lpddr2-val.dtb \
+	imx6sll-lpddr3-val.dtb \
+	imx6sll-lpddr3-val-ecspi.dtb
 
 dtb-$(CONFIG_MX6SX) += \
+	imx6sx-14x14-val.dtb \
+	imx6sx-17x17-val.dtb \
+	imx6sx-17x17-val-ecspi.dtb \
+	imx6sx-17x17-val-gpmi-weim.dtb \
+	imx6sx-19x19-val.dtb \
+	imx6sx-19x19-val-ecspi.dtb \
+	imx6sx-19x19-val-gpmi-weim.dtb \
 	imx6sx-sabreauto.dtb \
 	imx6sx-sdb.dtb \
+	imx6sx-sdb-emmc.dtb \
 	imx6sx-softing-vining-2000.dtb \
 	imx6sx-udoo-neo-basic.dtb \
 	imx6sx-udoo-neo-extended.dtb \
@@ -838,8 +855,13 @@ dtb-$(CONFIG_MX6UL) += \
 	imx6ul-isiot-emmc.dtb \
 	imx6ul-isiot-nand.dtb \
 	imx6ul-opos6uldev.dtb \
+	imx6ul-14x14-ddr3-val.dtb \
+	imx6ul-14x14-ddr3-val-emmc.dtb \
+	imx6ul-14x14-ddr3-val-gpmi-weim.dtb \
+	imx6ul-14x14-lpddr2-val.dtb \
 	imx6ul-14x14-evk.dtb \
-	imx6ul-9x9-evk.dtb \
+	imx6ul-14x14-evk-emmc.dtb \
+	imx6ul-14x14-evk-gpmi-weim.dtb \
 	imx6ul-9x9-evk.dtb \
 	imx6ul-liteboard.dtb \
 	imx6ul-phytec-segin-ff-rdk-nand.dtb \
@@ -849,7 +871,15 @@ dtb-$(CONFIG_MX6UL) += \
 	imx6ull-kontron-n641x-s.dtb
 
 dtb-$(CONFIG_MX6ULL) += \
+	imx6ull-14x14-ddr3-val.dtb \
+	imx6ull-14x14-ddr3-val-epdc.dtb \
+	imx6ull-14x14-ddr3-val-emmc.dtb \
+	imx6ull-14x14-ddr3-val-gpmi-weim.dtb \
+	imx6ull-14x14-ddr3-val-tsc.dtb \
 	imx6ull-14x14-evk.dtb \
+	imx6ull-14x14-evk-emmc.dtb \
+	imx6ull-14x14-evk-gpmi-weim.dtb \
+	imx6ull-9x9-evk.dtb \
 	imx6ull-colibri.dtb \
 	imx6ull-colibri-emmc.dtb \
 	imx6ull-myir-mys-6ulx-eval.dtb \
@@ -857,7 +887,9 @@ dtb-$(CONFIG_MX6ULL) += \
 	imx6ull-phytec-segin-ff-rdk-emmc.dtb \
 	imx6ull-dart-6ul.dtb \
 	imx6ull-somlabs-visionsom.dtb \
-	imx6ulz-14x14-evk.dtb
+	imx6ulz-14x14-evk.dtb \
+	imx6ulz-14x14-evk-emmc.dtb \
+	imx6ulz-14x14-evk-gpmi-weim.dtb
 
 dtb-$(CONFIG_ARCH_MX6) += \
 	imx6-apalis.dtb \
@@ -871,37 +903,72 @@ dtb-$(CONFIG_EV_IMX280_NANO_X_MB) += \
 
 dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
 	imx7d-sdb-qspi.dtb \
-	imx7-cm.dtb \
+	imx7d-sdb-epdc.dtb \
+	imx7d-sdb-gpmi-weim.dtb \
+	imx7d-sdb-reva.dtb \
 	imx7-colibri-emmc.dtb \
 	imx7-colibri-rawnand.dtb \
 	imx7s-warp.dtb \
 	imx7d-meerkat96.dtb \
 	imx7d-pico-pi.dtb \
 	imx7d-pico-hobbit.dtb \
-	imx7d-smegw01.dtb
+	imx7d-smegw01.dtb \
+	imx7d-12x12-lpddr3-val.dtb \
+	imx7d-12x12-lpddr3-val-ecspi.dtb \
+	imx7d-12x12-lpddr3-val-qspi.dtb \
+	imx7d-12x12-ddr3-val.dtb \
+	imx7d-19x19-ddr3-val.dtb \
+	imx7d-19x19-lpddr2-val.dtb \
+	imx7d-19x19-lpddr3-val.dtb
 
 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
-	imx7ulp-evk.dtb
+	imx7ulp-10x10-val.dtb \
+	imx7ulp-14x14-val.dtb \
+	imx7ulp-evk.dtb \
+	imx7ulp-evk-emmc.dtb \
+	imx7ulp-evk-qspi.dtb
 
 dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
 
 dtb-$(CONFIG_ARCH_IMX8) += \
 	fsl-imx8qm-apalis.dtb \
 	fsl-imx8qm-mek.dtb \
+	fsl-imx8qm-ddr4-val.dtb \
+	fsl-imx8qm-lpddr4-val.dtb \
+	fsl-imx8qm-mek-cockpit-a53.dtb \
+	fsl-imx8qm-mek-cockpit-a72.dtb \
+	fsl-imx8qm-mek-xen.dtb \
 	imx8qm-cgtqmx8.dtb \
 	imx8qm-rom7720-a1.dtb \
 	fsl-imx8qxp-ai_ml.dtb \
 	fsl-imx8qxp-colibri.dtb \
 	fsl-imx8qxp-apalis.dtb \
 	fsl-imx8qxp-mek.dtb \
+	fsl-imx8qxp-lpddr4-val.dtb \
+	fsl-imx8qxp-lpddr4-val-gpmi-nand.dtb \
+	fsl-imx8qxp-17x17-val.dtb \
+	fsl-imx8dx-17x17-val.dtb \
+	fsl-imx8dx-mek.dtb \
+	fsl-imx8dxl-phantom-mek.dtb \
+	fsl-imx8dxl-evk.dtb \
+	fsl-imx8dxl-evk-lcdif.dtb \
+	fsl-imx8dxl-ddr3l-evk.dtb \
 	imx8-deneb.dtb \
 	imx8-giedi.dtb
 
 dtb-$(CONFIG_ARCH_IMX8ULP) += \
-	imx8ulp-evk.dtb
+	imx8ulp-evk.dtb \
+	imx8ulp-evk-i3c.dtb \
+	imx8ulp-9x9-evk.dtb \
+	imx8ulp-9x9-evk-i3c.dtb
 
 dtb-$(CONFIG_ARCH_IMX8M) += \
+	imx8mm-ddr4-evk.dtb \
+	imx8mm-ddr4-ab2.dtb \
+	imx8mm-ddr3l-val.dtb \
+	imx8mm-ddr4-val.dtb \
 	imx8mm-evk.dtb \
+	imx8mm-ab2.dtb \
 	imx8mm-icore-mx8mm-ctouch2.dtb \
 	imx8mm-icore-mx8mm-edimm2.2.dtb \
 	imx8mm-kontron-n801x-s.dtb \
@@ -914,23 +981,32 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mm-venice-gw7902.dtb \
 	imx8mm-verdin.dtb \
 	phycore-imx8mm.dtb \
+	imx8mn-ddr3l-evk.dtb \
 	imx8mn-ddr4-evk.dtb \
+	imx8mn-ddr4-ab2.dtb \
 	imx8mq-cm.dtb \
 	imx8mn-evk.dtb \
+	imx8mn-ab2.dtb \
 	imx8mn-var-som-symphony.dtb \
 	imx8mn-venice.dtb \
 	imx8mn-venice-gw7902.dtb \
+	imx8mq-ddr3l-val.dtb \
+	imx8mq-ddr4-val.dtb \
 	imx8mq-evk.dtb \
 	imx8mm-beacon-kit.dtb \
 	imx8mn-beacon-kit.dtb \
 	imx8mq-mnt-reform2.dtb \
 	imx8mq-phanbell.dtb \
+	imx8mp-ddr4-evk.dtb \
 	imx8mp-evk.dtb \
 	imx8mp-phyboard-pollux-rdk.dtb \
 	imx8mp-verdin.dtb \
 	imx8mq-pico-pi.dtb \
 	imx8mq-kontron-pitx-imx8m.dtb
 
+dtb-$(CONFIG_ARCH_IMX9) += \
+	imx93-11x11-evk.dtb
+
 dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
 	imxrt1020-evk.dtb
 
diff --git a/arch/arm/dts/fsl-imx8-ca53.dtsi b/arch/arm/dts/fsl-imx8-ca53.dtsi
index 6a2292a51ec..b2039d2f9aa 100644
--- a/arch/arm/dts/fsl-imx8-ca53.dtsi
+++ b/arch/arm/dts/fsl-imx8-ca53.dtsi
@@ -12,6 +12,8 @@
  * GNU General Public License for more details.
  */
 
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
 /{
 	cpus {
 		#address-cells = <2>;
@@ -22,7 +24,6 @@
 
 			CPU_SLEEP: cpu-sleep {
 				compatible = "arm,idle-state";
-				local-timer-stop;
 				arm,psci-suspend-param = <0x0000000>;
 				entry-latency-us = <700>;
 				exit-latency-us = <250>;
@@ -31,7 +32,6 @@
 
 			CLUSTER_SLEEP: cluster-sleep {
 				compatible = "arm,idle-state";
-				local-timer-stop;
 				arm,psci-suspend-param = <0x1000000>;
 				entry-latency-us = <1000>;
 				exit-latency-us = <700>;
@@ -89,4 +89,11 @@
 		cpu_off	      = <0xc4000002>;
 		cpu_on	      = <0xc4000003>;
 	};
+
+	pmu {
+                compatible = "arm,armv8-pmuv3";
+                interrupts = <GIC_PPI 7
+                        (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+                interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
+        };
 };
diff --git a/arch/arm/dts/fsl-imx8-ca72.dtsi b/arch/arm/dts/fsl-imx8-ca72.dtsi
new file mode 100644
index 00000000000..92f8aa60cae
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8-ca72.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2018 NXP
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+/ {
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP: cpu-sleep {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0000000>;
+				entry-latency-us = <700>;
+				exit-latency-us = <250>;
+				min-residency-us = <1000>;
+			};
+
+			CLUSTER_SLEEP: cluster-sleep {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x1000000>;
+				entry-latency-us = <1000>;
+				exit-latency-us = <700>;
+				min-residency-us = <2700>;
+				wakeup-latency-us = <1500>;
+			};
+		};
+
+		/* We have 2nd clusters having 2 Cortex-A72 cores */
+		A72_0: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72","arm,armv8";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			next-level-cache = <&A72_L2>;
+			cpu-idle-states = <&CPU_SLEEP>;
+		};
+
+		A72_1: cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72","arm,armv8";
+			reg = <0x0 0x101>;
+			enable-method = "psci";
+			next-level-cache = <&A72_L2>;
+			cpu-idle-states = <&CPU_SLEEP>;
+		};
+
+		A72_L2: l2-cache1 {
+			compatible = "cache";
+		};
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7
+			(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupt-affinity = <&A72_0>, <&A72_1>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+		cpu_suspend   = <0xc4000001>;
+		cpu_off       = <0xc4000002>;
+		cpu_on        = <0xc4000003>;
+	};
+};
diff --git a/arch/arm/dts/fsl-imx8dx-17x17-val.dts b/arch/arm/dts/fsl-imx8dx-17x17-val.dts
new file mode 100644
index 00000000000..970fac337ee
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8dx-17x17-val.dts
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "fsl-imx8qxp-17x17-val.dts"
+
+/ {
+	model = "NXP i.MX8DX 17x17 Validation board";
+};
diff --git a/arch/arm/dts/fsl-imx8dx-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8dx-mek-u-boot.dtsi
new file mode 100644
index 00000000000..f89a781b2a8
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8dx-mek-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "fsl-imx8qxp-mek-u-boot.dtsi"
diff --git a/arch/arm/dts/fsl-imx8dx-mek.dts b/arch/arm/dts/fsl-imx8dx-mek.dts
new file mode 100644
index 00000000000..52055ff4790
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8dx-mek.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "fsl-imx8qxp-mek.dts"
+
+/ {
+	model = "NXP i.MX8DX MEK";
+};
diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi
index 7d95cf0b7dc..e2b4fcf0777 100644
--- a/arch/arm/dts/fsl-imx8dx.dtsi
+++ b/arch/arm/dts/fsl-imx8dx.dtsi
@@ -1,11 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "fsl-imx8-ca35.dtsi"
 #include <dt-bindings/soc/imx_rsrc.h>
+#include <dt-bindings/soc/imx8_hsio.h>
 #include <dt-bindings/soc/imx8_pd.h>
 #include <dt-bindings/clock/imx8qxp-clock.h>
 #include <dt-bindings/input/input.h>
@@ -14,23 +15,35 @@
 #include <dt-bindings/thermal/thermal.h>
 
 / {
-	model = "Freescale i.MX8DX";
+	model = "NXP i.MX8DX";
 	compatible = "fsl,imx8dx", "fsl,imx8qxp";
 	interrupt-parent = <&gic>;
 	#address-cells = <2>;
 	#size-cells = <2>;
 
 	aliases {
+		csi0 = &mipi_csi_0;
+		video0 = &dpu1;
 		ethernet0 = &fec1;
 		ethernet1 = &fec2;
+		dsiphy0 = &mipi_dsi_phy1;
+		dsiphy1 = &mipi_dsi_phy2;
+		mipidsi0 = &mipi_dsi1;
+		mipidsi1 = &mipi_dsi2;
+		display0 = &ldb1;
+		display1 = &ldb2;
+		isi0 = &isi_0;
+		isi1 = &isi_1;
+		isi2 = &isi_2;
+		isi3 = &isi_3;
+		isi4 = &isi_4;
+		isi5 = &isi_5;
+		isi6 = &isi_6;
+		isi7 = &isi_7;
 		serial0 = &lpuart0;
-		mmc0 = &usdhc1;
-		mmc1 = &usdhc2;
-		mmc2 = &usdhc3;
-		i2c0 = &i2c0;
-		i2c1 = &i2c1;
-		i2c2 = &i2c2;
-		i2c3 = &i2c3;
+		serial1 = &lpuart1;
+		serial2 = &lpuart2;
+		serial3 = &lpuart3;
 		gpio0 = &gpio0;
 		gpio1 = &gpio1;
 		gpio2 = &gpio2;
@@ -39,6 +52,48 @@
 		gpio5 = &gpio5;
 		gpio6 = &gpio6;
 		gpio7 = &gpio7;
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+		mmc2 = &usdhc3;
+		can0 = &flexcan1;
+		can1 = &flexcan2;
+		can2 = &flexcan3;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c13 = &i2c0_mipi_lvds0;
+		i2c15 = &i2c0_mipi_lvds1;
+		spi0 = &flexspi0;
+		usb0 = &usbotg1;
+		usbphy0 = &usbphy1;
+		usb1 = &usbotg3;
+		pci0 = &pcieb;
+		spi1 = &lpspi0;
+	};
+
+	cpus {
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP: cpu-sleep {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x10000>;
+				local-timer-stop;
+				entry-latency-us = <500>;
+				exit-latency-us = <500>;
+				min-residency-us = <5000>;
+			};
+
+			CLUSTER_SLEEP: cluster-sleep {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x10033>;
+				local-timer-stop;
+				entry-latency-us = <500>;
+				exit-latency-us = <2300>;
+				min-residency-us = <14000>;
+			};
+		};
 	};
 
 	memory@80000000 {
@@ -64,34 +119,39 @@
 		};
 		encoder_boot: encoder_boot@0x86000000 {
 			no-map;
-			reg = <0 0x86000000 0 0x2000000>;
+			reg = <0 0x86000000 0 0x200000>;
 		};
 		rpmsg_reserved: rpmsg@0x90000000 {
 			no-map;
 			reg = <0 0x90000000 0 0x400000>;
 		};
-		decoder_rpc: decoder_rpc@0x90400000 {
+		rpmsg_dma_reserved:rpmsg_dma@0x90400000 {
+			compatible = "shared-dma-pool";
+			no-map;
+			reg = <0 0x90400000 0 0x1C00000>;
+		};
+		decoder_rpc: decoder_rpc@0x92000000 {
 			no-map;
-			reg = <0 0x90400000 0 0x1000000>;
+			reg = <0 0x92000000 0 0x200000>;
 		};
-		encoder_rpc: encoder_rpc@0x91400000 {
+		encoder_rpc: encoder_rpc@0x92200000 {
 			no-map;
-			reg = <0 0x91400000 0 0x1000000>;
+			reg = <0 0x92200000 0 0x200000>;
 		};
 		dsp_reserved: dsp@0x92400000 {
 			no-map;
 			reg = <0 0x92400000 0 0x2000000>;
 		};
-		decoder_str: str@0x94400000 {
+		encoder_reserved: encoder_reserved@0x94400000 {
 			no-map;
-			reg = <0 0x94400000 0 0x1800000>;
+			reg = <0 0x94400000 0 0x800000>;
 		};
 		/* global autoconfigured region for contiguous allocations */
 		linux,cma {
 			compatible = "shared-dma-pool";
 			reusable;
-			size = <0 0x28000000>;
-			alloc-ranges = <0 0x96000000 0 0x28000000>;
+			size = <0 0x3c000000>;
+			alloc-ranges = <0 0x96000000 0 0x3c000000>;
 			linux,cma-default;
 		};
 	};
@@ -107,6 +167,14 @@
 		interrupt-parent = <&gic>;
 	};
 
+	mu8: mu@5d230000 {
+		compatible = "fsl,imx-m4-mu";
+		reg = <0x0 0x5d230000 0x0 0x10000>;
+		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&pd_lsio_mu8a>;
+		status = "okay";
+	};
+
 	mu: mu@5d1c0000 {
 		compatible = "fsl,imx8-mu";
 		reg = <0x0 0x5d1c0000 0x0 0x10000>;
@@ -124,6 +192,52 @@
 		};
 	};
 
+	mu13: mu13@5d280000 {
+		compatible = "fsl,imx8-mu-dsp";
+		reg = <0x0 0x5d280000 0x0 0x10000>;
+		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,dsp_ap_mu_id = <13>;
+		status = "okay";
+	};
+
+	mu_m4: mu_m4@37440000 {
+		compatible = "fsl,imx8-mu0-vpu-m4";
+		reg = <0x0 0x37440000 0x0 0x10000>;
+		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,vpu_ap_mu_id = <15>;
+		status = "okay";
+	};
+
+	mu_m0: mu_m0@2d000000 {
+		compatible = "fsl,imx8-mu0-vpu-m0";
+		reg = <0x0 0x2d000000 0x0 0x20000>;
+		interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,vpu_ap_mu_id = <16>;
+		status = "okay";
+	};
+
+	mu1_m0: mu1_m0@2d020000 {
+		compatible = "fsl,imx8-mu1-vpu-m0";
+		reg = <0x0 0x2d020000 0x0 0x20000>;
+		interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,vpu_ap_mu_id = <17>;
+		status = "okay";
+	};
+
+	rtc: rtc {
+		compatible = "fsl,imx-sc-rtc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+		clock-frequency = <8000000>;
+		interrupt-parent = <&gic>;
+	};
+
 	imx8qx-pm {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -136,6 +250,51 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
+			pd_lsio_pwm0: PD_LSIO_PWM_0 {
+				reg = <SC_R_PWM_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_pwm1: PD_LSIO_PWM_1 {
+				reg = <SC_R_PWM_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_pwm2: PD_LSIO_PWM_2 {
+				reg = <SC_R_PWM_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_pwm3: PD_LSIO_PWM_3 {
+				reg = <SC_R_PWM_3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_pwm4: PD_LSIO_PWM_4 {
+				reg = <SC_R_PWM_4>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_pwm5: PD_LSIO_PWM_5 {
+				reg = <SC_R_PWM_5>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_pwm6: PD_LSIO_PWM_6 {
+				reg = <SC_R_PWM_6>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_pwm7: PD_LSIO_PWM_7 {
+				reg = <SC_R_PWM_7>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_kpp: PD_LSIO_KPP {
+				reg = <SC_R_KPP>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
 			pd_lsio_gpio0: PD_LSIO_GPIO_0 {
 				reg = <SC_R_GPIO_0>;
 				#power-domain-cells = <0>;
@@ -166,7 +325,7 @@
 				#power-domain-cells = <0>;
 				power-domains = <&pd_lsio>;
 			};
-			pd_lsio_gpio6: PD_LSIO_GPIO_6 {
+			pd_lsio_gpio6:PD_LSIO_GPIO_6 {
 				reg = <SC_R_GPIO_6>;
 				#power-domain-cells = <0>;
 				power-domains = <&pd_lsio>;
@@ -176,6 +335,51 @@
 				#power-domain-cells = <0>;
 				power-domains = <&pd_lsio>;
 			};
+			pd_lsio_gpt0: PD_LSIO_GPT_0 {
+				reg = <SC_R_GPT_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpt1: PD_LSIO_GPT_1 {
+				reg = <SC_R_GPT_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpt2: PD_LSIO_GPT_2 {
+				reg = <SC_R_GPT_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpt3: PD_LSIO_GPT_3 {
+				reg = <SC_R_GPT_3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpt4: PD_LSIO_GPT_4 {
+				reg = <SC_R_GPT_4>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_flexspi0: PD_LSIO_FSPI_0 {
+				reg = <SC_R_FSPI_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_flexspi1: PD_LSIO_FSPI_1{
+				reg = <SC_R_FSPI_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_mu5a: PD_LSIO_MU5A {
+				reg = <SC_R_MU_5A>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_mu8a: PD_LSIO_MU8A {
+				reg = <SC_R_MU_8A>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
 		};
 
 		pd_conn: PD_CONN {
@@ -185,6 +389,43 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
+			pd_conn_usbotg0: PD_CONN_USB_0 {
+				reg = <SC_R_USB_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				wakeup-irq = <267>;
+
+				pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY {
+					reg = <SC_R_USB_0_PHY>;
+					#power-domain-cells = <0>;
+					power-domains = <&pd_conn_usbotg0>;
+					wakeup-irq = <267>;
+				};
+
+			};
+			pd_conn_usbotg1: PD_CONN_USB_1 {
+				reg = <SC_R_USB_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+			};
+			pd_conn_usb2: PD_CONN_USB_2 {
+				reg = <SC_R_USB_2>;
+				#power-domain-cells = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&pd_conn>;
+				wakeup-irq = <271>;
+
+				pd_conn_usb2_phy: PD_CONN_USB_2_PHY {
+					reg = <SC_R_USB_2_PHY>;
+					#power-domain-cells = <0>;
+					power-domains = <&pd_conn_usb2>;
+					wakeup-irq = <271>;
+				};
+
+			};
 			pd_conn_sdch0: PD_CONN_SDHC_0 {
 				reg = <SC_R_SDHC_0>;
 				#power-domain-cells = <0>;
@@ -204,11 +445,421 @@
 				reg = <SC_R_ENET_0>;
 				#power-domain-cells = <0>;
 				power-domains = <&pd_conn>;
+                                wakeup-irq = <258>;
 			};
 			pd_conn_enet1: PD_CONN_ENET_1 {
 				reg = <SC_R_ENET_1>;
 				#power-domain-cells = <0>;
 				power-domains = <&pd_conn>;
+                                fsl,wakeup_irq = <262>;
+			};
+			pd_conn_nand: PD_CONN_NAND {
+				reg = <SC_R_NAND>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+			};
+			pd_conn_mlb0: PD_CONN_MLB_0 {
+				reg = <SC_R_MLB_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+			};
+			pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 {
+				reg = <SC_R_DMA_4_CH0>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_conn>;
+			};
+			pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 {
+				reg = <SC_R_DMA_4_CH1>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_conn>;
+			};
+			pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 {
+				reg = <SC_R_DMA_4_CH2>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_conn>;
+			};
+			pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 {
+				reg = <SC_R_DMA_4_CH3>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_conn>;
+			};
+			pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 {
+				reg = <SC_R_DMA_4_CH4>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_conn>;
+			};
+		};
+
+		pd_audio: PD_AUDIO {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_NONE>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_audio_pll0: PD_AUD_AUDIO_PLL_0 {
+				reg = <SC_R_AUDIO_PLL_0>;
+				power-domains =<&pd_audio>;
+				#power-domain-cells = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_audio_pll1: PD_AUD_AUDIO_PLL_1 {
+					reg = <SC_R_AUDIO_PLL_1>;
+					power-domains =<&pd_audio_pll0>;
+					#power-domain-cells = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_audio_clk0: PD_AUD_AUDIO_CLK_0 {
+						reg = <SC_R_AUDIO_CLK_0>;
+						power-domains =<&pd_audio_pll1>;
+						#power-domain-cells = <0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						pd_audio_clk1: PD_AUD_AUDIO_CLK_1 {
+							reg = <SC_R_AUDIO_CLK_1>;
+							#power-domain-cells = <0>;
+							power-domains =<&pd_audio_clk0>;
+							#address-cells = <1>;
+							#size-cells = <0>;
+
+							pd_dma0_chan0: PD_ASRC_0_RXA {
+								reg = <SC_R_DMA_0_CH0>;
+								power-domains =<&pd_audio_clk1>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma0_chan1: PD_ASRC_0_RXB {
+								reg = <SC_R_DMA_0_CH1>;
+								power-domains =<&pd_dma0_chan0>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma0_chan2: PD_ASRC_0_RXC {
+								reg = <SC_R_DMA_0_CH2>;
+								power-domains =<&pd_dma0_chan1>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma0_chan3: PD_ASRC_0_TXA {
+								reg = <SC_R_DMA_0_CH3>;
+								power-domains =<&pd_dma0_chan2>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma0_chan4: PD_ASRC_0_TXB {
+								reg = <SC_R_DMA_0_CH4>;
+								power-domains =<&pd_dma0_chan3>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma0_chan5: PD_ASRC_0_TXC {
+								reg = <SC_R_DMA_0_CH5>;
+								power-domains =<&pd_dma0_chan4>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+								pd_asrc0:PD_AUD_ASRC_0 {
+									reg = <SC_R_ASRC_0>;
+									#power-domain-cells = <0>;
+									power-domains =<&pd_dma0_chan5>;
+								};
+							};
+							};
+							};
+							};
+							};
+							};
+
+							pd_dma1_chan0: PD_ASRC_1_RXA {
+								reg = <SC_R_DMA_1_CH0>;
+								power-domains =<&pd_audio_clk1>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma1_chan1: PD_ASRC_1_RXB {
+								reg = <SC_R_DMA_1_CH1>;
+								power-domains =<&pd_dma1_chan0>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma1_chan2: PD_ASRC_1_RXC {
+								reg = <SC_R_DMA_1_CH2>;
+								power-domains =<&pd_dma1_chan1>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma1_chan3: PD_ASRC_1_TXA {
+								reg = <SC_R_DMA_1_CH3>;
+								power-domains =<&pd_dma1_chan2>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma1_chan4: PD_ASRC_1_TXB {
+								reg = <SC_R_DMA_1_CH4>;
+								power-domains =<&pd_dma1_chan3>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma1_chan5: PD_ASRC_1_TXC {
+								reg = <SC_R_DMA_1_CH5>;
+								power-domains =<&pd_dma1_chan4>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+								pd_asrc1: PD_AUD_ASRC_1 {
+									reg = <SC_R_ASRC_1>;
+									#power-domain-cells = <0>;
+									power-domains =<&pd_dma1_chan5>;
+
+								};
+							};
+							};
+							};
+							};
+							};
+							};
+							pd_dma0_chan6: PD_ESAI_0_RX {
+								reg = <SC_R_DMA_0_CH6>;
+								power-domains =<&pd_audio_clk1>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma0_chan7: PD_ESAI_0_TX {
+								reg = <SC_R_DMA_0_CH7>;
+								power-domains =<&pd_dma0_chan6>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+								pd_esai0: PD_AUD_ESAI_0 {
+									reg = <SC_R_ESAI_0>;
+									#power-domain-cells = <0>;
+									power-domains =<&pd_dma0_chan7>;
+								};
+							};
+							};
+							pd_dma0_chan8: PD_SPDIF_0_RX {
+								reg = <SC_R_DMA_0_CH8>;
+								power-domains =<&pd_audio_clk1>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma0_chan9: PD_SPDIF_0_TX {
+								reg = <SC_R_DMA_0_CH9>;
+								power-domains =<&pd_dma0_chan8>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+								pd_spdif0: PD_AUD_SPDIF_0 {
+									reg = <SC_R_SPDIF_0>;
+									#power-domain-cells = <0>;
+									power-domains =<&pd_dma0_chan9>;
+
+								};
+							};
+							};
+							pd_dma0_chan12: PD_SAI_0_RX {
+								reg = <SC_R_DMA_0_CH12>;
+								power-domains =<&pd_audio_clk1>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma0_chan13: PD_SAI_0_TX {
+								reg = <SC_R_DMA_0_CH13>;
+								power-domains =<&pd_dma0_chan12>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+								pd_sai0:PD_AUD_SAI_0 {
+									reg = <SC_R_SAI_0>;
+									#power-domain-cells = <0>;
+									power-domains =<&pd_dma0_chan13>;
+								};
+							};
+
+							};
+							pd_dma0_chan14: PD_SAI_1_RX {
+								reg = <SC_R_DMA_0_CH14>;
+								power-domains =<&pd_audio_clk1>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma0_chan15: PD_SAI_1_TX {
+								reg = <SC_R_DMA_0_CH15>;
+								power-domains =<&pd_dma0_chan14>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+								pd_sai1: PD_AUD_SAI_1 {
+									reg = <SC_R_SAI_1>;
+									#power-domain-cells = <0>;
+									power-domains =<&pd_dma0_chan15>;
+								};
+							};
+							};
+							pd_dma0_chan16: PD_SAI_2_RX {
+								reg = <SC_R_DMA_0_CH16>;
+								power-domains =<&pd_audio_clk1>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+								pd_sai2: PD_AUD_SAI_2 {
+									reg = <SC_R_SAI_2>;
+									#power-domain-cells = <0>;
+									power-domains =<&pd_dma0_chan16>;
+								};
+							};
+							pd_dma0_chan17: PD_SAI_3_RX {
+								reg = <SC_R_DMA_0_CH17>;
+								power-domains =<&pd_audio_clk1>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+								pd_sai3: PD_AUD_SAI_3 {
+									reg = <SC_R_SAI_3>;
+									#power-domain-cells = <0>;
+									power-domains =<&pd_dma0_chan17>;
+								};
+							};
+							pd_dma1_chan8: PD_SAI_4_RX {
+								reg = <SC_R_DMA_1_CH8>;
+								power-domains =<&pd_audio_clk1>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma1_chan9: PD_SAI_4_TX {
+								reg = <SC_R_DMA_1_CH9>;
+								power-domains =<&pd_dma1_chan8>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+								pd_sai4: PD_AUD_SAI_4 {
+									reg = <SC_R_SAI_4>;
+									#power-domain-cells = <0>;
+									power-domains =<&pd_dma1_chan9>;
+
+								};
+							};
+							};
+							pd_dma1_chan10: PD_SAI_5_TX {
+								reg = <SC_R_DMA_1_CH10>;
+								power-domains =<&pd_audio_clk1>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+								pd_sai5: PD_AUD_SAI_5 {
+									reg = <SC_R_SAI_5>;
+									#power-domain-cells = <0>;
+									power-domains =<&pd_dma1_chan10>;
+								};
+							};
+							pd_gpt5: PD_AUD_GPT_5 {
+								reg = <SC_R_GPT_5>;
+								#power-domain-cells = <0>;
+								power-domains =<&pd_audio_clk1>;
+							};
+							pd_gpt6: PD_AUD_GPT_6 {
+								reg = <SC_R_GPT_6>;
+								#power-domain-cells = <0>;
+								power-domains =<&pd_audio_clk1>;
+							};
+							pd_gpt7: PD_AUD_GPT_7 {
+								reg = <SC_R_GPT_7>;
+								#power-domain-cells = <0>;
+								power-domains =<&pd_audio_clk1>;
+							};
+							pd_gpt8: PD_AUD_GPT_8 {
+								reg = <SC_R_GPT_8>;
+								#power-domain-cells = <0>;
+								power-domains =<&pd_audio_clk1>;
+							};
+							pd_gpt9: PD_AUD_GPT_9 {
+								reg = <SC_R_GPT_9>;
+								#power-domain-cells = <0>;
+								power-domains =<&pd_audio_clk1>;
+							};
+							pd_gpt10: PD_AUD_GPT_10 {
+								reg = <SC_R_GPT_10>;
+								#power-domain-cells = <0>;
+								power-domains =<&pd_audio_clk1>;
+							};
+							pd_amix: PD_AUD_AMIX {
+								reg = <SC_R_AMIX>;
+								#power-domain-cells = <0>;
+								power-domains =<&pd_audio_clk1>;
+							};
+							pd_mqs0: PD_AUD_MQS_0 {
+								reg = <SC_R_MQS_0>;
+								#power-domain-cells = <0>;
+								power-domains =<&pd_audio_clk1>;
+							};
+							pd_mclk_out0: PD_AUD_MCLK_OUT_0 {
+								reg = <SC_R_MCLK_OUT_0>;
+								#power-domain-cells = <0>;
+								power-domains =<&pd_audio_clk1>;
+							};
+							pd_mclk_out1: PD_AUD_MCLK_OUT_1 {
+								reg = <SC_R_MCLK_OUT_1>;
+								#power-domain-cells = <0>;
+								power-domains =<&pd_audio_clk1>;
+							};
+						};
+					};
+				};
+			};
+
+			pd_dsp_mu_A: PD_DSP_MU_A {
+				reg = <SC_R_MU_13A>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_audio>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_dsp_mu_B: PD_DSP_MU_B {
+					reg = <SC_R_MU_13B>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_dsp_mu_A>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_dsp_ram: PD_AUD_OCRAM {
+						reg = <SC_R_DSP_RAM>;
+						#power-domain-cells = <0>;
+						power-domains =<&pd_dsp_mu_B>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+						pd_dsp: PD_AUD_DSP {
+							reg = <SC_R_DSP>;
+							#power-domain-cells = <0>;
+							power-domains =<&pd_dsp_ram>;
+						};
+					};
+				};
 			};
 		};
 
@@ -219,6 +870,57 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
+			pd_dma_elcdif_pll: PD_DMA_ELCDIF_PLL {
+				reg = <SC_R_ELCDIF_PLL>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_dma_lcd0: PD_DMA_LCD_0 {
+					reg = <SC_R_LCD_0>;
+					#power-domain-cells = <0>;
+					power-domains = <&pd_dma_elcdif_pll>;
+				};
+			};
+			pd_dma_flexcan0: PD_DMA_CAN_0 {
+				reg = <SC_R_CAN_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+				wakeup-irq = <235>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_dma_flexcan1: PD_DMA_CAN_1 {
+					reg = <SC_R_CAN_1>;
+					#power-domain-cells = <0>;
+					power-domains = <&pd_dma_flexcan0>;
+					wakeup-irq = <236>;
+				};
+
+				pd_dma_flexcan2: PD_DMA_CAN_2 {
+					reg = <SC_R_CAN_2>;
+					#power-domain-cells = <0>;
+					power-domains = <&pd_dma_flexcan0>;
+					wakeup-irq = <237>;
+				};
+			};
+
+			pd_dma_ftm0: PD_DMA_FTM_0 {
+				reg = <SC_R_FTM_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_ftm1: PD_DMA_FTM_1 {
+				reg = <SC_R_FTM_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_adc0: PD_DMA_ADC_0 {
+				reg = <SC_R_ADC_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
 			pd_dma_lpi2c0: PD_DMA_I2C_0 {
 				reg = <SC_R_I2C_0>;
 				#power-domain-cells = <0>;
@@ -243,26 +945,1457 @@
 				reg = <SC_R_UART_0>;
 				#power-domain-cells = <0>;
 				power-domains = <&pd_dma>;
-				wakeup-irq = <225>;
+				wakeup-irq = <345>;
 			};
 			pd_dma_lpuart1: PD_DMA_UART1 {
 				reg = <SC_R_UART_1>;
 				#power-domain-cells = <0>;
 				power-domains = <&pd_dma>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				wakeup-irq = <346>;
+
+				pd_dma2_chan10: PD_UART1_RX {
+					reg = <SC_R_DMA_2_CH10>;
+					power-domains =<&pd_dma_lpuart1>;
+					#power-domain-cells = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_dma2_chan11: PD_UART1_TX {
+						reg = <SC_R_DMA_2_CH11>;
+						power-domains =<&pd_dma2_chan10>;
+						#power-domain-cells = <0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+					};
+				};
 			};
 			pd_dma_lpuart2: PD_DMA_UART2 {
 				reg = <SC_R_UART_2>;
 				#power-domain-cells = <0>;
 				power-domains = <&pd_dma>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				wakeup-irq = <347>;
+
+				pd_dma2_chan12: PD_UART2_RX {
+					reg = <SC_R_DMA_2_CH12>;
+					power-domains =<&pd_dma_lpuart2>;
+					#power-domain-cells = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_dma2_chan13: PD_UART2_TX {
+						reg = <SC_R_DMA_2_CH13>;
+						power-domains =<&pd_dma2_chan12>;
+						#power-domain-cells = <0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+					};
+				};
 			};
 			pd_dma_lpuart3: PD_DMA_UART3 {
 				reg = <SC_R_UART_3>;
 				#power-domain-cells = <0>;
 				power-domains = <&pd_dma>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				wakeup-irq = <348>;
+
+				pd_dma3_chan14: PD_UART3_RX {
+					reg = <SC_R_DMA_2_CH14>;
+					power-domains =<&pd_dma_lpuart3>;
+					#power-domain-cells = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_dma3_chan15: PD_UART3_TX {
+						reg = <SC_R_DMA_2_CH15>;
+						power-domains =<&pd_dma3_chan14>;
+						#power-domain-cells = <0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+					};
+				};
+			};
+			pd_dma_lpspi0: PD_DMA_SPI_0 {
+				reg = <SC_R_SPI_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpspi1: PD_DMA_SPI_1 {
+				reg = <SC_R_SPI_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpspi2: PD_DMA_SPI_2 {
+				reg = <SC_R_SPI_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpspi3: PD_DMA_SPI_3 {
+				reg = <SC_R_SPI_3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_pwm0: PD_DMA_PWM_0 {
+				reg = <SC_R_LCD_0_PWM_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+		};
+
+		pd_gpu: gpu-power-domain {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_NONE>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_gpu0: gpu0 {
+				name = "gpu0";
+				reg = <SC_R_GPU_0_PID0>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_gpu>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+
+		pd_vpu: vpu-power-domain {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_VPU>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_vpu_mu_enc: VPU_ENC_MU {
+				reg = <SC_R_VPU_MU_1>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_vpu>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_vpu_enc: VPU_ENC {
+					reg = <SC_R_VPU_ENC_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_vpu_mu_enc>;
+				};
+			};
+
+			pd_vpu_mu_dec: VPU_DEC_MU {
+				reg = <SC_R_VPU_MU_0>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_vpu>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_vpu_dec: VPU_DEC {
+					reg = <SC_R_VPU_DEC_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_vpu_mu_dec>;
+				};
+			};
+		};
+
+		pd_hsio: hsio-power-domain {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_NONE>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_hsio_gpio: PD_HSIO_GPIO {
+				reg = <SC_R_HSIO_GPIO>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_hsio>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_serdes1: PD_HSIO_SERDES_1 {
+					reg = <SC_R_SERDES_1>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_hsio_gpio>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_pcie: PD_HSIO_PCIE_B {
+						reg = <SC_R_PCIE_B>;
+						#power-domain-cells = <0>;
+						power-domains =<&pd_serdes1>;
+					};
+				};
+			};
+		};
+
+		pd_cm40: PD_CM40 {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_NONE>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_cm40_i2c: PD_CM40_I2C {
+				reg = <SC_R_M4_0_I2C>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_cm40>;
+			};
+
+			pd_cm40_intmux: PD_CM40_INTMUX {
+				reg = <SC_R_M4_0_INTMUX>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_cm40>;
+			};
+		};
+
+
+		pd_dc0: PD_DC_0 {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_DC_0>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_dc0_pll0: PD_DC_0_PLL_0{
+				reg = <SC_R_DC_0_PLL_0>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_dc0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_dc0_pll1: PD_DC_0_PLL_1{
+					reg = <SC_R_DC_0_PLL_1>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_dc0_pll0>;
+				};
+			};
+			pd_mipi_dsi0: PD_MIPI_0_DSI {
+				reg = <SC_R_MIPI_0>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_dc0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_mipi_dsi_0_lvds: PD_LVDS0 {
+					reg = <SC_R_LVDS_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi_dsi0>;
+				};
+
+				pd_mipi_dsi_0_aux_lvds: PD_AUX_LVDS0 {
+					reg = <SC_R_LVDS_0>;
+					#power-domain-cells = <0>;
+					power-domains = <&pd_mipi_dsi0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_mipi_dsi_1_dual_lvds: PD_DUAL_LVDS1 {
+						reg = <SC_R_LVDS_1>;
+						#power-domain-cells = <0>;
+						power-domains = <&pd_mipi_dsi_0_aux_lvds>;
+					};
+				};
+
+				pd_mipi_dsi_0_i2c0: PD_MIPI_0_DSI_I2C0 {
+					reg = <SC_R_MIPI_0_I2C_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi_dsi0>;
+				};
+				pd_mipi_dsi_0_i2c1: PD_MIPI_0_DSI_I2C1 {
+					reg = <SC_R_MIPI_0_I2C_1>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi_dsi0>;
+				};
+				pd_mipi_0_pwm0: PD_MIPI_0_DSI_PWM0 {
+					reg = <SC_R_MIPI_0_PWM_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi_dsi0>;
+				};
+			};
+
+			pd_mipi_dsi1: PD_MIPI_1_DSI {
+				reg = <SC_R_MIPI_1>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_dc0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_mipi_dsi_1_lvds: PD_LVDS1 {
+					reg = <SC_R_LVDS_1>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi_dsi1>;
+				};
+
+				pd_mipi_dsi_1_aux_lvds: PD_AUX_LVDS1 {
+					reg = <SC_R_LVDS_1>;
+					#power-domain-cells = <0>;
+					power-domains = <&pd_mipi_dsi1>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_mipi_dsi_0_dual_lvds: PD_DUAL_LVDS0 {
+						reg = <SC_R_LVDS_0>;
+						#power-domain-cells = <0>;
+						power-domains = <&pd_mipi_dsi_1_aux_lvds>;
+					};
+				};
+
+				pd_mipi_dsi_1_i2c0: PD_MIPI_1_DSI_I2C0 {
+					reg = <SC_R_MIPI_1_I2C_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi_dsi1>;
+				};
+				pd_mipi_dsi_1_i2c1: PD_MIPI_1_DSI_I2C1 {
+					reg = <SC_R_MIPI_1_I2C_1>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi_dsi1>;
+				};
+				pd_mipi_1_pwm0: PD_MIPI_1_DSI_PWM0 {
+					reg = <SC_R_MIPI_1_PWM_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi_dsi1>;
+				};
+			};
+		};
+
+		pd_isi_ch0: PD_IMAGING {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_ISI_CH0>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_mipi_csi: PD_MIPI_CSI0 {
+				reg = <SC_R_CSI_0>;
+				#power-domain-cells = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains =<&pd_isi_ch0>;
+
+				pd_mipi_csi_i2c0: PD_MIPI_CSI0_I2C0 {
+					reg = <SC_R_CSI_0_I2C_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi_csi>;
+				};
+
+				pd_mipi_csi_pwm0: PD_MIPI_CSI0_PWM {
+					name = "mipi_csi0_pwm";
+					reg = <SC_R_CSI_0_PWM_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi_csi>;
+				};
+			};
+
+			pd_parallel_csi: PD_PARALLEL_CSI {
+				reg = <SC_R_PI_0>;
+				#power-domain-cells = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains =<&pd_isi_ch0>;
+
+				pd_parallel_csi_i2c0: PD_PARALLEL_CSI_I2C {
+					name = "parallel_csi_i2c";
+					reg = <SC_R_PI_0_I2C_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_parallel_csi>;
+				};
+
+				pd_parallel_csi_pwm0: PD_PARALLEL_CSI_PWM {
+					name = "parallel_csi_pwm";
+					reg = <SC_R_PI_0_PWM_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_parallel_csi>;
+				};
+
+				pd_parallel_csi_pll: PD_PARALLEL_CSI_PLL {
+					name = "parallel_csi_pll";
+					reg = <SC_R_PI_0_PLL>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_parallel_csi>;
+				};
+			};
+
+			pd_isi_ch1: PD_IMAGING_PDMA1 {
+				reg = <SC_R_ISI_CH1>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_isi_ch0>;
+			};
+
+			pd_isi_ch2: PD_IMAGING_PDMA2 {
+				reg = <SC_R_ISI_CH2>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_isi_ch0>;
+			};
+
+			pd_isi_ch3: PD_IMAGING_PDMA3 {
+				reg = <SC_R_ISI_CH3>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_isi_ch0>;
+			};
+
+			pd_isi_ch4: PD_IMAGING_PDMA4 {
+				reg = <SC_R_ISI_CH4>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_isi_ch0>;
+			};
+
+			pd_isi_ch5: PD_IMAGING_PDMA5 {
+				reg = <SC_R_ISI_CH5>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_isi_ch0>;
+			};
+
+			pd_isi_ch6: PD_IMAGING_PDMA6 {
+				reg = <SC_R_ISI_CH6>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_isi_ch0>;
+			};
+
+			pd_isi_ch7: PD_IMAGING_PDMA7 {
+				reg = <SC_R_ISI_CH7>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_isi_ch0>;
+			};
+
+			pd_jpeg_dec_mp: PD_JPEG_DEC_MP{
+				reg = <SC_R_MJPEG_DEC_MP>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_isi_ch0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_jpgdec: PD_IMAGING_JPEG_DEC {
+					reg = <SC_R_MJPEG_DEC_S0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_jpeg_dec_mp>;
+				};
+			};
+
+			pd_jpeg_enc_mp: PD_JPEG_ENC_MP{
+				reg = <SC_R_MJPEG_ENC_MP>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_isi_ch0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_jpgenc: PD_IMAGING_JPEG_ENC {
+					reg = <SC_R_MJPEG_ENC_S0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_jpeg_enc_mp>;
+				};
+			};
+		};
+		pd_caam: PD_CAAM {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_NONE>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_caam_jr1: PD_CAAM_JR1 {
+				reg = <SC_R_CAAM_JR1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_caam>;
+			};
+			pd_caam_jr2: PD_CAAM_JR2 {
+				reg = <SC_R_CAAM_JR2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_caam>;
+			};
+			pd_caam_jr3: PD_CAAM_JR3 {
+				reg = <SC_R_CAAM_JR3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_caam>;
+			};
+		};
+	};
+
+	tsens: thermal-sensor {
+		compatible = "nxp,imx8qxp-sc-tsens";
+		u-boot,dm-pre-reloc;
+		/* number of the temp sensor on the chip */
+		tsens-num = <2>;
+		#thermal-sensor-cells = <1>;
+	};
+
+	thermal_zones: thermal-zones {
+		/* cpu thermal */
+		cpu-thermal0 {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			/*the slope and offset of the temp sensor */
+			thermal-sensors = <&tsens 0>;
+			trips {
+				cpu_alert0: trip0 {
+					temperature = <107000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit0: trip1 {
+					temperature = <127000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert0>;
+					cooling-device =
+					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		drc-thermal0 {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			thermal-sensors = <&tsens 1>;
+			status = "disabled";
+			trips {
+				drc_alert0: trip0 {
+					temperature = <107000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				drc_crit0: trip1 {
+					temperature = <127000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
+	irqsteer_csi: irqsteer@58220000 {
+		compatible = "nxp,imx-irqsteer";
+		reg = <0x0 0x58220000 0x0 0x1000>;
+		interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#interrupt-cells = <2>;
+		clocks = <&clk IMX8QXP_CLK_DUMMY>;
+		clock-names = "ipg";
+		power-domains = <&pd_mipi_csi>;
+	};
+
+	i2c0_csi0: i2c@58226000 {
+		compatible = "fsl,imx8qm-lpi2c";
+		reg = <0x0 0x58226000 0x0 0x1000>;
+		interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&irqsteer_csi>;
+		clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>,
+			<&clk IMX8QXP_CSI0_I2C0_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_mipi_csi_i2c0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	intmux_cm40: intmux@37400000 {
+		compatible = "nxp,imx-intmux";
+		reg = <0x0 0x37400000 0x0 0x1000>;
+		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#interrupt-cells = <2>;
+		clocks = <&clk IMX8QXP_CM40_IPG_CLK>;
+		clock-names = "ipg";
+		power-domains = <&pd_cm40_intmux>;
+		status = "disabled";
+	};
+
+	i2c0_cm40: i2c@37230000 {
+		compatible = "fsl,imx8qm-lpi2c";
+		reg = <0x0 0x37230000 0x0 0x1000>;
+		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&intmux_cm40>;
+		clocks = <&clk IMX8QXP_CM40_I2C_CLK>,
+			<&clk IMX8QXP_CM40_I2C_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_CM40_I2C_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_cm40_i2c>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	dpu_intsteer: dpu_intsteer@56000000 {
+		compatible = "fsl,imx8qxp-dpu-intsteer", "syscon";
+		reg = <0x0 0x56000000 0x0 0x10000>;
+	};
+
+	pixel_combiner: pixel-combiner@56020000 {
+		compatible = "fsl,imx8qxp-pixel-combiner";
+		reg = <0x0 0x56020000 0x0 0x10000>;
+		power-domains = <&pd_dc0>;
+		status = "disabled";
+	};
+
+	prg1: prg@56040000 {
+		compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+		reg = <0x0 0x56040000 0x0 0x10000>;
+		clocks = <&clk IMX8QXP_DC0_PRG0_APB_CLK>,
+			 <&clk IMX8QXP_DC0_PRG0_RTRAM_CLK>;
+		clock-names = "apb", "rtram";
+		power-domains = <&pd_dc0>;
+		status = "disabled";
+	};
+
+	prg2: prg@56050000 {
+		compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+		reg = <0x0 0x56050000 0x0 0x10000>;
+		clocks = <&clk IMX8QXP_DC0_PRG1_APB_CLK>,
+			 <&clk IMX8QXP_DC0_PRG1_RTRAM_CLK>;
+		clock-names = "apb", "rtram";
+		power-domains = <&pd_dc0>;
+		status = "disabled";
+	};
+
+	prg3: prg@56060000 {
+		compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+		reg = <0x0 0x56060000 0x0 0x10000>;
+		clocks = <&clk IMX8QXP_DC0_PRG2_APB_CLK>,
+			 <&clk IMX8QXP_DC0_PRG2_RTRAM_CLK>;
+		clock-names = "apb", "rtram";
+		power-domains = <&pd_dc0>;
+		status = "disabled";
+	};
+
+	prg4: prg@56070000 {
+		compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+		reg = <0x0 0x56070000 0x0 0x10000>;
+		clocks = <&clk IMX8QXP_DC0_PRG3_APB_CLK>,
+			 <&clk IMX8QXP_DC0_PRG3_RTRAM_CLK>;
+		clock-names = "apb", "rtram";
+		power-domains = <&pd_dc0>;
+		status = "disabled";
+	};
+
+	prg5: prg@56080000 {
+		compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+		reg = <0x0 0x56080000 0x0 0x10000>;
+		clocks = <&clk IMX8QXP_DC0_PRG4_APB_CLK>,
+			 <&clk IMX8QXP_DC0_PRG4_RTRAM_CLK>;
+		clock-names = "apb", "rtram";
+		power-domains = <&pd_dc0>;
+		status = "disabled";
+	};
+
+	prg6: prg@56090000 {
+		compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+		reg = <0x0 0x56090000 0x0 0x10000>;
+		clocks = <&clk IMX8QXP_DC0_PRG5_APB_CLK>,
+			 <&clk IMX8QXP_DC0_PRG5_RTRAM_CLK>;
+		clock-names = "apb", "rtram";
+		power-domains = <&pd_dc0>;
+		status = "disabled";
+	};
+
+	prg7: prg@560a0000 {
+		compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+		reg = <0x0 0x560a0000 0x0 0x10000>;
+		clocks = <&clk IMX8QXP_DC0_PRG6_APB_CLK>,
+			 <&clk IMX8QXP_DC0_PRG6_RTRAM_CLK>;
+		clock-names = "apb", "rtram";
+		power-domains = <&pd_dc0>;
+		status = "disabled";
+	};
+
+	prg8: prg@560b0000 {
+		compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+		reg = <0x0 0x560b0000 0x0 0x10000>;
+		clocks = <&clk IMX8QXP_DC0_PRG7_APB_CLK>,
+			 <&clk IMX8QXP_DC0_PRG7_RTRAM_CLK>;
+		clock-names = "apb", "rtram";
+		power-domains = <&pd_dc0>;
+		status = "disabled";
+	};
+
+	prg9: prg@560c0000 {
+		compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
+		reg = <0x0 0x560c0000 0x0 0x10000>;
+		clocks = <&clk IMX8QXP_DC0_PRG8_APB_CLK>,
+			 <&clk IMX8QXP_DC0_PRG8_RTRAM_CLK>;
+		clock-names = "apb", "rtram";
+		power-domains = <&pd_dc0>;
+		status = "disabled";
+	};
+
+	dpr1_channel1: dpr-channel@560d0000 {
+		compatible = "fsl,imx8qxp-dpr-channel",
+			     "fsl,imx8qm-dpr-channel";
+		reg = <0x0 0x560d0000 0x0 0x10000>;
+		fsl,sc-resource = <SC_R_DC_0_BLIT0>;
+		fsl,prgs = <&prg1>;
+		clocks = <&clk IMX8QXP_DC0_DPR0_APB_CLK>,
+			 <&clk IMX8QXP_DC0_DPR0_B_CLK>,
+			 <&clk IMX8QXP_DC0_RTRAM0_CLK>;
+		clock-names = "apb", "b", "rtram";
+		power-domains = <&pd_dc0>;
+		status = "disabled";
+	};
+
+	dpr1_channel2: dpr-channel@560e0000 {
+		compatible = "fsl,imx8qxp-dpr-channel",
+			     "fsl,imx8qm-dpr-channel";
+		reg = <0x0 0x560e0000 0x0 0x10000>;
+		fsl,sc-resource = <SC_R_DC_0_BLIT1>;
+		fsl,prgs = <&prg2>, <&prg1>;
+		clocks = <&clk IMX8QXP_DC0_DPR0_APB_CLK>,
+			 <&clk IMX8QXP_DC0_DPR0_B_CLK>,
+			 <&clk IMX8QXP_DC0_RTRAM0_CLK>;
+		clock-names = "apb", "b", "rtram";
+		power-domains = <&pd_dc0>;
+		status = "disabled";
+	};
+
+	dpr1_channel3: dpr-channel@560f0000 {
+		compatible = "fsl,imx8qxp-dpr-channel",
+			     "fsl,imx8qm-dpr-channel";
+		reg = <0x0 0x560f0000 0x0 0x10000>;
+		fsl,sc-resource = <SC_R_DC_0_FRAC0>;
+		fsl,prgs = <&prg3>;
+		clocks = <&clk IMX8QXP_DC0_DPR0_APB_CLK>,
+			 <&clk IMX8QXP_DC0_DPR0_B_CLK>,
+			 <&clk IMX8QXP_DC0_RTRAM0_CLK>;
+		clock-names = "apb", "b", "rtram";
+		power-domains = <&pd_dc0>;
+		status = "disabled";
+	};
+
+	dpr2_channel1: dpr-channel@56100000 {
+		compatible = "fsl,imx8qxp-dpr-channel",
+			     "fsl,imx8qm-dpr-channel";
+		reg = <0x0 0x56100000 0x0 0x10000>;
+		fsl,sc-resource = <SC_R_DC_0_VIDEO0>;
+		fsl,prgs = <&prg4>, <&prg5>;
+		clocks = <&clk IMX8QXP_DC0_DPR1_APB_CLK>,
+			 <&clk IMX8QXP_DC0_DPR1_B_CLK>,
+			 <&clk IMX8QXP_DC0_RTRAM1_CLK>;
+		clock-names = "apb", "b", "rtram";
+		power-domains = <&pd_dc0>;
+		status = "disabled";
+	};
+
+	dpr2_channel2: dpr-channel@56110000 {
+		compatible = "fsl,imx8qxp-dpr-channel",
+			     "fsl,imx8qm-dpr-channel";
+		reg = <0x0 0x56110000 0x0 0x10000>;
+		fsl,sc-resource = <SC_R_DC_0_VIDEO1>;
+		fsl,prgs = <&prg6>, <&prg7>;
+		clocks = <&clk IMX8QXP_DC0_DPR1_APB_CLK>,
+			 <&clk IMX8QXP_DC0_DPR1_B_CLK>,
+			 <&clk IMX8QXP_DC0_RTRAM1_CLK>;
+		clock-names = "apb", "b", "rtram";
+		power-domains = <&pd_dc0>;
+		status = "disabled";
+	};
+
+	dpr2_channel3: dpr-channel@56120000 {
+		compatible = "fsl,imx8qxp-dpr-channel",
+			     "fsl,imx8qm-dpr-channel";
+		reg = <0x0 0x56120000 0x0 0x10000>;
+		fsl,sc-resource = <SC_R_DC_0_WARP>;
+		fsl,prgs = <&prg8>, <&prg9>;
+		clocks = <&clk IMX8QXP_DC0_DPR1_APB_CLK>,
+			 <&clk IMX8QXP_DC0_DPR1_B_CLK>,
+			 <&clk IMX8QXP_DC0_RTRAM1_CLK>;
+		clock-names = "apb", "b", "rtram";
+		power-domains = <&pd_dc0>;
+		status = "disabled";
+	};
+
+	dpu1: dpu@56180000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx8qxp-dpu", "fsl,imx8qm-dpu";
+		reg = <0x0 0x56180000 0x0 0x40000>;
+		intsteer = <&dpu_intsteer>;
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "irq_common",
+				  "irq_stream0a",
+				  "irq_stream0b",	/* to M4? */
+				  "irq_stream1a",
+				  "irq_stream1b",	/* to M4? */
+				  "irq_reserved0",
+				  "irq_reserved1",
+				  "irq_blit",
+				  "irq_dpr0",
+				  "irq_dpr1";
+		clocks = <&clk IMX8QXP_DC0_PLL0_CLK>,
+			 <&clk IMX8QXP_DC0_PLL1_CLK>,
+			 <&clk IMX8QXP_DC0_DISP0_CLK>,
+			 <&clk IMX8QXP_DC0_DISP1_CLK>;
+		clock-names = "pll0", "pll1", "disp0", "disp1";
+		power-domains = <&pd_dc0_pll1>;
+		fsl,dpr-channels = <&dpr1_channel1>, <&dpr1_channel2>,
+				   <&dpr1_channel3>, <&dpr2_channel1>,
+				   <&dpr2_channel2>, <&dpr2_channel3>;
+		fsl,pixel-combiner = <&pixel_combiner>;
+		status = "disabled";
+
+		dpu_disp0: port@0 {
+			reg = <0>;
+
+			dpu_disp0_lvds0_ch0: endpoint@0 {
+				remote-endpoint = <&ldb1_ch0>;
+			};
+
+			dpu_disp0_lvds0_ch1: endpoint@1 {
+				remote-endpoint = <&ldb1_ch1>;
+			};
+
+			dpu_disp0_mipi_dsi: endpoint@2 {
+				remote-endpoint = <&mipi_dsi1_in>;
+			};
+		};
+
+		dpu_disp1: port@1 {
+			reg = <1>;
+
+			dpu_disp1_lvds1_ch0: endpoint@0 {
+				remote-endpoint = <&ldb2_ch0>;
+			};
+
+			dpu_disp1_lvds1_ch1: endpoint@1 {
+				remote-endpoint = <&ldb2_ch1>;
+			};
+
+			dpu_disp1_mipi_dsi: endpoint@2 {
+				remote-endpoint = <&mipi_dsi2_in>;
 			};
 		};
 	};
 
+	irqsteer_mipi_lvds0: irqsteer@56220000 {
+		compatible = "nxp,imx-irqsteer";
+		reg = <0x0 0x56220000 0x0 0x1000>;
+		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#interrupt-cells = <2>;
+		clocks = <&clk IMX8QXP_MIPI0_LIS_IPG_CLK>;
+		clock-names = "ipg";
+		power-domains = <&pd_mipi_dsi0>;
+	};
+
+	adma_lcdif: lcdif@5a180000 {
+		compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif";
+		reg = <0x0 0x5a180000 0x0 0x10000>;
+		clocks = <&clk IMX8QXP_LCD_DIV>,
+			 <&clk IMX8QXP_LCD_PXL_DIV>,
+			 <&clk IMX8QXP_LCD_IPG_CLK>;
+		clock-names = "pix", "disp_axi", "axi";
+		assigned-clocks = <&clk IMX8QXP_LCD_SEL>,
+				  <&clk IMX8QXP_LCD_PXL_SEL>,
+				   <&clk IMX8QXP_ELCDIF_PLL_DIV>;
+		assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL_DIV>,
+					 <&clk IMX8QXP_LCD_PXL_BYPASS_DIV>;
+		assigned-clock-rates = <0>, <0>, <804000000>;
+		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&pd_dma_lcd0>;
+		status = "disabled";
+	};
+
+	pwm_adma_lcdif: pwm@5a190000 {
+		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+		reg = <0x0 0x5a190000 0 0x1000>;
+		clocks = <&clk IMX8QXP_PWM_IPG_CLK>,
+			 <&clk IMX8QXP_PWM_CLK>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX8QXP_PWM_CLK>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <2>;
+		power-domains = <&pd_dma_pwm0>;
+		status = "disabled";
+	};
+
+	mipi_dsi_csr1: csr@56221000 {
+		compatible = "fsl,imx8qxp-mipi-dsi-csr", "syscon";
+		reg = <0x0 0x56221000 0x0 0x1000>;
+	};
+
+	mipi_dsi_phy1: dsi_phy@56228300 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "mixel,imx8qxp-mipi-dsi-phy";
+		reg = <0x0 0x56228300 0x0 0x100>;
+		#phy-cells = <0>;
+		status = "disabled";
+	};
+
+	mipi_dsi_bridge1: mipi_dsi_bridge@56228000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nwl,mipi-dsi";
+		reg = <0x0 0x56228000 0x0 0x300>;
+		interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&irqsteer_mipi_lvds0>;
+		clocks =
+			<&clk IMX8QXP_MIPI0_BYPASS_CLK>,
+			<&clk IMX8QXP_MIPI0_DSI_TX_ESC_CLK>,
+			<&clk IMX8QXP_MIPI0_DSI_RX_ESC_CLK>;
+		clock-names = "phy_ref", "tx_esc", "rx_esc";
+		assigned-clocks =
+			<&clk IMX8QXP_MIPI0_DSI_TX_ESC_SEL>,
+			<&clk IMX8QXP_MIPI0_DSI_RX_ESC_SEL>,
+			<&clk IMX8QXP_MIPI0_DSI_TX_ESC_CLK>,
+			<&clk IMX8QXP_MIPI0_DSI_RX_ESC_CLK>;
+		assigned-clock-rates = <0>, <0>, <18000000>, <72000000>;
+		assigned-clock-parents =
+			<&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>,
+			<&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>;
+		power-domains = <&pd_mipi_dsi0>;
+		phys = <&mipi_dsi_phy1>;
+		phy-names = "dphy";
+		status = "disabled";
+
+		port@0 {
+			mipi_dsi_bridge1_in: endpoint {
+				remote-endpoint = <&mipi_dsi1_out>;
+			};
+		};
+	};
+
+	mipi_dsi1: mipi_dsi@56228000 {
+		compatible = "fsl,imx8qxp-mipi-dsi";
+		clocks =
+			<&clk IMX8QXP_MIPI0_PIXEL_CLK>,
+			<&clk IMX8QXP_MIPI0_BYPASS_CLK>,
+			<&clk IMX8QXP_CLK_DUMMY>;
+		clock-names = "pixel", "bypass", "phy_ref";
+		power-domains = <&pd_mipi_dsi0>;
+		csr = <&mipi_dsi_csr1>;
+		phys = <&mipi_dsi_phy1>;
+		phy-names = "dphy";
+		status = "disabled";
+
+		port@0 {
+			mipi_dsi1_in: endpoint {
+				remote-endpoint = <&dpu_disp0_mipi_dsi>;
+			};
+		};
+
+		port@1 {
+			mipi_dsi1_out: endpoint {
+				remote-endpoint = <&mipi_dsi_bridge1_in>;
+			};
+		};
+	};
+
+	lvds_region1: lvds_region@56220000 {
+		compatible = "fsl,imx8qxp-lvds-region", "syscon";
+		reg = <0x0 0x56220000 0x0 0x10000>;
+	};
+
+	ldb1_phy: ldb_phy@56221000 {
+		compatible = "mixel,lvds-combo-phy";
+		reg = <0x0 0x56221000 0x0 0x100>, <0x0 0x56228000 0x0 0x1000>;
+		#phy-cells = <0>;
+		clocks = <&clk IMX8QXP_MIPI0_LVDS_PHY_CLK>;
+		clock-names = "phy";
+		status = "disabled";
+	};
+
+	ldb1: ldb@562210e0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx8qxp-ldb";
+		clocks = <&clk IMX8QXP_MIPI0_LVDS_PIXEL_CLK>,
+			 <&clk IMX8QXP_MIPI0_LVDS_BYPASS_CLK>,
+			 <&clk IMX8QXP_MIPI1_LVDS_PIXEL_CLK>,
+			 <&clk IMX8QXP_MIPI1_LVDS_BYPASS_CLK>;
+		clock-names = "pixel", "bypass", "aux_pixel", "aux_bypass";
+		power-domains = <&pd_mipi_dsi_0_lvds>;
+		gpr = <&lvds_region1>;
+		aux-gpr = <&lvds_region2>;
+		status = "disabled";
+
+		lvds-channel@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			phys = <&ldb1_phy>, <&ldb2_phy>;
+			phy-names = "ldb_phy", "aux_ldb_phy";
+			status = "disabled";
+
+			port@0 {
+				reg = <0>;
+
+				ldb1_ch0: endpoint {
+					remote-endpoint = <&dpu_disp0_lvds0_ch0>;
+				};
+			};
+		};
+
+		lvds-channel@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			phys = <&ldb1_phy>;
+			phy-names = "ldb_phy";
+			status = "disabled";
+
+			port@0 {
+				reg = <0>;
+
+				ldb1_ch1: endpoint {
+					remote-endpoint = <&dpu_disp0_lvds0_ch1>;
+				};
+			};
+		};
+	};
+
+	pwm_mipi_lvds0: pwm@56224000 {
+		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+		reg = <0x0 0x56224000 0 0x1000>;
+		clocks = <&clk IMX8QXP_MIPI0_PWM_IPG_CLK>,
+			 <&clk IMX8QXP_MIPI0_PWM_CLK>,
+			 <&clk IMX8QXP_MIPI0_PWM_32K_CLK>;
+		clock-names = "ipg", "per", "32k";
+		assigned-clocks = <&clk IMX8QXP_MIPI0_PWM_CLK>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <2>;
+		power-domains = <&pd_mipi_0_pwm0>;
+		status = "disabled";
+	};
+
+	i2c0_mipi_lvds0: i2c@56226000 {
+		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c";
+		reg = <0x0 0x56226000 0x0 0x1000>;
+		interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&irqsteer_mipi_lvds0>;
+		clocks = <&clk IMX8QXP_MIPI0_I2C0_CLK>,
+			 <&clk IMX8QXP_MIPI0_I2C0_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_MIPI0_I2C0_DIV>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_mipi_dsi_0_i2c0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	irqsteer_mipi_lvds1: irqsteer@56240000 {
+		compatible = "nxp,imx-irqsteer";
+		reg = <0x0 0x56240000 0x0 0x1000>;
+		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#interrupt-cells = <2>;
+		clocks = <&clk IMX8QXP_MIPI1_LIS_IPG_CLK>;
+		clock-names = "ipg";
+		power-domains = <&pd_mipi_dsi1>;
+	};
+
+	mipi_dsi_csr2: csr@56241000 {
+		compatible = "fsl,imx8qxp-mipi-dsi-csr", "syscon";
+		reg = <0x0 0x56241000 0x0 0x1000>;
+	};
+
+	mipi_dsi_phy2: dsi_phy@56248300 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "mixel,imx8qxp-mipi-dsi-phy";
+		reg = <0x0 0x56248300 0x0 0x100>;
+		#phy-cells = <0>;
+		status = "disabled";
+	};
+
+	mipi_dsi_bridge2: mipi_dsi_bridge@56248000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nwl,mipi-dsi";
+		reg = <0x0 0x56248000 0x0 0x300>;
+		interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&irqsteer_mipi_lvds1>;
+		clocks =
+			<&clk IMX8QXP_MIPI1_BYPASS_CLK>,
+			<&clk IMX8QXP_MIPI1_DSI_TX_ESC_CLK>,
+			<&clk IMX8QXP_MIPI1_DSI_RX_ESC_CLK>;
+		clock-names = "phy_ref", "tx_esc", "rx_esc";
+		assigned-clocks =
+			<&clk IMX8QXP_MIPI1_DSI_TX_ESC_SEL>,
+			<&clk IMX8QXP_MIPI1_DSI_RX_ESC_SEL>,
+			<&clk IMX8QXP_MIPI1_DSI_TX_ESC_CLK>,
+			<&clk IMX8QXP_MIPI1_DSI_RX_ESC_CLK>;
+		assigned-clock-rates = <0>, <0>, <18000000>, <72000000>;
+		assigned-clock-parents =
+			<&clk IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK>,
+			<&clk IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK>;
+		power-domains = <&pd_mipi_dsi1>;
+		phys = <&mipi_dsi_phy2>;
+		phy-names = "dphy";
+		status = "disabled";
+
+		port@0 {
+			mipi_dsi_bridge2_in: endpoint {
+				remote-endpoint = <&mipi_dsi2_out>;
+			};
+		};
+	};
+
+	mipi_dsi2: mipi_dsi@56248000 {
+		compatible = "fsl,imx8qxp-mipi-dsi";
+		clocks =
+			<&clk IMX8QXP_MIPI1_PIXEL_CLK>,
+			<&clk IMX8QXP_MIPI1_BYPASS_CLK>,
+			<&clk IMX8QXP_CLK_DUMMY>;
+		clock-names = "pixel", "bypass", "phy_ref";
+		power-domains = <&pd_mipi_dsi1>;
+		csr = <&mipi_dsi_csr2>;
+		phys = <&mipi_dsi_phy2>;
+		phy-names = "dphy";
+		status = "disabled";
+
+		port@0 {
+			mipi_dsi2_in: endpoint {
+				remote-endpoint = <&dpu_disp1_mipi_dsi>;
+			};
+		};
+
+		port@1 {
+			mipi_dsi2_out: endpoint {
+				remote-endpoint = <&mipi_dsi_bridge2_in>;
+			};
+		};
+	};
+
+	lvds_region2: lvds_region@56240000 {
+		compatible = "fsl,imx8qxp-lvds-region", "syscon";
+		reg = <0x0 0x56240000 0x0 0x10000>;
+	};
+
+	ldb2_phy: ldb_phy@56241000 {
+		compatible = "mixel,lvds-combo-phy";
+		reg = <0x0 0x56241000 0x0 0x100>, <0x0 0x56248000 0x0 0x1000>;
+		#phy-cells = <0>;
+		clocks = <&clk IMX8QXP_MIPI1_LVDS_PHY_CLK>;
+		clock-names = "phy";
+		status = "disabled";
+	};
+
+	ldb2: ldb@562410e0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx8qxp-ldb";
+		clocks = <&clk IMX8QXP_MIPI1_LVDS_PIXEL_CLK>,
+			 <&clk IMX8QXP_MIPI1_LVDS_BYPASS_CLK>,
+			 <&clk IMX8QXP_MIPI0_LVDS_PIXEL_CLK>,
+			 <&clk IMX8QXP_MIPI0_LVDS_BYPASS_CLK>;
+		clock-names = "pixel", "bypass", "aux_pixel", "aux_bypass";
+		power-domains = <&pd_mipi_dsi_1_lvds>;
+		gpr = <&lvds_region2>;
+		aux-gpr = <&lvds_region1>;
+		status = "disabled";
+
+		lvds-channel@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			phys = <&ldb2_phy>, <&ldb1_phy>;
+			phy-names = "ldb_phy", "aux_ldb_phy";
+			status = "disabled";
+
+			port@0 {
+				reg = <0>;
+
+				ldb2_ch0: endpoint {
+					remote-endpoint = <&dpu_disp1_lvds1_ch0>;
+				};
+			};
+		};
+
+		lvds-channel@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			phys = <&ldb2_phy>;
+			phy-names = "ldb_phy";
+			status = "disabled";
+
+			port@0 {
+				reg = <0>;
+
+				ldb2_ch1: endpoint {
+					remote-endpoint = <&dpu_disp1_lvds1_ch1>;
+				};
+			};
+		};
+	};
+
+	cameradev: camera {
+		compatible = "fsl,mxc-md", "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		isi_0: isi@58100000 {
+			compatible = "fsl,imx8-isi";
+			reg = <0x0 0x58100000 0x0 0x10000>;
+			interrupts = <0 297 0>;
+			interface = <2 0 2>;  /* <Input MIPI_VCx Output>
+									Input:  0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM
+									VCx:    0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only
+									Output: 0-DC0, 1-DC1, 2-MEM */
+			clocks = <&clk IMX8QXP_IMG_PDMA_0_CLK>;
+			clock-names = "per";
+			assigned-clocks = <&clk IMX8QXP_IMG_PDMA_0_CLK>;
+			assigned-clock-rates = <600000000>;
+			power-domains =<&pd_isi_ch0>;
+			status = "disabled";
+		};
+
+		isi_1: isi@58110000 {
+			compatible = "fsl,imx8-isi";
+			reg = <0x0 0x58110000 0x0 0x10000>;
+			interrupts = <0 298 0>;
+			interface = <2 1 2>;
+			clocks = <&clk IMX8QXP_IMG_PDMA_1_CLK>;
+			clock-names = "per";
+			assigned-clocks = <&clk IMX8QXP_IMG_PDMA_1_CLK>;
+			assigned-clock-rates = <600000000>;
+			power-domains =<&pd_isi_ch1>;
+			status = "disabled";
+		};
+
+		isi_2: isi@58120000 {
+			compatible = "fsl,imx8-isi";
+			reg = <0x0 0x58120000 0x0 0x10000>;
+			interrupts = <0 299 0>;
+			interface = <2 2 2>;
+			clocks = <&clk IMX8QXP_IMG_PDMA_2_CLK>;
+			clock-names = "per";
+			assigned-clocks = <&clk IMX8QXP_IMG_PDMA_2_CLK>;
+			assigned-clock-rates = <600000000>;
+			power-domains =<&pd_isi_ch2>;
+			status = "disabled";
+		};
+
+		isi_3: isi@58130000 {
+			compatible = "fsl,imx8-isi";
+			reg = <0x0 0x58130000 0x0 0x10000>;
+			interrupts = <0 300 0>;
+			interface = <2 3 2>;
+			clocks = <&clk IMX8QXP_IMG_PDMA_3_CLK>;
+			clock-names = "per";
+			assigned-clocks = <&clk IMX8QXP_IMG_PDMA_3_CLK>;
+			assigned-clock-rates = <600000000>;
+			power-domains =<&pd_isi_ch3>;
+			status = "disabled";
+		};
+
+		isi_4: isi@58140000 {
+			compatible = "fsl,imx8-isi";
+			reg = <0x0 0x58140000 0x0 0x10000>;
+			interrupts = <0 301 0>;
+			interface = <3 0 2>;
+			clocks = <&clk IMX8QXP_IMG_PDMA_4_CLK>;
+			clock-names = "per";
+			assigned-clocks = <&clk IMX8QXP_IMG_PDMA_4_CLK>;
+			assigned-clock-rates = <600000000>;
+			power-domains =<&pd_isi_ch4>;
+			status = "disabled";
+		};
+
+		isi_5: isi@58150000 {
+			compatible = "fsl,imx8-isi";
+			reg = <0x0 0x58150000 0x0 0x10000>;
+			interrupts = <0 302 0>;
+			interface = <3 1 2>;
+			clocks = <&clk IMX8QXP_IMG_PDMA_5_CLK>;
+			clock-names = "per";
+			assigned-clocks = <&clk IMX8QXP_IMG_PDMA_5_CLK>;
+			assigned-clock-rates = <600000000>;
+			power-domains =<&pd_isi_ch5>;
+			status = "disabled";
+		};
+
+		isi_6: isi@58160000 {
+			compatible = "fsl,imx8-isi";
+			reg = <0x0 0x58160000 0x0 0x10000>;
+			interrupts = <0 303 0>;
+			interface = <3 2 2>;
+			clocks = <&clk IMX8QXP_IMG_PDMA_6_CLK>;
+			clock-names = "per";
+			assigned-clocks = <&clk IMX8QXP_IMG_PDMA_6_CLK>;
+			assigned-clock-rates = <600000000>;
+			power-domains =<&pd_isi_ch6>;
+			status = "disabled";
+		};
+
+		isi_7: isi@58170000 {
+			compatible = "fsl,imx8-isi";
+			reg = <0x0 0x58170000 0x0 0x10000>;
+			interrupts = <0 304 0>;
+			interface = <3 3 2>;
+			clocks = <&clk IMX8QXP_IMG_PDMA_7_CLK>;
+			clock-names = "per";
+			assigned-clocks = <&clk IMX8QXP_IMG_PDMA_7_CLK>;
+			assigned-clock-rates = <600000000>;
+			power-domains =<&pd_isi_ch7>;
+			status = "disabled";
+		};
+
+		mipi_csi_0: csi@58227000 {
+			compatible = "fsl,mxc-mipi-csi2";
+			reg = <0x0 0x58227000 0x0 0x1000>, /* CSI0 Controler base addr */
+				<0x0 0x58221000 0x0 0x1000>; /* CSI0 Subsystem CSR base addr  */
+			interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&irqsteer_csi>;
+			clocks = <&clk IMX8QXP_CLK_DUMMY>,
+					<&clk IMX8QXP_CSI0_CORE_CLK>,
+					<&clk IMX8QXP_CSI0_ESC_CLK>,
+					<&clk IMX8QXP_IMG_PXL_LINK_CSI0_CLK>;
+			clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
+			assigned-clocks = <&clk IMX8QXP_CSI0_CORE_CLK>,
+							<&clk IMX8QXP_CSI0_ESC_CLK>;
+			assigned-clock-rates = <360000000>, <72000000>;
+			power-domains = <&pd_mipi_csi>;
+			status = "disabled";
+		};
+
+		parallel_csi: pcsi@58261000 {
+			compatible = "fsl,mxc-parallel-csi";
+			reg = <0x0 0x58261000 0x0 0x1000>;
+			clocks = <&clk IMX8QXP_PARALLEL_CSI_PIXEL_CLK>,
+				   <&clk IMX8QXP_PARALLEL_CSI_IPG_CLK>,
+				   <&clk IMX8QXP_PARALLEL_CSI_CLK_SEL>,
+				   <&clk IMX8QXP_PARALLEL_CSI_PER_CLK_DIV>,
+				   <&clk IMX8QXP_PARALLEL_CSI_CLK_DPLL>;
+			clock-names = "pixel", "ipg", "sel", "div", "dpll";
+			assigned-clocks = <&clk IMX8QXP_PARALLEL_CSI_CLK_SEL>,
+							<&clk IMX8QXP_PARALLEL_CSI_PER_CLK_DIV>;
+			assigned-clock-parents = <&clk IMX8QXP_PARALLEL_CSI_CLK_DPLL>;
+			assigned-clock-rates = <0>, <160000000>;  /* 160MHz */
+			power-domains = <&pd_parallel_csi>;
+			status = "disabled";
+		};
+
+		jpegdec: jpegdec@58400000 {
+			compatible = "fsl,imx8-jpgdec";
+			reg = <0x0 0x58400000 0x0 0x00040020 >;
+			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8QXP_IMG_JPEG_DEC_IPG_CLK >,
+					<&clk IMX8QXP_IMG_JPEG_DEC_CLK >;
+			clock-names = "ipg", "per";
+			assigned-clocks = <&clk IMX8QXP_IMG_JPEG_DEC_IPG_CLK >,
+					<&clk IMX8QXP_IMG_JPEG_DEC_CLK >;
+			assigned-clock-rates = <200000000>;
+			power-domains =<&pd_jpgdec>;
+			status = "okay";
+		};
+
+		jpegenc: jpegenc@58450000 {
+			compatible = "fsl,imx8-jpgenc";
+			reg = <0x0 0x58450000 0x0 0x00240020 >;
+			interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8QXP_IMG_JPEG_ENC_IPG_CLK >,
+					<&clk IMX8QXP_IMG_JPEG_ENC_CLK >;
+			clock-names = "ipg", "per";
+			assigned-clocks = <&clk IMX8QXP_IMG_JPEG_ENC_IPG_CLK >,
+					<&clk IMX8QXP_IMG_JPEG_ENC_CLK >;
+			assigned-clock-rates = <200000000>;
+			power-domains =<&pd_jpgenc>;
+			status = "okay";
+		};
+	};
+
+	i2c_rpbus_1: i2c-rpbus-1 {
+		compatible = "fsl,i2c-rpbus";
+		status = "disabled";
+	};
+
+	i2c_rpbus_5: i2c-rpbus-5 {
+		compatible = "fsl,i2c-rpbus";
+		status = "disabled";
+	};
+
+	i2c_rpbus_12: i2c-rpbus-12 {
+		compatible = "fsl,i2c-rpbus";
+		status = "disabled";
+	};
+
+	i2c_rpbus_13: i2c-rpbus-13 {
+		compatible = "fsl,i2c-rpbus";
+		status = "disabled";
+	};
+
+	i2c_rpbus_14: i2c-rpbus-14 {
+		compatible = "fsl,i2c-rpbus";
+		status = "disabled";
+	};
+
+	i2c_rpbus_15: i2c-rpbus-15 {
+		compatible = "fsl,i2c-rpbus";
+		status = "disabled";
+	};
+
+	pwm_mipi_lvds1: pwm@56244000 {
+		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+		reg = <0x0 0x56244000 0 0x1000>;
+		clocks = <&clk IMX8QXP_MIPI1_PWM_IPG_CLK>,
+			 <&clk IMX8QXP_MIPI1_PWM_CLK>,
+			 <&clk IMX8QXP_MIPI1_PWM_32K_CLK>;
+		clock-names = "ipg", "per", "32k";
+		assigned-clocks = <&clk IMX8QXP_MIPI1_PWM_CLK>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <2>;
+		power-domains = <&pd_mipi_1_pwm0>;
+		status = "disabled";
+	};
+
+	i2c0_mipi_lvds1: i2c@56246000 {
+		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c";
+		reg = <0x0 0x56246000 0x0 0x1000>;
+		interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&irqsteer_mipi_lvds1>;
+		clocks = <&clk IMX8QXP_MIPI1_I2C0_CLK>,
+			 <&clk IMX8QXP_MIPI1_I2C0_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_MIPI1_I2C0_DIV>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_mipi_dsi_1_i2c0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	adc0: adc@5a880000 {
+		compatible = "fsl,imx8qxp-adc";
+		reg = <0x0 0x5a880000 0x0 0x10000>;
+		interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QXP_ADC0_CLK>,
+			 <&clk IMX8QXP_ADC0_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_ADC0_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_dma_adc0>;
+		status = "disabled";
+	};
+
 	i2c0: i2c@5a800000 {
 		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
 		reg = <0x0 0x5a800000 0x0 0x4000>;
@@ -327,13 +2460,168 @@
 		status = "disabled";
 	};
 
+	usbmisc1: usbmisc@5b0d0200 {
+		#index-cells = <1>;
+		compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
+		reg = <0x0 0x5b0d0200 0x0 0x200>;
+	};
+
+	usbphy1: usbphy@0x5b100000 {
+		compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
+		reg = <0x0 0x5b100000 0x0 0x1000>;
+		clocks = <&clk IMX8QXP_USB2_PHY_IPG_CLK>;
+		power-domains = <&pd_conn_usbotg0_phy>;
+	};
+
+	usbotg1: usb@5b0d0000 {
+		compatible = "fsl,imx8qm-usb", "fsl,imx27-usb";
+		reg = <0x0 0x5b0d0000 0x0 0x200>;
+		interrupt-parent = <&wu>;
+		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,usbphy = <&usbphy1>;
+		fsl,usbmisc = <&usbmisc1 0>;
+		clocks = <&clk IMX8QXP_USB2_OH_AHB_CLK>;
+		ahb-burst-config = <0x0>;
+		tx-burst-size-dword = <0x10>;
+		rx-burst-size-dword = <0x10>;
+		#stream-id-cells = <1>;
+		power-domains = <&pd_conn_usbotg0>;
+		status = "disabled";
+	};
+
+	flexcan1: can@5a8d0000 {
+		compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
+		reg = <0x0 0x5a8d0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wu>;
+		clocks = <&clk IMX8QXP_CAN0_IPG_CLK>,
+			 <&clk IMX8QXP_CAN0_CLK>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
+		assigned-clock-rates = <40000000>;
+		power-domains = <&pd_dma_flexcan0>;
+		/* SLSlice[4] */
+		clk-src = <0>;
+		status = "disabled";
+	};
+
+	flexcan2: can@5a8e0000 {
+		compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
+		reg = <0x0 0x5a8e0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wu>;
+		/* CAN0 clock and PD is shared among all CAN instances */
+		clocks = <&clk IMX8QXP_CAN0_IPG_CLK>,
+			 <&clk IMX8QXP_CAN0_CLK>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
+		assigned-clock-rates = <40000000>;
+		power-domains = <&pd_dma_flexcan1>;
+		/* SLSlice[4] */
+		clk-src = <0>;
+		status = "disabled";
+	};
+
+	flexcan3: can@5a8f0000 {
+		compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
+		reg = <0x0 0x5a8f0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wu>;
+		/* CAN0 clock and PD is shared among all CAN instances */
+		clocks = <&clk IMX8QXP_CAN0_IPG_CLK>,
+			 <&clk IMX8QXP_CAN0_CLK>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
+		assigned-clock-rates = <40000000>;
+		power-domains = <&pd_dma_flexcan2>;
+		/* SLSlice[4] */
+		clk-src = <0>;
+		status = "disabled";
+	};
+
+	dma_apbh: dma-apbh@5b810000 {
+		compatible = "fsl,imx28-dma-apbh";
+		reg = <0x0 0x5b810000 0x0 0x2000>;
+		interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+		#dma-cells = <1>;
+		dma-channels = <4>;
+		clocks = <&clk IMX8QXP_APBHDMA_CLK>;
+		power-domains = <&pd_conn_nand>;
+	};
+
+	gpmi: gpmi-nand@5b812000{
+		compatible = "fsl,imx8qxp-gpmi-nand";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x0 0x5b812000 0x0 0x2000>, <0x0 0x5b814000 0x0 0x2000>;
+		reg-names = "gpmi-nand", "bch";
+		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "bch";
+		clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>,
+			<&clk IMX8QXP_GPMI_APB_CLK>,
+			<&clk IMX8QXP_GPMI_BCH_CLK>,
+			<&clk IMX8QXP_GPMI_APB_BCH_CLK>,
+			<&clk IMX8QXP_APBHDMA_CLK>;
+		clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_apb_bch", "gpmi_apbh_dma";
+		dmas = <&dma_apbh 0>;
+		dma-names = "rx-tx";
+		power-domains = <&pd_conn_nand>;
+		assigned-clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>;
+		assigned-clock-rates = <50000000>;
+		status = "disabled";
+	};
+
+	usbphynop1: usbphynop1 {
+		compatible = "usb-nop-xceiv";
+		clocks = <&clk IMX8QXP_USB3_PHY_CLK>;
+		clock-names = "main_clk";
+		power-domains = <&pd_conn_usb2_phy>;
+	};
+
+	usbotg3: usb3@5b110000 {
+		compatible = "Cadence,usb3";
+		reg = <0x0 0x5B110000 0x0 0x10000>,
+			<0x0 0x5B130000 0x0 0x10000>,
+			<0x0 0x5B140000 0x0 0x10000>,
+			<0x0 0x5B160000 0x0 0x40000>,
+			<0x0 0x5B120000 0x0 0x10000>;
+		reg-names = "none-core", "xhci", "dev", "phy", "otg";
+		interrupt-parent = <&wu>;
+		interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_USB3_LPM_CLK>,
+			<&clk IMX8QXP_USB3_BUS_CLK>,
+			<&clk IMX8QXP_USB3_ACLK>,
+			<&clk IMX8QXP_USB3_IPG_CLK>,
+			<&clk IMX8QXP_USB3_CORE_PCLK>;
+		clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk",
+			"usb3_ipg_clk", "usb3_core_pclk";
+		assigned-clocks = <&clk IMX8QXP_USB3_ACLK_DIV>,
+			   <&clk IMX8QXP_USB3_LPM_DIV>,
+			   <&clk IMX8QXP_USB3_BUS_DIV>;
+		assigned-clock-rates = <125000000>, <12000000>, <250000000>;
+		power-domains = <&pd_conn_usb2>;
+		cdns3,usbphy = <&usbphynop1>;
+		status = "disabled";
+	};
+
+	wu: wu {
+		compatible = "fsl,imx8-wu";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		interrupt-parent = <&gic>;
+	};
+
 	gpio0: gpio@5d080000 {
 		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
 		reg = <0x0 0x5d080000 0x0 0x10000>;
 		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 		gpio-controller;
 		#gpio-cells = <2>;
-		power-domains = <&pd_lsio_gpio0>;
+                power-domains = <&pd_lsio_gpio0>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
 	};
@@ -344,7 +2632,7 @@
 		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 		gpio-controller;
 		#gpio-cells = <2>;
-		power-domains = <&pd_lsio_gpio1>;
+                power-domains = <&pd_lsio_gpio1>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
 	};
@@ -355,7 +2643,7 @@
 		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 		gpio-controller;
 		#gpio-cells = <2>;
-		power-domains = <&pd_lsio_gpio2>;
+                power-domains = <&pd_lsio_gpio2>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
 	};
@@ -366,7 +2654,7 @@
 		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 		gpio-controller;
 		#gpio-cells = <2>;
-		power-domains = <&pd_lsio_gpio3>;
+                power-domains = <&pd_lsio_gpio3>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
 	};
@@ -388,7 +2676,7 @@
 		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 		gpio-controller;
 		#gpio-cells = <2>;
-		power-domains = <&pd_lsio_gpio5>;
+                power-domains = <&pd_lsio_gpio5>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
 	};
@@ -399,7 +2687,7 @@
 		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 		gpio-controller;
 		#gpio-cells = <2>;
-		power-domains = <&pd_lsio_gpio6>;
+                power-domains = <&pd_lsio_gpio6>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
 	};
@@ -410,15 +2698,111 @@
 		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 		gpio-controller;
 		#gpio-cells = <2>;
-		power-domains = <&pd_lsio_gpio7>;
+                power-domains = <&pd_lsio_gpio7>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio0_mipi_csi0: gpio@58222000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x58222000 0x0 0x1000>;
+		interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&irqsteer_csi>;
+		gpio-controller;
+		#gpio-cells = <2>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
+		power-domains = <&pd_mipi_csi>;
+	};
+
+	gpu_3d0: gpu@53100000 {
+		compatible = "fsl,imx8-gpu";
+		reg = <0x0 0x53100000 0 0x40000>;
+		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>;
+		clock-names = "core", "shader";
+		assigned-clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>;
+		assigned-clock-rates = <700000000>, <850000000>;
+		power-domains = <&pd_gpu0>;
+		status = "disabled";
+	};
+
+	imx8_gpu_ss: imx8_gpu_ss {
+		compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss";
+		cores = <&gpu_3d0>;
+		reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x10000000>;
+		reg-names = "phys_baseaddr", "contiguous_mem";
+		status = "disabled";
+	};
+
+	ddr_pmu0: ddr_pmu@5c020000 {
+		compatible = "fsl,imx8-ddr-pmu";
+		reg = <0x0 0x5c020000 0x0 0x10000>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	lpspi0: lpspi@5a000000 {
+		compatible = "fsl,imx7ulp-spi";
+		reg = <0x0 0x5a000000 0x0 0x10000>;
+		interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QXP_SPI0_CLK>,
+			 <&clk IMX8QXP_SPI0_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_SPI0_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma_lpspi0>;
+		status = "disabled";
+	};
+
+	lpspi1: lpspi@5a010000 {
+		compatible = "fsl,imx7ulp-spi";
+		reg = <0x0 0x5a010000 0x0 0x10000>;
+		interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QXP_SPI1_CLK>,
+			 <&clk IMX8QXP_SPI1_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_SPI1_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma_lpspi1>;
+		status = "disabled";
+	};
+
+	lpspi2: lpspi@5a020000 {
+		compatible = "fsl,imx7ulp-spi";
+		reg = <0x0 0x5a020000 0x0 0x10000>;
+		interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QXP_SPI2_CLK>,
+			 <&clk IMX8QXP_SPI2_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_SPI2_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma_lpspi2>;
+		status = "disabled";
+	};
+
+	lpspi3: lpspi@5a030000 {
+		compatible = "fsl,imx7ulp-spi";
+		reg = <0x0 0x5a030000 0x0 0x10000>;
+		interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QXP_SPI3_CLK>,
+			 <&clk IMX8QXP_SPI3_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_SPI3_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma_lpspi3>;
+		status = "disabled";
 	};
 
 	lpuart0: serial@5a060000 {
 		compatible = "fsl,imx8qm-lpuart";
 		reg = <0x0 0x5a060000 0x0 0x1000>;
-		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wu>;
 		clocks = <&clk IMX8QXP_UART0_CLK>,
 			 <&clk IMX8QXP_UART0_IPG_CLK>;
 		clock-names = "per", "ipg";
@@ -431,39 +2815,359 @@
 	lpuart1: serial@5a070000 {
 		compatible = "fsl,imx8qm-lpuart";
 		reg = <0x0 0x5a070000 0x0 0x1000>;
-		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wu>;
 		clocks = <&clk IMX8QXP_UART1_CLK>,
-			 <&clk IMX8QXP_UART1_IPG_CLK>;
+			<&clk IMX8QXP_UART1_IPG_CLK>;
 		clock-names = "per", "ipg";
 		assigned-clocks = <&clk IMX8QXP_UART1_CLK>;
 		assigned-clock-rates = <80000000>;
-		power-domains = <&pd_dma_lpuart1>;
+		power-domains = <&pd_dma2_chan11>;
+		dma-names = "tx","rx";
+		dmas = <&edma2 11 0 0>,
+			<&edma2 10 0 1>;
 		status = "disabled";
 	};
 
 	lpuart2: serial@5a080000 {
 		compatible = "fsl,imx8qm-lpuart";
 		reg = <0x0 0x5a080000 0x0 0x1000>;
-		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wu>;
 		clocks = <&clk IMX8QXP_UART2_CLK>,
-			 <&clk IMX8QXP_UART2_IPG_CLK>;
+			<&clk IMX8QXP_UART2_IPG_CLK>;
 		clock-names = "per", "ipg";
 		assigned-clocks = <&clk IMX8QXP_UART2_CLK>;
 		assigned-clock-rates = <80000000>;
-		power-domains = <&pd_dma_lpuart2>;
+		power-domains = <&pd_dma2_chan13>;
+		dma-names = "tx","rx";
+		dmas = <&edma2 13 0 0>,
+			<&edma2 12 0 1>;
 		status = "disabled";
 	};
 
 	lpuart3: serial@5a090000 {
 		compatible = "fsl,imx8qm-lpuart";
 		reg = <0x0 0x5a090000 0x0 0x1000>;
-		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wu>;
 		clocks = <&clk IMX8QXP_UART3_CLK>,
-			 <&clk IMX8QXP_UART3_IPG_CLK>;
+			<&clk IMX8QXP_UART3_IPG_CLK>;
 		clock-names = "per", "ipg";
 		assigned-clocks = <&clk IMX8QXP_UART3_CLK>;
 		assigned-clock-rates = <80000000>;
-		power-domains = <&pd_dma_lpuart3>;
+		power-domains = <&pd_dma3_chan15>;
+		dma-names = "tx","rx";
+		dmas = <&edma2 15 0 0>,
+			<&edma2 14 0 1>;
+		status = "disabled";
+	};
+
+	edma2: dma-controller@5a1f0000 {
+		compatible = "fsl,imx8qm-edma";
+		reg = <0x0 0x5a280000 0x0 0x10000>, /* channel8 UART0 rx */
+		      <0x0 0x5a290000 0x0 0x10000>, /* channel9 UART0 tx */
+		      <0x0 0x5a2a0000 0x0 0x10000>, /* channel10 UART1 rx */
+		      <0x0 0x5a2b0000 0x0 0x10000>, /* channel11 UART1 tx */
+		      <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART2 rx */
+		      <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART2 tx */
+		      <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART3 rx */
+		      <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART3 tx */
+		#dma-cells = <3>;
+		dma-channels = <8>;
+		interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx",
+				  "edma2-chan10-rx", "edma2-chan11-tx",
+				  "edma2-chan12-rx", "edma2-chan13-tx",
+				  "edma2-chan14-rx", "edma2-chan15-tx";
+		status = "okay";
+	};
+
+	edma0: dma-controller@591F0000 {
+		compatible = "fsl,imx8qm-edma";
+		reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */
+			<0x0 0x59210000 0x0 0x10000>,
+			<0x0 0x59220000 0x0 0x10000>,
+			<0x0 0x59230000 0x0 0x10000>,
+			<0x0 0x59240000 0x0 0x10000>,
+			<0x0 0x59250000 0x0 0x10000>,
+			<0x0 0x59260000 0x0 0x10000>, /* esai0 rx */
+			<0x0 0x59270000 0x0 0x10000>, /* esai0 tx */
+			<0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */
+			<0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */
+			<0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */
+			<0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */
+			<0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */
+			<0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */
+			<0x0 0x59350000 0x0 0x10000>,
+			<0x0 0x59370000 0x0 0x10000>;
+		#dma-cells = <3>;
+		shared-interrupt;
+		dma-channels = <16>;
+		interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */
+				<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */
+				<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
+				<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
+				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
+				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */
+				"edma0-chan2-rx", "edma0-chan3-tx",
+				"edma0-chan4-tx", "edma0-chan5-tx",
+				"edma0-chan6-rx", "edma0-chan7-tx", /* esai0 */
+				"edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */
+				"edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */
+				"edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */
+				"edma0-chan21-tx",		/* gpt5 */
+				"edma0-chan23-rx";		/* gpt7 */
+		status = "okay";
+	};
+
+	edma1: dma-controller@599F0000 {
+		compatible = "fsl,imx8qm-edma";
+		reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */
+			<0x0 0x59A10000 0x0 0x10000>,
+			<0x0 0x59A20000 0x0 0x10000>,
+			<0x0 0x59A30000 0x0 0x10000>,
+			<0x0 0x59A40000 0x0 0x10000>,
+			<0x0 0x59A50000 0x0 0x10000>,
+			<0x0 0x59A80000 0x0 0x10000>, /* sai4 rx */
+			<0x0 0x59A90000 0x0 0x10000>, /* sai4 tx */
+			<0x0 0x59AA0000 0x0 0x10000>; /* sai5 tx */
+		#dma-cells = <3>;
+		shared-interrupt;
+		dma-channels = <9>;
+		interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc 1 */
+				<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
+				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
+		interrupt-names = "edma1-chan0-rx", "edma1-chan1-rx", /* asrc1 */
+				"edma1-chan2-rx", "edma1-chan3-tx",
+				"edma1-chan4-tx", "edma1-chan5-tx",
+				"edma1-chan8-rx", "edma1-chan9-tx", /* sai4 */
+				"edma1-chan10-tx";                 /* sai5 */
+		status = "okay";
+	};
+
+	acm: acm@59e00000 {
+		compatible = "nxp,imx8qm-acm";
+		reg = <0x0 0x59e00000 0x0 0x1D0000>;
+		status = "disabled";
+	};
+
+	sai0: sai@59040000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x0 0x59040000 0x0 0x10000>;
+		interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_AUD_SAI_0_IPG>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_AUD_SAI_0_MCLK>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "rx", "tx";
+		dmas = <&edma0 12 0 1>, <&edma0 13 0 0>;
+		status = "disabled";
+		power-domains = <&pd_sai0>;
+	};
+
+	sai1: sai@59050000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x0 0x59050000 0x0 0x10000>;
+		interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_AUD_SAI_1_IPG>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_AUD_SAI_1_MCLK>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "rx", "tx";
+		dmas = <&edma0 14 0 1>, <&edma0 15 0 0>;
+		status = "disabled";
+		power-domains = <&pd_sai1>;
+	};
+
+	sai2: sai@59060000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x0 0x59060000 0x0 0x10000>;
+		interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_AUD_SAI_2_IPG>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_AUD_SAI_2_MCLK>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "rx";
+		dmas = <&edma0 16 0 1>;
+		status = "disabled";
+		power-domains = <&pd_sai2>;
+	};
+
+	sai3: sai@59070000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x0 0x59070000 0x0 0x10000>;
+		interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_AUD_SAI_3_IPG>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_AUD_SAI_3_MCLK>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "rx";
+		dmas = <&edma0 17 0 1>;
+		status = "disabled";
+		power-domains = <&pd_sai3>;
+	};
+
+	sai4: sai@59820000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x0 0x59820000 0x0 0x10000>;
+		interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_AUD_SAI_4_IPG>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_AUD_SAI_4_MCLK>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>;
+		dmas = <&edma1 8 0 1>, <&edma1 9 0 0>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "rx", "tx";
+		status = "disabled";
+		power-domains = <&pd_sai4>;
+	};
+
+	sai5: sai@59830000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x0 0x59830000 0x0 0x10000>;
+		interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_AUD_SAI_5_IPG>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_AUD_SAI_5_MCLK>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "tx";
+		dmas = <&edma1 10 0 0>;
+		status = "disabled";
+		power-domains = <&pd_sai5>;
+	};
+
+	amix: amix@59840000 {
+		compatible = "fsl,imx8qm-amix";
+		reg = <0x0 0x59840000 0x0 0x10000>;
+		clocks = <&clk IMX8QXP_AUD_AMIX_IPG>;
+		clock-names = "ipg";
+		power-domains = <&pd_amix>;
+		status = "disabled";
+	};
+
+	asrc0: asrc@59000000 {
+		compatible = "fsl,imx8qm-asrc0";
+		reg = <0x0 0x59000000 0x0 0x10000>;
+		interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_AUD_ASRC_0_IPG>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>,
+			<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>,
+			<&clk IMX8QXP_ACM_AUD_CLK0_SEL>,
+			<&clk IMX8QXP_ACM_AUD_CLK1_SEL>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>;
+		clock-names = "ipg", "mem",
+			"asrck_0", "asrck_1", "asrck_2", "asrck_3",
+			"asrck_4", "asrck_5", "asrck_6", "asrck_7",
+			"asrck_8", "asrck_9", "asrck_a", "asrck_b",
+			"asrck_c", "asrck_d", "asrck_e", "asrck_f",
+			"spba";
+		dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>,
+			<&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>;
+		dma-names = "rxa", "rxb", "rxc",
+				"txa", "txb", "txc";
+		fsl,asrc-rate  = <8000>;
+		fsl,asrc-width = <16>;
+		power-domains = <&pd_asrc0>;
+		status = "disabled";
+	};
+
+	asrc1: asrc@59800000 {
+		compatible = "fsl,imx8qm-asrc1";
+		reg = <0x0 0x59800000 0x0 0x10000>;
+		interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_AUD_ASRC_1_IPG>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>,
+			<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>,
+			<&clk IMX8QXP_ACM_AUD_CLK0_SEL>,
+			<&clk IMX8QXP_ACM_AUD_CLK1_SEL>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>;
+		clock-names = "ipg", "mem",
+			"asrck_0", "asrck_1", "asrck_2", "asrck_3",
+			"asrck_4", "asrck_5", "asrck_6", "asrck_7",
+			"asrck_8", "asrck_9", "asrck_a", "asrck_b",
+			"asrck_c", "asrck_d", "asrck_e", "asrck_f",
+			"spba";
+		dmas = <&edma1 0 0 0>, <&edma1 1 0 0>, <&edma1 2 0 0>,
+			<&edma1 3 0 1>, <&edma1 4 0 1>, <&edma1 5 0 1>;
+		dma-names = "rxa", "rxb", "rxc",
+				"txa", "txb", "txc";
+		fsl,asrc-rate  = <8000>;
+		fsl,asrc-width = <16>;
+		power-domains = <&pd_asrc1>;
+		status = "disabled";
+	};
+
+	mqs: mqs@59850000 {
+		compatible = "fsl,imx8qm-mqs";
+		reg = <0x0 0x59850000 0x0 0x10000>;
+		clocks = <&clk IMX8QXP_AUD_MQS_IPG>,
+			<&clk IMX8QXP_AUD_MQS_HMCLK>;
+		clock-names = "core", "mclk";
+		power-domains = <&pd_mqs0>;
 		status = "disabled";
 	};
 
@@ -474,10 +3178,10 @@
 		reg = <0x0 0x5b010000 0x0 0x10000>;
 		clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>,
 			<&clk IMX8QXP_SDHC0_CLK>,
-			<&clk IMX8QXP_CLK_DUMMY>;
+			<&clk IMX8QXP_SDHC0_AHB_CLK>;
 		clock-names = "ipg", "per", "ahb";
 		assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>;
-		assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
+		assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
 		assigned-clock-rates = <0>, <400000000>;
 		power-domains = <&pd_conn_sdch0>;
 		fsl,tuning-start-tap = <20>;
@@ -492,10 +3196,10 @@
 		reg = <0x0 0x5b020000 0x0 0x10000>;
 		clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>,
 			<&clk IMX8QXP_SDHC1_CLK>,
-			<&clk IMX8QXP_CLK_DUMMY>;
+			<&clk IMX8QXP_SDHC1_AHB_CLK>;
 		clock-names = "ipg", "per", "ahb";
 		assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>;
-		assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
+		assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
 		assigned-clock-rates = <0>, <200000000>;
 		power-domains = <&pd_conn_sdch1>;
 		fsl,tuning-start-tap = <20>;
@@ -510,109 +3214,370 @@
 		reg = <0x0 0x5b030000 0x0 0x10000>;
 		clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>,
 			<&clk IMX8QXP_SDHC2_CLK>,
-			<&clk IMX8QXP_CLK_DUMMY>;
+			<&clk IMX8QXP_SDHC2_AHB_CLK>;
 		clock-names = "ipg", "per", "ahb";
 		assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>;
-		assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
+		assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
 		assigned-clock-rates = <0>, <200000000>;
 		power-domains = <&pd_conn_sdch2>;
 		status = "disabled";
 	};
 
 	fec1: ethernet@5b040000 {
-		compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
+		compatible = "fsl,imx8qm-fec";
 		reg = <0x0 0x5b040000 0x0 0x10000>;
+                interrupt-parent = <&wu>;
 		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>,
-			<&clk IMX8QXP_ENET0_RGMII_TX_CLK>, <&clk IMX8QXP_ENET0_PTP_CLK>;
-		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
-		assigned-clocks = <&clk IMX8QXP_ENET0_REF_DIV>, <&clk IMX8QXP_ENET0_PTP_CLK>;
-		assigned-clock-rates = <125000000>, <125000000>;
+		clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, <&clk IMX8QXP_ENET0_RGMII_TX_CLK>,
+			<&clk IMX8QXP_ENET0_PTP_CLK>, <&clk IMX8QXP_ENET0_TX_CLK>;
+		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
+		assigned-clocks = <&clk IMX8QXP_ENET0_ROOT_DIV>,
+				  <&clk IMX8QXP_ENET0_REF_DIV>;
+		assigned-clock-rates = <250000000>, <125000000>;
 		fsl,num-tx-queues=<3>;
 		fsl,num-rx-queues=<3>;
+                fsl,wakeup_irq = <0>;
 		power-domains = <&pd_conn_enet0>;
 		status = "disabled";
 	};
 
 	fec2: ethernet@5b050000 {
-		compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec";
+		compatible = "fsl,imx8qm-fec";
 		reg = <0x0 0x5b050000 0x0 0x10000>;
+                interrupt-parent = <&wu>;
 		interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>,
-			<&clk IMX8QXP_ENET1_RGMII_TX_CLK>, <&clk IMX8QXP_ENET1_PTP_CLK>;
-		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
-		assigned-clocks = <&clk IMX8QXP_ENET1_REF_DIV>, <&clk IMX8QXP_ENET1_PTP_CLK>;
-		assigned-clock-rates = <125000000>, <125000000>;
+		clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>, <&clk IMX8QXP_ENET1_RGMII_TX_CLK>,
+			<&clk IMX8QXP_ENET1_PTP_CLK>, <&clk IMX8QXP_ENET1_TX_CLK>;
+		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
+		assigned-clocks = <&clk IMX8QXP_ENET1_ROOT_DIV>,
+				  <&clk IMX8QXP_ENET1_REF_DIV>;
+		assigned-clock-rates = <250000000>, <125000000>;
 		fsl,num-tx-queues=<3>;
 		fsl,num-rx-queues=<3>;
+                fsl,wakeup_irq = <0>;
 		power-domains = <&pd_conn_enet1>;
 		status = "disabled";
 	};
 
-	tsens: thermal-sensor {
-		compatible = "nxp,imx8qxp-sc-tsens";
-		/* number of the temp sensor on the chip */
-		tsens-num = <2>;
-		#thermal-sensor-cells = <1>;
+	mlb: mlb@5B060000 {
+		compatible = "fsl,imx6q-mlb150";
+		reg = <0x0 0x5B060000 0x0 0x10000>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 266 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_MLB_CLK>,
+			 <&clk IMX8QXP_MLB_HCLK>,
+			 <&clk IMX8QXP_MLB_IPG_CLK>;
+		clock-names = "mlb", "hclk", "ipg";
+		assigned-clocks = <&clk IMX8QXP_MLB_CLK>,
+				  <&clk IMX8QXP_MLB_HCLK>,
+				  <&clk IMX8QXP_MLB_IPG_CLK>;
+		assigned-clock-rates = <333333333>, <333333333>, <83333333>;
+		power-domains = <&pd_conn_mlb0>;
+		status = "disabled";
 	};
 
-	thermal_zones: thermal-zones {
-		/* cpu thermal */
-		cpu-thermal0 {
-			polling-delay-passive = <250>;
-			polling-delay = <2000>;
-			/*the slope and offset of the temp sensor */
-			thermal-sensors = <&tsens 0>;
-			trips {
-				cpu_alert0: trip0 {
-					temperature = <107000>;
-					hysteresis = <2000>;
-					type = "passive";
-				};
-				cpu_crit0: trip1 {
-					temperature = <127000>;
-					hysteresis = <2000>;
-					type = "critical";
-				};
-			};
-			cooling-maps {
-				map0 {
-					trip = <&cpu_alert0>;
-					cooling-device =
-					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-				};
-			};
+	gpt0: gpt0@5d140000 {
+		compatible = "fsl,imx8qxp-gpt";
+		reg = <0x0 0x5d140000 0x0 0x4000>;
+		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_CLK_DUMMY>, <&clk IMX8QXP_GPT_3M>;
+		clock-names = "ipg", "per";
+		power-domains = <&pd_lsio_gpt0>;
+	};
+
+	dsp: dsp@596e8000 {
+		compatible = "fsl,imx8qxp-dsp";
+		reserved-region = <&dsp_reserved>;
+		reg = <0x0 0x596e8000 0x0 0x88000>;
+		clocks = <&clk IMX8QXP_AUD_DSP_IPG>,
+			<&clk IMX8QXP_AUD_OCRAM_IPG>,
+			<&clk IMX8QXP_AUD_DSP_CORE_CLK>;
+		clock-names = "ipg", "ocram", "core";
+		fsl,dsp-firmware = "imx/dsp/hifi4.bin";
+		power-domains = <&pd_dsp>;
+	};
+
+	esai0: esai@59010000 {
+		compatible = "fsl,imx8qm-esai";
+		reg = <0x0 0x59010000 0x0 0x10000>;
+		interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_AUD_ESAI_0_IPG>,
+			<&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>,
+			<&clk IMX8QXP_AUD_ESAI_0_IPG>,
+			<&clk IMX8QXP_CLK_DUMMY>;
+		clock-names = "core", "extal", "fsys", "spba";
+		dmas = <&edma0 6 0 1>, <&edma0 7 0 0>;
+		dma-names = "rx", "tx";
+		power-domains = <&pd_esai0>;
+		status = "disabled";
+	};
+
+	spdif0: spdif@59020000 {
+		compatible = "fsl,imx8qm-spdif";
+		reg = <0x0 0x59020000 0x0 0x10000>;
+		interrupts =  <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */
+			     <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
+		clocks = <&clk IMX8QXP_AUD_SPDIF_0_GCLKW>, /* core */
+			<&clk IMX8QXP_CLK_DUMMY>, /* rxtx0 */
+			<&clk IMX8QXP_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */
+			<&clk IMX8QXP_CLK_DUMMY>, /* rxtx2 */
+			<&clk IMX8QXP_CLK_DUMMY>, /* rxtx3 */
+			<&clk IMX8QXP_CLK_DUMMY>, /* rxtx4 */
+			<&clk IMX8QXP_IPG_AUD_CLK_ROOT>, /* rxtx5 */
+			<&clk IMX8QXP_CLK_DUMMY>, /* rxtx6 */
+			<&clk IMX8QXP_CLK_DUMMY>, /* rxtx7 */
+			<&clk IMX8QXP_CLK_DUMMY>; /* spba */
+		clock-names = "core", "rxtx0",
+			      "rxtx1", "rxtx2",
+			      "rxtx3", "rxtx4",
+			      "rxtx5", "rxtx6",
+			      "rxtx7", "spba";
+		dmas = <&edma0 8 0 5>, <&edma0 9 0 4>;
+		dma-names = "rx", "tx";
+		power-domains = <&pd_spdif0>;
+		status = "disabled";
+	};
+
+	flexspi0: flexspi@05d120000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nxp,imx8qxp-fspi";
+		reg = <0x0 0x5d120000 0x0 0x10000>, <0x0 0x08000000 0x0 0x10000000>;
+		reg-names = "fspi_base", "fspi_mmap";
+		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_LSIO_FSPI0_CLK>,
+			<&clk IMX8QXP_LSIO_FSPI0_CLK>;
+		assigned-clocks = <&clk IMX8QXP_LSIO_FSPI0_DIV>;
+		assigned-clock-rates = <29000000>;
+		clock-names = "fspi", "fspi_en";
+		power-domains = <&pd_lsio_flexspi0>;
+		status = "disabled";
+	};
+
+	display-subsystem {
+		compatible = "fsl,imx-display-subsystem";
+		ports = <&dpu_disp0>, <&dpu_disp1>;
+	};
+
+	dma_cap: dma_cap {
+		compatible = "dma-capability";
+		only-dma-mask32 = <1>;
+	};
+
+	hsio: hsio@5f080000 {
+		compatible = "fsl,imx8qm-hsio", "syscon";
+		reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */
+	};
+
+	ocotp: ocotp {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,imx8qxp-ocotp", "syscon";
+	};
+
+	pcieb: pcie@0x5f010000 {
+		/*
+		 * pcieb phyx1 lane1 in default, adjust it refer to the
+		 * exact hw design.
+		 */
+		compatible = "fsl,imx8qxp-pcie","snps,dw-pcie";
+		reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg*/
+		      <0x0 0x7ff00000 0x0 0x80000>; /* PCI cfg space */
+		reg-names = "dbi", "config";
+		reserved-region = <&rpmsg_reserved>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */
+			  0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */
+		num-lanes = <1>;
+
+		#interrupt-cells = <1>;
+		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+		interrupt-names = "msi";
+
+		/*
+		 * Set these clocks in default, then clocks should be
+		 * refined for exact hw design of imx8 pcie.
+		 */
+		clocks = <&clk IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK>,
+			 <&clk IMX8QXP_HSIO_PCIE_SLV_AXI_CLK>,
+			 <&clk IMX8QXP_HSIO_PHY_X1_PCLK>,
+			 <&clk IMX8QXP_HSIO_PCIE_X1_PER_CLK>,
+			 <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>,
+			 <&clk IMX8QXP_HSIO_PHY_X1_PER_CLK>,
+			 <&clk IMX8QXP_HSIO_MISC_PER_CLK>;
+		clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi",
+					"phy_per", "misc_per";
+		interrupt-map-mask = <0 0 0 0x7>;
+		interrupt-map =  <0 0 0 1 &gic 0 105 4>,
+				 <0 0 0 2 &gic 0 106 4>,
+				 <0 0 0 3 &gic 0 107 4>,
+				 <0 0 0 4 &gic 0 108 4>;
+		power-domains = <&pd_pcie>;
+		fsl,max-link-speed = <3>;
+		hsio-cfg = <PCIEAX2PCIEBX1>;
+		hsio = <&hsio>;
+		ctrl-id = <1>; /* pcieb */
+		cpu-base-addr = <0x80000000>;
+		status = "disabled";
+	};
+
+	imx_ion {
+		compatible = "fsl,mxc-ion";
+		fsl,heap-id = <0>;
+	};
+
+	vpu: vpu@2c000000 {
+		compatible = "nxp,imx8qm-vpu", "nxp,imx8qxp-vpu";
+		reg = <0x0 0x2c000000 0x0 0x1000000>;
+		reg-names = "vpu_regs";
+		interrupts = <0 464 0x4>, /* encoder irq */
+		<0 465 0x4>, /* encoder fiq */
+		<0 466 0x4>, /* decoder irq */
+		<0 467 0x4>, /* decoder fiq */
+		<0 468 0x4>; /* decoder sif */
+		interrupt-names = "enc_irq", "enc_fiq", "dec_irq", "dec_fiq", "dec_sif";
+		clocks = <&clk IMX8QXP_VPU_DEC_CLK>;
+		clock-names = "vpu_clk";
+		assigned-clocks = <&clk IMX8QXP_VPU_DEC_CLK>;
+		power-domains = <&pd_vpu_dec>;
+		status = "disabled";
+	};
+
+	vpu_decoder: vpu_decoder@2c000000 {
+		compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec";
+		boot-region = <&decoder_boot>;
+		rpc-region = <&decoder_rpc>;
+		reg = <0x0 0x2c000000 0x0 0x1000000>;
+		reg-names = "vpu_regs";
+		power-domains = <&pd_vpu_dec>;
+		reg-csr = <0x2d040000>;
+		status = "disabled";
+	};
+
+	vpu_encoder: vpu_encoder@2d000000 {
+		compatible = "nxp,imx8qxp-b0-vpuenc";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot-region = <&encoder_boot>;
+		rpc-region = <&encoder_rpc>;
+		reserved-region = <&encoder_reserved>;
+		reg = <0x0 0x2d000000 0x0 0x1000000>,	/*VPU Encoder*/
+			<0x0 0x2c000000 0x0 0x2000000>; /*VPU*/
+		reg-names = "vpu_regs";
+		power-domains = <&pd_vpu_enc>;
+		reg-rpc-system = <0x40000000>;
+
+		resolution-max = <1920 1080>;
+		fps-max = <120>;
+		status = "disabled";
+
+		core0@1020000 {
+			compatible = "fsl,imx8-mu1-vpu-m0";
+			reg = <0x1020000 0x20000>;
+			reg-csr = <0x1050000 0x10000>;
+			interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
+			fsl,vpu_ap_mu_id = <17>;
+			fw-buf-size = <0x200000>;
+			rpc-buf-size = <0x80000>;
+			print-buf-size = <0x80000>;
 		};
+	};
+	imx_rpmsg: imx_rpmsg {
+		compatible = "fsl,rpmsg-bus", "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
 
-		drc-thermal0 {
-			polling-delay-passive = <250>;
-			polling-delay = <2000>;
-			thermal-sensors = <&tsens 1>;
+		mu_rpmsg: mu_rpmsg@5d200000 {
+			compatible = "fsl,imx6sx-mu";
+			reg = <0x0 0x5d200000 0x0 0x10000>;
+			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8QXP_LSIO_MU5A_IPG_CLK>;
+			clock-names = "ipg";
+			power-domains = <&pd_lsio_mu5a>;
+		};
+
+		rpmsg: rpmsg{
+			compatible = "fsl,imx8qxp-rpmsg";
 			status = "disabled";
-			trips {
-				drc_alert0: trip0 {
-					temperature = <107000>;
-					hysteresis = <2000>;
-					type = "passive";
-				};
-				drc_crit0: trip1 {
-					temperature = <127000>;
-					hysteresis = <2000>;
-					type = "critical";
-				};
-			};
+			mub-partition = <3>;
+			power-domains = <&pd_lsio_mu5a>;
+			memory-region = <&rpmsg_dma_reserved>;
+		};
+	};
+
+	crypto: caam@0x31400000 {
+		compatible = "fsl,sec-v4.0";
+		reg = <0 0x31400000 0 0x400000>;
+		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0x31400000 0x400000>;
+		fsl,first-jr-index = <2>;
+		fsl,sec-era = <9>;
+
+		sec_jr1: jr1@0x20000 {
+			compatible = "fsl,sec-v4.0-job-ring";
+			reg = <0x20000 0x1000>;
+			interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pd_caam_jr1>;
+			status = "disabled";
+		};
+
+		sec_jr2: jr2@30000 {
+			compatible = "fsl,sec-v4.0-job-ring";
+			reg = <0x30000 0x1000>;
+			interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pd_caam_jr2>;
+			status = "okay";
 		};
+
+		sec_jr3: jr3@40000 {
+			compatible = "fsl,sec-v4.0-job-ring";
+			reg = <0x40000 0x1000>;
+			interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pd_caam_jr3>;
+			status = "okay";
+		};
+	};
+
+	caam_sm: caam-sm@31800000 {
+		compatible = "fsl,imx6q-caam-sm";
+		reg = <0 0x31800000 0 0x10000>;
+	};
+
+	sc_pwrkey: sc-powerkey {
+		compatible = "fsl,imx8-pwrkey";
+		linux,keycode = <KEY_POWER>;
+		wakeup-source;
+	};
+
+	wdog: wdog {
+		compatible = "fsl,imx8-wdt";
 	};
 };
 
 &A35_0 {
+	operating-points = <
+		/* kHz	uV*/
+		/* voltage is maintained by SCFW, so no need here */
+		1200000 0
+		 900000 0
+	>;
 	clocks = <&clk IMX8QXP_A35_DIV>;
+	clock-latency = <61036>;
+	#cooling-cells = <2>;
 };
 
 /delete-node/ &A35_2;
diff --git a/arch/arm/dts/fsl-imx8dxl-ddr3l-evk-u-boot.dtsi b/arch/arm/dts/fsl-imx8dxl-ddr3l-evk-u-boot.dtsi
new file mode 100644
index 00000000000..8af1c20d4eb
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8dxl-ddr3l-evk-u-boot.dtsi
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+/ {
+	aliases {
+		usbgadget0 = &usbg1;
+		usbgadget1 = &usbg2;
+		gpio8 = &pca6416_a;
+		gpio9 = &pca6416_b;
+	};
+
+	usbg1: usbg1 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg1>;
+		status = "okay";
+		u-boot,dm-spl;
+	};
+
+	usbg2: usbg2 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg2>;
+		status = "okay";
+		u-boot,dm-spl;
+	};
+};
+
+&{/imx8dxl-pm} {
+
+	u-boot,dm-spl;
+};
+
+&mu {
+	u-boot,dm-spl;
+};
+
+&clk {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&{/regulators} {
+	u-boot,dm-spl;
+};
+
+&reg_usdhc2_vmmc {
+	u-boot,dm-spl;
+};
+
+&reg_usb_otg1_vbus {
+	u-boot,dm-spl;
+};
+
+&reg_usb_otg2_vbus {
+        u-boot,dm-spl;
+};
+
+&{/mu@5d1c0000/iomuxc/imx8dxl-evk} {
+	u-boot,dm-spl;
+};
+
+&pinctrl_lpuart0 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_100mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_200mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_flexspi0 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+	u-boot,dm-spl;
+};
+
+&pd_conn {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+	u-boot,dm-spl;
+};
+
+&pd_dma {
+	u-boot,dm-spl;
+};
+
+&pd_dma_lpuart0 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_flexspi0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0_phy {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg1 {
+        u-boot,dm-spl;
+};
+
+&pd_conn_usbotg1_phy {
+        u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&gpio5 {
+	u-boot,dm-spl;
+};
+
+&lpuart0 {
+	u-boot,dm-spl;
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
+};
+
+&flexspi0 {
+	u-boot,dm-spl;
+};
+
+&flash0 {
+	u-boot,dm-spl;
+};
+
+&usbphy1 {
+	u-boot,dm-spl;
+};
+
+&usbmisc1 {
+	u-boot,dm-spl;
+};
+
+&usbotg1 {
+	u-boot,dm-spl;
+};
+
+&ethphy0 {
+	reset-gpios = <&pca6416_a 2 GPIO_ACTIVE_LOW>;
+	reset-assert-us = <10000>;
+	reset-deassert-us = <150000>;
+
+	vddio0: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
+
+&eqos {
+	compatible = "fsl,imx-eqos";
+	phy-mode = "rgmii-id";
+};
+
+&usbphy2 {
+        u-boot,dm-spl;
+};
+
+&usbmisc2 {
+	u-boot,dm-spl;
+};
+
+&usbotg2 {
+        u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts b/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts
new file mode 100644
index 00000000000..040e52912e3
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8dxl-ddr3l-evk.dts
@@ -0,0 +1,417 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8dxl.dtsi"
+
+/ {
+	model = "NXP i.MX8DXL DDR3L EVK Board";
+	compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
+
+	chosen {
+		bootargs = "console=ttyLP0,115200 earlycon";
+		stdout-path = &lpuart0;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usdhc2_vmmc: usdhc2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "SD1_SPWR";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			startup-delay-us = <100>;
+			u-boot,off-on-delay-us = <12000>;
+		};
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg2_vbus: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "usb_otg2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx8dxl-evk {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0
+				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x00000021
+				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021
+			>;
+		};
+
+		pinctrl_eqos: eqosgrp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD		0x000514a0
+				SC_P_ENET0_MDC_CONN_EQOS_MDC				0x06000020
+				SC_P_ENET0_MDIO_CONN_EQOS_MDIO			0x06000020
+				SC_P_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL		0x00000060
+				SC_P_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC		0x00000060
+				SC_P_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0	0x00000060
+				SC_P_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1	0x00000060
+				SC_P_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2	0x00000060
+				SC_P_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3	0x00000060
+				SC_P_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC		0x00000060
+				SC_P_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL	0x00000060
+				SC_P_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0	0x00000060
+				SC_P_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1	0x00000060
+				SC_P_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2	0x00000060
+				SC_P_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3	0x00000060
+			>;
+		};
+
+		pinctrl_gpmi_nand_1: gpmi-nand-1 {
+			fsl,pins = <
+				SC_P_EMMC0_DATA0_CONN_NAND_DATA00	0x0e00004c
+				SC_P_EMMC0_DATA1_CONN_NAND_DATA01	0x0e00004c
+				SC_P_EMMC0_DATA2_CONN_NAND_DATA02	0x0e00004c
+				SC_P_EMMC0_DATA3_CONN_NAND_DATA03	0x0e00004c
+				SC_P_EMMC0_DATA4_CONN_NAND_DATA04	0x0e00004c
+				SC_P_EMMC0_DATA5_CONN_NAND_DATA05	0x0e00004c
+				SC_P_EMMC0_DATA6_CONN_NAND_DATA06	0x0e00004c
+				SC_P_EMMC0_DATA7_CONN_NAND_DATA07	0x0e00004c
+				SC_P_EMMC0_CLK_CONN_NAND_READY_B	0x0e00004c
+				SC_P_EMMC0_STROBE_CONN_NAND_CLE		0x0e00004c
+				SC_P_EMMC0_RESET_B_CONN_NAND_WP_B	0x0e00004c
+				SC_P_EMMC0_CMD_CONN_NAND_DQS		0x0e00004c
+
+				SC_P_USDHC1_RESET_B_CONN_NAND_WE_B	0x0e00004c
+				SC_P_USDHC1_WP_CONN_NAND_ALE		0x0e00004c
+				SC_P_USDHC1_VSELECT_CONN_NAND_RE_B  	0x0e00004c
+			>;
+		};
+
+		pinctrl_lpuart0: lpuart0grp {
+			fsl,pins = <
+				SC_P_UART0_RX_ADMA_UART0_RX	0x06000020
+				SC_P_UART0_TX_ADMA_UART0_TX	0x06000020
+			>;
+		};
+
+		pinctrl_lpi2c2: lpi2c2grp {
+			fsl,pins = <
+				SC_P_SPI1_SDO_ADMA_I2C2_SCL	0x06000021
+				SC_P_SPI1_SCK_ADMA_I2C2_SDA	0x06000021
+			>;
+		};
+
+		pinctrl_lpi2c3: lpi2c3grp {
+			fsl,pins = <
+				SC_P_SPI1_SDI_ADMA_I2C3_SCL	0x06000021
+				SC_P_SPI1_CS0_ADMA_I2C3_SDA	0x06000021
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+			fsl,pins = <
+				SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x00000021 /* RESET_B */
+				SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00		0x00000021 /* WP */
+				SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x00000021 /* CD */
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
+				SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD		0x00000021
+				SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
+				SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD		0x00000021
+				SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
+				SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD		0x00000021
+				SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_flexspi0: flexspi0grp {
+			fsl,pins = <
+				SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x06000021
+				SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x06000021
+				SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x06000021
+				SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x06000021
+				SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS		0x06000021
+				SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x06000021
+				SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x06000021
+				SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x06000021
+				SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x06000021
+				SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x06000021
+				SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x06000021
+			>;
+		};
+
+		pinctrl_pcieb: pcieagrp{
+			fsl,pins = <
+				SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00		0x06000021
+				SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01	0x06000021
+				SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02		0x04000021
+			>;
+		};
+	};
+};
+
+&A35_0 {
+	u-boot,dm-pre-reloc;
+};
+
+&lpuart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart0>;
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c2>;
+	status = "okay";
+
+	i2cswitch@70 {
+		compatible = "nxp,pca9646";
+		reg = <0x70>;
+		u-boot,i2c-offset-len = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		v2x_i2c2: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0>;
+		};
+
+		audio_codec1_i2c2: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x1>;
+		};
+
+		audio_codec2_i2c2: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2>;
+		};
+
+		audio_codec3_i2c2: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+		};
+
+		audio_codec0_i2c2: i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x4>;
+		};
+	};
+
+	pca6416_a: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pca6416_b: gpio@21 {
+		compatible = "ti,tca6416";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c3>;
+	status = "disabled";
+
+	i2cswitch@70 {
+		compatible = "nxp,pca9646";
+		reg = <0x70>;
+		u-boot,i2c-offset-len = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		alt_audio_codec1_i2c3: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0>;
+		};
+
+		alt_audio_codec2_i2c3: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x1>;
+		};
+
+		alt_audio_codec3_i2c3: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2>;
+		};
+
+		usb1_i2c3: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+		};
+
+		usb2_i2c3: i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x4>;
+		};
+	};
+
+	pca6416_c: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&flexspi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi0>;
+	status = "okay";
+
+	flash0: mt35xu512aba@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <8>;
+	};
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	max-frequency = <100000000>;
+	status = "okay";
+};
+
+&eqos {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eqos>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy0>;
+	fsl,ar8031-phy-fixup;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+
+	};
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "okay";
+	nand-on-flash-bbt;
+	fsl,use-minimum-ecc;
+};
+
+&pcieb{
+	ext_osc = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcieb>;
+	clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>;
+	reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	dr_mode = "otg";
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	power-polarity-active-high;
+	disable-over-current;
+	status = "okay";
+};
+
+&usbotg2 {
+	vbus-supply = <&reg_usb_otg2_vbus>;
+	dr_mode = "otg";
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	power-polarity-active-high;
+	disable-over-current;
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-imx8dxl-evk-lcdif.dts b/arch/arm/dts/fsl-imx8dxl-evk-lcdif.dts
new file mode 100644
index 00000000000..8ff96eeec05
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8dxl-evk-lcdif.dts
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 NXP.
+ */
+
+#include "fsl-imx8dxl-evk.dts"
+#include "fsl-imx8dxl-evk-u-boot.dtsi"
+
+&eqos {
+	status = "disabled";
+};
+
+&lpspi3 {
+	status = "disabled";
+};
+
+&iomuxc {
+	pinctrl_lcdif: lcdifgrp {
+		fsl,pins = <
+			SC_P_SPI3_SCK_ADMA_LCDIF_D00			0x00000023
+			SC_P_SPI3_SDO_ADMA_LCDIF_D01		0x00000023
+			SC_P_SPI3_SDI_ADMA_LCDIF_D02			0x00000023
+			SC_P_ENET1_RGMII_TXD3_ADMA_LCDIF_D03		0x00000023
+			SC_P_UART1_TX_ADMA_LCDIF_D04		0x00000023
+			SC_P_UART1_RX_ADMA_LCDIF_D05		0x00000023
+			SC_P_UART1_RTS_B_ADMA_LCDIF_D06		0x00000023
+			SC_P_UART1_CTS_B_ADMA_LCDIF_D07		0x00000023
+			SC_P_SPI0_SCK_ADMA_LCDIF_D08			0x00000023
+			SC_P_SPI0_SDI_ADMA_LCDIF_D09			0x00000023
+			SC_P_SPI0_SDO_ADMA_LCDIF_D10		0x00000023
+			SC_P_SPI0_CS1_ADMA_LCDIF_D11			0x00000023
+			SC_P_SPI0_CS0_ADMA_LCDIF_D12			0x00000023
+			SC_P_ADC_IN1_ADMA_LCDIF_D13			0x00200003
+			SC_P_ADC_IN0_ADMA_LCDIF_D14			0x00200003
+			SC_P_ADC_IN3_ADMA_LCDIF_D15			0x00200003
+			SC_P_ADC_IN2_ADMA_LCDIF_D16			0x00200003
+			SC_P_ADC_IN5_ADMA_LCDIF_D17			0x00200003
+			SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC		0x00000023
+			SC_P_SPI3_CS1_ADMA_LCDIF_RESET		0x00000023
+			SC_P_MCLK_IN1_ADMA_LCDIF_EN			0x00000023
+			SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC		0x00000023
+			SC_P_MCLK_OUT0_ADMA_LCDIF_CLK		0x00000023
+		>;
+	};
+};
+
+&adma_lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif>;
+	status = "okay";
+
+	assigned-clocks = <&clk IMX8QXP_LCD_SEL>,
+			<&clk IMX8QXP_LCD_PXL_SEL>,
+			<&clk IMX8QXP_ELCDIF_PLL_DIV>;
+	assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL_DIV>,
+			<&clk IMX8QXP_LCD_PXL_BYPASS_DIV>;
+	assigned-clock-rates = <0>, <0>, <711000000>;
+
+	display = <&display0>;
+
+	display0: display@0 {
+		bits-per-pixel = <18>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+				clock-frequency = <71100000>;
+				hactive = <1280>;
+				vactive = <800>;
+				hfront-porch = <70>;
+				hback-porch = <80>;
+				hsync-len = <10>;
+				vback-porch = <10>;
+				vfront-porch = <10>;
+				vsync-len = <3>;
+
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/fsl-imx8dxl-evk-u-boot.dtsi b/arch/arm/dts/fsl-imx8dxl-evk-u-boot.dtsi
new file mode 100644
index 00000000000..798ad9964a4
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8dxl-evk-u-boot.dtsi
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+/ {
+	aliases {
+		usbgadget0 = &usbg1;
+		usbgadget1 = &usbg2;
+		gpio8 = &pca6416_a;
+		gpio9 = &pca6416_b;
+	};
+
+	usbg1: usbg1 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg1>;
+		status = "okay";
+		u-boot,dm-spl;
+	};
+
+	usbg2: usbg2 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg2>;
+		status = "okay";
+		u-boot,dm-spl;
+	};
+};
+
+&{/imx8dxl-pm} {
+
+	u-boot,dm-spl;
+};
+
+&mu {
+	u-boot,dm-spl;
+};
+
+&clk {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&{/regulators} {
+	u-boot,dm-spl;
+};
+
+&reg_usdhc2_vmmc {
+	u-boot,dm-spl;
+};
+
+&reg_usb_otg1_vbus {
+	u-boot,dm-spl;
+};
+
+&reg_usb_otg2_vbus {
+        u-boot,dm-spl;
+};
+
+&{/mu@5d1c0000/iomuxc/imx8dxl-evk} {
+	u-boot,dm-spl;
+};
+
+&pinctrl_lpuart0 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_100mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_200mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_100mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_200mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_flexspi0 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+	u-boot,dm-spl;
+};
+
+&pd_conn {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+	u-boot,dm-spl;
+};
+
+&pd_dma {
+	u-boot,dm-spl;
+};
+
+&pd_dma_lpuart0 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_flexspi0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0_phy {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg1 {
+        u-boot,dm-spl;
+};
+
+&pd_conn_usbotg1_phy {
+        u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&gpio5 {
+	u-boot,dm-spl;
+};
+
+&lpuart0 {
+	u-boot,dm-spl;
+};
+
+&usdhc1 {
+	u-boot,dm-spl;
+	mmc-hs400-1_8v;
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
+};
+
+&flexspi0 {
+	u-boot,dm-spl;
+};
+
+&flash0 {
+	u-boot,dm-spl;
+};
+
+&usbphy1 {
+	u-boot,dm-spl;
+};
+
+&usbmisc1 {
+	u-boot,dm-spl;
+};
+
+&usbotg1 {
+	u-boot,dm-spl;
+};
+
+&eqos {
+	compatible = "fsl,imx-eqos";
+	phy-mode = "rgmii-id";
+};
+
+&fec1 {
+	phy-mode = "rgmii-id";
+};
+
+&ethphy0 {
+	reset-gpios = <&pca6416_a 2 GPIO_ACTIVE_LOW>;
+	reset-assert-us = <10000>;
+	reset-deassert-us = <150000>;
+
+	vddio0: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
+
+&ethphy1 {
+	vddio1: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
+
+&usbphy2 {
+        u-boot,dm-spl;
+};
+
+&usbmisc2 {
+	u-boot,dm-spl;
+};
+
+&usbotg2 {
+        u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/fsl-imx8dxl-evk.dts b/arch/arm/dts/fsl-imx8dxl-evk.dts
new file mode 100644
index 00000000000..4154c797b25
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8dxl-evk.dts
@@ -0,0 +1,565 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8dxl.dtsi"
+
+/ {
+	model = "NXP i.MX8DXL EVK Board";
+	compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
+
+	chosen {
+		bootargs = "console=ttyLP0,115200 earlycon";
+		stdout-path = &lpuart0;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_fec1: regfec1 {
+			compatible = "regulator-fixed";
+			regulator-name = "fec1_supply";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&pca6416_a 11 GPIO_ACTIVE_LOW>;
+			enable-active-high;
+		};
+
+		reg_usdhc2_vmmc: usdhc2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "SD1_SPWR";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			startup-delay-us = <100>;
+			u-boot,off-on-delay-us = <12000>;
+		};
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg2_vbus: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "usb_otg2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		epdev_on: fixedregulator@100 {
+			compatible = "regulator-fixed";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-name = "epdev_on";
+			gpio = 	<&pca6416_a 13 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+
+		};
+
+		pcie_clk_sel_ext: fixedregulator@101 {
+			compatible = "regulator-fixed";
+			regulator-min-microvolt = <0000000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-name = "clk_ext_sel";
+			gpio = <&pca6416_a 10 GPIO_ACTIVE_HIGH>;
+			regulator-always-on;
+		};
+
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx8dxl-evk {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0
+				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x00000021
+				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021
+			>;
+		};
+
+		pinctrl_eqos: eqosgrp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD		0x000514a0
+				SC_P_ENET0_MDC_CONN_EQOS_MDC				0x06000020
+				SC_P_ENET0_MDIO_CONN_EQOS_MDIO			0x06000020
+				SC_P_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL		0x00000060
+				SC_P_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC		0x00000060
+				SC_P_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0	0x00000060
+				SC_P_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1	0x00000060
+				SC_P_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2	0x00000060
+				SC_P_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3	0x00000060
+				SC_P_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC		0x00000060
+				SC_P_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL	0x00000060
+				SC_P_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0	0x00000060
+				SC_P_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1	0x00000060
+				SC_P_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2	0x00000060
+				SC_P_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3	0x00000060
+			>;
+		};
+
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000060
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x00000060
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000060
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000060
+				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x00000060
+				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x00000060
+				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x00000060
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000060
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000060
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000060
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x00000060
+				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x00000060
+			>;
+		};
+
+		pinctrl_lpuart0: lpuart0grp {
+			fsl,pins = <
+				SC_P_UART0_RX_ADMA_UART0_RX	0x06000020
+				SC_P_UART0_TX_ADMA_UART0_TX	0x06000020
+			>;
+		};
+
+		pinctrl_lpi2c2: lpi2c2grp {
+			fsl,pins = <
+				SC_P_SPI1_SDO_ADMA_I2C2_SCL	0x06000021
+				SC_P_SPI1_SCK_ADMA_I2C2_SDA	0x06000021
+			>;
+		};
+
+		pinctrl_lpi2c3: lpi2c3grp {
+			fsl,pins = <
+				SC_P_SPI1_SDI_ADMA_I2C3_SCL	0x06000021
+				SC_P_SPI1_CS0_ADMA_I2C3_SDA	0x06000021
+			>;
+		};
+
+		pinctrl_lpspi3: lpspi3grp {
+			fsl,pins = <
+				SC_P_SPI3_SCK_ADMA_SPI3_SCK	0x0600004c
+				SC_P_SPI3_SDO_ADMA_SPI3_SDO	0x0600004c
+				SC_P_SPI3_SDI_ADMA_SPI3_SDI	0x0600004c
+				SC_P_SPI3_CS1_ADMA_SPI3_CS1	0x0600004c
+				SC_P_SPI3_CS0_LSIO_GPIO0_IO16	0x21
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+			fsl,pins = <
+				SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x00000021 /* RESET_B */
+				SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00		0x00000021 /* WP */
+				SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x00000021 /* CD */
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
+				SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD		0x00000021
+				SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
+				SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD		0x00000021
+				SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
+				SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD		0x00000021
+				SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_flexspi0: flexspi0grp {
+			fsl,pins = <
+				SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x06000021
+				SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x06000021
+				SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x06000021
+				SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x06000021
+				SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS		0x06000021
+				SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x06000021
+				SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x06000021
+				SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x06000021
+				SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x06000021
+				SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x06000021
+				SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x06000021
+			>;
+		};
+
+		pinctrl_pcieb: pcieagrp{
+			fsl,pins = <
+				SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00		0x06000021
+				SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01	0x06000021
+				SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02		0x04000021
+			>;
+		};
+	};
+};
+
+&A35_0 {
+	u-boot,dm-pre-reloc;
+};
+
+&lpuart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart0>;
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&lpspi3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpspi3>;
+	cs-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>, <0>, <0>, <0>;
+	spi-max-frequency = <1000000>;
+	status = "okay";
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c2>;
+	status = "okay";
+
+	i2cswitch@70 {
+		compatible = "nxp,pca9646";
+		reg = <0x70>;
+		u-boot,i2c-offset-len = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		v2x_i2c2: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0>;
+		};
+
+		audio_codec1_i2c2: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x1>;
+		};
+
+		audio_codec2_i2c2: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2>;
+		};
+
+		audio_codec3_i2c2: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+		};
+
+		m2_i2c2: i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x4>;
+		};
+
+		pcie_i2c2: i2c@5 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x5>;
+		};
+
+		lcd_i2c2: i2c@6 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x6>;
+		};
+	};
+
+	pca6416_a: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pca6416_b: gpio@21 {
+		compatible = "ti,tca6416";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c3>;
+	status = "disabled";
+
+	i2cswitch@70 {
+		compatible = "nxp,pca9646";
+		reg = <0x70>;
+		u-boot,i2c-offset-len = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		alt_audio_codec1_i2c3: i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0>;
+		};
+
+		alt_audio_codec2_i2c3: i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x1>;
+		};
+
+		alt_audio_codec3_i2c3: i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2>;
+		};
+
+		usb1_i2c3: i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+		};
+
+		usb2_i2c3: i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x4>;
+		};
+	};
+
+	pca6416_c: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&flexspi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi0>;
+	nxp,fspi-dll-slvdly = <4>;
+	status = "okay";
+
+	flash0: mt35xu512aba@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <133000000>;
+		spi-tx-bus-width = <8>;
+		spi-rx-bus-width = <8>;
+	};
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	max-frequency = <100000000>;
+	status = "okay";
+};
+
+&eqos {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eqos>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy0>;
+	fsl,ar8031-phy-fixup;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+
+	};
+};
+
+&pcieb{
+	ext_osc = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcieb>;
+	clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>;
+	power-on-gpio = <&pca6416_a 12 GPIO_ACTIVE_HIGH>;
+	reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>;
+	epdev_on = <&epdev_on>;
+	status = "okay";
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy1>;
+	fsl,ar8031-phy-fixup;
+	fsl,magic-packet;
+	phy-supply = <&reg_fec1>;
+	status = "disable";
+	phy-reset-gpios = <&pca6416_a 0 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <10>;
+	phy-reset-post-delay = <150>;
+
+	/* mdio/mdc pins conflict with eqos, so should be shared mii bus
+	 * fec1 pins has conflict with usdhc2
+	 * for bringup, only enable one mac
+	 */
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>; /* ensure your net card phy id: 0x1 */
+		};
+
+	};
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	dr_mode = "otg";
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	power-polarity-active-high;
+	disable-over-current;
+	status = "okay";
+};
+
+&usbotg2 {
+	vbus-supply = <&reg_usb_otg2_vbus>;
+	dr_mode = "otg";
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	power-polarity-active-high;
+	disable-over-current;
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-imx8dxl-phantom-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8dxl-phantom-mek-u-boot.dtsi
new file mode 100644
index 00000000000..8808f8e5cec
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8dxl-phantom-mek-u-boot.dtsi
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+/ {
+	aliases {
+		usbgadget0 = &usbg1;
+	};
+
+	usbg1: usbg1 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg1>;
+		status = "okay";
+		u-boot,dm-spl;
+	};
+};
+
+&{/imx8qx-pm} {
+
+	u-boot,dm-spl;
+};
+
+&mu {
+	u-boot,dm-spl;
+};
+
+&clk {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&{/regulators} {
+	u-boot,dm-spl;
+};
+
+&reg_usdhc2_vmmc {
+	u-boot,dm-spl;
+};
+
+&{/mu@5d1c0000/iomuxc/imx8qxp-mek} {
+	u-boot,dm-spl;
+};
+
+&pinctrl_lpuart0 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_flexspi0 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+	u-boot,dm-spl;
+};
+
+&pd_conn {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+	u-boot,dm-spl;
+};
+
+&pd_dma {
+	u-boot,dm-spl;
+};
+
+&pd_dma_lpuart0 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_flexspi0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0_phy {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&lpuart0 {
+	u-boot,dm-spl;
+};
+
+&usdhc1 {
+	u-boot,dm-spl;
+	mmc-hs400-1_8v;
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
+};
+
+&flexspi0 {
+	u-boot,dm-spl;
+};
+
+&flash0 {
+	u-boot,dm-spl;
+};
+
+&usbmisc1 {
+	u-boot,dm-spl;
+};
+
+&usbphy1 {
+	u-boot,dm-spl;
+};
+
+&usbotg1 {
+	u-boot,dm-spl;
+};
+
+&fec2 {
+	phy-mode = "rgmii-id";
+};
+
+&ethphy0 {
+	vddio0: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
\ No newline at end of file
diff --git a/arch/arm/dts/fsl-imx8dxl-phantom-mek.dts b/arch/arm/dts/fsl-imx8dxl-phantom-mek.dts
new file mode 100644
index 00000000000..74810b13e0f
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8dxl-phantom-mek.dts
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qxp.dtsi"
+
+/ {
+	model = "NXP i.MX8DXL PHANTOM MEK";
+	compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
+
+	chosen {
+		bootargs = "console=ttyLP0,115200 earlycon";
+		stdout-path = &lpuart0;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usdhc2_vmmc: usdhc2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "SD1_SPWR";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			startup-delay-us = <100>;
+			off-on-delay-us = <12000>;
+		};
+
+		epdev_on: fixedregulator@100 {
+			compatible = "regulator-fixed";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&pinctrl_wlreg_on>;
+			pinctrl-1 = <&pinctrl_wlreg_on_sleep>;
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-name = "epdev_on";
+			gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx8qxp-mek {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0	0x0600004c
+				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0
+				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x00000021
+			>;
+		};
+
+		pinctrl_fec2: fec2grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0
+				SC_P_ENET0_MDC_CONN_ENET1_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET1_MDIO			0x06000020
+				SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x00000060
+				SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC		0x00000060
+				SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0	0x00000060
+				SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1	0x00000060
+				SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2		0x00000060
+				SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3		0x00000060
+				SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC		0x00000060
+				SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x00000060
+				SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x00000060
+				SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1	0x00000060
+				SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2	0x00000060
+				SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3		0x00000060
+				SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x00000021
+			>;
+		};
+
+		pinctrl_lpuart0: lpuart0grp {
+			fsl,pins = <
+				SC_P_UART0_RX_ADMA_UART0_RX	0x06000020
+				SC_P_UART0_TX_ADMA_UART0_TX	0x06000020
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+			fsl,pins = <
+				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19	0x00000021
+				SC_P_USDHC1_WP_LSIO_GPIO4_IO21		0x00000021
+				SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
+				SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD		0x00000021
+				SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_flexspi0: flexspi0grp {
+			fsl,pins = <
+				SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x06000021
+				SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x06000021
+				SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x06000021
+				SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x06000021
+				SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS		0x06000021
+				SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x06000021
+				SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x06000021
+				SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x06000021
+				SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x06000021
+				SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x06000021
+				SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x06000021
+			>;
+		};
+
+		pinctrl_pcieb: pcieagrp{
+			fsl,pins = <
+				SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00		0x06000021
+				SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01	0x06000021
+				SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02		0x04000021
+			>;
+		};
+
+		pinctrl_wlreg_on: wlregongrp{
+			fsl,pins = <
+				SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18		0x06000000
+			>;
+		};
+
+		pinctrl_wlreg_on_sleep: wlregon_sleepgrp{
+			fsl,pins = <
+				SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18		0x07800000
+			>;
+		};
+	};
+};
+
+&A35_0 {
+	u-boot,dm-pre-reloc;
+};
+
+&lpuart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart0>;
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&flexspi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi0>;
+	status = "okay";
+
+	flash0: mt35xu512aba@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <8>;
+	};
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1>;
+	pinctrl-2 = <&pinctrl_usdhc1>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec2>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy0>;
+	fsl,ar8031-phy-fixup;
+	fsl,magic-packet;
+	status = "okay";
+
+	phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <10>;
+	phy-reset-post-delay = <150>;
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+	};
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	power-polarity-active-high;
+	disable-over-current;
+	status = "okay";
+};
+
+&pcieb{
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcieb>;
+	clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>;
+	reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>;
+	epdev_on = <&epdev_on>;
+	ext_osc = <1>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-imx8dxl.dtsi b/arch/arm/dts/fsl-imx8dxl.dtsi
new file mode 100644
index 00000000000..05ce432806b
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8dxl.dtsi
@@ -0,0 +1,1952 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "fsl-imx8-ca35.dtsi"
+#include <dt-bindings/soc/imx_rsrc.h>
+#include <dt-bindings/soc/imx8_hsio.h>
+#include <dt-bindings/soc/imx8_pd.h>
+#include <dt-bindings/clock/imx8qxp-clock.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/pads-imx8dxl.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	model = "NXP i.MX8DXL";
+	compatible = "fsl,imx8dxl";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		ethernet0 = &fec1;
+		ethernet1 = &eqos;
+		serial0 = &lpuart0;
+		serial1 = &lpuart1;
+		serial2 = &lpuart2;
+		serial3 = &lpuart3;
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+		gpio3 = &gpio3;
+		gpio4 = &gpio4;
+		gpio5 = &gpio5;
+		gpio6 = &gpio6;
+		gpio7 = &gpio7;
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+		mmc2 = &usdhc3;
+		can0 = &flexcan1;
+		can1 = &flexcan2;
+		can2 = &flexcan3;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		spi0 = &flexspi0;
+		spi1 = &lpspi3;
+		usb0 = &usbotg1;
+		usbphy0 = &usbphy1;
+		usb1 = &usbotg2;
+		usbphy1 = &usbphy2;
+		pci0 = &pcieb;
+	};
+
+	cpus {
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP: cpu-sleep {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x10000>;
+				local-timer-stop;
+				entry-latency-us = <500>;
+				exit-latency-us = <500>;
+				min-residency-us = <5000>;
+			};
+
+			CLUSTER_SLEEP: cluster-sleep {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x10033>;
+				local-timer-stop;
+				entry-latency-us = <500>;
+				exit-latency-us = <2300>;
+				min-residency-us = <14000>;
+			};
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000 0 0x40000000>;
+		      /* DRAM space - 1, size : 1 GB DRAM */
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/*
+		 * reserved-memory layout
+		 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
+		 * Shouldn't be used at A core and Linux side.
+		 *
+		 */
+		rpmsg_reserved: rpmsg@0x90000000 {
+			no-map;
+			reg = <0 0x90000000 0 0x400000>;
+		};
+		rpmsg_dma_reserved:rpmsg_dma@0x90400000 {
+			compatible = "shared-dma-pool";
+			no-map;
+			reg = <0 0x90400000 0 0x1C00000>;
+		};
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0 0x3c000000>;
+			alloc-ranges = <0 0x96000000 0 0x3c000000>;
+			linux,cma-default;
+		};
+	};
+
+	gic: interrupt-controller@51a00000 {
+		compatible = "arm,gic-v3";
+		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
+		      <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupts = <GIC_PPI 9
+			(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupt-parent = <&gic>;
+	};
+
+	mu8: mu@5d230000 {
+		compatible = "fsl,imx-m4-mu";
+		reg = <0x0 0x5d230000 0x0 0x10000>;
+		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&pd_lsio_mu8a>;
+		status = "okay";
+	};
+
+	mu: mu@5d1c0000 {
+		compatible = "fsl,imx8-mu";
+		reg = <0x0 0x5d1c0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		status = "okay";
+
+		clk: clk {
+			compatible = "fsl,imx8qxp-clk";
+			#clock-cells = <1>;
+		};
+
+		iomuxc: iomuxc {
+			compatible = "fsl,imx8qxp-iomuxc";
+		};
+	};
+
+	mu13: mu13@5d280000 {
+		compatible = "fsl,imx8-mu-dsp";
+		reg = <0x0 0x5d280000 0x0 0x10000>;
+		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,dsp_ap_mu_id = <13>;
+		status = "okay";
+	};
+
+	rtc: rtc {
+		compatible = "fsl,imx-sc-rtc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+		clock-frequency = <8000000>;
+		interrupt-parent = <&gic>;
+	};
+
+	imx8dxl-pm {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pd_lsio: PD_LSIO {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_NONE>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_lsio_pwm0: PD_LSIO_PWM_0 {
+				reg = <SC_R_PWM_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_pwm1: PD_LSIO_PWM_1 {
+				reg = <SC_R_PWM_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_pwm2: PD_LSIO_PWM_2 {
+				reg = <SC_R_PWM_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_pwm3: PD_LSIO_PWM_3 {
+				reg = <SC_R_PWM_3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_pwm4: PD_LSIO_PWM_4 {
+				reg = <SC_R_PWM_4>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_pwm5: PD_LSIO_PWM_5 {
+				reg = <SC_R_PWM_5>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_pwm6: PD_LSIO_PWM_6 {
+				reg = <SC_R_PWM_6>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_pwm7: PD_LSIO_PWM_7 {
+				reg = <SC_R_PWM_7>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_kpp: PD_LSIO_KPP {
+				reg = <SC_R_KPP>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio0: PD_LSIO_GPIO_0 {
+				reg = <SC_R_GPIO_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio1: PD_LSIO_GPIO_1 {
+				reg = <SC_R_GPIO_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio2: PD_LSIO_GPIO_2 {
+				reg = <SC_R_GPIO_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio3: PD_LSIO_GPIO_3 {
+				reg = <SC_R_GPIO_3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio4: PD_LSIO_GPIO_4 {
+				reg = <SC_R_GPIO_4>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio5: PD_LSIO_GPIO_5{
+				reg = <SC_R_GPIO_5>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio6:PD_LSIO_GPIO_6 {
+				reg = <SC_R_GPIO_6>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio7: PD_LSIO_GPIO_7 {
+				reg = <SC_R_GPIO_7>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpt0: PD_LSIO_GPT_0 {
+				reg = <SC_R_GPT_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpt1: PD_LSIO_GPT_1 {
+				reg = <SC_R_GPT_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpt2: PD_LSIO_GPT_2 {
+				reg = <SC_R_GPT_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpt3: PD_LSIO_GPT_3 {
+				reg = <SC_R_GPT_3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpt4: PD_LSIO_GPT_4 {
+				reg = <SC_R_GPT_4>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_flexspi0: PD_LSIO_FSPI_0 {
+				reg = <SC_R_FSPI_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_flexspi1: PD_LSIO_FSPI_1{
+				reg = <SC_R_FSPI_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_mu5a: PD_LSIO_MU5A {
+				reg = <SC_R_MU_5A>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_mu8a: PD_LSIO_MU8A {
+				reg = <SC_R_MU_8A>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+		};
+
+		pd_conn: PD_CONN {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_NONE>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_conn_usbotg0: PD_CONN_USB_0 {
+				reg = <SC_R_USB_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				wakeup-irq = <169>;
+
+				pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY {
+					reg = <SC_R_USB_0_PHY>;
+					#power-domain-cells = <0>;
+					power-domains = <&pd_conn_usbotg0>;
+					wakeup-irq = <169>;
+				};
+
+			};
+			pd_conn_usbotg1: PD_CONN_USB_1 {
+				reg = <SC_R_USB_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				wakeup-irq = <166>;
+
+				pd_conn_usbotg1_phy: PD_CONN_USB_1_PHY {
+					reg = <SC_R_USB_1_PHY>;
+					#power-domain-cells = <0>;
+					power-domains = <&pd_conn_usbotg1>;
+					wakeup-irq = <166>;
+				};
+			};
+			pd_conn_sdch0: PD_CONN_SDHC_0 {
+				reg = <SC_R_SDHC_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+			};
+			pd_conn_sdch1: PD_CONN_SDHC_1 {
+				reg = <SC_R_SDHC_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+			};
+			pd_conn_sdch2: PD_CONN_SDHC_2 {
+				reg = <SC_R_SDHC_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+			};
+			pd_conn_enet0: PD_CONN_ENET_0 {
+				reg = <SC_R_ENET_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+                                wakeup-irq = <258>;
+			};
+			pd_conn_enet1: PD_CONN_ENET_1 {
+				reg = <SC_R_ENET_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+                                fsl,wakeup_irq = <262>;
+			};
+			pd_conn_nand: PD_CONN_NAND {
+				reg = <SC_R_NAND>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+			};
+		};
+
+		pd_audio: PD_AUDIO {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_NONE>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_audio_pll0: PD_AUD_AUDIO_PLL_0 {
+				reg = <SC_R_AUDIO_PLL_0>;
+				power-domains =<&pd_audio>;
+				#power-domain-cells = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_audio_pll1: PD_AUD_AUDIO_PLL_1 {
+					reg = <SC_R_AUDIO_PLL_1>;
+					power-domains =<&pd_audio_pll0>;
+					#power-domain-cells = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_audio_clk0: PD_AUD_AUDIO_CLK_0 {
+						reg = <SC_R_AUDIO_CLK_0>;
+						power-domains =<&pd_audio_pll1>;
+						#power-domain-cells = <0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						pd_audio_clk1: PD_AUD_AUDIO_CLK_1 {
+							reg = <SC_R_AUDIO_CLK_1>;
+							#power-domain-cells = <0>;
+							power-domains =<&pd_audio_clk0>;
+							#address-cells = <1>;
+							#size-cells = <0>;
+
+							pd_dma0_chan0: PD_ASRC_0_RXA {
+								reg = <SC_R_DMA_0_CH0>;
+								power-domains =<&pd_audio_clk1>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma0_chan1: PD_ASRC_0_RXB {
+								reg = <SC_R_DMA_0_CH1>;
+								power-domains =<&pd_dma0_chan0>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma0_chan2: PD_ASRC_0_RXC {
+								reg = <SC_R_DMA_0_CH2>;
+								power-domains =<&pd_dma0_chan1>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma0_chan3: PD_ASRC_0_TXA {
+								reg = <SC_R_DMA_0_CH3>;
+								power-domains =<&pd_dma0_chan2>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma0_chan4: PD_ASRC_0_TXB {
+								reg = <SC_R_DMA_0_CH4>;
+								power-domains =<&pd_dma0_chan3>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma0_chan5: PD_ASRC_0_TXC {
+								reg = <SC_R_DMA_0_CH5>;
+								power-domains =<&pd_dma0_chan4>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+								pd_asrc0:PD_AUD_ASRC_0 {
+									reg = <SC_R_ASRC_0>;
+									#power-domain-cells = <0>;
+									power-domains =<&pd_dma0_chan5>;
+								};
+							};
+							};
+							};
+							};
+							};
+							};
+
+							pd_dma0_chan8: PD_SPDIF_0_RX {
+								reg = <SC_R_DMA_0_CH8>;
+								power-domains =<&pd_audio_clk1>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma0_chan9: PD_SPDIF_0_TX {
+								reg = <SC_R_DMA_0_CH9>;
+								power-domains =<&pd_dma0_chan8>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+								pd_spdif0: PD_AUD_SPDIF_0 {
+									reg = <SC_R_SPDIF_0>;
+									#power-domain-cells = <0>;
+									power-domains =<&pd_dma0_chan9>;
+
+								};
+							};
+							};
+							pd_dma0_chan12: PD_SAI_0_RX {
+								reg = <SC_R_DMA_0_CH12>;
+								power-domains =<&pd_audio_clk1>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma0_chan13: PD_SAI_0_TX {
+								reg = <SC_R_DMA_0_CH13>;
+								power-domains =<&pd_dma0_chan12>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+								pd_sai0:PD_AUD_SAI_0 {
+									reg = <SC_R_SAI_0>;
+									#power-domain-cells = <0>;
+									power-domains =<&pd_dma0_chan13>;
+								};
+							};
+
+							};
+							pd_dma0_chan14: PD_SAI_1_RX {
+								reg = <SC_R_DMA_0_CH14>;
+								power-domains =<&pd_audio_clk1>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+							pd_dma0_chan15: PD_SAI_1_TX {
+								reg = <SC_R_DMA_0_CH15>;
+								power-domains =<&pd_dma0_chan14>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+								pd_sai1: PD_AUD_SAI_1 {
+									reg = <SC_R_SAI_1>;
+									#power-domain-cells = <0>;
+									power-domains =<&pd_dma0_chan15>;
+								};
+							};
+							};
+							pd_dma0_chan16: PD_SAI_2_RX {
+								reg = <SC_R_DMA_0_CH16>;
+								power-domains =<&pd_audio_clk1>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+								pd_sai2: PD_AUD_SAI_2 {
+									reg = <SC_R_SAI_2>;
+									#power-domain-cells = <0>;
+									power-domains =<&pd_dma0_chan16>;
+								};
+							};
+							pd_dma0_chan17: PD_SAI_3_RX {
+								reg = <SC_R_DMA_0_CH17>;
+								power-domains =<&pd_audio_clk1>;
+								#power-domain-cells = <0>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+								pd_sai3: PD_AUD_SAI_3 {
+									reg = <SC_R_SAI_3>;
+									#power-domain-cells = <0>;
+									power-domains =<&pd_dma0_chan17>;
+								};
+							};
+							pd_gpt5: PD_AUD_GPT_5 {
+								reg = <SC_R_GPT_5>;
+								#power-domain-cells = <0>;
+								power-domains =<&pd_audio_clk1>;
+							};
+							pd_gpt6: PD_AUD_GPT_6 {
+								reg = <SC_R_GPT_6>;
+								#power-domain-cells = <0>;
+								power-domains =<&pd_audio_clk1>;
+							};
+							pd_gpt7: PD_AUD_GPT_7 {
+								reg = <SC_R_GPT_7>;
+								#power-domain-cells = <0>;
+								power-domains =<&pd_audio_clk1>;
+							};
+							pd_gpt8: PD_AUD_GPT_8 {
+								reg = <SC_R_GPT_8>;
+								#power-domain-cells = <0>;
+								power-domains =<&pd_audio_clk1>;
+							};
+							pd_mqs0: PD_AUD_MQS_0 {
+								reg = <SC_R_MQS_0>;
+								#power-domain-cells = <0>;
+								power-domains =<&pd_audio_clk1>;
+							};
+							pd_mclk_out0: PD_AUD_MCLK_OUT_0 {
+								reg = <SC_R_MCLK_OUT_0>;
+								#power-domain-cells = <0>;
+								power-domains =<&pd_audio_clk1>;
+							};
+							pd_mclk_out1: PD_AUD_MCLK_OUT_1 {
+								reg = <SC_R_MCLK_OUT_1>;
+								#power-domain-cells = <0>;
+								power-domains =<&pd_audio_clk1>;
+							};
+						};
+					};
+				};
+			};
+		};
+
+		pd_dma: PD_DMA {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_NONE>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_dma_elcdif_pll: PD_DMA_ELCDIF_PLL {
+				reg = <SC_R_ELCDIF_PLL>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_dma_lcd0: PD_DMA_LCD_0 {
+					reg = <SC_R_LCD_0>;
+					#power-domain-cells = <0>;
+					power-domains = <&pd_dma_elcdif_pll>;
+				};
+			};
+			pd_dma_flexcan0: PD_DMA_CAN_0 {
+				reg = <SC_R_CAN_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+				wakeup-irq = <235>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_dma_flexcan1: PD_DMA_CAN_1 {
+					reg = <SC_R_CAN_1>;
+					#power-domain-cells = <0>;
+					power-domains = <&pd_dma_flexcan0>;
+					wakeup-irq = <236>;
+				};
+
+				pd_dma_flexcan2: PD_DMA_CAN_2 {
+					reg = <SC_R_CAN_2>;
+					#power-domain-cells = <0>;
+					power-domains = <&pd_dma_flexcan0>;
+					wakeup-irq = <237>;
+				};
+			};
+
+			pd_dma_ftm0: PD_DMA_FTM_0 {
+				reg = <SC_R_FTM_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_ftm1: PD_DMA_FTM_1 {
+				reg = <SC_R_FTM_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_adc0: PD_DMA_ADC_0 {
+				reg = <SC_R_ADC_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpi2c0: PD_DMA_I2C_0 {
+				reg = <SC_R_I2C_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpi2c1: PD_DMA_I2C_1 {
+				reg = <SC_R_I2C_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpi2c2:PD_DMA_I2C_2 {
+				reg = <SC_R_I2C_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpi2c3: PD_DMA_I2C_3 {
+				reg = <SC_R_I2C_3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpuart0: PD_DMA_UART0 {
+				reg = <SC_R_UART_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+				wakeup-irq = <345>;
+			};
+			pd_dma_lpuart1: PD_DMA_UART1 {
+				reg = <SC_R_UART_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				wakeup-irq = <346>;
+
+				pd_dma2_chan10: PD_UART1_RX {
+					reg = <SC_R_DMA_2_CH10>;
+					power-domains =<&pd_dma_lpuart1>;
+					#power-domain-cells = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_dma2_chan11: PD_UART1_TX {
+						reg = <SC_R_DMA_2_CH11>;
+						power-domains =<&pd_dma2_chan10>;
+						#power-domain-cells = <0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+					};
+				};
+			};
+			pd_dma_lpuart2: PD_DMA_UART2 {
+				reg = <SC_R_UART_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				wakeup-irq = <347>;
+
+				pd_dma2_chan12: PD_UART2_RX {
+					reg = <SC_R_DMA_2_CH12>;
+					power-domains =<&pd_dma_lpuart2>;
+					#power-domain-cells = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_dma2_chan13: PD_UART2_TX {
+						reg = <SC_R_DMA_2_CH13>;
+						power-domains =<&pd_dma2_chan12>;
+						#power-domain-cells = <0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+					};
+				};
+			};
+			pd_dma_lpuart3: PD_DMA_UART3 {
+				reg = <SC_R_UART_3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				wakeup-irq = <348>;
+
+				pd_dma3_chan14: PD_UART3_RX {
+					reg = <SC_R_DMA_2_CH14>;
+					power-domains =<&pd_dma_lpuart3>;
+					#power-domain-cells = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_dma3_chan15: PD_UART3_TX {
+						reg = <SC_R_DMA_2_CH15>;
+						power-domains =<&pd_dma3_chan14>;
+						#power-domain-cells = <0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+					};
+				};
+			};
+			pd_dma_lpspi0: PD_DMA_SPI_0 {
+				reg = <SC_R_SPI_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpspi1: PD_DMA_SPI_1 {
+				reg = <SC_R_SPI_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpspi2: PD_DMA_SPI_2 {
+				reg = <SC_R_SPI_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpspi3: PD_DMA_SPI_3 {
+				reg = <SC_R_SPI_3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_pwm0: PD_DMA_PWM_0 {
+				reg = <SC_R_LCD_0_PWM_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+		};
+
+		pd_hsio: hsio-power-domain {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_NONE>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_hsio_gpio: PD_HSIO_GPIO {
+				reg = <SC_R_HSIO_GPIO>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_hsio>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_serdes1: PD_HSIO_SERDES_1 {
+					reg = <SC_R_SERDES_1>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_hsio_gpio>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_pcie: PD_HSIO_PCIE_B {
+						reg = <SC_R_PCIE_B>;
+						#power-domain-cells = <0>;
+						power-domains =<&pd_serdes1>;
+					};
+				};
+			};
+		};
+
+		pd_cm40: PD_CM40 {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_NONE>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_cm40_i2c: PD_CM40_I2C {
+				reg = <SC_R_M4_0_I2C>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_cm40>;
+			};
+
+			pd_cm40_intmux: PD_CM40_INTMUX {
+				reg = <SC_R_M4_0_INTMUX>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_cm40>;
+			};
+		};
+
+		pd_caam: PD_CAAM {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_NONE>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_caam_jr1: PD_CAAM_JR1 {
+				reg = <SC_R_CAAM_JR1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_caam>;
+			};
+			pd_caam_jr2: PD_CAAM_JR2 {
+				reg = <SC_R_CAAM_JR2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_caam>;
+			};
+			pd_caam_jr3: PD_CAAM_JR3 {
+				reg = <SC_R_CAAM_JR3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_caam>;
+			};
+		};
+	};
+
+	tsens: thermal-sensor {
+		compatible = "nxp,imx8qxp-sc-tsens";
+		u-boot,dm-pre-reloc;
+		/* number of the temp sensor on the chip */
+		tsens-num = <2>;
+		#thermal-sensor-cells = <1>;
+	};
+
+	thermal_zones: thermal-zones {
+		/* cpu thermal */
+		cpu-thermal0 {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			/*the slope and offset of the temp sensor */
+			thermal-sensors = <&tsens 0>;
+			trips {
+				cpu_alert0: trip0 {
+					temperature = <107000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit0: trip1 {
+					temperature = <127000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert0>;
+					cooling-device =
+					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		drc-thermal0 {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			thermal-sensors = <&tsens 1>;
+			status = "disabled";
+			trips {
+				drc_alert0: trip0 {
+					temperature = <107000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				drc_crit0: trip1 {
+					temperature = <127000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
+	intmux_cm40: intmux@37400000 {
+		compatible = "nxp,imx-intmux";
+		reg = <0x0 0x37400000 0x0 0x1000>;
+		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#interrupt-cells = <2>;
+		clocks = <&clk IMX8QXP_CM40_IPG_CLK>;
+		clock-names = "ipg";
+		power-domains = <&pd_cm40_intmux>;
+		status = "disabled";
+	};
+
+	i2c0_cm40: i2c@37230000 {
+		compatible = "fsl,imx8qm-lpi2c";
+		reg = <0x0 0x37230000 0x0 0x1000>;
+		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&intmux_cm40>;
+		clocks = <&clk IMX8QXP_CM40_I2C_CLK>,
+			<&clk IMX8QXP_CM40_I2C_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_CM40_I2C_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_cm40_i2c>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	adma_lcdif: lcdif@5a180000 {
+		compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif";
+		reg = <0x0 0x5a180000 0x0 0x10000>;
+		clocks = <&clk IMX8QXP_LCD_DIV>,
+			 <&clk IMX8QXP_LCD_PXL_DIV>,
+			 <&clk IMX8QXP_LCD_IPG_CLK>;
+		clock-names = "pix", "disp_axi", "axi";
+		assigned-clocks = <&clk IMX8QXP_LCD_SEL>,
+				  <&clk IMX8QXP_LCD_PXL_SEL>,
+				  <&clk IMX8QXP_ELCDIF_PLL_DIV>;
+		assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL_DIV>,
+					 <&clk IMX8QXP_LCD_PXL_BYPASS_DIV>;
+		assigned-clock-rates = <0>, <0>, <804000000>;
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&pd_dma_lcd0>;
+		status = "disabled";
+	};
+
+	pwm_adma_lcdif: pwm@5a190000 {
+		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+		reg = <0x0 0x5a190000 0 0x1000>;
+		clocks = <&clk IMX8QXP_PWM_IPG_CLK>,
+			 <&clk IMX8QXP_PWM_CLK>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX8QXP_PWM_CLK>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <2>;
+		power-domains = <&pd_dma_pwm0>;
+		status = "disabled";
+	};
+
+	i2c_rpbus_1: i2c-rpbus-1 {
+		compatible = "fsl,i2c-rpbus";
+		status = "disabled";
+	};
+
+	i2c_rpbus_5: i2c-rpbus-5 {
+		compatible = "fsl,i2c-rpbus";
+		status = "disabled";
+	};
+
+	i2c_rpbus_12: i2c-rpbus-12 {
+		compatible = "fsl,i2c-rpbus";
+		status = "disabled";
+	};
+
+	i2c_rpbus_13: i2c-rpbus-13 {
+		compatible = "fsl,i2c-rpbus";
+		status = "disabled";
+	};
+
+	i2c_rpbus_14: i2c-rpbus-14 {
+		compatible = "fsl,i2c-rpbus";
+		status = "disabled";
+	};
+
+	i2c_rpbus_15: i2c-rpbus-15 {
+		compatible = "fsl,i2c-rpbus";
+		status = "disabled";
+	};
+
+	adc0: adc@5a880000 {
+		compatible = "fsl,imx8qxp-adc";
+		reg = <0x0 0x5a880000 0x0 0x10000>;
+		interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QXP_ADC0_CLK>,
+			 <&clk IMX8QXP_ADC0_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_ADC0_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_dma_adc0>;
+		status = "disabled";
+	};
+
+	i2c0: i2c@5a800000 {
+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x0 0x5a800000 0x0 0x4000>;
+		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QXP_I2C0_CLK>,
+			<&clk IMX8QXP_I2C0_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_dma_lpi2c0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c1: i2c@5a810000 {
+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x0 0x5a810000 0x0 0x4000>;
+		interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QXP_I2C1_CLK>,
+			<&clk IMX8QXP_I2C1_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_I2C1_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_dma_lpi2c1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@5a820000 {
+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x0 0x5a820000 0x0 0x4000>;
+		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QXP_I2C2_CLK>,
+			<&clk IMX8QXP_I2C2_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_dma_lpi2c2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c3: i2c@5a830000 {
+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x0 0x5a830000 0x0 0x4000>;
+		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QXP_I2C3_CLK>,
+			<&clk IMX8QXP_I2C3_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_I2C3_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_dma_lpi2c3>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	usbphy1: usbphy@0x5b100000 {
+		compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
+		reg = <0x0 0x5b100000 0x0 0x1000>;
+		clocks = <&clk IMX8QXP_USB2_PHY_IPG_CLK>;
+		power-domains = <&pd_conn_usbotg0_phy>;
+	};
+
+	usbphy2: usbphy@0x5b110000 {
+		compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
+		reg = <0x0 0x5b110000 0x0 0x1000>;
+		clocks = <&clk IMX8DXL_USB2_PHY2_IPG_CLK>;
+		power-domains = <&pd_conn_usbotg1_phy>;
+	};
+
+	usbmisc1: usbmisc@5b0d0200 {
+		#index-cells = <1>;
+		compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc";
+		reg = <0x0 0x5b0d0200 0x0 0x200>;
+	};
+
+	usbmisc2: usbmisc@5b0e0200 {
+		#index-cells = <1>;
+		compatible = "fsl,imx8dxl-usbmisc", "fsl,imx7ulp-usbmisc";
+		reg = <0x0 0x5b0e0200 0x0 0x200>;
+	};
+
+	usbotg1: usb@5b0d0000 {
+		compatible = "fsl,imx8qm-usb", "fsl,imx27-usb";
+		reg = <0x0 0x5b0d0000 0x0 0x200>;
+		interrupt-parent = <&wu>;
+		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,usbphy = <&usbphy1>;
+		fsl,usbmisc = <&usbmisc1 0>;
+		clocks = <&clk IMX8QXP_CLK_DUMMY>;
+		ahb-burst-config = <0x0>;
+		tx-burst-size-dword = <0x10>;
+		rx-burst-size-dword = <0x10>;
+		#stream-id-cells = <1>;
+		power-domains = <&pd_conn_usbotg0>;
+		status = "disabled";
+	};
+
+	usbotg2: usb@5b0e0000 {
+		compatible = "fsl,imx8qm-usb", "fsl,imx27-usb";
+		reg = <0x0 0x5b0e0000 0x0 0x200>;
+		interrupt-parent = <&wu>;
+		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,usbphy = <&usbphy2>;
+		fsl,usbmisc = <&usbmisc2 0>;
+		clocks = <&clk IMX8QXP_CLK_DUMMY>;
+		ahb-burst-config = <0x0>;
+		tx-burst-size-dword = <0x10>;
+		rx-burst-size-dword = <0x10>;
+		#stream-id-cells = <1>;
+		power-domains = <&pd_conn_usbotg1>;
+		status = "disabled";
+	};
+
+	flexcan1: can@5a8d0000 {
+		compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
+		reg = <0x0 0x5a8d0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wu>;
+		clocks = <&clk IMX8QXP_CAN0_IPG_CLK>,
+			 <&clk IMX8QXP_CAN0_CLK>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
+		assigned-clock-rates = <40000000>;
+		power-domains = <&pd_dma_flexcan0>;
+		/* SLSlice[4] */
+		clk-src = <0>;
+		status = "disabled";
+	};
+
+	flexcan2: can@5a8e0000 {
+		compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
+		reg = <0x0 0x5a8e0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wu>;
+		/* CAN0 clock and PD is shared among all CAN instances */
+		clocks = <&clk IMX8QXP_CAN0_IPG_CLK>,
+			 <&clk IMX8QXP_CAN0_CLK>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
+		assigned-clock-rates = <40000000>;
+		power-domains = <&pd_dma_flexcan1>;
+		/* SLSlice[4] */
+		clk-src = <0>;
+		status = "disabled";
+	};
+
+	flexcan3: can@5a8f0000 {
+		compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
+		reg = <0x0 0x5a8f0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wu>;
+		/* CAN0 clock and PD is shared among all CAN instances */
+		clocks = <&clk IMX8QXP_CAN0_IPG_CLK>,
+			 <&clk IMX8QXP_CAN0_CLK>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
+		assigned-clock-rates = <40000000>;
+		power-domains = <&pd_dma_flexcan2>;
+		/* SLSlice[4] */
+		clk-src = <0>;
+		status = "disabled";
+	};
+
+	dma_apbh: dma-apbh@5b810000 {
+		compatible = "fsl,imx28-dma-apbh";
+		reg = <0x0 0x5b810000 0x0 0x2000>;
+		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+		#dma-cells = <1>;
+		dma-channels = <4>;
+		clocks = <&clk IMX8QXP_APBHDMA_CLK>;
+		power-domains = <&pd_conn_nand>;
+	};
+
+	gpmi: gpmi-nand@5b812000{
+		compatible = "fsl,imx8qxp-gpmi-nand";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x0 0x5b812000 0x0 0x2000>, <0x0 0x5b814000 0x0 0x2000>;
+		reg-names = "gpmi-nand", "bch";
+		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "bch";
+		clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>,
+			<&clk IMX8QXP_GPMI_APB_CLK>,
+			<&clk IMX8QXP_GPMI_BCH_CLK>,
+			<&clk IMX8QXP_GPMI_APB_BCH_CLK>,
+			<&clk IMX8QXP_APBHDMA_CLK>;
+		clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_apb_bch", "gpmi_apbh_dma";
+		dmas = <&dma_apbh 0>;
+		dma-names = "rx-tx";
+		power-domains = <&pd_conn_nand>;
+		assigned-clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>;
+		assigned-clock-rates = <50000000>;
+		status = "disabled";
+	};
+
+	wu: wu {
+		compatible = "fsl,imx8-wu";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		interrupt-parent = <&gic>;
+	};
+
+	gpio0: gpio@5d080000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d080000 0x0 0x10000>;
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+                power-domains = <&pd_lsio_gpio0>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio1: gpio@5d090000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d090000 0x0 0x10000>;
+		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+                power-domains = <&pd_lsio_gpio1>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio2: gpio@5d0a0000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d0a0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+                power-domains = <&pd_lsio_gpio2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio3: gpio@5d0b0000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d0b0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+                power-domains = <&pd_lsio_gpio3>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio4: gpio@5d0c0000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d0c0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		power-domains = <&pd_lsio_gpio4>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio5: gpio@5d0d0000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d0d0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+                power-domains = <&pd_lsio_gpio5>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio6: gpio@5d0e0000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d0e0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+                power-domains = <&pd_lsio_gpio6>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio7: gpio@5d0f0000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d0f0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+                power-domains = <&pd_lsio_gpio7>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	ddr_pmu0: ddr_pmu@5c020000 {
+		compatible = "fsl,imx8-ddr-pmu";
+		reg = <0x0 0x5c020000 0x0 0x10000>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	lpspi0: lpspi@5a000000 {
+		compatible = "fsl,imx7ulp-spi";
+		reg = <0x0 0x5a000000 0x0 0x10000>;
+		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QXP_SPI0_CLK>,
+			 <&clk IMX8QXP_SPI0_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_SPI0_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma_lpspi0>;
+		status = "disabled";
+	};
+
+	lpspi1: lpspi@5a010000 {
+		compatible = "fsl,imx7ulp-spi";
+		reg = <0x0 0x5a010000 0x0 0x10000>;
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QXP_SPI1_CLK>,
+			 <&clk IMX8QXP_SPI1_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_SPI1_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma_lpspi1>;
+		status = "disabled";
+	};
+
+	lpspi2: lpspi@5a020000 {
+		compatible = "fsl,imx7ulp-spi";
+		reg = <0x0 0x5a020000 0x0 0x10000>;
+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QXP_SPI2_CLK>,
+			 <&clk IMX8QXP_SPI2_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_SPI2_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma_lpspi2>;
+		status = "disabled";
+	};
+
+	lpspi3: lpspi@5a030000 {
+		compatible = "fsl,imx7ulp-spi";
+		reg = <0x0 0x5a030000 0x0 0x10000>;
+		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QXP_SPI3_CLK>,
+			 <&clk IMX8QXP_SPI3_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_SPI3_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma_lpspi3>;
+		status = "disabled";
+	};
+
+	lpuart0: serial@5a060000 {
+		compatible = "fsl,imx8qm-lpuart";
+		reg = <0x0 0x5a060000 0x0 0x1000>;
+		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wu>;
+		clocks = <&clk IMX8QXP_UART0_CLK>,
+			 <&clk IMX8QXP_UART0_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_UART0_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma_lpuart0>;
+		status = "disabled";
+	};
+
+	lpuart1: serial@5a070000 {
+		compatible = "fsl,imx8qm-lpuart";
+		reg = <0x0 0x5a070000 0x0 0x1000>;
+		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wu>;
+		clocks = <&clk IMX8QXP_UART1_CLK>,
+			<&clk IMX8QXP_UART1_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_UART1_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma2_chan11>;
+		dma-names = "tx","rx";
+		dmas = <&edma2 11 0 0>,
+			<&edma2 10 0 1>;
+		status = "disabled";
+	};
+
+	lpuart2: serial@5a080000 {
+		compatible = "fsl,imx8qm-lpuart";
+		reg = <0x0 0x5a080000 0x0 0x1000>;
+		interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wu>;
+		clocks = <&clk IMX8QXP_UART2_CLK>,
+			<&clk IMX8QXP_UART2_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_UART2_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma2_chan13>;
+		dma-names = "tx","rx";
+		dmas = <&edma2 13 0 0>,
+			<&edma2 12 0 1>;
+		status = "disabled";
+	};
+
+	lpuart3: serial@5a090000 {
+		compatible = "fsl,imx8qm-lpuart";
+		reg = <0x0 0x5a090000 0x0 0x1000>;
+		interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wu>;
+		clocks = <&clk IMX8QXP_UART3_CLK>,
+			<&clk IMX8QXP_UART3_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QXP_UART3_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma3_chan15>;
+		dma-names = "tx","rx";
+		dmas = <&edma2 15 0 0>,
+			<&edma2 14 0 1>;
+		status = "disabled";
+	};
+
+	edma2: dma-controller@5a1f0000 {
+		compatible = "fsl,imx8qm-edma";
+		reg = <0x0 0x5a280000 0x0 0x10000>, /* channel8 UART0 rx */
+		      <0x0 0x5a290000 0x0 0x10000>, /* channel9 UART0 tx */
+		      <0x0 0x5a2a0000 0x0 0x10000>, /* channel10 UART1 rx */
+		      <0x0 0x5a2b0000 0x0 0x10000>, /* channel11 UART1 tx */
+		      <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART2 rx */
+		      <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART2 tx */
+		      <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART3 rx */
+		      <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART3 tx */
+		#dma-cells = <3>;
+		dma-channels = <8>;
+		interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx",
+				  "edma2-chan10-rx", "edma2-chan11-tx",
+				  "edma2-chan12-rx", "edma2-chan13-tx",
+				  "edma2-chan14-rx", "edma2-chan15-tx";
+		status = "okay";
+	};
+
+	edma0: dma-controller@591F0000 {
+		compatible = "fsl,imx8qm-edma";
+		reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */
+			<0x0 0x59210000 0x0 0x10000>,
+			<0x0 0x59220000 0x0 0x10000>,
+			<0x0 0x59230000 0x0 0x10000>,
+			<0x0 0x59240000 0x0 0x10000>,
+			<0x0 0x59250000 0x0 0x10000>,
+			<0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */
+			<0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */
+			<0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */
+			<0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */
+			<0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */
+			<0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */
+			<0x0 0x59350000 0x0 0x10000>,
+			<0x0 0x59370000 0x0 0x10000>;
+		#dma-cells = <3>;
+		shared-interrupt;
+		dma-channels = <16>;
+		interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */
+				<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
+				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
+				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
+				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */
+				"edma0-chan2-rx", "edma0-chan3-tx",
+				"edma0-chan4-tx", "edma0-chan5-tx",
+				"edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */
+				"edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */
+				"edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */
+				"edma0-chan21-tx",		/* gpt0 */
+				"edma0-chan23-rx";		/* gpt2 */
+		status = "okay";
+	};
+	acm: acm@59e00000 {
+		compatible = "nxp,imx8qm-acm";
+		reg = <0x0 0x59e00000 0x0 0x1D0000>;
+		status = "disabled";
+	};
+
+	sai0: sai@59040000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x0 0x59040000 0x0 0x10000>;
+		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_AUD_SAI_0_IPG>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_AUD_SAI_0_MCLK>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "rx", "tx";
+		dmas = <&edma0 12 0 1>, <&edma0 13 0 0>;
+		status = "disabled";
+		power-domains = <&pd_sai0>;
+	};
+
+	sai1: sai@59050000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x0 0x59050000 0x0 0x10000>;
+		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_AUD_SAI_1_IPG>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_AUD_SAI_1_MCLK>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "rx", "tx";
+		dmas = <&edma0 14 0 1>, <&edma0 15 0 0>;
+		status = "disabled";
+		power-domains = <&pd_sai1>;
+	};
+
+	sai2: sai@59060000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x0 0x59060000 0x0 0x10000>;
+		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_AUD_SAI_2_IPG>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_AUD_SAI_2_MCLK>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "rx";
+		dmas = <&edma0 16 0 1>;
+		status = "disabled";
+		power-domains = <&pd_sai2>;
+	};
+
+	sai3: sai@59070000 {
+		compatible = "fsl,imx8qm-sai";
+		reg = <0x0 0x59070000 0x0 0x10000>;
+		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_AUD_SAI_3_IPG>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_AUD_SAI_3_MCLK>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>;
+		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+		dma-names = "rx";
+		dmas = <&edma0 17 0 1>;
+		status = "disabled";
+		power-domains = <&pd_sai3>;
+	};
+
+	asrc0: asrc@59000000 {
+		compatible = "fsl,imx8qm-asrc0";
+		reg = <0x0 0x59000000 0x0 0x10000>;
+		interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_AUD_ASRC_0_IPG>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>,
+			<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>,
+			<&clk IMX8QXP_ACM_AUD_CLK0_SEL>,
+			<&clk IMX8QXP_ACM_AUD_CLK1_SEL>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>,
+			<&clk IMX8QXP_CLK_DUMMY>;
+		clock-names = "ipg", "mem",
+			"asrck_0", "asrck_1", "asrck_2", "asrck_3",
+			"asrck_4", "asrck_5", "asrck_6", "asrck_7",
+			"asrck_8", "asrck_9", "asrck_a", "asrck_b",
+			"asrck_c", "asrck_d", "asrck_e", "asrck_f",
+			"spba";
+		dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>,
+			<&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>;
+		dma-names = "rxa", "rxb", "rxc",
+				"txa", "txb", "txc";
+		fsl,asrc-rate  = <8000>;
+		fsl,asrc-width = <16>;
+		power-domains = <&pd_asrc0>;
+		status = "disabled";
+	};
+
+	mqs: mqs@59850000 {
+		compatible = "fsl,imx8qm-mqs";
+		reg = <0x0 0x59850000 0x0 0x10000>;
+		clocks = <&clk IMX8QXP_AUD_MQS_IPG>,
+			<&clk IMX8QXP_AUD_MQS_HMCLK>;
+		clock-names = "core", "mclk";
+		power-domains = <&pd_mqs0>;
+		status = "disabled";
+	};
+
+	usdhc1: usdhc@5b010000 {
+		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x0 0x5b010000 0x0 0x10000>;
+		clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>,
+			<&clk IMX8QXP_SDHC0_CLK>,
+			<&clk IMX8QXP_SDHC0_AHB_CLK>;
+		clock-names = "ipg", "per", "ahb";
+		assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>;
+		assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
+		assigned-clock-rates = <0>, <400000000>;
+		power-domains = <&pd_conn_sdch0>;
+		fsl,tuning-start-tap = <20>;
+		fsl,tuning-step= <2>;
+		status = "disabled";
+	};
+
+	usdhc2: usdhc@5b020000 {
+		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x0 0x5b020000 0x0 0x10000>;
+		clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>,
+			<&clk IMX8QXP_SDHC1_CLK>,
+			<&clk IMX8QXP_SDHC1_AHB_CLK>;
+		clock-names = "ipg", "per", "ahb";
+		assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>;
+		assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
+		assigned-clock-rates = <0>, <200000000>;
+		power-domains = <&pd_conn_sdch1>;
+		fsl,tuning-start-tap = <20>;
+		fsl,tuning-step= <2>;
+		status = "disabled";
+	};
+
+	usdhc3: usdhc@5b030000 {
+		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x0 0x5b030000 0x0 0x10000>;
+		clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>,
+			<&clk IMX8QXP_SDHC2_CLK>,
+			<&clk IMX8QXP_SDHC2_AHB_CLK>;
+		clock-names = "ipg", "per", "ahb";
+		assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>;
+		assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
+		assigned-clock-rates = <0>, <200000000>;
+		power-domains = <&pd_conn_sdch2>;
+		status = "disabled";
+	};
+
+	fec1: ethernet@5b040000 {
+		compatible = "fsl,imx8qm-fec";
+		reg = <0x0 0x5b040000 0x0 0x10000>;
+		interrupt-parent = <&wu>;
+		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, <&clk IMX8QXP_ENET0_RGMII_TX_CLK>,
+			<&clk IMX8QXP_ENET0_PTP_CLK>, <&clk IMX8QXP_ENET0_TX_CLK>;
+		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
+		assigned-clocks = <&clk IMX8QXP_ENET0_ROOT_DIV>,
+				  <&clk IMX8QXP_ENET0_REF_DIV>;
+		assigned-clock-rates = <250000000>, <125000000>;
+		fsl,num-tx-queues=<3>;
+		fsl,num-rx-queues=<3>;
+                fsl,wakeup_irq = <0>;
+		power-domains = <&pd_conn_enet0>;
+		status = "disabled";
+	};
+
+	eqos: ethernet@5b050000 {
+		compatible = "fsl,imx-eqos";
+		reg = <0x0 0x5b050000 0x0 0x10000>;
+		interrupt-parent = <&wu>;
+		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8DXL_EQOS_ACLK>, <&clk IMX8DXL_EQOS_CSR_CLK>, <&clk IMX8DXL_EQOS_CLK>,
+			<&clk IMX8DXL_EQOS_PTP_CLK>;
+		clock-names = "aclk", "csr", "tx_clk", "ptp";
+		assigned-clocks = <&clk IMX8QXP_ENET1_ROOT_DIV>;
+		assigned-clock-rates = <125000000>;
+		power-domains = <&pd_conn_enet1>;
+		status = "disabled";
+	};
+
+	gpt0: gpt0@5d140000 {
+		compatible = "fsl,imx8qxp-gpt";
+		reg = <0x0 0x5d140000 0x0 0x4000>;
+		interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_CLK_DUMMY>, <&clk IMX8QXP_GPT_3M>;
+		clock-names = "ipg", "per";
+		power-domains = <&pd_lsio_gpt0>;
+	};
+
+	spdif0: spdif@59020000 {
+		compatible = "fsl,imx8qm-spdif";
+		reg = <0x0 0x59020000 0x0 0x10000>;
+		interrupts =  <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* rx */
+			     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* tx */
+		clocks = <&clk IMX8QXP_AUD_SPDIF_0_GCLKW>, /* core */
+			<&clk IMX8QXP_CLK_DUMMY>, /* rxtx0 */
+			<&clk IMX8QXP_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */
+			<&clk IMX8QXP_CLK_DUMMY>, /* rxtx2 */
+			<&clk IMX8QXP_CLK_DUMMY>, /* rxtx3 */
+			<&clk IMX8QXP_CLK_DUMMY>, /* rxtx4 */
+			<&clk IMX8QXP_IPG_AUD_CLK_ROOT>, /* rxtx5 */
+			<&clk IMX8QXP_CLK_DUMMY>, /* rxtx6 */
+			<&clk IMX8QXP_CLK_DUMMY>, /* rxtx7 */
+			<&clk IMX8QXP_CLK_DUMMY>; /* spba */
+		clock-names = "core", "rxtx0",
+			      "rxtx1", "rxtx2",
+			      "rxtx3", "rxtx4",
+			      "rxtx5", "rxtx6",
+			      "rxtx7", "spba";
+		dmas = <&edma0 8 0 5>, <&edma0 9 0 4>;
+		dma-names = "rx", "tx";
+		power-domains = <&pd_spdif0>;
+		status = "disabled";
+	};
+
+	flexspi0: flexspi@05d120000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nxp,imx8dxl-fspi";
+		reg = <0x0 0x5d120000 0x0 0x10000>, <0x0 0x08000000 0x0 0x10000000>;
+		reg-names = "fspi_base", "fspi_mmap";
+		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QXP_LSIO_FSPI0_CLK>,
+			<&clk IMX8QXP_LSIO_FSPI0_CLK>;
+		assigned-clocks = <&clk IMX8QXP_LSIO_FSPI0_DIV>;
+		assigned-clock-rates = <29000000>;
+		clock-names = "fspi", "fspi_en";
+		power-domains = <&pd_lsio_flexspi0>;
+		status = "disabled";
+	};
+
+	dma_cap: dma_cap {
+		compatible = "dma-capability";
+		only-dma-mask32 = <1>;
+	};
+
+	hsio: hsio@5f080000 {
+		compatible = "fsl,imx8qm-hsio", "syscon";
+		reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */
+	};
+
+	ocotp: ocotp {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,imx8qxp-ocotp", "syscon";
+	};
+
+	pcieb: pcie@0x5f010000 {
+		/*
+		 * pcieb phyx1 lane1 in default, adjust it refer to the
+		 * exact hw design.
+		 */
+		compatible = "fsl,imx8qxp-pcie","snps,dw-pcie";
+		reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg*/
+		      <0x0 0x7ff00000 0x0 0x80000>; /* PCI cfg space */
+		reg-names = "dbi", "config";
+		reserved-region = <&rpmsg_reserved>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */
+			  0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */
+		num-lanes = <1>;
+
+		#interrupt-cells = <1>;
+		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+		interrupt-names = "msi";
+
+		/*
+		 * Set these clocks in default, then clocks should be
+		 * refined for exact hw design of imx8 pcie.
+		 */
+		clocks = <&clk IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK>,
+			 <&clk IMX8QXP_HSIO_PCIE_SLV_AXI_CLK>,
+			 <&clk IMX8QXP_HSIO_PHY_X1_PCLK>,
+			 <&clk IMX8QXP_HSIO_PCIE_X1_PER_CLK>,
+			 <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>,
+			 <&clk IMX8QXP_HSIO_PHY_X1_PER_CLK>,
+			 <&clk IMX8QXP_HSIO_MISC_PER_CLK>;
+		clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi",
+					"phy_per", "misc_per";
+		interrupt-map-mask = <0 0 0 0x7>;
+		interrupt-map =  <0 0 0 1 &gic 0 105 4>,
+				 <0 0 0 2 &gic 0 106 4>,
+				 <0 0 0 3 &gic 0 107 4>,
+				 <0 0 0 4 &gic 0 108 4>;
+		power-domains = <&pd_pcie>;
+		fsl,max-link-speed = <3>;
+		hsio-cfg = <PCIEAX2PCIEBX1>;
+		hsio = <&hsio>;
+		ctrl-id = <1>; /* pcieb */
+		cpu-base-addr = <0x80000000>;
+		status = "disabled";
+	};
+
+	imx_ion {
+		compatible = "fsl,mxc-ion";
+		fsl,heap-id = <0>;
+	};
+
+	imx_rpmsg: imx_rpmsg {
+		compatible = "fsl,rpmsg-bus", "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		mu_rpmsg: mu_rpmsg@5d200000 {
+			compatible = "fsl,imx6sx-mu";
+			reg = <0x0 0x5d200000 0x0 0x10000>;
+			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8QXP_LSIO_MU5A_IPG_CLK>;
+			clock-names = "ipg";
+			power-domains = <&pd_lsio_mu5a>;
+		};
+
+		rpmsg: rpmsg{
+			compatible = "fsl,imx8qxp-rpmsg";
+			status = "disabled";
+			mub-partition = <3>;
+			power-domains = <&pd_lsio_mu5a>;
+			memory-region = <&rpmsg_dma_reserved>;
+		};
+	};
+
+	crypto: caam@0x31400000 {
+		compatible = "fsl,sec-v4.0";
+		reg = <0 0x31400000 0 0x400000>;
+		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0x31400000 0x400000>;
+		fsl,first-jr-index = <2>;
+		fsl,sec-era = <9>;
+
+		sec_jr1: jr1@0x20000 {
+			compatible = "fsl,sec-v4.0-job-ring";
+			reg = <0x20000 0x1000>;
+			interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pd_caam_jr1>;
+			status = "disabled";
+		};
+
+		sec_jr2: jr2@30000 {
+			compatible = "fsl,sec-v4.0-job-ring";
+			reg = <0x30000 0x1000>;
+			interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pd_caam_jr2>;
+			status = "okay";
+		};
+
+		sec_jr3: jr3@40000 {
+			compatible = "fsl,sec-v4.0-job-ring";
+			reg = <0x40000 0x1000>;
+			interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pd_caam_jr3>;
+			status = "okay";
+		};
+	};
+
+	caam_sm: caam-sm@31800000 {
+		compatible = "fsl,imx6q-caam-sm";
+		reg = <0 0x31800000 0 0x10000>;
+	};
+
+	sc_pwrkey: sc-powerkey {
+		compatible = "fsl,imx8-pwrkey";
+		linux,keycode = <KEY_POWER>;
+		wakeup-source;
+	};
+
+	wdog: wdog {
+		compatible = "fsl,imx8-wdt";
+	};
+};
+
+&A35_0 {
+	operating-points = <
+		/* kHz	uV*/
+		/* voltage is maintained by SCFW, so no need here */
+		1200000 0
+		 900000 0
+	>;
+	clocks = <&clk IMX8QXP_A35_DIV>;
+	clock-latency = <61036>;
+	#cooling-cells = <2>;
+};
diff --git a/arch/arm/dts/fsl-imx8dxp.dtsi b/arch/arm/dts/fsl-imx8dxp.dtsi
index cc688f44695..ebadb02e7d4 100644
--- a/arch/arm/dts/fsl-imx8dxp.dtsi
+++ b/arch/arm/dts/fsl-imx8dxp.dtsi
@@ -6,6 +6,23 @@
 #include "fsl-imx8dx.dtsi"
 
 / {
-	model = "Freescale i.MX8DXP";
+	model = "NXP i.MX8DXP";
 	compatible = "fsl,imx8dxp", "fsl,imx8qxp";
+	
+	vpu_decoder: vpu_decoder@2c000000 {
+		compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec";
+		boot-region = <&decoder_boot>;
+		rpc-region = <&decoder_rpc>;
+		reg = <0x0 0x2c000000 0x0 0x1000000>;
+		reg-names = "vpu_regs";
+		clocks = <&clk IMX8QXP_VPU_DEC_CLK>;
+		clock-names = "vpu_clk";
+		assigned-clocks = <&clk IMX8QXP_VPU_DEC_CLK>;
+		power-domains = <&pd_vpu_dec>;
+		status = "disabled";
+	};
+};
+
+&gpu_3d0 {
+	assigned-clock-rates = <700000000>, <850000000>;
 };
diff --git a/arch/arm/dts/fsl-imx8qm-cockpit-a53.dtsi b/arch/arm/dts/fsl-imx8qm-cockpit-a53.dtsi
new file mode 100644
index 00000000000..26bb6ad7cc1
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm-cockpit-a53.dtsi
@@ -0,0 +1,351 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "fsl-imx8-ca53.dtsi"
+#include "fsl-imx8-ca72.dtsi"
+#include <dt-bindings/clock/imx8qm-clock.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/imx_rsrc.h>
+#include <dt-bindings/soc/imx8_hsio.h>
+#include <dt-bindings/soc/imx8_pd.h>
+#include <dt-bindings/pinctrl/pads-imx8qm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	compatible = "fsl,imx8qm";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		dpu0 = &dpu1;
+		ethernet0 = &fec1;
+		dsiphy0 = &mipi_dsi_phy1;
+		mipidsi0 = &mipi_dsi1;
+		ldb0 = &ldb1;
+		serial0 = &lpuart0;
+		serial1 = &lpuart1;
+		serial3 = &lpuart3;
+		serial4 = &lpuart4;
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+		gpio3 = &gpio3;
+		gpio4 = &gpio4;
+		gpio5 = &gpio5;
+		gpio6 = &gpio6;
+		gpio7 = &gpio7;
+		mmc1 = &usdhc2;
+		mmc2 = &usdhc3;
+		usb0 = &usbotg1;
+		usbphy0 = &usbphy1;
+		usb1 = &usbotg3;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c6 = &i2c1_lvds0;
+		spi0 = &flexspi0;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000 0 0x40000000>;
+		      /* DRAM space - 1, size : 1 GB DRAM */
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/*
+		 * reserved-memory layout
+		 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
+		 * Shouldn't be used at A core and Linux side.
+		 *
+		 */
+
+		decoder_boot: decoder_boot@0x84000000 {
+			no-map;
+			reg = <0 0x84000000 0 0x2000000>;
+		};
+		encoder_boot: encoder_boot@0x86000000 {
+			no-map;
+			reg = <0 0x86000000 0 0x400000>;
+		};
+		rpmsg_reserved: rpmsg@0x90000000 {
+			no-map;
+			reg = <0 0x90000000 0 0x400000>;
+		};
+		rpmsg_dma_reserved:rpmsg_dma@0x90400000 {
+			compatible = "shared-dma-pool";
+			no-map;
+			reg = <0 0x90400000 0 0x1C00000>;
+		};
+		decoder_rpc: decoder_rpc@0x92000000 {
+			no-map;
+			reg = <0 0x92000000 0 0x200000>;
+		};
+		encoder_rpc: encoder_rpc@0x92200000 {
+			no-map;
+			reg = <0 0x92200000 0 0x200000>;
+		};
+		dsp_reserved: dsp@0x92400000 {
+			no-map;
+			reg = <0 0x92400000 0 0x2000000>;
+		};
+		encoder_reserved: encoder_reserved@0x94400000 {
+			no-map;
+			reg = <0 0x94400000 0 0x800000>;
+		};
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0 0x3c000000>;
+			alloc-ranges = <0 0x96000000 0 0x3c000000>;
+			linux,cma-default;
+		};
+
+	};
+
+	gic: interrupt-controller@51a00000 {
+		compatible = "arm,gic-v3";
+		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
+		      <0x0 0x51b00000 0 0xC0000>, /* GICR */
+		      <0x0 0x52000000 0 0x2000>,  /* GICC */
+		      <0x0 0x52010000 0 0x1000>,  /* GICH */
+		      <0x0 0x52020000 0 0x20000>; /* GICV */
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupts = <GIC_PPI 9
+			(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupt-parent = <&gic>;
+	};
+
+	mu8: mu@5d230000 {
+		compatible = "fsl,imx-m4-mu";
+		reg = <0x0 0x5d230000 0x0 0x10000>;
+		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&pd_lsio_mu8a>;
+		status = "okay";
+	};
+
+	mu9: mu@5d240000 {
+		compatible = "fsl,imx-m4-mu";
+		reg = <0x0 0x5d240000 0x0 0x10000>;
+		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&pd_lsio_mu9a>;
+		status = "okay";
+	};
+
+	mu: mu@5d1c0000 {
+		compatible = "fsl,imx8-mu";
+		reg = <0x0 0x5d1c0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		#mbox-cells = <4>;
+		status = "okay";
+
+		clk: clk {
+			compatible = "fsl,imx8qm-clk";
+			#clock-cells = <1>;
+		};
+
+		iomuxc: iomuxc {
+			compatible = "fsl,imx8qm-iomuxc";
+		};
+	};
+
+	mu13: mu13@5d280000 {
+		compatible = "fsl,imx8-mu-dsp";
+		reg = <0x0 0x5d280000 0x0 0x10000>;
+		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,dsp_ap_mu_id = <13>;
+		status = "okay";
+	};
+
+	mu_m0: mu_m0@2d000000 {
+		compatible = "fsl,imx8-mu0-vpu-m0";
+		reg = <0x0 0x2d000000 0x0 0x20000>;
+		interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,vpu_ap_mu_id = <16>;
+		status = "disabled";
+	};
+
+	mu1_m0: mu1_m0@2d020000 {
+		compatible = "fsl,imx8-mu1-vpu-m0";
+		reg = <0x0 0x2d020000 0x0 0x20000>;
+		interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,vpu_ap_mu_id = <17>;
+		status = "disabled";
+	};
+
+	mu2_m0: mu2_m0@2d040000 {
+		compatible = "fsl,imx8-mu2-vpu-m0";
+		reg = <0x0 0x2d040000 0x0 0x20000>;
+		interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,vpu_ap_mu_id = <18>;
+		status = "disabled";
+	};
+
+	vpu_decoder: vpu_decoder@2c000000 {
+		compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec";
+		boot-region = <&decoder_boot>;
+		rpc-region = <&decoder_rpc>;
+		reg = <0x0 0x2c000000 0x0 0x1000000>;
+		reg-names = "vpu_regs";
+		reg-csr = <0x2d080000>;
+		status = "disabled";
+	};
+
+	vpu_encoder: vpu_encoder@2d000000 {
+		compatible = "nxp,imx8qm-b0-vpuenc";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot-region = <&encoder_boot>;
+		rpc-region = <&encoder_rpc>;
+		reserved-region = <&encoder_reserved>;
+		reg = <0x0 0x2d000000 0x0 0x1000000>,	/*VPU Encoder*/
+			<0x0 0x2c000000 0x0 0x2000000>; /*VPU*/
+		reg-names = "vpu_regs";
+		reg-rpc-system = <0x40000000>;
+
+		resolution-max = <1920 1080>;
+		fps-max = <120>;
+		status = "disabled";
+
+		core0@1020000 {
+			compatible = "fsl,imx8-mu1-vpu-m0";
+			reg = <0x1020000 0x20000>;
+			reg-csr = <0x1090000 0x10000>;
+			interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
+			fsl,vpu_ap_mu_id = <17>;
+			fw-buf-size = <0x200000>;
+			rpc-buf-size = <0x80000>;
+			print-buf-size = <0x80000>;
+		};
+		core1@1040000 {
+			compatible = "fsl,imx8-mu2-vpu-m0";
+			reg = <0x1040000 0x20000>;
+			reg-csr = <0x10a0000 0x10000>;
+			interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+			fsl,vpu_ap_mu_id = <18>;
+			fw-buf-size = <0x200000>;
+			rpc-buf-size = <0x80000>;
+			print-buf-size = <0x80000>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+		clock-frequency = <8000000>;
+		interrupt-parent = <&gic>;
+	};
+
+	smmu: iommu@51400000 {
+		compatible = "arm,mmu-500";
+		interrupt-parent = <&gic>;
+		reg = <0 0x51400000 0 0x40000>;
+		#global-interrupts = <1>;
+		#iommu-cells = <2>;
+		interrupts = <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>;
+	};
+
+	cci: cci@52090000 {
+		compatible = "arm,cci-400";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0 0x52090000 0 0x1000>;
+		ranges = <0 0 0x52090000 0x10000>;
+
+		pmu@9000 {
+			compatible = "arm,cci-400-pmu,r1",
+				     "arm,cci-400-pmu";
+			reg = <0x9000 0x4000>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&gic>;
+		};
+	};
+
+	#include "fsl-imx8qm-device.dtsi"
+};
+
+&A53_0 {
+	operating-points = <
+		/* kHz    uV */
+		/* voltage is maintained by SCFW, so no need here */
+		1200000	   0
+		1104000	   0
+		900000	   0
+		600000	   0
+	>;
+	clocks = <&clk IMX8QM_A53_DIV>;
+	clock-latency = <61036>;
+	#cooling-cells = <2>;
+	/delete-property/ cpu-idle-states;
+};
+
+&A72_0 {
+	operating-points = <
+		/* kHz    uV */
+		/* voltage is maintained by SCFW, so no need here */
+		1596000	   0
+		1296000	   0
+		1056000	   0
+		600000     0
+	>;
+	clocks = <&clk IMX8QM_A72_DIV>;
+	clock-latency = <61036>;
+	#cooling-cells = <2>;
+	/delete-property/ cpu-idle-states;
+};
+
+&A53_1 {
+	/delete-property/ cpu-idle-states;
+};
+
+&A53_2 {
+	/delete-property/ cpu-idle-states;
+};
+
+&A53_3 {
+	/delete-property/ cpu-idle-states;
+};
+
+&A72_1 {
+	/delete-property/ cpu-idle-states;
+};
diff --git a/arch/arm/dts/fsl-imx8qm-cockpit-a72.dtsi b/arch/arm/dts/fsl-imx8qm-cockpit-a72.dtsi
new file mode 100644
index 00000000000..3da1f464f5f
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm-cockpit-a72.dtsi
@@ -0,0 +1,343 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "fsl-imx8-ca53.dtsi"
+#include "fsl-imx8-ca72.dtsi"
+#include <dt-bindings/clock/imx8qm-clock.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/soc/imx_rsrc.h>
+#include <dt-bindings/soc/imx8_hsio.h>
+#include <dt-bindings/soc/imx8_pd.h>
+#include <dt-bindings/pinctrl/pads-imx8qm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	compatible = "fsl,imx8qm";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		dpu1 = &dpu2;
+		ethernet1 = &fec2;
+		dsiphy1 = &mipi_dsi_phy2;
+		mipidsi1 = &mipi_dsi2;
+		ldb1 = &ldb2;
+		serial2 = &lpuart2;
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+		gpio3 = &gpio3;
+		gpio4 = &gpio4;
+		gpio5 = &gpio5;
+		gpio6 = &gpio6;
+		gpio7 = &gpio7;
+		mmc0 = &usdhc1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c8 = &i2c1_lvds1;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x00000000 0xc0000000 0 0x40000000>;
+		      /* DRAM space - 1, size : 1 GB DRAM */
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/*
+		 * reserved-memory layout
+		 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
+		 * Shouldn't be used at A core and Linux side.
+		 *
+		 */
+
+		decoder_boot: decoder_boot@0x84000000 {
+			no-map;
+			reg = <0 0x84000000 0 0x2000000>;
+		};
+		encoder_boot: encoder_boot@0x86000000 {
+			no-map;
+			reg = <0 0x86000000 0 0x400000>;
+		};
+		rpmsg_reserved: rpmsg@0x90000000 {
+			no-map;
+			reg = <0 0x90000000 0 0x400000>;
+		};
+		rpmsg_dma_reserved:rpmsg_dma@0x90400000 {
+			compatible = "shared-dma-pool";
+			no-map;
+			reg = <0 0x90400000 0 0x1C00000>;
+		};
+		decoder_rpc: decoder_rpc@0x92000000 {
+			no-map;
+			reg = <0 0x92000000 0 0x200000>;
+		};
+		encoder_rpc: encoder_rpc@0x92200000 {
+			no-map;
+			reg = <0 0x92200000 0 0x200000>;
+		};
+		dsp_reserved: dsp@0x92400000 {
+			no-map;
+			reg = <0 0x92400000 0 0x2000000>;
+		};
+		encoder_reserved: encoder_reserved@0x94400000 {
+			no-map;
+			reg = <0 0x94400000 0 0x800000>;
+		};
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0 0x3c000000>;
+			alloc-ranges = <0 0xd6000000 0 0x3c000000>;
+			linux,cma-default;
+		};
+
+	};
+
+	gic: interrupt-controller@51a00000 {
+		compatible = "arm,gic-v3";
+		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
+		      <0x0 0x51b00000 0 0xC0000>, /* GICR */
+		      <0x0 0x52000000 0 0x2000>,  /* GICC */
+		      <0x0 0x52010000 0 0x1000>,  /* GICH */
+		      <0x0 0x52020000 0 0x20000>; /* GICV */
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupts = <GIC_PPI 9
+			(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupt-parent = <&gic>;
+	};
+
+	mu8: mu@5d230000 {
+		compatible = "fsl,imx-m4-mu";
+		reg = <0x0 0x5d230000 0x0 0x10000>;
+		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&pd_lsio_mu8a>;
+		status = "disabled";
+	};
+
+	mu9: mu@5d240000 {
+		compatible = "fsl,imx-m4-mu";
+		reg = <0x0 0x5d240000 0x0 0x10000>;
+		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&pd_lsio_mu9a>;
+		status = "disabled";
+	};
+
+	mu: mu@5d1d0000 {
+		compatible = "fsl,imx8-mu";
+		reg = <0x0 0x5d1d0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		#mbox-cells = <4>;
+		status = "okay";
+
+		clk: clk {
+			compatible = "fsl,imx8qm-clk";
+			#clock-cells = <1>;
+		};
+
+		iomuxc: iomuxc {
+			compatible = "fsl,imx8qm-iomuxc";
+		};
+	};
+
+	mu13: mu13@5d280000 {
+		compatible = "fsl,imx8-mu-dsp";
+		reg = <0x0 0x5d280000 0x0 0x10000>;
+		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,dsp_ap_mu_id = <13>;
+		status = "disabled";
+	};
+
+	mu_m0: mu_m0@2d000000 {
+		compatible = "fsl,imx8-mu0-vpu-m0";
+		reg = <0x0 0x2d000000 0x0 0x20000>;
+		interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,vpu_ap_mu_id = <16>;
+		status = "okay";
+	};
+
+	mu1_m0: mu1_m0@2d020000 {
+		compatible = "fsl,imx8-mu1-vpu-m0";
+		reg = <0x0 0x2d020000 0x0 0x20000>;
+		interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,vpu_ap_mu_id = <17>;
+		status = "okay";
+	};
+
+	mu2_m0: mu2_m0@2d040000 {
+		compatible = "fsl,imx8-mu2-vpu-m0";
+		reg = <0x0 0x2d040000 0x0 0x20000>;
+		interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,vpu_ap_mu_id = <18>;
+		status = "okay";
+	};
+
+	vpu_decoder: vpu_decoder@2c000000 {
+		compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec";
+		boot-region = <&decoder_boot>;
+		rpc-region = <&decoder_rpc>;
+		reg = <0x0 0x2c000000 0x0 0x1000000>;
+		reg-names = "vpu_regs";
+		reg-csr = <0x2d080000>;
+		status = "disabled";
+	};
+
+	vpu_encoder: vpu_encoder@2d000000 {
+		compatible = "nxp,imx8qm-b0-vpuenc";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot-region = <&encoder_boot>;
+		rpc-region = <&encoder_rpc>;
+		reserved-region = <&encoder_reserved>;
+		reg = <0x0 0x2d000000 0x0 0x1000000>,	/*VPU Encoder*/
+			<0x0 0x2c000000 0x0 0x2000000>; /*VPU*/
+		reg-names = "vpu_regs";
+		reg-rpc-system = <0x40000000>;
+
+		resolution-max = <1920 1080>;
+		fps-max = <120>;
+		status = "disabled";
+
+		core0@1020000 {
+			compatible = "fsl,imx8-mu1-vpu-m0";
+			reg = <0x1020000 0x20000>;
+			reg-csr = <0x1090000 0x10000>;
+			interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
+			fsl,vpu_ap_mu_id = <17>;
+			fw-buf-size = <0x200000>;
+			rpc-buf-size = <0x80000>;
+			print-buf-size = <0x80000>;
+		};
+		core1@1040000 {
+			compatible = "fsl,imx8-mu2-vpu-m0";
+			reg = <0x1040000 0x20000>;
+			reg-csr = <0x10a0000 0x10000>;
+			interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+			fsl,vpu_ap_mu_id = <18>;
+			fw-buf-size = <0x200000>;
+			rpc-buf-size = <0x80000>;
+			print-buf-size = <0x80000>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+		clock-frequency = <8000000>;
+		interrupt-parent = <&gic>;
+	};
+
+	smmu: iommu@51400000 {
+		compatible = "arm,mmu-500";
+		interrupt-parent = <&gic>;
+		reg = <0 0x51400000 0 0x40000>;
+		#global-interrupts = <1>;
+		#iommu-cells = <2>;
+		interrupts = <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>;
+	};
+
+	cci: cci@52090000 {
+		compatible = "arm,cci-400";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0 0x52090000 0 0x1000>;
+		ranges = <0 0 0x52090000 0x10000>;
+
+		pmu@9000 {
+			compatible = "arm,cci-400-pmu,r1",
+				     "arm,cci-400-pmu";
+			reg = <0x9000 0x4000>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&gic>;
+		};
+	};
+
+	#include "fsl-imx8qm-device.dtsi"
+};
+
+&A53_0 {
+	operating-points = <
+		/* kHz    uV */
+		/* voltage is maintained by SCFW, so no need here */
+		1200000	   0
+		1104000	   0
+		900000	   0
+		600000	   0
+	>;
+	clocks = <&clk IMX8QM_A53_DIV>;
+	clock-latency = <61036>;
+	#cooling-cells = <2>;
+	/delete-property/ cpu-idle-states;
+};
+
+&A72_0 {
+	operating-points = <
+		/* kHz    uV */
+		/* voltage is maintained by SCFW, so no need here */
+		1596000	   0
+		1296000	   0
+		1056000	   0
+		600000     0
+	>;
+	clocks = <&clk IMX8QM_A72_DIV>;
+	clock-latency = <61036>;
+	#cooling-cells = <2>;
+	/delete-property/ cpu-idle-states;
+};
+
+
+&A53_1 {
+	/delete-property/ cpu-idle-states;
+};
+
+&A53_2 {
+	/delete-property/ cpu-idle-states;
+};
+
+&A53_3 {
+	/delete-property/ cpu-idle-states;
+};
+
+&A72_1 {
+	/delete-property/ cpu-idle-states;
+};
diff --git a/arch/arm/dts/fsl-imx8qm-ddr4-val-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-ddr4-val-u-boot.dtsi
new file mode 100644
index 00000000000..a0a8c7d6f5a
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm-ddr4-val-u-boot.dtsi
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+/ {
+
+	aliases {
+		usbhost1 = &usbh3;
+		usbgadget0 = &usbg1;
+	};
+
+	usbh3: usbh3 {
+		compatible = "Cadence,usb3-host";
+		dr_mode = "host";
+		cdns3,usb = <&usbotg3>;
+		status = "okay";
+	};
+
+	usbg1: usbg1 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg1>;
+		status = "okay";
+		u-boot,dm-spl;
+	};
+};
+
+&{/imx8qm-pm} {
+
+	u-boot,dm-spl;
+};
+
+&mu {
+	u-boot,dm-spl;
+};
+
+&clk {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&{/mu@5d1c0000/iomuxc/imx8qm-val} {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3_100mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3_200mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_lpuart0 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+	u-boot,dm-spl;
+};
+
+&pd_conn {
+	u-boot,dm-spl;
+};
+
+&pd_dma {
+	u-boot,dm-spl;
+};
+
+&pd_dma_lpuart0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0_phy {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usb2 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usb2_phy {
+	u-boot,dm-spl;
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&lpuart0 {
+	u-boot,dm-spl;
+};
+
+&usbmisc1 {
+	u-boot,dm-spl;
+};
+
+&usbphy1 {
+	u-boot,dm-spl;
+};
+
+&usbotg1 {
+	u-boot,dm-spl;
+};
+
+&usbotg3 {
+	phys = <&usbphynop1>;
+	u-boot,dm-spl;
+};
+
+&usbphynop1 {
+	compatible = "cdns,usb3-phy";
+	reg = <0x0 0x5B160000 0x0 0x40000>;
+	#phy-cells = <0>;
+	u-boot,dm-spl;
+};
+
+&usdhc3 {
+	u-boot,dm-spl;
+};
+
+&wu {
+	u-boot,dm-spl;
+};
+
+&fec1 {
+	phy-mode = "rgmii-id";
+};
+
+&fec2 {
+	phy-mode = "rgmii-id";
+};
+
+&ethphy0 {
+	vddio0: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
+
+&ethphy1 {
+	vddio1: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
\ No newline at end of file
diff --git a/arch/arm/dts/fsl-imx8qm-ddr4-val.dts b/arch/arm/dts/fsl-imx8qm-ddr4-val.dts
new file mode 100644
index 00000000000..dfcf660f326
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm-ddr4-val.dts
@@ -0,0 +1,423 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017~2019 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qm.dtsi"
+
+/ {
+	model = "NXP i.MX8QM DDR4 VAL";
+	compatible = "fsl,imx8qm-val", "fsl,imx8qm";
+
+	aliases {
+		gpio8 = &pca9557_a;
+		gpio9 = &pca9557_b;
+		gpio10 = &pca9557_c;
+		gpio11 = &pca9557_d;
+	};
+
+	chosen {
+		bootargs = "console=ttyLP0,115200 earlycon";
+		stdout-path = &lpuart0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_leds>;
+		user {
+			label = "heartbeat";
+			gpios = <&gpio2 15 0>;
+			default-state = "on";
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+	};
+
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	imx8qm-val {
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	  0x06000048
+				SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06	  0x06000021
+				SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07	  0x06000021
+				SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12	  0x06000021
+				SC_P_SPDIF0_TX_LSIO_GPIO2_IO15	  0x06000021
+			>;
+		};
+
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD	0x000014a0
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000060
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x00000060
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000060
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000060
+				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x00000060
+				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x00000060
+				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x00000060
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000060
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000060
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000060
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x00000060
+				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x00000060
+			>;
+		};
+
+		pinctrl_fec2: fec2grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD	0x000014a0
+				SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x00000060
+				SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC	0x00000060
+				SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0	0x00000060
+				SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1	0x00000060
+				SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2	0x00000060
+				SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3	0x00000060
+				SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC	0x00000060
+				SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x00000060
+				SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0	0x00000060
+				SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1	0x00000060
+				SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2	0x00000060
+				SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3	0x00000060
+			>;
+		};
+
+		pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
+			fsl,pins = <
+				SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL	0xc600004c
+				SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA	0xc600004c
+			>;
+		};
+
+		pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {
+			fsl,pins = <
+				SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL	0xc600004c
+				SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA	0xc600004c
+			>;
+		};
+
+		pinctrl_lpuart0: lpuart0grp {
+			fsl,pins = <
+				SC_P_UART0_RX_DMA_UART0_RX		0x06000020
+				SC_P_UART0_TX_DMA_UART0_TX		0x06000020
+			>;
+		};
+
+
+
+		pinctrl_usdhc3_gpio: usdhc3grpgpio {
+			fsl,pins = <
+				SC_P_USDHC2_RESET_B_CONN_USDHC2_RESET_B	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000041
+				SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000021
+				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000021
+				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000021
+				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000021
+				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000021
+                                SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021
+				/* WP */
+				SC_P_USDHC2_WP_LSIO_GPIO4_IO11          0x00000021
+				/* CD */
+				SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12        0x00000021
+			>;
+		};
+                pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+                        fsl,pins = <
+                                SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000040
+				SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000020
+				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000020
+				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000020
+				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000020
+				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000020
+                                SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
+				/* WP */
+				SC_P_USDHC2_WP_LSIO_GPIO4_IO11          0x00000020
+				/* CD */
+				SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12        0x00000020
+			>;
+		};
+                pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+                        fsl,pins = <
+                                SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000040
+				SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000020
+				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000020
+				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000020
+				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000020
+				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000020
+                                SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
+				/* WP */
+				SC_P_USDHC2_WP_LSIO_GPIO4_IO11          0x00000020
+				/* CD */
+				SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12        0x00000020
+			>;
+		};
+
+
+		pinctrl_lpi2c1: lpi2c1grp {
+			fsl,pins = <
+				SC_P_GPT0_CLK_DMA_I2C1_SCL		0x06000020
+				SC_P_GPT0_CAPTURE_DMA_I2C1_SDA		0x06000020
+				/*
+				 * Change the default alt function from SCL/SDA to others,
+				 * to avoid select input conflict with GPT0
+				 */
+				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x0700004c
+				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04	0x0700004c
+				SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05	0x0700004c
+				SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06	0x0700004c
+			>;
+		};
+
+		pinctrl_lpspi0: lpspi0grp {
+			fsl,pins = <
+				SC_P_SPI0_SCK_DMA_SPI0_SCK		0x0600004c
+				SC_P_SPI0_SDO_DMA_SPI0_SDO		0x0600004c
+				SC_P_SPI0_SDI_DMA_SPI0_SDI		0x0600004c
+				SC_P_SPI0_CS0_DMA_SPI0_CS0		0x0600004c
+				SC_P_SPI0_CS1_DMA_SPI0_CS1		0x0600004c
+			>;
+		};
+
+		pinctrl_flexspi0: flexspi0grp {
+			fsl,pins = <
+				SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x06000021
+				SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x06000021
+				SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x06000021
+				SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x06000021
+				SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS		0x06000021
+				SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x06000021
+				SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B	0x06000021
+				SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x06000021
+				SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK	0x06000021
+				SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x06000021
+				SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x06000021
+				SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x06000021
+				SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x06000021
+				SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS		0x06000021
+				SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B	0x06000021
+				SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B	0x06000021
+			>;
+		};
+
+		pinctrl_gpio_leds: gpioledsgrp {
+			fsl,pins = <
+				SC_P_SPDIF0_TX_LSIO_GPIO2_IO15		0x00000021
+			>;
+		};
+	};
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>,<&pinctrl_usdhc3_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>,<&pinctrl_usdhc3_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
+        no-1-8-v;
+	status = "okay";
+
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	disable-over-current;
+	status = "okay";
+};
+
+&usbotg3 {
+	status = "okay";
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-txid";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	fsl,rgmii_rxc_dly;
+	status = "okay";
+	phy-reset-gpios = <&pca9557_a 1 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <10>;
+	phy-reset-post-delay = <150>;
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			at803x,eee-disabled;
+			at803x,vddio-1p8v;
+		};
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			at803x,eee-disabled;
+			at803x,vddio-1p8v;
+			status = "disabled";
+		};
+	};
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec2>;
+	phy-mode = "rgmii-txid";
+	phy-handle = <&ethphy1>;
+	fsl,magic-packet;
+	fsl,rgmii_rxc_dly;
+	status = "okay";
+	phy-reset-gpios = <&pca9557_a 4 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <10>;
+	phy-reset-post-delay = <150>;
+};
+
+&flexspi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi0>;
+	status = "okay";
+
+	flash0: mt35xu512aba@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <8>;
+	};
+};
+
+&i2c1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c1>;
+	status = "okay";
+
+	pca9557_a: gpio@18 {
+		compatible = "nxp,pca9557";
+		reg = <0x18>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pca9557_b: gpio@19 {
+		compatible = "nxp,pca9557";
+		reg = <0x19>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pca9557_c: gpio@1b {
+		compatible = "nxp,pca9557";
+		reg = <0x1b>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pca9557_d: gpio@1f {
+		compatible = "nxp,pca9557";
+		reg = <0x1f>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&i2c1_lvds0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	lvds-to-hdmi-bridge@4c {
+		compatible = "ite,it6263";
+		reg = <0x4c>;
+	};
+};
+
+&i2c1_lvds1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lvds1_lpi2c1>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	lvds-to-hdmi-bridge@4c {
+		compatible = "ite,it6263";
+		reg = <0x4c>;
+	};
+};
+
+&lpspi0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpspi0>;
+	status = "okay";
+
+	spidev0: spi@0 {
+		reg = <0>;
+		compatible = "rohm,dh2228fv";
+		spi-max-frequency = <4000000>;
+	};
+};
+
+&lpuart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart0>;
+	status = "okay";
+};
+
+&lpuart1 {
+	status = "okay";
+};
+
diff --git a/arch/arm/dts/fsl-imx8qm-device.dtsi b/arch/arm/dts/fsl-imx8qm-device.dtsi
new file mode 100644
index 00000000000..e4ce8b1a654
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm-device.dtsi
@@ -0,0 +1,2381 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+	imx8qm-pm {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		pd_dc0: PD_DC_0 {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_DC_0>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_dc0_pll0: PD_DC_0_PLL_0{
+				reg = <SC_R_DC_0_PLL_0>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_dc0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_dc0_pll1: PD_DC_0_PLL_1{
+					reg = <SC_R_DC_0_PLL_1>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_dc0_pll0>;
+				};
+			};
+
+			pd_mipi0: PD_MIPI_0_DSI {
+				reg = <SC_R_MIPI_0>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_dc0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_mipi0_i2c0: PD_MIPI_0_DSI_I2C0 {
+					reg = <SC_R_MIPI_0_I2C_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi0>;
+				};
+
+				pd_mipi0_i2c1: PD_MIPI_0_DSI_I2C1 {
+					reg = <SC_R_MIPI_0_I2C_1>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi0>;
+				};
+
+				pd_mipi0_pwm: PD_MIPI_0_DSI_PWM0 {
+					reg = <SC_R_MIPI_0_PWM_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi0>;
+				};
+			};
+
+			pd_lvds0: PD_LVDS0 {
+				reg = <SC_R_LVDS_0>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_dc0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_lvds0_i2c0: PD_LVDS0_I2C0 {
+					reg = <SC_R_LVDS_0_I2C_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_lvds0>;
+				};
+
+				pd_lvds0_pwm: PD_LVDS0_PWM {
+					reg = <SC_R_LVDS_0_PWM_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_lvds0>;
+				};
+			};
+
+			pd_hdmi: PD_HDMI {
+				reg = <SC_R_HDMI>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_dc0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_hdmi_pll0: PD_HDMI_PLL_0{
+					reg = <SC_R_HDMI_PLL_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_hdmi>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_hdmi_pll1: PD_HDMI_PLL_1{
+						reg = <SC_R_HDMI_PLL_1>;
+						#power-domain-cells = <0>;
+						power-domains =<&pd_hdmi_pll0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						pd_hdmi_i2c0: PD_HDMI_I2C_0 {
+							reg = <SC_R_HDMI_I2C_0>;
+							#power-domain-cells = <0>;
+							power-domains =<&pd_hdmi_pll1>;
+						};
+
+						pd_hdmi_i2s: PD_HDMI_I2S {
+							reg = <SC_R_HDMI_I2S>;
+							#power-domain-cells = <0>;
+							power-domains =<&pd_hdmi_pll1>;
+						};
+					};
+				};
+
+			};
+
+		};
+
+		pd_dc1: PD_DC_1 {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_DC_1>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_dc1_pll0: PD_DC_1_PLL_0{
+				reg = <SC_R_DC_1_PLL_0>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_dc1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_dc1_pll1: PD_DC_1_PLL_1{
+					reg = <SC_R_DC_1_PLL_1>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_dc1_pll0>;
+				};
+			};
+
+			pd_mipi1: PD_MIPI_1_DSI {
+				reg = <SC_R_MIPI_1>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_dc1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_mipi1_i2c0: PD_MIPI_1_DSI_I2C0 {
+					reg = <SC_R_MIPI_1_I2C_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi1>;
+				};
+
+				pd_mipi1_i2c1: PD_MIPI_1_DSI_I2C1 {
+					reg = <SC_R_MIPI_1_I2C_1>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi1>;
+				};
+
+				pd_mipi1_pwm: PD_MIPI_1_DSI_PWM {
+					reg = <SC_R_MIPI_1_PWM_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_mipi1>;
+				};
+			};
+
+			pd_lvds1: PD_LVDS1 {
+				reg = <SC_R_LVDS_1>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_dc1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_lvds1_i2c0: PD_LVDS1_I2C0 {
+					reg = <SC_R_LVDS_1_I2C_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_lvds1>;
+				};
+
+				pd_lvds1_pwm: PD_LVDS1_PWM {
+					reg = <SC_R_LVDS_1_PWM_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_lvds1>;
+				};
+			};
+		};
+
+		pd_lsio: PD_LSIO {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_NONE>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_lsio_gpio0: PD_LSIO_GPIO_0 {
+				reg = <SC_R_GPIO_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio1: PD_LSIO_GPIO_1 {
+				reg = <SC_R_GPIO_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio2: PD_LSIO_GPIO_2 {
+				reg = <SC_R_GPIO_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio3: PD_LSIO_GPIO_3 {
+				reg = <SC_R_GPIO_3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio4: PD_LSIO_GPIO_4 {
+				reg = <SC_R_GPIO_4>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio5: PD_LSIO_GPIO_5{
+				reg = <SC_R_GPIO_5>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio6:PD_LSIO_GPIO_6 {
+				reg = <SC_R_GPIO_6>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_gpio7: PD_LSIO_GPIO_7 {
+				reg = <SC_R_GPIO_7>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_flexspi0: PD_LSIO_FSPI_0 {
+				reg = <SC_R_FSPI_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_flexspi1: PD_LSIO_FSPI_1{
+				reg = <SC_R_FSPI_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_mu5a: PD_LSIO_MU5A {
+				reg = <SC_R_MU_5A>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_mu6a: PD_LSIO_MU6A {
+				reg = <SC_R_MU_6A>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_mu8a: PD_LSIO_MU8A {
+				reg = <SC_R_MU_8A>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+			pd_lsio_mu9a: PD_LSIO_MU9A {
+				reg = <SC_R_MU_9A>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_lsio>;
+			};
+		};
+
+		pd_conn: PD_CONN {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_NONE>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_conn_usbotg0: PD_CONN_USB_0 {
+				reg = <SC_R_USB_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+				wakeup-irq = <267>;
+			};
+
+			pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY {
+				reg = <SC_R_USB_0_PHY>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+				wakeup-irq = <267>;
+			};
+
+			pd_conn_usbh1: PD_CONN_USB_1 {
+				reg = <SC_R_USB_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+				wakeup-irq = <268>;
+			};
+
+			pd_conn_usb2: PD_CONN_USB_2 {
+				reg = <SC_R_USB_2>;
+				#power-domain-cells = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&pd_conn>;
+				wakeup-irq = <271>;
+
+				pd_conn_usb2_phy: PD_CONN_USB_2_PHY {
+					reg = <SC_R_USB_2_PHY>;
+					#power-domain-cells = <0>;
+					power-domains = <&pd_conn_usb2>;
+					wakeup-irq = <271>;
+				};
+			};
+			pd_conn_sdch0: PD_CONN_SDHC_0 {
+				reg = <SC_R_SDHC_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+			};
+			pd_conn_sdch1: PD_CONN_SDHC_1 {
+				reg = <SC_R_SDHC_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+			};
+			pd_conn_sdch2: PD_CONN_SDHC_2 {
+				reg = <SC_R_SDHC_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+			};
+			pd_conn_enet0: PD_CONN_ENET_0 {
+				reg = <SC_R_ENET_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+				wakeup-irq = <258>;
+			};
+			pd_conn_enet1: PD_CONN_ENET_1 {
+				reg = <SC_R_ENET_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+				fsl,wakeup_irq = <262>;
+			};
+			pd_conn_nand: PD_CONN_NAND {
+				reg = <SC_R_NAND>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+			};
+			pd_conn_mlb0: PD_CONN_MLB_0 {
+				reg = <SC_R_MLB_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_conn>;
+			};
+			pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 {
+				reg = <SC_R_DMA_4_CH0>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_conn>;
+			};
+			pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 {
+				reg = <SC_R_DMA_4_CH1>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_conn>;
+			};
+			pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 {
+				reg = <SC_R_DMA_4_CH2>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_conn>;
+			};
+			pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 {
+				reg = <SC_R_DMA_4_CH3>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_conn>;
+			};
+			pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 {
+				reg = <SC_R_DMA_4_CH4>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_conn>;
+			};
+		};
+
+		pd_hsio: PD_HSIO {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_NONE>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_hsio_gpio: PD_HSIO_GPIO {
+				reg = <SC_R_HSIO_GPIO>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_hsio>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_serdes0: PD_HSIO_SERDES_0 {
+					reg = <SC_R_SERDES_0>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_hsio_gpio>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_pcie0: PD_HSIO_PCIE_A {
+						reg = <SC_R_PCIE_A>;
+						#power-domain-cells = <0>;
+						power-domains =<&pd_serdes0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						pd_pcie1: PD_HSIO_PCIE_B {
+							reg = <SC_R_PCIE_B>;
+							#power-domain-cells = <0>;
+							power-domains =<&pd_pcie0>;
+							#address-cells = <1>;
+							#size-cells = <0>;
+
+							pd_serdes1: PD_HSIO_SERDES_1 {
+								reg = <SC_R_SERDES_1>;
+								#power-domain-cells = <0>;
+								power-domains =<&pd_pcie1>;
+								#address-cells = <1>;
+								#size-cells = <0>;
+
+								pd_sata0: PD_HSIO_SATA_0 {
+									reg = <SC_R_SATA_0>;
+									#power-domain-cells = <0>;
+									power-domains =<&pd_serdes1>;
+								};
+							};
+						};
+					};
+				};
+			};
+		};
+
+		pd_dma: PD_DMA {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_NONE>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_dma_lpi2c0: PD_DMA_I2C_0 {
+				reg = <SC_R_I2C_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpi2c1: PD_DMA_I2C_1 {
+				reg = <SC_R_I2C_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpi2c2:PD_DMA_I2C_2 {
+				reg = <SC_R_I2C_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpi2c3: PD_DMA_I2C_3 {
+				reg = <SC_R_I2C_3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpi2c4: PD_DMA_I2C_4 {
+				reg = <SC_R_I2C_4>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpuart0: PD_DMA_UART0 {
+				reg = <SC_R_UART_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+				wakeup-irq = <345>;
+			};
+			pd_dma_lpuart1: PD_DMA_UART1 {
+				reg = <SC_R_UART_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				wakeup-irq = <346>;
+
+				pd_dma0_chan14: PD_UART1_RX {
+					reg = <SC_R_DMA_0_CH14>;
+					power-domains =<&pd_dma_lpuart1>;
+					#power-domain-cells = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_dma0_chan15: PD_UART1_TX {
+						reg = <SC_R_DMA_0_CH15>;
+						power-domains =<&pd_dma0_chan14>;
+						#power-domain-cells = <0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+					};
+				};
+			};
+			pd_dma_lpuart2: PD_DMA_UART2 {
+				reg = <SC_R_UART_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				wakeup-irq = <347>;
+
+				pd_dma0_chan16: PD_UART2_RX {
+					reg = <SC_R_DMA_0_CH16>;
+					power-domains =<&pd_dma_lpuart2>;
+					#power-domain-cells = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_dma0_chan17: PD_UART2_TX {
+						reg = <SC_R_DMA_0_CH17>;
+						power-domains =<&pd_dma0_chan16>;
+						#power-domain-cells = <0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+					};
+				};
+			};
+			pd_dma_lpuart3: PD_DMA_UART3 {
+				reg = <SC_R_UART_3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				wakeup-irq = <348>;
+
+				pd_dma0_chan18: PD_UART3_RX {
+					reg = <SC_R_DMA_0_CH18>;
+					power-domains =<&pd_dma_lpuart3>;
+					#power-domain-cells = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_dma0_chan19: PD_UART3_TX {
+						reg = <SC_R_DMA_0_CH19>;
+						power-domains =<&pd_dma0_chan18>;
+						#power-domain-cells = <0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+					};
+				};
+			};
+			pd_dma_lpuart4: PD_DMA_UART4 {
+				reg = <SC_R_UART_4>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				wakeup-irq = <349>;
+
+				pd_dma0_chan20: PD_UART4_RX {
+					reg = <SC_R_DMA_0_CH20>;
+					power-domains =<&pd_dma_lpuart4>;
+					#power-domain-cells = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_dma0_chan21: PD_UART4_TX {
+						reg = <SC_R_DMA_0_CH21>;
+						power-domains =<&pd_dma0_chan20>;
+						#power-domain-cells = <0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+					};
+				};
+			};
+			pd_dma_lpspi0: PD_DMA_SPI_0 {
+				reg = <SC_R_SPI_0>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_dma0_chan0: PD_LPSPI0_RX {
+					reg = <SC_R_DMA_0_CH0>;
+					power-domains =<&pd_dma_lpspi0>;
+					#power-domain-cells = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_dma0_chan1: PD_LPSPI0_TX {
+						reg = <SC_R_DMA_0_CH1>;
+						power-domains =<&pd_dma0_chan0>;
+						#power-domain-cells = <0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+			};
+				};
+			};
+			pd_dma_lpspi1: PD_DMA_SPI_1 {
+				reg = <SC_R_SPI_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpspi2: PD_DMA_SPI_2 {
+				reg = <SC_R_SPI_2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+			pd_dma_lpspi3: PD_DMA_SPI_3 {
+				reg = <SC_R_SPI_3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_dma0_chan6: PD_LPSPI3_RX {
+					reg = <SC_R_DMA_0_CH6>;
+					power-domains =<&pd_dma_lpspi3>;
+					#power-domain-cells = <0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_dma0_chan7: PD_LPSPI3_TX {
+						reg = <SC_R_DMA_0_CH7>;
+						power-domains =<&pd_dma0_chan6>;
+						#power-domain-cells = <0>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+					};
+				};
+			};
+			pd_dma_emvsim0: PD_DMA_EMVSIM_0 {
+				reg = <SC_R_EMVSIM_0>;
+				power-domains = <&pd_dma>;
+				#power-domain-cells = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_ldo1_sim: LDO1_SIM {
+					reg = <SC_R_BOARD_R2>;
+					#power-domain-cells = <0>;
+					power-domains = <&pd_dma_emvsim0>;
+				};
+			};
+			pd_dma_emvsim1: PD_DMA_EMVSIM_1 {
+				reg = <SC_R_EMVSIM_1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+			};
+		};
+
+
+		pd_isi_ch0: PD_IMAGING {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_ISI_CH0>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_hdmi_rx: PD_HDMI_RX {
+				reg = <SC_R_HDMI_RX>;
+				#power-domain-cells = <0>;
+				power-domains =<&pd_isi_ch0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_hdmi_rx_bypass: PD_HDMI_RX_BYPASS {
+					reg = <SC_R_HDMI_RX_BYPASS>;
+					#power-domain-cells = <0>;
+					power-domains =<&pd_hdmi_rx>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pd_hdmi_rx_i2c0: PD_HDMI_RX_I2C {
+						reg = <SC_R_HDMI_RX_I2C_0>;
+						#power-domain-cells = <0>;
+						power-domains =<&pd_hdmi_rx_bypass>;
+					};
+
+					pd_hdmi_rx_pwm0: PD_HDMI_RX_PWM {
+						reg = <SC_R_HDMI_RX_PWM_0>;
+						#power-domain-cells = <0>;
+						power-domains =<&pd_hdmi_rx_bypass>;
+					};
+				};
+			};
+
+		};
+
+		pd_caam: PD_CAAM {
+			compatible = "nxp,imx8-pd";
+			reg = <SC_R_NONE>;
+			#power-domain-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pd_caam_jr1: PD_CAAM_JR1 {
+				reg = <SC_R_CAAM_JR1>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_caam>;
+			};
+			pd_caam_jr2: PD_CAAM_JR2 {
+				reg = <SC_R_CAAM_JR2>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_caam>;
+			};
+			pd_caam_jr3: PD_CAAM_JR3 {
+				reg = <SC_R_CAAM_JR3>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_caam>;
+			};
+		};
+	};
+
+	tsens: thermal-sensor {
+		compatible = "nxp,imx8qm-sc-tsens";
+		u-boot,dm-pre-reloc;
+		/* number of the temp sensor on the chip */
+		tsens-num = <5>;
+		#thermal-sensor-cells = <1>;
+	};
+
+	thermal_zones: thermal-zones {
+		/* cpu thermal */
+		cpu-thermal0 {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			/*the slope and offset of the temp sensor */
+			thermal-sensors = <&tsens 0>;
+			trips {
+				cpu_alert0: trip0 {
+					temperature = <107000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit0: trip1 {
+					temperature = <127000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert0>;
+					cooling-device =
+					<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		cpu-thermal1 {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			thermal-sensors = <&tsens 1>;
+			trips {
+				cpu_alert1: trip0 {
+					temperature = <107000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit1: trip1 {
+					temperature = <127000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert1>;
+					cooling-device =
+					<&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+
+		gpu-thermal0 {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			thermal-sensors = <&tsens 2>;
+			trips {
+				gpu_alert0: trip0 {
+					temperature = <107000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				gpu_crit0: trip1 {
+					temperature = <127000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		gpu-thermal1 {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			thermal-sensors = <&tsens 3>;
+			trips {
+				gpu_alert1: trip0 {
+					temperature = <107000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				gpu_crit1: trip1 {
+					temperature = <127000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+
+		drc-thermal0 {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			thermal-sensors = <&tsens 4>;
+			trips {
+				drc_alert0: trip0 {
+					temperature = <107000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				drc_crit0: trip1 {
+					temperature = <127000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
+	rtc: rtc {
+		compatible = "fsl,imx-sc-rtc";
+	};
+
+	dpu1_intsteer: dpu_intsteer@56000000 {
+		compatible = "fsl,imx8qm-dpu-intsteer", "syscon";
+		reg = <0x0 0x56000000 0x0 0x10000>;
+	};
+
+	dpu1: dpu@56180000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx8qm-dpu";
+		reg = <0x0 0x56180000 0x0 0x40000>;
+		intsteer = <&dpu1_intsteer>;
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "irq_common",
+				  "irq_stream0a",
+				  "irq_stream0b",	/* to M4? */
+				  "irq_stream1a",
+				  "irq_stream1b",	/* to M4? */
+				  "irq_reserved0",
+				  "irq_reserved1",
+				  "irq_blit",
+				  "irq_dpr0",
+				  "irq_dpr1";
+		clocks = <&clk IMX8QM_DC0_PLL0_CLK>,
+			 <&clk IMX8QM_DC0_PLL1_CLK>,
+			 <&clk IMX8QM_DC0_BYPASS_0_DIV>,
+			 <&clk IMX8QM_DC0_DISP0_SEL>,
+			 <&clk IMX8QM_DC0_DISP1_SEL>,
+			 <&clk IMX8QM_DC0_DISP0_CLK>,
+			 <&clk IMX8QM_DC0_DISP1_CLK>;
+		clock-names = "pll0", "pll1", "bypass0",
+			      "disp0_sel", "disp1_sel", "disp0", "disp1";
+		power-domains = <&pd_dc0_pll1>;
+		status = "disabled";
+
+		dpu1_disp0: port@0 {
+			reg = <0>;
+
+			dpu1_disp0_hdmi: endpoint@0 {
+				remote-endpoint = <&hdmi_disp>;
+			};
+
+			dpu1_disp0_mipi_dsi: endpoint@1 {
+				remote-endpoint = <&mipi_dsi1_in>;
+			};
+		};
+
+		dpu1_disp1: port@1 {
+			reg = <1>;
+
+			dpu1_disp1_lvds0: endpoint@0 {
+				remote-endpoint = <&ldb1_lvds0>;
+			};
+
+			dpu1_disp1_lvds1: endpoint@1 {
+				remote-endpoint = <&ldb1_lvds1>;
+			};
+		};
+	};
+
+	hdmi:hdmi@56268000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x56268000 0x0 0x100000>, /* HDP Controller */
+				<0x0 0x56261000 0x0 0x1000>; /* HDP SubSystem CSR  */
+		interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
+						<13 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "plug_in", "plug_out";
+		interrupt-parent = <&irqsteer_hdmi>;
+		status = "disabled";
+		clocks = <&clk IMX8QM_HDMI_DIG_PLL_CLK>,
+				<&clk IMX8QM_HDMI_AV_PLL_CLK>,
+				<&clk IMX8QM_HDMI_IPG_CLK>,
+				<&clk IMX8QM_HDMI_HDP_CORE_CLK>,
+				<&clk IMX8QM_HDMI_PXL_CLK>,
+				<&clk IMX8QM_HDMI_PXL_MUX_CLK>,
+				<&clk IMX8QM_HDMI_PXL_LINK_CLK>,
+				<&clk IMX8QM_HDMI_HDP_CLK>,
+				<&clk IMX8QM_HDMI_HDP_PHY_CLK>,
+				<&clk IMX8QM_HDMI_APB_CLK>,
+				<&clk IMX8QM_HDMI_LIS_IPG_CLK>,
+				<&clk IMX8QM_HDMI_MSI_HCLK>,
+				<&clk IMX8QM_HDMI_PXL_LPCG_CLK>,
+				<&clk IMX8QM_HDMI_PXL_EVEN_CLK>,
+				<&clk IMX8QM_HDMI_PXL_DBL_CLK>,
+				<&clk IMX8QM_HDMI_VIF_CLK>,
+				<&clk IMX8QM_HDMI_APB_MUX_CSR_CLK>,
+				<&clk IMX8QM_HDMI_APB_MUX_CTRL_CLK>,
+				<&clk IMX8QM_HDMI_I2S_CLK>,
+				<&clk IMX8QM_HDMI_I2S_BYPASS_CLK>;
+		clock-names = "dig_pll", "av_pll", "clk_ipg",
+						"clk_core", "clk_pxl", "clk_pxl_mux",
+						"clk_pxl_link", "clk_hdp", "clk_phy",
+						"clk_apb", "clk_lis","clk_msi",
+						"clk_lpcg", "clk_even","clk_dbl",
+						"clk_vif", "clk_apb_csr","clk_apb_ctrl",
+						"clk_i2s", "clk_i2s_bypass";
+		power-domains = <&pd_hdmi_i2s>;
+
+		port@0 {
+			reg = <0>;
+				hdmi_disp: endpoint {
+				remote-endpoint = <&dpu1_disp0_hdmi>;
+				};
+		};
+	};
+
+	irqsteer_dsi0: irqsteer@56220000 {
+		compatible = "nxp,imx-irqsteer";
+		reg = <0x0 0x56220000 0x0 0x1000>;
+		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#interrupt-cells = <2>;
+		clocks = <&clk IMX8QM_MIPI0_LIS_IPG_CLK>;
+		clock-names = "ipg";
+		power-domains = <&pd_mipi0>;
+	};
+
+	i2c0_mipi_dsi0: i2c@56226000 {
+		compatible = "fsl,imx8qm-lpi2c";
+		reg = <0x0 0x56226000 0x0 0x1000>;
+		interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&irqsteer_dsi0>;
+		clocks = <&clk IMX8QM_MIPI0_I2C0_CLK>,
+			 <&clk IMX8QM_MIPI0_I2C0_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_MIPI0_I2C0_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_mipi0_i2c0>;
+		status = "disabled";
+	};
+
+	mipi_dsi_csr1: csr@56221000 {
+		compatible = "fsl,imx8qm-mipi-dsi-csr", "syscon";
+		reg = <0x0 0x56221000 0x0 0x1000>;
+	};
+
+	mipi_dsi_phy1: dsi_phy@56228300 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "mixel,imx8qm-mipi-dsi-phy";
+		reg = <0x0 0x56228300 0x0 0x100>;
+		power-domains = <&pd_mipi0>;
+		#phy-cells = <0>;
+		status = "disabled";
+	};
+
+	mipi_dsi1: mipi_dsi@56228000 {
+		compatible = "fsl,imx8qm-mipi-dsi";
+		clocks =
+			<&clk IMX8QM_MIPI0_PXL_CLK>,
+			<&clk IMX8QM_MIPI0_BYPASS_CLK>,
+			<&clk IMX8QM_CLK_DUMMY>;
+		clock-names = "pixel", "bypass", "phy_ref";
+		power-domains = <&pd_mipi0>;
+		csr = <&mipi_dsi_csr1>;
+		phys = <&mipi_dsi_phy1>;
+		phy-names = "dphy";
+		pwr-delay = <100>;
+		status = "disabled";
+
+		port@0 {
+			mipi_dsi1_in: endpoint {
+				remote-endpoint = <&dpu1_disp0_mipi_dsi>;
+			};
+		};
+
+		port@1 {
+			mipi_dsi1_out: endpoint {
+				remote-endpoint = <&mipi_dsi_bridge1_in>;
+			};
+		};
+	};
+
+	mipi_dsi_bridge1: mipi_dsi_bridge@56228000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nwl,mipi-dsi";
+		reg = <0x0 0x56228000 0x0 0x300>;
+		interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&irqsteer_dsi0>;
+		clocks =
+			<&clk IMX8QM_MIPI0_BYPASS_CLK>,
+			<&clk IMX8QM_MIPI0_DSI_TX_ESC_CLK>,
+			<&clk IMX8QM_MIPI0_DSI_RX_ESC_CLK>;
+		clock-names = "phy_ref", "tx_esc", "rx_esc";
+		assigned-clocks = <&clk IMX8QM_MIPI0_DSI_TX_ESC_DIV>,
+				  <&clk IMX8QM_MIPI0_DSI_RX_ESC_DIV>;
+		assigned-clock-rates = <18000000>, <72000000>;
+		power-domains = <&pd_mipi0>;
+		phys = <&mipi_dsi_phy1>;
+		phy-names = "dphy";
+		status = "disabled";
+
+		port@0 {
+			mipi_dsi_bridge1_in: endpoint {
+				remote-endpoint = <&mipi_dsi1_out>;
+			};
+		};
+	};
+
+	lvds_region1: lvds_region@56240000 {
+		compatible = "fsl,imx8qm-lvds-region", "syscon";
+		reg = <0x0 0x56240000 0x0 0x10000>;
+	};
+
+	ldb1_phy: ldb_phy@56241000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "mixel,lvds-phy";
+		reg = <0x0 0x56241000 0x0 0x100>;
+		clocks = <&clk IMX8QM_LVDS0_PHY_CLK>;
+		clock-names = "phy";
+		power-domains = <&pd_lvds0>;
+		status = "disabled";
+
+		ldb1_phy1: port@0 {
+			reg = <0>;
+			#phy-cells = <0>;
+		};
+
+		ldb1_phy2: port@1 {
+			reg = <1>;
+			#phy-cells = <0>;
+		};
+	};
+
+	ldb1: ldb@562410e0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx8qm-ldb";
+		clocks = <&clk IMX8QM_LVDS0_PIXEL_CLK>,
+			 <&clk IMX8QM_LVDS0_BYPASS_CLK>;
+		clock-names = "pixel", "bypass";
+		power-domains = <&pd_lvds0>;
+		gpr = <&lvds_region1>;
+		status = "disabled";
+
+		lvds-channel@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			phys = <&ldb1_phy1>;
+			phy-names = "ldb_phy";
+			status = "disabled";
+
+			port@0 {
+				reg = <0>;
+
+				ldb1_lvds0: endpoint {
+					remote-endpoint = <&dpu1_disp1_lvds0>;
+				};
+			};
+		};
+
+		lvds-channel@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			phys = <&ldb1_phy2>;
+			phy-names = "ldb_phy";
+			status = "disabled";
+
+			port@0 {
+				reg = <0>;
+
+				ldb1_lvds1: endpoint {
+					remote-endpoint = <&dpu1_disp1_lvds1>;
+				};
+			};
+		};
+	};
+
+	lvds0_pwm: pwm@56244000 {
+		compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
+		reg = <0x0 0x56244000 0 0x1000>;
+		clocks = <&clk IMX8QM_LVDS0_PWM0_IPG_CLK>,
+			 <&clk IMX8QM_LVDS0_PWM0_CLK>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX8QM_LVDS0_PWM0_CLK>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <2>;
+		power-domains = <&pd_lvds0_pwm>;
+		status = "disabled";
+	};
+
+	dpu2_intsteer: dpu_intsteer@57000000 {
+		compatible = "fsl,imx8qm-dpu-intsteer", "syscon";
+		reg = <0x0 0x57000000 0x0 0x10000>;
+	};
+
+	dpu2: dpu@57180000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx8qm-dpu";
+		reg = <0x0 0x57180000 0x0 0x40000>;
+		intsteer = <&dpu2_intsteer>;
+		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "irq_common",
+				  "irq_stream0a",
+				  "irq_stream0b",	/* to M4? */
+				  "irq_stream1a",
+				  "irq_stream1b",	/* to M4? */
+				  "irq_reserved0",
+				  "irq_reserved1",
+				  "irq_blit",
+				  "irq_dpr0",
+				  "irq_dpr1";
+		clocks = <&clk IMX8QM_DC1_PLL0_CLK>,
+			 <&clk IMX8QM_DC1_PLL1_CLK>,
+			 <&clk IMX8QM_DC1_BYPASS_0_DIV>,
+			 <&clk IMX8QM_DC1_DISP0_SEL>,
+			 <&clk IMX8QM_DC1_DISP1_SEL>,
+			 <&clk IMX8QM_DC1_DISP0_CLK>,
+			 <&clk IMX8QM_DC1_DISP1_CLK>;
+		clock-names = "pll0", "pll1", "bypass0",
+			      "disp0_sel", "disp1_sel", "disp0", "disp1";
+		power-domains = <&pd_dc1_pll1>;
+		status = "disabled";
+
+		dpu2_disp0: port@0 {
+			reg = <0>;
+
+			dpu2_disp0_mipi_dsi: endpoint {
+				remote-endpoint = <&mipi_dsi2_in>;
+			};
+		};
+
+		dpu2_disp1: port@1 {
+			reg = <1>;
+
+			dpu2_disp1_lvds0: endpoint@0 {
+				remote-endpoint = <&ldb2_lvds0>;
+			};
+
+			dpu2_disp1_lvds1: endpoint@1 {
+				remote-endpoint = <&ldb2_lvds1>;
+			};
+		};
+	};
+
+	irqsteer_dsi1: irqsteer@57220000 {
+		compatible = "nxp,imx-irqsteer";
+		reg = <0x0 0x57220000 0x0 0x1000>;
+		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#interrupt-cells = <2>;
+		clocks = <&clk IMX8QM_MIPI1_LIS_IPG_CLK>;
+		clock-names = "ipg";
+		power-domains = <&pd_mipi1>;
+	};
+
+	i2c0_mipi_dsi1: i2c@57226000 {
+		compatible = "fsl,imx8qm-lpi2c";
+		reg = <0x0 0x57226000 0x0 0x1000>;
+		interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&irqsteer_dsi1>;
+		clocks = <&clk IMX8QM_MIPI1_I2C0_CLK>,
+			 <&clk IMX8QM_MIPI1_I2C0_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_MIPI1_I2C0_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_mipi1_i2c0>;
+		status = "disabled";
+	};
+
+	mipi_dsi_csr2: csr@57221000 {
+		compatible = "fsl,imx8qm-mipi-dsi-csr", "syscon";
+		reg = <0x0 0x57221000 0x0 0x1000>;
+	};
+
+	mipi_dsi_phy2: mipi_phy@57228300 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "mixel,imx8qm-mipi-dsi-phy";
+		reg = <0x0 0x57228300 0x0 0x100>;
+		power-domains = <&pd_mipi1>;
+		#phy-cells = <0>;
+		status = "disabled";
+	};
+
+	mipi_dsi2: mipi_dsi@57228000 {
+		compatible = "fsl,imx8qm-mipi-dsi";
+		clocks =
+			<&clk IMX8QM_MIPI1_PXL_CLK>,
+			<&clk IMX8QM_MIPI1_BYPASS_CLK>,
+			<&clk IMX8QM_CLK_DUMMY>;
+		clock-names = "pixel", "bypass", "phy_ref";
+		power-domains = <&pd_mipi1>;
+		csr = <&mipi_dsi_csr2>;
+		phys = <&mipi_dsi_phy2>;
+		phy-names = "dphy";
+		pwr-delay = <100>;
+		status = "disabled";
+
+		port@0 {
+			mipi_dsi2_in: endpoint {
+				remote-endpoint = <&dpu2_disp0_mipi_dsi>;
+			};
+		};
+
+		port@1 {
+			mipi_dsi2_out: endpoint {
+				remote-endpoint = <&mipi_dsi_bridge2_in>;
+			};
+		};
+	};
+
+	mipi_dsi_bridge2: mipi_dsi_bridge@57228000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nwl,mipi-dsi";
+		reg = <0x0 0x57228000 0x0 0x300>;
+		interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&irqsteer_dsi1>;
+		clocks =
+			<&clk IMX8QM_MIPI1_BYPASS_CLK>,
+			<&clk IMX8QM_MIPI1_DSI_TX_ESC_CLK>,
+			<&clk IMX8QM_MIPI1_DSI_RX_ESC_CLK>;
+		clock-names = "phy_ref", "tx_esc", "rx_esc";
+		assigned-clocks = <&clk IMX8QM_MIPI1_DSI_TX_ESC_DIV>,
+				  <&clk IMX8QM_MIPI1_DSI_RX_ESC_DIV>;
+		assigned-clock-rates = <18000000>, <72000000>;
+		power-domains = <&pd_mipi1>;
+		phys = <&mipi_dsi_phy2>;
+		phy-names = "dphy";
+		status = "disabled";
+
+		port@0 {
+			mipi_dsi_bridge2_in: endpoint {
+				remote-endpoint = <&mipi_dsi2_out>;
+			};
+		};
+	};
+
+	lvds_region2: lvds_region@57240000 {
+		compatible = "fsl,imx8qm-lvds-region", "syscon";
+		reg = <0x0 0x57240000 0x0 0x10000>;
+	};
+
+	ldb2_phy: ldb_phy@57241000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "mixel,lvds-phy";
+		reg = <0x0 0x57241000 0x0 0x100>;
+		clocks = <&clk IMX8QM_LVDS1_PHY_CLK>;
+		clock-names = "phy";
+		power-domains = <&pd_lvds1>;
+		status = "disabled";
+
+		ldb2_phy1: port@0 {
+			reg = <0>;
+			#phy-cells = <0>;
+		};
+
+		ldb2_phy2: port@1 {
+			reg = <1>;
+			#phy-cells = <0>;
+		};
+	};
+
+	ldb2: ldb@572410e0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx8qm-ldb";
+		clocks = <&clk IMX8QM_LVDS1_PIXEL_CLK>,
+			 <&clk IMX8QM_LVDS1_BYPASS_CLK>;
+		clock-names = "pixel", "bypass";
+		power-domains = <&pd_lvds1>;
+		gpr = <&lvds_region2>;
+		status = "disabled";
+
+		lvds-channel@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			phys = <&ldb2_phy1>;
+			phy-names = "ldb_phy";
+			status = "disabled";
+
+			port@0 {
+				reg = <0>;
+
+				ldb2_lvds0: endpoint {
+					remote-endpoint = <&dpu2_disp1_lvds0>;
+				};
+			};
+		};
+
+		lvds-channel@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			phys = <&ldb2_phy2>;
+			phy-names = "ldb_phy";
+			status = "disabled";
+
+			port@0 {
+				reg = <0>;
+
+				ldb2_lvds1: endpoint {
+					remote-endpoint = <&dpu2_disp1_lvds1>;
+				};
+			};
+		};
+	};
+
+	lvds1_pwm: pwm@57244000 {
+		compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
+		reg = <0x0 0x57244000 0 0x1000>;
+		clocks = <&clk IMX8QM_LVDS1_PWM0_IPG_CLK>,
+			 <&clk IMX8QM_LVDS1_PWM0_CLK>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX8QM_LVDS1_PWM0_CLK>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <2>;
+		power-domains = <&pd_lvds1_pwm>;
+		status = "disabled";
+	};
+
+	camera: camera {
+		compatible = "fsl,mxc-md", "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		isi_0: isi@58100000 {
+			compatible = "fsl,imx8-isi";
+			reg = <0x0 0x58100000 0x0 0x10000>;
+			interrupts = <0 297 0>;
+			interface = <2 0 2>;  /* <Input MIPI_VCx Output>
+									Input:  0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM
+									VCx:    0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only
+									Output: 0-DC0, 1-DC1, 2-MEM */
+			clocks = <&clk IMX8QM_IMG_PDMA_0_CLK>;
+			clock-names = "per";
+			assigned-clocks = <&clk IMX8QM_IMG_PDMA_0_CLK>;
+			assigned-clock-rates = <600000000>;
+			power-domains =<&pd_isi_ch0>;
+			status = "disabled";
+		};
+
+		hdmi_rx: hdmi_rx@58268000 {
+			compatible = "fsl,imx-hdmi-rx";
+			reg = <0x0 0x58268000 0x0 0x10000>, /* HDP Controller */
+					<0x0 0x58261000 0x0 0x1000>; /* HDP SubSystem CSR  */
+			interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
+							<13 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "plug_in", "plug_out";
+
+			interrupt-parent = <&irqsteer_hdmi_rx>;
+			clocks = <&clk IMX8QM_HDMI_RX_HD_REF_CLK>,
+						<&clk IMX8QM_HDMI_RX_HD_CORE_CLK>,
+						<&clk IMX8QM_HDMI_RX_PXL_CLK>,
+						<&clk IMX8QM_HDMI_RX_SINK_PCLK>,
+						<&clk IMX8QM_HDMI_RX_SINK_SCLK>,
+						<&clk IMX8QM_HDMI_RX_PXL_ENC_CLK>,
+						<&clk IMX8QM_HDMI_RX_I2S_CLK>,
+						<&clk IMX8QM_HDMI_RX_SPDIF_CLK>,
+						<&clk IMX8QM_IMG_PXL_LINK_HDMI_IN_CLK>;
+			clock-names = "ref_clk", "core_clk", "pxl_clk",
+							"pclk", "sclk", "enc_clk",
+							"i2s_clk", "spdif_clk",
+							"pxl_link_clk";
+			power-domains = <&pd_hdmi_rx_bypass>;
+			status = "disabled";
+		};
+	};
+
+	i2c0: i2c@5a800000 {
+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x0 0x5a800000 0x0 0x4000>;
+		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QM_I2C0_CLK>,
+			 <&clk IMX8QM_I2C0_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_I2C0_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_dma_lpi2c0>;
+		status = "disabled";
+	};
+
+	i2c1: i2c@5a810000 {
+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x0 0x5a810000 0x0 0x4000>;
+		interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QM_I2C1_CLK>,
+			 <&clk IMX8QM_I2C1_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_I2C1_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_dma_lpi2c1>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@5a820000 {
+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x0 0x5a820000 0x0 0x4000>;
+		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QM_I2C2_CLK>,
+			 <&clk IMX8QM_I2C2_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_I2C2_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_dma_lpi2c2>;
+		status = "disabled";
+	};
+
+	i2c3: i2c@5a830000 {
+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x0 0x5a830000 0x0 0x4000>;
+		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QM_I2C3_CLK>,
+			 <&clk IMX8QM_I2C3_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_I2C3_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_dma_lpi2c3>;
+		status = "disabled";
+	};
+
+	i2c4: i2c@5a840000 {
+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x0 0x5a840000 0x0 0x4000>;
+		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QM_I2C4_CLK>,
+			 <&clk IMX8QM_I2C4_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_I2C4_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_dma_lpi2c4>;
+		status = "disabled";
+	};
+
+	irqsteer_hdmi: irqsteer@56260000 {
+		compatible = "nxp,imx-irqsteer";
+		reg = <0x0 0x56260000 0x0 0x1000>;
+		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#interrupt-cells = <2>;
+		clocks = <&clk IMX8QM_HDMI_LIS_IPG_CLK>;
+		clock-names = "ipg";
+		assigned-clocks = <&clk IMX8QM_HDMI_DIG_PLL_CLK>,
+							<&clk IMX8QM_HDMI_LIS_IPG_CLK>;
+		assigned-clock-rates = <675000000>, <84375000>;
+		power-domains = <&pd_hdmi>;
+		status = "disabled";
+	};
+
+	irqsteer_hdmi_rx: irqsteer@58260000 {
+		compatible = "nxp,imx-irqsteer";
+		reg = <0x0 0x58260000 0x0 0x1000>;
+		interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		clocks = <&clk IMX8QM_HDMI_RX_IPG_CLK>;
+		clock-names = "ipg";
+		power-domains = <&pd_hdmi_rx>;
+	};
+
+
+	i2c0_hdmi: i2c@56266000 {
+		compatible = "fsl,imx8qm-lpi2c";
+		reg = <0x0 0x56266000 0x0 0x1000>;
+		interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&irqsteer_hdmi>;
+		clocks = <&clk IMX8QM_HDMI_I2C0_CLK>,
+			 <&clk IMX8QM_HDMI_I2C_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_HDMI_I2C0_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_hdmi_i2c0>;
+		status = "disabled";
+	};
+
+	irqsteer_lvds0: irqsteer@562400000 {
+		compatible = "nxp,imx-irqsteer";
+		reg = <0x0 0x56240000 0x0 0x1000>;
+		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#interrupt-cells = <2>;
+		clocks = <&clk IMX8QM_LVDS0_LIS_IPG_CLK>;
+		clock-names = "ipg";
+		power-domains = <&pd_lvds0>;
+	};
+
+
+	i2c1_lvds0: i2c@56247000 {
+		compatible = "fsl,imx8qm-lpi2c";
+		reg = <0x0 0x56247000 0x0 0x1000>;
+		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&irqsteer_lvds0>;
+		clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>,
+			 <&clk IMX8QM_LVDS0_I2C0_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_lvds0_i2c0>;
+		status = "disabled";
+	};
+
+	irqsteer_lvds1: irqsteer@572400000 {
+		compatible = "nxp,imx-irqsteer";
+		reg = <0x0 0x57240000 0x0 0x1000>;
+		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#interrupt-cells = <2>;
+		clocks = <&clk IMX8QM_LVDS1_LIS_IPG_CLK>;
+		clock-names = "ipg";
+		power-domains = <&pd_lvds1>;
+	};
+
+	i2c1_lvds1: i2c@57247000 {
+		compatible = "fsl,imx8qm-lpi2c";
+		reg = <0x0 0x57247000 0x0 0x1000>;
+		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&irqsteer_lvds1>;
+		clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>,
+			 <&clk IMX8QM_LVDS1_I2C0_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd_lvds1_i2c0>;
+		status = "disabled";
+	};
+
+	lpspi0: lpspi@5a000000 {
+		compatible = "fsl,imx7ulp-spi";
+		reg = <0x0 0x5a000000 0x0 0x10000>;
+		interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QM_SPI0_CLK>,
+			 <&clk IMX8QM_SPI0_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_SPI0_CLK>;
+		assigned-clock-rates = <20000000>;
+		power-domains = <&pd_dma0_chan1>;
+		dma-names = "tx","rx";
+		dmas = <&edma0 1 0 0>, <&edma0 0 0 1>;
+		status = "disabled";
+	};
+
+	lpspi3: lpspi@5a030000 {
+		compatible = "fsl,imx7ulp-spi";
+		reg = <0x0 0x5a030000 0x0 0x10000>;
+		interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+		clocks = <&clk IMX8QM_SPI3_CLK>,
+			 <&clk IMX8QM_SPI3_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_SPI3_CLK>;
+		assigned-clock-rates = <60000000>;
+		power-domains = <&pd_dma0_chan7>;
+		dma-names = "tx","rx";
+		dmas = <&edma0 7 0 0>, <&edma0 6 0 1>;
+		status = "disabled";
+	};
+
+	lpuart0: serial@5a060000 {
+		compatible = "fsl,imx8qm-lpuart";
+		reg = <0x0 0x5a060000 0x0 0x1000>;
+		interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wu>;
+		clocks = <&clk IMX8QM_UART0_CLK>,
+			 <&clk IMX8QM_UART0_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_UART0_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma_lpuart0>;
+		status = "disabled";
+	};
+
+	lpuart1: serial@5a070000 {
+		compatible = "fsl,imx8qm-lpuart";
+		reg = <0x0 0x5a070000 0x0 0x1000>;
+		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wu>;
+		clocks = <&clk IMX8QM_UART1_CLK>,
+			<&clk IMX8QM_UART1_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_UART1_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma0_chan15>;
+		dma-names = "tx","rx";
+		dmas = <&edma0 15 0 0>,
+			<&edma0 14 0 1>;
+		status = "disabled";
+	};
+
+	lpuart2: serial@5a080000 {
+		compatible = "fsl,imx8qm-lpuart";
+		reg = <0x0 0x5a080000 0x0 0x1000>;
+		interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wu>;
+		clocks = <&clk IMX8QM_UART2_CLK>,
+			<&clk IMX8QM_UART2_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_UART2_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma0_chan17>;
+		dma-names = "tx","rx";
+		dmas = <&edma0 17 0 0>,
+			<&edma0 16 0 1>;
+		status = "disabled";
+	};
+
+	lpuart3: serial@5a090000 {
+		compatible = "fsl,imx8qm-lpuart";
+		reg = <0x0 0x5a090000 0x0 0x1000>;
+		interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wu>;
+		clocks = <&clk IMX8QM_UART3_CLK>,
+			<&clk IMX8QM_UART3_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_UART3_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma0_chan19>;
+		dma-names = "tx","rx";
+		dmas = <&edma0 19 0 0>,
+			<&edma0 18 0 1>;
+		status = "disabled";
+	};
+
+	lpuart4: serial@5a0a0000 {
+		compatible = "fsl,imx8qm-lpuart";
+		reg = <0x0 0x5a0a0000 0x0 0x1000>;
+		interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&wu>;
+		clocks = <&clk IMX8QM_UART4_CLK>,
+			<&clk IMX8QM_UART4_IPG_CLK>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX8QM_UART4_CLK>;
+		assigned-clock-rates = <80000000>;
+		power-domains = <&pd_dma0_chan21>;
+		dma-names = "tx","rx";
+		dmas = <&edma0 21 0 0>,
+			<&edma0 20 0 1>;
+		status = "disabled";
+	};
+
+	edma0: dma-controller@5a1f0000 {
+		compatible = "fsl,imx8qm-edma";
+		reg = <0x0 0x5a200000 0x0 0x10000>, /* channel0 LPSPI0 rx */
+		      <0x0 0x5a210000 0x0 0x10000>, /* channel1 LPSPI0 tx */
+		      <0x0 0x5a260000 0x0 0x10000>, /* channel6 LPSPI3 rx */
+		      <0x0 0x5a270000 0x0 0x10000>, /* channel7 LPSPI3 tx */
+		      <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */
+		      <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */
+		      <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */
+		      <0x0 0x5a2f0000 0x0 0x10000>, /* channel15 UART1 tx */
+		      <0x0 0x5a300000 0x0 0x10000>, /* channel16 UART2 rx */
+		      <0x0 0x5a310000 0x0 0x10000>, /* channel17 UART2 tx */
+		      <0x0 0x5a320000 0x0 0x10000>, /* channel18 UART3 rx */
+		      <0x0 0x5a330000 0x0 0x10000>, /* channel19 UART3 tx */
+		      <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */
+		      <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */
+		#dma-cells = <3>;
+		dma-channels = <14>;
+		interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx",
+				  "edma0-chan6-rx", "edma0-chan7-tx",
+				  "edma0-chan12-rx", "edma0-chan13-tx",
+				  "edma0-chan14-rx", "edma0-chan15-tx",
+				  "edma0-chan16-rx", "edma0-chan17-tx",
+				  "edma0-chan18-rx", "edma0-chan19-tx",
+				  "edma0-chan20-rx", "edma0-chan21-tx";
+		status = "okay";
+	};
+
+	edma2: dma-controller@591F0000 {
+		compatible = "fsl,imx8qm-adma";
+		reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */
+			<0x0 0x59210000 0x0 0x10000>,
+			<0x0 0x59220000 0x0 0x10000>,
+			<0x0 0x59230000 0x0 0x10000>,
+			<0x0 0x59240000 0x0 0x10000>,
+			<0x0 0x59250000 0x0 0x10000>,
+			<0x0 0x59260000 0x0 0x10000>, /* esai0 rx */
+			<0x0 0x59270000 0x0 0x10000>, /* esai0 tx */
+			<0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */
+			<0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */
+			<0x0 0x592A0000 0x0 0x10000>, /* spdif1 rx */
+			<0x0 0x592B0000 0x0 0x10000>, /* spdif1 tx */
+			<0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */
+			<0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */
+			<0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */
+			<0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */
+			<0x0 0x59320000 0x0 0x10000>, /* sai4 rx */
+			<0x0 0x59330000 0x0 0x10000>; /* sai5 tx */
+		#dma-cells = <3>;
+		shared-interrupt;
+		dma-channels = <18>;
+		interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc0 */
+				<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */
+				<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
+				<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, /* spdif1 */
+				<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
+				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
+				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
+				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
+		interrupt-names = "edma2-chan0-rx", "edma2-chan1-rx", /* asrc0 */
+				"edma2-chan2-rx", "edma2-chan3-tx",
+				"edma2-chan4-tx", "edma2-chan5-tx",
+				"edma2-chan6-rx", "edma2-chan7-tx", /* esai0 */
+				"edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */
+				"edma2-chan10-rx", "edma2-chan11-tx", /* spdif1 */
+				"edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */
+				"edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */
+				"edma2-chan18-rx", "edma2-chan19-tx"; /* sai4, sai5 */
+		status = "okay";
+	};
+
+	edma3: dma-controller@599F0000 {
+		compatible = "fsl,imx8qm-adma";
+		reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */
+			<0x0 0x59A10000 0x0 0x10000>,
+			<0x0 0x59A20000 0x0 0x10000>,
+			<0x0 0x59A30000 0x0 0x10000>,
+			<0x0 0x59A40000 0x0 0x10000>,
+			<0x0 0x59A50000 0x0 0x10000>,
+			<0x0 0x59A80000 0x0 0x10000>, /* sai6 rx */
+			<0x0 0x59A90000 0x0 0x10000>, /* sai6 tx */
+			<0x0 0x59AA0000 0x0 0x10000>; /* sai7 tx */
+		#dma-cells = <3>;
+		shared-interrupt;
+		dma-channels = <9>;
+		interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc1 */
+				<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai6 */
+				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai7 */
+		interrupt-names = "edma3-chan0-rx", "edma3-chan1-rx", /* asrc1 */
+				"edma3-chan2-rx", "edma3-chan3-tx",
+				"edma3-chan4-tx", "edma3-chan5-tx",
+				"edma3-chan8-rx", "edma3-chan9-tx", /* sai6 */
+				"edma3-chan10-tx";                 /* sai7 */
+		status = "okay";
+	};
+
+	wu: wu {
+		compatible = "fsl,imx8-wu";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		interrupt-parent = <&gic>;
+	};
+
+	gpio0: gpio@5d080000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d080000 0x0 0x10000>;
+		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+                power-domains = <&pd_lsio_gpio0>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio1: gpio@5d090000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d090000 0x0 0x10000>;
+		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+                power-domains = <&pd_lsio_gpio1>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio2: gpio@5d0a0000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d0a0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+                power-domains = <&pd_lsio_gpio2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio3: gpio@5d0b0000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d0b0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+                power-domains = <&pd_lsio_gpio3>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio4: gpio@5d0c0000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d0c0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+                power-domains = <&pd_lsio_gpio4>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio5: gpio@5d0d0000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d0d0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+                power-domains = <&pd_lsio_gpio5>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio6: gpio@5d0e0000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d0e0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+                power-domains = <&pd_lsio_gpio6>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio7: gpio@5d0f0000 {
+		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
+		reg = <0x0 0x5d0f0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+                power-domains = <&pd_lsio_gpio7>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	mlb: mlb@5B060000 {
+		compatible = "fsl,imx6q-mlb150";
+		reg = <0x0 0x5B060000 0x0 0x10000>;
+		interrupt-parent = <&gic>;
+		interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>,
+			     <0 266 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QM_MLB_CLK>,
+			 <&clk IMX8QM_MLB_HCLK>,
+			 <&clk IMX8QM_MLB_IPG_CLK>;
+		clock-names = "mlb", "hclk", "ipg";
+		assigned-clocks = <&clk IMX8QM_MLB_CLK>,
+				  <&clk IMX8QM_MLB_HCLK>,
+				  <&clk IMX8QM_MLB_IPG_CLK>;
+		assigned-clock-rates = <333333333>, <333333333>, <83333333>;
+		power-domains = <&pd_conn_mlb0>;
+		status = "disabled";
+	};
+
+	usdhc1: usdhc@5b010000 {
+		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x0 0x5b010000 0x0 0x10000>;
+		clocks = <&clk IMX8QM_SDHC0_IPG_CLK>,
+			<&clk IMX8QM_SDHC0_CLK>,
+			<&clk IMX8QM_SDHC0_AHB_CLK>;
+		clock-names = "ipg", "per", "ahb";
+		assigned-clocks = <&clk IMX8QM_SDHC0_DIV>;
+		assigned-clock-rates = <400000000>;
+		power-domains = <&pd_conn_sdch0>;
+		fsl,tuning-start-tap = <20>;
+		fsl,tuning-step= <2>;
+		iommus = <&smmu 0x11 0x7f80>;
+		status = "disabled";
+	};
+
+	usdhc2: usdhc@5b020000 {
+		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x0 0x5b020000 0x0 0x10000>;
+		clocks = <&clk IMX8QM_SDHC1_IPG_CLK>,
+			<&clk IMX8QM_SDHC1_CLK>,
+			<&clk IMX8QM_SDHC1_AHB_CLK>;
+		clock-names = "ipg", "per", "ahb";
+		assigned-clocks = <&clk IMX8QM_SDHC1_DIV>;
+		assigned-clock-rates = <200000000>;
+		power-domains = <&pd_conn_sdch1>;
+		fsl,tuning-start-tap = <20>;
+		fsl,tuning-step= <2>;
+		iommus = <&smmu 0x11 0x7f80>;
+		status = "disabled";
+	};
+
+	usdhc3: usdhc@5b030000 {
+		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x0 0x5b030000 0x0 0x10000>;
+		clocks = <&clk IMX8QM_SDHC2_IPG_CLK>,
+			<&clk IMX8QM_SDHC2_CLK>,
+			<&clk IMX8QM_SDHC2_AHB_CLK>;
+		clock-names = "ipg", "per", "ahb";
+		assigned-clocks = <&clk IMX8QM_SDHC2_DIV>;
+		assigned-clock-rates = <200000000>;
+		power-domains = <&pd_conn_sdch2>;
+		iommus = <&smmu 0x11 0x7f80>;
+		status = "disabled";
+	};
+
+	fec1: ethernet@5b040000 {
+		compatible = "fsl,imx8qm-fec";
+		reg = <0x0 0x5b040000 0x0 0x10000>;
+		interrupt-parent = <&wu>;
+		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QM_ENET0_IPG_CLK>, <&clk IMX8QM_ENET0_AHB_CLK>, <&clk IMX8QM_ENET0_RGMII_TX_CLK>,
+			<&clk IMX8QM_ENET0_PTP_CLK>, <&clk IMX8QM_ENET0_TX_CLK>;
+		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
+		assigned-clocks = <&clk IMX8QM_ENET0_ROOT_DIV>,
+				  <&clk IMX8QM_ENET0_REF_DIV>;
+		assigned-clock-rates = <250000000>, <125000000>;
+		fsl,num-tx-queues=<3>;
+		fsl,num-rx-queues=<3>;
+		fsl,wakeup_irq = <0>;
+		power-domains = <&pd_conn_enet0>;
+		iommus = <&smmu 0x12 0x7f80>;
+		status = "disabled";
+	};
+
+	fec2: ethernet@5b050000 {
+		compatible = "fsl,imx8qm-fec";
+		reg = <0x0 0x5b050000 0x0 0x10000>;
+		interrupt-parent = <&wu>;
+		interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QM_ENET1_IPG_CLK>, <&clk IMX8QM_ENET1_AHB_CLK>, <&clk IMX8QM_ENET1_RGMII_TX_CLK>,
+			<&clk IMX8QM_ENET1_PTP_CLK>, <&clk IMX8QM_ENET1_TX_CLK>;
+		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
+		assigned-clocks = <&clk IMX8QM_ENET1_ROOT_DIV>,
+				  <&clk IMX8QM_ENET1_REF_DIV>;
+		assigned-clock-rates = <250000000>, <125000000>;
+		fsl,num-tx-queues=<3>;
+		fsl,num-rx-queues=<3>;
+		fsl,wakeup_irq = <0>;
+		power-domains = <&pd_conn_enet1>;
+		iommus = <&smmu 0x12 0x7f80>;
+		status = "disabled";
+	};
+
+	usbmisc1: usbmisc@5b0d0200 {
+		#index-cells = <1>;
+		compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc";
+		reg = <0x0 0x5b0d0200 0x0 0x200>;
+	};
+
+	usbmisc2: usbmisc@5b0e0200 {
+		#index-cells = <1>;
+		compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc";
+		reg = <0x0 0x5b0e0200 0x0 0x200>;
+	};
+
+	usbphy1: usbphy@0x5b100000 {
+		compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
+		reg = <0x0 0x5b100000 0x0 0x1000>;
+		clocks = <&clk IMX8QM_USB2_PHY_IPG_CLK>;
+		power-domains = <&pd_conn_usbotg0_phy>;
+	};
+
+	usbphynop1: usbphynop1 {
+		compatible = "usb-nop-xceiv";
+		clocks = <&clk IMX8QM_USB3_PHY_CLK>;
+		clock-names = "main_clk";
+		power-domains = <&pd_conn_usb2_phy>;
+	};
+
+	usbphynop2: usbphynop2 {
+		compatible = "usb-nop-xceiv";
+		clocks = <&clk IMX8QM_USB2_PHY_IPG_CLK>;
+		clock-names = "main_clk";
+		power-domains = <&pd_conn_usbotg0_phy>;
+	};
+
+	usbotg1: usb@5b0d0000 {
+		compatible = "fsl,imx8qm-usb", "fsl,imx27-usb";
+		reg = <0x0 0x5b0d0000 0x0 0x200>;
+		interrupt-parent = <&wu>;
+		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,usbphy = <&usbphy1>;
+		fsl,usbmisc = <&usbmisc1 0>;
+		clocks = <&clk IMX8QM_USB2_OH_AHB_CLK>;
+		ahb-burst-config = <0x0>;
+		tx-burst-size-dword = <0x10>;
+		rx-burst-size-dword = <0x10>;
+		#stream-id-cells = <1>;
+		power-domains = <&pd_conn_usbotg0>;
+		status = "disabled";
+	};
+
+	usbh1: usb@5b0e0000 {
+		compatible = "fsl,imx8qm-usb", "fsl,imx27-usb";
+		reg = <0x0 0x5b0e0000 0x0 0x200>;
+		interrupt-parent = <&wu>;
+		interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+		phy_type = "hsic";
+		dr_mode = "host";
+		fsl,usbphy = <&usbphynop2>;
+		fsl,usbmisc = <&usbmisc2 0>;
+		clocks = <&clk IMX8QM_USB2_OH_AHB_CLK>;
+		ahb-burst-config = <0x0>;
+		tx-burst-size-dword = <0x10>;
+		rx-burst-size-dword = <0x10>;
+		#stream-id-cells = <1>;
+		power-domains = <&pd_conn_usbh1>;
+		status = "disabled";
+	};
+
+	usbotg3: usb3@5b110000 {
+		compatible = "Cadence,usb3";
+		reg = <0x0 0x5B110000 0x0 0x10000>,
+			<0x0 0x5B130000 0x0 0x10000>,
+			<0x0 0x5B140000 0x0 0x10000>,
+			<0x0 0x5B160000 0x0 0x40000>,
+			<0x0 0x5B120000 0x0 0x10000>;
+		reg-names = "none-core", "xhci", "dev", "phy", "otg";
+		interrupt-parent = <&wu>;
+		interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QM_USB3_LPM_CLK>,
+			<&clk IMX8QM_USB3_BUS_CLK>,
+			<&clk IMX8QM_USB3_ACLK>,
+			<&clk IMX8QM_USB3_IPG_CLK>,
+			<&clk IMX8QM_USB3_CORE_PCLK>;
+		clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk",
+			"usb3_ipg_clk", "usb3_core_pclk";
+		assigned-clocks = <&clk IMX8QM_USB3_ACLK_DIV>,
+			   <&clk IMX8QM_USB3_LPM_DIV>,
+			   <&clk IMX8QM_USB3_BUS_DIV>;
+		assigned-clock-rates = <125000000>, <12000000>, <250000000>;
+		power-domains = <&pd_conn_usb2>;
+		cdns3,usbphy = <&usbphynop1>;
+		status = "disabled";
+	};
+
+	ddr_pmu0: ddr_pmu@5c020000 {
+		compatible = "fsl,imx8-ddr-pmu";
+		reg = <0x0 0x5c020000 0x0 0x10000>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	ddr_pmu1: ddr_pmu@5c120000 {
+		compatible = "fsl,imx8-ddr-pmu";
+		reg = <0x0 0x5c120000 0x0 0x10000>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	flexspi0: flexspi@05d120000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nxp,imx8qxp-fspi";
+		reg = <0x0 0x5d120000 0x0 0x10000>,
+			<0x0 0x08000000 0x0 0x19ffffff>;
+		reg-names = "fspi_base", "fspi_mmap";
+		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QM_FSPI0_CLK>,
+			<&clk IMX8QM_FSPI0_CLK>;
+		assigned-clocks = <&clk IMX8QM_FSPI0_DIV>;
+		assigned-clock-rates = <29000000>;
+		power-domains = <&pd_lsio_flexspi0>;
+		clock-names = "fspi", "fspi_en";
+		status = "disabled";
+	};
+
+	display: display-subsystem {
+		compatible = "fsl,imx-display-subsystem";
+		ports = <&dpu1_disp0>, <&dpu1_disp1>,
+			<&dpu2_disp0>, <&dpu2_disp1>;
+	};
+
+	dma_cap: dma_cap {
+		compatible = "dma-capability";
+		only-dma-mask32 = <1>;
+	};
+
+	hsio: hsio@5f080000 {
+		compatible = "fsl,imx8qm-hsio", "syscon";
+		reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */
+	};
+
+	ocotp: ocotp {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,imx8qm-ocotp", "syscon";
+	};
+
+	pciea: pcie@0x5f000000 {
+		compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
+		reg = <0x0 0x5f000000 0x0 0x10000>, /* Controller reg */
+		      <0x0 0x6ff00000 0x0 0x80000>; /* PCI cfg space */
+		reg-names = "dbi", "config";
+		reserved-region = <&rpmsg_reserved>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		ranges = <0x81000000 0 0x00000000 0x0 0x6ff80000 0 0x00010000 /* downstream I/O */
+			  0x82000000 0 0x60000000 0x0 0x60000000 0 0x0ff00000>; /* non-prefetchable memory */
+		num-lanes = <1>;
+
+		#interrupt-cells = <1>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+		interrupt-names = "msi";
+
+		/*
+		 * Set these clocks in default, then clocks should be
+		 * refined for exact hw design of imx8 pcie.
+		 */
+		clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>,
+			 <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>,
+			 <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>,
+			 <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>,
+			 <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>,
+			 <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>,
+			 <&clk IMX8QM_HSIO_MISC_PER_CLK>;
+		clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi",
+					"phy_per", "misc_per";
+		interrupt-map-mask = <0 0 0 0x7>;
+		interrupt-map =  <0 0 0 1 &gic 0 73 4>,
+				 <0 0 0 2 &gic 0 74 4>,
+				 <0 0 0 3 &gic 0 75 4>,
+				 <0 0 0 4 &gic 0 76 4>;
+		power-domains = <&pd_pcie1>;
+		fsl,max-link-speed = <3>;
+		hsio-cfg = <PCIEAX1PCIEBX1SATA>;
+		hsio = <&hsio>;
+		ctrl-id = <0>; /* pciea */
+		cpu-base-addr = <0x40000000>;
+		status = "disabled";
+	};
+
+	pcieb: pcie@0x5f010000 {
+		compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
+		reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg */
+		      <0x0 0x7ff00000 0x0 0x80000>; /* PCI cfg space */
+		reg-names = "dbi", "config";
+		reserved-region = <&rpmsg_reserved>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */
+			  0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */
+		num-lanes = <1>;
+
+		#interrupt-cells = <1>;
+		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+		interrupt-names = "msi";
+
+		/*
+		 * Set these clocks in default, then clocks should be
+		 * refined for exact hw design of imx8 pcie.
+		 */
+		clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>,
+			 <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>,
+			 <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>,
+			 <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>,
+			 <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>,
+			 <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>,
+			 <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>,
+			 <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>,
+			 <&clk IMX8QM_HSIO_MISC_PER_CLK>;
+		clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi",
+					"pciex2_per", "pcie_phy_pclk", "phy_per", "misc_per";
+		interrupt-map-mask = <0 0 0 0x7>;
+		interrupt-map =  <0 0 0 1 &gic 0 105 4>,
+				 <0 0 0 2 &gic 0 106 4>,
+				 <0 0 0 3 &gic 0 107 4>,
+				 <0 0 0 4 &gic 0 108 4>;
+		power-domains = <&pd_pcie1>;
+		fsl,max-link-speed = <3>;
+		hsio-cfg = <PCIEAX1PCIEBX1SATA>;
+		hsio = <&hsio>;
+		ctrl-id = <1>; /* pcieb */
+		cpu-base-addr = <0x80000000>;
+		status = "disabled";
+	};
+
+	sata: sata@5f020000 {
+		compatible = "fsl,imx8qm-ahci";
+		reg = <0x0 0x5f020000 0x0 0x10000>, /* Controller reg */
+			<0x0 0x5f1a0000 0x0 0x10000>; /* PHY reg */
+		reg-names = "ctl", "phy";
+		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX8QM_HSIO_SATA_CLK>,
+			 <&clk IMX8QM_HSIO_PHY_X1_PCLK>,
+			 <&clk IMX8QM_HSIO_SATA_EPCS_TX_CLK>,
+			 <&clk IMX8QM_HSIO_SATA_EPCS_RX_CLK>,
+			 <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>,
+			 <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>,
+			 <&clk IMX8QM_HSIO_PHY_X1_APB_CLK>;
+		clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx",
+				"phy_pclk0", "phy_pclk1", "phy_apbclk";
+		hsio = <&hsio>;
+		power-domains = <&pd_sata0>;
+		iommus = <&smmu 0x13 0x7f80>;
+		status = "disabled";
+	};
+
+	imx_rpmsg: imx_rpmsg {
+		compatible = "fsl,rpmsg-bus", "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		mu_rpmsg: mu_rpmsg@5d200000 {
+			compatible = "fsl,imx6sx-mu";
+			reg = <0x0 0x5d200000 0x0 0x10000>;
+			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8QM_LSIO_MU5A_IPG_CLK>;
+			clock-names = "ipg";
+			power-domains = <&pd_lsio_mu5a>;
+			status = "okay";
+		};
+
+		rpmsg: rpmsg {
+			compatible = "fsl,imx8qm-rpmsg";
+			power-domains = <&pd_lsio_mu5a>;
+			mub-partition = <3>;
+			memory-region = <&rpmsg_dma_reserved>;
+			status = "disabled";
+		};
+
+		mu_rpmsg1: mu_rpmsg1@5d210000 {
+			compatible = "fsl,imx-mu-rpmsg1";
+			reg = <0x0 0x5d210000 0x0 0x10000>;
+			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX8QM_LSIO_MU6A_IPG_CLK>;
+			clock-names = "ipg";
+			power-domains = <&pd_lsio_mu6a>;
+			status = "okay";
+		};
+
+		rpmsg1: rpmsg1{
+			compatible = "fsl,imx8qm-rpmsg";
+			multi-core-id = <1>;
+			mub-partition = <4>;
+			power-domains = <&pd_lsio_mu6a>;
+			memory-region = <&rpmsg_dma_reserved>;
+			status = "disabled";
+		};
+	};
+
+	crypto: caam@0x31400000 {
+		compatible = "fsl,sec-v4.0";
+		reg = <0 0x31400000 0 0x400000>;
+		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0x31400000 0x400000>;
+		fsl,first-jr-index = <2>;
+		fsl,sec-era = <9>;
+
+		sec_jr1: jr1@0x20000 {
+			compatible = "fsl,sec-v4.0-job-ring";
+			reg = <0x20000 0x1000>;
+			interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pd_caam_jr1>;
+			status = "disabled";
+		};
+
+		sec_jr2: jr2@30000 {
+			compatible = "fsl,sec-v4.0-job-ring";
+			reg = <0x30000 0x1000>;
+			interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pd_caam_jr2>;
+			status = "okay";
+		};
+
+		sec_jr3: jr3@40000 {
+			compatible = "fsl,sec-v4.0-job-ring";
+			reg = <0x40000 0x1000>;
+			interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pd_caam_jr3>;
+			status = "okay";
+		};
+	};
+
+	caam_sm: caam-sm@31800000 {
+		compatible = "fsl,imx6q-caam-sm";
+		reg = <0 0x31800000 0 0x10000>;
+	};
+
+	i2c_rpbus_0: i2c-rpbus-0 {
+		compatible = "fsl,i2c-rpbus";
+		status = "disabled";
+	};
+
+	i2c_rpbus_1: i2c-rpbus-1 {
+		compatible = "fsl,i2c-rpbus";
+		status = "disabled";
+	};
+
+	sc_pwrkey: sc-powerkey {
+		compatible = "fsl,imx8-pwrkey";
+		linux,keycode = <KEY_POWER>;
+		wakeup-source;
+	};
+
+	wdog: wdog {
+		compatible = "fsl,imx8-wdt";
+	};
diff --git a/arch/arm/dts/fsl-imx8qm-lpddr4-val-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-lpddr4-val-u-boot.dtsi
new file mode 100644
index 00000000000..beed9d85d69
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm-lpddr4-val-u-boot.dtsi
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+/ {
+
+	aliases {
+		usbhost1 = &usbh3;
+		usbgadget0 = &usbg1;
+	};
+
+	usbh3: usbh3 {
+		compatible = "Cadence,usb3-host";
+		dr_mode = "host";
+		cdns3,usb = <&usbotg3>;
+		status = "okay";
+	};
+
+	usbg1: usbg1 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg1>;
+		status = "okay";
+		u-boot,dm-spl;
+	};
+};
+
+&{/imx8qm-pm} {
+
+	u-boot,dm-spl;
+};
+
+&mu {
+	u-boot,dm-spl;
+};
+
+&clk {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&{/regulators} {
+	u-boot,dm-spl;
+};
+
+&reg_usdhc2_vmmc {
+	u-boot,dm-spl;
+};
+
+&{/mu@5d1c0000/iomuxc/imx8qm-val} {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_100mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_200mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_lpuart0 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_100mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_200mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_flexspi0 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_flexspi0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn {
+	u-boot,dm-spl;
+};
+
+&pd_dma {
+	u-boot,dm-spl;
+};
+
+&pd_dma_lpuart0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0_phy {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usb2 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usb2_phy {
+	u-boot,dm-spl;
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&gpio5 {
+	u-boot,dm-spl;
+};
+
+&lpuart0 {
+	u-boot,dm-spl;
+};
+
+&usbmisc1 {
+	u-boot,dm-spl;
+};
+
+&usbphy1 {
+	u-boot,dm-spl;
+};
+
+&usbotg1 {
+	u-boot,dm-spl;
+};
+
+&usbotg3 {
+	phys = <&usbphynop1>;
+	u-boot,dm-spl;
+};
+
+&usbphynop1 {
+	compatible = "cdns,usb3-phy";
+	reg = <0x0 0x5B160000 0x0 0x40000>;
+	#phy-cells = <0>;
+	u-boot,dm-spl;
+};
+
+&usdhc1 {
+	u-boot,dm-spl;
+	mmc-hs400-1_8v;
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
+};
+
+&usdhc3 {
+	u-boot,dm-spl;
+};
+
+&flexspi0 {
+	u-boot,dm-spl;
+};
+
+&flash0 {
+	u-boot,dm-spl;
+};
+
+&wu {
+	u-boot,dm-spl;
+};
+
+&fec1 {
+	phy-mode = "rgmii-id";
+};
+
+&fec2 {
+	phy-mode = "rgmii-id";
+};
+
+&ethphy0 {
+	vddio0: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
+
+&ethphy1 {
+	vddio1: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
\ No newline at end of file
diff --git a/arch/arm/dts/fsl-imx8qm-lpddr4-val.dts b/arch/arm/dts/fsl-imx8qm-lpddr4-val.dts
new file mode 100644
index 00000000000..2434c8d7754
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm-lpddr4-val.dts
@@ -0,0 +1,512 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017~2019 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qm.dtsi"
+
+/ {
+	model = "NXP i.MX8QM LPDDR4 VAL";
+	compatible = "fsl,imx8qm-val", "fsl,imx8qm";
+
+	aliases {
+		gpio8 = &pca9557_a;
+		gpio9 = &pca9557_b;
+		gpio10 = &pca9557_c;
+		gpio11 = &pca9557_d;
+	};
+
+	chosen {
+		bootargs = "console=ttyLP0,115200 earlycon";
+		stdout-path = &lpuart0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_leds>;
+		user {
+			label = "heartbeat";
+			gpios = <&gpio2 15 0>;
+			default-state = "on";
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usdhc2_vmmc: usdhc2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "sw-3p3-sd1";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+			off-on-delay-us = <4800>;
+			enable-active-high;
+		};
+
+	};
+
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	imx8qm-val {
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	  0x06000048
+				SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06	  0x06000021
+				SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07	  0x06000021
+				SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12	  0x06000021
+				SC_P_SPDIF0_TX_LSIO_GPIO2_IO15	  0x06000021
+			>;
+		};
+
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD	0x000014a0
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000060
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x00000060
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000060
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000060
+				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x00000060
+				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x00000060
+				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x00000060
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000060
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000060
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000060
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x00000060
+				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x00000060
+			>;
+		};
+
+		pinctrl_fec2: fec2grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD	0x000014a0
+				SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x00000060
+				SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC	0x00000060
+				SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0	0x00000060
+				SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1	0x00000060
+				SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2	0x00000060
+				SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3	0x00000060
+				SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC	0x00000060
+				SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x00000060
+				SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0	0x00000060
+				SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1	0x00000060
+				SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2	0x00000060
+				SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3	0x00000060
+			>;
+		};
+
+		pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
+			fsl,pins = <
+				SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL	0xc600004c
+				SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA	0xc600004c
+			>;
+		};
+
+		pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {
+			fsl,pins = <
+				SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL	0xc600004c
+				SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA	0xc600004c
+			>;
+		};
+
+		pinctrl_lpuart0: lpuart0grp {
+			fsl,pins = <
+				SC_P_UART0_RX_DMA_UART0_RX		0x06000020
+				SC_P_UART0_TX_DMA_UART0_TX		0x06000020
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grpgpio {
+			fsl,pins = <
+				SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21	0x00000021
+				SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22	0x00000021
+				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000040
+				SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000020
+				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000020
+				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000020
+				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000020
+				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000020
+				/* WP */
+				SC_P_USDHC2_WP_LSIO_GPIO4_IO11          0x00000021
+				/* CD */
+				SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12        0x00000021
+			>;
+		};
+
+		pinctrl_lpi2c1: lpi2c1grp {
+			fsl,pins = <
+				SC_P_GPT0_CLK_DMA_I2C1_SCL		0x06000020
+				SC_P_GPT0_CAPTURE_DMA_I2C1_SDA		0x06000020
+				/*
+				 * Change the default alt function from SCL/SDA to others,
+				 * to avoid select input conflict with GPT0
+				 */
+				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x0700004c
+				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04	0x0700004c
+				SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05	0x0700004c
+				SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06	0x0700004c
+			>;
+		};
+
+		pinctrl_lpspi0: lpspi0grp {
+			fsl,pins = <
+				SC_P_SPI0_SCK_DMA_SPI0_SCK		0x0600004c
+				SC_P_SPI0_SDO_DMA_SPI0_SDO		0x0600004c
+				SC_P_SPI0_SDI_DMA_SPI0_SDI		0x0600004c
+				SC_P_SPI0_CS0_DMA_SPI0_CS0		0x0600004c
+				SC_P_SPI0_CS1_DMA_SPI0_CS1		0x0600004c
+			>;
+		};
+
+		pinctrl_flexspi0: flexspi0grp {
+			fsl,pins = <
+				SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x06000021
+				SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x06000021
+				SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x06000021
+				SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x06000021
+				SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS		0x06000021
+				SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x06000021
+				SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B	0x06000021
+				SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x06000021
+				SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK	0x06000021
+				SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x06000021
+				SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x06000021
+				SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x06000021
+				SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x06000021
+				SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS		0x06000021
+				SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B	0x06000021
+				SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B	0x06000021
+			>;
+		};
+
+		pinctrl_gpio_leds: gpioledsgrp {
+			fsl,pins = <
+				SC_P_SPDIF0_TX_LSIO_GPIO2_IO15		0x00000021
+			>;
+		};
+	};
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	bus-width = <4>;
+	cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	disable-over-current;
+	status = "okay";
+};
+
+&usbotg3 {
+	status = "okay";
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-txid";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	fsl,rgmii_rxc_dly;
+	status = "okay";
+	phy-reset-gpios = <&pca9557_a 1 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <10>;
+	phy-reset-post-delay = <150>;
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			at803x,eee-disabled;
+			at803x,vddio-1p8v;
+		};
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			at803x,eee-disabled;
+			at803x,vddio-1p8v;
+			status = "disabled";
+		};
+	};
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec2>;
+	phy-mode = "rgmii-txid";
+	phy-handle = <&ethphy1>;
+	fsl,magic-packet;
+	fsl,rgmii_rxc_dly;
+	status = "okay";
+	phy-reset-gpios = <&pca9557_a 4 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <10>;
+	phy-reset-post-delay = <150>;
+};
+
+&flexspi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi0>;
+	status = "okay";
+
+	flash0: mt35xu512aba@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <8>;
+	};
+};
+
+&i2c1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c1>;
+	status = "okay";
+
+	pca9557_a: gpio@18 {
+		compatible = "nxp,pca9557";
+		reg = <0x18>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pca9557_b: gpio@19 {
+		compatible = "nxp,pca9557";
+		reg = <0x19>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pca9557_c: gpio@1b {
+		compatible = "nxp,pca9557";
+		reg = <0x1b>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pca9557_d: gpio@1f {
+		compatible = "nxp,pca9557";
+		reg = <0x1f>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&i2c1_lvds0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	lvds-to-hdmi-bridge@4c {
+		compatible = "ite,it6263";
+		reg = <0x4c>;
+	};
+};
+
+&i2c1_lvds1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lvds1_lpi2c1>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	lvds-to-hdmi-bridge@4c {
+		compatible = "ite,it6263";
+		reg = <0x4c>;
+	};
+};
+
+&lpspi0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpspi0>;
+	status = "okay";
+
+	spidev0: spi@0 {
+		reg = <0>;
+		compatible = "rohm,dh2228fv";
+		spi-max-frequency = <4000000>;
+	};
+};
+
+&lpuart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart0>;
+	status = "okay";
+};
+
+&lpuart1 {
+	status = "okay";
+};
+
diff --git a/arch/arm/dts/fsl-imx8qm-mek-cockpit-a53-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-cockpit-a53-u-boot.dtsi
new file mode 100644
index 00000000000..f87a4f6bcfb
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm-mek-cockpit-a53-u-boot.dtsi
@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+/ {
+
+	aliases {
+		usbhost1 = &usbh3;
+		usbgadget0 = &usbg1;
+	};
+
+	usbh3: usbh3 {
+		compatible = "Cadence,usb3-host";
+		dr_mode = "host";
+		cdns3,usb = <&usbotg3>;
+		status = "okay";
+	};
+
+	usbg1: usbg1 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg1>;
+		status = "okay";
+		u-boot,dm-spl;
+	};
+};
+
+&{/imx8qm-pm} {
+
+	u-boot,dm-spl;
+};
+
+&mu {
+	u-boot,dm-spl;
+};
+
+&clk {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&{/regulators} {
+	u-boot,dm-spl;
+};
+
+&reg_usdhc2_vmmc {
+	u-boot,dm-spl;
+};
+
+&{/mu@5d1c0000/iomuxc/imx8qm-mek} {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_100mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_200mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_lpuart0 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_flexspi0 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio1 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_flexspi0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+	u-boot,dm-spl;
+};
+
+&pd_dma {
+	u-boot,dm-spl;
+};
+
+&pd_dma_lpuart0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0_phy {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usb2 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usb2_phy {
+	u-boot,dm-spl;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&gpio5 {
+	u-boot,dm-spl;
+};
+
+&lpuart0 {
+	u-boot,dm-spl;
+};
+
+&usbmisc1 {
+	u-boot,dm-spl;
+};
+
+&usbphy1 {
+	u-boot,dm-spl;
+};
+
+&usbotg1 {
+	u-boot,dm-spl;
+};
+
+&usbotg3 {
+	phys = <&usbphynop1>;
+	u-boot,dm-spl;
+};
+
+&usbphynop1 {
+	compatible = "cdns,usb3-phy";
+	reg = <0x0 0x5B160000 0x0 0x40000>;
+	#phy-cells = <0>;
+	u-boot,dm-spl;
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
+};
+
+&flexspi0 {
+	u-boot,dm-spl;
+};
+
+&flash0 {
+	u-boot,dm-spl;
+};
+
+&wu {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/fsl-imx8qm-mek-cockpit-a53.dts b/arch/arm/dts/fsl-imx8qm-mek-cockpit-a53.dts
new file mode 100644
index 00000000000..5c8f8169b73
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm-mek-cockpit-a53.dts
@@ -0,0 +1,471 @@
+/*
+ * Copyright 2017-2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qm-cockpit-a53.dtsi"
+
+/ {
+	model = "Freescale i.MX8QM MEK";
+	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
+
+	chosen {
+		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
+		stdout-path = &lpuart0;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usdhc2_vmmc: usdhc2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "sw-3p3-sd1";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			startup-delay-us = <100>;
+			u-boot,off-on-delay-us = <12000>;
+		};
+
+		epdev_on: fixedregulator@100 {
+			compatible = "regulator-fixed";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&pinctrl_wlreg_on>;
+			pinctrl-1 = <&pinctrl_wlreg_on_sleep>;
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-name = "epdev_on";
+			gpio = <&gpio1 13 0>;
+			enable-active-high;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx8qm-mek {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06	  0x06000021
+				SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07	  0x06000021
+				SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20		  0x06000021
+				SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24		  0x06000021
+				SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23		  0x06000021
+			>;
+		};
+
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD	0x000014a0
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000061
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x00000061
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000061
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000061
+				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x00000061
+				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x00000061
+				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x00000061
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000061
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000061
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000061
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x00000061
+				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x00000061
+			>;
+		};
+
+		pinctrl_flexspi0: flexspi0grp {
+			fsl,pins = <
+				SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x06000021
+				SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x06000021
+				SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x06000021
+				SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x06000021
+				SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS		0x06000021
+				SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x06000021
+				SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B	0x06000021
+				SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x06000021
+				SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK	0x06000021
+				SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x06000021
+				SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x06000021
+				SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x06000021
+				SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x06000021
+				SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS		0x06000021
+				SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B	0x06000021
+				SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B	0x06000021
+			>;
+		};
+
+		pinctrl_lpuart0: lpuart0grp {
+			fsl,pins = <
+				SC_P_UART0_RX_DMA_UART0_RX		0x06000020
+				SC_P_UART0_TX_DMA_UART0_TX		0x06000020
+			>;
+		};
+
+		pinctrl_i2c0: i2c0grp {
+			fsl,pins = <
+				SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL	0x06000021
+				SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA	0x06000021
+			>;
+		};
+
+		pinctrl_pciea: pcieagrp{
+			fsl,pins = <
+				SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27	0x06000021
+				SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28		0x04000021
+				SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29		0x06000021
+				SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09		0x06000021
+			>;
+		};
+
+		pinctrl_typec: typecgrp {
+			fsl,pins = <
+				SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19	0x60
+				SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06	0x60
+				SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26	0x00000021
+			>;
+		};
+
+		pinctrl_usbotg1: usbotg1 {
+			fsl,pins = <
+				SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grpgpio {
+			fsl,pins = <
+				SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21	0x00000021
+				SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22	0x00000021
+				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
+			>;
+		};
+		pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
+			fsl,pins = <
+				SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL	0xc600004c
+				SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA	0xc600004c
+			>;
+		};
+
+		pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {
+			fsl,pins = <
+				SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL	0xc600004c
+				SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA	0xc600004c
+			>;
+		};
+
+		pinctrl_wlreg_on: wlregongrp{
+			fsl,pins = <
+				SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13		0x06000000
+			>;
+		};
+
+		pinctrl_wlreg_on_sleep: wlregon_sleepgrp{
+			fsl,pins = <
+				SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13		0x07800000
+			>;
+		};
+	};
+};
+
+&gpio0 {
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&gpio6 {
+};
+
+&gpio7 {
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	disable-over-current;
+	status = "okay";
+};
+
+&usbotg3 {
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	/delete-property/ iommus;
+	status = "okay";
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-txid";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	fsl,rgmii_rxc_dly;
+	/delete-property/ iommus;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			at803x,eee-disabled;
+			at803x,vddio-1p8v;
+		};
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			at803x,eee-disabled;
+			at803x,vddio-1p8v;
+		};
+	};
+};
+
+&flexspi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi0>;
+	status = "okay";
+
+	flash0: mt35xu512aba@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <8>;
+	};
+};
+
+&i2c0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0>;
+	status = "okay";
+
+	max7322: gpio@68 {
+		compatible = "maxim,max7322";
+		reg = <0x68>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	typec_ptn5110: typec@50 {
+		compatible = "usb,tcpci";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_typec>;
+		reg = <0x51>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+		ss-sel-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
+		reset-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+		src-pdos = <0x380190c8 0x3803c0c8>;
+		port-type = "drp";
+		sink-disable;
+		default-role = "source";
+		status = "okay";
+	};
+};
+
+&lpuart0 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart0>;
+	status = "okay";
+};
+
+&i2c1_lvds0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	lvds-to-hdmi-bridge@4c {
+		compatible = "ite,it6263";
+		reg = <0x4c>;
+	};
+};
+
+&i2c1_lvds1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lvds1_lpi2c1>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	lvds-to-hdmi-bridge@4c {
+		compatible = "ite,it6263";
+		reg = <0x4c>;
+	};
+};
+
+&pciea{
+	ext_osc = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pciea>;
+	disable-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
+	reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
+	clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
+	epdev_on = <&epdev_on>;
+	status = "okay";
+};
+
+&sata {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pciea>;
+	clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
+	/delete-property/ iommus;
+	status = "okay";
+};
+
+&tsens {
+	tsens-num = <6>;
+};
+
+&thermal_zones {
+	pmic-thermal0 {
+		polling-delay-passive = <250>;
+		polling-delay = <2000>;
+		thermal-sensors = <&tsens 5>;
+		trips {
+			pmic_alert0: trip0 {
+				temperature = <110000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+			pmic_crit0: trip1 {
+				temperature = <125000>;
+				hysteresis = <2000>;
+				type = "critical";
+			};
+		};
+		cooling-maps {
+			map0 {
+				trip = <&pmic_alert0>;
+				cooling-device =
+				<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			};
+			map1 {
+				trip = <&pmic_alert0>;
+				cooling-device =
+				<&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+};
+
+&display {
+	ports = <&dpu1_disp0>, <&dpu1_disp1>;
+};
+
+/delete-node/ &dpu2;
+/delete-node/ &fec2;
+/delete-node/ &ldb2;
+/delete-node/ &isi_0;
+/delete-node/ &lpuart2;
+/delete-node/ &i2c1;
+/delete-node/ &usdhc1;
+/delete-node/ &i2c0;
+/delete-node/ &i2c1_lvds1;
+/delete-node/ &dpu2_intsteer;
+/delete-node/ &lvds_region2;
+/delete-node/ &ldb2_phy;
+/delete-node/ &irqsteer_lvds1;
+/delete-node/ &mipi_dsi2;
+/delete-node/ &mipi_dsi_bridge2;
+/delete-node/ &pinctrl_lvds1_lpi2c1;
diff --git a/arch/arm/dts/fsl-imx8qm-mek-cockpit-a72-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-cockpit-a72-u-boot.dtsi
new file mode 100644
index 00000000000..b64b21fa450
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm-mek-cockpit-a72-u-boot.dtsi
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+/ {
+
+	aliases {
+		usbhost1 = &usbh3;
+		usbgadget0 = &usbg1;
+	};
+
+	usbh3: usbh3 {
+		compatible = "Cadence,usb3-host";
+		dr_mode = "host";
+		cdns3,usb = <&usbotg3>;
+		status = "okay";
+	};
+
+	usbg1: usbg1 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg1>;
+		status = "okay";
+		u-boot,dm-spl;
+	};
+};
+
+&{/imx8qm-pm} {
+
+	u-boot,dm-spl;
+};
+
+&mu {
+	u-boot,dm-spl;
+};
+
+&clk {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&{/regulators} {
+	u-boot,dm-spl;
+};
+
+&{/mu@5d1d0000/iomuxc/imx8qm-mek} {
+	u-boot,dm-spl;
+};
+
+&pinctrl_lpuart2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_100mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_200mhz {
+	u-boot,dm-spl;
+};
+
+&pd_lsio {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio1 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_flexspi0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+	u-boot,dm-spl;
+};
+
+&pd_dma {
+	u-boot,dm-spl;
+};
+
+&pd_dma_lpuart2 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0_phy {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usb2 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usb2_phy {
+	u-boot,dm-spl;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&gpio5 {
+	u-boot,dm-spl;
+};
+
+&lpuart2 {
+	u-boot,dm-spl;
+};
+
+&usbmisc1 {
+	u-boot,dm-spl;
+};
+
+&usbphy1 {
+	u-boot,dm-spl;
+};
+
+&usbotg1 {
+	u-boot,dm-spl;
+};
+
+&usbotg3 {
+	u-boot,dm-spl;
+};
+
+&usbphynop1 {
+	u-boot,dm-spl;
+};
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
+
+&wu {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/fsl-imx8qm-mek-cockpit-a72.dts b/arch/arm/dts/fsl-imx8qm-mek-cockpit-a72.dts
new file mode 100644
index 00000000000..ce3e2a1d99e
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm-mek-cockpit-a72.dts
@@ -0,0 +1,406 @@
+/*
+ * Copyright 2017-2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qm-cockpit-a72.dtsi"
+
+/ {
+	model = "Freescale i.MX8QM MEK";
+	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
+
+	aliases {
+		gpio8 = &max7322;
+	};
+
+	chosen {
+		bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
+		stdout-path = &lpuart2;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			status = "disabled";
+		};
+
+		epdev_on: fixedregulator@100 {
+			compatible = "regulator-fixed";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&pinctrl_wlreg_on>;
+			pinctrl-1 = <&pinctrl_wlreg_on_sleep>;
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-name = "epdev_on";
+			gpio = <&gpio1 13 0>;
+			enable-active-high;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	imx8qm-mek {
+		pinctrl_fec2: fec2grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD	0x000014a0
+				SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x00000060
+				SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC	0x00000060
+				SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0	0x00000060
+				SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1	0x00000060
+				SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2	0x00000060
+				SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3	0x00000060
+				SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC	0x00000060
+				SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x00000060
+				SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0	0x00000060
+				SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1	0x00000060
+				SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2	0x00000060
+				SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3	0x00000060
+			>;
+		};
+
+		pinctrl_lpuart2: lpuart2grp {
+			fsl,pins = <
+				SC_P_UART0_RTS_B_DMA_UART2_RX		0x06000020
+				SC_P_UART0_CTS_B_DMA_UART2_TX		0x06000020
+			>;
+		};
+
+		pinctrl_i2c0: i2c0grp {
+			fsl,pins = <
+				SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL	0x06000021
+				SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA	0x06000021
+			>;
+		};
+
+		pinctrl_pciea: pcieagrp{
+			fsl,pins = <
+				SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27	0x06000021
+				SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28		0x04000021
+				SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29		0x06000021
+				SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09		0x06000021
+			>;
+		};
+
+		pinctrl_typec: typecgrp {
+			fsl,pins = <
+				SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19	0x60
+				SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06	0x60
+				SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26	0x00000021
+			>;
+		};
+
+		pinctrl_usbotg1: usbotg1 {
+			fsl,pins = <
+				SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+			>;
+		};
+
+		pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
+			fsl,pins = <
+				SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL	0xc600004c
+				SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA	0xc600004c
+			>;
+		};
+
+		pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {
+			fsl,pins = <
+				SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL	0xc600004c
+				SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA	0xc600004c
+			>;
+		};
+
+		pinctrl_wlreg_on: wlregongrp{
+			fsl,pins = <
+				SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13		0x06000000
+			>;
+		};
+
+		pinctrl_wlreg_on_sleep: wlregon_sleepgrp{
+			fsl,pins = <
+				SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13		0x07800000
+			>;
+		};
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+};
+
+&gpio2 {
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+};
+
+&gpio5 {
+};
+
+&gpio6 {
+	status = "okay";
+};
+
+&gpio7 {
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	disable-over-current;
+	status = "disabled";
+};
+
+&usbotg3 {
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	/delete-property/ iommus;
+	status = "okay";
+};
+
+&i2c0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0>;
+	status = "okay";
+
+	max7322: gpio@68 {
+		compatible = "maxim,max7322";
+		reg = <0x68>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	typec_ptn5110: typec@50 {
+		compatible = "usb,tcpci";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_typec>;
+		reg = <0x51>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+		ss-sel-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
+		reset-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+		src-pdos = <0x380190c8 0x3803c0c8>;
+		port-type = "drp";
+		sink-disable;
+		default-role = "source";
+		status = "okay";
+	};
+};
+
+&lpuart2 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart2>;
+	status = "okay";
+};
+
+&i2c1_lvds0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	lvds-to-hdmi-bridge@4c {
+		compatible = "ite,it6263";
+		reg = <0x4c>;
+	};
+};
+
+&i2c1_lvds1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lvds1_lpi2c1>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	lvds-to-hdmi-bridge@4c {
+		compatible = "ite,it6263";
+		reg = <0x4c>;
+	};
+};
+
+&pciea{
+	ext_osc = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pciea>;
+	disable-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
+	reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
+	clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
+	epdev_on = <&epdev_on>;
+	status = "okay";
+};
+
+&sata {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pciea>;
+	clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
+	/delete-property/ iommus;
+	status = "okay";
+};
+
+&tsens {
+	tsens-num = <6>;
+};
+
+&thermal_zones {
+	pmic-thermal0 {
+		polling-delay-passive = <250>;
+		polling-delay = <2000>;
+		thermal-sensors = <&tsens 5>;
+		trips {
+			pmic_alert0: trip0 {
+				temperature = <110000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+			pmic_crit0: trip1 {
+				temperature = <125000>;
+				hysteresis = <2000>;
+				type = "critical";
+			};
+		};
+		cooling-maps {
+			map0 {
+				trip = <&pmic_alert0>;
+				cooling-device =
+				<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			};
+			map1 {
+				trip = <&pmic_alert0>;
+				cooling-device =
+				<&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+};
+
+&display {
+	ports = <&dpu2_disp0>, <&dpu2_disp1>;
+};
+
+
+/delete-node/ &dpu1;
+/delete-node/ &fec1;
+/delete-node/ &ldb1;
+/delete-node/ &isi_0;
+/delete-node/ &lpuart0;
+/delete-node/ &lpuart1;
+/delete-node/ &lpuart3;
+/delete-node/ &lpuart4;
+/delete-node/ &i2c2;
+/delete-node/ &i2c3;
+/delete-node/ &i2c4;
+/delete-node/ &i2c1_lvds0;
+/delete-node/ &usdhc2;
+/delete-node/ &usdhc3;
+/delete-node/ &flexspi0;
+/delete-node/ &dpu1_intsteer;
+/delete-node/ &lvds_region1;
+/delete-node/ &ldb1_phy;
+/delete-node/ &hdmi;
+/delete-node/ &i2c0_hdmi;
+/delete-node/ &irqsteer_lvds0;
+/delete-node/ &mipi_dsi1;
+/delete-node/ &mipi_dsi_bridge1;
+/delete-node/ &i2c0_mipi_dsi0;
+/delete-node/ &lpspi0;
+/delete-node/ &mlb;
+/delete-node/ &pciea;
+/delete-node/ &pcieb;
+/delete-node/ &pinctrl_lvds0_lpi2c1;
diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
index 9e0d264b71f..c3986526b65 100644
--- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
@@ -1,8 +1,31 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  */
 
+/ {
+
+	aliases {
+		usbhost1 = &usbh3;
+		usbgadget0 = &usbg1;
+	};
+
+	usbh3: usbh3 {
+		compatible = "Cadence,usb3-host";
+		dr_mode = "host";
+		cdns3,usb = <&usbotg3>;
+		status = "okay";
+	};
+
+	usbg1: usbg1 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg1>;
+		status = "okay";
+		u-boot,dm-spl;
+	};
+};
+
 &{/imx8qm-pm} {
 
 	u-boot,dm-spl;
@@ -20,6 +43,38 @@
 	u-boot,dm-spl;
 };
 
+&{/regulators} {
+	u-boot,dm-spl;
+};
+
+&reg_usdhc2_vmmc {
+	u-boot,dm-spl;
+};
+
+&{/mu@5d1c0000/iomuxc/imx8qm-mek} {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_lpuart0 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_flexspi0 {
+	u-boot,dm-spl;
+};
+
 &pd_lsio {
 	u-boot,dm-spl;
 };
@@ -56,6 +111,10 @@
 	u-boot,dm-spl;
 };
 
+&pd_lsio_flexspi0 {
+	u-boot,dm-spl;
+};
+
 &pd_conn {
 	u-boot,dm-spl;
 };
@@ -80,6 +139,38 @@
 	u-boot,dm-spl;
 };
 
+&pd_caam {
+	u-boot,dm-spl;
+};
+
+&pd_caam_jr1 {
+	u-boot,dm-spl;
+};
+
+&pd_caam_jr2 {
+	u-boot,dm-spl;
+};
+
+&pd_caam_jr3 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0_phy {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usb2 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usb2_phy {
+	u-boot,dm-spl;
+};
+
 &gpio0 {
 	u-boot,dm-spl;
 };
@@ -116,6 +207,30 @@
 	u-boot,dm-spl;
 };
 
+&usbmisc1 {
+	u-boot,dm-spl;
+};
+
+&usbphy1 {
+	u-boot,dm-spl;
+};
+
+&usbotg1 {
+	u-boot,dm-spl;
+};
+
+&usbotg3 {
+	phys = <&usbphynop1>;
+	u-boot,dm-spl;
+};
+
+&usbphynop1 {
+	compatible = "cdns,usb3-phy";
+	reg = <0x0 0x5B160000 0x0 0x40000>;
+	#phy-cells = <0>;
+	u-boot,dm-spl;
+};
+
 &usdhc1 {
 	u-boot,dm-spl;
 	mmc-hs400-1_8v;
@@ -126,3 +241,55 @@
 	sd-uhs-sdr104;
 	sd-uhs-ddr50;
 };
+
+&crypto {
+	u-boot,dm-spl;
+};
+
+&sec_jr1 {
+	u-boot,dm-spl;
+};
+
+&sec_jr2 {
+	u-boot,dm-spl;
+};
+
+&sec_jr3 {
+	u-boot,dm-spl;
+};
+
+&flexspi0 {
+	u-boot,dm-spl;
+};
+
+&flash0 {
+	u-boot,dm-spl;
+};
+
+&wu {
+	u-boot,dm-spl;
+};
+
+&fec1 {
+	phy-mode = "rgmii-id";
+};
+
+&fec2 {
+	phy-mode = "rgmii-id";
+};
+
+&ethphy0 {
+	vddio0: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
+
+&ethphy1 {
+	vddio1: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
diff --git a/arch/arm/dts/fsl-imx8qm-mek-xen.dts b/arch/arm/dts/fsl-imx8qm-mek-xen.dts
new file mode 100644
index 00000000000..56a3e085269
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm-mek-xen.dts
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "fsl-imx8qm-mek.dts"
+#include "fsl-imx8qm-mek-u-boot.dtsi"
+
+/ {
+	chosen {
+		bootargs = "console=hvc0 earlycon=hvc0 androidboot.console=hvc0 androidboot.android_dt_dir=/proc/device-tree/firmware/android/ androidboot.selinux=permissive";
+	};
+};
+
+&usdhc2 {
+	status = "disabled";
+};
+
+&gpio1 {
+	/delete-property/ power-domains;
+};
+
+&gpio2 {
+	status = "disabled";
+};
+
+&gpio4 {
+	/delete-property/ power-domains;
+	status = "okay";
+};
+
+&gpio5 {
+	status = "disabled";
+};
+
+&usbotg3 {
+	status = "disabled";
+};
+
+&fec1 {
+	status = "disabled";
+};
+
+&fec2 {
+	status = "disabled";
+};
+
+&flexspi0 {
+	status = "disabled";
+};
+
+&i2c0 {
+	status = "disabled";
+};
+
+&i2c1_lvds0 {
+	status = "disabled";
+};
+
+&i2c1_lvds1 {
+	status = "disabled";
+};
+
+&lpspi0 {
+	status = "disabled";
+};
+
+&lpuart0 {
+	compatible = "xen,xen";
+	/delete-property/ power-domains;
+	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
+};
+
+&mu {
+	reg = <0x0 0x5d1d0000 0x0 0x10000>;
+};
diff --git a/arch/arm/dts/fsl-imx8qm-mek.dts b/arch/arm/dts/fsl-imx8qm-mek.dts
index 63908ba6bf1..cc59a44ea4b 100644
--- a/arch/arm/dts/fsl-imx8qm-mek.dts
+++ b/arch/arm/dts/fsl-imx8qm-mek.dts
@@ -6,25 +6,56 @@
 /dts-v1/;
 
 #include "fsl-imx8qm.dtsi"
-#include "fsl-imx8qm-mek-u-boot.dtsi"
 
 / {
-	model = "Freescale i.MX8QM MEK";
+	model = "NXP i.MX8QM MEK";
 	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
 
+	aliases {
+		gpio8 = &max7322;
+	};
+
 	chosen {
-		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
+		bootargs = "console=ttyLP0,115200 earlycon";
 		stdout-path = &lpuart0;
 	};
 
-	reg_usdhc2_vmmc: usdhc2_vmmc {
-		compatible = "regulator-fixed";
-		regulator-name = "sw-3p3-sd1";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
-		off-on-delay = <4800>;
-		enable-active-high;
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usdhc2_vmmc: usdhc2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "sw-3p3-sd1";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+			off-on-delay-us = <4800>;
+			enable-active-high;
+		};
+
+		epdev_on: fixedregulator@100 {
+			compatible = "regulator-fixed";
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&pinctrl_wlreg_on>;
+			pinctrl-1 = <&pinctrl_wlreg_on_sleep>;
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-name = "epdev_on";
+			gpio = <&gpio1 13 0>;
+			enable-active-high;
+		};
 	};
 };
 
@@ -35,9 +66,12 @@
 	imx8qm-mek {
 		pinctrl_hog: hoggrp {
 			fsl,pins = <
-				SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0	0x0600004c
-				SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25	0x0600004c
-				SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31	0x0600004c
+				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	  0x06000048
+				SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06	  0x06000021
+				SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07	  0x06000021
+				SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20		  0x06000021
+				SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24		  0x06000021
+				SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23		  0x06000021
 			>;
 		};
 
@@ -79,6 +113,27 @@
 			>;
 		};
 
+		pinctrl_flexspi0: flexspi0grp {
+			fsl,pins = <
+				SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x06000021
+				SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x06000021
+				SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x06000021
+				SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x06000021
+				SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS		0x06000021
+				SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x06000021
+				SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B	0x06000021
+				SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x06000021
+				SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK	0x06000021
+				SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x06000021
+				SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x06000021
+				SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x06000021
+				SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x06000021
+				SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS		0x06000021
+				SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B	0x06000021
+				SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B	0x06000021
+			>;
+		};
+
 		pinctrl_lpuart0: lpuart0grp {
 			fsl,pins = <
 				SC_P_UART0_RX_DMA_UART0_RX		0x06000020
@@ -86,6 +141,36 @@
 			>;
 		};
 
+		pinctrl_i2c0: i2c0grp {
+			fsl,pins = <
+				SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL	0x06000021
+				SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA	0x06000021
+			>;
+		};
+
+		pinctrl_pciea: pcieagrp{
+			fsl,pins = <
+				SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27	0x06000021
+				SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28		0x04000021
+				SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29		0x06000021
+				SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09		0x06000021
+			>;
+		};
+
+		pinctrl_typec: typecgrp {
+			fsl,pins = <
+				SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19	0x60
+				SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06	0x60
+				SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26	0x00000021
+			>;
+		};
+
+		pinctrl_usbotg1: usbotg1 {
+			fsl,pins = <
+				SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021
+			>;
+		};
+
 		pinctrl_usdhc1: usdhc1grp {
 			fsl,pins = <
 				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
@@ -122,20 +207,79 @@
 				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
 			>;
 		};
+
+		pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
+			fsl,pins = <
+				SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL	0xc600004c
+				SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA	0xc600004c
+			>;
+		};
+
+		pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {
+			fsl,pins = <
+				SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL	0xc600004c
+				SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA	0xc600004c
+			>;
+		};
+
+		pinctrl_wlreg_on: wlregongrp{
+			fsl,pins = <
+				SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13		0x06000000
+			>;
+		};
+
+		pinctrl_wlreg_on_sleep: wlregon_sleepgrp{
+			fsl,pins = <
+				SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13		0x07800000
+			>;
+		};
 	};
 };
 
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	disable-over-current;
+	status = "okay";
+};
+
+&usbotg3 {
+	status = "okay";
+};
+
 &usdhc1 {
-	pinctrl-names = "default";
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1>;
+	pinctrl-2 = <&pinctrl_usdhc1>;
 	bus-width = <8>;
 	non-removable;
 	status = "okay";
 };
 
 &usdhc2 {
-	pinctrl-names = "default";
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 	bus-width = <4>;
 	cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
@@ -168,17 +312,201 @@
 			reg = <1>;
 			at803x,eee-disabled;
 			at803x,vddio-1p8v;
-			status = "disabled";
 		};
 	};
 };
 
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec2>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy1>;
+	fsl,ar8031-phy-fixup;
+	fsl,magic-packet;
+	status = "okay";
+};
+
+&flexspi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi0>;
+	status = "okay";
+
+	flash0: mt35xu512aba@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <8>;
+	};
+};
+
+&i2c0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0>;
+	status = "okay";
+
+	max7322: gpio@68 {
+		compatible = "maxim,max7322";
+		reg = <0x68>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	typec_ptn5110: typec@50 {
+		compatible = "usb,tcpci";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_typec>;
+		reg = <0x51>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+		ss-sel-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
+		reset-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+		src-pdos = <0x380190c8 0x3803c0c8>;
+		port-type = "drp";
+		sink-disable;
+		default-role = "source";
+		status = "okay";
+	};
+};
+
 &lpuart0 { /* console */
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lpuart0>;
 	status = "okay";
 };
 
-&gpio1 {
+&i2c1_lvds0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	lvds-to-hdmi-bridge@4c {
+		compatible = "ite,it6263";
+		reg = <0x4c>;
+
+		port {
+			it6263_0_in: endpoint {
+				clock-lanes = <3>;
+				data-lanes = <0 1 2 4>;
+				remote-endpoint = <&lvds0_out>;
+			};
+		};
+	};
+};
+
+&i2c1_lvds1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lvds1_lpi2c1>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	lvds-to-hdmi-bridge@4c {
+		compatible = "ite,it6263";
+		reg = <0x4c>;
+	};
+};
+
+&pciea{
+	ext_osc = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pciea>;
+	disable-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>;
+	reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
+	clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
+	epdev_on = <&epdev_on>;
 	status = "okay";
 };
+
+&sata {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pciea>;
+	clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&tsens {
+	tsens-num = <6>;
+};
+
+&thermal_zones {
+	pmic-thermal0 {
+		polling-delay-passive = <250>;
+		polling-delay = <2000>;
+		thermal-sensors = <&tsens 5>;
+		trips {
+			pmic_alert0: trip0 {
+				temperature = <110000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+			pmic_crit0: trip1 {
+				temperature = <125000>;
+				hysteresis = <2000>;
+				type = "critical";
+			};
+		};
+		cooling-maps {
+			map0 {
+				trip = <&pmic_alert0>;
+				cooling-device =
+				<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			};
+			map1 {
+				trip = <&pmic_alert0>;
+				cooling-device =
+				<&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+};
+
+&dpu1 {
+	status = "okay";
+};
+
+&ldb1_phy {
+	status = "okay";
+};
+
+&ldb1 {
+	status = "okay";
+
+	lvds-channel@0 {
+		fsl,data-mapping = "jeida";
+		fsl,data-width = <24>;
+		status = "okay";
+
+		display-timings {
+			native-mode = <&timing0>;
+
+			timing0: timing0 {
+				clock-frequency = <74250000>;
+				hactive = <1280>;
+				vactive = <720>;
+				hfront-porch = <220>;
+				hback-porch = <110>;
+				hsync-len = <40>;
+				vback-porch = <5>;
+				vfront-porch = <20>;
+				vsync-len = <5>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+
+			lvds0_out: endpoint {
+				remote-endpoint = <&it6263_0_in>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi
index 88aeaf65b31..f59ce3d5cc0 100644
--- a/arch/arm/dts/fsl-imx8qm.dtsi
+++ b/arch/arm/dts/fsl-imx8qm.dtsi
@@ -1,16 +1,19 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include "fsl-imx8-ca53.dtsi"
+#include "fsl-imx8-ca72.dtsi"
 #include <dt-bindings/clock/imx8qm-clock.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/soc/imx_rsrc.h>
+#include <dt-bindings/soc/imx8_hsio.h>
 #include <dt-bindings/soc/imx8_pd.h>
 #include <dt-bindings/pinctrl/pads-imx8qm.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
 	compatible = "fsl,imx8qm";
@@ -21,6 +24,15 @@
 	aliases {
 		ethernet0 = &fec1;
 		ethernet1 = &fec2;
+		dsiphy0 = &mipi_dsi_phy1;
+		dsiphy1 = &mipi_dsi_phy2;
+		mipidsi0 = &mipi_dsi1;
+		mipidsi1 = &mipi_dsi2;
+		serial0 = &lpuart0;
+		serial1 = &lpuart1;
+		serial2 = &lpuart2;
+		serial3 = &lpuart3;
+		serial4 = &lpuart4;
 		gpio0 = &gpio0;
 		gpio1 = &gpio1;
 		gpio2 = &gpio2;
@@ -29,19 +41,25 @@
 		gpio5 = &gpio5;
 		gpio6 = &gpio6;
 		gpio7 = &gpio7;
-		serial0 = &lpuart0;
-		serial1 = &lpuart1;
-		serial2 = &lpuart2;
-		serial3 = &lpuart3;
-		serial4 = &lpuart4;
 		mmc0 = &usdhc1;
 		mmc1 = &usdhc2;
 		mmc2 = &usdhc3;
+		usb0 = &usbotg1;
+		usbphy0 = &usbphy1;
+		usb1 = &usbotg3;
 		i2c0 = &i2c0;
 		i2c1 = &i2c1;
 		i2c2 = &i2c2;
 		i2c3 = &i2c3;
 		i2c4 = &i2c4;
+		i2c6 = &i2c1_lvds0;
+		i2c8 = &i2c1_lvds1;
+		spi0 = &flexspi0;
+		pci0 = &pciea;
+		display0 = &ldb1;
+		display1 = &ldb2;
+		video0 = &dpu1;
+		video1 = &dpu2;
 	};
 
 	memory@80000000 {
@@ -50,6 +68,63 @@
 		      /* DRAM space - 1, size : 1 GB DRAM */
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/*
+		 * reserved-memory layout
+		 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
+		 * Shouldn't be used at A core and Linux side.
+		 *
+		 */
+
+		decoder_boot: decoder_boot@0x84000000 {
+			no-map;
+			reg = <0 0x84000000 0 0x2000000>;
+		};
+		encoder_boot: encoder_boot@0x86000000 {
+			no-map;
+			reg = <0 0x86000000 0 0x400000>;
+		};
+		rpmsg_reserved: rpmsg@0x90000000 {
+			no-map;
+			reg = <0 0x90000000 0 0x400000>;
+		};
+		rpmsg_dma_reserved:rpmsg_dma@0x90400000 {
+			compatible = "shared-dma-pool";
+			no-map;
+			reg = <0 0x90400000 0 0x1C00000>;
+		};
+		decoder_rpc: decoder_rpc@0x92000000 {
+			no-map;
+			reg = <0 0x92000000 0 0x200000>;
+		};
+		encoder_rpc: encoder_rpc@0x92200000 {
+			no-map;
+			reg = <0 0x92200000 0 0x200000>;
+		};
+		dsp_reserved: dsp@0x92400000 {
+			no-map;
+			reg = <0 0x92400000 0 0x2000000>;
+		};
+		encoder_reserved: encoder_reserved@0x94400000 {
+			no-map;
+			reg = <0 0x94400000 0 0x800000>;
+		};
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0 0x3c000000>;
+			alloc-ranges = <0 0x96000000 0 0x3c000000>;
+			linux,cma-default;
+		};
+
+	};
+
 	gic: interrupt-controller@51a00000 {
 		compatible = "arm,gic-v3";
 		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
@@ -64,12 +139,28 @@
 		interrupt-parent = <&gic>;
 	};
 
+	mu8: mu@5d230000 {
+		compatible = "fsl,imx-m4-mu";
+		reg = <0x0 0x5d230000 0x0 0x10000>;
+		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&pd_lsio_mu8a>;
+		status = "okay";
+	};
+
+	mu9: mu@5d240000 {
+		compatible = "fsl,imx-m4-mu";
+		reg = <0x0 0x5d240000 0x0 0x10000>;
+		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&pd_lsio_mu9a>;
+		status = "okay";
+	};
+
 	mu: mu@5d1c0000 {
 		compatible = "fsl,imx8-mu";
 		reg = <0x0 0x5d1c0000 0x0 0x10000>;
 		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-parent = <&gic>;
-		fsl,scu_ap_mu_id = <0>;
+		#mbox-cells = <4>;
 		status = "okay";
 
 		clk: clk {
@@ -82,482 +173,131 @@
 		};
 	};
 
-	imx8qm-pm {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		pd_lsio: PD_LSIO {
-			compatible = "nxp,imx8-pd";
-			reg = <SC_R_NONE>;
-			#power-domain-cells = <0>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			pd_lsio_gpio0: PD_LSIO_GPIO_0 {
-				reg = <SC_R_GPIO_0>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_lsio>;
-			};
-			pd_lsio_gpio1: PD_LSIO_GPIO_1 {
-				reg = <SC_R_GPIO_1>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_lsio>;
-			};
-			pd_lsio_gpio2: PD_LSIO_GPIO_2 {
-				reg = <SC_R_GPIO_2>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_lsio>;
-			};
-			pd_lsio_gpio3: PD_LSIO_GPIO_3 {
-				reg = <SC_R_GPIO_3>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_lsio>;
-			};
-			pd_lsio_gpio4: PD_LSIO_GPIO_4 {
-				reg = <SC_R_GPIO_4>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_lsio>;
-			};
-			pd_lsio_gpio5: PD_LSIO_GPIO_5{
-				reg = <SC_R_GPIO_5>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_lsio>;
-			};
-			pd_lsio_gpio6:PD_LSIO_GPIO_6 {
-				reg = <SC_R_GPIO_6>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_lsio>;
-			};
-			pd_lsio_gpio7: PD_LSIO_GPIO_7 {
-				reg = <SC_R_GPIO_7>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_lsio>;
-			};
-		};
-
-		pd_conn: PD_CONN {
-			compatible = "nxp,imx8-pd";
-			reg = <SC_R_NONE>;
-			#power-domain-cells = <0>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			pd_conn_sdch0: PD_CONN_SDHC_0 {
-				reg = <SC_R_SDHC_0>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_conn>;
-			};
-			pd_conn_sdch1: PD_CONN_SDHC_1 {
-				reg = <SC_R_SDHC_1>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_conn>;
-			};
-			pd_conn_sdch2: PD_CONN_SDHC_2 {
-				reg = <SC_R_SDHC_2>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_conn>;
-			};
-			pd_conn_enet0: PD_CONN_ENET_0 {
-				reg = <SC_R_ENET_0>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_conn>;
-				wakeup-irq = <258>;
-			};
-			pd_conn_enet1: PD_CONN_ENET_1 {
-				reg = <SC_R_ENET_1>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_conn>;
-				fsl,wakeup_irq = <262>;
-			};
-		};
-
-		pd_dma: PD_DMA {
-			compatible = "nxp,imx8-pd";
-			reg = <SC_R_NONE>;
-			#power-domain-cells = <0>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			pd_dma_lpi2c0: PD_DMA_I2C_0 {
-				reg = <SC_R_I2C_0>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_dma>;
-			};
-			pd_dma_lpi2c1: PD_DMA_I2C_1 {
-				reg = <SC_R_I2C_1>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_dma>;
-			};
-			pd_dma_lpi2c2:PD_DMA_I2C_2 {
-				reg = <SC_R_I2C_2>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_dma>;
-			};
-			pd_dma_lpi2c3: PD_DMA_I2C_3 {
-				reg = <SC_R_I2C_3>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_dma>;
-			};
-			pd_dma_lpi2c4: PD_DMA_I2C_4 {
-				reg = <SC_R_I2C_4>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_dma>;
-			};
-			pd_dma_lpuart0: PD_DMA_UART0 {
-				reg = <SC_R_UART_0>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_dma>;
-				wakeup-irq = <345>;
-			};
-			pd_dma_lpuart1: PD_DMA_UART1 {
-				reg = <SC_R_UART_1>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_dma>;
-				wakeup-irq = <346>;
-			};
-			pd_dma_lpuart2: PD_DMA_UART2 {
-				reg = <SC_R_UART_2>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_dma>;
-				wakeup-irq = <347>;
-			};
-			pd_dma_lpuart3: PD_DMA_UART3 {
-				reg = <SC_R_UART_3>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_dma>;
-				wakeup-irq = <348>;
-			};
-			pd_dma_lpuart4: PD_DMA_UART4 {
-				reg = <SC_R_UART_4>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_dma>;
-				wakeup-irq = <349>;
-			};
-		};
+	mu13: mu13@5d280000 {
+		compatible = "fsl,imx8-mu-dsp";
+		reg = <0x0 0x5d280000 0x0 0x10000>;
+		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,dsp_ap_mu_id = <13>;
+		status = "okay";
 	};
 
-	i2c0: i2c@5a800000 {
-		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
-		reg = <0x0 0x5a800000 0x0 0x4000>;
-		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		clocks = <&clk IMX8QM_I2C0_CLK>,
-			 <&clk IMX8QM_I2C0_IPG_CLK>;
-		clock-names = "per", "ipg";
-		assigned-clocks = <&clk IMX8QM_I2C0_CLK>;
-		assigned-clock-rates = <24000000>;
-		power-domains = <&pd_dma_lpi2c0>;
-		status = "disabled";
+	mu_m0: mu_m0@2d000000 {
+		compatible = "fsl,imx8-mu0-vpu-m0";
+		reg = <0x0 0x2d000000 0x0 0x20000>;
+		interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,vpu_ap_mu_id = <16>;
+		status = "okay";
 	};
 
-	i2c1: i2c@5a810000 {
-		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
-		reg = <0x0 0x5a810000 0x0 0x4000>;
-		interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		clocks = <&clk IMX8QM_I2C1_CLK>,
-			 <&clk IMX8QM_I2C1_IPG_CLK>;
-		clock-names = "per", "ipg";
-		assigned-clocks = <&clk IMX8QM_I2C1_CLK>;
-		assigned-clock-rates = <24000000>;
-		power-domains = <&pd_dma_lpi2c1>;
-		status = "disabled";
+	mu1_m0: mu1_m0@2d020000 {
+		compatible = "fsl,imx8-mu1-vpu-m0";
+		reg = <0x0 0x2d020000 0x0 0x20000>;
+		interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,vpu_ap_mu_id = <17>;
+		status = "okay";
 	};
 
-	i2c2: i2c@5a820000 {
-		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
-		reg = <0x0 0x5a820000 0x0 0x4000>;
-		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-parent = <&gic>;
-		clocks = <&clk IMX8QM_I2C2_CLK>,
-			 <&clk IMX8QM_I2C2_IPG_CLK>;
-		clock-names = "per", "ipg";
-		assigned-clocks = <&clk IMX8QM_I2C2_CLK>;
-		assigned-clock-rates = <24000000>;
-		power-domains = <&pd_dma_lpi2c2>;
-		status = "disabled";
+	mu2_m0: mu2_m0@2d040000 {
+		compatible = "fsl,imx8-mu2-vpu-m0";
+		reg = <0x0 0x2d040000 0x0 0x20000>;
+		interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,vpu_ap_mu_id = <18>;
+		status = "okay";
 	};
 
-	i2c3: i2c@5a830000 {
-		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
-		reg = <0x0 0x5a830000 0x0 0x4000>;
-		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+		clock-frequency = <8000000>;
 		interrupt-parent = <&gic>;
-		clocks = <&clk IMX8QM_I2C3_CLK>,
-			 <&clk IMX8QM_I2C3_IPG_CLK>;
-		clock-names = "per", "ipg";
-		assigned-clocks = <&clk IMX8QM_I2C3_CLK>;
-		assigned-clock-rates = <24000000>;
-		power-domains = <&pd_dma_lpi2c3>;
-		status = "disabled";
 	};
 
-	i2c4: i2c@5a840000 {
-		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
-		reg = <0x0 0x5a840000 0x0 0x4000>;
-		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+	smmu: iommu@51400000 {
+		compatible = "arm,mmu-500";
 		interrupt-parent = <&gic>;
-		clocks = <&clk IMX8QM_I2C4_CLK>,
-			 <&clk IMX8QM_I2C4_IPG_CLK>;
-		clock-names = "per", "ipg";
-		assigned-clocks = <&clk IMX8QM_I2C4_CLK>;
-		assigned-clock-rates = <24000000>;
-		power-domains = <&pd_dma_lpi2c4>;
-		status = "disabled";
-	};
-
-	gpio0: gpio@5d080000 {
-		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
-		reg = <0x0 0x5d080000 0x0 0x10000>;
-		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		power-domains = <&pd_lsio_gpio0>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpio1: gpio@5d090000 {
-		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
-		reg = <0x0 0x5d090000 0x0 0x10000>;
-		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		power-domains = <&pd_lsio_gpio1>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpio2: gpio@5d0a0000 {
-		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
-		reg = <0x0 0x5d0a0000 0x0 0x10000>;
-		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		power-domains = <&pd_lsio_gpio2>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpio3: gpio@5d0b0000 {
-		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
-		reg = <0x0 0x5d0b0000 0x0 0x10000>;
-		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		power-domains = <&pd_lsio_gpio3>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpio4: gpio@5d0c0000 {
-		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
-		reg = <0x0 0x5d0c0000 0x0 0x10000>;
-		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		power-domains = <&pd_lsio_gpio4>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpio5: gpio@5d0d0000 {
-		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
-		reg = <0x0 0x5d0d0000 0x0 0x10000>;
-		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		power-domains = <&pd_lsio_gpio5>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpio6: gpio@5d0e0000 {
-		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
-		reg = <0x0 0x5d0e0000 0x0 0x10000>;
-		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		power-domains = <&pd_lsio_gpio6>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	gpio7: gpio@5d0f0000 {
-		compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
-		reg = <0x0 0x5d0f0000 0x0 0x10000>;
-		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		power-domains = <&pd_lsio_gpio7>;
-		interrupt-controller;
-		#interrupt-cells = <2>;
-	};
-
-	lpuart0: serial@5a060000 {
-		compatible = "fsl,imx8qm-lpuart";
-		reg = <0x0 0x5a060000 0x0 0x1000>;
-		interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clk IMX8QM_UART0_CLK>,
-			 <&clk IMX8QM_UART0_IPG_CLK>;
-		clock-names = "per", "ipg";
-		assigned-clocks = <&clk IMX8QM_UART0_CLK>;
-		assigned-clock-rates = <80000000>;
-		power-domains = <&pd_dma_lpuart0>;
-		status = "disabled";
+		reg = <0 0x51400000 0 0x40000>;
+		#global-interrupts = <1>;
+		#iommu-cells = <2>;
+		interrupts = <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>;
 	};
 
-	lpuart1: serial@5a070000 {
-		compatible = "fsl,imx8qm-lpuart";
-		reg = <0x0 0x5a070000 0x0 0x1000>;
-		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clk IMX8QM_UART1_CLK>,
-			 <&clk IMX8QM_UART1_IPG_CLK>;
-		clock-names = "per", "ipg";
-		assigned-clocks = <&clk IMX8QM_UART1_CLK>;
-		assigned-clock-rates = <80000000>;
-		power-domains = <&pd_dma_lpuart1>;
-		status = "disabled";
-	};
-
-	lpuart2: serial@5a080000 {
-		compatible = "fsl,imx8qm-lpuart";
-		reg = <0x0 0x5a080000 0x0 0x1000>;
-		interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clk IMX8QM_UART2_CLK>,
-			 <&clk IMX8QM_UART2_IPG_CLK>;
-		clock-names = "per", "ipg";
-		assigned-clocks = <&clk IMX8QM_UART2_CLK>;
-		assigned-clock-rates = <80000000>;
-		power-domains = <&pd_dma_lpuart2>;
-		status = "disabled";
-	};
-
-	lpuart3: serial@5a090000 {
-		compatible = "fsl,imx8qm-lpuart";
-		reg = <0x0 0x5a090000 0x0 0x1000>;
-		interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clk IMX8QM_UART3_CLK>,
-			 <&clk IMX8QM_UART3_IPG_CLK>;
-		clock-names = "per", "ipg";
-		assigned-clocks = <&clk IMX8QM_UART3_CLK>;
-		assigned-clock-rates = <80000000>;
-		power-domains = <&pd_dma_lpuart3>;
-		status = "disabled";
+	cci: cci@52090000 {
+		compatible = "arm,cci-400";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0 0x52090000 0 0x1000>;
+		ranges = <0 0 0x52090000 0x10000>;
+
+		pmu@9000 {
+			compatible = "arm,cci-400-pmu,r1",
+				     "arm,cci-400-pmu";
+			reg = <0x9000 0x4000>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&gic>;
+		};
 	};
 
-	lpuart4: serial@5a0a0000 {
-		compatible = "fsl,imx8qm-lpuart";
-		reg = <0x0 0x5a0a0000 0x0 0x1000>;
-		interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clk IMX8QM_UART4_CLK>,
-			 <&clk IMX8QM_UART4_IPG_CLK>;
-		clock-names = "per", "ipg";
-		assigned-clocks = <&clk IMX8QM_UART4_CLK>;
-		assigned-clock-rates = <80000000>;
-		power-domains = <&pd_dma_lpuart4>;
-		status = "disabled";
-	};
+	#include "fsl-imx8qm-device.dtsi"
+};
 
-	usdhc1: usdhc@5b010000 {
-		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
-		reg = <0x0 0x5b010000 0x0 0x10000>;
-		clocks = <&clk IMX8QM_SDHC0_IPG_CLK>,
-			 <&clk IMX8QM_SDHC0_CLK>,
-			 <&clk IMX8QM_CLK_DUMMY>;
-		clock-names = "ipg", "per", "ahb";
-		assigned-clocks = <&clk IMX8QM_SDHC0_DIV>;
-		assigned-clock-rates = <400000000>;
-		power-domains = <&pd_conn_sdch0>;
-		fsl,tuning-start-tap = <20>;
-		fsl,tuning-step= <2>;
-		status = "disabled";
-	};
+&A53_0 {
+	operating-points = <
+		/* kHz    uV */
+		/* voltage is maintained by SCFW, so no need here */
+		1200000	   0
+		1104000	   0
+		900000	   0
+		600000	   0
+	>;
+	clocks = <&clk IMX8QM_A53_DIV>;
+	clock-latency = <61036>;
+	#cooling-cells = <2>;
+	/delete-property/ cpu-idle-states;
+};
 
-	usdhc2: usdhc@5b020000 {
-		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
-		reg = <0x0 0x5b020000 0x0 0x10000>;
-		clocks = <&clk IMX8QM_SDHC1_IPG_CLK>,
-			 <&clk IMX8QM_SDHC1_CLK>,
-			 <&clk IMX8QM_CLK_DUMMY>;
-		clock-names = "ipg", "per", "ahb";
-		assigned-clocks = <&clk IMX8QM_SDHC1_DIV>;
-		assigned-clock-rates = <200000000>;
-		power-domains = <&pd_conn_sdch1>;
-		fsl,tuning-start-tap = <20>;
-		fsl,tuning-step= <2>;
-		status = "disabled";
-	};
+&A72_0 {
+	operating-points = <
+		/* kHz    uV */
+		/* voltage is maintained by SCFW, so no need here */
+		1596000	   0
+		1296000	   0
+		1056000	   0
+		600000     0
+	>;
+	clocks = <&clk IMX8QM_A72_DIV>;
+	clock-latency = <61036>;
+	#cooling-cells = <2>;
+	/delete-property/ cpu-idle-states;
+};
 
-	usdhc3: usdhc@5b030000 {
-		compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
-		interrupt-parent = <&gic>;
-		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
-		reg = <0x0 0x5b030000 0x0 0x10000>;
-		clocks = <&clk IMX8QM_SDHC2_IPG_CLK>,
-			 <&clk IMX8QM_SDHC2_CLK>,
-			 <&clk IMX8QM_CLK_DUMMY>;
-		clock-names = "ipg", "per", "ahb";
-		assigned-clocks = <&clk IMX8QM_SDHC2_DIV>;
-		assigned-clock-rates = <200000000>;
-		power-domains = <&pd_conn_sdch2>;
-		status = "disabled";
-	};
+&A53_1 {
+	/delete-property/ cpu-idle-states;
+};
 
-	fec1: ethernet@5b040000 {
-		compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec";
-		reg = <0x0 0x5b040000 0x0 0x10000>;
-		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clk IMX8QM_ENET0_IPG_CLK>,
-			 <&clk IMX8QM_ENET0_AHB_CLK>,
-			 <&clk IMX8QM_ENET0_RGMII_TX_CLK>,
-			 <&clk IMX8QM_ENET0_PTP_CLK>,
-			 <&clk IMX8QM_ENET0_TX_CLK>;
-		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp",
-			      "enet_2x_txclk";
-		assigned-clocks = <&clk IMX8QM_ENET0_ROOT_DIV>,
-				  <&clk IMX8QM_ENET0_REF_DIV>;
-		assigned-clock-rates = <250000000>, <125000000>;
-		fsl,num-tx-queues=<3>;
-		fsl,num-rx-queues=<3>;
-		fsl,wakeup_irq = <0>;
-		power-domains = <&pd_conn_enet0>;
-		status = "disabled";
-	};
+&A53_2 {
+	/delete-property/ cpu-idle-states;
+};
 
-	fec2: ethernet@5b050000 {
-		compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec";
-		reg = <0x0 0x5b050000 0x0 0x10000>;
-		interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clk IMX8QM_ENET1_IPG_CLK>,
-			 <&clk IMX8QM_ENET1_AHB_CLK>,
-			 <&clk IMX8QM_ENET1_RGMII_TX_CLK>,
-			 <&clk IMX8QM_ENET1_PTP_CLK>,
-			 <&clk IMX8QM_ENET1_TX_CLK>;
-		clock-names = "ipg", "ahb", "enet_clk_ref", "ptp",
-			      "enet_2x_txclk";
-		assigned-clocks = <&clk IMX8QM_ENET1_ROOT_DIV>,
-				  <&clk IMX8QM_ENET1_REF_DIV>;
-		assigned-clock-rates = <250000000>, <125000000>;
-		fsl,num-tx-queues=<3>;
-		fsl,num-rx-queues=<3>;
-		fsl,wakeup_irq = <0>;
-		power-domains = <&pd_conn_enet1>;
-		status = "disabled";
-	};
+&A53_3 {
+	/delete-property/ cpu-idle-states;
 };
 
-&A53_0 {
-	clocks = <&clk IMX8QM_A53_DIV>;
+&A72_1 {
+	/delete-property/ cpu-idle-states;
 };
diff --git a/arch/arm/dts/fsl-imx8qxp-17x17-val-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-17x17-val-u-boot.dtsi
new file mode 100644
index 00000000000..ee88f322b60
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-17x17-val-u-boot.dtsi
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+/ {
+	aliases {
+		usbgadget0 = &usbg1;
+	};
+
+	usbg1: usbg1 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg1>;
+		status = "okay";
+		u-boot,dm-spl;
+	};
+};
+
+&{/imx8qx-pm} {
+
+	u-boot,dm-spl;
+};
+
+&mu {
+	u-boot,dm-spl;
+};
+
+&clk {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&{/mu@5d1c0000/iomuxc/imx8qxp-val} {
+	u-boot,dm-spl;
+};
+
+&pinctrl_lpuart0 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_100mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_200mhz {
+	u-boot,dm-spl;
+};
+
+&pd_conn {
+	u-boot,dm-spl;
+};
+
+&pd_dma {
+	u-boot,dm-spl;
+};
+
+&pd_dma_lpuart0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0_phy {
+	u-boot,dm-spl;
+};
+
+&lpuart0 {
+	u-boot,dm-spl;
+};
+
+&usbmisc1 {
+	u-boot,dm-spl;
+};
+
+&usbphy1 {
+	u-boot,dm-spl;
+};
+
+&usbotg1 {
+	u-boot,dm-spl;
+};
+
+&usdhc1 {
+	u-boot,dm-spl;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+};
+
+&fec1 {
+	phy-mode = "rgmii-id";
+};
+
+&fec2 {
+	phy-mode = "rgmii-id";
+};
+
+&ethphy0 {
+	vddio0: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
+
+&ethphy1 {
+	vddio1: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
\ No newline at end of file
diff --git a/arch/arm/dts/fsl-imx8qxp-17x17-val.dts b/arch/arm/dts/fsl-imx8qxp-17x17-val.dts
new file mode 100644
index 00000000000..4ee085f9f19
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-17x17-val.dts
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ *
+ */
+
+#include "fsl-imx8qxp-lpddr4-val.dts"
+
+/ {
+	model = "NXP i.MX8QXP 17x17 Validation board";
+};
+
+&i2c1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c1>;
+	status = "okay";
+
+	pca9557_a: gpio@18 {
+		compatible = "nxp,pca9557";
+		reg = <0x18>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pca9557_b: gpio@19 {
+		compatible = "nxp,pca9557";
+		reg = <0x19>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&i2c3 {
+	status = "disabled";
+
+	/delete-node/ gpio@18;
+ 	/delete-node/ gpio@19;
+};
+
+&usdhc2 {
+	status = "disabled";
+};
+
+&usbotg3 {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/fsl-imx8qxp-lpddr4-val-gpmi-nand.dts b/arch/arm/dts/fsl-imx8qxp-lpddr4-val-gpmi-nand.dts
new file mode 100644
index 00000000000..4cca5c7fdfd
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-lpddr4-val-gpmi-nand.dts
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2019 NXP
+ */
+
+#include "fsl-imx8qxp-lpddr4-val.dts"
+#include "fsl-imx8qxp-lpddr4-val-u-boot.dtsi"
+
+&iomuxc {
+	imx8qxp-val {
+		pinctrl_gpmi_nand_1: gpmi-nand-1 {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_NAND_READY_B	0x0e00004c
+				SC_P_EMMC0_DATA0_CONN_NAND_DATA00	0x0e00004c
+				SC_P_EMMC0_DATA1_CONN_NAND_DATA01	0x0e00004c
+				SC_P_EMMC0_DATA2_CONN_NAND_DATA02	0x0e00004c
+				SC_P_EMMC0_DATA3_CONN_NAND_DATA03	0x0e00004c
+				SC_P_EMMC0_DATA4_CONN_NAND_DATA04	0x0e00004c
+				SC_P_EMMC0_DATA5_CONN_NAND_DATA05	0x0e00004c
+				SC_P_EMMC0_DATA6_CONN_NAND_DATA06	0x0e00004c
+				SC_P_EMMC0_DATA7_CONN_NAND_DATA07	0x0e00004c
+				SC_P_EMMC0_STROBE_CONN_NAND_CLE		0x0e00004c
+				SC_P_EMMC0_RESET_B_CONN_NAND_WP_B	0x0e00004c
+
+				SC_P_USDHC1_DATA0_CONN_NAND_CE1_B	0x0e00004c
+				SC_P_USDHC1_DATA2_CONN_NAND_WE_B	0x0e00004c
+				SC_P_USDHC1_DATA3_CONN_NAND_ALE		0x0e00004c
+				SC_P_USDHC1_CMD_CONN_NAND_CE0_B		0x0e00004c
+
+				/* i.MX8QXP NAND use nand_re_dqs_pins */
+				SC_P_USDHC1_CD_B_CONN_NAND_DQS      0x0e00004c
+				SC_P_USDHC1_VSELECT_CONN_NAND_RE_B  0x0e00004c
+
+			>;
+		};
+	};
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "okay";
+	nand-on-flash-bbt;
+	fsl,use-minimum-ecc;
+};
+
+/* Disabled the usdhc1/usdhc2 since pin conflict */
+&usdhc1 {
+	status = "disabled";
+};
+
+&usdhc2 {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/fsl-imx8qxp-lpddr4-val-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-lpddr4-val-u-boot.dtsi
new file mode 100644
index 00000000000..b54ee4d8495
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-lpddr4-val-u-boot.dtsi
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+/ {
+
+	aliases {
+		usbhost1 = &usbh3;
+		usbgadget0 = &usbg1;
+	};
+
+	usbh3: usbh3 {
+		compatible = "Cadence,usb3-host";
+		dr_mode = "host";
+		cdns3,usb = <&usbotg3>;
+		status = "okay";
+	};
+
+	usbg1: usbg1 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg1>;
+		status = "okay";
+		u-boot,dm-spl;
+	};
+
+};
+
+&{/imx8qx-pm} {
+
+	u-boot,dm-spl;
+};
+
+&mu {
+	u-boot,dm-spl;
+};
+
+&clk {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&{/regulators} {
+	u-boot,dm-spl;
+};
+
+&reg_usdhc2_vmmc {
+	u-boot,dm-spl;
+};
+
+&{/mu@5d1c0000/iomuxc/imx8qxp-val} {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_100mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_200mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_lpuart0 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_100mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_200mhz {
+	u-boot,dm-spl;
+};
+
+&pinctrl_flexspi0 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio0 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio3 {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+	u-boot,dm-spl;
+};
+
+&pd_conn {
+	u-boot,dm-spl;
+};
+
+&pd_dma {
+	u-boot,dm-spl;
+};
+
+&pd_dma_lpuart0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0_phy {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usb2 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usb2_phy {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_flexspi0 {
+	u-boot,dm-spl;
+};
+
+&gpio0 {
+	u-boot,dm-spl;
+};
+
+&gpio3 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&lpuart0 {
+	u-boot,dm-spl;
+};
+
+&usbmisc1 {
+	u-boot,dm-spl;
+};
+
+&usbphy1 {
+	u-boot,dm-spl;
+};
+
+&usbotg1 {
+	u-boot,dm-spl;
+};
+
+&usbotg3 {
+	phys = <&usbphynop1>;
+	u-boot,dm-spl;
+};
+
+&usbphynop1 {
+	compatible = "cdns,usb3-phy";
+	reg = <0x0 0x5B160000 0x0 0x40000>;
+	#phy-cells = <0>;
+	u-boot,dm-spl;
+};
+
+&usdhc1 {
+	u-boot,dm-spl;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
+};
+
+&flexspi0 {
+	u-boot,dm-spl;
+};
+
+&flash0 {
+	u-boot,dm-spl;
+};
+
+&wu {
+	u-boot,dm-spl;
+};
+
+&fec1 {
+	phy-mode = "rgmii-id";
+};
+
+&fec2 {
+	phy-mode = "rgmii-id";
+};
+
+&ethphy0 {
+	vddio0: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
+
+&ethphy1 {
+	vddio1: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
\ No newline at end of file
diff --git a/arch/arm/dts/fsl-imx8qxp-lpddr4-val.dts b/arch/arm/dts/fsl-imx8qxp-lpddr4-val.dts
new file mode 100644
index 00000000000..77e27a02058
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-lpddr4-val.dts
@@ -0,0 +1,470 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2019 NXP
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qxp.dtsi"
+
+/ {
+	model = "NXP i.MX8QXP LPDDR4 VAL";
+	compatible = "fsl,imx8qxp-lpddr4-val", "fsl,imx8qxp";
+
+	aliases {
+		gpio8 = &pca9557_a;
+		gpio9 = &pca9557_b;
+		gpio10 = &pca9557_c;
+	};
+
+	chosen {
+		bootargs = "console=ttyLP0,115200 earlycon";
+		stdout-path = &lpuart0;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usdhc2_vmmc: usdhc2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "SD1_SPWR";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			startup-delay-us = <300>;
+			off-on-delay-us = <5000>;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	imx8qxp-val {
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000048
+				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0
+			>;
+		};
+
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000060
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x00000060
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000060
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000060
+				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x00000060
+				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x00000060
+				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x00000060
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000060
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000060
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000060
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x00000060
+				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x00000060
+			>;
+		};
+
+		pinctrl_fec2: fec2grp {
+			fsl,pins = <
+				SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x00000060
+				SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC		0x00000060
+				SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0	0x00000060
+				SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1	0x00000060
+				SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2		0x00000060
+				SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3		0x00000060
+				SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC		0x00000060
+				SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x00000060
+				SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x00000060
+				SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1	0x00000060
+				SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2	0x00000060
+				SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3		0x00000060
+			>;
+		};
+
+		pinctrl_lpi2c1: lpi1cgrp {
+			fsl,pins = <
+				SC_P_USB_SS3_TC1_ADMA_I2C1_SCL	0x06000021
+				SC_P_USB_SS3_TC3_ADMA_I2C1_SDA	0x06000021
+			>;
+		};
+
+		pinctrl_lpi2c3: lpi2cgrp {
+			fsl,pins = <
+				SC_P_SPI3_CS1_ADMA_I2C3_SCL	0x06000020
+				SC_P_MCLK_IN1_ADMA_I2C3_SDA	0x06000020
+			>;
+		};
+
+		pinctrl_lpuart0: lpuart0grp {
+			fsl,pins = <
+				SC_P_UART0_RX_ADMA_UART0_RX	0x0600002c
+				SC_P_UART0_TX_ADMA_UART0_TX	0x0600002c
+			>;
+		};
+
+		pinctrl_lpspi0: lpspi0grp {
+			fsl,pins = <
+				SC_P_SPI0_SCK_ADMA_SPI0_SCK		0x600004c
+				SC_P_SPI0_SDO_ADMA_SPI0_SDO		0x600004c
+				SC_P_SPI0_SDI_ADMA_SPI0_SDI		0x600004c
+			>;
+		};
+
+		pinctrl_lpspi0_cs: lpspi0cs {
+			fsl,pins = <
+				SC_P_SPI0_CS0_LSIO_GPIO1_IO08		0x21
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+			fsl,pins = <
+				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19	0x00000021
+				SC_P_USDHC1_WP_LSIO_GPIO4_IO21		0x00000021
+				SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
+			>;
+		};
+
+		pinctrl_flexspi0: flexspi0grp {
+			fsl,pins = <
+				SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x06000021
+				SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x06000021
+				SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x06000021
+				SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x06000021
+				SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS		0x06000021
+				SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x06000021
+				SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B	0x06000021
+				SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x06000021
+				SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK	0x06000021
+				SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x06000021
+				SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x06000021
+				SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x06000021
+				SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x06000021
+				SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS		0x06000021
+				SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B	0x06000021
+				SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B	0x06000021
+			>;
+		};
+
+		pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp {
+			fsl,pins = <
+				SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020
+				SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020
+			>;
+		};
+
+		pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp {
+			fsl,pins = <
+				SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020
+				SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020
+			>;
+		};
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&lpspi0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>;
+	cs-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>, <0>, <0>, <0>;
+	spi-max-frequency = <1000000>;
+	status = "okay";
+
+	flash: at45db041e@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "atmel,at45", "atmel,dataflash";
+		spi-max-frequency = <1000000>;
+		reg = <0>;
+	};
+};
+
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-txid";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	fsl,rgmii_rxc_dly;
+	status = "okay";
+	phy-reset-gpios = <&pca9557_a 1 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <10>;
+	phy-reset-post-delay = <150>;
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			at803x,eee-disabled;
+			at803x,vddio-1p8v;
+		};
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			at803x,eee-disabled;
+			at803x,vddio-1p8v;
+			status = "disabled";
+		};
+	};
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec2>;
+	phy-mode = "rgmii-txid";
+	phy-handle = <&ethphy1>;
+	fsl,magic-packet;
+	fsl,rgmii_rxc_dly;
+	status = "disabled";
+	phy-reset-gpios = <&pca9557_a 4 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <10>;
+	phy-reset-post-delay = <150>;
+};
+
+&flexspi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi0>;
+	status = "okay";
+
+	flash0: mt35xu512aba@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <8>;
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c1>;
+	status = "okay";
+};
+
+&i2c3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c3>;
+	status = "okay";
+
+	pca9557_a: gpio@18 {
+		compatible = "nxp,pca9557";
+		reg = <0x18>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pca9557_b: gpio@19 {
+		compatible = "nxp,pca9557";
+		reg = <0x19>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pca9557_c: gpio@1b {
+		compatible = "nxp,pca9557";
+		reg = <0x1b>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&i2c0_mipi_lvds0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	it6263-0@4c {
+		compatible = "ITE,it6263";
+		reg = <0x4c>;
+	};
+};
+
+&i2c0_mipi_lvds1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	it6263-1@4c {
+		compatible = "ITE,it6263";
+		reg = <0x4c>;
+	};
+};
+
+&lpuart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart0>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	disable-over-current;
+	status = "okay";
+};
+
+&usbotg3 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
index 701af4434d5..5be7e601316 100644
--- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
@@ -1,8 +1,32 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  */
 
+/ {
+
+	aliases {
+		usbhost1 = &usbh3;
+		usbgadget0 = &usbg1;
+	};
+
+	usbh3: usbh3 {
+		compatible = "Cadence,usb3-host";
+		dr_mode = "host";
+		cdns3,usb = <&usbotg3>;
+		status = "okay";
+	};
+
+	usbg1: usbg1 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg1>;
+		status = "okay";
+		u-boot,dm-spl;
+	};
+
+};
+
 &{/imx8qx-pm} {
 
 	u-boot,dm-spl;
@@ -20,6 +44,38 @@
 	u-boot,dm-spl;
 };
 
+&{/regulators} {
+	u-boot,dm-spl;
+};
+
+&reg_usdhc2_vmmc {
+	u-boot,dm-spl;
+};
+
+&{/mu@5d1c0000/iomuxc/imx8qxp-mek} {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_lpuart0 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_flexspi0 {
+	u-boot,dm-spl;
+};
+
 &pd_lsio {
 	u-boot,dm-spl;
 };
@@ -80,6 +136,42 @@
 	u-boot,dm-spl;
 };
 
+&pd_caam {
+	u-boot,dm-spl;
+};
+
+&pd_caam_jr1 {
+	u-boot,dm-spl;
+};
+
+&pd_caam_jr2 {
+	u-boot,dm-spl;
+};
+
+&pd_caam_jr3 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usbotg0_phy {
+	u-boot,dm-spl;
+};
+
+&pd_lsio_flexspi0 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usb2 {
+	u-boot,dm-spl;
+};
+
+&pd_conn_usb2_phy {
+	u-boot,dm-spl;
+};
+
 &gpio0 {
 	u-boot,dm-spl;
 };
@@ -116,6 +208,30 @@
 	u-boot,dm-spl;
 };
 
+&usbmisc1 {
+	u-boot,dm-spl;
+};
+
+&usbphy1 {
+	u-boot,dm-spl;
+};
+
+&usbotg1 {
+	u-boot,dm-spl;
+};
+
+&usbotg3 {
+	phys = <&usbphynop1>;
+	u-boot,dm-spl;
+};
+
+&usbphynop1 {
+	compatible = "cdns,usb3-phy";
+	reg = <0x0 0x5B160000 0x0 0x40000>;
+	#phy-cells = <0>;
+	u-boot,dm-spl;
+};
+
 &usdhc1 {
 	u-boot,dm-spl;
 	mmc-hs400-1_8v;
@@ -126,3 +242,64 @@
 	sd-uhs-sdr104;
 	sd-uhs-ddr50;
 };
+
+&crypto {
+	u-boot,dm-spl;
+};
+
+&sec_jr1 {
+	u-boot,dm-spl;
+};
+
+&sec_jr2 {
+	u-boot,dm-spl;
+};
+
+&sec_jr3 {
+	u-boot,dm-spl;
+};
+
+&flexspi0 {
+	u-boot,dm-spl;
+};
+
+&flash0 {
+	u-boot,dm-spl;
+};
+
+&i2c1 {
+	compatible = "fsl,imx8qm-lpi2c", "fsl,imx-virt-i2c";
+};
+
+&{/i2c@5a810000/i2cswitch@71} {
+	compatible = "nxp,pca9646", "fsl,imx-virt-i2c-mux";
+	virtual-bus-seq = <12>;
+};
+
+&wu {
+	u-boot,dm-spl;
+};
+
+&fec1 {
+	phy-mode = "rgmii-id";
+};
+
+&fec2 {
+	phy-mode = "rgmii-id";
+};
+
+&ethphy0 {
+	vddio0: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
+
+&ethphy1 {
+	vddio1: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts
index 4f35fbe31db..86aa8684798 100644
--- a/arch/arm/dts/fsl-imx8qxp-mek.dts
+++ b/arch/arm/dts/fsl-imx8qxp-mek.dts
@@ -6,25 +6,59 @@
 /dts-v1/;
 
 #include "fsl-imx8qxp.dtsi"
-#include "fsl-imx8qxp-mek-u-boot.dtsi"
 
 / {
-	model = "Freescale i.MX8QXP MEK";
+	model = "NXP i.MX8QXP MEK";
 	compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
 
+	aliases {
+		i2c4 = &bb_i2c1;
+		i2c5 = &mfi_i2c1;
+		i2c6 = &i2cexp1_i2c1;
+		i2c7 = &i2cexp2_i2c1;
+		gpio8 = &pca9557_a;
+		gpio9 = &pca9557_b;
+	};
+
 	chosen {
-		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
+		bootargs = "console=ttyLP0,115200 earlycon";
 		stdout-path = &lpuart0;
 	};
 
-	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
-		compatible = "regulator-fixed";
-		regulator-name = "SD1_SPWR";
-		regulator-min-microvolt = <3000000>;
-		regulator-max-microvolt = <3000000>;
-		gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
-		off-on-delay = <3480>;
-		enable-active-high;
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "SD1_SPWR";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			off-on-delay-us = <3480>;
+		};
+
+		epdev_on: fixedregulator@100 {
+			compatible = "regulator-fixed";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-name = "epdev_on";
+			gpio = <&pca9557_a 0 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
 	};
 };
 
@@ -40,45 +74,41 @@
 			>;
 		};
 
-		pinctrl_ioexp_rst: ioexp-rst-grp {
-			fsl,pins = <
-				SC_P_SPI2_SDO_LSIO_GPIO1_IO01	0x06000021
-			>;
-		};
-
 		pinctrl_fec1: fec1grp {
 			fsl,pins = <
-				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000048
-				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000048
-				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000048
-				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000048
-				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000048
-				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000048
-				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000048
-				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000048
-				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000048
-				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000048
-				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000048
-				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000048
-				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000048
-				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000048
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000061
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x00000061
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000061
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000061
+				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x00000061
+				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x00000061
+				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x00000061
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000061
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000061
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000061
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x00000061
+				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x00000061
 			>;
 		};
 
 		pinctrl_fec2: fec2grp {
 			fsl,pins = <
-				SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x06000048
-				SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC		0x06000048
-				SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0	0x06000048
-				SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1	0x06000048
-				SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2		0x06000048
-				SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3		0x06000048
-				SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC		0x06000048
-				SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x06000048
-				SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x06000048
-				SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1	0x06000048
-				SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2	0x06000048
-				SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3		0x06000048
+				SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x00000060
+				SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC		0x00000060
+				SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0	0x00000060
+				SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1	0x00000060
+				SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2		0x00000060
+				SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3		0x00000060
+				SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC		0x00000060
+				SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x00000060
+				SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x00000060
+				SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1	0x00000060
+				SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2	0x00000060
+				SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3		0x00000060
 			>;
 		};
 
@@ -131,6 +161,49 @@
 				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
 			>;
 		};
+
+		pinctrl_pcieb: pcieagrp{
+			fsl,pins = <
+				SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00		0x06000021
+				SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01	0x06000021
+				SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02		0x04000021
+			>;
+		};
+
+		pinctrl_flexspi0: flexspi0grp {
+			fsl,pins = <
+				SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x06000021
+				SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x06000021
+				SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x06000021
+				SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x06000021
+				SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS		0x06000021
+				SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x06000021
+				SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B	0x06000021
+				SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x06000021
+				SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK	0x06000021
+				SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x06000021
+				SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x06000021
+				SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x06000021
+				SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x06000021
+				SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS		0x06000021
+				SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B	0x06000021
+				SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B	0x06000021
+			>;
+		};
+
+		pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp {
+			fsl,pins = <
+				SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020
+				SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020
+			>;
+		};
+
+		pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp {
+			fsl,pins = <
+				SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020
+				SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020
+			>;
+		};
 	};
 };
 
@@ -144,18 +217,49 @@
 	status = "okay";
 };
 
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&flexspi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi0>;
+	status = "okay";
+
+	flash0: mt35xu512aba@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <8>;
+	};
+};
+
 &i2c1 {
 	clock-frequency = <100000>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
+	pinctrl-0 = <&pinctrl_lpi2c1>;
 	status = "okay";
 
 	i2cswitch@71 {
 		compatible = "nxp,pca9646";
 		reg = <0x71>;
+		u-boot,i2c-offset-len = <0>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 
 		bb_i2c1: i2c@0 {
 			#address-cells = <1>;
@@ -196,17 +300,53 @@
 	};
 };
 
-&usdhc1 {
+&i2c0_mipi_lvds0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
 	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	lvds-to-hdmi-bridge@4c {
+		compatible = "ite,it6263";
+		reg = <0x4c>;
+		reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>;
+
+		port {
+			it6263_0_in: endpoint {
+				clock-lanes = <4>;
+				data-lanes = <0 1 2 3>;
+				remote-endpoint = <&lvds0_out>;
+			};
+		};
+	};
+};
+
+&i2c0_mipi_lvds1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>;
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1>;
+	pinctrl-2 = <&pinctrl_usdhc1>;
 	bus-width = <8>;
 	non-removable;
 	status = "okay";
 };
 
 &usdhc2 {
-	pinctrl-names = "default";
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 	bus-width = <4>;
 	cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
@@ -214,6 +354,17 @@
 	status = "okay";
 };
 
+&pcieb{
+	ext_osc = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcieb>;
+	clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>;
+	power-on-gpio = <&pca9557_a 2 GPIO_ACTIVE_HIGH>;
+	reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>;
+	epdev_on = <&epdev_on>;
+	status = "okay";
+};
+
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec1>;
@@ -240,3 +391,69 @@
 		};
 	};
 };
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec2>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy1>;
+	fsl,ar8031-phy-fixup;
+	fsl,magic-packet;
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	power-polarity-active-high;
+	disable-over-current;
+	status = "okay";
+};
+
+&usbotg3 {
+	status = "okay";
+};
+
+&dpu1 {
+	status = "okay";
+};
+
+&ldb1_phy {
+	status = "okay";
+};
+
+&ldb1 {
+	status = "okay";
+
+	lvds-channel@0 {
+		fsl,data-mapping = "jeida";
+		fsl,data-width = <24>;
+		status = "okay";
+
+		display-timings {
+			native-mode = <&timing0>;
+
+			timing0: timing0 {
+				clock-frequency = <74250000>;
+				hactive = <1280>;
+				vactive = <720>;
+				hfront-porch = <220>;
+				hback-porch = <110>;
+				hsync-len = <40>;
+				vback-porch = <5>;
+				vfront-porch = <20>;
+				vsync-len = <5>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+
+			lvds0_out: endpoint {
+				remote-endpoint = <&it6263_0_in>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/fsl-imx8qxp.dtsi b/arch/arm/dts/fsl-imx8qxp.dtsi
index 1bffff1314e..5f4fde1ca7c 100644
--- a/arch/arm/dts/fsl-imx8qxp.dtsi
+++ b/arch/arm/dts/fsl-imx8qxp.dtsi
@@ -16,7 +16,7 @@
 #include "fsl-imx8dxp.dtsi"
 
 / {
-	model = "Freescale i.MX8QXP";
+	model = "NXP i.MX8QXP";
 	compatible = "fsl,imx8qxp";
 
 	cpus {
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 0ea899c7d7c..1cdcc99c1ee 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
  * Copyright 2016 Freescale Semiconductor
  */
 
@@ -71,6 +71,50 @@
 			bus-width = <4>;
 		};
 
+		crypto: crypto@1700000 {
+			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+				     "fsl,sec-v4.0";
+			fsl,sec-era = <8>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x00 0x1700000 0x100000>;
+			reg = <0x00 0x1700000 0x0 0x100000>;
+			interrupts = <0 75 0x4>;
+			dma-coherent;
+
+			sec_jr0: jr@10000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x10000 0x10000>;
+				interrupts = <0 71 0x4>;
+			};
+
+			sec_jr1: jr@20000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x20000 0x10000>;
+				interrupts = <0 72 0x4>;
+			};
+
+			sec_jr2: jr@30000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x30000 0x10000>;
+				interrupts = <0 73 0x4>;
+			};
+
+			sec_jr3: jr@40000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x40000 0x10000>;
+				interrupts = <0 74 0x4>;
+			};
+		};
+
 		gpio0: gpio@2300000 {
 			compatible = "fsl,qoriq-gpio";
 			reg = <0x0 0x2300000 0x0 0x10000>;
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 52dc5a96382..72877d2ff58 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -2,7 +2,7 @@
 /*
  * Device Tree Include file for NXP Layerscape-1043A family SoC.
  *
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
  * Copyright (C) 2014-2015, Freescale Semiconductor
  *
  * Mingkai Hu <Mingkai.hu@freescale.com>
@@ -125,6 +125,49 @@
 			interrupts = <0 43 0x4>;
 		};
 
+		crypto: crypto@1700000 {
+			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+				     "fsl,sec-v4.0";
+			fsl,sec-era = <3>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x00 0x1700000 0x100000>;
+			reg = <0x00 0x1700000 0x0 0x100000>;
+			interrupts = <0 75 0x4>;
+
+			sec_jr0: jr@10000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x10000 0x10000>;
+				interrupts = <0 71 0x4>;
+			};
+
+			sec_jr1: jr@20000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x20000 0x10000>;
+				interrupts = <0 72 0x4>;
+			};
+
+			sec_jr2: jr@30000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x30000 0x10000>;
+				interrupts = <0 73 0x4>;
+			};
+
+			sec_jr3: jr@40000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x40000 0x10000>;
+				interrupts = <0 74 0x4>;
+			};
+		};
+
 		i2c0: i2c@2180000 {
 			compatible = "fsl,vf610-i2c";
 			#address-cells = <1>;
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index a60cbf11fc5..c655e002aa0 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -3,6 +3,7 @@
  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
  *
  * Copyright (C) 2016, Freescale Semiconductor
+ * Copyright 2021 NXP
  *
  * Mingkai Hu <mingkai.hu@nxp.com>
  */
@@ -124,6 +125,49 @@
 			interrupts = <0 43 0x4>;
 		};
 
+		crypto: crypto@1700000 {
+			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+				     "fsl,sec-v4.0";
+			fsl,sec-era = <8>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x00 0x1700000 0x100000>;
+			reg = <0x00 0x1700000 0x0 0x100000>;
+			interrupts = <0 75 0x4>;
+
+			sec_jr0: jr@10000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x10000 0x10000>;
+				interrupts = <0 71 0x4>;
+			};
+
+			sec_jr1: jr@20000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x20000 0x10000>;
+				interrupts = <0 72 0x4>;
+			};
+
+			sec_jr2: jr@30000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x30000 0x10000>;
+				interrupts = <0 73 0x4>;
+			};
+
+			sec_jr3: jr@40000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x40000 0x10000>;
+				interrupts = <0 74 0x4>;
+			};
+		};
+
 		i2c0: i2c@2180000 {
 			compatible = "fsl,vf610-i2c";
 			#address-cells = <1>;
diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
index f73fdfda8b5..9b7c54b260e 100644
--- a/arch/arm/dts/fsl-ls1088a.dtsi
+++ b/arch/arm/dts/fsl-ls1088a.dtsi
@@ -174,6 +174,45 @@
 		dr_mode = "host";
 	};
 
+	crypto: crypto@8000000 {
+		compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+		fsl,sec-era = <8>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x00 0x8000000 0x100000>;
+		reg = <0x00 0x8000000 0x0 0x100000>;
+		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+		dma-coherent;
+
+		sec_jr0: jr@10000 {
+			compatible = "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+			reg	   = <0x10000 0x10000>;
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		sec_jr1: jr@20000 {
+			compatible = "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+			reg	   = <0x20000 0x10000>;
+			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		sec_jr2: jr@30000 {
+			compatible = "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+			reg	   = <0x30000 0x10000>;
+			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		sec_jr3: jr@40000 {
+			compatible = "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+			reg	   = <0x40000 0x10000>;
+			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+
 	pcie1: pcie@3400000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index 72ba52594a1..a1837454f43 100644
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -239,6 +239,45 @@
 			status = "disabled";
 	};
 
+	crypto: crypto@8000000 {
+		compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+		fsl,sec-era = <8>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x00 0x8000000 0x100000>;
+		reg = <0x00 0x8000000 0x0 0x100000>;
+		interrupts = <0 139 0x4>;  /* Level high type */
+		dma-coherent;
+
+		sec_jr0: jr@10000 {
+			compatible = "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+			reg	   = <0x10000 0x10000>;
+			interrupts = <0 140 0x4>;  /* Level high type */
+		};
+
+		sec_jr1: jr@20000 {
+			compatible = "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+			reg	   = <0x20000 0x10000>;
+			interrupts = <0 141 0x4>;  /* Level high type */
+		};
+
+		sec_jr2: jr@30000 {
+			compatible = "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+			reg	   = <0x30000 0x10000>;
+			interrupts = <0 142 0x4>;  /* Level high type */
+		};
+
+		sec_jr3: jr@40000 {
+			compatible = "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+			reg	   = <0x40000 0x10000>;
+			interrupts = <0 143 0x4>;  /* Level high type */
+		};
+	};
+
 	fsl_mc: fsl-mc@80c000000 {
 		compatible = "fsl,qoriq-mc", "simple-mfd";
 		reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi
index 52e4d7205a2..57c7d3ef711 100644
--- a/arch/arm/dts/fsl-lx2160a.dtsi
+++ b/arch/arm/dts/fsl-lx2160a.dtsi
@@ -2,7 +2,7 @@
 /*
  * NXP lx2160a SOC common device tree source
  *
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2021 NXP
  *
  */
 
@@ -27,6 +27,45 @@
 		clock-output-names = "sysclk";
 	};
 
+	crypto: crypto@8000000 {
+		compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+		fsl,sec-era = <10>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x00 0x8000000 0x100000>;
+		reg = <0x00 0x8000000 0x0 0x100000>;
+		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+		dma-coherent;
+
+		sec_jr0: jr@10000 {
+			compatible = "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+			reg        = <0x10000 0x10000>;
+			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		sec_jr1: jr@20000 {
+			compatible = "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+			reg        = <0x20000 0x10000>;
+			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		sec_jr2: jr@30000 {
+			compatible = "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+			reg        = <0x30000 0x10000>;
+			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		sec_jr3: jr@40000 {
+			compatible = "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+			reg        = <0x40000 0x10000>;
+			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+
 	clockgen: clocking@1300000 {
 		compatible = "fsl,ls2080a-clockgen";
 		reg = <0 0x1300000 0 0xa0000>;
diff --git a/arch/arm/dts/imx6dl-sabreauto-ecspi.dts b/arch/arm/dts/imx6dl-sabreauto-ecspi.dts
new file mode 100644
index 00000000000..45ae1628362
--- /dev/null
+++ b/arch/arm/dts/imx6dl-sabreauto-ecspi.dts
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6dl-sabreauto.dts"
+
+&ecspi1 {
+	pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&can2 {
+	/* max7310_c on i2c3 is gone */
+	status = "disabled";
+};
+
+&i2c3 {
+	/* pin conflict with ecspi1 */
+	status = "disabled";
+};
+
+&uart3 {
+	/* the uart3 depends on the i2c3, so disable it too. */
+	status = "disabled";
+};
+
+&usbh1 {
+	/* max7310_b on i2c3 is gone */
+	status = "disabled";
+};
+
+&usbotg {
+	dr_mode = "peripheral";
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6dl-sabreauto-gpmi-weim.dts b/arch/arm/dts/imx6dl-sabreauto-gpmi-weim.dts
new file mode 100644
index 00000000000..ad2e937d4ff
--- /dev/null
+++ b/arch/arm/dts/imx6dl-sabreauto-gpmi-weim.dts
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6dl-sabreauto.dts"
+
+&ecspi1 {
+	/* pin conflict with weim */
+	status = "disabled";
+};
+
+&can2 {
+	/* max7310_c on i2c3 is gone */
+	status = "disabled";
+};
+
+&gpmi {
+	status = "okay";
+};
+
+&i2c3 {
+	/* pin conflict with weim */
+	status = "disabled";
+};
+
+&uart3 {
+	/* pin conflict with gpmi and weim */
+	status = "disabled";
+};
+
+&usbh1 {
+	/* max7310_b on i2c3 is gone */
+	status = "disabled";
+};
+
+&usbotg {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&weim {
+	pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6dl-sabreauto.dts b/arch/arm/dts/imx6dl-sabreauto.dts
index 660d52a245b..a2d11d1d83c 100644
--- a/arch/arm/dts/imx6dl-sabreauto.dts
+++ b/arch/arm/dts/imx6dl-sabreauto.dts
@@ -8,6 +8,35 @@
 #include "imx6qdl-sabreauto.dtsi"
 
 / {
-	model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
+	model = "i.MX6 DualLite/Solo SABRE Automotive Board";
 	compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
 };
+&ldb {
+	lvds-channel@0 {
+		crtc = "ipu1-di0";
+	};
+	lvds-channel@1 {
+		crtc = "ipu1-di1";
+	};
+};
+&mxcfb1 {
+	status = "okay";
+};
+&mxcfb2 {
+	status = "okay";
+};
+
+&cpu0 {
+	operating-points = <
+		/* kHz    uV */
+		996000  1275000
+		792000  1175000
+		396000  1150000
+	>;
+	fsl,soc-operating-points = <
+		/* ARM kHz  SOC-PU uV */
+		996000	1200000
+		792000	1175000
+		396000	1175000
+	>;
+};
diff --git a/arch/arm/dts/imx6dl-sabresd.dts b/arch/arm/dts/imx6dl-sabresd.dts
index cd6bbf22a16..8e8481ff59f 100644
--- a/arch/arm/dts/imx6dl-sabresd.dts
+++ b/arch/arm/dts/imx6dl-sabresd.dts
@@ -8,11 +8,146 @@
 #include "imx6qdl-sabresd.dtsi"
 
 / {
-	model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
+	model = "i.MX6 DualLite SABRE Smart Device Board";
 	compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
 };
 
+&battery {
+	offset-charger = <1485>;
+	offset-discharger = <1464>;
+	offset-usb-charger = <1285>;
+};
+
+&iomuxc {
+        epdc {
+                pinctrl_epdc_0: epdcgrp-0 {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_A16__EPDC_DATA00    0x80000000
+                                MX6QDL_PAD_EIM_DA10__EPDC_DATA01   0x80000000
+                                MX6QDL_PAD_EIM_DA12__EPDC_DATA02   0x80000000
+                                MX6QDL_PAD_EIM_DA11__EPDC_DATA03   0x80000000
+                                MX6QDL_PAD_EIM_LBA__EPDC_DATA04    0x80000000
+                                MX6QDL_PAD_EIM_EB2__EPDC_DATA05    0x80000000
+                                MX6QDL_PAD_EIM_CS0__EPDC_DATA06    0x80000000
+                                MX6QDL_PAD_EIM_RW__EPDC_DATA07     0x80000000
+                                MX6QDL_PAD_EIM_A21__EPDC_GDCLK     0x80000000
+                                MX6QDL_PAD_EIM_A22__EPDC_GDSP      0x80000000
+                                MX6QDL_PAD_EIM_A23__EPDC_GDOE      0x80000000
+                                MX6QDL_PAD_EIM_A24__EPDC_GDRL      0x80000000
+                                MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P   0x80000000
+                                MX6QDL_PAD_EIM_D27__EPDC_SDOE      0x80000000
+                                MX6QDL_PAD_EIM_DA1__EPDC_SDLE      0x80000000
+                                MX6QDL_PAD_EIM_EB1__EPDC_SDSHR     0x80000000
+                                MX6QDL_PAD_EIM_DA2__EPDC_BDR0      0x80000000
+                                MX6QDL_PAD_EIM_DA4__EPDC_SDCE0     0x80000000
+                                MX6QDL_PAD_EIM_DA5__EPDC_SDCE1     0x80000000
+                                MX6QDL_PAD_EIM_DA6__EPDC_SDCE2     0x80000000
+                        >;
+                };
+        };
+};
+
+&epdc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_epdc_0>;
+        V3P3-supply = <&V3P3_reg>;
+        VCOM-supply = <&VCOM_reg>;
+        DISPLAY-supply = <&DISPLAY_reg>;
+        status = "okay";
+};
+
+&i2c3 {
+        max17135@48 {
+                compatible = "maxim,max17135";
+                reg = <0x48>;
+                vneg_pwrup = <1>;
+                gvee_pwrup = <1>;
+                vpos_pwrup = <2>;
+                gvdd_pwrup = <1>;
+                gvdd_pwrdn = <1>;
+                vpos_pwrdn = <2>;
+                gvee_pwrdn = <1>;
+                vneg_pwrdn = <1>;
+                SENSOR-supply = <&reg_sensor>;
+                gpio_pmic_pwrgood = <&gpio2 21 0>;
+                gpio_pmic_vcom_ctrl = <&gpio3 17 0>;
+                gpio_pmic_wakeup = <&gpio3 20 0>;
+                gpio_pmic_v3p3 = <&gpio2 20 0>;
+                gpio_pmic_intr = <&gpio2 25 0>;
+
+                regulators {
+                        DISPLAY_reg: DISPLAY {
+                                regulator-name = "DISPLAY";
+                        };
+
+                        GVDD_reg: GVDD {
+                                /* 20v */
+                                regulator-name = "GVDD";
+                        };
+
+                        GVEE_reg: GVEE {
+                                /* -22v */
+                                regulator-name = "GVEE";
+                        };
+
+                        HVINN_reg: HVINN {
+                                /* -22v */
+                                regulator-name = "HVINN";
+                        };
+
+                        HVINP_reg: HVINP {
+                                /* 20v */
+                                regulator-name = "HVINP";
+                        };
+
+                        VCOM_reg: VCOM {
+                                regulator-name = "VCOM";
+                                /* Real max: -500000 */
+                                regulator-max-microvolt = <4325000>;
+                                /* Real min: -4325000 */
+                                regulator-min-microvolt = <500000>;
+                        };
+
+                        VNEG_reg: VNEG {
+                                /* -15v */
+                                regulator-name = "VNEG";
+                        };
+
+                        VPOS_reg: VPOS {
+                                /* 15v */
+                                regulator-name = "VPOS";
+                        };
+
+                        V3P3_reg: V3P3 {
+                                regulator-name = "V3P3";
+                        };
+                };
+        };
+};
+
 &ipu1_csi1_from_ipu1_csi1_mux {
 	clock-lanes = <0>;
 	data-lanes = <1 2>;
 };
+
+&ldb {
+	lvds-channel@0 {
+		crtc = "ipu1-di0";
+	};
+
+	lvds-channel@1 {
+		crtc = "ipu1-di1";
+	};
+};
+
+&mxcfb1 {
+	status = "okay";
+};
+
+&mxcfb2 {
+	status = "okay";
+};
+
+&pxp {
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi
index ae5aad6b9ef..814bbabe233 100644
--- a/arch/arm/dts/imx6dl.dtsi
+++ b/arch/arm/dts/imx6dl.dtsi
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 //
 // Copyright 2013 Freescale Semiconductor, Inc.
+// Copyright 2018 NXP
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include "imx6dl-pinfunc.h"
@@ -15,7 +16,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu@0 {
+		cpu0: cpu@0 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			reg = <0>;
@@ -33,14 +34,17 @@
 				396000	1175000
 			>;
 			clock-latency = <61036>; /* two CLK32 periods */
-			#cooling-cells = <2>;
 			clocks = <&clks IMX6QDL_CLK_ARM>,
 				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 				 <&clks IMX6QDL_CLK_STEP>,
 				 <&clks IMX6QDL_CLK_PLL1_SW>,
-				 <&clks IMX6QDL_CLK_PLL1_SYS>;
+				 <&clks IMX6QDL_CLK_PLL1_SYS>,
+				 <&clks IMX6QDL_CLK_PLL1>,
+				 <&clks IMX6QDL_PLL1_BYPASS>,
+				 <&clks IMX6QDL_PLL1_BYPASS_SRC>;
 			clock-names = "arm", "pll2_pfd2_396m", "step",
-				      "pll1_sw", "pll1_sys";
+				      "pll1_sw", "pll1_sys", "pll1",
+				      "pll1_bypass", "pll1_bypass_src";
 			arm-supply = <&reg_arm>;
 			pu-supply = <&reg_pu>;
 			soc-supply = <&reg_soc>;
@@ -51,56 +55,107 @@
 			device_type = "cpu";
 			reg = <1>;
 			next-level-cache = <&L2>;
-			operating-points = <
-				/* kHz    uV */
-				996000  1250000
-				792000  1175000
-				396000  1150000
-			>;
-			fsl,soc-operating-points = <
-				/* ARM kHz  SOC-PU uV */
-				996000	1175000
-				792000	1175000
-				396000	1175000
-			>;
-			clock-latency = <61036>; /* two CLK32 periods */
-			clocks = <&clks IMX6QDL_CLK_ARM>,
-				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
-				 <&clks IMX6QDL_CLK_STEP>,
-				 <&clks IMX6QDL_CLK_PLL1_SW>,
-				 <&clks IMX6QDL_CLK_PLL1_SYS>;
-			clock-names = "arm", "pll2_pfd2_396m", "step",
-				      "pll1_sw", "pll1_sys";
-			arm-supply = <&reg_arm>;
-			pu-supply = <&reg_pu>;
-			soc-supply = <&reg_soc>;
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x14000000>;
+			linux,cma-default;
 		};
 	};
 
 	soc {
-		ocram: sram@900000 {
+		busfreq {
+			compatible = "fsl,imx_busfreq";
+			clocks = <&clks IMX6QDL_CLK_PLL2_BUS>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+				<&clks IMX6QDL_CLK_PLL2_198M>, <&clks IMX6QDL_CLK_ARM>,
+				<&clks IMX6QDL_CLK_PLL3_USB_OTG>, <&clks IMX6QDL_CLK_PERIPH>,
+				<&clks IMX6QDL_CLK_PERIPH_PRE>, <&clks IMX6QDL_CLK_PERIPH_CLK2>,
+				<&clks IMX6QDL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6QDL_CLK_OSC>,
+				<&clks IMX6QDL_CLK_AXI_ALT_SEL>, <&clks IMX6QDL_CLK_AXI_SEL> ,
+				<&clks IMX6QDL_CLK_PLL3_PFD1_540M>;
+			clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
+				"periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_alt_sel", "axi_sel", "pll3_pfd1_540m";
+			interrupts = <0 107 0x04>, <0 112 0x4>;
+			interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
+			fsl,max_ddr_freq = <400000000>;
+		};
+
+		ocram: sram@905000 {
 			compatible = "mmio-sram";
-			reg = <0x00900000 0x20000>;
+			reg = <0x905000 0x1B000>;
 			clocks = <&clks IMX6QDL_CLK_OCRAM>;
 		};
 
-		aips1: bus@2000000 {
-			iomuxc: iomuxc@20e0000 {
-				compatible = "fsl,imx6dl-iomuxc";
-			};
+		ocram_optee: sram@918000 {
+			compatible = "fsl,optee-lpm-sram";
+			reg = <0x918000 0x8000>;
+			overw_reg = <&ocram 0x905000 0x13000>;
+		};
 
+		gpu: gpu@00130000 {
+			compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
+			reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
+			      <0x10000000 0x0>, <0x0 0x8000000>;
+			reg-names = "iobase_3d", "iobase_2d",
+				    "phys_baseaddr", "contiguous_mem";
+			interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>,
+				     <0 10 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "irq_3d", "irq_2d";
+			clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, <&clks IMX6QDL_CLK_GPU3D_AXI>,
+				 <&clks IMX6QDL_CLK_GPU2D_CORE>, <&clks IMX6QDL_CLK_GPU3D_CORE>,
+				 <&clks IMX6QDL_CLK_DUMMY>;
+			clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk",
+				      "gpu2d_clk", "gpu3d_clk",
+				      "gpu3d_shader_clk";
+			resets = <&src 0>, <&src 3>;
+			reset-names = "gpu3d", "gpu2d";
+			power-domains = <&pd_pu>;
+		};
+
+		aips1: bus@2000000 {
 			pxp: pxp@20f0000 {
-				reg = <0x020f0000 0x4000>;
+				compatible = "fsl,imx6dl-pxp-dma";
+				reg = <0x20f0000 0x4000>;
 				interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_DUMMY>;
+				clock-names = "pxp-axi", "disp-axi";
+				status = "disabled";
 			};
 
 			epdc: epdc@20f4000 {
-				reg = <0x020f4000 0x4000>;
+				compatible = "fsl,imx6dl-epdc";
+				reg = <0x20f4000 0x4000>;
 				interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_IPU2_DI1>;
+				clock-names = "epdc_axi", "epdc_pix";
+			};
+
+			lcdif: lcdif@20f8000 {
+				reg = <0x20f8000 0x4000>;
+				interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 			};
 		};
 
 		aips2: bus@2100000 {
+			mipi_dsi: mipi@21e0000 {
+				compatible = "fsl,imx6dl-mipi-dsi";
+				reg = <0x21e0000 0x4000>;
+				interrupts = <0 102 0x4>;
+				gpr = <&gpr>;
+				clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>;
+				clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
+				status = "disabled";
+			};
+
 			i2c4: i2c@21f8000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
@@ -122,6 +177,17 @@
 		compatible = "fsl,imx-display-subsystem";
 		ports = <&ipu1_di0>, <&ipu1_di1>;
 	};
+
+	gpu-subsystem {
+		compatible = "fsl,imx-gpu-subsystem";
+		cores = <&gpu_2d>, <&gpu_3d>;
+	};
+};
+
+&dcic2 {
+	clocks = <&clks IMX6QDL_CLK_DCIC1 >,
+		<&clks IMX6QDL_CLK_DCIC2>; /* DCIC2 depend on DCIC1 clock in imx6dl*/
+	clock-names = "dcic", "disp-axi";
 };
 
 &gpio1 {
@@ -295,6 +361,10 @@
 	compatible = "fsl,imx6dl-hdmi";
 };
 
+&iomuxc {
+	compatible = "fsl,imx6dl-iomuxc";
+};
+
 &ipu1_csi1 {
 	ipu1_csi1_from_ipu1_csi1_mux: endpoint {
 		remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
@@ -302,12 +372,19 @@
 };
 
 &ldb {
-	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+	compatible = "fsl,imx6dl-ldb", "fsl,imx53-ldb";
+	clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>,
 		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
-		 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
-	clock-names = "di0_pll", "di1_pll",
+		 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>,
+		 <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>,
+		 <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>,
+		 <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>;
+	clock-names = "ldb_di0", "ldb_di1",
 		      "di0_sel", "di1_sel",
-		      "di0", "di1";
+		      "di2_sel",
+		      "ldb_di0_div_3_5", "ldb_di1_div_3_5",
+		      "ldb_di0_div_7", "ldb_di1_div_7",
+		      "ldb_di0_div_sel", "ldb_di1_div_sel";
 };
 
 &mipi_csi {
@@ -389,3 +466,7 @@
 &vpu {
 	compatible = "fsl,imx6dl-vpu", "cnm,coda960";
 };
+
+&vpu_fsl {
+	iramsize = <0>;
+};
diff --git a/arch/arm/dts/imx6q-sabreauto-ecspi.dts b/arch/arm/dts/imx6q-sabreauto-ecspi.dts
new file mode 100644
index 00000000000..3cf99ed9be6
--- /dev/null
+++ b/arch/arm/dts/imx6q-sabreauto-ecspi.dts
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6q-sabreauto.dts"
+
+&ecspi1 {
+	pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&can2 {
+	/* max7310_c on i2c3 is gone */
+	status = "disabled";
+};
+
+&i2c3 {
+	/* pin conflict with ecspi1 */
+	status = "disabled";
+};
+
+&uart3 {
+	/* the uart3 depends on the i2c3, so disable it too. */
+	status = "disabled";
+};
+
+&usbh1 {
+	/* max7310_b on i2c3 is gone */
+	status = "disabled";
+};
+
+&usbotg {
+	/* max7310_c on i2c3 is gone */
+	status = "okay";
+	dr_mode = "peripheral";
+};
diff --git a/arch/arm/dts/imx6q-sabreauto-gpmi-weim.dts b/arch/arm/dts/imx6q-sabreauto-gpmi-weim.dts
new file mode 100644
index 00000000000..579aeb26e05
--- /dev/null
+++ b/arch/arm/dts/imx6q-sabreauto-gpmi-weim.dts
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6q-sabreauto.dts"
+
+&ecspi1 {
+	/* pin conflict with weim */
+	status = "disabled";
+};
+
+&can2 {
+	/* max7310_c on i2c3 is gone */
+	status = "disabled";
+};
+
+&gpmi {
+	status = "okay";
+};
+
+&i2c3 {
+	/* pin conflict with weim */
+	status = "disabled";
+};
+
+&uart3 {
+	/* pin conflict with gpmi and weim */
+	status = "disabled";
+};
+
+&usbh1 {
+	/* max7310_b on i2c3 is gone */
+	status = "disabled";
+};
+
+&usbotg {
+	/* max7310_c on i2c3 is gone */
+	status = "okay";
+	dr_mode = "peripheral";
+};
+
+&weim {
+	pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6q-sabreauto.dts b/arch/arm/dts/imx6q-sabreauto.dts
index 6e981a3e0a8..08889239eb7 100644
--- a/arch/arm/dts/imx6q-sabreauto.dts
+++ b/arch/arm/dts/imx6q-sabreauto.dts
@@ -9,10 +9,30 @@
 #include "imx6qdl-sabreauto.dtsi"
 
 / {
-	model = "Freescale i.MX6 Quad SABRE Automotive Board";
+	model = "i.MX6 Quad SABRE Automotive Board";
 	compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
 };
 
+&ldb {
+	lvds-channel@0 {
+		crtc = "ipu2-di0";
+	};
+	lvds-channel@1 {
+		crtc = "ipu2-di1";
+	};
+};
+&mxcfb1 {
+	status = "okay";
+};
+&mxcfb2 {
+	status = "okay";
+};
+&mxcfb3 {
+	status = "okay";
+};
+&mxcfb4 {
+	status = "okay";
+};
 &sata {
 	status = "okay";
 };
diff --git a/arch/arm/dts/imx6q-sabresd.dts b/arch/arm/dts/imx6q-sabresd.dts
index eec944673c0..e3cd664a225 100644
--- a/arch/arm/dts/imx6q-sabresd.dts
+++ b/arch/arm/dts/imx6q-sabresd.dts
@@ -9,10 +9,42 @@
 #include "imx6qdl-sabresd.dtsi"
 
 / {
-	model = "Freescale i.MX6 Quad SABRE Smart Device Board";
+	model = "i.MX6 Quad SABRE Smart Device Board";
 	compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
 };
 
+&battery {
+	offset-charger = <1900>;
+	offset-discharger = <1694>;
+	offset-usb-charger = <1685>;
+};
+
+&ldb {
+	lvds-channel@0 {
+		crtc = "ipu2-di0";
+	};
+
+	lvds-channel@1 {
+		crtc = "ipu2-di1";
+	};
+};
+
+&mxcfb1 {
+	status = "okay";
+};
+
+&mxcfb2 {
+	status = "okay";
+};
+
+&mxcfb3 {
+	status = "okay";
+};
+
+&mxcfb4 {
+	status = "okay";
+};
+
 &sata {
 	status = "okay";
 };
diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi
index c37484dce35..bc552d0c73d 100644
--- a/arch/arm/dts/imx6q.dtsi
+++ b/arch/arm/dts/imx6q.dtsi
@@ -39,130 +39,108 @@
 				396000	1175000
 			>;
 			clock-latency = <61036>; /* two CLK32 periods */
-			#cooling-cells = <2>;
 			clocks = <&clks IMX6QDL_CLK_ARM>,
 				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
 				 <&clks IMX6QDL_CLK_STEP>,
 				 <&clks IMX6QDL_CLK_PLL1_SW>,
-				 <&clks IMX6QDL_CLK_PLL1_SYS>;
+				 <&clks IMX6QDL_CLK_PLL1_SYS>,
+				 <&clks IMX6QDL_CLK_PLL1>,
+				 <&clks IMX6QDL_PLL1_BYPASS>,
+				 <&clks IMX6QDL_PLL1_BYPASS_SRC>,
+				 <&clks IMX6QDL_CLK_VPU_AXI_PODF>;
 			clock-names = "arm", "pll2_pfd2_396m", "step",
-				      "pll1_sw", "pll1_sys";
+				      "pll1_sw", "pll1_sys", "pll1",
+				      "pll1_bypass", "pll1_bypass_src",
+				      "vpu_axi_podf";
 			arm-supply = <&reg_arm>;
 			pu-supply = <&reg_pu>;
 			soc-supply = <&reg_soc>;
 		};
 
-		cpu1: cpu@1 {
+		cpu@1 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			reg = <1>;
 			next-level-cache = <&L2>;
-			operating-points = <
-				/* kHz    uV */
-				1200000 1275000
-				996000  1250000
-				852000  1250000
-				792000  1175000
-				396000  975000
-			>;
-			fsl,soc-operating-points = <
-				/* ARM kHz  SOC-PU uV */
-				1200000 1275000
-				996000	1250000
-				852000	1250000
-				792000	1175000
-				396000	1175000
-			>;
-			clock-latency = <61036>; /* two CLK32 periods */
-			clocks = <&clks IMX6QDL_CLK_ARM>,
-				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
-				 <&clks IMX6QDL_CLK_STEP>,
-				 <&clks IMX6QDL_CLK_PLL1_SW>,
-				 <&clks IMX6QDL_CLK_PLL1_SYS>;
-			clock-names = "arm", "pll2_pfd2_396m", "step",
-				      "pll1_sw", "pll1_sys";
-			arm-supply = <&reg_arm>;
-			pu-supply = <&reg_pu>;
-			soc-supply = <&reg_soc>;
 		};
 
-		cpu2: cpu@2 {
+		cpu@2 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			reg = <2>;
 			next-level-cache = <&L2>;
-			operating-points = <
-				/* kHz    uV */
-				1200000 1275000
-				996000  1250000
-				852000  1250000
-				792000  1175000
-				396000  975000
-			>;
-			fsl,soc-operating-points = <
-				/* ARM kHz  SOC-PU uV */
-				1200000 1275000
-				996000	1250000
-				852000	1250000
-				792000	1175000
-				396000	1175000
-			>;
-			clock-latency = <61036>; /* two CLK32 periods */
-			clocks = <&clks IMX6QDL_CLK_ARM>,
-				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
-				 <&clks IMX6QDL_CLK_STEP>,
-				 <&clks IMX6QDL_CLK_PLL1_SW>,
-				 <&clks IMX6QDL_CLK_PLL1_SYS>;
-			clock-names = "arm", "pll2_pfd2_396m", "step",
-				      "pll1_sw", "pll1_sys";
-			arm-supply = <&reg_arm>;
-			pu-supply = <&reg_pu>;
-			soc-supply = <&reg_soc>;
 		};
 
-		cpu3: cpu@3 {
+		cpu@3 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			reg = <3>;
 			next-level-cache = <&L2>;
-			operating-points = <
-				/* kHz    uV */
-				1200000 1275000
-				996000  1250000
-				852000  1250000
-				792000  1175000
-				396000  975000
-			>;
-			fsl,soc-operating-points = <
-				/* ARM kHz  SOC-PU uV */
-				1200000 1275000
-				996000	1250000
-				852000	1250000
-				792000	1175000
-				396000	1175000
-			>;
-			clock-latency = <61036>; /* two CLK32 periods */
-			clocks = <&clks IMX6QDL_CLK_ARM>,
-				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
-				 <&clks IMX6QDL_CLK_STEP>,
-				 <&clks IMX6QDL_CLK_PLL1_SW>,
-				 <&clks IMX6QDL_CLK_PLL1_SYS>;
-			clock-names = "arm", "pll2_pfd2_396m", "step",
-				      "pll1_sw", "pll1_sys";
-			arm-supply = <&reg_arm>;
-			pu-supply = <&reg_pu>;
-			soc-supply = <&reg_soc>;
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x14000000>;
+			linux,cma-default;
 		};
 	};
 
 	soc {
-		ocram: sram@900000 {
+		busfreq: busfreq {
+			compatible = "fsl,imx_busfreq";
+			clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
+				<&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>;
+			clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
+				"periph_pre", "periph_clk2", "periph_clk2_sel", "osc";
+			interrupts = <0 107 0x04>, <0 112 0x4>, <0 113 0x4>, <0 114 0x4>;
+			interrupt-names = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3";
+			fsl,max_ddr_freq = <528000000>;
+		};
+
+                gpu: gpu@00130000 {
+			compatible = "fsl,imx6q-gpu";
+			reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
+			      <0x02204000 0x4000>, <0x10000000 0x0>,
+			      <0x0 0x8000000>;
+			reg-names = "iobase_3d", "iobase_2d",
+				    "iobase_vg", "phys_baseaddr",
+				    "contiguous_mem";
+			interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>,
+				     <0 10 IRQ_TYPE_LEVEL_HIGH>,
+				     <0 11 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "irq_3d", "irq_2d", "irq_vg";
+			clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, <&clks IMX6QDL_CLK_OPENVG_AXI>,
+				 <&clks IMX6QDL_CLK_GPU3D_AXI>, <&clks IMX6QDL_CLK_GPU2D_CORE>,
+				 <&clks IMX6QDL_CLK_GPU3D_CORE>, <&clks IMX6QDL_CLK_GPU3D_SHADER>;
+			clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
+				      "gpu3d_axi_clk", "gpu2d_clk",
+				      "gpu3d_clk", "gpu3d_shader_clk";
+			resets = <&src 0>, <&src 3>, <&src 3>;
+			reset-names = "gpu3d", "gpu2d", "gpuvg";
+			power-domains = <&pd_pu>;
+		};
+
+		ocram: sram@905000 {
 			compatible = "mmio-sram";
-			reg = <0x00900000 0x40000>;
+			reg = <0x905000 0x3B000>;
 			clocks = <&clks IMX6QDL_CLK_OCRAM>;
 		};
 
-		bus@2000000 { /* AIPS1 */
+		ocram_optee: sram@938000 {
+			compatible = "fsl,optee-lpm-sram";
+			reg = <0x938000 0x8000>;
+			overw_reg = <&ocram 0x905000 0x33000>;
+		};
+
+		bus@2000000  { /* AIPS1 */
 			spba-bus@2000000 {
 				ecspi5: spi@2018000 {
 					#address-cells = <1>;
@@ -173,14 +151,22 @@
 					clocks = <&clks IMX6Q_CLK_ECSPI5>,
 						 <&clks IMX6Q_CLK_ECSPI5>;
 					clock-names = "ipg", "per";
-					dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
+					dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
 					dma-names = "rx", "tx";
 					status = "disabled";
 				};
 			};
+		};
 
-			iomuxc: iomuxc@20e0000 {
-				compatible = "fsl,imx6q-iomuxc";
+		bus@2100000 { /* AIPS2 */
+			mipi_dsi: mipi@21e0000 {
+				compatible = "fsl,imx6q-mipi-dsi";
+				reg = <0x21e0000 0x4000>;
+				interrupts = <0 102 0x4>;
+				gpr = <&gpr>;
+				clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>;
+				clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
+				status = "disabled";
 			};
 		};
 
@@ -192,6 +178,7 @@
 				 <&clks IMX6QDL_CLK_SATA_REF_100M>,
 				 <&clks IMX6QDL_CLK_AHB>;
 			clock-names = "sata", "sata_ref", "ahb";
+			gpr = <&gpr>;
 			status = "disabled";
 		};
 
@@ -215,9 +202,18 @@
 				     <0 7 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clks IMX6QDL_CLK_IPU2>,
 				 <&clks IMX6QDL_CLK_IPU2_DI0>,
-				 <&clks IMX6QDL_CLK_IPU2_DI1>;
-			clock-names = "bus", "di0", "di1";
+				 <&clks IMX6QDL_CLK_IPU2_DI1>,
+				 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>,
+				 <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
+				 <&clks IMX6QDL_CLK_LDB_DI0>,
+				 <&clks IMX6QDL_CLK_LDB_DI1>;
+			clock-names = "bus",
+				      "di0", "di1",
+				      "di0_sel", "di1_sel",
+				      "ldb_di0", "ldb_di1";
+
 			resets = <&src 4>;
+			bypass_reset = <0>;
 
 			ipu2_csi0: port@0 {
 				reg = <0>;
@@ -302,6 +298,11 @@
 		compatible = "fsl,imx-display-subsystem";
 		ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
 	};
+
+	gpu-subsystem {
+		compatible = "fsl,imx-gpu-subsystem";
+		cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
+	};
 };
 
 &gpio1 {
@@ -423,6 +424,10 @@
 	};
 };
 
+&iomuxc {
+	compatible = "fsl,imx6q-iomuxc";
+};
+
 &ipu1_csi1 {
 	ipu1_csi1_from_mipi_vc1: endpoint {
 		remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
@@ -430,13 +435,19 @@
 };
 
 &ldb {
-	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+	compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
+	clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>,
 		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 		 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
-		 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
-	clock-names = "di0_pll", "di1_pll",
-		      "di0_sel", "di1_sel", "di2_sel", "di3_sel",
-		      "di0", "di1";
+		 <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>,
+		 <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>,
+		 <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>;
+	clock-names = "ldb_di0", "ldb_di1",
+		      "di0_sel", "di1_sel",
+		      "di2_sel", "di3_sel",
+		      "ldb_di0_div_3_5", "ldb_di1_div_3_5",
+		      "ldb_di0_div_7", "ldb_di1_div_7",
+		      "ldb_di0_div_sel", "ldb_di1_div_sel";
 
 	lvds-channel@0 {
 		port@2 {
diff --git a/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi b/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi
index bf6b3a5ce07..6aa51709eb4 100644
--- a/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi
+++ b/arch/arm/dts/imx6qdl-dhcom-pdk2.dtsi
@@ -256,6 +256,7 @@
 };
 
 &pwm1 {
+	#pwm-cells = <3>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi b/arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi
index ea90f40a426..7c078e166fe 100644
--- a/arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi
+++ b/arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi
@@ -5,12 +5,6 @@
 
 #include "imx6qdl-u-boot.dtsi"
 
-/ {
-	aliases {
-		mmc0 = &usdhc3;
-	};
-};
-
 &usdhc3 {
 	no-1-8-v;
 	u-boot,dm-spl;
diff --git a/arch/arm/dts/imx6qdl-sabreauto.dtsi b/arch/arm/dts/imx6qdl-sabreauto.dtsi
index 28a7fdb0f1e..26c1ec17f9b 100644
--- a/arch/arm/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/dts/imx6qdl-sabreauto.dtsi
@@ -2,68 +2,76 @@
 //
 // Copyright 2012 Freescale Semiconductor, Inc.
 // Copyright 2011 Linaro Ltd.
+// Copyright 2017 NXP.
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 
 / {
-	chosen {
-		stdout-path = &uart4;
-	};
-
-	memory@10000000 {
-		reg = <0x10000000 0x80000000>;
+	aliases {
+		mxcfb0 = &mxcfb1;
+		mxcfb1 = &mxcfb2;
+		mxcfb2 = &mxcfb3;
+		mxcfb3 = &mxcfb4;
 	};
 
-	leds {
-		compatible = "gpio-leds";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpio_leds>;
-
-		user {
-			label = "debug";
-			gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
-		};
+	chosen {
+		stdout-path = &uart4;
 	};
 
 	gpio-keys {
-		compatible = "gpio-keys";
+		compatible = "gpio-keys1";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_gpio_keys>;
 
 		home {
 			label = "Home";
 			gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+			gpio-key,wakeup;
 			linux,code = <KEY_HOME>;
-			wakeup-source;
 		};
 
 		back {
 			label = "Back";
 			gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+			gpio-key,wakeup;
 			linux,code = <KEY_BACK>;
-			wakeup-source;
 		};
 
 		program {
 			label = "Program";
 			gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+			gpio-key,wakeup;
 			linux,code = <KEY_PROGRAM>;
-			wakeup-source;
 		};
 
 		volume-up {
 			label = "Volume Up";
 			gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+			gpio-key,wakeup;
 			linux,code = <KEY_VOLUMEUP>;
-			wakeup-source;
 		};
 
 		volume-down {
 			label = "Volume Down";
 			gpios = <&gpio5 14 GPIO_ACTIVE_LOW>;
+			gpio-key,wakeup;
 			linux,code = <KEY_VOLUMEDOWN>;
-			wakeup-source;
+		};
+	};
+
+	memory:	memory {
+		reg = <0x10000000 0x80000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_leds>;
+
+		user {
+			label = "debug";
+			gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
 		};
 	};
 
@@ -89,6 +97,14 @@
 			regulator-always-on;
 		};
 
+		reg_3p3v: 3p3v {
+			compatible = "regulator-fixed";
+			regulator-name = "3P3V";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
 		reg_usb_h1_vbus: regulator@1 {
 			compatible = "regulator-fixed";
 			reg = <1>;
@@ -108,28 +124,159 @@
 			gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
+
+		reg_si4763_vio1: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "vio1";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		reg_si4763_vio2: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "vio2";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		reg_si4763_vd: regulator@5 {
+			compatible = "regulator-fixed";
+			reg = <5>;
+			regulator-name = "vd";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		reg_si4763_va: regulator@6 {
+			compatible = "regulator-fixed";
+			reg = <6>;
+			regulator-name = "va";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+
+		reg_sd3_vmmc: regulator@7 {
+			compatible = "regulator-fixed";
+			regulator-name = "P3V3_SDa_SWITCHED";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			off-on-delay-us = <20000>;
+			/* remove below line to enable this regulator */
+			status = "disabled";
+		};
+
+		reg_can_en: regulator@8 {
+			compatible = "regulator-fixed";
+			reg = <8>;
+			regulator-name = "can-en";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_can_stby: regulator@9 {
+			compatible = "regulator-fixed";
+			reg = <9>;
+			regulator-name = "can-stby";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&reg_can_en>;
+		};
+	};
+
+	hannstar_cabc {
+		compatible = "hannstar,cabc";
+
+		lvds_share {
+			gpios = <&max7310_a 0 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	sound-hdmi {
+		compatible = "fsl,imx6q-audio-hdmi",
+			     "fsl,imx-audio-hdmi";
+		model = "imx-audio-hdmi";
+		hdmi-controller = <&hdmi_audio>;
+	};
+
+	mxcfb1: fb@0 {
+		compatible = "fsl,mxc_sdc_fb";
+		disp_dev = "ldb";
+		interface_pix_fmt = "RGB666";
+		default_bpp = <16>;
+		int_clk = <0>;
+		late_init = <0>;
+		status = "disabled";
+	};
+
+	mxcfb2: fb@1 {
+		compatible = "fsl,mxc_sdc_fb";
+		disp_dev = "hdmi";
+		interface_pix_fmt = "RGB24";
+		mode_str ="1920x1080M@60";
+		default_bpp = <24>;
+		int_clk = <0>;
+		late_init = <0>;
+		status = "disabled";
+	};
+
+	mxcfb3: fb@2 {
+		compatible = "fsl,mxc_sdc_fb";
+		disp_dev = "lcd";
+		interface_pix_fmt = "RGB565";
+		mode_str ="CLAA-WVGA";
+		default_bpp = <16>;
+		int_clk = <0>;
+		late_init = <0>;
+		status = "disabled";
+	};
+
+	mxcfb4: fb@3 {
+		compatible = "fsl,mxc_sdc_fb";
+		disp_dev = "ldb";
+		interface_pix_fmt = "RGB666";
+		default_bpp = <16>;
+		int_clk = <0>;
+		late_init = <0>;
+		status = "disabled";
+	};
+
+	clocks {
+		codec_osc: anaclk2 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <24576000>;
+		};
 	};
 
 	sound-cs42888 {
 		compatible = "fsl,imx6-sabreauto-cs42888",
-			"fsl,imx-audio-cs42888";
+				"fsl,imx-audio-cs42888";
 		model = "imx-cs42888";
-		audio-cpu = <&esai>;
-		audio-asrc = <&asrc>;
+		esai-controller = <&esai>;
+		asrc-controller = <&asrc>;
 		audio-codec = <&codec>;
-		audio-routing =
-			"Line Out Jack", "AOUT1L",
-			"Line Out Jack", "AOUT1R",
-			"Line Out Jack", "AOUT2L",
-			"Line Out Jack", "AOUT2R",
-			"Line Out Jack", "AOUT3L",
-			"Line Out Jack", "AOUT3R",
-			"Line Out Jack", "AOUT4L",
-			"Line Out Jack", "AOUT4R",
-			"AIN1L", "Line In Jack",
-			"AIN1R", "Line In Jack",
-			"AIN2L", "Line In Jack",
-			"AIN2R", "Line In Jack";
+	};
+
+	sound-fm {
+		compatible = "fsl,imx-audio-si476x",
+			   "fsl,imx-tuner-si476x";
+		model = "imx-radio-si4763";
+		ssi-controller = <&ssi2>;
+		fm-controller = <&si476x_codec>;
+		mux-int-port = <2>;
+		mux-ext-port = <5>;
 	};
 
 	sound-spdif {
@@ -163,19 +310,22 @@
 			#size-cells = <0>;
 			reg = <1>;
 
-			adv7180: camera@21 {
-				compatible = "adi,adv7180";
+			adv7180: adv7180@21 {
+				compatible = "adv,adv7180";
 				reg = <0x21>;
-				powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
-				interrupt-parent = <&gpio1>;
-				interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
-
-				port {
-					adv7180_to_ipu1_csi0_mux: endpoint {
-						remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
-						bus-width = <8>;
-					};
-				};
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_ipu1_1>;
+				clocks = <&clks IMX6QDL_CLK_CKO>;
+				clock-names = "csi_mclk";
+				DOVDD-supply = <&reg_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */
+				AVDD-supply = <&reg_3p3v>;  /* 1.8v */
+				DVDD-supply = <&reg_3p3v>;  /* 1.8v */
+				PVDD-supply = <&reg_3p3v>;  /* 1.8v */
+				pwn-gpios = <&max7310_b 2 0>;
+				csi_id = <0>;
+				mclk = <24000000>;
+				mclk_source = <0>;
+				cvbs = <1>;
 			};
 
 			max7310_a: gpio@30 {
@@ -202,28 +352,45 @@
 				#gpio-cells = <2>;
 			};
 
-			light-sensor@44 {
-				compatible = "isil,isl29023";
+			isl29023@44 {
+				compatible = "fsl,isl29023";
 				reg = <0x44>;
+				rext = <499>;
 				interrupt-parent = <&gpio5>;
-				interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
+				interrupts = <17 2>;
 			};
 
-			magnetometer@e {
+			mag3110@0e {
 				compatible = "fsl,mag3110";
 				reg = <0x0e>;
+				position = <2>;
 				interrupt-parent = <&gpio2>;
-				interrupts = <29 IRQ_TYPE_EDGE_RISING>;
+				interrupts = <29 1>;
 			};
 
-			accelerometer@1c {
+			mma8451@1c {
 				compatible = "fsl,mma8451";
 				reg = <0x1c>;
+				position = <7>;
 				interrupt-parent = <&gpio6>;
-				interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
+				interrupts = <31 8>;
+				interrupt-route = <1>;
 			};
 		};
 	};
+
+	v4l2_cap_0 {
+		compatible = "fsl,imx6q-v4l2-capture";
+		ipu_id = <0>;
+		csi_id = <0>;
+		mclk_source = <0>;
+		status = "okay";
+	};
+
+	v4l2_out {
+		compatible = "fsl,mxc_v4l2_output";
+		status = "okay";
+	};
 };
 
 &ipu1_csi0_from_ipu1_csi0_mux {
@@ -231,7 +398,10 @@
 };
 
 &ipu1_csi0_mux_from_parallel_sensor {
+	/* Downstream driver doesn't use endpoints */
+	/*
 	remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
+	 */
 	bus-width = <8>;
 };
 
@@ -240,6 +410,12 @@
 	pinctrl-0 = <&pinctrl_ipu1_csi0>;
 };
 
+&audmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_audmux>;
+	status = "okay";
+};
+
 &clks {
 	assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
 			  <&clks IMX6QDL_PLL4_BYPASS>,
@@ -248,12 +424,25 @@
 			  <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
 	assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
 				 <&clks IMX6QDL_PLL4_BYPASS_SRC>,
-				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
-				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+				 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
+				 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
 	assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
 };
 
+&dcic1 {
+	dcic_id = <0>;
+	dcic_mux = "dcic-hdmi";
+	status = "okay";
+};
+
+&dcic2 {
+	dcic_id = <1>;
+	dcic_mux = "dcic-lvds0";
+	status = "okay";
+};
+
 &ecspi1 {
+	fsl,spi-num-chipselects = <1>;
 	cs-gpios = <&gpio3 19 0>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
@@ -282,31 +471,86 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;
 	phy-mode = "rgmii-id";
-	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
-			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+	phy-handle = <&phy>;
+	fsl,magic-packet;
 	fsl,err006687-workaround-present;
 	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy: ethernet-phy@1 {
+			reg = <1>;
+			qca,clk-out-frequency = <125000000>;
+		};
+	};
+};
+
+&can1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	pinctrl-assert-gpios = <&max7310_b 3 GPIO_ACTIVE_HIGH>; /* TX */
+	xceiver-supply = <&reg_can_stby>;
+	status = "disabled"; /* pin conflict with fec */
+};
+
+&can2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	xceiver-supply = <&reg_can_stby>;
+	status = "okay";
 };
 
 &gpmi {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpmi_nand>;
+	status = "disabled"; /* pin conflict with uart3 */
+	nand-on-flash-bbt;
+	fsl,use-minimum-ecc;
+};
+
+&hdmi_audio {
 	status = "okay";
 };
 
-&hdmi {
+&hdmi_cec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hdmi_cec>;
-	ddc-i2c-bus = <&i2c2>;
+	status = "okay";
+};
+
+&hdmi_core {
+	ipu_id = <0>;
+	disp_id = <1>;
+	status = "okay";
+};
+
+&hdmi_video {
+	fsl,phy_reg_vlev = <0x0294>;
+	fsl,phy_reg_cksymtx = <0x800d>;
 	status = "okay";
 };
 
 &i2c2 {
 	clock-frequency = <100000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
+	egalax_ts@04 {
+		compatible = "eeti,egalax_ts";
+		reg = <0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_egalax_int>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <28 2>;
+		wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
+	};
+
 	pmic: pfuze100@8 {
 		compatible = "fsl,pfuze100";
 		reg = <0x08>;
@@ -352,6 +596,7 @@
 			sw4_reg: sw4 {
 				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
 			};
 
 			swbst_reg: swbst {
@@ -406,6 +651,11 @@
 		};
 	};
 
+	hdmi_edid: edid@50 {
+		compatible = "fsl,imx6-hdmi-i2c";
+		reg = <0x50>;
+	};
+
 	codec: cs42888@48 {
 		compatible = "cirrus,cs42888";
 		reg = <0x48>;
@@ -417,20 +667,27 @@
 		VLC-supply = <&reg_audio>;
 	};
 
-	touchscreen@4 {
-		compatible = "eeti,egalax_ts";
-		reg = <0x04>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_egalax_int>;
-		interrupt-parent = <&gpio2>;
-		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
-		wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
+	si4763: si4763@63 {
+		compatible = "si4761";
+		reg = <0x63>;
+		va-supply = <&reg_si4763_va>;
+		vd-supply = <&reg_si4763_vd>;
+		vio1-supply = <&reg_si4763_vio1>;
+		vio2-supply = <&reg_si4763_vio2>;
+		revision-a10; /* set to default A10 compatible command set */
+
+		si476x_codec: si476x-codec {
+			compatible = "si476x-codec";
+		};
 	};
 };
 
 &i2c3 {
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
 
@@ -439,11 +696,25 @@
 	pinctrl-0 = <&pinctrl_hog>;
 
 	imx6qdl-sabreauto {
+                pinctrl_audmux: audmux {
+                        fsl,pins = <
+                                MX6QDL_PAD_DISP0_DAT16__AUD5_TXC  0x130b0
+                                MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
+                                MX6QDL_PAD_DISP0_DAT19__AUD5_RXD  0x130b0
+                        >;
+                };
+
 		pinctrl_hog: hoggrp {
 			fsl,pins = <
-				MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
+				MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1f059
 				MX6QDL_PAD_SD2_DAT2__GPIO1_IO13  0x80000000
 				MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
+				MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000
+				MX6QDL_PAD_EIM_EB1__GPIO2_IO29	0x80000000
+				MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x80000000
+				MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000
+				MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x17059
+				MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x17059
 			>;
 		};
 
@@ -461,9 +732,9 @@
 			>;
 		};
 
-		pinctrl_egalax_int: egalax-intgrp {
+		pinctrl_egalax_int: egalax_intgrp {
 			fsl,pins = <
-				MX6QDL_PAD_EIM_EB0__GPIO2_IO28		0xb0b1
+				MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x80000000
 			>;
 		};
 
@@ -484,6 +755,12 @@
 				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
 				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
 				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
+			>;
+		};
+
+		pinctrl_enet_irq: enetirqgrp {
+			fsl,pins = <
 				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
 			>;
 		};
@@ -503,13 +780,27 @@
 			>;
 		};
 
-		pinctrl_gpio_keys: gpiokeysgrp {
+		pinctrl_flexcan1: flexcan1grp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x17059
+				MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x17059
+			>;
+		};
+
+		pinctrl_flexcan2: flexcan2grp {
 			fsl,pins = <
-				MX6QDL_PAD_SD2_CMD__GPIO1_IO11		0x1b0b0
-				MX6QDL_PAD_SD2_DAT3__GPIO1_IO12		0x1b0b0
-				MX6QDL_PAD_SD4_DAT4__GPIO2_IO12		0x1b0b0
-				MX6QDL_PAD_SD4_DAT7__GPIO2_IO15		0x1b0b0
-				MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14	0x1b0b0
+				MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX	0x17059
+				MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX	0x17059
+			>;
+		};
+
+		pinctrl_gpio_keys: gpio_keysgrp {
+			fsl,pins = <
+				MX6QDL_PAD_SD2_CMD__GPIO1_IO11	0x1b0b0
+				MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
+				MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
+				MX6QDL_PAD_SD4_DAT7__GPIO2_IO15	0x1b0b0
+				MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
 			>;
 		};
 
@@ -541,16 +832,41 @@
 			>;
 		};
 
-		pinctrl_hdmi_cec: hdmicecgrp {
+		pinctrl_i2c2: i2c2grp {
 			fsl,pins = <
-				MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE	0x1f8b0
+				MX6QDL_PAD_EIM_EB2__I2C2_SCL	0x4001b8b1
+				MX6QDL_PAD_KEY_ROW3__I2C2_SDA	0x4001b8b1
 			>;
 		};
 
-		pinctrl_i2c2: i2c2grp {
+		pinctrl_i2c2_gpio: i2c2grp_gpio {
 			fsl,pins = <
-				MX6QDL_PAD_EIM_EB2__I2C2_SCL	0x4001b8b1
-				MX6QDL_PAD_KEY_ROW3__I2C2_SDA	0x4001b8b1
+				MX6QDL_PAD_EIM_EB2__GPIO2_IO30    0x1b8b1
+				MX6QDL_PAD_KEY_ROW3__GPIO4_IO13   0x1b8b1
+			>;
+		};
+
+		pinctrl_ipu1_1: ipu1grp-1 { /* parallel port 16-bit */
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04   0x80000000
+				MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05   0x80000000
+				MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06   0x80000000
+				MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07   0x80000000
+				MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08   0x80000000
+				MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09   0x80000000
+				MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10  0x80000000
+				MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11  0x80000000
+				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0x80000000
+				MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0x80000000
+				MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0x80000000
+				MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0x80000000
+				MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0x80000000
+				MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0x80000000
+				MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0x80000000
+				MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0x80000000
+				MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
+				MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0x80000000
+				MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0x80000000
 			>;
 		};
 
@@ -561,6 +877,13 @@
 			>;
 		};
 
+		pinctrl_i2c3_gpio: i2c3grp_gpio {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_3__GPIO1_IO03  0x1b8b1
+				MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b8b1
+			>;
+		};
+
 		pinctrl_i2c3mux: i2c3muxgrp {
 			fsl,pins = <
 				MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
@@ -589,6 +912,14 @@
 			>;
 		};
 
+		pinctrl_mlb: mlb {
+			fsl,pins = <
+				MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x80000000
+				MX6QDL_PAD_GPIO_6__MLB_SIG    0x80000000
+				MX6QDL_PAD_GPIO_2__MLB_DATA   0x80000000
+			>;
+		};
+
 		pinctrl_pwm3: pwm1grp {
 			fsl,pins = <
 				MX6QDL_PAD_SD4_DAT1__PWM3_OUT		0x1b0b1
@@ -613,6 +944,24 @@
 			>;
 		};
 
+		pinctrl_uart3_1: uart3grp-1 {
+			fsl,pins = <
+				MX6QDL_PAD_SD4_CLK__UART3_RX_DATA	0x1b0b1
+				MX6QDL_PAD_SD4_CMD__UART3_TX_DATA	0x1b0b1
+				MX6QDL_PAD_EIM_D30__UART3_CTS_B		0x1b0b1
+				MX6QDL_PAD_EIM_EB3__UART3_RTS_B		0x1b0b1
+			>;
+		};
+
+		pinctrl_uart3dte_1: uart3dtegrp-1 {
+			fsl,pins = <
+				MX6QDL_PAD_SD4_CLK__UART3_TX_DATA	0x1b0b1
+				MX6QDL_PAD_SD4_CMD__UART3_RX_DATA	0x1b0b1
+				MX6QDL_PAD_EIM_D30__UART3_RTS_B		0x1b0b1
+				MX6QDL_PAD_EIM_EB3__UART3_CTS_B		0x1b0b1
+			>;
+		};
+
 		pinctrl_uart4: uart4grp {
 			fsl,pins = <
 				MX6QDL_PAD_KEY_COL0__UART4_TX_DATA	0x1b0b1
@@ -626,6 +975,17 @@
 			>;
 		};
 
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD1_CMD__SD1_CMD             0x17071
+				MX6QDL_PAD_SD1_CLK__SD1_CLK             0x10071
+				MX6QDL_PAD_SD1_DAT0__SD1_DATA0          0x17071
+				MX6QDL_PAD_SD1_DAT1__SD1_DATA1          0x17071
+				MX6QDL_PAD_SD1_DAT2__SD1_DATA2          0x17071
+				MX6QDL_PAD_SD1_DAT3__SD1_DATA3          0x17071
+			>;
+		};
+
 		pinctrl_usdhc3: usdhc3grp {
 			fsl,pins = <
 				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
@@ -724,6 +1084,12 @@
 				MX6QDL_PAD_EIM_DA0__EIM_AD00		0xb0b1
 			>;
 		};
+
+		pinctrl_hdmi_cec: hdmicecgrp {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
+			>;
+		};
 	};
 };
 
@@ -733,6 +1099,7 @@
 	lvds-channel@0 {
 		fsl,data-mapping = "spwg";
 		fsl,data-width = <18>;
+		primary;
 		status = "okay";
 
 		display-timings {
@@ -750,6 +1117,33 @@
 			};
 		};
 	};
+
+	lvds-channel@1 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <18>;
+		status = "okay";
+
+		display-timings {
+			native-mode = <&timing1>;
+			timing1: hsd100pxn1 {
+				clock-frequency = <65000000>;
+				hactive = <1024>;
+				vactive = <768>;
+				hback-porch = <220>;
+				hfront-porch = <40>;
+				vback-porch = <21>;
+				vfront-porch = <7>;
+				hsync-len = <60>;
+				vsync-len = <10>;
+			};
+		};
+	};
+};
+
+&mlb {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_mlb>;
+	status = "okay";
 };
 
 &pwm3 {
@@ -758,12 +1152,44 @@
 	status = "okay";
 };
 
+&pcie {
+	status = "okay";
+};
+
 &spdif {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_spdif>;
+	assigned-clocks = <&clks IMX6QDL_CLK_SPDIF_SEL>,
+			  <&clks IMX6QDL_CLK_SPDIF_PODF>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_PFD3_454M>;
+	assigned-clock-rates = <0>, <227368421>;
 	status = "okay";
 };
 
+&snvs_poweroff {
+	status = "okay";
+};
+
+&ssi2 {
+	assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <0>;
+	fsl,mode = "i2s-master";
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3_1>;
+	pinctrl-assert-gpios = <&max7310_b 4 GPIO_ACTIVE_HIGH>, /* CTS */
+			       <&max7310_c 3 GPIO_ACTIVE_HIGH>; /* RXD and TXD */
+	fsl,uart-has-rtscts;
+	status = "okay";
+	/* for DTE mode, add below change */
+	/* fsl,dte-mode; */
+	/* pinctrl-0 = <&pinctrl_uart3dte_1>; */
+};
+
 &uart4 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart4>;
@@ -779,6 +1205,19 @@
 	vbus-supply = <&reg_usb_otg_vbus>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usbotg>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+	no-1-8-v;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
 	status = "okay";
 };
 
@@ -789,6 +1228,20 @@
 	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 	cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+	/*
+	 * Due to board issue, we can not use external regulator for card slot
+	 * by default since the card power is shared with card detect pullup.
+	 * Disabling the vmmc regulator will cause unexpected card detect
+	 * interrupts.
+	 * HW rework is needed to fix this isssue. Remove R695 first, then you
+	 * can open below line to enable the using of external regulator.
+	 * Then you will be able to power off the card during suspend. This is
+	 * especially needed for a SD3.0 card re-enumeration working on UHS mode
+	 * Note: reg_sd3_vmmc is also need to be enabled
+	 */
+	/* vmmc-supply = <&reg_sd3_vmmc>; */
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/imx6qdl-sabresd.dtsi b/arch/arm/dts/imx6qdl-sabresd.dtsi
index eddb3901745..2c1d0288bf8 100644
--- a/arch/arm/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/dts/imx6qdl-sabresd.dtsi
@@ -2,21 +2,49 @@
 //
 // Copyright 2012 Freescale Semiconductor, Inc.
 // Copyright 2011 Linaro Ltd.
+// Copyright 2017 NXP.
 
 #include <dt-bindings/clock/imx6qdl-clock.h>
+
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 
 / {
 	aliases {
-		mmc1 = &usdhc3;
+		mxcfb0 = &mxcfb1;
+		mxcfb1 = &mxcfb2;
+		mxcfb2 = &mxcfb3;
+		mxcfb3 = &mxcfb4;
+	};
+
+	battery: max8903@0 {
+		compatible = "fsl,max8903-charger";
+		pinctrl-names = "default";
+		dok_input = <&gpio2 24 1>;
+		uok_input = <&gpio1 27 1>;
+		chg_input = <&gpio3 23 1>;
+		flt_input = <&gpio5 2 1>;
+		fsl,dcm_always_high;
+		fsl,dc_valid;
+		fsl,usb_valid;
+		status = "okay";
+	};
+
+	hannstar_cabc {
+		compatible = "hannstar,cabc";
+		lvds0 {
+			gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
+		};
+		lvds1 {
+			gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+		};
 	};
 
 	chosen {
 		stdout-path = &uart1;
 	};
 
-	memory@10000000 {
+	memory: memory {
 		reg = <0x10000000 0x40000000>;
 	};
 
@@ -64,6 +92,36 @@
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
 			gpio = <&gpio3 19 0>;
+			regulator-always-on;
+			enable-active-high;
+		};
+
+		reg_sensor: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "sensor-supply";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio2 31 0>;
+			startup-delay-us = <500>;
+			regulator-always-on;
+			enable-active-high;
+		};
+
+		reg_hdmi: regulator@5 {
+			compatible = "regulator-fixed";
+			reg = <5>;
+			regulator-name = "hdmi-5v-supply";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			hdmi-5v-supply = <&swbst_reg>;
+		};
+
+		reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on {
+			compatible = "regulator-fixed";
+			regulator-name = "mipi_dsi_pwr_on";
+			gpio = <&gpio6 14 0>;
 			enable-active-high;
 		};
 	};
@@ -99,20 +157,89 @@
 		compatible = "fsl,imx6q-sabresd-wm8962",
 			   "fsl,imx-audio-wm8962";
 		model = "wm8962-audio";
-		ssi-controller = <&ssi2>;
+		cpu-dai = <&ssi2>;
 		audio-codec = <&codec>;
+		asrc-controller = <&asrc>;
 		audio-routing =
 			"Headphone Jack", "HPOUTL",
 			"Headphone Jack", "HPOUTR",
 			"Ext Spk", "SPKOUTL",
 			"Ext Spk", "SPKOUTR",
 			"AMIC", "MICBIAS",
-			"IN3R", "AMIC";
+			"IN3R", "AMIC",
+			"DMIC", "MICBIAS",
+			"DMICDAT", "DMIC",
+			"CPU-Playback", "ASRC-Playback",
+			"Playback", "CPU-Playback",
+			"ASRC-Capture", "CPU-Capture",
+			"CPU-Capture", "Capture";
 		mux-int-port = <2>;
 		mux-ext-port = <3>;
+		codec-master;
+		hp-det-gpios = <&gpio7 8 1>;
+		mic-det-gpios = <&gpio1 9 1>;
+	};
+
+	sound-hdmi {
+		compatible = "fsl,imx6q-audio-hdmi",
+			     "fsl,imx-audio-hdmi";
+		model = "imx-audio-hdmi";
+		hdmi-controller = <&hdmi_audio>;
+	};
+
+	mxcfb1: fb@0 {
+		compatible = "fsl,mxc_sdc_fb";
+		disp_dev = "ldb";
+		interface_pix_fmt = "RGB666";
+		default_bpp = <16>;
+		int_clk = <0>;
+		late_init = <0>;
+		status = "disabled";
+	};
+
+	mxcfb2: fb@1 {
+		compatible = "fsl,mxc_sdc_fb";
+		disp_dev = "hdmi";
+		interface_pix_fmt = "RGB24";
+		mode_str ="1920x1080M@60";
+		default_bpp = <24>;
+		int_clk = <0>;
+		late_init = <0>;
+		status = "disabled";
 	};
 
-	backlight_lvds: backlight-lvds {
+	mxcfb3: fb@2 {
+		compatible = "fsl,mxc_sdc_fb";
+		disp_dev = "lcd";
+		interface_pix_fmt = "RGB565";
+		mode_str ="CLAA-WVGA";
+		default_bpp = <16>;
+		int_clk = <0>;
+		late_init = <0>;
+		status = "disabled";
+	};
+
+	mxcfb4: fb@3 {
+		compatible = "fsl,mxc_sdc_fb";
+		disp_dev = "ldb";
+		interface_pix_fmt = "RGB666";
+		default_bpp = <16>;
+		int_clk = <0>;
+		late_init = <0>;
+		status = "disabled";
+	};
+
+	lcd@0 {
+		compatible = "fsl,lcd";
+		ipu_id = <0>;
+		disp_id = <0>;
+		default_ifmt = "RGB565";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ipu1>;
+		status = "okay";
+	};
+
+	backlight {
 		compatible = "pwm-backlight";
 		pwms = <&pwm1 0 5000000>;
 		brightness-levels = <0 4 8 16 32 64 128 255>;
@@ -125,21 +252,32 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_gpio_leds>;
 
-		red {
+		charger-led {
 			gpios = <&gpio1 2 0>;
-			default-state = "on";
+			linux,default-trigger = "max8903-charger-charging";
+			retain-state-suspended;
 		};
 	};
 
-	panel {
-		compatible = "hannstar,hsd100pxn1";
-		backlight = <&backlight_lvds>;
+	v4l2_cap_0 {
+		compatible = "fsl,imx6q-v4l2-capture";
+		ipu_id = <0>;
+		csi_id = <0>;
+		mclk_source = <0>;
+		status = "okay";
+	};
 
-		port {
-			panel_in: endpoint {
-				remote-endpoint = <&lvds0_out>;
-			};
-		};
+	v4l2_cap_1 {
+		compatible = "fsl,imx6q-v4l2-capture";
+		ipu_id = <0>;
+		csi_id = <1>;
+		mclk_source = <0>;
+		status = "okay";
+	};
+
+	v4l2_out {
+		compatible = "fsl,mxc_v4l2_output";
+		status = "okay";
 	};
 };
 
@@ -151,7 +289,10 @@
 };
 
 &ipu1_csi0_mux_from_parallel_sensor {
+	/* Downstream driver doesn't use endpoints */
+	/*
 	remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
+	 */
 };
 
 &ipu1_csi0 {
@@ -161,16 +302,6 @@
 
 &mipi_csi {
 	status = "okay";
-
-	port@0 {
-		reg = <0>;
-
-		mipi_csi2_in: endpoint {
-			remote-endpoint = <&ov5640_to_mipi_csi2>;
-			clock-lanes = <0>;
-			data-lanes = <1 2>;
-		};
-	};
 };
 
 &audmux {
@@ -182,11 +313,12 @@
 &clks {
 	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
 			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
-	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
-				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
+				 <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
 };
 
 &ecspi1 {
+	fsl,spi-num-chipselects = <1>;
 	cs-gpios = <&gpio4 9 0>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ecspi1>;
@@ -206,20 +338,67 @@
 	pinctrl-0 = <&pinctrl_enet>;
 	phy-mode = "rgmii-id";
 	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+	phy-handle = <&phy>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy: ethernet-phy@1 {
+			reg = <1>;
+			qca,clk-out-frequency = <125000000>;
+		};
+	};
+};
+
+&gpc {
+	fsl,ldo-bypass = <1>;
+};
+
+&dcic1 {
+	dcic_id = <0>;
+	dcic_mux = "dcic-hdmi";
+	status = "okay";
+};
+
+&dcic2 {
+	dcic_id = <1>;
+	dcic_mux = "dcic-lvds1";
+	status = "okay";
+};
+
+&hdmi_audio {
 	status = "okay";
 };
 
-&hdmi {
+&hdmi_cec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hdmi_cec>;
-	ddc-i2c-bus = <&i2c2>;
+	status = "okay";
+};
+
+&hdmi_core {
+	ipu_id = <0>;
+	disp_id = <0>;
+	status = "okay";
+};
+
+&hdmi_video {
+	fsl,phy_reg_vlev = <0x0294>;
+	fsl,phy_reg_cksymtx = <0x800d>;
+	HDMI-supply = <&reg_hdmi>;
 	status = "okay";
 };
 
 &i2c1 {
 	clock-frequency = <100000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
 	codec: wm8962@1a {
@@ -242,61 +421,64 @@
 			0x8014 /* 4:FN_DMICCDAT */
 			0x0000 /* 5:Default */
 		>;
+		amic-mono;
 	};
 
-	ov5642: camera@3c {
-		compatible = "ovti,ov5642";
+	mma8451@1c {
+		compatible = "fsl,mma8451";
+		reg = <0x1c>;
+		position = <0>;
+		vdd-supply = <&reg_sensor>;
+		vddio-supply = <&reg_sensor>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <18 8>;
+		interrupt-route = <1>;
+	};
+
+	ov564x: ov564x@3c {
+		compatible = "ovti,ov564x";
+		reg = <0x3c>;
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_ov5642>;
+		pinctrl-0 = <&pinctrl_ipu1_2>;
 		clocks = <&clks IMX6QDL_CLK_CKO>;
-		clock-names = "xclk";
-		reg = <0x3c>;
+		clock-names = "csi_mclk";
 		DOVDD-supply = <&vgen4_reg>; /* 1.8v */
-		AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
-						rev B board is VGEN5 */
+		AVDD-supply = <&vgen3_reg>;  /* 2.8v, on rev C board is VGEN3,
+						on rev B board is VGEN5 */
 		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
-		powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
-		reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
-		status = "disabled";
-
-		port {
-			ov5642_to_ipu1_csi0_mux: endpoint {
-				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
-				bus-width = <8>;
-				hsync-active = <1>;
-				vsync-active = <1>;
-			};
-		};
+		pwn-gpios = <&gpio1 16 1>;   /* active low: SD1_DAT0 */
+		rst-gpios = <&gpio1 17 0>;   /* active high: SD1_DAT1 */
+		csi_id = <0>;
+		mclk = <24000000>;
+		mclk_source = <0>;
 	};
 };
 
 &i2c2 {
 	clock-frequency = <100000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
-	ov5640: camera@3c {
-		compatible = "ovti,ov5640";
+	egalax_ts@04 {
+		compatible = "eeti,egalax_ts";
+		reg = <0x04>;
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_ov5640>;
-		reg = <0x3c>;
-		clocks = <&clks IMX6QDL_CLK_CKO>;
-		clock-names = "xclk";
-		DOVDD-supply = <&vgen4_reg>; /* 1.8v */
-		AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
-						rev B board is VGEN5 */
-		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
-		powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
-		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
-
-		port {
-			ov5640_to_mipi_csi2: endpoint {
-				remote-endpoint = <&mipi_csi2_in>;
-				clock-lanes = <0>;
-				data-lanes = <1 2>;
-			};
-		};
+		pinctrl-0 = <&pinctrl_i2c2_egalax_int>;
+		interrupt-parent = <&gpio6>;
+		interrupts = <8 2>;
+		wakeup-gpios = <&gpio6 8 0>;
+	};
+
+	max11801@48 {
+		compatible = "maxim,max11801";
+		reg = <0x48>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <26 2>;
+		work-mode = <1>;/*DCM mode*/
 	};
 
 	pmic: pfuze100@8 {
@@ -399,21 +581,66 @@
 			};
 		};
 	};
+
+	hdmi_edid: edid@50 {
+		compatible = "fsl,imx6-hdmi-i2c";
+		reg = <0x50>;
+	};
+
+	ov564x_mipi: ov564x_mipi@3c { /* i2c2 driver */
+		compatible = "ovti,ov564x_mipi";
+		reg = <0x3c>;
+		clocks = <&clks 201>;
+		clock-names = "csi_mclk";
+		DOVDD-supply = <&vgen4_reg>; /* 1.8v */
+		AVDD-supply = <&vgen3_reg>;  /* 2.8v, rev C board is VGEN3
+						rev B board is VGEN5 */
+		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
+		pwn-gpios = <&gpio1 19 1>;   /* active low: SD1_CLK */
+		rst-gpios = <&gpio1 20 0>;   /* active high: SD1_DAT2 */
+		csi_id = <1>;
+		mclk = <24000000>;
+		mclk_source = <0>;
+	};
 };
 
 &i2c3 {
 	clock-frequency = <100000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
-	egalax_ts@4 {
+	egalax_ts@04 {
 		compatible = "eeti,egalax_ts";
 		reg = <0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_i2c3_egalax_int>;
 		interrupt-parent = <&gpio6>;
 		interrupts = <7 2>;
 		wakeup-gpios = <&gpio6 7 0>;
 	};
+
+	isl29023@44 {
+		compatible = "fsl,isl29023";
+		reg = <0x44>;
+		rext = <499>;
+		vdd-supply = <&reg_sensor>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <9 2>;
+	};
+
+	mag3110@0e {
+		compatible = "fsl,mag3110";
+		reg = <0x0e>;
+		position = <2>;
+		vdd-supply = <&reg_sensor>;
+		vddio-supply = <&reg_sensor>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <16 1>;
+	};
 };
 
 &iomuxc {
@@ -423,15 +650,29 @@
 	imx6qdl-sabresd {
 		pinctrl_hog: hoggrp {
 			fsl,pins = <
-				MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
-				MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
-				MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
-				MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
+				MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
+				MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
+				MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
+				MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
 				MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x130b0
-				MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
-				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
-				MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x1b0b0
-				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
+				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
+				MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x80000000
+				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
+				MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000
+				MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
+				MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
+				MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
+				MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
+				MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000
+				MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000
+				MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000
+				MX6QDL_PAD_SD3_RST__GPIO7_IO08	0x80000000
+				MX6QDL_PAD_GPIO_9__GPIO1_IO09 	0x80000000
+				MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
+				MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
+				MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
+				MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
+				MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000
 			>;
 		};
 
@@ -453,6 +694,18 @@
 			>;
 		};
 
+		pinctrl_i2c2_egalax_int: egalax_i2c2_intgrp {
+			fsl,pins = <
+				MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000
+			>;
+		};
+
+		pinctrl_i2c3_egalax_int: egalax_i2c3_intgrp {
+			fsl,pins = <
+				MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
+			>;
+		};
+
 		pinctrl_enet: enetgrp {
 			fsl,pins = <
 				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
@@ -474,6 +727,12 @@
 			>;
 		};
 
+		pinctrl_enet_irq: enetirqgrp {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
+			>;
+		};
+
 		pinctrl_gpio_keys: gpio_keysgrp {
 			fsl,pins = <
 				MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
@@ -484,7 +743,14 @@
 
 		pinctrl_hdmi_cec: hdmicecgrp {
 			fsl,pins = <
-				MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE	0x1f8b0
+				MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0
+			>;
+		};
+
+		pinctrl_hdmi_hdcp: hdmihdcpgrp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
+				MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
 			>;
 		};
 
@@ -495,6 +761,13 @@
 			>;
 		};
 
+		pinctrl_i2c1_gpio: i2c1grp_gpio {
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26        0x1b8b1
+				MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27        0x1b8b1
+			>;
+		};
+
 		pinctrl_i2c2: i2c2grp {
 			fsl,pins = <
 				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
@@ -502,6 +775,13 @@
 			>;
 		};
 
+		pinctrl_i2c2_gpio: i2c2_gpio_grp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL3__GPIO4_IO12		0x1b0b0
+				MX6QDL_PAD_KEY_ROW3__GPIO4_IO13		0x1b0b0
+			>;
+		};
+
 		pinctrl_i2c3: i2c3grp {
 			fsl,pins = <
 				MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
@@ -509,6 +789,66 @@
 			>;
 		};
 
+		pinctrl_i2c3_gpio: i2c3grp_gpio {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_3__GPIO1_IO03           0x1b8b1
+                                MX6QDL_PAD_GPIO_6__GPIO1_IO06           0x1b8b1
+                        >;
+                };
+
+		pinctrl_ipu1: ipu1grp {
+			fsl,pins = <
+				MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
+				MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
+				MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
+				MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
+				MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04        0x80000000
+				MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
+				MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
+				MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
+				MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
+				MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
+				MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
+				MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
+				MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
+				MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
+				MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
+				MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
+				MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
+				MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
+				MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
+				MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
+				MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
+				MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
+				MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
+				MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
+				MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
+				MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
+				MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
+				MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
+				MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
+			>;
+		};
+
+		pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
+			fsl,pins = <
+				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x80000000
+				MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13    0x80000000
+				MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14    0x80000000
+				MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15    0x80000000
+				MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16    0x80000000
+				MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17    0x80000000
+				MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18    0x80000000
+				MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19    0x80000000
+				MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
+				MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK   0x80000000
+				MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC      0x80000000
+				MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC     0x80000000
+				MX6QDL_PAD_SD1_DAT1__GPIO1_IO17            0x80000000
+				MX6QDL_PAD_SD1_DAT0__GPIO1_IO16            0x80000000
+			>;
+		};
+
 		pinctrl_ipu1_csi0: ipu1csi0grp {
 			fsl,pins = <
 				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12    0x1b0b0
@@ -564,6 +904,24 @@
 			>;
 		};
 
+		pinctrl_uart5_1: uart5grp-1 {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
+				MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
+				MX6QDL_PAD_KEY_COL4__UART5_RTS_B	0x1b0b1
+				MX6QDL_PAD_KEY_ROW4__UART5_CTS_B	0x1b0b1
+			>;
+		};
+
+		pinctrl_uart5dte_1: uart5dtegrp-1 {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA	0x1b0b1
+				MX6QDL_PAD_KEY_COL1__UART5_RX_DATA	0x1b0b1
+				MX6QDL_PAD_KEY_ROW4__UART5_RTS_B	0x1b0b1
+				MX6QDL_PAD_KEY_COL4__UART5_CTS_B	0x1b0b1
+			>;
+		};
+
 		pinctrl_usbotg: usbotggrp {
 			fsl,pins = <
 				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
@@ -617,7 +975,7 @@
 
 		pinctrl_wdog: wdoggrp {
 			fsl,pins = <
-				MX6QDL_PAD_GPIO_1__WDOG2_B		0x1b0b0
+				MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000
 			>;
 		};
 	};
@@ -634,26 +992,72 @@
 &ldb {
 	status = "okay";
 
-	lvds-channel@1 {
+	lvds-channel@0 {
 		fsl,data-mapping = "spwg";
 		fsl,data-width = <18>;
 		status = "okay";
 
-		port@4 {
-			reg = <4>;
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: hsd100pxn1 {
+				clock-frequency = <65000000>;
+				hactive = <1024>;
+				vactive = <768>;
+				hback-porch = <220>;
+				hfront-porch = <40>;
+				vback-porch = <21>;
+				vfront-porch = <7>;
+				hsync-len = <60>;
+				vsync-len = <10>;
+			};
+		};
+	};
+
+	lvds-channel@1 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <18>;
+		primary;
+		status = "okay";
 
-			lvds0_out: endpoint {
-				remote-endpoint = <&panel_in>;
+		display-timings {
+			native-mode = <&timing1>;
+			timing1: hsd100pxn1 {
+				clock-frequency = <65000000>;
+				hactive = <1024>;
+				vactive = <768>;
+				hback-porch = <220>;
+				hfront-porch = <40>;
+				vback-porch = <21>;
+				vfront-porch = <7>;
+				hsync-len = <60>;
+				vsync-len = <10>;
 			};
 		};
 	};
 };
 
+&mipi_csi {
+	status = "okay";
+	ipu_id = <0>;
+	csi_id = <1>;
+	v_channel = <0>;
+	lanes = <2>;
+};
+
+&mipi_dsi {
+	dev_id = <0>;
+	disp_id = <1>;
+	lcd_panel = "TRULY-WVGA";
+	disp-power-on-supply = <&reg_mipi_dsi_pwr_on>;
+	reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <50>;
+	status = "okay";
+};
+
 &pcie {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie>;
 	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
-	vpcie-supply = <&reg_pcie>;
 	status = "okay";
 };
 
@@ -680,6 +1084,13 @@
 };
 
 &ssi2 {
+	assigned-clocks = <&clks IMX6QDL_CLK_PLL4>,
+			  <&clks IMX6QDL_PLL4_BYPASS>,
+			  <&clks IMX6QDL_CLK_SSI2_SEL>;
+	assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>,
+				 <&clks IMX6QDL_CLK_PLL4>,
+				 <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <737280000>, <0>, <0>;
 	status = "okay";
 };
 
@@ -699,15 +1110,29 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usbotg>;
 	disable-over-current;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
 	status = "okay";
 };
 
+&usbphy1 {
+	fsl,tx-d-cal = <106>;
+};
+
+&usbphy2 {
+	fsl,tx-d-cal = <106>;
+};
+
 &usdhc2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usdhc2>;
 	bus-width = <8>;
 	cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+	no-1-8-v;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
 	status = "okay";
 };
 
@@ -717,6 +1142,9 @@
 	bus-width = <8>;
 	cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+	no-1-8-v;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
 	status = "okay";
 };
 
@@ -726,6 +1154,7 @@
 	bus-width = <8>;
 	non-removable;
 	no-1-8-v;
+	keep-power-in-suspend;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
index efd89510d51..c8a5c76ef0b 100644
--- a/arch/arm/dts/imx6qdl.dtsi
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -16,7 +16,7 @@
 	 * Also for U-Boot there must be a pre-existing /memory node.
 	 */
 	chosen {};
-	memory { device_type = "memory"; };
+	memory { device_type = "memory"; reg = <0 0>; };
 
 	aliases {
 		ethernet0 = &fec;
@@ -48,9 +48,16 @@
 		spi3 = &ecspi4;
 		usbphy0 = &usbphy1;
 		usbphy1 = &usbphy2;
+		usb0 = &usbotg;
+		usb1 = &usbh1;
+		usbgadget0 = &usbg1;
+		pci0 = &pcie;
 	};
 
 	clocks {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		ckil {
 			compatible = "fsl,imx-ckil", "fixed-clock";
 			#clock-cells = <0>;
@@ -70,75 +77,6 @@
 		};
 	};
 
-	tempmon: tempmon {
-		compatible = "fsl,imx6q-tempmon";
-		interrupt-parent = <&gpc>;
-		interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
-		fsl,tempmon = <&anatop>;
-		fsl,tempmon-data = <&ocotp>;
-		clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
-	};
-
-	ldb: ldb {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
-		gpr = <&gpr>;
-		status = "disabled";
-
-		lvds-channel@0 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0>;
-			status = "disabled";
-
-			port@0 {
-				reg = <0>;
-
-				lvds0_mux_0: endpoint {
-					remote-endpoint = <&ipu1_di0_lvds0>;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-
-				lvds0_mux_1: endpoint {
-					remote-endpoint = <&ipu1_di1_lvds0>;
-				};
-			};
-		};
-
-		lvds-channel@1 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <1>;
-			status = "disabled";
-
-			port@0 {
-				reg = <0>;
-
-				lvds1_mux_0: endpoint {
-					remote-endpoint = <&ipu1_di0_lvds1>;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-
-				lvds1_mux_1: endpoint {
-					remote-endpoint = <&ipu1_di1_lvds1>;
-				};
-			};
-		};
-	};
-
-	pmu: pmu {
-		compatible = "arm,cortex-a9-pmu";
-		interrupt-parent = <&gpc>;
-		interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
-	};
-
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -146,6 +84,11 @@
 		interrupt-parent = <&gpc>;
 		ranges;
 
+		caam_sm: caam-sm@100000 {
+			compatible = "fsl,imx6q-caam-sm";
+			reg = <0x100000 0x4000>;
+		};
+
 		dma_apbh: dma-apbh@110000 {
 			compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
 			reg = <0x00110000 0x2000>;
@@ -159,7 +102,17 @@
 			clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
 		};
 
-		gpmi: gpmi-nand@112000 {
+		irq_sec_vio: caam_secvio {
+			compatible = "fsl,imx6q-caam-secvio";
+			interrupts = <0 20 0x04>;
+			secvio_src = <0x8000001d>;
+			jtag-tamper = "disabled";
+			watchdog-tamper = "enabled";
+			internal-boot-tamper = "enabled";
+			external-pin-tamper = "disabled";
+		};
+
+		gpmi: nand-controller@112000 {
 			compatible = "fsl,imx6q-gpmi-nand";
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -228,6 +181,18 @@
 			power-domains = <&pd_pu>;
 		};
 
+		ocrams: sram@00900000 {
+			compatible = "fsl,lpm-sram";
+			reg = <0x00900000 0x4000>;
+			clocks = <&clks IMX6QDL_CLK_OCRAM>;
+		};
+
+		ocrams_ddr: sram@00904000 {
+			compatible = "fsl,ddr-lpm-sram";
+			reg = <0x00904000 0x1000>;
+			clocks = <&clks IMX6QDL_CLK_OCRAM>;
+		};
+
 		timer@a00600 {
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0x00a00600 0x20>;
@@ -245,7 +210,7 @@
 			interrupt-parent = <&intc>;
 		};
 
-		L2: l2-cache@a02000 {
+		L2: cache-controller@a02000 {
 			compatible = "arm,pl310-cache";
 			reg = <0x00a02000 0x1000>;
 			interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -280,6 +245,52 @@
 				 <&clks IMX6QDL_CLK_LVDS1_GATE>,
 				 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
 			clock-names = "pcie", "pcie_bus", "pcie_phy";
+			fsl,max-link-speed = <2>;
+			gpr = <&gpr>;
+			status = "disabled";
+		};
+
+		pmu {
+			compatible = "arm,cortex-a9-pmu";
+			interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		hdmi_core: hdmi_core@00120000 {
+			compatible = "fsl,imx6q-hdmi-core";
+			reg = <0x00120000 0x9000>;
+			clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
+					<&clks IMX6QDL_CLK_HDMI_IAHB>,
+					<&clks IMX6QDL_CLK_HSI_TX>;
+			clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
+			status = "disabled";
+		};
+
+		hdmi_video: hdmi_video@020e0000 {
+			compatible = "fsl,imx6q-hdmi-video";
+			reg = <0x020e0000 0x1000>;
+			reg-names = "hdmi_gpr";
+			interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
+					<&clks IMX6QDL_CLK_HDMI_IAHB>,
+					<&clks IMX6QDL_CLK_HSI_TX>;
+			clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
+			status = "disabled";
+		};
+
+		hdmi_audio: hdmi_audio@00120000 {
+			compatible = "fsl,imx6q-hdmi-audio";
+			clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
+					<&clks IMX6QDL_CLK_HDMI_IAHB>,
+					<&clks IMX6QDL_CLK_HSI_TX>;
+			clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
+			dmas = <&sdma 2 25 0>;
+			dma-names = "tx";
+			status = "disabled";
+		};
+
+		hdmi_cec: hdmi_cec@00120000 {
+			compatible = "fsl,imx6q-hdmi-cec";
+			interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};
 
@@ -307,7 +318,7 @@
 					clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
 						 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
 						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
-						 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
+						 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>,
 						 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
 					clock-names = "core",  "rxtx0",
 						      "rxtx1", "rxtx2",
@@ -326,7 +337,7 @@
 					clocks = <&clks IMX6QDL_CLK_ECSPI1>,
 						 <&clks IMX6QDL_CLK_ECSPI1>;
 					clock-names = "ipg", "per";
-					dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
+					dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
 					dma-names = "rx", "tx";
 					status = "disabled";
 				};
@@ -340,7 +351,7 @@
 					clocks = <&clks IMX6QDL_CLK_ECSPI2>,
 						 <&clks IMX6QDL_CLK_ECSPI2>;
 					clock-names = "ipg", "per";
-					dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
+					dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
 					dma-names = "rx", "tx";
 					status = "disabled";
 				};
@@ -354,7 +365,7 @@
 					clocks = <&clks IMX6QDL_CLK_ECSPI3>,
 						 <&clks IMX6QDL_CLK_ECSPI3>;
 					clock-names = "ipg", "per";
-					dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
+					dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
 					dma-names = "rx", "tx";
 					status = "disabled";
 				};
@@ -368,7 +379,7 @@
 					clocks = <&clks IMX6QDL_CLK_ECSPI4>,
 						 <&clks IMX6QDL_CLK_ECSPI4>;
 					clock-names = "ipg", "per";
-					dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
+					dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
 					dma-names = "rx", "tx";
 					status = "disabled";
 				};
@@ -491,6 +502,24 @@
 				power-domains = <&pd_pu>;
 				resets = <&src 1>;
 				iram = <&ocram>;
+				status = "disabled";
+			};
+
+			vpu_fsl: vpu_fsl@2040000 {
+				compatible = "fsl,imx6-vpu";
+				reg = <0x2040000 0x3c000>;
+				reg-names = "vpu_regs";
+				interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
+						<0 12 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq";
+				clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
+					 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
+					 <&clks IMX6QDL_CLK_OCRAM>;
+				clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram";
+				iramsize = <0x21000>;
+				iram = <&ocram>;
+				resets = <&src 1>;
+				power-domains = <&pd_pu>;
 			};
 
 			aipstz@207c000 { /* AIPSTZ1 */
@@ -548,6 +577,7 @@
 				clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
 					 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
 				clock-names = "ipg", "per";
+				fsl,stop-mode = <&gpr 0x34 28 0x10 17>;
 				status = "disabled";
 			};
 
@@ -558,10 +588,11 @@
 				clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
 					 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
 				clock-names = "ipg", "per";
+				fsl,stop-mode = <&gpr 0x34 29 0x10 18>;
 				status = "disabled";
 			};
 
-			gpt: gpt@2098000 {
+			gpt: timer@2098000 {
 				compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
 				reg = <0x02098000 0x4000>;
 				interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
@@ -648,7 +679,7 @@
 				#interrupt-cells = <2>;
 			};
 
-			kpp: kpp@20b8000 {
+			kpp: keypad@20b8000 {
 				compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
 				reg = <0x020b8000 0x4000>;
 				interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
@@ -656,22 +687,22 @@
 				status = "disabled";
 			};
 
-			wdog1: wdog@20bc000 {
+			wdog1: watchdog@20bc000 {
 				compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 				reg = <0x020bc000 0x4000>;
 				interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX6QDL_CLK_DUMMY>;
+				clocks = <&clks IMX6QDL_CLK_IPG>;
 			};
 
-			wdog2: wdog@20c0000 {
+			wdog2: watchdog@20c0000 {
 				compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
 				reg = <0x020c0000 0x4000>;
 				interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX6QDL_CLK_DUMMY>;
+				clocks = <&clks IMX6QDL_CLK_IPG>;
 				status = "disabled";
 			};
 
-			clks: ccm@20c4000 {
+			clks: clock-controller@20c4000 {
 				compatible = "fsl,imx6q-ccm";
 				reg = <0x020c4000 0x4000>;
 				interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
@@ -704,9 +735,8 @@
 				reg_vdd3p0: regulator-3p0 {
 					compatible = "fsl,anatop-regulator";
 					regulator-name = "vdd3p0";
-					regulator-min-microvolt = <2800000>;
-					regulator-max-microvolt = <3150000>;
-					regulator-always-on;
+					regulator-min-microvolt = <2625000>;
+					regulator-max-microvolt = <3400000>;
 					anatop-reg-offset = <0x120>;
 					anatop-vol-bit-shift = <8>;
 					anatop-vol-bit-width = <5>;
@@ -746,6 +776,7 @@
 					anatop-min-bit-val = <1>;
 					anatop-min-voltage = <725000>;
 					anatop-max-voltage = <1450000>;
+					regulator-allow-bypass;
 				};
 
 				reg_pu: regulator-vddpu {
@@ -763,6 +794,7 @@
 					anatop-min-bit-val = <1>;
 					anatop-min-voltage = <725000>;
 					anatop-max-voltage = <1450000>;
+					regulator-allow-bypass;
 				};
 
 				reg_soc: regulator-vddsoc {
@@ -780,14 +812,24 @@
 					anatop-min-bit-val = <1>;
 					anatop-min-voltage = <725000>;
 					anatop-max-voltage = <1450000>;
+					regulator-allow-bypass;
 				};
 			};
 
+			tempmon: tempmon {
+				compatible = "fsl,imx6q-tempmon";
+				interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
+				fsl,tempmon = <&anatop>;
+				fsl,tempmon-data = <&ocotp>;
+				clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+			};
+
 			usbphy1: usbphy@20c9000 {
 				compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
 				reg = <0x020c9000 0x1000>;
 				interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6QDL_CLK_USBPHY1>;
+				phy-3p0-supply = <&reg_vdd3p0>;
 				fsl,anatop = <&anatop>;
 			};
 
@@ -796,9 +838,27 @@
 				reg = <0x020ca000 0x1000>;
 				interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6QDL_CLK_USBPHY2>;
+				phy-3p0-supply = <&reg_vdd3p0>;
 				fsl,anatop = <&anatop>;
 			};
 
+			usbphy_nop1: usbphy_nop1 {
+				compatible = "usb-nop-xceiv";
+				clocks = <&clks IMX6QDL_CLK_USBPHY1>;
+				clock-names = "main_clk";
+			};
+
+			usbphy_nop2: usbphy_nop2 {
+				compatible = "usb-nop-xceiv";
+				clocks = <&clks IMX6QDL_CLK_USBPHY1>;
+				clock-names = "main_clk";
+			};
+
+			caam_snvs: caam-snvs@20cc000 {
+				compatible = "fsl,imx6q-caam-snvs";
+				reg = <0x20cc000 0x4000>;
+			};
+
 			snvs: snvs@20cc000 {
 				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 				reg = <0x020cc000 0x4000>;
@@ -819,10 +879,6 @@
 					mask = <0x60>;
 					status = "disabled";
 				};
-
-				snvs_lpgpr: snvs-lpgpr {
-					compatible = "fsl,imx6q-snvs-lpgpr";
-				};
 			};
 
 			epit1: epit@20d0000 { /* EPIT1 */
@@ -835,7 +891,7 @@
 				interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
-			src: src@20d8000 {
+			src: reset-controller@20d8000 {
 				compatible = "fsl,imx6q-src", "fsl,imx51-src";
 				reg = <0x020d8000 0x4000>;
 				interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
@@ -848,8 +904,7 @@
 				reg = <0x020dc000 0x4000>;
 				interrupt-controller;
 				#interrupt-cells = <3>;
-				interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
-					     <0 90 IRQ_TYPE_LEVEL_HIGH>;
+				interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-parent = <&intc>;
 				clocks = <&clks IMX6QDL_CLK_IPG>;
 				clock-names = "ipg";
@@ -886,26 +941,90 @@
 				};
 			};
 
-			iomuxc: iomuxc@20e0000 {
+			iomuxc: pinctrl@20e0000 {
 				compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
 				reg = <0x20e0000 0x4000>;
 			};
 
+			ldb: ldb {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
+				gpr = <&gpr>;
+				status = "disabled";
+
+				lvds-channel@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+					status = "disabled";
+
+					port@0 {
+						reg = <0>;
+
+						lvds0_mux_0: endpoint {
+							remote-endpoint = <&ipu1_di0_lvds0>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						lvds0_mux_1: endpoint {
+							remote-endpoint = <&ipu1_di1_lvds0>;
+						};
+					};
+				};
+
+				lvds-channel@1 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <1>;
+					status = "disabled";
+
+					port@0 {
+						reg = <0>;
+
+						lvds1_mux_0: endpoint {
+							remote-endpoint = <&ipu1_di0_lvds1>;
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						lvds1_mux_1: endpoint {
+							remote-endpoint = <&ipu1_di1_lvds1>;
+						};
+					};
+				};
+			};
+
 			dcic1: dcic@20e4000 {
-				reg = <0x020e4000 0x4000>;
+				compatible = "fsl,imx6q-dcic";
+				reg = <0x20e4000 0x4000>;
 				interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6QDL_CLK_DCIC1>, <&clks IMX6QDL_CLK_DCIC1>;
+				clock-names = "dcic", "disp-axi";
+				gpr = <&gpr>;
+				status = "disabled";
 			};
 
 			dcic2: dcic@20e8000 {
-				reg = <0x020e8000 0x4000>;
+				compatible = "fsl,imx6q-dcic";
+				reg = <0x20e8000 0x4000>;
 				interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6QDL_CLK_DCIC2>, <&clks IMX6QDL_CLK_DCIC2>;
+				clock-names = "dcic", "disp-axi";
+				gpr = <&gpr>;
+				status = "disabled";
 			};
 
 			sdma: sdma@20ec000 {
 				compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 				reg = <0x020ec000 0x4000>;
 				interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX6QDL_CLK_SDMA>,
+				clocks = <&clks IMX6QDL_CLK_IPG>,
 					 <&clks IMX6QDL_CLK_SDMA>;
 				clock-names = "ipg", "ahb";
 				#dma-cells = <3>;
@@ -920,25 +1039,35 @@
 			reg = <0x02100000 0x100000>;
 			ranges;
 
-			crypto: caam@2100000 {
+			crypto: crypto@2100000 {
 				compatible = "fsl,sec-v4.0";
 				#address-cells = <1>;
 				#size-cells = <1>;
 				reg = <0x2100000 0x10000>;
-				ranges = <0 0x2100000 0x10000>;
+				ranges = <0 0x2100000 0x40000>;
+				interrupt-parent = <&intc>; /* interrupts = <0 92 0x4>; */
 				clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
 					 <&clks IMX6QDL_CLK_CAAM_ACLK>,
 					 <&clks IMX6QDL_CLK_CAAM_IPG>,
 					 <&clks IMX6QDL_CLK_EIM_SLOW>;
 				clock-names = "mem", "aclk", "ipg", "emi_slow";
 
-				sec_jr0: jr0@1000 {
+				sec_ctrl: ctrl@0 {
+					/* CAAM Page 0 only accessible */
+					/*	by secure world */
+					compatible = "fsl,sec-v4.0-ctrl";
+					reg = <0x2100000 0x1000>;
+					secure-status = "okay";
+					status = "disabled";
+				};
+
+				sec_jr0: jr@1000 {
 					compatible = "fsl,sec-v4.0-job-ring";
 					reg = <0x1000 0x1000>;
 					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 				};
 
-				sec_jr1: jr1@2000 {
+				sec_jr1: jr@2000 {
 					compatible = "fsl,sec-v4.0-job-ring";
 					reg = <0x2000 0x1000>;
 					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
@@ -949,7 +1078,14 @@
 				reg = <0x0217c000 0x4000>;
 			};
 
-			usbotg: usb@2184000 {
+			usbg1: usbg1 {
+				compatible = "fsl,imx27-usb-gadget";
+				dr_mode = "peripheral";
+				chipidea,usb = <&usbotg>;
+				status = "okay";
+			};
+
+			usbotg: usb@02184000 {
 				compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
 				reg = <0x02184000 0x200>;
 				interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
@@ -959,6 +1095,7 @@
 				ahb-burst-config = <0x0>;
 				tx-burst-size-dword = <0x10>;
 				rx-burst-size-dword = <0x10>;
+				fsl,anatop = <&anatop>;
 				status = "disabled";
 			};
 
@@ -986,6 +1123,9 @@
 				ahb-burst-config = <0x0>;
 				tx-burst-size-dword = <0x10>;
 				rx-burst-size-dword = <0x10>;
+				phy_type = "hsic";
+				fsl,usbphy = <&usbphy_nop1>;
+				fsl,anatop = <&anatop>;
 				status = "disabled";
 			};
 
@@ -999,6 +1139,9 @@
 				ahb-burst-config = <0x0>;
 				tx-burst-size-dword = <0x10>;
 				rx-burst-size-dword = <0x10>;
+				phy_type = "hsic";
+				fsl,usbphy = <&usbphy_nop2>;
+				fsl,anatop = <&anatop>;
 				status = "disabled";
 			};
 
@@ -1012,25 +1155,31 @@
 			fec: ethernet@2188000 {
 				compatible = "fsl,imx6q-fec";
 				reg = <0x02188000 0x4000>;
-				interrupt-names = "int0", "pps";
 				interrupts-extended =
-					<&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
-					<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+					<&gpc 0 118 IRQ_TYPE_LEVEL_HIGH>,
+					<&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6QDL_CLK_ENET>,
 					 <&clks IMX6QDL_CLK_ENET>,
 					 <&clks IMX6QDL_CLK_ENET_REF>;
 				clock-names = "ipg", "ahb", "ptp";
+				stop-mode = <&gpr 0x34 27>;
+				fsl,wakeup_irq = <0>;
 				status = "disabled";
 			};
 
-			mlb@218c000 {
+			mlb: mlb@218c000 {
+				compatible = "fsl,imx6q-mlb150";
 				reg = <0x0218c000 0x4000>;
 				interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
 					     <0 117 IRQ_TYPE_LEVEL_HIGH>,
 					     <0 126 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6QDL_CLK_MLB>;
+				clock-names = "mlb";
+				iram = <&ocram>;
+				status = "disabled";
 			};
 
-			usdhc1: usdhc@2190000 {
+			usdhc1: mmc@2190000 {
 				compatible = "fsl,imx6q-usdhc";
 				reg = <0x02190000 0x4000>;
 				interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
@@ -1042,7 +1191,7 @@
 				status = "disabled";
 			};
 
-			usdhc2: usdhc@2194000 {
+			usdhc2: mmc@2194000 {
 				compatible = "fsl,imx6q-usdhc";
 				reg = <0x02194000 0x4000>;
 				interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
@@ -1054,7 +1203,7 @@
 				status = "disabled";
 			};
 
-			usdhc3: usdhc@2198000 {
+			usdhc3: mmc@2198000 {
 				compatible = "fsl,imx6q-usdhc";
 				reg = <0x02198000 0x4000>;
 				interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
@@ -1066,7 +1215,7 @@
 				status = "disabled";
 			};
 
-			usdhc4: usdhc@219c000 {
+			usdhc4: mmc@219c000 {
 				compatible = "fsl,imx6q-usdhc";
 				reg = <0x0219c000 0x4000>;
 				interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
@@ -1112,13 +1261,20 @@
 				reg = <0x021ac000 0x4000>;
 			};
 
-			mmdc0: mmdc@21b0000 { /* MMDC0 */
+			mmdc0-1@021b0000 { /* MMDC0-1 */
+				compatible = "fsl,imx6q-mmdc-combine";
+				reg = <0x021b0000 0x8000>;
+			};
+
+			mmdc0: memory-controller@21b0000 { /* MMDC0 */
 				compatible = "fsl,imx6q-mmdc";
 				reg = <0x021b0000 0x4000>;
 			};
 
-			mmdc1: mmdc@21b4000 { /* MMDC1 */
+			mmdc1: memory-controller@21b4000 { /* MMDC1 */
+				compatible = "fsl,imx6q-mmdc";
 				reg = <0x021b4000 0x4000>;
+				status = "disabled";
 			};
 
 			weim: weim@21b8000 {
@@ -1132,7 +1288,7 @@
 				status = "disabled";
 			};
 
-			ocotp: ocotp@21bc000 {
+			ocotp: efuse@21bc000 {
 				compatible = "fsl,imx6q-ocotp", "syscon";
 				reg = <0x021bc000 0x4000>;
 				clocks = <&clks IMX6QDL_CLK_IIM>;
@@ -1155,15 +1311,15 @@
 			};
 
 			mipi_csi: mipi@21dc000 {
-				compatible = "fsl,imx6-mipi-csi2";
+				compatible = "fsl,imx6q-mipi-csi2";
 				reg = <0x021dc000 0x4000>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 				interrupts = <0 100 0x04>, <0 101 0x04>;
 				clocks = <&clks IMX6QDL_CLK_HSI_TX>,
 					 <&clks IMX6QDL_CLK_VIDEO_27M>,
-					 <&clks IMX6QDL_CLK_EIM_PODF>;
-				clock-names = "dphy", "ref", "pix";
+					 <&clks IMX6QDL_CLK_EIM_SEL>;
+				clock-names = "dphy_clk", "cfg_clk", "pixel_clk";
 				status = "disabled";
 			};
 
@@ -1198,6 +1354,7 @@
 				reg = <0x021e4000 0x4000>;
 				interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6QDL_CLK_VDOA>;
+				iram = <&ocram>;
 			};
 
 			uart2: serial@21e8000 {
@@ -1257,10 +1414,15 @@
 			interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
 				     <0 5 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clks IMX6QDL_CLK_IPU1>,
-				 <&clks IMX6QDL_CLK_IPU1_DI0>,
-				 <&clks IMX6QDL_CLK_IPU1_DI1>;
-			clock-names = "bus", "di0", "di1";
+				 <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>,
+				 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
+				 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
+			clock-names = "bus",
+				      "di0", "di1",
+				      "di0_sel", "di1_sel",
+				      "ldb_di0", "ldb_di1";
 			resets = <&src 2>;
+			bypass_reset = <0>;
 
 			ipu1_csi0: port@0 {
 				reg = <0>;
diff --git a/arch/arm/dts/imx6qp-sabreauto-ecspi.dts b/arch/arm/dts/imx6qp-sabreauto-ecspi.dts
new file mode 100644
index 00000000000..8846739a555
--- /dev/null
+++ b/arch/arm/dts/imx6qp-sabreauto-ecspi.dts
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6qp-sabreauto.dts"
+
+&ecspi1 {
+	pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&can2 {
+	/* max7310_c on i2c3 is gone */
+	status = "disabled";
+};
+
+&i2c3 {
+	/* pin conflict with ecspi1 */
+	status = "disabled";
+};
+
+&uart3 {
+	/* the uart3 depends on the i2c3, so disable it too. */
+	status = "disabled";
+};
+
+&usbh1 {
+	/* max7310_b on i2c3 is gone */
+	status = "disabled";
+};
+
+&usbotg {
+	/* max7310_c on i2c3 is gone */
+	status = "okay";
+	dr_mode = "peripheral";
+};
diff --git a/arch/arm/dts/imx6qp-sabreauto-gpmi-weim.dts b/arch/arm/dts/imx6qp-sabreauto-gpmi-weim.dts
new file mode 100644
index 00000000000..b91ebad6111
--- /dev/null
+++ b/arch/arm/dts/imx6qp-sabreauto-gpmi-weim.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6qp-sabreauto.dts"
+
+&ecspi1 {
+	/* pin conflict with weim */
+	status = "disabled";
+};
+
+&can2 {
+	/* max7310_c on i2c3 is gone */
+	status = "disabled";
+};
+
+&gpmi {
+	compatible = "fsl,imx6qp-gpmi-nand";
+	status = "okay";
+};
+
+&i2c3 {
+	/* pin conflict with weim */
+	status = "disabled";
+};
+
+&uart3 {
+	/* pin conflict with gpmi and weim */
+	status = "disabled";
+};
+
+&usbh1 {
+	/* max7310_b on i2c3 is gone */
+	status = "disabled";
+};
+
+&usbotg {
+	/* max7310_c on i2c3 is gone */
+	status = "okay";
+	dr_mode = "peripheral";
+};
+
+&weim {
+	pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6qp-sabreauto.dts b/arch/arm/dts/imx6qp-sabreauto.dts
index d4caeeb0af7..46560263bd9 100644
--- a/arch/arm/dts/imx6qp-sabreauto.dts
+++ b/arch/arm/dts/imx6qp-sabreauto.dts
@@ -8,10 +8,44 @@
 #include "imx6qdl-sabreauto.dtsi"
 
 / {
-	model = "Freescale i.MX6 Quad Plus SABRE Automotive Board";
+	model = "i.MX6 Quad Plus SABRE Automotive Board";
 	compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
 };
 
+&ldb {
+	lvds-channel@0 {
+		crtc = "ipu2-di0";
+	};
+
+	lvds-channel@1 {
+		crtc = "ipu2-di1";
+	};
+};
+
+&mxcfb1 {
+	prefetch;
+	status = "okay";
+};
+
+&mxcfb2 {
+	prefetch;
+	status = "okay";
+};
+
+&mxcfb3 {
+	prefetch;
+	status = "okay";
+};
+
+&mxcfb4 {
+	prefetch;
+	status = "okay";
+};
+
+&fec {
+	pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>;
+};
+
 &i2c2 {
 	max7322: gpio@68 {
 		compatible = "maxim,max7322";
@@ -21,33 +55,47 @@
 	};
 };
 
-&iomuxc {
-	imx6qdl-sabreauto {
-		pinctrl_enet: enetgrp {
-			fsl,pins = <
-				MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
-				MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
-				MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b018
-				MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b018
-				MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b018
-				MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b018
-				MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b018
-				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b018
-				MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b018
-				MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b018
-				MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b018
-				MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b018
-				MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b018
-				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b018
-				MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
-				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
-			>;
-		};
-	};
+&pcie {
+	reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
+	status = "okay";
 };
 
-&pcie {
-	status = "disabled";
+&pre1 {
+	status = "okay";
+};
+
+&pre2 {
+	status = "okay";
+};
+
+&pre3 {
+	status = "okay";
+};
+
+&pre4 {
+	status = "okay";
+};
+
+&prg1 {
+	memory-region = <&memory>;
+	status = "okay";
+};
+
+&prg2 {
+	memory-region = <&memory>;
+	status = "okay";
+};
+
+&reg_sd3_vmmc {
+	status = "okay";
+};
+
+&sata {
+	status = "okay";
+};
+
+&usdhc3 {
+	vmmc-supply = <&reg_sd3_vmmc>;
 };
 
 &vgen3_reg {
diff --git a/arch/arm/dts/imx6qp-sabresd.dts b/arch/arm/dts/imx6qp-sabresd.dts
index f1b9cb104fd..c131bbd9050 100644
--- a/arch/arm/dts/imx6qp-sabresd.dts
+++ b/arch/arm/dts/imx6qp-sabresd.dts
@@ -8,7 +8,7 @@
 #include "imx6qdl-sabresd.dtsi"
 
 / {
-	model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board";
+	model = "i.MX6 Quad Plus SABRE Smart Device Board";
 	compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
 };
 
@@ -50,6 +50,112 @@
 	};
 };
 
+&iomuxc {
+	imx6qdl-sabresd {
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
+				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10071
+				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
+				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
+				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
+				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
+				MX6QDL_PAD_NANDF_D4__SD2_DATA4		0x17059
+				MX6QDL_PAD_NANDF_D5__SD2_DATA5		0x17059
+				MX6QDL_PAD_NANDF_D6__SD2_DATA6		0x17059
+				MX6QDL_PAD_NANDF_D7__SD2_DATA7		0x17059
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
+				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10071
+				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
+				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
+				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
+				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
+				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
+				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
+				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
+				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
+			>;
+		};
+	};
+};
+
+&ldb {
+	lvds-channel@0 {
+		crtc = "ipu2-di0";
+	};
+
+	lvds-channel@1 {
+		crtc = "ipu2-di1";
+	};
+};
+
+&mxcfb1 {
+	prefetch;
+	status = "okay";
+};
+
+&mxcfb2 {
+	prefetch;
+	status = "okay";
+};
+
+&mxcfb3 {
+	prefetch;
+	status = "okay";
+};
+
+&mxcfb4 {
+	prefetch;
+	status = "okay";
+};
+
+&ov564x {
+	AVDD-supply = <&vgen6_reg>; /* 2.8v */
+	DOVDD-supply = <&sw4_reg>; /* 1.8v */
+};
+
+&ov564x_mipi {
+	AVDD-supply = <&vgen6_reg>; /* 2.8v */
+	DOVDD-supply = <&sw4_reg>; /* 1.8v */
+};
+
 &pcie {
-	status = "disabled";
+	pcie-bus-supply = <&vgen3_reg>; /* 1.8v pwr up pcie ext osc on revb */
+	reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&pre1 {
+	status = "okay";
+};
+
+&pre2 {
+	status = "okay";
+};
+
+&pre3 {
+	status = "okay";
+};
+
+&pre4 {
+	status = "okay";
+};
+
+&prg1 {
+	memory-region = <&memory>;
+	status = "okay";
+};
+
+&prg2 {
+	memory-region = <&memory>;
+	status = "okay";
+};
+
+&sata {
+	status = "okay";
 };
diff --git a/arch/arm/dts/imx6qp.dtsi b/arch/arm/dts/imx6qp.dtsi
index 93b89dc1f53..ada0c318f6f 100644
--- a/arch/arm/dts/imx6qp.dtsi
+++ b/arch/arm/dts/imx6qp.dtsi
@@ -5,6 +5,15 @@
 #include "imx6q.dtsi"
 
 / {
+	aliases {
+		pre0 = &pre1;
+		pre1 = &pre2;
+		pre2 = &pre3;
+		pre3 = &pre4;
+		prg0 = &prg1;
+		prg1 = &prg2;
+	};
+
 	soc {
 		ocram2: sram@940000 {
 			compatible = "mmio-sram";
@@ -18,59 +27,87 @@
 			clocks = <&clks IMX6QDL_CLK_OCRAM>;
 		};
 
-		bus@2100000 {
+		pcie: pcie@1ffc000 {
+			compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
+			reg = <0x01ffc000 0x4000>, <0x01f00000 0x80000>;
+			reg-names = "dbi", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			bus-range = <0x00 0xff>;
+			ranges = <0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
+				  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
+			num-lanes = <1>;
+			interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 123 IRQ_TYPE_LEVEL_HIGH>,
+			                <0 0 0 2 &intc 0 122 IRQ_TYPE_LEVEL_HIGH>,
+			                <0 0 0 3 &intc 0 121 IRQ_TYPE_LEVEL_HIGH>,
+			                <0 0 0 4 &intc 0 120 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks IMX6QDL_CLK_PCIE_REF_125M>, <&clks IMX6QDL_PLL6_BYPASS>,
+				 <&clks IMX6QDL_PLL6_BYPASS_SRC>,
+				 <&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks IMX6QDL_CLK_PCIE_AXI>;
+			clock-names = "pcie_phy", "pcie_ext", "pcie_ext_src", "pcie_bus", "pcie";
+			status = "disabled";
+		};
+
+		bus@2100000 { /* AIPS2 */
 			pre1: pre@21c8000 {
-				compatible = "fsl,imx6qp-pre";
+				compatible = "fsl,imx6q-pre";
 				reg = <0x021c8000 0x1000>;
-				interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
 				clocks = <&clks IMX6QDL_CLK_PRE0>;
-				clock-names = "axi";
-				fsl,iram = <&ocram2>;
+				interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
+				ocram = <&ocram2>;
+				status = "disabled";
 			};
 
 			pre2: pre@21c9000 {
-				compatible = "fsl,imx6qp-pre";
+				compatible = "fsl,imx6q-pre";
 				reg = <0x021c9000 0x1000>;
-				interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
 				clocks = <&clks IMX6QDL_CLK_PRE1>;
-				clock-names = "axi";
-				fsl,iram = <&ocram2>;
+				interrupts = <0 97 IRQ_TYPE_EDGE_RISING>;
+				ocram = <&ocram2>;
+				status = "disabled";
 			};
 
 			pre3: pre@21ca000 {
-				compatible = "fsl,imx6qp-pre";
+				compatible = "fsl,imx6q-pre";
 				reg = <0x021ca000 0x1000>;
-				interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;
 				clocks = <&clks IMX6QDL_CLK_PRE2>;
-				clock-names = "axi";
-				fsl,iram = <&ocram3>;
+				interrupts = <0 98 IRQ_TYPE_EDGE_RISING>;
+				ocram = <&ocram3>;
+				status = "disabled";
 			};
 
 			pre4: pre@21cb000 {
-				compatible = "fsl,imx6qp-pre";
+				compatible = "fsl,imx6q-pre";
 				reg = <0x021cb000 0x1000>;
-				interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
 				clocks = <&clks IMX6QDL_CLK_PRE3>;
-				clock-names = "axi";
-				fsl,iram = <&ocram3>;
+				interrupts = <0 99 IRQ_TYPE_EDGE_RISING>;
+				ocram = <&ocram3>;
+				status = "disabled";
 			};
 
 			prg1: prg@21cc000 {
-				compatible = "fsl,imx6qp-prg";
+				compatible = "fsl,imx6q-prg";
 				reg = <0x021cc000 0x1000>;
-				clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
-					 <&clks IMX6QDL_CLK_PRG0_AXI>;
-				clock-names = "ipg", "axi";
-				fsl,pres = <&pre1>, <&pre2>, <&pre3>;
+				clocks = <&clks IMX6QDL_CLK_PRG0_AXI>,
+					 <&clks IMX6QDL_CLK_PRG0_APB>;
+				clock-names = "axi", "apb";
+				gpr = <&gpr>;
+				status = "disabled";
 			};
 
 			prg2: prg@21cd000 {
-				compatible = "fsl,imx6qp-prg";
+				compatible = "fsl,imx6q-prg";
 				reg = <0x021cd000 0x1000>;
-				clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
-					 <&clks IMX6QDL_CLK_PRG1_AXI>;
-				clock-names = "ipg", "axi";
-				fsl,pres = <&pre4>, <&pre2>, <&pre3>;
+				clocks = <&clks IMX6QDL_CLK_PRG1_AXI>,
+					 <&clks IMX6QDL_CLK_PRG1_APB>;
+				clock-names = "axi", "apb";
+				gpr = <&gpr>;
+				status = "disabled";
 			};
 		};
 	};
@@ -88,22 +125,34 @@
 
 &ipu1 {
 	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
+	clocks = <&clks IMX6QDL_CLK_IPU1>,
+		 <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>,
+		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
+		 <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>,
+		 <&clks IMX6QDL_CLK_PRG0_APB>;
+	clock-names = "bus",
+		      "di0", "di1",
+		      "di0_sel", "di1_sel",
+		      "ldb_di0", "ldb_di1", "prg";
 	fsl,prg = <&prg1>;
 };
 
 &ipu2 {
 	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
+	clocks = <&clks IMX6QDL_CLK_IPU2>,
+		 <&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>,
+		 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
+		 <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>,
+		 <&clks IMX6QDL_CLK_PRG1_APB>;
+	clock-names = "bus",
+		      "di0", "di1",
+		      "di0_sel", "di1_sel",
+		      "ldb_di0", "ldb_di1", "prg";
 	fsl,prg = <&prg2>;
 };
 
 &ldb {
-	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
-		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
-		 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
-		 <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;
-	clock-names = "di0_pll", "di1_pll",
-		      "di0_sel", "di1_sel", "di2_sel", "di3_sel",
-		      "di0", "di1";
+	compatible = "fsl,imx6qp-ldb", "fsl,imx6q-ldb", "fsl,imx53-ldb";
 };
 
 &mmdc0 {
diff --git a/arch/arm/dts/imx6sl-evk.dts b/arch/arm/dts/imx6sl-evk.dts
index 0a90eea1701..893e6791ae5 100644
--- a/arch/arm/dts/imx6sl-evk.dts
+++ b/arch/arm/dts/imx6sl-evk.dts
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -13,9 +14,26 @@
 #include "imx6sl.dtsi"
 
 / {
-	model = "Freescale i.MX6 SoloLite EVK Board";
+	model = "i.MX6 SoloLite EVK Board";
 	compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
 
+	battery: max8903@0 {
+		compatible = "fsl,max8903-charger";
+		pinctrl-names = "default";
+		dok_input = <&gpio4 13 1>;
+		uok_input = <&gpio4 13 1>;
+		chg_input = <&gpio4 15 1>;
+		flt_input = <&gpio4 14 1>;
+		fsl,dcm_always_high;
+		fsl,dc_valid;
+		fsl,adc_disable;
+		status = "okay";
+	};
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
 	memory {
 		reg = <0x80000000 0x40000000>;
 	};
@@ -39,6 +57,11 @@
 		};
 	};
 
+	pxp_v4l2_out {
+		compatible = "fsl,imx6sl-pxp-v4l2";
+		status = "okay";
+	};
+
 	regulators {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -96,7 +119,7 @@
 	sound {
 		compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
 		model = "wm8962-audio";
-		ssi-controller = <&ssi2>;
+		cpu-dai = <&ssi2>;
 		audio-codec = <&codec>;
 		audio-routing =
 			"Headphone Jack", "HPOUTL",
@@ -107,6 +130,23 @@
 			"IN3R", "AMIC";
 		mux-int-port = <2>;
 		mux-ext-port = <3>;
+		codec-master;
+		hp-det-gpios = <&gpio4 19 1>;
+	};
+
+	sound-spdif {
+		compatible = "fsl,imx-audio-spdif",
+			   "fsl,imx6sl-evk-spdif";
+		model = "imx-spdif";
+		spdif-controller = <&spdif>;
+		spdif-out;
+	};
+
+	sii902x_reset: sii902x-reset {
+		compatible = "gpio-reset";
+		reset-gpios = <&gpio2 19 1>;
+		reset-delay-us = <100000>;
+		#reset-cells = <0>;
 	};
 };
 
@@ -116,6 +156,29 @@
 	status = "okay";
 };
 
+&reg_arm {
+	vin-supply = <&sw1a_reg>;
+	regulator-allow-bypass;
+};
+
+&reg_soc {
+	vin-supply = <&sw1c_reg>;
+	regulator-allow-bypass;
+};
+
+&reg_pu {
+	vin-supply = <&sw1c_reg>;
+	regulator-allow-bypass;
+};
+
+&csi {
+	port {
+		csi_ep: endpoint {
+			remote-endpoint = <&ov5640_ep>;
+		};
+	};
+};
+
 &ecspi1 {
 	cs-gpios = <&gpio4 11 0>;
 	pinctrl-names = "default";
@@ -131,6 +194,15 @@
 	};
 };
 
+&epdc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_epdc_0>;
+        V3P3-supply = <&V3P3_reg>;
+        VCOM-supply = <&VCOM_reg>;
+        DISPLAY-supply = <&DISPLAY_reg>;
+        status = "okay";
+};
+
 &fec {
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&pinctrl_fec>;
@@ -139,13 +211,20 @@
 	status = "okay";
 };
 
+&gpc {
+	 fsl,ldo-bypass = <1>;
+};
+
 &i2c1 {
 	clock-frequency = <100000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
-	pmic: pfuze100@08 {
+	pmic: pfuze100@8 {
 		compatible = "fsl,pfuze100";
 		reg = <0x08>;
 
@@ -190,6 +269,7 @@
 			sw4_reg: sw4 {
 				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
 			};
 
 			swbst_reg: swbst {
@@ -244,12 +324,98 @@
 			};
 		};
 	};
+
+	elan@10 {
+		compatible = "elan,elan-touch";
+		reg = <0x10>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <10 2>;
+		gpio_elan_cs = <&gpio2 9 0>;
+		gpio_elan_rst = <&gpio4 4 0>;
+		gpio_intr = <&gpio2 10 0>;
+		status = "okay";
+	};
+
+	mma8450@1c {
+		compatible = "fsl,mma8450";
+		reg = <0x1c>;
+	};
+
+	max17135@48 {
+		compatible = "maxim,max17135";
+		reg = <0x48>;
+		vneg_pwrup = <1>;
+		gvee_pwrup = <2>;
+		vpos_pwrup = <10>;
+		gvdd_pwrup = <12>;
+		gvdd_pwrdn = <1>;
+		vpos_pwrdn = <2>;
+		gvee_pwrdn = <8>;
+		vneg_pwrdn = <10>;
+		gpio_pmic_pwrgood = <&gpio2 13 0>;
+		gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
+		gpio_pmic_wakeup = <&gpio2 14 0>;
+		gpio_pmic_v3p3 = <&gpio2 7 0>;
+		gpio_pmic_intr = <&gpio2 12 0>;
+
+		regulators {
+			DISPLAY_reg: DISPLAY {
+				regulator-name = "DISPLAY";
+			};
+
+			GVDD_reg: GVDD {
+				/* 20v */
+				regulator-name = "GVDD";
+			};
+
+			GVEE_reg: GVEE {
+				/* -22v */
+				regulator-name = "GVEE";
+			};
+
+			HVINN_reg: HVINN {
+				/* -22v */
+				regulator-name = "HVINN";
+			};
+
+			HVINP_reg: HVINP {
+				/* 20v */
+				regulator-name = "HVINP";
+			};
+
+			VCOM_reg: VCOM {
+				regulator-name = "VCOM";
+				/* Real max value: -500000 */
+				regulator-max-microvolt = <4325000>;
+				/* Real min value: -4325000 */
+				regulator-min-microvolt = <500000>;
+			};
+
+			VNEG_reg: VNEG {
+				/* -15v */
+				regulator-name = "VNEG";
+			};
+
+			VPOS_reg: VPOS {
+				/* 15v */
+				regulator-name = "VPOS";
+			};
+
+			V3P3_reg: V3P3 {
+				regulator-name = "V3P3";
+			};
+		};
+	};
+
 };
 
 &i2c2 {
 	clock-frequency = <100000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
 	codec: wm8962@1a {
@@ -264,6 +430,45 @@
 		PLLVDD-supply = <&vgen3_reg>;
 		SPKVDD1-supply = <&reg_aud4v>;
 		SPKVDD2-supply = <&reg_aud4v>;
+		amic-mono;
+	};
+
+	sii902x@39 {
+		compatible = "SiI,sii902x";
+		interrupt-parent = <&gpio2>;
+		interrupts = <10 2>;
+		mode_str ="1280x720M@60";
+		bits-per-pixel = <16>;
+		resets = <&sii902x_reset>;
+		reg = <0x39>;
+	};
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "disabled";
+
+	ov5640: ov5640@3c {
+		compatible = "ovti,ov5640";
+		reg = <0x3c>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_csi_0>;
+		clocks = <&clks IMX6SL_CLK_CSI>;
+		clock-names = "csi_mclk";
+		AVDD-supply = <&vgen6_reg>;  /* 2.8v */
+		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
+		pwn-gpios = <&gpio1 25 1>;
+		rst-gpios = <&gpio1 26 0>;
+		csi_id = <0>;
+		mclk = <24000000>;
+		mclk_source = <0>;
+		port {
+			ov5640_ep: endpoint {
+				remote-endpoint = <&csi_ep>;
+			};
+		};
 	};
 };
 
@@ -282,6 +487,17 @@
 				MX6SL_PAD_KEY_COL4__GPIO4_IO00	0x80000000
 				MX6SL_PAD_KEY_COL5__GPIO4_IO02	0x80000000
 				MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
+				MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
+				MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
+				MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15  0x17000
+				MX6SL_PAD_FEC_RX_ER__GPIO4_IO19	  0x1b0b0
+				MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x17000
+				MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x80000000
+				MX6SL_PAD_KEY_COL6__GPIO4_IO04    0x110b0
+				MX6SL_PAD_LCD_RESET__GPIO2_IO19   0x1b0b0
+				MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
+				MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
+				MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15  0x17000
 			>;
 		};
 
@@ -303,6 +519,39 @@
 			>;
 		};
 
+                pinctrl_epdc_0: epdcgrp-0 {
+                        fsl,pins = <
+                                MX6SL_PAD_EPDC_D0__EPDC_DATA00  0x80000000
+                                MX6SL_PAD_EPDC_D1__EPDC_DATA01  0x80000000
+                                MX6SL_PAD_EPDC_D2__EPDC_DATA02  0x80000000
+                                MX6SL_PAD_EPDC_D3__EPDC_DATA03  0x80000000
+                                MX6SL_PAD_EPDC_D4__EPDC_DATA04  0x80000000
+                                MX6SL_PAD_EPDC_D5__EPDC_DATA05  0x80000000
+                                MX6SL_PAD_EPDC_D6__EPDC_DATA06  0x80000000
+                                MX6SL_PAD_EPDC_D7__EPDC_DATA07  0x80000000
+                                MX6SL_PAD_EPDC_D8__EPDC_DATA08  0x80000000
+                                MX6SL_PAD_EPDC_D9__EPDC_DATA09  0x80000000
+                                MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x80000000
+                                MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x80000000
+                                MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x80000000
+                                MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x80000000
+                                MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x80000000
+                                MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x80000000
+                                MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x80000000
+                                MX6SL_PAD_EPDC_GDSP__EPDC_GDSP   0x80000000
+                                MX6SL_PAD_EPDC_GDOE__EPDC_GDOE   0x80000000
+                                MX6SL_PAD_EPDC_GDRL__EPDC_GDRL   0x80000000
+                                MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x80000000
+                                MX6SL_PAD_EPDC_SDOE__EPDC_SDOE   0x80000000
+                                MX6SL_PAD_EPDC_SDLE__EPDC_SDLE   0x80000000
+                                MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x80000000
+                                MX6SL_PAD_EPDC_BDR0__EPDC_BDR0   0x80000000
+                                MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x80000000
+                                MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x80000000
+                                MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x80000000
+                        >;
+                };
+
 		pinctrl_fec: fecgrp {
 			fsl,pins = <
 				MX6SL_PAD_FEC_MDC__FEC_MDC		0x1b0b0
@@ -337,6 +586,12 @@
 			>;
 		};
 
+		pinctrl_i2c1_gpio: i2c1grp_gpio {
+			fsl,pins = <
+				MX6SL_PAD_I2C1_SCL__GPIO3_IO12  0x1b8b1
+				MX6SL_PAD_I2C1_SDA__GPIO3_IO13  0x1b8b1
+			>;
+		};
 
 		pinctrl_i2c2: i2c2grp {
 			fsl,pins = <
@@ -345,6 +600,20 @@
 			>;
 		};
 
+		pinctrl_i2c2_gpio: i2c2grp_gpio {
+			fsl,pins = <
+				MX6SL_PAD_I2C2_SCL__GPIO3_IO14  0x1b8b1
+				MX6SL_PAD_I2C2_SDA__GPIO3_IO15  0x1b8b1
+			>;
+		};
+
+		pinctrl_i2c3: i2c3grp {
+			fsl,pins = <
+				MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x4001b8b1
+				MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x4001b8b1
+			>;
+		};
+
 		pinctrl_kpp: kppgrp {
 			fsl,pins = <
 				MX6SL_PAD_KEY_ROW0__KEY_ROW0    0x1b010
@@ -356,7 +625,7 @@
 			>;
 		};
 
-		pinctrl_lcd: lcdgrp {
+		pinctrl_lcdif_dat: lcdifdatgrp {
 			fsl,pins = <
 				MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
 				MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
@@ -382,6 +651,11 @@
 				MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
 				MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
 				MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
+			>;
+		};
+
+		pinctrl_lcdif_ctrl: lcdifctrlgrp {
+			fsl,pins = <
 				MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
 				MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
 				MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
@@ -401,6 +675,12 @@
 			>;
 		};
 
+		pinctrl_spdif: spdifgrp {
+			fsl,pins = <
+				MX6SL_PAD_SD2_DAT4__SPDIF_OUT 0x80000000
+			>;
+		};
+
 		pinctrl_uart1: uart1grp {
 			fsl,pins = <
 				MX6SL_PAD_UART1_RXD__UART1_RX_DATA	0x1b0b1
@@ -408,6 +688,24 @@
 			>;
 		};
 
+		pinctrl_uart4_1: uart4grp-1 {
+			fsl,pins = <
+				MX6SL_PAD_SD1_DAT4__UART4_RX_DATA	0x1b0b1
+				MX6SL_PAD_SD1_DAT5__UART4_TX_DATA	0x1b0b1
+				MX6SL_PAD_SD1_DAT7__UART4_CTS_B		0x1b0b1
+				MX6SL_PAD_SD1_DAT6__UART4_RTS_B		0x1b0b1
+			>;
+		};
+
+		pinctrl_uart4dte_1: uart4dtegrp-1 {
+			fsl,pins = <
+				MX6SL_PAD_SD1_DAT5__UART4_RX_DATA	0x1b0b1
+				MX6SL_PAD_SD1_DAT4__UART4_TX_DATA	0x1b0b1
+				MX6SL_PAD_SD1_DAT6__UART4_CTS_B		0x1b0b1
+				MX6SL_PAD_SD1_DAT7__UART4_RTS_B		0x1b0b1
+			>;
+		};
+
 		pinctrl_usbotg1: usbotg1grp {
 			fsl,pins = <
 				MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID	0x17059
@@ -524,9 +822,34 @@
 				MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
 			>;
 		};
+
+		pinctrl_csi_0: csigrp-0 {
+			fsl,pins = <
+				MX6SL_PAD_EPDC_GDRL__CSI_MCLK	0x110b0
+				MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x110b0
+				MX6SL_PAD_EPDC_GDSP__CSI_VSYNC	0x110b0
+				MX6SL_PAD_EPDC_GDOE__CSI_HSYNC	0x110b0
+				MX6SL_PAD_EPDC_SDLE__CSI_DATA09	0x110b0
+				MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110b0
+				MX6SL_PAD_EPDC_D7__CSI_DATA07	0x110b0
+				MX6SL_PAD_EPDC_D6__CSI_DATA06	0x110b0
+				MX6SL_PAD_EPDC_D5__CSI_DATA05	0x110b0
+				MX6SL_PAD_EPDC_D4__CSI_DATA04	0x110b0
+				MX6SL_PAD_EPDC_D3__CSI_DATA03	0x110b0
+				MX6SL_PAD_EPDC_D2__CSI_DATA02	0x110b0
+				MX6SL_PAD_EPDC_D1__CSI_DATA01	0x110b0
+				MX6SL_PAD_EPDC_D0__CSI_DATA00	0x110b0
+				MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000
+				MX6SL_PAD_EPDC_SDOE__GPIO1_IO25	 0x80000000
+			>;
+		};
 	};
 };
 
+&pxp {
+	status = "okay";
+};
+
 &kpp {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_kpp>;
@@ -545,13 +868,14 @@
 
 &lcdif {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lcd>;
+	pinctrl-0 = <&pinctrl_lcdif_dat
+		     &pinctrl_lcdif_ctrl>;
 	lcd-supply = <&reg_lcd_3v3>;
 	display = <&display0>;
 	status = "okay";
 
-	display0: display0 {
-		bits-per-pixel = <32>;
+	display0: display@0 {
+		bits-per-pixel = <16>;
 		bus-width = <24>;
 
 		display-timings {
@@ -585,7 +909,21 @@
 	status = "okay";
 };
 
+&spdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spdif>;
+	assigned-clocks = <&clks IMX6SL_CLK_SPDIF0_SEL>,
+		<&clks IMX6SL_CLK_SPDIF0_PODF>;
+	assigned-clock-parents = <&clks IMX6SL_CLK_PLL3_PFD3>;
+	assigned-clock-rates = <0>, <227368421>;
+	status = "okay";
+};
+
 &ssi2 {
+	fsl,mode = "i2s-slave";
+	assigned-clocks = <&clks IMX6SL_CLK_SSI2_SEL>,
+			  <&clks IMX6SL_CLK_SSI2>;
+	assigned-clock-rates = <0>, <24000000>;
 	status = "okay";
 };
 
@@ -600,6 +938,9 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_usbotg1>;
 	disable-over-current;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
 	status = "okay";
 };
 
@@ -610,6 +951,14 @@
 	status = "okay";
 };
 
+&usbphy1 {
+	fsl,tx-d-cal = <106>;
+};
+
+&usbphy2 {
+	fsl,tx-d-cal = <106>;
+};
+
 &usdhc1 {
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc1>;
@@ -618,6 +967,8 @@
 	bus-width = <8>;
 	cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
 	status = "okay";
 };
 
@@ -628,6 +979,8 @@
 	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
 	status = "okay";
 };
 
@@ -637,5 +990,7 @@
 	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
 	status = "okay";
 };
diff --git a/arch/arm/dts/imx6sl.dtsi b/arch/arm/dts/imx6sl.dtsi
index 37e341c6c35..39514718297 100644
--- a/arch/arm/dts/imx6sl.dtsi
+++ b/arch/arm/dts/imx6sl.dtsi
@@ -1,5 +1,6 @@
 /*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -30,6 +31,10 @@
 		gpio2 = &gpio3;
 		gpio3 = &gpio4;
 		gpio4 = &gpio5;
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+		mmc2 = &usdhc3;
+		mmc3 = &usdhc4;
 		serial0 = &uart1;
 		serial1 = &uart2;
 		serial2 = &uart3;
@@ -41,6 +46,10 @@
 		spi3 = &ecspi4;
 		usbphy0 = &usbphy1;
 		usbphy1 = &usbphy2;
+		usb0 = &usbotg1;
+		usb1 = &usbotg2;
+		usbgadget0 = &usbg1;
+		usbgadget1 = &usbg2;
 	};
 
 	cpus {
@@ -65,17 +74,37 @@
 				396000          1175000
 			>;
 			clock-latency = <61036>; /* two CLK32 periods */
-			clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
-					<&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
-					<&clks IMX6SL_CLK_PLL1_SYS>;
+			clocks = <&clks IMX6SL_CLK_ARM>,
+				 <&clks IMX6SL_CLK_PLL2_PFD2>,
+				 <&clks IMX6SL_CLK_STEP>,
+				 <&clks IMX6SL_CLK_PLL1_SW>,
+				 <&clks IMX6SL_CLK_PLL1_SYS>,
+				 <&clks IMX6SL_CLK_PLL1>,
+				 <&clks IMX6SL_PLL1_BYPASS>,
+				 <&clks IMX6SL_PLL1_BYPASS_SRC>;
 			clock-names = "arm", "pll2_pfd2_396m", "step",
-				      "pll1_sw", "pll1_sys";
+				      "pll1_sw", "pll1_sys", "pll1", "pll1_bypass",
+				      "pll1_bypass_src";
 			arm-supply = <&reg_arm>;
 			pu-supply = <&reg_pu>;
 			soc-supply = <&reg_soc>;
 		};
 	};
 
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x14000000>;
+			linux,cma-default;
+		};
+	};
+
 	intc: interrupt-controller@00a01000 {
 		compatible = "arm,cortex-a9-gic";
 		#interrupt-cells = <3>;
@@ -102,6 +131,10 @@
 		};
 	};
 
+	reg_vbus_wakeup: usb_vbus_wakeup {
+		compatible = "fsl,imx6-dummy-ldo2p5";
+	};
+
 	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -109,12 +142,51 @@
 		interrupt-parent = <&gpc>;
 		ranges;
 
-		ocram: sram@00900000 {
+		busfreq { /* BUSFREQ */
+			compatible = "fsl,imx_busfreq";
+			clocks = <&clks IMX6SL_CLK_PLL2_BUS>, <&clks IMX6SL_CLK_PLL2_PFD2>,
+					<&clks IMX6SL_CLK_PLL2_198M>, <&clks IMX6SL_CLK_ARM>,
+					<&clks IMX6SL_CLK_PLL3_USB_OTG>, <&clks IMX6SL_CLK_PERIPH>,
+					<&clks IMX6SL_CLK_PRE_PERIPH_SEL>, <&clks IMX6SL_CLK_PERIPH_CLK2_PODF>,
+					<&clks IMX6SL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SL_CLK_OSC>,
+					<&clks IMX6SL_CLK_PLL1_SYS>, <&clks IMX6SL_CLK_PERIPH2>,
+					<&clks IMX6SL_CLK_AHB>, <&clks IMX6SL_CLK_OCRAM_PODF>,
+					<&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PRE_PERIPH2_SEL>,
+					<&clks IMX6SL_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SL_CLK_PERIPH2_CLK2_PODF>,
+					<&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_PLL2_BYPASS_SRC>, <&clks IMX6SL_PLL2_BYPASS>,
+					<&clks IMX6SL_CLK_PLL2>, <&clks IMX6SL_CLK_PLL1>, <&clks IMX6SL_PLL1_BYPASS>,
+					<&clks IMX6SL_PLL1_BYPASS_SRC>;
+			clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
+				"periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb",
+				"ocram", "pll1_sw", "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "pll2_bypass_src",
+				"pll2_bypass", "pll2", "pll1", "pll1_bypass", "pll1_bypass_src";
+			fsl,max_ddr_freq = <400000000>;
+		};
+
+		ocrams: sram@00900000 {
+			compatible = "fsl,lpm-sram";
+			reg = <0x00900000 0x4000>;
+			clocks = <&clks IMX6SL_CLK_OCRAM>;
+		};
+
+		ocrams_ddr: sram@00904000 {
+			compatible = "fsl,ddr-lpm-sram";
+			reg = <0x00904000 0x1000>;
+			clocks = <&clks IMX6SL_CLK_OCRAM>;
+		};
+
+		ocram: sram@00905000 {
 			compatible = "mmio-sram";
-			reg = <0x00900000 0x20000>;
+			reg = <0x00905000 0x1B000>;
 			clocks = <&clks IMX6SL_CLK_OCRAM>;
 		};
 
+		ocram_optee: sram@00918000 {
+			compatible = "fsl,optee-lpm-sram";
+			reg = <0x00918000 0x8000>;
+			overw_reg = <&ocram 0x00905000 0x13000>;
+		};
+
 		L2: l2-cache@00a02000 {
 			compatible = "arm,pl310-cache";
 			reg = <0x00a02000 0x1000>;
@@ -174,6 +246,8 @@
 					clocks = <&clks IMX6SL_CLK_ECSPI1>,
 						 <&clks IMX6SL_CLK_ECSPI1>;
 					clock-names = "ipg", "per";
+					dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
+					dma-names = "rx", "tx";
 					status = "disabled";
 				};
 
@@ -186,6 +260,8 @@
 					clocks = <&clks IMX6SL_CLK_ECSPI2>,
 						 <&clks IMX6SL_CLK_ECSPI2>;
 					clock-names = "ipg", "per";
+					dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
+					dma-names = "rx", "tx";
 					status = "disabled";
 				};
 
@@ -198,6 +274,8 @@
 					clocks = <&clks IMX6SL_CLK_ECSPI3>,
 						 <&clks IMX6SL_CLK_ECSPI3>;
 					clock-names = "ipg", "per";
+					dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
+					dma-names = "rx", "tx";
 					status = "disabled";
 				};
 
@@ -210,6 +288,8 @@
 					clocks = <&clks IMX6SL_CLK_ECSPI4>,
 						 <&clks IMX6SL_CLK_ECSPI4>;
 					clock-names = "ipg", "per";
+					dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
+					dma-names = "rx", "tx";
 					status = "disabled";
 				};
 
@@ -261,8 +341,8 @@
 					clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
 						 <&clks IMX6SL_CLK_SSI1>;
 					clock-names = "ipg", "baud";
-					dmas = <&sdma 37 1 0>,
-					       <&sdma 38 1 0>;
+					dmas = <&sdma 37 22 0>,
+					       <&sdma 38 22 0>;
 					dma-names = "rx", "tx";
 					fsl,fifo-depth = <15>;
 					status = "disabled";
@@ -277,8 +357,8 @@
 					clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
 						 <&clks IMX6SL_CLK_SSI2>;
 					clock-names = "ipg", "baud";
-					dmas = <&sdma 41 1 0>,
-					       <&sdma 42 1 0>;
+					dmas = <&sdma 41 22 0>,
+					       <&sdma 42 22 0>;
 					dma-names = "rx", "tx";
 					fsl,fifo-depth = <15>;
 					status = "disabled";
@@ -293,8 +373,8 @@
 					clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
 						 <&clks IMX6SL_CLK_SSI3>;
 					clock-names = "ipg", "baud";
-					dmas = <&sdma 45 1 0>,
-					       <&sdma 46 1 0>;
+					dmas = <&sdma 45 22 0>,
+					       <&sdma 46 22 0>;
 					dma-names = "rx", "tx";
 					fsl,fifo-depth = <15>;
 					status = "disabled";
@@ -530,20 +610,21 @@
 					anatop-min-bit-val = <4>;
 					anatop-min-voltage = <800000>;
 					anatop-max-voltage = <1375000>;
+					anatop-enable-bit = <0>;
 				};
 
-				regulator-3p0 {
+				reg_3p0: regulator-3p0@120 {
 					compatible = "fsl,anatop-regulator";
 					regulator-name = "vdd3p0";
-					regulator-min-microvolt = <2800000>;
-					regulator-max-microvolt = <3150000>;
-					regulator-always-on;
+					regulator-min-microvolt = <2625000>;
+					regulator-max-microvolt = <3400000>;
 					anatop-reg-offset = <0x120>;
 					anatop-vol-bit-shift = <8>;
 					anatop-vol-bit-width = <5>;
 					anatop-min-bit-val = <0>;
 					anatop-min-voltage = <2625000>;
 					anatop-max-voltage = <3400000>;
+					anatop-enable-bit = <0>;
 				};
 
 				regulator-2p5 {
@@ -558,6 +639,7 @@
 					anatop-min-bit-val = <0>;
 					anatop-min-voltage = <2100000>;
 					anatop-max-voltage = <2850000>;
+					anatop-enable-bit = <0>;
 				};
 
 				reg_arm: regulator-vddcore {
@@ -575,6 +657,7 @@
 					anatop-min-bit-val = <1>;
 					anatop-min-voltage = <725000>;
 					anatop-max-voltage = <1450000>;
+					regulator-allow-bypass;
 				};
 
 				reg_pu: regulator-vddpu {
@@ -582,7 +665,8 @@
 					regulator-name = "vddpu";
 					regulator-min-microvolt = <725000>;
 					regulator-max-microvolt = <1450000>;
-					regulator-always-on;
+					regulator-enable-ramp-delay = <150>;
+					regulator-boot-on;
 					anatop-reg-offset = <0x140>;
 					anatop-vol-bit-shift = <9>;
 					anatop-vol-bit-width = <5>;
@@ -592,6 +676,7 @@
 					anatop-min-bit-val = <1>;
 					anatop-min-voltage = <725000>;
 					anatop-max-voltage = <1450000>;
+					regulator-allow-bypass;
 				};
 
 				reg_soc: regulator-vddsoc {
@@ -609,6 +694,7 @@
 					anatop-min-bit-val = <1>;
 					anatop-min-voltage = <725000>;
 					anatop-max-voltage = <1450000>;
+					regulator-allow-bypass;
 				};
 			};
 
@@ -625,6 +711,7 @@
 				reg = <0x020c9000 0x1000>;
 				interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SL_CLK_USBPHY1>;
+				phy-3p0-supply = <&reg_3p0>;
 				fsl,anatop = <&anatop>;
 			};
 
@@ -633,9 +720,16 @@
 				reg = <0x020ca000 0x1000>;
 				interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SL_CLK_USBPHY2>;
+				phy-3p0-supply = <&reg_3p0>;
 				fsl,anatop = <&anatop>;
 			};
 
+			usbphy_nop1: usbphy_nop1 {
+				compatible = "usb-nop-xceiv";
+				clocks = <&clks IMX6SL_CLK_USBPHY1>;
+				clock-names = "main_clk";
+			};
+
 			snvs: snvs@020cc000 {
 				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 				reg = <0x020cc000 0x4000>;
@@ -652,7 +746,8 @@
 					compatible = "syscon-poweroff";
 					regmap = <&snvs>;
 					offset = <0x38>;
-					mask = <0x60>;
+					value = <0x61>;
+					mask = <0x61>;
 					status = "disabled";
 				};
 			};
@@ -683,8 +778,12 @@
 				interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-parent = <&intc>;
 				pu-supply = <&reg_pu>;
-				clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
-					 <&clks IMX6SL_CLK_GPU2D_PODF>;
+				clocks = <&clks IMX6SL_CLK_GPU2D_PODF>, <&clks IMX6SL_CLK_GPU2D_OVG>,
+					<&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_LCDIF_AXI>,
+					<&clks IMX6SL_CLK_LCDIF_PIX>, <&clks IMX6SL_CLK_EPDC_AXI>,
+					<&clks IMX6SL_CLK_EPDC_PIX>, <&clks IMX6SL_CLK_PXP_AXI>;
+				clock-names = "gpu2d_podf", "gpu2d_ovg", "ipg", "lcd_axi",
+						"lcd_pix", "epdc_axi", "epdc_pix", "pxp_axi";
 				#power-domain-cells = <1>;
 			};
 
@@ -700,8 +799,14 @@
 			};
 
 			csi: csi@020e4000 {
+				compatible = "fsl,imx6sl-csi";
 				reg = <0x020e4000 0x4000>;
 				interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6SL_CLK_DUMMY>,
+					<&clks IMX6SL_CLK_DUMMY>,
+					<&clks IMX6SL_CLK_DUMMY>;
+				clock-names = "disp-axi", "csi_mclk", "disp_dcic";
+				status = "disabled";
 			};
 
 			spdc: spdc@020e8000 {
@@ -717,18 +822,26 @@
 					 <&clks IMX6SL_CLK_SDMA>;
 				clock-names = "ipg", "ahb";
 				#dma-cells = <3>;
+				iram = <&ocram>;
 				/* imx6sl reuses imx6q sdma firmware */
 				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 			};
 
 			pxp: pxp@020f0000 {
+				compatible = "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
 				reg = <0x020f0000 0x4000>;
 				interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6SL_CLK_PXP_AXI>, <&clks IMX6SL_CLK_DUMMY>;
+				clock-names = "pxp-axi", "disp-axi";
+				status = "disabled";
 			};
 
 			epdc: epdc@020f4000 {
+				compatible = "fsl,imx6sl-epdc", "fsl,imx6dl-epdc";
 				reg = <0x020f4000 0x4000>;
 				interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6SL_CLK_EPDC_AXI>, <&clks IMX6SL_CLK_EPDC_PIX>;
+				clock-names = "epdc_axi", "epdc_pix";
 			};
 
 			lcdif: lcdif@020f8000 {
@@ -748,6 +861,10 @@
 				interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
 					     <0 100 IRQ_TYPE_LEVEL_HIGH>,
 					     <0 101 IRQ_TYPE_LEVEL_HIGH>;
+				/* DCP clock always on */
+				clocks = <&clks IMX6SL_CLK_DUMMY>;
+				clock-names = "dcp";
+				status = "okay";
 			};
 		};
 
@@ -758,6 +875,20 @@
 			reg = <0x02100000 0x100000>;
 			ranges;
 
+			usbg1: usbg1 {
+				compatible = "fsl,imx27-usb-gadget";
+				dr_mode = "peripheral";
+				chipidea,usb = <&usbotg1>;
+				status = "okay";
+			};
+
+			usbg2: usbg2 {
+				compatible = "fsl,imx27-usb-gadget";
+				dr_mode = "peripheral";
+				chipidea,usb = <&usbotg2>;
+				status = "okay";
+			};
+
 			usbotg1: usb@02184000 {
 				compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 				reg = <0x02184000 0x200>;
@@ -768,6 +899,7 @@
 				ahb-burst-config = <0x0>;
 				tx-burst-size-dword = <0x10>;
 				rx-burst-size-dword = <0x10>;
+				fsl,anatop = <&anatop>;
 				status = "disabled";
 			};
 
@@ -794,6 +926,9 @@
 				ahb-burst-config = <0x0>;
 				tx-burst-size-dword = <0x10>;
 				rx-burst-size-dword = <0x10>;
+				phy_type = "hsic";
+				fsl,usbphy = <&usbphy_nop1>;
+				fsl,anatop = <&anatop>;
 				status = "disabled";
 			};
 
@@ -802,6 +937,7 @@
 				compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
 				reg = <0x02184800 0x200>;
 				clocks = <&clks IMX6SL_CLK_USBOH3>;
+				vbus-wakeup-supply = <&reg_vbus_wakeup>;
 			};
 
 			fec: ethernet@02188000 {
@@ -897,9 +1033,11 @@
 				reg = <0x021b0000 0x4000>;
 			};
 
-			rngb: rngb@021b4000 {
+			rng: rng@021b4000 {
+				compatible = "fsl,imx6sl-rng", "fsl,imx-rng", "imx-rng";
 				reg = <0x021b4000 0x4000>;
 				interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6SL_CLK_DUMMY>;
 			};
 
 			weim: weim@021b8000 {
@@ -922,6 +1060,24 @@
 				reg = <0x021d8000 0x4000>;
 				status = "disabled";
 			};
+
+			gpu: gpu@02200000 {
+				compatible = "fsl,imx6sl-gpu", "fsl,imx6q-gpu";
+				reg = <0x02200000 0x4000>, <0x02204000 0x4000>,
+					  <0x80000000 0x0>, <0x0 0x8000000>;
+				reg-names = "iobase_2d", "iobase_vg",
+						"phys_baseaddr", "contiguous_mem";
+				interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>, <0 11 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "irq_2d", "irq_vg";
+				clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
+						<&clks IMX6SL_CLK_MMDC_ROOT>,
+						<&clks IMX6SL_CLK_GPU2D_OVG>;
+				clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
+						  "gpu2d_clk";
+				resets = <&src 3>, <&src 3>;
+				reset-names = "gpu2d", "gpuvg";
+				power-domains = <&gpc 1>;
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/imx6sll-evk.dts b/arch/arm/dts/imx6sll-evk.dts
index b4af007c983..b5f06c8ffbe 100644
--- a/arch/arm/dts/imx6sll-evk.dts
+++ b/arch/arm/dts/imx6sll-evk.dts
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -13,9 +14,13 @@
 #include "imx6sll.dtsi"
 
 / {
-	model = "Freescale i.MX6SLL EVK Board";
+	model = "i.MX6SLL EVK Board";
 	compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
 
+	chosen {
+		stdout-path = &uart1;
+	};
+
 	memory {
 		reg = <0x80000000 0x80000000>;
 	};
@@ -93,7 +98,7 @@
 			compatible = "regulator-fixed";
 			reg = <4>;
 			regulator-name = "lcd-pwr";
-			gpio = <&gpio4 8 0>;
+			gpio = <&gpio4 3 0>;
 			enable-active-high;
 		};
 
@@ -103,6 +108,8 @@
 			regulator-min-microvolt = <3000000>;
 			regulator-max-microvolt = <3000000>;
 			gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
+			off-on-delay-us = <10000>;
+			startup-delay-us = <2000>;
 			enable-active-high;
 		};
 
@@ -120,6 +127,8 @@
 			regulator-min-microvolt = <3000000>;
 			regulator-max-microvolt = <3000000>;
 			gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+			off-on-delay-us = <10000>;
+			startup-delay-us = <2000>;
 			enable-active-high;
 		};
 
@@ -162,11 +171,14 @@
 
 &i2c1 {
 	clock-frequency = <100000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
-	pmic: pfuze100@08 {
+	pmic: pfuze100@8 {
 		compatible = "fsl,pfuze100";
 		reg = <0x08>;
 
@@ -211,6 +223,7 @@
 			sw4_reg: sw4 {
 				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
 			};
 
 			swbst_reg: swbst {
@@ -314,10 +327,10 @@
 
 			VCOM_reg: VCOM {
 				regulator-name = "VCOM";
-				/* 2's-compliment, -4325000 */
-				regulator-min-microvolt = <0xffbe0178>;
-				/* 2's-compliment, -500000 */
-				regulator-max-microvolt = <0xfff85ee0>;
+				/* Real max value: -500000 */
+				regulator-max-microvolt = <4325000>;
+				/* Real min value: -4325000 */
+				regulator-min-microvolt = <500000>;
 			};
 
 			VNEG_reg: VNEG {
@@ -339,8 +352,11 @@
 
 &i2c3 {
 	clock-frequency = <100000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
 	codec: wm8962@1a {
@@ -485,8 +501,8 @@
 				MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE	0x79
 				MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC		0x79
 				MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC		0x79
-				MX6SLL_PAD_LCD_RESET__LCD_RESET		0x79
-				MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08	0x79
+				MX6SLL_PAD_LCD_RESET__GPIO2_IO19		0x17059
+				MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x17059
 			>;
 		};
 
@@ -534,34 +550,34 @@
 
 		pinctrl_usdhc1: usdhc1grp {
 			fsl,pins = <
-				MX6SLL_PAD_SD1_CMD__SD1_CMD	0x17059
-				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x13059
-				MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x17059
-				MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x17059
-				MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x17059
-				MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x17059
+				MX6SLL_PAD_SD1_CMD__SD1_CMD	0x17061
+				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x13061
+				MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x17061
+				MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x17061
+				MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x17061
+				MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x17061
 			>;
 		};
 
 		pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
 			fsl,pins = <
-				MX6SLL_PAD_SD1_CMD__SD1_CMD	0x170b9
-				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x130b9
-				MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x170b9
-				MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x170b9
-				MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x170b9
-				MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x170b9
+				MX6SLL_PAD_SD1_CMD__SD1_CMD	0x170a1
+				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x130a1
+				MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x170a1
+				MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x170a1
+				MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x170a1
+				MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x170a1
 			>;
 		};
 
 		pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
 			fsl,pins = <
-				MX6SLL_PAD_SD1_CMD__SD1_CMD	0x170f9
+				MX6SLL_PAD_SD1_CMD__SD1_CMD	0x170e9
 				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x130f9
-				MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x170f9
-				MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x170f9
-				MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x170f9
-				MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x170f9
+				MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x170e9
+				MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x170e9
+				MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x170e9
+				MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x170e9
 			>;
 		};
 
@@ -615,34 +631,34 @@
 
 		pinctrl_usdhc3: usdhc3grp {
 			fsl,pins = <
-				MX6SLL_PAD_SD3_CMD__SD3_CMD	0x17059
-				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x13059
-				MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x17059
-				MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x17059
-				MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x17059
-				MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x17059
+				MX6SLL_PAD_SD3_CMD__SD3_CMD	0x17061
+				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x13061
+				MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x17061
+				MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x17061
+				MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x17061
+				MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x17061
 			>;
 		};
 
 		pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 			fsl,pins = <
-				MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170b9
-				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x130b9
-				MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170b9
-				MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170b9
-				MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170b9
-				MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x170b9
+				MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170a1
+				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x130a1
+				MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170a1
+				MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170a1
+				MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170a1
+				MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x170a1
 			>;
 		};
 
 		pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 			fsl,pins = <
-				MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170f9
+				MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170e9
 				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x130f9
-				MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170f9
-				MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170f9
-				MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170f9
-				MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x170f9
+				MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170e9
+				MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170e9
+				MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170e9
+				MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x170e9
 			>;
 		};
 
@@ -659,6 +675,13 @@
 			>;
 		};
 
+		pinctrl_i2c1_gpio: i2c1grp_gpio {
+			fsl,pins = <
+				MX6SLL_PAD_I2C1_SCL__GPIO3_IO12  0x1b8b1
+				MX6SLL_PAD_I2C1_SDA__GPIO3_IO13  0x1b8b1
+			>;
+		};
+
 		pinctrl_i2c3: i2c3grp {
 			fsl,pins = <
 				MX6SLL_PAD_AUD_RXFS__I2C3_SCL  0x4041b8b1
@@ -666,11 +689,24 @@
 			>;
 		};
 
+		pinctrl_i2c3_gpio: i2c3grp_gpio {
+			fsl,pins = <
+				MX6SLL_PAD_AUD_RXFS__GPIO1_IO00  0x41b8b1
+				MX6SLL_PAD_AUD_RXC__GPIO1_IO01   0x41b8b1
+			>;
+		};
+
 		pinctrl_pwm1: pmw1grp {
 			fsl,pins = <
 				MX6SLL_PAD_PWM1__PWM1_OUT   0x110b0
 			>;
 		};
+
+		pinctrl_wdog1: wdog1grp	{
+			fsl,pins = <
+				MX6SLL_PAD_WDOG_B__WDOG1_B   0x170b0
+			>;
+		};
 	};
 };
 
@@ -679,11 +715,11 @@
 	pinctrl-0 = <&pinctrl_lcdif_dat
 		     &pinctrl_lcdif_ctrl>;
 	lcd-supply = <&reg_lcd>;
-	display = <&display>;
+	display = <&display0>;
 	status = "okay";
 
-	display: display {
-		bits-per-pixel = <16>;
+	display0: display@0 {
+		bits-per-pixel = <24>;
 		bus-width = <24>;
 
 		display-timings {
@@ -753,7 +789,7 @@
 	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 	vqmmc-supply = <&reg_sd2_vmmc>;
 	bus-width = <8>;
-	no-removable;
+	non-removable;
 	status = "okay";
 };
 
@@ -799,3 +835,9 @@
 &ssi2 {
 	status = "okay";
 };
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog1>;
+	fsl,ext-reset-output;
+};
diff --git a/arch/arm/dts/imx6sll-lpddr2-val.dts b/arch/arm/dts/imx6sll-lpddr2-val.dts
new file mode 100644
index 00000000000..66111b85fb1
--- /dev/null
+++ b/arch/arm/dts/imx6sll-lpddr2-val.dts
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6sll-lpddr3-val.dts"
+
diff --git a/arch/arm/dts/imx6sll-lpddr3-val-ecspi.dts b/arch/arm/dts/imx6sll-lpddr3-val-ecspi.dts
new file mode 100644
index 00000000000..60b90bd0232
--- /dev/null
+++ b/arch/arm/dts/imx6sll-lpddr3-val-ecspi.dts
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6sll-lpddr3-val.dts"
+
+&ecspi1 {
+	status = "okay";
+};
+
+&lcdif {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/imx6sll-lpddr3-val.dts b/arch/arm/dts/imx6sll-lpddr3-val.dts
new file mode 100644
index 00000000000..458789a394b
--- /dev/null
+++ b/arch/arm/dts/imx6sll-lpddr3-val.dts
@@ -0,0 +1,857 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "imx6sll.dtsi"
+
+/ {
+	model = "i.MX6SLL Validation Board";
+	compatible = "fsl,imx6sll-lpddr3-val", "fsl,imx6sll";
+
+	memory {
+		reg = <0x80000000 0x80000000>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_led>;
+
+		users {
+			label = "debug";
+			gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm1 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+		status = "okay";
+	};
+
+	pxp_v4l2_out {
+		compatible = "fsl,imx6sl-pxp-v4l2";
+		status = "okay";
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&swbst_reg>;
+		};
+
+		reg_usb_otg2_vbus: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "usb_otg2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&swbst_reg>;
+		};
+
+		reg_aud3v: regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "wm8962-supply-3v15";
+			regulator-min-microvolt = <3150000>;
+			regulator-max-microvolt = <3150000>;
+			regulator-boot-on;
+		};
+
+		reg_aud4v: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "wm8962-supply-4v2";
+			regulator-min-microvolt = <4325000>;
+			regulator-max-microvolt = <4325000>;
+			regulator-boot-on;
+		};
+
+		reg_lcd: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "lcd-pwr";
+			gpio = <&gpio4 8 0>;
+			enable-active-high;
+		};
+
+		reg_sd1_vmmc: sd1_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "SD1_SPWR";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
+			off-on-delay-us = <20000>;
+			startup-delay-us = <2000>;
+			enable-active-high;
+		};
+
+		reg_sd2_vmmc: sd2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "eMMC-VCCQ";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-boot-on;
+		};
+
+		reg_sd3_vmmc: sd3_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "SD3_WIFI";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+			off-on-delay-us = <20000>;
+			startup-delay-us = <2000>;
+			enable-active-high;
+		};
+
+	};
+
+	sound {
+		compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962";
+		model = "wm8962-audio";
+		cpu-dai = <&ssi2>;
+		audio-codec = <&codec>;
+		audio-routing =
+			"Headphone Jack", "HPOUTL",
+			"Headphone Jack", "HPOUTR",
+			"Ext Spk", "SPKOUTL",
+			"Ext Spk", "SPKOUTR",
+			"AMIC", "MICBIAS",
+			"IN3R", "AMIC";
+		mux-int-port = <2>;
+		mux-ext-port = <3>;
+		codec-master;
+		hp-det-gpios = <&gpio4 24 1>;
+	};
+};
+
+&audmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_audmux3>;
+	status = "okay";
+};
+
+&clks {
+	assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <393216000>;
+};
+
+&cpu0 {
+	arm-supply = <&sw1a_reg>;
+	soc-supply = <&sw1c_reg>;
+};
+
+&csi {
+	status = "disabled";
+
+	port {
+		csi1_ep: endpoint {
+			remote-endpoint = <&ov5640_ep>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pfuze100@8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3b_reg: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-always-on;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+
+	max17135: max17135@48 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_max17135>;
+		compatible = "maxim,max17135";
+		reg = <0x48>;
+		status = "okay";
+
+		vneg_pwrup = <1>;
+		gvee_pwrup = <2>;
+		vpos_pwrup = <10>;
+		gvdd_pwrup = <12>;
+		gvdd_pwrdn = <1>;
+		vpos_pwrdn = <2>;
+		gvee_pwrdn = <8>;
+		vneg_pwrdn = <10>;
+		gpio_pmic_pwrgood = <&gpio2 13 0>;
+		gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
+		gpio_pmic_wakeup = <&gpio2 14 0>;
+		gpio_pmic_v3p3 = <&gpio2 7 0>;
+		gpio_pmic_intr = <&gpio2 12 0>;
+
+		regulators {
+			DISPLAY_reg: DISPLAY {
+				regulator-name = "DISPLAY";
+			};
+
+			GVDD_reg: GVDD {
+				/* 20v */
+				regulator-name = "GVDD";
+			};
+
+			GVEE_reg: GVEE {
+				/* -22v */
+				regulator-name = "GVEE";
+			};
+
+			HVINN_reg: HVINN {
+				/* -22v */
+				regulator-name = "HVINN";
+			};
+
+			HVINP_reg: HVINP {
+				/* 20v */
+				regulator-name = "HVINP";
+			};
+
+			VCOM_reg: VCOM {
+				regulator-name = "VCOM";
+				/* Real max value: -500000 */
+				regulator-max-microvolt = <4325000>;
+				/* Real min value: -4325000 */
+				regulator-min-microvolt = <500000>;
+			};
+
+			VNEG_reg: VNEG {
+				/* -15v */
+				regulator-name = "VNEG";
+			};
+
+			VPOS_reg: VPOS {
+				/* 15v */
+				regulator-name = "VPOS";
+			};
+
+			V3P3_reg: V3P3 {
+				regulator-name = "V3P3";
+			};
+		};
+	};
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+        scl-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+        sda-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	codec: wm8962@1a {
+		compatible = "wlf,wm8962";
+		reg = <0x1a>;
+		clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>;
+		DCVDD-supply = <&vgen3_reg>;
+		DBVDD-supply = <&reg_aud3v>;
+		AVDD-supply = <&vgen3_reg>;
+		CPVDD-supply = <&vgen3_reg>;
+		MICVDD-supply = <&reg_aud3v>;
+		PLLVDD-supply = <&vgen3_reg>;
+		SPKVDD1-supply = <&reg_aud4v>;
+		SPKVDD2-supply = <&reg_aud4v>;
+		amic-mono;
+	};
+
+	ov5640: ov5640@3c {
+		compatible = "ovti,ov5640";
+		reg = <0x3c>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_csi1>;
+		clocks = <&clks IMX6SLL_CLK_CSI>;
+		clock-names = "csi_mclk";
+		AVDD-supply = <&vgen6_reg>;  /* 2.8v */
+		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
+		pwn-gpios = <&gpio1 25 1>;
+		rst-gpios = <&gpio1 26 0>;
+		csi_id = <0>;
+		mclk = <24000000>;
+		mclk_source = <0>;
+		status = "disabled";
+		port {
+			ov5640_ep: endpoint {
+				remote-endpoint = <&csi1_ep>;
+			};
+		};
+	};
+};
+
+&gpc {
+	fsl,ldo-bypass = <1>;
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog &pinctrl_hog_sd2_reset>;
+
+	imx6sll-lpddr3-val {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
+				MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x17059
+				MX6SLL_PAD_KEY_COL3__GPIO3_IO30	0x17059
+				MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059
+				MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 /* SD3 CD */
+				MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 /*SD3 RESET */
+				MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059
+				MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */
+			>;
+		};
+
+		pinctrl_hog_sd2_reset: hoggrp-1 {
+			fsl,pins = <
+				MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x417059
+			>;
+		};
+
+		pinctrl_audmux3: audmux3grp {
+			fsl,pins = <
+				MX6SLL_PAD_AUD_TXC__AUD3_TXC		0x4130b0
+				MX6SLL_PAD_AUD_TXFS__AUD3_TXFS		0x4130b0
+				MX6SLL_PAD_AUD_TXD__AUD3_TXD		0x4110b0
+				MX6SLL_PAD_AUD_RXD__AUD3_RXD		0x4130b0
+				MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT	0x4130b0
+			>;
+		};
+
+		pinctrl_csi1: csi1grp {
+			fsl,pins = <
+				MX6SLL_PAD_EPDC_GDRL__CSI_MCLK		0x1b088
+				MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK	0x1b088
+				MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC		0x1b088
+				MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC		0x1b088
+				MX6SLL_PAD_EPDC_DATA02__CSI_DATA02	0x1b088
+				MX6SLL_PAD_EPDC_DATA03__CSI_DATA03	0x1b088
+				MX6SLL_PAD_EPDC_DATA04__CSI_DATA04	0x1b088
+				MX6SLL_PAD_EPDC_DATA05__CSI_DATA05	0x1b088
+				MX6SLL_PAD_EPDC_DATA06__CSI_DATA06	0x1b088
+				MX6SLL_PAD_EPDC_DATA07__CSI_DATA07	0x1b088
+				MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08	0x1b088
+				MX6SLL_PAD_EPDC_SDLE__CSI_DATA09	0x1b088
+				MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26	0x80000000
+				MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25	0x80000000
+			>;
+		};
+
+		pinctrl_led: ledgrp {
+			fsl,pins = <
+				MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x17059
+			>;
+		};
+
+                pinctrl_epdc0: epdcgrp0 {
+                        fsl,pins = <
+				MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00	0x100b1
+				MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01	0x100b1
+				MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02	0x100b1
+				MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03	0x100b1
+				MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04	0x100b1
+				MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05	0x100b1
+				MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06	0x100b1
+				MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07	0x100b1
+				MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08	0x100b1
+				MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09	0x100b1
+				MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10	0x100b1
+				MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11	0x100b1
+				MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12	0x100b1
+				MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13	0x100b1
+				MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14	0x100b1
+				MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15	0x100b1
+				MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P	0x100b1
+				MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE		0x100b1
+				MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE		0x100b1
+				MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR	0x100b1
+				MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0	0x100b1
+				MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK	0x100b1
+				MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE		0x100b1
+				MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL		0x100b1
+				MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP		0x100b1
+                       >;
+                };
+
+		pinctrl_lcdif_dat: lcdifdatgrp {
+			fsl,pins = <
+				MX6SLL_PAD_LCD_DATA00__LCD_DATA00	0x79
+				MX6SLL_PAD_LCD_DATA01__LCD_DATA01	0x79
+				MX6SLL_PAD_LCD_DATA02__LCD_DATA02	0x79
+				MX6SLL_PAD_LCD_DATA03__LCD_DATA03	0x79
+				MX6SLL_PAD_LCD_DATA04__LCD_DATA04	0x79
+				MX6SLL_PAD_LCD_DATA05__LCD_DATA05	0x79
+				MX6SLL_PAD_LCD_DATA06__LCD_DATA06	0x79
+				MX6SLL_PAD_LCD_DATA07__LCD_DATA07	0x79
+				MX6SLL_PAD_LCD_DATA08__LCD_DATA08	0x79
+				MX6SLL_PAD_LCD_DATA09__LCD_DATA09	0x79
+				MX6SLL_PAD_LCD_DATA10__LCD_DATA10	0x79
+				MX6SLL_PAD_LCD_DATA11__LCD_DATA11	0x79
+				MX6SLL_PAD_LCD_DATA12__LCD_DATA12	0x79
+				MX6SLL_PAD_LCD_DATA13__LCD_DATA13	0x79
+				MX6SLL_PAD_LCD_DATA14__LCD_DATA14	0x79
+				MX6SLL_PAD_LCD_DATA15__LCD_DATA15	0x79
+				MX6SLL_PAD_LCD_DATA16__LCD_DATA16	0x79
+				MX6SLL_PAD_LCD_DATA17__LCD_DATA17	0x79
+				MX6SLL_PAD_LCD_DATA18__LCD_DATA18	0x79
+				MX6SLL_PAD_LCD_DATA19__LCD_DATA19	0x79
+				MX6SLL_PAD_LCD_DATA20__LCD_DATA20	0x79
+				MX6SLL_PAD_LCD_DATA21__LCD_DATA21	0x79
+				MX6SLL_PAD_LCD_DATA22__LCD_DATA22	0x79
+				MX6SLL_PAD_LCD_DATA23__LCD_DATA23	0x79
+			>;
+		};
+
+		pinctrl_lcdif_ctrl: lcdifctrlgrp {
+			fsl,pins = <
+				MX6SLL_PAD_LCD_CLK__LCD_CLK		0x79
+				MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE	0x79
+				MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC		0x79
+				MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC		0x79
+				MX6SLL_PAD_LCD_RESET__LCD_RESET		0x79
+				MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08	0x79
+			>;
+		};
+
+		pinctrl_max17135: max17135grp-1 {
+			fsl,pins = <
+				MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13	0x80000000  /* pwrgood */
+				MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03	0x80000000  /* vcom_ctrl */
+				MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14	0x80000000  /* wakeup */
+				MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07	0x80000000  /* v3p3 */
+				MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12	0x80000000  /* pwr int */
+			>;
+		};
+
+		pinctrl_spdif: spdifgrp {
+			fsl,pins = <
+				MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x4130b0
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1
+				MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX6SLL_PAD_SD1_CMD__SD1_CMD	0x17059
+				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x17059
+				MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x17059
+				MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x17059
+				MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x17059
+				MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x17059
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+			fsl,pins = <
+				MX6SLL_PAD_SD1_CMD__SD1_CMD	0x170b9
+				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x170b9
+				MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x170b9
+				MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x170b9
+				MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x170b9
+				MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x170b9
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+			fsl,pins = <
+				MX6SLL_PAD_SD1_CMD__SD1_CMD	0x170f9
+				MX6SLL_PAD_SD1_CLK__SD1_CLK	0x170f9
+				MX6SLL_PAD_SD1_DATA0__SD1_DATA0	0x170f9
+				MX6SLL_PAD_SD1_DATA1__SD1_DATA1	0x170f9
+				MX6SLL_PAD_SD1_DATA2__SD1_DATA2	0x170f9
+				MX6SLL_PAD_SD1_DATA3__SD1_DATA3	0x170f9
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6SLL_PAD_SD2_CMD__SD2_CMD		0x17059
+				MX6SLL_PAD_SD2_CLK__SD2_CLK		0x13059
+				MX6SLL_PAD_SD2_DATA0__SD2_DATA0 	0x17059
+				MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x17059
+				MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x17059
+				MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x17059
+				MX6SLL_PAD_SD2_DATA4__SD2_DATA4		0x17059
+				MX6SLL_PAD_SD2_DATA5__SD2_DATA5		0x17059
+				MX6SLL_PAD_SD2_DATA6__SD2_DATA6		0x17059
+				MX6SLL_PAD_SD2_DATA7__SD2_DATA7		0x17059
+				MX6SLL_PAD_GPIO4_IO21__SD2_STROBE	0x413059
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
+			fsl,pins = <
+				MX6SLL_PAD_SD2_CMD__SD2_CMD		0x170b9
+				MX6SLL_PAD_SD2_CLK__SD2_CLK		0x130b9
+				MX6SLL_PAD_SD2_DATA0__SD2_DATA0 	0x170b9
+				MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x170b9
+				MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x170b9
+				MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x170b9
+				MX6SLL_PAD_SD2_DATA4__SD2_DATA4		0x170b9
+				MX6SLL_PAD_SD2_DATA5__SD2_DATA5		0x170b9
+				MX6SLL_PAD_SD2_DATA6__SD2_DATA6		0x170b9
+				MX6SLL_PAD_SD2_DATA7__SD2_DATA7		0x170b9
+				MX6SLL_PAD_GPIO4_IO21__SD2_STROBE	0x4130b9
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
+			fsl,pins = <
+				MX6SLL_PAD_SD2_CMD__SD2_CMD		0x170f9
+				MX6SLL_PAD_SD2_CLK__SD2_CLK		0x130f9
+				MX6SLL_PAD_SD2_DATA0__SD2_DATA0 	0x170f9
+				MX6SLL_PAD_SD2_DATA1__SD2_DATA1		0x170f9
+				MX6SLL_PAD_SD2_DATA2__SD2_DATA2		0x170f9
+				MX6SLL_PAD_SD2_DATA3__SD2_DATA3		0x170f9
+				MX6SLL_PAD_SD2_DATA4__SD2_DATA4		0x170f9
+				MX6SLL_PAD_SD2_DATA5__SD2_DATA5		0x170f9
+				MX6SLL_PAD_SD2_DATA6__SD2_DATA6		0x170f9
+				MX6SLL_PAD_SD2_DATA7__SD2_DATA7		0x170f9
+				MX6SLL_PAD_GPIO4_IO21__SD2_STROBE	0x4130f9
+			>;
+		};
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX6SLL_PAD_SD3_CMD__SD3_CMD	0x17059
+				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x17059
+				MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x17059
+				MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x17059
+				MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x17059
+				MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x17059
+			>;
+		};
+
+		pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+			fsl,pins = <
+				MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170b9
+				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x170b9
+				MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170b9
+				MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170b9
+				MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170b9
+				MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x170b9
+			>;
+		};
+
+		pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+			fsl,pins = <
+				MX6SLL_PAD_SD3_CMD__SD3_CMD	0x170f9
+				MX6SLL_PAD_SD3_CLK__SD3_CLK	0x170f9
+				MX6SLL_PAD_SD3_DATA0__SD3_DATA0	0x170f9
+				MX6SLL_PAD_SD3_DATA1__SD3_DATA1	0x170f9
+				MX6SLL_PAD_SD3_DATA2__SD3_DATA2	0x170f9
+				MX6SLL_PAD_SD3_DATA3__SD3_DATA3	0x170f9
+			>;
+		};
+
+		pinctrl_usbotg1: usbotg1grp {
+			fsl,pins = <
+				MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX6SLL_PAD_I2C1_SCL__I2C1_SCL	 0x4001b8b1
+				MX6SLL_PAD_I2C1_SDA__I2C1_SDA	 0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c1_gpio: i2c1grp_gpio {
+			fsl,pins = <
+				MX6SLL_PAD_I2C1_SCL__GPIO3_IO12    0x1b8b1
+				MX6SLL_PAD_I2C1_SDA__GPIO3_IO13    0x1b8b1
+			>;
+		};
+
+		pinctrl_i2c3: i2c3grp {
+			fsl,pins = <
+				MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL  0x4041b8b1
+				MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA  0x4041b8b1
+			>;
+		};
+
+		pinctrl_i2c3_gpio: i2c3grp_gpio {
+			fsl,pins = <
+				MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29  0x41b8b1
+				MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30  0x41b8b1
+			>;
+		};
+
+		pinctrl_pwm1: pmw1grp {
+			fsl,pins = <
+				MX6SLL_PAD_PWM1__PWM1_OUT   0x110b0
+			>;
+		};
+
+		pinctrl_ecspi1: ecspi1grp {
+			fsl,pins = <
+				MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO	 0x100b1
+				MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI	 0x100b1
+				MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK	 0x100b1
+				MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11	 0x100b1
+			>;
+		};
+	};
+};
+
+&lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif_dat
+		     &pinctrl_lcdif_ctrl>;
+	lcd-supply = <&reg_lcd>;
+	display = <&display0>;
+	status = "okay";
+
+	display0: display@0 {
+		bits-per-pixel = <16>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+				clock-frequency = <33500000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <89>;
+				hfront-porch = <164>;
+				vback-porch = <23>;
+				vfront-porch = <10>;
+				hsync-len = <10>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&pxp {
+	status = "okay";
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sd1_vmmc>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+	vqmmc-supply = <&reg_sd2_vmmc>;
+	bus-width = <8>;
+	no-removable;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sd3_vmmc>;
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg1>;
+	disable-over-current;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usbotg2 {
+	vbus-supply = <&reg_usb_otg2_vbus>;
+	dr_mode = "host";
+	disable-over-current;
+	status = "okay";
+};
+
+&ecspi1 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio4 11 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	status = "disabled";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	flash: m25p80@0 {
+		compatible = "st,m25p32", "jedec,spi-nor";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&epdc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_epdc0>;
+	V3P3-supply = <&V3P3_reg>;
+	VCOM-supply = <&VCOM_reg>;
+	DISPLAY-supply = <&DISPLAY_reg>;
+	status = "okay";
+};
+
+&ssi2 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6sll.dtsi b/arch/arm/dts/imx6sll.dtsi
index ebc6d9d2c98..a79ff2f937b 100644
--- a/arch/arm/dts/imx6sll.dtsi
+++ b/arch/arm/dts/imx6sll.dtsi
@@ -1,5 +1,6 @@
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -37,6 +38,11 @@
 		spi4 = &ecspi4;
 		usbphy0 = &usbphy1;
 		usbphy1 = &usbphy2;
+		usb0 = &usbotg1;
+		usb1 = &usbotg2;
+		usbgadget0 = &usbg1;
+		usbgadget1 = &usbg2;
+		video0 = &lcdif;
 	};
 
 	cpus {
@@ -50,14 +56,14 @@
 			next-level-cache = <&L2>;
 			operating-points = <
 				/* kHz    uV */
-				996000  1225000
+				996000  1275000
 				792000  1175000
 				396000  1075000
 				198000	975000
 			>;
 			fsl,soc-operating-points = <
 				/* ARM kHz      SOC-PU uV */
-				996000          1225000
+				996000          1175000
 				792000          1175000
 				396000          1175000
 				198000		1175000
@@ -166,6 +172,12 @@
 			reg = <0x00905000 0x1B000>;
 		};
 
+		ocram_optee: sram@00918000 {
+			compatible = "fsl,optee-lpm-sram";
+			reg = <0x00918000 0x8000>;
+			overw_reg = <&ocram 0x00905000 0x13000>;
+		};
+
 		L2: l2-cache@00a02000 {
 			compatible = "arm,pl310-cache";
 			reg = <0x00a02000 0x1000>;
@@ -210,7 +222,7 @@
 						      "rxtx1", "rxtx2",
 						      "rxtx3", "rxtx4",
 						      "rxtx5", "rxtx6",
-						      "rxtx7", "dma";
+						      "rxtx7", "spba";
 					status = "disabled";
 				};
 
@@ -395,8 +407,8 @@
 				reg = <0x02098000 0x4000>;
 				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
-					 <&clks IMX6SLL_CLK_GPT_SERIAL>;
-				clock-names = "ipg", "per";
+					 <&clks IMX6SLL_CLK_GPT_3M>;
+				clock-names = "ipg", "osc_per";
 			};
 
 			gpio1: gpio@0209c000 {
@@ -528,7 +540,6 @@
 				fsl,tempmon = <&anatop>;
 				fsl,tempmon-data = <&ocotp>;
 				clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
-				status = "disabled";
 			};
 
 			usbphy1: usbphy@020c9000 {
@@ -574,7 +585,7 @@
 					regmap = <&snvs>;
 					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 					linux,keycode = <KEY_POWER>;
-					wakeup;
+					wakeup-source;
 				};
 			};
 
@@ -629,7 +640,7 @@
 			};
 
 			sdma: sdma@020ec000 {
-				compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma";
+				compatible = "fsl,imx6ul-sdma", "fsl,imx35-sdma";
 				reg = <0x020ec000 0x4000>;
 				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SLL_CLK_SDMA>,
@@ -689,6 +700,20 @@
 			reg = <0x02100000 0x100000>;
 			ranges;
 
+			usbg1: usbg1 {
+				compatible = "fsl,imx27-usb-gadget";
+				dr_mode = "peripheral";
+				chipidea,usb = <&usbotg1>;
+				status = "okay";
+			};
+
+			usbg2: usbg2 {
+				compatible = "fsl,imx27-usb-gadget";
+				dr_mode = "peripheral";
+				chipidea,usb = <&usbotg2>;
+				status = "okay";
+			};
+
 			usbotg1: usb@02184000 {
 				compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
 						"fsl,imx27-usb";
@@ -726,7 +751,7 @@
 			};
 
 			usdhc1: usdhc@02190000 {
-				compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
+				compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc";
 				reg = <0x02190000 0x4000>;
 				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SLL_CLK_USDHC1>,
@@ -740,7 +765,7 @@
 			};
 
 			usdhc2: usdhc@02194000 {
-				compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
+				compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc";
 				reg = <0x02194000 0x4000>;
 				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SLL_CLK_USDHC2>,
@@ -754,7 +779,7 @@
 			};
 
 			usdhc3: usdhc@02198000 {
-				compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
+				compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc";
 				reg = <0x02198000 0x4000>;
 				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SLL_CLK_USDHC3>,
diff --git a/arch/arm/dts/imx6sx-14x14-val.dts b/arch/arm/dts/imx6sx-14x14-val.dts
new file mode 100644
index 00000000000..c4357eb5978
--- /dev/null
+++ b/arch/arm/dts/imx6sx-14x14-val.dts
@@ -0,0 +1,1374 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx6sx.dtsi"
+
+/ {
+	model = "i.MX6 SoloX 14x14 VAL Board";
+	compatible = "fsl,imx6sx-14x14-lpddr2-val", "fsl,imx6sx";
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm3 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+	};
+
+	clocks {
+	        codec_osc: codec_osc {
+		        #clock-cells = <0>;
+		        compatible = "fixed-clock";
+		        clock-frequency = <12000000>;
+		};
+	};
+
+	max7322_reset: max7322-reset {
+		compatible = "gpio-reset";
+		reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <1>;
+		#reset-cells = <0>;
+	};
+
+	pxp_v4l2_out {
+		compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
+		status = "okay";
+	};
+
+	regulators {
+		compatible = "simple-bus";
+
+		reg_3p3v: 3p3v {
+			compatible = "regulator-fixed";
+			regulator-name = "3P3V";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		reg_sdb_vmmc: sdb_vmmc{
+			compatible = "regulator-fixed";
+			regulator-name = "SD2_SPWR";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio2 11 GPIO_ACTIVE_LOW>;
+			off-on-delay-us = <20000>;
+		};
+
+		reg_usb_otg1_vbus: usb_otg1_vbus {
+			compatible = "regulator-fixed";
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 9 0>;
+			enable-active-high;
+		};
+
+		reg_usb_otg2_vbus: usb_otg2_vbus {
+			compatible = "regulator-fixed";
+			regulator-name = "usb_otg2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 12 0>;
+			enable-active-high;
+		};
+
+		reg_vref_3v3: regulator@0 {
+			compatible = "regulator-fixed";
+			regulator-name = "vref-3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+	};
+
+	memory {
+		reg = <0x80000000 0x40000000>;
+	};
+
+	sound {
+		compatible = "fsl,imx6sx-arm2-sgtl5000",
+			   "fsl,imx-audio-sgtl5000";
+		model = "imx6sx-arm2-sgtl5000";
+		cpu-dai = <&ssi1>;
+		audio-codec = <&codec>;
+		audio-routing =
+			"LINE_IN", "Line In Jack",
+			"Headphone Jack", "HP_OUT";
+		mux-int-port = <1>;
+		mux-ext-port = <4>;
+	};
+};
+
+&adc1 {
+	vref-supply = <&reg_vref_3v3>;
+	status = "okay";
+};
+
+&adc2 {
+	vref-supply = <&reg_vref_3v3>;
+	status = "okay";
+};
+
+&audmux {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_audmux_2>;
+       status = "okay";
+};
+
+&cpu0 {
+	operating-points = <
+		/* kHz    uV */
+		996000  1250000
+		792000  1175000
+		396000  1175000
+	>;
+	fsl,soc-operating-points = <
+		/* ARM kHz      SOC uV */
+		996000  1250000
+		792000  1175000
+		396000  1175000
+	>;
+	fsl,arm-soc-shared = <1>;
+};
+
+&reg_arm {
+	vin-supply = <&sw1a_reg>;
+	regulator-allow-bypass;
+};
+
+&reg_soc {
+	vin-supply = <&sw1a_reg>;
+	regulator-allow-bypass;
+};
+
+&ecspi4 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio7 4 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>;
+	status = "disabled"; /* pin conflict with USDHC3 */
+
+	flash: m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p32";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1_1>;
+	phy-mode = "rgmii";
+	phy-id = <1>;
+	fsl,num_tx_queues=<3>;
+	fsl,num_rx_queues=<3>;
+	pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>;
+	fsl,magic-packet;
+	status = "okay";
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2_1>;
+	phy-mode = "rgmii";
+	phy-id = <0>;
+	fsl,num_tx_queues=<3>;
+	fsl,num_rx_queues=<3>;
+	pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>;
+	fsl,magic-packet;
+	status = "okay";
+};
+
+&flexcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1_1>;
+	trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
+	trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+	trx-err-gpio = <&gpio4 24 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2_1>;
+	trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
+	trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+	trx-err-gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&gpc {
+	fsl,cpu_pdnscr_iso2sw = <0x1>;
+	fsl,cpu_pdnscr_iso = <0x1>;
+	fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "disabled"; /* pin conflict with qspi*/
+	nand-on-flash-bbt;
+	fsl,use-minimum-ecc;
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1_1>;
+	pinctrl-1 = <&pinctrl_i2c1_1_gpio>;
+	scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pfuze100@8 {
+		compatible = "fsl,pfuze200";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3b_reg: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2_1>;
+	pinctrl-1 = <&pinctrl_i2c2_1_gpio>;
+	scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	max7322_1: gpio@68 {
+		compatible = "maxim,max7322";
+		reg = <0x68>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		resets = <&max7322_reset>;
+	};
+
+	max7322_2: gpio@69 {
+		compatible = "maxim,max7322";
+		reg = <0x69>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		resets = <&max7322_reset>;
+	};
+
+	codec: sgtl5000@0a {
+		compatible = "fsl,sgtl5000";
+		reg = <0x0a>;
+		clocks = <&codec_osc>;
+		VDDA-supply = <&vgen4_reg>;
+		VDDIO-supply = <&reg_3p3v>;
+	};
+};
+
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3_1>;
+	pinctrl-1 = <&pinctrl_i2c3_1_gpio>;
+	scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c4_1>;
+	pinctrl-1 = <&pinctrl_i2c4_1_gpio>;
+	scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	hog {
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_KEY_COL0__GPIO2_IO_10		0x1f059
+				MX6SX_PAD_KEY_ROW0__GPIO2_IO_15		0x1f059
+				MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22     0x80000000
+				/* CAN1_2_EN */
+				MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25     0x17059
+				/* CAN1_2_STBY_B */
+				MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27     0x17059
+				/* CAN1_ERR_B */
+				MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24	0x17059
+				/* CAN2_ERR_B */
+				MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30     0x17059
+				/* SD2_PWROFF */
+				MX6SX_PAD_KEY_COL1__GPIO2_IO_11		0x17059
+			>;
+		};
+	};
+};
+
+&lcdif1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif_dat_0
+		     &pinctrl_lcdif_ctrl_0>;
+	display = <&display0>;
+	status = "okay";
+
+	display0: display@0 {
+		bits-per-pixel = <16>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+				clock-frequency = <33500000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <89>;
+				hfront-porch = <164>;
+				vback-porch = <23>;
+				vfront-porch = <10>;
+				hsync-len = <10>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&mlb {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_mlb_1>;
+	status = "disabled";/* pin conflict with usdhc2*/
+};
+
+&pwm3 {
+	#pwm-cells = <2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm3_0>;
+	status = "okay";
+};
+
+&pxp {
+	status = "okay";
+};
+
+&qspi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi2_1>;
+	status = "okay";
+	ddrsmp=<2>;
+
+	flash0: n25q256a@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		reg = <0>;
+	};
+
+	flash1: n25q256a@1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		reg = <1>;
+	};
+};
+
+&sai2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai2_1>;
+	status = "disabled";
+};
+
+&spdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spdif_1>;
+	status = "disabled";
+};
+
+&ssi1 {
+	fsl,mode = "i2s-slave";
+	status = "okay";
+};
+
+&snvs_poweroff {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2_1>;
+	status = "okay";
+};
+
+&usbh {
+	pinctrl-names = "idle", "active";
+	pinctrl-0 = <&pinctrl_usbh_1>;
+	pinctrl-1 = <&pinctrl_usbh_2>;
+	osc-clkgate-delay = <0x3>;
+	pad-supply = <&vgen1_reg>;
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg1_1>;
+	disable-over-current;
+	status = "okay";
+};
+
+&usbotg2 {
+	/*
+	 * Pin conflict with others, need to switch R580 & R579
+	 * to B and disable pwm3 to enable it.
+	 */
+	vbus-supply = <&reg_usb_otg2_vbus>;
+	disable-over-current;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg2_1>;
+	status = "disabled";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2_1>;
+	non-removable;
+	/* need hw rework to enable signal voltage switch */
+	no-1-8-v;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3_1>;
+	pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
+	bus-width = <8>;
+	cd-gpios = <&gpio2 10 0>;
+	wp-gpios = <&gpio2 15 0>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sdb_vmmc>;
+	status = "okay";
+};
+
+&usdhc4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc4_1>;
+	bus-width = <8>;
+	non-removable;
+	/* need hw rework to enable signal voltage switch */
+	no-1-8-v;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,wdog_b;
+};
+
+&iomuxc {
+	audmux {
+		pinctrl_audmux_1: audmuxgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC   0x130B0
+				MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS  0x130B0
+				MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD    0x120B0
+				MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD    0x130B0
+				MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK       0x130B0
+			>;
+		};
+
+		pinctrl_audmux_2: audmuxgrp-2 {
+			fsl,pins = <
+				MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 	 0x130b0
+				MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD     0x130b0
+				MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0
+				MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD  0x130b0
+			>;
+		};
+
+		pinctrl_audmux_3: audmux-3 {
+			fsl,pins = <
+				MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC    0x130b0
+				MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS   0x130b0
+				MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD  0x130b0
+			>;
+		};
+	};
+
+	ecspi4 {
+		pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD3_DATA2__GPIO7_IO_4  0x80000000
+			>;
+		};
+
+		pinctrl_ecspi4_1: ecspi4grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1
+				MX6SX_PAD_SD3_CMD__ECSPI4_MOSI   0x100b1
+				MX6SX_PAD_SD3_CLK__ECSPI4_SCLK   0x100b1
+			>;
+		};
+	};
+
+	csi {
+		pinctrl_csi_0: csigrp-0 {
+			fsl,pins = <
+				MX6SX_PAD_LCD1_DATA07__CSI1_MCLK	0x110b0
+				MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK	0x110b0
+				MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC	0x110b0
+				MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC	0x110b0
+				MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0	0x110b0
+				MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1	0x110b0
+				MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2	0x110b0
+				MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3	0x110b0
+				MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4	0x110b0
+				MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5	0x110b0
+				MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6	0x110b0
+				MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7	0x110b0
+				MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8	0x110b0
+				MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9	0x110b0
+				MX6SX_PAD_LCD1_RESET__GPIO3_IO_27	0x80000000
+				MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28	0x80000000
+			>;
+		};
+
+		pinctrl_csi_1: csigrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_MCLK__CSI1_MCLK		0x110b0
+				MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK	0x110b0
+				MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC		0x110b0
+				MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC		0x110b0
+				MX6SX_PAD_CSI_DATA00__CSI1_DATA_2	0x110b0
+				MX6SX_PAD_CSI_DATA01__CSI1_DATA_3	0x110b0
+				MX6SX_PAD_CSI_DATA02__CSI1_DATA_4	0x110b0
+				MX6SX_PAD_CSI_DATA03__CSI1_DATA_5	0x110b0
+				MX6SX_PAD_CSI_DATA04__CSI1_DATA_6	0x110b0
+				MX6SX_PAD_CSI_DATA05__CSI1_DATA_7	0x110b0
+				MX6SX_PAD_CSI_DATA06__CSI1_DATA_8	0x110b0
+				MX6SX_PAD_CSI_DATA07__CSI1_DATA_9	0x110b0
+
+				MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25	0x80000000
+				MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26	0x80000000
+			>;
+		};
+	};
+
+	enet1 {
+		pinctrl_enet1_1: enet1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
+				MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
+				MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b9
+				MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
+				MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
+				MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
+				MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
+				MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
+				MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
+				MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
+				MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
+				MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
+				MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
+				MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
+			>;
+		};
+
+		pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M	0x91
+			>;
+		};
+	};
+
+	enet2 {
+		pinctrl_enet2_1: enet2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
+				MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
+				MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
+				MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
+				MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
+				MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
+				MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
+				MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
+				MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
+				MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
+				MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
+				MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
+			>;
+		};
+	};
+
+	esai {
+		pinctrl_esai_1: esaigrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK  0x1b030
+				MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK   0x1b030
+				MX6SX_PAD_CSI_DATA01__ESAI_TX_FS    0x1b030
+				MX6SX_PAD_CSI_HSYNC__ESAI_TX0       0x1b030
+				MX6SX_PAD_CSI_DATA04__ESAI_TX1      0x1b030
+				MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3  0x1b030
+				MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2  0x1b030
+				MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK   0x1b030
+				MX6SX_PAD_CSI_DATA03__ESAI_RX_FS    0x1b030
+				MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0   0x1b030
+				MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1  0x1b030
+			>;
+		};
+
+		pinctrl_esai_2: esaigrp-2 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK   0x1b030
+				MX6SX_PAD_CSI_DATA01__ESAI_TX_FS    0x1b030
+				MX6SX_PAD_CSI_HSYNC__ESAI_TX0       0x1b030
+				MX6SX_PAD_CSI_DATA04__ESAI_TX1      0x1b030
+				MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3  0x1b030
+				MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2  0x1b030
+				MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK   0x1b030
+				MX6SX_PAD_CSI_DATA03__ESAI_RX_FS    0x1b030
+				MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0   0x1b030
+				MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1  0x1b030
+			>;
+		};
+	};
+
+	flexcan1 {
+		pinctrl_flexcan1_1: flexcan1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1B_DQS__CAN1_TX	0x1b020
+				MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX	0x1b020
+			>;
+		};
+	};
+
+	flexcan2 {
+		pinctrl_flexcan2_1: flexcan2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
+				MX6SX_PAD_QSPI1A_DQS__CAN2_TX	0x1b020
+			>;
+		};
+	};
+
+	gpmi-nand {
+		pinctrl_gpmi_nand_1: gpmi-nand-1 {
+			fsl,pins = <
+				MX6SX_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
+				MX6SX_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
+				MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
+				MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
+				MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
+				MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B     0xb0b1
+				MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
+				MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
+				MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
+				MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
+				MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
+				MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
+				MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
+				MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
+				MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
+				MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
+			>;
+		};
+	};
+
+	i2c1 {
+		pinctrl_i2c1_1: i2c1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO01__I2C1_SDA          0x4001b8b1
+				MX6SX_PAD_GPIO1_IO00__I2C1_SCL          0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c1_1_gpio: i2c1grp-1-gpio {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1        0x1b8b1
+				MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0        0x1b8b1
+			>;
+		};
+
+		pinctrl_i2c1_2: i2c1grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA01__I2C1_SDA          0x4001b8b1
+				MX6SX_PAD_CSI_DATA00__I2C1_SCL          0x4001b8b1
+			>;
+		};
+	};
+
+	i2c2 {
+		pinctrl_i2c2_1: i2c2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO03__I2C2_SDA          0x4001b8b1
+				MX6SX_PAD_GPIO1_IO02__I2C2_SCL          0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c2_1_gpio: i2c2grp-1-gpio {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3        0x1b8b1
+				MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2        0x1b8b1
+			>;
+		};
+	};
+
+	i2c3 {
+		pinctrl_i2c3_1: i2c3grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA        0x4001b8b1
+				MX6SX_PAD_KEY_COL4__I2C3_SCL            0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c3_1_gpio: i2c3grp-1-gpio {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9      0x1b8b1
+				MX6SX_PAD_KEY_COL4__GPIO2_IO_14         0x1b8b1
+			>;
+		};
+
+		pinctrl_i2c3_2: i2c3grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_KEY_ROW4__I2C3_SDA            0x4001b8b1
+				MX6SX_PAD_KEY_COL4__I2C3_SCL            0x4001b8b1
+			>;
+		};
+	};
+
+	i2c4 {
+		pinctrl_i2c4_1: i2c4grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA07__I2C4_SDA          0x4001b8b1
+				MX6SX_PAD_CSI_DATA06__I2C4_SCL          0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c4_1_gpio: i2c4grp-1-gpio {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA07__GPIO1_IO_21       0x1b8b1
+				MX6SX_PAD_CSI_DATA06__GPIO1_IO_20       0x1b8b1
+			>;
+		};
+
+		pinctrl_i2c4_2: i2c4grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_SD3_DATA1__I2C4_SDA           0x4001b8b1
+				MX6SX_PAD_SD3_DATA0__I2C4_SCL           0x4001b8b1
+			>;
+		};
+	};
+
+	lcdif1 {
+		pinctrl_lcdif_dat_0: lcdifdatgrp-0 {
+			fsl,pins = <
+				MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
+			>;
+		};
+
+		pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 {
+			fsl,pins = <
+				MX6SX_PAD_LCD1_CLK__LCDIF1_CLK	0x4001b0b0
+				MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
+				MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
+				MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
+				MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x1b0b0
+			>;
+		};
+	};
+
+	mlb {
+		pinctrl_mlb_1: mlbgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD2_DATA3__MLB_DATA	0x31
+				MX6SX_PAD_SD2_CLK__MLB_SIG	0x31
+				MX6SX_PAD_SD2_CMD__MLB_CLK	0x31
+			>;
+		};
+
+		pinctrl_mlb_2: mlbgrp-2 {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_RX_CLK__MLB_DATA	0x31
+				MX6SX_PAD_ENET2_CRS__MLB_SIG		0x31
+				MX6SX_PAD_ENET2_TX_CLK__MLB_CLK		0x31
+			>;
+		};
+	};
+
+	mqs {
+		pinctrl_mqs_1: mqsgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x80000000
+				MX6SX_PAD_SD2_CMD__MQS_LEFT 0x80000000
+			>;
+		};
+	};
+
+	pwm3 {
+		pinctrl_pwm3_0: pwm3grp-0 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0
+			>;
+		};
+
+		pinctrl_pwm3_1: pwm3grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
+			>;
+		};
+	};
+
+	pwm4 {
+		pinctrl_pwm4_0: pwm4grp-0 {
+			fsl,pins = <
+				MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
+			>;
+		};
+	};
+
+	qspi1 {
+		pinctrl_qspi1_1: qspi1grp_1 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0  0x70a1
+				MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1  0x70a1
+				MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2  0x70a1
+				MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3  0x70a1
+				MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK     0x70a1
+				MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B   0x70a1
+				MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0  0x70a1
+				MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1  0x70a1
+				MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2  0x70a1
+				MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3  0x70a1
+				MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK     0x70a1
+				MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B   0x70a1
+			>;
+		};
+	};
+
+	qspi2 {
+		pinctrl_qspi2_1: qspi2grp_1 {
+			fsl,pins = <
+				MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70a1
+				MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70a1
+				MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70a1
+				MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70a1
+				MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70a1
+				MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70a1
+				MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70a1
+				MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70a1
+				MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70a1
+				MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70a1
+				MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70a1
+				MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70a1
+			>;
+		};
+	};
+
+	sai1 {
+		pinctrl_sai1_1: sai1grp_1 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK     0x1b030
+				MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC     0x1b030
+				MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK     0x1b030
+				MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC     0x1b030
+				MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0    0x1b030
+				MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0    0x1b030
+			>;
+		};
+
+		pinctrl_sai1_2: sai1grp_2 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK     0x130B0
+				MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC     0x130B0
+				MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0    0x120B0
+				MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0    0x130B0
+				MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK      0x130B0
+			>;
+		};
+	};
+
+	sai2 {
+		pinctrl_sai2_1: sai2grp_1 {
+			fsl,pins = <
+				MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK       0x1b030
+				MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC       0x1b030
+				MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0     0x1b030
+				MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0     0x1b030
+			>;
+		};
+	};
+
+
+	spdif {
+		pinctrl_spdif_1: spdifgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT	0x1b0b0
+				MX6SX_PAD_ENET2_COL__SPDIF_IN		0x1b0b0
+			>;
+		};
+
+		pinctrl_spdif_2: spdifgrp-2 {
+			fsl,pins = <
+				MX6SX_PAD_SD4_DATA4__SPDIF_OUT		0x1b0b0
+			>;
+		};
+
+		pinctrl_spdif_3: spdifgrp-3 {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_COL__SPDIF_IN		0x1b0b0
+			>;
+		};
+	};
+
+	uart1 {
+		pinctrl_uart1_1: uart1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
+				MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
+			>;
+		};
+
+		pinctrl_uart1_2: uart1grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1
+				MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1
+			>;
+		};
+	};
+
+	uart2 {
+		pinctrl_uart2_1: uart2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
+				MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
+			>;
+		};
+
+		pinctrl_uart2_2: uart2grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1
+				MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1
+			>;
+		};
+	};
+
+	uart5 {
+		pinctrl_uart5_1: uart5grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_KEY_ROW3__UART5_RX    0x1b0b1
+				MX6SX_PAD_KEY_COL3__UART5_TX    0x1b0b1
+				MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
+				MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
+			>;
+		};
+
+		pinctrl_uart5dte_1: uart5dtegrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_KEY_ROW3__UART5_TX	0x1b0b1
+				MX6SX_PAD_KEY_COL3__UART5_RX    0x1b0b1
+				MX6SX_PAD_KEY_ROW2__UART5_RTS_B	0x1b0b1
+				MX6SX_PAD_KEY_COL2__UART5_CTS_B	0x1b0b1
+			>;
+		};
+	};
+
+	usbh {
+		pinctrl_usbh_1: usbhgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_USB_H_STROBE__USB_H_STROBE	0x40013030
+				MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030
+			>;
+		};
+
+		pinctrl_usbh_2: usbhgrp-2 {
+			fsl,pins = <
+				MX6SX_PAD_USB_H_STROBE__USB_H_STROBE	0x40017030
+			>;
+		};
+	};
+
+	usbotg1 {
+		pinctrl_usbotg1_1: usbotg1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
+			>;
+		};
+
+		pinctrl_usbotg1_2: usbotg1grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059
+			>;
+		};
+
+		pinctrl_usbotg1_3: usbotg1grp-3 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059
+			>;
+		};
+	};
+
+	usbotg2 {
+		pinctrl_usbotg2_1: usbotg2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059
+			>;
+		};
+
+		pinctrl_usbotg2_2: usbotg2grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059
+			>;
+		};
+
+		pinctrl_usbotg2_3: usbotg2grp-3 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059
+			>;
+		};
+	};
+
+	usdhc1 {
+		pinctrl_usdhc1_1: usdhc1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD1_CMD__USDHC1_CMD     0x17059
+				MX6SX_PAD_SD1_CLK__USDHC1_CLK     0x10059
+				MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+				MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+				MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+				MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+			>;
+		};
+	};
+
+	usdhc2 {
+		pinctrl_usdhc2_1: usdhc2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD2_CMD__USDHC2_CMD     0x17059
+				MX6SX_PAD_SD2_CLK__USDHC2_CLK     0x10059
+				MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
+				MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
+				MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
+				MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
+			>;
+		};
+	};
+
+	usdhc3 {
+		pinctrl_usdhc3_1: usdhc3grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD3_CMD__USDHC3_CMD	  0x17059
+				MX6SX_PAD_SD3_CLK__USDHC3_CLK	  0x10059
+				MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
+				MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
+				MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
+				MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
+				MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
+				MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
+				MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
+				MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
+			>;
+		};
+
+		pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
+			fsl,pins = <
+				MX6SX_PAD_SD3_CMD__USDHC3_CMD	  0x170b9
+				MX6SX_PAD_SD3_CLK__USDHC3_CLK	  0x100b9
+				MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
+				MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
+				MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
+				MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
+				MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
+				MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
+				MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
+				MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
+			>;
+		};
+
+		pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
+			fsl,pins = <
+				MX6SX_PAD_SD3_CMD__USDHC3_CMD	  0x170f9
+				MX6SX_PAD_SD3_CLK__USDHC3_CLK	  0x100f9
+				MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
+				MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
+				MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
+				MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
+				MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
+				MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
+				MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
+				MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
+			>;
+		};
+
+	};
+
+	usdhc4 {
+			pinctrl_usdhc4_1: usdhc4grp-1 {
+				fsl,pins = <
+					MX6SX_PAD_SD4_CMD__USDHC4_CMD     0x17059
+					MX6SX_PAD_SD4_CLK__USDHC4_CLK     0x10059
+					MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
+					MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
+					MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
+					MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
+					MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
+					MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
+					MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
+					MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
+				>;
+			};
+
+			pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz {
+				fsl,pins = <
+					MX6SX_PAD_SD4_CMD__USDHC4_CMD     0x170b9
+					MX6SX_PAD_SD4_CLK__USDHC4_CLK     0x100b9
+					MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
+					MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
+					MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
+					MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
+					MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
+					MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
+					MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
+					MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
+				>;
+			};
+
+			pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz {
+				fsl,pins = <
+					MX6SX_PAD_SD4_CMD__USDHC4_CMD     0x170f9
+					MX6SX_PAD_SD4_CLK__USDHC4_CLK     0x100f9
+					MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
+					MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
+					MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
+					MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
+					MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
+					MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
+					MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
+					MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
+				>;
+			};
+
+			pinctrl_usdhc4_2: usdhc4grp-2 {
+				fsl,pins = <
+					MX6SX_PAD_SD4_CMD__USDHC4_CMD     0x17059
+					MX6SX_PAD_SD4_CLK__USDHC4_CLK     0x10059
+					MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
+					MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
+					MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
+					MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
+				>;
+			};
+
+			pinctrl_usdhc4_3: usdhc4grp-3 {
+				fsl,pins = <
+					MX6SX_PAD_SD4_CMD__USDHC4_CMD     0x17071
+					MX6SX_PAD_SD4_CLK__USDHC4_CLK     0x10071
+					MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071
+					MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071
+					MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071
+					MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071
+					MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071
+					MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071
+					MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071
+					MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071
+				>;
+			};
+
+	};
+
+	wdog {
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0
+			>;
+		};
+	};
+
+	weim {
+		pinctrl_weim_cs0_1: weim_cs0grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_NAND_ALE__WEIM_CS0_B       0xb0b1
+			>;
+		};
+
+		pinctrl_weim_nor_1: weim_norgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_NAND_CE1_B__WEIM_OE        0xb0b1
+				MX6SX_PAD_NAND_RE_B__WEIM_RW         0xb0b1
+				MX6SX_PAD_NAND_WE_B__WEIM_WAIT       0xb060
+				/* data */
+				MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0   0x1b0b0
+				MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1  0x1b0b0
+				MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2  0x1b0b0
+				MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3  0x1b0b0
+				MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4  0x1b0b0
+				MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5  0x1b0b0
+				MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6  0x1b0b0
+				MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7    0x1b0b0
+				MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8   0x1b0b0
+				MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9  0x1b0b0
+				MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0
+				MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0
+				MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0
+				MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0
+				MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0
+				MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15   0x1b0b0
+				/* address */
+				MX6SX_PAD_NAND_DATA00__WEIM_AD_0     0xb0b1
+				MX6SX_PAD_NAND_DATA01__WEIM_AD_1     0xb0b1
+				MX6SX_PAD_NAND_DATA02__WEIM_AD_2     0xb0b1
+				MX6SX_PAD_NAND_DATA03__WEIM_AD_3     0xb0b1
+				MX6SX_PAD_NAND_DATA04__WEIM_AD_4     0xb0b1
+				MX6SX_PAD_NAND_DATA05__WEIM_AD_5     0xb0b1
+				MX6SX_PAD_NAND_DATA06__WEIM_AD_6     0xb0b1
+				MX6SX_PAD_NAND_DATA07__WEIM_AD_7     0xb0b1
+				MX6SX_PAD_LCD1_DATA08__WEIM_AD_8     0xb0b1
+				MX6SX_PAD_LCD1_DATA09__WEIM_AD_9     0xb0b1
+				MX6SX_PAD_LCD1_DATA10__WEIM_AD_10    0xb0b1
+				MX6SX_PAD_LCD1_DATA11__WEIM_AD_11    0xb0b1
+				MX6SX_PAD_LCD1_DATA12__WEIM_AD_12    0xb0b1
+				MX6SX_PAD_LCD1_DATA13__WEIM_AD_13    0xb0b1
+				MX6SX_PAD_LCD1_DATA14__WEIM_AD_14    0xb0b1
+				MX6SX_PAD_LCD1_DATA15__WEIM_AD_15    0xb0b1
+				MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16  0xb0b1
+				MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17  0xb0b1
+				MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18  0xb0b1
+				MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19  0xb0b1
+				MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20  0xb0b1
+				MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21  0xb0b1
+				MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22  0xb0b1
+				MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24  0xb0b1
+				MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25  0xb0b1
+				MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26  0xb0b1
+			>;
+		};
+	};
+};
diff --git a/arch/arm/dts/imx6sx-17x17-val-ecspi.dts b/arch/arm/dts/imx6sx-17x17-val-ecspi.dts
new file mode 100644
index 00000000000..36875a4aa90
--- /dev/null
+++ b/arch/arm/dts/imx6sx-17x17-val-ecspi.dts
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6sx-17x17-val.dts"
+
+&usdhc3 {
+	status = "disabled";
+};
+
+&ecspi4 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio7 4 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>;
+	status = "okay"; /* pin conflict with USDHC3 */
+
+	flash: m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p32", "jedec,spi-nor";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
\ No newline at end of file
diff --git a/arch/arm/dts/imx6sx-17x17-val-gpmi-weim.dts b/arch/arm/dts/imx6sx-17x17-val-gpmi-weim.dts
new file mode 100644
index 00000000000..d089fd6c810
--- /dev/null
+++ b/arch/arm/dts/imx6sx-17x17-val-gpmi-weim.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6sx-17x17-val.dts"
+
+&qspi2 {
+	status = "disabled";
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "okay"; /* pin conflict with qspi*/
+	nand-on-flash-bbt;
+	fsl,use-minimum-ecc;
+};
diff --git a/arch/arm/dts/imx6sx-17x17-val.dts b/arch/arm/dts/imx6sx-17x17-val.dts
new file mode 100644
index 00000000000..58550ce9da1
--- /dev/null
+++ b/arch/arm/dts/imx6sx-17x17-val.dts
@@ -0,0 +1,1318 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx6sx.dtsi"
+
+/ {
+	model = "i.MX6 SoloX 17x17 VAL Board";
+	compatible = "fsl,imx6sx-17x17-val", "fsl,imx6sx";
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm3 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+	};
+
+	clocks {
+	        codec_osc: codec_osc {
+		        #clock-cells = <0>;
+		        compatible = "fixed-clock";
+		        clock-frequency = <12000000>;
+		};
+	};
+
+	max7322_reset: max7322-reset {
+		compatible = "gpio-reset";
+		reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <1>;
+		#reset-cells = <0>;
+	};
+
+	pxp_v4l2_out {
+		compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
+		status = "okay";
+	};
+
+	regulators {
+		compatible = "simple-bus";
+
+		reg_3p3v: 3p3v {
+			compatible = "regulator-fixed";
+			regulator-name = "3P3V";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		reg_sdb_vmmc: sdb_vmmc{
+			compatible = "regulator-fixed";
+			regulator-name = "SD2_SPWR";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio2 11 GPIO_ACTIVE_LOW>;
+			off-on-delay-us = <20000>;
+		};
+
+		reg_usb_otg1_vbus: usb_otg1_vbus {
+			compatible = "regulator-fixed";
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 9 0>;
+			enable-active-high;
+		};
+
+		reg_usb_otg2_vbus: usb_otg2_vbus {
+			compatible = "regulator-fixed";
+			regulator-name = "usb_otg2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 12 0>;
+			enable-active-high;
+		};
+
+		reg_vref_3v3: regulator@0 {
+			compatible = "regulator-fixed";
+			regulator-name = "vref-3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+	};
+
+	memory {
+		reg = <0x80000000 0x40000000>;
+	};
+
+	sound {
+		compatible = "fsl,imx6sx-arm2-sgtl5000",
+			   "fsl,imx-audio-sgtl5000";
+		model = "imx6sx-arm2-sgtl5000";
+		cpu-dai = <&ssi1>;
+		audio-codec = <&codec>;
+		audio-routing =
+			"LINE_IN", "Line In Jack",
+			"Headphone Jack", "HP_OUT";
+		mux-int-port = <1>;
+		mux-ext-port = <4>;
+	};
+};
+
+&adc1 {
+	vref-supply = <&reg_vref_3v3>;
+	status = "okay";
+};
+
+&adc2 {
+	vref-supply = <&reg_vref_3v3>;
+	status = "okay";
+};
+
+&audmux {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_audmux_2>;
+       status = "okay";
+};
+
+&cpu0 {
+	operating-points = <
+		/* kHz    uV */
+		996000  1250000
+		792000  1175000
+		396000  1175000
+	>;
+	fsl,soc-operating-points = <
+		/* ARM kHz      SOC uV */
+		996000  1250000
+		792000  1175000
+		396000  1175000
+	>;
+	fsl,arm-soc-shared = <1>;
+};
+
+&reg_arm {
+	vin-supply = <&sw1a_reg>;
+	regulator-allow-bypass;
+};
+
+&reg_soc {
+	vin-supply = <&sw1a_reg>;
+	regulator-allow-bypass;
+};
+
+&ecspi4 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio7 4 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>;
+	status = "disabled"; /* pin conflict with USDHC3 */
+
+	flash: m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p32";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1_1>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy1>;
+	pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+	};
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2_1>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy0>;
+	pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>;
+	fsl,magic-packet;
+	status = "okay";
+};
+
+&flexcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1_1>;
+	trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
+	trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+	trx-err-gpio = <&gpio4 24 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2_1>;
+	trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
+	trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+	trx-err-gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&gpc {
+	fsl,cpu_pupscr_sw2iso = <0x2>;
+	fsl,cpu_pupscr_sw = <0x1>;
+	fsl,cpu_pdnscr_iso2sw = <0x1>;
+	fsl,cpu_pdnscr_iso = <0x1>;
+	fsl,wdog-reset = <1>; /* watchdog select of reset source */
+	fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1_1>;
+	pinctrl-1 = <&pinctrl_i2c1_1_gpio>;
+	scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pfuze100@8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3b_reg: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2_1>;
+	pinctrl-1 = <&pinctrl_i2c2_1_gpio>;
+	scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	max7322_1: gpio@68 {
+		compatible = "maxim,max7322";
+		reg = <0x68>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		resets = <&max7322_reset>;
+	};
+
+	max7322_2: gpio@69 {
+		compatible = "maxim,max7322";
+		reg = <0x69>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		resets = <&max7322_reset>;
+	};
+
+	codec: sgtl5000@0a {
+		compatible = "fsl,sgtl5000";
+		reg = <0x0a>;
+		clocks = <&codec_osc>;
+		VDDA-supply = <&vgen4_reg>;
+		VDDIO-supply = <&reg_3p3v>;
+	};
+};
+
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3_1>;
+	pinctrl-1 = <&pinctrl_i2c3_1_gpio>;
+	scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c4_1>;
+	pinctrl-1 = <&pinctrl_i2c4_1_gpio>;
+	scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	hog {
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_KEY_COL0__GPIO2_IO_10		0x1f059
+				MX6SX_PAD_KEY_ROW0__GPIO2_IO_15		0x1f059
+				MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22     0x80000000
+				/* CAN1_2_EN */
+				MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25     0x17059
+				/* CAN1_2_STBY_B */
+				MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27     0x17059
+				/* CAN1_ERR_B */
+				MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24	0x17059
+				/* CAN2_ERR_B */
+				MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30     0x17059
+				/* SD2_PWROFF */
+				MX6SX_PAD_KEY_COL1__GPIO2_IO_11		0x17059
+				/* WDOG_B reset */
+				MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY	0x10b0
+			>;
+		};
+	};
+};
+
+&lcdif1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif_dat_0
+		     &pinctrl_lcdif_ctrl_0>;
+	display = <&display0>;
+	status = "okay";
+
+	display0: display@0 {
+		bits-per-pixel = <16>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+				clock-frequency = <33500000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <89>;
+				hfront-porch = <164>;
+				vback-porch = <23>;
+				vfront-porch = <10>;
+				hsync-len = <10>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&mlb {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_mlb_1>;
+	status = "disabled";/* pin conflict with usdhc2*/
+};
+
+&pwm3 {
+	#pwm-cells = <2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm3_0>;
+	status = "okay";
+};
+
+&pxp {
+	status = "okay";
+};
+
+&qspi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi2_1>;
+	status = "okay";
+	ddrsmp=<2>;
+
+	flash0: n25q256a@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		reg = <0>;
+	};
+
+	flash1: n25q256a@1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		reg = <1>;
+	};
+};
+
+&sai2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai2_1>;
+	status = "disabled";
+};
+
+&spdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spdif_1>;
+	status = "disabled";
+};
+
+&ssi1 {
+	fsl,mode = "i2s-slave";
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2_1>;
+	status = "okay";
+};
+
+&usbh {
+	pinctrl-names = "idle", "active";
+	pinctrl-0 = <&pinctrl_usbh_1>;
+	pinctrl-1 = <&pinctrl_usbh_2>;
+	osc-clkgate-delay = <0x3>;
+	pad-supply = <&vgen1_reg>;
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg1_1>;
+	disable-over-current;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usbotg2 {
+	/*
+	 * Pin conflict with others, need to switch R580 & R579
+	 * to B and disable pwm3 to enable it.
+	 */
+	vbus-supply = <&reg_usb_otg2_vbus>;
+	disable-over-current;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg2_1>;
+	status = "disabled";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2_1>;
+	non-removable;
+	/* need hw rework to enable signal voltage switch */
+	no-1-8-v;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3_1>;
+	pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
+	bus-width = <8>;
+	cd-gpios = <&gpio2 10 0>;
+	wp-gpios = <&gpio2 15 0>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sdb_vmmc>;
+	status = "okay";
+};
+
+&usdhc4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc4_1>;
+	bus-width = <8>;
+	non-removable;
+	/* need hw rework to enable signal voltage switch */
+	no-1-8-v;
+	status = "okay";
+};
+
+&iomuxc {
+	audmux {
+		pinctrl_audmux_1: audmuxgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC   0x130B0
+				MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS  0x130B0
+				MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD    0x120B0
+				MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD    0x130B0
+				MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK       0x130B0
+			>;
+		};
+
+		pinctrl_audmux_2: audmuxgrp-2 {
+			fsl,pins = <
+				MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 	 0x130b0
+				MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD     0x130b0
+				MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0
+				MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD  0x130b0
+			>;
+		};
+	};
+
+	ecspi4 {
+		pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD3_DATA2__GPIO7_IO_4  0x80000000
+			>;
+		};
+
+		pinctrl_ecspi4_1: ecspi4grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1
+				MX6SX_PAD_SD3_CMD__ECSPI4_MOSI   0x100b1
+				MX6SX_PAD_SD3_CLK__ECSPI4_SCLK   0x100b1
+			>;
+		};
+	};
+
+	canfd1 {
+		pinctrl_canfd1_1: canfd1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1B_DQS__CANFD_TX1		0x1b0b0
+				MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1	0x1b0b0
+			>;
+		};
+	};
+
+	canfd2 {
+		pinctrl_canfd2_1: canfd2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2	0x1b0b0
+				MX6SX_PAD_QSPI1A_DQS__CANFD_TX2		0x1b0b0
+			>;
+		};
+	};
+
+	csi {
+		pinctrl_csi_0: csigrp-0 {
+			fsl,pins = <
+				MX6SX_PAD_LCD1_DATA07__CSI1_MCLK	0x110b0
+				MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK	0x110b0
+				MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC	0x110b0
+				MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC	0x110b0
+				MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0	0x110b0
+				MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1	0x110b0
+				MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2	0x110b0
+				MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3	0x110b0
+				MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4	0x110b0
+				MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5	0x110b0
+				MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6	0x110b0
+				MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7	0x110b0
+				MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8	0x110b0
+				MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9	0x110b0
+				MX6SX_PAD_LCD1_RESET__GPIO3_IO_27	0x80000000
+				MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28	0x80000000
+			>;
+		};
+
+		pinctrl_csi_1: csigrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_MCLK__CSI1_MCLK		0x110b0
+				MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK	0x110b0
+				MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC		0x110b0
+				MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC		0x110b0
+				MX6SX_PAD_CSI_DATA00__CSI1_DATA_2	0x110b0
+				MX6SX_PAD_CSI_DATA01__CSI1_DATA_3	0x110b0
+				MX6SX_PAD_CSI_DATA02__CSI1_DATA_4	0x110b0
+				MX6SX_PAD_CSI_DATA03__CSI1_DATA_5	0x110b0
+				MX6SX_PAD_CSI_DATA04__CSI1_DATA_6	0x110b0
+				MX6SX_PAD_CSI_DATA05__CSI1_DATA_7	0x110b0
+				MX6SX_PAD_CSI_DATA06__CSI1_DATA_8	0x110b0
+				MX6SX_PAD_CSI_DATA07__CSI1_DATA_9	0x110b0
+
+				MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25	0x80000000
+				MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26	0x80000000
+			>;
+		};
+	};
+
+	enet1 {
+		pinctrl_enet1_1: enet1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
+				MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
+				MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b9
+				MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
+				MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
+				MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
+				MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
+				MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
+				MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
+				MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
+				MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
+				MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
+				MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
+				MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
+			>;
+		};
+
+		pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M	0x91
+			>;
+		};
+	};
+
+	enet2 {
+		pinctrl_enet2_1: enet2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
+				MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
+				MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
+				MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
+				MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
+				MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
+				MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
+				MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
+				MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
+				MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
+				MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
+				MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
+			>;
+		};
+	};
+
+	esai {
+		pinctrl_esai_1: esaigrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK  0x1b030
+				MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK   0x1b030
+				MX6SX_PAD_CSI_DATA01__ESAI_TX_FS    0x1b030
+				MX6SX_PAD_CSI_HSYNC__ESAI_TX0       0x1b030
+				MX6SX_PAD_CSI_DATA04__ESAI_TX1      0x1b030
+				MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3  0x1b030
+				MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2  0x1b030
+				MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK   0x1b030
+				MX6SX_PAD_CSI_DATA03__ESAI_RX_FS    0x1b030
+				MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0   0x1b030
+				MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1  0x1b030
+			>;
+		};
+	};
+
+	flexcan1 {
+		pinctrl_flexcan1_1: flexcan1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1B_DQS__CAN1_TX	0x1b020
+				MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX	0x1b020
+			>;
+		};
+	};
+
+	flexcan2 {
+		pinctrl_flexcan2_1: flexcan2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
+				MX6SX_PAD_QSPI1A_DQS__CAN2_TX	0x1b020
+			>;
+		};
+	};
+
+	gpmi-nand {
+		pinctrl_gpmi_nand_1: gpmi-nand-1 {
+			fsl,pins = <
+				MX6SX_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
+				MX6SX_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
+				MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
+				MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
+				MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
+				MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B     0xb0b1
+				MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
+				MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
+				MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
+				MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
+				MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
+				MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
+				MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
+				MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
+				MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
+				MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
+			>;
+		};
+	};
+
+	i2c1 {
+		pinctrl_i2c1_1: i2c1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO01__I2C1_SDA          0x4001b8b1
+				MX6SX_PAD_GPIO1_IO00__I2C1_SCL          0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c1_1_gpio: i2c1grp-1-gpio {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1        0x1b8b1
+				MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0        0x1b8b1
+			>;
+		};
+
+		pinctrl_i2c1_2: i2c1grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA01__I2C1_SDA          0x4001b8b1
+				MX6SX_PAD_CSI_DATA00__I2C1_SCL          0x4001b8b1
+			>;
+		};
+	};
+
+	i2c2 {
+		pinctrl_i2c2_1: i2c2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO03__I2C2_SDA          0x4001b8b1
+				MX6SX_PAD_GPIO1_IO02__I2C2_SCL          0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c2_1_gpio: i2c2grp-1-gpio {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3        0x1b8b1
+				MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2        0x1b8b1
+			>;
+		};
+	};
+
+	i2c3 {
+		pinctrl_i2c3_1: i2c3grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA        0x4001b8b1
+				MX6SX_PAD_KEY_COL4__I2C3_SCL            0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c3_1_gpio: i2c3grp-1-gpio {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9      0x1b8b1
+				MX6SX_PAD_KEY_COL4__GPIO2_IO_14         0x1b8b1
+			>;
+		};
+
+		pinctrl_i2c3_2: i2c3grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_KEY_ROW4__I2C3_SDA            0x4001b8b1
+				MX6SX_PAD_KEY_COL4__I2C3_SCL            0x4001b8b1
+			>;
+		};
+	};
+
+	i2c4 {
+		pinctrl_i2c4_1: i2c4grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA07__I2C4_SDA          0x4001b8b1
+				MX6SX_PAD_CSI_DATA06__I2C4_SCL          0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c4_1_gpio: i2c4grp-1-gpio {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA07__GPIO1_IO_21       0x1b8b1
+				MX6SX_PAD_CSI_DATA06__GPIO1_IO_20       0x1b8b1
+			>;
+		};
+
+		pinctrl_i2c4_2: i2c4grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_SD3_DATA1__I2C4_SDA           0x4001b8b1
+				MX6SX_PAD_SD3_DATA0__I2C4_SCL           0x4001b8b1
+			>;
+		};
+	};
+
+	lcdif1 {
+		pinctrl_lcdif_dat_0: lcdifdatgrp-0 {
+			fsl,pins = <
+				MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
+			>;
+		};
+
+		pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 {
+			fsl,pins = <
+				MX6SX_PAD_LCD1_CLK__LCDIF1_CLK	0x4001b0b0
+				MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
+				MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
+				MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
+				MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x1b0b0
+			>;
+		};
+	};
+
+	mlb {
+		pinctrl_mlb_1: mlbgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD2_DATA3__MLB_DATA	0x31
+				MX6SX_PAD_SD2_CLK__MLB_SIG	0x31
+				MX6SX_PAD_SD2_CMD__MLB_CLK	0x31
+			>;
+		};
+	};
+
+	pwm3 {
+		pinctrl_pwm3_0: pwm3grp-0 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0
+			>;
+		};
+
+		pinctrl_pwm3_1: pwm3grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
+			>;
+		};
+	};
+
+	pwm4 {
+		pinctrl_pwm4_0: pwm4grp-0 {
+			fsl,pins = <
+				MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
+			>;
+		};
+	};
+
+	qspi2 {
+		pinctrl_qspi2_1: qspi2grp_1 {
+			fsl,pins = <
+				MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70a1
+				MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70a1
+				MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70a1
+				MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70a1
+				MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70a1
+				MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70a1
+				MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70a1
+				MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70a1
+				MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70a1
+				MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70a1
+				MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70a1
+				MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70a1
+			>;
+		};
+	};
+
+	sai1 {
+		pinctrl_sai1_1: sai1grp_1 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK     0x1b030
+				MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC     0x1b030
+				MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK     0x1b030
+				MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC     0x1b030
+				MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0    0x1b030
+				MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0    0x1b030
+			>;
+		};
+
+		pinctrl_sai1_2: sai1grp_2 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK     0x130B0
+				MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC     0x130B0
+				MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0    0x120B0
+				MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0    0x130B0
+				MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK      0x130B0
+			>;
+		};
+	};
+
+	sai2 {
+		pinctrl_sai2_1: sai2grp_1 {
+			fsl,pins = <
+				MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK       0x1b030
+				MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC       0x1b030
+				MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0     0x1b030
+				MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0     0x1b030
+			>;
+		};
+	};
+
+
+	spdif {
+		pinctrl_spdif_1: spdifgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT	0x1b0b0
+				MX6SX_PAD_ENET2_COL__SPDIF_IN		0x1b0b0
+			>;
+		};
+
+		pinctrl_spdif_2: spdifgrp-2 {
+			fsl,pins = <
+				MX6SX_PAD_SD4_DATA4__SPDIF_OUT		0x1b0b0
+			>;
+		};
+	};
+
+	uart1 {
+		pinctrl_uart1_1: uart1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
+				MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
+			>;
+		};
+
+		pinctrl_uart1_2: uart1grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1
+				MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1
+			>;
+		};
+	};
+
+	uart2 {
+		pinctrl_uart2_1: uart2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
+				MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
+			>;
+		};
+
+		pinctrl_uart2_2: uart2grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1
+				MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1
+			>;
+		};
+	};
+
+	uart5 {
+		pinctrl_uart5_1: uart5grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_KEY_ROW3__UART5_RX    0x1b0b1
+				MX6SX_PAD_KEY_COL3__UART5_TX    0x1b0b1
+				MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
+				MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
+			>;
+		};
+
+		pinctrl_uart5dte_1: uart5dtegrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_KEY_ROW3__UART5_TX	0x1b0b1
+				MX6SX_PAD_KEY_COL3__UART5_RX    0x1b0b1
+				MX6SX_PAD_KEY_ROW2__UART5_RTS_B	0x1b0b1
+				MX6SX_PAD_KEY_COL2__UART5_CTS_B	0x1b0b1
+			>;
+		};
+	};
+
+	usbh {
+		pinctrl_usbh_1: usbhgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_USB_H_STROBE__USB_H_STROBE	0x40013030
+				MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030
+			>;
+		};
+
+		pinctrl_usbh_2: usbhgrp-2 {
+			fsl,pins = <
+				MX6SX_PAD_USB_H_STROBE__USB_H_STROBE	0x40017030
+			>;
+		};
+	};
+
+	usbotg1 {
+		pinctrl_usbotg1_1: usbotg1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
+			>;
+		};
+
+		pinctrl_usbotg1_2: usbotg1grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059
+			>;
+		};
+
+		pinctrl_usbotg1_3: usbotg1grp-3 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059
+			>;
+		};
+	};
+
+	usbotg2 {
+		pinctrl_usbotg2_1: usbotg2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059
+			>;
+		};
+
+		pinctrl_usbotg2_2: usbotg2grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059
+			>;
+		};
+
+		pinctrl_usbotg2_3: usbotg2grp-3 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059
+			>;
+		};
+	};
+
+	usdhc1 {
+		pinctrl_usdhc1_1: usdhc1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD1_CMD__USDHC1_CMD     0x17059
+				MX6SX_PAD_SD1_CLK__USDHC1_CLK     0x10059
+				MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+				MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+				MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+				MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+			>;
+		};
+	};
+
+	usdhc2 {
+		pinctrl_usdhc2_1: usdhc2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD2_CMD__USDHC2_CMD     0x17059
+				MX6SX_PAD_SD2_CLK__USDHC2_CLK     0x10059
+				MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
+				MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
+				MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
+				MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
+			>;
+		};
+	};
+
+	usdhc3 {
+		pinctrl_usdhc3_1: usdhc3grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD3_CMD__USDHC3_CMD	  0x17059
+				MX6SX_PAD_SD3_CLK__USDHC3_CLK	  0x10059
+				MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
+				MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
+				MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
+				MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
+				MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
+				MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
+				MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
+				MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
+			>;
+		};
+
+		pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
+			fsl,pins = <
+				MX6SX_PAD_SD3_CMD__USDHC3_CMD	  0x170b9
+				MX6SX_PAD_SD3_CLK__USDHC3_CLK	  0x100b9
+				MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
+				MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
+				MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
+				MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
+				MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
+				MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
+				MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
+				MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
+			>;
+		};
+
+		pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
+			fsl,pins = <
+				MX6SX_PAD_SD3_CMD__USDHC3_CMD	  0x170f9
+				MX6SX_PAD_SD3_CLK__USDHC3_CLK	  0x100f9
+				MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
+				MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
+				MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
+				MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
+				MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
+				MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
+				MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
+				MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
+			>;
+		};
+
+	};
+
+	usdhc4 {
+			pinctrl_usdhc4_1: usdhc4grp-1 {
+				fsl,pins = <
+					MX6SX_PAD_SD4_CMD__USDHC4_CMD     0x17059
+					MX6SX_PAD_SD4_CLK__USDHC4_CLK     0x10059
+					MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
+					MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
+					MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
+					MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
+					MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
+					MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
+					MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
+					MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
+				>;
+			};
+
+			pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz {
+				fsl,pins = <
+					MX6SX_PAD_SD4_CMD__USDHC4_CMD     0x170b9
+					MX6SX_PAD_SD4_CLK__USDHC4_CLK     0x100b9
+					MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
+					MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
+					MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
+					MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
+					MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
+					MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
+					MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
+					MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
+				>;
+			};
+
+			pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz {
+				fsl,pins = <
+					MX6SX_PAD_SD4_CMD__USDHC4_CMD     0x170f9
+					MX6SX_PAD_SD4_CLK__USDHC4_CLK     0x100f9
+					MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
+					MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
+					MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
+					MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
+					MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
+					MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
+					MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
+					MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
+				>;
+			};
+
+			pinctrl_usdhc4_2: usdhc4grp-2 {
+				fsl,pins = <
+					MX6SX_PAD_SD4_CMD__USDHC4_CMD     0x17059
+					MX6SX_PAD_SD4_CLK__USDHC4_CLK     0x10059
+					MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
+					MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
+					MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
+					MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
+				>;
+			};
+
+	};
+
+	weim {
+		pinctrl_weim_cs0_1: weim_cs0grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_NAND_ALE__WEIM_CS0_B       0xb0b1
+			>;
+		};
+
+		pinctrl_weim_nor_1: weim_norgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_NAND_CE1_B__WEIM_OE        0xb0b1
+				MX6SX_PAD_NAND_RE_B__WEIM_RW         0xb0b1
+				MX6SX_PAD_NAND_WE_B__WEIM_WAIT       0xb060
+				/* data */
+				MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0   0x1b0b0
+				MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1  0x1b0b0
+				MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2  0x1b0b0
+				MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3  0x1b0b0
+				MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4  0x1b0b0
+				MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5  0x1b0b0
+				MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6  0x1b0b0
+				MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7    0x1b0b0
+				MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8   0x1b0b0
+				MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9  0x1b0b0
+				MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0
+				MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0
+				MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0
+				MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0
+				MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0
+				MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15   0x1b0b0
+				/* address */
+				MX6SX_PAD_NAND_DATA00__WEIM_AD_0     0xb0b1
+				MX6SX_PAD_NAND_DATA01__WEIM_AD_1     0xb0b1
+				MX6SX_PAD_NAND_DATA02__WEIM_AD_2     0xb0b1
+				MX6SX_PAD_NAND_DATA03__WEIM_AD_3     0xb0b1
+				MX6SX_PAD_NAND_DATA04__WEIM_AD_4     0xb0b1
+				MX6SX_PAD_NAND_DATA05__WEIM_AD_5     0xb0b1
+				MX6SX_PAD_NAND_DATA06__WEIM_AD_6     0xb0b1
+				MX6SX_PAD_NAND_DATA07__WEIM_AD_7     0xb0b1
+				MX6SX_PAD_LCD1_DATA08__WEIM_AD_8     0xb0b1
+				MX6SX_PAD_LCD1_DATA09__WEIM_AD_9     0xb0b1
+				MX6SX_PAD_LCD1_DATA10__WEIM_AD_10    0xb0b1
+				MX6SX_PAD_LCD1_DATA11__WEIM_AD_11    0xb0b1
+				MX6SX_PAD_LCD1_DATA12__WEIM_AD_12    0xb0b1
+				MX6SX_PAD_LCD1_DATA13__WEIM_AD_13    0xb0b1
+				MX6SX_PAD_LCD1_DATA14__WEIM_AD_14    0xb0b1
+				MX6SX_PAD_LCD1_DATA15__WEIM_AD_15    0xb0b1
+				MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16  0xb0b1
+				MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17  0xb0b1
+				MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18  0xb0b1
+				MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19  0xb0b1
+				MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20  0xb0b1
+				MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21  0xb0b1
+				MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22  0xb0b1
+				MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24  0xb0b1
+				MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25  0xb0b1
+				MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26  0xb0b1
+			>;
+		};
+	};
+};
diff --git a/arch/arm/dts/imx6sx-19x19-val-ecspi.dts b/arch/arm/dts/imx6sx-19x19-val-ecspi.dts
new file mode 100644
index 00000000000..fcbaf3526b7
--- /dev/null
+++ b/arch/arm/dts/imx6sx-19x19-val-ecspi.dts
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6sx-19x19-val.dts"
+
+&usdhc3 {
+	status = "disabled";
+};
+
+&ecspi4 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio7 4 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>;
+	status = "okay"; /* pin conflict with USDHC3 */
+
+	flash: m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p32", "jedec,spi-nor";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
\ No newline at end of file
diff --git a/arch/arm/dts/imx6sx-19x19-val-gpmi-weim.dts b/arch/arm/dts/imx6sx-19x19-val-gpmi-weim.dts
new file mode 100644
index 00000000000..e4221223fd6
--- /dev/null
+++ b/arch/arm/dts/imx6sx-19x19-val-gpmi-weim.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6sx-19x19-val.dts"
+
+&qspi2 {
+	status = "disabled";
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "okay"; /* pin conflict with qspi*/
+	nand-on-flash-bbt;
+	fsl,use-minimum-ecc;
+};
diff --git a/arch/arm/dts/imx6sx-19x19-val.dts b/arch/arm/dts/imx6sx-19x19-val.dts
new file mode 100644
index 00000000000..ac0330ebdac
--- /dev/null
+++ b/arch/arm/dts/imx6sx-19x19-val.dts
@@ -0,0 +1,1309 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx6sx.dtsi"
+
+/ {
+	model = "i.MX6 SoloX 19x19 VAL Board";
+	compatible = "fsl,imx6sx-19x19-val", "fsl,imx6sx";
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm3 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+	};
+
+	hannstar_cabc {
+		compatible = "hannstar,cabc";
+
+		lvds0 {
+			gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	clocks {
+		codec_osc: codec_osc {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <12000000>;
+		};
+	};
+
+	max7322_reset: max7322-reset {
+		compatible = "gpio-reset";
+		reset-gpios = <&gpio6 18 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <1>;
+		#reset-cells = <0>;
+	};
+
+	pxp_v4l2_out {
+		compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
+		status = "okay";
+	};
+
+	regulators {
+		compatible = "simple-bus";
+
+		reg_3p3v: 3p3v {
+			compatible = "regulator-fixed";
+			regulator-name = "3P3V";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		reg_usb_otg1_vbus: usb_otg1_vbus {
+			compatible = "regulator-fixed";
+			regulator-name = "usb_otg1_vbus";
+			pinctrl-0 = <&pinctrl_usb_otg1_vbus>;
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 9 0>;
+			enable-active-high;
+		};
+	};
+
+	memory {
+		reg = <0x80000000 0x40000000>;
+	};
+
+	sound-cs42888 {
+		compatible = "fsl,imx6-sabreauto-cs42888",
+				"fsl,imx-audio-cs42888";
+		model = "imx-cs42888";
+		esai-controller = <&esai>;
+		asrc-controller = <&asrc>;
+		audio-codec = <&cs42888>;
+	};
+};
+
+&esai {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_esai_1>;
+	status = "okay";
+};
+
+&csi1 {
+	status = "okay";
+
+	port {
+		csi1_ep: endpoint {
+			remote-endpoint = <&ov5640_ep>;
+		};
+	};
+};
+
+&csi2 {
+	status = "okay";
+	port {
+		csi2_ep: endpoint {
+			remote-endpoint = <&vadc_ep>;
+		};
+	};
+};
+
+&cpu0 {
+	operating-points = <
+		/* kHz    uV */
+		996000  1275000
+		792000  1175000
+		396000  1075000
+		198000	975000
+		>;
+	fsl,soc-operating-points = <
+		/* ARM kHz      SOC uV */
+		996000	1175000
+		792000	1175000
+		396000	1175000
+		198000	1175000
+	>;
+};
+
+&reg_arm {
+	vin-supply = <&sw1a_reg>;
+	regulator-allow-bypass;
+};
+
+&reg_soc {
+	vin-supply = <&sw1c_reg>;
+	regulator-allow-bypass;
+};
+
+&gpc {
+	fsl,ldo-bypass = <1>;
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1_1>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy1>;
+	pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+	};
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2_1>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy0>;
+	pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>;
+	fsl,magic-packet;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1_1>;
+	pinctrl-1 = <&pinctrl_i2c1_1_gpio>;
+	scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pfuze100@8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3b_reg: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2_1>;
+	pinctrl-1 = <&pinctrl_i2c2_1_gpio>;
+	scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	max7322_1: gpio@68 {
+		compatible = "maxim,max7322";
+		reg = <0x68>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		resets = <&max7322_reset>;
+	};
+
+	max7322_2: gpio@69 {
+		compatible = "maxim,max7322";
+		reg = <0x69>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		resets = <&max7322_reset>;
+	};
+
+	ov5640: ov5640@3c {
+		compatible = "ovti,ov5640";
+		reg = <0x3c>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_csi_1>;
+		clocks = <&clks IMX6SX_CLK_CSI>;
+		clock-names = "csi_mclk";
+		AVDD-supply = <&vgen3_reg>;  /* 2.8v */
+		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
+		pwn-gpios = <&gpio3 26 1>;
+		rst-gpios = <&gpio3 25 0>;
+		csi_id = <0>;
+		mclk = <24000000>;
+		mclk_source = <0>;
+		status = "disabled";
+		port {
+			ov5640_ep: endpoint {
+				remote-endpoint = <&csi1_ep>;
+			};
+		};
+	};
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3_1>;
+	pinctrl-1 = <&pinctrl_i2c3_1_gpio>;
+	scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&i2c4 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c4_2>;
+	pinctrl-1 = <&pinctrl_i2c4_2_gpio>;
+	scl-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	sgtl5000: sgtl5000@0a {
+		compatible = "fsl,sgtl5000";
+		reg = <0x0a>;
+		clocks = <&codec_osc>;
+		VDDA-supply = <&vgen4_reg>;
+		VDDIO-supply = <&reg_3p3v>;
+	};
+
+	cs42888: cs42888@048 {
+		compatible = "cirrus,cs42888";
+		reg = <0x048>;
+		clocks = <&clks IMX6SX_CLK_ESAI_EXTAL>;
+		clock-names = "mclk";
+		VA-supply = <&reg_3p3v>;
+		VD-supply = <&reg_3p3v>;
+		VLS-supply = <&reg_3p3v>;
+		VLC-supply = <&reg_3p3v>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	hog {
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD4_DATA4__GPIO6_IO_18     0x1b0b0
+				MX6SX_PAD_KEY_ROW1__GPIO2_IO_16      0x1b0b0
+			 >;
+		};
+	};
+};
+
+&lcdif1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif_dat_0
+		     &pinctrl_lcdif_ctrl_0>;
+	display = <&display0>;
+	status = "disabled";
+
+	display0: display {
+		bits-per-pixel = <16>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+				clock-frequency = <33500000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <89>;
+				hfront-porch = <164>;
+				vback-porch = <23>;
+				vfront-porch = <10>;
+				hsync-len = <10>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&lcdif2 {
+	display = <&display1>;
+	disp-dev = "ldb";
+	status = "okay";
+
+	display1: display {
+		bits-per-pixel = <16>;
+		bus-width = <18>;
+	};
+};
+
+&pwm3 {
+	#pwm-cells = <2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm3_0>;
+	status = "okay";
+};
+
+&pxp {
+	status = "okay";
+};
+
+&sai1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai1_1>;
+	status = "disabled";
+};
+
+&snvs_poweroff {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2_1>;
+	status = "okay";
+};
+
+&qspi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi2_1>;
+	status = "okay";
+	ddrsmp=<2>;
+
+	flash0: n25q256a@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		reg = <0>;
+	};
+
+	flash1: n25q256a@1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		reg = <1>;
+	};
+};
+
+&usbh {
+	pinctrl-names = "idle", "active";
+	pinctrl-0 = <&pinctrl_usbh_1>;
+	pinctrl-1 = <&pinctrl_usbh_2>;
+	osc-clkgate-delay = <0x3>;
+	pad-supply = <&vgen1_reg>;
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg1_1>;
+	disable-over-current;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1_1>;
+	bus-width = <4>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	no-1-8-v;
+	status = "okay";
+};
+
+&weim {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
+	#address-cells = <2>;
+	#size-cells = <1>;
+	ranges = <0 0 0x50000000 0x08000000>;
+	status = "disabled"; /* pin conflict with qspi, nand and lcd1 */
+
+	nor@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0 0x02000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		bank-width = <2>;
+		fsl,weim-cs-timing = <0x00610081 0x00000001 0x1c022000
+				0x0000c000 0x1404a38e 0x00000000>;
+	};
+};
+
+&vadc {
+	vadc_in = <0>;
+	csi_id = <1>;
+	status = "okay";
+	port {
+		vadc_ep: endpoint {
+			remote-endpoint = <&csi2_ep>;
+		};
+	};
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+};
+
+&iomuxc {
+	audmux {
+		pinctrl_audmux_1: audmuxgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC   0x130B0
+				MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS  0x130B0
+				MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD    0x120B0
+				MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD    0x130B0
+				MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK       0x130B0
+			>;
+		};
+
+		pinctrl_audmux_2: audmuxgrp-2 {
+			fsl,pins = <
+				MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 	 0x130b0
+				MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD     0x130b0
+				MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0
+				MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD  0x130b0
+			>;
+		};
+	};
+
+	ecspi4 {
+		pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD3_DATA2__GPIO7_IO_4  0x80000000
+			>;
+		};
+
+		pinctrl_ecspi4_1: ecspi4grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1
+				MX6SX_PAD_SD3_CMD__ECSPI4_MOSI   0x100b1
+				MX6SX_PAD_SD3_CLK__ECSPI4_SCLK   0x100b1
+			>;
+		};
+	};
+
+	canfd1 {
+		pinctrl_canfd1_1: canfd1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1B_DQS__CANFD_TX1		0x1b0b0
+				MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1	0x1b0b0
+			>;
+		};
+	};
+
+	canfd2 {
+		pinctrl_canfd2_1: canfd2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2	0x1b0b0
+				MX6SX_PAD_QSPI1A_DQS__CANFD_TX2		0x1b0b0
+			>;
+		};
+	};
+
+	csi {
+		pinctrl_csi_0: csigrp-0 {
+			fsl,pins = <
+				MX6SX_PAD_LCD1_DATA07__CSI1_MCLK	0x110b0
+				MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK	0x110b0
+				MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC	0x110b0
+				MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC	0x110b0
+				MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0	0x110b0
+				MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1	0x110b0
+				MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2	0x110b0
+				MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3	0x110b0
+				MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4	0x110b0
+				MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5	0x110b0
+				MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6	0x110b0
+				MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7	0x110b0
+				MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8	0x110b0
+				MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9	0x110b0
+				MX6SX_PAD_LCD1_RESET__GPIO3_IO_27	0x80000000
+				MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28	0x80000000
+			>;
+		};
+
+		pinctrl_csi_1: csigrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_MCLK__CSI1_MCLK		0x110b0
+				MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK	0x110b0
+				MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC		0x110b0
+				MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC		0x110b0
+				MX6SX_PAD_CSI_DATA00__CSI1_DATA_2	0x110b0
+				MX6SX_PAD_CSI_DATA01__CSI1_DATA_3	0x110b0
+				MX6SX_PAD_CSI_DATA02__CSI1_DATA_4	0x110b0
+				MX6SX_PAD_CSI_DATA03__CSI1_DATA_5	0x110b0
+				MX6SX_PAD_CSI_DATA04__CSI1_DATA_6	0x110b0
+				MX6SX_PAD_CSI_DATA05__CSI1_DATA_7	0x110b0
+				MX6SX_PAD_CSI_DATA06__CSI1_DATA_8	0x110b0
+				MX6SX_PAD_CSI_DATA07__CSI1_DATA_9	0x110b0
+
+				MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25	0x80000000
+				MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26	0x80000000
+			>;
+		};
+	};
+
+	enet1 {
+		pinctrl_enet1_1: enet1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
+				MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
+				MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b9
+				MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
+				MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
+				MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
+				MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
+				MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
+				MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
+				MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
+				MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
+				MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
+				MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
+				MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
+			>;
+		};
+
+		pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M	0x91
+			>;
+		};
+	};
+
+	enet2 {
+		pinctrl_enet2_1: enet2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
+				MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
+				MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
+				MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
+				MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
+				MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
+				MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
+				MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
+				MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
+				MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
+				MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
+				MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
+			>;
+		};
+	};
+
+	esai {
+		pinctrl_esai_1: esaigrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK  0x1b030
+				MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK   0x1b030
+				MX6SX_PAD_CSI_DATA01__ESAI_TX_FS    0x1b030
+				MX6SX_PAD_CSI_HSYNC__ESAI_TX0       0x1b030
+				MX6SX_PAD_CSI_DATA04__ESAI_TX1      0x1b030
+				MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3  0x1b030
+				MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2  0x1b030
+				MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK   0x1b030
+				MX6SX_PAD_CSI_DATA03__ESAI_RX_FS    0x1b030
+				MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0   0x1b030
+				MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1  0x1b030
+			>;
+		};
+	};
+
+	flexcan1 {
+		pinctrl_flexcan1_1: flexcan1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1B_DQS__CAN1_TX	0x1b0b0
+				MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX	0x1b0b0
+			>;
+		};
+	};
+
+	flexcan2 {
+		pinctrl_flexcan2_1: flexcan2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0
+				MX6SX_PAD_QSPI1A_DQS__CAN2_TX	0x1b0b0
+			>;
+		};
+	};
+
+	gpmi-nand {
+		pinctrl_gpmi_nand_1: gpmi-nand-1 {
+			fsl,pins = <
+				MX6SX_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
+				MX6SX_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
+				MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
+				MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
+				MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
+				MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B     0xb0b1
+				MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
+				MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
+				MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
+				MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
+				MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
+				MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
+				MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
+				MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
+				MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
+				MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
+			>;
+		};
+	};
+
+	i2c1 {
+		pinctrl_i2c1_1: i2c1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO01__I2C1_SDA          0x4001b8b1
+				MX6SX_PAD_GPIO1_IO00__I2C1_SCL          0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c1_1_gpio: i2c1grp-1-gpio {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1        0x1b8b1
+				MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0        0x1b8b1
+			>;
+		};
+
+		pinctrl_i2c1_2: i2c1grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA01__I2C1_SDA          0x4001b8b1
+				MX6SX_PAD_CSI_DATA00__I2C1_SCL          0x4001b8b1
+			>;
+		};
+	};
+
+	i2c2 {
+		pinctrl_i2c2_1: i2c2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO03__I2C2_SDA          0x4001b8b1
+				MX6SX_PAD_GPIO1_IO02__I2C2_SCL          0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c2_1_gpio: i2c2grp-1-gpio {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3        0x1b8b1
+				MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2        0x1b8b1
+			>;
+		};
+	};
+
+	i2c3 {
+		pinctrl_i2c3_1: i2c3grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA        0x4001b8b1
+				MX6SX_PAD_KEY_COL4__I2C3_SCL            0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c3_1_gpio: i2c3grp-1-gpio {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9      0x1b8b1
+				MX6SX_PAD_KEY_COL4__GPIO2_IO_14         0x1b8b1
+			>;
+		};
+
+		pinctrl_i2c3_2: i2c3grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_KEY_ROW4__I2C3_SDA            0x4001b8b1
+				MX6SX_PAD_KEY_COL4__I2C3_SCL            0x4001b8b1
+			>;
+		};
+	};
+
+	i2c4 {
+		pinctrl_i2c4_1: i2c4grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA07__I2C4_SDA          0x4001b8b1
+				MX6SX_PAD_CSI_DATA06__I2C4_SCL          0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c4_2: i2c4grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_SD3_DATA1__I2C4_SDA           0x4001b8b1
+				MX6SX_PAD_SD3_DATA0__I2C4_SCL           0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c4_2_gpio: i2c4grp-2-gpio {
+			fsl,pins = <
+				MX6SX_PAD_SD3_DATA1__GPIO7_IO_3         0x1b8b1
+				MX6SX_PAD_SD3_DATA0__GPIO7_IO_2         0x1b8b1
+			>;
+		};
+	};
+
+	lcdif1 {
+		pinctrl_lcdif_dat_0: lcdifdatgrp-0 {
+			fsl,pins = <
+				MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
+				MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
+			>;
+		};
+
+		pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 {
+			fsl,pins = <
+				MX6SX_PAD_LCD1_CLK__LCDIF1_CLK	0x4001b0b0
+				MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
+				MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
+				MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
+				MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
+			>;
+		};
+	};
+
+	mlb {
+		pinctrl_mlb_1: mlbgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD2_DATA3__MLB_DATA	0x31
+				MX6SX_PAD_SD2_CLK__MLB_SIG	0x31
+				MX6SX_PAD_SD2_CMD__MLB_CLK	0x31
+			>;
+		};
+	};
+
+	mqs {
+		pinctrl_mqs_1: mqsgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x80000000
+				MX6SX_PAD_SD2_CMD__MQS_LEFT 0x80000000
+			>;
+		};
+	};
+
+	pwm3 {
+		pinctrl_pwm3_0: pwm3grp-0 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0
+			>;
+		};
+
+		pinctrl_pwm3_1: pwm3grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
+			>;
+		};
+	};
+
+	pwm4 {
+		pinctrl_pwm4_0: pwm4grp-0 {
+			fsl,pins = <
+				MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
+			>;
+		};
+	};
+
+	qspi2 {
+		pinctrl_qspi2_1: qspi2grp_1 {
+			fsl,pins = <
+				MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70a1
+				MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1  0x70a1
+				MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2    0x70a1
+				MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3    0x70a1
+				MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK        0x70a1
+				MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B       0x70a1
+				MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0   0x70a1
+				MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1   0x70a1
+				MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2     0x70a1
+				MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3     0x70a1
+				MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK     0x70a1
+				MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B    0x70a1
+			>;
+		};
+	};
+
+	sai1 {
+		pinctrl_sai1_1: sai1grp_1 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK     0x1b030
+				MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC     0x1b030
+				MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK     0x1b030
+				MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC     0x1b030
+				MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0    0x1b030
+				MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0    0x1b030
+			>;
+		};
+
+		pinctrl_sai1_2: sai1grp_2 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK     0x130B0
+				MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC     0x130B0
+				MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0    0x120B0
+				MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0    0x130B0
+				MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK      0x130B0
+			>;
+		};
+	};
+
+	sai2 {
+		pinctrl_sai2_1: sai2grp_1 {
+			fsl,pins = <
+				MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK       0x1b030
+				MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC       0x1b030
+				MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0     0x1b030
+				MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0     0x1b030
+			>;
+		};
+	};
+
+
+	spdif {
+		pinctrl_spdif_1: spdifgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT	0x1b0b0
+				MX6SX_PAD_ENET2_COL__SPDIF_IN		0x1b0b0
+			>;
+		};
+
+		pinctrl_spdif_2: spdifgrp-2 {
+			fsl,pins = <
+				MX6SX_PAD_SD4_DATA4__SPDIF_OUT		0x1b0b0
+			>;
+		};
+	};
+
+	uart1 {
+		pinctrl_uart1_1: uart1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
+				MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
+			>;
+		};
+
+		pinctrl_uart1_2: uart1grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1
+				MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1
+			>;
+		};
+	};
+
+	uart2 {
+		pinctrl_uart2_1: uart2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
+				MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
+			>;
+		};
+
+		pinctrl_uart2_2: uart2grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1
+				MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1
+			>;
+		};
+	};
+
+	uart5 {
+		pinctrl_uart5_1: uart5grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_KEY_ROW3__UART5_RX    0x1b0b1
+				MX6SX_PAD_KEY_COL3__UART5_TX    0x1b0b1
+				MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
+				MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
+			>;
+		};
+
+		pinctrl_uart5dte_1: uart5dtegrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_KEY_ROW3__UART5_TX	0x1b0b1
+				MX6SX_PAD_KEY_COL3__UART5_RX    0x1b0b1
+				MX6SX_PAD_KEY_ROW2__UART5_RTS_B	0x1b0b1
+				MX6SX_PAD_KEY_COL2__UART5_CTS_B	0x1b0b1
+			>;
+		};
+	};
+
+	usbh {
+		pinctrl_usbh_1: usbhgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_USB_H_STROBE__USB_H_STROBE	0x40013030
+				MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030
+			>;
+		};
+
+		pinctrl_usbh_2: usbhgrp-2 {
+			fsl,pins = <
+				MX6SX_PAD_USB_H_STROBE__USB_H_STROBE	0x40017030
+			>;
+		};
+	};
+
+	usbotg1 {
+		pinctrl_usb_otg1_vbus: usbotg1vbusgrp {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9     0x10b0
+			>;
+		};
+
+		pinctrl_usbotg1_1: usbotg1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
+			>;
+		};
+
+		pinctrl_usbotg1_2: usbotg1grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059
+			>;
+		};
+
+		pinctrl_usbotg1_3: usbotg1grp-3 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059
+			>;
+		};
+	};
+
+	usbotg2 {
+		pinctrl_usbotg2_1: usbotg2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059
+			>;
+		};
+
+		pinctrl_usbotg2_2: usbotg2grp-2 {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059
+			>;
+		};
+
+		pinctrl_usbotg2_3: usbotg2grp-3 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059
+			>;
+		};
+	};
+
+	usdhc1 {
+		pinctrl_usdhc1_1: usdhc1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD1_CMD__USDHC1_CMD     0x17059
+				MX6SX_PAD_SD1_CLK__USDHC1_CLK     0x10059
+				MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+				MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+				MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+				MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+			>;
+		};
+	};
+
+	usdhc2 {
+		pinctrl_usdhc2_1: usdhc2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD2_CMD__USDHC2_CMD     0x17059
+				MX6SX_PAD_SD2_CLK__USDHC2_CLK     0x10059
+				MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
+				MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
+				MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
+				MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
+			>;
+		};
+	};
+
+	usdhc3 {
+		pinctrl_usdhc3_1: usdhc3grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD3_CMD__USDHC3_CMD	  0x17059
+				MX6SX_PAD_SD3_CLK__USDHC3_CLK	  0x10059
+				MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
+				MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
+				MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
+				MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
+				MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
+				MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
+				MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
+				MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
+			>;
+		};
+
+		pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
+			fsl,pins = <
+				MX6SX_PAD_SD3_CMD__USDHC3_CMD	  0x170b9
+				MX6SX_PAD_SD3_CLK__USDHC3_CLK	  0x100b9
+				MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
+				MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
+				MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
+				MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
+				MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
+				MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
+				MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
+				MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
+			>;
+		};
+
+		pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
+			fsl,pins = <
+				MX6SX_PAD_SD3_CMD__USDHC3_CMD	  0x170f9
+				MX6SX_PAD_SD3_CLK__USDHC3_CLK	  0x100f9
+				MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
+				MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
+				MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
+				MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
+				MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
+				MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
+				MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
+				MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
+			>;
+		};
+
+	};
+
+	usdhc4 {
+			pinctrl_usdhc4_1: usdhc4grp-1 {
+				fsl,pins = <
+					MX6SX_PAD_SD4_CMD__USDHC4_CMD     0x17059
+					MX6SX_PAD_SD4_CLK__USDHC4_CLK     0x10059
+					MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
+					MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
+					MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
+					MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
+					MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
+					MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
+					MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
+					MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
+				>;
+			};
+
+			pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz {
+				fsl,pins = <
+					MX6SX_PAD_SD4_CMD__USDHC4_CMD     0x170b9
+					MX6SX_PAD_SD4_CLK__USDHC4_CLK     0x100b9
+					MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
+					MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
+					MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
+					MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
+					MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
+					MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
+					MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
+					MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
+				>;
+			};
+
+			pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz {
+				fsl,pins = <
+					MX6SX_PAD_SD4_CMD__USDHC4_CMD     0x170f9
+					MX6SX_PAD_SD4_CLK__USDHC4_CLK     0x100f9
+					MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
+					MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
+					MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
+					MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
+					MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
+					MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
+					MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
+					MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
+				>;
+			};
+
+			pinctrl_usdhc4_2: usdhc4grp-2 {
+				fsl,pins = <
+					MX6SX_PAD_SD4_CMD__USDHC4_CMD     0x17059
+					MX6SX_PAD_SD4_CLK__USDHC4_CLK     0x10059
+					MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
+					MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
+					MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
+					MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
+				>;
+			};
+
+	};
+
+	wdog {
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0
+			>;
+		};
+	};
+
+	weim {
+		pinctrl_weim_cs0_1: weim_cs0grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_NAND_ALE__WEIM_CS0_B       0xb0b1
+			>;
+		};
+
+		pinctrl_weim_nor_1: weim_norgrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_NAND_CE1_B__WEIM_OE        0xb0b1
+				MX6SX_PAD_NAND_RE_B__WEIM_RW         0xb0b1
+				MX6SX_PAD_NAND_WE_B__WEIM_WAIT       0xb060
+				/* data */
+				MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0   0x1b0b0
+				MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1  0x1b0b0
+				MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2  0x1b0b0
+				MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3  0x1b0b0
+				MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4  0x1b0b0
+				MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5  0x1b0b0
+				MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6  0x1b0b0
+				MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7    0x1b0b0
+				MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8   0x1b0b0
+				MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9  0x1b0b0
+				MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0
+				MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0
+				MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0
+				MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0
+				MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0
+				MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15   0x1b0b0
+				/* address */
+				MX6SX_PAD_NAND_DATA00__WEIM_AD_0     0xb0b1
+				MX6SX_PAD_NAND_DATA01__WEIM_AD_1     0xb0b1
+				MX6SX_PAD_NAND_DATA02__WEIM_AD_2     0xb0b1
+				MX6SX_PAD_NAND_DATA03__WEIM_AD_3     0xb0b1
+				MX6SX_PAD_NAND_DATA04__WEIM_AD_4     0xb0b1
+				MX6SX_PAD_NAND_DATA05__WEIM_AD_5     0xb0b1
+				MX6SX_PAD_NAND_DATA06__WEIM_AD_6     0xb0b1
+				MX6SX_PAD_NAND_DATA07__WEIM_AD_7     0xb0b1
+				MX6SX_PAD_LCD1_DATA08__WEIM_AD_8     0xb0b1
+				MX6SX_PAD_LCD1_DATA09__WEIM_AD_9     0xb0b1
+				MX6SX_PAD_LCD1_DATA10__WEIM_AD_10    0xb0b1
+				MX6SX_PAD_LCD1_DATA11__WEIM_AD_11    0xb0b1
+				MX6SX_PAD_LCD1_DATA12__WEIM_AD_12    0xb0b1
+				MX6SX_PAD_LCD1_DATA13__WEIM_AD_13    0xb0b1
+				MX6SX_PAD_LCD1_DATA14__WEIM_AD_14    0xb0b1
+				MX6SX_PAD_LCD1_DATA15__WEIM_AD_15    0xb0b1
+				MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16  0xb0b1
+				MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17  0xb0b1
+				MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18  0xb0b1
+				MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19  0xb0b1
+				MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20  0xb0b1
+				MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21  0xb0b1
+				MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22  0xb0b1
+				MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24  0xb0b1
+				MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25  0xb0b1
+				MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26  0xb0b1
+			>;
+		};
+	};
+};
diff --git a/arch/arm/dts/imx6sx-pinfunc.h b/arch/arm/dts/imx6sx-pinfunc.h
index f4dc4620795..78c95f020a1 100644
--- a/arch/arm/dts/imx6sx-pinfunc.h
+++ b/arch/arm/dts/imx6sx-pinfunc.h
@@ -67,6 +67,7 @@
 #define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK                           0x002C 0x0374 0x0000 0x3 0x0
 #define MX6SX_PAD_GPIO1_IO06__UART1_DCE_RTS                       0x002C 0x0374 0x082C 0x4 0x0
 #define MX6SX_PAD_GPIO1_IO06__UART1_DTE_CTS                       0x002C 0x0374 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO06__UART1_CTS_B                         0x002C 0x0374 0x0000 0x4 0x0
 #define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6                          0x002C 0x0374 0x0000 0x5 0x0
 #define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET                    0x002C 0x0374 0x0000 0x6 0x0
 #define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED     0x002C 0x0374 0x0000 0x7 0x0
@@ -77,6 +78,7 @@
 #define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK                         0x0030 0x0378 0x0000 0x3 0x0
 #define MX6SX_PAD_GPIO1_IO07__UART1_DCE_CTS                       0x0030 0x0378 0x0000 0x4 0x0
 #define MX6SX_PAD_GPIO1_IO07__UART1_DTE_RTS                       0x0030 0x0378 0x082C 0x4 0x1
+#define MX6SX_PAD_GPIO1_IO07__UART1_RTS_B                         0x0030 0x0378 0x082C 0x4 0x1
 #define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7                          0x0030 0x0378 0x0000 0x5 0x0
 #define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET                     0x0030 0x0378 0x0000 0x6 0x0
 #define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT                           0x0030 0x0378 0x0000 0x7 0x0
@@ -87,6 +89,7 @@
 #define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY                        0x0034 0x037C 0x069C 0x3 0x1
 #define MX6SX_PAD_GPIO1_IO08__UART2_DCE_RTS                       0x0034 0x037C 0x0834 0x4 0x0
 #define MX6SX_PAD_GPIO1_IO08__UART2_DTE_CTS                       0x0034 0x037C 0x0000 0x4 0x0
+#define MX6SX_PAD_GPIO1_IO08__UART2_CTS_B                         0x0034 0x037C 0x0000 0x4 0x0
 #define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8                          0x0034 0x037C 0x0000 0x5 0x0
 #define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET                    0x0034 0x037C 0x0000 0x6 0x0
 #define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT                           0x0034 0x037C 0x0000 0x7 0x0
@@ -97,6 +100,7 @@
 #define MX6SX_PAD_GPIO1_IO09__CCM_OUT0                            0x0038 0x0380 0x0000 0x3 0x0
 #define MX6SX_PAD_GPIO1_IO09__UART2_DCE_CTS                       0x0038 0x0380 0x0000 0x4 0x0
 #define MX6SX_PAD_GPIO1_IO09__UART2_DTE_RTS                       0x0038 0x0380 0x0834 0x4 0x1
+#define MX6SX_PAD_GPIO1_IO09__UART2_RTS_B                         0x0038 0x0380 0x0834 0x4 0x1
 #define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9                          0x0038 0x0380 0x0000 0x5 0x0
 #define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT                        0x0038 0x0380 0x0000 0x6 0x0
 #define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4                   0x0038 0x0380 0x0000 0x7 0x0
@@ -205,6 +209,7 @@
 #define MX6SX_PAD_CSI_DATA06__KPP_COL_7                           0x0064 0x03AC 0x07D0 0x3 0x0
 #define MX6SX_PAD_CSI_DATA06__UART6_DCE_RTS                       0x0064 0x03AC 0x0854 0x4 0x0
 #define MX6SX_PAD_CSI_DATA06__UART6_DTE_CTS                       0x0064 0x03AC 0x0000 0x4 0x0
+#define MX6SX_PAD_CSI_DATA06__UART6_CTS_B                         0x0064 0x03AC 0x0000 0x4 0x0
 #define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20                         0x0064 0x03AC 0x0000 0x5 0x0
 #define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17                        0x0064 0x03AC 0x0000 0x6 0x0
 #define MX6SX_PAD_CSI_DATA06__DCIC2_OUT                           0x0064 0x03AC 0x0000 0x7 0x0
@@ -216,6 +221,7 @@
 #define MX6SX_PAD_CSI_DATA07__KPP_ROW_7                           0x0068 0x03B0 0x07DC 0x3 0x0
 #define MX6SX_PAD_CSI_DATA07__UART6_DCE_CTS                       0x0068 0x03B0 0x0000 0x4 0x0
 #define MX6SX_PAD_CSI_DATA07__UART6_DTE_RTS                       0x0068 0x03B0 0x0854 0x4 0x1
+#define MX6SX_PAD_CSI_DATA07__UART6_RTS_B                         0x0068 0x03B0 0x0854 0x4 0x1
 #define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21                         0x0068 0x03B0 0x0000 0x5 0x0
 #define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16                        0x0068 0x03B0 0x0000 0x6 0x0
 #define MX6SX_PAD_CSI_DATA07__DCIC1_OUT                           0x0068 0x03B0 0x0000 0x7 0x0
@@ -226,6 +232,7 @@
 #define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD                      0x006C 0x03B4 0x0678 0x2 0x1
 #define MX6SX_PAD_CSI_HSYNC__UART4_DCE_RTS                        0x006C 0x03B4 0x0844 0x3 0x2
 #define MX6SX_PAD_CSI_HSYNC__UART4_DTE_CTS                        0x006C 0x03B4 0x0000 0x3 0x0
+#define MX6SX_PAD_CSI_HSYNC__UART4_CTS_B                          0x006C 0x03B4 0x0000 0x3 0x0
 #define MX6SX_PAD_CSI_HSYNC__MQS_LEFT                             0x006C 0x03B4 0x0000 0x4 0x0
 #define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22                          0x006C 0x03B4 0x0000 0x5 0x0
 #define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25                         0x006C 0x03B4 0x0000 0x6 0x0
@@ -259,6 +266,7 @@
 #define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD                      0x0078 0x03C0 0x0674 0x2 0x1
 #define MX6SX_PAD_CSI_VSYNC__UART4_DCE_CTS                        0x0078 0x03C0 0x0000 0x3 0x0
 #define MX6SX_PAD_CSI_VSYNC__UART4_DTE_RTS                        0x0078 0x03C0 0x0844 0x3 0x3
+#define MX6SX_PAD_CSI_VSYNC__UART4_RTS_B                          0x0078 0x03C0 0x0844 0x3 0x3
 #define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT                            0x0078 0x03C0 0x0000 0x4 0x0
 #define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25                          0x0078 0x03C0 0x0000 0x5 0x0
 #define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24                         0x0078 0x03C0 0x0000 0x6 0x0
@@ -362,6 +370,7 @@
 #define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL                          0x009C 0x03E4 0x07B8 0x2 0x1
 #define MX6SX_PAD_ENET2_RX_CLK__UART1_DCE_RTS                     0x009C 0x03E4 0x082C 0x3 0x2
 #define MX6SX_PAD_ENET2_RX_CLK__UART1_DTE_CTS                     0x009C 0x03E4 0x0000 0x3 0x0
+#define MX6SX_PAD_ENET2_RX_CLK__UART1_CTS_B                       0x009C 0x03E4 0x0000 0x3 0x0
 #define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA                          0x009C 0x03E4 0x07EC 0x4 0x1
 #define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8                        0x009C 0x03E4 0x0000 0x5 0x0
 #define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC                       0x009C 0x03E4 0x085C 0x6 0x1
@@ -373,6 +382,7 @@
 #define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA                          0x00A0 0x03E8 0x07BC 0x2 0x1
 #define MX6SX_PAD_ENET2_TX_CLK__UART1_DCE_CTS                     0x00A0 0x03E8 0x0000 0x3 0x0
 #define MX6SX_PAD_ENET2_TX_CLK__UART1_DTE_RTS                     0x00A0 0x03E8 0x082C 0x3 0x3
+#define MX6SX_PAD_ENET2_TX_CLK__UART1_RTS_B                       0x00A0 0x03E8 0x082C 0x3 0x3
 #define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK                           0x00A0 0x03E8 0x07E8 0x4 0x1
 #define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9                        0x00A0 0x03E8 0x0000 0x5 0x0
 #define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR                      0x00A0 0x03E8 0x0000 0x6 0x0
@@ -383,6 +393,7 @@
 #define MX6SX_PAD_KEY_COL0__USDHC3_CD_B                           0x00A4 0x03EC 0x0000 0x1 0x0
 #define MX6SX_PAD_KEY_COL0__UART6_DCE_RTS                         0x00A4 0x03EC 0x0854 0x2 0x2
 #define MX6SX_PAD_KEY_COL0__UART6_DTE_CTS                         0x00A4 0x03EC 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_COL0__UART6_CTS_B                           0x00A4 0x03EC 0x0000 0x2 0x0
 #define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK                           0x00A4 0x03EC 0x0710 0x3 0x0
 #define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC                       0x00A4 0x03EC 0x066C 0x4 0x0
 #define MX6SX_PAD_KEY_COL0__GPIO2_IO_10                           0x00A4 0x03EC 0x0000 0x5 0x0
@@ -402,6 +413,7 @@
 #define MX6SX_PAD_KEY_COL2__USDHC4_CD_B                           0x00AC 0x03F4 0x0874 0x1 0x1
 #define MX6SX_PAD_KEY_COL2__UART5_DCE_RTS                         0x00AC 0x03F4 0x084C 0x2 0x2
 #define MX6SX_PAD_KEY_COL2__UART5_DTE_CTS                         0x00AC 0x03F4 0x0000 0x2 0x0
+#define MX6SX_PAD_KEY_COL2__UART5_CTS_B                           0x00AC 0x03F4 0x0000 0x2 0x0
 #define MX6SX_PAD_KEY_COL2__CAN1_TX                               0x00AC 0x03F4 0x0000 0x3 0x0
 #define MX6SX_PAD_KEY_COL2__CANFD_TX1                             0x00AC 0x03F4 0x0000 0x4 0x0
 #define MX6SX_PAD_KEY_COL2__GPIO2_IO_12                           0x00AC 0x03F4 0x0000 0x5 0x0
@@ -428,6 +440,7 @@
 #define MX6SX_PAD_KEY_ROW0__USDHC3_WP                             0x00B8 0x0400 0x0000 0x1 0x0
 #define MX6SX_PAD_KEY_ROW0__UART6_DCE_CTS                         0x00B8 0x0400 0x0000 0x2 0x0
 #define MX6SX_PAD_KEY_ROW0__UART6_DTE_RTS                         0x00B8 0x0400 0x0854 0x2 0x3
+#define MX6SX_PAD_KEY_ROW0__UART6_RTS_B                           0x00B8 0x0400 0x0854 0x2 0x3
 #define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI                           0x00B8 0x0400 0x0718 0x3 0x0
 #define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD                       0x00B8 0x0400 0x0660 0x4 0x0
 #define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15                           0x00B8 0x0400 0x0000 0x5 0x0
@@ -448,6 +461,7 @@
 #define MX6SX_PAD_KEY_ROW2__USDHC4_WP                             0x00C0 0x0408 0x0878 0x1 0x1
 #define MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS                         0x00C0 0x0408 0x0000 0x2 0x0
 #define MX6SX_PAD_KEY_ROW2__UART5_DTE_RTS                         0x00C0 0x0408 0x084C 0x2 0x3
+#define MX6SX_PAD_KEY_ROW2__UART5_RTS_B                           0x00C0 0x0408 0x084C 0x2 0x3
 #define MX6SX_PAD_KEY_ROW2__CAN1_RX                               0x00C0 0x0408 0x068C 0x3 0x1
 #define MX6SX_PAD_KEY_ROW2__CANFD_RX1                             0x00C0 0x0408 0x0694 0x4 0x1
 #define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17                           0x00C0 0x0408 0x0000 0x5 0x0
@@ -831,6 +845,7 @@
 #define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B                      0x0160 0x04A8 0x0000 0x2 0x0
 #define MX6SX_PAD_NAND_DATA04__UART3_DCE_RTS                      0x0160 0x04A8 0x083C 0x3 0x0
 #define MX6SX_PAD_NAND_DATA04__UART3_DTE_CTS                      0x0160 0x04A8 0x0000 0x3 0x0
+#define MX6SX_PAD_NAND_DATA04__UART3_CTS_B                        0x0160 0x04A8 0x0000 0x3 0x0
 #define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS                   0x0160 0x04A8 0x0650 0x4 0x0
 #define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8                         0x0160 0x04A8 0x0000 0x5 0x0
 #define MX6SX_PAD_NAND_DATA04__WEIM_AD_4                          0x0160 0x04A8 0x0000 0x6 0x0
@@ -842,6 +857,7 @@
 #define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS                        0x0164 0x04AC 0x0000 0x2 0x0
 #define MX6SX_PAD_NAND_DATA05__UART3_DCE_CTS                      0x0164 0x04AC 0x0000 0x3 0x0
 #define MX6SX_PAD_NAND_DATA05__UART3_DTE_RTS                      0x0164 0x04AC 0x083C 0x3 0x1
+#define MX6SX_PAD_NAND_DATA05__UART3_RTS_B                        0x0164 0x04AC 0x083C 0x3 0x1
 #define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC                    0x0164 0x04AC 0x064C 0x4 0x0
 #define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9                         0x0164 0x04AC 0x0000 0x5 0x0
 #define MX6SX_PAD_NAND_DATA05__WEIM_AD_5                          0x0164 0x04AC 0x0000 0x6 0x0
@@ -985,6 +1001,7 @@
 #define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0                    0x01A0 0x04E8 0x0000 0x0 0x0
 #define MX6SX_PAD_QSPI1B_DATA0__UART3_DCE_CTS                     0x01A0 0x04E8 0x0000 0x1 0x0
 #define MX6SX_PAD_QSPI1B_DATA0__UART3_DTE_RTS                     0x01A0 0x04E8 0x083C 0x1 0x4
+#define MX6SX_PAD_QSPI1B_DATA0__UART3_RTS_B                       0x01A0 0x04E8 0x083C 0x1 0x4
 #define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI                       0x01A0 0x04E8 0x0738 0x2 0x1
 #define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS                        0x01A0 0x04E8 0x0778 0x3 0x2
 #define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22                      0x01A0 0x04E8 0x06F4 0x4 0x1
@@ -994,6 +1011,7 @@
 #define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1                    0x01A4 0x04EC 0x0000 0x0 0x0
 #define MX6SX_PAD_QSPI1B_DATA1__UART3_DCE_RTS                     0x01A4 0x04EC 0x083C 0x1 0x5
 #define MX6SX_PAD_QSPI1B_DATA1__UART3_DTE_CTS                     0x01A4 0x04EC 0x0000 0x1 0x0
+#define MX6SX_PAD_QSPI1B_DATA1__UART3_CTS_B                       0x01A4 0x04EC 0x0000 0x1 0x0
 #define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO                       0x01A4 0x04EC 0x0734 0x2 0x1
 #define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK                       0x01A4 0x04EC 0x0788 0x3 0x2
 #define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21                      0x01A4 0x04EC 0x06F0 0x4 0x1
@@ -1266,6 +1284,7 @@
 #define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2                         0x0230 0x0578 0x0000 0x3 0x0
 #define MX6SX_PAD_SD1_DATA2__UART2_DCE_CTS                        0x0230 0x0578 0x0000 0x4 0x0
 #define MX6SX_PAD_SD1_DATA2__UART2_DTE_RTS                        0x0230 0x0578 0x0834 0x4 0x2
+#define MX6SX_PAD_SD1_DATA2__UART2_RTS_B                          0x0230 0x0578 0x0834 0x4 0x2
 #define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4                           0x0230 0x0578 0x0000 0x5 0x0
 #define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY                           0x0230 0x0578 0x0000 0x6 0x0
 #define MX6SX_PAD_SD1_DATA2__CCM_OUT0                             0x0230 0x0578 0x0000 0x7 0x0
@@ -1276,6 +1295,7 @@
 #define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3                         0x0234 0x057C 0x0000 0x3 0x0
 #define MX6SX_PAD_SD1_DATA3__UART2_DCE_RTS                        0x0234 0x057C 0x0834 0x4 0x3
 #define MX6SX_PAD_SD1_DATA3__UART2_DTE_CTS                        0x0234 0x057C 0x0000 0x4 0x0
+#define MX6SX_PAD_SD1_DATA3__UART2_CTS_B                          0x0234 0x057C 0x0000 0x4 0x0
 #define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5                           0x0234 0x057C 0x0000 0x5 0x0
 #define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1                           0x0234 0x057C 0x0000 0x6 0x0
 #define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY                         0x0234 0x057C 0x069C 0x7 0x2
@@ -1347,6 +1367,7 @@
 #define MX6SX_PAD_SD3_CLK__USDHC3_CLK                             0x0250 0x0598 0x0000 0x0 0x0
 #define MX6SX_PAD_SD3_CLK__UART4_DCE_CTS                          0x0250 0x0598 0x0000 0x1 0x0
 #define MX6SX_PAD_SD3_CLK__UART4_DTE_RTS                          0x0250 0x0598 0x0844 0x1 0x0
+#define MX6SX_PAD_SD3_CLK__UART4_RTS_B                            0x0250 0x0598 0x0844 0x1 0x0
 #define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK                            0x0250 0x0598 0x0740 0x2 0x0
 #define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS                       0x0250 0x0598 0x0680 0x3 0x0
 #define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC                           0x0250 0x0598 0x0000 0x4 0x0
@@ -1387,6 +1408,7 @@
 #define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2                         0x0260 0x05A8 0x0000 0x0 0x0
 #define MX6SX_PAD_SD3_DATA2__UART4_DCE_RTS                        0x0260 0x05A8 0x0844 0x1 0x1
 #define MX6SX_PAD_SD3_DATA2__UART4_DTE_CTS                        0x0260 0x05A8 0x0000 0x1 0x0
+#define MX6SX_PAD_SD3_DATA2__UART4_CTS_B                          0x0260 0x05A8 0x0000 0x1 0x0
 #define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0                           0x0260 0x05A8 0x074C 0x2 0x0
 #define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS                     0x0260 0x05A8 0x0688 0x3 0x0
 #define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK                           0x0260 0x05A8 0x0000 0x4 0x0
@@ -1433,6 +1455,7 @@
 #define MX6SX_PAD_SD3_DATA6__CANFD_TX2                            0x0270 0x05B8 0x0000 0x2 0x0
 #define MX6SX_PAD_SD3_DATA6__UART3_DCE_RTS                        0x0270 0x05B8 0x083C 0x3 0x2
 #define MX6SX_PAD_SD3_DATA6__UART3_DTE_CTS                        0x0270 0x05B8 0x0000 0x3 0x0
+#define MX6SX_PAD_SD3_DATA6__UART3_CTS_B                          0x0270 0x05B8 0x0000 0x3 0x0
 #define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4                        0x0270 0x05B8 0x0000 0x4 0x0
 #define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8                           0x0270 0x05B8 0x0000 0x5 0x0
 #define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT                0x0270 0x05B8 0x0000 0x6 0x0
@@ -1444,6 +1467,7 @@
 #define MX6SX_PAD_SD3_DATA7__CANFD_RX1                            0x0274 0x05BC 0x0694 0x2 0x0
 #define MX6SX_PAD_SD3_DATA7__UART3_DCE_CTS                        0x0274 0x05BC 0x0000 0x3 0x0
 #define MX6SX_PAD_SD3_DATA7__UART3_DTE_RTS                        0x0274 0x05BC 0x083C 0x3 0x3
+#define MX6SX_PAD_SD3_DATA7__UART3_RTS_B                          0x0274 0x05BC 0x083C 0x3 0x3
 #define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5                        0x0274 0x05BC 0x0000 0x4 0x0
 #define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9                           0x0274 0x05BC 0x0000 0x5 0x0
 #define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN                 0x0274 0x05BC 0x0000 0x6 0x0
@@ -1536,6 +1560,7 @@
 #define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B                        0x0298 0x05E0 0x0000 0x1 0x0
 #define MX6SX_PAD_SD4_DATA6__UART5_DCE_RTS                        0x0298 0x05E0 0x084C 0x2 0x0
 #define MX6SX_PAD_SD4_DATA6__UART5_DTE_CTS                        0x0298 0x05E0 0x0000 0x2 0x0
+#define MX6SX_PAD_SD4_DATA6__UART5_CTS_B                          0x0298 0x05E0 0x0000 0x2 0x0
 #define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO                          0x0298 0x05E0 0x0734 0x3 0x0
 #define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6                        0x0298 0x05E0 0x0000 0x4 0x0
 #define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20                          0x0298 0x05E0 0x0000 0x5 0x0
@@ -1547,6 +1572,7 @@
 #define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08                       0x029C 0x05E4 0x0000 0x1 0x0
 #define MX6SX_PAD_SD4_DATA7__UART5_DCE_CTS                        0x029C 0x05E4 0x0000 0x2 0x0
 #define MX6SX_PAD_SD4_DATA7__UART5_DTE_RTS                        0x029C 0x05E4 0x084C 0x2 0x1
+#define MX6SX_PAD_SD4_DATA7__UART5_RTS_B                          0x029C 0x05E4 0x084C 0x2 0x1
 #define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0                           0x029C 0x05E4 0x073C 0x3 0x0
 #define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15                       0x029C 0x05E4 0x0000 0x4 0x0
 #define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21                          0x029C 0x05E4 0x0000 0x5 0x0
diff --git a/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi b/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi
index 549461df71e..caa0a8e6071 100644
--- a/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi
+++ b/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi
@@ -3,6 +3,91 @@
  * Copyright 2018 NXP
  */
 
+&{/aliases} {
+	video0 = &lcdif1;
+	video1 = &lcdif2;
+	display0 = &ldb;
+};
+
+&lcdif1 {
+	display = <&display0>;
+	status = "okay";
+
+	display0: display@0 {
+		bits-per-pixel = <24>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+				clock-frequency = <33500000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <89>;
+				hfront-porch = <164>;
+				vback-porch = <23>;
+				vfront-porch = <10>;
+				hsync-len = <10>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&lcdif2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	display1: display@1 {
+		bits-per-pixel = <18>;
+		bus-width = <18>;
+	};
+
+	port@0 {
+		reg = <0>;
+
+		lcdif2_lvds0: endpoint@0 {
+			remote-endpoint = <&ldb_lvds0>;
+		};
+	};
+};
+
+&{/soc/bus@2000000/ldb@20e0014/lvds-channel@0} {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	display-timings {
+		native-mode = <&timing1>;
+		timing1: hsd100pxn1 {
+			clock-frequency = <65000000>;
+			hactive = <1024>;
+			vactive = <768>;
+			hback-porch = <220>;
+			hfront-porch = <40>;
+			vback-porch = <21>;
+			vfront-porch = <7>;
+			hsync-len = <60>;
+			vsync-len = <10>;
+			hsync-active = <0>;
+			vsync-active = <0>;
+			de-active = <1>;
+			pixelclk-active = <0>;
+		};
+	};
+
+	port@0 {
+		reg = <0>;
+
+		ldb_lvds0: endpoint {
+			remote-endpoint = <&lcdif2_lvds0>;
+		};
+	};
+};
+
 &qspi1 {
 	num-cs = <2>;
 
@@ -14,3 +99,19 @@
 		compatible = "jedec,spi-nor";
 	};
 };
+
+&ethphy0 {
+	vddio0: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
+
+&ethphy1 {
+	vddio1: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
diff --git a/arch/arm/dts/imx6sx-sabreauto.dts b/arch/arm/dts/imx6sx-sabreauto.dts
index 9643d1fe064..d5df4da072a 100644
--- a/arch/arm/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/dts/imx6sx-sabreauto.dts
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -11,18 +12,86 @@
 #include "imx6sx.dtsi"
 
 / {
-	model = "Freescale i.MX6 SoloX Sabre Auto Board";
+	model = "i.MX6 SoloX Sabre Auto Board";
 	compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
 
+	backlight2 {
+		compatible = "pwm-backlight";
+		pwms = <&pwm4 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+		fb-names = "mxs-lcdif1";
+	};
+
+	clocks {
+		codec_osc: anaclk2 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <24576000>;
+		};
+	};
+
+	max7310_reset: max7310-reset {
+		compatible = "gpio-reset";
+		reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <1>;
+		#reset-cells = <0>;
+	};
+
 	memory {
 		reg = <0x80000000 0x80000000>;
 	};
 
+	pxp_v4l2_out {
+		compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
+		status = "okay";
+	};
+
 	regulators {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <0>;
 
+		reg_audio: cs42888_supply {
+			compatible = "regulator-fixed";
+			regulator-name = "cs42888_supply";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		si4763_vio1: vio1_tnr {
+			compatible = "regulator-fixed";
+			regulator-name = "vio1";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		si4763_vio2: vio2_tnr {
+			compatible = "regulator-fixed";
+			regulator-name = "vio2";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		si4763_vd: f3v3_tnr {
+			compatible = "regulator-fixed";
+			regulator-name = "vd";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		si4763_va: f5v_tnr {
+			compatible = "regulator-fixed";
+			regulator-name = "va";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+
 		vcc_sd3: regulator@0 {
 			compatible = "regulator-fixed";
 			reg = <0>;
@@ -34,51 +103,350 @@
 			gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
 			enable-active-high;
 		};
+
+		reg_usb_otg1_vbus: usb_otg1_vbus {
+			compatible = "regulator-fixed";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb_otg1_vbus>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 9 0>;
+			enable-active-high;
+		};
+
+		reg_usb_otg2_vbus: usb_otg2_vbus {
+			compatible = "regulator-fixed";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb_otg2_vbus>;
+			regulator-name = "usb_otg2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 12 0>;
+			enable-active-high;
+		};
+
+		reg_can_wake: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "can-wake";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_can_en: regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "can-en";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&reg_can_wake>;
+		};
+
+		reg_can_stby: regulator@3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "can-stby";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+			vin-supply = <&reg_can_en>;
+		};
+
+		reg_vref_3v3: regulator@4 {
+			compatible = "regulator-fixed";
+			regulator-name = "vref-3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+	};
+
+	sound-cs42888 {
+		compatible = "fsl,imx6-sabreauto-cs42888",
+			   "fsl,imx-audio-cs42888";
+		model = "imx-cs42888";
+		esai-controller = <&esai>;
+		asrc-controller = <&asrc>;
+		audio-codec = <&codec>;
+	};
+
+	sound-fm {
+		compatible = "fsl,imx-audio-si476x",
+			   "fsl,imx-tuner-si476x";
+		model = "imx-radio-si4763";
+
+		ssi-controller = <&ssi2>;
+		fm-controller = <&si476x_codec>;
+		mux-int-port = <2>;
+		mux-ext-port = <5>;
+	};
+
+	sound-spdif {
+		compatible = "fsl,imx-audio-spdif";
+		model = "imx-spdif";
+		spdif-controller = <&spdif>;
+		spdif-in;
 	};
 };
 
-&uart1 {
+&adc1 {
+	vref-supply = <&reg_vref_3v3>;
+	status = "okay";
+};
+
+&adc2 {
+	vref-supply = <&reg_vref_3v3>;
+	status = "okay";
+};
+
+&audmux {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart1>;
+	pinctrl-0 = <&pinctrl_audmux_3>;
 	status = "okay";
 };
 
-&usdhc3 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc3>;
-	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
-	bus-width = <8>;
-	cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
-	wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
-	keep-power-in-suspend;
-	wakeup-source;
-	vmmc-supply = <&vcc_sd3>;
+&clks {
+	assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>,
+			  <&clks IMX6SX_PLL4_BYPASS>,
+			  <&clks IMX6SX_CLK_PLL4_POST_DIV>;
+	assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>,
+				 <&clks IMX6SX_PLL4_BYPASS_SRC>;
+	assigned-clock-rates = <0>, <0>, <24576000>;
+};
+
+&esai {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_esai_2>;
+	assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>,
+		          <&clks IMX6SX_CLK_ESAI_EXTAL>;
+	assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <0>, <24576000>;
 	status = "okay";
 };
 
-&usdhc4 {
+&fec1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc4>;
-	bus-width = <8>;
-	cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
-	no-1-8-v;
-	keep-power-in-suspend;
-	wakeup-source;
+	pinctrl-0 = <&pinctrl_enet1_1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy1>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+	};
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2_1>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+};
+
+&flexcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	xceiver-supply = <&reg_can_stby>;
+	status = "okay";
+};
+
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	xceiver-supply = <&reg_can_stby>;
+	status = "okay";
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	nand-on-flash-bbt;
+	fsl,use-minimum-ecc;
 	status = "okay";
 };
 
 &i2c2 {
 	clock-frequency = <100000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c2_1>;
+	pinctrl-1 = <&pinctrl_i2c2_1_gpio>;
+	scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
 	status = "okay";
+
+	codec: cs42888@048 {
+		compatible = "cirrus,cs42888";
+		reg = <0x048>;
+		clocks = <&codec_osc 0>;
+		clock-names = "mclk";
+		VA-supply = <&reg_audio>;
+		VD-supply = <&reg_audio>;
+		VLS-supply = <&reg_audio>;
+		VLC-supply = <&reg_audio>;
+	};
+
+	egalax_ts@04 {
+		compatible = "eeti,egalax_ts";
+		reg = <0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_egalax_int>;
+		interrupt-parent = <&gpio6>;
+		interrupts = <22 2>;
+		wakeup-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>;
+	};
+
+	si4763: si4763@63 {
+		compatible = "si4761";
+		reg = <0x63>;
+		va-supply = <&si4763_va>;
+		vd-supply = <&si4763_vd>;
+		vio1-supply = <&si4763_vio1>;
+		vio2-supply = <&si4763_vio2>;
+		revision-a10; /* set to default A10 compatible command set */
+
+		si476x_codec: si476x-codec {
+			compatible = "si476x-codec";
+		};
+	};
+
+	max7322: gpio@68 {
+		compatible = "maxim,max7322";
+		reg = <0x68>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		out-default = /bits/ 16 <0x1 0x1>;
+	};
+
+	pmic: pfuze100@8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3b_reg: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-always-on;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
 };
 
 &i2c3 {
         clock-frequency = <100000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c3_2>;
+	pinctrl-1 = <&pinctrl_i2c3_2_gpio>;
+	scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
 	max7310_a: gpio@30 {
@@ -86,6 +454,7 @@
 		reg = <0x30>;
 		gpio-controller;
 		#gpio-cells = <2>;
+		resets = <&max7310_reset>;
 	};
 
 	max7310_b: gpio@32 {
@@ -93,9 +462,84 @@
 		reg = <0x32>;
 		gpio-controller;
 		#gpio-cells = <2>;
+		resets = <&max7310_reset>;
+	};
+
+	mma8451@1c {
+		compatible = "fsl,mma8451";
+		reg = <0x1c>;
+		position = <7>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <24 8>;
+		interrupt-route = <1>;
+	};
+
+	mag3110@0e {
+		compatible = "fsl,mag3110";
+		reg = <0x0e>;
+		position = <2>;
+		interrupt-parent = <&gpio6>;
+		interrupts = <6 1>;
+	};
+
+	isl29023@44 {
+		compatible = "fsl,isl29023";
+		reg = <0x44>;
+		rext = <499>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <23 2>;
+	};
+
+};
+
+&lcdif2 {
+	display = <&display1>;
+	disp-dev = "ldb";
+	status = "okay";
+
+	display1: display@1 {
+		bits-per-pixel = <16>;
+		bus-width = <18>;
+	};
+};
+
+&ldb {
+	status = "okay";
+
+	lvds-channel@0 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <18>;
+		crtc = "lcdif2";
+		status = "okay";
+
+		display-timings {
+			native-mode = <&timing1>;
+			timing1: hsd100pxn1 {
+				clock-frequency = <65000000>;
+				hactive = <1024>;
+				vactive = <768>;
+				hback-porch = <220>;
+				hfront-porch = <40>;
+				vback-porch = <21>;
+				vfront-porch = <7>;
+				hsync-len = <60>;
+				vsync-len = <10>;
+			};
+		};
 	};
 };
 
+&mlb {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_mlb_2>;
+	status = "okay";
+};
+
+&pcie {
+	reset-gpio = <&max7310_b 3 0>;
+	status = "okay";
+};
+
 &qspi1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_qspi1_1>;
@@ -119,8 +563,193 @@
 	};
 };
 
+&spdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spdif_3>;
+	status = "okay";
+};
+
+&ssi2 {
+	fsl,mode = "i2s-master";
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2_1>;
+	status = "okay";
+};
+
+&uart5 { /* for bluetooth */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart5_1>;
+	fsl,uart-has-rtscts;
+	status = "okay";
+	/* for DTE mode, add below change */
+	/* fsl,dte-mode;*/
+	/* pinctrl-0 = <&pinctrl_uart5dte_1>; */
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_otg1_id>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usbotg2 {
+	vbus-supply = <&reg_usb_otg2_vbus>;
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	bus-width = <8>;
+	cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+	keep-power-in-suspend;
+	wakeup-source;
+	vmmc-supply = <&vcc_sd3>;
+	status = "okay";
+};
+
+&usdhc4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc4>;
+	bus-width = <8>;
+	cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
+	no-1-8-v;
+	keep-power-in-suspend;
+	wakeup-source;
+	status = "okay";
+};
+
+&pwm4 {
+	#pwm-cells = <2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm4_0>;
+	status = "okay";
+};
+
+&pxp {
+	status = "okay";
+};
+
 &iomuxc {
 	imx6x-sabreauto {
+		pinctrl_audmux_3: audmux-3 {
+			fsl,pins = <
+				MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC    0x130b0
+				MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS   0x130b0
+				MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD  0x130b0
+			>;
+		};
+
+		pinctrl_egalax_int: egalax_intgrp {
+			fsl,pins = <
+				MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22      0x80000000
+			>;
+		};
+
+		pinctrl_enet1_1: enet1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_ENET1_MDIO__ENET1_MDIO        0xa0b1
+				MX6SX_PAD_ENET1_MDC__ENET1_MDC          0xa0b1
+				MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC   0xa0b9
+				MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0   0xa0b1
+				MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1   0xa0b1
+				MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2   0xa0b1
+				MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3   0xa0b1
+				MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN    0xa0b1
+				MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK      0x3081
+				MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0   0x3081
+				MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1   0x3081
+				MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2   0x3081
+				MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3   0x3081
+				MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN    0x3081
+			>;
+		};
+
+		pinctrl_enet2_1: enet2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC   0xa0b9
+				MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0   0xa0b1
+				MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1   0xa0b1
+				MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2   0xa0b1
+				MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3   0xa0b1
+				MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN    0xa0b1
+				MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK      0x3081
+				MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0   0x3081
+				MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1   0x3081
+				MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2   0x3081
+				MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3   0x3081
+				MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN    0x3081
+			>;
+		};
+
+		pinctrl_esai_2: esaigrp-2 {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK   0x1b030
+				MX6SX_PAD_CSI_DATA01__ESAI_TX_FS    0x1b030
+				MX6SX_PAD_CSI_HSYNC__ESAI_TX0       0x1b030
+				MX6SX_PAD_CSI_DATA04__ESAI_TX1      0x1b030
+				MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3  0x1b030
+				MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2  0x1b030
+				MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK   0x1b030
+				MX6SX_PAD_CSI_DATA03__ESAI_RX_FS    0x1b030
+				MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0   0x1b030
+				MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1  0x1b030
+			>;
+		};
+
+		pinctrl_flexcan1: flexcan1grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1B_DQS__CAN1_TX   0x1b020
+				MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX	0x1b020
+			>;
+		};
+
+		pinctrl_flexcan2: flexcan2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
+				MX6SX_PAD_QSPI1A_DQS__CAN2_TX	0x1b020
+			>;
+		};
+
+		pinctrl_gpmi_nand_1: gpmi-nand-1 {
+			fsl,pins = <
+				MX6SX_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
+				MX6SX_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
+				MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
+				MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
+				MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
+				MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B     0xb0b1
+				MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
+				MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
+				MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
+				MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
+				MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
+				MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
+				MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
+				MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
+				MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
+				MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
+			>;
+		};
+
 		pinctrl_i2c2_1: i2c2grp-1 {
 			fsl,pins = <
 				MX6SX_PAD_GPIO1_IO03__I2C2_SDA          0x4001b8b1
@@ -128,6 +757,13 @@
 			>;
 		};
 
+		pinctrl_i2c2_1_gpio: i2c2grp-1-gpio {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3        0x1b8b1
+				MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2        0x1b8b1
+			>;
+		};
+
 		pinctrl_i2c3_2: i2c3grp-2 {
 			fsl,pins = <
 				MX6SX_PAD_KEY_ROW4__I2C3_SDA            0x4001b8b1
@@ -135,6 +771,27 @@
 			>;
 		};
 
+		pinctrl_i2c3_2_gpio: i2c3grp-2-gpio {
+			fsl,pins = <
+				MX6SX_PAD_KEY_ROW4__GPIO2_IO_19         0x1b8b1
+				MX6SX_PAD_KEY_COL4__GPIO2_IO_14         0x1b8b1
+			>;
+		};
+
+		pinctrl_mlb_2: mlbgrp-2 {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_RX_CLK__MLB_DATA        0x31
+				MX6SX_PAD_ENET2_CRS__MLB_SIG            0x31
+				MX6SX_PAD_ENET2_TX_CLK__MLB_CLK         0x31
+			>;
+		};
+
+		pinctrl_pwm4_0: pwm4grp-0 {
+			fsl,pins = <
+				MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
+			>;
+		};
+
 		pinctrl_qspi1_1: qspi1grp_1 {
 			fsl,pins = <
 				MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0  0x70a1
@@ -152,6 +809,12 @@
 			>;
 		};
 
+		pinctrl_spdif_3: spdifgrp-3 {
+			fsl,pins = <
+				MX6SX_PAD_ENET2_COL__SPDIF_IN           0x1b0b0
+			>;
+		};
+
 		pinctrl_uart1: uart1grp {
 			fsl,pins = <
 				MX6SX_PAD_GPIO1_IO04__UART1_TX		0x1b0b1
@@ -159,6 +822,49 @@
 			>;
 		};
 
+		pinctrl_uart2_1: uart2grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
+				MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
+			>;
+		};
+
+		pinctrl_uart5_1: uart5grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_KEY_ROW3__UART5_RX    0x1b0b1
+				MX6SX_PAD_KEY_COL3__UART5_TX    0x1b0b1
+				MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
+				MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
+			>;
+		};
+
+		pinctrl_uart5dte_1: uart5dtegrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_KEY_ROW3__UART5_TX	0x1b0b1
+				MX6SX_PAD_KEY_COL3__UART5_RX	0x1b0b1
+				MX6SX_PAD_KEY_ROW2__UART5_RTS_B	0x1b0b1
+				MX6SX_PAD_KEY_COL2__UART5_CTS_B	0x1b0b1
+			>;
+		};
+
+		pinctrl_usb_otg1_vbus: usbotg1vbusgrp {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9     0x10b0
+			>;
+		};
+
+		pinctrl_usb_otg1_id: usbotg1idgrp {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
+			>;
+		};
+
+		pinctrl_usb_otg2_vbus: usbotg2vbusgrp {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12    0x10b0
+			>;
+		};
+
 		pinctrl_usdhc3: usdhc3grp {
 			fsl,pins = <
 				MX6SX_PAD_SD3_CMD__USDHC3_CMD		0x17059
@@ -171,8 +877,8 @@
 				MX6SX_PAD_SD3_DATA5__USDHC3_DATA5	0x17059
 				MX6SX_PAD_SD3_DATA6__USDHC3_DATA6	0x17059
 				MX6SX_PAD_SD3_DATA7__USDHC3_DATA7	0x17059
-				MX6SX_PAD_KEY_COL0__GPIO2_IO_10		0x17059 /* CD */
-				MX6SX_PAD_KEY_ROW0__GPIO2_IO_15		0x17059 /* WP */
+				MX6SX_PAD_USB_H_DATA__GPIO7_IO_10       0x17059 /* CD */
+				MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19      0x17059 /* WP */
 			>;
 		};
 
@@ -208,14 +914,13 @@
 
 		pinctrl_usdhc4: usdhc4grp {
 			fsl,pins = <
-				MX6SX_PAD_SD4_CMD__USDHC4_CMD		0x17059
-				MX6SX_PAD_SD4_CLK__USDHC4_CLK		0x10059
-				MX6SX_PAD_SD4_DATA0__USDHC4_DATA0	0x17059
-				MX6SX_PAD_SD4_DATA1__USDHC4_DATA1	0x17059
-				MX6SX_PAD_SD4_DATA2__USDHC4_DATA2	0x17059
-				MX6SX_PAD_SD4_DATA3__USDHC4_DATA3	0x17059
-				MX6SX_PAD_SD4_DATA7__GPIO6_IO_21	0x17059 /* CD */
-				MX6SX_PAD_SD4_DATA6__GPIO6_IO_20	0x17059 /* WP */
+				MX6SX_PAD_SD4_CMD__USDHC4_CMD		0x17071
+				MX6SX_PAD_SD4_CLK__USDHC4_CLK		0x10071
+				MX6SX_PAD_SD4_DATA0__USDHC4_DATA0	0x17071
+				MX6SX_PAD_SD4_DATA1__USDHC4_DATA1	0x17071
+				MX6SX_PAD_SD4_DATA2__USDHC4_DATA2	0x17071
+				MX6SX_PAD_SD4_DATA3__USDHC4_DATA3	0x17071
+				MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11	0x17071 /* CD */
 			>;
 		};
 
@@ -224,5 +929,48 @@
 				MX6SX_PAD_KEY_COL1__GPIO2_IO_11		0x17059
 			>;
 		};
+
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
+			>;
+		};
+	};
+};
+&csi2 {
+	status = "okay";
+	port {
+		csi2_ep: endpoint {
+			remote-endpoint = <&vadc_ep>;
+		};
+	};
+};
+
+&dcic1 {
+	dcic_id = <0>;
+	dcic_mux = "dcic-lcdif1";
+	status = "okay";
+};
+
+&dcic2 {
+	dcic_id = <1>;
+	dcic_mux = "dcic-lvds";
+	status = "okay";
+};
+
+&vadc {
+	vadc_in = <0>;
+	csi_id = <1>;
+	status = "okay";
+	port {
+		vadc_ep: endpoint {
+			remote-endpoint = <&csi2_ep>;
+		};
 	};
 };
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+};
diff --git a/arch/arm/dts/imx6sx-sdb-emmc.dts b/arch/arm/dts/imx6sx-sdb-emmc.dts
new file mode 100644
index 00000000000..c9a0063d489
--- /dev/null
+++ b/arch/arm/dts/imx6sx-sdb-emmc.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6sx-sdb.dts"
+
+/*
+ * The eMMC chip on imx6sx sdb board is DNP by default.
+ * Need do hw rework to burn the eMMC4.5 chip on the eMMC socket on uSDHC4
+ * and connect eMMC signals as well as disconnect BOOT SD CARD slot signals
+ */
+&usdhc4 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc4_1>;
+	pinctrl-1 = <&pinctrl_usdhc4_1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc4_1_200mhz>;
+	bus-width = <8>;
+	auto-cmd23-broken;
+	/*
+	 * overwrite cd-gpios and wp-gpios since they are reused as eMMC DATA
+	 * signals after rework
+	 */
+	cd-gpios = <>;
+	wp-gpios = <>;
+	non-removable;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6sx-sdb-u-boot.dtsi b/arch/arm/dts/imx6sx-sdb-u-boot.dtsi
new file mode 100644
index 00000000000..7e287db2f81
--- /dev/null
+++ b/arch/arm/dts/imx6sx-sdb-u-boot.dtsi
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+&{/aliases} {
+	video0 = &lcdif1;
+	video1 = &lcdif2;
+	display0 = &ldb;
+};
+
+&lcdif1 {
+	status = "okay";
+
+	display0: display@0 {
+		bits-per-pixel = <24>;
+		bus-width = <24>;
+	};
+};
+
+&lcdif2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	display1: display@1 {
+		bits-per-pixel = <18>;
+		bus-width = <18>;
+	};
+
+	port@0 {
+		reg = <0>;
+
+		lcdif2_lvds0: endpoint@0 {
+			remote-endpoint = <&ldb_lvds0>;
+		};
+	};
+};
+
+&{/soc/bus@2000000/ldb@20e0014/lvds-channel@0} {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	display-timings {
+		native-mode = <&timing1>;
+		timing1: hsd100pxn1 {
+			clock-frequency = <65000000>;
+			hactive = <1024>;
+			vactive = <768>;
+			hback-porch = <220>;
+			hfront-porch = <40>;
+			vback-porch = <21>;
+			vfront-porch = <7>;
+			hsync-len = <60>;
+			vsync-len = <10>;
+			hsync-active = <0>;
+			vsync-active = <0>;
+			de-active = <1>;
+			pixelclk-active = <0>;
+		};
+	};
+
+	port@0 {
+		reg = <0>;
+
+		ldb_lvds0: endpoint {
+			remote-endpoint = <&lcdif2_lvds0>;
+		};
+	};
+};
+
+&ethphy1 {
+	vddio1: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
+
+&ethphy2 {
+	vddio2: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
diff --git a/arch/arm/dts/imx6sx-sdb.dts b/arch/arm/dts/imx6sx-sdb.dts
index 5a63ca61572..6e3d1b6f085 100644
--- a/arch/arm/dts/imx6sx-sdb.dts
+++ b/arch/arm/dts/imx6sx-sdb.dts
@@ -5,14 +5,16 @@
 #include "imx6sx-sdb.dtsi"
 
 / {
-	model = "Freescale i.MX6 SoloX SDB RevB Board";
+	model = "NXP i.MX6 SoloX SDB RevB Board";
 };
 
 &i2c1 {
 	clock-frequency = <100000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
-	status = "okay";
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
 
 	pmic: pfuze100@8 {
 		compatible = "fsl,pfuze200";
@@ -103,6 +105,23 @@
 	};
 };
 
+&cpu0 {
+	operating-points = <
+		/* kHz    uV */
+		996000  1250000
+		792000  1175000
+		396000  1175000
+	>;
+	fsl,soc-operating-points = <
+		/* ARM kHz      SOC uV */
+		996000  1250000
+		792000  1175000
+		396000  1175000
+	>;
+
+	fsl,arm-soc-shared = <1>;
+};
+
 &qspi2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_qspi2>;
@@ -114,7 +133,7 @@
 		compatible = "micron,n25q256a", "jedec,spi-nor";
 		spi-max-frequency = <29000000>;
 		spi-rx-bus-width = <4>;
-		spi-tx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
 		reg = <0>;
 	};
 
@@ -124,17 +143,19 @@
 		compatible = "micron,n25q256a", "jedec,spi-nor";
 		spi-max-frequency = <29000000>;
 		spi-rx-bus-width = <4>;
-		spi-tx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
 		reg = <2>;
 	};
 };
 
 &reg_arm {
 	vin-supply = <&sw1a_reg>;
+	regulator-allow-bypass;
 };
 
 &reg_soc {
 	vin-supply = <&sw1a_reg>;
+	regulator-allow-bypass;
 };
 
 &reg_vdd1p1 {
diff --git a/arch/arm/dts/imx6sx-sdb.dtsi b/arch/arm/dts/imx6sx-sdb.dtsi
index f6972deb5e3..8c4589dedd9 100644
--- a/arch/arm/dts/imx6sx-sdb.dtsi
+++ b/arch/arm/dts/imx6sx-sdb.dtsi
@@ -9,7 +9,7 @@
 #include "imx6sx.dtsi"
 
 / {
-	model = "Freescale i.MX6 SoloX SDB Board";
+	model = "NXP i.MX6 SoloX SDB Board";
 	compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
 
 	chosen {
@@ -28,6 +28,14 @@
 		default-brightness-level = <6>;
 	};
 
+	backlight2 {
+		compatible = "pwm-backlight";
+		pwms = <&pwm4 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+		fb-names = "mxs-lcdif1";
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 		pinctrl-names = "default";
@@ -56,6 +64,7 @@
 		regulator-min-microvolt = <3000000>;
 		regulator-max-microvolt = <3000000>;
 		gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+		off-on-delay-us = <20000>;
 		enable-active-high;
 	};
 
@@ -93,6 +102,7 @@
 		regulator-name = "lcd-3v3";
 		gpio = <&gpio3 27 0>;
 		enable-active-high;
+		status = "disabled";
 	};
 
 	reg_peri_3v3: regulator-peri-3v3 {
@@ -151,10 +161,24 @@
 		regulator-max-microvolt = <3300000>;
 	};
 
+	reg_vref_3v3: regulator-adc-verf {
+		compatible = "regulator-fixed";
+		regulator-name = "vref-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	pxp_v4l2_out {
+		compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
+		status = "okay";
+	};
+
 	sound {
 		compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_hp>;
 		model = "wm8962-audio";
-		ssi-controller = <&ssi2>;
+		audio-cpu = <&ssi2>;
 		audio-codec = <&codec>;
 		audio-routing =
 			"Headphone Jack", "HPOUTL",
@@ -165,28 +189,73 @@
 			"IN3R", "AMIC";
 		mux-int-port = <2>;
 		mux-ext-port = <6>;
+		hp-det-gpio = <&gpio1 17 GPIO_ACTIVE_LOW>;
 	};
 
-	panel {
-		compatible = "sii,43wvf1g";
-		backlight = <&backlight_display>;
-		dvdd-supply = <&reg_lcd_3v3>;
-		avdd-supply = <&reg_lcd_5v>;
+	sound-spdif {
+		compatible = "fsl,imx-audio-spdif",
+			   "fsl,imx6sx-sdb-spdif";
+		model = "imx-spdif";
+		spdif-controller = <&spdif>;
+		spdif-out;
+	};
 
-		port {
-			panel_in: endpoint {
-				remote-endpoint = <&display_out>;
-			};
-		};
+	sii902x_reset: sii902x-reset {
+		compatible = "gpio-reset";
+		reset-gpios = <&gpio3 27 1>;
+		reset-delay-us = <100000>;
+		#reset-cells = <0>;
+		status = "disabled";
 	};
 };
 
+&adc1 {
+	vref-supply = <&reg_vref_3v3>;
+	status = "okay";
+};
+
+&adc2 {
+	vref-supply = <&reg_vref_3v3>;
+	status = "okay";
+};
+
 &audmux {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_audmux>;
 	status = "okay";
 };
 
+&csi1 {
+	status = "okay";
+
+	port {
+		csi1_ep: endpoint {
+			remote-endpoint = <&ov5640_ep>;
+		};
+	};
+};
+
+&csi2 {
+	status = "okay";
+	port {
+		csi2_ep: endpoint {
+			remote-endpoint = <&vadc_ep>;
+		};
+	};
+};
+
+&dcic1 {
+	dcic_id = <0>;
+	dcic_mux = "dcic-lcdif1";
+	status = "okay";
+};
+
+&dcic2 {
+	dcic_id = <1>;
+	dcic_mux = "dcic-lvds";
+	status = "okay";
+};
+
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet1>;
@@ -194,6 +263,7 @@
 	phy-mode = "rgmii-id";
 	phy-handle = <&ethphy1>;
 	phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
+	fsl,magic-packet;
 	status = "okay";
 
 	mdio {
@@ -202,10 +272,12 @@
 
 		ethphy1: ethernet-phy@1 {
 			reg = <1>;
+			qca,disable-smarteee;
 		};
 
 		ethphy2: ethernet-phy@2 {
 			reg = <2>;
+			qca,disable-smarteee;
 		};
 	};
 };
@@ -213,8 +285,9 @@
 &fec2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet2>;
-	phy-mode = "rgmii";
+	phy-mode = "rgmii-id";
 	phy-handle = <&ethphy2>;
+	fsl,magic-packet;
 	status = "okay";
 };
 
@@ -232,17 +305,116 @@
 	status = "okay";
 };
 
+&gpc {
+	fsl,ldo-bypass = <1>;
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	ov5640: ov5640@3c {
+		compatible = "ovti,ov5640";
+		reg = <0x3c>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_csi_0>;
+		clocks = <&clks IMX6SX_CLK_CSI>;
+		clock-names = "csi_mclk";
+		AVDD-supply = <&vgen3_reg>;  /* 2.8v */
+		DVDD-supply = <&vgen2_reg>;  /* 1.5v*/
+		pwn-gpios = <&gpio3 28 1>;
+		rst-gpios = <&gpio3 27 0>;
+		csi_id = <0>;
+		mclk = <24000000>;
+		mclk_source = <0>;
+		port {
+			ov5640_ep: endpoint {
+				remote-endpoint = <&csi1_ep>;
+			};
+		};
+	};
+
+	sii902x@39 {
+		compatible = "SiI,sii902x";
+		interrupt-parent = <&gpio4>;
+		interrupts = <21 2>;
+		mode_str ="1280x720M@60";
+		bits-per-pixel = <16>;
+		resets = <&sii902x_reset>;
+		reg = <0x39>;
+		status = "disabled";
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	egalax_ts@04 {
+		compatible = "eeti,egalax_ts";
+		reg = <0x04>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_egalax_int>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <19 2>;
+		wakeup-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+	};
+};
+
 &i2c3 {
 	clock-frequency = <100000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
 	status = "okay";
+
+	isl29023@44 {
+		compatible = "fsl,isl29023";
+		reg = <0x44>;
+		rext = <499>;
+		interrupt-parent = <&gpio6>;
+		interrupts = <5 1>;
+		shared-interrupt;
+	};
+
+	mag3110@e {
+		compatible = "fsl,mag3110";
+		reg = <0xe>;
+		position = <2>;
+		interrupt-parent = <&gpio6>;
+		interrupts = <5 1>;
+		shared-interrupt;
+	};
+
+	mma8451@1c {
+		compatible = "fsl,mma8451";
+		reg = <0x1c>;
+		position = <1>;
+		interrupt-parent = <&gpio6>;
+		interrupts = <2 8>;
+		interrupt-route = <2>;
+	};
 };
 
 &i2c4 {
 	clock-frequency = <100000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c4>;
+	pinctrl-1 = <&pinctrl_i2c4_gpio>;
+	scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
 	codec: wm8962@1a {
@@ -271,21 +443,87 @@
 &lcdif1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lcd>;
+	lcd-supply = <&reg_lcd_3v3>;
+	display = <&display0>;
+	status = "disabled";
+
+	display0: display@0 {
+		bits-per-pixel = <16>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+				clock-frequency = <33500000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <89>;
+				hfront-porch = <164>;
+				vback-porch = <23>;
+				vfront-porch = <10>;
+				hsync-len = <10>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&lcdif2 {
+	display = <&display1>;
+	disp-dev = "ldb";
 	status = "okay";
+	display1: display@1 {
+		bits-per-pixel = <16>;
+		bus-width = <18>;
+	};
+};
 
-	port {
-		display_out: endpoint {
-			remote-endpoint = <&panel_in>;
+&ldb {
+	status = "okay";
+	lvds-channel@0 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <18>;
+		crtc = "lcdif2";
+		status = "okay";
+		display-timings {
+			native-mode = <&timing1>;
+			timing1: hsd100pxn1 {
+				clock-frequency = <65000000>;
+				hactive = <1024>;
+				vactive = <768>;
+				hback-porch = <220>;
+				hfront-porch = <40>;
+				vback-porch = <21>;
+				vfront-porch = <7>;
+				hsync-len = <60>;
+				vsync-len = <10>;
+			};
 		};
 	};
 };
 
 &pwm3 {
+	#pwm-cells = <2>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm3>;
 	status = "okay";
 };
 
+&pwm4 {
+	#pwm-cells = <2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm4>;
+	status = "okay";
+};
+
+&pxp {
+	status = "okay";
+};
+
 &snvs_poweroff {
 	status = "okay";
 };
@@ -296,7 +534,22 @@
 	status = "disabled";
 };
 
+&spdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_spdif>;
+	assigned-clocks = <&clks IMX6SX_CLK_SPDIF_PODF>;
+	assigned-clock-rates = <24576000>;
+	status = "okay";
+};
+
 &ssi2 {
+	assigned-clocks = <&clks IMX6SX_CLK_PLL4>,
+			  <&clks IMX6SX_PLL4_BYPASS>,
+			  <&clks IMX6SX_CLK_SSI2_SEL>;
+	assigned-clock-parents = <&clks IMX6SX_CLK_OSC>,
+				 <&clks IMX6SX_CLK_PLL4>,
+				 <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <737280000>, <0>, <0>;
 	status = "okay";
 };
 
@@ -311,6 +564,9 @@
 	pinctrl-0 = <&pinctrl_uart5>;
 	uart-has-rtscts;
 	status = "okay";
+	/* for DTE mode, add below change */
+	/* fsl,dte-mode;*/
+	/* pinctrl-0 = <&pinctrl_uart5dte_1>; */
 };
 
 &usbotg1 {
@@ -374,6 +630,24 @@
 
 &iomuxc {
 	imx6x-sdb {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_hog &pinctrl_can_gpios>;
+
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059
+				MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0xb000
+				MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059
+			>;
+		};
+
+		pinctrl_can_gpios: can-gpios {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059
+				MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059
+			>;
+		};
+
 		pinctrl_audmux: audmuxgrp {
 			fsl,pins = <
 				MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC	0x130b0
@@ -384,11 +658,38 @@
 			>;
 		};
 
+		pinctrl_csi_0: csigrp-0 {
+			fsl,pins = <
+				MX6SX_PAD_LCD1_DATA07__CSI1_MCLK	0x110b0
+				MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK	0x110b0
+				MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC	0x110b0
+				MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC	0x110b0
+				MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0	0x110b0
+				MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1	0x110b0
+				MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2	0x110b0
+				MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3	0x110b0
+				MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4	0x110b0
+				MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5	0x110b0
+				MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6	0x110b0
+				MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7	0x110b0
+				MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8	0x110b0
+				MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9	0x110b0
+				MX6SX_PAD_LCD1_RESET__GPIO3_IO_27	0x80000000
+				MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28	0x80000000
+			>;
+		};
+
+		pinctrl_egalax_int: egalax_intgrp {
+			fsl,pins = <
+				MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x80000000
+			>;
+		};
+
 		pinctrl_enet1: enet1grp {
 			fsl,pins = <
 				MX6SX_PAD_ENET1_MDIO__ENET1_MDIO	0xa0b1
 				MX6SX_PAD_ENET1_MDC__ENET1_MDC		0xa0b1
-				MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC	0xa0b1
+				MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC	0xa0b9
 				MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0	0xa0b1
 				MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1	0xa0b1
 				MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2	0xa0b1
@@ -450,6 +751,12 @@
 			>;
 		};
 
+		pinctrl_hp: hpgrp {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059
+			>;
+		};
+
 		pinctrl_i2c1: i2c1grp {
 			fsl,pins = <
 				MX6SX_PAD_GPIO1_IO01__I2C1_SDA		0x4001b8b1
@@ -457,10 +764,37 @@
 			>;
 		};
 
+		pinctrl_i2c1_gpio: i2c1grp-gpio {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1        0x1b8b1
+				MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0        0x1b8b1
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
+				MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c2_gpio: i2c2grp-gpio {
+			fsl,pins = <
+				MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3        0x1b8b1
+				MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2        0x1b8b1
+			>;
+		};
 		pinctrl_i2c3: i2c3grp {
 			fsl,pins = <
-				MX6SX_PAD_KEY_ROW4__I2C3_SDA		0x4001b8b1
-				MX6SX_PAD_KEY_COL4__I2C3_SCL		0x4001b8b1
+				MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
+				MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c3_gpio: i2c3grp-gpio {
+			fsl,pins = <
+				MX6SX_PAD_KEY_ROW4__GPIO2_IO_19         0x1b8b1
+				MX6SX_PAD_KEY_COL4__GPIO2_IO_14         0x1b8b1
 			>;
 		};
 
@@ -471,6 +805,13 @@
 			>;
 		};
 
+		pinctrl_i2c4_gpio: i2c4grp-gpio {
+			fsl,pins = <
+				MX6SX_PAD_CSI_DATA07__GPIO1_IO_21       0x1b8b1
+				MX6SX_PAD_CSI_DATA06__GPIO1_IO_20       0x1b8b1
+			>;
+		};
+
 		pinctrl_lcd: lcdgrp {
 			fsl,pins = <
 				MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
@@ -505,6 +846,13 @@
 			>;
 		};
 
+		pinctrl_mqs: mqsgrp {
+			fsl,pins = <
+				MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0
+				MX6SX_PAD_SD2_CMD__MQS_LEFT  0x120b0
+			>;
+		};
+
 		pinctrl_pcie: pciegrp {
 			fsl,pins = <
 				MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
@@ -529,6 +877,12 @@
 			>;
 		};
 
+		pinctrl_pwm4: pwm4grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
+			>;
+		};
+
 		pinctrl_qspi2: qspi2grp {
 			fsl,pins = <
 				MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0     0x70f1
@@ -562,19 +916,34 @@
 			>;
 		};
 
+		pinctrl_spdif: spdifgrp {
+			fsl,pins = <
+				MX6SX_PAD_SD4_DATA4__SPDIF_OUT          0x1b0b0
+			>;
+		};
+
 		pinctrl_uart1: uart1grp {
 			fsl,pins = <
-				MX6SX_PAD_GPIO1_IO04__UART1_TX		0x1b0b1
-				MX6SX_PAD_GPIO1_IO05__UART1_RX		0x1b0b1
+				MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX	0x1b0b1
+				MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX	0x1b0b1
 			>;
 		};
 
 		pinctrl_uart5: uart5grp {
 			fsl,pins = <
-				MX6SX_PAD_KEY_ROW3__UART5_RX		0x1b0b1
-				MX6SX_PAD_KEY_COL3__UART5_TX		0x1b0b1
-				MX6SX_PAD_KEY_ROW2__UART5_CTS_B		0x1b0b1
-				MX6SX_PAD_KEY_COL2__UART5_RTS_B		0x1b0b1
+				MX6SX_PAD_KEY_ROW3__UART5_DCE_RX	0x1b0b1
+				MX6SX_PAD_KEY_COL3__UART5_DCE_TX	0x1b0b1
+				MX6SX_PAD_KEY_ROW2__UART5_DCE_CTS	0x1b0b1
+				MX6SX_PAD_KEY_COL2__UART5_DCE_RTS	0x1b0b1
+			>;
+		};
+
+		pinctrl_uart5dte_1: uart5dtegrp-1 {
+			fsl,pins = <
+				MX6SX_PAD_KEY_ROW3__UART5_TX		0x1b0b1
+				MX6SX_PAD_KEY_COL3__UART5_RX		0x1b0b1
+				MX6SX_PAD_KEY_ROW2__UART5_RTS_B		0x1b0b1
+				MX6SX_PAD_KEY_COL2__UART5_CTS_B		0x1b0b1
 			>;
 		};
 
@@ -667,6 +1036,51 @@
 			>;
 		};
 
+		pinctrl_usdhc4_1: usdhc4grp-1 {
+			fsl,pins = <
+				MX6SX_PAD_SD4_CMD__USDHC4_CMD		0x17059
+				MX6SX_PAD_SD4_CLK__USDHC4_CLK		0x10059
+				MX6SX_PAD_SD4_DATA0__USDHC4_DATA0	0x17059
+				MX6SX_PAD_SD4_DATA1__USDHC4_DATA1	0x17059
+				MX6SX_PAD_SD4_DATA2__USDHC4_DATA2	0x17059
+				MX6SX_PAD_SD4_DATA3__USDHC4_DATA3	0x17059
+				MX6SX_PAD_SD4_DATA4__USDHC4_DATA4	0x17059
+				MX6SX_PAD_SD4_DATA5__USDHC4_DATA5	0x17059
+				MX6SX_PAD_SD4_DATA6__USDHC4_DATA6	0x17059
+				MX6SX_PAD_SD4_DATA7__USDHC4_DATA7	0x17059
+			>;
+		};
+
+		pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz {
+			fsl,pins = <
+				MX6SX_PAD_SD4_CMD__USDHC4_CMD		0x170b9
+				MX6SX_PAD_SD4_CLK__USDHC4_CLK		0x100b9
+				MX6SX_PAD_SD4_DATA0__USDHC4_DATA0	0x170b9
+				MX6SX_PAD_SD4_DATA1__USDHC4_DATA1	0x170b9
+				MX6SX_PAD_SD4_DATA2__USDHC4_DATA2	0x170b9
+				MX6SX_PAD_SD4_DATA3__USDHC4_DATA3	0x170b9
+				MX6SX_PAD_SD4_DATA4__USDHC4_DATA4	0x170b9
+				MX6SX_PAD_SD4_DATA5__USDHC4_DATA5	0x170b9
+				MX6SX_PAD_SD4_DATA6__USDHC4_DATA6	0x170b9
+				MX6SX_PAD_SD4_DATA7__USDHC4_DATA7	0x170b9
+			>;
+		};
+
+		pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz {
+			fsl,pins = <
+				MX6SX_PAD_SD4_CMD__USDHC4_CMD		0x170f9
+				MX6SX_PAD_SD4_CLK__USDHC4_CLK		0x100f9
+				MX6SX_PAD_SD4_DATA0__USDHC4_DATA0	0x170f9
+				MX6SX_PAD_SD4_DATA1__USDHC4_DATA1	0x170f9
+				MX6SX_PAD_SD4_DATA2__USDHC4_DATA2	0x170f9
+				MX6SX_PAD_SD4_DATA3__USDHC4_DATA3	0x170f9
+				MX6SX_PAD_SD4_DATA4__USDHC4_DATA4	0x170f9
+				MX6SX_PAD_SD4_DATA5__USDHC4_DATA5	0x170f9
+				MX6SX_PAD_SD4_DATA6__USDHC4_DATA6	0x170f9
+				MX6SX_PAD_SD4_DATA7__USDHC4_DATA7	0x170f9
+			>;
+		};
+
 		pinctrl_wdog: wdoggrp {
 			fsl,pins = <
 				MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
@@ -674,3 +1088,14 @@
 		};
 	};
 };
+
+&vadc {
+	vadc_in = <0>;
+	csi_id = <1>;
+	status = "okay";
+	port {
+		vadc_ep: endpoint {
+			remote-endpoint = <&csi2_ep>;
+		};
+	};
+};
diff --git a/arch/arm/dts/imx6sx-softing-vining-2000.dts b/arch/arm/dts/imx6sx-softing-vining-2000.dts
index 78dd5755a37..40099250f39 100644
--- a/arch/arm/dts/imx6sx-softing-vining-2000.dts
+++ b/arch/arm/dts/imx6sx-softing-vining-2000.dts
@@ -516,18 +516,21 @@
 };
 
 &pwm1 {
+	#pwm-cells = <2>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm1>;
 	status = "okay";
 };
 
 &pwm2 {
+	#pwm-cells = <2>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm2>;
 	status = "okay";
 };
 
 &pwm6 {
+	#pwm-cells = <2>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm6>;
 	status = "okay";
diff --git a/arch/arm/dts/imx6sx.dtsi b/arch/arm/dts/imx6sx.dtsi
index 8d2d396ad13..c377ae737a6 100644
--- a/arch/arm/dts/imx6sx.dtsi
+++ b/arch/arm/dts/imx6sx.dtsi
@@ -1,6 +1,11 @@
-// SPDX-License-Identifier: GPL-2.0
-//
-// Copyright 2014 Freescale Semiconductor, Inc.
+/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
 
 #include <dt-bindings/clock/imx6sx-clock.h>
 #include <dt-bindings/gpio/gpio.h>
@@ -44,13 +49,22 @@
 		serial3 = &uart4;
 		serial4 = &uart5;
 		serial5 = &uart6;
-		spi0 = &ecspi1;
-		spi1 = &ecspi2;
-		spi2 = &ecspi3;
-		spi3 = &ecspi4;
-		spi4 = &ecspi5;
+		spi0 = &qspi1;
+		spi1 = &qspi2;
+		spi2 = &ecspi1;
+		spi3 = &ecspi2;
+		spi4 = &ecspi3;
+		spi5 = &ecspi4;
+		spi6 = &ecspi5;
 		usbphy0 = &usbphy1;
 		usbphy1 = &usbphy2;
+		lcdif0 = &lcdif1;
+		lcdif1 = &lcdif2;
+		usb0 = &usbotg1;
+		usb1 = &usbotg2;
+		pci0 = &pcie;
+		usbgadget0 = &usbg1;
+		usbgadget1 = &usbg2;
 	};
 
 	cpus {
@@ -82,14 +96,34 @@
 				 <&clks IMX6SX_CLK_PLL2_PFD2>,
 				 <&clks IMX6SX_CLK_STEP>,
 				 <&clks IMX6SX_CLK_PLL1_SW>,
-				 <&clks IMX6SX_CLK_PLL1_SYS>;
+				 <&clks IMX6SX_CLK_PLL1_SYS>,
+				 <&clks IMX6SX_CLK_PLL1>,
+				 <&clks IMX6SX_PLL1_BYPASS>,
+				 <&clks IMX6SX_PLL1_BYPASS_SRC>;
 			clock-names = "arm", "pll2_pfd2_396m", "step",
-				      "pll1_sw", "pll1_sys";
+				      "pll1_sw", "pll1_sys", "pll1",
+				      "pll1_bypass", "pll1_bypass_src";
 			arm-supply = <&reg_arm>;
 			soc-supply = <&reg_soc>;
+			nvmem-cells = <&cpu_speed_grade>;
+			nvmem-cell-names = "speed_grade";
 		};
 	};
 
+        reserved-memory {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                /* global autoconfigured region for contiguous allocations */
+                linux,cma {
+                        compatible = "shared-dma-pool";
+                        reusable;
+                        size = <0x14000000>;
+                        linux,cma-default;
+                };
+        };
+
 	ckil: clock-ckil {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -132,14 +166,10 @@
 		clock-output-names = "anaclk2";
 	};
 
-	tempmon: tempmon {
-		compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
-		interrupt-parent = <&gpc>;
-		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
-		fsl,tempmon = <&anatop>;
-		nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
-		nvmem-cell-names = "calib", "temp_grade";
-		clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
+	mqs: mqs {
+		compatible = "fsl,imx6sx-mqs";
+		gpr = <&gpr>;
+		status = "disabled";
 	};
 
 	pmu {
@@ -160,18 +190,61 @@
 		interrupt-parent = <&gpc>;
 		ranges;
 
-		ocram_s: sram@8f8000 {
-			compatible = "mmio-sram";
-			reg = <0x008f8000 0x4000>;
+		busfreq {
+			compatible = "fsl,imx_busfreq";
+			clocks = <&clks IMX6SX_CLK_PLL2_BUS>, <&clks IMX6SX_CLK_PLL2_PFD2>,
+				<&clks IMX6SX_CLK_PLL2_198M>, <&clks IMX6SX_CLK_ARM>,
+				<&clks IMX6SX_CLK_PLL3_USB_OTG>, <&clks IMX6SX_CLK_PERIPH>,
+				<&clks IMX6SX_CLK_PERIPH_PRE>, <&clks IMX6SX_CLK_PERIPH_CLK2>,
+				<&clks IMX6SX_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SX_CLK_OSC>,
+				<&clks IMX6SX_CLK_PLL1_SYS>, <&clks IMX6SX_CLK_PERIPH2>,
+				<&clks IMX6SX_CLK_AHB>, <&clks IMX6SX_CLK_OCRAM_PODF>,
+				<&clks IMX6SX_CLK_PLL1_SW>, <&clks IMX6SX_CLK_PERIPH2_PRE>,
+				<&clks IMX6SX_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SX_CLK_PERIPH2_CLK2>,
+				<&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_MMDC_PODF>,
+				<&clks IMX6SX_CLK_M4>;
+			clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm",
+					"pll3_usb_otg", "periph", "periph_pre", "periph_clk2",
+					"periph_clk2_sel", "osc", "pll1_sys", "periph2",
+					"ahb", "ocram", "pll1_sw", "periph2_pre",
+					"periph2_clk2_sel", "periph2_clk2", "step", "mmdc",
+					"m4";
+			fsl,max_ddr_freq = <400000000>;
+		};
+
+		ocrams: sram@8f8000 {
+			compatible = "fsl,lpm-sram";
+			reg = <0x8f8000 0x4000>;
 			clocks = <&clks IMX6SX_CLK_OCRAM_S>;
 		};
 
-		ocram: sram@900000 {
+		ocrams_ddr: sram@900000 {
+			compatible = "fsl,ddr-lpm-sram";
+			reg = <0x900000 0x1000>;
+			clocks = <&clks IMX6SX_CLK_OCRAM>;
+		};
+
+		ocram: sram@901000 {
 			compatible = "mmio-sram";
-			reg = <0x00900000 0x20000>;
+			reg = <0x901000 0x1F000>;
 			clocks = <&clks IMX6SX_CLK_OCRAM>;
 		};
 
+		ocram_mf: sram-mf@900000 {
+			compatible = "fsl,mega-fast-sram";
+			reg = <0x900000 0x20000>;
+			clocks = <&clks IMX6SX_CLK_OCRAM>;
+		};
+
+		ocram_optee {
+			compatible = "fsl,optee-lpm-sram";
+			reg = <0x8f8000 0x4000>;
+			overw_reg = <&ocrams_ddr 0x904000 0x1000>,
+					<&ocram 0x905000 0x1b000>,
+					<&ocrams 0x900000 0x4000>;
+			overw_clock = <&ocrams &clks IMX6SX_CLK_OCRAM>;
+		};
+
 		intc: interrupt-controller@a01000 {
 			compatible = "arm,cortex-a9-gic";
 			#interrupt-cells = <3>;
@@ -181,7 +254,7 @@
 			interrupt-parent = <&intc>;
 		};
 
-		L2: l2-cache@a02000 {
+		L2: cache-controller@a02000 {
 			compatible = "arm,pl310-cache";
 			reg = <0x00a02000 0x1000>;
 			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -200,6 +273,23 @@
 				 <&clks IMX6SX_CLK_GPU>;
 			clock-names = "bus", "core", "shader";
 			power-domains = <&pd_pu>;
+			status = "disabled";
+		};
+
+		gpu3d: gpu3d@1800000 {
+			compatible = "fsl,imx6sx-gpu", "fsl,imx6q-gpu";
+			reg = <0x1800000 0x4000>, <0x80000000 0x0>,
+				<0x0 0x8000000>;
+			reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem";
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "irq_3d";
+			clocks = <&clks IMX6SX_CLK_GPU_AXI_PODF>, <&clks IMX6SX_CLK_GPU>,
+				<&clks 0>;
+			clock-names = "gpu3d_axi_clk", "gpu3d_clk",
+				"gpu3d_shader_clk";
+			resets = <&src 0>;
+			reset-names = "gpu3d";
+			power-domains = <&pd_pu>;
 		};
 
 		dma_apbh: dma-apbh@1804000 {
@@ -215,7 +305,12 @@
 			clocks = <&clks IMX6SX_CLK_APBH_DMA>;
 		};
 
-		gpmi: gpmi-nand@1806000{
+		caam_sm: caam-sm@100000 {
+			compatible = "fsl,imx6q-caam-sm";
+			reg = <0x100000 0x8000>;
+		};
+
+		gpmi: nand-controller@1806000{
 			compatible = "fsl,imx6sx-gpmi-nand";
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -333,6 +428,7 @@
 				};
 
 				esai: esai@2024000 {
+					compatible = "fsl,imx6sx-esai", "fsl,imx35-esai";
 					reg = <0x02024000 0x4000>;
 					interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 					clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
@@ -342,6 +438,9 @@
 						 <&clks IMX6SX_CLK_SPBA>;
 					clock-names = "core", "mem", "extal",
 						      "fsys", "spba";
+					dmas = <&sdma 23 21 0>,
+					       <&sdma 24 21 0>;
+					dma-names = "rx", "tx";
 					status = "disabled";
 				};
 
@@ -388,18 +487,28 @@
 				};
 
 				asrc: asrc@2034000 {
+					compatible = "fsl,imx6sx-asrc", "fsl,imx53-asrc";
 					reg = <0x02034000 0x4000>;
 					interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-					clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
-						 <&clks IMX6SX_CLK_ASRC_IPG>,
-						 <&clks IMX6SX_CLK_SPDIF>,
-						 <&clks IMX6SX_CLK_SPBA>;
-					clock-names = "mem", "ipg", "asrck", "spba";
-					dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
-					       <&sdma 19 20 1>, <&sdma 20 20 1>,
-					       <&sdma 21 20 1>, <&sdma 22 20 1>;
+					clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
+						<&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
+						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+						<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
+						<&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
+						<&clks IMX6SX_CLK_SPBA>;
+					clock-names = "mem", "ipg", "asrck_0",
+						"asrck_1", "asrck_2", "asrck_3", "asrck_4",
+						"asrck_5", "asrck_6", "asrck_7", "asrck_8",
+						"asrck_9", "asrck_a", "asrck_b", "asrck_c",
+						"asrck_d", "asrck_e", "asrck_f", "spba";
+					dmas = <&sdma 17 23 1>, <&sdma 18 23 1>,
+					       <&sdma 19 23 1>, <&sdma 20 23 1>,
+					       <&sdma 21 23 1>, <&sdma 22 23 1>;
 					dma-names = "rxa", "rxb", "rxc",
 						    "txa", "txb", "txc";
+					fsl,asrc-rate  = <48000>;
+					fsl,asrc-width = <16>;
 					status = "okay";
 				};
 			};
@@ -411,7 +520,7 @@
 				clocks = <&clks IMX6SX_CLK_PWM1>,
 					 <&clks IMX6SX_CLK_PWM1>;
 				clock-names = "ipg", "per";
-				#pwm-cells = <2>;
+				#pwm-cells = <3>;
 			};
 
 			pwm2: pwm@2084000 {
@@ -421,7 +530,7 @@
 				clocks = <&clks IMX6SX_CLK_PWM2>,
 					 <&clks IMX6SX_CLK_PWM2>;
 				clock-names = "ipg", "per";
-				#pwm-cells = <2>;
+				#pwm-cells = <3>;
 			};
 
 			pwm3: pwm@2088000 {
@@ -431,7 +540,7 @@
 				clocks = <&clks IMX6SX_CLK_PWM3>,
 					 <&clks IMX6SX_CLK_PWM3>;
 				clock-names = "ipg", "per";
-				#pwm-cells = <2>;
+				#pwm-cells = <3>;
 			};
 
 			pwm4: pwm@208c000 {
@@ -441,7 +550,7 @@
 				clocks = <&clks IMX6SX_CLK_PWM4>,
 					 <&clks IMX6SX_CLK_PWM4>;
 				clock-names = "ipg", "per";
-				#pwm-cells = <2>;
+				#pwm-cells = <3>;
 			};
 
 			flexcan1: can@2090000 {
@@ -451,7 +560,7 @@
 				clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
 					 <&clks IMX6SX_CLK_CAN1_SERIAL>;
 				clock-names = "ipg", "per";
-				fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
+				fsl,stop-mode = <&gpr 0x10 1>;
 				status = "disabled";
 			};
 
@@ -462,11 +571,11 @@
 				clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
 					 <&clks IMX6SX_CLK_CAN2_SERIAL>;
 				clock-names = "ipg", "per";
-				fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
+				fsl,stop-mode = <&gpr 0x10 2>;
 				status = "disabled";
 			};
 
-			gpt: gpt@2098000 {
+			gpt: timer@2098000 {
 				compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
 				reg = <0x02098000 0x4000>;
 				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
@@ -559,7 +668,7 @@
 				gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
 			};
 
-			kpp: kpp@20b8000 {
+			kpp: keypad@20b8000 {
 				compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
 				reg = <0x020b8000 0x4000>;
 				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
@@ -567,14 +676,14 @@
 				status = "disabled";
 			};
 
-			wdog1: wdog@20bc000 {
+			wdog1: watchdog@20bc000 {
 				compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 				reg = <0x020bc000 0x4000>;
 				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SX_CLK_IPG>;
 			};
 
-			wdog2: wdog@20c0000 {
+			wdog2: watchdog@20c0000 {
 				compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 				reg = <0x020c0000 0x4000>;
 				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
@@ -582,7 +691,7 @@
 				status = "disabled";
 			};
 
-			clks: ccm@20c4000 {
+			clks: clock-controller@20c4000 {
 				compatible = "fsl,imx6sx-ccm";
 				reg = <0x020c4000 0x4000>;
 				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
@@ -694,6 +803,16 @@
 					anatop-min-voltage = <725000>;
 					anatop-max-voltage = <1450000>;
 				};
+
+				tempmon: tempmon {
+					compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
+					interrupt-parent = <&gpc>;
+					interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+					fsl,tempmon = <&anatop>;
+					nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
+					nvmem-cell-names = "calib", "temp_grade";
+					clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
+				};
 			};
 
 			usbphy1: usbphy@20c9000 {
@@ -712,6 +831,20 @@
 				fsl,anatop = <&anatop>;
 			};
 
+			irq_sec_vio: caam_secvio {
+				compatible = "fsl,imx6q-caam-secvio";
+				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+				jtag-tamper = "disabled";
+				watchdog-tamper = "enabled";
+				internal-boot-tamper = "enabled";
+				external-pin-tamper = "disabled";
+			};
+
+			caam_snvs: caam-snvs@20cc000 {
+				compatible = "fsl,imx6q-caam-snvs";
+				reg = <0x20cc000 0x4000>;
+			};
+
 			snvs: snvs@20cc000 {
 				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 				reg = <0x020cc000 0x4000>;
@@ -752,7 +885,7 @@
 				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
-			src: src@20d8000 {
+			src: reset-controller@20d8000 {
 				compatible = "fsl,imx6sx-src", "fsl,imx51-src";
 				reg = <0x020d8000 0x4000>;
 				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
@@ -767,6 +900,7 @@
 				#interrupt-cells = <3>;
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 				interrupt-parent = <&intc>;
+				fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x400240>;
 				clocks = <&clks IMX6SX_CLK_IPG>;
 				clock-names = "ipg";
 
@@ -806,7 +940,7 @@
 				};
 			};
 
-			iomuxc: iomuxc@20e0000 {
+			iomuxc: pinctrl@20e0000 {
 				compatible = "fsl,imx6sx-iomuxc";
 				reg = <0x020e0000 0x4000>;
 			};
@@ -817,6 +951,30 @@
 				reg = <0x020e4000 0x4000>;
 			};
 
+			ldb: ldb@20e0014 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx6sx-ldb", "fsl,imx53-ldb";
+				gpr = <&gpr>;
+				status = "disabled";
+				clocks = <&clks IMX6SX_CLK_LDB_DI0>,
+					 <&clks IMX6SX_CLK_LCDIF1_SEL>,
+					 <&clks IMX6SX_CLK_LCDIF2_SEL>,
+					 <&clks IMX6SX_CLK_LDB_DI0_DIV_3_5>,
+					 <&clks IMX6SX_CLK_LDB_DI0_DIV_7>,
+					 <&clks IMX6SX_CLK_LDB_DI0_DIV_SEL>;
+				clock-names = "ldb_di0",
+					      "di0_sel",
+					      "di1_sel",
+					      "ldb_di0_div_3_5",
+					      "ldb_di0_div_7",
+					      "ldb_di0_div_sel";
+				lvds-channel@0 {
+					reg = <0>;
+					status = "disabled";
+				};
+			};
+
 			sdma: sdma@20ec000 {
 				compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
 				reg = <0x020ec000 0x4000>;
@@ -837,7 +995,7 @@
 			reg = <0x02100000 0x100000>;
 			ranges;
 
-			crypto: caam@2100000 {
+			crypto: crypto@2100000 {
 				compatible = "fsl,sec-v4.0";
 				#address-cells = <1>;
 				#size-cells = <1>;
@@ -850,19 +1008,33 @@
 					 <&clks IMX6SX_CLK_EIM_SLOW>;
 				clock-names = "mem", "aclk", "ipg", "emi_slow";
 
-				sec_jr0: jr0@1000 {
+				sec_jr0: jr@1000 {
 					compatible = "fsl,sec-v4.0-job-ring";
 					reg = <0x1000 0x1000>;
 					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 				};
 
-				sec_jr1: jr1@2000 {
+				sec_jr1: jr@2000 {
 					compatible = "fsl,sec-v4.0-job-ring";
 					reg = <0x2000 0x1000>;
 					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 				};
 			};
 
+			usbg1: usbg1 {
+				compatible = "fsl,imx27-usb-gadget";
+				dr_mode = "peripheral";
+				chipidea,usb = <&usbotg1>;
+				status = "okay";
+			};
+
+			usbg2: usbg2 {
+				compatible = "fsl,imx27-usb-gadget";
+				dr_mode = "peripheral";
+				chipidea,usb = <&usbotg2>;
+				status = "okay";
+			};
+
 			usbotg1: usb@2184000 {
 				compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
 				reg = <0x02184000 0x200>;
@@ -928,6 +1100,8 @@
 					      "enet_clk_ref", "enet_out";
 				fsl,num-tx-queues = <3>;
 				fsl,num-rx-queues = <3>;
+				fsl,stop-mode = <&gpr 0x10 3>;
+				fsl,wakeup_irq = <0>;
 				status = "disabled";
 			};
 
@@ -940,7 +1114,7 @@
 				status = "disabled";
 			};
 
-			usdhc1: usdhc@2190000 {
+			usdhc1: mmc@2190000 {
 				compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 				reg = <0x02190000 0x4000>;
 				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
@@ -949,10 +1123,12 @@
 					 <&clks IMX6SX_CLK_USDHC1>;
 				clock-names = "ipg", "ahb", "per";
 				bus-width = <4>;
+				fsl,tuning-start-tap = <20>;
+				fsl,tuning-step= <2>;
 				status = "disabled";
 			};
 
-			usdhc2: usdhc@2194000 {
+			usdhc2: mmc@2194000 {
 				compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 				reg = <0x02194000 0x4000>;
 				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
@@ -961,10 +1137,12 @@
 					 <&clks IMX6SX_CLK_USDHC2>;
 				clock-names = "ipg", "ahb", "per";
 				bus-width = <4>;
+				fsl,tuning-start-tap = <20>;
+				fsl,tuning-step= <2>;
 				status = "disabled";
 			};
 
-			usdhc3: usdhc@2198000 {
+			usdhc3: mmc@2198000 {
 				compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 				reg = <0x02198000 0x4000>;
 				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
@@ -973,10 +1151,12 @@
 					 <&clks IMX6SX_CLK_USDHC3>;
 				clock-names = "ipg", "ahb", "per";
 				bus-width = <4>;
+				fsl,tuning-start-tap = <20>;
+				fsl,tuning-step= <2>;
 				status = "disabled";
 			};
 
-			usdhc4: usdhc@219c000 {
+			usdhc4: mmc@219c000 {
 				compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
 				reg = <0x0219c000 0x4000>;
 				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
@@ -985,6 +1165,8 @@
 					 <&clks IMX6SX_CLK_USDHC4>;
 				clock-names = "ipg", "ahb", "per";
 				bus-width = <4>;
+				fsl,tuning-start-tap = <20>;
+				fsl,tuning-step= <2>;
 				status = "disabled";
 			};
 
@@ -1037,6 +1219,10 @@
 					 <&clks IMX6SX_CLK_ENET_PTP>;
 				clock-names = "ipg", "ahb", "ptp",
 					      "enet_clk_ref", "enet_out";
+				fsl,stop-mode = <&gpr 0x10 4>;
+				fsl,num-tx-queues=<3>;
+				fsl,num-rx-queues=<3>;
+				fsl,wakeup_irq = <0>;
 				status = "disabled";
 			};
 
@@ -1051,13 +1237,17 @@
 				status = "disabled";
 			};
 
-			ocotp: ocotp@21bc000 {
+			ocotp: efuse@21bc000 {
 				#address-cells = <1>;
 				#size-cells = <1>;
 				compatible = "fsl,imx6sx-ocotp", "syscon";
 				reg = <0x021bc000 0x4000>;
 				clocks = <&clks IMX6SX_CLK_OCOTP>;
 
+				cpu_speed_grade: speed-grade@10 {
+					reg = <0x10 4>;
+				};
+
 				tempmon_calib: calib@38 {
 					reg = <0x38 4>;
 				};
@@ -1125,6 +1315,12 @@
 				status = "disabled";
 			};
 
+			qspi_m4: qspi-m4 {
+				compatible = "fsl,imx6sx-qspi-m4-restore";
+				reg = <0x021e4000 0x4000>;
+				status = "disabled";
+			};
+
 			uart2: serial@21e8000 {
 				compatible = "fsl,imx6sx-uart",
 					     "fsl,imx6q-uart", "fsl,imx21-uart";
@@ -1203,21 +1399,46 @@
 				ranges;
 
 				csi1: csi@2214000 {
+					compatible = "fsl,imx6s-csi";
 					reg = <0x02214000 0x4000>;
 					interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 					clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
 						 <&clks IMX6SX_CLK_CSI>,
 						 <&clks IMX6SX_CLK_DCIC1>;
-					clock-names = "disp-axi", "csi_mclk", "dcic";
+					clock-names = "disp-axi", "csi_mclk", "disp_dcic";
+					power-domains = <&pd_disp>;
+					status = "disabled";
+				};
+
+				dcic1: dcic@220c000 {
+					compatible = "fsl,imx6sx-dcic";
+					reg = <0x220c000 0x4000>;
+					interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX6SX_CLK_DCIC1>,
+						<&clks IMX6SX_CLK_DISPLAY_AXI>;
+					clock-names = "dcic", "disp-axi";
+					gpr = <&gpr>;
+					status = "disabled";
+				};
+
+				dcic2: dcic@2210000 {
+					compatible = "fsl,imx6sx-dcic";
+					reg = <0x2210000 0x4000>;
+					interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX6SX_CLK_DCIC2>,
+						<&clks IMX6SX_CLK_DISPLAY_AXI>;
+					clock-names = "dcic", "disp-axi";
+					gpr = <&gpr>;
 					status = "disabled";
 				};
 
 				pxp: pxp@2218000 {
-					compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
+					compatible = "fsl,imx6sx-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
 					reg = <0x02218000 0x4000>;
 					interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-					clocks = <&clks IMX6SX_CLK_PXP_AXI>;
-					clock-names = "axi";
+					clocks = <&clks IMX6SX_CLK_PXP_AXI>,
+						 <&clks IMX6SX_CLK_DISPLAY_AXI>;
+					clock-names = "pxp-axi", "disp-axi";
 					power-domains = <&pd_disp>;
 					status = "disabled";
 				};
@@ -1257,12 +1478,14 @@
 				};
 
 				vadc: vadc@2228000 {
+					compatible = "fsl,imx6sx-vadc";
 					reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
 					reg-names = "vadc-vafe", "vadc-vdec";
 					clocks = <&clks IMX6SX_CLK_VADC>,
 						 <&clks IMX6SX_CLK_CSI>;
 					clock-names = "vadc", "csi";
 					power-domains = <&pd_disp>;
+					gpr = <&gpr>;
 					status = "disabled";
 				};
 			};
@@ -1273,6 +1496,7 @@
 				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SX_CLK_IPG>;
 				clock-names = "adc";
+				num-channels = <4>;
 				fsl,adck-max-frequency = <30000000>, <40000000>,
 							 <20000000>;
 				status = "disabled";
@@ -1284,12 +1508,13 @@
 				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX6SX_CLK_IPG>;
 				clock-names = "adc";
+				num-channels = <4>;
 				fsl,adck-max-frequency = <30000000>, <40000000>,
 							 <20000000>;
 				status = "disabled";
 			};
 
-			wdog3: wdog@2288000 {
+			wdog3: watchdog@2288000 {
 				compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
 				reg = <0x02288000 0x4000>;
 				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
@@ -1309,6 +1534,27 @@
 				status = "disabled";
 			};
 
+			sema4: sema4@02290000 { /* sema4 */
+				compatible = "fsl,imx6sx-sema4";
+				reg = <0x02290000 0x4000>;
+				interrupts = <0 116 0x04>;
+				status = "okay";
+			};
+
+			mu: mu@02294000 { /* mu */
+				compatible = "fsl,imx6sx-mu";
+				reg = <0x02294000 0x4000>;
+				interrupts = <0 90 0x04>;
+				#mbox-cells = <2>;
+			};
+
+			mu_lp: mu_lp@02294000 { /* mu */
+				compatible = "fsl,imx6sx-mu-lp";
+				reg = <0x02294000 0x4000>;
+				interrupts = <0 90 0x04>;
+				status = "okay";
+			};
+
 			uart6: serial@22a0000 {
 				compatible = "fsl,imx6sx-uart",
 					     "fsl,imx6q-uart", "fsl,imx21-uart";
@@ -1329,7 +1575,7 @@
 				clocks = <&clks IMX6SX_CLK_PWM5>,
 					 <&clks IMX6SX_CLK_PWM5>;
 				clock-names = "ipg", "per";
-				#pwm-cells = <2>;
+				#pwm-cells = <3>;
 			};
 
 			pwm6: pwm@22a8000 {
@@ -1339,7 +1585,7 @@
 				clocks = <&clks IMX6SX_CLK_PWM6>,
 					 <&clks IMX6SX_CLK_PWM6>;
 				clock-names = "ipg", "per";
-				#pwm-cells = <2>;
+				#pwm-cells = <3>;
 			};
 
 			pwm7: pwm@22ac000 {
@@ -1349,7 +1595,7 @@
 				clocks = <&clks IMX6SX_CLK_PWM7>,
 					 <&clks IMX6SX_CLK_PWM7>;
 				clock-names = "ipg", "per";
-				#pwm-cells = <2>;
+				#pwm-cells = <3>;
 			};
 
 			pwm8: pwm@22b0000 {
@@ -1359,7 +1605,7 @@
 				clocks = <&clks IMX6SX_CLK_PWM8>,
 					 <&clks IMX6SX_CLK_PWM8>;
 				clock-names = "ipg", "per";
-				#pwm-cells = <2>;
+				#pwm-cells = <3>;
 			};
 		};
 
@@ -1371,8 +1617,6 @@
 			#size-cells = <2>;
 			device_type = "pci";
 			bus-range = <0x00 0xff>;
-			ranges = <0x81000000 0 0          0x08f80000 0 0x00010000 /* downstream I/O */
-				  0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
 			num-lanes = <1>;
 			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "msi";
@@ -1391,5 +1635,36 @@
 			power-domain-names = "pcie", "pcie_phy";
 			status = "disabled";
 		};
+
+		pcie_ep: pcie_ep@8ffc000 {
+			compatible = "fsl,imx6sx-pcie-ep";
+			reg = <0x08ffc000 0x04000>, <0x08000000 0xf00000>;
+			reg-names = "regs", "addr_space";
+			num-lanes = <1>;
+			clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
+				 <&clks IMX6SX_CLK_LVDS1_OUT>,
+				 <&clks IMX6SX_CLK_PCIE_REF_125M>,
+				 <&clks IMX6SX_CLK_DISPLAY_AXI>;
+			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
+			power-domains = <&pd_disp>, <&pd_pci>;
+			power-domain-names = "pcie", "pcie_phy";
+			num-ib-windows = <4>;
+			num-ob-windows = <4>;
+			status = "disabled";
+		};
+	};
+
+	rpmsg: rpmsg{
+		compatible = "fsl,imx6sx-rpmsg";
+		/* up to now, the following channels are used in imx rpmsg
+		 * - tx1/rx1: messages channel.
+		 * - general interrupt1: remote proc finish re-init rpmsg stack
+		 *   when A core is partition reset.
+		 */
+		mbox-names = "tx", "rx", "rxdb";
+		mboxes = <&mu 0 1
+			  &mu 1 1
+			  &mu 3 1>;
+		status = "disabled";
 	};
 };
diff --git a/arch/arm/dts/imx6ul-14x14-ddr3-val-emmc.dts b/arch/arm/dts/imx6ul-14x14-ddr3-val-emmc.dts
new file mode 100644
index 00000000000..336f0a4e0ca
--- /dev/null
+++ b/arch/arm/dts/imx6ul-14x14-ddr3-val-emmc.dts
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6ul-14x14-ddr3-val.dts"
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1_8bit>;
+	pinctrl-1 = <&pinctrl_usdhc1_8bit_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_8bit_200mhz>;
+	bus-width = <8>;
+	cd-gpios = <>;
+	wp-gpios = <>;
+	vmmc-supply = <>;
+	tuning-step = <2>;
+	non-removable;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6ul-14x14-ddr3-val-gpmi-weim.dts b/arch/arm/dts/imx6ul-14x14-ddr3-val-gpmi-weim.dts
new file mode 100644
index 00000000000..fd5b550c9a0
--- /dev/null
+++ b/arch/arm/dts/imx6ul-14x14-ddr3-val-gpmi-weim.dts
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6ul-14x14-ddr3-val.dts"
+
+/*
+ * solve pin conflict with NAND
+ *
+ * USDHC2_CD, SD2_RST_B, USDHC2_WP conflict with RAWNAND CE pins , also
+ * overwritten the conflict of SD2_RST_B with RAWNAND ALE in hog
+ * QSPI CLK, CE and DATA pins conflict with RAWNAND data pins and CE, CLE, RB,
+ * WP, DQS pin
+ *
+ */
+&iomuxc {
+	pinctrl-0 = <&pinctrl_hog>;
+};
+
+&qspi{
+	status = "disabled";
+};
+
+&gpmi{
+	status = "okay";
+};
+
+&usdhc2 {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/imx6ul-14x14-ddr3-val.dts b/arch/arm/dts/imx6ul-14x14-ddr3-val.dts
new file mode 100644
index 00000000000..fa4baa2c920
--- /dev/null
+++ b/arch/arm/dts/imx6ul-14x14-ddr3-val.dts
@@ -0,0 +1,776 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx6ul.dtsi"
+
+/ {
+	model = "i.MX6 UltraLite DDR3 VAL Board";
+	compatible = "fsl,imx6ul-14x14-ddr3-val", "fsl,imx6ul";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory {
+		reg = <0x80000000 0x40000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x14000000>;
+			linux,cma-default;
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_sd1_vmmc: sd1_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "SD1_SPWR";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+			u-boot,off-on-delay-us = <20000>;
+			enable-active-high;
+		};
+
+		reg_sd2_vmmc: sd2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "SD2_SPWR";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
+			u-boot,off-on-delay-us = <20000>;
+			enable-active-high;
+		};
+
+		reg_can2_3v3: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "can2-3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio1 15 GPIO_ACTIVE_LOW>;
+		};
+
+		reg_vref_3v3: regulator@1 {
+			compatible = "regulator-fixed";
+			regulator-name = "vref-3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+		reg_usb_otg1_vbus: regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb_otg1>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+	};
+};
+
+&clks {
+	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <786432000>;
+};
+
+&cpu0 {
+	/*
+	 * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN,
+	 * to align with other platform and use the same cpufreq
+	 * driver, still use the seperated OPP define for arm
+	 * and soc.
+	 */
+	operating-points = <
+		/* kHz	uV */
+		528000	1175000
+		396000	1175000
+		198000	1175000
+	>;
+	fsl,soc-operating-points = <
+		/* KHz	uV */
+		528000	1175000
+		396000	1175000
+		198000	1175000
+	>;
+	fsl,arm-soc-shared = <1>;
+};
+
+&reg_arm {
+	vin-supply = <&sw1a_reg>;
+	regulator-allow-bypass;
+};
+
+&reg_soc {
+	vin-supply = <&sw1a_reg>;
+	regulator-allow-bypass;
+};
+
+&ecspi1 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio4 26 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>;
+	status = "okay";
+
+	flash: n25q032@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,n25q032", "jedec,spi-nor";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy0>;
+	status = "okay";
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2>;
+	phy-mode = "mii";
+	phy-handle = <&ethphy1>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+
+		ethphy1: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+		};
+	};
+};
+
+&can2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	xceiver-supply = <&reg_can2_3v3>;
+	status = "disabled";
+};
+
+&gpc {
+	fsl,cpu_pupscr_sw2iso = <0xf>;
+	fsl,cpu_pupscr_sw = <0x0>;
+	fsl,cpu_pdnscr_iso2sw = <0x1>;
+	fsl,cpu_pdnscr_iso = <0x1>;
+	fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "disabled";
+	nand-on-flash-bbt;
+	fsl,use-minimum-ecc;
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pfuze100@8 {
+		compatible = "fsl,pfuze200";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			sw3b_reg: sw3b {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog &pinctrl_hog1 &pinctrl_hog_sd>;
+
+	imx6ul-ddr3-val {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059	/* SD1 CD */
+				MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x17059	/* SD1 WP */
+				MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT	0x17059	/* SD1 VSELECT */
+				MX6UL_PAD_CSI_MCLK__GPIO4_IO17		0x17059	/* SD2 CD */
+				MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18	0x17059	/* SD2 WP */
+			>;
+		};
+
+		pinctrl_hog1: hoggrp1 {
+			fsl,pins = <
+				MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x17059 /* SD2 RESECT */
+			>;
+		};
+
+		pinctrl_hog_sd: hoggrp_sd {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
+				MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT    0x17059 /* SD2 VSELECT */
+			>;
+		};
+
+		pinctrl_adc1: adc1grp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO00__GPIO1_IO00        0xb0
+				MX6UL_PAD_GPIO1_IO01__GPIO1_IO01        0xb0
+			>;
+		};
+
+		pinctrl_bt: btgrp {
+			fsl,pins = <
+				MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x80000000
+				MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x80000000
+				MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x80000000
+			>;
+		};
+
+		pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 {
+			fsl,pins = <
+				MX6UL_PAD_CSI_DATA05__GPIO4_IO26  0x10b0
+			>;
+		};
+
+		pinctrl_ecspi1_1: ecspi1grp-1 {
+			fsl,pins = <
+				MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x10b0
+				MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x10b0
+				MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x10b0
+			>;
+		};
+
+		pinctrl_enet1: enet1grp {
+			fsl,pins = <
+				MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
+				MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
+				MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
+				MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
+				MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
+				MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
+				MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
+				MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b0a8
+			>;
+		};
+
+		pinctrl_enet2: enet2grp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
+				MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
+				MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
+				MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
+				MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02	0x1b0b0
+				MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03	0x1b0b0
+				MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK	0x4001b0a8
+				MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
+				MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
+				MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
+				MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02	0x1b0b0
+				MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03	0x1b0b0
+				MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
+				MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
+				MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK	0x4001b0a8
+				MX6UL_PAD_UART5_RX_DATA__ENET2_COL	0x1b0b0
+				MX6UL_PAD_UART5_TX_DATA__ENET2_CRS	0x1b0b0
+			>;
+		};
+
+		pinctrl_flexcan2: flexcan2grp{
+			fsl,pins = <
+				MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
+				MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
+				MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15	0x17059	/* STBY */
+			>;
+		};
+
+		pinctrl_gpmi_nand_1: gpmi-nand-1 {
+			fsl,pins = <
+				MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
+				MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
+				MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
+				MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
+				MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
+				MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B     0xb0b1
+				MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
+				MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
+				MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
+				MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
+				MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
+				MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
+				MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
+				MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
+				MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
+				MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO03__I2C1_SDA	0x4001b8b1
+				MX6UL_PAD_GPIO1_IO02__I2C1_SCL	0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c1_gpio: i2c1grp_gpio {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO03__GPIO1_IO03  0x1b8b1
+				MX6UL_PAD_GPIO1_IO02__GPIO1_IO02  0x1b8b1
+			>;
+		};
+
+		pinctrl_i2c4: i2c4grp {
+			fsl,pins = <
+				MX6UL_PAD_UART2_TX_DATA__I2C4_SCL	0x4001b8b0
+				MX6UL_PAD_UART2_RX_DATA__I2C4_SDA	0x4001b8b0
+			>;
+		};
+
+		pinctrl_lcdif_dat: lcdifdatgrp {
+			fsl,pins = <
+				MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
+				MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
+				MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
+				MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
+				MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
+				MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
+				MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
+				MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
+				MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
+				MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
+				MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
+				MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
+				MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
+				MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
+				MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
+				MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
+				MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
+				MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
+				MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
+				MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
+				MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
+				MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
+				MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
+				MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
+			>;
+		};
+
+		pinctrl_lcdif_ctrl: lcdifctrlgrp {
+			fsl,pins = <
+				MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x79
+				MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
+				MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
+				MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
+				MX6UL_PAD_LCD_RESET__LCDIF_RESET    0x79
+			>;
+		};
+
+		pinctrl_mqs: mqsgrp {
+			fsl,pins = <
+				MX6UL_PAD_JTAG_TDI__MQS_LEFT         0x11088
+				MX6UL_PAD_JTAG_TDO__MQS_RIGHT        0x11088
+			>;
+		};
+
+		pinctrl_pwm1: pmw1grp {
+			fsl,pins = <
+				MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x110b0
+			>;
+		};
+
+		pinctrl_qspi: qspigrp {
+			fsl,pins = <
+				MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK      0x70a1
+				MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
+				MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01   0x70a1
+				MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02   0x70a1
+				MX6UL_PAD_NAND_CLE__QSPI_A_DATA03     0x70a1
+				MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B      0x70a1
+				MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B   0x70a1
+				MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK      0x70a1
+				MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00  0x70a1
+				MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01  0x70a1
+				MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02  0x70a1
+				MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03  0x70a1
+				MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B     0x70a1
+				MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B   0x70a1
+			>;
+		};
+
+		pinctrl_sai2: sai2grp {
+			fsl,pins = <
+				MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC     0x1b0b0
+				MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK     0x1b0b0
+				MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA     0x110b0
+				MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA     0x1f0b8
+				MX6UL_PAD_SD1_CLK__SAI2_MCLK          0x1b0b0
+				MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00   0x17059
+			>;
+		};
+
+		pinctrl_spdif: spdifgrp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO08__SPDIF_OUT       0x1b0b0
+				MX6UL_PAD_GPIO1_IO09__SPDIF_IN        0x1b0b0
+			>;
+		};
+
+		pinctrl_tsc: tscgrp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0xb0
+				MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0xb0
+				MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
+				MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0xb0
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+				MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+			>;
+		};
+
+		pinctrl_uart2: uart2grp {
+			fsl,pins = <
+				MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
+				MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
+				MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS  0x1b0b1
+				MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS  0x1b0b1
+			>;
+		};
+
+		pinctrl_uart2dte: uart2dtegrp {
+			fsl,pins = <
+				MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
+				MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
+				MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS  0x1b0b1
+				MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS  0x1b0b1
+			>;
+		};
+
+		pinctrl_usb_otg1_id: usbotg1idgrp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
+			>;
+		};
+
+		pinctrl_usb_otg1: usbotg1grp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO04__GPIO1_IO04        0x10b0
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+			>;
+		};
+
+		pinctrl_usdhc1_8bit: usdhc1_8bit_grp {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x17059
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     	0x10059
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 	0x17059
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 	0x17059
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 	0x17059
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 	0x17059
+				MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x17059
+				MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x17059
+				MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x17059
+				MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x17059
+			>;
+		};
+
+		pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x170b9
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     	0x100b9
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 	0x170b9
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 	0x170b9
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 	0x170b9
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 	0x170b9
+				MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x170b9
+				MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x170b9
+				MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x170b9
+				MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x170b9
+			>;
+		};
+
+		pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x170f9
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     	0x100f9
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 	0x170f9
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 	0x170f9
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 	0x170f9
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 	0x170f9
+				MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x170f9
+				MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x170f9
+				MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x170f9
+				MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x170f9
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6UL_PAD_CSI_HSYNC__USDHC2_CMD		0x17059
+				MX6UL_PAD_CSI_VSYNC__USDHC2_CLK		0x10059
+				MX6UL_PAD_CSI_DATA00__USDHC2_DATA0	0x17059
+				MX6UL_PAD_CSI_DATA01__USDHC2_DATA1	0x17059
+				MX6UL_PAD_CSI_DATA02__USDHC2_DATA2	0x17059
+				MX6UL_PAD_CSI_DATA03__USDHC2_DATA3	0x17059
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				MX6UL_PAD_CSI_HSYNC__USDHC2_CMD		0x170b9
+				MX6UL_PAD_CSI_VSYNC__USDHC2_CLK		0x100b9
+				MX6UL_PAD_CSI_DATA00__USDHC2_DATA0	0x170b9
+				MX6UL_PAD_CSI_DATA01__USDHC2_DATA1	0x170b9
+				MX6UL_PAD_CSI_DATA02__USDHC2_DATA2	0x170b9
+				MX6UL_PAD_CSI_DATA03__USDHC2_DATA3	0x170b9
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				MX6UL_PAD_CSI_HSYNC__USDHC2_CMD		0x170f9
+				MX6UL_PAD_CSI_VSYNC__USDHC2_CLK		0x100f9
+				MX6UL_PAD_CSI_DATA00__USDHC2_DATA0	0x170f9
+				MX6UL_PAD_CSI_DATA01__USDHC2_DATA1	0x170f9
+				MX6UL_PAD_CSI_DATA02__USDHC2_DATA2	0x170f9
+				MX6UL_PAD_CSI_DATA03__USDHC2_DATA3	0x170f9
+			>;
+		};
+	};
+};
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi>;
+	status = "okay";
+	fsl,qspi-has-second-chip = <1>;
+	ddrsmp=<0>;
+
+	flash0: n25q256a@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <0>;
+	};
+
+	flash1: n25q256a@1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <1>;
+	};
+
+	flash2: n25q256a@2 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <2>;
+	};
+
+	flash3: n25q256a@3 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <3>;
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2
+		     &pinctrl_bt>;
+	fsl,uart-has-rtscts;
+	/* for DTE mode, add below change */
+	/* fsl,dte-mode; */
+	/* pinctrl-0 = <&pinctrl_uart2dte>; */
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_otg1_id>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sd1_vmmc>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+	cd-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sd2_vmmc>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6ul-14x14-evk-emmc.dts b/arch/arm/dts/imx6ul-14x14-evk-emmc.dts
new file mode 100644
index 00000000000..bc4e53f2556
--- /dev/null
+++ b/arch/arm/dts/imx6ul-14x14-evk-emmc.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#include "imx6ul-14x14-evk.dts"
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2_8bit>;
+	pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
diff --git a/arch/arm/dts/imx6ul-14x14-evk-gpmi-weim.dts b/arch/arm/dts/imx6ul-14x14-evk-gpmi-weim.dts
new file mode 100644
index 00000000000..dfd39afcf60
--- /dev/null
+++ b/arch/arm/dts/imx6ul-14x14-evk-gpmi-weim.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2015 Freescale Semiconductor, Inc.
+
+#include "imx6ul-14x14-evk.dts"
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "okay";
+	nand-on-flash-bbt;
+	fsl,use-minimum-ecc;
+};
+
+&iomuxc {
+	pinctrl_gpmi_nand_1: gpmi-nand-1 {
+		fsl,pins = <
+			MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
+			MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
+			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
+			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
+			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
+			MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B     0xb0b1
+			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
+			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
+			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
+			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
+			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
+			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
+			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
+			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
+			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
+			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
+		>;
+	};
+};
+
+&qspi {
+	status = "disabled";
+};
+
+&usdhc2 {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi b/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi
index d0cbf79e33f..25e54b0582a 100644
--- a/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi
@@ -25,33 +25,3 @@
 &iomuxc {
 	u-boot,dm-pre-reloc;
 };
-
-&lcdif {
-	display = <&display0>;
-	u-boot,dm-pre-reloc;
-
-	display0: display@0 {
-		bits-per-pixel = <24>;
-		bus-width = <24>;
-
-		display-timings {
-			native-mode = <&timing0>;
-
-			timing0: timing0 {
-				clock-frequency = <9200000>;
-				hactive = <480>;
-				vactive = <272>;
-				hfront-porch = <8>;
-				hback-porch = <4>;
-				hsync-len = <41>;
-				vback-porch = <2>;
-				vfront-porch = <4>;
-				vsync-len = <10>;
-				hsync-active = <0>;
-				vsync-active = <0>;
-				de-active = <1>;
-				pixelclk-active = <0>;
-			};
-		};
-	};
-};
diff --git a/arch/arm/dts/imx6ul-14x14-evk.dtsi b/arch/arm/dts/imx6ul-14x14-evk.dtsi
index 463d7ca124b..0789ca6ed6a 100644
--- a/arch/arm/dts/imx6ul-14x14-evk.dtsi
+++ b/arch/arm/dts/imx6ul-14x14-evk.dtsi
@@ -16,21 +16,13 @@
 		reg = <0x80000000 0x20000000>;
 	};
 
-	backlight_display: backlight-display {
-		compatible = "pwm-backlight";
-		pwms = <&pwm1 0 5000000>;
-		brightness-levels = <0 4 8 16 32 64 128 255>;
-		default-brightness-level = <6>;
-		status = "okay";
-	};
-
-
 	reg_sd1_vmmc: regulator-sd1-vmmc {
 		compatible = "regulator-fixed";
 		regulator-name = "VSD_3V3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+		off-on-delay-us = <20000>;
 		enable-active-high;
 	};
 
@@ -47,6 +39,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_spi4>;
 		status = "okay";
+		pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
 		gpio-sck = <&gpio5 11 0>;
 		gpio-mosi = <&gpio5 10 0>;
 		cs-gpios = <&gpio5 7 0>;
@@ -60,20 +53,10 @@
 			#gpio-cells = <2>;
 			reg = <0>;
 			registers-number = <1>;
+			registers-default = /bits/ 8 <0x57>;
 			spi-max-frequency = <100000>;
 		};
 	};
-
-	panel {
-		compatible = "innolux,at043tn24";
-		backlight = <&backlight_display>;
-
-		port {
-			panel_in: endpoint {
-				remote-endpoint = <&display_out>;
-			};
-		};
-	};
 };
 
 &clks {
@@ -82,7 +65,7 @@
 };
 
 &i2c2 {
-	clock_frequency = <100000>;
+	clock-frequency = <100000>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_i2c2>;
 	status = "okay";
@@ -160,16 +143,35 @@
 };
 
 &lcdif {
-	assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
-	assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lcdif_dat
 		     &pinctrl_lcdif_ctrl>;
+
+	display = <&display0>;
 	status = "okay";
 
-	port {
-		display_out: endpoint {
-			remote-endpoint = <&panel_in>;
+	display0: display@0 {
+		bits-per-pixel = <24>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+			clock-frequency = <9200000>;
+			hactive = <480>;
+			vactive = <272>;
+			hfront-porch = <8>;
+			hback-porch = <4>;
+			hsync-len = <41>;
+			vback-porch = <2>;
+			vfront-porch = <4>;
+			vsync-len = <10>;
+
+			hsync-active = <0>;
+			vsync-active = <0>;
+			de-active = <1>;
+			pixelclk-active = <0>;
+			};
 		};
 	};
 };
@@ -188,10 +190,8 @@
 	flash0: n25q256a@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "micron,n25q256a";
+		compatible = "micron,n25q256a", "jedec,spi-nor";
 		spi-max-frequency = <29000000>;
-		spi-rx-bus-width = <4>;
-		spi-tx-bus-width = <4>;
 		reg = <0>;
 	};
 };
@@ -235,6 +235,8 @@
 
 &usbotg1 {
 	dr_mode = "otg";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_otg1>;
 	status = "okay";
 };
 
@@ -476,10 +478,16 @@
 		>;
 	};
 
+	pinctrl_usb_otg1: usbotg1grp {
+		fsl,pins = <
+			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
+		>;
+	};
+
 	pinctrl_usdhc1: usdhc1grp {
 		fsl,pins = <
 			MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x17059
-			MX6UL_PAD_SD1_CLK__USDHC1_CLK     	0x10059
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10071
 			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 	0x17059
 			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 	0x17059
 			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 	0x17059
@@ -524,6 +532,51 @@
 		>;
 	};
 
+	pinctrl_usdhc2_8bit: usdhc2grp_8bit {
+		fsl,pins = <
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
+			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
+			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
+			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
+		>;
+	};
+
+	pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
+		fsl,pins = <
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100b9
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170b9
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
+			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
+			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
+			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
+			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
+		>;
+	};
+
+	pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
+		fsl,pins = <
+			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100f9
+			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170f9
+			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
+			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
+			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
+			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
+		>;
+	};
+
 	pinctrl_wdog: wdoggrp {
 		fsl,pins = <
 			MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
diff --git a/arch/arm/dts/imx6ul-14x14-lpddr2-val.dts b/arch/arm/dts/imx6ul-14x14-lpddr2-val.dts
new file mode 100644
index 00000000000..695cb107468
--- /dev/null
+++ b/arch/arm/dts/imx6ul-14x14-lpddr2-val.dts
@@ -0,0 +1,779 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx6ul.dtsi"
+
+/ {
+	model = "i.MX6 UltraLite 14X14 LPDDR2 VAL Board";
+	compatible = "fsl,imx6ul-14x14-lpddr2-val", "fsl,imx6ul";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory {
+		reg = <0x80000000 0x20000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x14000000>;
+			linux,cma-default;
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_sd1_vmmc: sd1_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "SD1_SPWR";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio4 11 GPIO_ACTIVE_HIGH>;
+			u-boot,off-on-delay-us = <20000>;
+			enable-active-high;
+		};
+
+		reg_sd2_vmmc: sd2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "SD2_SPWR";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_can1_3v3: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "can1-3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio1 15 GPIO_ACTIVE_LOW>;
+		};
+
+		reg_vref_3v3: regulator@1 {
+			compatible = "regulator-fixed";
+			regulator-name = "vref-3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+		reg_usb_otg1_vbus: regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb_otg1>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+	};
+};
+
+&ecspi2 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio4 22 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi2_1 &pinctrl_ecspi2_cs_1>;
+	status = "disabled";
+
+	flash: n25q032@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,n25q032";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&cpu0 {
+	/*
+	 * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN,
+	 * to align with other platform and use the same cpufreq
+	 * driver, still use the seperated OPP define for arm
+	 * and soc.
+	 */
+	operating-points = <
+		/* kHz	uV */
+		528000	1175000
+		396000	1175000
+		198000	1175000
+	>;
+	fsl,soc-operating-points = <
+		/* KHz	uV */
+		528000	1175000
+		396000	1175000
+		198000	1175000
+	>;
+	fsl,arm-soc-shared = <1>;
+};
+
+&reg_arm {
+	vin-supply = <&sw1a_reg>;
+	regulator-allow-bypass;
+};
+
+&reg_soc {
+	vin-supply = <&sw1a_reg>;
+	regulator-allow-bypass;
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	phy-mode = "mii";
+	phy-handle = <&ethphy0>;
+	status = "disabled";
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy1>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+		};
+
+		ethphy1: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+	};
+};
+
+&can1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	xceiver-supply = <&reg_can1_3v3>;
+	status = "disabled";
+};
+
+&gpc {
+	fsl,cpu_pupscr_sw2iso = <0xf>;
+	fsl,cpu_pupscr_sw = <0x0>;
+	fsl,cpu_pdnscr_iso2sw = <0x1>;
+	fsl,cpu_pdnscr_iso = <0x1>;
+	fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "disabled";
+	nand-on-flash-bbt;
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	status = "okay";
+
+	pmic: pfuze100@8 {
+		compatible = "fsl,pfuze200";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			sw3b_reg: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi>;
+	status = "disabled";
+	fsl,qspi-has-second-chip = <1>;
+	ddrsmp=<0>;
+
+	flash0: n25q256a@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <0>;
+	};
+
+	flash1: n25q256a@1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <1>;
+	};
+
+	flash2: n25q256a@2 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <2>;
+	};
+
+	flash3: n25q256a@3 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <3>;
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_otg1_id>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	cd-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sd1_vmmc>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2_8bit>;
+	pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
+	keep-power-in-suspend;
+	vmmc-supply = <&reg_sd2_vmmc>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog &pinctrl_hog_nand>;
+
+	imx6ul-14x14-lpddr2-val {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				MX6UL_PAD_CSI_DATA05__GPIO4_IO26	0x17059	/* SD1 CD */
+				MX6UL_PAD_CSI_DATA04__GPIO4_IO25	0x17059	/* SD1 WP */
+				MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT	0x17059	/* SD1 VSELECT */
+				MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT    0x17059 /* SD2 VSELECT */
+			>;
+		};
+
+		pinctrl_hog_nand: hoggrp_nand {
+			fsl,pins = <
+				MX6UL_PAD_NAND_WP_B__GPIO4_IO11         0x17059 /* SD1 RESET */
+				MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x17059 /* SD2 RESET */
+			>;
+		};
+
+		pinctrl_ecspi2_cs_1: ecspi2_cs_grp-1 {
+			fsl,pins = <
+				MX6UL_PAD_CSI_DATA01__GPIO4_IO22  0x10b0
+			>;
+		};
+
+		pinctrl_ecspi2_1: ecspi2grp-1 {
+			fsl,pins = <
+				MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x10b0
+				MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x10b0
+				MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x10b0
+			>;
+		};
+
+		pinctrl_enet1: enet1grp {
+			fsl,pins = <
+				MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
+				MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
+				MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
+				MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
+				MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02	0x1b0b0
+				MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03	0x1b0b0
+				MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK	0x4b01b0a8
+				MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
+				MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
+				MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02	0x1b0b0
+				MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03	0x1b0b0
+				MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK	0x4b01b0a8
+				MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
+				MX6UL_PAD_UART2_RTS_B__ENET1_COL	0x1b0b0
+				MX6UL_PAD_UART2_CTS_B__ENET1_CRS	0x1b0b0
+			>;
+		};
+
+		pinctrl_enet2: enet2grp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
+				MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
+				MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
+				MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
+				MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
+				MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b0a8
+				MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
+				MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
+				MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
+				MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
+				MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK	0x4001b0a8
+				MX6UL_PAD_UART5_RX_DATA__ENET2_COL	0x1b0b0
+				MX6UL_PAD_UART5_TX_DATA__ENET2_CRS	0x1b0b0
+			>;
+		};
+
+		pinctrl_flexcan1: flexcan1grp{
+			fsl,pins = <
+				MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX	0x1b020
+				MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX	0x1b020
+				MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15	0x17059	/* STBY */
+			>;
+		};
+
+		pinctrl_gpmi_nand_1: gpmi-nand-1 {
+			fsl,pins = <
+				MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
+				MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
+				MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
+				MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
+				MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
+				MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B     0xb0b1
+				MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
+				MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
+				MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
+				MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
+				MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
+				MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
+				MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
+				MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
+				MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
+				MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX6UL_PAD_CSI_VSYNC__I2C2_SDA	        0x4001b8b0
+				MX6UL_PAD_CSI_HSYNC__I2C2_SCL          	0x4001b8b0
+			>;
+		};
+
+		pinctrl_lcdif_dat: lcdifdatgrp {
+			fsl,pins = <
+				MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
+				MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
+				MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
+				MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
+				MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
+				MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
+				MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
+				MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
+				MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
+				MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
+				MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
+				MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
+				MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
+				MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
+				MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
+				MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
+				MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
+				MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
+				MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
+				MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
+				MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
+				MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
+				MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
+				MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
+			>;
+		};
+
+		pinctrl_lcdif_ctrl: lcdifctrlgrp {
+			fsl,pins = <
+				MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x79
+				MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
+				MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
+				MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
+				MX6UL_PAD_LCD_RESET__LCDIF_RESET    0x79
+			>;
+		};
+
+		pinctrl_pwm1: pmw1grp {
+			fsl,pins = <
+				MX6UL_PAD_NAND_DQS__PWM5_OUT        0x110b0
+			>;
+		};
+
+		pinctrl_qspi: qspigrp {
+			fsl,pins = <
+				MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK      0x70a1
+				MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
+				MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01   0x70a1
+				MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02   0x70a1
+				MX6UL_PAD_NAND_CLE__QSPI_A_DATA03     0x70a1
+				MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B      0x70a1
+				MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B   0x70a1
+				MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK      0x70a1
+				MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00  0x70a1
+				MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01  0x70a1
+				MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02  0x70a1
+				MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03  0x70a1
+				MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B     0x70a1
+				MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B   0x70a1
+			>;
+		};
+
+		pinctrl_mqs: mqsgrp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO01__MQS_LEFT         0x11088
+				MX6UL_PAD_GPIO1_IO00__MQS_RIGHT        0x11088
+			>;
+		};
+
+		pinctrl_sai1: sai1grp {
+			fsl,pins = <
+				MX6UL_PAD_CSI_DATA01__SAI1_MCLK        0x1b0b0
+				MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC     0x1b0b0
+				MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK     0x1b0b0
+				MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC     0x1b0b0
+				MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK     0x1b0b0
+				MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA     0x110b0
+				MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA     0x1f0b8
+				MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00     0x17059
+			>;
+		};
+
+		pinctrl_spdif: spdifgrp {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__SPDIF_OUT           0x1b0b0
+				MX6UL_PAD_SD1_CLK__SPDIF_IN            0x1b0b0
+			>;
+		};
+
+		pinctrl_tsc: tscgrp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0xb0
+				MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0xb0
+				MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
+				MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0xb0
+			>;
+		};
+
+		pinctrl_adc1: adc1grp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO00__GPIO1_IO00        0xb0
+				MX6UL_PAD_GPIO1_IO01__GPIO1_IO01        0xb0
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO03__I2C1_SDA	0x4001b8b1
+				MX6UL_PAD_GPIO1_IO02__I2C1_SCL	0x4001b8b1
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+				MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+			>;
+		};
+
+		pinctrl_uart2: uart2grp {
+			fsl,pins = <
+				MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
+				MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
+				MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS  0x1b0b1
+				MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS  0x1b0b1
+			>;
+		};
+
+		pinctrl_uart2dte: uart2dtegrp {
+			fsl,pins = <
+				MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
+				MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
+				MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS  0x1b0b1
+				MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS  0x1b0b1
+			>;
+		};
+
+		pinctrl_usb_otg1_id: usbotg1idgrp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
+			>;
+		};
+
+		pinctrl_usb_otg1: usbotg1grp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO04__GPIO1_IO04        0x10b0
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+			>;
+		};
+
+		pinctrl_usdhc1_8bit: usdhc1_8bit_grp {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x17059
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     	0x10059
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 	0x17059
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 	0x17059
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 	0x17059
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 	0x17059
+				MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x17059
+				MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x17059
+				MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x17059
+				MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x17059
+			>;
+		};
+
+		pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x170b9
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     	0x100b9
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 	0x170b9
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 	0x170b9
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 	0x170b9
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 	0x170b9
+				MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x170b9
+				MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x170b9
+				MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x170b9
+				MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x170b9
+			>;
+		};
+
+		pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x170f9
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     	0x100f9
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 	0x170f9
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 	0x170f9
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 	0x170f9
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 	0x170f9
+				MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x170f9
+				MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x170f9
+				MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x170f9
+				MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x170f9
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x17059
+				MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10059
+				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x17059
+				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x17059
+				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x17059
+				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x17059
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170b9
+				MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100b9
+				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170b9
+				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170b9
+				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170b9
+				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170b9
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170f9
+				MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100f9
+				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170f9
+				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170f9
+				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170f9
+				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170f9
+			>;
+		};
+
+		pinctrl_usdhc2_8bit: usdhc2_8bit_grp {
+			fsl,pins = <
+				MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x17059
+				MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x10059
+				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x17059
+				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x17059
+				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x17059
+				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x17059
+				MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x17059
+				MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x17059
+				MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x17059
+				MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x17059
+			>;
+		};
+
+		pinctrl_usdhc2_8bit_100mhz: usdhc2_8bit_100mhz_grp {
+			fsl,pins = <
+				MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170b9
+				MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100b9
+				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170b9
+				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170b9
+				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170b9
+				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170b9
+				MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x170b9
+				MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x170b9
+				MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x170b9
+				MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x170b9
+			>;
+		};
+
+		pinctrl_usdhc2_8bit_200mhz: usdhc2_8bit_200mhz_grp {
+			fsl,pins = <
+				MX6UL_PAD_NAND_WE_B__USDHC2_CMD		0x170f9
+				MX6UL_PAD_NAND_RE_B__USDHC2_CLK		0x100f9
+				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170f9
+				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170f9
+				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170f9
+				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170f9
+				MX6UL_PAD_NAND_DATA04__USDHC2_DATA4	0x170f9
+				MX6UL_PAD_NAND_DATA05__USDHC2_DATA5	0x170f9
+				MX6UL_PAD_NAND_DATA06__USDHC2_DATA6	0x170f9
+				MX6UL_PAD_NAND_DATA07__USDHC2_DATA7	0x170f9
+			>;
+		};
+	};
+};
diff --git a/arch/arm/dts/imx6ul-9x9-evk-u-boot.dtsi b/arch/arm/dts/imx6ul-9x9-evk-u-boot.dtsi
index 77cb461a215..4a8311dd378 100644
--- a/arch/arm/dts/imx6ul-9x9-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx6ul-9x9-evk-u-boot.dtsi
@@ -3,8 +3,29 @@
  * Copyright 2018 NXP
  */
 
+&{/aliases} {
+	u-boot,dm-pre-reloc;
+	display0 = &lcdif;
+};
+
 &qspi {
 	flash0: n25q256a@0 {
 		compatible = "jedec,spi-nor";
 	};
-};
\ No newline at end of file
+};
+
+&{/soc} {
+	u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+	u-boot,dm-pre-reloc;
+};
+
+&iomuxc {
+	u-boot,dm-pre-reloc;
+};
+
+&lcdif {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/imx6ul-9x9-evk.dts b/arch/arm/dts/imx6ul-9x9-evk.dts
index 2270451121b..55b85e02a6e 100644
--- a/arch/arm/dts/imx6ul-9x9-evk.dts
+++ b/arch/arm/dts/imx6ul-9x9-evk.dts
@@ -9,7 +9,7 @@
 #include "imx6ul.dtsi"
 
 / {
-	model = "Freescale i.MX6 UltraLite 9x9 EVK Board";
+	model = "i.MX6 UltraLite 9x9 EVK Board";
 	compatible = "fsl,imx6ul-9x9-evk", "fsl,imx6ul";
 
 	aliases {
@@ -56,7 +56,7 @@
 			regulator-min-microvolt = <3300000>;
 			regulator-max-microvolt = <3300000>;
 			gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
-			off-on-delay = <20000>;
+			off-on-delay-us = <20000>;
 			enable-active-high;
 		};
 	};
@@ -126,7 +126,7 @@
 	sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
-	pmic: pfuze3000@08 {
+	pmic: pfuze3000@8 {
 		compatible = "fsl,pfuze3000";
 		reg = <0x08>;
 
@@ -217,7 +217,7 @@
 		};
 	};
 
-	mag3110@0e {
+	mag3110@e {
 		compatible = "fsl,mag3110";
 		reg = <0x0e>;
 		position = <2>;
@@ -318,6 +318,46 @@
 			>;
 		};
 
+		pinctrl_lcdif_ctrl: lcdifctrlgrp {
+			fsl,pins = <
+				MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x79
+				MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
+				MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
+				MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
+				/* used for lcd reset */
+				MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
+			>;
+		};
+
+		pinctrl_lcdif_dat: lcdifdatgrp {
+			fsl,pins = <
+				MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
+				MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
+				MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
+				MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
+				MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
+				MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
+				MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
+				MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
+				MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
+				MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
+				MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
+				MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
+				MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
+				MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
+				MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
+				MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
+				MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
+				MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
+				MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
+				MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
+				MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
+				MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
+				MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
+				MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
+			>;
+		};
+
 		pinctrl_qspi: qspigrp {
 			fsl,pins = <
 				MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK      0x70a1
@@ -404,6 +444,41 @@
 	};
 };
 
+
+&lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif_dat
+		     &pinctrl_lcdif_ctrl>;
+
+	display = <&display0>;
+	status = "okay";
+
+	display0: display {
+		bits-per-pixel = <24>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+			clock-frequency = <9200000>;
+			hactive = <480>;
+			vactive = <272>;
+			hfront-porch = <8>;
+			hback-porch = <4>;
+			hsync-len = <41>;
+			vback-porch = <2>;
+			vfront-porch = <4>;
+			vsync-len = <10>;
+
+			hsync-active = <0>;
+			vsync-active = <0>;
+			de-active = <1>;
+			pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
 &qspi {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_qspi>;
diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi
index ad9cb37db77..3384bff5dc5 100644
--- a/arch/arm/dts/imx6ul.dtsi
+++ b/arch/arm/dts/imx6ul.dtsi
@@ -52,6 +52,8 @@
 		usbphy1 = &usbphy2;
 		usb0 = &usbotg1;
 		usb1 = &usbotg2;
+		usbgadget0 = &usbg1;
+		usbgadget1 = &usbg2;
 	};
 
 	cpus {
@@ -800,6 +802,20 @@
 				};
 			};
 
+			usbg1: usbg1 {
+				compatible = "fsl,imx27-usb-gadget";
+				dr_mode = "peripheral";
+				chipidea,usb = <&usbotg1>;
+				status = "okay";
+			};
+
+			usbg2: usbg2 {
+				compatible = "fsl,imx27-usb-gadget";
+				dr_mode = "peripheral";
+				chipidea,usb = <&usbotg2>;
+				status = "okay";
+			};
+
 			usbotg1: usb@2184000 {
 				compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 				reg = <0x02184000 0x200>;
diff --git a/arch/arm/dts/imx6ull-14x14-ddr3-val-emmc.dts b/arch/arm/dts/imx6ull-14x14-ddr3-val-emmc.dts
new file mode 100644
index 00000000000..966ce614f96
--- /dev/null
+++ b/arch/arm/dts/imx6ull-14x14-ddr3-val-emmc.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6ull-14x14-ddr3-val.dts"
+
+&usdhc1 {
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	cd-gpios = <>;
+	wp-gpios = <>;
+	vmmc-supply = <>;
+	non-removable;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6ull-14x14-ddr3-val-epdc.dts b/arch/arm/dts/imx6ull-14x14-ddr3-val-epdc.dts
new file mode 100644
index 00000000000..5d521dafaff
--- /dev/null
+++ b/arch/arm/dts/imx6ull-14x14-ddr3-val-epdc.dts
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6ull-14x14-ddr3-val.dts"
+
+&epdc {
+        status = "okay";
+};
+
+&fec2 {
+        status = "disabled";
+};
+
+&lcdif {
+        status = "disabled";
+};
+
+&max17135 {
+        status = "okay";
+};
diff --git a/arch/arm/dts/imx6ull-14x14-ddr3-val-gpmi-weim.dts b/arch/arm/dts/imx6ull-14x14-ddr3-val-gpmi-weim.dts
new file mode 100644
index 00000000000..3c6cdf00171
--- /dev/null
+++ b/arch/arm/dts/imx6ull-14x14-ddr3-val-gpmi-weim.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6ull-14x14-ddr3-val.dts"
+
+&gpmi {
+	status ="okay";
+};
+
+&qspi {
+	status ="disabled";
+};
+
+&usdhc2{
+	status ="disabled";
+};
diff --git a/arch/arm/dts/imx6ull-14x14-ddr3-val-lcdif.dts b/arch/arm/dts/imx6ull-14x14-ddr3-val-lcdif.dts
new file mode 100644
index 00000000000..cb7f1d9cbcd
--- /dev/null
+++ b/arch/arm/dts/imx6ull-14x14-ddr3-val-lcdif.dts
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* DTS file for LCDIF at imx6ull ddr3 val board */
+
+#include "imx6ull-14x14-ddr3-val.dts"
+
+/ {
+	backlight {
+		status = "okay";
+	};
+};
+
+&fec1 {
+	status = "disabled";
+};
+
+&lcdif {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6ull-14x14-ddr3-val-tsc.dts b/arch/arm/dts/imx6ull-14x14-ddr3-val-tsc.dts
new file mode 100644
index 00000000000..95084f5a780
--- /dev/null
+++ b/arch/arm/dts/imx6ull-14x14-ddr3-val-tsc.dts
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6ull-14x14-ddr3-val-lcdif.dts"
+
+&i2c1 {
+	status = "disabled";
+};
+
+&reg_usb_otg1_vbus {
+	pinctrl-0 = < >;
+	gpio = < >;
+};
+
+&usbotg1 {
+	status = "disabled";
+};
+
+&tsc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_tsc>;
+	status = "okay";
+	xnur-gpio = <&gpio1 3 0>;
+	measure_delay_time = <0xfff>;
+	pre_charge_time = <0xffff>;
+};
diff --git a/arch/arm/dts/imx6ull-14x14-ddr3-val.dts b/arch/arm/dts/imx6ull-14x14-ddr3-val.dts
new file mode 100644
index 00000000000..e465297b829
--- /dev/null
+++ b/arch/arm/dts/imx6ull-14x14-ddr3-val.dts
@@ -0,0 +1,1009 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx6ull.dtsi"
+
+/ {
+	model = "i.MX6 ULL DDR3 VAL Board";
+	compatible = "fsl,imx6ull-ddr3-val", "fsl,imx6ull";
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory {
+		reg = <0x80000000 0x40000000>;
+	};
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm1 0 5000000>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+		status = "disabled";
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_sd1_vmmc: sd1_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "SD1_SPWR";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+			u-boot,off-on-delay-us = <20000>;
+			enable-active-high;
+		};
+
+		reg_sd2_vmmc: sd2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "SD2_SPWR";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>;
+			off-on-delay-us = <20000>;
+			enable-active-high;
+		};
+
+		reg_can2_3v3: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "can2-3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio1 15 GPIO_ACTIVE_LOW>;
+		};
+
+		reg_vref_3v3: regulator@1 {
+			compatible = "regulator-fixed";
+			regulator-name = "vref-3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+
+		reg_usb_otg1_vbus: regulator@2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb_otg1>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+	};
+};
+
+&clks {
+	/* For bringup, comments this.
+	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+	assigned-clock-rates = <786432000>;
+	*/
+};
+
+&cpu0 {
+	/*
+	 * on i.MX6ULL, no seperated VDD_ARM_IN and VDD_SOC_IN,
+	 * to align with other platform and use the same cpufreq
+	 * driver, still use the seperated OPP define for arm
+	 * and soc.
+	 */
+	operating-points = <
+		/* kHz	uV */
+		528000	1175000
+		396000	1175000
+		198000	1175000
+	>;
+	fsl,soc-operating-points = <
+		/* KHz	uV */
+		528000	1175000
+		396000	1175000
+		198000	1175000
+	>;
+	fsl,arm-soc-shared = <1>;
+};
+
+&reg_arm {
+	vin-supply = <&sw1a_reg>;
+	regulator-allow-bypass;
+};
+
+&reg_soc {
+	vin-supply = <&sw1a_reg>;
+	regulator-allow-bypass;
+};
+
+&ecspi1 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio4 26 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>;
+	status = "disabled";
+
+	flash: n25q032@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,n25q032", "jedec,spi-nor";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&epdc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_epdc0>;
+	V3P3-supply = <&V3P3_reg>;
+	VCOM-supply = <&VCOM_reg>;
+	DISPLAY-supply = <&DISPLAY_reg>;
+	status = "disabled";
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy0>;
+	status = "okay";
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2>;
+	phy-mode = "mii";
+	phy-handle = <&ethphy1>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+
+		ethphy1: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+		};
+	};
+};
+
+&can2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	xceiver-supply = <&reg_can2_3v3>;
+	status = "disabled";
+};
+
+&gpc {
+	fsl,cpu_pupscr_sw2iso = <0xf>;
+	fsl,cpu_pupscr_sw = <0x0>;
+	fsl,cpu_pdnscr_iso2sw = <0x1>;
+	fsl,cpu_pdnscr_iso = <0x1>;
+	fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "disabled";
+	nand-on-flash-bbt;
+	fsl,use-minimum-ecc;
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pfuze100@8 {
+		compatible = "fsl,pfuze200";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			sw3b_reg: sw3b {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c4 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	pinctrl-1 = <&pinctrl_i2c4_gpio>;
+	scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	max17135: max17135@48 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_max17135>;
+		compatible = "maxim,max17135";
+		reg = <0x48>;
+		status = "disabled";
+
+		vneg_pwrup = <1>;
+		gvee_pwrup = <2>;
+		vpos_pwrup = <10>;
+		gvdd_pwrup = <12>;
+		gvdd_pwrdn = <1>;
+		vpos_pwrdn = <2>;
+		gvee_pwrdn = <8>;
+		vneg_pwrdn = <10>;
+		gpio_pmic_pwrgood = <&gpio3 16 0>;
+		gpio_pmic_vcom_ctrl = <&gpio3 24 0>;
+		gpio_pmic_wakeup = <&gpio3 14 0>;
+		gpio_pmic_v3p3 = <&gpio3 17 0>;
+		gpio_pmic_intr = <&gpio3 13 0>;
+
+		regulators {
+			DISPLAY_reg: DISPLAY {
+				regulator-name = "DISPLAY";
+			};
+
+			GVDD_reg: GVDD {
+				/* 20v */
+				regulator-name = "GVDD";
+			};
+
+			GVEE_reg: GVEE {
+				/* -22v */
+				regulator-name = "GVEE";
+			};
+
+			HVINN_reg: HVINN {
+				/* -22v */
+				regulator-name = "HVINN";
+			};
+
+			HVINP_reg: HVINP {
+				/* 20v */
+				regulator-name = "HVINP";
+			};
+
+			VCOM_reg: VCOM {
+				regulator-name = "VCOM";
+				/* Real max: -500000 */
+				regulator-max-microvolt = <4325000>;
+				/* Real min: -4325000 */
+				regulator-min-microvolt = <500000>;
+			};
+
+			VNEG_reg: VNEG {
+				/* -15v */
+				regulator-name = "VNEG";
+			};
+
+			VPOS_reg: VPOS {
+				/* 15v */
+				regulator-name = "VPOS";
+			};
+
+			V3P3_reg: V3P3 {
+				regulator-name = "V3P3";
+			};
+		};
+	};
+};
+
+&iomuxc {
+	imx6ull-ddr3-val {
+		pinctrl_adc1: adc1grp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO00__GPIO1_IO00        0xb0
+				MX6UL_PAD_GPIO1_IO01__GPIO1_IO01        0xb0
+			>;
+		};
+
+
+		pinctrl_csi1: csi1grp {
+			fsl,pins = <
+				MX6UL_PAD_CSI_MCLK__CSI_MCLK		0x1b088
+				MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK	0x1b088
+				MX6UL_PAD_CSI_VSYNC__CSI_VSYNC		0x1b088
+				MX6UL_PAD_CSI_HSYNC__CSI_HSYNC		0x1b088
+				MX6UL_PAD_CSI_DATA00__CSI_DATA02	0x1b088
+				MX6UL_PAD_CSI_DATA01__CSI_DATA03	0x1b088
+				MX6UL_PAD_CSI_DATA02__CSI_DATA04	0x1b088
+				MX6UL_PAD_CSI_DATA03__CSI_DATA05	0x1b088
+				MX6UL_PAD_CSI_DATA04__CSI_DATA06	0x1b088
+				MX6UL_PAD_CSI_DATA05__CSI_DATA07	0x1b088
+				MX6UL_PAD_CSI_DATA06__CSI_DATA08	0x1b088
+				MX6UL_PAD_CSI_DATA07__CSI_DATA09	0x1b088
+			>;
+		};
+
+		pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 {
+			fsl,pins = <
+				MX6UL_PAD_CSI_DATA05__GPIO4_IO26  0x10b0
+			>;
+		};
+
+		pinctrl_ecspi1_1: ecspi1grp-1 {
+			fsl,pins = <
+				MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x10b0
+				MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x10b0
+				MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x10b0
+			>;
+		};
+
+		pinctrl_enet1: enet1grp {
+			fsl,pins = <
+				MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
+				MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
+				MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
+				MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
+				MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
+				MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
+				MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
+				MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b0a0
+			>;
+		};
+
+		pinctrl_enet2: enet2grp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b098
+				MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
+				MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0a0
+				MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0a0
+				MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02	0x1b0a0
+				MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03	0x1b0a0
+				MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK	0x4001b0a8
+				MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
+				MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
+				MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
+				MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02	0x1b0b0
+				MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03	0x1b0b0
+				MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
+				MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
+				MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK	0x4001b0a8
+				MX6UL_PAD_UART5_RX_DATA__ENET2_COL	0x1b0b0
+				MX6UL_PAD_UART5_TX_DATA__ENET2_CRS	0x1b0b0
+			>;
+		};
+
+                pinctrl_epdc0: epdcgrp0 {
+                        fsl,pins = <
+				MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08                    0x10b1
+				MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09                    0x10b1
+				MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10                       0x10b1
+				MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11                    0x10b1
+				MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12                    0x10b1
+				MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13                       0x10b1
+				MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14                      0x10b1
+				MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15                       0x10b1
+				MX6ULL_PAD_LCD_CLK__EPDC_SDCLK                            0x10b1
+				MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE                          0x10b1
+				MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE                           0x10b1
+				MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0                          0x10b1
+				MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00                        0x10b1
+				MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01                        0x10b1
+				MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02                        0x10b1
+				MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03                        0x10b1
+				MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04                        0x10b1
+				MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05                        0x10b1
+				MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06                        0x10b1
+				MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07                        0x10b1
+				MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR                         0x10b1
+				MX6ULL_PAD_LCD_DATA15__EPDC_GDRL                          0x10b1
+				MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK                         0x10b1
+				MX6ULL_PAD_LCD_DATA17__EPDC_GDSP                          0x10b1
+				MX6ULL_PAD_LCD_RESET__EPDC_GDOE                           0x10b1
+                        >;
+                };
+
+		pinctrl_esai: esaigrp {
+			fsl,pins = <
+				MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK     0x1b0b0
+				MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK     0x1b0b0
+				MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS         0x1b0b0
+				MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK        0x1b0b0
+				MX6ULL_PAD_CSI_DATA07__ESAI_TX0           0x1b0b0
+				MX6ULL_PAD_CSI_HSYNC__ESAI_TX1            0x1b0b0
+				MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3       0x1b0b0
+				MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2         0x1b0b0
+				MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS         0x1b0b0
+				MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK        0x1b0b0
+				MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0       0x1b0b0
+				MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1        0x1b0b0
+			>;
+		};
+
+		pinctrl_flexcan2: flexcan2grp{
+			fsl,pins = <
+				MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
+				MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
+				MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15	0x17059	/* STBY */
+			>;
+		};
+
+		pinctrl_gpmi_nand_1: gpmi-nand-1 {
+			fsl,pins = <
+				MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
+				MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
+				MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
+				MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
+				MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
+				MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B     0xb0b1
+				MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
+				MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
+				MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
+				MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
+				MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
+				MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
+				MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
+				MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
+				MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
+				MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO03__I2C1_SDA	0x4001b8b1
+				MX6UL_PAD_GPIO1_IO02__I2C1_SCL	0x4001b8b1
+			>;
+		};
+
+		pinctrl_i2c1_gpio: i2c1grp_gpio {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO03__GPIO1_IO03  0x1b8b1
+				MX6UL_PAD_GPIO1_IO02__GPIO1_IO02  0x1b8b1
+			>;
+		};
+
+		pinctrl_i2c4: i2c4grp {
+			fsl,pins = <
+				MX6UL_PAD_UART2_TX_DATA__I2C4_SCL	0x4001b8b0
+				MX6UL_PAD_UART2_RX_DATA__I2C4_SDA	0x4001b8b0
+			>;
+		};
+
+		pinctrl_i2c4_gpio: i2c4grp_gpio {
+			fsl,pins = <
+				MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20	0x1b8b0
+				MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21	0x1b8b0
+			>;
+		};
+
+		pinctrl_lcdif_dat: lcdifdatgrp {
+			fsl,pins = <
+				MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
+				MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
+				MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
+				MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
+				MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
+				MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
+				MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
+				MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
+				MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
+				MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
+				MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
+				MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
+				MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
+				MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
+				MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
+				MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
+				MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
+				MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
+				MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
+				MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
+				MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
+				MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
+				MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
+				MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
+			>;
+		};
+
+		pinctrl_lcdif_ctrl: lcdifctrlgrp {
+			fsl,pins = <
+				MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x79
+				MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
+				MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
+				MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
+				MX6UL_PAD_LCD_RESET__LCDIF_RESET    0x79
+			>;
+		};
+
+		pinctrl_max17135: max17135grp-1 {
+			fsl,pins = <
+				MX6UL_PAD_LCD_DATA11__GPIO3_IO16	0x80000000  /* pwrgood */
+				MX6UL_PAD_LCD_DATA19__GPIO3_IO24	0x80000000  /* vcom_ctrl */
+				MX6UL_PAD_LCD_DATA09__GPIO3_IO14	0x80000000  /* wakeup */
+				MX6UL_PAD_LCD_DATA12__GPIO3_IO17	0x80000000  /* v3p3 */
+				MX6UL_PAD_LCD_DATA08__GPIO3_IO13	0x80000000  /* pwr int */
+			>;
+		};
+
+		pinctrl_mqs: mqsgrp {
+			fsl,pins = <
+				MX6UL_PAD_JTAG_TDI__MQS_LEFT         0x11088
+				MX6UL_PAD_JTAG_TDO__MQS_RIGHT        0x11088
+			>;
+		};
+
+		pinctrl_pwm1: pmw1grp {
+			fsl,pins = <
+				MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT   0x110b0
+			>;
+		};
+
+		pinctrl_qspi: qspigrp {
+			fsl,pins = <
+				MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK      0x70a1
+				MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
+				MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01   0x70a1
+				MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02   0x70a1
+				MX6UL_PAD_NAND_CLE__QSPI_A_DATA03     0x70a1
+				MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B      0x70a1
+#ifdef REWORKED_ENABLE_ALL_QSPI
+				MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B   0x70a1
+				MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK      0x70a1
+				MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00  0x70a1
+				MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01  0x70a1
+				MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02  0x70a1
+				MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03  0x70a1
+				MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B     0x70a1
+				MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B   0x70a1
+#endif
+			>;
+		};
+
+		pinctrl_sai2: sai2grp {
+			fsl,pins = <
+				MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC     0x1b0b0
+				MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK     0x1b0b0
+				MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA     0x110b0
+				MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA     0x110b0
+				MX6UL_PAD_SD1_CLK__SAI2_MCLK          0x1b0b0
+			>;
+		};
+
+		pinctrl_spdif: spdifgrp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO08__SPDIF_OUT       0x1b0b0
+				MX6UL_PAD_GPIO1_IO09__SPDIF_IN        0x1b0b0
+			>;
+		};
+
+		pinctrl_tsc: tscgrp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0xb0
+				MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0xb0
+				MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
+				MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0xb0
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+				MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+			>;
+		};
+
+		pinctrl_uart2: uart2grp {
+			fsl,pins = <
+				MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
+				MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
+				MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS  0x1b0b1
+				MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS  0x1b0b1
+			>;
+		};
+
+		pinctrl_uart2dte: uart2dtegrp {
+			fsl,pins = <
+				MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
+				MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
+				MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS  0x1b0b1
+				MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS  0x1b0b1
+			>;
+		};
+
+		pinctrl_usb_otg1_id: usbotg1idgrp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
+			>;
+		};
+
+		pinctrl_usb_otg1: usbotg1grp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO04__GPIO1_IO04        0x10b0
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+			>;
+		};
+
+		pinctrl_usdhc1_8bit: usdhc1_8bit_grp {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x17059
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     	0x10059
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 	0x17059
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 	0x17059
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 	0x17059
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 	0x17059
+				MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x17059
+				MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x17059
+				MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x17059
+				MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x17059
+			>;
+		};
+
+		pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x170b9
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     	0x100b9
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 	0x170b9
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 	0x170b9
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 	0x170b9
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 	0x170b9
+				MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x170b9
+				MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x170b9
+				MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x170b9
+				MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x170b9
+			>;
+		};
+
+		pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x170f9
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     	0x100f9
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 	0x170f9
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 	0x170f9
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 	0x170f9
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 	0x170f9
+				MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x170f9
+				MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x170f9
+				MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x170f9
+				MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x170f9
+			>;
+		};
+
+		pinctrl_usdhc1_cd_wp: usdhc1_cd_wp_grp {
+			fsl,pins = <
+				MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059	/* SD1 CD */
+				MX6UL_PAD_UART1_CTS_B__GPIO1_IO18	0x17059	/* SD1 WP */
+			>;
+		};
+
+		pinctrl_usdhc1_rst: usdhc1_rst_grp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
+			>;
+		};
+
+		pinctrl_usdhc1_vselect: usdhc1_vselect_grp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT	0x17059	/* SD1 VSELECT */
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6UL_PAD_NAND_WE_B__USDHC2_CMD	0x17059
+				MX6UL_PAD_NAND_RE_B__USDHC2_CLK	0x10059
+				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x17059
+				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x17059
+				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x17059
+				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x17059
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				MX6UL_PAD_NAND_WE_B__USDHC2_CMD	0x170b9
+				MX6UL_PAD_NAND_RE_B__USDHC2_CLK	0x100a9
+				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170a9
+				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170a9
+				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170a9
+				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170a9
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				MX6UL_PAD_NAND_WE_B__USDHC2_CMD	0x170f9
+				MX6UL_PAD_NAND_RE_B__USDHC2_CLK	0x100f9
+				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0	0x170f9
+				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1	0x170f9
+				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2	0x170f9
+				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3	0x170f9
+			>;
+		};
+
+		pinctrl_usdhc2_rst: usdhc2_rst_grp {
+			fsl,pins = <
+				MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x17059 /* SD2 RESET */
+			>;
+		};
+
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B	0x30b0
+			>;
+		};
+	};
+};
+
+&iomuxc_snvs {
+	imx6ull-ddr3-val {
+		pinctrl_bt: btgrp {
+			fsl,pins = <
+				MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06	0x80000000
+				MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09	0x80000000
+				MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05	0x80000000
+			>;
+		};
+
+		pinctrl_sai2_hp_det_b: sai2_hp_det_grp {
+			fsl,pins = <
+				MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00   0x17059
+			>;
+		};
+	};
+};
+
+&lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif_dat
+		     &pinctrl_lcdif_ctrl>;
+	display = <&display0>;
+	status = "disabled";
+
+	display0: display {
+		bits-per-pixel = <16>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+				clock-frequency = <33500000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <89>;
+				hfront-porch = <164>;
+				vback-porch = <23>;
+				vfront-porch = <10>;
+				hsync-len = <10>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "disabled";
+};
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi>;
+	status = "okay";
+#ifdef REWORKED_ENABLE_ALL_QSPI
+	fsl,qspi-has-second-chip = <1>;
+#endif
+	ddrsmp=<0>;
+
+	flash0: n25q256a@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <0>;
+	};
+
+#ifdef REWORKED_ENABLE_ALL_QSPI
+
+	flash1: n25q256a@1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <1>;
+	};
+
+	flash2: n25q256a@2 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <2>;
+	};
+
+	flash3: n25q256a@3 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <3>;
+	};
+#endif
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2
+		     &pinctrl_bt>;
+	fsl,uart-has-rtscts;
+	/* for DTE mode, add below change */
+	/* fsl,dte-mode; */
+	/* pinctrl-0 = <&pinctrl_uart2dte>; */
+	status = "disabled";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_otg1_id>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>;
+	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sd1_vmmc>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_rst>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_rst>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_rst>;
+	non-removable;
+	no-1-8-v;	/* VSELECT not connected by default */
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sd2_vmmc>;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+};
diff --git a/arch/arm/dts/imx6ull-14x14-evk-emmc.dts b/arch/arm/dts/imx6ull-14x14-evk-emmc.dts
new file mode 100644
index 00000000000..d6dc9121b74
--- /dev/null
+++ b/arch/arm/dts/imx6ull-14x14-evk-emmc.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#include "imx6ull-14x14-evk.dts"
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2_8bit>;
+	pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
diff --git a/arch/arm/dts/imx6ull-14x14-evk-gpmi-weim.dts b/arch/arm/dts/imx6ull-14x14-evk-gpmi-weim.dts
new file mode 100644
index 00000000000..8c41e6b9899
--- /dev/null
+++ b/arch/arm/dts/imx6ull-14x14-evk-gpmi-weim.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2016 Freescale Semiconductor, Inc.
+
+#include "imx6ull-14x14-evk.dts"
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "okay";
+	nand-on-flash-bbt;
+	fsl,use-minimum-ecc;
+};
+
+&iomuxc {
+	pinctrl_gpmi_nand_1: gpmi-nand-1 {
+		fsl,pins = <
+			MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
+			MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
+			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
+			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
+			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
+			MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B     0xb0b1
+			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
+			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
+			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
+			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
+			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
+			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
+			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
+			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
+			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
+			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
+		>;
+	};
+};
+
+&qspi {
+	status = "disabled";
+};
+
+&usdhc2 {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/imx6ull-14x14-evk.dts b/arch/arm/dts/imx6ull-14x14-evk.dts
index 74aaa8a56a3..1542335f9ab 100644
--- a/arch/arm/dts/imx6ull-14x14-evk.dts
+++ b/arch/arm/dts/imx6ull-14x14-evk.dts
@@ -6,9 +6,10 @@
 
 #include "imx6ull.dtsi"
 #include "imx6ul-14x14-evk.dtsi"
+#include "imx6ul-14x14-evk-u-boot.dtsi"
 
 / {
-	model = "Freescale i.MX6 UltraLiteLite 14x14 EVK Board";
+	model = "i.MX6 ULL 14x14 EVK Board";
 	compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
 };
 
diff --git a/arch/arm/dts/imx6ull-9x9-evk-u-boot.dtsi b/arch/arm/dts/imx6ull-9x9-evk-u-boot.dtsi
new file mode 100644
index 00000000000..4b692694402
--- /dev/null
+++ b/arch/arm/dts/imx6ull-9x9-evk-u-boot.dtsi
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+&{/aliases} {
+	u-boot,dm-pre-reloc;
+	display0 = &lcdif;
+};
+
+&qspi {
+	flash0: n25q256a@0 {
+		compatible = "jedec,spi-nor";
+	};
+};
+
+&{/soc} {
+	u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+	u-boot,dm-pre-reloc;
+};
+
+&iomuxc {
+	u-boot,dm-pre-reloc;
+};
+
+&iomuxc_snvs {
+	u-boot,dm-pre-reloc;
+};
+
+&lcdif {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/imx6ull-9x9-evk.dts b/arch/arm/dts/imx6ull-9x9-evk.dts
new file mode 100644
index 00000000000..7fab500dad8
--- /dev/null
+++ b/arch/arm/dts/imx6ull-9x9-evk.dts
@@ -0,0 +1,561 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx6ull.dtsi"
+
+/ {
+	model = "i.MX6 ULL 9x9 EVK Board";
+	compatible = "fsl,imx6ull-9x9-evk", "fsl,imx6ull";
+
+	aliases {
+		spi5 = &soft_spi;
+	};
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	memory {
+		reg = <0x80000000 0x10000000>;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_can_3v3: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "can-3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
+		};
+
+		reg_gpio_dvfs: regulator-gpio {
+			compatible = "regulator-gpio";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_dvfs>;
+			regulator-min-microvolt = <1300000>;
+			regulator-max-microvolt = <1400000>;
+			regulator-name = "gpio_dvfs";
+			regulator-type = "voltage";
+			gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
+			states = <1300000 0x1 1400000 0x0>;
+		};
+
+		reg_sd1_vmmc: regulator@1 {
+			compatible = "regulator-fixed";
+			regulator-name = "VSD_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+			off-on-delay-us = <20000>;
+			enable-active-high;
+		};
+	};
+
+	soft_spi: soft-spi {
+		compatible = "spi-gpio";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_spi4>;
+		pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
+		status = "okay";
+		gpio-sck = <&gpio5 11 0>;
+		gpio-mosi = <&gpio5 10 0>;
+		cs-gpios = <&gpio5 7 0>;
+		num-chipselects = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		gpio_spi: gpio_spi@0 {
+			compatible = "fairchild,74hc595";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0>;
+			registers-number = <1>;
+			registers-default = /bits/ 8 <0x57>;
+			spi-max-frequency = <100000>;
+		};
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy0>;
+	status = "okay";
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy1>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+		};
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pfuze3000@8 {
+		compatible = "fsl,pfuze3000";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1a {
+					regulator-min-microvolt = <700000>;
+					regulator-max-microvolt = <3300000>;
+					regulator-boot-on;
+					regulator-always-on;
+					regulator-ramp-delay = <6250>;
+			};
+
+			/* use sw1c_reg to align with pfuze100/pfuze200 */
+			sw1c_reg: sw1b {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <2500000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1650000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vldo1 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen2_reg: vldo2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-always-on;
+			};
+
+			vgen3_reg: vccsd {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: v33 {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vldo3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vldo4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+
+	mag3110@e {
+		compatible = "fsl,mag3110";
+		reg = <0x0e>;
+		position = <2>;
+	};
+
+	fxls8471@1e {
+		compatible = "fsl,fxls8471";
+		reg = <0x1e>;
+		position = <0>;
+		interrupt-parent = <&gpio5>;
+		interrupts = <0 8>;
+	};
+};
+
+&i2c2 {
+	clock_frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+	imx6ul-evk {
+
+		pinctrl_enet1: enet1grp {
+			fsl,pins = <
+				MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
+				MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
+				MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
+				MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
+				MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
+				MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
+				MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
+				MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
+			>;
+		};
+
+		pinctrl_enet2: enet2grp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
+				MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
+				MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
+				MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
+				MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
+				MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
+				MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
+				MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
+				MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
+				MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
+			>;
+		};
+
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				MX6UL_PAD_UART1_RTS_B__GPIO1_IO19	0x17059 /* SD1 CD */
+				MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT	0x17059 /* SD1 VSELECT */
+				MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+				MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+			>;
+		};
+
+		pinctrl_i2c1_gpio: i2c1grp_gpio {
+			fsl,pins = <
+				MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
+				MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+				MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+			>;
+		};
+		
+		pinctrl_i2c2_gpio: i2c2grp_gpio {
+			fsl,pins = <
+				MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
+				MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
+			>;
+		};
+
+		pinctrl_lcdif_ctrl: lcdifctrlgrp {
+			fsl,pins = <
+				MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x79
+				MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
+				MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
+				MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
+			>;
+		};
+
+		pinctrl_lcdif_dat: lcdifdatgrp {
+			fsl,pins = <
+				MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
+				MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
+				MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
+				MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
+				MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
+				MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
+				MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
+				MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
+				MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
+				MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
+				MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
+				MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
+				MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
+				MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
+				MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
+				MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
+				MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
+				MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
+				MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
+				MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
+				MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
+				MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
+				MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
+				MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
+			>;
+		};
+
+		pinctrl_qspi: qspigrp {
+			fsl,pins = <
+				MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK      0x70a1
+				MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
+				MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01   0x70a1
+				MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02   0x70a1
+				MX6UL_PAD_NAND_CLE__QSPI_A_DATA03     0x70a1
+				MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B      0x70a1
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+				MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+			>;
+		};
+		
+		pinctrl_usb_otg1_id: usbotg1idgrp {
+			fsl,pins = <
+				MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
+				MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
+				MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+				MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+				MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+				MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
+				MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
+				MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+				MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+				MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+				MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+			>;
+		};
+
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
+			>;
+		};
+	};
+};
+
+&iomuxc_snvs {
+	pinctrl-names = "default_snvs";
+        pinctrl-0 = <&pinctrl_hog_2>;
+        imx6ull-evk {
+		pinctrl_hog_2: hoggrp-2 {
+                        fsl,pins = <
+                                MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00      0x80000000
+                        >;
+                };
+
+		pinctrl_dvfs: dvfsgrp {
+                        fsl,pins = <
+                                MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03      0x79
+                        >;
+                };
+
+		pinctrl_lcdif_reset: lcdifresetgrp {
+                        fsl,pins = <
+                                /* used for lcd reset */
+                                MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
+                        >;
+                };
+
+		pinctrl_spi4: spi4grp {
+                        fsl,pins = <
+                                MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10        0x70a1
+                                MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11        0x70a1
+                                MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x70a1
+                                MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x80000000
+                        >;
+                };
+        };
+};
+
+&lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif_dat
+		     &pinctrl_lcdif_ctrl
+		     &pinctrl_lcdif_reset>;
+	display = <&display0>;
+	status = "okay";
+
+	display0: display {
+		bits-per-pixel = <24>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+			clock-frequency = <9200000>;
+			hactive = <480>;
+			vactive = <272>;
+			hfront-porch = <8>;
+			hback-porch = <4>;
+			hsync-len = <41>;
+			vback-porch = <2>;
+			vfront-porch = <4>;
+			vsync-len = <10>;
+
+			hsync-active = <0>;
+			vsync-active = <0>;
+			de-active = <1>;
+			pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&qspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi>;
+	status = "okay";
+	ddrsmp=<0>;
+
+	flash0: n25q256a@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <0>;
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&usbotg1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb_otg1_id>;
+	dr_mode = "otg";
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usbotg2 {
+	dr_mode = "host";
+	disable-over-current;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sd1_vmmc>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	no-1-8-v;
+	non-removable;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+};
diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi
index f224e20bda9..c5d5a5ab7bd 100644
--- a/arch/arm/dts/imx6ull.dtsi
+++ b/arch/arm/dts/imx6ull.dtsi
@@ -36,10 +36,16 @@
 
 &usdhc1 {
 	compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
+	assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
+	assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+	assigned-clock-rates = <0>, <132000000>;
 };
 
 &usdhc2 {
 	compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
+	assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
+	assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+	assigned-clock-rates = <0>, <132000000>;
 };
 
 / {
@@ -60,6 +66,12 @@
 				clocks = <&clks IMX6ULL_CLK_DCP_CLK>;
 				clock-names = "dcp";
 			};
+			rngb: rng@2284000 {
+				compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb";
+				reg = <0x02284000 0x4000>;
+				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX6UL_CLK_DUMMY>;
+			};
 
 			iomuxc_snvs: iomuxc-snvs@2290000 {
 				compatible = "fsl,imx6ull-iomuxc-snvs";
@@ -76,6 +88,18 @@
 				clock-names = "ipg", "per";
 				status = "disabled";
 			};
+
+			epdc: epdc@228c000 {
+				compatible = "fsl,imx7d-epdc";
+				interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x228c000 0x4000>;
+				clocks = <&clks IMX6ULL_CLK_EPDC_ACLK>,
+					 <&clks IMX6ULL_CLK_EPDC_PIX>;
+				clock-names = "epdc_axi", "epdc_pix";
+				/* Need to fix epdc-ram */
+				/* epdc-ram = <&gpr 0x4 30>; */
+				status = "disabled";
+			};
 		};
 	};
 };
diff --git a/arch/arm/dts/imx6ulz-14x14-evk-emmc.dts b/arch/arm/dts/imx6ulz-14x14-evk-emmc.dts
new file mode 100644
index 00000000000..e477952759e
--- /dev/null
+++ b/arch/arm/dts/imx6ulz-14x14-evk-emmc.dts
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "imx6ulz-14x14-evk.dts"
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2_8bit>;
+	pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx6ulz-14x14-evk-gpmi-weim.dts b/arch/arm/dts/imx6ulz-14x14-evk-gpmi-weim.dts
new file mode 100644
index 00000000000..05c219cfc26
--- /dev/null
+++ b/arch/arm/dts/imx6ulz-14x14-evk-gpmi-weim.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2018 NXP
+
+#include "imx6ulz-14x14-evk.dts"
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "okay";
+	nand-on-flash-bbt;
+	fsl,use-minimum-ecc;
+};
+
+&iomuxc {
+	pinctrl_gpmi_nand_1: gpmi-nand-1 {
+		fsl,pins = <
+			MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
+			MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
+			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
+			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
+			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
+			MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B     0xb0b1
+			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
+			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
+			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
+			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
+			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
+			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
+			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
+			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
+			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
+			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
+		>;
+	};
+};
+
+&qspi {
+	status = "disabled";
+};
+
+&usdhc2 {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/imx6ulz-14x14-evk.dts b/arch/arm/dts/imx6ulz-14x14-evk.dts
index 483d9732c00..78e1db8e660 100644
--- a/arch/arm/dts/imx6ulz-14x14-evk.dts
+++ b/arch/arm/dts/imx6ulz-14x14-evk.dts
@@ -15,7 +15,7 @@
 /delete-node/ &tsc;
 
 / {
-	model = "Freescale i.MX6 ULZ 14x14 EVK Board";
+	model = "i.MX6 ULZ 14x14 EVK Board";
 	compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz";
 
 	/delete-node/ panel;
diff --git a/arch/arm/dts/imx7d-12x12-ddr3-val.dts b/arch/arm/dts/imx7d-12x12-ddr3-val.dts
new file mode 100644
index 00000000000..7081183acff
--- /dev/null
+++ b/arch/arm/dts/imx7d-12x12-ddr3-val.dts
@@ -0,0 +1,578 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx7d.dtsi"
+
+/ {
+	model = "i.MX7 DDR3 12x12 VAL Board";
+	compatible = "fsl,imx7d-12x12-ddr3-val", "fsl,imx7d";
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm1 0 5000000 0>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+		status = "okay";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_keys>;
+
+		volume-up {
+			label = "Volume Up";
+			gpios = <&gpio3 17 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEUP>;
+		};
+
+		volume-down {
+			label = "Volume Down";
+			gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEDOWN>;
+		};
+	};
+
+	pxp_v4l2_out {
+		compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
+		status = "okay";
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_sd3_vmmc: sd3_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "VCC_SD3";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio6 11 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg2_vbus: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "usb_otg2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_vref_1v8: regulator@2 {
+			compatible = "regulator-fixed";
+			regulator-name = "vref-1v8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		reg_can1_3v3: can1-3v3 {
+			compatible = "regulator-fixed";
+			regulator-name = "can1-3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+		};
+
+		reg_can2_3v3: can2-3v3 {
+			compatible = "regulator-fixed";
+			regulator-name = "can2-3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	memory {
+		reg = <0x80000000 0x80000000>;
+	};
+};
+
+&adc1 {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&sw1a_reg>;
+};
+
+&ecspi4 {
+	fsl,spi-num-chipselects = <4>;
+	cs-gpios = <&gpio5 3 0>, <&gpio5 4 0>, <&gpio5 5 0>, <&gpio5 6 0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>;
+	status = "disabled";
+
+	flash: m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p32";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&epxp {
+	status = "okay";
+};
+
+&flexcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	xceiver-supply = <&reg_can1_3v3>;
+	status = "disabled";
+};
+
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	xceiver-supply = <&reg_can2_3v3>;
+	status = "disabled";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1_1>;
+	pinctrl-1 = <&pinctrl_i2c1_1_gpio>;
+	scl-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pfuze3000@8 {
+		compatible = "fsl,pfuze3000";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1a {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+			/* use sw1c_reg to align with pfuze100/pfuze200 */
+			sw1c_reg: sw1b {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1850000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1650000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vldo1 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen2_reg: vldo2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vccsd {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: v33 {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vldo3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vldo4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3_1>;
+	pinctrl-1 = <&pinctrl_i2c3_1_gpio>;
+	scl-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	imx7d-12x12-ddr3-val {
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO14__GPIO1_IO14 	0x59
+				MX7D_PAD_GPIO1_IO15__GPIO1_IO15 	0x59
+				MX7D_PAD_SD2_RESET_B__GPIO5_IO11 	0x59
+			>;
+		};
+
+		pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 {
+			fsl,pins = <
+				MX7D_PAD_SD1_CLK__GPIO5_IO3 	0x2
+				MX7D_PAD_SD1_CMD__GPIO5_IO4 	0x2
+				MX7D_PAD_SD1_DATA0__GPIO5_IO5 	0x2
+				MX7D_PAD_SD1_DATA1__GPIO5_IO6 	0x2
+			>;
+		};
+
+		pinctrl_ecspi4_1: ecspi4grp-1 {
+			fsl,pins = <
+				MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK 	0x2
+				MX7D_PAD_SD1_WP__ECSPI4_MOSI 		0x2
+				MX7D_PAD_SD1_CD_B__ECSPI4_MISO 	 	0x2
+			>;
+		};
+
+		pinctrl_flexcan1: flexcan1grp {
+			fsl,pins = <
+				MX7D_PAD_SD3_DATA5__FLEXCAN1_TX 	0x59
+				MX7D_PAD_SD3_DATA7__FLEXCAN1_RX 	0x59
+			>;
+		};
+
+		pinctrl_flexcan2: flexcan2grp {
+			fsl,pins = <
+				MX7D_PAD_SD3_DATA6__FLEXCAN2_TX 	0x59
+				MX7D_PAD_SD3_DATA4__FLEXCAN2_RX 	0x59
+			>;
+		};
+
+		pinctrl_gpio_keys: gpio_keysgrp {
+			fsl,pins = <
+				MX7D_PAD_LCD_DATA12__GPIO3_IO17 0x32
+				MX7D_PAD_LCD_DATA13__GPIO3_IO18 0x32
+			>;
+		};
+
+		pinctrl_i2c3_1: i2c3grp-1 {
+			fsl,pins = <
+				MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x4000007f
+				MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x4000007f
+			>;
+		};
+
+		pinctrl_i2c3_1_gpio: i2c3grp-1-gpio {
+			fsl,pins = <
+				MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x7f
+				MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x7f
+			>;
+		};
+
+		pinctrl_i2c4_1: i2c4grp-1 {
+			fsl,pins = <
+				MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f
+				MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f
+			>;
+		};
+
+		pinctrl_lcdif_dat: lcdifdatgrp {
+			fsl,pins = <
+				MX7D_PAD_EPDC_DATA00__LCD_DATA0  0x4001b0b0
+				MX7D_PAD_EPDC_DATA01__LCD_DATA1  0x4001b0b0
+				MX7D_PAD_EPDC_DATA02__LCD_DATA2  0x4001b0b0
+				MX7D_PAD_EPDC_DATA03__LCD_DATA3  0x4001b0b0
+				MX7D_PAD_EPDC_DATA04__LCD_DATA4  0x4001b0b0
+				MX7D_PAD_EPDC_DATA05__LCD_DATA5  0x4001b0b0
+				MX7D_PAD_EPDC_DATA06__LCD_DATA6  0x4001b0b0
+				MX7D_PAD_EPDC_DATA07__LCD_DATA7  0x4001b0b0
+				MX7D_PAD_EPDC_DATA08__LCD_DATA8  0x4001b0b0
+				MX7D_PAD_EPDC_DATA09__LCD_DATA9  0x4001b0b0
+				MX7D_PAD_EPDC_DATA10__LCD_DATA10 0x4001b0b0
+				MX7D_PAD_EPDC_DATA11__LCD_DATA11 0x4001b0b0
+				MX7D_PAD_EPDC_DATA12__LCD_DATA12 0x4001b0b0
+				MX7D_PAD_EPDC_DATA13__LCD_DATA13 0x4001b0b0
+				MX7D_PAD_EPDC_DATA14__LCD_DATA14 0x4001b0b0
+				MX7D_PAD_EPDC_DATA15__LCD_DATA15 0x4001b0b0
+				MX7D_PAD_EPDC_SDLE__LCD_DATA16   0x4001b0b0
+				MX7D_PAD_EPDC_SDOE__LCD_DATA17   0x4001b0b0
+				MX7D_PAD_EPDC_SDSHR__LCD_DATA18  0x4001b0b0
+				MX7D_PAD_EPDC_SDCE0__LCD_DATA19  0x4001b0b0
+				MX7D_PAD_EPDC_SDCE1__LCD_DATA20  0x4001b0b0
+				MX7D_PAD_EPDC_SDCE2__LCD_DATA21  0x4001b0b0
+				MX7D_PAD_EPDC_SDCE3__LCD_DATA22  0x4001b0b0
+				MX7D_PAD_EPDC_GDCLK__LCD_DATA23  0x4001b0b0
+			>;
+		};
+
+		pinctrl_lcdif_ctrl: lcdifctrlgrp {
+			fsl,pins = <
+				MX7D_PAD_EPDC_SDCLK__LCD_CLK 		0x4001b0b0
+				MX7D_PAD_EPDC_BDR1__LCD_ENABLE 		0x4001b0b0
+				MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC 	0x4001b0b0
+				MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC 	0x4001b0b0
+			>;
+		};
+
+		pinctrl_pwm1: pwm1grp {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
+			>;
+		};
+
+		pinctrl_uart1_1: uart1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
+				MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
+			>;
+		};
+
+		pinctrl_usdhc2_1: usdhc2grp-1 {
+			fsl,pins = <
+				MX7D_PAD_SD2_CMD__SD2_CMD     	0x59
+				MX7D_PAD_SD2_CLK__SD2_CLK     	0x19
+				MX7D_PAD_SD2_DATA0__SD2_DATA0 	0x59
+				MX7D_PAD_SD2_DATA1__SD2_DATA1 	0x59
+				MX7D_PAD_SD2_DATA2__SD2_DATA2 	0x59
+				MX7D_PAD_SD2_DATA3__SD2_DATA3 	0x59
+				MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x59
+				MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x59
+				MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x59
+				MX7D_PAD_ECSPI1_SS0__SD2_DATA7 	0x59
+			>;
+		};
+
+		pinctrl_usdhc2_1_100mhz: usdhc2grp-1_100mhz {
+			fsl,pins = <
+				MX7D_PAD_SD2_CMD__SD2_CMD     	0x5a
+				MX7D_PAD_SD2_CLK__SD2_CLK     	0x1a
+				MX7D_PAD_SD2_DATA0__SD2_DATA0 	0x5a
+				MX7D_PAD_SD2_DATA1__SD2_DATA1 	0x5a
+				MX7D_PAD_SD2_DATA2__SD2_DATA2 	0x5a
+				MX7D_PAD_SD2_DATA3__SD2_DATA3 	0x5a
+				MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x5a
+				MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x5a
+				MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x5a
+				MX7D_PAD_ECSPI1_SS0__SD2_DATA7 	0x5a
+			>;
+		};
+
+		pinctrl_usdhc2_1_200mhz: usdhc2grp-1_200mhz {
+			fsl,pins = <
+				MX7D_PAD_SD2_CMD__SD2_CMD     	0x5b
+				MX7D_PAD_SD2_CLK__SD2_CLK     	0x1b
+				MX7D_PAD_SD2_DATA0__SD2_DATA0 	0x5b
+				MX7D_PAD_SD2_DATA1__SD2_DATA1 	0x5b
+				MX7D_PAD_SD2_DATA2__SD2_DATA2 	0x5b
+				MX7D_PAD_SD2_DATA3__SD2_DATA3 	0x5b
+				MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x5b
+				MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x5b
+				MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x5b
+				MX7D_PAD_ECSPI1_SS0__SD2_DATA7 	0x5b
+			>;
+		};
+
+		pinctrl_usdhc3_1: usdhc3grp-1 {
+			fsl,pins = <
+				MX7D_PAD_SD3_CMD__SD3_CMD	    0x59
+				MX7D_PAD_SD3_CLK__SD3_CLK	    0x19
+				MX7D_PAD_SD3_DATA0__SD3_DATA0   0x59
+				MX7D_PAD_SD3_DATA1__SD3_DATA1   0x59
+				MX7D_PAD_SD3_DATA2__SD3_DATA2   0x59
+				MX7D_PAD_SD3_DATA3__SD3_DATA3   0x59
+			>;
+		};
+	};
+};
+
+&iomuxc_lpsr {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_2>;
+
+	imx7d-12x12-ddr3-val {
+		pinctrl_hog_2: hoggrp-2 {
+			fsl,pins = <
+				MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2	0x59 /* flexcan stby1 */
+				MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3	0x59 /* flexcan stby2 */
+				MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT	0x80000000
+			>;
+		};
+
+		pinctrl_i2c1_1: i2c1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL	0x4000007f
+				MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA	0x4000007f
+			>;
+		};
+
+		pinctrl_i2c1_1_gpio: i2c1grp-1-gpio {
+			fsl,pins = <
+				MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 	0x7f
+				MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5   0x7f
+			>;
+		};
+
+		pinctrl_i2c2_1: i2c2grp-1 {
+			fsl,pins = <
+				MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL	0x4000007f
+				MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA	0x4000007f
+			>;
+		};
+	};
+};
+
+&lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif_dat
+		     &pinctrl_lcdif_ctrl>;
+	display = <&display0>;
+	status = "okay";
+
+	display0: display {
+		bits-per-pixel = <16>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+				clock-frequency = <33500000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <89>;
+				hfront-porch = <164>;
+				vback-porch = <23>;
+				vfront-porch = <10>;
+				hsync-len = <10>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&sdma {
+	status = "okay";
+};
+
+&pcie {
+	pinctrl-names = "default";
+	status = "disabled";
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_1>;
+	status = "okay";
+};
+
+&usbh {
+	status = "okay";
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usbotg2 {
+	vbus-supply = <&reg_usb_otg2_vbus>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2_1>;
+	pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>;
+	assigned-clocks = <&clks IMX7D_USDHC2_ROOT_CLK>;
+	assigned-clocks-rates = <400000000>;
+	bus-width = <8>;
+	tuning-step = <2>;
+	non-removable;
+	keep-power-in-suspend;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3_1>;
+	vmmc-supply = <&reg_sd3_vmmc>;
+	cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	no-1-8-v;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx7d-12x12-lpddr3-val-ecspi.dts b/arch/arm/dts/imx7d-12x12-lpddr3-val-ecspi.dts
new file mode 100644
index 00000000000..29abc2c86b3
--- /dev/null
+++ b/arch/arm/dts/imx7d-12x12-lpddr3-val-ecspi.dts
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx7d-12x12-lpddr3-val.dts"
+
+&epdc {
+        status = "disabled";
+};
+
+&ecspi1{
+        status = "okay";
+};
+
+/*
+ * pin conflict with ecspi1
+ * default hog setting conflicts with ECSPI1 MOSI and MISO
+ * EPDC PWRCTRL conflicts with ECSPI1 CS pin
+ */
+&iomuxc {
+	pinctrl-0 = <&pinctrl_hog_1>;
+	pinctrl-1 = <&pinctrl_hog_1>;
+};
diff --git a/arch/arm/dts/imx7d-12x12-lpddr3-val-qspi.dts b/arch/arm/dts/imx7d-12x12-lpddr3-val-qspi.dts
new file mode 100644
index 00000000000..5ceccd2ba0d
--- /dev/null
+++ b/arch/arm/dts/imx7d-12x12-lpddr3-val-qspi.dts
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx7d-12x12-lpddr3-val.dts"
+
+/* disable epdc, conflict with qspi */
+&epdc {
+        status = "disabled";
+};
+
+&iomuxc {
+	qspi1 {
+		pinctrl_qspi1_1: qspi1grp_1 {
+			fsl,pins = <
+				MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51
+				MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51
+				MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51
+				MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51
+				MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x51
+				MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51
+				MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51
+				MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x51
+				MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x51
+				MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x51
+				MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x51
+				MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x51
+				MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x51
+				MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x51
+				MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x51
+				MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x51
+			>;
+		};
+	};
+};
+
+&qspi1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_qspi1_1>;
+	pinctrl-1 = <&pinctrl_qspi1_1>;
+	status = "okay";
+	fsl,qspi-has-second-chip = <1>;
+	ddrsmp=<0>;
+
+	flash0: n25q256a@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <0>;
+	};
+
+	flash1: n25q256a@1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <1>;
+	};
+
+	flash2: n25q256a@2 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <2>;
+	};
+
+	flash3: n25q256a@3 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q256a", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <3>;
+	};
+};
diff --git a/arch/arm/dts/imx7d-12x12-lpddr3-val.dts b/arch/arm/dts/imx7d-12x12-lpddr3-val.dts
new file mode 100644
index 00000000000..4b6257c57c7
--- /dev/null
+++ b/arch/arm/dts/imx7d-12x12-lpddr3-val.dts
@@ -0,0 +1,1047 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx7d.dtsi"
+
+/ {
+	model = "i.MX7 LPDDR3 12x12 VAL Board";
+	compatible = "fsl,imx7d-12x12-lpddr3-val", "fsl,imx7d";
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm1 0 5000000 0>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+		status = "okay";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&pinctrl_gpio_keys>;
+		pinctrl-1 = <&pinctrl_gpio_keys_sleep>;
+
+		volume-up {
+			label = "Volume Up";
+			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEUP>;
+		};
+
+		volume-down {
+			label = "Volume Down";
+			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEDOWN>;
+		};
+	};
+
+	pxp_v4l2_out {
+		compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
+		status = "okay";
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_aud_1v8: aud_1v8 {
+			compatible = "regulator-fixed";
+			regulator-name = "AUD_1V8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_can1_3v3: can1-3v3 {
+			compatible = "regulator-fixed";
+			regulator-name = "can1-3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio1 10 GPIO_ACTIVE_LOW>;
+		};
+
+		reg_can2_3v3: can2-3v3 {
+			compatible = "regulator-fixed";
+			regulator-name = "can2-3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio1 11 GPIO_ACTIVE_LOW>;
+		};
+
+		reg_coedc_5v: coedc_5v {
+			compatible = "regulator-fixed";
+			regulator-name = "CODEC_5V";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_sd1_vmmc: sd1_vmmc{
+			compatible = "regulator-fixed";
+			regulator-name = "VCC_SD1";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_sd2_vmmc: sd2_vmmc{
+			compatible = "regulator-fixed";
+			regulator-name = "VCC_SD2";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg2_vbus: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "usb_otg2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_vref_1v8: regulator@2 {
+			compatible = "regulator-fixed";
+			regulator-name = "vref-1v8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on {
+			compatible = "regulator-fixed";
+			regulator-name = "mipi_dsi_pwr_on";
+			gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+                };
+	};
+
+	memory {
+		reg = <0x80000000 0x80000000>;
+	};
+};
+
+&adc1 {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&sw1a_reg>;
+};
+
+&epdc {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&pinctrl_epdc_0>;
+        pinctrl-1 = <&pinctrl_epdc_0>;
+        V3P3-supply = <&V3P3_reg>;
+        VCOM-supply = <&VCOM_reg>;
+        DISPLAY-supply = <&DISPLAY_reg>;
+        status = "okay";
+};
+
+&epxp {
+	status = "okay";
+};
+
+&ecspi1 {
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio4 19 0>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>;
+	pinctrl-1 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>;
+	status = "disabled";
+
+	spi_flash1: m25p80@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p32", "jedec,spi-nor";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_enet1>;
+	pinctrl-1 = <&pinctrl_enet1>;
+	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
+	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+	assigned-clock-rates = <0>, <100000000>;
+	phy-mode = "rgmii-txid";
+	phy-handle = <&ethphy1>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@5 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <5>;
+
+			vddio0: vddio-regulator {
+				regulator-name = "VDDIO";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+		};
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+
+			vddio1: vddio-regulator {
+				regulator-name = "VDDIO";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+			};
+		};
+	};
+};
+
+&fec2 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_enet2>;
+	pinctrl-1 = <&pinctrl_enet2>;
+	pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>;
+	assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
+			  <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
+	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+	assigned-clock-rates = <0>, <100000000>;
+	phy-mode = "rgmii-txid";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "disabled";
+};
+
+&flexcan1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	pinctrl-1 = <&pinctrl_flexcan1>;
+	xceiver-supply = <&reg_can1_3v3>;
+	status = "disabled";
+};
+
+&flexcan2 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	pinctrl-1 = <&pinctrl_flexcan2>;
+	xceiver-supply = <&reg_can2_3v3>;
+	status = "disabled";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "sleep", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1_1>;
+	pinctrl-1 = <&pinctrl_i2c1_1>;
+	pinctrl-2 = <&pinctrl_i2c1_1_gpio>;
+	scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pfuze3000@8 {
+		compatible = "fsl,pfuze3000";
+		reg = <0x08>;
+		fsl,lpsr-mode;
+
+		regulators {
+			sw1a_reg: sw1a {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+			/* use sw1c_reg to align with pfuze100/pfuze200 */
+			sw1c_reg: sw1b {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1850000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1650000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vldo1 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen2_reg: vldo2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vccsd {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: v33 {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vldo3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vldo4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "sleep", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3_1>;
+	pinctrl-1 = <&pinctrl_i2c3_1>;
+	pinctrl-2 = <&pinctrl_i2c3_1_gpio>;
+	scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	max7322: gpio@68 {
+		compatible = "maxim,max7322";
+		reg = <0x68>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	max17135@48 {
+		compatible = "maxim,max17135";
+		reg = <0x48>;
+		vneg_pwrup = <1>;
+		gvee_pwrup = <2>;
+		vpos_pwrup = <10>;
+		gvdd_pwrup = <12>;
+		gvdd_pwrdn = <1>;
+		vpos_pwrdn = <2>;
+		gvee_pwrdn = <8>;
+		vneg_pwrdn = <10>;
+		gpio_pmic_pwrgood = <&gpio2 31 0>;
+		gpio_pmic_vcom_ctrl = <&gpio4 14 0>;
+		gpio_pmic_wakeup = <&gpio4 23 0>;
+		gpio_pmic_v3p3 = <&gpio4 20 0>;
+		gpio_pmic_intr = <&gpio4 18 0>;
+
+		regulators {
+			DISPLAY_reg: DISPLAY {
+				regulator-name = "DISPLAY";
+			};
+
+			GVDD_reg: GVDD {
+				/* 20v */
+				regulator-name = "GVDD";
+			};
+
+			GVEE_reg: GVEE {
+				/* -22v */
+				regulator-name = "GVEE";
+			};
+
+			HVINN_reg: HVINN {
+				/* -22v */
+				regulator-name = "HVINN";
+			};
+
+			HVINP_reg: HVINP {
+				/* 20v */
+				regulator-name = "HVINP";
+			};
+
+			VCOM_reg: VCOM {
+				regulator-name = "VCOM";
+				/* Real max value: -500000 */
+				regulator-max-microvolt = <4325000>;
+				/* Real min value: -4325000 */
+				regulator-min-microvolt = <500000>;
+			};
+
+			VNEG_reg: VNEG {
+				/* -15v */
+				regulator-name = "VNEG";
+			};
+
+			VPOS_reg: VPOS {
+				/* 15v */
+				regulator-name = "VPOS";
+			};
+
+			V3P3_reg: V3P3 {
+				regulator-name = "V3P3";
+			};
+		};
+	};
+
+	codec: wm8958@1a {
+		compatible = "wlf,wm8958";
+		reg = <0x1a>;
+		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>,
+		         <&clks IMX7D_CLK_DUMMY>;
+		clock-names = "mclk1", "mclk2";
+
+		DBVDD1-supply = <&reg_aud_1v8>;
+		DBVDD2-supply = <&reg_aud_1v8>;
+		DBVDD3-supply = <&reg_aud_1v8>;
+		AVDD2-supply = <&reg_aud_1v8>;
+		CPVDD-supply = <&reg_aud_1v8>;
+		SPKVDD1-supply = <&reg_coedc_5v>;
+		SPKVDD2-supply = <&reg_coedc_5v>;
+		wlf,ldo1ena;
+		wlf,ldo2ena;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect &pinctrl_hog_mipi>;
+	pinctrl-1 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect &pinctrl_hog_mipi>;
+
+	imx7d-12x12-lpddr3-val {
+
+		pinctrl_bt: btgrp-1 {
+			fsl,pins = <
+				MX7D_PAD_ENET1_CRS__GPIO7_IO14    0x80000000  /* BT REG on */
+			>;
+		};
+
+		pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 {
+			fsl,pins = <
+				MX7D_PAD_ECSPI1_SS0__GPIO4_IO19     0x2
+			>;
+		};
+
+		pinctrl_ecspi1_1: ecspi1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO   0x2
+				MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI   0x2
+				MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK   0x2
+			>;
+		};
+
+		pinctrl_enet1: enet1grp {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO10__ENET1_MDIO			0x3
+				MX7D_PAD_GPIO1_IO11__ENET1_MDC			0x3
+				MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x1
+				MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x1
+				MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x1
+				MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x1
+				MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x1
+				MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x1
+				MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x1
+				MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x1
+				MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x1
+				MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x1
+				MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x1
+				MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x1
+			>;
+		};
+
+		pinctrl_enet2: enet2grp {
+			fsl,pins = <
+				MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC     0x1
+				MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0    0x1
+				MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1    0x1
+				MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2    0x1
+				MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3     0x1
+				MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL  0x1
+				MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC    0x1
+				MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0    0x1
+				MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1     0x1
+				MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2     0x1
+				MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3    0x1
+				MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
+			>;
+		};
+
+		pinctrl_epdc_0: epdcgrp-0 {
+			fsl,pins = <
+				MX7D_PAD_EPDC_DATA00__EPDC_DATA0  0x2
+				MX7D_PAD_EPDC_DATA01__EPDC_DATA1  0x2
+				MX7D_PAD_EPDC_DATA02__EPDC_DATA2  0x2
+				MX7D_PAD_EPDC_DATA03__EPDC_DATA3  0x2
+				MX7D_PAD_EPDC_DATA04__EPDC_DATA4  0x2
+				MX7D_PAD_EPDC_DATA05__EPDC_DATA5  0x2
+				MX7D_PAD_EPDC_DATA06__EPDC_DATA6  0x2
+				MX7D_PAD_EPDC_DATA07__EPDC_DATA7  0x2
+				MX7D_PAD_EPDC_DATA08__EPDC_DATA8  0x2
+				MX7D_PAD_EPDC_DATA09__EPDC_DATA9  0x2
+				MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2
+				MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2
+				MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2
+				MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2
+				MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2
+				MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2
+				MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK   0x2
+				MX7D_PAD_EPDC_SDLE__EPDC_SDLE     0x2
+				MX7D_PAD_EPDC_SDOE__EPDC_SDOE     0x2
+				MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR   0x2
+				MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0   0x2
+				MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1   0x2
+				MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2   0x2
+				MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3   0x2
+				MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK   0x2
+				MX7D_PAD_EPDC_GDOE__EPDC_GDOE     0x2
+				MX7D_PAD_EPDC_GDRL__EPDC_GDRL     0x2
+				MX7D_PAD_EPDC_GDSP__EPDC_GDSP     0x2
+				MX7D_PAD_EPDC_BDR0__EPDC_BDR0     0x2
+				MX7D_PAD_EPDC_BDR1__EPDC_BDR1     0x2
+				MX7D_PAD_ECSPI1_MISO__GPIO4_IO18  0x80000000  /* pwr int */
+			>;
+		};
+
+		pinctrl_flexcan1: flexcan1grp {
+			fsl,pins = <
+				MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX	0x59
+				MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX	0x59
+				MX7D_PAD_GPIO1_IO10__GPIO1_IO10		0x59 /* STBY */
+			>;
+		};
+
+		pinctrl_flexcan2: flexcan2grp {
+			fsl,pins = <
+				MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX	0x59
+				MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX	0x59
+				MX7D_PAD_GPIO1_IO11__GPIO1_IO11		0x59  /* STBY */
+			>;
+		};
+
+		pinctrl_gpio_keys: gpio_keysgrp {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32
+				MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32
+			>;
+		};
+
+		pinctrl_gpio_keys_sleep: gpio_keysgrp_sleep {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14
+				MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14
+			>;
+		};
+
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C4_SCL__GPIO4_IO14	0x80000000
+				MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000
+				MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20  0x80000000
+				MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21  0x80000000
+				MX7D_PAD_ECSPI2_MISO__GPIO4_IO22  0x80000000
+				MX7D_PAD_ECSPI2_SS0__GPIO4_IO23	  0x80000000
+				MX7D_PAD_SD1_RESET_B__GPIO5_IO2   0x59
+				MX7D_PAD_SD1_CD_B__GPIO5_IO0      0x59
+				MX7D_PAD_SD1_WP__GPIO5_IO1        0x59
+				MX7D_PAD_SD2_CD_B__GPIO5_IO9      0x59
+				MX7D_PAD_SD2_WP__GPIO5_IO10       0x59
+				MX7D_PAD_SD2_RESET_B__GPIO5_IO11  0x59
+				MX7D_PAD_GPIO1_IO13__GPIO1_IO13   0x59
+			>;
+		};
+
+		pinctrl_hog_mipi: hoggrp_mipi {
+			fsl,pins = <
+                                MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16  0x59
+                                MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17  0x59
+			>;
+		};
+
+		pinctrl_hog_sd2_vselect: hoggrp_sd2vselect {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO12__SD2_VSELECT  0x59
+			>;
+		};
+
+		pinctrl_hog_headphone_det: hoggrp_headphone_det {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO12__GPIO1_IO12	  0x59
+			>;
+		};
+
+		pinctrl_i2c1_1: i2c1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C1_SDA__I2C1_SDA          0x4000007f
+				MX7D_PAD_I2C1_SCL__I2C1_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_i2c1_1_gpio: i2c1grp-1-gpio {
+			fsl,pins = <
+				MX7D_PAD_I2C1_SDA__GPIO4_IO9          0x7f
+				MX7D_PAD_I2C1_SCL__GPIO4_IO8          0x7f
+			>;
+		};
+
+		pinctrl_i2c2_1: i2c2grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C2_SDA__I2C2_SDA          0x4000007f
+				MX7D_PAD_I2C2_SCL__I2C2_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_i2c3_1: i2c3grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C3_SDA__I2C3_SDA	     0x4000007f
+				MX7D_PAD_I2C3_SCL__I2C3_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_i2c3_1_gpio: i2c3grp-1-gpio {
+			fsl,pins = <
+				MX7D_PAD_I2C3_SDA__GPIO4_IO13          0x7f
+				MX7D_PAD_I2C3_SCL__GPIO4_IO12          0x7f
+			>;
+		};
+
+		pinctrl_i2c4_1: i2c4grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C4_SDA__I2C4_SDA          0x4000007f
+				MX7D_PAD_I2C4_SCL__I2C4_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_lcdif_dat: lcdifdatgrp {
+			fsl,pins = <
+				MX7D_PAD_LCD_DATA00__LCD_DATA0  0x79
+				MX7D_PAD_LCD_DATA01__LCD_DATA1  0x79
+				MX7D_PAD_LCD_DATA02__LCD_DATA2  0x79
+				MX7D_PAD_LCD_DATA03__LCD_DATA3  0x79
+				MX7D_PAD_LCD_DATA04__LCD_DATA4  0x79
+				MX7D_PAD_LCD_DATA05__LCD_DATA5  0x79
+				MX7D_PAD_LCD_DATA06__LCD_DATA6  0x79
+				MX7D_PAD_LCD_DATA07__LCD_DATA7  0x79
+				MX7D_PAD_LCD_DATA08__LCD_DATA8  0x79
+				MX7D_PAD_LCD_DATA09__LCD_DATA9  0x79
+				MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
+				MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
+				MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
+				MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
+				MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
+				MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
+				MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
+				MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
+				MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79
+				MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79
+				MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79
+				MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79
+				MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79
+				MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79
+			>;
+		};
+
+		pinctrl_lcdif_ctrl: lcdifctrlgrp {
+			fsl,pins = <
+				MX7D_PAD_LCD_CLK__LCD_CLK       0x79
+				MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
+				MX7D_PAD_LCD_VSYNC__LCD_VSYNC   0x79
+				MX7D_PAD_LCD_HSYNC__LCD_HSYNC   0x79
+			>;
+		};
+
+		pinctrl_mqs: mqsgrp {
+			fsl,pins = <
+				MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT     0x0
+				MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT      0x0
+			>;
+		};
+
+		pinctrl_pcie: pciegrp {
+			fsl,pins = <
+				MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19	0x2
+				MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21	0x2
+			>;
+		};
+
+		pinctrl_sai1: sai1grp {
+			fsl,pins = <
+				MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
+				MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK     0x1f
+				MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC     0x1f
+				MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC     0x1f
+				MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0    0x1f
+				MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0    0
+			>;
+		};
+
+		pinctrl_sai2: sai2grp {
+			fsl,pins = <
+				MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK     0x1f
+				MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC     0x1f
+				MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0    0x1f
+				MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0    0
+			>;
+		};
+
+		pinctrl_uart1_1: uart1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
+				MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
+			>;
+		};
+
+		pinctrl_uart3_1: uart3grp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX    0x79
+				MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX    0x79
+				MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS     0x79
+				MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS     0x79
+			>;
+		};
+
+		pinctrl_uart3dte_1: uart3dtegrp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX    0x79
+				MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX    0x79
+				MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS     0x79
+				MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS     0x79
+			>;
+		};
+
+		pinctrl_usdhc1_1: usdhc1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_SD1_CMD__SD1_CMD	0x59
+				MX7D_PAD_SD1_CLK__SD1_CLK	0x19
+				MX7D_PAD_SD1_DATA0__SD1_DATA0	0x59
+				MX7D_PAD_SD1_DATA1__SD1_DATA1	0x59
+				MX7D_PAD_SD1_DATA2__SD1_DATA2	0x59
+				MX7D_PAD_SD1_DATA3__SD1_DATA3	0x59
+			>;
+		};
+
+		pinctrl_usdhc2_1: usdhc2grp-1 {
+			fsl,pins = <
+				MX7D_PAD_SD2_CMD__SD2_CMD	0x59
+				MX7D_PAD_SD2_CLK__SD2_CLK	0x19
+				MX7D_PAD_SD2_DATA0__SD2_DATA0	0x59
+				MX7D_PAD_SD2_DATA1__SD2_DATA1	0x59
+				MX7D_PAD_SD2_DATA2__SD2_DATA2	0x59
+				MX7D_PAD_SD2_DATA3__SD2_DATA3	0x59
+			>;
+		};
+
+		pinctrl_usdhc2_1_100mhz: usdhc2grp-1_100mhz {
+			fsl,pins = <
+				MX7D_PAD_SD2_CMD__SD2_CMD	0x5a
+				MX7D_PAD_SD2_CLK__SD2_CLK	0x1a
+				MX7D_PAD_SD2_DATA0__SD2_DATA0	0x5a
+				MX7D_PAD_SD2_DATA1__SD2_DATA1	0x5a
+				MX7D_PAD_SD2_DATA2__SD2_DATA2	0x5a
+				MX7D_PAD_SD2_DATA3__SD2_DATA3	0x5a
+			>;
+		};
+
+		pinctrl_usdhc2_1_200mhz: usdhc2grp-1_200mhz {
+			fsl,pins = <
+				MX7D_PAD_SD2_CMD__SD2_CMD	0x5b
+				MX7D_PAD_SD2_CLK__SD2_CLK	0x1b
+				MX7D_PAD_SD2_DATA0__SD2_DATA0	0x5b
+				MX7D_PAD_SD2_DATA1__SD2_DATA1	0x5b
+				MX7D_PAD_SD2_DATA2__SD2_DATA2	0x5b
+				MX7D_PAD_SD2_DATA3__SD2_DATA3	0x5b
+			>;
+		};
+
+		pinctrl_usdhc3_1: usdhc3grp-1 {
+			fsl,pins = <
+				MX7D_PAD_SD3_CMD__SD3_CMD	0x59
+				MX7D_PAD_SD3_CLK__SD3_CLK	0x19
+				MX7D_PAD_SD3_DATA0__SD3_DATA0	0x59
+				MX7D_PAD_SD3_DATA1__SD3_DATA1	0x59
+				MX7D_PAD_SD3_DATA2__SD3_DATA2	0x59
+				MX7D_PAD_SD3_DATA3__SD3_DATA3	0x59
+				MX7D_PAD_SD3_DATA4__SD3_DATA4	0x59
+				MX7D_PAD_SD3_DATA5__SD3_DATA5	0x59
+				MX7D_PAD_SD3_DATA6__SD3_DATA6	0x59
+				MX7D_PAD_SD3_DATA7__SD3_DATA7	0x59
+				MX7D_PAD_SD3_STROBE__SD3_STROBE	0x19
+			>;
+		};
+
+		pinctrl_usdhc3_1_100mhz: usdhc3grp-1_100mhz {
+			fsl,pins = <
+				MX7D_PAD_SD3_CMD__SD3_CMD	0x5a
+				MX7D_PAD_SD3_CLK__SD3_CLK	0x1a
+				MX7D_PAD_SD3_DATA0__SD3_DATA0	0x5a
+				MX7D_PAD_SD3_DATA1__SD3_DATA1	0x5a
+				MX7D_PAD_SD3_DATA2__SD3_DATA2	0x5a
+				MX7D_PAD_SD3_DATA3__SD3_DATA3	0x5a
+				MX7D_PAD_SD3_DATA4__SD3_DATA4	0x5a
+				MX7D_PAD_SD3_DATA5__SD3_DATA5	0x5a
+				MX7D_PAD_SD3_DATA6__SD3_DATA6	0x5a
+				MX7D_PAD_SD3_DATA7__SD3_DATA7	0x5a
+				MX7D_PAD_SD3_STROBE__SD3_STROBE	0x1a
+			>;
+		};
+
+		pinctrl_usdhc3_1_200mhz: usdhc3grp-1_200mhz {
+			fsl,pins = <
+				MX7D_PAD_SD3_CMD__SD3_CMD	0x5b
+				MX7D_PAD_SD3_CLK__SD3_CLK	0x1b
+				MX7D_PAD_SD3_DATA0__SD3_DATA0	0x5b
+				MX7D_PAD_SD3_DATA1__SD3_DATA1	0x5b
+				MX7D_PAD_SD3_DATA2__SD3_DATA2	0x5b
+				MX7D_PAD_SD3_DATA3__SD3_DATA3	0x5b
+				MX7D_PAD_SD3_DATA4__SD3_DATA4	0x5b
+				MX7D_PAD_SD3_DATA5__SD3_DATA5	0x5b
+				MX7D_PAD_SD3_DATA6__SD3_DATA6	0x5b
+				MX7D_PAD_SD3_DATA7__SD3_DATA7	0x5b
+				MX7D_PAD_SD3_STROBE__SD3_STROBE	0x1b
+			>;
+		};
+
+		pinctrl_sim1_1: sim1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B         0x77
+				MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD            0x77
+				MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN          0x77
+				MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK           0x73
+				MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD          0x73
+			>;
+		};
+
+	};
+};
+
+&iomuxc_lpsr {
+	imx7d-12x12-lpddr3-val {
+		pinctrl_pwm1: pwm1grp {
+			fsl,pins = <
+				MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT	0x30
+			>;
+		};
+
+		pinctrl_usbotg1_vbus: usbotg1vbusgrp {
+			fsl,pins = <
+				MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 	  0x14
+			>;
+		};
+
+		pinctrl_usbotg2_vbus: usbotg2vbusgrp {
+			fsl,pins = <
+				MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7    0x14
+			>;
+		};
+
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
+			>;
+		};
+	};
+};
+
+&lcdif {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_lcdif_dat
+		     &pinctrl_lcdif_ctrl>;
+	pinctrl-1 = <&pinctrl_lcdif_dat
+		     &pinctrl_lcdif_ctrl>;
+	display = <&display0>;
+	status = "okay";
+
+	display0: display {
+		bits-per-pixel = <16>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+				clock-frequency = <33500000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <89>;
+				hfront-porch = <164>;
+				vback-porch = <23>;
+				vfront-porch = <10>;
+				hsync-len = <10>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&ocrams {
+	fsl,enable-lpsr;
+};
+
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+	reset-gpio = <&gpio6 21 GPIO_ACTIVE_LOW>;
+	power-on-gpio = <&gpio6 19 GPIO_ACTIVE_HIGH>;
+	status = "disabled";
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm1>;
+	status = "okay";
+};
+
+&sim1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_sim1_1>;
+	pinctrl-1 = <&pinctrl_sim1_1>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_uart1_1>;
+	pinctrl-1 = <&pinctrl_uart1_1>;
+	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_uart3_1
+		     &pinctrl_bt>;
+	pinctrl-1 = <&pinctrl_uart3_1
+		     &pinctrl_bt>;
+	fsl,uart-has-rtscts;
+	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+	status = "okay";
+	/* for DTE mode, add below change */
+	/* fsl,dte-mode;*/
+	/* pinctrl-0 = <&pinctrl_uart3dte_1>; */
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg1_vbus>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usbotg2 {
+	vbus-supply = <&reg_usb_otg2_vbus>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg2_vbus>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc1_1>;
+	pinctrl-1 = <&pinctrl_usdhc1_1>;
+	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+	no-1-8-v;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sd1_vmmc>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc2_1>;
+	pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>;
+	pinctrl-3 = <&pinctrl_usdhc2_1>;
+	cd-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sd2_vmmc>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc3_1>;
+	pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
+	pinctrl-3 = <&pinctrl_usdhc3_1>;
+	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
+	assigned-clock-rates = <400000000>;
+	bus-width = <8>;
+	non-removable;
+	keep-power-in-suspend;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+};
diff --git a/arch/arm/dts/imx7d-19x19-ddr3-val.dts b/arch/arm/dts/imx7d-19x19-ddr3-val.dts
new file mode 100644
index 00000000000..47cfaa0ddb2
--- /dev/null
+++ b/arch/arm/dts/imx7d-19x19-ddr3-val.dts
@@ -0,0 +1,882 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx7d.dtsi"
+
+/ {
+	model = "i.MX7 DDR3L 19x19 VAL Board";
+	compatible = "fsl,imx7d-19x19-ddr3-val", "fsl,imx7d";
+
+	max7322_reset: max7322-reset {
+		compatible = "gpio-reset";
+		reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <1>;
+		#reset-cells = <0>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_keys>;
+		/* gpios disconnected see resistors R601, R583 */
+		status = "disabled";
+
+		volume-up {
+			label = "Volume Up";
+			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEUP>;
+		};
+
+		volume-down {
+			label = "Volume Down";
+			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEDOWN>;
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_lcd_reset: lcd-reset {
+			compatible = "regulator-fixed";
+			regulator-name = "lcd-reset";
+			gpio = <&gpio3 4 0>;
+			enable-active-high;
+		};
+
+		reg_sd2_vmmc: sd2_vmmc{
+			compatible = "regulator-fixed";
+			regulator-name = "VCC_SD2";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_sd3_vmmc: sd3_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "VCC_SD3";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio6 11 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg2_vbus: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "usb_otg2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_vref_1v8: regulator@2 {
+			compatible = "regulator-fixed";
+			regulator-name = "vref-1v8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		reg_coedc_5v: coedc_5v {
+			compatible = "regulator-fixed";
+			regulator-name = "CODEC_5V";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_aud_3v3: aud_3v3 {
+			compatible = "regulator-fixed";
+			regulator-name = "AUD_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_aud_1v8: aud_1v8 {
+			compatible = "regulator-fixed";
+			regulator-name = "AUD_1V8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+	};
+
+	pxp_v4l2_out {
+		compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
+		status = "okay";
+	};
+
+	memory {
+		reg = <0x80000000 0x80000000>;
+	};
+};
+
+&adc1 {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
+
+&adc2 {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&sw1a_reg>;
+};
+
+&ecspi1 {
+	    fsl,spi-num-chipselects = <1>;
+		cs-gpios = <&gpio4 19 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>;
+		status = "okay";
+
+	    flash: at45@0 {
+	        #address-cells = <1>;
+	        #size-cells = <1>;
+	        compatible = "atmel,at45", "jedec,spi-nor";
+	        spi-max-frequency = <20000000>;
+	        reg = <0>;
+	    };
+};
+
+&epxp {
+        status = "okay";
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>;
+	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
+	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+	assigned-clock-rates = <0>, <100000000>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy1>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+
+		ethphy1: ethernet-phy@5 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <5>;
+		};
+	};
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2>;
+	pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>;
+	assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
+			  <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
+	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+	assigned-clock-rates = <0>, <100000000>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1_1>;
+	pinctrl-1 = <&pinctrl_i2c1_1_gpio>;
+	scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pfuze3000@8 {
+		compatible = "fsl,pfuze3000";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1a {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+			/* use sw1c_reg to align with pfuze100/pfuze200 */
+			sw1c_reg: sw1b {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1850000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1650000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vldo1 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen2_reg: vldo2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vccsd {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: v33 {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vldo3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vldo4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2_1>;
+	pinctrl-1 = <&pinctrl_i2c2_1_gpio>;
+	scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3_1>;
+	pinctrl-1 = <&pinctrl_i2c3_1_gpio>;
+	scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	max7322: gpio@68 {
+		compatible = "maxim,max7322";
+		reg = <0x68>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		resets = <&max7322_reset>;
+	};
+	codec: wm8958@1a {
+		compatible = "wlf,wm8958";
+		reg = <0x1a>;
+		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>,
+		       <&clks IMX7D_CLK_DUMMY>;
+		clock-names = "mclk1", "mclk2";
+
+		DBVDD1-supply = <&reg_aud_1v8>;
+		DBVDD2-supply = <&reg_aud_1v8>;
+		DBVDD3-supply = <&reg_aud_3v3>;
+		AVDD2-supply = <&reg_aud_1v8>;
+		CPVDD-supply = <&reg_aud_1v8>;
+		SPKVDD1-supply = <&reg_coedc_5v>;
+		SPKVDD2-supply = <&reg_coedc_5v>;
+
+		wlf,ldo1ena;
+		wlf,ldo2ena;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_sd3_vselect>;
+
+	imx7d-19x19-ddr3-val {
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO12__SD2_VSELECT   0x59
+				MX7D_PAD_SD2_CD_B__GPIO5_IO9       0x59
+				MX7D_PAD_SD2_WP__GPIO5_IO10        0x59
+				MX7D_PAD_SD2_RESET_B__GPIO5_IO11   0x59
+				MX7D_PAD_SD3_RESET_B__GPIO6_IO11   0x59
+				MX7D_PAD_GPIO1_IO14__GPIO1_IO14    0x59
+				MX7D_PAD_GPIO1_IO15__GPIO1_IO15    0x59
+				MX7D_PAD_SD3_STROBE__GPIO6_IO10    0x59
+
+				MX7D_PAD_I2C4_SCL__GPIO4_IO14	  0x7F
+				MX7D_PAD_I2C4_SDA__GPIO4_IO15     0x7F
+			>;
+		};
+
+		pinctrl_hog_sd3_vselect: hoggrp_sd3vselect {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO13__SD3_VSELECT   0x59
+			>;
+		};
+
+		pinctrl_csi: csigrp-1 {
+			fsl,pins = <
+				MX7D_PAD_LCD_DATA04__CSI_VSYNC 	0x0F
+				MX7D_PAD_LCD_DATA05__CSI_HSYNC 	0x0F
+				MX7D_PAD_LCD_DATA06__CSI_PIXCLK 0x0F
+				MX7D_PAD_LCD_DATA07__CSI_MCLK 	0x0F
+				MX7D_PAD_LCD_DATA08__CSI_DATA9 	0x0F
+				MX7D_PAD_LCD_DATA09__CSI_DATA8 	0x0F
+				MX7D_PAD_LCD_DATA10__CSI_DATA7 	0x0F
+				MX7D_PAD_LCD_DATA11__CSI_DATA6 	0x0F
+				MX7D_PAD_LCD_DATA12__CSI_DATA5 	0x0F
+				MX7D_PAD_LCD_DATA13__CSI_DATA4 	0x0F
+				MX7D_PAD_LCD_DATA14__CSI_DATA3 	0x0F
+				MX7D_PAD_LCD_DATA15__CSI_DATA2 	0x0F
+				MX7D_PAD_LCD_DATA02__GPIO3_IO7 	0x0F
+				MX7D_PAD_LCD_DATA03__GPIO3_IO8 	0x0F
+			>;
+		};
+
+		pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 {
+			fsl,pins = <
+				MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 	0x2
+			>;
+		};
+
+		pinctrl_ecspi1_1: ecspi1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 	0x2
+				MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 	0x2
+				MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 	0x2
+			>;
+		};
+
+		pinctrl_enet1: enet1grp {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
+				MX7D_PAD_GPIO1_IO11__ENET1_MDC  0x3
+				MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
+				MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
+				MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
+				MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
+				MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
+				MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
+				MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
+				MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
+				MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
+				MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
+				MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
+				MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
+			>;
+		};
+
+		pinctrl_enet2: enet2grp {
+			fsl,pins = <
+				MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC	0x1
+				MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0	0x1
+				MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1	0x1
+				MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2	0x1
+				MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3	0x1
+				MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL	0x1
+				MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC	0x1
+				MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0	0x1
+				MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1	0x1
+				MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2	0x1
+				MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3	0x1
+				MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL	0x1
+			>;
+		};
+
+		pinctrl_gpio_keys: gpio_keysgrp {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32
+				MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32
+			>;
+		};
+
+		pinctrl_i2c1_1: i2c1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C1_SDA__I2C1_SDA          0x4000007f
+				MX7D_PAD_I2C1_SCL__I2C1_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_i2c1_1_gpio: i2c1grp-1-gpio {
+			fsl,pins = <
+				MX7D_PAD_I2C1_SDA__GPIO4_IO9          0x7f
+				MX7D_PAD_I2C1_SCL__GPIO4_IO8          0x7f
+			>;
+		};
+
+		pinctrl_i2c2_1: i2c2grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C2_SDA__I2C2_SDA          0x4000007f
+				MX7D_PAD_I2C2_SCL__I2C2_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_i2c2_1_gpio: i2c2grp-1-gpio {
+			fsl,pins = <
+				MX7D_PAD_I2C2_SDA__GPIO4_IO11          0x7f
+				MX7D_PAD_I2C2_SCL__GPIO4_IO10          0x7f
+			>;
+		};
+
+		pinctrl_i2c3_1: i2c3grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C3_SDA__I2C3_SDA	     0x4000007f
+				MX7D_PAD_I2C3_SCL__I2C3_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_i2c3_1_gpio: i2c3grp-1-gpio {
+			fsl,pins = <
+				MX7D_PAD_I2C3_SDA__GPIO4_IO13          0x7f
+				MX7D_PAD_I2C3_SCL__GPIO4_IO12          0x7f
+			>;
+		};
+
+		pinctrl_i2c4_1: i2c4grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C4_SDA__I2C4_SDA          0x4000007f
+				MX7D_PAD_I2C4_SCL__I2C4_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_lcdif_dat: lcdifdatgrp {
+			fsl,pins = <
+				MX7D_PAD_LCD_DATA00__LCD_DATA0	0x79
+				MX7D_PAD_LCD_DATA01__LCD_DATA1	0x79
+				MX7D_PAD_LCD_DATA02__LCD_DATA2	0x79
+				MX7D_PAD_LCD_DATA03__LCD_DATA3	0x79
+				MX7D_PAD_LCD_DATA04__LCD_DATA4	0x79
+				MX7D_PAD_LCD_DATA05__LCD_DATA5	0x79
+				MX7D_PAD_LCD_DATA06__LCD_DATA6	0x79
+				MX7D_PAD_LCD_DATA07__LCD_DATA7	0x79
+				MX7D_PAD_LCD_DATA08__LCD_DATA8	0x79
+				MX7D_PAD_LCD_DATA09__LCD_DATA9	0x79
+				MX7D_PAD_LCD_DATA10__LCD_DATA10	0x79
+				MX7D_PAD_LCD_DATA11__LCD_DATA11	0x79
+				MX7D_PAD_LCD_DATA12__LCD_DATA12	0x79
+				MX7D_PAD_LCD_DATA13__LCD_DATA13	0x79
+				MX7D_PAD_LCD_DATA14__LCD_DATA14	0x79
+				MX7D_PAD_LCD_DATA15__LCD_DATA15	0x79
+				MX7D_PAD_LCD_DATA16__LCD_DATA16	0x79
+				MX7D_PAD_LCD_DATA17__LCD_DATA17	0x79
+				MX7D_PAD_LCD_DATA18__LCD_DATA18	0x79
+				MX7D_PAD_LCD_DATA19__LCD_DATA19	0x79
+				MX7D_PAD_LCD_DATA20__LCD_DATA20	0x79
+				MX7D_PAD_LCD_DATA21__LCD_DATA21	0x79
+				MX7D_PAD_LCD_DATA22__LCD_DATA22	0x79
+				MX7D_PAD_LCD_DATA23__LCD_DATA23	0x79
+			>;
+		};
+
+		pinctrl_lcdif_ctrl: lcdifctrlgrp {
+			fsl,pins = <
+				MX7D_PAD_LCD_CLK__LCD_CLK	0x79
+				MX7D_PAD_LCD_ENABLE__LCD_ENABLE	0x79
+				MX7D_PAD_LCD_VSYNC__LCD_VSYNC	0x79
+				MX7D_PAD_LCD_HSYNC__LCD_HSYNC	0x79
+			>;
+		};
+
+		pinctrl_sai1: sai1grp {
+			fsl,pins = <
+				MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
+				MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK     0x1f
+				MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC     0x1f
+				MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC     0x1f
+				MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0    0x1f
+				MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0    0
+			>;
+		};
+
+		pinctrl_sai2: sai2grp {
+			fsl,pins = <
+				MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
+				MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK     0x1f
+				MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC     0x1f
+				MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0    0x1f
+				MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0    0
+				MX7D_PAD_GPIO1_IO13__GPIO1_IO13		0x59
+			>;
+		};
+
+		pinctrl_uart1_1: uart1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
+				MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
+			>;
+		};
+
+		pinctrl_uart3_1: uart3grp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX	0x79
+				MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX	0x79
+				MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS	0x79
+				MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS	0x79
+			>;
+		};
+
+		pinctrl_uart3dte_1: uart3dtegrp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX	0x79
+				MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX	0x79
+				MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS	0x79
+				MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS	0x79
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX7D_PAD_SD1_CMD__SD1_CMD       0x59
+				MX7D_PAD_SD1_CLK__SD1_CLK       0x19
+				MX7D_PAD_SD1_DATA0__SD1_DATA0   0x59
+				MX7D_PAD_SD1_DATA1__SD1_DATA1   0x59
+				MX7D_PAD_SD1_DATA2__SD1_DATA2   0x59
+				MX7D_PAD_SD1_DATA3__SD1_DATA3   0x59
+				MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 0x59
+				MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 0x59
+				MX7D_PAD_ECSPI2_MISO__SD1_DATA6 0x59
+				MX7D_PAD_ECSPI2_SS0__SD1_DATA7  0x59
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX7D_PAD_SD2_CMD__SD2_CMD     0x59
+				MX7D_PAD_SD2_CLK__SD2_CLK     0x19
+				MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
+				MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
+				MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
+				MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
+			fsl,pins = <
+				MX7D_PAD_SD2_CMD__SD2_CMD     0x5a
+				MX7D_PAD_SD2_CLK__SD2_CLK     0x1a
+				MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
+				MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
+				MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
+				MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
+			fsl,pins = <
+				MX7D_PAD_SD2_CMD__SD2_CMD     0x5b
+				MX7D_PAD_SD2_CLK__SD2_CLK     0x1b
+				MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
+				MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
+				MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
+				MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX7D_PAD_SD3_CMD__SD3_CMD     0x59
+				MX7D_PAD_SD3_CLK__SD3_CLK     0x19
+				MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
+				MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
+				MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
+				MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
+				MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
+				MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
+				MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
+				MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
+			>;
+		};
+
+		pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+			fsl,pins = <
+				MX7D_PAD_SD3_CMD__SD3_CMD     0x5a
+				MX7D_PAD_SD3_CLK__SD3_CLK     0x1a
+				MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
+				MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
+				MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
+				MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
+				MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
+				MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
+				MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
+				MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
+			>;
+		};
+
+		pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+			fsl,pins = <
+				MX7D_PAD_SD3_CMD__SD3_CMD     0x5b
+				MX7D_PAD_SD3_CLK__SD3_CLK     0x1b
+				MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
+				MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
+				MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
+				MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
+				MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
+				MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
+				MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
+				MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
+			>;
+		};
+		
+		pinctrl_qspi1_1: qspi1grp_1 {
+			fsl,pins = <
+				MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51
+				MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51
+				MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51
+				MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51
+				MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x51
+				MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51
+				MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51
+				MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x51
+				MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x51
+				MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x51
+				MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x51
+				MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x51
+				MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x51
+				MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x51
+				MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x51
+				MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x51
+			>;
+		};
+	};
+};
+
+&iomuxc_lpsr {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_2>;
+
+	imx7d-19x19-ddr3-val {
+		pinctrl_hog_2: hoggrp-2 {
+			fsl,pins = <
+				MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x80000000
+				MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x80000000
+			>;
+		};
+
+		pinctrl_mipi_csi: mipicsigrp-1 {
+			fsl,pins = <
+				MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x3
+			>;
+		};
+	};
+};
+
+&lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif_dat
+		     &pinctrl_lcdif_ctrl>;
+	display = <&display0>;
+	status = "okay";
+
+	display0: display {
+		bits-per-pixel = <16>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+				clock-frequency = <33500000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <89>;
+				hfront-porch = <164>;
+				vback-porch = <23>;
+				vfront-porch = <10>;
+				hsync-len = <10>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&sai1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai1>;
+	status = "disabled";
+};
+
+&sai2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai2>;
+	status = "disabled";
+};
+
+&sdma {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_1>;
+	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3_1>;
+	fsl,uart-has-rtscts;
+	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+	status = "okay";
+	/* for DTE mode, add below change */
+	/* fsl,dte-mode;*/
+	pinctrl-0 = <&pinctrl_uart3dte_1>;
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+	cd-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	tuning-step = <2>;
+	vmmc-supply = <&reg_sd2_vmmc>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	tuning-step = <2>;
+	vmmc-supply = <&reg_sd3_vmmc>;
+	status = "okay";
+};
+
+&qspi1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_qspi1_1>;
+	pinctrl-1 = <&pinctrl_qspi1_1>;
+	status = "okay";
+	fsl,qspi-has-second-chip = <1>;
+	ddrsmp=<0>;
+
+	flash0: n25q512ax3@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q512ax3", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <0>;
+	};
+
+	flash1: n25q512ax3@1 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q512ax3", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <1>;
+	};
+
+	flash2: n25q512ax3@2 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q512ax3", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <2>;
+	};
+
+	flash3: n25q512ax3@3 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q512ax3", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+		reg = <3>;
+	};
+};
\ No newline at end of file
diff --git a/arch/arm/dts/imx7d-19x19-lpddr2-val.dts b/arch/arm/dts/imx7d-19x19-lpddr2-val.dts
new file mode 100644
index 00000000000..2475ad46b91
--- /dev/null
+++ b/arch/arm/dts/imx7d-19x19-lpddr2-val.dts
@@ -0,0 +1,395 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx7d.dtsi"
+
+/ {
+	model = "i.MX7D LPDDR2 19x19 VAL Board";
+	compatible = "fsl,imx7d-19x19-lpddr2-val", "fsl,imx7d";
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_keys>;
+		status = "disabled";
+
+		volume-up {
+			label = "Volume Up";
+			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEUP>;
+		};
+
+		volume-down {
+			label = "Volume Down";
+			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEDOWN>;
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_sd1_vmmc: sd1_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "VCC_SD1";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg2_vbus: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "usb_otg2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_vref_1v8: regulator@2 {
+			compatible = "regulator-fixed";
+			regulator-name = "vref-1v8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+	};
+
+	memory {
+		reg = <0x80000000 0x20000000>;
+	};
+};
+
+&adc1 {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&sw1a_reg>;
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1_1>;
+	pinctrl-1 = <&pinctrl_i2c1_1_gpio>;
+	scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pfuze3000@8 {
+		compatible = "fsl,pfuze3000";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1a {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+			/* use sw1c_reg to align with pfuze100/pfuze200 */
+			sw1c_reg: sw1b {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1850000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1650000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vldo1 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen2_reg: vldo2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vccsd {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: v33 {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vldo3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vldo4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2_1>;
+	pinctrl-1 = <&pinctrl_i2c2_1_gpio>;
+	scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	imx7d-19x19-lpddr3-val {
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C4_SCL__GPIO4_IO14	   0x80000000
+
+				MX7D_PAD_SD1_CD_B__GPIO5_IO0 		0x59
+				MX7D_PAD_SD1_WP__GPIO5_IO1 			0x59
+				MX7D_PAD_SD1_RESET_B__GPIO5_IO2 	0x59
+
+				MX7D_PAD_GPIO1_IO14__GPIO1_IO14    	0x59
+				MX7D_PAD_GPIO1_IO15__GPIO1_IO15    	0x59
+			>;
+		};
+
+		pinctrl_gpio_keys: gpio_keysgrp {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32
+				MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32
+			>;
+		};
+
+		pinctrl_gpmi_nand_1: gpmi-nand-1 {
+			fsl,pins = <
+				MX7D_PAD_SD3_CLK__NAND_CLE			0x71
+				MX7D_PAD_SD3_CMD__NAND_ALE			0x71
+				MX7D_PAD_SAI1_MCLK__NAND_WP_B		0x71
+				MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B	0x71
+				MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B	0x71
+				MX7D_PAD_SAI1_TX_DATA__NAND_READY_B	0x74
+				MX7D_PAD_SD3_STROBE__NAND_RE_B		0x71
+				MX7D_PAD_SD3_RESET_B__NAND_WE_B		0x71
+				MX7D_PAD_SD3_DATA0__NAND_DATA00		0x71
+				MX7D_PAD_SD3_DATA1__NAND_DATA01		0x71
+				MX7D_PAD_SD3_DATA2__NAND_DATA02		0x71
+				MX7D_PAD_SD3_DATA3__NAND_DATA03		0x71
+				MX7D_PAD_SD3_DATA4__NAND_DATA04		0x71
+				MX7D_PAD_SD3_DATA5__NAND_DATA05		0x71
+				MX7D_PAD_SD3_DATA6__NAND_DATA06		0x71
+				MX7D_PAD_SD3_DATA7__NAND_DATA07		0x71
+			>;
+		};
+
+		pinctrl_i2c1_1: i2c1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C1_SDA__I2C1_SDA          0x4000007f
+				MX7D_PAD_I2C1_SCL__I2C1_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_i2c1_1_gpio: i2c1grp-1-gpio {
+			fsl,pins = <
+				MX7D_PAD_I2C1_SDA__GPIO4_IO9          0x7f
+				MX7D_PAD_I2C1_SCL__GPIO4_IO8          0x7f
+			>;
+		};
+
+		pinctrl_i2c2_1: i2c2grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C2_SDA__I2C2_SDA          0x4000007f
+				MX7D_PAD_I2C2_SCL__I2C2_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_i2c2_1_gpio: i2c2grp-1-gpio {
+			fsl,pins = <
+				MX7D_PAD_I2C2_SDA__GPIO4_IO11          0x7f
+				MX7D_PAD_I2C2_SCL__GPIO4_IO10          0x7f
+			>;
+		};
+
+		pinctrl_uart1_1: uart1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
+				MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
+			>;
+		};
+
+		pinctrl_uart3_1: uart3grp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX	0x79
+				MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX	0x79
+				MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS		0x79
+				MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS		0x79
+			>;
+		};
+
+		pinctrl_uart3dte_1: uart3dtegrp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX	0x79
+				MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX	0x79
+				MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS		0x79
+				MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS		0x79
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX7D_PAD_SD1_CMD__SD1_CMD       0x59
+				MX7D_PAD_SD1_CLK__SD1_CLK       0x19
+				MX7D_PAD_SD1_DATA0__SD1_DATA0   0x59
+				MX7D_PAD_SD1_DATA1__SD1_DATA1   0x59
+				MX7D_PAD_SD1_DATA2__SD1_DATA2   0x59
+				MX7D_PAD_SD1_DATA3__SD1_DATA3   0x59
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+			fsl,pins = <
+				MX7D_PAD_SD1_CMD__SD1_CMD       0x5a
+				MX7D_PAD_SD1_CLK__SD1_CLK       0x1a
+				MX7D_PAD_SD1_DATA0__SD1_DATA0   0x5a
+				MX7D_PAD_SD1_DATA1__SD1_DATA1   0x5a
+				MX7D_PAD_SD1_DATA2__SD1_DATA2   0x5a
+				MX7D_PAD_SD1_DATA3__SD1_DATA3   0x5a
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+			fsl,pins = <
+				MX7D_PAD_SD1_CMD__SD1_CMD       0x5b
+				MX7D_PAD_SD1_CLK__SD1_CLK       0x1b
+				MX7D_PAD_SD1_DATA0__SD1_DATA0   0x5b
+				MX7D_PAD_SD1_DATA1__SD1_DATA1   0x5b
+				MX7D_PAD_SD1_DATA2__SD1_DATA2   0x5b
+				MX7D_PAD_SD1_DATA3__SD1_DATA3   0x5b
+			>;
+		};
+	};
+};
+
+&iomuxc_lpsr {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_2>;
+
+	imx7d-19x19-lpddr3-val {
+		pinctrl_hog_2: hoggrp-2 {
+			fsl,pins = <
+				MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14
+				MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14
+				MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14
+			>;
+		};
+	};
+};
+
+&sdma {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_1>;
+	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3_1>;
+	fsl,uart-has-rtscts;
+	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+	status = "okay";
+	/* for DTE mode, add below change */
+	/* fsl,dte-mode;*/
+	pinctrl-0 = <&pinctrl_uart3dte_1>;
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	status = "okay";
+};
+
+&usbotg2 {
+	vbus-supply = <&reg_usb_otg2_vbus>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+	no-1-8-v;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sd1_vmmc>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx7d-19x19-lpddr3-val.dts b/arch/arm/dts/imx7d-19x19-lpddr3-val.dts
new file mode 100644
index 00000000000..c7b98e9b0b8
--- /dev/null
+++ b/arch/arm/dts/imx7d-19x19-lpddr3-val.dts
@@ -0,0 +1,403 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx7d.dtsi"
+
+/ {
+	model = "i.MX7 LPDDR3 19x19 VAL Board";
+	compatible = "fsl,imx7d-19x19-lpddr3-val", "fsl,imx7d";
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_keys>;
+		status = "disabled";
+
+		volume-up {
+			label = "Volume Up";
+			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEUP>;
+		};
+
+		volume-down {
+			label = "Volume Down";
+			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEDOWN>;
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_sd1_vmmc: sd1_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "VCC_SD1";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg2_vbus: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "usb_otg2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_vref_1v8: regulator@2 {
+			compatible = "regulator-fixed";
+			regulator-name = "vref-1v8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+	};
+
+	memory {
+		reg = <0x80000000 0x80000000>;
+	};
+};
+
+&adc1 {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&sw1a_reg>;
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "okay";
+	nand-on-flash-bbt;
+	fsl,use-minimum-ecc;
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1_1>;
+	pinctrl-1 = <&pinctrl_i2c1_1_gpio>;
+	scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pfuze3000@8 {
+		compatible = "fsl,pfuze3000";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1a {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+			/* use sw1c_reg to align with pfuze100/pfuze200 */
+			sw1c_reg: sw1b {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1850000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1650000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vldo1 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen2_reg: vldo2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vccsd {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: v33 {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vldo3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vldo4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2_1>;
+	pinctrl-1 = <&pinctrl_i2c2_1_gpio>;
+	scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	imx7d-19x19-lpddr3-val {
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C4_SCL__GPIO4_IO14	   0x80000000
+
+				MX7D_PAD_SD1_CD_B__GPIO5_IO0 		0x59
+				MX7D_PAD_SD1_WP__GPIO5_IO1 			0x59
+				MX7D_PAD_SD1_RESET_B__GPIO5_IO2 	0x59
+
+				MX7D_PAD_GPIO1_IO14__GPIO1_IO14    	0x59
+				MX7D_PAD_GPIO1_IO15__GPIO1_IO15    	0x59
+			>;
+		};
+
+		pinctrl_gpio_keys: gpio_keysgrp {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32
+				MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32
+			>;
+		};
+
+		pinctrl_gpmi_nand_1: gpmi-nand-1 {
+			fsl,pins = <
+				MX7D_PAD_SD3_CLK__NAND_CLE			0x71
+				MX7D_PAD_SD3_CMD__NAND_ALE			0x71
+				MX7D_PAD_SAI1_MCLK__NAND_WP_B		0x71
+				MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B	0x71
+				MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B	0x71
+				MX7D_PAD_SAI1_TX_DATA__NAND_READY_B	0x74
+				MX7D_PAD_SD3_STROBE__NAND_RE_B		0x71
+				MX7D_PAD_SD3_RESET_B__NAND_WE_B		0x71
+				MX7D_PAD_SD3_DATA0__NAND_DATA00		0x71
+				MX7D_PAD_SD3_DATA1__NAND_DATA01		0x71
+				MX7D_PAD_SD3_DATA2__NAND_DATA02		0x71
+				MX7D_PAD_SD3_DATA3__NAND_DATA03		0x71
+				MX7D_PAD_SD3_DATA4__NAND_DATA04		0x71
+				MX7D_PAD_SD3_DATA5__NAND_DATA05		0x71
+				MX7D_PAD_SD3_DATA6__NAND_DATA06		0x71
+				MX7D_PAD_SD3_DATA7__NAND_DATA07		0x71
+			>;
+		};
+
+		pinctrl_i2c1_1: i2c1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C1_SDA__I2C1_SDA          0x4000007f
+				MX7D_PAD_I2C1_SCL__I2C1_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_i2c1_1_gpio: i2c1grp-1-gpio {
+			fsl,pins = <
+				MX7D_PAD_I2C1_SDA__GPIO4_IO9          0x7f
+				MX7D_PAD_I2C1_SCL__GPIO4_IO8          0x7f
+			>;
+		};
+
+		pinctrl_i2c2_1: i2c2grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C2_SDA__I2C2_SDA          0x4000007f
+				MX7D_PAD_I2C2_SCL__I2C2_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_i2c2_1_gpio: i2c2grp-1-gpio {
+			fsl,pins = <
+				MX7D_PAD_I2C2_SDA__GPIO4_IO11          0x7f
+				MX7D_PAD_I2C2_SCL__GPIO4_IO10          0x7f
+			>;
+		};
+
+		pinctrl_uart1_1: uart1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
+				MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
+			>;
+		};
+
+		pinctrl_uart3_1: uart3grp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX	0x79
+				MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX	0x79
+				MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS		0x79
+				MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS		0x79
+			>;
+		};
+
+		pinctrl_uart3dte_1: uart3dtegrp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX	0x79
+				MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX	0x79
+				MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS		0x79
+				MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS		0x79
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX7D_PAD_SD1_CMD__SD1_CMD       0x59
+				MX7D_PAD_SD1_CLK__SD1_CLK       0x19
+				MX7D_PAD_SD1_DATA0__SD1_DATA0   0x59
+				MX7D_PAD_SD1_DATA1__SD1_DATA1   0x59
+				MX7D_PAD_SD1_DATA2__SD1_DATA2   0x59
+				MX7D_PAD_SD1_DATA3__SD1_DATA3   0x59
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+			fsl,pins = <
+				MX7D_PAD_SD1_CMD__SD1_CMD       0x5a
+				MX7D_PAD_SD1_CLK__SD1_CLK       0x1a
+				MX7D_PAD_SD1_DATA0__SD1_DATA0   0x5a
+				MX7D_PAD_SD1_DATA1__SD1_DATA1   0x5a
+				MX7D_PAD_SD1_DATA2__SD1_DATA2   0x5a
+				MX7D_PAD_SD1_DATA3__SD1_DATA3   0x5a
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+			fsl,pins = <
+				MX7D_PAD_SD1_CMD__SD1_CMD       0x5b
+				MX7D_PAD_SD1_CLK__SD1_CLK       0x1b
+				MX7D_PAD_SD1_DATA0__SD1_DATA0   0x5b
+				MX7D_PAD_SD1_DATA1__SD1_DATA1   0x5b
+				MX7D_PAD_SD1_DATA2__SD1_DATA2   0x5b
+				MX7D_PAD_SD1_DATA3__SD1_DATA3   0x5b
+			>;
+		};
+	};
+};
+
+&iomuxc_lpsr {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_2>;
+
+	imx7d-19x19-lpddr3-val {
+		pinctrl_hog_2: hoggrp-2 {
+			fsl,pins = <
+				MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14
+				MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14
+				MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14
+			>;
+		};
+	};
+};
+
+&sdma {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_1>;
+	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3_1>;
+	fsl,uart-has-rtscts;
+	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+	status = "okay";
+	/* for DTE mode, add below change */
+	/* fsl,dte-mode;*/
+	pinctrl-0 = <&pinctrl_uart3dte_1>;
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	status = "okay";
+};
+
+&usbotg2 {
+	vbus-supply = <&reg_usb_otg2_vbus>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+	no-1-8-v;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sd1_vmmc>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx7d-pinfunc.h b/arch/arm/dts/imx7d-pinfunc.h
index f2493bc63da..aa9dbead4b8 100644
--- a/arch/arm/dts/imx7d-pinfunc.h
+++ b/arch/arm/dts/imx7d-pinfunc.h
@@ -592,7 +592,7 @@
 #define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX                      0x0130 0x03A0 0x06FC 0x0 0x2
 #define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX                      0x0130 0x03A0 0x0000 0x0 0x0
 #define MX7D_PAD_UART2_RX_DATA__I2C2_SCL                          0x0130 0x03A0 0x05DC 0x1 0x0
-#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK                      0x0130 0x03A0 0x0000 0x2 0x0
+#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK                      0x0130 0x03A0 0x06C4 0x2 0x0
 #define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3                        0x0130 0x03A0 0x0000 0x3 0x0
 #define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN              0x0130 0x03A0 0x0000 0x4 0x0
 #define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2                         0x0130 0x03A0 0x0000 0x5 0x0
@@ -1112,13 +1112,13 @@
 #define MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9                       0x0250 0x04C0 0x0000 0x5 0x0
 #define MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS                0x0250 0x04C0 0x0000 0x7 0x0
 #define MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL           0x0254 0x04C4 0x0000 0x0 0x0
-#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC                 0x0254 0x04C4 0x0000 0x2 0x0
+#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC                 0x0254 0x04C4 0x06A4 0x2 0x1
 #define MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1                0x0254 0x04C4 0x0000 0x3 0x0
 #define MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2               0x0254 0x04C4 0x0000 0x4 0x0
 #define MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10                   0x0254 0x04C4 0x0000 0x5 0x0
 #define MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC                 0x0258 0x04C8 0x0000 0x0 0x0
 #define MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER                     0x0258 0x04C8 0x0000 0x1 0x0
-#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK                    0x0258 0x04C8 0x0000 0x2 0x0
+#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK                    0x0258 0x04C8 0x069C 0x2 0x1
 #define MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2                   0x0258 0x04C8 0x0000 0x3 0x0
 #define MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3                  0x0258 0x04C8 0x0000 0x4 0x0
 #define MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11                      0x0258 0x04C8 0x0000 0x5 0x0
diff --git a/arch/arm/dts/imx7d-sdb-epdc.dts b/arch/arm/dts/imx7d-sdb-epdc.dts
new file mode 100644
index 00000000000..8183a254142
--- /dev/null
+++ b/arch/arm/dts/imx7d-sdb-epdc.dts
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ */
+
+#include "imx7d-sdb.dts"
+
+&epdc {
+        status = "okay";
+};
+
+&fec1 {
+	status = "okay";
+};
+
+&fec2 {
+	status = "disabled";
+};
+
+&reg_can2_3v3 {
+	status = "disabled";
+};
+
+&reg_fec2_3v3 {
+	status = "disabled";
+};
+
+&flexcan2 {
+	status = "disabled";
+};
+
+&max17135 {
+        status = "okay";
+};
+
+&sii902x {
+	status = "disabled";
+};
+
+&sim1 {
+	status = "disabled";
+};
+
+&uart5 {
+	status = "disabled";
+};
+
+&i2c3 {
+	elan@10 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_epdc_elan_touch>;
+		compatible = "elan,elan-touch";
+		reg = <0x10>;
+		interrupt-parent = <&gpio6>;
+		interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+		gpio_elan_cs = <&gpio6 13 0>;
+		gpio_elan_rst = <&gpio6 15 0>;
+		gpio_intr = <&gpio6 12 0>;
+		status = "okay";
+	};
+};
diff --git a/arch/arm/dts/imx7d-sdb-gpmi-weim.dts b/arch/arm/dts/imx7d-sdb-gpmi-weim.dts
new file mode 100644
index 00000000000..cba5f52f3a7
--- /dev/null
+++ b/arch/arm/dts/imx7d-sdb-gpmi-weim.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
+ */
+
+#include "imx7d-sdb.dts"
+
+&gpmi{
+	status = "okay";
+};
+
+&sai1{
+	status = "disabled";
+};
+
+&usdhc3{
+	status = "disabled";
+};
+
+&uart5{
+	status = "disabled";
+};
diff --git a/arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi b/arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi
deleted file mode 100644
index 585af6d211f..00000000000
--- a/arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi
+++ /dev/null
@@ -1,10 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2018 NXP
- */
-
-&qspi1 {
-	flash0: mx25l51245g@0 {
-		compatible = "jedec,spi-nor";
-	};
-};
diff --git a/arch/arm/dts/imx7d-sdb-qspi.dts b/arch/arm/dts/imx7d-sdb-qspi.dts
index 9bb4c743c14..e88564fc902 100644
--- a/arch/arm/dts/imx7d-sdb-qspi.dts
+++ b/arch/arm/dts/imx7d-sdb-qspi.dts
@@ -12,17 +12,15 @@
 };
 
 &iomuxc {
-	qspi1 {
-		pinctrl_qspi1_1: qspi1grp_1 {
-			fsl,pins = <
-				MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51
-				MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51
-				MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51
-				MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51
-				MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51
-				MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51
-			>;
-		};
+	pinctrl_qspi1_1: qspi1grp_1 {
+		fsl,pins = <
+			MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51
+			MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51
+			MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51
+			MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51
+			MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51
+			MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51
+		>;
 	};
 };
 
@@ -35,10 +33,8 @@
 	flash0: mx25l51245g@0 {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "macronix,mx25l51245g";
+		compatible = "jedec,spi-nor";
 		spi-max-frequency = <29000000>;
-		/* take off one dummy cycle */
-		spi-nor,ddr-quad-read-dummy = <5>;
 		reg = <0>;
 	};
 };
diff --git a/arch/arm/dts/imx7d-sdb-reva.dts b/arch/arm/dts/imx7d-sdb-reva.dts
new file mode 100644
index 00000000000..df06df09647
--- /dev/null
+++ b/arch/arm/dts/imx7d-sdb-reva.dts
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx7d-sdb.dts"
+
+/ {
+	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
+		pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg_reva>;
+		gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&fec2 {
+	/delete-property/phy-supply;
+};
+
+&iomuxc {
+	imx7d-sdb {
+		pinctrl_tsc2046_pendown: tsc2046_pendown {
+			fsl,pins = <
+				MX7D_PAD_EPDC_DATA13__GPIO2_IO13	0x59
+			>;
+		};
+
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				MX7D_PAD_ECSPI2_SS0__GPIO4_IO23		0x34  /* bt reg on */
+			>;
+		};
+
+		pinctrl_usb_otg2_vbus_reg_reva: usbotg2vbusregrevagrp {
+			fsl,pins = <
+				MX7D_PAD_UART3_CTS_B__GPIO4_IO7		0x14
+			>;
+		};
+	};
+};
diff --git a/arch/arm/dts/imx7d-sdb-u-boot.dtsi b/arch/arm/dts/imx7d-sdb-u-boot.dtsi
deleted file mode 100644
index b78358fa139..00000000000
--- a/arch/arm/dts/imx7d-sdb-u-boot.dtsi
+++ /dev/null
@@ -1,7 +0,0 @@
-&fec2 {
-	status = "disable";
-};
-
-&usbotg1 {
-	dr_mode = "peripheral";
-};
diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts
index ea2e58dd5aa..9f65b275629 100644
--- a/arch/arm/dts/imx7d-sdb.dts
+++ b/arch/arm/dts/imx7d-sdb.dts
@@ -8,9 +8,14 @@
 #include "imx7d.dtsi"
 
 / {
-	model = "Freescale i.MX7 SabreSD Board";
+	model = "i.MX7 SabreSD Board";
 	compatible = "fsl,imx7d-sdb", "fsl,imx7d";
 
+	aliases {
+		spi5 = &soft_spi;
+		gpio7 = &extended_io;
+	};
+
 	chosen {
 		stdout-path = &uart1;
 	};
@@ -20,6 +25,13 @@
 		reg = <0x80000000 0x80000000>;
 	};
 
+	modem_reset: modem-reset {
+		compatible = "gpio-reset";
+		reset-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <1000>;
+		#reset-cells = <0>;
+	};
+
 	gpio-keys {
 		compatible = "gpio-keys";
 		pinctrl-names = "default";
@@ -40,7 +52,7 @@
 		};
 	};
 
-	spi4 {
+	soft_spi: soft-spi {
 		compatible = "spi-gpio";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_spi4>;
@@ -57,6 +69,7 @@
 			#gpio-cells = <2>;
 			reg = <0>;
 			registers-number = <1>;
+			registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/
 			spi-max-frequency = <100000>;
 		};
 	};
@@ -88,16 +101,15 @@
 		regulator-max-microvolt = <1800000>;
 	};
 
-	reg_brcm: regulator-brcm {
+	reg_sd1_vmmc: regulator-sd1-vmmc {
 		compatible = "regulator-fixed";
-		gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-		regulator-name = "brcm_reg";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_brcm_reg>;
+		regulator-name = "VDD_SD1";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
 		startup-delay-us = <200000>;
+		off-on-delay-us = <20000>;
+		enable-active-high;
 	};
 
 	reg_lcd_3v3: regulator-lcd-3v3 {
@@ -136,16 +148,41 @@
 		status = "okay";
 	};
 
-	panel {
-		compatible = "innolux,at043tn24";
-		backlight = <&backlight>;
-		power-supply = <&reg_lcd_3v3>;
+	pxp_v4l2_out {
+		compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
+		status = "okay";
+	};
 
-		port {
-			panel_in: endpoint {
-				remote-endpoint = <&display_out>;
-			};
-		};
+	sound {
+		compatible = "fsl,imx7d-evk-wm8960",
+			     "fsl,imx-audio-wm8960";
+		model = "wm8960-audio";
+		audio-cpu = <&sai1>;
+		audio-codec = <&codec>;
+		hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>;
+		audio-routing =
+			"Headphone Jack", "HP_L",
+			"Headphone Jack", "HP_R",
+			"Ext Spk", "SPK_LP",
+			"Ext Spk", "SPK_LN",
+			"Ext Spk", "SPK_RP",
+			"Ext Spk", "SPK_RN",
+			"LINPUT1", "AMIC",
+			"AMIC", "MICB";
+	};
+
+	sound-hdmi {
+		compatible = "fsl,imx-audio-sii902x";
+		model = "sii902x-audio";
+		audio-cpu = <&sai3>;
+		hdmi-out;
+	};
+
+	usdhc2_pwrseq: usdhc2_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_brcm_reg>;
+		reset-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
 	};
 };
 
@@ -163,10 +200,26 @@
 	cpu-supply = <&sw1a_reg>;
 };
 
+&cpu1 {
+	cpu-supply = <&sw1a_reg>;
+};
+
+&csi1 {
+	csi-mux-mipi = <&gpr 0x14 4>;
+	fsl,mipi-mode;
+	status = "okay";
+
+	port {
+		csi_ep: endpoint {
+			remote-endpoint = <&csi_mipi_ep>;
+		};
+	};
+};
+
 &ecspi3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ecspi3>;
-	cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 	status = "okay";
 
 	tsc2046@0 {
@@ -188,13 +241,32 @@
 	};
 };
 
+&epdc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_epdc0 &pinctrl_enet2_reg>;
+	V3P3-supply = <&V3P3_reg>;
+	VCOM-supply = <&VCOM_reg>;
+	DISPLAY-supply = <&DISPLAY_reg>;
+	en-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+	status = "disabled";
+};
+
+&epxp {
+	status = "okay";
+};
+
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet1>;
-	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
-			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
-	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
-	assigned-clock-rates = <0>, <100000000>;
+	assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>,
+			  <&clks IMX7D_ENET_AXI_ROOT_SRC>,
+			  <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
+			  <&clks IMX7D_ENET_AXI_ROOT_CLK>;
+	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>,
+				 <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
+				 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+	assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>;
 	phy-mode = "rgmii";
 	phy-handle = <&ethphy0>;
 	fsl,magic-packet;
@@ -218,10 +290,15 @@
 &fec2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet2>;
-	assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
-			  <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
-	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
-	assigned-clock-rates = <0>, <100000000>;
+	assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>,
+			  <&clks IMX7D_ENET_AXI_ROOT_SRC>,
+			  <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
+			  <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
+			  <&clks IMX7D_ENET_AXI_ROOT_CLK>;
+	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>,
+				 <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
+				 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+	assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>;
 	phy-mode = "rgmii";
 	phy-handle = <&ethphy1>;
 	phy-supply = <&reg_fec2_3v3>;
@@ -236,6 +313,32 @@
 	status = "okay";
 };
 
+&mipi_csi {
+	clock-frequency = <240000000>;
+	status = "okay";
+	port {
+		mipi_sensor_ep: endpoint@1 {
+			remote-endpoint = <&ov5640_mipi_ep>;
+			data-lanes = <2>;
+			csis-hs-settle = <13>;
+			csis-clk-settle = <2>;
+			csis-wclk;
+		};
+
+		csi_mipi_ep: endpoint@2 {
+			remote-endpoint = <&csi_ep>;
+		};
+	};
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "disabled";
+	nand-on-flash-bbt;
+	fsl,use-minimum-ecc;
+};
+
 &i2c1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_i2c1>;
@@ -333,10 +436,24 @@
 };
 
 &i2c2 {
-	pinctrl-names = "default";
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
+	fxas2100x@20 {
+		compatible = "nxp,fxas21002c";
+		reg = <0x20>;
+	};
+
+	fxos8700@1e {
+		compatible = "fsl,fxos8700";
+		reg = <0x1e>;
+	};
+
 	mpl3115@60 {
 		compatible = "fsl,mpl3115";
 		reg = <0x60>;
@@ -344,14 +461,104 @@
 };
 
 &i2c3 {
-	pinctrl-names = "default";
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
 	status = "okay";
+
+	sii902x: sii902x@39 {
+		compatible = "SiI,sii902x";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_sii902x>;
+		interrupt-parent = <&gpio2>;
+		interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+		mode_str ="1280x720M@60";
+		bits-per-pixel = <16>;
+		reg = <0x39>;
+		status = "okay";
+	};
+
+	max17135: max17135@48 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_max17135>;
+		compatible = "maxim,max17135";
+		reg = <0x48>;
+		status = "disabled";
+
+		vneg_pwrup = <1>;
+		gvee_pwrup = <2>;
+		vpos_pwrup = <10>;
+		gvdd_pwrup = <12>;
+		gvdd_pwrdn = <1>;
+		vpos_pwrdn = <2>;
+		gvee_pwrdn = <8>;
+		vneg_pwrdn = <10>;
+		gpio_pmic_pwrgood = <&gpio2 31 0>;
+		gpio_pmic_vcom_ctrl = <&gpio4 14 0>;
+		gpio_pmic_wakeup = <&gpio2 23 0>;
+		gpio_pmic_v3p3 = <&gpio2 30 0>;
+		gpio_pmic_intr = <&gpio2 22 0>;
+
+		regulators {
+			DISPLAY_reg: DISPLAY {
+				regulator-name = "DISPLAY";
+			};
+
+			GVDD_reg: GVDD {
+				/* 20v */
+				regulator-name = "GVDD";
+			};
+
+			GVEE_reg: GVEE {
+				/* -22v */
+				regulator-name = "GVEE";
+			};
+
+			HVINN_reg: HVINN {
+				/* -22v */
+				regulator-name = "HVINN";
+			};
+
+			HVINP_reg: HVINP {
+				/* 20v */
+				regulator-name = "HVINP";
+			};
+
+			VCOM_reg: VCOM {
+				regulator-name = "VCOM";
+				/* Real max value: -500000 */
+				regulator-max-microvolt = <4325000>;
+				/* Real min value: -4325000 */
+				regulator-min-microvolt = <500000>;
+			};
+
+			VNEG_reg: VNEG {
+				/* -15v */
+				regulator-name = "VNEG";
+			};
+
+			VPOS_reg: VPOS {
+				/* 15v */
+				regulator-name = "VPOS";
+			};
+
+			V3P3_reg: V3P3 {
+				regulator-name = "V3P3";
+			};
+		};
+	};
 };
 
 &i2c4 {
-	pinctrl-names = "default";
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c4>;
+	pinctrl-1 = <&pinctrl_i2c4_gpio>;
+	scl-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
 	codec: wm8960@1a {
@@ -360,21 +567,113 @@
 		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 		clock-names = "mclk";
 		wlf,shared-lrclk;
+		wlf,hp-cfg = <2 2 3>;
+		wlf,gpio-cfg = <1 3>;
+		assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
+				  <&clks IMX7D_PLL_AUDIO_POST_DIV>,
+				  <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
+		assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+		assigned-clock-rates = <0>, <884736000>, <12288000>;
+	};
+
+	ov5640_mipi: ov5640_mipi@3c {
+		compatible = "ovti,ov5640_mipi";
+		reg = <0x3c>;
+		clocks = <&clks IMX7D_CLK_DUMMY>;
+		clock-names = "csi_mclk";
+		csi_id = <0>;
+		pwn-gpios = <&extended_io 6 GPIO_ACTIVE_HIGH>;
+		AVDD-supply = <&vgen6_reg>;
+		mclk = <24000000>;
+		mclk_source = <0>;
+		port {
+			ov5640_mipi_ep: endpoint {
+				remote-endpoint = <&mipi_sensor_ep>;
+			};
+		};
 	};
 };
 
 &lcdif {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lcdif>;
+	lcd-supply = <&reg_lcd_3v3>;
+	display = <&display0>;
 	status = "okay";
 
-	port {
-		display_out: endpoint {
-			remote-endpoint = <&panel_in>;
+	display0: display@0 {
+		bits-per-pixel = <24>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+
+			timing0: timing0 {
+				clock-frequency = <9200000>;
+				hactive = <480>;
+				vactive = <272>;
+				hfront-porch = <8>;
+				hback-porch = <4>;
+				hsync-len = <41>;
+				vback-porch = <2>;
+				vfront-porch = <4>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
 		};
 	};
 };
 
+&pcie {
+	reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&reg_1p0d {
+	vin-supply = <&sw2_reg>;
+};
+
+&reg_1p2 {
+	vin-supply = <&sw2_reg>;
+};
+
+&sai1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai1>;
+	assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
+			  <&clks IMX7D_PLL_AUDIO_POST_DIV>,
+			  <&clks IMX7D_SAI1_ROOT_CLK>;
+	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+	assigned-clock-rates = <0>, <884736000>, <36864000>;
+	status = "okay";
+};
+
+&sai3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>;
+	assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
+			  <&clks IMX7D_PLL_AUDIO_POST_DIV>,
+			  <&clks IMX7D_SAI3_ROOT_CLK>;
+	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+	assigned-clock-rates = <0>, <884736000>, <36864000>;
+	status = "okay";
+};
+
+&sim1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sim1_1>;
+	port = <0>;
+	sven_low_active;
+	status = "okay";
+};
+
+&snvs_poweroff {
+	status = "okay";
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };
@@ -383,7 +682,18 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1>;
 	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+	status = "okay";
+};
+
+&uart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart5>;
+	assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
 	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+	/* for DTE mode, add below change */
+	/* fsl,dte-mode; */
+	/* pinctrl-0 = <&pinctrl_uart5dte>; */
 	status = "okay";
 };
 
@@ -393,6 +703,7 @@
 	assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
 	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 	uart-has-rtscts;
+	resets = <&modem_reset>;
 	status = "okay";
 };
 
@@ -408,26 +719,35 @@
 };
 
 &usdhc1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
 	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
-	wakeup-source;
-	keep-power-in-suspend;
+	vmmc-supply = <&reg_sd1_vmmc>;
 	status = "okay";
 };
 
 &usdhc2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc2>;
-	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
-	wakeup-source;
+	pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz &pinctrl_wifi>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz &pinctrl_wifi>;
 	keep-power-in-suspend;
 	non-removable;
-	vmmc-supply = <&reg_brcm>;
+	mmc-pwrseq = <&usdhc2_pwrseq>;
 	fsl,tuning-step = <2>;
-	status = "okay";
+	pm-ignore-notify;
+	cap-power-off-card;
+	status = "disabled";
+
+	brcmf: bcrmf@1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+	};
 };
 
 &usdhc3 {
@@ -438,8 +758,8 @@
 	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 	assigned-clock-rates = <400000000>;
 	bus-width = <8>;
-	fsl,tuning-step = <2>;
 	non-removable;
+	auto-cmd23-broken;
 	status = "okay";
 };
 
@@ -460,6 +780,19 @@
 			>;
 		};
 
+		pinctrl_epdc_elan_touch: epdc_elan_touch_grp {
+			fsl,pins = <
+				MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x59
+				MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x1b
+				MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x80000000
+			>;
+		};
+		pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp {
+			fsl,pins = <
+				MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x1b
+			>;
+		};
+
 		pinctrl_ecspi3: ecspi3grp {
 			fsl,pins = <
 				MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO	0x2
@@ -505,9 +838,34 @@
 			>;
 		};
 
-		pinctrl_enet2_reg: enet2reggrp {
+		pinctrl_epdc0: epdcgrp0 {
 			fsl,pins = <
-				MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4	0x14
+				MX7D_PAD_EPDC_DATA00__EPDC_DATA0  0x2
+				MX7D_PAD_EPDC_DATA01__EPDC_DATA1  0x2
+				MX7D_PAD_EPDC_DATA02__EPDC_DATA2  0x2
+				MX7D_PAD_EPDC_DATA03__EPDC_DATA3  0x2
+				MX7D_PAD_EPDC_DATA04__EPDC_DATA4  0x2
+				MX7D_PAD_EPDC_DATA05__EPDC_DATA5  0x2
+				MX7D_PAD_EPDC_DATA06__EPDC_DATA6  0x2
+				MX7D_PAD_EPDC_DATA07__EPDC_DATA7  0x2
+				MX7D_PAD_EPDC_DATA08__EPDC_DATA8  0x2
+				MX7D_PAD_EPDC_DATA09__EPDC_DATA9  0x2
+				MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2
+				MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2
+				MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2
+				MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2
+				MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2
+				MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2
+				MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK   0x2
+				MX7D_PAD_EPDC_SDLE__EPDC_SDLE     0x2
+				MX7D_PAD_EPDC_SDOE__EPDC_SDOE     0x2
+				MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR   0x2
+				MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0   0x2
+				MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1   0x2
+				MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK   0x2
+				MX7D_PAD_EPDC_GDOE__EPDC_GDOE     0x2
+				MX7D_PAD_EPDC_GDRL__EPDC_GDRL     0x2
+				MX7D_PAD_EPDC_GDSP__EPDC_GDSP     0x2
 			>;
 		};
 
@@ -531,6 +889,27 @@
 			>;
 		};
 
+		pinctrl_gpmi_nand_1: gpmi-nand-1 {
+			fsl,pins = <
+				MX7D_PAD_SD3_CLK__NAND_CLE		0x71
+				MX7D_PAD_SD3_CMD__NAND_ALE		0x71
+				MX7D_PAD_SAI1_MCLK__NAND_WP_B		0x71
+				MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B	0x71
+				MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B	0x71
+				MX7D_PAD_SAI1_TX_DATA__NAND_READY_B	0x74
+				MX7D_PAD_SD3_STROBE__NAND_RE_B		0x71
+				MX7D_PAD_SD3_RESET_B__NAND_WE_B		0x71
+				MX7D_PAD_SD3_DATA0__NAND_DATA00		0x71
+				MX7D_PAD_SD3_DATA1__NAND_DATA01		0x71
+				MX7D_PAD_SD3_DATA2__NAND_DATA02		0x71
+				MX7D_PAD_SD3_DATA3__NAND_DATA03		0x71
+				MX7D_PAD_SD3_DATA4__NAND_DATA04		0x71
+				MX7D_PAD_SD3_DATA5__NAND_DATA05		0x71
+				MX7D_PAD_SD3_DATA6__NAND_DATA06		0x71
+				MX7D_PAD_SD3_DATA7__NAND_DATA07		0x71
+			>;
+		};
+
 		pinctrl_hog: hoggrp {
 			fsl,pins = <
 				MX7D_PAD_ECSPI2_SS0__GPIO4_IO23		0x34  /* bt reg on */
@@ -544,6 +923,13 @@
 			>;
 		};
 
+		pinctrl_i2c1_gpio: i2c1grp_gpio {
+			fsl,pins = <
+				MX7D_PAD_I2C1_SDA__GPIO4_IO9	0x7f
+				MX7D_PAD_I2C1_SCL__GPIO4_IO8	0x7f
+			>;
+		};
+
 		pinctrl_i2c2: i2c2grp {
 			fsl,pins = <
 				MX7D_PAD_I2C2_SDA__I2C2_SDA		0x4000007f
@@ -551,6 +937,13 @@
 			>;
 		};
 
+		pinctrl_i2c2_gpio: i2c2grp_gpio {
+			fsl,pins = <
+				MX7D_PAD_I2C2_SDA__GPIO4_IO11	0x7f
+				MX7D_PAD_I2C2_SCL__GPIO4_IO10	0x7f
+			>;
+		};
+
 		pinctrl_i2c3: i2c3grp {
 			fsl,pins = <
 				MX7D_PAD_I2C3_SDA__I2C3_SDA		0x4000007f
@@ -558,6 +951,13 @@
 			>;
 		};
 
+		pinctrl_i2c3_gpio: i2c3grp_gpio {
+			fsl,pins = <
+				MX7D_PAD_I2C3_SDA__GPIO4_IO13          0x7f
+				MX7D_PAD_I2C3_SCL__GPIO4_IO12          0x7f
+			>;
+		};
+
 		pinctrl_i2c4: i2c4grp {
 			fsl,pins = <
 				MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA		0x4000007f
@@ -565,6 +965,13 @@
 			>;
 		};
 
+		pinctrl_i2c4_gpio: i2c4grp_gpio {
+			fsl,pins = <
+				MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17		0x7f
+				MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16		0x7f
+			>;
+		};
+
 		pinctrl_lcdif: lcdifgrp {
 			fsl,pins = <
 				MX7D_PAD_LCD_DATA00__LCD_DATA0		0x79
@@ -595,10 +1002,46 @@
 				MX7D_PAD_LCD_ENABLE__LCD_ENABLE		0x79
 				MX7D_PAD_LCD_VSYNC__LCD_VSYNC		0x79
 				MX7D_PAD_LCD_HSYNC__LCD_HSYNC		0x79
-				MX7D_PAD_LCD_RESET__LCD_RESET		0x79
+				MX7D_PAD_LCD_RESET__GPIO3_IO4		0x80000000
 			>;
 		};
 
+		pinctrl_sai1: sai1grp {
+			fsl,pins = <
+				MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
+				MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK     0x1f
+				MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC	0x1f
+				MX7D_PAD_ENET1_COL__SAI1_TX_DATA0	0x30
+				MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0	0x1f
+			>;
+		};
+
+		pinctrl_sai2: sai2grp {
+			fsl,pins = <
+				MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK     0x1f
+				MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC     0x1f
+				MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0    0x30
+				MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0    0x1f
+			>;
+		};
+
+		pinctrl_sai3: sai3grp {
+			fsl,pins = <
+				MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK   0x1f
+				MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC     0x1f
+				MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0    0x30
+			>;
+		};
+
+		pinctrl_max17135: max17135grp-1 {
+			fsl,pins = <
+				MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31	0x80000000  /* pwrgood */
+				MX7D_PAD_I2C4_SCL__GPIO4_IO14		0x80000000  /* vcom_ctrl */
+				MX7D_PAD_EPDC_SDCE3__GPIO2_IO23		0x80000000  /* wakeup */
+				MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30	0x80000000  /* v3p3 */
+				MX7D_PAD_EPDC_SDCE2__GPIO2_IO22		0x80000000  /* pwr int */
+			>;
+		};
 		pinctrl_spi4: spi4grp {
 			fsl,pins = <
 				MX7D_PAD_GPIO1_IO09__GPIO1_IO9	0x59
@@ -613,6 +1056,22 @@
 			>;
 		};
 
+		pinctrl_sii902x: hdmigrp-1 {
+			fsl,pins = <
+				MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59
+			>;
+		};
+
+		pinctrl_sim1_1: sim1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B 0x77
+				MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD    0x77
+				MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN  0x77
+				MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK   0x73
+				MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD  0x73
+			>;
+		};
+
 		pinctrl_uart1: uart1grp {
 			fsl,pins = <
 				MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX	0x79
@@ -624,8 +1083,13 @@
 			fsl,pins = <
 				MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX	0x79
 				MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX	0x79
-				MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS	0x79
-				MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS	0x79
+			>;
+		};
+
+		pinctrl_uart5dte: uart5dtegrp {
+			fsl,pins = <
+				MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x79
+				MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x79
 			>;
 		};
 
@@ -638,6 +1102,15 @@
 			>;
 		};
 
+		pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
+			fsl,pins = <
+				MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x59 /* CD */
+				MX7D_PAD_SD1_WP__GPIO5_IO1		0x59 /* WP */
+				MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0x59 /* vmmc */
+				MX7D_PAD_GPIO1_IO08__SD1_VSELECT	0x59 /* VSELECT */
+			>;
+		};
+
 		pinctrl_usdhc1: usdhc1grp {
 			fsl,pins = <
 				MX7D_PAD_SD1_CMD__SD1_CMD		0x59
@@ -646,9 +1119,28 @@
 				MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
 				MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
 				MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
-				MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x59 /* CD */
-				MX7D_PAD_SD1_WP__GPIO5_IO1		0x59 /* WP */
-				MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0x59 /* vmmc */
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+			fsl,pins = <
+				MX7D_PAD_SD1_CMD__SD1_CMD		0x5a
+				MX7D_PAD_SD1_CLK__SD1_CLK		0x1a
+				MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5a
+				MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5a
+				MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5a
+				MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5a
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+			fsl,pins = <
+				MX7D_PAD_SD1_CMD__SD1_CMD		0x5b
+				MX7D_PAD_SD1_CLK__SD1_CLK		0x1b
+				MX7D_PAD_SD1_DATA0__SD1_DATA0		0x5b
+				MX7D_PAD_SD1_DATA1__SD1_DATA1		0x5b
+				MX7D_PAD_SD1_DATA2__SD1_DATA2		0x5b
+				MX7D_PAD_SD1_DATA3__SD1_DATA3		0x5b
 			>;
 		};
 
@@ -733,6 +1225,12 @@
 				MX7D_PAD_SD3_STROBE__SD3_STROBE		0x1b
 			>;
 		};
+
+		pinctrl_wifi: wifigrp {
+			fsl,pins = <
+				MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20	0x19 /* WL_HOST_WAKE */
+			>;
+		};
 	};
 };
 
@@ -743,6 +1241,21 @@
 };
 
 &iomuxc_lpsr {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_2 &pinctrl_usb_otg2_vbus_reg>;
+	
+	pinctrl_hog_2: hoggrp-2 {
+		fsl,pins = <
+			MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5	  0x14
+		>;
+	};
+
+	pinctrl_enet2_reg: enet2reggrp {
+		fsl,pins = <
+			MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4	0x80000000
+		>;
+	};
+
 	pinctrl_wdog: wdoggrp {
 		fsl,pins = <
 			MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B		0x74
@@ -760,4 +1273,11 @@
 			MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7	  0x14
 		>;
 	};
+
+	pinctrl_sai3_mclk: sai3grp_mclk {
+		fsl,pins = <
+			MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK	0x1f
+		>;
+	};
+
 };
diff --git a/arch/arm/dts/imx7d.dtsi b/arch/arm/dts/imx7d.dtsi
index 75566c780a4..0b54fa23428 100644
--- a/arch/arm/dts/imx7d.dtsi
+++ b/arch/arm/dts/imx7d.dtsi
@@ -42,19 +42,27 @@
  */
 
 #include "imx7s.dtsi"
+#include <dt-bindings/reset/imx7-reset.h>
 
 / {
 	aliases {
+		spi0 = &qspi1;
+		spi1 = &ecspi1;
+		spi2 = &ecspi2;
+		spi3 = &ecspi3;
+		spi4 = &ecspi4;
 		ethernet1 = &fec2;
+		usb1 = &usbotg2;
+		usbgadget1 = &usbg2;
 	};
+
 	cpus {
 		cpu0: cpu@0 {
-			operating-points = <
-				/* KHz	uV */
-				996000	1075000
-				792000	975000
-			>;
 			clock-frequency = <996000000>;
+			operating-points-v2 = <&cpu0_opp_table>;
+			#cooling-cells = <2>;
+			nvmem-cells = <&cpu_speed_grade>;
+			nvmem-cell-names = "speed_grade";
 		};
 
 		cpu1: cpu@1 {
@@ -62,10 +70,103 @@
 			device_type = "cpu";
 			reg = <1>;
 			clock-frequency = <996000000>;
+			operating-points-v2 = <&cpu0_opp_table>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	cpu0_opp_table: opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-792000000 {
+			opp-hz = /bits/ 64 <792000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <150000>;
+			opp-supported-hw = <0xf>, <0xf>;
+		};
+
+		opp-996000000 {
+			opp-hz = /bits/ 64 <996000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <150000>;
+			opp-supported-hw = <0xc>, <0xf>;
+		};
+
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1225000>;
+			clock-latency-ns = <150000>;
+			opp-supported-hw = <0x8>, <0xf>;
 		};
 	};
 
+	usbphynop2: usbphynop2 {
+		compatible = "usb-nop-xceiv";
+		clocks = <&clks IMX7D_USB_PHY2_CLK>;
+		clock-names = "main_clk";
+		#phy-cells = <0>;
+	};
+
 	soc {
+		busfreq {
+			compatible = "fsl,imx_busfreq";
+			fsl,max_ddr_freq = <533000000>;
+			clocks = <&clks IMX7D_OSC_24M_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_SRC>,
+				<&clks IMX7D_AHB_CHANNEL_ROOT_SRC>, <&clks IMX7D_PLL_SYS_PFD0_392M_CLK>,
+				<&clks IMX7D_DRAM_ROOT_SRC>, <&clks IMX7D_DRAM_ALT_ROOT_SRC>,
+				<&clks IMX7D_PLL_DRAM_MAIN_CLK>, <&clks IMX7D_DRAM_ALT_ROOT_CLK>,
+				<&clks IMX7D_PLL_SYS_PFD2_270M_CLK>, <&clks IMX7D_PLL_SYS_PFD1_332M_CLK>,
+				<&clks IMX7D_AHB_CHANNEL_ROOT_DIV>, <&clks IMX7D_MAIN_AXI_ROOT_DIV>;
+			clock-names = "osc", "axi_sel", "ahb_sel", "pfd0_392m", "dram_root",
+					"dram_alt_sel", "pll_dram", "dram_alt_root", "pfd2_270m",
+					"pfd1_332m", "ahb", "axi";
+			interrupts = <0 112 0x04>, <0 113 0x04>;
+			interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
+		};
+
+		ocrams_ddr: sram@900000 {
+			compatible = "fsl,ddr-lpm-sram";
+			reg = <0x900000 0x1000>;
+			clocks = <&clks IMX7D_OCRAM_CLK>;
+		};
+
+		ocram: sram@901000 {
+			compatible = "mmio-sram";
+			reg = <0x901000 0x1f000>;
+			clocks = <&clks IMX7D_OCRAM_CLK>;
+		};
+
+		ocrams: sram@180000 {
+			compatible = "fsl,lpm-sram";
+			reg = <0x180000 0x8000>;
+			clocks = <&clks IMX7D_OCRAM_S_CLK>;
+			status = "disabled";
+		};
+
+		ocram_optee {
+			compatible = "fsl,optee-lpm-sram";
+			reg = <0x180000 0x8000>;
+			overw_reg = <&ocrams_ddr 0x904000 0x1000>,
+					<&ocram 0x905000 0x1b000>,
+					<&ocrams 0x900000 0x4000>;
+			overw_clock = <&ocrams &clks IMX7D_OCRAM_CLK>;
+		};
+
+		ocrams_mf: sram-mf@900000 {
+			compatible = "fsl,mega-fast-sram";
+			reg = <0x900000 0x20000>;
+			clocks = <&clks IMX7D_OCRAM_CLK>;
+		};
+
 		etm@3007d000 {
 			compatible = "arm,coresight-etm3x", "arm,primecell";
 			reg = <0x3007d000 0x1000>;
@@ -80,16 +181,59 @@
 			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 			clock-names = "apb_pclk";
 
-			port {
-				etm1_out_port: endpoint {
-					remote-endpoint = <&ca_funnel_in_port1>;
+			out-ports {
+				port {
+					etm1_out_port: endpoint {
+						remote-endpoint = <&ca_funnel_in_port1>;
+					};
 				};
 			};
 		};
+
+		intc: interrupt-controller@31001000 {
+			compatible = "arm,cortex-a7-gic";
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			interrupt-parent = <&intc>;
+			reg = <0x31001000 0x1000>,
+			      <0x31002000 0x2000>,
+			      <0x31004000 0x2000>,
+			      <0x31006000 0x2000>;
+		};
 	};
 };
 
+/delete-node/&csi;
+/delete-node/&video_mux;
+
 &aips2 {
+	pcie_phy: pcie-phy@306d0000 {
+		  compatible = "fsl,imx7d-pcie-phy";
+		  reg = <0x306d0000 0x10000>;
+		  status = "disabled";
+	};
+
+	system_counter_rd: system-counter-rd@306a0000 {
+		compatible = "fsl,imx7d-system-counter-rd";
+		reg = <0x306a0000 0x10000>;
+		status = "disabled";
+	};
+
+	system_counter_cmp: system-counter-cmp@306b0000 {
+		compatible = "fsl,imx7d-system-counter-cmp";
+		reg = <0x306b0000 0x10000>;
+		status = "disabled";
+	};
+
+	system_counter_ctrl: system-counter-ctrl@306c0000 {
+		compatible = "fsl,imx7d-system-counter-ctrl";
+		reg = <0x306c0000 0x10000>;
+		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
 	epdc: epdc@306f0000 {
 		compatible = "fsl,imx7d-epdc";
 		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
@@ -97,11 +241,127 @@
 		clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>;
 		clock-names = "epdc_axi", "epdc_pix";
 		epdc-ram = <&gpr 0x4 30>;
+		qos = <&qosc>;
+		status = "disabled";
+	};
+
+	epxp: epxp@30700000 {
+		compatible = "fsl,imx7d-pxp-dma";
+		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+		reg = <0x30700000 0x10000>;
+		clocks = <&clks IMX7D_PXP_IPG_CLK>, <&clks IMX7D_PXP_AXI_CLK>;
+		clock-names = "pxp_ipg", "pxp_axi";
+		status = "disabled";
+	};
+
+	csi1: csi1@30710000 {
+		compatible = "fsl,imx7d-csi", "fsl,imx6s-csi";
+		reg = <0x30710000 0x10000>;
+		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clks IMX7D_CLK_DUMMY>,
+			<&clks IMX7D_CSI_MCLK_ROOT_CLK>,
+			<&clks IMX7D_CLK_DUMMY>;
+		clock-names = "disp-axi", "csi_mclk", "disp_dcic";
+		status = "disabled";
+	};
+
+	mipi_csi: mipi-csi@30750000 {
+		compatible = "fsl,imx7d-mipi-csi";
+		reg = <0x30750000 0x10000>;
+		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
+				<&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
+		clock-names = "mipi_clk", "phy_clk";
+		mipi-phy-supply = <&reg_1p0d>;
+		csis-phy-reset = <&src 0x28 2>;
+		bus-width = <4>;
+		status = "disabled";
+		/delete-node/ port@0;
+		/delete-node/ port@1;
+	};
+
+	mipi_dsi: mipi-dsi@30760000 {
+		compatible = "fsl,imx7d-mipi-dsi";
+		reg = <0x30760000 0x10000>;
+		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>,
+			<&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
+		clock-names = "mipi_cfg_clk", "mipi_pllref_clk";
+		power-domains = <&pgc_mipi_phy>;
 		status = "disabled";
 	};
+
+	qosc: qosc@307f0000 {
+		compatible = "fsl,imx7d-qosc", "syscon";
+		reg = <0x307f0000 0x4000>;
+	};
 };
 
 &aips3 {
+	mu: mu@30aa0000 {
+		compatible = "fsl,imx7d-mu", "fsl,imx6sx-mu";
+		reg = <0x30aa0000 0x10000>;
+		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clks IMX7D_MU_ROOT_CLK>;
+		clock-names = "mu";
+		#mbox-cells = <2>;
+	};
+
+	mu_lp: mu_lp@30aa0000 {
+		compatible = "fsl,imx7d-mu-lp", "fsl,imx6sx-mu-lp";
+		reg = <0x30aa0000 0x10000>;
+		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clks IMX7D_MU_ROOT_CLK>;
+		clock-names = "mu";
+		status = "okay";
+	};
+
+	sema4: sema4@30ac0000 {
+		compatible = "fsl,imx7d-sema4";
+		reg = <0x30ac0000 0x10000>;
+		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clks IMX7D_SEMA4_HS_ROOT_CLK>;
+		clock-names = "sema4";
+		status = "okay";
+	};
+
+	sim1: sim@30b90000 {
+		compatible = "fsl,imx7d-sim";
+		reg = <0x30b90000 0x10000>;
+		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clks IMX7D_SIM1_ROOT_CLK>;
+		clock-names = "sim";
+		status = "disabled";
+	};
+
+	qspi1: spi@30bb0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx7d-qspi";
+		reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
+		reg-names = "QuadSPI", "QuadSPI-memory";
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
+			<&clks IMX7D_QSPI_ROOT_CLK>;
+		clock-names = "qspi_en", "qspi";
+		status = "disabled";
+	};
+
+	sim2: sim@30ba0000 {
+		compatible = "fsl,imx7d-sim";
+		reg = <0x30ba0000 0x10000>;
+		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	usbg2: usbg2 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg2>;
+		status = "okay";
+	};
+
 	usbotg2: usb@30b20000 {
 		compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
 		reg = <0x30b20000 0x200>;
@@ -119,36 +379,92 @@
 		reg = <0x30b20200 0x200>;
 	};
 
-	usbphynop2: usbphynop2 {
-		compatible = "usb-nop-xceiv";
-		clocks = <&clks IMX7D_USB_PHY2_CLK>;
-		clock-names = "main_clk";
-	};
-
 	fec2: ethernet@30bf0000 {
 		compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
 		reg = <0x30bf0000 0x10000>;
-		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+		interrupt-names = "int0", "int1", "int2", "pps";
+		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 			<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
-			<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
-		clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+			<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
 			<&clks IMX7D_ENET_AXI_ROOT_CLK>,
 			<&clks IMX7D_ENET2_TIME_ROOT_CLK>,
 			<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
-			<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
+			<&clks IMX7D_ENET_PHY_REF_ROOT_DIV>;
 		clock-names = "ipg", "ahb", "ptp",
 			"enet_clk_ref", "enet_out";
-		fsl,num-tx-queues=<3>;
-		fsl,num-rx-queues=<3>;
+		fsl,num-tx-queues = <3>;
+		fsl,num-rx-queues = <3>;
+		status = "disabled";
+	};
+
+	pcie: pcie@33800000 {
+		compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
+		reg = <0x33800000 0x4000>,
+		      <0x4ff00000 0x80000>;
+		reg-names = "dbi", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x00 0xff>;
+		ranges = <0x81000000 0 0          0x4ff80000 0 0x00010000   /* downstream I/O */
+			  0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
+		num-lanes = <1>;
+		num-viewport = <4>;
+		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "msi";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0x7>;
+		/*
+		 * Reference manual lists pci irqs incorrectly
+		 * Real hardware ordering is same as imx6: D+MSI, C, B, A
+		 */
+		interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
+			 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
+			 <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
+		clock-names = "pcie", "pcie_bus", "pcie_phy";
+		assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
+				  <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
+		assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
+					 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+
+		fsl,max-link-speed = <2>;
+		power-domains = <&pgc_pcie_phy>;
+		resets = <&src IMX7_RESET_PCIEPHY>,
+			 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
+			 <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
+		reset-names = "pciephy", "apps", "turnoff";
+		fsl,imx7d-pcie-phy = <&pcie_phy>;
+		status = "disabled";
+	};
+
+	rpmsg: rpmsg{
+		compatible = "fsl,imx7d-rpmsg";
+		/* up to now, the following channels are used in imx rpmsg
+		 * - tx1/rx1: messages channel.
+		 * - general interrupt1: remote proc finish re-init rpmsg stack
+		 *   when A core is partition reset.
+		 */
+		mbox-names = "tx", "rx", "rxdb";
+		mboxes = <&mu 0 1
+			  &mu 1 1
+			  &mu 3 1>;
 		status = "disabled";
 	};
 };
 
-&ca_funnel_ports {
+&ca_funnel_in_ports {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
 	port@1 {
 		reg = <1>;
 		ca_funnel_in_port1: endpoint {
-			slave-mode;
 			remote-endpoint = <&etm1_out_port>;
 		};
 	};
diff --git a/arch/arm/dts/imx7s.dtsi b/arch/arm/dts/imx7s.dtsi
index 483824fc06e..9ec83f86da2 100644
--- a/arch/arm/dts/imx7s.dtsi
+++ b/arch/arm/dts/imx7s.dtsi
@@ -46,6 +46,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/imx7-reset.h>
 #include "imx7d-pinfunc.h"
 
 / {
@@ -55,10 +56,8 @@
 	 * The decompressor and also some bootloaders rely on a
 	 * pre-existing /chosen node to be available to insert the
 	 * command line and merge other ATAGS info.
-	 * Also for U-Boot there must be a pre-existing /memory node.
 	 */
 	chosen {};
-	memory { device_type = "memory"; };
 
 	aliases {
 		gpio0 = &gpio1;
@@ -82,12 +81,14 @@
 		serial4 = &uart5;
 		serial5 = &uart6;
 		serial6 = &uart7;
-		spi0 = &qspi1;
-		spi1 = &ecspi1;
-		spi2 = &ecspi2;
-		spi3 = &ecspi3;
-		spi4 = &ecspi4;
+		spi0 = &ecspi1;
+		spi1 = &ecspi2;
+		spi2 = &ecspi3;
+		spi3 = &ecspi4;
 		ethernet0 = &fec1;
+		usb0 = &usbotg1;
+		usbgadget0 = &usbg1;
+		video0 = &lcdif;
 	};
 
 	cpus {
@@ -144,9 +145,9 @@
 		 * non-configurable replicators don't show up on the
 		 * AMBA bus.  As such no need to add "arm,primecell"
 		 */
-		compatible = "arm,coresight-replicator";
+		compatible = "arm,coresight-static-replicator";
 
-		ports {
+		out-ports {
 			#address-cells = <1>;
 			#size-cells = <0>;
 				/* replicator output ports */
@@ -163,25 +164,26 @@
 					remote-endpoint = <&etr_in_port>;
 				};
 			};
+		};
 
-			/* replicator input port */
-			port@2 {
-				reg = <0>;
+		in-ports {
+			port {
 				replicator_in_port0: endpoint {
-					slave-mode;
 					remote-endpoint = <&etf_out_port>;
 				};
 			};
 		};
 	};
 
-	timer {
-		compatible = "arm,armv7-timer";
-		interrupt-parent = <&intc>;
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	tempmon: tempmon {
+		compatible = "fsl,imx7d-tempmon";
+		interrupt-parent = <&gpc>;
+		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,tempmon = <&anatop>;
+		nvmem-cells = <&tempmon_calib>,
+			<&tempmon_temp_grade>;
+		nvmem-cell-names = "calib", "temp_grade";
+		clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
 	};
 
 	soc {
@@ -192,33 +194,28 @@
 		ranges;
 
 		funnel@30041000 {
-			compatible = "arm,coresight-funnel", "arm,primecell";
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 			reg = <0x30041000 0x1000>;
 			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 			clock-names = "apb_pclk";
 
-			ca_funnel_ports: ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				/* funnel input ports */
-				port@0 {
-					reg = <0>;
+			ca_funnel_in_ports: in-ports {
+				port {
 					ca_funnel_in_port0: endpoint {
-						slave-mode;
 						remote-endpoint = <&etm0_out_port>;
 					};
 				};
 
-				/* funnel output port */
-				port@2 {
-					reg = <0>;
+				/* the other input ports are not connect to anything */
+			};
+
+			out-ports {
+				port {
 					ca_funnel_out_port0: endpoint {
 						remote-endpoint = <&hugo_funnel_in_port0>;
 					};
 				};
 
-				/* the other input ports are not connect to anything */
 			};
 		};
 
@@ -229,28 +226,33 @@
 			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 			clock-names = "apb_pclk";
 
-			port {
-				etm0_out_port: endpoint {
-					remote-endpoint = <&ca_funnel_in_port0>;
+			out-ports {
+				port {
+					etm0_out_port: endpoint {
+						remote-endpoint = <&ca_funnel_in_port0>;
+					};
 				};
 			};
 		};
 
+		caam_sm: caam-sm@100000 {
+			 compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm";
+			 reg = <0x100000 0x8000>;
+		};
+
 		funnel@30083000 {
-			compatible = "arm,coresight-funnel", "arm,primecell";
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 			reg = <0x30083000 0x1000>;
 			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 			clock-names = "apb_pclk";
 
-			ports {
+			in-ports {
 				#address-cells = <1>;
 				#size-cells = <0>;
 
-				/* funnel input ports */
 				port@0 {
 					reg = <0>;
 					hugo_funnel_in_port0: endpoint {
-						slave-mode;
 						remote-endpoint = <&ca_funnel_out_port0>;
 					};
 				};
@@ -258,18 +260,18 @@
 				port@1 {
 					reg = <1>;
 					hugo_funnel_in_port1: endpoint {
-						slave-mode; /* M4 input */
+						/* M4 input */
 					};
 				};
+				/* the other input ports are not connect to anything */
+			};
 
-				port@2 {
-					reg = <0>;
+			out-ports {
+				port {
 					hugo_funnel_out_port0: endpoint {
 						remote-endpoint = <&etf_in_port>;
 					};
 				};
-
-				/* the other input ports are not connect to anything */
 			};
 		};
 
@@ -279,20 +281,16 @@
 			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 			clock-names = "apb_pclk";
 
-			ports {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				port@0 {
-					reg = <0>;
+			in-ports {
+				port {
 					etf_in_port: endpoint {
-						slave-mode;
 						remote-endpoint = <&hugo_funnel_out_port0>;
 					};
 				};
+			};
 
-				port@1 {
-					reg = <0>;
+			out-ports {
+				port {
 					etf_out_port: endpoint {
 						remote-endpoint = <&replicator_in_port0>;
 					};
@@ -306,10 +304,11 @@
 			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 			clock-names = "apb_pclk";
 
-			port {
-				etr_in_port: endpoint {
-					slave-mode;
-					remote-endpoint = <&replicator_out_port1>;
+			in-ports {
+				port {
+					etr_in_port: endpoint {
+						remote-endpoint = <&replicator_out_port1>;
+					};
 				};
 			};
 		};
@@ -320,17 +319,18 @@
 			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
 			clock-names = "apb_pclk";
 
-			port {
-				tpiu_in_port: endpoint {
-					slave-mode;
-					remote-endpoint = <&replicator_out_port0>;
+			in-ports {
+				port {
+					tpiu_in_port: endpoint {
+						remote-endpoint = <&replicator_out_port0>;
+					};
 				};
 			};
 		};
 
 		intc: interrupt-controller@31001000 {
 			compatible = "arm,cortex-a7-gic";
-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
 			#interrupt-cells = <3>;
 			interrupt-controller;
 			interrupt-parent = <&intc>;
@@ -340,6 +340,17 @@
 			      <0x31006000 0x2000>;
 		};
 
+		timer {
+			compatible = "arm,armv7-timer";
+			arm,cpu-registers-not-fw-configured;
+			interrupt-parent = <&intc>;
+			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+				     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+				     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+				     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+			clock-frequency = <8000000>;
+		};
+
 		aips1: bus@30000000 {
 			compatible = "fsl,aips-bus", "simple-bus";
 			#address-cells = <1>;
@@ -472,16 +483,17 @@
 				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 				reg = <0x302d0000 0x10000>;
 				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX7D_CLK_DUMMY>,
-					 <&clks IMX7D_GPT1_ROOT_CLK>;
-				clock-names = "ipg", "per";
+				clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
+					<&clks IMX7D_GPT1_ROOT_CLK>,
+					<&clks IMX7D_GPT_3M_CLK>;
+				clock-names = "ipg", "per", "osc_per";
 			};
 
 			gpt2: gpt@302e0000 {
 				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 				reg = <0x302e0000 0x10000>;
 				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX7D_CLK_DUMMY>,
+				clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
 					 <&clks IMX7D_GPT2_ROOT_CLK>;
 				clock-names = "ipg", "per";
 				status = "disabled";
@@ -491,7 +503,7 @@
 				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 				reg = <0x302f0000 0x10000>;
 				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX7D_CLK_DUMMY>,
+				clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
 					 <&clks IMX7D_GPT3_ROOT_CLK>;
 				clock-names = "ipg", "per";
 				status = "disabled";
@@ -501,7 +513,7 @@
 				compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
 				reg = <0x30300000 0x10000>;
 				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX7D_CLK_DUMMY>,
+				clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
 					 <&clks IMX7D_GPT4_ROOT_CLK>;
 				clock-names = "ipg", "per";
 				status = "disabled";
@@ -522,8 +534,43 @@
 
 			gpr: iomuxc-gpr@30340000 {
 				compatible = "fsl,imx7d-iomuxc-gpr",
-					"fsl,imx6q-iomuxc-gpr", "syscon";
+					"fsl,imx6q-iomuxc-gpr", "syscon",
+					"simple-mfd";
 				reg = <0x30340000 0x10000>;
+
+				mux: mux-controller {
+					compatible = "mmio-mux";
+					#mux-control-cells = <0>;
+					mux-reg-masks = <0x14 0x00000010>;
+				};
+
+				video_mux: csi-mux {
+					compatible = "video-mux";
+					mux-controls = <&mux 0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					status = "disabled";
+
+					port@0 {
+						reg = <0>;
+					};
+
+					port@1 {
+						reg = <1>;
+
+						csi_mux_from_mipi_vc0: endpoint {
+							remote-endpoint = <&mipi_vc0_to_csi_mux>;
+						};
+					};
+
+					port@2 {
+						reg = <2>;
+
+						csi_mux_to_csi: endpoint {
+							remote-endpoint = <&csi_from_csi_mux>;
+						};
+					};
+				};
 			};
 
 			ocotp: ocotp-ctrl@30350000 {
@@ -540,16 +587,10 @@
 				tempmon_temp_grade: temp-grade@10 {
 					reg = <0x10 0x4>;
 				};
-			};
 
-			tempmon: tempmon {
-				compatible = "fsl,imx7d-tempmon";
-				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
-				fsl,tempmon =<&anatop>;
-				nvmem-cells = <&tempmon_calib>,
-					<&tempmon_temp_grade>;
-				nvmem-cell-names = "calib", "temp_grade";
-				clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
+				cpu_speed_grade: speed-grade@10 {
+					reg = <0x10 0x4>;
+				};
 			};
 
 			anatop: anatop@30360000 {
@@ -558,11 +599,8 @@
 				reg = <0x30360000 0x10000>;
 				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
-				#address-cells = <1>;
-				#size-cells = <0>;
 
-				reg_1p0d: regulator-vdd1p0d@30360210 {
-					reg = <0x30360210>;
+				reg_1p0d: regulator-vdd1p0d {
 					compatible = "fsl,anatop-regulator";
 					regulator-name = "vdd1p0d";
 					regulator-min-microvolt = <800000>;
@@ -575,6 +613,34 @@
 					anatop-max-voltage = <1200000>;
 					anatop-enable-bit = <0>;
 				};
+
+				reg_1p2: regulator-vdd1p2 {
+					compatible = "fsl,anatop-regulator";
+					regulator-name = "vdd1p2";
+					regulator-min-microvolt = <1100000>;
+					regulator-max-microvolt = <1300000>;
+					anatop-reg-offset = <0x220>;
+					anatop-vol-bit-shift = <8>;
+					anatop-vol-bit-width = <5>;
+					anatop-min-bit-val = <0x14>;
+					anatop-min-voltage = <1100000>;
+					anatop-max-voltage = <1300000>;
+					anatop-enable-bit = <0>;
+				};
+			};
+
+			irq_sec_vio: caam_secvio {
+				compatible = "fsl,imx6q-caam-secvio";
+				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+				jtag-tamper = "disabled";
+				watchdog-tamper = "enabled";
+				internal-boot-tamper = "enabled";
+				external-pin-tamper = "disabled";
+			};
+
+			caam_snvs: caam-snvs@30370000 {
+				compatible = "fsl,imx6q-caam-snvs";
+				reg = <0x30370000 0x10000>;
 			};
 
 			snvs: snvs@30370000 {
@@ -597,14 +663,18 @@
 					offset = <0x38>;
 					value = <0x60>;
 					mask = <0x60>;
+					status = "disabled";
 				};
 
 				snvs_pwrkey: snvs-powerkey {
 					compatible = "fsl,sec-v4.0-pwrkey";
 					regmap = <&snvs>;
 					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clks IMX7D_SNVS_CLK>;
+					clock-names = "snvs";
 					linux,keycode = <KEY_POWER>;
 					wakeup-source;
+					status = "disabled";
 				};
 			};
 
@@ -619,7 +689,7 @@
 			};
 
 			src: src@30390000 {
-				compatible = "fsl,imx7d-src", "syscon";
+				compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
 				reg = <0x30390000 0x10000>;
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 				#reset-cells = <1>;
@@ -632,17 +702,30 @@
 				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 				#interrupt-cells = <3>;
 				interrupt-parent = <&intc>;
+				fsl,mf-mix-wakeup-irq = <0x54010000 0xc00 0x0 0x1040640>;
 				#power-domain-cells = <1>;
 
 				pgc {
 					#address-cells = <1>;
 					#size-cells = <0>;
 
-					pgc_pcie_phy: pgc-power-domain@1 {
+					pgc_mipi_phy: power-domain@0 {
+						#power-domain-cells = <0>;
+						reg = <0>;
+						power-supply = <&reg_1p0d>;
+					};
+
+					pgc_pcie_phy: power-domain@1 {
 						#power-domain-cells = <0>;
 						reg = <1>;
 						power-supply = <&reg_1p0d>;
 					};
+
+					pgc_hsic_phy: power-domain@2 {
+						#power-domain-cells = <0>;
+						reg = <2>;
+						power-supply = <&reg_1p2>;
+					};
 				};
 			};
 		};
@@ -669,10 +752,11 @@
 				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX7D_ADC_ROOT_CLK>;
 				clock-names = "adc";
+				#io-channel-cells = <1>;
 				status = "disabled";
 			};
 
-			ecspi4: ecspi@30630000 {
+			ecspi4: spi@30630000 {
 				#address-cells = <1>;
 				#size-cells = <0>;
 				compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@@ -728,15 +812,67 @@
 				status = "disabled";
 			};
 
+			csi: csi@30710000 {
+				compatible = "fsl,imx7-csi";
+				reg = <0x30710000 0x10000>;
+				interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_CLK_DUMMY>,
+					 <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
+					 <&clks IMX7D_CLK_DUMMY>;
+				clock-names = "axi", "mclk", "dcic";
+				status = "disabled";
+
+				port {
+					csi_from_csi_mux: endpoint {
+						remote-endpoint = <&csi_mux_to_csi>;
+					};
+				};
+			};
+
 			lcdif: lcdif@30730000 {
 				compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
 				reg = <0x30730000 0x10000>;
 				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
-					<&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
-				clock-names = "pix", "axi";
+					 <&clks IMX7D_CLK_DUMMY>,
+					 <&clks IMX7D_CLK_DUMMY>;
+				clock-names = "pix", "axi", "disp_axi";
 				status = "disabled";
 			};
+
+			mipi_csi: mipi-csi@30750000 {
+				compatible = "fsl,imx7-mipi-csi2";
+				reg = <0x30750000 0x10000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+					 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
+					 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
+				clock-names = "pclk", "wrap", "phy";
+				power-domains = <&pgc_mipi_phy>;
+				phy-supply = <&reg_1p0d>;
+				resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
+				reset-names = "mrst";
+				status = "disabled";
+
+				port@0 {
+					reg = <0>;
+				};
+
+				port@1 {
+					reg = <1>;
+
+					mipi_vc0_to_csi_mux: endpoint {
+						remote-endpoint = <&csi_mux_from_mipi_vc0>;
+					};
+				};
+			};
+
+			ddrc: ddrc@307a0000 {
+				compatible = "fsl,imx7-ddrc";
+				reg = <0x307a0000 0x10000>;
+			};
 		};
 
 		aips3: bus@30800000 {
@@ -753,7 +889,7 @@
 				reg = <0x30800000 0x100000>;
 				ranges;
 
-				ecspi1: ecspi@30820000 {
+				ecspi1: spi@30820000 {
 					#address-cells = <1>;
 					#size-cells = <0>;
 					compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@@ -765,7 +901,7 @@
 					status = "disabled";
 				};
 
-				ecspi2: ecspi@30830000 {
+				ecspi2: spi@30830000 {
 					#address-cells = <1>;
 					#size-cells = <0>;
 					compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@@ -777,7 +913,7 @@
 					status = "disabled";
 				};
 
-				ecspi3: ecspi@30840000 {
+				ecspi3: spi@30840000 {
 					#address-cells = <1>;
 					#size-cells = <0>;
 					compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
@@ -808,6 +944,8 @@
 					clocks = <&clks IMX7D_UART2_ROOT_CLK>,
 						<&clks IMX7D_UART2_ROOT_CLK>;
 					clock-names = "ipg", "per";
+					dmas = <&sdma 24 4 0>, <&sdma 25 4 0>;
+					dma-names = "rx", "tx";
 					status = "disabled";
 				};
 
@@ -819,6 +957,8 @@
 					clocks = <&clks IMX7D_UART3_ROOT_CLK>,
 						<&clks IMX7D_UART3_ROOT_CLK>;
 					clock-names = "ipg", "per";
+					dmas = <&sdma 26 4 0>, <&sdma 27 4 0>;
+					dma-names = "rx", "tx";
 					status = "disabled";
 				};
 
@@ -905,6 +1045,7 @@
 				clocks = <&clks IMX7D_CLK_DUMMY>,
 					<&clks IMX7D_CAN1_ROOT_CLK>;
 				clock-names = "ipg", "per";
+				fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
 				status = "disabled";
 			};
 
@@ -915,6 +1056,7 @@
 				clocks = <&clks IMX7D_CLK_DUMMY>,
 					<&clks IMX7D_CAN2_ROOT_CLK>;
 				clock-names = "ipg", "per";
+				fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
 				status = "disabled";
 			};
 
@@ -966,6 +1108,8 @@
 				clocks = <&clks IMX7D_UART4_ROOT_CLK>,
 					<&clks IMX7D_UART4_ROOT_CLK>;
 				clock-names = "ipg", "per";
+				dmas = <&sdma 28 4 0>, <&sdma 29 4 0>;
+				dma-names = "rx", "tx";
 				status = "disabled";
 			};
 
@@ -977,6 +1121,8 @@
 				clocks = <&clks IMX7D_UART5_ROOT_CLK>,
 					<&clks IMX7D_UART5_ROOT_CLK>;
 				clock-names = "ipg", "per";
+				dmas = <&sdma 30 4 0>, <&sdma 31 4 0>;
+				dma-names = "rx", "tx";
 				status = "disabled";
 			};
 
@@ -988,6 +1134,8 @@
 				clocks = <&clks IMX7D_UART6_ROOT_CLK>,
 					<&clks IMX7D_UART6_ROOT_CLK>;
 				clock-names = "ipg", "per";
+				dmas = <&sdma 32 4 0>, <&sdma 33 4 0>;
+				dma-names = "rx", "tx";
 				status = "disabled";
 			};
 
@@ -999,9 +1147,37 @@
 				clocks = <&clks IMX7D_UART7_ROOT_CLK>,
 					<&clks IMX7D_UART7_ROOT_CLK>;
 				clock-names = "ipg", "per";
+				dmas = <&sdma 34 4 0>, <&sdma 35 4 0>;
+				dma-names = "rx", "tx";
 				status = "disabled";
 			};
 
+			mu0a: mailbox@30aa0000 {
+				compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
+				reg = <0x30aa0000 0x10000>;
+				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_MU_ROOT_CLK>;
+				#mbox-cells = <2>;
+				status = "disabled";
+			};
+
+			mu0b: mailbox@30ab0000 {
+				compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
+				reg = <0x30ab0000 0x10000>;
+				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clks IMX7D_MU_ROOT_CLK>;
+				#mbox-cells = <2>;
+				fsl,mu-side-b;
+				status = "disabled";
+			};
+
+			usbg1: usbg1 {
+				compatible = "fsl,imx27-usb-gadget";
+				dr_mode = "peripheral";
+				chipidea,usb = <&usbotg1>;
+				status = "okay";
+			};
+
 			usbotg1: usb@30b10000 {
 				compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
 				reg = <0x30b10000 0x200>;
@@ -1017,6 +1193,7 @@
 				compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
 				reg = <0x30b30000 0x200>;
 				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&pgc_hsic_phy>;
 				clocks = <&clks IMX7D_USB_CTRL_CLK>;
 				fsl,usbphy = <&usbphynop3>;
 				fsl,usbmisc = <&usbmisc3 0>;
@@ -1047,6 +1224,8 @@
 					<&clks IMX7D_USDHC1_ROOT_CLK>;
 				clock-names = "ipg", "ahb", "per";
 				bus-width = <4>;
+				fsl,tuning-step = <2>;
+				fsl,tuning-start-tap = <20>;
 				status = "disabled";
 			};
 
@@ -1059,6 +1238,8 @@
 					<&clks IMX7D_USDHC2_ROOT_CLK>;
 				clock-names = "ipg", "ahb", "per";
 				bus-width = <4>;
+				fsl,tuning-step = <2>;
+				fsl,tuning-start-tap = <20>;
 				status = "disabled";
 			};
 
@@ -1071,19 +1252,8 @@
 					<&clks IMX7D_USDHC3_ROOT_CLK>;
 				clock-names = "ipg", "ahb", "per";
 				bus-width = <4>;
-				status = "disabled";
-			};
-
-			qspi1: qspi@30bb0000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "fsl,imx7d-qspi";
-				reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
-				reg-names = "QuadSPI", "QuadSPI-memory";
-				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
-					<&clks IMX7D_QSPI_ROOT_CLK>;
-				clock-names = "qspi_en", "qspi";
+				fsl,tuning-step = <2>;
+				fsl,tuning-start-tap = <20>;
 				status = "disabled";
 			};
 
@@ -1091,8 +1261,8 @@
 				compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
 				reg = <0x30bd0000 0x10000>;
 				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX7D_SDMA_CORE_CLK>,
-					 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
+				clocks = <&clks IMX7D_IPG_ROOT_CLK>,
+					 <&clks IMX7D_SDMA_CORE_CLK>;
 				clock-names = "ipg", "ahb";
 				#dma-cells = <3>;
 				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
@@ -1106,15 +1276,15 @@
 					<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+				clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
 					<&clks IMX7D_ENET_AXI_ROOT_CLK>,
 					<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
 					<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
-					<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
+					<&clks IMX7D_ENET_PHY_REF_ROOT_DIV>;
 				clock-names = "ipg", "ahb", "ptp",
 					"enet_clk_ref", "enet_out";
-				fsl,num-tx-queues=<3>;
-				fsl,num-rx-queues=<3>;
+				fsl,num-tx-queues = <3>;
+				fsl,num-rx-queues = <3>;
 				status = "disabled";
 			};
 		};
diff --git a/arch/arm/dts/imx7ulp-10x10-val.dts b/arch/arm/dts/imx7ulp-10x10-val.dts
new file mode 100644
index 00000000000..47a4b56c043
--- /dev/null
+++ b/arch/arm/dts/imx7ulp-10x10-val.dts
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+	model = "NXP i.MX7ULP 10x10 val";
+	compatible = "fsl,imx7ulp-10x10-val", "fsl,imx7ulp", "Generic DT based system";
+
+	chosen {
+		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x40A60000,115200";
+		stdout-path = &lpuart6;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x60000000 0x40000000>;
+	};
+};
+
+&iomuxc1 {
+	pinctrl-names = "default";
+
+	imx7ulp-10x10-val {
+		pinctrl_lpuart6: lpuart6grp {
+			fsl,pins = <
+				IMX7ULP_PAD_PTE11__LPUART6_RX	0x400
+				IMX7ULP_PAD_PTE10__LPUART6_TX	0x400
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				IMX7ULP_PAD_PTE3__SDHC1_CMD	0x843
+				IMX7ULP_PAD_PTE2__SDHC1_CLK	0x843
+				IMX7ULP_PAD_PTE4__SDHC1_D3	0x843
+				IMX7ULP_PAD_PTE5__SDHC1_D2	0x843
+				IMX7ULP_PAD_PTE0__SDHC1_D1	0x843
+				IMX7ULP_PAD_PTE1__SDHC1_D0	0x843
+			>;
+		};
+
+		pinctrl_qspi1_1: qspi1grp_1 {
+			fsl,pins = <
+				IMX7ULP_PAD_PTB14__QSPIA_SS1_B   0x43 /* SS1 */
+				IMX7ULP_PAD_PTB8__QSPIA_SS0_B   0x43 /* SS0 */
+				IMX7ULP_PAD_PTB15__QSPIA_SCLK   0x43 /* SCLK */
+				IMX7ULP_PAD_PTB16__QSPIA_DATA3  0x43 /* D3 */
+				IMX7ULP_PAD_PTB17__QSPIA_DATA2  0x43 /* D2 */
+				IMX7ULP_PAD_PTB18__QSPIA_DATA1  0x43 /* D1 */
+				IMX7ULP_PAD_PTB19__QSPIA_DATA0  0x43 /* D0 */
+				IMX7ULP_PAD_PTB5__PTB5 0x20003
+			>;
+		};
+	};
+};
+
+&lpuart6 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart6>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1>;
+	non-removable;
+	status = "okay";
+};
+
+&qspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi1_1>;
+	status = "okay";
+
+	flash0: n25q512ax3@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,n25q512ax3", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+	};
+};
diff --git a/arch/arm/dts/imx7ulp-14x14-val.dts b/arch/arm/dts/imx7ulp-14x14-val.dts
new file mode 100644
index 00000000000..0b392cf71c7
--- /dev/null
+++ b/arch/arm/dts/imx7ulp-14x14-val.dts
@@ -0,0 +1,98 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+	model = "NXP i.MX7ULP 14x14 val";
+	compatible = "fsl,imx7ulp-14x14-val", "fsl,imx7ulp", "Generic DT based system";
+
+	chosen {
+		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200";
+		stdout-path = &lpuart4;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x60000000 0x40000000>;
+	};
+};
+
+&iomuxc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	imx7ulp-14x14-val {
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				IMX7ULP_PAD_PTC10__PTC10	0x30100
+				IMX7ULP_PAD_PTC1__PTC1		0x20100
+			>;
+		};
+
+		pinctrl_lpuart4: lpuart4grp {
+			fsl,pins = <
+				IMX7ULP_PAD_PTC3__LPUART4_RX	0x400
+				IMX7ULP_PAD_PTC2__LPUART4_TX	0x400
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				IMX7ULP_PAD_PTE3__SDHC1_CMD	0x843
+				IMX7ULP_PAD_PTE2__SDHC1_CLK	0x843
+				IMX7ULP_PAD_PTE4__SDHC1_D3	0x843
+				IMX7ULP_PAD_PTE5__SDHC1_D2	0x843
+				IMX7ULP_PAD_PTE0__SDHC1_D1	0x843
+				IMX7ULP_PAD_PTE1__SDHC1_D0	0x843
+			>;
+		};
+		pinctrl_qspi1_1: qspi1grp_1 {
+			fsl,pins = <
+				IMX7ULP_PAD_PTB8__QSPIA_SS0_B   0x43 /* SS0 */
+				IMX7ULP_PAD_PTB15__QSPIA_SCLK   0x43 /* SCLK */
+				IMX7ULP_PAD_PTB9__QSPIA_DQS     0x43 /* DQS */
+				IMX7ULP_PAD_PTB16__QSPIA_DATA3  0x43 /* D3 */
+				IMX7ULP_PAD_PTB17__QSPIA_DATA2  0x43 /* D2 */
+				IMX7ULP_PAD_PTB18__QSPIA_DATA1  0x43 /* D1 */
+				IMX7ULP_PAD_PTB19__QSPIA_DATA0  0x43 /* D0 */
+				IMX7ULP_PAD_PTB12__PTB12 0x20003
+			>;
+		};
+	};
+};
+
+&lpuart4 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart4>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1>;
+	non-removable;
+	status = "okay";
+};
+
+&qspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi1_1>;
+	status = "okay";
+
+	flash0: mt35xu512aba@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "micron,mt35xu512aba", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+	};
+};
\ No newline at end of file
diff --git a/arch/arm/dts/imx7ulp-evk-emmc.dts b/arch/arm/dts/imx7ulp-evk-emmc.dts
new file mode 100644
index 00000000000..9407d198c38
--- /dev/null
+++ b/arch/arm/dts/imx7ulp-evk-emmc.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx7ulp-evk-qspi.dts"
+
+/* To support eMMC HS200/HS400, need to do the following reowrk:
+ * 1,remove TF sd slot, replace eMMC chip
+ * 2,fix eMMC I/O voltage to 1.8v, remove R183, short TP3 and TP89
+ * 3,add R107, make eMMC boot work
+ */
+&usdhc0 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc0_8bit>;
+	pinctrl-1 = <&pinctrl_usdhc0_8bit>;
+	pinctrl-2 = <&pinctrl_usdhc0_8bit>;
+	pinctrl-3 = <&pinctrl_usdhc0_8bit>;
+	non-removable;
+	bus-width = <8>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx7ulp-evk-qspi.dts b/arch/arm/dts/imx7ulp-evk-qspi.dts
new file mode 100644
index 00000000000..982a172d568
--- /dev/null
+++ b/arch/arm/dts/imx7ulp-evk-qspi.dts
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx7ulp-evk.dts"
+
+&qspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi1_1>;
+	status = "okay";
+
+	flash0: mx25r6435f@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "macronix,mx25r6435f", "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+	};
+};
+
+&iomuxc {
+	status = "okay";
+};
+
+&iomuxc {
+	imx7ulp-evk {
+		pinctrl_qspi1_1: qspi1grp_1 {
+			fsl,pins = <
+				IMX7ULP_PAD_PTB7__QSPIA_SS1_B    0x43 /* SS1 */
+				IMX7ULP_PAD_PTB8__QSPIA_SS0_B    0x43 /* SS0 */
+				IMX7ULP_PAD_PTB15__QSPIA_SCLK    0x43 /* SCLK */
+				IMX7ULP_PAD_PTB9__QSPIA_DQS      0x43 /* DQS */
+				IMX7ULP_PAD_PTB16__QSPIA_DATA3   0x43 /* D3 */
+				IMX7ULP_PAD_PTB17__QSPIA_DATA2   0x43 /* D2 */
+				IMX7ULP_PAD_PTB18__QSPIA_DATA1   0x43 /* D1 */
+				IMX7ULP_PAD_PTB19__QSPIA_DATA0   0x43 /* D0 */
+			>;
+		};
+	};
+};
+
diff --git a/arch/arm/dts/imx7ulp-evk.dts b/arch/arm/dts/imx7ulp-evk.dts
index 8f6a935e241..f21942f9da6 100644
--- a/arch/arm/dts/imx7ulp-evk.dts
+++ b/arch/arm/dts/imx7ulp-evk.dts
@@ -31,7 +31,7 @@
 		reg = <0x60000000 0x40000000>;
 	};
 
-	backlight {
+	backlight: backlight {
 		compatible = "gpio-backlight";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_backlight>;
@@ -47,6 +47,25 @@
 		#reset-cells = <0>;
 	};
 
+	dsi_host: dsi-host {
+		compatible = "northwest,mipi-dsi";
+		status = "okay";
+	};
+
+	hx8394f_panel {
+		compatible = "rocktech,hx8394f";
+		himax,dsi-lanes = <2>;
+		reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
+		backlight = <&backlight>;
+		status = "okay";
+
+		port {
+			hx8394f_from_dsim: endpoint {
+				remote-endpoint = <&dsim_to_hx8394f>;
+			};
+		};
+	};
+
 	regulators {
 		compatible = "simple-bus";
 		#address-cells = <1>;
@@ -240,7 +259,7 @@
 				IMX7ULP_PAD_PTF16__LPSPI3_SIN	0x0
 				IMX7ULP_PAD_PTF17__LPSPI3_SOUT	0x0
 				IMX7ULP_PAD_PTF18__LPSPI3_SCK	0x0
-				IMX7ULP_PAD_PTF19__LPSPI3_PCS0	0x0
+				IMX7ULP_PAD_PTF19__PTF19	0x0
 			>;
 		};
 
@@ -285,32 +304,21 @@
 };
 
 &lcdif {
+	#address-cells = <1>;
+	#size-cells = <0>;
 	status = "okay";
-	disp-dev = "mipi_dsi_northwest";
 	display = <&display0>;
 
 	display0: display@0 {
-		bits-per-pixel = <16>;
+		bits-per-pixel = <24>;
 		bus-width = <24>;
+	};
 
-		display-timings {
-			native-mode = <&timing0>;
-			timing0: timing0 {
-			clock-frequency = <9200000>;
-			hactive = <480>;
-			vactive = <272>;
-			hfront-porch = <8>;
-			hback-porch = <4>;
-			hsync-len = <41>;
-			vback-porch = <2>;
-			vfront-porch = <4>;
-			vsync-len = <10>;
-
-			hsync-active = <0>;
-			vsync-active = <0>;
-			de-active = <1>;
-			pixelclk-active = <0>;
-			};
+	lcdif_disp0: port@0 {
+		reg = <0>;
+
+		lcdif_to_dsim: endpoint {
+			remote-endpoint = <&dsim_from_lcdif>;
 		};
 	};
 };
@@ -335,21 +343,31 @@
 	#size-cells = <0>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_lpspi3>;
+	cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>, <0>, <0>, <0>;
+	spi-max-frequency = <1000000>;
 	status = "okay";
-
-	spidev0: spi@0 {
-		reg = <0>;
-		compatible = "rohm,dh2228fv";
-		spi-max-frequency = <1000000>;
-	};
 };
 
 &mipi_dsi {
+	#address-cells = <1>;
+	#size-cells = <0>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_mipi_dsi_reset>;
 	lcd_panel = "TRULY-WVGA-TFT3P5581E";
 	resets = <&mipi_dsi_reset>;
 	status = "okay";
+
+	port@0 {
+		dsim_from_lcdif: endpoint {
+			remote-endpoint = <&lcdif_to_dsim>;
+		};
+	};
+
+	port@1 {
+		dsim_to_hx8394f: endpoint {
+			remote-endpoint = <&hx8394f_from_dsim>;
+		};
+	};
 };
 
 &lpuart4 { /* console */
diff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi
index 7bcd2cc3469..34274ff6783 100644
--- a/arch/arm/dts/imx7ulp.dtsi
+++ b/arch/arm/dts/imx7ulp.dtsi
@@ -1,5 +1,6 @@
 /*
  * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -30,11 +31,13 @@
 		serial3 = &lpuart7;
 		usbphy0 = &usbphy1;
 		usb0 = &usbotg1;
+		usbgadget0 = &usbg1;
 		i2c4 = &lpi2c4;
 		i2c5 = &lpi2c5;
 		i2c6 = &lpi2c6;
 		i2c7 = &lpi2c7;
 		spi0 = &qspi1;
+		spi3 = &lpspi3;
 	};
 
 	cpus {
@@ -198,6 +201,29 @@
 			};
 		};
 
+		crypto: crypto@40240000 {
+			compatible = "fsl,sec-v4.0";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x40240000 0x10000>;
+			ranges = <0 0x40240000 0x10000>;
+			clocks = <&clks IMX7ULP_CLK_CAAM>,
+				 <&clks IMX7ULP_CLK_NIC1_BUS_DIV>;
+			clock-names = "aclk", "ipg";
+
+			sec_jr0: jr@1000 {
+				compatible = "fsl,sec-v4.0-job-ring";
+				reg = <0x1000 0x1000>;
+				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr1: jr@2000 {
+				compatible = "fsl,sec-v4.0-job-ring";
+				reg = <0x2000 0x1000>;
+				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
 		tpm5: tpm@40260000 {
 			compatible = "fsl,imx7ulp-tpm";
 			reg = <0x40260000 0x1000>;
@@ -244,8 +270,9 @@
 			compatible = "fsl,imx7ulp-spi";
 			reg = <0x40290000 0x10000>;
 			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clks IMX7ULP_CLK_LPSPI2>;
-			clock-names = "ipg";
+			clocks = <&clks IMX7ULP_CLK_LPSPI2>,
+				 <&clks IMX7ULP_CLK_DUMMY>;
+			clock-names = "per", "ipg";
 			assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>;
 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
 			assigned-clock-rates = <48000000>;
@@ -256,8 +283,9 @@
 			compatible = "fsl,imx7ulp-spi";
 			reg = <0x402A0000 0x10000>;
 			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clks IMX7ULP_CLK_LPSPI3>;
-			clock-names = "ipg";
+			clocks = <&clks IMX7ULP_CLK_LPSPI3>,
+				 <&clks IMX7ULP_CLK_DUMMY>;
+			clock-names = "per", "ipg";
 			assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>;
 			assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>;
 			assigned-clock-rates = <48000000>;
@@ -290,6 +318,13 @@
 			status = "disabled";
 		};
 
+		usbg1: usbg1 {
+			compatible = "fsl,imx27-usb-gadget";
+			dr_mode = "peripheral";
+			chipidea,usb = <&usbotg1>;
+			status = "okay";
+		};
+
 		usbotg1: usb@40330000 {
 			compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb",
 				"fsl,imx27-usb";
@@ -480,6 +515,9 @@
 			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clks IMX7ULP_CLK_DSI>;
 			clock-names = "mipi_dsi_clk";
+			data-lanes-num = <2>;
+			phy-ref-clkfreq = <24000000>;
+			max-data-rate  = <800000000>;
 			sim = <&sim>;
 			status = "disabled";
 		};
diff --git a/arch/arm/dts/imx8mm-ab2-u-boot.dtsi b/arch/arm/dts/imx8mm-ab2-u-boot.dtsi
new file mode 100644
index 00000000000..c0b93bf9c1e
--- /dev/null
+++ b/arch/arm/dts/imx8mm-ab2-u-boot.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mm-evk-u-boot.dtsi"
+
+/ {
+	usbg2: usbg2 {
+		status = "disabled";
+	};
+};
+
+&fec1 {
+	phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+};
+
+&usbotg1 {
+	status = "okay";
+	extcon = <&ptn5150>;
+};
diff --git a/arch/arm/dts/imx8mm-ab2.dts b/arch/arm/dts/imx8mm-ab2.dts
new file mode 100644
index 00000000000..6d3667ef9a9
--- /dev/null
+++ b/arch/arm/dts/imx8mm-ab2.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mm-evk.dts"
+#include "imx8mm-ab2.dtsi"
+
+/ {
+	model = "NXP i.MX8MM Audio board 2.0";
+	compatible = "fsl,imx8mm-ab2", "fsl,imx8mm";
+};
diff --git a/arch/arm/dts/imx8mm-ab2.dtsi b/arch/arm/dts/imx8mm-ab2.dtsi
new file mode 100644
index 00000000000..d945d27c54b
--- /dev/null
+++ b/arch/arm/dts/imx8mm-ab2.dtsi
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 NXP
+ */
+
+/ {
+	/delete-node/ audio-codec;
+	/delete-node/ dsi-host;
+	/delete-node/ ir-receiver;
+	/delete-node/ rm67199_panel;
+	/delete-node/ sound-wm8524;
+
+	leds {
+		panel {
+			label = "green:panel";
+			gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+	};
+
+	reg_ab2_ana_pwr: regulator-ab2-ana-pwr {
+		compatible = "regulator-fixed";
+		regulator-name = "ANA_12V0";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ab2_ana_pwr>;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&buck5_reg>;
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_5V0";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+		vin-supply = <&buck5_reg>;
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&fec1 {
+	mdio {
+		ethphy0: ethernet-phy@0 {
+			reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+			max-speed = <100>;
+		};
+	};
+};
+
+&i2c2 {
+	/delete-node/ adv7535@3d;
+	/delete-node/ tcpc@50;
+
+	pca6408_2: gpio@20 {
+		compatible = "ti,tca6408";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	ptn5150: tcpc@1d {
+		compatible = "nxp,ptn5150";
+		reg = <0x1d>;
+		status = "okay";
+
+		port {
+			typec1_dr_sw: endpoint {
+				remote-endpoint = <&usb1_drd_sw>;
+			};
+		};
+
+		typec1_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			power-role = "dual";
+			data-role = "dual";
+			try-power-role = "sink";
+			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+				PDO_VAR(5000, 20000, 3000)>;
+			op-sink-microwatt = <15000000>;
+			self-powered;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3
+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x19	/* ENET_PHY_RST_B */
+			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x19	/* ENET_PHY_INT_B */
+		>;
+	};
+
+	pinctrl_ab2_ana_pwr: ab2anapwrgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x41
+		>;
+	};
+
+	pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x41
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4
+		>;
+	};
+};
+
+&lcdif {
+	status = "disabled";
+};
+
+&mipi_dsi {
+	status = "disabled";
+
+	/delete-node/ port@1;
+	/delete-node/ port@2;
+};
+
+&sai3 {
+	status = "disabled";
+};
+
+&usbotg1 {
+	extcon = <&ptn5150>;
+};
+
+&usdhc2 {
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/imx8mm-ddr3l-val.dts b/arch/arm/dts/imx8mm-ddr3l-val.dts
new file mode 100644
index 00000000000..1edbddc8572
--- /dev/null
+++ b/arch/arm/dts/imx8mm-ddr3l-val.dts
@@ -0,0 +1,393 @@
+// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright 2018 NXP
+  */
+
+/dts-v1/;
+
+#include "imx8mm.dtsi"
+
+/ {
+	model = "NXP i.MX8MM DDR3L Validation board";
+	compatible = "fsl,imx8mm-val", "fsl,imx8mm";
+
+	chosen {
+		bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
+		stdout-path = &uart2;
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	imx8mm-val {
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3
+				MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO	0x23
+				MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK	0x4000001f
+				MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x56
+				MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x56
+				MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x56
+				MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x56
+				MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER	0x56
+				MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x56
+				MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x56
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
+				MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
+				MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
+			>;
+		};
+
+		pinctrl_i2c3: i2c3grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
+				MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
+			>;
+		};
+
+		pinctrl_i2c1_gpio: i2c1grp-gpio {
+			fsl,pins = <
+				MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14        		0x1c3
+				MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15        	0x1c3
+			>;
+		};
+
+		pinctrl_i2c2_gpio: i2c2grp-gpio {
+			fsl,pins = <
+				MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16        		0x1c3
+				MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17        	0x1c3
+			>;
+		};
+
+		pinctrl_i2c3_gpio: i2c3grp-gpio {
+			fsl,pins = <
+				MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18        		0x1c3
+				MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19        	0x1c3
+			>;
+		};
+
+		pinctrl_uart2: uart2grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
+				MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grpgpio {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
+				MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
+				MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
+				MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
+				MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
+				MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
+				MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
+				MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
+				MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
+				MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
+				MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
+				MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
+				MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
+				MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
+				MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
+				MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
+				MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
+				MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
+				MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+			>;
+		};
+
+		pinctrl_gpmi_nand_1: gpmi-nand-1 {
+			fsl,pins = <
+				MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE		0x00000096
+				MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B		0x00000096
+				MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE		0x00000096
+				MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00		0x00000096
+				MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01		0x00000096
+				MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02		0x00000096
+				MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03		0x00000096
+				MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04		0x00000096
+				MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05		0x00000096
+				MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06		0x00000096
+				MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07		0x00000096
+				MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B		0x00000096
+				MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B	0x00000056
+				MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B		0x00000096
+				MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B		0x00000096
+			>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: bd71837@4b {
+		reg = <0x4b>;
+		compatible = "rohm,bd71837";
+
+		gpo {
+			rohm,drv = <0x0C>;	/* 0b0000_1100 all gpos with cmos output mode */
+		};
+
+		regulators {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			bd71837,pmic-buck2-uses-i2c-dvs;
+			bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
+
+			buck1_reg: regulator@0 {
+				reg = <0>;
+				regulator-compatible = "buck1";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <1250>;
+			};
+
+			buck2_reg: regulator@1 {
+				reg = <1>;
+				regulator-compatible = "buck2";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <1250>;
+			};
+
+			buck3_reg: regulator@2 {
+				reg = <2>;
+				regulator-compatible = "buck3";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+			};
+
+			buck4_reg: regulator@3 {
+				reg = <3>;
+				regulator-compatible = "buck4";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+			};
+
+			buck5_reg: regulator@4 {
+				reg = <4>;
+				regulator-compatible = "buck5";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6_reg: regulator@5 {
+				reg = <5>;
+				regulator-compatible = "buck6";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck7_reg: regulator@6 {
+				reg = <6>;
+				regulator-compatible = "buck7";
+				regulator-min-microvolt = <1605000>;
+				regulator-max-microvolt = <1995000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck8_reg: regulator@7 {
+				reg = <7>;
+				regulator-compatible = "buck8";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1_reg: regulator@8 {
+				reg = <8>;
+				regulator-compatible = "ldo1";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2_reg: regulator@9 {
+				reg = <9>;
+				regulator-compatible = "ldo2";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3_reg: regulator@10 {
+				reg = <10>;
+				regulator-compatible = "ldo3";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4_reg: regulator@11 {
+				reg = <11>;
+				regulator-compatible = "ldo4";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5_reg: regulator@12 {
+				reg = <12>;
+				regulator-compatible = "ldo5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			ldo6_reg: regulator@13 {
+				reg = <13>;
+				regulator-compatible = "ldo6";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo7_reg: regulator@14 {
+				reg = <14>;
+				regulator-compatible = "ldo7";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+	};
+};
+
+&uart2 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&usbotg1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usbotg2 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	non-removable;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "okay";
+	nand-on-flash-bbt;
+	fsl,use-minimum-ecc;
+};
+
+&A53_0 {
+	arm-supply = <&buck2_reg>;
+};
diff --git a/arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi b/arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi
new file mode 100644
index 00000000000..27daf58a225
--- /dev/null
+++ b/arch/arm/dts/imx8mm-ddr4-ab2-u-boot.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mm-ddr4-evk-u-boot.dtsi"
+
+/ {
+	usbg2: usbg2 {
+		status = "disabled";
+	};
+};
+
+&fec1 {
+	phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+};
+
+&usbotg1 {
+	status = "okay";
+	extcon = <&ptn5150>;
+};
diff --git a/arch/arm/dts/imx8mm-ddr4-ab2.dts b/arch/arm/dts/imx8mm-ddr4-ab2.dts
new file mode 100644
index 00000000000..418db5789ee
--- /dev/null
+++ b/arch/arm/dts/imx8mm-ddr4-ab2.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mm-ddr4-evk.dts"
+#include "imx8mm-ab2.dtsi"
+
+/ {
+	model = "NXP i.MX8MM DDR4 Audio board 2.0";
+	compatible = "fsl,imx8mm-ab2", "fsl,imx8mm";
+};
diff --git a/arch/arm/dts/imx8mm-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-ddr4-evk-u-boot.dtsi
new file mode 100644
index 00000000000..e66bd5830dd
--- /dev/null
+++ b/arch/arm/dts/imx8mm-ddr4-evk-u-boot.dtsi
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mm-u-boot.dtsi"
+
+/ {
+	chosen {
+		bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
+	};
+
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog1>;
+		u-boot,dm-spl;
+	};
+
+	aliases {
+		usbgadget0 = &usbg1;
+		usbgadget1 = &usbg2;
+	};
+
+	usbg1: usbg1 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg1>;
+		status = "okay";
+	};
+
+	usbg2: usbg2 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg2>;
+		status = "okay";
+	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+};
+
+&reg_usdhc2_vmmc {
+	u-boot,off-on-delay-us = <20000>;
+	u-boot,dm-spl;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+	u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+};
+
+&gpio3 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&gpio5 {
+	u-boot,dm-spl;
+};
+
+&uart2 {
+	u-boot,dm-spl;
+};
+
+&usdhc1 {
+	u-boot,dm-spl;
+	assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
+	assigned-clock-rates = <400000000>;
+	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
+	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
+	assigned-clock-rates = <400000000>;
+	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
+	fsl,signal-voltage-switch-extra-delay-ms = <8>;
+};
+
+&i2c1 {
+	u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
+	u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
+	u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+	u-boot,dm-spl;
+};
+
+&fec1 {
+	phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+};
+
+&ethphy0 {
+	vddio0: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
+
+&wdog1 {
+	u-boot,dm-spl;
+};
+
+&usbotg1 {
+	status = "okay";
+	extcon = <&ptn5110>;
+};
+
+&lcdif {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
+};
+
+&mipi_dsi {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
+};
+
+&blob_1d_imem {
+			filename = "ddr4_imem_1d.bin";
+};
+
+&blob_1d_dmem {
+			filename = "ddr4_dmem_1d.bin";
+};
+
+&blob_2d_imem {
+			filename = "ddr4_imem_2d.bin";
+};
+
+&blob_2d_dmem {
+			filename = "ddr4_dmem_2d.bin";
+};
diff --git a/arch/arm/dts/imx8mm-ddr4-evk.dts b/arch/arm/dts/imx8mm-ddr4-evk.dts
new file mode 100644
index 00000000000..1000977d68f
--- /dev/null
+++ b/arch/arm/dts/imx8mm-ddr4-evk.dts
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright 2018 NXP
+  */
+
+/dts-v1/;
+
+#include "imx8mm-evk.dtsi"
+
+/ {
+	model = "NXP i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board";
+	compatible = "fsl,imx8mm-ddr4-evk", "fsl,imx8mm";
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand>;
+	nand-on-flash-bbt;
+	fsl,use-minimum-ecc;
+	status = "okay";
+};
+
+/delete-node/ &pmic;
+
+&i2c1 {
+	pmic: pmic@4b {
+		compatible = "rohm,bd71847";
+		reg = <0x4b>;
+		pinctrl-0 = <&pinctrl_pmic>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <3 GPIO_ACTIVE_LOW>;
+		rohm,reset-snvs-powered;
+
+		regulators {
+			buck1_reg: BUCK1 {
+				regulator-name = "BUCK1";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <1250>;
+			};
+
+			buck2_reg: BUCK2 {
+				regulator-name = "BUCK2";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <1250>;
+				rohm,dvs-run-voltage = <1000000>;
+				rohm,dvs-idle-voltage = <900000>;
+			};
+
+			buck3_reg: BUCK3 {
+				// BUCK5 in datasheet
+				regulator-name = "BUCK3";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck4_reg: BUCK4 {
+				// BUCK6 in datasheet
+				regulator-name = "BUCK4";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5_reg: BUCK5 {
+				// BUCK7 in datasheet
+				regulator-name = "BUCK5";
+				regulator-min-microvolt = <1605000>;
+				regulator-max-microvolt = <1995000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6_reg: BUCK6 {
+				// BUCK8 in datasheet
+				regulator-name = "BUCK6";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1_reg: LDO1 {
+				regulator-name = "LDO1";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2_reg: LDO2 {
+				regulator-name = "LDO2";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3_reg: LDO3 {
+				regulator-name = "LDO3";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4_reg: LDO4 {
+				regulator-name = "LDO4";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo6_reg: LDO6 {
+				regulator-name = "LDO6";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl_gpmi_nand: gpmi-nand {
+		fsl,pins = <
+			MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE		0x00000096
+			MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B		0x00000096
+			MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B		0x00000096
+			MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE		0x00000096
+			MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00		0x00000096
+			MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01		0x00000096
+			MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02		0x00000096
+			MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03		0x00000096
+			MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04		0x00000096
+			MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05		0x00000096
+			MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06		0x00000096
+			MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07		0x00000096
+			MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B		0x00000096
+			MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B	0x00000056
+			MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B		0x00000096
+			MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B		0x00000096
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8mm-ddr4-val.dts b/arch/arm/dts/imx8mm-ddr4-val.dts
new file mode 100644
index 00000000000..de0b8da4e8b
--- /dev/null
+++ b/arch/arm/dts/imx8mm-ddr4-val.dts
@@ -0,0 +1,530 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "imx8mm.dtsi"
+
+/ {
+	model = "NXP i.MX8MM DDR4 Validation board";
+	compatible = "fsl,imx8mm-val", "fsl,imx8mm";
+
+	chosen {
+		bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
+		stdout-path = &uart2;
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		startup-delay-us = <100>;
+		off-on-delay-us = <12000>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	imx8mm-val {
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3
+				MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
+				MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
+				MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
+				MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
+				MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
+				MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
+				MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
+				MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
+				MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
+				MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
+				MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
+				MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+				MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+				MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19
+			>;
+		};
+
+		pinctrl_flexspi: flexspigrp {
+			fsl,pins = <
+				MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4
+				MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84
+
+				MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
+				MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
+				MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
+				MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
+				MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
+				MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
+			>;
+		};
+
+		pinctrl_i2c3: i2c3grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
+				MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
+			>;
+		};
+
+		pinctrl_i2c1_gpio: i2c1grp-gpio {
+			fsl,pins = <
+				MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14        		0x1c3
+				MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15        	0x1c3
+			>;
+		};
+
+		pinctrl_i2c2_gpio: i2c2grp-gpio {
+			fsl,pins = <
+				MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16        		0x1c3
+				MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17        	0x1c3
+			>;
+		};
+
+		pinctrl_i2c3_gpio: i2c3grp-gpio {
+			fsl,pins = <
+				MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18        		0x1c3
+				MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19        	0x1c3
+			>;
+		};
+
+		pinctrl_pmic: pmicirq {
+			fsl,pins = <
+				MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41
+			>;
+		};
+
+		pinctrl_uart2: uart1grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x49
+				MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x49
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grpgpio {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
+				MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
+				MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
+				MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
+				MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
+				MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
+				MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
+				MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
+				MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
+				MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
+				MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
+				MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
+				MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
+				MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
+				MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
+				MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
+				MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
+				MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
+				MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000190
+				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
+				MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
+				MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
+				MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
+				MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
+				MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
+				MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
+				MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
+				MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
+				MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x190
+			>;
+		};
+
+		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+			fsl,pins = <
+				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000194
+				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
+				MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
+				MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
+				MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
+				MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
+				MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
+				MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
+				MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
+				MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
+				MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x194
+			>;
+		};
+
+		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+			fsl,pins = <
+				MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000196
+				MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
+				MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
+				MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
+				MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
+				MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
+				MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
+				MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
+				MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
+				MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
+				MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x196
+			>;
+		};
+
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
+			>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: bd71837@4b {
+		reg = <0x4b>;
+		compatible = "rohm,bd71837";
+		/* PMIC BD71837 PMIC_nINT GPIO1_IO3 */
+		pinctrl-0 = <&pinctrl_pmic>;
+		gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
+
+		gpo {
+			rohm,drv = <0x0C>;	/* 0b0000_1100 all gpos with cmos output mode */
+		};
+
+		regulators {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			bd71837,pmic-buck2-uses-i2c-dvs;
+			bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */
+
+			buck1_reg: regulator@0 {
+				reg = <0>;
+				regulator-compatible = "buck1";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <1250>;
+			};
+
+			buck2_reg: regulator@1 {
+				reg = <1>;
+				regulator-compatible = "buck2";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <1250>;
+			};
+
+			buck3_reg: regulator@2 {
+				reg = <2>;
+				regulator-compatible = "buck3";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+			};
+
+			buck4_reg: regulator@3 {
+				reg = <3>;
+				regulator-compatible = "buck4";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1300000>;
+			};
+
+			buck5_reg: regulator@4 {
+				reg = <4>;
+				regulator-compatible = "buck5";
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6_reg: regulator@5 {
+				reg = <5>;
+				regulator-compatible = "buck6";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck7_reg: regulator@6 {
+				reg = <6>;
+				regulator-compatible = "buck7";
+				regulator-min-microvolt = <1605000>;
+				regulator-max-microvolt = <1995000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck8_reg: regulator@7 {
+				reg = <7>;
+				regulator-compatible = "buck8";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1_reg: regulator@8 {
+				reg = <8>;
+				regulator-compatible = "ldo1";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2_reg: regulator@9 {
+				reg = <9>;
+				regulator-compatible = "ldo2";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3_reg: regulator@10 {
+				reg = <10>;
+				regulator-compatible = "ldo3";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4_reg: regulator@11 {
+				reg = <11>;
+				regulator-compatible = "ldo4";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5_reg: regulator@12 {
+				reg = <12>;
+				regulator-compatible = "ldo5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			ldo6_reg: regulator@13 {
+				reg = <13>;
+				regulator-compatible = "ldo6";
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo7_reg: regulator@14 {
+				reg = <14>;
+				regulator-compatible = "ldo7";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	ptn5110: tcpc@50 {
+		compatible = "nxp,ptn5110";
+		reg = <0x50>;
+		status = "okay";
+
+		typec1_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			power-role = "dual";
+			data-role = "dual";
+			try-power-role = "sink";
+			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+				     PDO_VAR(5000, 20000, 3000)>;
+			op-sink-microwatt = <15000000>;
+			self-powered;
+		};
+	};
+
+	ptn5110_2: tcpc@52 {
+		compatible = "nxp,ptn5110";
+		reg = <0x52>;
+		status = "okay";
+
+		typec2_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			power-role = "dual";
+			data-role = "dual";
+			try-power-role = "sink";
+			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+				     PDO_VAR(5000, 20000, 3000)>;
+			op-sink-microwatt = <15000000>;
+			self-powered;
+		};
+	};
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&flexspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi>;
+	status = "okay";
+
+	flash0: n25q256a@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <8>;
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			at803x,led-act-blind-workaround;
+			at803x,eee-okay;
+			at803x,vddio-1p8v;
+		};
+	};
+};
+
+&uart2 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&usbotg1 {
+	status = "okay";
+	extcon = <&ptn5110>;
+};
+
+&usbotg2 {
+	status = "okay";
+	extcon = <&ptn5110_2>;
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	non-removable;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&A53_0 {
+	arm-supply = <&buck2_reg>;
+};
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
index 6b459831e74..7ff878b5f96 100644
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
  */
 
 #include "imx8mm-u-boot.dtsi"
@@ -12,6 +12,25 @@
 		u-boot,dm-spl;
 	};
 
+	aliases {
+		usbgadget0 = &usbg1;
+		usbgadget1 = &usbg2;
+	};
+
+	usbg1: usbg1 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg1>;
+		status = "okay";
+	};
+
+	usbg2: usbg2 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg2>;
+		status = "okay";
+	};
+
 	firmware {
 		optee {
 			compatible = "linaro,optee-tz";
@@ -22,6 +41,7 @@
 
 &reg_usdhc2_vmmc {
 	u-boot,off-on-delay-us = <20000>;
+	u-boot,dm-spl;
 };
 
 &pinctrl_reg_usdhc2_vmmc {
@@ -68,14 +88,36 @@
 	u-boot,dm-spl;
 };
 
+&crypto {
+	u-boot,dm-spl;
+};
+
+&sec_jr0 {
+	u-boot,dm-spl;
+};
+
+&sec_jr1 {
+	u-boot,dm-spl;
+};
+
+&sec_jr2 {
+	u-boot,dm-spl;
+};
+
 &usdhc1 {
 	u-boot,dm-spl;
+	assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
+	assigned-clock-rates = <400000000>;
+	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
 };
 
 &usdhc2 {
 	u-boot,dm-spl;
 	sd-uhs-sdr104;
 	sd-uhs-ddr50;
+	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
+	assigned-clock-rates = <400000000>;
+	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
 	fsl,signal-voltage-switch-extra-delay-ms = <8>;
 };
 
@@ -83,6 +125,9 @@
 	u-boot,dm-spl;
 	mmc-hs400-1_8v;
 	mmc-hs400-enhanced-strobe;
+	assigned-clocks = <&clk IMX8MM_CLK_USDHC3>;
+	assigned-clock-rates = <400000000>;
+	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
 };
 
 &i2c1 {
@@ -109,6 +154,31 @@
 	phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 };
 
+&ethphy0 {
+	vddio0: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
+
 &wdog1 {
 	u-boot,dm-spl;
 };
+
+&usbotg1 {
+	status = "okay";
+	extcon = <&ptn5110>;
+};
+
+&lcdif {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
+};
+
+&mipi_dsi {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
+};
diff --git a/arch/arm/dts/imx8mm-evk.dts b/arch/arm/dts/imx8mm-evk.dts
index 4e2820d1924..c07eb8be8e4 100644
--- a/arch/arm/dts/imx8mm-evk.dts
+++ b/arch/arm/dts/imx8mm-evk.dts
@@ -9,9 +9,13 @@
 #include "imx8mm-evk.dtsi"
 
 / {
-	model = "FSL i.MX8MM EVK board";
+	model = "NXP i.MX8MM EVK board";
 	compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
 
+	chosen {
+		bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
+	};
+
 	aliases {
 		spi0 = &flexspi;
 	};
diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi
index 60179e006d3..95d339bb373 100644
--- a/arch/arm/dts/imx8mm-evk.dtsi
+++ b/arch/arm/dts/imx8mm-evk.dtsi
@@ -81,6 +81,32 @@
 			clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
 		};
 	};
+
+	dsi_host: dsi-host {
+		compatible = "samsung,sec-mipi-dsi";
+		status = "okay";
+	};
+
+	rm67199_panel {
+		compatible = "raydium,rm67199";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_mipi_dsi_en>;
+		reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
+		dsi-lanes = <4>;
+		video-mode = <2>;	/* 0: burst mode
+					 * 1: non-burst mode with sync event
+					 * 2: non-burst mode with sync pulse
+					 */
+		panel-width-mm = <68>;
+		panel-height-mm = <121>;
+		status = "okay";
+
+		port {
+			rm67191_from_dsim: endpoint {
+				remote-endpoint = <&dsim_to_rm67191>;
+			};
+		};
+	};
 };
 
 &A53_0 {
@@ -99,6 +125,23 @@
 	cpu-supply = <&buck2_reg>;
 };
 
+
+&ecspi2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	fsl,spi-num-chipselects = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
+	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+	status = "okay";
+
+	spidev0: spi@0 {
+		reg = <0>;
+		compatible = "rohm,dh2228fv";
+		spi-max-frequency = <500000>;
+	};
+};
+
 &fec1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec1>;
@@ -122,8 +165,11 @@
 
 &i2c1 {
 	clock-frequency = <400000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
 	pmic: pca9450@25 {
@@ -246,10 +292,27 @@
 
 &i2c2 {
 	clock-frequency = <400000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
+	adv_bridge: adv7535@3d {
+		compatible = "adi,adv7535";
+		reg = <0x3d>;
+		adi,addr-cec = <0x3c>;
+		adi,dsi-lanes = <4>;
+		status = "okay";
+
+		port {
+			adv7535_from_dsim: endpoint {
+				remote-endpoint = <&dsim_to_adv7535>;
+			};
+		};
+	};
+
 	ptn5110: tcpc@50 {
 		compatible = "nxp,ptn5110";
 		pinctrl-names = "default";
@@ -281,9 +344,12 @@
 };
 
 &i2c3 {
-	clock-frequency = <400000>;
-	pinctrl-names = "default";
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
 	pca6416: gpio@20 {
@@ -319,6 +385,7 @@
 	srp-disable;
 	adp-disable;
 	usb-role-switch;
+	disable-over-current;
 	samsung,picophy-pre-emp-curr-control = <3>;
 	samsung,picophy-dc-vol-level-adjust = <7>;
 	status = "okay";
@@ -350,7 +417,47 @@
 	status = "okay";
 };
 
+&lcdif {
+	display = <&display0>;
+	status = "okay";
+
+	display0: display@0 {
+		bits-per-pixel = <24>;
+		bus-width = <24>;
+	};
+};
+
+&mipi_dsi {
+	status = "okay";
+
+	port@1 {
+		dsim_to_adv7535: endpoint {
+			remote-endpoint = <&adv7535_from_dsim>;
+		};
+	};
+
+	port@2 {
+		dsim_to_rm67191: endpoint {
+			remote-endpoint = <&rm67191_from_dsim>;
+		};
+	};
+};
+
 &iomuxc {
+	pinctrl_ecspi2: ecspi2grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK		0x82
+			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI		0x82
+			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO		0x82
+		>;
+	};
+
+	pinctrl_ecspi2_cs: ecspi2cs {
+		fsl,pins = <
+			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x40000
+		>;
+	};
+
 	pinctrl_fec1: fec1grp {
 		fsl,pins = <
 			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
@@ -410,6 +517,27 @@
 		>;
 	};
 
+	pinctrl_i2c1_gpio: i2c1grp-gpio {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14        		0x1c3
+			MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15        	0x1c3
+		>;
+	};
+
+	pinctrl_i2c2_gpio: i2c2grp-gpio {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16        		0x1c3
+			MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17        	0x1c3
+		>;
+	};
+
+	pinctrl_i2c3_gpio: i2c3grp-gpio {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18        		0x1c3
+			MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19        	0x1c3
+		>;
+	};
+
 	pinctrl_pmic: pmicirqgrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141
@@ -488,7 +616,13 @@
 
 	pinctrl_wdog: wdoggrp {
 		fsl,pins = <
-			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x166
+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
+		>;
+	};
+
+	pinctrl_mipi_dsi_en: mipi_dsi_en {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x19
 		>;
 	};
 };
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index 3ea03a96d6d..5a54dfbbb4a 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -39,25 +39,25 @@
 			filename = "u-boot-spl.bin";
 		};
 
-		1d-imem {
+		blob_1d_imem: blob-ext@1 {
 			filename = "lpddr4_pmu_train_1d_imem.bin";
 			size = <0x8000>;
 			type = "blob-ext";
 		};
 
-		1d-dmem {
+		blob_1d_dmem: blob-ext@2 {
 			filename = "lpddr4_pmu_train_1d_dmem.bin";
 			size = <0x4000>;
 			type = "blob-ext";
 		};
 
-		2d-imem {
+		blob_2d_imem: blob-ext@3 {
 			filename = "lpddr4_pmu_train_2d_imem.bin";
 			size = <0x8000>;
 			type = "blob-ext";
 		};
 
-		2d-dmem {
+		blob_2d_dmem: blob-ext@4 {
 			filename = "lpddr4_pmu_train_2d_dmem.bin";
 			size = <0x4000>;
 			type = "blob-ext";
diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
index 724f6ddbf39..f5ecc6d385c 100644
--- a/arch/arm/dts/imx8mm.dtsi
+++ b/arch/arm/dts/imx8mm.dtsi
@@ -4,11 +4,11 @@
  */
 
 #include <dt-bindings/clock/imx8mm-clock.h>
-#include <dt-bindings/power/imx8mm-power.h>
 #include <dt-bindings/reset/imx8mq-reset.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/imx8mm-dispmix.h>
 #include <dt-bindings/thermal/thermal.h>
 
 #include "imx8mm-pinfunc.h"
@@ -39,6 +39,9 @@
 		spi0 = &ecspi1;
 		spi1 = &ecspi2;
 		spi2 = &ecspi3;
+		usb0 = &usbotg1;
+		usb1 = &usbotg2;
+		video0 = &lcdif;
 	};
 
 	cpus {
@@ -196,16 +199,120 @@
 	pmu {
 		compatible = "arm,armv8-pmuv3";
 		interrupts = <GIC_PPI 7
-			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			     (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
 		interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
 	};
 
+	power-domains {
+		compatible = "simple-bus";
+		/* HSIO SS */
+		hsiomix_pd: hsiomix-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <0>;
+			domain-name = "hsiomix";
+			clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
+		};
+
+		pcie_pd: pcie-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <1>;
+			domain-name = "pcie";
+			parent-domains = <&hsiomix_pd>;
+			clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
+		};
+
+		usb_otg1_pd: usbotg1-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <2>;
+			domain-name = "usb_otg1";
+			parent-domains = <&hsiomix_pd>;
+		};
+
+		usb_otg2_pd: usbotg2-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <3>;
+			domain-name = "usb_otg2";
+			parent-domains = <&hsiomix_pd>;
+		};
+
+		/* GPU SS */
+		gpumix_pd: gpumix-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <4>;
+			domain-name = "gpumix";
+			clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+				 <&clk IMX8MM_CLK_GPU_AHB>,
+				 <&clk IMX8MM_CLK_GPU2D_ROOT>,
+				 <&clk IMX8MM_CLK_GPU3D_ROOT>;
+		};
+
+		/* VPU SS */
+		vpumix_pd: vpumix-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <5>;
+			domain-name = "vpumix";
+			clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
+		};
+
+		vpu_g1_pd: vpug1-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <6>;
+			domain-name = "vpu_g1";
+			parent-domains = <&vpumix_pd>;
+			clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
+		};
+
+		vpu_g2_pd: vpug2-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <7>;
+			domain-name = "vpu_g2";
+			parent-domains = <&vpumix_pd>;
+			clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
+		};
+
+		vpu_h1_pd: vpuh1-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <8>;
+			domain-name = "vpu_h1";
+			parent-domains = <&vpumix_pd>;
+			clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>;
+		};
+
+		/* DISP SS */
+		dispmix_pd: dispmix-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <9>;
+			domain-name = "dispmix";
+			clocks = <&clk IMX8MM_CLK_DISP_ROOT>,
+				 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+				 <&clk IMX8MM_CLK_DISP_APB_ROOT>;
+		};
+
+		mipi_pd: mipi-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <10>;
+			domain-name = "mipi";
+			parent-domains = <&dispmix_pd>;
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
 		clock-frequency = <8000000>;
 		arm,no-tick-in-suspend;
 	};
@@ -266,6 +373,11 @@
 		#size-cells = <1>;
 		ranges = <0x0 0x0 0x0 0x3e000000>;
 
+		caam_sm: caam-sm@100000 {
+			compatible = "fsl,imx6q-caam-sm";
+			reg = <0x100000 0x8000>;
+		};
+
 		aips1: bus@30000000 {
 			compatible = "fsl,aips-bus", "simple-bus";
 			reg = <0x30000000 0x400000>;
@@ -278,12 +390,13 @@
 				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 				reg = <0x30010000 0x10000>;
 				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
+				clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>,
 					 <&clk IMX8MM_CLK_SAI1_ROOT>,
 					 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
-				clock-names = "bus", "mclk1", "mclk2", "mclk3";
+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
 				dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
 				dma-names = "rx", "tx";
+				fsl,dataline = <0 0xff 0xff>;
 				status = "disabled";
 			};
 
@@ -292,10 +405,10 @@
 				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 				reg = <0x30020000 0x10000>;
 				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
+				clocks = <&clk IMX8MM_CLK_SAI2_IPG>, <&clk IMX8MM_CLK_DUMMY>,
 					<&clk IMX8MM_CLK_SAI2_ROOT>,
 					<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
-				clock-names = "bus", "mclk1", "mclk2", "mclk3";
+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
 				dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
 				dma-names = "rx", "tx";
 				status = "disabled";
@@ -306,10 +419,10 @@
 				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 				reg = <0x30030000 0x10000>;
 				interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
+				clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>,
 					 <&clk IMX8MM_CLK_SAI3_ROOT>,
 					 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
-				clock-names = "bus", "mclk1", "mclk2", "mclk3";
+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
 				dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
 				dma-names = "rx", "tx";
 				status = "disabled";
@@ -320,12 +433,13 @@
 				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 				reg = <0x30050000 0x10000>;
 				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
+				clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>,
 					 <&clk IMX8MM_CLK_SAI5_ROOT>,
 					 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
-				clock-names = "bus", "mclk1", "mclk2", "mclk3";
+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
 				dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
 				dma-names = "rx", "tx";
+				fsl,dataline = <0 0xf 0xf>;
 				status = "disabled";
 			};
 
@@ -334,16 +448,16 @@
 				compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 				reg = <0x30060000 0x10000>;
 				interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
+				clocks = <&clk IMX8MM_CLK_SAI6_IPG>, <&clk IMX8MM_CLK_DUMMY>,
 					 <&clk IMX8MM_CLK_SAI6_ROOT>,
 					 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
-				clock-names = "bus", "mclk1", "mclk2", "mclk3";
+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
 				dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
 				dma-names = "rx", "tx";
 				status = "disabled";
 			};
 
-			micfil: audio-controller@30080000 {
+			micfil: micfil@30080000 {
 				compatible = "fsl,imx8mm-micfil";
 				reg = <0x30080000 0x10000>;
 				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
@@ -363,7 +477,7 @@
 			};
 
 			spdif1: spdif@30090000 {
-				compatible = "fsl,imx35-spdif";
+				compatible = "fsl,imx8mm-spdif";
 				reg = <0x30090000 0x10000>;
 				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
@@ -525,6 +639,10 @@
 				cpu_speed_grade: speed-grade@10 {
 					reg = <0x10 4>;
 				};
+
+				fec_mac_address: mac-address@640 {
+					reg = <0x90 6>;
+				};
 			};
 
 			anatop: anatop@30360000 {
@@ -532,6 +650,22 @@
 				reg = <0x30360000 0x10000>;
 			};
 
+			irq_sec_vio: caam_secvio {
+				compatible = "fsl,imx6q-caam-secvio";
+				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+				jtag-tamper = "disabled";
+				watchdog-tamper = "enabled";
+				internal-boot-tamper = "enabled";
+				external-pin-tamper = "disabled";
+			};
+
+			caam_snvs: caam-snvs@30370000 {
+				compatible = "fsl,imx6q-caam-snvs";
+				reg = <0x30370000 0x10000>;
+				clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
+				clock-names = "ipg";
+			};
+
 			snvs: snvs@30370000 {
 				compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
 				reg = <0x30370000 0x10000>;
@@ -594,75 +728,6 @@
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 				#reset-cells = <1>;
 			};
-
-			gpc: gpc@303a0000 {
-				compatible = "fsl,imx8mm-gpc";
-				reg = <0x303a0000 0x10000>;
-				interrupt-parent = <&gic>;
-				interrupt-controller;
-				#interrupt-cells = <3>;
-
-				pgc {
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					pgc_hsiomix: power-domain@0 {
-						#power-domain-cells = <0>;
-						reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
-						clocks = <&clk IMX8MM_CLK_USB_BUS>;
-					};
-
-					pgc_pcie: power-domain@1 {
-						#power-domain-cells = <0>;
-						reg = <IMX8MM_POWER_DOMAIN_PCIE>;
-						power-domains = <&pgc_hsiomix>;
-					};
-
-					pgc_otg1: power-domain@2 {
-						#power-domain-cells = <0>;
-						reg = <IMX8MM_POWER_DOMAIN_OTG1>;
-						power-domains = <&pgc_hsiomix>;
-					};
-
-					pgc_otg2: power-domain@3 {
-						#power-domain-cells = <0>;
-						reg = <IMX8MM_POWER_DOMAIN_OTG2>;
-						power-domains = <&pgc_hsiomix>;
-					};
-
-					pgc_gpumix: power-domain@4 {
-						#power-domain-cells = <0>;
-						reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
-						clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
-						         <&clk IMX8MM_CLK_GPU_AHB>;
-					};
-
-					pgc_gpu: power-domain@5 {
-						#power-domain-cells = <0>;
-						reg = <IMX8MM_POWER_DOMAIN_GPU>;
-						clocks = <&clk IMX8MM_CLK_GPU_AHB>,
-						         <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
-						         <&clk IMX8MM_CLK_GPU2D_ROOT>,
-						         <&clk IMX8MM_CLK_GPU3D_ROOT>;
-						resets = <&src IMX8MQ_RESET_GPU_RESET>;
-						power-domains = <&pgc_gpumix>;
-					};
-
-					dispmix_pd: power-domain@10 {
-						#power-domain-cells = <0>;
-						reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
-						clocks = <&clk IMX8MM_CLK_DISP_ROOT>,
-							 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
-							 <&clk IMX8MM_CLK_DISP_APB_ROOT>;
-					};
-
-					mipi_pd: power-domain@11 {
-						#power-domain-cells = <0>;
-						reg = <IMX8MM_POWER_DOMAIN_MIPI>;
-						power-domains = <&dispmix_pd>;
-					};
-				};
-			};
 		};
 
 		aips2: bus@30400000 {
@@ -824,6 +889,7 @@
 					compatible = "fsl,sec-v4.0-job-ring";
 					reg = <0x1000 0x1000>;
 					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+					status = "disabled";
 				};
 
 				sec_jr1: jr@2000 {
@@ -896,6 +962,7 @@
 				reg = <0x30aa0000 0x10000>;
 				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX8MM_CLK_MU_ROOT>;
+				clock-names = "mu";
 				#mbox-cells = <2>;
 			};
 
@@ -966,7 +1033,7 @@
 			};
 
 			fec1: ethernet@30be0000 {
-				compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
+				compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
 				reg = <0x30be0000 0x10000>;
 				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
@@ -982,18 +1049,47 @@
 				assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
 						  <&clk IMX8MM_CLK_ENET_TIMER>,
 						  <&clk IMX8MM_CLK_ENET_REF>,
-						  <&clk IMX8MM_CLK_ENET_TIMER>;
+						  <&clk IMX8MM_CLK_ENET_PHY_REF>;
 				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
 							 <&clk IMX8MM_SYS_PLL2_100M>,
-							 <&clk IMX8MM_SYS_PLL2_125M>;
-				assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
+							 <&clk IMX8MM_SYS_PLL2_125M>,
+							 <&clk IMX8MM_SYS_PLL2_50M>;
+				assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
 				fsl,num-tx-queues = <3>;
 				fsl,num-rx-queues = <3>;
+				nvmem-cells = <&fec_mac_address>;
+				nvmem-cell-names = "mac-address";
+				nvmem_macaddr_swap;
+				fsl,stop-mode = <&gpr 0x10 3>;
+				fsl,wakeup_irq = <2>;
 				status = "disabled";
 			};
 
 		};
 
+		noc: interconnect@32700000 {
+			compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc";
+			reg = <0x32700000 0x100000>;
+			clocks = <&clk IMX8MM_CLK_NOC>;
+			fsl,ddrc = <&ddrc>;
+			#interconnect-cells = <1>;
+			operating-points-v2 = <&noc_opp_table>;
+
+			noc_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-150M {
+					opp-hz = /bits/ 64 <150000000>;
+				};
+				opp-375M {
+					opp-hz = /bits/ 64 <375000000>;
+				};
+				opp-750M {
+					opp-hz = /bits/ 64 <750000000>;
+				};
+			};
+		};
+
 		aips4: bus@32c00000 {
 			compatible = "fsl,aips-bus", "simple-bus";
 			reg = <0x32c00000 0x400000>;
@@ -1001,17 +1097,112 @@
 			#size-cells = <1>;
 			ranges = <0x32c00000 0x32c00000 0x400000>;
 
+			lcdif: lcdif@32e00000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8mm-lcdif";
+				reg = <0x32e00000 0x10000>;
+				clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
+					 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+					 <&clk IMX8MM_CLK_DISP_APB_ROOT>;
+				clock-names = "pix", "disp-axi", "disp-apb";
+				assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
+						  <&clk IMX8MM_CLK_DISP_AXI>,
+						  <&clk IMX8MM_CLK_DISP_APB>;
+				assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
+							 <&clk IMX8MM_SYS_PLL2_1000M>,
+							 <&clk IMX8MM_SYS_PLL1_800M>;
+				assigned-clock-rates = <594000000>, <500000000>, <200000000>;
+				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+				lcdif-gpr = <&dispmix_gpr>;
+				resets = <&lcdif_resets>;
+				power-domains = <&dispmix_pd>;
+				status = "disabled";
+
+				lcdif_disp0: port@0 {
+					reg = <0>;
+
+					lcdif_to_dsim: endpoint {
+						remote-endpoint = <&dsim_from_lcdif>;
+					};
+				};
+			};
+
+			mipi_dsi: mipi_dsi@32e10000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8mm-mipi-dsim";
+				reg = <0x32e10000 0x400>;
+				clocks = <&clk IMX8MM_CLK_DSI_CORE>,
+					 <&clk IMX8MM_CLK_DSI_PHY_REF>;
+				clock-names = "cfg", "pll-ref";
+				assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
+						  <&clk IMX8MM_CLK_DSI_PHY_REF>;
+				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
+							 <&clk IMX8MM_CLK_24M>;
+				assigned-clock-rates = <266000000>, <12000000>;
+				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+				dsi-gpr = <&dispmix_gpr>;
+				resets = <&mipi_dsi_resets>;
+				power-domains = <&mipi_pd>;
+				status = "disabled";
+
+				port@0 {
+					dsim_from_lcdif: endpoint {
+						remote-endpoint = <&lcdif_to_dsim>;
+					};
+				};
+			};
+
+			csi1_bridge: csi1_bridge@32e20000 {
+				compatible = "fsl,imx8mm-csi", "fsl,imx8mq-csi", "fsl,imx6s-csi";
+				reg = <0x32e20000 0x1000>;
+				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+					<&clk IMX8MM_CLK_CSI1_ROOT>,
+					<&clk IMX8MM_CLK_DISP_APB_ROOT>;
+				clock-names = "disp-axi", "csi_mclk", "disp_dcic";
+				power-domains = <&dispmix_pd>;
+				status = "disabled";
+			};
+
+			mipi_csi_1: mipi_csi@32e30000 {
+				compatible = "fsl,imx8mm-mipi-csi";
+				reg = <0x32e30000 0x1000>;
+				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+				clock-frequency = <333000000>;
+				clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
+					<&clk IMX8MM_CLK_CSI1_PHY_REF>,
+					<&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+					<&clk IMX8MM_CLK_DISP_APB_ROOT>;
+				clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb";
+				bus-width = <4>;
+				power-domains = <&mipi_pd>;
+				status = "disabled";
+			};
+
+			dispmix_gpr: display-gpr@32e28000 {
+				compatible = "fsl, imx8mm-iomuxc-gpr", "syscon";
+				reg = <0x32e28000 0x100>;
+			};
+
+			display-subsystem {
+				compatible = "fsl,imx-display-subsystem";
+				ports = <&lcdif_disp0>;
+			};
+
 			usbotg1: usb@32e40000 {
-				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
+				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
 				reg = <0x32e40000 0x200>;
 				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
 				clock-names = "usb1_ctrl_root_clk";
-				assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
-				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
+				assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
+						<&clk IMX8MM_CLK_USB_CORE_REF>;
+				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
+							<&clk IMX8MM_SYS_PLL1_100M>;
 				phys = <&usbphynop1>;
 				fsl,usbmisc = <&usbmisc1 0>;
-				power-domains = <&pgc_otg1>;
 				status = "disabled";
 			};
 
@@ -1022,16 +1213,17 @@
 			};
 
 			usbotg2: usb@32e50000 {
-				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
+				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
 				reg = <0x32e50000 0x200>;
 				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
 				clock-names = "usb1_ctrl_root_clk";
-				assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
-				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
+				assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
+						<&clk IMX8MM_CLK_USB_CORE_REF>;
+				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
+						<&clk IMX8MM_SYS_PLL1_100M>;
 				phys = <&usbphynop2>;
 				fsl,usbmisc = <&usbmisc2 0>;
-				power-domains = <&pgc_otg2>;
 				status = "disabled";
 			};
 
@@ -1107,15 +1299,38 @@
 					<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 			fsl,max-link-speed = <2>;
 			linux,pci-domain = <0>;
-			power-domains = <&pgc_pcie>;
-			resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+			power-domains = <&pcie_pd>;
+			resets = <&src IMX8MQ_RESET_PCIEPHY>,
+				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>,
 				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
-			reset-names = "apps", "turnoff";
+			reset-names = "pciephy", "apps", "clkreq", "turnoff";
 			phys = <&pcie_phy>;
 			phy-names = "pcie-phy";
 			status = "disabled";
 		};
 
+		pcie0_ep: pcie_ep@33800000 {
+			compatible = "fsl,imx8mm-pcie-ep";
+			reg = <0x33800000 0x000400000>,
+			      <0x18000000 0x08000000>;
+			reg-names = "regs", "addr_space";
+			num-lanes = <1>;
+			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+			interrupt-names = "dma";
+			fsl,max-link-speed = <2>;
+			power-domains = <&pcie_pd>;
+			resets = <&src IMX8MQ_RESET_PCIEPHY>,
+				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>,
+				 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+			reset-names = "pciephy", "apps", "clkreq", "turnoff";
+			fsl,imx7d-pcie-phy = <&pcie_phy>;
+			num-ib-windows = <4>;
+			num-ob-windows = <4>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@38800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x38800000 0x10000>, /* GIC Dist */
@@ -1141,4 +1356,79 @@
 			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 		};
 	};
+
+	dispmix-reset {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		dispmix_sft_rstn: dispmix-sft-rstn@32e28000 {
+			compatible = "fsl,imx8mm-dispmix-sft-rstn";
+			reg = <0x0 0x32e28000 0x0 0x4>;
+			clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>;
+			clock-names = "disp_apb_root_clk";
+			active_low;
+			power-domains = <&dispmix_pd>;
+			#reset-cells = <1>;
+		};
+
+		dispmix_clk_en: dispmix-clk-en@32e28004 {
+			compatible = "fsl,imx8mm-dispmix-clk-en";
+			reg = <0x0 0x32e28004 0x0 0x4>;
+			clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>;
+			clock-names = "disp_apb_root_clk";
+			power-domains = <&dispmix_pd>;
+			#reset-cells = <1>;
+		};
+
+		dispmix_mipi_rst: dispmix-mipi-rst@32e28008 {
+			compatible = "fsl,imx8mm-dispmix-mipi-rst";
+			reg = <0x0 0x32e28008 0x0 0x4>;
+			clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>;
+			clock-names = "disp_apb_root_clk";
+			active_low;
+			power-domains = <&dispmix_pd>;
+			#reset-cells = <1>;
+		};
+	};
+
+	lcdif_resets: lcdif-resets {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#reset-cells = <0>;
+
+		lcdif-soft-resetn {
+			compatible = "lcdif,soft-resetn";
+			resets = <&dispmix_sft_rstn IMX8MM_BUS_RSTN_BLK_SYNC>;
+		};
+
+		lcdif-clk-enable {
+			compatible = "lcdif,clk-enable";
+			resets = <&dispmix_clk_en IMX8MM_LCDIF_APB_CLK_EN>,
+				 <&dispmix_clk_en IMX8MM_LCDIF_PIXEL_CLK_EN>;
+		};
+	};
+
+	mipi_dsi_resets: mipi-dsi-resets {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#reset-cells = <0>;
+
+		dsi-soft-resetn {
+			compatible = "dsi,soft-resetn";
+			resets = <&dispmix_sft_rstn IMX8MM_MIPI_DSI_I_PRESET>;
+		};
+
+		dsi-clk-enable {
+			compatible = "dsi,clk-enable";
+			resets = <&dispmix_clk_en IMX8MM_MIPI_DSI_CLKREF_EN>,
+				 <&dispmix_clk_en IMX8MM_MIPI_DSI_PCLK_EN>;
+		};
+
+		dsi-mipi-reset {
+			compatible = "dsi,mipi-reset";
+			resets = <&dispmix_mipi_rst IMX8MM_MIPI_M_RESET>;
+		};
+	};
 };
diff --git a/arch/arm/dts/imx8mn-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ab2-u-boot.dtsi
new file mode 100644
index 00000000000..689f6f3218d
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ab2-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mn-evk-u-boot.dtsi"
+
+&fec1 {
+	phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/imx8mn-ab2.dts b/arch/arm/dts/imx8mn-ab2.dts
new file mode 100644
index 00000000000..9a5b5f63f89
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ab2.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mn-evk.dts"
+#include "imx8mn-ab2.dtsi"
+
+/ {
+	model = "NXP i.MX8MNano LPDDR4 Audio board 2.0";
+	compatible = "fsl,imx8mn-ab2", "fsl,imx8mn";
+};
diff --git a/arch/arm/dts/imx8mn-ab2.dtsi b/arch/arm/dts/imx8mn-ab2.dtsi
new file mode 100644
index 00000000000..039f3d549ac
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ab2.dtsi
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+/ {
+	/delete-node/ dsi-host;
+	/delete-node/ ir-receiver;
+	/delete-node/ rm67199_panel;
+
+	gpio-leds {
+		panel {
+			label = "green:panel";
+			gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
+			default-state = "on";
+		};
+	};
+
+	reg_ab2_ana_pwr: regulator-ab2-ana-pwr {
+		compatible = "regulator-fixed";
+		regulator-name = "ANA_12V0";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ab2_ana_pwr>;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_5V0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		regulator-boot-on;
+		enable-active-high;
+	};
+};
+
+&fec1 {
+	phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+
+	mdio {
+		ethphy0: ethernet-phy@0 {
+			max-speed = <100>;
+		};
+	};
+};
+
+&i2c2 {
+	/delete-node/ adv7535@3d;
+	/delete-node/ tcpc@50;
+
+	pca6408_2: gpio@20 {
+		compatible = "ti,tca6408";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	ptn5150: tcpc@1d {
+		compatible = "nxp,ptn5150";
+		reg = <0x1d>;
+		status = "okay";
+
+		port {
+			typec1_dr_sw: endpoint {
+				remote-endpoint = <&usb1_drd_sw>;
+			};
+		};
+
+		typec1_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			power-role = "dual";
+			data-role = "dual";
+			try-power-role = "sink";
+			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+				PDO_VAR(5000, 20000, 3000)>;
+			op-sink-microwatt = <15000000>;
+			self-powered;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC		0x3
+			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
+			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
+			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
+			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
+			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
+			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
+			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
+			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
+			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
+			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
+			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
+			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+			MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x16
+		>;
+	};
+
+	pinctrl_ab2_ana_pwr: ab2anapwrgrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x41
+		>;
+	};
+
+	pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x41
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4
+		>;
+	};
+};
+
+&lcdif {
+	status = "disabled";
+};
+
+&mipi_dsi {
+	status = "disabled";
+
+	/delete-node/ port@1;
+	/delete-node/ port@2;
+};
+
+&usdhc2 {
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+};
+
+&usbotg1 {
+	extcon = <&ptn5150>;
+};
diff --git a/arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi
new file mode 100644
index 00000000000..9d595da3a90
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr3l-ab2-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mn-ab2-u-boot.dtsi"
+
+&blob_1 {
+	filename = "ddr3_imem_1d_201810.bin";
+};
+
+&blob_2 {
+	filename = "ddr3_dmem_1d_201810.bin";
+};
+
+/delete-node/ &blob_3;
+
+/delete-node/ &blob_4;
diff --git a/arch/arm/dts/imx8mn-ddr3l-ab2.dts b/arch/arm/dts/imx8mn-ddr3l-ab2.dts
new file mode 100644
index 00000000000..b89e1ce81b2
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr3l-ab2.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright 2021 NXP
+  */
+
+#include "imx8mn-ddr3l-evk.dts"
+#include "imx8mn-ab2.dtsi"
+
+/ {
+	model = "NXP i.MX8MNano DDR3L Audio board 2.0";
+};
diff --git a/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
new file mode 100644
index 00000000000..9bdd5b11b7e
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr3l-evk-u-boot.dtsi
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mn-evk-u-boot.dtsi"
+
+/ {
+	mcu_rdc {
+		compatible = "imx8m,mcu_rdc";
+			    /* rdc config when MCU starts
+			     * master
+			     *   SDMA3p --> domain 1
+			     *   SDMA3b --> domian 1
+			     *   SDMA3_SPBA2  --> domian 1
+			     * peripheral:
+			     *   SAI3   --> Only Domian 1 can access
+			     *   UART4  --> Only Domian 1 can access
+			     *   GPT1   --> Only Domian 1 can access
+			     * memory:
+			     *   no MRC should be configured when GPU3D is disabled.
+			     * end.
+			     */
+		start-config = <
+			    RDC_MDA  RDC_MDA_SDMA3p DID1 0x0 0x0
+			    RDC_MDA  RDC_MDA_SDMA3b DID1 0x0 0x0
+			    RDC_MDA  RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0
+			    RDC_PDAP RDC_PDAP_SAI3  PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_UART4 PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_GPT1  PDAP_D1_ACCESS 0x0 0x0
+			    0x0      0x0            0x0  0x0 0x0
+			  >;
+			    /* rdc config when MCU stops
+			     * memory:
+			     *   no MRC should be configured when GPU3D is disabled.
+			     * end.
+			     */
+		stop-config = <
+			    0x0      0x0            0x0  0x0 0x0
+			  >;
+	};
+};
+
+&blob_1 {
+	filename = "ddr3_imem_1d_201810.bin";
+};
+
+&blob_2 {
+	filename = "ddr3_dmem_1d_201810.bin";
+};
+
+/delete-node/ &blob_3;
+
+/delete-node/ &blob_4;
diff --git a/arch/arm/dts/imx8mn-ddr3l-evk.dts b/arch/arm/dts/imx8mn-ddr3l-evk.dts
new file mode 100644
index 00000000000..debb6a41b7c
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr3l-evk.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright 2020 NXP
+  */
+
+#include "imx8mn-evk.dts"
+
+#include "imx8mn-sec-def.h"
+
+/ {
+	model = "NXP i.MX8MNano DDR3L EVK board";
+};
+
+&dsi_host {
+	status = "disabled";
+};
+
+&{/rm67199_panel} {
+	status = "disabled";
+};
+
+&lcdif {
+	status = "disabled";
+};
+
+&mipi_dsi {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi
new file mode 100644
index 00000000000..6df56985d63
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr4-ab2-u-boot.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mn-ddr4-evk-u-boot.dtsi"
+
+&fec1 {
+	phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/dts/imx8mn-ddr4-ab2.dts b/arch/arm/dts/imx8mn-ddr4-ab2.dts
new file mode 100644
index 00000000000..40c9c56bfc5
--- /dev/null
+++ b/arch/arm/dts/imx8mn-ddr4-ab2.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 NXP
+ */
+
+#include "imx8mn-ddr4-evk.dts"
+#include "imx8mn-ab2.dtsi"
+
+/ {
+	model = "NXP i.MX8MNano DDR4 Audio board 2.0";
+	compatible = "fsl,imx8mn-ab2", "fsl,imx8mn";
+};
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 2e397907663..89740a6d99d 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -1,8 +1,10 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
  */
 
+#include "imx8mn-sec-def.h"
+
 / {
 	binman: binman {
 		multiple-images;
@@ -13,12 +15,64 @@
 		wdt = <&wdog1>;
 		u-boot,dm-spl;
 	};
+
+	aliases {
+		usbgadget0 = &usbg1;
+	};
+
+	usbg1: usbg1 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg1>;
+		status = "okay";
+	};
+
 	firmware {
 		optee {
 			compatible = "linaro,optee-tz";
 			method = "smc";
 		};
 	};
+
+	mcu_rdc {
+		compatible = "imx8m,mcu_rdc";
+			    /* rdc config when MCU starts
+			     * master
+			     *   SDMA3p --> domain 1
+			     *   SDMA3b --> domian 1
+			     *   SDMA3_SPBA2  --> domian 1
+			     * peripheral:
+			     *   SAI3   --> Only Domian 1 can access
+			     *   UART4  --> Only Domian 1 can access
+			     *   GPT1   --> Only Domian 1 can access
+			     * memory:
+			     *   TCM    --> Only Domian 1 can access (0x7E0000~0x81FFFF)
+			     *   DDR    --> Only Domian 1 can access (0x80000000~0x81000000)
+			     * end.
+			     */
+		start-config = <
+			    RDC_MDA  RDC_MDA_SDMA3p DID1 0x0 0x0
+			    RDC_MDA  RDC_MDA_SDMA3b DID1 0x0 0x0
+			    RDC_MDA  RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0
+			    RDC_PDAP RDC_PDAP_SAI3  PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_UART4 PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_GPT1  PDAP_D1_ACCESS 0x0 0x0
+			    RDC_MEM_REGION 26 TCM_START TCM_END MEM_D1_ACCESS
+			    RDC_MEM_REGION 0 M4_EVK_DDR4_START M4_EVK_DDR4_END MEM_D1_ACCESS
+			    0x0      0x0            0x0  0x0 0x0
+			  >;
+			    /* rdc config when MCU stops
+			     * memory:
+			     *   TCM    --> domain 0/1 can access (0x7E0000~0x81FFFF)
+			     *   DDR    --> domain 0/1 can access (0x80000000~0x81000000)
+			     * end.
+			     */
+		stop-config = <
+			    RDC_MEM_REGION 26 TCM_START TCM_END MEM_D0D1_ACCESS
+			    RDC_MEM_REGION 0 M4_EVK_DDR4_START M4_EVK_DDR4_END MEM_D0D1_ACCESS
+			    0x0      0x0            0x0  0x0 0x0
+			  >;
+	};
 };
 
 &{/soc@0} {
@@ -56,12 +110,13 @@
 	u-boot,dm-spl;
 };
 
-&pinctrl_reg_usdhc2_vmmc {
+&reg_usdhc2_vmmc {
 	u-boot,dm-spl;
+	u-boot,off-on-delay-us = <20000>;
 };
 
-&reg_usdhc2_vmmc {
-	u-boot,off-on-delay-us = <20000>;
+&pinctrl_reg_usdhc2_vmmc {
+	u-boot,dm-spl;
 };
 
 &pinctrl_uart2 {
@@ -104,20 +159,45 @@
 	u-boot,dm-spl;
 };
 
+&crypto {
+	u-boot,dm-spl;
+};
+
+&sec_jr0 {
+	u-boot,dm-spl;
+};
+
+&sec_jr1 {
+	u-boot,dm-spl;
+};
+
+&sec_jr2 {
+	u-boot,dm-spl;
+};
+
 &usdhc1 {
 	u-boot,dm-spl;
+	assigned-clocks = <&clk IMX8MN_CLK_USDHC1>;
+	assigned-clock-rates = <400000000>;
+	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>;
 };
 
 &usdhc2 {
 	u-boot,dm-spl;
 	sd-uhs-sdr104;
 	sd-uhs-ddr50;
+	assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
+	assigned-clock-rates = <400000000>;
+	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>;
 };
 
 &usdhc3 {
 	u-boot,dm-spl;
 	mmc-hs400-1_8v;
 	mmc-hs400-enhanced-strobe;
+	assigned-clocks = <&clk IMX8MN_CLK_USDHC3>;
+	assigned-clock-rates = <400000000>;
+	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>;
 };
 
 &wdog1 {
@@ -242,3 +322,55 @@
 		};
 	};
 };
+
+&tmu {
+	u-boot,dm-pre-reloc;
+};
+
+&i2c1 {
+	u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
+	u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
+	u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_i2c1_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+	u-boot,dm-spl;
+};
+
+&fec1 {
+	phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+};
+
+&ethphy0 {
+	vddio0: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
+
+&lcdif {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
+};
+
+&mipi_dsi {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
+};
diff --git a/arch/arm/dts/imx8mn-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
index 3db46d4cbcb..f92c0f586f7 100644
--- a/arch/arm/dts/imx8mn-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-evk-u-boot.dtsi
@@ -3,25 +3,203 @@
  * Copyright 2019 NXP
  */
 
-#include "imx8mn-ddr4-evk-u-boot.dtsi"
+#include "imx8mn-sec-def.h"
 
-&i2c1 {
+/ {
+	binman: binman {
+		multiple-images;
+	};
+
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog1>;
+		u-boot,dm-spl;
+	};
+
+	aliases {
+		usbgadget0 = &usbg1;
+	};
+
+	usbg1: usbg1 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg1>;
+		status = "okay";
+	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+	mcu_rdc {
+		compatible = "imx8m,mcu_rdc";
+			    /* rdc config when MCU starts
+			     * master
+			     *   SDMA3p --> domain 1
+			     *   SDMA3b --> domian 1
+			     *   SDMA3_SPBA2  --> domian 1
+			     * peripheral:
+			     *   SAI3   --> Only Domian 1 can access
+			     *   UART4  --> Only Domian 1 can access
+			     *   GPT1   --> Only Domian 1 can access
+			     * memory:
+			     *   TCM    --> Only Domian 1 can access (0x7E0000~0x81FFFF)
+			     *   DDR    --> Only Domian 1 can access (0x80000000~0x81000000)
+			     * end.
+			     */
+		start-config = <
+			    RDC_MDA  RDC_MDA_SDMA3p DID1 0x0 0x0
+			    RDC_MDA  RDC_MDA_SDMA3b DID1 0x0 0x0
+			    RDC_MDA  RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0
+			    RDC_PDAP RDC_PDAP_SAI3  PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_UART4 PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_GPT1  PDAP_D1_ACCESS 0x0 0x0
+			    RDC_MEM_REGION 26 TCM_START TCM_END MEM_D1_ACCESS
+			    RDC_MEM_REGION 0 M4_EVK_DDR4_START M4_EVK_DDR4_END MEM_D1_ACCESS
+			    0x0      0x0            0x0  0x0 0x0
+			  >;
+			    /* rdc config when MCU stops
+			     * memory:
+			     *   TCM    --> domain 0/1 can access (0x7E0000~0x81FFFF)
+			     *   DDR    --> domain 0/1 can access (0x80000000~0x81000000)
+			     * end.
+			     */
+		stop-config = <
+			    RDC_MEM_REGION 26 TCM_START TCM_END MEM_D0D1_ACCESS
+			    RDC_MEM_REGION 0 M4_EVK_DDR4_START M4_EVK_DDR4_END MEM_D0D1_ACCESS
+			    0x0      0x0            0x0  0x0 0x0
+			  >;
+	};
+};
+
+&{/soc@0} {
+	u-boot,dm-pre-reloc;
 	u-boot,dm-spl;
 };
 
-&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
+&clk {
 	u-boot,dm-spl;
+	u-boot,dm-pre-reloc;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
 };
 
-&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
+&osc_24m {
 	u-boot,dm-spl;
+	u-boot,dm-pre-reloc;
 };
 
-&pinctrl_i2c1 {
+&aips1 {
 	u-boot,dm-spl;
+	u-boot,dm-pre-reloc;
 };
 
-&pinctrl_pmic {
+&aips2 {
+	u-boot,dm-spl;
+};
+
+&aips3 {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&reg_usdhc2_vmmc {
+	u-boot,dm-spl;
+	u-boot,off-on-delay-us = <20000>;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+	u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+};
+
+&gpio3 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&gpio5 {
+	u-boot,dm-spl;
+};
+
+&uart2 {
+	u-boot,dm-spl;
+};
+
+&crypto {
+	u-boot,dm-spl;
+};
+
+&sec_jr0 {
+	u-boot,dm-spl;
+};
+
+&sec_jr1 {
+	u-boot,dm-spl;
+};
+
+&sec_jr2 {
+	u-boot,dm-spl;
+};
+
+&usdhc1 {
+	u-boot,dm-spl;
+	assigned-clocks = <&clk IMX8MN_CLK_USDHC1>;
+	assigned-clock-rates = <400000000>;
+	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>;
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
+	assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
+	assigned-clock-rates = <400000000>;
+	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>;
+};
+
+&usdhc3 {
+	u-boot,dm-spl;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
+	assigned-clocks = <&clk IMX8MN_CLK_USDHC3>;
+	assigned-clock-rates = <400000000>;
+	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>;
+};
+
+&wdog1 {
 	u-boot,dm-spl;
 };
 
@@ -126,3 +304,55 @@
 		};
 	};
 };
+
+&tmu {
+	u-boot,dm-pre-reloc;
+};
+
+&i2c1 {
+	u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
+	u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
+	u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_i2c1_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+	u-boot,dm-spl;
+};
+
+&fec1 {
+	phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+};
+
+&ethphy0 {
+	vddio0: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
+
+&lcdif {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
+};
+
+&mipi_dsi {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
+};
diff --git a/arch/arm/dts/imx8mn-evk.dts b/arch/arm/dts/imx8mn-evk.dts
index cd11fb28f54..4d1c350f862 100644
--- a/arch/arm/dts/imx8mn-evk.dts
+++ b/arch/arm/dts/imx8mn-evk.dts
@@ -12,6 +12,11 @@
 / {
 	model = "NXP i.MX8MNano EVK board";
 	compatible = "fsl,imx8mn-evk", "fsl,imx8mn";
+
+	chosen {
+		bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
+	};
+
 };
 
 &A53_0 {
diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi
index 416fadb22b1..d533520efa9 100644
--- a/arch/arm/dts/imx8mn-evk.dtsi
+++ b/arch/arm/dts/imx8mn-evk.dtsi
@@ -8,6 +8,7 @@
 
 / {
 	chosen {
+		bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
 		stdout-path = &uart2;
 	};
 
@@ -46,6 +47,32 @@
 		pinctrl-0 = <&pinctrl_ir>;
 		linux,autosuspend-period = <125>;
 	};
+
+	dsi_host: dsi-host {
+		compatible = "samsung,sec-mipi-dsi";
+		status = "okay";
+	};
+
+	rm67199_panel {
+		compatible = "raydium,rm67199";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_mipi_dsi_en>;
+		reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
+		dsi-lanes = <4>;
+		video-mode = <2>;	/* 0: burst mode
+					 * 1: non-burst mode with sync event
+					 * 2: non-burst mode with sync pulse
+					 */
+		panel-width-mm = <68>;
+		panel-height-mm = <121>;
+		status = "okay";
+
+		port {
+			rm67191_from_dsim: endpoint {
+				remote-endpoint = <&dsim_to_rm67191>;
+			};
+		};
+	};
 };
 
 &fec1 {
@@ -70,17 +97,37 @@
 
 &i2c1 {
 	clock-frequency = <400000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
 
 &i2c2 {
 	clock-frequency = <400000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
+	adv_bridge: adv7535@3d {
+		compatible = "adi,adv7535";
+		reg = <0x3d>;
+		adi,addr-cec = <0x3c>;
+		adi,dsi-lanes = <4>;
+		status = "okay";
+
+		port {
+			adv7535_from_dsim: endpoint {
+				remote-endpoint = <&dsim_to_adv7535>;
+			};
+		};
+	};
+
 	ptn5110: tcpc@50 {
 		compatible = "nxp,ptn5110";
 		pinctrl-names = "default";
@@ -112,9 +159,12 @@
 };
 
 &i2c3 {
-	clock-frequency = <400000>;
-	pinctrl-names = "default";
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
 	pca6416: gpio@20 {
@@ -125,6 +175,46 @@
 	};
 };
 
+&flexspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi0>;
+	status = "okay";
+
+	flash0: mt25qu256aba@0 {
+		reg = <0>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <80000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
+&lcdif {
+	display = <&display0>;
+	status = "okay";
+
+	display0: display@0 {
+		bits-per-pixel = <24>;
+		bus-width = <24>;
+	};
+};
+
+&mipi_dsi {
+	status = "okay";
+
+	port@1 {
+		dsim_to_adv7535: endpoint {
+			remote-endpoint = <&adv7535_from_dsim>;
+		};
+	};
+
+	port@2 {
+		dsim_to_rm67191: endpoint {
+			remote-endpoint = <&rm67191_from_dsim>;
+		};
+	};
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };
@@ -141,9 +231,11 @@
 	srp-disable;
 	adp-disable;
 	usb-role-switch;
+	disable-over-current;
 	samsung,picophy-pre-emp-curr-control = <3>;
 	samsung,picophy-dc-vol-level-adjust = <7>;
 	status = "okay";
+	extcon = <&ptn5110>;
 
 	port {
 		usb1_drd_sw: endpoint {
@@ -205,6 +297,18 @@
 		>;
 	};
 
+	pinctrl_flexspi0: flexspi0grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4
+			MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84
+			MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x40000084
+			MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
+			MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
+			MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
+			MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
+		>;
+	};
+
 	pinctrl_gpio_led: gpioledgrp {
 		fsl,pins = <
 			MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
@@ -238,6 +342,27 @@
 		>;
 	};
 
+	pinctrl_i2c1_gpio: i2c1grp-gpio {
+		fsl,pins = <
+			MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14        	0x1c3
+			MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15        	0x1c3
+		>;
+	};
+
+	pinctrl_i2c2_gpio: i2c2grp-gpio {
+		fsl,pins = <
+			MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16		0x1c3
+			MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17		0x1c3
+		>;
+	};
+
+	pinctrl_i2c3_gpio: i2c3grp-gpio {
+		fsl,pins = <
+			MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18		0x1c3
+			MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19		0x1c3
+		>;
+	};
+
 	pinctrl_pmic: pmicirqgrp {
 		fsl,pins = <
 			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x141
@@ -358,4 +483,10 @@
 			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x166
 		>;
 	};
+
+	pinctrl_mipi_dsi_en: mipi_dsi_en {
+		fsl,pins = <
+			MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x16
+		>;
+	};
 };
diff --git a/arch/arm/dts/imx8mn-sec-def.h b/arch/arm/dts/imx8mn-sec-def.h
new file mode 100644
index 00000000000..03a16ada67a
--- /dev/null
+++ b/arch/arm/dts/imx8mn-sec-def.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef IMX8MN_SEC_DEF_H
+#define IMX8MN_SEC_DEF_H
+
+/* Domain ID */
+#define DID0            0x0
+#define DID1            0x1
+#define DID2            0x2
+#define DID3            0x3
+
+/* Domain RD/WR permission */
+#define LOCK           0x80000000
+#define ENA            0x40000000
+#define D3R            0x00000080
+#define D3W            0x00000040
+#define D2R            0x00000020
+#define D2W            0x00000010
+#define D1R            0x00000008
+#define D1W            0x00000004
+#define D0R            0x00000002
+#define D0W            0x00000001
+
+#define PDAP_D1_ACCESS 0x0000000C /* D1W|D1R */
+#define MEM_D1_ACCESS  0x4000000C /* ENA|D1W|D1R */
+#define MEM_D0D1_ACCESS  0x4000000F /* ENA|D0W|D0R|D1W|D1R */
+
+/* RDC type */
+#define RDC_INVALID 0
+#define RDC_MDA 1
+#define RDC_PDAP 2
+#define RDC_MEM_REGION 3
+
+/* RDC MDA index */
+#define RDC_MDA_A53  0
+#define RDC_MDA_M7  1
+#define RDC_MDA_SDMA3p  3
+#define RDC_MDA_LCDIF1  5
+#define RDC_MDA_ISI  6
+#define RDC_MDA_SDMA3b  7
+#define RDC_MDA_Coresight  8
+#define RDC_MDA_DAP  9
+#define RDC_MDA_CAAM  10
+#define RDC_MDA_SDMA1p  11
+#define RDC_MDA_SDMA1b  12
+#define RDC_MDA_APBHDMA  13
+#define RDC_MDA_RAWNAND  14
+#define RDC_MDA_uSDHC1  15
+#define RDC_MDA_uSDHC2  16
+#define RDC_MDA_uSDHC3  17
+#define RDC_MDA_GPU  18
+#define RDC_MDA_USB1 19
+#define RDC_MDA_TESTPORT 21
+#define RDC_MDA_ENET1_TX 22
+#define RDC_MDA_ENET1_RX 23
+#define RDC_MDA_SDMA2 24
+#define RDC_MDA_SDMA3_SPBA2 25
+
+/* RDC Peripherals index */
+#define RDC_PDAP_GPIO1  0
+#define RDC_PDAP_GPIO2  1
+#define RDC_PDAP_GPIO3  2
+#define RDC_PDAP_GPIO4  3
+#define RDC_PDAP_GPIO5  4
+#define RDC_PDAP_ANA_TSENSOR  6
+#define RDC_PDAP_ANA_OSC  7
+#define RDC_PDAP_WDOG1  8
+#define RDC_PDAP_WDOG2  9
+#define RDC_PDAP_WDOG3  10
+#define RDC_PDAP_SDMA2  12
+#define RDC_PDAP_GPT1  13
+#define RDC_PDAP_GPT2  14
+#define RDC_PDAP_GPT3  15
+#define RDC_PDAP_ROMCP  17
+#define RDC_PDAP_IOMUXC  19
+#define RDC_PDAP_IOMUXC_GPR  20
+#define RDC_PDAP_OCOTP_CTRL  21
+#define RDC_PDAP_ANA_PLL  22
+#define RDC_PDAP_SNVS_HP  23
+#define RDC_PDAP_CCM  24
+#define RDC_PDAP_SRC  25
+#define RDC_PDAP_GPC  26
+#define RDC_PDAP_SEMAPHORE1  27
+#define RDC_PDAP_SEMAPHORE2  28
+#define RDC_PDAP_RDC  29
+#define RDC_PDAP_CSU  30
+#define RDC_PDAP_LCDIF  32
+#define RDC_PDAP_MIPI_DSI  33
+#define RDC_PDAP_ISI  34
+#define RDC_PDAP_MIPI_CSI  35
+#define RDC_PDAP_USB1  36
+#define RDC_PDAP_PWM1  38
+#define RDC_PDAP_PWM2  39
+#define RDC_PDAP_PWM3  40
+#define RDC_PDAP_PWM4  41
+#define RDC_PDAP_System_Counter_RD  42
+#define RDC_PDAP_System_Counter_CMP  43
+#define RDC_PDAP_System_Counter_CTRL  44
+#define RDC_PDAP_GPT6  46
+#define RDC_PDAP_GPT5  47
+#define RDC_PDAP_GPT4  48
+#define RDC_PDAP_TZASC  56
+#define RDC_PDAP_PERFMON1  60
+#define RDC_PDAP_PERFMON2  61
+#define RDC_PDAP_PLATFORM_CTRL  62
+#define RDC_PDAP_QoSC  63
+#define RDC_PDAP_I2C1  66
+#define RDC_PDAP_I2C2  67
+#define RDC_PDAP_I2C3  68
+#define RDC_PDAP_I2C4  69
+#define RDC_PDAP_UART4  70
+#define RDC_PDAP_MU_A  74
+#define RDC_PDAP_MU_B  75
+#define RDC_PDAP_SEMAPHORE_HS  76
+#define RDC_PDAP_SAI2  79
+#define RDC_PDAP_SAI3  80
+#define RDC_PDAP_SAI5  82
+#define RDC_PDAP_SAI6  83
+#define RDC_PDAP_uSDHC1  84
+#define RDC_PDAP_uSDHC2  85
+#define RDC_PDAP_uSDHC3  86
+#define RDC_PDAP_SAI7  87
+#define RDC_PDAP_SPBA2  90
+#define RDC_PDAP_QSPI  91
+#define RDC_PDAP_SDMA1  93
+#define RDC_PDAP_ENET1  94
+#define RDC_PDAP_SPDIF1  97
+#define RDC_PDAP_eCSPI1  98
+#define RDC_PDAP_eCSPI2  99
+#define RDC_PDAP_eCSPI3  100
+#define RDC_PDAP_MICFIL  101
+#define RDC_PDAP_UART1  102
+#define RDC_PDAP_UART3  104
+#define RDC_PDAP_UART2  105
+#define RDC_PDAP_ASRC  107
+#define RDC_PDAP_SPBA1  111
+#define RDC_PDAP_CAAM  114
+
+/* RDC MEMORY REGION */
+#define TCM_START 0x7E0000
+#define TCM_END   0x820000
+
+#define M4_EVK_DDR4_START 0x20000000
+#define M4_EVK_DDR4_END 0x20800000
+
+#define M4_EVK_DDR3L_START 0x1B800000
+#define M4_EVK_DDR3L_END 0x1C000000
+
+#endif /* IMX8MN_SEC_DEF_H */
diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi
index edcb415b53d..c0b82e3d7da 100644
--- a/arch/arm/dts/imx8mn.dtsi
+++ b/arch/arm/dts/imx8mn.dtsi
@@ -4,10 +4,9 @@
  */
 
 #include <dt-bindings/clock/imx8mn-clock.h>
-#include <dt-bindings/power/imx8mn-power.h>
-#include <dt-bindings/reset/imx8mq-reset.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
+#include <dt-bindings/reset/imx8mn-dispmix.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/thermal/thermal.h>
 
@@ -36,9 +35,9 @@
 		serial1 = &uart2;
 		serial2 = &uart3;
 		serial3 = &uart4;
-		spi0 = &ecspi1;
-		spi1 = &ecspi2;
-		spi2 = &ecspi3;
+		spi0 = &flexspi;
+		usb0 = &usbotg1;
+		video0 = &lcdif;
 	};
 
 	cpus {
@@ -146,6 +145,21 @@
 		};
 	};
 
+	resmem: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0 0x28000000>;
+			alloc-ranges = <0 0x40000000 0 0x40000000>;
+			linux,cma-default;
+		};
+	};
+
 	osc_32k: clock-osc-32k {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -188,11 +202,76 @@
 		clock-output-names = "clk_ext4";
 	};
 
+	busfreq { /* BUSFREQ */
+		compatible = "fsl,imx_busfreq";
+		clocks = <&clk IMX8MN_DRAM_PLL_OUT>, <&clk IMX8MN_CLK_DRAM_ALT>,
+			 <&clk IMX8MN_CLK_DRAM_APB>, <&clk IMX8MN_CLK_DRAM_APB>,
+			 <&clk IMX8MN_CLK_DRAM_CORE>, <&clk IMX8MN_CLK_DRAM_ALT_ROOT>,
+			 <&clk IMX8MN_SYS_PLL1_40M>, <&clk IMX8MN_SYS_PLL1_100M>,
+			 <&clk IMX8MN_SYS_PLL2_333M>, <&clk IMX8MN_CLK_NOC>,
+			 <&clk IMX8MN_CLK_AHB>, <&clk IMX8MN_CLK_MAIN_AXI>,
+			 <&clk IMX8MN_CLK_24M>, <&clk IMX8MN_SYS_PLL1_800M>,
+			 <&clk IMX8MN_DRAM_PLL>;
+		clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div",
+			      "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m",
+			      "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m",
+			      "sys_pll1_800m", "dram_pll_div";
+	};
+
+	power-domains {
+		compatible = "simple-bus";
+
+		/* HSIOMIX */
+		hsiomix_pd: hsiomix-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			domain-index = <0>;
+			#power-domain-cells = <0>;
+			domain-name = "hsiomix";
+			clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
+		};
+
+		usb_otg1_pd: usbotg1-pd{
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <2>;
+			domain-name = "usb_otg1";
+			parent-domains = <&hsiomix_pd>;
+		};
+
+		/* GPU2D&3D */
+		gpumix_pd: gpumix-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			domain-index = <4>;
+			#power-domain-cells = <0>;
+			domain-name = "gpumix";
+			clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
+				 <&clk IMX8MN_CLK_GPU_SHADER_DIV>,
+				 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
+				 <&clk IMX8MN_CLK_GPU_AHB>;
+		};
+
+		dispmix_pd: dispmix-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			domain-index = <9>;
+			#power-domain-cells = <0>;
+			domain-name = "dispmix";
+			clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+				 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
+		};
+
+		mipi_pd: mipi-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			domain-index = <10>;
+			#power-domain-cells = <0>;
+			domain-name = "mipi";
+			parent-domains = <&dispmix_pd>;
+		};
+	};
+
 	pmu {
 		compatible = "arm,cortex-a53-pmu";
 		interrupts = <GIC_PPI 7
 			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-		interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
 	};
 
 	psci {
@@ -200,7 +279,7 @@
 		method = "smc";
 	};
 
-	thermal-zones {
+	thermal: thermal-zones {
 		cpu-thermal {
 			polling-delay-passive = <250>;
 			polling-delay = <2000>;
@@ -242,14 +321,60 @@
 		arm,no-tick-in-suspend;
 	};
 
+	lcdif_resets: lcdif-resets {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#reset-cells = <0>;
+
+		lcdif-soft-resetn {
+			compatible = "lcdif,soft-resetn";
+			resets = <&dispmix_sft_rstn IMX8MN_LCDIF_APB_CLK_RESET>,
+				 <&dispmix_sft_rstn IMX8MN_LCDIF_PIXEL_CLK_RESET>;
+		};
+
+		lcdif-clk-enable {
+			compatible = "lcdif,clk-enable";
+			resets = <&dispmix_clk_en IMX8MN_LCDIF_APB_CLK_EN>,
+				 <&dispmix_clk_en IMX8MN_LCDIF_PIXEL_CLK_EN>;
+		};
+	};
+
+	mipi_dsi_resets: mipi-dsi-resets {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#reset-cells = <0>;
+
+		dsi-soft-resetn {
+			compatible = "dsi,soft-resetn";
+			resets = <&dispmix_sft_rstn IMX8MN_MIPI_DSI_CLKREF_RESET>,
+				 <&dispmix_sft_rstn IMX8MN_MIPI_DSI_PCLK_RESET>;
+		};
+
+		dsi-clk-enable {
+			compatible = "dsi,clk-enable";
+			resets = <&dispmix_clk_en IMX8MN_MIPI_DSI_CLKREF_EN>,
+				 <&dispmix_clk_en IMX8MN_MIPI_DSI_PCLK_EN>;
+		};
+
+		dsi-mipi-reset {
+			compatible = "dsi,mipi-reset";
+			resets = <&dispmix_mipi_rst IMX8MN_MIPI_M_RESET>;
+		};
+	};
 	soc@0 {
-		compatible = "fsl,imx8mn-soc", "simple-bus";
+		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0x0 0x0 0x0 0x3e000000>;
+		dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
 		nvmem-cells = <&imx8mn_uid>;
 		nvmem-cell-names = "soc_unique_id";
 
+		caam_sm: caam-sm@00100000 {
+			compatible = "fsl,imx6q-caam-sm";
+			reg = <0x100000 0x8000>;
+		};
+
 		aips1: bus@30000000 {
 			compatible = "fsl,aips-bus", "simple-bus";
 			reg = <0x30000000 0x400000>;
@@ -257,7 +382,7 @@
 			#size-cells = <1>;
 			ranges;
 
-			spba: spba-bus@30000000 {
+			spba2: spba-bus@30000000 {
 				compatible = "fsl,spba-bus", "simple-bus";
 				#address-cells = <1>;
 				#size-cells = <1>;
@@ -497,7 +622,7 @@
 			};
 
 			sdma3: dma-controller@302b0000 {
-				compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
+				compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
 				reg = <0x302b0000 0x10000>;
 				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
@@ -508,7 +633,7 @@
 			};
 
 			sdma2: dma-controller@302c0000 {
-				compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
+				compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
 				reg = <0x302c0000 0x10000>;
 				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
@@ -529,7 +654,7 @@
 			};
 
 			ocotp: efuse@30350000 {
-				compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
+				compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon", "simple-mfd";
 				reg = <0x30350000 0x10000>;
 				clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
 				#address-cells = <1>;
@@ -546,6 +671,12 @@
 				fec_mac_address: mac-address@90 {
 					reg = <0x90 6>;
 				};
+
+				imx8mn_soc: imx8mn-soc {
+					compatible = "fsl,imx8mn-soc";
+					nvmem-cells = <&imx8mn_uid>;
+					nvmem-cell-names = "soc_unique_id";
+				};
 			};
 
 			anatop: anatop@30360000 {
@@ -554,9 +685,26 @@
 				reg = <0x30360000 0x10000>;
 			};
 
+			irq_sec_vio: caam_secvio {
+				compatible = "fsl,imx6q-caam-secvio";
+				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+				jtag-tamper = "disabled";
+				watchdog-tamper = "enabled";
+				internal-boot-tamper = "enabled";
+				external-pin-tamper = "disabled";
+			};
+
+			caam_snvs: caam-snvs@30370000 {
+				compatible = "fsl,imx6q-caam-snvs";
+				reg = <0x30370000 0x10000>;
+				clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
+				clock-names = "ipg";
+			};
+
 			snvs: snvs@30370000 {
 				compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
 				reg = <0x30370000 0x10000>;
+				status = "disabled";
 
 				snvs_rtc: snvs-rtc-lp {
 					compatible = "fsl,sec-v4.0-mon-rtc-lp";
@@ -566,6 +714,7 @@
 						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 					clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
 					clock-names = "snvs-rtc";
+					status = "disabled";
 				};
 
 				snvs_pwrkey: snvs-powerkey {
@@ -614,54 +763,6 @@
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 				#reset-cells = <1>;
 			};
-
-			gpc: gpc@303a0000 {
-				compatible = "fsl,imx8mn-gpc";
-				reg = <0x303a0000 0x10000>;
-				interrupt-parent = <&gic>;
-				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
-
-				pgc {
-					#address-cells = <1>;
-					#size-cells = <0>;
-
-					pgc_hsiomix: power-domain@0 {
-						#power-domain-cells = <0>;
-						reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>;
-						clocks = <&clk IMX8MN_CLK_USB_BUS>;
-					};
-
-					pgc_otg1: power-domain@1 {
-						#power-domain-cells = <0>;
-						reg = <IMX8MN_POWER_DOMAIN_OTG1>;
-						power-domains = <&pgc_hsiomix>;
-					};
-
-					pgc_gpumix: power-domain@2 {
-						#power-domain-cells = <0>;
-						reg = <IMX8MN_POWER_DOMAIN_GPUMIX>;
-						clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
-							 <&clk IMX8MN_CLK_GPU_SHADER_DIV>,
-							 <&clk IMX8MN_CLK_GPU_BUS_ROOT>,
-							 <&clk IMX8MN_CLK_GPU_AHB>;
-						resets = <&src IMX8MQ_RESET_GPU_RESET>;
-					};
-
-					dispmix_pd: power-domain@3 {
-						#power-domain-cells = <0>;
-						reg = <IMX8MN_POWER_DOMAIN_DISPMIX>;
-						clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
-							 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
-							 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
-					};
-
-					mipi_pd: power-domain@4 {
-						#power-domain-cells = <0>;
-						reg = <IMX8MN_POWER_DOMAIN_MIPI>;
-						power-domains = <&dispmix_pd>;
-					};
-				};
-			};
 		};
 
 		aips2: bus@30400000 {
@@ -731,80 +832,88 @@
 			#size-cells = <1>;
 			ranges;
 
-			ecspi1: spi@30820000 {
-				compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
+			spba1: spba-bus@30800000 {
+				compatible = "fsl,spba-bus", "simple-bus";
 				#address-cells = <1>;
-				#size-cells = <0>;
-				reg = <0x30820000 0x10000>;
-				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
-					 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
-				clock-names = "ipg", "per";
-				dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
-				dma-names = "rx", "tx";
-				status = "disabled";
-			};
+				#size-cells = <1>;
+				reg = <0x30800000 0x100000>;
+				ranges;
 
-			ecspi2: spi@30830000 {
-				compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reg = <0x30830000 0x10000>;
-				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
-					 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
-				clock-names = "ipg", "per";
-				dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
-				dma-names = "rx", "tx";
-				status = "disabled";
-			};
+				ecspi1: spi@30820000 {
+					compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x30820000 0x10000>;
+					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
+						 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
+					clock-names = "ipg", "per";
+					dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
 
-			ecspi3: spi@30840000 {
-				compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
-				#address-cells = <1>;
-				#size-cells = <0>;
-				reg = <0x30840000 0x10000>;
-				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
-					 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
-				clock-names = "ipg", "per";
-				dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
-				dma-names = "rx", "tx";
-				status = "disabled";
-			};
+				ecspi2: spi@30830000 {
+					compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x30830000 0x10000>;
+					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
+						 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
+					clock-names = "ipg", "per";
+					dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
 
-			uart1: serial@30860000 {
-				compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
-				reg = <0x30860000 0x10000>;
-				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
-					 <&clk IMX8MN_CLK_UART1_ROOT>;
-				clock-names = "ipg", "per";
-				dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
-				dma-names = "rx", "tx";
-				status = "disabled";
-			};
+				ecspi3: spi@30840000 {
+					compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x30840000 0x10000>;
+					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
+						 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
+					clock-names = "ipg", "per";
+					dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
 
-			uart3: serial@30880000 {
-				compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
-				reg = <0x30880000 0x10000>;
-				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
-					 <&clk IMX8MN_CLK_UART3_ROOT>;
-				clock-names = "ipg", "per";
-				dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
-				dma-names = "rx", "tx";
-				status = "disabled";
-			};
+				uart1: serial@30860000 {
+					compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
+					reg = <0x30860000 0x10000>;
+					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
+						 <&clk IMX8MN_CLK_UART1_ROOT>;
+					clock-names = "ipg", "per";
+					dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
 
-			uart2: serial@30890000 {
-				compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
-				reg = <0x30890000 0x10000>;
-				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
-					 <&clk IMX8MN_CLK_UART2_ROOT>;
-				clock-names = "ipg", "per";
-				status = "disabled";
+				uart3: serial@30880000 {
+					compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
+					reg = <0x30880000 0x10000>;
+					interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
+						 <&clk IMX8MN_CLK_UART3_ROOT>;
+					clock-names = "ipg", "per";
+					dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
+					dma-names = "rx", "tx";
+					status = "disabled";
+				};
+
+				uart2: serial@30890000 {
+					compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
+					reg = <0x30890000 0x10000>;
+					interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
+						 <&clk IMX8MN_CLK_UART2_ROOT>;
+					clock-names = "ipg", "per";
+					status = "disabled";
+				};
 			};
 
 			crypto: crypto@30900000 {
@@ -822,6 +931,7 @@
 					 compatible = "fsl,sec-v4.0-job-ring";
 					 reg = <0x1000 0x1000>;
 					 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+					 status = "disabled";
 				};
 
 				sec_jr1: jr@2000 {
@@ -894,6 +1004,7 @@
 				reg = <0x30aa0000 0x10000>;
 				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX8MN_CLK_MU_ROOT>;
+				clock-names = "mu";
 				#mbox-cells = <2>;
 			};
 
@@ -948,12 +1059,15 @@
 				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX8MN_CLK_QSPI_ROOT>,
 					 <&clk IMX8MN_CLK_QSPI_ROOT>;
-				clock-names = "fspi", "fspi_en";
+				clock-names = "fspi_en", "fspi";
+				assigned-clock-rates = <80000000>;
+				assigned-clocks = <&clk IMX8MN_CLK_QSPI>;
+				assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>;
 				status = "disabled";
 			};
 
 			sdma1: dma-controller@30bd0000 {
-				compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
+				compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma", "fsl,imx7d-sdma";
 				reg = <0x30bd0000 0x10000>;
 				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
@@ -964,7 +1078,7 @@
 			};
 
 			fec1: ethernet@30be0000 {
-				compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
+				compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
 				reg = <0x30be0000 0x10000>;
 				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
@@ -992,6 +1106,7 @@
 				nvmem-cell-names = "mac-address";
 				nvmem_macaddr_swap;
 				fsl,stop-mode = <&gpr 0x10 3>;
+				fsl,wakeup_irq = <2>;
 				status = "disabled";
 			};
 
@@ -1004,17 +1119,81 @@
 			#size-cells = <1>;
 			ranges;
 
+			lcdif: lcd-controller@32e00000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8mn-lcdif";
+				reg = <0x32e00000 0x10000>;
+				clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
+					 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+					 <&clk IMX8MN_CLK_DISP_APB_ROOT>;
+				clock-names = "pix", "disp-axi", "disp-apb";
+				assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL>,
+						  <&clk IMX8MN_CLK_DISP_AXI>,
+						  <&clk IMX8MN_CLK_DISP_APB>;
+				assigned-clock-parents = <&clk IMX8MN_VIDEO_PLL1_OUT>,
+							 <&clk IMX8MN_SYS_PLL2_1000M>,
+							 <&clk IMX8MN_SYS_PLL1_800M>;
+				assigned-clock-rates = <594000000>,
+						      <500000000>,
+						      <200000000>;
+				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&lcdif_resets>;
+				power-domains = <&dispmix_pd>;
+				status = "disabled";
+
+				lcdif_disp0: port@0 {
+					reg = <0>;
+
+					lcdif_to_dsim: endpoint {
+						remote-endpoint = <&dsim_from_lcdif>;
+					};
+				};
+			};
+
+			mipi_dsi: dsi_controller@32e10000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8mn-mipi-dsim";
+				reg = <0x32e10000 0x400>;
+				clocks = <&clk IMX8MN_CLK_DSI_CORE>,
+					 <&clk IMX8MN_CLK_DSI_PHY_REF>;
+				clock-names = "cfg", "pll-ref";
+				assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
+						  <&clk IMX8MN_CLK_DSI_PHY_REF>;
+				assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
+							 <&clk IMX8MN_VIDEO_PLL1_OUT>;
+				assigned-clock-rates = <266000000>,
+						       <594000000>;
+				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&mipi_dsi_resets>;
+				power-domains = <&mipi_pd>;
+				status = "disabled";
+
+				port@0 {
+					dsim_from_lcdif: endpoint {
+						remote-endpoint = <&lcdif_to_dsim>;
+					};
+				};
+			};
+
+			display-subsystem {
+				compatible = "fsl,imx-display-subsystem";
+				ports = <&lcdif_disp0>;
+			};
+
 			usbotg1: usb@32e40000 {
-				compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
+				compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
 				reg = <0x32e40000 0x200>;
 				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
 				clock-names = "usb1_ctrl_root_clk";
-				assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
-				assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
+				assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
+						  <&clk IMX8MN_CLK_USB_CORE_REF>;
+				assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
+							 <&clk IMX8MN_SYS_PLL1_100M>;
 				phys = <&usbphynop1>;
 				fsl,usbmisc = <&usbmisc1 0>;
-				power-domains = <&pgc_otg1>;
 				status = "disabled";
 			};
 
@@ -1080,6 +1259,38 @@
 		};
 	};
 
+	gpu: gpu@38000000 {
+		compatible = "fsl,imx8mn-gpu", "fsl,imx6q-gpu";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		reg = <0x0 0x38000000 0x0 0x40000>,
+			 <0x0 0x40000000 0x0 0x80000000>,
+			 <0x0 0x0 0x0 0x8000000>;
+		reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem";
+		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "irq_3d";
+		clocks =	<&clk IMX8MN_CLK_GPU_CORE_ROOT>,
+				<&clk IMX8MN_CLK_GPU_SHADER_DIV>,
+				<&clk IMX8MN_CLK_GPU_BUS_ROOT>,
+				<&clk IMX8MN_CLK_GPU_AHB>;
+		clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk";
+		assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE_SRC>,
+			<&clk IMX8MN_CLK_GPU_SHADER_SRC>,
+			<&clk IMX8MN_CLK_GPU_AXI>,
+			<&clk IMX8MN_CLK_GPU_AHB>,
+			<&clk IMX8MN_GPU_PLL>,
+			<&clk IMX8MN_CLK_GPU_CORE_DIV>,
+			<&clk IMX8MN_CLK_GPU_SHADER_DIV>;
+		assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
+			<&clk IMX8MN_GPU_PLL_OUT>,
+			<&clk IMX8MN_SYS_PLL1_800M>,
+			<&clk IMX8MN_SYS_PLL1_800M>;
+		assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>,
+			<600000000>, <600000000>;
+		power-domains = <&gpumix_pd>;
+		status = "disabled";
+	};
+
 	usbphynop1: usbphynop1 {
 		#phy-cells = <0>;
 		compatible = "usb-nop-xceiv";
@@ -1088,4 +1299,40 @@
 		assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
 		clock-names = "main_clk";
 	};
+
+	dispmix-reset {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		dispmix_sft_rstn: dispmix-sft-rstn@32e28000 {
+			compatible = "fsl,imx8mn-dispmix-sft-rstn";
+			reg = <0x0 0x32e28000 0x0 0x4>;
+			clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>;
+			clock-names = "disp_apb_root_clk";
+			active_low;
+			power-domains = <&dispmix_pd>;
+			#reset-cells = <1>;
+		};
+
+		dispmix_clk_en: dispmix-clk-en@32e28004 {
+			compatible = "fsl,imx8mn-dispmix-clk-en";
+			reg = <0x0 0x32e28004 0x0 0x4>;
+			clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>;
+			clock-names = "disp_apb_root_clk";
+			power-domains = <&dispmix_pd>;
+			#reset-cells = <1>;
+		};
+
+		dispmix_mipi_rst: dispmix-mipi-rst@32e28008 {
+			compatible = "fsl,imx8mn-dispmix-mipi-rst";
+			reg = <0x0 0x32e28008 0x0 0x4>;
+			clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>;
+			clock-names = "disp_apb_root_clk";
+			active_low;
+			power-domains = <&dispmix_pd>;
+			#reset-cells = <1>;
+		};
+	};
 };
diff --git a/arch/arm/dts/imx8mp-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-ddr4-evk-u-boot.dtsi
new file mode 100644
index 00000000000..d757eecf0d9
--- /dev/null
+++ b/arch/arm/dts/imx8mp-ddr4-evk-u-boot.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include "imx8mp-evk-u-boot.dtsi"
+
+&blob_1 {
+	filename = "ddr4_imem_1d_202006.bin";
+};
+
+&blob_2 {
+	filename = "ddr4_dmem_1d_202006.bin";
+};
+
+&blob_3 {
+	filename = "ddr4_imem_2d_202006.bin";
+};
+
+&blob_4 {
+	filename = "ddr4_dmem_2d_202006.bin";
+};
\ No newline at end of file
diff --git a/arch/arm/dts/imx8mp-ddr4-evk.dts b/arch/arm/dts/imx8mp-ddr4-evk.dts
new file mode 100644
index 00000000000..a67df09e7d2
--- /dev/null
+++ b/arch/arm/dts/imx8mp-ddr4-evk.dts
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Copyright 2020 NXP
+  */
+
+#include "imx8mp-evk.dts"
+
+/ {
+	model = "NXP i.MX8MPlus DDR4 EVK board";
+};
+
+&flexspi {
+	status = "disabled";
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "okay";
+	nand-on-flash-bbt;
+	fsl,use-minimum-ecc;
+};
+
+&usdhc3 {
+	status = "disabled";
+};
+
+&iomuxc {
+	pinctrl_gpmi_nand_1: gpmi-nand-1 {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_ALE__NAND_ALE		0x00000096
+			MX8MP_IOMUXC_NAND_CE0_B__NAND_CE0_B		0x00000096
+			MX8MP_IOMUXC_NAND_CE1_B__NAND_CE1_B		0x00000096
+			MX8MP_IOMUXC_NAND_CE2_B__NAND_CE2_B		0x00000096
+			MX8MP_IOMUXC_NAND_CE3_B__NAND_CE3_B		0x00000096
+			MX8MP_IOMUXC_NAND_CLE__NAND_CLE		0x00000096
+			MX8MP_IOMUXC_NAND_DATA00__NAND_DATA00		0x00000096
+			MX8MP_IOMUXC_NAND_DATA01__NAND_DATA01		0x00000096
+			MX8MP_IOMUXC_NAND_DATA02__NAND_DATA02		0x00000096
+			MX8MP_IOMUXC_NAND_DATA03__NAND_DATA03		0x00000096
+			MX8MP_IOMUXC_NAND_DATA04__NAND_DATA04		0x00000096
+			MX8MP_IOMUXC_NAND_DATA05__NAND_DATA05		0x00000096
+			MX8MP_IOMUXC_NAND_DATA06__NAND_DATA06		0x00000096
+			MX8MP_IOMUXC_NAND_DATA07__NAND_DATA07		0x00000096
+			MX8MP_IOMUXC_NAND_RE_B__NAND_RE_B		0x00000096
+			MX8MP_IOMUXC_NAND_READY_B__NAND_READY_B	0x00000056
+			MX8MP_IOMUXC_NAND_WE_B__NAND_WE_B		0x00000096
+			MX8MP_IOMUXC_NAND_WP_B__NAND_WP_B		0x00000096
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index ab849ebaaca..203d05e66ea 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -1,7 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
  */
+#include "imx8mp-sec-def.h"
 
 #include "imx8mp-u-boot.dtsi"
 
@@ -17,14 +18,62 @@
 			method = "smc";
 		};
 	};
+
+	mcu_rdc {
+		compatible = "imx8m,mcu_rdc";
+			    /* rdc config when MCU starts
+			     * master
+			     *   SDMA3p --> domain 1
+			     *   SDMA3b --> domian 1
+			     *   SDMA3_SPBA2  --> domian 1
+			     * peripheral:
+			     *   SAI3   --> Only Domian 1 can access
+			     *   UART4  --> Only Domian 1 can access
+			     *   GPT1   --> Only Domian 1 can access
+			     *   SDMA3  --> Only Domian 1 can access
+			     *   I2C3   --> Only Domian 1 can access
+			     * memory:
+			     *   TCM    --> Only Domian 1 can access (0x7E0000~0x81FFFF)
+			     *   DDR    --> Only Domian 1 can access (0x80000000~0x81000000)
+			     * end.
+			     */
+		start-config = <
+			    RDC_MDA  RDC_MDA_SDMA3p DID1 0x0 0x0
+			    RDC_MDA  RDC_MDA_ENET1_TX DID1 0x0 0x0
+			    RDC_MDA  RDC_MDA_ENET1_RX DID1 0x0 0x0
+			    RDC_MDA  RDC_MDA_SDMA3b DID1 0x0 0x0
+			    RDC_MDA  RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0
+			    RDC_PDAP RDC_PDAP_ENET1 PDAP_D0D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_SAI3  PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_UART4 PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_GPT1  PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_SDMA3 PDAP_D1_ACCESS 0x0 0x0
+			    RDC_PDAP RDC_PDAP_I2C3  PDAP_D1_ACCESS 0x0 0x0
+			    RDC_MEM_REGION 22 TCM_START TCM_END MEM_D1_ACCESS
+			    RDC_MEM_REGION 39 M4_DDR_START M4_DDR_END MEM_D1_ACCESS
+			    0x0      0x0            0x0  0x0 0x0
+			  >;
+			    /* rdc config when MCU stops
+			     * memory:
+			     *   TCM    --> domain 0/1 can access (0x7E0000~0x81FFFF)
+			     *   DDR    --> domain 0/1 can access (0x80000000~0x81000000)
+			     * end.
+			     */
+		stop-config = <
+			    RDC_MEM_REGION 22 TCM_START TCM_END MEM_D0D1_ACCESS
+			    RDC_MEM_REGION 39 M4_DDR_START M4_DDR_END MEM_D0D1_ACCESS
+			    0x0      0x0            0x0  0x0 0x0
+			  >;
+	};
 };
 
-&reg_usdhc2_vmmc {
-	u-boot,off-on-delay-us = <20000>;
+&pinctrl_reg_usdhc2_vmmc {
+	u-boot,dm-spl;
 };
 
 &reg_usdhc2_vmmc {
 	u-boot,dm-spl;
+	u-boot,off-on-delay-us = <20000>;
 };
 
 &pinctrl_uart2 {
@@ -67,50 +116,83 @@
 	u-boot,dm-spl;
 };
 
-&i2c1 {
+&crypto {
 	u-boot,dm-spl;
 };
 
-&i2c2 {
+&sec_jr0 {
 	u-boot,dm-spl;
 };
 
-&i2c3 {
+&sec_jr1 {
+	u-boot,dm-spl;
+};
+
+&sec_jr2 {
 	u-boot,dm-spl;
 };
 
-&i2c4 {
+&i2c1 {
+	u-boot,dm-spl;
+};
+
+&i2c2 {
+	u-boot,dm-spl;
+};
+
+&i2c3 {
 	u-boot,dm-spl;
 };
 
-&i2c5 {
+&pinctrl_i2c1 {
 	u-boot,dm-spl;
 };
 
-&i2c6 {
+&pinctrl_i2c1_gpio {
 	u-boot,dm-spl;
 };
 
 &usdhc1 {
 	u-boot,dm-spl;
+	assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
+	assigned-clock-rates = <400000000>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
 };
 
 &usdhc2 {
 	u-boot,dm-spl;
 	sd-uhs-sdr104;
 	sd-uhs-ddr50;
+	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
+	assigned-clock-rates = <400000000>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
 };
 
 &usdhc3 {
 	u-boot,dm-spl;
 	mmc-hs400-1_8v;
 	mmc-hs400-enhanced-strobe;
+	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+	assigned-clock-rates = <400000000>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
 };
 
 &wdog1 {
 	u-boot,dm-spl;
 };
 
+&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
+	u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
+	u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+	u-boot,dm-spl;
+};
+
 &eqos {
 	compatible = "fsl,imx-eqos";
 	/delete-property/ assigned-clocks;
@@ -120,8 +202,8 @@
 
 &ethphy0 {
 	reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
-	reset-delay-us = <15000>;
-	reset-post-delay-us = <100000>;
+	reset-assert-us = <15000>;
+	reset-deassert-us = <100000>;
 };
 
 &fec {
@@ -130,4 +212,40 @@
 	phy-reset-post-delay = <100>;
 };
 
+&flexspi {
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
+};
+
+&lcdif1 {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
+};
+
+&mipi_dsi {
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-parents;
+	/delete-property/ assigned-clock-rates;
+};
+
+&usb3_0 {
+	/delete-property/ power-domains;
+};
+
+&usb3_1 {
+	/delete-property/ power-domains;
+};
 
+&usb_dwc3_0 {
+	compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
+	assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
+	assigned-clock-rates = <400000000>;
+};
+
+&usb_dwc3_1 {
+	compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
+	assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
+	assigned-clock-rates = <400000000>;
+};
diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts
index f846d69dac9..0df546dfd06 100644
--- a/arch/arm/dts/imx8mp-evk.dts
+++ b/arch/arm/dts/imx8mp-evk.dts
@@ -5,13 +5,15 @@
 
 /dts-v1/;
 
+#include <dt-bindings/usb/pd.h>
 #include "imx8mp.dtsi"
 
 / {
-	model = "NXP i.MX8MPlus EVK board";
+	model = "NXP i.MX8MPlus LPDDR4 EVK board";
 	compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
 
 	chosen {
+		bootargs = "console=ttymxc1,115200";
 		stdout-path = &uart2;
 	};
 
@@ -64,6 +66,48 @@
 		regulator-max-microvolt = <3300000>;
 		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
+		startup-delay-us = <100>;
+		off-on-delay-us = <12000>;
+	};
+
+	dsi_host: dsi-host {
+		compatible = "samsung,sec-mipi-dsi";
+		status = "okay";
+	};
+
+	rm67199_panel {
+		compatible = "raydium,rm67199";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_mipi_dsi_en>;
+		reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
+		dsi-lanes = <4>;
+		video-mode = <2>;	/* 0: burst mode
+					 * 1: non-burst mode with sync event
+					 * 2: non-burst mode with sync pulse
+					 */
+		panel-width-mm = <68>;
+		panel-height-mm = <121>;
+		status = "okay";
+
+		port {
+			rm67191_from_dsim: endpoint {
+				remote-endpoint = <&dsim_to_rm67191>;
+			};
+		};
+	};
+
+	cbtl04gp {
+		compatible = "nxp,cbtl04gp";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_typec_mux>;
+		switch-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
+		orientation-switch;
+
+		port {
+			usb3_data_ss: endpoint {
+				remote-endpoint = <&typec_con_ss>;
+			};
+		};
 	};
 };
 
@@ -117,15 +161,214 @@
 			compatible = "ethernet-phy-ieee802.3-c22";
 			reg = <1>;
 			eee-broken-1000t;
-			reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
 		};
 	};
 };
 
-&i2c3 {
-	clock-frequency = <400000>;
+&flexspi {
 	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi0>;
+	status = "okay";
+
+	flash0: mt25qu256aba@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <80000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pca9450@25 {
+		reg = <0x25>;
+		compatible = "nxp,pca9450c";
+		/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
+		pinctrl-0 = <&pinctrl_pmic>;
+		gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
+
+		regulators {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pca9450,pmic-buck2-uses-i2c-dvs;
+			/* Run/Standby voltage */
+			pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
+
+			buck1_reg: regulator@0 {
+				reg = <0>;
+				regulator-compatible = "buck1";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck2_reg: regulator@1 {
+				reg = <1>;
+				regulator-compatible = "buck2";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck4_reg: regulator@3 {
+				reg = <3>;
+				regulator-compatible = "buck4";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5_reg: regulator@4 {
+				reg = <4>;
+				regulator-compatible = "buck5";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6_reg: regulator@5 {
+				reg = <5>;
+				regulator-compatible = "buck6";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1_reg: regulator@6 {
+				reg = <6>;
+				regulator-compatible = "ldo1";
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2_reg: regulator@7 {
+				reg = <7>;
+				regulator-compatible = "ldo2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3_reg: regulator@8 {
+				reg = <8>;
+				regulator-compatible = "ldo3";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4_reg: regulator@9 {
+				reg = <9>;
+				regulator-compatible = "ldo4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5_reg: regulator@10 {
+				reg = <10>;
+				regulator-compatible = "ldo5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	adv_bridge: adv7535@3d {
+		compatible = "adi,adv7535";
+		reg = <0x3d>;
+		adi,addr-cec = <0x3c>;
+		adi,dsi-lanes = <4>;
+		status = "okay";
+
+		port {
+			adv7535_from_dsim: endpoint {
+				remote-endpoint = <&dsim_to_adv7535>;
+			};
+		};
+	};
+
+	ptn5110: tcpc@50 {
+		compatible = "nxp,ptn5110";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_typec>;
+		reg = <0x50>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <19 8>;
+
+		port {
+			typec_dr_sw: endpoint {
+				remote-endpoint = <&usb3_drd_sw>;
+			};
+		};
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			power-role = "dual";
+			data-role = "dual";
+			try-power-role = "sink";
+			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+				     PDO_VAR(5000, 20000, 3000)>;
+			op-sink-microwatt = <15000000>;
+			self-powered;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@1 {
+					reg = <1>;
+					typec_con_ss: endpoint {
+						remote-endpoint = <&usb3_data_ss>;
+					};
+				};
+			};
+		};
+	};
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
 	pca6416: gpio@20 {
@@ -136,6 +379,26 @@
 	};
 };
 
+&lcdif1 {
+	status = "okay";
+};
+
+&mipi_dsi {
+	status = "okay";
+
+	port@1 {
+		dsim_to_adv7535: endpoint {
+			remote-endpoint = <&adv7535_from_dsim>;
+		};
+	};
+
+	port@2 {
+		dsim_to_rm67191: endpoint {
+			remote-endpoint = <&rm67191_from_dsim>;
+		};
+	};
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };
@@ -147,9 +410,55 @@
 	status = "okay";
 };
 
+&usb3_phy0 {
+	vbus-power-supply = <&ptn5110>;
+	fsl,phy-tx-vref-tune = <0xe>;
+	fsl,phy-tx-preemp-amp-tune = <3>;
+	fsl,phy-tx-vboost-level = <5>;
+	fsl,phy-comp-dis-tune = <7>;
+	fsl,pcs-tx-deemph-3p5db = <0x21>;
+	fsl,phy-pcs-tx-swing-full = <0x7f>;
+	status = "okay";
+};
+
+&usb3_0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	usb-role-switch;
+	role-switch-default-mode = "none";
+	status = "okay";
+
+	port {
+		usb3_drd_sw: endpoint {
+			remote-endpoint = <&typec_dr_sw>;
+		};
+	};
+};
+
+&usb3_phy1 {
+	fsl,phy-tx-preemp-amp-tune = <3>;
+	fsl,phy-tx-vref-tune = <0xb>;
+	status = "okay";
+};
+
+&usb3_1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb1_vbus>;
+	dr_mode = "host";
+	status = "okay";
+};
+
 &usdhc2 {
-	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
-	assigned-clock-rates = <400000000>;
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
@@ -161,8 +470,6 @@
 };
 
 &usdhc3 {
-	assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
-	assigned-clock-rates = <400000000>;
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc3>;
 	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
@@ -180,6 +487,8 @@
 };
 
 &iomuxc {
+	pinctrl-names = "default";
+
 	pinctrl_eqos: eqosgrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC	0x3
@@ -246,20 +555,90 @@
 		>;
 	};
 
+	pinctrl_flexspi0: flexspi0grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK		0x1c2
+			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B	0x82
+			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00	0x82
+			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01	0x82
+			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02	0x82
+			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03	0x82
+		>;
+	};
+
 	pinctrl_gpio_led: gpioledgrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x19
 		>;
 	};
 
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3
+			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c3
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL			0x400001c3
+			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA			0x400001c3
+		>;
+	};
+
 	pinctrl_i2c3: i2c3grp {
 		fsl,pins = <
-			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c3
-			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c3
+			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x400001c3
+			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x400001c3
 		>;
 	};
 
-	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+	pinctrl_i2c1_gpio: i2c1grp-gpio {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14        	0x1c3
+			MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15        	0x1c3
+		>;
+	};
+
+	pinctrl_i2c2_gpio: i2c2grp-gpio {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16        	0x1c3
+			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17        	0x1c3
+		>;
+	};
+
+	pinctrl_i2c3_gpio: i2c3grp-gpio {
+		fsl,pins = <
+			MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18        	0x1c3
+			MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19        	0x1c3
+		>;
+	};
+
+	pinctrl_mipi_dsi_en: mipi_dsi_en {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08	0x16
+		>;
+	};
+
+	pinctrl_pmic: pmicirq {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03	0x41
+		>;
+	};
+
+	pinctrl_typec: typec1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19	0x1c4
+		>;
+	};
+
+	pinctrl_typec_mux: typec1muxgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x16
+		>;
+	};
+
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
 		fsl,pins = <
 			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x41
 		>;
@@ -267,8 +646,14 @@
 
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
-			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x49
-			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x49
+			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
+			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_usb1_vbus: usb1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR	0x19
 		>;
 	};
 
@@ -364,7 +749,7 @@
 
 	pinctrl_wdog: wdoggrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0x166
+			MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B	0xc6
 		>;
 	};
 };
diff --git a/arch/arm/dts/imx8mp-sec-def.h b/arch/arm/dts/imx8mp-sec-def.h
new file mode 100644
index 00000000000..155aab14284
--- /dev/null
+++ b/arch/arm/dts/imx8mp-sec-def.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef IMX8MP_SEC_DEF_H
+#define IMX8MP_SEC_DEF_H
+
+/* Domain ID */
+#define DID0            0x0
+#define DID1            0x1
+#define DID2            0x2
+#define DID3            0x3
+
+/* Domain RD/WR permission */
+#define LOCK           0x80000000
+#define ENA            0x40000000
+#define D3R            0x00000080
+#define D3W            0x00000040
+#define D2R            0x00000020
+#define D2W            0x00000010
+#define D1R            0x00000008
+#define D1W            0x00000004
+#define D0R            0x00000002
+#define D0W            0x00000001
+
+#define PDAP_D1_ACCESS 0x0000000C /* D1W|D1R */
+#define PDAP_D0D1_ACCESS 0x0000000F /* D0R|D0W|D1W|D1R */
+#define MEM_D1_ACCESS  0x4000000C /* ENA|D1W|D1R */
+#define MEM_D0D1_ACCESS  0x4000000F /* ENA|D0W|D0R|D1W|D1R */
+
+/* RDC type */
+#define RDC_INVALID 0
+#define RDC_MDA 1
+#define RDC_PDAP 2
+#define RDC_MEM_REGION 3
+
+/* RDC MDA index */
+#define RDC_MDA_A53  0
+#define RDC_MDA_M7  1
+#define RDC_MDA_SDMA3p  3
+#define RDC_MDA_SDMA3b  4
+#define RDC_MDA_LCDIF1  5
+#define RDC_MDA_ISI  6
+#define RDC_MDdA_NPU = 7
+#define RDC_MDA_Coresight  8
+#define RDC_MDA_DAP  9
+#define RDC_MDA_CAAM  10
+#define RDC_MDA_SDMA1p  11
+#define RDC_MDA_SDMA1b  12
+#define RDC_MDA_APBHDMA  13
+#define RDC_MDA_RAWNAND  14
+#define RDC_MDA_uSDHC1  15
+#define RDC_MDA_uSDHC2  16
+#define RDC_MDA_uSDHC3  17
+#define RDC_MDA_ENET1_TX 22
+#define RDC_MDA_ENET1_RX 23
+#define RDC_MDA_SDMA3_SPBA2 25
+#define RDC_MDA_LCDIF2  27
+#define RDC_MDA_HDMI_TX  28
+#define RDC_MDA_GPU3D  30
+#define RDC_MDA_GPU2D  31
+#define RDC_MDA_VPUG1  32
+#define RDC_MDA_VPUG2  33
+#define RDC_MDA_VC8000E  34
+
+/* RDC Peripherals index */
+#define RDC_PDAP_GPIO1  0
+#define RDC_PDAP_GPIO2  1
+#define RDC_PDAP_GPIO3  2
+#define RDC_PDAP_GPIO4  3
+#define RDC_PDAP_GPIO5  4
+#define RDC_PDAP_ANA_TSENSOR  6
+#define RDC_PDAP_ANA_OSC  7
+#define RDC_PDAP_WDOG1  8
+#define RDC_PDAP_WDOG2  9
+#define RDC_PDAP_WDOG3  10
+#define RDC_PDAP_SDMA2  12
+#define RDC_PDAP_GPT1  13
+#define RDC_PDAP_GPT2  14
+#define RDC_PDAP_GPT3  15
+#define RDC_PDAP_ROMCP  17
+#define RDC_PDAP_IOMUXC  19
+#define RDC_PDAP_IOMUXC_GPR  20
+#define RDC_PDAP_OCOTP_CTRL  21
+#define RDC_PDAP_ANA_PLL  22
+#define RDC_PDAP_SNVS_HP  23
+#define RDC_PDAP_CCM  24
+#define RDC_PDAP_SRC  25
+#define RDC_PDAP_GPC  26
+#define RDC_PDAP_SEMAPHORE1  27
+#define RDC_PDAP_SEMAPHORE2  28
+#define RDC_PDAP_RDC  29
+#define RDC_PDAP_CSU  30
+#define RDC_PDAP_LCDIF  32
+#define RDC_PDAP_MIPI_DSI  33
+#define RDC_PDAP_ISI  34
+#define RDC_PDAP_MIPI_CSI  35
+#define RDC_PDAP_USB1  36
+#define RDC_PDAP_PWM1  38
+#define RDC_PDAP_PWM2  39
+#define RDC_PDAP_PWM3  40
+#define RDC_PDAP_PWM4  41
+#define RDC_PDAP_System_Counter_RD  42
+#define RDC_PDAP_System_Counter_CMP  43
+#define RDC_PDAP_System_Counter_CTRL  44
+#define RDC_PDAP_GPT6  46
+#define RDC_PDAP_GPT5  47
+#define RDC_PDAP_GPT4  48
+#define RDC_PDAP_TZASC  56
+#define RDC_PDAP_PERFMON1  60
+#define RDC_PDAP_PERFMON2  61
+#define RDC_PDAP_PLATFORM_CTRL  62
+#define RDC_PDAP_QoSC  63
+#define RDC_PDAP_I2C1  66
+#define RDC_PDAP_I2C2  67
+#define RDC_PDAP_I2C3  68
+#define RDC_PDAP_I2C4  69
+#define RDC_PDAP_UART4  70
+#define RDC_PDAP_MU_A  74
+#define RDC_PDAP_MU_B  75
+#define RDC_PDAP_SEMAPHORE_HS  76
+#define RDC_PDAP_SAI2  79
+#define RDC_PDAP_SAI3  80
+#define RDC_PDAP_SAI5  82
+#define RDC_PDAP_SAI6  83
+#define RDC_PDAP_uSDHC1  84
+#define RDC_PDAP_uSDHC2  85
+#define RDC_PDAP_uSDHC3  86
+#define RDC_PDAP_SAI7  87
+#define RDC_PDAP_SPBA2  90
+#define RDC_PDAP_QSPI  91
+#define RDC_PDAP_SDMA1  93
+#define RDC_PDAP_ENET1  94
+#define RDC_PDAP_SPDIF1  97
+#define RDC_PDAP_eCSPI1  98
+#define RDC_PDAP_eCSPI2  99
+#define RDC_PDAP_eCSPI3  100
+#define RDC_PDAP_MICFIL  101
+#define RDC_PDAP_UART1  102
+#define RDC_PDAP_UART3  104
+#define RDC_PDAP_UART2  105
+#define RDC_PDAP_ASRC  107
+#define RDC_PDAP_SDMA3  109
+#define RDC_PDAP_SPBA1  111
+#define RDC_PDAP_CAAM  114
+
+/* RDC MEMORY REGION */
+#define TCM_START 0x7E0000
+#define TCM_END   0x820000
+#define M4_DDR_START 0x20000000
+#define M4_DDR_END 0x20800000
+
+#endif /* IMX8MP_SEC_DEF_H */
diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index c2d51a46cb3..2876b94b2ac 100644
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/clock/imx8mp-clock.h>
+#include <dt-bindings/reset/imx8mp-reset.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -37,6 +38,10 @@
 		serial1 = &uart2;
 		serial2 = &uart3;
 		serial3 = &uart4;
+		usb0 = &usb_dwc3_0;
+		usb1 = &usb_dwc3_1;
+		spi0 = &flexspi;
+		video0 = &lcdif1;
 	};
 
 	cpus {
@@ -92,6 +97,31 @@
 		};
 	};
 
+	gic: interrupt-controller@38800000 {
+		compatible = "arm,gic-v3";
+		reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
+		      <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+	};
+
+	resmem: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0 0x3c000000>;
+			alloc-ranges = <0 0x40000000 0 0xC0000000>;
+			linux,cma-default;
+		};
+	};
+
 	osc_32k: clock-osc-32k {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -134,10 +164,200 @@
 		clock-output-names = "clk_ext4";
 	};
 
+	busfreq { /* BUSFREQ */
+		compatible = "fsl,imx_busfreq";
+		clocks = <&clk IMX8MP_DRAM_PLL_OUT>, <&clk IMX8MP_CLK_DRAM_ALT>,
+			 <&clk IMX8MP_CLK_DRAM_APB>, <&clk IMX8MP_CLK_DRAM_APB>,
+			 <&clk IMX8MP_CLK_DRAM_CORE>, <&clk IMX8MP_CLK_DRAM_ALT_ROOT>,
+			 <&clk IMX8MP_SYS_PLL1_40M>, <&clk IMX8MP_SYS_PLL1_100M>,
+			 <&clk IMX8MP_SYS_PLL2_333M>, <&clk IMX8MP_CLK_NOC>,
+			 <&clk IMX8MP_CLK_AHB>, <&clk IMX8MP_CLK_MAIN_AXI>,
+			 <&clk IMX8MP_CLK_24M>, <&clk IMX8MP_SYS_PLL1_800M>,
+			 <&clk IMX8MP_DRAM_PLL>;
+		clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div",
+			      "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m",
+			      "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m",
+			      "sys_pll1_800m", "dram_pll_div";
+	};
+
+	power-domains {
+		compatible = "simple-bus";
+
+		/* HSIO SS */
+		hsiomix_pd: hsiomix-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			active-wakeup;
+			rpm-always-on;
+			#power-domain-cells = <0>;
+			domain-index = <0>;
+			domain-name = "hsiomix";
+		};
+
+		pcie_pd: pcie-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <1>;
+			domain-name = "pcie";
+			parent-domains = <&hsiomix_pd>;
+		};
+
+		usb_otg1_pd: usbotg1-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <2>;
+			domain-name = "usb_otg1";
+			parent-domains = <&hsiomix_pd>;
+		};
+
+		usb_otg2_pd: usbotg2-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <3>;
+			domain-name = "usb_otg2";
+			parent-domains = <&hsiomix_pd>;
+		};
+
+		/* MLMIX */
+		mlmix_pd: mlmix-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <4>;
+			domain-name = "mlmix";
+			clocks = <&clk IMX8MP_CLK_ML_AXI>,
+				 <&clk IMX8MP_CLK_ML_AHB>,
+				 <&clk IMX8MP_CLK_NPU_ROOT>;
+		};
+
+		audiomix_pd: audiomix-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <5>;
+			domain-name = "audiomix";
+			clocks = <&clk IMX8MP_CLK_AUDIO_AHB_ROOT>,
+				 <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>;
+		};
+
+		gpumix_pd: gpumix-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <6>;
+			domain-name = "gpumix";
+			clocks = <&clk IMX8MP_CLK_GPU_ROOT>, <&clk IMX8MP_CLK_GPU_AHB>,
+				 <&clk IMX8MP_CLK_GPU_AXI>;
+		};
+
+		gpu2d_pd: gpu2d-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <7>;
+			domain-name = "gpu2d";
+			parent-domains = <&gpumix_pd>;
+			clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
+		};
+
+		gpu3d_pd: gpu3d-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <8>;
+			domain-name = "gpu3d";
+			parent-domains = <&gpumix_pd>;
+			clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
+				 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
+		};
+
+		vpumix_pd: vpumix-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <9>;
+			domain-name = "vpumix";
+			clocks =<&clk IMX8MP_CLK_VPU_ROOT>;
+		};
+
+		vpu_g1_pd: vpug1-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <10>;
+			domain-name = "vpu_g1";
+			parent-domains = <&vpumix_pd>;
+			clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
+		};
+
+		vpu_g2_pd: vpug2-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <11>;
+			domain-name = "vpu_g2";
+			parent-domains = <&vpumix_pd>;
+			clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
+		};
+
+		vpu_h1_pd: vpuh1-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <12>;
+			domain-name = "vpu_h1";
+			parent-domains = <&vpumix_pd>;
+			clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
+		};
+
+		mediamix_pd: mediamix-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <13>;
+			domain-name = "mediamix";
+			clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+				 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+		};
+
+		ispdwp_pd: power-domain@14 {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <14>;
+			domain-name = "ispdwp";
+			parent-domains = <&mediamix_pd>;
+			clocks = <&clk IMX8MP_CLK_MEDIA_ISP>;
+		};
+
+		mipi_phy1_pd: mipiphy1-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <15>;
+			domain-name = "mipi_phy1";
+			parent-domains = <&mediamix_pd>;
+		};
+
+		mipi_phy2_pd: mipiphy2-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <16>;
+			domain-name = "mipi_phy2";
+			parent-domains = <&mediamix_pd>;
+		};
+
+		hdmimix_pd: hdmimix-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <17>;
+			domain-name = "hdmimix";
+			clocks = <&clk IMX8MP_CLK_HDMI_ROOT>,
+				 <&clk IMX8MP_CLK_HDMI_APB>,
+				 <&clk IMX8MP_CLK_HDMI_REF_266M>;
+		};
+
+		hdmi_phy_pd: hdmiphy-pd {
+			compatible = "fsl,imx8m-pm-domain";
+			#power-domain-cells = <0>;
+			domain-index = <18>;
+			domain-name = "hdmi_phy";
+			parent-domains = <&hdmimix_pd>;
+		};
+	};
+
 	pmu {
-		compatible = "arm,cortex-a53-pmu";
+		compatible = "arm,armv8-pmuv3";
+		interrupt-parent = <&gic>;
 		interrupts = <GIC_PPI 7
-			     (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			     (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
 		interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
 	};
 
@@ -210,12 +430,13 @@
 
 	timer {
 		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
 		clock-frequency = <8000000>;
 		arm,no-tick-in-suspend;
+		interrupt-parent = <&gic>;
 	};
 
 	soc@0 {
@@ -226,6 +447,11 @@
 		nvmem-cells = <&imx8mp_uid>;
 		nvmem-cell-names = "soc_unique_id";
 
+		caam_sm: caam-sm@100000 {
+			compatible = "fsl,imx6q-caam-sm";
+			reg = <0x100000 0x8000>;
+		};
+
 		aips1: bus@30000000 {
 			compatible = "fsl,aips-bus", "simple-bus";
 			reg = <0x30000000 0x400000>;
@@ -295,7 +521,6 @@
 				#gpio-cells = <2>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
-				gpio-ranges = <&iomuxc 0 114 30>;
 			};
 
 			tmu: tmu@30260000 {
@@ -335,7 +560,8 @@
 			};
 
 			gpr: iomuxc-gpr@30340000 {
-				compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
+				compatible = "fsl,imx8mp-iomuxc-gpr",
+					     "fsl,imx6q-iomuxc-gpr", "syscon";
 				reg = <0x30340000 0x10000>;
 			};
 
@@ -366,9 +592,26 @@
 				reg = <0x30360000 0x10000>;
 			};
 
+			irq_sec_vio: caam_secvio {
+				compatible = "fsl,imx6q-caam-secvio";
+				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+				jtag-tamper = "disabled";
+				watchdog-tamper = "enabled";
+				internal-boot-tamper = "enabled";
+				external-pin-tamper = "disabled";
+			};
+
+			caam_snvs: caam-snvs@30370000 {
+				compatible = "fsl,imx6q-caam-snvs";
+				reg = <0x30370000 0x10000>;
+				clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
+				clock-names = "ipg";
+			};
+
 			snvs: snvs@30370000 {
 				compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
 				reg = <0x30370000 0x10000>;
+				status = "disabled";
 
 				snvs_rtc: snvs-rtc-lp {
 					compatible = "fsl,sec-v4.0-mon-rtc-lp";
@@ -378,6 +621,7 @@
 						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 					clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
 					clock-names = "snvs-rtc";
+					status = "disabled";
 				};
 
 				snvs_pwrkey: snvs-powerkey {
@@ -409,7 +653,8 @@
 						  <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
 						  <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
 						  <&clk IMX8MP_AUDIO_PLL1>,
-						  <&clk IMX8MP_AUDIO_PLL2>;
+						  <&clk IMX8MP_AUDIO_PLL2>,
+						  <&clk IMX8MP_VIDEO_PLL1>;
 				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
 							 <&clk IMX8MP_ARM_PLL_OUT>,
 							 <&clk IMX8MP_SYS_PLL2_1000M>,
@@ -425,7 +670,8 @@
 						       <800000000>,
 						       <400000000>,
 						       <393216000>,
-						       <361267200>;
+						       <361267200>,
+						       <1039500000>;
 			};
 
 			src: reset-controller@30390000 {
@@ -512,6 +758,9 @@
 				clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
 					 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
 				clock-names = "ipg", "per";
+				assigned-clock-rates = <80000000>;
+				assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
+				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
 				dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
 				dma-names = "rx", "tx";
 				status = "disabled";
@@ -526,6 +775,9 @@
 				clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
 					 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
 				clock-names = "ipg", "per";
+				assigned-clock-rates = <80000000>;
+				assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
+				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
 				dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
 				dma-names = "rx", "tx";
 				status = "disabled";
@@ -540,6 +792,9 @@
 				clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
 					 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
 				clock-names = "ipg", "per";
+				assigned-clock-rates = <80000000>;
+				assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
+				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
 				dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
 				dma-names = "rx", "tx";
 				status = "disabled";
@@ -589,8 +844,8 @@
 				assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
 				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
 				assigned-clock-rates = <40000000>;
-				fsl,clk-source = /bits/ 8 <0>;
-				fsl,stop-mode = <&gpr 0x10 4>;
+				fsl,clk-source= <0>;
+				fsl,stop-mode = <&gpr 0x10 4 0x10 20>;
 				status = "disabled";
 			};
 
@@ -604,8 +859,8 @@
 				assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
 				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
 				assigned-clock-rates = <40000000>;
-				fsl,clk-source = /bits/ 8 <0>;
-				fsl,stop-mode = <&gpr 0x10 5>;
+				fsl,clk-source= <0>;
+				fsl,stop-mode = <&gpr 0x10 5 0x10 21>;
 				status = "disabled";
 			};
 
@@ -624,6 +879,7 @@
 					compatible = "fsl,sec-v4.0-job-ring";
 					reg = <0x1000 0x1000>;
 					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+					status = "disabled";
 				};
 
 				sec_jr1: jr@2000 {
@@ -719,6 +975,15 @@
 				status = "disabled";
 			};
 
+			flexspi_nand: flexspi_nand@30bb0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8mp-fspi-nand";
+				reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>;
+				reg-names = "FlexSPI", "FlexSPI-memory";
+				status = "disabled";
+			};
+
 			usdhc1: mmc@30b40000 {
 				compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
 				reg = <0x30b40000 0x10000>;
@@ -727,6 +992,8 @@
 					 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
 					 <&clk IMX8MP_CLK_USDHC1_ROOT>;
 				clock-names = "ipg", "ahb", "per";
+				assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
+				assigned-clock-rates = <400000000>;
 				fsl,tuning-start-tap = <20>;
 				fsl,tuning-step= <2>;
 				bus-width = <4>;
@@ -741,6 +1008,8 @@
 					 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
 					 <&clk IMX8MP_CLK_USDHC2_ROOT>;
 				clock-names = "ipg", "ahb", "per";
+				assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
+				assigned-clock-rates = <400000000>;
 				fsl,tuning-start-tap = <20>;
 				fsl,tuning-step= <2>;
 				bus-width = <4>;
@@ -755,12 +1024,29 @@
 					 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
 					 <&clk IMX8MP_CLK_USDHC3_ROOT>;
 				clock-names = "ipg", "ahb", "per";
+				assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+				assigned-clock-rates = <400000000>;
 				fsl,tuning-start-tap = <20>;
 				fsl,tuning-step= <2>;
 				bus-width = <4>;
 				status = "disabled";
 			};
 
+			flexspi: spi@30bb0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "nxp,imx8mm-fspi";
+				reg = <0x30bb0000 0x10000>, <0x08000000 0x10000000>;
+				reg-names = "fspi_base", "fspi_mmap";
+				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
+					 <&clk IMX8MP_CLK_QSPI_ROOT>;
+				clock-names = "fspi", "fspi_en";
+				assigned-clock-rates = <80000000>;
+				assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
+				status = "disabled";
+			};
+
 			sdma1: dma-controller@30bd0000 {
 				compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
 				reg = <0x30bd0000 0x10000>;
@@ -770,6 +1056,7 @@
 				clock-names = "ipg", "ahb";
 				#dma-cells = <3>;
 				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+				status = "disabled";
 			};
 
 			fec: ethernet@30be0000 {
@@ -827,14 +1114,71 @@
 			};
 		};
 
-		gic: interrupt-controller@38800000 {
-			compatible = "arm,gic-v3";
-			reg = <0x38800000 0x10000>,
-			      <0x38880000 0xc0000>;
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-parent = <&gic>;
+		aips4: bus@32c00000 {
+			compatible = "simple-bus";
+			reg = <0x32c00000 0x400000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			mipi_dsi: mipi_dsi@32e60000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8mp-mipi-dsim";
+				reg = <0x32e60000 0x10000>;
+				clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
+				clock-names = "cfg", "pll-ref";
+				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
+				assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
+				assigned-clock-rates = <594000000>;
+				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&mipi_phy1_pd>;
+				status = "disabled";
+
+				port@0 {
+					dsim_from_lcdif: endpoint {
+						remote-endpoint = <&lcdif_to_dsim>;
+					};
+				};
+			};
+
+			lcdif1: lcd-controller@32e80000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8mp-lcdif1";
+				reg = <0x32e80000 0x10000>;
+				clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+				clock-names = "pix", "disp-axi", "disp-apb";
+				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
+						  <&clk IMX8MP_CLK_MEDIA_AXI>,
+						  <&clk IMX8MP_CLK_MEDIA_APB>;
+				assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>,
+							 <&clk IMX8MP_SYS_PLL2_1000M>,
+							 <&clk IMX8MP_SYS_PLL1_800M>;
+				assigned-clock-rates = <594000000>, <500000000>, <200000000>;
+				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+				blk-ctl = <&mediamix_blk_ctl>;
+				power-domains = <&mediamix_pd>;
+				status = "disabled";
+
+				lcdif_disp0: port@0 {
+					reg = <0>;
+
+					lcdif_to_dsim: endpoint {
+						remote-endpoint = <&dsim_from_lcdif>;
+					};
+				};
+			};
+
+			mediamix_blk_ctl: blk-ctl@32ec0000 {
+				compatible = "fsl,imx8mp-mediamix-blk-ctl",
+					     "syscon";
+				reg = <0x32ec0000 0x10000>;
+			};
+
 		};
 
 		ddr-pmu@3d800000 {
@@ -861,6 +1205,7 @@
 				 <&clk IMX8MP_CLK_USB_ROOT>;
 			clock-names = "hsio", "suspend";
 			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&hsiomix_pd>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			dma-ranges = <0x40000000 0x40000000 0xc0000000>;
@@ -902,6 +1247,7 @@
 				 <&clk IMX8MP_CLK_USB_ROOT>;
 			clock-names = "hsio", "suspend";
 			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&hsiomix_pd>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			dma-ranges = <0x40000000 0x40000000 0xc0000000>;
@@ -925,4 +1271,83 @@
 			};
 		};
 	};
+
+	pcie_phy: pcie-phy@32f00000 {
+		compatible = "fsl,imx8mp-pcie-phy";
+		reg = <0x0 0x32f00000 0x0 0x10000>;
+		clocks = <&clk IMX8MP_CLK_PCIE_PHY>;
+		clock-names = "phy";
+		assigned-clocks = <&clk IMX8MP_CLK_PCIE_PHY>;
+		assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+		#phy-cells = <0>;
+		status = "disabled";
+	};
+
+	hsio_mix: hsio-mix@32f10000 {
+		  compatible = "fsl,imx8mp-hsio-mix";
+		  reg = <0x0 0x32f10000 0x0 0x8>;
+	};
+
+	dma_apbh: dma-apbh@33000000 {
+		compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
+		reg = <0 0x33000000 0 0x2000>;
+		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+		#dma-cells = <1>;
+		dma-channels = <4>;
+		clocks = <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
+	};
+
+	gpmi: gpmi-nand@33002000{
+		compatible = "fsl,imx7d-gpmi-nand";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0 0x33002000 0 0x2000>, <0 0x33004000 0 0x4000>;
+		reg-names = "gpmi-nand", "bch";
+		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "bch";
+		clocks = <&clk IMX8MP_CLK_NAND_ROOT>,
+			<&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
+		clock-names = "gpmi_io", "gpmi_bch_apb";
+		dmas = <&dma_apbh 0>;
+		dma-names = "rx-tx";
+		status = "disabled";
+	};
+
+	pcie: pcie@33800000 {
+		compatible = "fsl,imx8mp-pcie", "snps,dw-pcie";
+		reg = <0x0 0x33800000 0x0 0x400000>,
+			<0x0 0x1ff00000 0x0 0x80000>;
+		reg-names = "dbi", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		ranges =  <0x81000000 0 0x00000000 0x0 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
+			   0x82000000 0 0x18000000 0x0 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+		num-lanes = <1>;
+		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+		interrupt-names = "msi", "dma";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 0x7>;
+		interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+				<0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,max-link-speed = <3>;
+		power-domains = <&pcie_pd>;
+		resets = <&src IMX8MP_RESET_PCIEPHY>,
+			 <&src IMX8MP_RESET_PCIEPHY_PERST>,
+			 <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
+			 <&src IMX8MP_RESET_PCIE_CTRL_APPS_CLK_REQ>,
+			 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
+		reset-names = "pciephy", "pciephy_perst", "apps", "clkreq", "turnoff";
+		phys = <&pcie_phy>;
+		phy-names = "pcie-phy";
+		fsl,imx8mp-hsio-mix = <&hsio_mix>;
+		status = "disabled";
+	};
 };
diff --git a/arch/arm/dts/imx8mq-ddr3l-val.dts b/arch/arm/dts/imx8mq-ddr3l-val.dts
new file mode 100644
index 00000000000..38c948b678d
--- /dev/null
+++ b/arch/arm/dts/imx8mq-ddr3l-val.dts
@@ -0,0 +1,484 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+
+/ {
+	model = "NXP i.MX8MQ DDR3L VAL";
+	compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
+
+	chosen {
+		bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
+		stdout-path = &uart1;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usdhc2_vmmc: usdhc2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "VSD_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+			off-on-delay-us = <20000>;
+			enable-active-high;
+		};
+	};
+
+	modem_reset: modem-reset {
+		compatible = "gpio-reset";
+		reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <2000>;
+		reset-post-delay-ms = <40>;
+		#reset-cells = <0>;
+	};
+
+	wm8524: audio-codec {
+		#sound-dai-cells = <0>;
+		compatible = "wlf,wm8524";
+		wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		ledpwm2 {
+			label = "PWM2";
+			pwms = <&pwm2 0 50000>;
+			max-brightness = <255>;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	imx8mq-val {
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3
+				MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO	0x23
+				MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK	0x4000001f
+				MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x56
+				MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x56
+				MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x56
+				MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x56
+				MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER	0x56
+				MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x56
+				MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x56
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
+				MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f
+				MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f
+			>;
+		};
+
+		pinctrl_i2c1_gpio: i2c1grp-gpio {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14        		0x7f
+				MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15        		0x7f
+			>;
+		};
+
+		pinctrl_i2c2_gpio: i2c2grp-gpio {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16        		0x7f
+				MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17        		0x7f
+			>;
+		};
+
+		pinctrl_pwm2: pwm2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT	0x16
+			>;
+		};
+
+		pinctrl_qspi: qspigrp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK	0x82
+				MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK	0x82
+				MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B	0x82
+				MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B	0x82
+				MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0	0x82
+				MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1	0x82
+				MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2	0x82
+				MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3	0x82
+				MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0	0x82
+				MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1	0x82
+				MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2	0x82
+				MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3	0x82
+
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x79
+				MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x79
+			>;
+		};
+
+		pinctrl_uart3: uart3grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x79
+				MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x79
+				MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x79
+				MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B		0x79
+				MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5			0x19
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x83
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x85
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x87
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grpgpio {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
+				MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
+				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
+				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
+				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+			>;
+		};
+
+		pinctrl_sai2: sai2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6
+				MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6
+				MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6
+				MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
+				MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8	0xd6
+			>;
+		};
+
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+			>;
+		};
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pfuze100@8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x8>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3ab {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-always-on;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+	status = "disabled";
+};
+
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>;
+	status = "okay";
+};
+
+&uart1 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
+	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+	status = "okay";
+};
+
+&qspi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi>;
+	num-cs =<2>;
+	status = "okay";
+
+	flash0: gd25q16@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+	};
+
+	flash1: gd25q16@1 {
+		reg = <1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <6>;
+	};
+};
+
+&uart3 { /* BT */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
+	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
+	fsl,uart-has-rtscts;
+	resets = <&modem_reset>;
+	status = "okay";
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	usb-role-switch;
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
+	status = "okay";
+};
+
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx8mq-ddr4-val.dts b/arch/arm/dts/imx8mq-ddr4-val.dts
new file mode 100644
index 00000000000..6719df2ef1a
--- /dev/null
+++ b/arch/arm/dts/imx8mq-ddr4-val.dts
@@ -0,0 +1,448 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+
+/ {
+	model = "NXP i.MX8MQ DDR4 VAL";
+	compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
+
+	chosen {
+		bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
+		stdout-path = &uart1;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usdhc2_vmmc: usdhc2_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "VSD_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+			off-on-delay-us = <20000>;
+			enable-active-high;
+		};
+	};
+
+	modem_reset: modem-reset {
+		compatible = "gpio-reset";
+		reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <2000>;
+		reset-post-delay-ms = <40>;
+		#reset-cells = <0>;
+	};
+
+	wm8524: audio-codec {
+		#sound-dai-cells = <0>;
+		compatible = "wlf,wm8524";
+		wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		ledpwm2 {
+			label = "PWM2";
+			pwms = <&pwm2 0 50000>;
+			max-brightness = <255>;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	imx8mq-val {
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3
+				MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO	0x23
+				MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
+				MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
+				MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
+				MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
+				MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
+				MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
+				MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
+				MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
+				MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
+				MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
+				MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+				MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+				MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x19
+			>;
+		};
+
+		pinctrl_i2c1: i2c1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
+				MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
+			>;
+		};
+
+		pinctrl_i2c2: i2c2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f
+				MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f
+			>;
+		};
+
+		pinctrl_i2c1_gpio: i2c1grp-gpio {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14        		0x7f
+				MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15        		0x7f
+			>;
+		};
+
+		pinctrl_i2c2_gpio: i2c2grp-gpio {
+			fsl,pins = <
+				MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16        		0x7f
+				MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17        		0x7f
+			>;
+		};
+
+		pinctrl_pwm2: pwm2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT	0x16
+			>;
+		};
+
+		pinctrl_uart1: uart1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x79
+				MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x79
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x83
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x85
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc5
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc5
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc5
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc5
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc5
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc5
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc5
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc5
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc5
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x85
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x87
+				MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc7
+				MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc7
+				MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc7
+				MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc7
+				MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc7
+				MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc7
+				MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc7
+				MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc7
+				MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc7
+				MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 		0x87
+				MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grpgpio {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
+				MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
+				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x85
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc5
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5
+				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x87
+				MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc7
+				MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7
+				MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7
+				MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7
+				MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7
+				MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
+			>;
+		};
+
+		pinctrl_wdog: wdoggrp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+			>;
+		};
+
+		pinctrl_gpmi_nand_1: gpmi-nand-1 {
+			fsl,pins = <
+				MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE		0x00000096
+				MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B		0x00000096
+				MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE		0x00000096
+				MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00		0x00000096
+				MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01		0x00000096
+				MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02		0x00000096
+				MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03		0x00000096
+				MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04		0x00000096
+				MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05		0x00000096
+				MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06		0x00000096
+				MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07		0x00000096
+				MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B		0x00000096
+				MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B	0x00000056
+				MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B		0x00000096
+				MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B		0x00000096
+			>;
+		};
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <10>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			at803x,led-act-blind-workaround;
+			at803x,eee-disabled;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pmic: pfuze100@8 {
+		compatible = "fsl,pfuze100";
+		reg = <0x8>;
+
+		regulators {
+			sw1a_reg: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			sw1c_reg: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3ab {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			sw4_reg: sw4 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-always-on;
+			};
+
+			vgen1_reg: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen2_reg: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-always-on;
+			};
+
+			vgen3_reg: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+	status = "disabled";
+};
+
+&pwm2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm2>;
+	status = "okay";
+};
+
+&uart1 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
+	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+	status = "okay";
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	usb-role-switch;
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
+	status = "okay";
+};
+
+&usb3_phy1 {
+	status = "okay";
+};
+
+&usb_dwc3_1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	bus-width = <4>;
+	cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "okay";
+	nand-on-flash-bbt;
+	fsl,use-minimum-ecc;
+};
diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
index 6f9c81462ea..51dd3d7ec45 100644
--- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
@@ -10,3 +10,16 @@
 	sd-uhs-sdr104;
 	sd-uhs-ddr50;
 };
+
+&fec1 {
+	phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <10>;
+};
+
+&ethphy0 {
+	vddio0: vddio-regulator {
+		regulator-name = "VDDIO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+};
diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
index 85b045253a0..de709088e51 100644
--- a/arch/arm/dts/imx8mq-evk.dts
+++ b/arch/arm/dts/imx8mq-evk.dts
@@ -13,9 +13,17 @@
 	compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
 
 	chosen {
+		bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
 		stdout-path = &uart1;
 	};
 
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+
 	memory@40000000 {
 		device_type = "memory";
 		reg = <0x00000000 0x40000000 0 0xc0000000>;
@@ -35,6 +43,7 @@
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		off-on-delay-us = <20000>;
 		enable-active-high;
 	};
 
@@ -169,6 +178,7 @@
 			reg = <0>;
 			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <10000>;
+			at803x,eee-disabled;
 		};
 	};
 };
@@ -186,12 +196,16 @@
 
 &i2c1 {
 	clock-frequency = <100000>;
-	pinctrl-names = "default";
+	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 
 	pmic@8 {
 		compatible = "fsl,pfuze100";
+		fsl,pfuze-support-disable-sw;
 		reg = <0x8>;
 
 		regulators {
@@ -309,6 +323,16 @@
 	};
 };
 
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
 &pcie0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie0>;
@@ -318,6 +342,7 @@
 		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
 		 <&pcie0_refclk>;
 	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+	hard-wired = <1>;
 	status = "okay";
 };
 
@@ -330,12 +355,15 @@
 	pinctrl-0 = <&pinctrl_qspi>;
 	status = "okay";
 
-	n25q256a: flash@0 {
+	flash0: n25q256a@0 {
 		reg = <0>;
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "micron,n25q256a", "jedec,spi-nor";
+		compatible = "jedec,spi-nor";
 		spi-max-frequency = <29000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		spi-nor,ddr-quad-read-dummy = <6>;
 	};
 };
 
@@ -371,6 +399,23 @@
 &uart1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1>;
+	assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
+	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+	status = "okay";
+};
+
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	usb-role-switch;
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
 	status = "okay";
 };
 
@@ -417,7 +462,47 @@
 	status = "okay";
 };
 
+&dcss {
+	status = "okay";
+	port@0 {
+		dcss_out: endpoint {
+			remote-endpoint = <&hdmi_in>;
+		};
+	};
+};
+
+&hdmi {
+	compatible = "fsl,imx8mq-hdmi";
+	status = "okay";
+
+	display-timings {
+		native-mode = <&timing1>;
+
+		timing1: timing1 {
+			clock-frequency = <74250000>;
+			hactive = <1280>;
+			vactive = <720>;
+			hfront-porch = <110>;
+			hback-porch = <220>;
+			hsync-len = <40>;
+			vback-porch = <20>;
+			vfront-porch = <5>;
+			vsync-len = <5>;
+			hsync-active = <1>;
+			vsync-active = <1>;
+		};
+	};
+
+	port@0 {
+		hdmi_in: endpoint {
+			remote-endpoint = <&dcss_out>;
+		};
+	};
+};
+
 &iomuxc {
+	pinctrl-names = "default";
+
 	pinctrl_buck2: vddarmgrp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x19
@@ -464,6 +549,27 @@
 		>;
 	};
 
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL	0x40000067
+			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA	0x40000067
+		>;
+	};
+
+	pinctrl_i2c1_gpio: i2c1grp-gpio {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14        		0x7f
+			MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15        		0x7f
+		>;
+	};
+
+	pinctrl_i2c2_gpio: i2c2grp-gpio {
+		fsl,pins = <
+			MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16        		0x7f
+			MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17        		0x7f
+		>;
+	};
+
 	pinctrl_pcie0: pcie0grp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B		0x76
@@ -485,6 +591,7 @@
 
 	pinctrl_reg_usdhc2: regusdhc2gpiogrp {
 		fsl,pins = <
+			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
 			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0x41
 		>;
 	};
@@ -506,6 +613,18 @@
 		>;
 	};
 
+	pinctrl_ss_sel: usb3ssgrp{
+		fsl,pins = <
+			MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15		0x16
+		>;
+	};
+
+	pinctrl_typec: typecgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3		0x17059
+		>;
+	};
+
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
diff --git a/arch/arm/dts/imx8mq-pinfunc.h b/arch/arm/dts/imx8mq-pinfunc.h
index 68e8fa17297..760321ac5f9 100644
--- a/arch/arm/dts/imx8mq-pinfunc.h
+++ b/arch/arm/dts/imx8mq-pinfunc.h
@@ -555,12 +555,12 @@
 #define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21                                 0x228 0x490 0x000 0x7 0x0
 #define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL                                      0x22C 0x494 0x000 0x0 0x0
 #define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT                                      0x22C 0x494 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B                                0x22C 0x494 0x524 0x2 0x0
+#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B                                0x22C 0x494 0x524 0x12 0x0
 #define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20                                    0x22C 0x494 0x000 0x5 0x0
 #define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22                                 0x22C 0x494 0x000 0x7 0x0
 #define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA                                      0x230 0x498 0x000 0x0 0x0
 #define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT                                      0x230 0x498 0x000 0x1 0x0
-#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B                                0x230 0x498 0x528 0x2 0x0
+#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B                                0x230 0x498 0x528 0x12 0x0
 #define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21                                    0x230 0x498 0x000 0x5 0x0
 #define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23                                 0x230 0x498 0x000 0x7 0x0
 #define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX                                 0x234 0x49C 0x4F4 0x0 0x0
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index 71bf497f99c..1da379d872f 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -37,9 +37,9 @@
 		serial1 = &uart2;
 		serial2 = &uart3;
 		serial3 = &uart4;
-		spi0 = &ecspi1;
-		spi1 = &ecspi2;
-		spi2 = &ecspi3;
+		usb0 = &usb_dwc3_0;
+		usb1 = &usb_dwc3_1;
+		spi0 = &qspi0;
 	};
 
 	ckil: clock-ckil {
@@ -204,7 +204,7 @@
 		cpu_thermal: cpu-thermal {
 			polling-delay-passive = <250>;
 			polling-delay = <2000>;
-			thermal-sensors = <&tmu 0>;
+			thermal-sensors = <&tmu>;
 
 			trips {
 				cpu_alert: cpu-alert {
@@ -231,48 +231,6 @@
 				};
 			};
 		};
-
-		gpu-thermal {
-			polling-delay-passive = <250>;
-			polling-delay = <2000>;
-			thermal-sensors = <&tmu 1>;
-
-			trips {
-				gpu_alert: gpu-alert {
-					temperature = <80000>;
-					hysteresis = <2000>;
-					type = "passive";
-				};
-
-				gpu-crit {
-					temperature = <90000>;
-					hysteresis = <2000>;
-					type = "critical";
-				};
-			};
-
-			cooling-maps {
-				map0 {
-					trip = <&gpu_alert>;
-					cooling-device =
-						<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-				};
-			};
-		};
-
-		vpu-thermal {
-			polling-delay-passive = <250>;
-			polling-delay = <2000>;
-			thermal-sensors = <&tmu 2>;
-
-			trips {
-				vpu-crit {
-					temperature = <90000>;
-					hysteresis = <2000>;
-					type = "critical";
-				};
-			};
-		};
 	};
 
 	timer {
@@ -294,6 +252,11 @@
 		nvmem-cells = <&imx8mq_uid>;
 		nvmem-cell-names = "soc_unique_id";
 
+		caam_sm: caam-sm@100000 {
+			compatible = "fsl,imx6q-caam-sm";
+			reg = <0x100000 0x8000>;
+		};
+
 		bus@30000000 { /* AIPS1 */
 			compatible = "fsl,aips-bus", "simple-bus";
 			reg = <0x30000000 0x400000>;
@@ -428,6 +391,7 @@
 				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
 				little-endian;
+				u-boot,dm-pre-reloc;
 				fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
 				fsl,tmu-calibration = <0x00000000 0x00000023
 						       0x00000001 0x00000029
@@ -472,7 +436,7 @@
 						       0x00030005 0x00000053
 						       0x00030006 0x0000005f
 						       0x00030007 0x00000071>;
-				#thermal-sensor-cells =  <1>;
+				#thermal-sensor-cells =  <0>;
 			};
 
 			wdog1: watchdog@30280000 {
@@ -576,6 +540,20 @@
 				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 			};
 
+			irq_sec_vio: caam_secvio {
+				compatible = "fsl,imx6q-caam-secvio";
+				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+				jtag-tamper = "disabled";
+				watchdog-tamper = "enabled";
+				internal-boot-tamper = "enabled";
+				external-pin-tamper = "disabled";
+			};
+
+			caam_snvs: caam-snvs@30370000 {
+				compatible = "fsl,imx6q-caam-snvs";
+				reg = <0x30370000 0x10000>;
+			};
+
 			snvs: snvs@30370000 {
 				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 				reg = <0x30370000 0x10000>;
@@ -616,25 +594,20 @@
 				              "clk_ext3", "clk_ext4";
 				assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
 						  <&clk IMX8MQ_CLK_A53_CORE>,
+						  <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 						  <&clk IMX8MQ_CLK_NOC>,
 						  <&clk IMX8MQ_CLK_AUDIO_AHB>,
-						  <&clk IMX8MQ_AUDIO_PLL1_BYPASS>,
-						  <&clk IMX8MQ_AUDIO_PLL2_BYPASS>,
 						  <&clk IMX8MQ_AUDIO_PLL1>,
 						  <&clk IMX8MQ_AUDIO_PLL2>;
-				assigned-clock-rates = <0>, <0>,
-						       <800000000>,
-						       <0>,
-						       <0>,
-						       <0>,
+				assigned-clock-rates = <0>, <0>, <266000000>,
+						       <800000000>, <0>,
 						       <786432000>,
 						       <722534400>;
 				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
 							 <&clk IMX8MQ_ARM_PLL_OUT>,
 							 <0>,
-							 <&clk IMX8MQ_SYS2_PLL_500M>,
-							 <&clk IMX8MQ_AUDIO_PLL1>,
-							 <&clk IMX8MQ_AUDIO_PLL2>;
+							 <&clk IMX8MQ_SYS1_PLL_800M>,
+							 <&clk IMX8MQ_SYS2_PLL_500M>;
 			};
 
 			src: reset-controller@30390000 {
@@ -969,6 +942,7 @@
 					compatible = "fsl,sec-v4.0-job-ring";
 					reg = <0x1000 0x1000>;
 					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+					status = "disabled";
 				};
 
 				sec_jr1: jr@2000 {
@@ -991,14 +965,20 @@
 					 <&clk IMX8MQ_CLK_DSI_AHB>,
 					 <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
 					 <&clk IMX8MQ_CLK_DSI_PHY_REF>,
+					 <&clk IMX8MQ_VIDEO_PLL1>,
 					 <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
-				clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
-				assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
+				clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "video_pll", "lcdif";
+				assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>,
 						  <&clk IMX8MQ_CLK_DSI_CORE>,
+						  <&clk IMX8MQ_CLK_DSI_AHB>,
 						  <&clk IMX8MQ_CLK_DSI_IPG_DIV>;
-				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
-							 <&clk IMX8MQ_SYS1_PLL_266M>;
-				assigned-clock-rates = <80000000>, <266000000>, <20000000>;
+				assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
+							 <&clk IMX8MQ_SYS1_PLL_266M>,
+							 <&clk IMX8MQ_SYS1_PLL_80M>;
+				assigned-clock-rates = <27000000>,
+						       <266000000>,
+						       <80000000>,
+						       <20000000>;
 				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 				mux-controls = <&mux 0>;
 				power-domains = <&pgc_mipi>;
@@ -1292,6 +1272,7 @@
 				nvmem-cell-names = "mac-address";
 				nvmem_macaddr_swap;
 				fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
+				fsl,wakeup_irq = <2>;
 				status = "disabled";
 			};
 		};
@@ -1328,6 +1309,14 @@
 			#size-cells = <1>;
 			ranges = <0x32c00000 0x32c00000 0x400000>;
 
+			hdmi: hdmi@32c00000 {
+				reg = <0x32c00000 0x100000>,
+					<0x32e40000 0x40000>;
+				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+							 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "plug_in", "plug_out";
+			};
+
 			irqsteer: interrupt-controller@32e2d000 {
 				compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
 				reg = <0x32e2d000 0x1000>;
@@ -1339,6 +1328,35 @@
 				interrupt-controller;
 				#interrupt-cells = <1>;
 			};
+
+			dcss: display-controller@32e00000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "nxp,imx8mq-dcss";
+				reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
+				interrupts = <6>, <8>, <9>, <16>, <17>;
+				interrupt-names = "ctx_ld", "ctxld_kick", "vblank",
+								  "dtrc_ch1", "dtrc_ch2";
+				interrupt-parent = <&irqsteer>;
+				clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
+					 <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
+					 <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
+					 <&clk IMX8MQ_VIDEO2_PLL_OUT>,
+					 <&clk IMX8MQ_CLK_DISP_DTRC>,
+					 <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>,
+					 <&clk IMX8MQ_CLK_PHY_27MHZ>;
+				clock-names = "apb", "axi", "rtrm", "pix", "dtrc", "pll_src",
+						      "pll_phy_ref";
+				assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>,
+						  <&clk IMX8MQ_CLK_DISP_RTRM>,
+						  <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
+				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
+							 <&clk IMX8MQ_SYS1_PLL_800M>,
+							 <&clk IMX8MQ_CLK_27M>;
+				assigned-clock-rates = <800000000>,
+							   <400000000>;
+				status = "disabled";
+			};
 		};
 
 		gpu: gpu@38000000 {
@@ -1364,6 +1382,7 @@
 			assigned-clock-rates = <800000000>, <800000000>,
 			                       <800000000>, <800000000>, <0>;
 			power-domains = <&pgc_gpu>;
+			status = "disabled";
 		};
 
 		usb_dwc3_0: usb@38100000 {
@@ -1383,6 +1402,7 @@
 			phy-names = "usb2-phy", "usb3-phy";
 			power-domains = <&pgc_otg1>;
 			usb3-resume-missing-cas;
+			snps,power-down-scale = <2>;
 			status = "disabled";
 		};
 
@@ -1415,6 +1435,7 @@
 			phy-names = "usb2-phy", "usb3-phy";
 			power-domains = <&pgc_otg2>;
 			usb3-resume-missing-cas;
+			snps,power-down-scale = <2>;
 			status = "disabled";
 		};
 
@@ -1430,30 +1451,33 @@
 			status = "disabled";
 		};
 
-		vpu: video-codec@38300000 {
-			compatible = "nxp,imx8mq-vpu";
-			reg = <0x38300000 0x10000>,
-			      <0x38310000 0x10000>,
-			      <0x38320000 0x10000>;
-			reg-names = "g1", "g2", "ctrl";
-			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "g1", "g2";
-			clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
-				 <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
-				 <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
-			clock-names = "g1", "g2", "bus";
-			assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
-					  <&clk IMX8MQ_CLK_VPU_G2>,
-					  <&clk IMX8MQ_CLK_VPU_BUS>,
-					  <&clk IMX8MQ_VPU_PLL_BYPASS>;
-			assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
-						 <&clk IMX8MQ_VPU_PLL_OUT>,
-						 <&clk IMX8MQ_SYS1_PLL_800M>,
-						 <&clk IMX8MQ_VPU_PLL>;
-			assigned-clock-rates = <600000000>, <600000000>,
-					       <800000000>, <0>;
-			power-domains = <&pgc_vpu>;
+		dma_apbh: dma-apbh@33000000 {
+			compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
+			reg = <0x33000000 0x2000>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+			#dma-cells = <1>;
+			dma-channels = <4>;
+			clocks = <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
+		};
+
+		gpmi: gpmi-nand@33002000{
+			compatible = "fsl,imx7d-gpmi-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
+			reg-names = "gpmi-nand", "bch";
+			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "bch";
+			clocks = <&clk IMX8MQ_CLK_RAWNAND_ROOT>,
+				<&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
+			clock-names = "gpmi_io", "gpmi_bch_apb";
+			dmas = <&dma_apbh 0>;
+			dma-names = "rx-tx";
+			status = "disabled";
 		};
 
 		pcie0: pcie@33800000 {
@@ -1468,8 +1492,10 @@
 			ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
 				 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
 			num-lanes = <1>;
-			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "msi";
+			num-viewport = <4>;
+			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+			interrupt-names = "msi", "dma";
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0x7>;
 			interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
@@ -1505,8 +1531,10 @@
 			ranges =  <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */
 				  <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
 			num-lanes = <1>;
-			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "msi";
+			num-viewport = <4>;
+			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+			interrupt-names = "msi", "dma";
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0x7>;
 			interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
@@ -1560,5 +1588,20 @@
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 		};
+
+		vpu: vpu@38300000 {
+			compatible = "nxp,imx8mq-hantro";
+			reg = <0x38300000 0x200000>;
+			reg-names = "regs_hantro";
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "irq_hantro_g1", "irq_hantro_g2";
+			clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, <&clk IMX8MQ_CLK_VPU_G2_ROOT>, <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+			clock-names = "clk_hantro_g1", "clk_hantro_g2", "clk_hantro_bus";
+			assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, <&clk IMX8MQ_CLK_VPU_G2>, <&clk IMX8MQ_CLK_VPU_BUS>;
+			assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_SYS1_PLL_800M>;
+			assigned-clock-rates = <600000000>, <600000000>, <800000000>;
+			power-domains = <&pgc_vpu>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/arch/arm/dts/imx8ulp-9x9-evk-i3c.dts b/arch/arm/dts/imx8ulp-9x9-evk-i3c.dts
new file mode 100644
index 00000000000..9df26207912
--- /dev/null
+++ b/arch/arm/dts/imx8ulp-9x9-evk-i3c.dts
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2022 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8ulp-9x9-evk.dts"
+
+&fec {
+	status = "disabled";
+};
+
+&lpspi5 {
+	status = "disabled";
+};
+
+&i3c2 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_i3c2>;
+	pinctrl-1 = <&pinctrl_i3c2>;
+	status = "okay";
+};
+
+&iomuxc1 {
+	pinctrl_i3c2: i3c2grp {
+		fsl,pins = <
+			MX8ULP_PAD_PTE19__I3C2_PUR	0x3
+			MX8ULP_PAD_PTF6__I3C2_SCL	0x3
+			MX8ULP_PAD_PTF7__I3C2_SDA	0x3
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8ulp-9x9-evk.dts b/arch/arm/dts/imx8ulp-9x9-evk.dts
new file mode 100644
index 00000000000..81adc5d69c0
--- /dev/null
+++ b/arch/arm/dts/imx8ulp-9x9-evk.dts
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8ulp-evk.dts"
+#include "imx8ulp-evk-u-boot.dtsi"
+
+/ {
+	model = "NXP i.MX8ULP 9X9 EVK";
+};
+
+&{/soc@0/bus@2d800000/dsi@2db00000/panel@0} {
+	reset-gpios = <&gpiof 21 GPIO_ACTIVE_LOW>;
+};
+
+&pinctrl_dsi {
+	fsl,pins = <
+		MX8ULP_PAD_PTF21__PTF21		0x3
+	>;
+};
+
+&pinctrl_enet {
+	fsl,pins = <
+		MX8ULP_PAD_PTF9__ENET0_MDC     0x43
+		MX8ULP_PAD_PTF8__ENET0_MDIO    0x43
+		MX8ULP_PAD_PTF5__ENET0_RXER    0x43
+		MX8ULP_PAD_PTF6__ENET0_CRS_DV  0x43
+		MX8ULP_PAD_PTF1__ENET0_RXD0     0x43
+		MX8ULP_PAD_PTF0__ENET0_RXD1    0x43
+		MX8ULP_PAD_PTF4__ENET0_TXEN    0x43
+		MX8ULP_PAD_PTF3__ENET0_TXD0    0x43
+		MX8ULP_PAD_PTF2__ENET0_TXD1    0x43
+		MX8ULP_PAD_PTF7__ENET0_REFCLK  0x43
+		MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
+	>;
+};
+
+&pinctrl_otgid1 {
+	fsl,pins = <
+		MX8ULP_PAD_PTE16__USB0_ID	0x10003
+		MX8ULP_PAD_PTE18__USB0_OC	0x10003
+	>;
+};
+
+&pinctrl_otgid2 {
+	fsl,pins = <
+		MX8ULP_PAD_PTD23__USB1_ID	0x10003
+		MX8ULP_PAD_PTE20__USB1_OC	0x10003
+	>;
+};
\ No newline at end of file
diff --git a/arch/arm/dts/imx8ulp-evk-i3c.dts b/arch/arm/dts/imx8ulp-evk-i3c.dts
new file mode 100644
index 00000000000..4f83ecd7cb4
--- /dev/null
+++ b/arch/arm/dts/imx8ulp-evk-i3c.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8ulp-evk.dts"
+#include "imx8ulp-evk-u-boot.dtsi"
+
+&fec {
+	status = "disabled";
+};
+
+&lpspi5 {
+	status = "disabled";
+};
+
+&i3c2 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_i3c2>;
+	pinctrl-1 = <&pinctrl_i3c2>;
+	switch-gpio = <&pcal6416 10 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&iomuxc1 {
+	pinctrl_i3c2: i3c2grp {
+		fsl,pins = <
+			MX8ULP_PAD_PTE15__I3C2_PUR	0x3
+			MX8ULP_PAD_PTE22__I3C2_SCL	0x3
+			MX8ULP_PAD_PTE23__I3C2_SDA	0x3
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
index 7c1dab2acfc..b22d62c0d9f 100644
--- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
@@ -3,10 +3,48 @@
  * Copyright 2021 NXP
  */
 
+/ {
+	aliases {
+		usbgadget0 = &usbg1;
+		usbgadget1 = &usbg2;
+	};
+
+	usbg1: usbg1 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg1>;
+		status = "okay";
+	};
+
+	usbg2: usbg2 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg2>;
+		status = "okay";
+	};
+
+	dsi_host: dsi-host {
+		compatible = "northwest,mipi-dsi";
+		status = "okay";
+	};
+};
+
 &{/soc@0} {
 	u-boot,dm-spl;
 };
 
+&{/firmware} {
+	u-boot,dm-pre-reloc;
+};
+
+&{/firmware/scmi} {
+	u-boot,dm-pre-reloc;
+};
+
+&{/firmware/scmi/protocol@15} {
+	u-boot,dm-pre-reloc;
+};
+
 &per_bridge3 {
 	u-boot,dm-spl;
 };
@@ -17,6 +55,7 @@
 
 &iomuxc1 {
 	u-boot,dm-spl;
+	fsl,mux_mask = <0xf00>;
 };
 
 &pinctrl_lpuart5 {
@@ -33,8 +72,62 @@
 
 &usdhc0 {
 	u-boot,dm-spl;
+	mmc-hs400-1_8v;
+	mmc-hs400-enhanced-strobe;
 };
 
 &pinctrl_usdhc0 {
 	u-boot,dm-spl;
 };
+
+&crypto {
+	u-boot,dm-spl;
+};
+
+&sec_jr0 {
+	u-boot,dm-spl;
+};
+
+&sec_jr1 {
+	u-boot,dm-spl;
+};
+
+&sec_jr2 {
+	u-boot,dm-spl;
+};
+
+&sec_jr3 {
+	u-boot,dm-spl;
+};
+
+&lpi2c0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	pcal6416: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&scmi_buf {
+	reg = <0x0 0x1000>; /* Align page size */
+};
+
+&dsi {
+	data-lanes-num = <4>;
+};
+
+&usbotg1 {
+	compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx27-usb";
+	fsl,usbphy = <&usbphy1>;
+};
+
+&usbotg2 {
+	compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx27-usb";
+	fsl,usbphy = <&usbphy2>;
+};
diff --git a/arch/arm/dts/imx8ulp-evk.dts b/arch/arm/dts/imx8ulp-evk.dts
index da09ff48ff8..041bb0b6b6a 100644
--- a/arch/arm/dts/imx8ulp-evk.dts
+++ b/arch/arm/dts/imx8ulp-evk.dts
@@ -8,7 +8,7 @@
 #include "imx8ulp.dtsi"
 
 / {
-	model = "FSL i.MX8ULP EVK";
+	model = "NXP i.MX8ULP EVK";
 	compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
 
 	chosen {
@@ -16,10 +16,76 @@
 		bootargs = "console=ttyLP1,115200 earlycon";
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0 0x28000000>;
+			linux,cma-default;
+		};
+
+	};
+
+	reg_5v: regulator-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+	};
+
 	usdhc2_pwrseq: usdhc2_pwrseq {
 		compatible = "mmc-pwrseq-simple";
 		reset-gpios = <&pcal6408 2 GPIO_ACTIVE_LOW>;
 	};
+
+};
+
+
+&clock_ext_ts {
+	/* External ts clock is 50MHZ from PHY on EVK board. */
+	clock-frequency = <50000000>;
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
+	assigned-clock-parents = <&clock_ext_ts>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy>;
+	status = "okay";
+
+	phy-reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy: ethernet-phy {
+			reg = <1>;
+			micrel,led-mode = <1>;
+		};
+	};
+};
+
+&flexspi2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi2_ptd>;
+	status = "okay";
+
+	flash1: mt35xu512aba@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <29000000>;
+		spi-nor,ddr-quad-read-dummy = <8>;
+	};
 };
 
 &lpuart5 {
@@ -30,86 +96,84 @@
 	status = "okay";
 };
 
-&iomuxc1 {
-	pinctrl_lpuart5: lpuart5grp {
-		fsl,pins = <
-			MX8ULP_PAD_PTF14__LPUART5_TX	0x03
-			MX8ULP_PAD_PTF15__LPUART5_RX	0x03
-		>;
-	};
+&lpi2c0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	status = "okay";
 
-	pinctrl_lpi2c7: lpi2c7grp {
-		fsl,pins = <
-			MX8ULP_PAD_PTE12__LPI2C7_SCL	0x27
-			MX8ULP_PAD_PTE13__LPI2C7_SDA	0x27
-		>;
+	pcal6416: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
 	};
+};
 
-	pinctrl_usdhc0: usdhc0grp {
-		fsl,pins = <
-			MX8ULP_PAD_PTD0__SDHC0_RESET_B  0x43
-			MX8ULP_PAD_PTD1__SDHC0_CMD	0x43
-			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10042
-			MX8ULP_PAD_PTD10__SDHC0_D0	0x43
-			MX8ULP_PAD_PTD9__SDHC0_D1	0x43
-			MX8ULP_PAD_PTD8__SDHC0_D2	0x43
-			MX8ULP_PAD_PTD7__SDHC0_D3	0x43
-			MX8ULP_PAD_PTD6__SDHC0_D4	0x43
-			MX8ULP_PAD_PTD5__SDHC0_D5	0x43
-			MX8ULP_PAD_PTD4__SDHC0_D6	0x43
-			MX8ULP_PAD_PTD3__SDHC0_D7	0x43
-			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10042
-		>;
-	};
+&lpi2c7 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c7>;
+	status = "okay";
 
-	pinctrl_usdhc2_pte: usdhc2ptegrp {
-		fsl,pins = <
-			MX8ULP_PAD_PTE1__SDHC2_D0	0x43
-			MX8ULP_PAD_PTE0__SDHC2_D1	0x43
-			MX8ULP_PAD_PTE5__SDHC2_D2	0x43
-			MX8ULP_PAD_PTE4__SDHC2_D3	0x43
-			MX8ULP_PAD_PTE2__SDHC2_CLK	0x10042
-			MX8ULP_PAD_PTE3__SDHC2_CMD	0x43
-			MX8ULP_PAD_PTE7__PTE7		0x10003
-		>;
+	pcal6408: gpio@21 {
+		compatible = "ti,tca6408";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
 	};
+};
 
-	pinctrl_fec: fecgrp {
-		fsl,pins = <
-			MX8ULP_PAD_PTE14__ENET0_MDIO		0x43
-			MX8ULP_PAD_PTE15__ENET0_MDC	0x43
-			MX8ULP_PAD_PTE18__ENET0_CRS_DV	0x43
-			MX8ULP_PAD_PTE17__ENET0_RXER	0x43
-			MX8ULP_PAD_PTF1__ENET0_RXD0	0x43
-			MX8ULP_PAD_PTE20__ENET0_RXD1	0x43
-			MX8ULP_PAD_PTE16__ENET0_TXEN	0x43
-			MX8ULP_PAD_PTE23__ENET0_TXD0	0x43
-			MX8ULP_PAD_PTE22__ENET0_TXD1	0x43
-			MX8ULP_PAD_PTE19__ENET0_REFCLK	0x10043
-			MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x10043
-		>;
-	};
+&usbotg1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_otgid1>;
+	pinctrl-1 = <&pinctrl_otgid1>;
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	over-current-active-low;
+	status = "okay";
+};
 
-	pinctrl_usbotg0_id: otg0idgrp {
-		fsl,pins = <
-			MX8ULP_PAD_PTF2__USB0_ID	0x10003
-		>;
-	};
+&usbphy1 {
+	status = "okay";
+};
 
-	pinctrl_usbotg1_id: otg1idgrp {
-		fsl,pins = <
-			MX8ULP_PAD_PTD23__USB1_ID	0x10003
-		>;
-	};
+&usbmisc1 {
+	status = "okay";
+};
+
+&usbotg2 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_otgid2>;
+	pinctrl-1 = <&pinctrl_otgid2>;
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	over-current-active-low;
+	status = "okay";
+};
+
+&usbphy2 {
+	status = "okay";
+};
+
+&usbmisc2 {
+	status = "okay";
 };
 
 &usdhc0 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
 	pinctrl-0 = <&pinctrl_usdhc0>;
 	pinctrl-1 = <&pinctrl_usdhc0>;
 	pinctrl-2 = <&pinctrl_usdhc0>;
-	bus-width = <8>;
+	pinctrl-3 = <&pinctrl_usdhc0>;
 	non-removable;
+	bus-width = <8>;
 	status = "okay";
 };
 
@@ -135,20 +199,102 @@
 	};
 };
 
-&lpi2c7 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	clock-frequency = <100000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lpi2c7>;
-	status = "okay";
+&iomuxc1 {
+	pinctrl_dsi: dsigrp {
+		fsl,pins = <
+			MX8ULP_PAD_PTF8__PTF8		0x3
+		>;
+	};
 
-	pcal6408: gpio@21 {
-		compatible = "ti,tca6408";
-		reg = <0x21>;
-		gpio-controller;
-		#gpio-cells = <2>;
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX8ULP_PAD_PTE15__ENET0_MDC     0x43
+			MX8ULP_PAD_PTE14__ENET0_MDIO    0x43
+			MX8ULP_PAD_PTE17__ENET0_RXER    0x43
+			MX8ULP_PAD_PTE18__ENET0_CRS_DV  0x43
+			MX8ULP_PAD_PTF1__ENET0_RXD0     0x43
+			MX8ULP_PAD_PTE20__ENET0_RXD1    0x43
+			MX8ULP_PAD_PTE16__ENET0_TXEN    0x43
+			MX8ULP_PAD_PTE23__ENET0_TXD0    0x43
+			MX8ULP_PAD_PTE22__ENET0_TXD1    0x43
+			MX8ULP_PAD_PTE19__ENET0_REFCLK  0x43
+			MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
+		>;
+	};
+
+	pinctrl_flexspi2_ptd: flexspi2ptdgrp {
+		fsl,pins = <
+
+			MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B	0x42
+			MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK	0x42
+			MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3	0x42
+			MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2	0x42
+			MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1	0x42
+			MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0	0x42
+			MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS	0x42
+			MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7	0x42
+			MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6	0x42
+			MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5	0x42
+			MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4	0x42
+		>;
+	};
+
+	pinctrl_lpuart5: lpuart5grp {
+		fsl,pins = <
+			MX8ULP_PAD_PTF14__LPUART5_TX	0x3
+			MX8ULP_PAD_PTF15__LPUART5_RX	0x3
+		>;
 	};
+
+	pinctrl_lpi2c7: lpi2c7grp {
+		fsl,pins = <
+			MX8ULP_PAD_PTE12__LPI2C7_SCL	0x20
+			MX8ULP_PAD_PTE13__LPI2C7_SDA	0x20
+		>;
+	};
+
+	pinctrl_otgid1: usb1grp {
+		fsl,pins = <
+			MX8ULP_PAD_PTF2__USB0_ID	0x10003
+			MX8ULP_PAD_PTF4__USB0_OC	0x10003
+		>;
+	};
+
+	pinctrl_otgid2: usb2grp {
+		fsl,pins = <
+			MX8ULP_PAD_PTD23__USB1_ID	0x10003
+			MX8ULP_PAD_PTF6__USB1_OC	0x10003
+		>;
+	};
+
+	pinctrl_usdhc0: usdhc0grp {
+		fsl,pins = <
+			MX8ULP_PAD_PTD1__SDHC0_CMD	0x3
+			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10002
+			MX8ULP_PAD_PTD10__SDHC0_D0	0x3
+			MX8ULP_PAD_PTD9__SDHC0_D1	0x3
+			MX8ULP_PAD_PTD8__SDHC0_D2	0x3
+			MX8ULP_PAD_PTD7__SDHC0_D3	0x3
+			MX8ULP_PAD_PTD6__SDHC0_D4	0x3
+			MX8ULP_PAD_PTD5__SDHC0_D5	0x3
+			MX8ULP_PAD_PTD4__SDHC0_D6	0x3
+			MX8ULP_PAD_PTD3__SDHC0_D7	0x3
+			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10002
+		>;
+	};
+
+	pinctrl_usdhc2_pte: usdhc2ptegrp {
+		fsl,pins = <
+			MX8ULP_PAD_PTE1__SDHC2_D0	0x3
+			MX8ULP_PAD_PTE0__SDHC2_D1	0x3
+			MX8ULP_PAD_PTE5__SDHC2_D2	0x3
+			MX8ULP_PAD_PTE4__SDHC2_D3	0x3
+			MX8ULP_PAD_PTE2__SDHC2_CLK	0x10002
+			MX8ULP_PAD_PTE3__SDHC2_CMD	0x3
+			MX8ULP_PAD_PTE7__PTE7		0x10003
+		>;
+	};
+
 };
 
 &flexspi0 {
@@ -163,61 +309,41 @@
 	};
 };
 
-&flexspi2 {
+&dsi {
 	status = "okay";
 
-	flash1: mt35xu512aba@0 {
+	panel@0 {
+		compatible = "rocktech,hx8394f";
 		reg = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <29000000>;
-		spi-nor,ddr-quad-read-dummy = <8>;
-	};
-};
-
-&fec {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_fec>;
-	phy-mode = "rmii";
-	phy-handle = <&ethphy>;
-	status = "okay";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_dsi>;
+		himax,dsi-lanes = <2>;
+		reset-gpios = <&gpiof 8 GPIO_ACTIVE_LOW>;
+		vcc-supply = <&reg_5v>;
+		iovcc-supply = <&reg_5v>;
 
-	phy-reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&mipi_dsi_out>;
+			};
+		};
+	};
 
-		ethphy: ethernet-phy@1 {
+	ports {
+		port@1 {
 			reg = <1>;
-			micrel,led-mode = <1>;
+
+			mipi_dsi_out: endpoint {
+				remote-endpoint = <&panel_in>;
+			};
 		};
 	};
 };
 
-&usbotg0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usbotg0_id>;
-	srp-disable;
-	hnp-disable;
-	adp-disable;
+&dcnano {
 	status = "okay";
 };
 
-&usbphy0 {
-	fsl,tx-d-cal = <88>;
-};
-
-&usbotg1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usbotg1_id>;
-	srp-disable;
-	hnp-disable;
-	adp-disable;
+&dphy {
 	status = "okay";
 };
-
-&usbphy1 {
-	fsl,tx-d-cal = <88>;
-};
diff --git a/arch/arm/dts/imx8ulp.dtsi b/arch/arm/dts/imx8ulp.dtsi
index d3b16bd2feb..901766957df 100644
--- a/arch/arm/dts/imx8ulp.dtsi
+++ b/arch/arm/dts/imx8ulp.dtsi
@@ -6,6 +6,10 @@
 #include <dt-bindings/clock/imx8ulp-clock.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/imx8ulp-pcc-reset.h>
+#include <dt-bindings/power/imx8ulp-power.h>
+#include <dt-bindings/reset/imx8ulp-sim-reset.h>
+
 #include "imx8ulp-pinfunc.h"
 
 / {
@@ -24,39 +28,25 @@
 		spi0 = &flexspi0;
 		spi2 = &flexspi2;
 		ethernet0 = &fec;
+		i2c0 = &lpi2c0;
 		i2c7 = &lpi2c7;
-		usbphy0 = &usbphy0;
-		usb0 = &usbotg0;
-		usbphy1 = &usbphy1;
-		usb1 = &usbotg1;
+		i2c8 = &i3c2;
+		usbphy0 = &usbphy1;
+		usb0 = &usbotg1;
+		usbphy1 = &usbphy2;
+		usb1 = &usbotg2;
 	};
 
-	cpus: cpus {
+	cpus {
 		#address-cells = <2>;
 		#size-cells = <0>;
 
-		idle-states {
-			entry-method = "psci";
-
-			CPU_SLEEP: cpu-sleep {
-				compatible = "arm,idle-state";
-				arm,psci-suspend-param = <0x0010033>;
-				local-timer-stop;
-				entry-latency-us = <1000>;
-				exit-latency-us = <700>;
-				min-residency-us = <2700>;
-				wakeup-latency-us = <1500>;
-			};
-		};
-
-		/* We have 1 clusters with 4 Cortex-A35 cores */
 		A35_0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a35";
 			reg = <0x0 0x0>;
 			enable-method = "psci";
 			next-level-cache = <&A35_L2>;
-			clocks = <&cgc1 IMX8ULP_CLK_A35_DIV>;
 		};
 
 		A35_1: cpu@1 {
@@ -65,7 +55,6 @@
 			reg = <0x0 0x1>;
 			enable-method = "psci";
 			next-level-cache = <&A35_L2>;
-			clocks = <&cgc1 IMX8ULP_CLK_A35_DIV>;
 		};
 
 		A35_L2: l2-cache0 {
@@ -73,32 +62,7 @@
 		};
 	};
 
-	a35_opp_table: opp-table {
-		compatible = "operating-points-v2";
-		opp-shared;
-
-		opp-504000000 {
-			opp-hz = /bits/ 64 <504000000>;
-			opp-microvolt = <800000>;
-			clock-latency-ns = <150000>;
-		};
-
-		opp-744000000 {
-			opp-hz = /bits/ 64 <744000000>;
-			opp-microvolt = <900000>;
-			clock-latency-ns = <150000>;
-		};
-
-		opp-1008000000 {
-			opp-hz = /bits/ 64 <1008000000>;
-			opp-microvolt = <1000000>;
-			clock-latency-ns = <150000>;
-			opp-suspend;
-		};
-	};
-
 	s400_mu: mu@27020000 {
-		u-boot,dm-spl;
 		compatible = "fsl,imx8ulp-mu";
 		reg = <0 0x27020000 0 0x10000>;
 		status = "okay";
@@ -154,7 +118,20 @@
 		#clock-cells = <0>;
 	};
 
-	sram@0x2201f000 {
+	clock_ext_rmii: clock-ext-rmii {
+		compatible = "fixed-clock";
+		clock-frequency = <50000000>;
+		#clock-cells = <0>;
+		clock-output-names = "ext_rmii_clk";
+	};
+
+	clock_ext_ts: clock-ext-ts {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-output-names = "ext_ts_clk";
+	};
+
+	sram@2201f000 {
 		compatible = "mmio-sram";
 		reg = <0x0 0x2201f000 0x0 0x1000>;
 
@@ -162,10 +139,9 @@
 		#size-cells = <1>;
 		ranges = <0 0x0 0x2201f000 0x1000>;
 
-		/* TODO: split or unify */
-		scmi_pd: scmi_pd@0 {
+		scmi_buf: scmi_buf@0 {
 			compatible = "arm,scmi-shmem";
-			reg = <0x0 0x200>;
+			reg = <0x0 0x400>;
 		};
 	};
 
@@ -175,25 +151,36 @@
 			arm,smc-id = <0xc20000fe>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			shmem = <&scmi_pd>;
+			shmem = <&scmi_buf>;
 
 			scmi_devpd: protocol@11 {
 				reg = <0x11>;
 				#power-domain-cells = <1>;
 			};
 
-			scmi_perf: protocol@13 {
-				reg = <0x13>;
+			scmi_sensor: protocol@15 {
+				reg = <0x15>;
+				#thermal-sensor-cells = <0>;
 			};
 		};
 	};
 
+	rtc-rpmsg {
+		compatible = "fsl,imx-rpmsg-rtc";
+	};
+
 	soc@0 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges = <0x0 0x0 0x0 0x80000000>;
 
+		pmc: pmc@28359000 {
+			compatible = "fsl,imx8ulp-pmc-temperature";
+			reg = <0x28359000 0x1000>;
+			adc = <&adc1>;
+		};
+
 		per_bridge0: bus@28000000 {
 			compatible = "simple-bus";
 			reg = <0x28000000 0x800000>;
@@ -212,6 +199,24 @@
 			};
 		};
 
+		per_bridge1: bus@28080000 {
+			compatible = "simple-bus";
+			reg = <0x28080000 0x800000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			lpi2c0: lpi2c0@28098000 {
+				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
+				reg = <0x28098000 0x10000>;
+				status = "disabled";
+			};
+
+			adc1: adc1@0x280a2000 {
+				reg = <0x280a2000 0x1000>;
+			};
+		};
+
 		per_bridge3: bus@29000000 {
 			compatible = "simple-bus";
 			reg = <0x29000000 0x800000>;
@@ -335,18 +340,62 @@
 				timeout-sec = <40>;
 			};
 
+			crypto: crypto@292e0000 {
+				compatible = "fsl,sec-v4.0";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				reg = <0x292e0000 0x10000>;
+				ranges = <0 0x292e0000 0x10000>;
+				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc3 IMX8ULP_CLK_CAAM>,
+					<&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>;
+				clock-names = "ipg", "aclk";
+
+				sec_jr0: jr@1000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x1000 0x1000>;
+					interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+					status = "disabled";
+				};
+
+				sec_jr1: jr@2000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x2000 0x1000>;
+					interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				};
+
+				sec_jr2: jr@3000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x3000 0x1000>;
+					interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				};
+
+				sec_jr3: jr@4000 {
+					compatible = "fsl,sec-v4.0-job-ring";
+					reg = <0x4000 0x1000>;
+					interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				};
+			};
+
 			cgc1: clock-controller@292c0000 {
 				compatible = "fsl,imx8ulp-cgc1";
 				reg = <0x292c0000 0x10000>;
 				clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>;
 				clock-names = "rosc", "sosc", "frosc", "lposc";
 				#clock-cells = <1>;
+				assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3>,
+						  <&cgc1 IMX8ULP_CLK_SPLL3_PFD1>,
+						  <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>;
+				assigned-clock-rates = <540672000>,
+						       <540672000>,
+						       <12288000>;
 			};
 
 			pcc3: clock-controller@292d0000 {
 				compatible = "fsl,imx8ulp-pcc3";
 				reg = <0x292d0000 0x10000>;
 				#clock-cells = <1>;
+				#reset-cells = <1>;
 			};
 
 			tpm5: tpm@29340000 {
@@ -356,6 +405,52 @@
 				clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
 					 <&pcc3 IMX8ULP_CLK_TPM5>;
 				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			i3c2: i3c@29360000 {
+				compatible = "fsl,imx8ulp-i3c";
+				reg = <0x29360000 0x10000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc3 IMX8ULP_CLK_I3C2>,
+					 <&pcc3 IMX8ULP_CLK_I3C2>;
+				clock-names = "per", "ipg";
+				assigned-clocks = <&pcc3 IMX8ULP_CLK_I3C2>;
+				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
+				assigned-clock-rates = <48000000>;
+				status = "disabled";
+			};
+
+			lpi2c4: i2c@29370000 {
+				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
+				reg = <0x29370000 0x10000>;
+				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
+					 <&pcc3 IMX8ULP_CLK_LPI2C4>;
+				clock-names = "per", "ipg";
+				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
+				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
+				assigned-clock-rates = <48000000>;
+				dmas = <&edma1 46 0 0>, <&edma1 45 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpi2c5: i2c@29380000 {
+				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
+				reg = <0x29380000 0x10000>;
+				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
+					 <&pcc3 IMX8ULP_CLK_LPI2C5>;
+				clock-names = "per", "ipg";
+				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
+				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
+				assigned-clock-rates = <48000000>;
+				dmas = <&edma1 48 0 0>, <&edma1 47 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
 			};
 
 			lpuart4: serial@29390000 {
@@ -364,14 +459,57 @@
 				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
 				clock-names = "ipg";
+				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPUART4>;
+				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
+				assigned-clock-rates = <48000000>;
+				dmas = <&edma1 56 0 0>, <&edma1 55 0 1>;
+				dma-names = "tx","rx";
 				status = "disabled";
 			};
 
 			lpuart5: serial@293a0000 {
 				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
 				reg = <0x293a0000 0x1000>;
+				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
 				clock-names = "ipg";
+				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
+				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_CGC2_SOSC_DIV2>;
+				assigned-clock-rates = <24000000>;
+				status = "disabled";
+			};
+
+			lpspi4: spi@293b0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
+				reg = <0x293b0000 0x10000>;
+				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
+					 <&pcc3 IMX8ULP_CLK_LPSPI4>;
+				clock-names = "per", "ipg";
+				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
+				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
+				assigned-clock-rates = <48000000>;
+				dmas = <&edma1 64 0 0>, <&edma1 63 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpspi5: spi@293c0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
+				reg = <0x293c0000 0x10000>;
+				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
+					 <&pcc3 IMX8ULP_CLK_LPSPI5>;
+				clock-names = "per", "ipg";
+				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
+				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
+				assigned-clock-rates = <48000000>;
+				dmas = <&edma1 66 0 0>, <&edma1 65 0 1>;
+				dma-names = "tx","rx";
 				status = "disabled";
 			};
 		};
@@ -387,61 +525,135 @@
 				compatible = "fsl,imx8ulp-pcc4";
 				reg = <0x29800000 0x10000>;
 				#clock-cells = <1>;
+				#reset-cells = <1>;
+			};
+
+			flexspi2: spi@29810000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "nxp,imx8ulp-fspi";
+				reg = <0x29810000 0x10000>,
+					<0x60000000 0x10000000>;
+				reg-names = "fspi_base", "fspi_mmap";
+				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>,
+					 <&pcc4 IMX8ULP_CLK_FLEXSPI2>;
+				clock-names = "fspi", "fspi_en";
+				status = "disabled";
 			};
 
-			lpi2c6: lpi2c6@29840000 {
+			flexspi2_nand: flexspi2_nand@29810000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8-fspi-nand";
+				reg = <0x29810000 0x10000>, <0x60000000 0x10000000>;
+				reg-names = "FlexSPI", "FlexSPI-memory";
+				status = "disabled";
+			};
+
+			lpi2c6: i2c@29840000 {
 				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
 				reg = <0x29840000 0x10000>;
 				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
 					 <&pcc4 IMX8ULP_CLK_LPI2C6>;
 				clock-names = "per", "ipg";
+				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
+				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
+				assigned-clock-rates = <48000000>;
+				dmas = <&edma1 50 0 0>, <&edma1 49 0 1>;
+				dma-names = "tx","rx";
 				status = "disabled";
 			};
 
-			lpi2c7: lpi2c7@29850000 {
+			lpi2c7: i2c@29850000 {
 				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
 				reg = <0x29850000 0x10000>;
 				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
 					 <&pcc4 IMX8ULP_CLK_LPI2C7>;
 				clock-names = "per", "ipg";
+				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
+				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>;
+				assigned-clock-rates = <48000000>;
+				dmas = <&edma1 52 0 0>, <&edma1 51 0 1>;
+				dma-names = "tx","rx";
 				status = "disabled";
 			};
 
-			flexspi2: flexspi@29810000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "nxp,imx8ulp-fspi";
-				reg = <0x29810000 0x10000>,
-					<0x60000000 0xfffffff>;
-				reg-names = "fspi_base", "fspi_mmap";
+			lpuart6: serial@29860000 {
+				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x29860000 0x1000>;
+				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
+				clock-names = "ipg";
+				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
+				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
+				assigned-clock-rates = <48000000>;
+				dmas = <&edma1 60 0 0>, <&edma1 59 0 1>;
+				dma-names = "tx","rx";
 				status = "disabled";
 			};
 
-			flexspi2_nand: flexspi2_nand@29810000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "fsl,imx8-fspi-nand";
-				reg = <0x29810000 0x10000>, <0x60000000 0x10000000>;
-				reg-names = "FlexSPI", "FlexSPI-memory";
+			lpuart7: serial@29870000 {
+				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x29870000 0x1000>;
+				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
+				clock-names = "ipg";
+				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
+				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
+				assigned-clock-rates = <48000000>;
+				dmas = <&edma1 62 0 0>, <&edma1 61 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			sai4: sai@29880000 {
+				compatible = "fsl,imx8ulp-sai", "fsl,imx7ulp-sai";
+				reg = <0x29880000 0x10000>;
+				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc4 IMX8ULP_CLK_SAI4>, <&cgc1 IMX8ULP_CLK_DUMMY>,
+					 <&cgc1 IMX8ULP_CLK_SAI4_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
+					 <&cgc1 IMX8ULP_CLK_DUMMY>;
+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+				dmas = <&edma1 67 0 1>, <&edma1 68 0 0>;
+				dma-names = "rx", "tx";
+				fsl,dataline = <0 0x03 0x03>;
+				status = "disabled";
+			};
+
+			sai5: sai@29890000 {
+				compatible = "fsl,imx8ulp-sai", "fsl,imx7ulp-sai";
+				reg = <0x29890000 0x10000>;
+				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc4 IMX8ULP_CLK_SAI5>, <&cgc1 IMX8ULP_CLK_DUMMY>,
+					 <&cgc1 IMX8ULP_CLK_SAI5_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
+					 <&cgc1 IMX8ULP_CLK_DUMMY>;
+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+				dmas = <&edma1 69 0 1>, <&edma1 70 0 0>;
+				dma-names = "rx", "tx";
+				fsl,dataline = <0 0x0f 0x0f>;
 				status = "disabled";
 			};
 
 			iomuxc1: pinctrl@298c0000 {
 				compatible = "fsl,imx8ulp-iomuxc1";
 				reg = <0x298c0000 0x10000>;
-				fsl,mux_mask = <0xf00>;
 			};
 
 			usdhc0: mmc@298d0000 {
-				compatible = "fsl,imx8ulp-usdhc", "fsl,imx7ulp-usdhc";
+				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
 				reg = <0x298d0000 0x10000>;
 				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&cgc1 IMX8ULP_CLK_DUMMY>,
-					 <&cgc1 IMX8ULP_CLK_DUMMY>,
+				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
+					 <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
 					 <&pcc4 IMX8ULP_CLK_USDHC0>;
 				clock-names = "ipg", "ahb", "per";
+				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
+				assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2>, <&pcc4 IMX8ULP_CLK_USDHC0>;
+				assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>;
+				assigned-clock-rates = <396000000>, <396000000>;
 				fsl,tuning-start-tap = <20>;
 				fsl,tuning-step= <2>;
 				bus-width = <4>;
@@ -449,13 +661,17 @@
 			};
 
 			usdhc1: mmc@298e0000 {
-				compatible = "fsl,imx8ulp-usdhc", "fsl,imx7ulp-usdhc";
+				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
 				reg = <0x298e0000 0x10000>;
 				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&cgc1 IMX8ULP_CLK_DUMMY>,
-					 <&cgc1 IMX8ULP_CLK_DUMMY>,
+				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
+					 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
 					 <&pcc4 IMX8ULP_CLK_USDHC1>;
 				clock-names = "ipg", "ahb", "per";
+				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
+				assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2>, <&pcc4 IMX8ULP_CLK_USDHC1>;
+				assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>;
+				assigned-clock-rates = <396000000>, <396000000>;
 				fsl,tuning-start-tap = <20>;
 				fsl,tuning-step= <2>;
 				bus-width = <4>;
@@ -470,6 +686,7 @@
 					 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
 					 <&pcc4 IMX8ULP_CLK_USDHC2>;
 				clock-names = "ipg", "ahb", "per";
+				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
 				assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2>, <&pcc4 IMX8ULP_CLK_USDHC2>;
 				assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>;
 				assigned-clock-rates = <396000000>, <396000000>;
@@ -479,85 +696,85 @@
 				status = "disabled";
 			};
 
-			usbotg0: usb@29900000 {
-				compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb",
-					"fsl,imx27-usb";
+			usbotg1: usb@29900000 {
+				compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
 				reg = <0x29900000 0x200>;
 				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&pcc4 IMX8ULP_CLK_USB0>;
-				fsl,usbphy = <&usbphy0>;
-				fsl,usbmisc = <&usbmisc0 0>;
+				power-domains = <&scmi_devpd IMX8ULP_PD_USB0>;
+				phys = <&usbphy1>;
+				fsl,usbmisc = <&usbmisc1 0>;
 				ahb-burst-config = <0x0>;
 				tx-burst-size-dword = <0x8>;
 				rx-burst-size-dword = <0x8>;
 				status = "disabled";
 			};
 
-			usbmisc0: usbmisc@29900200 {
+			usbmisc1: usbmisc@29900200 {
+				compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc";
 				#index-cells = <1>;
-				compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc",
-					"fsl,imx6q-usbmisc";
 				reg = <0x29900200 0x200>;
+				status = "disabled";
 			};
 
-			usbphy0: usbphy@29910000 {
-				compatible = "fsl,imx8ulp-usbphy",
-					"fsl,imx7ulp-usbphy", "fsl,imx23-usbphy";
-				reg = <0x29910000 0x1000>;
+			usbphy1: usb-phy@29910000 {
+				compatible = "fsl,imx7ulp-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
+				reg = <0x29910000 0x10000>;
 				interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>;
+				#phy-cells = <0>;
+				status = "disabled";
 			};
 
-			usbotg1: usb@29920000 {
-				compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb",
-					"fsl,imx27-usb";
+			usbotg2: usb@29920000 {
+				compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
 				reg = <0x29920000 0x200>;
 				interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&pcc4 IMX8ULP_CLK_USB1>;
-				fsl,usbphy = <&usbphy1>;
-				fsl,usbmisc = <&usbmisc1 0>;
+				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
+				phys = <&usbphy2>;
+				fsl,usbmisc = <&usbmisc2 0>;
 				ahb-burst-config = <0x0>;
 				tx-burst-size-dword = <0x8>;
 				rx-burst-size-dword = <0x8>;
 				status = "disabled";
 			};
 
-			usbmisc1: usbmisc@29920200 {
+			usbmisc2: usbmisc@29920200 {
+				compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc";
 				#index-cells = <1>;
-				compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc",
-					"fsl,imx6q-usbmisc";
 				reg = <0x29920200 0x200>;
+				status = "disabled";
 			};
 
-			usbphy1: usbphy@29930000 {
-				compatible = "fsl,imx8ulp-usbphy",
-					"fsl,imx7ulp-usbphy", "fsl,imx23-usbphy";
-				reg = <0x29930000 0x1000>;
+			usbphy2: usb-phy@29930000 {
+				compatible = "fsl,imx7ulp-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
+				reg = <0x29930000 0x10000>;
 				interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>;
+				#phy-cells = <0>;
+				status = "disabled";
 			};
 
 			fec: ethernet@29950000 {
-				compatible = "fsl,imx8ulp-fec", "fsl,imx6sx-fec";
+				compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec";
 				reg = <0x29950000 0x10000>;
 				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc4 IMX8ULP_CLK_ENET>,
-					 <&pcc4 IMX8ULP_CLK_ENET>,
-					 <&cgc1 IMX8ULP_CLK_ENETSTAMP_SEL>,
+				interrupt-names = "int0";
+				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
 					 <&pcc4 IMX8ULP_CLK_ENET>,
-					 <&pcc4 IMX8ULP_CLK_ENET>;
-				clock-names = "ipg", "ahb", "ptp",
-					      "enet_clk_ref", "enet_out";
-				fsl,num-tx-queues = <3>;
-				fsl,num-rx-queues = <3>;
+					 <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
+					 <&clock_ext_rmii>;
+				clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
+				fsl,num-tx-queues = <1>;
+				fsl,num-rx-queues = <1>;
 				status = "disabled";
 			};
-
 		};
 
 		gpioe: gpio@2d000000 {
-			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
-			reg = <0x2d000080 0x1000 0x2d000040 0x40>;
+			compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+			reg = <0x2d000080 0x1000>, <0x2d000040 0x40>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
@@ -570,8 +787,8 @@
 		};
 
 		gpiof: gpio@2d010000 {
-			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
-			reg = <0x2d010080 0x1000 0x2d010040 0x40>;
+			compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+			reg = <0x2d010080 0x1000>, <0x2d010040 0x40>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
@@ -580,7 +797,7 @@
 			clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
 				 <&pcc4 IMX8ULP_CLK_PCTLF>;
 			clock-names = "gpio", "port";
-			gpio-ranges = <&iomuxc1 0 64 24>;
+			gpio-ranges = <&iomuxc1 0 64 32>;
 		};
 
 		per_bridge5: bus@2d800000 {
@@ -592,6 +809,7 @@
 
 			edma2: dma-controller@2d800000 {
 				compatible = "fsl,imx8ulp-edma";
+				power-domains = <&scmi_devpd IMX8ULP_PD_DMA2>;
 				reg = <0x2d800000 0x10000>,
 				      <0x2d810000 0x10000>, <0x2d820000 0x10000>,
 				      <0x2d830000 0x10000>, <0x2d840000 0x10000>,
@@ -696,6 +914,23 @@
 				status = "okay";
 			};
 
+			avd_sim: syscon@2da50000 {
+				compatible = "nxp,imx8ulp-avd-sim", "syscon", "simple-mfd";
+				reg = <0x2da50000 0x38>;
+				clocks = <&pcc5 IMX8ULP_CLK_AVD_SIM>;
+
+				mux: mux-controller {
+					compatible = "mmio-mux";
+					#mux-control-cells = <1>;
+					mux-reg-masks = <0x8 0x00000200>; /* DSI_DPI2_EPDC_DCNANO_MUX_SEL */
+				};
+
+				avd_sim_rst: reset-controller {
+					compatible = "nxp,imx8ulp-avd-sim-reset";
+					#reset-cells = <1>;
+				};
+			};
+
 			cgc2: clock-controller@2da60000 {
 				compatible = "fsl,imx8ulp-cgc2";
 				reg = <0x2da60000 0x10000>;
@@ -708,12 +943,96 @@
 				compatible = "fsl,imx8ulp-pcc5";
 				reg = <0x2da70000 0x10000>;
 				#clock-cells = <1>;
+				#reset-cells = <1>;
+			};
+
+			dsi: dsi@2db00000 {
+				compatible = "fsl,imx8ulp-nwl-dsi";
+				reg = <0x2db00000 0x300>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>,
+					 <&pcc5 IMX8ULP_CLK_DSI>,
+					 <&pcc5 IMX8ULP_CLK_DSI_TX_ESC>,
+					 <&cgc2 IMX8ULP_CLK_DSI_PHY_REF>;
+				clock-names = "core", "rx_esc", "tx_esc", "phy_ref";
+				power-domains = <&scmi_devpd IMX8ULP_PD_MIPI_DSI>;
+				assigned-clocks = <&pcc5 IMX8ULP_CLK_DSI>;
+				assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD3_DIV2>;
+				assigned-clock-rates = <79200000>;
+				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+				mux-controls = <&mux 0>;
+				csr = <&avd_sim>;
+				phys = <&dphy>;
+				phy-names = "dphy";
+				resets = <&avd_sim_rst IMX8ULP_SIM_RESET_MIPI_DSI_RST_BYTE_N>,
+					 <&avd_sim_rst IMX8ULP_SIM_RESET_MIPI_DSI_RST_DPI_N>,
+					 <&avd_sim_rst IMX8ULP_SIM_RESET_MIPI_DSI_RST_ESC_N>,
+					 <&pcc5 PCC5_DSI_SWRST>;
+				reset-names = "byte", "dpi", "esc", "pclk";
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						#address-cells = <1>;
+						#size-cells = <0>;
+						reg = <0>;
+
+						mipi_dsi_to_dcnano_dpi: endpoint@0 {
+							reg = <0>;
+							remote-endpoint = <&dcnano_dpi_to_mipi_dsi>;
+						};
+					};
+				};
+			};
+
+			dphy: phy@2db00300 {
+				compatible = "fsl,imx8ulp-mipi-dphy";
+				reg = <0x2db00300 0x100>;
+				clocks = <&cgc2 IMX8ULP_CLK_DSI_PHY_REF>;
+				clock-names = "phy_ref";
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+		};
+
+		dcnano: display-controller@2e050000 {
+			compatible = "nxp,imx8ulp-dcnano";
+			reg = <0x2e050000 0x10000>;
+			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cgc2 IMX8ULP_CLK_LPAV_AXI_DIV>,
+				 <&cgc2 IMX8ULP_CLK_LPAV_AHB_DIV>,
+				 <&pcc5 IMX8ULP_CLK_DC_NANO>;
+			clock-names = "axi", "ahb", "pixel";
+			resets = <&pcc5 PCC5_DC_NANO_SWRST>;
+			power-domains = <&scmi_devpd IMX8ULP_PD_DCNANO>;
+			assigned-clocks = <&pcc5 IMX8ULP_CLK_DC_NANO>;
+			assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD0_DIV1>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				dcnano_dpi: port@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0>;
+
+					dcnano_dpi_to_mipi_dsi: endpoint@0 {
+						reg = <0>;
+						remote-endpoint = <&mipi_dsi_to_dcnano_dpi>;
+					};
+				};
 			};
 		};
 
 		gpiod: gpio@2e200000 {
-			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
-			reg = <0x2e200080 0x1000 0x2e200040 0x40>;
+			compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+			reg = <0x2e200080 0x1000>, <0x2e200040 0x40>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
new file mode 100644
index 00000000000..13474a35fca
--- /dev/null
+++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+/ {
+	wdt-reboot {
+		compatible = "wdt-reboot";
+		wdt = <&wdog3>;
+		u-boot,dm-spl;
+	};
+
+	aliases {
+		usbgadget0 = &usbg1;
+		usbgadget1 = &usbg2;
+	};
+
+	usbg1: usbg1 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg1>;
+		status = "okay";
+	};
+
+	usbg2: usbg2 {
+		compatible = "fsl,imx27-usb-gadget";
+		dr_mode = "peripheral";
+		chipidea,usb = <&usbotg2>;
+		status = "okay";
+	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
+};
+
+&{/soc@0} {
+	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
+};
+
+&aips1 {
+	u-boot,dm-spl;
+	u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+	u-boot,dm-spl;
+};
+
+&aips3 {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&reg_usdhc2_vmmc {
+	u-boot,off-on-delay-us = <20000>;
+	u-boot,dm-spl;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+	u-boot,dm-spl;
+};
+
+&pinctrl_uart1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+};
+
+&gpio3 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&lpuart1 {
+	u-boot,dm-spl;
+};
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+	fsl,signal-voltage-switch-extra-delay-ms = <8>;
+};
+
+&lpi2c1 {
+	u-boot,dm-spl;
+};
+
+&lpi2c2 {
+	u-boot,dm-spl;
+};
+
+&lpi2c3 {
+	u-boot,dm-spl;
+};
+
+&{/soc@0/bus@44000000/i2c@44350000/pmic@25} {
+	u-boot,dm-spl;
+};
+
+&{/soc@0/bus@44000000/i2c@44350000/pmic@25/regulators} {
+	u-boot,dm-spl;
+};
+
+&pinctrl_lpi2c1 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_lpi2c2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_lpi2c3 {
+	u-boot,dm-spl;
+};
+
+&fec {
+	phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <15>;
+	phy-reset-post-delay = <100>;
+};
+
+&eqos {
+	compatible = "fsl,imx-eqos";
+};
+
+&ethphy1 {
+	reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
+	reset-assert-us = <15000>;
+	reset-deassert-us = <100000>;
+};
+
+&usbotg1 {
+	status = "okay";
+	extcon = <&ptn5110>;
+};
+
+&usbotg2 {
+	status = "okay";
+	extcon = <&ptn5110_2>;
+};
+
+&s4muap {
+	u-boot,dm-spl;
+	status = "okay";
+};
+
+&clk {
+	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
+	/delete-property/ assigned-clocks;
+	/delete-property/ assigned-clock-rates;
+};
+
+&osc_32k {
+	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
+};
+
+&osc_24m {
+	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
+};
+
+&clk_ext1 {
+	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
+};
+
+&lcdif {
+	assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>, <&clk IMX93_CLK_MEDIA_APB>;
+	assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+	assigned-clock-rates = <400000000>, <133333334>;
+};
diff --git a/arch/arm/dts/imx93-11x11-evk.dts b/arch/arm/dts/imx93-11x11-evk.dts
new file mode 100644
index 00000000000..38bf2aeb99a
--- /dev/null
+++ b/arch/arm/dts/imx93-11x11-evk.dts
@@ -0,0 +1,624 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+/dts-v1/;
+
+#include "imx93.dtsi"
+
+/{
+	model = "NXP i.MX93 11X11 EVK board";
+	compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
+
+	chosen {
+		stdout-path = &lpuart1;
+	};
+
+	aliases {
+		i2c8 = &flexio_i2c_master;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		audio: audio@a4120000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0xa4120000 0 0x100000>;
+			no-map;
+		};
+	};
+
+	reg_can2_stby: regulator-can2-stby {
+		compatible = "regulator-fixed";
+		regulator-name = "can2-stby";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&adp5585gpio 5 GPIO_ACTIVE_LOW>;
+		enable-active-low;
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	usdhc3_pwrseq: usdhc3_pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&pcal6524 20 GPIO_ACTIVE_LOW>;
+	};
+
+	reg_vref_1v8: regulator-adc-vref {
+		compatible = "regulator-fixed";
+		regulator-name = "vref_1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	dsi_host: dsi-host {
+		compatible = "synopsys,dw-mipi-dsi";
+		status = "okay";
+	};
+
+	rm67199_panel {
+		compatible = "raydium,rm67199";
+		reset-gpio = <&adp5585gpio 6 GPIO_ACTIVE_LOW>;
+		dsi-lanes = <4>;
+		video-mode = <2>;	/* 0: burst mode
+					 * 1: non-burst mode with sync event
+					 * 2: non-burst mode with sync pulse
+					 */
+		width-mm = <68>;
+		height-mm = <121>;
+		status = "okay";
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&dsi_out>;
+			};
+		};
+	};
+};
+
+&dphy {
+	status = "okay";
+};
+
+&dsi {
+	status = "okay";
+
+	ports {
+		port@1 {
+			dsi_to_adv7535: endpoint {
+				remote-endpoint = <&adv7535_to_dsi>;
+			};
+		};
+
+		port@2 {
+			dsi_out: endpoint {
+				remote-endpoint = <&panel_in>;
+			};
+		};
+	};
+};
+
+&lcdif {
+	status = "okay";
+	assigned-clock-rates = <484000000>, <121000000>, <400000000>, <133333333>;
+};
+
+&lpi2c1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_lpi2c1>;
+	pinctrl-1 = <&pinctrl_lpi2c1>;
+	status = "okay";
+
+	adv7535: hdmi@3d {
+		compatible = "adi,adv7535";
+		reg = <0x3d>;
+		adi,addr-cec = <0x3c>;
+		adi,dsi-lanes = <4>;
+		status = "okay";
+
+		port {
+			adv7535_to_dsi: endpoint {
+				remote-endpoint = <&dsi_to_adv7535>;
+			};
+		};
+	};
+};
+
+&lpi2c2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_lpi2c2>;
+	pinctrl-1 = <&pinctrl_lpi2c2>;
+	status = "okay";
+
+	pmic@25 {
+		compatible = "nxp,pca9451a";
+		reg = <0x25>;
+		pinctrl-names = "default";
+		interrupt-parent = <&pcal6524>;
+		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+
+		regulators {
+			buck1: BUCK1 {
+				regulator-name = "BUCK1";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck2: BUCK2 {
+				regulator-name = "BUCK2";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck4: BUCK4{
+				regulator-name = "BUCK4";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5: BUCK5{
+				regulator-name = "BUCK5";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6: BUCK6 {
+				regulator-name = "BUCK6";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1: LDO1 {
+				regulator-name = "LDO1";
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo2: LDO2 {
+				regulator-name = "LDO2";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1150000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo3: LDO3 {
+				regulator-name = "LDO3";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4: LDO4 {
+				regulator-name = "LDO4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5: LDO5 {
+				regulator-name = "LDO5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+
+	pcal6524: gpio@22 {
+		compatible = "nxp,pcal6524";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pcal6524>;
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	adp5585gpio: gpio@34 {
+		compatible = "adp5585";
+		reg = <0x34>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&lpi2c3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_lpi2c3>;
+	pinctrl-1 = <&pinctrl_lpi2c3>;
+	status = "okay";
+
+	ptn5110: tcpc@50 {
+		compatible = "nxp,ptn5110";
+		reg = <0x50>;
+		interrupt-parent = <&pcal6524>;
+		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+		status = "okay";
+
+		port {
+			typec1_dr_sw: endpoint {
+				remote-endpoint = <&usb1_drd_sw>;
+			};
+		};
+
+		typec1_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			power-role = "dual";
+			data-role = "dual";
+			try-power-role = "sink";
+			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+				     PDO_VAR(5000, 20000, 3000)>;
+			op-sink-microwatt = <15000000>;
+			self-powered;
+		};
+	};
+
+	ptn5110_2: tcpc@51 {
+		compatible = "nxp,ptn5110";
+		reg = <0x51>;
+		interrupt-parent = <&pcal6524>;
+		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+		status = "okay";
+
+		port {
+			typec2_dr_sw: endpoint {
+				remote-endpoint = <&usb2_drd_sw>;
+			};
+		};
+
+		typec2_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			power-role = "dual";
+			data-role = "dual";
+			try-power-role = "sink";
+			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+				     PDO_VAR(5000, 20000, 3000)>;
+			op-sink-microwatt = <15000000>;
+			self-powered;
+		};
+	};
+};
+
+&lpuart1 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>;
+	clock-names = "ipg", "per";
+	status = "okay";
+};
+
+&lpuart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "disabled";
+};
+
+&usbotg1 {
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	usb-role-switch;
+	disable-over-current;
+	samsung,picophy-pre-emp-curr-control = <3>;
+	samsung,picophy-dc-vol-level-adjust = <7>;
+	status = "okay";
+
+	port {
+		usb1_drd_sw: endpoint {
+			remote-endpoint = <&typec1_dr_sw>;
+		};
+	};
+};
+
+&usbotg2 {
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	usb-role-switch;
+	disable-over-current;
+	samsung,picophy-pre-emp-curr-control = <3>;
+	samsung,picophy-dc-vol-level-adjust = <7>;
+	status = "okay";
+
+	port {
+		usb2_drd_sw: endpoint {
+			remote-endpoint = <&typec2_dr_sw>;
+		};
+	};
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1>;
+	pinctrl-2 = <&pinctrl_usdhc1>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	bus-width = <4>;
+	status = "okay";
+	no-sdio;
+	no-mmc;
+};
+
+&usdhc3 {
+	status = "disabled";
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy2>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-frequency = <5000000>;
+
+		ethphy2: ethernet-phy@2 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <2>;
+			eee-broken-1000t;
+			rtl821x,aldps-disable;
+			rtl821x,clkout-disable;
+		};
+	};
+};
+
+&eqos {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_eqos>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy1>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-frequency = <5000000>;
+
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			eee-broken-1000t;
+			rtl821x,aldps-disable;
+			rtl821x,clkout-disable;
+		};
+	};
+};
+
+&flexcan2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan2>;
+	xceiver-supply = <&reg_can2_stby>;
+	status = "okay";
+};
+
+&flexspi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexspi>;
+	status = "disabled";
+
+	flash0: flash@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <80000000>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	status = "okay";
+
+	pinctrl_flexcan2: flexcan2grp {
+		fsl,pins = <
+			MX93_PAD_GPIO_IO25__CAN2_TX	0x139e
+			MX93_PAD_GPIO_IO27__CAN2_RX	0x139e
+		>;
+	};
+
+	pinctrl_flexspi: flexspigrp {
+		fsl,pins = <
+			MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B	0x42
+			MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B	0x42
+			MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK	0x42
+			MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS	0x42
+			MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00	0x42
+			MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01	0x42
+			MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02	0x42
+			MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03	0x42
+			MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04	0x42
+			MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05	0x42
+			MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06	0x42
+			MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07	0x42
+		>;
+	};
+
+	pinctrl_fec: fecgrp {
+		fsl,pins = <
+			MX93_PAD_ENET2_MDC__ENET1_MDC			0x57e
+			MX93_PAD_ENET2_MDIO__ENET1_MDIO			0x57e
+			MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		0x57e
+			MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		0x57e
+			MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2		0x57e
+			MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3		0x57e
+			MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC		0x5fe
+			MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	0x57e
+			MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0		0x57e
+			MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1		0x57e
+			MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2		0x57e
+			MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3		0x57e
+			MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC		0x5fe
+			MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL	0x57e
+		>;
+	};
+
+	pinctrl_eqos: eqosgrp {
+		fsl,pins = <
+			MX93_PAD_ENET1_MDC__ENET_QOS_MDC			0x57e
+			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x57e
+			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x57e
+			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x57e
+			MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x57e
+			MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x57e
+			MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x5fe
+			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x57e
+			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x57e
+			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1			0x57e
+			MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x57e
+			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x57e
+			MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x5fe
+			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x57e
+		>;
+	};
+
+	pinctrl_lpi2c1: lpi2c1grp {
+		fsl,pins = <
+			MX93_PAD_I2C1_SCL__LPI2C1_SCL			0x40000b9e
+			MX93_PAD_I2C1_SDA__LPI2C1_SDA			0x40000b9e
+		>;
+	};
+
+	pinctrl_lpi2c2: lpi2c2grp {
+		fsl,pins = <
+			MX93_PAD_I2C2_SCL__LPI2C2_SCL			0x40000b9e
+			MX93_PAD_I2C2_SDA__LPI2C2_SDA			0x40000b9e
+		>;
+	};
+
+	pinctrl_lpi2c3: lpi2c3grp {
+		fsl,pins = <
+			MX93_PAD_GPIO_IO28__LPI2C3_SDA			0x40000b9e
+			MX93_PAD_GPIO_IO29__LPI2C3_SCL			0x40000b9e
+		>;
+	};
+
+	pinctrl_pcal6524: pcal6524grp {
+		fsl,pins = <
+			MX93_PAD_CCM_CLKO2__GPIO3_IO27			0x31e
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX93_PAD_UART1_RXD__LPUART1_RX			0x31e
+			MX93_PAD_UART1_TXD__LPUART1_TX			0x31e
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX93_PAD_UART2_TXD__LPUART2_TX			0x31e
+			MX93_PAD_UART2_RXD__LPUART2_RX			0x31e
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX93_PAD_SD1_CLK__USDHC1_CLK			0x17fe
+			MX93_PAD_SD1_CMD__USDHC1_CMD			0x13fe
+			MX93_PAD_SD1_DATA0__USDHC1_DATA0		0x13fe
+			MX93_PAD_SD1_DATA1__USDHC1_DATA1        	0x13fe
+			MX93_PAD_SD1_DATA2__USDHC1_DATA2        	0x13fe
+			MX93_PAD_SD1_DATA3__USDHC1_DATA3        	0x13fe
+			MX93_PAD_SD1_DATA4__USDHC1_DATA4        	0x13fe
+			MX93_PAD_SD1_DATA5__USDHC1_DATA5        	0x13fe
+			MX93_PAD_SD1_DATA6__USDHC1_DATA6        	0x13fe
+			MX93_PAD_SD1_DATA7__USDHC1_DATA7        	0x13fe
+			MX93_PAD_SD1_STROBE__USDHC1_STROBE		0x17fe
+		>;
+	};
+
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+		fsl,pins = <
+			MX93_PAD_SD2_RESET_B__GPIO3_IO07		0x31e
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			MX93_PAD_SD2_CD_B__GPIO3_IO00			0x31e
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX93_PAD_SD2_CLK__USDHC2_CLK			0x17fe
+			MX93_PAD_SD2_CMD__USDHC2_CMD			0x13fe
+			MX93_PAD_SD2_DATA0__USDHC2_DATA0		0x13fe
+			MX93_PAD_SD2_DATA1__USDHC2_DATA1        	0x13fe
+			MX93_PAD_SD2_DATA2__USDHC2_DATA2        	0x13fe
+			MX93_PAD_SD2_DATA3__USDHC2_DATA3        	0x13fe
+			MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e
+		>;
+	};
+};
+
+&wdog3 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx93-pinfunc.h b/arch/arm/dts/imx93-pinfunc.h
new file mode 100644
index 00000000000..4298a145f8a
--- /dev/null
+++ b/arch/arm/dts/imx93-pinfunc.h
@@ -0,0 +1,623 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __DTS_IMX93_PINFUNC_H
+#define __DTS_IMX93_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI                            0x0000 0x01B0 0x03D8 0x0 0x0
+#define MX93_PAD_DAP_TDI__MQS2_LEFT                               0x0000 0x01B0 0x0000 0x1 0x0
+#define MX93_PAD_DAP_TDI__CAN2_TX                                 0x0000 0x01B0 0x0000 0x3 0x0
+#define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30                        0x0000 0x01B0 0x0000 0x4 0x0
+#define MX93_PAD_DAP_TDI__GPIO3_IO28                              0x0000 0x01B0 0x0000 0x5 0x0
+#define MX93_PAD_DAP_TDI__LPUART5_RX                              0x0000 0x01B0 0x0430 0x6 0x0
+#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS                      0x0004 0x01B4 0x03DC 0x0 0x0
+#define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31                  0x0004 0x01B4 0x0000 0x4 0x0
+#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29                        0x0004 0x01B4 0x0000 0x5 0x0
+#define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B                     0x0004 0x01B4 0x0000 0x6 0x0
+#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK                     0x0008 0x01B8 0x03D4 0x0 0x0
+#define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30                 0x0008 0x01B8 0x0000 0x4 0x0
+#define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30                       0x0008 0x01B8 0x0000 0x5 0x0
+#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B                    0x0008 0x01B8 0x042C 0x6 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO                   0x000C 0x01BC 0x0000 0x0 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT                     0x000C 0x01BC 0x0000 0x1 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX                        0x000C 0x01BC 0x0364 0x3 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31               0x000C 0x01BC 0x0000 0x4 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31                     0x000C 0x01BC 0x0000 0x5 0x0
+#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX                     0x000C 0x01BC 0x0434 0x6 0x0
+#define MX93_PAD_GPIO_IO00__GPIO2_IO00                            0x0010 0x01C0 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO00__LPI2C3_SDA                            0x0010 0x01C0 0x03E4 0x11 0x0
+#define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK                      0x0010 0x01C0 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK                     0x0010 0x01C0 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO00__LPSPI6_PCS0                           0x0010 0x01C0 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO00__LPUART5_TX                            0x0010 0x01C0 0x0434 0x5 0x1
+#define MX93_PAD_GPIO_IO00__LPI2C5_SDA                            0x0010 0x01C0 0x03EC 0x16 0x0
+#define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00                      0x0010 0x01C0 0x036C 0x7 0x0
+#define MX93_PAD_GPIO_IO01__GPIO2_IO01                            0x0014 0x01C4 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO01__LPI2C3_SCL                            0x0014 0x01C4 0x03E0 0x11 0x0
+#define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00                   0x0014 0x01C4 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE                      0x0014 0x01C4 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO01__LPSPI6_SIN                            0x0014 0x01C4 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO01__LPUART5_RX                            0x0014 0x01C4 0x0430 0x5 0x1
+#define MX93_PAD_GPIO_IO01__LPI2C5_SCL                            0x0014 0x01C4 0x03E8 0x16 0x0
+#define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01                      0x0014 0x01C4 0x0370 0x7 0x0
+#define MX93_PAD_GPIO_IO02__GPIO2_IO02                            0x0018 0x01C8 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO02__LPI2C4_SDA                            0x0018 0x01C8 0x0000 0x11 0x0
+#define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC                    0x0018 0x01C8 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC                   0x0018 0x01C8 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO02__LPSPI6_SOUT                           0x0018 0x01C8 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B                         0x0018 0x01C8 0x042C 0x5 0x1
+#define MX93_PAD_GPIO_IO02__LPI2C6_SDA                            0x0018 0x01C8 0x03F4 0x16 0x0
+#define MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02                      0x0018 0x01C8 0x0374 0x7 0x0
+#define MX93_PAD_GPIO_IO03__GPIO2_IO03                            0x001C 0x01CC 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO03__LPI2C4_SCL                            0x001C 0x01CC 0x0000 0x11 0x0
+#define MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC                    0x001C 0x01CC 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC                   0x001C 0x01CC 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO03__LPSPI6_SCK                            0x001C 0x01CC 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO03__LPUART5_RTS_B                         0x001C 0x01CC 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO03__LPI2C6_SCL                            0x001C 0x01CC 0x03F0 0x16 0x0
+#define MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03                      0x001C 0x01CC 0x0378 0x7 0x0
+#define MX93_PAD_GPIO_IO04__GPIO2_IO04                            0x0020 0x01D0 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO04__TPM3_CH0                              0x0020 0x01D0 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO04__PDM_CLK                               0x0020 0x01D0 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00                  0x0020 0x01D0 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO04__LPSPI7_PCS0                           0x0020 0x01D0 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO04__LPUART6_TX                            0x0020 0x01D0 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO04__LPI2C6_SDA                            0x0020 0x01D0 0x03F4 0x16 0x1
+#define MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04                      0x0020 0x01D0 0x037C 0x7 0x0
+#define MX93_PAD_GPIO_IO05__GPIO2_IO05                            0x0024 0x01D4 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO05__TPM4_CH0                              0x0024 0x01D4 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00                      0x0024 0x01D4 0x0438 0x2 0x0
+#define MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01                  0x0024 0x01D4 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO05__LPSPI7_SIN                            0x0024 0x01D4 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO05__LPUART6_RX                            0x0024 0x01D4 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO05__LPI2C6_SCL                            0x0024 0x01D4 0x03F0 0x16 0x1
+#define MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05                      0x0024 0x01D4 0x0380 0x7 0x0
+#define MX93_PAD_GPIO_IO06__GPIO2_IO06                            0x0028 0x01D8 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO06__TPM5_CH0                              0x0028 0x01D8 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01                      0x0028 0x01D8 0x043C 0x2 0x0
+#define MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02                  0x0028 0x01D8 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO06__LPSPI7_SOUT                           0x0028 0x01D8 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO06__LPUART6_CTS_B                         0x0028 0x01D8 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO06__LPI2C7_SDA                            0x0028 0x01D8 0x03FC 0x16 0x0
+#define MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06                      0x0028 0x01D8 0x0384 0x7 0x0
+#define MX93_PAD_GPIO_IO07__GPIO2_IO07                            0x002C 0x01DC 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO07__LPSPI3_PCS1                           0x002C 0x01DC 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01                   0x002C 0x01DC 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03                  0x002C 0x01DC 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO07__LPSPI7_SCK                            0x002C 0x01DC 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO07__LPUART6_RTS_B                         0x002C 0x01DC 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO07__LPI2C7_SCL                            0x002C 0x01DC 0x03F8 0x16 0x0
+#define MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07                      0x002C 0x01DC 0x0388 0x7 0x0
+#define MX93_PAD_GPIO_IO08__GPIO2_IO08                            0x0030 0x01E0 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO08__LPSPI3_PCS0                           0x0030 0x01E0 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02                   0x0030 0x01E0 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04                  0x0030 0x01E0 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO08__TPM6_CH0                              0x0030 0x01E0 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO08__LPUART7_TX                            0x0030 0x01E0 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO08__LPI2C7_SDA                            0x0030 0x01E0 0x03FC 0x16 0x1
+#define MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08                      0x0030 0x01E0 0x038C 0x7 0x0
+#define MX93_PAD_GPIO_IO09__GPIO2_IO09                            0x0034 0x01E4 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO09__LPSPI3_SIN                            0x0034 0x01E4 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03                   0x0034 0x01E4 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05                  0x0034 0x01E4 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO09__TPM3_EXTCLK                           0x0034 0x01E4 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO09__LPUART7_RX                            0x0034 0x01E4 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO09__LPI2C7_SCL                            0x0034 0x01E4 0x03F8 0x16 0x1
+#define MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09                      0x0034 0x01E4 0x0390 0x7 0x0
+#define MX93_PAD_GPIO_IO10__GPIO2_IO10                            0x0038 0x01E8 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO10__LPSPI3_SOUT                           0x0038 0x01E8 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04                   0x0038 0x01E8 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06                  0x0038 0x01E8 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO10__TPM4_EXTCLK                           0x0038 0x01E8 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO10__LPUART7_CTS_B                         0x0038 0x01E8 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO10__LPI2C8_SDA                            0x0038 0x01E8 0x0404 0x16 0x0
+#define MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10                      0x0038 0x01E8 0x0394 0x7 0x0
+#define MX93_PAD_GPIO_IO11__GPIO2_IO11                            0x003C 0x01EC 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO11__LPSPI3_SCK                            0x003C 0x01EC 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05                   0x003C 0x01EC 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07                  0x003C 0x01EC 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO11__TPM5_EXTCLK                           0x003C 0x01EC 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO11__LPUART7_RTS_B                         0x003C 0x01EC 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO11__LPI2C8_SCL                            0x003C 0x01EC 0x0400 0x16 0x0
+#define MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11                      0x003C 0x01EC 0x0398 0x7 0x0
+#define MX93_PAD_GPIO_IO12__GPIO2_IO12                            0x0040 0x01F0 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO12__TPM3_CH2                              0x0040 0x01F0 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02                      0x0040 0x01F0 0x0440 0x2 0x0
+#define MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08                  0x0040 0x01F0 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO12__LPSPI8_PCS0                           0x0040 0x01F0 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO12__LPUART8_TX                            0x0040 0x01F0 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO12__LPI2C8_SDA                            0x0040 0x01F0 0x0404 0x16 0x1
+#define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC                          0x0040 0x01F0 0x0450 0x7 0x0
+#define MX93_PAD_GPIO_IO13__GPIO2_IO13                            0x0044 0x01F4 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO13__TPM4_CH2                              0x0044 0x01F4 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03                      0x0044 0x01F4 0x0444 0x2 0x0
+#define MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09                  0x0044 0x01F4 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO13__LPSPI8_SIN                            0x0044 0x01F4 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO13__LPUART8_RX                            0x0044 0x01F4 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO13__LPI2C8_SCL                            0x0044 0x01F4 0x0400 0x16 0x1
+#define MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13                      0x0044 0x01F4 0x039C 0x7 0x0
+#define MX93_PAD_GPIO_IO14__GPIO2_IO14                            0x0048 0x01F8 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO14__LPUART3_TX                            0x0048 0x01F8 0x041C 0x1 0x0
+#define MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06                   0x0048 0x01F8 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10                  0x0048 0x01F8 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO14__LPSPI8_SOUT                           0x0048 0x01F8 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO14__LPUART8_CTS_B                         0x0048 0x01F8 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO14__LPUART4_TX                            0x0048 0x01F8 0x0428 0x6 0x0
+#define MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14                      0x0048 0x01F8 0x03A0 0x7 0x0
+#define MX93_PAD_GPIO_IO15__GPIO2_IO15                            0x004C 0x01FC 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO15__LPUART3_RX                            0x004C 0x01FC 0x0418 0x1 0x0
+#define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07                   0x004C 0x01FC 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11                  0x004C 0x01FC 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO15__LPSPI8_SCK                            0x004C 0x01FC 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO15__LPUART8_RTS_B                         0x004C 0x01FC 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO15__LPUART4_RX                            0x004C 0x01FC 0x0424 0x6 0x0
+#define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15                      0x004C 0x01FC 0x03A4 0x7 0x0
+#define MX93_PAD_GPIO_IO16__GPIO2_IO16                            0x0050 0x0200 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO16__SAI3_TX_BCLK                          0x0050 0x0200 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02                      0x0050 0x0200 0x0440 0x2 0x1
+#define MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12                  0x0050 0x0200 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO16__LPUART3_CTS_B                         0x0050 0x0200 0x0414 0x4 0x0
+#define MX93_PAD_GPIO_IO16__LPSPI4_PCS2                           0x0050 0x0200 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO16__LPUART4_CTS_B                         0x0050 0x0200 0x0420 0x6 0x0
+#define MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16                      0x0050 0x0200 0x03A8 0x7 0x0
+#define MX93_PAD_GPIO_IO17__GPIO2_IO17                            0x0054 0x0204 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO17__SAI3_MCLK                             0x0054 0x0204 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08                   0x0054 0x0204 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13                  0x0054 0x0204 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO17__LPUART3_RTS_B                         0x0054 0x0204 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO17__LPSPI4_PCS1                           0x0054 0x0204 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO17__LPUART4_RTS_B                         0x0054 0x0204 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17                      0x0054 0x0204 0x03AC 0x7 0x0
+#define MX93_PAD_GPIO_IO18__GPIO2_IO18                            0x0058 0x0208 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK                          0x0058 0x0208 0x044C 0x1 0x0
+#define MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09                   0x0058 0x0208 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14                  0x0058 0x0208 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO18__LPSPI5_PCS0                           0x0058 0x0208 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO18__LPSPI4_PCS0                           0x0058 0x0208 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO18__TPM5_CH2                              0x0058 0x0208 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18                      0x0058 0x0208 0x03B0 0x7 0x0
+#define MX93_PAD_GPIO_IO19__GPIO2_IO19                            0x005C 0x020C 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC                          0x005C 0x020C 0x0450 0x1 0x1
+#define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03                      0x005C 0x020C 0x0444 0x2 0x1
+#define MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15                  0x005C 0x020C 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO19__LPSPI5_SIN                            0x005C 0x020C 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO19__LPSPI4_SIN                            0x005C 0x020C 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO19__TPM6_CH2                              0x005C 0x020C 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO19__SAI3_TX_DATA00                        0x005C 0x020C 0x0000 0x7 0x0
+#define MX93_PAD_GPIO_IO20__GPIO2_IO20                            0x0060 0x0210 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO20__SAI3_RX_DATA00                        0x0060 0x0210 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00                      0x0060 0x0210 0x0438 0x2 0x1
+#define MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16                  0x0060 0x0210 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO20__LPSPI5_SOUT                           0x0060 0x0210 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO20__LPSPI4_SOUT                           0x0060 0x0210 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO20__TPM3_CH1                              0x0060 0x0210 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20                      0x0060 0x0210 0x03B4 0x7 0x0
+#define MX93_PAD_GPIO_IO21__GPIO2_IO21                            0x0064 0x0214 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO21__SAI3_TX_DATA00                        0x0064 0x0214 0x0000 0x1 0x0
+#define MX93_PAD_GPIO_IO21__PDM_CLK                               0x0064 0x0214 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17                  0x0064 0x0214 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO21__LPSPI5_SCK                            0x0064 0x0214 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO21__LPSPI4_SCK                            0x0064 0x0214 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO21__TPM4_CH1                              0x0064 0x0214 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK                          0x0064 0x0214 0x044C 0x7 0x1
+#define MX93_PAD_GPIO_IO22__GPIO2_IO22                            0x0068 0x0218 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO22__USDHC3_CLK                            0x0068 0x0218 0x0458 0x1 0x0
+#define MX93_PAD_GPIO_IO22__SPDIF_IN                              0x0068 0x0218 0x0454 0x2 0x0
+#define MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18                  0x0068 0x0218 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO22__TPM5_CH1                              0x0068 0x0218 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO22__TPM6_EXTCLK                           0x0068 0x0218 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO22__LPI2C5_SDA                            0x0068 0x0218 0x03EC 0x16 0x1
+#define MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22                      0x0068 0x0218 0x03B8 0x7 0x0
+#define MX93_PAD_GPIO_IO23__GPIO2_IO23                            0x006C 0x021C 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO23__USDHC3_CMD                            0x006C 0x021C 0x045C 0x1 0x0
+#define MX93_PAD_GPIO_IO23__SPDIF_OUT                             0x006C 0x021C 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19                  0x006C 0x021C 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO23__TPM6_CH1                              0x006C 0x021C 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO23__LPI2C5_SCL                            0x006C 0x021C 0x03E8 0x16 0x1
+#define MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23                      0x006C 0x021C 0x03BC 0x7 0x0
+#define MX93_PAD_GPIO_IO24__GPIO2_IO24                            0x0070 0x0220 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO24__USDHC3_DATA0                          0x0070 0x0220 0x0460 0x1 0x0
+#define MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20                  0x0070 0x0220 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO24__TPM3_CH3                              0x0070 0x0220 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO24__JTAG_MUX_TDO                          0x0070 0x0220 0x0000 0x5 0x0
+#define MX93_PAD_GPIO_IO24__LPSPI6_PCS1                           0x0070 0x0220 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24                      0x0070 0x0220 0x03C0 0x7 0x0
+#define MX93_PAD_GPIO_IO25__GPIO2_IO25                            0x0074 0x0224 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO25__USDHC3_DATA1                          0x0074 0x0224 0x0464 0x1 0x0
+#define MX93_PAD_GPIO_IO25__CAN2_TX                               0x0074 0x0224 0x0000 0x2 0x0
+#define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21                  0x0074 0x0224 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO25__TPM4_CH3                              0x0074 0x0224 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK                          0x0074 0x0224 0x03D4 0x5 0x1
+#define MX93_PAD_GPIO_IO25__LPSPI7_PCS1                           0x0074 0x0224 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25                      0x0074 0x0224 0x03C4 0x7 0x0
+#define MX93_PAD_GPIO_IO26__GPIO2_IO26                            0x0078 0x0228 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO26__USDHC3_DATA2                          0x0078 0x0228 0x0468 0x1 0x0
+#define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01                      0x0078 0x0228 0x043C 0x2 0x1
+#define MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22                  0x0078 0x0228 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO26__TPM5_CH3                              0x0078 0x0228 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI                          0x0078 0x0228 0x03D8 0x5 0x1
+#define MX93_PAD_GPIO_IO26__LPSPI8_PCS1                           0x0078 0x0228 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO26__SAI3_TX_SYNC                          0x0078 0x0228 0x0000 0x7 0x0
+#define MX93_PAD_GPIO_IO27__GPIO2_IO27                            0x007C 0x022C 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO27__USDHC3_DATA3                          0x007C 0x022C 0x046C 0x1 0x0
+#define MX93_PAD_GPIO_IO27__CAN2_RX                               0x007C 0x022C 0x0364 0x2 0x1
+#define MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23                  0x007C 0x022C 0x0000 0x3 0x0
+#define MX93_PAD_GPIO_IO27__TPM6_CH3                              0x007C 0x022C 0x0000 0x4 0x0
+#define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS                          0x007C 0x022C 0x03DC 0x5 0x1
+#define MX93_PAD_GPIO_IO27__LPSPI5_PCS1                           0x007C 0x022C 0x0000 0x6 0x0
+#define MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27                      0x007C 0x022C 0x03C8 0x7 0x0
+#define MX93_PAD_GPIO_IO28__GPIO2_IO28                            0x0080 0x0230 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO28__LPI2C3_SDA                            0x0080 0x0230 0x03E4 0x11 0x1
+#define MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28                      0x0080 0x0230 0x0000 0x7 0x0
+#define MX93_PAD_GPIO_IO29__GPIO2_IO29                            0x0084 0x0234 0x0000 0x0 0x0
+#define MX93_PAD_GPIO_IO29__LPI2C3_SCL                            0x0084 0x0234 0x03E0 0x11 0x1
+#define MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29                      0x0084 0x0234 0x0000 0x7 0x0
+#define MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1                    0x0088 0x0238 0x0000 0x0 0x0
+#define MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26                      0x0088 0x0238 0x0000 0x4 0x0
+#define MX93_PAD_CCM_CLKO1__GPIO3_IO26                            0x0088 0x0238 0x0000 0x5 0x0
+#define MX93_PAD_CCM_CLKO2__GPIO3_IO27                            0x008C 0x023C 0x0000 0x5 0x0
+#define MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2                    0x008C 0x023C 0x0000 0x0 0x0
+#define MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27                      0x008C 0x023C 0x03C8 0x4 0x1
+#define MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3                    0x0090 0x0240 0x0000 0x0 0x0
+#define MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28                      0x0090 0x0240 0x0000 0x4 0x0
+#define MX93_PAD_CCM_CLKO3__GPIO4_IO28                            0x0090 0x0240 0x0000 0x5 0x0
+#define MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4                    0x0094 0x0244 0x0000 0x0 0x0
+#define MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29                      0x0094 0x0244 0x0000 0x4 0x0
+#define MX93_PAD_CCM_CLKO4__GPIO4_IO29                            0x0094 0x0244 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_MDC__ENET_QOS_MDC                          0x0098 0x0248 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_MDC__LPUART3_DCB_B                         0x0098 0x0248 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_MDC__I3C2_SCL                              0x0098 0x0248 0x03CC 0x2 0x0
+#define MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1                       0x0098 0x0248 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00                      0x0098 0x0248 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_MDC__GPIO4_IO00                            0x0098 0x0248 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO                        0x009C 0x024C 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_MDIO__LPUART3_RIN_B                        0x009C 0x024C 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_MDIO__I3C2_SDA                             0x009C 0x024C 0x03D0 0x2 0x0
+#define MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1                     0x009C 0x024C 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01                     0x009C 0x024C 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_MDIO__GPIO4_IO01                           0x009C 0x024C 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3                    0x00A0 0x0250 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TD3__CAN2_TX                               0x00A0 0x0250 0x0000 0x2 0x0
+#define MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2                       0x00A0 0x0250 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02                      0x00A0 0x0250 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TD3__GPIO4_IO02                            0x00A0 0x0250 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2                    0x00A4 0x0254 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK   0x00A4 0x0254 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_TD2__CAN2_RX                               0x00A4 0x0254 0x0364 0x2 0x2
+#define MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2                       0x00A4 0x0254 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03                      0x00A4 0x0254 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TD2__GPIO4_IO03                            0x00A4 0x0254 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1                    0x00A8 0x0258 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TD1__LPUART3_RTS_B                         0x00A8 0x0258 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_TD1__I3C2_PUR                              0x00A8 0x0258 0x0000 0x2 0x0
+#define MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1                       0x00A8 0x0258 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04                      0x00A8 0x0258 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TD1__GPIO4_IO04                            0x00A8 0x0258 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TD1__I3C2_PUR_B                            0x00A8 0x0258 0x0000 0x6 0x0
+#define MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0                    0x00AC 0x025C 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TD0__LPUART3_TX                            0x00AC 0x025C 0x041C 0x1 0x1
+#define MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05                      0x00AC 0x025C 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TD0__GPIO4_IO05                            0x00AC 0x025C 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL              0x00B0 0x0260 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B                      0x00B0 0x0260 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06                   0x00B0 0x0260 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TX_CTL__GPIO4_IO06                         0x00B0 0x0260 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK    0x00B4 0x0264 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER                        0x00B4 0x0264 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07                      0x00B4 0x0264 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_TXC__GPIO4_IO07                            0x00B4 0x0264 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL              0x00B8 0x0268 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B                      0x00B8 0x0268 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2                   0x00B8 0x0268 0x0000 0x3 0x0
+#define MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08                   0x00B8 0x0268 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RX_CTL__GPIO4_IO08                         0x00B8 0x0268 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK    0x00BC 0x026C 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER                        0x00BC 0x026C 0x0000 0x1 0x0
+#define MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09                      0x00BC 0x026C 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RXC__GPIO4_IO09                            0x00BC 0x026C 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0                    0x00C0 0x0270 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RD0__LPUART3_RX                            0x00C0 0x0270 0x0418 0x1 0x1
+#define MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10                      0x00C0 0x0270 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RD0__GPIO4_IO10                            0x00C0 0x0270 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1                    0x00C4 0x0274 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RD1__LPUART3_CTS_B                         0x00C4 0x0274 0x0414 0x1 0x1
+#define MX93_PAD_ENET1_RD1__LPTMR2_ALT1                           0x00C4 0x0274 0x0408 0x3 0x0
+#define MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11                      0x00C4 0x0274 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RD1__GPIO4_IO11                            0x00C4 0x0274 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2                    0x00C8 0x0278 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RD2__LPTMR2_ALT2                           0x00C8 0x0278 0x040C 0x3 0x0
+#define MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12                      0x00C8 0x0278 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RD2__GPIO4_IO12                            0x00C8 0x0278 0x0000 0x5 0x0
+#define MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3                    0x00CC 0x027C 0x0000 0x0 0x0
+#define MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER               0x00CC 0x027C 0x0000 0x2 0x0
+#define MX93_PAD_ENET1_RD3__LPTMR2_ALT3                           0x00CC 0x027C 0x0410 0x3 0x0
+#define MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13                      0x00CC 0x027C 0x0000 0x4 0x0
+#define MX93_PAD_ENET1_RD3__GPIO4_IO13                            0x00CC 0x027C 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_MDC__ENET1_MDC                             0x00D0 0x0280 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_MDC__LPUART4_DCB_B                         0x00D0 0x0280 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_MDC__SAI2_RX_SYNC                          0x00D0 0x0280 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14                      0x00D0 0x0280 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_MDC__GPIO4_IO14                            0x00D0 0x0280 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_MDIO__ENET1_MDIO                           0x00D4 0x0284 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_MDIO__LPUART4_RIN_B                        0x00D4 0x0284 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK                         0x00D4 0x0284 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15                     0x00D4 0x0284 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_MDIO__GPIO4_IO15                           0x00D4 0x0284 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TD3__SAI2_RX_DATA00                        0x00D8 0x0288 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16                      0x00D8 0x0288 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TD3__GPIO4_IO16                            0x00D8 0x0288 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3                       0x00D8 0x0288 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2                       0x00DC 0x028C 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TD2__ENET1_TX_CLK                          0x00DC 0x028C 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_TD2__SAI2_RX_DATA01                        0x00DC 0x028C 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17                      0x00DC 0x028C 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TD2__GPIO4_IO17                            0x00DC 0x028C 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1                       0x00E0 0x0290 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TD1__LPUART4_RTS_B                         0x00E0 0x0290 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_TD1__SAI2_RX_DATA02                        0x00E0 0x0290 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18                      0x00E0 0x0290 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TD1__GPIO4_IO18                            0x00E0 0x0290 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0                       0x00E4 0x0294 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TD0__LPUART4_TX                            0x00E4 0x0294 0x0428 0x1 0x1
+#define MX93_PAD_ENET2_TD0__SAI2_RX_DATA03                        0x00E4 0x0294 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19                      0x00E4 0x0294 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TD0__GPIO4_IO19                            0x00E4 0x0294 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL                 0x00E8 0x0298 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B                      0x00E8 0x0298 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC                       0x00E8 0x0298 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20                   0x00E8 0x0298 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TX_CTL__GPIO4_IO20                         0x00E8 0x0298 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC                       0x00EC 0x029C 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_TXC__ENET1_TX_ER                           0x00EC 0x029C 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_TXC__SAI2_TX_BCLK                          0x00EC 0x029C 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21                      0x00EC 0x029C 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_TXC__GPIO4_IO21                            0x00EC 0x029C 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL                 0x00F0 0x02A0 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B                      0x00F0 0x02A0 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00                     0x00F0 0x02A0 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22                   0x00F0 0x02A0 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RX_CTL__GPIO4_IO22                         0x00F0 0x02A0 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC                       0x00F4 0x02A4 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RXC__ENET1_RX_ER                           0x00F4 0x02A4 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_RXC__SAI2_TX_DATA01                        0x00F4 0x02A4 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23                      0x00F4 0x02A4 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RXC__GPIO4_IO23                            0x00F4 0x02A4 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0                       0x00F8 0x02A8 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RD0__LPUART4_RX                            0x00F8 0x02A8 0x0424 0x1 0x1
+#define MX93_PAD_ENET2_RD0__SAI2_TX_DATA02                        0x00F8 0x02A8 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24                      0x00F8 0x02A8 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RD0__GPIO4_IO24                            0x00F8 0x02A8 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1                       0x00FC 0x02AC 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RD1__SPDIF_IN                              0x00FC 0x02AC 0x0454 0x1 0x1
+#define MX93_PAD_ENET2_RD1__SAI2_TX_DATA03                        0x00FC 0x02AC 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25                      0x00FC 0x02AC 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RD1__GPIO4_IO25                            0x00FC 0x02AC 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2                       0x0100 0x02B0 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RD2__LPUART4_CTS_B                         0x0100 0x02B0 0x0420 0x1 0x1
+#define MX93_PAD_ENET2_RD2__SAI2_MCLK                             0x0100 0x02B0 0x0000 0x2 0x0
+#define MX93_PAD_ENET2_RD2__MQS2_RIGHT                            0x0100 0x02B0 0x0000 0x3 0x0
+#define MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26                      0x0100 0x02B0 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RD2__GPIO4_IO26                            0x0100 0x02B0 0x0000 0x5 0x0
+#define MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3                       0x0104 0x02B4 0x0000 0x0 0x0
+#define MX93_PAD_ENET2_RD3__SPDIF_OUT                             0x0104 0x02B4 0x0000 0x1 0x0
+#define MX93_PAD_ENET2_RD3__SPDIF_IN                              0x0104 0x02B4 0x0454 0x2 0x2
+#define MX93_PAD_ENET2_RD3__MQS2_LEFT                             0x0104 0x02B4 0x0000 0x3 0x0
+#define MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27                      0x0104 0x02B4 0x0000 0x4 0x0
+#define MX93_PAD_ENET2_RD3__GPIO4_IO27                            0x0104 0x02B4 0x0000 0x5 0x0
+#define MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08                        0x0108 0x02B8 0x038C 0x4 0x1
+#define MX93_PAD_SD1_CLK__GPIO3_IO08                              0x0108 0x02B8 0x0000 0x5 0x0
+#define MX93_PAD_SD1_CLK__USDHC1_CLK                              0x0108 0x02B8 0x0000 0x0 0x0
+#define MX93_PAD_SD1_CMD__USDHC1_CMD                              0x010C 0x02BC 0x0000 0x0 0x0
+#define MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09                        0x010C 0x02BC 0x0390 0x4 0x1
+#define MX93_PAD_SD1_CMD__GPIO3_IO09                              0x010C 0x02BC 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA0__USDHC1_DATA0                          0x0110 0x02C0 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10                      0x0110 0x02C0 0x0394 0x4 0x1
+#define MX93_PAD_SD1_DATA0__GPIO3_IO10                            0x0110 0x02C0 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA1__USDHC1_DATA1                          0x0114 0x02C4 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11                      0x0114 0x02C4 0x0398 0x4 0x1
+#define MX93_PAD_SD1_DATA1__GPIO3_IO11                            0x0114 0x02C4 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT                 0x0114 0x02C4 0x0000 0x6 0x0
+#define MX93_PAD_SD1_DATA2__USDHC1_DATA2                          0x0118 0x02C8 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12                      0x0118 0x02C8 0x0000 0x4 0x0
+#define MX93_PAD_SD1_DATA2__GPIO3_IO12                            0x0118 0x02C8 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY               0x0118 0x02C8 0x0000 0x6 0x0
+#define MX93_PAD_SD1_DATA3__USDHC1_DATA3                          0x011C 0x02CC 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B                      0x011C 0x02CC 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13                      0x011C 0x02CC 0x039C 0x4 0x1
+#define MX93_PAD_SD1_DATA3__GPIO3_IO13                            0x011C 0x02CC 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA4__USDHC1_DATA4                          0x0120 0x02D0 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04                     0x0120 0x02D0 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14                      0x0120 0x02D0 0x03A0 0x4 0x1
+#define MX93_PAD_SD1_DATA4__GPIO3_IO14                            0x0120 0x02D0 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA5__USDHC1_DATA5                          0x0124 0x02D4 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05                     0x0124 0x02D4 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA5__USDHC1_RESET_B                        0x0124 0x02D4 0x0000 0x2 0x0
+#define MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15                      0x0124 0x02D4 0x03A4 0x4 0x1
+#define MX93_PAD_SD1_DATA5__GPIO3_IO15                            0x0124 0x02D4 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA6__USDHC1_DATA6                          0x0128 0x02D8 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06                     0x0128 0x02D8 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA6__USDHC1_CD_B                           0x0128 0x02D8 0x0000 0x2 0x0
+#define MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16                      0x0128 0x02D8 0x03A8 0x4 0x1
+#define MX93_PAD_SD1_DATA6__GPIO3_IO16                            0x0128 0x02D8 0x0000 0x5 0x0
+#define MX93_PAD_SD1_DATA7__USDHC1_DATA7                          0x012C 0x02DC 0x0000 0x0 0x0
+#define MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07                     0x012C 0x02DC 0x0000 0x1 0x0
+#define MX93_PAD_SD1_DATA7__USDHC1_WP                             0x012C 0x02DC 0x0000 0x2 0x0
+#define MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17                      0x012C 0x02DC 0x03AC 0x4 0x1
+#define MX93_PAD_SD1_DATA7__GPIO3_IO17                            0x012C 0x02DC 0x0000 0x5 0x0
+#define MX93_PAD_SD1_STROBE__USDHC1_STROBE                        0x0130 0x02E0 0x0000 0x0 0x0
+#define MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS                       0x0130 0x02E0 0x0000 0x1 0x0
+#define MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18                     0x0130 0x02E0 0x03B0 0x4 0x1
+#define MX93_PAD_SD1_STROBE__GPIO3_IO18                           0x0130 0x02E0 0x0000 0x5 0x0
+#define MX93_PAD_SD2_VSELECT__USDHC2_VSELECT                      0x0134 0x02E4 0x0000 0x0 0x0
+#define MX93_PAD_SD2_VSELECT__USDHC2_WP                           0x0134 0x02E4 0x0000 0x1 0x0
+#define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3                         0x0134 0x02E4 0x0410 0x2 0x1
+#define MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19                    0x0134 0x02E4 0x0000 0x4 0x0
+#define MX93_PAD_SD2_VSELECT__GPIO3_IO19                          0x0134 0x02E4 0x0000 0x5 0x0
+#define MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1               0x0134 0x02E4 0x0368 0x6 0x0
+#define MX93_PAD_SD3_CLK__USDHC3_CLK                              0x0138 0x02E8 0x0458 0x0 0x1
+#define MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK                         0x0138 0x02E8 0x0000 0x1 0x0
+#define MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20                        0x0138 0x02E8 0x03B4 0x4 0x1
+#define MX93_PAD_SD3_CLK__GPIO3_IO20                              0x0138 0x02E8 0x0000 0x5 0x0
+#define MX93_PAD_SD3_CMD__USDHC3_CMD                              0x013C 0x02EC 0x045C 0x0 0x1
+#define MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B                        0x013C 0x02EC 0x0000 0x1 0x0
+#define MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21                        0x013C 0x02EC 0x0000 0x4 0x0
+#define MX93_PAD_SD3_CMD__GPIO3_IO21                              0x013C 0x02EC 0x0000 0x5 0x0
+#define MX93_PAD_SD3_DATA0__USDHC3_DATA0                          0x0140 0x02F0 0x0460 0x0 0x1
+#define MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00                     0x0140 0x02F0 0x0000 0x1 0x0
+#define MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22                      0x0140 0x02F0 0x03B8 0x4 0x1
+#define MX93_PAD_SD3_DATA0__GPIO3_IO22                            0x0140 0x02F0 0x0000 0x5 0x0
+#define MX93_PAD_SD3_DATA1__USDHC3_DATA1                          0x0144 0x02F4 0x0464 0x0 0x1
+#define MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01                     0x0144 0x02F4 0x0000 0x1 0x0
+#define MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23                      0x0144 0x02F4 0x03BC 0x4 0x1
+#define MX93_PAD_SD3_DATA1__GPIO3_IO23                            0x0144 0x02F4 0x0000 0x5 0x0
+#define MX93_PAD_SD3_DATA2__USDHC3_DATA2                          0x0148 0x02F8 0x0468 0x0 0x1
+#define MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02                     0x0148 0x02F8 0x0000 0x1 0x0
+#define MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24                      0x0148 0x02F8 0x03C0 0x4 0x1
+#define MX93_PAD_SD3_DATA2__GPIO3_IO24                            0x0148 0x02F8 0x0000 0x5 0x0
+#define MX93_PAD_SD3_DATA3__USDHC3_DATA3                          0x014C 0x02FC 0x046C 0x0 0x1
+#define MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03                     0x014C 0x02FC 0x0000 0x1 0x0
+#define MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25                      0x014C 0x02FC 0x03C4 0x4 0x1
+#define MX93_PAD_SD3_DATA3__GPIO3_IO25                            0x014C 0x02FC 0x0000 0x5 0x0
+#define MX93_PAD_SD2_CD_B__USDHC2_CD_B                            0x0150 0x0300 0x0000 0x0 0x0
+#define MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN                0x0150 0x0300 0x0000 0x1 0x0
+#define MX93_PAD_SD2_CD_B__I3C2_SCL                               0x0150 0x0300 0x03CC 0x2 0x1
+#define MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00                       0x0150 0x0300 0x036C 0x4 0x1
+#define MX93_PAD_SD2_CD_B__GPIO3_IO00                             0x0150 0x0300 0x0000 0x5 0x0
+#define MX93_PAD_SD2_CLK__USDHC2_CLK                              0x0154 0x0304 0x0000 0x0 0x0
+#define MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT                0x0154 0x0304 0x0000 0x1 0x0
+#define MX93_PAD_SD2_CLK__I3C2_SDA                                0x0154 0x0304 0x03D0 0x2 0x1
+#define MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01                        0x0154 0x0304 0x0370 0x4 0x1
+#define MX93_PAD_SD2_CLK__GPIO3_IO01                              0x0154 0x0304 0x0000 0x5 0x0
+#define MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0                   0x0154 0x0304 0x0000 0x6 0x0
+#define MX93_PAD_SD2_CMD__USDHC2_CMD                              0x0158 0x0308 0x0000 0x0 0x0
+#define MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN                    0x0158 0x0308 0x0000 0x1 0x0
+#define MX93_PAD_SD2_CMD__I3C2_PUR                                0x0158 0x0308 0x0000 0x2 0x0
+#define MX93_PAD_SD2_CMD__I3C2_PUR_B                              0x0158 0x0308 0x0000 0x3 0x0
+#define MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02                        0x0158 0x0308 0x0374 0x4 0x1
+#define MX93_PAD_SD2_CMD__GPIO3_IO02                              0x0158 0x0308 0x0000 0x5 0x0
+#define MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1                   0x0158 0x0308 0x0000 0x6 0x0
+#define MX93_PAD_SD2_DATA0__USDHC2_DATA0                          0x015C 0x030C 0x0000 0x0 0x0
+#define MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT                 0x015C 0x030C 0x0000 0x1 0x0
+#define MX93_PAD_SD2_DATA0__CAN2_TX                               0x015C 0x030C 0x0000 0x2 0x0
+#define MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03                      0x015C 0x030C 0x0378 0x4 0x1
+#define MX93_PAD_SD2_DATA0__GPIO3_IO03                            0x015C 0x030C 0x0000 0x5 0x0
+#define MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2                 0x015C 0x030C 0x0000 0x6 0x0
+#define MX93_PAD_SD2_DATA1__USDHC2_DATA1                          0x0160 0x0310 0x0000 0x0 0x0
+#define MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN                  0x0160 0x0310 0x0000 0x1 0x0
+#define MX93_PAD_SD2_DATA1__CAN2_RX                               0x0160 0x0310 0x0364 0x2 0x3
+#define MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04                      0x0160 0x0310 0x037C 0x4 0x1
+#define MX93_PAD_SD2_DATA1__GPIO3_IO04                            0x0160 0x0310 0x0000 0x5 0x0
+#define MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT                     0x0160 0x0310 0x0000 0x6 0x0
+#define MX93_PAD_SD2_DATA2__USDHC2_DATA2                          0x0164 0x0314 0x0000 0x0 0x0
+#define MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT                 0x0164 0x0314 0x0000 0x1 0x0
+#define MX93_PAD_SD2_DATA2__MQS2_RIGHT                            0x0164 0x0314 0x0000 0x2 0x0
+#define MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05                      0x0164 0x0314 0x0380 0x4 0x1
+#define MX93_PAD_SD2_DATA2__GPIO3_IO05                            0x0164 0x0314 0x0000 0x5 0x0
+#define MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP                     0x0164 0x0314 0x0000 0x6 0x0
+#define MX93_PAD_SD2_DATA3__USDHC2_DATA3                          0x0168 0x0318 0x0000 0x0 0x0
+#define MX93_PAD_SD2_DATA3__LPTMR2_ALT1                           0x0168 0x0318 0x0408 0x1 0x1
+#define MX93_PAD_SD2_DATA3__MQS2_LEFT                             0x0168 0x0318 0x0000 0x2 0x0
+#define MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06                      0x0168 0x0318 0x0384 0x4 0x1
+#define MX93_PAD_SD2_DATA3__GPIO3_IO06                            0x0168 0x0318 0x0000 0x5 0x0
+#define MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET              0x0168 0x0318 0x0000 0x6 0x0
+#define MX93_PAD_SD2_RESET_B__USDHC2_RESET_B                      0x016C 0x031C 0x0000 0x0 0x0
+#define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2                         0x016C 0x031C 0x040C 0x1 0x1
+#define MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07                    0x016C 0x031C 0x0388 0x4 0x1
+#define MX93_PAD_SD2_RESET_B__GPIO3_IO07                          0x016C 0x031C 0x0000 0x5 0x0
+#define MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET           0x016C 0x031C 0x0000 0x6 0x0
+#define MX93_PAD_I2C1_SCL__LPI2C1_SCL                             0x0170 0x0320 0x0000 0x10 0x0
+#define MX93_PAD_I2C1_SCL__I3C1_SCL                               0x0170 0x0320 0x0000 0x1 0x0
+#define MX93_PAD_I2C1_SCL__LPUART1_DCB_B                          0x0170 0x0320 0x0000 0x2 0x0
+#define MX93_PAD_I2C1_SCL__TPM2_CH0                               0x0170 0x0320 0x0000 0x3 0x0
+#define MX93_PAD_I2C1_SCL__GPIO1_IO00                             0x0170 0x0320 0x0000 0x5 0x0
+#define MX93_PAD_I2C1_SDA__LPI2C1_SDA                             0x0174 0x0324 0x0000 0x10 0x0
+#define MX93_PAD_I2C1_SDA__I3C1_SDA                               0x0174 0x0324 0x0000 0x1 0x0
+#define MX93_PAD_I2C1_SDA__LPUART1_RIN_B                          0x0174 0x0324 0x0000 0x2 0x0
+#define MX93_PAD_I2C1_SDA__TPM2_CH1                               0x0174 0x0324 0x0000 0x3 0x0
+#define MX93_PAD_I2C1_SDA__GPIO1_IO01                             0x0174 0x0324 0x0000 0x5 0x0
+#define MX93_PAD_I2C2_SCL__LPI2C2_SCL                             0x0178 0x0328 0x0000 0x10 0x0
+#define MX93_PAD_I2C2_SCL__I3C1_PUR                               0x0178 0x0328 0x0000 0x1 0x0
+#define MX93_PAD_I2C2_SCL__LPUART2_DCB_B                          0x0178 0x0328 0x0000 0x2 0x0
+#define MX93_PAD_I2C2_SCL__TPM2_CH2                               0x0178 0x0328 0x0000 0x3 0x0
+#define MX93_PAD_I2C2_SCL__SAI1_RX_SYNC                           0x0178 0x0328 0x0000 0x4 0x0
+#define MX93_PAD_I2C2_SCL__GPIO1_IO02                             0x0178 0x0328 0x0000 0x5 0x0
+#define MX93_PAD_I2C2_SCL__I3C1_PUR_B                             0x0178 0x0328 0x0000 0x6 0x0
+#define MX93_PAD_I2C2_SDA__LPI2C2_SDA                             0x017C 0x032C 0x0000 0x10 0x0
+#define MX93_PAD_I2C2_SDA__LPUART2_RIN_B                          0x017C 0x032C 0x0000 0x2 0x0
+#define MX93_PAD_I2C2_SDA__TPM2_CH3                               0x017C 0x032C 0x0000 0x3 0x0
+#define MX93_PAD_I2C2_SDA__SAI1_RX_BCLK                           0x017C 0x032C 0x0000 0x4 0x0
+#define MX93_PAD_I2C2_SDA__GPIO1_IO03                             0x017C 0x032C 0x0000 0x5 0x0
+#define MX93_PAD_UART1_RXD__LPUART1_RX                            0x0180 0x0330 0x0000 0x0 0x0
+#define MX93_PAD_UART1_RXD__S400_UART_RX                          0x0180 0x0330 0x0000 0x1 0x0
+#define MX93_PAD_UART1_RXD__LPSPI2_SIN                            0x0180 0x0330 0x0000 0x2 0x0
+#define MX93_PAD_UART1_RXD__TPM1_CH0                              0x0180 0x0330 0x0000 0x3 0x0
+#define MX93_PAD_UART1_RXD__GPIO1_IO04                            0x0180 0x0330 0x0000 0x5 0x0
+#define MX93_PAD_UART1_TXD__LPUART1_TX                            0x0184 0x0334 0x0000 0x0 0x0
+#define MX93_PAD_UART1_TXD__S400_UART_TX                          0x0184 0x0334 0x0000 0x1 0x0
+#define MX93_PAD_UART1_TXD__LPSPI2_PCS0                           0x0184 0x0334 0x0000 0x2 0x0
+#define MX93_PAD_UART1_TXD__TPM1_CH1                              0x0184 0x0334 0x0000 0x3 0x0
+#define MX93_PAD_UART1_TXD__GPIO1_IO05                            0x0184 0x0334 0x0000 0x5 0x0
+#define MX93_PAD_UART2_RXD__LPUART2_RX                            0x0188 0x0338 0x0000 0x0 0x0
+#define MX93_PAD_UART2_RXD__LPUART1_CTS_B                         0x0188 0x0338 0x0000 0x1 0x0
+#define MX93_PAD_UART2_RXD__LPSPI2_SOUT                           0x0188 0x0338 0x0000 0x2 0x0
+#define MX93_PAD_UART2_RXD__TPM1_CH2                              0x0188 0x0338 0x0000 0x3 0x0
+#define MX93_PAD_UART2_RXD__SAI1_MCLK                             0x0188 0x0338 0x0448 0x4 0x0
+#define MX93_PAD_UART2_RXD__GPIO1_IO06                            0x0188 0x0338 0x0000 0x5 0x0
+#define MX93_PAD_UART2_TXD__LPUART2_TX                            0x018C 0x033C 0x0000 0x0 0x0
+#define MX93_PAD_UART2_TXD__LPUART1_RTS_B                         0x018C 0x033C 0x0000 0x1 0x0
+#define MX93_PAD_UART2_TXD__LPSPI2_SCK                            0x018C 0x033C 0x0000 0x2 0x0
+#define MX93_PAD_UART2_TXD__TPM1_CH3                              0x018C 0x033C 0x0000 0x3 0x0
+#define MX93_PAD_UART2_TXD__GPIO1_IO07                            0x018C 0x033C 0x0000 0x5 0x0
+#define MX93_PAD_PDM_CLK__PDM_CLK                                 0x0190 0x0340 0x0000 0x0 0x0
+#define MX93_PAD_PDM_CLK__MQS1_LEFT                               0x0190 0x0340 0x0000 0x1 0x0
+#define MX93_PAD_PDM_CLK__LPTMR1_ALT1                             0x0190 0x0340 0x0000 0x4 0x0
+#define MX93_PAD_PDM_CLK__GPIO1_IO08                              0x0190 0x0340 0x0000 0x5 0x0
+#define MX93_PAD_PDM_CLK__CAN1_TX                                 0x0190 0x0340 0x0000 0x6 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00                0x0194 0x0344 0x0438 0x0 0x2
+#define MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT                      0x0194 0x0344 0x0000 0x1 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1                     0x0194 0x0344 0x0000 0x2 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK                     0x0194 0x0344 0x0000 0x3 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2                     0x0194 0x0344 0x0000 0x4 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09                      0x0194 0x0344 0x0000 0x5 0x0
+#define MX93_PAD_PDM_BIT_STREAM0__CAN1_RX                         0x0194 0x0344 0x0360 0x6 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01                0x0198 0x0348 0x043C 0x0 0x2
+#define MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI                    0x0198 0x0348 0x0000 0x1 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1                     0x0198 0x0348 0x0000 0x2 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK                     0x0198 0x0348 0x0000 0x3 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3                     0x0198 0x0348 0x0000 0x4 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10                      0x0198 0x0348 0x0000 0x5 0x0
+#define MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1           0x0198 0x0348 0x0368 0x6 0x1
+#define MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC                          0x019C 0x034C 0x0000 0x0 0x0
+#define MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01                        0x019C 0x034C 0x0000 0x1 0x0
+#define MX93_PAD_SAI1_TXFS__LPSPI1_PCS0                           0x019C 0x034C 0x0000 0x2 0x0
+#define MX93_PAD_SAI1_TXFS__LPUART2_DTR_B                         0x019C 0x034C 0x0000 0x3 0x0
+#define MX93_PAD_SAI1_TXFS__MQS1_LEFT                             0x019C 0x034C 0x0000 0x4 0x0
+#define MX93_PAD_SAI1_TXFS__GPIO1_IO11                            0x019C 0x034C 0x0000 0x5 0x0
+#define MX93_PAD_SAI1_TXC__SAI1_TX_BCLK                           0x01A0 0x0350 0x0000 0x0 0x0
+#define MX93_PAD_SAI1_TXC__LPUART2_CTS_B                          0x01A0 0x0350 0x0000 0x1 0x0
+#define MX93_PAD_SAI1_TXC__LPSPI1_SIN                             0x01A0 0x0350 0x0000 0x2 0x0
+#define MX93_PAD_SAI1_TXC__LPUART1_DSR_B                          0x01A0 0x0350 0x0000 0x3 0x0
+#define MX93_PAD_SAI1_TXC__CAN1_RX                                0x01A0 0x0350 0x0360 0x4 0x1
+#define MX93_PAD_SAI1_TXC__GPIO1_IO12                             0x01A0 0x0350 0x0000 0x5 0x0
+#define MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00                        0x01A4 0x0354 0x0000 0x0 0x0
+#define MX93_PAD_SAI1_TXD0__LPUART2_RTS_B                         0x01A4 0x0354 0x0000 0x1 0x0
+#define MX93_PAD_SAI1_TXD0__LPSPI1_SCK                            0x01A4 0x0354 0x0000 0x2 0x0
+#define MX93_PAD_SAI1_TXD0__LPUART1_DTR_B                         0x01A4 0x0354 0x0000 0x3 0x0
+#define MX93_PAD_SAI1_TXD0__CAN1_TX                               0x01A4 0x0354 0x0000 0x4 0x0
+#define MX93_PAD_SAI1_TXD0__GPIO1_IO13                            0x01A4 0x0354 0x0000 0x5 0x0
+#define MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00                        0x01A8 0x0358 0x0000 0x0 0x0
+#define MX93_PAD_SAI1_RXD0__SAI1_MCLK                             0x01A8 0x0358 0x0448 0x1 0x1
+#define MX93_PAD_SAI1_RXD0__LPSPI1_SOUT                           0x01A8 0x0358 0x0000 0x2 0x0
+#define MX93_PAD_SAI1_RXD0__LPUART2_DSR_B                         0x01A8 0x0358 0x0000 0x3 0x0
+#define MX93_PAD_SAI1_RXD0__MQS1_RIGHT                            0x01A8 0x0358 0x0000 0x4 0x0
+#define MX93_PAD_SAI1_RXD0__GPIO1_IO14                            0x01A8 0x0358 0x0000 0x5 0x0
+#define MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY                         0x01AC 0x035C 0x0000 0x0 0x0
+#define MX93_PAD_WDOG_ANY__GPIO1_IO15                             0x01AC 0x035C 0x0000 0x5 0x0
+
+#endif /* __DTS_IMX93_PINFUNC_H */
diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi
new file mode 100644
index 00000000000..59a09b5ec58
--- /dev/null
+++ b/arch/arm/dts/imx93.dtsi
@@ -0,0 +1,1514 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+#include <dt-bindings/clock/imx93-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/power/imx93-power.h>
+#include <dt-bindings/usb/pd.h>
+
+#include "imx93-pinfunc.h"
+
+/ {
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+		mmc2 = &usdhc3;
+		ethernet0 = &fec;
+		ethernet1 = &eqos;
+		serial0 = &lpuart1;
+		serial1 = &lpuart2;
+		serial2 = &lpuart3;
+		serial3 = &lpuart4;
+		serial4 = &lpuart5;
+		serial5 = &lpuart6;
+		serial6 = &lpuart7;
+		serial7 = &lpuart8;
+		isi0 = &isi_0;
+		i2c0 = &lpi2c1;
+		i2c1 = &lpi2c2;
+		i2c2 = &lpi2c3;
+		i2c3 = &lpi2c4;
+		i2c4 = &lpi2c5;
+		i2c5 = &lpi2c6;
+		i2c6 = &lpi2c7;
+		i2c7 = &lpi2c8;
+		csi0 = &mipi_csi;
+		usb0 = &usbotg1;
+		usb1 = &usbotg2;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		A55_0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0>;
+			enable-method = "psci";
+			#cooling-cells = <2>;
+		};
+
+		A55_1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			enable-method = "psci";
+			#cooling-cells = <2>;
+		};
+
+	};
+
+	osc_32k: clock-osc-32k {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "osc_32k";
+	};
+
+	osc_24m: clock-osc-24m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		clock-output-names = "osc_24m";
+	};
+
+	clk_ext1: clock-ext1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <133000000>;
+		clock-output-names = "clk_ext1";
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <24000000>;
+		arm,no-tick-in-suspend;
+		interrupt-parent = <&gic>;
+	};
+
+	gic: interrupt-controller@48000000 {
+		compatible = "arm,gic-v3";
+		reg = <0 0x48000000 0 0x10000>,
+		      <0 0x48040000 0 0xc0000>;
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&gic>;
+	};
+
+	thermal-zones {
+		cpu-thermal {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+
+			thermal-sensors = <&tmu 0>;
+
+			trips {
+				cpu_alert: cpu-alert {
+					temperature = <80000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu_crit: cpu-crit {
+					temperature = <90000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert>;
+					cooling-device =
+						<&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+						<&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
+	soc@0 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x0 0x80000000>,
+			 <0x28000000 0x0 0x28000000 0x10000000>;
+
+		aips1: bus@44000000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			reg = <0x44000000 0x800000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			mu1: mailbox@44230000 {
+				compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
+				reg = <0x44230000 0x10000>;
+				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+				#mbox-cells = <2>;
+				status = "disabled";
+			};
+
+			edma1: dma-controller@44000000{
+				compatible = "fsl,imx93-edma-v3";
+				reg = <0x44000000 0x10000>,
+				      <0x44010000 0x10000>, <0x44020000 0x10000>,
+				      <0x44030000 0x10000>, <0x44040000 0x10000>,
+				      <0x44050000 0x10000>, <0x44060000 0x10000>,
+				      <0x44070000 0x10000>, <0x44080000 0x10000>,
+				      <0x44090000 0x10000>, <0x440a0000 0x10000>,
+				      <0x440b0000 0x10000>, <0x440c0000 0x10000>,
+				      <0x440d0000 0x10000>, <0x440e0000 0x10000>,
+				      <0x440f0000 0x10000>, <0x44100000 0x10000>,
+				      <0x44110000 0x10000>, <0x44120000 0x10000>,
+				      <0x44130000 0x10000>, <0x44140000 0x10000>,
+				      <0x44150000 0x10000>, <0x44160000 0x10000>,
+				      <0x44170000 0x10000>, <0x44180000 0x10000>,
+				      <0x44190000 0x10000>, <0x441a0000 0x10000>,
+				      <0x441b0000 0x10000>, <0x441c0000 0x10000>,
+				      <0x441d0000 0x10000>, <0x441e0000 0x10000>,
+				      <0x441f0000 0x10000>;
+				#dma-cells = <3>;
+				dma-channels = <31>;
+				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "edma1-chan0-tx", "edma1-chan1-tx",
+						  "edma1-chan2-tx", "edma1-chan3-tx",
+						  "edma1-chan4-tx", "edma1-chan5-tx",
+						  "edma1-chan6-tx", "edma1-chan7-tx",
+						  "edma1-chan8-tx", "edma1-chan9-tx",
+						  "edma1-chan10-tx", "edma1-chan11-tx",
+						  "edma1-chan12-tx", "edma1-chan13-tx",
+						  "edma1-chan14-tx", "edma1-chan15-tx",
+						  "edma1-chan16-tx", "edma1-chan17-tx",
+						  "edma1-chan18-tx", "edma1-chan19-tx",
+						  "edma1-chan20-tx", "edma1-chan21-tx",
+						  "edma1-chan22-tx", "edma1-chan23-tx",
+						  "edma1-chan24-tx", "edma1-chan25-tx",
+						  "edma1-chan26-tx", "edma1-chan27-tx",
+						  "edma1-chan28-tx", "edma1-chan29-tx",
+						  "edma1-chan30-tx", "edma1-err";
+				clocks = <&clk IMX93_CLK_EDMA1_GATE>;
+				clock-names = "edma";
+				status = "disabled";
+			};
+
+			anomix_ns_gpr: blk-ctrl-anomix@42420000 {
+				compatible = "syscon";
+				reg = <0x44210000 0x1000>;
+			};
+
+			system_counter: timer@44290000 {
+				compatible = "nxp,sysctr-timer";
+				reg = <0x44290000 0x30000>;
+				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&osc_24m>;
+				clock-names = "per";
+			};
+
+			i3c1: i3c-master@44330000 {
+				#address-cells = <3>;
+				#size-cells = <0>;
+				compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master";
+				reg = <0x44330000 0x10000>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_I3C1_GATE>,
+					 <&clk IMX93_CLK_I3C1_GATE>,
+					 <&clk IMX93_CLK_DUMMY>;
+				clock-names = "pclk", "fast_clk", "slow_clk";
+				status = "disabled";
+			};
+
+			lpi2c1: i2c@44340000 {
+				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+				reg = <0x44340000 0x10000>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPI2C1_GATE>,
+					 <&clk IMX93_CLK_LPI2C1_GATE>;
+				clock-names = "per", "ipg";
+				dmas = <&edma1 7 0 0>, <&edma1 8 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpi2c2: i2c@44350000 {
+				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+				reg = <0x44350000 0x10000>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPI2C2_GATE>,
+					 <&clk IMX93_CLK_LPI2C2_GATE>;
+				clock-names = "per", "ipg";
+				dmas = <&edma1 9 0 0>, <&edma1 10 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpspi1: spi@44360000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+				reg = <0x44360000 0x10000>;
+				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPSPI1_GATE>,
+					 <&clk IMX93_CLK_LPSPI1_GATE>;
+				clock-names = "per", "ipg";
+				dmas = <&edma1 11 0 0>, <&edma1 12 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpspi2: spi@44370000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+				reg = <0x44370000 0x10000>;
+				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPSPI2_GATE>,
+					 <&clk IMX93_CLK_LPSPI2_GATE>;
+				clock-names = "per", "ipg";
+				dmas = <&edma1 13 0 0>, <&edma1 14 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpuart1: serial@44380000 {
+				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x44380000 0x1000>;
+				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPUART1_GATE>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			lpuart2: serial@44390000 {
+				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x44390000 0x1000>;
+				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPUART2_GATE>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+
+			flexcan1: can@443a0000 {
+				compatible = "fsl,imx93-flexcan", "fsl,imx8mp-flexcan";
+				reg = <0x443a0000 0x10000>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_BUS_AON>,
+					 <&clk IMX93_CLK_CAN1_GATE>;
+				clock-names = "ipg", "per";
+				assigned-clocks = <&clk IMX93_CLK_CAN1>;
+				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+				assigned-clock-rates = <40000000>;
+				fsl,clk-source = /bits/ 8 <0>;
+				//fsl,stop-mode = <&gpr 0x10 4 0x10 20>;
+				status = "disabled";
+			};
+
+			sai1: sai@443b0000 {
+				compatible = "fsl,imx93-sai";
+				reg = <0x443b0000 0x10000>;
+				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>,
+					 <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>,
+					 <&clk IMX93_CLK_DUMMY>;
+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+				dmas = <&edma1 22 0 1>, <&edma1 21 0 0>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+				/* sai1 supports 2x TX/RX */
+			};
+
+			mqs1: mqs1 {
+				compatible = "fsl,imx93-mqs";
+				gpr = <&anomix_ns_gpr>;
+				status = "disabled";
+			};
+
+			mqs2: mqs2 {
+				compatible = "fsl,imx93-mqs";
+				gpr = <&wakeupmix_gpr>;
+				status = "disabled";
+			};
+
+			iomuxc: pinctrl@443c0000 {
+				compatible = "fsl,imx93-iomuxc";
+				reg = <0x443c0000 0x10000>;
+			};
+
+			bbnsm: bbnsm@44440000 {
+				compatible = "syscon", "simple-mfd";
+				reg = <0x44440000 0x10000>;
+
+				bbnsm_rtc: rtc {
+					compatible = "nxp,bbnsm-rtc";
+					regmap = <&bbnsm>;
+					interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+				};
+
+				bbnsm_pwrkey: pwrkey {
+					compatible = "nxp,bbnsm-pwrkey";
+					regmap = <&bbnsm>;
+					interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+					linux,keycode = <KEY_POWER>;
+					wakeup-source;
+				};
+			};
+
+			clk: clock-controller@44450000 {
+				compatible = "fsl,imx93-ccm";
+				reg = <0x44450000 0x10000>;
+				#clock-cells = <1>;
+				clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
+				clock-names = "osc_32k", "osc_24m", "clk_ext1";
+				assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>;
+				assigned-clock-rates = <393216000>;
+				status = "okay";
+			};
+
+			src: src@44460000 {
+				compatible = "fsl,imx93-src";
+				reg = <0x44460000 0x10000>;
+
+				slice {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					mlmix: slice@1800 {
+						reg = <IMX93_POWER_DOMAIN_MLMIX>;
+						#power-domain-cells = <0>;
+					};
+
+					mediamix: slice@2400 {
+						reg = <IMX93_POWER_DOMAIN_MEDIAMIX>;
+						#power-domain-cells = <0>;
+						clocks = <&clk IMX93_CLK_MEDIA_AXI>,
+							 <&clk IMX93_CLK_MEDIA_APB>;
+					};
+				};
+			};
+
+			anatop: anatop@44480000 {
+				compatible = "fsl,imx93-anatop", "syscon";
+				reg = <0x44480000 0x10000>;
+			};
+
+			tmu: tmu@44482000 {
+				compatible = "fsl,imx93-tmu", "fsl,imx8mq-tmu";
+				little-endian;
+				reg = <0x44482000 0x1000>;
+				clocks = <&clk IMX93_CLK_TMC_GATE>;
+				fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
+				fsl,tmu-calibration = <0x00000000 0x00000023
+						       0x00000001 0x00000029
+						       0x00000002 0x0000002f
+						       0x00000003 0x00000035
+						       0x00000004 0x0000003d
+						       0x00000005 0x00000043
+						       0x00000006 0x0000004b
+						       0x00000007 0x00000051
+						       0x00000008 0x00000057
+						       0x00000009 0x0000005f
+						       0x0000000a 0x00000067
+						       0x0000000b 0x0000006f
+
+						       0x00010000 0x0000001b
+						       0x00010001 0x00000023
+						       0x00010002 0x0000002b
+						       0x00010003 0x00000033
+						       0x00010004 0x0000003b
+						       0x00010005 0x00000043
+						       0x00010006 0x0000004b
+						       0x00010007 0x00000055
+						       0x00010008 0x0000005d
+						       0x00010009 0x00000067
+						       0x0001000a 0x00000070
+
+						       0x00020000 0x00000017
+						       0x00020001 0x00000023
+						       0x00020002 0x0000002d
+						       0x00020003 0x00000037
+						       0x00020004 0x00000041
+						       0x00020005 0x0000004b
+						       0x00020006 0x00000057
+						       0x00020007 0x00000063
+						       0x00020008 0x0000006f
+
+						       0x00030000 0x00000015
+						       0x00030001 0x00000021
+						       0x00030002 0x0000002d
+						       0x00030003 0x00000039
+						       0x00030004 0x00000045
+						       0x00030005 0x00000053
+						       0x00030006 0x0000005f
+						       0x00030007 0x00000071>;
+				#thermal-sensor-cells =  <0>;
+				status = "disabled";
+			};
+		
+			micfil: micfil@44520000 {
+				compatible = "fsl,imx93-micfil";
+				reg = <0x44520000 0x10000>;
+				/*
+					199	pdm	ipi_int_hwvad_err
+					200	pdm	ipi_int_hwvad_event
+					201	pdm	ipi_int_mic_err
+					202	pdm	ipi_int_mic_filter
+				*/
+				interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+							<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+							<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+							<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_BUS_AON>,
+						<&clk IMX93_CLK_PDM_GATE>,
+						<&clk IMX93_CLK_AUDIO_PLL>,
+						<&clk IMX93_CLK_DUMMY>;
+				clock-names = "ipg_clk", "ipg_clk_app",
+							"pll8k", "clkext3";
+				dmas = <&edma1 29 0 5>;
+				dma-names = "rx";
+				status = "disabled";
+			};
+
+			adc1: adc@44530000 {
+				compatible = "nxp,imx93-adc";
+				reg = <0x44530000 0x10000>;
+				interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_ADC1_GATE>;
+				clock-names = "ipg";
+				status = "disabled";
+			};
+		};
+
+		aips2: bus@42000000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			reg = <0x42000000 0x800000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			edma2: dma-controller@42000000{
+				compatible = "fsl,imx93-edma-v4";
+				reg = <0x42000000 0x10000>,
+				      <0x42010000 0x8000>, <0x42018000 0x8000>,
+				      <0x42020000 0x8000>, <0x42028000 0x8000>,
+				      <0x42030000 0x8000>, <0x42038000 0x8000>,
+				      <0x42040000 0x8000>, <0x42048000 0x8000>,
+				      <0x42050000 0x8000>, <0x42058000 0x8000>,
+				      <0x42060000 0x8000>, <0x42068000 0x8000>,
+				      <0x42070000 0x8000>, <0x42078000 0x8000>,
+				      <0x42080000 0x8000>, <0x42088000 0x8000>,
+				      <0x42090000 0x8000>, <0x42098000 0x8000>,
+				      <0x420a0000 0x8000>, <0x420a8000 0x8000>,
+				      <0x420b0000 0x8000>, <0x420b8000 0x8000>,
+				      <0x420c0000 0x8000>, <0x420c8000 0x8000>,
+				      <0x420d0000 0x8000>, <0x420d8000 0x8000>,
+				      <0x420e0000 0x8000>, <0x420e8000 0x8000>,
+				      <0x420f0000 0x8000>, <0x420f8000 0x8000>,
+				      <0x42100000 0x8000>, <0x42108000 0x8000>,
+				      <0x42110000 0x8000>, <0x42118000 0x8000>,
+				      <0x42120000 0x8000>, <0x42128000 0x8000>,
+				      <0x42130000 0x8000>, <0x42138000 0x8000>,
+				      <0x42140000 0x8000>, <0x42148000 0x8000>,
+				      <0x42150000 0x8000>, <0x42158000 0x8000>,
+				      <0x42160000 0x8000>, <0x42168000 0x8000>,
+				      <0x42170000 0x8000>, <0x42178000 0x8000>,
+				      <0x42180000 0x8000>, <0x42188000 0x8000>,
+				      <0x42190000 0x8000>, <0x42198000 0x8000>,
+				      <0x421a0000 0x8000>, <0x421a8000 0x8000>,
+				      <0x421b0000 0x8000>, <0x421b8000 0x8000>,
+				      <0x421c0000 0x8000>, <0x421c8000 0x8000>,
+				      <0x421d0000 0x8000>, <0x421d8000 0x8000>,
+				      <0x421e0000 0x8000>, <0x421e8000 0x8000>,
+				      <0x421f0000 0x8000>, <0x421f8000 0x8000>,
+				      <0x42200000 0x8000>, <0x42208000 0x8000>;
+				#dma-cells = <3>;
+				shared-interrupt;
+				dma-channels = <64>;
+				interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "edma2-chan0-tx", "edma2-chan1-tx",
+						  "edma2-chan2-tx", "edma2-chan3-tx",
+						  "edma2-chan4-tx", "edma2-chan5-tx",
+						  "edma2-chan6-tx", "edma2-chan7-tx",
+						  "edma2-chan8-tx", "edma2-chan9-tx",
+						  "edma2-chan10-tx", "edma2-chan11-tx",
+						  "edma2-chan12-tx", "edma2-chan13-tx",
+						  "edma2-chan14-tx", "edma2-chan15-tx",
+						  "edma2-chan16-tx", "edma2-chan17-tx",
+						  "edma2-chan18-tx", "edma2-chan19-tx",
+						  "edma2-chan20-tx", "edma2-chan21-tx",
+						  "edma2-chan22-tx", "edma2-chan23-tx",
+						  "edma2-chan24-tx", "edma2-chan25-tx",
+						  "edma2-chan26-tx", "edma2-chan27-tx",
+						  "edma2-chan28-tx", "edma2-chan29-tx",
+						  "edma2-chan30-tx", "edma2-chan31-tx",
+						  "edma2-chan32-tx", "edma2-chan33-tx",
+						  "edma2-chan34-tx", "edma2-chan35-tx",
+						  "edma2-chan36-tx", "edma2-chan37-tx",
+						  "edma2-chan38-tx", "edma2-chan39-tx",
+						  "edma2-chan40-tx", "edma2-chan41-tx",
+						  "edma2-chan42-tx", "edma2-chan43-tx",
+						  "edma2-chan44-tx", "edma2-chan45-tx",
+						  "edma2-chan46-tx", "edma2-chan47-tx",
+						  "edma2-chan48-tx", "edma2-chan49-tx",
+						  "edma2-chan50-tx", "edma2-chan51-tx",
+						  "edma2-chan52-tx", "edma2-chan53-tx",
+						  "edma2-chan54-tx", "edma2-chan55-tx",
+						  "edma2-chan56-tx", "edma2-chan57-tx",
+						  "edma2-chan58-tx", "edma2-chan59-tx",
+						  "edma2-chan60-tx", "edma2-chan61-tx",
+						  "edma2-chan62-tx", "edma2-chan63-tx",
+						  "edma2-err";
+				clocks = <&clk IMX93_CLK_EDMA2_GATE>;
+				clock-names = "edma";
+				status = "disabled";
+			};
+
+			wakeupmix_gpr: blk-ctrl-wakeupmix@42420000 {
+				compatible = "syscon";
+				reg = <0x42420000 0x1000>;
+			};
+
+			mu2: mailbox@42440000 {
+				compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
+				reg = <0x42440000 0x10000>;
+				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+				#mbox-cells = <2>;
+				status = "disabled";
+			};
+
+			wdog3: wdog@42490000 {
+				compatible = "fsl,imx93-wdt";
+				reg = <0x42490000 0x10000>;
+				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_WDOG3_GATE>;
+				timeout-sec = <40>;
+				status = "disabled";
+			};
+
+			tpm4: pwm@424f0000 {
+				compatible = "fsl,imx7ulp-pwm";
+				reg = <0x424f0000 0x1000>;
+				clocks = <&clk IMX93_CLK_TPM4_GATE>;
+				assigned-clocks = <&clk IMX93_CLK_TPM4>;
+				assigned-clock-parents = <&clk IMX93_CLK_24M>;
+				assigned-clock-rates = <24000000>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			i3c2: i3c-master@42520000 {
+				#address-cells = <3>;
+				#size-cells = <0>;
+				compatible = "fsl,imx93-i3c-master", "silvaco,i3c-master";
+				reg = <0x42520000 0x10000>;
+				interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_I3C2_GATE>,
+					 <&clk IMX93_CLK_I3C2_GATE>,
+					 <&clk IMX93_CLK_DUMMY>;
+				clock-names = "pclk", "fast_clk", "slow_clk";
+				status = "disabled";
+			};
+
+			lpi2c3: i2c@42530000 {
+				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+				reg = <0x42530000 0x10000>;
+				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPI2C3_GATE>,
+					 <&clk IMX93_CLK_LPI2C3_GATE>;
+				clock-names = "per", "ipg";
+				dmas = <&edma2 8 0 0>, <&edma2 9 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpi2c4: i2c@42540000 {
+				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+				reg = <0x42540000 0x10000>;
+				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPI2C4_GATE>,
+					 <&clk IMX93_CLK_LPI2C4_GATE>;
+				clock-names = "per", "ipg";
+				dmas = <&edma2 10 0 0>, <&edma2 11 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpspi3: spi@42550000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+				reg = <0x42550000 0x10000>;
+				interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPSPI3_GATE>,
+					 <&clk IMX93_CLK_LPSPI3_GATE>;
+				clock-names = "per", "ipg";
+				dmas = <&edma2 12 0 0>, <&edma2 13 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpspi4: spi@42560000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+				reg = <0x42560000 0x10000>;
+				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPSPI4_GATE>,
+					 <&clk IMX93_CLK_LPSPI4_GATE>;
+				clock-names = "per", "ipg";
+				dmas = <&edma2 14 0 0>, <&edma2 15 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpuart3: serial@42570000 {
+				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x42570000 0x1000>;
+				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPUART3_GATE>;
+				clock-names = "ipg";
+				dmas = <&edma2 17 0 0>, <&edma2 18 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpuart4: serial@42580000 {
+				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x42580000 0x1000>;
+				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPUART4_GATE>;
+				clock-names = "ipg";
+				dmas = <&edma2 19 0 0>, <&edma2 20 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpuart5: serial@42590000 {
+				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x42590000 0x1000>;
+				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPUART5_GATE>;
+				clock-names = "ipg";
+				dmas = <&edma2 21 0 0>, <&edma2 22 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpuart6: serial@425a0000 {
+				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x425a0000 0x1000>;
+				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPUART6_GATE>;
+				clock-names = "ipg";
+				dmas = <&edma2 23 0 0>, <&edma2 24 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			flexcan2: can@425b0000 {
+				compatible = "fsl,imx93-flexcan", "fsl,imx8mp-flexcan";
+				reg = <0x425b0000 0x10000>;
+				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
+					 <&clk IMX93_CLK_CAN2_GATE>;
+				clock-names = "ipg", "per";
+				assigned-clocks = <&clk IMX93_CLK_CAN2>;
+				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+				assigned-clock-rates = <40000000>;
+				fsl,clk-source = /bits/ 8 <0>;
+				//fsl,stop-mode = <&gpr 0x10 4 0x10 20>;
+				status = "disabled";
+			};
+
+			flexspi: spi@425e0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "nxp,imx8mm-fspi";
+				reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
+				reg-names = "fspi_base", "fspi_mmap";
+				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_DUMMY>,
+					 <&clk IMX93_CLK_DUMMY>;
+				clock-names = "fspi", "fspi_en";
+				status = "disabled";
+			};
+
+			sai2: sai@42650000 {
+				compatible = "fsl,imx93-sai";
+				reg = <0x42650000 0x10000>;
+				interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_SAI2_IPG>, <&clk IMX93_CLK_DUMMY>,
+					 <&clk IMX93_CLK_SAI2_GATE>,
+					 <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>;
+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+				dmas = <&edma1 59 0 1>, <&edma1 58 0 0>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			sai3: sai@42660000 {
+				compatible = "fsl,imx93-sai";
+				reg = <0x42660000 0x10000>;
+				interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>,
+					 <&clk IMX93_CLK_SAI3_GATE>,
+					 <&clk IMX93_CLK_DUMMY>, <&clk IMX93_CLK_DUMMY>;
+				clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+				dmas = <&edma2 61 0 1>, <&edma2 60 0 0>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			spdif: spdif@42680000 {
+				compatible = "fsl,imx93-spdif";
+				reg = <0x42680000 0x800>,
+						<0x42680800 0x400>,
+						<0x42680c00 0x080>,
+						<0x42680e00 0x080>;
+				reg-names = "ram", "regs", "rxfifo",
+							"txfifo";
+				interrupts = /* XCVR IRQ 0 */
+							<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+							/* XCVR IRQ 1 */
+							<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+							/* XCVR PHY - SPDIF wakeup IRQ */
+				clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
+						<&clk IMX93_CLK_SPDIF_GATE>,
+						<&clk IMX93_CLK_DUMMY>,
+						<&clk IMX93_CLK_AUD_XCVR_GATE>;
+				clock-names = "ipg", "phy", "spba", "pll_ipg";
+				dmas = <&edma2 65 0 1>, <&edma2 66 0 0>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			lpuart7: serial@42690000 {
+				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x42690000 0x1000>;
+				interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPUART7_GATE>;
+				clock-names = "ipg";
+				dmas = <&edma2 87 0 0>, <&edma2 88 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpuart8: serial@426a0000 {
+				compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x426a0000 0x1000>;
+				interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPUART8_GATE>;
+				clock-names = "ipg";
+				dmas = <&edma2 89 0 0>, <&edma2 90 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpi2c5: i2c@426b0000 {
+				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+				reg = <0x426b0000 0x10000>;
+				interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPI2C5_GATE>,
+					 <&clk IMX93_CLK_LPI2C5_GATE>;
+				clock-names = "per", "ipg";
+				dmas = <&edma2 71 0 0>, <&edma2 72 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpi2c6: i2c@426c0000 {
+				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+				reg = <0x426c0000 0x10000>;
+				interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPI2C6_GATE>,
+					 <&clk IMX93_CLK_LPI2C6_GATE>;
+				clock-names = "per", "ipg";
+				dmas = <&edma2 73 0 0>, <&edma2 74 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpi2c7: i2c@426d0000 {
+				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+				reg = <0x426d0000 0x10000>;
+				interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPI2C7_GATE>,
+					 <&clk IMX93_CLK_LPI2C7_GATE>;
+				clock-names = "per", "ipg";
+				dmas = <&edma2 75 0 0>, <&edma2 76 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpi2c8: i2c@426e0000 {
+				compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
+				reg = <0x426e0000 0x10000>;
+				interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPI2C8_GATE>,
+					 <&clk IMX93_CLK_LPI2C8_GATE>;
+				clock-names = "per", "ipg";
+				dmas = <&edma2 77 0 0>, <&edma2 78 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpspi5: spi@426f0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+				reg = <0x426f0000 0x10000>;
+				interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPSPI5_GATE>,
+					 <&clk IMX93_CLK_LPSPI5_GATE>;
+				clock-names = "per", "ipg";
+				dmas = <&edma2 79 0 0>, <&edma2 80 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpspi6: spi@42700000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+				reg = <0x42700000 0x10000>;
+				interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPSPI6_GATE>,
+					 <&clk IMX93_CLK_LPSPI6_GATE>;
+				clock-names = "per", "ipg";
+				dmas = <&edma2 81 0 0>, <&edma2 82 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpspi7: spi@42710000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+				reg = <0x42710000 0x10000>;
+				interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPSPI7_GATE>,
+					 <&clk IMX93_CLK_LPSPI7_GATE>;
+				clock-names = "per", "ipg";
+				dmas = <&edma2 83 0 0>, <&edma2 84 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			lpspi8: spi@42720000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
+				reg = <0x42720000 0x10000>;
+				interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_LPSPI8_GATE>,
+					 <&clk IMX93_CLK_LPSPI8_GATE>;
+				clock-names = "per", "ipg";
+				dmas = <&edma2 85 0 0>, <&edma2 86 0 1>;
+				dma-names = "tx","rx";
+				status = "disabled";
+			};
+
+			flexio_i2c_master: flexio@425c0000 {
+				compatible = "imx,flexio_i2c_master";
+				reg = <0x425c0000 0x10000>;
+				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_FLEXIO1_GATE>,
+					 <&clk IMX93_CLK_FLEXIO1_GATE>;
+				clock-names = "per", "ipg";
+				assigned-clocks = <&clk IMX93_CLK_FLEXIO1_GATE>;
+				assigned-clock-parents = <&clk IMX93_CLK_FLEXIO1>;
+				assigned-clock-rates = <24000000>;
+				status = "disabled";
+			};
+		};
+
+		aips3: bus@42800000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			reg = <0x42800000 0x800000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			usdhc1: mmc@42850000 {
+				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
+				reg = <0x42850000 0x10000>;
+				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_DUMMY>,
+					 <&clk IMX93_CLK_DUMMY>,
+					 <&clk IMX93_CLK_USDHC1_GATE>;
+				clock-names = "ipg", "ahb", "per";
+				bus-width = <8>;
+				fsl,tuning-start-tap = <20>;
+				fsl,tuning-step= <2>;
+				status = "disabled";
+			};
+
+			usdhc2: mmc@42860000 {
+				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
+				reg = <0x42860000 0x10000>;
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_DUMMY>,
+					 <&clk IMX93_CLK_DUMMY>,
+					 <&clk IMX93_CLK_USDHC2_GATE>;
+				clock-names = "ipg", "ahb", "per";
+				bus-width = <4>;
+				fsl,tuning-start-tap = <20>;
+				fsl,tuning-step= <2>;
+				status = "disabled";
+			};
+
+			fec: ethernet@42890000 {
+				compatible = "fsl,imx93-fec", "fsl,imx8mp-fec", "fsl,imx8mq-fec";
+				reg = <0x42890000 0x10000>;
+				interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_WAKEUP_AXI>,
+					 <&clk IMX93_CLK_WAKEUP_AXI>,
+					 <&clk IMX93_CLK_ENET_TIMER1>,
+					 <&clk IMX93_CLK_ENET_REF>,
+					 <&clk IMX93_CLK_ENET_REF_PHY>;
+				clock-names = "ipg", "ahb", "ptp",
+					      "enet_clk_ref", "enet_out";
+				assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
+						  <&clk IMX93_CLK_ENET_REF>,
+						  <&clk IMX93_CLK_ENET_REF_PHY>;
+				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
+							 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,
+							 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+				assigned-clock-rates = <100000000>, <250000000>, <50000000>;
+				fsl,num-tx-queues = <3>;
+				fsl,num-rx-queues = <3>;
+				fsl,wakeup_irq = <2>;
+				status = "disabled";
+			};
+
+			eqos: ethernet@428a0000 {
+				compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
+				reg = <0x428a0000 0x10000>;
+				interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "eth_wake_irq", "macirq";
+				clocks = <&clk IMX93_CLK_WAKEUP_AXI>,
+					 <&clk IMX93_CLK_WAKEUP_AXI>,
+					 <&clk IMX93_CLK_ENET_TIMER2>,
+					 <&clk IMX93_CLK_ENET>,
+					 <&clk IMX93_CLK_WAKEUP_AXI>;
+				clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
+				assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
+						  <&clk IMX93_CLK_ENET>;
+				assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
+							 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
+				assigned-clock-rates = <100000000>, <250000000>;
+				intf_mode = <&wakeupmix_gpr 0x28>;
+				clk_csr = <0>;
+				status = "disabled";
+			};
+
+			usdhc3: mmc@428b0000 {
+				compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
+				reg = <0x428b0000 0x10000>;
+				interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_DUMMY>,
+					 <&clk IMX93_CLK_DUMMY>,
+					 <&clk IMX93_CLK_USDHC3_GATE>;
+				clock-names = "ipg", "ahb", "per";
+				bus-width = <4>;
+				fsl,tuning-start-tap = <20>;
+				fsl,tuning-step= <2>;
+				status = "disabled";
+			};
+
+			epxp: epxp@4ae20000 {
+				compatible = "fsl,imx93-pxp-dma", "fsl,imx8ulp-pxp-dma";
+				reg = <0x4ae20000 0x10000>;
+				interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX93_CLK_MEDIA_APB>,
+					 <&clk IMX93_CLK_MEDIA_AXI>;
+				clock-names = "pxp_ipg", "pxp_axi";
+				pxp-gpr = <&media_blk_ctrl>;
+				power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_PXP>;
+				status = "disabled";
+			};
+
+			cameradev: camera {
+				compatible = "fsl,mxc-md", "simple-bus";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges;
+				status = "disabled";
+
+				isi_0: isi@4ae40000{
+					compatible = "fsl,imx93-isi", "fsl,imx8-isi";
+					reg = <0x4ae40000 0x10000>;
+					interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX93_CLK_ISI_GATE>,
+						 <&clk IMX93_CLK_MEDIA_AXI>;
+					clock-names = "per", "axi";
+					assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>,
+							  <&clk IMX93_CLK_MEDIA_APB>;
+					assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>,
+								 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+					assigned-clock-rates = <400000000>, <133333333>;
+					interface = <2 0 2>;
+					no-reset-control;
+					power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_ISI>;
+					gasket = <&media_blk_ctrl>;
+					status = "disabled";
+
+					cap_device {
+						compatible = "imx-isi-capture";
+						status = "disabled";
+					};
+				};
+
+				mipi_csi: csi@4ae00000 {
+					compatible = "fsl,dwc-mipi-csi2-host";
+					reg = <0x4ae00000 0x10000>;
+					interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+					clocks = <&clk IMX93_CLK_MIPI_CSI_GATE>,
+						 <&clk IMX93_CLK_CAM_PIX>,
+						 <&clk IMX93_CLK_MIPI_PHY_CFG>;
+					clock-names = "clk_core", "clk_pixel", "phy_cfg";
+					assigned-clocks = <&clk IMX93_CLK_CAM_PIX>,
+							  <&clk IMX93_CLK_MIPI_PHY_CFG>;
+					assigned-clock-parents = <&clk IMX93_CLK_VIDEO_PLL>,
+								 <&clk IMX93_CLK_24M>;
+					assigned-clock-rates = <140000000>, <24000000>;
+					gasket = <&media_blk_ctrl>;
+					power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_CSI>;
+					status = "disabled";
+				};
+			};
+		};
+
+		gpio2: gpio@43810000 {
+				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+				reg = <0x43810080 0x1000>, <0x43810040 0x40>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				/*
+				clocks = <&clk IMX93_CLK_RGPIO2>,
+					 <&clk IMX93_CLK_PCTL2>;
+				clock-names = "gpio", "port";
+				*/
+				gpio-ranges = <&iomuxc 0 32 32>;
+		};
+
+		gpio3: gpio@43820000 {
+				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+				reg = <0x43820080 0x1000>, <0x43820040 0x40>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				/*
+				clocks = <&clk IMX93_CLK_RGPIO3>,
+					 <&clk IMX93_CLK_PCTL3>;
+				clock-names = "gpio", "port";
+				*/
+				gpio-ranges = <&iomuxc 0 64 32>;
+		};
+
+		gpio4: gpio@43830000 {
+				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+				reg = <0x43830080 0x1000>, <0x43830040 0x40>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				/*
+				clocks = <&clk IMX93_CLK_RGPIO4>,
+					 <&clk IMX93_CLK_PCTL4>;
+				clock-names = "gpio", "port";
+				*/
+				gpio-ranges = <&iomuxc 0 96 32>;
+		};
+
+		gpio1: gpio@47400000 {
+				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+				reg = <0x47400080 0x1000>, <0x47400040 0x40>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				/*
+				clocks = <&clk IMX93_CLK_RGPIO1>,
+					 <&clk IMX93_CLK_PCTL1>;
+				clock-names = "gpio", "port";
+				*/
+				gpio-ranges = <&iomuxc 0 0 32>;
+		};
+
+		ocotp: efuse@47510000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,imx93-ocotp", "syscon";
+			reg = <0x47510000 0x1000>;
+			status = "disabled";
+		};
+
+		s4muap: s4muap@47520000 {
+			compatible = "fsl,imx93-mu-s4";
+			reg = <0x47520000 0x10000>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "txirq", "rxirq";
+			#mbox-cells = <2>;
+			status = "okay";
+		};
+
+		sentnl_mu: sentnl-mu {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fsl,imx-sentnl";
+			mboxes = <&s4muap 0 0 &s4muap 1 0>;
+			mbox-names = "tx", "rx";
+			fsl,sentnl_mu_id = <2>;
+			fsl,sentnl_mu_max_users = <4>;
+			status = "okay";
+			dma-ranges = <0x80000000 0x80000000 0x20000000>;
+		};
+
+		media_blk_ctrl: blk-ctrl@4ac10000 {
+			compatible = "fsl,imx93-media-blk-ctrl", "syscon", "simple-mfd";
+			reg = <0x4ac10000 0x10000>;
+			power-domains = <&mediamix>;
+			clocks = <&clk IMX93_CLK_MEDIA_APB>,
+				 <&clk IMX93_CLK_MEDIA_AXI>,
+				 <&clk IMX93_CLK_NIC_MEDIA_GATE>,
+				 <&clk IMX93_CLK_MEDIA_DISP_PIX>,
+				 <&clk IMX93_CLK_CAM_PIX>,
+				 <&clk IMX93_CLK_PXP_GATE>,
+				 <&clk IMX93_CLK_LCDIF_GATE>,
+				 <&clk IMX93_CLK_ISI_GATE>,
+				 <&clk IMX93_CLK_MIPI_CSI_GATE>,
+				 <&clk IMX93_CLK_MIPI_DSI_GATE>;
+			clock-names = "apb", "axi", "nic", "disp", "cam",
+				      "pxp", "lcdif", "isi", "csi", "dsi";
+			#power-domain-cells = <1>;
+
+			dphy: dphy {
+				compatible = "fsl,imx93-mipi-dphy";
+				clocks = <&clk IMX93_CLK_MIPI_PHY_CFG>,
+					 <&clk IMX93_CLK_24M>;
+				clock-names = "phy_cfg", "phy_ref";
+				assigned-clocks = <&clk IMX93_CLK_MIPI_PHY_CFG>;
+				assigned-clock-parents = <&clk IMX93_CLK_24M>;
+				assigned-clock-rates = <24000000>;
+				#phy-cells = <0>;
+				power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>;
+				status = "disabled";
+			};
+		};
+
+		ldb: ldb@4ac10020 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,imx93-ldb";
+			clocks = <&clk IMX93_CLK_LVDS_GATE>;
+			clock-names = "ldb";
+			assigned-clocks = <&clk IMX93_CLK_MEDIA_LDB>;
+			assigned-clock-parents = <&clk IMX93_CLK_VIDEO_PLL>;
+			gpr = <&media_blk_ctrl>;
+			power-domains = <&mediamix>;
+			status = "disabled";
+
+			lvds-channel@0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0>;
+				phys = <&ldb_phy1>;
+				phy-names = "ldb_phy";
+				status = "disabled";
+
+				port@0 {
+					reg = <0>;
+
+					ldb_ch0: endpoint {
+						remote-endpoint = <&lcdif_to_ldb>;
+					};
+				};
+			};
+		};
+
+		ldb_phy: phy@4ac10024 {
+			compatible = "fsl,imx93-lvds-phy";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gpr = <&media_blk_ctrl>;
+			clocks = <&clk IMX93_CLK_MEDIA_APB>;
+			clock-names = "apb";
+			power-domains = <&mediamix>;
+			status = "disabled";
+
+			ldb_phy1: port@0 {
+				reg = <0>;
+				#phy-cells = <0>;
+			};
+		};
+
+		dsi: dsi@4ae10000 {
+			compatible = "fsl,imx93-mipi-dsi";
+			reg = <0x4ae10000 0x4000>;
+			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX93_CLK_MIPI_TEST_BYTE>,
+				 <&clk IMX93_CLK_MIPI_DSI_GATE>;
+			clock-names = "byte", "pclk";
+			assigned-clocks = <&clk IMX93_CLK_MIPI_TEST_BYTE>,
+					  <&clk IMX93_CLK_MEDIA_APB>;
+			assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD0>,
+						 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+			assigned-clock-rates = <20000000>, <133333334>;
+			phys = <&dphy>;
+			phy-names = "dphy";
+			power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_MIPI_DSI>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					dsi_to_lcdif: endpoint {
+						remote-endpoint = <&lcdif_to_dsi>;
+					};
+				};
+			};
+		};
+
+		lcdif: lcd-controller@4ae30000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "fsl,imx93-lcdif";
+			reg = <0x4ae30000 0x10000>;
+			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+			fsl,gpr = <&media_blk_ctrl>;
+			clocks = <&clk IMX93_CLK_MEDIA_DISP_PIX>,
+				 <&clk IMX93_CLK_MEDIA_AXI>,
+				 <&clk IMX93_CLK_LCDIF_GATE>;
+			clock-names = "pix", "disp-axi", "disp-apb";
+			assigned-clocks = <&clk IMX93_CLK_VIDEO_PLL>,
+					  <&clk IMX93_CLK_MEDIA_DISP_PIX>,
+					  <&clk IMX93_CLK_MEDIA_AXI>,
+					  <&clk IMX93_CLK_MEDIA_APB>;
+			assigned-clock-parents = <&clk IMX93_CLK_24M>,
+						 <&clk IMX93_CLK_VIDEO_PLL>,
+						 <&clk IMX93_CLK_SYS_PLL_PFD1>,
+						 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+			power-domains = <&media_blk_ctrl IMX93_MEDIABLK_PD_LCDIF>;
+			status = "disabled";
+
+			lcdif_disp: port@0 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0>;
+
+				lcdif_to_dsi: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&dsi_to_lcdif>;
+				};
+
+				lcdif_to_ldb: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&ldb_ch0>;
+				};
+			};
+		};
+
+		ddr-pmu@4e300dc0 {
+			compatible = "fsl,imx93-ddr-pmu";
+			reg = <0x4e300dc0 0x200>;
+			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		usbphynop1: usbphynop1 {
+			compatible = "usb-nop-xceiv";
+			clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
+			clock-names = "main_clk";
+		};
+
+		usbotg1: usb@4c100000 {
+			compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
+			reg = <0x4c100000 0x200>;
+			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
+			clock-names = "usb1_ctrl_root_clk";
+			assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
+			assigned-clock-parents = <&clk IMX93_CLK_HSIO>;
+			fsl,usbphy = <&usbphynop1>;
+			fsl,usbmisc = <&usbmisc1 0>;
+			status = "disabled";
+		};
+
+		usbmisc1: usbmisc@4c100200 {
+			compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
+			#index-cells = <1>;
+			reg = <0x4c100200 0x200>;
+		};
+
+		usbphynop2: usbphynop2 {
+			compatible = "usb-nop-xceiv";
+			clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
+			clock-names = "main_clk";
+		};
+
+		usbotg2: usb@4c200000 {
+			compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
+			reg = <0x4c200000 0x200>;
+			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
+			clock-names = "usb2_ctrl_root_clk";
+			assigned-clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>;
+			assigned-clock-parents = <&clk IMX93_CLK_HSIO>;
+			fsl,usbphy = <&usbphynop2>;
+			fsl,usbmisc = <&usbmisc2 0>;
+			status = "disabled";
+		};
+
+		usbmisc2: usbmisc@4c200200 {
+			compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
+			#index-cells = <1>;
+			reg = <0x4c200200 0x200>;
+		};
+	};
+
+	display-subsystem {
+		compatible = "fsl,imx-display-subsystem";
+		ports = <&lcdif_disp>;
+	};
+};
diff --git a/arch/arm/dts/ls1021a-twr-u-boot.dtsi b/arch/arm/dts/ls1021a-twr-u-boot.dtsi
new file mode 100644
index 00000000000..3711e424199
--- /dev/null
+++ b/arch/arm/dts/ls1021a-twr-u-boot.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2022 NXP
+ */
+
+&{/soc} {
+	u-boot,dm-spl;
+	u-boot,dm-pre-reloc;
+};
+
+&crypto {
+	u-boot,dm-spl;
+};
+
+&sec_jr0 {
+	u-boot,dm-spl;
+};
+
+&sec_jr1 {
+	u-boot,dm-spl;
+};
+
+&sec_jr2 {
+	u-boot,dm-spl;
+};
+
+&sec_jr3 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/ls1021a-twr.dtsi b/arch/arm/dts/ls1021a-twr.dtsi
index bf96af7e360..82df2f11bb9 100644
--- a/arch/arm/dts/ls1021a-twr.dtsi
+++ b/arch/arm/dts/ls1021a-twr.dtsi
@@ -6,6 +6,7 @@
  */
 
 #include "ls1021a.dtsi"
+#include "ls1021a-twr-u-boot.dtsi"
 
 / {
 	model = "LS1021A TWR Board";
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 86192cbb7f3..be330c130f5 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -3,6 +3,7 @@
  * Freescale ls1021a SOC common device tree source
  *
  * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include "skeleton.dtsi"
@@ -144,6 +145,45 @@
 			big-endian;
 		};
 
+		crypto: crypto@1700000 {
+			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+			fsl,sec-era = <7>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg		 = <0x1700000 0x100000>;
+			ranges		 = <0x0 0x1700000 0x100000>;
+			interrupts	 = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+
+			sec_jr0: jr@10000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+				reg = <0x10000 0x10000>;
+				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr1: jr@20000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+				reg = <0x20000 0x10000>;
+				interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr2: jr@30000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+				reg = <0x30000 0x10000>;
+				interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr3: jr@40000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+				     "fsl,sec-v4.0-job-ring";
+				reg = <0x40000 0x10000>;
+				interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+		};
+
 		clockgen: clocking@1ee1000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index fe963789710..f326c903126 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2018-2020 NXP
  */
 
 #define MXC_CPU_MX23		0x23
@@ -47,9 +48,11 @@
 #define MXC_CPU_IMX8MP6		0x186 /* dummy ID */
 #define MXC_CPU_IMX8MPL		0x187 /* dummy ID */
 #define MXC_CPU_IMX8MPD		0x188 /* dummy ID */
+#define MXC_CPU_IMX8MPUL	0x189 /* dummy ID */
 #define MXC_CPU_IMX8QXP_A0	0x90 /* dummy ID */
 #define MXC_CPU_IMX8QM		0x91 /* dummy ID */
 #define MXC_CPU_IMX8QXP		0x92 /* dummy ID */
+#define MXC_CPU_IMX8DXL     0x9E /* dummy ID */
 
 #define MXC_CPU_IMX8ULP		0xA1 /* dummy ID */
 
@@ -58,6 +61,7 @@
 
 #define MXC_CPU_MX7ULP		0xE1 /* Temporally hard code */
 #define MXC_CPU_VF610		0xF6 /* dummy ID */
+#define MXC_CPU_IMX93		0xC1 /* dummy ID */
 
 #define MXC_SOC_MX6		0x60
 #define MXC_SOC_MX7		0x70
@@ -65,6 +69,7 @@
 #define MXC_SOC_IMX8		0x90 /* dummy */
 #define MXC_SOC_IMXRT		0xB0 /* dummy */
 #define MXC_SOC_MX7ULP		0xE0 /* dummy */
+#define MXC_SOC_IMX9		0xC0 /* dummy */
 
 #define CHIP_REV_1_0            0x10
 #define CHIP_REV_1_1            0x11
@@ -80,6 +85,8 @@
 #define CHIP_REV_A		0x0
 #define CHIP_REV_B		0x1
 #define CHIP_REV_C		0x2
+#define CHIP_REV_A1		0x11
+#define CHIP_REV_A2		0x12
 
 #define BOARD_REV_1_0           0x0
 #define BOARD_REV_2_0           0x1
diff --git a/arch/arm/include/asm/arch-imx8/clock.h b/arch/arm/include/asm/arch-imx8/clock.h
index bea157171fb..4435259d610 100644
--- a/arch/arm/include/asm/arch-imx8/clock.h
+++ b/arch/arm/include/asm/arch-imx8/clock.h
@@ -23,5 +23,13 @@ enum mxc_clock {
 };
 
 u32 mxc_get_clock(enum mxc_clock clk);
+u32 get_lpuart_clk(void);
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
+u32 imx_get_i2cclk(unsigned i2c_num);
+void enable_usboh3_clk(unsigned char enable);
+u32 imx_get_fecclk(void);
+void init_clk_usdhc(u32 index);
+void init_clk_gpmi_nand(void);
+void init_clk_usb3(int index);
 
 #endif /* __ASM_ARCH_IMX8_CLOCK_H__ */
diff --git a/arch/arm/include/asm/arch-imx8/i2c.h b/arch/arm/include/asm/arch-imx8/i2c.h
new file mode 100644
index 00000000000..ea2b83ee7e9
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/i2c.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2017-2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ */
+#ifndef __ASM_ARCH_IMX8_I2C_H__
+#define __ASM_ARCH_IMX8_I2C_H__
+
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/lpcg.h>
+
+struct imx_i2c_map {
+	unsigned index;
+	sc_rsrc_t rsrc;
+	u32 lpcg[4];
+};
+
+static struct imx_i2c_map imx_i2c_desc[] = {
+	{0, SC_R_I2C_0, {LPI2C_0_LPCG}},
+	{1, SC_R_I2C_1, {LPI2C_1_LPCG}},
+	{2, SC_R_I2C_2, {LPI2C_2_LPCG}},
+	{3, SC_R_I2C_3, {LPI2C_3_LPCG}},
+#ifdef CONFIG_IMX8QM
+	{4, SC_R_I2C_4, {LPI2C_4_LPCG}},
+	{5, SC_R_LVDS_0_I2C_0, {DI_LVDS_0_LPCG + 0x10}}, /* lvds0 i2c0 */
+	{6, SC_R_LVDS_0_I2C_1, {DI_LVDS_0_LPCG + 0x14}}, /* lvds0 i2c1 */
+	{7, SC_R_LVDS_1_I2C_0, {DI_LVDS_1_LPCG + 0x10}}, /* lvds1 i2c0 */
+	{8, SC_R_LVDS_1_I2C_1, {DI_LVDS_1_LPCG + 0x14}}, /* lvds1 i2c1 */
+#endif
+	{9, SC_R_CSI_0_I2C_0, {MIPI_CSI_0_LPCG + 0x14}},
+#ifdef CONFIG_IMX8QM
+	{10, SC_R_CSI_1_I2C_0, {MIPI_CSI_1_LPCG + 0x14}},
+	{11, SC_R_HDMI_I2C_0, {DI_HDMI_LPCG}},
+	{12, SC_R_HDMI_RX_I2C_0, {RX_HDMI_LPCG + 0x10, RX_HDMI_LPCG + 0x14, RX_HDMI_LPCG + 0x18, RX_HDMI_LPCG + 0x1C}},
+	{13, SC_R_MIPI_0_I2C_0, {MIPI_DSI_0_LPCG + 0x14, MIPI_DSI_0_LPCG + 0x18, MIPI_DSI_0_LPCG + 0x1c}},
+	{14, SC_R_MIPI_0_I2C_1, {MIPI_DSI_0_LPCG + 0x24, MIPI_DSI_0_LPCG + 0x28, MIPI_DSI_0_LPCG + 0x2c}},
+	{15, SC_R_MIPI_1_I2C_0, {MIPI_DSI_1_LPCG + 0x14, MIPI_DSI_1_LPCG + 0x18, MIPI_DSI_1_LPCG + 0x1c}},
+	{16, SC_R_MIPI_1_I2C_1, {MIPI_DSI_1_LPCG + 0x24, MIPI_DSI_1_LPCG + 0x28, MIPI_DSI_1_LPCG + 0x2c}},
+#else
+	{13, SC_R_MIPI_0_I2C_0, {DI_MIPI0_LPCG + 0x10}},
+	{14, SC_R_MIPI_0_I2C_1, {DI_MIPI0_LPCG + 0x14}},
+	{15, SC_R_MIPI_1_I2C_0, {DI_MIPI1_LPCG + 0x10}},
+	{16, SC_R_MIPI_1_I2C_1, {DI_MIPI1_LPCG + 0x14}},
+#endif
+};
+#endif /* __ASM_ARCH_IMX8_I2C_H__ */
diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h
index ed6e05e5569..b55bdcfe45d 100644
--- a/arch/arm/include/asm/arch-imx8/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8/imx-regs.h
@@ -1,11 +1,13 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  */
 
 #ifndef __ASM_ARCH_IMX8_REGS_H__
 #define __ASM_ARCH_IMX8_REGS_H__
 
+#include <asm/mach-imx/regs-lcdif.h>
+
 #define ARCH_MXC
 
 #define LPUART_BASE		0x5A060000
@@ -35,6 +37,13 @@
 #define MIPI1_SS_BASE		0x56240000
 #endif
 
+#ifdef CONFIG_IMX8QM
+#define LVDS0_PHYCTRL_BASE 0x56241000
+#define LVDS1_PHYCTRL_BASE 0x57241000
+#define MIPI0_SS_BASE 0x56220000
+#define MIPI1_SS_BASE 0x57220000
+#endif
+
 #define APBH_DMA_ARB_BASE_ADDR	0x5B810000
 #define APBH_DMA_ARB_END_ADDR	0x5B81FFFF
 #define MXS_APBH_BASE		APBH_DMA_ARB_BASE_ADDR
@@ -46,5 +55,88 @@
 
 #define USB_BASE_ADDR		0x5b0d0000
 #define USB_PHY0_BASE_ADDR	0x5b100000
+#define USB_PHY1_BASE_ADDR	0x5b110000
+
+#define CAAM_ARB_BASE_ADDR      (0x31800000)
+#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#include <stdbool.h>
+
+bool is_usb_boot(void);
+void disconnect_from_pc(void);
+#define is_boot_from_usb  is_usb_boot
+
+struct usbphy_regs {
+	u32	usbphy_pwd;			/* 0x000 */
+	u32	usbphy_pwd_set;			/* 0x004 */
+	u32	usbphy_pwd_clr;			/* 0x008 */
+	u32	usbphy_pwd_tog;			/* 0x00c */
+	u32	usbphy_tx;			/* 0x010 */
+	u32	usbphy_tx_set;			/* 0x014 */
+	u32	usbphy_tx_clr;			/* 0x018 */
+	u32	usbphy_tx_tog;			/* 0x01c */
+	u32	usbphy_rx;			/* 0x020 */
+	u32	usbphy_rx_set;			/* 0x024 */
+	u32	usbphy_rx_clr;			/* 0x028 */
+	u32	usbphy_rx_tog;			/* 0x02c */
+	u32	usbphy_ctrl;			/* 0x030 */
+	u32	usbphy_ctrl_set;		/* 0x034 */
+	u32	usbphy_ctrl_clr;		/* 0x038 */
+	u32	usbphy_ctrl_tog;		/* 0x03c */
+	u32	usbphy_status;			/* 0x040 */
+	u32	reserved0[3];
+	u32	usbphy_debug0;			/* 0x050 */
+	u32	usbphy_debug0_set;		/* 0x054 */
+	u32	usbphy_debug0_clr;		/* 0x058 */
+	u32	usbphy_debug0_tog;		/* 0x05c */
+	u32	reserved1[4];
+	u32	usbphy_debug1;			/* 0x070 */
+	u32	usbphy_debug1_set;		/* 0x074 */
+	u32	usbphy_debug1_clr;		/* 0x078 */
+	u32	usbphy_debug1_tog;		/* 0x07c */
+	u32	usbphy_version;			/* 0x080 */
+	u32	reserved2[7];
+	u32	usb1_pll_480_ctrl;		/* 0x0a0 */
+	u32	usb1_pll_480_ctrl_set;		/* 0x0a4 */
+	u32	usb1_pll_480_ctrl_clr;		/* 0x0a8 */
+	u32	usb1_pll_480_ctrl_tog;		/* 0x0ac */
+	u32	reserved3[4];
+	u32	usb1_vbus_detect;		/* 0xc0 */
+	u32	usb1_vbus_detect_set;		/* 0xc4 */
+	u32	usb1_vbus_detect_clr;		/* 0xc8 */
+	u32	usb1_vbus_detect_tog;		/* 0xcc */
+	u32	usb1_vbus_det_stat;		/* 0xd0 */
+	u32	reserved4[3];
+	u32	usb1_chrg_detect;		/* 0xe0 */
+	u32	usb1_chrg_detect_set;		/* 0xe4 */
+	u32	usb1_chrg_detect_clr;		/* 0xe8 */
+	u32	usb1_chrg_detect_tog;		/* 0xec */
+	u32	usb1_chrg_det_stat;		/* 0xf0 */
+	u32	reserved5[3];
+	u32	usbphy_anactrl;			/* 0x100 */
+	u32	usbphy_anactrl_set;		/* 0x104 */
+	u32	usbphy_anactrl_clr;		/* 0x108 */
+	u32	usbphy_anactrl_tog;		/* 0x10c */
+	u32	usb1_loopback;			/* 0x110 */
+	u32	usb1_loopback_set;		/* 0x114 */
+	u32	usb1_loopback_clr;		/* 0x118 */
+	u32	usb1_loopback_tog;		/* 0x11c */
+	u32	usb1_loopback_hsfscnt;		/* 0x120 */
+	u32	usb1_loopback_hsfscnt_set;	/* 0x124 */
+	u32	usb1_loopback_hsfscnt_clr;	/* 0x128 */
+	u32	usb1_loopback_hsfscnt_tog;	/* 0x12c */
+	u32	usphy_trim_override_en;		/* 0x130 */
+	u32	usphy_trim_override_en_set;	/* 0x134 */
+	u32	usphy_trim_override_en_clr;	/* 0x138 */
+	u32	usphy_trim_override_en_tog;	/* 0x13c */
+	u32	usb1_pfda_ctrl1;		/* 0x140 */
+	u32	usb1_pfda_ctrl1_set;		/* 0x144 */
+	u32	usb1_pfda_ctrl1_clr;		/* 0x148 */
+	u32	usb1_pfda_ctrl1_tog;		/* 0x14c */
+};
+#endif
 
 #endif /* __ASM_ARCH_IMX8_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-imx8/imx8-pins.h b/arch/arm/include/asm/arch-imx8/imx8-pins.h
index 2130298163a..6b1123b1079 100644
--- a/arch/arm/include/asm/arch-imx8/imx8-pins.h
+++ b/arch/arm/include/asm/arch-imx8/imx8-pins.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
  */
 
 #ifndef __ASM_ARCH_IMX8_PINS_H__
@@ -10,6 +10,8 @@
 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
 #elif defined(CONFIG_IMX8QM)
 #include <dt-bindings/pinctrl/pads-imx8qm.h>
+#elif defined(CONFIG_IMX8DXL)
+#include <dt-bindings/pinctrl/pads-imx8dxl.h>
 #else
 #error "No pin header"
 #endif
diff --git a/arch/arm/include/asm/arch-imx8/imx8_lvds.h b/arch/arm/include/asm/arch-imx8/imx8_lvds.h
new file mode 100644
index 00000000000..68fbf6d41e6
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/imx8_lvds.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _IMX8_LVDS_H_
+#define _IMX8_LVDS_H_
+
+#define IMX_LVDS_SET_FIELD(__field__, __value__) (((__value__) << (__field__ ## _SHIFT)) & (__field__ ## _MASK))
+#define IMX_LVDS_GET_FIELD(__field__, __reg__) (((__reg__) & (__field__ ## _MASK)) >> (__field__  ## _SHIFT))
+
+#define IMX_LVDS_SET(__reg__)   (reg+0x4)
+#define IMX_LVDS_CLEAR(__reg__) (reg+0x8)
+#define IMX_LVDS_TOGGLE(__reg__)(reg+0x4)
+
+#define LVDS_CTRL                     0x0e0
+#define LVDS_CTRL_CH0_MODE_MASK       0x03U
+#define LVDS_CTRL_CH0_MODE_SHIFT      0U
+#define LVDS_CTRL_CH0_MODE__DISABLED  0x00U
+#define LVDS_CTRL_CH0_MODE__DI0       0x01U
+#define LVDS_CTRL_CH0_MODE__RESERVED  0x02U
+#define LVDS_CTRL_CH0_MODE__DI1       0x03U
+
+#define LVDS_CTRL_CH1_MODE_MASK       0x0cU
+#define LVDS_CTRL_CH1_MODE_SHIFT      2U
+#define LVDS_CTRL_CH1_MODE__DISABLED  0x00U
+#define LVDS_CTRL_CH1_MODE__DI0       0x01U
+#define LVDS_CTRL_CH1_MODE__RESERVED  0x02U
+#define LVDS_CTRL_CH1_MODE__DI1       0x03U
+
+#define LVDS_CTRL_SPLIT_MODE_MASK      0x10U
+#define LVDS_CTRL_SPLIT_MODE_SHIFT     4U
+#define LVDS_CTRL_SPLIT_MODE__DISABLE  0x00U
+#define LVDS_CTRL_SPLIT_MODE__ENABLE   0x01U
+
+#define LVDS_CTRL_CH0_DATA_WIDTH_MASK   0x20U
+#define LVDS_CTRL_CH0_DATA_WIDTH_SHIFT  5U
+#define LVDS_CTRL_CH0_DATA_WIDTH__18BIT 0x00U
+#define LVDS_CTRL_CH0_DATA_WIDTH__24BIT 0x01U
+
+#define LVDS_CTRL_CH0_BIT_MAP_MASK   0x40U
+#define LVDS_CTRL_CH0_BIT_MAP_SHIFT  6U
+#define LVDS_CTRL_CH0_BIT_MAP__SWWG  0x00U
+#define LVDS_CTRL_CH0_BIT_MAP__JEIDA 0x01U
+
+#define LVDS_CTRL_CH1_DATA_WIDTH_MASK   0x80U
+#define LVDS_CTRL_CH1_DATA_WIDTH_SHIFT  7U
+#define LVDS_CTRL_CH1_DATA_WIDTH__18BIT 0x00U
+#define LVDS_CTRL_CH1_DATA_WIDTH__24BIT 0x01U
+
+#define LVDS_CTRL_CH1_BIT_MAP_MASK  0x100U
+#define LVDS_CTRL_CH1_BIT_MAP_SHIFT  8U
+#define LVDS_CTRL_CH1_BIT_MAP__SWWG  0x00U
+#define LVDS_CTRL_CH1_BIT_MAP__JEIDA 0x01U
+
+#define LVDS_CTRL_DI0_VSYNC_POL_MASK        0x200U
+#define LVDS_CTRL_DI0_VSYNC_POL_SHIFT        9U
+#define LVDS_CTRL_DI0_VSYNC_POL__ACTIVE_LOW  0x00U
+#define LVDS_CTRL_DI0_VSYNC_POL__ACTIVE_HIGH 0x01U
+
+#define LVDS_CTRL_DI1_VSYNC_POL_MASK        0x400U
+#define LVDS_CTRL_DI1_VSYNC_POL_SHIFT        10U
+#define LVDS_CTRL_DI1_VSYNC_POL__ACTIVE_LOW  0x00U
+#define LVDS_CTRL_DI1_VSYNC_POL__ACTIVE_HIGH 0x01U
+
+#define LVDS_CTRL_CH0_10BIT_ENABLE_MASK         0x400000U
+#define LVDS_CTRL_CH0_10BIT_ENABLE_SHIFT           22U
+#define LVDS_CTRL_CH0_10BIT_ENABLE__USE_DATA_WIDTH 0x00U
+#define LVDS_CTRL_CH0_10BIT_ENABLE__10BIT          0x01U
+
+#define LVDS_CTRL_CH1_10BIT_ENABLE_MASK         0x800000U
+#define LVDS_CTRL_CH1_10BIT_ENABLE_SHIFT           23U
+#define LVDS_CTRL_CH1_10BIT_ENABLE__USE_DATA_WIDTH 0x00U
+#define LVDS_CTRL_CH1_10BIT_ENABLE__10BIT          0x01U
+
+#define LVDS_CTRL_DI0_DATA_WIDTH_MASK         0x03000000U
+#define LVDS_CTRL_DI0_DATA_WIDTH_SHIFT        24U
+#define LVDS_CTRL_DI0_DATA_WIDTH__USE_18BIT   0x00U
+#define LVDS_CTRL_DI0_DATA_WIDTH__USE_24BIT   0x1U
+#define LVDS_CTRL_DI0_DATA_WIDTH__USE_30BIT   0x2U
+
+#define LVDS_CTRL_DI1_DATA_WIDTH_MASK         0x0C000000U
+#define LVDS_CTRL_DI1_DATA_WIDTH_SHIFT        26U
+#define LVDS_CTRL_DI1_DATA_WIDTH__USE_18BIT   0x00U
+#define LVDS_CTRL_DI1_DATA_WIDTH__USE_24BIT   0x1U
+#define LVDS_CTRL_DI1_DATA_WIDTH__USE_30BIT   0x2U
+
+#define LVDS_PHY_CTRL	       (0x0)
+
+#define LVDS_PHY_CTRL_PD_MASK       (1<<0)
+#define LVDS_PHY_CTRL_PD_SHIFT      (0)
+#define LVDS_PHY_CTRL_RFB_MASK      (1<<1)
+#define LVDS_PHY_CTRL_RFB_SHIFT     (1)
+#define LVDS_PHY_CTRL_NB_MASK       (1<<2)
+#define LVDS_PHY_CTRL_NB_SHIFT      (2)
+#define LVDS_PHY_CTRL_CH0_EN_MASK   (1<<3)
+#define LVDS_PHY_CTRL_CH0_EN_SHIFT  (3)
+#define LVDS_PHY_CTRL_CH1_EN_MASK   (1<<4)
+#define LVDS_PHY_CTRL_CH1_EN_SHIFT  (4)
+
+#define LVDS_PHY_CTRL_TST_MASK      (0x3f<<5)
+#define LVDS_PHY_CTRL_TST_SHIFT     (5)
+
+#define LVDS_PHY_CTRL_CA_MASK       (0x7<<11)
+#define LVDS_PHY_CTRL_CA_SHIFT      (11)
+
+#define LVDS_PHY_CTRL_CCM_MASK      (0x7<<14)
+#define LVDS_PHY_CTRL_CCM_SHIFT     (14)
+
+#define LVDS_PHY_CTRL_M_MASK        (0x3<<17)
+#define LVDS_PHY_CTRL_M_SHIFT       (17)
+
+#endif	/* _IMX8_LVDS_H_ */
diff --git a/arch/arm/include/asm/arch-imx8/imx8_mipi_dsi.h b/arch/arm/include/asm/arch-imx8/imx8_mipi_dsi.h
new file mode 100644
index 00000000000..63024f3fc5f
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/imx8_mipi_dsi.h
@@ -0,0 +1,394 @@
+/*
+ * Copyright 2015-2017 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _IMX8_MIPI_DSI_H_
+#define _IMX8_MIPI_DSI_H_
+
+#define MIPI_CSR_OFFSET 0x1000 /* Subsystem Control Status Registers (CSR) */
+#define MIPI_CSR_TX_ULPS  0x0
+#define MIPIv2_CSR_TX_ULPS  0x30
+#define MIPI_CSR_TX_ULPS_VALUE  0x1F
+
+#define MIPI_CSR_PXL2DPI         0x4
+#define MIPIv2_CSR_PXL2DPI         0x40
+
+#define MIPI_CSR_PXL2DPI_16_BIT_PACKED       0x0
+#define MIPI_CSR_PXL2DPI_16_BIT_565_ALIGNED  0x1
+#define MIPI_CSR_PXL2DPI_16_BIT_565_SHIFTED  0x2
+#define MIPI_CSR_PXL2DPI_18_BIT_PACKED       0x3
+#define MIPI_CSR_PXL2DPI_18_BIT_ALIGNED      0x4
+#define MIPI_CSR_PXL2DPI_24_BIT              0x5
+
+#define	DSI_CMD_BUF_MAXSIZE         (128)
+
+#define MIPI_DSI_OFFSET 0x8000 /* MIPI DSI Controller */
+
+/* DPI interface pixel color coding map */
+enum mipi_dsi_dpi_fmt {
+	MIPI_RGB565_PACKED = 0,
+	MIPI_RGB565_LOOSELY,
+	MIPI_RGB565_CONFIG3,
+	MIPI_RGB666_PACKED,
+	MIPI_RGB666_LOOSELY,
+	MIPI_RGB888,
+};
+
+struct mipi_dsi_context {
+	char *NAME;
+	uint32_t REGS_BASE;
+	uint32_t CSR_REGS_BASE;
+};
+
+struct dsi_cfg_csr_object {
+	uint32_t dsi_host_cfg_num_lanes;
+	uint32_t dsi_host_cfg_noncont_clk;
+	uint32_t dsi_host_cfg_t_pre;
+	uint32_t dsi_host_cfg_t_post;
+	uint32_t dsi_host_cfg_tx_gap;
+	uint32_t dsi_host_cfg_autoinsert_eotp;
+	uint32_t dsi_host_cfg_extrcmd_after_eotp;
+	uint32_t dsi_host_cfg_htx_to_cnt;
+	uint32_t dsi_host_cfg_lrx_h_to_cnt;
+	uint32_t dsi_host_cfg_bta_h_to_cnt;
+	uint32_t dsi_host_cfg_twakeup;
+};
+
+struct dsi_cfg_dpi_object {
+	uint32_t dsi_host_cfg_dpi_pxl_payld_size;
+	uint32_t dsi_host_cfg_dpi_pxl_fifo_send_lev;
+	uint32_t dsi_host_cfg_dpi_if_color_coding;
+	uint32_t dsi_host_cfg_dpi_pxl_format;
+	uint32_t dsi_host_cfg_dpi_vsync_pol;
+	uint32_t dsi_host_cfg_dpi_hsync_pol;
+	uint32_t dsi_host_cfg_dpi_video_mode;
+	uint32_t dsi_host_cfg_dpi_hfp;
+	uint32_t dsi_host_cfg_dpi_hbp;
+	uint32_t dsi_host_cfg_dpi_hsa;
+	uint32_t dsi_host_cfg_dpi_en_mult_pkt;
+	uint32_t dsi_host_cfg_dpi_vbp;
+	uint32_t dsi_host_cfg_dpi_vfp;
+	uint32_t dsi_host_cfg_dpi_bllp_mode;
+	uint32_t dsi_host_cfg_dpi_null_pkt_bllp;
+	uint32_t dsi_host_cfg_dpi_vactive;
+	uint32_t dsi_host_cfg_dpi_vc;
+};
+
+struct dsi_cfg_pkt_object {
+	uint32_t dsi_host_pkt_ctrl;
+	uint32_t dsi_host_send_pkt;
+	uint32_t dsi_host_irq_mask;
+	uint32_t dsi_host_irq_mask2;
+};
+
+struct dsi_cfg_dphy_object {
+	uint32_t dphy_pd_tx;
+	uint32_t dphy_m_prg_hs_prepare;
+	uint32_t dphy_mc_prg_hs_prepare;
+	uint32_t dphy_m_prg_hs_zero;
+	uint32_t dphy_mc_prg_hs_zero;
+	uint32_t dphy_m_prg_hs_trial;
+	uint32_t dphy_mc_prg_hs_trial;
+	uint32_t dphy_pd_pll;
+	uint32_t dphy_tst;
+	uint32_t dphy_cn;
+	uint32_t dphy_cm;
+	uint32_t dphy_co;
+	uint32_t dphy_lock;
+	uint32_t dphy_lock_byp;
+	uint32_t dphy_tx_rcal;
+	uint32_t dphy_auto_pd_en;
+	uint32_t dphy_rxlprp;
+	uint32_t dphy_rxcdrp;
+};
+
+/* dphy */
+#define DPHY_PD_TX			0x300
+#define DPHY_M_PRG_HS_PREPARE		0x304
+#define DPHY_MC_PRG_HS_PREPARE		0x308
+#define DPHY_M_PRG_HS_ZERO		0x30c
+#define DPHY_MC_PRG_HS_ZERO		0x310
+#define DPHY_M_PRG_HS_TRAIL		0x314
+#define DPHY_MC_PRG_HS_TRAIL		0x318
+#define DPHY_PD_PLL			0x31c
+#define DPHY_TST			0x320
+#define DPHY_CN				0x324
+#define DPHY_CM				0x328
+#define DPHY_CO				0x32c
+#define DPHY_LOCK			0x330
+#define DPHY_LOCK_BYP			0x334
+#define DPHY_RTERM_SEL			0x338
+#define DPHY_AUTO_PD_EN			0x33c
+#define DPHY_RXLPRP			0x340
+#define DPHY_RXCDRP			0x344
+
+/* host */
+#define HOST_CFG_NUM_LANES		0x0
+#define HOST_CFG_NONCONTINUOUS_CLK	0x4
+#define HOST_CFG_T_PRE			0x8
+#define HOST_CFG_T_POST			0xc
+#define HOST_CFG_TX_GAP			0x10
+#define HOST_CFG_AUTOINSERT_EOTP	0x14
+#define HOST_CFG_EXTRA_CMDS_AFTER_EOTP	0x18
+#define HOST_CFG_HTX_TO_COUNT		0x1c
+#define HOST_CFG_LRX_H_TO_COUNT		0x20
+#define HOST_CFG_BTA_H_TO_COUNT		0x24
+#define HOST_CFG_TWAKEUP		0x28
+#define HOST_CFG_STATUS_OUT		0x2c
+#define HOST_RX_ERROR_STATUS		0x30
+
+/* dpi */
+#define DPI_PIXEL_PAYLOAD_SIZE		0x200
+#define DPI_PIXEL_FIFO_SEND_LEVEL	0x204
+#define DPI_INTERFACE_COLOR_CODING	0x208
+#define DPI_PIXEL_FORMAT		0x20c
+#define DPI_VSYNC_POLARITY		0x210
+#define DPI_HSYNC_POLARITY		0x214
+#define DPI_VIDEO_MODE			0x218
+#define DPI_HFP				0x21c
+#define DPI_HBP				0x220
+#define DPI_HSA				0x224
+#define DPI_ENABLE_MULT_PKTS		0x228
+#define DPI_VBP				0x22c
+#define DPI_VFP				0x230
+#define DPI_BLLP_MODE			0x234
+#define DPI_USE_NULL_PKT_BLLP		0x238
+#define DPI_VACTIVE			0x23c
+#define DPI_VC				0x240
+
+/* apb pkt */
+#define HOST_TX_PAYLOAD			0x280
+
+#define HOST_PKT_CONTROL		0x284
+#define HOST_PKT_CONTROL_WC(x)		(((x) & 0xffff) << 0)
+#define HOST_PKT_CONTROL_VC(x)		(((x) & 0x3) << 16)
+#define HOST_PKT_CONTROL_DT(x)		(((x) & 0x3f) << 18)
+#define HOST_PKT_CONTROL_HS_SEL(x)	(((x) & 0x1) << 24)
+#define HOST_PKT_CONTROL_BTA_TX(x)	(((x) & 0x1) << 25)
+#define HOST_PKT_CONTROL_BTA_NO_TX(x)	(((x) & 0x1) << 26)
+
+#define HOST_SEND_PACKET		0x288
+#define HOST_PKT_STATUS			0x28c
+#define HOST_PKT_FIFO_WR_LEVEL		0x290
+#define HOST_PKT_FIFO_RD_LEVEL		0x294
+#define HOST_PKT_RX_PAYLOAD		0x298
+
+#define HOST_PKT_RX_PKT_HEADER		0x29c
+#define HOST_PKT_RX_PKT_HEADER_WC(x)	(((x) & 0xffff) << 0)
+#define HOST_PKT_RX_PKT_HEADER_DT(x)	(((x) & 0x3f) << 16)
+#define HOST_PKT_RX_PKT_HEADER_VC(x)	(((x) & 0x3) << 22)
+
+#define HOST_IRQ_STATUS			0x2a0
+#define HOST_IRQ_STATUS_SM_NOT_IDLE			(1 << 0)
+#define HOST_IRQ_STATUS_TX_PKT_DONE			(1 << 1)
+#define HOST_IRQ_STATUS_DPHY_DIRECTION			(1 << 2)
+#define HOST_IRQ_STATUS_TX_FIFO_OVFLW			(1 << 3)
+#define HOST_IRQ_STATUS_TX_FIFO_UDFLW			(1 << 4)
+#define HOST_IRQ_STATUS_RX_FIFO_OVFLW			(1 << 5)
+#define HOST_IRQ_STATUS_RX_FIFO_UDFLW			(1 << 6)
+#define HOST_IRQ_STATUS_RX_PKT_HDR_RCVD			(1 << 7)
+#define HOST_IRQ_STATUS_RX_PKT_PAYLOAD_DATA_RCVD	(1 << 8)
+#define HOST_IRQ_STATUS_HOST_BTA_TIMEOUT		(1 << 29)
+#define HOST_IRQ_STATUS_LP_RX_TIMEOUT			(1 << 30)
+#define HOST_IRQ_STATUS_HS_TX_TIMEOUT			(1 << 31)
+
+#define HOST_IRQ_STATUS2		0x2a4
+#define HOST_IRQ_STATUS2_SINGLE_BIT_ECC_ERR		(1 << 0)
+#define HOST_IRQ_STATUS2_MULTI_BIT_ECC_ERR		(1 << 1)
+#define HOST_IRQ_STATUS2_CRC_ERR			(1 << 2)
+
+#define HOST_IRQ_MASK			0x2a8
+#define HOST_IRQ_MASK_SM_NOT_IDLE_MASK			(1 << 0)
+#define HOST_IRQ_MASK_TX_PKT_DONE_MASK			(1 << 1)
+#define HOST_IRQ_MASK_DPHY_DIRECTION_MASK		(1 << 2)
+#define HOST_IRQ_MASK_TX_FIFO_OVFLW_MASK		(1 << 3)
+#define HOST_IRQ_MASK_TX_FIFO_UDFLW_MASK		(1 << 4)
+#define HOST_IRQ_MASK_RX_FIFO_OVFLW_MASK		(1 << 5)
+#define HOST_IRQ_MASK_RX_FIFO_UDFLW_MASK		(1 << 6)
+#define HOST_IRQ_MASK_RX_PKT_HDR_RCVD_MASK		(1 << 7)
+#define HOST_IRQ_MASK_RX_PKT_PAYLOAD_DATA_RCVD_MASK	(1 << 8)
+#define HOST_IRQ_MASK_HOST_BTA_TIMEOUT_MASK		(1 << 29)
+#define HOST_IRQ_MASK_LP_RX_TIMEOUT_MASK		(1 << 30)
+#define HOST_IRQ_MASK_HS_TX_TIMEOUT_MASK		(1 << 31)
+
+#define HOST_IRQ_MASK2			0x2ac
+#define HOST_IRQ_MASK2_SINGLE_BIT_ECC_ERR_MASK		(1 << 0)
+#define HOST_IRQ_MASK2_MULTI_BIT_ECC_ERR_MASK		(1 << 1)
+#define HOST_IRQ_MASK2_CRC_ERR_MASK			(1 << 2)
+
+/* ------------------------------------- end -------------------------------- */
+#define BITSLICE(x, a, b) (((x) >> (b)) & ((1 << ((a)-(b)+1)) - 1))
+
+#ifdef DEBUG
+#define W32(reg, val) \
+do {printf("%s():%d reg 0x%p  val 0x%08x\n",\
+		   __func__, __LINE__, reg, val);\
+		__raw_writel(val, reg); } while (0)
+#else
+#define W32(reg, val) __raw_writel(val, reg)
+#endif
+
+#define R32(reg) __raw_readl(reg)
+
+/* helper functions */
+inline void dsi_host_ctrl_csr_setup(void __iomem *base,
+	struct dsi_cfg_csr_object *dsi_config,
+	uint16_t csr_setup_mask)
+{
+	if (BITSLICE(csr_setup_mask, 0, 0))
+		W32(base + HOST_CFG_NUM_LANES,
+			dsi_config->dsi_host_cfg_num_lanes);
+	if (BITSLICE(csr_setup_mask, 1, 1))
+		W32(base + HOST_CFG_NONCONTINUOUS_CLK,
+			dsi_config->dsi_host_cfg_noncont_clk);
+	if (BITSLICE(csr_setup_mask, 2, 2))
+		W32(base + HOST_CFG_T_PRE, dsi_config->dsi_host_cfg_t_pre);
+	if (BITSLICE(csr_setup_mask, 3, 3))
+		W32(base + HOST_CFG_T_POST,
+			dsi_config->dsi_host_cfg_t_post);
+	if (BITSLICE(csr_setup_mask, 4, 4))
+		W32(base + HOST_CFG_TX_GAP,
+			dsi_config->dsi_host_cfg_tx_gap);
+	if (BITSLICE(csr_setup_mask, 5, 5))
+		W32(base + HOST_CFG_AUTOINSERT_EOTP,
+			dsi_config->dsi_host_cfg_autoinsert_eotp);
+	if (BITSLICE(csr_setup_mask, 6, 6))
+		W32(base + HOST_CFG_EXTRA_CMDS_AFTER_EOTP,
+			dsi_config->dsi_host_cfg_extrcmd_after_eotp);
+	if (BITSLICE(csr_setup_mask, 7, 7))
+		W32(base + HOST_CFG_HTX_TO_COUNT,
+			dsi_config->dsi_host_cfg_htx_to_cnt);
+	if (BITSLICE(csr_setup_mask, 8, 8))
+		W32(base + HOST_CFG_LRX_H_TO_COUNT,
+			dsi_config->dsi_host_cfg_lrx_h_to_cnt);
+	if (BITSLICE(csr_setup_mask, 9, 9))
+		W32(base + HOST_CFG_BTA_H_TO_COUNT,
+			dsi_config->dsi_host_cfg_bta_h_to_cnt);
+	if (BITSLICE(csr_setup_mask, 10, 10))
+		W32(base + HOST_CFG_TWAKEUP,
+			dsi_config->dsi_host_cfg_twakeup);
+}
+
+inline void dsi_host_ctrl_dpi_setup(void __iomem *base,
+	struct dsi_cfg_dpi_object *dsi_config,
+	uint32_t dpi_setup_mask)
+{
+	if (BITSLICE(dpi_setup_mask, 0, 0))
+		W32(base + DPI_PIXEL_PAYLOAD_SIZE,
+			dsi_config->dsi_host_cfg_dpi_pxl_payld_size);
+	if (BITSLICE(dpi_setup_mask, 1, 1))
+		W32(base + DPI_PIXEL_FIFO_SEND_LEVEL,
+			dsi_config->dsi_host_cfg_dpi_pxl_fifo_send_lev);
+	if (BITSLICE(dpi_setup_mask, 2, 2))
+		W32(base + DPI_INTERFACE_COLOR_CODING,
+			dsi_config->dsi_host_cfg_dpi_if_color_coding);
+	if (BITSLICE(dpi_setup_mask, 3, 3))
+		W32(base + DPI_PIXEL_FORMAT,
+			dsi_config->dsi_host_cfg_dpi_pxl_format);
+	if (BITSLICE(dpi_setup_mask, 4, 4))
+		W32(base + DPI_VSYNC_POLARITY,
+			dsi_config->dsi_host_cfg_dpi_vsync_pol);
+	if (BITSLICE(dpi_setup_mask, 5, 5))
+		W32(base + DPI_HSYNC_POLARITY,
+			dsi_config->dsi_host_cfg_dpi_hsync_pol);
+	if (BITSLICE(dpi_setup_mask, 6, 6))
+		W32(base + DPI_VIDEO_MODE,
+			dsi_config->dsi_host_cfg_dpi_video_mode);
+	if (BITSLICE(dpi_setup_mask, 7, 7))
+		W32(base + DPI_HFP, dsi_config->dsi_host_cfg_dpi_hfp);
+	if (BITSLICE(dpi_setup_mask, 8, 8))
+		W32(base + DPI_HBP, dsi_config->dsi_host_cfg_dpi_hbp);
+	if (BITSLICE(dpi_setup_mask, 9, 9))
+		W32(base + DPI_HSA, dsi_config->dsi_host_cfg_dpi_hsa);
+	if (BITSLICE(dpi_setup_mask, 10, 10))
+		W32(base + DPI_ENABLE_MULT_PKTS,
+			dsi_config->dsi_host_cfg_dpi_en_mult_pkt);
+	if (BITSLICE(dpi_setup_mask, 11, 11))
+		W32(base + DPI_VBP, dsi_config->dsi_host_cfg_dpi_vbp);
+	if (BITSLICE(dpi_setup_mask, 12, 12))
+		W32(base + DPI_VFP, dsi_config->dsi_host_cfg_dpi_vfp);
+	if (BITSLICE(dpi_setup_mask, 13, 13))
+		W32(base + DPI_BLLP_MODE,
+			dsi_config->dsi_host_cfg_dpi_bllp_mode);
+	if (BITSLICE(dpi_setup_mask, 14, 14))
+		W32(base + DPI_USE_NULL_PKT_BLLP,
+			dsi_config->dsi_host_cfg_dpi_null_pkt_bllp);
+	if (BITSLICE(dpi_setup_mask, 15, 15))
+		W32(base + DPI_VACTIVE,
+			dsi_config->dsi_host_cfg_dpi_vactive);
+	if (BITSLICE(dpi_setup_mask, 16, 16))
+		W32(base + DPI_VC, dsi_config->dsi_host_cfg_dpi_vc);
+}
+
+inline void dsi_host_ctrl_pkt_setup(void __iomem *base,
+	struct dsi_cfg_pkt_object *dsi_config,
+	uint8_t pkt_setup_mask)
+{
+	if (BITSLICE(pkt_setup_mask, 0, 0))
+		W32(base + HOST_PKT_CONTROL,
+			dsi_config->dsi_host_pkt_ctrl);
+	if (BITSLICE(pkt_setup_mask, 2, 2))
+		W32(base + HOST_IRQ_MASK, dsi_config->dsi_host_irq_mask);
+	if (BITSLICE(pkt_setup_mask, 3, 3))
+		W32(base + HOST_IRQ_MASK2, dsi_config->dsi_host_irq_mask2);
+	if (BITSLICE(pkt_setup_mask, 1, 1))
+		W32(base + HOST_SEND_PACKET,
+			dsi_config->dsi_host_send_pkt);
+}
+
+inline void dsi_host_ctrl_dphy_setup(void __iomem *base,
+	struct dsi_cfg_dphy_object *dsi_config,
+	uint32_t dphy_setup_mask)
+{
+	int i;
+
+	if (BITSLICE(dphy_setup_mask, 8, 8))
+		W32(base + DPHY_TST, dsi_config->dphy_tst);
+	if (BITSLICE(dphy_setup_mask, 9, 9))
+		W32(base + DPHY_CN, dsi_config->dphy_cn);
+	if (BITSLICE(dphy_setup_mask, 10, 10))
+		W32(base + DPHY_CM, dsi_config->dphy_cm);
+	if (BITSLICE(dphy_setup_mask, 11, 11))
+		W32(base + DPHY_CO, dsi_config->dphy_co);
+	if (BITSLICE(dphy_setup_mask, 7, 7))
+		W32(base + DPHY_PD_PLL, dsi_config->dphy_pd_pll);
+	/* todo: disable on zebu */
+	/*Polling of DPHY Lock status / wait for PLL lock */
+	for (i = 0; i < 100; i++) {
+		u32 lock;
+		udelay(10);
+		/*todo: zebu abort when reading DPHY LOCK */
+		lock = R32(DPHY_LOCK);
+		printf("DPHY PLL Lock = 0x%08x\n", lock);
+	}
+	/*todo: Need to wait for lock here */
+
+	if (BITSLICE(dphy_setup_mask, 1, 1))
+		W32(base + DPHY_M_PRG_HS_PREPARE,
+			dsi_config->dphy_m_prg_hs_prepare);
+	if (BITSLICE(dphy_setup_mask, 2, 2))
+		W32(base + DPHY_MC_PRG_HS_PREPARE,
+			dsi_config->dphy_mc_prg_hs_prepare);
+	if (BITSLICE(dphy_setup_mask, 3, 3))
+		W32(base + DPHY_M_PRG_HS_ZERO,
+			dsi_config->dphy_m_prg_hs_zero);
+	if (BITSLICE(dphy_setup_mask, 4, 4))
+		W32(base + DPHY_MC_PRG_HS_ZERO,
+			dsi_config->dphy_mc_prg_hs_zero);
+	if (BITSLICE(dphy_setup_mask, 5, 5))
+		W32(base + DPHY_M_PRG_HS_TRAIL,
+			dsi_config->dphy_m_prg_hs_trial);
+	if (BITSLICE(dphy_setup_mask, 6, 6))
+		W32(base + DPHY_MC_PRG_HS_TRAIL,
+			dsi_config->dphy_mc_prg_hs_trial);
+	if (BITSLICE(dphy_setup_mask, 0, 0))
+		W32(base + DPHY_PD_TX, dsi_config->dphy_pd_tx);
+	if (BITSLICE(dphy_setup_mask, 12, 12))
+		W32(base + DPHY_LOCK, dsi_config->dphy_lock);
+	if (BITSLICE(dphy_setup_mask, 13, 13))
+		W32(base + DPHY_LOCK_BYP, dsi_config->dphy_lock_byp);
+}
+#endif /* _IMX8_MIPI_DSI_H_ */
diff --git a/arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h b/arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h
new file mode 100644
index 00000000000..692c27f7d30
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _SC_LPCG_H
+#define _SC_LPCG_H
+
+/*LSIO SS */
+#define		PWM_0_LPCG		0x5D400000
+#define		PWM_1_LPCG		0x5D410000
+#define		PWM_2_LPCG		0x5D420000
+#define		PWM_3_LPCG		0x5D430000
+#define		PWM_4_LPCG		0x5D440000
+#define		PWM_5_LPCG		0x5D450000
+#define		PWM_6_LPCG		0x5D460000
+#define		PWM_7_LPCG		0x5D470000
+#define		GPIO_0_LPCG		0x5D480000
+#define		GPIO_1_LPCG		0x5D490000
+#define		GPIO_2_LPCG		0x5D4A0000
+#define		GPIO_3_LPCG		0x5D4B0000
+#define		GPIO_4_LPCG		0x5D4C0000
+#define		GPIO_5_LPCG		0x5D4D0000
+#define		GPIO_6_LPCG		0x5D4E0000
+#define		GPIO_7_LPCG		0x5D4F0000
+#define		FSPI_0_LPCG		0x5D520000
+#define		FSPI_1_LPCG		0x5D530000
+#define		GPT_0_LPCG		0x5D540000
+#define		GPT_1_LPCG		0x5D550000
+#define		GPT_2_LPCG		0x5D560000
+#define		GPT_3_LPCG		0x5D570000
+#define		GPT_4_LPCG		0x5D580000
+#define		OCRAM_LPCG		0x5D590000
+#define		KPP_LPCG		0x5D5A0000
+#define		MU_5A_LPCG		0x5D600000
+#define		MU_6A_LPCG		0x5D610000
+#define		MU_7A_LPCG		0x5D620000
+#define		MU_8A_LPCG		0x5D630000
+#define		MU_9A_LPCG		0x5D640000
+#define		MU_10A_LPCG		0x5D650000
+#define		MU_11A_LPCG		0x5D660000
+#define		MU_12A_LPCG		0x5D670000
+#define		MU_13A_LPCG		0x5D680000
+
+/* HSIO SS */
+#define		CRR_5_LPCG		0x5F0F0000
+#define		CRR_4_LPCG		0x5F0E0000
+#define		CRR_3_LPCG		0x5F0D0000
+#define		CRR_2_LPCG		0x5F0C0000
+#define		CRR_1_LPCG		0x5F0B0000
+#define		CRR_0_LPCG		0x5F0A0000
+#define		PHY_1_LPCG		0x5F090000
+#define		PHY_2_LPCG		0x5F080000
+#define		SATA_0_LPCG		0x5F070000
+#define		PCIE_B_LPCG		0x5F060000
+#define		PCIE_A_LPCG		0x5F050000
+
+/* DMA SS */
+#define		FLEX_CAN_2_LPCG		0x5ACF0000
+#define		FLEX_CAN_1_LPCG		0x5ACE0000
+#define		FLEX_CAN_0_LPCG		0x5ACD0000
+#define		FTM_1_LPCG		0x5ACB0000
+#define		FTM_0_LPCG		0x5ACA0000
+#define		ADC_1_LPCG		0x5AC90000
+#define		ADC_0_LPCG		0x5AC80000
+#define		LPI2C_4_LPCG		0x5AC40000
+#define		LPI2C_3_LPCG		0x5AC30000
+#define		LPI2C_2_LPCG		0x5AC20000
+#define		LPI2C_1_LPCG		0x5AC10000
+#define		LPI2C_0_LPCG		0x5AC00000
+#define		EMVSIM_1_LPCG		0x5A4E0000
+#define		EMVSIM_0_LPCG		0x5A4D0000
+#define		LPUART_4_LPCG		0x5A4A0000
+#define		LPUART_3_LPCG		0x5A490000
+#define		LPUART_2_LPCG		0x5A480000
+#define		LPUART_1_LPCG		0x5A470000
+#define		LPUART_0_LPCG		0x5A460000
+#define		LPSPI_3_LPCG		0x5A430000
+#define		LPSPI_2_LPCG		0x5A420000
+#define		LPSPI_1_LPCG		0x5A410000
+#define		LPSPI_0_LPCG		0x5A400000
+
+/* Display SS */
+#define		DC_0_LPCG		0x56010000
+#define		DC_1_LPCG		0x57010000
+
+/* LVDS */
+#define		DI_LVDS_0_LPCG		0x56243000
+#define		DI_LVDS_1_LPCG		0x57243000
+
+/* DI HDMI */
+#define		DI_HDMI_LPCG		0x56263000
+
+/* RX-HDMI */
+#define		RX_HDMI_LPCG		0x58263000
+
+/* MIPI CSI SS */
+#define		MIPI_CSI_0_LPCG		0x58223000
+#define		MIPI_CSI_1_LPCG		0x58243000
+
+/* MIPI DSI SS */
+#define		MIPI_DSI_0_LPCG		0x56223000
+#define		MIPI_DSI_1_LPCG		0x57223000
+
+/* Imaging SS */
+#define IMG_JPEG_ENC_LPCG		0x585F0000
+#define IMG_JPEG_DEC_LPCG		0x585D0000
+#define IMG_PXL_LINK_DC1_LPCG	0x585C0000
+#define IMG_PXL_LINK_DC0_LPCG	0x585B0000
+#define IMG_PXL_LINK_HDMI_LPCG	0x585A0000
+#define IMG_PXL_LINK_CSI1_LPCG	0x58590000
+#define IMG_PXL_LINK_CSI0_LPCG	0x58580000
+#define IMG_PDMA_7_LPCG			0x58570000
+#define IMG_PDMA_6_LPCG			0x58560000
+#define IMG_PDMA_5_LPCG			0x58550000
+#define IMG_PDMA_4_LPCG			0x58540000
+#define IMG_PDMA_3_LPCG			0x58530000
+#define IMG_PDMA_2_LPCG			0x58520000
+#define IMG_PDMA_1_LPCG			0x58510000
+#define IMG_PDMA_0_LPCG			0x58500000
+
+/* HSIO SS */
+#define HSIO_GPIO_LPCG			0x5F100000
+#define HSIO_MISC_LPCG			0x5F0F0000
+#define HSIO_SATA_CRR4_LPCG		0x5F0E0000
+#define HSIO_PCIE_X1_CRR3_LPCG	0x5F0D0000
+#define HSIO_PCIE_X2_CRR2_LPCG	0x5F0C0000
+#define HSIO_PHY_X1_CRR1_LPCG	0x5F0B0000
+#define HSIO_PHY_X2_CRR0_LPCG	0x5F0A0000
+#define HSIO_PHY_X1_LPCG		0x5F090000
+#define HSIO_PHY_X2_LPCG		0x5F080000
+#define HSIO_SATA_LPCG			0x5F070000
+#define HSIO_PCIE_X1_LPCG		0x5F060000
+#define HSIO_PCIE_X2_LPCG		0x5F050000
+
+/* M4 SS */
+#define		M4_0_I2C_LPCG		0x37630000
+#define		M4_0_LPUART_LPCG	0x37620000
+#define		M4_0_LPIT_LPCG		0x37610000
+#define		M4_1_I2C_LPCG		0x3B630000
+#define		M4_1_LPUART_LPCG	0x3B620000
+#define		M4_1_LPIT_LPCG		0x3B610000
+
+/* Audio SS */
+#define     AUD_ASRC_0_LPCG         0x59400000
+#define     AUD_ESAI_0_LPCG         0x59410000
+#define     AUD_SPDIF_0_LPCG        0x59420000
+#define     AUD_SPDIF_1_LPCG        0x59430000
+#define     AUD_SAI_0_LPCG          0x59440000
+#define     AUD_SAI_1_LPCG          0x59450000
+#define     AUD_SAI_2_LPCG          0x59460000
+#define     AUD_SAI_3_LPCG          0x59470000
+#define     AUD_HDMI_RX_SAI_0_LPCG  0x59480000
+#define     AUD_HDMI_TX_SAI_0_LPCG  0x59490000
+#define     AUD_GPT_5_LPCG          0x594B0000
+#define     AUD_GPT_6_LPCG          0x594C0000
+#define     AUD_GPT_7_LPCG          0x594D0000
+#define     AUD_GPT_8_LPCG          0x594E0000
+#define     AUD_GPT_9_LPCG          0x594F0000
+#define     AUD_GPT_10_LPCG         0x59500000
+#define     AUD_DSP_LPCG            0x59580000
+#define     AUD_OCRAM_LPCG          0x59590000
+#define     AUD_EDMA_0_LPCG         0x595f0000
+#define     AUD_ASRC_1_LPCG         0x59c00000
+#define     AUD_ESAI_1_LPCG         0x59c10000
+#define     AUD_SAI_6_LPCG          0x59c20000
+#define     AUD_SAI_7_LPCG          0x59c30000
+#define     AUD_AMIX_LPCG           0x59c40000
+#define     AUD_MQS_LPCG            0x59c50000
+#define     AUD_ACM_LPCG            0x59c60000
+#define     AUD_REC_CLK0_LPCG       0x59d00000
+#define     AUD_REC_CLK1_LPCG       0x59d10000
+#define     AUD_PLL_CLK0_LPCG       0x59d20000
+#define     AUD_PLL_CLK1_LPCG       0x59d30000
+#define     AUD_MCLKOUT0_LPCG       0x59d50000
+#define     AUD_MCLKOUT1_LPCG       0x59d60000
+#define     AUD_EDMA_1_LPCG         0x59df0000
+
+
+/* Connectivity SS */
+#define     USDHC_0_LPCG        0x5B200000
+#define     USDHC_1_LPCG        0x5B210000
+#define     USDHC_2_LPCG        0x5B220000
+#define     ENET_0_LPCG         0x5B230000
+#define     ENET_1_LPCG         0x5B240000
+#define     DTCP_LPCG           0x5B250000
+#define     MLB_LPCG            0x5B260000
+#define     USB_2_LPCG          0x5B270000
+#define     USB_3_LPCG          0x5B280000
+#define     NAND_LPCG           0x5B290000
+#define     EDMA_LPCG           0x5B2A0000
+
+/* CM40 SS */
+#define	CM40_I2C_LPCG		0x37630000
+
+/* CM41 SS */
+#define	CM41_I2C_LPCG		0x3B630000
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h b/arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h
new file mode 100644
index 00000000000..5fed5140c1a
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _SC_LPCG_H
+#define _SC_LPCG_H
+
+/*LSIO SS */
+#define		PWM_0_LPCG		0x5D400000
+#define		PWM_1_LPCG		0x5D410000
+#define		PWM_2_LPCG		0x5D420000
+#define		PWM_3_LPCG		0x5D430000
+#define		PWM_4_LPCG		0x5D440000
+#define		PWM_5_LPCG		0x5D450000
+#define		PWM_6_LPCG		0x5D460000
+#define		PWM_7_LPCG		0x5D470000
+#define		GPIO_0_LPCG		0x5D480000
+#define		GPIO_1_LPCG		0x5D490000
+#define		GPIO_2_LPCG		0x5D4A0000
+#define		GPIO_3_LPCG		0x5D4B0000
+#define		GPIO_4_LPCG		0x5D4C0000
+#define		GPIO_5_LPCG		0x5D4D0000
+#define		GPIO_6_LPCG		0x5D4E0000
+#define		GPIO_7_LPCG		0x5D4F0000
+#define		FSPI_0_LPCG		0x5D520000
+#define		FSPI_1_LPCG		0x5D530000
+#define		GPT_0_LPCG		0x5D540000
+#define		GPT_1_LPCG		0x5D550000
+#define		GPT_2_LPCG		0x5D560000
+#define		GPT_3_LPCG		0x5D570000
+#define		GPT_4_LPCG		0x5D580000
+#define		OCRAM_LPCG		0x5D590000
+#define		KPP_LPCG		0x5D5A0000
+#define		ROMCP_LPCG		0x5D500000
+#define		MU_5A_LPCG		0x5D600000
+#define		MU_6A_LPCG		0x5D610000
+#define		MU_7A_LPCG		0x5D620000
+#define		MU_8A_LPCG		0x5D630000
+#define		MU_9A_LPCG		0x5D640000
+#define		MU_10A_LPCG		0x5D650000
+#define		MU_11A_LPCG		0x5D660000
+#define		MU_12A_LPCG		0x5D670000
+#define		MU_13A_LPCG		0x5D680000
+
+/* HSIO SS */
+#define		CRR_5_LPCG		0x5F0F0000
+#define		CRR_4_LPCG		0x5F0E0000
+#define		CRR_3_LPCG		0x5F0D0000
+#define		CRR_2_LPCG		0x5F0C0000
+#define		CRR_1_LPCG		0x5F0B0000
+#define		CRR_0_LPCG		0x5F0A0000
+#define		PHY_1_LPCG		0x5F090000
+#define		PHY_2_LPCG		0x5F080000
+#define		SATA_0_LPCG		0x5F070000
+#define		PCIE_B_LPCG		0x5F060000
+#define		PCIE_A_LPCG		0x5F050000
+
+/* DMA SS */
+#define		FLEX_CAN_2_LPCG		0x5ACF0000
+#define		FLEX_CAN_1_LPCG		0x5ACE0000
+#define		FLEX_CAN_0_LPCG		0x5ACD0000
+#define		FTM_1_LPCG		0x5ACB0000
+#define		FTM_0_LPCG		0x5ACA0000
+#define		ADC_0_LPCG		0x5AC80000
+#define		LPI2C_3_LPCG		0x5AC30000
+#define		LPI2C_2_LPCG		0x5AC20000
+#define		LPI2C_1_LPCG		0x5AC10000
+#define		LPI2C_0_LPCG		0x5AC00000
+#define		PWM_LPCG		0x5A590000
+#define		LCD_LPCG		0x5A580000
+#define		LPUART_3_LPCG		0x5A490000
+#define		LPUART_2_LPCG		0x5A480000
+#define		LPUART_1_LPCG		0x5A470000
+#define		LPUART_0_LPCG		0x5A460000
+#define		LPSPI_3_LPCG		0x5A430000
+#define		LPSPI_2_LPCG		0x5A420000
+#define		LPSPI_1_LPCG		0x5A410000
+#define		LPSPI_0_LPCG		0x5A400000
+
+/* Display SS */
+#define		DC_0_LPCG		0x56010000
+#define		DC_1_LPCG		0x57010000
+
+/* LVDS */
+#define		DI_LVDS_0_LPCG		0x56243000
+#define		DI_LVDS_1_LPCG		0x57243000
+
+/* DI HDMI */
+#define		DI_HDMI_LPCG		0x56263000
+
+/* RX-HDMI */
+#define		RX_HDMI_LPCG		0x58263000
+
+/* MIPI CSI SS */
+#define		MIPI_CSI_0_LPCG		0x58223000
+#define		MIPI_CSI_1_LPCG		0x58243000
+
+/* PARALLEL CSI SS */
+#define		PARALLEL_CSI_LPCG	0x58263000
+
+/* Display MIPI SS */
+#define		DI_MIPI0_LPCG		0x56223000
+#define		DI_MIPI1_LPCG		0x56243000
+
+/* Imaging SS */
+#define IMG_JPEG_ENC_LPCG		0x585F0000
+#define IMG_JPEG_DEC_LPCG		0x585D0000
+#define IMG_PXL_LINK_DC1_LPCG	0x585C0000
+#define IMG_PXL_LINK_DC0_LPCG	0x585B0000
+#define IMG_PXL_LINK_HDMI_LPCG	0x585A0000
+#define IMG_PXL_LINK_CSI1_LPCG	0x58590000
+#define IMG_PXL_LINK_CSI0_LPCG	0x58580000
+#define IMG_PDMA_7_LPCG			0x58570000
+#define IMG_PDMA_6_LPCG			0x58560000
+#define IMG_PDMA_5_LPCG			0x58550000
+#define IMG_PDMA_4_LPCG			0x58540000
+#define IMG_PDMA_3_LPCG			0x58530000
+#define IMG_PDMA_2_LPCG			0x58520000
+#define IMG_PDMA_1_LPCG			0x58510000
+#define IMG_PDMA_0_LPCG			0x58500000
+
+/* HSIO SS */
+#define HSIO_GPIO_LPCG			0x5F100000
+#define HSIO_MISC_LPCG			0x5F0F0000
+#define HSIO_SATA_CRR4_LPCG		0x5F0E0000
+#define HSIO_PCIE_X1_CRR3_LPCG	0x5F0D0000
+#define HSIO_PCIE_X2_CRR2_LPCG	0x5F0C0000
+#define HSIO_PHY_X1_CRR1_LPCG	0x5F0B0000
+#define HSIO_PHY_X2_CRR0_LPCG	0x5F0A0000
+#define HSIO_PHY_X1_LPCG		0x5F090000
+#define HSIO_PHY_X2_LPCG		0x5F080000
+#define HSIO_SATA_LPCG			0x5F070000
+#define HSIO_PCIE_X1_LPCG		0x5F060000
+#define HSIO_PCIE_X2_LPCG		0x5F050000
+
+/* M4 SS */
+#define		M4_0_I2C_LPCG		0x37630000
+#define		M4_0_LPUART_LPCG	0x37620000
+#define		M4_0_LPIT_LPCG		0x37610000
+#define		M4_1_I2C_LPCG		0x3B630000
+#define		M4_1_LPUART_LPCG	0x3B620000
+#define		M4_1_LPIT_LPCG		0x3B610000
+
+/* Audio SS */
+#define     AUD_ASRC_0_LPCG         0x59400000
+#define     AUD_ESAI_0_LPCG         0x59410000
+#define     AUD_SPDIF_0_LPCG        0x59420000
+#define     AUD_SAI_0_LPCG          0x59440000
+#define     AUD_SAI_1_LPCG          0x59450000
+#define     AUD_SAI_2_LPCG          0x59460000
+#define     AUD_SAI_3_LPCG          0x59470000
+#define     AUD_GPT_5_LPCG          0x594B0000
+#define     AUD_GPT_6_LPCG          0x594C0000
+#define     AUD_GPT_7_LPCG          0x594D0000
+#define     AUD_GPT_8_LPCG          0x594E0000
+#define     AUD_GPT_9_LPCG          0x594F0000
+#define     AUD_GPT_10_LPCG         0x59500000
+#define     AUD_DSP_LPCG            0x59580000
+#define     AUD_OCRAM_LPCG          0x59590000
+#define     AUD_EDMA_0_LPCG         0x595f0000
+#define     AUD_ASRC_1_LPCG         0x59c00000
+#define     AUD_SAI_4_LPCG          0x59c20000
+#define     AUD_SAI_5_LPCG          0x59c30000
+#define     AUD_AMIX_LPCG           0x59c40000
+#define     AUD_MQS_LPCG            0x59c50000
+#define     AUD_ACM_LPCG            0x59c60000
+#define     AUD_REC_CLK0_LPCG       0x59d00000
+#define     AUD_REC_CLK1_LPCG       0x59d10000
+#define     AUD_PLL_CLK0_LPCG       0x59d20000
+#define     AUD_PLL_CLK1_LPCG       0x59d30000
+#define     AUD_MCLKOUT0_LPCG       0x59d50000
+#define     AUD_MCLKOUT1_LPCG       0x59d60000
+#define     AUD_EDMA_1_LPCG         0x59df0000
+
+
+/* Connectivity SS */
+#define     USDHC_0_LPCG        0x5B200000
+#define     USDHC_1_LPCG        0x5B210000
+#define     USDHC_2_LPCG        0x5B220000
+#define     ENET_0_LPCG         0x5B230000
+#define     ENET_1_LPCG         0x5B240000
+#define     DTCP_LPCG           0x5B250000
+#define     MLB_LPCG            0x5B260000
+#define     USB_2_LPCG          0x5B270000
+#define     USB_3_LPCG          0x5B280000
+#define     NAND_LPCG           0x5B290000
+#define     EDMA_LPCG           0x5B2A0000
+
+/* CM40 SS */
+#define     CM40_I2C_LPCG       0x37630000
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx8/lpcg.h b/arch/arm/include/asm/arch-imx8/lpcg.h
new file mode 100644
index 00000000000..85cb5b30c19
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/lpcg.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_IMX8_LPCG_H__
+#define __ASM_ARCH_IMX8_LPCG_H__
+
+#if defined(CONFIG_IMX8QM)
+#include "imx8qm_lpcg.h"
+#elif defined(CONFIG_IMX8QXP)
+#include "imx8qxp_lpcg.h"
+#elif defined(CONFIG_IMX8DXL)
+#include "imx8qxp_lpcg.h"
+#else
+#error "No lpcg header"
+#endif
+
+void lpcg_clock_off(u32 lpcg_addr, u8 clk);
+void lpcg_clock_on(u32 lpcg_addr, u8 clk);
+void lpcg_clock_autogate(u32 lpcg_addr, u8 clk);
+bool lpcg_is_clock_on(u32 lpcg_addr, u8 clk);
+void lpcg_all_clock_off(u32 lpcg_addr);
+void lpcg_all_clock_on(u32 lpcg_addr);
+void lpcg_all_clock_autogate(u32 lpcg_addr);
+
+#endif	/* __ASM_ARCH_IMX8_LPCG_H__ */
diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h b/arch/arm/include/asm/arch-imx8/sci/rpc.h
index 9f55904f442..041e4d002dc 100644
--- a/arch/arm/include/asm/arch-imx8/sci/rpc.h
+++ b/arch/arm/include/asm/arch-imx8/sci/rpc.h
@@ -11,7 +11,7 @@
 /* Defines */
 
 #define SCFW_API_VERSION_MAJOR  1U
-#define SCFW_API_VERSION_MINOR  15U
+#define SCFW_API_VERSION_MINOR  21U
 
 #define SC_RPC_VERSION          1U
 
@@ -22,13 +22,13 @@
 #define RPC_SVC(MSG)            ((MSG)->svc)
 #define RPC_FUNC(MSG)           ((MSG)->func)
 #define RPC_R8(MSG)             ((MSG)->func)
-#define RPC_I64(MSG, IDX)       ((s64)(RPC_U32((MSG), (IDX))) << 32ULL) | \
-				  (s64)(RPC_U32((MSG), (IDX) + 4U))
+#define RPC_I64(MSG, IDX)       ((s64)(RPC_U32((MSG), (IDX))) << 32ULL) \
+                                    | (s64)(RPC_U32((MSG), (IDX) + 4U))
 #define RPC_I32(MSG, IDX)       ((MSG)->DATA.i32[(IDX) / 4U])
 #define RPC_I16(MSG, IDX)       ((MSG)->DATA.i16[(IDX) / 2U])
 #define RPC_I8(MSG, IDX)        ((MSG)->DATA.i8[(IDX)])
-#define RPC_U64(MSG, IDX)       ((u64)(RPC_U32((MSG), (IDX))) << 32ULL) | \
-				  (u64)(RPC_U32((MSG), (IDX) + 4U))
+#define RPC_U64(MSG, IDX)       ((u64)(RPC_U32((MSG), (IDX))) << 32ULL) \
+                                    | (u64)(RPC_U32((MSG), (IDX) + 4U))
 #define RPC_U32(MSG, IDX)       ((MSG)->DATA.u32[(IDX) / 4U])
 #define RPC_U16(MSG, IDX)       ((MSG)->DATA.u16[(IDX) / 2U])
 #define RPC_U8(MSG, IDX)        ((MSG)->DATA.u8[(IDX)])
@@ -67,7 +67,9 @@ struct sc_rpc_msg_s {
 #define PM_FUNC_SET_SYS_POWER_MODE		19U
 #define PM_FUNC_SET_PARTITION_POWER_MODE	1U
 #define PM_FUNC_GET_SYS_POWER_MODE		2U
+#define PM_FUNC_PARTITION_WAKE 			28U
 #define PM_FUNC_SET_RESOURCE_POWER_MODE		3U
+#define PM_FUNC_SET_RESOURCE_POWER_MODE_ALL 22U
 #define PM_FUNC_GET_RESOURCE_POWER_MODE		4U
 #define PM_FUNC_REQ_LOW_POWER_MODE		16U
 #define PM_FUNC_REQ_CPU_LOW_POWER_MODE		20U
@@ -81,12 +83,15 @@ struct sc_rpc_msg_s {
 #define PM_FUNC_GET_CLOCK_PARENT		15U
 #define PM_FUNC_RESET				13U
 #define PM_FUNC_RESET_REASON			10U
+#define PM_FUNC_GET_RESET_PART 		26U
 #define PM_FUNC_BOOT				8U
+#define PM_FUNC_SET_BOOT_PARM 		27U
 #define PM_FUNC_REBOOT				9U
 #define PM_FUNC_REBOOT_PARTITION		12U
+#define PM_FUNC_REBOOT_CONTINUE 	25U
 #define PM_FUNC_CPU_START			11U
-#define PM_FUNC_CPU_RESET			23U
-#define PM_FUNC_RESOURCE_RESET			29U
+#define PM_FUNC_CPU_RESET 			23U
+#define PM_FUNC_RESOURCE_RESET 		29U
 #define PM_FUNC_IS_PARTITION_STARTED 24U
 
 /* MISC RPC */
@@ -95,16 +100,10 @@ struct sc_rpc_msg_s {
 #define MISC_FUNC_GET_CONTROL			2U
 #define MISC_FUNC_SET_MAX_DMA_GROUP		4U
 #define MISC_FUNC_SET_DMA_GROUP			5U
-#define MISC_FUNC_SECO_IMAGE_LOAD		8U
-#define MISC_FUNC_SECO_AUTHENTICATE		9U
-#define MISC_FUNC_SECO_FUSE_WRITE		20U
-#define MISC_FUNC_SECO_ENABLE_DEBUG		21U
-#define MISC_FUNC_SECO_FORWARD_LIFECYCLE	22U
-#define MISC_FUNC_SECO_RETURN_LIFECYCLE		23U
-#define MISC_FUNC_SECO_BUILD_INFO		24U
 #define MISC_FUNC_DEBUG_OUT			10U
 #define MISC_FUNC_WAVEFORM_CAPTURE		6U
 #define MISC_FUNC_BUILD_INFO			15U
+#define MISC_FUNC_API_VER			35U
 #define MISC_FUNC_UNIQUE_ID			19U
 #define MISC_FUNC_SET_ARI			3U
 #define MISC_FUNC_BOOT_STATUS			7U
@@ -114,8 +113,11 @@ struct sc_rpc_msg_s {
 #define MISC_FUNC_SET_TEMP			12U
 #define MISC_FUNC_GET_TEMP			13U
 #define MISC_FUNC_GET_BOOT_DEV			16U
-#define MISC_FUNC_GET_BUTTON_STATUS		18U
+#define MISC_FUNC_GET_BOOT_TYPE			33U
 #define MISC_FUNC_GET_BOOT_CONTAINER	36U
+#define MISC_FUNC_GET_BUTTON_STATUS		18U
+#define MISC_FUNC_ROMPATCH_CHECKSUM 	26U
+#define MISC_FUNC_BOARD_IOCTL 			34U
 
 /* PAD RPC */
 #define PAD_FUNC_UNKNOWN			0
@@ -160,6 +162,7 @@ struct sc_rpc_msg_s {
 #define RM_FUNC_GET_RESOURCE_INFO		16U
 #define RM_FUNC_MEMREG_ALLOC			17U
 #define RM_FUNC_MEMREG_SPLIT			29U
+#define RM_FUNC_MEMREG_FRAG 			32U
 #define RM_FUNC_MEMREG_FREE			18U
 #define RM_FUNC_FIND_MEMREG			30U
 #define RM_FUNC_ASSIGN_MEMREG			19U
@@ -190,6 +193,7 @@ struct sc_rpc_msg_s {
 #define SECO_FUNC_UPDATE_MPMR 14U /* Index for seco_update_mpmr() RPC call */
 #define SECO_FUNC_GET_MP_SIGN 15U /* Index for seco_get_mp_sign() RPC call */
 #define SECO_FUNC_BUILD_INFO 16U /* Index for seco_build_info() RPC call */
+#define SECO_FUNC_V2X_BUILD_INFO 30U /* Index for sc_seco_v2x_build_info() RPC call */
 #define SECO_FUNC_CHIP_INFO 17U /* Index for seco_chip_info() RPC call */
 #define SECO_FUNC_ENABLE_DEBUG 18U /* Index for seco_enable_debug() RPC call */
 #define SECO_FUNC_GET_EVENT 19U /* Index for seco_get_event() RPC call */
@@ -210,6 +214,7 @@ struct sc_rpc_msg_s {
 #define TIMER_FUNC_UNKNOWN 0 /* Unknown function */
 #define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for sc_timer_set_wdog_timeout() RPC call */
 #define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for sc_timer_set_wdog_pre_timeout() RPC call */
+#define TIMER_FUNC_SET_WDOG_WINDOW 19U /* Index for sc_timer_set_wdog_window() RPC call */
 #define TIMER_FUNC_START_WDOG 2U /* Index for sc_timer_start_wdog() RPC call */
 #define TIMER_FUNC_STOP_WDOG 3U /* Index for sc_timer_stop_wdog() RPC call */
 #define TIMER_FUNC_PING_WDOG 4U /* Index for sc_timer_ping_wdog() RPC call */
diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h
index 1c29209b399..94b62dc16d1 100644
--- a/arch/arm/include/asm/arch-imx8/sci/sci.h
+++ b/arch/arm/include/asm/arch-imx8/sci/sci.h
@@ -13,6 +13,8 @@
 #include <asm/arch/sci/svc/pm/api.h>
 #include <asm/arch/sci/svc/rm/api.h>
 #include <asm/arch/sci/svc/seco/api.h>
+#include <asm/arch/sci/svc/irq/api.h>
+#include <asm/arch/sci/svc/timer/api.h>
 #include <asm/arch/sci/rpc.h>
 #include <dt-bindings/soc/imx_rsrc.h>
 #include <linux/errno.h>
@@ -72,6 +74,7 @@ int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
 			   sc_pm_clk_parent_t parent);
 int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
 		    sc_faddr_t address);
+void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type);
 sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt);
 int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource);
 
@@ -87,6 +90,7 @@ void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit);
 int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val);
 int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp,
 		     s16 *celsius, s8 *tenths);
+void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status);
 
 /* RM API */
 sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
@@ -116,6 +120,9 @@ int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val);
 /* SMMU API */
 int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid);
 
+/* Timer API */
+int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window);
+
 /* SECO API */
 int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
 			 sc_faddr_t addr);
@@ -123,16 +130,20 @@ int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change);
 int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l,
 		      u32 *uid_h);
 void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit);
+int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit);
 int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event);
 int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr,
 			 sc_faddr_t export_addr, u16 max_size);
-int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size);
-int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock);
+int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr,
+			u16 dst_size);
+int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr,
+			u8 size, u8 lock);
 int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr,
 			u16 msg_size, sc_faddr_t dst_addr, u16 dst_size);
-int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data);
 int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access,
-			  u32 *data0, u32 *data1, u32 *data2, u32 *data3,
-			  u32 *data4, u8 size);
+	u32 *data0, u32 *data1, u32 *data2, u32 *data3,
+	u32 *data4, u8 size);
+int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access,
+	u32 *data);
 
 #endif
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h
new file mode 100644
index 00000000000..f701e601331
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef SC_IRQ_API_H
+#define SC_IRQ_API_H
+
+/* Defines */
+
+#define SC_IRQ_NUM_GROUP        7U   /* Number of groups */
+
+/* Defines for sc_irq_group_t */
+#define SC_IRQ_GROUP_TEMP       0U   /* Temp interrupts */
+#define SC_IRQ_GROUP_WDOG       1U   /* Watchdog interrupts */
+#define SC_IRQ_GROUP_RTC        2U   /* RTC interrupts */
+#define SC_IRQ_GROUP_WAKE       3U   /* Wakeup interrupts */
+#define SC_IRQ_GROUP_SYSCTR     4U   /* System counter interrupts */
+#define SC_IRQ_GROUP_REBOOTED   5U   /* Partition reboot complete */
+#define SC_IRQ_GROUP_REBOOT     6U   /* Partition reboot starting */
+
+/* Defines for sc_irq_temp_t */
+#define SC_IRQ_TEMP_HIGH         (1UL << 0U)    /* Temp alarm interrupt */
+#define SC_IRQ_TEMP_CPU0_HIGH    (1UL << 1U)    /* CPU0 temp alarm interrupt */
+#define SC_IRQ_TEMP_CPU1_HIGH    (1UL << 2U)    /* CPU1 temp alarm interrupt */
+#define SC_IRQ_TEMP_GPU0_HIGH    (1UL << 3U)    /* GPU0 temp alarm interrupt */
+#define SC_IRQ_TEMP_GPU1_HIGH    (1UL << 4U)    /* GPU1 temp alarm interrupt */
+#define SC_IRQ_TEMP_DRC0_HIGH    (1UL << 5U)    /* DRC0 temp alarm interrupt */
+#define SC_IRQ_TEMP_DRC1_HIGH    (1UL << 6U)    /* DRC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_VPU_HIGH     (1UL << 7U)    /* DRC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC0_HIGH   (1UL << 8U)    /* PMIC0 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC1_HIGH   (1UL << 9U)    /* PMIC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_LOW          (1UL << 10U)   /* Temp alarm interrupt */
+#define SC_IRQ_TEMP_CPU0_LOW     (1UL << 11U)   /* CPU0 temp alarm interrupt */
+#define SC_IRQ_TEMP_CPU1_LOW     (1UL << 12U)   /* CPU1 temp alarm interrupt */
+#define SC_IRQ_TEMP_GPU0_LOW     (1UL << 13U)   /* GPU0 temp alarm interrupt */
+#define SC_IRQ_TEMP_GPU1_LOW     (1UL << 14U)   /* GPU1 temp alarm interrupt */
+#define SC_IRQ_TEMP_DRC0_LOW     (1UL << 15U)   /* DRC0 temp alarm interrupt */
+#define SC_IRQ_TEMP_DRC1_LOW     (1UL << 16U)   /* DRC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_VPU_LOW      (1UL << 17U)   /* DRC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC0_LOW    (1UL << 18U)   /* PMIC0 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC1_LOW    (1UL << 19U)   /* PMIC1 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC2_HIGH   (1UL << 20U)   /* PMIC2 temp alarm interrupt */
+#define SC_IRQ_TEMP_PMIC2_LOW    (1UL << 21U)   /* PMIC2 temp alarm interrupt */
+
+/* Defines for sc_irq_wdog_t */
+#define SC_IRQ_WDOG              (1U << 0U)    /* Watchdog interrupt */
+
+/* Defines for sc_irq_rtc_t */
+#define SC_IRQ_RTC               (1U << 0U)    /* RTC interrupt */
+
+/* Defines for sc_irq_wake_t */
+#define SC_IRQ_BUTTON            (1U << 0U)    /* Button interrupt */
+#define SC_IRQ_PAD               (1U << 1U)    /* Pad wakeup */
+#define SC_IRQ_USR1              (1U << 2U)    /* User defined 1 */
+#define SC_IRQ_USR2              (1U << 3U)    /* User defined 2 */
+#define SC_IRQ_BC_PAD            (1U << 4U)    /* Pad wakeup (broadcast to all partitions) */
+#define SC_IRQ_SW_WAKE           (1U << 5U)    /* Software requested wake */
+#define SC_IRQ_SECVIO            (1U << 6U)    /* Security violation */
+
+/* Defines for sc_irq_sysctr_t */
+#define SC_IRQ_SYSCTR            (1U << 0U)    /* SYSCTR interrupt */
+
+/* Types */
+
+/*
+ * This type is used to declare an interrupt group.
+ */
+typedef u8 sc_irq_group_t;
+
+/*
+ * This type is used to declare a bit mask of temp interrupts.
+ */
+typedef u8 sc_irq_temp_t;
+
+/*
+ * This type is used to declare a bit mask of watchdog interrupts.
+ */
+typedef u8 sc_irq_wdog_t;
+
+/*
+ * This type is used to declare a bit mask of RTC interrupts.
+ */
+typedef u8 sc_irq_rtc_t;
+
+/*
+ * This type is used to declare a bit mask of wakeup interrupts.
+ */
+typedef u8 sc_irq_wake_t;
+
+#endif /* SC_IRQ_API_H */
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
index 3629eb68d7a..a4b92b86cc6 100644
--- a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h
@@ -5,27 +5,45 @@
 
 #ifndef SC_MISC_API_H
 #define SC_MISC_API_H
+/* Defines for type widths */
+#define SC_MISC_DMA_GRP_W       5U      /* Width of sc_misc_dma_group_t */
 
+/* Max DMA channel priority group */
+#define SC_MISC_DMA_GRP_MAX     31U
 /* Defines for sc_misc_boot_status_t */
 #define SC_MISC_BOOT_STATUS_SUCCESS	0U	/* Success */
 #define SC_MISC_BOOT_STATUS_SECURITY	1U	/* Security violation */
 
-/* Defines for sc_misc_seco_auth_cmd_t */
-#define SC_MISC_SECO_AUTH_SECO_FW	0U   /* SECO Firmware */
-#define SC_MISC_SECO_AUTH_HDMI_TX_FW	1U   /* HDMI TX Firmware */
-#define SC_MISC_SECO_AUTH_HDMI_RX_FW	2U   /* HDMI RX Firmware */
-
 /* Defines for sc_misc_temp_t */
-#define SC_MISC_TEMP			0U	/* Temp sensor */
-#define SC_MISC_TEMP_HIGH		1U	/* Temp high alarm */
-#define SC_MISC_TEMP_LOW		2U	/* Temp low alarm */
+#define SC_MISC_TEMP                    0U   /* Temp sensor */
+#define SC_MISC_TEMP_HIGH               1U   /* Temp high alarm */
+#define SC_MISC_TEMP_LOW                2U   /* Temp low alarm */
+
+/* Defines for sc_misc_bt_t */
+#define SC_MISC_BT_PRIMARY              0U   /* Primary boot */
+#define SC_MISC_BT_SECONDARY            1U   /* Secondary boot */
+#define SC_MISC_BT_RECOVERY             2U   /* Recovery boot */
+#define SC_MISC_BT_MANUFACTURE          3U   /* Manufacture boot */
+#define SC_MISC_BT_SERIAL               4U   /* Serial boot */
+/* Types */
 
-/* Defines for sc_misc_seco_auth_cmd_t */
-#define SC_MISC_AUTH_CONTAINER	0U	/* Authenticate container */
-#define SC_MISC_VERIFY_IMAGE	1U	/* Verify image */
-#define SC_MISC_REL_CONTAINER	2U	/* Release container */
+/*
+ * This type is used to store a DMA channel priority group.
+ */
+typedef u8 sc_misc_dma_group_t;
 
+/*
+ * This type is used report boot status.
+ */
 typedef u8 sc_misc_boot_status_t;
+
+/*
+ * This type is used report boot status.
+ */
 typedef u8 sc_misc_temp_t;
 
+/*
+ * This type is used report the boot type.
+ */
+typedef u8 sc_misc_bt_t;
 #endif /* SC_MISC_API_H */
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h
index 9008b85c6f6..95956d74ffd 100644
--- a/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h
@@ -6,6 +6,14 @@
 #ifndef SC_PM_API_H
 #define SC_PM_API_H
 
+#include <asm/arch/sci/types.h>
+/* Defines for type widths */
+#define SC_PM_POWER_MODE_W      2U      /* Width of sc_pm_power_mode_t */
+#define SC_PM_CLOCK_MODE_W      3U      /* Width of sc_pm_clock_mode_t */
+#define SC_PM_RESET_TYPE_W      2U      /* Width of sc_pm_reset_type_t */
+#define SC_PM_RESET_REASON_W    4U      /* Width of sc_pm_reset_reason_t */
+/* Defines for ALL parameters */
+#define SC_PM_CLK_ALL   ((sc_pm_clk_t) UINT8_MAX)   /* All clocks */
 /* Defines for sc_pm_power_mode_t */
 #define SC_PM_PW_MODE_OFF	0U /* Power off */
 #define SC_PM_PW_MODE_STBY	1U /* Power in standby */
@@ -35,10 +43,91 @@
 #define SC_PM_CLK_MODE_AUTOGATE_HW	4U /* Clock is in HW autogate mode */
 #define SC_PM_CLK_MODE_AUTOGATE_SW_HW	5U /* Clock is in SW-HW autogate mode */
 
+/* Defines for sc_pm_clk_parent_t */
+#define SC_PM_PARENT_XTAL              0U    /*!< Parent is XTAL. */
+#define SC_PM_PARENT_PLL0              1U    /*!< Parent is PLL0 */
+#define SC_PM_PARENT_PLL1              2U    /*!< Parent is PLL1 or PLL0/2 */
+#define SC_PM_PARENT_PLL2              3U    /*!< Parent in PLL2 or PLL0/4 */
+#define SC_PM_PARENT_BYPS              4U    /*!< Parent is a bypass clock. */
+
+/* Defines for sc_pm_reset_type_t */
+#define SC_PM_RESET_TYPE_COLD          0U    /* Cold reset */
+#define SC_PM_RESET_TYPE_WARM          1U    /* Warm reset */
+#define SC_PM_RESET_TYPE_BOARD         2U    /* Board reset */
+
+/* Defines for sc_pm_reset_reason_t */
+#define SC_PM_RESET_REASON_POR         0U    /* Power on reset */
+#define SC_PM_RESET_REASON_JTAG        1U    /* JTAG reset */
+#define SC_PM_RESET_REASON_SW          2U    /* Software reset */
+#define SC_PM_RESET_REASON_WDOG        3U    /* Partition watchdog reset */
+#define SC_PM_RESET_REASON_LOCKUP      4U    /* SCU lockup reset */
+#define SC_PM_RESET_REASON_SNVS        5U    /* SNVS reset */
+#define SC_PM_RESET_REASON_TEMP        6U    /* Temp panic reset */
+#define SC_PM_RESET_REASON_MSI         7U    /* MSI reset */
+#define SC_PM_RESET_REASON_UECC        8U    /* ECC reset */
+#define SC_PM_RESET_REASON_SCFW_WDOG   9U    /* SCFW watchdog reset */
+#define SC_PM_RESET_REASON_ROM_WDOG    10U   /* SCU ROM watchdog reset */
+#define SC_PM_RESET_REASON_SECO        11U   /* SECO reset */
+#define SC_PM_RESET_REASON_SCFW_FAULT  12U   /* SCFW fault reset */
+
+/* Defines for sc_pm_sys_if_t */
+#define SC_PM_SYS_IF_INTERCONNECT       0U   /* System interconnect */
+#define SC_PM_SYS_IF_MU                 1U   /* AP -> SCU message units */
+#define SC_PM_SYS_IF_OCMEM              2U   /* On-chip memory (ROM/OCRAM) */
+#define SC_PM_SYS_IF_DDR                3U   /* DDR memory */
+
+/* Defines for sc_pm_wake_src_t */
+#define SC_PM_WAKE_SRC_NONE             0U   /* No wake source, used for self-kill */
+#define SC_PM_WAKE_SRC_SCU              1U   /* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */
+#define SC_PM_WAKE_SRC_IRQSTEER         2U   /* Wakeup from IRQSTEER to resume CPU (GIC powered down) */
+#define SC_PM_WAKE_SRC_IRQSTEER_GIC     3U   /* Wakeup from IRQSTEER+GIC to wake CPU  (GIC clock gated) */
+#define SC_PM_WAKE_SRC_GIC              4U   /* Wakeup from GIC to wake CPU */
+/* Types */
+
+/*
+ * This type is used to declare a power mode. Note resources only use
+ * SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only
+ * as system power modes.
+ */
 typedef u8 sc_pm_power_mode_t;
+
+/*
+ * This type is used to declare a clock.
+ */
 typedef u8 sc_pm_clk_t;
+
+/*
+ * This type is used to declare a clock mode.
+ */
 typedef u8 sc_pm_clk_mode_t;
+
+/*
+ * This type is used to declare the clock parent.
+ */
 typedef u8 sc_pm_clk_parent_t;
+
+/*
+ * This type is used to declare clock rates.
+ */
 typedef u32 sc_pm_clock_rate_t;
 
+/*
+ * This type is used to declare a desired reset type.
+ */
+typedef u8 sc_pm_reset_type_t;
+
+/*
+ * This type is used to declare a reason for a reset.
+ */
+typedef u8 sc_pm_reset_reason_t;
+
+/*
+ * This type is used to specify a system-level interface to be power managed.
+ */
+typedef u8 sc_pm_sys_if_t;
+
+/*
+ * This type is used to specify a wake source for CPU resources.
+ */
+typedef u8 sc_pm_wake_src_t;
 #endif /* SC_PM_API_H */
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h
index ed303881e73..bbc9de90162 100644
--- a/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h
@@ -38,32 +38,36 @@
 
 /* Types */
 
-/*!
+/*
  * This type is used to declare a resource partition.
  */
 typedef u8 sc_rm_pt_t;
 
-/*!
+/*
  * This type is used to declare a memory region.
  */
 typedef u8 sc_rm_mr_t;
 
-/*!
+/*
  * This type is used to declare a resource domain ID used by the
  * isolation HW.
  */
 typedef u8 sc_rm_did_t;
 
-/*!
+/*
  * This type is used to declare an SMMU StreamID.
  */
 typedef u16 sc_rm_sid_t;
 
-/*!
+/*
  * This type is a used to declare master transaction attributes.
  */
 typedef u8 sc_rm_spa_t;
 
+/*
+ * This type is used to declare a resource/memory region access permission.
+ * Refer to the XRDC2 Block Guide for more information.
+ */
 typedef u8 sc_rm_perm_t;
 
 #endif /* SC_RM_API_H */
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h
index 3ed05842d99..5963330d3ae 100644
--- a/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h
@@ -17,6 +17,7 @@
 #define SC_SECO_AUTH_SECO_FW            3U   /* SECO Firmware */
 #define SC_SECO_AUTH_HDMI_TX_FW         4U   /* HDMI TX Firmware */
 #define SC_SECO_AUTH_HDMI_RX_FW         5U   /* HDMI RX Firmware */
+#define SC_SECO_EVERIFY_IMAGE           6U   /* Enhanced verify image */
 
 #define SC_SECO_RNG_STAT_UNAVAILABLE    0U  /* Unable to initialize the RNG */
 #define SC_SECO_RNG_STAT_INPROGRESS     1U  /* Initialization is on-going */
@@ -24,12 +25,12 @@
 
 /* Types */
 
-/*!
+/*
  * This type is used to issue SECO authenticate commands.
  */
 typedef u8 sc_seco_auth_cmd_t;
 
-/*!
+/*
  * This type is used to return the RNG initialization status.
  */
 typedef u32 sc_seco_rng_stat_t;
diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h
new file mode 100644
index 00000000000..d5750444b30
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+
+#ifndef SC_TIMER_API_H
+#define SC_TIMER_API_H
+
+/* Defines */
+
+/* Defines for type widths */
+#define SC_TIMER_ACTION_W   3U      /* Width of sc_timer_wdog_action_t */
+
+/* Defines for sc_timer_wdog_action_t */
+#define SC_TIMER_WDOG_ACTION_PARTITION      0U   /* Reset partition */
+#define SC_TIMER_WDOG_ACTION_WARM           1U   /* Warm reset system */
+#define SC_TIMER_WDOG_ACTION_COLD           2U   /* Cold reset system */
+#define SC_TIMER_WDOG_ACTION_BOARD          3U   /* Reset board */
+#define SC_TIMER_WDOG_ACTION_IRQ            4U   /* Only generate IRQs */
+
+/* Types */
+
+/*
+ * This type is used to configure the watchdog action.
+ */
+typedef u8 sc_timer_wdog_action_t;
+
+/*
+ * This type is used to declare a watchdog time value in milliseconds.
+ */
+typedef u32 sc_timer_wdog_time_t;
+
+#endif /* SC_TIMER_API_H */
diff --git a/arch/arm/include/asm/arch-imx8/sci/types.h b/arch/arm/include/asm/arch-imx8/sci/types.h
index adfed13e330..36d5dee96e3 100644
--- a/arch/arm/include/asm/arch-imx8/sci/types.h
+++ b/arch/arm/include/asm/arch-imx8/sci/types.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier:     GPL-2.0+ */
 /*
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
  */
 
 #ifndef SC_TYPES_H
@@ -19,6 +19,7 @@ typedef u64 sc_ipc_t;
 /* Defines for common frequencies */
 #define SC_32KHZ            32768U   /* 32KHz */
 #define SC_10MHZ         10000000U   /* 10MHz */
+#define SC_16MHZ         16000000U   /* 16MHz */
 #define SC_20MHZ         20000000U   /* 20MHz */
 #define SC_25MHZ         25000000U   /* 25MHz */
 #define SC_27MHZ         27000000U   /* 27MHz */
@@ -58,21 +59,33 @@ typedef u64 sc_ipc_t;
 #define SC_594MHZ       594000000U   /* 594MHz */
 #define SC_625MHZ       625000000U   /* 625MHz */
 #define SC_640MHZ       640000000U   /* 640MHz */
+#define SC_648MHZ       648000000U   /* 648MHz */
 #define SC_650MHZ       650000000U   /* 650MHz */
 #define SC_667MHZ       666666667U   /* 667MHz */
 #define SC_675MHZ       675000000U   /* 675MHz */
 #define SC_700MHZ       700000000U   /* 700MHz */
 #define SC_720MHZ       720000000U   /* 720MHz */
 #define SC_750MHZ       750000000U   /* 750MHz */
+#define SC_753MHZ       753000000U   /* 753MHz */
+#define SC_793MHZ       793000000U   /* 793MHz */
 #define SC_800MHZ       800000000U   /* 800MHz */
 #define SC_850MHZ       850000000U   /* 850MHz */
+#define SC_858MHZ       858000000U   /* 858MHz */
 #define SC_900MHZ       900000000U   /* 900MHz */
+#define SC_953MHZ       953000000U   /* 953MHz */
+#define SC_963MHZ       963000000U   /* 963MHz */
 #define SC_1000MHZ     1000000000U   /* 1GHz */
 #define SC_1060MHZ     1060000000U   /* 1.06GHz */
+#define SC_1068MHZ     1068000000U   /* 1.068GHz */
+#define SC_1121MHZ     1121000000U   /* 1.121GHz */
+#define SC_1173MHZ     1173000000U   /* 1.173GHz */
 #define SC_1188MHZ     1188000000U   /* 1.188GHz */
 #define SC_1260MHZ     1260000000U   /* 1.26GHz */
+#define SC_1278MHZ     1278000000U   /* 1.278GHz */
 #define SC_1280MHZ     1280000000U   /* 1.28GHz */
 #define SC_1300MHZ     1300000000U   /* 1.3GHz */
+#define SC_1313MHZ     1313000000U   /* 1.313GHz */
+#define SC_1345MHZ     1345000000U   /* 1.345GHz */
 #define SC_1400MHZ     1400000000U   /* 1.4GHz */
 #define SC_1500MHZ     1500000000U   /* 1.5GHz */
 #define SC_1600MHZ     1600000000U   /* 1.6GHz */
@@ -119,7 +132,6 @@ typedef u64 sc_ipc_t;
 #define SC_755MHZ       755250000U   /* 755.25MHz */
 
 /* Defines for type widths */
-#define SC_FADDR_W      36U          /* Width of sc_faddr_t */
 #define SC_BOOL_W       1U           /* Width of sc_bool_t */
 #define SC_ERR_W        4U           /* Width of sc_err_t */
 #define SC_RSRC_W       10U          /* Width of sc_rsrc_t */
@@ -191,9 +203,23 @@ typedef u64 sc_ipc_t;
 #define SC_C_RST0                       43U
 #define SC_C_RST1                       44U
 #define SC_C_SEL0                       45U
-#define SC_C_LAST                       46U
-
-#define SC_P_ALL        ((sc_pad_t)UINT16_MAX)   /* All pads */
+#define SC_C_CALIB0                     46U
+#define SC_C_CALIB1                     47U
+#define SC_C_CALIB2                     48U
+#define SC_C_IPG_DEBUG                  49U
+#define SC_C_IPG_DOZE                   50U
+#define SC_C_IPG_WAIT                   51U
+#define SC_C_IPG_STOP                   52U
+#define SC_C_IPG_STOP_MODE              53U
+#define SC_C_IPG_STOP_ACK               54U
+#define SC_C_SYNC_CTRL                  55U
+#define SC_C_OFS_AUDIO_ALT              56U
+#define SC_C_DSP_BYP                    57U
+#define SC_C_CLK_GEN_EN                 58U
+#define SC_C_INTF_SEL                   59U
+#define SC_C_RXC_DLY                    60U
+#define SC_C_TIMER_SEL                  61U
+#define SC_C_LAST                       62U
 
 /* Types */
 
diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h b/arch/arm/include/asm/arch-imx8/sys_proto.h
index 6f1fc8f999d..e4bd2961730 100644
--- a/arch/arm/include/asm/arch-imx8/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8/sys_proto.h
@@ -21,7 +21,7 @@ struct pass_over_info_t {
 	u32 g_ap_mu;
 };
 
-extern unsigned long boot_pointer[];
+extern unsigned long rom_pointer[];
 void build_info(void);
 enum boot_device get_boot_device(void);
 int print_bootinfo(void);
diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h
index c705dfdf460..d6184ca0cb7 100644
--- a/arch/arm/include/asm/arch-imx8m/clock.h
+++ b/arch/arm/include/asm/arch-imx8m/clock.h
@@ -253,12 +253,16 @@ void dram_pll_init(ulong pll_val);
 void dram_enable_bypass(ulong clk_val);
 void dram_disable_bypass(void);
 u32 imx_get_fecclk(void);
+u32 imx_get_eqos_csr_clk(void);
+int imx_eqos_txclk_set_rate(unsigned long rate);
 u32 imx_get_uartclk(void);
 int clock_init(void);
 void init_clk_usdhc(u32 index);
+void init_nand_clk(void);
 void init_uart_clk(u32 index);
 void init_usb_clk(void);
 void init_wdog_clk(void);
+void init_clk_ecspi(u32 index);
 unsigned int mxc_get_clock(enum mxc_clock clk);
 int clock_enable(enum clk_ccgr_index index, bool enable);
 int clock_root_enabled(enum clk_root_index clock_id);
@@ -272,8 +276,11 @@ int clock_get_postdiv(enum clk_root_index clock_id,
 int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
 void mxs_set_lcdclk(u32 base_addr, u32 freq);
 int set_clk_qspi(void);
+void init_clk_fspi(int index);
 void enable_ocotp_clk(unsigned char enable);
 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
 int set_clk_enet(enum enet_freq type);
 int set_clk_eqos(enum enet_freq type);
 void hab_caam_clock_enable(unsigned char enable);
+void enable_usboh3_clk(unsigned char enable);
+u32 get_dsi_phy_ref_clk(void);
diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h
index 0f1e832c038..5e4fbecf052 100644
--- a/arch/arm/include/asm/arch-imx8m/ddr.h
+++ b/arch/arm/include/asm/arch-imx8m/ddr.h
@@ -724,6 +724,8 @@ void ddrphy_init_read_msg_block(enum fw_type type);
 void update_umctl2_rank_space_setting(unsigned int pstat_num);
 void get_trained_CDD(unsigned int fsp);
 
+ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr);
+
 static inline void reg32_write(unsigned long addr, u32 val)
 {
 	writel(val, addr);
@@ -740,9 +742,9 @@ static inline void reg32setbit(unsigned long addr, u32 bit)
 }
 
 #define dwc_ddrphy_apb_wr(addr, data) \
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data)
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr), data)
 #define dwc_ddrphy_apb_rd(addr) \
-	reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr))
+	reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr))
 
 extern struct dram_cfg_param ddrphy_trained_csr[];
 extern uint32_t ddrphy_trained_csr_num;
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 45d95a7c197..333e57c603a 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -13,58 +13,212 @@
 #define ROM_VERSION_A0		IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
 #define ROM_VERSION_B0		IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
 
-#define M4_BOOTROM_BASE_ADDR   0x007E0000
-
-#define GPIO1_BASE_ADDR		0X30200000
+#define MCU_BOOTROM_BASE_ADDR	0x007E0000
+
+#define SAI1_BASE_ADDR		0x30010000
+#define SAI6_BASE_ADDR		0x30030000
+#define SAI5_BASE_ADDR		0x30040000
+#define SAI4_BASE_ADDR		0x30050000
+#define SPBA2_BASE_ADDR		0x300F0000
+#define AIPS1_BASE_ADDR		0x301F0000
+#define GPIO1_BASE_ADDR		0x30200000
 #define GPIO2_BASE_ADDR		0x30210000
 #define GPIO3_BASE_ADDR		0x30220000
 #define GPIO4_BASE_ADDR		0x30230000
 #define GPIO5_BASE_ADDR		0x30240000
+#define ANA_TSENSOR_ADDR	0x30260000
+#define ANA_OSC_BASE_ADDR	0x30270000
 #define WDOG1_BASE_ADDR		0x30280000
 #define WDOG2_BASE_ADDR		0x30290000
 #define WDOG3_BASE_ADDR		0x302A0000
+#ifdef CONFIG_IMX8MP
+#define OCRAM_MECC_BASE_ADDR	0x302B0000
+#define OCRAM_S_MECC_BASE_ADDR	0x302C0000
+#else
+#define SDMA3_BASE_ADDR		0x302B0000
+#define SDMA2_BASE_ADDR		0x302C0000
+#endif
+#define GPT1_BASE_ADDR		0x302D0000
+#define GPT2_BASE_ADDR		0x302E0000
+#define GPT3_BASE_ADDR		0x302F0000
+#define ROMCP_BASE_ADDR		0x30310000
+#define LCDIF_BASE_ADDR_IMX8MQ		0x30320000
 #define IOMUXC_BASE_ADDR	0x30330000
 #define IOMUXC_GPR_BASE_ADDR	0x30340000
 #define OCOTP_BASE_ADDR		0x30350000
 #define ANATOP_BASE_ADDR	0x30360000
+#define SNVS_HP_BASE_ADDR	0x30370000
 #define CCM_BASE_ADDR		0x30380000
 #define SRC_BASE_ADDR		0x30390000
 #define GPC_BASE_ADDR		0x303A0000
-
+#define SEMA1_BASE_ADDR		0x303B0000
+#define SEMA2_BASE_ADDR		0x303C0000
+#define RDC_BASE_ADDR		0x303D0000
+#define CSU_BASE_ADDR		0x303E0000
+
+#define AIPS2_BASE_ADDR		0x305F0000
+#define PWM1_BASE_ADDR		0x30660000
+#define PWM2_BASE_ADDR		0x30670000
+#define PWM3_BASE_ADDR		0x30680000
+#define PWM4_BASE_ADDR		0x30690000
 #define SYSCNT_RD_BASE_ADDR	0x306A0000
 #define SYSCNT_CMP_BASE_ADDR	0x306B0000
 #define SYSCNT_CTRL_BASE_ADDR	0x306C0000
-
+#define GPT6_BASE_ADDR		0x306E0000
+#define GPT5_BASE_ADDR		0x306F0000
+#define GPT4_BASE_ADDR		0x30700000
+#define PERFMON1_ADDR		0x307C0000
+#define PERFMON2_ADDR		0x307D0000
+#define QOSC_BASE_ADDR		0x307F0000
+
+#define SPDIF1_BASE_ADDR	0x30810000
+#define ECSPI1_BASE_ADDR	0x30820000
+#define ECSPI2_BASE_ADDR	0x30830000
+#define ECSPI3_BASE_ADDR	0x30840000
 #define UART1_BASE_ADDR		0x30860000
 #define UART3_BASE_ADDR		0x30880000
 #define UART2_BASE_ADDR		0x30890000
+
+#define SPDIF2_BASE_ADDR	0x308A0000
+#define SAI2_BASE_ADDR		0x308B0000
+#define SAI3_BASE_ADDR		0x308C0000
+#define CANFD1_BASE_ADDR	0x308C0000
+#define CANFD2_BASE_ADDR	0x308D0000
+#define SPBA_BASE_ADDR		0x308F0000
+#define CAAM_BASE_ADDR		0x30900000
+#define AIPS3_BASE_ADDR		0x309F0000
+#define MIPI_PHY_BASE_ADDR_IMX8MQ	0x30A00000
+#define MIPI_DSI_BASE_ADDR_IMX8MQ	0x30A10000
 #define I2C1_BASE_ADDR		0x30A20000
 #define I2C2_BASE_ADDR		0x30A30000
 #define I2C3_BASE_ADDR		0x30A40000
 #define I2C4_BASE_ADDR		0x30A50000
 #define UART4_BASE_ADDR		0x30A60000
+#define MIPI_CSI_BASE_ADDR_IMX8MQ	0x30A70000
+#define MIPI_CSI_PHY1_BASE_ADDR_IMX8MQ	0x30A80000
+#define IRQ_STEER_BASE_ADDR	0x30A80000
+#define CSI1_BASE_ADDR_IMX8MQ		0x30A90000
+#define MU_A_BASE_ADDR		0x30AA0000
+#define MU_B_BASE_ADDR		0x30AB0000
+#define SEMAPHOR_HS_BASE_ADDR	0x30AC0000
+#define I2C5_BASE_ADDR		0x30AD0000
+#define I2C6_BASE_ADDR		0x30AE0000
 #define USDHC1_BASE_ADDR	0x30B40000
 #define USDHC2_BASE_ADDR	0x30B50000
-#ifdef CONFIG_IMX8MM
 #define USDHC3_BASE_ADDR	0x30B60000
-#endif
+#define MIPI_CS2_BASE_ADDR	0x30B60000
+#define MIPI_CSI_PHY2_BASE_ADDR	0x30B70000
+#define CSI2_BASE_ADDR		0x30B80000
+#define QSPI0_BASE_ADDR		0x30BB0000
+#define QSPI0_AMBA_BASE		0x08000000
+#define SDMA1_BASE_ADDR		0x30BD0000
+#define ENET1_BASE_ADDR		0x30BE0000
+#define ENET2_TSN_BASE_ADDR	0x30BF0000
+#define HDMI_CTRL_BASE_ADDR	0x32C00000
+#define AIPS4_BASE_ADDR		0x32DF0000
+#ifdef CONFIG_IMX8MQ
+#define DC1_BASE_ADDR		0x32E00000
+#define DC2_BASE_ADDR		0x32E10000
+#define DC3_BASE_ADDR		0x32E20000
+#define HDMI_SEC_BASE_ADDR	0x32E40000
+#define TZASC_BASE_ADDR		0x32F80000
+#define MTR_BASE_ADDR		0x32FB0000
+#define PLATFORM_CTRL_BASE_ADDR	0x32FE0000
+
+#define USB1_BASE_ADDR		0x38100000
+#define USB2_BASE_ADDR		0x38200000
+#define USB1_PHY_BASE_ADDR	0x381F0000
+#define USB2_PHY_BASE_ADDR	0x382F0000
+
+#elif defined(CONFIG_IMX8MP)
+#define ISI_BASE_ADDR		0x32E00000
+#define ISP1_BASE_ADDR		0x32E10000
+#define ISP2_BASE_ADDR		0x32E20000
+#define IPS_DEWARP_BASE_ADDR	0x32E30000
+#define MIPI_CSI1_BASE_ADDR	0x32E40000
+#define MIPI_CSI2_BASE_ADDR	0x32E50000
+#define MIPI_DSI_BASE_ADDR	0x32E60000
+#define LCDIF1_BASE_ADDR	0x32E80000
+#define LCDIF2_BASE_ADDR	0x32E90000
+#define LCDIF_BASE_ADDR		LCDIF1_BASE_ADDR
+#define LVDS1_BASE_ADDR		0x32EA0000
+#define LVDS2_BASE_ADDR		0x32EB0000
+#define MEDIAMIX_CTRL_BASE_ADDR	0x32EC0000
+#define PCIE_PHY1_BASE_ADDR	0x32F00000
+#define HSIOMIX_CTRL_BASE_ADDR	0x32F10000
+#define TZASC_BASE_ADDR		0x32F80000
+#define HDMI_TX_BASE_ADDR	0x32FC0000
+#define NOC_CTRL_BASE_ADDR	0x32FE0000
+
+#define USB1_BASE_ADDR		0x38100000
+#define USB2_BASE_ADDR		0x38200000
+#define USB1_PHY_BASE_ADDR	0x381F0000
+#define USB2_PHY_BASE_ADDR	0x382F0000
 
+#else
+#define LCDIF_BASE_ADDR		0x32E00000
+#define MIPI_DSI_BASE_ADDR	0x32E10000
+#define CSI_BASE_ADDR		0x32E20000
+#define ISI_BASE_ADDR		0x32E20000
+#define MIPI_CSI_BASE_ADDR	0x32E30000
+#define USB1_BASE_ADDR		0x32E40000
+#define USB2_BASE_ADDR		0x32E50000
+#define PCIE_PHY1_BASE_ADDR	0x32F00000
 #define TZASC_BASE_ADDR		0x32F80000
+#define PLAT_CTRL_BASE_ADDR	0x32FE0000
+#endif
+
+#define MXS_APBH_BASE		0x33000000
+#define MXS_GPMI_BASE		0x33002000
+#define MXS_BCH_BASE		0x33004000
+
+
+#define USB_BASE_ADDR		USB1_BASE_ADDR
 
 #define MXS_LCDIF_BASE		IS_ENABLED(CONFIG_IMX8MQ) ? \
-					0x30320000 : 0x32e00000
+								LCDIF_BASE_ADDR_IMX8MQ : LCDIF_BASE_ADDR
+
+#define IOMUXC_GPR0		(IOMUXC_GPR_BASE_ADDR + 0x00)
+#define IOMUXC_GPR1		(IOMUXC_GPR_BASE_ADDR + 0x04)
+#define IOMUXC_GPR2		(IOMUXC_GPR_BASE_ADDR + 0x08)
+#define IOMUXC_GPR3		(IOMUXC_GPR_BASE_ADDR + 0x0c)
+#define IOMUXC_GPR4		(IOMUXC_GPR_BASE_ADDR + 0x10)
+#define IOMUXC_GPR5		(IOMUXC_GPR_BASE_ADDR + 0x14)
+#define IOMUXC_GPR6		(IOMUXC_GPR_BASE_ADDR + 0x18)
+#define IOMUXC_GPR7		(IOMUXC_GPR_BASE_ADDR + 0x1c)
+#define IOMUXC_GPR8		(IOMUXC_GPR_BASE_ADDR + 0x20)
+#define IOMUXC_GPR9		(IOMUXC_GPR_BASE_ADDR + 0x24)
+#define IOMUXC_GPR10		(IOMUXC_GPR_BASE_ADDR + 0x28)
+#define IOMUXC_GPR11		(IOMUXC_GPR_BASE_ADDR + 0x2C)
+#define IOMUXC_GPR22		(IOMUXC_GPR_BASE_ADDR + 0x58)
+
+#define CNTCR_OFF	0x00
+#define CNTFID0_OFF	0x20
+#define CNTFID1_OFF	0x24
+
+#define SC_CNTCR_ENABLE		(1 << 0)
+#define SC_CNTCR_HDBG		(1 << 1)
+#define SC_CNTCR_FREQ0		(1 << 8)
+#define SC_CNTCR_FREQ1		(1 << 9)
+
+#define IMX_CSPI1_BASE		0x30820000
+#define IMX_CSPI2_BASE		0x30830000
+#define IMX_CSPI3_BASE		0x30840000
+
+#define MXC_SPI_BASE_ADDRESSES \
+	IMX_CSPI1_BASE, \
+	IMX_CSPI2_BASE, \
+	IMX_CSPI3_BASE
 
 #define SRC_IPS_BASE_ADDR	0x30390000
 #define SRC_DDRC_RCR_ADDR	0x30391000
 #define SRC_DDRC2_RCR_ADDR	0x30391004
+#define SRC_DDR1_ENABLE_MASK		0x8F000000UL
 
 #define DDRC_DDR_SS_GPR0	0x3d000000
 #define DDRC_IPS_BASE_ADDR(X)	(0x3d400000 + ((X) * 0x2000000))
 #define DDR_CSD1_BASE_ADDR	0x40000000
 
-#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
-#define FEC_QUIRK_ENET_MAC
-
 #define CAAM_ARB_BASE_ADDR              (0x00100000)
 #define CAAM_ARB_END_ADDR               (0x00107FFF)
 #define CAAM_IPS_BASE_ADDR              (0x30900000)
@@ -72,6 +226,7 @@
 #define CONFIG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR + \
 					 CONFIG_SYS_FSL_SEC_OFFSET)
 #define CONFIG_SYS_FSL_JR0_OFFSET       (0x1000)
+#define CONFIG_SYS_FSL_JR1_OFFSET       (0x2000)
 #define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR + \
 					 CONFIG_SYS_FSL_JR0_OFFSET)
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC   1
@@ -96,8 +251,15 @@
 #define SRC_DDR1_RCR_CORE_RESET_N_MASK	BIT(1)
 #define SRC_DDR1_RCR_PRESET_N_MASK	BIT(0)
 
+#define FEC_QUIRK_ENET_MAC
+#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u
+#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
+
+#define SNVS_HPSR              (SNVS_HP_BASE_ADDR + 0x14)
+
 struct iomuxc_gpr_base_regs {
-	u32 gpr[47];
+	u32 gpr[48];
 };
 
 struct ocotp_regs {
@@ -515,5 +677,17 @@ struct pgc_reg {
 	u32 pgauxsw;
 	u32 pgdr;
 };
+
+
+#include <stdbool.h>
+bool is_usb_boot(void);
+#define is_boot_from_usb  is_usb_boot
+
+#if defined(CONFIG_IMX8MP) || defined(CONFIG_IMX8MQ)
+#define disconnect_from_pc(void) clrbits_le32(USB1_BASE_ADDR + 0xc704, (1 << 31));
+#else
+#define disconnect_from_pc(void) writel(0x0, USB1_BASE_ADDR + 0x140)
+#endif
+
 #endif
 #endif
diff --git a/arch/arm/include/asm/arch-imx8m/imx8m_csu.h b/arch/arm/include/asm/arch-imx8m/imx8m_csu.h
new file mode 100644
index 00000000000..fffe71af584
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/imx8m_csu.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef IMX_CSU_H
+#define IMX_CSU_H
+
+#include <common.h>
+
+#define CSU_SEC_LEVEL_0		0xff
+#define CSU_SEC_LEVEL_1		0xbb
+#define CSU_SEC_LEVEL_2		0x3f
+#define CSU_SEC_LEVEL_3		0x3b
+#define CSU_SEC_LEVEL_4		0x33
+#define CSU_SEC_LEVEL_5		0x22
+#define CSU_SEC_LEVEL_6		0x03
+#define CSU_SEC_LEVEL_7		0x0
+
+#define IMX_CSU_BASE		UL(0x303e0000)
+
+#define LOCKED			0x1
+#define UNLOCKED		0x0
+
+#define CSLx_REG(x)		(IMX_CSU_BASE + ((x) / 2) * 4)
+#define CSLx_LOCK(x)		((0x1 << (((x) % 2) * 16 + 8)))
+#define CSLx_CFG(x, n)		((x) << (((n) % 2) * 16))
+
+#define CSU_HP_REG(x)		(IMX_CSU_BASE + ((x) / 16) * 4 + 0x200)
+#define CSU_HP_LOCK(x)		((0x1 << (((x) % 16) * 2 + 1)))
+#define CSU_HP_CFG(x, n)	((x) << (((n) % 16) * 2))
+
+#define CSU_SA_REG(x)		(IMX_CSU_BASE + ((x) / 16) * 4 + 0x218)
+#define CSU_SA_LOCK(x)		((0x1 << (((x) % 16) * 2 + 1)))
+#define CSU_SA_CFG(x, n)	((x) << (((n) % 16) * 2))
+
+#define CSU_HPCONTROL_REG(x)		(IMX_CSU_BASE + (((x) / 16) * 4) + 0x358)
+#define CSU_HPCONTROL_LOCK(x)		((0x1 << (((x) % 16) * 2 + 1)))
+#define CSU_HPCONTROL_CFG(x, n)		((x) << (((n) % 16) * 2))
+
+enum csu_cfg_type {
+	CSU_INVALID,
+	CSU_CSL,
+	CSU_HP,
+	CSU_SA,
+	CSU_HPCONTROL,
+};
+
+struct imx_csu_cfg {
+	enum csu_cfg_type type;
+	uint16_t idx;
+	uint16_t lock : 1;
+	uint16_t csl_level : 8;
+	uint16_t hp : 1;
+	uint16_t sa : 1;
+	uint16_t hpctrl : 1;
+};
+
+#define CSU_CSLx(i, level, lk)	\
+	{CSU_CSL, .idx = (i), .csl_level = (level), .lock = (lk),}
+
+#define CSU_HPx(i, val, lk)	\
+	{CSU_HP, .idx = (i), .hp = (val), .lock =(lk), }
+
+#define CSU_SA(i, val, lk)	\
+	{CSU_SA, .idx = (i), .sa = (val), .lock = (lk), }
+
+#define CSU_HPCTRL(i, val, lk)	\
+	{CSU_HPCONTROL, .idx = (i), .hpctrl = (val), .lock = (lk), }
+
+void imx_csu_init(const struct imx_csu_cfg *csu_cfg);
+
+#endif /* IMX_CSU_H */
diff --git a/arch/arm/include/asm/arch-imx8m/imx8m_rdc.h b/arch/arm/include/asm/arch-imx8m/imx8m_rdc.h
new file mode 100644
index 00000000000..c68759e456b
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/imx8m_rdc.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2019, NXP. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IMX_RDC_H
+#define IMX_RDC_H
+
+#include <common.h>
+
+#define IMX_RDC_BASE	UL(0x303D0000)
+
+#define MDAn(x)		(IMX_RDC_BASE + 0x200 + (x) * 4)
+#define PDAPn(x)	(IMX_RDC_BASE + 0x400 + (x) * 4)
+#define MRSAn(x)	(IMX_RDC_BASE + 0x800 + (x) * 0x10)
+#define MREAn(x)	(IMX_RDC_BASE + 0x804 + (x) * 0x10)
+#define MRCn(x)		(IMX_RDC_BASE + 0x808 + (x) * 0x10)
+
+#define LCK		BIT(31)
+#define SREQ		BIT(30)
+#define ENA		BIT(30)
+
+#define DID0		UL(0x0)
+#define DID1		UL(0x1)
+#define DID2		UL(0x2)
+#define DID3		UL(0x3)
+
+#define D3R		BIT(7)
+#define D3W		BIT(6)
+#define D2R		BIT(5)
+#define D2W		BIT(4)
+#define D1R		BIT(3)
+#define D1W		BIT(2)
+#define D0R		BIT(1)
+#define D0W		BIT(0)
+
+union rdc_setting {
+	uint32_t rdc_mda; /* Master Domain Assignment */
+	uint32_t rdc_pdap; /* Peripheral Domain Access Permissions */
+	uint32_t rdc_mem_region[3]; /* Memory Region Access Control */
+};
+
+enum rdc_type {
+	RDC_INVALID,
+	RDC_MDA,
+	RDC_PDAP,
+	RDC_MEM_REGION,
+};
+
+struct imx_rdc_cfg {
+	enum rdc_type type; /* config type Master, Peripheral or Memory region */
+	int index;
+	union rdc_setting setting;
+};
+
+#define RDC_MDAn(i, mda)	\
+	{RDC_MDA, (i), .setting.rdc_mda = (mda), }
+#define RDC_PDAPn(i, pdap)	\
+	{RDC_PDAP, (i), .setting.rdc_pdap = (pdap), }
+
+#define RDC_MEM_REGIONn(i, msa, mea, mrc)	\
+	{ RDC_MEM_REGION, (i), 			\
+	  .setting.rdc_mem_region[0] = (msa),	\
+	  .setting.rdc_mem_region[1] = (mea),	\
+	  .setting.rdc_mem_region[2] = (mrc),	\
+	}
+
+void imx_rdc_init(const struct imx_rdc_cfg *cfg);
+
+#endif /* IMX_RDC_H */
+
diff --git a/arch/arm/include/asm/arch-imx8m/imx8mn_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mn_pins.h
index b4298f2b838..fd44f1b5cfe 100644
--- a/arch/arm/include/asm/arch-imx8m/imx8mn_pins.h
+++ b/arch/arm/include/asm/arch-imx8m/imx8mn_pins.h
@@ -10,10 +10,10 @@
 
 enum {
 	IMX8MN_PAD_BOOT_MODE2__CCMSRCGPCMIX_BOOT_MODE2                          = IOMUX_PAD(0x025C, 0x0020, 0, 0x0000, 0, 0),
-	IMX8MN_PAD_BOOT_MODE2__I2C1_SCL                                         = IOMUX_PAD(0x025C, 0x0020, 1, 0x055C, 3, 0),
+	IMX8MN_PAD_BOOT_MODE2__I2C1_SCL                                         = IOMUX_PAD(0x025C, 0x0020, 1 | IOMUX_CONFIG_SION, 0x055C, 3, 0),
 
 	IMX8MN_PAD_BOOT_MODE3__CCMSRCGPCMIX_BOOT_MODE3                          = IOMUX_PAD(0x0260, 0x0024, 0, 0x0000, 0, 0),
-	IMX8MN_PAD_BOOT_MODE3__I2C1_SDA                                         = IOMUX_PAD(0x0260, 0x0024, 1, 0x056C, 3, 0),
+	IMX8MN_PAD_BOOT_MODE3__I2C1_SDA                                         = IOMUX_PAD(0x0260, 0x0024, 1 | IOMUX_CONFIG_SION, 0x056C, 3, 0),
 
 	IMX8MN_PAD_GPIO1_IO00__GPIO1_IO0                                        = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0),
 	IMX8MN_PAD_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT               = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0),
@@ -224,28 +224,28 @@ enum {
 
 	IMX8MN_PAD_SD1_DATA4__USDHC1_DATA4                                      = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0),
 	IMX8MN_PAD_SD1_DATA4__ENET1_RGMII_TX_CTL                                = IOMUX_PAD(0x0320, 0x00B8, 1, 0x0000, 0, 0),
-	IMX8MN_PAD_SD1_DATA4__I2C1_SCL                                          = IOMUX_PAD(0x0320, 0x00B8, 3, 0x055C, 1, 0),
+	IMX8MN_PAD_SD1_DATA4__I2C1_SCL                                          = IOMUX_PAD(0x0320, 0x00B8, 3 | IOMUX_CONFIG_SION, 0x055C, 1, 0),
 	IMX8MN_PAD_SD1_DATA4__UART2_DCE_RTS_B                                   = IOMUX_PAD(0x0320, 0x00B8, 4, 0x04F8, 4, 0),
 	IMX8MN_PAD_SD1_DATA4__UART2_DTE_CTS_B                                   = IOMUX_PAD(0x0320, 0x00B8, 4, 0x0000, 0, 0),
 	IMX8MN_PAD_SD1_DATA4__GPIO2_IO6                                         = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0),
 
 	IMX8MN_PAD_SD1_DATA5__USDHC1_DATA5                                      = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0),
 	IMX8MN_PAD_SD1_DATA5__ENET1_TX_ER                                       = IOMUX_PAD(0x0324, 0x00BC, 1, 0x0000, 0, 0),
-	IMX8MN_PAD_SD1_DATA5__I2C1_SDA                                          = IOMUX_PAD(0x0324, 0x00BC, 3, 0x056C, 1, 0),
+	IMX8MN_PAD_SD1_DATA5__I2C1_SDA                                          = IOMUX_PAD(0x0324, 0x00BC, 3 | IOMUX_CONFIG_SION, 0x056C, 1, 0),
 	IMX8MN_PAD_SD1_DATA5__UART2_DCE_CTS_B                                   = IOMUX_PAD(0x0324, 0x00BC, 4, 0x0000, 0, 0),
 	IMX8MN_PAD_SD1_DATA5__UART2_DTE_RTS_B                                   = IOMUX_PAD(0x0324, 0x00BC, 4, 0x04F8, 5, 0),
 	IMX8MN_PAD_SD1_DATA5__GPIO2_IO7                                         = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0),
 
 	IMX8MN_PAD_SD1_DATA6__USDHC1_DATA6                                      = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0),
 	IMX8MN_PAD_SD1_DATA6__ENET1_RGMII_RX_CTL                                = IOMUX_PAD(0x0328, 0x00C0, 1, 0x0574, 1, 0),
-	IMX8MN_PAD_SD1_DATA6__I2C2_SCL                                          = IOMUX_PAD(0x0328, 0x00C0, 3, 0x05D0, 1, 0),
+	IMX8MN_PAD_SD1_DATA6__I2C2_SCL                                          = IOMUX_PAD(0x0328, 0x00C0, 3 | IOMUX_CONFIG_SION, 0x05D0, 1, 0),
 	IMX8MN_PAD_SD1_DATA6__UART3_DCE_TX                                      = IOMUX_PAD(0x0328, 0x00C0, 4, 0x0000, 0, 0),
 	IMX8MN_PAD_SD1_DATA6__UART3_DTE_RX                                      = IOMUX_PAD(0x0328, 0x00C0, 4, 0x0504, 4, 0),
 	IMX8MN_PAD_SD1_DATA6__GPIO2_IO8                                         = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0),
 
 	IMX8MN_PAD_SD1_DATA7__USDHC1_DATA7                                      = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0),
 	IMX8MN_PAD_SD1_DATA7__ENET1_RX_ER                                       = IOMUX_PAD(0x032C, 0x00C4, 1, 0x05C8, 1, 0),
-	IMX8MN_PAD_SD1_DATA7__I2C2_SDA                                          = IOMUX_PAD(0x032C, 0x00C4, 3, 0x0560, 1, 0),
+	IMX8MN_PAD_SD1_DATA7__I2C2_SDA                                          = IOMUX_PAD(0x032C, 0x00C4, 3 | IOMUX_CONFIG_SION, 0x0560, 1, 0),
 	IMX8MN_PAD_SD1_DATA7__UART3_DCE_RX                                      = IOMUX_PAD(0x032C, 0x00C4, 4, 0x0504, 5, 0),
 	IMX8MN_PAD_SD1_DATA7__UART3_DTE_TX                                      = IOMUX_PAD(0x032C, 0x00C4, 4, 0x0000, 0, 0),
 	IMX8MN_PAD_SD1_DATA7__GPIO2_IO9                                         = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0),
@@ -253,13 +253,13 @@ enum {
 	IMX8MN_PAD_SD1_RESET_B__USDHC1_RESET_B                                  = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0),
 	IMX8MN_PAD_SD1_RESET_B__ENET1_TX_CLK                              = IOMUX_PAD(0x0330, 0x00C8, 1, 0x05A4, 1, 0),
 	IMX8MN_PAD_SD1_RESET_B__CCMSRCGPCMIX_ENET_REF_CLK_ROOT                  = IOMUX_PAD(0x0330, 0x00C8, 1, 0x05A4, 0, 0),
-	IMX8MN_PAD_SD1_RESET_B__I2C3_SCL                                        = IOMUX_PAD(0x0330, 0x00C8, 3, 0x0588, 1, 0),
+	IMX8MN_PAD_SD1_RESET_B__I2C3_SCL                                        = IOMUX_PAD(0x0330, 0x00C8, 3 | IOMUX_CONFIG_SION, 0x0588, 1, 0),
 	IMX8MN_PAD_SD1_RESET_B__UART3_DCE_RTS_B                                 = IOMUX_PAD(0x0330, 0x00C8, 4, 0x0500, 2, 0),
 	IMX8MN_PAD_SD1_RESET_B__UART3_DTE_CTS_B                                 = IOMUX_PAD(0x0330, 0x00C8, 4, 0x0000, 0, 0),
 	IMX8MN_PAD_SD1_RESET_B__GPIO2_IO10                                      = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0),
 
 	IMX8MN_PAD_SD1_STROBE__USDHC1_STROBE                                    = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0),
-	IMX8MN_PAD_SD1_STROBE__I2C3_SDA                                         = IOMUX_PAD(0x0334, 0x00CC, 3, 0x05BC, 1, 0),
+	IMX8MN_PAD_SD1_STROBE__I2C3_SDA                                         = IOMUX_PAD(0x0334, 0x00CC, 3 | IOMUX_CONFIG_SION, 0x05BC, 1, 0),
 	IMX8MN_PAD_SD1_STROBE__UART3_DCE_CTS_B                                  = IOMUX_PAD(0x0334, 0x00CC, 4, 0x0000, 0, 0),
 	IMX8MN_PAD_SD1_STROBE__UART3_DTE_RTS_B                                  = IOMUX_PAD(0x0334, 0x00CC, 4, 0x0500, 3, 0),
 	IMX8MN_PAD_SD1_STROBE__GPIO2_IO11                                       = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0),
@@ -288,7 +288,7 @@ enum {
 
 	IMX8MN_PAD_SD2_DATA0__USDHC2_DATA0                                      = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0),
 	IMX8MN_PAD_SD2_DATA0__SAI5_RX_DATA0                                     = IOMUX_PAD(0x0344, 0x00DC, 1, 0x04D4, 1, 0),
-	IMX8MN_PAD_SD2_DATA0__I2C4_SDA                                          = IOMUX_PAD(0x0344, 0x00DC, 2, 0x058C, 1, 0),
+	IMX8MN_PAD_SD2_DATA0__I2C4_SDA                                          = IOMUX_PAD(0x0344, 0x00DC, 2 | IOMUX_CONFIG_SION, 0x058C, 1, 0),
 	IMX8MN_PAD_SD2_DATA0__UART2_DCE_RX                                      = IOMUX_PAD(0x0344, 0x00DC, 3, 0x04FC, 6, 0),
 	IMX8MN_PAD_SD2_DATA0__UART2_DTE_TX                                      = IOMUX_PAD(0x0344, 0x00DC, 3, 0x0000, 0, 0),
 	IMX8MN_PAD_SD2_DATA0__PDM_BIT_STREAM0                                   = IOMUX_PAD(0x0344, 0x00DC, 4, 0x0534, 2, 0),
@@ -297,7 +297,7 @@ enum {
 
 	IMX8MN_PAD_SD2_DATA1__USDHC2_DATA1                                      = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0),
 	IMX8MN_PAD_SD2_DATA1__SAI5_TX_SYNC                                      = IOMUX_PAD(0x0348, 0x00E0, 1, 0x04EC, 1, 0),
-	IMX8MN_PAD_SD2_DATA1__I2C4_SCL                                          = IOMUX_PAD(0x0348, 0x00E0, 2, 0x05D4, 1, 0),
+	IMX8MN_PAD_SD2_DATA1__I2C4_SCL                                          = IOMUX_PAD(0x0348, 0x00E0, 2 | IOMUX_CONFIG_SION, 0x05D4, 1, 0),
 	IMX8MN_PAD_SD2_DATA1__UART2_DCE_TX                                      = IOMUX_PAD(0x0348, 0x00E0, 3, 0x0000, 0, 0),
 	IMX8MN_PAD_SD2_DATA1__UART2_DTE_RX                                      = IOMUX_PAD(0x0348, 0x00E0, 3, 0x04FC, 7, 0),
 	IMX8MN_PAD_SD2_DATA1__PDM_BIT_STREAM1                                   = IOMUX_PAD(0x0348, 0x00E0, 4, 0x0538, 4, 0),
@@ -348,7 +348,7 @@ enum {
 	IMX8MN_PAD_NAND_CE1_B__QSPI_A_SS1_B                                     = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0),
 	IMX8MN_PAD_NAND_CE1_B__USDHC3_STROBE                                    = IOMUX_PAD(0x0364, 0x00FC, 2, 0x059C, 0, 0),
 	IMX8MN_PAD_NAND_CE1_B__PDM_BIT_STREAM0                                  = IOMUX_PAD(0x0364, 0x00FC, 3, 0x0534, 4, 0),
-	IMX8MN_PAD_NAND_CE1_B__I2C4_SCL                                         = IOMUX_PAD(0x0364, 0x00FC, 4, 0x05D4, 2, 0),
+	IMX8MN_PAD_NAND_CE1_B__I2C4_SCL                                         = IOMUX_PAD(0x0364, 0x00FC, 4 | IOMUX_CONFIG_SION, 0x05D4, 2, 0),
 	IMX8MN_PAD_NAND_CE1_B__GPIO3_IO2                                        = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0),
 	IMX8MN_PAD_NAND_CE1_B__CORESIGHT_TRACE0                                 = IOMUX_PAD(0x0364, 0x00FC, 6, 0x0000, 0, 0),
 
@@ -356,7 +356,7 @@ enum {
 	IMX8MN_PAD_NAND_CE2_B__QSPI_B_SS0_B                                     = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0),
 	IMX8MN_PAD_NAND_CE2_B__USDHC3_DATA5                                     = IOMUX_PAD(0x0368, 0x0100, 2, 0x0550, 0, 0),
 	IMX8MN_PAD_NAND_CE2_B__PDM_BIT_STREAM1                                  = IOMUX_PAD(0x0368, 0x0100, 3, 0x0538, 6, 0),
-	IMX8MN_PAD_NAND_CE2_B__I2C4_SDA                                         = IOMUX_PAD(0x0368, 0x0100, 4, 0x058C, 2, 0),
+	IMX8MN_PAD_NAND_CE2_B__I2C4_SDA                                         = IOMUX_PAD(0x0368, 0x0100, 4 | IOMUX_CONFIG_SION, 0x058C, 2, 0),
 	IMX8MN_PAD_NAND_CE2_B__GPIO3_IO3                                        = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0),
 	IMX8MN_PAD_NAND_CE2_B__CORESIGHT_TRACE1                                 = IOMUX_PAD(0x0368, 0x0100, 6, 0x0000, 0, 0),
 
@@ -364,7 +364,7 @@ enum {
 	IMX8MN_PAD_NAND_CE3_B__QSPI_B_SS1_B                                     = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0),
 	IMX8MN_PAD_NAND_CE3_B__USDHC3_DATA6                                     = IOMUX_PAD(0x036C, 0x0104, 2, 0x0584, 0, 0),
 	IMX8MN_PAD_NAND_CE3_B__PDM_BIT_STREAM2                                  = IOMUX_PAD(0x036C, 0x0104, 3, 0x053C, 5, 0),
-	IMX8MN_PAD_NAND_CE3_B__I2C3_SDA                                         = IOMUX_PAD(0x036C, 0x0104, 4, 0x05BC, 2, 0),
+	IMX8MN_PAD_NAND_CE3_B__I2C3_SDA                                         = IOMUX_PAD(0x036C, 0x0104, 4 | IOMUX_CONFIG_SION, 0x05BC, 2, 0),
 	IMX8MN_PAD_NAND_CE3_B__GPIO3_IO4                                        = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0),
 	IMX8MN_PAD_NAND_CE3_B__CORESIGHT_TRACE2                                 = IOMUX_PAD(0x036C, 0x0104, 6, 0x0000, 0, 0),
 
@@ -393,7 +393,7 @@ enum {
 	IMX8MN_PAD_NAND_DATA02__RAWNAND_DATA02                                  = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0),
 	IMX8MN_PAD_NAND_DATA02__QSPI_A_DATA2                                    = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0),
 	IMX8MN_PAD_NAND_DATA02__USDHC3_CD_B                                     = IOMUX_PAD(0x037C, 0x0114, 2, 0x0598, 0, 0),
-	IMX8MN_PAD_NAND_DATA02__I2C4_SDA                                        = IOMUX_PAD(0x037C, 0x0114, 4, 0x058C, 3, 0),
+	IMX8MN_PAD_NAND_DATA02__I2C4_SDA                                        = IOMUX_PAD(0x037C, 0x0114, 4 | IOMUX_CONFIG_SION, 0x058C, 3, 0),
 	IMX8MN_PAD_NAND_DATA02__GPIO3_IO8                                       = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0),
 	IMX8MN_PAD_NAND_DATA02__CORESIGHT_TRACE6                                = IOMUX_PAD(0x037C, 0x0114, 6, 0x0000, 0, 0),
 
@@ -430,7 +430,7 @@ enum {
 	IMX8MN_PAD_NAND_DQS__RAWNAND_DQS                                        = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0),
 	IMX8MN_PAD_NAND_DQS__QSPI_A_DQS                                         = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0),
 	IMX8MN_PAD_NAND_DQS__PDM_CLK                                            = IOMUX_PAD(0x0394, 0x012C, 3, 0x0000, 0, 0),
-	IMX8MN_PAD_NAND_DQS__I2C3_SCL                                           = IOMUX_PAD(0x0394, 0x012C, 4, 0x0588, 2, 0),
+	IMX8MN_PAD_NAND_DQS__I2C3_SCL                                           = IOMUX_PAD(0x0394, 0x012C, 4 | IOMUX_CONFIG_SION, 0x0588, 2, 0),
 	IMX8MN_PAD_NAND_DQS__GPIO3_IO14                                         = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0),
 	IMX8MN_PAD_NAND_DQS__CORESIGHT_TRACE12                                  = IOMUX_PAD(0x0394, 0x012C, 6, 0x0000, 0, 0),
 
@@ -444,19 +444,19 @@ enum {
 	IMX8MN_PAD_NAND_READY_B__RAWNAND_READY_B                                = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0),
 	IMX8MN_PAD_NAND_READY_B__USDHC3_RESET_B                                 = IOMUX_PAD(0x039C, 0x0134, 2, 0x0000, 0, 0),
 	IMX8MN_PAD_NAND_READY_B__PDM_BIT_STREAM3                                = IOMUX_PAD(0x039C, 0x0134, 3, 0x0540, 6, 0),
-	IMX8MN_PAD_NAND_READY_B__I2C3_SCL                                       = IOMUX_PAD(0x039C, 0x0134, 4, 0x0588, 3, 0),
+	IMX8MN_PAD_NAND_READY_B__I2C3_SCL                                       = IOMUX_PAD(0x039C, 0x0134, 4 | IOMUX_CONFIG_SION, 0x0588, 3, 0),
 	IMX8MN_PAD_NAND_READY_B__GPIO3_IO16                                     = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0),
 	IMX8MN_PAD_NAND_READY_B__CORESIGHT_TRACE14                              = IOMUX_PAD(0x039C, 0x0134, 6, 0x0000, 0, 0),
 
 	IMX8MN_PAD_NAND_WE_B__RAWNAND_WE_B                                      = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0),
-	IMX8MN_PAD_NAND_WE_B__USDHC3_CLK                                        = IOMUX_PAD(0x03A0, 0x0138, 2  | IOMUX_CONFIG_SION, 0x05A0, 0, 0),
-	IMX8MN_PAD_NAND_WE_B__I2C3_SDA                                          = IOMUX_PAD(0x03A0, 0x0138, 4, 0x05BC, 3, 0),
+	IMX8MN_PAD_NAND_WE_B__USDHC3_CLK                                        = IOMUX_PAD(0x03A0, 0x0138, 2 | IOMUX_CONFIG_SION, 0x05A0, 0, 0),
+	IMX8MN_PAD_NAND_WE_B__I2C3_SDA                                          = IOMUX_PAD(0x03A0, 0x0138, 4 | IOMUX_CONFIG_SION, 0x05BC, 3, 0),
 	IMX8MN_PAD_NAND_WE_B__GPIO3_IO17                                        = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0),
 	IMX8MN_PAD_NAND_WE_B__CORESIGHT_TRACE15                                 = IOMUX_PAD(0x03A0, 0x0138, 6, 0x0000, 0, 0),
 
 	IMX8MN_PAD_NAND_WP_B__RAWNAND_WP_B                                      = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0),
 	IMX8MN_PAD_NAND_WP_B__USDHC3_CMD                                        = IOMUX_PAD(0x03A4, 0x013C, 2, 0x05DC, 0, 0),
-	IMX8MN_PAD_NAND_WP_B__I2C4_SDA                                          = IOMUX_PAD(0x03A4, 0x013C, 4, 0x058C, 4, 0),
+	IMX8MN_PAD_NAND_WP_B__I2C4_SDA                                          = IOMUX_PAD(0x03A4, 0x013C, 4 | IOMUX_CONFIG_SION, 0x058C, 4, 0),
 	IMX8MN_PAD_NAND_WP_B__GPIO3_IO18                                        = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0),
 	IMX8MN_PAD_NAND_WP_B__CORESIGHT_EVENTO                                  = IOMUX_PAD(0x03A4, 0x013C, 6, 0x0000, 0, 0),
 
@@ -609,28 +609,28 @@ enum {
 	IMX8MN_PAD_ECSPI1_SCLK__ECSPI1_SCLK                                     = IOMUX_PAD(0x045C, 0x01F4, 0, 0x05D8, 0, 0),
 	IMX8MN_PAD_ECSPI1_SCLK__UART3_DCE_RX                                    = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0),
 	IMX8MN_PAD_ECSPI1_SCLK__UART3_DTE_TX                                    = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0000, 0, 0),
-	IMX8MN_PAD_ECSPI1_SCLK__I2C1_SCL                                        = IOMUX_PAD(0x045C, 0x01F4, 2, 0x055C, 2, 0),
+	IMX8MN_PAD_ECSPI1_SCLK__I2C1_SCL                                        = IOMUX_PAD(0x045C, 0x01F4, 2 | IOMUX_CONFIG_SION, 0x055C, 2, 0),
 	IMX8MN_PAD_ECSPI1_SCLK__SAI5_RX_SYNC                                    = IOMUX_PAD(0x045C, 0x01F4, 3, 0x04DC, 2, 0),
 	IMX8MN_PAD_ECSPI1_SCLK__GPIO5_IO6                                       = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0),
 
 	IMX8MN_PAD_ECSPI1_MOSI__ECSPI1_MOSI                                     = IOMUX_PAD(0x0460, 0x01F8, 0, 0x05A8, 0, 0),
 	IMX8MN_PAD_ECSPI1_MOSI__UART3_DCE_TX                                    = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0000, 0, 0),
 	IMX8MN_PAD_ECSPI1_MOSI__UART3_DTE_RX                                    = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0),
-	IMX8MN_PAD_ECSPI1_MOSI__I2C1_SDA                                        = IOMUX_PAD(0x0460, 0x01F8, 2, 0x056C, 2, 0),
+	IMX8MN_PAD_ECSPI1_MOSI__I2C1_SDA                                        = IOMUX_PAD(0x0460, 0x01F8, 2 | IOMUX_CONFIG_SION, 0x056C, 2, 0),
 	IMX8MN_PAD_ECSPI1_MOSI__SAI5_RX_BCLK                                    = IOMUX_PAD(0x0460, 0x01F8, 3, 0x04D0, 3, 0),
 	IMX8MN_PAD_ECSPI1_MOSI__GPIO5_IO7                                       = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0),
 
 	IMX8MN_PAD_ECSPI1_MISO__ECSPI1_MISO                                     = IOMUX_PAD(0x0464, 0x01FC, 0, 0x05C4, 0, 0),
 	IMX8MN_PAD_ECSPI1_MISO__UART3_DCE_CTS_B                                 = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0000, 0, 0),
 	IMX8MN_PAD_ECSPI1_MISO__UART3_DTE_RTS_B                                 = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0),
-	IMX8MN_PAD_ECSPI1_MISO__I2C2_SCL                                        = IOMUX_PAD(0x0464, 0x01FC, 2, 0x05D0, 2, 0),
+	IMX8MN_PAD_ECSPI1_MISO__I2C2_SCL                                        = IOMUX_PAD(0x0464, 0x01FC, 2 | IOMUX_CONFIG_SION, 0x05D0, 2, 0),
 	IMX8MN_PAD_ECSPI1_MISO__SAI5_RX_DATA0                                   = IOMUX_PAD(0x0464, 0x01FC, 3, 0x04D4, 3, 0),
 	IMX8MN_PAD_ECSPI1_MISO__GPIO5_IO8                                       = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0),
 
 	IMX8MN_PAD_ECSPI1_SS0__ECSPI1_SS0                                       = IOMUX_PAD(0x0468, 0x0200, 0, 0x0564, 0, 0),
 	IMX8MN_PAD_ECSPI1_SS0__UART3_DCE_RTS_B                                  = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0),
 	IMX8MN_PAD_ECSPI1_SS0__UART3_DTE_CTS_B                                  = IOMUX_PAD(0x0468, 0x0200, 1, 0x0000, 0, 0),
-	IMX8MN_PAD_ECSPI1_SS0__I2C2_SDA                                         = IOMUX_PAD(0x0468, 0x0200, 2, 0x0560, 2, 0),
+	IMX8MN_PAD_ECSPI1_SS0__I2C2_SDA                                         = IOMUX_PAD(0x0468, 0x0200, 2 | IOMUX_CONFIG_SION, 0x0560, 2, 0),
 	IMX8MN_PAD_ECSPI1_SS0__SAI5_RX_DATA1                                    = IOMUX_PAD(0x0468, 0x0200, 3, 0x04D8, 2, 0),
 	IMX8MN_PAD_ECSPI1_SS0__SAI5_TX_SYNC                                     = IOMUX_PAD(0x0468, 0x0200, 4, 0x04EC, 3, 0),
 	IMX8MN_PAD_ECSPI1_SS0__GPIO5_IO9                                        = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0),
@@ -638,7 +638,7 @@ enum {
 	IMX8MN_PAD_ECSPI2_SCLK__ECSPI2_SCLK                                     = IOMUX_PAD(0x046C, 0x0204, 0, 0x0580, 0, 0),
 	IMX8MN_PAD_ECSPI2_SCLK__UART4_DCE_RX                                    = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0),
 	IMX8MN_PAD_ECSPI2_SCLK__UART4_DTE_TX                                    = IOMUX_PAD(0x046C, 0x0204, 1, 0x0000, 0, 0),
-	IMX8MN_PAD_ECSPI2_SCLK__I2C3_SCL                                        = IOMUX_PAD(0x046C, 0x0204, 2, 0x0588, 4, 0),
+	IMX8MN_PAD_ECSPI2_SCLK__I2C3_SCL                                        = IOMUX_PAD(0x046C, 0x0204, 2 | IOMUX_CONFIG_SION, 0x0588, 4, 0),
 	IMX8MN_PAD_ECSPI2_SCLK__SAI5_RX_DATA2                                   = IOMUX_PAD(0x046C, 0x0204, 3, 0x0000, 0, 0),
 	IMX8MN_PAD_ECSPI2_SCLK__SAI5_TX_BCLK                                    = IOMUX_PAD(0x046C, 0x0204, 4, 0x04E8, 3, 0),
 	IMX8MN_PAD_ECSPI2_SCLK__GPIO5_IO10                                      = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0),
@@ -646,7 +646,7 @@ enum {
 	IMX8MN_PAD_ECSPI2_MOSI__ECSPI2_MOSI                                     = IOMUX_PAD(0x0470, 0x0208, 0, 0x0590, 0, 0),
 	IMX8MN_PAD_ECSPI2_MOSI__UART4_DCE_TX                                    = IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0),
 	IMX8MN_PAD_ECSPI2_MOSI__UART4_DTE_RX                                    = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0),
-	IMX8MN_PAD_ECSPI2_MOSI__I2C3_SDA                                        = IOMUX_PAD(0x0470, 0x0208, 2, 0x05BC, 4, 0),
+	IMX8MN_PAD_ECSPI2_MOSI__I2C3_SDA                                        = IOMUX_PAD(0x0470, 0x0208, 2 | IOMUX_CONFIG_SION, 0x05BC, 4, 0),
 	IMX8MN_PAD_ECSPI2_MOSI__SAI5_RX_DATA3                                   = IOMUX_PAD(0x0470, 0x0208, 3, 0x04E0, 2, 0),
 	IMX8MN_PAD_ECSPI2_MOSI__SAI5_TX_DATA0                                   = IOMUX_PAD(0x0470, 0x0208, 4, 0x0000, 0, 0),
 	IMX8MN_PAD_ECSPI2_MOSI__GPIO5_IO11                                      = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0),
@@ -654,14 +654,14 @@ enum {
 	IMX8MN_PAD_ECSPI2_MISO__ECSPI2_MISO                                     = IOMUX_PAD(0x0474, 0x020C, 0, 0x0578, 0, 0),
 	IMX8MN_PAD_ECSPI2_MISO__UART4_DCE_CTS_B                                 = IOMUX_PAD(0x0474, 0x020C, 1, 0x0000, 0, 0),
 	IMX8MN_PAD_ECSPI2_MISO__UART4_DTE_RTS_B                                 = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0),
-	IMX8MN_PAD_ECSPI2_MISO__I2C4_SCL                                        = IOMUX_PAD(0x0474, 0x020C, 2, 0x05D4, 3, 0),
+	IMX8MN_PAD_ECSPI2_MISO__I2C4_SCL                                        = IOMUX_PAD(0x0474, 0x020C, 2 | IOMUX_CONFIG_SION, 0x05D4, 3, 0),
 	IMX8MN_PAD_ECSPI2_MISO__SAI5_MCLK                                       = IOMUX_PAD(0x0474, 0x020C, 3, 0x0594, 4, 0),
 	IMX8MN_PAD_ECSPI2_MISO__GPIO5_IO12                                      = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0),
 
 	IMX8MN_PAD_ECSPI2_SS0__ECSPI2_SS0                                       = IOMUX_PAD(0x0478, 0x0210, 0, 0x0570, 0, 0),
 	IMX8MN_PAD_ECSPI2_SS0__UART4_DCE_RTS_B                                  = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0),
 	IMX8MN_PAD_ECSPI2_SS0__UART4_DTE_CTS_B                                  = IOMUX_PAD(0x0478, 0x0210, 1, 0x0000, 0, 0),
-	IMX8MN_PAD_ECSPI2_SS0__I2C4_SDA                                         = IOMUX_PAD(0x0478, 0x0210, 2, 0x058C, 5, 0),
+	IMX8MN_PAD_ECSPI2_SS0__I2C4_SDA                                         = IOMUX_PAD(0x0478, 0x0210, 2 | IOMUX_CONFIG_SION, 0x058C, 5, 0),
 	IMX8MN_PAD_ECSPI2_SS0__GPIO5_IO13                                       = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0),
 
 	IMX8MN_PAD_I2C1_SCL__I2C1_SCL                                           = IOMUX_PAD(0x047C, 0x0214, 0 | IOMUX_CONFIG_SION, 0x055C, 0, 0),
@@ -674,36 +674,36 @@ enum {
 	IMX8MN_PAD_I2C1_SDA__ECSPI1_MOSI                                        = IOMUX_PAD(0x0480, 0x0218, 3, 0x05A8, 1, 0),
 	IMX8MN_PAD_I2C1_SDA__GPIO5_IO15                                         = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0),
 
-	IMX8MN_PAD_I2C2_SCL__I2C2_SCL                                           = IOMUX_PAD(0x0484, 0x021C, 0, 0x05D0, 0, 0),
+	IMX8MN_PAD_I2C2_SCL__I2C2_SCL                                           = IOMUX_PAD(0x0484, 0x021C, 0 | IOMUX_CONFIG_SION, 0x05D0, 0, 0),
 	IMX8MN_PAD_I2C2_SCL__ENET1_1588_EVENT1_IN                               = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0),
 	IMX8MN_PAD_I2C2_SCL__USDHC3_CD_B                                        = IOMUX_PAD(0x0484, 0x021C, 2, 0x0598, 1, 0),
 	IMX8MN_PAD_I2C2_SCL__ECSPI1_MISO                                        = IOMUX_PAD(0x0484, 0x021C, 3, 0x05C4, 1, 0),
 	IMX8MN_PAD_I2C2_SCL__GPIO5_IO16                                         = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0),
 
-	IMX8MN_PAD_I2C2_SDA__I2C2_SDA                                           = IOMUX_PAD(0x0488, 0x0220, 0, 0x0560, 0, 0),
+	IMX8MN_PAD_I2C2_SDA__I2C2_SDA                                           = IOMUX_PAD(0x0488, 0x0220, 0 | IOMUX_CONFIG_SION, 0x0560, 0, 0),
 	IMX8MN_PAD_I2C2_SDA__ENET1_1588_EVENT1_OUT                              = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0),
 	IMX8MN_PAD_I2C2_SDA__USDHC3_WP                                          = IOMUX_PAD(0x0488, 0x0220, 2, 0x05B8, 1, 0),
 	IMX8MN_PAD_I2C2_SDA__ECSPI1_SS0                                         = IOMUX_PAD(0x0488, 0x0220, 3, 0x0564, 1, 0),
 	IMX8MN_PAD_I2C2_SDA__GPIO5_IO17                                         = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0),
 
-	IMX8MN_PAD_I2C3_SCL__I2C3_SCL                                           = IOMUX_PAD(0x048C, 0x0224, 0, 0x0588, 0, 0),
+	IMX8MN_PAD_I2C3_SCL__I2C3_SCL                                           = IOMUX_PAD(0x048C, 0x0224, 0 | IOMUX_CONFIG_SION, 0x0588, 0, 0),
 	IMX8MN_PAD_I2C3_SCL__PWM4_OUT                                           = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0),
 	IMX8MN_PAD_I2C3_SCL__GPT2_CLK                                           = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0),
 	IMX8MN_PAD_I2C3_SCL__ECSPI2_SCLK                                        = IOMUX_PAD(0x048C, 0x0224, 3, 0x0580, 2, 0),
 	IMX8MN_PAD_I2C3_SCL__GPIO5_IO18                                         = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0),
 
-	IMX8MN_PAD_I2C3_SDA__I2C3_SDA                                           = IOMUX_PAD(0x0490, 0x0228, 0, 0x05BC, 0, 0),
+	IMX8MN_PAD_I2C3_SDA__I2C3_SDA                                           = IOMUX_PAD(0x0490, 0x0228, 0 | IOMUX_CONFIG_SION, 0x05BC, 0, 0),
 	IMX8MN_PAD_I2C3_SDA__PWM3_OUT                                           = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0),
 	IMX8MN_PAD_I2C3_SDA__GPT3_CLK                                           = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0),
 	IMX8MN_PAD_I2C3_SDA__ECSPI2_MOSI                                        = IOMUX_PAD(0x0490, 0x0228, 3, 0x0590, 2, 0),
 	IMX8MN_PAD_I2C3_SDA__GPIO5_IO19                                         = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0),
 
-	IMX8MN_PAD_I2C4_SCL__I2C4_SCL                                           = IOMUX_PAD(0x0494, 0x022C, 0, 0x05D4, 0, 0),
+	IMX8MN_PAD_I2C4_SCL__I2C4_SCL                                           = IOMUX_PAD(0x0494, 0x022C, 0 | IOMUX_CONFIG_SION, 0x05D4, 0, 0),
 	IMX8MN_PAD_I2C4_SCL__PWM2_OUT                                           = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0),
 	IMX8MN_PAD_I2C4_SCL__ECSPI2_MISO                                        = IOMUX_PAD(0x0494, 0x022C, 3, 0x0578, 2, 0),
 	IMX8MN_PAD_I2C4_SCL__GPIO5_IO20                                         = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0),
 
-	IMX8MN_PAD_I2C4_SDA__I2C4_SDA                                           = IOMUX_PAD(0x0498, 0x0230, 0, 0x058C, 0, 0),
+	IMX8MN_PAD_I2C4_SDA__I2C4_SDA                                           = IOMUX_PAD(0x0498, 0x0230, 0 | IOMUX_CONFIG_SION, 0x058C, 0, 0),
 	IMX8MN_PAD_I2C4_SDA__PWM1_OUT                                           = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0),
 	IMX8MN_PAD_I2C4_SDA__ECSPI2_SS0                                         = IOMUX_PAD(0x0498, 0x0230, 3, 0x0570, 1, 0),
 	IMX8MN_PAD_I2C4_SDA__GPIO5_IO21                                         = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-imx8m/imx8mp_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mp_pins.h
index e7f32218233..309453e1a97 100644
--- a/arch/arm/include/asm/arch-imx8m/imx8mp_pins.h
+++ b/arch/arm/include/asm/arch-imx8m/imx8mp_pins.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  */
 
 #ifndef __ASM_ARCH_IMX8MP_PINS_H__
@@ -10,210 +10,176 @@
 
 enum {
 	MX8MP_PAD_GPIO1_IO00__GPIO1_IO00                         = IOMUX_PAD(0x0274, 0x0014, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0274, 0x0014, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO00__MEDIAMIX_ISP_FL_TRIG_0             = IOMUX_PAD(0x0274, 0x0014, 3, 0x05D4, 0, 0),
-	MX8MP_PAD_GPIO1_IO00__ANAMIX_REF_CLK_32K                 = IOMUX_PAD(0x0274, 0x0014, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO00__CCMSRCGPCMIX_EXT_CLK1              = IOMUX_PAD(0x0274, 0x0014, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO00__SJC_FAIL                           = IOMUX_PAD(0x0274, 0x0014, 7, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT          = IOMUX_PAD(0x0274, 0x0014, 1, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO00__ISP_FL_TRIG_0                      = IOMUX_PAD(0x0274, 0x0014, 3, 0x05D4, 0, 0),
+	MX8MP_PAD_GPIO1_IO00__CCM_EXT_CLK1                       = IOMUX_PAD(0x0274, 0x0014, 6, 0x0000, 0, 0),
 
 	MX8MP_PAD_GPIO1_IO01__GPIO1_IO01                         = IOMUX_PAD(0x0278, 0x0018, 0, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO01__PWM1_OUT                           = IOMUX_PAD(0x0278, 0x0018, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO01__MEDIAMIX_ISP_SHUTTER_TRIG_0        = IOMUX_PAD(0x0278, 0x0018, 3, 0x05DC, 0, 0),
-	MX8MP_PAD_GPIO1_IO01__ANAMIX_REF_CLK_24M                 = IOMUX_PAD(0x0278, 0x0018, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO01__CCMSRCGPCMIX_EXT_CLK2              = IOMUX_PAD(0x0278, 0x0018, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO01__SJC_ACTIVE                         = IOMUX_PAD(0x0278, 0x0018, 7, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO01__ISP_SHUTTER_TRIG_0                 = IOMUX_PAD(0x0278, 0x0018, 3, 0x05DC, 0, 0),
+	MX8MP_PAD_GPIO1_IO01__CCM_EXT_CLK2                       = IOMUX_PAD(0x0278, 0x0018, 6, 0x0000, 0, 0),
 
 	MX8MP_PAD_GPIO1_IO02__GPIO1_IO02                         = IOMUX_PAD(0x027C, 0x001C, 0, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B                       = IOMUX_PAD(0x027C, 0x001C, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO02__MEDIAMIX_ISP_FLASH_TRIG_0          = IOMUX_PAD(0x027C, 0x001C, 3, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO02__ISP_FLASH_TRIG_0                   = IOMUX_PAD(0x027C, 0x001C, 3, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_ANY                     = IOMUX_PAD(0x027C, 0x001C, 5, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO02__SJC_DE_B                           = IOMUX_PAD(0x027C, 0x001C, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_GPIO1_IO03__GPIO1_IO03                         = IOMUX_PAD(0x0280, 0x0020, 0, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO03__USDHC1_VSELECT                     = IOMUX_PAD(0x0280, 0x0020, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO03__MEDIAMIX_ISP_PRELIGHT_TRIG_0       = IOMUX_PAD(0x0280, 0x0020, 3, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO03__ISP_PRELIGHT_TRIG_0                = IOMUX_PAD(0x0280, 0x0020, 3, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO03__SDMA1_EXT_EVENT00                  = IOMUX_PAD(0x0280, 0x0020, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO03__ANAMIX_XTAL_OK                     = IOMUX_PAD(0x0280, 0x0020, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO03__SJC_DONE                           = IOMUX_PAD(0x0280, 0x0020, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_GPIO1_IO04__GPIO1_IO04                         = IOMUX_PAD(0x0284, 0x0024, 0, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO04__USDHC2_VSELECT                     = IOMUX_PAD(0x0284, 0x0024, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO04__MEDIAMIX_ISP_SHUTTER_OPEN_0        = IOMUX_PAD(0x0284, 0x0024, 3, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO04__ISP_SHUTTER_OPEN_0                 = IOMUX_PAD(0x0284, 0x0024, 3, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO04__SDMA1_EXT_EVENT01                  = IOMUX_PAD(0x0284, 0x0024, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO04__ANAMIX_XTAL_OK_LV                  = IOMUX_PAD(0x0284, 0x0024, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO04__USDHC1_TEST_TRIG                   = IOMUX_PAD(0x0284, 0x0024, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_GPIO1_IO05__GPIO1_IO05                         = IOMUX_PAD(0x0288, 0x0028, 0, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO05__M7_NMI                             = IOMUX_PAD(0x0288, 0x0028, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO05__MEDIAMIX_ISP_FL_TRIG_1             = IOMUX_PAD(0x0288, 0x0028, 3, 0x05D8, 0, 0),
-	MX8MP_PAD_GPIO1_IO05__CCMSRCGPCMIX_PMIC_READY            = IOMUX_PAD(0x0288, 0x0028, 5, 0x0554, 0, 0),
-	MX8MP_PAD_GPIO1_IO05__CCMSRCGPCMIX_INT_BOOT              = IOMUX_PAD(0x0288, 0x0028, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO05__USDHC2_TEST_TRIG                   = IOMUX_PAD(0x0288, 0x0028, 7, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO05__ISP_FL_TRIG_1                      = IOMUX_PAD(0x0288, 0x0028, 3, 0x05D8, 0, 0),
+	MX8MP_PAD_GPIO1_IO05__CCM_PMIC_READY                     = IOMUX_PAD(0x0288, 0x0028, 5, 0x0554, 0, 0),
 
 	MX8MP_PAD_GPIO1_IO06__GPIO1_IO06                         = IOMUX_PAD(0x028C, 0x002C, 0, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO06__ENET_QOS_MDC                       = IOMUX_PAD(0x028C, 0x002C, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO06__MEDIAMIX_ISP_SHUTTER_TRIG_1        = IOMUX_PAD(0x028C, 0x002C, 3, 0x05E0, 0, 0),
+	MX8MP_PAD_GPIO1_IO06__ISP_SHUTTER_TRIG_1                 = IOMUX_PAD(0x028C, 0x002C, 3, 0x05E0, 0, 0),
 	MX8MP_PAD_GPIO1_IO06__USDHC1_CD_B                        = IOMUX_PAD(0x028C, 0x002C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO06__CCMSRCGPCMIX_EXT_CLK3              = IOMUX_PAD(0x028C, 0x002C, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO06__ECSPI1_TEST_TRIG                   = IOMUX_PAD(0x028C, 0x002C, 7, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO06__CCM_EXT_CLK3                       = IOMUX_PAD(0x028C, 0x002C, 6, 0x0000, 0, 0),
 
 	MX8MP_PAD_GPIO1_IO07__GPIO1_IO07                         = IOMUX_PAD(0x0290, 0x0030, 0, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO07__ENET_QOS_MDIO                      = IOMUX_PAD(0x0290, 0x0030, 1, 0x0590, 0, 0),
-	MX8MP_PAD_GPIO1_IO07__MEDIAMIX_ISP_FLASH_TRIG_1          = IOMUX_PAD(0x0290, 0x0030, 3, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO07__ISP_FLASH_TRIG_1                   = IOMUX_PAD(0x0290, 0x0030, 3, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO07__USDHC1_WP                          = IOMUX_PAD(0x0290, 0x0030, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO07__CCMSRCGPCMIX_EXT_CLK4              = IOMUX_PAD(0x0290, 0x0030, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO07__ECSPI2_TEST_TRIG                   = IOMUX_PAD(0x0290, 0x0030, 7, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO07__CCM_EXT_CLK4                       = IOMUX_PAD(0x0290, 0x0030, 6, 0x0000, 0, 0),
 
 	MX8MP_PAD_GPIO1_IO08__GPIO1_IO08                         = IOMUX_PAD(0x0294, 0x0034, 0, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN            = IOMUX_PAD(0x0294, 0x0034, 1, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO08__PWM1_OUT                           = IOMUX_PAD(0x0294, 0x0034, 2, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO08__MEDIAMIX_ISP_PRELIGHT_TRIG_1       = IOMUX_PAD(0x0294, 0x0034, 3, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO08__ISP_PRELIGHT_TRIG_1                = IOMUX_PAD(0x0294, 0x0034, 3, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN        = IOMUX_PAD(0x0294, 0x0034, 4, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO08__USDHC2_RESET_B                     = IOMUX_PAD(0x0294, 0x0034, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO08__CCMSRCGPCMIX_WAIT                  = IOMUX_PAD(0x0294, 0x0034, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO08__FLEXSPI_TEST_TRIG                  = IOMUX_PAD(0x0294, 0x0034, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_GPIO1_IO09__GPIO1_IO09                         = IOMUX_PAD(0x0298, 0x0038, 0, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT           = IOMUX_PAD(0x0298, 0x0038, 1, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO09__PWM2_OUT                           = IOMUX_PAD(0x0298, 0x0038, 2, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO09__MEDIAMIX_ISP_SHUTTER_OPEN_1        = IOMUX_PAD(0x0298, 0x0038, 3, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO09__ISP_SHUTTER_OPEN_1                 = IOMUX_PAD(0x0298, 0x0038, 3, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO09__USDHC3_RESET_B                     = IOMUX_PAD(0x0298, 0x0038, 4, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO09__AUDIOMIX_EXT_EVENT00               = IOMUX_PAD(0x0298, 0x0038, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO09__CCMSRCGPCMIX_STOP                  = IOMUX_PAD(0x0298, 0x0038, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO09__RAWNAND_TEST_TRIG                  = IOMUX_PAD(0x0298, 0x0038, 7, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO09__SDMA2_EXT_EVENT00                  = IOMUX_PAD(0x0298, 0x0038, 5, 0x0000, 0, 0),
 
 	MX8MP_PAD_GPIO1_IO10__GPIO1_IO10                         = IOMUX_PAD(0x029C, 0x003C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO10__HSIOMIX_usb1_OTG_ID                = IOMUX_PAD(0x029C, 0x003C, 1, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO10__USB1_OTG_ID                        = IOMUX_PAD(0x029C, 0x003C, 1, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO10__PWM3_OUT                           = IOMUX_PAD(0x029C, 0x003C, 2, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO10__OCOTP_FUSE_LATCHED                 = IOMUX_PAD(0x029C, 0x003C, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_GPIO1_IO11__GPIO1_IO11                         = IOMUX_PAD(0x02A0, 0x0040, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO11__HSIOMIX_usb2_OTG_ID                = IOMUX_PAD(0x02A0, 0x0040, 1, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO11__USB2_OTG_ID                        = IOMUX_PAD(0x02A0, 0x0040, 1, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO11__PWM2_OUT                           = IOMUX_PAD(0x02A0, 0x0040, 2, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO11__USDHC3_VSELECT                     = IOMUX_PAD(0x02A0, 0x0040, 4, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO11__CCMSRCGPCMIX_PMIC_READY            = IOMUX_PAD(0x02A0, 0x0040, 5, 0x0554, 1, 0),
-	MX8MP_PAD_GPIO1_IO11__CCMSRCGPCMIX_OUT0                  = IOMUX_PAD(0x02A0, 0x0040, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO11__CAAM_RNG_OSC_OBS                   = IOMUX_PAD(0x02A0, 0x0040, 7, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO11__CCM_PMIC_READY                     = IOMUX_PAD(0x02A0, 0x0040, 5, 0x0554, 1, 0),
 
 	MX8MP_PAD_GPIO1_IO12__GPIO1_IO12                         = IOMUX_PAD(0x02A4, 0x0044, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO12__HSIOMIX_usb1_OTG_PWR               = IOMUX_PAD(0x02A4, 0x0044, 1, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO12__AUDIOMIX_EXT_EVENT01               = IOMUX_PAD(0x02A4, 0x0044, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO12__CCMSRCGPCMIX_OUT1                  = IOMUX_PAD(0x02A4, 0x0044, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT00                = IOMUX_PAD(0x02A4, 0x0044, 7, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO12__USB1_OTG_PWR                       = IOMUX_PAD(0x02A4, 0x0044, 1, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO12__SDMA2_EXT_EVENT01                  = IOMUX_PAD(0x02A4, 0x0044, 5, 0x0000, 0, 0),
 
 	MX8MP_PAD_GPIO1_IO13__GPIO1_IO13                         = IOMUX_PAD(0x02A8, 0x0048, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO13__HSIOMIX_usb1_OTG_OC                = IOMUX_PAD(0x02A8, 0x0048, 1, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO13__USB1_OTG_OC                        = IOMUX_PAD(0x02A8, 0x0048, 1, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO13__PWM2_OUT                           = IOMUX_PAD(0x02A8, 0x0048, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO13__CCMSRCGPCMIX_OUT2                  = IOMUX_PAD(0x02A8, 0x0048, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT01                = IOMUX_PAD(0x02A8, 0x0048, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_GPIO1_IO14__GPIO1_IO14                         = IOMUX_PAD(0x02AC, 0x004C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO14__HSIOMIX_usb2_OTG_PWR               = IOMUX_PAD(0x02AC, 0x004C, 1, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO14__USB2_OTG_PWR                       = IOMUX_PAD(0x02AC, 0x004C, 1, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO14__USDHC3_CD_B                        = IOMUX_PAD(0x02AC, 0x004C, 4, 0x0608, 0, 0),
 	MX8MP_PAD_GPIO1_IO14__PWM3_OUT                           = IOMUX_PAD(0x02AC, 0x004C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO14__CCMSRCGPCMIX_CLKO1                 = IOMUX_PAD(0x02AC, 0x004C, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT02                = IOMUX_PAD(0x02AC, 0x004C, 7, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO14__CCM_CLKO1                          = IOMUX_PAD(0x02AC, 0x004C, 6, 0x0000, 0, 0),
 
 	MX8MP_PAD_GPIO1_IO15__GPIO1_IO15                         = IOMUX_PAD(0x02B0, 0x0050, 0, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO15__HSIOMIX_usb2_OTG_OC                = IOMUX_PAD(0x02B0, 0x0050, 1, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO15__USB2_OTG_OC                        = IOMUX_PAD(0x02B0, 0x0050, 1, 0x0000, 0, 0),
 	MX8MP_PAD_GPIO1_IO15__USDHC3_WP                          = IOMUX_PAD(0x02B0, 0x0050, 4, 0x0634, 0, 0),
 	MX8MP_PAD_GPIO1_IO15__PWM4_OUT                           = IOMUX_PAD(0x02B0, 0x0050, 5, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO15__CCMSRCGPCMIX_CLKO2                 = IOMUX_PAD(0x02B0, 0x0050, 6, 0x0000, 0, 0),
-	MX8MP_PAD_GPIO1_IO15__CSU_CSU_INT_DEB                    = IOMUX_PAD(0x02B0, 0x0050, 7, 0x0000, 0, 0),
+	MX8MP_PAD_GPIO1_IO15__CCM_CLKO2                          = IOMUX_PAD(0x02B0, 0x0050, 6, 0x0000, 0, 0),
 
 	MX8MP_PAD_ENET_MDC__ENET_QOS_MDC                         = IOMUX_PAD(0x02B4, 0x0054, 0, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00              = IOMUX_PAD(0x02B4, 0x0054, 2, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_MDC__GPIO1_IO16                           = IOMUX_PAD(0x02B4, 0x0054, 5, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_MDC__USDHC3_STROBE                        = IOMUX_PAD(0x02B4, 0x0054, 6, 0x0630, 0, 0),
-	MX8MP_PAD_ENET_MDC__SIM_M_HADDR15                        = IOMUX_PAD(0x02B4, 0x0054, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_ENET_MDIO__ENET_QOS_MDIO                       = IOMUX_PAD(0x02B8, 0x0058, 0, 0x0590, 1, 0),
 	MX8MP_PAD_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC               = IOMUX_PAD(0x02B8, 0x0058, 2, 0x0528, 0, 0),
+	MX8MP_PAD_ENET_MDIO__AUDIOMIX_PDM_BIT_STREAM03           = IOMUX_PAD(0x02B8, 0x0058, 3, 0x04CC, 0, 0),
 	MX8MP_PAD_ENET_MDIO__GPIO1_IO17                          = IOMUX_PAD(0x02B8, 0x0058, 5, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_MDIO__USDHC3_DATA5                        = IOMUX_PAD(0x02B8, 0x0058, 6, 0x0624, 0, 0),
-	MX8MP_PAD_ENET_MDIO__SIM_M_HADDR16                       = IOMUX_PAD(0x02B8, 0x0058, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_ENET_TD3__ENET_QOS_RGMII_TD3                   = IOMUX_PAD(0x02BC, 0x005C, 0, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK                = IOMUX_PAD(0x02BC, 0x005C, 2, 0x0524, 0, 0),
+	MX8MP_PAD_ENET_TD3__AUDIOMIX_PDM_BIT_STREAM02            = IOMUX_PAD(0x02BC, 0x005C, 3, 0x04C8, 0, 0),
 	MX8MP_PAD_ENET_TD3__GPIO1_IO18                           = IOMUX_PAD(0x02BC, 0x005C, 5, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_TD3__USDHC3_DATA6                         = IOMUX_PAD(0x02BC, 0x005C, 6, 0x0628, 0, 0),
-	MX8MP_PAD_ENET_TD3__SIM_M_HADDR17                        = IOMUX_PAD(0x02BC, 0x005C, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_ENET_TD2__ENET_QOS_RGMII_TD2                   = IOMUX_PAD(0x02C0, 0x0060, 0, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK  = IOMUX_PAD(0x02C0, 0x0060, 1, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00              = IOMUX_PAD(0x02C0, 0x0060, 2, 0x051C, 0, 0),
+	MX8MP_PAD_ENET_TD2__AUDIOMIX_PDM_BIT_STREAM01            = IOMUX_PAD(0x02C0, 0x0060, 3, 0x04C4, 0, 0),
 	MX8MP_PAD_ENET_TD2__GPIO1_IO19                           = IOMUX_PAD(0x02C0, 0x0060, 5, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_TD2__USDHC3_DATA7                         = IOMUX_PAD(0x02C0, 0x0060, 6, 0x062C, 0, 0),
-	MX8MP_PAD_ENET_TD2__SIM_M_HADDR18                        = IOMUX_PAD(0x02C0, 0x0060, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_ENET_TD1__ENET_QOS_RGMII_TD1                   = IOMUX_PAD(0x02C4, 0x0064, 0, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC                = IOMUX_PAD(0x02C4, 0x0064, 2, 0x0520, 0, 0),
+	MX8MP_PAD_ENET_TD1__AUDIOMIX_PDM_BIT_STREAM00            = IOMUX_PAD(0x02C4, 0x0064, 3, 0x04C0, 0, 0),
 	MX8MP_PAD_ENET_TD1__GPIO1_IO20                           = IOMUX_PAD(0x02C4, 0x0064, 5, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_TD1__USDHC3_CD_B                          = IOMUX_PAD(0x02C4, 0x0064, 6, 0x0608, 1, 0),
-	MX8MP_PAD_ENET_TD1__SIM_M_HADDR19                        = IOMUX_PAD(0x02C4, 0x0064, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_ENET_TD0__ENET_QOS_RGMII_TD0                   = IOMUX_PAD(0x02C8, 0x0068, 0, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK                = IOMUX_PAD(0x02C8, 0x0068, 2, 0x0518, 0, 0),
+	MX8MP_PAD_ENET_TD0__AUDIOMIX_PDM_CLK                     = IOMUX_PAD(0x02C8, 0x0068, 3, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_TD0__GPIO1_IO21                           = IOMUX_PAD(0x02C8, 0x0068, 5, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_TD0__USDHC3_WP                            = IOMUX_PAD(0x02C8, 0x0068, 6, 0x0634, 1, 0),
-	MX8MP_PAD_ENET_TD0__SIM_M_HADDR20                        = IOMUX_PAD(0x02C8, 0x0068, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL             = IOMUX_PAD(0x02CC, 0x006C, 0, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK                = IOMUX_PAD(0x02CC, 0x006C, 2, 0x0514, 0, 0),
-	MX8MP_PAD_ENET_TX_CTL__AUDIOMIX_SPDIF_OUT                = IOMUX_PAD(0x02CC, 0x006C, 3, 0x0000, 0, 0),
+	MX8MP_PAD_ENET_TX_CTL__AUDIOMIX_SPDIF1_OUT               = IOMUX_PAD(0x02CC, 0x006C, 3, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_TX_CTL__GPIO1_IO22                        = IOMUX_PAD(0x02CC, 0x006C, 5, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_TX_CTL__USDHC3_DATA0                      = IOMUX_PAD(0x02CC, 0x006C, 6, 0x0610, 0, 0),
-	MX8MP_PAD_ENET_TX_CTL__SIM_M_HADDR21                     = IOMUX_PAD(0x02CC, 0x006C, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK   = IOMUX_PAD(0x02D0, 0x0070, 0, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_TXC__ENET_QOS_TX_ER                       = IOMUX_PAD(0x02D0, 0x0070, 1, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00              = IOMUX_PAD(0x02D0, 0x0070, 2, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_TXC__GPIO1_IO23                           = IOMUX_PAD(0x02D0, 0x0070, 5, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_TXC__USDHC3_DATA1                         = IOMUX_PAD(0x02D0, 0x0070, 6, 0x0614, 0, 0),
-	MX8MP_PAD_ENET_TXC__SIM_M_HADDR22                        = IOMUX_PAD(0x02D0, 0x0070, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL             = IOMUX_PAD(0x02D4, 0x0074, 0, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC             = IOMUX_PAD(0x02D4, 0x0074, 2, 0x0540, 0, 0),
-	MX8MP_PAD_ENET_RX_CTL__AUDIOMIX_BIT_STREAM03             = IOMUX_PAD(0x02D4, 0x0074, 3, 0x04CC, 0, 0),
+	MX8MP_PAD_ENET_RX_CTL__AUDIOMIX_PDM_BIT_STREAM03         = IOMUX_PAD(0x02D4, 0x0074, 3, 0x04CC, 1, 0),
 	MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24                        = IOMUX_PAD(0x02D4, 0x0074, 5, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_RX_CTL__USDHC3_DATA2                      = IOMUX_PAD(0x02D4, 0x0074, 6, 0x0618, 0, 0),
-	MX8MP_PAD_ENET_RX_CTL__SIM_M_HADDR23                     = IOMUX_PAD(0x02D4, 0x0074, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK   = IOMUX_PAD(0x02D8, 0x0078, 0, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_RXC__ENET_QOS_RX_ER                       = IOMUX_PAD(0x02D8, 0x0078, 1, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK                = IOMUX_PAD(0x02D8, 0x0078, 2, 0x053C, 0, 0),
-	MX8MP_PAD_ENET_RXC__AUDIOMIX_BIT_STREAM02                = IOMUX_PAD(0x02D8, 0x0078, 3, 0x04C8, 0, 0),
+	MX8MP_PAD_ENET_RXC__AUDIOMIX_PDM_BIT_STREAM02            = IOMUX_PAD(0x02D8, 0x0078, 3, 0x04C8, 1, 0),
 	MX8MP_PAD_ENET_RXC__GPIO1_IO25                           = IOMUX_PAD(0x02D8, 0x0078, 5, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_RXC__USDHC3_DATA3                         = IOMUX_PAD(0x02D8, 0x0078, 6, 0x061C, 0, 0),
-	MX8MP_PAD_ENET_RXC__SIM_M_HADDR24                        = IOMUX_PAD(0x02D8, 0x0078, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_ENET_RD0__ENET_QOS_RGMII_RD0                   = IOMUX_PAD(0x02DC, 0x007C, 0, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00              = IOMUX_PAD(0x02DC, 0x007C, 2, 0x0534, 0, 0),
-	MX8MP_PAD_ENET_RD0__AUDIOMIX_BIT_STREAM01                = IOMUX_PAD(0x02DC, 0x007C, 3, 0x04C4, 0, 0),
+	MX8MP_PAD_ENET_RD0__AUDIOMIX_PDM_BIT_STREAM01            = IOMUX_PAD(0x02DC, 0x007C, 3, 0x04C4, 1, 0),
 	MX8MP_PAD_ENET_RD0__GPIO1_IO26                           = IOMUX_PAD(0x02DC, 0x007C, 5, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_RD0__USDHC3_DATA4                         = IOMUX_PAD(0x02DC, 0x007C, 6, 0x0620, 0, 0),
-	MX8MP_PAD_ENET_RD0__SIM_M_HADDR25                        = IOMUX_PAD(0x02DC, 0x007C, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_ENET_RD1__ENET_QOS_RGMII_RD1                   = IOMUX_PAD(0x02E0, 0x0080, 0, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC                = IOMUX_PAD(0x02E0, 0x0080, 2, 0x0538, 0, 0),
-	MX8MP_PAD_ENET_RD1__AUDIOMIX_BIT_STREAM00                = IOMUX_PAD(0x02E0, 0x0080, 3, 0x04C0, 0, 0),
+	MX8MP_PAD_ENET_RD1__AUDIOMIX_PDM_BIT_STREAM00            = IOMUX_PAD(0x02E0, 0x0080, 3, 0x04C0, 1, 0),
 	MX8MP_PAD_ENET_RD1__GPIO1_IO27                           = IOMUX_PAD(0x02E0, 0x0080, 5, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_RD1__USDHC3_RESET_B                       = IOMUX_PAD(0x02E0, 0x0080, 6, 0x0000, 0, 0),
-	MX8MP_PAD_ENET_RD1__SIM_M_HADDR26                        = IOMUX_PAD(0x02E0, 0x0080, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_ENET_RD2__ENET_QOS_RGMII_RD2                   = IOMUX_PAD(0x02E4, 0x0084, 0, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK                = IOMUX_PAD(0x02E4, 0x0084, 2, 0x0530, 0, 0),
-	MX8MP_PAD_ENET_RD2__AUDIOMIX_CLK                         = IOMUX_PAD(0x02E4, 0x0084, 3, 0x0000, 0, 0),
+	MX8MP_PAD_ENET_RD2__AUDIOMIX_PDM_CLK                     = IOMUX_PAD(0x02E4, 0x0084, 3, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_RD2__GPIO1_IO28                           = IOMUX_PAD(0x02E4, 0x0084, 5, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_RD2__USDHC3_CLK                           = IOMUX_PAD(0x02E4, 0x0084, 6, 0x0604, 0, 0),
-	MX8MP_PAD_ENET_RD2__SIM_M_HADDR27                        = IOMUX_PAD(0x02E4, 0x0084, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_ENET_RD3__ENET_QOS_RGMII_RD3                   = IOMUX_PAD(0x02E8, 0x0088, 0, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_RD3__AUDIOMIX_SAI7_MCLK                   = IOMUX_PAD(0x02E8, 0x0088, 2, 0x052C, 0, 0),
-	MX8MP_PAD_ENET_RD3__AUDIOMIX_SPDIF_IN                    = IOMUX_PAD(0x02E8, 0x0088, 3, 0x0544, 0, 0),
+	MX8MP_PAD_ENET_RD3__AUDIOMIX_SPDIF1_IN                   = IOMUX_PAD(0x02E8, 0x0088, 3, 0x0544, 0, 0),
 	MX8MP_PAD_ENET_RD3__GPIO1_IO29                           = IOMUX_PAD(0x02E8, 0x0088, 5, 0x0000, 0, 0),
 	MX8MP_PAD_ENET_RD3__USDHC3_CMD                           = IOMUX_PAD(0x02E8, 0x0088, 6, 0x060C, 0, 0),
-	MX8MP_PAD_ENET_RD3__SIM_M_HADDR28                        = IOMUX_PAD(0x02E8, 0x0088, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD1_CLK__USDHC1_CLK                            = IOMUX_PAD(0x02EC, 0x008C, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_CLK__ENET1_MDC                             = IOMUX_PAD(0x02EC, 0x008C, 1, 0x0000, 0, 0),
@@ -221,7 +187,6 @@ enum {
 	MX8MP_PAD_SD1_CLK__UART1_DCE_TX                          = IOMUX_PAD(0x02EC, 0x008C, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_CLK__UART1_DTE_RX                          = IOMUX_PAD(0x02EC, 0x008C, 4, 0x05E8, 0, 0),
 	MX8MP_PAD_SD1_CLK__GPIO2_IO00                            = IOMUX_PAD(0x02EC, 0x008C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_CLK__SIM_M_HADDR29                         = IOMUX_PAD(0x02EC, 0x008C, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD1_CMD__USDHC1_CMD                            = IOMUX_PAD(0x02F0, 0x0090, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_CMD__ENET1_MDIO                            = IOMUX_PAD(0x02F0, 0x0090, 1, 0x057C, 0, 0),
@@ -229,7 +194,6 @@ enum {
 	MX8MP_PAD_SD1_CMD__UART1_DCE_RX                          = IOMUX_PAD(0x02F0, 0x0090, 4, 0x05E8, 1, 0),
 	MX8MP_PAD_SD1_CMD__UART1_DTE_TX                          = IOMUX_PAD(0x02F0, 0x0090, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_CMD__GPIO2_IO01                            = IOMUX_PAD(0x02F0, 0x0090, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_CMD__SIM_M_HADDR30                         = IOMUX_PAD(0x02F0, 0x0090, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD1_DATA0__USDHC1_DATA0                        = IOMUX_PAD(0x02F4, 0x0094, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_DATA0__ENET1_RGMII_TD1                     = IOMUX_PAD(0x02F4, 0x0094, 1, 0x0000, 0, 0),
@@ -237,7 +201,6 @@ enum {
 	MX8MP_PAD_SD1_DATA0__UART1_DCE_RTS                       = IOMUX_PAD(0x02F4, 0x0094, 4, 0x05E4, 0, 0),
 	MX8MP_PAD_SD1_DATA0__UART1_DTE_CTS                       = IOMUX_PAD(0x02F4, 0x0094, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_DATA0__GPIO2_IO02                          = IOMUX_PAD(0x02F4, 0x0094, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA0__SIM_M_HADDR31                       = IOMUX_PAD(0x02F4, 0x0094, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD1_DATA1__USDHC1_DATA1                        = IOMUX_PAD(0x02F8, 0x0098, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_DATA1__ENET1_RGMII_TD0                     = IOMUX_PAD(0x02F8, 0x0098, 1, 0x0000, 0, 0),
@@ -245,7 +208,6 @@ enum {
 	MX8MP_PAD_SD1_DATA1__UART1_DCE_CTS                       = IOMUX_PAD(0x02F8, 0x0098, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_DATA1__UART1_DTE_RTS                       = IOMUX_PAD(0x02F8, 0x0098, 4, 0x05E4, 1, 0),
 	MX8MP_PAD_SD1_DATA1__GPIO2_IO03                          = IOMUX_PAD(0x02F8, 0x0098, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA1__SIM_M_HBURST00                      = IOMUX_PAD(0x02F8, 0x0098, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD1_DATA2__USDHC1_DATA2                        = IOMUX_PAD(0x02FC, 0x009C, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_DATA2__ENET1_RGMII_RD0                     = IOMUX_PAD(0x02FC, 0x009C, 1, 0x0580, 0, 0),
@@ -253,7 +215,6 @@ enum {
 	MX8MP_PAD_SD1_DATA2__UART2_DCE_TX                        = IOMUX_PAD(0x02FC, 0x009C, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_DATA2__UART2_DTE_RX                        = IOMUX_PAD(0x02FC, 0x009C, 4, 0x05F0, 0, 0),
 	MX8MP_PAD_SD1_DATA2__GPIO2_IO04                          = IOMUX_PAD(0x02FC, 0x009C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA2__SIM_M_HBURST01                      = IOMUX_PAD(0x02FC, 0x009C, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD1_DATA3__USDHC1_DATA3                        = IOMUX_PAD(0x0300, 0x00A0, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_DATA3__ENET1_RGMII_RD1                     = IOMUX_PAD(0x0300, 0x00A0, 1, 0x0584, 0, 0),
@@ -261,7 +222,6 @@ enum {
 	MX8MP_PAD_SD1_DATA3__UART2_DCE_RX                        = IOMUX_PAD(0x0300, 0x00A0, 4, 0x05F0, 1, 0),
 	MX8MP_PAD_SD1_DATA3__UART2_DTE_TX                        = IOMUX_PAD(0x0300, 0x00A0, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_DATA3__GPIO2_IO05                          = IOMUX_PAD(0x0300, 0x00A0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA3__SIM_M_HBURST02                      = IOMUX_PAD(0x0300, 0x00A0, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD1_DATA4__USDHC1_DATA4                        = IOMUX_PAD(0x0304, 0x00A4, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_DATA4__ENET1_RGMII_TX_CTL                  = IOMUX_PAD(0x0304, 0x00A4, 1, 0x0000, 0, 0),
@@ -269,7 +229,6 @@ enum {
 	MX8MP_PAD_SD1_DATA4__UART2_DCE_RTS                       = IOMUX_PAD(0x0304, 0x00A4, 4, 0x05EC, 0, 0),
 	MX8MP_PAD_SD1_DATA4__UART2_DTE_CTS                       = IOMUX_PAD(0x0304, 0x00A4, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_DATA4__GPIO2_IO06                          = IOMUX_PAD(0x0304, 0x00A4, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA4__SIM_M_HRESP                         = IOMUX_PAD(0x0304, 0x00A4, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD1_DATA5__USDHC1_DATA5                        = IOMUX_PAD(0x0308, 0x00A8, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_DATA5__ENET1_TX_ER                         = IOMUX_PAD(0x0308, 0x00A8, 1, 0x0000, 0, 0),
@@ -277,7 +236,6 @@ enum {
 	MX8MP_PAD_SD1_DATA5__UART2_DCE_CTS                       = IOMUX_PAD(0x0308, 0x00A8, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_DATA5__UART2_DTE_RTS                       = IOMUX_PAD(0x0308, 0x00A8, 4, 0x05EC, 1, 0),
 	MX8MP_PAD_SD1_DATA5__GPIO2_IO07                          = IOMUX_PAD(0x0308, 0x00A8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA5__TPSMP_HDATA05                       = IOMUX_PAD(0x0308, 0x00A8, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD1_DATA6__USDHC1_DATA6                        = IOMUX_PAD(0x030C, 0x00AC, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_DATA6__ENET1_RGMII_RX_CTL                  = IOMUX_PAD(0x030C, 0x00AC, 1, 0x0588, 0, 0),
@@ -285,7 +243,6 @@ enum {
 	MX8MP_PAD_SD1_DATA6__UART3_DCE_TX                        = IOMUX_PAD(0x030C, 0x00AC, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_DATA6__UART3_DTE_RX                        = IOMUX_PAD(0x030C, 0x00AC, 4, 0x05F8, 0, 0),
 	MX8MP_PAD_SD1_DATA6__GPIO2_IO08                          = IOMUX_PAD(0x030C, 0x00AC, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA6__TPSMP_HDATA06                       = IOMUX_PAD(0x030C, 0x00AC, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD1_DATA7__USDHC1_DATA7                        = IOMUX_PAD(0x0310, 0x00B0, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_DATA7__ENET1_RX_ER                         = IOMUX_PAD(0x0310, 0x00B0, 1, 0x058C, 0, 0),
@@ -293,7 +250,6 @@ enum {
 	MX8MP_PAD_SD1_DATA7__UART3_DCE_RX                        = IOMUX_PAD(0x0310, 0x00B0, 4, 0x05F8, 1, 0),
 	MX8MP_PAD_SD1_DATA7__UART3_DTE_TX                        = IOMUX_PAD(0x0310, 0x00B0, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_DATA7__GPIO2_IO09                          = IOMUX_PAD(0x0310, 0x00B0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_DATA7__TPSMP_HDATA07                       = IOMUX_PAD(0x0310, 0x00B0, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD1_RESET_B__USDHC1_RESET_B                    = IOMUX_PAD(0x0314, 0x00B4, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_RESET_B__ENET1_TX_CLK                      = IOMUX_PAD(0x0314, 0x00B4, 1, 0x0578, 0, 0),
@@ -301,152 +257,130 @@ enum {
 	MX8MP_PAD_SD1_RESET_B__UART3_DCE_RTS                     = IOMUX_PAD(0x0314, 0x00B4, 4, 0x05F4, 0, 0),
 	MX8MP_PAD_SD1_RESET_B__UART3_DTE_CTS                     = IOMUX_PAD(0x0314, 0x00B4, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_RESET_B__GPIO2_IO10                        = IOMUX_PAD(0x0314, 0x00B4, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_RESET_B__ECSPI3_TEST_TRIG                  = IOMUX_PAD(0x0314, 0x00B4, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD1_STROBE__USDHC1_STROBE                      = IOMUX_PAD(0x0318, 0x00B8, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_STROBE__I2C3_SDA                           = IOMUX_PAD(0x0318, 0x00B8, 3 | IOMUX_CONFIG_SION, 0x05B8, 0, 0),
 	MX8MP_PAD_SD1_STROBE__UART3_DCE_CTS                      = IOMUX_PAD(0x0318, 0x00B8, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SD1_STROBE__UART3_DTE_RTS                      = IOMUX_PAD(0x0318, 0x00B8, 4, 0x05F4, 1, 0),
 	MX8MP_PAD_SD1_STROBE__GPIO2_IO11                         = IOMUX_PAD(0x0318, 0x00B8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD1_STROBE__USDHC3_TEST_TRIG                   = IOMUX_PAD(0x0318, 0x00B8, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD2_CD_B__USDHC2_CD_B                          = IOMUX_PAD(0x031C, 0x00BC, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD2_CD_B__GPIO2_IO12                           = IOMUX_PAD(0x031C, 0x00BC, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK              = IOMUX_PAD(0x031C, 0x00BC, 6, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD2_CLK__USDHC2_CLK                            = IOMUX_PAD(0x0320, 0x00C0, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD2_CLK__ECSPI2_SCLK                           = IOMUX_PAD(0x0320, 0x00C0, 2, 0x0568, 0, 0),
 	MX8MP_PAD_SD2_CLK__UART4_DCE_RX                          = IOMUX_PAD(0x0320, 0x00C0, 3, 0x0600, 0, 0),
 	MX8MP_PAD_SD2_CLK__UART4_DTE_TX                          = IOMUX_PAD(0x0320, 0x00C0, 3, 0x0000, 0, 0),
 	MX8MP_PAD_SD2_CLK__GPIO2_IO13                            = IOMUX_PAD(0x0320, 0x00C0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0                 = IOMUX_PAD(0x0320, 0x00C0, 6, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_CLK__OBSERVE_MUX_OUT00                     = IOMUX_PAD(0x0320, 0x00C0, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD2_CMD__USDHC2_CMD                            = IOMUX_PAD(0x0324, 0x00C4, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD2_CMD__ECSPI2_MOSI                           = IOMUX_PAD(0x0324, 0x00C4, 2, 0x0570, 0, 0),
 	MX8MP_PAD_SD2_CMD__UART4_DCE_TX                          = IOMUX_PAD(0x0324, 0x00C4, 3, 0x0000, 0, 0),
 	MX8MP_PAD_SD2_CMD__UART4_DTE_RX                          = IOMUX_PAD(0x0324, 0x00C4, 3, 0x0600, 1, 0),
-	MX8MP_PAD_SD2_CMD__AUDIOMIX_CLK                          = IOMUX_PAD(0x0324, 0x00C4, 4, 0x0000, 0, 0),
+	MX8MP_PAD_SD2_CMD__AUDIOMIX_PDM_CLK                      = IOMUX_PAD(0x0324, 0x00C4, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SD2_CMD__GPIO2_IO14                            = IOMUX_PAD(0x0324, 0x00C4, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1                 = IOMUX_PAD(0x0324, 0x00C4, 6, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_CMD__OBSERVE_MUX_OUT01                     = IOMUX_PAD(0x0324, 0x00C4, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD2_DATA0__USDHC2_DATA0                        = IOMUX_PAD(0x0328, 0x00C8, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD2_DATA0__I2C4_SDA                            = IOMUX_PAD(0x0328, 0x00C8, 2 | IOMUX_CONFIG_SION, 0x05C0, 1, 0),
 	MX8MP_PAD_SD2_DATA0__UART2_DCE_RX                        = IOMUX_PAD(0x0328, 0x00C8, 3, 0x05F0, 2, 0),
 	MX8MP_PAD_SD2_DATA0__UART2_DTE_TX                        = IOMUX_PAD(0x0328, 0x00C8, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA0__AUDIOMIX_BIT_STREAM00               = IOMUX_PAD(0x0328, 0x00C8, 4, 0x04C0, 1, 0),
+	MX8MP_PAD_SD2_DATA0__AUDIOMIX_PDM_BIT_STREAM00           = IOMUX_PAD(0x0328, 0x00C8, 4, 0x04C0, 2, 0),
 	MX8MP_PAD_SD2_DATA0__GPIO2_IO15                          = IOMUX_PAD(0x0328, 0x00C8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2               = IOMUX_PAD(0x0328, 0x00C8, 6, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA0__OBSERVE_MUX_OUT02                   = IOMUX_PAD(0x0328, 0x00C8, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD2_DATA1__USDHC2_DATA1                        = IOMUX_PAD(0x032C, 0x00CC, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD2_DATA1__I2C4_SCL                            = IOMUX_PAD(0x032C, 0x00CC, 2 | IOMUX_CONFIG_SION, 0x05BC, 1, 0),
 	MX8MP_PAD_SD2_DATA1__UART2_DCE_TX                        = IOMUX_PAD(0x032C, 0x00CC, 3, 0x0000, 0, 0),
 	MX8MP_PAD_SD2_DATA1__UART2_DTE_RX                        = IOMUX_PAD(0x032C, 0x00CC, 3, 0x05F0, 3, 0),
-	MX8MP_PAD_SD2_DATA1__AUDIOMIX_BIT_STREAM01               = IOMUX_PAD(0x032C, 0x00CC, 4, 0x04C4, 1, 0),
+	MX8MP_PAD_SD2_DATA1__AUDIOMIX_PDM_BIT_STREAM01           = IOMUX_PAD(0x032C, 0x00CC, 4, 0x04C4, 2, 0),
 	MX8MP_PAD_SD2_DATA1__GPIO2_IO16                          = IOMUX_PAD(0x032C, 0x00CC, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT                   = IOMUX_PAD(0x032C, 0x00CC, 6, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA1__OBSERVE_MUX_OUT03                   = IOMUX_PAD(0x032C, 0x00CC, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD2_DATA2__USDHC2_DATA2                        = IOMUX_PAD(0x0330, 0x00D0, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD2_DATA2__ECSPI2_SS0                          = IOMUX_PAD(0x0330, 0x00D0, 2, 0x0574, 0, 0),
-	MX8MP_PAD_SD2_DATA2__AUDIOMIX_SPDIF_OUT                  = IOMUX_PAD(0x0330, 0x00D0, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA2__AUDIOMIX_BIT_STREAM02               = IOMUX_PAD(0x0330, 0x00D0, 4, 0x04C8, 1, 0),
+	MX8MP_PAD_SD2_DATA2__AUDIOMIX_SPDIF1_OUT                 = IOMUX_PAD(0x0330, 0x00D0, 3, 0x0000, 0, 0),
+	MX8MP_PAD_SD2_DATA2__AUDIOMIX_PDM_BIT_STREAM02           = IOMUX_PAD(0x0330, 0x00D0, 4, 0x04C8, 2, 0),
 	MX8MP_PAD_SD2_DATA2__GPIO2_IO17                          = IOMUX_PAD(0x0330, 0x00D0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP                   = IOMUX_PAD(0x0330, 0x00D0, 6, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA2__OBSERVE_MUX_OUT04                   = IOMUX_PAD(0x0330, 0x00D0, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD2_DATA3__USDHC2_DATA3                        = IOMUX_PAD(0x0334, 0x00D4, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD2_DATA3__ECSPI2_MISO                         = IOMUX_PAD(0x0334, 0x00D4, 2, 0x056C, 0, 0),
-	MX8MP_PAD_SD2_DATA3__AUDIOMIX_SPDIF_IN                   = IOMUX_PAD(0x0334, 0x00D4, 3, 0x0544, 1, 0),
-	MX8MP_PAD_SD2_DATA3__AUDIOMIX_BIT_STREAM03               = IOMUX_PAD(0x0334, 0x00D4, 4, 0x04CC, 1, 0),
+	MX8MP_PAD_SD2_DATA3__AUDIOMIX_SPDIF1_IN                  = IOMUX_PAD(0x0334, 0x00D4, 3, 0x0544, 1, 0),
+	MX8MP_PAD_SD2_DATA3__AUDIOMIX_PDM_BIT_STREAM03           = IOMUX_PAD(0x0334, 0x00D4, 4, 0x04CC, 2, 0),
 	MX8MP_PAD_SD2_DATA3__GPIO2_IO18                          = IOMUX_PAD(0x0334, 0x00D4, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET            = IOMUX_PAD(0x0334, 0x00D4, 6, 0x0000, 0, 0),
+	MX8MP_PAD_SD2_DATA3__SRC_EARLY_RESET                     = IOMUX_PAD(0x0334, 0x00D4, 6, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD2_RESET_B__USDHC2_RESET_B                    = IOMUX_PAD(0x0338, 0x00D8, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD2_RESET_B__GPIO2_IO19                        = IOMUX_PAD(0x0338, 0x00D8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET         = IOMUX_PAD(0x0338, 0x00D8, 6, 0x0000, 0, 0),
+	MX8MP_PAD_SD2_RESET_B__SRC_SYSTEM_RESET                  = IOMUX_PAD(0x0338, 0x00D8, 6, 0x0000, 0, 0),
 
 	MX8MP_PAD_SD2_WP__USDHC2_WP                              = IOMUX_PAD(0x033C, 0x00DC, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SD2_WP__GPIO2_IO20                             = IOMUX_PAD(0x033C, 0x00DC, 5, 0x0000, 0, 0),
 	MX8MP_PAD_SD2_WP__CORESIGHT_EVENTI                       = IOMUX_PAD(0x033C, 0x00DC, 6, 0x0000, 0, 0),
-	MX8MP_PAD_SD2_WP__SIM_M_HMASTLOCK                        = IOMUX_PAD(0x033C, 0x00DC, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_NAND_ALE__RAWNAND_ALE                          = IOMUX_PAD(0x0340, 0x00E0, 0, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_ALE__NAND_ALE                             = IOMUX_PAD(0x0340, 0x00E0, 0, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_ALE__FLEXSPI_A_SCLK                       = IOMUX_PAD(0x0340, 0x00E0, 1, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK                = IOMUX_PAD(0x0340, 0x00E0, 2, 0x04E8, 0, 0),
-	MX8MP_PAD_NAND_ALE__MEDIAMIX_ISP_FL_TRIG_0               = IOMUX_PAD(0x0340, 0x00E0, 3, 0x05D4, 1, 0),
+	MX8MP_PAD_NAND_ALE__ISP_FL_TRIG_0                        = IOMUX_PAD(0x0340, 0x00E0, 3, 0x05D4, 1, 0),
 	MX8MP_PAD_NAND_ALE__UART3_DCE_RX                         = IOMUX_PAD(0x0340, 0x00E0, 4, 0x05F8, 2, 0),
 	MX8MP_PAD_NAND_ALE__UART3_DTE_TX                         = IOMUX_PAD(0x0340, 0x00E0, 4, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_ALE__GPIO3_IO00                           = IOMUX_PAD(0x0340, 0x00E0, 5, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_ALE__CORESIGHT_TRACE_CLK                  = IOMUX_PAD(0x0340, 0x00E0, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_ALE__SIM_M_HPROT00                        = IOMUX_PAD(0x0340, 0x00E0, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_NAND_CE0_B__RAWNAND_CE0_B                      = IOMUX_PAD(0x0344, 0x00E4, 0, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_CE0_B__NAND_CE0_B                         = IOMUX_PAD(0x0344, 0x00E4, 0, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_CE0_B__FLEXSPI_A_SS0_B                    = IOMUX_PAD(0x0344, 0x00E4, 1, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00            = IOMUX_PAD(0x0344, 0x00E4, 2, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE0_B__MEDIAMIX_ISP_SHUTTER_TRIG_0        = IOMUX_PAD(0x0344, 0x00E4, 3, 0x05DC, 1, 0),
+	MX8MP_PAD_NAND_CE0_B__ISP_SHUTTER_TRIG_0                 = IOMUX_PAD(0x0344, 0x00E4, 3, 0x05DC, 1, 0),
 	MX8MP_PAD_NAND_CE0_B__UART3_DCE_TX                       = IOMUX_PAD(0x0344, 0x00E4, 4, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_CE0_B__UART3_DTE_RX                       = IOMUX_PAD(0x0344, 0x00E4, 4, 0x05F8, 3, 0),
 	MX8MP_PAD_NAND_CE0_B__GPIO3_IO01                         = IOMUX_PAD(0x0344, 0x00E4, 5, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_CE0_B__CORESIGHT_TRACE_CTL                = IOMUX_PAD(0x0344, 0x00E4, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE0_B__SIM_M_HPROT01                      = IOMUX_PAD(0x0344, 0x00E4, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_NAND_CE1_B__RAWNAND_CE1_B                      = IOMUX_PAD(0x0348, 0x00E8, 0, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_CE1_B__NAND_CE1_B                         = IOMUX_PAD(0x0348, 0x00E8, 0, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_CE1_B__FLEXSPI_A_SS1_B                    = IOMUX_PAD(0x0348, 0x00E8, 1, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_CE1_B__USDHC3_STROBE                      = IOMUX_PAD(0x0348, 0x00E8, 2, 0x0630, 1, 0),
 	MX8MP_PAD_NAND_CE1_B__I2C4_SCL                           = IOMUX_PAD(0x0348, 0x00E8, 4 | IOMUX_CONFIG_SION, 0x05BC, 2, 0),
 	MX8MP_PAD_NAND_CE1_B__GPIO3_IO02                         = IOMUX_PAD(0x0348, 0x00E8, 5, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_CE1_B__CORESIGHT_TRACE00                  = IOMUX_PAD(0x0348, 0x00E8, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE1_B__SIM_M_HPROT02                      = IOMUX_PAD(0x0348, 0x00E8, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_NAND_CE2_B__RAWNAND_CE2_B                      = IOMUX_PAD(0x034C, 0x00EC, 0, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_CE2_B__NAND_CE2_B                         = IOMUX_PAD(0x034C, 0x00EC, 0, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_CE2_B__FLEXSPI_B_SS0_B                    = IOMUX_PAD(0x034C, 0x00EC, 1, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5                       = IOMUX_PAD(0x034C, 0x00EC, 2, 0x0624, 1, 0),
 	MX8MP_PAD_NAND_CE2_B__I2C4_SDA                           = IOMUX_PAD(0x034C, 0x00EC, 4 | IOMUX_CONFIG_SION, 0x05C0, 2, 0),
 	MX8MP_PAD_NAND_CE2_B__GPIO3_IO03                         = IOMUX_PAD(0x034C, 0x00EC, 5, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_CE2_B__CORESIGHT_TRACE01                  = IOMUX_PAD(0x034C, 0x00EC, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE2_B__SIM_M_HPROT03                      = IOMUX_PAD(0x034C, 0x00EC, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_NAND_CE3_B__RAWNAND_CE3_B                      = IOMUX_PAD(0x0350, 0x00F0, 0, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_CE3_B__NAND_CE3_B                         = IOMUX_PAD(0x0350, 0x00F0, 0, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_CE3_B__FLEXSPI_B_SS1_B                    = IOMUX_PAD(0x0350, 0x00F0, 1, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6                       = IOMUX_PAD(0x0350, 0x00F0, 2, 0x0628, 1, 0),
 	MX8MP_PAD_NAND_CE3_B__I2C3_SDA                           = IOMUX_PAD(0x0350, 0x00F0, 4 | IOMUX_CONFIG_SION, 0x05B8, 1, 0),
 	MX8MP_PAD_NAND_CE3_B__GPIO3_IO04                         = IOMUX_PAD(0x0350, 0x00F0, 5, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_CE3_B__CORESIGHT_TRACE02                  = IOMUX_PAD(0x0350, 0x00F0, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CE3_B__SIM_M_HADDR00                      = IOMUX_PAD(0x0350, 0x00F0, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_NAND_CLE__RAWNAND_CLE                          = IOMUX_PAD(0x0354, 0x00F4, 0, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_CLE__NAND_CLE                             = IOMUX_PAD(0x0354, 0x00F4, 0, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_CLE__FLEXSPI_B_SCLK                       = IOMUX_PAD(0x0354, 0x00F4, 1, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_CLE__USDHC3_DATA7                         = IOMUX_PAD(0x0354, 0x00F4, 2, 0x062C, 1, 0),
 	MX8MP_PAD_NAND_CLE__UART4_DCE_RX                         = IOMUX_PAD(0x0354, 0x00F4, 4, 0x0600, 2, 0),
 	MX8MP_PAD_NAND_CLE__UART4_DTE_TX                         = IOMUX_PAD(0x0354, 0x00F4, 4, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_CLE__GPIO3_IO05                           = IOMUX_PAD(0x0354, 0x00F4, 5, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_CLE__CORESIGHT_TRACE03                    = IOMUX_PAD(0x0354, 0x00F4, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_CLE__SIM_M_HADDR01                        = IOMUX_PAD(0x0354, 0x00F4, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_NAND_DATA00__RAWNAND_DATA00                    = IOMUX_PAD(0x0358, 0x00F8, 0, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_DATA00__NAND_DATA00                       = IOMUX_PAD(0x0358, 0x00F8, 0, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA00__FLEXSPI_A_DATA00                  = IOMUX_PAD(0x0358, 0x00F8, 1, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00           = IOMUX_PAD(0x0358, 0x00F8, 2, 0x04E4, 0, 0),
-	MX8MP_PAD_NAND_DATA00__MEDIAMIX_ISP_FLASH_TRIG_0         = IOMUX_PAD(0x0358, 0x00F8, 3, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_DATA00__ISP_FLASH_TRIG_0                  = IOMUX_PAD(0x0358, 0x00F8, 3, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA00__UART4_DCE_RX                      = IOMUX_PAD(0x0358, 0x00F8, 4, 0x0600, 3, 0),
 	MX8MP_PAD_NAND_DATA00__UART4_DTE_TX                      = IOMUX_PAD(0x0358, 0x00F8, 4, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA00__GPIO3_IO06                        = IOMUX_PAD(0x0358, 0x00F8, 5, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA00__CORESIGHT_TRACE04                 = IOMUX_PAD(0x0358, 0x00F8, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA00__SIM_M_HADDR02                     = IOMUX_PAD(0x0358, 0x00F8, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_NAND_DATA01__RAWNAND_DATA01                    = IOMUX_PAD(0x035C, 0x00FC, 0, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_DATA01__NAND_DATA01                       = IOMUX_PAD(0x035C, 0x00FC, 0, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA01__FLEXSPI_A_DATA01                  = IOMUX_PAD(0x035C, 0x00FC, 1, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC             = IOMUX_PAD(0x035C, 0x00FC, 2, 0x04EC, 0, 0),
-	MX8MP_PAD_NAND_DATA01__MEDIAMIX_ISP_PRELIGHT_TRIG_0      = IOMUX_PAD(0x035C, 0x00FC, 3, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_DATA01__ISP_PRELIGHT_TRIG_0               = IOMUX_PAD(0x035C, 0x00FC, 3, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA01__UART4_DCE_TX                      = IOMUX_PAD(0x035C, 0x00FC, 4, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA01__UART4_DTE_RX                      = IOMUX_PAD(0x035C, 0x00FC, 4, 0x0600, 4, 0),
 	MX8MP_PAD_NAND_DATA01__GPIO3_IO07                        = IOMUX_PAD(0x035C, 0x00FC, 5, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA01__CORESIGHT_TRACE05                 = IOMUX_PAD(0x035C, 0x00FC, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA01__SIM_M_HADDR03                     = IOMUX_PAD(0x035C, 0x00FC, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_NAND_DATA02__RAWNAND_DATA02                    = IOMUX_PAD(0x0360, 0x0100, 0, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_DATA02__NAND_DATA02                       = IOMUX_PAD(0x0360, 0x0100, 0, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA02__FLEXSPI_A_DATA02                  = IOMUX_PAD(0x0360, 0x0100, 1, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA02__USDHC3_CD_B                       = IOMUX_PAD(0x0360, 0x0100, 2, 0x0608, 2, 0),
 	MX8MP_PAD_NAND_DATA02__UART4_DCE_CTS                     = IOMUX_PAD(0x0360, 0x0100, 3, 0x0000, 0, 0),
@@ -454,92 +388,81 @@ enum {
 	MX8MP_PAD_NAND_DATA02__I2C4_SDA                          = IOMUX_PAD(0x0360, 0x0100, 4 | IOMUX_CONFIG_SION, 0x05C0, 3, 0),
 	MX8MP_PAD_NAND_DATA02__GPIO3_IO08                        = IOMUX_PAD(0x0360, 0x0100, 5, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA02__CORESIGHT_TRACE06                 = IOMUX_PAD(0x0360, 0x0100, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA02__SIM_M_HADDR04                     = IOMUX_PAD(0x0360, 0x0100, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_NAND_DATA03__RAWNAND_DATA03                    = IOMUX_PAD(0x0364, 0x0104, 0, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_DATA03__NAND_DATA03                       = IOMUX_PAD(0x0364, 0x0104, 0, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA03__FLEXSPI_A_DATA03                  = IOMUX_PAD(0x0364, 0x0104, 1, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA03__USDHC3_WP                         = IOMUX_PAD(0x0364, 0x0104, 2, 0x0634, 2, 0),
 	MX8MP_PAD_NAND_DATA03__UART4_DCE_RTS                     = IOMUX_PAD(0x0364, 0x0104, 3, 0x05FC, 1, 0),
 	MX8MP_PAD_NAND_DATA03__UART4_DTE_CTS                     = IOMUX_PAD(0x0364, 0x0104, 3, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA03__MEDIAMIX_ISP_FL_TRIG_1            = IOMUX_PAD(0x0364, 0x0104, 4, 0x05D8, 1, 0),
+	MX8MP_PAD_NAND_DATA03__ISP_FL_TRIG_1                     = IOMUX_PAD(0x0364, 0x0104, 4, 0x05D8, 1, 0),
 	MX8MP_PAD_NAND_DATA03__GPIO3_IO09                        = IOMUX_PAD(0x0364, 0x0104, 5, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA03__CORESIGHT_TRACE07                 = IOMUX_PAD(0x0364, 0x0104, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA03__SIM_M_HADDR05                     = IOMUX_PAD(0x0364, 0x0104, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_NAND_DATA04__RAWNAND_DATA04                    = IOMUX_PAD(0x0368, 0x0108, 0, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_DATA04__NAND_DATA04                       = IOMUX_PAD(0x0368, 0x0108, 0, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA04__FLEXSPI_B_DATA00                  = IOMUX_PAD(0x0368, 0x0108, 1, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA04__USDHC3_DATA0                      = IOMUX_PAD(0x0368, 0x0108, 2, 0x0610, 1, 0),
 	MX8MP_PAD_NAND_DATA04__FLEXSPI_A_DATA04                  = IOMUX_PAD(0x0368, 0x0108, 3, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA04__MEDIAMIX_ISP_SHUTTER_TRIG_1       = IOMUX_PAD(0x0368, 0x0108, 4, 0x05E0, 1, 0),
+	MX8MP_PAD_NAND_DATA04__ISP_SHUTTER_TRIG_1                = IOMUX_PAD(0x0368, 0x0108, 4, 0x05E0, 1, 0),
 	MX8MP_PAD_NAND_DATA04__GPIO3_IO10                        = IOMUX_PAD(0x0368, 0x0108, 5, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA04__CORESIGHT_TRACE08                 = IOMUX_PAD(0x0368, 0x0108, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA04__SIM_M_HADDR06                     = IOMUX_PAD(0x0368, 0x0108, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_NAND_DATA05__RAWNAND_DATA05                    = IOMUX_PAD(0x036C, 0x010C, 0, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_DATA05__NAND_DATA05                       = IOMUX_PAD(0x036C, 0x010C, 0, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA05__FLEXSPI_B_DATA01                  = IOMUX_PAD(0x036C, 0x010C, 1, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA05__USDHC3_DATA1                      = IOMUX_PAD(0x036C, 0x010C, 2, 0x0614, 1, 0),
 	MX8MP_PAD_NAND_DATA05__FLEXSPI_A_DATA05                  = IOMUX_PAD(0x036C, 0x010C, 3, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA05__MEDIAMIX_ISP_FLASH_TRIG_1         = IOMUX_PAD(0x036C, 0x010C, 4, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_DATA05__ISP_FLASH_TRIG_1                  = IOMUX_PAD(0x036C, 0x010C, 4, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA05__GPIO3_IO11                        = IOMUX_PAD(0x036C, 0x010C, 5, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA05__CORESIGHT_TRACE09                 = IOMUX_PAD(0x036C, 0x010C, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA05__SIM_M_HADDR07                     = IOMUX_PAD(0x036C, 0x010C, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_NAND_DATA06__RAWNAND_DATA06                    = IOMUX_PAD(0x0370, 0x0110, 0, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_DATA06__NAND_DATA06                       = IOMUX_PAD(0x0370, 0x0110, 0, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA06__FLEXSPI_B_DATA02                  = IOMUX_PAD(0x0370, 0x0110, 1, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA06__USDHC3_DATA2                      = IOMUX_PAD(0x0370, 0x0110, 2, 0x0618, 1, 0),
 	MX8MP_PAD_NAND_DATA06__FLEXSPI_A_DATA06                  = IOMUX_PAD(0x0370, 0x0110, 3, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA06__MEDIAMIX_ISP_PRELIGHT_TRIG_1      = IOMUX_PAD(0x0370, 0x0110, 4, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_DATA06__ISP_PRELIGHT_TRIG_1               = IOMUX_PAD(0x0370, 0x0110, 4, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA06__GPIO3_IO12                        = IOMUX_PAD(0x0370, 0x0110, 5, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA06__CORESIGHT_TRACE10                 = IOMUX_PAD(0x0370, 0x0110, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA06__SIM_M_HADDR08                     = IOMUX_PAD(0x0370, 0x0110, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_NAND_DATA07__RAWNAND_DATA07                    = IOMUX_PAD(0x0374, 0x0114, 0, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_DATA07__NAND_DATA07                       = IOMUX_PAD(0x0374, 0x0114, 0, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA07__FLEXSPI_B_DATA03                  = IOMUX_PAD(0x0374, 0x0114, 1, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA07__USDHC3_DATA3                      = IOMUX_PAD(0x0374, 0x0114, 2, 0x061C, 1, 0),
 	MX8MP_PAD_NAND_DATA07__FLEXSPI_A_DATA07                  = IOMUX_PAD(0x0374, 0x0114, 3, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA07__MEDIAMIX_ISP_SHUTTER_OPEN_1       = IOMUX_PAD(0x0374, 0x0114, 4, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_DATA07__ISP_SHUTTER_OPEN_1                = IOMUX_PAD(0x0374, 0x0114, 4, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA07__GPIO3_IO13                        = IOMUX_PAD(0x0374, 0x0114, 5, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DATA07__CORESIGHT_TRACE11                 = IOMUX_PAD(0x0374, 0x0114, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DATA07__SIM_M_HADDR09                     = IOMUX_PAD(0x0374, 0x0114, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_NAND_DQS__RAWNAND_DQS                          = IOMUX_PAD(0x0378, 0x0118, 0, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_DQS__NAND_DQS                             = IOMUX_PAD(0x0378, 0x0118, 0, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DQS__FLEXSPI_A_DQS                        = IOMUX_PAD(0x0378, 0x0118, 1, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DQS__AUDIOMIX_SAI3_MCLK                   = IOMUX_PAD(0x0378, 0x0118, 2, 0x04E0, 0, 0),
-	MX8MP_PAD_NAND_DQS__MEDIAMIX_ISP_SHUTTER_OPEN_0          = IOMUX_PAD(0x0378, 0x0118, 3, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_DQS__ISP_SHUTTER_OPEN_0                   = IOMUX_PAD(0x0378, 0x0118, 3, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DQS__I2C3_SCL                             = IOMUX_PAD(0x0378, 0x0118, 4 | IOMUX_CONFIG_SION, 0x05B4, 1, 0),
 	MX8MP_PAD_NAND_DQS__GPIO3_IO14                           = IOMUX_PAD(0x0378, 0x0118, 5, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_DQS__CORESIGHT_TRACE12                    = IOMUX_PAD(0x0378, 0x0118, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_DQS__SIM_M_HADDR10                        = IOMUX_PAD(0x0378, 0x0118, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_NAND_RE_B__RAWNAND_RE_B                        = IOMUX_PAD(0x037C, 0x011C, 0, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_RE_B__NAND_RE_B                           = IOMUX_PAD(0x037C, 0x011C, 0, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_RE_B__FLEXSPI_B_DQS                       = IOMUX_PAD(0x037C, 0x011C, 1, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_RE_B__USDHC3_DATA4                        = IOMUX_PAD(0x037C, 0x011C, 2, 0x0620, 1, 0),
 	MX8MP_PAD_NAND_RE_B__UART4_DCE_TX                        = IOMUX_PAD(0x037C, 0x011C, 4, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_RE_B__UART4_DTE_RX                        = IOMUX_PAD(0x037C, 0x011C, 4, 0x0600, 5, 0),
 	MX8MP_PAD_NAND_RE_B__GPIO3_IO15                          = IOMUX_PAD(0x037C, 0x011C, 5, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_RE_B__CORESIGHT_TRACE13                   = IOMUX_PAD(0x037C, 0x011C, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_RE_B__SIM_M_HADDR11                       = IOMUX_PAD(0x037C, 0x011C, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_NAND_READY_B__RAWNAND_READY_B                  = IOMUX_PAD(0x0380, 0x0120, 0, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_READY_B__NAND_READY_B                     = IOMUX_PAD(0x0380, 0x0120, 0, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_READY_B__USDHC3_RESET_B                   = IOMUX_PAD(0x0380, 0x0120, 2, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_READY_B__I2C3_SCL                         = IOMUX_PAD(0x0380, 0x0120, 4 | IOMUX_CONFIG_SION, 0x05B4, 2, 0),
 	MX8MP_PAD_NAND_READY_B__GPIO3_IO16                       = IOMUX_PAD(0x0380, 0x0120, 5, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_READY_B__CORESIGHT_TRACE14                = IOMUX_PAD(0x0380, 0x0120, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_READY_B__SIM_M_HADDR12                    = IOMUX_PAD(0x0380, 0x0120, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_NAND_WE_B__RAWNAND_WE_B                        = IOMUX_PAD(0x0384, 0x0124, 0, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_WE_B__NAND_WE_B                           = IOMUX_PAD(0x0384, 0x0124, 0, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_WE_B__USDHC3_CLK                          = IOMUX_PAD(0x0384, 0x0124, 2, 0x0604, 1, 0),
 	MX8MP_PAD_NAND_WE_B__I2C3_SDA                            = IOMUX_PAD(0x0384, 0x0124, 4 | IOMUX_CONFIG_SION, 0x05B8, 2, 0),
 	MX8MP_PAD_NAND_WE_B__GPIO3_IO17                          = IOMUX_PAD(0x0384, 0x0124, 5, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_WE_B__CORESIGHT_TRACE15                   = IOMUX_PAD(0x0384, 0x0124, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_WE_B__SIM_M_HADDR13                       = IOMUX_PAD(0x0384, 0x0124, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_NAND_WP_B__RAWNAND_WP_B                        = IOMUX_PAD(0x0388, 0x0128, 0, 0x0000, 0, 0),
+	MX8MP_PAD_NAND_WP_B__NAND_WP_B                           = IOMUX_PAD(0x0388, 0x0128, 0, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_WP_B__USDHC3_CMD                          = IOMUX_PAD(0x0388, 0x0128, 2, 0x060C, 1, 0),
 	MX8MP_PAD_NAND_WP_B__I2C4_SCL                            = IOMUX_PAD(0x0388, 0x0128, 4 | IOMUX_CONFIG_SION, 0x05BC, 3, 0),
 	MX8MP_PAD_NAND_WP_B__GPIO3_IO18                          = IOMUX_PAD(0x0388, 0x0128, 5, 0x0000, 0, 0),
 	MX8MP_PAD_NAND_WP_B__CORESIGHT_EVENTO                    = IOMUX_PAD(0x0388, 0x0128, 6, 0x0000, 0, 0),
-	MX8MP_PAD_NAND_WP_B__SIM_M_HADDR14                       = IOMUX_PAD(0x0388, 0x0128, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC               = IOMUX_PAD(0x038C, 0x012C, 0, 0x0508, 0, 0),
 	MX8MP_PAD_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00             = IOMUX_PAD(0x038C, 0x012C, 1, 0x0000, 0, 0),
@@ -551,21 +474,21 @@ enum {
 	MX8MP_PAD_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01              = IOMUX_PAD(0x0390, 0x0130, 1, 0x0000, 0, 0),
 	MX8MP_PAD_SAI5_RXC__PWM3_OUT                             = IOMUX_PAD(0x0390, 0x0130, 2, 0x0000, 0, 0),
 	MX8MP_PAD_SAI5_RXC__I2C6_SDA                             = IOMUX_PAD(0x0390, 0x0130, 3 | IOMUX_CONFIG_SION, 0x05D0, 1, 0),
-	MX8MP_PAD_SAI5_RXC__AUDIOMIX_CLK                         = IOMUX_PAD(0x0390, 0x0130, 4, 0x0000, 0, 0),
+	MX8MP_PAD_SAI5_RXC__AUDIOMIX_PDM_CLK                     = IOMUX_PAD(0x0390, 0x0130, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI5_RXC__GPIO3_IO20                           = IOMUX_PAD(0x0390, 0x0130, 5, 0x0000, 0, 0),
 
 	MX8MP_PAD_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00             = IOMUX_PAD(0x0394, 0x0134, 0, 0x04F8, 0, 0),
 	MX8MP_PAD_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02             = IOMUX_PAD(0x0394, 0x0134, 1, 0x0000, 0, 0),
 	MX8MP_PAD_SAI5_RXD0__PWM2_OUT                            = IOMUX_PAD(0x0394, 0x0134, 2, 0x0000, 0, 0),
 	MX8MP_PAD_SAI5_RXD0__I2C5_SCL                            = IOMUX_PAD(0x0394, 0x0134, 3 | IOMUX_CONFIG_SION, 0x05C4, 1, 0),
-	MX8MP_PAD_SAI5_RXD0__AUDIOMIX_BIT_STREAM00               = IOMUX_PAD(0x0394, 0x0134, 4, 0x04C0, 2, 0),
+	MX8MP_PAD_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00           = IOMUX_PAD(0x0394, 0x0134, 4, 0x04C0, 3, 0),
 	MX8MP_PAD_SAI5_RXD0__GPIO3_IO21                          = IOMUX_PAD(0x0394, 0x0134, 5, 0x0000, 0, 0),
 
 	MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01             = IOMUX_PAD(0x0398, 0x0138, 0, 0x04FC, 0, 0),
 	MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03             = IOMUX_PAD(0x0398, 0x0138, 1, 0x0000, 0, 0),
 	MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC               = IOMUX_PAD(0x0398, 0x0138, 2, 0x04D8, 0, 0),
 	MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC               = IOMUX_PAD(0x0398, 0x0138, 3, 0x0510, 0, 0),
-	MX8MP_PAD_SAI5_RXD1__AUDIOMIX_BIT_STREAM01               = IOMUX_PAD(0x0398, 0x0138, 4, 0x04C4, 2, 0),
+	MX8MP_PAD_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01           = IOMUX_PAD(0x0398, 0x0138, 4, 0x04C4, 3, 0),
 	MX8MP_PAD_SAI5_RXD1__GPIO3_IO22                          = IOMUX_PAD(0x0398, 0x0138, 5, 0x0000, 0, 0),
 	MX8MP_PAD_SAI5_RXD1__CAN1_TX                             = IOMUX_PAD(0x0398, 0x0138, 6, 0x0000, 0, 0),
 
@@ -573,7 +496,7 @@ enum {
 	MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04             = IOMUX_PAD(0x039C, 0x013C, 1, 0x0000, 0, 0),
 	MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC               = IOMUX_PAD(0x039C, 0x013C, 2, 0x04D8, 1, 0),
 	MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK               = IOMUX_PAD(0x039C, 0x013C, 3, 0x050C, 0, 0),
-	MX8MP_PAD_SAI5_RXD2__AUDIOMIX_BIT_STREAM02               = IOMUX_PAD(0x039C, 0x013C, 4, 0x04C8, 2, 0),
+	MX8MP_PAD_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02           = IOMUX_PAD(0x039C, 0x013C, 4, 0x04C8, 3, 0),
 	MX8MP_PAD_SAI5_RXD2__GPIO3_IO23                          = IOMUX_PAD(0x039C, 0x013C, 5, 0x0000, 0, 0),
 	MX8MP_PAD_SAI5_RXD2__CAN1_RX                             = IOMUX_PAD(0x039C, 0x013C, 6, 0x054C, 0, 0),
 
@@ -581,7 +504,7 @@ enum {
 	MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05             = IOMUX_PAD(0x03A0, 0x0140, 1, 0x0000, 0, 0),
 	MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC               = IOMUX_PAD(0x03A0, 0x0140, 2, 0x04D8, 2, 0),
 	MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00             = IOMUX_PAD(0x03A0, 0x0140, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SAI5_RXD3__AUDIOMIX_BIT_STREAM03               = IOMUX_PAD(0x03A0, 0x0140, 4, 0x04CC, 2, 0),
+	MX8MP_PAD_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03           = IOMUX_PAD(0x03A0, 0x0140, 4, 0x04CC, 3, 0),
 	MX8MP_PAD_SAI5_RXD3__GPIO3_IO24                          = IOMUX_PAD(0x03A0, 0x0140, 5, 0x0000, 0, 0),
 	MX8MP_PAD_SAI5_RXD3__CAN2_TX                             = IOMUX_PAD(0x03A0, 0x0140, 6, 0x0000, 0, 0),
 
@@ -593,38 +516,32 @@ enum {
 	MX8MP_PAD_SAI5_MCLK__CAN2_RX                             = IOMUX_PAD(0x03A4, 0x0144, 6, 0x0550, 0, 0),
 
 	MX8MP_PAD_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC               = IOMUX_PAD(0x03A8, 0x0148, 0, 0x04D0, 0, 0),
-	MX8MP_PAD_SAI1_RXFS__AUDIOMIX_SAI5_RX_SYNC               = IOMUX_PAD(0x03A8, 0x0148, 1, 0x0508, 1, 0),
 	MX8MP_PAD_SAI1_RXFS__ENET1_1588_EVENT0_IN                = IOMUX_PAD(0x03A8, 0x0148, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI1_RXFS__GPIO4_IO00                          = IOMUX_PAD(0x03A8, 0x0148, 5, 0x0000, 0, 0),
 
 	MX8MP_PAD_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK                = IOMUX_PAD(0x03AC, 0x014C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXC__AUDIOMIX_SAI5_RX_BCLK                = IOMUX_PAD(0x03AC, 0x014C, 1, 0x04F4, 1, 0),
-	MX8MP_PAD_SAI1_RXC__AUDIOMIX_CLK                         = IOMUX_PAD(0x03AC, 0x014C, 3, 0x0000, 0, 0),
+	MX8MP_PAD_SAI1_RXC__AUDIOMIX_PDM_CLK                     = IOMUX_PAD(0x03AC, 0x014C, 3, 0x0000, 0, 0),
 	MX8MP_PAD_SAI1_RXC__ENET1_1588_EVENT0_OUT                = IOMUX_PAD(0x03AC, 0x014C, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI1_RXC__GPIO4_IO01                           = IOMUX_PAD(0x03AC, 0x014C, 5, 0x0000, 0, 0),
 
 	MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00             = IOMUX_PAD(0x03B0, 0x0150, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI5_RX_DATA00             = IOMUX_PAD(0x03B0, 0x0150, 1, 0x04F8, 1, 0),
 	MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01             = IOMUX_PAD(0x03B0, 0x0150, 2, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD0__AUDIOMIX_BIT_STREAM00               = IOMUX_PAD(0x03B0, 0x0150, 3, 0x04C0, 3, 0),
+	MX8MP_PAD_SAI1_RXD0__AUDIOMIX_PDM_BIT_STREAM00           = IOMUX_PAD(0x03B0, 0x0150, 3, 0x04C0, 4, 0),
 	MX8MP_PAD_SAI1_RXD0__ENET1_1588_EVENT1_IN                = IOMUX_PAD(0x03B0, 0x0150, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI1_RXD0__GPIO4_IO02                          = IOMUX_PAD(0x03B0, 0x0150, 5, 0x0000, 0, 0),
 
 	MX8MP_PAD_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01             = IOMUX_PAD(0x03B4, 0x0154, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD1__AUDIOMIX_SAI5_RX_DATA01             = IOMUX_PAD(0x03B4, 0x0154, 1, 0x04FC, 1, 0),
-	MX8MP_PAD_SAI1_RXD1__AUDIOMIX_BIT_STREAM01               = IOMUX_PAD(0x03B4, 0x0154, 3, 0x04C4, 3, 0),
+	MX8MP_PAD_SAI1_RXD1__AUDIOMIX_PDM_BIT_STREAM01           = IOMUX_PAD(0x03B4, 0x0154, 3, 0x04C4, 4, 0),
 	MX8MP_PAD_SAI1_RXD1__ENET1_1588_EVENT1_OUT               = IOMUX_PAD(0x03B4, 0x0154, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI1_RXD1__GPIO4_IO03                          = IOMUX_PAD(0x03B4, 0x0154, 5, 0x0000, 0, 0),
 
 	MX8MP_PAD_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02             = IOMUX_PAD(0x03B8, 0x0158, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD2__AUDIOMIX_SAI5_RX_DATA02             = IOMUX_PAD(0x03B8, 0x0158, 1, 0x0500, 1, 0),
-	MX8MP_PAD_SAI1_RXD2__AUDIOMIX_BIT_STREAM02               = IOMUX_PAD(0x03B8, 0x0158, 3, 0x04C8, 3, 0),
+	MX8MP_PAD_SAI1_RXD2__AUDIOMIX_PDM_BIT_STREAM02           = IOMUX_PAD(0x03B8, 0x0158, 3, 0x04C8, 4, 0),
 	MX8MP_PAD_SAI1_RXD2__ENET1_MDC                           = IOMUX_PAD(0x03B8, 0x0158, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI1_RXD2__GPIO4_IO04                          = IOMUX_PAD(0x03B8, 0x0158, 5, 0x0000, 0, 0),
 
 	MX8MP_PAD_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03             = IOMUX_PAD(0x03BC, 0x015C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_RXD3__AUDIOMIX_SAI5_RX_DATA03             = IOMUX_PAD(0x03BC, 0x015C, 1, 0x0504, 1, 0),
-	MX8MP_PAD_SAI1_RXD3__AUDIOMIX_BIT_STREAM03               = IOMUX_PAD(0x03BC, 0x015C, 3, 0x04CC, 3, 0),
+	MX8MP_PAD_SAI1_RXD3__AUDIOMIX_PDM_BIT_STREAM03           = IOMUX_PAD(0x03BC, 0x015C, 3, 0x04CC, 4, 0),
 	MX8MP_PAD_SAI1_RXD3__ENET1_MDIO                          = IOMUX_PAD(0x03BC, 0x015C, 4, 0x057C, 1, 0),
 	MX8MP_PAD_SAI1_RXD3__GPIO4_IO05                          = IOMUX_PAD(0x03BC, 0x015C, 5, 0x0000, 0, 0),
 
@@ -655,32 +572,26 @@ enum {
 	MX8MP_PAD_SAI1_RXD7__GPIO4_IO09                          = IOMUX_PAD(0x03CC, 0x016C, 5, 0x0000, 0, 0),
 
 	MX8MP_PAD_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC               = IOMUX_PAD(0x03D0, 0x0170, 0, 0x04D8, 4, 0),
-	MX8MP_PAD_SAI1_TXFS__AUDIOMIX_SAI5_TX_SYNC               = IOMUX_PAD(0x03D0, 0x0170, 1, 0x0510, 1, 0),
 	MX8MP_PAD_SAI1_TXFS__ENET1_RGMII_RX_CTL                  = IOMUX_PAD(0x03D0, 0x0170, 4, 0x0588, 1, 0),
 	MX8MP_PAD_SAI1_TXFS__GPIO4_IO10                          = IOMUX_PAD(0x03D0, 0x0170, 5, 0x0000, 0, 0),
 
 	MX8MP_PAD_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK                = IOMUX_PAD(0x03D4, 0x0174, 0, 0x04D4, 1, 0),
-	MX8MP_PAD_SAI1_TXC__AUDIOMIX_SAI5_TX_BCLK                = IOMUX_PAD(0x03D4, 0x0174, 1, 0x050C, 1, 0),
 	MX8MP_PAD_SAI1_TXC__ENET1_RGMII_RXC                      = IOMUX_PAD(0x03D4, 0x0174, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI1_TXC__GPIO4_IO11                           = IOMUX_PAD(0x03D4, 0x0174, 5, 0x0000, 0, 0),
 
 	MX8MP_PAD_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00             = IOMUX_PAD(0x03D8, 0x0178, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD0__AUDIOMIX_SAI5_TX_DATA00             = IOMUX_PAD(0x03D8, 0x0178, 1, 0x0000, 0, 0),
 	MX8MP_PAD_SAI1_TXD0__ENET1_RGMII_TD0                     = IOMUX_PAD(0x03D8, 0x0178, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI1_TXD0__GPIO4_IO12                          = IOMUX_PAD(0x03D8, 0x0178, 5, 0x0000, 0, 0),
 
 	MX8MP_PAD_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01             = IOMUX_PAD(0x03DC, 0x017C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD1__AUDIOMIX_SAI5_TX_DATA01             = IOMUX_PAD(0x03DC, 0x017C, 1, 0x0000, 0, 0),
 	MX8MP_PAD_SAI1_TXD1__ENET1_RGMII_TD1                     = IOMUX_PAD(0x03DC, 0x017C, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI1_TXD1__GPIO4_IO13                          = IOMUX_PAD(0x03DC, 0x017C, 5, 0x0000, 0, 0),
 
 	MX8MP_PAD_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02             = IOMUX_PAD(0x03E0, 0x0180, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD2__AUDIOMIX_SAI5_TX_DATA02             = IOMUX_PAD(0x03E0, 0x0180, 1, 0x0000, 0, 0),
 	MX8MP_PAD_SAI1_TXD2__ENET1_RGMII_TD2                     = IOMUX_PAD(0x03E0, 0x0180, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI1_TXD2__GPIO4_IO14                          = IOMUX_PAD(0x03E0, 0x0180, 5, 0x0000, 0, 0),
 
 	MX8MP_PAD_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03             = IOMUX_PAD(0x03E4, 0x0184, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_TXD3__AUDIOMIX_SAI5_TX_DATA03             = IOMUX_PAD(0x03E4, 0x0184, 1, 0x0000, 0, 0),
 	MX8MP_PAD_SAI1_TXD3__ENET1_RGMII_TD3                     = IOMUX_PAD(0x03E4, 0x0184, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI1_TXD3__GPIO4_IO15                          = IOMUX_PAD(0x03E4, 0x0184, 5, 0x0000, 0, 0),
 
@@ -704,12 +615,11 @@ enum {
 
 	MX8MP_PAD_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07             = IOMUX_PAD(0x03F4, 0x0194, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SAI1_TXD7__AUDIOMIX_SAI6_MCLK                  = IOMUX_PAD(0x03F4, 0x0194, 1, 0x0514, 2, 0),
-	MX8MP_PAD_SAI1_TXD7__AUDIOMIX_CLK                        = IOMUX_PAD(0x03F4, 0x0194, 3, 0x0000, 0, 0),
+	MX8MP_PAD_SAI1_TXD7__AUDIOMIX_PDM_CLK                    = IOMUX_PAD(0x03F4, 0x0194, 3, 0x0000, 0, 0),
 	MX8MP_PAD_SAI1_TXD7__ENET1_TX_ER                         = IOMUX_PAD(0x03F4, 0x0194, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI1_TXD7__GPIO4_IO19                          = IOMUX_PAD(0x03F4, 0x0194, 5, 0x0000, 0, 0),
 
 	MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI1_MCLK                  = IOMUX_PAD(0x03F8, 0x0198, 0, 0x0000, 0, 0),
-	MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI5_MCLK                  = IOMUX_PAD(0x03F8, 0x0198, 1, 0x04F0, 1, 0),
 	MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK               = IOMUX_PAD(0x03F8, 0x0198, 2, 0x04D4, 2, 0),
 	MX8MP_PAD_SAI1_MCLK__ENET1_TX_CLK                        = IOMUX_PAD(0x03F8, 0x0198, 4, 0x0578, 1, 0),
 	MX8MP_PAD_SAI1_MCLK__GPIO4_IO20                          = IOMUX_PAD(0x03F8, 0x0198, 5, 0x0000, 0, 0),
@@ -721,8 +631,7 @@ enum {
 	MX8MP_PAD_SAI2_RXFS__UART1_DCE_TX                        = IOMUX_PAD(0x03FC, 0x019C, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI2_RXFS__UART1_DTE_RX                        = IOMUX_PAD(0x03FC, 0x019C, 4, 0x05E8, 2, 0),
 	MX8MP_PAD_SAI2_RXFS__GPIO4_IO21                          = IOMUX_PAD(0x03FC, 0x019C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_RXFS__AUDIOMIX_BIT_STREAM02               = IOMUX_PAD(0x03FC, 0x019C, 6, 0x04C8, 4, 0),
-	MX8MP_PAD_SAI2_RXFS__SIM_M_HSIZE00                       = IOMUX_PAD(0x03FC, 0x019C, 7, 0x0000, 0, 0),
+	MX8MP_PAD_SAI2_RXFS__AUDIOMIX_PDM_BIT_STREAM02           = IOMUX_PAD(0x03FC, 0x019C, 6, 0x04C8, 5, 0),
 
 	MX8MP_PAD_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK                = IOMUX_PAD(0x0400, 0x01A0, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK                = IOMUX_PAD(0x0400, 0x01A0, 1, 0x050C, 2, 0),
@@ -730,8 +639,7 @@ enum {
 	MX8MP_PAD_SAI2_RXC__UART1_DCE_RX                         = IOMUX_PAD(0x0400, 0x01A0, 4, 0x05E8, 3, 0),
 	MX8MP_PAD_SAI2_RXC__UART1_DTE_TX                         = IOMUX_PAD(0x0400, 0x01A0, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI2_RXC__GPIO4_IO22                           = IOMUX_PAD(0x0400, 0x01A0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_RXC__AUDIOMIX_BIT_STREAM01                = IOMUX_PAD(0x0400, 0x01A0, 6, 0x04C4, 4, 0),
-	MX8MP_PAD_SAI2_RXC__SIM_M_HSIZE01                        = IOMUX_PAD(0x0400, 0x01A0, 7, 0x0000, 0, 0),
+	MX8MP_PAD_SAI2_RXC__AUDIOMIX_PDM_BIT_STREAM01            = IOMUX_PAD(0x0400, 0x01A0, 6, 0x04C4, 5, 0),
 
 	MX8MP_PAD_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00             = IOMUX_PAD(0x0404, 0x01A4, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00             = IOMUX_PAD(0x0404, 0x01A4, 1, 0x0000, 0, 0),
@@ -740,8 +648,7 @@ enum {
 	MX8MP_PAD_SAI2_RXD0__UART1_DCE_RTS                       = IOMUX_PAD(0x0404, 0x01A4, 4, 0x05E4, 2, 0),
 	MX8MP_PAD_SAI2_RXD0__UART1_DTE_CTS                       = IOMUX_PAD(0x0404, 0x01A4, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI2_RXD0__GPIO4_IO23                          = IOMUX_PAD(0x0404, 0x01A4, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_RXD0__AUDIOMIX_BIT_STREAM03               = IOMUX_PAD(0x0404, 0x01A4, 6, 0x04CC, 4, 0),
-	MX8MP_PAD_SAI2_RXD0__SIM_M_HSIZE02                       = IOMUX_PAD(0x0404, 0x01A4, 7, 0x0000, 0, 0),
+	MX8MP_PAD_SAI2_RXD0__AUDIOMIX_PDM_BIT_STREAM03           = IOMUX_PAD(0x0404, 0x01A4, 6, 0x04CC, 5, 0),
 
 	MX8MP_PAD_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC               = IOMUX_PAD(0x0408, 0x01A8, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01             = IOMUX_PAD(0x0408, 0x01A8, 1, 0x0000, 0, 0),
@@ -750,15 +657,13 @@ enum {
 	MX8MP_PAD_SAI2_TXFS__UART1_DCE_CTS                       = IOMUX_PAD(0x0408, 0x01A8, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI2_TXFS__UART1_DTE_RTS                       = IOMUX_PAD(0x0408, 0x01A8, 4, 0x05E4, 3, 0),
 	MX8MP_PAD_SAI2_TXFS__GPIO4_IO24                          = IOMUX_PAD(0x0408, 0x01A8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXFS__AUDIOMIX_BIT_STREAM02               = IOMUX_PAD(0x0408, 0x01A8, 6, 0x04C8, 5, 0),
-	MX8MP_PAD_SAI2_TXFS__SIM_M_HWRITE                        = IOMUX_PAD(0x0408, 0x01A8, 7, 0x0000, 0, 0),
+	MX8MP_PAD_SAI2_TXFS__AUDIOMIX_PDM_BIT_STREAM02           = IOMUX_PAD(0x0408, 0x01A8, 6, 0x04C8, 6, 0),
 
 	MX8MP_PAD_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK                = IOMUX_PAD(0x040C, 0x01AC, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02              = IOMUX_PAD(0x040C, 0x01AC, 1, 0x0000, 0, 0),
 	MX8MP_PAD_SAI2_TXC__CAN1_RX                              = IOMUX_PAD(0x040C, 0x01AC, 3, 0x054C, 1, 0),
 	MX8MP_PAD_SAI2_TXC__GPIO4_IO25                           = IOMUX_PAD(0x040C, 0x01AC, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXC__AUDIOMIX_BIT_STREAM01                = IOMUX_PAD(0x040C, 0x01AC, 6, 0x04C4, 5, 0),
-	MX8MP_PAD_SAI2_TXC__SIM_M_HREADYOUT                      = IOMUX_PAD(0x040C, 0x01AC, 7, 0x0000, 0, 0),
+	MX8MP_PAD_SAI2_TXC__AUDIOMIX_PDM_BIT_STREAM01            = IOMUX_PAD(0x040C, 0x01AC, 6, 0x04C4, 6, 0),
 
 	MX8MP_PAD_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00             = IOMUX_PAD(0x0410, 0x01B0, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03             = IOMUX_PAD(0x0410, 0x01B0, 1, 0x0000, 0, 0),
@@ -766,8 +671,6 @@ enum {
 	MX8MP_PAD_SAI2_TXD0__CAN2_TX                             = IOMUX_PAD(0x0410, 0x01B0, 3, 0x0000, 0, 0),
 	MX8MP_PAD_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN         = IOMUX_PAD(0x0410, 0x01B0, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI2_TXD0__GPIO4_IO26                          = IOMUX_PAD(0x0410, 0x01B0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXD0__CCMSRCGPCMIX_BOOT_MODE04            = IOMUX_PAD(0x0410, 0x01B0, 6, 0x0000, 0, 0),
-	MX8MP_PAD_SAI2_TXD0__TPSMP_CLK                           = IOMUX_PAD(0x0410, 0x01B0, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI2_MCLK                  = IOMUX_PAD(0x0414, 0x01B4, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI5_MCLK                  = IOMUX_PAD(0x0414, 0x01B4, 1, 0x04F0, 2, 0),
@@ -776,16 +679,14 @@ enum {
 	MX8MP_PAD_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN         = IOMUX_PAD(0x0414, 0x01B4, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI2_MCLK__GPIO4_IO27                          = IOMUX_PAD(0x0414, 0x01B4, 5, 0x0000, 0, 0),
 	MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI3_MCLK                  = IOMUX_PAD(0x0414, 0x01B4, 6, 0x04E0, 1, 0),
-	MX8MP_PAD_SAI2_MCLK__TPSMP_HDATA_DIR                     = IOMUX_PAD(0x0414, 0x01B4, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC               = IOMUX_PAD(0x0418, 0x01B8, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01             = IOMUX_PAD(0x0418, 0x01B8, 1, 0x04DC, 1, 0),
 	MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC               = IOMUX_PAD(0x0418, 0x01B8, 2, 0x0508, 2, 0),
 	MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01             = IOMUX_PAD(0x0418, 0x01B8, 3, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SPDIF_IN                   = IOMUX_PAD(0x0418, 0x01B8, 4, 0x0544, 2, 0),
+	MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SPDIF1_IN                  = IOMUX_PAD(0x0418, 0x01B8, 4, 0x0544, 2, 0),
 	MX8MP_PAD_SAI3_RXFS__GPIO4_IO28                          = IOMUX_PAD(0x0418, 0x01B8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_RXFS__AUDIOMIX_BIT_STREAM00               = IOMUX_PAD(0x0418, 0x01B8, 6, 0x04C0, 4, 0),
-	MX8MP_PAD_SAI3_RXFS__TPSMP_HTRANS00                      = IOMUX_PAD(0x0418, 0x01B8, 7, 0x0000, 0, 0),
+	MX8MP_PAD_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00           = IOMUX_PAD(0x0418, 0x01B8, 6, 0x04C0, 5, 0),
 
 	MX8MP_PAD_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK                = IOMUX_PAD(0x041C, 0x01BC, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02              = IOMUX_PAD(0x041C, 0x01BC, 1, 0x0000, 0, 0),
@@ -794,8 +695,7 @@ enum {
 	MX8MP_PAD_SAI3_RXC__UART2_DCE_CTS                        = IOMUX_PAD(0x041C, 0x01BC, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI3_RXC__UART2_DTE_RTS                        = IOMUX_PAD(0x041C, 0x01BC, 4, 0x05EC, 2, 0),
 	MX8MP_PAD_SAI3_RXC__GPIO4_IO29                           = IOMUX_PAD(0x041C, 0x01BC, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_RXC__AUDIOMIX_CLK                         = IOMUX_PAD(0x041C, 0x01BC, 6, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_RXC__TPSMP_HTRANS01                       = IOMUX_PAD(0x041C, 0x01BC, 7, 0x0000, 0, 0),
+	MX8MP_PAD_SAI3_RXC__AUDIOMIX_PDM_CLK                     = IOMUX_PAD(0x041C, 0x01BC, 6, 0x0000, 0, 0),
 
 	MX8MP_PAD_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00              = IOMUX_PAD(0x0420, 0x01C0, 0, 0x04E4, 1, 0),
 	MX8MP_PAD_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03              = IOMUX_PAD(0x0420, 0x01C0, 1, 0x0000, 0, 0),
@@ -803,8 +703,7 @@ enum {
 	MX8MP_PAD_SAI3_RXD__UART2_DCE_RTS                        = IOMUX_PAD(0x0420, 0x01C0, 4, 0x05EC, 3, 0),
 	MX8MP_PAD_SAI3_RXD__UART2_DTE_CTS                        = IOMUX_PAD(0x0420, 0x01C0, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI3_RXD__GPIO4_IO30                           = IOMUX_PAD(0x0420, 0x01C0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_RXD__AUDIOMIX_BIT_STREAM01                = IOMUX_PAD(0x0420, 0x01C0, 6, 0x04C4, 6, 0),
-	MX8MP_PAD_SAI3_RXD__TPSMP_HDATA00                        = IOMUX_PAD(0x0420, 0x01C0, 7, 0x0000, 0, 0),
+	MX8MP_PAD_SAI3_RXD__AUDIOMIX_PDM_BIT_STREAM01            = IOMUX_PAD(0x0420, 0x01C0, 6, 0x04C4, 7, 0),
 
 	MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC               = IOMUX_PAD(0x0424, 0x01C4, 0, 0x04EC, 1, 0),
 	MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01             = IOMUX_PAD(0x0424, 0x01C4, 1, 0x0000, 0, 0),
@@ -813,8 +712,7 @@ enum {
 	MX8MP_PAD_SAI3_TXFS__UART2_DCE_RX                        = IOMUX_PAD(0x0424, 0x01C4, 4, 0x05F0, 4, 0),
 	MX8MP_PAD_SAI3_TXFS__UART2_DTE_TX                        = IOMUX_PAD(0x0424, 0x01C4, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI3_TXFS__GPIO4_IO31                          = IOMUX_PAD(0x0424, 0x01C4, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_TXFS__AUDIOMIX_BIT_STREAM03               = IOMUX_PAD(0x0424, 0x01C4, 6, 0x04CC, 5, 0),
-	MX8MP_PAD_SAI3_TXFS__TPSMP_HDATA01                       = IOMUX_PAD(0x0424, 0x01C4, 7, 0x0000, 0, 0),
+	MX8MP_PAD_SAI3_TXFS__AUDIOMIX_PDM_BIT_STREAM03           = IOMUX_PAD(0x0424, 0x01C4, 6, 0x04CC, 6, 0),
 
 	MX8MP_PAD_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK                = IOMUX_PAD(0x0428, 0x01C8, 0, 0x04E8, 1, 0),
 	MX8MP_PAD_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02              = IOMUX_PAD(0x0428, 0x01C8, 1, 0x0000, 0, 0),
@@ -823,34 +721,30 @@ enum {
 	MX8MP_PAD_SAI3_TXC__UART2_DCE_TX                         = IOMUX_PAD(0x0428, 0x01C8, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI3_TXC__UART2_DTE_RX                         = IOMUX_PAD(0x0428, 0x01C8, 4, 0x05F0, 5, 0),
 	MX8MP_PAD_SAI3_TXC__GPIO5_IO00                           = IOMUX_PAD(0x0428, 0x01C8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_TXC__AUDIOMIX_BIT_STREAM02                = IOMUX_PAD(0x0428, 0x01C8, 6, 0x04C8, 6, 0),
-	MX8MP_PAD_SAI3_TXC__TPSMP_HDATA02                        = IOMUX_PAD(0x0428, 0x01C8, 7, 0x0000, 0, 0),
+	MX8MP_PAD_SAI3_TXC__AUDIOMIX_PDM_BIT_STREAM02            = IOMUX_PAD(0x0428, 0x01C8, 6, 0x04C8, 7, 0),
 
 	MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00              = IOMUX_PAD(0x042C, 0x01CC, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03              = IOMUX_PAD(0x042C, 0x01CC, 1, 0x0000, 0, 0),
 	MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03              = IOMUX_PAD(0x042C, 0x01CC, 2, 0x0504, 2, 0),
 	MX8MP_PAD_SAI3_TXD__GPT1_CAPTURE2                        = IOMUX_PAD(0x042C, 0x01CC, 3, 0x0598, 0, 0),
-	MX8MP_PAD_SAI3_TXD__AUDIOMIX_SPDIF_EXT_CLK               = IOMUX_PAD(0x042C, 0x01CC, 4, 0x0548, 0, 0),
+	MX8MP_PAD_SAI3_TXD__AUDIOMIX_SPDIF1_EXT_CLK              = IOMUX_PAD(0x042C, 0x01CC, 4, 0x0548, 0, 0),
 	MX8MP_PAD_SAI3_TXD__GPIO5_IO01                           = IOMUX_PAD(0x042C, 0x01CC, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_TXD__CCMSRCGPCMIX_BOOT_MODE05             = IOMUX_PAD(0x042C, 0x01CC, 6, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_TXD__TPSMP_HDATA03                        = IOMUX_PAD(0x042C, 0x01CC, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SAI3_MCLK                  = IOMUX_PAD(0x0430, 0x01D0, 0, 0x04E0, 2, 0),
 	MX8MP_PAD_SAI3_MCLK__PWM4_OUT                            = IOMUX_PAD(0x0430, 0x01D0, 1, 0x0000, 0, 0),
 	MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SAI5_MCLK                  = IOMUX_PAD(0x0430, 0x01D0, 2, 0x04F0, 3, 0),
-	MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SPDIF_OUT                  = IOMUX_PAD(0x0430, 0x01D0, 4, 0x0000, 0, 0),
+	MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SPDIF1_OUT                 = IOMUX_PAD(0x0430, 0x01D0, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SAI3_MCLK__GPIO5_IO02                          = IOMUX_PAD(0x0430, 0x01D0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SPDIF_IN                   = IOMUX_PAD(0x0430, 0x01D0, 6, 0x0544, 3, 0),
-	MX8MP_PAD_SAI3_MCLK__TPSMP_HDATA04                       = IOMUX_PAD(0x0430, 0x01D0, 7, 0x0000, 0, 0),
+	MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SPDIF1_IN                  = IOMUX_PAD(0x0430, 0x01D0, 6, 0x0544, 3, 0),
 
-	MX8MP_PAD_SPDIF_TX__AUDIOMIX_SPDIF_OUT                   = IOMUX_PAD(0x0434, 0x01D4, 0, 0x0000, 0, 0),
+	MX8MP_PAD_SPDIF_TX__AUDIOMIX_SPDIF1_OUT                  = IOMUX_PAD(0x0434, 0x01D4, 0, 0x0000, 0, 0),
 	MX8MP_PAD_SPDIF_TX__PWM3_OUT                             = IOMUX_PAD(0x0434, 0x01D4, 1, 0x0000, 0, 0),
 	MX8MP_PAD_SPDIF_TX__I2C5_SCL                             = IOMUX_PAD(0x0434, 0x01D4, 2 | IOMUX_CONFIG_SION, 0x05C4, 2, 0),
 	MX8MP_PAD_SPDIF_TX__GPT1_COMPARE1                        = IOMUX_PAD(0x0434, 0x01D4, 3, 0x0000, 0, 0),
 	MX8MP_PAD_SPDIF_TX__CAN1_TX                              = IOMUX_PAD(0x0434, 0x01D4, 4, 0x0000, 0, 0),
 	MX8MP_PAD_SPDIF_TX__GPIO5_IO03                           = IOMUX_PAD(0x0434, 0x01D4, 5, 0x0000, 0, 0),
 
-	MX8MP_PAD_SPDIF_RX__AUDIOMIX_SPDIF_IN                    = IOMUX_PAD(0x0438, 0x01D8, 0, 0x0544, 4, 0),
+	MX8MP_PAD_SPDIF_RX__AUDIOMIX_SPDIF1_IN                   = IOMUX_PAD(0x0438, 0x01D8, 0, 0x0544, 4, 0),
 	MX8MP_PAD_SPDIF_RX__PWM2_OUT                             = IOMUX_PAD(0x0438, 0x01D8, 1, 0x0000, 0, 0),
 	MX8MP_PAD_SPDIF_RX__I2C5_SDA                             = IOMUX_PAD(0x0438, 0x01D8, 2 | IOMUX_CONFIG_SION, 0x05C8, 2, 0),
 	MX8MP_PAD_SPDIF_RX__GPT1_COMPARE2                        = IOMUX_PAD(0x0438, 0x01D8, 3, 0x0000, 0, 0),
@@ -859,7 +753,7 @@ enum {
 	MX8MP_PAD_SPDIF_EXT_CLK__GPT1_COMPARE3                   = IOMUX_PAD(0x043C, 0x01DC, 3, 0x0000, 0, 0),
 	MX8MP_PAD_SPDIF_EXT_CLK__GPIO5_IO05                      = IOMUX_PAD(0x043C, 0x01DC, 5, 0x0000, 0, 0),
 
-	MX8MP_PAD_SPDIF_EXT_CLK__AUDIOMIX_SPDIF_EXT_CLK          = IOMUX_PAD(0x043C, 0x01DC, 0, 0x0548, 1, 0),
+	MX8MP_PAD_SPDIF_EXT_CLK__AUDIOMIX_SPDIF1_EXT_CLK         = IOMUX_PAD(0x043C, 0x01DC, 0, 0x0548, 1, 0),
 	MX8MP_PAD_SPDIF_EXT_CLK__PWM1_OUT                        = IOMUX_PAD(0x043C, 0x01DC, 1, 0x0000, 0, 0),
 
 	MX8MP_PAD_ECSPI1_SCLK__ECSPI1_SCLK                       = IOMUX_PAD(0x0440, 0x01E0, 0, 0x0558, 0, 0),
@@ -868,7 +762,6 @@ enum {
 	MX8MP_PAD_ECSPI1_SCLK__I2C1_SCL                          = IOMUX_PAD(0x0440, 0x01E0, 2 | IOMUX_CONFIG_SION, 0x05A4, 1, 0),
 	MX8MP_PAD_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC             = IOMUX_PAD(0x0440, 0x01E0, 3, 0x0538, 1, 0),
 	MX8MP_PAD_ECSPI1_SCLK__GPIO5_IO06                        = IOMUX_PAD(0x0440, 0x01E0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI1_SCLK__TPSMP_HDATA08                     = IOMUX_PAD(0x0440, 0x01E0, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_ECSPI1_MOSI__ECSPI1_MOSI                       = IOMUX_PAD(0x0444, 0x01E4, 0, 0x0560, 0, 0),
 	MX8MP_PAD_ECSPI1_MOSI__UART3_DCE_TX                      = IOMUX_PAD(0x0444, 0x01E4, 1, 0x0000, 0, 0),
@@ -876,7 +769,6 @@ enum {
 	MX8MP_PAD_ECSPI1_MOSI__I2C1_SDA                          = IOMUX_PAD(0x0444, 0x01E4, 2 | IOMUX_CONFIG_SION, 0x05A8, 1, 0),
 	MX8MP_PAD_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK             = IOMUX_PAD(0x0444, 0x01E4, 3, 0x0530, 1, 0),
 	MX8MP_PAD_ECSPI1_MOSI__GPIO5_IO07                        = IOMUX_PAD(0x0444, 0x01E4, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI1_MOSI__TPSMP_HDATA09                     = IOMUX_PAD(0x0444, 0x01E4, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_ECSPI1_MISO__ECSPI1_MISO                       = IOMUX_PAD(0x0448, 0x01E8, 0, 0x055C, 0, 0),
 	MX8MP_PAD_ECSPI1_MISO__UART3_DCE_CTS                     = IOMUX_PAD(0x0448, 0x01E8, 1, 0x0000, 0, 0),
@@ -884,7 +776,6 @@ enum {
 	MX8MP_PAD_ECSPI1_MISO__I2C2_SCL                          = IOMUX_PAD(0x0448, 0x01E8, 2 | IOMUX_CONFIG_SION, 0x05AC, 1, 0),
 	MX8MP_PAD_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00           = IOMUX_PAD(0x0448, 0x01E8, 3, 0x0534, 1, 0),
 	MX8MP_PAD_ECSPI1_MISO__GPIO5_IO08                        = IOMUX_PAD(0x0448, 0x01E8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI1_MISO__TPSMP_HDATA10                     = IOMUX_PAD(0x0448, 0x01E8, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_ECSPI1_SS0__ECSPI1_SS0                         = IOMUX_PAD(0x044C, 0x01EC, 0, 0x0564, 0, 0),
 	MX8MP_PAD_ECSPI1_SS0__UART3_DCE_RTS                      = IOMUX_PAD(0x044C, 0x01EC, 1, 0x05F4, 3, 0),
@@ -892,7 +783,6 @@ enum {
 	MX8MP_PAD_ECSPI1_SS0__I2C2_SDA                           = IOMUX_PAD(0x044C, 0x01EC, 2 | IOMUX_CONFIG_SION, 0x05B0, 1, 0),
 	MX8MP_PAD_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC              = IOMUX_PAD(0x044C, 0x01EC, 3, 0x0540, 1, 0),
 	MX8MP_PAD_ECSPI1_SS0__GPIO5_IO09                         = IOMUX_PAD(0x044C, 0x01EC, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI1_SS0__TPSMP_HDATA11                      = IOMUX_PAD(0x044C, 0x01EC, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_ECSPI2_SCLK__ECSPI2_SCLK                       = IOMUX_PAD(0x0450, 0x01F0, 0, 0x0568, 1, 0),
 	MX8MP_PAD_ECSPI2_SCLK__UART4_DCE_RX                      = IOMUX_PAD(0x0450, 0x01F0, 1, 0x0600, 6, 0),
@@ -900,7 +790,6 @@ enum {
 	MX8MP_PAD_ECSPI2_SCLK__I2C3_SCL                          = IOMUX_PAD(0x0450, 0x01F0, 2 | IOMUX_CONFIG_SION, 0x05B4, 3, 0),
 	MX8MP_PAD_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK             = IOMUX_PAD(0x0450, 0x01F0, 3, 0x053C, 1, 0),
 	MX8MP_PAD_ECSPI2_SCLK__GPIO5_IO10                        = IOMUX_PAD(0x0450, 0x01F0, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI2_SCLK__TPSMP_HDATA12                     = IOMUX_PAD(0x0450, 0x01F0, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_ECSPI2_MOSI__ECSPI2_MOSI                       = IOMUX_PAD(0x0454, 0x01F4, 0, 0x0570, 1, 0),
 	MX8MP_PAD_ECSPI2_MOSI__UART4_DCE_TX                      = IOMUX_PAD(0x0454, 0x01F4, 1, 0x0000, 0, 0),
@@ -908,36 +797,31 @@ enum {
 	MX8MP_PAD_ECSPI2_MOSI__I2C3_SDA                          = IOMUX_PAD(0x0454, 0x01F4, 2 | IOMUX_CONFIG_SION, 0x05B8, 3, 0),
 	MX8MP_PAD_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00           = IOMUX_PAD(0x0454, 0x01F4, 3, 0x0000, 0, 0),
 	MX8MP_PAD_ECSPI2_MOSI__GPIO5_IO11                        = IOMUX_PAD(0x0454, 0x01F4, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI2_MOSI__TPSMP_HDATA13                     = IOMUX_PAD(0x0454, 0x01F4, 7, 0x0000, 0, 0),
 	MX8MP_PAD_ECSPI2_MISO__GPIO5_IO12                        = IOMUX_PAD(0x0458, 0x01F8, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI2_MISO__TPSMP_HDATA14                     = IOMUX_PAD(0x0458, 0x01F8, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_ECSPI2_MISO__ECSPI2_MISO                       = IOMUX_PAD(0x0458, 0x01F8, 0, 0x056C, 1, 0),
 	MX8MP_PAD_ECSPI2_MISO__UART4_DCE_CTS                     = IOMUX_PAD(0x0458, 0x01F8, 1, 0x0000, 0, 0),
 	MX8MP_PAD_ECSPI2_MISO__UART4_DTE_RTS                     = IOMUX_PAD(0x0458, 0x01F8, 1, 0x05FC, 2, 0),
 	MX8MP_PAD_ECSPI2_MISO__I2C4_SCL                          = IOMUX_PAD(0x0458, 0x01F8, 2 | IOMUX_CONFIG_SION, 0x05BC, 4, 0),
 	MX8MP_PAD_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK                = IOMUX_PAD(0x0458, 0x01F8, 3, 0x052C, 1, 0),
-	MX8MP_PAD_ECSPI2_MISO__CCMSRCGPCMIX_CLKO1                = IOMUX_PAD(0x0458, 0x01F8, 4, 0x0000, 0, 0),
+	MX8MP_PAD_ECSPI2_MISO__CCM_CLKO1                         = IOMUX_PAD(0x0458, 0x01F8, 4, 0x0000, 0, 0),
 
 	MX8MP_PAD_ECSPI2_SS0__ECSPI2_SS0                         = IOMUX_PAD(0x045C, 0x01FC, 0, 0x0574, 1, 0),
 	MX8MP_PAD_ECSPI2_SS0__UART4_DCE_RTS                      = IOMUX_PAD(0x045C, 0x01FC, 1, 0x05FC, 3, 0),
 	MX8MP_PAD_ECSPI2_SS0__UART4_DTE_CTS                      = IOMUX_PAD(0x045C, 0x01FC, 1, 0x0000, 0, 0),
 	MX8MP_PAD_ECSPI2_SS0__I2C4_SDA                           = IOMUX_PAD(0x045C, 0x01FC, 2 | IOMUX_CONFIG_SION, 0x05C0, 4, 0),
-	MX8MP_PAD_ECSPI2_SS0__CCMSRCGPCMIX_CLKO2                 = IOMUX_PAD(0x045C, 0x01FC, 4, 0x0000, 0, 0),
+	MX8MP_PAD_ECSPI2_SS0__CCM_CLKO2                          = IOMUX_PAD(0x045C, 0x01FC, 4, 0x0000, 0, 0),
 	MX8MP_PAD_ECSPI2_SS0__GPIO5_IO13                         = IOMUX_PAD(0x045C, 0x01FC, 5, 0x0000, 0, 0),
-	MX8MP_PAD_ECSPI2_SS0__TPSMP_HDATA15                      = IOMUX_PAD(0x045C, 0x01FC, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_I2C1_SCL__I2C1_SCL                             = IOMUX_PAD(0x0460, 0x0200, 0 | IOMUX_CONFIG_SION, 0x05A4, 2, 0),
 	MX8MP_PAD_I2C1_SCL__ENET_QOS_MDC                         = IOMUX_PAD(0x0460, 0x0200, 1, 0x0000, 0, 0),
 	MX8MP_PAD_I2C1_SCL__ECSPI1_SCLK                          = IOMUX_PAD(0x0460, 0x0200, 3, 0x0558, 1, 0),
 	MX8MP_PAD_I2C1_SCL__GPIO5_IO14                           = IOMUX_PAD(0x0460, 0x0200, 5, 0x0000, 0, 0),
-	MX8MP_PAD_I2C1_SCL__TPSMP_HDATA16                        = IOMUX_PAD(0x0460, 0x0200, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_I2C1_SDA__I2C1_SDA                             = IOMUX_PAD(0x0464, 0x0204, 0 | IOMUX_CONFIG_SION, 0x05A8, 2, 0),
 	MX8MP_PAD_I2C1_SDA__ENET_QOS_MDIO                        = IOMUX_PAD(0x0464, 0x0204, 1, 0x0590, 2, 0),
 	MX8MP_PAD_I2C1_SDA__ECSPI1_MOSI                          = IOMUX_PAD(0x0464, 0x0204, 3, 0x0560, 1, 0),
 	MX8MP_PAD_I2C1_SDA__GPIO5_IO15                           = IOMUX_PAD(0x0464, 0x0204, 5, 0x0000, 0, 0),
-	MX8MP_PAD_I2C1_SDA__TPSMP_HDATA17                        = IOMUX_PAD(0x0464, 0x0204, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_I2C2_SCL__I2C2_SCL                             = IOMUX_PAD(0x0468, 0x0208, 0 | IOMUX_CONFIG_SION, 0x05AC, 2, 0),
 	MX8MP_PAD_I2C2_SCL__ENET_QOS_1588_EVENT1_IN              = IOMUX_PAD(0x0468, 0x0208, 1, 0x0000, 0, 0),
@@ -945,55 +829,47 @@ enum {
 	MX8MP_PAD_I2C2_SCL__ECSPI1_MISO                          = IOMUX_PAD(0x0468, 0x0208, 3, 0x055C, 1, 0),
 	MX8MP_PAD_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN          = IOMUX_PAD(0x0468, 0x0208, 4, 0x0000, 0, 0),
 	MX8MP_PAD_I2C2_SCL__GPIO5_IO16                           = IOMUX_PAD(0x0468, 0x0208, 5, 0x0000, 0, 0),
-	MX8MP_PAD_I2C2_SCL__TPSMP_HDATA18                        = IOMUX_PAD(0x0468, 0x0208, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_I2C2_SDA__I2C2_SDA                             = IOMUX_PAD(0x046C, 0x020C, 0 | IOMUX_CONFIG_SION, 0x05B0, 2, 0),
 	MX8MP_PAD_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT             = IOMUX_PAD(0x046C, 0x020C, 1, 0x0000, 0, 0),
 	MX8MP_PAD_I2C2_SDA__USDHC3_WP                            = IOMUX_PAD(0x046C, 0x020C, 2, 0x0634, 3, 0),
 	MX8MP_PAD_I2C2_SDA__ECSPI1_SS0                           = IOMUX_PAD(0x046C, 0x020C, 3, 0x0564, 1, 0),
 	MX8MP_PAD_I2C2_SDA__GPIO5_IO17                           = IOMUX_PAD(0x046C, 0x020C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_I2C2_SDA__TPSMP_HDATA19                        = IOMUX_PAD(0x046C, 0x020C, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_I2C3_SCL__I2C3_SCL                             = IOMUX_PAD(0x0470, 0x0210, 0 | IOMUX_CONFIG_SION, 0x05B4, 4, 0),
 	MX8MP_PAD_I2C3_SCL__PWM4_OUT                             = IOMUX_PAD(0x0470, 0x0210, 1, 0x0000, 0, 0),
 	MX8MP_PAD_I2C3_SCL__GPT2_CLK                             = IOMUX_PAD(0x0470, 0x0210, 2, 0x0000, 0, 0),
 	MX8MP_PAD_I2C3_SCL__ECSPI2_SCLK                          = IOMUX_PAD(0x0470, 0x0210, 3, 0x0568, 2, 0),
 	MX8MP_PAD_I2C3_SCL__GPIO5_IO18                           = IOMUX_PAD(0x0470, 0x0210, 5, 0x0000, 0, 0),
-	MX8MP_PAD_I2C3_SCL__TPSMP_HDATA20                        = IOMUX_PAD(0x0470, 0x0210, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_I2C3_SDA__I2C3_SDA                             = IOMUX_PAD(0x0474, 0x0214, 0 | IOMUX_CONFIG_SION, 0x05B8, 4, 0),
 	MX8MP_PAD_I2C3_SDA__PWM3_OUT                             = IOMUX_PAD(0x0474, 0x0214, 1, 0x0000, 0, 0),
 	MX8MP_PAD_I2C3_SDA__GPT3_CLK                             = IOMUX_PAD(0x0474, 0x0214, 2, 0x0000, 0, 0),
 	MX8MP_PAD_I2C3_SDA__ECSPI2_MOSI                          = IOMUX_PAD(0x0474, 0x0214, 3, 0x0570, 2, 0),
 	MX8MP_PAD_I2C3_SDA__GPIO5_IO19                           = IOMUX_PAD(0x0474, 0x0214, 5, 0x0000, 0, 0),
-	MX8MP_PAD_I2C3_SDA__TPSMP_HDATA21                        = IOMUX_PAD(0x0474, 0x0214, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_I2C4_SCL__I2C4_SCL                             = IOMUX_PAD(0x0478, 0x0218, 0 | IOMUX_CONFIG_SION, 0x05BC, 5, 0),
 	MX8MP_PAD_I2C4_SCL__PWM2_OUT                             = IOMUX_PAD(0x0478, 0x0218, 1, 0x0000, 0, 0),
-	MX8MP_PAD_I2C4_SCL__HSIOMIX_PCIE_CLKREQ_B                = IOMUX_PAD(0x0478, 0x0218, 2, 0x05A0, 0, 0),
+	MX8MP_PAD_I2C4_SCL__PCIE_CLKREQ_B                        = IOMUX_PAD(0x0478, 0x0218, 2, 0x05A0, 0, 0),
 	MX8MP_PAD_I2C4_SCL__ECSPI2_MISO                          = IOMUX_PAD(0x0478, 0x0218, 3, 0x056C, 2, 0),
 	MX8MP_PAD_I2C4_SCL__GPIO5_IO20                           = IOMUX_PAD(0x0478, 0x0218, 5, 0x0000, 0, 0),
-	MX8MP_PAD_I2C4_SCL__TPSMP_HDATA22                        = IOMUX_PAD(0x0478, 0x0218, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_I2C4_SDA__I2C4_SDA                             = IOMUX_PAD(0x047C, 0x021C, 0 | IOMUX_CONFIG_SION, 0x05C0, 5, 0),
 	MX8MP_PAD_I2C4_SDA__PWM1_OUT                             = IOMUX_PAD(0x047C, 0x021C, 1, 0x0000, 0, 0),
 	MX8MP_PAD_I2C4_SDA__ECSPI2_SS0                           = IOMUX_PAD(0x047C, 0x021C, 3, 0x0574, 2, 0),
 	MX8MP_PAD_I2C4_SDA__GPIO5_IO21                           = IOMUX_PAD(0x047C, 0x021C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_I2C4_SDA__TPSMP_HDATA23                        = IOMUX_PAD(0x047C, 0x021C, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_UART1_RXD__UART1_DCE_RX                        = IOMUX_PAD(0x0480, 0x0220, 0, 0x05E8, 4, 0),
 
 	MX8MP_PAD_UART1_RXD__UART1_DTE_TX                        = IOMUX_PAD(0x0480, 0x0220, 0, 0x0000, 0, 0),
 	MX8MP_PAD_UART1_RXD__ECSPI3_SCLK                         = IOMUX_PAD(0x0480, 0x0220, 1, 0x0000, 0, 0),
 	MX8MP_PAD_UART1_RXD__GPIO5_IO22                          = IOMUX_PAD(0x0480, 0x0220, 5, 0x0000, 0, 0),
-	MX8MP_PAD_UART1_RXD__TPSMP_HDATA24                       = IOMUX_PAD(0x0480, 0x0220, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_UART1_TXD__UART1_DCE_TX                        = IOMUX_PAD(0x0484, 0x0224, 0, 0x0000, 0, 0),
 
 	MX8MP_PAD_UART1_TXD__UART1_DTE_RX                        = IOMUX_PAD(0x0484, 0x0224, 0, 0x05E8, 5, 0),
 	MX8MP_PAD_UART1_TXD__ECSPI3_MOSI                         = IOMUX_PAD(0x0484, 0x0224, 1, 0x0000, 0, 0),
 	MX8MP_PAD_UART1_TXD__GPIO5_IO23                          = IOMUX_PAD(0x0484, 0x0224, 5, 0x0000, 0, 0),
-	MX8MP_PAD_UART1_TXD__TPSMP_HDATA25                       = IOMUX_PAD(0x0484, 0x0224, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_UART2_RXD__UART2_DCE_RX                        = IOMUX_PAD(0x0488, 0x0228, 0, 0x05F0, 6, 0),
 
@@ -1001,7 +877,6 @@ enum {
 	MX8MP_PAD_UART2_RXD__ECSPI3_MISO                         = IOMUX_PAD(0x0488, 0x0228, 1, 0x0000, 0, 0),
 	MX8MP_PAD_UART2_RXD__GPT1_COMPARE3                       = IOMUX_PAD(0x0488, 0x0228, 3, 0x0000, 0, 0),
 	MX8MP_PAD_UART2_RXD__GPIO5_IO24                          = IOMUX_PAD(0x0488, 0x0228, 5, 0x0000, 0, 0),
-	MX8MP_PAD_UART2_RXD__TPSMP_HDATA26                       = IOMUX_PAD(0x0488, 0x0228, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_UART2_TXD__UART2_DCE_TX                        = IOMUX_PAD(0x048C, 0x022C, 0, 0x0000, 0, 0),
 
@@ -1009,7 +884,6 @@ enum {
 	MX8MP_PAD_UART2_TXD__ECSPI3_SS0                          = IOMUX_PAD(0x048C, 0x022C, 1, 0x0000, 0, 0),
 	MX8MP_PAD_UART2_TXD__GPT1_COMPARE2                       = IOMUX_PAD(0x048C, 0x022C, 3, 0x0000, 0, 0),
 	MX8MP_PAD_UART2_TXD__GPIO5_IO25                          = IOMUX_PAD(0x048C, 0x022C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_UART2_TXD__TPSMP_HDATA27                       = IOMUX_PAD(0x048C, 0x022C, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_UART3_RXD__UART3_DCE_RX                        = IOMUX_PAD(0x0490, 0x0230, 0, 0x05F8, 6, 0),
 
@@ -1020,7 +894,6 @@ enum {
 	MX8MP_PAD_UART3_RXD__GPT1_CAPTURE2                       = IOMUX_PAD(0x0490, 0x0230, 3, 0x0598, 1, 0),
 	MX8MP_PAD_UART3_RXD__CAN2_TX                             = IOMUX_PAD(0x0490, 0x0230, 4, 0x0000, 0, 0),
 	MX8MP_PAD_UART3_RXD__GPIO5_IO26                          = IOMUX_PAD(0x0490, 0x0230, 5, 0x0000, 0, 0),
-	MX8MP_PAD_UART3_RXD__TPSMP_HDATA28                       = IOMUX_PAD(0x0490, 0x0230, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_UART3_TXD__UART3_DCE_TX                        = IOMUX_PAD(0x0494, 0x0234, 0, 0x0000, 0, 0),
 
@@ -1031,18 +904,16 @@ enum {
 	MX8MP_PAD_UART3_TXD__GPT1_CLK                            = IOMUX_PAD(0x0494, 0x0234, 3, 0x059C, 1, 0),
 	MX8MP_PAD_UART3_TXD__CAN2_RX                             = IOMUX_PAD(0x0494, 0x0234, 4, 0x0550, 2, 0),
 	MX8MP_PAD_UART3_TXD__GPIO5_IO27                          = IOMUX_PAD(0x0494, 0x0234, 5, 0x0000, 0, 0),
-	MX8MP_PAD_UART3_TXD__TPSMP_HDATA29                       = IOMUX_PAD(0x0494, 0x0234, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_UART4_RXD__UART4_DCE_RX                        = IOMUX_PAD(0x0498, 0x0238, 0, 0x0600, 8, 0),
 
 	MX8MP_PAD_UART4_RXD__UART4_DTE_TX                        = IOMUX_PAD(0x0498, 0x0238, 0, 0x0000, 0, 0),
 	MX8MP_PAD_UART4_RXD__UART2_DCE_CTS                       = IOMUX_PAD(0x0498, 0x0238, 1, 0x0000, 0, 0),
 	MX8MP_PAD_UART4_RXD__UART2_DTE_RTS                       = IOMUX_PAD(0x0498, 0x0238, 1, 0x05EC, 4, 0),
-	MX8MP_PAD_UART4_RXD__HSIOMIX_PCIE_CLKREQ_B               = IOMUX_PAD(0x0498, 0x0238, 2, 0x05A0, 1, 0),
+	MX8MP_PAD_UART4_RXD__PCIE_CLKREQ_B                       = IOMUX_PAD(0x0498, 0x0238, 2, 0x05A0, 1, 0),
 	MX8MP_PAD_UART4_RXD__GPT1_COMPARE1                       = IOMUX_PAD(0x0498, 0x0238, 3, 0x0000, 0, 0),
 	MX8MP_PAD_UART4_RXD__I2C6_SCL                            = IOMUX_PAD(0x0498, 0x0238, 4 | IOMUX_CONFIG_SION, 0x05CC, 2, 0),
 	MX8MP_PAD_UART4_RXD__GPIO5_IO28                          = IOMUX_PAD(0x0498, 0x0238, 5, 0x0000, 0, 0),
-	MX8MP_PAD_UART4_RXD__TPSMP_HDATA30                       = IOMUX_PAD(0x0498, 0x0238, 7, 0x0000, 0, 0),
 
 	MX8MP_PAD_UART4_TXD__UART4_DCE_TX                        = IOMUX_PAD(0x049C, 0x023C, 0, 0x0000, 0, 0),
 
@@ -1052,27 +923,24 @@ enum {
 	MX8MP_PAD_UART4_TXD__GPT1_CAPTURE1                       = IOMUX_PAD(0x049C, 0x023C, 3, 0x0594, 1, 0),
 	MX8MP_PAD_UART4_TXD__I2C6_SDA                            = IOMUX_PAD(0x049C, 0x023C, 4 | IOMUX_CONFIG_SION, 0x05D0, 2, 0),
 	MX8MP_PAD_UART4_TXD__GPIO5_IO29                          = IOMUX_PAD(0x049C, 0x023C, 5, 0x0000, 0, 0),
-	MX8MP_PAD_UART4_TXD__TPSMP_HDATA31                       = IOMUX_PAD(0x049C, 0x023C, 7, 0x0000, 0, 0),
 
-	MX8MP_PAD_HDMI_DDC_SCL__HDMIMIX_EARC_SCL                 = IOMUX_PAD(0x04A0, 0x0240, 0, 0x0000, 0, 0),
+	MX8MP_PAD_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL                 = IOMUX_PAD(0x04A0, 0x0240, 0, 0x0000, 0, 0),
 	MX8MP_PAD_HDMI_DDC_SCL__I2C5_SCL                         = IOMUX_PAD(0x04A0, 0x0240, 3 | IOMUX_CONFIG_SION, 0x05C4, 3, 0),
 	MX8MP_PAD_HDMI_DDC_SCL__CAN1_TX                          = IOMUX_PAD(0x04A0, 0x0240, 4, 0x0000, 0, 0),
 	MX8MP_PAD_HDMI_DDC_SCL__GPIO3_IO26                       = IOMUX_PAD(0x04A0, 0x0240, 5, 0x0000, 0, 0),
-	MX8MP_PAD_HDMI_DDC_SCL__AUDIOMIX_test_out00              = IOMUX_PAD(0x04A0, 0x0240, 6, 0x0000, 0, 0),
 
-	MX8MP_PAD_HDMI_DDC_SDA__HDMIMIX_EARC_SDA                 = IOMUX_PAD(0x04A4, 0x0244, 0, 0x0000, 0, 0),
+	MX8MP_PAD_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA                 = IOMUX_PAD(0x04A4, 0x0244, 0, 0x0000, 0, 0),
 	MX8MP_PAD_HDMI_DDC_SDA__I2C5_SDA                         = IOMUX_PAD(0x04A4, 0x0244, 3 | IOMUX_CONFIG_SION, 0x05C8, 3, 0),
 	MX8MP_PAD_HDMI_DDC_SDA__CAN1_RX                          = IOMUX_PAD(0x04A4, 0x0244, 4, 0x054C, 3, 0),
 	MX8MP_PAD_HDMI_DDC_SDA__GPIO3_IO27                       = IOMUX_PAD(0x04A4, 0x0244, 5, 0x0000, 0, 0),
-	MX8MP_PAD_HDMI_DDC_SDA__AUDIOMIX_test_out01              = IOMUX_PAD(0x04A4, 0x0244, 6, 0x0000, 0, 0),
 
-	MX8MP_PAD_HDMI_CEC__HDMIMIX_EARC_CEC                     = IOMUX_PAD(0x04A8, 0x0248, 0, 0x0000, 0, 0),
+	MX8MP_PAD_HDMI_CEC__HDMIMIX_HDMI_CEC                     = IOMUX_PAD(0x04A8, 0x0248, 0, 0x0000, 0, 0),
 	MX8MP_PAD_HDMI_CEC__I2C6_SCL                             = IOMUX_PAD(0x04A8, 0x0248, 3 | IOMUX_CONFIG_SION, 0x05CC, 3, 0),
 	MX8MP_PAD_HDMI_CEC__CAN2_TX                              = IOMUX_PAD(0x04A8, 0x0248, 4, 0x0000, 0, 0),
 	MX8MP_PAD_HDMI_CEC__GPIO3_IO28                           = IOMUX_PAD(0x04A8, 0x0248, 5, 0x0000, 0, 0),
 
-	MX8MP_PAD_HDMI_HPD__HDMIMIX_EARC_DC_HPD                  = IOMUX_PAD(0x04AC, 0x024C, 0, 0x0000, 0, 0),
-	MX8MP_PAD_HDMI_HPD__AUDIOMIX_EARC_HDMI_HPD_O             = IOMUX_PAD(0x04AC, 0x024C, 1, 0x0000, 0, 0),
+	MX8MP_PAD_HDMI_HPD__HDMIMIX_HDMI_HPD                     = IOMUX_PAD(0x04AC, 0x024C, 0, 0x0000, 0, 0),
+	MX8MP_PAD_HDMI_HPD__AUDIOMIX_HDMI_HPD_O                  = IOMUX_PAD(0x04AC, 0x024C, 1, 0x0000, 0, 0),
 	MX8MP_PAD_HDMI_HPD__I2C6_SDA                             = IOMUX_PAD(0x04AC, 0x024C, 3 | IOMUX_CONFIG_SION, 0x05D0, 3, 0),
 	MX8MP_PAD_HDMI_HPD__CAN2_RX                              = IOMUX_PAD(0x04AC, 0x024C, 4, 0x0550, 3, 0),
 	MX8MP_PAD_HDMI_HPD__GPIO3_IO29                           = IOMUX_PAD(0x04AC, 0x024C, 5, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-imx8m/imx8mq_sec_def.h b/arch/arm/include/asm/arch-imx8m/imx8mq_sec_def.h
new file mode 100644
index 00000000000..71678e672d7
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/imx8mq_sec_def.h
@@ -0,0 +1,268 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef IMX_SEC_DEF_H
+#define IMX_SEC_DEF_H
+
+/* RDC MDA index */
+enum rdc_mda_idx {
+	RDC_MDA_A53 = 0,
+	RDC_MDA_M4 = 1,
+	RDC_MDA_PCIE_CTRL1 = 2,
+	RDC_MDA_PCIE_CTRL2 = 3,
+	RDC_MDA_VPU_DEC = 4,
+	RDC_MDA_LCDIF = 5,
+	RDC_MDA_CSI1 = 6,
+	RDC_MDA_CSI2 = 7,
+	RDC_MDA_Coresight = 8,
+	RDC_MDA_DAP = 9,
+	RDC_MDA_CAAM = 10,
+	RDC_MDA_SDMAp = 11,
+	RDC_MDA_SDMAb = 12,
+	RDC_MDA_APBHDMA = 13,
+	RDC_MDA_RAWNAND = 14,
+	RDC_MDA_uSDHC1 = 15,
+	RDC_MDA_uSDHC2 = 16,
+	RDC_MDA_DCSS = 17,
+	RDC_MDA_GPU = 18,
+	RDC_MDA_USB1 = 19,
+	RDC_MDA_USB2 = 20,
+	RDC_MDA_TESTPORT = 21,
+	RDC_MDA_ENET1_TX = 22,
+	RDC_MDA_ENET1_RX = 23,
+	RDC_MDA_SDMA2 = 24,
+	RDC_MDA_SDMA1 = 26,
+};
+
+/* RDC Peripherals index */
+enum rdc_pdap_idx {
+	RDC_PDAP_GPIO1 = 0,
+	RDC_PDAP_GPIO2 = 1,
+	RDC_PDAP_GPIO3 = 2,
+	RDC_PDAP_GPIO4 = 3,
+	RDC_PDAP_GPIO5 = 4,
+	RDC_PDAP_ANA_TSENSOR = 6,
+	RDC_PDAP_ANA_OSC = 7,
+	RDC_PDAP_WDOG1 = 8,
+	RDC_PDAP_WDOG2 = 9,
+	RDC_PDAP_WDOG3 = 10,
+	RDC_PDAP_SDMA2 = 12,
+	RDC_PDAP_GPT1 = 13,
+	RDC_PDAP_GPT2 = 14,
+	RDC_PDAP_GPT3 = 15,
+	RDC_PDAP_ROMCP = 17,
+	RDC_PDAP_LCDIF = 18,
+	RDC_PDAP_IOMUXC = 19,
+	RDC_PDAP_IOMUXC_GPR = 20,
+	RDC_PDAP_OCOTP_CTRL = 21,
+	RDC_PDAP_ANATOP_PLL = 22,
+	RDC_PDAP_SNVS_HP = 23,
+	RDC_PDAP_CCM = 24,
+	RDC_PDAP_SRC = 25,
+	RDC_PDAP_GPC = 26,
+	RDC_PDAP_SEMAPHORE1 = 27,
+	RDC_PDAP_SEMAPHORE2 = 28,
+	RDC_PDAP_RDC = 29,
+	RDC_PDAP_CSU = 30,
+	RDC_PDAP_MST0 = 32,
+	RDC_PDAP_MST1 = 33,
+	RDC_PDAP_MST2 = 34,
+	RDC_PDAP_MST3 = 35,
+	RDC_PDAP_HDMI_SEC = 36,
+	RDC_PDAP_PWM1 = 38,
+	RDC_PDAP_PWM2 = 39,
+	RDC_PDAP_PWM3 = 40,
+	RDC_PDAP_PWM4 = 41,
+	RDC_PDAP_SysCounter_RD = 42,
+	RDC_PDAP_SysCounter_CMP = 43,
+	RDC_PDAP_SysCounter_CTRL = 44,
+	RDC_PDAP_HDMI_CTRL = 45,
+	RDC_PDAP_GPT6 = 46,
+	RDC_PDAP_GPT5 = 47,
+	RDC_PDAP_GPT4 = 48,
+	RDC_PDAP_TZASC = 56,
+	RDC_PDAP_MTR = 59,
+	RDC_PDAP_PERFMON1 = 60,
+	RDC_PDAP_PERFMON2 = 61,
+	RDC_PDAP_PLATFORM_CTRL = 62,
+	RDC_PDAP_QoSC = 63,
+	RDC_PDAP_MIPI_PHY = 64,
+	RDC_PDAP_MIPI_DSI = 65,
+	RDC_PDAP_I2C1 = 66,
+	RDC_PDAP_I2C2 = 67,
+	RDC_PDAP_I2C3 = 68,
+	RDC_PDAP_I2C4 = 69,
+	RDC_PDAP_UART4 = 70,
+	RDC_PDAP_MIPI_CSI1 = 71,
+	RDC_PDAP_MIPI_CSI_PHY1 = 72,
+	RDC_PDAP_CSI1 = 73,
+	RDC_PDAP_MU_A = 74,
+	RDC_PDAP_MU_B = 75,
+	RDC_PDAP_SEMAPHORE_HS = 76,
+	RDC_PDAP_SAI1 = 78,
+	RDC_PDAP_SAI6 = 80,
+	RDC_PDAP_SAI5 = 81,
+	RDC_PDAP_SAI4 = 82,
+	RDC_PDAP_USDHC1 = 84,
+	RDC_PDAP_USDHC2 = 85,
+	RDC_PDAP_MIPI_CSI2 = 86,
+	RDC_PDAP_MIPI_CSI_PHY2 = 87,
+	RDC_PDAP_CSI2 = 88,
+	RDC_PDAP_QSPI = 91,
+	RDC_PDAP_SDMA1 = 93,
+	RDC_PDAP_ENET1 = 94,
+	RDC_PDAP_SPDIF1 = 97,
+	RDC_PDAP_ECSPI1 = 98,
+	RDC_PDAP_ECSPI2 = 99,
+	RDC_PDAP_ECSPI3 = 100,
+	RDC_PDAP_UART1 = 102,
+	RDC_PDAP_UART3 = 104,
+	RDC_PDAP_UART2 = 105,
+	RDC_PDAP_SPDIF2 = 106,
+	RDC_PDAP_SAI2 = 107,
+	RDC_PDAP_SAI3 = 108,
+	RDC_PDAP_SPBA1 = 111,
+	RDC_PDAP_CAAM = 114,
+	RDC_PDAP_DDRC_SEC = 115,
+	RDC_PDAP_GIC_EXSC = 116,
+	RDC_PDAP_USB_EXSC = 117,
+	RDC_PDAP_OCRAM_TZ = 118,
+	RDC_PDAP_OCRAM_S_TZ = 119,
+	RDC_PDAP_VPU_SEC = 120,
+	RDC_PDAP_DAP_EXSC = 121,
+	RDC_PDAP_ROMCP_SEC = 122,
+	RDC_PDAP_APBHDMA_SEC = 123,
+	RDC_PDAP_M4_SEC = 124,
+	RDC_PDAP_QSPI_SEC = 125,
+	RDC_PDAP_GPU_EXSC = 126,
+	RDC_PDAP_PCIE = 127,
+};
+
+enum csu_csl_idx {
+	CSU_CSL_GPIO1 = 0,
+	CSU_CSL_GPIO2 = 1,
+	CSU_CSL_GPIO3 = 2,
+	CSU_CSL_GPIO4 = 3,
+	CSU_CSL_GPIO5 = 4,
+	CSU_CSL_ANA_TSENSOR = 6,
+	CSU_CSL_ANA_OSC = 7,
+	CSU_CSL_WDOG1 = 8,
+	CSU_CSL_WDOG2 = 9,
+	CSU_CSL_WDOG3 = 10,
+	CSU_CSL_SDMA2 = 12,
+	CSU_CSL_GPT1 = 13,
+	CSU_CSL_GPT2 = 14,
+	CSU_CSL_GPT3 = 15,
+	CSU_CSL_ROMCP = 17,
+	CSU_CSL_LCDIF = 18,
+	CSU_CSL_IOMUXC = 19,
+	CSU_CSL_IOMUXC_GPR = 20,
+	CSU_CSL_OCOTP_CTRL = 21,
+	CSU_CSL_ANATOP_PLL = 22,
+	CSU_CSL_SNVS_HP = 23,
+	CSU_CSL_CCM = 24,
+	CSU_CSL_SRC = 25,
+	CSU_CSL_GPC = 26,
+	CSU_CSL_SEMAPHORE1 = 27,
+	CSU_CSL_SEMAPHORE2 = 28,
+	CSU_CSL_RDC = 29,
+	CSU_CSL_CSU = 30,
+	CSU_CSL_MST0 = 32,
+	CSU_CSL_MST1 = 33,
+	CSU_CSL_MST2 = 34,
+	CSU_CSL_MST3 = 35,
+	CSU_CSL_HDMI_SEC = 36,
+	CSU_CSL_PWM1 = 38,
+	CSU_CSL_PWM2 = 39,
+	CSU_CSL_PWM3 = 40,
+	CSU_CSL_PWM4 = 41,
+	CSU_CSL_SysCounter_RD = 42,
+	CSU_CSL_SysCounter_CMP = 43,
+	CSU_CSL_SysCounter_CTRL = 44,
+	CSU_CSL_HDMI_CTRL = 45,
+	CSU_CSL_GPT6 = 46,
+	CSU_CSL_GPT5 = 47,
+	CSU_CSL_GPT4 = 48,
+	CSU_CSL_TZASC = 56,
+	CSU_CSL_MTR = 59,
+	CSU_CSL_PERFMON1 = 60,
+	CSU_CSL_PERFMON2 = 61,
+	CSU_CSL_PLATFORM_CTRL = 62,
+	CSU_CSL_QoSC = 63,
+	CSU_CSL_MIPI_PHY = 64,
+	CSU_CSL_MIPI_DSI = 65,
+	CSU_CSL_I2C1 = 66,
+	CSU_CSL_I2C2 = 67,
+	CSU_CSL_I2C3 = 68,
+	CSU_CSL_I2C4 = 69,
+	CSU_CSL_UART4 = 70,
+	CSU_CSL_MIPI_CSI1 = 71,
+	CSU_CSL_MIPI_CSI_PHY1 = 72,
+	CSU_CSL_CSI1 = 73,
+	CSU_CSL_MU_A = 74,
+	CSU_CSL_MU_B = 75,
+	CSU_CSL_SEMAPHORE_HS = 76,
+	CSU_CSL_SAI1 = 78,
+	CSU_CSL_SAI6 = 80,
+	CSU_CSL_SAI5 = 81,
+	CSU_CSL_SAI4 = 82,
+	CSU_CSL_USDHC1 = 84,
+	CSU_CSL_USDHC2 = 85,
+	CSU_CSL_MIPI_CSI2 = 86,
+	CSU_CSL_MIPI_CSI_PHY2 = 87,
+	CSU_CSL_CSI2 = 88,
+	CSU_CSL_QSPI = 91,
+	CSU_CSL_SDMA1 = 93,
+	CSU_CSL_ENET1 = 94,
+	CSU_CSL_SPDIF1 = 97,
+	CSU_CSL_ECSPI1 = 98,
+	CSU_CSL_ECSPI2 = 99,
+	CSU_CSL_ECSPI3 = 100,
+	CSU_CSL_UART1 = 102,
+	CSU_CSL_UART3 = 104,
+	CSU_CSL_UART2 = 105,
+	CSU_CSL_SPDIF2 = 106,
+	CSU_CSL_SAI2 = 107,
+	CSU_CSL_SAI3 = 108,
+	CSU_CSL_SPBA1 = 111,
+	CSU_CSL_MOD_EN3 = 112,
+	CSU_CSL_MOD_EN0 = 113,
+	CSU_CSL_CAAM = 114,
+	CSU_CSL_DDRC_SEC = 115,
+	CSU_CSL_GIC_EXSC = 116,
+	CSU_CSL_USB_EXSC = 117,
+	CSU_CSL_OCRAM = 118,
+	CSU_CSL_OCRAM_S = 119,
+	CSU_CSL_VPU_SEC = 120,
+	CSU_CSL_DAP_EXSC = 121,
+	CSU_CSL_ROMCP_SEC = 122,
+	CSU_CSL_APBHDMA_SEC = 123,
+	CSU_CSL_M4_SEC = 124,
+	CSU_CSL_QSPI_SEC = 125,
+	CSU_CSL_GPU_EXSC = 126,
+	CSU_CSL_PCIE = 127,
+};
+
+enum csu_sa_idx {
+	CSU_SA_M4 = 1 ,
+	CSU_SA_SDMA1 = 2 ,
+	CSU_SA_LCDIF = 3 ,
+	CSU_SA_USB = 4 ,
+	CSU_SA_PCIE_CTRL = 5 ,
+	CSU_SA_VPU_DECODER = 6 ,
+	CSU_SA_GPU = 7 ,
+	CSU_SA_APBHDMA = 8 ,
+	CSU_SA_ENET1 = 9 ,
+	CSU_SA_USDHC1 = 10 ,
+	CSU_SA_USDHC2 = 11 ,
+	CSU_SA_DISPLAY_CONTROLLER = 12 ,
+	CSU_SA_HUGO = 13 ,
+	CSU_SA_DAP = 14 ,
+	CSU_SA_SDMA2 = 15 ,
+	CSU_SA_CAAM = 16 ,
+};
+
+#endif /* IMX_SEC_DEF_H */
diff --git a/arch/arm/include/asm/arch-imx8m/sys_proto.h b/arch/arm/include/asm/arch-imx8m/sys_proto.h
index d328542ece2..3e54f9b6764 100644
--- a/arch/arm/include/asm/arch-imx8m/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h
@@ -11,6 +11,7 @@
 void set_wdog_reset(struct wdog_regs *wdog);
 void enable_tzc380(void);
 void restore_boot_params(void);
+int imx8m_usb_power(int usb_id, bool on);
 extern unsigned long rom_pointer[];
 enum boot_device get_boot_device(void);
 bool is_usb_boot(void);
diff --git a/arch/arm/include/asm/arch-imx8ulp/cgc.h b/arch/arm/include/asm/arch-imx8ulp/cgc.h
index ad3edc85adb..83a246b15a7 100644
--- a/arch/arm/include/asm/arch-imx8ulp/cgc.h
+++ b/arch/arm/include/asm/arch-imx8ulp/cgc.h
@@ -146,11 +146,11 @@ struct cgc2_regs {
 };
 
 u32 cgc_clk_get_rate(enum cgc_clk clk);
-void cgc1_pll3_init(void);
-void cgc1_pll2_init(void);
+void cgc1_pll3_init(ulong freq);
+void cgc1_pll2_init(ulong freq);
 void cgc1_soscdiv_init(void);
-void cgc1_init_core_clk(void);
-void cgc2_pll4_init(void);
+void cgc1_init_core_clk(ulong freq);
+void cgc2_pll4_init(bool pll4_reset);
 void cgc2_ddrclk_config(u32 src, u32 div);
 void cgc2_ddrclk_wait_unlock(void);
 u32 cgc1_sosc_div(enum cgc_clk clk);
diff --git a/arch/arm/include/asm/arch-imx8ulp/clock.h b/arch/arm/include/asm/arch-imx8ulp/clock.h
index c0f32cc087f..2275a49ac54 100644
--- a/arch/arm/include/asm/arch-imx8ulp/clock.h
+++ b/arch/arm/include/asm/arch-imx8ulp/clock.h
@@ -6,6 +6,8 @@
 #ifndef _ASM_ARCH_IMX8ULP_CLOCK_H
 #define _ASM_ARCH_IMX8ULP_CLOCK_H
 
+#define MHZ(X)	((X) * 1000000UL)
+
 /* Mainly for compatible to imx common code. */
 enum mxc_clock {
 	MXC_ARM_CLK = 0,
@@ -36,7 +38,8 @@ void init_clk_usdhc(u32 index);
 void init_clk_fspi(int index);
 void init_clk_ddr(void);
 int set_ddr_clk(u32 phy_freq_mhz);
-void clock_init(void);
+void clock_init_early(void);
+void clock_init_late(void);
 void cgc1_enet_stamp_sel(u32 clk_src);
 void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz);
 void reset_lcdclk(void);
diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
index 91adc85525c..e07012e7d63 100644
--- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
@@ -10,10 +10,13 @@
 #include <linux/bitops.h>
 #include <linux/sizes.h>
 
+#define CAAM_ARB_BASE_ADDR      0x26000000
+
 #define PBRIDGE0_BASE		0x28000000
 
 #define CMC0_RBASE		0x28025000
 
+#define MU0_B_BASE_ADDR		0x29220000
 #define CMC1_BASE_ADDR		0x29240000
 
 #define SIM1_BASE_ADDR		0x29290000
@@ -59,8 +62,13 @@
 #define AVD_SIM_LPDDR_CTRL	(AVD_SIM_BASE_ADDR + 0x14)
 #define AVD_SIM_LPDDR_CTRL2	(AVD_SIM_BASE_ADDR + 0x18)
 
+#define CONFIG_SYS_FSL_SEC_ADDR	0x292e0000
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
+
 #define FEC_QUIRK_ENET_MAC
 
+#define IMG_CONTAINER_BASE             (0x22010000UL)
+
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
 
@@ -158,6 +166,72 @@ struct usbphy_regs {
 	u32	usb1_pfda_ctrl1_clr;		/* 0x148 */
 	u32	usb1_pfda_ctrl1_tog;		/* 0x14c */
 };
+
+struct adc_regs {
+	u32	verid;		/* 0x000 */
+	u32	param;		/* 0x004 */
+	u32	reserved0[2];	/* 0x008 */
+	u32	ctrl;		/* 0x010 */
+	u32	stat;		/* 0x014 */
+	u32	ie;		/* 0x018 */
+	u32	de;		/* 0x01c */
+	u32	cfg;		/* 0x020 */
+	u32	pause;		/* 0x024 */
+	u32	reserved1[3];	/* 0x028 */
+	u32	swtrig;		/* 0x034 */
+	u32	tstat;		/* 0x038 */
+	u32	reserved2[25];	/* 0x03c */
+	u32	tctrl0;		/* 0x0a0 */
+	u32	tctrl1;		/* 0x0a4 */
+	u32	tctrl2;		/* 0x0a8 */
+	u32	tctrl3;		/* 0x0ac */
+	u32	reserved3[12];	/* 0x0b0 */
+	u32	fctrl0;		/* 0x0e0 */
+	u32	reserved4[7];	/* 0x0e4 */
+	u32	cmdl1;		/* 0x100 */
+	u32	cmdh1;		/* 0x104 */
+	u32	cmdl2;		/* 0x108 */
+	u32	cmdh2;		/* 0x10c */
+	u32	cmdl3;		/* 0x110 */
+	u32	cmdh3;		/* 0x114 */
+	u32	cmdl4;		/* 0x118 */
+	u32	cmdh4;		/* 0x11c */
+	u32	cmdl5;		/* 0x120 */
+	u32	cmdh5;		/* 0x124 */
+	u32	cmdl6;		/* 0x128 */
+	u32	cmdh6;		/* 0x12c */
+	u32	cmdl7;		/* 0x130 */
+	u32	cmdh7;		/* 0x134 */
+	u32	cmdl8;		/* 0x138 */
+	u32	cmdh8;		/* 0x13c */
+	u32	cmdl9;		/* 0x140 */
+	u32	cmdh9;		/* 0x144 */
+	u32	cmdl10;		/* 0x148 */
+	u32	cmdh10;		/* 0x14c */
+	u32	cmdl11;		/* 0x150 */
+	u32	cmdh11;		/* 0x154 */
+	u32	cmdl12;		/* 0x158 */
+	u32	cmdh12;		/* 0x15c */
+	u32	cmdl13;		/* 0x160 */
+	u32	cmdh13;		/* 0x164 */
+	u32	cmdl14;		/* 0x168 */
+	u32	cmdh14;		/* 0x16c */
+	u32	cmdl15;		/* 0x170 */
+	u32	cmdh15;		/* 0x174 */
+	u32	reserved5[34];	/* 0x178 */
+	u32	cv1;		/* 0x200 */
+	u32	cv2;		/* 0x204 */
+	u32	cv3;		/* 0x208 */
+	u32	cv4;		/* 0x20c */
+	u32	reserved6[60];	/* 0x210 */
+	u32	resfifo0;	/* 0x300 */
+};
+
+#include <stdbool.h>
+bool is_usb_boot(void);
+void disconnect_from_pc(void);
+#define is_boot_from_usb  is_usb_boot
+
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h b/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h
index d0eefcbc929..b002970fd81 100644
--- a/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h
+++ b/arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h
@@ -19,6 +19,19 @@ enum {
 	IMX8ULP_PAD_PTB10__PMIC0_SDA                        = IOMUX_PAD(0x00A8, 0x00A8, IOMUX_CONFIG_MPORTS | 0xA, 0x0804, 0x2, 0),
 	IMX8ULP_PAD_PTB11__PMIC0_SCL                        = IOMUX_PAD(0x00AC, 0x00AC, IOMUX_CONFIG_MPORTS | 0xA, 0x0800, 0x2, 0),
 
+	IMX8ULP_PAD_PTC0__FLEXSPI0_A_DQS					= IOMUX_PAD(0x0100, 0x0100, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	IMX8ULP_PAD_PTC1__FLEXSPI0_A_DATA7					= IOMUX_PAD(0x0104, 0x0104, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	IMX8ULP_PAD_PTC2__FLEXSPI0_A_DATA6					= IOMUX_PAD(0x0108, 0x0108, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	IMX8ULP_PAD_PTC3__FLEXSPI0_A_DATA5					= IOMUX_PAD(0x010c, 0x010c, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	IMX8ULP_PAD_PTC4__FLEXSPI0_A_DATA4					= IOMUX_PAD(0x0110, 0x0110, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	IMX8ULP_PAD_PTC5__FLEXSPI0_A_SS0_b					= IOMUX_PAD(0x0114, 0x0114, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	IMX8ULP_PAD_PTC6__FLEXSPI0_A_SCLK					= IOMUX_PAD(0x0118, 0x0118, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	IMX8ULP_PAD_PTC7__FLEXSPI0_A_DATA3					= IOMUX_PAD(0x011c, 0x011c, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	IMX8ULP_PAD_PTC8__FLEXSPI0_A_DATA2					= IOMUX_PAD(0x0120, 0x0120, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	IMX8ULP_PAD_PTC9__FLEXSPI0_A_DATA1					= IOMUX_PAD(0x0124, 0x0124, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+	IMX8ULP_PAD_PTC10__FLEXSPI0_A_DATA0					= IOMUX_PAD(0x0128, 0x0128, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
+
+
 	IMX8ULP_PAD_PTD0__SDHC0_RESET_b                     = IOMUX_PAD(0x0000, 0x0000, 0x8, 0x0000, 0x0, 0),
 	IMX8ULP_PAD_PTD1__SDHC0_CMD                         = IOMUX_PAD(0x0004, 0x0004, 0x8, 0x0000, 0x0, 0),
 	IMX8ULP_PAD_PTD2__SDHC0_CLK                         = IOMUX_PAD(0x0008, 0x0008, 0x8, 0x0000, 0x0, 0),
diff --git a/arch/arm/include/asm/arch-imx8ulp/pcc.h b/arch/arm/include/asm/arch-imx8ulp/pcc.h
index 46386f1aba4..d9b2d7c2998 100644
--- a/arch/arm/include/asm/arch-imx8ulp/pcc.h
+++ b/arch/arm/include/asm/arch-imx8ulp/pcc.h
@@ -52,6 +52,7 @@ enum pcc3_entry {
 	UPOWER_PCC3_SLOT = 40,
 	WDOG3_PCC3_SLOT = 42,
 	WDOG4_PCC3_SLOT = 43,
+	CAAM_PCC3_SLOT = 46,
 	XRDC_MGR_PCC3_SLOT = 47,
 	SEMA42_1_PCC3_SLOT = 48,
 	ROMCP1_PCC3_SLOT = 49,
diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h b/arch/arm/include/asm/arch-imx8ulp/s400_api.h
deleted file mode 100644
index c848f0dfb8f..00000000000
--- a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2021 NXP
- */
-
-#ifndef __S400_API_H__
-#define __S400_API_H__
-
-#define AHAB_VERSION    0x6
-#define AHAB_CMD_TAG    0x17
-#define AHAB_RESP_TAG   0xe1
-
-#define AHAB_LOG_CID            0x21
-#define AHAB_AUTH_OEM_CTNR_CID  0x87
-#define AHAB_VERIFY_IMG_CID     0x88
-#define AHAB_RELEASE_CTNR_CID   0x89
-#define AHAB_WRITE_SECURE_FUSE_REQ_CID	0x91
-#define AHAB_FWD_LIFECYCLE_UP_REQ_CID   0x95
-#define AHAB_READ_FUSE_REQ_CID	0x97
-#define AHAB_RELEASE_RDC_REQ_CID   0xC4
-#define AHAB_WRITE_FUSE_REQ_CID	0xD6
-
-#define S400_MAX_MSG          8U
-
-struct imx8ulp_s400_msg {
-	u8 version;
-	u8 size;
-	u8 command;
-	u8 tag;
-	u32 data[(S400_MAX_MSG - 1U)];
-};
-
-int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response);
-int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
-int ahab_release_container(u32 *response);
-int ahab_verify_image(u32 img_id, u32 *response);
-int ahab_forward_lifecycle(u16 life_cycle, u32 *response);
-int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response);
-int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response);
-
-#endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index 284ccafc988..e240ee6fca5 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -18,4 +18,7 @@ int xrdc_config_pdac_openacc(u32 bridge, u32 index);
 enum boot_device get_boot_device(void);
 void set_lpav_qos(void);
 void load_lposc_fuse(void);
+bool m33_image_booted(void);
+bool is_m33_handshake_necessary(void);
+int m33_image_handshake(ulong timeout_ms);
 #endif
diff --git a/arch/arm/include/asm/arch-imx9/ccm_regs.h b/arch/arm/include/asm/arch-imx9/ccm_regs.h
new file mode 100644
index 00000000000..d326a6ea516
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/ccm_regs.h
@@ -0,0 +1,266 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_CCM_REGS_H__
+#define __ASM_ARCH_IMX9_CCM_REGS_H__
+#define IMX93_CLK_ROOT_MAX	95
+#define IMX93_CLK_CCGR_MAX	127
+
+#define ARM_A55_PERIPH_CLK_ROOT		0
+#define ARM_A55_MTR_BUS_CLK_ROOT	1
+#define ARM_A55_CLK_ROOT		2
+#define M33_CLK_ROOT			3
+#define SENTINEL_CLK_ROOT		4
+#define BUS_WAKEUP_CLK_ROOT		5
+#define BUS_AON_CLK_ROOT		6
+#define WAKEUP_AXI_CLK_ROOT		7
+#define SWO_TRACE_CLK_ROOT		8
+#define M33_SYSTICK_CLK_ROOT		9
+#define FLEXIO1_CLK_ROOT		10
+#define FLEXIO2_CLK_ROOT		11
+#define LPIT1_CLK_ROOT			12
+#define LPIT2_CLK_ROOT			13
+#define LPTMR1_CLK_ROOT			14
+#define LPTMR2_CLK_ROOT			15
+#define TPM1_CLK_ROOT			16
+#define TPM2_CLK_ROOT			17
+#define TPM3_CLK_ROOT			18
+#define TPM4_CLK_ROOT			19
+#define TPM5_CLK_ROOT			20
+#define TPM6_CLK_ROOT			21
+#define FLEXSPI1_CLK_ROOT		22
+#define CAN1_CLK_ROOT			23
+#define CAN2_CLK_ROOT			24
+#define LPUART1_CLK_ROOT		25
+#define LPUART2_CLK_ROOT		26
+#define LPUART3_CLK_ROOT		27
+#define LPUART4_CLK_ROOT		28
+#define LPUART5_CLK_ROOT		29
+#define LPUART6_CLK_ROOT		30
+#define LPUART7_CLK_ROOT		31
+#define LPUART8_CLK_ROOT		32
+#define LPI2C1_CLK_ROOT			33
+#define LPI2C2_CLK_ROOT			34
+#define LPI2C3_CLK_ROOT			35
+#define LPI2C4_CLK_ROOT			36
+#define LPI2C5_CLK_ROOT			37
+#define LPI2C6_CLK_ROOT			38
+#define LPI2C7_CLK_ROOT			39
+#define LPI2C8_CLK_ROOT			40
+#define LPSPI1_CLK_ROOT			41
+#define LPSPI2_CLK_ROOT			42
+#define LPSPI3_CLK_ROOT			43
+#define LPSPI4_CLK_ROOT			44
+#define LPSPI5_CLK_ROOT			45
+#define LPSPI6_CLK_ROOT			46
+#define LPSPI7_CLK_ROOT			47
+#define LPSPI8_CLK_ROOT			48
+#define I3C1_CLK_ROOT			49
+#define I3C2_CLK_ROOT			50
+#define USDHC1_CLK_ROOT			51
+#define USDHC2_CLK_ROOT			52
+#define USDHC3_CLK_ROOT			53
+#define SAI1_CLK_ROOT			54
+#define SAI2_CLK_ROOT			55
+#define SAI3_CLK_ROOT			56
+#define CCM_CKO1_CLK_ROOT		57
+#define CCM_CKO2_CLK_ROOT		58
+#define CCM_CKO3_CLK_ROOT		59
+#define CCM_CKO4_CLK_ROOT		60
+#define HSIO_CLK_ROOT			61
+#define HSIO_USB_TEST_60M_CLK_ROOT	62
+#define HSIO_ACSCAN_80M_CLK_ROOT	63
+#define HSIO_ACSCAN_480M_CLK_ROOT	64
+#define NIC_CLK_ROOT			65
+#define NIC_APB_CLK_ROOT		66
+#define ML_APB_CLK_ROOT			67
+#define ML_CLK_ROOT			68
+#define MEDIA_AXI_CLK_ROOT		69
+#define MEDIA_APB_CLK_ROOT		70
+#define MEDIA_LDB_CLK_ROOT		71
+#define MEDIA_DISP_PIX_CLK_ROOT		72
+#define CAM_PIX_CLK_ROOT		73
+#define MIPI_TEST_BYTE_CLK_ROOT		74
+#define MIPI_PHY_CFG_CLK_ROOT		75
+#define DRAM_ALT_CLK_ROOT		76
+#define DRAM_APB_CLK_ROOT		77
+#define ADC_CLK_ROOT			78
+#define PDM_CLK_ROOT			79
+#define TSTMR1_CLK_ROOT			80
+#define TSTMR2_CLK_ROOT			81
+#define MQS1_CLK_ROOT			82
+#define MQS2_CLK_ROOT			83
+#define AUDIO_XCVR_CLK_ROOT		84
+#define SPDIF_CLK_ROOT			85
+#define ENET_CLK_ROOT			86
+#define ENET_TIMER1_CLK_ROOT		87
+#define ENET_TIMER2_CLK_ROOT		88
+#define ENET_REF_CLK_ROOT		89
+#define ENET_REF_PHY_CLK_ROOT		90
+#define I3C1_SLOW_CLK_ROOT		91
+#define I3C2_SLOW_CLK_ROOT		92
+#define USB_PHY_BURUNIN_CLK_ROOT	93
+#define PAL_CAME_SCAN_CLK_ROOT	94
+#define CLK_ROOT_NUM			95
+
+#define CCGR_A55	0
+#define CCGR_CM33	1
+#define CCGR_ARMTROUT	2
+#define CCGR_SENT	3
+#define CCGR_BUSM	4
+#define CCGR_BUS7	5
+#define CCGR_BUSD	6
+#define CCGR_ANAD	7
+#define CCGR_SRC	8
+#define CCGR_CCM	9
+#define CCGR_GPC	10
+#define CCGR_ADC	11
+#define CCGR_WDG1	12
+#define CCGR_WDG2	13
+#define CCGR_WDG3	14
+#define CCGR_WDG4	15
+#define CCGR_WDG5	16
+#define CCGR_SEM1	17
+#define CCGR_SEM2	18
+#define CCGR_MUA	19
+#define CCGR_MUB	20
+#define CCGR_DMA1	21
+#define CCGR_DMA2	22
+#define CCGR_ROMCA55	23
+#define CCGR_ROMCM33	24
+#define CCGR_QSP1	25
+#define CCGR_AONRDC	26
+#define CCGR_WKUPRDC	27
+#define CCGR_FUSE	28
+#define CCGR_SNVH	29
+#define CCGR_SNVS	30
+#define CCGR_TRAC	31
+#define CCGR_SWO	32
+#define CCGR_IOCG	33
+#define CCGR_PIO1	34
+#define CCGR_PIO2	35
+#define CCGR_PIO3	36
+#define CCGR_PIO4	37
+#define CCGR_FIO1	38
+#define CCGR_FIO2	39
+#define CCGR_PIT1	40
+#define CCGR_PIT2	41
+#define CCGR_GPT1	42
+#define CCGR_GPT2	43
+#define CCGR_TPM1	44
+#define CCGR_TPM2	45
+#define CCGR_TPM3	46
+#define CCGR_TPM4	47
+#define CCGR_TPM5	48
+#define CCGR_TPM6	49
+#define CCGR_CAN1	50
+#define CCGR_CAN2	51
+#define CCGR_URT1	52
+#define CCGR_URT2	53
+#define CCGR_URT3	54
+#define CCGR_URT4	55
+#define CCGR_URT5	56
+#define CCGR_URT6	57
+#define CCGR_URT7	58
+#define CCGR_URT8	59
+#define CCGR_I2C1	60
+#define CCGR_I2C2	61
+#define CCGR_I2C3	62
+#define CCGR_I2C4	63
+#define CCGR_I2C5	64
+#define CCGR_I2C6	65
+#define CCGR_I2C7	66
+#define CCGR_I2C8	67
+#define CCGR_SPI1	68
+#define CCGR_SPI2	69
+#define CCGR_SPI3	70
+#define CCGR_SPI4	71
+#define CCGR_SPI5	72
+#define CCGR_SPI6	73
+#define CCGR_SPI7	74
+#define CCGR_SPI8	75
+#define CCGR_I3C1	76
+#define CCGR_I3C2	77
+#define CCGR_USDHC1	78
+#define CCGR_USDHC2	79
+#define CCGR_USDHC3	80
+#define CCGR_SAI1	81
+#define CCGR_SAI2	82
+#define CCGR_SAI3	83
+#define CCGR_W2AO	84
+#define CCGR_AO2W	85
+#define CCGR_MIPIC	86
+#define CCGR_MIPID	87
+#define CCGR_LVDS	88
+#define CCGR_LCDIF	89
+#define CCGR_PXP	90
+#define CCGR_ISI	91
+#define CCGR_NMED	92
+#define CCGR_DFI	93
+#define CCGR_DDRC	94
+#define CCGR_DFIC	95
+#define CCGR_DSSI	96
+#define CCGR_DBYP	97
+#define CCGR_DAPB	98
+#define CCGR_DRAMP	99
+#define CCGR_DCLKC	100
+#define CCGR_NCTL	101
+#define CCGR_GIC	102
+#define CCGR_NICAPB	103
+#define CCGR_USBC	104
+#define CCGR_USBT	105
+#define CCGR_HSIO	106
+#define CCGR_PDM	107
+#define CCGR_MQS1	108
+#define CCGR_MQS2	109
+#define CCGR_AXCVR	110
+#define CCGR_MECC	111
+#define CCGR_SPDIF	112
+#define CCGR_ML2NIC	113
+#define CCGR_MED2NIC	114
+#define CCGR_HSIO2NIC	115
+#define CCGR_W2NIC	116
+#define CCGR_NIC2W	117
+#define CCGR_NIC2DDR	118
+#define CCGR_HSIO32K	119
+#define CCGR_ENET1	120
+#define CCGR_ENETQOS	121
+#define CCGR_SYSCNT	122
+#define CCGR_TSTMR1	123
+#define CCGR_TSTMR2	124
+#define CCGR_TMC	125
+#define CCGR_PMRO	126
+#define CCGR_NUM	127
+
+#define SHARED_GPR_EXT_CLK 0
+#define SHARED_GPR_EXT_CLK_SEL_EXT1 0
+#define SHARED_GPR_EXT_CLK_SEL_EXT2 BIT(0)
+#define SHARED_GPR_EXT_CLK_SEL_EXT3 BIT(1)
+#define SHARED_GPR_EXT_CLK_SEL_EXT4 GENMASK(1, 0)
+
+#define SHARED_GPR_A55_CLK 1
+#define SHARED_GPR_A55_CLK_SEL_CCM 0
+#define SHARED_GPR_A55_CLK_SEL_PLL BIT(0)
+
+#define SHARED_GPR_DRAM_CLK 2
+#define SHARED_GPR_DRAM_CLK_SEL_PLL 0
+#define SHARED_GPR_DRAM_CLK_SEL_CCM BIT(0)
+
+#define SHARED_GPR_NUM 8
+#define PRIVATE_GPR_NUM 8
+
+#define CLK_ROOT_STATUS_OFF		BIT(24)
+#define CLK_ROOT_STATUS_CHANGING	BIT(31)
+#define CLK_ROOT_MUX_MASK		GENMASK(9, 8)
+#define CLK_ROOT_MUX_SHIFT		8
+#define CLK_ROOT_DIV_MASK		GENMASK(7, 0)
+
+#define CCM_AUTHEN_LOCK_TZ		BIT(11)
+#define CCM_AUTHEN_TZ_NS		BIT(9)
+#define CCM_AUTHEN_TZ_USER		BIT(8)
+#define CCM_AUTHEN_CPULPM_MODE	BIT(2)
+#define CCM_AUTHEN_AUTO_CTRL	BIT(3)
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h
new file mode 100644
index 00000000000..5cb762d4299
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -0,0 +1,249 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ *
+ * Peng Fan <peng.fan at nxp.com>
+ */
+
+#ifndef __CLOCK_IMX9__
+#define __CLOCK_IMX9__
+
+#include <linux/bitops.h>
+
+#define MHZ(x)	((x) * 1000000UL)
+
+enum enet_freq {
+	ENET_25MHZ = 0,
+	ENET_50MHZ,
+	ENET_125MHZ,
+};
+
+enum ccm_clk_src {
+	OSC_24M_CLK,
+	ARM_PLL,
+	ARM_PLL_CLK,
+	SYS_PLL_PG,
+	SYS_PLL_PFD0_PG,
+	SYS_PLL_PFD0,
+	SYS_PLL_PFD0_DIV2,
+	SYS_PLL_PFD1_PG,
+	SYS_PLL_PFD1,
+	SYS_PLL_PFD1_DIV2,
+	SYS_PLL_PFD2_PG,
+	SYS_PLL_PFD2,
+	SYS_PLL_PFD2_DIV2,
+	AUDIO_PLL,
+	AUDIO_PLL_CLK,
+	DRAM_PLL,
+	DRAM_PLL_CLK,
+	VIDEO_PLL,
+	VIDEO_PLL_CLK,
+	OSCPLL_END,
+	EXT_CLK,
+};
+
+/* Mainly for compatible to imx common code. */
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_IPG_CLK,
+	MXC_FLEXSPI_CLK,
+	MXC_CSPI_CLK,
+	MXC_ESDHC_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_ESDHC3_CLK,
+	MXC_UART_CLK,
+	MXC_I2C_CLK,
+	MXC_FEC_CLK,
+};
+
+struct ccm_obs {
+	u32 direct;
+	u32 reserved[31];
+};
+
+struct ccm_gpr {
+	u32 gpr;
+	u32 gpr_set;
+	u32 gpr_clr;
+	u32 gpr_tog;
+	u32 authen;
+	u32 authen_set;
+	u32 authen_clr;
+	u32 authen_tog;
+};
+
+struct ccm_lpcg_oscpll {
+	u32 direct;
+	u32 lpm_status0;
+	u32 lpm_status1;
+	u32 reserved0;
+	u32 lpm0;
+	u32 lpm1;
+	u32 reserved1;
+	u32 lpm_cur;
+	u32 status0;
+	u32 status1;
+	u32 reserved2[2];
+	u32 authen;
+	u32 reserved3[3];
+};
+
+struct ccm_root {
+	u32 control;
+	u32 control_set;
+	u32 control_clr;
+	u32 control_tog;
+	u32 reserved[4];
+	u32 status0;
+	u32 reserved1[3];
+	u32 authen;
+	u32 reserved2[19];
+};
+
+struct ccm_reg {
+	struct ccm_root clk_roots[95]; /* 0x0 */
+	u32 reserved_0[1312];
+	struct ccm_obs clk_obs[6]; /* 0x4400 */
+	u32 reserved_1[64];
+	struct ccm_gpr clk_shared_gpr[8]; /* 0x4800 */
+	u32 reserved_2[192];
+	struct ccm_gpr clk_private_gpr[8]; /* 0x4C00 */
+	u32 reserved_3[192];
+	struct ccm_lpcg_oscpll clk_oscplls[19]; /* 0x5000 */
+	u32 reserved_4[2768];
+	struct ccm_lpcg_oscpll clk_lpcgs[122]; /* 0x8000 */
+};
+
+struct ana_pll_reg_elem {
+	u32 reg;
+	u32 reg_set;
+	u32 reg_clr;
+	u32 reg_tog;
+};
+
+struct ana_pll_dfs {
+	struct ana_pll_reg_elem dfs_ctrl;
+	struct ana_pll_reg_elem dfs_div;
+};
+
+struct ana_pll_reg {
+	struct ana_pll_reg_elem ctrl;
+	struct ana_pll_reg_elem ana_prg;
+	struct ana_pll_reg_elem test;
+	struct ana_pll_reg_elem ss; /* Spread spectrum */
+	struct ana_pll_reg_elem num; /* numerator */
+	struct ana_pll_reg_elem denom; /* demoninator */
+	struct ana_pll_reg_elem div;
+	struct ana_pll_dfs dfs[4];
+	u32 pll_status;
+	u32 dfs_status;
+	u32 reserved[2];
+};
+
+struct anatop_reg {
+	u32 osc_ctrl;
+	u32 osc_state;
+	u32 reserved_0[510];
+	u32 chip_version;
+	u32 reserved_1[511];
+	struct ana_pll_reg arm_pll;
+	struct ana_pll_reg sys_pll;
+	struct ana_pll_reg audio_pll;
+	struct ana_pll_reg dram_pll;
+	struct ana_pll_reg video_pll;
+};
+
+#define PLL_CTRL_HW_CTRL_SEL BIT(16)
+#define PLL_CTRL_CLKMUX_BYPASS BIT(2)
+#define PLL_CTRL_CLKMUX_EN BIT(1)
+#define PLL_CTRL_POWERUP BIT(0)
+
+#define PLL_STATUS_PLL_LOCK BIT(0)
+#define PLL_DFS_CTRL_ENABLE BIT(31)
+#define PLL_DFS_CTRL_CLKOUT BIT(30)
+#define PLL_DFS_CTRL_CLKOUT_DIV2 BIT(29)
+#define PLL_DFS_CTRL_BYPASS BIT(23)
+
+#define PLL_SS_EN BIT(15)
+
+struct imx_intpll_rate_table {
+	u32 rate; /*khz*/
+	int rdiv;
+	int mfi;
+	int odiv;
+};
+
+struct imx_fracpll_rate_table {
+	u32 rate; /*khz*/
+	int rdiv;
+	int mfi;
+	int odiv;
+	int mfn;
+	int mfd;
+};
+
+#define INT_PLL_RATE(_rate, _r, _m, _o)			\
+	{							\
+		.rate	=	(_rate),			\
+		.rdiv	=	(_r),				\
+		.mfi	=	(_m),				\
+		.odiv	=	(_o),				\
+	}
+
+#define FRAC_PLL_RATE(_rate, _r, _m, _o, _n, _d)			\
+	{							\
+		.rate	=	(_rate),			\
+		.rdiv	=	(_r),				\
+		.mfi	=	(_m),				\
+		.odiv	=	(_o),				\
+		.mfn	=	(_n),				\
+		.mfd	=	(_d),				\
+	}
+
+struct clk_root_map {
+	u32 clk_root_id;
+	u32 mux_type;
+};
+
+
+int clock_init(void);
+u32 get_clk_src_rate(enum ccm_clk_src source);
+u32 get_lpuart_clk(void);
+void init_uart_clk(u32 index);
+void init_clk_usdhc(u32 index);
+int enable_i2c_clk(unsigned char enable, u32 i2c_num);
+u32 imx_get_i2cclk(u32 i2c_num);
+u32 mxc_get_clock(enum mxc_clock clk);
+void dram_pll_init(ulong pll_val);
+void dram_enable_bypass(ulong clk_val);
+void dram_disable_bypass(void);
+
+int configure_intpll(enum ccm_clk_src pll, u32 freq);
+
+int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable);
+int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable);
+int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable);
+int ccm_clk_src_config_lpm(enum ccm_clk_src oscpll, u32 domain, u32 lpm_val);
+bool ccm_clk_src_is_clk_on(enum ccm_clk_src oscpll);
+int ccm_clk_src_tz_access(enum ccm_clk_src oscpll,
+	bool non_secure, bool user_mode, bool lock_tz);
+int ccm_clk_root_cfg(u32 clk_root_id, enum ccm_clk_src src, u32 div);
+u32 ccm_clk_root_get_rate(u32 clk_root_id);
+int ccm_clk_root_tz_access(u32 clk_root_id,
+	bool non_secure, bool user_mode, bool lock_tz);
+int ccm_lpcg_on(u32 lpcg, bool enable);
+int ccm_lpcg_lpm(u32 lpcg, bool enable);
+int ccm_lpcg_config_lpm(u32 lpcg, u32 domain, u32 lpm_val);
+bool ccm_lpcg_is_clk_on(u32 lpcg);
+int ccm_lpcg_tz_access(u32 lpcg,
+	bool non_secure, bool user_mode, bool lock_tz);
+int ccm_shared_gpr_set(u32 gpr, u32 val);
+int ccm_shared_gpr_get(u32 gpr, u32 *val);
+int ccm_shared_gpr_tz_access(u32 gpr,
+	bool non_secure, bool user_mode, bool lock_tz);
+
+void enable_usboh3_clk(unsigned char enable);
+int set_clk_enet(enum enet_freq type);
+int set_clk_eqos(enum enet_freq type);
+void mxs_set_lcdclk(u32 base_addr, u32 freq);
+#endif
diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h
new file mode 100644
index 00000000000..83983ed391b
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/ddr.h
@@ -0,0 +1,128 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8M_DDR_H
+#define __ASM_ARCH_IMX8M_DDR_H
+
+#include <asm/io.h>
+#include <asm/types.h>
+
+#define DDR_CTL_BASE			0x4E300000
+#define DDR_PHY_BASE 		   	0x4E100000
+#define DDRMIX_BLK_CTRL_BASE    0x4E010000
+
+#define REG_DDRDSR_2        	          (DDR_CTL_BASE + 0xB24)
+#define REG_DDR_TIMING_CFG_0			(DDR_CTL_BASE + 0x104)
+#define REG_DDR_SDRAM_CFG        	      (DDR_CTL_BASE + 0x110)
+#define REG_DDR_TIMING_CFG_4			(DDR_CTL_BASE + 0x160)
+#define REG_DDR_DEBUG_19        	      (DDR_CTL_BASE + 0xF48)
+
+#define SRC_BASE_ADDR                     (0x44460000)
+#define SRC_DPHY_BASE_ADDR                (SRC_BASE_ADDR + 0x1400)
+#define REG_SRC_DPHY_SW_CTRL              (SRC_DPHY_BASE_ADDR + 0x20)
+#define REG_SRC_DPHY_SINGLE_RESET_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x24)
+
+#define IP2APB_DDRPHY_IPS_BASE_ADDR(X)	(DDR_PHY_BASE + (X * 0x2000000))
+#define DDRPHY_MEM(X)			(DDR_PHY_BASE + (X * 0x2000000) + 0x50000)
+
+/* PHY State */
+enum pstate {
+	PS0,
+	PS1,
+	PS2,
+	PS3,
+};
+
+enum msg_response {
+	TRAIN_SUCCESS = 0x7,
+	TRAIN_STREAM_START = 0x8,
+	TRAIN_FAIL = 0xff,
+};
+
+/* user data type */
+enum fw_type {
+	FW_1D_IMAGE,
+	FW_2D_IMAGE,
+};
+
+struct dram_cfg_param {
+	unsigned int reg;
+	unsigned int val;
+};
+
+struct dram_fsp_msg {
+	unsigned int drate;
+	enum fw_type fw_type;
+	struct dram_cfg_param *fsp_cfg;
+	unsigned int fsp_cfg_num;
+};
+
+struct dram_timing_info {
+	/* umctl2 config */
+	struct dram_cfg_param *ddrc_cfg;
+	unsigned int ddrc_cfg_num;
+	/* ddrphy config */
+	struct dram_cfg_param *ddrphy_cfg;
+	unsigned int ddrphy_cfg_num;
+	/* ddr fsp train info */
+	struct dram_fsp_msg *fsp_msg;
+	unsigned int fsp_msg_num;
+	/* ddr phy trained CSR */
+	struct dram_cfg_param *ddrphy_trained_csr;
+	unsigned int ddrphy_trained_csr_num;
+	/* ddr phy PIE */
+	struct dram_cfg_param *ddrphy_pie;
+	unsigned int ddrphy_pie_num;
+	/* initialized drate table */
+	unsigned int fsp_table[4];
+};
+
+extern struct dram_timing_info dram_timing;
+
+void ddr_load_train_firmware(enum fw_type type);
+int ddr_init(struct dram_timing_info *timing_info);
+int ddr_cfg_phy(struct dram_timing_info *timing_info);
+void load_lpddr4_phy_pie(void);
+void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
+void dram_config_save(struct dram_timing_info *info, unsigned long base);
+void board_dram_ecc_scrub(void);
+void ddrc_inline_ecc_scrub(unsigned int start_address,
+			   unsigned int range_address);
+void ddrc_inline_ecc_scrub_end(unsigned int start_address,
+			       unsigned int range_address);
+
+/* utils function for ddr phy training */
+int wait_ddrphy_training_complete(void);
+void ddrphy_init_set_dfi_clk(unsigned int drate);
+void ddrphy_init_read_msg_block(enum fw_type type);
+
+void get_trained_CDD(unsigned int fsp);
+
+ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr);
+
+static inline void reg32_write(unsigned long addr, u32 val)
+{
+	writel(val, addr);
+}
+
+static inline u32 reg32_read(unsigned long addr)
+{
+	return readl(addr);
+}
+
+static inline void reg32setbit(unsigned long addr, u32 bit)
+{
+	setbits_le32(addr, (1 << bit));
+}
+
+#define dwc_ddrphy_apb_wr(addr, data) \
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr), data)
+#define dwc_ddrphy_apb_rd(addr) \
+	reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr))
+
+extern struct dram_cfg_param ddrphy_trained_csr[];
+extern uint32_t ddrphy_trained_csr_num;
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx9/gpio.h b/arch/arm/include/asm/arch-imx9/gpio.h
new file mode 100644
index 00000000000..599f7511c3b
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/gpio.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_GPIO_H
+#define __ASM_ARCH_IMX9_GPIO_H
+
+#include <common.h>
+
+struct gpio_regs {
+	u32 gpio_pdor;
+	u32 gpio_psor;
+	u32 gpio_pcor;
+	u32 gpio_ptor;
+	u32 gpio_pdir;
+	u32 gpio_pddr;
+	u32 gpio_pidr;
+	u8 gpio_pxdr[32];
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
new file mode 100644
index 00000000000..593409c30c0
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -0,0 +1,246 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_REGS_H__
+#define __ASM_ARCH_IMX9_REGS_H__
+
+#define ARCH_MXC
+#define FEC_QUIRK_ENET_MAC
+
+#define IOMUXC_BASE_ADDR	0x443C0000UL
+#define CCM_BASE_ADDR		0x44450000UL
+#define CCM_CCGR_BASE_ADDR	0x44458000UL
+#define SYSCNT_CTRL_BASE_ADDR	0x44290000
+
+#define WDG3_BASE_ADDR      0x42490000UL
+#define WDG4_BASE_ADDR      0x424a0000UL
+#define WDG5_BASE_ADDR      0x424b0000UL
+
+#define ANATOP_BASE_ADDR    0x44480000UL
+
+#define USB1_BASE_ADDR		0x4c100000
+#define USB2_BASE_ADDR		0x4c200000
+
+#define USB_BASE_ADDR		USB1_BASE_ADDR
+
+#define FSB_BASE_ADDR   0x47510000
+
+#define BLK_CTRL_WAKEUPMIX_BASE_ADDR 0x42420000
+#define BLK_CTRL_S_ANOMIX_BASE_ADDR  0x444f0000
+
+#define SRC_IPS_BASE_ADDR			(0x44460000)
+#define SRC_GLOBAL_RBASE			(SRC_IPS_BASE_ADDR + 0x0000)
+
+#define SRC_DDR_RBASE				(SRC_IPS_BASE_ADDR + 0x1000)
+#define SRC_ML_RBASE				(SRC_IPS_BASE_ADDR + 0x1800)
+#define SRC_MEDIA_RBASE				(SRC_IPS_BASE_ADDR + 0x2400)
+#define SRC_M33P_RBASE				(SRC_IPS_BASE_ADDR + 0x2800)
+
+#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT BIT(0)
+#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT BIT(2)
+#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
+#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
+
+#define IMG_CONTAINER_BASE             (0x80000000UL)
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#include <stdbool.h>
+
+#define BCTRL_GPR_ENET_QOS_INTF_MODE_MASK        GENMASK(3, 1)
+#define BCTRL_GPR_ENET_QOS_INTF_SEL_MII          (0x0 << 1)
+#define BCTRL_GPR_ENET_QOS_INTF_SEL_RMII         (0x4 << 1)
+#define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII        (0x1 << 1)
+#define BCTRL_GPR_ENET_QOS_CLK_GEN_EN            (0x1 << 0)
+
+#define BCTRL_S_ANOMIX_M33_CPU_WAIT_MASK 		BIT(2)
+
+enum mix_power_domain {
+	MIX_PD_MEDIAMIX,
+	MIX_PD_MLMIX,
+	MIX_PD_DDRMIX,
+};
+
+enum src_mix_slice_id {
+	SRC_MIX_EDGELOCK = 0,
+	SRC_MIX_AONMIX = 1,
+	SRC_MIX_WAKEUPMIX = 2,
+	SRC_MIX_DDRMIX = 3,
+	SRC_MIX_DDRPHY = 4,
+	SRC_MIX_ML = 5,
+	SRC_MIX_NIC = 6,
+	SRC_MIX_HSIO = 7,
+	SRC_MIX_MEDIA = 8,
+	SRC_MIX_CM33 = 9,
+	SRC_MIX_CA55C0 = 10,
+	SRC_MIX_CA55C1 = 11,
+	SRC_MIX_CA55CLUSTER = 12,
+};
+
+enum src_mem_slice_id {
+	SRC_MEM_AONMIX = 0,
+	SRC_MEM_WAKEUPMIX = 1,
+	SRC_MEM_DDRMIX = 2,
+	SRC_MEM_DDRPHY = 3,
+	SRC_MEM_ML = 4,
+	SRC_MEM_NIC = 5,
+	SRC_MEM_OCRAM = 6,
+	SRC_MEM_HSIO = 7,
+	SRC_MEM_MEDIA = 8,
+	SRC_MEM_CA55C0 = 9,
+	SRC_MEM_CA55C1 = 10,
+	SRC_MEM_CA55CLUSTER = 11,
+	SRC_MEM_L3 = 12,
+};
+
+struct blk_ctrl_s_aonmix_regs {
+	u32 cm33_irq_mask[7];
+	u32 initnsvtor;
+	u32 reserved1[8];
+	u32 ca55_irq_mask[7];
+	u32 initsvtor;
+	u32 m33_cfg;
+	u32 reserved2[11];
+	u32 axbs_aon_ctrl;
+	u32 reserved3[27];
+	u32 dap_access_stkybit;
+	u32 reserved4[3];
+	u32 lp_handshake[2];
+	u32 ca55_cpuwait;
+	u32 ca55_rvbaraddr0_l;
+	u32 ca55_rvbaraddr0_h;
+	u32 ca55_rvbaraddr1_l;
+	u32 ca55_rvbaraddr1_h;
+	u32 s401_irq_mask;
+	u32 s401_reset_req_mask;
+	u32 s401_halt_st;
+	u32 ca55_mode;
+	u32 nmi_mask;
+	u32 nmi_clr;
+	u32 wdog_any_mask;
+	u32 s4v1_ipi_noclk_ref1;
+};
+
+struct blk_ctrl_wakeupmix_regs {
+	u32 upper_addr;
+	u32 ipg_debug_cm33;
+	u32 reserved[2];
+	u32 qch_dis;
+	u32 ssi;
+	u32 reserved1[1];
+	u32 dexsc_err;
+	u32 mqs_setting;
+	u32 sai_clk_sel;
+	u32 eqos_gpr;
+	u32 enet_clk_sel;
+	u32 reserved2[1];
+	u32 volt_detect;
+	u32 i3c2_wakeup;
+	u32 ipg_debug_ca55c0;
+	u32 ipg_debug_ca55c1;
+	u32 axi_attr_cfg;
+	u32 i3c2_sda_irq;
+};
+
+struct mu_type {
+	u32 ver;
+	u32 par;
+	u32 cr;
+	u32 sr;
+	u32 reserved0[60];
+	u32 fcr;
+	u32 fsr;
+	u32 reserved1[2];
+	u32 gier;
+	u32 gcr;
+	u32 gsr;
+	u32 reserved2;
+	u32 tcr;
+	u32 tsr;
+	u32 rcr;
+	u32 rsr;
+	u32 reserved3[52];
+	u32 tr[16];
+	u32 reserved4[16];
+	u32 rr[16];
+	u32 reserved5[14];
+	u32 mu_attr;
+};
+
+struct src_general_regs {
+	u32 reserved[1];
+	u32 authen_ctrl;
+	u32 reserved1[2];
+	u32 scr;
+	u32 srtmr;
+	u32 srmask;
+	u32 reserved2[1];
+	u32 srmr[6];
+	u32 reserved3[2];
+	u32 sbmr[2];
+	u32 reserved4[2];
+	u32 srsr;
+	u32 gpr[19];
+	u32 reserved5[24];
+	u32 gpr20;
+	u32 cm_quiesce;
+	u32 cold_reset_ssar_ack_ctrl;
+	u32 sp_iso_ctrl;
+	u32 rom_lp_ctrl;
+	u32 a55_deny_stat;
+};
+
+struct src_mem_slice_regs {
+	u32 reserved[1];
+	u32 mem_ctrl;
+	u32 memlp_ctrl_0;
+	u32 reserved1[1];
+	u32 memlp_ctrl_1;
+	u32 memlp_ctrl_2;
+	u32 mem_stat;
+};
+
+struct src_mix_slice_regs {
+	u32 reserved[1];
+	u32 authen_ctrl;
+	u32 reserved1[2];
+	u32 lpm_setting[3];
+	u32 reserved2[1];
+	u32 slice_sw_ctrl;
+	u32 single_reset_sw_ctrl;
+	u32 reserved3[6];
+	u32 a55_hdsk_ack_ctrl;
+	u32 a55_hdsk_ack_stat;
+	u32 reserved4[2];
+	u32 ssar_ack_ctrl;
+	u32 ssar_ack_stat;
+	u32 reserved5[1];
+	u32 iso_off_dly_por;
+	u32 iso_on_dly;
+	u32 iso_off_dly;
+	u32 psw_off_lf_dly;
+	u32 reserved6[1];
+	u32 psw_off_hf_dly;
+	u32 psw_on_lf_dly;
+	u32 psw_on_hf_dly;
+	u32 reserved7[1];
+	u32 psw_ack_ctrl[2];
+	u32 psw_ack_stat;
+	u32 reserved8[1];
+	u32 mtr_ack_ctrl;
+	u32 mtr_ack_stat;
+	u32 reserved9[2];
+	u32 upi_stat[4];
+	u32 fsm_stat;
+	u32 func_stat;
+};
+
+bool is_usb_boot(void);
+void disconnect_from_pc(void);
+#define is_boot_from_usb  is_usb_boot
+
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx9/imx93_pins.h b/arch/arm/include/asm/arch-imx9/imx93_pins.h
new file mode 100644
index 00000000000..ae0eaa8354e
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/imx93_pins.h
@@ -0,0 +1,729 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX93_PINS_H__
+#define __ASM_ARCH_IMX93_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+         MX93_PAD_DAP_TDI__JTAG_MUX_TDI                           = IOMUX_PAD(0x01B0, 0x0000, 0, 0x03D8, 0, 0),
+         MX93_PAD_DAP_TDI__MQS2_LEFT                              = IOMUX_PAD(0x01B0, 0x0000, 1, 0x0000, 0, 0),
+         MX93_PAD_DAP_TDI__CAN2_TX                                = IOMUX_PAD(0x01B0, 0x0000, 3, 0x0000, 0, 0),
+         MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30                       = IOMUX_PAD(0x01B0, 0x0000, 4, 0x0000, 0, 0),
+         MX93_PAD_DAP_TDI__GPIO3_IO28                             = IOMUX_PAD(0x01B0, 0x0000, 5, 0x0000, 0, 0),
+         MX93_PAD_DAP_TDI__LPUART5_RX                             = IOMUX_PAD(0x01B0, 0x0000, 6, 0x0430, 0, 0),
+
+         MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS                     = IOMUX_PAD(0x01B4, 0x0004, 0, 0x03DC, 0, 0),
+         MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31                 = IOMUX_PAD(0x01B4, 0x0004, 4, 0x0000, 0, 0),
+         MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29                       = IOMUX_PAD(0x01B4, 0x0004, 5, 0x0000, 0, 0),
+         MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B                    = IOMUX_PAD(0x01B4, 0x0004, 6, 0x0000, 0, 0),
+
+         MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK                    = IOMUX_PAD(0x01B8, 0x0008, 0, 0x03D4, 0, 0),
+         MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30                = IOMUX_PAD(0x01B8, 0x0008, 4, 0x0000, 0, 0),
+         MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30                      = IOMUX_PAD(0x01B8, 0x0008, 5, 0x0000, 0, 0),
+         MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B                   = IOMUX_PAD(0x01B8, 0x0008, 6, 0x042C, 0, 0),
+
+         MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO                  = IOMUX_PAD(0x01BC, 0x000C, 0, 0x0000, 0, 0),
+         MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT                    = IOMUX_PAD(0x01BC, 0x000C, 1, 0x0000, 0, 0),
+         MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX                       = IOMUX_PAD(0x01BC, 0x000C, 3, 0x0364, 0, 0),
+         MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31              = IOMUX_PAD(0x01BC, 0x000C, 4, 0x0000, 0, 0),
+         MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31                    = IOMUX_PAD(0x01BC, 0x000C, 5, 0x0000, 0, 0),
+         MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX                    = IOMUX_PAD(0x01BC, 0x000C, 6, 0x0434, 0, 0),
+
+         MX93_PAD_GPIO_IO00__GPIO2_IO00                           = IOMUX_PAD(0x01C0, 0x0010, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO00__LPI2C3_SDA                           = IOMUX_PAD(0x01C0, 0x0010, 1 | IOMUX_CONFIG_SION, 0x03E4, 0, 0),
+         MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK                     = IOMUX_PAD(0x01C0, 0x0010, 2, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK                    = IOMUX_PAD(0x01C0, 0x0010, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO00__LPSPI6_PCS0                          = IOMUX_PAD(0x01C0, 0x0010, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO00__LPUART5_TX                           = IOMUX_PAD(0x01C0, 0x0010, 5, 0x0434, 1, 0),
+         MX93_PAD_GPIO_IO00__LPI2C5_SDA                           = IOMUX_PAD(0x01C0, 0x0010, 6 | IOMUX_CONFIG_SION, 0x03EC, 0, 0),
+         MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00                     = IOMUX_PAD(0x01C0, 0x0010, 7, 0x036C, 0, 0),
+
+         MX93_PAD_GPIO_IO01__GPIO2_IO01                           = IOMUX_PAD(0x01C4, 0x0014, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO01__LPI2C3_SCL                           = IOMUX_PAD(0x01C4, 0x0014, 1 | IOMUX_CONFIG_SION, 0x03E0, 0, 0),
+         MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00                  = IOMUX_PAD(0x01C4, 0x0014, 2, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE                     = IOMUX_PAD(0x01C4, 0x0014, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO01__LPSPI6_SIN                           = IOMUX_PAD(0x01C4, 0x0014, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO01__LPUART5_RX                           = IOMUX_PAD(0x01C4, 0x0014, 5, 0x0430, 1, 0),
+         MX93_PAD_GPIO_IO01__LPI2C5_SCL                           = IOMUX_PAD(0x01C4, 0x0014, 6 | IOMUX_CONFIG_SION, 0x03E8, 0, 0),
+         MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01                     = IOMUX_PAD(0x01C4, 0x0014, 7, 0x0370, 0, 0),
+
+         MX93_PAD_GPIO_IO02__GPIO2_IO02                           = IOMUX_PAD(0x01C8, 0x0018, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO02__LPI2C4_SDA                           = IOMUX_PAD(0x01C8, 0x0018, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC                   = IOMUX_PAD(0x01C8, 0x0018, 2, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC                  = IOMUX_PAD(0x01C8, 0x0018, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO02__LPSPI6_SOUT                          = IOMUX_PAD(0x01C8, 0x0018, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO02__LPUART5_CTS_B                        = IOMUX_PAD(0x01C8, 0x0018, 5, 0x042C, 1, 0),
+         MX93_PAD_GPIO_IO02__LPI2C6_SDA                           = IOMUX_PAD(0x01C8, 0x0018, 6 | IOMUX_CONFIG_SION, 0x03F4, 0, 0),
+         MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02                     = IOMUX_PAD(0x01C8, 0x0018, 7, 0x0374, 0, 0),
+
+         MX93_PAD_GPIO_IO03__GPIO2_IO03                           = IOMUX_PAD(0x01CC, 0x001C, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO03__LPI2C4_SCL                           = IOMUX_PAD(0x01CC, 0x001C, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC                   = IOMUX_PAD(0x01CC, 0x001C, 2, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC                  = IOMUX_PAD(0x01CC, 0x001C, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO03__LPSPI6_SCK                           = IOMUX_PAD(0x01CC, 0x001C, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO03__LPUART5_RTS_B                        = IOMUX_PAD(0x01CC, 0x001C, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO03__LPI2C6_SCL                           = IOMUX_PAD(0x01CC, 0x001C, 6 | IOMUX_CONFIG_SION, 0x03F0, 0, 0),
+         MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03                     = IOMUX_PAD(0x01CC, 0x001C, 7, 0x0378, 0, 0),
+
+         MX93_PAD_GPIO_IO04__GPIO2_IO04                           = IOMUX_PAD(0x01D0, 0x0020, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO04__TPM3_CH0                             = IOMUX_PAD(0x01D0, 0x0020, 1, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO04__PDM_CLK                              = IOMUX_PAD(0x01D0, 0x0020, 2, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00                 = IOMUX_PAD(0x01D0, 0x0020, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO04__LPSPI7_PCS0                          = IOMUX_PAD(0x01D0, 0x0020, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO04__LPUART6_TX                           = IOMUX_PAD(0x01D0, 0x0020, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO04__LPI2C6_SDA                           = IOMUX_PAD(0x01D0, 0x0020, 6 | IOMUX_CONFIG_SION, 0x03F4, 1, 0),
+         MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04                     = IOMUX_PAD(0x01D0, 0x0020, 7, 0x037C, 0, 0),
+
+         MX93_PAD_GPIO_IO05__GPIO2_IO05                           = IOMUX_PAD(0x01D4, 0x0024, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO05__TPM4_CH0                             = IOMUX_PAD(0x01D4, 0x0024, 1, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00                     = IOMUX_PAD(0x01D4, 0x0024, 2, 0x0438, 0, 0),
+         MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01                 = IOMUX_PAD(0x01D4, 0x0024, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO05__LPSPI7_SIN                           = IOMUX_PAD(0x01D4, 0x0024, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO05__LPUART6_RX                           = IOMUX_PAD(0x01D4, 0x0024, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO05__LPI2C6_SCL                           = IOMUX_PAD(0x01D4, 0x0024, 6 | IOMUX_CONFIG_SION, 0x03F0, 1, 0),
+         MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05                     = IOMUX_PAD(0x01D4, 0x0024, 7, 0x0380, 0, 0),
+
+         MX93_PAD_GPIO_IO06__GPIO2_IO06                           = IOMUX_PAD(0x01D8, 0x0028, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO06__TPM5_CH0                             = IOMUX_PAD(0x01D8, 0x0028, 1, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01                     = IOMUX_PAD(0x01D8, 0x0028, 2, 0x043C, 0, 0),
+         MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02                 = IOMUX_PAD(0x01D8, 0x0028, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO06__LPSPI7_SOUT                          = IOMUX_PAD(0x01D8, 0x0028, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO06__LPUART6_CTS_B                        = IOMUX_PAD(0x01D8, 0x0028, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO06__LPI2C7_SDA                           = IOMUX_PAD(0x01D8, 0x0028, 6 | IOMUX_CONFIG_SION, 0x03FC, 0, 0),
+         MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06                     = IOMUX_PAD(0x01D8, 0x0028, 7, 0x0384, 0, 0),
+
+         MX93_PAD_GPIO_IO07__GPIO2_IO07                           = IOMUX_PAD(0x01DC, 0x002C, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO07__LPSPI3_PCS1                          = IOMUX_PAD(0x01DC, 0x002C, 1, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01                  = IOMUX_PAD(0x01DC, 0x002C, 2, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03                 = IOMUX_PAD(0x01DC, 0x002C, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO07__LPSPI7_SCK                           = IOMUX_PAD(0x01DC, 0x002C, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO07__LPUART6_RTS_B                        = IOMUX_PAD(0x01DC, 0x002C, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO07__LPI2C7_SCL                           = IOMUX_PAD(0x01DC, 0x002C, 6 | IOMUX_CONFIG_SION, 0x03F8, 0, 0),
+         MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07                     = IOMUX_PAD(0x01DC, 0x002C, 7, 0x0388, 0, 0),
+
+         MX93_PAD_GPIO_IO08__GPIO2_IO08                           = IOMUX_PAD(0x01E0, 0x0030, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO08__LPSPI3_PCS0                          = IOMUX_PAD(0x01E0, 0x0030, 1, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02                  = IOMUX_PAD(0x01E0, 0x0030, 2, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04                 = IOMUX_PAD(0x01E0, 0x0030, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO08__TPM6_CH0                             = IOMUX_PAD(0x01E0, 0x0030, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO08__LPUART7_TX                           = IOMUX_PAD(0x01E0, 0x0030, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO08__LPI2C7_SDA                           = IOMUX_PAD(0x01E0, 0x0030, 6 | IOMUX_CONFIG_SION, 0x03FC, 1, 0),
+         MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08                     = IOMUX_PAD(0x01E0, 0x0030, 7, 0x038C, 0, 0),
+
+         MX93_PAD_GPIO_IO09__GPIO2_IO09                           = IOMUX_PAD(0x01E4, 0x0034, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO09__LPSPI3_SIN                           = IOMUX_PAD(0x01E4, 0x0034, 1, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03                  = IOMUX_PAD(0x01E4, 0x0034, 2, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05                 = IOMUX_PAD(0x01E4, 0x0034, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO09__TPM3_EXTCLK                          = IOMUX_PAD(0x01E4, 0x0034, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO09__LPUART7_RX                           = IOMUX_PAD(0x01E4, 0x0034, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO09__LPI2C7_SCL                           = IOMUX_PAD(0x01E4, 0x0034, 6 | IOMUX_CONFIG_SION, 0x03F8, 1, 0),
+         MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09                     = IOMUX_PAD(0x01E4, 0x0034, 7, 0x0390, 0, 0),
+
+         MX93_PAD_GPIO_IO10__GPIO2_IO10                           = IOMUX_PAD(0x01E8, 0x0038, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO10__LPSPI3_SOUT                          = IOMUX_PAD(0x01E8, 0x0038, 1, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04                  = IOMUX_PAD(0x01E8, 0x0038, 2, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06                 = IOMUX_PAD(0x01E8, 0x0038, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO10__TPM4_EXTCLK                          = IOMUX_PAD(0x01E8, 0x0038, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO10__LPUART7_CTS_B                        = IOMUX_PAD(0x01E8, 0x0038, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO10__LPI2C8_SDA                           = IOMUX_PAD(0x01E8, 0x0038, 6 | IOMUX_CONFIG_SION, 0x0404, 0, 0),
+         MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10                     = IOMUX_PAD(0x01E8, 0x0038, 7, 0x0394, 0, 0),
+
+         MX93_PAD_GPIO_IO11__GPIO2_IO11                           = IOMUX_PAD(0x01EC, 0x003C, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO11__LPSPI3_SCK                           = IOMUX_PAD(0x01EC, 0x003C, 1, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05                  = IOMUX_PAD(0x01EC, 0x003C, 2, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07                 = IOMUX_PAD(0x01EC, 0x003C, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO11__TPM5_EXTCLK                          = IOMUX_PAD(0x01EC, 0x003C, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO11__LPUART7_RTS_B                        = IOMUX_PAD(0x01EC, 0x003C, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO11__LPI2C8_SCL                           = IOMUX_PAD(0x01EC, 0x003C, 6 | IOMUX_CONFIG_SION, 0x0400, 0, 0),
+         MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11                     = IOMUX_PAD(0x01EC, 0x003C, 7, 0x0398, 0, 0),
+
+         MX93_PAD_GPIO_IO12__GPIO2_IO12                           = IOMUX_PAD(0x01F0, 0x0040, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO12__TPM3_CH2                             = IOMUX_PAD(0x01F0, 0x0040, 1, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02                     = IOMUX_PAD(0x01F0, 0x0040, 2, 0x0440, 0, 0),
+         MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08                 = IOMUX_PAD(0x01F0, 0x0040, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO12__LPSPI8_PCS0                          = IOMUX_PAD(0x01F0, 0x0040, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO12__LPUART8_TX                           = IOMUX_PAD(0x01F0, 0x0040, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO12__LPI2C8_SDA                           = IOMUX_PAD(0x01F0, 0x0040, 6 | IOMUX_CONFIG_SION, 0x0404, 1, 0),
+         MX93_PAD_GPIO_IO12__SAI3_RX_SYNC                         = IOMUX_PAD(0x01F0, 0x0040, 7, 0x0450, 0, 0),
+
+         MX93_PAD_GPIO_IO13__GPIO2_IO13                           = IOMUX_PAD(0x01F4, 0x0044, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO13__TPM4_CH2                             = IOMUX_PAD(0x01F4, 0x0044, 1, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03                     = IOMUX_PAD(0x01F4, 0x0044, 2, 0x0444, 0, 0),
+         MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09                 = IOMUX_PAD(0x01F4, 0x0044, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO13__LPSPI8_SIN                           = IOMUX_PAD(0x01F4, 0x0044, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO13__LPUART8_RX                           = IOMUX_PAD(0x01F4, 0x0044, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO13__LPI2C8_SCL                           = IOMUX_PAD(0x01F4, 0x0044, 6 | IOMUX_CONFIG_SION, 0x0400, 1, 0),
+         MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13                     = IOMUX_PAD(0x01F4, 0x0044, 7, 0x039C, 0, 0),
+
+         MX93_PAD_GPIO_IO14__GPIO2_IO14                           = IOMUX_PAD(0x01F8, 0x0048, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO14__LPUART3_TX                           = IOMUX_PAD(0x01F8, 0x0048, 1, 0x041C, 0, 0),
+         MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06                  = IOMUX_PAD(0x01F8, 0x0048, 2, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10                 = IOMUX_PAD(0x01F8, 0x0048, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO14__LPSPI8_SOUT                          = IOMUX_PAD(0x01F8, 0x0048, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO14__LPUART8_CTS_B                        = IOMUX_PAD(0x01F8, 0x0048, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO14__LPUART4_TX                           = IOMUX_PAD(0x01F8, 0x0048, 6, 0x0428, 0, 0),
+         MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14                     = IOMUX_PAD(0x01F8, 0x0048, 7, 0x03A0, 0, 0),
+
+         MX93_PAD_GPIO_IO15__GPIO2_IO15                           = IOMUX_PAD(0x01FC, 0x004C, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO15__LPUART3_RX                           = IOMUX_PAD(0x01FC, 0x004C, 1, 0x0418, 0, 0),
+         MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07                  = IOMUX_PAD(0x01FC, 0x004C, 2, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11                 = IOMUX_PAD(0x01FC, 0x004C, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO15__LPSPI8_SCK                           = IOMUX_PAD(0x01FC, 0x004C, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO15__LPUART8_RTS_B                        = IOMUX_PAD(0x01FC, 0x004C, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO15__LPUART4_RX                           = IOMUX_PAD(0x01FC, 0x004C, 6, 0x0424, 0, 0),
+         MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15                     = IOMUX_PAD(0x01FC, 0x004C, 7, 0x03A4, 0, 0),
+
+         MX93_PAD_GPIO_IO16__GPIO2_IO16                           = IOMUX_PAD(0x0200, 0x0050, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO16__SAI3_TX_BCLK                         = IOMUX_PAD(0x0200, 0x0050, 1, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02                     = IOMUX_PAD(0x0200, 0x0050, 2, 0x0440, 1, 0),
+         MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12                 = IOMUX_PAD(0x0200, 0x0050, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO16__LPUART3_CTS_B                        = IOMUX_PAD(0x0200, 0x0050, 4, 0x0414, 0, 0),
+         MX93_PAD_GPIO_IO16__LPSPI4_PCS2                          = IOMUX_PAD(0x0200, 0x0050, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO16__LPUART4_CTS_B                        = IOMUX_PAD(0x0200, 0x0050, 6, 0x0420, 0, 0),
+         MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16                     = IOMUX_PAD(0x0200, 0x0050, 7, 0x03A8, 0, 0),
+
+         MX93_PAD_GPIO_IO17__GPIO2_IO17                           = IOMUX_PAD(0x0204, 0x0054, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO17__SAI3_MCLK                            = IOMUX_PAD(0x0204, 0x0054, 1, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08                  = IOMUX_PAD(0x0204, 0x0054, 2, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13                 = IOMUX_PAD(0x0204, 0x0054, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO17__LPUART3_RTS_B                        = IOMUX_PAD(0x0204, 0x0054, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO17__LPSPI4_PCS1                          = IOMUX_PAD(0x0204, 0x0054, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO17__LPUART4_RTS_B                        = IOMUX_PAD(0x0204, 0x0054, 6, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17                     = IOMUX_PAD(0x0204, 0x0054, 7, 0x03AC, 0, 0),
+
+         MX93_PAD_GPIO_IO18__GPIO2_IO18                           = IOMUX_PAD(0x0208, 0x0058, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO18__SAI3_RX_BCLK                         = IOMUX_PAD(0x0208, 0x0058, 1, 0x044C, 0, 0),
+         MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09                  = IOMUX_PAD(0x0208, 0x0058, 2, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14                 = IOMUX_PAD(0x0208, 0x0058, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO18__LPSPI5_PCS0                          = IOMUX_PAD(0x0208, 0x0058, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO18__LPSPI4_PCS0                          = IOMUX_PAD(0x0208, 0x0058, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO18__TPM5_CH2                             = IOMUX_PAD(0x0208, 0x0058, 6, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18                     = IOMUX_PAD(0x0208, 0x0058, 7, 0x03B0, 0, 0),
+
+         MX93_PAD_GPIO_IO19__GPIO2_IO19                           = IOMUX_PAD(0x020C, 0x005C, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO19__SAI3_RX_SYNC                         = IOMUX_PAD(0x020C, 0x005C, 1, 0x0450, 1, 0),
+         MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03                     = IOMUX_PAD(0x020C, 0x005C, 2, 0x0444, 1, 0),
+         MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15                 = IOMUX_PAD(0x020C, 0x005C, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO19__LPSPI5_SIN                           = IOMUX_PAD(0x020C, 0x005C, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO19__LPSPI4_SIN                           = IOMUX_PAD(0x020C, 0x005C, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO19__TPM6_CH2                             = IOMUX_PAD(0x020C, 0x005C, 6, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO19__SAI3_TX_DATA00                       = IOMUX_PAD(0x020C, 0x005C, 7, 0x0000, 0, 0),
+
+         MX93_PAD_GPIO_IO20__GPIO2_IO20                           = IOMUX_PAD(0x0210, 0x0060, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO20__SAI3_RX_DATA00                       = IOMUX_PAD(0x0210, 0x0060, 1, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00                     = IOMUX_PAD(0x0210, 0x0060, 2, 0x0438, 1, 0),
+         MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16                 = IOMUX_PAD(0x0210, 0x0060, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO20__LPSPI5_SOUT                          = IOMUX_PAD(0x0210, 0x0060, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO20__LPSPI4_SOUT                          = IOMUX_PAD(0x0210, 0x0060, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO20__TPM3_CH1                             = IOMUX_PAD(0x0210, 0x0060, 6, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20                     = IOMUX_PAD(0x0210, 0x0060, 7, 0x03B4, 0, 0),
+
+         MX93_PAD_GPIO_IO21__GPIO2_IO21                           = IOMUX_PAD(0x0214, 0x0064, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO21__SAI3_TX_DATA00                       = IOMUX_PAD(0x0214, 0x0064, 1, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO21__PDM_CLK                              = IOMUX_PAD(0x0214, 0x0064, 2, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17                 = IOMUX_PAD(0x0214, 0x0064, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO21__LPSPI5_SCK                           = IOMUX_PAD(0x0214, 0x0064, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO21__LPSPI4_SCK                           = IOMUX_PAD(0x0214, 0x0064, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO21__TPM4_CH1                             = IOMUX_PAD(0x0214, 0x0064, 6, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO21__SAI3_RX_BCLK                         = IOMUX_PAD(0x0214, 0x0064, 7, 0x044C, 1, 0),
+
+         MX93_PAD_GPIO_IO22__GPIO2_IO22                           = IOMUX_PAD(0x0218, 0x0068, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO22__USDHC3_CLK                           = IOMUX_PAD(0x0218, 0x0068, 1, 0x0458, 0, 0),
+         MX93_PAD_GPIO_IO22__SPDIF_IN                             = IOMUX_PAD(0x0218, 0x0068, 2, 0x0454, 0, 0),
+         MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18                 = IOMUX_PAD(0x0218, 0x0068, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO22__TPM5_CH1                             = IOMUX_PAD(0x0218, 0x0068, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO22__TPM6_EXTCLK                          = IOMUX_PAD(0x0218, 0x0068, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO22__LPI2C5_SDA                           = IOMUX_PAD(0x0218, 0x0068, 6 | IOMUX_CONFIG_SION, 0x03EC, 1, 0),
+         MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22                     = IOMUX_PAD(0x0218, 0x0068, 7, 0x03B8, 0, 0),
+
+         MX93_PAD_GPIO_IO23__GPIO2_IO23                           = IOMUX_PAD(0x021C, 0x006C, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO23__USDHC3_CMD                           = IOMUX_PAD(0x021C, 0x006C, 1, 0x045C, 0, 0),
+         MX93_PAD_GPIO_IO23__SPDIF_OUT                            = IOMUX_PAD(0x021C, 0x006C, 2, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19                 = IOMUX_PAD(0x021C, 0x006C, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO23__TPM6_CH1                             = IOMUX_PAD(0x021C, 0x006C, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO23__LPI2C5_SCL                           = IOMUX_PAD(0x021C, 0x006C, 6 | IOMUX_CONFIG_SION, 0x03E8, 1, 0),
+         MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23                     = IOMUX_PAD(0x021C, 0x006C, 7, 0x03BC, 0, 0),
+
+         MX93_PAD_GPIO_IO24__GPIO2_IO24                           = IOMUX_PAD(0x0220, 0x0070, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO24__USDHC3_DATA0                         = IOMUX_PAD(0x0220, 0x0070, 1, 0x0460, 0, 0),
+         MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20                 = IOMUX_PAD(0x0220, 0x0070, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO24__TPM3_CH3                             = IOMUX_PAD(0x0220, 0x0070, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO24__JTAG_MUX_TDO                         = IOMUX_PAD(0x0220, 0x0070, 5, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO24__LPSPI6_PCS1                          = IOMUX_PAD(0x0220, 0x0070, 6, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24                     = IOMUX_PAD(0x0220, 0x0070, 7, 0x03C0, 0, 0),
+
+         MX93_PAD_GPIO_IO25__GPIO2_IO25                           = IOMUX_PAD(0x0224, 0x0074, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO25__USDHC3_DATA1                         = IOMUX_PAD(0x0224, 0x0074, 1, 0x0464, 0, 0),
+         MX93_PAD_GPIO_IO25__CAN2_TX                              = IOMUX_PAD(0x0224, 0x0074, 2, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21                 = IOMUX_PAD(0x0224, 0x0074, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO25__TPM4_CH3                             = IOMUX_PAD(0x0224, 0x0074, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO25__JTAG_MUX_TCK                         = IOMUX_PAD(0x0224, 0x0074, 5, 0x03D4, 1, 0),
+         MX93_PAD_GPIO_IO25__LPSPI7_PCS1                          = IOMUX_PAD(0x0224, 0x0074, 6, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25                     = IOMUX_PAD(0x0224, 0x0074, 7, 0x03C4, 0, 0),
+
+         MX93_PAD_GPIO_IO26__GPIO2_IO26                           = IOMUX_PAD(0x0228, 0x0078, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO26__USDHC3_DATA2                         = IOMUX_PAD(0x0228, 0x0078, 1, 0x0468, 0, 0),
+         MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01                     = IOMUX_PAD(0x0228, 0x0078, 2, 0x043C, 1, 0),
+         MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22                 = IOMUX_PAD(0x0228, 0x0078, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO26__TPM5_CH3                             = IOMUX_PAD(0x0228, 0x0078, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO26__JTAG_MUX_TDI                         = IOMUX_PAD(0x0228, 0x0078, 5, 0x03D8, 1, 0),
+         MX93_PAD_GPIO_IO26__LPSPI8_PCS1                          = IOMUX_PAD(0x0228, 0x0078, 6, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO26__SAI3_TX_SYNC                         = IOMUX_PAD(0x0228, 0x0078, 7, 0x0000, 0, 0),
+
+         MX93_PAD_GPIO_IO27__GPIO2_IO27                           = IOMUX_PAD(0x022C, 0x007C, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO27__USDHC3_DATA3                         = IOMUX_PAD(0x022C, 0x007C, 1, 0x046C, 0, 0),
+         MX93_PAD_GPIO_IO27__CAN2_RX                              = IOMUX_PAD(0x022C, 0x007C, 2, 0x0364, 1, 0),
+         MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23                 = IOMUX_PAD(0x022C, 0x007C, 3, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO27__TPM6_CH3                             = IOMUX_PAD(0x022C, 0x007C, 4, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO27__JTAG_MUX_TMS                         = IOMUX_PAD(0x022C, 0x007C, 5, 0x03DC, 1, 0),
+         MX93_PAD_GPIO_IO27__LPSPI5_PCS1                          = IOMUX_PAD(0x022C, 0x007C, 6, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27                     = IOMUX_PAD(0x022C, 0x007C, 7, 0x03C8, 0, 0),
+
+         MX93_PAD_GPIO_IO28__GPIO2_IO28                           = IOMUX_PAD(0x0230, 0x0080, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO28__LPI2C3_SDA                           = IOMUX_PAD(0x0230, 0x0080, 1 | IOMUX_CONFIG_SION, 0x03E4, 1, 0),
+         MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28                     = IOMUX_PAD(0x0230, 0x0080, 7, 0x0000, 0, 0),
+
+         MX93_PAD_GPIO_IO29__GPIO2_IO29                           = IOMUX_PAD(0x0234, 0x0084, 0, 0x0000, 0, 0),
+         MX93_PAD_GPIO_IO29__LPI2C3_SCL                           = IOMUX_PAD(0x0234, 0x0084, 1 | IOMUX_CONFIG_SION, 0x03E0, 1, 0),
+         MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29                     = IOMUX_PAD(0x0234, 0x0084, 7, 0x0000, 0, 0),
+
+         MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1                   = IOMUX_PAD(0x0238, 0x0088, 0, 0x0000, 0, 0),
+         MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26                     = IOMUX_PAD(0x0238, 0x0088, 4, 0x0000, 0, 0),
+         MX93_PAD_CCM_CLKO1__GPIO3_IO26                           = IOMUX_PAD(0x0238, 0x0088, 5, 0x0000, 0, 0),
+         MX93_PAD_CCM_CLKO2__GPIO3_IO27                           = IOMUX_PAD(0x023C, 0x008C, 5, 0x0000, 0, 0),
+
+         MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2                   = IOMUX_PAD(0x023C, 0x008C, 0, 0x0000, 0, 0),
+         MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27                     = IOMUX_PAD(0x023C, 0x008C, 4, 0x03C8, 1, 0),
+
+         MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3                   = IOMUX_PAD(0x0240, 0x0090, 0, 0x0000, 0, 0),
+         MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28                     = IOMUX_PAD(0x0240, 0x0090, 4, 0x0000, 0, 0),
+         MX93_PAD_CCM_CLKO3__GPIO4_IO28                           = IOMUX_PAD(0x0240, 0x0090, 5, 0x0000, 0, 0),
+
+         MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4                   = IOMUX_PAD(0x0244, 0x0094, 0, 0x0000, 0, 0),
+         MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29                     = IOMUX_PAD(0x0244, 0x0094, 4, 0x0000, 0, 0),
+         MX93_PAD_CCM_CLKO4__GPIO4_IO29                           = IOMUX_PAD(0x0244, 0x0094, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET1_MDC__ENET_QOS_MDC                         = IOMUX_PAD(0x0248, 0x0098, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET1_MDC__LPUART3_DCB_B                        = IOMUX_PAD(0x0248, 0x0098, 1, 0x0000, 0, 0),
+         MX93_PAD_ENET1_MDC__I3C2_SCL                             = IOMUX_PAD(0x0248, 0x0098, 2 | IOMUX_CONFIG_SION, 0x03CC, 0, 0),
+         MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1                      = IOMUX_PAD(0x0248, 0x0098, 3, 0x0000, 0, 0),
+         MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00                     = IOMUX_PAD(0x0248, 0x0098, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET1_MDC__GPIO4_IO00                           = IOMUX_PAD(0x0248, 0x0098, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO                       = IOMUX_PAD(0x024C, 0x009C, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET1_MDIO__LPUART3_RIN_B                       = IOMUX_PAD(0x024C, 0x009C, 1, 0x0000, 0, 0),
+         MX93_PAD_ENET1_MDIO__I3C2_SDA                            = IOMUX_PAD(0x024C, 0x009C, 2 | IOMUX_CONFIG_SION, 0x03D0, 0, 0),
+         MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1                    = IOMUX_PAD(0x024C, 0x009C, 3, 0x0000, 0, 0),
+         MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01                    = IOMUX_PAD(0x024C, 0x009C, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET1_MDIO__GPIO4_IO01                          = IOMUX_PAD(0x024C, 0x009C, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3                   = IOMUX_PAD(0x0250, 0x00A0, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TD3__CAN2_TX                              = IOMUX_PAD(0x0250, 0x00A0, 2, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2                      = IOMUX_PAD(0x0250, 0x00A0, 3, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02                     = IOMUX_PAD(0x0250, 0x00A0, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TD3__GPIO4_IO02                           = IOMUX_PAD(0x0250, 0x00A0, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2                   = IOMUX_PAD(0x0254, 0x00A4, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK  = IOMUX_PAD(0x0254, 0x00A4, 1, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TD2__CAN2_RX                              = IOMUX_PAD(0x0254, 0x00A4, 2, 0x0364, 2, 0),
+         MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2                      = IOMUX_PAD(0x0254, 0x00A4, 3, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03                     = IOMUX_PAD(0x0254, 0x00A4, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TD2__GPIO4_IO03                           = IOMUX_PAD(0x0254, 0x00A4, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1                   = IOMUX_PAD(0x0258, 0x00A8, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TD1__LPUART3_RTS_B                        = IOMUX_PAD(0x0258, 0x00A8, 1, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TD1__I3C2_PUR                             = IOMUX_PAD(0x0258, 0x00A8, 2, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1                      = IOMUX_PAD(0x0258, 0x00A8, 3, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04                     = IOMUX_PAD(0x0258, 0x00A8, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TD1__GPIO4_IO04                           = IOMUX_PAD(0x0258, 0x00A8, 5, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TD1__I3C2_PUR_B                           = IOMUX_PAD(0x0258, 0x00A8, 6, 0x0000, 0, 0),
+
+         MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0                   = IOMUX_PAD(0x025C, 0x00AC, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TD0__LPUART3_TX                           = IOMUX_PAD(0x025C, 0x00AC, 1, 0x041C, 1, 0),
+         MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05                     = IOMUX_PAD(0x025C, 0x00AC, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TD0__GPIO4_IO05                           = IOMUX_PAD(0x025C, 0x00AC, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL             = IOMUX_PAD(0x0260, 0x00B0, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B                     = IOMUX_PAD(0x0260, 0x00B0, 1, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06                  = IOMUX_PAD(0x0260, 0x00B0, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TX_CTL__GPIO4_IO06                        = IOMUX_PAD(0x0260, 0x00B0, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK   = IOMUX_PAD(0x0264, 0x00B4, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER                       = IOMUX_PAD(0x0264, 0x00B4, 1, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07                     = IOMUX_PAD(0x0264, 0x00B4, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET1_TXC__GPIO4_IO07                           = IOMUX_PAD(0x0264, 0x00B4, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL             = IOMUX_PAD(0x0268, 0x00B8, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B                     = IOMUX_PAD(0x0268, 0x00B8, 1, 0x0000, 0, 0),
+         MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2                  = IOMUX_PAD(0x0268, 0x00B8, 3, 0x0000, 0, 0),
+         MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08                  = IOMUX_PAD(0x0268, 0x00B8, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET1_RX_CTL__GPIO4_IO08                        = IOMUX_PAD(0x0268, 0x00B8, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK   = IOMUX_PAD(0x026C, 0x00BC, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER                       = IOMUX_PAD(0x026C, 0x00BC, 1, 0x0000, 0, 0),
+         MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09                     = IOMUX_PAD(0x026C, 0x00BC, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET1_RXC__GPIO4_IO09                           = IOMUX_PAD(0x026C, 0x00BC, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0                   = IOMUX_PAD(0x0270, 0x00C0, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET1_RD0__LPUART3_RX                           = IOMUX_PAD(0x0270, 0x00C0, 1, 0x0418, 1, 0),
+         MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10                     = IOMUX_PAD(0x0270, 0x00C0, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET1_RD0__GPIO4_IO10                           = IOMUX_PAD(0x0270, 0x00C0, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1                   = IOMUX_PAD(0x0274, 0x00C4, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET1_RD1__LPUART3_CTS_B                        = IOMUX_PAD(0x0274, 0x00C4, 1, 0x0414, 1, 0),
+         MX93_PAD_ENET1_RD1__LPTMR2_ALT1                          = IOMUX_PAD(0x0274, 0x00C4, 3, 0x0408, 0, 0),
+         MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11                     = IOMUX_PAD(0x0274, 0x00C4, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET1_RD1__GPIO4_IO11                           = IOMUX_PAD(0x0274, 0x00C4, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2                   = IOMUX_PAD(0x0278, 0x00C8, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET1_RD2__LPTMR2_ALT2                          = IOMUX_PAD(0x0278, 0x00C8, 3, 0x040C, 0, 0),
+         MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12                     = IOMUX_PAD(0x0278, 0x00C8, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET1_RD2__GPIO4_IO12                           = IOMUX_PAD(0x0278, 0x00C8, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3                   = IOMUX_PAD(0x027C, 0x00CC, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER              = IOMUX_PAD(0x027C, 0x00CC, 2, 0x0000, 0, 0),
+         MX93_PAD_ENET1_RD3__LPTMR2_ALT3                          = IOMUX_PAD(0x027C, 0x00CC, 3, 0x0410, 0, 0),
+         MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13                     = IOMUX_PAD(0x027C, 0x00CC, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET1_RD3__GPIO4_IO13                           = IOMUX_PAD(0x027C, 0x00CC, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET2_MDC__ENET1_MDC                            = IOMUX_PAD(0x0280, 0x00D0, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET2_MDC__LPUART4_DCB_B                        = IOMUX_PAD(0x0280, 0x00D0, 1, 0x0000, 0, 0),
+         MX93_PAD_ENET2_MDC__SAI2_RX_SYNC                         = IOMUX_PAD(0x0280, 0x00D0, 2, 0x0000, 0, 0),
+         MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14                     = IOMUX_PAD(0x0280, 0x00D0, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET2_MDC__GPIO4_IO14                           = IOMUX_PAD(0x0280, 0x00D0, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET2_MDIO__ENET1_MDIO                          = IOMUX_PAD(0x0284, 0x00D4, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET2_MDIO__LPUART4_RIN_B                       = IOMUX_PAD(0x0284, 0x00D4, 1, 0x0000, 0, 0),
+         MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK                        = IOMUX_PAD(0x0284, 0x00D4, 2, 0x0000, 0, 0),
+         MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15                    = IOMUX_PAD(0x0284, 0x00D4, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET2_MDIO__GPIO4_IO15                          = IOMUX_PAD(0x0284, 0x00D4, 5, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TD3__SAI2_RX_DATA00                       = IOMUX_PAD(0x0288, 0x00D8, 2, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16                     = IOMUX_PAD(0x0288, 0x00D8, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TD3__GPIO4_IO16                           = IOMUX_PAD(0x0288, 0x00D8, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3                      = IOMUX_PAD(0x0288, 0x00D8, 0, 0x0000, 0, 0),
+
+         MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2                      = IOMUX_PAD(0x028C, 0x00DC, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TD2__ENET1_TX_CLK                         = IOMUX_PAD(0x028C, 0x00DC, 1, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TD2__SAI2_RX_DATA01                       = IOMUX_PAD(0x028C, 0x00DC, 2, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17                     = IOMUX_PAD(0x028C, 0x00DC, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TD2__GPIO4_IO17                           = IOMUX_PAD(0x028C, 0x00DC, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1                      = IOMUX_PAD(0x0290, 0x00E0, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TD1__LPUART4_RTS_B                        = IOMUX_PAD(0x0290, 0x00E0, 1, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TD1__SAI2_RX_DATA02                       = IOMUX_PAD(0x0290, 0x00E0, 2, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18                     = IOMUX_PAD(0x0290, 0x00E0, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TD1__GPIO4_IO18                           = IOMUX_PAD(0x0290, 0x00E0, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0                      = IOMUX_PAD(0x0294, 0x00E4, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TD0__LPUART4_TX                           = IOMUX_PAD(0x0294, 0x00E4, 1, 0x0428, 1, 0),
+         MX93_PAD_ENET2_TD0__SAI2_RX_DATA03                       = IOMUX_PAD(0x0294, 0x00E4, 2, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19                     = IOMUX_PAD(0x0294, 0x00E4, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TD0__GPIO4_IO19                           = IOMUX_PAD(0x0294, 0x00E4, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL                = IOMUX_PAD(0x0298, 0x00E8, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B                     = IOMUX_PAD(0x0298, 0x00E8, 1, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC                      = IOMUX_PAD(0x0298, 0x00E8, 2, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20                  = IOMUX_PAD(0x0298, 0x00E8, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TX_CTL__GPIO4_IO20                        = IOMUX_PAD(0x0298, 0x00E8, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC                      = IOMUX_PAD(0x029C, 0x00EC, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TXC__ENET1_TX_ER                          = IOMUX_PAD(0x029C, 0x00EC, 1, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TXC__SAI2_TX_BCLK                         = IOMUX_PAD(0x029C, 0x00EC, 2, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21                     = IOMUX_PAD(0x029C, 0x00EC, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET2_TXC__GPIO4_IO21                           = IOMUX_PAD(0x029C, 0x00EC, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL                = IOMUX_PAD(0x02A0, 0x00F0, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B                     = IOMUX_PAD(0x02A0, 0x00F0, 1, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00                    = IOMUX_PAD(0x02A0, 0x00F0, 2, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22                  = IOMUX_PAD(0x02A0, 0x00F0, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RX_CTL__GPIO4_IO22                        = IOMUX_PAD(0x02A0, 0x00F0, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC                      = IOMUX_PAD(0x02A4, 0x00F4, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RXC__ENET1_RX_ER                          = IOMUX_PAD(0x02A4, 0x00F4, 1, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RXC__SAI2_TX_DATA01                       = IOMUX_PAD(0x02A4, 0x00F4, 2, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23                     = IOMUX_PAD(0x02A4, 0x00F4, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RXC__GPIO4_IO23                           = IOMUX_PAD(0x02A4, 0x00F4, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0                      = IOMUX_PAD(0x02A8, 0x00F8, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RD0__LPUART4_RX                           = IOMUX_PAD(0x02A8, 0x00F8, 1, 0x0424, 1, 0),
+         MX93_PAD_ENET2_RD0__SAI2_TX_DATA02                       = IOMUX_PAD(0x02A8, 0x00F8, 2, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24                     = IOMUX_PAD(0x02A8, 0x00F8, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RD0__GPIO4_IO24                           = IOMUX_PAD(0x02A8, 0x00F8, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1                      = IOMUX_PAD(0x02AC, 0x00FC, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RD1__SPDIF_IN                             = IOMUX_PAD(0x02AC, 0x00FC, 1, 0x0454, 1, 0),
+         MX93_PAD_ENET2_RD1__SAI2_TX_DATA03                       = IOMUX_PAD(0x02AC, 0x00FC, 2, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25                     = IOMUX_PAD(0x02AC, 0x00FC, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RD1__GPIO4_IO25                           = IOMUX_PAD(0x02AC, 0x00FC, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2                      = IOMUX_PAD(0x02B0, 0x0100, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RD2__LPUART4_CTS_B                        = IOMUX_PAD(0x02B0, 0x0100, 1, 0x0420, 1, 0),
+         MX93_PAD_ENET2_RD2__SAI2_MCLK                            = IOMUX_PAD(0x02B0, 0x0100, 2, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RD2__MQS2_RIGHT                           = IOMUX_PAD(0x02B0, 0x0100, 3, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26                     = IOMUX_PAD(0x02B0, 0x0100, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RD2__GPIO4_IO26                           = IOMUX_PAD(0x02B0, 0x0100, 5, 0x0000, 0, 0),
+
+         MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3                      = IOMUX_PAD(0x02B4, 0x0104, 0, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RD3__SPDIF_OUT                            = IOMUX_PAD(0x02B4, 0x0104, 1, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RD3__SPDIF_IN                             = IOMUX_PAD(0x02B4, 0x0104, 2, 0x0454, 2, 0),
+         MX93_PAD_ENET2_RD3__MQS2_LEFT                            = IOMUX_PAD(0x02B4, 0x0104, 3, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27                     = IOMUX_PAD(0x02B4, 0x0104, 4, 0x0000, 0, 0),
+         MX93_PAD_ENET2_RD3__GPIO4_IO27                           = IOMUX_PAD(0x02B4, 0x0104, 5, 0x0000, 0, 0),
+         MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08                       = IOMUX_PAD(0x02B8, 0x0108, 4, 0x038C, 1, 0),
+         MX93_PAD_SD1_CLK__GPIO3_IO08                             = IOMUX_PAD(0x02B8, 0x0108, 5, 0x0000, 0, 0),
+
+         MX93_PAD_SD1_CLK__USDHC1_CLK                             = IOMUX_PAD(0x02B8, 0x0108, 0, 0x0000, 0, 0),
+
+         MX93_PAD_SD1_CMD__USDHC1_CMD                             = IOMUX_PAD(0x02BC, 0x010C, 0, 0x0000, 0, 0),
+         MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09                       = IOMUX_PAD(0x02BC, 0x010C, 4, 0x0390, 1, 0),
+         MX93_PAD_SD1_CMD__GPIO3_IO09                             = IOMUX_PAD(0x02BC, 0x010C, 5, 0x0000, 0, 0),
+
+         MX93_PAD_SD1_DATA0__USDHC1_DATA0                         = IOMUX_PAD(0x02C0, 0x0110, 0, 0x0000, 0, 0),
+         MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10                     = IOMUX_PAD(0x02C0, 0x0110, 4, 0x0394, 1, 0),
+         MX93_PAD_SD1_DATA0__GPIO3_IO10                           = IOMUX_PAD(0x02C0, 0x0110, 5, 0x0000, 0, 0),
+
+         MX93_PAD_SD1_DATA1__USDHC1_DATA1                         = IOMUX_PAD(0x02C4, 0x0114, 0, 0x0000, 0, 0),
+         MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11                     = IOMUX_PAD(0x02C4, 0x0114, 4, 0x0398, 1, 0),
+         MX93_PAD_SD1_DATA1__GPIO3_IO11                           = IOMUX_PAD(0x02C4, 0x0114, 5, 0x0000, 0, 0),
+         MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT                = IOMUX_PAD(0x02C4, 0x0114, 6, 0x0000, 0, 0),
+
+         MX93_PAD_SD1_DATA2__USDHC1_DATA2                         = IOMUX_PAD(0x02C8, 0x0118, 0, 0x0000, 0, 0),
+         MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12                     = IOMUX_PAD(0x02C8, 0x0118, 4, 0x0000, 0, 0),
+         MX93_PAD_SD1_DATA2__GPIO3_IO12                           = IOMUX_PAD(0x02C8, 0x0118, 5, 0x0000, 0, 0),
+         MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY              = IOMUX_PAD(0x02C8, 0x0118, 6, 0x0000, 0, 0),
+
+         MX93_PAD_SD1_DATA3__USDHC1_DATA3                         = IOMUX_PAD(0x02CC, 0x011C, 0, 0x0000, 0, 0),
+         MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B                     = IOMUX_PAD(0x02CC, 0x011C, 1, 0x0000, 0, 0),
+         MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13                     = IOMUX_PAD(0x02CC, 0x011C, 4, 0x039C, 1, 0),
+         MX93_PAD_SD1_DATA3__GPIO3_IO13                           = IOMUX_PAD(0x02CC, 0x011C, 5, 0x0000, 0, 0),
+
+         MX93_PAD_SD1_DATA4__USDHC1_DATA4                         = IOMUX_PAD(0x02D0, 0x0120, 0, 0x0000, 0, 0),
+         MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04                    = IOMUX_PAD(0x02D0, 0x0120, 1, 0x0000, 0, 0),
+         MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14                     = IOMUX_PAD(0x02D0, 0x0120, 4, 0x03A0, 1, 0),
+         MX93_PAD_SD1_DATA4__GPIO3_IO14                           = IOMUX_PAD(0x02D0, 0x0120, 5, 0x0000, 0, 0),
+
+         MX93_PAD_SD1_DATA5__USDHC1_DATA5                         = IOMUX_PAD(0x02D4, 0x0124, 0, 0x0000, 0, 0),
+         MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05                    = IOMUX_PAD(0x02D4, 0x0124, 1, 0x0000, 0, 0),
+         MX93_PAD_SD1_DATA5__USDHC1_RESET_B                       = IOMUX_PAD(0x02D4, 0x0124, 2, 0x0000, 0, 0),
+         MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15                     = IOMUX_PAD(0x02D4, 0x0124, 4, 0x03A4, 1, 0),
+         MX93_PAD_SD1_DATA5__GPIO3_IO15                           = IOMUX_PAD(0x02D4, 0x0124, 5, 0x0000, 0, 0),
+
+         MX93_PAD_SD1_DATA6__USDHC1_DATA6                         = IOMUX_PAD(0x02D8, 0x0128, 0, 0x0000, 0, 0),
+         MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06                    = IOMUX_PAD(0x02D8, 0x0128, 1, 0x0000, 0, 0),
+         MX93_PAD_SD1_DATA6__USDHC1_CD_B                          = IOMUX_PAD(0x02D8, 0x0128, 2, 0x0000, 0, 0),
+         MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16                     = IOMUX_PAD(0x02D8, 0x0128, 4, 0x03A8, 1, 0),
+         MX93_PAD_SD1_DATA6__GPIO3_IO16                           = IOMUX_PAD(0x02D8, 0x0128, 5, 0x0000, 0, 0),
+
+         MX93_PAD_SD1_DATA7__USDHC1_DATA7                         = IOMUX_PAD(0x02DC, 0x012C, 0, 0x0000, 0, 0),
+         MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07                    = IOMUX_PAD(0x02DC, 0x012C, 1, 0x0000, 0, 0),
+         MX93_PAD_SD1_DATA7__USDHC1_WP                            = IOMUX_PAD(0x02DC, 0x012C, 2, 0x0000, 0, 0),
+         MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17                     = IOMUX_PAD(0x02DC, 0x012C, 4, 0x03AC, 1, 0),
+         MX93_PAD_SD1_DATA7__GPIO3_IO17                           = IOMUX_PAD(0x02DC, 0x012C, 5, 0x0000, 0, 0),
+
+         MX93_PAD_SD1_STROBE__USDHC1_STROBE                       = IOMUX_PAD(0x02E0, 0x0130, 0, 0x0000, 0, 0),
+         MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS                      = IOMUX_PAD(0x02E0, 0x0130, 1, 0x0000, 0, 0),
+         MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18                    = IOMUX_PAD(0x02E0, 0x0130, 4, 0x03B0, 1, 0),
+         MX93_PAD_SD1_STROBE__GPIO3_IO18                          = IOMUX_PAD(0x02E0, 0x0130, 5, 0x0000, 0, 0),
+
+         MX93_PAD_SD2_VSELECT__USDHC2_VSELECT                     = IOMUX_PAD(0x02E4, 0x0134, 0, 0x0000, 0, 0),
+         MX93_PAD_SD2_VSELECT__USDHC2_WP                          = IOMUX_PAD(0x02E4, 0x0134, 1, 0x0000, 0, 0),
+         MX93_PAD_SD2_VSELECT__LPTMR2_ALT3                        = IOMUX_PAD(0x02E4, 0x0134, 2, 0x0410, 1, 0),
+         MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19                   = IOMUX_PAD(0x02E4, 0x0134, 4, 0x0000, 0, 0),
+         MX93_PAD_SD2_VSELECT__GPIO3_IO19                         = IOMUX_PAD(0x02E4, 0x0134, 5, 0x0000, 0, 0),
+         MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1              = IOMUX_PAD(0x02E4, 0x0134, 6, 0x0368, 0, 0),
+
+         MX93_PAD_SD3_CLK__USDHC3_CLK                             = IOMUX_PAD(0x02E8, 0x0138, 0, 0x0458, 1, 0),
+         MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK                        = IOMUX_PAD(0x02E8, 0x0138, 1, 0x0000, 0, 0),
+         MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20                       = IOMUX_PAD(0x02E8, 0x0138, 4, 0x03B4, 1, 0),
+         MX93_PAD_SD3_CLK__GPIO3_IO20                             = IOMUX_PAD(0x02E8, 0x0138, 5, 0x0000, 0, 0),
+
+         MX93_PAD_SD3_CMD__USDHC3_CMD                             = IOMUX_PAD(0x02EC, 0x013C, 0, 0x045C, 1, 0),
+         MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B                       = IOMUX_PAD(0x02EC, 0x013C, 1, 0x0000, 0, 0),
+         MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21                       = IOMUX_PAD(0x02EC, 0x013C, 4, 0x0000, 0, 0),
+         MX93_PAD_SD3_CMD__GPIO3_IO21                             = IOMUX_PAD(0x02EC, 0x013C, 5, 0x0000, 0, 0),
+
+         MX93_PAD_SD3_DATA0__USDHC3_DATA0                         = IOMUX_PAD(0x02F0, 0x0140, 0, 0x0460, 1, 0),
+         MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00                    = IOMUX_PAD(0x02F0, 0x0140, 1, 0x0000, 0, 0),
+         MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22                     = IOMUX_PAD(0x02F0, 0x0140, 4, 0x03B8, 1, 0),
+         MX93_PAD_SD3_DATA0__GPIO3_IO22                           = IOMUX_PAD(0x02F0, 0x0140, 5, 0x0000, 0, 0),
+
+         MX93_PAD_SD3_DATA1__USDHC3_DATA1                         = IOMUX_PAD(0x02F4, 0x0144, 0, 0x0464, 1, 0),
+         MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01                    = IOMUX_PAD(0x02F4, 0x0144, 1, 0x0000, 0, 0),
+         MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23                     = IOMUX_PAD(0x02F4, 0x0144, 4, 0x03BC, 1, 0),
+         MX93_PAD_SD3_DATA1__GPIO3_IO23                           = IOMUX_PAD(0x02F4, 0x0144, 5, 0x0000, 0, 0),
+
+         MX93_PAD_SD3_DATA2__USDHC3_DATA2                         = IOMUX_PAD(0x02F8, 0x0148, 0, 0x0468, 1, 0),
+         MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02                    = IOMUX_PAD(0x02F8, 0x0148, 1, 0x0000, 0, 0),
+         MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24                     = IOMUX_PAD(0x02F8, 0x0148, 4, 0x03C0, 1, 0),
+         MX93_PAD_SD3_DATA2__GPIO3_IO24                           = IOMUX_PAD(0x02F8, 0x0148, 5, 0x0000, 0, 0),
+
+         MX93_PAD_SD3_DATA3__USDHC3_DATA3                         = IOMUX_PAD(0x02FC, 0x014C, 0, 0x046C, 1, 0),
+         MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03                    = IOMUX_PAD(0x02FC, 0x014C, 1, 0x0000, 0, 0),
+         MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25                     = IOMUX_PAD(0x02FC, 0x014C, 4, 0x03C4, 1, 0),
+         MX93_PAD_SD3_DATA3__GPIO3_IO25                           = IOMUX_PAD(0x02FC, 0x014C, 5, 0x0000, 0, 0),
+
+         MX93_PAD_SD2_CD_B__USDHC2_CD_B                           = IOMUX_PAD(0x0300, 0x0150, 0, 0x0000, 0, 0),
+         MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN               = IOMUX_PAD(0x0300, 0x0150, 1, 0x0000, 0, 0),
+         MX93_PAD_SD2_CD_B__I3C2_SCL                              = IOMUX_PAD(0x0300, 0x0150, 2 | IOMUX_CONFIG_SION, 0x03CC, 1, 0),
+         MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00                      = IOMUX_PAD(0x0300, 0x0150, 4, 0x036C, 1, 0),
+         MX93_PAD_SD2_CD_B__GPIO3_IO00                            = IOMUX_PAD(0x0300, 0x0150, 5, 0x0000, 0, 0),
+
+         MX93_PAD_SD2_CLK__USDHC2_CLK                             = IOMUX_PAD(0x0304, 0x0154, 0, 0x0000, 0, 0),
+         MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT               = IOMUX_PAD(0x0304, 0x0154, 1, 0x0000, 0, 0),
+         MX93_PAD_SD2_CLK__I3C2_SDA                               = IOMUX_PAD(0x0304, 0x0154, 2 | IOMUX_CONFIG_SION, 0x03D0, 1, 0),
+         MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01                       = IOMUX_PAD(0x0304, 0x0154, 4, 0x0370, 1, 0),
+         MX93_PAD_SD2_CLK__GPIO3_IO01                             = IOMUX_PAD(0x0304, 0x0154, 5, 0x0000, 0, 0),
+         MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0                  = IOMUX_PAD(0x0304, 0x0154, 6, 0x0000, 0, 0),
+
+         MX93_PAD_SD2_CMD__USDHC2_CMD                             = IOMUX_PAD(0x0308, 0x0158, 0, 0x0000, 0, 0),
+         MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN                   = IOMUX_PAD(0x0308, 0x0158, 1, 0x0000, 0, 0),
+         MX93_PAD_SD2_CMD__I3C2_PUR                               = IOMUX_PAD(0x0308, 0x0158, 2, 0x0000, 0, 0),
+         MX93_PAD_SD2_CMD__I3C2_PUR_B                             = IOMUX_PAD(0x0308, 0x0158, 3, 0x0000, 0, 0),
+         MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02                       = IOMUX_PAD(0x0308, 0x0158, 4, 0x0374, 1, 0),
+         MX93_PAD_SD2_CMD__GPIO3_IO02                             = IOMUX_PAD(0x0308, 0x0158, 5, 0x0000, 0, 0),
+         MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1                  = IOMUX_PAD(0x0308, 0x0158, 6, 0x0000, 0, 0),
+
+         MX93_PAD_SD2_DATA0__USDHC2_DATA0                         = IOMUX_PAD(0x030C, 0x015C, 0, 0x0000, 0, 0),
+         MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT                = IOMUX_PAD(0x030C, 0x015C, 1, 0x0000, 0, 0),
+         MX93_PAD_SD2_DATA0__CAN2_TX                              = IOMUX_PAD(0x030C, 0x015C, 2, 0x0000, 0, 0),
+         MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03                     = IOMUX_PAD(0x030C, 0x015C, 4, 0x0378, 1, 0),
+         MX93_PAD_SD2_DATA0__GPIO3_IO03                           = IOMUX_PAD(0x030C, 0x015C, 5, 0x0000, 0, 0),
+         MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2                = IOMUX_PAD(0x030C, 0x015C, 6, 0x0000, 0, 0),
+
+         MX93_PAD_SD2_DATA1__USDHC2_DATA1                         = IOMUX_PAD(0x0310, 0x0160, 0, 0x0000, 0, 0),
+         MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN                 = IOMUX_PAD(0x0310, 0x0160, 1, 0x0000, 0, 0),
+         MX93_PAD_SD2_DATA1__CAN2_RX                              = IOMUX_PAD(0x0310, 0x0160, 2, 0x0364, 3, 0),
+         MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04                     = IOMUX_PAD(0x0310, 0x0160, 4, 0x037C, 1, 0),
+         MX93_PAD_SD2_DATA1__GPIO3_IO04                           = IOMUX_PAD(0x0310, 0x0160, 5, 0x0000, 0, 0),
+         MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT                    = IOMUX_PAD(0x0310, 0x0160, 6, 0x0000, 0, 0),
+
+         MX93_PAD_SD2_DATA2__USDHC2_DATA2                         = IOMUX_PAD(0x0314, 0x0164, 0, 0x0000, 0, 0),
+         MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT                = IOMUX_PAD(0x0314, 0x0164, 1, 0x0000, 0, 0),
+         MX93_PAD_SD2_DATA2__MQS2_RIGHT                           = IOMUX_PAD(0x0314, 0x0164, 2, 0x0000, 0, 0),
+         MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05                     = IOMUX_PAD(0x0314, 0x0164, 4, 0x0380, 1, 0),
+         MX93_PAD_SD2_DATA2__GPIO3_IO05                           = IOMUX_PAD(0x0314, 0x0164, 5, 0x0000, 0, 0),
+         MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP                    = IOMUX_PAD(0x0314, 0x0164, 6, 0x0000, 0, 0),
+
+         MX93_PAD_SD2_DATA3__USDHC2_DATA3                         = IOMUX_PAD(0x0318, 0x0168, 0, 0x0000, 0, 0),
+         MX93_PAD_SD2_DATA3__LPTMR2_ALT1                          = IOMUX_PAD(0x0318, 0x0168, 1, 0x0408, 1, 0),
+         MX93_PAD_SD2_DATA3__MQS2_LEFT                            = IOMUX_PAD(0x0318, 0x0168, 2, 0x0000, 0, 0),
+         MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06                     = IOMUX_PAD(0x0318, 0x0168, 4, 0x0384, 1, 0),
+         MX93_PAD_SD2_DATA3__GPIO3_IO06                           = IOMUX_PAD(0x0318, 0x0168, 5, 0x0000, 0, 0),
+         MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET             = IOMUX_PAD(0x0318, 0x0168, 6, 0x0000, 0, 0),
+
+         MX93_PAD_SD2_RESET_B__USDHC2_RESET_B                     = IOMUX_PAD(0x031C, 0x016C, 0, 0x0000, 0, 0),
+         MX93_PAD_SD2_RESET_B__LPTMR2_ALT2                        = IOMUX_PAD(0x031C, 0x016C, 1, 0x040C, 1, 0),
+         MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07                   = IOMUX_PAD(0x031C, 0x016C, 4, 0x0388, 1, 0),
+         MX93_PAD_SD2_RESET_B__GPIO3_IO07                         = IOMUX_PAD(0x031C, 0x016C, 5, 0x0000, 0, 0),
+         MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET          = IOMUX_PAD(0x031C, 0x016C, 6, 0x0000, 0, 0),
+
+         MX93_PAD_I2C1_SCL__LPI2C1_SCL                            = IOMUX_PAD(0x0320, 0x0170, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+         MX93_PAD_I2C1_SCL__I3C1_SCL                              = IOMUX_PAD(0x0320, 0x0170, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+         MX93_PAD_I2C1_SCL__LPUART1_DCB_B                         = IOMUX_PAD(0x0320, 0x0170, 2, 0x0000, 0, 0),
+         MX93_PAD_I2C1_SCL__TPM2_CH0                              = IOMUX_PAD(0x0320, 0x0170, 3, 0x0000, 0, 0),
+         MX93_PAD_I2C1_SCL__GPIO1_IO00                            = IOMUX_PAD(0x0320, 0x0170, 5, 0x0000, 0, 0),
+
+         MX93_PAD_I2C1_SDA__LPI2C1_SDA                            = IOMUX_PAD(0x0324, 0x0174, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+         MX93_PAD_I2C1_SDA__I3C1_SDA                              = IOMUX_PAD(0x0324, 0x0174, 1 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+         MX93_PAD_I2C1_SDA__LPUART1_RIN_B                         = IOMUX_PAD(0x0324, 0x0174, 2, 0x0000, 0, 0),
+         MX93_PAD_I2C1_SDA__TPM2_CH1                              = IOMUX_PAD(0x0324, 0x0174, 3, 0x0000, 0, 0),
+         MX93_PAD_I2C1_SDA__GPIO1_IO01                            = IOMUX_PAD(0x0324, 0x0174, 5, 0x0000, 0, 0),
+
+         MX93_PAD_I2C2_SCL__LPI2C2_SCL                            = IOMUX_PAD(0x0328, 0x0178, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+         MX93_PAD_I2C2_SCL__I3C1_PUR                              = IOMUX_PAD(0x0328, 0x0178, 1, 0x0000, 0, 0),
+         MX93_PAD_I2C2_SCL__LPUART2_DCB_B                         = IOMUX_PAD(0x0328, 0x0178, 2, 0x0000, 0, 0),
+         MX93_PAD_I2C2_SCL__TPM2_CH2                              = IOMUX_PAD(0x0328, 0x0178, 3, 0x0000, 0, 0),
+         MX93_PAD_I2C2_SCL__SAI1_RX_SYNC                          = IOMUX_PAD(0x0328, 0x0178, 4, 0x0000, 0, 0),
+         MX93_PAD_I2C2_SCL__GPIO1_IO02                            = IOMUX_PAD(0x0328, 0x0178, 5, 0x0000, 0, 0),
+         MX93_PAD_I2C2_SCL__I3C1_PUR_B                            = IOMUX_PAD(0x0328, 0x0178, 6, 0x0000, 0, 0),
+
+         MX93_PAD_I2C2_SDA__LPI2C2_SDA                            = IOMUX_PAD(0x032C, 0x017C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+         MX93_PAD_I2C2_SDA__LPUART2_RIN_B                         = IOMUX_PAD(0x032C, 0x017C, 2, 0x0000, 0, 0),
+         MX93_PAD_I2C2_SDA__TPM2_CH3                              = IOMUX_PAD(0x032C, 0x017C, 3, 0x0000, 0, 0),
+         MX93_PAD_I2C2_SDA__SAI1_RX_BCLK                          = IOMUX_PAD(0x032C, 0x017C, 4, 0x0000, 0, 0),
+         MX93_PAD_I2C2_SDA__GPIO1_IO03                            = IOMUX_PAD(0x032C, 0x017C, 5, 0x0000, 0, 0),
+
+         MX93_PAD_UART1_RXD__LPUART1_RX                           = IOMUX_PAD(0x0330, 0x0180, 0, 0x0000, 0, 0),
+         MX93_PAD_UART1_RXD__S400_UART_RX                         = IOMUX_PAD(0x0330, 0x0180, 1, 0x0000, 0, 0),
+         MX93_PAD_UART1_RXD__LPSPI2_SIN                           = IOMUX_PAD(0x0330, 0x0180, 2, 0x0000, 0, 0),
+         MX93_PAD_UART1_RXD__TPM1_CH0                             = IOMUX_PAD(0x0330, 0x0180, 3, 0x0000, 0, 0),
+         MX93_PAD_UART1_RXD__GPIO1_IO04                           = IOMUX_PAD(0x0330, 0x0180, 5, 0x0000, 0, 0),
+
+         MX93_PAD_UART1_TXD__LPUART1_TX                           = IOMUX_PAD(0x0334, 0x0184, 0, 0x0000, 0, 0),
+         MX93_PAD_UART1_TXD__S400_UART_TX                         = IOMUX_PAD(0x0334, 0x0184, 1, 0x0000, 0, 0),
+         MX93_PAD_UART1_TXD__LPSPI2_PCS0                          = IOMUX_PAD(0x0334, 0x0184, 2, 0x0000, 0, 0),
+         MX93_PAD_UART1_TXD__TPM1_CH1                             = IOMUX_PAD(0x0334, 0x0184, 3, 0x0000, 0, 0),
+         MX93_PAD_UART1_TXD__GPIO1_IO05                           = IOMUX_PAD(0x0334, 0x0184, 5, 0x0000, 0, 0),
+
+         MX93_PAD_UART2_RXD__LPUART2_RX                           = IOMUX_PAD(0x0338, 0x0188, 0, 0x0000, 0, 0),
+         MX93_PAD_UART2_RXD__LPUART1_CTS_B                        = IOMUX_PAD(0x0338, 0x0188, 1, 0x0000, 0, 0),
+         MX93_PAD_UART2_RXD__LPSPI2_SOUT                          = IOMUX_PAD(0x0338, 0x0188, 2, 0x0000, 0, 0),
+         MX93_PAD_UART2_RXD__TPM1_CH2                             = IOMUX_PAD(0x0338, 0x0188, 3, 0x0000, 0, 0),
+         MX93_PAD_UART2_RXD__SAI1_MCLK                            = IOMUX_PAD(0x0338, 0x0188, 4, 0x0448, 0, 0),
+         MX93_PAD_UART2_RXD__GPIO1_IO06                           = IOMUX_PAD(0x0338, 0x0188, 5, 0x0000, 0, 0),
+
+         MX93_PAD_UART2_TXD__LPUART2_TX                           = IOMUX_PAD(0x033C, 0x018C, 0, 0x0000, 0, 0),
+         MX93_PAD_UART2_TXD__LPUART1_RTS_B                        = IOMUX_PAD(0x033C, 0x018C, 1, 0x0000, 0, 0),
+         MX93_PAD_UART2_TXD__LPSPI2_SCK                           = IOMUX_PAD(0x033C, 0x018C, 2, 0x0000, 0, 0),
+         MX93_PAD_UART2_TXD__TPM1_CH3                             = IOMUX_PAD(0x033C, 0x018C, 3, 0x0000, 0, 0),
+         MX93_PAD_UART2_TXD__GPIO1_IO07                           = IOMUX_PAD(0x033C, 0x018C, 5, 0x0000, 0, 0),
+
+         MX93_PAD_PDM_CLK__PDM_CLK                                = IOMUX_PAD(0x0340, 0x0190, 0, 0x0000, 0, 0),
+         MX93_PAD_PDM_CLK__MQS1_LEFT                              = IOMUX_PAD(0x0340, 0x0190, 1, 0x0000, 0, 0),
+         MX93_PAD_PDM_CLK__LPTMR1_ALT1                            = IOMUX_PAD(0x0340, 0x0190, 4, 0x0000, 0, 0),
+         MX93_PAD_PDM_CLK__GPIO1_IO08                             = IOMUX_PAD(0x0340, 0x0190, 5, 0x0000, 0, 0),
+         MX93_PAD_PDM_CLK__CAN1_TX                                = IOMUX_PAD(0x0340, 0x0190, 6, 0x0000, 0, 0),
+
+         MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00               = IOMUX_PAD(0x0344, 0x0194, 0, 0x0438, 2, 0),
+         MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT                     = IOMUX_PAD(0x0344, 0x0194, 1, 0x0000, 0, 0),
+         MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1                    = IOMUX_PAD(0x0344, 0x0194, 2, 0x0000, 0, 0),
+         MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK                    = IOMUX_PAD(0x0344, 0x0194, 3, 0x0000, 0, 0),
+         MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2                    = IOMUX_PAD(0x0344, 0x0194, 4, 0x0000, 0, 0),
+         MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09                     = IOMUX_PAD(0x0344, 0x0194, 5, 0x0000, 0, 0),
+         MX93_PAD_PDM_BIT_STREAM0__CAN1_RX                        = IOMUX_PAD(0x0344, 0x0194, 6, 0x0360, 0, 0),
+
+         MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01               = IOMUX_PAD(0x0348, 0x0198, 0, 0x043C, 2, 0),
+         MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI                   = IOMUX_PAD(0x0348, 0x0198, 1, 0x0000, 0, 0),
+         MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1                    = IOMUX_PAD(0x0348, 0x0198, 2, 0x0000, 0, 0),
+         MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK                    = IOMUX_PAD(0x0348, 0x0198, 3, 0x0000, 0, 0),
+         MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3                    = IOMUX_PAD(0x0348, 0x0198, 4, 0x0000, 0, 0),
+         MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10                     = IOMUX_PAD(0x0348, 0x0198, 5, 0x0000, 0, 0),
+         MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1          = IOMUX_PAD(0x0348, 0x0198, 6, 0x0368, 1, 0),
+
+         MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC                         = IOMUX_PAD(0x034C, 0x019C, 0, 0x0000, 0, 0),
+         MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01                       = IOMUX_PAD(0x034C, 0x019C, 1, 0x0000, 0, 0),
+         MX93_PAD_SAI1_TXFS__LPSPI1_PCS0                          = IOMUX_PAD(0x034C, 0x019C, 2, 0x0000, 0, 0),
+         MX93_PAD_SAI1_TXFS__LPUART2_DTR_B                        = IOMUX_PAD(0x034C, 0x019C, 3, 0x0000, 0, 0),
+         MX93_PAD_SAI1_TXFS__MQS1_LEFT                            = IOMUX_PAD(0x034C, 0x019C, 4, 0x0000, 0, 0),
+         MX93_PAD_SAI1_TXFS__GPIO1_IO11                           = IOMUX_PAD(0x034C, 0x019C, 5, 0x0000, 0, 0),
+
+         MX93_PAD_SAI1_TXC__SAI1_TX_BCLK                          = IOMUX_PAD(0x0350, 0x01A0, 0, 0x0000, 0, 0),
+         MX93_PAD_SAI1_TXC__LPUART2_CTS_B                         = IOMUX_PAD(0x0350, 0x01A0, 1, 0x0000, 0, 0),
+         MX93_PAD_SAI1_TXC__LPSPI1_SIN                            = IOMUX_PAD(0x0350, 0x01A0, 2, 0x0000, 0, 0),
+         MX93_PAD_SAI1_TXC__LPUART1_DSR_B                         = IOMUX_PAD(0x0350, 0x01A0, 3, 0x0000, 0, 0),
+         MX93_PAD_SAI1_TXC__CAN1_RX                               = IOMUX_PAD(0x0350, 0x01A0, 4, 0x0360, 1, 0),
+         MX93_PAD_SAI1_TXC__GPIO1_IO12                            = IOMUX_PAD(0x0350, 0x01A0, 5, 0x0000, 0, 0),
+
+         MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00                       = IOMUX_PAD(0x0354, 0x01A4, 0, 0x0000, 0, 0),
+         MX93_PAD_SAI1_TXD0__LPUART2_RTS_B                        = IOMUX_PAD(0x0354, 0x01A4, 1, 0x0000, 0, 0),
+         MX93_PAD_SAI1_TXD0__LPSPI1_SCK                           = IOMUX_PAD(0x0354, 0x01A4, 2, 0x0000, 0, 0),
+         MX93_PAD_SAI1_TXD0__LPUART1_DTR_B                        = IOMUX_PAD(0x0354, 0x01A4, 3, 0x0000, 0, 0),
+         MX93_PAD_SAI1_TXD0__CAN1_TX                              = IOMUX_PAD(0x0354, 0x01A4, 4, 0x0000, 0, 0),
+         MX93_PAD_SAI1_TXD0__GPIO1_IO13                           = IOMUX_PAD(0x0354, 0x01A4, 5, 0x0000, 0, 0),
+
+         MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00                       = IOMUX_PAD(0x0358, 0x01A8, 0, 0x0000, 0, 0),
+         MX93_PAD_SAI1_RXD0__SAI1_MCLK                            = IOMUX_PAD(0x0358, 0x01A8, 1, 0x0448, 1, 0),
+         MX93_PAD_SAI1_RXD0__LPSPI1_SOUT                          = IOMUX_PAD(0x0358, 0x01A8, 2, 0x0000, 0, 0),
+         MX93_PAD_SAI1_RXD0__LPUART2_DSR_B                        = IOMUX_PAD(0x0358, 0x01A8, 3, 0x0000, 0, 0),
+         MX93_PAD_SAI1_RXD0__MQS1_RIGHT                           = IOMUX_PAD(0x0358, 0x01A8, 4, 0x0000, 0, 0),
+         MX93_PAD_SAI1_RXD0__GPIO1_IO14                           = IOMUX_PAD(0x0358, 0x01A8, 5, 0x0000, 0, 0),
+
+         MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY                        = IOMUX_PAD(0x035C, 0x01AC, 0, 0x0000, 0, 0),
+         MX93_PAD_WDOG_ANY__GPIO1_IO15                            = IOMUX_PAD(0x035C, 0x01AC, 5, 0x0000, 0, 0),
+};
+#endif  /* __ASM_ARCH_IMX93_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h
new file mode 100644
index 00000000000..292635982f0
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 NXP
+ */
+
+#ifndef __ARCH_IMX9_SYS_PROTO_H
+#define __ARCH_NMX9_SYS_PROTO_H
+
+#include <asm/mach-imx/sys_proto.h>
+
+ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf);
+ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev);
+extern unsigned long rom_pointer[];
+enum boot_device get_boot_device(void);
+bool is_usb_boot(void);
+int mix_power_init(enum mix_power_domain pd);
+void soc_power_init(void);
+bool m33_is_rom_kicked(void);
+int m33_prepare(void);
+#endif
diff --git a/arch/arm/include/asm/arch-imx9/trdc.h b/arch/arm/include/asm/arch-imx9/trdc.h
new file mode 100644
index 00000000000..7c984d9ce92
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/trdc.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_TRDC_H
+#define __ASM_ARCH_IMX9_TRDC_H
+
+int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x,
+	u32 glbac_id, u32 glbac_val);
+int trdc_mbc_blk_config(ulong trdc_reg, u32 mbc_x,
+	u32 dom_x, u32 mem_x, u32 blk_x, bool sec_access, u32 glbac_id);
+int trdc_mrc_set_control(ulong trdc_reg, u32 mrc_x,
+	u32 glbac_id, u32 glbac_val);
+int trdc_mrc_region_config(ulong trdc_reg, u32 mrc_x,
+	u32 dom_x, u32 addr_start, u32 addr_end, bool sec_access, u32 glbac_id);
+
+void trdc_early_init(void);
+void trdc_init(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 8ae49715789..0bcc96660ec 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -77,11 +77,14 @@ void disable_ipu_clock(void);
 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
 void enable_enet_clk(unsigned char enable);
 int enable_lcdif_clock(u32 base_addr, bool enable);
+int enable_lvds_clock(u32 lcd_base_addr);
 void enable_qspi_clk(int qspi_num);
 void enable_thermal_clk(void);
+void enable_epdc_clock(void);
 void mxs_set_lcdclk(u32 base_addr, u32 freq);
 void select_ldb_di_clock_source(enum ldb_di_clock clk);
 void enable_eim_clk(unsigned char enable);
+void mxs_set_vadcclk(void);
 int do_mx6_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
 		      char *const argv[]);
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 2a2b8dd806b..5ef17f0cc9d 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -264,11 +264,20 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET		29
 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK		(0x7 << 26)
 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET		26
-/* LCDIF on i.MX6SX/UL */
+/* LCDIF on i.MX6SX/UL/SLL */
 #define MXC_CCM_CBCMR_LCDIF1_PODF_MASK                  (0x7 << 23)
 #define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET                23
-#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK		(0x7 << 23)
-#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET		23
+#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_PODF_MASK		(0x7 << 23)
+#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_PODF_OFFSET		23
+
+/* For i.MX6SL */
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK		(0x7 << 29)
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET		29
+#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_PODF_MASK		(0x7 << 26)
+#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_PODF_OFFSET		26
+#define MXC_CCM_CBCMR_EPDC_PIX_PODF_MASK		(0x7 << 23)
+#define MXC_CCM_CBCMR_EPDC_PIX_PODF_OFFSET		23
+
 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK		(0x3 << 21)
 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET	21
 #define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL			(1 << 20)
@@ -290,6 +299,14 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET	8
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK		(0x3 << 4)
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET		4
+
+/* For i.MX6SL */
+#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_SEL_MASK		(0x3 << 8)
+#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_SEL_OFFSET	8
+#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_CLK_SEL_MASK		(0x3 << 4)
+#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_CLK_SEL_OFFSET		4
+
+
 /* Exists on i.MX6QP */
 #define MXC_CCM_CBCMR_PRE_CLK_SEL			(1 << 1)
 
@@ -431,15 +448,15 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)		(((v) & 0x3) << 16)
 
 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK		\
-	((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?	\
+	((is_mx6dqp() || is_mx6ul() || is_mx6ull()) ? \
 	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP :		\
 	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ)
 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET		\
-	((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?	\
+	((is_mx6dqp() || is_mx6ul() || is_mx6ull()) ? \
 	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP :	\
 	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ)
 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v)			\
-	((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ?	\
+	((is_mx6dqp() || is_mx6ul() || is_mx6ull()) ? \
 	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) :		\
 	 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v))
 
@@ -499,7 +516,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK		(0x7)
 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET		0
 
-/* i.MX6ULL */
+/* i.MX6ULL/SLL */
 #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK		(0x7 << 15)
 #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET		15
 #define MXC_CCM_CHSCCDR_EPDC_PODF_MASK			(0x7 << 12)
@@ -516,13 +533,20 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET		19
 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
 #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK		(0x1 << 18)
-/* LCDIF1 on i.MX6SX/UL */
+/* LCDIF1 on i.MX6SX/UL/SLL */
 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK             (0x7 << 15)
 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET           15
 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK              (0x7 << 12)
 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET            12
 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK              (0x7 << 9)
 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET            9
+
+/* EPDC on i.MX6SL */
+#define MXC_CCM_CSCDR2_EPDC_PIX_CLK_SEL_MASK             (0x7 << 15)
+#define MXC_CCM_CSCDR2_EPDC_PIX_CLK_SEL_OFFSET           15
+#define MXC_CCM_CSCDR2_EPDC_PIX_PRE_DIV_MASK              (0x7 << 12)
+#define MXC_CCM_CSCDR2_EPDC_PIX_PRE_DIV_OFFSET            12
+
 /* LCDIF2 on i.MX6SX */
 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK             (0x7 << 6)
 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET           6
@@ -567,6 +591,16 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_OFFSET		16
 #define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK		(0x3 << 14)
 #define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET		14
+#define MXC_CCM_CSCDR3_CSI_CORE_PODF_MASK		(0x7 << 11)
+#define MXC_CCM_CSCDR3_CSI_CORE_PODF_OFFSET		11
+#define MXC_CCM_CSCDR3_CSI_CORE_CLK_SEL_MASK		(0x3 << 9)
+#define MXC_CCM_CSCDR3_CSI_CORE_CLK_SEL_OFFSET		9
+
+/* For i.MX6SLL */
+#define MXC_CCM_CSCDR3_PXP_PODF_MASK		(0x7 << 16)
+#define MXC_CCM_CSCDR3_PXP_PODF_OFFSET		16
+#define MXC_CCM_CSCDR3_PXP_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CSCDR3_PXP_CLK_SEL_OFFSET		14
 
 /* Define the bits in register CDHIPR */
 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY			(1 << 16)
@@ -769,7 +803,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR2_IPMUX3_MASK			(3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET	22
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
-/* i.MX6SX/UL LCD and PXP */
+/* i.MX6SX/UL/SLL LCD and PXP */
 #define MXC_CCM_CCGR2_LCD_OFFSET			28
 #define MXC_CCM_CCGR2_LCD_MASK				(3 << MXC_CCM_CCGR2_LCD_OFFSET)
 #define MXC_CCM_CCGR2_PXP_OFFSET			30
@@ -798,10 +832,18 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR3_QSPI_MASK					(3 << MXC_CCM_CCGR3_QSPI_OFFSET)
 
 /* i.MX6SL */
-#define MXC_CCM_CCGR3_LCDIF_AXI_OFFSET				6
-#define MXC_CCM_CCGR3_LCDIF_AXI_MASK				(3 << MXC_CCM_CCGR3_LCDIF_AXI_OFFSET)
-#define MXC_CCM_CCGR3_LCDIF_PIX_OFFSET				8
-#define MXC_CCM_CCGR3_LCDIF_PIX_MASK				(3 << MXC_CCM_CCGR3_LCDIF_PIX_OFFSET)
+#define MXC_CCM_CCGR3_CSI_CORE_OFFSET			0
+#define MXC_CCM_CCGR3_CSI_CORE_MASK				(3 << MXC_CCM_CCGR3_CSI_CORE_OFFSET)
+#define MXC_CCM_CCGR3_PXP_AXI_OFFSET			2
+#define MXC_CCM_CCGR3_PXP_AXI_MASK				(3 << MXC_CCM_CCGR3_PXP_AXI_OFFSET)
+#define MXC_CCM_CCGR3_EPDC_AXI_OFFSET			4
+#define MXC_CCM_CCGR3_EPDC_AXI_MASK				(3 << MXC_CCM_CCGR3_EPDC_AXI_OFFSET)
+#define MXC_CCM_CCGR3_LCDIF_AXI_OFFSET			6
+#define MXC_CCM_CCGR3_LCDIF_AXI_MASK			(3 << MXC_CCM_CCGR3_LCDIF_AXI_OFFSET)
+#define MXC_CCM_CCGR3_LCDIF_PIX_OFFSET			8
+#define MXC_CCM_CCGR3_LCDIF_PIX_MASK			(3 << MXC_CCM_CCGR3_LCDIF_PIX_OFFSET)
+#define MXC_CCM_CCGR3_EPDC_PIX_OFFSET			10
+#define MXC_CCM_CCGR3_EPDC_PIX_MASK				(3 << MXC_CCM_CCGR3_EPDC_PIX_OFFSET)
 
 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET				0
 #define MXC_CCM_CCGR3_IPU1_IPU_MASK				(3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index a8a5bf7a575..1a1159908dc 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -23,7 +23,7 @@
 #define GPU_ARB_END_ADDR                0x01803FFF
 #define APBH_DMA_ARB_BASE_ADDR          0x01804000
 #define APBH_DMA_ARB_END_ADDR           0x0180BFFF
-#define M4_BOOTROM_BASE_ADDR			0x007F8000
+#define MCU_BOOTROM_BASE_ADDR			0x007F8000
 
 #elif !defined(CONFIG_MX6SLL)
 #define CAAM_ARB_BASE_ADDR              0x00100000
@@ -122,7 +122,7 @@
 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
 #endif
 
-#ifndef CONFIG_MX6SX
+#if (!(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)))
 #define IPU_SOC_BASE_ADDR		IPU1_ARB_BASE_ADDR
 #define IPU_SOC_OFFSET			0x00200000
 #endif
@@ -158,12 +158,21 @@
 #define UART1_BASE                  (ATZ1_BASE_ADDR + 0x20000)
 #define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000)
 #define UART8_BASE                  (ATZ1_BASE_ADDR + 0x24000)
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define SAI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
+#define SAI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
+#define SAI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
+#else
 #define SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
 #define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
 #define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
+#endif
 #define ASRC_BASE_ADDR              (ATZ1_BASE_ADDR + 0x34000)
 
-#ifndef CONFIG_MX6SX
+#if defined(CONFIG_MX6UL)
+#define TOUCH_CTRL_BASE_ADDR        (ATZ1_BASE_ADDR + 0x40000)
+#define BEE_BASE_ADDR               (ATZ1_BASE_ADDR + 0x44000)
+#elif !defined(CONFIG_MX6SX)
 #define SPBA_BASE_ADDR              (ATZ1_BASE_ADDR + 0x3C000)
 #define VPU_BASE_ADDR               (ATZ1_BASE_ADDR + 0x40000)
 #endif
@@ -185,8 +194,13 @@
 #define GPIO4_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x28000)
 #define GPIO5_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x2C000)
 #define MX6UL_SNVS_LP_BASE_ADDR     (AIPS1_OFF_BASE_ADDR + 0x30000)
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define SNVS_LP_BASE_ADDR           (AIPS1_OFF_BASE_ADDR + 0x30000)
+#define ENET2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
+#else
 #define GPIO6_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x30000)
 #define GPIO7_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
+#endif
 #define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
 #define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
 #define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
@@ -211,6 +225,7 @@
 #define CSI_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x64000)
 #define SIPIX_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#define EPDC_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x74000)
 #elif defined(CONFIG_MX6SX)
 #define CANFD1_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define SDMA_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x6C000)
@@ -218,10 +233,19 @@
 #define SEMAPHORE1_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x74000)
 #define SEMAPHORE2_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x78000)
 #define RDC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x7C000)
+
+#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define GPT2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define SDMA_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#define PWM5_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x70000)
+#define PWM6_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x74000)
+#define PWM7_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x78000)
+#define PWM8_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x7C000)
 #else
 #define DCIC1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x64000)
 #define DCIC2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#define EPDC_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x74000)
 #endif
 
 #define MX6SL_LCDIF_BASE_ADDR      (AIPS1_OFF_BASE_ADDR + 0x78000)
@@ -231,12 +255,14 @@
 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
 #define AIPS3_ON_BASE_ADDR          (ATZ3_BASE_ADDR + 0x7C000)
 #define AIPS3_OFF_BASE_ADDR         (ATZ3_BASE_ADDR + 0x80000)
+
 #if defined(CONFIG_MX6UL)
 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR + 0x40000)
+#define ARM_BASE_ADDR               (ATZ2_BASE_ADDR)
 #else
 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
+#define ARM_BASE_ADDR		    	(ATZ2_BASE_ADDR + 0x40000)
 #endif
-#define ARM_BASE_ADDR		    (ATZ2_BASE_ADDR + 0x40000)
 
 #define CONFIG_SYS_FSL_SEC_OFFSET   0
 #define CONFIG_SYS_FSL_SEC_ADDR     (CAAM_BASE_ADDR + \
@@ -252,6 +278,8 @@
 #define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
 #ifdef CONFIG_MX6SL
 #define MSHC_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0xC000)
+#elif defined(CONFIG_MX6UL)
+#define SIM1_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0xC000)
 #else
 #define MLB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0xC000)
 #endif
@@ -260,6 +288,9 @@
 #define USDHC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x14000)
 #define USDHC3_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x18000)
 #define USDHC4_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x1C000)
+
+#define MX6UL_ADC1_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x18000)
+#define MX6UL_ADC2_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x1C000)
 #define I2C1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x20000)
 #define I2C2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x24000)
 #define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
@@ -279,12 +310,16 @@
 #define WEIM_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x38000)
 #define OCOTP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x3C000)
 #define CSU_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x40000)
-#ifdef CONFIG_MX6SLL
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define CSI_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x44000)
+#define PXP_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4C000)
+#elif defined(CONFIG_MX6SLL)
 #define IOMUXC_GPR_SNVS_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x44000)
 #define IOMUXC_SNVS_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x48000)
-#endif
+#else
 #define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
 #define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
+#endif
 #define MX6UL_LCDIF1_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x48000)
 #define MX6ULL_LCDIF1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x48000)
 #ifdef CONFIG_MX6SX
@@ -294,9 +329,10 @@
 #endif
 #define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
 #if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
-#define SCTR_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
+#define SYSCNT_RD_IPS_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
+#define SYSCNT_CMP_IPS_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x58000)
+#define SYSCNT_CTRL_IPS_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
-#define UART6_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x7C000)
 #elif defined(CONFIG_MX6SX)
 #define SAI1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x54000)
 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
@@ -314,9 +350,20 @@
 #define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
 #define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
 #define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
+/* i.MX6SLL */
+#define MTR_MASTER_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x7C000)
+/* i.MX6SX/UL */
 #define I2C4_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x78000)
+/* i.MX6UL */
+#define MX6UL_UART6_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x7C000)
 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
+
+#define OTG_BASE_ADDR               USB_BASE_ADDR
+
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#define SCTR_BASE_ADDR              SYSCNT_CTRL_IPS_BASE_ADDR
+#endif
 /* i.MX6SLL */
 #define MTR_MASTER_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x7C000)
 
@@ -331,19 +378,18 @@
 #define VDEC_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x2C000)
 #define SPBA_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x3C000)
 #define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
-#define ADC1_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x80000)
-#define ADC2_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
+#define MX6SX_ADC1_BASE_ADDR        (AIPS3_ARB_BASE_ADDR + 0x80000)
+#define MX6SX_ADC2_BASE_ADDR        (AIPS3_ARB_BASE_ADDR + 0x84000)
 #define ECSPI5_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x8C000)
 #define HS_BASE_ADDR                (AIPS3_ARB_BASE_ADDR + 0x90000)
 #define MU_MCU_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x94000)
 #define CANFD_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x98000)
 #define MU_DSP_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x9C000)
-#define UART6_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0xA0000)
 #define PWM5_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA4000)
 #define PWM6_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA8000)
 #define PWM7_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xAC000)
 #define PWM8_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xB0000)
-#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#elif defined(CONFIG_MX6ULL)
 #define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
 #define DCP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x80000)
 #define RNGB_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)
@@ -359,6 +405,7 @@
 #define LCDIF2_BASE_ADDR            (AIPS3_ARB_BASE_ADDR + 0x24000)
 #define MX6SX_LCDIF1_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x20000)
 #define MX6SX_WDOG3_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x88000)
+#define MX6SX_UART6_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0xA0000)
 
 #if !(defined(CONFIG_MX6SX) || \
 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
@@ -368,6 +415,7 @@
 #define IRAM_SIZE                    0x00020000
 #endif
 #define FEC_QUIRK_ENET_MAC
+#define SNVS_LPGPR                   0x68
 
 #include <asm/mach-imx/regs-lcdif.h>
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
@@ -385,6 +433,12 @@
 			  MX6UL_LCDIF1_BASE_ADDR :		\
 			  ((is_mx6ull()) ?	\
 			  MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)))
+#define UART6_BASE_ADDR ((is_mx6ul() || is_mx6ull()) ? \
+			  MX6UL_UART6_BASE_ADDR : MX6SX_UART6_BASE_ADDR)
+
+#define MXS_LCDIF_BASE LCDIF1_BASE_ADDR
+
+#define MXS_LCDIF_BASE LCDIF1_BASE_ADDR
 
 
 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
@@ -585,7 +639,12 @@ struct iomuxc {
 #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
 	u8 reserved[0x4000];
 #endif
+
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+	u32 gpr[15];
+#else
 	u32 gpr[14];
+#endif
 };
 
 struct gpc {
@@ -668,10 +727,19 @@ struct gpc {
 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0		(IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1		(IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 
-/*
- * CSPI register definitions
- */
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK			(0x3 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN		(0x0 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD			(0x1 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI	(0x2 << 4)
+#define IMX6SX_GPR5_CSI1_MUX_CTRL_GND			(0x3 << 4)
+
+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) ||\
+	defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL)
+#define SPI_MAX_NUM	3
+#else
 #define SPI_MAX_NUM	4
+#endif
+
 #if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
 	defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 #define MXC_SPI_BASE_ADDRESSES \
@@ -688,6 +756,8 @@ struct gpc {
 	ECSPI5_BASE_ADDR
 #endif
 
+#define ANATOP_PLL_VIDEO        0xA0
+
 struct ocotp_regs {
 	u32	ctrl;
 	u32	ctrl_set;
@@ -937,6 +1007,25 @@ struct anatop_regs {
 #define ANATOP_PFD_CLKGATE_SHIFT(n)	(7+((n)*8))
 #define ANATOP_PFD_CLKGATE_MASK(n)	(1<<ANATOP_PFD_CLKGATE_SHIFT(n))
 
+struct iomuxc_gpr_base_regs {
+#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+	u32     gpr[15];        /* 0x000 */
+#else
+	u32     gpr[14];        /* 0x000 */
+#endif
+};
+
+struct iomuxc_base_regs {
+#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+	u32     gpr[14];        /* 0x000 */
+#endif
+	u32     obsrv[5];       /* 0x038 */
+	u32     swmux_ctl[197]; /* 0x04c */
+	u32     swpad_ctl[250]; /* 0x360 */
+	u32     swgrp[26];      /* 0x748 */
+	u32     daisy[104];     /* 0x7b0..94c */
+};
+
 struct wdog_regs {
 	u16	wcr;	/* Control */
 	u16	wsr;	/* Service */
@@ -962,11 +1051,28 @@ struct pwm_regs {
 	u32	cnr;
 };
 
+struct dbg_monitor_regs {
+	u32	ctrl[4];		/* Control */
+	u32	master_en[4];		/* Master enable */
+	u32	irq[4];			/* IRQ */
+	u32	trap_addr_low[4];	/* Trap address low */
+	u32	trap_addr_high[4];	/* Trap address high */
+	u32	trap_id[4];		/* Trap ID */
+	u32	snvs_addr[4];		/* SNVS address */
+	u32	snvs_data[4];		/* SNVS data */
+	u32	snvs_info[4];		/* SNVS info */
+	u32	version[4];		/* Version */
+};
+
 /*
  * If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB
  * If boot from the other mode, USB0_PWD will keep reset value
  */
-#define	is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20)))
+#include <stdbool.h>
+bool is_usb_boot(void);
+#define	is_boot_from_usb  is_usb_boot
+#define	is_usbphy_power_on(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20)))
+#define	disconnect_from_pc(void) writel(0x0, OTG_BASE_ADDR + 0x140)
 
 #endif /* __ASSEMBLY__ */
 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index dbc97b25df8..b42af53e42d 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -6,7 +6,7 @@
 #define __ASM_ARCH_MX6_DDR_H__
 
 #ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_MX6Q
+#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QP)
 #include "mx6q-ddr.h"
 #else
 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
@@ -26,7 +26,7 @@
 #endif	/* CONFIG_MX6UL */
 #endif	/* CONFIG_MX6SX */
 #endif	/* CONFIG_MX6DL or CONFIG_MX6S */
-#endif	/* CONFIG_MX6Q */
+#endif	/* CONFIG_MX6Q or CONFIG_MX6QP */
 #else
 
 enum {
diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h
index 9a99a6b7047..e8c0bec2463 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h
@@ -20,7 +20,7 @@ enum {
 	MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc),
 #include "mx6dl_pins.h"
 };
-#elif defined(CONFIG_MX6Q)
+#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6QP)
 enum {
 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
 	MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
diff --git a/arch/arm/include/asm/arch-mx6/mx6_bee.h b/arch/arm/include/asm/arch-mx6/mx6_bee.h
new file mode 100644
index 00000000000..eb51dfef75d
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/mx6_bee.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#define GPR0           0x0
+#define GPR1           0x4
+#define GPR2           0x8
+#define GPR3           0xC
+#define GPR4           0x10
+#define GPR5           0x14
+#define GPR6           0x18
+#define GPR7           0x1C
+#define GPR8           0x20
+#define GPR9           0x24
+#define GPR10          0x28
+#define GPR11          0x2C
+
+#define GPR0_CTRL_CLK_EN_LOCK	(1 << 31)
+#define GPR0_CTRL_CLK_EN	(1 << 15)
+#define GPR0_CTRL_SFTRST_N_LOCK	(1 << 30)
+#define GPR0_CTRL_SFTRST	(0 << 14)
+#define GPR0_CTRL_SFTRST_N	(1 << 14)
+#define GPR0_CTRL_AES_MODE_LOCK	(1 << 29)
+#define GPR0_CTRL_AES_MODE_ECB	(0 << 13)
+#define GPR0_CTRL_AES_MODE_CTR	(1 << 13)
+#define GPR0_SEC_LEVEL_LOCK	(3 << 24)
+#define GPR0_SEC_LEVEL		(3 << 8)
+#define GPR0_AES_KEY_SEL_LOCK	(1 << 20)
+#define GPR0_AES_KEY_SEL_SNVS	(0 << 4)
+#define GPR0_AES_KEY_SEL_SOFT	(1 << 4)
+#define GPR0_BEE_ENABLE_LOCK	(1 << 16)
+#define GPR0_BEE_ENABLE		(1 << 0)
+
+/*
+ * SECURITY LEVEL
+ *        Non-Secure User |  Non-Secure Spvr | Secure User | Secure Spvr
+ * Level
+ * (0)00      RD + WR           RD + WR          RD + WR       RD + WR
+ * (1)01      None              RD + WR          RD + WR       RD + WR
+ * (2)10      None              None             RD + WR       RD + WR
+ * (3)11      None              None             None          RD + WR
+ */
+#define GPR0_SEC_LEVEL_0	(0 << 8)
+#define GPR0_SEC_LEVEL_1	(1 << 8)
+#define GPR0_SEC_LEVEL_2	(2 << 8)
+#define GPR0_SEC_LEVEL_3	(3 << 8)
diff --git a/arch/arm/include/asm/arch-mx6/mx6_plugin.S b/arch/arm/include/asm/arch-mx6/mx6_plugin.S
index 4d12c6873b3..4ad38b803b9 100644
--- a/arch/arm/include/asm/arch-mx6/mx6_plugin.S
+++ b/arch/arm/include/asm/arch-mx6/mx6_plugin.S
@@ -63,12 +63,12 @@ plugin_start:
 before_calling_rom___pu_irom_hwcnfg_setup:
 	ldr r3, =ROM_VERSION_OFFSET
 	ldr r4, [r3]
-#if defined(CONFIG_MX6SOLO) || defined(CONFIG_MX6DL)
+#if defined(CONFIG_MX6S) || defined(CONFIG_MX6DL)
 	ldr r3, =ROM_VERSION_TO12
 	cmp r4, r3
 	ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DL_TO12
 	ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
-#elif defined(CONFIG_MX6Q)
+#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6QP)
 	ldr r3, =ROM_VERSION_TO15
 	cmp r4, r3
 	ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15
diff --git a/arch/arm/include/asm/arch-mx6/mx6q-ddr.h b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
index c76a9202023..009fbe3a71f 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
@@ -5,7 +5,7 @@
 #ifndef __ASM_ARCH_MX6Q_DDR_H__
 #define __ASM_ARCH_MX6Q_DDR_H__
 
-#ifndef CONFIG_MX6Q
+#if !defined(CONFIG_MX6Q) && !defined(CONFIG_MX6QP)
 #error "wrong CPU"
 #endif
 
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 01b14d73dc9..6e01ca82816 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -59,14 +59,70 @@ enum {
 	MX6_PAD_FEC_RX_ER__GPIO_4_19				= IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0),
 	MX6_PAD_FEC_TX_CLK__GPIO_4_21				= IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0),
 
-	MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID			= IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0),
+	MX6_PAD_KEY_COL0__KPP_COL_0				= IOMUX_PAD(0x0474, 0x016C, 0, 0x0734, 0, 0),
+	MX6_PAD_KEY_COL1__KPP_COL_1				= IOMUX_PAD(0x0478, 0x0170, 0, 0x0738, 0, 0),
+	MX6_PAD_KEY_COL2__KPP_COL_2				= IOMUX_PAD(0x047C, 0x0174, 0, 0x073C, 0, 0),
+	MX6_PAD_KEY_COL3__KPP_COL_3				= IOMUX_PAD(0x0480, 0x0178, 0, 0x0740, 0, 0),
+	MX6_PAD_KEY_ROW0__KPP_ROW_0				= IOMUX_PAD(0x0494, 0x018C, 0, 0x0754, 0, 0),
+	MX6_PAD_KEY_ROW1__KPP_ROW_1				= IOMUX_PAD(0x0498, 0x0190, 0, 0x0758, 0, 0),
+	MX6_PAD_KEY_ROW2__KPP_ROW_2				= IOMUX_PAD(0x049C, 0x0194, 0, 0x075C, 0, 0),
+	MX6_PAD_KEY_ROW3__KPP_ROW_3				= IOMUX_PAD(0x04A0, 0x0198, 0, 0x0760, 0, 0),
 
 	MX6_PAD_KEY_COL4__USB_USBOTG1_PWR			= IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0),
 	MX6_PAD_KEY_COL5__USB_USBOTG2_PWR			= IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0),
+	MX6_PAD_KEY_COL6__GPIO_4_4				= IOMUX_PAD(0x048C, 0x0184, 5, 0x0000, 0, 0),
 
 	MX6_PAD_I2C1_SDA__I2C1_SDA				= IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0),
 	MX6_PAD_I2C1_SDA__GPIO_3_13				= IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0),
 	MX6_PAD_I2C1_SCL__I2C1_SCL				= IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0),
 	MX6_PAD_I2C1_SCL__GPIO_3_12				= IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0),
+
+	MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID			= IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0),
+	MX6_PAD_EPDC_PWRCTRL2__GPIO_2_9				= IOMUX_PAD(0x03DC, 0x00EC, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_PWRCTRL3__GPIO_2_10			= IOMUX_PAD(0x03E0, 0x00F0, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_PWRSTAT__GPIO_2_13				= IOMUX_PAD(0x03E8, 0x00F8, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_VCOM0__GPIO_2_3				= IOMUX_PAD(0x0410, 0x0120, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14			= IOMUX_PAD(0x03EC, 0x00FC, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7				= IOMUX_PAD(0x03D4, 0x00E4, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D0__EPDC_SDDO_0				= IOMUX_PAD(0x0380, 0x0090, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D1__EPDC_SDDO_1				= IOMUX_PAD(0x0384, 0x0094, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D2__EPDC_SDDO_2				= IOMUX_PAD(0x03A0, 0x00B0, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D3__EPDC_SDDO_3				= IOMUX_PAD(0x03A4, 0x00B4, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D4__EPDC_SDDO_4				= IOMUX_PAD(0x03A8, 0x00B8, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D5__EPDC_SDDO_5				= IOMUX_PAD(0x03AC, 0x00BC, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D6__EPDC_SDDO_6				= IOMUX_PAD(0x03B0, 0x00C0, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D7__EPDC_SDDO_7				= IOMUX_PAD(0x03B4, 0x00C4, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDCLK__EPDC_GDCLK				= IOMUX_PAD(0x03C0, 0x00D0, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDSP__EPDC_GDSP				= IOMUX_PAD(0x03CC, 0x00DC, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDOE__EPDC_GDOE				= IOMUX_PAD(0x03C4, 0x00D4, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDRL__EPDC_GDRL				= IOMUX_PAD(0x03C8, 0x00D8, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCLK__EPDC_SDCLK				= IOMUX_PAD(0x0400, 0x0110, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDOE__EPDC_SDOE				= IOMUX_PAD(0x0408, 0x0118, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDLE__EPDC_SDLE				= IOMUX_PAD(0x0404, 0x0114, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDSHR__EPDC_SDSHR				= IOMUX_PAD(0x040C, 0x011C, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_BDR0__EPDC_BDR_0				= IOMUX_PAD(0x0378, 0x0088, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE0__EPDC_SDCE_0				= IOMUX_PAD(0x03F0, 0x0100, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE1__EPDC_SDCE_1				= IOMUX_PAD(0x03F4, 0x0104, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE2__EPDC_SDCE_2				= IOMUX_PAD(0x03F8, 0x0108, 0, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D0__GPIO_1_7				= IOMUX_PAD(0x0380, 0x0090, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D1__GPIO_1_8				= IOMUX_PAD(0x0384, 0x0094, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D2__GPIO_1_9				= IOMUX_PAD(0x03A0, 0x00B0, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D3__GPIO_1_10				= IOMUX_PAD(0x03A4, 0x00B4, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D4__GPIO_1_11				= IOMUX_PAD(0x03A8, 0x00B8, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D5__GPIO_1_12				= IOMUX_PAD(0x03AC, 0x00BC, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D6__GPIO_1_13				= IOMUX_PAD(0x03B0, 0x00C0, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_D7__GPIO_1_14				= IOMUX_PAD(0x03B4, 0x00C4, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDCLK__GPIO_1_31				= IOMUX_PAD(0x03C0, 0x00D0, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDSP__GPIO_2_2				= IOMUX_PAD(0x03CC, 0x00DC, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDOE__GPIO_2_0				= IOMUX_PAD(0x03C4, 0x00D4, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_GDRL__GPIO_2_1				= IOMUX_PAD(0x03C8, 0x00D8, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCLK__GPIO_1_23				= IOMUX_PAD(0x0400, 0x0110, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDOE__GPIO_1_25				= IOMUX_PAD(0x0408, 0x0118, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDLE__GPIO_1_24				= IOMUX_PAD(0x0404, 0x0114, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDSHR__GPIO_1_26				= IOMUX_PAD(0x040C, 0x011C, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_BDR0__GPIO_2_5				= IOMUX_PAD(0x0378, 0x0088, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE0__GPIO_1_27				= IOMUX_PAD(0x03F0, 0x0100, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE1__GPIO_1_28				= IOMUX_PAD(0x03F4, 0x0104, 5, 0x0000, 0, 0),
+	MX6_PAD_EPDC_SDCE2__GPIO_1_29				= IOMUX_PAD(0x03F8, 0x0108, 5, 0x0000, 0, 0),
 };
 #endif	/* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/mx6ul_pins.h b/arch/arm/include/asm/arch-mx6/mx6ul_pins.h
index 031b4a0a880..fdd63b920b1 100644
--- a/arch/arm/include/asm/arch-mx6/mx6ul_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6ul_pins.h
@@ -66,6 +66,7 @@ enum {
 	MX6_PAD_JTAG_TCK__SAI2_RX_DATA                         = IOMUX_PAD(0x02E0, 0x0054, 2, 0x05F4, 0, 0),
 	MX6_PAD_JTAG_TCK__PWM7_OUT                             = IOMUX_PAD(0x02E0, 0x0054, 4, 0x0000, 0, 0),
 	MX6_PAD_JTAG_TCK__GPIO1_IO14                           = IOMUX_PAD(0x02E0, 0x0054, 5, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TCK__REF_CLK_32K                          = IOMUX_PAD(0x02E0, 0x0054, 6, 0x0000, 0, 0),
 	MX6_PAD_JTAG_TCK__SIM2_POWER_FAIL                      = IOMUX_PAD(0x02E0, 0x0054, 8, 0x0000, 0, 0),
 
 	MX6_PAD_JTAG_TRST_B__SJC_TRSTB                         = IOMUX_PAD(0x02E4, 0x0058, 0, 0x0000, 0, 0),
@@ -73,6 +74,7 @@ enum {
 	MX6_PAD_JTAG_TRST_B__SAI2_TX_DATA                      = IOMUX_PAD(0x02E4, 0x0058, 2, 0x0000, 0, 0),
 	MX6_PAD_JTAG_TRST_B__PWM8_OUT                          = IOMUX_PAD(0x02E4, 0x0058, 4, 0x0000, 0, 0),
 	MX6_PAD_JTAG_TRST_B__GPIO1_IO15                        = IOMUX_PAD(0x02E4, 0x0058, 5, 0x0000, 0, 0),
+	MX6_PAD_JTAG_TRST_B__REF_CLK_24M                       = IOMUX_PAD(0x02E4, 0x0058, 6, 0x0000, 0, 0),
 	MX6_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS                  = IOMUX_PAD(0x02E4, 0x0058, 8, 0x0000, 0, 0),
 
 	MX6_PAD_GPIO1_IO00__I2C2_SCL                           = IOMUX_PAD(0x02E8, 0x005C, IOMUX_CONFIG_SION | 0, 0x05AC, 1, 0),
@@ -109,6 +111,7 @@ enum {
 	MX6_PAD_GPIO1_IO03__I2C1_SDA                           = IOMUX_PAD(0x02F4, 0x0068, IOMUX_CONFIG_SION | 0, 0x05A8, 1, 0),
 	MX6_PAD_GPIO1_IO03__GPT1_COMPARE3                      = IOMUX_PAD(0x02F4, 0x0068, 1, 0x0000, 0, 0),
 	MX6_PAD_GPIO1_IO03__USB_OTG2_OC                        = IOMUX_PAD(0x02F4, 0x0068, 2, 0x0660, 0, 0),
+	MX6_PAD_GPIO1_IO03__REF_CLK_32K                        = IOMUX_PAD(0x02F4, 0x0068, 3, 0x0000, 0, 0),
 	MX6_PAD_GPIO1_IO03__USDHC1_CD_B                        = IOMUX_PAD(0x02F4, 0x0068, 4, 0x0668, 0, 0),
 	MX6_PAD_GPIO1_IO03__GPIO1_IO03                         = IOMUX_PAD(0x02F4, 0x0068, 5, 0x0000, 0, 0),
 	MX6_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK                    = IOMUX_PAD(0x02F4, 0x0068, 6, 0x0000, 0, 0),
@@ -119,6 +122,7 @@ enum {
 	MX6_PAD_GPIO1_IO04__ENET1_REF_CLK1                     = IOMUX_PAD(0x02F8, 0x006C, 0, 0x0574, 1, 0),
 	MX6_PAD_GPIO1_IO04__PWM3_OUT                           = IOMUX_PAD(0x02F8, 0x006C, 1, 0x0000, 0, 0),
 	MX6_PAD_GPIO1_IO04__USB_OTG1_PWR                       = IOMUX_PAD(0x02F8, 0x006C, 2, 0x0000, 0, 0),
+	MX6_PAD_GPIO1_IO04__REF_CLK_24M                        = IOMUX_PAD(0x02F8, 0x006C, 3, 0x0000, 0, 0),
 	MX6_PAD_GPIO1_IO04__USDHC1_RESET_B                     = IOMUX_PAD(0x02F8, 0x006C, 4, 0x0000, 0, 0),
 	MX6_PAD_GPIO1_IO04__GPIO1_IO04                         = IOMUX_PAD(0x02F8, 0x006C, 5, 0x0000, 0, 0),
 	MX6_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN               = IOMUX_PAD(0x02F8, 0x006C, 6, 0x0000, 0, 0),
@@ -365,6 +369,7 @@ enum {
 	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN                       = IOMUX_PAD(0x0358, 0x00CC, 0, 0x0000, 0, 0),
 	MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS                     = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 3, 0),
 	MX6_PAD_ENET1_RX_EN__UART5_DTE_CTS                     = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0000, 0, 0),
+	MX6_PAD_ENET1_RX_EN__REF_CLK_32K                       = IOMUX_PAD(0x0358, 0x00CC, 2, 0x0000, 0, 0),
 	MX6_PAD_ENET1_RX_EN__CSI_DATA18                        = IOMUX_PAD(0x0358, 0x00CC, 3, 0x050C, 0, 0),
 	MX6_PAD_ENET1_RX_EN__FLEXCAN2_TX                       = IOMUX_PAD(0x0358, 0x00CC, 4, 0x0000, 0, 0),
 	MX6_PAD_ENET1_RX_EN__GPIO2_IO02                        = IOMUX_PAD(0x0358, 0x00CC, 5, 0x0000, 0, 0),
@@ -374,6 +379,7 @@ enum {
 	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00                  = IOMUX_PAD(0x035C, 0x00D0, 0, 0x0000, 0, 0),
 	MX6_PAD_ENET1_TX_DATA0__UART5_DCE_CTS                  = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0000, 0, 0),
 	MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS                  = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 4, 0),
+	MX6_PAD_ENET1_TX_DATA0__REF_CLK_24M                    = IOMUX_PAD(0x035C, 0x00D0, 2, 0x0000, 0, 0),
 	MX6_PAD_ENET1_TX_DATA0__CSI_DATA19                     = IOMUX_PAD(0x035C, 0x00D0, 3, 0x0510, 0, 0),
 	MX6_PAD_ENET1_TX_DATA0__FLEXCAN2_RX                    = IOMUX_PAD(0x035C, 0x00D0, 4, 0x0588, 1, 0),
 	MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03                     = IOMUX_PAD(0x035C, 0x00D0, 5, 0x0000, 0, 0),
@@ -458,6 +464,7 @@ enum {
 	MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02                     = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11                     = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_DATA0__KPP_COL05                      = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA0__REF_CLK_24M                    = IOMUX_PAD(0x037C, 0x00F0, 8, 0x0000, 0, 0),
 
 	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01                  = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX                   = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0),
@@ -545,6 +552,7 @@ enum {
 
 	MX6_PAD_LCD_DATA00__LCDIF_DATA00                       = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA00__PWM1_OUT                           = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA00__CA7_MX6UL_TRACE0                   = IOMUX_PAD(0x03A4, 0x0118, 2, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN               = IOMUX_PAD(0x03A4, 0x0118, 3, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA00__I2C3_SDA                           = IOMUX_PAD(0x03A4, 0x0118, IOMUX_CONFIG_SION | 4, 0x05B8, 2, 0),
 	MX6_PAD_LCD_DATA00__GPIO3_IO05                         = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0),
@@ -553,6 +561,7 @@ enum {
 
 	MX6_PAD_LCD_DATA01__LCDIF_DATA01                       = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA01__PWM2_OUT                           = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA01__CA7_MX6UL_TRACE1                   = IOMUX_PAD(0x03A8, 0x011C, 2, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT              = IOMUX_PAD(0x03A8, 0x011C, 3, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA01__I2C3_SCL                           = IOMUX_PAD(0x03A8, 0x011C, IOMUX_CONFIG_SION | 4, 0x05B4, 2, 0),
 	MX6_PAD_LCD_DATA01__GPIO3_IO06                         = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0),
@@ -561,6 +570,7 @@ enum {
 
 	MX6_PAD_LCD_DATA02__LCDIF_DATA02                       = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA02__PWM3_OUT                           = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA02__CA7_MX6UL_TRACE2                   = IOMUX_PAD(0x03AC, 0x0120, 2, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN               = IOMUX_PAD(0x03AC, 0x0120, 3, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA02__I2C4_SDA                           = IOMUX_PAD(0x03AC, 0x0120, IOMUX_CONFIG_SION | 4, 0x05C0, 2, 0),
 	MX6_PAD_LCD_DATA02__GPIO3_IO07                         = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0),
@@ -569,6 +579,7 @@ enum {
 
 	MX6_PAD_LCD_DATA03__LCDIF_DATA03                       = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA03__PWM4_OUT                           = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA03__CA7_MX6UL_TRACE3                   = IOMUX_PAD(0x03B0, 0x0124, 2, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT              = IOMUX_PAD(0x03B0, 0x0124, 3, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA03__I2C4_SCL                           = IOMUX_PAD(0x03B0, 0x0124, IOMUX_CONFIG_SION | 4, 0x05BC, 2, 0),
 	MX6_PAD_LCD_DATA03__GPIO3_IO08                         = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0),
@@ -578,6 +589,7 @@ enum {
 	MX6_PAD_LCD_DATA04__LCDIF_DATA04                       = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA04__UART8_DCE_CTS                      = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA04__UART8_DTE_RTS                      = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0658, 2, 0),
+	MX6_PAD_LCD_DATA04__CA7_MX6UL_TRACE4                   = IOMUX_PAD(0x03B4, 0x0128, 2, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN               = IOMUX_PAD(0x03B4, 0x0128, 3, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA04__SPDIF_SR_CLK                       = IOMUX_PAD(0x03B4, 0x0128, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA04__GPIO3_IO09                         = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0),
@@ -587,6 +599,7 @@ enum {
 	MX6_PAD_LCD_DATA05__LCDIF_DATA05                       = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA05__UART8_DCE_RTS                      = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0),
 	MX6_PAD_LCD_DATA05__UART8_DTE_CTS                      = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA05__CA7_MX6UL_TRACE5                   = IOMUX_PAD(0x03B8, 0x012C, 2, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT              = IOMUX_PAD(0x03B8, 0x012C, 3, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA05__SPDIF_OUT                          = IOMUX_PAD(0x03B8, 0x012C, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA05__GPIO3_IO10                         = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0),
@@ -596,6 +609,7 @@ enum {
 	MX6_PAD_LCD_DATA06__LCDIF_DATA06                       = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA06__UART7_DCE_CTS                      = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA06__UART7_DTE_RTS                      = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0650, 2, 0),
+	MX6_PAD_LCD_DATA06__CA7_MX6UL_TRACE6                   = IOMUX_PAD(0x03BC, 0x0130, 2, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN               = IOMUX_PAD(0x03BC, 0x0130, 3, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA06__SPDIF_LOCK                         = IOMUX_PAD(0x03BC, 0x0130, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA06__GPIO3_IO11                         = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0),
@@ -605,6 +619,7 @@ enum {
 	MX6_PAD_LCD_DATA07__LCDIF_DATA07                       = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA07__UART7_DCE_RTS                      = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0),
 	MX6_PAD_LCD_DATA07__UART7_DTE_CTS                      = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA07__CA7_MX6UL_TRACE7                   = IOMUX_PAD(0x03C0, 0x0134, 2, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT              = IOMUX_PAD(0x03C0, 0x0134, 3, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA07__SPDIF_EXT_CLK                      = IOMUX_PAD(0x03C0, 0x0134, 4, 0x061C, 0, 0),
 	MX6_PAD_LCD_DATA07__GPIO3_IO12                         = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0),
@@ -613,6 +628,7 @@ enum {
 
 	MX6_PAD_LCD_DATA08__LCDIF_DATA08                       = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA08__SPDIF_IN                           = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0),
+	MX6_PAD_LCD_DATA08__CA7_MX6UL_TRACE8                   = IOMUX_PAD(0x03C4, 0x0138, 2, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA08__CSI_DATA16                         = IOMUX_PAD(0x03C4, 0x0138, 3, 0x0504, 1, 0),
 	MX6_PAD_LCD_DATA08__EIM_DATA00                         = IOMUX_PAD(0x03C4, 0x0138, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA08__GPIO3_IO13                         = IOMUX_PAD(0x03C4, 0x0138, 5, 0x0000, 0, 0),
@@ -621,6 +637,7 @@ enum {
 
 	MX6_PAD_LCD_DATA09__LCDIF_DATA09                       = IOMUX_PAD(0x03C8, 0x013C, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA09__SAI3_MCLK                          = IOMUX_PAD(0x03C8, 0x013C, 1, 0x0600, 1, 0),
+	MX6_PAD_LCD_DATA09__CA7_MX6UL_TRACE9                   = IOMUX_PAD(0x03C8, 0x013C, 2, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA09__CSI_DATA17                         = IOMUX_PAD(0x03C8, 0x013C, 3, 0x0508, 1, 0),
 	MX6_PAD_LCD_DATA09__EIM_DATA01                         = IOMUX_PAD(0x03C8, 0x013C, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA09__GPIO3_IO14                         = IOMUX_PAD(0x03C8, 0x013C, 5, 0x0000, 0, 0),
@@ -629,6 +646,7 @@ enum {
 
 	MX6_PAD_LCD_DATA10__LCDIF_DATA10                       = IOMUX_PAD(0x03CC, 0x0140, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA10__SAI3_RX_SYNC                       = IOMUX_PAD(0x03CC, 0x0140, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA10__CA7_MX6UL_TRACE10                  = IOMUX_PAD(0x03CC, 0x0140, 2, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA10__CSI_DATA18                         = IOMUX_PAD(0x03CC, 0x0140, 3, 0x050C, 1, 0),
 	MX6_PAD_LCD_DATA10__EIM_DATA02                         = IOMUX_PAD(0x03CC, 0x0140, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA10__GPIO3_IO15                         = IOMUX_PAD(0x03CC, 0x0140, 5, 0x0000, 0, 0),
@@ -637,6 +655,7 @@ enum {
 
 	MX6_PAD_LCD_DATA11__LCDIF_DATA11                       = IOMUX_PAD(0x03D0, 0x0144, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA11__SAI3_RX_BCLK                       = IOMUX_PAD(0x03D0, 0x0144, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA11__CA7_MX6UL_TRACE11                  = IOMUX_PAD(0x03D0, 0x0144, 2, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA11__CSI_DATA19                         = IOMUX_PAD(0x03D0, 0x0144, 3, 0x0510, 1, 0),
 	MX6_PAD_LCD_DATA11__EIM_DATA03                         = IOMUX_PAD(0x03D0, 0x0144, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA11__GPIO3_IO16                         = IOMUX_PAD(0x03D0, 0x0144, 5, 0x0000, 0, 0),
@@ -645,6 +664,7 @@ enum {
 
 	MX6_PAD_LCD_DATA12__LCDIF_DATA12                       = IOMUX_PAD(0x03D4, 0x0148, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA12__SAI3_TX_SYNC                       = IOMUX_PAD(0x03D4, 0x0148, 1, 0x060C, 1, 0),
+	MX6_PAD_LCD_DATA12__CA7_MX6UL_TRACE12                  = IOMUX_PAD(0x03D4, 0x0148, 2, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA12__CSI_DATA20                         = IOMUX_PAD(0x03D4, 0x0148, 3, 0x0514, 1, 0),
 	MX6_PAD_LCD_DATA12__EIM_DATA04                         = IOMUX_PAD(0x03D4, 0x0148, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA12__GPIO3_IO17                         = IOMUX_PAD(0x03D4, 0x0148, 5, 0x0000, 0, 0),
@@ -653,6 +673,7 @@ enum {
 
 	MX6_PAD_LCD_DATA13__LCDIF_DATA13                       = IOMUX_PAD(0x03D8, 0x014C, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA13__SAI3_TX_BCLK                       = IOMUX_PAD(0x03D8, 0x014C, 1, 0x0608, 1, 0),
+	MX6_PAD_LCD_DATA13__CA7_MX6UL_TRACE13                  = IOMUX_PAD(0x03D8, 0x014C, 2, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA13__CSI_DATA21                         = IOMUX_PAD(0x03D8, 0x014C, 3, 0x0518, 1, 0),
 	MX6_PAD_LCD_DATA13__EIM_DATA05                         = IOMUX_PAD(0x03D8, 0x014C, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA13__GPIO3_IO18                         = IOMUX_PAD(0x03D8, 0x014C, 5, 0x0000, 0, 0),
@@ -661,6 +682,7 @@ enum {
 
 	MX6_PAD_LCD_DATA14__LCDIF_DATA14                       = IOMUX_PAD(0x03DC, 0x0150, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA14__SAI3_RX_DATA                       = IOMUX_PAD(0x03DC, 0x0150, 1, 0x0604, 1, 0),
+	MX6_PAD_LCD_DATA14__CA7_MX6UL_TRACE14                  = IOMUX_PAD(0x03DC, 0x0150, 2, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA14__CSI_DATA22                         = IOMUX_PAD(0x03DC, 0x0150, 3, 0x051C, 1, 0),
 	MX6_PAD_LCD_DATA14__EIM_DATA06                         = IOMUX_PAD(0x03DC, 0x0150, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA14__GPIO3_IO19                         = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0),
@@ -669,6 +691,7 @@ enum {
 
 	MX6_PAD_LCD_DATA15__LCDIF_DATA15                       = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA15__SAI3_TX_DATA                       = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA15__CA7_MX6UL_TRACE15                  = IOMUX_PAD(0x03E0, 0x0154, 2, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA15__CSI_DATA23                         = IOMUX_PAD(0x03E0, 0x0154, 3, 0x0520, 1, 0),
 	MX6_PAD_LCD_DATA15__EIM_DATA07                         = IOMUX_PAD(0x03E0, 0x0154, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA15__GPIO3_IO20                         = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0),
@@ -678,6 +701,7 @@ enum {
 	MX6_PAD_LCD_DATA16__LCDIF_DATA16                       = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA16__UART7_DCE_TX                       = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA16__UART7_DTE_RX                       = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0654, 2, 0),
+	MX6_PAD_LCD_DATA16__CA7_MX6UL_TRACE_CLK                = IOMUX_PAD(0x03E4, 0x0158, 2, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA16__CSI_DATA01                         = IOMUX_PAD(0x03E4, 0x0158, 3, 0x04D4, 1, 0),
 	MX6_PAD_LCD_DATA16__EIM_DATA08                         = IOMUX_PAD(0x03E4, 0x0158, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA16__GPIO3_IO21                         = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0),
@@ -687,6 +711,7 @@ enum {
 	MX6_PAD_LCD_DATA17__LCDIF_DATA17                       = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA17__UART7_DCE_RX                       = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0),
 	MX6_PAD_LCD_DATA17__UART7_DTE_TX                       = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA17__CA7_MX6UL_TRACE_CTL                = IOMUX_PAD(0x03E8, 0x015C, 2, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA17__CSI_DATA00                         = IOMUX_PAD(0x03E8, 0x015C, 3, 0x04D0, 1, 0),
 	MX6_PAD_LCD_DATA17__EIM_DATA09                         = IOMUX_PAD(0x03E8, 0x015C, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA17__GPIO3_IO22                         = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-mx6/mx6ull_pins.h b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h
index 842d0caa640..0984364fafb 100644
--- a/arch/arm/include/asm/arch-mx6/mx6ull_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h
@@ -429,6 +429,7 @@ enum {
 	MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08                    = IOMUX_PAD(0x0370, 0x00E4, 5, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_DATA0__KPP_ROW04                     = IOMUX_PAD(0x0370, 0x00E4, 6, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_DATA0__USB_OTG1_PWR                  = IOMUX_PAD(0x0370, 0x00E4, 8, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_DATA0__EPDC_SDDO08                   = IOMUX_PAD(0x0370, 0x00E4, 9, 0x0000, 0, 0),
 
 	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01                 = IOMUX_PAD(0x0374, 0x00E8, 0, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_DATA1__UART6_DCE_RX                  = IOMUX_PAD(0x0374, 0x00E8, 1, 0x064C, 2, 0),
@@ -439,6 +440,7 @@ enum {
 	MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09                    = IOMUX_PAD(0x0374, 0x00E8, 5, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_DATA1__KPP_COL04                     = IOMUX_PAD(0x0374, 0x00E8, 6, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_DATA1__USB_OTG1_OC                   = IOMUX_PAD(0x0374, 0x00E8, 8, 0x0664, 1, 0),
+	MX6_PAD_ENET2_RX_DATA1__EPDC_SDDO09                   = IOMUX_PAD(0x0374, 0x00E8, 9, 0x0000, 0, 0),
 
 	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN                      = IOMUX_PAD(0x0378, 0x00EC, 0, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_EN__UART7_DCE_TX                     = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0000, 0, 0),
@@ -449,6 +451,7 @@ enum {
 	MX6_PAD_ENET2_RX_EN__GPIO2_IO10                       = IOMUX_PAD(0x0378, 0x00EC, 5, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_EN__KPP_ROW05                        = IOMUX_PAD(0x0378, 0x00EC, 6, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M                = IOMUX_PAD(0x0378, 0x00EC, 8, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_EN__EPDC_SDDO10                      = IOMUX_PAD(0x0378, 0x00EC, 9, 0x0000, 0, 0),
 
 	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00                 = IOMUX_PAD(0x037C, 0x00F0, 0, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX                  = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0654, 1, 0),
@@ -458,6 +461,7 @@ enum {
 	MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02                    = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11                    = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_DATA0__KPP_COL05                     = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA0__EPDC_SDDO11                   = IOMUX_PAD(0x037C, 0x00F0, 9, 0x0000, 0, 0),
 
 	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01                 = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX                  = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0),
@@ -468,6 +472,7 @@ enum {
 	MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12                    = IOMUX_PAD(0x0380, 0x00F4, 5, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_DATA1__KPP_ROW06                     = IOMUX_PAD(0x0380, 0x00F4, 6, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR                  = IOMUX_PAD(0x0380, 0x00F4, 8, 0x0000, 0, 0),
+	MX6_PAD_ENET2_TX_DATA1__EPDC_SDDO12                   = IOMUX_PAD(0x0380, 0x00F4, 9, 0x0000, 0, 0),
 
 	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN                      = IOMUX_PAD(0x0384, 0x00F8, 0, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_EN__UART8_DCE_RX                     = IOMUX_PAD(0x0384, 0x00F8, 1, 0x065C, 1, 0),
@@ -478,6 +483,7 @@ enum {
 	MX6_PAD_ENET2_TX_EN__GPIO2_IO13                       = IOMUX_PAD(0x0384, 0x00F8, 5, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_EN__KPP_COL06                        = IOMUX_PAD(0x0384, 0x00F8, 6, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_EN__USB_OTG2_OC                      = IOMUX_PAD(0x0384, 0x00F8, 8, 0x0660, 1, 0),
+	MX6_PAD_ENET2_TX_EN__EPDC_SDDO13                      = IOMUX_PAD(0x0384, 0x00F8, 9, 0x0000, 0, 0),
 
 	MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK                    = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS                   = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0000, 0, 0),
@@ -488,6 +494,7 @@ enum {
 	MX6_PAD_ENET2_TX_CLK__GPIO2_IO14                      = IOMUX_PAD(0x0388, 0x00FC, 5, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_CLK__KPP_ROW07                       = IOMUX_PAD(0x0388, 0x00FC, 6, 0x0000, 0, 0),
 	MX6_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID                  = IOMUX_PAD(0x0388, 0x00FC, 8, 0x04BC, 1, 0),
+	MX6_PAD_ENET2_TX_CLK__EPDC_SDDO14                     = IOMUX_PAD(0x0388, 0x00FC, 9, 0x0000, 0, 0),
 
 	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER                      = IOMUX_PAD(0x038C, 0x0100, 0, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS                    = IOMUX_PAD(0x038C, 0x0100, 1, 0x0658, 1, 0),
@@ -498,6 +505,7 @@ enum {
 	MX6_PAD_ENET2_RX_ER__GPIO2_IO15                       = IOMUX_PAD(0x038C, 0x0100, 5, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_ER__KPP_COL07                        = IOMUX_PAD(0x038C, 0x0100, 6, 0x0000, 0, 0),
 	MX6_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY                   = IOMUX_PAD(0x038C, 0x0100, 8, 0x0000, 0, 0),
+	MX6_PAD_ENET2_RX_ER__EPDC_SDDO15                      = IOMUX_PAD(0x038C, 0x0100, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_CLK__LCDIF_CLK                            = IOMUX_PAD(0x0390, 0x0104, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_CLK__LCDIF_WR_RWN                         = IOMUX_PAD(0x0390, 0x0104, 1, 0x0000, 0, 0),
@@ -507,6 +515,7 @@ enum {
 	MX6_PAD_LCD_CLK__EIM_CS2_B                            = IOMUX_PAD(0x0390, 0x0104, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_CLK__GPIO3_IO00                           = IOMUX_PAD(0x0390, 0x0104, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB                 = IOMUX_PAD(0x0390, 0x0104, 8, 0x0000, 0, 0),
+	MX6_PAD_LCD_CLK__EPDC_SDCLK                           = IOMUX_PAD(0x0390, 0x0104, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_ENABLE__LCDIF_ENABLE                      = IOMUX_PAD(0x0394, 0x0108, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_ENABLE__LCDIF_RD_E                        = IOMUX_PAD(0x0394, 0x0108, 1, 0x0000, 0, 0),
@@ -516,6 +525,7 @@ enum {
 	MX6_PAD_LCD_ENABLE__EIM_CS3_B                         = IOMUX_PAD(0x0394, 0x0108, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_ENABLE__GPIO3_IO01                        = IOMUX_PAD(0x0394, 0x0108, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_ENABLE__ECSPI2_RDY                        = IOMUX_PAD(0x0394, 0x0108, 8, 0x0000, 0, 0),
+	MX6_PAD_LCD_ENABLE__EPDC_SDLE                         = IOMUX_PAD(0x0394, 0x0108, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_HSYNC__LCDIF_HSYNC                        = IOMUX_PAD(0x0398, 0x010C, 0, 0x05DC, 0, 0),
 	MX6_PAD_LCD_HSYNC__LCDIF_RS                           = IOMUX_PAD(0x0398, 0x010C, 1, 0x0000, 0, 0),
@@ -525,6 +535,7 @@ enum {
 	MX6_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB               = IOMUX_PAD(0x0398, 0x010C, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_HSYNC__GPIO3_IO02                         = IOMUX_PAD(0x0398, 0x010C, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_HSYNC__ECSPI2_SS1                         = IOMUX_PAD(0x0398, 0x010C, 8, 0x0000, 0, 0),
+	MX6_PAD_LCD_HSYNC__EPDC_SDOE                          = IOMUX_PAD(0x0398, 0x010C, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_VSYNC__LCDIF_VSYNC                        = IOMUX_PAD(0x039C, 0x0110, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_VSYNC__LCDIF_BUSY                         = IOMUX_PAD(0x039C, 0x0110, 1, 0x05DC, 1, 0),
@@ -534,6 +545,7 @@ enum {
 	MX6_PAD_LCD_VSYNC__WDOG2_WDOG_B                       = IOMUX_PAD(0x039C, 0x0110, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_VSYNC__GPIO3_IO03                         = IOMUX_PAD(0x039C, 0x0110, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_VSYNC__ECSPI2_SS2                         = IOMUX_PAD(0x039C, 0x0110, 8, 0x0000, 0, 0),
+	MX6_PAD_LCD_VSYNC__EPDC_SDCE0                         = IOMUX_PAD(0x039C, 0x0110, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_RESET__LCDIF_RESET                        = IOMUX_PAD(0x03A0, 0x0114, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_RESET__LCDIF_CS                           = IOMUX_PAD(0x03A0, 0x0114, 1, 0x0000, 0, 0),
@@ -542,6 +554,7 @@ enum {
 	MX6_PAD_LCD_RESET__WDOG1_WDOG_ANY                     = IOMUX_PAD(0x03A0, 0x0114, 4, 0x0000, 0, 0),
 	MX6_PAD_LCD_RESET__GPIO3_IO04                         = IOMUX_PAD(0x03A0, 0x0114, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_RESET__ECSPI2_SS3                         = IOMUX_PAD(0x03A0, 0x0114, 8, 0x0000, 0, 0),
+	MX6_PAD_LCD_RESET__EPDC_GDOE                          = IOMUX_PAD(0x03A0, 0x0114, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA00__LCDIF_DATA00                      = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA00__PWM1_OUT                          = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0),
@@ -550,6 +563,7 @@ enum {
 	MX6_PAD_LCD_DATA00__GPIO3_IO05                        = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA00__SRC_BT_CFG00                      = IOMUX_PAD(0x03A4, 0x0118, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA00__SAI1_MCLK                         = IOMUX_PAD(0x03A4, 0x0118, 8, 0x05E0, 1, 0),
+	MX6_PAD_LCD_DATA00__EPDC_SDDO00                       = IOMUX_PAD(0x03A4, 0x0118, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA01__LCDIF_DATA01                      = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA01__PWM2_OUT                          = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0),
@@ -558,6 +572,7 @@ enum {
 	MX6_PAD_LCD_DATA01__GPIO3_IO06                        = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA01__SRC_BT_CFG01                      = IOMUX_PAD(0x03A8, 0x011C, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA01__SAI1_TX_SYNC                      = IOMUX_PAD(0x03A8, 0x011C, 8, 0x05EC, 0, 0),
+	MX6_PAD_LCD_DATA01__EPDC_SDDO01                       = IOMUX_PAD(0x03A8, 0x011C, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA02__LCDIF_DATA02                      = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA02__PWM3_OUT                          = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0),
@@ -566,6 +581,7 @@ enum {
 	MX6_PAD_LCD_DATA02__GPIO3_IO07                        = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA02__SRC_BT_CFG02                      = IOMUX_PAD(0x03AC, 0x0120, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA02__SAI1_TX_BCLK                      = IOMUX_PAD(0x03AC, 0x0120, 8, 0x05E8, 0, 0),
+	MX6_PAD_LCD_DATA02__EPDC_SDDO02                       = IOMUX_PAD(0x03AC, 0x0120, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA03__LCDIF_DATA03                      = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA03__PWM4_OUT                          = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0),
@@ -574,6 +590,7 @@ enum {
 	MX6_PAD_LCD_DATA03__GPIO3_IO08                        = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA03__SRC_BT_CFG03                      = IOMUX_PAD(0x03B0, 0x0124, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA03__SAI1_RX_DATA                      = IOMUX_PAD(0x03B0, 0x0124, 8, 0x05E4, 0, 0),
+	MX6_PAD_LCD_DATA03__EPDC_SDDO03                       = IOMUX_PAD(0x03B0, 0x0124, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA04__LCDIF_DATA04                      = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA04__UART8_DCE_CTS                     = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0),
@@ -583,6 +600,7 @@ enum {
 	MX6_PAD_LCD_DATA04__GPIO3_IO09                        = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA04__SRC_BT_CFG04                      = IOMUX_PAD(0x03B4, 0x0128, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA04__SAI1_TX_DATA                      = IOMUX_PAD(0x03B4, 0x0128, 8, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA04__EPDC_SDDO04                       = IOMUX_PAD(0x03B4, 0x0128, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA05__LCDIF_DATA05                      = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA05__UART8_DCE_RTS                     = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0),
@@ -592,6 +610,7 @@ enum {
 	MX6_PAD_LCD_DATA05__GPIO3_IO10                        = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA05__SRC_BT_CFG05                      = IOMUX_PAD(0x03B8, 0x012C, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA05__ECSPI1_SS1                        = IOMUX_PAD(0x03B8, 0x012C, 8, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA05__EPDC_SDDO05                       = IOMUX_PAD(0x03B8, 0x012C, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA06__LCDIF_DATA06                      = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA06__UART7_DCE_CTS                     = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0),
@@ -601,6 +620,7 @@ enum {
 	MX6_PAD_LCD_DATA06__GPIO3_IO11                        = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA06__SRC_BT_CFG06                      = IOMUX_PAD(0x03BC, 0x0130, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA06__ECSPI1_SS2                        = IOMUX_PAD(0x03BC, 0x0130, 8, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA06__EPDC_SDDO06                       = IOMUX_PAD(0x03BC, 0x0130, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA07__LCDIF_DATA07                      = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA07__UART7_DCE_RTS                     = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0),
@@ -610,6 +630,7 @@ enum {
 	MX6_PAD_LCD_DATA07__GPIO3_IO12                        = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA07__SRC_BT_CFG07                      = IOMUX_PAD(0x03C0, 0x0134, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA07__ECSPI1_SS3                        = IOMUX_PAD(0x03C0, 0x0134, 8, 0x0000, 0, 0),
+	MX6_PAD_LCD_DATA07__EPDC_SDDO07                       = IOMUX_PAD(0x03C0, 0x0134, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA08__LCDIF_DATA08                      = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA08__SPDIF_IN                          = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0),
@@ -666,6 +687,7 @@ enum {
 	MX6_PAD_LCD_DATA14__GPIO3_IO19                        = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA14__SRC_BT_CFG14                      = IOMUX_PAD(0x03DC, 0x0150, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA14__USDHC2_DATA4                      = IOMUX_PAD(0x03DC, 0x0150, 8, 0x068C, 0, 0),
+	MX6_PAD_LCD_DATA14__EPDC_SDSHR                        = IOMUX_PAD(0x03DC, 0x0150, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA15__LCDIF_DATA15                      = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA15__SAI3_TX_DATA                      = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0),
@@ -674,6 +696,7 @@ enum {
 	MX6_PAD_LCD_DATA15__GPIO3_IO20                        = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA15__SRC_BT_CFG15                      = IOMUX_PAD(0x03E0, 0x0154, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA15__USDHC2_DATA5                      = IOMUX_PAD(0x03E0, 0x0154, 8, 0x0690, 0, 0),
+	MX6_PAD_LCD_DATA15__EPDC_GDRL                         = IOMUX_PAD(0x03E0, 0x0154, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA16__LCDIF_DATA16                      = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA16__UART7_DCE_TX                      = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0),
@@ -683,6 +706,7 @@ enum {
 	MX6_PAD_LCD_DATA16__GPIO3_IO21                        = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA16__SRC_BT_CFG24                      = IOMUX_PAD(0x03E4, 0x0158, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA16__USDHC2_DATA6                      = IOMUX_PAD(0x03E4, 0x0158, 8, 0x0694, 0, 0),
+	MX6_PAD_LCD_DATA16__EPDC_GDCLK                        = IOMUX_PAD(0x03E4, 0x0158, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA17__LCDIF_DATA17                      = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA17__UART7_DCE_RX                      = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0),
@@ -692,6 +716,7 @@ enum {
 	MX6_PAD_LCD_DATA17__GPIO3_IO22                        = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA17__SRC_BT_CFG25                      = IOMUX_PAD(0x03E8, 0x015C, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA17__USDHC2_DATA7                      = IOMUX_PAD(0x03E8, 0x015C, 8, 0x0698, 0, 0),
+	MX6_PAD_LCD_DATA17__EPDC_GDSP                         = IOMUX_PAD(0x03E8, 0x015C, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA18__LCDIF_DATA18                      = IOMUX_PAD(0x03EC, 0x0160, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA18__PWM5_OUT                          = IOMUX_PAD(0x03EC, 0x0160, 1, 0x0000, 0, 0),
@@ -730,6 +755,7 @@ enum {
 	MX6_PAD_LCD_DATA21__GPIO3_IO26                        = IOMUX_PAD(0x03F8, 0x016C, 5, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA21__SRC_BT_CFG29                      = IOMUX_PAD(0x03F8, 0x016C, 6, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA21__USDHC2_DATA1                      = IOMUX_PAD(0x03F8, 0x016C, 8, 0x0680, 1, 0),
+	MX6_PAD_LCD_DATA21__EPDC_SDCE1                        = IOMUX_PAD(0x03F8, 0x016C, 9, 0x0000, 0, 0),
 
 	MX6_PAD_LCD_DATA22__LCDIF_DATA22                      = IOMUX_PAD(0x03FC, 0x0170, 0, 0x0000, 0, 0),
 	MX6_PAD_LCD_DATA22__MQS_RIGHT                         = IOMUX_PAD(0x03FC, 0x0170, 1, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index c49759af92d..412acbf1bcf 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -39,4 +39,16 @@ static inline void iomuxc_set_rgmii_io_voltage(int io_vol)
 	__raw_writel(io_vol, IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII);
 }
 
+void set_wdog_reset(struct wdog_regs *wdog);
+enum boot_device get_boot_device(void);
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+int check_ldo_bypass(void);
+int check_1_2G(void);
+int set_anatop_bypass(int wdog_reset_pin);
+void ldo_mode_set(int ldo_bypass);
+void prep_anatop_bypass(void);
+void finish_anatop_bypass(void);
+#endif
+
 #endif /* __SYS_PROTO_IMX6_ */
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index 5cab12f30d8..dec03176d29 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -18,7 +18,7 @@
 #define GIC400_ARB_END_ADDR             0x31007FFF
 #define APBH_DMA_ARB_BASE_ADDR          0x33000000
 #define APBH_DMA_ARB_END_ADDR           0x33007FFF
-#define M4_BOOTROM_BASE_ADDR            0x00180000
+#define MCU_BOOTROM_BASE_ADDR            0x00180000
 
 #define MXS_APBH_BASE			APBH_DMA_ARB_BASE_ADDR
 #define MXS_GPMI_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x02000)
@@ -143,7 +143,7 @@
 #define ELCDIF1_IPS_BASE_ADDR           (AIPS2_OFF_BASE_ADDR+0x130000)
 #define MIPI_CSI2_IPS_BASE_ADDR         (AIPS2_OFF_BASE_ADDR+0x150000)
 #define MIPI_DSI_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR+0x160000)
-#define IP2APB_TZASC1_IPS_BASE_ADDR     (AIPS2_OFF_BASE_ADDR+0x180000)
+#define IP2APB_TZASC1_BASE_ADDR     	(AIPS2_OFF_BASE_ADDR+0x180000)
 #define DDRPHY_IPS_BASE_ADDR            (AIPS2_OFF_BASE_ADDR+0x190000)
 #define DDRC_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x1A0000)
 #define IP2APB_PERFMON1_IPS_BASE_ADDR   (AIPS2_OFF_BASE_ADDR+0x1C0000)
@@ -212,6 +212,10 @@
 #define SEMAPHORE1_BASE_ADDR SEMA41_IPS_BASE_ADDR
 #define SEMAPHORE2_BASE_ADDR SEMA42_IPS_BASE_ADDR
 #define RDC_BASE_ADDR RDC_IPS_BASE_ADDR
+#define REGS_QOS_BASE     QOSC_IPS_BASE_ADDR
+#define REGS_QOS_EPDC     (QOSC_IPS_BASE_ADDR + 0x3400)
+#define REGS_QOS_PXP0     (QOSC_IPS_BASE_ADDR + 0x2C00)
+#define REGS_QOS_PXP1     (QOSC_IPS_BASE_ADDR + 0x3C00)
 
 #define FEC_QUIRK_ENET_MAC
 #define SNVS_LPGPR	0x68
@@ -834,6 +838,7 @@ struct src {
 #define IMX7D_GPR5_CSI1_MUX_CTRL_MIPI_CSI		(0x1 << 4)
 
 struct iomuxc {
+	u32 reserved[0x4000];
 	u32 gpr[23];
 	/* mux and pad registers */
 };
@@ -1169,10 +1174,14 @@ extern void check_cpu_temperature(void);
 extern void pcie_power_up(void);
 extern void pcie_power_off(void);
 
+#include <stdbool.h>
+bool is_usb_boot(void);
+#define is_boot_from_usb  is_usb_boot
+
 /* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB
  * If boot from the other mode, USB0_PWD will keep reset value
  */
-#define	is_boot_from_usb(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \
+#define	is_usbotg_boot_enabled(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \
 	readl(USBOTG2_IPS_BASE_ADDR + 0x158))
 #define	disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140)
 
diff --git a/arch/arm/include/asm/arch-mx7/snvs.h b/arch/arm/include/asm/arch-mx7/snvs.h
new file mode 100644
index 00000000000..a18f8535109
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/snvs.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX7_SNVS_H__
+#define __MX7_SNVS_H__
+
+#define SNVS_HPCOMR			SNVS_BASE_ADDR + 0x04
+#define SNVS_HPSICR			SNVS_BASE_ADDR + 0x0C
+#define SNVS_HPSVCR			SNVS_BASE_ADDR + 0x10
+#define SNVS_HPSR			SNVS_BASE_ADDR + 0x14
+#define SNVS_HPSVSR			SNVS_BASE_ADDR + 0x18
+#define SNVS_LPCR			SNVS_BASE_ADDR + 0x38
+#define SNVS_LPMKCR			SNVS_BASE_ADDR + 0x3C
+#define SNVS_LPTGFCR		SNVS_BASE_ADDR + 0x44
+#define SNVS_LPTDCR			SNVS_BASE_ADDR + 0x48
+#define SNVS_LPSR			SNVS_BASE_ADDR + 0x4C
+#define SNVS_LPPGDR			SNVS_BASE_ADDR + 0x64
+#define SNVS_LPZMKR0		SNVS_BASE_ADDR + 0x6C
+#define SNVS_LPZMKR1		SNVS_BASE_ADDR + 0x70
+#define SNVS_LPZMKR2		SNVS_BASE_ADDR + 0x74
+#define SNVS_LPZMKR3		SNVS_BASE_ADDR + 0x78
+#define SNVS_LPZMKR4		SNVS_BASE_ADDR + 0x7C
+#define SNVS_LPZMKR5		SNVS_BASE_ADDR + 0x80
+#define SNVS_LPZMKR6		SNVS_BASE_ADDR + 0x84
+#define SNVS_LPZMKR7		SNVS_BASE_ADDR + 0x88
+#define SNVS_LPTDC2R		SNVS_BASE_ADDR + 0xA0
+#define SNVS_LPTDSR			SNVS_BASE_ADDR + 0xA4
+#define SNVS_LPTGF1CR		SNVS_BASE_ADDR + 0xA8
+#define SNVS_LPTGF2CR		SNVS_BASE_ADDR + 0xAC
+#define SNVS_LPAT1CR		SNVS_BASE_ADDR + 0xC0
+#define SNVS_LPATCTLR		SNVS_BASE_ADDR + 0xE0
+#define SNVS_LPATCLKR		SNVS_BASE_ADDR + 0xE4
+#define SNVS_LPATRC1R		SNVS_BASE_ADDR + 0xE8
+#define SNVS_LPATRC2R		SNVS_BASE_ADDR + 0xEC
+
+#define AT5_POLYSEED		0x12345678
+
+#endif
diff --git a/arch/arm/include/asm/arch-mx7ulp/clock.h b/arch/arm/include/asm/arch-mx7ulp/clock.h
index 92d4463dff5..150c145eafb 100644
--- a/arch/arm/include/asm/arch-mx7ulp/clock.h
+++ b/arch/arm/include/asm/arch-mx7ulp/clock.h
@@ -15,7 +15,7 @@ enum mxc_clock {
 	MXC_AHB_CLK,
 	MXC_IPG_CLK,
 	MXC_UART_CLK,
-	MXC_CSPI_CLK,
+	MXC_LPSPI_CLK,
 	MXC_AXI_CLK,
 	MXC_DDR_CLK,
 	MXC_ESDHC_CLK,
@@ -29,12 +29,19 @@ u32 get_lpuart_clk(void);
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 u32 imx_get_i2cclk(unsigned i2c_num);
 #endif
+#ifdef CONFIG_FSL_LPSPI
+int enable_lpspi_clk(unsigned char enable, unsigned spi_num);
+u32 imx_get_spiclk(unsigned spi_num);
+#endif
 #ifdef CONFIG_MXC_OCOTP
 void enable_ocotp_clk(unsigned char enable);
 #endif
 #ifdef CONFIG_USB_EHCI_HCD
 void enable_usboh3_clk(unsigned char enable);
+int enable_usb_pll(ulong usb_phy_base);
 #endif
+void enable_mipi_dsi_clk(unsigned char enable);
+void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq_in_khz);
 void init_clk_usdhc(u32 index);
 void clock_init(void);
 void hab_caam_clock_enable(unsigned char enable);
diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
index cb0c2c15c03..4103c6ec8a6 100644
--- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
@@ -67,6 +67,8 @@
 #define SIM1_PCC1_SLOT			(48)
 #define MMDC0_AIPS3_SLOT		(43)
 #define IOMUXC_DDR_AIPS3_SLOT		(45)
+#define DSI_AIPS3_SLOT			(41)
+#define LCDIF_AIPS3_SLOT		(42)
 
 #define LPI2C0_AIPS0_SLOT		(51)
 #define LPI2C1_AIPS0_SLOT		(52)
@@ -129,6 +131,9 @@
 #define SIM_SOPT1_PMIC_STBY_REQ		(1<<2)
 #define SIM_SOPT1_A7_SW_RESET		(1<<0)
 
+#define WKPU_WAKEUP_EN			0x88
+#define WKPU_QSPI_CHANNEL		BIT(20)
+
 #define IOMUXC_PCR_MUX_ALT_SHIFT	(8)
 #define IOMUXC_PCR_MUX_ALT_MASK		(0xF00)
 #define IOMUXC_PSMI_IMUX_ALT_SHIFT	(0)
@@ -180,6 +185,10 @@
 #define USDHC0_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT)))
 #define USDHC1_RBASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT)))
 
+#define LCDIF_RBASE	((AIPS3_BASE + (AIPS3_SLOT_SIZE * LCDIF_AIPS3_SLOT)))
+#define MXS_LCDIF_BASE	LCDIF_RBASE
+
+
 #define SNVS_BASE	((AIPS2_BASE + (AIPS2_SLOT_SIZE * SNVS_AIPS2_SLOT)))
 #define SNVS_LP_LPCR	(SNVS_BASE + 0x38)
 
@@ -957,12 +966,15 @@
 
 #define SNVS_LPCR_DPEN				(0x20)
 #define SNVS_LPCR_SRTC_ENV			(0x1)
+#define SNVS_BASE_REVB				(0x41070000)
+#define SNVS_HPSR_REVB				(SNVS_BASE_REVB + 0x14)
 
 #define SRC_BASE_ADDR			CMC1_RBASE
 #define IRAM_BASE_ADDR			OCRAM_0_BASE
 #define IOMUXC_BASE_ADDR		IOMUXC1_RBASE
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/mach-imx/regs-lcdif.h>
 
 #include <asm/types.h>
 
@@ -1149,7 +1161,9 @@ struct bootrom_sw_info {
 	u32 reserved_3[3];
 };
 
-#define	is_boot_from_usb(void)		(!(readl(USB_PHY0_BASE_ADDR) & (1<<20)))
+#include <stdbool.h>
+bool is_usb_boot(void);
+#define is_boot_from_usb  is_usb_boot
 #define	disconnect_from_pc(void)	writel(0x0, USBOTG0_RBASE + 0x140)
 
 #endif
diff --git a/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h b/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h
index 139b766c261..1e19745d145 100644
--- a/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h
+++ b/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h
@@ -12,7 +12,7 @@ enum {
 	MX7ULP_PAD_PTA0__CMP0_IN1_3V                                 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA0__PTA0                                        = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA0__LPSPI0_PCS1                                 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x2, 0),
-	MX7ULP_PAD_PTA0__LPUART0_CTS_b                               = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x2, 0),
+	MX7ULP_PAD_PTA0__LPUART0_CTS_B                               = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x2, 0),
 	MX7ULP_PAD_PTA0__LPI2C0_SCL                                  = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x2, 0),
 	MX7ULP_PAD_PTA0__TPM0_CLKIN                                  = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x2, 0),
 	MX7ULP_PAD_PTA0__I2S0_RX_BCLK                                = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8, 0x2, 0),
@@ -20,7 +20,7 @@ enum {
 	MX7ULP_PAD_PTA1__CMP0_IN2_3V                                 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA1__PTA1                                        = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA1__LPSPI0_PCS2                                 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x1, 0),
-	MX7ULP_PAD_PTA1__LPUART0_RTS_b                               = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA1__LPUART0_RTS_B                               = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA1__LPI2C0_SDA                                  = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x1, 0),
 	MX7ULP_PAD_PTA1__TPM0_CH0                                    = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x1, 0),
 	MX7ULP_PAD_PTA1__I2S0_RX_FS                                  = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x7, 0xD1BC, 0x1, 0),
@@ -42,72 +42,72 @@ enum {
 	MX7ULP_PAD_PTA4__ADC1_CH3A                                   = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA4__PTA4                                        = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA4__LPSPI0_SIN                                  = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x1, 0),
-	MX7ULP_PAD_PTA4__LPUART1_CTS_b                               = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x1, 0),
+	MX7ULP_PAD_PTA4__LPUART1_CTS_B                               = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x1, 0),
 	MX7ULP_PAD_PTA4__LPI2C1_SCL                                  = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x1, 0),
 	MX7ULP_PAD_PTA4__TPM0_CH3                                    = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x6, 0xD144, 0x1, 0),
 	MX7ULP_PAD_PTA4__I2S0_MCLK                                   = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B4, 0x1, 0),
 	MX7ULP_PAD_PTA5__ADC1_CH3B                                   = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA5__PTA5                                        = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA5__LPSPI0_SOUT                                 = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x1, 0),
-	MX7ULP_PAD_PTA5__LPUART1_RTS_b                               = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA5__LPUART1_RTS_B                               = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA5__LPI2C1_SDA                                  = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x1, 0),
 	MX7ULP_PAD_PTA5__TPM0_CH4                                    = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x6, 0xD148, 0x1, 0),
 	MX7ULP_PAD_PTA5__I2S0_TX_BCLK                                = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C0, 0x1, 0),
-	MX7ULP_PAD_PTA6__ADC1_CH4A_5A_6A_7A_8A                       = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA6__ADC1_CH4A                                   = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA6__PTA6                                        = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA6__LPSPI0_SCK                                  = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x1, 0),
 	MX7ULP_PAD_PTA6__LPUART1_TX                                  = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x1, 0),
 	MX7ULP_PAD_PTA6__LPI2C1_HREQ                                 = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x1, 0),
 	MX7ULP_PAD_PTA6__TPM0_CH5                                    = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x6, 0xD14C, 0x1, 0),
 	MX7ULP_PAD_PTA6__I2S0_TX_FS                                  = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C4, 0x1, 0),
-	MX7ULP_PAD_PTA7__ADC1_CH4B_5B_6B_7B_8B                       = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA7__ADC1_CH4B                                   = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA7__PTA7                                        = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA7__LPUART1_RX                                  = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x1, 0),
 	MX7ULP_PAD_PTA7__TPM1_CH1                                    = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x1, 0),
 	MX7ULP_PAD_PTA7__I2S0_TXD0                                   = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTA8__ADC1_CH4A_5A_6A_7A_8A                       = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA8__ADC1_CH5A                                   = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA8__PTA8                                        = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA8__LPSPI1_PCS1                                 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x1, 0),
-	MX7ULP_PAD_PTA8__LPUART2_CTS_b                               = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x1, 0),
+	MX7ULP_PAD_PTA8__LPUART2_CTS_B                               = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x1, 0),
 	MX7ULP_PAD_PTA8__LPI2C2_SCL                                  = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x1, 0),
 	MX7ULP_PAD_PTA8__TPM1_CLKIN                                  = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x1, 0),
 	MX7ULP_PAD_PTA8__I2S0_TXD1                                   = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTA9__ADC1_CH4B_5B_6B_7B_8B                       = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA9__ADC1_CH5B                                   = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA9__PTA9                                        = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA9__LPSPI1_PCS2                                 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x1, 0),
-	MX7ULP_PAD_PTA9__LPUART2_RTS_b                               = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA9__LPUART2_RTS_B                               = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA9__LPI2C2_SDA                                  = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x1, 0),
 	MX7ULP_PAD_PTA9__TPM1_CH0                                    = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x1, 0),
-	MX7ULP_PAD_PTA9__NMI0_b                                      = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTA10__ADC1_CH4A_5A_6A_7A_8A                      = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA9__NMI0_B                                      = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA10__ADC1_CH6A                                  = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA10__PTA10                                      = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA10__LPSPI1_PCS3                                = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x1, 0),
 	MX7ULP_PAD_PTA10__LPUART2_TX                                 = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x1, 0),
 	MX7ULP_PAD_PTA10__LPI2C2_HREQ                                = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x1, 0),
 	MX7ULP_PAD_PTA10__TPM2_CLKIN                                 = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x1, 0),
 	MX7ULP_PAD_PTA10__I2S0_RX_BCLK                               = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8, 0x1, 0),
-	MX7ULP_PAD_PTA11__ADC1_CH4B_5B_6B_7B_8B                      = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA11__ADC1_CH6B                                  = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA11__PTA11                                      = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA11__LPUART2_RX                                 = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x1, 0),
 	MX7ULP_PAD_PTA11__TPM2_CH0                                   = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x1, 0),
 	MX7ULP_PAD_PTA11__I2S0_RX_FS                                 = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1BC, 0x2, 0),
-	MX7ULP_PAD_PTA12__ADC1_CH4A_5A_6A_7A_8A                      = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA12__ADC1_CH7A                                  = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA12__PTA12                                      = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA12__LPSPI1_SIN                                 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x1, 0),
-	MX7ULP_PAD_PTA12__LPUART3_CTS_b                              = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x1, 0),
+	MX7ULP_PAD_PTA12__LPUART3_CTS_B                              = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x1, 0),
 	MX7ULP_PAD_PTA12__LPI2C3_SCL                                 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x1, 0),
 	MX7ULP_PAD_PTA12__TPM2_CH1                                   = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x1, 0),
 	MX7ULP_PAD_PTA12__I2S0_RXD0                                  = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x7, 0xD1DC, 0x2, 0),
-	MX7ULP_PAD_PTA13__ADC1_CH4B_5B_6B_7B_8B                      = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA13__ADC1_CH7B                                  = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA13__PTA13                                      = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA13__LPSPI1_SOUT                                = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x2, 0),
-	MX7ULP_PAD_PTA13__LPUART3_RTS_b                              = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA13__LPUART3_RTS_B                              = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA13__LPI2C3_SDA                                 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x2, 0),
 	MX7ULP_PAD_PTA13__TPM3_CLKIN                                 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x1, 0),
 	MX7ULP_PAD_PTA13__I2S0_RXD1                                  = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E0, 0x2, 0),
 	MX7ULP_PAD_PTA13__CMP0_OUT                                   = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA13__LLWU0_P2                                   = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTA14__ADC1_CH4A_5A_6A_7A_8A                      = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA14__ADC1_CH8A                                  = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA14__PTA14                                      = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA14__LPSPI1_SCK                                 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x2, 0),
 	MX7ULP_PAD_PTA14__LPUART3_TX                                 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x2, 0),
@@ -115,7 +115,7 @@ enum {
 	MX7ULP_PAD_PTA14__TPM3_CH0                                   = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x1, 0),
 	MX7ULP_PAD_PTA14__I2S0_MCLK                                  = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B4, 0x2, 0),
 	MX7ULP_PAD_PTA14__LLWU0_P3                                   = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTA15__ADC1_CH4B_5B_6B_7B_8B                      = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA15__ADC1_CH8B                                  = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA15__PTA15                                      = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA15__LPSPI1_PCS0                                = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x1, 0),
 	MX7ULP_PAD_PTA15__LPUART3_RX                                 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x1, 0),
@@ -125,7 +125,7 @@ enum {
 	MX7ULP_PAD_PTA16__PTA16                                      = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA16__FXIO0_D0                                   = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA16__LPSPI0_SOUT                                = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x2, 0),
-	MX7ULP_PAD_PTA16__LPUART0_CTS_b                              = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x1, 0),
+	MX7ULP_PAD_PTA16__LPUART0_CTS_B                              = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x1, 0),
 	MX7ULP_PAD_PTA16__LPI2C0_SCL                                 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x1, 0),
 	MX7ULP_PAD_PTA16__TPM3_CH2                                   = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x6, 0xD168, 0x1, 0),
 	MX7ULP_PAD_PTA16__I2S0_TX_FS                                 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C4, 0x2, 0),
@@ -133,7 +133,7 @@ enum {
 	MX7ULP_PAD_PTA17__PTA17                                      = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA17__FXIO0_D1                                   = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA17__LPSPI0_SCK                                 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x2, 0),
-	MX7ULP_PAD_PTA17__LPUART0_RTS_b                              = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA17__LPUART0_RTS_B                              = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA17__LPI2C0_SDA                                 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x2, 0),
 	MX7ULP_PAD_PTA17__TPM3_CH3                                   = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x6, 0xD16C, 0x1, 0),
 	MX7ULP_PAD_PTA17__I2S0_TXD0                                  = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
@@ -154,23 +154,23 @@ enum {
 	MX7ULP_PAD_PTA19__I2S1_RX_BCLK                               = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1CC, 0x1, 0),
 	MX7ULP_PAD_PTA19__LPTMR0_ALT3                                = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA19__LLWU0_P5                                   = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTA20__ADC0_CH8A_9A_10A                           = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA20__ADC0_10A                                   = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA20__PTA20                                      = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA20__FXIO0_D4                                   = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA20__LPSPI0_SIN                                 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x2, 0),
-	MX7ULP_PAD_PTA20__LPUART1_CTS_b                              = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x2, 0),
+	MX7ULP_PAD_PTA20__LPUART1_CTS_B                              = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x2, 0),
 	MX7ULP_PAD_PTA20__LPI2C1_SCL                                 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x2, 0),
 	MX7ULP_PAD_PTA20__TPM0_CLKIN                                 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x1, 0),
 	MX7ULP_PAD_PTA20__I2S1_RX_FS                                 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D0, 0x1, 0),
-	MX7ULP_PAD_PTA21__ADC0_CH8B_9B_10B                           = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA21__ADC0_CH10B                                 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA21__PTA21                                      = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA21__FXIO0_D5                                   = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA21__LPSPI0_PCS1                                = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x1, 0),
-	MX7ULP_PAD_PTA21__LPUART1_RTS_b                              = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA21__LPUART1_RTS_B                              = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA21__LPI2C1_SDA                                 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x2, 0),
 	MX7ULP_PAD_PTA21__TPM0_CH0                                   = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x2, 0),
 	MX7ULP_PAD_PTA21__I2S1_RXD0                                  = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E4, 0x1, 0),
-	MX7ULP_PAD_PTA22__ADC0_CH8A_9A_10A                           = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA22__ADC0_CH9A                                  = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA22__PTA22                                      = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA22__FXIO0_D6                                   = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA22__LPSPI0_PCS2                                = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x2, 0),
@@ -179,8 +179,8 @@ enum {
 	MX7ULP_PAD_PTA22__TPM0_CH1                                   = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x2, 0),
 	MX7ULP_PAD_PTA22__I2S1_RXD1                                  = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E8, 0x1, 0),
 	MX7ULP_PAD_PTA22__LPTMR0_ALT2                                = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTA22__EWM_OUT_b                                  = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTA23__ADC0_CH8B_9B_10B                           = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA22__EWM_OUT_B                                  = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA23__ADC0_CH9B                                  = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA23__PTA23                                      = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA23__FXIO0_D7                                   = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA23__LPSPI0_PCS3                                = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x2, 0),
@@ -188,19 +188,19 @@ enum {
 	MX7ULP_PAD_PTA23__TPM0_CH2                                   = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x6, 0xD140, 0x2, 0),
 	MX7ULP_PAD_PTA23__I2S1_MCLK                                  = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C8, 0x1, 0),
 	MX7ULP_PAD_PTA23__LLWU0_P6                                   = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTA24__ADC0_CH8A_9A_10A                           = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA24__ADC0_CH8A                                  = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA24__PTA24                                      = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA24__FXIO0_D8                                   = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA24__LPSPI1_PCS1                                = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x2, 0),
-	MX7ULP_PAD_PTA24__LPUART2_CTS_b                              = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x2, 0),
+	MX7ULP_PAD_PTA24__LPUART2_CTS_B                              = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x2, 0),
 	MX7ULP_PAD_PTA24__LPI2C2_SCL                                 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x2, 0),
 	MX7ULP_PAD_PTA24__TPM0_CH3                                   = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x6, 0xD144, 0x2, 0),
 	MX7ULP_PAD_PTA24__I2S1_TX_BCLK                               = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D4, 0x1, 0),
-	MX7ULP_PAD_PTA25__ADC0_CH8B_9B_10B                           = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA25__ADC0_CH8B                                  = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA25__PTA25                                      = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA25__FXIO0_D9                                   = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA25__LPSPI1_PCS2                                = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x2, 0),
-	MX7ULP_PAD_PTA25__LPUART2_RTS_b                              = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA25__LPUART2_RTS_B                              = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA25__LPI2C2_SDA                                 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x2, 0),
 	MX7ULP_PAD_PTA25__TPM0_CH4                                   = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x6, 0xD148, 0x2, 0),
 	MX7ULP_PAD_PTA25__I2S1_TX_FS                                 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D8, 0x1, 0),
@@ -222,7 +222,7 @@ enum {
 	MX7ULP_PAD_PTA28__JTAG_TDI                                   = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA28__FXIO0_D12                                  = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA28__LPSPI1_SIN                                 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x2, 0),
-	MX7ULP_PAD_PTA28__LPUART3_CTS_b                              = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x2, 0),
+	MX7ULP_PAD_PTA28__LPUART3_CTS_B                              = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x2, 0),
 	MX7ULP_PAD_PTA28__LPI2C3_SCL                                 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x2, 0),
 	MX7ULP_PAD_PTA28__TPM1_CLKIN                                 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x2, 0),
 	MX7ULP_PAD_PTA28__I2S1_TXD2                                  = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
@@ -230,7 +230,7 @@ enum {
 	MX7ULP_PAD_PTA29__JTAG_TCLK_SWD_CLK                          = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA29__FXIO0_D13                                  = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA29__LPSPI1_SOUT                                = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x1, 0),
-	MX7ULP_PAD_PTA29__LPUART3_RTS_b                              = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA29__LPUART3_RTS_B                              = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA29__LPI2C3_SDA                                 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x1, 0),
 	MX7ULP_PAD_PTA29__TPM1_CH0                                   = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x2, 0),
 	MX7ULP_PAD_PTA29__I2S1_TXD3                                  = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
@@ -242,7 +242,7 @@ enum {
 	MX7ULP_PAD_PTA30__LPI2C3_HREQ                                = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x1, 0),
 	MX7ULP_PAD_PTA30__TPM2_CLKIN                                 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x2, 0),
 	MX7ULP_PAD_PTA30__I2S1_TXD0                                  = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTA30__JTAG_TRST_b                                = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTA30__JTAG_TRST_B                                = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA31__ADC0_CH1B                                  = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA31__PTA31                                      = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTA31__FXIO0_D15                                  = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
@@ -261,7 +261,7 @@ enum {
 	MX7ULP_PAD_PTB0__TPM2_CH1                                    = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x2, 0),
 	MX7ULP_PAD_PTB0__CLKOUT0                                     = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB0__CMP1_OUT                                    = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTB0__EWM_OUT_b                                   = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB0__EWM_OUT_B                                   = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB1__ADC0_CH0B                                   = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB1__PTB1                                        = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB1__FXIO0_D17                                   = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
@@ -272,7 +272,7 @@ enum {
 	MX7ULP_PAD_PTB1__RTC_CLKOUT                                  = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB1__EWM_IN                                      = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xc, 0xD228, 0x2, 0),
 	MX7ULP_PAD_PTB1__LLWU0_P8                                    = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTB2__ADC0_CH4A_5A_6A                             = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB2__ADC0_CH6A                                   = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB2__PTB2                                        = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB2__FXIO0_D18                                   = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB2__LPSPI0_SCK                                  = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x3, 0),
@@ -280,7 +280,7 @@ enum {
 	MX7ULP_PAD_PTB2__TPM3_CH0                                    = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x2, 0),
 	MX7ULP_PAD_PTB2__I2S1_TX_FS                                  = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D8, 0x2, 0),
 	MX7ULP_PAD_PTB2__TRACE_CLKOUT                                = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTB3__ADC0_CH4B_5B_6B                             = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB3__ADC0_CH6B                                   = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB3__PTB3                                        = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB3__FXIO0_D19                                   = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB3__LPSPI0_PCS0                                 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x3, 0),
@@ -299,6 +299,7 @@ enum {
 	MX7ULP_PAD_PTB4__I2S1_TXD1                                   = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB4__QSPIA_DATA7                                 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB4__TRACE_D1                                    = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB4__SEC_VIO_B                                   = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB5__PTB5                                        = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB5__FXIO0_D21                                   = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB5__LPSPI0_PCS2                                 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x3, 0),
@@ -308,6 +309,7 @@ enum {
 	MX7ULP_PAD_PTB5__I2S1_TXD2                                   = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB5__QSPIA_DATA6                                 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB5__TRACE_D2                                    = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB5__RTC_CLKOUT                                  = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB6__ADC1_CH1A                                   = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB6__PTB6                                        = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB6__FXIO0_D22                                   = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
@@ -369,6 +371,7 @@ enum {
 	MX7ULP_PAD_PTB12__PTB12                                      = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB12__FXIO0_D28                                  = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB12__LPSPI1_PCS2                                = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x3, 0),
+	MX7ULP_PAD_PTB12__LPUART2_TX                                 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x4, 0),
 	MX7ULP_PAD_PTB12__LPI2C3_SCL                                 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x3, 0),
 	MX7ULP_PAD_PTB12__TPM1_CH0                                   = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x3, 0),
 	MX7ULP_PAD_PTB12__I2S1_RXD2                                  = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x7, 0xD1EC, 0x2, 0),
@@ -377,6 +380,7 @@ enum {
 	MX7ULP_PAD_PTB13__PTB13                                      = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB13__FXIO0_D29                                  = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB13__LPSPI1_PCS3                                = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x3, 0),
+	MX7ULP_PAD_PTB13__LPUART2_RX                                 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x4, 0),
 	MX7ULP_PAD_PTB13__LPI2C3_SDA                                 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x3, 0),
 	MX7ULP_PAD_PTB13__TPM1_CH1                                   = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x3, 0),
 	MX7ULP_PAD_PTB13__I2S1_RXD3                                  = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x7, 0xD1F0, 0x2, 0),
@@ -388,7 +392,8 @@ enum {
 	MX7ULP_PAD_PTB14__LPI2C2_HREQ                                = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x3, 0),
 	MX7ULP_PAD_PTB14__TPM2_CLKIN                                 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x3, 0),
 	MX7ULP_PAD_PTB14__QSPIA_SS1_B                                = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTB14__QSPIA_SCLK_b                               = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB14__QSPIA_SCLK_B                               = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB14__RTC_CLKOUT                                 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB14__LLWU0_P13                                  = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB15__ADC1_CH2B                                  = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB15__PTB15                                      = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
@@ -396,70 +401,64 @@ enum {
 	MX7ULP_PAD_PTB15__LPI2C3_HREQ                                = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x3, 0),
 	MX7ULP_PAD_PTB15__TPM2_CH0                                   = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x3, 0),
 	MX7ULP_PAD_PTB15__QSPIA_SCLK                                 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTB16__ADC0_CH4A_5A_6A                            = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB16__ADC0_CH4A                                  = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB16__PTB16                                      = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB16__TPM2_CH1                                   = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x3, 0),
 	MX7ULP_PAD_PTB16__QSPIA_DATA3                                = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB16__LLWU0_P14                                  = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTB17__ADC0_CH4B_5B_6B                            = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB17__ADC0_CH4B                                  = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB17__PTB17                                      = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB17__TPM3_CLKIN                                 = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x2, 0),
 	MX7ULP_PAD_PTB17__QSPIA_DATA2                                = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTB18__ADC0_CH4A_5A_6A                            = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB18__ADC0_CH5A                                  = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB18__PTB18                                      = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB18__TPM3_CH0                                   = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x3, 0),
 	MX7ULP_PAD_PTB18__QSPIA_DATA1                                = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTB19__ADC0_CH4B_5B_6B                            = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB19__ADC0_CH5B                                  = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB19__PTB19                                      = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTB19__TPM3_CH1                                   = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x3, 0),
 	MX7ULP_PAD_PTB19__QSPIA_DATA0                                = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTB19__USB0_ID                                    = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTB19__USB0_ID                                    = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xa, 0xD338, 0x0, 0),
 	MX7ULP_PAD_PTB19__LLWU0_P15                                  = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC0__PTC0                                        = IOMUX_PAD(0x0000, 0x0000, 0x1, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC0__LPUART4_CTS_b                               = IOMUX_PAD(0x0000, 0x0000, 0x4, 0x0244, 0x1, 0),
+	MX7ULP_PAD_PTC0__LPUART4_CTS_B                               = IOMUX_PAD(0x0000, 0x0000, 0x4, 0x0244, 0x1, 0),
 	MX7ULP_PAD_PTC0__LPI2C4_SCL                                  = IOMUX_PAD(0x0000, 0x0000, 0x5, 0x0278, 0x1, 0),
 	MX7ULP_PAD_PTC0__TPM4_CLKIN                                  = IOMUX_PAD(0x0000, 0x0000, 0x6, 0x0298, 0x1, 0),
 	MX7ULP_PAD_PTC0__FB_AD0                                      = IOMUX_PAD(0x0000, 0x0000, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC0__TRACE_D15                                   = IOMUX_PAD(0x0000, 0x0000, 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC0__DEBUG_MUX0                                  = IOMUX_PAD(0x0000, 0x0000, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC1__PTC1                                        = IOMUX_PAD(0x0004, 0x0004, 0x1, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC1__LPUART4_RTS_b                               = IOMUX_PAD(0x0004, 0x0004, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC1__LPUART4_RTS_B                               = IOMUX_PAD(0x0004, 0x0004, 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC1__LPI2C4_SDA                                  = IOMUX_PAD(0x0004, 0x0004, 0x5, 0x027C, 0x1, 0),
 	MX7ULP_PAD_PTC1__TPM4_CH0                                    = IOMUX_PAD(0x0004, 0x0004, 0x6, 0x0280, 0x1, 0),
 	MX7ULP_PAD_PTC1__FB_AD1                                      = IOMUX_PAD(0x0004, 0x0004, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC1__TRACE_D14                                   = IOMUX_PAD(0x0004, 0x0004, 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC1__DEBUG_MUX1                                  = IOMUX_PAD(0x0004, 0x0004, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC2__PTC2                                        = IOMUX_PAD(0x0008, 0x0008, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC2__LPUART4_TX                                  = IOMUX_PAD(0x0008, 0x0008, 0x4, 0x024C, 0x1, 0),
 	MX7ULP_PAD_PTC2__LPI2C4_HREQ                                 = IOMUX_PAD(0x0008, 0x0008, 0x5, 0x0274, 0x1, 0),
 	MX7ULP_PAD_PTC2__TPM4_CH1                                    = IOMUX_PAD(0x0008, 0x0008, 0x6, 0x0284, 0x1, 0),
 	MX7ULP_PAD_PTC2__FB_AD2                                      = IOMUX_PAD(0x0008, 0x0008, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC2__TRACE_D13                                   = IOMUX_PAD(0x0008, 0x0008, 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC2__DEBUG_MUX2                                  = IOMUX_PAD(0x0008, 0x0008, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC3__PTC3                                        = IOMUX_PAD(0x000C, 0x000C, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC3__LPUART4_RX                                  = IOMUX_PAD(0x000C, 0x000C, 0x4, 0x0248, 0x1, 0),
 	MX7ULP_PAD_PTC3__TPM4_CH2                                    = IOMUX_PAD(0x000C, 0x000C, 0x6, 0x0288, 0x1, 0),
 	MX7ULP_PAD_PTC3__FB_AD3                                      = IOMUX_PAD(0x000C, 0x000C, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC3__TRACE_D12                                   = IOMUX_PAD(0x000C, 0x000C, 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC3__DEBUG_MUX3                                  = IOMUX_PAD(0x000C, 0x000C, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC4__PTC4                                        = IOMUX_PAD(0x0010, 0x0010, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC4__FXIO1_D0                                    = IOMUX_PAD(0x0010, 0x0010, 0x2, 0x0204, 0x1, 0),
 	MX7ULP_PAD_PTC4__LPSPI2_PCS1                                 = IOMUX_PAD(0x0010, 0x0010, 0x3, 0x02A0, 0x1, 0),
-	MX7ULP_PAD_PTC4__LPUART5_CTS_b                               = IOMUX_PAD(0x0010, 0x0010, 0x4, 0x0250, 0x1, 0),
+	MX7ULP_PAD_PTC4__LPUART5_CTS_B                               = IOMUX_PAD(0x0010, 0x0010, 0x4, 0x0250, 0x1, 0),
 	MX7ULP_PAD_PTC4__LPI2C5_SCL                                  = IOMUX_PAD(0x0010, 0x0010, 0x5, 0x02BC, 0x1, 0),
 	MX7ULP_PAD_PTC4__TPM4_CH3                                    = IOMUX_PAD(0x0010, 0x0010, 0x6, 0x028C, 0x1, 0),
 	MX7ULP_PAD_PTC4__FB_AD4                                      = IOMUX_PAD(0x0010, 0x0010, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC4__TRACE_D11                                   = IOMUX_PAD(0x0010, 0x0010, 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC4__DEBUG_MUX4                                  = IOMUX_PAD(0x0010, 0x0010, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC5__PTC5                                        = IOMUX_PAD(0x0014, 0x0014, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC5__FXIO1_D1                                    = IOMUX_PAD(0x0014, 0x0014, 0x2, 0x0208, 0x1, 0),
 	MX7ULP_PAD_PTC5__LPSPI2_PCS2                                 = IOMUX_PAD(0x0014, 0x0014, 0x3, 0x02A4, 0x1, 0),
-	MX7ULP_PAD_PTC5__LPUART5_RTS_b                               = IOMUX_PAD(0x0014, 0x0014, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC5__LPUART5_RTS_B                               = IOMUX_PAD(0x0014, 0x0014, 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC5__LPI2C5_SDA                                  = IOMUX_PAD(0x0014, 0x0014, 0x5, 0x02C0, 0x1, 0),
 	MX7ULP_PAD_PTC5__TPM4_CH4                                    = IOMUX_PAD(0x0014, 0x0014, 0x6, 0x0290, 0x1, 0),
 	MX7ULP_PAD_PTC5__FB_AD5                                      = IOMUX_PAD(0x0014, 0x0014, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC5__TRACE_D10                                   = IOMUX_PAD(0x0014, 0x0014, 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC5__DEBUG_MUX5                                  = IOMUX_PAD(0x0014, 0x0014, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC6__PTC6                                        = IOMUX_PAD(0x0018, 0x0018, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC6__FXIO1_D2                                    = IOMUX_PAD(0x0018, 0x0018, 0x2, 0x020C, 0x1, 0),
 	MX7ULP_PAD_PTC6__LPSPI2_PCS3                                 = IOMUX_PAD(0x0018, 0x0018, 0x3, 0x02A8, 0x1, 0),
@@ -468,32 +467,28 @@ enum {
 	MX7ULP_PAD_PTC6__TPM4_CH5                                    = IOMUX_PAD(0x0018, 0x0018, 0x6, 0x0294, 0x1, 0),
 	MX7ULP_PAD_PTC6__FB_AD6                                      = IOMUX_PAD(0x0018, 0x0018, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC6__TRACE_D9                                    = IOMUX_PAD(0x0018, 0x0018, 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC6__DEBUG_MUX6                                  = IOMUX_PAD(0x0018, 0x0018, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC7__PTC7                                        = IOMUX_PAD(0x001C, 0x001C, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC7__FXIO1_D3                                    = IOMUX_PAD(0x001C, 0x001C, 0x2, 0x0210, 0x1, 0),
 	MX7ULP_PAD_PTC7__LPUART5_RX                                  = IOMUX_PAD(0x001C, 0x001C, 0x4, 0x0254, 0x1, 0),
 	MX7ULP_PAD_PTC7__TPM5_CH1                                    = IOMUX_PAD(0x001C, 0x001C, 0x6, 0x02C8, 0x1, 0),
 	MX7ULP_PAD_PTC7__FB_AD7                                      = IOMUX_PAD(0x001C, 0x001C, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC7__TRACE_D8                                    = IOMUX_PAD(0x001C, 0x001C, 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC7__DEBUG_MUX7                                  = IOMUX_PAD(0x001C, 0x001C, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC8__PTC8                                        = IOMUX_PAD(0x0020, 0x0020, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC8__FXIO1_D4                                    = IOMUX_PAD(0x0020, 0x0020, 0x2, 0x0214, 0x1, 0),
 	MX7ULP_PAD_PTC8__LPSPI2_SIN                                  = IOMUX_PAD(0x0020, 0x0020, 0x3, 0x02B0, 0x1, 0),
-	MX7ULP_PAD_PTC8__LPUART6_CTS_b                               = IOMUX_PAD(0x0020, 0x0020, 0x4, 0x025C, 0x1, 0),
+	MX7ULP_PAD_PTC8__LPUART6_CTS_B                               = IOMUX_PAD(0x0020, 0x0020, 0x4, 0x025C, 0x1, 0),
 	MX7ULP_PAD_PTC8__LPI2C6_SCL                                  = IOMUX_PAD(0x0020, 0x0020, 0x5, 0x02FC, 0x1, 0),
 	MX7ULP_PAD_PTC8__TPM5_CLKIN                                  = IOMUX_PAD(0x0020, 0x0020, 0x6, 0x02CC, 0x1, 0),
 	MX7ULP_PAD_PTC8__FB_AD8                                      = IOMUX_PAD(0x0020, 0x0020, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC8__TRACE_D7                                    = IOMUX_PAD(0x0020, 0x0020, 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC8__DEBUG_MUX8                                  = IOMUX_PAD(0x0020, 0x0020, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC9__PTC9                                        = IOMUX_PAD(0x0024, 0x0024, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC9__FXIO1_D5                                    = IOMUX_PAD(0x0024, 0x0024, 0x2, 0x0218, 0x1, 0),
 	MX7ULP_PAD_PTC9__LPSPI2_SOUT                                 = IOMUX_PAD(0x0024, 0x0024, 0x3, 0x02B4, 0x1, 0),
-	MX7ULP_PAD_PTC9__LPUART6_RTS_b                               = IOMUX_PAD(0x0024, 0x0024, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC9__LPUART6_RTS_B                               = IOMUX_PAD(0x0024, 0x0024, 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC9__LPI2C6_SDA                                  = IOMUX_PAD(0x0024, 0x0024, 0x5, 0x0300, 0x1, 0),
 	MX7ULP_PAD_PTC9__TPM5_CH0                                    = IOMUX_PAD(0x0024, 0x0024, 0x6, 0x02C4, 0x1, 0),
 	MX7ULP_PAD_PTC9__FB_AD9                                      = IOMUX_PAD(0x0024, 0x0024, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC9__TRACE_D6                                    = IOMUX_PAD(0x0024, 0x0024, 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC9__DEBUG_MUX9                                  = IOMUX_PAD(0x0024, 0x0024, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC10__PTC10                                      = IOMUX_PAD(0x0028, 0x0028, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC10__FXIO1_D6                                   = IOMUX_PAD(0x0028, 0x0028, 0x2, 0x021C, 0x1, 0),
 	MX7ULP_PAD_PTC10__LPSPI2_SCK                                 = IOMUX_PAD(0x0028, 0x0028, 0x3, 0x02AC, 0x1, 0),
@@ -502,7 +497,6 @@ enum {
 	MX7ULP_PAD_PTC10__TPM7_CH3                                   = IOMUX_PAD(0x0028, 0x0028, 0x6, 0x02E8, 0x1, 0),
 	MX7ULP_PAD_PTC10__FB_AD10                                    = IOMUX_PAD(0x0028, 0x0028, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC10__TRACE_D5                                   = IOMUX_PAD(0x0028, 0x0028, 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC10__DEBUG_MUX10                                = IOMUX_PAD(0x0028, 0x0028, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC11__PTC11                                      = IOMUX_PAD(0x002C, 0x002C, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC11__FXIO1_D7                                   = IOMUX_PAD(0x002C, 0x002C, 0x2, 0x0220, 0x1, 0),
 	MX7ULP_PAD_PTC11__LPSPI2_PCS0                                = IOMUX_PAD(0x002C, 0x002C, 0x3, 0x029C, 0x1, 0),
@@ -510,25 +504,23 @@ enum {
 	MX7ULP_PAD_PTC11__TPM7_CH4                                   = IOMUX_PAD(0x002C, 0x002C, 0x6, 0x02EC, 0x1, 0),
 	MX7ULP_PAD_PTC11__FB_AD11                                    = IOMUX_PAD(0x002C, 0x002C, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC11__TRACE_D4                                   = IOMUX_PAD(0x002C, 0x002C, 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC11__DEBUG_MUX11                                = IOMUX_PAD(0x002C, 0x002C, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC12__PTC12                                      = IOMUX_PAD(0x0030, 0x0030, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC12__FXIO1_D8                                   = IOMUX_PAD(0x0030, 0x0030, 0x2, 0x0224, 0x1, 0),
 	MX7ULP_PAD_PTC12__LPSPI3_PCS1                                = IOMUX_PAD(0x0030, 0x0030, 0x3, 0x0314, 0x1, 0),
-	MX7ULP_PAD_PTC12__LPUART7_CTS_b                              = IOMUX_PAD(0x0030, 0x0030, 0x4, 0x0268, 0x1, 0),
+	MX7ULP_PAD_PTC12__LPUART7_CTS_B                              = IOMUX_PAD(0x0030, 0x0030, 0x4, 0x0268, 0x1, 0),
 	MX7ULP_PAD_PTC12__LPI2C7_SCL                                 = IOMUX_PAD(0x0030, 0x0030, 0x5, 0x0308, 0x1, 0),
 	MX7ULP_PAD_PTC12__TPM7_CH5                                   = IOMUX_PAD(0x0030, 0x0030, 0x6, 0x02F0, 0x1, 0),
 	MX7ULP_PAD_PTC12__FB_AD12                                    = IOMUX_PAD(0x0030, 0x0030, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC12__TRACE_D3                                   = IOMUX_PAD(0x0030, 0x0030, 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC12__DEBUG_MUX12                                = IOMUX_PAD(0x0030, 0x0030, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC13__PTC13                                      = IOMUX_PAD(0x0034, 0x0034, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC13__FXIO1_D9                                   = IOMUX_PAD(0x0034, 0x0034, 0x2, 0x0228, 0x1, 0),
 	MX7ULP_PAD_PTC13__LPSPI3_PCS2                                = IOMUX_PAD(0x0034, 0x0034, 0x3, 0x0318, 0x1, 0),
-	MX7ULP_PAD_PTC13__LPUART7_RTS_b                              = IOMUX_PAD(0x0034, 0x0034, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC13__LPUART7_RTS_B                              = IOMUX_PAD(0x0034, 0x0034, 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC13__LPI2C7_SDA                                 = IOMUX_PAD(0x0034, 0x0034, 0x5, 0x030C, 0x1, 0),
 	MX7ULP_PAD_PTC13__TPM7_CLKIN                                 = IOMUX_PAD(0x0034, 0x0034, 0x6, 0x02F4, 0x1, 0),
 	MX7ULP_PAD_PTC13__FB_AD13                                    = IOMUX_PAD(0x0034, 0x0034, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC13__TRACE_D2                                   = IOMUX_PAD(0x0034, 0x0034, 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC13__DEBUG_MUX13                                = IOMUX_PAD(0x0034, 0x0034, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC13__USB0_ID                                    = IOMUX_PAD(0x0034, 0x0034, 0xb, 0x0338, 0x1, 0),
 	MX7ULP_PAD_PTC14__PTC14                                      = IOMUX_PAD(0x0038, 0x0038, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC14__FXIO1_D10                                  = IOMUX_PAD(0x0038, 0x0038, 0x2, 0x022C, 0x1, 0),
 	MX7ULP_PAD_PTC14__LPSPI3_PCS3                                = IOMUX_PAD(0x0038, 0x0038, 0x3, 0x031C, 0x1, 0),
@@ -537,122 +529,107 @@ enum {
 	MX7ULP_PAD_PTC14__TPM7_CH0                                   = IOMUX_PAD(0x0038, 0x0038, 0x6, 0x02DC, 0x1, 0),
 	MX7ULP_PAD_PTC14__FB_AD14                                    = IOMUX_PAD(0x0038, 0x0038, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC14__TRACE_D1                                   = IOMUX_PAD(0x0038, 0x0038, 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC14__DEBUG_MUX14                                = IOMUX_PAD(0x0038, 0x0038, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC15__PTC15                                      = IOMUX_PAD(0x003C, 0x003C, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC15__FXIO1_D11                                  = IOMUX_PAD(0x003C, 0x003C, 0x2, 0x0230, 0x1, 0),
 	MX7ULP_PAD_PTC15__LPUART7_RX                                 = IOMUX_PAD(0x003C, 0x003C, 0x4, 0x026C, 0x1, 0),
 	MX7ULP_PAD_PTC15__TPM7_CH1                                   = IOMUX_PAD(0x003C, 0x003C, 0x6, 0x02E0, 0x1, 0),
 	MX7ULP_PAD_PTC15__FB_AD15                                    = IOMUX_PAD(0x003C, 0x003C, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC15__TRACE_D0                                   = IOMUX_PAD(0x003C, 0x003C, 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC15__DEBUG_MUX15                                = IOMUX_PAD(0x003C, 0x003C, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC16__PTC16                                      = IOMUX_PAD(0x0040, 0x0040, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC16__FXIO1_D12                                  = IOMUX_PAD(0x0040, 0x0040, 0x2, 0x0234, 0x1, 0),
 	MX7ULP_PAD_PTC16__LPSPI3_SIN                                 = IOMUX_PAD(0x0040, 0x0040, 0x3, 0x0324, 0x1, 0),
 	MX7ULP_PAD_PTC16__TPM7_CH2                                   = IOMUX_PAD(0x0040, 0x0040, 0x6, 0x02E4, 0x1, 0),
-	MX7ULP_PAD_PTC16__FB_ALE_FB_CS1_b_FB_TS_b                    = IOMUX_PAD(0x0040, 0x0040, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B                    = IOMUX_PAD(0x0040, 0x0040, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC16__TRACE_CLKOUT                               = IOMUX_PAD(0x0040, 0x0040, 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC16__USB1_ULPI_OC2                              = IOMUX_PAD(0x0040, 0x0040, 0xb, 0x0334, 0x1, 0),
+	MX7ULP_PAD_PTC16__USB1_OC2                                   = IOMUX_PAD(0x0040, 0x0040, 0xb, 0x0334, 0x1, 0),
 	MX7ULP_PAD_PTC17__PTC17                                      = IOMUX_PAD(0x0044, 0x0044, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC17__FXIO1_D13                                  = IOMUX_PAD(0x0044, 0x0044, 0x2, 0x0238, 0x1, 0),
 	MX7ULP_PAD_PTC17__LPSPI3_SOUT                                = IOMUX_PAD(0x0044, 0x0044, 0x3, 0x0328, 0x1, 0),
 	MX7ULP_PAD_PTC17__TPM6_CLKIN                                 = IOMUX_PAD(0x0044, 0x0044, 0x6, 0x02D8, 0x1, 0),
-	MX7ULP_PAD_PTC17__FB_CS0_b                                   = IOMUX_PAD(0x0044, 0x0044, 0x9, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC17__DEBUG_MUX16                                = IOMUX_PAD(0x0044, 0x0044, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC17__FB_CS0_B                                   = IOMUX_PAD(0x0044, 0x0044, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC18__PTC18                                      = IOMUX_PAD(0x0048, 0x0048, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC18__FXIO1_D14                                  = IOMUX_PAD(0x0048, 0x0048, 0x2, 0x023C, 0x1, 0),
 	MX7ULP_PAD_PTC18__LPSPI3_SCK                                 = IOMUX_PAD(0x0048, 0x0048, 0x3, 0x0320, 0x1, 0),
 	MX7ULP_PAD_PTC18__TPM6_CH0                                   = IOMUX_PAD(0x0048, 0x0048, 0x6, 0x02D0, 0x1, 0),
-	MX7ULP_PAD_PTC18__FB_OE_b                                    = IOMUX_PAD(0x0048, 0x0048, 0x9, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC18__DEBUG_MUX17                                = IOMUX_PAD(0x0048, 0x0048, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC18__FB_OE_B                                    = IOMUX_PAD(0x0048, 0x0048, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC18__USB0_ID                                    = IOMUX_PAD(0x0048, 0x0048, 0xb, 0x0338, 0x2, 0),
+	MX7ULP_PAD_PTC18__VIU_DE                                     = IOMUX_PAD(0x0048, 0x0048, 0xc, 0x033c, 0x1, 0),
 	MX7ULP_PAD_PTC19__PTC19                                      = IOMUX_PAD(0x004C, 0x004C, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTC19__FXIO1_D15                                  = IOMUX_PAD(0x004C, 0x004C, 0x2, 0x0240, 0x1, 0),
 	MX7ULP_PAD_PTC19__LPSPI3_PCS0                                = IOMUX_PAD(0x004C, 0x004C, 0x3, 0x0310, 0x1, 0),
 	MX7ULP_PAD_PTC19__TPM6_CH1                                   = IOMUX_PAD(0x004C, 0x004C, 0x6, 0x02D4, 0x1, 0),
 	MX7ULP_PAD_PTC19__FB_A16                                     = IOMUX_PAD(0x004C, 0x004C, 0x9, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTC19__USB1_ULPI_PWR2                             = IOMUX_PAD(0x004C, 0x004C, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC19__USB0_ID                                    = IOMUX_PAD(0x004C, 0x004C, 0xa, 0x0338, 0x3, 0),
+	MX7ULP_PAD_PTC19__USB1_PWR2                                  = IOMUX_PAD(0x004C, 0x004C, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTC19__VIU_DE                                     = IOMUX_PAD(0x004C, 0x004C, 0xc, 0x033c, 0x3, 0),
 	MX7ULP_PAD_PTD0__PTD0                                        = IOMUX_PAD(0x0080, 0x0080, 0x1, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTD0__SDHC0_RESET_b                               = IOMUX_PAD(0x0080, 0x0080, 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTD0__DEBUG_MUX18                                 = IOMUX_PAD(0x0080, 0x0080, 0xe, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTD0__SDHC0_RESET_B                               = IOMUX_PAD(0x0080, 0x0080, 0x8, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD1__PTD1                                        = IOMUX_PAD(0x0084, 0x0084, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD1__SDHC0_CMD                                   = IOMUX_PAD(0x0084, 0x0084, 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTD1__DEBUG_MUX19                                 = IOMUX_PAD(0x0084, 0x0084, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD2__PTD2                                        = IOMUX_PAD(0x0088, 0x0088, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD2__SDHC0_CLK                                   = IOMUX_PAD(0x0088, 0x0088, 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTD2__DEBUG_MUX20                                 = IOMUX_PAD(0x0088, 0x0088, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD3__PTD3                                        = IOMUX_PAD(0x008C, 0x008C, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD3__SDHC0_D7                                    = IOMUX_PAD(0x008C, 0x008C, 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTD3__DEBUG_MUX21                                 = IOMUX_PAD(0x008C, 0x008C, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD4__PTD4                                        = IOMUX_PAD(0x0090, 0x0090, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD4__SDHC0_D6                                    = IOMUX_PAD(0x0090, 0x0090, 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTD4__DEBUG_MUX22                                 = IOMUX_PAD(0x0090, 0x0090, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD5__PTD5                                        = IOMUX_PAD(0x0094, 0x0094, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD5__SDHC0_D5                                    = IOMUX_PAD(0x0094, 0x0094, 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTD5__DEBUG_MUX23                                 = IOMUX_PAD(0x0094, 0x0094, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD6__PTD6                                        = IOMUX_PAD(0x0098, 0x0098, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD6__SDHC0_D4                                    = IOMUX_PAD(0x0098, 0x0098, 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTD6__DEBUG_MUX24                                 = IOMUX_PAD(0x0098, 0x0098, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD7__PTD7                                        = IOMUX_PAD(0x009C, 0x009C, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD7__SDHC0_D3                                    = IOMUX_PAD(0x009C, 0x009C, 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTD7__DEBUG_MUX25                                 = IOMUX_PAD(0x009C, 0x009C, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD8__PTD8                                        = IOMUX_PAD(0x00A0, 0x00A0, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD8__TPM4_CLKIN                                  = IOMUX_PAD(0x00A0, 0x00A0, 0x6, 0x0298, 0x2, 0),
 	MX7ULP_PAD_PTD8__SDHC0_D2                                    = IOMUX_PAD(0x00A0, 0x00A0, 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTD8__DEBUG_MUX26                                 = IOMUX_PAD(0x00A0, 0x00A0, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD9__PTD9                                        = IOMUX_PAD(0x00A4, 0x00A4, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD9__TPM4_CH0                                    = IOMUX_PAD(0x00A4, 0x00A4, 0x6, 0x0280, 0x2, 0),
 	MX7ULP_PAD_PTD9__SDHC0_D1                                    = IOMUX_PAD(0x00A4, 0x00A4, 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTD9__DEBUG_MUX27                                 = IOMUX_PAD(0x00A4, 0x00A4, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD10__PTD10                                      = IOMUX_PAD(0x00A8, 0x00A8, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD10__TPM4_CH1                                   = IOMUX_PAD(0x00A8, 0x00A8, 0x6, 0x0284, 0x2, 0),
 	MX7ULP_PAD_PTD10__SDHC0_D0                                   = IOMUX_PAD(0x00A8, 0x00A8, 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTD10__DEBUG_MUX28                                = IOMUX_PAD(0x00A8, 0x00A8, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD11__PTD11                                      = IOMUX_PAD(0x00AC, 0x00AC, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTD11__TPM4_CH2                                   = IOMUX_PAD(0x00AC, 0x00AC, 0x6, 0x0288, 0x2, 0),
 	MX7ULP_PAD_PTD11__SDHC0_DQS                                  = IOMUX_PAD(0x00AC, 0x00AC, 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTD11__DEBUG_MUX29                                = IOMUX_PAD(0x00AC, 0x00AC, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE0__PTE0                                        = IOMUX_PAD(0x0100, 0x0100, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE0__FXIO1_D31                                   = IOMUX_PAD(0x0100, 0x0100, 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE0__LPSPI2_PCS1                                 = IOMUX_PAD(0x0100, 0x0100, 0x3, 0x02A0, 0x2, 0),
-	MX7ULP_PAD_PTE0__LPUART4_CTS_b                               = IOMUX_PAD(0x0100, 0x0100, 0x4, 0x0244, 0x2, 0),
+	MX7ULP_PAD_PTE0__LPUART4_CTS_B                               = IOMUX_PAD(0x0100, 0x0100, 0x4, 0x0244, 0x2, 0),
 	MX7ULP_PAD_PTE0__LPI2C4_SCL                                  = IOMUX_PAD(0x0100, 0x0100, 0x5, 0x0278, 0x2, 0),
 	MX7ULP_PAD_PTE0__SDHC1_D1                                    = IOMUX_PAD(0x0100, 0x0100, 0x8, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE0__FB_A25                                      = IOMUX_PAD(0x0100, 0x0100, 0x9, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTE0__DEBUG_MUX30                                 = IOMUX_PAD(0x0100, 0x0100, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE1__PTE1                                        = IOMUX_PAD(0x0104, 0x0104, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE1__FXIO1_D30                                   = IOMUX_PAD(0x0104, 0x0104, 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE1__LPSPI2_PCS2                                 = IOMUX_PAD(0x0104, 0x0104, 0x3, 0x02A4, 0x2, 0),
-	MX7ULP_PAD_PTE1__LPUART4_RTS_b                               = IOMUX_PAD(0x0104, 0x0104, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE1__LPUART4_RTS_B                               = IOMUX_PAD(0x0104, 0x0104, 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE1__LPI2C4_SDA                                  = IOMUX_PAD(0x0104, 0x0104, 0x5, 0x027C, 0x2, 0),
 	MX7ULP_PAD_PTE1__SDHC1_D0                                    = IOMUX_PAD(0x0104, 0x0104, 0x8, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE1__FB_A26                                      = IOMUX_PAD(0x0104, 0x0104, 0x9, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTE1__DEBUG_MUX31                                 = IOMUX_PAD(0x0104, 0x0104, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE2__PTE2                                        = IOMUX_PAD(0x0108, 0x0108, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE2__FXIO1_D29                                   = IOMUX_PAD(0x0108, 0x0108, 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE2__LPSPI2_PCS3                                 = IOMUX_PAD(0x0108, 0x0108, 0x3, 0x02A8, 0x2, 0),
 	MX7ULP_PAD_PTE2__LPUART4_TX                                  = IOMUX_PAD(0x0108, 0x0108, 0x4, 0x024C, 0x2, 0),
 	MX7ULP_PAD_PTE2__LPI2C4_HREQ                                 = IOMUX_PAD(0x0108, 0x0108, 0x5, 0x0274, 0x2, 0),
 	MX7ULP_PAD_PTE2__SDHC1_CLK                                   = IOMUX_PAD(0x0108, 0x0108, 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTE2__DEBUG_MUX32                                 = IOMUX_PAD(0x0108, 0x0108, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE3__PTE3                                        = IOMUX_PAD(0x010C, 0x010C, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE3__FXIO1_D28                                   = IOMUX_PAD(0x010C, 0x010C, 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE3__LPUART4_RX                                  = IOMUX_PAD(0x010C, 0x010C, 0x4, 0x0248, 0x2, 0),
 	MX7ULP_PAD_PTE3__TPM5_CH1                                    = IOMUX_PAD(0x010C, 0x010C, 0x6, 0x02C8, 0x2, 0),
 	MX7ULP_PAD_PTE3__SDHC1_CMD                                   = IOMUX_PAD(0x010C, 0x010C, 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTE3__DEBUG_MUX33                                 = IOMUX_PAD(0x010C, 0x010C, 0xe, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE4__PTE4                                        = IOMUX_PAD(0x0110, 0x0110, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE4__FXIO1_D27                                   = IOMUX_PAD(0x0110, 0x0110, 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE4__LPSPI2_SIN                                  = IOMUX_PAD(0x0110, 0x0110, 0x3, 0x02B0, 0x2, 0),
-	MX7ULP_PAD_PTE4__LPUART5_CTS_b                               = IOMUX_PAD(0x0110, 0x0110, 0x4, 0x0250, 0x2, 0),
+	MX7ULP_PAD_PTE4__LPUART5_CTS_B                               = IOMUX_PAD(0x0110, 0x0110, 0x4, 0x0250, 0x2, 0),
 	MX7ULP_PAD_PTE4__LPI2C5_SCL                                  = IOMUX_PAD(0x0110, 0x0110, 0x5, 0x02BC, 0x2, 0),
 	MX7ULP_PAD_PTE4__TPM5_CLKIN                                  = IOMUX_PAD(0x0110, 0x0110, 0x6, 0x02CC, 0x2, 0),
 	MX7ULP_PAD_PTE4__SDHC1_D3                                    = IOMUX_PAD(0x0110, 0x0110, 0x8, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE5__PTE5                                        = IOMUX_PAD(0x0114, 0x0114, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE5__FXIO1_D26                                   = IOMUX_PAD(0x0114, 0x0114, 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE5__LPSPI2_SOUT                                 = IOMUX_PAD(0x0114, 0x0114, 0x3, 0x02B4, 0x2, 0),
-	MX7ULP_PAD_PTE5__LPUART5_RTS_b                               = IOMUX_PAD(0x0114, 0x0114, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE5__LPUART5_RTS_B                               = IOMUX_PAD(0x0114, 0x0114, 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE5__LPI2C5_SDA                                  = IOMUX_PAD(0x0114, 0x0114, 0x5, 0x02C0, 0x2, 0),
 	MX7ULP_PAD_PTE5__TPM5_CH0                                    = IOMUX_PAD(0x0114, 0x0114, 0x6, 0x02C4, 0x2, 0),
 	MX7ULP_PAD_PTE5__SDHC1_D2                                    = IOMUX_PAD(0x0114, 0x0114, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE5__VIU_DE                                      = IOMUX_PAD(0x0114, 0x0114, 0xc, 0x033c, 0x2, 0),
 	MX7ULP_PAD_PTE6__PTE6                                        = IOMUX_PAD(0x0118, 0x0118, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE6__FXIO1_D25                                   = IOMUX_PAD(0x0118, 0x0118, 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE6__LPSPI2_SCK                                  = IOMUX_PAD(0x0118, 0x0118, 0x3, 0x02AC, 0x2, 0),
@@ -677,23 +654,23 @@ enum {
 	MX7ULP_PAD_PTE8__VIU_D16                                     = IOMUX_PAD(0x0120, 0x0120, 0xc, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE8__FXIO1_D23                                   = IOMUX_PAD(0x0120, 0x0120, 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE8__LPSPI3_PCS1                                 = IOMUX_PAD(0x0120, 0x0120, 0x3, 0x0314, 0x2, 0),
-	MX7ULP_PAD_PTE8__LPUART6_CTS_b                               = IOMUX_PAD(0x0120, 0x0120, 0x4, 0x025C, 0x2, 0),
+	MX7ULP_PAD_PTE8__LPUART6_CTS_B                               = IOMUX_PAD(0x0120, 0x0120, 0x4, 0x025C, 0x2, 0),
 	MX7ULP_PAD_PTE8__LPI2C6_SCL                                  = IOMUX_PAD(0x0120, 0x0120, 0x5, 0x02FC, 0x2, 0),
 	MX7ULP_PAD_PTE8__TPM7_CH5                                    = IOMUX_PAD(0x0120, 0x0120, 0x6, 0x02F0, 0x2, 0),
 	MX7ULP_PAD_PTE8__SDHC1_WP                                    = IOMUX_PAD(0x0120, 0x0120, 0x7, 0x0200, 0x1, 0),
 	MX7ULP_PAD_PTE8__SDHC1_D6                                    = IOMUX_PAD(0x0120, 0x0120, 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTE8__FB_CS3_b_FB_BE7_0_BLS31_24_b                = IOMUX_PAD(0x0120, 0x0120, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B                = IOMUX_PAD(0x0120, 0x0120, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE9__PTE9                                        = IOMUX_PAD(0x0124, 0x0124, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE9__TRACE_D5                                    = IOMUX_PAD(0x0124, 0x0124, 0xa, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE9__VIU_D17                                     = IOMUX_PAD(0x0124, 0x0124, 0xc, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE9__FXIO1_D22                                   = IOMUX_PAD(0x0124, 0x0124, 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE9__LPSPI3_PCS2                                 = IOMUX_PAD(0x0124, 0x0124, 0x3, 0x0318, 0x2, 0),
-	MX7ULP_PAD_PTE9__LPUART6_RTS_b                               = IOMUX_PAD(0x0124, 0x0124, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE9__LPUART6_RTS_B                               = IOMUX_PAD(0x0124, 0x0124, 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE9__LPI2C6_SDA                                  = IOMUX_PAD(0x0124, 0x0124, 0x5, 0x0300, 0x2, 0),
 	MX7ULP_PAD_PTE9__TPM7_CLKIN                                  = IOMUX_PAD(0x0124, 0x0124, 0x6, 0x02F4, 0x2, 0),
 	MX7ULP_PAD_PTE9__SDHC1_CD                                    = IOMUX_PAD(0x0124, 0x0124, 0x7, 0x032C, 0x1, 0),
 	MX7ULP_PAD_PTE9__SDHC1_D7                                    = IOMUX_PAD(0x0124, 0x0124, 0x8, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTE9__FB_TBST_b_FB_CS2_b_FB_BE15_8_BLS23_16_b     = IOMUX_PAD(0x0124, 0x0124, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B     = IOMUX_PAD(0x0124, 0x0124, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE10__PTE10                                      = IOMUX_PAD(0x0128, 0x0128, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE10__TRACE_D4                                   = IOMUX_PAD(0x0128, 0x0128, 0xa, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE10__VIU_D18                                    = IOMUX_PAD(0x0128, 0x0128, 0xc, 0x0000, 0x0, 0),
@@ -711,29 +688,29 @@ enum {
 	MX7ULP_PAD_PTE11__FXIO1_D20                                  = IOMUX_PAD(0x012C, 0x012C, 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE11__LPUART6_RX                                 = IOMUX_PAD(0x012C, 0x012C, 0x4, 0x0260, 0x2, 0),
 	MX7ULP_PAD_PTE11__TPM7_CH1                                   = IOMUX_PAD(0x012C, 0x012C, 0x6, 0x02E0, 0x2, 0),
-	MX7ULP_PAD_PTE11__SDHC1_RESET_b                              = IOMUX_PAD(0x012C, 0x012C, 0x8, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE11__SDHC1_RESET_B                              = IOMUX_PAD(0x012C, 0x012C, 0x8, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE11__FB_A20                                     = IOMUX_PAD(0x012C, 0x012C, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE12__PTE12                                      = IOMUX_PAD(0x0130, 0x0130, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE12__FXIO1_D19                                  = IOMUX_PAD(0x0130, 0x0130, 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE12__LPSPI3_SIN                                 = IOMUX_PAD(0x0130, 0x0130, 0x3, 0x0324, 0x2, 0),
-	MX7ULP_PAD_PTE12__LPUART7_CTS_b                              = IOMUX_PAD(0x0130, 0x0130, 0x4, 0x0268, 0x2, 0),
+	MX7ULP_PAD_PTE12__LPUART7_CTS_B                              = IOMUX_PAD(0x0130, 0x0130, 0x4, 0x0268, 0x2, 0),
 	MX7ULP_PAD_PTE12__LPI2C7_SCL                                 = IOMUX_PAD(0x0130, 0x0130, 0x5, 0x0308, 0x2, 0),
 	MX7ULP_PAD_PTE12__TPM7_CH2                                   = IOMUX_PAD(0x0130, 0x0130, 0x6, 0x02E4, 0x2, 0),
 	MX7ULP_PAD_PTE12__SDHC1_WP                                   = IOMUX_PAD(0x0130, 0x0130, 0x8, 0x0200, 0x2, 0),
 	MX7ULP_PAD_PTE12__FB_A21                                     = IOMUX_PAD(0x0130, 0x0130, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE12__TRACE_D2                                   = IOMUX_PAD(0x0130, 0x0130, 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTE12__USB1_ULPI_OC2                              = IOMUX_PAD(0x0130, 0x0130, 0xb, 0x0334, 0x2, 0),
+	MX7ULP_PAD_PTE12__USB1_OC2                                   = IOMUX_PAD(0x0130, 0x0130, 0xb, 0x0334, 0x2, 0),
 	MX7ULP_PAD_PTE12__VIU_D20                                    = IOMUX_PAD(0x0130, 0x0130, 0xc, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE13__PTE13                                      = IOMUX_PAD(0x0134, 0x0134, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE13__FXIO1_D18                                  = IOMUX_PAD(0x0134, 0x0134, 0x2, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE13__LPSPI3_SOUT                                = IOMUX_PAD(0x0134, 0x0134, 0x3, 0x0328, 0x2, 0),
-	MX7ULP_PAD_PTE13__LPUART7_RTS_b                              = IOMUX_PAD(0x0134, 0x0134, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE13__LPUART7_RTS_B                              = IOMUX_PAD(0x0134, 0x0134, 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE13__LPI2C7_SDA                                 = IOMUX_PAD(0x0134, 0x0134, 0x5, 0x030C, 0x2, 0),
 	MX7ULP_PAD_PTE13__TPM6_CLKIN                                 = IOMUX_PAD(0x0134, 0x0134, 0x6, 0x02D8, 0x2, 0),
 	MX7ULP_PAD_PTE13__SDHC1_CD                                   = IOMUX_PAD(0x0134, 0x0134, 0x8, 0x032C, 0x2, 0),
 	MX7ULP_PAD_PTE13__FB_A22                                     = IOMUX_PAD(0x0134, 0x0134, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE13__TRACE_D1                                   = IOMUX_PAD(0x0134, 0x0134, 0xa, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTE13__USB1_ULPI_PWR2                             = IOMUX_PAD(0x0134, 0x0134, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTE13__USB1_PWR2                                  = IOMUX_PAD(0x0134, 0x0134, 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE13__VIU_D21                                    = IOMUX_PAD(0x0134, 0x0134, 0xc, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE14__PTE14                                      = IOMUX_PAD(0x0138, 0x0138, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE14__FXIO1_D17                                  = IOMUX_PAD(0x0138, 0x0138, 0x2, 0x0000, 0x0, 0),
@@ -756,13 +733,13 @@ enum {
 	MX7ULP_PAD_PTE15__USB0_PWR                                   = IOMUX_PAD(0x013C, 0x013C, 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTE15__VIU_D23                                    = IOMUX_PAD(0x013C, 0x013C, 0xc, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF0__PTF0                                        = IOMUX_PAD(0x0180, 0x0180, 0x1, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTF0__LPUART4_CTS_b                               = IOMUX_PAD(0x0180, 0x0180, 0x4, 0x0244, 0x3, 0),
+	MX7ULP_PAD_PTF0__LPUART4_CTS_B                               = IOMUX_PAD(0x0180, 0x0180, 0x4, 0x0244, 0x3, 0),
 	MX7ULP_PAD_PTF0__LPI2C4_SCL                                  = IOMUX_PAD(0x0180, 0x0180, 0x5, 0x0278, 0x3, 0),
 	MX7ULP_PAD_PTF0__TPM4_CLKIN                                  = IOMUX_PAD(0x0180, 0x0180, 0x6, 0x0298, 0x3, 0),
-	MX7ULP_PAD_PTF0__FB_RW_b                                     = IOMUX_PAD(0x0180, 0x0180, 0x9, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTF0__VIU_DE                                      = IOMUX_PAD(0x0180, 0x0180, 0xc, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF0__FB_RW_B                                     = IOMUX_PAD(0x0180, 0x0180, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF0__VIU_DE                                      = IOMUX_PAD(0x0180, 0x0180, 0xc, 0x033C, 0x0, 0),
 	MX7ULP_PAD_PTF1__PTF1                                        = IOMUX_PAD(0x0184, 0x0184, 0x1, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTF1__LPUART4_RTS_b                               = IOMUX_PAD(0x0184, 0x0184, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF1__LPUART4_RTS_B                               = IOMUX_PAD(0x0184, 0x0184, 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF1__LPI2C4_SDA                                  = IOMUX_PAD(0x0184, 0x0184, 0x5, 0x027C, 0x3, 0),
 	MX7ULP_PAD_PTF1__TPM4_CH0                                    = IOMUX_PAD(0x0184, 0x0184, 0x6, 0x0280, 0x3, 0),
 	MX7ULP_PAD_PTF1__CLKOUT                                      = IOMUX_PAD(0x0184, 0x0184, 0x9, 0x0000, 0x0, 0),
@@ -771,7 +748,7 @@ enum {
 	MX7ULP_PAD_PTF2__LPUART4_TX                                  = IOMUX_PAD(0x0188, 0x0188, 0x4, 0x024C, 0x3, 0),
 	MX7ULP_PAD_PTF2__LPI2C4_HREQ                                 = IOMUX_PAD(0x0188, 0x0188, 0x5, 0x0274, 0x3, 0),
 	MX7ULP_PAD_PTF2__TPM4_CH1                                    = IOMUX_PAD(0x0188, 0x0188, 0x6, 0x0284, 0x3, 0),
-	MX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_b_FB_BE23_16_BLS15_8_b      = IOMUX_PAD(0x0188, 0x0188, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B      = IOMUX_PAD(0x0188, 0x0188, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF2__VIU_VSYNC                                   = IOMUX_PAD(0x0188, 0x0188, 0xc, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF3__PTF3                                        = IOMUX_PAD(0x018C, 0x018C, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF3__LPUART4_RX                                  = IOMUX_PAD(0x018C, 0x018C, 0x4, 0x0248, 0x3, 0),
@@ -781,7 +758,7 @@ enum {
 	MX7ULP_PAD_PTF4__PTF4                                        = IOMUX_PAD(0x0190, 0x0190, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF4__FXIO1_D0                                    = IOMUX_PAD(0x0190, 0x0190, 0x2, 0x0204, 0x2, 0),
 	MX7ULP_PAD_PTF4__LPSPI2_PCS1                                 = IOMUX_PAD(0x0190, 0x0190, 0x3, 0x02A0, 0x3, 0),
-	MX7ULP_PAD_PTF4__LPUART5_CTS_b                               = IOMUX_PAD(0x0190, 0x0190, 0x4, 0x0250, 0x3, 0),
+	MX7ULP_PAD_PTF4__LPUART5_CTS_B                               = IOMUX_PAD(0x0190, 0x0190, 0x4, 0x0250, 0x3, 0),
 	MX7ULP_PAD_PTF4__LPI2C5_SCL                                  = IOMUX_PAD(0x0190, 0x0190, 0x5, 0x02BC, 0x3, 0),
 	MX7ULP_PAD_PTF4__TPM4_CH3                                    = IOMUX_PAD(0x0190, 0x0190, 0x6, 0x028C, 0x2, 0),
 	MX7ULP_PAD_PTF4__FB_AD17                                     = IOMUX_PAD(0x0190, 0x0190, 0x9, 0x0000, 0x0, 0),
@@ -789,7 +766,7 @@ enum {
 	MX7ULP_PAD_PTF5__PTF5                                        = IOMUX_PAD(0x0194, 0x0194, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF5__FXIO1_D1                                    = IOMUX_PAD(0x0194, 0x0194, 0x2, 0x0208, 0x2, 0),
 	MX7ULP_PAD_PTF5__LPSPI2_PCS2                                 = IOMUX_PAD(0x0194, 0x0194, 0x3, 0x02A4, 0x3, 0),
-	MX7ULP_PAD_PTF5__LPUART5_RTS_b                               = IOMUX_PAD(0x0194, 0x0194, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF5__LPUART5_RTS_B                               = IOMUX_PAD(0x0194, 0x0194, 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF5__LPI2C5_SDA                                  = IOMUX_PAD(0x0194, 0x0194, 0x5, 0x02C0, 0x3, 0),
 	MX7ULP_PAD_PTF5__TPM4_CH4                                    = IOMUX_PAD(0x0194, 0x0194, 0x6, 0x0290, 0x2, 0),
 	MX7ULP_PAD_PTF5__FB_AD18                                     = IOMUX_PAD(0x0194, 0x0194, 0x9, 0x0000, 0x0, 0),
@@ -811,20 +788,20 @@ enum {
 	MX7ULP_PAD_PTF8__PTF8                                        = IOMUX_PAD(0x01A0, 0x01A0, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF8__FXIO1_D4                                    = IOMUX_PAD(0x01A0, 0x01A0, 0x2, 0x0214, 0x2, 0),
 	MX7ULP_PAD_PTF8__LPSPI2_SIN                                  = IOMUX_PAD(0x01A0, 0x01A0, 0x3, 0x02B0, 0x3, 0),
-	MX7ULP_PAD_PTF8__LPUART6_CTS_b                               = IOMUX_PAD(0x01A0, 0x01A0, 0x4, 0x025C, 0x3, 0),
+	MX7ULP_PAD_PTF8__LPUART6_CTS_B                               = IOMUX_PAD(0x01A0, 0x01A0, 0x4, 0x025C, 0x3, 0),
 	MX7ULP_PAD_PTF8__LPI2C6_SCL                                  = IOMUX_PAD(0x01A0, 0x01A0, 0x5, 0x02FC, 0x3, 0),
 	MX7ULP_PAD_PTF8__TPM5_CLKIN                                  = IOMUX_PAD(0x01A0, 0x01A0, 0x6, 0x02CC, 0x3, 0),
 	MX7ULP_PAD_PTF8__FB_AD21                                     = IOMUX_PAD(0x01A0, 0x01A0, 0x9, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTF8__USB1_ULPI_CLK                               = IOMUX_PAD(0x01A0, 0x01A0, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF8__USB1_CLK                                    = IOMUX_PAD(0x01A0, 0x01A0, 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF8__VIU_D4                                      = IOMUX_PAD(0x01A0, 0x01A0, 0xc, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF9__PTF9                                        = IOMUX_PAD(0x01A4, 0x01A4, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF9__FXIO1_D5                                    = IOMUX_PAD(0x01A4, 0x01A4, 0x2, 0x0218, 0x2, 0),
 	MX7ULP_PAD_PTF9__LPSPI2_SOUT                                 = IOMUX_PAD(0x01A4, 0x01A4, 0x3, 0x02B4, 0x3, 0),
-	MX7ULP_PAD_PTF9__LPUART6_RTS_b                               = IOMUX_PAD(0x01A4, 0x01A4, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF9__LPUART6_RTS_B                               = IOMUX_PAD(0x01A4, 0x01A4, 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF9__LPI2C6_SDA                                  = IOMUX_PAD(0x01A4, 0x01A4, 0x5, 0x0300, 0x3, 0),
 	MX7ULP_PAD_PTF9__TPM5_CH0                                    = IOMUX_PAD(0x01A4, 0x01A4, 0x6, 0x02C4, 0x3, 0),
 	MX7ULP_PAD_PTF9__FB_AD22                                     = IOMUX_PAD(0x01A4, 0x01A4, 0x9, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTF9__USB1_ULPI_NXT                               = IOMUX_PAD(0x01A4, 0x01A4, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF9__USB1_NXT                                    = IOMUX_PAD(0x01A4, 0x01A4, 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF9__VIU_D5                                      = IOMUX_PAD(0x01A4, 0x01A4, 0xc, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF10__PTF10                                      = IOMUX_PAD(0x01A8, 0x01A8, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF10__FXIO1_D6                                   = IOMUX_PAD(0x01A8, 0x01A8, 0x2, 0x021C, 0x2, 0),
@@ -833,33 +810,33 @@ enum {
 	MX7ULP_PAD_PTF10__LPI2C6_HREQ                                = IOMUX_PAD(0x01A8, 0x01A8, 0x5, 0x02F8, 0x3, 0),
 	MX7ULP_PAD_PTF10__TPM7_CH3                                   = IOMUX_PAD(0x01A8, 0x01A8, 0x6, 0x02E8, 0x3, 0),
 	MX7ULP_PAD_PTF10__FB_AD23                                    = IOMUX_PAD(0x01A8, 0x01A8, 0x9, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTF10__USB1_ULPI_STP                              = IOMUX_PAD(0x01A8, 0x01A8, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF10__USB1_STP                                   = IOMUX_PAD(0x01A8, 0x01A8, 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF10__VIU_D6                                     = IOMUX_PAD(0x01A8, 0x01A8, 0xc, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF11__PTF11                                      = IOMUX_PAD(0x01AC, 0x01AC, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF11__FXIO1_D7                                   = IOMUX_PAD(0x01AC, 0x01AC, 0x2, 0x0220, 0x2, 0),
 	MX7ULP_PAD_PTF11__LPSPI2_PCS0                                = IOMUX_PAD(0x01AC, 0x01AC, 0x3, 0x029C, 0x3, 0),
 	MX7ULP_PAD_PTF11__LPUART6_RX                                 = IOMUX_PAD(0x01AC, 0x01AC, 0x4, 0x0260, 0x3, 0),
 	MX7ULP_PAD_PTF11__TPM7_CH4                                   = IOMUX_PAD(0x01AC, 0x01AC, 0x6, 0x02EC, 0x3, 0),
-	MX7ULP_PAD_PTF11__FB_CS4_b_FB_TSIZ0_FB_BE31_24_BLS7_0_b      = IOMUX_PAD(0x01AC, 0x01AC, 0x9, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTF11__USB1_ULPI_DIR                              = IOMUX_PAD(0x01AC, 0x01AC, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B      = IOMUX_PAD(0x01AC, 0x01AC, 0x9, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF11__USB1_DIR                                   = IOMUX_PAD(0x01AC, 0x01AC, 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF11__VIU_D7                                     = IOMUX_PAD(0x01AC, 0x01AC, 0xc, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF12__PTF12                                      = IOMUX_PAD(0x01B0, 0x01B0, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF12__FXIO1_D8                                   = IOMUX_PAD(0x01B0, 0x01B0, 0x2, 0x0224, 0x2, 0),
 	MX7ULP_PAD_PTF12__LPSPI3_PCS1                                = IOMUX_PAD(0x01B0, 0x01B0, 0x3, 0x0314, 0x3, 0),
-	MX7ULP_PAD_PTF12__LPUART7_CTS_b                              = IOMUX_PAD(0x01B0, 0x01B0, 0x4, 0x0268, 0x3, 0),
+	MX7ULP_PAD_PTF12__LPUART7_CTS_B                              = IOMUX_PAD(0x01B0, 0x01B0, 0x4, 0x0268, 0x3, 0),
 	MX7ULP_PAD_PTF12__LPI2C7_SCL                                 = IOMUX_PAD(0x01B0, 0x01B0, 0x5, 0x0308, 0x3, 0),
 	MX7ULP_PAD_PTF12__TPM7_CH5                                   = IOMUX_PAD(0x01B0, 0x01B0, 0x6, 0x02F0, 0x3, 0),
 	MX7ULP_PAD_PTF12__FB_AD24                                    = IOMUX_PAD(0x01B0, 0x01B0, 0x9, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTF12__USB1_ULPI_DATA0                            = IOMUX_PAD(0x01B0, 0x01B0, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF12__USB1_DATA0                                 = IOMUX_PAD(0x01B0, 0x01B0, 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF12__VIU_D8                                     = IOMUX_PAD(0x01B0, 0x01B0, 0xc, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF13__PTF13                                      = IOMUX_PAD(0x01B4, 0x01B4, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF13__FXIO1_D9                                   = IOMUX_PAD(0x01B4, 0x01B4, 0x2, 0x0228, 0x2, 0),
 	MX7ULP_PAD_PTF13__LPSPI3_PCS2                                = IOMUX_PAD(0x01B4, 0x01B4, 0x3, 0x0318, 0x3, 0),
-	MX7ULP_PAD_PTF13__LPUART7_RTS_b                              = IOMUX_PAD(0x01B4, 0x01B4, 0x4, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF13__LPUART7_RTS_B                              = IOMUX_PAD(0x01B4, 0x01B4, 0x4, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF13__LPI2C7_SDA                                 = IOMUX_PAD(0x01B4, 0x01B4, 0x5, 0x030C, 0x3, 0),
 	MX7ULP_PAD_PTF13__TPM7_CLKIN                                 = IOMUX_PAD(0x01B4, 0x01B4, 0x6, 0x02F4, 0x3, 0),
 	MX7ULP_PAD_PTF13__FB_AD25                                    = IOMUX_PAD(0x01B4, 0x01B4, 0x9, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTF13__USB1_ULPI_DATA1                            = IOMUX_PAD(0x01B4, 0x01B4, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF13__USB1_DATA1                                 = IOMUX_PAD(0x01B4, 0x01B4, 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF13__VIU_D9                                     = IOMUX_PAD(0x01B4, 0x01B4, 0xc, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF14__PTF14                                      = IOMUX_PAD(0x01B8, 0x01B8, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF14__FXIO1_D10                                  = IOMUX_PAD(0x01B8, 0x01B8, 0x2, 0x022C, 0x2, 0),
@@ -868,38 +845,38 @@ enum {
 	MX7ULP_PAD_PTF14__LPI2C7_HREQ                                = IOMUX_PAD(0x01B8, 0x01B8, 0x5, 0x0304, 0x3, 0),
 	MX7ULP_PAD_PTF14__TPM7_CH0                                   = IOMUX_PAD(0x01B8, 0x01B8, 0x6, 0x02DC, 0x3, 0),
 	MX7ULP_PAD_PTF14__FB_AD26                                    = IOMUX_PAD(0x01B8, 0x01B8, 0x9, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTF14__USB1_ULPI_DATA2                            = IOMUX_PAD(0x01B8, 0x01B8, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF14__USB1_DATA2                                 = IOMUX_PAD(0x01B8, 0x01B8, 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF14__VIU_D10                                    = IOMUX_PAD(0x01B8, 0x01B8, 0xc, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF15__PTF15                                      = IOMUX_PAD(0x01BC, 0x01BC, 0x1, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF15__FXIO1_D11                                  = IOMUX_PAD(0x01BC, 0x01BC, 0x2, 0x0230, 0x2, 0),
 	MX7ULP_PAD_PTF15__LPUART7_RX                                 = IOMUX_PAD(0x01BC, 0x01BC, 0x4, 0x026C, 0x3, 0),
 	MX7ULP_PAD_PTF15__TPM7_CH1                                   = IOMUX_PAD(0x01BC, 0x01BC, 0x6, 0x02E0, 0x3, 0),
 	MX7ULP_PAD_PTF15__FB_AD27                                    = IOMUX_PAD(0x01BC, 0x01BC, 0x9, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTF15__USB1_ULPI_DATA3                            = IOMUX_PAD(0x01BC, 0x01BC, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF15__USB1_DATA3                                 = IOMUX_PAD(0x01BC, 0x01BC, 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF15__VIU_D11                                    = IOMUX_PAD(0x01BC, 0x01BC, 0xc, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF16__PTF16                                      = IOMUX_PAD(0x01C0, 0x01C0, 0x1, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTF16__USB1_ULPI_DATA4                            = IOMUX_PAD(0x01C0, 0x01C0, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF16__USB1_DATA4                                 = IOMUX_PAD(0x01C0, 0x01C0, 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF16__VIU_D12                                    = IOMUX_PAD(0x01C0, 0x01C0, 0xc, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF16__FXIO1_D12                                  = IOMUX_PAD(0x01C0, 0x01C0, 0x2, 0x0234, 0x2, 0),
 	MX7ULP_PAD_PTF16__LPSPI3_SIN                                 = IOMUX_PAD(0x01C0, 0x01C0, 0x3, 0x0324, 0x3, 0),
 	MX7ULP_PAD_PTF16__TPM7_CH2                                   = IOMUX_PAD(0x01C0, 0x01C0, 0x6, 0x02E4, 0x3, 0),
 	MX7ULP_PAD_PTF16__FB_AD28                                    = IOMUX_PAD(0x01C0, 0x01C0, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF17__PTF17                                      = IOMUX_PAD(0x01C4, 0x01C4, 0x1, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTF17__USB1_ULPI_DATA5                            = IOMUX_PAD(0x01C4, 0x01C4, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF17__USB1_DATA5                                 = IOMUX_PAD(0x01C4, 0x01C4, 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF17__VIU_D13                                    = IOMUX_PAD(0x01C4, 0x01C4, 0xc, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF17__FXIO1_D13                                  = IOMUX_PAD(0x01C4, 0x01C4, 0x2, 0x0238, 0x2, 0),
 	MX7ULP_PAD_PTF17__LPSPI3_SOUT                                = IOMUX_PAD(0x01C4, 0x01C4, 0x3, 0x0328, 0x3, 0),
 	MX7ULP_PAD_PTF17__TPM6_CLKIN                                 = IOMUX_PAD(0x01C4, 0x01C4, 0x6, 0x02D8, 0x3, 0),
 	MX7ULP_PAD_PTF17__FB_AD29                                    = IOMUX_PAD(0x01C4, 0x01C4, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF18__PTF18                                      = IOMUX_PAD(0x01C8, 0x01C8, 0x1, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTF18__USB1_ULPI_DATA6                            = IOMUX_PAD(0x01C8, 0x01C8, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF18__USB1_DATA6                                 = IOMUX_PAD(0x01C8, 0x01C8, 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF18__VIU_D14                                    = IOMUX_PAD(0x01C8, 0x01C8, 0xc, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF18__FXIO1_D14                                  = IOMUX_PAD(0x01C8, 0x01C8, 0x2, 0x023C, 0x2, 0),
 	MX7ULP_PAD_PTF18__LPSPI3_SCK                                 = IOMUX_PAD(0x01C8, 0x01C8, 0x3, 0x0320, 0x3, 0),
 	MX7ULP_PAD_PTF18__TPM6_CH0                                   = IOMUX_PAD(0x01C8, 0x01C8, 0x6, 0x02D0, 0x3, 0),
 	MX7ULP_PAD_PTF18__FB_AD30                                    = IOMUX_PAD(0x01C8, 0x01C8, 0x9, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF19__PTF19                                      = IOMUX_PAD(0x01CC, 0x01CC, 0x1, 0x0000, 0x0, 0),
-	MX7ULP_PAD_PTF19__USB1_ULPI_DATA7                            = IOMUX_PAD(0x01CC, 0x01CC, 0xb, 0x0000, 0x0, 0),
+	MX7ULP_PAD_PTF19__USB1_DATA7                                 = IOMUX_PAD(0x01CC, 0x01CC, 0xb, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF19__VIU_D15                                    = IOMUX_PAD(0x01CC, 0x01CC, 0xc, 0x0000, 0x0, 0),
 	MX7ULP_PAD_PTF19__FXIO1_D15                                  = IOMUX_PAD(0x01CC, 0x01CC, 0x2, 0x0240, 0x2, 0),
 	MX7ULP_PAD_PTF19__LPSPI3_PCS0                                = IOMUX_PAD(0x01CC, 0x01CC, 0x3, 0x0310, 0x3, 0),
diff --git a/arch/arm/include/asm/arch-mx7ulp/scg.h b/arch/arm/include/asm/arch-mx7ulp/scg.h
index 3b5b7f6803c..59cb92473ab 100644
--- a/arch/arm/include/asm/arch-mx7ulp/scg.h
+++ b/arch/arm/include/asm/arch-mx7ulp/scg.h
@@ -323,6 +323,7 @@ typedef struct scg_regs {
 
 u32 scg_clk_get_rate(enum scg_clk clk);
 int scg_enable_pll_pfd(enum scg_clk clk, u32 frac);
+int scg_disable_pll_pfd(enum scg_clk clk);
 int scg_enable_usb_pll(bool usb_control);
 u32 decode_pll(enum pll_clocks pll);
 
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 085e12b5d4d..8d25c32c3a9 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -90,10 +90,16 @@ struct arch_global_data {
 	struct udevice *scu_dev;
 #endif
 
-#ifdef CONFIG_ARCH_IMX8ULP
+#ifdef CONFIG_IMX_SENTINEL
 	struct udevice *s400_dev;
+	u32 soc_rev;
+	u32 lifecycle;
+	u32 uid[4];
 #endif
 
+#ifdef CONFIG_ARCH_IMX8ULP
+	bool m33_handshake_done;
+#endif
 };
 
 #include <asm-generic/global_data.h>
diff --git a/arch/arm/include/asm/mach-imx/ahab.h b/arch/arm/include/asm/mach-imx/ahab.h
new file mode 100644
index 00000000000..2b152d2d222
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/ahab.h
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __IMX_AHAB_H__
+#define __IMX_AHAB_H__
+
+#include <asm/mach-imx/image.h>
+
+int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length);
+int ahab_auth_release(void);
+int ahab_verify_cntr_image(struct boot_img_t *img, int image_index);
+
+#endif
diff --git a/arch/arm/include/asm/mach-imx/boot_mode.h b/arch/arm/include/asm/mach-imx/boot_mode.h
index 6dc58559680..a568c443722 100644
--- a/arch/arm/include/asm/mach-imx/boot_mode.h
+++ b/arch/arm/include/asm/mach-imx/boot_mode.h
@@ -29,6 +29,7 @@ enum boot_device {
 	QSPI_BOOT,
 	FLEXSPI_BOOT,
 	USB_BOOT,
+	USB2_BOOT,
 	UNKNOWN_BOOT,
 	BOOT_DEV_NUM = UNKNOWN_BOOT,
 };
diff --git a/arch/arm/include/asm/mach-imx/imx_vservice.h b/arch/arm/include/asm/mach-imx/imx_vservice.h
new file mode 100644
index 00000000000..9e083e98443
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/imx_vservice.h
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ *
+ */
+
+#ifndef __IMX_VSERVICE_H__
+#define __IMX_VSERVICE_H__
+
+#include <common.h>
+#include <linux/list.h>
+
+struct imx_vservice_channel
+{
+	u32 msg_seq;
+	struct udevice *mu_dev;
+	struct list_head channel_head;
+};
+
+void * imx_vservice_get_buffer(struct imx_vservice_channel *node, u32 size);
+int imx_vservice_blocking_request(struct imx_vservice_channel *node, u8 *buf, u32* size);
+struct imx_vservice_channel * imx_vservice_setup(struct udevice *virt_dev);
+
+#endif
diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h
index 231b9c027ce..cd2c6e73e01 100644
--- a/arch/arm/include/asm/mach-imx/iomux-v3.h
+++ b/arch/arm/include/asm/mach-imx/iomux-v3.h
@@ -86,7 +86,16 @@ typedef u64 iomux_v3_cfg_t;
 #define IOMUX_CONFIG_LPSR       0x20
 #define MUX_MODE_LPSR           ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
 				MUX_MODE_SHIFT)
-#ifdef CONFIG_IMX8M
+#ifdef CONFIG_IMX93
+#define PAD_CTL_FSEL2		(0x2 << 7)
+#define PAD_CTL_FSEL3		(0x3 << 7)
+#define PAD_CTL_PUE		(0x1 << 9)
+#define PAD_CTL_PDE		(0x1 << 10)
+#define PAD_CTL_ODE		(0x1 << 11)
+#define PAD_CTL_HYS		(0x1 << 12)
+#define PAD_CTL_DSE(x)		(((x) << 1) & 0x7f)
+
+#elif defined(CONFIG_IMX8M)
 #define PAD_CTL_FSEL0		(0x0 << 3)
 #define PAD_CTL_FSEL1		(0x1 << 3)
 #define PAD_CTL_FSEL2		(0x2 << 3)
@@ -282,10 +291,10 @@ if (is_mx6dq() || is_mx6dqp()) {				\
 }
 #define SETUP_IOMUX_PADS(x)					\
 	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
-#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
-#define IOMUX_PADS(x) MX6Q_##x
+#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6QP)
+#define IOMUX_PADS(x) MX6_##x
 #define SETUP_IOMUX_PAD(def)					\
-	imx_iomux_v3_setup_pad(MX6Q_##def);
+	imx_iomux_v3_setup_pad(MX6_##def);
 #define SETUP_IOMUX_PADS(x)					\
 	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
 #elif defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
@@ -295,9 +304,9 @@ if (is_mx6dq() || is_mx6dqp()) {				\
 #define SETUP_IOMUX_PADS(x)					\
 	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
 #else
-#define IOMUX_PADS(x) MX6DL_##x
+#define IOMUX_PADS(x) MX6_##x
 #define SETUP_IOMUX_PAD(def)					\
-	imx_iomux_v3_setup_pad(MX6DL_##def);
+	imx_iomux_v3_setup_pad(MX6_##def);
 #define SETUP_IOMUX_PADS(x)					\
 	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
 #endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h b/arch/arm/include/asm/mach-imx/mu_hal.h
index 10d966d5d43..5db559c1ac5 100644
--- a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h
+++ b/arch/arm/include/asm/mach-imx/mu_hal.h
@@ -3,8 +3,8 @@
  * Copyright 2021 NXP
  */
 
-#ifndef __IMX8ULP_MU_HAL_H__
-#define __IMX8ULP_MU_HAL_H__
+#ifndef __SNT_MU_HAL_H__
+#define __SNT_MU_HAL_H__
 
 void mu_hal_init(ulong base);
 int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg);
diff --git a/arch/arm/include/asm/mach-imx/mxc_key_defs.h b/arch/arm/include/asm/mach-imx/mxc_key_defs.h
new file mode 100644
index 00000000000..3c0f4ce4545
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/mxc_key_defs.h
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2009-2014 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ */
+
+#ifndef _MXC_KEYPAD_H_
+#define _MXC_KEYPAD_H_
+
+#define KEY_1                   2
+#define KEY_2                   3
+#define KEY_3                   4
+#define KEY_F1                  59
+#define KEY_UP                  103
+#define KEY_F2                  60
+
+#define KEY_4                   5
+#define KEY_5                   6
+#define KEY_6                   7
+#define KEY_LEFT                105
+#define KEY_SELECT              0x161
+#define KEY_RIGHT               106
+
+#define KEY_7                   8
+#define KEY_8                   9
+#define KEY_9                   10
+#define KEY_F3                  61
+#define KEY_DOWN                108
+#define KEY_F4                  62
+
+#define KEY_0                   11
+#define KEY_OK                  0x160
+#define KEY_ESC                 1
+#define KEY_ENTER               28
+#define KEY_MENU                139     /* Menu (show menu) */
+#define KEY_BACK                158     /* AC Back */
+
+#endif
diff --git a/arch/arm/include/asm/mach-imx/optee.h b/arch/arm/include/asm/mach-imx/optee.h
new file mode 100644
index 00000000000..f13c5a397f8
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/optee.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+#ifndef __IMX_OPTEE_H__
+#define __IMX_OPTEE_H__
+
+#include <common.h>
+
+#define OPTEE_SHM_SIZE 0x00400000
+int ft_add_optee_node(void *fdt, struct bd_info *bd);
+#endif
diff --git a/arch/arm/include/asm/mach-imx/regs-bch.h b/arch/arm/include/asm/mach-imx/regs-bch.h
index 5a149002e2a..d2acb1194ab 100644
--- a/arch/arm/include/asm/mach-imx/regs-bch.h
+++ b/arch/arm/include/asm/mach-imx/regs-bch.h
@@ -36,6 +36,7 @@ struct mxs_bch_regs {
 	mxs_reg_32(hw_bch_flash2layout1)
 	mxs_reg_32(hw_bch_flash3layout0)
 	mxs_reg_32(hw_bch_flash3layout1)
+	mxs_reg_32(hw_bch_debug0)
 	mxs_reg_32(hw_bch_dbgkesread)
 	mxs_reg_32(hw_bch_dbgcsferead)
 	mxs_reg_32(hw_bch_dbgsyndegread)
diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h b/arch/arm/include/asm/mach-imx/regs-lcdif.h
index 58746387966..a44ce354223 100644
--- a/arch/arm/include/asm/mach-imx/regs-lcdif.h
+++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h
@@ -22,7 +22,7 @@ struct mxs_lcdif_regs {
 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
 	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
-	defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT)
+	defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) || defined(CONFIG_IMXRT)
 	mxs_reg_32(hw_lcdif_ctrl2)		/* 0x20 */
 #endif
 	mxs_reg_32(hw_lcdif_transfer_count)	/* 0x20/0x30 */
@@ -61,7 +61,7 @@ struct mxs_lcdif_regs {
 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
 	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
-	defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT)
+	defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) || defined(CONFIG_IMXRT)
 	mxs_reg_32(hw_lcdif_crc_stat)		/* 0x1a0 */
 #endif
 	mxs_reg_32(hw_lcdif_lcdif_stat)		/* 0x1d0/0x1b0 */
@@ -73,7 +73,7 @@ struct mxs_lcdif_regs {
 	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
 	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
 	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
-	defined(CONFIG_IMX8M)
+	defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
 	mxs_reg_32(hw_lcdif_thres)
 	mxs_reg_32(hw_lcdif_as_ctrl)
 	mxs_reg_32(hw_lcdif_as_buf)
diff --git a/arch/arm/include/asm/mach-imx/regs-usbphy.h b/arch/arm/include/asm/mach-imx/regs-usbphy.h
index 2b18ec20f3f..bd1bca54b61 100644
--- a/arch/arm/include/asm/mach-imx/regs-usbphy.h
+++ b/arch/arm/include/asm/mach-imx/regs-usbphy.h
@@ -22,4 +22,7 @@
 #define USBPHY_CTRL_CLKGATE				(1 << 30)
 #define USBPHY_CTRL_SFTRST				(1 << 31)
 
+#define USBNC_PHY_STATUS_OFFSET	0x23C
+#define USBNC_PHYSTATUS_ID_DIG	(1 << 4) /* otg_id status */
+
 #endif /* __REGS_USBPHY_H__ */
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h b/arch/arm/include/asm/mach-imx/s400_api.h
new file mode 100644
index 00000000000..9e3c8136dfb
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -0,0 +1,148 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef __S400_API_H__
+#define __S400_API_H__
+
+#define AHAB_VERSION    0x6
+#define AHAB_CMD_TAG    0x17
+#define AHAB_RESP_TAG   0xe1
+
+/* ELE commands */
+#define ELE_PING_REQ (0x01)
+#define ELE_FW_AUTH_REQ (0x02)
+#define ELE_RESTART_RST_TIMER_REQ (0x04)
+#define ELE_DUMP_DEBUG_BUFFER_REQ (0x21)
+#define ELE_OEM_CNTN_AUTH_REQ (0x87)
+#define ELE_VERIFY_IMAGE_REQ (0x88)
+#define ELE_RELEASE_CONTAINER_REQ (0x89)
+#define ELE_WRITE_SECURE_FUSE_REQ (0x91)
+#define ELE_FWD_LIFECYCLE_UP_REQ (0x95)
+#define ELE_READ_FUSE_REQ (0x97)
+#define ELE_GET_FW_VERSION_REQ (0x9D)
+#define ELE_RET_LIFECYCLE_UP_REQ (0xA0)
+#define ELE_GET_EVENTS_REQ (0xA2)
+#define ELE_START_RNG (0xA3)
+#define ELE_ENABLE_PATCH_REQ (0xC3)
+#define ELE_RELEASE_RDC_REQ (0xC4)
+#define ELE_GET_FW_STATUS_REQ (0xC5)
+#define ELE_ENABLE_OTFAD_REQ (0xC6)
+#define ELE_RESET_REQ (0xC7)
+#define ELE_UPDATE_OTP_CLKDIV_REQ (0xD0)
+#define ELE_POWER_DOWN_REQ (0xD1)
+#define ELE_ENABLE_APC_REQ (0xD2)
+#define ELE_ENABLE_RTC_REQ (0xD3)
+#define ELE_DEEP_POWER_DOWN_REQ (0xD4)
+#define ELE_STOP_RST_TIMER_REQ (0xD5)
+#define ELE_WRITE_FUSE_REQ (0xD6)
+#define ELE_RELEASE_CAAM_REQ (0xD7)
+#define ELE_RESET_A35_CTX_REQ (0xD8)
+#define ELE_MOVE_TO_UNSECURED_REQ (0xD9)
+#define ELE_GET_INFO_REQ (0xDA)
+#define ELE_ATTEST_REQ (0xDB)
+#define ELE_RELEASE_PATCH_REQ (0xDC)
+#define ELE_OTP_SEQ_SWITH_REQ (0xDD)
+
+/* ELE failure indications */
+#define ELE_ROM_PING_FAILURE_IND (0x0A)
+#define ELE_FW_PING_FAILURE_IND (0x1A)
+#define ELE_BAD_SIGNATURE_FAILURE_IND (0xF0)
+#define ELE_BAD_HASH_FAILURE_IND (0xF1)
+#define ELE_INVALID_LIFECYCLE_IND (0xF2)
+#define ELE_PERMISSION_DENIED_FAILURE_IND (0xF3)
+#define ELE_INVALID_MESSAGE_FAILURE_IND (0xF4)
+#define ELE_BAD_VALUE_FAILURE_IND (0xF5)
+#define ELE_BAD_FUSE_ID_FAILURE_IND (0xF6)
+#define ELE_BAD_CONTAINER_FAILURE_IND (0xF7)
+#define ELE_BAD_VERSION_FAILURE_IND (0xF8)
+#define ELE_INVALID_KEY_FAILURE_IND (0xF9)
+#define ELE_BAD_KEY_HASH_FAILURE_IND (0xFA)
+#define ELE_NO_VALID_CONTAINER_FAILURE_IND (0xFB)
+#define ELE_BAD_CERTIFICATE_FAILURE_IND (0xFC)
+#define ELE_BAD_UID_FAILURE_IND (0xFD)
+#define ELE_BAD_MONOTONIC_COUNTER_FAILURE_IND (0xFE)
+#define ELE_MUST_SIGNED_FAILURE_IND (0xE0)
+#define ELE_NO_AUTHENTICATION_FAILURE_IND (0xEE)
+#define ELE_BAD_SRK_SET_FAILURE_IND (0xEF)
+#define ELE_UNALIGNED_PAYLOAD_FAILURE_IND (0xA6)
+#define ELE_WRONG_SIZE_FAILURE_IND (0xA7)
+#define ELE_ENCRYPTION_FAILURE_IND (0xA8)
+#define ELE_DECRYPTION_FAILURE_IND (0xA9)
+#define ELE_OTP_PROGFAIL_FAILURE_IND (0xAA)
+#define ELE_OTP_LOCKED_FAILURE_IND (0xAB)
+#define ELE_OTP_INVALID_IDX_FAILURE_IND (0xAD)
+#define ELE_TIME_OUT_FAILURE_IND (0xB0)
+#define ELE_BAD_PAYLOAD_FAILURE_IND (0xB1)
+#define ELE_WRONG_ADDRESS_FAILURE_IND (0xB4)
+#define ELE_DMA_FAILURE_IND (0xB5)
+#define ELE_DISABLED_FEATURE_FAILURE_IND (0xB6)
+#define ELE_MUST_ATTEST_FAILURE_IND (0xB7)
+#define ELE_RNG_NOT_STARTED_FAILURE_IND (0xB8)
+#define ELE_CRC_ERROR_IND (0xB9)
+#define ELE_AUTH_SKIPPED_OR_FAILED_FAILURE_IND (0xBB)
+#define ELE_INCONSISTENT_PAR_FAILURE_IND (0xBC)
+#define ELE_RNG_INST_FAILURE_FAILURE_IND (0xBD)
+#define ELE_LOCKED_REG_FAILURE_IND (0xBE)
+#define ELE_BAD_ID_FAILURE_IND (0xBF)
+#define ELE_INVALID_OPERATION_FAILURE_IND (0xC0)
+#define ELE_NON_SECURE_STATE_FAILURE_IND (0xC1)
+#define ELE_MSG_TRUNCATED_IND (0xC2)
+#define ELE_BAD_IMAGE_NUM_FAILURE_IND (0xC3)
+#define ELE_BAD_IMAGE_ADDR_FAILURE_IND (0xC4)
+#define ELE_BAD_IMAGE_PARAM_FAILURE_IND (0xC5)
+#define ELE_BAD_IMAGE_TYPE_FAILURE_IND (0xC6)
+#define ELE_CORRUPTED_SRK_FAILURE_IND (0xD0)
+#define ELE_OUT_OF_MEMORY_IND (0xD1)
+#define ELE_CSTM_FAILURE_IND (0xCF)
+#define ELE_OLD_VERSION_FAILURE_IND (0xCE)
+#define ELE_WRONG_BOOT_MODE_FAILURE_IND (0xCD)
+#define ELE_APC_ALREADY_ENABLED_FAILURE_IND (0xCB)
+#define ELE_RTC_ALREADY_ENABLED_FAILURE_IND (0xCC)
+#define ELE_ABORT_IND (0xFF)
+
+/* ELE IPC identifier */
+#define ELE_IPC_MU_RTD (0x1)
+#define ELE_IPC_MU_APD (0x2)
+
+/* ELE Status*/
+#define ELE_SUCCESS_IND (0xD6)
+#define ELE_FAILURE_IND (0x29)
+
+#define S400_MAX_MSG          255U
+
+struct sentinel_msg {
+	u8 version;
+	u8 size;
+	u8 command;
+	u8 tag;
+	u32 data[(S400_MAX_MSG - 1U)];
+};
+
+struct sentinel_get_info_data{
+	u32 hdr;
+	u32 soc;
+	u32 lc;
+	u32 uid[4];
+	u32 sha256_rom_patch[8];
+	u32 sha_fw[8];
+};
+
+int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response);
+int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
+int ahab_release_container(u32 *response);
+int ahab_verify_image(u32 img_id, u32 *response);
+int ahab_forward_lifecycle(u16 life_cycle, u32 *response);
+int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response);
+int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response);
+int ahab_release_caam(u32 core_did, u32 *response);
+int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response);
+int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
+int ahab_get_info(struct sentinel_get_info_data *info, u32 *response);
+int ahab_get_fw_status(u32 *status, u32 *response);
+int ahab_release_m33_trout(void);
+int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response);
+int ahab_start_rng(void);
+
+#endif
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 0c0c7814fb2..972cbbce4bb 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -2,6 +2,7 @@
 /*
  * (C) Copyright 2009
  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ * Copyright 2018-2020 NXP
  */
 
 #ifndef _SYS_PROTO_H_
@@ -31,6 +32,7 @@ struct bd_info;
 #define is_mx7() (is_soc_type(MXC_SOC_MX7))
 #define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
 #define is_imx8() (is_soc_type(MXC_SOC_IMX8))
+#define is_imx9() (is_soc_type(MXC_SOC_IMX9))
 #define is_imxrt() (is_soc_type(MXC_SOC_IMXRT))
 
 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
@@ -73,16 +75,23 @@ struct bd_info;
 #define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD))
 #define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS))
 #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP)  || is_cpu_type(MXC_CPU_IMX8MPD) || \
-	is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6))
+	is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MPUL))
 #define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD))
 #define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL))
 #define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6))
+#define is_imx8mpul() (is_cpu_type(MXC_CPU_IMX8MPUL))
 
 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
+#define is_imx8dxl() (is_cpu_type(MXC_CPU_IMX8DXL))
+
+#define is_imx93() (is_cpu_type(MXC_CPU_IMX93))
 
 #define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
 #define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))
 
+/* gd->flags reserves high 16 bits for arch-specific flags */
+#define GD_FLG_ARCH_IMX_USB_BOOT		0x80000000	 /* Only used for MX6/7, If set, the u-boot is booting from USB serial download */
+
 #ifdef CONFIG_MX6
 #define IMX6_SRC_GPR10_BMODE			BIT(28)
 #define IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT	BIT(30)
@@ -145,7 +154,7 @@ struct rproc_att {
 	u32 size; /* size of reg range */
 };
 
-#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX8ULP)
+#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX8ULP) || defined(CONFIG_IMX9)
 struct rom_api {
 	u16 ver;
 	u16 tag;
@@ -207,6 +216,7 @@ void board_mem_get_layout(u64 *phys_sdram_1_start,
 			  u64 *phys_sdram_2_start,
 			  u64 *phys_sdram_2_size);
 
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data);
 int arch_auxiliary_core_check_up(u32 core_id);
 
 int board_mmc_get_env_dev(int devno);
@@ -228,6 +238,14 @@ int mxs_reset_block(struct mxs_register_32 *reg);
 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
 
+void board_late_mmc_env_init(void);
+
+void vadc_power_up(void);
+void vadc_power_down(void);
+
+void pcie_power_up(void);
+void pcie_power_off(void);
+
 unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
 			   unsigned long reg1, unsigned long reg2,
 			   unsigned long reg3);
@@ -241,4 +259,8 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
 void enable_ca7_smp(void);
 #endif
 
+int add_res_mem_dt_node(void *fdt, const char *name, phys_addr_t pa,
+			size_t size);
+int add_dt_path_subnode(void *fdt, const char *path, const char *subnode);
+void configure_tzc380(void);
 #endif
diff --git a/arch/arm/include/asm/mach-imx/video.h b/arch/arm/include/asm/mach-imx/video.h
index d1a14ad7d34..51f21f212a8 100644
--- a/arch/arm/include/asm/mach-imx/video.h
+++ b/arch/arm/include/asm/mach-imx/video.h
@@ -1,10 +1,18 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ */
 
 #ifndef __IMX_VIDEO_H_
 #define __IMX_VIDEO_H_
 
 #include <linux/fb.h>
+#if defined(CONFIG_VIDEO_IPUV3)
 #include <ipu_pixfmt.h>
+#elif defined(CONFIG_VIDEO_MXS)
+#include <mxsfb.h>
+#endif
 
 struct display_info_t {
 	int	bus;
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index f75eea16b36..08cbef73289 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -498,7 +498,11 @@ enum dcache_option {
 	DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
 	DCACHE_WRITETHROUGH = TTB_SECT_DOMAIN(0) | TTB_SECT | TTB_SECT_C_MASK,
 	DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
+#ifdef CONFIG_IMX_TRUSTY_OS
+	DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1) | TTB_SECT_S_MASK,
+#else
 	DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
+#endif
 };
 #else
 #define TTB_SECT_AP		(3 << 10)
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index a59a5e6c0ea..d41377c4a3a 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -32,6 +32,7 @@
 #include <bootm.h>
 #include <vxworks.h>
 #include <asm/cache.h>
+#include <video_link.h>
 
 #ifdef CONFIG_ARMV7_NONSEC
 #include <asm/armv7.h>
@@ -65,6 +66,10 @@ static void announce_and_cleanup(int fake)
 	udc_disconnect();
 #endif
 
+#if defined(CONFIG_VIDEO_LINK)
+	video_link_shut_down();
+#endif
+
 	board_quiesce_devices();
 
 	printf("\nStarting kernel ...%s\n\n", fake ?
@@ -74,10 +79,12 @@ static void announce_and_cleanup(int fake)
 	 * This may be useful for last-stage operations, like cancelling
 	 * of DMA operation or releasing device internal buffers.
 	 */
+#ifndef CONFIG_POWER_DOMAIN
 	dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL);
 
 	/* Remove all active vital devices next */
 	dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL);
+#endif
 
 	cleanup_before_linux();
 }
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 0893915b300..a4d790b6e7e 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -249,11 +249,14 @@ static void cache_disable(uint32_t cache_bit)
 	reg = get_cr();
 
 #ifdef CONFIG_SYS_ARM_MMU
-	if (cache_bit == (CR_C | CR_M))
+	if (cache_bit == (CR_C | CR_M)) {
 #elif defined(CONFIG_SYS_ARM_MPU)
-	if (cache_bit == CR_C)
+	if (cache_bit == CR_C) {
 #endif
 		flush_dcache_all();
+		set_cr(reg & ~CR_C);
+		flush_dcache_all();
+	}
 	set_cr(reg & ~cache_bit);
 }
 #endif
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 9aa1d84336b..0616b05a054 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -9,6 +9,11 @@ config IMX_CONFIG
 	depends on MACH_IMX
 	default "arch/arm/mach-imx/spl_sd.cfg"
 
+config IMX_OPTEE
+	bool "Support OP-TEE"
+	help
+	 Enable support for OP-TEE
+
 config ROM_UNIFIED_SECTIONS
 	bool
 
@@ -28,7 +33,7 @@ config IMX_RDC
 
 config IMX_BOOTAUX
 	bool "Support boot auxiliary core"
-	depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8M
+	depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8 || ARCH_IMX8M
 	help
 	  bootaux [addr] to boot auxiliary core.
 
@@ -39,6 +44,26 @@ config IMX_MODULE_FUSE
 	  i.MX module fuse to runtime disable some driver, including
 	  Linux OS device node.
 
+config IMX_VSERVICE_SHARED_BUFFER
+	hex "Define the buffer address used for virtual service"
+	depends on IMX_VSERVICE
+	help
+	  IMX virtual service will use this buffer for exchanging data with remote core.
+
+config IMX_VSERVICE_SHARED_BUFFER_SIZE
+	hex "Define the size of buffer address used for virtual service"
+	default 0x400000
+	depends on IMX_VSERVICE
+	help
+	  The buffer size for IMX virtual service needs enough large to fit all possible message.
+
+config IMX_VSERVICE
+	bool
+    select MISC
+    select IMX_M4_MU
+	help
+	  This enables imx virtual service provides framework for imx virtual driver working.
+
 config USE_IMXIMG_PLUGIN
 	bool "Use imximage plugin code"
 	depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX7ULP
@@ -51,6 +76,7 @@ config IMX_HAB
 	depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M || ARCH_MX7ULP
 	select FSL_CAAM if HAS_CAAM
 	imply CMD_DEKBLOB if HAS_CAAM
+	imply CMD_PROVISION_KEY if HAS_CAAM
 	help
 	  This option enables the support for secure boot (HAB).
 	  See doc/imx/habv4/* for more details.
@@ -90,6 +116,7 @@ config CMD_DEKBLOB
 	  more information.
 
 config IMX_CAAM_DEK_ENCAP
+	select FSL_BLOB
 	bool "Support the DEK blob encapsulation with CAAM U-Boot driver"
 	help
 	  This enables the DEK blob encapsulation with the U-Boot CAAM driver.
@@ -127,7 +154,7 @@ config CMD_NANDBCB
 	bool "i.MX6 NAND Boot Control Block(BCB) command"
 	depends on MTD_RAW_NAND && CMD_MTDPARTS
 	select BCH if MX6UL || MX6ULL
-	default y if ((ARCH_MX6 || ARCH_MX7 || ARCH_IMX8M) && NAND_MXS)
+	default y if ((ARCH_MX6 || ARCH_MX7 || ARCH_IMX8M || ARCH_IMX8) && NAND_MXS)
 	help
 	  Unlike normal 'nand write/erase' commands, this command update
 	  Boot Control Block(BCB) for i.MX6 platform NAND IP's.
@@ -135,15 +162,45 @@ config CMD_NANDBCB
 	  This is similar to kobs-ng, which is used in Linux as separate
 	  rootfs package.
 
+config CMD_QSPIHDR
+	bool "Q(F)SPI Boot Config Header command"
+	depends on DM_SPI_FLASH
+	default y
+	help
+	  Boot from Q(F)SPI need a boot config header, this command can
+	  help to check if header already exists or add one if not.
+
 config FSL_MFGPROT
 	bool "Support the 'mfgprot' command"
-	depends on IMX_HAB && ARCH_MX7
+	depends on IMX_HAB || AHAB_BOOT
+	select IMX_CAAM_MFG_PROT if (ARCH_MX7 || ARCH_IMX8M)
+	select IMX_SECO_MFG_PROT if ARCH_IMX8
 	help
 	  This option enables the manufacturing protection command
 	  which can be used has a protection feature for Manufacturing
 	  process. With this tool is possible to authenticate the
 	  chip to the OEM's server.
 
+config IMX_CAAM_MFG_PROT
+	bool "Support the manufacturing protection with CAAM U-Boot driver"
+	help
+	  This enables the manufacturing protection feature with the U-Boot
+	  CAAM driver. This option is only available on iMX7D/S.
+
+config IMX_SECO_MFG_PROT
+	bool "Support the manufacturing protection with SECO API"
+	help
+	  This enables the manufacturing protection feature with the SECO API.
+	  This option is only available on iMX8/8x series.
+
+config DBG_MONITOR
+	bool "Enable the AXI debug monitor"
+	depends on ARCH_MX6 || ARCH_MX7
+	help
+	  This option enables the debug monitor which prints out last
+	  failed AXI access info when system reboot is caused by AXI
+	  access failure.
+
 config NXP_BOARD_REVISION
 	bool "Read NXP board revision from fuses"
 	depends on ARCH_MX6 || ARCH_MX7
@@ -152,6 +209,12 @@ config NXP_BOARD_REVISION
 	  stored in the fuses. Select this option if you want to be able to
 	  retrieve the board revision information.
 
+config FLASH_MCUFIRMWARE_SUPPORT
+	bool "Enable mcu firmware flash support"
+	depends on ARCH_MX7ULP || ARCH_IMX8M
+	help
+	  This enables the mcu firmware flash support for some SOCs.
+
 config DDRMC_VF610_CALIBRATION
 	bool "Enable DDRMC (DDR3) on-chip calibration"
 	depends on ARCH_VF610
@@ -166,11 +229,12 @@ config DDRMC_VF610_CALIBRATION
 
 config SPL_IMX_ROMAPI_LOADADDR
 	hex "Default load address to load image through ROM API"
-	depends on IMX8MN || IMX8MP || IMX8ULP
+	depends on IMX8MN || IMX8MP || IMX8ULP || IMX9
 
 config IMX_DCD_ADDR
 	hex "DCD Blocks location on the image"
-	default 0x00910000 if !ARCH_MX7ULP
+	default 0x00910000 if (!ARCH_MX7ULP && !ARCH_MX7)
+	default 0x00911000 if ARCH_MX7
 	default 0x2f010000 if ARCH_MX7ULP
 	help
 	  Indicates where the Device Configuration Data, a binary table used by
@@ -190,3 +254,153 @@ config IMX_CONTAINER_CFG
 	help
 	  This is to specific the cfg file for generating container
 	  image which will be loaded by SPL.
+
+config CMD_PROVISION_KEY
+	bool "Support to provision a encrypted key as black blob"
+	depends on IMX8MM || IMX8MN
+	select IMX_CAAM_MFG_PROT
+	help
+	  reads manufacturing protection public key(MPPUBK).
+	  derive PKEK = sha256(MPPUBK).
+	  read encrypted key and decrypt it using PKEK.
+	  generate black blob of decrypted key, add 20 bytes TAG to black blob.
+
+config ANDROID_SUPPORT
+	bool "Standard Android features support"
+	default n
+	select FSL_FASTBOOT
+	select FASTBOOT_LOCK
+	select BCB_SUPPORT
+	select ANDROID_RECOVERY
+	select SUPPORT_RAW_INITRD
+	select LIBAVB
+	select AVB_SUPPORT
+
+config ANDROID_AUTO_SUPPORT
+	bool "Android Automotive features support"
+	default n
+	select FSL_FASTBOOT
+	select FASTBOOT_LOCK
+	select BCB_SUPPORT
+	select ANDROID_RECOVERY
+	select SUPPORT_RAW_INITRD
+	select LIBAVB
+	select AVB_SUPPORT
+
+config ANDROID_THINGS_SUPPORT
+	bool "Android Things features support"
+	default n
+	select FSL_FASTBOOT
+	select FASTBOOT_LOCK
+	select BCB_SUPPORT
+	select ANDROID_RECOVERY
+	select SUPPORT_RAW_INITRD
+	select LIBAVB
+	select AVB_SUPPORT
+
+config AT_AUTHENTICATE_UNLOCK
+	bool "Enable authenticate unlock for Android Things devices"
+	depends on ANDROID_THINGS_SUPPORT
+
+config ANDROID_AB_SUPPORT
+	bool "Android A/B slots support"
+	depends on ANDROID_SUPPORT || ANDROID_AUTO_SUPPORT || ANDROID_THINGS_SUPPORT
+	default n
+	select SYSTEM_RAMDISK_SUPPORT
+
+config SYSTEM_RAMDISK_SUPPORT
+	bool "Support build ramdisk in system image"
+	default n
+
+menu "TRUSTY OS Support"
+
+config IMX_TRUSTY_OS
+	bool "Support Trusty OS related feature"
+	select SYS_ARM_CACHE_WRITEALLOC
+	select CMD_MMC_RPMB
+	select SUPPORT_EMMC_RPMB
+	select SPL_SUPPORT_EMMC_RPMB
+	select SPL_MMC_WRITE
+
+config TRUSTY_UNLOCK_PERMISSION
+	bool "Support unlock permission protection in trusty"
+	default y
+	depends on IMX_TRUSTY_OS
+
+config LOAD_KEY_FROM_RPMB
+	bool "Support load AVB public key from RPMB storage"
+	default y
+	depends on IMX_TRUSTY_OS
+
+config ID_ATTESTATION
+	bool "Support device ID attestation"
+	default y
+	depends on IMX_TRUSTY_OS
+
+config ATTESTATION_ID_BRAND
+	string "brand name"
+	depends on IMX_TRUSTY_OS && ID_ATTESTATION
+	default ""
+
+config ATTESTATION_ID_DEVICE
+	string "device name"
+	depends on IMX_TRUSTY_OS && ID_ATTESTATION
+	default ""
+
+config ATTESTATION_ID_PRODUCT
+	string "product name"
+	depends on IMX_TRUSTY_OS && ID_ATTESTATION
+	default ""
+
+config ATTESTATION_ID_IMEI
+	string "IMEI id"
+	depends on IMX_TRUSTY_OS && ID_ATTESTATION
+	default ""
+
+config ATTESTATION_ID_MEID
+	string "MEID id"
+	depends on IMX_TRUSTY_OS && ID_ATTESTATION
+	default ""
+
+config ATTESTATION_ID_MANUFACTURER
+	string "manufacture name"
+	depends on IMX_TRUSTY_OS && ID_ATTESTATION
+	default ""
+
+config ATTESTATION_ID_MODEL
+	string "model name"
+	depends on IMX_TRUSTY_OS && ID_ATTESTATION
+	default ""
+
+config GENERATE_MPPUBK
+	bool "Enable manufacturing production public key extraction"
+	default y
+	depends on IMX_TRUSTY_OS
+
+config SECURE_UNLOCK
+	bool "Enable secure unlock for Android devices, it can only be enabled on HAB closed board"
+	depends on IMX_TRUSTY_OS
+
+endmenu
+
+config APPEND_BOOTARGS
+	bool "Append bootargs support"
+
+config DUAL_BOOTLOADER
+	bool "Enable dual bootloader support"
+	select SPL_MMC
+	select SPL_MMC_WRITE
+	help
+	  Enable A/B bootloader select in SPL.
+
+config ANDROID_DYNAMIC_PARTITION
+	bool "Support to boot up Android with system image in logical partitions"
+
+config VIRTUAL_AB_SUPPORT
+	bool "Support virtual AB update"
+	select ANDROID_DYNAMIC_PARTITION
+
+config BOOTLOADER_MENU
+	bool "Enable bootloader menu for android device"
+	help
+	bootloader menu feature for android device.
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 77e72702bba..4ebf95d2b35 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -5,15 +5,16 @@
 #
 # (C) Copyright 2011 Freescale Semiconductor, Inc.
 
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m vf610))
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m imx9 vf610))
 obj-y	= iomux-v3.o
 endif
 
 ifeq ($(SOC),$(filter $(SOC),imx8m))
 ifneq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
+obj-$(CONFIG_CMD_PROVISION_KEY) += cmd_prov_key.o
 endif
-obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
+obj-y += mmc_env.o
 obj-$(CONFIG_FEC_MXC) += mac.o
 obj-$(CONFIG_DWC_ETH_QOS) += mac.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
@@ -29,17 +30,24 @@ endif
 obj-$(CONFIG_GPT_TIMER) += timer.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imxrt))
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx7ulp imx8m imx8 imxrt imx8ulp imx9))
 obj-y	+= misc.o
 obj-$(CONFIG_CMD_PRIBLOB) += priblob.o
 obj-$(CONFIG_SPL_BUILD)	+= spl.o
 endif
+ifeq ($(SOC),$(filter $(SOC),imx8m imx8 imx8ulp imx9))
+obj-y	+= dt_optee.o
+endif
 ifeq ($(SOC),$(filter $(SOC),mx7))
 obj-y	+= cpu.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
-obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
+obj-y += mmc_env.o
+endif
+ifeq ($(SOC),$(filter $(SOC),mx7 imx8 imx8m))
+ifneq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o
 endif
+endif
 ifeq ($(SOC),$(filter $(SOC),mx5 mx6 mx7))
 obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 endif
@@ -53,6 +61,7 @@ endif
 obj-$(CONFIG_SATA) += sata.o
 obj-$(CONFIG_IMX_HAB)    += hab.o
 obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
+obj-$(CONFIG_IMX_TRUSTY_OS) += trusty.o
 endif
 ifeq ($(SOC),$(filter $(SOC),mx7ulp))
 obj-y  += cache.o mmdc_size.o
@@ -62,17 +71,28 @@ ifeq ($(SOC),$(filter $(SOC),vf610))
 obj-y += ddrmc-vf610.o
 obj-$(CONFIG_DDRMC_VF610_CALIBRATION) += ddrmc-vf610-calibration.o
 endif
+ifeq ($(SOC),$(filter $(SOC),imx8))
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
+endif
+endif
 ifneq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
 obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
 obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
 obj-$(CONFIG_CMD_NANDBCB) += cmd_nandbcb.o
+obj-$(CONFIG_CMD_QSPIHDR) += cmd_qspihdr.o
+obj-$(CONFIG_IMX_VSERVICE) += imx_vservice.o
 endif
 
 ifeq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image-container.o parse-container.o
 endif
 
+ifeq ($(SOC),$(filter $(SOC),imx8ulp imx9))
+obj-$(CONFIG_AHAB_BOOT) += ele_ahab.o
+endif
+
 PLUGIN = board/$(BOARDDIR)/plugin
 
 ifeq ($(CONFIG_USE_IMXIMG_PLUGIN),y)
@@ -121,12 +141,41 @@ IMAGE_TYPE := imximage
 DEPFILE_EXISTS := 0
 endif
 
-MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
+MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $(PLUGIN).bin $(QSPI_HEADER) $< $(PHONY),$^) \
 	-T $(IMAGE_TYPE) -e $(CONFIG_SYS_TEXT_BASE)
 u-boot.imx: MKIMAGEOUTPUT = u-boot.imx.log
 
-u-boot.imx: u-boot.bin u-boot.cfgout $(PLUGIN).bin FORCE
+QSPI_HEADER_SOURCE = board/freescale/common/qspi_header
+QSPI_HEADER = qspi_header
+QSPI_HEADER_OFF = 1
+QSPI_UBOOT_OFF = 4
+ifeq ($(SOC),$(filter $(SOC),mx7))
+QSPI_HEADER_OFF = 0
+QSPI_UBOOT_OFF = 1
+endif
+
+ifeq ($(CONFIG_QSPI_BOOT),y)
+$(QSPI_HEADER): $(QSPI_HEADER_SOURCE) FORCE
+	@cp $< $@
+
+else
+$(QSPI_HEADER):
+
+endif
+
+u-boot.imx: u-boot.bin u-boot.cfgout $(PLUGIN).bin $(QSPI_HEADER) FORCE
 	$(call if_changed,mkimage)
+ifeq ($(CONFIG_QSPI_BOOT),y)
+	@awk '{s="0000000"$$1;l=length(s);if(!((NR-1)%4))printf "%08x ",(NR-1)*4; \
+		for(i=1;i<8;i+=2)printf " %s",substr(s,l-i,2);if(!(NR%4))printf "\n";}' \
+		$(QSPI_HEADER) > qspi.tmp
+	@xxd -r qspi.tmp qspi.bin
+	@dd if=$@ of=u-boot.tmp bs=1k seek=$(QSPI_UBOOT_OFF)
+	@dd if=qspi.bin of=u-boot.tmp bs=1k seek=$(QSPI_HEADER_OFF) conv=notrunc
+	@mv u-boot.tmp $@
+	@rm qspi.tmp qspi.bin
+	@echo "Packed QSPI header with $@"
+endif
 
 ifeq ($(CONFIG_MULTI_DTB_FIT),y)
 MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
@@ -138,13 +187,24 @@ ifeq ($(DEPFILE_EXISTS),0)
 	$(call if_changed,mkimage)
 endif
 else ifeq ($(CONFIG_OF_SEPARATE),y)
-MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
+MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $(QSPI_HEADER) $< $(PHONY),$^) \
 	-T $(IMAGE_TYPE) -e $(CONFIG_SYS_TEXT_BASE)
 u-boot-dtb.imx: MKIMAGEOUTPUT = u-boot-dtb.imx.log
 
-u-boot-dtb.imx: u-boot-dtb.bin u-boot-dtb.cfgout $(PLUGIN).bin FORCE
+u-boot-dtb.imx: u-boot-dtb.bin u-boot-dtb.cfgout $(PLUGIN).bin $(QSPI_HEADER) FORCE
 ifeq ($(DEPFILE_EXISTS),0)
 	$(call if_changed,mkimage)
+ifeq ($(CONFIG_QSPI_BOOT),y)
+	@awk '{s="0000000"$$1;l=length(s);if(!((NR-1)%4))printf "%08x ",(NR-1)*4; \
+		for(i=1;i<8;i+=2)printf " %s",substr(s,l-i,2);if(!(NR%4))printf "\n";}' \
+		$(QSPI_HEADER) > qspi.tmp
+	@xxd -r qspi.tmp qspi.bin
+	@dd if=$@ of=u-boot.tmp bs=1k seek=$(QSPI_UBOOT_OFF)
+	@dd if=qspi.bin of=u-boot.tmp bs=1k seek=$(QSPI_HEADER_OFF) conv=notrunc
+	@mv u-boot.tmp $@
+	@rm qspi.tmp qspi.bin
+	@echo "Packed QSPI header with $@"
+endif
 endif
 endif
 
@@ -236,6 +296,7 @@ obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
 obj-$(CONFIG_ARCH_IMX8ULP) += imx8ulp/
 obj-$(CONFIG_IMX8M) += imx8m/
 obj-$(CONFIG_ARCH_IMX8) += imx8/
+obj-$(CONFIG_ARCH_IMX9) += imx9/
 obj-$(CONFIG_ARCH_IMXRT) += imxrt/
 
 obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o
diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c
index 89da89c51d5..701bf516df5 100644
--- a/arch/arm/mach-imx/cmd_dek.c
+++ b/arch/arm/mach-imx/cmd_dek.c
@@ -9,6 +9,7 @@
 #include <command.h>
 #include <log.h>
 #include <malloc.h>
+#include <memalign.h>
 #include <asm/byteorder.h>
 #include <linux/compiler.h>
 #include <fsl_sec.h>
@@ -100,6 +101,7 @@ static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
 			       0x0, &shm_output);
 	if (ret < 0) {
 		printf("Cannot register output shared memory 0x%X\n", ret);
+		tee_shm_free(shm_input);
 		goto error;
 	}
 
@@ -121,11 +123,11 @@ static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
 	if (ret < 0)
 		printf("Cannot generate Blob with PTA DEK Blob 0x%X\n", ret);
 
-error:
 	/* Free shared memory */
 	tee_shm_free(shm_input);
 	tee_shm_free(shm_output);
 
+error:
 	/* Close session */
 	ret = tee_close_session(dev, arg.session);
 	if (ret < 0)
@@ -153,7 +155,7 @@ error:
 
 static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
 {
-	sc_err_t err;
+	int err;
 	sc_rm_mr_t mr_input, mr_output;
 	struct generate_key_blob_hdr hdr;
 	u8 in_size, out_size;
diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c
index aed3b2f83da..b20cd942145 100644
--- a/arch/arm/mach-imx/cmd_mfgprot.c
+++ b/arch/arm/mach-imx/cmd_mfgprot.c
@@ -7,17 +7,19 @@
  * functions in supported i.MX devices.
  */
 
-#include <asm/byteorder.h>
-#include <asm/arch/clock.h>
-#include <linux/compiler.h>
 #include <command.h>
 #include <common.h>
-#include <environment.h>
-#include <fsl_sec.h>
+#include <env.h>
 #include <mapmem.h>
 #include <memalign.h>
-
-DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_IMX_CAAM_MFG_PROT
+#include <asm/arch/clock.h>
+#include <fsl_sec.h>
+#endif
+#ifdef CONFIG_IMX_SECO_MFG_PROT
+#include <asm/io.h>
+#include <asm/arch/sci/sci.h>
+#endif
 
 /**
  * do_mfgprot() - Handle the "mfgprot" command-line command
@@ -29,6 +31,8 @@ DECLARE_GLOBAL_DATA_PTR;
  * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
  * on error.
  */
+#ifdef CONFIG_IMX_CAAM_MFG_PROT
+
 static int do_mfgprot(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
 	u8 *m_ptr, *dgst_ptr, *c_ptr, *d_ptr, *dst_ptr;
@@ -134,6 +138,121 @@ free_m:
 	}
 	return ret;
 }
+#endif /* CONFIG_IMX_CAAM_MFG_PROT */
+
+#ifdef CONFIG_IMX_SECO_MFG_PROT
+
+#define FSL_CAAM_MP_PUBK_BYTES			96
+#define FSL_CAAM_MP_SIGN_BYTES			96
+#define SCU_SEC_SECURE_RAM_BASE			(0x20800000UL)
+#define SEC_SECURE_RAM_BASE			(0x31800000UL)
+
+static int do_mfgprot(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	u8 *m_ptr, *sign_ptr, *dst_ptr;
+	char *pubk, *sign, *sel;
+	int m_size, i, ret;
+	u32 m_addr;
+
+	pubk = "pubk";
+	sign = "sign";
+	sel = argv[1];
+
+	if (!sel)
+		return CMD_RET_USAGE;
+
+	if (strcmp(sel, pubk) == 0) {
+		dst_ptr = malloc_cache_aligned(FSL_CAAM_MP_PUBK_BYTES);
+		if (!dst_ptr)
+			return -ENOMEM;
+
+		puts("\nGenerating Manufacturing Protection Public Key\n");
+
+		ret = sc_seco_get_mp_key(-1, SCU_SEC_SECURE_RAM_BASE,
+					 FSL_CAAM_MP_PUBK_BYTES);
+		if (ret) {
+			printf("SECO get MP key failed, return %d\n", ret);
+			ret = -EIO;
+			free(dst_ptr);
+			return ret;
+		}
+
+		memcpy((void *)dst_ptr, (const void *)SEC_SECURE_RAM_BASE,
+			ALIGN(FSL_CAAM_MP_PUBK_BYTES,
+			CONFIG_SYS_CACHELINE_SIZE));
+
+		/* Output results */
+		puts("\nPublic key:\n");
+		for (i = 0; i < FSL_CAAM_MP_PUBK_BYTES; i++)
+			printf("%02X", (dst_ptr)[i]);
+		puts("\n");
+		free(dst_ptr);
+
+	} else if (strcmp(sel, sign) == 0) {
+		if (argc != 4)
+			return CMD_RET_USAGE;
+
+		m_addr = simple_strtoul(argv[2], NULL, 16);
+		m_size = simple_strtoul(argv[3], NULL, 10);
+		m_ptr = map_physmem(m_addr, m_size, MAP_NOCACHE);
+		if (!m_ptr)
+			return -ENOMEM;
+
+		sign_ptr = malloc_cache_aligned(FSL_CAAM_MP_SIGN_BYTES);
+		if (!sign_ptr) {
+			ret = -ENOMEM;
+			goto free_m;
+		}
+
+		memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)m_ptr,
+			ALIGN(m_size, CONFIG_SYS_CACHELINE_SIZE));
+
+		puts("\nSigning message with SECO MP signature function\n");
+
+		ret = sc_seco_get_mp_sign(-1, SCU_SEC_SECURE_RAM_BASE, m_size,
+					  SCU_SEC_SECURE_RAM_BASE + 0x1000,
+					  FSL_CAAM_MP_SIGN_BYTES);
+
+		if (ret) {
+			printf("SECO get MP signature failed, return %d\n",
+			       ret);
+			ret = -EIO;
+			goto free_sign;
+		}
+
+		memcpy((void *)sign_ptr, (const void *)SEC_SECURE_RAM_BASE
+			+ 0x1000, ALIGN(FSL_CAAM_MP_SIGN_BYTES,
+			CONFIG_SYS_CACHELINE_SIZE));
+
+		/* Output results */
+		puts("\nMessage: ");
+		for (i = 0; i < m_size; i++)
+			printf("%02X", (m_ptr)[i]);
+		puts("\n");
+
+		puts("\nSignature:\n");
+		puts("c:\n");
+		for (i = 0; i < FSL_CAAM_MP_SIGN_BYTES / 2; i++)
+			printf("%02X", (sign_ptr)[i]);
+		puts("\n");
+
+		puts("d:\n");
+		for (i = FSL_CAAM_MP_SIGN_BYTES / 2; i < FSL_CAAM_MP_SIGN_BYTES;
+		     i++)
+			printf("%02X", (sign_ptr)[i]);
+		puts("\n");
+
+free_sign:
+	free(sign_ptr);
+free_m:
+	unmap_sysmem(m_ptr);
+
+	} else {
+		return CMD_RET_USAGE;
+	}
+	return ret;
+}
+#endif /* CONFIG_IMX_SECO_MFG_PROT */
 
 /***************************************************/
 static char mfgprot_help_text[] =
diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c
index f119e9f88d5..c241f418320 100644
--- a/arch/arm/mach-imx/cmd_nandbcb.c
+++ b/arch/arm/mach-imx/cmd_nandbcb.c
@@ -1521,7 +1521,7 @@ static int do_nandbcb(struct cmd_tbl *cmdtp, int flag, int argc,
 		plat_config = imx8mm_plat_config;
 	} else if (is_imx8mn() || is_imx8mp()) {
 		plat_config = imx8mn_plat_config;
-	} else if (is_imx8qm() || is_imx8qxp()) {
+    } else if (is_imx8qm() || is_imx8qxp() || is_imx8dxl()) {
 		plat_config = imx8q_plat_config;
 	} else {
 		printf("ERROR: Unknown platform\n");
@@ -1529,7 +1529,7 @@ static int do_nandbcb(struct cmd_tbl *cmdtp, int flag, int argc,
 	}
 
 	if ((plat_config.misc_flags) & BT_SEARCH_CNT_FROM_FUSE) {
-		if (is_imx8qxp())
+		if (is_imx8qxp() || is_imx8dxl())
 			g_boot_search_count = fuse_to_search_count(0, 720, 0xc0, 6);
 		if (is_imx8mn() || is_imx8mp())
 			g_boot_search_count = fuse_to_search_count(2, 2, 0x6000, 13);
diff --git a/arch/arm/mach-imx/cmd_prov_key.c b/arch/arm/mach-imx/cmd_prov_key.c
new file mode 100644
index 00000000000..b09e275d237
--- /dev/null
+++ b/arch/arm/mach-imx/cmd_prov_key.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * @file - cmd_prov_key.c
+ * @brief - NXP command support
+ * Command for provisioning encrypted key as black blob,
+ *
+ * Copyright 2021 NXP
+ *
+ */
+
+/*
+ *Concepts:
+ *
+ *  - black key: secure encrypted key that can only be used by the CAAM HW
+ *               module on the device generating this key.
+ *  - black blob: black blob is an encapsulation of black data (key) that can
+ *                only be decapsulated by the initiator device. The
+ *                decapsulation will result in a new black data readable only
+ *                by the CAAM HW.
+ *
+ *
+ *Generation of the key black blob:
+ *
+ *     1) Compile the bootloader with configuration:
+ *        CONFIG_IMX_HAB
+ *        CONFIG_FSL_CAAM
+ *        CONFIG_IMX_CAAM_MFG_PROT
+ *        CONFIG_CMD_PROVISION_KEY
+ *     2) Boot the bootloader on the board
+ *     3) Bootloader will generate the MPPubK
+ *     4) PKEK = hash(MPPUBK)
+ *     5) Read the encrypted key from RAM
+ *     6) Decrypt using PKEK
+ *     7) Encapsulate the decrypted key in black blob
+ *     8) Add the 20 bytes TAG to black blob
+ *     9) Copy the black blob in a binary file.
+ *        The file must have a size of 112 bytes (0x70 bytes).
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <command.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <asm/byteorder.h>
+#include <linux/compiler.h>
+#include <fsl_sec.h>
+#include <hash.h>
+#include <u-boot/sha256.h>
+#include <asm/arch/clock.h>
+
+/* Key modifier for CAAM blobs, used as a revision number */
+static const char caam_key_modifier[16] = {
+		'C', 'A', 'A', 'M', '_', 'K', 'E', 'Y',
+		'_', 'T', 'Y', 'P', 'E', '_', 'V', '1',
+};
+
+/**
+ * do_export_key_blob() - Handle the "export_key_blob" command-line command
+ * @cmdtp:	Command data struct pointer
+ * @flag:	Command flag
+ * @argc:	Command-line argument count
+ * @argv:	Array of command-line arguments
+ *
+ * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
+ * on error.
+ */
+static int do_export_key_blob(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	ulong src_addr, dst_addr;
+	uint8_t *src_ptr, *dst_ptr;
+	uint8_t *mppubk = NULL, *pkek = NULL, *black_key = NULL;
+	size_t key_len = AES256_KEY_SZ, pkek_len = SHA256_SUM_LEN;
+	size_t blob_len, blob_max_len;
+	int size, ret = 0;
+
+	ALLOC_CACHE_ALIGN_BUFFER(uint8_t, km_ptr, 16);
+
+	if (argc != 3)
+		return CMD_RET_USAGE;
+
+	/* generate mppubk */
+	mppubk = malloc_cache_aligned(FSL_CAAM_MP_PUBK_BYTES);
+	if (!mppubk) {
+		printf("Failed to allocate mem for mppubk\n");
+		return -ENOMEM;
+	}
+
+	ret = gen_mppubk(mppubk);
+	if (ret) {
+		printf("Failed to generate MPPubK\n");
+		goto free_m;
+	}
+
+	/* Derive PKEK = SHA256(MPPUBK) */
+	pkek = malloc_cache_aligned(pkek_len);
+	if (!pkek) {
+		printf("Failed to allocate memory for pkek\n");
+		ret = -ENOMEM;
+		goto free_m;
+	}
+
+	ret = hash_block("sha256", mppubk, FSL_CAAM_MP_PUBK_BYTES, pkek, (int *)&pkek_len);
+	if (ret)
+		goto free_pkek;
+
+	/* use pkek to decrypt src_addr which has enc key*/
+	src_addr = simple_strtoul(argv[1], NULL, 16);
+	src_ptr = (uint8_t *)(uintptr_t)src_addr;
+
+	black_key = malloc_cache_aligned(key_len);
+	if (!black_key) {
+		printf("Failed to allocate memory for black_key\n");
+		ret = -ENOMEM;
+		goto free_pkek;
+	}
+
+	ret = aesecb_decrypt(pkek, pkek_len, src_ptr, black_key, key_len);
+	if (ret)
+		goto free_blk_key;
+
+	/* create key black blob */
+	dst_addr = simple_strtoul(argv[2], NULL, 16);
+	dst_ptr = (uint8_t *)(uintptr_t)dst_addr;
+
+	/* copy key modifier, must be same as used in kernel */
+	memcpy(km_ptr, caam_key_modifier, 16);
+
+	ret = blob_encap((uint8_t *)km_ptr, black_key, dst_ptr, key_len, 1);
+	if (ret)
+		goto free_blk_key;
+
+	/* Tag the black blob so it can be passed to kernel */
+	blob_len = BLOB_SIZE(key_len) + CCM_OVERHEAD;
+	blob_max_len = MAX_BLOB_SIZE;
+	ret = tag_black_obj(dst_ptr, blob_len, key_len, blob_max_len);
+	if (ret)
+		printf("Failed to tag black blob: %d\n", ret);
+
+free_blk_key:
+	free(black_key);
+free_pkek:
+	memset(pkek, 0, pkek_len);
+	size = ALIGN(pkek_len, ARCH_DMA_MINALIGN);
+	flush_dcache_range((unsigned long)pkek, (unsigned long)pkek + size);
+	free(pkek);
+free_m:
+	memset(mppubk, 0, FSL_CAAM_MP_PUBK_BYTES);
+	size = ALIGN(FSL_CAAM_MP_PUBK_BYTES, ARCH_DMA_MINALIGN);
+	flush_dcache_range((unsigned long)mppubk, (unsigned long)mppubk + size);
+	free(mppubk);
+
+	return ret;
+}
+
+/***************************************************/
+
+U_BOOT_CMD(
+	export_key_blob, 3, 0, do_export_key_blob,
+	"Provision encrypted key as black blob.",
+	"src_addr dst_addr \n\n"
+	" - src_addr: source addr which has encrypted key(32 byte) to provision.\n"
+	"             must be 64 byte aligned.\n"
+	" - dst_addr: destination addr which will have key black blob(112 byte).\n"
+	"             must be 64 byte aligned.\n"
+);
diff --git a/arch/arm/mach-imx/cmd_qspihdr.c b/arch/arm/mach-imx/cmd_qspihdr.c
new file mode 100644
index 00000000000..6e2758664f8
--- /dev/null
+++ b/arch/arm/mach-imx/cmd_qspihdr.c
@@ -0,0 +1,610 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 NXP
+ */
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <mapmem.h>
+#include <asm/io.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <dm/device-internal.h>
+
+static struct spi_flash *flash;
+
+#define QSPI_HDR_TAG		0xc0ffee01 /* c0ffee01 */
+#define QSPI_HDR_TAG_OFF	0x1fc
+#define FSPI_HDR_TAG		0x42464346/* FCFB, bigendian */
+#define FSPI_HDR_TAG_OFF	0x0
+
+#define HDR_LEN			0x200
+
+#ifdef CONFIG_MX7
+#define QSPI_HDR_OFF	0x0
+#define QSPI_DATA_OFF	0x400
+#else
+#define QSPI_HDR_OFF	0x400
+#define QSPI_DATA_OFF	0x1000
+#endif
+
+#ifdef CONFIG_IMX8MM
+#define FSPI_HDR_OFF	0x0
+#define FSPI_DATA_OFF	0x1000
+#else
+#define FSPI_HDR_OFF	0x400
+#define FSPI_DATA_OFF	0x1000
+#endif
+
+#define FLAG_VERBOSE		1
+
+struct qspi_config_parameter {
+	u32 dqs_loopback;			/* Sets DQS LoopBack Mode to enable Dummy Pad MCR[24] */
+	u32 hold_delay;				/* No needed on ULT1 */
+	u32 hsphs;				/* Half Speed Phase Shift */
+	u32 hsdly;				/* Half Speed Delay Selection */
+	u32 device_quad_mode_en;		/* Write Command to Device */
+	u32 device_cmd;				/* Cmd to xfer to device */
+	u32 write_cmd_ipcr;			/* IPCR value of Write Cmd */
+	u32 write_enable_ipcr;			/* IPCR value of Write enable */
+	u32 cs_hold_time;			/* CS hold time in terms of serial clock.(for example 1 serial clock cyle) */
+	u32 cs_setup_time;			/* CS setup time in terms of serial clock.(for example 1 serial clock cyle) */
+	u32 sflash_A1_size;			/* interms of Bytes */
+	u32 sflash_A2_size;			/* interms of Bytes */
+	u32 sflash_B1_size;			/* interms of Bytes */
+	u32 sflash_B2_size;			/* interms of Bytes */
+	u32 sclk_freq;				/* 0 - 18MHz, 1 - 49MHz, 2 - 55MHz, 3 - 60MHz, 4 - 66Mhz, 5 - 76MHz, 6 - 99MHz (only for SDR Mode) */
+	u16 busy_bit_offset;			/* Flash device busy bit offset in status register */
+	u16 busy_bit_polarity;			/* Polarity of busy bit, 0 means the busy bit is 1 while busy and vice versa. */
+	u32 sflash_type;			/* 1 - Single, 2 - Dual, 4 - Quad */
+	u32 sflash_port;			/* 0 - Only Port-A, 1 - Both PortA and PortB */
+	u32 ddr_mode_enable;			/* Enable DDR mode if set to TRUE */
+	u32 dqs_enable;				/* Enable DQS mode if set to TRUE. Bit 0 represents DQS_EN, bit 1 represents DQS_LAT_EN */
+	u32 parallel_mode_enable;		/* Enable Individual or parrallel mode. */
+	u32 portA_cs1;				/* Enable Port A CS1 */
+	u32 portB_cs1;				/* Enable Port B CS1 */
+	u32 fsphs;				/* Full Speed Phase Selection */
+	u32 fsdly;				/* Full Speed Phase Selection */
+	u32 ddrsmp;				/* Select the sampling point for incoming data when serial flash is in DDR mode. */
+	u32 command_seq[64];			/* Set of seq to perform optimum read on SFLASH as as per vendor SFLASH */
+	u32 read_status_ipcr;			/* IPCR value of Read Status Reg */
+	u32 enable_dqs_phase;			/* Enable DQS phase */
+	u32 config_cmds_en;			/* Enable config commands */
+	u32 config_cmds[4];			/* config commands, used to configure nor flash */
+	u32 config_cmds_args[4];		/* config commands argu */
+	u32 dqs_pad_setting_override;		/* DQS pin pad setting override */
+	u32 sclk_pad_setting_override;		/* SCLK pin pad setting override */
+	u32 data_pad_setting_override;		/* DATA pins pad setting override */
+	u32 cs_pad_setting_override;		/* CS pins pad setting override */
+	u32 dqs_loopback_internal;		/* 0: dqs loopback from pad, 1: dqs loopback internally */
+	u32 dqs_phase_sel;			/* dqs phase sel */
+	u32 dqs_fa_delay_chain_sel;		/* dqs fa delay chain selection */
+	u32 dqs_fb_delay_chain_sel;		/* dqs fb delay chain selection */
+	u32 sclk_fa_delay_chain_sel;		/* sclk fa delay chain selection */
+	u32 sclk_fb_delay_chain_sel;		/* sclk fb delay chain selection */
+	u32 misc_clock_enable;			/* Misc clock enable, bit 0 means differential clock enable, bit 1 means CK2 clock enable. */
+	u32 reserve[15];			/* Reserved area, the total size of configuration structure should be 512 bytes */
+	u32 tag;				/* QSPI configuration TAG, should be 0xc0ffee01 */
+};
+
+struct fspi_config_parameter {
+	u32 tag;			/* tag, 0x46434642 ascii 'FCFB' */
+	u32 version;			/* 0x00000156 ascii bugfix | minor | major | 'V' */
+	u16 reserved;
+	u8  reserved0[2];
+	u8  readSampleClkSrc;		/* 0 - internal loopback, 1 - loopback from DQS pad, 2 - loopback from SCK pad, 3 - Flash provided DQS */
+	u8  dataHoldTime;		/* CS hold time */
+	u8  dataSetupTime;		/* CS setup time */
+	u8  columnAddressWidth;		/* 3 - for HyperFlash, 0 - other devices */
+	u8  deviceModeCfgEnable;	/* device mode configuration enable feature, 0 - disable, 1- enable */
+	u8  reserved1[3];
+	u32 deviceModeSeq;		/* sequence parameter for device mode configuration */
+	u32 deviceModeArg;		/* device mode argument, effective only when deviceModeCfgEnable = 1 */
+	u8  configCmdEnable;		/* config command enable feature, 0 - disable, 1 - enable */
+	u8  reserved2[3];
+	u32 configCmdSeqs[4];		/* sequences for config command, allow 4 separate configuration command sequences */
+	u32 configCmdArgs[4];		/* arguments for each separate configuration command sequence */
+	u32 controllerMiscOption;
+					/*
+					 *
+					 * +--------+----------------------------------------------------------+
+					 * | offset | description                                              |
+					 * +--------+----------------------------------------------------------+
+					 * |        | differential clock enable                                |
+					 * |   0    |                                                          |
+					 * |        | 0 - differential clock is not supported                  |
+					 * |        | 1 - differential clock is supported                      |
+					 * +--------+----------------------------------------------------------+
+					 * |        | CK2 enable                                               |
+					 * |   1    |                                                          |
+					 * |        | must set 0 for this silicon                              |
+					 * |        |                                                          |
+					 * +--------+----------------------------------------------------------+
+					 * |        | parallel mode enable                                     |
+					 * |   2    |                                                          |
+					 * |        | must set 0 for this silicon                              |
+					 * |        |                                                          |
+					 * +--------+----------------------------------------------------------+
+					 * |        | word addressable enable                                  |
+					 * |   3    |                                                          |
+					 * |        | 0 - device is not word addressable                       |
+					 * |        | 1 - device is word addressable                           |
+					 * +--------+----------------------------------------------------------+
+					 * |        | safe configuration frequency enable                      |
+					 * |   4    |                                                          |
+					 * |        | 0 - configure external device using specified frequency  |
+					 * |        | 1 - configure external device using 30MHz                |
+					 * +--------+----------------------------------------------------------+
+					 * |   5    | reserved                                                 |
+					 * +--------+----------------------------------------------------------+
+					 * |        | ddr mode enable                                          |
+					 * |   6    |                                                          |
+					 * |        | 0 - external device works using SDR commands             |
+					 * |        | 1 - external device works using DDR commands             |
+					 * +--------+----------------------------------------------------------+
+					 */
+	u8  deviceType;			/* 1 - serial NOR */
+	u8  sflashPadType;		/* 1 - single pad, 2 - dual pads, 4 - quad pads, 8 - octal pads */
+	u8  serialClkFreq;		/* 1 - 20MHz, 2 - 50MHz, 3 - 60MHz, 4 - 80MHz, 5 - 100MHz, 6 - 133MHz, 7 - 166MHz, other values - 20MHz*/
+	u8  lutCustomSeqEnable;		/* 0 - use pre-defined LUT sequence index and number, 1 - use LUT sequence parameters provided in this block */
+	u32 reserved3[2];
+	u32 sflashA1Size;		/* For SPI NOR, need to fill with actual size, in terms of bytes */
+	u32 sflashA2Size;		/* same as above */
+	u32 sflashB1Size;		/* same as above */
+	u32 sflashB2Size;		/* same as above */
+	u32 csPadSettingOverride;	/* set to 0 if it is not supported */
+	u32 sclkPadSettingOverride;	/* set to 0 if it is not supported */
+	u32 dataPadSettingOverride;	/* set to 0 if it is not supported */
+	u32 dqsPadSettingOverride;	/* set to 0 if it is not supported */
+	u32 timeoutInMs;		/* maximum wait time during dread busy status, not used in ROM */
+	u32 commandInterval;		/* interval of CS deselected period, set to 0 */
+	u16 dataValidTime[2];		/* time from clock edge to data valid edge */
+					/* This field is used when the FlexSPI root clock is less than 100MHz and the read sample */
+					/* clock source is device provided DQS signal without CK2 support. */
+					/* [31:16] - data valid time for DLLB in terms of 0.1ns */
+					/* [15:0]  - data valid time for DLLA in terms of 0.1ns */
+	u16 busyOffset;			/* busy bit offset, valid range: 0 - 31 */
+	u16 busyBitPolarity;		/* 0 - busy bit is 1 if device is busy, 1 - busy bit is 0 if device is busy */
+	u32 lookupTable[64];		/* lookup table */
+	u32 lutCustomSeq[12];		/* customized LUT sequence */
+	u32 reserved4[4];
+	u32 pageSize;			/* page size of serial NOR flash, not used in ROM */
+	u32 sectorSize;			/* sector size of serial NOR flash, not used in ROM */
+	u32 reserved5[14];
+};
+
+struct header_config {
+	union {
+		struct qspi_config_parameter qspi_hdr_config;
+		struct fspi_config_parameter fspi_hdr_config;
+	};
+};
+
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP)
+static struct qspi_config_parameter qspi_safe_config = {
+	.cs_hold_time		= 3,
+	.cs_setup_time		= 3,
+	.sflash_A1_size		= 0x4000000,
+	.sflash_B1_size		= 0x4000000,
+	.sflash_type		= 1,
+	.command_seq[0]		= 0x08180403,
+	.command_seq[1]		= 0x24001c00,
+	.tag			= 0xc0ffee01,
+};
+
+static struct header_config *safe_config = (struct header_config *)&qspi_safe_config;
+#else
+static struct fspi_config_parameter fspi_safe_config = {
+	.tag			= 0x42464346,
+	.version		= 0x56010000,
+	.dataHoldTime		= 0x3,
+	.dataSetupTime		= 0x3,
+	.deviceType		= 0x1,
+	.sflashPadType		= 0x1,
+	.serialClkFreq		= 0x2,
+	.sflashA1Size		= 0x10000000,
+	.lookupTable[0]		= 0x0818040b,
+	.lookupTable[1]		= 0x24043008,
+};
+
+static struct header_config *safe_config = (struct header_config *)&fspi_safe_config;
+#endif
+
+static int qspi_erase_update(struct spi_flash *flash, int off, int len, void *buf)
+{
+	int size;
+	int ret;
+
+	size = ROUND(len, flash->sector_size);
+	ret = spi_flash_erase(flash, off, size);
+	printf("Erase %#x bytes @ %#x %s\n",
+	       size, off, ret ? "ERROR" : "OK");
+	if (ret)
+		return ret;
+
+	ret = spi_flash_write(flash, off, len, buf);
+	printf("Write %#x bytes @ %#x %s\n",
+	       len, off, ret ? "ERROR" : "OK");
+
+	return ret;
+}
+
+static int do_qspihdr_check(int argc, char * const argv[], int flag)
+{
+	u32 buf;
+	unsigned long addr;
+	char *endp;
+	void *tmp;
+
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP)
+	int off = QSPI_HDR_OFF + QSPI_HDR_TAG_OFF;
+	int tag = QSPI_HDR_TAG;
+#else
+	int off = FSPI_HDR_OFF + FSPI_HDR_TAG_OFF;
+	int tag = FSPI_HDR_TAG;
+#endif
+
+	if (argc == 3) {
+		/* check data in memory */
+		addr = simple_strtoul(argv[2], &endp, 16);
+
+		tmp = map_physmem(addr + off, 4, MAP_WRBACK);
+		if (!tmp) {
+			printf("Failed to map physical memory\n");
+			return 1;
+		}
+
+		if (*(u32 *)tmp == tag) {
+			if (flag & FLAG_VERBOSE)
+				printf("Found boot config header in memory\n");
+			unmap_physmem(tmp, 4);
+			return 0;
+		} else {
+			if (flag & FLAG_VERBOSE)
+				printf("NO boot config header in memory\n");
+			unmap_physmem(tmp, 4);
+			return 1;
+		}
+	} else {
+		spi_flash_read(flash, off, 4, &buf);
+
+		if (buf == tag) {
+			if (flag & FLAG_VERBOSE)
+				printf("Found boot config header in Q(F)SPI\n");
+			return 0;
+		} else {
+			if (flag & FLAG_VERBOSE)
+				printf("NO boot config header in Q(F)SPI\n");
+			return 1;
+		}
+	}
+}
+
+static void hdr_dump(void *data)
+{
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP)
+	struct qspi_config_parameter *hdr =
+		(struct qspi_config_parameter *)data;
+#else
+	struct fspi_config_parameter *hdr =
+		(struct fspi_config_parameter *)data;
+#endif
+	int i;
+
+#define PH(mem, cnt) (						\
+{								\
+	if (cnt > 1) {						\
+		int len = strlen(#mem);				\
+		char *sub = strchr(#mem, '[');			\
+		if (sub)					\
+			*sub = '\0';				\
+		for (i = 0; i < cnt; ++i)			\
+			printf("  %s[%02d%-*s = %08x\n",	\
+			       #mem, i, 25 - len, "]",		\
+			       (u32)*(&hdr->mem + i));		\
+	} else {						\
+		printf("  %-25s = %0*x\n",			\
+		       #mem, (int)sizeof(hdr->mem), hdr->mem);	\
+		}						\
+}								\
+)
+
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP)
+	PH(dqs_loopback, 1);
+	PH(hold_delay, 1);
+	PH(hsphs, 1);
+	PH(hsdly, 1);
+	PH(device_quad_mode_en, 1);
+	PH(write_cmd_ipcr, 1);
+	PH(write_enable_ipcr, 1);
+	PH(cs_hold_time, 1);
+	PH(cs_setup_time, 1);
+	PH(sflash_A1_size, 1);
+	PH(sflash_A2_size, 1);
+	PH(sflash_B1_size, 1);
+	PH(sflash_B2_size, 1);
+	PH(sclk_freq, 1);
+	PH(busy_bit_offset, 1);
+	PH(busy_bit_polarity, 1);
+	PH(sflash_type, 1);
+	PH(sflash_port, 1);
+	PH(ddr_mode_enable, 1);
+	PH(dqs_enable, 1);
+	PH(parallel_mode_enable, 1);
+	PH(portA_cs1, 1);
+	PH(portB_cs1, 1);
+	PH(fsphs, 1);
+	PH(fsdly, 1);
+	PH(ddrsmp, 1);
+	PH(command_seq[0], 64);
+	PH(read_status_ipcr, 1);
+	PH(enable_dqs_phase, 1);
+	PH(config_cmds_en, 1);
+	PH(config_cmds[0], 4);
+	PH(config_cmds_args[0], 4);
+	PH(dqs_pad_setting_override, 1);
+	PH(sclk_pad_setting_override, 1);
+	PH(data_pad_setting_override, 1);
+	PH(cs_pad_setting_override, 1);
+	PH(dqs_loopback_internal, 1);
+	PH(dqs_phase_sel, 1);
+	PH(dqs_fa_delay_chain_sel, 1);
+	PH(dqs_fb_delay_chain_sel, 1);
+	PH(sclk_fa_delay_chain_sel, 1);
+	PH(sclk_fb_delay_chain_sel, 1);
+	PH(misc_clock_enable, 1);
+	PH(tag, 1);
+#else
+	PH(tag, 1);
+	PH(version, 1);
+	PH(readSampleClkSrc, 1);
+	PH(dataHoldTime, 1);
+	PH(dataSetupTime, 1);
+	PH(columnAddressWidth, 1);
+	PH(deviceModeCfgEnable, 1);
+	PH(deviceModeSeq, 1);
+	PH(deviceModeArg, 1);
+	PH(configCmdEnable, 1);
+	PH(configCmdSeqs[0], 4);
+	PH(configCmdArgs[0], 4);
+	PH(controllerMiscOption, 1);
+	PH(deviceType, 1);
+	PH(sflashPadType, 1);
+	PH(serialClkFreq, 1);
+	PH(lutCustomSeqEnable, 1);
+	PH(sflashA1Size, 1);
+	PH(sflashA2Size, 1);
+	PH(sflashB1Size, 1);
+	PH(sflashB2Size, 1);
+	PH(csPadSettingOverride, 1);
+	PH(sclkPadSettingOverride, 1);
+	PH(dataPadSettingOverride, 1);
+	PH(dqsPadSettingOverride, 1);
+	PH(timeoutInMs, 1);
+	PH(commandInterval, 1);
+	PH(dataValidTime[0], 2);
+	PH(busyOffset, 1);
+	PH(busyBitPolarity, 1);
+	PH(lookupTable[0], 64);
+	PH(lutCustomSeq[0], 12);
+	PH(pageSize, 1);
+	PH(sectorSize, 1);
+#endif
+}
+
+static int do_qspihdr_dump(int argc, char * const argv[])
+{
+	unsigned long addr;
+	char *endp;
+	void *tmp;
+	void *buf;
+
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP)
+	int off = QSPI_HDR_OFF;
+#else
+	int off = FSPI_HDR_OFF;
+#endif
+
+	if (argc == 3) {
+		/* check data in memory */
+		if (do_qspihdr_check(3, argv, FLAG_VERBOSE)) {
+			/* return 0 in any cases */
+			return 0;
+		}
+
+		addr = simple_strtoul(argv[2], &endp, 16);
+
+		tmp = map_physmem(addr + off, HDR_LEN, MAP_WRBACK);
+		if (!tmp) {
+			printf("Failed to map physical memory\n");
+			return 1;
+		}
+
+		hdr_dump(tmp);
+		unmap_physmem(tmp, HDR_LEN);
+	} else {
+		/* check data in Q(F)SPI */
+		buf = malloc(HDR_LEN);
+		if (!buf) {
+			printf("Failed to alloc memory\n");
+			/* return 0 in any cases */
+			return 0;
+		}
+
+		spi_flash_read(flash, off, HDR_LEN, buf);
+
+		hdr_dump(buf);
+		free(buf);
+	}
+
+	return 0;
+}
+
+static int do_qspihdr_init(int argc, char * const argv[])
+{
+	unsigned long addr, len;
+	char *endp;
+	int total_len;
+	void *tmp;
+	void *buf;
+	bool hdr_flag = false;
+	int ret;
+
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP)
+	int hdr_off = QSPI_HDR_OFF;
+	int data_off = QSPI_DATA_OFF;
+#else
+	int hdr_off = FSPI_HDR_OFF;
+	int data_off = FSPI_DATA_OFF;
+
+	safe_config->fspi_hdr_config.pageSize = flash->page_size;
+	safe_config->fspi_hdr_config.sectorSize = flash->sector_size;
+#endif
+
+	addr = simple_strtoul(argv[2], &endp, 16);
+	len = simple_strtoul(argv[3], &endp, 16);
+
+	total_len = data_off + len;
+	if (total_len > flash->size) {
+		printf("Error: length %lx over flash size (%#x)\n",
+		       len, flash->size);
+		return 1;
+	}
+
+	/* check if header exists in this memory area*/
+	if (do_qspihdr_check(3, argv, 0) == 0)
+		hdr_flag = true;
+
+	tmp = map_physmem(addr, len, MAP_WRBACK);
+	if (!tmp) {
+		printf("Failed to map physical memory\n");
+		return 1;
+	}
+
+	if (hdr_flag)
+		goto burn_image;
+
+	buf = malloc(total_len);
+	if (!buf) {
+		printf("Failed to alloc memory\n");
+		unmap_physmem(tmp, total_len);
+		return 1;
+	}
+
+	memset(buf, 0xff, total_len);
+	memcpy(buf + hdr_off, safe_config, HDR_LEN);
+	memcpy(buf + data_off, tmp, len);
+
+burn_image:
+	if (hdr_flag) {
+		ret = qspi_erase_update(flash, 0, len, tmp);
+	} else {
+		ret = qspi_erase_update(flash, 0, total_len, buf);
+		free(buf);
+	}
+
+	unmap_physmem(tmp, total_len);
+	return ret;
+}
+
+static int do_qspihdr_update(int argc, char * const argv[])
+{
+	int len;
+	int size;
+	void *buf;
+	int ret;
+
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP)
+	int hdr_off = QSPI_HDR_OFF;
+#else
+	int hdr_off = FSPI_HDR_OFF;
+#endif
+
+	len = hdr_off + HDR_LEN;
+	size = ROUND(len, flash->sector_size);
+
+	buf = malloc(size);
+	if (!buf) {
+		printf("Failed to alloc memory\n");
+		return 1;
+	}
+
+	spi_flash_read(flash, 0, size, buf);
+	memcpy(buf + hdr_off, safe_config, HDR_LEN);
+
+	ret = qspi_erase_update(flash, 0, size, buf);
+	free(buf);
+
+	return ret;
+}
+
+static int do_qspihdr(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+	char *cmd;
+	unsigned int bus = CONFIG_SF_DEFAULT_BUS;
+	unsigned int cs = CONFIG_SF_DEFAULT_CS;
+	unsigned int speed = CONFIG_SF_DEFAULT_SPEED;
+	unsigned int mode = CONFIG_SF_DEFAULT_MODE;
+	int flags = 0;
+	int ret;
+
+	if (argc < 2)
+		goto usage;
+
+#ifdef CONFIG_DM_SPI_FLASH
+	struct udevice *new, *bus_dev;
+
+	ret = spi_find_bus_and_cs(bus, cs, &bus_dev, &new);
+	if (!ret)
+		device_remove(new, DM_REMOVE_NORMAL);
+	flash = NULL;
+	ret = spi_flash_probe_bus_cs(bus, cs, speed, mode, &new);
+	if (ret) {
+		printf("Failed to initialize SPI flash at %u:%u (error %d)\n",
+		       bus, cs, ret);
+		return 1;
+	}
+	flash = dev_get_uclass_priv(new);
+#endif
+
+	cmd = argv[1];
+
+	if (strcmp(cmd, "check") == 0)
+		return do_qspihdr_check(argc, argv, flags | FLAG_VERBOSE);
+
+	if (strcmp(cmd, "dump") == 0)
+		return do_qspihdr_dump(argc, argv);
+
+	if (strcmp(cmd, "init") == 0) {
+		if (argc < 5)
+			goto usage;
+		return do_qspihdr_init(argc, argv);
+	}
+
+	if (strcmp(cmd, "update") == 0) {
+		if (argc < 3)
+			goto usage;
+		return do_qspihdr_update(argc, argv);
+	}
+
+	return 0;
+usage:
+	return CMD_RET_USAGE;
+}
+
+static char qspihdr_help_text[] =
+	"check [addr] - check if boot config already exists, 0-yes, 1-no\n"
+	"		with addr, it will check data in memory of this addr\n"
+	"		without addr, it will check data in Q(F)SPI chip\n"
+	"qspihdr dump [addr] - dump the header information, if exists\n"
+	"		with addr, it will check data in memory of this addr\n"
+	"		without addr, it will check data in Q(F)SPI chip\n"
+	"qspihdr init addr len safe - burn data to Q(F)SPI with header\n"
+	"		if data contains header, it will be used, otherwise,\n"
+	"		safe: most common header, single line, sdr, low freq\n"
+	"qspihdr update safe - only update the header in Q(F)SPI\n";
+
+U_BOOT_CMD(qspihdr, 5, 1, do_qspihdr,
+	"Q(F)SPI Boot Config sub-system",
+	qspihdr_help_text
+);
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 8eb05c8dd67..fce63eb1928 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -27,6 +27,10 @@
 #include <dm/device-internal.h>
 #include <dm/uclass-internal.h>
 
+#ifdef CONFIG_VIDEO_GIS
+#include <gis.h>
+#endif
+
 #ifdef CONFIG_FSL_ESDHC_IMX
 #include <fsl_esdhc_imx.h>
 #endif
@@ -40,7 +44,10 @@ u32 get_imx_reset_cause(void)
 	if (reset_cause == -1) {
 		reset_cause = readl(&src_regs->srsr);
 /* preserve the value for U-Boot proper */
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ANDROID_BOOT_IMAGE)
+		/* We will read the ssrs states later for android so we don't
+		 * clear the states here.
+		 */
 		writel(reset_cause, &src_regs->srsr);
 #endif
 	}
@@ -91,6 +98,17 @@ static char *get_reset_cause(void)
 		return "unknown reset";
 	}
 }
+
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+void get_reboot_reason(char *ret)
+{
+	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+	strcpy(ret, (const char *)get_reset_cause());
+	/* clear the srsr here, its state has been recorded in reset_cause */
+	writel(reset_cause, &src_regs->srsr);
+}
+#endif
 #endif
 
 #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
@@ -106,6 +124,8 @@ const char *get_imx_type(u32 imxtype)
 		return "8MP Lite[4]";	/* Quad-core Lite version of the imx8mp */
 	case MXC_CPU_IMX8MP6:
 		return "8MP[6]";	/* Quad-core version of the imx8mp, NPU fused */
+	case MXC_CPU_IMX8MPUL:
+		return "8MP UltraLite";	/* Quad-core UltraLite version of the imx8mp */
 	case MXC_CPU_IMX8MN:
 		return "8MNano Quad"; /* Quad-core version */
 	case MXC_CPU_IMX8MND:
@@ -183,6 +203,10 @@ int print_cpuinfo(void)
 {
 	u32 cpurev;
 	__maybe_unused u32 max_freq;
+#if defined(CONFIG_DBG_MONITOR)
+	struct dbg_monitor_regs *dbg =
+		(struct dbg_monitor_regs *)DEBUG_MONITOR_BASE_ADDR;
+#endif
 
 	cpurev = get_cpu_rev();
 
@@ -190,7 +214,7 @@ int print_cpuinfo(void)
 	struct udevice *thermal_dev;
 	int cpu_tmp, minc, maxc, ret;
 
-	printf("CPU:   Freescale i.MX%s rev%d.%d",
+	printf("CPU:   i.MX%s rev%d.%d",
 	       get_imx_type((cpurev & 0x1FF000) >> 12),
 	       (cpurev & 0x000F0) >> 4,
 	       (cpurev & 0x0000F) >> 0);
@@ -202,7 +226,7 @@ int print_cpuinfo(void)
 		       mxc_get_clock(MXC_ARM_CLK) / 1000000);
 	}
 #else
-	printf("CPU:   Freescale i.MX%s rev%d.%d at %d MHz\n",
+	printf("CPU:   i.MX%s rev%d.%d at %d MHz\n",
 		get_imx_type((cpurev & 0x1FF000) >> 12),
 		(cpurev & 0x000F0) >> 4,
 		(cpurev & 0x0000F) >> 0,
@@ -240,6 +264,14 @@ int print_cpuinfo(void)
 	puts("\n");
 #endif
 
+#if defined(CONFIG_DBG_MONITOR)
+	if (readl(&dbg->snvs_addr))
+		printf("DBG snvs regs addr 0x%x, data 0x%x, info 0x%x\n",
+		       readl(&dbg->snvs_addr),
+		       readl(&dbg->snvs_data),
+		       readl(&dbg->snvs_info));
+#endif
+
 	printf("Reset cause: %s\n", get_reset_cause());
 	return 0;
 }
@@ -304,10 +336,17 @@ void arch_preboot_os(void)
 #endif
 	}
 #endif
+#if defined(CONFIG_LDO_BYPASS_CHECK)
+	ldo_mode_set(check_ldo_bypass());
+#endif
 #if defined(CONFIG_VIDEO_IPUV3)
 	/* disable video before launching O/S */
 	ipuv3_fb_shutdown();
 #endif
+#ifdef CONFIG_VIDEO_GIS
+	/* Entry for GIS */
+	mxc_disable_gis();
+#endif
 #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
 	lcdif_power_down();
 #endif
diff --git a/arch/arm/mach-imx/dt_optee.c b/arch/arm/mach-imx/dt_optee.c
new file mode 100644
index 00000000000..45794944373
--- /dev/null
+++ b/arch/arm/mach-imx/dt_optee.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/optee.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <fdtdec.h>
+
+
+#ifdef CONFIG_OF_SYSTEM_SETUP
+int ft_add_optee_node(void *fdt, struct bd_info *bd)
+{
+	const char *path, *subpath;
+	int ret = 0;
+	int offs;
+	phys_addr_t optee_start;
+	size_t optee_size;
+
+	/* Not let uboot create the node */
+	if (CONFIG_IS_ENABLED(XEN))
+		return 0;
+	/*
+	 * No TEE space allocated indicating no TEE running, so no
+	 * need to add optee node in dts
+	 */
+	if (!rom_pointer[1])
+		return 0;
+
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+	if (rom_pointer[2]) {
+		debug("OP-TEE: applying overlay on 0x%lx\n",rom_pointer[2]);
+		ret = fdt_check_header((void*)rom_pointer[2]);
+		if (ret == 0) {
+			/* Copy the fdt overlay to next 1M and use copied overlay */
+			memcpy((void *)(rom_pointer[2] + SZ_1M), (void *)rom_pointer[2],
+				fdt_totalsize((void*)rom_pointer[2]));
+			ret = fdt_overlay_apply_verbose(fdt, (void*)(rom_pointer[2] + SZ_1M));
+			if (ret == 0) {
+				debug("Overlay applied with success");
+				fdt_pack(fdt);
+				return 0;
+			}
+		}
+	}
+	/* Fallback to previous implementation */
+#endif
+
+	optee_start = (phys_addr_t)rom_pointer[0];
+	optee_size = rom_pointer[1] - OPTEE_SHM_SIZE;
+
+	offs = fdt_increase_size(fdt, 512);
+	if (offs) {
+		printf("No Space for dtb\n");
+		return -1;
+	}
+
+	path = "/firmware";
+	offs = fdt_path_offset(fdt, path);
+	if (offs < 0) {
+		offs = add_dt_path_subnode(fdt, "/", "firmware");
+		if (offs < 0)
+			return -1;
+	}
+
+	if (fdt_path_offset(fdt, "/firmware/optee") < 0) {
+		subpath = "optee";
+		offs = fdt_add_subnode(fdt, offs, subpath);
+		if (offs < 0) {
+			printf("Could not create %s node.\n", subpath);
+			return -1;
+		}
+
+		fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz");
+		fdt_setprop_string(fdt, offs, "method", "smc");
+	}
+
+	unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
+	struct fdt_memory carveout = {
+		.start = optee_start,
+		.end = optee_start + optee_size - 1,
+	};
+
+	ret = fdtdec_add_reserved_memory(fdt, "optee_core", &carveout,
+		NULL, 0, NULL, flags);
+	if (ret < 0) {
+		printf("Could not create optee_core node.\n");
+		return -1;
+	}
+
+	carveout.start = optee_start + optee_size;
+	carveout.end = optee_start + optee_size + OPTEE_SHM_SIZE - 1;
+
+	ret = fdtdec_add_reserved_memory(fdt, "optee_shm", &carveout,
+		NULL, 0, NULL, flags);
+	if (ret < 0) {
+		printf("Could not create optee_shm node.\n");
+		return -1;
+	}
+
+	return ret;
+}
+#endif
diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c
new file mode 100644
index 00000000000..66732c5faea
--- /dev/null
+++ b/arch/arm/mach-imx/ele_ahab.c
@@ -0,0 +1,583 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/sys_proto.h>
+#include <asm/arch-imx/cpu.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/image.h>
+#include <console.h>
+#include <cpu_func.h>
+#include <asm/mach-imx/ahab.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMG_CONTAINER_END_BASE         (IMG_CONTAINER_BASE + 0xFFFFUL)
+
+#define AHAB_MAX_EVENTS 8
+
+static char *ele_ipc_str[] = {
+	"IPC = MU RTD (0x1)\n",
+	"IPC = MU APD (0x2)\n",
+	"IPC = INVALID\n",
+	NULL
+};
+
+static char *ele_status_str[] = {
+	"STA = ELE_SUCCESS_IND (0xD6)\n",
+	"STA = ELE_FAILURE_IND (0x29)\n",
+	"STA = INVALID\n",
+	NULL
+};
+
+static char *ele_cmd_str[] = {
+	"CMD = ELE_PING_REQ (0x01)\n",
+	"CMD = ELE_FW_AUTH_REQ (0x02)\n",
+	"CMD = ELE_RESTART_RST_TIMER_REQ (0x04)\n",
+	"CMD = ELE_DUMP_DEBUG_BUFFER_REQ (0x21)\n",
+	"CMD = ELE_OEM_CNTN_AUTH_REQ (0x87)\n",
+	"CMD = ELE_VERIFY_IMAGE_REQ (0x88)\n",
+	"CMD = ELE_RELEASE_CONTAINER_REQ (0x89)\n",
+	"CMD = ELE_WRITE_SECURE_FUSE_REQ (0x91)\n",
+	"CMD = ELE_FWD_LIFECYCLE_UP_REQ (0x95)\n",
+	"CMD = ELE_READ_FUSE_REQ (0x97)\n",
+	"CMD = ELE_GET_FW_VERSION_REQ (0x9D)\n",
+	"CMD = ELE_RET_LIFECYCLE_UP_REQ (0xA0)\n",
+	"CMD = ELE_GET_EVENTS_REQ (0xA2)\n",
+	"CMD = ELE_ENABLE_PATCH_REQ (0xC3)\n",
+	"CMD = ELE_RELEASE_RDC_REQ (0xC4)\n",
+	"CMD = ELE_GET_FW_STATUS_REQ (0xC5)\n",
+	"CMD = ELE_ENABLE_OTFAD_REQ (0xC6)\n",
+	"CMD = ELE_RESET_REQ (0xC7)\n",
+	"CMD = ELE_UPDATE_OTP_CLKDIV_REQ (0xD0)\n",
+	"CMD = ELE_POWER_DOWN_REQ (0xD1)\n",
+	"CMD = ELE_ENABLE_APC_REQ (0xD2)\n",
+	"CMD = ELE_ENABLE_RTC_REQ (0xD3)\n",
+	"CMD = ELE_DEEP_POWER_DOWN_REQ (0xD4)\n",
+	"CMD = ELE_STOP_RST_TIMER_REQ (0xD5)\n",
+	"CMD = ELE_WRITE_FUSE_REQ (0xD6)\n",
+	"CMD = ELE_RELEASE_CAAM_REQ (0xD7)\n",
+	"CMD = ELE_RESET_A35_CTX_REQ (0xD8)\n",
+	"CMD = ELE_MOVE_TO_UNSECURED_REQ (0xD9)\n",
+	"CMD = ELE_GET_INFO_REQ (0xDA)\n",
+	"CMD = ELE_ATTEST_REQ (0xDB)\n",
+	"CMD = ELE_RELEASE_PATCH_REQ (0xDC)\n",
+	"CMD = ELE_OTP_SEQ_SWITH_REQ (0xDD)\n",
+	"CMD = INVALID\n",
+	NULL
+};
+
+static char *ele_ind_str[] = {
+	"IND = ELE_ROM_PING_FAILURE_IND (0x0A)\n",
+	"IND = ELE_FW_PING_FAILURE_IND (0x1A)\n",
+	"IND = ELE_BAD_SIGNATURE_FAILURE_IND (0xF0)\n",
+	"IND = ELE_BAD_HASH_FAILURE_IND (0xF1)\n",
+	"IND = ELE_INVALID_LIFECYCLE_IND (0xF2)\n",
+	"IND = ELE_PERMISSION_DENIED_FAILURE_IND (0xF3)\n",
+	"IND = ELE_INVALID_MESSAGE_FAILURE_IND (0xF4)\n",
+	"IND = ELE_BAD_VALUE_FAILURE_IND (0xF5)\n",
+	"IND = ELE_BAD_FUSE_ID_FAILURE_IND (0xF6)\n",
+	"IND = ELE_BAD_CONTAINER_FAILURE_IND (0xF7)\n",
+	"IND = ELE_BAD_VERSION_FAILURE_IND (0xF8)\n",
+	"IND = ELE_INVALID_KEY_FAILURE_IND (0xF9)\n",
+	"IND = ELE_BAD_KEY_HASH_FAILURE_IND (0xFA)\n",
+	"IND = ELE_NO_VALID_CONTAINER_FAILURE_IND (0xFB)\n",
+	"IND = ELE_BAD_CERTIFICATE_FAILURE_IND (0xFC)\n",
+	"IND = ELE_BAD_UID_FAILURE_IND (0xFD)\n",
+	"IND = ELE_BAD_MONOTONIC_COUNTER_FAILURE_IND (0xFE)\n",
+	"IND = ELE_MUST_SIGNED_FAILURE_IND (0xE0)\n",
+	"IND = ELE_NO_AUTHENTICATION_FAILURE_IND (0xEE)\n",
+	"IND = ELE_BAD_SRK_SET_FAILURE_IND (0xEF)\n",
+	"IND = ELE_UNALIGNED_PAYLOAD_FAILURE_IND (0xA6)\n",
+	"IND = ELE_WRONG_SIZE_FAILURE_IND (0xA7)\n",
+	"IND = ELE_ENCRYPTION_FAILURE_IND (0xA8)\n",
+	"IND = ELE_DECRYPTION_FAILURE_IND (0xA9)\n",
+	"IND = ELE_OTP_PROGFAIL_FAILURE_IND (0xAA)\n",
+	"IND = ELE_OTP_LOCKED_FAILURE_IND (0xAB)\n",
+	"IND = ELE_OTP_INVALID_IDX_FAILURE_IND (0xAD)\n",
+	"IND = ELE_TIME_OUT_FAILURE_IND (0xB0)\n",
+	"IND = ELE_BAD_PAYLOAD_FAILURE_IND (0xB1)\n",
+	"IND = ELE_WRONG_ADDRESS_FAILURE_IND (0xB4)\n",
+	"IND = ELE_DMA_FAILURE_IND (0xB5)\n",
+	"IND = ELE_DISABLED_FEATURE_FAILURE_IND (0xB6)\n",
+	"IND = ELE_MUST_ATTEST_FAILURE_IND (0xB7)\n",
+	"IND = ELE_RNG_NOT_STARTED_FAILURE_IND (0xB8)\n",
+	"IND = ELE_CRC_ERROR_IND (0xB9)\n",
+	"IND = ELE_AUTH_SKIPPED_OR_FAILED_FAILURE_IND (0xBB)\n",
+	"IND = ELE_INCONSISTENT_PAR_FAILURE_IND (0xBC)\n",
+	"IND = ELE_RNG_INST_FAILURE_FAILURE_IND (0xBD)\n",
+	"IND = ELE_LOCKED_REG_FAILURE_IND (0xBE)\n",
+	"IND = ELE_BAD_ID_FAILURE_IND (0xBF)\n",
+	"IND = ELE_INVALID_OPERATION_FAILURE_IND (0xC0)\n",
+	"IND = ELE_NON_SECURE_STATE_FAILURE_IND (0xC1)\n",
+	"IND = ELE_MSG_TRUNCATED_IND (0xC2)\n",
+	"IND = ELE_BAD_IMAGE_NUM_FAILURE_IND (0xC3)\n",
+	"IND = ELE_BAD_IMAGE_ADDR_FAILURE_IND (0xC4)\n",
+	"IND = ELE_BAD_IMAGE_PARAM_FAILURE_IND (0xC5)\n",
+	"IND = ELE_BAD_IMAGE_TYPE_FAILURE_IND (0xC6)\n",
+	"IND = ELE_CORRUPTED_SRK_FAILURE_IND (0xD0)\n",
+	"IND = ELE_OUT_OF_MEMORY_IND (0xD1)\n",
+	"IND = ELE_CSTM_FAILURE_IND (0xCF)\n",
+	"IND = ELE_OLD_VERSION_FAILURE_IND (0xCE)\n",
+	"IND = ELE_WRONG_BOOT_MODE_FAILURE_IND (0xCD)\n",
+	"IND = ELE_APC_ALREADY_ENABLED_FAILURE_IND (0xCB)\n",
+	"IND = ELE_RTC_ALREADY_ENABLED_FAILURE_IND (0xCC)\n",
+	"IND = ELE_ABORT_IND (0xFF)\n",
+	"IND = INVALID\n",
+	NULL
+};
+
+static u8 ele_cmd[] = {
+	ELE_PING_REQ,
+	ELE_FW_AUTH_REQ,
+	ELE_RESTART_RST_TIMER_REQ,
+	ELE_DUMP_DEBUG_BUFFER_REQ,
+	ELE_OEM_CNTN_AUTH_REQ,
+	ELE_VERIFY_IMAGE_REQ,
+	ELE_RELEASE_CONTAINER_REQ,
+	ELE_WRITE_SECURE_FUSE_REQ,
+	ELE_FWD_LIFECYCLE_UP_REQ,
+	ELE_READ_FUSE_REQ,
+	ELE_GET_FW_VERSION_REQ,
+	ELE_RET_LIFECYCLE_UP_REQ,
+	ELE_GET_EVENTS_REQ,
+	ELE_ENABLE_PATCH_REQ,
+	ELE_RELEASE_RDC_REQ,
+	ELE_GET_FW_STATUS_REQ,
+	ELE_ENABLE_OTFAD_REQ,
+	ELE_RESET_REQ,
+	ELE_UPDATE_OTP_CLKDIV_REQ,
+	ELE_POWER_DOWN_REQ,
+	ELE_ENABLE_APC_REQ,
+	ELE_ENABLE_RTC_REQ,
+	ELE_DEEP_POWER_DOWN_REQ,
+	ELE_STOP_RST_TIMER_REQ,
+	ELE_WRITE_FUSE_REQ,
+	ELE_RELEASE_CAAM_REQ,
+	ELE_RESET_A35_CTX_REQ,
+	ELE_MOVE_TO_UNSECURED_REQ,
+	ELE_GET_INFO_REQ,
+	ELE_ATTEST_REQ,
+	ELE_RELEASE_PATCH_REQ,
+	ELE_OTP_SEQ_SWITH_REQ
+};
+
+static u8 ele_ind[] = {
+	ELE_ROM_PING_FAILURE_IND,
+	ELE_FW_PING_FAILURE_IND,
+	ELE_BAD_SIGNATURE_FAILURE_IND,
+	ELE_BAD_HASH_FAILURE_IND,
+	ELE_INVALID_LIFECYCLE_IND,
+	ELE_PERMISSION_DENIED_FAILURE_IND,
+	ELE_INVALID_MESSAGE_FAILURE_IND,
+	ELE_BAD_VALUE_FAILURE_IND,
+	ELE_BAD_FUSE_ID_FAILURE_IND,
+	ELE_BAD_CONTAINER_FAILURE_IND,
+	ELE_BAD_VERSION_FAILURE_IND,
+	ELE_INVALID_KEY_FAILURE_IND,
+	ELE_BAD_KEY_HASH_FAILURE_IND,
+	ELE_NO_VALID_CONTAINER_FAILURE_IND,
+	ELE_BAD_CERTIFICATE_FAILURE_IND,
+	ELE_BAD_UID_FAILURE_IND,
+	ELE_BAD_MONOTONIC_COUNTER_FAILURE_IND,
+	ELE_MUST_SIGNED_FAILURE_IND,
+	ELE_NO_AUTHENTICATION_FAILURE_IND,
+	ELE_BAD_SRK_SET_FAILURE_IND,
+	ELE_UNALIGNED_PAYLOAD_FAILURE_IND,
+	ELE_WRONG_SIZE_FAILURE_IND,
+	ELE_ENCRYPTION_FAILURE_IND,
+	ELE_DECRYPTION_FAILURE_IND,
+	ELE_OTP_PROGFAIL_FAILURE_IND,
+	ELE_OTP_LOCKED_FAILURE_IND,
+	ELE_OTP_INVALID_IDX_FAILURE_IND,
+	ELE_TIME_OUT_FAILURE_IND,
+	ELE_BAD_PAYLOAD_FAILURE_IND,
+	ELE_WRONG_ADDRESS_FAILURE_IND,
+	ELE_DMA_FAILURE_IND,
+	ELE_DISABLED_FEATURE_FAILURE_IND,
+	ELE_MUST_ATTEST_FAILURE_IND,
+	ELE_RNG_NOT_STARTED_FAILURE_IND,
+	ELE_CRC_ERROR_IND,
+	ELE_AUTH_SKIPPED_OR_FAILED_FAILURE_IND,
+	ELE_INCONSISTENT_PAR_FAILURE_IND,
+	ELE_RNG_INST_FAILURE_FAILURE_IND,
+	ELE_LOCKED_REG_FAILURE_IND,
+	ELE_BAD_ID_FAILURE_IND,
+	ELE_INVALID_OPERATION_FAILURE_IND,
+	ELE_NON_SECURE_STATE_FAILURE_IND,
+	ELE_MSG_TRUNCATED_IND,
+	ELE_BAD_IMAGE_NUM_FAILURE_IND,
+	ELE_BAD_IMAGE_ADDR_FAILURE_IND,
+	ELE_BAD_IMAGE_PARAM_FAILURE_IND,
+	ELE_BAD_IMAGE_TYPE_FAILURE_IND,
+	ELE_CORRUPTED_SRK_FAILURE_IND,
+	ELE_OUT_OF_MEMORY_IND,
+	ELE_CSTM_FAILURE_IND,
+	ELE_OLD_VERSION_FAILURE_IND,
+	ELE_WRONG_BOOT_MODE_FAILURE_IND,
+	ELE_APC_ALREADY_ENABLED_FAILURE_IND,
+	ELE_RTC_ALREADY_ENABLED_FAILURE_IND,
+	ELE_ABORT_IND
+};
+
+static u8 ele_ipc[] = {
+	ELE_IPC_MU_RTD,
+	ELE_IPC_MU_APD
+};
+
+static u8 ele_status[] = {
+	ELE_SUCCESS_IND,
+	ELE_FAILURE_IND
+};
+
+static inline u32 get_idx(u8 *list, u8 tgt, u32 size)
+{
+	u32 i;
+
+	for (i = 0; i < size; i++) {
+		if (list[i] == tgt)
+			return i;
+	}
+
+	return i; /* last str is invalid */
+}
+
+static void display_ahab_auth_ind(u32 event)
+{
+	u8 resp_ind = (event >> 8) & 0xff;
+
+	printf("%s\n", ele_ind_str[get_idx(ele_ind, resp_ind, ARRAY_SIZE(ele_ind))]);
+}
+
+int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
+{
+	int err;
+	u32 resp;
+	memcpy((void *)IMG_CONTAINER_BASE, (const void *)container,
+	       ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
+
+	flush_dcache_range(IMG_CONTAINER_BASE,
+		IMG_CONTAINER_BASE + ALIGN(length, CONFIG_SYS_CACHELINE_SIZE) - 1);
+
+	err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE,
+				   &resp);
+	if (err) {
+		printf("Authenticate container hdr failed, return %d, resp 0x%x\n",
+		       err, resp);
+		display_ahab_auth_ind(resp);
+	}
+
+	return err;
+}
+
+int ahab_auth_release(void)
+{
+	int err;
+	u32 resp;
+
+	err = ahab_release_container(&resp);
+	if (err) {
+		printf("Error: release container failed, resp 0x%x!\n", resp);
+		display_ahab_auth_ind(resp);
+	}
+
+	return err;
+}
+
+int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
+{
+	int err;
+	u32 resp;
+
+	err = ahab_verify_image(image_index, &resp);
+	if (err) {
+		printf("Authenticate img %d failed, return %d, resp 0x%x\n",
+		       image_index, err, resp);
+		display_ahab_auth_ind(resp);
+
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static inline bool check_in_dram(ulong addr)
+{
+	int i;
+	struct bd_info *bd = gd->bd;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+		if (bd->bi_dram[i].size) {
+			if (addr >= bd->bi_dram[i].start &&
+			    addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))
+				return true;
+		}
+	}
+
+	return false;
+}
+
+int authenticate_os_container(ulong addr)
+{
+	struct container_hdr *phdr;
+	int i, ret = 0;
+	int err;
+	u16 length;
+	struct boot_img_t *img;
+	unsigned long s, e;
+
+	if (addr % 4) {
+		puts("Error: Image's address is not 4 byte aligned\n");
+		return -EINVAL;
+	}
+
+	if (!check_in_dram(addr)) {
+		puts("Error: Image's address is invalid\n");
+		return -EINVAL;
+	}
+
+	phdr = (struct container_hdr *)addr;
+	if (phdr->tag != 0x87 || phdr->version != 0x0) {
+		printf("Error: Wrong container header\n");
+		return -EFAULT;
+	}
+
+	if (!phdr->num_images) {
+		printf("Error: Wrong container, no image found\n");
+		return -EFAULT;
+	}
+
+	length = phdr->length_lsb + (phdr->length_msb << 8);
+
+	debug("container length %u\n", length);
+
+	err = ahab_auth_cntr_hdr(phdr, length);
+	if (err) {
+		ret = -EIO;
+		goto exit;
+	}
+
+	debug("Verify images\n");
+
+	/* Copy images to dest address */
+	for (i = 0; i < phdr->num_images; i++) {
+		img = (struct boot_img_t *)(addr +
+					    sizeof(struct container_hdr) +
+					    i * sizeof(struct boot_img_t));
+
+		debug("img %d, dst 0x%x, src 0x%lx, size 0x%x\n",
+		      i, (uint32_t) img->dst, img->offset + addr, img->size);
+
+		memcpy((void *)img->dst, (const void *)(img->offset + addr),
+		       img->size);
+
+		s = img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+		e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1;
+
+		flush_dcache_range(s, e);
+
+		ret = ahab_verify_cntr_image(img, i);
+		if (ret)
+			goto exit;
+	}
+
+exit:
+	debug("ahab_auth_release, 0x%x\n", ret);
+	ahab_auth_release();
+
+	return ret;
+}
+
+static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc,
+			   char *const argv[])
+{
+	ulong addr;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	addr = simple_strtoul(argv[1], NULL, 16);
+
+	printf("Authenticate OS container at 0x%lx\n", addr);
+
+	if (authenticate_os_container(addr))
+		return CMD_RET_FAILURE;
+
+	return CMD_RET_SUCCESS;
+}
+
+static void display_life_cycle(u32 lc)
+{
+	printf("Lifecycle: 0x%08X, ", lc);
+	switch (lc) {
+	case 0x1:
+		printf("BLANK\n\n");
+		break;
+	case 0x2:
+		printf("FAB\n\n");
+		break;
+	case 0x4:
+		printf("NXP Provisioned\n\n");
+		break;
+	case 0x8:
+		printf("OEM Open\n\n");
+		break;
+	case 0x10:
+		printf("OEM Secure World Closed\n\n");
+		break;
+	case 0x20:
+		printf("OEM closed\n\n");
+		break;
+	case 0x40:
+		printf("Field Return OEM\n\n");
+		break;
+	case 0x80:
+		printf("Field Return NXP\n\n");
+		break;
+	case 0x100:
+		printf("OEM Locked\n\n");
+		break;
+	case 0x200:
+		printf("BRICKED\n\n");
+		break;
+	default:
+		printf("Unknown\n\n");
+		break;
+	}
+}
+
+static int confirm_close(void)
+{
+	puts("Warning: Please ensure your sample is in NXP closed state, "
+	     "OEM SRK hash has been fused, \n"
+	     "         and you are able to boot a signed image successfully "
+	     "without any SECO events reported.\n"
+	     "         If not, your sample will be unrecoverable.\n"
+	     "\nReally perform this operation? <y/N>\n");
+
+	if (confirm_yesno())
+		return 1;
+
+	puts("Ahab close aborted\n");
+	return 0;
+}
+
+static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char *const argv[])
+{
+	int err;
+	u32 resp;
+
+	if (!confirm_close())
+		return -EACCES;
+
+	err = ahab_forward_lifecycle(8, &resp);
+	if (err != 0) {
+		printf("Error in forward lifecycle to OEM closed\n");
+		return -EIO;
+	}
+
+	printf("Change to OEM closed successfully\n");
+
+	return 0;
+}
+
+int ahab_dump(void)
+{
+	u32 buffer[32];
+	int ret, i = 0;
+
+	do {
+		ret = ahab_dump_buffer(buffer, 32);
+		if (ret < 0) {
+			printf("Error in dump AHAB log\n");
+			return -EIO;
+		}
+
+		if (ret == 1) {
+			break;
+		} else {
+			for (i = 0; i < ret; i++)
+				printf("0x%x\n", buffer[i]);
+		}
+	} while (ret >= 21);
+
+	return 0;
+}
+
+static int do_ahab_dump(struct cmd_tbl *cmdtp, int flag, int argc,
+			 char *const argv[])
+{
+	return ahab_dump();
+}
+
+static void display_event(u32 event)
+{
+	printf("\n\t0x%08x\n", event);
+	printf("\t%s", ele_ipc_str[get_idx(ele_ipc,
+		(event >> 24) & 0xFF, ARRAY_SIZE(ele_ipc))]);
+	printf("\t%s", ele_cmd_str[get_idx(ele_cmd,
+		(event >> 16) & 0xFF, ARRAY_SIZE(ele_cmd))]);
+	printf("\t%s", ele_ind_str[get_idx(ele_ind,
+		(event >> 8) & 0xFF, ARRAY_SIZE(ele_ind))]);
+	printf("\t%s", ele_status_str[get_idx(ele_status,
+		event & 0xFF, ARRAY_SIZE(ele_status))]);
+}
+
+static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc,
+			  char *const argv[])
+{
+	u32 lc, i;
+	u32 events[AHAB_MAX_EVENTS];
+	u32 cnt = AHAB_MAX_EVENTS;
+	int ret;
+
+	lc = readl(FSB_BASE_ADDR + 0x41c);
+	lc &= 0x3ff;
+
+	display_life_cycle(lc);
+
+	ret = ahab_get_events(events, &cnt, NULL);
+	if (ret) {
+		printf("Get ELE EVENTS error %d\n", ret);
+		return CMD_RET_FAILURE;
+	}
+
+	if (!cnt) {
+		puts("\n\tNo Events Found!\n");
+		return 0;
+	}
+
+	for (i = 0; i < cnt; i++)
+		display_event(events[i]);
+
+	return 0;
+}
+
+U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate,
+	   "autenticate OS container via AHAB",
+	   "addr\n"
+	   "addr - OS container hex address\n"
+);
+
+U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close,
+	   "Change AHAB lifecycle to OEM closed",
+	   ""
+);
+
+U_BOOT_CMD(ahab_dump, CONFIG_SYS_MAXARGS, 1, do_ahab_dump,
+	   "Dump AHAB log for debug",
+	   ""
+);
+
+U_BOOT_CMD(ahab_status, CONFIG_SYS_MAXARGS, 1, do_ahab_status,
+	   "display AHAB lifecycle only",
+	   ""
+);
diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c
index 55317abba23..27c87f0cd18 100644
--- a/arch/arm/mach-imx/hab.c
+++ b/arch/arm/mach-imx/hab.c
@@ -288,9 +288,10 @@ static char *rsn_str[] = {
 };
 
 static char *sts_str[] = {
-			  "STS = HAB_SUCCESS (0xF0)\n",
+			  "STS = HAB_STS_ANY (0x00)\n",
 			  "STS = HAB_FAILURE (0x33)\n",
 			  "STS = HAB_WARNING (0x69)\n",
+			  "STS = HAB_SUCCESS (0xF0)\n",
 			  "STS = INVALID\n",
 			  NULL
 };
@@ -335,8 +336,7 @@ static uint8_t hab_statuses[5] = {
 	HAB_STS_ANY,
 	HAB_FAILURE,
 	HAB_WARNING,
-	HAB_SUCCESS,
-	-1
+	HAB_SUCCESS
 };
 
 static uint8_t hab_reasons[26] = {
@@ -364,8 +364,7 @@ static uint8_t hab_reasons[26] = {
 	HAB_UNS_ITEM,
 	HAB_UNS_KEY,
 	HAB_UNS_PROTOCOL,
-	HAB_UNS_STATE,
-	-1
+	HAB_UNS_STATE
 };
 
 static uint8_t hab_contexts[12] = {
@@ -379,8 +378,7 @@ static uint8_t hab_contexts[12] = {
 	HAB_CTX_COMMAND,
 	HAB_CTX_AUT_DAT,
 	HAB_CTX_ASSERT,
-	HAB_CTX_EXIT,
-	-1
+	HAB_CTX_EXIT
 };
 
 static uint8_t hab_engines[16] = {
@@ -398,30 +396,34 @@ static uint8_t hab_engines[16] = {
 	HAB_ENG_ROM,
 	HAB_ENG_HDCP,
 	HAB_ENG_RTL,
-	HAB_ENG_SW,
-	-1
+	HAB_ENG_SW
 };
 
-static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
+static inline uint32_t get_idx(uint8_t *list, uint8_t tgt, uint32_t size)
 {
-	uint8_t idx = 0;
-	uint8_t element = list[idx];
-	while (element != -1) {
+	uint32_t idx = 0;
+	uint8_t element;
+	while (idx < size) {
+		element = list[idx];
 		if (element == tgt)
 			return idx;
-		element = list[++idx];
+		++idx;
 	}
-	return -1;
+	return idx;
 }
 
 static void process_event_record(uint8_t *event_data, size_t bytes)
 {
 	struct record *rec = (struct record *)event_data;
 
-	printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0])]);
-	printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1])]);
-	printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2])]);
-	printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]);
+	printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0],
+		ARRAY_SIZE(hab_statuses))]);
+	printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1],
+		ARRAY_SIZE(hab_reasons))]);
+	printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2],
+		ARRAY_SIZE(hab_contexts))]);
+	printf("%s", eng_str[get_idx(hab_engines, rec->contents[3],
+		ARRAY_SIZE(hab_engines))]);
 }
 
 static void display_event(uint8_t *event_data, size_t bytes)
diff --git a/arch/arm/mach-imx/i2c-mxv7.c b/arch/arm/mach-imx/i2c-mxv7.c
index d36347d8e82..9a8b033031d 100644
--- a/arch/arm/mach-imx/i2c-mxv7.c
+++ b/arch/arm/mach-imx/i2c-mxv7.c
@@ -1,6 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2012 Boundary Devices Inc.
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
  */
 #include <common.h>
 #include <malloc.h>
@@ -33,13 +35,36 @@ int force_idle_bus(void *priv)
 
 	printf("%s: sda=%d scl=%d sda.gp=0x%x scl.gp=0x%x\n", __func__,
 		sda, scl, p->sda.gp, p->scl.gp);
+	gpio_direction_output(p->scl.gp, 1);
+	udelay(1000);
 	/* Send high and low on the SCL line */
 	for (i = 0; i < 9; i++) {
-		gpio_direction_output(p->scl.gp, 0);
+		gpio_direction_output(p->scl.gp, 1);
 		udelay(50);
-		gpio_direction_input(p->scl.gp);
+		gpio_direction_output(p->scl.gp, 0);
 		udelay(50);
 	}
+
+	/* Simulate the NACK */
+	gpio_direction_output(p->sda.gp, 1);
+	udelay(50);
+	gpio_direction_output(p->scl.gp, 1);
+	udelay(50);
+	gpio_direction_output(p->scl.gp, 0);
+	udelay(50);
+
+	/* Simulate the STOP signal */
+	gpio_direction_output(p->sda.gp, 0);
+	udelay(50);
+	gpio_direction_output(p->scl.gp, 1);
+	udelay(50);
+	gpio_direction_output(p->sda.gp, 1);
+	udelay(50);
+
+	/* Get the bus status */
+	gpio_direction_input(p->sda.gp);
+	gpio_direction_input(p->scl.gp);
+
 	start_time = get_timer(0);
 	for (;;) {
 		sda = gpio_get_value(p->sda.gp);
diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c
index 0e767864822..b857a48da17 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -20,6 +20,25 @@
 #define NAND_DEV	2
 #define QSPI_NOR_DEV	3
 #define ROM_API_DEV	4
+#define RAM_DEV	5
+
+/* The unit of second image offset number which provision by the fuse bits */
+#define SND_IMG_OFF_UNIT    (0x100000UL)
+
+/*
+ * If num = 0, off = (2 ^ 2) * 1MB
+ * else If num = 2, off = (2 ^ 0) * 1MB
+ * else off = (2 ^ num) * 1MB
+ */
+#define SND_IMG_NUM_TO_OFF(num) \
+        ((1UL << ((0 == (num)) ? 2 : (2 == (num)) ? 0 : (num))) * SND_IMG_OFF_UNIT)
+
+
+#if defined(CONFIG_IMX8QM)
+#define FUSE_IMG_SET_OFF_WORD 464
+#elif defined(CONFIG_IMX8QXP) || defined (CONFIG_IMX8DXL)
+#define FUSE_IMG_SET_OFF_WORD 720
+#endif
 
 int get_container_size(ulong addr, u16 *header_length)
 {
@@ -30,7 +49,7 @@ int get_container_size(ulong addr, u16 *header_length)
 	u32 max_offset = 0, img_end;
 
 	phdr = (struct container_hdr *)addr;
-	if (phdr->tag != 0x87 && phdr->version != 0x0) {
+	if (phdr->tag != 0x87 || phdr->version != 0x0) {
 		debug("Wrong container header\n");
 		return -EFAULT;
 	}
@@ -128,6 +147,12 @@ static int get_dev_container_size(void *dev, int dev_type, unsigned long offset,
 	}
 #endif
 
+#ifdef CONFIG_SPL_RAM_SUPPORT
+	if (dev_type == RAM_DEV)
+		memcpy(buf, (const void *)offset, CONTAINER_HDR_ALIGNMENT);
+#endif
+
+
 	ret = get_container_size((ulong)buf, header_length);
 
 	free(buf);
@@ -135,15 +160,48 @@ static int get_dev_container_size(void *dev, int dev_type, unsigned long offset,
 	return ret;
 }
 
+static bool check_secondary_cnt_set(unsigned long *set_off)
+{
+#if IS_ENABLED(CONFIG_ARCH_IMX8)
+	int ret;
+	u8 set_id = 1;
+	u32 fuse_val = 0;
+
+	if (!(is_imx8qxp() && is_soc_rev(CHIP_REV_B))) {
+		ret = sc_misc_get_boot_container(-1, &set_id);
+		if (!ret) {
+			/* Secondary boot */
+			if (set_id == 2) {
+				ret = sc_misc_otp_fuse_read(-1, FUSE_IMG_SET_OFF_WORD, &fuse_val);
+				if (!ret) {
+					if (set_off)
+						*set_off = SND_IMG_NUM_TO_OFF(fuse_val);
+					return true;
+				}
+			}
+		}
+	}
+#endif
+
+	return false;
+}
+
 static unsigned long get_boot_device_offset(void *dev, int dev_type)
 {
-	unsigned long offset = 0;
+	unsigned long offset = 0, sec_set_off = 0;
+	bool sec_boot = false;
+
+	sec_boot = check_secondary_cnt_set(&sec_set_off);
+	if (sec_boot)
+		printf("Secondary set selected\n");
+	else
+		printf("Primary set selected\n");
 
 	if (dev_type == MMC_DEV) {
 		struct mmc *mmc = (struct mmc *)dev;
 
 		if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) {
-			offset = CONTAINER_HDR_MMCSD_OFFSET;
+			offset = sec_boot? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET;
 		} else {
 			u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
 
@@ -153,61 +211,82 @@ static unsigned long get_boot_device_offset(void *dev, int dev_type)
 				else
 					offset = CONTAINER_HDR_EMMC_OFFSET;
 			} else {
-				offset = CONTAINER_HDR_MMCSD_OFFSET;
+				offset = sec_boot? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET;
 			}
 		}
 	} else if (dev_type == QSPI_DEV) {
-		offset = CONTAINER_HDR_QSPI_OFFSET;
+		offset = sec_boot? (sec_set_off + CONTAINER_HDR_QSPI_OFFSET) : CONTAINER_HDR_QSPI_OFFSET;
 	} else if (dev_type == NAND_DEV) {
-		offset = CONTAINER_HDR_NAND_OFFSET;
+		offset = sec_boot? (sec_set_off + CONTAINER_HDR_NAND_OFFSET) : CONTAINER_HDR_NAND_OFFSET;
 	} else if (dev_type == QSPI_NOR_DEV) {
 		offset = CONTAINER_HDR_QSPI_OFFSET + 0x08000000;
 	} else if (dev_type == ROM_API_DEV) {
 		offset = (unsigned long)dev;
+	} else if (dev_type == RAM_DEV) {
+		offset = (unsigned long)dev + CONTAINER_HDR_MMCSD_OFFSET;
 	}
 
+	debug("container set offset 0x%lx\n", offset);
+
 	return offset;
 }
 
-static int get_imageset_end(void *dev, int dev_type)
+static __maybe_unused ulong get_imageset_end(void *dev, int dev_type)
 {
-	unsigned long offset1 = 0, offset2 = 0;
-	int value_container[2];
+	unsigned long offset[3] = {};
+	int value_container[3] = {};
 	u16 hdr_length;
 
-	offset1 = get_boot_device_offset(dev, dev_type);
-	offset2 = CONTAINER_HDR_ALIGNMENT + offset1;
+	offset[0] = get_boot_device_offset(dev, dev_type);
 
-	value_container[0] = get_dev_container_size(dev, dev_type, offset1, &hdr_length);
+	value_container[0] = get_dev_container_size(dev, dev_type, offset[0], &hdr_length);
 	if (value_container[0] < 0) {
 		printf("Parse seco container failed %d\n", value_container[0]);
-		return value_container[0];
+		return 0;
 	}
 
 	debug("seco container size 0x%x\n", value_container[0]);
 
-	value_container[1] = get_dev_container_size(dev, dev_type, offset2, &hdr_length);
-	if (value_container[1] < 0) {
-		debug("Parse scu container failed %d, only seco container\n",
-		      value_container[1]);
-		/* return seco container total size */
-		return value_container[0] + offset1;
+	if (is_imx8dxl()) {
+		offset[1] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[0];
+
+		value_container[1] = get_dev_container_size(dev, dev_type, offset[1], &hdr_length);
+		if (value_container[1] < 0) {
+			printf("Parse v2x container failed %d\n", value_container[1]);
+			return value_container[0] + offset[0]; /* return seco container total size */
+		}
+
+		debug("v2x container size 0x%x\n", value_container[1]);
+
+		offset[2] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[1];
+	} else {
+		/* Skip offset[1] */
+		offset[2] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[0];
+	}
+
+	value_container[2] = get_dev_container_size(dev, dev_type, offset[2], &hdr_length);
+	if (value_container[2] < 0) {
+		debug("Parse scu container image failed %d, only seco container\n", value_container[2]);
+		if (is_imx8dxl())
+			return value_container[1] + offset[1]; /* return seco + v2x container total size */
+		else
+			return value_container[0] + offset[0]; /* return seco container total size */
 	}
 
-	debug("scu container size 0x%x\n", value_container[1]);
+	debug("scu container size 0x%x\n", value_container[2]);
 
-	return value_container[1] + offset2;
+	return value_container[2] + offset[2];
 }
 
 #ifdef CONFIG_SPL_SPI_LOAD
 unsigned long spl_spi_get_uboot_offs(struct spi_flash *flash)
 {
-	int end;
+	ulong end;
 
 	end = get_imageset_end(flash, QSPI_DEV);
 	end = ROUND(end, SZ_1K);
 
-	printf("Load image from QSPI 0x%x\n", end);
+	printf("Load image from QSPI 0x%lx\n", end);
 
 	return end;
 }
@@ -217,26 +296,52 @@ unsigned long spl_spi_get_uboot_offs(struct spi_flash *flash)
 unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
 					   unsigned long raw_sect)
 {
-	int end;
+	ulong end;
 
 	end = get_imageset_end(mmc, MMC_DEV);
 	end = ROUND(end, SZ_1K);
 
-	printf("Load image from MMC/SD 0x%x\n", end);
+	printf("Load image from MMC/SD 0x%lx\n", end);
 
 	return end / mmc->read_bl_len;
 }
+
+int spl_mmc_emmc_boot_partition(struct mmc *mmc)
+{
+	int part = 0;
+
+#ifdef CONFIG_DUAL_BOOTLOADER
+	/* Bootloader is stored in eMMC user partition for
+	 * dual bootloader.
+	 */
+	part = 0;
+#else
+	part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
+	if (part == 1 || part == 2) {
+		unsigned long sec_set_off = 0;
+		bool sec_boot = false;
+
+		sec_boot = check_secondary_cnt_set(&sec_set_off);
+		if (sec_boot)
+			part = (part == 1)? 2 : 1;
+	} else if (part == 7) {
+		part = 0;
+	}
+#endif
+
+	return part;
+}
 #endif
 
 #ifdef CONFIG_SPL_NAND_SUPPORT
 uint32_t spl_nand_get_uboot_raw_page(void)
 {
-	int end;
+	ulong end;
 
 	end = get_imageset_end((void *)NULL, NAND_DEV);
 	end = ROUND(end, SZ_16K);
 
-	printf("Load image from NAND 0x%x\n", end);
+	printf("Load image from NAND 0x%lx\n", end);
 
 	return end;
 }
@@ -245,7 +350,7 @@ uint32_t spl_nand_get_uboot_raw_page(void)
 #ifdef CONFIG_SPL_NOR_SUPPORT
 unsigned long spl_nor_get_uboot_base(void)
 {
-	int end;
+	ulong end;
 
 	/* Calculate the image set end,
 	 * if it is less than CONFIG_SYS_UBOOT_BASE(0x8281000),
@@ -258,7 +363,7 @@ unsigned long spl_nor_get_uboot_base(void)
 	else
 		end = ROUND(end, SZ_1K);
 
-	printf("Load image from NOR 0x%x\n", end);
+	printf("Load image from NOR 0x%lx\n", end);
 
 	return end;
 }
@@ -284,3 +389,17 @@ ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev)
 	return end;
 }
 #endif
+
+#ifdef CONFIG_SPL_RAM_SUPPORT
+unsigned long spl_ram_get_uboot_base(void)
+{
+	ulong end;
+
+	end = get_imageset_end((void *)CONFIG_SPL_LOAD_FIT_ADDRESS, RAM_DEV);
+	end = ROUND(end, SZ_1K);
+
+	printf("Load image from RAM 0x%lx\n", end);
+
+	return end;
+}
+#endif
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index b43739e5c64..a2f29ffa90e 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -6,8 +6,21 @@ config AHAB_BOOT
 	help
 	  This option enables the support for AHAB secure boot.
 
+config IMX_LOAD_HDMI_FIMRWARE_RX
+	bool "Enable HDMI rx firmware loading"
+	depends on ARCH_IMX8 || VIDEO_IMX_HDP_LOAD
+	help
+	  This enable the hdmi rx firmware loading. It depends on the "hdprx" command.
+
+config IMX_LOAD_HDMI_FIMRWARE_TX
+	bool "Enable HDMI tx firmware loading"
+	depends on ARCH_IMX8 || VIDEO_IMX_HDP_LOAD
+	help
+	  This enable the hdmi tx firmware loading. It depends on the "hdp" command.
+
 config IMX8
 	bool
+	select HAS_CAAM
 
 config MU_BASE_SPL
 	hex "MU base address used in SPL"
@@ -28,6 +41,12 @@ config IMX8QXP
 	select SPL_RECOVER_DATA_SECTION
 	bool
 
+config IMX8DXL
+	select IMX8
+	select SUPPORT_SPL
+	select SPL_RECOVER_DATA_SECTION
+	bool
+
 config SYS_SOC
 	default "imx8"
 
@@ -39,6 +58,12 @@ config BOOTAUX_RESERVED_MEM_SIZE
 	hex "i.MX auxiliary core dram memory size"
 	default 0
 
+config PSCI_BOARD_REBOOT
+	bool "Enable psci board reboot command"
+	depends on ARM_PSCI_FW
+	help
+	  This is a optional command used to trigger system board reboot on imx8.
+
 choice
 	prompt "i.MX8 board select"
 	optional
@@ -72,6 +97,20 @@ config TARGET_IMX8QM_MEK
 	bool "Support i.MX8QM MEK board"
 	select BOARD_LATE_INIT
 	select IMX8QM
+	select FSL_CAAM
+	select FSL_BLOB
+	select ARCH_MISC_INIT
+	select SPL_CRYPTO if SPL
+
+config TARGET_IMX8QM_LPDDR4_VAL
+	bool "Support i.MX8QM lpddr4 validation board"
+	select BOARD_LATE_INIT
+	select IMX8QM
+
+config TARGET_IMX8QM_DDR4_VAL
+	bool "Support i.MX8QM ddr4 validation board"
+	select BOARD_LATE_INIT
+	select IMX8QM
 
 config TARGET_CONGA_QMX8
 	bool "Support congatec conga-QMX8 board"
@@ -89,12 +128,82 @@ config TARGET_IMX8QXP_MEK
 	bool "Support i.MX8QXP MEK board"
 	select BOARD_LATE_INIT
 	select IMX8QXP
+	select FSL_CAAM
+	select FSL_BLOB
+	select ARCH_MISC_INIT
+	select SPL_CRYPTO if SPL
+
+config TARGET_IMX8QM_MEK_A53_ONLY
+        bool "Support i.MX8QM MEK board, cluster A53 only"
+        select BOARD_LATE_INIT
+        select IMX8QM
+
+config TARGET_IMX8QM_MEK_A72_ONLY
+        bool "Support i.MX8QM MEK board, cluster A72 only"
+        select BOARD_LATE_INIT
+        select IMX8QM
+
+config TARGET_IMX8QXP_LPDDR4_VAL
+	bool "Support i.MX8QXP lpddr4 validation board"
+	select BOARD_LATE_INIT
+	select IMX8QXP
+
+config TARGET_IMX8QXP_DDR3_VAL
+	bool "Support i.MX8QXP ddr3 validation board"
+	select BOARD_LATE_INIT
+	select IMX8QXP
+
+config TARGET_IMX8X_17X17_VAL
+	bool "Support i.MX8QXP/DX 17x17 validation board"
+	select BOARD_LATE_INIT
+	select IMX8QXP
+
+config TARGET_IMX8DXL_PHANTOM_MEK
+	bool "Support i.MX8DXL PHANTOM MEK board"
+	select BOARD_LATE_INIT
+	select IMX8QXP
+	select FSL_CAAM
+	select FSL_BLOB
+	select ARCH_MISC_INIT
+	select SPL_CRYPTO if SPL
+
+config TARGET_IMX8DX_MEK
+	bool "Support i.MX8DX MEK board"
+	select BOARD_LATE_INIT
+	select SUPPORT_SPL
+	select IMX8QXP
+	select FSL_CAAM
+	select FSL_BLOB
+	select ARCH_MISC_INIT
+	select SPL_CRYPTO if SPL
+
+config TARGET_IMX8DXL_EVK
+	bool "Support i.MX8DXL EVK board"
+	select BOARD_LATE_INIT
+	select IMX8DXL
+	select FSL_CAAM
+	select FSL_BLOB
+	select ARCH_MISC_INIT
+	select SPL_CRYPTO if SPL
+
+config TARGET_IMX8DXL_DDR3_EVK
+	bool "Support i.MX8DXL EVK board"
+	select BOARD_LATE_INIT
+	select IMX8DXL
+	select FSL_CAAM
+	select FSL_BLOB
+	select ARCH_MISC_INIT
+	select SPL_CRYPTO if SPL
 
 endchoice
 
 source "board/freescale/imx8qm_mek/Kconfig"
 source "board/freescale/imx8qxp_mek/Kconfig"
 source "board/congatec/cgtqmx8/Kconfig"
+source "board/freescale/imx8qm_val/Kconfig"
+source "board/freescale/imx8qxp_val/Kconfig"
+source "board/freescale/imx8dxl_phantom_mek/Kconfig"
+source "board/freescale/imx8dxl_evk/Kconfig"
 source "board/advantech/imx8qm_rom7720_a1/Kconfig"
 source "board/toradex/apalis-imx8/Kconfig"
 source "board/toradex/colibri-imx8x/Kconfig"
diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile
index 4ca4c14bddb..4a8779cf339 100644
--- a/arch/arm/mach-imx/imx8/Makefile
+++ b/arch/arm/mach-imx/imx8/Makefile
@@ -4,8 +4,11 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += cpu.o iomux.o misc.o lowlevel_init.o
+obj-y += cpu.o iomux.o misc.o lowlevel_init.o lpcg.o clock.o
 obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
 obj-$(CONFIG_AHAB_BOOT) += ahab.o
 
+ifndef CONFIG_SPL_BUILD
+obj-y += partition.o
 obj-$(CONFIG_IMX_SNVS_SEC_SC) += snvs_security_sc.o
+endif
diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c
index 5a4d39cdaad..3c3c4cdc4fa 100644
--- a/arch/arm/mach-imx/imx8/ahab.c
+++ b/arch/arm/mach-imx/imx8/ahab.c
@@ -16,6 +16,7 @@
 #include <asm/mach-imx/image.h>
 #include <console.h>
 #include <cpu_func.h>
+#include <asm/mach-imx/ahab.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -25,6 +26,86 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define SECO_PT                 2U
 
+int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
+{
+	int err;
+	memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)container,
+		ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
+
+	err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER,
+				   SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
+
+	if (err) {
+		printf("Authenticate container hdr failed, return %d\n",
+		       err);
+	}
+
+	return err;
+}
+
+int ahab_auth_release(void)
+{
+	int err;
+
+	err = sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0);
+	if (err)
+		printf("Error: release container failed!\n");
+
+	return err;
+}
+
+int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
+{
+	sc_faddr_t start, end;
+	sc_rm_mr_t mr;
+	int err;
+	int ret = 0;
+
+	debug("img %d, dst 0x%llx, src 0x%x, size 0x%x\n",
+	      image_index, img->dst, img->offset, img->size);
+
+	/* Find the memreg and set permission for seco pt */
+	err = sc_rm_find_memreg(-1, &mr,
+				img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1),
+				ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1);
+
+	if (err) {
+		printf("Error: can't find memreg for image load address 0x%llx, error %d\n", img->dst, err);
+		return -ENOMEM;
+	}
+
+	err = sc_rm_get_memreg_info(-1, mr, &start, &end);
+	if (!err)
+		debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end);
+
+	err = sc_rm_set_memreg_permissions(-1, mr,
+					   SECO_PT, SC_RM_PERM_FULL);
+	if (err) {
+		printf("Set permission failed for img %d, error %d\n",
+		       image_index, err);
+		return -EPERM;
+	}
+
+	err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE,
+				   1 << image_index);
+	if (err) {
+		printf("Authenticate img %d failed, return %d\n",
+		       image_index, err);
+		ret = -EIO;
+	}
+
+	err = sc_rm_set_memreg_permissions(-1, mr,
+					   SECO_PT, SC_RM_PERM_NONE);
+	if (err) {
+		printf("Remove permission failed for img %d, error %d\n",
+		       image_index, err);
+		ret = -EPERM;
+	}
+
+	return ret;
+}
+
+
 static inline bool check_in_dram(ulong addr)
 {
 	int i;
@@ -46,8 +127,6 @@ int authenticate_os_container(ulong addr)
 	struct container_hdr *phdr;
 	int i, ret = 0;
 	int err;
-	sc_rm_mr_t mr;
-	sc_faddr_t start, end;
 	u16 length;
 	struct boot_img_t *img;
 	unsigned long s, e;
@@ -76,14 +155,9 @@ int authenticate_os_container(ulong addr)
 	length = phdr->length_lsb + (phdr->length_msb << 8);
 
 	debug("container length %u\n", length);
-	memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)addr,
-	       ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
 
-	err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER,
-				   SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
+	err = ahab_auth_cntr_hdr(phdr, length);
 	if (err) {
-		printf("Authenticate container hdr failed, return %d\n",
-		       err);
 		ret = -EIO;
 		goto exit;
 	}
@@ -105,50 +179,13 @@ int authenticate_os_container(ulong addr)
 
 		flush_dcache_range(s, e);
 
-		/* Find the memreg and set permission for seco pt */
-		err = sc_rm_find_memreg(-1, &mr, s, e);
-		if (err) {
-			printf("Error: can't find memreg for image load address 0x%llx, error %d\n", img->dst, err);
-			ret = -ENOMEM;
-			goto exit;
-		}
-
-		err = sc_rm_get_memreg_info(-1, mr, &start, &end);
-		if (!err)
-			debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end);
-
-		err = sc_rm_set_memreg_permissions(-1, mr, SECO_PT,
-						   SC_RM_PERM_FULL);
-		if (err) {
-			printf("Set permission failed for img %d, error %d\n",
-			       i, err);
-			ret = -EPERM;
-			goto exit;
-		}
-
-		err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE,
-					   (1 << i));
-		if (err) {
-			printf("Authenticate img %d failed, return %d\n",
-			       i, err);
-			ret = -EIO;
-		}
-
-		err = sc_rm_set_memreg_permissions(-1, mr, SECO_PT,
-						   SC_RM_PERM_NONE);
-		if (err) {
-			printf("Remove permission failed for img %d, err %d\n",
-			       i, err);
-			ret = -EPERM;
-		}
-
+		ret = ahab_verify_cntr_image(img, i);
 		if (ret)
 			goto exit;
 	}
 
 exit:
-	if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0) != SC_ERR_NONE)
-		printf("Error: release container failed!\n");
+	ahab_auth_release();
 
 	return ret;
 }
@@ -263,7 +300,7 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc,
 	u16 lc;
 
 	err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL);
-	if (err != SC_ERR_NONE) {
+	if (err) {
 		printf("Error in get lifecycle\n");
 		return -EIO;
 	}
@@ -271,7 +308,7 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc,
 	display_life_cycle(lc);
 
 	err = sc_seco_get_event(-1, idx, &event);
-	while (err == SC_ERR_NONE) {
+	while (!err) {
 		printf("SECO Event[%u] = 0x%08X\n", idx, event);
 		display_ahab_auth_event(event);
 
@@ -312,7 +349,7 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
 		return -EACCES;
 
 	err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL);
-	if (err != SC_ERR_NONE) {
+	if (err) {
 		printf("Error in get lifecycle\n");
 		return -EIO;
 	}
@@ -324,7 +361,7 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc,
 	}
 
 	err = sc_seco_forward_lifecycle(-1, 16);
-	if (err != SC_ERR_NONE) {
+	if (err) {
 		printf("Error in forward lifecycle to OEM closed\n");
 		return -EIO;
 	}
diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c
index 9941b57b4be..17ce7c09591 100644
--- a/arch/arm/mach-imx/imx8/clock.c
+++ b/arch/arm/mach-imx/imx8/clock.c
@@ -1,18 +1,78 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
  */
 
 #include <common.h>
 #include <asm/global_data.h>
 #include <linux/errno.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/i2c.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/lpcg.h>
+#include <asm/arch/sci/sci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+u32 get_lpuart_clk(void)
+{
+	return mxc_get_clock(MXC_UART_CLK);
+}
+
 u32 mxc_get_clock(enum mxc_clock clk)
 {
+	int err;
+	sc_pm_clock_rate_t clkrate;
+
 	switch (clk) {
+	case MXC_UART_CLK:
+		err = sc_pm_get_clock_rate(-1,
+				SC_R_UART_0, 2, &clkrate);
+		if (err) {
+			printf("sc get UART clk failed! err=%d\n", err);
+			return 0;
+		}
+		return clkrate;
+	case MXC_ESDHC_CLK:
+		err = sc_pm_get_clock_rate(-1,
+				SC_R_SDHC_0, 2, &clkrate);
+		if (err) {
+			printf("sc get uSDHC1 clk failed! err=%d\n", err);
+			return 0;
+		}
+		return clkrate;
+	case MXC_ESDHC2_CLK:
+		err = sc_pm_get_clock_rate(-1,
+				SC_R_SDHC_1, 2, &clkrate);
+		if (err) {
+			printf("sc get uSDHC2 clk failed! err=%d\n", err);
+			return 0;
+		}
+		return clkrate;
+	case MXC_ESDHC3_CLK:
+		err = sc_pm_get_clock_rate(-1,
+				SC_R_SDHC_2, 2, &clkrate);
+		if (err) {
+			printf("sc get uSDHC3 clk failed! err=%d\n", err);
+			return 0;
+		}
+		return clkrate;
+	case MXC_FEC_CLK:
+		err = sc_pm_get_clock_rate(-1,
+				SC_R_ENET_0, 2, &clkrate);
+		if (err) {
+			printf("sc get ENET clk failed! err=%d\n", err);
+			return 0;
+		}
+		return clkrate;
+	case MXC_DDR_CLK:
+		err = sc_pm_get_clock_rate(-1,
+				SC_R_DRC_0, 0, &clkrate);
+		if (err) {
+			printf("sc get DRC0 clk failed! err=%d\n", err);
+			return 0;
+		}
+		return clkrate;
 	default:
 		printf("Unsupported mxc_clock %d\n", clk);
 		break;
@@ -20,3 +80,351 @@ u32 mxc_get_clock(enum mxc_clock clk)
 
 	return 0;
 }
+
+u32 imx_get_fecclk(void)
+{
+	return mxc_get_clock(MXC_FEC_CLK);
+}
+
+static struct imx_i2c_map *get_i2c_desc(unsigned i2c_num)
+{
+	int i;
+	for (i = 0; i < ARRAY_SIZE(imx_i2c_desc); i++) {
+		if (imx_i2c_desc[i].index == i2c_num)
+			return &imx_i2c_desc[i];
+	}
+	return NULL;
+}
+
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
+{
+	int err;
+	struct imx_i2c_map *desc;
+	int i;
+
+	desc = get_i2c_desc(i2c_num);
+	if (!desc)
+		return -EINVAL;
+
+
+	if (enable)
+		err = sc_pm_clock_enable(-1,
+			desc->rsrc, 2, true, false);
+	else
+		err = sc_pm_clock_enable(-1,
+			desc->rsrc, 2, false, false);
+
+	if (err) {
+		printf("i2c clock error %d\n", err);
+		return -EPERM;
+	}
+
+	for (i = 0; i < 4; i++) {
+		if (desc->lpcg[i] == 0)
+			break;
+		lpcg_all_clock_on(desc->lpcg[i]);
+	}
+
+	return 0;
+}
+
+u32 imx_get_i2cclk(unsigned i2c_num)
+{
+	int err;
+	u32 clock_rate;
+	struct imx_i2c_map *desc;
+
+	desc = get_i2c_desc(i2c_num);
+	if (!desc)
+		return -EINVAL;
+
+	err = sc_pm_get_clock_rate(-1, desc->rsrc, 2,
+		&clock_rate);
+	if (err)
+		return 0;
+
+	return clock_rate;
+}
+
+void init_clk_fspi(int index)
+{
+	int err = 0;
+	sc_pm_clock_rate_t rate;
+
+	/* Set FSPI0 clock root to 29 MHz */
+	rate = 29000000;
+	err = sc_pm_set_clock_rate(-1, SC_R_FSPI_0, SC_PM_CLK_PER, &rate);
+	if (err) {
+		puts("FSPI0 setrate failed\n");
+		return;
+	}
+
+	/* Enable FSPI0 clock root */
+	err = sc_pm_clock_enable(-1, SC_R_FSPI_0, SC_PM_CLK_PER, true, false);
+	if (err) {
+		puts("FSPI0 enable clock failed\n");
+		return;
+	}
+
+	lpcg_all_clock_on(FSPI_0_LPCG);
+
+	return;
+}
+
+void init_clk_gpmi_nand(void)
+{
+	int err = 0;
+	sc_pm_clock_rate_t rate;
+
+	/* Set NAND BCH clock root to 50 MHz */
+	rate = 50000000;
+	err = sc_pm_set_clock_rate(-1, SC_R_NAND, SC_PM_CLK_PER, &rate);
+	if (err) {
+		puts("NAND BCH set rate failed\n");
+		return;
+	}
+
+	/* Enable NAND BCH clock root */
+	err = sc_pm_clock_enable(-1, SC_R_NAND, SC_PM_CLK_PER, true, false);
+	if (err) {
+		puts("NAND BCH enable clock failed\n");
+		return;
+	}
+
+	/* Set NAND GPMI clock root to 50 MHz */
+	rate = 50000000;
+	err = sc_pm_set_clock_rate(-1, SC_R_NAND, SC_PM_CLK_MST_BUS, &rate);
+	if (err) {
+		puts("NAND GPMI set rate failed\n");
+		return;
+	 }
+
+	/* Enable NAND GPMI clock root */
+	err = sc_pm_clock_enable(-1, SC_R_NAND, SC_PM_CLK_MST_BUS, true, false);
+	if (err) {
+		puts("NAND GPMI enable clock failed\n");
+		return;
+	}
+
+	lpcg_all_clock_on(NAND_LPCG);
+	lpcg_all_clock_on(NAND_LPCG + 0x4);
+
+	return;
+}
+
+void enable_usboh3_clk(unsigned char enable)
+{
+#if !defined(CONFIG_IMX8DXL)
+	lpcg_all_clock_on(USB_2_LPCG);
+#endif
+	return;
+}
+
+void init_clk_usb3(int index)
+{
+	int err;
+	sc_pm_clock_rate_t rate;
+
+	err = sc_pm_clock_enable(-1, SC_R_USB_2, SC_PM_CLK_MISC, false, false);
+	if (err)
+		printf("USB3 set clock failed!, line=%d (error = %d)\n",
+			__LINE__, err);
+
+	err = sc_pm_clock_enable(-1, SC_R_USB_2, SC_PM_CLK_MST_BUS, false, false);
+	if (err)
+		printf("USB3 set clock failed!, line=%d (error = %d)\n",
+			__LINE__, err);
+
+	err = sc_pm_clock_enable(-1, SC_R_USB_2, SC_PM_CLK_PER, false, false);
+	if (err)
+		printf("USB3 set clock failed!, line=%d (error = %d)\n",
+			__LINE__, err);
+
+	rate = 12000000;
+	err = sc_pm_set_clock_rate(-1, SC_R_USB_2, SC_PM_CLK_MISC, &rate);
+	if (err)
+		printf("USB3 set MISC clock rate failed!, line=%d (error = %d)\n",
+			__LINE__, err);
+
+	rate = 250000000;
+	err = sc_pm_set_clock_rate(-1, SC_R_USB_2, SC_PM_CLK_MST_BUS, &rate);
+	if (err)
+		printf("USB3 set BUS clock rate failed!, line=%d (error = %d)\n",
+			__LINE__, err);
+
+	rate = 125000000;
+	err = sc_pm_set_clock_rate(-1, SC_R_USB_2, SC_PM_CLK_PER, &rate);
+	if (err)
+		printf("USB3 set PER clock rate failed!, line=%d (error = %d)\n",
+			__LINE__, err);
+
+	err = sc_pm_clock_enable(-1, SC_R_USB_2, SC_PM_CLK_MISC, true, false);
+	if (err)
+		printf("USB3 set clock failed!, line=%d (error = %d)\n",
+			__LINE__, err);
+
+	err = sc_pm_clock_enable(-1, SC_R_USB_2, SC_PM_CLK_MST_BUS, true, false);
+	if (err)
+		printf("USB3 set clock failed!, line=%d (error = %d)\n",
+			__LINE__, err);
+
+	err = sc_pm_clock_enable(-1, SC_R_USB_2, SC_PM_CLK_PER, true, false);
+	if (err)
+		printf("USB3 set clock failed!, line=%d (error = %d)\n",
+			__LINE__, err);
+
+	lpcg_all_clock_on(USB_3_LPCG);
+	return;
+}
+
+int cdns3_enable_clks(int index)
+{
+	init_clk_usb3(index);
+	return 0;
+}
+
+int cdns3_disable_clks(int index)
+{
+	int err;
+
+	lpcg_all_clock_off(USB_3_LPCG);
+
+	err = sc_pm_clock_enable(-1, SC_R_USB_2, SC_PM_CLK_MISC, false, false);
+	if (err)
+		printf("USB3 disable clock failed!, line=%d (error = %d)\n",
+			__LINE__, err);
+
+	err = sc_pm_clock_enable(-1, SC_R_USB_2, SC_PM_CLK_MST_BUS, false, false);
+	if (err)
+		printf("USB3 disable clock failed!, line=%d (error = %d)\n",
+			__LINE__, err);
+
+	err = sc_pm_clock_enable(-1, SC_R_USB_2, SC_PM_CLK_PER, false, false);
+	if (err)
+		printf("USB3 disable clock failed!, line=%d (error = %d)\n",
+			__LINE__, err);
+
+	return 0;
+}
+
+void init_clk_usdhc(u32 index)
+{
+#ifdef CONFIG_IMX8QM
+	sc_rsrc_t usdhcs[] = {SC_R_SDHC_0, SC_R_SDHC_1, SC_R_SDHC_2};
+	u32 instances = 3;
+#else
+	sc_rsrc_t usdhcs[] = {SC_R_SDHC_0, SC_R_SDHC_1};
+	u32 instances = 2;
+#endif
+
+	int err;
+	sc_pm_clock_rate_t actual = 400000000;
+
+	if (index >= instances)
+		return;
+
+	/* Must disable the clock before set clock parent */
+	err = sc_pm_clock_enable(-1, usdhcs[index], SC_PM_CLK_PER, false, false);
+	if (err) {
+		printf("SDHC_%d per clk enable failed!\n", index);
+		return;
+	}
+
+	/*
+	 * IMX8QXP USDHC_CLK_ROOT default source from DPLL, but this DPLL
+	 * do not stable, will cause usdhc data transfer crc error. So here
+	 * is a workaround, let USDHC_CLK_ROOT source from AVPLL. Due to
+	 * AVPLL is fixed to 1000MHz, so here config USDHC1_CLK_ROOT to 333MHz,
+	 * USDHC2_CLK_ROOT to 200MHz, make eMMC HS400ES work at 166MHz, and SD
+	 * SDR104 work at 200MHz.
+	 */
+	if (is_imx8qxp()) {
+		err = sc_pm_set_clock_parent(-1, usdhcs[index], 2, SC_PM_PARENT_PLL1);
+		if (err)
+			printf("SDHC_%d set clock parent failed!(error = %d)\n", index, err);
+
+		if (index == 1)
+			actual = 200000000;
+	}
+
+	err = sc_pm_set_clock_rate(-1, usdhcs[index], 2, &actual);
+	if (err) {
+		printf("SDHC_%d set clock failed! (error = %d)\n", index, err);
+		return;
+	}
+
+	if (actual != 400000000)
+		debug("Actual rate for SDHC_%d is %d\n", index, actual);
+
+	err = sc_pm_clock_enable(-1, usdhcs[index], SC_PM_CLK_PER, true, false);
+	if (err) {
+		printf("SDHC_%d per clk enable failed!\n", index);
+		return;
+	}
+
+	lpcg_all_clock_on(USDHC_0_LPCG + index * 0x10000);
+}
+
+void init_clk_fec(int index)
+{
+	int err;
+	sc_pm_clock_rate_t rate = 24000000;
+	sc_rsrc_t enet[2] = {SC_R_ENET_0, SC_R_ENET_1};
+
+	if (index > 1)
+		return;
+
+	if (index == -1)
+		index = 0;
+
+	/* Disable SC_R_ENET_0 clock root */
+	err = sc_pm_clock_enable(-1, enet[index], 0, false, false);
+	err |= sc_pm_clock_enable(-1, enet[index], 2, false, false);
+	err |= sc_pm_clock_enable(-1, enet[index], 4, false, false);
+	if (err) {
+		printf("\nSC_R_ENET_0 set clock disable failed! (error = %d)\n", err);
+		return;
+	}
+
+	/* Set SC_R_ENET_0 clock root to 250 MHz, the clkdiv is set to div 2
+	* so finally RGMII TX clk is 125Mhz
+	*/
+	rate = 250000000;
+	if (is_imx8dxl() && index == 1) /* eQos */
+		rate = 125000000;
+
+	/* div = 8 clk_source = PLL_1 ss_slice #7 in verfication codes */
+	err = sc_pm_set_clock_rate(-1, enet[index], 2, &rate);
+	if (err) {
+		printf("\nSC_R_ENET_0 set clock ref clock 125M failed! (error = %d)\n", err);
+		return;
+	}
+
+	/* Enable SC_R_ENET_0 clock root */
+	err = sc_pm_clock_enable(-1, enet[index], 0, true, true);
+	err |= sc_pm_clock_enable(-1, enet[index], 2, true, true);
+	err |= sc_pm_clock_enable(-1, enet[index], 4, true, true);
+	if (err) {
+		printf("\nSC_R_ENET_0 set clock enable failed! (error = %d)\n", err);
+		return;
+	}
+
+	/* Configure GPR regisers */
+	if (!(is_imx8dxl() && index == 1)) {
+		if (sc_misc_set_control(-1, enet[index], SC_C_TXCLK,  0))
+			printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_TXCLK);
+		/* Enable divclk */
+		if (sc_misc_set_control(-1, enet[index], SC_C_CLKDIV,  1))
+			printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_CLKDIV);
+	}
+	if (sc_misc_set_control(-1, enet[index], SC_C_DISABLE_50,  1))
+		printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_DISABLE_50);
+	if (sc_misc_set_control(-1, enet[index], SC_C_DISABLE_125,  1))
+		printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_DISABLE_125);
+	if (sc_misc_set_control(-1, enet[index], SC_C_SEL_125,  0))
+		printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_SEL_125);
+	if (sc_misc_set_control(-1, enet[index], SC_C_IPG_STOP,  0))
+		printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_IPG_STOP);
+
+	lpcg_all_clock_on(ENET_0_LPCG + index * 0x10000);
+}
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index ee5cc479039..10fcada0cbe 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2017-2021 NXP
  */
 
 #include <common.h>
@@ -13,12 +13,15 @@
 #include <asm/cache.h>
 #include <asm/global_data.h>
 #include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
 #include <dm/lists.h>
 #include <dm/uclass.h>
 #include <errno.h>
-#include <spl.h>
+#include <asm/arch/clock.h>
 #include <thermal.h>
 #include <asm/arch/sci/sci.h>
+#include <power-domain.h>
+#include <elf.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch-imx/cpu.h>
 #include <asm/armv8/cpu.h>
@@ -26,6 +29,9 @@
 #include <asm/setup.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <spl.h>
+#include <env.h>
+#include <asm/mach-imx/imx_vservice.h>
+#include <usb/ci_udc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -48,24 +54,11 @@ int arch_cpu_init(void)
 	spl_save_restore_data();
 #endif
 
-#ifdef CONFIG_SPL_BUILD
-	struct pass_over_info_t *pass_over;
-
-	if (is_soc_rev(CHIP_REV_A)) {
-		pass_over = get_pass_over_info();
-		if (pass_over && pass_over->g_ap_mu == 0) {
-			/*
-			 * When ap_mu is 0, means the U-Boot booted
-			 * from first container
-			 */
-			sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
-		}
-	}
-#endif
-
 	return 0;
 }
 
+static void power_off_all_usb(void);
+
 int arch_cpu_init_dm(void)
 {
 	struct udevice *devp;
@@ -79,15 +72,226 @@ int arch_cpu_init_dm(void)
 		return ret;
 	}
 
+	if (IS_ENABLED(CONFIG_XEN))
+		return 0;
+
+	struct pass_over_info_t *pass_over;
+
+	if ((is_imx8qm() || is_imx8qxp()) && is_soc_rev(CHIP_REV_A)) {
+		pass_over = get_pass_over_info();
+		if (pass_over && pass_over->g_ap_mu == 0) {
+			/*
+			 * When ap_mu is 0, means the U-Boot booted
+			 * from first container
+			 */
+			sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS);
+		}
+	}
+
+#if !defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY) && !defined(CONFIG_TARGET_IMX8QM_MEK_A53_ONLY)
 	if (is_imx8qm()) {
 		ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU,
 						    SC_PM_PW_MODE_ON);
 		if (ret)
 			return ret;
 	}
+#endif
+
+	power_off_all_usb();
+
+	return 0;
+}
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+#if !defined(CONFIG_ANDROID_SUPPORT) && !defined(CONFIG_ANDROID_AUTO_SUPPORT)
+	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+		struct udevice *dev;
+		int ret;
+
+		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+		if (ret)
+			printf("Failed to initialize caam_jr: %d\n", ret);
+	}
+#endif
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_IMX_BOOTAUX
+
+#ifdef CONFIG_IMX8QM
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
+{
+	sc_rsrc_t core_rsrc, mu_rsrc;
+	sc_faddr_t tcml_addr;
+	u32 tcm_size = SZ_256K; /* TCML + TCMU */
+	ulong addr;
+
+
+	switch (core_id) {
+	case 0:
+		core_rsrc = SC_R_M4_0_PID0;
+		tcml_addr = 0x34FE0000;
+		mu_rsrc = SC_R_M4_0_MU_1A;
+		break;
+	case 1:
+		core_rsrc = SC_R_M4_1_PID0;
+		tcml_addr = 0x38FE0000;
+		mu_rsrc = SC_R_M4_1_MU_1A;
+		break;
+	default:
+		printf("Not support this core boot up, ID:%u\n", core_id);
+		return -EINVAL;
+	}
+
+	addr = (sc_faddr_t)boot_private_data;
+
+	if (addr >= tcml_addr && addr <= tcml_addr + tcm_size) {
+		printf("Wrong image address 0x%lx, should not in TCML\n",
+			addr);
+		return -EINVAL;
+	}
+
+	printf("Power on M4 and MU\n");
+
+	if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON))
+		return -EIO;
+
+	if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON))
+		return -EIO;
+
+	printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr);
+
+	if (addr != tcml_addr)
+		memcpy((void *)tcml_addr, (void *)addr, tcm_size);
+
+	printf("Start M4 %u\n", core_id);
+	if (sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr))
+		return -EIO;
+
+	printf("bootaux complete\n");
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_IMX8QXP) || defined(CONFIG_IMX8DXL)
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
+{
+	sc_rsrc_t core_rsrc, mu_rsrc = SC_R_NONE;
+	sc_faddr_t aux_core_ram;
+	u32 size;
+	ulong addr;
+
+	switch (core_id) {
+	case 0:
+		core_rsrc = SC_R_M4_0_PID0;
+		aux_core_ram = 0x34FE0000;
+		mu_rsrc = SC_R_M4_0_MU_1A;
+		size = SZ_256K;
+		break;
+	case 1:
+		core_rsrc = SC_R_DSP;
+		aux_core_ram = 0x596f8000;
+		size = SZ_2K;
+		break;
+	default:
+		printf("Not support this core boot up, ID:%u\n", core_id);
+		return -EINVAL;
+	}
+
+	addr = (sc_faddr_t)boot_private_data;
+
+	if (addr >= aux_core_ram && addr <= aux_core_ram + size) {
+		printf("Wrong image address 0x%lx, should not in aux core ram\n",
+			addr);
+		return -EINVAL;
+	}
+
+	printf("Power on aux core %d\n", core_id);
+
+	if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON))
+		return -EIO;
+
+	if (mu_rsrc != SC_R_NONE) {
+		if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON))
+			return -EIO;
+	}
+
+	if (core_id == 1) {
+		struct power_domain pd;
+
+		if (sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false)) {
+			printf("Error enable clock\n");
+			return -EIO;
+		}
+
+		if (!power_domain_lookup_name("audio_sai0", &pd)) {
+			if (power_domain_on(&pd)) {
+				printf("Error power on SAI0\n");
+				return -EIO;
+			}
+		}
+
+		if (!power_domain_lookup_name("audio_ocram", &pd)) {
+			if (power_domain_on(&pd)) {
+				printf("Error power on HIFI RAM\n");
+				return -EIO;
+			}
+		}
+	}
+
+	printf("Copy image from 0x%lx to 0x%lx\n", addr, (ulong)aux_core_ram);
+	if (core_id == 0) {
+		/* M4 use bin file */
+		memcpy((void *)aux_core_ram, (void *)addr, size);
+	} else {
+		/* HIFI use elf file */
+		if (!valid_elf_image(addr))
+			return -1;
+		addr = load_elf_image_shdr(addr);
+	}
+
+	printf("Start %s\n", core_id == 0 ? "M4" : "HIFI");
+
+	if (sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram))
+		return -EIO;
+
+	printf("bootaux complete\n");
+	return 0;
+}
+#endif
+
+int arch_auxiliary_core_check_up(u32 core_id)
+{
+	sc_rsrc_t core_rsrc;
+	sc_pm_power_mode_t power_mode;
+
+	switch (core_id) {
+	case 0:
+		core_rsrc = SC_R_M4_0_PID0;
+		break;
+#ifdef CONFIG_IMX8QM
+	case 1:
+		core_rsrc = SC_R_M4_1_PID0;
+		break;
+#endif
+	default:
+		printf("Not support this core, ID:%u\n", core_id);
+		return 0;
+	}
+
+	if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode))
+		return 0;
+
+	if (power_mode != SC_PM_PW_MODE_OFF)
+		return 1;
 
 	return 0;
 }
+#endif
 
 int print_bootinfo(void)
 {
@@ -139,6 +343,15 @@ enum boot_device get_boot_device(void)
 
 	sc_rsrc_t dev_rsrc;
 
+#if defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY)
+	return MMC1_BOOT;
+#elif defined(CONFIG_TARGET_IMX8QM_MEK_A53_ONLY)
+	return SD2_BOOT;
+#endif
+	/* Note we only support android in EMMC SDHC0 */
+	if (IS_ENABLED(CONFIG_XEN))
+		return MMC1_BOOT;
+
 	sc_misc_get_boot_dev(-1, &dev_rsrc);
 
 	switch (dev_rsrc) {
@@ -172,12 +385,17 @@ enum boot_device get_boot_device(void)
 	return boot_dev;
 }
 
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+bool is_usb_boot(void)
+{
+	return get_boot_device() == USB_BOOT;
+}
+
+#if defined(CONFIG_SERIAL_TAG) || defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 #define FUSE_UNIQUE_ID_WORD0 16
 #define FUSE_UNIQUE_ID_WORD1 17
 void get_board_serial(struct tag_serialnr *serialnr)
 {
-	sc_err_t err;
+	int err;
 	u32 val1 = 0, val2 = 0;
 	u32 word1, word2;
 
@@ -188,13 +406,13 @@ void get_board_serial(struct tag_serialnr *serialnr)
 	word2 = FUSE_UNIQUE_ID_WORD1;
 
 	err = sc_misc_otp_fuse_read(-1, word1, &val1);
-	if (err != SC_ERR_NONE) {
+	if (err) {
 		printf("%s fuse %d read error: %d\n", __func__, word1, err);
 		return;
 	}
 
 	err = sc_misc_otp_fuse_read(-1, word2, &val2);
-	if (err != SC_ERR_NONE) {
+	if (err) {
 		printf("%s fuse %d read error: %d\n", __func__, word2, err);
 		return;
 	}
@@ -203,10 +421,9 @@ void get_board_serial(struct tag_serialnr *serialnr)
 }
 #endif /*CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG*/
 
-#ifdef CONFIG_ENV_IS_IN_MMC
 __weak int board_mmc_get_env_dev(int devno)
 {
-	return CONFIG_SYS_MMC_ENV_DEV;
+	return devno;
 }
 
 int mmc_get_env_dev(void)
@@ -214,7 +431,11 @@ int mmc_get_env_dev(void)
 	sc_rsrc_t dev_rsrc;
 	int devno;
 
+#if defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY)
+	dev_rsrc = SC_R_SDHC_0;
+#else
 	sc_misc_get_boot_dev(-1, &dev_rsrc);
+#endif
 
 	switch (dev_rsrc) {
 	case SC_R_SDHC_0:
@@ -228,15 +449,35 @@ int mmc_get_env_dev(void)
 		break;
 	default:
 		/* If not boot from sd/mmc, use default value */
-		return CONFIG_SYS_MMC_ENV_DEV;
+		return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV);
 	}
 
 	return board_mmc_get_env_dev(devno);
 }
-#endif
 
 #define MEMSTART_ALIGNMENT  SZ_2M /* Align the memory start with 2MB */
 
+static sc_faddr_t reserve_optee_shm(sc_faddr_t addr_start)
+{
+	/* OPTEE has a share memory at its top address,
+	 * ATF assigns the share memory to non-secure os partition for share with kernel
+	 * We should not add this share memory to DDR bank, as this memory is dedicated for
+	 * optee, optee driver will memremap it and can't be used by system malloc.
+	 */
+
+	sc_faddr_t optee_start = rom_pointer[0];
+	sc_faddr_t optee_size = rom_pointer[1];
+
+	if (optee_size && optee_start <= addr_start &&
+		addr_start < optee_start + optee_size) {
+		debug("optee 0x%llx 0x%llx, addr_start 0x%llx\n",
+			optee_start, optee_size, addr_start);
+		return optee_start + optee_size;
+	}
+
+	return addr_start;
+}
+
 static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
 			    sc_faddr_t *addr_end)
 {
@@ -252,7 +493,7 @@ static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
 			return -EINVAL;
 		}
 		debug("0x%llx -- 0x%llx\n", start, end);
-		*addr_start = start;
+		*addr_start = reserve_optee_shm(start);
 		*addr_end = end;
 
 		return 0;
@@ -285,6 +526,10 @@ phys_size_t get_effective_memsize(void)
 
 
 	end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
+
+	if (IS_ENABLED(CONFIG_XEN))
+		return PHYS_SDRAM_1_SIZE;
+
 	for (mr = 0; mr < 64; mr++) {
 		err = get_owned_memreg(mr, &start, &end);
 		if (!err) {
@@ -323,6 +568,14 @@ int dram_init(void)
 
 	end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
 	end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
+
+	if (IS_ENABLED(CONFIG_XEN)) {
+		gd->ram_size = PHYS_SDRAM_1_SIZE;
+		gd->ram_size += PHYS_SDRAM_2_SIZE;
+
+		return 0;
+	}
+
 	for (mr = 0; mr < 64; mr++) {
 		err = get_owned_memreg(mr, &start, &end);
 		if (!err) {
@@ -391,6 +644,16 @@ int dram_init_banksize(void)
 
 	end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size;
 	end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size;
+
+	if (IS_ENABLED(CONFIG_XEN)) {
+		gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+		gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+		gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+		gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+
+		return 0;
+	}
+
 	for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
 		err = get_owned_memreg(mr, &start, &end);
 		if (!err) {
@@ -449,7 +712,11 @@ static u64 get_block_attrs(sc_faddr_t addr_start)
 	     addr_start <= ((sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size)) ||
 	    (addr_start >= phys_sdram_2_start &&
 	     addr_start <= ((sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size)))
+#ifdef CONFIG_IMX_TRUSTY_OS
+		return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE);
+#else
 		return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
+#endif
 
 	return attr;
 }
@@ -490,6 +757,40 @@ void enable_caches(void)
 	sc_faddr_t start, end;
 	int err, i;
 
+	if (IS_ENABLED(CONFIG_XEN)) {
+		imx8_mem_map[0].virt = 0x00000000UL;
+		imx8_mem_map[0].phys = 0x00000000UL;
+		imx8_mem_map[0].size = 0x39000000UL;
+		imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+		imx8_mem_map[1].virt = 0x39000000UL;
+		imx8_mem_map[1].phys = 0x39000000UL;
+		imx8_mem_map[1].size = 0x01000000UL;
+		imx8_mem_map[1].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE);
+
+		imx8_mem_map[2].virt = 0x40000000UL;
+		imx8_mem_map[2].phys = 0x40000000UL;
+		imx8_mem_map[2].size = 0x40000000UL;
+		imx8_mem_map[2].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+
+		imx8_mem_map[3].virt = 0x80000000UL;
+		imx8_mem_map[3].phys = 0x80000000UL;
+		imx8_mem_map[3].size = 0x80000000UL;
+		imx8_mem_map[3].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE);
+
+		imx8_mem_map[4].virt = 0x100000000UL;
+		imx8_mem_map[4].phys = 0x100000000UL;
+		imx8_mem_map[4].size = 0x100000000UL;
+		imx8_mem_map[4].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+
+		icache_enable();
+		dcache_enable();
+
+		return;
+	}
+
 	/* Create map for registers access from 0x1c000000 to 0x80000000*/
 	imx8_mem_map[0].virt = 0x1c000000UL;
 	imx8_mem_map[0].phys = 0x1c000000UL;
@@ -498,6 +799,16 @@ void enable_caches(void)
 			 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
 
 	i = 1;
+
+#ifdef CONFIG_IMX_VSERVICE_SHARED_BUFFER
+	imx8_mem_map[i].virt = CONFIG_IMX_VSERVICE_SHARED_BUFFER;
+	imx8_mem_map[i].phys = CONFIG_IMX_VSERVICE_SHARED_BUFFER;
+	imx8_mem_map[i].size = CONFIG_IMX_VSERVICE_SHARED_BUFFER_SIZE;
+	imx8_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+	i++;
+#endif
+
 	for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
 		err = get_owned_memreg(mr, &start, &end);
 		if (!err) {
@@ -561,7 +872,7 @@ u64 get_page_table_size(void)
 #define FUSE_MAC0_WORD1 453
 #define FUSE_MAC1_WORD0 454
 #define FUSE_MAC1_WORD1 455
-#elif defined(CONFIG_IMX8QXP)
+#elif defined(CONFIG_IMX8QXP) || defined (CONFIG_IMX8DXL)
 #define FUSE_MAC0_WORD0 708
 #define FUSE_MAC0_WORD1 709
 #define FUSE_MAC1_WORD0 710
@@ -606,14 +917,25 @@ u32 get_cpu_rev(void)
 	u32 id = 0, rev = 0;
 	int ret;
 
+	/* returns ID - chip id [4:0], chip revision [9:5]*/
 	ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id);
 	if (ret)
 		return 0;
 
+	/* Extract silicon version */
 	rev = (id >> 5)  & 0xf;
+	/* Extract chip ID and add dummy */
 	id = (id & 0x1f) + MXC_SOC_IMX8;  /* Dummy ID for chip */
 
-	return (id << 12) | rev;
+	/* 8DXL A1: use dummy rev to differentiate from B */
+	if (id == MXC_CPU_IMX8DXL && rev == CHIP_REV_B)
+		rev = CHIP_REV_A1;
+	/* 8DXL B0: detect as B instead of C */
+	else if (id == MXC_CPU_IMX8DXL && rev == CHIP_REV_C)
+		rev = CHIP_REV_B;
+
+	/* return Chip ID in [31:12] and silicon ver in [11:0]*/
+	return (id << 12) | (rev & 0xfff);
 }
 
 void board_boot_order(u32 *spl_boot_list)
@@ -656,3 +978,245 @@ bool m4_parts_booted(void)
 
 	return false;
 }
+
+void disconnect_from_pc(void)
+{
+	int ret;
+	struct power_domain pd;
+
+	if (!power_domain_lookup_name("conn_usb0", &pd)) {
+		ret = power_domain_on(&pd);
+		if (ret) {
+			printf("conn_usb0 Power up failed! (error = %d)\n", ret);
+			return;
+		}
+
+		writel(0x0, USB_BASE_ADDR + 0x140);
+
+		ret = power_domain_off(&pd);
+		if (ret) {
+			printf("conn_usb0 Power off failed! (error = %d)\n", ret);
+			return;
+		}
+	} else {
+		printf("conn_usb0 finding failed!\n");
+		return;
+	}
+}
+
+bool check_owned_udevice(struct udevice *dev)
+{
+	int ret;
+	sc_rsrc_t resource_id;
+	struct ofnode_phandle_args args;
+
+	/* Get the resource id from its power-domain */
+	ret = dev_read_phandle_with_args(dev, "power-domains",
+					 "#power-domain-cells", 0, 0, &args);
+	if (ret) {
+		printf("no power-domains found\n");
+		return false;
+	}
+
+	/* Get the owner partition for resource*/
+	resource_id = (sc_rsrc_t)ofnode_read_u32_default(args.node, "reg", SC_R_NONE);
+	if (resource_id == SC_R_NONE) {
+		printf("Can't find the resource id for udev %s\n", dev->name);
+		return false;
+	}
+
+	debug("udev %s, resource id %d\n", dev->name, resource_id);
+
+	return sc_rm_is_resource_owned(-1, resource_id);
+}
+
+#ifdef CONFIG_IMX_VSERVICE
+struct udevice * board_imx_vservice_find_mu(struct udevice *dev)
+{
+	int ret;
+	const char *m4_mu_name[2] = {
+		"mu@5d230000",
+		"mu@5d240000"
+	};
+	struct udevice *m4_mu[2];
+	sc_rm_pt_t m4_parts[2];
+	int err;
+	struct ofnode_phandle_args args;
+	sc_rsrc_t resource_id;
+	sc_rm_pt_t resource_part;
+
+	/* Get the resource id from its power-domain */
+	ret = dev_read_phandle_with_args(dev, "power-domains",
+					 "#power-domain-cells", 0, 0, &args);
+	if (ret) {
+		printf("Can't find the power-domains property for udev %s\n", dev->name);
+		return NULL;
+	}
+
+	/* Get the owner partition for resource*/
+	resource_id = (sc_rsrc_t)ofnode_read_u32_default(args.node, "reg", SC_R_NONE);
+	if (resource_id == SC_R_NONE) {
+		printf("Can't find the resource id for udev %s\n", dev->name);
+		return NULL;
+	}
+
+	err = sc_rm_get_resource_owner(-1, resource_id, &resource_part);
+	if (err) {
+		printf("%s get resource [%d] owner error: %d\n", __func__, resource_id, err);
+		return NULL;
+	}
+
+	debug("udev %s, resource id %d, resource part %d\n", dev->name, resource_id, resource_part);
+
+	/* MU8 for communication between M4_0 and u-boot, MU9 for M4_1 and u-boot */
+	err = sc_rm_get_resource_owner(-1, SC_R_M4_0_PID0, &m4_parts[0]);
+	if (err) {
+		printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_0_PID0, err);
+		return NULL;
+	}
+
+	ret = uclass_find_device_by_name(UCLASS_MISC,  m4_mu_name[0], &m4_mu[0]);
+	if (!ret) {
+		/* If the i2c is in m4_0 partition, return the mu8 */
+		if (resource_part == m4_parts[0])
+			return m4_mu[0];
+	}
+
+	if (is_imx8qm()) {
+		err = sc_rm_get_resource_owner(-1, SC_R_M4_1_PID0, &m4_parts[1]);
+		if (err) {
+			printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_1_PID0, err);
+			return NULL;
+		}
+
+		ret = uclass_find_device_by_name(UCLASS_MISC,  m4_mu_name[1], &m4_mu[1]);
+		if (!ret) {
+			/* If the i2c is in m4_1 partition, return the mu9 */
+			if (resource_part == m4_parts[1])
+				return m4_mu[1];
+		}
+	}
+
+	return NULL;
+}
+
+void * board_imx_vservice_get_buffer(struct imx_vservice_channel *node, u32 size)
+{
+	const char *m4_mu_name[2] = {
+		"mu@5d230000",
+		"mu@5d240000"
+	};
+
+	/* Each MU ownes 1M buffer */
+	if (size <= 0x100000) {
+		if (!strcmp(node->mu_dev->name, m4_mu_name[0]))
+			return (void * )CONFIG_IMX_VSERVICE_SHARED_BUFFER;
+		else if (!strcmp(node->mu_dev->name, m4_mu_name[1]))
+			return (void * )(CONFIG_IMX_VSERVICE_SHARED_BUFFER + 0x100000);
+		else
+			return NULL;
+	}
+
+	return NULL;
+}
+#endif
+
+/* imx8qxp i2c1 has lots of devices may used by both M4 and A core
+*   If A core partition does not own the resource, we will start
+*   virtual i2c driver. Otherwise use local i2c driver.
+*/
+int board_imx_virt_i2c_bind(struct udevice *dev)
+{
+	if (check_owned_udevice(dev))
+		return -ENODEV;
+
+	return 0;
+}
+
+int board_imx_lpi2c_bind(struct udevice *dev)
+{
+	if (check_owned_udevice(dev))
+		return 0;
+
+	return -ENODEV;
+}
+
+#ifdef CONFIG_USB_PORT_AUTO
+static int usb_port_auto_check(void)
+{
+	int ret;
+	u32 usb2_data;
+	struct power_domain pd;
+	struct power_domain phy_pd;
+	struct ehci_mx6_phy_data phy_data;
+
+	if (!power_domain_lookup_name("conn_usb0", &pd)) {
+		ret = power_domain_on(&pd);
+		if (ret) {
+			printf("conn_usb0 Power up failed!\n");
+			return ret;
+		}
+
+		if (!power_domain_lookup_name("conn_usb0_phy", &phy_pd)) {
+			ret = power_domain_on(&phy_pd);
+			if (ret) {
+				printf("conn_usb0_phy Power up failed!\n");
+				return ret;
+			}
+		} else {
+			return -1;
+		}
+
+		phy_data.phy_addr = (void __iomem *)(ulong)USB_PHY0_BASE_ADDR;
+		phy_data.misc_addr = (void __iomem *)(ulong)(USB_BASE_ADDR + 0x200);
+		phy_data.anatop_addr = NULL;
+
+		enable_usboh3_clk(1);
+		usb2_data = ci_udc_check_bus_active(USB_BASE_ADDR, &phy_data, 0);
+
+		ret = power_domain_off(&phy_pd);
+		if (ret) {
+			printf("conn_usb0_phy Power off failed!\n");
+			return ret;
+		}
+		ret = power_domain_off(&pd);
+		if (ret) {
+			printf("conn_usb0 Power off failed!\n");
+			return ret;
+		}
+
+		if (!usb2_data)
+			return 1;
+		else
+			return 0;
+	}
+	return -1;
+}
+
+int board_usb_gadget_port_auto(void)
+{
+    int usb_boot_index;
+	usb_boot_index = usb_port_auto_check();
+
+	if (usb_boot_index < 0)
+		usb_boot_index = 0;
+
+	printf("auto usb %d\n", usb_boot_index);
+
+	return usb_boot_index;
+}
+#endif
+
+static void power_off_all_usb(void)
+{
+	if (is_usb_boot()) {
+		/* Turn off all usb resource to let conn SS power down */
+		sc_pm_set_resource_power_mode(-1, SC_R_USB_0_PHY, SC_PM_PW_MODE_OFF);
+		sc_pm_set_resource_power_mode(-1, SC_R_USB_1_PHY, SC_PM_PW_MODE_OFF);
+		sc_pm_set_resource_power_mode(-1, SC_R_USB_2_PHY, SC_PM_PW_MODE_OFF);
+
+		sc_pm_set_resource_power_mode(-1, SC_R_USB_0, SC_PM_PW_MODE_OFF);
+		sc_pm_set_resource_power_mode(-1, SC_R_USB_1, SC_PM_PW_MODE_OFF);
+		sc_pm_set_resource_power_mode(-1, SC_R_USB_2, SC_PM_PW_MODE_OFF);
+	}
+}
diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c
index a132ce2e6a3..a9560714e18 100644
--- a/arch/arm/mach-imx/imx8/fdt.c
+++ b/arch/arm/mach-imx/imx8/fdt.c
@@ -8,12 +8,21 @@
 #include <asm/arch/sci/sci.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/global_data.h>
+#include <asm/mach-imx/optee.h>
 #include <dm/ofnode.h>
 #include <fdt_support.h>
 #include <linux/libfdt.h>
+#include <malloc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+struct edma_ch_map {
+	sc_rsrc_t ch_start_rsrc;
+	u32 ch_start_regs;
+	u32 ch_num;
+	const char* node_path;
+};
+
 static bool check_owned_resource(sc_rsrc_t rsrc_id)
 {
 	bool owned;
@@ -43,7 +52,339 @@ static int disable_fdt_node(void *blob, int nodeoffset)
 	return rc;
 }
 
-static void update_fdt_with_owned_resources(void *blob)
+static void fdt_edma_debug_int_array(u32 *array, int count, u32 stride)
+{
+#ifdef DEBUG
+	int i;
+	for (i = 0; i < count; i++) {
+		printf("0x%x ", array[i]);
+		if (i % stride == stride - 1)
+			printf("\n");
+	}
+
+	printf("\n");
+#endif
+}
+
+static void fdt_edma_debug_stringlist(const char *stringlist, int length)
+{
+#ifdef DEBUG
+	int i = 0, len;
+	while (i < length) {
+		printf("%s\n", stringlist);
+
+		len = strlen(stringlist) + 1;
+		i += len;
+		stringlist += len;
+	}
+
+	printf("\n");
+#endif
+}
+
+static void fdt_edma_swap_int_array(u32 *array, int count)
+{
+	int i;
+	for (i = 0; i < count; i++) {
+		array[i] = cpu_to_fdt32(array[i]);
+	}
+}
+
+static int fdt_edma_update_int_array(u32 *array, int count, u32 *new_array, u32 stride, int *remove_array, int remove_count)
+{
+	int i = 0, j, curr = 0, new_cnt = 0;
+
+	do {
+		if (remove_count && curr == remove_array[i]) {
+			i++;
+			remove_count--;
+			array += stride;
+		} else {
+			for (j = 0; j< stride; j++) {
+				*new_array = *array;
+				new_array++;
+				array++;
+			}
+			new_cnt+= j;
+		}
+		curr++;
+	} while ((curr * stride) < count);
+
+	return new_cnt;
+}
+
+static int fdt_edma_update_stringlist(const char *stringlist, int stringlist_count, char *newlist, int *remove_array, int remove_count)
+{
+	int i = 0, curr = 0, new_len = 0;
+	int length;
+
+	debug("fdt_edma_update_stringlist, remove_cnt %d\n", remove_count);
+
+	do {
+		if (remove_count && curr == remove_array[i]) {
+			debug("remove %s at %d\n", stringlist, remove_array[i]);
+
+			length = strlen(stringlist) + 1;
+			stringlist += length;
+			i++;
+			remove_count--;
+		} else {
+			length = strlen(stringlist) + 1;
+			strcpy(newlist, stringlist);
+
+			debug("copy %s, %s, curr %d, len %d\n", newlist, stringlist, curr, length);
+
+			stringlist += length;
+			newlist += length;
+			new_len += length;
+		}
+		curr++;
+	} while (curr < stringlist_count);
+
+	return new_len;
+}
+
+static int fdt_edma_get_channel_id(u32 *regs, int index, struct edma_ch_map *edma)
+{
+	u32 ch_reg = regs[(index << 2) + 1];
+	u32 ch_reg_size = regs[(index << 2) + 3];
+	int ch_id = (ch_reg - edma->ch_start_regs) / ch_reg_size;
+	if (ch_id >= edma->ch_num)
+		return -1;
+
+	return ch_id;
+}
+
+static __maybe_unused void update_fdt_edma_nodes(void *blob)
+{
+	struct edma_ch_map edma_qm[] = {
+		{ SC_R_DMA_0_CH0, 0x5a200000, 32, "/dma-controller@5a1f0000"},
+		{ SC_R_DMA_1_CH0, 0x5aa00000, 32, "/dma-controller@5a9f0000"},
+		{ SC_R_DMA_2_CH0, 0x59200000, 5, "/dma-controller@591F0000"},
+		{ SC_R_DMA_2_CH5, 0x59250000, 27, "/dma-controller@591F0000"},
+		{ SC_R_DMA_3_CH0, 0x59a00000, 32, "/dma-controller@599F0000"},
+	};
+
+	struct edma_ch_map edma_qxp[] = {
+		{ SC_R_DMA_0_CH0, 0x59200000, 32, "/dma-controller@591F0000"},
+		{ SC_R_DMA_1_CH0, 0x59a00000, 32, "/dma-controller@599F0000"},
+		{ SC_R_DMA_2_CH0, 0x5a200000, 5, "/dma-controller@5a1f0000"},
+		{ SC_R_DMA_2_CH5, 0x5a250000, 27, "/dma-controller@5a1f0000"},
+		{ SC_R_DMA_3_CH0, 0x5aa00000, 32, "/dma-controller@5a9f0000"},
+	};
+
+	u32 i, j, edma_size;
+	int nodeoff, ret;
+	struct edma_ch_map *edma_array;
+
+	if (is_imx8qm()) {
+		edma_array = edma_qm;
+		edma_size = ARRAY_SIZE(edma_qm);
+	} else {
+		edma_array = edma_qxp;
+		edma_size = ARRAY_SIZE(edma_qxp);
+	}
+
+	for (i = 0; i < edma_size; i++, edma_array++) {
+		u32 regs[128];
+		u32 interrupts[96];
+		u32 dma_channels;
+		int regs_count, interrupts_count, int_names_count;
+
+		const char *list;
+		int list_len, newlist_len;
+		int remove[32];
+		int remove_cnt = 0;
+		char * newlist;
+
+		nodeoff = fdt_path_offset(blob, edma_array->node_path);
+		if (nodeoff < 0)
+			continue; /* Not found, skip it */
+
+		printf("%s, %d\n", edma_array->node_path, nodeoff);
+
+		regs_count = fdtdec_get_int_array_count(blob, nodeoff, "reg", regs, 128);
+		debug("regs_count %d\n", regs_count);
+		if (regs_count < 0)
+			continue;
+
+		interrupts_count = fdtdec_get_int_array_count(blob, nodeoff, "interrupts", interrupts, 96);
+		debug("interrupts_count %d\n", interrupts_count);
+		if (interrupts_count < 0)
+			continue;
+
+		dma_channels = fdtdec_get_uint(blob, nodeoff, "dma-channels", 0);
+		if (dma_channels == 0)
+			continue;
+
+		list = fdt_getprop(blob, nodeoff, "interrupt-names", &list_len);
+		if (!list)
+			continue;
+
+		int_names_count = fdt_stringlist_count(blob, nodeoff, "interrupt-names");
+
+		fdt_edma_debug_int_array(regs, regs_count, 4);
+		fdt_edma_debug_int_array(interrupts, interrupts_count, 3);
+		fdt_edma_debug_stringlist(list, list_len);
+
+		for (j = 0; j < (regs_count >> 2); j++) {
+			int ch_id = fdt_edma_get_channel_id(regs, j, edma_array);
+			if (ch_id < 0)
+				continue;
+
+			if (!check_owned_resource(edma_array->ch_start_rsrc + ch_id)) {
+				printf("remove edma items %d\n", j);
+
+				dma_channels--;
+
+				remove[remove_cnt] = j;
+				remove_cnt++;
+			}
+		}
+
+		if (remove_cnt > 0) {
+			u32 new_regs[128];
+			u32 new_interrupts[96];
+
+			regs_count = fdt_edma_update_int_array(regs, regs_count, new_regs, 4, remove, remove_cnt);
+			interrupts_count = fdt_edma_update_int_array(interrupts, interrupts_count, new_interrupts, 3, remove, remove_cnt);
+
+			fdt_edma_debug_int_array(new_regs, regs_count, 4);
+			fdt_edma_debug_int_array(new_interrupts, interrupts_count, 3);
+
+			fdt_edma_swap_int_array(new_regs, regs_count);
+			fdt_edma_swap_int_array(new_interrupts, interrupts_count);
+
+			/* malloc a new string list */
+			newlist = (char *)malloc(list_len);
+			if (!newlist) {
+				printf("malloc new string list failed, len=%d\n", list_len);
+				continue;
+			}
+
+			newlist_len = fdt_edma_update_stringlist(list, int_names_count, newlist, remove, remove_cnt);
+			fdt_edma_debug_stringlist(newlist, newlist_len);
+
+			ret = fdt_setprop(blob, nodeoff, "reg", new_regs, regs_count * sizeof(u32));
+			if (ret)
+				printf("fdt_setprop regs error %d\n", ret);
+
+			ret = fdt_setprop(blob, nodeoff, "interrupts", new_interrupts, interrupts_count * sizeof(u32));
+			if (ret)
+				printf("fdt_setprop interrupts error %d\n", ret);
+
+			ret = fdt_setprop_u32(blob, nodeoff, "dma-channels", dma_channels);
+			if (ret)
+				printf("fdt_setprop_u32 dma-channels error %d\n", ret);
+
+			ret = fdt_setprop(blob, nodeoff, "interrupt-names", newlist, newlist_len);
+			if (ret)
+				printf("fdt_setprop interrupt-names error %d\n", ret);
+
+			free(newlist);
+		}
+	}
+}
+
+static bool check_owned_resources_in_pd_tree(void *blob, int nodeoff,
+	unsigned int *unowned_rsrc)
+{
+	unsigned int rsrc_id;
+	int phplen;
+	const fdt32_t *php;
+
+	/* Search the ancestors nodes in current SS power-domain tree,
+	*   if all ancestors' resources are owned,  we can enable the node,
+	*   otherwise any ancestor is not owned, we should disable the node.
+	*/
+
+	do {
+		php = fdt_getprop(blob, nodeoff, "power-domains", &phplen);
+		if (!php) {
+			debug("   - ignoring no power-domains\n");
+			break;
+		}
+		if (phplen != 4) {
+			printf("ignoring %s power-domains of unexpected length %d\n",
+					fdt_get_name(blob, nodeoff, NULL), phplen);
+			break;
+		}
+		nodeoff = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*php));
+
+		rsrc_id = fdtdec_get_uint(blob, nodeoff, "reg", 0);
+		if (rsrc_id == SC_R_NONE) {
+			debug("%s's power domain use SC_R_NONE\n",
+				fdt_get_name(blob, nodeoff, NULL));
+			break;
+		}
+
+		debug("power-domains node 0x%x, resource id %u\n", nodeoff, rsrc_id);
+
+		if (!check_owned_resource(rsrc_id)) {
+			if (unowned_rsrc != NULL)
+				*unowned_rsrc = rsrc_id;
+			return false;
+		}
+	} while (fdt_node_check_compatible(blob, nodeoff, "nxp,imx8-pd"));
+
+	return true;
+}
+
+static void update_fdt_with_owned_resources_legacy(void *blob)
+{
+	/* Traverses the fdt nodes,
+	  * check its power domain and use the resource id in the power domain
+	  * for checking whether it is owned by current partition
+	  */
+
+	int offset = 0, next_off;
+	int depth = 0, next_depth;
+	unsigned int rsrc_id;
+	int rc;
+
+	for (offset = fdt_next_node(blob, offset, &depth); offset > 0;
+		 offset = fdt_next_node(blob, offset, &depth)) {
+
+		debug("Node name: %s, depth %d\n", fdt_get_name(blob, offset, NULL), depth);
+
+		if (!fdtdec_get_is_enabled(blob, offset)) {
+			debug("   - ignoring disabled device\n");
+			continue;
+		}
+
+		if (!fdt_node_check_compatible(blob, offset, "nxp,imx8-pd")) {
+			/* Skip to next depth=1 node*/
+			next_off = offset;
+			next_depth = depth;
+			do {
+				offset = next_off;
+				depth = next_depth;
+				next_off = fdt_next_node(blob, offset, &next_depth);
+				if (next_off < 0 || next_depth < 1)
+					break;
+
+				debug("PD name: %s, offset %d, depth %d\n",
+					fdt_get_name(blob, next_off, NULL), next_off, next_depth);
+			} while (next_depth > 1);
+
+			continue;
+		}
+
+		if (!check_owned_resources_in_pd_tree(blob, offset, &rsrc_id)) {
+			/* If the resource is not owned, disable it in FDT */
+			rc = disable_fdt_node(blob, offset);
+			if (!rc)
+				printf("Disable %s, resource id %u not owned\n",
+					fdt_get_name(blob, offset, NULL), rsrc_id);
+			else
+				printf("Unable to disable %s, err=%s\n",
+					fdt_get_name(blob, offset, NULL), fdt_strerror(rc));
+		}
+
+	}
+}
+
+static __maybe_unused void update_fdt_with_owned_resources(void *blob)
 {
 	/*
 	 * Traverses the fdt nodes, check its power domain and use
@@ -53,7 +394,12 @@ static void update_fdt_with_owned_resources(void *blob)
 	struct fdtdec_phandle_args args;
 	int offset = 0, depth = 0;
 	u32 rsrc_id;
-	int rc, i;
+	int rc, i, count;
+
+	/* Check the new PD, if not find, continue with old PD tree */
+	count = fdt_node_offset_by_compatible(blob, -1, "fsl,scu-pd");
+	if (count < 0)
+		return update_fdt_with_owned_resources_legacy(blob);
 
 	for (offset = fdt_next_node(blob, offset, &depth); offset > 0;
 	     offset = fdt_next_node(blob, offset, &depth)) {
@@ -110,7 +456,7 @@ static int config_smmu_resource_sid(int rsrc, int sid)
 
 	err = sc_rm_set_master_sid(-1, rsrc, sid);
 	debug("set_master_sid rsrc=%d sid=0x%x err=%d\n", rsrc, sid, err);
-	if (err != SC_ERR_NONE) {
+	if (err) {
 		if (!check_owned_resource(rsrc)) {
 			printf("%s rsrc[%d] not owned\n", __func__, rsrc);
 			return -1;
@@ -154,16 +500,16 @@ static int config_smmu_fdt_device_sid(void *blob, int device_offset, int sid)
 						     "#power-domain-cells",
 						     0, i++, &args);
 		if (ret == -ENOENT) {
-			break;
+			return 0;
 		} else if (ret) {
 			printf("Parse power-domains of node %s wrong: %d\n",
 			       fdt_get_name(blob, device_offset, NULL), ret);
 			continue;
 		}
 
+		rsrc = args.args[0];
 		debug("configure node %s sid 0x%x rsrc=%d\n",
 		      name, sid, rsrc);
-		rsrc = args.args[0];
 
 		ret = config_smmu_resource_sid(rsrc, sid);
 		if (ret)
@@ -229,56 +575,6 @@ static int config_smmu_fdt(void *blob)
 	return 0;
 }
 
-static int ft_add_optee_node(void *fdt, struct bd_info *bd)
-{
-	const char *path, *subpath;
-	int offs;
-
-	/*
-	 * No TEE space allocated indicating no TEE running, so no
-	 * need to add optee node in dts
-	 */
-	if (!boot_pointer[1])
-		return 0;
-
-	offs = fdt_increase_size(fdt, 512);
-	if (offs) {
-		printf("No Space for dtb\n");
-		return 1;
-	}
-
-	path = "/firmware";
-	offs = fdt_path_offset(fdt, path);
-	if (offs < 0) {
-		path = "/";
-		offs = fdt_path_offset(fdt, path);
-
-		if (offs < 0) {
-			printf("Could not find root node.\n");
-			return offs;
-		}
-
-		subpath = "firmware";
-		offs = fdt_add_subnode(fdt, offs, subpath);
-		if (offs < 0) {
-			printf("Could not create %s node.\n", subpath);
-			return offs;
-		}
-	}
-
-	subpath = "optee";
-	offs = fdt_add_subnode(fdt, offs, subpath);
-	if (offs < 0) {
-		printf("Could not create %s node.\n", subpath);
-		return offs;
-	}
-
-	fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz");
-	fdt_setprop_string(fdt, offs, "method", "smc");
-
-	return 0;
-}
-
 int ft_system_setup(void *blob, struct bd_info *bd)
 {
 	int ret;
@@ -292,8 +588,11 @@ int ft_system_setup(void *blob, struct bd_info *bd)
 			       fdt_strerror(off));
 	}
 
+#ifndef CONFIG_SKIP_RESOURCE_CHECKING
 	update_fdt_with_owned_resources(blob);
+#endif
 
+	update_fdt_edma_nodes(blob);
 	if (is_imx8qm()) {
 		ret = config_smmu_fdt(blob);
 		if (ret)
diff --git a/arch/arm/mach-imx/imx8/lowlevel_init.S b/arch/arm/mach-imx/imx8/lowlevel_init.S
index a66243c5e4f..84798eab6b0 100644
--- a/arch/arm/mach-imx/imx8/lowlevel_init.S
+++ b/arch/arm/mach-imx/imx8/lowlevel_init.S
@@ -6,8 +6,8 @@
 #include <config.h>
 
 .align 8
-.global boot_pointer
-boot_pointer:
+.global rom_pointer
+rom_pointer:
 	.space 32
 
 /*
@@ -17,7 +17,7 @@ boot_pointer:
 .global save_boot_params
 save_boot_params:
 	/* The firmware provided ATAG/FDT address can be found in r2/x0 */
-	adr	x0, boot_pointer
+	adr	x0, rom_pointer
 	stp	x1, x2, [x0], #16
 	stp	x3, x4, [x0], #16
 
diff --git a/arch/arm/mach-imx/imx8/lpcg.c b/arch/arm/mach-imx/imx8/lpcg.c
new file mode 100644
index 00000000000..bda2046b4ac
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/lpcg.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2017-2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <asm/arch/lpcg.h>
+#include <linux/delay.h>
+
+#define LPCG_CLOCK_MASK         0x3U
+#define LPCG_CLOCK_OFF          0x0U
+#define LPCG_CLOCK_ON           0x2U
+#define LPCG_CLOCK_AUTO         0x3U
+#define LPCG_CLOCK_STOP         0x8U
+
+#define LPCG_ALL_CLOCK_OFF      0x00000000U
+#define LPCG_ALL_CLOCK_ON       0x22222222U
+#define LPCG_ALL_CLOCK_AUTO     0x33333333U
+#define LPCG_ALL_CLOCK_STOP     0x88888888U
+
+static inline void lpcg_write(u32 lpcgVal, ulong lpcg_addr)
+{
+	/*
+	* Write twice with 4x DSC clock cycles (40x IPS clock cycles) interval
+	* to work around LPCG issue
+	*/
+	writel(lpcgVal, lpcg_addr);
+	udelay(10); /* 10us is enough. Worst case is 40x IPS cycle (200Mhz) */
+	writel(lpcgVal, lpcg_addr);
+	udelay(10);
+}
+
+void lpcg_clock_off(u32 lpcg_addr, u8 clk)
+{
+	u32 lpcgVal;
+
+	/* Read from LPCG */
+	lpcgVal = readl((ulong)lpcg_addr);
+
+	/* Modify */
+	lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U));
+	lpcgVal |= ((u32)(LPCG_CLOCK_OFF) << (clk * 4U));
+
+	/* Write to LPCG */
+	lpcg_write(lpcgVal, (ulong)lpcg_addr);
+}
+
+void lpcg_clock_on(u32 lpcg_addr, u8 clk)
+{
+	u32 lpcgVal;
+
+	/* Read from LPCG */
+	lpcgVal = readl((ulong)lpcg_addr);
+
+	/* Modify */
+	lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U));
+	lpcgVal |= ((u32)(LPCG_CLOCK_ON) << (clk * 4U));
+
+	/* Write to LPCG */
+	lpcg_write(lpcgVal, (ulong)lpcg_addr);
+}
+
+bool lpcg_is_clock_on(u32 lpcg_addr, u8 clk)
+{
+	u32 lpcgVal;
+
+	/* Read from LPCG */
+	lpcgVal = readl((ulong)lpcg_addr);
+	lpcgVal = (lpcgVal >> (clk * 4U)) & (u32)(LPCG_CLOCK_MASK);
+
+	if (lpcgVal == LPCG_CLOCK_ON)
+		return true;
+
+	return false;
+}
+
+void lpcg_clock_autogate(u32 lpcg_addr, u8 clk)
+{
+	u32 lpcgVal;
+
+	/* Read from LPCG */
+	lpcgVal = readl((ulong)lpcg_addr);
+
+	/* Modify */
+	lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U));
+	lpcgVal |= ((u32)(LPCG_CLOCK_AUTO) << (clk * 4U));
+
+	/* Write to LPCG */
+	lpcg_write(lpcgVal, (ulong)lpcg_addr);
+}
+
+void lpcg_all_clock_off(u32 lpcg_addr)
+{
+	/* Write to LPCG */
+	lpcg_write(LPCG_ALL_CLOCK_OFF, (ulong)lpcg_addr);
+}
+
+void lpcg_all_clock_on(u32 lpcg_addr)
+{
+	/* Write to LPCG */
+	lpcg_write(LPCG_ALL_CLOCK_ON, (ulong)lpcg_addr);
+
+	/* Wait for clocks to start */
+	while ((readl((ulong)lpcg_addr) & LPCG_ALL_CLOCK_STOP) != 0U)
+	{
+	}
+}
+
+void lpcg_all_clock_autogate(u32 lpcg_addr)
+{
+	/* Write to LPCG */
+	lpcg_write(LPCG_ALL_CLOCK_AUTO, (ulong)lpcg_addr);
+}
diff --git a/arch/arm/mach-imx/imx8/misc.c b/arch/arm/mach-imx/imx8/misc.c
index de19955e2f7..0f695708c5b 100644
--- a/arch/arm/mach-imx/imx8/misc.c
+++ b/arch/arm/mach-imx/imx8/misc.c
@@ -3,14 +3,27 @@
 #include <log.h>
 #include <asm/arch/sci/sci.h>
 #include <asm/mach-imx/sys_proto.h>
+#include <asm/global_data.h>
 #include <imx_sip.h>
+#include <env.h>
 #include <linux/arm-smccc.h>
+#include <generated/version_autogenerated.h>
+#include <linux/libfdt.h>
+#include <asm/arch/lpcg.h>
+#include <linux/psci.h>
+#include <dm.h>
+#include <command.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate)
 {
 	sc_pm_clock_rate_t rate = clk_rate;
 	int ret;
 
+	if (uart_rsrc < SC_R_UART_0 || uart_rsrc > SC_R_UART_4)
+		return -EINVAL;
+
 	/* Power up UARTn */
 	ret = sc_pm_set_resource_power_mode(-1, uart_rsrc, SC_PM_PW_MODE_ON);
 	if (ret)
@@ -26,15 +39,42 @@ int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate)
 	if (ret)
 		return ret;
 
+	lpcg_all_clock_on(LPUART_0_LPCG + (uart_rsrc - SC_R_UART_0) * 0x10000);
+
 	return 0;
 }
 
+extern uint32_t _end_ofs;
+
+#define V2X_PROD_VER(X)      (((X) >> 16) & 0x7FFF)
+#define V2X_MAJOR_VER(X)     (((X) >> 4) & 0xFFF)
+#define V2X_MINOR_VER(X)     ((X) & 0xF)
+
+static void set_buildinfo_to_env(uint32_t scfw, uint32_t secofw, char *mkimage, char *atf)
+{
+	if (!mkimage || !atf)
+		return;
+
+	env_set("commit_mkimage", mkimage);
+	env_set("commit_atf", atf);
+	env_set_hex("commit_scfw", (ulong)scfw);
+	env_set_hex("commit_secofw", (ulong)secofw);
+}
+
+static void set_v2x_buildinfo_to_env(u32 v2x_build, u32 v2x_commit)
+{
+	env_set_hex("commit_v2x", (ulong)v2x_commit);
+	env_set_hex("version_v2x", (ulong)v2x_build);
+}
+
 void build_info(void)
 {
 	struct arm_smccc_res res;
 	u32 seco_build = 0, seco_commit = 0;
 	u32 sc_build = 0, sc_commit = 0;
+	char *mkimage_commit, *temp;
 	ulong atf_commit = 0;
+	u32 v2x_build = 0, v2x_commit = 0;
 
 	/* Get SCFW build and commit id */
 	sc_misc_build_info(-1, &sc_build, &sc_commit);
@@ -51,6 +91,30 @@ void build_info(void)
 		seco_commit = 0;
 	}
 
+	if (is_imx8dxl()) {
+		int ret;
+		ret = sc_seco_v2x_build_info(-1, &v2x_build, &v2x_commit);
+		if (ret) {
+			debug("Failed to get V2X FW build info\n");
+			/* Display 0 when the build info is not supported */
+			v2x_build = 0;
+			v2x_commit = 0;
+		}
+	}
+
+	/* Get imx-mkimage commit id.
+	 * The imx-mkimage puts the commit hash behind the end of u-boot.bin
+	 */
+	mkimage_commit = (char *)(ulong)(CONFIG_SYS_TEXT_BASE +
+		_end_ofs + fdt_totalsize(gd->fdt_blob));
+	temp = mkimage_commit + 8;
+	*temp = '\0';
+
+	if (strlen(mkimage_commit) == 0) {
+		debug("IMX-MKIMAGE does not support build info\n");
+		mkimage_commit = "0"; /* Display 0 */
+	}
+
 	/* Get ARM Trusted Firmware commit id */
 	arm_smccc_smc(IMX_SIP_BUILDINFO, IMX_SIP_BUILDINFO_GET_COMMITHASH,
 		      0, 0, 0, 0, 0, 0, &res);
@@ -60,6 +124,38 @@ void build_info(void)
 		atf_commit = 0x30; /* Display 0 */
 	}
 
-	printf("Build: SCFW %08x, SECO-FW %08x, ATF %s\n",
-	       sc_commit, seco_commit, (char *)&atf_commit);
+	/* Set all to env */
+	set_buildinfo_to_env(sc_commit, seco_commit, mkimage_commit, (char *)&atf_commit);
+
+	printf("\n BuildInfo: \n  - SCFW %08x, SECO-FW %08x, IMX-MKIMAGE %s, ATF %s\n  - %s \n",
+		sc_commit, seco_commit, mkimage_commit, (char *)&atf_commit, U_BOOT_VERSION);
+
+	if (is_imx8dxl() && v2x_build != 0 && v2x_commit != 0) {
+		set_v2x_buildinfo_to_env(v2x_build, v2x_commit);
+		printf("  - V2X-FW %08x version %u.%u.%u\n", v2x_commit,
+			V2X_PROD_VER(v2x_build), V2X_MAJOR_VER(v2x_build), V2X_MINOR_VER(v2x_build));
+	}
+	printf("\n");
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PSCI_BOARD_REBOOT)
+
+#define PSCI_SYSTEM_RESET2_AARCH64		0xc4000012
+#define PSCI_RESET2_SYSTEM_BOARD_RESET		0x80000002
+
+int do_board_reboot(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct udevice *dev;
+
+	uclass_get_device_by_name(UCLASS_FIRMWARE, "psci", &dev);
+	invoke_psci_fn(PSCI_SYSTEM_RESET2_AARCH64, PSCI_RESET2_SYSTEM_BOARD_RESET, 0, 0);
+
+	return 1;
 }
+
+U_BOOT_CMD(
+	reboot,	1,	1,	do_board_reboot,
+	"reboot\n",
+	"system board reboot for i.MX 8 Quad devices \n"
+);
+#endif
diff --git a/arch/arm/mach-imx/imx8/partition.c b/arch/arm/mach-imx/imx8/partition.c
new file mode 100644
index 00000000000..1cecaea95d4
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/partition.c
@@ -0,0 +1,377 @@
+/*
+ * Copyright 2018 NXP.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <malloc.h>
+#include <command.h>
+#include <asm/arch-imx/cpu.h>
+#include <asm/arch/sys_proto.h>
+#include <fdt_support.h>
+#include <fdtdec.h>
+#include <linux/libfdt.h>
+#include <linux/io.h>
+#include <linux/compat.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SC_MAX_PARTS	32
+
+struct scu_rm_part_data {
+	bool used;
+	bool isolated;
+	bool restricted;
+	bool grant;
+	sc_rm_did_t did;
+	sc_rm_pt_t self;
+	sc_rm_pt_t parent;
+	char *name;
+};
+
+static struct scu_rm_part_data rm_part_data[SC_MAX_PARTS];
+
+static int partition_alloc(bool isolated, bool restricted, bool grant, sc_rm_pt_t *pt)
+{
+	sc_rm_pt_t parent_part, os_part;
+	int err;
+	int i;
+
+	for (i = 0; i < SC_MAX_PARTS; i++) {
+		if (!rm_part_data[i].used)
+			break;
+	}
+
+	if (i == SC_MAX_PARTS) {
+		puts("No empty slots\n");
+		return -EINVAL;
+	}
+
+	err = sc_rm_get_partition(-1, &parent_part);
+	if (err) {
+		puts("sc_rm_get_partition failure\n");
+		return -EINVAL;
+	}
+
+	debug("isolated %d, restricted %d, grant %d\n", isolated, restricted, grant);
+	err = sc_rm_partition_alloc(-1, &os_part, false, isolated,
+				    restricted, grant, false);
+	if (err) {
+		printf("sc_rm_partition_alloc failure %d\n", err);
+		return -EINVAL;
+	}
+
+	err = sc_rm_set_parent(-1, os_part, parent_part);
+	if (err) {
+		sc_rm_partition_free(-1, os_part);
+		return -EINVAL;
+	}
+
+
+	rm_part_data[i].self = os_part;
+	rm_part_data[i].parent = parent_part;
+	rm_part_data[i].used = true;
+	rm_part_data[i].restricted = restricted;
+	rm_part_data[i].isolated = isolated;
+	rm_part_data[i].grant = grant;
+
+	if (pt)
+		*pt = os_part;
+
+	printf("%s: os_part, %d: parent_part, %d\n", __func__, os_part,
+	       parent_part);
+
+	return 0;
+}
+
+static int do_part_alloc(int argc, char * const argv[])
+{
+	bool restricted = false, isolated = false, grant = false;
+	int ret;
+
+	if (argv[0])
+		isolated = simple_strtoul(argv[0], NULL, 10);
+	if (argv[1])
+		restricted = simple_strtoul(argv[1], NULL, 10);
+	if (argv[2])
+		grant = simple_strtoul(argv[2], NULL, 10);
+
+	ret = partition_alloc(isolated, restricted, grant, NULL);
+	if (ret)
+		return CMD_RET_FAILURE;
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_part_dtb(int argc, char * const argv[])
+{
+	int err;
+	sc_rm_pt_t pt;
+	char *pathp = "/domu";
+	int nodeoffset, subnode;
+	int rsrc_size = 0, pad_size = 0;
+	int i, ret;
+	u32 *rsrc_data = NULL, *pad_data = NULL;
+	const struct fdt_property *prop;
+	bool init_ignore_domu_power = false;
+	char *tmp;
+	void *fdt;
+
+	tmp = env_get("domu-init-ignore-poweroff");
+	if (tmp && !strncmp(tmp, "yes", 3)) {
+		init_ignore_domu_power = true;
+		printf("ignore init power off domu power\n");
+	}
+
+	if (argc)
+		fdt = (void *)simple_strtoul(argv[0], NULL, 16);
+	else
+		fdt = working_fdt;
+	printf("fdt addr %p\n", fdt);
+	nodeoffset = fdt_path_offset(fdt, pathp);
+	debug("%s %s %p\n", __func__, fdt_get_name(fdt, nodeoffset, NULL), fdt);
+	fdt_for_each_subnode(subnode, fdt, nodeoffset) {
+		if (!fdtdec_get_is_enabled(fdt, subnode))
+			continue;
+		if (!fdt_node_check_compatible(fdt, subnode, "xen,domu")) {
+			u32 temp;
+			prop = fdt_getprop(fdt, subnode, "rsrcs", &rsrc_size);
+			if (!prop)
+				debug("No rsrcs %s\n", fdt_get_name(fdt, subnode, NULL));
+			if (rsrc_size > 0) {
+				rsrc_data = kmalloc(rsrc_size, __GFP_ZERO);
+				if (!rsrc_data) {
+					debug("No mem\n");
+					return CMD_RET_FAILURE;
+				}
+				if (fdtdec_get_int_array(fdt, subnode, "rsrcs",
+							 rsrc_data, rsrc_size >> 2)) {
+					debug("Error reading rsrcs\n");
+					kfree(rsrc_data);
+					return CMD_RET_FAILURE;
+				}
+			}
+
+			prop = fdt_getprop(fdt, subnode, "pads", &pad_size);
+			if (!prop)
+				debug("No pads %s %d\n", fdt_get_name(fdt, subnode, NULL), pad_size);
+			if (pad_size > 0) {
+				pad_data = kmalloc(pad_size, __GFP_ZERO);
+				if (!pad_data) {
+					debug("No mem\n");
+					if (rsrc_data != NULL)
+						kfree(rsrc_data);
+					return CMD_RET_FAILURE;
+				}
+				if (fdtdec_get_int_array(fdt, subnode, "pads",
+							 pad_data, pad_size >> 2)) {
+					debug("Error reading pad\n");
+					kfree(pad_data);
+					kfree(rsrc_data);
+					return CMD_RET_FAILURE;
+				}
+			}
+
+			if ((rsrc_size <= 0) && (pad_size <= 0))
+				continue;
+
+			ret = partition_alloc(false, false, true, &pt);
+			if (ret)
+				goto free_data;
+
+			temp = cpu_to_fdt32(pt);
+			ret = fdt_setprop(fdt, subnode, "reg", &temp,
+					  sizeof(u32));
+			if (ret) {
+				printf("Could not set reg property %d\n", ret);
+				sc_rm_partition_free(-1, pt);
+				goto free_data;
+			}
+
+			if (rsrc_size > 0) {
+				for (i = 0; i < rsrc_size >> 2; i++) {
+					switch (rsrc_data[i]) {
+					case SC_R_MU_2A:
+					case SC_R_MU_3A:
+					case SC_R_MU_4A:
+						err = sc_pm_set_resource_power_mode(-1, rsrc_data[i], SC_PM_PW_MODE_ON);
+						if (err)
+							debug("power on resource %d, err %d\n", rsrc_data[i], err);
+						break;
+					default:
+						if (init_ignore_domu_power)
+							break;
+						err = sc_pm_set_resource_power_mode(-1, rsrc_data[i], SC_PM_PW_MODE_OFF);
+						if (err)
+							debug("power off resource %d, err %d\n", rsrc_data[i], err);
+						break;
+					}
+					if (sc_rm_is_resource_owned(-1, rsrc_data[i])) {
+						err = sc_rm_assign_resource(-1, pt, rsrc_data[i]);
+						debug("pt %d, resource %d, err %d\n", pt, rsrc_data[i], err);
+					}
+				}
+			}
+
+			if (pad_size > 0) {
+				for (i = 0; i < pad_size >> 2; i++) {
+					if (sc_rm_is_pad_owned(-1, pad_data[i])) {
+						err = sc_rm_assign_pad(-1, pt, pad_data[i]);
+						debug("pt %d, pad %d, err %d\n", pt, pad_data[i], err);
+					}
+				}
+			}
+
+			free_data:
+				if (pad_size > 0)
+					kfree(pad_data);
+				if (rsrc_size > 0) {
+					kfree(rsrc_data);
+					rsrc_data = NULL;
+				}
+		}
+
+	}
+
+	return 0;
+}
+
+static int do_part_free(int argc, char * const argv[])
+{
+	sc_rm_pt_t os_part;
+	int err;
+	int i;
+
+	if (argc == 0)
+		return CMD_RET_FAILURE;
+
+	os_part = simple_strtoul(argv[0], NULL, 10);
+
+	err = sc_rm_partition_free(-1, os_part);
+	if (err) {
+		printf("free partiiton %d err %d\n", os_part, err);
+		return CMD_RET_FAILURE;
+	}
+
+	for (i = 0; i < SC_MAX_PARTS; i++) {
+		if ((rm_part_data[i].self == os_part) && rm_part_data[i].used) {
+			rm_part_data[i].used = false;
+			break;
+		}
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_resource_assign(int argc, char * const argv[])
+{
+	sc_rm_pt_t os_part;
+	int err;
+	sc_rsrc_t resource;
+	sc_pad_t pad;
+	int i, flag;
+
+
+	if (argc < 3)
+		return CMD_RET_FAILURE;
+
+	os_part = simple_strtoul(argv[0], NULL, 10);
+	flag = simple_strtoul(argv[1], NULL, 10);
+	if (flag)
+		pad = simple_strtoul(argv[2], NULL, 10);
+	else
+		resource = simple_strtoul(argv[2], NULL, 10);
+
+	for (i = 0; i < SC_MAX_PARTS; i++) {
+		if ((rm_part_data[i].self == os_part) && rm_part_data[i].used)
+			break;
+	}
+
+	if (i == SC_MAX_PARTS) {
+		puts("Not valid partition\n");
+		return CMD_RET_FAILURE;
+	}
+
+	if (flag)
+		err = sc_rm_assign_pad(-1, os_part, pad);
+	else
+		err = sc_rm_assign_resource(-1, os_part, resource);
+	if (err) {
+		printf("assign resource/pad error %d\n", err);
+		return CMD_RET_FAILURE;
+	}
+
+	printf("%s: os_part, %d, %d\n", __func__, os_part,
+	       flag ? pad : resource);
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_part_list(int argc, char * const argv[])
+{
+	int i;
+
+	for (i = 0; i < SC_MAX_PARTS; i++) {
+		if (rm_part_data[i].used)
+			printf("part id: %d %d\n", rm_part_data[i].self,
+			       rm_part_data[i].parent);
+	}
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_part_test(int argc, char * const argv[])
+{
+	int err;
+	sc_rsrc_t resource;
+
+	if (argc < 1)
+		return CMD_RET_FAILURE;
+
+	resource = simple_strtoul(argv[0], NULL, 10);
+
+	err = sc_pm_set_resource_power_mode(-1, resource, SC_PM_PW_MODE_ON);
+	if (err == -EACCES)
+		puts("NO ACCESS\n");
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_scu_rm(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	if (!strcmp(argv[1], "alloc"))
+		return do_part_alloc(argc - 2, argv + 2);
+	else if (!strcmp(argv[1], "dtb"))
+		return do_part_dtb(argc - 2, argv + 2);
+	else if (!strcmp(argv[1], "free"))
+		return do_part_free(argc - 2, argv + 2);
+	else if (!strcmp(argv[1], "assign"))
+		return do_resource_assign(argc - 2, argv + 2);
+	else if (!strcmp(argv[1], "test"))
+		return do_part_test(argc - 2, argv + 2);
+	else if (!strcmp(argv[1], "print"))
+		return do_part_list(argc - 2, argv + 2);
+
+	return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+	scu_rm, CONFIG_SYS_MAXARGS, 1, do_scu_rm,
+	"scu partition function",
+	"\n"
+	"scu_rm alloc [isolated] [restricted] [grant]\n"
+	"scu_rm dtb [fdt]\n"
+	"scu_rm free pt\n"
+	"scu_rm assign pt 0 resource\n"
+	"scu_rm assign pt 1 pad\n"
+	"scu_rm test resource\n"
+	"scu_rm print\n"
+);
diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc.c b/arch/arm/mach-imx/imx8/snvs_security_sc.c
index 507b5b42314..ebba9f41b24 100644
--- a/arch/arm/mach-imx/imx8/snvs_security_sc.c
+++ b/arch/arm/mach-imx/imx8/snvs_security_sc.c
@@ -9,19 +9,28 @@
  *  - passive mode expecting VCC on the line: "_passive_vcc_"
  *  - passive mode expecting VCC on the line: "_passive_gnd_"
  *  - active mode: "_active_"
+ *
+ * WARNING:
+ * The silicon revision B0 of the iMX8QM and iMX8QXP have a bug in the SECO ROM:
+ * If the SSM of the SNVS changes state, the next call to SECO will trigger an
+ * integrity check of the SECO firmware which will fail due to incorrect CAAM
+ * keys hence the SECO will not respond to the call. The system will hang in
+ * this state until a watchdog resets the board.
  */
 
 #include <command.h>
 #include <log.h>
 #include <stddef.h>
 #include <common.h>
+#include <console.h>
 #include <asm/arch/sci/sci.h>
 #include <asm/arch-imx8/imx8-pins.h>
 #include <asm/arch-imx8/snvs_security_sc.h>
 #include <asm/global_data.h>
-
-/* Access to gd */
-DECLARE_GLOBAL_DATA_PTR;
+#include <asm/arch/sys_proto.h>
+#include "snvs_security_sc_conf_board.h"
+#include <imx_sip.h>
+#include <linux/arm-smccc.h>
 
 #define SC_WRITE_CONF 1
 
@@ -29,240 +38,17 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SRTC_EN 0x1
 #define DP_EN BIT(5)
 
-struct snvs_security_sc_conf {
-	struct snvs_hp_conf {
-		u32 lock;		/* HPLR - HP Lock */
-		u32 __cmd;		/* HPCOMR - HP Command */
-		u32 __ctl;		/* HPCR - HP Control */
-		u32 secvio_intcfg;	/* HPSICR - Security Violation Int
-					 * Config
-					 */
-		u32 secvio_ctl;		/* HPSVCR - Security Violation Control*/
-		u32 status;		/* HPSR - HP Status */
-		u32 secvio_status;	/* HPSVSR - Security Violation Status */
-		u32 __ha_counteriv;	/* High Assurance Counter IV */
-		u32 __ha_counter;		/* High Assurance Counter */
-		u32 __rtc_msb;		/* Real Time Clock/Counter MSB */
-		u32 __rtc_lsb;		/* Real Time Counter LSB */
-		u32 __time_alarm_msb;	/* Time Alarm MSB */
-		u32 __time_alarm_lsb;	/* Time Alarm LSB */
-	} hp;
-	struct snvs_lp_conf {
-		u32 lock;
-		u32 __ctl;
-		u32 __mstr_key_ctl;	/* Master Key Control */
-		u32 secvio_ctl;		/* Security Violation Control */
-		u32 tamper_filt_cfg;	/* Tamper Glitch Filters Configuration*/
-		u32 tamper_det_cfg;	/* Tamper Detectors Configuration */
-		u32 status;
-		u32 __srtc_msb;		/* Secure Real Time Clock/Counter MSB */
-		u32 __srtc_lsb;		/* Secure Real Time Clock/Counter LSB */
-		u32 __time_alarm;		/* Time Alarm */
-		u32 __smc_msb;		/* Secure Monotonic Counter MSB */
-		u32 __smc_lsb;		/* Secure Monotonic Counter LSB */
-		u32 __pwr_glitch_det;	/* Power Glitch Detector */
-		u32 __gen_purpose;
-		u8 __zmk[32];		/* Zeroizable Master Key */
-		u32 __rsvd0;
-		u32 __gen_purposes[4];	/* gp0_30 to gp0_33 */
-		u32 tamper_det_cfg2;	/* Tamper Detectors Configuration2 */
-		u32 tamper_det_status;	/* Tamper Detectors status */
-		u32 tamper_filt1_cfg;	/* Tamper Glitch Filter1 Configuration*/
-		u32 tamper_filt2_cfg;	/* Tamper Glitch Filter2 Configuration*/
-		u32 __rsvd1[4];
-		u32 act_tamper1_cfg;	/* Active Tamper1 Configuration */
-		u32 act_tamper2_cfg;	/* Active Tamper2 Configuration */
-		u32 act_tamper3_cfg;	/* Active Tamper3 Configuration */
-		u32 act_tamper4_cfg;	/* Active Tamper4 Configuration */
-		u32 act_tamper5_cfg;	/* Active Tamper5 Configuration */
-		u32 __rsvd2[3];
-		u32 act_tamper_ctl;	/* Active Tamper Control */
-		u32 act_tamper_clk_ctl;	/* Active Tamper Clock Control */
-		u32 act_tamper_routing_ctl1;/* Active Tamper Routing Control1 */
-		u32 act_tamper_routing_ctl2;/* Active Tamper Routing Control2 */
-	} lp;
-};
-
-static struct snvs_security_sc_conf snvs_default_config = {
-	.hp = {
-		.lock = 0x1f0703ff,
-		.secvio_ctl = 0x3000007f,
-	},
-	.lp = {
-		.lock = 0x1f0003ff,
-		.secvio_ctl = 0x36,
-		.tamper_filt_cfg = 0,
-		.tamper_det_cfg = 0x76, /* analogic tampers
-					 * + rollover tampers
-					 */
-		.tamper_det_cfg2 = 0,
-		.tamper_filt1_cfg = 0,
-		.tamper_filt2_cfg = 0,
-		.act_tamper1_cfg = 0,
-		.act_tamper2_cfg = 0,
-		.act_tamper3_cfg = 0,
-		.act_tamper4_cfg = 0,
-		.act_tamper5_cfg = 0,
-		.act_tamper_ctl = 0,
-		.act_tamper_clk_ctl = 0,
-		.act_tamper_routing_ctl1 = 0,
-		.act_tamper_routing_ctl2 = 0,
-	}
-};
-
-static struct snvs_security_sc_conf snvs_passive_vcc_config = {
-	.hp = {
-		.lock = 0x1f0703ff,
-		.secvio_ctl = 0x3000007f,
-	},
-	.lp = {
-		.lock = 0x1f0003ff,
-		.secvio_ctl = 0x36,
-		.tamper_filt_cfg = 0,
-		.tamper_det_cfg = 0x276, /* ET1 will trig on line at GND
-					  *  + analogic tampers
-					  *  + rollover tampers
-					  */
-		.tamper_det_cfg2 = 0,
-		.tamper_filt1_cfg = 0,
-		.tamper_filt2_cfg = 0,
-		.act_tamper1_cfg = 0,
-		.act_tamper2_cfg = 0,
-		.act_tamper3_cfg = 0,
-		.act_tamper4_cfg = 0,
-		.act_tamper5_cfg = 0,
-		.act_tamper_ctl = 0,
-		.act_tamper_clk_ctl = 0,
-		.act_tamper_routing_ctl1 = 0,
-		.act_tamper_routing_ctl2 = 0,
-	}
-};
-
-static struct snvs_security_sc_conf snvs_passive_gnd_config = {
-	.hp = {
-		.lock = 0x1f0703ff,
-		.secvio_ctl = 0x3000007f,
-	},
-	.lp = {
-		.lock = 0x1f0003ff,
-		.secvio_ctl = 0x36,
-		.tamper_filt_cfg = 0,
-		.tamper_det_cfg = 0xa76, /* ET1 will trig on line at VCC
-					  *  + analogic tampers
-					  *  + rollover tampers
-					  */
-		.tamper_det_cfg2 = 0,
-		.tamper_filt1_cfg = 0,
-		.tamper_filt2_cfg = 0,
-		.act_tamper1_cfg = 0,
-		.act_tamper2_cfg = 0,
-		.act_tamper3_cfg = 0,
-		.act_tamper4_cfg = 0,
-		.act_tamper5_cfg = 0,
-		.act_tamper_ctl = 0,
-		.act_tamper_clk_ctl = 0,
-		.act_tamper_routing_ctl1 = 0,
-		.act_tamper_routing_ctl2 = 0,
-	}
-};
-
-static struct snvs_security_sc_conf snvs_active_config = {
-	.hp = {
-		.lock = 0x1f0703ff,
-		.secvio_ctl = 0x3000007f,
-	},
-	.lp = {
-		.lock = 0x1f0003ff,
-		.secvio_ctl = 0x36,
-		.tamper_filt_cfg = 0x00800000, /* Enable filtering */
-		.tamper_det_cfg = 0x276, /* ET1 enabled + analogic tampers
-					  *  + rollover tampers
-					  */
-		.tamper_det_cfg2 = 0,
-		.tamper_filt1_cfg = 0,
-		.tamper_filt2_cfg = 0,
-		.act_tamper1_cfg = 0x84001111,
-		.act_tamper2_cfg = 0,
-		.act_tamper3_cfg = 0,
-		.act_tamper4_cfg = 0,
-		.act_tamper5_cfg = 0,
-		.act_tamper_ctl = 0x00010001,
-		.act_tamper_clk_ctl = 0,
-		.act_tamper_routing_ctl1 = 0x1,
-		.act_tamper_routing_ctl2 = 0,
-	}
-};
-
+#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO
 static struct snvs_security_sc_conf *get_snvs_config(void)
 {
 	return &snvs_default_config;
 }
 
-struct snvs_dgo_conf {
-	u32 tamper_offset_ctl;
-	u32 tamper_pull_ctl;
-	u32 tamper_ana_test_ctl;
-	u32 tamper_sensor_trim_ctl;
-	u32 tamper_misc_ctl;
-	u32 tamper_core_volt_mon_ctl;
-};
-
-static struct snvs_dgo_conf snvs_dgo_default_config = {
-	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
-};
-
-static struct snvs_dgo_conf snvs_dgo_passive_vcc_config = {
-	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
-	.tamper_pull_ctl = 0x00000001, /* Pull down ET1 */
-	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
-};
-
-static struct snvs_dgo_conf snvs_dgo_passive_gnd_config = {
-	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
-	.tamper_pull_ctl = 0x00000401, /* Pull up ET1 */
-	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
-};
-
-static struct snvs_dgo_conf snvs_dgo_active_config = {
-	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
-	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
-};
-
 static struct snvs_dgo_conf *get_snvs_dgo_config(void)
 {
 	return &snvs_dgo_default_config;
 }
-
-struct tamper_pin_cfg {
-	u32 pad;
-	u32 mux_conf;
-};
-
-static struct tamper_pin_cfg tamper_pin_list_default_config[] = {
-	{SC_P_CSI_D00, 0}, /* Tamp_Out0 */
-	{SC_P_CSI_D01, 0}, /* Tamp_Out1 */
-	{SC_P_CSI_D02, 0}, /* Tamp_Out2 */
-	{SC_P_CSI_D03, 0}, /* Tamp_Out3 */
-	{SC_P_CSI_D04, 0}, /* Tamp_Out4 */
-	{SC_P_CSI_D05, 0}, /* Tamp_In0 */
-	{SC_P_CSI_D06, 0}, /* Tamp_In1 */
-	{SC_P_CSI_D07, 0}, /* Tamp_In2 */
-	{SC_P_CSI_HSYNC, 0}, /* Tamp_In3 */
-	{SC_P_CSI_VSYNC, 0}, /* Tamp_In4 */
-};
-
-static struct tamper_pin_cfg tamper_pin_list_passive_vcc_config[] = {
-	{SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
-};
-
-static struct tamper_pin_cfg tamper_pin_list_passive_gnd_config[] = {
-	{SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
-};
-
-static struct tamper_pin_cfg tamper_pin_list_active_config[] = {
-	{SC_P_CSI_D00, 0x1a000060}, /* Tamp_Out0 */ /* Sel tamper + OD */
-	{SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
-};
+#endif
 
 #define TAMPER_PIN_LIST_CHOSEN tamper_pin_list_default_config
 
@@ -283,19 +69,19 @@ static u32 ptr_value(u32 *_p)
 }
 
 static int check_write_secvio_config(u32 id, u32 *_p1, u32 *_p2,
-				     u32 *_p3, u32 *_p4, u32 *_p5,
-				     u32 _cnt)
+					  u32 *_p3, u32 *_p4, u32 *_p5,
+					  u32 _cnt)
 {
-	int scierr = 0;
+	int err = 0;
 	u32 d1 = ptr_value(_p1);
 	u32 d2 = ptr_value(_p2);
 	u32 d3 = ptr_value(_p3);
 	u32 d4 = ptr_value(_p4);
 	u32 d5 = ptr_value(_p5);
 
-	scierr = sc_seco_secvio_config(-1, id, SC_WRITE_CONF, &d1, &d2, &d3,
+	err = sc_seco_secvio_config(-1, id, SC_WRITE_CONF, &d1, &d2, &d3,
 				       &d4, &d4, _cnt);
-	if (scierr != SC_ERR_NONE) {
+	if (err) {
 		printf("Failed to set secvio configuration\n");
 		debug("Failed to set conf id 0x%x with values ", id);
 		debug("0x%.8x 0x%.8x 0x%.8x 0x%.8x 0x%.8x (cnt: %d)\n",
@@ -315,7 +101,7 @@ static int check_write_secvio_config(u32 id, u32 *_p1, u32 *_p2,
 		*(u32 *)_p5 = d5;
 
 exit:
-	return scierr;
+	return err;
 }
 
 #define SC_CHECK_WRITE1(id, _p1) \
@@ -323,12 +109,13 @@ exit:
 
 static int apply_snvs_config(struct snvs_security_sc_conf *cnf)
 {
-	int scierr = 0;
+	int err = 0;
 
 	debug("%s\n", __func__);
 
 	debug("Applying config:\n"
 		  "\thp.lock = 0x%.8x\n"
+		  "\thp.secvio_intcfg = 0x%.8x\n"
 		  "\thp.secvio_ctl = 0x%.8x\n"
 		  "\tlp.lock = 0x%.8x\n"
 		  "\tlp.secvio_ctl = 0x%.8x\n"
@@ -347,6 +134,7 @@ static int apply_snvs_config(struct snvs_security_sc_conf *cnf)
 		  "\tlp.act_tamper_routing_ctl1 = 0x%.8x\n"
 		  "\tlp.act_tamper_routing_ctl2 = 0x%.8x\n",
 			cnf->hp.lock,
+			cnf->hp.secvio_intcfg,
 			cnf->hp.secvio_ctl,
 			cnf->lp.lock,
 			cnf->lp.secvio_ctl,
@@ -365,92 +153,101 @@ static int apply_snvs_config(struct snvs_security_sc_conf *cnf)
 			cnf->lp.act_tamper_routing_ctl1,
 			cnf->lp.act_tamper_routing_ctl2);
 
-	scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_filt_cfg),
+	err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_filt_cfg),
 					   &cnf->lp.tamper_filt_cfg,
 					   &cnf->lp.tamper_filt1_cfg,
 					   &cnf->lp.tamper_filt2_cfg, NULL,
 					   NULL, 3);
-	if (scierr != SC_ERR_NONE)
+	if (err)
 		goto exit;
 
 	/* Configure AT */
-	scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper1_cfg),
+	err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper1_cfg),
 					   &cnf->lp.act_tamper1_cfg,
 					   &cnf->lp.act_tamper2_cfg,
-					   &cnf->lp.act_tamper2_cfg,
-					   &cnf->lp.act_tamper2_cfg,
-					   &cnf->lp.act_tamper2_cfg, 5);
-	if (scierr != SC_ERR_NONE)
+					   &cnf->lp.act_tamper3_cfg,
+					   &cnf->lp.act_tamper4_cfg,
+					   &cnf->lp.act_tamper5_cfg, 5);
+	if (err)
 		goto exit;
 
 	/* Configure AT routing */
-	scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper_routing_ctl1),
+	err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper_routing_ctl1),
 					   &cnf->lp.act_tamper_routing_ctl1,
 					   &cnf->lp.act_tamper_routing_ctl2,
 					   NULL, NULL, NULL, 2);
-	if (scierr != SC_ERR_NONE)
+	if (err)
 		goto exit;
 
 	/* Configure AT frequency */
-	scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_clk_ctl),
+	err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_clk_ctl),
 				 &cnf->lp.act_tamper_clk_ctl);
-	if (scierr != SC_ERR_NONE)
+	if (err)
 		goto exit;
 
 	/* Activate the ATs */
-	scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_ctl),
+	err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_ctl),
 				 &cnf->lp.act_tamper_ctl);
-	if (scierr != SC_ERR_NONE)
+	if (err)
 		goto exit;
 
 	/* Activate the detectors */
-	scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_cfg),
+	err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_cfg),
 					   &cnf->lp.tamper_det_cfg,
 					   &cnf->lp.tamper_det_cfg2, NULL, NULL,
 					   NULL, 2);
-	if (scierr != SC_ERR_NONE)
+	if (err)
 		goto exit;
 
 	/* Configure LP secvio */
-	scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.secvio_ctl),
+	err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.secvio_ctl),
 				 &cnf->lp.secvio_ctl);
-	if (scierr != SC_ERR_NONE)
+	if (err)
 		goto exit;
 
 	/* Configure HP secvio */
-	scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.secvio_ctl),
+	err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.secvio_ctl),
 				 &cnf->hp.secvio_ctl);
-	if (scierr != SC_ERR_NONE)
+	if (err)
 		goto exit;
 
-	/* Lock access */
-	scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.lock), &cnf->hp.lock);
-	if (scierr != SC_ERR_NONE)
+	err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.secvio_intcfg),
+				 &cnf->hp.secvio_intcfg);
+	if (err)
 		goto exit;
 
-	scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.lock), &cnf->lp.lock);
-	if (scierr != SC_ERR_NONE)
-		goto exit;
+	/* Lock access */
+	if (cnf->hp.lock) {
+		err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.lock), &cnf->hp.lock);
+		if (err)
+			goto exit;
+	}
+
+	if (cnf->lp.lock) {
+		err = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.lock), &cnf->lp.lock);
+		if (err)
+			goto exit;
+	}
 
 exit:
-	return (scierr == SC_ERR_NONE) ? 0 : -EIO;
+	return err;
 }
 
 static int dgo_write(u32 _id, u8 _access, u32 *_pdata)
 {
-	int scierr = sc_seco_secvio_dgo_config(-1, _id, _access, _pdata);
+	int err = sc_seco_secvio_dgo_config(-1, _id, _access, _pdata);
 
-	if (scierr != SC_ERR_NONE) {
+	if (err) {
 		printf("Failed to set dgo configuration\n");
 		debug("Failed to set conf id 0x%x : 0x%.8x", _id, *_pdata);
 	}
 
-	return scierr;
+	return err;
 }
 
 static int apply_snvs_dgo_config(struct snvs_dgo_conf *cnf)
 {
-	int scierr = 0;
+	int err = 0;
 
 	debug("%s\n", __func__);
 
@@ -468,99 +265,79 @@ static int apply_snvs_dgo_config(struct snvs_dgo_conf *cnf)
 			cnf->tamper_misc_ctl,
 			cnf->tamper_core_volt_mon_ctl);
 
-	dgo_write(0x04, 1, &cnf->tamper_offset_ctl);
-	if (scierr != SC_ERR_NONE)
+	err = dgo_write(0x04, 1, &cnf->tamper_offset_ctl);
+	if (err)
 		goto exit;
 
-	dgo_write(0x14, 1, &cnf->tamper_pull_ctl);
-	if (scierr != SC_ERR_NONE)
+	err = dgo_write(0x14, 1, &cnf->tamper_pull_ctl);
+	if (err)
 		goto exit;
 
-	dgo_write(0x24, 1, &cnf->tamper_ana_test_ctl);
-	if (scierr != SC_ERR_NONE)
+	err = dgo_write(0x24, 1, &cnf->tamper_ana_test_ctl);
+	if (err)
 		goto exit;
 
-	dgo_write(0x34, 1, &cnf->tamper_sensor_trim_ctl);
-	if (scierr != SC_ERR_NONE)
+	err = dgo_write(0x34, 1, &cnf->tamper_sensor_trim_ctl);
+	if (err)
 		goto exit;
 
-	dgo_write(0x54, 1, &cnf->tamper_core_volt_mon_ctl);
-	if (scierr != SC_ERR_NONE)
+	err = dgo_write(0x54, 1, &cnf->tamper_core_volt_mon_ctl);
+	if (err)
 		goto exit;
 
 	/* Last as it could lock the writes */
-	dgo_write(0x44, 1, &cnf->tamper_misc_ctl);
-	if (scierr != SC_ERR_NONE)
+	err = dgo_write(0x44, 1, &cnf->tamper_misc_ctl);
+	if (err)
 		goto exit;
 
 exit:
-	return (scierr == SC_ERR_NONE) ? 0 : -EIO;
+	return err;
 }
 
 static int pad_write(u32 _pad, u32 _value)
 {
-	int scierr = sc_pad_set(-1, _pad, _value);
+	int err = sc_pad_set(-1, _pad, _value);
 
-	if (scierr != SC_ERR_NONE) {
+	if (err) {
 		printf("Failed to set pad configuration\n");
 		debug("Failed to set conf pad 0x%x : 0x%.8x", _pad, _value);
 	}
 
-	return scierr;
+	return err;
+}
+
+static int pad_read(u32 _pad, u32 *_value)
+{
+	int err = sc_pad_get(-1, _pad, _value);
+
+	if (err) {
+		printf("Failed to get pad configuration\n");
+		printf("Failed to get conf pad %d", _pad);
+	}
+
+	return err;
 }
 
 static int apply_tamper_pin_list_config(struct tamper_pin_cfg *confs, u32 size)
 {
-	int scierr = 0;
+	int err = 0;
 	u32 idx;
 
 	debug("%s\n", __func__);
 
 	for (idx = 0; idx < size; idx++) {
+		if (confs[idx].pad == TAMPER_NOT_DEFINED)
+			continue;
+
 		debug("\t idx %d: pad %d: 0x%.8x\n", idx, confs[idx].pad,
 		      confs[idx].mux_conf);
-		pad_write(confs[idx].pad, 3 << 30 | confs[idx].mux_conf);
-		if (scierr != SC_ERR_NONE)
+		err = pad_write(confs[idx].pad, 3 << 30 | confs[idx].mux_conf);
+		if (err)
 			goto exit;
 	}
 
 exit:
-	return (scierr == SC_ERR_NONE) ? 0 : -EIO;
-}
-
-int examples(void)
-{
-	u32 size;
-	struct snvs_security_sc_conf *snvs_conf;
-	struct snvs_dgo_conf *snvs_dgo_conf;
-	struct tamper_pin_cfg *tamper_pin_conf;
-
-	/* Caller */
-	snvs_conf = get_snvs_config();
-	snvs_dgo_conf = get_snvs_dgo_config();
-	tamper_pin_conf = get_tamper_pin_cfg_list(&size);
-
-	/* Default */
-	snvs_conf = &snvs_default_config;
-	snvs_dgo_conf = &snvs_dgo_default_config;
-	tamper_pin_conf = tamper_pin_list_default_config;
-
-	/* Passive tamper expecting VCC on the line */
-	snvs_conf = &snvs_passive_vcc_config;
-	snvs_dgo_conf = &snvs_dgo_passive_vcc_config;
-	tamper_pin_conf = tamper_pin_list_passive_vcc_config;
-
-	/* Passive tamper expecting GND on the line */
-	snvs_conf = &snvs_passive_gnd_config;
-	snvs_dgo_conf = &snvs_dgo_passive_gnd_config;
-	tamper_pin_conf = tamper_pin_list_passive_gnd_config;
-
-	/* Active tamper */
-	snvs_conf = &snvs_active_config;
-	snvs_dgo_conf = &snvs_dgo_active_config;
-	tamper_pin_conf = tamper_pin_list_active_config;
-
-	return !snvs_conf + !snvs_dgo_conf + !tamper_pin_conf;
+	return err;
 }
 
 #ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO
@@ -606,6 +383,7 @@ exit:
 static char snvs_cfg_help_text[] =
 	"snvs_cfg\n"
 	"\thp.lock\n"
+	"\thp.secvio_intcfg\n"
 	"\thp.secvio_ctl\n"
 	"\tlp.lock\n"
 	"\tlp.secvio_ctl\n"
@@ -626,7 +404,7 @@ static char snvs_cfg_help_text[] =
 	"\n"
 	"ALL values should be in hexadecimal format";
 
-#define NB_REGISTERS 18
+#define NB_REGISTERS 19
 static int do_snvs_cfg(struct cmd_tbl *cmdtp, int flag, int argc,
 		       char *const argv[])
 {
@@ -639,6 +417,7 @@ static int do_snvs_cfg(struct cmd_tbl *cmdtp, int flag, int argc,
 		return CMD_RET_USAGE;
 
 	conf.hp.lock = hextoul(argv[++idx], NULL);
+	conf.hp.secvio_intcfg = hextoul(argv[++idx], NULL);
 	conf.hp.secvio_ctl = hextoul(argv[++idx], NULL);
 	conf.lp.lock = hextoul(argv[++idx], NULL);
 	conf.lp.secvio_ctl = hextoul(argv[++idx], NULL);
@@ -742,8 +521,6 @@ U_BOOT_CMD(tamper_pin_cfg,
 
 static char snvs_clear_status_help_text[] =
 	"snvs_clear_status\n"
-	"\tHPSR\n"
-	"\tHPSVSR\n"
 	"\tLPSR\n"
 	"\tLPTDSR\n"
 	"\n"
@@ -753,7 +530,7 @@ static char snvs_clear_status_help_text[] =
 static int do_snvs_clear_status(struct cmd_tbl *cmdtp, int flag, int argc,
 				char *const argv[])
 {
-	int scierr = 0;
+	int err = 0;
 	u32 idx = 0;
 
 	struct snvs_security_sc_conf conf = {0};
@@ -764,20 +541,20 @@ static int do_snvs_clear_status(struct cmd_tbl *cmdtp, int flag, int argc,
 	conf.lp.status = hextoul(argv[++idx], NULL);
 	conf.lp.tamper_det_status = hextoul(argv[++idx], NULL);
 
-	scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.status),
+	err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.status),
 					   &conf.lp.status, NULL, NULL, NULL,
 					   NULL, 1);
-	if (scierr != SC_ERR_NONE)
+	if (err)
 		goto exit;
 
-	scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_status),
+	err = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_status),
 					   &conf.lp.tamper_det_status, NULL,
 					   NULL, NULL, NULL, 1);
-	if (scierr != SC_ERR_NONE)
+	if (err)
 		goto exit;
 
 exit:
-	return (scierr == SC_ERR_NONE) ? 0 : 1;
+	return err;
 }
 
 U_BOOT_CMD(snvs_clear_status,
@@ -793,23 +570,11 @@ static char snvs_sec_status_help_text[] =
 static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc,
 			      char *const argv[])
 {
-	int scierr;
+	int err;
 	u32 idx;
-
+	u32 nb_pins;
 	u32 data[5];
-
-	u32 pads[] = {
-		SC_P_CSI_D00,
-		SC_P_CSI_D01,
-		SC_P_CSI_D02,
-		SC_P_CSI_D03,
-		SC_P_CSI_D04,
-		SC_P_CSI_D05,
-		SC_P_CSI_D06,
-		SC_P_CSI_D07,
-		SC_P_CSI_HSYNC,
-		SC_P_CSI_VSYNC,
-	};
+	struct tamper_pin_cfg *pin_cfg_list = get_tamper_pin_cfg_list(&nb_pins);
 
 	u32 fuses[] = {
 		14,
@@ -861,14 +626,17 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc,
 
 	/* Pins */
 	printf("Pins:\n");
-	for (idx = 0; idx < ARRAY_SIZE(pads); idx++) {
-		u8 pad_id = pads[idx];
+	for (idx = 0; idx < nb_pins; idx++) {
+		struct tamper_pin_cfg *cfg = &pin_cfg_list[idx];
 
-		scierr = sc_pad_get(-1, pad_id, &data[0]);
-		if (scierr == 0)
-			printf("\t- Pin %d: %.8x\n", pad_id, data[0]);
+		if (cfg->pad == TAMPER_NOT_DEFINED)
+			continue;
+
+		err = sc_pad_get(-1, cfg->pad, &data[0]);
+		if (err == 0)
+			printf("\t- Pin %d: %.8x\n", cfg->pad, data[0]);
 		else
-			printf("Failed to read Pin %d\n", pad_id);
+			printf("Failed to read Pin %d\n", cfg->pad);
 	}
 
 	/* Fuses */
@@ -876,8 +644,8 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc,
 	for (idx = 0; idx < ARRAY_SIZE(fuses); idx++) {
 		u32 fuse_id = fuses[idx];
 
-		scierr = sc_misc_otp_fuse_read(-1, fuse_id, &data[0]);
-		if (scierr == 0)
+		err = sc_misc_otp_fuse_read(-1, fuse_id, &data[0]);
+		if (err == 0)
 			printf("\t- Fuse %d: %.8x\n", fuse_id, data[0]);
 		else
 			printf("Failed to read Fuse %d\n", fuse_id);
@@ -888,10 +656,10 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc,
 	for (idx = 0; idx < ARRAY_SIZE(snvs); idx++) {
 		struct snvs_reg *reg = &snvs[idx];
 
-		scierr = sc_seco_secvio_config(-1, reg->id, 0, &data[0],
+		err = sc_seco_secvio_config(-1, reg->id, 0, &data[0],
 					       &data[1], &data[2], &data[3],
 					       &data[4], reg->nb);
-		if (scierr == 0) {
+		if (err == 0) {
 			int subidx;
 
 			printf("\t- SNVS %.2x(%d):", reg->id, reg->nb);
@@ -908,8 +676,8 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc,
 	for (idx = 0; idx < ARRAY_SIZE(dgo); idx++) {
 		u8 dgo_id = dgo[idx];
 
-		scierr = sc_seco_secvio_dgo_config(-1, dgo_id, 0, &data[0]);
-		if (scierr == 0)
+		err = sc_seco_secvio_dgo_config(-1, dgo_id, 0, &data[0]);
+		if (err == 0)
 			printf("\t- DGO %.2x: %.8x\n", dgo_id, data[0]);
 		else
 			printf("Failed to read DGO %d\n", dgo_id);
@@ -923,3 +691,113 @@ U_BOOT_CMD(snvs_sec_status,
 	   "tamper pin configuration",
 	   snvs_sec_status_help_text
 );
+
+static char gpio_conf_help_text[] =
+	"gpio_conf <pad> <hexval>\n"
+	"Configure the GPIO of an IOMUX:\n"
+	" - pad:\n"
+	" - hexval:";
+
+static int do_gpio_conf(struct cmd_tbl *cmdtp, int flag, int argc,
+			char *const argv[])
+{
+	int err = -EIO;
+	u32 pad, val, valcheck;
+
+	pad = simple_strtoul(argv[1], NULL, 10);
+	val = simple_strtoul(argv[2], NULL, 16);
+
+	printf("Configuring GPIO %d with %x\n", pad, val);
+
+	err = pad_write(pad, 3 << 30 | val);
+	if (err) {
+		printf("Error writing conf\n");
+		goto exit;
+	}
+
+	err = pad_read(pad, &valcheck);
+	if (err) {
+		printf("Error reading conf\n");
+		goto exit;
+	}
+
+	if (valcheck != val) {
+		printf("Error: configured %x instead of %x\n", valcheck, val);
+		goto exit;
+	}
+
+exit:
+	return err;
+}
+
+U_BOOT_CMD(gpio_conf,
+	   3, 1, do_gpio_conf,
+	   "gpio configuration",
+	   gpio_conf_help_text
+);
+
+static
+int do_set_fips_mode(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	u8 fips_mode = 0;
+	struct arm_smccc_res res;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	fips_mode = simple_strtoul(argv[1], NULL, 16);
+
+	if (argc == 2) {
+		printf("Warning: Setting FIPS mode [%x] will burn a fuse and\n"
+		       "is permanent\n"
+		       "Really perform this fuse programming? <y/N>\n",
+		       fips_mode);
+
+		/* If the user does not answer yes (1), we return */
+		if (confirm_yesno() != 1)
+			return 0;
+	}
+
+	if (argc == 3 && !(argv[2][0] == '-' && argv[2][1] == 'y'))
+		return CMD_RET_USAGE;
+
+	arm_smccc_smc(IMX_SIP_FIPS_CONFIG, IMX_SIP_FIPS_CONFIG_SET,
+		      fips_mode, 0, 0, 0, 0, 0, &res);
+	if (res.a0) {
+		printf("Failed to set fips mode %d. err: %ld\n",
+		       fips_mode, res.a0);
+	}
+
+	return (res.a0) ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(set_fips_mode,
+	   3, 0, do_set_fips_mode,
+	   "Set FIPS mode",
+	   "<mode in hex> [-y] \n"
+	   "    The SoC will be configured in FIPS <mode> (PERMANENT)\n"
+	   "    If \"-y\" is not passed, the function will ask for validation\n"
+	   "ex: set_fips_mode 1\n"
+);
+
+static
+int do_check_fips_mode(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	int err = -EIO;
+	u32 fuse_value = 0;
+
+	/* The FIPS bit is the bit 3 in the word 0xA */
+	err = sc_misc_otp_fuse_read(-1, 0xA, &fuse_value);
+	if (err)
+		return err;
+
+	printf("FIPS mode: %x\n", fuse_value >> 3 & 0x1);
+
+	return 0;
+}
+
+U_BOOT_CMD(check_fips_mode,
+	   1, 0, do_check_fips_mode,
+	   "Display the FIPS mode of the SoC by reading fuse 0xA, bit 3",
+	   NULL
+);
diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc_conf.h b/arch/arm/mach-imx/imx8/snvs_security_sc_conf.h
new file mode 100644
index 00000000000..79c5ed57c3a
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/snvs_security_sc_conf.h
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP.
+ */
+
+#ifndef SNVS_SECURITY_SC_CONF_H_
+#define SNVS_SECURITY_SC_CONF_H_
+
+/*
+ * File to list different example of tamper configuration:
+ * - default
+ * - passive to ground
+ * - passive to vcc
+ * - active
+ *
+ * for the different platform supported:
+ * - imx8qxp-mek
+ * - imx8qm-mek
+ * - imx8dxl-evk
+ */
+
+#include <asm/arch-imx8/imx8-pins.h>
+
+/* Definition of the structures */
+
+struct snvs_security_sc_conf {
+	struct snvs_hp_conf {
+		u32 lock;		/* HPLR - HP Lock */
+		u32 __cmd;		/* HPCOMR - HP Command */
+		u32 __ctl;		/* HPCR - HP Control */
+		u32 secvio_intcfg;	/* HPSICR - Security Violation Int
+					 * Config
+					 */
+		u32 secvio_ctl;		/* HPSVCR - Security Violation Control*/
+		u32 status;		/* HPSR - HP Status */
+		u32 secvio_status;	/* HPSVSR - Security Violation Status */
+		u32 __ha_counteriv;	/* High Assurance Counter IV */
+		u32 __ha_counter;		/* High Assurance Counter */
+		u32 __rtc_msb;		/* Real Time Clock/Counter MSB */
+		u32 __rtc_lsb;		/* Real Time Counter LSB */
+		u32 __time_alarm_msb;	/* Time Alarm MSB */
+		u32 __time_alarm_lsb;	/* Time Alarm LSB */
+	} hp;
+	struct snvs_lp_conf {
+		u32 lock;
+		u32 __ctl;
+		u32 __mstr_key_ctl;	/* Master Key Control */
+		u32 secvio_ctl;		/* Security Violation Control */
+		u32 tamper_filt_cfg;	/* Tamper Glitch Filters Configuration*/
+		u32 tamper_det_cfg;	/* Tamper Detectors Configuration */
+		u32 status;
+		u32 __srtc_msb;		/* Secure Real Time Clock/Counter MSB */
+		u32 __srtc_lsb;		/* Secure Real Time Clock/Counter LSB */
+		u32 __time_alarm;		/* Time Alarm */
+		u32 __smc_msb;		/* Secure Monotonic Counter MSB */
+		u32 __smc_lsb;		/* Secure Monotonic Counter LSB */
+		u32 __pwr_glitch_det;	/* Power Glitch Detector */
+		u32 __gen_purpose;
+		u8 __zmk[32];		/* Zeroizable Master Key */
+		u32 __rsvd0;
+		u32 __gen_purposes[4];	/* gp0_30 to gp0_33 */
+		u32 tamper_det_cfg2;	/* Tamper Detectors Configuration2 */
+		u32 tamper_det_status;	/* Tamper Detectors status */
+		u32 tamper_filt1_cfg;	/* Tamper Glitch Filter1 Configuration*/
+		u32 tamper_filt2_cfg;	/* Tamper Glitch Filter2 Configuration*/
+		u32 __rsvd1[4];
+		u32 act_tamper1_cfg;	/* Active Tamper1 Configuration */
+		u32 act_tamper2_cfg;	/* Active Tamper2 Configuration */
+		u32 act_tamper3_cfg;	/* Active Tamper3 Configuration */
+		u32 act_tamper4_cfg;	/* Active Tamper4 Configuration */
+		u32 act_tamper5_cfg;	/* Active Tamper5 Configuration */
+		u32 __rsvd2[3];
+		u32 act_tamper_ctl;	/* Active Tamper Control */
+		u32 act_tamper_clk_ctl;	/* Active Tamper Clock Control */
+		u32 act_tamper_routing_ctl1;/* Active Tamper Routing Control1 */
+		u32 act_tamper_routing_ctl2;/* Active Tamper Routing Control2 */
+	} lp;
+};
+
+struct snvs_dgo_conf {
+	u32 tamper_offset_ctl;
+	u32 tamper_pull_ctl;
+	u32 tamper_ana_test_ctl;
+	u32 tamper_sensor_trim_ctl;
+	u32 tamper_misc_ctl;
+	u32 tamper_core_volt_mon_ctl;
+};
+
+struct tamper_pin_cfg {
+	u32 pad;
+	u32 mux_conf;
+};
+
+#define TAMPER_NOT_DEFINED -1
+#define TAMPER_NO_IOMUX TAMPER_NOT_DEFINED
+
+/* There is 10 tampers and the list start at 1 */
+enum EXT_TAMPER {
+	EXT_TAMPER_ET1 = 0,
+	EXT_TAMPER_ET2 = 1,
+	EXT_TAMPER_ET3 = 2,
+	EXT_TAMPER_ET4 = 3,
+	EXT_TAMPER_ET5 = 4,
+	EXT_TAMPER_ET6 = 5,
+	EXT_TAMPER_ET7 = 6,
+	EXT_TAMPER_ET8 = 7,
+	EXT_TAMPER_ET9 = 8,
+	EXT_TAMPER_ET10 = 9,
+};
+
+enum ACT_TAMPER {
+	ACT_TAMPER_AT1 = EXT_TAMPER_ET6,
+	ACT_TAMPER_AT2 = EXT_TAMPER_ET7,
+	ACT_TAMPER_AT3 = EXT_TAMPER_ET8,
+	ACT_TAMPER_AT4 = EXT_TAMPER_ET9,
+	ACT_TAMPER_AT5 = EXT_TAMPER_ET10,
+};
+
+#endif /* SNVS_SECURITY_SC_CONF_H_ */
diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8dxl_evk.h b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8dxl_evk.h
new file mode 100644
index 00000000000..2b4e6bc27f4
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8dxl_evk.h
@@ -0,0 +1,168 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP.
+ */
+
+#ifndef SNVS_SECURITY_SC_CONF_8DXL_EVK_H_
+#define SNVS_SECURITY_SC_CONF_8DXL_EVK_H_
+
+#include "snvs_security_sc_conf.h"
+
+static __maybe_unused struct snvs_security_sc_conf snvs_default_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x76, /* analogic tampers
+					 * + rollover tampers
+					 */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_default_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+};
+
+static __maybe_unused struct snvs_security_sc_conf snvs_passive_vcc_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x076, /* analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0x11, /* ET3 + ET7 will trig on line at GND*/
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_security_sc_conf snvs_passive_gnd_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x076, /* analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0x110011, /* ET3 + ET7 will trig on line at
+					      * VCC
+					      */
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_security_sc_conf snvs_active_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x076, /* analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0x10, /* Enable ET7 tamper */
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0x80, /* Enable filtering */
+		.act_tamper1_cfg = 0x84001111,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0x10001,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0x1000000, /* Route AT1 to ET 7 */
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_vcc_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+	.tamper_pull_ctl = 0x00000044, /* Pull down IN4 and OUT0 */
+	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_gnd_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+	.tamper_pull_ctl = 0x00011044, /* Pull down IN4 and OUT0 */
+	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_active_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
+};
+
+static struct tamper_pin_cfg tamper_pin_list_default_config[] = {
+	{SC_P_SNVS_TAMPER_IN0, 0}, /* Tamp_In0 */
+	{SC_P_SNVS_TAMPER_IN1, 0}, /* Tamp_In1 */
+	{SC_P_SNVS_TAMPER_IN2, 0}, /* Tamp_In2 */
+	{SC_P_SNVS_TAMPER_IN3, 0}, /* Tamp_In3 */
+	{TAMPER_NO_IOMUX, 0}, /* Tamp_In4 */
+	{TAMPER_NO_IOMUX, 0}, /* Tamp_Out0 */
+	{SC_P_SNVS_TAMPER_OUT1, 0}, /* Tamp_Out1 */
+	{SC_P_SNVS_TAMPER_OUT2, 0}, /* Tamp_Out2 */
+	{SC_P_SNVS_TAMPER_OUT3, 0}, /* Tamp_Out3 */
+	{SC_P_SNVS_TAMPER_OUT4, 0}, /* Tamp_Out4 */
+};
+
+static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_vcc_config[] = {
+};
+
+static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_gnd_config[] = {
+};
+
+static __maybe_unused struct tamper_pin_cfg tamper_pin_list_active_config[] = {
+};
+
+#endif /* SNVS_SECURITY_SC_CONF_8DXL_EVK_H_ */
diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qm_mek.h b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qm_mek.h
new file mode 100644
index 00000000000..20dad8b126b
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qm_mek.h
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP.
+ */
+
+#ifndef SNVS_SECURITY_SC_CONF_8QM_MEK_H_
+#define SNVS_SECURITY_SC_CONF_8QM_MEK_H_
+
+#include "snvs_security_sc_conf.h"
+
+/* Configuration */
+
+static __maybe_unused struct snvs_security_sc_conf snvs_default_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x76, /* analogic tampers
+					 * + rollover tampers
+					 */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_default_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+};
+
+static __maybe_unused struct snvs_security_sc_conf snvs_passive_vcc_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x276, /* ET1 will trig on line at GND
+					  *  + analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_security_sc_conf snvs_passive_gnd_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0xa76, /* ET1 will trig on line at VCC
+					  *  + analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_security_sc_conf snvs_active_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0x00800000, /* Enable filtering */
+		.tamper_det_cfg = 0x276, /* ET1 enabled + analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0x84001111,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0x00010001,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0x1,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_vcc_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+	.tamper_pull_ctl = 0x00000001, /* Pull down ET1 */
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_gnd_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+	.tamper_pull_ctl = 0x00000401, /* Pull up ET1 */
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_active_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+};
+
+static struct tamper_pin_cfg tamper_pin_list_default_config[] = {
+};
+
+static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_vcc_config[] = {
+};
+
+static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_gnd_config[] = {
+};
+
+static __maybe_unused struct tamper_pin_cfg tamper_pin_list_active_config[] = {
+};
+
+#endif /* SNVS_SECURITY_SC_CONF_8QM_MEK_H_ */
diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qxp_mek.h b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qxp_mek.h
new file mode 100644
index 00000000000..2cd3461008d
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qxp_mek.h
@@ -0,0 +1,172 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP.
+ */
+
+#ifndef SNVS_SECURITY_SC_CONF_8QXP_MEK_H_
+#define SNVS_SECURITY_SC_CONF_8QXP_MEK_H_
+
+#include "snvs_security_sc_conf.h"
+
+static __maybe_unused struct snvs_security_sc_conf snvs_default_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x76, /* analogic tampers
+					 * + rollover tampers
+					 */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_default_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+};
+
+static __maybe_unused struct snvs_security_sc_conf snvs_passive_vcc_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x276, /* ET1 will trig on line at GND
+					  *  + analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_security_sc_conf snvs_passive_gnd_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0xa76, /* ET1 will trig on line at VCC
+					  *  + analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_security_sc_conf snvs_active_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0x00800000, /* Enable filtering */
+		.tamper_det_cfg = 0x276, /* ET1 enabled + analogic tampers
+					  *  + rollover tampers
+					  */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0x84001111,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0x00010001,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0x1,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_vcc_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+	.tamper_pull_ctl = 0x00000001, /* Pull down ET1 */
+	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_gnd_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+	.tamper_pull_ctl = 0x00000401, /* Pull up ET1 */
+	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_active_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+	.tamper_ana_test_ctl = 0x20000000, /* Enable tamper */
+};
+
+static struct tamper_pin_cfg tamper_pin_list_default_config[] = {
+	{SC_P_CSI_D05, 0}, /* Tamp_In0 */
+	{SC_P_CSI_D06, 0}, /* Tamp_In1 */
+	{SC_P_CSI_D07, 0}, /* Tamp_In2 */
+	{SC_P_CSI_HSYNC, 0}, /* Tamp_In3 */
+	{SC_P_CSI_VSYNC, 0}, /* Tamp_In4 */
+	{SC_P_CSI_D00, 0}, /* Tamp_Out0 */
+	{SC_P_CSI_D01, 0}, /* Tamp_Out1 */
+	{SC_P_CSI_D02, 0}, /* Tamp_Out2 */
+	{SC_P_CSI_D03, 0}, /* Tamp_Out3 */
+	{SC_P_CSI_D04, 0}, /* Tamp_Out4 */
+};
+
+static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_vcc_config[] = {
+	{SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
+};
+
+static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_gnd_config[] = {
+	{SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
+};
+
+static __maybe_unused struct tamper_pin_cfg tamper_pin_list_active_config[] = {
+	{SC_P_CSI_D00, 0x1a000060}, /* Tamp_Out0 */ /* Sel tamper + OD */
+	{SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */
+};
+
+#endif /* SNVS_SECURITY_SC_CONF_8QXP_MEK_H_ */
diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc_conf_board.h b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_board.h
new file mode 100644
index 00000000000..250952b7df6
--- /dev/null
+++ b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_board.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP.
+ */
+
+#ifndef SNVS_SECURITY_SC_CONF_BOARD_H_
+#define SNVS_SECURITY_SC_CONF_BOARD_H_
+
+#ifdef CONFIG_TARGET_IMX8QM_MEK
+#include "snvs_security_sc_conf_8qm_mek.h"
+#elif CONFIG_TARGET_IMX8QXP_MEK
+#include "snvs_security_sc_conf_8qxp_mek.h"
+#elif CONFIG_TARGET_IMX8DXL_EVK
+#include "snvs_security_sc_conf_8dxl_evk.h"
+#else
+
+#include "snvs_security_sc_conf.h"
+
+/* Default configuration of the tamper for all boards */
+static __maybe_unused struct snvs_security_sc_conf snvs_default_config = {
+	.hp = {
+		.lock = 0x1f0703ff,
+		.secvio_intcfg = 0x8000002f,
+		.secvio_ctl = 0xC000007f,
+	},
+	.lp = {
+		.lock = 0x1f0003ff,
+		.secvio_ctl = 0x36,
+		.tamper_filt_cfg = 0,
+		.tamper_det_cfg = 0x76, /* analogic tampers
+					 * + rollover tampers
+					 */
+		.tamper_det_cfg2 = 0,
+		.tamper_filt1_cfg = 0,
+		.tamper_filt2_cfg = 0,
+		.act_tamper1_cfg = 0,
+		.act_tamper2_cfg = 0,
+		.act_tamper3_cfg = 0,
+		.act_tamper4_cfg = 0,
+		.act_tamper5_cfg = 0,
+		.act_tamper_ctl = 0,
+		.act_tamper_clk_ctl = 0,
+		.act_tamper_routing_ctl1 = 0,
+		.act_tamper_routing_ctl2 = 0,
+	}
+};
+
+static __maybe_unused struct snvs_dgo_conf snvs_dgo_default_config = {
+	.tamper_misc_ctl = 0x80000000, /* Lock the DGO */
+};
+
+static struct tamper_pin_cfg tamper_pin_list_default_config[] = {0};
+
+#endif
+
+#endif /* SNVS_SECURITY_SC_CONF_BOARD_H_ */
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index fae70499953..a225a9784f4 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -8,14 +8,17 @@ config IMX8M
 config IMX8MQ
 	bool
 	select IMX8M
+	select ARMV8_SPL_EXCEPTION_VECTORS
 
 config IMX8MM
 	bool
 	select IMX8M
+	select ARMV8_SPL_EXCEPTION_VECTORS
 
 config IMX8MN
 	bool
 	select IMX8M
+	select ARMV8_SPL_EXCEPTION_VECTORS
 
 config IMX8MP
 	bool
@@ -24,6 +27,33 @@ config IMX8MP
 config SYS_SOC
 	default "imx8m"
 
+config SECONDARY_BOOT_SECTOR_OFFSET
+	hex "SD/MMC sector offset used for ROM secondary boot"
+	default 0x0
+	depends on IMX8MQ || IMX8MM
+	help
+	  Set the sector offset to non-zero value in SPL used for
+	  secondary boot image. This value should be same as the
+	  firstSectorNumber in secondary image table.
+
+config SECURE_STICKY_BITS_LOCKUP
+	bool "Enable workaround to fix sticky bits lock up issue"
+	depends on IMX8MQ && IMX_HAB
+	default y
+
+config IMX_UNIQUE_ID
+	hex "Enable workaround to fix sticky bits lock up issue"
+	depends on IMX8MQ && IMX_HAB && !SECURE_STICKY_BITS_LOCKUP
+	default 0x0
+
+config IMX8M_MCU_RDC_START_CONFIG_ADDR
+	hex "Start address of mcu rdc config when mcu starts"
+	default 0x186000
+
+config IMX8M_MCU_RDC_STOP_CONFIG_ADDR
+	hex "Start address of mcu rdc config when mcu stops"
+	default 0x187000
+
 choice
 	prompt "NXP i.MX8M board select"
 	optional
@@ -36,9 +66,12 @@ config TARGET_IMX8MQ_CM
 
 config TARGET_IMX8MQ_EVK
 	bool "imx8mq_evk"
-	select BINMAN
 	select IMX8MQ
 	select IMX8M_LPDDR4
+	select FSL_CAAM
+	select FSL_BLOB
+	select ARCH_MISC_INIT
+	select SPL_CRYPTO if SPL
 
 config TARGET_IMX8MQ_PHANBELL
 	bool "imx8mq_phanbell"
@@ -46,12 +79,64 @@ config TARGET_IMX8MQ_PHANBELL
 	select IMX8MQ
 	select IMX8M_LPDDR4
 
+config TARGET_IMX8MQ_DDR3L_VAL
+	bool "imx8mq_ddr3l_val"
+	select IMX8MQ
+
+config TARGET_IMX8MQ_DDR4_VAL
+	bool "imx8mq_ddr4_val"
+	select IMX8MQ
+	select IMX8M_DDR4
+
+config TARGET_IMX8MM_DDR4_VAL
+	bool "imx8mm DDR4 validation board"
+	select IMX8MM
+	select SUPPORT_SPL
+	select IMX8M_DDR4
+
+config TARGET_IMX8MM_DDR3L_VAL
+	bool "imx8mm DDR3L validation board"
+	select IMX8MM
+	select SUPPORT_SPL
+	select IMX8M_DDR3L
+
 config TARGET_IMX8MM_EVK
 	bool "imx8mm LPDDR4 EVK board"
-	select BINMAN
 	select IMX8MM
 	select SUPPORT_SPL
 	select IMX8M_LPDDR4
+	select FSL_CAAM
+	select FSL_BLOB
+	select ARCH_MISC_INIT
+	select SPL_CRYPTO if SPL
+
+config TARGET_IMX8MM_DDR4_EVK
+	bool "imx8mm DDR4 EVK board"
+	select IMX8MM
+	select SUPPORT_SPL
+	select IMX8M_DDR4
+	select FSL_CAAM
+	select FSL_BLOB
+	select ARCH_MISC_INIT
+	select SPL_CRYPTO if SPL
+
+config TARGET_IMX8MM_AB2
+	bool "imx8mm LPDDR4 Audio board 2.0"
+	select IMX8MM
+	select SUPPORT_SPL
+	select IMX8M_LPDDR4
+	select FSL_CAAM
+	select FSL_BLOB
+	select SPL_CRYPTO if SPL
+
+config TARGET_IMX8MM_DDR4_AB2
+	bool "imx8mm DDR4 Audio board 2.0"
+	select IMX8MM
+	select SUPPORT_SPL
+	select IMX8M_DDR4
+	select FSL_CAAM
+	select FSL_BLOB
+	select SPL_CRYPTO if SPL
 
 config TARGET_IMX8MM_ICORE_MX8MM
 	bool "Engicam i.Core MX8M Mini SOM"
@@ -87,17 +172,57 @@ config TARGET_KONTRON_MX8MM
 
 config TARGET_IMX8MN_EVK
 	bool "imx8mn LPDDR4 EVK board"
-	select BINMAN
 	select IMX8MN
 	select SUPPORT_SPL
 	select IMX8M_LPDDR4
+	select FSL_CAAM
+	select FSL_BLOB
+	select SPL_CRYPTO if SPL
 
 config TARGET_IMX8MN_DDR4_EVK
 	bool "imx8mn DDR4 EVK board"
-	select BINMAN
 	select IMX8MN
 	select SUPPORT_SPL
 	select IMX8M_DDR4
+	select FSL_CAAM
+	select FSL_BLOB
+	select SPL_CRYPTO if SPL
+
+config TARGET_IMX8MN_DDR3_EVK
+	bool "imx8mn 11x11 DDR3 EVK board"
+	select IMX8MN
+	select SUPPORT_SPL
+	select IMX8M_DDR3L
+	select FSL_CAAM
+	select FSL_BLOB
+	select SPL_CRYPTO if SPL
+
+config TARGET_IMX8MN_AB2
+	bool "imx8mn LPDDR4 Audio board 2.0"
+	select IMX8MN
+	select SUPPORT_SPL
+	select IMX8M_LPDDR4
+	select FSL_CAAM
+	select FSL_BLOB
+	select SPL_CRYPTO if SPL
+
+config TARGET_IMX8MN_DDR4_AB2
+	bool "imx8mn DDR4 Audio board 2.0"
+	select IMX8MN
+	select SUPPORT_SPL
+	select IMX8M_DDR4
+	select FSL_CAAM
+	select FSL_BLOB
+	select SPL_CRYPTO if SPL
+
+config TARGET_IMX8MN_DDR3L_AB2
+	bool "imx8mn DDR3L Audio board 2.0"
+	select IMX8MN
+	select SUPPORT_SPL
+	select IMX8M_DDR3L
+	select FSL_CAAM
+	select FSL_BLOB
+	select SPL_CRYPTO if SPL
 
 config TARGET_IMX8MN_VENICE
 	bool "Support Gateworks Venice iMX8M Nano module"
@@ -108,10 +233,23 @@ config TARGET_IMX8MN_VENICE
 
 config TARGET_IMX8MP_EVK
 	bool "imx8mp LPDDR4 EVK board"
-	select BINMAN
 	select IMX8MP
 	select SUPPORT_SPL
 	select IMX8M_LPDDR4
+	select FSL_CAAM
+	select FSL_BLOB
+	select ARCH_MISC_INIT
+	select SPL_CRYPTO if SPL
+
+config TARGET_IMX8MP_DDR4_EVK
+	bool "imx8mp DDR4 EVK board"
+	select IMX8MP
+	select SUPPORT_SPL
+	select IMX8M_DDR4
+	select FSL_CAAM
+	select FSL_BLOB
+	select ARCH_MISC_INIT
+	select SPL_CRYPTO if SPL
 
 config TARGET_PICO_IMX8MQ
 	bool "Support Technexion Pico iMX8MQ"
@@ -211,7 +349,10 @@ source "board/beacon/imx8mn/Kconfig"
 source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
 source "board/engicam/imx8mm/Kconfig"
 source "board/freescale/imx8mq_evk/Kconfig"
+source "board/freescale/imx8mq_val/Kconfig"
+source "board/freescale/imx8mm_ab2/Kconfig"
 source "board/freescale/imx8mm_evk/Kconfig"
+source "board/freescale/imx8mm_val/Kconfig"
 source "board/freescale/imx8mn_evk/Kconfig"
 source "board/freescale/imx8mp_evk/Kconfig"
 source "board/gateworks/venice/Kconfig"
diff --git a/arch/arm/mach-imx/imx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile
index d9dee894aae..b8978cf6f86 100644
--- a/arch/arm/mach-imx/imx8m/Makefile
+++ b/arch/arm/mach-imx/imx8m/Makefile
@@ -6,3 +6,5 @@ obj-y += lowlevel_init.o
 obj-y += clock_slice.o soc.o
 obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
 obj-$(CONFIG_IMX8MM)$(CONFIG_IMX8MN)$(CONFIG_IMX8MP) += clock_imx8mm.o
+obj-$(CONFIG_ANDROID_SUPPORT) += imx8m_csu.o
+obj-$(CONFIG_ANDROID_SUPPORT) += imx8m_rdc.o
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 76132defc21..d6be307e6e9 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <command.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
@@ -15,6 +16,7 @@
 #include <errno.h>
 #include <linux/bitops.h>
 #include <linux/delay.h>
+#include <log.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -45,18 +47,17 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 	return 0;
 }
 
-#ifdef CONFIG_SPL_BUILD
 static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
 	PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
-	PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
-	PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
+	PLL_1443X_RATE(800000000U, 200, 3, 1, 0),
+	PLL_1443X_RATE(750000000U, 250, 2, 2, 0),
 	PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
 	PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
 	PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
-	PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
-	PLL_1443X_RATE(266000000U, 400, 9, 2, 0),
+	PLL_1443X_RATE(400000000U, 400, 3, 3, 0),
+	PLL_1443X_RATE(266000000U, 266, 3, 3, 0),
 	PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
-	PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
+	PLL_1443X_RATE(100000000U, 200, 3, 4, 0),
 };
 
 static int fracpll_configure(enum pll_clocks pll, u32 freq)
@@ -123,6 +124,7 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq)
 	return 0;
 }
 
+#ifdef CONFIG_SPL_BUILD
 void dram_pll_init(ulong pll_val)
 {
 	fracpll_configure(ANATOP_DRAM_PLL, pll_val);
@@ -297,6 +299,106 @@ int intpll_configure(enum pll_clocks pll, ulong freq)
 	return 0;
 }
 
+#define VIDEO_PLL_RATE 594000000U
+
+void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
+{
+	uint32_t div, pre, post;
+
+	div = VIDEO_PLL_RATE / 1000;
+	div = (div + freq - 1) / freq;
+
+	if (div < 1)
+		div = 1;
+
+	for (pre = 1; pre <= 8; pre++) {
+		for (post = 1; post <= 64; post++) {
+			if (pre * post == div) {
+				goto find;
+			}
+		}
+	}
+
+	printf("Fail to set rate to %dkhz", freq);
+	return;
+
+find:
+	/* Select to video PLL */
+	debug("mxs_set_lcdclk, pre = %d, post = %d\n", pre, post);
+
+#ifdef CONFIG_IMX8MP
+	clock_set_target_val(MEDIA_DISP1_PIX_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_PRE_DIV(pre - 1) | CLK_ROOT_POST_DIV(post - 1));
+#elif defined(CONFIG_IMX8MN)
+	clock_set_target_val(DISPLAY_PIXEL_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_PRE_DIV(pre - 1) | CLK_ROOT_POST_DIV(post - 1));
+#else
+	clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_PRE_DIV(pre - 1) | CLK_ROOT_POST_DIV(post - 1));
+#endif
+
+}
+
+#ifdef CONFIG_IMX8MP
+void enable_display_clk(unsigned char enable)
+{
+	if (enable) {
+		clock_enable(CCGR_DISPMIX, false);
+
+		/* Set Video PLL to 594Mhz, p = 1, m = 99,  k = 0, s = 2 */
+		fracpll_configure(ANATOP_VIDEO_PLL, VIDEO_PLL_RATE);
+
+		/* 400Mhz */
+		clock_set_target_val(MEDIA_AXI_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV2));
+
+		/* 200Mhz */
+		clock_set_target_val(MEDIA_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2) |CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
+
+		/* 27Mhz MIPI DPHY PLL ref from video PLL */
+		clock_set_target_val(MEDIA_MIPI_PHY1_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(7) |CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV22));
+		clock_enable(CCGR_DISPMIX, true);
+	} else {
+		clock_enable(CCGR_DISPMIX, false);
+	}
+}
+#else
+void enable_display_clk(unsigned char enable)
+{
+	if (enable) {
+		clock_enable(CCGR_DISPMIX, false);
+
+		/* Set Video PLL to 594Mhz, p = 1, m = 99,  k = 0, s = 2 */
+		fracpll_configure(ANATOP_VIDEO_PLL, VIDEO_PLL_RATE);
+
+		/* 500Mhz */
+		clock_set_target_val(DISPLAY_AXI_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV2));
+
+		/* 200Mhz */
+		clock_set_target_val(DISPLAY_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2) |CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
+
+		clock_set_target_val(MIPI_DSI_CORE_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
+
+		/* 27Mhz MIPI DPHY PLL ref from video PLL */
+#ifdef CONFIG_IMX8MN
+		clock_set_target_val(DISPLAY_DSI_PHY_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(7) |CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV22));
+#else
+		clock_set_target_val(MIPI_DSI_PHY_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(7) |CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV22));
+#endif
+		clock_enable(CCGR_DISPMIX, true);
+	} else {
+		clock_enable(CCGR_DISPMIX, false);
+	}
+}
+#endif
+
+u32 get_dsi_phy_ref_clk(void)
+{
+#ifdef CONFIG_IMX8MP
+	return get_root_clk(MEDIA_MIPI_PHY1_REF_CLK_ROOT);
+#elif defined(CONFIG_IMX8MN)
+	return get_root_clk(DISPLAY_DSI_PHY_REF_CLK_ROOT);
+#else
+	return get_root_clk(MIPI_DSI_PHY_REF_CLK_ROOT);
+#endif
+}
+
 void init_uart_clk(u32 index)
 {
 	/*
@@ -484,13 +586,160 @@ int clock_init(void)
 
 	clock_enable(CCGR_SEC_DEBUG, 1);
 
+	enable_display_clk(1);
 	return 0;
 };
 
-u32 imx_get_uartclk(void)
+void init_clk_fspi(int index)
+{
+	/*
+	 * set qspi root
+	 * sys pll1 100M
+	 */
+	clock_enable(CCGR_QSPI, 0);
+	clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(7));
+	clock_enable(CCGR_QSPI, 1);
+}
+
+#ifdef CONFIG_DWC_ETH_QOS
+int set_clk_eqos(enum enet_freq type)
+{
+	u32 target;
+	u32 enet1_ref;
+
+	switch (type) {
+	case ENET_125MHZ:
+		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
+		break;
+	case ENET_50MHZ:
+		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
+		break;
+	case ENET_25MHZ:
+		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* disable the clock first */
+	clock_enable(CCGR_QOS_ETHENET, 0);
+	clock_enable(CCGR_SDMA2, 0);
+
+	/* set enet axi clock 266Mhz */
+	target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
+		 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+		 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+	clock_set_target_val(ENET_AXI_CLK_ROOT, target);
+
+	target = CLK_ROOT_ON | enet1_ref |
+		 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+		 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+	clock_set_target_val(ENET_QOS_CLK_ROOT, target);
+
+	target = CLK_ROOT_ON |
+		ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
+		CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+		CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+	clock_set_target_val(ENET_QOS_TIMER_CLK_ROOT, target);
+
+	/* enable clock */
+	clock_enable(CCGR_QOS_ETHENET, 1);
+	clock_enable(CCGR_SDMA2, 1);
+
+	return 0;
+}
+
+int imx_eqos_txclk_set_rate(ulong rate)
 {
-	return 24000000U;
+	u32 val;
+	u32 eqos_post_div;
+
+	/* disable the clock first */
+	clock_enable(CCGR_QOS_ETHENET, 0);
+	clock_enable(CCGR_SDMA2, 0);
+
+	switch (rate) {
+	case 125000000:
+		eqos_post_div = 1;
+		break;
+	case 25000000:
+		eqos_post_div = 125000000 / 25000000;
+		break;
+	case 2500000:
+		eqos_post_div = 125000000 / 2500000;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	clock_get_target_val(ENET_QOS_CLK_ROOT, &val);
+	val &= ~(CLK_ROOT_PRE_DIV_MASK | CLK_ROOT_POST_DIV_MASK);
+	val |= CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+	       CLK_ROOT_POST_DIV(eqos_post_div - 1);
+	clock_set_target_val(ENET_QOS_CLK_ROOT, val);
+
+	/* enable clock */
+	clock_enable(CCGR_QOS_ETHENET, 1);
+	clock_enable(CCGR_SDMA2, 1);
+
+	return 0;
 }
+#endif
+
+#ifdef CONFIG_FEC_MXC
+int set_clk_enet(enum enet_freq type)
+{
+	u32 target;
+	u32 enet1_ref;
+
+	/* disable the clock first */
+	clock_enable(CCGR_ENET1, 0);
+	clock_enable(CCGR_SIM_ENET, 0);
+
+	switch (type) {
+	case ENET_125MHZ:
+		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
+		break;
+	case ENET_50MHZ:
+		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
+		break;
+	case ENET_25MHZ:
+		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* set enet axi clock 266Mhz */
+	target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
+		 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+		 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+	clock_set_target_val(ENET_AXI_CLK_ROOT, target);
+
+	target = CLK_ROOT_ON | enet1_ref |
+		 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+		 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+	clock_set_target_val(ENET_REF_CLK_ROOT, target);
+
+	target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
+		 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+		 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+	clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
+
+#ifdef CONFIG_FEC_MXC_25M_REF_CLK
+	target = CLK_ROOT_ON |
+		 ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
+		 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+		 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+	clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
+#endif
+	/* enable clock */
+	clock_enable(CCGR_SIM_ENET, 1);
+	clock_enable(CCGR_ENET1, 1);
+
+	return 0;
+}
+#endif
 
 static u32 decode_intpll(enum clk_root_src intpll)
 {
@@ -818,141 +1067,118 @@ u32 mxc_get_clock(enum mxc_clock clk)
 	return 0;
 }
 
-#ifdef CONFIG_DWC_ETH_QOS
-int set_clk_eqos(enum enet_freq type)
+u32 imx_get_uartclk(void)
 {
-	u32 target;
-	u32 enet1_ref;
-
-	switch (type) {
-	case ENET_125MHZ:
-		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
-		break;
-	case ENET_50MHZ:
-		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
-		break;
-	case ENET_25MHZ:
-		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	/* disable the clock first */
-	clock_enable(CCGR_QOS_ETHENET, 0);
-	clock_enable(CCGR_SDMA2, 0);
-
-	/* set enet axi clock 266Mhz */
-	target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
-		 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
-		 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
-	clock_set_target_val(ENET_AXI_CLK_ROOT, target);
-
-	target = CLK_ROOT_ON | enet1_ref |
-		 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
-		 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
-	clock_set_target_val(ENET_QOS_CLK_ROOT, target);
-
-	target = CLK_ROOT_ON |
-		ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
-		CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
-		CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
-	clock_set_target_val(ENET_QOS_TIMER_CLK_ROOT, target);
-
-	/* enable clock */
-	clock_enable(CCGR_QOS_ETHENET, 1);
-	clock_enable(CCGR_SDMA2, 1);
-
-	return 0;
+	return mxc_get_clock(MXC_UART_CLK);
 }
 
-int imx_eqos_txclk_set_rate(ulong rate)
+u32 imx_get_fecclk(void)
 {
-	u32 val;
-	u32 eqos_post_div;
-
-	/* disable the clock first */
-	clock_enable(CCGR_QOS_ETHENET, 0);
-	clock_enable(CCGR_SDMA2, 0);
-
-	switch (rate) {
-	case 125000000:
-		eqos_post_div = 1;
-		break;
-	case 25000000:
-		eqos_post_div = 125000000 / 25000000;
-		break;
-	case 2500000:
-		eqos_post_div = 125000000 / 2500000;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	clock_get_target_val(ENET_QOS_CLK_ROOT, &val);
-	val &= ~(CLK_ROOT_PRE_DIV_MASK | CLK_ROOT_POST_DIV_MASK);
-	val |= CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
-	       CLK_ROOT_POST_DIV(eqos_post_div - 1);
-	clock_set_target_val(ENET_QOS_CLK_ROOT, val);
-
-	/* enable clock */
-	clock_enable(CCGR_QOS_ETHENET, 1);
-	clock_enable(CCGR_SDMA2, 1);
-
-	return 0;
+	return get_root_clk(ENET_AXI_CLK_ROOT);
 }
 
 u32 imx_get_eqos_csr_clk(void)
 {
 	return get_root_clk(ENET_AXI_CLK_ROOT);
 }
-#endif
 
-#ifdef CONFIG_FEC_MXC
-int set_clk_enet(enum enet_freq type)
+#if defined(CONFIG_IMX8MP)
+void init_usb_clk(void)
 {
-	u32 target;
-	u32 enet1_ref;
-
-	switch (type) {
-	case ENET_125MHZ:
-		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
-		break;
-	case ENET_50MHZ:
-		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
-		break;
-	case ENET_25MHZ:
-		enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	/* disable the clock first */
-	clock_enable(CCGR_ENET1, 0);
-	clock_enable(CCGR_SIM_ENET, 0);
+	clock_enable(CCGR_USB_MSCALE_PL301, 0);
+	clock_enable(CCGR_USB_PHY_8MP, 0);
 
-	/* set enet axi clock 266Mhz */
-	target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
-		 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
-		 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
-	clock_set_target_val(ENET_AXI_CLK_ROOT, target);
+	/* HSIOMIX AXI BUS root already been set by ROM */
 
-	target = CLK_ROOT_ON | enet1_ref |
-		 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
-		 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
-	clock_set_target_val(ENET_REF_CLK_ROOT, target);
+	/* 100MHz */
+	clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(1));
+	/* 100MHz */
+	clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(1));
 
-	target = CLK_ROOT_ON |
-		ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
-		CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
-		CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
-	clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
+	clock_enable(CCGR_USB_MSCALE_PL301, 1);
+	clock_enable(CCGR_USB_PHY_8MP, 1);
+}
+#else
+void enable_usboh3_clk(unsigned char enable)
+{
+	if (enable) {
+		clock_enable(CCGR_USB_MSCALE_PL301, 0);
+		/* 500M */
+		clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
+		/* 100M */
+		clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
+		/* 100M */
+		clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
+		clock_enable(CCGR_USB_MSCALE_PL301, 1);
+	} else {
+		clock_enable(CCGR_USB_MSCALE_PL301, 0);
+	}
+}
+#endif
 
-	/* enable clock */
-	clock_enable(CCGR_SIM_ENET, 1);
-	clock_enable(CCGR_ENET1, 1);
+/*
+ * Dump some clockes.
+ */
+#ifndef CONFIG_SPL_BUILD
+int do_mscale_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+	u32 freq;
+
+	freq = decode_intpll(ARM_PLL_CLK);
+	printf("ARM_PLL    %8d MHz\n", freq / 1000000);
+	freq = decode_fracpll(DRAM_PLL1_CLK);
+	printf("DRAM_PLL    %8d MHz\n", freq / 1000000);
+	freq = decode_intpll(SYSTEM_PLL1_800M_CLK);
+	printf("SYS_PLL1_800    %8d MHz\n", freq / 1000000);
+	freq = decode_intpll(SYSTEM_PLL1_400M_CLK);
+	printf("SYS_PLL1_400    %8d MHz\n", freq / 1000000);
+	freq = decode_intpll(SYSTEM_PLL1_266M_CLK);
+	printf("SYS_PLL1_266    %8d MHz\n", freq / 1000000);
+	freq = decode_intpll(SYSTEM_PLL1_160M_CLK);
+	printf("SYS_PLL1_160    %8d MHz\n", freq / 1000000);
+	freq = decode_intpll(SYSTEM_PLL1_133M_CLK);
+	printf("SYS_PLL1_133    %8d MHz\n", freq / 1000000);
+	freq = decode_intpll(SYSTEM_PLL1_100M_CLK);
+	printf("SYS_PLL1_100    %8d MHz\n", freq / 1000000);
+	freq = decode_intpll(SYSTEM_PLL1_80M_CLK);
+	printf("SYS_PLL1_80    %8d MHz\n", freq / 1000000);
+	freq = decode_intpll(SYSTEM_PLL1_40M_CLK);
+	printf("SYS_PLL1_40    %8d MHz\n", freq / 1000000);
+	freq = decode_intpll(SYSTEM_PLL2_1000M_CLK);
+	printf("SYS_PLL2_1000    %8d MHz\n", freq / 1000000);
+	freq = decode_intpll(SYSTEM_PLL2_500M_CLK);
+	printf("SYS_PLL2_500    %8d MHz\n", freq / 1000000);
+	freq = decode_intpll(SYSTEM_PLL2_333M_CLK);
+	printf("SYS_PLL2_333    %8d MHz\n", freq / 1000000);
+	freq = decode_intpll(SYSTEM_PLL2_250M_CLK);
+	printf("SYS_PLL2_250    %8d MHz\n", freq / 1000000);
+	freq = decode_intpll(SYSTEM_PLL2_200M_CLK);
+	printf("SYS_PLL2_200    %8d MHz\n", freq / 1000000);
+	freq = decode_intpll(SYSTEM_PLL2_166M_CLK);
+	printf("SYS_PLL2_166    %8d MHz\n", freq / 1000000);
+	freq = decode_intpll(SYSTEM_PLL2_125M_CLK);
+	printf("SYS_PLL2_125    %8d MHz\n", freq / 1000000);
+	freq = decode_intpll(SYSTEM_PLL2_100M_CLK);
+	printf("SYS_PLL2_100    %8d MHz\n", freq / 1000000);
+	freq = decode_intpll(SYSTEM_PLL2_50M_CLK);
+	printf("SYS_PLL2_50    %8d MHz\n", freq / 1000000);
+	freq = decode_intpll(SYSTEM_PLL3_CLK);
+	printf("SYS_PLL3       %8d MHz\n", freq / 1000000);
+	freq = mxc_get_clock(MXC_UART_CLK);
+	printf("UART1          %8d MHz\n", freq / 1000000);
+	freq = mxc_get_clock(MXC_ESDHC_CLK);
+	printf("USDHC1         %8d MHz\n", freq / 1000000);
+	freq = mxc_get_clock(MXC_QSPI_CLK);
+	printf("QSPI           %8d MHz\n", freq / 1000000);
 
 	return 0;
 }
+
+U_BOOT_CMD(
+	clocks,	CONFIG_SYS_MAXARGS, 1, do_mscale_showclocks,
+	"display clocks",
+	""
+);
 #endif
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
index 9db62b944e4..43c4e89aaa2 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
@@ -372,13 +372,16 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 	case MXC_QSPI_CLK:
 		return get_root_clk(QSPI_CLK_ROOT);
 	default:
-		return get_root_clk(clk);
+		printf("Unsupported mxc_clock %d\n", clk);
+		break;
 	}
+
+	return 0;
 }
 
 u32 imx_get_uartclk(void)
 {
-	return mxc_get_clock(UART1_CLK_ROOT);
+	return mxc_get_clock(MXC_UART_CLK);
 }
 
 void mxs_set_lcdclk(u32 base_addr, u32 freq)
@@ -734,6 +737,77 @@ static int frac_pll_init(u32 pll, enum frac_pll_out_val val)
 	return 0;
 }
 
+int sscg_pll_init(u32 pll)
+{
+	void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2;
+	u32 val_cfg0, val_cfg1, val_cfg2, val;
+	u32 bypass1_mask = 0x20, bypass2_mask = 0x10;
+	int ret;
+
+	switch (pll) {
+	case ANATOP_SYSTEM_PLL1:
+		pll_cfg0 = &ana_pll->sys_pll1_cfg0;
+		pll_cfg1 = &ana_pll->sys_pll1_cfg1;
+		pll_cfg2 = &ana_pll->sys_pll1_cfg2;
+		/* 800MHz */
+		val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
+			SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
+		val_cfg1 = 0;
+		val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
+			SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
+			SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
+			SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
+			SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
+			SSCG_PLL_REFCLK_SEL_OSC_25M;
+		break;
+	case ANATOP_SYSTEM_PLL2:
+		pll_cfg0 = &ana_pll->sys_pll2_cfg0;
+		pll_cfg1 = &ana_pll->sys_pll2_cfg1;
+		pll_cfg2 = &ana_pll->sys_pll2_cfg2;
+		/* 1000MHz */
+		val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
+			SSCG_PLL_FEEDBACK_DIV_F2_VAL(4);
+		val_cfg1 = 0;
+		val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
+			SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
+			SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
+			SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
+			SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
+			SSCG_PLL_REFCLK_SEL_OSC_25M;
+		break;
+	case ANATOP_SYSTEM_PLL3:
+		pll_cfg0 = &ana_pll->sys_pll3_cfg0;
+		pll_cfg1 = &ana_pll->sys_pll3_cfg1;
+		pll_cfg2 = &ana_pll->sys_pll3_cfg2;
+		/* 800MHz */
+		val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
+			SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
+		val_cfg1 = 0;
+		val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK |  SSCG_PLL_LOCK_SEL_MASK |
+			SSCG_PLL_REFCLK_SEL_OSC_25M;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/*bypass*/
+	setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask);
+	/* set value */
+	writel(val_cfg2, pll_cfg2);
+	writel(val_cfg1, pll_cfg1);
+	/*unbypass1 and wait 70us */
+	writel(val_cfg0 | bypass2_mask, pll_cfg1);
+
+	__udelay(70);
+
+	/* unbypass2 and wait lock */
+	writel(val_cfg0, pll_cfg1);
+	ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1);
+	if (ret)
+		printf("%s timeout\n", __func__);
+
+	return ret;
+}
 
 int clock_init(void)
 {
@@ -790,6 +864,20 @@ int clock_init(void)
 }
 #endif
 
+int imx8m_dcss_clock_init(u32 pixclk)
+{
+	/* b_clk: bus_clk_root(4) sel 2nd input source and
+	   pre_div to 0; output should be 800M */
+	clock_set_target_val(DISPLAY_AXI_CLK_ROOT, CLK_ROOT_ON |CLK_ROOT_SOURCE_SEL(2));
+
+	/* rtr_clk: bus_clk_root(6) sel 1st input source
+		   and pre_div to 1; output should be 400M */
+	clock_set_target_val(DISPLAY_RTRM_CLK_ROOT,
+		CLK_ROOT_ON |CLK_ROOT_SOURCE_SEL(1) |CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV2));
+
+	return 0;
+}
+
 /*
  * Dump some clockes.
  */
@@ -841,11 +929,11 @@ static int do_imx8m_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
 	printf("SYS_PLL2_50    %8d MHz\n", freq / 1000000);
 	freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
 	printf("SYS_PLL3       %8d MHz\n", freq / 1000000);
-	freq = mxc_get_clock(UART1_CLK_ROOT);
+	freq = mxc_get_clock(MXC_UART_CLK);
 	printf("UART1          %8d MHz\n", freq / 1000000);
-	freq = mxc_get_clock(USDHC1_CLK_ROOT);
+	freq = mxc_get_clock(MXC_ESDHC_CLK);
 	printf("USDHC1         %8d MHz\n", freq / 1000000);
-	freq = mxc_get_clock(QSPI_CLK_ROOT);
+	freq = mxc_get_clock(MXC_QSPI_CLK);
 	printf("QSPI           %8d MHz\n", freq / 1000000);
 	return 0;
 }
diff --git a/arch/arm/mach-imx/imx8m/imx8m_csu.c b/arch/arm/mach-imx/imx8m/imx8m_csu.c
new file mode 100644
index 00000000000..791f7d0d4d6
--- /dev/null
+++ b/arch/arm/mach-imx/imx8m/imx8m_csu.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <asm/arch/imx8m_csu.h>
+
+void imx_csu_init(const struct imx_csu_cfg *csu_cfg)
+{
+	const struct imx_csu_cfg *csu = csu_cfg;
+	unsigned int val;
+
+	while (csu->type != CSU_INVALID) {
+		switch (csu->type) {
+		case CSU_CSL:
+			val = readl((uint32_t *)CSLx_REG(csu->idx));
+			if (val & CSLx_LOCK(csu->idx))
+				break;
+			clrsetbits_le32((uint32_t *)CSLx_REG(csu->idx), CSLx_CFG(0xff, csu->idx),
+				CSLx_CFG(csu->csl_level | (csu->lock << 8), csu->idx));
+			break;
+		case CSU_HP:
+			val = readl((uint32_t *)CSU_HP_REG(csu->idx));
+			if (val & CSU_HP_LOCK(csu->idx))
+				break;
+			clrsetbits_le32((uint32_t *)CSU_HP_REG(csu->idx), CSU_HP_CFG(0x1, csu->idx),
+				CSU_HP_CFG(csu->hp | (csu->lock << 0x1), csu->idx));
+			break;
+		case CSU_SA:
+			val = readl((uint32_t *)CSU_SA_REG(csu->idx));
+			if (val & CSU_SA_LOCK(csu->idx))
+				break;
+			clrsetbits_le32((uint32_t *)CSU_SA_REG(csu->idx), CSU_SA_CFG(0x1, csu->idx),
+				CSU_SA_CFG(csu->sa | (csu->lock << 0x1), csu->idx));
+			break;
+		case CSU_HPCONTROL:
+			val = readl((uint32_t *)CSU_HPCONTROL_REG(csu->idx));
+			if (val & CSU_HPCONTROL_LOCK(csu->idx))
+				break;
+			clrsetbits_le32((uint32_t *)CSU_HPCONTROL_REG(csu->idx), CSU_HPCONTROL_CFG(0x1, csu->idx),
+				CSU_HPCONTROL_CFG(csu->hpctrl | (csu->lock << 0x1), csu->idx));
+			break;
+		default:
+			break;
+		}
+
+		csu++;
+	}
+}
diff --git a/arch/arm/mach-imx/imx8m/imx8m_rdc.c b/arch/arm/mach-imx/imx8m/imx8m_rdc.c
new file mode 100644
index 00000000000..f6fec62f4fd
--- /dev/null
+++ b/arch/arm/mach-imx/imx8m/imx8m_rdc.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2019, NXP. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <asm/arch/imx8m_rdc.h>
+
+void imx_rdc_init(const struct imx_rdc_cfg *rdc_cfg)
+{
+	const struct imx_rdc_cfg *rdc = rdc_cfg;
+
+	while (rdc->type != RDC_INVALID) {
+		switch (rdc->type) {
+		case RDC_MDA:
+			/* MDA config */
+			writel(rdc->setting.rdc_mda, MDAn(rdc->index));
+			break;
+		case RDC_PDAP:
+			/* peripheral access permission config */
+			writel(rdc->setting.rdc_pdap, PDAPn(rdc->index));
+			break;
+		case RDC_MEM_REGION:
+			/* memory region access permission config */
+			writel(rdc->setting.rdc_mem_region[0], MRSAn(rdc->index));
+			writel(rdc->setting.rdc_mem_region[1], MREAn(rdc->index));
+			writel(rdc->setting.rdc_mem_region[2], MRCn(rdc->index));
+			break;
+		default:
+			break;
+		}
+
+		rdc++;
+	}
+}
diff --git a/arch/arm/mach-imx/imx8m/imximage-8mn-ddr3l.cfg b/arch/arm/mach-imx/imx8m/imximage-8mn-ddr3l.cfg
new file mode 100644
index 00000000000..ab43bf5b011
--- /dev/null
+++ b/arch/arm/mach-imx/imx8m/imximage-8mn-ddr3l.cfg
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#define __ASSEMBLY__
+
+FIT
+BOOT_FROM	sd
+LOADER		spl/u-boot-spl-ddr.bin	0x912000
+SECOND_LOADER	u-boot.itb		0x40200000 0x60000
+
+DDR_FW ddr3_imem_1d.bin
+DDR_FW ddr3_dmem_1d.bin
diff --git a/arch/arm/mach-imx/imx8m/imximage-8mp-ddr4.cfg b/arch/arm/mach-imx/imx8m/imximage-8mp-ddr4.cfg
new file mode 100644
index 00000000000..74bb66831e4
--- /dev/null
+++ b/arch/arm/mach-imx/imx8m/imximage-8mp-ddr4.cfg
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#define __ASSEMBLY__
+
+FIT
+ROM_VERSION	v2
+BOOT_FROM	sd
+LOADER		spl/u-boot-spl-ddr.bin	0x920000
+SECOND_LOADER	u-boot.itb		0x40200000 0x60000
+
+DDR_FW ddr4_imem_1d.bin
+DDR_FW ddr4_dmem_1d.bin
+DDR_FW ddr4_imem_2d.bin
+DDR_FW ddr4_dmem_2d.bin
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 1a5a391443d..0d2f7a5897f 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2019, 2021 NXP
  *
  * Peng Fan <peng.fan@nxp.com>
  */
@@ -16,10 +16,12 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/hab.h>
 #include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/optee.h>
 #include <asm/mach-imx/syscounter.h>
 #include <asm/ptrace.h>
 #include <asm/armv8/mmu.h>
 #include <dm/uclass.h>
+#include <dm/device.h>
 #include <efi_loader.h>
 #include <env.h>
 #include <env_internal.h>
@@ -29,10 +31,12 @@
 #include <imx_sip.h>
 #include <linux/arm-smccc.h>
 #include <linux/bitops.h>
+#include <asm/setup.h>
+#include <asm/bootm.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_IMX_HAB)
+#if defined(CONFIG_IMX_HAB) || defined(CONFIG_AVB_ATX) || defined(CONFIG_IMX_TRUSTY_OS)
 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
 	.bank = 1,
 	.word = 3,
@@ -71,15 +75,13 @@ void enable_tzc380(void)
 	 * According to TRM, TZASC_ID_SWAP_BYPASS should be set in
 	 * order to avoid AXI Bus errors when GPU is in use
 	 */
-	if (is_imx8mm() || is_imx8mn() || is_imx8mp())
-		setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
+	setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
 
 	/*
-	 * imx8mn and imx8mp implements the lock bit for
+	 * imx8m implements the lock bit for
 	 * TZASC_ID_SWAP_BYPASS, enable it to lock settings
 	 */
-	if (is_imx8mn() || is_imx8mp())
-		setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
+	setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
 
 	/*
 	 * set Region 0 attribute to allow secure and non-secure
@@ -153,7 +155,11 @@ static struct mm_region imx8m_mem_map[] = {
 		.phys = 0x40000000UL,
 		.size = PHYS_SDRAM_SIZE,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+#ifdef CONFIG_IMX_TRUSTY_OS
+			 PTE_BLOCK_INNER_SHARE
+#else
 			 PTE_BLOCK_OUTER_SHARE
+#endif
 #ifdef PHYS_SDRAM_2_SIZE
 	}, {
 		/* DRAM2 */
@@ -161,8 +167,12 @@ static struct mm_region imx8m_mem_map[] = {
 		.phys = 0x100000000UL,
 		.size = PHYS_SDRAM_2_SIZE,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+#ifdef CONFIG_IMX_TRUSTY_OS
+			 PTE_BLOCK_INNER_SHARE
+#else
 			 PTE_BLOCK_OUTER_SHARE
 #endif
+#endif
 	}, {
 		/* empty entrie to split table entry 5 if needed when TEEs are used */
 		0,
@@ -187,32 +197,29 @@ static unsigned int imx8m_find_dram_entry_in_mem_map(void)
 
 void enable_caches(void)
 {
-	/* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
-	if (rom_pointer[1]) {
-		/*
-		 * TEE are loaded, So the ddr bank structures
-		 * have been modified update mmu table accordingly
-		 */
-		int i = 0;
-		/*
-		 * please make sure that entry initial value matches
-		 * imx8m_mem_map for DRAM1
-		 */
-		int entry = imx8m_find_dram_entry_in_mem_map();
-		u64 attrs = imx8m_mem_map[entry].attrs;
-
-		while (i < CONFIG_NR_DRAM_BANKS &&
-		       entry < ARRAY_SIZE(imx8m_mem_map)) {
-			if (gd->bd->bi_dram[i].start == 0)
-				break;
-			imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
-			imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
-			imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
-			imx8m_mem_map[entry].attrs = attrs;
-			debug("Added memory mapping (%d): %llx %llx\n", entry,
-			      imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
-			i++; entry++;
-		}
+	/* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch
+	 * If OPTEE does not run, still update the MMU table according to dram banks structure
+	 * to set correct dram size from board_phys_sdram_size
+	 */
+	int i = 0;
+	/*
+	 * please make sure that entry initial value matches
+	 * imx8m_mem_map for DRAM1
+	 */
+	int entry = imx8m_find_dram_entry_in_mem_map();
+	u64 attrs = imx8m_mem_map[entry].attrs;
+
+	while (i < CONFIG_NR_DRAM_BANKS &&
+	       entry < ARRAY_SIZE(imx8m_mem_map)) {
+		if (gd->bd->bi_dram[i].start == 0)
+			break;
+		imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
+		imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
+		imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
+		imx8m_mem_map[entry].attrs = attrs;
+		debug("Added memory mapping (%d): %llx %llx\n", entry,
+		      imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
+		i++; entry++;
 	}
 
 	icache_enable();
@@ -225,12 +232,15 @@ __weak int board_phys_sdram_size(phys_size_t *size)
 		return -EINVAL;
 
 	*size = PHYS_SDRAM_SIZE;
+
+#ifdef PHYS_SDRAM_2_SIZE
+	*size += PHYS_SDRAM_2_SIZE;
+#endif
 	return 0;
 }
 
 int dram_init(void)
 {
-	unsigned int entry = imx8m_find_dram_entry_in_mem_map();
 	phys_size_t sdram_size;
 	int ret;
 
@@ -244,13 +254,6 @@ int dram_init(void)
 	else
 		gd->ram_size = sdram_size;
 
-	/* also update the SDRAM size in the mem_map used externally */
-	imx8m_mem_map[entry].size = sdram_size;
-
-#ifdef PHYS_SDRAM_2_SIZE
-	gd->ram_size += PHYS_SDRAM_2_SIZE;
-#endif
-
 	return 0;
 }
 
@@ -259,18 +262,28 @@ int dram_init_banksize(void)
 	int bank = 0;
 	int ret;
 	phys_size_t sdram_size;
+	phys_size_t sdram_b1_size, sdram_b2_size;
 
 	ret = board_phys_sdram_size(&sdram_size);
 	if (ret)
 		return ret;
 
+	/* Bank 1 can't cross over 4GB space */
+	if (sdram_size > 0xc0000000) {
+		sdram_b1_size = 0xc0000000;
+		sdram_b2_size = sdram_size - 0xc0000000;
+	} else {
+		sdram_b1_size = sdram_size;
+		sdram_b2_size = 0;
+	}
+
 	gd->bd->bi_dram[bank].start = PHYS_SDRAM;
 	if (rom_pointer[1]) {
 		phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
 		phys_size_t optee_size = (size_t)rom_pointer[1];
 
 		gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
-		if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
+		if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
 			if (++bank >= CONFIG_NR_DRAM_BANKS) {
 				puts("CONFIG_NR_DRAM_BANKS is not enough\n");
 				return -1;
@@ -278,59 +291,51 @@ int dram_init_banksize(void)
 
 			gd->bd->bi_dram[bank].start = optee_start + optee_size;
 			gd->bd->bi_dram[bank].size = PHYS_SDRAM +
-				sdram_size - gd->bd->bi_dram[bank].start;
+				sdram_b1_size - gd->bd->bi_dram[bank].start;
 		}
 	} else {
-		gd->bd->bi_dram[bank].size = sdram_size;
+		gd->bd->bi_dram[bank].size = sdram_b1_size;
 	}
 
-#ifdef PHYS_SDRAM_2_SIZE
-	if (++bank >= CONFIG_NR_DRAM_BANKS) {
-		puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
-		return -1;
+	if (sdram_b2_size) {
+		if (++bank >= CONFIG_NR_DRAM_BANKS) {
+			puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
+			return -1;
+		}
+		gd->bd->bi_dram[bank].start = 0x100000000UL;
+		gd->bd->bi_dram[bank].size = sdram_b2_size;
 	}
-	gd->bd->bi_dram[bank].start = PHYS_SDRAM_2;
-	gd->bd->bi_dram[bank].size = PHYS_SDRAM_2_SIZE;
-#endif
 
 	return 0;
 }
 
 phys_size_t get_effective_memsize(void)
 {
-	/* return the first bank as effective memory */
-	if (rom_pointer[1])
-		return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
-
-#ifdef PHYS_SDRAM_2_SIZE
-	return gd->ram_size - PHYS_SDRAM_2_SIZE;
-#else
-	return gd->ram_size;
-#endif
-}
-
-ulong board_get_usable_ram_top(ulong total_size)
-{
-	ulong top_addr = PHYS_SDRAM + gd->ram_size;
-
-	/*
-	 * Some IPs have their accessible address space restricted by
-	 * the interconnect. Let's make sure U-Boot only ever uses the
-	 * space below the 4G address boundary (which is 3GiB big),
-	 * even when the effective available memory is bigger.
-	 */
-	if (top_addr > 0x80000000)
-		top_addr = 0x80000000;
+	int ret;
+	phys_size_t sdram_size;
+	phys_size_t sdram_b1_size;
+	ret = board_phys_sdram_size(&sdram_size);
+	if (!ret) {
+		/* Bank 1 can't cross over 4GB space */
+		if (sdram_size > 0xc0000000) {
+			sdram_b1_size = 0xc0000000;
+		} else {
+			sdram_b1_size = sdram_size;
+		}
 
-	/*
-	 * rom_pointer[0] stores the TEE memory start address.
-	 * rom_pointer[1] stores the size TEE uses.
-	 * We need to reserve the memory region for TEE.
-	 */
-	if (rom_pointer[0] && rom_pointer[1] && top_addr > rom_pointer[0])
-		top_addr = rom_pointer[0];
+		if (rom_pointer[1]) {
+			/* We will relocate u-boot to Top of dram1. Tee position has two cases:
+			 * 1. At the top of dram1,  Then return the size removed optee size.
+			 * 2. In the middle of dram1, return the size of dram1.
+			 */
+			if ((rom_pointer[0] + rom_pointer[1]) == (PHYS_SDRAM + sdram_b1_size))
+				return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
+		}
 
-	return top_addr;
+		return sdram_b1_size;
+	} else {
+		return PHYS_SDRAM_SIZE;
+	}
 }
 
 static u32 get_cpu_variant_type(u32 type)
@@ -413,7 +418,21 @@ static u32 get_cpu_variant_type(u32 type)
 		if ((value & 0x3) == 0x3)
 			flag |= (1 << 2);
 
+		/* gpu disabled */
+		if ((value & 0xc0) == 0xc0)
+			flag |= (1 << 3);
+
+		/* lvds disabled */
+		if ((value & 0x180000) == 0x180000)
+			flag |= (1 << 4);
+
+		/* mipi dsi disabled */
+		if ((value & 0x60000) == 0x60000)
+			flag |= (1 << 5);
+
 		switch (flag) {
+		case 0x3f:
+			return MXC_CPU_IMX8MPUL;
 		case 7:
 			return MXC_CPU_IMX8MPL;
 		case 2:
@@ -512,6 +531,53 @@ int arch_cpu_init_dm(void)
 	return 0;
 }
 
+#if defined(CONFIG_IMX_HAB) && defined(CONFIG_IMX8MQ)
+static bool is_hdmi_fused(void) {
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[1];
+	struct fuse_bank1_regs *fuse =
+		(struct fuse_bank1_regs *)bank->fuse_regs;
+
+	u32 value = readl(&fuse->tester4);
+
+	if (is_imx8mq()) {
+		if (value & 0x02000000)
+			return true;
+	}
+
+	return false;
+}
+
+bool is_uid_matched(u64 uid) {
+	struct tag_serialnr nr;
+	get_board_serial(&nr);
+
+	if (lower_32_bits(uid) == nr.low &&
+		upper_32_bits(uid) == nr.high)
+		return true;
+
+	return false;
+}
+
+static void secure_lockup(void)
+{
+	if (is_imx8mq() && is_soc_rev(CHIP_REV_2_1) &&
+		imx_hab_is_enabled() && !is_hdmi_fused()) {
+#ifdef CONFIG_SECURE_STICKY_BITS_LOCKUP
+		struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+
+		clock_enable(CCGR_OCOTP, 1);
+		setbits_le32(&ocotp->sw_sticky, 0x6); /* Lock up field return and SRK revoke */
+		writel(0x80000000, &ocotp->scs_set); /* Lock up SCS */
+#else
+		/* Check the Unique ID, if it is matched with UID config, then allow to leave sticky bits unlocked */
+		if (!is_uid_matched(CONFIG_IMX_UNIQUE_ID))
+			hang();
+#endif
+	}
+}
+#endif
+
 int arch_cpu_init(void)
 {
 	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@@ -531,6 +597,9 @@ int arch_cpu_init(void)
 		clock_init();
 		imx_set_wdog_powerdown(false);
 
+#if defined(CONFIG_IMX_HAB) && defined(CONFIG_IMX8MQ)
+		secure_lockup();
+#endif
 		if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() ||
 		    is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() ||
 		    is_imx8mnsl() || is_imx8mpd() || is_imx8mnud() || is_imx8mnus()) {
@@ -551,6 +620,11 @@ int arch_cpu_init(void)
 		}
 	}
 
+#if defined(CONFIG_ANDROID_SUPPORT)
+	/* Enable RTC */
+	writel(0x21, 0x30370038);
+#endif
+
 	if (is_imx8mq()) {
 		clock_enable(CCGR_OCOTP, 1);
 		if (readl(&ocotp->ctrl) & 0x200)
@@ -673,6 +747,18 @@ bool is_usb_boot(void)
 {
 	return get_boot_device() == USB_BOOT;
 }
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[0];
+	struct fuse_bank0_regs *fuse =
+		(struct fuse_bank0_regs *)bank->fuse_regs;
+
+	serialnr->low = fuse->uid_low;
+	serialnr->high = fuse->uid_high;
+}
+#endif
 
 #ifdef CONFIG_OF_SYSTEM_SETUP
 bool check_fdt_new_path(void *blob)
@@ -699,7 +785,7 @@ static int disable_fdt_nodes(void *blob, const char *const nodes_path[], int siz
 		if (nodeoff < 0)
 			continue; /* Not found, skip it */
 
-		printf("Found %s node\n", nodes_path[i]);
+		debug("Found %s node\n", nodes_path[i]);
 
 add_status:
 		rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1);
@@ -827,6 +913,14 @@ static int check_mipi_dsi_nodes(void *blob)
 }
 #endif
 
+void board_quiesce_devices(void)
+{
+#ifdef CONFIG_USB_DWC3
+	if (is_usb_boot())
+		disconnect_from_pc();
+#endif
+}
+
 int disable_vpu_nodes(void *blob)
 {
 	static const char * const nodes_path_8mq[] = {
@@ -864,33 +958,122 @@ static int low_drive_gpu_freq(void *blob)
 		"/soc@0/gpu@38000000"
 	};
 
-	int nodeoff, cnt, i;
+	int nodeoff, cnt, i, j;
 	u32 assignedclks[7];
 
-	nodeoff = fdt_path_offset(blob, nodes_path_8mn[0]);
-	if (nodeoff < 0)
-		return nodeoff;
+	for (i = 0; i < ARRAY_SIZE(nodes_path_8mn); i++) {
+		nodeoff = fdt_path_offset(blob, nodes_path_8mn[i]);
+		if (nodeoff < 0)
+			continue;
+
+		cnt = fdtdec_get_int_array_count(blob, nodeoff, "assigned-clock-rates", assignedclks, 7);
+		if (cnt < 0)
+			return cnt;
 
-	cnt = fdtdec_get_int_array_count(blob, nodeoff, "assigned-clock-rates", assignedclks, 7);
-	if (cnt < 0)
-		return cnt;
+		if (cnt != 7)
+			printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[i], cnt);
 
-	if (cnt != 7)
-		printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt);
+		assignedclks[cnt - 1] = 200000000;
+		assignedclks[cnt - 2] = 200000000;
 
-	assignedclks[cnt - 1] = 200000000;
-	assignedclks[cnt - 2] = 200000000;
+		for (j = 0; j < cnt; j++) {
+			debug("<%u>, ", assignedclks[j]);
+			assignedclks[j] = cpu_to_fdt32(assignedclks[j]);
+		}
+		debug("\n");
 
-	for (i = 0; i < cnt; i++) {
-		debug("<%u>, ", assignedclks[i]);
-		assignedclks[i] = cpu_to_fdt32(assignedclks[i]);
+		return fdt_setprop(blob, nodeoff, "assigned-clock-rates", &assignedclks, sizeof(assignedclks));
 	}
-	debug("\n");
 
-	return fdt_setprop(blob, nodeoff, "assigned-clock-rates", &assignedclks, sizeof(assignedclks));
+	return -ENOENT;
 }
 #endif
 
+static bool check_remote_endpoint(void *blob, const char *ep1, const char *ep2)
+{
+	int lookup_node;
+	int nodeoff;
+
+	nodeoff = fdt_path_offset(blob, ep1);
+	if (nodeoff) {
+		lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
+		nodeoff = fdt_path_offset(blob, ep2);
+
+		if (nodeoff > 0 && nodeoff == lookup_node) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+int disable_dsi_lcdif_nodes(void *blob)
+{
+	int ret;
+
+	static const char * const dsi_path_8mp[] = {
+		"/soc@0/bus@32c00000/mipi_dsi@32e60000"
+	};
+
+	static const char * const lcdif_path_8mp[] = {
+		"/soc@0/bus@32c00000/lcd-controller@32e80000"
+	};
+
+	static const char * const lcdif_ep_path_8mp[] = {
+		"/soc@0/bus@32c00000/lcd-controller@32e80000/port@0/endpoint"
+	};
+	static const char * const dsi_ep_path_8mp[] = {
+		"/soc@0/bus@32c00000/mipi_dsi@32e60000/port@0/endpoint"
+	};
+
+	ret = disable_fdt_nodes(blob, dsi_path_8mp, ARRAY_SIZE(dsi_path_8mp));
+	if (ret)
+		return ret;
+
+	if (check_remote_endpoint(blob, dsi_ep_path_8mp[0], lcdif_ep_path_8mp[0])) {
+		/* Disable lcdif node */
+		return disable_fdt_nodes(blob, lcdif_path_8mp, ARRAY_SIZE(lcdif_path_8mp));
+	}
+
+	return 0;
+}
+
+int disable_lvds_lcdif_nodes(void *blob)
+{
+	int ret, i;
+
+	static const char * const ldb_path_8mp[] = {
+		"/soc@0/bus@32c00000/ldb@32ec005c",
+		"/soc@0/bus@32c00000/phy@32ec0128"
+	};
+
+	static const char * const lcdif_path_8mp[] = {
+		"/soc@0/bus@32c00000/lcd-controller@32e90000"
+	};
+
+	static const char * const lcdif_ep_path_8mp[] = {
+		"/soc@0/bus@32c00000/lcd-controller@32e90000/port@0/endpoint@0",
+		"/soc@0/bus@32c00000/lcd-controller@32e90000/port@0/endpoint@1"
+	};
+	static const char * const ldb_ep_path_8mp[] = {
+		"/soc@0/bus@32c00000/ldb@32ec005c/lvds-channel@0/port@0/endpoint",
+		"/soc@0/bus@32c00000/ldb@32ec005c/lvds-channel@1/port@0/endpoint"
+	};
+
+	ret = disable_fdt_nodes(blob, ldb_path_8mp, ARRAY_SIZE(ldb_path_8mp));
+	if (ret)
+		return ret;
+
+	for (i = 0; i < ARRAY_SIZE(ldb_ep_path_8mp); i++) {
+		if (check_remote_endpoint(blob, ldb_ep_path_8mp[i], lcdif_ep_path_8mp[i])) {
+			/* Disable lcdif node */
+			return disable_fdt_nodes(blob, lcdif_path_8mp, ARRAY_SIZE(lcdif_path_8mp));
+		}
+	}
+
+	return 0;
+}
+
 int disable_gpu_nodes(void *blob)
 {
 	static const char * const nodes_path_8mn[] = {
@@ -898,7 +1081,15 @@ int disable_gpu_nodes(void *blob)
 		"/soc@/gpu@38000000"
 	};
 
-	return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
+	static const char * const nodes_path_8mp[] = {
+		"/gpu3d@38000000",
+		"/gpu2d@38008000"
+	};
+
+	if (is_imx8mp())
+		return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
+	else
+		return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
 }
 
 int disable_npu_nodes(void *blob)
@@ -1040,6 +1231,60 @@ static int disable_cpu_nodes(void *blob, u32 disabled_cores)
 	return 0;
 }
 
+static int delete_u_boot_nodes(void *blob)
+{
+	static const char * const nodes_path = "/u-boot-node";
+	int nodeoff;
+	int rc;
+
+	nodeoff = fdt_path_offset(blob, nodes_path);
+	if (nodeoff < 0)
+		return 0;
+
+	debug("Found %s node\n", nodes_path);
+
+	rc = fdt_del_node(blob, nodeoff);
+	if (rc < 0) {
+		printf("Unable to delete node %s, err=%s\n",
+		       nodes_path, fdt_strerror(rc));
+	} else {
+		printf("Delete node %s\n", nodes_path);
+	}
+
+	return 0;
+}
+
+static int cleanup_nodes_for_efi(void *blob)
+{
+	static const char * const path[][2] = {
+		{ "/soc@0/bus@32c00000/usb@32e40000", "extcon" },
+		{ "/soc@0/bus@32c00000/usb@32e50000", "extcon" },
+		{ "/soc@0/bus@30800000/ethernet@30be0000", "phy-reset-gpios" },
+		{ "/soc@0/bus@30800000/ethernet@30bf0000", "phy-reset-gpios" }
+	};
+	int nodeoff, i, rc;
+
+	for (i = 0; i < ARRAY_SIZE(path); i++) {
+		nodeoff = fdt_path_offset(blob, path[i][0]);
+		if (nodeoff < 0)
+			continue; /* Not found, skip it */
+		debug("Found %s node\n", path[i][0]);
+
+		rc = fdt_delprop(blob, nodeoff, path[i][1]);
+		if (rc == -FDT_ERR_NOTFOUND)
+			continue;
+		if (rc) {
+			printf("Unable to update property %s:%s, err=%s\n",
+			       path[i][0], path[i][1], fdt_strerror(rc));
+			return rc;
+		}
+
+		printf("Remove %s:%s\n", path[i][0], path[i][1]);
+	}
+
+	return 0;
+}
+
 int ft_system_setup(void *blob, struct bd_info *bd)
 {
 #ifdef CONFIG_IMX8MQ
@@ -1154,25 +1399,78 @@ usb_modify_speed:
 		disable_cpu_nodes(blob, 3);
 
 #elif defined(CONFIG_IMX8MP)
-	if (is_imx8mpl())
+	if (is_imx8mpul()) {
+		/* Disable GPU */
+		disable_gpu_nodes(blob);
+
+		/* Disable DSI */
+		disable_dsi_lcdif_nodes(blob);
+
+		/* Disable LVDS */
+		disable_lvds_lcdif_nodes(blob);
+	}
+
+	if (is_imx8mpul() || is_imx8mpl())
 		disable_vpu_nodes(blob);
 
-	if (is_imx8mpl() || is_imx8mp6())
+	if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
 		disable_npu_nodes(blob);
 
-	if (is_imx8mpl())
+	if (is_imx8mpul() || is_imx8mpl())
 		disable_isp_nodes(blob);
 
-	if (is_imx8mpl() || is_imx8mp6())
+	if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
 		disable_dsp_nodes(blob);
 
 	if (is_imx8mpd())
 		disable_cpu_nodes(blob, 2);
 #endif
 
+	cleanup_nodes_for_efi(blob);
+
+	delete_u_boot_nodes(blob);
+
+#if defined(CONFIG_ANDROID_SUPPORT) || defined(CONFIG_ANDROID_AUTO_SUPPORT)
+	return 0;
+#else
+	return ft_add_optee_node(blob, bd);
+#endif
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_FIXUP
+#ifndef CONFIG_SPL_BUILD
+int board_fix_fdt(void *fdt)
+{
+	if (is_imx8mpul()) {
+		int i = 0;
+		int nodeoff, ret;
+		const char *status = "disabled";
+		static const char * dsi_nodes[] = {
+			"/soc@0/bus@32c00000/mipi_dsi@32e60000",
+			"/soc@0/bus@32c00000/lcd-controller@32e80000",
+			"/dsi-host"
+		};
+
+		for (i = 0; i < ARRAY_SIZE(dsi_nodes); i++) {
+			nodeoff = fdt_path_offset(fdt, dsi_nodes[i]);
+			if (nodeoff > 0) {
+set_status:
+				ret = fdt_setprop(fdt, nodeoff, "status", status,
+					strlen(status) + 1);
+				if (ret == -FDT_ERR_NOSPACE) {
+					ret = fdt_increase_size(fdt, 512);
+					if (!ret)
+						goto set_status;
+				}
+			}
+		}
+	}
+
 	return 0;
 }
 #endif
+#endif
 
 #if !CONFIG_IS_ENABLED(SYSRESET)
 void reset_cpu(void)
@@ -1191,7 +1489,7 @@ void reset_cpu(void)
 #endif
 
 #if defined(CONFIG_ARCH_MISC_INIT)
-static void acquire_buildinfo(void)
+static __maybe_unused void acquire_buildinfo(void)
 {
 	u64 atf_commit = 0;
 	struct arm_smccc_res res;
@@ -1210,12 +1508,93 @@ static void acquire_buildinfo(void)
 
 int arch_misc_init(void)
 {
+#ifndef CONFIG_ANDROID_SUPPORT
+	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+		struct udevice *dev;
+		int ret;
+
+		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+		if (ret)
+			printf("Failed to initialize caam_jr: %d\n", ret);
+	}
+#endif
 	acquire_buildinfo();
 
 	return 0;
 }
 #endif
 
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_IMX8MP
+#define HSIO_GPR_BASE                               (0x32F10000U)
+#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT    (1)
+#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN          (0x1U << HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT)
+#endif
+
+static uint32_t gpc_pu_m_core_offset[11] = {
+	0xc00, 0xc40, 0xc80, 0xcc0,
+	0xdc0, 0xe00, 0xe40, 0xe80,
+	0xec0, 0xf00, 0xf40,
+};
+
+#define PGC_PCR				0
+
+void imx_gpc_set_m_core_pgc(unsigned int offset, bool pdn)
+{
+	uint32_t val;
+	uintptr_t reg = GPC_BASE_ADDR + offset;
+
+	val = readl(reg);
+	val &= ~(0x1 << PGC_PCR);
+
+	if(pdn)
+		val |= 0x1 << PGC_PCR;
+	writel(val, reg);
+}
+
+void imx8m_usb_power_domain(uint32_t domain_id, bool on)
+{
+	uint32_t val;
+	uintptr_t reg;
+
+#ifdef CONFIG_IMX8MP
+	if (on) {
+		/* enable usb clock via hsio gpr */
+		reg = readl(HSIO_GPR_BASE);
+		reg |= HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN;
+		writel(reg, HSIO_GPR_BASE);
+	}
+#endif
+
+	imx_gpc_set_m_core_pgc(gpc_pu_m_core_offset[domain_id], true);
+
+	reg = GPC_BASE_ADDR + (on ? 0xf8 : 0x104);
+	val = 1 << (domain_id > 3 ? (domain_id + 3) : domain_id);
+	writel(val, reg);
+	while (readl(reg) & val)
+		;
+	imx_gpc_set_m_core_pgc(gpc_pu_m_core_offset[domain_id], false);
+}
+#endif
+
+int imx8m_usb_power(int usb_id, bool on)
+{
+	if (usb_id > 1)
+		return -EINVAL;
+
+#ifdef CONFIG_SPL_BUILD
+	imx8m_usb_power_domain(2 + usb_id, on);
+#else
+	struct arm_smccc_res res;
+	arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN,
+			2 + usb_id, on, 0, 0, 0, 0, &res);
+	if (res.a0)
+		return -EPERM;
+#endif
+
+	return 0;
+}
+
 void imx_tmu_arch_init(void *reg_base)
 {
 	if (is_imx8mm() || is_imx8mn()) {
@@ -1361,3 +1740,16 @@ enum env_location env_get_location(enum env_operation op, int prio)
 }
 
 #endif
+
+#ifdef CONFIG_IMX8MQ
+int imx8m_dcss_power_init(void)
+{
+	/* Enable the display CCGR before power on */
+	clock_enable(CCGR_DISPLAY, 1);
+
+	writel(0x0000ffff, 0x303A00EC); /*PGC_CPU_MAPPING */
+	setbits_le32(0x303A00F8, 0x1 << 10); /*PU_PGC_SW_PUP_REQ : disp was 10 */
+
+	return 0;
+}
+#endif
diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-imx/imx8ulp/Kconfig
index 963fc93d34f..fe6ff519175 100644
--- a/arch/arm/mach-imx/imx8ulp/Kconfig
+++ b/arch/arm/mach-imx/imx8ulp/Kconfig
@@ -1,12 +1,24 @@
 if ARCH_IMX8ULP
 
+config AHAB_BOOT
+	bool "Support i.MX8ULP AHAB features"
+	help
+	  This option enables the support for AHAB secure boot.
+
 config IMX8ULP
+	select ARCH_EARLY_INIT_R
 	bool
-	select ARMV8_SPL_EXCEPTION_VECTORS
 
 config SYS_SOC
 	default "imx8ulp"
 
+config IMX8ULP_LD_MODE
+	bool
+	default n
+
+config IMX8ULP_ND_MODE
+	bool "i.MX8ULP Low Driver Mode"
+
 choice
 	prompt "i.MX8ULP board select"
 	optional
@@ -15,6 +27,21 @@ config TARGET_IMX8ULP_EVK
 	bool "imx8ulp_evk"
 	select IMX8ULP
 	select SUPPORT_SPL
+	select IMX8ULP_DRAM
+	select FSL_CAAM
+	select FSL_BLOB
+	select ARCH_MISC_INIT
+	select SPL_CRYPTO if SPL
+
+config TARGET_IMX8ULP_9X9_EVK
+	bool "imx8ulp_9x9_evk"
+	select IMX8ULP
+	select SUPPORT_SPL
+	select IMX8ULP_DRAM
+	select FSL_CAAM
+	select FSL_BLOB
+	select ARCH_MISC_INIT
+	select SPL_CRYPTO_SUPPORT if SPL
 
 endchoice
 
diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c
index 38bcbb91e6e..3913b170515 100644
--- a/arch/arm/mach-imx/imx8ulp/cgc.c
+++ b/arch/arm/mach-imx/imx8ulp/cgc.c
@@ -9,9 +9,11 @@
 #include <errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/cgc.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/global_data.h>
 #include <linux/delay.h>
+#include <hang.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -29,7 +31,7 @@ void cgc1_soscdiv_init(void)
 	clrbits_le32(&cgc1_regs->frodiv, BIT(7));
 }
 
-void cgc1_pll2_init(void)
+void cgc1_pll2_init(ulong freq)
 {
 	u32 reg;
 
@@ -44,8 +46,8 @@ void cgc1_pll2_init(void)
 	while ((readl(&cgc1_regs->pll2csr) & BIT(24)))
 		;
 
-	/* Select SOSC as source, freq = 31 * 24 =744mhz */
-	reg = 31 << 16;
+	/* Select SOSC as source */
+	reg = (freq / MHZ(24)) << 16;
 	writel(reg, &cgc1_regs->pll2cfg);
 
 	/* Enable PLL2 */
@@ -74,7 +76,7 @@ static void cgc1_set_a35_clk(u32 clk_src, u32 div_core)
 		;
 }
 
-void cgc1_init_core_clk(void)
+void cgc1_init_core_clk(ulong freq)
 {
 	u32 reg = readl(&cgc1_regs->ca35clk);
 
@@ -82,8 +84,7 @@ void cgc1_init_core_clk(void)
 	if (((reg >> 28) & 0x3) == 0x1)
 		cgc1_set_a35_clk(0, 1);
 
-	/* Set pll2 to 750Mhz for 1V  */
-	cgc1_pll2_init();
+	cgc1_pll2_init(freq);
 
 	/* Set A35 clock to pll2 */
 	cgc1_set_a35_clk(1, 1);
@@ -94,7 +95,7 @@ void cgc1_enet_stamp_sel(u32 clk_src)
 	writel((clk_src & 0x7) << 24, &cgc1_regs->enetstamp);
 }
 
-void cgc1_pll3_init(void)
+void cgc1_pll3_init(ulong freq)
 {
 	/* Gate off VCO */
 	setbits_le32(&cgc1_regs->pll3div_vco, BIT(7));
@@ -115,11 +116,15 @@ void cgc1_pll3_init(void)
 	/* Select SOSC as source */
 	clrbits_le32(&cgc1_regs->pll3cfg, BIT(0));
 
-	//setbits_le32(&cgc1_regs->pll3cfg, 22 << 16);
-	writel(22 << 16, &cgc1_regs->pll3cfg);
-
-	writel(578, &cgc1_regs->pll3num);
-	writel(1000, &cgc1_regs->pll3denom);
+	switch (freq) {
+	case 540672000:
+		writel(0x16 << 16, &cgc1_regs->pll3cfg);
+		writel(0x16e3600, &cgc1_regs->pll3denom);
+		writel(0xc15c00, &cgc1_regs->pll3num);
+		break;
+	default:
+		hang();
+	}
 
 	/* Enable PLL3 */
 	setbits_le32(&cgc1_regs->pll3csr, BIT(0));
@@ -130,23 +135,30 @@ void cgc1_pll3_init(void)
 	/* Gate on VCO */
 	clrbits_le32(&cgc1_regs->pll3div_vco, BIT(7));
 
-	/*
-	 * PFD0: 380MHz/396/396/328
-	 */
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F);
-	setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 0);
+
+	if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
+		setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 0);
+		clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 3 << 21); /* 195M */
+	} else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
+		setbits_le32(&cgc1_regs->pll3pfdcfg, 21 << 0);
+		clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 1 << 21); /* 231M */
+	} else {
+		setbits_le32(&cgc1_regs->pll3pfdcfg, 30 << 0); /* 324M */
+	}
+
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(7));
 	while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(6)))
 		;
 
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 8);
-	setbits_le32(&cgc1_regs->pll3pfdcfg, 24 << 8);
+	setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 8);
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(15));
 	while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(14)))
 		;
 
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 16);
-	setbits_le32(&cgc1_regs->pll3pfdcfg, 24 << 16);
+	setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 16);
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(23));
 	while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(22)))
 		;
@@ -166,10 +178,24 @@ void cgc1_pll3_init(void)
 	clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(15));
 	clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(23));
 	clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(31));
+
+	if (!IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) && !IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
+		clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(29, 28), BIT(28)); /* nicclk select pll3 pfd0 */
+		while (!(readl(&cgc1_regs->nicclk) & BIT(27)))
+			;
+	}
 }
 
-void cgc2_pll4_init(void)
+void cgc2_pll4_init(bool pll4_reset)
 {
+	/* Check the NICLPAV first to ensure not from PLL4 PFD1 clock */
+	if ((readl(&cgc2_regs->niclpavclk) & GENMASK(29, 28)) == BIT(28)) {
+		/* switch to FRO 192 first */
+		clrbits_le32(&cgc2_regs->niclpavclk, GENMASK(29, 28));
+		while (!(readl(&cgc2_regs->niclpavclk) & BIT(27)))
+			;
+	}
+
 	/* Disable PFD DIV and clear DIV */
 	writel(0x80808080, &cgc2_regs->pll4div_pfd0);
 	writel(0x80808080, &cgc2_regs->pll4div_pfd1);
@@ -177,22 +203,33 @@ void cgc2_pll4_init(void)
 	/* Gate off and clear PFD  */
 	writel(0x80808080, &cgc2_regs->pll4pfdcfg);
 
-	/* Disable PLL4 */
-	writel(0x0, &cgc2_regs->pll4csr);
+	if (pll4_reset) {
+		/* Disable PLL4 */
+		writel(0x0, &cgc2_regs->pll4csr);
 
-	/* Configure PLL4 to 528Mhz and clock source from SOSC */
-	writel(22 << 16, &cgc2_regs->pll4cfg);
-	writel(0x1, &cgc2_regs->pll4csr);
+		/* Configure PLL4 to 528Mhz and clock source from SOSC */
+		writel(22 << 16, &cgc2_regs->pll4cfg);
+		writel(0x1, &cgc2_regs->pll4csr);
 
-	/* wait for PLL4 output valid */
-	while (!(readl(&cgc2_regs->pll4csr) & BIT(24)))
-		;
+		/* wait for PLL4 output valid */
+		while (!(readl(&cgc2_regs->pll4csr) & BIT(24)))
+			;
+	}
 
 	/* Enable all 4 PFDs */
-	setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0);
-	setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */
-	setbits_le32(&cgc2_regs->pll4pfdcfg, 12 << 16);
-	setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24);
+	setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0); /* 528 */
+	if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
+		setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 8);
+		clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 3 << 21); /* 99Mhz for NIC_LPAV */
+	} else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
+		setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 8);
+		clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 1 << 21); /* 198Mhz for NIC_LPAV */
+	} else {
+		setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */
+		clrbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21));
+	}
+	setbits_le32(&cgc2_regs->pll4pfdcfg, 12 << 16); /* 792 */
+	setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24); /* 396 */
 
 	clrbits_le32(&cgc2_regs->pll4pfdcfg, BIT(7) | BIT(15) | BIT(23) | BIT(31));
 
@@ -203,6 +240,10 @@ void cgc2_pll4_init(void)
 	/* Enable PFD DIV */
 	clrbits_le32(&cgc2_regs->pll4div_pfd0, BIT(7) | BIT(15) | BIT(23) | BIT(31));
 	clrbits_le32(&cgc2_regs->pll4div_pfd1, BIT(7) | BIT(15) | BIT(23) | BIT(31));
+
+	clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(29, 28), BIT(28));
+	while (!(readl(&cgc2_regs->niclpavclk) & BIT(27)))
+		;
 }
 
 void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd)
diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index 91580b2c29c..2898c8b96c8 100644
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -101,8 +101,8 @@ void init_clk_ddr(void)
 	writel(0xc0000000, PCC5_LPDDR4_ADDR);
 
 	/* enable pll4 and ddrclk*/
-	cgc2_pll4_init();
-	cgc2_ddrclk_config(1, 1);
+	cgc2_pll4_init(true);
+	cgc2_ddrclk_config(4, 1);
 
 	/* enable ddr pcc */
 	writel(0xd0000000, PCC5_LPDDR4_ADDR);
@@ -153,30 +153,70 @@ int set_ddr_clk(u32 phy_freq_mhz)
 	return 0;
 }
 
-void clock_init(void)
+void clock_init_early(void)
 {
 	cgc1_soscdiv_init();
-	cgc1_init_core_clk();
 
 	init_clk_lpuart();
 
-	pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
-	pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD1_DIV2);
-	pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
-	pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
+	/* Enable upower mu1 clk */
+	pcc_clock_enable(3, UPOWER_PCC3_SLOT, true);
+}
 
-	pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
-	pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV1);
-	pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
-	pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
+/* This will be invoked after pmic voltage setting */
+void clock_init_late(void)
+{
 
-	pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
-	pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV1);
-	pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
-	pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
+	if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
+		cgc1_init_core_clk(MHZ(500));
+	} else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
+		cgc1_init_core_clk(MHZ(750));
+	} else {
+		cgc1_init_core_clk(MHZ(960));
 
-	/* Enable upower mu1 clk */
-	pcc_clock_enable(3, UPOWER_PCC3_SLOT, true);
+	}
+	/*
+	 * Audio use this frequency in kernel dts,
+	 * however nic use pll3 pfd0, we have to
+	 * make the freqency same as kernel to make nic
+	 * not being disabled
+	 */
+	cgc1_pll3_init(540672000);
+
+	if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) || IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
+		pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
+		pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD2_DIV2);
+		pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
+		pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
+
+		pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
+		pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV2);
+		pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
+		pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
+
+		pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
+		pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV2);
+		pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
+		pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
+	} else {
+		pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
+		pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD1_DIV2);
+		pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
+		pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
+
+		pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
+		pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV1);
+		pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
+		pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
+
+		pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
+		pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV1);
+		pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
+		pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
+	}
+
+	/* enable MU0_MUB clock before access the register of MU0_MUB */
+	pcc_clock_enable(3, MU0_B_PCC3_SLOT, true);
 
 	/*
 	 * Enable clock division
@@ -237,6 +277,32 @@ u32 imx_get_i2cclk(u32 i2c_num)
 }
 #endif
 
+#if IS_ENABLED(CONFIG_SYS_I2C_IMX_I3C)
+int enable_i3c_clk(unsigned char enable, u32 i3c_num)
+{
+	if (i3c_num != 8)
+		return -EINVAL;
+
+	if (enable) {
+		pcc_clock_enable(3, I3C2_PCC3_SLOT, false);
+		pcc_clock_sel(3, I3C2_PCC3_SLOT, SOSC_DIV2);
+		pcc_clock_enable(3, I3C2_PCC3_SLOT, true);
+		pcc_reset_peripheral(3, I3C2_PCC3_SLOT, false);
+	} else {
+		pcc_clock_enable(3, I3C2_PCC3_SLOT, false);
+	}
+	return 0;
+}
+
+u32 imx_get_i3cclk(u32 i3c_num)
+{
+	if (i3c_num != 8)
+		return 0;
+
+	return pcc_clock_get_rate(3, I3C2_PCC3_SLOT);
+}
+#endif
+
 void enable_usboh3_clk(unsigned char enable)
 {
 	if (enable) {
@@ -381,10 +447,9 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz)
 	debug("PLL4 rate %ukhz\n", pll4_rate);
 
 	for (pfd = 12; pfd <= 35; pfd++) {
-		parent_rate = pll4_rate;
-		parent_rate = parent_rate * 18 / pfd;
-
 		for (div = 1; div <= 64; div++) {
+			parent_rate = pll4_rate;
+			parent_rate = parent_rate * 18 / pfd;
 			parent_rate = parent_rate / div;
 
 			for (pcd = 0; pcd < 8; pcd++) {
diff --git a/arch/arm/mach-imx/imx8ulp/pcc.c b/arch/arm/mach-imx/imx8ulp/pcc.c
index 7909d770afe..e3c6d6760be 100644
--- a/arch/arm/mach-imx/imx8ulp/pcc.c
+++ b/arch/arm/mach-imx/imx8ulp/pcc.c
@@ -135,6 +135,7 @@ static struct pcc_entry pcc3_arrays[] = {
 	{PCC3_RBASE, UPOWER_PCC3_SLOT,		CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},
 	{PCC3_RBASE, WDOG3_PCC3_SLOT,		CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B},
 	{PCC3_RBASE, WDOG4_PCC3_SLOT,		CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B},
+	{PCC3_RBASE, CAAM_PCC3_SLOT,		CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B},
 	{PCC3_RBASE, XRDC_MGR_PCC3_SLOT,	CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},
 	{PCC3_RBASE, SEMA42_1_PCC3_SLOT,	CLKSRC_PER_BUS, PCC_NO_DIV, PCC_NO_RST_B},
 	{PCC3_RBASE, ROMCP1_PCC3_SLOT,		CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},
diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index e2eca0633e3..b6afed90b6c 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -8,8 +8,8 @@
 #include <asm/types.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/mu_hal.h>
-#include <asm/arch/s400_api.h>
+#include <asm/mach-imx/mu_hal.h>
+#include <asm/mach-imx/s400_api.h>
 #include <asm/arch/rdc.h>
 #include <div64.h>
 
@@ -184,14 +184,14 @@ int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm)
 int release_rdc(enum rdc_type type)
 {
 	ulong s_mu_base = 0x27020000UL;
-	struct imx8ulp_s400_msg msg;
+	struct sentinel_msg msg;
 	int ret;
 	u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74;
 
 	msg.version = AHAB_VERSION;
 	msg.tag = AHAB_CMD_TAG;
 	msg.size = 2;
-	msg.command = AHAB_RELEASE_RDC_REQ_CID;
+	msg.command = ELE_RELEASE_RDC_REQ;
 	msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */
 
 	mu_hal_init(s_mu_base);
@@ -276,6 +276,16 @@ void xrdc_init_mda(void)
 
 void xrdc_init_mrc(void)
 {
+	/* Set MRC4 and MRC5 for DDR access from A35 and AP NIC PER masters */
+	xrdc_config_mrc_w0_w1(4, 0, CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
+	xrdc_config_mrc_dx_perm(4, 0, 1, 1);
+	xrdc_config_mrc_dx_perm(4, 0, 7, 1);
+	xrdc_config_mrc_w3_w4(4, 0, 0x0, 0x80000FFF);
+
+	xrdc_config_mrc_w0_w1(5, 0, CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
+	xrdc_config_mrc_dx_perm(5, 0, 1, 1);
+	xrdc_config_mrc_w3_w4(5, 0, 0x0, 0x80000FFF);
+
 	/* The MRC8 is for SRAM1 */
 	xrdc_config_mrc_w0_w1(8, 0, 0x21000000, 0x10000);
 	/* Allow for all domains: So domain 2/3 (HIFI DSP/LPAV) is ok to access */
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 934b0ef038c..38e279a7f6a 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -13,8 +13,8 @@
 #include <efi_loader.h>
 #include <spl.h>
 #include <asm/arch/rdc.h>
-#include <asm/arch/s400_api.h>
-#include <asm/arch/mu_hal.h>
+#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/mu_hal.h>
 #include <cpu_func.h>
 #include <asm/setup.h>
 #include <dm.h>
@@ -23,8 +23,14 @@
 #include <dm/uclass.h>
 #include <dm/device.h>
 #include <dm/uclass-internal.h>
+#include <asm/arch/pcc.h>
 #include <fuse.h>
 #include <thermal.h>
+#include <asm/mach-imx/optee.h>
+#include <env.h>
+#include <env_internal.h>
+#include <linux/iopoll.h>
+#include <thermal.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -65,18 +71,33 @@ enum boot_device get_boot_device(void)
 		boot_dev = QSPI_BOOT;
 		break;
 	case BT_DEV_TYPE_USB:
-		boot_dev = USB_BOOT;
+		boot_dev = boot_instance + USB_BOOT;
 		break;
 	default:
 		break;
 	}
 
+	debug("boot dev %d\n", boot_dev);
+
 	return boot_dev;
 }
 
 bool is_usb_boot(void)
 {
-	return get_boot_device() == USB_BOOT;
+	enum boot_device bt_dev = get_boot_device();
+	return (bt_dev == USB_BOOT || bt_dev == USB2_BOOT);
+}
+
+void disconnect_from_pc(void)
+{
+	enum boot_device bt_dev = get_boot_device();
+
+	if (bt_dev == USB_BOOT)
+		writel(0x0, USBOTG0_RBASE + 0x140);
+	else if (bt_dev == USB2_BOOT)
+		writel(0x0, USBOTG1_RBASE + 0x140);
+
+	return;
 }
 
 #ifdef CONFIG_ENV_IS_IN_MMC
@@ -105,17 +126,44 @@ int mmc_get_env_dev(void)
 	boot_type = boot >> 16;
 	boot_instance = (boot >> 8) & 0xff;
 
+	debug("boot_type %d, instance %d\n", boot_type, boot_instance);
+
 	/* If not boot from sd/mmc, use default value */
-	if (boot_type != BOOT_TYPE_SD && boot_type != BOOT_TYPE_MMC)
+	if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
 		return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV);
 
 	return board_mmc_get_env_dev(boot_instance);
+
 }
 #endif
 
+#ifdef CONFIG_USB_PORT_AUTO
+int board_usb_gadget_port_auto(void)
+{
+    enum boot_device bt_dev = get_boot_device();
+	int usb_boot_index = 0;
+
+	if (bt_dev == USB2_BOOT)
+		usb_boot_index = 1;
+
+	printf("auto usb %d\n", usb_boot_index);
+
+	return usb_boot_index;
+}
+#endif
+
+static void set_cpu_info(struct sentinel_get_info_data *info)
+{
+	gd->arch.soc_rev = info->soc;
+	gd->arch.lifecycle = info->lc;
+	memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32));
+}
+
 u32 get_cpu_rev(void)
 {
-	return (MXC_CPU_IMX8ULP << 12) | CHIP_REV_1_0;
+	u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
+
+	return (MXC_CPU_IMX8ULP << 12) | (CHIP_REV_1_0 + rev);
 }
 
 enum bt_mode get_boot_mode(void)
@@ -136,6 +184,96 @@ enum bt_mode get_boot_mode(void)
 	return LOW_POWER_BOOT;
 }
 
+bool m33_image_booted(void)
+{
+	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+		u32 gp6 = 0;
+
+		/* DGO_GP6 */
+		gp6 = readl(SIM_SEC_BASE_ADDR + 0x28);
+		if (gp6 & (1 << 5))
+			return true;
+
+		return false;
+	} else {
+		u32 gpr0 = readl(SIM1_BASE_ADDR);
+		if (gpr0 & 0x1)
+			return true;
+
+		return false;
+	}
+}
+
+bool rdc_enabled_in_boot(void)
+{
+	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+		u32 val = 0;
+		int ret;
+		bool rdc_en = true; /* Default assume DBD_EN is set */
+
+		/* Read DBD_EN fuse */
+		ret = fuse_read(8, 1, &val);
+		if (!ret)
+			rdc_en = !!(val & 0x200); /* only A1 part uses DBD_EN, so check DBD_EN new place*/
+
+		return rdc_en;
+	} else {
+		u32 gpr0 = readl(SIM1_BASE_ADDR);
+		if (gpr0 & 0x2)
+			return true;
+
+		return false;
+	}
+}
+
+static void spl_pass_boot_info(void)
+{
+	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+		bool m33_booted = m33_image_booted();
+		bool rdc_en = rdc_enabled_in_boot();
+		u32 val = 0;
+
+		if (m33_booted)
+			val |= 0x1;
+
+		if (rdc_en)
+			val |= 0x2;
+
+		writel(val, SIM1_BASE_ADDR);
+	}
+}
+
+bool is_m33_handshake_necessary(void)
+{
+	/* Only need handshake in u-boot */
+	if (!IS_ENABLED(CONFIG_SPL_BUILD))
+		return (m33_image_booted() || rdc_enabled_in_boot());
+	else
+		return false;
+}
+
+int m33_image_handshake(ulong timeout_ms)
+{
+	u32 fsr;
+	int ret;
+	ulong timeout_us = timeout_ms * 1000;
+
+	/* Notify m33 that it's ready to do init srtm(enable mu receive interrupt and so on) */
+	setbits_le32(MU0_B_BASE_ADDR + 0x100, BIT(0)); /* set FCR F0 flag of MU0_MUB */
+
+	/*
+	 * Wait m33 to set FCR F0 flag of MU0_MUA
+	 * Clear FCR F0 flag of MU0_MUB after m33 has set FCR F0 flag of MU0_MUA
+	 */
+	ret = readl_poll_sleep_timeout(MU0_B_BASE_ADDR + 0x104,
+		fsr, fsr & BIT(0), 10, timeout_us);
+	if (ret == 0)
+		clrbits_le32(MU0_B_BASE_ADDR + 0x100, BIT(0));
+
+	return ret;
+}
+
+
 #define CMC_SRS_TAMPER                    BIT(31)
 #define CMC_SRS_SECURITY                  BIT(30)
 #define CMC_SRS_TZWDG                     BIT(29)
@@ -217,7 +355,7 @@ int print_cpuinfo(void)
 	       (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
 	       mxc_get_clock(MXC_ARM_CLK) / 1000000);
 
-#if defined(CONFIG_IMX_PMC_TEMPERATURE)
+#if defined(CONFIG_SCMI_THERMAL)
 	struct udevice *udev;
 	int ret, temp;
 
@@ -262,15 +400,12 @@ static void disable_wdog(void __iomem *wdog_base)
 {
 	u32 val_cs = readl(wdog_base + 0x00);
 
-	if (!(val_cs & 0x80))
-		return;
-
 	dmb();
 	__raw_writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
 	__raw_writel(REFRESH_WORD1, (wdog_base + 0x04));
 	dmb();
 
-	if (!(val_cs & 800)) {
+	if (!(val_cs & 0x800)) {
 		dmb();
 		__raw_writel(UNLOCK_WORD0, (wdog_base + 0x04));
 		__raw_writel(UNLOCK_WORD1, (wdog_base + 0x04));
@@ -281,7 +416,7 @@ static void disable_wdog(void __iomem *wdog_base)
 	}
 	writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
 	writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
-	writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
+	writel(0x2120, (wdog_base + 0x00)); /* Change to 32bit cmd, disable it and set update */
 
 	while (!(readl(wdog_base + 0x00) & 0x400))
 		;
@@ -364,7 +499,11 @@ static struct mm_region imx8ulp_arm64_mem_map[] = {
 		.phys = 0x80000000UL,
 		.size = PHYS_SDRAM_SIZE,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+#ifdef CONFIG_IMX_TRUSTY_OS
+			 PTE_BLOCK_INNER_SHARE
+#else
 			 PTE_BLOCK_OUTER_SHARE
+#endif
 	}, {
 		/*
 		 * empty entrie to split table entry 5
@@ -379,6 +518,17 @@ static struct mm_region imx8ulp_arm64_mem_map[] = {
 
 struct mm_region *mem_map = imx8ulp_arm64_mem_map;
 
+static unsigned int imx8ulp_find_dram_entry_in_mem_map(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(imx8ulp_arm64_mem_map); i++)
+		if (imx8ulp_arm64_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
+			return i;
+
+	hang();	/* Entry not found, this must never happen. */
+}
+
 /* simplify the page table size to enhance boot speed */
 #define MAX_PTE_ENTRIES		512
 #define MAX_MEM_MAP_REGIONS	16
@@ -410,20 +560,107 @@ u64 get_page_table_size(void)
 
 void enable_caches(void)
 {
-	/* TODO: add TEE memmap region */
+	/* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
+	if (rom_pointer[1]) {
+		/*
+		 * TEE are loaded, So the ddr bank structures
+		 * have been modified update mmu table accordingly
+		 */
+		int i = 0;
+		int entry = imx8ulp_find_dram_entry_in_mem_map();
+		u64 attrs = imx8ulp_arm64_mem_map[entry].attrs;
+
+		while (i < CONFIG_NR_DRAM_BANKS &&
+		       entry < ARRAY_SIZE(imx8ulp_arm64_mem_map)) {
+			if (gd->bd->bi_dram[i].start == 0)
+				break;
+			imx8ulp_arm64_mem_map[entry].phys = gd->bd->bi_dram[i].start;
+			imx8ulp_arm64_mem_map[entry].virt = gd->bd->bi_dram[i].start;
+			imx8ulp_arm64_mem_map[entry].size = gd->bd->bi_dram[i].size;
+			imx8ulp_arm64_mem_map[entry].attrs = attrs;
+			debug("Added memory mapping (%d): %llx %llx\n", entry,
+			      imx8ulp_arm64_mem_map[entry].phys, imx8ulp_arm64_mem_map[entry].size);
+			i++; entry++;
+		}
+	}
 
 	icache_enable();
 	dcache_enable();
 }
 
+__weak int board_phys_sdram_size(phys_size_t *size)
+{
+	if (!size)
+		return -EINVAL;
+
+	*size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
 int dram_init(void)
 {
-	gd->ram_size = PHYS_SDRAM_SIZE;
+	unsigned int entry = imx8ulp_find_dram_entry_in_mem_map();
+	phys_size_t sdram_size;
+	int ret;
 
+	ret = board_phys_sdram_size(&sdram_size);
+	if (ret)
+		return ret;
+
+	/* rom_pointer[1] contains the size of TEE occupies */
+	if (rom_pointer[1])
+		gd->ram_size = sdram_size - rom_pointer[1];
+	else
+		gd->ram_size = sdram_size;
+
+	/* also update the SDRAM size in the mem_map used externally */
+	imx8ulp_arm64_mem_map[entry].size = sdram_size;
 	return 0;
 }
 
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+int dram_init_banksize(void)
+{
+	int bank = 0;
+	int ret;
+	phys_size_t sdram_size;
+
+	ret = board_phys_sdram_size(&sdram_size);
+	if (ret)
+		return ret;
+
+	gd->bd->bi_dram[bank].start = PHYS_SDRAM;
+	if (rom_pointer[1]) {
+		phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
+		phys_size_t optee_size = (size_t)rom_pointer[1];
+
+		gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
+		if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
+			if (++bank >= CONFIG_NR_DRAM_BANKS) {
+				puts("CONFIG_NR_DRAM_BANKS is not enough\n");
+				return -1;
+			}
+
+			gd->bd->bi_dram[bank].start = optee_start + optee_size;
+			gd->bd->bi_dram[bank].size = PHYS_SDRAM +
+				sdram_size - gd->bd->bi_dram[bank].start;
+		}
+	} else {
+		gd->bd->bi_dram[bank].size = sdram_size;
+	}
+
+	return 0;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+	/* return the first bank as effective memory */
+	if (rom_pointer[1])
+		return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
+
+	return gd->ram_size;
+}
+
+#if defined(CONFIG_SERIAL_TAG) || defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 void get_board_serial(struct tag_serialnr *serialnr)
 {
 	u32 uid[4];
@@ -460,40 +697,72 @@ static void set_core0_reset_vector(u32 entry)
 	setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26));
 }
 
-static int trdc_set_access(void)
+/* Not used now */
+int trdc_set_access(void)
 {
 	/*
 	 * TRDC mgr + 4 MBC + 2 MRC.
-	 * S400 should already configure when release RDC
-	 * A35 only map non-secure region for pbridge0 and 1, set sec_access to false
 	 */
-	trdc_mbc_set_access(2, 7, 0, 49, false);
-	trdc_mbc_set_access(2, 7, 0, 50, false);
-	trdc_mbc_set_access(2, 7, 0, 51, false);
-	trdc_mbc_set_access(2, 7, 0, 52, false);
-	trdc_mbc_set_access(2, 7, 0, 53, false);
-	trdc_mbc_set_access(2, 7, 0, 54, false);
-
-	/* CGC0: PBridge0 slot 47 */
+	trdc_mbc_set_access(2, 7, 0, 49, true);
+	trdc_mbc_set_access(2, 7, 0, 50, true);
+	trdc_mbc_set_access(2, 7, 0, 51, true);
+	trdc_mbc_set_access(2, 7, 0, 52, true);
+	trdc_mbc_set_access(2, 7, 0, 53, true);
+	trdc_mbc_set_access(2, 7, 0, 54, true);
+
+	/* 0x1fff8000 used for resource table by remoteproc */
+	trdc_mbc_set_access(0, 7, 2, 31, false);
+
+	/* CGC0: PBridge0 slot 47 and PCC0 slot 48 */
 	trdc_mbc_set_access(2, 7, 0, 47, false);
+	trdc_mbc_set_access(2, 7, 0, 48, false);
+
+	/* PCC1 */
+	trdc_mbc_set_access(2, 7, 1, 17, false);
+	trdc_mbc_set_access(2, 7, 1, 34, false);
 
 	/* Iomuxc0: : PBridge1 slot 33 */
 	trdc_mbc_set_access(2, 7, 1, 33, false);
 
 	/* flexspi0 */
+	trdc_mbc_set_access(2, 7, 0, 57, false);
 	trdc_mrc_region_set_access(0, 7, 0x04000000, 0x0c000000, false);
 
 	/* tpm0: PBridge1 slot 21 */
 	trdc_mbc_set_access(2, 7, 1, 21, false);
 	/* lpi2c0: PBridge1 slot 24 */
 	trdc_mbc_set_access(2, 7, 1, 24, false);
+
+	/* Allow M33 to access TRDC MGR */
+	trdc_mbc_set_access(2, 6, 0, 49, true);
+	trdc_mbc_set_access(2, 6, 0, 50, true);
+	trdc_mbc_set_access(2, 6, 0, 51, true);
+	trdc_mbc_set_access(2, 6, 0, 52, true);
+	trdc_mbc_set_access(2, 6, 0, 53, true);
+	trdc_mbc_set_access(2, 6, 0, 54, true);
+
+	/* Set SAI0 for eDMA 0, NS */
+	trdc_mbc_set_access(2, 0, 1, 28, false);
+
+	/* Set SSRAM for eDMA0 access */
+	trdc_mbc_set_access(0, 0, 2, 0, false);
+	trdc_mbc_set_access(0, 0, 2, 1, false);
+	trdc_mbc_set_access(0, 0, 2, 2, false);
+	trdc_mbc_set_access(0, 0, 2, 3, false);
+	trdc_mbc_set_access(0, 0, 2, 4, false);
+	trdc_mbc_set_access(0, 0, 2, 5, false);
+	trdc_mbc_set_access(0, 0, 2, 6, false);
+	trdc_mbc_set_access(0, 0, 2, 7, false);
+
+	writel(0x800000a0, 0x28031840);
+
 	return 0;
 }
 
-void lpav_configure(void)
+void lpav_configure(bool lpav_to_m33)
 {
-	/* LPAV to APD */
-	setbits_le32(SIM_SEC_BASE_ADDR + 0x44, BIT(7));
+	if (!lpav_to_m33)
+		setbits_le32(SIM_SEC_BASE_ADDR + 0x44, BIT(7)); /* LPAV to APD */
 
 	/* PXP/GPU 2D/3D/DCNANO/MIPI_DSI/EPDC/HIFI4 to APD */
 	setbits_le32(SIM_SEC_BASE_ADDR + 0x4c, 0x7F);
@@ -533,34 +802,37 @@ void set_lpav_qos(void)
 int arch_cpu_init(void)
 {
 	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
-		u32 val = 0;
-		int ret;
-		bool rdc_en = true; /* Default assume DBD_EN is set */
+		/* Enable System Reset Interrupt using WDOG_AD */
+		setbits_le32(CMC1_BASE_ADDR + 0x8C, BIT(13));
+		/* Clear AD_PERIPH Power switch domain out of reset interrupt flag */
+		setbits_le32(CMC1_BASE_ADDR + 0x70, BIT(4));
+
+		if (readl(CMC1_BASE_ADDR + 0x90) & BIT(13)) {
+			/* Clear System Reset Interrupt Flag Register of WDOG_AD */
+			setbits_le32(CMC1_BASE_ADDR + 0x90, BIT(13));
+			/* Reset WDOG to clear reset request */
+			pcc_reset_peripheral(3, WDOG3_PCC3_SLOT, true);
+			pcc_reset_peripheral(3, WDOG3_PCC3_SLOT, false);
+		}
 
 		/* Disable wdog */
 		init_wdog();
 
-		/* Read DBD_EN fuse */
-		ret = fuse_read(8, 1, &val);
-		if (!ret)
-			rdc_en = !!(val & 0x4000);
-
 		if (get_boot_mode() == SINGLE_BOOT) {
-			if (rdc_en)
-				release_rdc(RDC_TRDC);
-
-			trdc_set_access();
-
-			lpav_configure();
+			lpav_configure(false);
+		} else {
+			lpav_configure(true);
 		}
 
 		/* Release xrdc, then allow A35 to write SRAM2 */
-		if (rdc_en)
+		if (rdc_enabled_in_boot())
 			release_rdc(RDC_XRDC);
 
 		xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00);
 
-		clock_init();
+		clock_init_early();
+
+		spl_pass_boot_info();
 	} else {
 		/* reconfigure core0 reset vector to ROM */
 		set_core0_reset_vector(0x1000);
@@ -569,10 +841,34 @@ int arch_cpu_init(void)
 	return 0;
 }
 
+int checkcpu(void)
+{
+	if (is_m33_handshake_necessary()) {
+		if (!gd->arch.m33_handshake_done)
+			panic("M33 Sync: Timeout, Boot Stop!\n");
+		else
+			puts("M33 Sync: OK\n");
+	}
+	return 0;
+}
+
 int arch_cpu_init_dm(void)
 {
 	struct udevice *devp;
 	int node, ret;
+	u32 res;
+	struct sentinel_get_info_data info;
+
+	if (!IS_ENABLED(CONFIG_SPL_BUILD) && is_m33_handshake_necessary()) {
+		/* Start handshake with M33 to ensure TRDC configuration completed */
+		ret = m33_image_handshake(1000);
+		if (!ret) {
+			gd->arch.m33_handshake_done = true;
+		} else {
+			gd->arch.m33_handshake_done = false;
+			return 0; /* Skip and go through to panic in checkcpu as console is ready then */
+		}
+	}
 
 	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8ulp-mu");
 
@@ -582,8 +878,52 @@ int arch_cpu_init_dm(void)
 		return ret;
 	}
 
+	ret = ahab_get_info(&info, &res);
+	if (ret) {
+		printf("ahab_get_info failed %d\n", ret);
+		/* fallback to A0.1 revision */
+		memset((void *)&info, 0, sizeof(struct sentinel_get_info_data));
+		info.soc = 0xa000084d;
+	}
+
+	set_cpu_info(&info);
+
+	return 0;
+}
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+		struct udevice *dev;
+		int ret;
+
+		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+		if (ret)
+			printf("Failed to initialize caam_jr: %d\n", ret);
+	}
+
 	return 0;
 }
+#endif
+
+#ifdef CONFIG_ARCH_EARLY_INIT_R
+int arch_early_init_r(void)
+{
+	struct udevice *devp;
+	int node, ret;
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8ulp-mu");
+
+	ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
+	if (ret) {
+		printf("could not get S400 mu %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+#endif
 
 #if defined(CONFIG_SPL_BUILD)
 __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
@@ -635,8 +975,79 @@ int (*card_emmc_is_boot_part_en)(void) = (void *)0x67cc;
 u32 spl_arch_boot_image_offset(u32 image_offset, u32 rom_bt_dev)
 {
 	/* Hard code for eMMC image_offset on 8ULP ROM, need fix by ROM, temp workaround */
-	if (((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_MMC && card_emmc_is_boot_part_en())
+	if (is_soc_rev(CHIP_REV_1_0) && ((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_MMC &&
+		card_emmc_is_boot_part_en())
 		image_offset = 0;
 
 	return image_offset;
 }
+
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+	u32 uid[4];
+	u32 res;
+	int ret;
+	int nodeoff = fdt_path_offset(blob, "/soc");
+	/* Nibble 1st for major version
+	 * Nibble 0th for minor version.
+	 */
+	const u32 rev = 0x10;
+
+	if (nodeoff < 0) {
+		printf("Node to update the SoC serial number is not found.\n");
+		goto skip_upt;
+	}
+
+	ret = ahab_read_common_fuse(1, uid, 4, &res);
+	if (ret) {
+		printf("ahab read fuse failed %d, 0x%x\n", ret, res);
+		memset(uid, 0x0, 4 * sizeof(u32));
+	}
+
+	ret = fdt_setprop_u32(blob, nodeoff, "soc-rev", rev);
+	if (ret)
+		printf("Error[0x%x] fdt_setprop revision-number.\n", ret);
+
+	ret = fdt_setprop_u64(blob, nodeoff, "soc-serial",
+				(u64)uid[3] << 32 | uid[0]);
+	if (ret)
+		printf("Error[0x%x] fdt_setprop serial-number.\n", ret);
+
+
+skip_upt:
+	return ft_add_optee_node(blob, bd);
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	enum boot_device dev = get_boot_device();
+	enum env_location env_loc = ENVL_UNKNOWN;
+
+	if (prio)
+		return env_loc;
+
+	switch (dev) {
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+	case QSPI_BOOT:
+		env_loc = ENVL_SPI_FLASH;
+		break;
+#endif
+#ifdef CONFIG_ENV_IS_IN_MMC
+	case SD1_BOOT:
+	case SD2_BOOT:
+	case SD3_BOOT:
+	case MMC1_BOOT:
+	case MMC2_BOOT:
+	case MMC3_BOOT:
+		env_loc =  ENVL_MMC;
+		break;
+#endif
+	default:
+#if defined(CONFIG_ENV_IS_NOWHERE)
+		env_loc = ENVL_NOWHERE;
+#endif
+		break;
+	}
+
+	return env_loc;
+}
diff --git a/arch/arm/mach-imx/imx8ulp/upower/upmu.h b/arch/arm/mach-imx/imx8ulp/upower/upmu.h
new file mode 100644
index 00000000000..919d3ccc3c2
--- /dev/null
+++ b/arch/arm/mach-imx/imx8ulp/upower/upmu.h
@@ -0,0 +1,336 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef _MU_H_
+#define _MU_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+#ifdef __MWERKS__
+#pragma push
+#pragma ANSI_strict off
+#endif
+#ifdef __ghs__
+#pragma ghs nowarning 618
+#endif
+#ifdef __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+#include <stdint.h>
+typedef volatile unsigned int vuint32_t;
+
+/****************************************************************************/
+/*                              MODULE: MU                    */
+/****************************************************************************/
+
+/***************************Configuration Registers**************************/
+
+
+
+typedef union MU_VER_union_tag {       /* VER Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t FEATURE   :16; // FEATURE Number
+    vuint32_t MINOR     : 8; // MINOR Number
+    vuint32_t MAJOR     : 8; // MAJOR Number
+  } B;
+} MU_VER_tag;
+
+
+typedef union MU_PAR_union_tag {       /* PAR Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t TR_NUM    : 8; // TR_NUM Number
+    vuint32_t RR_NUM    : 8; // RR_NUM Number
+    vuint32_t GIR_NUM   : 8; // GIR_NUM Number
+    vuint32_t FLAG_WIDTH: 8; // FLAG_WIDTH Number
+  } B;
+} MU_PAR_tag;
+
+
+typedef union MU_CR_union_tag {       /* CR Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t MUR       : 1; // MUR Number
+    vuint32_t MURIE     : 1; // MURIE Number
+    vuint32_t rsrv_1    :30; // rsrv_1 Number
+  } B;
+} MU_CR_tag;
+
+
+typedef union MU_SR_union_tag {       /* SR Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t MURS      : 1; // MURS Number
+    vuint32_t MURIP     : 1; // MURIP Number
+    vuint32_t EP        : 1; // EP Number
+    vuint32_t FUP       : 1; // FUP Number
+    vuint32_t GIRP      : 1; // GIRP Number
+    vuint32_t TEP       : 1; // TEP Number
+    vuint32_t RFP       : 1; // RFP Number
+    vuint32_t CEP       : 1; // CEP Number
+    vuint32_t rsrv_1    :24; // rsrv_1 Number
+  } B;
+} MU_SR_tag;
+
+
+typedef union MU_CCR0_union_tag {       /* CCR0 Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t NMI       : 1; // NMI Number
+    vuint32_t HR        : 1; // HR Number
+    vuint32_t HRM       : 1; // HRM Number
+    vuint32_t CLKE      : 1; // CLKE Number
+    vuint32_t RSTH      : 1; // RSTH Number
+    vuint32_t BOOT      : 2; // BOOT Number
+    vuint32_t rsrv_1    :25; // rsrv_1 Number
+  } B;
+} MU_CCR0_tag;
+
+
+typedef union MU_CIER0_union_tag {       /* CIER0 Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t rsrv_1    : 1; // rsrv_1 Number
+    vuint32_t HRIE      : 1; // HRIE Number
+    vuint32_t RUNIE     : 1; // RUNIE Number
+    vuint32_t RAIE      : 1; // RAIE Number
+    vuint32_t HALTIE    : 1; // HALTIE Number
+    vuint32_t WAITIE    : 1; // WAITIE Number
+    vuint32_t STOPIE    : 1; // STOPIE Number
+    vuint32_t PDIE      : 1; // PDIE Number
+    vuint32_t rsrv_2    :24; // rsrv_2 Number
+  } B;
+} MU_CIER0_tag;
+
+
+typedef union MU_CSSR0_union_tag {       /* CSSR0 Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t NMIC      : 1; // NMIC Number
+    vuint32_t HRIP      : 1; // HRIP Number
+    vuint32_t RUN       : 1; // RUN Number
+    vuint32_t RAIP      : 1; // RAIP Number
+    vuint32_t HALT      : 1; // HALT Number
+    vuint32_t WAIT      : 1; // WAIT Number
+    vuint32_t STOP      : 1; // STOP Number
+    vuint32_t PD        : 1; // PD Number
+    vuint32_t rsrv_1    :24; // rsrv_1 Number
+  } B;
+} MU_CSSR0_tag;
+
+
+typedef union MU_CSR0_union_tag {       /* CSR0 Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t rsrv_1    : 1; // rsrv_1 Number
+    vuint32_t HRIP      : 1; // HRIP Number
+    vuint32_t RUN       : 1; // RUN Number
+    vuint32_t RAIP      : 1; // RAIP Number
+    vuint32_t HALT      : 1; // HALT Number
+    vuint32_t WAIT      : 1; // WAIT Number
+    vuint32_t STOP      : 1; // STOP Number
+    vuint32_t PD        : 1; // PD Number
+    vuint32_t rsrv_2    :24; // rsrv_2 Number
+  } B;
+} MU_CSR0_tag;
+
+
+typedef union MU_FCR_union_tag {       /* FCR Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t F0        : 1; // F0 Number
+    vuint32_t F1        : 1; // F1 Number
+    vuint32_t F2        : 1; // F2 Number
+    vuint32_t rsrv_1    :29; // rsrv_1 Number
+  } B;
+} MU_FCR_tag;
+
+
+typedef union MU_FSR_union_tag {       /* FSR Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t F0        : 1; // F0 Number
+    vuint32_t F1        : 1; // F1 Number
+    vuint32_t F2        : 1; // F2 Number
+    vuint32_t rsrv_1    :29; // rsrv_1 Number
+  } B;
+} MU_FSR_tag;
+
+
+typedef union MU_GIER_union_tag {       /* GIER Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t GIE0      : 1; // GIE0 Number
+    vuint32_t GIE1      : 1; // GIE1 Number
+    vuint32_t rsrv_1    :30; // rsrv_1 Number
+  } B;
+} MU_GIER_tag;
+
+
+typedef union MU_GCR_union_tag {       /* GCR Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t GIR0      : 1; // GIR0 Number
+    vuint32_t GIR1      : 1; // GIR1 Number
+    vuint32_t rsrv_1    :30; // rsrv_1 Number
+  } B;
+} MU_GCR_tag;
+
+
+typedef union MU_GSR_union_tag {       /* GSR Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t GIP0      : 1; // GIP0 Number
+    vuint32_t GIP1      : 1; // GIP1 Number
+    vuint32_t rsrv_1    :30; // rsrv_1 Number
+  } B;
+} MU_GSR_tag;
+
+
+typedef union MU_TCR_union_tag {       /* TCR Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t TIE0      : 1; // TIE0 Number
+    vuint32_t TIE1      : 1; // TIE1 Number
+    vuint32_t rsrv_1    :30; // rsrv_1 Number
+  } B;
+} MU_TCR_tag;
+
+
+typedef union MU_TSR_union_tag {       /* TSR Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t TE0       : 1; // TE0 Number
+    vuint32_t TE1       : 1; // TE1 Number
+    vuint32_t rsrv_1    :30; // rsrv_1 Number
+  } B;
+} MU_TSR_tag;
+
+
+typedef union MU_RCR_union_tag {       /* RCR Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t RIE0      : 1; // RIE0 Number
+    vuint32_t RIE1      : 1; // RIE1 Number
+    vuint32_t rsrv_1    :30; // rsrv_1 Number
+  } B;
+} MU_RCR_tag;
+
+
+typedef union MU_RSR_union_tag {       /* RSR Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t RF0       : 1; // RF0 Number
+    vuint32_t RF1       : 1; // RF1 Number
+    vuint32_t rsrv_1    :30; // rsrv_1 Number
+  } B;
+} MU_RSR_tag;
+
+
+typedef union MU_TR0_union_tag {       /* TR0 Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t TR_DATA   :32; // TR_DATA Number
+  } B;
+} MU_TR0_tag;
+
+
+typedef union MU_TR1_union_tag {       /* TR1 Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t TR_DATA   :32; // TR_DATA Number
+  } B;
+} MU_TR1_tag;
+
+
+typedef union MU_RR0_union_tag {       /* RR0 Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t RR_DATA   :32; // RR_DATA Number
+  } B;
+} MU_RR0_tag;
+
+
+typedef union MU_RR1_union_tag {       /* RR1 Register */
+
+  vuint32_t R;
+  struct{
+    vuint32_t RR_DATA   :32; // RR_DATA Number
+  } B;
+} MU_RR1_tag;
+
+
+
+struct MU_tag  {
+
+
+  MU_VER_tag              VER       ;      //VER Register
+  MU_PAR_tag              PAR       ;      //PAR Register
+  MU_CR_tag               CR        ;      //CR Register
+  MU_SR_tag               SR        ;      //SR Register
+  MU_CCR0_tag             CCR0      ;      //CCR0 Register
+  MU_CIER0_tag            CIER0     ;      //CIER0 Register
+  MU_CSSR0_tag            CSSR0     ;      //CSSR0 Register
+  MU_CSR0_tag             CSR0      ;      //CSR0 Register
+  uint8_t MU_reserved0[224];
+  MU_FCR_tag              FCR       ;      //FCR Register
+  MU_FSR_tag              FSR       ;      //FSR Register
+  uint8_t MU_reserved1[8];
+  MU_GIER_tag             GIER      ;      //GIER Register
+  MU_GCR_tag              GCR       ;      //GCR Register
+  MU_GSR_tag              GSR       ;      //GSR Register
+  uint8_t MU_reserved2[4];
+  MU_TCR_tag              TCR       ;      //TCR Register
+  MU_TSR_tag              TSR       ;      //TSR Register
+  MU_RCR_tag              RCR       ;      //RCR Register
+  MU_RSR_tag              RSR       ;      //RSR Register
+  uint8_t MU_reserved3[208];
+  MU_TR0_tag              TR[2]       ;      //TR0 Register
+  //MU_TR1_tag              TR1       ;      //TR1 Register
+  uint8_t MU_reserved4[120];
+  MU_RR0_tag              RR[2]       ;      //RR0 Register
+  //MU_RR1_tag              RR1       ;      //RR1 Register
+
+};
+
+
+
+#ifdef __MWERKS__
+#pragma pop
+#endif
+#ifdef __ghs__
+#pragma ghs endnowarning
+#endif
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+#ifdef  __cplusplus
+}
+#endif
+#endif /* ifdef _MU_H_ */
+
diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_api.c b/arch/arm/mach-imx/imx8ulp/upower/upower_api.c
index 5e19b9861f0..524b1afbedf 100644
--- a/arch/arm/mach-imx/imx8ulp/upower/upower_api.c
+++ b/arch/arm/mach-imx/imx8ulp/upower/upower_api.c
@@ -1,351 +1,710 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright 2021 NXP
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* +FHDR----------------------------------------------------------------------
+ * Copyright 2019-2021 NXP
+ * ---------------------------------------------------------------------------
+ * FILE NAME      : upower_api.c
+ * DEPARTMENT     : BSTC - Campinas, Brazil
+ * AUTHOR         : Celso Brites
+ * AUTHOR'S EMAIL : celso.brites@nxp.com
+ * ---------------------------------------------------------------------------
+ * RELEASE HISTORY
+ * VERSION DATE        AUTHOR                  DESCRIPTION
+ *
+ * $Log: upower_api.c.rca $
+ *
+ *  Revision: 1.216 Fri May 28 06:27:06 2021 nxa55768
+ *  powersys_fw_048.011.012.006
+ *
+ *
+ *  Revision: 1.215 Fri Apr 30 06:27:06 2021 nxa10721
+ *  powersys_fw_048.011.012.006
+ *
+ *  Revision: 1.62 Tue Apr 27 12:43:01 2021 nxa11511
+ *  Spec review fixes.
+ *  Fixes uninitialized variable in upwr_pwm_power_on, upwr_pwm_power_off, upwr_pwm_chng_switch_mem.
+ *  Adds new service upwr_pwm_reg_config.
+ *
+ *  Revision: 1.54 Fri Oct 23 13:19:58 2020 nxa11511
+ *  Deleted the GPL license statements, leaving only BSD, as it is compatible with Linux and good for closed ROM/firmware code.
+ *
+ *  Revision: 1.53 Thu Sep 24 16:42:38 2020 nxa11511
+ *  Fixes API buffer base setting.
+ *
+ *  Revision: 1.51 Wed Sep 16 15:58:44 2020 nxa11511
+ *  Fixes the APD/RTD API buffer overlap issue using new #defines and tupedefs in upower_soc_defs.h
+ *
+ *  Revision: 1.39 Sun Jun 21 14:34:54 2020 nxa11511
+ *  Fixes compilation outside block-level testbench.
+ *
+ *  Revision: 1.25 Tue Mar 10 06:23:23 2020 nxa11511
+ *  Fixes copying of argument structs to shared memory.
+ *  Fixes shared memory argument buffer size, fixing TKT0534585.
+ *
+ *  Revision: 1.24 Mon Mar  2 12:25:32 2020 nxa11511
+ *  Updates comments to the new version 20200222.
+ *  upwr_start callback now checks start error, doesn't change API state in case.
+ *  Adds same-domain checks in calls with domain argument.
+ *  Updates upwr_start to the new definition.
+ *
+ *  Revision: 1.17 Mon Jan 27 20:18:07 2020 nxa10721
+ *  powersys_fw_021.002.000.004
+ *
+ *  Revision: 1.19 Mon Jan 27 15:29:03 2020 nxa11511
+ *  Adds memcpy, under #ifdef NO_MEMCPY.
+ *
+ *  Revision: 1.13 Fri Sep 27 10:54:30 2019 nxa13158
+ *  added if NULL condition to check if user_callback exists
+ *
+ *  Revision: 1.12 Mon Sep  9 23:54:18 2019 nxa16953
+ *  Updated based on latest register structs.
+ *
+ *  Revision: 1.11 Fri Aug 23 17:51:07 2019 nxa11511
+ *  Adds macros to simplify service request implementation.
+ *  Adds shutdown support.
+ *  Adds some message field asserts.
+ *  Bug fixes.
+ *  Changes ok/ko response to an error code.
+ *  Adds Exception service requests.
+ *  Adds bias setting functions and Diagnostic mode function.
+ *  full implementation of the API spec in shared review (version 20190818).
+ *
+ *  Revision: 1.8 Wed Aug 14 13:45:13 2019 nxa11511
+ *  Fixes compilation for simulation.
+ *
+ *  Revision: 1.7 Wed Aug 14 07:10:53 2019 nxa11511
+ *  Partial editing only, not compiled, not tested:
+ *  - updates upwr_init to the latest spec, including new argument waitinit.
+ *  - bug fixes.
+ *  - Rx and Tx interrupts treated in the same ISR.
+ *
+ *  Revision: 1.3 Sat Aug 10 09:04:32 2019 nxa11511
+ *  No longer gets UPWR_NAMESPACE.
+ *  Fixes some strict compiling errors.
+ *
+ *  Revision: 1.1 Fri Aug  2 14:28:58 2019 nxa11511
+ *  mvfile on Fri Aug  2 14:28:58 2019 by user nxa11511.
+ *  Originated from sync://sync-15088:15088/Projects/common_blocks/da_ip_ahb_upower_subsys_ln28fdsoi_tb/vectors/firmware/stimulus/src/drvapi/vers0/upower_api.cc;1.8
+ *
+ *  Revision: 1.8 Fri Aug  2 14:28:40 2019 nxa11511
+ *  Adapted to Linux coding guidelines.
+ *  Converted to C (no longer using C++ features).
+ *
+ *  Revision: 1.7 Wed Jun 12 15:44:39 2019 nxa11511
+ *  Number of MUs now #defined by UPWR_MU_INSTANCES.
+ *  Adds optional namespace definition with #define UPWR_NAMESPACE.
+ *  No longer disables interrupt at the ISR start (automatically done by CAPI).
+ *
+ *  Revision: 1.5 Wed Apr 10 14:43:35 2019 nxa11511
+ *  Several bug fixes.
+ *
+ * -----------------------------------------------------------------------------
+ * KEYWORDS: micro-power uPower driver API
+ * -----------------------------------------------------------------------------
+ * PURPOSE: uPower driver API
+ * -----------------------------------------------------------------------------
+ * PARAMETERS:
+ * PARAM NAME RANGE:DESCRIPTION:       DEFAULTS:                           UNITS
+ * -----------------------------------------------------------------------------
+ * REUSE ISSUES: no reuse issues
+ * -FHDR------------------------------------------------------------------------
  */
 
-#include <linux/types.h>
-#include <string.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/io.h>
+#include "upower_soc_defs.h"
 #include "upower_api.h"
 
-enum upwr_api_state api_state;
-enum soc_domain pwr_domain;
-void *sh_buffer[UPWR_SG_COUNT];
-struct upwr_code_vers fw_rom_version;
-struct upwr_code_vers fw_ram_version;
-u32 fw_launch_option;
-u32 sg_busy;
-struct mu_type *mu;
-upwr_up_max_msg sg_rsp_msg[UPWR_SG_COUNT];
-upwr_callb user_callback[UPWR_SG_COUNT];
-UPWR_RX_CALLB_FUNC_T  sgrp_callback[UPWR_SG_COUNT];
-u32 sg_rsp_siz[UPWR_SG_COUNT];
-
-#define UPWR_MU_MSG_SIZE            (2)
-#define UPWR_SG_BUSY(sg) (sg_busy & (1 << (sg)))
-#define UPWR_USR_CALLB(sg, cb)		\
-	do {				\
-		user_callback[sg] = cb;	\
-	} while (0)
-#define UPWR_MSG_HDR(hdr, sg, fn)		\
-	(hdr).domain   = (u32)pwr_domain;	\
-	(hdr).srvgrp   = sg;			\
-	(hdr).function = fn
-
-static u32 upwr_ptr2offset(u64 ptr, enum upwr_sg sg, size_t siz, size_t offset, const void *vptr)
-{
-	if (ptr >= UPWR_DRAM_SHARED_BASE_ADDR &&
-	    ((ptr - UPWR_DRAM_SHARED_BASE_ADDR) < UPWR_DRAM_SHARED_SIZE)) {
-		return (u32)(ptr - UPWR_DRAM_SHARED_BASE_ADDR);
-	}
+#ifdef  UPWR_BLOCK_LEVEL
 
-	/* pointer is outside the shared memory, copy the struct to buffer */
-	memcpy(offset + (char *)sh_buffer[sg], (void *)vptr, siz);
+#include "capi_wrapper.h"
+#include "CAPI_RAM.hh"
 
-	return (u32)((u64)sh_buffer[sg] + offset - UPWR_DRAM_SHARED_BASE_ADDR);
-}
+#define UPWR_API_ASSERT(c) do { if (!(c)) { ERROR("upower_api.c", "assert failed @line " UPWR_API_STRING(__LINE__)); }} while (0)
 
-enum upwr_req_status upwr_req_status(enum upwr_sg sg, u32 *sgfptr, enum upwr_resp *errptr,
-				     int *retptr)
-{
-	enum upwr_req_status status;
+#else
 
-	status = (sg_rsp_msg[sg].hdr.errcode == UPWR_RESP_OK) ? UPWR_REQ_OK : UPWR_REQ_ERR;
+#define UPWR_API_ASSERT(c) do {} while (0)
 
-	return status;
-}
+#ifdef NO_MEMCPY
 
-void upwr_copy2tr(struct mu_type *mu, const u32 *msg, u32 size)
+typedef unsigned int size_t;
+
+void *memcpy(void *dest, const void *src, size_t n)
 {
-	int i;
+	uint32_t *ldest = (uint32_t*) dest;
+	uint32_t *lsrc  = (uint32_t*) src;
+
+	while (n > 3) {
+		*(ldest++) = *(lsrc++);
+		n -= 4;
+	}
 
-	for (i = size - 1; i > -1; i--)
-		writel(msg[i], &mu->tr[i]);
+	if (n > 0) {
+		uint8_t  *bdest = (uint8_t*) ldest;
+		uint8_t  *bsrc  = (uint8_t*) lsrc;
+
+		while (n > 0) {
+			*(bdest++) = *(bsrc++);
+			n--;
+		}
+	}
+
+	return dest;
 }
+#else
+#include <string.h>
+#endif /* NO_MEMCPY */
 
-int upwr_tx(const u32 *msg, u32 size)
-{
-	if (size > UPWR_MU_MSG_SIZE)
-		return -2;
-	if (!size)
-		return -2;
+#endif /* not block-level code */
 
-	if (readl(&mu->tsr) != UPWR_MU_TSR_EMPTY)
-		return -1;  /* not all TE bits in 1: some data to send still */
+#ifndef __UPWR_API_CODE__
+#define __UPWR_API_CODE__
+#endif
 
-	upwr_copy2tr(mu, msg, size);
-	writel(1 << (size - 1), &mu->tcr);
+#ifndef __UPWR_API_DATA__
+#define __UPWR_API_DATA__
+#endif
 
-	return 0;
-}
+#ifndef __UPWR_API_SHARED_RAM__
+#define __UPWR_API_SHARED_RAM__
+#endif
 
-void upwr_srv_req(enum upwr_sg sg, u32 *msg, u32 size)
-{
-	sg_busy |= 1 << sg;
+#define UPWR_API_STR(s)     #s
+#define UPWR_API_STRING(s)     UPWR_API_STR(s)
+#define UPWR_API_CNCT(a,b)   a##b
+#define UPWR_API_CONCAT(a,b) UPWR_API_CNCT(a,b)
 
-	upwr_tx(msg, size);
-}
 
-int upwr_pwm_power_on(const u32 swton[], const u32 memon[], upwr_callb callb)
-{
-	upwr_pwm_pwron_msg txmsg;
-	u64 ptrval; /* needed for X86, ARM64 */
-	size_t stsize = 0;
+/* ---------------------------------------------------------------
+ * Common Macros
+ * ---------------------------------------------------------------
+ */
 
-	if (api_state != UPWR_API_READY)
-		return -3;
-	if (UPWR_SG_BUSY(UPWR_SG_PWRMGMT))
-		return -1;
+/* tests Service Group busy */
+#define UPWR_SG_BUSY(sg) (sg_busy & (1 << sg))
 
-	UPWR_USR_CALLB(UPWR_SG_PWRMGMT, callb);
+/* installs a user callback for the Service Group */
+#define UPWR_USR_CALLB(sg, cb) do { user_callback[sg] = cb; } while (0)
 
-	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_PWRMGMT, UPWR_PWM_PWR_ON);
+/* fills up common message header info */
+#define UPWR_MSG_HDR(hdr, sg, fn)           \
+	hdr.domain   = (uint32_t)pwr_domain;\
+	hdr.srvgrp   = sg;                  \
+	hdr.function = fn;
 
-	if (!swton)
-		txmsg.ptrs.ptr0 = 0; /* NULL pointer -> 0 offset */
-	else
-		txmsg.ptrs.ptr0 = upwr_ptr2offset(ptrval, UPWR_SG_PWRMGMT,
-						  (stsize = UPWR_PMC_SWT_WORDS * 4), 0, swton);
+/* ---------------------------------------------------------------
+ * Common Data Structures
+ * ---------------------------------------------------------------
+ */
 
-	if (!memon)
-		txmsg.ptrs.ptr1 = 0; /* NULL pointer -> 0 offset */
-	else
-		txmsg.ptrs.ptr1 = upwr_ptr2offset(ptrval, UPWR_SG_PWRMGMT, UPWR_PMC_MEM_WORDS * 4,
-						  stsize, memon);
+soc_domain_t __UPWR_API_DATA__ pwr_domain; /* CPU/power domain */
 
-	upwr_srv_req(UPWR_SG_PWRMGMT, (u32 *)&txmsg, sizeof(txmsg) / 4);
+upwr_code_vers_t __UPWR_API_DATA__ fw_rom_version;
+upwr_code_vers_t __UPWR_API_DATA__ fw_ram_version;
+uint32_t         __UPWR_API_DATA__ fw_launch_option;
 
-	return 0;
-}
+/* shared memory buffers */
 
-enum upwr_req_status upwr_poll_req_status(enum upwr_sg sg, u32 *sgfptr,
-					  enum upwr_resp *errptr, int *retptr,
-					  u32 attempts)
-{
-	u32 i;
-	enum upwr_req_status ret;
+#define UPWR_API_BUFFER_SIZE (MAX_SG_EXCEPT_MEM_SIZE + MAX_SG_PWRMGMT_MEM_SIZE + MAX_SG_VOLTM_MEM_SIZE)
 
-	if (!attempts) {
-		ret = UPWR_REQ_BUSY;
-		while (ret == UPWR_REQ_BUSY)
-			ret = upwr_req_status(sg, sgfptr, errptr, retptr);
-		return ret;
-	}
+void* __UPWR_API_DATA__  sh_buffer[UPWR_SG_COUNT]; /* service group shared mem
+                                                      buffer pointers */
 
-	for (i = 0; i < attempts; i++) {
-		ret = upwr_req_status(sg, sgfptr, errptr, retptr);
-		if (ret != UPWR_REQ_BUSY)
-			break;
-	}
+/* Callbacks registered for each service group :
+ *
+ * NULL means no callback is registered;
+ * for sgrp_callback, it also means the service group is free to
+ * receive a new request.
+ */
 
-	return ret;
+upwr_callb            __UPWR_API_DATA__ user_callback[UPWR_SG_COUNT];/* user */
+UPWR_RX_CALLB_FUNC_T  __UPWR_API_DATA__ sgrp_callback[UPWR_SG_COUNT];/* API  */
+
+/* request data structures for each service group */
+                                                   /* message waiting for TX */
+upwr_down_max_msg __UPWR_API_DATA__ sg_req_msg[UPWR_SG_COUNT];
+                                                     /* waiting message size */
+unsigned int      __UPWR_API_DATA__ sg_req_siz[UPWR_SG_COUNT];
+                                                            /* response msg  */
+upwr_up_max_msg   __UPWR_API_DATA__ sg_rsp_msg[UPWR_SG_COUNT];
+                                                        /* response msg size */
+unsigned int      __UPWR_API_DATA__ sg_rsp_siz[UPWR_SG_COUNT];
+
+/* tx pending status for each (1 bit per service group) */
+volatile uint32_t  __UPWR_API_DATA__ sg_tx_pend;
+                                 /* serv.group of current ongoing Tx, if any */
+volatile upwr_sg_t __UPWR_API_DATA__ sg_tx_curr;
+
+/* service group busy status, only for this domain (MU index 0) */
+                               /* SG bit = 1 if group is busy with a request */
+volatile uint32_t  __UPWR_API_DATA__   sg_busy;
+
+                                  /* OS-dependent memory allocation function */
+upwr_malloc_ptr_t  __UPWR_API_DATA__ os_malloc;
+               /* OS-dependent pointer->physical address conversion function */
+upwr_phyadr_ptr_t  __UPWR_API_DATA__ os_ptr2phy;
+                              /* OS-dependent function to lock critical code */
+upwr_lock_ptr_t    __UPWR_API_DATA__ os_lock;
+
+struct MU_tag*     __UPWR_API_DATA__ mu      ; /* pointer to MU structure */
+
+                                        /* maps id -> MU Tx interrupt vector */
+unsigned int       __UPWR_API_DATA__ mu_txvec;
+                                        /* maps id -> MU Rx interrupt vector */
+unsigned int       __UPWR_API_DATA__ mu_rxvec;
+
+int __UPWR_API_DATA__ mu_tx_pend;  /* indicates that a transmission was done
+                                    * and is pending; this bit is necessary
+                                    * because the Tx and Rx interrupts are ORed
+                                    * together, and there is no way of telling
+                                    * if only Rx interrupt or both occurred just
+                                    * by looking at the MU status registers */
+UPWR_TX_CALLB_FUNC_T __UPWR_API_DATA__ mu_tx_callb; /* Tx callback */
+UPWR_RX_CALLB_FUNC_T __UPWR_API_DATA__ mu_rx_callb; /* Rx callback */
+
+typedef enum {
+	UPWR_API_INIT_WAIT,        /* waiting for ROM firmware initialization */
+	UPWR_API_INITLZED,         /* ROM firmware initialized */
+	UPWR_API_START_WAIT,       /* waiting for start services */
+	UPWR_API_SHUTDOWN_WAIT,    /* waiting for shutdown */
+	UPWR_API_READY             /* ready to receive service requests */
+} upwr_api_state_t;
+
+volatile upwr_api_state_t __UPWR_API_DATA__ api_state;
+
+#ifdef  __cplusplus
+#ifndef UPWR_NAMESPACE /* extern "C" 'cancels' the effect of namespace */
+extern "C" {
+#endif
+#endif
+
+/* default pointer->physical address conversion, returns the same address */
+
+static void* ptr2phys(const void* ptr) {
+	return (void*)ptr;
 }
 
-int upwr_xcp_i2c_access(u16 addr, int8_t data_size, uint8_t subaddr_size, u32 subaddr,
-			u32 wdata, const upwr_callb callb)
-{
-	u64 ptrval = (u64)sh_buffer[UPWR_SG_EXCEPT];
-	struct upwr_i2c_access *i2c_acc_ptr = (struct upwr_i2c_access *)ptrval;
-	struct upwr_pointer_msg txmsg;
-
-	if (api_state != UPWR_API_READY)
-		return -3;
-	if (UPWR_SG_BUSY(UPWR_SG_EXCEPT))
-		return -1;
+/* ---------------------------------------------------------------
+ * SHARED MEMORY MANAGEMENT
+ * --------------------------------------------------------------
+ */
 
-	UPWR_USR_CALLB(UPWR_SG_EXCEPT, callb);
+/* upwr_ptr2offset() - converts a pointer (casted to uint64_t) to an
+ *                     address offset from the  shared memory start.
+ *                     If it does not point to a shared memory location,
+ *                     the structure pointed is copied to a buffer in the
+ *                     shared memory,  and the buffer offset is returned.
+ *                     The 2nd argument is the service group to which the
+ *                     buffer belongs;
+ *                     The 3rd argument is the size of structure to be copied.
+ *                     The 4th argument is an offset to apply to the copy
+ *                     destination address.
+ *                     The 5th argument is ptr before the conversion to physical
+ *                     address.
+ *                     2nd, 3rd. 4th and 5th arguments are not used if the
+ *                     1st one points to a location inside the shared memory.
+ */
 
-	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_EXCEPT, UPWR_XCP_I2C);
+static uint32_t upwr_ptr2offset(unsigned long         ptr,
+				upwr_sg_t        sg,
+				size_t           siz,
+				size_t           offset,
+				const void*      vptr)
+{
+	if ((ptr >= UPWR_DRAM_SHARED_BASE_ADDR) &&
+	    ((ptr - UPWR_DRAM_SHARED_BASE_ADDR) < UPWR_DRAM_SHARED_SIZE)) {
+		return (uint32_t)(ptr - UPWR_DRAM_SHARED_BASE_ADDR);
+	}
 
-	i2c_acc_ptr->addr = addr;
-	i2c_acc_ptr->subaddr = subaddr;
-	i2c_acc_ptr->subaddr_size = subaddr_size;
-	i2c_acc_ptr->data = wdata;
-	i2c_acc_ptr->data_size = data_size;
+	/* pointer is outside the shared memory, copy the struct to buffer */
+	memcpy(offset + (char*)sh_buffer[sg], (void*)vptr, siz);
+	return (uint32_t)((unsigned long)sh_buffer[sg] + offset - UPWR_DRAM_SHARED_BASE_ADDR);
+}
 
-	txmsg.ptr = upwr_ptr2offset(ptrval,
-				    UPWR_SG_EXCEPT,
-				    (size_t)sizeof(struct upwr_i2c_access),
-				    0,
-				    i2c_acc_ptr);
+/* ---------------------------------------------------------------
+ * INTERRUPTS AND CALLBACKS
+ *   Service-group specific callbacks are in their own sections
+ * --------------------------------------------------------------
+ */
 
-	upwr_srv_req(UPWR_SG_EXCEPT, (u32 *)&txmsg, sizeof(txmsg) / 4);
+/* upwr_lock()- locks (lock=1) or unlocks (lock=0) a critical code section;
+ *              for now it only needs to protect a portion of the code from
+ *              being interrupted by the MU.
+ */
 
-	return 0;
+static void upwr_lock(int lock)
+{
+  if (os_lock != NULL) os_lock(lock);
 }
 
-int upwr_xcp_set_ddr_retention(enum soc_domain domain, u32 enable, const upwr_callb callb)
+/* upwr_exp_isr()- handles the exception interrupt from uPower */
+
+void __UPWR_API_CODE__ upwr_exp_isr(void)
 {
-	union upwr_down_1w_msg txmsg;
+	/* TBD - what do do here */
+}
 
-	if (api_state != UPWR_API_READY)
-		return -3;
-	if (UPWR_SG_BUSY(UPWR_SG_EXCEPT))
-		return -1;
+/* upwr_copy2tr prototype; function definition in auxiliary function section */
+void upwr_copy2tr(struct MU_tag* mu, const uint32_t* msg, unsigned int size);
 
-	UPWR_USR_CALLB(UPWR_SG_EXCEPT, callb);
+#define UPWR_MU_TSR_EMPTY ((uint32_t)((1 << UPWR_MU_MSG_SIZE) -1))
 
-	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_EXCEPT, UPWR_XCP_SET_DDR_RETN);
-	txmsg.hdr.domain = (u32)domain;
-	txmsg.hdr.arg    = (u32)enable;
+/* upwr_txrx_isr()- handles both the Tx and Rx MU interrupts */
 
-	upwr_srv_req(UPWR_SG_EXCEPT, (u32 *)&txmsg, sizeof(txmsg) / 4);
+void __UPWR_API_CODE__ upwr_txrx_isr(void)
+{
+	if (mu_tx_pend &&                              /* Tx pending and ... */
+           (mu->TSR.R == UPWR_MU_TSR_EMPTY)) {    /* ... Tx registers empty: */
+	                                                  /* Tx ISR occurred */
+		mu_tx_pend   = 0;
+		mu->TCR.R    = 0; /* disable the tx interrupts */
+		mu->FCR.B.F0 = 0; /* urgency flag off, in case it was set */
+		if (mu_tx_callb != NULL) mu_tx_callb();
+	}
 
-	return 0;
+	if (mu->RSR.R != (uint32_t)0) {                   /* Rx ISR occurred */
+
+		mu->RCR.R = 0;   /* disable the interrupt until data is read */
+
+		if (mu_rx_callb != NULL) mu_rx_callb();
+	}
 }
 
-int upwr_rx(u32 *msg, u32 *size)
-{
-	u32 len = readl(&mu->rsr);
+/**
+ * upwr_next_req() - sends the next pending service request message, if any.
+ *
+ * Called upon MU Tx interrupts, it checks if there is any service request
+ * pending amongst the service groups, and sends the request if needed.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: none (void).
+ */
 
-	len = (len == 0x0) ? 0 :
-	      (len == 0x1) ? 1 :
-	      #if UPWR_MU_MSG_SIZE > 1
-	      (len == 0x3) ? 2 :
-	      #if UPWR_MU_MSG_SIZE > 2
-	      (len == 0x7) ? 3 :
-	      #if UPWR_MU_MSG_SIZE > 3
-	      (len == 0xF) ? 4 :
-	      #endif
-	      #endif
-	      #endif
-	      0xFFFFFFFF; /* something wrong */
+void upwr_next_req(void)
+{
+	upwr_sg_t sg = (upwr_sg_t)0;
 
-	if (len == 0xFFFFFFFF)
-		return -3;
+	/* no lock needed here, this is called from an MU ISR */
+	sg_tx_pend &= ~(1 << sg_tx_curr); /* no longer pending */
 
-	*size = len;
-	if (!len)
-		return -1;
+	if (sg_tx_pend == 0) return; /* no other pending */
 
-	/* copy the received message to the rx queue, so the interrupts are cleared; */
-	for (u32 i = 0; i < len; i++)
-		msg[i] = readl(&mu->rr[i]);
+	/* find the next one pending */
+	for (uint32_t mask = 1; mask < (1 << UPWR_SG_COUNT); mask = mask << 1) {
+		if (sg_tx_pend & mask) break;
+		sg = (upwr_sg_t)((int)sg + 1);
+	}
 
-	return 0;
+	sg_tx_curr = sg;
+	if (upwr_tx((uint32_t*)&sg_req_msg[sg],
+		     sg_req_siz[sg],
+		     upwr_next_req) < 0) {
+		UPWR_API_ASSERT(0);
+		return; /* leave the Tx pending */
+	}
 }
 
-void msg_copy(u32 *dest, u32 *src, u32 size)
-{
-	*dest = *src;
-	if (size > 1)
-		*(dest + 1) = *(src + 1);
-}
+/**
+ * upwr_mu_int_callback() - general MU interrupt callback.
+ *
+ * Called upon MU Rx interrupts, it calls the Service Group-specific callback,
+ * if any registered, based on the service group field in the received message.
+ * Otherwise, calls the user callback, if any registered.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: none (void).
+ */
 
 void upwr_mu_int_callback(void)
 {
-	enum upwr_sg sg;	/* service group number */
-	UPWR_RX_CALLB_FUNC_T sg_callb; /* service group callback */
-	struct upwr_up_2w_msg rxmsg;
-	u32 size;	/* in words */
+	upwr_sg_t              sg;       /* service group number */
+	UPWR_RX_CALLB_FUNC_T   sg_callb; /* service group callback */
+	upwr_up_max_msg        rxmsg = {0};
+	unsigned int           size;     /* in words */
 
-	if (upwr_rx((u32 *)&rxmsg, &size) < 0) {
+	if (upwr_rx((char *)&rxmsg, &size) < 0) {
 		UPWR_API_ASSERT(0);
 		return;
 	}
 
-	sg = (enum upwr_sg)rxmsg.hdr.srvgrp;
+	sg = (upwr_sg_t)rxmsg.hdr.srvgrp;
 
 	/* copy msg to the service group buffer */
-	msg_copy((u32 *)&sg_rsp_msg[sg], (u32 *)&rxmsg, size);
+	msg_copy((char *)&sg_rsp_msg[sg], (char *)&rxmsg, size);
 	sg_rsp_siz[sg] = size;
-	sg_busy &= ~(1 << sg);
 
-	sg_callb = sgrp_callback[sg];
-	if (!sg_callb) {
+	/* clear the service group busy status */
+	sg_busy &= ~(1 << sg);	/* no lock needed here, we're in the MU ISR */
+
+	if ((sg_callb = sgrp_callback[sg]) == NULL) {
 		upwr_callb user_callb = user_callback[sg];
 
 		/* no service group callback; call the user callback if any */
-		if (!user_callb)
-			goto done; /* no user callback */
+
+		if (user_callb == NULL) goto done; /* no user callback */
 
 		/* make the user callback */
-		user_callb(sg, rxmsg.hdr.function, (enum upwr_resp)rxmsg.hdr.errcode,
-			   (int)(size == 2) ? rxmsg.word2 : rxmsg.hdr.ret);
+		user_callb(sg,
+			   rxmsg.hdr.function,
+			   (upwr_resp_t)rxmsg.hdr.errcode,
+			   (int)(size == 2)? rxmsg.word2:rxmsg.hdr.ret);
 		goto done;
 	}
 
-	/* finally make the group callback */
-	sg_callb();
+	sg_callb();                    /* finally make the group callback */
 	/* don't uninstall the group callback, it's permanent */
+
 done:
-	if (rxmsg.hdr.errcode == UPWR_RESP_SHUTDOWN) /* shutdown error: */
+	if (rxmsg.hdr.errcode == UPWR_RESP_SHUTDOWN) { /* shutdown error: */
 		api_state = UPWR_API_INITLZED;
+					 /* change the API state automatically
+					  * so new requests are rejected by
+					  * the API immediately */
+	}
 }
 
-void upwr_txrx_isr(void)
+/**
+ * upwr_srv_req() - sends a service request message.
+ * @sg: message service group.
+ * @msg: pointer to the message
+ * @size: message size in 32-bit words.
+ *
+ * The message is sent right away if possible, or gets pending to be sent later.
+ * If pending, the message is stored in sg_req_msg and will be sent when the
+ * MU tranmission buffer is clear and there are no other pending messages
+ * from higher priority service groups.
+ *
+ * This is an auxiliary function used by the rest of the API calls.
+ * It is normally not called by the driver code, unless maybe for test purposes.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: none (void)
+ */
+
+void upwr_srv_req(upwr_sg_t     sg,
+		  uint32_t*     msg,
+		  unsigned int  size)
 {
-	if (readl(&mu->rsr))
-		upwr_mu_int_callback();
+	int rc;
+
+	upwr_lock(1);
+	sg_busy |= 1 << sg;
+	upwr_lock(0);
+
+	rc = upwr_tx(msg, size, upwr_next_req);
+	if (rc  < 0) {
+		UPWR_API_ASSERT(rc == -1);
+		/* queue full, make the transmission pending */
+		msg_copy((char *)&sg_req_msg[sg], (char *)msg, size);
+		sg_req_siz[sg] = size;
+		upwr_lock(1);
+		sg_tx_curr  = sg;
+		sg_tx_pend |= 1 << sg;
+		upwr_lock(0);
+		return;
+	}
 }
 
+/**---------------------------------------------------------------
+ * INITIALIZATION, CONFIGURATION
+ *
+ * A reference uPower initialization sequence goes as follows:
+ *
+ * 1. host CPU calls upwr_init.
+ * 2. (optional) host checks the ROM version and SoC code calling upwr_vers(...)
+ *    and optionally performs any configuration or workaround accordingly.
+ * 3. host CPU calls upwr_start to start the uPower services, passing a
+ *    service option number.
+ *    If no RAM code is loaded or it has no service options, the launch option
+ *    number passed must be 0, which will start the services available in ROM.
+ *    upwr_start also receives a pointer to a callback called by the API
+ *    when the firmware is ready to receive service requests.
+ *    The callback may be replaced by polling, calling upwr_req_status in a loop
+ *    or upwr_poll_req_status; in this case the callback pointer may be NULL.
+ *    A host may call upwr_start even if the services were already started by
+ *    any host: if the launch option is the same, the response will be ok,
+ *    but will indicate error if the services were already started with a
+ *    different launch option.
+ * 4. host waits for the callback calling, or polling finishing;
+ *    if no error is returned, it can start making service calls using the API.
+ *
+ * Variations on that reference sequence are possible:
+ *  - the uPower services can be started using the ROM code only, which includes
+ *    the basic Power Management services, among others, with launch option
+ *    number = 0.
+ *    The code RAM can be loaded while these services are running and,
+ *    when the loading is done, the services can be re-started with these 2
+ *    requests executed in order: upwr_xcp_shutdown and upwr_start,
+ *    using the newly loaded RAM code (launch option > 0).
+ *
+ * NOTE: the initialization call upwr_init is not effective and
+ *       returns error when called after the uPower services are started.
+ */
+
+/**
+ * upwr_start_callb() - internal callback for the Rx message from uPower
+ * that indicates the firmware is ready to receive the start commands.
+ * It calls the user callbacks registered in the upwr_start_boot and upwr_start
+ * call.
+ */
+
 void upwr_start_callb(void)
 {
 	switch (api_state) {
-	case UPWR_API_START_WAIT:
-	{
-		upwr_rdy_callb start_callb = (upwr_rdy_callb)user_callback[UPWR_SG_EXCEPT];
-
-		union upwr_ready_msg *msg = (union upwr_ready_msg *)&sg_rsp_msg[UPWR_SG_EXCEPT];
+		case UPWR_API_START_WAIT:
+		{
+			upwr_rdy_callb start_callb = (upwr_rdy_callb)
+						  user_callback[UPWR_SG_EXCEPT];
+
+			upwr_ready_msg* msg =
+				(upwr_ready_msg*)&sg_rsp_msg[UPWR_SG_EXCEPT];
+
+			/* message sanity check */
+			UPWR_API_ASSERT(msg->hdr.srvgrp   == UPWR_SG_EXCEPT);
+			UPWR_API_ASSERT(msg->hdr.function == UPWR_XCP_START);
+			UPWR_API_ASSERT(msg->hdr.errcode  == UPWR_RESP_OK);
+
+			fw_ram_version.soc_id = fw_rom_version.soc_id;
+			fw_ram_version.vmajor = msg->args.vmajor;
+			fw_ram_version.vminor = msg->args.vminor;
+			fw_ram_version.vfixes = msg->args.vfixes;
+
+			/* vmajor == vminor == vfixes == 0 indicates start error
+			   in this case, go back to the INITLZED state */
+
+			if ((fw_ram_version.vmajor != 0) ||
+			    (fw_ram_version.vminor != 0) ||
+			    (fw_ram_version.vfixes != 0)) {
+
+				api_state = UPWR_API_READY;
+
+				/* initialization is over:
+				   uninstall the user callback just in case */
+				UPWR_USR_CALLB(UPWR_SG_EXCEPT, NULL);
+
+				if (fw_launch_option == 0) {
+					/* launched ROM firmware:
+					 * RAM fw versions must be all 0s */
+					fw_ram_version.vmajor =
+					fw_ram_version.vminor =
+					fw_ram_version.vfixes = 0;
+				}
+			}
+			else api_state = UPWR_API_INITLZED;
 
-		/* message sanity check */
-		UPWR_API_ASSERT(msg->hdr.srvgrp   == UPWR_SG_EXCEPT);
-		UPWR_API_ASSERT(msg->hdr.function == UPWR_XCP_START);
-		UPWR_API_ASSERT(msg->hdr.errcode  == UPWR_RESP_OK);
+			start_callb(msg->args.vmajor,
+			            msg->args.vminor,
+				    msg->args.vfixes);
+		}
+		break;
 
-		fw_ram_version.soc_id = fw_rom_version.soc_id;
-		fw_ram_version.vmajor = msg->args.vmajor;
-		fw_ram_version.vminor = msg->args.vminor;
-		fw_ram_version.vfixes = msg->args.vfixes;
+		case UPWR_API_SHUTDOWN_WAIT:
+		{
+			upwr_callb user_callb = (upwr_callb)
+						  user_callback[UPWR_SG_EXCEPT];
 
-		/*
-		 * vmajor == vminor == vfixes == 0 indicates start error
-		 * in this case, go back to the INITLZED state
-		 */
+			upwr_shutdown_msg* msg =
+				(upwr_shutdown_msg*)&sg_rsp_msg[UPWR_SG_EXCEPT];
 
-		if (fw_ram_version.vmajor || fw_ram_version.vminor || fw_ram_version.vfixes) {
-			api_state = UPWR_API_READY;
+			/* message sanity check */
+			UPWR_API_ASSERT(msg->hdr.srvgrp   == UPWR_SG_EXCEPT);
+			UPWR_API_ASSERT(msg->hdr.function == UPWR_XCP_SHUTDOWN);
+			UPWR_API_ASSERT(msg->hdr.errcode  == UPWR_RESP_OK);
 
-			/* initialization is over: uninstall the callbacks just in case */
-			UPWR_USR_CALLB(UPWR_SG_EXCEPT, NULL);
-			sgrp_callback[UPWR_SG_EXCEPT] = NULL;
+			if ((upwr_resp_t)msg->hdr.errcode == UPWR_RESP_OK)
+				api_state = UPWR_API_INITLZED;
 
-			if (!fw_launch_option) {
-				/* launched ROM firmware: RAM fw versions must be all 0s */
-				fw_ram_version.vmajor =
-				fw_ram_version.vminor =
-				fw_ram_version.vfixes = 0;
-			}
-		} else {
-			api_state = UPWR_API_INITLZED;
+			if (user_callb != NULL) user_callb(UPWR_SG_EXCEPT,
+			                                   UPWR_XCP_SHUTDOWN,
+				                           (upwr_resp_t)
+							     msg->hdr.errcode,
+			                                   0);
 		}
+		break;
 
-		start_callb(msg->args.vmajor, msg->args.vminor, msg->args.vfixes);
-	}
-	break;
+		case UPWR_API_READY:
+		{
+			upwr_callb user_callb = (upwr_callb)
+						  user_callback[UPWR_SG_EXCEPT];
 
-	default:
-		UPWR_API_ASSERT(0);
+			upwr_up_max_msg* msg =
+				    (upwr_up_max_msg*)&sg_rsp_msg[UPWR_SG_EXCEPT];
+
+			/* message sanity check */
+			UPWR_API_ASSERT(msg->hdr.srvgrp   == UPWR_SG_EXCEPT);
+
+			if (user_callb != NULL) user_callb(UPWR_SG_EXCEPT,
+			                                   msg->hdr.function,
+				                           (upwr_resp_t)
+							     msg->hdr.errcode,
+			                                   (int)(sg_rsp_siz[UPWR_SG_EXCEPT] == 2) ? msg->word2 : msg->hdr.ret);
+		}
 		break;
+
+		default:
+			UPWR_API_ASSERT(0);
+			break;
 	}
 }
 
-int upwr_init(enum soc_domain domain, struct mu_type *muptr)
+/**
+ * upwr_init() - API initialization; must be the first API call after reset.
+ * @domain: SoC-dependent CPU domain id; identifier used by the firmware in
+ * many services. Defined by SoC-dependent type soc_domain_t found in
+ * upower_soc_defs.h.
+ * @muptr: pointer to the MU instance.
+ * @mallocptr: pointer to the memory allocation function
+ * @physaddrptr: pointer to the function to convert pointers to
+ * physical addresses. If NULL, no conversion is made (pointer=physical address)
+ * @isrinstptr: pointer to the function to install the uPower ISR callbacks;
+ * the function receives the pointers to the MU tx/rx and Exception ISRs
+ * callbacks, which must be called from the actual system ISRs.
+ * The function pointed by isrinstptr must also enable the interrupt at the
+ * core/interrupt controller, but must not enable the interrupt at the MU IP.
+ * The system ISRs are responsible for dealing with the interrupt controller,
+ * performing any other context save/restore, and any other housekeeping.
+ * @lockptr: pointer to a function that prevents MU interrupts (if argrument=1)
+ * or allows it (if argument=0). The API calls this function to make small
+ * specific code portions thread safe. Only MU interrupts must be avoided,
+ * the code may be suspended for other reasons.
+ * If no MU interrupts can happen during the execution of an API call or
+ * callback, even if enabled, for some other reason (e.g. interrupt priority),
+ * then this argument may be NULL.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if failed to allocate memory, or use some other resource.
+ *        -2 if any argument is invalid.
+ *        -3 if failed to send the ping message.
+ *        -4 if failed to receive the initialization message, or was invalid
+ */
+
+int upwr_init(	soc_domain_t               domain,
+		struct MU_tag*             muptr,
+		const  upwr_malloc_ptr_t   mallocptr,
+		const  upwr_phyadr_ptr_t   phyadrptr,
+		const  upwr_inst_isr_ptr_t isrinstptr,
+		const  upwr_lock_ptr_t     lockptr)
 {
-	u32 dom_buffer_base = ((UPWR_API_BUFFER_ENDPLUS + UPWR_API_BUFFER_BASE) / 2);
-	union upwr_init_msg *msg = (union upwr_init_msg *)&sg_rsp_msg[UPWR_SG_EXCEPT];
-	enum upwr_sg sg; /* service group number */
-	u32 size; /* in words */
 	int j;
 
-	mu = muptr;
-	writel(0, &mu->tcr);
-	writel(0, &mu->rcr);
+	upwr_sg_t           sg;       /* service group number */
+	unsigned int        size;     /* in words */
+	unsigned long        dom_buffer_base = (domain == RTD_DOMAIN)?
+							   UPWR_API_BUFFER_BASE:
+                           ((UPWR_API_BUFFER_ENDPLUS + UPWR_API_BUFFER_BASE)/2);
+
+	upwr_init_msg*      msg = (upwr_init_msg*)&sg_rsp_msg[UPWR_SG_EXCEPT];
 
-	api_state = UPWR_API_INIT_WAIT;
-	pwr_domain = domain;
-	sg_busy = 0;
+        mu = muptr;
+	mu->TCR.R = mu->RCR.R = 0; /* disable tx and rx interrupts, in case
+				      not called 1st time after reset   */
+
+	os_malloc   = mallocptr;
+	os_ptr2phy  = (phyadrptr == (upwr_phyadr_ptr_t)NULL)? ptr2phys :
+                                                              phyadrptr;
+        os_lock     = lockptr;
+	api_state   = UPWR_API_INIT_WAIT;
+        sg_busy     = 0;
+	pwr_domain  = domain;
 
 	/* initialize the versions, in case they are polled */
 	fw_rom_version.soc_id =
@@ -358,128 +717,2591 @@ int upwr_init(enum soc_domain domain, struct mu_type *muptr)
 	fw_ram_version.vminor =
 	fw_ram_version.vfixes = 0;
 
-	sh_buffer[UPWR_SG_EXCEPT] = (void *)(ulong)dom_buffer_base;
-	sh_buffer[UPWR_SG_PWRMGMT] = (void *)(ulong)(dom_buffer_base +
-						     sizeof(union upwr_xcp_union));
-	sh_buffer[UPWR_SG_DELAYM] = NULL;
-	sh_buffer[UPWR_SG_VOLTM] = NULL;
-	sh_buffer[UPWR_SG_CURRM] = NULL;
-	sh_buffer[UPWR_SG_TEMPM] = NULL;
-	sh_buffer[UPWR_SG_DIAG] = NULL;
+	mu_tx_pend     = 0;
+	sg_tx_pend     = 0;
+	sg_tx_curr     = UPWR_SG_COUNT; /* means none here */
+
+	/* must have enough headroom for the shared RAM API buffers */
+	UPWR_API_ASSERT((UPWR_DRAM_SHARED_ENDPLUS - dom_buffer_base) >=
+			 UPWR_API_BUFFER_SIZE);
+
+	/* UPWR_API_BUFFER_BASE must let enough buffer for both domains */
+	UPWR_API_ASSERT((UPWR_DRAM_SHARED_ENDPLUS - UPWR_API_BUFFER_BASE) >=
+			(UPWR_API_BUFFER_SIZE*2));
+
+	sh_buffer[UPWR_SG_EXCEPT ] = (void*)(unsigned long)dom_buffer_base;
+	sh_buffer[UPWR_SG_PWRMGMT] = (void*)(unsigned long)(dom_buffer_base + MAX_SG_EXCEPT_MEM_SIZE);
+	sh_buffer[UPWR_SG_DELAYM ] = NULL;
+	sh_buffer[UPWR_SG_VOLTM  ] = (void*)(unsigned long)(dom_buffer_base + MAX_SG_EXCEPT_MEM_SIZE + MAX_SG_PWRMGMT_MEM_SIZE);
+	sh_buffer[UPWR_SG_CURRM  ] = NULL;
+	sh_buffer[UPWR_SG_TEMPM  ] = NULL;
+	sh_buffer[UPWR_SG_DIAG   ] = NULL;
 	/* (no buffers service groups other than xcp and pwm for now) */
 
-	for (j = 0; j < UPWR_SG_COUNT; j++) {
+	for (j = 0; j < UPWR_SG_COUNT; j++)
+	{
 		user_callback[j] = NULL;
-		/* service group Exception gets the initialization callbacks */
-		sgrp_callback[j] = (j == UPWR_SG_EXCEPT) ? upwr_start_callb : NULL;
+	        /* service group Exception gets the initialization callbacks */
+		sgrp_callback[j] = (j == UPWR_SG_EXCEPT)? upwr_start_callb:NULL;
 
 		/* response messages with an initial consistent content */
 		sg_rsp_msg[j].hdr.errcode = UPWR_RESP_SHUTDOWN;
 	}
 
-	if (readl(&mu->fsr) & BIT(0)) {
+	if (mu->FSR.B.F0) {            /* init message already received:
+		                          assume tasks are running on uPower */
+
 		/* send a ping message down to get the ROM version back */
-		upwr_xcp_ping_msg ping_msg;
+		upwr_xcp_ping_msg ping_msg = {0};
 
-		ping_msg.hdr.domain = pwr_domain;
-		ping_msg.hdr.srvgrp = UPWR_SG_EXCEPT;
+		ping_msg.hdr.domain   = pwr_domain;
+		ping_msg.hdr.srvgrp   = UPWR_SG_EXCEPT;
 		ping_msg.hdr.function = UPWR_XCP_PING;
 
-		if (readl(&mu->rsr) & BIT(0)) /* first clean any Rx message left over */
-			upwr_rx((u32 *)msg, &size);
+		if (mu->RSR.B.RF0) { /* first clean any Rx message left over */
+			upwr_rx((char *)msg, &size);
+		}
 
-		while (readl(&mu->tsr) != UPWR_MU_TSR_EMPTY)
-			;
+		while (mu->TSR.R != UPWR_MU_TSR_EMPTY) {    /* wait any Tx ...
+						    ... left over to be sent */
+			#ifdef UPWR_BLOCK_LEVEL
+			WAIT_CLK(1000); /* waiting loop must advance clock */
+			#endif
+		};
 
-		/*
-		 * now send the ping message;
-		 * do not use upwr_tx, which needs API initilized;
-		 * just write to the MU TR register(s)
+		/* now send the ping message;
+		   do not use upwr_tx, which needs API initilized;
+		   just write to the MU TR register(s)
 		 */
-		setbits_le32(&mu->fcr, BIT(0)); /* flag urgency status */
-		upwr_copy2tr(mu, (u32 *)&ping_msg, sizeof(ping_msg) / 4);
+		mu->FCR.B.F0 = 1; /* flag urgency status */
+		upwr_copy2tr(mu, (uint32_t*)&ping_msg, sizeof(ping_msg)/4);
 	}
 
 	do {
 		/* poll for the MU Rx status: wait for an init message, either
 		 * 1st sent from uPower after reset or as a response to a ping
 		 */
-		while (!readl(&mu->rsr) & BIT(0))
-			;
+		while (mu->RSR.B.RF0 == (uint32_t)0)	{
+			#ifdef UPWR_BLOCK_LEVEL
+			WAIT_CLK(1000); /* waiting loop must advance clock */
+			#endif
+		};
 
-		clrbits_le32(&mu->fcr, BIT(0));
+		mu->FCR.B.F0 = 0; /* urgency status off, in case it was set */
 
-		if (upwr_rx((u32 *)msg, &size) < 0)
+		if (upwr_rx((char *)msg, &size) < 0) {
 			return -4;
+		}
 
-		if (size != (sizeof(union upwr_init_msg) / 4)) {
-			if (readl(&mu->fsr) & BIT(0))
-				continue; /* discard left over msg */
-			else
-				return -4;
+		if (size != (sizeof(upwr_init_msg)/4)) {
+			if (mu->FSR.B.F0) continue; /* discard left over msg */
+				     else return -4;
 		}
 
-		sg = (enum upwr_sg)msg->hdr.srvgrp;
+		sg = (upwr_sg_t)msg->hdr.srvgrp;
 		if (sg != UPWR_SG_EXCEPT) {
-			if (readl(&mu->fsr) & BIT(0))
-				continue;
-			else
-				return -4;
+			if (mu->FSR.B.F0) continue; /* discard left over msg */
+				     else return -4;
 		}
 
-		if ((enum upwr_xcp_f)msg->hdr.function   != UPWR_XCP_INIT) {
-			if (readl(&mu->fsr) & BIT(0))
-				continue;
-			else
-				return -4;
+		if ((upwr_xcp_f_t)msg->hdr.function   != UPWR_XCP_INIT) {
+			if (mu->FSR.B.F0) continue; /* discard left over msg */
+				     else return -4;
 		}
 
 		break;
-	} while (true);
+	} while (1);
 
 	fw_rom_version.soc_id = msg->args.soc;
 	fw_rom_version.vmajor = msg->args.vmajor;
 	fw_rom_version.vminor = msg->args.vminor;
 	fw_rom_version.vfixes = msg->args.vfixes;
 
-	api_state = UPWR_API_INITLZED;
+        if (upwr_rx_callback(upwr_mu_int_callback) < 0) {
+		/* catastrophic error, but is it possible to happen? */
+		UPWR_API_ASSERT(0);
+		return -1;
+	}
 
+	mu_tx_callb    = NULL; /* assigned on upwr_tx */
+
+	/* install the ISRs and enable the interrupts */
+
+        isrinstptr(upwr_txrx_isr, upwr_exp_isr);
+
+	mu->RCR.R = 1;    /* enable only RR[0] receive interrupt */
+
+        api_state = UPWR_API_INITLZED;
 	return 0;
 } /* upwr_init */
 
-int upwr_start(u32 launchopt, const upwr_rdy_callb rdycallb)
+/**
+ * upwr_start() - Starts the uPower services.
+ * @launchopt: a number to select between multiple launch options,
+ * that may define, among other things, which services will be started,
+ * or which services implementations, features etc.
+ * launchopt = 0 selects a subset of services implemented in ROM;
+ * any other number selects service sets implemented in RAM, launched
+ * by the firmware function ram_launch; if an invalid launchopt value is passed,
+ * no services are started, and the callback returns error (see below).
+ * @rdycallb: pointer to the callback to be called when the uPower is ready
+ * to receive service requests. NULL if no callback needed.
+ * The callback receives as arguments the RAM firmware version numbers.
+ * If all 3 numbers (vmajor, vminor, vfixes) are 0, that means the
+ * service launching failed.
+ * Firmware version numbers will be the same as ROM if launchopt = 0,
+ * selecting the ROM services.
+ *
+ * upwr_start can be called by any domain even if the services are already
+ * started: it has no effect, returning success, if the launch option is the
+ * same as the one that actually started the service, and returns error if
+ * called with a different option.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded or
+ * not.
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_EXCEPT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if a resource failed,
+ *        -2 if the domain passed is the same as the caller,
+ *        -3 if called in an invalid API state
+ */
+
+int upwr_start(	uint32_t                launchopt,
+		const upwr_rdy_callb    rdycallb)
 {
-	upwr_start_msg txmsg;
+	upwr_start_msg txmsg = {0};
 
-	if (api_state != UPWR_API_INITLZED)
-		return -3;
+	if (api_state != UPWR_API_INITLZED) return -3;
 
 	UPWR_USR_CALLB(UPWR_SG_EXCEPT, (upwr_callb)rdycallb);
 
 	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_EXCEPT, UPWR_XCP_START);
 
-	txmsg.hdr.arg = launchopt;
-	fw_launch_option = launchopt;
+	txmsg.hdr.arg = fw_launch_option = launchopt;
 
-	if (upwr_tx((u32 *)&txmsg, sizeof(txmsg) / 4) < 0) {
+	if (upwr_tx((uint32_t*)&txmsg, sizeof(txmsg)/4, NULL) < 0) {
 		/* catastrophic error, but is it possible to happen? */
 		UPWR_API_ASSERT(0);
 		return -1;
 	}
 
 	api_state = UPWR_API_START_WAIT;
+	return 0;
+} /* upwr_start */
+
+/**---------------------------------------------------------------
+ * EXCEPTION SERVICE GROUP
+ */
+
+/**
+ * upwr_xcp_config() - Applies general uPower configurations.
+ * @config: pointer to the uPower SoC-dependent configuration struct
+ * upwr_xcp_config_t defined in upower_soc_defs.h. NULL may be passed, meaning
+ * a request to read the configuration, in which case it appears in the callback
+ * argument ret, or can be pointed by argument retptr in the upwr_req_status and
+ * upwr_poll_req_status calls, casted to upwr_xcp_config_t.
+ * @callb: pointer to the callback to be called when the uPower has finished
+ * the configuration, or NULL if no callback needed (polling used instead).
+ *
+ * Some configurations are targeted for a specific domain (see the struct
+ * upwr_xcp_config_t definition in upower_soc_defs.h); this call has implicit
+ * domain target (the same domain from which is called).
+ *
+ * The return value is always the current configuration value, either in a
+ * read-only request (config = NULL) or after setting a new cnfiguration
+ * (non-NULL config).
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded or
+ * not.
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_EXCEPT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ */
+
+int upwr_xcp_config(const upwr_xcp_config_t* config, const upwr_callb callb)
+{
+	upwr_xcp_config_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)  return -3;
+        if (UPWR_SG_BUSY(UPWR_SG_EXCEPT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_EXCEPT, callb);
+
+	if (config == NULL) {
+		txmsg.hdr.arg = 1;         /* 1= read, txmsg.word2 ignored */
+	}
+	else {
+		txmsg.hdr.arg = 0;         /* 1= write */
+		txmsg.word2   = config->R;
+	}
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_EXCEPT, UPWR_XCP_CONFIG);
+
+	upwr_srv_req(UPWR_SG_EXCEPT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**
+ * upwr_xcp_sw_alarm() - Makes uPower issue an alarm interrupt to given domain.
+ * @domain: identifier of the domain to alarm. Defined by SoC-dependent type
+ * soc_domain_t found in upower_soc_defs.h.
+ * @code: alarm code. Defined by SoC-dependent type upwr_alarm_t found in
+ * upower_soc_defs.h.
+ * @callb: pointer to the callback to be called when the uPower has finished
+ * the alarm, or NULL if no callback needed (polling used instead).
+ *
+ * The function requests the uPower to issue an alarm of the given code as if
+ * it had originated internally. This service is useful mainly to test the
+ * system response to such alarms, or to make the system handle a similar alarm
+ * situation detected externally to uPower.
+ *
+ * The system ISR/code handling the alarm may retrieve the alarm code by calling
+ * the auxiliary function upwr_alarm_code.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded or
+ * not.
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_EXCEPT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ */
+
+int upwr_xcp_sw_alarm(soc_domain_t     domain,
+		      upwr_alarm_t     code,
+		      const upwr_callb callb)
+{
+	upwr_xcp_swalarm_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)  return -3;
+	if (UPWR_SG_BUSY(UPWR_SG_EXCEPT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_EXCEPT, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_EXCEPT, UPWR_XCP_SW_ALARM);
+	txmsg.hdr.domain = (uint32_t)domain;
+	txmsg.hdr.arg    = (uint32_t)code;
+
+	upwr_srv_req(UPWR_SG_EXCEPT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**
+ * upwr_xcp_set_ddr_retention() - M33/A35 can use this API to set/clear ddr retention
+ * @domain: identifier of the caller domain.
+ * soc_domain_t found in upower_soc_defs.h.
+ * @enable: true, means that set ddr retention, false clear ddr retention.
+ * @callb: NULL
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_EXCEPT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ */
+
+int upwr_xcp_set_ddr_retention(soc_domain_t     domain,
+                        uint32_t enable,
+                        const upwr_callb callb)
+{
+	upwr_xcp_ddr_retn_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)  return -3;
+	if (UPWR_SG_BUSY(UPWR_SG_EXCEPT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_EXCEPT, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_EXCEPT, UPWR_XCP_SET_DDR_RETN);
+	txmsg.hdr.domain = (uint32_t)domain;
+	txmsg.hdr.arg    = (uint32_t)enable;
+
+	upwr_srv_req(UPWR_SG_EXCEPT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**
+ * upwr_xcp_set_rtd_use_ddr() - M33 call this API to inform uPower, M33 is using ddr
+ * @domain: identifier of the caller domain.
+ * soc_domain_t found in upower_soc_defs.h.
+ * @enable: not 0, true, means that RTD is using ddr. 0, false, means that, RTD is not using ddr.
+ * @callb: NULL
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_EXCEPT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ */
+
+int upwr_xcp_set_rtd_use_ddr(soc_domain_t     domain,
+                        uint32_t is_use_ddr,
+                        const upwr_callb callb)
+{
+	upwr_xcp_rtd_use_ddr_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)  return -3;
+	if (UPWR_SG_BUSY(UPWR_SG_EXCEPT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_EXCEPT, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_EXCEPT, UPWR_XCP_SET_RTD_USE_DDR);
+	txmsg.hdr.domain = (uint32_t)domain;
+	txmsg.hdr.arg    = (uint32_t)is_use_ddr;
+
+	upwr_srv_req(UPWR_SG_EXCEPT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**
+ * upwr_xcp_set_rtd_apd_llwu() - M33/A35 can use this API to set/clear rtd_llwu apd_llwu
+ * @domain: set which domain (RTD_DOMAIN, APD_DOMAIN) LLWU.
+ * soc_domain_t found in upower_soc_defs.h.
+ * @enable: true, means that set rtd_llwu or apd_llwu, false clear rtd_llwu or apd_llwu.
+ * @callb: NULL
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_EXCEPT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ */
+
+int upwr_xcp_set_rtd_apd_llwu(soc_domain_t     domain,
+                        uint32_t enable,
+                        const upwr_callb callb)
+{
+	upwr_xcp_rtd_apd_llwu_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)  return -3;
+	if (UPWR_SG_BUSY(UPWR_SG_EXCEPT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_EXCEPT, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_EXCEPT, UPWR_XCP_SET_RTD_APD_LLWU);
+	txmsg.hdr.domain = (uint32_t)domain;
+	txmsg.hdr.arg    = (uint32_t)enable;
+
+	upwr_srv_req(UPWR_SG_EXCEPT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**
+ * upwr_xcp_shutdown() - Shuts down all uPower services and power mode tasks.
+ * @callb: pointer to the callback to be called when the uPower has finished
+ * the shutdown, or NULL if no callback needed
+ * (polling used instead).
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded or
+ * not.
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_EXCEPT as the service group argument.
+ *
+ * At the callback the uPower/API is back to initialization/start-up phase,
+ * so service request calls return error.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ */
+
+int upwr_xcp_shutdown(const upwr_callb callb)
+{
+	upwr_xcp_shutdown_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)  return -3;
+    if (UPWR_SG_BUSY(UPWR_SG_EXCEPT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_EXCEPT, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_EXCEPT, UPWR_XCP_SHUTDOWN);
+
+	upwr_srv_req(UPWR_SG_EXCEPT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	api_state = UPWR_API_SHUTDOWN_WAIT;
+
+	return 0;
+}
+
+/**
+ * upwr_xcp_i2c_access() - Performs an access through the uPower I2C interface.
+ * @addr: I2C slave address, up to 10 bits.
+ * @data_size: determines the access direction and data size in bytes, up to 4;
+ * negetive data_size determines a read  access with size -data_size;
+ * positive data_size determines a write access with size  data_size;
+ * data_size=0 is invalid, making the service return error UPWR_RESP_BAD_REQ.
+ * @subaddr_size: size of the sub-address in bytes, up to 4; if subaddr_size=0,
+ * no subaddress is used.
+ * @subaddr: sub-address, only used if subaddr_size > 0.
+ * @wdata: write data, up to 4 bytes; ignored if data_size < 0 (read)
+ * @callb: pointer to the callback to be called when the uPower has finished
+ * the access, or NULL if no callback needed
+ * (polling used instead).
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded or
+ * not.
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_EXCEPT as the service group argument.
+ *
+ * The service performs a read (data_size < 0) or a write (data_size > 0) of
+ * up to 4 bytes on the uPower I2C interface. The data read from I2C comes via
+ * the callback argument ret, or written to the variable pointed by retptr,
+ * if polling is used (calls upwr_req_status or upwr_poll_req_status).
+ * ret (or *retptr) also returns the data written on writes.
+ *
+ * Sub-addressing is supported, with sub-address size determined by the argument
+ * subaddr_size, up to 4 bytes. Sub-addressing is not used if subaddr_size=0.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ */
+
+#ifdef UPWR_BLOCK_LEVEL
+/* emulated struct equivalent to upwr_i2c_access in upower_defs.h
+   (simulation only)
+ */
+
+struct upwr_i2c_access_emul {
+	CapiRamHalf      addr;
+	CapiRamByte      data_size;
+	CapiRamByte      subaddr_size;
+	CapiRamWord      subaddr;
+	CapiRamWord      data;
+
+	upwr_i2c_access_emul(unsigned int address)
+	{
+		addr.setAddress        (address);
+		data_size.setAddress   (address+2);
+		subaddr_size.setAddress(address+3);
+		subaddr.setAddress     (address+4);
+		data.setAddress        (address+8);
+	}
+};
+#endif
+
+int upwr_xcp_i2c_access(uint16_t         addr,
+			int8_t           data_size,
+			uint8_t          subaddr_size,
+			uint32_t         subaddr,
+			uint32_t         wdata,
+			const upwr_callb callb)
+{
+	unsigned long ptrval = (unsigned long)sh_buffer[UPWR_SG_EXCEPT];
+	#ifdef UPWR_BLOCK_LEVEL
+	upwr_i2c_access_emul  i2c_acc((unsigned int)ptrval);
+	upwr_i2c_access_emul* i2c_acc_ptr = &i2c_acc;
+	#else
+	upwr_i2c_access*      i2c_acc_ptr = (upwr_i2c_access*)ptrval;
+	#endif
+	upwr_pwm_pmiccfg_msg  txmsg = {0};
+
+	if (api_state != UPWR_API_READY)  return -3;
+	if (UPWR_SG_BUSY(UPWR_SG_EXCEPT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_EXCEPT, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_EXCEPT, UPWR_XCP_I2C);
+
+	i2c_acc_ptr->addr         = addr       ;
+	i2c_acc_ptr->subaddr      = subaddr    ;
+	i2c_acc_ptr->subaddr_size = subaddr_size;
+	i2c_acc_ptr->data         = wdata      ;
+	i2c_acc_ptr->data_size    = data_size  ;
+
+	txmsg.ptr = upwr_ptr2offset(ptrval,
+				    UPWR_SG_EXCEPT,
+				    (size_t)sizeof(upwr_i2c_access),
+				    0,
+				    i2c_acc_ptr);
+
+	upwr_srv_req(UPWR_SG_EXCEPT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**---------------------------------------------------------------
+ * VOLTAGE MANAGERMENT SERVICE GROUP
+ */
+
+/**
+ * upwr_vtm_pmic_cold_reset() -request cold reset the pmic
+ * pmic will power cycle all the regulators
+ * @callb: response callback pointer; NULL if no callback needed.
+ *
+ * The function requests uPower to cold reset the pmic.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+int upwr_vtm_pmic_cold_reset(upwr_callb callb)
+{
+	upwr_volt_pmic_cold_reset_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)   return -3;
+    if (UPWR_SG_BUSY(UPWR_SG_VOLTM)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_VOLTM, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_VOLTM, UPWR_VTM_PMIC_COLD_RESET);
+
+	upwr_srv_req(UPWR_SG_VOLTM, (uint32_t*)&txmsg, sizeof(txmsg) / 4);
+
+	return 0;
+}
+
+/**
+ * upwr_vtm_set_pmic_mode() -request uPower set pmic mode
+ * @pmic_mode: the target mode need to be set
+ * @callb: response callback pointer; NULL if no callback needed.
+ *
+ * The function requests uPower to set pmic mode
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+int upwr_vtm_set_pmic_mode(uint32_t pmic_mode, upwr_callb callb)
+{
+	upwr_volt_pmic_set_mode_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)   return -3;
+    if (UPWR_SG_BUSY(UPWR_SG_VOLTM)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_VOLTM, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_VOLTM, UPWR_VTM_SET_PMIC_MODE);
+
+    txmsg.hdr.arg = pmic_mode;
+
+	upwr_srv_req(UPWR_SG_VOLTM, (uint32_t*)&txmsg, sizeof(txmsg) / 4);
+
+	return 0;
+}
+
+/**
+ * upwr_vtm_chng_pmic_voltage() - Changes the voltage of a given rail.
+ * @rail: pmic rail id.
+ * @volt: the target voltage of the given rail, accurate to uV
+ * If pass volt value 0, means that power off this rail.
+ * @callb: response callback pointer; NULL if no callback needed.
+ *
+ * The function requests uPower to change the voltage of the given rail.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_vtm_chng_pmic_voltage(uint32_t rail, uint32_t volt, upwr_callb callb)
+{
+	upwr_volt_pmic_set_volt_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)   return -3;
+    if (UPWR_SG_BUSY(UPWR_SG_VOLTM)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_VOLTM, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_VOLTM, UPWR_VTM_CHNG_PMIC_RAIL_VOLT);
+
+	txmsg.args.rail = rail;
+
+    txmsg.args.volt = (volt + PMIC_VOLTAGE_MIN_STEP - 1) / PMIC_VOLTAGE_MIN_STEP;
+
+	upwr_srv_req(UPWR_SG_VOLTM, (uint32_t*)&txmsg, sizeof(txmsg) / 4);
+
+	return 0;
+}
+
+/**
+ * upwr_vtm_get_pmic_voltage() - Get the voltage of a given rail.
+ * @rail: pmic rail id.
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to get the voltage of the given rail.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * The voltage data read from uPower via
+ * the callback argument ret, or written to the variable pointed by retptr,
+ * if polling is used (calls upwr_req_status or upwr_poll_req_status).
+ * ret (or *retptr) also returns the data written on writes.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_vtm_get_pmic_voltage(uint32_t rail, upwr_callb callb)
+{
+	upwr_volt_pmic_get_volt_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)   return -3;
+    if (UPWR_SG_BUSY(UPWR_SG_VOLTM)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_VOLTM, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_VOLTM, UPWR_VTM_GET_PMIC_RAIL_VOLT);
+
+	txmsg.args.rail = rail;
+
+	upwr_srv_req(UPWR_SG_VOLTM, (uint32_t*)&txmsg, sizeof(txmsg) / 4);
+
+	return 0;
+}
+
+/**
+ * upwr_vtm_dump_dva_info() - Dump dva information to M33/A35
+ * @dump_addr: uPower dump dva information to the given address
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to dump dva information to the given address
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_vtm_dump_dva_info(uint32_t dump_addr, upwr_callb callb)
+{
+	upwr_volt_dva_dump_info_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)   return -3;
+    if (UPWR_SG_BUSY(UPWR_SG_VOLTM)) return -1;
+
+	if ((dump_addr < UPWR_DRAM_SHARED_BASE_ADDR) ||
+	    ((dump_addr - UPWR_DRAM_SHARED_BASE_ADDR) >= UPWR_DRAM_SHARED_SIZE)) {
+		return -2;
+    }
+
+	UPWR_USR_CALLB(UPWR_SG_VOLTM, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_VOLTM, UPWR_VTM_DVA_DUMP_INFO);
+
+	txmsg.args.addr_offset = dump_addr - UPWR_DRAM_SHARED_BASE_ADDR;
+
+	upwr_srv_req(UPWR_SG_VOLTM, (uint32_t*)&txmsg, sizeof(txmsg) / 4);
 
 	return 0;
 }
 
-u32 upwr_rom_version(u32 *vmajor, u32 *vminor, u32 *vfixes)
+/**
+ * upwr_vtm_dva_request() - request uPower to dva an array IDs
+ * @id: id of soc components, such as A35, M33, GPU, SDHC and etc, it is a bit group, extending to two u32 types.
+ * @mode: OD (over drive) mode, ND (normal drive)  mode, LD (lower drive) mode,
+ * type: enum work_mode, defined in upower_defs.h
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to dva an array IDs to the give work mode.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * M33/A35 need to check the execute result
+ * 0 means success, 1 means hold on(A35 request LD, but GPU request OD), negative value means failure.
+ * upower fw needs support cocurrent request from M33 and A35.
+ * upower fw needs support multiple masters requesting different modes.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_vtm_dva_request(const uint32_t id[], enum work_mode mode, upwr_callb callb)
 {
-	u32 soc;
+	unsigned long ptrval = (unsigned long)sh_buffer[UPWR_SG_VOLTM];
+    upwr_dva_id_struct *dva_id_struct_ptr = (upwr_dva_id_struct *)ptrval;
+	upwr_volt_dva_req_id_msg  txmsg = {0};
+
+	if (api_state != UPWR_API_READY)  return -3;
+	if (UPWR_SG_BUSY(UPWR_SG_VOLTM)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_VOLTM, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_VOLTM, UPWR_VTM_DVA_REQ_ID);
+
+    memcpy(&(dva_id_struct_ptr->id_word0), &id[0], 4);
+    memcpy(&(dva_id_struct_ptr->id_word1), &id[1], 4);
+    dva_id_struct_ptr->mode = mode;
+
+	txmsg.ptr = upwr_ptr2offset(ptrval,
+				    UPWR_SG_VOLTM,
+				    (size_t)sizeof(upwr_dva_id_struct),
+				    0,
+				    dva_id_struct_ptr);
+
+	upwr_srv_req(UPWR_SG_VOLTM, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**
+ * upwr_vtm_dva_request_soc() - request uPower to dva the whole SOC to the given work mode
+ * @mode: OD (over drive) mode, ND (normal drive)  mode, LD (lower drive) mode,
+ * type: enum work_mode, defined in upower_defs.h
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to switch whole SOC to the given work mode.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * M33/A35 need to check the execute result
+ * 0 means success, 1 means hold on(A35 request LD, but GPU request OD), negative value means failure.
+ * upower fw needs support cocurrent request from M33 and A35.
+ * upower fw needs support multiple masters requesting different modes.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+int upwr_vtm_dva_request_soc(enum work_mode mode, upwr_callb callb)
+{
+	upwr_volt_dva_req_soc_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)   return -3;
+    if (UPWR_SG_BUSY(UPWR_SG_VOLTM)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_VOLTM, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_VOLTM, UPWR_VTM_DVA_REQ_SOC);
+
+	txmsg.args.mode = mode;
+
+	upwr_srv_req(UPWR_SG_VOLTM, (uint32_t*)&txmsg, sizeof(txmsg) / 4);
+
+	return 0;
+}
+
+
+/**
+ * upwr_vtm_dva_domain_request() - request uPower to dva one domain to the given work mode
+ * @domain_id: RTD, APD, LPAV, defined in upower_defs.h
+ * @mode: OD (over drive) mode, ND (normal drive)  mode, LD (lower drive) mode,
+ * type: enum work_mode, defined in upower_defs.h
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to switch one domain to the given work mode.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * M33/A35 need to check the execute result
+ * 0 means success, 1 means hold on(A35 request LD, but GPU request OD), negative value means failure.
+ * upower fw needs support cocurrent request from M33 and A35.
+ * upower fw needs support multiple masters requesting different modes.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_vtm_dva_domain_request(uint32_t domain_id, enum work_mode mode, upwr_callb callb)
+{
+	upwr_volt_dva_req_domain_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)   return -3;
+    if (UPWR_SG_BUSY(UPWR_SG_VOLTM)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_VOLTM, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_VOLTM, UPWR_VTM_DVA_REQ_DOMAIN);
+
+	txmsg.args.mode = mode;
+	txmsg.args.domain = domain_id;
+
+	upwr_srv_req(UPWR_SG_VOLTM, (uint32_t*)&txmsg, sizeof(txmsg) / 4);
+
+	return 0;
+}
+
+/**
+ * upwr_vtm_power_measure() - request uPower to measure power consumption
+ * @ssel: This field determines which power switches will have their currents sampled to be accounted for a
+current/power measurement. Support 0~7
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to measure power consumption
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * The power consumption data read from uPower via
+ * the callback argument ret, or written to the variable pointed by retptr,
+ * if polling is used (calls upwr_req_status or upwr_poll_req_status).
+ * ret (or *retptr) also returns the data written on writes.
+ * upower fw needs support cocurrent request from M33 and A35.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+int upwr_vtm_power_measure(uint32_t ssel, upwr_callb callb)
+{
+	upwr_volt_pmeter_meas_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)   return -3;
+    if (UPWR_SG_BUSY(UPWR_SG_VOLTM)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_VOLTM, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_VOLTM, UPWR_VTM_PMETER_MEAS);
+
+	txmsg.hdr.arg = ssel;
+
+	upwr_srv_req(UPWR_SG_VOLTM, (uint32_t*)&txmsg, sizeof(txmsg) / 4);
+
+	return 0;
+}
+
+/**
+ * upwr_vtm_vmeter_measure() - request uPower to measure voltage
+ * @vdetsel: Voltage Detector Selector, support 0~3
+ * 00b - RTD sense point
+   01b - LDO output
+   10b - APD domain sense point
+   11b - AVD domain sense point
+   Refer to upower_defs.h
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to use vmeter to measure voltage
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * The voltage data read from uPower via
+ * the callback argument ret, or written to the variable pointed by retptr,
+ * if polling is used (calls upwr_req_status or upwr_poll_req_status).
+ * ret (or *retptr) also returns the data written on writes.
+ * upower fw needs support cocurrent request from M33 and A35.
+ *
+ * Refer to RM COREREGVL (Core Regulator Voltage Level)
+ * uPower return VDETLVL to user, user can calculate the real voltage:
+ *
+0b000000(0x00) - 0.595833V
+0b100110(0x26) - 1.007498V
+<value> - 0.595833V + <value>x10.8333mV
+0b110010(0x32) - 1.138V
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+int upwr_vtm_vmeter_measure(uint32_t vdetsel, upwr_callb callb)
+{
+	upwr_volt_vmeter_meas_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)   return -3;
+    if (UPWR_SG_BUSY(UPWR_SG_VOLTM)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_VOLTM, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_VOLTM, UPWR_VTM_VMETER_MEAS);
+
+	txmsg.hdr.arg = vdetsel;
+
+	upwr_srv_req(UPWR_SG_VOLTM, (uint32_t*)&txmsg, sizeof(txmsg) / 4);
+
+	return 0;
+}
+
+/**
+ * upwr_vtm_pmic_config() - Configures the SoC PMIC (Power Management IC).
+ * @config: pointer to a PMIC-dependent struct defining the PMIC configuration.
+ * @size:   size of the struct pointed by config, in bytes.
+ * @callb: pointer to the callback called when configurations are applied.
+ * NULL if no callback is required.
+ *
+ * The function requests uPower to change/define the PMIC configuration.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy,
+ *        -2 if the pointer conversion to physical address failed,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ *
+ * Sample code:
+
+// The tag value is fixed 0x706D6963, used by uPower PMIC driver to judge if the config data are valid.
+#define PMIC_CONFIG_TAG 0x706D6963
+
+// used to define reg_addr_data_arry, user can modify this value
+// or you can use variable-length array
+// or zero-length array
+// or other C language technology skills
+#define PMIC_CONFIG_REG_ARRAY_SIZE  8
+
+struct pmic_reg_addr_data
+{
+    uint32_t reg;       // the target configured register of PMIC IC
+    uint32_t data;      // the value of the target configured register
+};
+
+struct pmic_config_struct
+{
+    uint32_t cfg_tag;       // cfg_tag = PMIC_CONFIG_TAG, used to judge if the config data are valid
+    uint32_t cfg_reg_size;  // how many registers shall be configured
+    struct pmic_reg_addr_data reg_addr_data_array[PMIC_CONFIG_REG_ARRAY_SIZE];
+};
+
 
-	soc = fw_rom_version.soc_id;
+    struct pmic_config_struct pmic_config_struct_data;
+    pmic_config_struct_data.cfg_tag = PMIC_CONFIG_TAG;
+    pmic_config_struct_data.cfg_reg_size = 3;
+
+    pmic_config_struct_data.reg_addr_data_array[0].reg = 0x31 ;
+    pmic_config_struct_data.reg_addr_data_array[0].data = 0x83;
+    pmic_config_struct_data.reg_addr_data_array[1].reg = 0x36;
+    pmic_config_struct_data.reg_addr_data_array[1].data = 0x03;
+    pmic_config_struct_data.reg_addr_data_array[2].reg = 0x38;
+    pmic_config_struct_data.reg_addr_data_array[2].data = 0x03;
+
+    int size = sizeof(pmic_config_struct_data.cfg_tag) +
+                sizeof(pmic_config_struct_data.cfg_reg_size) +
+                pmic_config_struct_data.cfg_reg_size *  (sizeof(uint32_t) + sizeof(uint32_t));
+
+    upower_pwm_chng_pmic_config((void *)&pmic_config_struct_data, size);
+
+
+
+ *
+ * Please must notice that, it will take very long time to finish,
+ * beause it will send many I2C commands to pmic chip.
+ */
+
+int upwr_vtm_pmic_config(const void* config, uint32_t size, upwr_callb callb)
+{
+	upwr_pwm_pmiccfg_msg txmsg = {0};
+	unsigned long ptrval = 0UL; /* needed for X86, ARM64 */
+
+	if (api_state != UPWR_API_READY)   return -3;
+	if (UPWR_SG_BUSY(UPWR_SG_VOLTM)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_VOLTM, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_VOLTM, UPWR_VTM_PMIC_CONFIG);
+
+	if ((ptrval = (unsigned long)os_ptr2phy(config)) == 0)
+		return -2; /* pointer conversion failed */
+
+	txmsg.ptr = upwr_ptr2offset(ptrval,
+				    UPWR_SG_VOLTM,
+				    (size_t)size,
+				    0,
+				    config);
+
+	upwr_srv_req(UPWR_SG_VOLTM, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**---------------------------------------------------------------
+ * TEMPERATURE MANAGEMENT SERVICE GROUP
+ */
+
+/**
+ * upwr_tpm_get_temperature() - request uPower to get temperature of one temperature sensor
+ * @sensor_id: temperature sensor ID, support 0~2
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to measure temperature
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_TEMPM as the service group argument.
+ *
+ * The temperature data read from uPower via
+ * the callback argument ret, or written to the variable pointed by retptr,
+ * if polling is used (calls upwr_req_status or upwr_poll_req_status).
+ * ret (or *retptr) also returns the data written on writes.
+ *
+ * uPower return TSEL to the caller (M33 or A35), caller calculate the real temperature
+ * Tsh = 0.000002673049*TSEL[7:0]^3 + 0.0003734262*TSEL[7:0]^2 +
+0.4487042*TSEL[7:0] - 46.98694
+ *
+ * upower fw needs support cocurrent request from M33 and A35.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+int upwr_tpm_get_temperature(uint32_t sensor_id, upwr_callb callb)
+{
+	upwr_temp_get_cur_temp_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)   return -3;
+    if (UPWR_SG_BUSY(UPWR_SG_TEMPM)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_TEMPM, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_TEMPM, UPWR_TEMP_GET_CUR_TEMP);
+
+	txmsg.args.sensor_id = sensor_id;
+
+	upwr_srv_req(UPWR_SG_TEMPM, (uint32_t*)&txmsg, sizeof(txmsg) / 4);
+
+	return 0;
+}
+
+/**---------------------------------------------------------------
+ * DELAY MANAGEMENT SERVICE GROUP
+ */
+
+/**
+ * upwr_dlm_get_delay_margin() - request uPower to get delay margin
+ * @path: The critical path
+ * @index: Use whitch delay meter
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to get delay margin
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_DELAYM as the service group argument.
+ *
+ * The delay margin data read from uPower via
+ * the callback argument ret, or written to the variable pointed by retptr,
+ * if polling is used (calls upwr_req_status or upwr_poll_req_status).
+ * ret (or *retptr) also returns the data written on writes.
+ * upower fw needs support cocurrent request from M33 and A35.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+int upwr_dlm_get_delay_margin(uint32_t path, uint32_t index, upwr_callb callb)
+{
+	upwr_dmeter_get_delay_margin_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)   return -3;
+    if (UPWR_SG_BUSY(UPWR_SG_DELAYM)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_DELAYM, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_DELAYM, UPWR_DMETER_GET_DELAY_MARGIN);
+
+	txmsg.args.path = path;
+	txmsg.args.index = index;
+
+	upwr_srv_req(UPWR_SG_DELAYM, (uint32_t*)&txmsg, sizeof(txmsg) / 4);
+
+	return 0;
+}
+
+/**
+ * upwr_dlm_set_delay_margin() - request uPower to set delay margin
+ * @path: The critical path
+ * @index: Use whitch delay meter
+ * @delay_margin: the value of delay margin
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to set delay margin
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_DELAYM as the service group argument.
+ *
+ * The result of the corresponding critical path,  failed or not  read from uPower via
+ * the callback argument ret, or written to the variable pointed by retptr,
+ * if polling is used (calls upwr_req_status or upwr_poll_req_status).
+ * ret (or *retptr) also returns the data written on writes.
+ * upower fw needs support cocurrent request from M33 and A35.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+int upwr_dlm_set_delay_margin(uint32_t path, uint32_t index, uint32_t delay_margin, upwr_callb callb)
+{
+	upwr_dmeter_set_delay_margin_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)   return -3;
+    if (UPWR_SG_BUSY(UPWR_SG_DELAYM)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_DELAYM, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_DELAYM, UPWR_DMETER_SET_DELAY_MARGIN);
+
+	txmsg.args.path = path;
+	txmsg.args.index = index;
+	txmsg.args.dm = delay_margin;
+
+	upwr_srv_req(UPWR_SG_DELAYM, (uint32_t*)&txmsg, sizeof(txmsg) / 4);
+
+	return 0;
+}
+
+/**
+ * upwr_dlm_process_monitor() - request uPower to do process monitor
+ * @chain_sel: Chain Cell Type Selection
+ * Select the chain to be used for the clock signal generation.
+ * Support two types chain cell, 0~1
+0b - P4 type delay cells selected
+1b - P16 type delay cells selected
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to do process monitor
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_DELAYM as the service group argument.
+ *
+ * The result of process monitor,  failed or not  read from uPower via
+ * the callback argument ret, or written to the variable pointed by retptr,
+ * if polling is used (calls upwr_req_status or upwr_poll_req_status).
+ * ret (or *retptr) also returns the data written on writes.
+ * upower fw needs support cocurrent request from M33 and A35.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+int upwr_dlm_process_monitor(uint32_t chain_sel, upwr_callb callb)
+{
+	upwr_pmon_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)   return -3;
+    if (UPWR_SG_BUSY(UPWR_SG_DELAYM)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_DELAYM, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_DELAYM, UPWR_PMON_REQ);
+
+	txmsg.args.chain_sel = chain_sel;
+
+	upwr_srv_req(UPWR_SG_DELAYM, (uint32_t*)&txmsg, sizeof(txmsg) / 4);
+
+	return 0;
+}
+
+/**---------------------------------------------------------------
+ * POWER MANAGEMENT SERVICE GROUP
+ */
+
+/**
+ * upwr_pwm_dom_power_on() - Commands uPower to power on the platform of other
+ * domain (not necessarily its core(s)); does not release the core reset.
+ * @domain: identifier of the domain to power on. Defined by SoC-dependent type
+ * soc_domain_t found in upower_soc_defs.h.
+ * @boot_start: must be 1 to start the domain core(s) boot(s), releasing
+ * its (their) resets, or 0 otherwise.
+ * @pwroncallb: pointer to the callback to be called when the uPower has
+ * finished the power on procedure, or NULL if no callback needed
+ * (polling used instead).
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded or
+ * not.
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -2 if the domain passed is the same as the caller,
+ *        -3 if called in an invalid API state
+ */
+
+int upwr_pwm_dom_power_on(soc_domain_t      domain,
+                          int               boot_start,
+                          const upwr_callb  pwroncallb)
+{
+	upwr_pwm_dom_pwron_msg txmsg = {0};
+
+	if (pwr_domain == domain)          return -2;
+	if (api_state != UPWR_API_READY)   return -3;
+	if (UPWR_SG_BUSY(UPWR_SG_PWRMGMT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_PWRMGMT, (upwr_callb)pwroncallb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_PWRMGMT, UPWR_PWM_DOM_PWRON);
+	txmsg.hdr.domain = (uint32_t)domain;
+	txmsg.hdr.arg    = boot_start;
+
+	upwr_srv_req(UPWR_SG_PWRMGMT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**
+ * upwr_pwm_boot_start() - Commands uPower to release the reset of other CPU(s),
+ * starting their boots.
+ * @domain: identifier of the domain to release the reset. Defined by
+ * SoC-dependent type soc_domain_t found in upower_soc_defs.h.
+ * @bootcallb: pointer to the callback to be called when the uPower has finished
+ * the boot start procedure, or NULL if no callback needed
+ * (polling used instead).
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded or
+ * not.
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * The callback calling doesn't mean the CPUs boots have finished:
+ * it only indicates that uPower released the CPUs resets, and can receive
+ * other power management service group requests.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -2 if the domain passed is the same as the caller,
+ *        -3 if called in an invalid API state
+ */
+
+int upwr_pwm_boot_start(soc_domain_t domain, const upwr_callb  bootcallb)
+{
+	upwr_pwm_boot_start_msg txmsg = {0};
+
+	if (pwr_domain == domain)          return -2;
+	if (api_state != UPWR_API_READY)   return -3;
+	if (UPWR_SG_BUSY(UPWR_SG_PWRMGMT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_PWRMGMT, (upwr_callb)bootcallb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_PWRMGMT, UPWR_PWM_BOOT);
+	txmsg.hdr.domain = (uint32_t)domain;
+
+	upwr_srv_req(UPWR_SG_PWRMGMT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**
+ * upwr_pwm_param() - Changes Power Management parameters.
+ * @param: pointer to a parameter structure upwr_pwm_param_t, SoC-dependent,
+ * defined in upwr_soc_defines.h. NULL may be passed, meaning
+ * a request to read the parameter set, in which case it appears in the callback
+ * argument ret, or can be pointed by argument retptr in the upwr_req_status and
+ * upwr_poll_req_status calls, casted to upwr_pwm_param_t.
+ * @callb: response callback pointer; NULL if no callback needed.
+ *
+ * The return value is always the current parameter set value, either in a
+ * read-only request (param = NULL) or after setting a new parameter
+ * (non-NULL param).
+ *
+ * Some parameters may be targeted for a specific domain (see the struct
+ * upwr_pwm_param_t definition in upower_soc_defs.h); this call has implicit
+ * domain target (the same domain from which is called).
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded or
+ * not.
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ */
+
+int upwr_pwm_param(upwr_pwm_param_t* param, const upwr_callb  callb)
+{
+	upwr_pwm_param_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)   return -3;
+        if (UPWR_SG_BUSY(UPWR_SG_PWRMGMT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_PWRMGMT, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_PWRMGMT, UPWR_PWM_PARAM);
+
+	if (param == NULL) {
+		txmsg.hdr.arg = 1;        /* 1= read, txmsg.word2 ignored */
+	}
+	else {
+		txmsg.hdr.arg = 0;        /* 1= write */
+		txmsg.word2   = param->R; /* just 1 word, so that's ok */
+	}
+
+	upwr_srv_req(UPWR_SG_PWRMGMT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**
+ * upwr_pwm_chng_reg_voltage() - Changes the voltage at a given regulator.
+ * @reg: regulator id.
+ * @volt: voltage value; value unit is SoC-dependent, converted from mV by the
+ * macro UPWR_VTM_MILIV, or from micro-Volts by the macro UPWR_VTM_MICROV,
+ * both macros in upower_soc_defs.h
+ * @callb: response callback pointer; NULL if no callback needed.
+ *
+ * The function requests uPower to change the voltage of the given regulator.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_chng_reg_voltage(uint32_t reg, uint32_t volt, upwr_callb callb)
+{
+	upwr_pwm_volt_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)   return -3;
+    if (UPWR_SG_BUSY(UPWR_SG_PWRMGMT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_PWRMGMT, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_PWRMGMT, UPWR_PWM_VOLT);
+
+	txmsg.args.reg = reg;
+	txmsg.args.volt = volt;
+
+	upwr_srv_req(UPWR_SG_PWRMGMT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**
+ * upwr_pwm_freq_setup() - Determines the next frequency target for a given
+ *                         domain and current frequency.
+ * @domain: identifier of the domain to change frequency. Defined by
+ * SoC-dependent type soc_domain_t found in upower_soc_defs.h.
+ * @rail: the pmic regulator number for the target domain.
+ * @target_freq: the target adjust frequency, accurate to MHz
+ *
+ * refer to upower_defs.h structure definition upwr_pwm_freq_msg
+ *
+ * In some SoC implementations this may not be needed (argument is not used),
+ * if uPower can measure the current frequency by itself.
+ * @callb: response callback pointer; NULL if no callback needed.
+ *
+ * The function informs uPower that the given domain frequency has changed or
+ * will change to the given value. uPower firmware will then adjust voltage and
+ * bias to cope with the new frequency (if decreasing) or prepare for it
+ * (if increasing). The function must be called after decreasing the frequency,
+ * and before increasing it. The actual increase in frequency must not occur
+ * before the service returns its response.
+ *
+ * The request is executed if arguments are within range.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_freq_setup(soc_domain_t domain, uint32_t rail, uint32_t target_freq,
+			upwr_callb   callb)
+{
+	upwr_pwm_freq_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)   return -3;
+    if (UPWR_SG_BUSY(UPWR_SG_PWRMGMT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_PWRMGMT, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_PWRMGMT, UPWR_PWM_FREQ);
+
+	txmsg.hdr.domain   = (uint32_t)domain;
+	txmsg.args.rail  = rail;
+	txmsg.args.target_freq  = target_freq;
+
+	upwr_srv_req(UPWR_SG_PWRMGMT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**
+ * upwr_pwm_power_on()- Powers on (not off) one or more switches and ROM/RAMs.
+ * @swton: pointer to an array of words that tells which power switches to
+ *  turn on. Each word in the array has 1 bit for each switch.
+ *  A bit=1 means the respective switch must be turned on,
+ *  bit = 0 means it will stay unchanged (on or off).
+ *  The pointer may be set to NULL, in which case no switch will be changed,
+ *  unless a memory that it feeds must be turned on.
+ *  WARNING: swton must not point to the first shared memory address.
+ * @memon: pointer to an array of words that tells which memories to turn on.
+ *  Each word in the array has 1 bit for each switch.
+ *  A bit=1 means the respective memory must be turned on, both array and
+ *  periphery logic;
+ *  bit = 0 means it will stay unchanged (on or off).
+ *  The pointer may be set to NULL, in which case no memory will be changed.
+ *  WARNING: memon must not point to the first shared memory address.
+ * @callb: pointer to the callback called when configurations are applyed.
+ * NULL if no callback is required.
+ *
+ * The function requests uPower to turn on the PMC and memory array/peripheral
+ * switches that control their power, as specified above.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate memory power state related to overall system state.
+ *
+ * If a memory is requested to turn on, but the power switch that feeds that
+ * memory is not, the power switch will be turned on anyway, if the pwron
+ * array is not provided (that is, if pwron is NULL).
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Callback or polling may return error if the service contends for a resource
+ * already being used by a power mode transition or an ongoing service in
+ * another domain.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy,
+ *        -2 if a pointer conversion to physical address failed,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_power_on(const uint32_t swton[],
+		      const uint32_t memon[],
+		      upwr_callb     callb)
+{
+	upwr_pwm_pwron_msg         txmsg = {0};
+	unsigned long              ptrval = 0UL; /* needed for X86, ARM64 */
+	size_t                     stsize = 0;
+
+	if (api_state != UPWR_API_READY)   return -3;
+        if (UPWR_SG_BUSY(UPWR_SG_PWRMGMT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_PWRMGMT, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_PWRMGMT, UPWR_PWM_PWR_ON);
+
+	if (swton == NULL) txmsg.ptrs.ptr0 = 0; /* NULL pointer -> 0 offset */
+	else if ((ptrval = (unsigned long)os_ptr2phy((void*)swton)) == 0)
+		return -2; /* pointer conversion failed */
+	else txmsg.ptrs.ptr0 = upwr_ptr2offset(ptrval,
+					       UPWR_SG_PWRMGMT,
+					       (stsize = UPWR_PMC_SWT_WORDS*4),
+					       0,
+					       swton);
+
+	if (memon == NULL) txmsg.ptrs.ptr1 = 0; /* NULL pointer -> 0 offset */
+	else if ((ptrval = (unsigned long)os_ptr2phy((void*)memon)) == 0)
+		return -2; /* pointer conversion failed */
+	else txmsg.ptrs.ptr1 = upwr_ptr2offset(ptrval,
+					       UPWR_SG_PWRMGMT,
+					       UPWR_PMC_MEM_WORDS*4,
+					       stsize,
+					       memon);
+
+	upwr_srv_req(UPWR_SG_PWRMGMT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**
+ * upwr_pwm_power_off()- Powers off (not on) one or more switches and ROM/RAMs.
+ * @swtoff: pointer to an array of words that tells which power switches to
+ *  turn off. Each word in the array has 1 bit for each switch.
+ *  A bit=1 means the respective switch must be turned off,
+ *  bit = 0 means it will stay unchanged (on or off).
+ *  The pointer may be set to NULL, in which case no switch will be changed.
+ *  WARNING: swtoff must not point to the first shared memory address.
+ * @memoff: pointer to an array of words that tells which memories to turn off.
+ *  Each word in the array has 1 bit for each switch.
+ *  A bit=1 means the respective memory must be turned off, both array and
+ *  periphery logic;
+ *  bit = 0 means it will stay unchanged (on or off).
+ *  The pointer may be set to NULL, in which case no memory will be changed,
+ *  but notice it may be turned off if the switch that feeds it is powered off.
+ *  WARNING: memoff must not point to the first shared memory address.
+ * @callb: pointer to the callback called when configurations are applyed.
+ * NULL if no callback is required.
+ *
+ * The function requests uPower to turn off the PMC and memory array/peripheral
+ * switches that control their power, as specified above.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate memory power state related to overall system state.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Callback or polling may return error if the service contends for a resource
+ * already being used by a power mode transition or an ongoing service in
+ * another domain.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy,
+ *        -2 if a pointer conversion to physical address failed,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_power_off(const uint32_t swtoff[],
+		       const uint32_t memoff[],
+		       upwr_callb     callb)
+{
+	upwr_pwm_pwroff_msg        txmsg = {0};
+	unsigned long              ptrval = 0UL; /* needed for X86, ARM64 */
+	size_t                     stsize = 0;
+
+	if (api_state != UPWR_API_READY)   return -3;
+    if (UPWR_SG_BUSY(UPWR_SG_PWRMGMT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_PWRMGMT, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_PWRMGMT, UPWR_PWM_PWR_OFF);
+
+	if (swtoff == NULL) txmsg.ptrs.ptr0 = 0; /* NULL pointer -> 0 offset */
+	else if ((ptrval = (unsigned long)os_ptr2phy((void*)swtoff)) == 0)
+		return -2; /* pointer conversion failed */
+	else txmsg.ptrs.ptr0 = upwr_ptr2offset(ptrval,
+					       UPWR_SG_PWRMGMT,
+					       (stsize = UPWR_PMC_SWT_WORDS*4),
+					       0,
+					       swtoff);
+
+	if (memoff == NULL) txmsg.ptrs.ptr1 = 0; /* NULL pointer -> 0 offset */
+	else if ((ptrval = (unsigned long)os_ptr2phy((void*)memoff)) == 0)
+		return -2; /* pointer conversion failed */
+	else txmsg.ptrs.ptr1 = upwr_ptr2offset(ptrval,
+					       UPWR_SG_PWRMGMT,
+					       UPWR_PMC_MEM_WORDS*4,
+					       stsize,
+					       memoff);
+
+	upwr_srv_req(UPWR_SG_PWRMGMT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**
+ * upwr_pwm_mem_retain()- Configures one or more memory power switches to
+ * retain its contents, having the power array on, while its peripheral logic
+ * is turned off.
+ * @mem: pointer to an array of words that tells which memories to put in a
+ *  retention state. Each word in the array has 1 bit for each memory.
+ *  A bit=1 means the respective memory must be put in retention state,
+ *  bit = 0 means it will stay unchanged (retention, fully on or off).
+ * @callb: pointer to the callback called when configurations are applyed.
+ * NULL if no callback is required.
+ *
+ * The function requests uPower to turn off the memory peripheral and leave
+ * its array on, as specified above.
+ * The request is executed if arguments are within range.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Callback or polling may return error if the service contends for a resource
+ * already being used by a power mode transition or an ongoing service in
+ * another domain.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy,
+ *        -2 if a pointer conversion to physical address failed,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_mem_retain(const uint32_t mem[], upwr_callb callb)
+{
+	upwr_pwm_retain_msg        txmsg = {0};
+	unsigned long              ptrval = 0UL; /* needed for X86, ARM64 */
+
+	if (api_state != UPWR_API_READY)   return -3;
+        if (UPWR_SG_BUSY(UPWR_SG_PWRMGMT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_PWRMGMT, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_PWRMGMT, UPWR_PWM_RETAIN);
+
+	if ((ptrval = (unsigned long)os_ptr2phy((void*)mem)) == 0)
+		return -2; /* pointer conversion failed */
+
+	txmsg.ptr = upwr_ptr2offset(ptrval,
+				    UPWR_SG_PWRMGMT,
+				    UPWR_PMC_MEM_WORDS*4,
+				    0,
+				    mem);
+	upwr_srv_req(UPWR_SG_PWRMGMT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**
+ * upwr_pwm_chng_switch_mem() - Turns on/off power on one or more PMC switches
+ * and memories, including their array and peripheral logic.
+ * @swt: pointer to a list of PMC switches to be opened/closed.
+ *  The list is structured as an array of struct upwr_switch_board_t
+ *  (see upower_defs.h), each one containing a word for up to 32 switches,
+ *  one per bit. A bit = 1 means switch closed, bit = 0 means switch open.
+ *  struct upwr_switch_board_t also specifies a mask with 1 bit for each
+ *  respective switch: mask bit = 1 means the open/close action is applied,
+ *  mask bit = 0 means the switch stays unchanged.
+ *  The pointer may be set to NULL, in which case no switch will be changed,
+ *  unless a memory that it feeds must be turned on.
+ *  WARNING: swt must not point to the first shared memory address.
+ * @mem: pointer to a list of switches to be turned on/off.
+ *  The list is structured as an array of struct upwr_mem_switches_t
+ *  (see upower_defs.h), each one containing 2 word for up to 32 switches,
+ *  one per bit, one word for the RAM array power switch, other for the
+ *  RAM peripheral logic power switch. A bit = 1 means switch closed,
+ *  bit = 0 means switch open.
+ *  struct upwr_mem_switches_t also specifies a mask with 1 bit for each
+ *  respective switch: mask bit = 1 means the open/close action is applied,
+ *  mask bit = 0 means the switch stays unchanged.
+ *  The pointer may be set to NULL, in which case no memory switch will be
+ *  changed, but notice it may be turned off if the switch that feeds it is
+ *  powered off.
+ *  WARNING: mem must not point to the first shared memory address.
+ * @callb: pointer to the callback called when the configurations are applied.
+ * NULL if no callback is required.
+ *
+ * The function requests uPower to change the PMC switches and/or memory power
+ * as specified above.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate switch combinations and overall system state.
+ *
+ * If a memory is requested to turn on, but the power switch that feeds that
+ * memory is not, the power switch will be turned on anyway, if the swt
+ * array is not provided (that is, if swt is NULL).
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Callback or polling may return error if the service contends for a resource
+ * already being used by a power mode transition or an ongoing service in
+ * another domain.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy.
+ *        -2 if a pointer conversion to physical address failed,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_chng_switch_mem(const struct upwr_switch_board_t  swt[],
+			     const struct upwr_mem_switches_t  mem[],
+			     upwr_callb                        callb)
+{
+	upwr_pwm_switch_msg        txmsg = {0};
+	unsigned long              ptrval = 0UL; /* needed for X86, ARM64 */
+	size_t                     stsize = 0;
+
+	if (api_state != UPWR_API_READY)   return -3;
+        if (UPWR_SG_BUSY(UPWR_SG_PWRMGMT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_PWRMGMT, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_PWRMGMT, UPWR_PWM_SWITCH);
+
+	if (swt == NULL) txmsg.ptrs.ptr0 = 0; /* NULL pointer -> 0 offset */
+	else if ((ptrval = (unsigned long)os_ptr2phy((void*)swt)) == 0)
+		return -2; /* pointer conversion failed */
+	else txmsg.ptrs.ptr0 = upwr_ptr2offset(ptrval,
+					       UPWR_SG_PWRMGMT,
+					       (stsize = UPWR_PMC_SWT_WORDS*
+					                 sizeof(struct
+						         upwr_switch_board_t)),
+					       0,
+					       swt);
+
+	if (mem == NULL) txmsg.ptrs.ptr1 = 0; /* NULL pointer -> 0 offset */
+	else if ((ptrval = (unsigned long)os_ptr2phy((void*)mem)) == 0)
+		return -2; /* pointer conversion failed */
+	else txmsg.ptrs.ptr1 = upwr_ptr2offset(ptrval,
+					       UPWR_SG_PWRMGMT,
+					       UPWR_PMC_MEM_WORDS*
+					       sizeof(struct
+							  upwr_mem_switches_t),
+					       stsize,
+					       mem);
+
+	upwr_srv_req(UPWR_SG_PWRMGMT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**
+ * upwr_pwm_pmode_config() - Configures a given power mode in a given domain.
+ * @domain: identifier of the domain to which the power mode belongs.
+ * Defined by SoC-dependent type soc_domain_t found in upower_soc_defs.h.
+ * @pmode: SoC-dependent power mode identifier defined by type abs_pwr_mode_t
+ * found in upower_soc_defs.h.
+ * @config: pointer to an SoC-dependent struct defining the power mode
+ * configuration, found in upower_soc_defs.h.
+ * @callb: pointer to the callback called when configurations are applied.
+ * NULL if no callback is required.
+ *
+ * The function requests uPower to change the power mode configuration as
+ * specified above. The request is executed if arguments are within range,
+ * and complies with SoC-dependent restrictions on value combinations.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy,
+ *        -2 if the pointer conversion to physical address failed,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_pmode_config(soc_domain_t   domain,
+			  abs_pwr_mode_t pmode,
+			  const void*    config,
+			  upwr_callb     callb)
+{
+	upwr_pwm_pmode_cfg_msg     txmsg = {0};
+	unsigned long              ptrval = 0UL; /* needed for X86, ARM64 */
+
+	if (api_state != UPWR_API_READY)   return -3;
+	if (UPWR_SG_BUSY(UPWR_SG_PWRMGMT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_PWRMGMT, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_PWRMGMT, UPWR_PWM_CONFIG);
+	txmsg.hdr.domain = (uint32_t)domain;
+	txmsg.hdr.arg    = pmode;
+
+	if ((ptrval = (unsigned long)os_ptr2phy(config)) == 0)
+		return -2; /* pointer conversion failed */
+
+	/* upwr_pwm_pmode_config is an exception:
+           use the pointer (physical addr) as is */
+
+	txmsg.ptr = (uint32_t)ptrval;
+
+	upwr_srv_req(UPWR_SG_PWRMGMT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**
+ * upwr_pwm_reg_config() - Configures the uPower internal regulators.
+ * @config: pointer to the struct defining the regulator configuration;
+ * the struct upwr_reg_config_t is defined in the file upower_defs.h.
+ * @callb: pointer to the callback called when configurations are applied.
+ * NULL if no callback is required.
+ *
+ * The function requests uPower to change/define the configurations of the
+ * internal regulators.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * The service may fail with error UPWR_RESP_RESOURCE if a power mode transition
+ * or the same service (called from another domain) is executing simultaneously.
+ * This error should be interpreted as a "try later" response, as the service
+ * will succeed once those concurrent executions are done, and no other is
+ * started.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy,
+ *        -2 if the pointer conversion to physical address failed,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_reg_config(const struct upwr_reg_config_t* config,
+			upwr_callb   callb)
+{
+	upwr_pwm_regcfg_msg txmsg = {0};
+	unsigned long ptrval = 0UL; /* needed for X86, ARM64 */
+
+	if (api_state != UPWR_API_READY)   return -3;
+	if (UPWR_SG_BUSY(UPWR_SG_PWRMGMT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_PWRMGMT, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_PWRMGMT, UPWR_PWM_REGCFG);
+
+	if ((ptrval = (unsigned long)os_ptr2phy(config)) == 0)
+		return -2; /* pointer conversion failed */
+
+	txmsg.ptr = upwr_ptr2offset(ptrval,
+				    UPWR_SG_PWRMGMT,
+				    sizeof(struct upwr_reg_config_t),
+				    0,
+				    config);
+
+	upwr_srv_req(UPWR_SG_PWRMGMT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**
+ * upwr_pwm_chng_dom_bias() - Changes the domain bias.
+ * @bias: pointer to a domain bias configuration struct (see upower_soc_defs.h).
+ * @callb: pointer to the callback called when configurations are applied.
+ * NULL if no callback is required.
+ *
+ * The function requests uPower to change the domain bias configuration as
+ * specified above. The request is executed if arguments are within range,
+ * with no protections regarding the adequate value combinations and
+ * overall system state.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_chng_dom_bias(const struct upwr_dom_bias_cfg_t* bias,
+			   upwr_callb                        callb)
+{
+	upwr_pwm_dom_bias_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)   return -3;
+	if (UPWR_SG_BUSY(UPWR_SG_PWRMGMT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_PWRMGMT, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_PWRMGMT, UPWR_PWM_DOM_BIAS);
+
+	/* SoC-dependent argument filling, defined in upower_soc_defs.h */
+	UPWR_FILL_DOMBIAS_ARGS(txmsg.hdr.domain, bias, txmsg.args);
+
+	upwr_srv_req(UPWR_SG_PWRMGMT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**
+ * upwr_pwm_chng_mem_bias()- Changes a ROM/RAM power bias.
+ * @domain: identifier of the domain upon which the bias is applied.
+ * Defined by SoC-dependent type soc_domain_t found in upower_soc_defs.h.
+ * @bias: pointer to a memory bias configuration struct (see upower_soc_defs.h).
+ * @callb: pointer to the callback called when configurations are applied.
+ * NULL if no callback is required.
+ *
+ * The function requests uPower to change the memory bias configuration as
+ * specified above. The request is executed if arguments are within range,
+ * with no protections regarding the adequate value combinations and
+ * overall system state.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_chng_mem_bias(soc_domain_t                      domain,
+			   const struct upwr_mem_bias_cfg_t* bias,
+			   upwr_callb                        callb)
+{
+	upwr_pwm_mem_bias_msg txmsg = {0};
+
+	if (api_state != UPWR_API_READY)   return -3;
+	if (UPWR_SG_BUSY(UPWR_SG_PWRMGMT)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_PWRMGMT, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_PWRMGMT, UPWR_PWM_MEM_BIAS);
+
+	txmsg.hdr.domain = (uint32_t)domain;
+
+	/* SoC-dependent argument filling, defined in upower_soc_defs.h */
+	UPWR_FILL_MEMBIAS_ARGS(bias, txmsg.args);
+
+	upwr_srv_req(UPWR_SG_PWRMGMT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+#ifdef UPWR_VERIFICATION
+
+#include "upower_api_verif.h"
+
+/* VERIFICATION ONLY: NOT TO MAKE INTO THE API SPEC, NOT EVEN INTO upower_api.h
+ * upwr_xcp_reg_access()- accesses (read or write) a register inside uPower.
+ * @access: pointer to the access specification struct (see upower_soc_defs.h).
+ *          access->mask determines the bits of access->data written (if any)
+ *          at access->addr; if access->mask = 0, the service performs a read.
+ * @callb: pointer to the callback called when configurations are applied.
+ * NULL if no callback is required.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check a service group response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * This service has as return value the final register value (read value on a
+ * read or the updated value on a write), which is obtained from the callback
+ * argument ret or *retptr in case of polling using the functions
+ * upwr_req_status or upwr_poll_req_status.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy,
+ *        -2 if the pointer conversion to physical address failed,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_xcp_reg_access(const struct upwr_reg_access_t* access,
+			upwr_callb                      callb)
+{
+	upwr_xcp_access_msg txmsg = {0};
+	unsigned long ptrval = 0UL;; /* needed for X86, ARM64 */
+
+	if (api_state != UPWR_API_READY)           return -3;
+	if (UPWR_SG_BUSY(UPWR_SG_EXCEPT))          return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_EXCEPT, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_EXCEPT, UPWR_XCP_SPARE_15);
+
+	if ((ptrval = (unsigned long)os_ptr2phy(access)) == 0)
+		return -2; /* pointer conversion failed */
+
+	txmsg.ptr = UPWR_DRAM_SHARED_BASE_ADDR +
+		    upwr_ptr2offset(ptrval,
+                                    UPWR_SG_EXCEPT,
+                                    sizeof(struct upwr_reg_access_t),
+                                    0,
+				    access);
+
+	upwr_srv_req(UPWR_SG_EXCEPT, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+#endif /* ifdef UPWR_VERIFICATION */
+
+/**---------------------------------------------------------------
+ * DIAGNOSE SERVICE GROUP
+ */
+
+/**
+ * upwr_dgn_mode() - Sets the diagnostic mode.
+ * @mode:  diagnostic mode, which can be:
+ *  - UPWR_DGN_NONE:   no diagnostic recorded
+ *  - UPWR_DGN_TRACE:  warnings, errors, service, internal activity recorded
+ *  - UPWR_DGN_SRVREQ: warnings, errors, service activity recorded
+ *  - UPWR_DGN_WARN:   warnings and errors recorded
+ *  - UPWR_DGN_ALL:    trace, service, warnings, errors, task state recorded
+ *  - UPWR_DGN_ERROR:  only errors recorded
+ *  - UPWR_DGN_ALL2ERR: record all until an error occurs,
+ *    freeze recording on error
+ *  - UPWR_DGN_ALL2HLT: record all until an error occurs,
+ *    executes an ebreak on error, which halts the core if enabled through
+ *    the debug interface
+ * @callb: pointer to the callback called when mode is changed.
+ * NULL if no callback is required.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ */
+
+int upwr_dgn_mode(upwr_dgn_mode_t mode, const upwr_callb callb)
+{
+	upwr_dgn_mode_msg txmsg = {0};
+
+    if (UPWR_SG_BUSY(UPWR_SG_DIAG)) return -1;
+
+	UPWR_USR_CALLB(UPWR_SG_DIAG, callb);
+
+	UPWR_MSG_HDR(txmsg.hdr, UPWR_SG_DIAG, UPWR_DGN_MODE);
+
+	txmsg.hdr.arg = mode;
+
+	upwr_srv_req(UPWR_SG_DIAG, (uint32_t*)&txmsg, sizeof(txmsg)/4);
+
+	return 0;
+}
+
+/**---------------------------------------------------------------
+ * AUXILIARY CALLS
+ */
+
+/**
+ * upwr_rom_version() - informs the ROM firwmware version.
+ * @vmajor: pointer to the variable to get the firmware major version number.
+ * @vminor: pointer to the variable to get the firmware minor version number.
+ * @vfixes: pointer to the variable to get the firmware fixes number.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: SoC id.
+ */
+
+uint32_t upwr_rom_version(uint32_t *vmajor, uint32_t *vminor, uint32_t *vfixes)
+{
+	uint32_t soc;
+
+	upwr_lock(1);
+	soc     = fw_rom_version.soc_id;
 	*vmajor = fw_rom_version.vmajor;
 	*vminor = fw_rom_version.vminor;
 	*vfixes = fw_rom_version.vfixes;
-
+	upwr_lock(0);
 	return soc;
 }
+
+/**
+ * upwr_ram_version() - informs the RAM firwmware version.
+ * @vminor: pointer to the variable to get the firmware minor version number.
+ * @vfixes: pointer to the variable to get the firmware fixes number.
+ *
+ * The 3 values returned are 0 if no RAM firmwmare was loaded and initialized.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: firmware major version number.
+ */
+
+uint32_t upwr_ram_version(uint32_t* vminor, uint32_t* vfixes)
+{
+	uint32_t vmajor;
+
+	upwr_lock(1);
+	vmajor  = fw_ram_version.vmajor;
+	*vminor = fw_ram_version.vminor;
+	*vfixes = fw_ram_version.vfixes;
+	upwr_lock(0);
+	return vmajor;
+}
+
+/**
+ * upwr_req_status() - tells the status of the service group request, and
+ *                     returns a request return value, if any.
+ * @sg: service group of the request
+ * @sgfptr: pointer to the variable that will hold the function id of
+ * the last request completed; can be NULL, in which case it is not used.
+ * @errptr: pointer to the variable that will hold the error code;
+ * can be NULL, in which case it is not used.
+ * @retptr: pointer to the variable that will hold the value returned
+ * by the last request completed (invalid if the last request completed didn't
+ * return any value); can be NULL, in which case it is not used.
+ * Note that a request may return a value even if service error is returned
+ * (*errptr != UPWR_RESP_OK): that is dependent on the specific service.
+ *
+ * This call can be used in a poll loop of a service request completion in case
+ * a callback was not registered.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: service request status: succeeded, failed, or ongoing (busy)
+ */
+
+upwr_req_status_t upwr_req_status(upwr_sg_t     sg,
+				  uint32_t*     sgfptr,
+				  upwr_resp_t*  errptr,
+				  int*          retptr)
+{
+	upwr_req_status_t status;
+
+	upwr_lock(1);
+	if (sgfptr != NULL) *sgfptr =(uint32_t)    sg_rsp_msg[sg].hdr.function;
+	if (errptr != NULL) *errptr =(upwr_resp_t) sg_rsp_msg[sg].hdr.errcode;
+	if (retptr != NULL) *retptr =(int) (sg_rsp_siz[sg] == 2)?
+							sg_rsp_msg[sg].word2:
+							sg_rsp_msg[sg].hdr.ret;
+
+	status = (sg_busy & (1 << sg))?                        UPWR_REQ_BUSY :
+	         (sg_rsp_msg[sg].hdr.errcode == UPWR_RESP_OK)? UPWR_REQ_OK   :
+							       UPWR_REQ_ERR  ;
+	upwr_lock(0);
+	return status;
+}
+
+/**
+ * upwr_poll_req_status() - polls the status of the service group request, and
+ *                          returns a request return value, if any.
+ * @sg: service group of the request
+ * @sgfptr: pointer to the variable that will hold the function id of
+ * the last request completed; can be NULL, in which case it is not used.
+ * @errptr: pointer to the variable that will hold the error code;
+ * can be NULL, in which case it is not used.
+ * @retptr: pointer to the variable that will hold the value returned
+ * by the last request completed (invalid if the last request completed didn't
+ * return any value); can be NULL, in which case it is not used.
+ * Note that a request may return a value even if service error is returned
+ * (*errptr != UPWR_RESP_OK): that is dependent on the specific service.
+ * @attempts: maximum number of polling attempts; if attempts > 0 and is
+ * reached with no service response received, upwr_poll_req_status returns
+ * UPWR_REQ_BUSY and variables pointed by sgfptr, retptr and errptr are not
+ * updated; if attempts = 0, upwr_poll_req_status waits "forever".
+ *
+ * This call can be used to poll a service request completion in case a
+ * callback was not registered.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: service request status: succeeded, failed, or ongoing (busy)
+ */
+
+upwr_req_status_t upwr_poll_req_status(upwr_sg_t     sg,
+				       uint32_t*     sgfptr,
+				       upwr_resp_t*  errptr,
+				       int*          retptr,
+				       uint32_t      attempts)
+{
+	uint32_t          i;
+	upwr_req_status_t ret;
+
+	if (attempts == 0)
+	{
+		while ((ret = upwr_req_status(sg, sgfptr, errptr, retptr)) ==
+		       UPWR_REQ_BUSY)
+		{
+			#ifdef UPWR_BLOCK_LEVEL
+			WAIT_CLK(10); /* waiting loop must advance clock */
+			#endif
+		}
+		return ret;
+	}
+
+	for (i = 0; i < attempts; i++)
+	{
+		if ((ret = upwr_req_status(sg, sgfptr, errptr, retptr)) !=
+		    UPWR_REQ_BUSY) break;
+
+		#ifdef UPWR_BLOCK_LEVEL
+		WAIT_CLK(10); /* waiting loop must advance clock */
+		#endif
+	}
+	return ret;
+}
+
+/**
+ * upwr_alarm_code() - returns the alarm code of the last alarm occurrence.
+ *
+ * The value returned is not meaningful if no alarm was issued by uPower.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: alarm code, as defined by the type upwr_alarm_t in upwr_soc_defines.h
+ */
+
+upwr_alarm_t upwr_alarm_code()
+{
+	return (upwr_alarm_t)(3 & (mu->FSR.R >> 1)); /* FSR[2:1] */
+}
+
+/**---------------------------------------------------------------
+ * TRANSMIT/RECEIVE PRIMITIVES
+ * ---------------------------------------------------------------
+ */
+
+/*
+ * upwr_copy2tr() - copies a message to the MU TR registers;
+ * fill the TR registers before writing TIEN to avoid early interrupts;
+ * also, fill them from the higher index to the lowest, so the receive
+ * interrupt flag RF[0] will be the last to set, regardless of message size;
+ */
+
+void upwr_copy2tr(struct MU_tag* local_mu, const uint32_t* msg, unsigned int size)
+{
+	for (int i = size - 1; i > -1; i--) local_mu->TR[i].R = msg[i];
+}
+
+/**
+ * upwr_tx() - queues a message for transmission.
+ * @msg : pointer to the message sent.
+ * @size: message size in 32-bit words
+ * @callback: pointer to a function to be called when transmission done;
+ *            can be NULL, in which case no callback is done.
+ *
+ * This is an auxiliary function used by the rest of the API calls.
+ * It is normally not called by the driver code, unless maybe for test purposes.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: number of vacant positions left in the trasmission queue, or
+ *         -1 if the queue was already full when upwr_tx was called, or
+ *         -2 if any argument is invalid (like size off-range)
+ */
+
+int upwr_tx(const uint32_t*         msg,
+            unsigned int            size,
+            UPWR_TX_CALLB_FUNC_T    callback)
+{
+	if (size >  UPWR_MU_MSG_SIZE) return -2;
+	if (size ==                0) return -2;
+
+	if (mu->TSR.R != UPWR_MU_TSR_EMPTY)
+		return -1;  /* not all TE bits in 1: some data to send still */
+
+	mu_tx_callb = callback;
+
+	upwr_copy2tr(mu, msg, size);
+	mu->TCR.R = 1 << (size - 1);
+
+	mu_tx_pend = 1;
+
+	return 0;
+}
+
+/**
+ * upwr_rx() - unqueues a received message from the reception queue.
+ * @msg: pointer to the message destination buffer.
+ * @size: pointer to variable to hold message size in 32-bit words.
+ *
+ * This is an auxiliary function used by the rest of the API calls.
+ * It is normally not called by the driver code, unless maybe for test purposes.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: number of messages remaining in the reception queue, or
+ *         -1 if the queue was already empty when upwr_rx was called, or
+ *         -2 if any argument is invalid (like mu off-range)
+ */
+
+int upwr_rx(char *msg, unsigned int *size)
+{
+	unsigned int len = mu->RSR.R;
+
+	len = (len == 0x0)? 0:
+	      (len == 0x1)? 1:
+	      #if UPWR_MU_MSG_SIZE > 1
+	      (len == 0x3)? 2:
+	      #if UPWR_MU_MSG_SIZE > 2
+	      (len == 0x7)? 3:
+	      #if UPWR_MU_MSG_SIZE > 3
+	      (len == 0xF)? 4:
+	      #endif
+	      #endif
+	      #endif
+	                    0xFFFFFFFF; /* something wrong */
+
+	if (len  == 0xFFFFFFFF) return -3;
+	if ((*size = len) == 0) return -1;
+
+	/* copy the received message to the rx queue,
+         * so the interrupts are cleared;*/
+    msg_copy(msg, (char *)&mu->RR[0], len);
+
+	mu->RCR.R = 1; /* enable only RR[0] receive interrupt */
+
+	return 0;
+}
+
+/**
+ * upwr_rx_callback() - sets up a callback for a message receiving event.
+ * @callback: pointer to a function to be called when a message arrives;
+ *            can be NULL, in which case no callback is done.
+ *
+ * This is an auxiliary function used by the rest of the API calls.
+ * It is normally not called by the driver code, unless maybe for test purposes.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok; -2 if any argument is invalid (mu off-range).
+ */
+
+int upwr_rx_callback(UPWR_RX_CALLB_FUNC_T    callback)
+{
+	mu_rx_callb = callback;
+
+	return 0;
+}
+
+/**
+ * msg_copy() - copies a message.
+ * @dest: pointer to the destination message.
+ * @src : pointer to the source message.
+ * @size: message size in words.
+ *
+ * This is an auxiliary function used by the rest of the API calls.
+ * It is normally not called by the driver code, unless maybe for test purposes.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: none (void)
+ */
+
+void msg_copy(char *dest, char *src, unsigned int size)
+{
+    for (uint32_t i = 0; i < size * sizeof(uint32_t); i++)
+    {
+        dest[i] = src[i];
+    }
+}
+
+#ifdef  __cplusplus
+#ifndef UPWR_NAMESPACE /* extern "C" 'cancels' the effect of namespace */
+} /* extern "C" */
+#endif
+#endif
+
diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_api.h b/arch/arm/mach-imx/imx8ulp/upower/upower_api.h
index 5cd7802a3db..c67f37572fd 100644
--- a/arch/arm/mach-imx/imx8ulp/upower/upower_api.h
+++ b/arch/arm/mach-imx/imx8ulp/upower/upower_api.h
@@ -1,258 +1,1853 @@
 /* SPDX-License-Identifier: BSD-3-Clause */
+/* +FHDR------------------------------------------------------------------------
+ * Copyright 2019-2021 NXP
+ * -----------------------------------------------------------------------------
+ * FILE NAME      : upower_api.h
+ * DEPARTMENT     : BSTC - Campinas, Brazil
+ * AUTHOR         : Celso Brites
+ * AUTHOR'S EMAIL : celso.brites@nxp.com
+ * -----------------------------------------------------------------------------
+ * RELEASE HISTORY
+ * VERSION DATE        AUTHOR                  DESCRIPTION
+ *
+ * $Log: upower_api.h.rca $
+ *
+ *  Revision: 1.216 Fri May 28 06:27:06 2021 nxa55768
+ *  powersys_fw_048.011.012.006
+ *
+ *
+ *  Revision: 1.42 Tue Apr 27 12:45:06 2021 nxa11511
+ *  Fixes from the spec shared review -> new spec version 20210430.
+ *  Adds new service upwr_pwm_reg_config.
+ *
+ *  Revision: 1.36 Fri Oct 23 13:19:58 2020 nxa11511
+ *  Deleted the GPL license statements, leaving only BSD, as it is compatible with Linux and good for closed ROM/firmware code.
+ *
+ *  Revision: 1.35 Mon Sep 14 15:30:50 2020 nxa11511
+ *  New upwr_xcp_sw_alarm argument code.
+ *  also adds new associated API auxiliary call upwr_alarm_code()
+ *
+ *  Revision: 1.29 Mon Jun  8 06:44:56 2020 nxa11511
+ *  Adds #include "upower_api_verif.h" (under #ifdef UPWR_VERIFICATION)
+ *
+ *  Revision: 1.25 Mon Mar 30 14:28:47 2020 nxa11511
+ *  Attaching Log message:
+ *  API functions upwr_power_on and upwr_boot_start deleted.
+ *  API functions upwr_xcp_power_on and upwr_xcp_boot_start moved to the Power Management service group;
+ *  renamed to upwr_pwm_dom_power_on and upwr_pwm_boot_start
+ *
+ *  Revision: 1.23 Mon Mar  2 12:23:19 2020 nxa11511
+ *  Updates comments to the new version 20200222.
+ *
+ *  Revision: 1.21 Sun Feb 23 15:22:10 2020 nxa10721
+ *  Added upwr_pwm_chng_pmc_switch() for backward compatibility
+ *
+ *  Revision: 1.20 Fri Feb 21 18:31:28 2020 nxa11511
+ *  Updates version to 20200222.
+ *
+ *  Revision: 1.13 Fri Aug 23 17:52:39 2019 nxa11511
+ *  Changes ok/ko response to an error code.
+ *  Adds Exception service requests.
+ *  Adds bias setting functions and Diagnostic mode function.
+ *  Comments formated for spec extraction.
+ *  Introdutory text added.
+ *
+ *  Revision: 1.7 Sat Aug 10 09:05:13 2019 nxa11511
+ *  No longer gets UPWR_NAMESPACE.
+ *  Fixes some strict compiling errors.
+ *
+ *  Revision: 1.5 Wed Jun 12 15:45:07 2019 nxa11511
+ *  Number of MUs now #defined by UPWR_MU_INSTANCES.
+ *  Adds optional namespace definition with #define UPWR_NAMESPACE.
+ *
+ *  Revision: 1.4 Wed Apr 10 14:44:05 2019 nxa11511
+ *  Adds const to upwr_tx argument msg.
+ *
+ * -----------------------------------------------------------------------------
+ * KEYWORDS: micro-power uPower driver API
+ * -----------------------------------------------------------------------------
+ * PURPOSE: uPower driver API
+ * -----------------------------------------------------------------------------
+ * PARAMETERS:
+ * PARAM NAME RANGE:DESCRIPTION:       DEFAULTS:                           UNITS
+ * -----------------------------------------------------------------------------
+ * REUSE ISSUES: no reuse issues
+ * -FHDR------------------------------------------------------------------------
+ */
+
+#ifndef _UPWR_API_H_
+#define _UPWR_API_H_
+
+#ifdef UPWR_BLOCK_LEVEL
+
+#include <stdint.h> /* this include breaks the SoC compile - TBD why? */
+
+/* Includes/defines for use in block level simulation */
+
+#include "upmu.hh" /* emulated structure */
+
+#else
+
+/* Includes/definitions for use in production code */
+
+#include "upmu.h"
+
+#endif /* UPWR_BLOCK_LEVEL */
+
+/* Includes/definitions for use in both block level simulation and production */
+
+#include "upower_defs.h"
+
+#ifdef  __cplusplus
+#ifndef UPWR_NAMESPACE /* extern "C" 'cancels' the effect of namespace */
+extern "C" {
+#endif
+#endif
+
+/******************************************************************************
+ * uPower API Overview and Concepts
+ *
+ * Version: 20210820 Copyright 2019-2021 NXP
+ *
+ * This API is intended to be used by the OS drivers (Linux, FreeRTOS etc)
+ * as well as bare metal drivers to command and use services from the uPower.
+ * It aims to be OS-independent.
+ *
+ * The API functions fall in 3 categories:
+ *  - initialization/start-up
+ *  - service requests
+ *  - auxiliary
+ *
+ * The communication with the uPower is mostly made through the Message Unit
+ * (MU) IP. uPower provides one MU for each CPU cluster in a different
+ * power domain. An API instance runs on each CPU cluster.
+ *
+ * The API assumes each SoC power domain/CPU cluster receives 2 interrupts
+ * from the uPower MU:
+ *  1. Tx/Rx, which is issued on both transmission and reception
+ *  2. Exception interrupt, to handle critical alams, catastrophic errors, etc.
+ *     This interrupt should have a high priority, preferably an NMI.
+ *
+ * The normal uPower operation is done by service requests. There is an API
+ * function for each service request, and all service requests send back a
+ * response, at least to indicate success/failure.
+ * The service request functions are non-blocking, and their completion can be
+ * tracked in two ways:
+ *  1. by a callback, registered when the service request call is made by
+ *     passing the callback function pointer; a NULL pointer may be passed,
+ *     in which case no callback is made.
+ *  2. by polling, using the auxiliary functions upwr_req_status or
+ *     upwr_poll_req_status;
+ *     polling must be used if no callback is registered, but callbacks and
+ *     polling are completely independent.
+ *
+ * Note: a service request must not be started from a callback.
+ *
+ * uPower service requests are classified in Service Groups.
+ * Each Service Group has a set of related functions, named upwr_XXX_,
+ * where XXX is a 3-letter service group mnemonic. The service groups are:
+ *  - Exception Service Group - upwr_xcp_*
+ *     ~ gathers functions that deal with errors and other processes outside
+ *       the functional scope.
+ *  - Power Management Service Group - upwr_pwm_*
+ *     ~ functions to control switches, configure power modes, set internal voltage etc
+ *  - Delay Measurement Service Group - upwr_dlm_*
+ *     ~ delay measurements function using the process monitor and delay meter
+ *  - Voltage Measurement Service Group - upwr_vtm_*
+ *     ~ functions for voltage measurements, comparisons, alarms, power meter, set PMIC rail voltage
+ *  - Temperature Measurement Service Group - upwr_tpm_*
+ *     ~ functions for temperature measurements, comparisons, alarms
+ *  - Current Measurement Service Group  - upwr_crm_*
+ *     ~ functions for current and charge measurement
+ *  - Diagnostic Service Group - upwr_dgn_*
+ *     ~ functions for log configuration and statistics collecting
+ *
+ * Service requests follow this "golden rule":
+ * *** No two requests run simultaneously for the same service group,
+ *     on the same domain ***
+ * They can run simultaneously on different domains (RTD/APD), and can also run
+ * simultaneously if belong to different service groups (even on same domain).
+ * Therefore, requests to the same service group on the same domain must be
+ * serialized. A service request call returns error if there is another request
+ * on the same service group pending, waiting a response (on the same domain).
+ *
+ * A request for continuous service does not block the service group.
+ * For instance, a request to "measure the temperature each 10 miliseconds"
+ * responds quickly, unlocks the service group, and the temperature
+ * continues to be measured as requested, every 10 miliseconds from then on.
+ *
+ * Service Groups have a fixed priority in the API, from higher to lower:
+ *  1. Exception
+ *  2. Power Management
+ *  3. Delay Measurement
+ *  4. Voltage Measurement
+ *  5. Current Measurement
+ *  6. Temperature Measurement
+ *  7. Diagnostics
+ *
+ * The priority above only affects the order in which requests are sent to the
+ * uPower firmware: request to the higher priority Service Group is sent first,
+ * even if the call was made later, if there is an MU transmission pending,
+ * blocking it. The service priorities in the firmware depend on other factors.
+ *
+ * Services are requested using API functions. A service function returns with
+ * no error if a request was successfully made, but it doesn't mean the service
+ * was completed. The service is executed asynchronously, and returns a result
+ * (at least success/fail) via a callback or polling for service status.
+ * The possible service response codes are:
+ * - UPWR_RESP_OK = 0,     : no error
+ * - UPWR_RESP_SG_BUSY     : service group is busy
+ * - UPWR_RESP_SHUTDOWN    : services not up or shutting down
+ * - UPWR_RESP_BAD_REQ     : invalid request (usually invalid argumnents)
+ * - UPWR_RESP_BAD_STATE   : system state doesn't allow perform the request
+ * - UPWR_RESP_UNINSTALLD  : service or function not installed
+ * - UPWR_RESP_UNINSTALLED : service or function not installed (alias)
+ * - UPWR_RESP_RESOURCE    : resource not available
+ * - UPWR_RESP_TIMEOUT     : service timeout
+ */
+
+/**
+ * upwr_callb()-generic function pointer for a request return callback;
+ * @sg: request service group
+ * @func: service request function id.
+ * @errcode: error code.
+ * @ret: return value, if any. Note that a request may return a value even if
+ * service error is returned (errcode != UPWR_RESP_OK); that is dependent on
+ * the specific service.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: none (void)
+ */
+typedef void (*upwr_callb)(upwr_sg_t     sg,
+			   uint32_t      func,
+			   upwr_resp_t   errcode,
+			   int           ret);
+
+/**---------------------------------------------------------------
+ * INITIALIZATION, CONFIGURATION
+ *
+ * A reference uPower initialization sequence goes as follows:
+ *
+ * 1. host CPU calls upwr_init.
+ * 2. (optional) host checks the ROM version and SoC code calling upwr_vers(...)
+ *    and optionally performs any configuration or workaround accordingly.
+ * 3. host CPU calls upwr_start to start the uPower services, passing a
+ *    service option number.
+ *    If no RAM code is loaded or it has no service options, the launch option
+ *    number passed must be 0, which will start the services available in ROM.
+ *    upwr_start also receives a pointer to a callback called by the API
+ *    when the firmware is ready to receive service requests.
+ *    The callback may be replaced by polling, calling upwr_req_status in a loop
+ *    or upwr_poll_req_status; in this case the callback pointer may be NULL.
+ *    A host may call upwr_start even if the services were already started by
+ *    any host: if the launch option is the same, the response will be ok,
+ *    but will indicate error if the services were already started with a
+ *    different launch option.
+ * 4. host waits for the callback calling, or polling finishing;
+ *    if no error is returned, it can start making service calls using the API.
+ *
+ * Variations on that reference sequence are possible:
+ *  - the uPower services can be started using the ROM code only, which includes
+ *    the basic Power Management services, among others, with launch option
+ *    number = 0.
+ *    The code RAM can be loaded while these services are running and,
+ *    when the loading is done, the services can be re-started with these 2
+ *    requests executed in order: upwr_xcp_shutdown and upwr_start,
+ *    using the newly loaded RAM code (launch option > 0).
+ *
+ * NOTE: the initialization call upwr_init is not effective and
+ *       returns error when called after the uPower services are started.
+ */
+
+/**
+ * upwr_init() - API initialization; must be the first API call after reset.
+ * @domain: SoC-dependent CPU domain id; identifier used by the firmware in
+ * many services. Defined by SoC-dependent type soc_domain_t found in
+ * upower_soc_defs.h.
+ * @muptr: pointer to the MU instance.
+ * @mallocptr: pointer to the memory allocation function
+ * @physaddrptr: pointer to the function to convert pointers to
+ * physical addresses. If NULL, no conversion is made (pointer=physical address)
+ * @isrinstptr: pointer to the function to install the uPower ISR callbacks;
+ * the function receives the pointers to the MU tx/rx and Exception ISRs
+ * callbacks, which must be called from the actual system ISRs.
+ * The function pointed by isrinstptr must also enable the interrupt at the
+ * core/interrupt controller, but must not enable the interrupt at the MU IP.
+ * The system ISRs are responsible for dealing with the interrupt controller,
+ * performing any other context save/restore, and any other housekeeping.
+ * @lockptr: pointer to a function that prevents MU interrupts (if argrument=1)
+ * or allows it (if argument=0). The API calls this function to make small
+ * specific code portions thread safe. Only MU interrupts must be avoided,
+ * the code may be suspended for other reasons.
+ * If no MU interrupts can happen during the execution of an API call or
+ * callback, even if enabled, for some other reason (e.g. interrupt priority),
+ * then this argument may be NULL.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if failed to allocate memory, or use some other resource.
+ *        -2 if any argument is invalid.
+ *        -3 if failed to send the ping message.
+ *        -4 if failed to receive the initialization message, or was invalid
+ */
+
+typedef void* (*upwr_malloc_ptr_t)(long unsigned int); /* malloc function ptr */
+typedef void* (*upwr_phyadr_ptr_t)(const void*);   /* pointer->physical address
+                                                      conversion function ptr */
+
 /*
- * Copyright 2020 NXP
+ * upwr_lock_ptr_t: pointer to a function that prevents MU interrupts
+ * (if argrument lock=1) or allows it (if argument lock=0).
+ * The API calls this function to make small specific code portions thread safe.
+ * Only MU interrupts must be avoided, the code may be suspended for other
+ * reasons.
  */
+typedef void  (*upwr_lock_ptr_t)(int lock);
 
-enum soc_domain {
-	RTD_DOMAIN = 0,
-	APD_DOMAIN = 1,
-	UPWR_MAIN_DOMAINS,                           /* RTD, AVD */
-	AVD_DOMAIN = UPWR_MAIN_DOMAINS,
-	UPWR_DOMAIN_COUNT,                           /* RTD, APD, AVD */
-	PSD_DOMAIN = UPWR_DOMAIN_COUNT,
-	UPWR_ALL_DOMAINS                             /* RTD, APD, AVD, PSD */
-};
+typedef void (*upwr_isr_callb)(void);
 
-enum upwr_api_state {
-	UPWR_API_INIT_WAIT,        /* waiting for ROM firmware initialization */
-	UPWR_API_INITLZED,         /* ROM firmware initialized */
-	UPWR_API_START_WAIT,       /* waiting for start services */
-	UPWR_API_READY             /* ready to receive service requests */
-};
+typedef void (*upwr_inst_isr_ptr_t)(upwr_isr_callb txrx_isr,
+				    upwr_isr_callb excp_isr);
 
-enum upwr_sg { /* Service Groups in priority order, high to low */
-	UPWR_SG_EXCEPT,   /* 0 = exception           */
-	UPWR_SG_PWRMGMT, /* 1 = power management    */
-	UPWR_SG_DELAYM,   /* 2 = delay   measurement */
-	UPWR_SG_VOLTM,   /* 3 = voltage measurement */
-	UPWR_SG_CURRM,    /* 4 = current measurement */
-	UPWR_SG_TEMPM,    /* 5 = temperature measurement */
-	UPWR_SG_DIAG,     /* 6 = diagnostic  */
-	UPWR_SG_COUNT
-};
+int upwr_init(	soc_domain_t               domain,
+		struct MU_tag*             muptr,
+		const  upwr_malloc_ptr_t   mallocptr,
+		const  upwr_phyadr_ptr_t   phyadrptr,
+		const  upwr_inst_isr_ptr_t isrinstptr,
+		const  upwr_lock_ptr_t     lockptr);
 
-enum  upwr_xcp_f {		/* Exception Functions */
-	/* 0 = init msg (not a service request itself) */
-	UPWR_XCP_INIT,
-	/* 0 = also ping request, since its response is an init msg */
-	UPWR_XCP_PING = UPWR_XCP_INIT,
-	UPWR_XCP_START,    /* 1 = service start: upwr_start (not a service request itself) */
-	UPWR_XCP_SHUTDOWN, /*  2 = service shutdown: upwr_xcp_shutdown */
-	UPWR_XCP_CONFIG,   /*  3 = uPower configuration: upwr_xcp_config */
-	UPWR_XCP_SW_ALARM, /*  4 = uPower software alarm: upwr_xcp_sw_alarm */
-	UPWR_XCP_I2C,      /*  5 = I2C access: upwr_xcp_i2c_access */
-	UPWR_XCP_SPARE_6,  /*  6 = spare */
-	UPWR_XCP_SET_DDR_RETN,  /*  7 = set/clear ddr retention */
-	UPWR_XCP_SPARE_8,  /*  8 = spare */
-	UPWR_XCP_SPARE_9,  /*  9 = spare */
-	UPWR_XCP_SPARE_10, /* 10 = spare */
-	UPWR_XCP_SPARE_11, /* 11 = spare */
-	UPWR_XCP_SPARE_12, /* 12 = spare */
-	UPWR_XCP_SPARE_13, /* 13 = spare */
-	UPWR_XCP_SPARE_14, /* 14 = spare */
-	UPWR_XCP_SPARE_15, /* 15 = spare */
-	UPWR_XCP_F_COUNT
-};
+/**
+ * upwr_start() - Starts the uPower services.
+ * @launchopt: a number to select between multiple launch options,
+ * that may define, among other things, which services will be started,
+ * or which services implementations, features etc.
+ * launchopt = 0 selects a subset of services implemented in ROM;
+ * any other number selects service sets implemented in RAM, launched
+ * by the firmware function ram_launch; if an invalid launchopt value is passed,
+ * no services are started, and the callback returns error (see below).
+ * @rdycallb: pointer to the callback to be called when the uPower is ready
+ * to receive service requests. NULL if no callback needed.
+ * The callback receives as arguments the RAM firmware version numbers.
+ * If all 3 numbers (vmajor, vminor, vfixes) are 0, that means the
+ * service launching failed.
+ * Firmware version numbers will be the same as ROM if launchopt = 0,
+ * selecting the ROM services.
+ *
+ * upwr_start can be called by any domain even if the services are already
+ * started: it has no effect, returning success, if the launch option is the
+ * same as the one that actually started the service, and returns error if
+ * called with a different option.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded or
+ * not.
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_EXCEPT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if a resource failed,
+ *        -2 if the domain passed is the same as the caller,
+ *        -3 if called in an invalid API state
+ */
 
-enum upwr_resp { /* response error codes */
-	UPWR_RESP_OK = 0,     /* no error */
-	UPWR_RESP_SG_BUSY,    /* service group is busy */
-	UPWR_RESP_SHUTDOWN,   /* services not up or shutting down */
-	UPWR_RESP_BAD_REQ,    /* invalid request */
-	UPWR_RESP_BAD_STATE,  /* system state doesn't allow perform the request */
-	UPWR_RESP_UNINSTALLD, /* service or function not installed */
-	UPWR_RESP_UNINSTALLED =
-	UPWR_RESP_UNINSTALLD, /* service or function not installed (alias) */
-	UPWR_RESP_RESOURCE,   /* resource not available */
-	UPWR_RESP_TIMEOUT,    /* service timeout */
-	UPWR_RESP_COUNT
-};
+typedef void (*upwr_rdy_callb)(uint32_t vmajor,uint32_t vminor,uint32_t vfixes);
 
-#define UPWR_SRVGROUP_BITS	(4)
-#define UPWR_FUNCTION_BITS	(4)
-#define UPWR_PWDOMAIN_BITS	(4)
-#define UPWR_HEADER_BITS	(UPWR_SRVGROUP_BITS + UPWR_FUNCTION_BITS + UPWR_PWDOMAIN_BITS)
-#define UPWR_ARG_BITS		(32 - UPWR_HEADER_BITS)
+int upwr_start(	uint32_t                launchopt,
+		const upwr_rdy_callb    rdycallb);
 
-#define UPWR_DUAL_OFFSET_BITS    ((UPWR_ARG_BITS + 32) >> 1)
 
-struct upwr_msg_hdr {
-	u32 domain   :UPWR_PWDOMAIN_BITS;           /* power domain */
-	u32 srvgrp   :UPWR_SRVGROUP_BITS;          /* service group */
-	u32 function :UPWR_FUNCTION_BITS;             /* function */
-	u32 arg      :UPWR_ARG_BITS;     /* function-specific argument */
-};
+/**---------------------------------------------------------------
+ * EXCEPTION SERVICE GROUP
+ */
 
-union upwr_down_1w_msg {
-	struct upwr_msg_hdr hdr;
-	u32 word; /* message first word */
-};
+/**
+ * upwr_xcp_config() - Applies general uPower configurations.
+ * @config: pointer to the uPower SoC-dependent configuration struct
+ * upwr_xcp_config_t defined in upower_soc_defs.h. NULL may be passed, meaning
+ * a request to read the configuration, in which case it appears in the callback
+ * argument ret, or can be pointed by argument retptr in the upwr_req_status and
+ * upwr_poll_req_status calls, casted to upwr_xcp_config_t.
+ * @callb: pointer to the callback to be called when the uPower has finished
+ * the configuration, or NULL if no callback needed (polling used instead).
+ *
+ * Some configurations are targeted for a specific domain (see the struct
+ * upwr_xcp_config_t definition in upower_soc_defs.h); this call has implicit
+ * domain target (the same domain from which is called).
+ *
+ * The return value is always the current configuration value, either in a
+ * read-only request (config = NULL) or after setting a new cnfiguration
+ * (non-NULL config).
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded or
+ * not.
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_EXCEPT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ */
 
-#define upwr_start_msg union upwr_down_1w_msg
-#define upwr_xcp_ping_msg union upwr_down_1w_msg
+int upwr_xcp_config(const upwr_xcp_config_t* config, const upwr_callb callb);
 
-#define UPWR_RESP_ERR_BITS (4)
-#define UPWR_RESP_HDR_BITS (UPWR_RESP_ERR_BITS + \
-			    UPWR_SRVGROUP_BITS + UPWR_FUNCTION_BITS)
-#define UPWR_RESP_RET_BITS (32 - UPWR_RESP_HDR_BITS)
+/**
+ * upwr_xcp_sw_alarm() - Makes uPower issue an alarm interrupt to given domain.
+ * @domain: identifier of the domain to alarm. Defined by SoC-dependent type
+ * soc_domain_t found in upower_soc_defs.h.
+ * @code: alarm code. Defined by SoC-dependent type upwr_alarm_t found in
+ * upower_soc_defs.h.
+ * @callb: pointer to the callback to be called when the uPower has finished
+ * the alarm, or NULL if no callback needed (polling used instead).
+ *
+ * The function requests the uPower to issue an alarm of the given code as if
+ * it had originated internally. This service is useful mainly to test the
+ * system response to such alarms, or to make the system handle a similar alarm
+ * situation detected externally to uPower.
+ *
+ * The system ISR/code handling the alarm may retrieve the alarm code by calling
+ * the auxiliary function upwr_alarm_code.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded or
+ * not.
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_EXCEPT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ */
 
-struct upwr_resp_hdr {
-	u32 errcode :UPWR_RESP_ERR_BITS;
-	u32 srvgrp  :UPWR_SRVGROUP_BITS;      /* service group */
-	u32 function:UPWR_FUNCTION_BITS;
-	u32 ret     :UPWR_RESP_RET_BITS;      /* return value, if any */
-};
+int upwr_xcp_sw_alarm(soc_domain_t     domain,
+		      upwr_alarm_t     code,
+		      const upwr_callb callb);
 
-struct upwr_up_2w_msg {
-	struct upwr_resp_hdr   hdr;
-	u32               word2;  /* message second word */
-};
+/**
+ * upwr_xcp_set_ddr_retention() - M33/A35 can use this API to set/clear ddr retention
+ * @domain: identifier of the caller domain.
+ * soc_domain_t found in upower_soc_defs.h.
+ * @enable: true, means that set ddr retention, false clear ddr retention.
+ * @callb: NULL
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_EXCEPT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ */
 
-#define upwr_up_max_msg struct upwr_up_2w_msg
+int upwr_xcp_set_ddr_retention(soc_domain_t     domain,
+                        uint32_t enable,
+                        const upwr_callb callb);
 
-union upwr_2pointer_msg {
-	struct upwr_msg_hdr  hdr;
-	struct {
-		u64:UPWR_HEADER_BITS;
-		u64 ptr0:UPWR_DUAL_OFFSET_BITS;
-		u64 ptr1:UPWR_DUAL_OFFSET_BITS;
-	} ptrs;
-};
+/**
+ * upwr_xcp_set_rtd_use_ddr() - M33 call this API to inform uPower, M33 is using ddr
+ * @domain: identifier of the caller domain.
+ * soc_domain_t found in upower_soc_defs.h.
+ * @enable: not 0, true, means that RTD is using ddr. 0, false, means that, RTD is not using ddr.
+ * @callb: NULL
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_EXCEPT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ */
 
-#define upwr_pwm_pwron_msg union upwr_2pointer_msg
+int upwr_xcp_set_rtd_use_ddr(soc_domain_t     domain,
+                        uint32_t enable,
+                        const upwr_callb callb);
 
-struct upwr_pointer_msg {
-	struct upwr_msg_hdr  hdr;
-	u32             ptr; /* config struct offset */
+/**
+ * upwr_xcp_set_rtd_apd_llwu() - M33/A35 can use this API to set/clear rtd_llwu apd_llwu
+ * @domain: set which domain (RTD_DOMAIN, APD_DOMAIN) LLWU.
+ * soc_domain_t found in upower_soc_defs.h.
+ * @enable: true, means that set rtd_llwu or apd_llwu, false clear rtd_llwu or apd_llwu.
+ * @callb: NULL
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_EXCEPT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ */
+
+int upwr_xcp_set_rtd_apd_llwu(soc_domain_t     domain,
+                        uint32_t enable,
+                        const upwr_callb callb);
+/**
+ * upwr_xcp_shutdown() - Shuts down all uPower services and power mode tasks.
+ * @callb: pointer to the callback to be called when the uPower has finished
+ * the shutdown, or NULL if no callback needed
+ * (polling used instead).
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded or
+ * not.
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_EXCEPT as the service group argument.
+ *
+ * At the callback the uPower/API is back to initialization/start-up phase,
+ * so service request calls return error.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ */
+
+int upwr_xcp_shutdown(const upwr_callb callb);
+
+/**
+ * upwr_xcp_i2c_access() - Performs an access through the uPower I2C interface.
+ * @addr: I2C slave address, up to 10 bits.
+ * @data_size: determines the access direction and data size in bytes, up to 4;
+ * negetive data_size determines a read  access with size -data_size;
+ * positive data_size determines a write access with size  data_size;
+ * data_size=0 is invalid, making the service return error UPWR_RESP_BAD_REQ.
+ * @subaddr_size: size of the sub-address in bytes, up to 4; if subaddr_size=0,
+ * no subaddress is used.
+ * @subaddr: sub-address, only used if subaddr_size > 0.
+ * @wdata: write data, up to 4 bytes; ignored if data_size < 0 (read)
+ * @callb: pointer to the callback to be called when the uPower has finished
+ * the access, or NULL if no callback needed
+ * (polling used instead).
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded or
+ * not.
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_EXCEPT as the service group argument.
+ *
+ * The service performs a read (data_size < 0) or a write (data_size > 0) of
+ * up to 4 bytes on the uPower I2C interface. The data read from I2C comes via
+ * the callback argument ret, or written to the variable pointed by retptr,
+ * if polling is used (calls upwr_req_status or upwr_poll_req_status).
+ * ret (or *retptr) also returns the data written on writes.
+ *
+ * Sub-addressing is supported, with sub-address size determined by the argument
+ * subaddr_size, up to 4 bytes. Sub-addressing is not used if subaddr_size=0.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ */
+
+int upwr_xcp_i2c_access(uint16_t         addr,
+			int8_t           data_size,
+			uint8_t          subaddr_size,
+			uint32_t         subaddr,
+			uint32_t         wdata,
+			const upwr_callb callb);
+
+
+/**---------------------------------------------------------------
+ * VOLTAGE MANAGEMENT SERVICE GROUP
+ */
+
+/**
+ * upwr_vtm_pmic_cold_reset() -request cold reset the pmic
+ * pmic will power cycle all the regulators
+ * @callb: response callback pointer; NULL if no callback needed.
+ *
+ * The function requests uPower to cold reset the pmic.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+int upwr_vtm_pmic_cold_reset(upwr_callb callb);
+
+/**
+ * upwr_vtm_set_pmic_mode() -request uPower set pmic mode
+ * @pmic_mode: the target mode need to be set
+ * @callb: response callback pointer; NULL if no callback needed.
+ *
+ * The function requests uPower to set pmic mode
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+int upwr_vtm_set_pmic_mode(uint32_t pmic_mode, upwr_callb callb);
+
+/**
+ * upwr_vtm_chng_pmic_voltage() - Changes the voltage of a given rail.
+ * @rail: pmic rail id.
+ * @volt: the target voltage of the given rail, accurate to uV
+ * If pass volt value 0, means that power off this rail.
+ * @callb: response callback pointer; NULL if no callback needed.
+ *
+ * The function requests uPower to change the voltage of the given rail.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_vtm_chng_pmic_voltage(uint32_t rail, uint32_t volt, upwr_callb callb);
+
+/**
+ * upwr_vtm_get_pmic_voltage() - Get the voltage of a given ral.
+ * @rail: pmic rail id.
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to get the voltage of the given rail.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * The voltage data read from uPower via
+ * the callback argument ret, or written to the variable pointed by retptr,
+ * if polling is used (calls upwr_req_status or upwr_poll_req_status).
+ * ret (or *retptr) also returns the data written on writes.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_vtm_get_pmic_voltage(uint32_t rail, upwr_callb callb);
+
+/**
+ * upwr_vtm_dump_dva_info() - Dump dva information to M33/A35
+ * @dump_addr: uPower dump dva information to the given address
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to dump dva information to the given address
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_vtm_dump_dva_info(uint32_t dump_addr, upwr_callb callb);
+
+/**
+ * upwr_vtm_dva_request() - request uPower to dva an array IDs
+ * @id: id of soc components, such as A35, M33, GPU, SDHC and etc, it is a bit group, extending to two u32 types.
+ * @mode: OD (over drive) mode, ND (normal drive)  mode, LD (lower drive) mode,
+ * type: enum work_mode, defined in upower_defs.h
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to dva an array IDs to the give work mode.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * M33/A35 need to check the execute result
+ * 0 means success, 1 means hold on(A35 request LD, but GPU request OD), negative value means failure.
+ * upower fw needs support cocurrent request from M33 and A35.
+ * upower fw needs support multiple masters requesting different modes.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_vtm_dva_request(const uint32_t id[], enum work_mode mode, upwr_callb callb);
+
+/**
+ * upwr_vtm_dva_request_soc() - request uPower to dva the whole SOC to the given work mode
+ * @mode: OD (over drive) mode, ND (normal drive)  mode, LD (lower drive) mode,
+ * type: enum work_mode, defined in upower_defs.h
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to switch whole SOC to the given work mode.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * M33/A35 need to check the execute result
+ * 0 means success, 1 means hold on(A35 request LD, but GPU request OD), negative value means failure.
+ * upower fw needs support cocurrent request from M33 and A35.
+ * upower fw needs support multiple masters requesting different modes.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_vtm_dva_request_soc(enum work_mode mode, upwr_callb callb);
+
+/**
+ * upwr_vtm_power_measure() - request uPower to measure power consumption
+ * @ssel: This field determines which power switches will have their currents sampled to be accounted for a
+current/power measurement. Support 0~7
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to measure power consumption
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * The power consumption data read from uPower via
+ * the callback argument ret, or written to the variable pointed by retptr,
+ * if polling is used (calls upwr_req_status or upwr_poll_req_status).
+ * ret (or *retptr) also returns the data written on writes.
+ * upower fw needs support cocurrent request from M33 and A35.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+int upwr_vtm_power_measure(uint32_t ssel, upwr_callb callb);
+
+/**
+ * upwr_vtm_vmeter_measure() - request uPower to measure voltage
+ * @vdetsel: Voltage Detector Selector, support 0~3
+ * 00b - RTD sense point
+   01b - LDO output
+   10b - APD domain sense point
+   11b - AVD domain sense point
+   Refer to upower_defs.h
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to use vmeter to measure voltage
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * The voltage data read from uPower via
+ * the callback argument ret, or written to the variable pointed by retptr,
+ * if polling is used (calls upwr_req_status or upwr_poll_req_status).
+ * ret (or *retptr) also returns the data written on writes.
+ * upower fw needs support cocurrent request from M33 and A35.
+ *
+ * Refer to RM COREREGVL (Core Regulator Voltage Level)
+ * uPower return VDETLVL to user, user can calculate the real voltage:
+ *
+0b000000(0x00) - 0.595833V
+0b100110(0x26) - 1.007498V
+<value> - 0.595833V + <value>x10.8333mV
+0b110010(0x32) - 1.138V
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+int upwr_vtm_vmeter_measure(uint32_t vdetsel, upwr_callb callb);
+
+/**
+ * upwr_vtm_pmic_config() - Configures the SoC PMIC (Power Management IC).
+ * @config: pointer to a PMIC-dependent struct defining the PMIC configuration.
+ * @size:   size of the struct pointed by config, in bytes.
+ * @callb: pointer to the callback called when configurations are applied.
+ * NULL if no callback is required.
+ *
+ * The function requests uPower to change/define the PMIC configuration.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy,
+ *        -2 if the pointer conversion to physical address failed,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ *
+ * Sample code:
+
+// The tag value is fixed 0x706D6963, used by uPower PMIC driver to judge if the config data are valid.
+#define PMIC_CONFIG_TAG 0x706D6963
+
+// used to define reg_addr_data_arry, user can modify this value
+// or you can use variable-length array
+// or zero-length array
+// or other C language technology skills
+#define PMIC_CONFIG_REG_ARRAY_SIZE  8
+
+struct pmic_reg_addr_data
+{
+    uint32_t reg;       // the target configured register of PMIC IC
+    uint32_t data;      // the value of the target configured register
 };
 
-struct upwr_i2c_access { /* structure pointed by message upwr_xcp_i2c_msg */
-	u16         addr;
-	s8           data_size;
-	u8          subaddr_size;
-	u32         subaddr;
-	u32         data;
+struct pmic_config_struct
+{
+    uint32_t cfg_tag;       // cfg_tag = PMIC_CONFIG_TAG, used to judge if the config data are valid
+    uint32_t cfg_reg_size;  // how many registers shall be configured
+    struct pmic_reg_addr_data reg_addr_data_array[PMIC_CONFIG_REG_ARRAY_SIZE];
 };
 
-enum upwr_req_status {
+
+    struct pmic_config_struct pmic_config_struct_data;
+    pmic_config_struct_data.cfg_tag = PMIC_CONFIG_TAG;
+    pmic_config_struct_data.cfg_reg_size = 3;
+
+    pmic_config_struct_data.reg_addr_data_array[0].reg = 0x31 ;
+    pmic_config_struct_data.reg_addr_data_array[0].data = 0x83;
+    pmic_config_struct_data.reg_addr_data_array[1].reg = 0x36;
+    pmic_config_struct_data.reg_addr_data_array[1].data = 0x03;
+    pmic_config_struct_data.reg_addr_data_array[2].reg = 0x38;
+    pmic_config_struct_data.reg_addr_data_array[2].data = 0x03;
+
+    int size = sizeof(pmic_config_struct_data.cfg_tag) +
+                sizeof(pmic_config_struct_data.cfg_reg_size) +
+                pmic_config_struct_data.cfg_reg_size *  (sizeof(uint32_t) + sizeof(uint32_t));
+
+    upower_pwm_chng_pmic_config((void *)&pmic_config_struct_data, size);
+
+
+
+ *
+ * Please must notice that, it will take very long time to finish,
+ * beause it will send many I2C commands to pmic chip.
+ */
+int upwr_vtm_pmic_config(const void* config, uint32_t size, upwr_callb callb);
+
+/**---------------------------------------------------------------
+ * TEMPERATURE MANAGEMENT SERVICE GROUP
+ */
+
+/**
+ * upwr_tpm_get_temperature() - request uPower to get temperature of one temperature sensor
+ * @sensor_id: temperature sensor ID, support 0~2
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to measure temperature
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_TEMPM as the service group argument.
+ *
+ * The temperature data read from uPower via
+ * the callback argument ret, or written to the variable pointed by retptr,
+ * if polling is used (calls upwr_req_status or upwr_poll_req_status).
+ * ret (or *retptr) also returns the data written on writes.
+ *
+ * uPower return TSEL to the caller (M33 or A35), caller calculate the real temperature
+ * Tsh = 0.000002673049*TSEL[7:0]^3 + 0.0003734262*TSEL[7:0]^2 +
+0.4487042*TSEL[7:0] - 46.98694
+ *
+ * upower fw needs support cocurrent request from M33 and A35.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+int upwr_tpm_get_temperature(uint32_t sensor_id, upwr_callb callb);
+
+/**---------------------------------------------------------------
+ * DELAY MANAGEMENT SERVICE GROUP
+ */
+
+/**
+ * upwr_dlm_get_delay_margin() - request uPower to get delay margin
+ * @path: The critical path
+ * @index: Use whitch delay meter
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to get delay margin
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_DELAYM as the service group argument.
+ *
+ * The delay margin data read from uPower via
+ * the callback argument ret, or written to the variable pointed by retptr,
+ * if polling is used (calls upwr_req_status or upwr_poll_req_status).
+ * ret (or *retptr) also returns the data written on writes.
+ * upower fw needs support cocurrent request from M33 and A35.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+int upwr_dlm_get_delay_margin(uint32_t path, uint32_t index, upwr_callb callb);
+
+/**
+ * upwr_dlm_set_delay_margin() - request uPower to set delay margin
+ * @path: The critical path
+ * @index: Use whitch delay meter
+ * @delay_margin: the value of delay margin
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to set delay margin
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_DELAYM as the service group argument.
+ *
+ * The result of the corresponding critical path,  failed or not  read from uPower via
+ * the callback argument ret, or written to the variable pointed by retptr,
+ * if polling is used (calls upwr_req_status or upwr_poll_req_status).
+ * ret (or *retptr) also returns the data written on writes.
+ * upower fw needs support cocurrent request from M33 and A35.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+int upwr_dlm_set_delay_margin(uint32_t path, uint32_t index, uint32_t delay_margin, upwr_callb callb);
+
+/**
+ * upwr_dlm_process_monitor() - request uPower to do process monitor
+ * @chain_sel: Chain Cell Type Selection
+ * Select the chain to be used for the clock signal generation.
+ * Support two types chain cell, 0~1
+0b - P4 type delay cells selected
+1b - P16 type delay cells selected
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to do process monitor
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_DELAYM as the service group argument.
+ *
+ * The result of process monitor,  failed or not  read from uPower via
+ * the callback argument ret, or written to the variable pointed by retptr,
+ * if polling is used (calls upwr_req_status or upwr_poll_req_status).
+ * ret (or *retptr) also returns the data written on writes.
+ * upower fw needs support cocurrent request from M33 and A35.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+int upwr_dlm_process_monitor(uint32_t chain_sel, upwr_callb callb);
+
+/**
+ * upwr_dva_domain_request() - request uPower to dva one domain to the given work mode
+ * @domain_id: RTD, APD, LPAV, defined in upower_defs.h
+ * @mode: OD (over drive) mode, ND (normal drive)  mode, LD (lower drive) mode,
+ * type: enum work_mode, defined in upower_defs.h
+ * @callb: response callback pointer; NULL if no callback needed.
+ * (polling used instead)
+ *
+ * The function requests uPower to switch one domain to the given work mode.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_VOLTM as the service group argument.
+ *
+ * M33/A35 need to check the execute result
+ * 0 means success, 1 means hold on(A35 request LD, but GPU request OD), negative value means failure.
+ * upower fw needs support cocurrent request from M33 and A35.
+ * upower fw needs support multiple masters requesting different modes.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_dva_domain_request(uint32_t domain_id, enum work_mode mode, upwr_callb callb);
+
+/**---------------------------------------------------------------
+ * POWER MANAGEMENT SERVICE GROUP
+ */
+
+/**
+ * upwr_pwm_dom_power_on() - Commands uPower to power on the platform of other
+ * domain (not necessarily its core(s)); does not release the core reset.
+ * @domain: identifier of the domain to power on. Defined by SoC-dependent type
+ * soc_domain_t found in upower_soc_defs.h.
+ * @boot_start: must be 1 to start the domain core(s) boot(s), releasing
+ * its (their) resets, or 0 otherwise.
+ * @pwroncallb: pointer to the callback to be called when the uPower has
+ * finished the power on procedure, or NULL if no callback needed
+ * (polling used instead).
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded or
+ * not.
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -2 if the domain passed is the same as the caller,
+ *        -3 if called in an invalid API state
+ */
+
+int upwr_pwm_dom_power_on(soc_domain_t      domain,
+                          int               boot_start,
+                          const upwr_callb  pwroncallb);
+
+/**
+ * upwr_pwm_boot_start() - Commands uPower to release the reset of other CPU(s),
+ * starting their boots.
+ * @domain: identifier of the domain to release the reset. Defined by
+ * SoC-dependent type soc_domain_t found in upower_soc_defs.h.
+ * @bootcallb: pointer to the callback to be called when the uPower has finished
+ * the boot start procedure, or NULL if no callback needed
+ * (polling used instead).
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded or
+ * not.
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * The callback calling doesn't mean the CPUs boots have finished:
+ * it only indicates that uPower released the CPUs resets, and can receive
+ * other power management service group requests.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -2 if the domain passed is the same as the caller,
+ *        -3 if called in an invalid API state
+ */
+
+int upwr_pwm_boot_start(soc_domain_t domain, const upwr_callb  bootcallb);
+
+/**
+ * upwr_pwm_param() - Changes Power Management parameters.
+ * @param: pointer to a parameter structure upwr_pwm_param_t, SoC-dependent,
+ * defined in upwr_soc_defines.h. NULL may be passed, meaning
+ * a request to read the parameter set, in which case it appears in the callback
+ * argument ret, or can be pointed by argument retptr in the upwr_req_status and
+ * upwr_poll_req_status calls, casted to upwr_pwm_param_t.
+ * @callb: response callback pointer; NULL if no callback needed.
+ *
+ * The return value is always the current parameter set value, either in a
+ * read-only request (param = NULL) or after setting a new parameter
+ * (non-NULL param).
+ *
+ * Some parameters may be targeted for a specific domain (see the struct
+ * upwr_pwm_param_t definition in upower_soc_defs.h); this call has implicit
+ * domain target (the same domain from which is called).
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded or
+ * not.
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ */
+
+int upwr_pwm_param(upwr_pwm_param_t* param, const upwr_callb  callb);
+
+/**
+ * upwr_pwm_chng_reg_voltage() - Changes the voltage at a given regulator.
+ * @reg: regulator id.
+ * @volt: voltage value; value unit is SoC-dependent, converted from mV by the
+ * macro UPWR_VOLT_MILIV, or from micro-Volts by the macro UPWR_VOLT_MICROV,
+ * both macros in upower_soc_defs.h
+ * @callb: response callback pointer; NULL if no callback needed.
+ *
+ * The function requests uPower to change the voltage of the given regulator.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate voltage value for the given domain process,
+ * temperature and frequency.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_chng_reg_voltage(uint32_t reg, uint32_t volt, upwr_callb callb);
+
+
+/**
+ * upwr_pwm_freq_setup() - Determines the next frequency target for a given
+ *                         domain and current frequency.
+ * @domain: identifier of the domain to change frequency. Defined by
+ * SoC-dependent type soc_domain_t found in upower_soc_defs.h.
+ * @rail: the pmic regulator number for the target domain.
+ * @target_freq: the target adjust frequency, accurate to MHz
+ *
+ * refer to upower_defs.h structure definition upwr_pwm_freq_msg
+ *
+ * In some SoC implementations this may not be needed (argument is not used),
+ * if uPower can measure the current frequency by itself.
+ * @callb: response callback pointer; NULL if no callback needed.
+ *
+ * The function informs uPower that the given domain frequency has changed or
+ * will change to the given value. uPower firmware will then adjust voltage and
+ * bias to cope with the new frequency (if decreasing) or prepare for it
+ * (if increasing). The function must be called after decreasing the frequency,
+ * and before increasing it. The actual increase in frequency must not occur
+ * before the service returns its response.
+ *
+ * The request is executed if arguments are within range.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_freq_setup(soc_domain_t domain, uint32_t rail, uint32_t target_freq, upwr_callb   callb);
+
+/**
+ * upwr_pwm_power_on()- Powers on (not off) one or more switches and ROM/RAMs.
+ * @swton: pointer to an array of words that tells which power switches to
+ *  turn on. Each word in the array has 1 bit for each switch.
+ *  A bit=1 means the respective switch must be turned on,
+ *  bit = 0 means it will stay unchanged (on or off).
+ *  The pointer may be set to NULL, in which case no switch will be changed,
+ *  unless a memory that it feeds must be turned on.
+ *  WARNING: swton must not point to the first shared memory address.
+ * @memon: pointer to an array of words that tells which memories to turn on.
+ *  Each word in the array has 1 bit for each switch.
+ *  A bit=1 means the respective memory must be turned on, both array and
+ *  periphery logic;
+ *  bit = 0 means it will stay unchanged (on or off).
+ *  The pointer may be set to NULL, in which case no memory will be changed.
+ *  WARNING: memon must not point to the first shared memory address.
+ * @callb: pointer to the callback called when configurations are applyed.
+ * NULL if no callback is required.
+ *
+ * The function requests uPower to turn on the PMC and memory array/peripheral
+ * switches that control their power, as specified above.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate memory power state related to overall system state.
+ *
+ * If a memory is requested to turn on, but the power switch that feeds that
+ * memory is not, the power switch will be turned on anyway, if the pwron
+ * array is not provided (that is, if pwron is NULL).
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Callback or polling may return error if the service contends for a resource
+ * already being used by a power mode transition or an ongoing service in
+ * another domain.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy,
+ *        -2 if a pointer conversion to physical address failed,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_power_on(const uint32_t swton[],
+		      const uint32_t memon[],
+		      upwr_callb     callb);
+
+/**
+ * upwr_pwm_power_off()- Powers off (not on) one or more switches and ROM/RAMs.
+ * @swtoff: pointer to an array of words that tells which power switches to
+ *  turn off. Each word in the array has 1 bit for each switch.
+ *  A bit=1 means the respective switch must be turned off,
+ *  bit = 0 means it will stay unchanged (on or off).
+ *  The pointer may be set to NULL, in which case no switch will be changed.
+ *  WARNING: swtoff must not point to the first shared memory address.
+ * @memoff: pointer to an array of words that tells which memories to turn off.
+ *  Each word in the array has 1 bit for each switch.
+ *  A bit=1 means the respective memory must be turned off, both array and
+ *  periphery logic;
+ *  bit = 0 means it will stay unchanged (on or off).
+ *  The pointer may be set to NULL, in which case no memory will be changed,
+ *  but notice it may be turned off if the switch that feeds it is powered off.
+ *  WARNING: memoff must not point to the first shared memory address.
+ * @callb: pointer to the callback called when configurations are applyed.
+ * NULL if no callback is required.
+ *
+ * The function requests uPower to turn off the PMC and memory array/peripheral
+ * switches that control their power, as specified above.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate memory power state related to overall system state.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Callback or polling may return error if the service contends for a resource
+ * already being used by a power mode transition or an ongoing service in
+ * another domain.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy,
+ *        -2 if a pointer conversion to physical address failed,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_power_off(const uint32_t swtoff[],
+		       const uint32_t memoff[],
+		       upwr_callb     callb);
+
+/**
+ * upwr_pwm_mem_retain()- Configures one or more memory power switches to
+ * retain its contents, having the power array on, while its peripheral logic
+ * is turned off.
+ * @mem: pointer to an array of words that tells which memories to put in a
+ *  retention state. Each word in the array has 1 bit for each memory.
+ *  A bit=1 means the respective memory must be put in retention state,
+ *  bit = 0 means it will stay unchanged (retention, fully on or off).
+ * @callb: pointer to the callback called when configurations are applyed.
+ * NULL if no callback is required.
+ *
+ * The function requests uPower to turn off the memory peripheral and leave
+ * its array on, as specified above.
+ * The request is executed if arguments are within range.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Callback or polling may return error if the service contends for a resource
+ * already being used by a power mode transition or an ongoing service in
+ * another domain.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy,
+ *        -2 if a pointer conversion to physical address failed,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_mem_retain(const uint32_t mem[], upwr_callb callb);
+
+/**
+ * upwr_pwm_chng_switch_mem() - Turns on/off power on one or more PMC switches
+ * and memories, including their array and peripheral logic.
+ * @swt: pointer to a list of PMC switches to be opened/closed.
+ *  The list is structured as an array of struct upwr_switch_board_t
+ *  (see upower_defs.h), each one containing a word for up to 32 switches,
+ *  one per bit. A bit = 1 means switch closed, bit = 0 means switch open.
+ *  struct upwr_switch_board_t also specifies a mask with 1 bit for each
+ *  respective switch: mask bit = 1 means the open/close action is applied,
+ *  mask bit = 0 means the switch stays unchanged.
+ *  The pointer may be set to NULL, in which case no switch will be changed,
+ *  unless a memory that it feeds must be turned on.
+ *  WARNING: swt must not point to the first shared memory address.
+ * @mem: pointer to a list of switches to be turned on/off.
+ *  The list is structured as an array of struct upwr_mem_switches_t
+ *  (see upower_defs.h), each one containing 2 word for up to 32 switches,
+ *  one per bit, one word for the RAM array power switch, other for the
+ *  RAM peripheral logic power switch. A bit = 1 means switch closed,
+ *  bit = 0 means switch open.
+ *  struct upwr_mem_switches_t also specifies a mask with 1 bit for each
+ *  respective switch: mask bit = 1 means the open/close action is applied,
+ *  mask bit = 0 means the switch stays unchanged.
+ *  The pointer may be set to NULL, in which case no memory switch will be
+ *  changed, but notice it may be turned off if the switch that feeds it is
+ *  powered off.
+ *  WARNING: mem must not point to the first shared memory address.
+ * @callb: pointer to the callback called when the configurations are applied.
+ * NULL if no callback is required.
+ *
+ * The function requests uPower to change the PMC switches and/or memory power
+ * as specified above.
+ * The request is executed if arguments are within range, with no protections
+ * regarding the adequate switch combinations and overall system state.
+ *
+ * If a memory is requested to turn on, but the power switch that feeds that
+ * memory is not, the power switch will be turned on anyway, if the swt
+ * array is not provided (that is, if swt is NULL).
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Callback or polling may return error if the service contends for a resource
+ * already being used by a power mode transition or an ongoing service in
+ * another domain.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy.
+ *        -2 if a pointer conversion to physical address failed,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_chng_switch_mem(const struct upwr_switch_board_t  swt[],
+			     const struct upwr_mem_switches_t  mem[],
+			     upwr_callb                        callb);
+
+/**
+ * upwr_pwm_pmode_config() - Configures a given power mode in a given domain.
+ * @domain: identifier of the domain to which the power mode belongs.
+ * Defined by SoC-dependent type soc_domain_t found in upower_soc_defs.h.
+ * @pmode: SoC-dependent power mode identifier defined by type abs_pwr_mode_t
+ * found in upower_soc_defs.h.
+ * @config: pointer to an SoC-dependent struct defining the power mode
+ * configuration, found in upower_soc_defs.h.
+ * @callb: pointer to the callback called when configurations are applied.
+ * NULL if no callback is required.
+ *
+ * The function requests uPower to change the power mode configuration as
+ * specified above. The request is executed if arguments are within range,
+ * and complies with SoC-dependent restrictions on value combinations.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy,
+ *        -2 if the pointer conversion to physical address failed,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_pmode_config(soc_domain_t   domain,
+			  abs_pwr_mode_t pmode,
+			  const void*    config,
+			  upwr_callb     callb);
+
+
+
+/**
+ * upwr_pwm_reg_config() - Configures the uPower internal regulators.
+ * @config: pointer to the struct defining the regulator configuration;
+ * the struct upwr_reg_config_t is defined in the file upower_defs.h.
+ * @callb: pointer to the callback called when configurations are applied.
+ * NULL if no callback is required.
+ *
+ * The function requests uPower to change/define the configurations of the
+ * internal regulators.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * The service may fail with error UPWR_RESP_RESOURCE if a power mode transition
+ * or the same service (called from another domain) is executing simultaneously.
+ * This error should be interpreted as a "try later" response, as the service
+ * will succeed once those concurrent executions are done, and no other is
+ * started.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy,
+ *        -2 if the pointer conversion to physical address failed,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_reg_config(const struct upwr_reg_config_t* config,
+			upwr_callb   callb);
+
+/**
+ * upwr_pwm_chng_dom_bias() - Changes the domain bias.
+ * @bias: pointer to a domain bias configuration struct (see upower_soc_defs.h).
+ * @callb: pointer to the callback called when configurations are applied.
+ * NULL if no callback is required.
+ *
+ * The function requests uPower to change the domain bias configuration as
+ * specified above. The request is executed if arguments are within range,
+ * with no protections regarding the adequate value combinations and
+ * overall system state.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_chng_dom_bias(const struct upwr_dom_bias_cfg_t* bias,
+			   upwr_callb                        callb);
+
+/**
+ * upwr_pwm_chng_mem_bias()- Changes a ROM/RAM power bias.
+ * @domain: identifier of the domain upon which the bias is applied.
+ * Defined by SoC-dependent type soc_domain_t found in upower_soc_defs.h.
+ * @bias: pointer to a memory bias configuration struct (see upower_soc_defs.h).
+ * @callb: pointer to the callback called when configurations are applied.
+ * NULL if no callback is required.
+ *
+ * The function requests uPower to change the memory bias configuration as
+ * specified above. The request is executed if arguments are within range,
+ * with no protections regarding the adequate value combinations and
+ * overall system state.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check the response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_pwm_chng_mem_bias(soc_domain_t                      domain,
+			   const struct upwr_mem_bias_cfg_t* bias,
+			   upwr_callb                        callb);
+
+/**---------------------------------------------------------------
+ * DIAGNOSE SERVICE GROUP
+ */
+
+/**
+ * upwr_dgn_mode() - Sets the diagnostic mode.
+ * @mode:  diagnostic mode, which can be:
+ *  - UPWR_DGN_NONE:   no diagnostic recorded
+ *  - UPWR_DGN_TRACE:  warnings, errors, service, internal activity recorded
+ *  - UPWR_DGN_SRVREQ: warnings, errors, service activity recorded
+ *  - UPWR_DGN_WARN:   warnings and errors recorded
+ *  - UPWR_DGN_ALL:    trace, service, warnings, errors, task state recorded
+ *  - UPWR_DGN_ERROR:  only errors recorded
+ *  - UPWR_DGN_ALL2ERR: record all until an error occurs,
+ *    freeze recording on error
+ *  - UPWR_DGN_ALL2HLT: record all until an error occurs,
+ *    executes an ebreak on error, which halts the core if enabled through
+ *    the debug interface
+ * @callb: pointer to the callback called when mode is changed.
+ * NULL if no callback is required.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok,
+ *        -1 if service group is busy,
+ *        -3 if called in an invalid API state
+ */
+
+int upwr_dgn_mode(upwr_dgn_mode_t mode, const upwr_callb callb);
+
+/**---------------------------------------------------------------
+ * AUXILIARY CALLS
+ */
+
+/**
+ * upwr_rom_version() - informs the ROM firwmware version.
+ * @vmajor: pointer to the variable to get the firmware major version number.
+ * @vminor: pointer to the variable to get the firmware minor version number.
+ * @vfixes: pointer to the variable to get the firmware fixes number.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: SoC id.
+ */
+
+uint32_t upwr_rom_version(uint32_t *vmajor, uint32_t *vminor, uint32_t *vfixes);
+
+/**
+ * upwr_ram_version() - informs the RAM firwmware version.
+ * @vminor: pointer to the variable to get the firmware minor version number.
+ * @vfixes: pointer to the variable to get the firmware fixes number.
+ *
+ * The 3 values returned are 0 if no RAM firmwmare was loaded and initialized.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: firmware major version number.
+ */
+
+uint32_t upwr_ram_version(uint32_t* vminor, uint32_t *vfixes);
+
+/**
+ * upwr_req_status() - tells the status of the service group request, and
+ *                     returns a request return value, if any.
+ * @sg: service group of the request
+ * @sgfptr: pointer to the variable that will hold the function id of
+ * the last request completed; can be NULL, in which case it is not used.
+ * @errptr: pointer to the variable that will hold the error code;
+ * can be NULL, in which case it is not used.
+ * @retptr: pointer to the variable that will hold the value returned
+ * by the last request completed (invalid if the last request completed didn't
+ * return any value); can be NULL, in which case it is not used.
+ * Note that a request may return a value even if service error is returned
+ * (*errptr != UPWR_RESP_OK): that is dependent on the specific service.
+ *
+ * This call can be used in a poll loop of a service request completion in case
+ * a callback was not registered.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: service request status: succeeded, failed, or ongoing (busy)
+ */
+
+/* service request status */
+
+typedef enum {
 	UPWR_REQ_OK,     /* request succeeded */
 	UPWR_REQ_ERR,    /* request failed */
 	UPWR_REQ_BUSY    /* request execution ongoing */
-};
+} upwr_req_status_t;
 
-#define UPWR_SOC_BITS    (7)
-#define UPWR_VMINOR_BITS (4)
-#define UPWR_VFIXES_BITS (4)
-#define UPWR_VMAJOR_BITS  \
-	(32 - UPWR_HEADER_BITS - UPWR_SOC_BITS - UPWR_VMINOR_BITS - UPWR_VFIXES_BITS)
-union upwr_init_msg {
-	struct upwr_resp_hdr hdr;
-	struct {
-		u32 rsv:UPWR_RESP_HDR_BITS;
-		u32 soc:UPWR_SOC_BITS;        /* SoC identification */
-		u32 vmajor:UPWR_VMAJOR_BITS;  /* firmware major version */
-		u32 vminor:UPWR_VMINOR_BITS;  /* firmware minor version */
-		u32 vfixes:UPWR_VFIXES_BITS;  /* firmware fixes version */
-	} args;
-};
+upwr_req_status_t upwr_req_status(upwr_sg_t     sg,
+				  uint32_t*     sgfptr,
+				  upwr_resp_t*  errptr,
+				  int*          retptr);
 
-#define UPWR_RAM_VMINOR_BITS (7)
-#define UPWR_RAM_VFIXES_BITS (6)
-#define UPWR_RAM_VMAJOR_BITS (32 - UPWR_HEADER_BITS - UPWR_RAM_VFIXES_BITS - UPWR_RAM_VMINOR_BITS)
-
-union upwr_ready_msg {
-	struct upwr_resp_hdr hdr;
-	struct {
-		u32 rsv:UPWR_RESP_HDR_BITS;
-		u32 vmajor:UPWR_RAM_VMAJOR_BITS; /* RAM fw major version */
-		u32 vminor:UPWR_RAM_VMINOR_BITS; /* RAM fw minor version */
-		u32 vfixes:UPWR_RAM_VFIXES_BITS; /* RAM fw fixes version */
-	} args;
-};
+/**
+ * upwr_poll_req_status() - polls the status of the service group request, and
+ *                          returns a request return value, if any.
+ * @sg: service group of the request
+ * @sgfptr: pointer to the variable that will hold the function id of
+ * the last request completed; can be NULL, in which case it is not used.
+ * @errptr: pointer to the variable that will hold the error code;
+ * can be NULL, in which case it is not used.
+ * @retptr: pointer to the variable that will hold the value returned
+ * by the last request completed (invalid if the last request completed didn't
+ * return any value); can be NULL, in which case it is not used.
+ * Note that a request may return a value even if service error is returned
+ * (*errptr != UPWR_RESP_OK): that is dependent on the specific service.
+ * @attempts: maximum number of polling attempts; if attempts > 0 and is
+ * reached with no service response received, upwr_poll_req_status returns
+ * UPWR_REQ_BUSY and variables pointed by sgfptr, retptr and errptr are not
+ * updated; if attempts = 0, upwr_poll_req_status waits "forever".
+ *
+ * This call can be used to poll a service request completion in case a
+ * callback was not registered.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: service request status: succeeded, failed, or ongoing (busy)
+ */
 
-struct upwr_reg_access_t {
-	u32 addr;
-	u32 data;
-	u32 mask; /* mask=0 commands read */
-};
+upwr_req_status_t upwr_poll_req_status(upwr_sg_t     sg,
+				       uint32_t*     sgfptr,
+				       upwr_resp_t*  errptr,
+				       int*          retptr,
+				       uint32_t      attempts);
 
-union upwr_xcp_union {
-	struct upwr_reg_access_t reg_access;
-};
+/**
+ * upwr_alarm_code() - returns the alarm code of the last alarm occurrence.
+ *
+ * The value returned is not meaningful if no alarm was issued by uPower.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: alarm code, as defined by the type upwr_alarm_t in upwr_soc_defines.h
+ */
 
-enum {			/* Power Management Functions */
-	UPWR_PWM_REGCFG,	/* 0 = regulator config: upwr_pwm_reg_config */
-	UPWR_PWM_DEVMODE = UPWR_PWM_REGCFG, /* deprecated, for old compile */
-	UPWR_PWM_VOLT,		/* 1 = voltage change: upwr_pwm_chng_reg_voltage */
-	UPWR_PWM_SWITCH,	/* 2 = switch control: upwr_pwm_chng_switch_mem */
-	UPWR_PWM_PWR_ON,	/* 3 = switch/RAM/ROM power on: upwr_pwm_power_on  */
-	UPWR_PWM_PWR_OFF,	/* 4 = switch/RAM/ROM power off: upwr_pwm_power_off */
-	UPWR_PWM_RETAIN,	/* 5 = retain memory array: upwr_pwm_mem_retain */
-	UPWR_PWM_DOM_BIAS,	/* 6 = Domain bias control: upwr_pwm_chng_dom_bias */
-	UPWR_PWM_MEM_BIAS,	/* 7 = Memory bias control: upwr_pwm_chng_mem_bias */
-	UPWR_PWM_PMICCFG,	/* 8 = PMIC configuration:  upwr_pwm_pmic_config */
-	UPWR_PWM_PMICMOD = UPWR_PWM_PMICCFG, /* deprecated, for old compile */
-	UPWR_PWM_PES,		/* 9 = Power Event Sequencer */
-	UPWR_PWM_CONFIG,	/* 10= apply power mode defined configuration */
-	UPWR_PWM_CFGPTR,	/* 11= configuration pointer */
-	UPWR_PWM_DOM_PWRON,	/* 12 = domain power on: upwr_pwm_dom_power_on */
-	UPWR_PWM_BOOT,		/* 13 = boot start: upwr_pwm_boot_start */
-	UPWR_PWM_FREQ,		/* 14 = domain frequency setup */
-	UPWR_PWM_PARAM,		/* 15 = power management parameters */
-	UPWR_PWM_F_COUNT
-};
+upwr_alarm_t upwr_alarm_code(void);
 
-#ifndef UPWR_PMC_SWT_WORDS
-#define UPWR_PMC_SWT_WORDS		(1)
-#endif
+/**---------------------------------------------------------------
+ * TRANSMIT/RECEIVE PRIMITIVES
+ * ---------------------------------------------------------------
+ */
 
-#ifndef UPWR_PMC_MEM_WORDS
-#define UPWR_PMC_MEM_WORDS		(2)
-#endif
+typedef void (*UPWR_TX_CALLB_FUNC_T)(void);
+typedef void (*UPWR_RX_CALLB_FUNC_T)(void);
 
-#define UPWR_API_ASSERT(c) do { } while (0)
+/**
+ * upwr_tx() - queues a message for transmission.
+ * @msg : pointer to the message sent.
+ * @size: message size in 32-bit words
+ * @callback: pointer to a function to be called when transmission done;
+ *            can be NULL, in which case no callback is done.
+ *
+ * This is an auxiliary function used by the rest of the API calls.
+ * It is normally not called by the driver code, unless maybe for test purposes.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: number of vacant positions left in the trasmission queue, or
+ *         -1 if the queue was already full when upwr_tx was called, or
+ *         -2 if any argument is invalid (like size off-range)
+ */
 
-struct upwr_code_vers {
-	u32 soc_id;
-	u32 vmajor;
-	u32 vminor;
-	u32 vfixes;
-};
+int upwr_tx(const uint32_t*         msg,
+            unsigned int            size,
+            UPWR_TX_CALLB_FUNC_T    callback);
 
-#define UPWR_MU_MSG_SIZE	(2)
+/**
+ * upwr_rx() - unqueues a received message from the reception queue.
+ * @msg: pointer to the message destination buffer.
+ * @size: pointer to variable to hold message size in 32-bit words.
+ *
+ * This is an auxiliary function used by the rest of the API calls.
+ * It is normally not called by the driver code, unless maybe for test purposes.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: number of messages remaining in the reception queue, or
+ *         -1 if the queue was already empty when upwr_rx was called, or
+ *         -2 if any argument is invalid (like mu off-range)
+ */
 
-#define UPWR_MU_TSR_EMPTY	((u32)((1 << UPWR_MU_MSG_SIZE) - 1))
+int upwr_rx(char *msg, unsigned int *size);
 
-#ifndef UPWR_DRAM_SHARED_BASE_ADDR
-#define UPWR_DRAM_SHARED_BASE_ADDR	(0x28330000)
-#endif
+/**
+ * upwr_rx_callback() - sets up a callback for a message receiving event.
+ * @callback: pointer to a function to be called when a message arrives;
+ *            can be NULL, in which case no callback is done.
+ *
+ * This is an auxiliary function used by the rest of the API calls.
+ * It is normally not called by the driver code, unless maybe for test purposes.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok; -2 if any argument is invalid (mu off-range).
+ */
 
-#ifndef UPWR_DRAM_SHARED_SIZE
-#define UPWR_DRAM_SHARED_SIZE		(2048)
-#endif
+int upwr_rx_callback(UPWR_RX_CALLB_FUNC_T    callback);
 
-#define UPWR_DRAM_SHARED_ENDPLUS	(UPWR_DRAM_SHARED_BASE_ADDR + UPWR_DRAM_SHARED_SIZE)
+/**
+ * msg_copy() - copies a message.
+ * @dest: pointer to the destination message.
+ * @src : pointer to the source message.
+ * @size: message size in words.
+ *
+ * This is an auxiliary function used by the rest of the API calls.
+ * It is normally not called by the driver code, unless maybe for test purposes.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: none (void)
+ */
 
-#ifndef UPWR_API_BUFFER_BASE
-#define UPWR_API_BUFFER_BASE		(0x28330600)
-#endif
+void msg_copy(char* dest, char* src, unsigned int size);
+
+/**
+  */
 
-#ifndef UPWR_API_BUFFER_ENDPLUS
-#define UPWR_API_BUFFER_ENDPLUS		(UPWR_DRAM_SHARED_ENDPLUS - 64)
+#ifdef UPWR_VERIFICATION
+#include "upower_api_verif.h"
 #endif
 
-typedef void (*upwr_rdy_callb)(u32 vmajor, u32 vminor, u32 vfixes);
-typedef void (*upwr_callb)(enum upwr_sg sg, u32 func, enum upwr_resp errcode, int ret);
-int upwr_init(enum soc_domain domain, struct mu_type *muptr);
-int upwr_start(u32 launchopt, const upwr_rdy_callb rdycallb);
-u32 upwr_rom_version(u32 *vmajor, u32 *vminor, u32 *vfixes);
-typedef void (*UPWR_RX_CALLB_FUNC_T)(void);
+#ifdef  __cplusplus
+#ifndef UPWR_NAMESPACE /* extern "C" 'cancels' the effect of namespace */
+} /* extern "C" */
+#endif
+#endif
 
-int upwr_xcp_set_ddr_retention(enum soc_domain domain, u32 enable, const upwr_callb callb);
-int upwr_pwm_power_on(const u32 swton[], const u32 memon[], upwr_callb  callb);
-int upwr_xcp_i2c_access(u16 addr, s8 data_size, u8 subaddr_size, u32 subaddr,
-			u32 wdata, const upwr_callb callb);
-enum upwr_req_status upwr_poll_req_status(enum upwr_sg sg, u32 *sgfptr,
-					  enum upwr_resp *errptr, int *retptr,
-					  u32 attempts);
-void upwr_txrx_isr(void);
+#endif /* _UPWR_API_H_ */
diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_api_verif.h b/arch/arm/mach-imx/imx8ulp/upower/upower_api_verif.h
new file mode 100644
index 00000000000..8457e7f2bb5
--- /dev/null
+++ b/arch/arm/mach-imx/imx8ulp/upower/upower_api_verif.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* +FHDR------------------------------------------------------------------------
+ * Copyright 2019-2021 NXP
+ * -----------------------------------------------------------------------------
+ * FILE NAME      : upower_api_verif.h
+ * DEPARTMENT     : BSTC - Campinas, Brazil
+ * AUTHOR         : Celso Brites
+ * AUTHOR'S EMAIL : celso.brites@nxp.com
+ * -----------------------------------------------------------------------------
+ * RELEASE HISTORY
+ * VERSION DATE        AUTHOR                  DESCRIPTION
+ *
+ * $Log: upower_api_verif.h.rca $
+ *
+ *  Revision: 1.4 Tue Sep 15 17:52:21 2020 nxa11511
+ *  Verification-only service upwr_pwm_reg_access moved to Exception service group and was renamed upwr_xcp_reg_access.
+ *
+ *  Revision: 1.3 Wed Jun 17 17:01:08 2020 nxa11511
+ *  Comment fix.
+ *
+ *  Revision: 1.2 Mon Jun  8 06:46:13 2020 nxa11511
+ *  Removes verification-only typedefs, moved to upower_soc_defs.h
+ *
+ * -----------------------------------------------------------------------------
+ * KEYWORDS: micro-power uPower driver API verification
+ * -----------------------------------------------------------------------------
+ * PURPOSE: uPower driver verification-only API:
+ *          calls available only for veriifcation, but not production
+ * -----------------------------------------------------------------------------
+ * PARAMETERS:
+ * PARAM NAME RANGE:DESCRIPTION:       DEFAULTS:                           UNITS
+ * -----------------------------------------------------------------------------
+ * REUSE ISSUES: no reuse issues
+ * -FHDR------------------------------------------------------------------------
+ */
+
+#ifndef _UPWR_API_VERIF_H_
+#define _UPWR_API_VERIF_H_
+
+/* definitions for the verification-only service upwr_pwm_read_write */
+
+/*
+ * upwr_xcp_reg_access()- accesses (read or write) a register inside uPower.
+ * @access: pointer to the access specification struct (see upower_soc_defs.h).
+ *          access->mask determines the bits of access->data written (if any)
+ *          at access->addr; if access->mask = 0, the service performs a read.
+ * @callb: pointer to the callback called when configurations are applied.
+ * NULL if no callback is required.
+ *
+ * A callback can be optionally registered, and will be called upon the arrival
+ * of the request response from the uPower firmware, telling if it succeeded
+ * or not.
+ *
+ * A callback may not be registered (NULL pointer), in which case polling has
+ * to be used to check a service group response, by calling upwr_req_status or
+ * upwr_poll_req_status, using UPWR_SG_PWRMGMT as the service group argument.
+ *
+ * This service has as return value the final register value (read value on a
+ * read or the updated value on a write), which is obtained from the callback
+ * argument ret or *retptr in case of polling using the functions
+ * upwr_req_status or upwr_poll_req_status.
+ *
+ * Context: no sleep, no locks taken/released.
+ * Return: 0 if ok, -1 if service group is busy,
+ *        -2 if the pointer conversion to physical address failed,
+ *        -3 if called in an invalid API state.
+ * Note that this is not the error response from the request itself:
+ * it only tells if the request was successfully sent to the uPower.
+ */
+
+int upwr_xcp_reg_access(const struct upwr_reg_access_t* access,
+			upwr_callb                      callb);
+#endif
diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_defs.h b/arch/arm/mach-imx/imx8ulp/upower/upower_defs.h
new file mode 100644
index 00000000000..379a1c2521b
--- /dev/null
+++ b/arch/arm/mach-imx/imx8ulp/upower/upower_defs.h
@@ -0,0 +1,883 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* +FHDR------------------------------------------------------------------------
+ * Copyright 2019-2021 NXP
+ * -----------------------------------------------------------------------------
+ * FILE NAME      : upower_defs.h
+ * DEPARTMENT     : BSTC - Campinas, Brazil
+ * AUTHOR         : Celso Brites
+ * AUTHOR'S EMAIL : celso.brites@nxp.com
+ * -----------------------------------------------------------------------------
+ * RELEASE HISTORY
+ * VERSION DATE        AUTHOR                  DESCRIPTION
+ *
+ * $Log: upower_defs.h.rca $
+ *
+ *  Revision: 1.66 Tue Apr 27 12:48:48 2021 nxa11511
+ *  Adds new pwm function number UPWR_PWM_REGCFG for new service upwr_pwm_reg_config
+ *  (same value as UPWR_PWM_DEVMOD, deprecated).
+ *  Adds struct upwr_reg_config_t, only a stub for now.
+ *  Replaces typedef upwr_pwm_devmode_msg with upwr_pwm_regcfg_msg.
+ *  upwr_pwm_msg.devmode replaced with upwr_pwm_msg.regcfg
+ *
+ *  Revision: 1.60 Fri Oct 23 11:49:56 2020 nxa11511
+ *  Deleted the GPL license statements, leaving only BSD, as it is compatible with Linux and good for closed ROM/firmware code.
+ *
+ *  Revision: 1.59 Wed Sep 30 15:57:35 2020 nxa11511
+ *  Now UPWR_DGN_MAX = UPWR_DGN_ALL.
+ *  Redefines upwr_dgn_log_t according to dgn_lib.S;
+ *  Merge from branch dgn_lib.
+ *
+ *  Revision: 1.58.1.1 Tue Sep 29 10:07:12 2020 nxa11511
+ *  Adds UPWR_DGN_ALL to upwr_dgn_mode_t, which is now also UPWR_DGN_MAX.
+ *  In upwr_dgn_log_t, DGN_LOG_EVENTNEW added DGN_LOG_SPARE deleted.
+ *
+ *  Revision: 1.49 Mon Jun  8 06:46:30 2020 nxa11511
+ *  *** empty comment string ***
+ *
+ *  Revision: 1.44 Tue Apr  7 13:34:01 2020 nxf42682
+ *  Put TYPES_LOCAL_H - fixed serious compilation error of version 1.42 and 1.43
+ *
+ *  Revision: 1.43 Tue Mar 31 12:50:46 2020 nxf42682
+ *  Merged version 1.42 with 1.41.1.1
+ *
+ *  Revision: 1.42 Tue Mar 31 08:06:59 2020 nxa11511
+ *  Fixes a compiling error.
+ *
+ *  Revision: 1.41 Mon Mar 30 23:07:26 2020 nxa10721
+ *  Added support for AVD bias
+ *
+ *  Revision: 1.40 Mon Mar 30 14:29:44 2020 nxa11511
+ *  Updates to API spec 20200404:
+ *  API functions upwr_power_on and upwr_boot_start deleted.
+ *  API functions upwr_xcp_power_on and upwr_xcp_boot_start moved to the Power Management service group;
+ *  renamed to upwr_pwm_dom_power_on and upwr_pwm_boot_start
+ *
+ *  Revision: 1.39 Fri Mar 27 17:17:34 2020 nxa11511
+ *  Adds typedef upwr_start_msg.
+ *  (sets new typedef upwr_xcp_start_msg;
+ *  Adds typedef upwr_resp_msg upwr_shutdown_msg;
+ *
+ *  Revision: 1.35 Tue Mar 10 06:24:09 2020 nxa11511
+ *  Fixes identations to comply with the Linux kernel coding guidelines.
+ *
+ *  Revision: 1.34 Thu Mar  5 22:08:03 2020 nxa10721
+ *  Using the RTD monitor config also for APD
+ *
+ *  Revision: 1.33 Mon Mar  2 12:16:14 2020 nxa11511
+ *  Changes typedef upwr_start_msg to simple 1-word message.
+ *
+ *  Revision: 1.29 Mon Feb 10 10:34:29 2020 nxa10721
+ *  Temporarily turns RTD config pointers as uint32_t for A35 compilation in SoC
+ *
+ *  Revision: 1.28 Sun Feb  9 16:10:01 2020 nxa10721
+ *  Added abs_pwr_mode_t, solving TKT0532383
+ *  Define RTD swt and mem configs as a pointer or 32-bit word, according to CPU
+ *
+ *  Revision: 1.27 Thu Jan 30 07:09:03 2020 nxa11511
+ *  typedef upwr_rom_vers_t members major and minor renamed to vmajor and vminor to avoid clashing with a Linux include macro.
+ *
+ *  Revision: 1.23 Mon Nov 25 10:38:33 2019 nxa10721
+ *  Typecastings to reduce warns
+ *
+ *  Revision: 1.21 Wed Nov 13 21:59:44 2019 nxa10721
+ *  Added toutines to handle swt offset
+ *
+ *  Revision: 1.20 Tue Nov  5 12:46:45 2019 nxa10721
+ *  Added APD power mode config structs, using offsets instead of pointers
+ *
+ *  Revision: 1.19 Thu Oct 24 11:33:48 2019 nxa10721
+ *  Remove some g++ warns on strings
+ *
+ *  Revision: 1.18 Fri Oct 18 06:42:40 2019 nxa10721
+ *  Added APD and core power modes
+ *
+ *  Revision: 1.17 Wed Oct  9 11:35:24 2019 nxa13158
+ *  replaced powersys low power mode config by struct config
+ *
+ *  Revision: 1.16 Tue Sep 24 12:16:30 2019 nxa13158
+ *  updated upwr_pmc_mon_rtd_cfg_t struct (removed unecessary union)
+ *
+ *  Revision: 1.15 Mon Aug 26 14:24:26 2019 nxa13158
+ *  reorganized power modes enum to make easy to reuse in tb
+ *
+ *  Revision: 1.14 Fri Aug 23 17:54:11 2019 nxa11511
+ *  Renames UPWR_RESP_NOT_IMPL to UPWR_RESP_UNINSTALLD.
+ *
+ *  Revision: 1.13 Wed Aug 21 12:59:15 2019 nxa13158
+ *  renamed RTD mode to active DMA, moved pmc_bias_mode_t to
+ *  pmc_api. Updated mem bias struct config
+ *
+ *  Revision: 1.12 Wed Aug 21 07:01:47 2019 nxa11511
+ *  Several changes in message formats.
+ *
+ *  Revision: 1.9 Thu Aug 15 17:10:04 2019 nxa13158
+ *  removed POR from power modes transitions. Not needed anymore
+ *
+ *  Revision: 1.8 Thu Aug 15 11:50:08 2019 nxa11511
+ *  UPWR_SG_PMODE renamed to UPWR_SG_PMGMT.
+ *
+ *  Revision: 1.7 Wed Aug 14 10:16:48 2019 nxa13158
+ *  Fixed upwr_pmc_bias_cfg_t struct definition
+ *
+ *  Revision: 1.6 Tue Aug 13 17:52:07 2019 nxa11511
+ *  Adds Exception function enum.
+ *  Fixes union upwr_pmc_mon_rtd_cfg_t.
+ *
+ *  Revision: 1.5 Tue Aug 13 15:26:40 2019 nxa13158
+ *  added Power Modes configuration structs.
+ *
+ *  Revision: 1.4 Mon Aug 12 18:18:40 2019 nxa11511
+ *  Message structs/unions turned into typedefs.
+ *  Adds message formats for the new initialization procedure with the boot start step.
+ *
+ *  Revision: 1.3 Sat Aug 10 09:06:21 2019 nxa11511
+ *  Adds extern "C" if __cplusplus is #defined and UPWR_NAMESPACE is #undefined.
+ *
+ *  Revision: 1.1 Thu Aug  1 17:14:33 2019 nxa11511
+ *  uPower driver API #defines and typedefs shared with the firmware
+ *
+ * -----------------------------------------------------------------------------
+ * KEYWORDS: micro-power uPower driver API
+ * -----------------------------------------------------------------------------
+ * PURPOSE: uPower driver API #defines and typedefs shared with the firmware
+ * -----------------------------------------------------------------------------
+ * PARAMETERS:
+ * PARAM NAME RANGE:DESCRIPTION:       DEFAULTS:                           UNITS
+ * -----------------------------------------------------------------------------
+ * REUSE ISSUES: no reuse issues
+ * -FHDR--------------------------------------------------------------------- */
+
+#ifndef _UPWR_DEFS_H
+#define _UPWR_DEFS_H
+
+#ifndef TYPES_LOCAL_H
+
+#include <stdint.h> /* this include breaks the SoC compile - TBD why? */
+
+#endif /* not production code */
+
+#ifndef UPWR_PMC_SWT_WORDS
+#define UPWR_PMC_SWT_WORDS              (1U)
+#endif
+
+#ifndef UPWR_PMC_MEM_WORDS
+#define UPWR_PMC_MEM_WORDS              (2U)
+#endif
+
+/* ****************************************************************************
+ * DOWNSTREAM MESSAGES - COMMANDS/FUNCTIONS
+ * ****************************************************************************
+ */
+
+#define UPWR_SRVGROUP_BITS  (4U)
+#define UPWR_FUNCTION_BITS  (4U)
+#define UPWR_PWDOMAIN_BITS  (4U)
+#define UPWR_HEADER_BITS   \
+                      (UPWR_SRVGROUP_BITS + UPWR_FUNCTION_BITS + UPWR_PWDOMAIN_BITS)
+#define UPWR_ARG_BITS      (32U - UPWR_HEADER_BITS)
+#if   ((UPWR_ARG_BITS & 1U) > 0U)
+#error "UPWR_ARG_BITS must be an even number"
+#endif
+#define UPWR_ARG64_BITS          (64U - UPWR_HEADER_BITS)
+#define UPWR_HALF_ARG_BITS       (UPWR_ARG_BITS >> 1U)
+#define UPWR_DUAL_OFFSET_BITS    ((UPWR_ARG_BITS + 32U) >> 1U)
+
+#ifdef  __cplusplus
+#ifndef UPWR_NAMESPACE /* extern "C" 'cancels' the effect of namespace */
+extern "C" {
+#endif
+#endif
+
+/* message header: header fields common to all downstream messages.
+ */
+
+struct upwr_msg_hdr {
+	uint32_t domain   :UPWR_PWDOMAIN_BITS;           /* power domain */
+	uint32_t srvgrp   :UPWR_SRVGROUP_BITS;          /* service group */
+	uint32_t function :UPWR_FUNCTION_BITS;             /* function */
+	uint32_t arg      :UPWR_ARG_BITS;     /* function-specific argument */
+};
+
+/* generic 1-word downstream message format */
+
+typedef union {
+	struct upwr_msg_hdr  hdr;
+	uint32_t             word;  /* message first word */
+} upwr_down_1w_msg;
+
+/* generic 2-word downstream message format */
+
+typedef struct {
+	struct upwr_msg_hdr  hdr;
+	uint32_t             word2;  /* message second word */
+} upwr_down_2w_msg;
+
+/* message format for functions that receive a pointer/offset */
+
+typedef struct {
+	struct upwr_msg_hdr  hdr;
+	uint32_t             ptr; /* config struct offset */
+} upwr_pointer_msg;
+
+/* message format for functions that receive 2 pointers/offsets */
+
+typedef union {
+	struct upwr_msg_hdr  hdr;
+	struct {
+		uint64_t :UPWR_HEADER_BITS;
+		uint64_t ptr0:UPWR_DUAL_OFFSET_BITS;
+		uint64_t ptr1:UPWR_DUAL_OFFSET_BITS;
+	} ptrs;
+} upwr_2pointer_msg;
+
+typedef enum { /* Service Groups in priority order, high to low */
+	UPWR_SG_EXCEPT,   /* 0 = exception           */
+	UPWR_SG_PWRMGMT , /* 1 = power management    */
+	UPWR_SG_DELAYM,   /* 2 = delay   measurement */
+	UPWR_SG_VOLTM ,   /* 3 = voltage measurement */
+	UPWR_SG_CURRM,    /* 4 = current measurement */
+	UPWR_SG_TEMPM,    /* 5 = temperature measurement */
+	UPWR_SG_DIAG,     /* 6 = diagnostic  */
+	UPWR_SG_COUNT
+} upwr_sg_t;
+
+/* *************************************************************************
+ * Initialization - downstream
+ ***************************************************************************/
+
+typedef upwr_down_1w_msg upwr_start_msg; /* start command message */
+
+typedef upwr_down_1w_msg upwr_power_on_msg;   /* power on   command message */
+typedef upwr_down_1w_msg upwr_boot_start_msg; /* boot start command message */
+
+typedef union {
+	struct upwr_msg_hdr hdr;
+	upwr_power_on_msg   power_on;
+	upwr_boot_start_msg boot_start;
+	upwr_start_msg      start;
+} upwr_startup_down_msg;
+
+/* *************************************************************************
+ * Service Group EXCEPTION - downstream
+ ***************************************************************************/
+
+typedef enum {             /* Exception Functions */
+	UPWR_XCP_INIT,     /*  0 = init msg (not a service request itself) */
+	UPWR_XCP_PING = UPWR_XCP_INIT,
+			   /*  0 = also ping request, since its response is
+				   an init msg */
+	UPWR_XCP_START,    /*  1 = service start: upwr_start
+                            *      (not a service request itself) */
+	UPWR_XCP_SHUTDOWN, /*  2 = service shutdown: upwr_xcp_shutdown */
+	UPWR_XCP_CONFIG,   /*  3 = uPower configuration: upwr_xcp_config */
+	UPWR_XCP_SW_ALARM, /*  4 = uPower software alarm: upwr_xcp_sw_alarm */
+	UPWR_XCP_I2C,      /*  5 = I2C access: upwr_xcp_i2c_access */
+	UPWR_XCP_SPARE_6,  /*  6 = spare */
+	UPWR_XCP_SET_DDR_RETN,  /*  7 = set/clear ddr retention */
+	UPWR_XCP_SET_RTD_APD_LLWU,  /*  8 = set/clear rtd/apd llwu */
+	UPWR_XCP_SPARE_8 = UPWR_XCP_SET_RTD_APD_LLWU,  /*  8 = spare */
+    UPWR_XCP_SET_RTD_USE_DDR,      /* 9 = M33 core set it is using DDR or not */
+	UPWR_XCP_SPARE_9 = UPWR_XCP_SET_RTD_USE_DDR,  /*  9 = spare */
+	UPWR_XCP_SPARE_10, /* 10 = spare */
+	UPWR_XCP_SPARE_11, /* 11 = spare */
+	UPWR_XCP_SPARE_12, /* 12 = spare */
+	UPWR_XCP_SPARE_13, /* 13 = spare */
+	UPWR_XCP_SPARE_14, /* 14 = spare */
+	UPWR_XCP_SPARE_15, /* 15 = spare */
+	UPWR_XCP_F_COUNT
+} upwr_xcp_f_t;
+
+typedef upwr_down_1w_msg    upwr_xcp_ping_msg;
+typedef upwr_down_1w_msg    upwr_xcp_shutdown_msg;
+typedef upwr_power_on_msg   upwr_xcp_power_on_msg;
+typedef upwr_boot_start_msg upwr_xcp_boot_start_msg;
+typedef upwr_start_msg      upwr_xcp_start_msg;
+typedef upwr_down_2w_msg    upwr_xcp_config_msg;
+typedef upwr_down_1w_msg    upwr_xcp_swalarm_msg;
+typedef upwr_down_1w_msg    upwr_xcp_ddr_retn_msg;
+typedef upwr_down_1w_msg    upwr_xcp_rtd_use_ddr_msg;
+typedef upwr_down_1w_msg    upwr_xcp_rtd_apd_llwu_msg;
+typedef upwr_pointer_msg    upwr_xcp_i2c_msg;
+
+typedef struct { /* structure pointed by message upwr_xcp_i2c_msg */
+	uint16_t         addr;
+	int8_t           data_size;
+	uint8_t          subaddr_size;
+	uint32_t         subaddr;
+	uint32_t         data;
+} upwr_i2c_access;
+
+/* Exception all messages */
+
+typedef union {
+    struct upwr_msg_hdr       hdr;       /* message header */
+	upwr_xcp_ping_msg         ping;      /* ping */
+    upwr_xcp_start_msg        start;     /* service start */
+	upwr_xcp_shutdown_msg     shutdown;  /* shutdown */
+	upwr_xcp_boot_start_msg   bootstart; /* boot start */
+	upwr_xcp_config_msg       config;    /* uPower configuration */
+	upwr_xcp_swalarm_msg      swalarm;   /* software alarm */
+	upwr_xcp_i2c_msg          i2c;       /* I2C access */
+	upwr_xcp_ddr_retn_msg     set_ddr_retn;       /* set ddr retention msg */
+	upwr_xcp_rtd_use_ddr_msg     set_rtd_use_ddr;       /* set rtd is using ddr msg */
+	upwr_xcp_rtd_apd_llwu_msg     set_llwu;       /* set rtd/apd llwu msg */
+} upwr_xcp_msg;
+
+typedef struct { /* structure pointed by message upwr_volt_dva_req_id_msg */
+	uint32_t         id_word0;
+	uint32_t         id_word1;
+	uint32_t         mode;
+} upwr_dva_id_struct;
+
+/**
+ * PMIC voltage accuracy is 12.5 mV, 12500 uV
+ */
+#define PMIC_VOLTAGE_MIN_STEP 12500U
+
+/* *************************************************************************
+ * Service Group POWER MANAGEMENT - downstream
+ ***************************************************************************/
+
+typedef enum {            /* Power Management Functions */
+	UPWR_PWM_REGCFG,  /* 0 = regulator config: upwr_pwm_reg_config */
+	UPWR_PWM_DEVMODE = UPWR_PWM_REGCFG, /* deprecated, for old compile */
+	UPWR_PWM_VOLT   , /* 1 = voltage change: upwr_pwm_chng_reg_voltage */
+	UPWR_PWM_SWITCH , /* 2 = switch control: upwr_pwm_chng_switch_mem */
+	UPWR_PWM_PWR_ON,  /* 3 = switch/RAM/ROM power on: upwr_pwm_power_on  */
+	UPWR_PWM_PWR_OFF, /* 4 = switch/RAM/ROM power off: upwr_pwm_power_off */
+	UPWR_PWM_RETAIN,  /* 5 = retain memory array: upwr_pwm_mem_retain */
+	UPWR_PWM_DOM_BIAS,/* 6 = Domain bias control: upwr_pwm_chng_dom_bias */
+	UPWR_PWM_MEM_BIAS,/* 7 = Memory bias control: upwr_pwm_chng_mem_bias */
+	UPWR_PWM_PMICCFG, /* 8 = PMIC configuration:  upwr_pwm_pmic_config */
+	UPWR_PWM_PMICMOD = UPWR_PWM_PMICCFG, /* deprecated, for old compile */
+	UPWR_PWM_PES,      /* 9 so far, no use */
+	UPWR_PWM_CONFIG , /* 10= apply power mode defined configuration */
+	UPWR_PWM_CFGPTR,  /* 11= configuration pointer */
+	UPWR_PWM_DOM_PWRON,/* 12 = domain power on: upwr_pwm_dom_power_on */
+	UPWR_PWM_BOOT,     /* 13 = boot start: upwr_pwm_boot_start */
+    UPWR_PWM_FREQ,     /* 14 = domain frequency setup */
+	UPWR_PWM_PARAM,    /* 15 = power management parameters */
+	UPWR_PWM_F_COUNT
+} upwr_pwm_f_t;
+
+#define MAX_PMETER_SSEL 7U
+
+typedef enum {            /* Voltage Management Functions */
+	UPWR_VTM_CHNG_PMIC_RAIL_VOLT,  /* 0 = change pmic rail voltage */
+	UPWR_VTM_GET_PMIC_RAIL_VOLT, /* 1 = get pmic rail voltage */
+	UPWR_VTM_PMIC_CONFIG, /* 2 = configure PMIC IC */
+    UPWR_VTM_DVA_DUMP_INFO, /* 3 = dump dva information */
+    UPWR_VTM_DVA_REQ_ID, /* 4 = dva request ID array */
+    UPWR_VTM_DVA_REQ_DOMAIN, /* 5 = dva request domain */
+    UPWR_VTM_DVA_REQ_SOC, /* 6 = dva request the whole SOC */
+    UPWR_VTM_PMETER_MEAS, /* 7 = pmeter measure */
+    UPWR_VTM_VMETER_MEAS, /* 8 = vmeter measure */
+    UPWR_VTM_PMIC_COLD_RESET, /* 9 = pmic cold reset */
+    UPWR_VTM_SET_DVFS_PMIC_RAIL,     /* 10 = set which domain use which pmic rail, for DVFS use */
+    UPWR_VTM_SET_PMIC_MODE,        /* 11 = set pmic mode */
+    UPWR_VTM_F_COUNT
+} upwr_volt_f_t;
+
+#define VMETER_SEL_RTD 0U
+#define VMETER_SEL_LDO 1U
+#define VMETER_SEL_APD 2U
+#define VMETER_SEL_AVD 3U
+#define VMETER_SEL_MAX 3U
+
+/**
+ * The total TSEL count is 256
+ */
+#define MAX_TEMP_TSEL 256U
+
+/**
+ * Support 3 temperature sensor, sensor 0, 1, 2
+ */
+#define MAX_TEMP_SENSOR 2U
+
+typedef enum {          /* Temperature Management Functions */
+    UPWR_TEMP_GET_CUR_TEMP,  /* 0 = get current temperature */
+    UPWR_TEMP_F_COUNT
+} upwr_temp_f_t;
+
+typedef enum {          /* Delay Meter Management Functions */
+    UPWR_DMETER_GET_DELAY_MARGIN, /* 0 = get delay margin */
+    UPWR_DMETER_SET_DELAY_MARGIN, /* 1 = set delay margin */
+    UPWR_PMON_REQ, /* 2 = process monitor service */
+    UPWR_DMETER_F_COUNT
+} upwr_dmeter_f_t;
+
+typedef upwr_down_1w_msg    upwr_volt_pmeter_meas_msg;
+
+typedef upwr_down_1w_msg    upwr_volt_pmic_set_mode_msg;
+
+typedef upwr_down_1w_msg    upwr_volt_vmeter_meas_msg;
+
+struct upwr_reg_config_t {
+	uint32_t reg;   // TODO: real config
+};
+
+struct upwr_switch_board_t { /* set of 32 switches */
+	uint32_t on;   /* Switch on state,   1 bit per instance */
+	uint32_t mask; /* actuation mask, 1 bit per instance */
+                       /* (bit = 1 applies on bit) */
+};
+
+struct upwr_mem_switches_t { /* set of 32 RAM/ROM switches */
+	uint32_t array;   /* RAM/ROM array state,      1 bit per instance */
+	uint32_t perif;   /* RAM/ROM peripheral state, 1 bit per instance */
+	uint32_t mask;    /* actuation mask,       1 bit per instance */
+                          /* (bit = 1 applies on bit) */
+};
+
+typedef upwr_down_1w_msg upwr_pwm_dom_pwron_msg;  /* domain power on message */
+typedef upwr_down_1w_msg upwr_pwm_boot_start_msg; /* boot start      message */
+
+
+/* functions with complex arguments use the pointer message formats: */
+
+typedef upwr_pointer_msg upwr_pwm_retain_msg;
+typedef upwr_pointer_msg upwr_pwm_pmode_cfg_msg;
+
+#if    ( UPWR_ARG_BITS       < UPWR_DOMBIAS_ARG_BITS)
+#if    ((UPWR_ARG_BITS + 32) < UPWR_DOMBIAS_ARG_BITS)
+#error "too few message bits for domain bias argument"
+#endif
+#endif
+
+typedef union {
+	struct upwr_msg_hdr           hdr;       /* message header */
+	struct {
+		upwr_pwm_dom_bias_args  B;
+	} args;
+} upwr_pwm_dom_bias_msg;
+
+/* upwr_pwm_dom_bias_args
+   is an SoC-dependent message, defined in upower_soc_defs.h */
+
+typedef union {
+	struct upwr_msg_hdr           hdr;       /* message header */
+	struct {
+		upwr_pwm_mem_bias_args  B;
+	} args;
+} upwr_pwm_mem_bias_msg;
+
+/* upwr_pwm_mem_bias_args
+   is an SoC-dependent message, defined in upower_soc_defs.h */
+
+typedef upwr_pointer_msg upwr_pwm_pes_seq_msg;
+
+/* upwr_pwm_reg_config-specific message format */
+
+typedef upwr_pointer_msg upwr_pwm_regcfg_msg ;
+
+/* upwr_volt_pmic_volt-specific message format */
+
+typedef union {
+	struct upwr_msg_hdr           hdr;       /* message header */
+	struct {
+		uint32_t rsv:UPWR_HEADER_BITS;
+        uint32_t domain: 8U;
+        uint32_t rail: 8U;
+	} args;
+} upwr_volt_dom_pmic_rail_msg;
+
+typedef union {
+	struct upwr_msg_hdr hdr;
+	struct {
+		uint32_t rsv:UPWR_HEADER_BITS;
+		uint32_t rail: 4U;  /* pmic rail id  */
+		uint32_t volt: 12U; /* voltage value, accurate to mV, support 0~3.3V */
+	} args;
+} upwr_volt_pmic_set_volt_msg;
+
+typedef union {
+	struct upwr_msg_hdr hdr;
+	struct {
+		uint32_t rsv:UPWR_HEADER_BITS;
+		uint32_t rail: 16U;  /* pmic rail id  */
+	} args;
+} upwr_volt_pmic_get_volt_msg;
+
+typedef union {
+	struct upwr_msg_hdr hdr;
+	struct {
+		uint32_t rsv:UPWR_HEADER_BITS;
+		uint32_t domain: 8U;
+		uint32_t mode: 8U; /* work mode */
+	} args;
+} upwr_volt_dva_req_domain_msg;
+
+typedef union {
+	struct upwr_msg_hdr hdr;
+	struct {
+		uint32_t rsv:UPWR_HEADER_BITS;
+		uint32_t mode: 16U;  /* work mode  */
+	} args;
+} upwr_volt_dva_req_soc_msg;
+
+typedef union {
+	struct upwr_msg_hdr hdr;
+	struct {
+		uint32_t rsv:UPWR_HEADER_BITS;
+		uint32_t addr_offset: 16U;  /* addr_offset to 0x28330000  */
+	} args;
+} upwr_volt_dva_dump_info_msg;
+
+typedef upwr_pointer_msg upwr_volt_pmiccfg_msg;
+typedef upwr_pointer_msg upwr_volt_dva_req_id_msg;
+typedef upwr_down_1w_msg upwr_volt_pmic_cold_reset_msg;
+
+/* upwr_pwm_volt-specific message format */
+
+typedef union {
+	struct upwr_msg_hdr hdr;
+	struct {
+		uint32_t rsv:UPWR_HEADER_BITS;
+		uint32_t reg:UPWR_HALF_ARG_BITS;  /* regulator id  */
+		uint32_t volt:UPWR_HALF_ARG_BITS; /* voltage value */
+	} args;
+} upwr_pwm_volt_msg;
+
+/* upwr_pwm_freq_setup-specific message format */
+
+/**
+ * This message structure is used for DVFS feature
+ * 1. Because user may use different PMIC or different board,
+ * the pmic regulator of RTD/APD may change,
+ * so, user need to tell uPower the regulator number.
+ * The number must be matched with PMIC IC and board.
+ * use 4 bits for pmic regulator, support to 16 regulator.
+ *
+ * use 12 bits for target frequency, accurate to MHz, support to 4096 MHz
+ */
+typedef union {
+	struct upwr_msg_hdr hdr;
+	struct {
+		uint32_t rsv: UPWR_HEADER_BITS;
+		uint32_t rail: 4; /* pmic regulator  */
+		uint32_t target_freq: 12; /* target frequency */
+	} args;
+} upwr_pwm_freq_msg;
+
+typedef upwr_down_2w_msg upwr_pwm_param_msg;
+
+/* upwr_pwm_pmiccfg-specific message format */
+
+typedef upwr_pointer_msg upwr_pwm_pmiccfg_msg;
+
+/* functions that pass a pointer use message format upwr_pointer_msg */
+
+typedef upwr_pointer_msg upwr_pwm_cfgptr_msg;
+
+/* functions that pass 2 pointers use message format upwr_2pointer_msg
+ */
+
+typedef upwr_2pointer_msg upwr_pwm_switch_msg;
+typedef upwr_2pointer_msg upwr_pwm_pwron_msg;
+typedef upwr_2pointer_msg upwr_pwm_pwroff_msg;
+
+/* Power Management all messages */
+
+typedef union {
+	struct upwr_msg_hdr     hdr;      /* message header */
+	upwr_pwm_param_msg      param;    /* power management parameters */
+	upwr_pwm_dom_bias_msg   dom_bias; /* domain bias message */
+	upwr_pwm_mem_bias_msg   mem_bias; /* memory bias message */
+	upwr_pwm_pes_seq_msg    pes;      /* PE seq. message */
+	upwr_pwm_pmode_cfg_msg  pmode;    /* power mode config message */
+	upwr_pwm_regcfg_msg     regcfg;   /* regulator config message */
+	upwr_pwm_volt_msg       volt;     /* set voltage message */
+	upwr_pwm_freq_msg       freq;     /* set frequency message */
+	upwr_pwm_switch_msg     switches; /* switch control message */
+	upwr_pwm_pwron_msg      pwron;    /* switch/RAM/ROM power on  message */
+	upwr_pwm_pwroff_msg     pwroff;   /* switch/RAM/ROM power off message */
+	upwr_pwm_retain_msg     retain;   /* memory retain message */
+	upwr_pwm_cfgptr_msg     cfgptr;   /* configuration pointer message*/
+	upwr_pwm_dom_pwron_msg  dompwron; /* domain power on message */
+	upwr_pwm_boot_start_msg boot;     /* boot start      message */
+} upwr_pwm_msg;
+
+typedef union {
+	struct upwr_msg_hdr     hdr;      /* message header */
+	upwr_volt_pmic_set_volt_msg  set_pmic_volt;     /* set pmic voltage message */
+	upwr_volt_pmic_get_volt_msg  get_pmic_volt;     /* set pmic voltage message */
+	upwr_volt_pmic_set_mode_msg  set_pmic_mode;     /* set pmic mode message */
+	upwr_volt_pmiccfg_msg    pmiccfg;  /* PMIC configuration message */
+	upwr_volt_dom_pmic_rail_msg   dom_pmic_rail; /* domain bias message */
+	upwr_volt_dva_dump_info_msg    dva_dump_info;  /* dump dva info message */
+	upwr_volt_dva_req_id_msg    dva_req_id;  /* dump dva request id array message */
+	upwr_volt_dva_req_domain_msg    dva_req_domain;  /* dump dva request domain message */
+	upwr_volt_dva_req_soc_msg    dva_req_soc;  /* dump dva request whole soc message */
+	upwr_volt_pmeter_meas_msg    pmeter_meas_msg;  /* pmeter measure message */
+	upwr_volt_vmeter_meas_msg    vmeter_meas_msg;  /* vmeter measure message */
+	upwr_volt_pmic_cold_reset_msg    cold_reset_msg;  /* pmic cold reset message */
+} upwr_volt_msg;
+
+
+typedef union {
+	struct upwr_msg_hdr hdr;
+	struct {
+		uint32_t rsv:UPWR_HEADER_BITS;
+		uint32_t sensor_id: 16U;  /* temperature sensor id  */
+	} args;
+} upwr_temp_get_cur_temp_msg;
+
+typedef union {
+	struct upwr_msg_hdr hdr;
+	struct {
+		uint32_t rsv:UPWR_HEADER_BITS;
+		uint32_t index: 8U;  /* the delay meter index  */
+		uint32_t path: 8U;  /* the critical path number  */
+	} args;
+} upwr_dmeter_get_delay_margin_msg;
+
+#define MAX_DELAY_MARGIN 63U
+#define MAX_DELAY_CRITICAL_PATH 7U
+#define MAX_DELAY_METER_NUM 1U
+
+typedef union {
+	struct upwr_msg_hdr hdr;
+	struct {
+		uint32_t rsv:UPWR_HEADER_BITS;
+		uint32_t index: 4U;  /* the delay meter index  */
+		uint32_t path: 4U;  /* the critical path number  */
+		uint32_t dm: 8U;  /* the delay margin value of delay meter  */
+	} args;
+} upwr_dmeter_set_delay_margin_msg;
+
+#define MAX_PMON_CHAIN_SEL 1U
+
+typedef union {
+	struct upwr_msg_hdr hdr;
+	struct {
+		uint32_t rsv:UPWR_HEADER_BITS;
+		uint32_t chain_sel: 16U;  /* the process monitor delay chain sel  */
+	} args;
+} upwr_pmon_msg;
+
+typedef union {
+    struct upwr_msg_hdr hdr;           /* message header */
+    upwr_temp_get_cur_temp_msg  get_temp_msg;      /* get current temperature message */
+} upwr_temp_msg;
+
+typedef union {
+    struct upwr_msg_hdr hdr;           /* message header */
+    upwr_dmeter_get_delay_margin_msg  get_margin_msg;      /* get delay margin message */
+    upwr_dmeter_set_delay_margin_msg  set_margin_msg;      /* set delay margin message */
+    upwr_pmon_msg  pmon_msg;      /* process monitor message */
+} upwr_dmeter_msg;
+
+typedef upwr_down_2w_msg upwr_down_max_msg; /* longest downstream msg */
+
+/* upwr_dom_bias_cfg_t and upwr_mem_bias_cfg_t
+   are SoC-dependent structs, defined in upower_soc_defs.h */
+
+/* Power and mem switches */
+typedef struct {
+	volatile struct upwr_switch_board_t  swt_board[UPWR_PMC_SWT_WORDS];
+	volatile struct upwr_mem_switches_t  swt_mem  [UPWR_PMC_MEM_WORDS]  ;
+} swt_config_t;
+
+/* *************************************************************************
+ * Service Group DIAGNOSE - downstream
+ ***************************************************************************/
+
+typedef enum {            /* Diagnose Functions */
+	UPWR_DGN_MODE,    /* 0 = diagnose mode: upwr_dgn_mode */
+	UPWR_DGN_F_COUNT,
+    UPWR_DGN_BUFFER_EN,
+} upwr_dgn_f_t;
+
+typedef enum {
+	UPWR_DGN_ALL2ERR, /* record all until an error occurs,
+			     freeze recording on error             */
+	UPWR_DGN_ALL2HLT, /* record all until an error occurs,
+			     halt core        on error             */
+	UPWR_DGN_ALL,     /* trace, warnings, errors, task state recorded */
+	UPWR_DGN_MAX = UPWR_DGN_ALL,
+	UPWR_DGN_TRACE,   /* trace, warnings, errors recorded      */
+	UPWR_DGN_SRVREQ,  /* service request activity recorded     */
+	UPWR_DGN_WARN,    /* warnings and errors recorded          */
+	UPWR_DGN_ERROR,   /* only errors recorded                  */
+	UPWR_DGN_NONE,    /* no diagnostic recorded                */
+	UPWR_DGN_COUNT
+} upwr_dgn_mode_t;
+
+typedef upwr_down_1w_msg upwr_dgn_mode_msg;
+
+typedef union {
+	struct upwr_msg_hdr   hdr;
+	upwr_dgn_mode_msg     mode_msg;
+} upwr_dgn_msg;
+
+typedef struct {
+    struct upwr_msg_hdr   hdr;
+    uint32_t              buf_addr;
+} upwr_dgn_v2_msg;
+
+/* diagnostics log types in the shared RAM log buffer */
+
+typedef enum {
+	DGN_LOG_NONE       =   0x00000000,
+	DGN_LOG_INFO       =   0x10000000,
+	DGN_LOG_ERROR      =   0x20000000,
+	DGN_LOG_ASSERT     =   0x30000000,
+	DGN_LOG_EXCEPT     =   0x40000000,
+	DGN_LOG_EVENT      =   0x50000000, // old event trace
+	DGN_LOG_EVENTNEW   =   0x60000000, // new event trace
+	DGN_LOG_SERVICE    =   0x70000000,
+	DGN_LOG_TASKDEF    =   0x80000000,
+	DGN_LOG_TASKEXE    =   0x90000000,
+	DGN_LOG_MUTEX      =   0xA0000000,
+	DGN_LOG_SEMAPH     =   0xB0000000,
+	DGN_LOG_TIMER      =   0xC0000000,
+	DGN_LOG_CALLTRACE  =   0xD0000000,
+	DGN_LOG_DATA       =   0xE0000000,
+	DGN_LOG_PCTRACE    =   0xF0000000
+} upwr_dgn_log_t;
+
+/* ****************************************************************************
+ * UPSTREAM MESSAGES - RESPONSES
+ * ****************************************************************************
+ */
+
+/* generic ok/ko response message */
+
+#define UPWR_RESP_ERR_BITS (4U)
+#define UPWR_RESP_HDR_BITS (UPWR_RESP_ERR_BITS+\
+                            UPWR_SRVGROUP_BITS+UPWR_FUNCTION_BITS)
+#define UPWR_RESP_RET_BITS (32U - UPWR_RESP_HDR_BITS)
+
+typedef enum { /* response error codes */
+	UPWR_RESP_OK = 0,     /* no error */
+	UPWR_RESP_SG_BUSY,    /* service group is busy */
+	UPWR_RESP_SHUTDOWN,   /* services not up or shutting down */
+	UPWR_RESP_BAD_REQ,    /* invalid request */
+	UPWR_RESP_BAD_STATE,  /* system state doesn't allow perform the request */
+	UPWR_RESP_UNINSTALLD, /* service or function not installed */
+	UPWR_RESP_UNINSTALLED =
+	UPWR_RESP_UNINSTALLD, /* service or function not installed (alias) */
+	UPWR_RESP_RESOURCE,   /* resource not available */
+	UPWR_RESP_TIMEOUT,    /* service timeout */
+	UPWR_RESP_COUNT
+} upwr_resp_t;
+
+struct upwr_resp_hdr {
+	uint32_t errcode :UPWR_RESP_ERR_BITS;
+	uint32_t srvgrp  :UPWR_SRVGROUP_BITS;      /* service group */
+	uint32_t function:UPWR_FUNCTION_BITS;
+	uint32_t ret     :UPWR_RESP_RET_BITS;      /* return value, if any */
+};
+
+/* generic 1-word upstream message format */
+
+typedef union {
+	struct upwr_resp_hdr hdr;
+	uint32_t             word;
+} upwr_resp_msg;
+
+/* generic 2-word upstream message format */
+
+typedef struct {
+	struct upwr_resp_hdr   hdr;
+	uint32_t               word2;  /* message second word */
+} upwr_up_2w_msg;
+
+typedef upwr_up_2w_msg   upwr_up_max_msg;
+
+/* *************************************************************************
+ * Exception/Initialization - upstream
+ ***************************************************************************/
+
+#define UPWR_SOC_BITS    (7U)
+#define UPWR_VMINOR_BITS (4U)
+#define UPWR_VFIXES_BITS (4U)
+#define UPWR_VMAJOR_BITS \
+           (32U - UPWR_HEADER_BITS - UPWR_SOC_BITS - UPWR_VMINOR_BITS - UPWR_VFIXES_BITS)
+
+typedef struct {
+	uint32_t soc_id;
+	uint32_t vmajor;
+	uint32_t vminor;
+	uint32_t vfixes;
+} upwr_code_vers_t;
+
+/* message sent by firmware initialization, received by upwr_init */
+
+typedef union {
+	struct upwr_resp_hdr hdr;
+	struct {
+		uint32_t rsv:UPWR_RESP_HDR_BITS;
+		uint32_t soc:UPWR_SOC_BITS;        /* SoC identification */
+		uint32_t vmajor:UPWR_VMAJOR_BITS;  /* firmware major version */
+		uint32_t vminor:UPWR_VMINOR_BITS;  /* firmware minor version */
+		uint32_t vfixes:UPWR_VFIXES_BITS;  /* firmware fixes version */
+	} args;
+} upwr_init_msg;
+
+/* message sent by firmware when the core platform is powered up */
+
+typedef upwr_resp_msg upwr_power_up_msg;
+
+/* message sent by firmware when the core reset is released for boot */
+
+typedef upwr_resp_msg upwr_boot_up_msg;
+
+/* message sent by firmware when ready for service requests */
+
+#define UPWR_RAM_VMINOR_BITS (7)
+#define UPWR_RAM_VFIXES_BITS (6)
+#define UPWR_RAM_VMAJOR_BITS (32-UPWR_HEADER_BITS \
+                                -UPWR_RAM_VFIXES_BITS-UPWR_RAM_VMINOR_BITS)
+
+typedef union {
+	struct upwr_resp_hdr hdr;
+	struct {
+		uint32_t rsv:UPWR_RESP_HDR_BITS;
+		uint32_t vmajor:UPWR_RAM_VMAJOR_BITS; /* RAM fw major version */
+		uint32_t vminor:UPWR_RAM_VMINOR_BITS; /* RAM fw minor version */
+		uint32_t vfixes:UPWR_RAM_VFIXES_BITS; /* RAM fw fixes version */
+	} args;
+} upwr_ready_msg;
+
+/* message sent by firmware when shutdown finishes */
+
+typedef upwr_resp_msg upwr_shutdown_msg;
+
+typedef union {
+	struct upwr_resp_hdr hdr;
+	upwr_init_msg        init;
+	upwr_power_up_msg    pwrup;
+	upwr_boot_up_msg     booted;
+	upwr_ready_msg       ready;
+} upwr_startup_up_msg;
+
+/* message sent by firmware for uPower config setting */
+
+typedef upwr_resp_msg upwr_config_resp_msg;
+
+/* message sent by firmware for uPower alarm */
+
+typedef upwr_resp_msg upwr_alarm_resp_msg;
+
+/* *************************************************************************
+ * Power Management - upstream
+ ***************************************************************************/
+
+typedef upwr_resp_msg upwr_param_resp_msg;
+
+enum work_mode {
+    OVER_DRIVE,
+    NORMAL_DRIVE,
+    LOW_DRIVE
+};
+
+#define UTIMER3_MAX_COUNT 0xFFFFU
+
+#ifdef  __cplusplus
+#ifndef UPWR_NAMESPACE /* extern "C" 'cancels' the effect of namespace */
+} /* extern "C" */
+#endif
+#endif
+
+#endif /* #ifndef _UPWR_DEFS_H */
diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
index b6811d56c9c..87152ca8186 100644
--- a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
+++ b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
@@ -1,54 +1,68 @@
-// SPDX-License-Identifier: BSD-3-Clause
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2021 NXP
  */
 
 #include <log.h>
 #include <asm/io.h>
-#include <asm/arch/imx-regs.h>
 #include <linux/delay.h>
+#include <asm/arch/sys_proto.h>
 
+#include "upower_soc_defs.h"
 #include "upower_api.h"
+#include "upower_defs.h"
 
 #define UPOWER_AP_MU1_ADDR	0x29280000
-static struct mu_type *muptr = (struct mu_type *)UPOWER_AP_MU1_ADDR;
+
+static struct MU_tag *muptr = (struct MU_tag *)UPOWER_AP_MU1_ADDR;
+
+extern void upwr_txrx_isr(void);
+
+void upower_apd_inst_isr(upwr_isr_callb txrx_isr, upwr_isr_callb excp_isr)
+{
+    printf("%s: entry\n", __func__);
+}
 
 void upower_wait_resp(void)
 {
-	while (!(readl(&muptr->rsr) & BIT(0))) {
-		debug("%s: poll the mu:%x\n", __func__, readl(&muptr->rsr));
-		udelay(100);
-	}
+    while(muptr->RSR.B.RF0 == 0) {
+        debug("%s: poll the mu:%x\n", __func__, muptr->RSR.R);
+        udelay(100);
+    }
+
+    upwr_txrx_isr();
+}
+
+void usr_upwr_callb(upwr_sg_t sg, uint32_t func, upwr_resp_t errcode, int ret)
+{
 
-	upwr_txrx_isr();
 }
 
 u32 upower_status(int status)
 {
-	u32 ret = -1;
-
-	switch (status) {
-	case 0:
-		debug("%s: finished successfully!\n", __func__);
-		ret = 0;
-		break;
-	case -1:
-		printf("%s: memory allocation or resource failed!\n", __func__);
-		break;
-	case -2:
-		printf("%s: invalid argument!\n", __func__);
-		break;
-	case -3:
-		printf("%s: called in an invalid API state!\n", __func__);
-		break;
-	default:
-		printf("%s: invalid return status\n", __func__);
-		break;
-	}
-	return ret;
+    u32 ret = -1;
+    switch(status) {
+        case 0:
+            debug("%s: finished successfully!\n", __func__);
+            ret = 0;
+            break;
+        case -1:
+            printf("%s: memory allocation or resource failed!\n", __func__);
+            break;
+        case -2:
+            printf("%s: invalid argument!\n", __func__);
+            break;
+        case -3:
+            printf("%s: called in an invalid API state!\n", __func__);
+            break;
+        default:
+            printf("%s: invalid return status\n", __func__);
+            break;
+    }
+    return ret;
 }
 
-void user_upwr_rdy_callb(u32 soc, u32 vmajor, u32 vminor)
+void user_upwr_rdy_callb(uint32_t soc, uint32_t vmajor, uint32_t vminor)
 {
 	printf("%s: soc=%x\n", __func__, soc);
 	printf("%s: RAM version:%d.%d\n", __func__, vmajor, vminor);
@@ -57,18 +71,18 @@ void user_upwr_rdy_callb(u32 soc, u32 vmajor, u32 vminor)
 int upower_pmic_i2c_write(u32 reg_addr, u32 reg_val)
 {
 	int ret, ret_val;
-	enum upwr_resp err_code;
+	upwr_resp_t err_code;
 
 	ret = upwr_xcp_i2c_access(0x32, 1, 1, reg_addr, reg_val, NULL);
 	if (ret) {
-		printf("pmic i2c write failed ret %d\n", ret);
+		printf("pmic i2c read failed ret %d\n", ret);
 		return ret;
 	}
 
 	upower_wait_resp();
 	ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, &err_code, &ret_val, 1000);
 	if (ret != UPWR_REQ_OK) {
-		printf("i2c poll Failure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
+		printk("i2c poll Faliure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
 		return ret;
 	}
 
@@ -80,7 +94,7 @@ int upower_pmic_i2c_write(u32 reg_addr, u32 reg_val)
 int upower_pmic_i2c_read(u32 reg_addr, u32 *reg_val)
 {
 	int ret, ret_val;
-	enum upwr_resp err_code;
+	upwr_resp_t err_code;
 
 	if (!reg_val)
 		return -1;
@@ -94,7 +108,7 @@ int upower_pmic_i2c_read(u32 reg_addr, u32 *reg_val)
 	upower_wait_resp();
 	ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, &err_code, &ret_val, 1000);
 	if (ret != UPWR_REQ_OK) {
-		printf("i2c poll Failure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
+		printk("i2c poll Faliure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
 		return ret;
 	}
 
@@ -111,26 +125,28 @@ int upower_init(void)
 	u32 soc_id;
 	int status;
 
-	u32 swton;
-	u64 memon;
+	uint32_t swton;
+	uint64_t memon;
 	int ret, ret_val;
 
+	struct upwr_dom_bias_cfg_t bias;
+
 	do {
-		status = upwr_init(1, muptr);
+		status = upwr_init(1, muptr, NULL, NULL, upower_apd_inst_isr, NULL);
 		if (upower_status(status)) {
 			printf("%s: upower init failure\n", __func__);
 			break;
 		}
 
 		soc_id = upwr_rom_version(&fw_major, &fw_minor, &fw_vfixes);
-		if (!soc_id) {
+		if (soc_id == 0) {
 			printf("%s:, soc_id not initialized\n", __func__);
 			break;
+		} else {
+			printf("%s: soc_id=%d\n", __func__, soc_id);
+			printf("%s: version:%d.%d.%d\n", __func__, fw_major, fw_minor, fw_vfixes);
 		}
 
-		printf("%s: soc_id=%d\n", __func__, soc_id);
-		printf("%s: version:%d.%d.%d\n", __func__, fw_major, fw_minor, fw_vfixes);
-
 		printf("%s: start uPower RAM service\n", __func__);
 		status = upwr_start(1, user_upwr_rdy_callb);
 		upower_wait_resp();
@@ -138,29 +154,29 @@ int upower_init(void)
 			printf("%s: upower init failure\n", __func__);
 			break;
 		}
-	} while (0);
+	} while(0);
 
 	swton = 0xfff80;
-	ret = upwr_pwm_power_on(&swton, NULL, NULL);
+	ret = upwr_pwm_power_on(&swton, NULL /* no memories */, NULL /* no callback */);
 	if (ret)
 		printf("Turn on switches fail %d\n", ret);
 	else
 		printf("Turn on switches ok\n");
-	upower_wait_resp();
+    upower_wait_resp();
 	ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000);
 	if (ret != UPWR_REQ_OK)
-		printf("Failure %d\n", ret);
+		printk("Faliure %d\n", ret);
 
 	memon = 0x3FFFFFFFFFFFFCUL;
-	ret = upwr_pwm_power_on(NULL, (const u32 *)&memon, NULL);
+	ret = upwr_pwm_power_on(NULL, (const uint32_t *)&memon /* no memories */, NULL /* no callback */);
 	if (ret)
 		printf("Turn on memories fail %d\n", ret);
 	else
 		printf("Turn on memories ok\n");
-	upower_wait_resp();
+    upower_wait_resp();
 	ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000);
 	if (ret != UPWR_REQ_OK)
-		printf("Failure %d\n", ret);
+		printk("Faliure %d\n", ret);
 
 	mdelay(1);
 
@@ -174,7 +190,24 @@ int upower_init(void)
 
 	ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, NULL, &ret_val, 1000);
 	if (ret != UPWR_REQ_OK)
-		printf("Failure %d\n", ret);
+		printk("Faliure %d\n", ret);
+
+	if (is_soc_rev(CHIP_REV_1_0)) {
+		/* Enable AFBB for AP domain */
+		bias.apply = BIAS_APPLY_APD;
+		bias.dommode = AFBB_BIAS_MODE;
+		ret = upwr_pwm_chng_dom_bias(&bias, NULL);
+
+		if (ret)
+			printf("Enable AFBB for APD bias fail %d\n", ret);
+		else
+			printf("Enable AFBB for APD bias ok\n");
+
+		upower_wait_resp();
+		ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000);
+		if (ret != UPWR_REQ_OK)
+			printk("Faliure %d\n", ret);
+	}
 
 	return 0;
 }
diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_soc_defs.h b/arch/arm/mach-imx/imx8ulp/upower/upower_soc_defs.h
new file mode 100644
index 00000000000..3ebb0e9eedd
--- /dev/null
+++ b/arch/arm/mach-imx/imx8ulp/upower/upower_soc_defs.h
@@ -0,0 +1,1431 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/* +FHDR------------------------------------------------------------------------
+ * Copyright 2019-2021 NXP
+ * -----------------------------------------------------------------------------
+ * FILE NAME      : upower_soc_defs.h
+ * DEPARTMENT     : BSTC - Campinas, Brazil
+ * AUTHOR         : Celso Brites
+ * AUTHOR'S EMAIL : celso.brites@nxp.com
+ * -----------------------------------------------------------------------------
+ * RELEASE HISTORY
+ * VERSION DATE        AUTHOR                  DESCRIPTION
+ *
+ * $Log: upower_soc_defs.h.rca $
+ *
+ *  Revision: 1.56 Tue Apr 27 12:58:16 2021 nxa11511
+ *  Adds macro UPWR_VOLT_MICROV
+ *
+ *  Revision: 1.52 Fri Dec 11 17:03:29 2020 nxa06695
+ *  Add ifdef TYPES_LOCAL_H.
+ *
+ *  Revision: 1.51 Tue Nov 17 15:19:56 2020 nxa11511
+ *  Comments change for the API spec release 20201122,
+ *  with the new chapter with 8ULP-dependent definitions.
+ *
+ *  Revision: 1.47 Fri Oct 23 11:49:56 2020 nxa11511
+ *  Deleted the GPL license statements, leaving only BSD, as it is compatible with Linux and good for closed ROM/firmware code.
+ *
+ *  Revision: 1.46 Thu Sep 24 16:44:46 2020 nxa11511
+ *  Reduces UPWR_API_BUFFER_ENDPLUS 64 bytes to give room to diag buffer.
+ *
+ *  Revision: 1.39 Tue Sep  1 12:47:49 2020 nxa11511
+ *  Adds back GPL-2.0 license, keeping BSD3 (dual licensing).
+ *
+ *  Revision: 1.33 Thu Jun 18 11:30:48 2020 nxa11511
+ *  RDY2PATCH replaces APD_BOOTED in sic_gpor_t.
+ *
+ *  Revision: 1.30 Thu Jun  4 07:57:09 2020 nxa11511
+ *  Adds power management parameter bit SLP_ALLOW
+ *
+ *  Revision: 1.29 Tue Jun  2 05:55:04 2020 nxf42682
+ *  Updated upwr_mon_cfg_union_t bitfields to uint32_t
+ *
+ *  Revision: 1.28 Thu May 28 10:50:03 2020 nxa11511
+ *  Removed #defines for memory bias min/max voltages.
+ *
+ *  Revision: 1.21 Thu May  7 11:38:41 2020 nxf42682
+ *  Merge 1.20 with 1.15.1.1
+ *
+ *  Revision: 1.20 Wed May  6 12:40:51 2020 nxa11511
+ *  Adds #ifdefs for SoC VE compilation.
+ *
+ *  Revision: 1.14 Thu Apr 16 15:22:16 2020 nxa08113
+ *  Change the position of UPWR_APD_CORES define
+ *
+ *  Revision: 1.12 Thu Apr 16 09:54:42 2020 nxa11511
+ *  typedefs needed by API users moved from pmc_api.h to upower_soc_defs.h
+ *
+ *  Revision: 1.10 Thu Apr  9 19:28:19 2020 nxa10721
+ *  Use offsets instead pointers on APD config struct and routines, as it must be
+ *
+ *  Revision: 1.9 Thu Apr  9 05:50:36 2020 nxf42682
+ *  Returned to v1.7, for 1.8 DID NOT compile for FW releases
+ *
+ *  Revision: 1.7 Mon Apr  6 11:27:32 2020 nxa10721
+ *  Added AVD PMIC mode msk
+ *
+ *  Revision: 1.6 Mon Apr  6 11:11:34 2020 nxa11511
+ *  Adds typedef SOC_BOOT_TYPE_T, moved from 8ulp_pmc_hal.h
+ *
+ *  Revision: 1.4 Mon Mar 30 22:52:00 2020 nxa10721
+ *  Added PMIC controls for AVD domain
+ *
+ *  Revision: 1.3 Fri Mar 27 17:18:26 2020 nxa11511
+ *  Adds #ifndef guards for the RAM and word count #defines.
+ *
+ *  Revision: 1.2 Tue Mar 24 10:51:42 2020 nxa11511
+ *  Adds typedef soc_domain_t.
+ *  Moves #include "upower_defs.h" to fix compile errors.
+ *  Adds Power Mode configuration definitions.
+ *
+ * -----------------------------------------------------------------------------
+ * KEYWORDS: micro-power uPower driver API
+ * -----------------------------------------------------------------------------
+ * PURPOSE: SoC-dependent uPower driver API #defines and typedefs shared
+ *          with the firmware
+ * -----------------------------------------------------------------------------
+ * PARAMETERS:
+ * PARAM NAME RANGE:DESCRIPTION:       DEFAULTS:                           UNITS
+ * -----------------------------------------------------------------------------
+ * REUSE ISSUES: no reuse issues
+ * -FHDR--------------------------------------------------------------------- */
+
+#ifndef _UPWR_SOC_DEFS_H
+#define _UPWR_SOC_DEFS_H
+
+#include <stdbool.h>
+
+#include <linux/types.h>
+
+#ifndef TYPES_LOCAL_H
+#include <stdint.h>
+#endif
+
+#ifdef _UPWR_DEFS_H
+#error "upower_defs.h or upower_api.h included before upower_soc_defs.h"
+#endif
+
+#define UPWR_MU_MSG_SIZE            (2U) /* words */
+
+#ifdef   NUM_PMC_SWT_WORDS
+#define UPWR_PMC_SWT_WORDS          NUM_PMC_SWT_WORDS
+#endif
+
+#ifdef   NUM_PMC_RAM_WORDS
+#define UPWR_PMC_MEM_WORDS          NUM_PMC_RAM_WORDS
+#endif
+
+#ifndef UPWR_DRAM_SHARED_BASE_ADDR
+#define UPWR_DRAM_SHARED_BASE_ADDR      (0x28330000U)
+#endif
+
+#ifndef UPWR_DRAM_SHARED_SIZE
+#define UPWR_DRAM_SHARED_SIZE           (2048U)
+#endif
+
+#define UPWR_DRAM_SHARED_ENDPLUS        (UPWR_DRAM_SHARED_BASE_ADDR+\
+					 UPWR_DRAM_SHARED_SIZE)
+
+#ifndef UPWR_API_BUFFER_BASE
+#define UPWR_API_BUFFER_BASE            (0x28330600U)
+#endif
+
+#ifndef UPWR_API_BUFFER_ENDPLUS
+#define UPWR_API_BUFFER_ENDPLUS         (UPWR_DRAM_SHARED_ENDPLUS - 64U)
+#endif
+
+#ifndef UPWR_PMC_SWT_WORDS
+#define UPWR_PMC_SWT_WORDS              (1U)
+#endif
+
+#ifndef UPWR_PMC_MEM_WORDS
+#define UPWR_PMC_MEM_WORDS              (2U)
+#endif
+
+#define UPWR_OSC_HI_FREQ               (64U) // MHz
+#define UPWR_OSC_LO_FREQ               (16U) // MHz
+
+#ifndef UPWR_I2C_FREQ
+#define UPWR_I2C_FREQ                  (UPWR_OSC_HI_FREQ * 1000000U)
+#endif
+
+/******************************************************************************
+ * i.MX8ULP-dependent uPower API Definition
+ *
+ * Version: 20210430 Copyright 2019-2021 NXP
+ *
+ * This chapter documents the API definitions that are specific to the
+ * i.MX8ULP SoC.
+ *
+ */
+
+/**---------------------------------------------------------------
+ * INITIALIZATION, CONFIGURATION
+ *
+ * i.MX8ULP provides only one Message Unit (MU) for each core domain:
+ * Real Time Domain (RTD) and Application Domain (APD), which has two A35 cores.
+ * Both A35 cores in APD must share the same API instance, meaning upwr_init
+ * must be called only once for each domain. The API does not provide any
+ * mutually exclusion or locking mechanism for concurrent accesses from both
+ * APD cores, so any API arbitration, if needed, must be implemented by the
+ * API user code.
+ *
+ * A domain must not go to Power Down (PD) or Deep Power Down (DPD) power modes
+ * with any service still pending (response not received).
+ *
+ * Next sections describe the i.MX8ULP particularities of service calls.
+ *
+ */
+
+/**+
+ * upwr_start()
+ *
+ * i.MX8ULP ROM firmware provides only the launch option 0, which has no
+ * power mode transition support and provides the following services:
+ * - upwr_xcp_config
+ * - upwr_xcp_sw_alarm
+ * - upwr_pwm_param
+ * - upwr_pwm_power_on
+ * - upwr_pwm_power-off
+ * - upwr_pwm_mem_retain
+ * - upwr_pwm_chng_dom_bias
+ * - upwr_pwm_chng_mem_bias
+ *
+ * i.MX8ULP RAM firmware provides 2 launch options:
+ *
+ * 1. starts all tasks, services and power mode ones;
+ *    this is the full-featured firmware option.
+ * 2. starts only the power mode tasks; services are not available with
+ *    this option, and futher calls to upwr_start (from either domain)
+ *    have no response; this option is mostly used to accelerate power mode
+ *    mixed-signal simulations, and not intended to be used with silicon.
+ *
+ * Note: option 0 is also available if the RAM firmware is loaded.
+ */
+
+/* service upwr_pwm_set_domain_pmic_rail message argument fields*/
+typedef struct {
+	uint32_t domain: 16U;
+	uint32_t rail: 16U;
+} upwr_pwm_dom_pmic_rail_args;
+
+/* service upwr_pwm_chng_dom_bias message argument fields */
+
+#define UPWR_DOMBIAS_MODE_BITS    (2U)
+#define UPWR_DOMBIAS_RBB_BITS     (8U)
+#define UPWR_DOMBIAS_RSV_BITS     (14U)
+#define UPWR_DOMBIAS_ARG_BITS     (UPWR_DOMBIAS_RSV_BITS      + \
+                                   (2U * UPWR_DOMBIAS_MODE_BITS) + \
+                                   (4U * UPWR_DOMBIAS_RBB_BITS)  + 2U)
+
+typedef struct {
+	uint32_t  :12U; /* TODO: find a way to use UPWR_HEADER_BITS */
+	uint32_t dommode:UPWR_DOMBIAS_MODE_BITS;
+	uint32_t avdmode:UPWR_DOMBIAS_MODE_BITS;
+	uint32_t domapply:1U;
+	uint32_t avdapply:1U;
+	uint32_t rsv     :UPWR_DOMBIAS_RSV_BITS;
+	uint32_t domrbbn :UPWR_DOMBIAS_RBB_BITS;/* RTD/APD back bias N-well */
+	uint32_t domrbbp :UPWR_DOMBIAS_RBB_BITS;/* RTD/APD back bias P-well */
+	uint32_t avdrbbn :UPWR_DOMBIAS_RBB_BITS;/* AVD     back bias N-well */
+	uint32_t avdrbbp :UPWR_DOMBIAS_RBB_BITS;/* AVD     back bias P-well */
+} upwr_pwm_dom_bias_args;
+
+#define UPWR_FILL_DOMBIAS_ARGS(dom, bias, args)           \
+do {                                                      \
+	args.B.domapply = args.B.avdapply = 0U;            \
+                                                          \
+	switch (bias->apply) {                            \
+		case BIAS_APPLY_RTD_AVD:                  \
+			args.B.avdapply = 1U;              \
+			/* no break here, fallthrough */  \
+		case BIAS_APPLY_RTD:                      \
+			dom = (uint32_t)RTD_DOMAIN;       \
+			args.B.domapply = 1U;              \
+			break;                            \
+		case BIAS_APPLY_APD_AVD:                  \
+			args.B.avdapply = 1U;              \
+			/* no break here, fallthrough */  \
+		case BIAS_APPLY_APD:                      \
+			dom = (uint32_t)APD_DOMAIN;       \
+			args.B.domapply = 1U;              \
+			break;                            \
+		case BIAS_APPLY_AVD:                      \
+			args.B.avdapply = 1U;              \
+			break;                            \
+        default:                              \
+            break;                            \
+    }                                                 \
+	args.B.dommode = (uint32_t)bias->dommode;         \
+	args.B.avdmode = (uint32_t)bias->avdmode;         \
+	uint32_t sat = UPWR_BIAS2MILIV((1U << UPWR_DOMBIAS_RBB_BITS) - 1U);\
+	args.B.domrbbn = (bias->dombias.rbbn > sat)? sat: \
+                     UPWR_BIAS_MILIV(bias->dombias.rbbn); \
+	args.B.domrbbp = (bias->dombias.rbbp > sat)? sat: \
+                     UPWR_BIAS_MILIV(bias->dombias.rbbp); \
+	args.B.avdrbbn = (bias->avdbias.rbbn > sat)? sat: \
+                     UPWR_BIAS_MILIV(bias->avdbias.rbbn); \
+	args.B.avdrbbp = (bias->avdbias.rbbp > sat)? sat: \
+                     UPWR_BIAS_MILIV(bias->avdbias.rbbp); \
+} while (0)
+
+/* service upwr_pwm_chng_mem_bias message argument fields */
+
+typedef struct {
+	uint32_t  :12U; /* TODO: find a way to use UPWR_HEADER_BITS */
+	uint32_t en:1U;
+	uint32_t rsv:19U;
+} upwr_pwm_mem_bias_args;
+
+#define UPWR_FILL_MEMBIAS_ARGS(bias, args)                \
+do {                                                      \
+	args.B.en = bias->en;                             \
+} while (0)
+
+#include "upower_defs.h"
+
+#ifdef  __cplusplus
+#ifndef UPWR_NAMESPACE /* extern "C" 'cancels' the effect of namespace */
+extern "C" {
+#endif
+#endif
+
+#define UPWR_APD_CORES      (2U)
+#define UPWR_RTD_CORES      (1U)
+
+#define RTD_DOMAIN (0U)
+#define APD_DOMAIN (1U)
+#define UPWR_MAIN_DOMAINS (2U)
+#define AVD_DOMAIN (2U)
+#define UPWR_DOMAIN_COUNT (3U)
+#define PSD_DOMAIN (3U)
+#define UPWR_ALL_DOMAINS (4U)
+
+typedef uint32_t soc_domain_t;
+
+/*=========================================================================
+ * UNIT CONVERSION MACROS
+ *   These macros convert physical units to the values passed as arguments
+ *   in API functions.
+ *=========================================================================*/
+
+#define UPWR_VOLT_MILIV(v) (v)        /* voltage in mV    to argument value */
+#define UPWR_VOLT_MICROV(v)((v) / 1000U) /* voltage in uV    to argument value */
+#define UPWR_BIAS_MILIV(v) (((v) + 49U ) / 50U)   /* bias voltage(mV) to argument value */
+#define UPWR_BIAS2MILIV(v) ((v) * 50U)   /* inverse of UPWR_BIAS_MILIV         */
+#define UPWR_FREQ_KHZ(f)   (f)        /* frequency (kHz)  to argument value */
+
+#define UPWR_DOMBIAS_MAX_MV      (UPWR_BIAS2MILIV((1U << UPWR_DOMBIAS_RBB_BITS) - 1U))
+
+/**---------------------------------------------------------------
+ * EXCEPTION SERVICE GROUP
+ */
+
+/**+
+ * upwr_xcp_config()
+ *
+ * The i.MX8ULP uPower configuration struct contains the following bitfields:
+ *
+ *  - ALARM_INT (1 bit): tells which RTD MU interrupt should be used for alarms;
+ *    1= MU GPI1; 0= MU GPI0; APD alarms always use GPI0.
+ *  - CFG_IOMUX (1 bit): determintes if uPower configures i.MX8ULP IOMUX for
+ *    I2C and mode pins used to control an external PMIC;
+ *    1= uPower firmware or PMIC driver configures i.MX8ULP IOMUX and mode pins;
+ *    0= i.MX8ULP IOMUX and mode pins not configured by uPower;
+ *  - DGNBUFBITS (4 bits): determines the diagnostic buffer size according to
+ *    the formula: size = 2^(DGNBUFBITS+3) bytes;
+ *
+ *  Defaults are all zeroes; all other bits are reserved, and must be written 0.
+ */
+
+typedef union {
+	uint32_t R;
+	struct {
+		uint32_t ALARM_INT   :1U; /* 1= use MU GPI1 for alarm interrupt;
+					    0= use MU GPI0 for alarm interrupt;
+					    this configuration is valid for
+					    RTD only
+					  */
+		uint32_t CFG_IOMUX  : 1U; /* 1= tells uPower fw/PMIC driver to
+					       config i.MX8ULP IOMUX for the PMIC
+					       I2C and mode pins;
+					    0= uPower fw/PMIC must not config
+					       i.MX8ULP IOMUX, leave it to host
+					  */
+		uint32_t DGNBUFBITS : 4U; /* defines the diagnostic buffer size
+					    according to the formula:
+					    size = 2^(DGNBUFBITS+3) bytes */
+		uint32_t RSV        :26U; /* reserved bits: should be all 0s  */
+	} B;
+} upwr_xcp_config_t;
+
+/**+
+ * upwr_xcp_sw_alarm()
+ *
+ * Argument code is defined by the enum upwr_alarm_t, with the values:
+ *  - UPWR_ALARM_INTERNAL: internal software error
+ *  - UPWR_ALARM_EXCEPTION: uPower core exception, either illegal instruction or
+ *    bus error
+ *  - UPWR_ALARM_SLACK: delay path too slow, meaning a timing violation occurred
+ *    or is iminent.
+ *  - UPWR_ALARM_VOLTAGE: one of the measured voltages is below safety margins.
+ *
+ * Note that this service emulates an alarm that would normally be issued by
+ * uPower when it detects one of the causes above. A request to alarm the APD
+ * domain when it is powered off returns success, but is ineffective.
+ *
+ */
+
+typedef enum {
+	UPWR_ALARM_INTERNAL,             /* internal error */
+	UPWR_ALARM_EXCEPTION,            /* core exception */
+	UPWR_ALARM_SLACK,                /* delay path too slow */
+	UPWR_ALARM_VOLTAGE,              /* voltage drop */
+	UPWR_ALARM_LAST = UPWR_ALARM_VOLTAGE
+} upwr_alarm_t;
+
+/**---------------------------------------------------------------
+ * POWER MANAGEMENT SERVICE GROUP
+ */
+
+                                     /* values in mV: */
+
+#define UPWR_RTD_RBBN_MAX     (1300U) /* max. RTD Reverse Back Bias N-Well */
+#define UPWR_RTD_RBBN_MIN      (100U) /* min. RTD Reverse Back Bias N-Well */
+
+#define UPWR_RTD_RBBP_MAX     (1300U) /* max. RTD Reverse Back Bias P-Well */
+#define UPWR_RTD_RBBP_MIN      (100U) /* min. RTD Reverse Back Bias P-Well */
+
+/* APD bias can only two values (mV): */
+
+#define UPWR_APD_RBBN_LO      (1000U) /* low  APD Reverse Back Bias N-Well */
+#define UPWR_APD_RBBN_HI      (1300U) /* high APD Reverse Back Bias N-Well */
+
+#define UPWR_APD_RBBP_LO      (1000U) /* low  APD Reverse Back Bias P-Well */
+#define UPWR_APD_RBBP_HI      (1300U) /* high APD Reverse Back Bias P-Well */
+
+/* AVD bias can only two values (mV): */
+
+#define UPWR_AVD_RBBN_LO      (1000U) /* low  AVD Reverse Back Bias N-Well */
+#define UPWR_AVD_RBBN_HI      (1300U) /* high AVD Reverse Back Bias N-Well */
+
+#define UPWR_AVD_RBBP_LO      (1000U) /* low  AVD Reverse Back Bias P-Well */
+#define UPWR_AVD_RBBP_HI      (1300U) /* high AVD Reverse Back Bias P-Well */
+
+/**+
+ * upwr_pwm_param()
+ *
+ * Argument param is defined by the struct/union upwr_pwm_param_t with the
+ * following i.MX8ULP-specific bitfields:
+ * - DPD_ALLOW (1 bit): 1= allows uPower power mode to go Deep Power Down (DPD);
+ *   uPower DPD also depends on other conditions, but if this bit is 0 uPower
+ *   won't go DPD even if those conditions are met; it can go either Sleep or
+ *   Deep Sleep (DSL) depending on the other configurations.
+ * - DSL_DIS (1 bit): if this bit is 1, uPower power mode won't go Deep Sleep
+ *   (DSL) even if the other conditions for that are met;
+ *   it may go Sleep instead.
+ * - SLP_ALLOW (1 bit): if this bit is 1, uPower power mode will go Sleep if
+ *   the conditions for Partial Active are met; it may also go Deep Sleep if bit
+ *   DSL_DIS=1.
+ * - DSL_BGAP_OFF (1 bit): 1= turns bandgap off when uPower goes Deep Sleep;
+ *   0= leaves bandgap on when uPower goes Deep Sleep (DSL).
+ * - DPD_BGAP_ON (1 bit): 1= leaves bandgap on when uPower goes Deep Power Down
+ *   (DPD); 0= powers off bandgap when uPower goes Deep Power Down (DPD).
+ *
+ *  Defaults are all zeroes; all other bits are reserved, and must be written 0.
+ */
+
+typedef union {
+	uint32_t R;
+	struct {
+		uint32_t DPD_ALLOW   :1U; /* 1= uPower can go Deep Power Down */
+		uint32_t DSL_DIS     :1U; /* 1= uPower won't go Deep Sleep    */
+		uint32_t SLP_ALLOW   :1U; /* 1= uPower goes Sleep in the same
+					       conditions as Active, and even
+					       DSL if DSL_DIS=1  */
+		uint32_t DSL_BGAP_OFF:1U; /* 1= turn bandgap off when uPower
+					       goes Deep Sleep               */
+		uint32_t DPD_BGAP_ON :1U; /* 1= leave bandgap on when uPower
+                                               goes Deep Power Down          */
+		uint32_t RSV        :27U; /* reserved bits: should be all 0s  */
+	} B;
+} upwr_pwm_param_t;
+
+/**+
+ * upwr_pwm_chng_reg_voltage()
+ *
+ * Argument reg is defined by the enum upwr_pmc_reg_t, with regulator ids:
+ *  - RTD_PMC_REG: RTD regulator
+ *  - APD_PMC_REG: APD regulator
+ *  - RTD_BIAS_PMC_REG: RTD bias regulator
+ *  - APD_BIAS_PMC_REG: APD bias regulator
+ *  - RTD_LVD_PMC_MON: RTD LVD regulator
+ *  - APD_LVD_PMC_MON: APD LVD regulator
+ *  - AVD_LVD_PMC_MON: AVD LVD regulator
+ *
+ * Argument volt is defined by the formula:
+ *
+ * argument = 92.30797633*V - 55.000138, rounded to the nearest integer,
+ * where V is the value in Volts, with a minimum of 0.595833 V (argument = 0).
+ *
+ */
+
+/* Regulator ids */
+
+typedef enum {
+	RTD_PMC_REG,
+	APD_PMC_REG,
+	RTD_BIAS_PMC_REG,
+	APD_BIAS_PMC_REG,
+	RTD_LVD_PMC_MON,
+	APD_LVD_PMC_MON,
+	AVD_LVD_PMC_MON
+} upwr_pmc_reg_t;
+
+/**+
+ * upwr_pwm_freq_setup()
+ *
+ * Argument domain is either RTD_DOMAIN or APD_DOMAIN.
+ * Arguments nextfq and currfq are to be defined (TBD).
+ */
+
+/**+
+ * upwr_pwm_dom_power_on()
+ *
+ * The arguments must comply with the restrictions below, otherwise the service
+ * is not executed and returns error UPWR_RESP_BAD_REQ:
+ * - argument domain can only be APD_DOMAIN, because in i.MX8ULP it is not
+ *   possible APD powered on (calling the service) with RTD completely
+ *   powered off.
+ * - the call can only be made from the RTD domain, for the same reason.
+ * - argument boot can only be 1, because in i.MX8ULP it is not possible to
+ *   power on the APD domain without starting the core boot.
+ *
+ * If APD is already powered on and booting/booted when the service is called,
+ * it returns success without doing anything.
+ */
+
+/**+
+ * upwr_pwm_boot_start()
+ *
+ * The arguments must comply with the restrictions below, otherwise the service
+ * is not executed and returns error UPWR_RESP_BAD_REQ:
+ * - argument domain can only be APD_DOMAIN, because in i.MX8ULP it is not
+ *   possible APD powered on (calling the service) with RTD completely
+ *   powered off.
+ * - the call can only be made from the RTD domain, for the same reason.
+ *
+ * If APD is already booted when the service is called, it returns success
+ * without doing anything. Otherwise, it returns the error UPWR_RESP_BAD_STATE,
+ * because in i.MX8ULP APD cannot be booted separately from power on.
+ */
+
+/**+
+ * upwr_pwm_power_on(),
+ * upwr_pwm_power_off(),
+ * upwr_pwm_mem_retain()
+ *
+ * These three service functions use the same arguments:
+ *
+ * argument swt is an array of one 32-bit word: uint32_t swt[1];
+ * naturally the pointer to a single uint32_t variable may be passed.
+ * Each bit of the word correponds to a switch, according to the i.MX8ULP
+ * Reference Manual Rev B draft 2 table 64 Power switch reset state,
+ * and the following formula:
+ *
+ * if switch number < 10 bit number = switch number;
+ * if switch number >  9 bit number = switch number + 3;
+ *
+ * bits 9, 10, 11 and 12 must have the same value (corresponding to switch 9)
+ *
+ * Note: this argument is not used in upwr_pwm_mem_retain.
+ *
+ * argument mem is an array of two 32-bit words: uint32_t mem[2];
+ * naturally the pointer to a single uint64_t variable may be passed, since
+ * both ARM and RISC-V are little endian architectures.
+ * Each bit of the words correponds to a memory, according to the i.MX8ULP
+ * Reference Manual table "Memory Partitions".
+ *
+ * Turning a memory completely on (array and peripheral) will automatically
+ * turn on its power switch, even if not explicitely commanded.
+ * Turning a memory's power switch off will automatically turn off its array
+ * and peripheral beforehand, even if not explicitly commanded.
+ *
+ * Argument restrictions:
+ *
+ * The swt and mem arguments must comply with the restrictions below, otherwise
+ * the service is not executed (no switch/memory is changed) and returns error
+ * UPWR_RESP_BAD_REQ:
+ *  1. one must not put a memory in retention comming from an off state.
+ *  2. switches 9, 10, 11 and 12 must be turned on/off simultaneously.
+ *  3. an AVD switch can only be turned off if all AVD switches belong to the
+ *     domain requesting the service (as defined by registers SYSCTRL0,
+ *     LPAV_MASTER_ALLOC_CTRL and LPAV_SLAVE_ALLOC_CTRL);
+ *     there is no such restriction to turn the switch on.
+ *  4. an AVD memory can only be turned off or put in retention if all
+ *     AVD memories belong to the domain requesting the service
+ *     (as defined by registers SYSCTRL0, LPAV_MASTER_ALLOC_CTRL and
+ *      LPAV_SLAVE_ALLOC_CTRL); there is no such restriction to turn on the
+ *     memories.
+ *  5. EdgeLock RAMs must not be turned off, unless RTD domain is in
+ *     Deep Power Down (DPD).
+ *  6. Power Switch 19 must be on to turn on switches 17 (MIPI/DSI),
+ *     18 (MIPI/CSI), and all AVD power switches.
+ *
+ * Service Errors:
+ *
+ * Besides the error UPWR_RESP_BAD_REQ caused by violations of the restrictions
+ * above, the services may fail with error UPWR_RESP_RESOURCE if a power mode
+ * transition or a similar service is executing at the same time.
+ * This error should be interpreted as a "try later" response, as the service
+ * will succeed once those concurrent executions are done, and no other is
+ * started.
+ */
+
+/**+
+ * upwr_pwm_chng_switch_mem()
+ *
+ * The bit numbers in the argument struct mask and on/off state fields
+ * are the same as for services upwr_pwm_power_on, upwr_pwm_power_off and
+ * upwr_pwm_mem_retain.
+ *
+ * Turning a memory completely on (array and peripheral) will automatically
+ * turn on its power switch, even if not explicitely commanded.
+ *
+ * Argument restrictions:
+ *
+ * Same argument restrictions as services upwr_pwm_power_on, upwr_pwm_power_off
+ * and upwr_pwm_mem_retain, plus the following:
+ *
+ *  1. one must not turn a memory peripheral on and a memory array off.
+ *  2. one must not put a memory in retention and switch its power switch off.
+ *
+ * Service Errors:
+ *
+ * Besides the error UPWR_RESP_BAD_REQ caused by violations of the restrictions
+ * above, the service may fail with error UPWR_RESP_RESOURCE if a power mode
+ * transition or a similar service is executing at the same time.
+ * This error should be interpreted as a "try later" response, as the service
+ * will succeed once those concurrent executions are done, and no other is
+ * started.
+ */
+
+/**+
+ * upwr_pwm_pmode_config()
+ *
+ * The same power switch and memory restrictions of service
+ * upwr_pwm_chng_switch_mem apply between power modes, however they are not
+ * enforced by this service, that is, it does not return service error.
+ *
+ * The default power mode configurations for RTD and APD are documented in the
+ * i.MX8ULP Reference Manual sections "Power mode details (real-time domain)"
+ * and "Power mode details (application domain)", respectively.
+ * If those configurations are satisfactory, this service does not have
+ * to be called.
+ *
+ * Power Mode Configuration Structure:
+ *
+ * Follows a description of the power mode configuration structure elements.
+ * - dom_swts: the same switch configuration structures used in service
+ *             upwr_pwm_chng_switch_mem argument swt.
+ * - mem_swts: the same memory configuration structures used in service
+ *             upwr_pwm_chng_switch_mem argument mem.
+ * - regs: an array of structs base_reg_cfg_t (see upower_soc_defs.h),
+ *         one element for each regulator; base_reg_cfg_t has fields
+ *         mode (regulator-dependent), lvl (voltage level in uV),
+ *         comp (regulator-dependent complamentary info).
+ * - pads: pad configuration in low power; see pad_cfg_t definition below.
+ * - mons: domain monitors (LVD and HVD) configuration;
+ *         see mon_cfg_t definition below.
+ * - avd_mons: same as mons for the AVD domain; see mon_cfg_t definition below.
+ * - dom_bbias: back-bias configuration for the domain;
+ *              see base_bbias_cfg_t definition below.
+ * - avd_bbias: back-bias configuration for the AVD domain;
+ *              see base_bbias_cfg_t definition below.
+ * - mem_bbias: back-bias configuration for the memory;
+ *              see base_bbias_cfg_t definition below.
+ * - mem_fbias: forward-bias configuration for the memory;
+ *              see base_fbias_cfg_t definition below.
+ * - pmic: PMIC-specific configuration
+ *
+ * Structure pad_cfg_t:
+ *
+ * Pad control for low power modes (power off, etc), 1 bit per pad segment.
+ * - rst  : put pad segment in reset.
+ * - iso  : put pad segment in isolation.
+ * - compl: specific pad segment information.
+ * - msk  : select which pads will be updated.
+ *
+ * Structure mon_cfg_t:
+ *
+ * Configures a voltage monitor and its actions.
+ * There are monitors for RTD, APD and AVD, monitoring LVD and HVD.
+ * - lvl  : Voltage level (in uV).
+ * - mode : Mode of monitor (ON, OFF, LP, etc).
+ * - compl: Extra info for the monitor.
+ *
+ * Structure base_bbias_cfg_t:
+ *
+ * Configures back-bias (for domain or memory).
+ * - mode : Back bias mode (OFF, RBB, ARBB, etc).
+ * - p_lvl: Voltage level of p-well (in mV).
+ * - n_lvl: Voltage level of n-well (in mV).
+ * - compl: Complementary bias-specific (enable reset, interrupt, clamp, etc).
+ *
+ * Structure base_fbias_cfg_t:
+ *
+ * Configure memory forward bias for a memory segment.
+ *
+ * - mode : Forward bias mode (OFF, ON).
+ * - msk  : Selects which memory will be updated
+ *
+ */
+
+/*=========================================================================
+ * Domain bias
+ *=========================================================================*/
+
+/**+
+ * upwr_pwm_chng_dom_bias()
+ *
+ * Argument bias is a pointer to a struct with fields:
+ *  - apply: tells to which domains the bias must be applied;
+ *    options are RTD only (BIAS_APPLY_RTD), RTD and AVD (BIAS_APPLY_RTD_AVD),
+ *    APD only (BIAS_APPLY_APD), APD and AVD (BIAS_APPLY_APD_AVD),
+ *    AVD only (BIAS_APPLY_AVD)
+ *  - dommode: bias mode of the main domain (RTD or APD, determined by apply);
+ *    options are disabled (NBB_BIAS_MODE), reverse back bias (RBB_BIAS_MODE),
+ *    asymmetrical forward bias (AFBB_BIAS_MODE), asymmetrical reverse bias
+ *    (ARBB_BIAS_MODE).
+ *  - avdmode: bias mode of Audio-Video Domain (AVD);
+ *    options are the same as dommode.
+ *  - dombias: bias voltage level(s) for the main domain (RTD or APD,
+ *    determined by apply); it is a structure with 2 fields, rbbn and rbbp,
+ *    for the N-well and P-well voltages, respectively; values are in mV.
+ *  - avdbias: bias voltage level(s) for the Audio-Video Domain (AVD);
+ *    same fields as dombias;
+ *
+ * Argument restrictions:
+ *
+ * Voltage levels must comply with the #define-determined limits/options:
+ * between UPWR_RTD_RBBN_MIN and UPWR_RTD_RBBN_MAX (inclusive) for RTD N-well;
+ * between UPWR_RTD_RBBP_MIN and UPWR_RTD_RBBP_MAX (inclusive) for RTD P-well;
+ * either UPWR_APD_RBBN_LO or UPWR_APD_RBBN_HI for APD N-well;
+ * either UPWR_APD_RBBP_LO or UPWR_APD_RBBP_HI for APD P-well;
+ * either UPWR_AVD_RBBN_LO or UPWR_AVD_RBBN_HI for AVD N-well;
+ * either UPWR_AVD_RBBP_LO or UPWR_AVD_RBBP_HI for AVD P-well;
+ *
+ * But note that the limits/options above do not apply to all bias modes:
+ * rbbn is used and checked only in mode RBB_BIAS_MODE;
+ * rbbp is used and checked only in modes RBB_BIAS_MODE and ARBB_BIAS_MODE;
+ * modes AFBB_BIAS_MODE and NBB_BIAS_MODE use or check neither rbbn nor rbbp;
+ *
+ * Service error UPWR_RESP_BAD_REQ is returned if the voltage limits/options
+ * above are violated.
+ */
+
+/* argument struct for service upwr_pwm_chng_dom_bias:
+ */
+
+typedef enum {               /* bias modes (both domain and memory): */
+	NBB_BIAS_MODE  = 0,  /* bias disabled */
+	RBB_BIAS_MODE  = 1,  /* reverse back bias enabled */
+	AFBB_BIAS_MODE = 2,  /* asymmetrical forward bias */
+	ARBB_BIAS_MODE = 3   /* asymmetrical reverse bias */
+} upwr_bias_mode_t;
+
+/* Domain Bias config (one per domain) */
+
+typedef enum {
+	BIAS_APPLY_RTD,      /* apply to RTD only    */
+	BIAS_APPLY_RTD_AVD,  /* apply to RTD and AVD */
+	BIAS_APPLY_APD,      /* apply to APD only    */
+	BIAS_APPLY_APD_AVD,  /* apply to APD and AVD */
+	BIAS_APPLY_AVD,      /* apply to AVD only    */
+	BIAS_APPLY_COUNT     /* number of apply options */
+} upwr_bias_apply_t;
+
+typedef struct {
+	uint16_t          rbbn;    /* reverse back bias N well (mV) */
+	uint16_t          rbbp;    /* reverse back bias P well (mV) */
+} upwr_rbb_t;
+
+struct upwr_dom_bias_cfg_t {
+	upwr_bias_apply_t apply;   /* bias application option  */
+	upwr_bias_mode_t  dommode; /* RTD/APD bias mode config */
+	upwr_bias_mode_t  avdmode; /* AVD     bias mode config */
+	upwr_rbb_t        dombias; /* RTD/APD reverse back bias */
+	upwr_rbb_t        avdbias; /* AVD     reverse back bias */
+};
+
+/* bias struct used in power mode config definitions */
+
+/**
+ *
+
+ When write power mode transition program, please read below comments carefully.
+ The structure and logic is complex, There is a lot of extension and reuse.
+
+ First, for mode, extend "uint32_t mode" to a union struct, add support for AVD:
+typedef union {
+  uint32_t                  R;
+  struct {
+    uint32_t                  mode      : 8;    // Dom bias mode
+    uint32_t                  rsrv_1    : 8;
+    uint32_t                  avd_mode  : 8;    // AVD bias mode
+    uint32_t                  rsrv_2    : 8;
+  }                         B;
+} dom_bias_mode_cfg_t;
+
+  Second, if mode is AFBB mode, no need to configure rbbn and rbbp, uPower firmware will configure all SRAM_AFBB_0 or SRAM_AFBB_1 for corresponding domain.
+
+  Third, if mode is RBB mode, extend "uint32_t rbbn" and "uint32_t rbbp" to a union struct, add support for AVD:
+  typedef union {
+  uint32_t                  R;
+  struct {
+    uint32_t                  lvl       : 8;    // Dom bias level
+    uint32_t                  rsrv_1    : 8;
+    uint32_t                  avd_lvl   : 8;    // AVD bias level
+    uint32_t                  rsrv_2    : 8;
+  }                         B;
+} dom_bias_lvl_cfg_t;
+
+ *
+ */
+typedef struct {
+	uint32_t mode; /* Domain bias mode config, extend to dom_bias_mode_cfg_t to support RTD, APD, AVD */
+	uint32_t rbbn; /* reverse back bias N well */
+	uint32_t rbbp; /* reverse back bias P well */
+} UPWR_DOM_BIAS_CFG_T;
+
+/*=========================================================================
+ * Memory bias
+ *=========================================================================*/
+
+/**+
+ * upwr_pwm_chng_mem_bias()
+ *
+ * Argument struct contains only the field en, which can be either 1 (bias
+ * enabled) or 0 (bias disabled).
+ *
+ * Argument domain must be either RTD_DOMAIN (Real Time Domain) or APD_DOMAIN
+ * (Application Domain).
+ */
+
+/* Memory Bias config */
+
+struct upwr_mem_bias_cfg_t {
+	uint32_t en; /* Memory bias enable config */
+};
+
+/* bias struct used in power mode config definitions */
+
+typedef struct {
+	uint32_t en; /* Memory bias enable config */
+} UPWR_MEM_BIAS_CFG_T;
+
+/* Split different Bias */
+
+struct upwr_pmc_bias_cfg_t {
+	UPWR_DOM_BIAS_CFG_T dombias_cfg; /* Domain Bias config */
+	UPWR_MEM_BIAS_CFG_T membias_cfg; /* Memory Bias config */
+};
+
+/*=========================================================================
+ * Power modes
+ *=========================================================================*/
+
+typedef enum {/* from msb->lsb: Azure bit, dual boot bit, low power boot bit */
+	SOC_BOOT_SINGLE   = 0,
+	SOC_BOOT_LOW_PWR  = 1,
+	SOC_BOOT_DUAL     = 2,
+	SOC_BOOT_AZURE    = 4
+} SOC_BOOT_TYPE_T;
+
+#define GEN_CASE_ENUM_NAME(e) \
+  case(e): return (char*)#e
+
+/* Power modes for RTD domain  */
+typedef enum {
+	DPD_RTD_PWR_MODE, /* Real Time Deep Power Down mode */
+	PD_RTD_PWR_MODE,  /* Real Time Power Down mode */
+	DSL_RTD_PWR_MODE, /* Real Time Domain Deep Sleep Mode */
+	HLD_RTD_PWR_MODE, /* Real Time Domain Hold Mode */
+	SLP_RTD_PWR_MODE, /* Sleep Mode */
+	ADMA_RTD_PWR_MODE,/* Active DMA Mode */
+	ACT_RTD_PWR_MODE, /* Active Domain Mode */
+	NUM_RTD_PWR_MODES
+} upwr_ps_rtd_pwr_mode_t;
+
+static inline const char* get_rtd_pwr_mode_name(upwr_ps_rtd_pwr_mode_t mode)
+{
+	switch(mode) {
+		GEN_CASE_ENUM_NAME(DPD_RTD_PWR_MODE);
+		GEN_CASE_ENUM_NAME(PD_RTD_PWR_MODE);
+		GEN_CASE_ENUM_NAME(DSL_RTD_PWR_MODE);
+		GEN_CASE_ENUM_NAME(HLD_RTD_PWR_MODE);
+		GEN_CASE_ENUM_NAME(SLP_RTD_PWR_MODE);
+		GEN_CASE_ENUM_NAME(ADMA_RTD_PWR_MODE);
+		GEN_CASE_ENUM_NAME(ACT_RTD_PWR_MODE);
+		default: return (char*)"WRONG_RTD_PWER_MODE";
+	}
+}
+
+/* Abstract power modes */
+typedef enum {
+	DPD_PWR_MODE,
+	PD_PWR_MODE,
+	PACT_PWR_MODE,
+	DSL_PWR_MODE,
+	HLD_PWR_MODE,
+	SLP_PWR_MODE,
+	ADMA_PWR_MODE,
+	ACT_PWR_MODE,
+	NUM_PWR_MODES,
+	NUM_APD_PWR_MODES = NUM_PWR_MODES,
+	TRANS_PWR_MODE    = NUM_PWR_MODES,
+	INVALID_PWR_MODE  = TRANS_PWR_MODE + 1
+} abs_pwr_mode_t;
+
+typedef struct {
+	abs_pwr_mode_t  mode;
+	bool            ok;
+} pch_trans_t;
+
+typedef pch_trans_t rtd_trans_t;
+
+typedef struct {
+	abs_pwr_mode_t  mode;
+	pch_trans_t     core[UPWR_APD_CORES];
+} apd_trans_t;
+
+
+/* Get name of a power mode */
+static inline char *get_abs_pwr_mode_name(abs_pwr_mode_t mode)
+{
+	switch(mode) {
+		GEN_CASE_ENUM_NAME(DPD_PWR_MODE);
+		GEN_CASE_ENUM_NAME(PD_PWR_MODE);
+		GEN_CASE_ENUM_NAME(PACT_PWR_MODE);
+		GEN_CASE_ENUM_NAME(DSL_PWR_MODE);
+		GEN_CASE_ENUM_NAME(HLD_PWR_MODE);
+		GEN_CASE_ENUM_NAME(SLP_PWR_MODE);
+		GEN_CASE_ENUM_NAME(ADMA_PWR_MODE);
+		GEN_CASE_ENUM_NAME(ACT_PWR_MODE);
+		default: return (char*)"WRONG_ABS_PWR_MODE";
+	}
+}
+
+
+/* Power modes for APD cores. PCH pactive is one-hot w/ these values */
+#if 0 // TODO: remove it?
+typedef enum {
+  PD_CORE_PWR_MODE,
+  SLP_CORE_PWR_MODE,
+  ADMA_CORE_PWR_MODE,
+  ACT_CORE_PWR_MODE,
+  NUM_CORE_PWR_MODES
+} upwr_core_pwr_mode_t;
+
+static inline const char* get_core_pwr_mode_name(upwr_core_pwr_mode_t mode) {
+  switch(mode) {
+  GEN_CASE_ENUM_NAME(PD_CORE_PWR_MODE);
+  GEN_CASE_ENUM_NAME(SLP_CORE_PWR_MODE);
+  GEN_CASE_ENUM_NAME(ADMA_CORE_PWR_MODE);
+  GEN_CASE_ENUM_NAME(ACT_CORE_PWR_MODE);
+  default: return (char*)"WRONG_CORE_PWR_MODE";
+  }
+}
+#endif
+
+/* Codes for APD pwr mode as programmed in LPMODE reg */
+typedef enum {
+	ACT_APD_LPM,
+	SLP_APD_LPM    = 1,
+	DSL_APD_LPM    = 3,
+	PACT_APD_LPM   = 7,
+	PD_APD_LPM     = 15,
+	DPD_APD_LPM    = 31,
+	HLD_APD_LPM    = 63
+} upwr_apd_lpm_t;
+
+static inline const char *get_apd_pwr_mode_name(upwr_apd_lpm_t mode)
+{
+	switch(mode) {
+		GEN_CASE_ENUM_NAME(ACT_APD_LPM);
+		GEN_CASE_ENUM_NAME(SLP_APD_LPM);
+		GEN_CASE_ENUM_NAME(DSL_APD_LPM);
+		GEN_CASE_ENUM_NAME(PACT_APD_LPM);
+		GEN_CASE_ENUM_NAME(PD_APD_LPM);
+		GEN_CASE_ENUM_NAME(DPD_APD_LPM);
+		GEN_CASE_ENUM_NAME(HLD_APD_LPM);
+		default: return (char*)"WRONG_APD_LPM";
+	}
+}
+
+/* PowerSys low power config */
+
+struct upwr_powersys_cfg_t {
+	uint32_t lpm_mode; /* Powersys low power mode */
+};
+
+/*=*************************************************************************
+ * RTD
+ *=*************************************************************************/
+
+/* Config pmc PADs */
+
+struct upwr_pmc_pad_cfg_t {
+	uint32_t pad_close;   /* PMC PAD close config */
+	uint32_t pad_reset;   /* PMC PAD reset config */
+	uint32_t pad_tqsleep; /* PMC PAD TQ Sleep config */
+};
+
+/* Config regulator (internal and external) */
+
+struct upwr_reg_cfg_t {
+	uint32_t volt;  /* Regulator voltage config */
+	uint32_t mode;  /* Regulator mode config */
+};
+
+/* Config pmc monitors */
+
+struct  upwr_pmc_mon_cfg_t {
+	uint32_t mon_hvd_en; /* PMC mon HVD */
+	uint32_t mon_lvd_en; /* PMC mon LVD */
+	uint32_t mon_lvdlvl; /* PMC mon LVDLVL */
+};
+
+/* Same monitor config for RTD (for compatibility) */
+
+#define upwr_pmc_mon_rtd_cfg_t upwr_pmc_mon_cfg_t
+
+typedef swt_config_t ps_rtd_swt_cfgs_t[NUM_RTD_PWR_MODES];
+typedef swt_config_t ps_apd_swt_cfgs_t[NUM_APD_PWR_MODES];
+
+/*=*************************************************************************
+ * APD
+ *=*************************************************************************/
+
+/* PowerSys PMIC config */
+struct upwr_pmic_cfg_t {
+	uint32_t                      volt;
+	uint32_t                      mode;
+	uint32_t                      mode_msk;
+};
+
+typedef uint32_t offs_t;
+
+struct ps_apd_pwr_mode_cfg_t {
+	#ifdef UPWR_SIMULATOR_ONLY
+	struct upwr_switch_board_t*   swt_board_offs;
+	struct upwr_mem_switches_t*   swt_mem_offs;
+	#else
+	offs_t                        swt_board_offs;
+	offs_t                        swt_mem_offs;
+	#endif
+	struct upwr_pmic_cfg_t        pmic_cfg;
+	struct upwr_pmc_pad_cfg_t     pad_cfg;
+	struct upwr_pmc_bias_cfg_t    bias_cfg;
+};
+
+/* Get the pointer to swt config */
+static inline struct upwr_switch_board_t*
+get_apd_swt_cfg(volatile struct ps_apd_pwr_mode_cfg_t *cfg)
+{
+	char  *ptr;
+	ptr = (char*)cfg;
+	ptr += (uint64_t)cfg->swt_board_offs;
+	return (struct upwr_switch_board_t*)ptr;
+}
+
+/* Get the pointer to mem config */
+static inline struct upwr_mem_switches_t*
+get_apd_mem_cfg(volatile struct ps_apd_pwr_mode_cfg_t *cfg)
+{
+	char  *ptr;
+	ptr =  (char*)cfg;
+	ptr += (uint64_t)cfg->swt_mem_offs;
+	return (struct upwr_mem_switches_t*)ptr;
+}
+
+/* Power Mode configuration */
+
+#define ps_rtd_pwr_mode_cfg_t upwr_power_mode_cfg_t
+
+/* these typedefs are just for RISC-V sizeof purpose */
+typedef uint32_t swt_board_ptr_t;
+typedef uint32_t swt_mem_ptr_t;
+
+struct upwr_power_mode_cfg_t {
+	#ifdef UPWR_SIMULATOR_ONLY
+	struct upwr_switch_board_t*   swt_board; /* Swt board for mem. */
+	struct upwr_mem_switches_t*   swt_mem;   /* Swt to mem. arrays, perif */
+	#else
+	#ifdef __LP64__
+	uint32_t                      swt_board;
+	uint32_t                      swt_mem;
+	#else
+	struct upwr_switch_board_t*   swt_board; /* Swt board for mem. */
+	struct upwr_mem_switches_t*   swt_mem;   /* Swt to mem. arrays, perif */
+	#endif
+	#endif
+	struct upwr_reg_cfg_t         in_reg_cfg; /* internal regulator config*/
+	struct upwr_reg_cfg_t         pmic_cfg;   /* external regulator - pmic*/
+	struct upwr_pmc_pad_cfg_t     pad_cfg;  /* Pad conf for power trans*/
+	struct upwr_pmc_mon_rtd_cfg_t mon_cfg;    /*monitor configuration */
+	struct upwr_pmc_bias_cfg_t    bias_cfg;   /* Memomry/Domain Bias conf */
+	struct upwr_powersys_cfg_t    pwrsys_lpm_cfg;/* pwrsys low power config*/
+};
+
+static inline int unsigned upwr_sizeof_pmode_cfg(uint32_t domain)
+{
+	switch (domain)
+	{
+		case RTD_DOMAIN: return sizeof(struct upwr_power_mode_cfg_t) +
+					(sizeof(struct upwr_switch_board_t)*
+					 UPWR_PMC_SWT_WORDS) +
+					(sizeof(struct upwr_mem_switches_t)*
+					 UPWR_PMC_MEM_WORDS) -
+					2*(sizeof(void*) - sizeof(swt_board_ptr_t));
+		case APD_DOMAIN: return sizeof(struct ps_apd_pwr_mode_cfg_t) +
+					(sizeof(struct upwr_switch_board_t)*
+					 UPWR_PMC_SWT_WORDS) +
+					(sizeof(struct upwr_mem_switches_t)*
+					 UPWR_PMC_MEM_WORDS);
+	}
+
+	return 0;
+}
+
+/*=*************************************************************************
+ * SIC
+ *=*************************************************************************/
+
+/* SIC GPO according to Integration Guide */
+typedef union {
+	volatile uint32_t       R;
+	struct {
+		/* b[0] */
+		volatile uint32_t     PMODE         : 7;
+		volatile uint32_t     MODECHG       : 1;
+		/* b[1] */
+		volatile uint32_t     SNTL_RETN     : 1;
+		volatile uint32_t     rsrv_1        : 2;
+		volatile uint32_t     IRAM_RETN     : 1;
+		volatile uint32_t     DRAM_RETN     : 1;
+		volatile uint32_t     RTD_KEEP_RST  : 1;
+		volatile uint32_t     APD_KEEP_RST  : 1;
+		volatile uint32_t     RDY2PATCH     : 1;
+		/* b[2] */
+		volatile uint32_t     RTD_LLWU      : 1;
+		volatile uint32_t     APD_LLWU      : 1;
+		volatile uint32_t     rsrv_3        : 1;
+		volatile uint32_t     AVD_RST_HOLD  : 1;
+		volatile uint32_t     USB0_RETN     : 1;
+		volatile uint32_t     MIPI_DSI_ENA  : 1;
+		volatile uint32_t     DDR_RETN      : 1;
+		volatile uint32_t     PMIC_WAIT_DIS : 1;
+		/* b[3] */
+		volatile uint32_t     RTD_EARLY_REL : 1;
+		volatile uint32_t     RTD_ASYNC_REL : 1;
+		volatile uint32_t     RTD_CORE_REL  : 1;
+		volatile uint32_t     RTD_RST_HOLD  : 1;
+		volatile uint32_t     APD_EARLY_REL : 1;
+		volatile uint32_t     APD_ASYNC_REL : 1;
+		volatile uint32_t     APD_CORE_REL  : 1;
+		volatile uint32_t     APD_RST_HOLD  : 1;
+	}               B;
+	volatile uint8_t        b[4];
+} sic_gpor_t;
+
+/* SIC GPI according to Integration Guide */
+
+/* AVD domain power switches */
+#define AVD_PWR_SWITCH_MASK           ((1 <<  7)|\
+                                       (1 <<  8)|\
+                                       (1 <<  9)|\
+                                       (1 << 10)|\
+                                       (1 << 11)|\
+                                       (1 << 12)|\
+                                       (1 << 13)|\
+                                       (1 << 14)|\
+                                       (1 << 15)|\
+                                       (1 << 16))
+
+typedef union {
+	volatile uint32_t          R;
+	struct {
+		/* AVD Slave */
+		volatile uint32_t       LPAV_MASTER         : 1;
+		volatile uint32_t       LPAV_SAI6           : 1;
+		volatile uint32_t       LPAV_SAI7           : 1;
+		volatile uint32_t       LPAV_SEMA42         : 1;
+		volatile uint32_t       LPAV_LPTMP8         : 1;
+		volatile uint32_t       LPAV_SPDIF          : 1;
+		volatile uint32_t       rsrv_1              : 2;
+		/* AVD Master */
+		volatile uint32_t       LPAV_PXP            : 1;
+		volatile uint32_t       LPAV_GPU2D          : 1;
+		volatile uint32_t       LPAV_GPU3D          : 1;
+		volatile uint32_t       LPAV_DCNANO         : 1;
+		volatile uint32_t       LPAV_MIPI_DSI       : 1;
+		volatile uint32_t       rsrv_2              : 1;
+		volatile uint32_t       LPAV_EPDC           : 1;
+		volatile uint32_t       LPAV_HIFI4          : 1;
+		/* APD LPMODE */
+		volatile uint32_t       APD_LPMODE          : 6;
+		volatile uint32_t       rsrv_3              : 2;
+		/* General */
+		volatile uint32_t       rsrv_4              : 4;
+		volatile uint32_t       SENT_BUSY           : 1;
+		volatile uint32_t       APD_RES_RTD         : 1;
+		volatile uint32_t       SENT_ACK            : 1;
+		volatile uint32_t       LDOEN               : 1;
+	} B;
+} sic_gpir_t;
+
+/* Mask the AVD peripherals in sic_gpir_t */
+#define AVD_PERIPH_OWNER_MSK          (0xffffUL & ~(0x3UL<<6) & ~(0x1UL<<13))
+
+/*=*************************************************************************
+ * PMC
+ *=*************************************************************************/
+
+/* Operating modes of devices */
+typedef enum {
+	OFF_PMC_MODE,
+	ON_PMC_MODE,
+	LP_PMC_MODE,
+	HP_PMC_MODE,
+	ENA_PMC_MODE,
+	DIS_PMC_MODE
+} pmc_dev_mode_t;
+
+/* Monitor Inputs types */
+typedef enum {
+	RTD_LVD_INP,
+	APD_LVD_INP,
+	AVD_LVD_INP,
+	RTD_HVD_INP,
+	APD_HVD_INP,
+	AVD_HVD_INP,
+	POR_INP,
+	LDOEN_INP
+} pmc_inp_t;
+
+typedef enum {
+	PAD_CLOSE_EVT,
+	PAD_RST_EVT,
+	PAD_TQSLEEP_EVT
+} pmc_pad_evt_t;
+
+
+/*=*************************************************************************
+ * All configs
+ *=*************************************************************************/
+
+/* LVD/HVD monitor config for a single domain */
+
+/* Domain + AVD monitor config
+ * For RTD, mapped in mon_cfg.mon_hvd_en
+ * For APD, mapped temporarily in pad_cfg.pad_tqsleep
+ */
+typedef union upwr_mon_cfg_union_t {
+		volatile uint32_t         R;
+		struct {
+		/* Original config, not change */
+		volatile uint32_t          rsrv_1          : 8;
+		/* DOM */
+		volatile uint32_t          dom_lvd_irq_ena : 1;
+		volatile uint32_t          dom_lvd_rst_ena : 1;
+		volatile uint32_t          dom_hvd_irq_ena : 1;
+		volatile uint32_t          dom_hvd_rst_ena : 1;
+		volatile uint32_t          dom_lvd_lvl     : 4;
+		volatile uint32_t          dom_lvd_ena     : 1;
+		volatile uint32_t          dom_hvd_ena     : 1;
+		/* AVD */
+		volatile uint32_t          avd_lvd_irq_ena : 1;
+		volatile uint32_t          avd_lvd_rst_ena : 1;
+		volatile uint32_t          avd_hvd_irq_ena : 1;
+		volatile uint32_t          avd_hvd_rst_ena : 1;
+		volatile uint32_t          avd_lvd_lvl     : 4;
+		volatile uint32_t          avd_lvd_ena     : 1;
+		volatile uint32_t          avd_hvd_ena     : 1;
+	}                         B;
+} upwr_mon_cfg_t;
+
+/* Get the monitor config word from RAM (domaind and AVD) */
+
+static inline uint32_t get_mon_cfg(uint8_t dom, void *mode_cfg)
+{
+	if (dom == RTD_DOMAIN) {
+		return
+		  ((struct ps_rtd_pwr_mode_cfg_t*)mode_cfg)->mon_cfg.mon_hvd_en;
+	}
+	else {
+		return
+		 ((struct ps_apd_pwr_mode_cfg_t*)mode_cfg)->pad_cfg.pad_tqsleep;
+	}
+}
+
+/* Set the monitor config word in RAM (domaind and AVD) */
+
+static inline void  set_mon_cfg(uint8_t        dom,
+				void          *mode_cfg,
+				upwr_mon_cfg_t mon_cfg)
+{
+	uint32_t        *cfg;
+	if (dom == RTD_DOMAIN) {
+		cfg = (uint32_t*)
+		 &((struct ps_rtd_pwr_mode_cfg_t*)mode_cfg)->mon_cfg.mon_hvd_en;
+	}
+	else {
+		cfg = (uint32_t*)
+		&((struct ps_apd_pwr_mode_cfg_t*)mode_cfg)->pad_cfg.pad_tqsleep;
+	}
+	*cfg = mon_cfg.R;
+}
+
+/* Uniformize access to PMIC cfg for RTD and APD */
+
+typedef union {
+	struct upwr_reg_cfg_t     RTD;
+	struct upwr_pmic_cfg_t    APD;
+} pmic_cfg_t;
+
+/* Access to PMIC mode mask and AVD mode */
+
+typedef union {
+	uint32_t                  R;
+	struct {
+		uint8_t                   mode;     /* Domain PMIC mode */
+		uint8_t                   msk;      /* Domain PMIC mode mask */
+		uint8_t                   avd_mode; /* AVD PMIC mode */
+		uint8_t                   avd_msk;  /* AVD PMIC mode mask */
+	}                         B;
+} pmic_mode_cfg_t;
+
+/* Access RTD, APD and AVD modes and masks */
+
+static inline pmic_mode_cfg_t *get_pmic_mode_cfg(uint8_t dom, pmic_cfg_t *cfg)
+{
+	uint32_t        *mode_cfg;
+
+	if (dom == RTD_DOMAIN) mode_cfg = &cfg->RTD.mode;
+			  else mode_cfg = &cfg->APD.mode;
+	return (pmic_mode_cfg_t*)mode_cfg;
+}
+
+static inline uint8_t get_pmic_mode(uint8_t dom, pmic_cfg_t *cfg)
+{
+	return get_pmic_mode_cfg(dom, cfg)->B.mode;
+}
+
+static inline void set_pmic_mode(uint8_t dom, pmic_cfg_t *cfg, uint8_t mode)
+{
+	get_pmic_mode_cfg(dom, cfg)->B.mode = mode;
+}
+
+static inline uint8_t get_pmic_mode_msk(uint8_t dom, pmic_cfg_t *cfg)
+{
+	pmic_mode_cfg_t   *mode_cfg;
+
+	if (dom == RTD_DOMAIN) {
+		mode_cfg = (pmic_mode_cfg_t*)&cfg->RTD.mode;
+		return mode_cfg->B.msk;
+	}
+	else return cfg->APD.mode_msk;
+}
+
+static inline void set_pmic_mode_msk(uint8_t dom, pmic_cfg_t *cfg, uint8_t msk)
+{
+	pmic_mode_cfg_t   *mode_cfg;
+
+	if (dom == RTD_DOMAIN) {
+		mode_cfg = (pmic_mode_cfg_t*)&cfg->RTD.mode;
+		mode_cfg->B.msk = msk;
+	}
+	else cfg->APD.mode_msk = msk;
+}
+
+/* Getters and setters for AVD mode and mask */
+static inline uint8_t get_avd_pmic_mode(uint8_t dom, pmic_cfg_t *cfg)
+{
+	return get_pmic_mode_cfg(dom, cfg)->B.avd_mode;
+}
+
+static inline void set_avd_pmic_mode(uint8_t dom, pmic_cfg_t *cfg, uint8_t mode)
+{
+	get_pmic_mode_cfg(dom, cfg)->B.avd_mode = mode;
+}
+
+static inline uint8_t get_avd_pmic_mode_msk(uint8_t dom, pmic_cfg_t *cfg)
+{
+	return get_pmic_mode_cfg(dom, cfg)->B.avd_msk;
+}
+
+static inline void set_avd_pmic_mode_msk(uint8_t     dom,
+					 pmic_cfg_t *cfg,
+					 uint8_t     msk)
+{
+	get_pmic_mode_cfg(dom, cfg)->B.avd_msk = msk;
+}
+
+
+typedef struct ps_rtd_pwr_mode_cfg_t ps_rtd_pwr_mode_cfgs_t[NUM_RTD_PWR_MODES];
+typedef struct ps_apd_pwr_mode_cfg_t ps_apd_pwr_mode_cfgs_t[NUM_APD_PWR_MODES];
+
+struct ps_pwr_mode_cfg_t {
+	ps_rtd_pwr_mode_cfgs_t  ps_rtd_pwr_mode_cfg;
+	ps_rtd_swt_cfgs_t       ps_rtd_swt_cfg;
+	ps_apd_pwr_mode_cfgs_t  ps_apd_pwr_mode_cfg ;
+	ps_apd_swt_cfgs_t       ps_apd_swt_cfg;
+};
+
+#define UPWR_XCP_MIN_ADDR   (0x28350000U)
+#define UPWR_XCP_MAX_ADDR   (0x2836FFFCU)
+
+struct upwr_reg_access_t {
+	uint32_t     addr;
+	uint32_t     data;
+	uint32_t     mask; /* mask=0 commands read */
+};
+
+typedef upwr_pointer_msg upwr_xcp_access_msg;
+
+/* unions for the shared memory buffer */
+
+typedef union {
+	struct upwr_reg_access_t            reg_access;
+} upwr_xcp_union_t;
+
+typedef union {
+	struct {
+		struct ps_rtd_pwr_mode_cfg_t rtd_struct;
+		struct upwr_switch_board_t   rtd_switch;
+		struct upwr_mem_switches_t   rtd_memory;
+	}                                                rtd_pwr_mode;
+	struct {
+		struct ps_apd_pwr_mode_cfg_t apd_struct;
+		struct upwr_switch_board_t   apd_switch;
+		struct upwr_mem_switches_t   apd_memory;
+	}                                                apd_pwr_mode;
+} upwr_pwm_union_t;
+
+#define MAX_SG_EXCEPT_MEM_SIZE sizeof(upwr_xcp_union_t)
+#define MAX_SG_PWRMGMT_MEM_SIZE sizeof(upwr_pwm_union_t)
+
+/**
+ * VOLTM group need shared memory for PMIC IC configuration
+ * 256 Bytes is enough for PMIC register array
+ */
+#define MAX_SG_VOLTM_MEM_SIZE 256U
+
+#ifdef  __cplusplus
+#ifndef UPWR_NAMESPACE /* extern "C" 'cancels' the effect of namespace */
+} /* extern "C" */
+#endif
+#endif
+
+#endif /* #ifndef _UPWR_SOC_DEFS_H */
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
new file mode 100644
index 00000000000..c709448411d
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -0,0 +1,35 @@
+if ARCH_IMX9
+
+config AHAB_BOOT
+    bool "Support i.MX9 AHAB features"
+    help
+    This option enables the support for AHAB secure boot.
+
+config IMX9
+	bool
+	select ARCH_EARLY_INIT_R
+	select HAS_CAAM
+	select ROM_UNIFIED_SECTIONS
+
+config IMX93
+	bool
+	select IMX9
+	select ARMV8_SPL_EXCEPTION_VECTORS
+
+config SYS_SOC
+	default "imx9"
+
+choice
+	prompt  "NXP i.MX9 board select"
+	optional
+
+config TARGET_IMX93_11X11_EVK
+	bool "imx93_11x11_evk"
+	select IMX93
+
+endchoice
+
+source "board/freescale/imx93_evk/Kconfig"
+
+endif
+
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
new file mode 100644
index 00000000000..e1b09ab5341
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2022 NXP
+
+obj-y += lowlevel_init.o
+obj-y += soc.o clock.o clock_root.o trdc.o
+
+#ifndef CONFIG_SPL_BUILD
+obj-y += imx_bootaux.o
+#endif
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
new file mode 100644
index 00000000000..7dc33941a9e
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -0,0 +1,882 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/ccm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <errno.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <log.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct anatop_reg *ana_regs = (struct anatop_reg *)ANATOP_BASE_ADDR;
+
+static struct imx_intpll_rate_table imx9_intpll_tbl[] = {
+	INT_PLL_RATE(1800000000U, 1, 150, 2), /* 1.8Ghz */
+	INT_PLL_RATE(1700000000U, 1, 141, 2), /* 1.7Ghz */
+	INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */
+	INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */
+	INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */
+};
+
+static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
+	FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */
+	FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */
+	FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */
+	FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1),
+	FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1),
+	FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */
+	FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */
+};
+
+/* return in khz */
+static u32 decode_pll_vco(struct ana_pll_reg *reg, bool fracpll)
+{
+	u32 ctrl;
+	u32 pll_status;
+	u32 div;
+	int rdiv, mfi, mfn, mfd;
+	int clk = 24000;
+
+	ctrl = readl(&reg->ctrl.reg);
+	pll_status = readl(&reg->pll_status);
+	div = readl(&reg->div.reg);
+
+	if (!(ctrl & PLL_CTRL_POWERUP))
+		return 0;
+
+	if (!(pll_status & PLL_STATUS_PLL_LOCK))
+		return 0;
+
+	mfi = (div & GENMASK(24, 16)) >> 16;
+	rdiv = (div & GENMASK(15, 13)) >> 13;
+
+	if (rdiv == 0)
+		rdiv = 1;
+
+	if (fracpll) {
+		mfn = (int)readl(&reg->num.reg);
+		mfn >>= 2;
+		mfd = (int)(readl(&reg->denom.reg) & GENMASK(29, 0));
+
+		clk = clk * (mfi * mfd + mfn) / mfd / rdiv;
+	} else {
+		clk = clk * mfi / rdiv;
+	}
+
+	return (u32)clk;
+}
+
+/* return in khz */
+static u32 decode_pll_out(struct ana_pll_reg *reg, bool fracpll)
+{
+	u32 ctrl = readl(&reg->ctrl.reg);
+	u32 div;
+
+	if (ctrl & PLL_CTRL_CLKMUX_BYPASS)
+		return 24000;
+
+	if (!(ctrl & PLL_CTRL_CLKMUX_EN))
+		return 0;
+
+	div = readl(&reg->div.reg);
+	div &= 0xff; /* odiv */
+
+	if (div == 0)
+		div = 2;
+	else if (div == 1)
+		div = 3;
+
+	return decode_pll_vco(reg, fracpll) / div;
+}
+
+/* return in khz */
+static u32 decode_pll_pfd(struct ana_pll_reg *reg,
+	struct ana_pll_dfs *dfs_reg, bool div2, bool fracpll)
+{
+	u32 pllvco = decode_pll_vco(reg, fracpll);
+	u32 dfs_ctrl = readl(&dfs_reg->dfs_ctrl.reg);
+	u32 dfs_div = readl(&dfs_reg->dfs_div.reg);
+	u32 mfn, mfi;
+	u32 output;
+
+	if (dfs_ctrl & PLL_DFS_CTRL_BYPASS)
+		return pllvco;
+
+	if (!(dfs_ctrl & PLL_DFS_CTRL_ENABLE) ||
+		(div2 && !(dfs_ctrl & PLL_DFS_CTRL_CLKOUT_DIV2)) ||
+		(!div2 && !(dfs_ctrl & PLL_DFS_CTRL_CLKOUT)))
+		return 0;
+
+	mfn = dfs_div & GENMASK(2, 0);
+	mfi = (dfs_div & GENMASK(15, 8)) >> 8;
+
+	if (mfn > 3)
+		return 0; /* valid mfn 0-3 */
+
+	if (mfi == 0 || mfi == 1)
+		return 0; /* valid mfi 2-255 */
+
+	output = (pllvco * 5) / (mfi * 5 + mfn);
+
+	if (div2)
+		return output >> 1;
+
+	return output;
+}
+
+static u32 decode_pll(enum ccm_clk_src pll)
+{
+	switch (pll) {
+	case ARM_PLL_CLK:
+		return decode_pll_out(&ana_regs->arm_pll, false);
+	case SYS_PLL_PG:
+		return decode_pll_out(&ana_regs->sys_pll, false);
+	case SYS_PLL_PFD0:
+		return decode_pll_pfd(&ana_regs->sys_pll,
+			&ana_regs->sys_pll.dfs[0], false, true);
+	case SYS_PLL_PFD0_DIV2:
+		return decode_pll_pfd(&ana_regs->sys_pll,
+			&ana_regs->sys_pll.dfs[0], true, true);
+	case SYS_PLL_PFD1:
+		return decode_pll_pfd(&ana_regs->sys_pll,
+			&ana_regs->sys_pll.dfs[1], false, true);
+	case SYS_PLL_PFD1_DIV2:
+		return decode_pll_pfd(&ana_regs->sys_pll,
+			&ana_regs->sys_pll.dfs[1], true, true);
+	case SYS_PLL_PFD2:
+		return decode_pll_pfd(&ana_regs->sys_pll,
+			&ana_regs->sys_pll.dfs[2], false, true);
+	case SYS_PLL_PFD2_DIV2:
+		return decode_pll_pfd(&ana_regs->sys_pll,
+			&ana_regs->sys_pll.dfs[2], true, true);
+	case AUDIO_PLL_CLK:
+		return decode_pll_out(&ana_regs->audio_pll, true);
+	case DRAM_PLL_CLK:
+		return decode_pll_out(&ana_regs->dram_pll, true);
+	case VIDEO_PLL_CLK:
+		return decode_pll_out(&ana_regs->video_pll, true);
+	default:
+		printf("Invalid clock source to decode\n");
+		break;
+	}
+
+	return 0;
+}
+
+int configure_intpll(enum ccm_clk_src pll, u32 freq)
+{
+	int i;
+	struct imx_intpll_rate_table *rate;
+	struct ana_pll_reg *reg;
+	u32 pll_status;
+
+	for (i = 0; i < ARRAY_SIZE(imx9_intpll_tbl); i++) {
+		if (freq == imx9_intpll_tbl[i].rate)
+			break;
+	}
+
+	if (i == ARRAY_SIZE(imx9_intpll_tbl)) {
+		debug("No matched freq table %u\n", freq);
+		return -EINVAL;
+	}
+
+	rate = &imx9_intpll_tbl[i];
+
+	/* ROM has configured SYS PLL and PFD, no need for it */
+	switch (pll) {
+	case ARM_PLL_CLK:
+		reg = &ana_regs->arm_pll;
+		break;
+	default:
+		return -EPERM;
+	}
+
+	/* Bypass the PLL to ref */
+	writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_set);
+
+	/* disable pll and output */
+	writel(PLL_CTRL_CLKMUX_EN | PLL_CTRL_POWERUP, &reg->ctrl.reg_clr);
+
+	/* Program the ODIV, RDIV, MFI */
+	writel((rate->odiv & GENMASK(7, 0)) |
+		((rate->rdiv << 13 ) & GENMASK(15, 13)) |
+		((rate->mfi << 16) & GENMASK(24, 16)), &reg->div.reg);
+
+#ifndef CONFIG_TARGET_IMX93_EMU
+	/* wait 5us */
+	udelay(5);
+#endif
+
+	/* power up the PLL and wait lock (max wait time 100 us) */
+	writel(PLL_CTRL_POWERUP, &reg->ctrl.reg_set);
+
+#ifndef CONFIG_TARGET_IMX93_EMU
+	udelay(100);
+#endif
+
+	pll_status = readl(&reg->pll_status);
+	if (pll_status & PLL_STATUS_PLL_LOCK) {
+		writel(PLL_CTRL_CLKMUX_EN, &reg->ctrl.reg_set);
+
+		/* clear bypass */
+		writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_clr);
+
+	} else {
+		debug("Fail to lock PLL %u\n", pll);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+
+int configure_fracpll(enum ccm_clk_src pll, u32 freq)
+{
+	int i;
+	struct imx_fracpll_rate_table *rate;
+	struct ana_pll_reg *reg;
+	u32 pll_status;
+
+	for (i = 0; i < ARRAY_SIZE(imx9_fracpll_tbl); i++) {
+		if (freq == imx9_fracpll_tbl[i].rate)
+			break;
+	}
+
+	if (i == ARRAY_SIZE(imx9_fracpll_tbl)) {
+		debug("No matched freq table %u\n", freq);
+		return -EINVAL;
+	}
+
+	rate = &imx9_fracpll_tbl[i];
+
+	switch (pll) {
+	case SYS_PLL_PG:
+		reg = &ana_regs->sys_pll;
+		break;
+	case DRAM_PLL_CLK:
+		reg = &ana_regs->dram_pll;
+		break;
+	case VIDEO_PLL_CLK:
+		reg = &ana_regs->video_pll;
+		break;
+	default:
+		return -EPERM;
+	}
+
+	/* Bypass the PLL to ref */
+	writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_set);
+
+	/* disable pll and output */
+	writel(PLL_CTRL_CLKMUX_EN | PLL_CTRL_POWERUP, &reg->ctrl.reg_clr);
+
+	/* Program the ODIV, RDIV, MFI */
+	writel((rate->odiv & GENMASK(7, 0)) |
+		((rate->rdiv << 13 ) & GENMASK(15, 13)) |
+		((rate->mfi << 16) & GENMASK(24, 16)), &reg->div.reg);
+
+	/* Set SPREAD_SPECRUM enable to 0 */
+	writel(PLL_SS_EN, &reg->ss.reg_clr);
+
+	/* Program NUMERATOR and DENOMINATOR */
+	writel((rate->mfn << 2), &reg->num.reg);
+	writel((rate->mfd & GENMASK(29, 0)), &reg->denom.reg);
+
+#ifndef CONFIG_TARGET_IMX93_EMU
+	/* wait 5us */
+	udelay(5);
+#endif
+
+	/* power up the PLL and wait lock (max wait time 100 us) */
+	writel(PLL_CTRL_POWERUP, &reg->ctrl.reg_set);
+
+#ifndef CONFIG_TARGET_IMX93_EMU
+	udelay(100);
+#endif
+
+	pll_status = readl(&reg->pll_status);
+	if (pll_status & PLL_STATUS_PLL_LOCK) {
+		writel(PLL_CTRL_CLKMUX_EN, &reg->ctrl.reg_set);
+
+#ifndef CONFIG_TARGET_IMX93_EMU
+		/* check the MFN is updated */
+		pll_status = readl(&reg->pll_status);
+		if ((pll_status & ~0x3) != (rate->mfn << 2)) {
+			debug("MFN update not matched, pll_status 0x%x, mfn 0x%x\n",
+				pll_status, rate->mfn);
+			return -EIO;
+		}
+#endif
+		/* clear bypass */
+		writel(PLL_CTRL_CLKMUX_BYPASS, &reg->ctrl.reg_clr);
+
+	} else {
+		debug("Fail to lock PLL %u\n", pll);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+int configure_pll_pfd(enum ccm_clk_src pll_pfg, u32 mfi, u32 mfn, bool div2_en)
+{
+	struct ana_pll_dfs *dfs;
+	struct ana_pll_reg *reg;
+	u32 dfs_status;
+	u32 index;
+
+	if (mfn > 3)
+		return -EINVAL; /* valid mfn 0-3 */
+
+	if (mfi < 2 || mfi > 255)
+		return -EINVAL; /* valid mfi 2-255 */
+
+	switch (pll_pfg) {
+	case SYS_PLL_PFD0:
+		reg = &ana_regs->sys_pll;
+		index = 0;
+		break;
+	case SYS_PLL_PFD1:
+		reg = &ana_regs->sys_pll;
+		index = 1;
+		break;
+	case SYS_PLL_PFD2:
+		reg = &ana_regs->sys_pll;
+		index = 2;
+		break;
+	default:
+		return -EPERM;
+	}
+
+	dfs = &reg->dfs[index];
+
+	/* Bypass the DFS to PLL VCO */
+	writel(PLL_DFS_CTRL_BYPASS, &dfs->dfs_ctrl.reg_set);
+
+	/* disable DFS and output */
+	writel(PLL_DFS_CTRL_ENABLE | PLL_DFS_CTRL_CLKOUT |
+		PLL_DFS_CTRL_CLKOUT_DIV2, &dfs->dfs_ctrl.reg_clr);
+
+	writel(((mfi << 8) & GENMASK(15, 8)) | (mfn & GENMASK(2, 0)),
+		&dfs->dfs_div.reg);
+
+	writel(PLL_DFS_CTRL_CLKOUT, &dfs->dfs_ctrl.reg_set);
+	if (div2_en)
+		writel(PLL_DFS_CTRL_CLKOUT_DIV2, &dfs->dfs_ctrl.reg_set);
+	writel(PLL_DFS_CTRL_ENABLE, &dfs->dfs_ctrl.reg_set);
+
+#ifndef CONFIG_TARGET_IMX93_EMU
+	/*
+         * As HW expert said: after enabling the DFS, clock will start
+         * coming after 6 cycles output clock period.
+         * 5us is much bigger than expected, so it will be safe
+         */
+	udelay(5);
+#endif
+
+	dfs_status = readl(&reg->dfs_status);
+
+	if (!(dfs_status & (1 << index))) {
+		debug("DFS lock failed\n");
+		return -EIO;
+	}
+
+	/* Bypass the DFS to PLL VCO */
+	writel(PLL_DFS_CTRL_BYPASS, &dfs->dfs_ctrl.reg_clr);
+
+	return 0;
+}
+
+int update_fracpll_mfn(enum ccm_clk_src pll, int mfn)
+{
+	struct ana_pll_reg *reg;
+	bool repoll = false;
+	u32 pll_status;
+	int count = 20;
+
+	switch (pll) {
+	case AUDIO_PLL_CLK:
+		reg = &ana_regs->audio_pll;
+		break;
+	case DRAM_PLL_CLK:
+		reg = &ana_regs->dram_pll;
+		break;
+	case VIDEO_PLL_CLK:
+		reg = &ana_regs->video_pll;
+		break;
+	default:
+		printf("Invalid pll %u for update FRAC PLL MFN\n", pll);
+		return -EINVAL;
+	}
+
+	if (readl(&reg->pll_status) & PLL_STATUS_PLL_LOCK)
+		repoll = true;
+
+	mfn <<= 2;
+	writel(mfn, &reg->num);
+
+	if (repoll) {
+		do {
+			pll_status = readl(&reg->pll_status);
+			udelay(5);
+			count--;
+		} while (((pll_status & ~0x3) != (u32)mfn) && count > 0);
+
+		if (count <= 0) {
+			printf("update MFN timeout, pll_status 0x%x, mfn 0x%x\n",
+				pll_status, mfn);
+			return -EIO;
+		}
+	}
+
+	return 0;
+}
+
+int update_pll_pfd_mfn(enum ccm_clk_src pll_pfd, u32 mfn)
+{
+	struct ana_pll_dfs *dfs;
+	u32 val;
+	u32 index;
+
+	switch (pll_pfd) {
+	case SYS_PLL_PFD0:
+	case SYS_PLL_PFD0_DIV2:
+		index = 0;
+		break;
+	case SYS_PLL_PFD1:
+	case SYS_PLL_PFD1_DIV2:
+		index = 1;
+		break;
+	case SYS_PLL_PFD2:
+	case SYS_PLL_PFD2_DIV2:
+		index = 2;
+		break;
+	default:
+		printf("Invalid pfd %u for update PLL PFD MFN\n", pll_pfd);
+		return -EINVAL;
+	}
+
+	dfs = &ana_regs->sys_pll.dfs[index];
+
+	val = readl(&dfs->dfs_div.reg);
+	val &= ~0x3;
+	val |= mfn & 0x3;
+	writel(val, &dfs->dfs_div.reg);
+
+	return 0;
+}
+
+/* return in khz */
+u32 get_clk_src_rate(enum ccm_clk_src source)
+{
+	u32 ctrl;
+	bool clk_on;
+
+	switch (source) {
+	case ARM_PLL_CLK:
+		ctrl = readl(&ana_regs->arm_pll.ctrl.reg);
+	case AUDIO_PLL_CLK:
+		ctrl = readl(&ana_regs->audio_pll.ctrl.reg);
+		break;
+	case DRAM_PLL_CLK:
+		ctrl = readl(&ana_regs->dram_pll.ctrl.reg);
+		break;
+	case VIDEO_PLL_CLK:
+		ctrl = readl(&ana_regs->video_pll.ctrl.reg);
+		break;
+	case SYS_PLL_PFD0:
+	case SYS_PLL_PFD0_DIV2:
+		ctrl = readl(&ana_regs->sys_pll.dfs[0].dfs_ctrl.reg);
+		break;
+	case SYS_PLL_PFD1:
+	case SYS_PLL_PFD1_DIV2:
+		ctrl = readl(&ana_regs->sys_pll.dfs[1].dfs_ctrl.reg);
+		break;
+	case SYS_PLL_PFD2:
+	case SYS_PLL_PFD2_DIV2:
+		ctrl = readl(&ana_regs->sys_pll.dfs[2].dfs_ctrl.reg);
+		break;
+	case OSC_24M_CLK:
+		return 24000;
+	default:
+		printf("Invalid clock source to get rate\n");
+		return 0;
+	}
+
+	if (ctrl & PLL_CTRL_HW_CTRL_SEL) {
+		/* When using HW ctrl, check OSCPLL */
+		clk_on = ccm_clk_src_is_clk_on(source);
+		if (clk_on)
+			return decode_pll(source);
+		else
+			return 0;
+	} else {
+		/* controlled by pll registers */
+		return decode_pll(source);
+	}
+}
+
+u32 get_arm_core_clk(void)
+{
+	u32 val;
+	ccm_shared_gpr_get(SHARED_GPR_A55_CLK, &val);
+
+	if (val & SHARED_GPR_A55_CLK_SEL_PLL)
+		return decode_pll(ARM_PLL_CLK) * 1000;
+
+	return ccm_clk_root_get_rate(ARM_A55_CLK_ROOT);
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return get_arm_core_clk();
+	case MXC_IPG_CLK:
+		return ccm_clk_root_get_rate(BUS_WAKEUP_CLK_ROOT);
+	case MXC_CSPI_CLK:
+		return ccm_clk_root_get_rate(LPSPI1_CLK_ROOT);
+	case MXC_ESDHC_CLK:
+		return ccm_clk_root_get_rate(USDHC1_CLK_ROOT);
+	case MXC_ESDHC2_CLK:
+		return ccm_clk_root_get_rate(USDHC2_CLK_ROOT);
+	case MXC_ESDHC3_CLK:
+		return ccm_clk_root_get_rate(USDHC3_CLK_ROOT);
+	case MXC_UART_CLK:
+		return ccm_clk_root_get_rate(LPUART1_CLK_ROOT);
+	case MXC_FLEXSPI_CLK:
+		return ccm_clk_root_get_rate(FLEXSPI1_CLK_ROOT);
+	default:
+		return -1;
+	};
+
+	return -1;
+};
+
+int enable_i2c_clk(unsigned char enable, u32 i2c_num)
+{
+	if (i2c_num > 7)
+		return -EINVAL;
+
+	if (enable) {
+		/* 24M */
+		ccm_lpcg_on(CCGR_I2C1 + i2c_num, false);
+		ccm_clk_root_cfg(LPI2C1_CLK_ROOT + i2c_num, OSC_24M_CLK, 1);
+		ccm_lpcg_on(CCGR_I2C1 + i2c_num, true);
+	} else {
+		ccm_lpcg_on(CCGR_I2C1 + i2c_num, false);
+	}
+
+	return 0;
+}
+
+u32 imx_get_i2cclk(u32 i2c_num)
+{
+	if (i2c_num > 7)
+		return -EINVAL;
+
+	return ccm_clk_root_get_rate(LPI2C1_CLK_ROOT + i2c_num);
+}
+
+u32 get_lpuart_clk(void)
+{
+	return mxc_get_clock(MXC_UART_CLK);
+}
+
+void init_uart_clk(u32 index)
+{
+	switch(index) {
+	case LPUART1_CLK_ROOT:
+		/* 24M */
+		ccm_lpcg_on(CCGR_URT1, false);
+		ccm_clk_root_cfg(LPUART1_CLK_ROOT, OSC_24M_CLK, 1);
+		ccm_lpcg_on(CCGR_URT1, true);
+		break;
+	default:
+		break;
+	}
+}
+
+void init_clk_usdhc(u32 index)
+{
+	/* 400 Mhz */
+	switch (index) {
+	case 0:
+		ccm_lpcg_on(CCGR_USDHC1, 0);
+		ccm_clk_root_cfg(USDHC1_CLK_ROOT, SYS_PLL_PFD1, 2);
+		ccm_lpcg_on(CCGR_USDHC1, 1);
+		break;
+	case 1:
+		ccm_lpcg_on(CCGR_USDHC2, 0);
+		ccm_clk_root_cfg(USDHC2_CLK_ROOT, SYS_PLL_PFD1, 2);
+		ccm_lpcg_on(CCGR_USDHC2, 1);
+		break;
+	case 2:
+		ccm_lpcg_on(CCGR_USDHC3, 0);
+		ccm_clk_root_cfg(USDHC3_CLK_ROOT, SYS_PLL_PFD1, 2);
+		ccm_lpcg_on(CCGR_USDHC3, 1);
+		break;
+	default:
+		return;
+	};
+}
+
+void enable_usboh3_clk(unsigned char enable)
+{
+	if (enable) {
+		ccm_clk_root_cfg(HSIO_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+		ccm_lpcg_on(CCGR_USBC, 1);
+	} else {
+		ccm_lpcg_on(CCGR_USBC, 0);
+	}
+}
+
+#ifdef CONFIG_SPL_BUILD
+void dram_pll_init(ulong pll_val)
+{
+	configure_fracpll(DRAM_PLL_CLK, pll_val);
+}
+
+void dram_enable_bypass(ulong clk_val)
+{
+	switch (clk_val) {
+	case MHZ(400):
+		ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 2);
+		break;
+	case MHZ(333):
+		ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD0, 3);
+		break;
+	case MHZ(200):
+		ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 4);
+		break;
+	case MHZ(100):
+		ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 8);
+		break;
+	default:
+		printf("No matched freq table %lu\n", clk_val);
+		return;
+	}
+
+	/* Set DRAM APB to 133Mhz */
+	ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+	/* Switch from DRAM  clock root from PLL to CCM */
+	ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_CCM);
+}
+
+void dram_disable_bypass(void)
+{
+	/* Set DRAM APB to 133Mhz */
+	ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+	/* Switch from DRAM  clock root from CCM to PLL */
+	ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_PLL);
+}
+#endif
+
+int clock_init(void)
+{
+	/* Set A55 periphal to 333M */
+	ccm_clk_root_cfg(ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3);
+	/* Set A55 mtr bus to 133M */
+	ccm_clk_root_cfg(ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+
+	/* Sentinel to 200M */
+	ccm_clk_root_cfg(SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2);
+	/* Bus_wakeup to 133M */
+	ccm_clk_root_cfg(BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+	/* Bus_AON to 133M */
+	ccm_clk_root_cfg(BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+	/* M33 to 200M */
+	ccm_clk_root_cfg(M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2);
+	/* WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for generating MII clock at 2.5M  */
+	ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2);
+	/* SWO TRACE to 133M */
+	ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+	/* M33 systetick to 133M */
+	ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+	/* NIC to 400M */
+	ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD1, 2);
+	/* NIC_APB to 133M */
+	ccm_clk_root_cfg(NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+
+	/* allow for non-secure access */
+	int i;
+	for (i = 0; i < OSCPLL_END; i++)
+		ccm_clk_src_tz_access(i, true, false, false);
+
+	for (i = 0; i < CLK_ROOT_NUM; i++)
+		ccm_clk_root_tz_access(i, true, false, false);
+
+	for (i = 0; i < CCGR_NUM; i++)
+		ccm_lpcg_tz_access(i, true, false, false);
+
+	for (i = 0; i < SHARED_GPR_NUM; i++)
+		ccm_shared_gpr_tz_access(i, true, false, false);
+
+	return 0;
+}
+
+int set_clk_eqos(enum enet_freq type)
+{
+	u32 eqos_post_div;
+
+	switch (type) {
+	case ENET_125MHZ:
+		eqos_post_div = 2; /* 250M clock */
+		break;
+	case ENET_50MHZ:
+		eqos_post_div = 5; /* 100M clock */
+		break;
+	case ENET_25MHZ:
+		eqos_post_div = 10; /* 50M clock*/
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* disable the clock first */
+	ccm_lpcg_on(CCGR_ENETQOS, false);
+
+	ccm_clk_root_cfg(ENET_CLK_ROOT, SYS_PLL_PFD0_DIV2, eqos_post_div);
+	ccm_clk_root_cfg(ENET_TIMER2_CLK_ROOT, SYS_PLL_PFD0_DIV2, 5);
+
+	/* enable clock */
+	ccm_lpcg_on(CCGR_ENETQOS, true);
+
+	return 0;
+}
+
+u32 imx_get_eqos_csr_clk(void)
+{
+	return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT);
+}
+
+u32 imx_get_fecclk(void)
+{
+	return ccm_clk_root_get_rate(WAKEUP_AXI_CLK_ROOT);
+}
+
+int set_clk_enet(enum enet_freq type)
+{
+	u32 div;
+
+	/* disable the clock first */
+	ccm_lpcg_on(CCGR_ENET1, false);
+
+	switch (type) {
+	case ENET_125MHZ:
+		div = 2; /* 250Mhz */
+		break;
+	case ENET_50MHZ:
+		div = 5; /* 100Mhz */
+		break;
+	case ENET_25MHZ:
+		div = 10; /* 50Mhz */
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	ccm_clk_root_cfg(ENET_REF_CLK_ROOT, SYS_PLL_PFD0_DIV2, div);
+	ccm_clk_root_cfg(ENET_TIMER1_CLK_ROOT, SYS_PLL_PFD0_DIV2, 5);
+
+#ifdef CONFIG_FEC_MXC_25M_REF_CLK
+	ccm_clk_root_cfg(ENET_REF_PHY_CLK_ROOT, SYS_PLL_PFD0_DIV2, 20);
+#endif
+
+	/* enable clock */
+	ccm_lpcg_on(CCGR_ENET1, true);
+
+	return 0;
+}
+
+void mxs_set_lcdclk(u32 base_addr, u32 freq)
+{
+	u32 div, i, krate, temp;
+	u32 best = 0, best_div = 0, best_pll = 0;
+
+	debug("%s to set rate to %dkhz\n", __func__, freq);
+
+	for (i = 0; i < ARRAY_SIZE(imx9_fracpll_tbl); i++) {
+		krate = imx9_fracpll_tbl[i].rate / 1000;
+		div = (krate + freq - 1) / freq;
+
+		if (div > 256)
+			continue;
+
+		temp = krate / div;
+		if (best == 0 || temp > best) {
+			best = temp;
+			best_div = div;
+			best_pll = imx9_fracpll_tbl[i].rate;
+		}
+	}
+
+	if (best == 0) {
+		printf("Can't find parent clock for LCDIF, target freq: %u\n", freq);
+		return;
+	}
+
+	/* Select to video PLL */
+	debug("%s, best_pll = %u, div = %u\n", __func__, best_pll, best_div);
+
+	configure_fracpll(VIDEO_PLL_CLK, best_pll);
+	ccm_clk_root_cfg(MEDIA_DISP_PIX_CLK_ROOT, VIDEO_PLL_CLK, best_div);
+}
+
+/*
+ * Dump some clockes.
+ */
+#ifndef CONFIG_SPL_BUILD
+int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+	u32 freq;
+
+	freq = decode_pll(ARM_PLL_CLK);
+	printf("ARM_PLL    %8d MHz\n", freq / 1000);
+	freq = decode_pll(DRAM_PLL_CLK);
+	printf("DRAM_PLL    %8d MHz\n", freq / 1000);
+	freq = decode_pll(SYS_PLL_PFD0);
+	printf("SYS_PLL_PFD0    %8d MHz\n", freq / 1000);
+	freq = decode_pll(SYS_PLL_PFD0_DIV2);
+	printf("SYS_PLL_PFD0_DIV2    %8d MHz\n", freq / 1000);
+	freq = decode_pll(SYS_PLL_PFD1);
+	printf("SYS_PLL_PFD1    %8d MHz\n", freq / 1000);
+	freq = decode_pll(SYS_PLL_PFD1_DIV2);
+	printf("SYS_PLL_PFD1_DIV2    %8d MHz\n", freq / 1000);
+	freq = decode_pll(SYS_PLL_PFD2);
+	printf("SYS_PLL_PFD2    %8d MHz\n", freq / 1000);
+	freq = decode_pll(SYS_PLL_PFD2_DIV2);
+	printf("SYS_PLL_PFD2_DIV2    %8d MHz\n", freq / 1000);
+	freq = mxc_get_clock(MXC_ARM_CLK);
+	printf("ARM CORE    %8d MHz\n", freq / 1000000);
+	freq = mxc_get_clock(MXC_IPG_CLK);
+	printf("IPG    		%8d MHz\n", freq / 1000000);
+	freq = mxc_get_clock(MXC_UART_CLK);
+	printf("UART3          %8d MHz\n", freq / 1000000);
+	freq = mxc_get_clock(MXC_ESDHC_CLK);
+	printf("USDHC1         %8d MHz\n", freq / 1000000);
+	freq = mxc_get_clock(MXC_FLEXSPI_CLK);
+	printf("FLEXSPI           %8d MHz\n", freq / 1000000);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	clocks,	CONFIG_SYS_MAXARGS, 1, do_showclocks,
+	"display clocks",
+	""
+);
+#endif
+
diff --git a/arch/arm/mach-imx/imx9/clock_root.c b/arch/arm/mach-imx/imx9/clock_root.c
new file mode 100644
index 00000000000..5748e28ff06
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/clock_root.c
@@ -0,0 +1,450 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/ccm_regs.h>
+#include <asm/global_data.h>
+#include <linux/iopoll.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
+
+static enum ccm_clk_src clk_root_mux[][4] = {
+	{ OSC_24M_CLK,	SYS_PLL_PFD0,		SYS_PLL_PFD1,		SYS_PLL_PFD2      }, /* bus */
+	{ OSC_24M_CLK,	SYS_PLL_PFD0_DIV2,	SYS_PLL_PFD1_DIV2,	SYS_PLL_PFD2_DIV2 }, /* non-IO */
+	{ OSC_24M_CLK,	SYS_PLL_PFD0_DIV2,	SYS_PLL_PFD1_DIV2,	VIDEO_PLL_CLK     }, /* IO*/
+	{ OSC_24M_CLK,	SYS_PLL_PFD0,		AUDIO_PLL_CLK,		EXT_CLK           }, /* TPM */
+	{ OSC_24M_CLK,	AUDIO_PLL_CLK,		VIDEO_PLL_CLK,		EXT_CLK           }, /* Audio */
+	{ OSC_24M_CLK,	AUDIO_PLL_CLK,		VIDEO_PLL_CLK,		SYS_PLL_PFD0      }, /* Video */
+	{ OSC_24M_CLK,	SYS_PLL_PFD0,		SYS_PLL_PFD1,		AUDIO_PLL_CLK     }, /* CKO1 */
+	{ OSC_24M_CLK,	SYS_PLL_PFD0,		SYS_PLL_PFD1,		VIDEO_PLL_CLK     }, /* CKO2 */
+	{ OSC_24M_CLK,	AUDIO_PLL_CLK,		VIDEO_PLL_CLK,		SYS_PLL_PFD2      }, /* CAMSCAN */
+};
+
+static struct clk_root_map clk_root_array[] = {
+	{ ARM_A55_PERIPH_CLK_ROOT, 	0 },
+	{ ARM_A55_MTR_BUS_CLK_ROOT, 2 },
+	{ ARM_A55_CLK_ROOT, 		0 },
+	{ M33_CLK_ROOT, 			2 },
+	{ SENTINEL_CLK_ROOT, 		2 },
+	{ BUS_WAKEUP_CLK_ROOT, 		2 },
+	{ BUS_AON_CLK_ROOT, 		2 },
+	{ WAKEUP_AXI_CLK_ROOT, 		0 },
+	{ SWO_TRACE_CLK_ROOT, 		2 },
+	{ M33_SYSTICK_CLK_ROOT, 	2 },
+	{ FLEXIO1_CLK_ROOT, 		2 },
+	{ FLEXIO2_CLK_ROOT, 		2 },
+	{ LPIT1_CLK_ROOT, 			2 },
+	{ LPIT2_CLK_ROOT, 			2 },
+	{ LPTMR1_CLK_ROOT, 			2 },
+	{ LPTMR2_CLK_ROOT,			2 },
+	{ TPM1_CLK_ROOT,			3 },
+	{ TPM2_CLK_ROOT,			3 },
+	{ TPM3_CLK_ROOT,			3 },
+	{ TPM4_CLK_ROOT,			3 },
+	{ TPM5_CLK_ROOT,			3 },
+	{ TPM6_CLK_ROOT,			3 },
+	{ FLEXSPI1_CLK_ROOT,		0 },
+	{ CAN1_CLK_ROOT,			2 },
+	{ CAN2_CLK_ROOT,			2 },
+	{ LPUART1_CLK_ROOT,			2 },
+	{ LPUART2_CLK_ROOT,			2 },
+	{ LPUART3_CLK_ROOT,			2 },
+	{ LPUART4_CLK_ROOT,			2 },
+	{ LPUART5_CLK_ROOT,			2 },
+	{ LPUART6_CLK_ROOT,			2 },
+	{ LPUART7_CLK_ROOT,			2 },
+	{ LPUART8_CLK_ROOT,			2 },
+	{ LPI2C1_CLK_ROOT,			2 },
+	{ LPI2C2_CLK_ROOT,			2 },
+	{ LPI2C3_CLK_ROOT,			2 },
+	{ LPI2C4_CLK_ROOT,			2 },
+	{ LPI2C5_CLK_ROOT,			2 },
+	{ LPI2C6_CLK_ROOT,			2 },
+	{ LPI2C7_CLK_ROOT,			2 },
+	{ LPI2C8_CLK_ROOT,			2 },
+	{ LPSPI1_CLK_ROOT,			2 },
+	{ LPSPI2_CLK_ROOT,			2 },
+	{ LPSPI3_CLK_ROOT,			2 },
+	{ LPSPI4_CLK_ROOT,			2 },
+	{ LPSPI5_CLK_ROOT,			2 },
+	{ LPSPI6_CLK_ROOT,			2 },
+	{ LPSPI7_CLK_ROOT,			2 },
+	{ LPSPI8_CLK_ROOT,			2 },
+	{ I3C1_CLK_ROOT,			2 },
+	{ I3C2_CLK_ROOT,			2 },
+	{ USDHC1_CLK_ROOT,			0 },
+	{ USDHC2_CLK_ROOT,			0 },
+	{ USDHC3_CLK_ROOT,			0 },
+	{ SAI1_CLK_ROOT,			4 },
+	{ SAI2_CLK_ROOT,			4 },
+	{ SAI3_CLK_ROOT,			4 },
+	{ CCM_CKO1_CLK_ROOT,		6 },
+	{ CCM_CKO2_CLK_ROOT,		7 },
+	{ CCM_CKO3_CLK_ROOT,		6 },
+	{ CCM_CKO4_CLK_ROOT,		7 },
+	{ HSIO_CLK_ROOT,			2 },
+	{ HSIO_USB_TEST_60M_CLK_ROOT,	2 },
+	{ HSIO_ACSCAN_80M_CLK_ROOT,		2 },
+	{ HSIO_ACSCAN_480M_CLK_ROOT,	0 },
+	{ NIC_CLK_ROOT,				0 },
+	{ NIC_APB_CLK_ROOT,			2 },
+	{ ML_APB_CLK_ROOT,			2 },
+	{ ML_CLK_ROOT, 				0 },
+	{ MEDIA_AXI_CLK_ROOT,		0 },
+	{ MEDIA_APB_CLK_ROOT,		2 },
+	{ MEDIA_LDB_CLK_ROOT,		5 },
+	{ MEDIA_DISP_PIX_CLK_ROOT,	5 },
+	{ CAM_PIX_CLK_ROOT,			5 },
+	{ MIPI_TEST_BYTE_CLK_ROOT,	5 },
+	{ MIPI_PHY_CFG_CLK_ROOT,	5 },
+	{ DRAM_ALT_CLK_ROOT,		0 },
+	{ DRAM_APB_CLK_ROOT,		1 },
+	{ ADC_CLK_ROOT,				2 },
+	{ PDM_CLK_ROOT,				4 },
+	{ TSTMR1_CLK_ROOT,			2 },
+	{ TSTMR2_CLK_ROOT,			2 },
+	{ MQS1_CLK_ROOT,			4 },
+	{ MQS2_CLK_ROOT,			4 },
+	{ AUDIO_XCVR_CLK_ROOT,		1 },
+	{ SPDIF_CLK_ROOT,			4 },
+	{ ENET_CLK_ROOT,			1 },
+	{ ENET_TIMER1_CLK_ROOT,		2 },
+	{ ENET_TIMER2_CLK_ROOT,		2 },
+	{ ENET_REF_CLK_ROOT,		1 },
+	{ ENET_REF_PHY_CLK_ROOT,	2 },
+	{ I3C1_SLOW_CLK_ROOT,		2 },
+	{ I3C2_SLOW_CLK_ROOT,		2 },
+	{ USB_PHY_BURUNIN_CLK_ROOT, 2 },
+	{ PAL_CAME_SCAN_CLK_ROOT, 	8 },
+};
+
+int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable)
+{
+	u32 authen;
+
+	if (oscpll >= OSCPLL_END)
+		return -EINVAL;
+
+	authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
+
+	/* If using cpulpm, need disable it first */
+	if (authen & CCM_AUTHEN_CPULPM_MODE)
+		return -EPERM;
+
+	if (enable)
+		writel(1, &ccm_reg->clk_oscplls[oscpll].direct);
+	else
+		writel(0, &ccm_reg->clk_oscplls[oscpll].direct);
+
+	return 0;
+}
+
+/* auto mode, enable =  DIRECT[ON] | STATUS0[IN_USE] */
+int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable)
+{
+	u32 authen;
+
+	if (oscpll >= OSCPLL_END)
+		return -EINVAL;
+
+	authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
+
+	/* AUTO CTRL and CPULPM are mutual exclusion, need disable CPULPM first */
+	if (authen & CCM_AUTHEN_CPULPM_MODE)
+		return -EPERM;
+
+	if (enable) {
+		writel(authen | CCM_AUTHEN_AUTO_CTRL,
+			&ccm_reg->clk_oscplls[oscpll].authen);
+	} else
+		writel((authen & ~CCM_AUTHEN_AUTO_CTRL),
+			&ccm_reg->clk_oscplls[oscpll].authen);
+
+	return 0;
+}
+
+int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable)
+{
+	u32 authen;
+
+	if (oscpll >= OSCPLL_END)
+		return -EINVAL;
+
+	authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
+
+	/* AUTO CTRL and CPULPM are mutual exclusion, need disable AUTO CTRL first */
+	if (authen & CCM_AUTHEN_AUTO_CTRL)
+		return -EPERM;
+
+	if (enable)
+		writel(authen | CCM_AUTHEN_CPULPM_MODE,
+			&ccm_reg->clk_oscplls[oscpll].authen);
+	else
+		writel((authen & ~CCM_AUTHEN_CPULPM_MODE),
+			&ccm_reg->clk_oscplls[oscpll].authen);
+
+	return 0;
+}
+
+int ccm_clk_src_config_lpm(enum ccm_clk_src oscpll, u32 domain, u32 lpm_val)
+{
+	u32 lpm, authen;
+
+	if (oscpll >= OSCPLL_END || domain >= 16)
+		return -EINVAL;
+
+	authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
+	if (!(authen & CCM_AUTHEN_CPULPM_MODE))
+		return -EPERM;
+
+	if (domain > 7) {
+		lpm = readl(&ccm_reg->clk_oscplls[oscpll].lpm1);
+		lpm &= ~(0x3 << ((domain - 8) * 4));
+		lpm |= (lpm_val & 0x3) << ((domain - 8) * 4);
+		writel(lpm, &ccm_reg->clk_oscplls[oscpll].lpm1);
+	} else {
+		lpm = readl(&ccm_reg->clk_oscplls[oscpll].lpm0);
+		lpm &= ~(0x3 << (domain * 4));
+		lpm |= (lpm_val & 0x3) << (domain * 4);
+		writel(lpm, &ccm_reg->clk_oscplls[oscpll].lpm0);
+	}
+
+	return 0;
+}
+
+bool ccm_clk_src_is_clk_on(enum ccm_clk_src oscpll)
+{
+	return !!(readl(&ccm_reg->clk_oscplls[oscpll].status0) & 0x1);
+}
+
+int ccm_clk_src_tz_access(enum ccm_clk_src oscpll,
+	bool non_secure, bool user_mode, bool lock_tz)
+{
+	u32 authen;
+
+	if (oscpll >= OSCPLL_END)
+		return -EINVAL;
+
+	authen = readl(&ccm_reg->clk_oscplls[oscpll].authen);
+
+	authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0;
+	authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0;
+	authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0;
+
+	writel(authen, &ccm_reg->clk_oscplls[oscpll].authen);
+
+	return 0;
+}
+
+int ccm_clk_root_cfg(u32 clk_root_id, enum ccm_clk_src src, u32 div)
+{
+	int i;
+	int ret;
+	u32 mux, status;
+
+	if (clk_root_id >= CLK_ROOT_NUM || div > 256 || div == 0)
+		return -EINVAL;
+
+	mux = clk_root_array[clk_root_id].mux_type;
+
+	for (i = 0; i < 4; i++) {
+		if (src == clk_root_mux[mux][i])
+			break;
+	}
+
+	if (i == 4) {
+		printf("Invalid source [%u] for this clk root\n", src);
+		return -EINVAL;
+	}
+
+	writel((i << 8) | (div - 1), &ccm_reg->clk_roots[clk_root_id].control);
+
+	ret = readl_poll_timeout(&ccm_reg->clk_roots[clk_root_id].status0, status,
+				 !(status & CLK_ROOT_STATUS_CHANGING), 200000);
+	if (ret)
+		printf("%s: failed, status: 0x%x\n", __func__,
+			readl(&ccm_reg->clk_roots[clk_root_id].status0));
+
+	return ret;
+};
+
+u32 ccm_clk_root_get_rate(u32 clk_root_id)
+{
+	u32 mux, status, div, rate;
+	enum ccm_clk_src src;
+
+	if (clk_root_id >= CLK_ROOT_NUM)
+		return 0;
+
+	status = readl(&ccm_reg->clk_roots[clk_root_id].control);
+
+	if (status & CLK_ROOT_STATUS_OFF)
+		return 0; /* clock is off */
+
+	mux = (status & CLK_ROOT_MUX_MASK) >> CLK_ROOT_MUX_SHIFT;
+	div = status & CLK_ROOT_DIV_MASK;
+	src = clk_root_mux[clk_root_array[clk_root_id].mux_type][mux];
+
+	rate = get_clk_src_rate(src) * 1000;
+
+	return rate / (div + 1); /* return in hz */
+}
+
+int ccm_clk_root_tz_access(u32 clk_root_id,
+	bool non_secure, bool user_mode, bool lock_tz)
+{
+	u32 authen;
+
+	if (clk_root_id >= CLK_ROOT_NUM)
+		return -EINVAL;
+
+	authen = readl(&ccm_reg->clk_roots[clk_root_id].authen);
+
+	authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0;
+	authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0;
+	authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0;
+
+	writel(authen, &ccm_reg->clk_roots[clk_root_id].authen);
+
+	return 0;
+}
+
+int ccm_lpcg_on(u32 lpcg, bool enable)
+{
+	u32 authen;
+
+	if (lpcg >= CCGR_NUM)
+		return -EINVAL;
+
+	authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen);
+
+	/* If using cpulpm, need disable it first */
+	if (authen & CCM_AUTHEN_CPULPM_MODE)
+		return -EPERM;
+
+	if (enable)
+		writel(1, &ccm_reg->clk_lpcgs[lpcg].direct);
+	else
+		writel(0, &ccm_reg->clk_lpcgs[lpcg].direct);
+
+	return 0;
+
+}
+
+int ccm_lpcg_lpm(u32 lpcg, bool enable)
+{
+	u32 authen;
+
+	if (lpcg >= CCGR_NUM)
+		return -EINVAL;
+
+	authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen);
+
+	if (enable)
+		writel(authen | CCM_AUTHEN_CPULPM_MODE,
+			&ccm_reg->clk_lpcgs[lpcg].authen);
+	else
+		writel((authen & ~CCM_AUTHEN_CPULPM_MODE),
+			&ccm_reg->clk_lpcgs[lpcg].authen);
+
+	return 0;
+}
+
+int ccm_lpcg_config_lpm(u32 lpcg, u32 domain, u32 lpm_val)
+{
+	u32 lpm, authen;
+
+	if (lpcg >= CCGR_NUM || domain >= 16)
+		return -EINVAL;
+
+	authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen);
+	if (!(authen & CCM_AUTHEN_CPULPM_MODE))
+		return -EPERM;
+
+	if (domain > 7) {
+		lpm = readl(&ccm_reg->clk_lpcgs[lpcg].lpm1);
+		lpm &= ~(0x3 << ((domain - 8) * 4));
+		lpm |= (lpm_val & 0x3) << ((domain - 8) * 4);
+		writel(lpm, &ccm_reg->clk_lpcgs[lpcg].lpm1);
+	} else {
+		lpm = readl(&ccm_reg->clk_lpcgs[lpcg].lpm0);
+		lpm &= ~(0x3 << (domain * 4));
+		lpm |= (lpm_val & 0x3) << (domain * 4);
+		writel(lpm, &ccm_reg->clk_lpcgs[lpcg].lpm0);
+	}
+
+	return 0;
+}
+
+bool ccm_lpcg_is_clk_on(u32 lpcg)
+{
+	return !!(readl(&ccm_reg->clk_lpcgs[lpcg].status0) & 0x1);
+}
+
+int ccm_lpcg_tz_access(u32 lpcg,
+	bool non_secure, bool user_mode, bool lock_tz)
+{
+	u32 authen;
+
+	if (lpcg >= CCGR_NUM)
+		return -EINVAL;
+
+	authen = readl(&ccm_reg->clk_lpcgs[lpcg].authen);
+
+	authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0;
+	authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0;
+	authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0;
+
+	writel(authen, &ccm_reg->clk_lpcgs[lpcg].authen);
+
+	return 0;
+}
+
+int ccm_shared_gpr_set(u32 gpr, u32 val)
+{
+	if (gpr >= SHARED_GPR_NUM)
+		return -EINVAL;
+
+	writel(val, &ccm_reg->clk_shared_gpr[gpr].gpr);
+
+	return 0;
+}
+
+int ccm_shared_gpr_get(u32 gpr, u32 *val)
+{
+	if (gpr >= SHARED_GPR_NUM || !val)
+		return -EINVAL;
+
+	*val = readl(&ccm_reg->clk_shared_gpr[gpr].gpr);
+
+	return 0;
+}
+
+
+int ccm_shared_gpr_tz_access(u32 gpr,
+	bool non_secure, bool user_mode, bool lock_tz)
+{
+	u32 authen;
+
+	if (gpr >= SHARED_GPR_NUM)
+		return -EINVAL;
+
+	authen = readl(&ccm_reg->clk_shared_gpr[gpr].authen);
+
+	authen |= non_secure ? CCM_AUTHEN_TZ_NS : 0;
+	authen |= user_mode ? CCM_AUTHEN_TZ_USER : 0;
+	authen |= lock_tz ? CCM_AUTHEN_LOCK_TZ : 0;
+
+	writel(authen, &ccm_reg->clk_shared_gpr[gpr].authen);
+
+	return 0;
+}
diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c b/arch/arm/mach-imx/imx9/imx_bootaux.c
new file mode 100644
index 00000000000..721e77193e3
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/imx_bootaux.c
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/mach-imx/sys_proto.h>
+#include <command.h>
+#include <elf.h>
+#include <imx_sip.h>
+#include <linux/arm-smccc.h>
+#include <linux/compiler.h>
+#include <cpu_func.h>
+
+int arch_auxiliary_core_check_up(u32 core_id)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0,
+		      0, 0, 0, 0, &res);
+
+	return res.a0;
+}
+
+int arch_auxiliary_core_down(u32 core_id)
+{
+	struct arm_smccc_res res;
+
+	printf("## Stopping auxiliary core\n");
+
+	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STOP, 0, 0,
+		      0, 0, 0, 0, &res);
+
+	return 0;
+}
+
+int arch_auxiliary_core_up(u32 core_id, ulong addr)
+{
+	struct arm_smccc_res res;
+	u32 stack, pc;
+
+	if (!addr)
+		return -EINVAL;
+
+	stack = *(u32 *)addr;
+	pc = *(u32 *)(addr + 4);
+
+	printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n", stack, pc);
+
+	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, 0, 0,
+		      0, 0, 0, 0, &res);
+
+	return 0;
+}
+
+/*
+ * To i.MX6SX and i.MX7D, the image supported by bootaux needs
+ * the reset vector at the head for the image, with SP and PC
+ * as the first two words.
+ *
+ * Per the cortex-M reference manual, the reset vector of M4/M7 needs
+ * to exist at 0x0 (TCMUL/IDTCM). The PC and SP are the first two addresses
+ * of that vector.  So to boot M4/M7, the A core must build the M4/M7's reset
+ * vector with getting the PC and SP from image and filling them to
+ * TCMUL/IDTCM. When M4/M7 is kicked, it will load the PC and SP by itself.
+ * The TCMUL/IDTCM is mapped to (MCU_BOOTROM_BASE_ADDR) at A core side for
+ * accessing the M4/M7 TCMUL/IDTCM.
+ */
+static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
+		      char *const argv[])
+{
+	ulong addr;
+	int ret, up;
+	u32 core = 0;
+	u32 stop = 0;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	if (argc > 2)
+		core = simple_strtoul(argv[2], NULL, 10);
+
+	if (argc > 3)
+		stop = simple_strtoul(argv[3], NULL, 10);
+
+	up = arch_auxiliary_core_check_up(core);
+	if (up) {
+		printf("## Auxiliary core is already up\n");
+		return CMD_RET_SUCCESS;
+	}
+
+	addr = simple_strtoul(argv[1], NULL, 16);
+
+	if (!addr)
+		return CMD_RET_FAILURE;
+
+	ret = arch_auxiliary_core_up(core, addr);
+	if (ret)
+		return CMD_RET_FAILURE;
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_stopaux(struct cmd_tbl *cmdtp, int flag, int argc,
+		      char *const argv[])
+{
+	int ret, up;
+
+	up = arch_auxiliary_core_check_up(0);
+	if (!up) {
+		printf("## Auxiliary core is already down\n");
+		return CMD_RET_SUCCESS;
+	}
+
+	ret = arch_auxiliary_core_down(0);
+	if (ret)
+		return CMD_RET_FAILURE;
+
+	return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+	stopaux, CONFIG_SYS_MAXARGS, 1,	do_stopaux,
+	"Start auxiliary core",
+	"<address> [<core>]\n"
+	"   - start auxiliary core [<core>] (default 0),\n"
+	"     at address <address>\n"
+);
+
+U_BOOT_CMD(
+	bootaux, CONFIG_SYS_MAXARGS, 1,	do_bootaux,
+	"Start auxiliary core",
+	"<address> [<core>]\n"
+	"   - start auxiliary core [<core>] (default 0),\n"
+	"     at address <address>\n"
+);
diff --git a/arch/arm/mach-imx/imx9/lowlevel_init.S b/arch/arm/mach-imx/imx9/lowlevel_init.S
new file mode 100644
index 00000000000..1dc1dbfcddc
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/lowlevel_init.S
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <config.h>
+
+.align 8
+.global rom_pointer
+rom_pointer:
+	.space 256
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ */
+
+.global save_boot_params
+save_boot_params:
+#ifndef CONFIG_SPL_BUILD
+	/* The firmware provided ATAG/FDT address can be found in r2/x0 */
+	adr	x0, rom_pointer
+	stp	x1, x2, [x0], #16
+	stp	x3, x4, [x0], #16
+#endif
+	/* Returns */
+	b	save_boot_params_ret
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
new file mode 100644
index 00000000000..2b3f52038c4
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -0,0 +1,576 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <log.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ccm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/trdc.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/syscounter.h>
+#include <asm/armv8/mmu.h>
+#include <dm/uclass.h>
+#include <env.h>
+#include <env_internal.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <linux/bitops.h>
+#include <asm/setup.h>
+#include <asm/bootm.h>
+#include <asm/arch-imx/cpu.h>
+#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/optee.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rom_api *g_rom_api = (struct rom_api *)0x1980;
+
+enum boot_device get_boot_device(void)
+{
+	volatile gd_t *pgd = gd;
+	int ret;
+	u32 boot;
+	u16 boot_type;
+	u8 boot_instance;
+	enum boot_device boot_dev = SD1_BOOT;
+
+	ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
+					  ((uintptr_t)&boot) ^ QUERY_BT_DEV);
+	set_gd(pgd);
+
+	if (ret != ROM_API_OKAY) {
+		puts("ROMAPI: failure at query_boot_info\n");
+		return -1;
+	}
+
+	boot_type = boot >> 16;
+	boot_instance = (boot >> 8) & 0xff;
+
+	switch (boot_type) {
+	case BT_DEV_TYPE_SD:
+		boot_dev = boot_instance + SD1_BOOT;
+		break;
+	case BT_DEV_TYPE_MMC:
+		boot_dev = boot_instance + MMC1_BOOT;
+		break;
+	case BT_DEV_TYPE_NAND:
+		boot_dev = NAND_BOOT;
+		break;
+	case BT_DEV_TYPE_FLEXSPINOR:
+		boot_dev = QSPI_BOOT;
+		break;
+	case BT_DEV_TYPE_USB:
+		boot_dev = boot_instance + USB_BOOT;
+		break;
+	default:
+		break;
+	}
+
+	debug("boot dev %d\n", boot_dev);
+
+	return boot_dev;
+}
+
+bool is_usb_boot(void)
+{
+	enum boot_device bt_dev = get_boot_device();
+	return (bt_dev == USB_BOOT || bt_dev == USB2_BOOT);
+}
+
+void disconnect_from_pc(void)
+{
+	enum boot_device bt_dev = get_boot_device();
+
+	if (bt_dev == USB_BOOT)
+		writel(0x0, USB1_BASE_ADDR + 0x140);
+	else if (bt_dev == USB2_BOOT)
+		writel(0x0, USB2_BASE_ADDR + 0x140);
+
+	return;
+}
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+__weak int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int mmc_get_env_dev(void)
+{
+	volatile gd_t *pgd = gd;
+	int ret;
+	u32 boot;
+	u16 boot_type;
+	u8 boot_instance;
+
+	ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
+					  ((uintptr_t)&boot) ^ QUERY_BT_DEV);
+	set_gd(pgd);
+
+	if (ret != ROM_API_OKAY) {
+		puts("ROMAPI: failure at query_boot_info\n");
+		return CONFIG_SYS_MMC_ENV_DEV;
+	}
+
+	boot_type = boot >> 16;
+	boot_instance = (boot >> 8) & 0xff;
+
+	debug("boot_type %d, instance %d\n", boot_type, boot_instance);
+
+	/* If not boot from sd/mmc, use default value */
+	if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
+		return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV);
+
+	return board_mmc_get_env_dev(boot_instance);
+
+}
+#endif
+
+#ifdef CONFIG_USB_PORT_AUTO
+int board_usb_gadget_port_auto(void)
+{
+    enum boot_device bt_dev = get_boot_device();
+	int usb_boot_index = 0;
+
+	if (bt_dev == USB2_BOOT)
+		usb_boot_index = 1;
+
+	printf("auto usb %d\n", usb_boot_index);
+
+	return usb_boot_index;
+}
+#endif
+
+static void set_cpu_info(struct sentinel_get_info_data *info)
+{
+	gd->arch.soc_rev = info->soc;
+	gd->arch.lifecycle = info->lc;
+	memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32));
+}
+
+u32 get_cpu_rev(void)
+{
+	u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
+	return (MXC_CPU_IMX93 << 12) | (CHIP_REV_1_0 + rev);
+}
+
+#define UNLOCK_WORD 0xD928C520 /* unlock word */
+#define REFRESH_WORD 0xB480A602 /* refresh word */
+
+static void disable_wdog(void __iomem *wdog_base)
+{
+	u32 val_cs = readl(wdog_base + 0x00);
+
+	if (!(val_cs & 0x80))
+		return;
+
+	/* default is 32bits cmd */
+	writel(REFRESH_WORD, (wdog_base + 0x04)); /* Refresh the CNT */
+
+	if (!(val_cs & 0x800)) {
+		writel(UNLOCK_WORD, (wdog_base + 0x04));
+		while (!(readl(wdog_base + 0x00) & 0x800))
+			;
+	}
+	writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
+	writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
+	writel(0x2120, (wdog_base + 0x00)); /* Disable it and set update */
+
+	while (!(readl(wdog_base + 0x00) & 0x400))
+		;
+}
+
+void init_wdog(void)
+{
+	u32 src_val;
+
+	disable_wdog((void __iomem *)WDG3_BASE_ADDR);
+	disable_wdog((void __iomem *)WDG4_BASE_ADDR);
+	disable_wdog((void __iomem *)WDG5_BASE_ADDR);
+
+	src_val = readl(0x54460018); /* reset mask */
+	src_val &= ~0x1c;
+	writel(src_val, 0x54460018);
+}
+
+static struct mm_region imx93_mem_map[] = {
+	{
+		/* ROM */
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x100000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		/* TCM */
+		.virt = 0x201c0000UL,
+		.phys = 0x201c0000UL,
+		.size = 0x80000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* OCRAM */
+		.virt = 0x20480000UL,
+		.phys = 0x20480000UL,
+		.size = 0xA0000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		/* AIPS */
+		.virt = 0x40000000UL,
+		.phys = 0x40000000UL,
+		.size = 0x40000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* Flexible Serial Peripheral Interface */
+		.virt = 0x28000000UL,
+		.phys = 0x28000000UL,
+		.size = 0x30000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* DRAM1 */
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = PHYS_SDRAM_SIZE,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		/* empty entrie to split table entry 5 if needed when TEEs are used */
+		0,
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = imx93_mem_map;
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	mac[0] = 0x1;
+	mac[1] = 0x2;
+	mac[2] = 0x3;
+	mac[3] = 0x4;
+	mac[4] = 0x5;
+	mac[5] = 0x6;
+}
+
+int print_cpuinfo(void)
+{
+	u32 cpurev;
+
+	cpurev = get_cpu_rev();
+
+	printf("CPU:   i.MX93 rev%d.%d\n", (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0);
+
+	return 0;
+
+}
+
+int arch_misc_init(void)
+{
+	return 0;
+}
+
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+	return ft_add_optee_node(blob, bd);
+}
+
+#if defined(CONFIG_SERIAL_TAG) || defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	printf("UID: 0x%x 0x%x 0x%x 0x%x\n",
+		gd->arch.uid[0], gd->arch.uid[1], gd->arch.uid[2], gd->arch.uid[3]);
+
+	serialnr->low = gd->arch.uid[0];
+	serialnr->high = gd->arch.uid[3];
+}
+#endif
+
+int arch_cpu_init(void)
+{
+	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+		/* Disable wdog */
+		init_wdog();
+
+		clock_init();
+
+		trdc_early_init();
+	}
+
+	return 0;
+}
+
+int arch_cpu_init_dm(void)
+{
+	struct udevice *devp;
+	int node, ret;
+	u32 res;
+	struct sentinel_get_info_data info;
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx93-mu-s4");
+
+	ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
+	if (ret)
+		return ret;
+
+	ret = ahab_get_info(&info, &res);
+	if (ret)
+		return ret;
+
+	set_cpu_info(&info);
+
+	return 0;
+}
+
+#ifdef CONFIG_ARCH_EARLY_INIT_R
+int arch_early_init_r(void)
+{
+	struct udevice *devp;
+	int node, ret;
+
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx93-mu-s4");
+
+	ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
+	if (ret) {
+		printf("could not get S400 mu %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+#endif
+
+int timer_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
+	unsigned long freq = readl(&sctr->cntfid0);
+
+	/* Update with accurate clock frequency */
+	asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
+
+	clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
+			SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
+#endif
+
+	gd->arch.tbl = 0;
+	gd->arch.tbu = 0;
+
+	return 0;
+}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	enum boot_device dev = get_boot_device();
+	enum env_location env_loc = ENVL_UNKNOWN;
+
+	if (prio)
+		return env_loc;
+
+	switch (dev) {
+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+	case QSPI_BOOT:
+		env_loc = ENVL_SPI_FLASH;
+		break;
+#endif
+#ifdef CONFIG_ENV_IS_IN_MMC
+	case SD1_BOOT:
+	case SD2_BOOT:
+	case SD3_BOOT:
+	case MMC1_BOOT:
+	case MMC2_BOOT:
+	case MMC3_BOOT:
+		env_loc =  ENVL_MMC;
+		break;
+#endif
+	default:
+#if defined(CONFIG_ENV_IS_NOWHERE)
+		env_loc = ENVL_NOWHERE;
+#endif
+		break;
+	}
+
+	return env_loc;
+}
+
+int mix_power_init(enum mix_power_domain pd)
+{
+	enum src_mix_slice_id mix_id;
+	enum src_mem_slice_id mem_id;
+	struct src_mix_slice_regs *mix_regs;
+	struct src_mem_slice_regs *mem_regs;
+	struct src_general_regs *global_regs;
+	u32 scr, val;
+
+	switch (pd) {
+	case MIX_PD_MEDIAMIX:
+		mix_id = SRC_MIX_MEDIA;
+		mem_id = SRC_MEM_MEDIA;
+		scr = BIT(5);
+
+		/* Enable S400 handshake */
+		struct blk_ctrl_s_aonmix_regs *s_regs =
+			(struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
+
+		setbits_le32(&s_regs->lp_handshake[0], BIT(13));
+		break;
+	case MIX_PD_MLMIX:
+		mix_id = SRC_MIX_ML;
+		mem_id = SRC_MEM_ML;
+		scr = BIT(4);
+		break;
+	case MIX_PD_DDRMIX:
+		mix_id = SRC_MIX_DDRMIX;
+		mem_id = SRC_MEM_DDRMIX;
+		scr = BIT(6);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	mix_regs = (struct src_mix_slice_regs *)(ulong)(SRC_IPS_BASE_ADDR + 0x400 * (mix_id + 1));
+	mem_regs = (struct src_mem_slice_regs *)(ulong)(SRC_IPS_BASE_ADDR + 0x3800 + 0x400 * mem_id);
+	global_regs = (struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE;
+
+	/* Allow NS to set it */
+	setbits_le32(&mix_regs->authen_ctrl, BIT(9));
+
+	clrsetbits_le32(&mix_regs->psw_ack_ctrl[0], BIT(28), BIT(29));
+
+	/* mix reset will be held until boot core write this bit to 1 */
+	setbits_le32(&global_regs->scr, scr);
+
+	/* Enable mem in Low power auto sequence */
+	setbits_le32(&mem_regs->mem_ctrl, BIT(2));
+
+	/* Set the power down state */
+	val = readl(&mix_regs->func_stat);
+	if (val & SRC_MIX_SLICE_FUNC_STAT_PSW_STAT) {
+		/* The mix is default power off, power down it to make PDN_SFT bit
+		 *  aligned with FUNC STAT
+		 */
+		setbits_le32(&mix_regs->slice_sw_ctrl, BIT(31));
+		val = readl(&mix_regs->func_stat);
+
+		/* Since PSW_STAT is 1, can't be used for power off status (SW_CTRL BIT31 set)) */
+		/* Check the MEM STAT change to ensure SSAR is completed */
+		while (!(val & SRC_MIX_SLICE_FUNC_STAT_MEM_STAT)) {
+			val = readl(&mix_regs->func_stat);
+		}
+
+		/* wait few ipg clock cycles to ensure FSM done and power off status is correct */
+		/* About 5 cycles at 24Mhz, 1us is enough  */
+		udelay(1);
+	} else {
+		/*  The mix is default power on, Do mix power cycle */
+		setbits_le32(&mix_regs->slice_sw_ctrl, BIT(31));
+		val = readl(&mix_regs->func_stat);
+		while (!(val & SRC_MIX_SLICE_FUNC_STAT_PSW_STAT)) {
+			val = readl(&mix_regs->func_stat);
+		}
+	}
+
+	/* power on */
+	clrbits_le32(&mix_regs->slice_sw_ctrl, BIT(31));
+	val = readl(&mix_regs->func_stat);
+	while (val & SRC_MIX_SLICE_FUNC_STAT_ISO_STAT) {
+		val = readl(&mix_regs->func_stat);
+	}
+
+	return 0;
+}
+
+void disable_isolation(void)
+{
+	struct src_general_regs *global_regs = (struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE;
+	/* clear isolation for usbphy, dsi, csi*/
+	writel(0x0, &global_regs->sp_iso_ctrl);
+}
+
+void soc_power_init(void)
+{
+	mix_power_init(MIX_PD_MEDIAMIX);
+	mix_power_init(MIX_PD_MLMIX);
+
+	disable_isolation();
+}
+
+bool m33_is_rom_kicked(void)
+{
+	struct blk_ctrl_s_aonmix_regs *s_regs =
+			(struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
+
+	if (!(readl(&s_regs->m33_cfg) & BCTRL_S_ANOMIX_M33_CPU_WAIT_MASK))
+		return true;
+
+	return false;
+}
+
+int m33_prepare(void)
+{
+	struct src_mix_slice_regs *mix_regs =
+		(struct src_mix_slice_regs *)(ulong)(SRC_IPS_BASE_ADDR + 0x400 * (SRC_MIX_CM33 + 1));
+	struct src_general_regs *global_regs =
+		(struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE;
+	struct blk_ctrl_s_aonmix_regs *s_regs =
+			(struct blk_ctrl_s_aonmix_regs *)BLK_CTRL_S_ANOMIX_BASE_ADDR;
+	u32 val;
+
+	/* Allow NS to set it */
+	setbits_le32(&mix_regs->authen_ctrl, BIT(9));
+
+	if (m33_is_rom_kicked())
+		return -EPERM;
+
+	/* Release reset of M33 */
+	setbits_le32(&global_regs->scr, BIT(0));
+
+	/* Check the reset released in M33 MIX func stat */
+	val = readl(&mix_regs->func_stat);
+	while (!(val & SRC_MIX_SLICE_FUNC_STAT_RST_STAT)) {
+		val = readl(&mix_regs->func_stat);
+	}
+
+	/* Because CPUWAIT is default set, so M33 won't run, Clear it when kick M33 */
+	/* Release Sentinel TROUT */
+	ahab_release_m33_trout();
+
+	/* Mask WDOG1 IRQ from A55, we use it for M33 reset */
+	setbits_le32(&s_regs->ca55_irq_mask[1], BIT(6));
+
+	/* Turn on WDOG1 clock */
+	ccm_lpcg_on(CCGR_WDG1, 1);
+
+	/* Set sentinel LP handshake for M33 reset */
+	setbits_le32(&s_regs->lp_handshake[0], BIT(6));
+
+	/* Clear M33 TCM for ECC */
+	memset((void *)(ulong)0x201e0000, 0, 0x40000);
+
+	return 0;
+}
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
new file mode 100644
index 00000000000..bb137a7912d
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -0,0 +1,593 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <div64.h>
+#include <asm/mach-imx/s400_api.h>
+#include <asm/mach-imx/mu_hal.h>
+
+#define DID_NUM 16
+#define MBC_MAX_NUM 4
+#define MRC_MAX_NUM 2
+#define MBC_NUM(HWCFG) ((HWCFG >> 16) & 0xF)
+#define MRC_NUM(HWCFG) ((HWCFG >> 24) & 0x1F)
+
+struct mbc_mem_dom {
+	u32 mem_glbcfg[4];
+	u32 nse_blk_index;
+	u32 nse_blk_set;
+	u32 nse_blk_clr;
+	u32 nsr_blk_clr_all;
+	u32 memn_glbac[8];
+	/* The upper only existed in the beginning of each MBC */
+	u32 mem0_blk_cfg_w[64];
+	u32 mem0_blk_nse_w[16];
+	u32 mem1_blk_cfg_w[8];
+	u32 mem1_blk_nse_w[2];
+	u32 mem2_blk_cfg_w[8];
+	u32 mem2_blk_nse_w[2];
+	u32 mem3_blk_cfg_w[8];
+	u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */
+	u32 reserved[2];
+};
+
+struct mrc_rgn_dom {
+	u32 mrc_glbcfg[4];
+	u32 nse_rgn_indirect;
+	u32 nse_rgn_set;
+	u32 nse_rgn_clr;
+	u32 nse_rgn_clr_all;
+	u32 memn_glbac[8];
+	/* The upper only existed in the beginning of each MRC */
+	u32 rgn_desc_words[16][2]; /* 16  regions at max, 2 words per region */
+	u32	rgn_nse;
+	u32 reserved2[15];
+};
+
+struct mda_inst {
+	u32 mda_w[8];
+};
+
+struct trdc_mgr {
+	u32 trdc_cr;
+	u32 res0[59];
+	u32 trdc_hwcfg0;
+	u32 trdc_hwcfg1;
+	u32 res1[450];
+	struct mda_inst mda[8];
+	u32 res2[15808];
+};
+
+struct trdc_mbc {
+	struct mbc_mem_dom mem_dom[DID_NUM];
+};
+
+struct trdc_mrc {
+	struct mrc_rgn_dom mrc_dom[DID_NUM];
+};
+
+
+int trdc_mda_set_cpu(ulong trdc_reg, u32 mda_inst, u32 mda_reg, u8 sa, u8 dids, u8 did, u8 pe, u8 pidm, u8 pid)
+{
+	struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
+	u32 *mda_w = &trdc_base->mda[mda_inst].mda_w[mda_reg];
+	u32 val = readl(mda_w);
+
+	if (val & BIT(29)) /* non-cpu */
+		return -EINVAL;
+
+	val = BIT(31) | ((pid & 0x3f) << 16) | ((pidm & 0x3f) << 8) | ((pe & 0x3) << 6) | ((sa & 0x3) << 14) | ((dids & 0x3) << 4) | (did & 0xf);
+
+	writel(val, mda_w);
+
+	return 0;
+}
+
+int trdc_mda_set_noncpu(ulong trdc_reg, u32 mda_inst, u32 mda_reg, bool did_bypass, u8 sa, u8 pa, u8 did)
+{
+	struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
+	u32 *mda_w = &trdc_base->mda[mda_inst].mda_w[mda_reg];
+	u32 val = readl(mda_w);
+
+	if (!(val & BIT(29))) /* cpu */
+		return -EINVAL;
+
+	val = BIT(31) | ((sa & 0x3) << 6) | ((pa & 0x3) << 4) | (did & 0xf);
+	if (did_bypass)
+		val |= BIT(8);
+
+	writel(val, mda_w);
+
+	return 0;
+}
+
+static ulong trdc_get_mbc_base(ulong trdc_reg, u32 mbc_x)
+{
+	struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
+	u32 mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0);
+
+	if (mbc_x >= mbc_num)
+		return 0;
+
+	return trdc_reg + 0x10000 + 0x2000 * mbc_x;
+}
+
+static ulong trdc_get_mrc_base(ulong trdc_reg, u32 mrc_x)
+{
+	struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
+	u32 mbc_num = MBC_NUM(trdc_base->trdc_hwcfg0);
+	u32 mrc_num = MRC_NUM(trdc_base->trdc_hwcfg0);
+
+	if (mrc_x >= mrc_num)
+		return 0;
+
+	return trdc_reg + 0x10000 + 0x2000 * mbc_num + 0x1000 * mrc_x;
+}
+
+int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x, u32 glbac_id, u32 glbac_val)
+{
+	struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
+	struct mbc_mem_dom *mbc_dom;
+
+	if (mbc_base == 0 || glbac_id >= 8)
+		return -EINVAL;
+
+	/* only first dom has the glbac */
+	mbc_dom = &mbc_base->mem_dom[0];
+
+	debug("mbc 0x%lx\n", (ulong)mbc_dom);
+
+	writel(glbac_val, &mbc_dom->memn_glbac[glbac_id]);
+
+	return 0;
+}
+
+int trdc_mbc_blk_config(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, bool sec_access, u32 glbac_id)
+{
+	struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
+	struct mbc_mem_dom *mbc_dom;
+	u32 *cfg_w, *nse_w;
+	u32 index, offset, val;
+
+	if (mbc_base == 0 || glbac_id >= 8)
+		return -EINVAL;
+
+	mbc_dom = &mbc_base->mem_dom[dom_x];
+
+	debug("mbc 0x%lx\n", (ulong)mbc_dom);
+
+	switch (mem_x) {
+	case 0:
+		cfg_w = &mbc_dom->mem0_blk_cfg_w[blk_x / 8];
+		nse_w = &mbc_dom->mem0_blk_nse_w[blk_x / 32];
+		break;
+	case 1:
+		cfg_w = &mbc_dom->mem1_blk_cfg_w[blk_x / 8];
+		nse_w = &mbc_dom->mem1_blk_nse_w[blk_x / 32];
+		break;
+	case 2:
+		cfg_w = &mbc_dom->mem2_blk_cfg_w[blk_x / 8];
+		nse_w = &mbc_dom->mem2_blk_nse_w[blk_x / 32];
+		break;
+	case 3:
+		cfg_w = &mbc_dom->mem3_blk_cfg_w[blk_x / 8];
+		nse_w = &mbc_dom->mem3_blk_nse_w[blk_x / 32];
+		break;
+	default:
+		return -EINVAL;
+	};
+
+	index = blk_x % 8;
+	offset = index * 4;
+
+	val = readl((void __iomem *)cfg_w);
+
+	val &= ~(0xFU << offset);
+
+	/* MBC0-3
+	 *  Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
+	 *  So select MBC0_MEMN_GLBAC0
+	 */
+	if (sec_access) {
+		val |= ((0x0 | (glbac_id & 0x7)) << offset);
+		writel(val, (void __iomem *)cfg_w);
+	} else {
+		val |= ((0x8 | (glbac_id & 0x7)) << offset); /* nse bit set */
+		writel(val, (void __iomem *)cfg_w);
+	}
+
+	return 0;
+}
+
+int trdc_mrc_set_control(ulong trdc_reg, u32 mrc_x, u32 glbac_id, u32 glbac_val)
+{
+	struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x);
+	struct mrc_rgn_dom *mrc_dom;
+
+	if (mrc_base == 0 || glbac_id >= 8)
+		return -EINVAL;
+
+	/* only first dom has the glbac */
+	mrc_dom = &mrc_base->mrc_dom[0];
+
+	debug("mrc_dom 0x%lx\n", (ulong)mrc_dom);
+
+	writel(glbac_val, &mrc_dom->memn_glbac[glbac_id]);
+
+	return 0;
+}
+
+int trdc_mrc_region_config(ulong trdc_reg, u32 mrc_x, u32 dom_x, u32 addr_start, u32 addr_end, bool sec_access, u32 glbac_id)
+{
+	struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x);
+	struct mrc_rgn_dom *mrc_dom;
+	u32 *desc_w;
+	u32 start, end;
+	u32 i, free = 8;;
+	bool vld, hit = false;
+
+	if (mrc_base == 0 || glbac_id >= 8)
+		return -EINVAL;
+
+	mrc_dom = &mrc_base->mrc_dom[dom_x];
+
+	addr_start &= ~0x3fff;
+	addr_end &= ~0x3fff;
+
+	debug("mrc_dom 0x%lx\n", (ulong)mrc_dom);
+
+	for (i = 0; i < 8; i++) {
+		desc_w = &mrc_dom->rgn_desc_words[i][0];
+
+		debug("desc_w 0x%lx\n", (ulong)desc_w);
+
+		start = readl((void __iomem *)desc_w) & (~0x3fff);
+		end = readl((void __iomem *)(desc_w + 1));
+		vld = end & 0x1;
+		end = end & (~0x3fff);
+
+		if (start == 0 && end == 0 && !vld && free >= 8)
+			free = i;
+
+		/* Check all the region descriptors, even overlap */
+		if (addr_start >= end || addr_end <= start || !vld)
+			continue;
+
+		/* MRC0,1
+		 *  Global 0, 0x7777 secure pri/user read/write/execute, S400 has already set it.
+		 *  So select MRCx_MEMN_GLBAC0
+		 */
+		if (sec_access) {
+			writel(start | (glbac_id & 0x7), (void __iomem *)desc_w);
+			writel(end | 0x1, (void __iomem *)(desc_w + 1));
+		} else {
+			writel(start | (glbac_id & 0x7), (void __iomem *)desc_w);
+			writel(end | 0x1 | 0x10, (void __iomem *)(desc_w + 1));
+		}
+
+		if (addr_start >= start && addr_end <= end)
+			hit = true;
+	}
+
+	if (!hit) {
+		if (free >= 8)
+			return -EFAULT;
+
+		desc_w = &mrc_dom->rgn_desc_words[free][0];
+
+		debug("free desc_w 0x%lx\n", (ulong)desc_w);
+		debug("[0x%x] [0x%x]\n", addr_start | (glbac_id & 0x7), addr_end | 0x1);
+
+		if (sec_access) {
+			writel(addr_start | (glbac_id & 0x7), (void __iomem *)desc_w);
+			writel(addr_end | 0x1, (void __iomem *)(desc_w + 1));
+		} else {
+			writel(addr_start | (glbac_id & 0x7), (void __iomem *)desc_w);
+			writel((addr_end | 0x1 | 0x10), (void __iomem *)(desc_w + 1));
+		}
+	}
+
+	return 0;
+}
+
+bool trdc_mrc_enabled(ulong trdc_base)
+{
+	return (!!(readl((void __iomem *)trdc_base) & 0x8000));
+}
+
+bool trdc_mbc_enabled(ulong trdc_base)
+{
+	return (!!(readl((void __iomem *)trdc_base) & 0x4000));
+}
+
+int release_rdc(u8 xrdc)
+{
+	ulong s_mu_base = 0x47520000UL;
+	struct sentinel_msg msg;
+	int ret;
+	u32 rdc_id;
+
+	switch (xrdc) {
+	case 0:
+		rdc_id = 0x74;
+		break;
+	case 1:
+		rdc_id = 0x78;
+		break;
+	case 2:
+		rdc_id = 0x82;
+		break;
+	case 3:
+		rdc_id = 0x86;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	msg.version = AHAB_VERSION;
+	msg.tag = AHAB_CMD_TAG;
+	msg.size = 2;
+	msg.command = ELE_RELEASE_RDC_REQ;
+	msg.data[0] = (rdc_id << 8) | 0x2; /* A55 */
+
+	mu_hal_init(s_mu_base);
+	mu_hal_sendmsg(s_mu_base, 0, *((u32 *)&msg));
+	mu_hal_sendmsg(s_mu_base, 1, msg.data[0]);
+
+	ret = mu_hal_receivemsg(s_mu_base, 0, (u32 *)&msg);
+	if (!ret) {
+		ret = mu_hal_receivemsg(s_mu_base, 1, &msg.data[0]);
+		if (!ret) {
+			if ((msg.data[0] & 0xff) == 0xd6)
+				return 0;
+		}
+
+		return -EIO;
+	}
+
+	return ret;
+}
+
+void trdc_early_init(void)
+{
+	int ret = 0, i;
+	ret |= release_rdc(0);
+	ret |= release_rdc(2);
+	ret |= release_rdc(1);
+	ret |= release_rdc(3);
+
+	if (!ret) {
+		/* Set OCRAM to RWX for secure, when OEM_CLOSE, the image is RX only */
+		trdc_mbc_set_control(0x49010000, 3, 0, 0x7700);
+
+		for (i = 0; i < 40; i++) {
+			trdc_mbc_blk_config(0x49010000, 3, 3, 0, i, true, 0);
+		}
+
+		for (i = 0; i < 40; i++) {
+			trdc_mbc_blk_config(0x49010000, 3, 3, 1, i, true, 0);
+		}
+
+		for (i = 0; i < 40; i++) {
+			trdc_mbc_blk_config(0x49010000, 3, 0, 0, i, true, 0);
+		}
+
+		for (i = 0; i < 40; i++) {
+			trdc_mbc_blk_config(0x49010000, 3, 0, 1, i, true, 0);
+		}
+	}
+}
+
+void trdc_init(void)
+{
+	/* TRDC mega */
+	if (trdc_mrc_enabled(0x49010000)) {
+
+		/* DDR */
+		trdc_mrc_set_control(0x49010000, 0, 0, 0x7777);
+
+		/* S400*/
+		trdc_mrc_region_config(0x49010000, 0, 0, 0x80000000, 0xFFFFFFFF, false, 0);
+
+		/* MTR */
+		trdc_mrc_region_config(0x49010000, 0, 1, 0x80000000, 0xFFFFFFFF, false, 0);
+
+		/* M33 */
+		trdc_mrc_region_config(0x49010000, 0, 2, 0x80000000, 0xFFFFFFFF, false, 0);
+
+		/* A55*/
+		trdc_mrc_region_config(0x49010000, 0, 3, 0x80000000, 0xFFFFFFFF, false, 0);
+
+		/* For USDHC1 to DDR, USDHC1 is default force to non-secure */
+		trdc_mrc_region_config(0x49010000, 0, 5, 0x80000000, 0xFFFFFFFF, false, 0);
+
+		/* For USDHC2 to DDR, USDHC2 is default force to non-secure */
+		trdc_mrc_region_config(0x49010000, 0, 6, 0x80000000, 0xFFFFFFFF, false, 0);
+
+		/* eDMA */
+		trdc_mrc_region_config(0x49010000, 0, 7, 0x80000000, 0xFFFFFFFF, false, 0);
+
+		/*CoreSight, TestPort*/
+		trdc_mrc_region_config(0x49010000, 0, 8, 0x80000000, 0xFFFFFFFF, false, 0);
+
+		/* DAP */
+		trdc_mrc_region_config(0x49010000, 0, 9, 0x80000000, 0xFFFFFFFF, false, 0);
+
+		/*SoC masters */
+		trdc_mrc_region_config(0x49010000, 0, 10, 0x80000000, 0xFFFFFFFF, false, 0);
+
+		/*USB*/
+		trdc_mrc_region_config(0x49010000, 0, 11, 0x80000000, 0xFFFFFFFF, false, 0);
+
+	}
+}
+
+#if DEBUG
+int trdc_mbc_control_dump(ulong trdc_reg, u32 mbc_x, u32 glbac_id)
+{
+	struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
+	struct mbc_mem_dom *mbc_dom;
+
+	if (mbc_base == 0 || glbac_id >= 8)
+		return -EINVAL;
+
+	/* only first dom has the glbac */
+	mbc_dom = &mbc_base->mem_dom[0];
+
+	printf("mbc_dom %u glbac %u: 0x%x\n", mbc_x, glbac_id, readl(&mbc_dom->memn_glbac[glbac_id]));
+
+	return 0;
+}
+
+int trdc_mbc_mem_dump(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x, u32 word)
+{
+	struct trdc_mbc *mbc_base = (struct trdc_mbc *)trdc_get_mbc_base(trdc_reg, mbc_x);
+	struct mbc_mem_dom *mbc_dom;
+	u32 *cfg_w;
+
+	if (mbc_base == 0)
+		return -EINVAL;
+
+	mbc_dom = &mbc_base->mem_dom[dom_x];
+
+	switch (mem_x) {
+	case 0:
+		cfg_w = &mbc_dom->mem0_blk_cfg_w[word];
+		break;
+	case 1:
+		cfg_w = &mbc_dom->mem1_blk_cfg_w[word];
+		break;
+	case 2:
+		cfg_w = &mbc_dom->mem2_blk_cfg_w[word];
+		break;
+	case 3:
+		cfg_w = &mbc_dom->mem3_blk_cfg_w[word];
+		break;
+	default:
+		return -EINVAL;
+	};
+
+	printf("mbc_dom %u dom %u mem %u word %u: 0x%x\n", mbc_x, dom_x, mem_x, word, readl((void __iomem *)cfg_w));
+
+	return 0;
+}
+
+int trdc_mrc_control_dump(ulong trdc_reg, u32 mrc_x, u32 glbac_id)
+{
+	struct trdc_mrc *mrc_base = (struct trdc_mrc *)trdc_get_mrc_base(trdc_reg, mrc_x);
+	struct mrc_rgn_dom *mrc_dom;
+
+	if (mrc_base == 0 || glbac_id >= 8)
+		return -EINVAL;
+
+	/* only first dom has the glbac */
+	mrc_dom = &mrc_base->mrc_dom[0];
+
+	printf("mrc_dom %u glbac %u: 0x%x\n", mrc_x, glbac_id, readl(&mrc_dom->memn_glbac[glbac_id]));
+
+	return 0;
+}
+
+void trdc_dump(void)
+{
+	u32 i;
+	printf("TRDC AONMIX MBC\n");
+
+	trdc_mbc_control_dump(0x44270000, 0, 0);
+	trdc_mbc_control_dump(0x44270000, 1, 0);
+
+	for (i = 0; i < 11; i++) {
+		trdc_mbc_mem_dump(0x44270000, 0, 3, 0, i);
+	}
+	for (i = 0; i < 1; i++) {
+		trdc_mbc_mem_dump(0x44270000, 0, 3, 1, i);
+	}
+
+	for (i = 0; i < 4; i++) {
+		trdc_mbc_mem_dump(0x44270000, 1, 3, 0, i);
+	}
+	for (i = 0; i < 4; i++) {
+		trdc_mbc_mem_dump(0x44270000, 1, 3, 1, i);
+	}
+
+	printf("TRDC WAKEUP MBC\n");
+
+	trdc_mbc_control_dump(0x42460000, 0, 0);
+	trdc_mbc_control_dump(0x42460000, 1, 0);
+
+	for (i = 0; i < 15; i++) {
+		trdc_mbc_mem_dump(0x42460000, 0, 3, 0, i);
+	}
+	trdc_mbc_mem_dump(0x42460000, 0, 3, 1, 0);
+	trdc_mbc_mem_dump(0x42460000, 0, 3, 2, 0);
+
+	for (i = 0; i < 2; i++) {
+		trdc_mbc_mem_dump(0x42460000, 1, 3, 0, i);
+	}
+	trdc_mbc_mem_dump(0x42460000, 1, 3, 1, 0);
+	trdc_mbc_mem_dump(0x42460000, 1, 3, 2, 0);
+	trdc_mbc_mem_dump(0x42460000, 1, 3, 3, 0);
+
+	printf("TRDC NICMIX MBC\n");
+
+	trdc_mbc_control_dump(0x49010000, 0, 0);
+	trdc_mbc_control_dump(0x49010000, 1, 0);
+	trdc_mbc_control_dump(0x49010000, 2, 0);
+	trdc_mbc_control_dump(0x49010000, 3, 0);
+
+	for (i = 0; i < 7; i++) {
+		trdc_mbc_mem_dump(0x49010000, 0, 3, 0, i);
+	}
+
+	for (i = 0; i < 2; i++) {
+		trdc_mbc_mem_dump(0x49010000, 0, 3, 1, i);
+	}
+
+	for (i = 0; i < 5; i++) {
+		trdc_mbc_mem_dump(0x49010000, 0, 3, 2, i);
+	}
+
+	for (i = 0; i < 6; i++) {
+		trdc_mbc_mem_dump(0x49010000, 0, 3, 3, i);
+	}
+
+	for (i = 0; i < 1; i++) {
+		trdc_mbc_mem_dump(0x49010000, 1, 3, 0, i);
+	}
+
+	for (i = 0; i < 1; i++) {
+		trdc_mbc_mem_dump(0x49010000, 1, 3, 1, i);
+	}
+
+	for (i = 0; i < 3; i++) {
+		trdc_mbc_mem_dump(0x49010000, 1, 3, 2, i);
+	}
+
+	for (i = 0; i < 3; i++) {
+		trdc_mbc_mem_dump(0x49010000, 1, 3, 3, i);
+	}
+
+	for (i = 0; i < 2; i++) {
+		trdc_mbc_mem_dump(0x49010000, 2, 3, 0, i);
+	}
+
+	for (i = 0; i < 2; i++) {
+		trdc_mbc_mem_dump(0x49010000, 2, 3, 1, i);
+	}
+
+	for (i = 0; i < 5; i++) {
+		trdc_mbc_mem_dump(0x49010000, 3, 3, 0, i);
+	}
+
+	for (i = 0; i < 5; i++) {
+		trdc_mbc_mem_dump(0x49010000, 3, 3, 1, i);
+	}
+}
+#endif
diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c
index 9ffe5ac6e34..682a7880c93 100644
--- a/arch/arm/mach-imx/imx_bootaux.c
+++ b/arch/arm/mach-imx/imx_bootaux.c
@@ -14,6 +14,7 @@
 #include <linux/compiler.h>
 #include <cpu_func.h>
 
+#ifndef CONFIG_IMX8
 #ifndef CONFIG_IMX8M
 const __weak struct rproc_att hostmap[] = { };
 
@@ -81,7 +82,7 @@ static unsigned long load_elf_image_m_core_phdr(unsigned long addr)
 
 int arch_auxiliary_core_up(u32 core_id, ulong addr)
 {
-	ulong stack, pc;
+	u32 stack, pc;
 
 	if (!addr)
 		return -EINVAL;
@@ -110,18 +111,26 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
 		pc = *(u32 *)(addr + 4);
 	}
 #endif
-	printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n",
+	printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n",
 	       stack, pc);
 
-	/* Set the stack and pc to M4 bootROM */
-	writel(stack, M4_BOOTROM_BASE_ADDR);
-	writel(pc, M4_BOOTROM_BASE_ADDR + 4);
+	/* Set the stack and pc to MCU bootROM */
+	writel(stack, MCU_BOOTROM_BASE_ADDR);
+	writel(pc, MCU_BOOTROM_BASE_ADDR + 4);
 
 	flush_dcache_all();
 
-	/* Enable M4 */
+	/* Enable MCU */
 #ifdef CONFIG_IMX8M
-	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0,
+#if defined(CONFIG_IMX_HAB) && defined(CONFIG_ANDROID_SUPPORT)
+	extern int authenticate_image(
+		uint32_t ddr_start, uint32_t raw_image_size);
+	if (authenticate_image(addr, ANDROID_MCU_FIRMWARE_SIZE) != 0) {
+		printf("Authenticate MCU Image Fail, Please check.\n");
+		return -EINVAL;
+	}
+#endif
+	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, 0, 0,
 		      0, 0, 0, 0, NULL);
 #else
 	clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
@@ -136,7 +145,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
 #ifdef CONFIG_IMX8M
 	struct arm_smccc_res res;
 
-	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0,
+	arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0,
 		      0, 0, 0, 0, &res);
 
 	return res.a0;
@@ -151,30 +160,34 @@ int arch_auxiliary_core_check_up(u32 core_id)
 	return 1;
 #endif
 }
-
+#endif
 /*
  * To i.MX6SX and i.MX7D, the image supported by bootaux needs
  * the reset vector at the head for the image, with SP and PC
  * as the first two words.
  *
- * Per the cortex-M reference manual, the reset vector of M4 needs
- * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses
- * of that vector.  So to boot M4, the A core must build the M4's reset
+ * Per the cortex-M reference manual, the reset vector of M4/M7 needs
+ * to exist at 0x0 (TCMUL/IDTCM). The PC and SP are the first two addresses
+ * of that vector.  So to boot M4/M7, the A core must build the M4/M7's reset
  * vector with getting the PC and SP from image and filling them to
- * TCMUL. When M4 is kicked, it will load the PC and SP by itself.
- * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
- * accessing the M4 TCMUL.
+ * TCMUL/IDTCM. When M4/M7 is kicked, it will load the PC and SP by itself.
+ * The TCMUL/IDTCM is mapped to (MCU_BOOTROM_BASE_ADDR) at A core side for
+ * accessing the M4/M7 TCMUL/IDTCM.
  */
 static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
 		      char *const argv[])
 {
 	ulong addr;
 	int ret, up;
+	u32 core = 0;
 
 	if (argc < 2)
 		return CMD_RET_USAGE;
 
-	up = arch_auxiliary_core_check_up(0);
+	if (argc > 2)
+		core = simple_strtoul(argv[2], NULL, 10);
+
+	up = arch_auxiliary_core_check_up(core);
 	if (up) {
 		printf("## Auxiliary core is already up\n");
 		return CMD_RET_SUCCESS;
@@ -185,7 +198,7 @@ static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
 	if (!addr)
 		return CMD_RET_FAILURE;
 
-	ret = arch_auxiliary_core_up(0, addr);
+	ret = arch_auxiliary_core_up(core, addr);
 	if (ret)
 		return CMD_RET_FAILURE;
 
@@ -195,5 +208,7 @@ static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
 U_BOOT_CMD(
 	bootaux, CONFIG_SYS_MAXARGS, 1,	do_bootaux,
 	"Start auxiliary core",
-	""
+	"<address> [<core>]\n"
+	"   - start auxiliary core [<core>] (default 0),\n"
+	"     at address <address>\n"
 );
diff --git a/arch/arm/mach-imx/imx_vservice.c b/arch/arm/mach-imx/imx_vservice.c
new file mode 100644
index 00000000000..1669e24819a
--- /dev/null
+++ b/arch/arm/mach-imx/imx_vservice.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <dm/root.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+#include <misc.h>
+#include <asm/mach-imx/imx_vservice.h>
+#include <imx_m4_mu.h>
+#include <malloc.h>
+
+static LIST_HEAD(vservice_channels);
+
+void * __weak board_imx_vservice_get_buffer(struct imx_vservice_channel *node, u32 size)
+{
+	if (size <= CONFIG_IMX_VSERVICE_SHARED_BUFFER_SIZE)
+		return (void * )CONFIG_IMX_VSERVICE_SHARED_BUFFER;
+
+	return NULL;
+}
+
+void * imx_vservice_get_buffer(struct imx_vservice_channel *node, u32 size)
+{
+	return board_imx_vservice_get_buffer(node, size);
+}
+
+int imx_vservice_blocking_request(struct imx_vservice_channel *node, u8 *buf, u32* size)
+{
+	int ret = 0;
+	union imx_m4_msg msg;
+
+	msg.format.seq = node->msg_seq;
+	msg.format.type = MU_MSG_REQ;
+	msg.format.buffer = (u32)(ulong)buf;
+	msg.format.size = *size;
+
+	ret = misc_call(node->mu_dev, 1000000, &msg, 4, &msg, 4);
+	if (ret) {
+		printf("%s: Send request MU message failed, ret %d\n", __func__, ret);
+		goto MU_ERR;
+	}
+
+	if (msg.format.type != MU_MSG_RESP|| msg.format.seq != node->msg_seq) {
+		printf("%s: wrong msg response: type %d, seq %d, expect seq %d\n",
+			__func__, msg.format.type, msg.format.seq, node->msg_seq);
+		ret = -EIO;
+		goto MU_ERR;
+	}
+
+	*size = msg.format.size;
+
+MU_ERR:
+	node->msg_seq++;
+
+	return ret;
+}
+
+static int imx_vservice_connect(struct imx_vservice_channel *node)
+{
+	int ret = 0;
+	union imx_m4_msg msg;
+
+	unsigned long timeout = timer_get_us() + 2000000; /* 2s timeout */
+
+	for (;;) {
+		msg.format.seq = 0;
+		msg.format.type = MU_MSG_READY_A;
+		msg.format.buffer = 0;
+		msg.format.size = 0;
+
+		ret = misc_call(node->mu_dev, 100000, &msg, 4, &msg, 4);
+		if (!ret && msg.format.type == MU_MSG_READY_B)
+			return 0;
+
+		if (time_after(timer_get_us(), timeout)) {
+			printf("%s: Timeout to connect peer, %d\n", __func__, ret);
+			return -ETIMEDOUT;
+		}
+	}
+
+	return -EIO;
+}
+
+struct udevice * __weak board_imx_vservice_find_mu(struct udevice *virt_dev)
+{
+	int ret;
+	struct ofnode_phandle_args args;
+	struct udevice *mu_dev;
+
+	/* Default get mu from "fsl,vservice-mu" property*/
+	ret = dev_read_phandle_with_args(virt_dev, "fsl,vservice-mu",
+					 NULL, 0, 0, &args);
+	if (ret) {
+		printf("Can't find \"fsl,vservice-mu\" property\n");
+		return NULL;
+	}
+
+	ret = uclass_find_device_by_ofnode(UCLASS_MISC, args.node, &mu_dev);
+	if (ret) {
+		printf("Can't find MU device, err %d\n", ret);
+		return NULL;
+	}
+
+	return mu_dev;
+}
+
+static struct udevice * imx_vservice_find_mu(struct udevice *virt_dev)
+{
+	return board_imx_vservice_find_mu(virt_dev);
+}
+
+struct imx_vservice_channel * imx_vservice_setup(struct udevice *virt_dev)
+{
+	int ret;
+	 struct udevice *mu_dev;
+	 struct imx_vservice_channel *channel;
+
+	mu_dev = imx_vservice_find_mu(virt_dev);
+	if (mu_dev == NULL) {
+		printf("No MU device for virtual service %s connection\n", virt_dev->name);
+		return NULL;
+	}
+
+	ret = device_probe(mu_dev);
+	if (ret) {
+		printf("Probe MU device failed\n");
+		return NULL;
+	}
+
+	list_for_each_entry(channel, &vservice_channels, channel_head) {
+		if (channel->mu_dev == mu_dev)
+			return channel;
+	}
+
+	channel = malloc(sizeof(struct imx_vservice_channel));
+	if (!channel) {
+		printf("Malloc vservice channel is failed\n");
+		return NULL;
+	}
+
+	channel->msg_seq = 0;
+	channel->mu_dev = mu_dev;
+	INIT_LIST_HEAD(&channel->channel_head);
+
+	ret = imx_vservice_connect(channel);
+	if (ret) {
+		printf("VService: Connection is failed, ret %d\n", ret);
+		free(channel);
+		return NULL;
+	}
+
+	list_add_tail(&channel->channel_head, &vservice_channels);
+
+	printf("VService: Connection is ok on MU %s\n", mu_dev->name);
+
+	return channel;
+}
diff --git a/arch/arm/mach-imx/lowlevel.S b/arch/arm/mach-imx/lowlevel.S
index 158fdb7d87b..2cb2d056a95 100644
--- a/arch/arm/mach-imx/lowlevel.S
+++ b/arch/arm/mach-imx/lowlevel.S
@@ -6,6 +6,16 @@
 #include <linux/linkage.h>
 
 ENTRY(lowlevel_init)
+#ifdef CONFIG_SPL_BUILD
+	mrs	x0, CurrentEL
+	cmp	x0, #12
+	b.eq	1f
+	ret
+1:
+	msr daifclr, #4
+	isb
+	ret
+#else
 	mrs	x0, CurrentEL
 	cmp	x0, #8
 	b.eq	1f
@@ -19,4 +29,5 @@ ENTRY(lowlevel_init)
 	msr	hcr_el2, x0
 	isb
 	ret
+#endif
 ENDPROC(lowlevel_init)
diff --git a/arch/arm/mach-imx/misc.c b/arch/arm/mach-imx/misc.c
index 09a758ff6e8..b0fc165dd5b 100644
--- a/arch/arm/mach-imx/misc.c
+++ b/arch/arm/mach-imx/misc.c
@@ -12,6 +12,7 @@
 #include <linux/errno.h>
 #include <asm/io.h>
 #include <asm/mach-imx/regs-common.h>
+#include <fdt_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -77,3 +78,107 @@ int mxs_reset_block(struct mxs_register_32 *reg)
 
 	return 0;
 }
+
+void configure_tzc380(void)
+{
+#if defined (IP2APB_TZASC1_BASE_ADDR)
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	if (iomux->gpr[9] & 0x1)
+		writel(0xf0000000, IP2APB_TZASC1_BASE_ADDR + 0x108);
+#endif
+#if defined (IP2APB_TZASC2_BASE_ADDR)
+	if (iomux->gpr[9] & 0x2)
+		writel(0xf0000000, IP2APB_TZASC2_BASE_ADDR + 0x108);
+#endif
+}
+
+static void set_dt_val(void *data, uint32_t cell_size, uint64_t val)
+{
+	if (cell_size == 1) {
+		fdt32_t v = cpu_to_fdt32((uint32_t)val);
+
+		memcpy(data, &v, sizeof(v));
+	} else {
+		fdt64_t v = cpu_to_fdt64(val);
+
+		memcpy(data, &v, sizeof(v));
+	}
+}
+
+int add_dt_path_subnode(void *fdt, const char *path, const char *subnode)
+{
+	int offs;
+
+	offs = fdt_path_offset(fdt, path);
+	if (offs < 0)
+		return -1;
+
+	offs = fdt_add_subnode(fdt, offs, subnode);
+	if (offs < 0)
+		return -1;
+	return offs;
+}
+
+int add_res_mem_dt_node(void *fdt, const char *name, phys_addr_t pa,
+			size_t size)
+{
+	int offs = 0;
+	int ret = 0;
+	int addr_size = -1;
+	int len_size = -1;
+	bool found = true;
+	char subnode_name[80] = { 0 };
+
+	offs = fdt_path_offset(fdt, "/reserved-memory");
+
+	if (offs < 0) {
+		found = false;
+		offs = 0;
+	}
+
+	len_size = fdt_size_cells(fdt, offs);
+	if (len_size < 0)
+		return -1;
+	addr_size = fdt_address_cells(fdt, offs);
+	if (addr_size < 0)
+		return -1;
+
+	if (!found) {
+		offs = add_dt_path_subnode(fdt, "/", "reserved-memory");
+		if (offs < 0)
+			return -1;
+
+		ret = fdt_setprop_cell(fdt, offs, "#address-cells", addr_size);
+		if (ret < 0)
+			return -1;
+		ret = fdt_setprop_cell(fdt, offs, "#size-cells", len_size);
+		if (ret < 0)
+			return -1;
+		ret = fdt_setprop(fdt, offs, "ranges", NULL, 0);
+		if (ret < 0)
+			return -1;
+	}
+
+#ifdef CONFIG_PHYS_64BIT
+	snprintf(subnode_name, sizeof(subnode_name), "%s@0x%llx", name, pa);
+#else
+	snprintf(subnode_name, sizeof(subnode_name), "%s@0x%lx", name, pa);
+#endif
+	offs = fdt_add_subnode(fdt, offs, subnode_name);
+	if (offs >= 0) {
+		u32 data[FDT_MAX_NCELLS * 2];
+
+		set_dt_val(data, addr_size, pa);
+		set_dt_val(data + addr_size, len_size, size);
+		ret = fdt_setprop(fdt, offs, "reg", data,
+				  sizeof(uint32_t) * (addr_size + len_size));
+		if (ret < 0)
+			return -1;
+		ret = fdt_setprop(fdt, offs, "no-map", NULL, 0);
+		if (ret < 0)
+			return -1;
+	} else {
+		return -1;
+	}
+	return 0;
+}
diff --git a/arch/arm/mach-imx/mmc_env.c b/arch/arm/mach-imx/mmc_env.c
index 9c822f721c6..7012ae9d7bd 100644
--- a/arch/arm/mach-imx/mmc_env.c
+++ b/arch/arm/mach-imx/mmc_env.c
@@ -8,10 +8,11 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <asm/mach-imx/boot_mode.h>
+#include <env.h>
 
 __weak int board_mmc_get_env_dev(int devno)
 {
-	return CONFIG_SYS_MMC_ENV_DEV;
+	return devno;
 }
 
 int mmc_get_env_dev(void)
@@ -23,7 +24,7 @@ int mmc_get_env_dev(void)
 
 	/* If not boot from sd/mmc, use default value */
 	if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
-		return CONFIG_SYS_MMC_ENV_DEV;
+		return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV);
 
 	return board_mmc_get_env_dev(devno);
 }
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 98df4d4e428..8954278ccc4 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -33,6 +33,11 @@ config MX6Q
 	select HAS_CAAM
 	select MX6_SMP
 
+config MX6QP
+	bool "i.MX 6QuadPlus SoC support"
+	select HAS_CAAM
+	select MX6_SMP
+
 config MX6QDL
 	bool "i.MX 6Dual and 6Quad SoC support"
 	select HAS_CAAM
@@ -106,6 +111,48 @@ config MX6_DDRCAL
 	  Say "Y" if your board uses dynamic (per-boot) DDR calibration.
 	  If unsure, say N.
 
+config LDO_BYPASS_CHECK
+	bool "Enable the LDO bypass checking and setting"
+	default y if !MX6SLL
+	help
+	  This feature searches the gpc node in loaded DTB and checking the
+	  "fsl,ldo-bypass" property. When the property is set, board relevant 
+	  PMIC settings are called to adjust for LDO bypass. 
+
+config CMD_BEE
+	bool "Enable commands for Bus Encryption Engine(BEE)"
+	depends on MX6UL
+	help
+	  Set "Y" to enable the bee commands
+
+config TARGET_MX6SABREAUTO_COMMON
+    bool
+    select BOARD_LATE_INIT
+    select DM
+    select DM_THERMAL
+    select IMX_THERMAL
+    select BOARD_EARLY_INIT_F
+    select NXP_BOARD_REVISION
+    imply CMD_DM
+    select FSL_CAAM
+    select FSL_BLOB
+    select ARCH_MISC_INIT
+    select RNG_SELF_TEST
+
+config TARGET_MX6SABRESD_COMMON
+    bool
+    select BOARD_LATE_INIT
+    select DM
+    select DM_THERMAL
+    select IMX_THERMAL
+    select BOARD_EARLY_INIT_F
+    select NXP_BOARD_REVISION
+    imply CMD_DM
+    select FSL_CAAM
+    select FSL_BLOB
+    select ARCH_MISC_INIT
+    select RNG_SELF_TEST
+
 choice
 	prompt "MX6 board select"
 	optional
@@ -354,6 +401,8 @@ config TARGET_MX6SABREAUTO
 	select DM_THERMAL
 	select SUPPORT_SPL
 	imply CMD_DM
+	select FSL_CAAM
+	select ARCH_MISC_INIT
 
 config TARGET_MX6SABRESD
 	bool "mx6sabresd"
@@ -364,6 +413,48 @@ config TARGET_MX6SABRESD
 	select DM_THERMAL
 	select SUPPORT_SPL
 	imply CMD_DM
+	select FSL_CAAM
+	select ARCH_MISC_INIT
+
+config TARGET_MX6QSABREAUTO
+    bool "mx6qsabreauto"
+    select TARGET_MX6SABREAUTO_COMMON
+    depends on MX6Q
+
+config TARGET_MX6QPSABREAUTO
+    bool "mx6qpsabreauto"
+    select TARGET_MX6SABREAUTO_COMMON
+    depends on MX6QP
+
+config TARGET_MX6DLSABREAUTO
+    bool "mx6dlsabreauto"
+    select TARGET_MX6SABREAUTO_COMMON
+    depends on MX6DL
+
+config TARGET_MX6SOLOSABREAUTO
+    bool "mx6solosabreauto"
+    select TARGET_MX6SABREAUTO_COMMON
+    depends on MX6S
+
+config TARGET_MX6QSABRESD
+	bool "mx6qsabresd"
+    select TARGET_MX6SABRESD_COMMON
+    depends on MX6Q
+
+config TARGET_MX6QPSABRESD
+	bool "mx6qpsabresd"
+    select TARGET_MX6SABRESD_COMMON
+    depends on MX6QP
+
+config TARGET_MX6DLSABRESD
+	bool "mx6dlsabresd"
+    select TARGET_MX6SABRESD_COMMON
+    depends on MX6DL
+
+config TARGET_MX6SOLOSABRESD
+	bool "mx6solosabresd"
+    select TARGET_MX6SABRESD_COMMON
+    depends on MX6S
 
 config TARGET_MX6SLEVK
 	bool "mx6slevk"
@@ -378,6 +469,14 @@ config TARGET_MX6SLLEVK
 	select DM_THERMAL
 	imply CMD_DM
 
+config TARGET_MX6SLL_VAL
+	bool "mx6sll val"
+	depends on MX6SLL
+	select BOARD_LATE_INIT
+	select DM
+	select DM_THERMAL
+	imply CMD_DM
+
 config TARGET_MX6SXSABRESD
 	bool "mx6sxsabresd"
 	depends on MX6SX
@@ -386,6 +485,10 @@ config TARGET_MX6SXSABRESD
 	select DM
 	select DM_THERMAL
 	select SUPPORT_SPL
+	select FSL_CAAM
+	select FSL_BLOB
+	select ARCH_MISC_INIT
+	select RNG_SELF_TEST
 
 config TARGET_MX6SXSABREAUTO
 	bool "mx6sxsabreauto"
@@ -396,6 +499,33 @@ config TARGET_MX6SXSABREAUTO
 	select DM_THERMAL
 	imply CMD_DM
 
+config TARGET_MX6SX_14X14_VAL
+	bool "mx6sx_14x14_val"
+	depends on MX6SX
+	select DM
+	select DM_THERMAL
+	select BOARD_EARLY_INIT_F
+	select BOARD_LATE_INIT
+	imply CMD_DM
+
+config TARGET_MX6SX_17X17_VAL
+	bool "mx6sx_17x17_val"
+	depends on MX6SX
+	select DM
+	select DM_THERMAL
+	select BOARD_EARLY_INIT_F
+	select BOARD_LATE_INIT
+	imply CMD_DM
+
+config TARGET_MX6SX_19X19_VAL
+	bool "mx6sx_19x19_val"
+	depends on MX6SX
+	select DM
+	select DM_THERMAL
+	select BOARD_EARLY_INIT_F
+	select BOARD_LATE_INIT
+	imply CMD_DM
+
 config TARGET_MX6UL_9X9_EVK
 	bool "mx6ul_9x9_evk"
 	depends on MX6UL
@@ -403,7 +533,12 @@ config TARGET_MX6UL_9X9_EVK
 	select DM
 	select DM_THERMAL
 	select SUPPORT_SPL
+	select IMX_MODULE_FUSE
+	select OF_SYSTEM_SETUP
 	imply CMD_DM
+	select FSL_CAAM
+	select FSL_BLOB
+	select ARCH_MISC_INIT
 
 config TARGET_MX6UL_14X14_EVK
 	bool "mx6ul_14x14_evk"
@@ -412,6 +547,31 @@ config TARGET_MX6UL_14X14_EVK
 	select DM
 	select DM_THERMAL
 	select SUPPORT_SPL
+	select IMX_MODULE_FUSE
+	select OF_SYSTEM_SETUP
+	imply CMD_DM
+	select FSL_CAAM
+	select FSL_BLOB
+	select ARCH_MISC_INIT
+
+config TARGET_MX6UL_14X14_DDR3_VAL
+	bool "mx6ul_14x14_ddr3_val"
+	depends on MX6UL
+	select BOARD_LATE_INIT
+	select DM
+	select DM_THERMAL
+	select IMX_MODULE_FUSE
+	select OF_SYSTEM_SETUP
+	imply CMD_DM
+
+config TARGET_MX6UL_14X14_LPDDR2_VAL
+	bool "mx6ul_14x14_lpddr2_val"
+	depends on MX6UL
+	select BOARD_LATE_INIT
+	select DM
+	select DM_THERMAL
+	select IMX_MODULE_FUSE
+	select OF_SYSTEM_SETUP
 	imply CMD_DM
 
 config TARGET_MX6UL_ENGICAM
@@ -432,12 +592,34 @@ config TARGET_MX6UL_ENGICAM
 	select SUPPORT_SPL
 	imply CMD_DM
 
+config TARGET_MX6ULL_DDR3_VAL
+	bool "Support mx6ull_ddr3_val"
+	depends on MX6ULL
+	select BOARD_LATE_INIT
+	select DM
+	select DM_THERMAL
+	select IMX_MODULE_FUSE
+	select OF_SYSTEM_SETUP
+	imply CMD_DM
+
+config TARGET_MX6ULL_9X9_EVK
+	bool "Support mx6ull_9x9_evk"
+	depends on MX6ULL
+	select BOARD_LATE_INIT
+	select DM
+	select DM_THERMAL
+	select IMX_MODULE_FUSE
+	select OF_SYSTEM_SETUP
+	imply CMD_DM
+
 config TARGET_MX6ULL_14X14_EVK
 	bool "Support mx6ull_14x14_evk"
 	depends on MX6ULL
 	select BOARD_LATE_INIT
 	select DM
 	select DM_THERMAL
+	select IMX_MODULE_FUSE
+	select OF_SYSTEM_SETUP
 	imply CMD_DM
 
 config TARGET_MYS_6ULX
@@ -669,11 +851,17 @@ source "board/freescale/mx6memcal/Kconfig"
 source "board/freescale/mx6sabreauto/Kconfig"
 source "board/freescale/mx6sabresd/Kconfig"
 source "board/freescale/mx6slevk/Kconfig"
+source "board/freescale/mx6sll_val/Kconfig"
 source "board/freescale/mx6sllevk/Kconfig"
 source "board/freescale/mx6sxsabresd/Kconfig"
 source "board/freescale/mx6sxsabreauto/Kconfig"
+source "board/freescale/mx6sx_17x17_val/Kconfig"
+source "board/freescale/mx6sx_19x19_val/Kconfig"
 source "board/freescale/mx6ul_14x14_evk/Kconfig"
+source "board/freescale/mx6ul_14x14_ddr3_val/Kconfig"
+source "board/freescale/mx6ul_14x14_lpddr2_val/Kconfig"
 source "board/freescale/mx6ullevk/Kconfig"
+source "board/freescale/mx6ull_ddr3_val/Kconfig"
 source "board/grinn/liteboard/Kconfig"
 source "board/phytec/pcm058/Kconfig"
 source "board/phytec/pcl063/Kconfig"
diff --git a/arch/arm/mach-imx/mx6/Makefile b/arch/arm/mach-imx/mx6/Makefile
index 7ea8f91e4f0..a6e45391db2 100644
--- a/arch/arm/mach-imx/mx6/Makefile
+++ b/arch/arm/mach-imx/mx6/Makefile
@@ -4,6 +4,8 @@
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # (C) Copyright 2011 Freescale Semiconductor, Inc.
+# Copyright 2018 NXP
+#
 
 obj-y	:= soc.o clock.o
 obj-$(CONFIG_IMX_MODULE_FUSE) += module_fuse.o
@@ -11,3 +13,6 @@ obj-$(CONFIG_SPL_BUILD)	     += ddr.o
 obj-$(CONFIG_MP)             += mp.o
 obj-$(CONFIG_MX6UL_LITESOM)  += litesom.o
 obj-$(CONFIG_MX6UL_OPOS6UL)  += opos6ul.o
+ifdef CONFIG_MX6UL
+obj-$(CONFIG_CMD_BEE)        += bee.o
+endif
diff --git a/arch/arm/mach-imx/mx6/bee.c b/arch/arm/mach-imx/mx6/bee.c
new file mode 100644
index 00000000000..50f8676bbf0
--- /dev/null
+++ b/arch/arm/mach-imx/mx6/bee.c
@@ -0,0 +1,466 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/mx6_bee.h>
+#include <linux/errno.h>
+#include <asm/system.h>
+#include <common.h>
+#include <command.h>
+#include <fuse.h>
+#include <asm/arch/sys_proto.h>
+#include <cpu_func.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if (defined(CONFIG_SYS_DCACHE_OFF) || defined(CONFIG_SYS_ICACHE_OFF))
+#error "Bee needs Cache Open"
+#endif
+
+struct bee_parameters {
+	int key_method;
+	int mode;
+	u32 start1;
+	u32 size1;
+	u32 start2;
+	u32 size2;
+};
+
+#define SOFT_KEY 0
+#define SNVS_KEY 1
+
+#define ECB_MODE 0
+#define CTR_MODE 1
+
+#define AES_REGION0_ADDR	0x10000000
+#define AES_REGION1_ADDR	0x30000000
+
+static struct bee_parameters para;
+static int bee_inited;
+
+union key_soft {
+	u8 s_key[16];
+	u32 b_key[4];
+};
+
+union key_soft key_bad;
+
+/* software version */
+u8 hw_get_random_byte(void)
+{
+	static u32 lcg_state;
+	static u32 nb_soft = 9876543;
+#define MAX_SOFT_RNG 1024
+	static const u32 a = 1664525;
+	static const u32 c = 1013904223;
+	nb_soft = (nb_soft + 1) % MAX_SOFT_RNG;
+	lcg_state = (a * lcg_state + c);
+	return (u8) (lcg_state >> 24);
+}
+
+/*
+ * Lock bee GPR0 bits
+ * Only reset can release these bits.
+ */
+static int bee_lock(void)
+{
+	int val;
+
+	val = readl(BEE_BASE_ADDR + GPR0);
+	val |= (GPR0_CTRL_CLK_EN_LOCK | GPR0_CTRL_SFTRST_N_LOCK |
+		GPR0_CTRL_AES_MODE_LOCK | GPR0_SEC_LEVEL_LOCK |
+		GPR0_AES_KEY_SEL_LOCK | GPR0_BEE_ENABLE_LOCK);
+	writel(val, BEE_BASE_ADDR + GPR0);
+
+	return 0;
+}
+
+/* Only check bee enable lock is enough */
+static int bee_locked(void)
+{
+	int val;
+
+	val = readl(BEE_BASE_ADDR + GPR0);
+
+	return val & GPR0_BEE_ENABLE_LOCK ? 1 : 0;
+}
+
+int bee_init(struct bee_parameters *p)
+{
+	int i;
+	union key_soft *key = &key_bad;
+	u32 value;
+
+	if (bee_locked()) {
+		printf("BEE already enabled and locked.\n");
+		return CMD_RET_FAILURE;
+	}
+
+	/* CLKGATE, SFTRST */
+	writel(GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N, BEE_BASE_ADDR + GPR0);
+	/* OFFSET_ADDR0 */
+	writel(p->start1 >> 16, BEE_BASE_ADDR + GPR1);
+	/*
+	 * OFFSET_ADDR1
+	 * Default protect IRAM region, if what you want to protect
+	 * bigger that 512M which is the max size that one AES region
+	 * can protect, we need AES region 1 to cover.
+	 */
+	writel(p->start2 >> 16, BEE_BASE_ADDR + GPR2);
+
+	if (p->key_method == SOFT_KEY) {
+		for (i = 0; i < 16; i++)
+			key->s_key[i] = hw_get_random_byte();
+		/* AES 128 key from software */
+		/* aes0_key0_w0 */
+		writel(key->b_key[0], BEE_BASE_ADDR + GPR3);
+		/* aes0_key0_w1 */
+		writel(key->b_key[1], BEE_BASE_ADDR + GPR4);
+		/* aes0_key0_w2 */
+		writel(key->b_key[2], BEE_BASE_ADDR + GPR5);
+		/* aes0_key0_w3 */
+		writel(key->b_key[3], BEE_BASE_ADDR + GPR6);
+	}
+
+	if (p->mode == ECB_MODE) {
+		value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N |
+			GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SNVS |
+			GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_ECB;
+		if (p->key_method == SOFT_KEY)
+			value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N |
+				GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SOFT |
+				GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_ECB;
+		writel(value, BEE_BASE_ADDR + GPR0);
+	} else {
+		for (i = 0; i < 16; i++)
+			key->s_key[i] = hw_get_random_byte();
+		/* aes_key1_w0 */
+		writel(key->b_key[0], BEE_BASE_ADDR + GPR8);
+		/* aes_key1_w1 */
+		writel(key->b_key[1], BEE_BASE_ADDR + GPR9);
+		/* aes_key1_w2 */
+		writel(key->b_key[2], BEE_BASE_ADDR + GPR10);
+		/* aes_key1_w3 */
+		writel(key->b_key[3], BEE_BASE_ADDR + GPR11);
+
+		value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N |
+			GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SNVS |
+			GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_CTR;
+		if (p->key_method == SOFT_KEY)
+			value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N |
+				GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SOFT |
+				GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_CTR;
+		writel(value, BEE_BASE_ADDR + GPR0);
+	}
+
+	bee_lock();
+
+	printf("BEE is settings as: %s mode, %s %d key\n",
+	       (p->mode == ECB_MODE) ? "ECB" : "CTR",
+	       (p->key_method == SOFT_KEY) ? "SOFT" : "SNVS HW",
+	       (p->mode == ECB_MODE) ? 128 : 256);
+
+	return CMD_RET_SUCCESS;
+}
+
+int bee_test(struct bee_parameters *p, int region)
+{
+	u32 result = 0, range, address;
+	int i, val;
+	/*
+	 * Test instruction running in AES Region:
+	 * int test(void)
+	 * {
+	 *	return 0x55aa55aa;
+	 * }
+	 * Assemble:
+	 * 0xe59f0000: ldr r0, [pc]
+	 * 0xe12fff1e: bx lr
+	 * 0x55aa55aa: 0x55aa55aa
+	 */
+	u32 inst[3] = {0xe59f0000, 0xe12fff1e, 0x55aa55aa};
+
+	/* Cache enabled? */
+	if ((get_cr() & (CR_I | CR_C)) != (CR_I | CR_C)) {
+		printf("Enable dcache and icache first!\n");
+		return CMD_RET_FAILURE;
+	}
+
+	printf("Test Region %d\nBegin Data test: Writing... ", region);
+
+	range = (region == 0) ? p->size1 : p->size2;
+	address = (region == 0) ? AES_REGION0_ADDR : AES_REGION1_ADDR;
+	for (i = 0; i < range; i = i + 4)
+		writel(i, address + i);
+
+	printf("Finshed Write!\n");
+
+	flush_dcache_range(address, address + range);
+
+	printf("Reading... ");
+	for (i = 0; i < range; i = i + 4) {
+		val = readl(address + i);
+		if (val != i)
+			result++;
+	}
+	printf("Finshed Read!\n");
+
+	if (result > 0)
+		printf("BEE Data Test check Failed!\n");
+	else
+		printf("BEE Data Test Check Passed!\n");
+
+	for (i = 0; i < ARRAY_SIZE(inst); i++)
+		writel(inst[i], address + (i * 4));
+
+	flush_dcache_range(address, address + sizeof(inst));
+
+	val = ((int (*)(void))address)();
+
+	printf("\nBee Instruction test, Program:\n"
+	       "int test(void)\n"
+	       "{\n"
+	       "      return 0x55aa55aa;\n"
+	       "}\n"
+	       "Assemble:\n"
+	       "0xe59f0000: ldr r0, [pc]\n"
+	       "0xe12fff1e: bx lr\n"
+	       "0x55aa55aa: 0x55aa55aa\n"
+	       "Runnint at 0x%x\n", address);
+	if (val == 0x55aa55aa)
+		printf("Bee Instruction Test Passed!\n");
+	else
+		printf("Bee Instruction Test Failed!\n");
+
+	return CMD_RET_SUCCESS;
+}
+
+static int region_valid(u32 start, u32 size)
+{
+	if ((start < PHYS_SDRAM) || (start >= (start + size - 1)) ||
+	    (start >= (PHYS_SDRAM + PHYS_SDRAM_SIZE - 1))) {
+		printf("Invalid start 0x%x, size 0x%x\n", start, size);
+		return -EINVAL;
+	}
+
+	if (size > SZ_512M) {
+		printf("The region size exceeds SZ_512M\n");
+		return -EINVAL;
+	}
+
+	if ((start & 0xFFFF) && (size & 0xFFFF)) {
+		printf("start or size not 64KB aligned!\n");
+		return -EINVAL;
+	}
+
+	/* 128K for U-Boot Stack */
+	if ((start + size - 1) >= (gd->start_addr_sp - SZ_128K)) {
+		printf("Overlap with uboot execution environment!\n"
+		       "Decrease size or start\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int do_bee_init(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	u32 start, size;
+	int ret;
+	struct bee_parameters *p = &para;
+
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+	enum dcache_option option = DCACHE_WRITETHROUGH;
+#else
+	enum dcache_option option = DCACHE_WRITEBACK;
+#endif
+
+	if (argc > 5)
+		return CMD_RET_USAGE;
+
+	if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
+		if (check_module_fused(MODULE_BEE)) {
+			printf("BEE is fused, disable it!\n");
+			return CMD_RET_FAILURE;
+		}
+	}
+
+	/* Cache enabled? */
+	if ((get_cr() & (CR_I | CR_C)) != (CR_I | CR_C)) {
+		/*
+		 * Here we need icache and dcache both enabled, because
+		 * we may take the protected region for instruction and
+		 * data usage. And icache and dcache both enabled are
+		 * better for performance.
+		 */
+		printf("Please enable dcache and icache first!\n");
+		return CMD_RET_FAILURE;
+	}
+
+	p->key_method = SOFT_KEY;
+	p->mode = ECB_MODE;
+	p->start1 = PHYS_SDRAM;
+	p->size1 = SZ_512M;
+	p->start2 = IRAM_BASE_ADDR;
+	p->size2 = IRAM_SIZE;
+
+	if (argc == 2) {
+		p->key_method = (int)simple_strtoul(argv[1], NULL, 16);
+		p->mode = ECB_MODE;
+		p->start1 = PHYS_SDRAM;
+		p->size1 = SZ_512M;
+	} else if (argc == 3) {
+		p->key_method = (int)simple_strtoul(argv[1], NULL, 16);
+		p->mode = (int)simple_strtoul(argv[2], NULL, 10);
+		p->start1 = PHYS_SDRAM;
+		p->size1 = SZ_512M;
+	} else if ((argc == 4) || (argc == 5)) {
+		p->key_method = (int)simple_strtoul(argv[1], NULL, 16);
+		p->mode = (int)simple_strtoul(argv[2], NULL, 10);
+		start = (u32)simple_strtoul(argv[3], NULL, 16);
+		/* Default size that AES Region0 can protected */
+		size = SZ_512M;
+		if (argc == 5)
+			size = (u32)simple_strtoul(argv[4], NULL, 16);
+		p->start1 = start;
+		p->size1 = size;
+	}
+
+	if ((p->key_method != SOFT_KEY) && (p->key_method != SNVS_KEY))
+		return CMD_RET_USAGE;
+
+	if ((p->mode != ECB_MODE) && (p->mode != CTR_MODE))
+		return CMD_RET_USAGE;
+
+	/*
+	 * No need to check region valid for IRAM, since it is fixed.
+	 * Only check DRAM region here.
+	 */
+	if (region_valid(p->start1, p->size1))
+		return CMD_RET_FAILURE;
+
+	ret = bee_init(p);
+	if (ret)
+		return CMD_RET_FAILURE;
+
+	/*
+	 * Set DCACHE OFF to AES REGION0 and AES REGION1 first
+	 * to avoid possible unexcepted cache settings.
+	 */
+	mmu_set_region_dcache_behaviour(AES_REGION0_ADDR, SZ_1G, DCACHE_OFF);
+
+	mmu_set_region_dcache_behaviour(AES_REGION0_ADDR, p->size1, option);
+
+	mmu_set_region_dcache_behaviour(AES_REGION1_ADDR, p->size2, option);
+
+	printf("Access Region 0x%x - 0x%x to protect 0x%x - 0x%x\n"
+	       "Do not directly access 0x%x - 0x%x\n"
+	       "Access Region 0x%x - 0x%x to protect 0x%x - 0x%x\n"
+	       "Do not directly access 0x%x - 0x%x\n",
+	       AES_REGION0_ADDR, AES_REGION0_ADDR + p->size1 - 1,
+	       p->start1, p->start1 + p->size1 - 1,
+	       p->start1, p->start1 + p->size1 - 1,
+	       AES_REGION1_ADDR, AES_REGION1_ADDR + p->size2 - 1,
+	       p->start2, p->start2 + p->size2 - 1,
+	       p->start2, p->start2 + p->size2 - 1);
+
+	bee_inited = 1;
+
+	return CMD_RET_SUCCESS;
+}
+
+static int do_bee_test(struct cmd_tbl *cmdtp, int flag, int argc,
+		       char * const argv[])
+{
+	int ret;
+	int region;
+
+	if (bee_inited == 0) {
+		printf("Bee not initialized, run bee init first!\n");
+		return CMD_RET_FAILURE;
+	}
+	if (argc > 2)
+		return CMD_RET_USAGE;
+
+	region = 0;
+	if (argc == 2)
+		region = (int)simple_strtoul(argv[1], NULL, 16);
+	/* Only two regions are supported, 0 and 1 */
+	if (region >= 2)
+		return CMD_RET_USAGE;
+
+	ret = bee_test(&para, region);
+	if (ret)
+		return CMD_RET_FAILURE;
+
+	return CMD_RET_SUCCESS;
+}
+
+static struct cmd_tbl cmd_bmp_sub[] = {
+	U_BOOT_CMD_MKENT(init, 5, 0, do_bee_init, "", ""),
+	U_BOOT_CMD_MKENT(test, 2, 0, do_bee_test, "", ""),
+};
+
+static int do_bee_ops(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct cmd_tbl *c;
+
+	c = find_cmd_tbl(argv[1], &cmd_bmp_sub[0], ARRAY_SIZE(cmd_bmp_sub));
+
+	/* Drop off the 'bee' command argument */
+	argc--;
+	argv++;
+
+	if (c)
+		return  c->cmd(cmdtp, flag, argc, argv);
+	else
+		return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+	bee, CONFIG_SYS_MAXARGS, 1, do_bee_ops,
+	"BEE function test",
+	"init [key] [mode] [start] [size]	- BEE block initial\n"
+	"  key: 0 | 1, 0 means software key, 1 means SNVS random key\n"
+	"  mode: 0 | 1, 0 means ECB mode, 1 means CTR mode\n"
+	"  start: start address that you want to protect\n"
+	"  size: The size of the area that you want to protect\n"
+	"  start and end(start + size) addr both should be 64KB aligned.\n"
+	"\n"
+	" After initialization, the mapping:\n"
+	" 1. [0x10000000 - (0x10000000 + size - 1)] <--->\n"
+	"    [start - (start + size - 1)]\n"
+	"    Here [start - (start + size -1)] is fixed mapping to\n"
+	"    [0x10000000 - (0x10000000 + size - 1)], whatever start is.\n"
+	" 2. [0x30000000 - (0x30000000 + IRAM_SIZE - 1)] <--->\n"
+	"    [IRAM_BASE_ADDR - (IRAM_BASE_ADDR + IRAM_SIZE - 1)]\n"
+	"\n"
+	" Note: Here we only use AES region 0 to protect the DRAM\n"
+	"       area that you specified, max size SZ_512M.\n"
+	"       AES region 1 is used to protect IRAM area.\n"
+	" Example:\n"
+	" 1. bee init 1 1 0xa0000000 0x10000\n"
+	"    Access 0x10000000 - 0x10010000 to protect 0xa0000000 - 0xa0010000\n"
+	" 2. bee init 1 1 0x80000000 0x20000\n"
+	"    Access 0x10000000 - 0x10020000 to protect 0x80000000 - 0x80020000\n"
+	"\n"
+	" Default configuration if only `bee init` without any args:\n"
+	" 1. software key\n"
+	" 2. ECB mode\n"
+	" 3. Address protected:\n"
+	"   Remapped Region0: PHYS_SDRAM - PHYS_SDRAM + SZ_512M\n"
+	"   Remapped Region1: IRAM_BASE_ADDR - IRAM_BASE_ADDR + IRAM_SIZE\n"
+	" 4. Default Mapping for 6UL:\n"
+	"   [0x10000000 - 0x2FFFFFFF] <-> [0x80000000 - 0x9FFFFFFF]\n"
+	"   [0x30000000 - 0x3001FFFF] <-> [0x00900000 - 0x0091FFFF]\n"
+	"\n"
+	"bee test [region]			- BEE function test\n"
+	"  region: 0 | 1, 0 means region0, 1 means regions1\n"
+);
+
diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
index cb9d629be40..6d454565f30 100644
--- a/arch/arm/mach-imx/mx6/clock.c
+++ b/arch/arm/mach-imx/mx6/clock.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
  */
 
 #include <common.h>
@@ -60,6 +61,12 @@ void setup_gpmi_io_clk(u32 cfg)
 			cfg);
 
 	setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
+#elif defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+	clrsetbits_le32(&imx_ccm->cs2cdr,
+			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+			cfg);
 #else
 	clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 
@@ -647,7 +654,8 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 	if (is_mx6sx()) {
 		reg = readl(&imx_ccm->cscdr2);
 		/* Can't change clocks when clock not from pre-mux */
-		if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
+		if ((base_addr == LCDIF2_BASE_ADDR) &&
+			(reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
 			return;
 	}
 
@@ -851,6 +859,50 @@ int enable_lcdif_clock(u32 base_addr, bool enable)
 
 	return 0;
 }
+
+int enable_lvds_clock(u32 lcd_base_addr)
+{
+	u32 reg = 0;
+
+	if (is_cpu_type(MXC_CPU_MX6SX)) {
+		if ((lcd_base_addr != LCDIF1_BASE_ADDR) &&
+		    (lcd_base_addr != LCDIF2_BASE_ADDR)) {
+			puts("Wrong LCD interface!\n");
+			return -EINVAL;
+		}
+	} else {
+		debug("This chip not support lvds bridge!\n");
+		return 0;
+	}
+
+	/* Turn on LDB DI0 clocks */
+	reg = readl(&imx_ccm->CCGR3);
+	reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
+	writel(reg, &imx_ccm->CCGR3);
+
+	/* set LDB DI0 clk select to 011 PLL2 PFD3 200M*/
+	reg = readl(&imx_ccm->cs2cdr);
+	reg &= ~MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
+	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET);
+	writel(reg, &imx_ccm->cs2cdr);
+
+	reg = readl(&imx_ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+	writel(reg, &imx_ccm->cscmr2);
+
+	/* set LDB DI0 clock for LCDIF PIX clock */
+	reg = readl(&imx_ccm->cscdr2);
+	if (lcd_base_addr == LCDIF1_BASE_ADDR) {
+		reg &= ~MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
+		reg |= (0x3 << MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET);
+	} else {
+		reg &= ~MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK;
+		reg |= (0x3 << MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET);
+	}
+	writel(reg, &imx_ccm->cscdr2);
+	return 0;
+}
+
 #endif
 
 #ifdef CONFIG_FSL_QSPI
@@ -903,6 +955,18 @@ void enable_qspi_clk(int qspi_num)
 }
 #endif
 
+#if defined(CONFIG_VIDEO_GIS)
+void mxs_set_vadcclk()
+{
+	u32 reg = 0;
+
+	reg = readl(&imx_ccm->cscmr2);
+	reg &= ~MXC_CCM_CSCMR2_VID_CLK_SEL_MASK;
+	reg |= 0x19 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET;
+	writel(reg, &imx_ccm->cscmr2);
+}
+#endif
+
 #ifdef CONFIG_FEC_MXC
 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 {
@@ -1043,7 +1107,7 @@ u32 imx_get_fecclk(void)
 	return mxc_get_clock(MXC_IPG_CLK);
 }
 
-#if defined(CONFIG_SATA) || defined(CONFIG_PCIE_IMX)
+#if defined(CONFIG_SATA) || defined(CONFIG_IMX_AHCI) || defined(CONFIG_PCIE_IMX)
 static int enable_enet_pll(uint32_t en)
 {
 	struct mxc_ccm_reg *const imx_ccm
@@ -1070,7 +1134,7 @@ static int enable_enet_pll(uint32_t en)
 }
 #endif
 
-#ifdef CONFIG_SATA
+#if defined(CONFIG_SATA) || defined(CONFIG_IMX_AHCI)
 static void ungate_sata_clock(void)
 {
 	struct mxc_ccm_reg *const imx_ccm =
@@ -1096,6 +1160,15 @@ void disable_sata_clock(void)
 #endif
 
 #ifdef CONFIG_PCIE_IMX
+static void ungate_disp_axi_clock(void)
+{
+	struct mxc_ccm_reg *const imx_ccm =
+		(struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* Enable display axi clock. */
+	setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_DISP_AXI_MASK);
+}
+
 static void ungate_pcie_clock(void)
 {
 	struct mxc_ccm_reg *const imx_ccm =
@@ -1143,14 +1216,22 @@ int enable_pcie_clock(void)
 	/* PCIe reference clock sourced from AXI. */
 	clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 
+	if (!is_mx6sx()) {
 	/* Party time! Ungate the clock to the PCIe. */
-#ifdef CONFIG_SATA
-	ungate_sata_clock();
+#if defined(CONFIG_SATA) || defined(CONFIG_IMX_AHCI)
+		ungate_sata_clock();
 #endif
-	ungate_pcie_clock();
+		ungate_pcie_clock();
 
-	return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
-			       BM_ANADIG_PLL_ENET_ENABLE_PCIE);
+		return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
+				       BM_ANADIG_PLL_ENET_ENABLE_PCIE);
+	} else {
+		/* Party time! Ungate the clock to the PCIe. */
+		ungate_disp_axi_clock();
+		ungate_pcie_clock();
+
+		return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_PCIE);
+	}
 }
 #endif
 
@@ -1341,7 +1422,7 @@ int do_mx6_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
 }
 
 #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \
-	defined(CONFIG_MX6S) || defined(CONFIG_MX6QDL)
+	defined(CONFIG_MX6S) || defined(CONFIG_MX6QDL) || defined(CONFIG_MX6QP)
 static void disable_ldb_di_clock_sources(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -1490,6 +1571,38 @@ void select_ldb_di_clock_source(enum ldb_di_clock clk)
 }
 #endif
 
+
+#if defined(CONFIG_MXC_EPDC)
+#if defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)
+void enable_epdc_clock(void)
+{
+	u32 reg = 0;
+
+	/* disable the clock gate first */
+	clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK);
+
+	/* PLL3_PFD2 */
+	reg = readl(&imx_ccm->chsccdr);
+	reg &= ~MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK;
+	reg |= 5 << MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET;
+	writel(reg, &imx_ccm->chsccdr);
+
+	reg = readl(&imx_ccm->chsccdr);
+	reg &= ~MXC_CCM_CHSCCDR_EPDC_PODF_MASK;
+	reg |= 7 << MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET;
+	writel(reg, &imx_ccm->chsccdr);
+
+	reg = readl(&imx_ccm->chsccdr);
+	reg &= ~MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK;
+	reg |= 0 <<MXC_CCM_CHSCCDR_EPDC_CLK_SEL_OFFSET;
+	writel(reg, &imx_ccm->chsccdr);
+
+	/* enable the clock gate */
+	setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK);
+}
+#endif
+#endif
+
 /***************************************************/
 
 U_BOOT_CMD(
diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c
index f872bfdab31..704869cbdd9 100644
--- a/arch/arm/mach-imx/mx6/ddr.c
+++ b/arch/arm/mach-imx/mx6/ddr.c
@@ -780,7 +780,7 @@ void mx6sl_dram_iocfg(unsigned width,
 }
 #endif
 
-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6QP)
 /* Configure MX6DQ mmdc iomux */
 void mx6dq_dram_iocfg(unsigned width,
 		      const struct mx6dq_iomux_ddr_regs *ddr,
diff --git a/arch/arm/mach-imx/mx6/module_fuse.c b/arch/arm/mach-imx/mx6/module_fuse.c
index 0f4565e3117..c24d8279eda 100644
--- a/arch/arm/mach-imx/mx6/module_fuse.c
+++ b/arch/arm/mach-imx/mx6/module_fuse.c
@@ -13,6 +13,45 @@
 
 static struct fuse_entry_desc mx6_fuse_descs[] = {
 #if defined(CONFIG_MX6ULL)
+	{MODULE_TSC, "/soc/bus@2000000/tsc@2040000", 0x430, 22},
+	{MODULE_ADC2, "/soc/bus@2100000/adc@219c000", 0x430, 23},
+	{MODULE_EPDC, "/soc/bus@2200000/epdc@228c000", 0x430, 24},
+	{MODULE_ESAI, "/soc/bus@2000000/spba-bus@2000000/esai@2024000", 0x430, 25},
+	{MODULE_FLEXCAN1, "/soc/bus@2000000/can@2090000", 0x430, 26},
+	{MODULE_FLEXCAN2, "/soc/bus@2000000/can@2094000", 0x430, 27},
+	{MODULE_SPDIF, "/soc/bus@2000000/spba-bus@2000000/spdif@2004000", 0x440, 2},
+	{MODULE_EIM, "/soc/bus@2100000/weim@21b8000", 0x440, 3},
+	{MODULE_SD1, "/soc/bus@2100000/usdhc@2190000", 0x440, 4},
+	{MODULE_SD2, "/soc/bus@2100000/usdhc@2194000", 0x440, 5},
+	{MODULE_QSPI1, "/soc/bus@2100000/qspi@21e0000", 0x440, 6},
+	{MODULE_GPMI, "/soc/nand-controller@1806000", 0x440, 7},
+	{MODULE_APBHDMA, "/soc/dma-apbh@1804000", 0x440, 7},
+	{MODULE_LCDIF, "/soc/bus@2100000/lcdif@21c8000", 0x440, 8},
+	{MODULE_PXP, "/soc/bus@2100000/pxp@21cc000", 0x440, 9},
+	{MODULE_CSI, "/soc/bus@2100000/csi@21c4000", 0x440, 10},
+	{MODULE_ADC1, "/soc/bus@2100000/adc@2198000", 0x440, 11},
+	{MODULE_ENET1, "/soc/bus@2100000/ethernet@2188000", 0x440, 12},
+	{MODULE_ENET2, "/soc/bus@2000000/ethernet@20b4000", 0x440, 13},
+	{MODULE_DCP, "/soc/bus@2200000/dcp@2280000", 0x440, 14},
+	{MODULE_USB_OTG2, "/soc/bus@2100000/usb@2184200", 0x440, 15},
+	{MODULE_SAI2, "/soc/bus@2000000/spba-bus@2000000/sai@202c000", 0x440, 24},
+	{MODULE_SAI3, "/soc/bus@2000000/spba-bus@2000000/sai@2030000", 0x440, 24},
+	{MODULE_DCP_CRYPTO, "/soc/bus@2200000/dcp@2280000", 0x440, 25},
+	{MODULE_UART5, "/soc/bus@2100000/serial@21f4000", 0x440, 26},
+	{MODULE_UART6, "/soc/bus@2100000/serial@21fc000", 0x440, 26},
+	{MODULE_UART7, "/soc/bus@2000000/spba-bus@2000000/serial@2018000", 0x440, 26},
+	{MODULE_UART8, "/soc/bus@2200000/serial@2288000", 0x440, 26},
+	{MODULE_PWM5, "/soc/bus@2000000/pwm@20f0000", 0x440, 27},
+	{MODULE_PWM6, "/soc/bus@2000000/pwm@20f4000", 0x440, 27},
+	{MODULE_PWM7, "/soc/bus@2000000/pwm@20f8000", 0x440, 27},
+	{MODULE_PWM8, "/soc/bus@2000000/pwm@20fc000", 0x440, 27},
+	{MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/ecspi@2010000", 0x440, 28},
+	{MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/ecspi@2014000", 0x440, 28},
+	{MODULE_I2C3, "/soc/bus@2100000/i2c@21a8000", 0x440, 29},
+	{MODULE_I2C4, "/soc/bus@2100000/i2c@21f8000", 0x440, 29},
+	{MODULE_GPT2, "/soc/bus@2000000/gpt@20e8000", 0x440, 30},
+	{MODULE_EPIT2, "/soc/bus@2000000/epit@20d4000", 0x440, 31},
+
 	{MODULE_TSC, "/soc/aips-bus@2000000/tsc@2040000", 0x430, 22},
 	{MODULE_ADC2, "/soc/aips-bus@2100000/adc@219c000", 0x430, 23},
 	{MODULE_EPDC, "/soc/aips-bus@2200000/epdc@228c000", 0x430, 24},
@@ -91,6 +130,45 @@ static struct fuse_entry_desc mx6_fuse_descs[] = {
 	{MODULE_GPT2, "/soc/aips-bus@02000000/gpt@020e8000", 0x440, 30},
 	{MODULE_EPIT2, "/soc/aips-bus@02000000/epit@020d4000", 0x440, 31},
 #elif defined(CONFIG_MX6UL)
+	{MODULE_TSC, "/soc/bus@2000000/tsc@2040000", 0x430, 22},
+	{MODULE_ADC2, "/soc/bus@2100000/adc@219c000", 0x430, 23},
+	{MODULE_SIM1, "/soc/bus@2100000/sim@218c000", 0x430, 24},
+	{MODULE_SIM2, "/soc/bus@2100000/sim@21b4000", 0x430, 25},
+	{MODULE_FLEXCAN1, "/soc/bus@2000000/can@2090000", 0x430, 26},
+	{MODULE_FLEXCAN2, "/soc/bus@2000000/can@2094000", 0x430, 27},
+	{MODULE_SPDIF, "/soc/bus@2000000/spba-bus@2000000/spdif@2004000", 0x440, 2},
+	{MODULE_EIM, "/soc/bus@2100000/weim@21b8000", 0x440, 3},
+	{MODULE_SD1, "/soc/bus@2100000/usdhc@2190000", 0x440, 4},
+	{MODULE_SD2, "/soc/bus@2100000/usdhc@2194000", 0x440, 5},
+	{MODULE_QSPI1, "/soc/bus@2100000/qspi@21e0000", 0x440, 6},
+	{MODULE_GPMI, "/soc/nand-controller@1806000", 0x440, 7},
+	{MODULE_APBHDMA, "/soc/dma-apbh@1804000", 0x440, 7},
+	{MODULE_LCDIF, "/soc/bus@2100000/lcdif@21c8000", 0x440, 8},
+	{MODULE_PXP, "/soc/bus@2100000/pxp@21cc000", 0x440, 9},
+	{MODULE_CSI, "/soc/bus@2100000/csi@21c4000", 0x440, 10},
+	{MODULE_ADC1, "/soc/bus@2100000/adc@2198000", 0x440, 11},
+	{MODULE_ENET1, "/soc/bus@2100000/ethernet@2188000", 0x440, 12},
+	{MODULE_ENET2, "/soc/bus@2000000/ethernet@20b4000", 0x440, 13},
+	{MODULE_CAAM, "/soc/bus@2100000/caam@2140000", 0x440, 14},
+	{MODULE_USB_OTG2, "/soc/bus@2100000/usb@2184200", 0x440, 15},
+	{MODULE_SAI2, "/soc/bus@2000000/spba-bus@2000000/sai@202c000", 0x440, 24},
+	{MODULE_SAI3, "/soc/bus@2000000/spba-bus@2000000/sai@2030000", 0x440, 24},
+	{MODULE_BEE, "/soc/bus@2000000/bee@2044000", 0x440, 25},
+	{MODULE_UART5, "/soc/bus@2100000/serial@21f4000", 0x440, 26},
+	{MODULE_UART6, "/soc/bus@2100000/serial@21fc000", 0x440, 26},
+	{MODULE_UART7, "/soc/bus@2000000/spba-bus@2000000/serial@2018000", 0x440, 26},
+	{MODULE_UART8, "/soc/bus@2000000/spba-bus@2000000/serial@2024000", 0x440, 26},
+	{MODULE_PWM5, "/soc/bus@2000000/pwm@20f0000", 0x440, 27},
+	{MODULE_PWM6, "/soc/bus@2000000/pwm@20f4000", 0x440, 27},
+	{MODULE_PWM7, "/soc/bus@2000000/pwm@20f8000", 0x440, 27},
+	{MODULE_PWM8, "/soc/bus@2000000/pwm@20fc000", 0x440, 27},
+	{MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/ecspi@2010000", 0x440, 28},
+	{MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/ecspi@2014000", 0x440, 28},
+	{MODULE_I2C3, "/soc/bus@2100000/i2c@21a8000", 0x440, 29},
+	{MODULE_I2C4, "/soc/bus@2100000/i2c@21f8000", 0x440, 29},
+	{MODULE_GPT2, "/soc/bus@2000000/gpt@20e8000", 0x440, 30},
+	{MODULE_EPIT2, "/soc/bus@2000000/epit@20d4000", 0x440, 31},
+
 	{MODULE_TSC, "/soc/aips-bus@2000000/tsc@2040000", 0x430, 22},
 	{MODULE_ADC2, "/soc/aips-bus@2100000/adc@219c000", 0x430, 23},
 	{MODULE_SIM1, "/soc/aips-bus@2100000/sim@218c000", 0x430, 24},
@@ -129,6 +207,7 @@ static struct fuse_entry_desc mx6_fuse_descs[] = {
 	{MODULE_I2C4, "/soc/aips-bus@2100000/i2c@21f8000", 0x440, 29},
 	{MODULE_GPT2, "/soc/aips-bus@2000000/gpt@20e8000", 0x440, 30},
 	{MODULE_EPIT2, "/soc/aips-bus@2000000/epit@20d4000", 0x440, 31},
+
 	/* Paths for older imx tree: */
 	{MODULE_TSC, "/soc/aips-bus@02000000/tsc@02040000", 0x430, 22},
 	{MODULE_ADC2, "/soc/aips-bus@02100000/adc@0219c000", 0x430, 23},
@@ -206,7 +285,7 @@ int ft_system_setup(void *blob, struct bd_info *bd)
 			if (off < 0)
 				continue; /* Not found, skip it */
 add_status:
-			rc = fdt_setprop(blob, nodeoff, "status", status,
+			rc = fdt_setprop(blob, off, "status", status,
 					 strlen(status) + 1);
 			if (rc) {
 				if (rc == -FDT_ERR_NOSPACE) {
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index 03d6b8c1ce9..9bf16119c20 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -4,6 +4,7 @@
  * Sascha Hauer, Pengutronix
  *
  * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2018-2021 NXP
  */
 
 #include <common.h>
@@ -26,6 +27,14 @@
 #include <fsl_sec.h>
 #include <imx_thermal.h>
 #include <mmc.h>
+#include <asm/setup.h>
+#include <hang.h>
+#include <cpu_func.h>
+#include <env.h>
+#include<dm/device-internal.h>
+#include<dm/lists.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 #define has_err007805() \
 	(is_mx6sl() || is_mx6dl() || is_mx6solo() || is_mx6ull())
@@ -234,6 +243,35 @@ u32 __weak get_board_rev(void)
 }
 #endif
 
+#ifdef CONFIG_IMX_TRUSTY_OS
+#ifdef CONFIG_MX6UL
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+           return;
+}
+
+void smp_waitloop(unsigned previous_address)
+{
+           return;
+}
+#endif
+#endif
+
+static void init_csu(void)
+{
+#ifdef CONFIG_ARMV7_NONSEC
+	int i;
+	u32 csu = CSU_BASE_ADDR;
+	/*
+	 * This is to allow device can be accessed in non-secure world.
+	 * All imx6 chips CSU have 40 Config security level registers.
+	 */
+	for (i = 0; i < 40; i ++) {
+	    *((u32 *)csu + i) = 0xffffffff;
+	}
+#endif
+}
+
 static void clear_ldo_ramp(void)
 {
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
@@ -356,28 +394,26 @@ static void init_bandgap(void)
 	/*
 	 * On i.MX6ULL,we need to set VBGADJ bits according to the
 	 * REFTOP_TRIM[3:0] in fuse table
-	 *	000 - set REFTOP_VBGADJ[2:0] to 3b'110,
-	 *	110 - set REFTOP_VBGADJ[2:0] to 3b'000,
-	 *	001 - set REFTOP_VBGADJ[2:0] to 3b'001,
-	 *	010 - set REFTOP_VBGADJ[2:0] to 3b'010,
-	 *	011 - set REFTOP_VBGADJ[2:0] to 3b'011,
-	 *	100 - set REFTOP_VBGADJ[2:0] to 3b'100,
-	 *	101 - set REFTOP_VBGADJ[2:0] to 3b'101,
-	 *	111 - set REFTOP_VBGADJ[2:0] to 3b'111,
+	 *	000 - set REFTOP_VBGADJ[2:0] to 3'b000
+	 *	001 - set REFTOP_VBGADJ[2:0] to 3'b001
+	 *	010 - set REFTOP_VBGADJ[2:0] to 3'b010
+	 *	011 - set REFTOP_VBGADJ[2:0] to 3'b011
+	 *	100 - set REFTOP_VBGADJ[2:0] to 3'b100
+	 *	101 - set REFTOP_VBGADJ[2:0] to 3'b101
+	 *	110 - set REFTOP_VBGADJ[2:0] to 3'b110
+	 *	111 - set REFTOP_VBGADJ[2:0] to 3'b111
 	 */
 	if (is_mx6ull()) {
-		static const u32 map[] = {6, 1, 2, 3, 4, 5, 0, 7};
-
 		val = readl(&fuse->mem0);
 		val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
 		val &= 0x7;
 
-		writel(map[val] << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
+		writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
 		       &anatop->ana_misc0_set);
 	}
 }
 
-#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
+#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL) || defined(CONFIG_MX6QP)
 static void noc_setup(void)
 {
 	enable_ipu_clock();
@@ -408,12 +444,144 @@ static void noc_setup(void)
 }
 #endif
 
+#ifdef CONFIG_MX6SX
+void vadc_power_up(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	u32 val;
+
+	/* csi0 */
+	val = readl(&iomux->gpr[5]);
+	val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK,
+	val |= IMX6SX_GPR5_CSI1_MUX_CTRL_CVD;
+	writel(val, &iomux->gpr[5]);
+
+	/* Power on vadc analog
+	 * Power down vadc ext power */
+	val = readl(GPC_BASE_ADDR + 0);
+	val &= ~0x60000;
+	writel(val, GPC_BASE_ADDR + 0);
+
+	/* software reset afe  */
+	val = readl(&iomux->gpr[1]);
+	writel(val | 0x80000, &iomux->gpr[1]);
+
+	udelay(10*1000);
+
+	/* Release reset bit  */
+	writel(val & ~0x80000, &iomux->gpr[1]);
+
+	/* Power on vadc ext power */
+	val = readl(GPC_BASE_ADDR + 0);
+	val |= 0x40000;
+	writel(val, GPC_BASE_ADDR + 0);
+}
+
+void vadc_power_down(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	u32 val;
+
+	/* Power down vadc ext power
+	 * Power off vadc analog */
+	val = readl(GPC_BASE_ADDR + 0);
+	val &= ~0x40000;
+	val |= 0x20000;
+	writel(val, GPC_BASE_ADDR + 0);
+
+	/* clean csi0 connect to vadc  */
+	val = readl(&iomux->gpr[5]);
+	val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK,
+	writel(val, &iomux->gpr[5]);
+}
+
+void pcie_power_up(void)
+{
+	set_ldo_voltage(LDO_PU, 1100);	/* Set VDDPU to 1.1V */
+}
+
+void pcie_power_off(void)
+{
+	set_ldo_voltage(LDO_PU, 0);	/* Set VDDPU to 1.1V */
+}
+#endif
+
+static void imx_set_vddpu_power_down(void)
+{
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	u32 val;
+
+	/* need to power down xPU in GPC before turn off PU LDO */
+	val = readl(GPC_BASE_ADDR + 0x260);
+	writel(val | 0x1, GPC_BASE_ADDR + 0x260);
+
+	val = readl(GPC_BASE_ADDR + 0x0);
+	writel(val | 0x1, GPC_BASE_ADDR + 0x0);
+	while (readl(GPC_BASE_ADDR + 0x0) & 0x1)
+		;
+
+	/* disable VDDPU */
+	val = 0x3e00;
+	writel(val, &anatop->reg_core_clr);
+}
+
+static void imx_set_pcie_phy_power_down(void)
+{
+	u32 val;
+
+	if (!is_cpu_type(MXC_CPU_MX6SX)) {
+		val = readl(IOMUXC_BASE_ADDR + 0x4);
+		val |= 0x1 << 18;
+		writel(val, IOMUXC_BASE_ADDR + 0x4);
+	} else {
+		val = readl(IOMUXC_GPR_BASE_ADDR + 0x30);
+		val |= 0x1 << 30;
+		writel(val, IOMUXC_GPR_BASE_ADDR + 0x30);
+	}
+}
+
+bool is_usb_boot(void)
+{
+	if (gd->flags & GD_FLG_ARCH_IMX_USB_BOOT)
+		return true;
+
+	return false;
+}
+
 int arch_cpu_init(void)
 {
 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
+	if (is_usbphy_power_on())
+		gd->flags |= GD_FLG_ARCH_IMX_USB_BOOT;
+
+	if (!is_mx6sl() && !is_mx6sx()
+		&& !is_mx6ul() && !is_mx6ull()
+		&& !is_mx6sll()) {
+		/*
+		 * imx6sl doesn't have pcie at all.
+		 * this bit is not used by imx6sx anymore
+		 */
+		u32 val;
+
+		/*
+		 * There are about 0.02% percentage, random pcie link down
+		 * when warm-reset is used.
+		 * clear the ref_ssp_en bit16 of gpr1 to workaround it.
+		 * then warm-reset imx6q/dl/solo again.
+		 */
+		val = readl(IOMUXC_BASE_ADDR + 0x4);
+		if (val & (0x1 << 16)) {
+			val &= ~(0x1 << 16);
+			writel(val, IOMUXC_BASE_ADDR + 0x4);
+			reset_cpu();
+		}
+	}
+
 	init_aips();
 
+	init_csu();
+
 	/* Need to clear MMDC_CHx_MASK to make warm reset work. */
 	clear_mmdc_ch_mask();
 
@@ -483,22 +651,34 @@ int arch_cpu_init(void)
 	if (is_mx6sx())
 		setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL);
 
+	if (!is_mx6sl() && !is_mx6ul() &&
+		!is_mx6ull() && !is_mx6sll())
+		imx_set_pcie_phy_power_down();
+
+	if (!is_mx6dqp() && !is_mx6ul() &&
+		!is_mx6ull() && !is_mx6sll())
+		imx_set_vddpu_power_down();
+
 	init_src();
 
-#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
+#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL) || defined(CONFIG_MX6QP)
 	if (is_mx6dqp())
 		noc_setup();
 #endif
 
 	enable_ca7_smp();
+	configure_tzc380();
 
 	return 0;
 }
 
-#ifdef CONFIG_ENV_IS_IN_MMC
+#ifndef CONFIG_SYS_MMC_ENV_DEV
+#define CONFIG_SYS_MMC_ENV_DEV -1
+#endif
+
 __weak int board_mmc_get_env_dev(int devno)
 {
-	return CONFIG_SYS_MMC_ENV_DEV;
+	return devno;
 }
 
 static int mmc_get_boot_dev(void)
@@ -516,7 +696,7 @@ static int mmc_get_boot_dev(void)
 	bootsel = (soc_sbmr & 0x000000FF) >> 6;
 
 	/* No boot from sd/mmc */
-	if (bootsel != 1)
+	if (is_usb_boot() || bootsel != 1)
 		return -1;
 
 	/* BOOT_CFG2[3] and BOOT_CFG2[4] */
@@ -531,7 +711,7 @@ int mmc_get_env_dev(void)
 
 	/* If not boot from sd/mmc, use default value */
 	if (devno < 0)
-		return CONFIG_SYS_MMC_ENV_DEV;
+	    return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV);
 
 	return board_mmc_get_env_dev(devno);
 }
@@ -553,7 +733,6 @@ uint mmc_get_env_part(struct mmc *mmc)
 	return board_mmc_get_env_part(devno);
 }
 #endif
-#endif
 
 int board_postclk_init(void)
 {
@@ -566,6 +745,19 @@ int board_postclk_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[0];
+	struct fuse_bank0_regs *fuse =
+		(struct fuse_bank0_regs *)bank->fuse_regs;
+
+	serialnr->low = fuse->uid_low;
+	serialnr->high = fuse->uid_high;
+}
+#endif
+
 #ifndef CONFIG_SPL_BUILD
 /*
  * cfg_val will be used for
@@ -579,7 +771,7 @@ const struct boot_mode soc_boot_modes[] = {
 #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 	{"usb",		MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
 #else
-	{"usb",		MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+	{"usb",		MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
 #endif
 	{"sata",	MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
 	{"ecspi1:0",	MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
@@ -595,6 +787,71 @@ const struct boot_mode soc_boot_modes[] = {
 };
 #endif
 
+enum boot_device get_boot_device(void)
+{
+	enum boot_device boot_dev = UNKNOWN_BOOT;
+	uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
+	uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
+	uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
+	uint bt_dev_port = (soc_sbmr & 0x00001800) >> 11;
+
+	switch (bt_mem_ctl) {
+	case 0x0:
+		if (bt_mem_type)
+			boot_dev = ONE_NAND_BOOT;
+		else
+			boot_dev = WEIM_NOR_BOOT;
+		break;
+	case 0x2:
+			boot_dev = SATA_BOOT;
+		break;
+	case 0x3:
+		if (bt_mem_type)
+			boot_dev = I2C_BOOT;
+		else
+			boot_dev = SPI_NOR_BOOT;
+		break;
+	case 0x4:
+	case 0x5:
+		boot_dev = bt_dev_port + SD1_BOOT;
+		break;
+	case 0x6:
+	case 0x7:
+		boot_dev = bt_dev_port + MMC1_BOOT;
+		break;
+	case 0x8 ... 0xf:
+		boot_dev = NAND_BOOT;
+		break;
+	default:
+		boot_dev = UNKNOWN_BOOT;
+		break;
+	}
+
+    return boot_dev;
+}
+
+void set_wdog_reset(struct wdog_regs *wdog)
+{
+	u32 reg = readw(&wdog->wcr);
+	/*
+	 * use WDOG_B mode to reset external pmic because it's risky for the
+	 * following watchdog reboot in case of cpu freq at lowest 400Mhz with
+	 * ldo-bypass mode. Because boot frequency maybe higher 800Mhz i.e. So
+	 * in ldo-bypass mode watchdog reset will only triger POR reset, not
+	 * WDOG reset. But below code depends on hardware design, if HW didn't
+	 * connect WDOG_B pin to external pmic such as i.mx6slevk, we can skip
+	 * these code since it assumed boot from 400Mhz always.
+	 */
+	reg = readw(&wdog->wcr);
+	reg |= 1 << 3;
+	/*
+	 * WDZST bit is write-once only bit. Align this bit in kernel,
+	 * otherwise kernel code will have no chance to set this bit.
+	 */
+	reg |= 1 << 0;
+	writew(reg, &wdog->wcr);
+}
+
 void reset_misc(void)
 {
 #ifndef CONFIG_SPL_BUILD
@@ -612,6 +869,10 @@ void s_init(void)
 	u32 mask528;
 	u32 reg, periph1, periph2;
 
+#if defined(CONFIG_ANDROID_SUPPORT)
+        /* Enable RTC */
+        writel(0x21, 0x020cc038);
+#endif
 	if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll())
 		return;
 
@@ -738,9 +999,28 @@ static void setup_serial_number(void)
 
 int arch_misc_init(void)
 {
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
+	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+		struct udevice *dev;
+		int ret;
+
+		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+		if (ret)
+			printf("Failed to initialize caam_jr: %d\n", ret);
+	}
+
+	if (IS_ENABLED(CONFIG_FSL_DCP_RNG)) {
+		struct udevice *dev;
+		int ret;
+
+		ret = device_bind_driver(NULL, "dcp_rng", "dcp_rng", NULL);
+		if (ret)
+			printf("Couldn't bind dcp rng driver (%d)\n", ret);
+
+		ret = uclass_get_device_by_driver(UCLASS_RNG, DM_DRIVER_GET(dcp_rng), &dev);
+		if (ret)
+			printf("Failed to initialize dcp rng: %d\n", ret);
+	}
+
 	setup_serial_number();
 	return 0;
 }
@@ -774,3 +1054,122 @@ void gpr_init(void)
 		writel(0x007F007F, &iomux->gpr[7]);
 	}
 }
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+DECLARE_GLOBAL_DATA_PTR;
+static int ldo_bypass;
+
+int check_ldo_bypass(void)
+{
+	const int *ldo_mode;
+	int node;
+
+	/* get the right fdt_blob from the global working_fdt */
+	gd->fdt_blob = working_fdt;
+	/* Get the node from FDT for anatop ldo-bypass */
+	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
+		"fsl,imx6q-gpc");
+	if (node < 0) {
+		printf("No gpc device node %d, force to ldo-enable.\n", node);
+		return 0;
+	}
+	ldo_mode = fdt_getprop(gd->fdt_blob, node, "fsl,ldo-bypass", NULL);
+	/*
+	 * return 1 if "fsl,ldo-bypass = <1>", else return 0 if
+	 * "fsl,ldo-bypass = <0>" or no "fsl,ldo-bypass" property
+	 */
+	ldo_bypass = fdt32_to_cpu(*ldo_mode) == 1 ? 1 : 0;
+
+	return ldo_bypass;
+}
+
+int check_1_2G(void)
+{
+	u32 reg;
+	int result = 0;
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[0];
+	struct fuse_bank0_regs *fuse_bank0 =
+			(struct fuse_bank0_regs *)bank->fuse_regs;
+
+	reg = readl(&fuse_bank0->cfg3);
+	if (((reg >> 16) & 0x3) == 0x3) {
+		if (ldo_bypass) {
+			printf("Wrong dtb file used! i.MX6Q@1.2Ghz only "
+				"works with ldo-enable mode!\n");
+			/*
+			 * Currently, only imx6q-sabresd board might be here,
+			 * since only i.MX6Q support 1.2G and only Sabresd board
+			 * support ldo-bypass mode. So hardcode here.
+			 * You can also modify your board(i.MX6Q) dtb name if it
+			 * supports both ldo-bypass and ldo-enable mode.
+			 */
+			printf("Please use imx6q-sabresd-ldo.dtb!\n");
+			hang();
+		}
+		result = 1;
+	}
+
+	return result;
+}
+
+static int arm_orig_podf;
+void set_arm_freq_400M(bool is_400M)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	if (is_400M)
+		writel(0x1, &mxc_ccm->cacrr);
+	else
+		writel(arm_orig_podf, &mxc_ccm->cacrr);
+}
+
+void prep_anatop_bypass(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	arm_orig_podf = readl(&mxc_ccm->cacrr);
+	/*
+	 * Downgrade ARM speed to 400Mhz as half of boot 800Mhz before ldo
+	 * bypassed, also downgrade internal vddarm ldo to 0.975V.
+	 * VDDARM_IN 0.975V + 125mV = 1.1V < Max(1.3V)
+	 * otherwise at 800Mhz(i.mx6dl):
+	 * VDDARM_IN 1.175V + 125mV = 1.3V = Max(1.3V)
+	 * We need provide enough gap in this case.
+	 * skip if boot from 400M.
+	 */
+	if (!arm_orig_podf)
+		set_arm_freq_400M(true);
+
+	if (!is_mx6dl() && !is_mx6sx())
+		set_ldo_voltage(LDO_ARM, 975);
+	else
+		set_ldo_voltage(LDO_ARM, 1150);
+}
+
+int set_anatop_bypass(int wdog_reset_pin)
+{
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	struct wdog_regs *wdog;
+	u32 reg = readl(&anatop->reg_core);
+
+	/* bypass VDDARM/VDDSOC */
+	reg = reg | (0x1F << 18) | 0x1F;
+	writel(reg, &anatop->reg_core);
+
+	if (wdog_reset_pin == 2)
+		wdog = (struct wdog_regs *) WDOG2_BASE_ADDR;
+	else if (wdog_reset_pin == 1)
+		wdog = (struct wdog_regs *) WDOG1_BASE_ADDR;
+	else
+		return arm_orig_podf;
+	set_wdog_reset(wdog);
+	return arm_orig_podf;
+}
+
+void finish_anatop_bypass(void)
+{
+	if (!arm_orig_podf)
+		set_arm_freq_400M(false);
+}
+#endif
diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
index 0cad825287c..e1278f497b3 100644
--- a/arch/arm/mach-imx/mx7/Kconfig
+++ b/arch/arm/mach-imx/mx7/Kconfig
@@ -31,6 +31,11 @@ config OPTEE_TZDRAM_SIZE
 	  The size of pre-allocated Trust Zone DRAM to allocate for the OPTEE
 	  runtime.
 
+config IMX_TAMPER
+	bool "Enable commands for SNVS tamper pin configuration and test"
+	help
+	  Set "Y" to enable the tamper commands
+
 choice
 	prompt "MX7 board select"
 	optional
@@ -68,6 +73,48 @@ config TARGET_MX7DSABRESD
 	select DM_THERMAL
 	select MX7D
 	imply CMD_DM
+	select FSL_CAAM
+	select FSL_BLOB
+
+config TARGET_MX7D_12X12_LPDDR3_VAL
+	bool "Support mx7d_12x12_lpddr3_val"
+	select BOARD_LATE_INIT
+	select MX7D
+	select DM
+	select DM_THERMAL
+	imply CMD_DM
+
+config TARGET_MX7D_12X12_DDR3_VAL
+	bool "Support mx7d_12x12_ddr3_val"
+	select BOARD_LATE_INIT
+	select MX7D
+	select DM
+	select DM_THERMAL
+	imply CMD_DM
+
+config TARGET_MX7D_19X19_DDR3_VAL
+	bool "Support mx7d_19x19_ddr3_val"
+	select BOARD_LATE_INIT
+	select MX7D
+	select DM
+	select DM_THERMAL
+	imply CMD_DM
+
+config TARGET_MX7D_19X19_LPDDR3_VAL
+	bool "Support mx7d_19x19_lpddr3_val"
+	select BOARD_LATE_INIT
+	select MX7D
+	select DM
+	select DM_THERMAL
+	imply CMD_DM
+
+config TARGET_MX7D_19X19_LPDDR2_VAL
+	bool "Support mx7d_19x19_lpddr2_val"
+	select BOARD_LATE_INIT
+	select MX7D
+	select DM
+	select DM_THERMAL
+	imply CMD_DM
 
 config TARGET_PICO_IMX7D
 	bool "pico-imx7d"
@@ -110,6 +157,10 @@ config SYS_SOC
 source "board/compulab/cl-som-imx7/Kconfig"
 source "board/ronetix/imx7-cm/Kconfig"
 source "board/freescale/mx7dsabresd/Kconfig"
+source "board/freescale/mx7d_12x12_lpddr3_val/Kconfig"
+source "board/freescale/mx7d_12x12_ddr3_val/Kconfig"
+source "board/freescale/mx7d_19x19_ddr3_val/Kconfig"
+source "board/freescale/mx7d_19x19_lpddr3_val/Kconfig"
 source "board/novtech/meerkat96/Kconfig"
 source "board/storopack/smegw01/Kconfig"
 source "board/technexion/pico-imx7d/Kconfig"
diff --git a/arch/arm/mach-imx/mx7/Makefile b/arch/arm/mach-imx/mx7/Makefile
index f1436e2d0d7..255503790d3 100644
--- a/arch/arm/mach-imx/mx7/Makefile
+++ b/arch/arm/mach-imx/mx7/Makefile
@@ -4,4 +4,5 @@
 #
 
 obj-y	:= soc.o clock.o clock_slice.o ddr.o snvs.o
+obj-$(CONFIG_IMX_TAMPER) += tamper.o
 obj-$(CONFIG_ARMV7_PSCI)  += psci-mx7.o psci-suspend.o
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index f6aec5a3aa2..dbe72d7429e 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -20,9 +21,9 @@
 #include <dm.h>
 #include <env.h>
 #include <imx_thermal.h>
-#include <fsl_sec.h>
 #include <asm/setup.h>
 #include <linux/delay.h>
+#include <fsl_wdog.h>
 
 #define IOMUXC_GPR1		0x4
 #define BM_IOMUXC_GPR1_IRQ	0x1000
@@ -127,7 +128,7 @@ static void isolate_resource(void)
 }
 #endif
 
-#if defined(CONFIG_IMX_HAB)
+#if defined(CONFIG_IMX_HAB) || defined(CONFIG_AVB_ATX)
 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
 	.bank = 1,
 	.word = 3,
@@ -306,8 +307,43 @@ static void imx_gpcv2_init(void)
 	udelay(65);
 }
 
+static void set_epdc_qos(void)
+{
+	writel(0, REGS_QOS_BASE);  /*  Disable clkgate & soft_reset */
+	writel(0, REGS_QOS_BASE + 0x60);  /*  Enable all masters */
+	writel(0, REGS_QOS_EPDC);   /*  Disable clkgate & soft_reset */
+	writel(0, REGS_QOS_PXP0);   /*  Disable clkgate & soft_reset */
+	writel(0, REGS_QOS_PXP1);   /*  Disable clkgate & soft_reset */
+
+	writel(0x0f020722, REGS_QOS_EPDC + 0xd0);   /*  WR, init = 7 with red flag */
+	writel(0x0f020722, REGS_QOS_EPDC + 0xe0);   /*  RD,  init = 7 with red flag */
+
+	writel(1, REGS_QOS_PXP0);   /*  OT_CTRL_EN =1 */
+	writel(1, REGS_QOS_PXP1);   /*  OT_CTRL_EN =1 */
+
+	writel(0x0f020222, REGS_QOS_PXP0 + 0x50);   /*  WR,  init = 2 with red flag */
+	writel(0x0f020222, REGS_QOS_PXP1 + 0x50);   /*  WR,  init = 2 with red flag */
+	writel(0x0f020222, REGS_QOS_PXP0 + 0x60);   /*  rD,  init = 2 with red flag */
+	writel(0x0f020222, REGS_QOS_PXP1 + 0x60);   /*  rD,  init = 2 with red flag */
+	writel(0x0f020422, REGS_QOS_PXP0 + 0x70);   /*  tOTAL,  init = 4 with red flag */
+	writel(0x0f020422, REGS_QOS_PXP1 + 0x70);   /*  TOTAL,  init = 4 with red flag */
+
+	writel(0xe080, IOMUXC_GPR_BASE_ADDR + 0x0034); /* EPDC AW/AR CACHE ENABLE */
+}
+
+bool is_usb_boot(void)
+{
+	if (gd->flags & GD_FLG_ARCH_IMX_USB_BOOT)
+		return true;
+
+	return false;
+}
+
 int arch_cpu_init(void)
 {
+	if (is_usbotg_boot_enabled())
+		gd->flags |= GD_FLG_ARCH_IMX_USB_BOOT;
+
 	init_aips();
 
 	init_csu();
@@ -316,6 +352,8 @@ int arch_cpu_init(void)
 
 	init_cpu_basic();
 
+	set_epdc_qos();
+
 #if CONFIG_IS_ENABLED(IMX_RDC)
 	isolate_resource();
 #endif
@@ -323,6 +361,7 @@ int arch_cpu_init(void)
 	init_snvs();
 
 	imx_gpcv2_init();
+	configure_tzc380();
 
 	enable_ca7_smp();
 
@@ -340,7 +379,7 @@ int arch_cpu_init(void)
 #ifdef CONFIG_ARCH_MISC_INIT
 int arch_misc_init(void)
 {
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#if defined(CONFIG_SERIAL_TAG) || defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 	struct tag_serialnr serialnr;
 	char serial_string[0x20];
 
@@ -356,15 +395,19 @@ int arch_misc_init(void)
 	env_set("serial#", serial_string);
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
+	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+		struct udevice *dev;
+		int ret;
+		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+		if (ret)
+			printf("Failed to initialize caam_jr: %d\n", ret);
+	}
 
 	return 0;
 }
 #endif
 
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#if defined(CONFIG_SERIAL_TAG) || defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 /*
  * OCOTP_TESTER
  * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
@@ -421,6 +464,10 @@ void s_init(void)
 	/* clock configuration. */
 	clock_init();
 
+#if defined(CONFIG_ANDROID_SUPPORT)
+        /* Enable RTC */
+        writel(0x21, 0x30370038);
+#endif
 	return;
 }
 
@@ -448,3 +495,31 @@ void reset_misc(void)
 #endif
 #endif
 }
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#ifdef CONFIG_MX7D
+void smp_set_core_boot_addr(unsigned long addr, int corenr)
+{
+            return;
+}
+
+void smp_waitloop(unsigned previous_address)
+{
+            return;
+}
+#endif
+#endif
+
+void reset_cpu(ulong addr)
+{
+	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+
+	/* Clear WDA to trigger WDOG_B immediately */
+	writew((WCR_WDE | WCR_SRS), &wdog->wcr);
+
+	while (1) {
+		/*
+		 * spin for .5 seconds before reset
+		 */
+	}
+}
diff --git a/arch/arm/mach-imx/mx7/tamper.c b/arch/arm/mach-imx/mx7/tamper.c
new file mode 100644
index 00000000000..7d6ef3605b0
--- /dev/null
+++ b/arch/arm/mach-imx/mx7/tamper.c
@@ -0,0 +1,385 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/arch/snvs.h>
+
+void enable_active_tamper(unsigned int tx, unsigned int rx)
+{
+	int val;
+
+	printf("start active tamper test on %d -> %d\n", tx, rx);
+
+	/****************************
+	 *   Configuring CAAM and SNVS  *
+	 ****************************/
+
+	/* Initialize power glitch detector register */
+	val = 0x41736166;
+	writel(val, SNVS_LPPGDR);
+
+	/* W1C PGD */
+	val = readl(SNVS_LPSR) & 0x00000008;
+	writel(val, SNVS_LPSR);
+
+	/* Programming ZMK via SW */
+	writel(0x11110000, SNVS_LPZMKR0);
+	writel(0x22220000, SNVS_LPZMKR1);
+	writel(0x33330000, SNVS_LPZMKR2);
+	writel(0x44440000, SNVS_LPZMKR3);
+	writel(0x55550000, SNVS_LPZMKR4);
+	writel(0x66660000, SNVS_LPZMKR5);
+	writel(0x77770000, SNVS_LPZMKR6);
+	writel(0x88880000, SNVS_LPZMKR7);
+
+	val = readl(SNVS_LPMKCR) | 0xa;
+	writel(val, SNVS_LPMKCR);
+	val = readl(SNVS_HPCOMR) | 0x1000;
+	writel(val, SNVS_HPCOMR);
+
+	val = readl(SNVS_LPMKCR) | 0x10;
+	writel(val, SNVS_LPMKCR);
+
+	val = readl(SNVS_HPSVSR);
+
+	/* LP Security Violation is a non-fatal Violation */
+	val = 0x40000000;
+	writel(val, SNVS_HPSVCR);
+
+	/* Enable SRTC invalidation in case of security violation */
+	val = readl(SNVS_LPCR);
+	val |= 0x11;
+	writel(val, SNVS_LPCR);
+
+	/*********************************
+	 *   Configuring active tamper tx output  *
+	 *********************************/
+
+	/* Configure LFSR polynomial and seed for active tamper tx */
+	val = AT5_POLYSEED;
+	writel(val, SNVS_LPAT1CR + (tx - 5) * 4);
+
+	/* Enable active tamper tx external pad */
+	val = readl(SNVS_LPATCTLR) | (1 << (tx - 5 + 16));
+	writel(val, SNVS_LPATCTLR);
+
+	/* Enable active tamper tx clk 16hz */
+	val = readl(SNVS_LPATCLKR);
+	val &= ~(3 << (tx - 5) * 4);
+	writel(val, SNVS_LPATCLKR);
+
+	/* Enable active tamper tx LFSR */
+	val = readl(SNVS_LPATCTLR) | (1 << (tx - 5));
+	writel(val, SNVS_LPATCTLR);
+
+	/* Enable glitch filter for external tamper rx */
+	if (rx < 2) {
+		val = readl(SNVS_LPTGFCR);
+		if (rx == 0)
+			val |= 0x800000;
+		else if (rx == 1)
+			val |= 0x80000000;
+		writel(val, SNVS_LPTGFCR);
+	} else if (rx < 6) {
+		val = readl(SNVS_LPTGF1CR);
+		val |= 1 << ((rx - 1) * 8 - 1);
+		writel(val, SNVS_LPTGF1CR);
+	} else {
+		val = readl(SNVS_LPTGF2CR);
+		val |= 1 << ((rx - 5) * 8 - 1);
+		writel(val, SNVS_LPTGF2CR);
+	}
+
+	/* Route active tamper tx to external tamper rx */
+	if (rx < 8) {
+		val = readl(SNVS_LPATRC1R);
+		val &= ~(0xf << (rx * 4));
+		val |= ((tx - 4) << (rx * 4));
+		writel(val, SNVS_LPATRC1R);
+	} else {
+		val = readl(SNVS_LPATRC2R);
+		val &= ~(0xf << ((rx - 8) * 4));
+		val |= ((tx - 4) << ((rx - 8) * 4));
+		writel(val, SNVS_LPATRC2R);
+	}
+
+	/* Enable external tamper rx */
+	if (rx < 2) {
+		val = readl(SNVS_LPTDCR);
+		if (rx == 0)
+			val |= 0x200;
+		else if (rx == 1)
+			val |= 0x400;
+		writel(val, SNVS_LPTDCR);
+	} else {
+		val = readl(SNVS_LPTDC2R);
+		val |= 1 << (rx - 2);
+		writel(val, SNVS_LPTDC2R);
+	}
+}
+
+void enable_passive_tamper(unsigned int rx, unsigned int high)
+{
+	int val;
+
+	printf("start passive tamper test on pin %d\n", rx);
+
+	/****************************
+	 *   Configuring CAAM and SNVS  *
+	 ****************************/
+
+	/* Initialize power glitch detector register */
+	val = 0x41736166;
+	writel(val, SNVS_LPPGDR);
+
+	/* W1C PGD */
+	val = readl(SNVS_LPSR) & 0x00000008;
+	writel(val, SNVS_LPSR);
+
+	/* Programming ZMK via SW */
+	writel(0x11111111, SNVS_LPZMKR0);
+	writel(0x22222222, SNVS_LPZMKR1);
+	writel(0x33333333, SNVS_LPZMKR2);
+	writel(0x44444444, SNVS_LPZMKR3);
+	writel(0x55555555, SNVS_LPZMKR4);
+	writel(0x66666666, SNVS_LPZMKR5);
+	writel(0x77777777, SNVS_LPZMKR6);
+	writel(0x88888888, SNVS_LPZMKR7);
+
+	val = readl(SNVS_LPMKCR) | 0xa;
+	writel(val, SNVS_LPMKCR);
+	val = readl(SNVS_HPCOMR) | 0x1000;
+	writel(val, SNVS_HPCOMR);
+
+	val = readl(SNVS_LPMKCR) | 0x10;
+	writel(val, SNVS_LPMKCR);
+
+	/* LP Security Violation is a non-fatal Violation */
+	val = 0x40000000;
+	writel(val, SNVS_HPSVCR);
+
+	/* Enable SRTC invalidation in case of security violation */
+	val = readl(SNVS_LPCR);
+	val |= 0x11;
+	writel(val, SNVS_LPCR);
+
+	/*********************************
+	 *   Configuring passive tamper rx          *
+	 *********************************/
+
+	/* Enable glitch filter for external tamper rx */
+	if (rx < 2) {
+		val = readl(SNVS_LPTGFCR);
+		if (rx == 0)
+			val |= 0x800000;
+		else if (rx == 1)
+			val |= 0x80000000;
+		writel(val, SNVS_LPTGFCR);
+	} else if (rx < 6) {
+		val = readl(SNVS_LPTGF1CR);
+		val |= 1 << ((rx - 1) * 8 - 1);
+		writel(val, SNVS_LPTGF1CR);
+	} else {
+		val = readl(SNVS_LPTGF2CR);
+		val |= 1 << ((rx - 5) * 8 - 1);
+		writel(val, SNVS_LPTGF2CR);
+	}
+
+	if (high == 1) {
+		/* Set external tampering rx polarity to high and enable tamper */
+		if (rx < 2) {
+			val = readl(SNVS_LPTDCR);
+			if (rx == 0)
+				val |= 0x800;
+			else if (rx == 1)
+				val |= 0x1000;
+			writel(val, SNVS_LPTDCR);
+		} else {
+			val = readl(SNVS_LPTDC2R);
+			val |= 1 << (rx - 2 + 16);
+			writel(val, SNVS_LPTDC2R);
+		}
+	}
+	/* Enable external tamper rx */
+	if (rx < 2) {
+		val = readl(SNVS_LPTDCR);
+		if (rx == 0)
+			val |= 0x200;
+		else if (rx == 1)
+			val |= 0x400;
+		writel(val, SNVS_LPTDCR);
+	} else {
+		val = readl(SNVS_LPTDC2R);
+		val |= 1 << (rx - 2);
+		writel(val, SNVS_LPTDC2R);
+	}
+}
+
+void stop_tamper(int rx)
+{
+	int val;
+
+	/* stop tamper */
+	if (rx < 2) {
+		val = readl(SNVS_LPTDCR);
+		if (rx == 0)
+			val &= ~0x200;
+		else if (rx == 1)
+			val &= ~0x400;
+		writel(val, SNVS_LPTDCR);
+	} else {
+		val = readl(SNVS_LPTDC2R);
+		val &= ~(1 << (rx - 2));
+		writel(val, SNVS_LPTDC2R);
+	}
+
+	/* clear tamper status */
+	if (rx < 2) {
+		val = readl(SNVS_LPSR);
+		val |= 1 << (rx + 9);
+		writel(val, SNVS_LPSR);
+	} else if (rx < 10) {
+		val = readl(SNVS_LPTDSR);
+		val |= 1 << (rx - 2);
+		writel(val, SNVS_LPTDSR);
+	}
+}
+
+static void get_tamper_status(void)
+{
+	unsigned int lpsr, lptdsr, hpsr, ssm;
+
+	lpsr = readl(SNVS_LPSR);
+	lptdsr = readl(SNVS_LPTDSR);
+	hpsr = readl(SNVS_HPSR);
+	ssm = (hpsr & 0xf00) >> 8;
+
+	if (lpsr & (1 << 9))
+		printf("External Tampering 0 Detected\n");
+	if (lpsr & (1 << 10))
+		printf("External Tampering 1 Detected\n");
+	if (lptdsr & (1 << 0))
+		printf("External Tampering 2 Detected\n");
+	if (lptdsr & (1 << 1))
+		printf("External Tampering 3 Detected\n");
+	if (lptdsr & (1 << 2))
+		printf("External Tampering 4 Detected\n");
+	if (lptdsr & (1 << 3))
+		printf("External Tampering 5 Detected\n");
+	if (lptdsr & (1 << 4))
+		printf("External Tampering 6 Detected\n");
+	if (lptdsr & (1 << 5))
+		printf("External Tampering 7 Detected\n");
+	if (lptdsr & (1 << 6))
+		printf("External Tampering 8 Detected\n");
+	if (lptdsr & (1 << 7))
+		printf("External Tampering 9 Detected\n");
+	if (!(lpsr & (3 << 9)) && !(lptdsr & 0xff))
+		printf("No External Tampering Detected\n");
+
+	if (hpsr & 0x80000000)
+		printf("Zeroizable Master Key is clear\n");
+	else
+		printf("Zeroizable Master Key is not zero\n");
+
+	if (ssm == 0)
+		printf("System Security Monitor State: Init\n");
+	else if (ssm == 0x8)
+		printf("System Security Monitor State: Init Intermediate\n");
+	else if (ssm == 0x9)
+		printf("System Security Monitor State: Check\n");
+	else if (ssm == 0xb)
+		printf("System Security Monitor State: Non-Secure\n");
+	else if (ssm == 0xd)
+		printf("System Security Monitor State: Trusted\n");
+	else if (ssm == 0xf)
+		printf("System Security Monitor State: Secure\n");
+	else if (ssm == 0x3)
+		printf("System Security Monitor State: Soft Fail\n");
+	else if (ssm == 0x1)
+		printf("System Security Monitor State: Hard Fail\n");
+	else
+		printf("System Security Monitor State: 0x%x\n", ssm);
+}
+
+static void clear_tamper_warning(void)
+{
+	unsigned int lpsr, lptdsr;
+
+	lpsr = readl(SNVS_LPSR);
+	lptdsr = readl(SNVS_LPTDSR);
+
+	writel(lpsr, SNVS_LPSR);
+	writel(lptdsr, SNVS_LPTDSR);
+}
+
+static int do_tamper(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	const char *op = argc >= 2 ? argv[1] : NULL;
+	unsigned int tx, rx, high;
+
+	if (argc < 2)
+		return CMD_RET_USAGE;
+
+	if (!strcmp(op, "active")) {
+		if (argc < 4)
+			return CMD_RET_USAGE;
+
+		tx = simple_strtoul(argv[2], NULL, 16);
+		rx = simple_strtoul(argv[3], NULL, 16);
+		if ((tx > 9) || (tx < 5))
+			return CMD_RET_USAGE;
+		if ((rx > 9) || (rx == tx))
+			return CMD_RET_USAGE;
+
+		enable_active_tamper(tx, rx);
+
+	} else if (!strcmp(op, "passive")) {
+		if (argc < 4)
+			return CMD_RET_USAGE;
+
+		rx = simple_strtoul(argv[2], NULL, 16);
+		if (rx > 9)
+			return CMD_RET_USAGE;
+
+		high = simple_strtoul(argv[3], NULL, 16);
+		if (high != 0)
+			high = 1;
+		enable_passive_tamper(rx, high);
+
+	} else if (!strcmp(op, "status")) {
+		get_tamper_status();
+	} else if (!strcmp(op, "clear")) {
+		clear_tamper_warning();
+	} else if (!strcmp(op, "stop")) {
+		if (argc < 3)
+			return CMD_RET_USAGE;
+
+		rx = simple_strtoul(argv[2], NULL, 16);
+		if (rx > 9)
+			return CMD_RET_USAGE;
+		stop_tamper(rx);
+	} else {
+		return CMD_RET_USAGE;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+		imx_tamper, CONFIG_SYS_MAXARGS, 0, do_tamper,
+		"imx tamper command for setting for test",
+		"active <tx rx>  - tx is active tamper pin from 9 ~ 5, \n"
+		"    rx pin is from 9 ~ 0 and should not equal to tx pin\n"
+		"passive <rx> <high> - rx is passive tamper pin from 9 ~ 0, \n"
+		"    high: 1 - high assert, 0 - low assert\n"
+		"status - Get tamper status\n"
+		"clear - clear tamper warning\n"
+		"stop rx - rx is tamper pin to stop\n"
+	  );
diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig
index 15c3ab6dae0..f045707519d 100644
--- a/arch/arm/mach-imx/mx7ulp/Kconfig
+++ b/arch/arm/mach-imx/mx7ulp/Kconfig
@@ -15,6 +15,12 @@ config MX7ULP
 	select HAS_CAAM
 	bool
 
+config IMX_M4_BIND
+	bool "Bind ULP M4 image to final u-boot"
+	help
+	  Select this to bind a ULP M4 image to final u-boot image
+	  User needs put the M4 image ulp_m4.bin under u-boot directory
+
 choice
 	prompt "MX7ULP board select"
 	optional
@@ -36,14 +42,28 @@ config TARGET_MX7ULP_COM
 	select SPL_SERIAL_SUPPORT if SPL
 	select SUPPORT_SPL
 
+config TARGET_MX7ULP_10X10_VAL
+	bool "Support mx7ulp 10x10 validation board"
+	select SYS_ARCH_TIMER
+	select MX7ULP
+
+config TARGET_MX7ULP_14X14_VAL
+	bool "Support mx7ulp 14x14 validation board"
+	select SYS_ARCH_TIMER
+	select MX7ULP
+
 config TARGET_MX7ULP_EVK
 	bool "Support mx7ulp EVK board"
 	select MX7ULP
 	select SYS_ARCH_TIMER
+	select FSL_CAAM
+	select FSL_BLOB
+	select ARCH_MISC_INIT
 
 endchoice
 
 source "board/ea/mx7ulp_com/Kconfig"
+source "board/freescale/mx7ulp_val/Kconfig"
 source "board/freescale/mx7ulp_evk/Kconfig"
 
 endif
diff --git a/arch/arm/mach-imx/mx7ulp/Makefile b/arch/arm/mach-imx/mx7ulp/Makefile
index adb8d7aecb0..1b131dd28e0 100644
--- a/arch/arm/mach-imx/mx7ulp/Makefile
+++ b/arch/arm/mach-imx/mx7ulp/Makefile
@@ -4,3 +4,4 @@
 #
 
 obj-y	:= soc.o clock.o iomux.o pcc.o scg.o
+obj-$(CONFIG_IMX_M4_BIND) += piggy_m4.o
diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c
index 6191153917f..16f24d3375d 100644
--- a/arch/arm/mach-imx/mx7ulp/clock.c
+++ b/arch/arm/mach-imx/mx7ulp/clock.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
  */
 
 #include <common.h>
@@ -115,6 +116,42 @@ u32 imx_get_i2cclk(unsigned i2c_num)
 }
 #endif
 
+#ifdef CONFIG_FSL_LPSPI
+int enable_lpspi_clk(unsigned char enable, unsigned spi_num)
+{
+	/* Set parent to FIRC DIV2 clock */
+	const enum pcc_clk lpspi_pcc_clks[] = {
+		PER_CLK_LPSPI2,
+		PER_CLK_LPSPI3,
+	};
+
+	if (spi_num < 2 || spi_num > 3)
+		return -EINVAL;
+
+	if (enable) {
+		pcc_clock_enable(lpspi_pcc_clks[spi_num - 2], false);
+		pcc_clock_sel(lpspi_pcc_clks[spi_num - 2], SCG_FIRC_DIV2_CLK);
+		pcc_clock_enable(lpspi_pcc_clks[spi_num - 2], true);
+	} else {
+		pcc_clock_enable(lpspi_pcc_clks[spi_num - 2], false);
+	}
+	return 0;
+}
+
+u32 imx_get_spiclk(unsigned spi_num)
+{
+	const enum pcc_clk lpspi_pcc_clks[] = {
+		PER_CLK_LPSPI2,
+		PER_CLK_LPSPI3,
+	};
+
+	if (spi_num < 2 || spi_num > 3)
+		return 0;
+
+	return pcc_clock_get_rate(lpspi_pcc_clks[spi_num - 2]);
+}
+#endif
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
 	switch (clk) {
@@ -128,6 +165,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 		return get_ipg_clk();
 	case MXC_I2C_CLK:
 		return pcc_clock_get_rate(PER_CLK_LPI2C4);
+	case MXC_LPSPI_CLK:
+		return pcc_clock_get_rate(PER_CLK_LPSPI3);
 	case MXC_UART_CLK:
 		return get_lpuart_clk();
 	case MXC_ESDHC_CLK:
@@ -151,8 +190,8 @@ void init_clk_usdhc(u32 index)
 		/*Disable the clock before configure it */
 		pcc_clock_enable(PER_CLK_USDHC0, false);
 
-		/* 158MHz / 1 = 158MHz */
-		pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK);
+		/* 352.8MHz / 1 = 352.8MHz */
+		pcc_clock_sel(PER_CLK_USDHC0, SCG_APLL_PFD1_CLK);
 		pcc_clock_div_config(PER_CLK_USDHC0, false, 1);
 		pcc_clock_enable(PER_CLK_USDHC0, true);
 		break;
@@ -160,9 +199,9 @@ void init_clk_usdhc(u32 index)
 		/*Disable the clock before configure it */
 		pcc_clock_enable(PER_CLK_USDHC1, false);
 
-		/* 158MHz / 1 = 158MHz */
-		pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK);
-		pcc_clock_div_config(PER_CLK_USDHC1, false, 1);
+		/* 352.8MHz / 2 = 176.4MHz */
+		pcc_clock_sel(PER_CLK_USDHC1, SCG_APLL_PFD1_CLK);
+		pcc_clock_div_config(PER_CLK_USDHC1, false, 2);
 		pcc_clock_enable(PER_CLK_USDHC1, true);
 		break;
 	default:
@@ -221,6 +260,11 @@ void enable_usboh3_clk(unsigned char enable)
 	}
 }
 
+int enable_usb_pll(ulong usb_phy_base)
+{
+	return scg_enable_usb_pll(true);
+}
+
 static void lpuart_set_clk(uint32_t index, enum scg_clk clk)
 {
 	const enum pcc_clk lpuart_pcc_clks[] = {
@@ -305,8 +349,8 @@ void clock_init(void)
 
 	scg_a7_init_core_clk();
 
-	/* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */
-	scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35);
+	/* APLL PFD1 = 352.8Mhz, PFD2=340.2Mhz, PFD3=793.8Mhz */
+	scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 27);
 	scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28);
 	scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12);
 
@@ -327,6 +371,88 @@ void hab_caam_clock_enable(unsigned char enable)
 }
 #endif
 
+void enable_mipi_dsi_clk(unsigned char enable)
+{
+	if (enable) {
+		pcc_clock_enable(PER_CLK_DSI, false);
+
+		/* mipi dsi escape clock range is 40-80Mhz, we expect to set it to about 60 Mhz
+		 * To avoid PCD issue, we select parent clock with lowest frequency
+		 * NIC1_CLK = 1584000khz, frac = 1, div = 5,  output = 63.360Mhz
+		 */
+		pcc_clock_sel(PER_CLK_DSI, SCG_NIC1_CLK);
+		pcc_clock_div_config(PER_CLK_DSI, 1, 5);
+
+		pcc_clock_enable(PER_CLK_DSI, true);
+	} else {
+		pcc_clock_enable(PER_CLK_DSI, false);
+	}
+}
+
+void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq_in_khz)
+{
+	/* Scan the parent clock to find best fit clock, whose generate actual frequence <= freq
+	*   Otherwise, the higher actual freq may introduce some problem
+	*   1. The real frequency exceeds max framerate that screen supports
+	*   2. The DSI PHY clock depends on the lcdif clock, so the higher lcdif clock may violate
+	*       DSI PHY clock requirement
+	*/
+	u8 pcd, best_pcd = 0;
+	u32 parent, frac, rate, parent_rate;
+	u32 best_parent = 0, best_frac = 0, best = 0;
+
+	static enum scg_clk clksrc_plat[] = {
+		SCG_NIC1_BUS_CLK,
+		SCG_NIC1_CLK,
+		SCG_DDR_CLK,
+		SCG_APLL_PFD2_CLK,
+		SCG_APLL_PFD1_CLK,
+		SCG_APLL_PFD0_CLK,
+		USB_PLL_OUT,
+	};
+
+	pcc_clock_enable(PER_CLK_LCDIF, false);
+
+	for (parent = 0; parent < ARRAY_SIZE(clksrc_plat); parent++) {
+		parent_rate = scg_clk_get_rate(clksrc_plat[parent]);
+		if (!parent_rate)
+			continue;
+
+		parent_rate = parent_rate / 1000; /* Change to khz*/
+
+		for (pcd = 0; pcd < 8; pcd++) {
+			for (frac = 0; frac < 2; frac++) {
+				if (pcd == 0 && frac == 1)
+					continue;
+
+				rate = parent_rate * (frac + 1) / (pcd + 1);
+				if (rate > freq_in_khz)
+					continue;
+
+				if (best == 0 || rate > best) {
+					best = rate;
+					best_parent = parent;
+					best_frac = frac;
+					best_pcd = pcd;
+				}
+			}
+		}
+	}
+
+	if (best == 0) {
+		printf("Can't find parent clock for LCDIF, target freq: %u\n", freq_in_khz);
+		return;
+	}
+
+	debug("LCD target rate %ukhz, best rate %ukhz, frac %u, pcd %u, best_parent %u\n",
+	      freq_in_khz, best, best_frac, best_pcd, best_parent);
+
+	pcc_clock_sel(PER_CLK_LCDIF, clksrc_plat[best_parent]);
+	pcc_clock_div_config(PER_CLK_LCDIF, best_frac, best_pcd + 1);
+	pcc_clock_enable(PER_CLK_LCDIF, true);
+}
+
+
 #ifndef CONFIG_SPL_BUILD
 /*
  * Dump some core clockes.
diff --git a/arch/arm/mach-imx/mx7ulp/piggy_m4.S b/arch/arm/mach-imx/mx7ulp/piggy_m4.S
new file mode 100644
index 00000000000..b33e8422ea6
--- /dev/null
+++ b/arch/arm/mach-imx/mx7ulp/piggy_m4.S
@@ -0,0 +1,2 @@
+	.section .firmware_image,#alloc
+	.incbin	"ulp_m4.bin"
diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c
index 4c066557c1c..275311d51ff 100644
--- a/arch/arm/mach-imx/mx7ulp/scg.c
+++ b/arch/arm/mach-imx/mx7ulp/scg.c
@@ -715,6 +715,61 @@ int scg_enable_pll_pfd(enum scg_clk clk, u32 frac)
 	return 0;
 }
 
+int scg_disable_pll_pfd(enum scg_clk clk)
+{
+	u32 reg;
+	u32 gate;
+	u32 addr;
+
+	switch (clk) {
+	case SCG_SPLL_PFD0_CLK:
+	case SCG_APLL_PFD0_CLK:
+		gate = SCG_PLL_PFD0_GATE_MASK;
+
+		if (clk == SCG_SPLL_PFD0_CLK)
+			addr = (u32)(&scg1_regs->spllpfd);
+		else
+			addr = (u32)(&scg1_regs->apllpfd);
+		break;
+	case SCG_SPLL_PFD1_CLK:
+	case SCG_APLL_PFD1_CLK:
+		gate = SCG_PLL_PFD1_GATE_MASK;
+
+		if (clk == SCG_SPLL_PFD1_CLK)
+			addr = (u32)(&scg1_regs->spllpfd);
+		else
+			addr = (u32)(&scg1_regs->apllpfd);
+		break;
+	case SCG_SPLL_PFD2_CLK:
+	case SCG_APLL_PFD2_CLK:
+		gate = SCG_PLL_PFD2_GATE_MASK;
+
+		if (clk == SCG_SPLL_PFD2_CLK)
+			addr = (u32)(&scg1_regs->spllpfd);
+		else
+			addr = (u32)(&scg1_regs->apllpfd);
+		break;
+	case SCG_SPLL_PFD3_CLK:
+	case SCG_APLL_PFD3_CLK:
+		gate = SCG_PLL_PFD3_GATE_MASK;
+
+		if (clk == SCG_SPLL_PFD3_CLK)
+			addr = (u32)(&scg1_regs->spllpfd);
+		else
+			addr = (u32)(&scg1_regs->apllpfd);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Gate the PFD */
+	reg = readl(addr);
+	reg |= gate;
+	writel(reg, addr);
+
+	return 0;
+}
+
 #define SIM_MISC_CTRL0_USB_PLL_EN_MASK (0x1 << 2)
 int scg_enable_usb_pll(bool usb_control)
 {
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index bc41cbc6871..72fdecd9433 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2021 NXP
  */
 
 #include <common.h>
@@ -10,12 +11,15 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/sections.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/hab.h>
 #include <asm/mach-imx/sys_proto.h>
 #include <asm/setup.h>
 #include <linux/bitops.h>
+#include <dm.h>
+#include <asm/setup.h>
 
 #define PMC0_BASE_ADDR		0x410a1000
 #define PMC0_CTRL		0x28
@@ -48,7 +52,22 @@ u32 get_cpu_rev(void)
 	/* Check the ROM version for cpu revision */
 	u32 rom_version = readl((void __iomem *)ROM_VERSION_ADDR);
 
-	return (MXC_CPU_MX7ULP << 12) | (rom_version & 0xFF);
+	rom_version &= 0xFF;
+	if (rom_version == CHIP_REV_1_0) {
+		return (MXC_CPU_MX7ULP << 12) | (rom_version);
+	} else {
+		/* Check the "Mirror of JTAG ID" SIM register since RevB */
+		uint32_t id;
+		id = readl(SIM0_RBASE + 0x8c);
+		id = (id >> 28) & 0xFF;
+
+		/* Revision Number ULP1 Version
+		 * 0000				A0
+		 * 0001				B0
+		 * 0010				B1
+		 */
+		return (MXC_CPU_MX7ULP << 12) | (CHIP_REV_2_0 + (id - 1));
+	}
 }
 
 #ifdef CONFIG_REVISION_TAG
@@ -76,11 +95,65 @@ enum bt_mode get_boot_mode(void)
 	return LOW_POWER_BOOT;
 }
 
+#ifdef CONFIG_IMX_M4_BIND
+char __firmware_image_start[0] __attribute__((section(".__firmware_image_start")));
+char __firmware_image_end[0] __attribute__((section(".__firmware_image_end")));
+
+int mcore_early_load_and_boot(void)
+{
+	u32 *src_addr = (u32 *)&__firmware_image_start;
+	u32 *dest_addr = (u32 *)TCML_BASE; /*TCML*/
+	u32 image_size = SZ_128K + SZ_64K; /* 192 KB*/
+	u32 pc = 0, tag = 0;
+
+	memcpy(dest_addr, src_addr, image_size);
+
+	/* Set GP register to tell the M4 rom the image entry */
+	/* We assume the M4 image has IVT head and padding which
+	 * should be same as the one programmed into QSPI flash
+	 */
+	tag = *(dest_addr + 1024);
+	if (tag != 0x402000d1 && tag !=0x412000d1)
+		return -1;
+
+	pc = *(dest_addr + 1025);
+
+	writel(pc, SIM0_RBASE + 0x70); /*GP7*/
+
+	return 0;
+}
+#endif
+
 int arch_cpu_init(void)
 {
 	enable_ca7_smp();
+
+#ifdef CONFIG_IMX_M4_BIND
+	int ret;
+	if (get_boot_mode() == SINGLE_BOOT) {
+		ret = mcore_early_load_and_boot();
+		if (ret)
+			puts("Invalid M4 image, boot failed\n");
+	}
+#endif
+	return 0;
+}
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+		struct udevice *dev;
+		int ret;
+
+		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+		if (ret)
+			printf("Failed to initialize caam_jr: %d\n", ret);
+	}
+
 	return 0;
 }
+#endif
 
 #ifdef CONFIG_BOARD_POSTCLK_INIT
 int board_postclk_init(void)
@@ -106,7 +179,7 @@ static void disable_wdog(u32 wdog_base)
 	__raw_writel(REFRESH_WORD1, (wdog_base + 0x04));
 	dmb();
 
-	if (!(val_cs & 800)) {
+	if (!(val_cs & 0x800)) {
 		dmb();
 		__raw_writel(UNLOCK_WORD0, (wdog_base + 0x04));
 		__raw_writel(UNLOCK_WORD1, (wdog_base + 0x04));
@@ -207,6 +280,11 @@ void s_init(void)
 	if (soc_rev() < CHIP_REV_2_0) {
 		/* enable dumb pmic */
 		writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR);
+
+#if defined(CONFIG_ANDROID_SUPPORT)
+		/* Enable RTC */
+		writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_SRTC_ENV), SNVS_LP_LPCR);
+#endif
 	}
 
 #if defined(CONFIG_LDO_ENABLED_MODE)
@@ -238,7 +316,7 @@ int print_cpuinfo(void)
 
 	cpurev = get_cpu_rev();
 
-	printf("CPU:   Freescale i.MX%s rev%d.%d at %d MHz\n",
+	printf("CPU:   i.MX%s rev%d.%d at %d MHz\n",
 	       get_imx_type((cpurev & 0xFF000) >> 12),
 	       (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0,
 	       mxc_get_clock(MXC_ARM_CLK) / 1000000);
@@ -256,6 +334,10 @@ int print_cpuinfo(void)
 	case SINGLE_BOOT:
 	default:
 		printf("Single boot\n");
+#ifdef CONFIG_IMX_M4_BIND
+		if (readl(SIM0_RBASE + 0x70))
+			printf("M4 start at 0x%x\n", readl(SIM0_RBASE + 0x70));
+#endif
 		break;
 	}
 
@@ -296,7 +378,12 @@ static char *get_reset_cause(char *ret)
 
 	srs = readl(reg_srs);
 	cause1 = readl(reg_ssrs);
+#ifndef CONFIG_ANDROID_BOOT_IMAGE
+	/* We will read the ssrs states later for android so we don't
+	 * clear the states here.
+	 */
 	writel(cause1, reg_ssrs);
+#endif
 
 	reset_cause = cause1;
 
@@ -336,10 +423,28 @@ static char *get_reset_cause(char *ret)
 	return ret;
 }
 
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+void get_reboot_reason(char *ret)
+{
+	u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28);
+
+	get_reset_cause(ret);
+	/* clear the ssrs here, its state has been recorded in reset_cause */
+	writel(reset_cause, reg_ssrs);
+}
+#endif
+
+void arch_preboot_os(void)
+{
+	scg_disable_pll_pfd(SCG_APLL_PFD1_CLK);
+	scg_disable_pll_pfd(SCG_APLL_PFD2_CLK);
+	scg_disable_pll_pfd(SCG_APLL_PFD3_CLK);
+}
+
 #ifdef CONFIG_ENV_IS_IN_MMC
 __weak int board_mmc_get_env_dev(int devno)
 {
-	return CONFIG_SYS_MMC_ENV_DEV;
+	return devno;
 }
 
 int mmc_get_env_dev(void)
@@ -384,7 +489,12 @@ enum boot_device get_boot_device(void)
 	return boot_dev;
 }
 
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+bool is_usb_boot(void)
+{
+	return get_boot_device() == USB_BOOT;
+}
+
+#if defined(CONFIG_SERIAL_TAG) || defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
 /*
  * OCOTP_CFG (SJC CHALLENGE, Unique ID)
  * i.MX 7ULP Applications Processor Reference Manual, Rev. 0, 09/2020
diff --git a/arch/arm/mach-imx/parse-container.c b/arch/arm/mach-imx/parse-container.c
index 039a4c73035..334fe3b12e1 100644
--- a/arch/arm/mach-imx/parse-container.c
+++ b/arch/arm/mach-imx/parse-container.c
@@ -1,75 +1,16 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2021 NXP
  */
 
 #include <common.h>
+#include <stdlib.h>
 #include <errno.h>
 #include <log.h>
 #include <spl.h>
 #include <asm/mach-imx/image.h>
 #ifdef CONFIG_AHAB_BOOT
-#include <asm/arch/sci/sci.h>
-#endif
-
-#define SEC_SECURE_RAM_BASE		0x31800000UL
-#define SEC_SECURE_RAM_END_BASE		(SEC_SECURE_RAM_BASE + 0xFFFFUL)
-#define SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE	0x60000000UL
-
-#define SECO_PT         2U
-
-#ifdef CONFIG_AHAB_BOOT
-static int authenticate_image(struct boot_img_t *img, int image_index)
-{
-	sc_faddr_t start, end;
-	sc_rm_mr_t mr;
-	int err;
-	int ret = 0;
-
-	debug("img %d, dst 0x%x, src 0x%x, size 0x%x\n",
-	      image_index, (uint32_t)img->dst, img->offset, img->size);
-
-	/* Find the memreg and set permission for seco pt */
-	err = sc_rm_find_memreg(-1, &mr,
-				img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1),
-				ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1);
-
-	if (err) {
-		printf("can't find memreg for image %d load address 0x%x, error %d\n",
-		       image_index, img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1), err);
-		return -ENOMEM;
-	}
-
-	err = sc_rm_get_memreg_info(-1, mr, &start, &end);
-	if (!err)
-		debug("memreg %u 0x%x -- 0x%x\n", mr, start, end);
-
-	err = sc_rm_set_memreg_permissions(-1, mr,
-					   SECO_PT, SC_RM_PERM_FULL);
-	if (err) {
-		printf("set permission failed for img %d, error %d\n",
-		       image_index, err);
-		return -EPERM;
-	}
-
-	err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE,
-				   1 << image_index);
-	if (err) {
-		printf("authenticate img %d failed, return %d\n",
-		       image_index, err);
-		ret = -EIO;
-	}
-
-	err = sc_rm_set_memreg_permissions(-1, mr,
-					   SECO_PT, SC_RM_PERM_NONE);
-	if (err) {
-		printf("remove permission failed for img %d, error %d\n",
-		       image_index, err);
-		ret = -EPERM;
-	}
-
-	return ret;
-}
+#include <asm/mach-imx/ahab.h>
 #endif
 
 static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image,
@@ -110,10 +51,8 @@ static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image,
 	}
 
 #ifdef CONFIG_AHAB_BOOT
-	if (authenticate_image(&images[image_index], image_index)) {
-		printf("Failed to authenticate image %d\n", image_index);
+	if (ahab_verify_cntr_image(&images[image_index], image_index))
 		return NULL;
-	}
 #endif
 
 	return &images[image_index];
@@ -134,21 +73,27 @@ static int read_auth_container(struct spl_image_info *spl_image,
 	 * It will not override the ATF code, so safe to use it here,
 	 * no need malloc
 	 */
-	container = (struct container_hdr *)spl_get_load_buffer(-size, size);
+	container = malloc(size);
+	if (!container)
+		return -ENOMEM;
 
 	debug("%s: container: %p sector: %lu sectors: %u\n", __func__,
 	      container, sector, sectors);
-	if (info->read(info, sector, sectors, container) != sectors)
-		return -EIO;
+	if (info->read(info, sector, sectors, container) != sectors) {
+		ret = -EIO;
+		goto end;
+	}
 
 	if (container->tag != 0x87 && container->version != 0x0) {
 		printf("Wrong container header");
-		return -ENOENT;
+		ret = -ENOENT;
+		goto end;
 	}
 
 	if (!container->num_images) {
 		printf("Wrong container, no image found");
-		return -ENOENT;
+		ret = -ENOENT;
+		goto end;
 	}
 
 	length = container->length_lsb + (container->length_msb << 8);
@@ -158,25 +103,24 @@ static int read_auth_container(struct spl_image_info *spl_image,
 		size = roundup(length, info->bl_len);
 		sectors = size / info->bl_len;
 
-		container = (struct container_hdr *)spl_get_load_buffer(-size, size);
+		free(container);
+		container = malloc(size);
+		if (!container)
+			return -ENOMEM;
 
 		debug("%s: container: %p sector: %lu sectors: %u\n",
 		      __func__, container, sector, sectors);
 		if (info->read(info, sector, sectors, container) !=
-		    sectors)
-			return -EIO;
+		    sectors) {
+			ret = -EIO;
+			goto end;
+		}
 	}
 
 #ifdef CONFIG_AHAB_BOOT
-	memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)container,
-	       ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
-
-	ret = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER,
-				   SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
-	if (ret) {
-		printf("authenticate container hdr failed, return %d\n", ret);
-		return ret;
-	}
+	ret = ahab_auth_cntr_hdr(container, length);
+	if (ret)
+		goto end_auth;
 #endif
 
 	for (i = 0; i < container->num_images; i++) {
@@ -195,11 +139,20 @@ static int read_auth_container(struct spl_image_info *spl_image,
 		}
 	}
 
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX_TRUSTY_OS)
+	/* Everything checks out, get the sw_version now. */
+	spl_image->rbindex = (uint64_t)container->sw_version;
+#endif
+
+
 end_auth:
 #ifdef CONFIG_AHAB_BOOT
-	if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0))
-		printf("Error: release container failed!\n");
+	ahab_auth_release();
 #endif
+
+end:
+	free(container);
+
 	return ret;
 }
 
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 2832b735096..919eb6180e0 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -20,12 +20,49 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <g_dnl.h>
 #include <linux/libfdt.h>
+#include <mmc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 __weak int spl_board_boot_device(enum boot_device boot_dev_spl)
 {
-	return 0;
+	switch (boot_dev_spl) {
+#if defined(CONFIG_MX7)
+	case SD1_BOOT:
+	case MMC1_BOOT:
+	case SD2_BOOT:
+	case MMC2_BOOT:
+	case SD3_BOOT:
+	case MMC3_BOOT:
+		return BOOT_DEVICE_MMC1;
+#elif defined(CONFIG_IMX8)
+	case MMC1_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD2_BOOT:
+		return BOOT_DEVICE_MMC2_2;
+	case SD3_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case FLEXSPI_BOOT:
+		return BOOT_DEVICE_SPI;
+#elif defined(CONFIG_IMX8M)
+	case SD1_BOOT:
+	case MMC1_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC2;
+#endif
+	case NAND_BOOT:
+		return BOOT_DEVICE_NAND;
+	case SPI_NOR_BOOT:
+		return BOOT_DEVICE_SPI;
+	case QSPI_BOOT:
+		return BOOT_DEVICE_NOR;
+	case USB_BOOT:
+		return BOOT_DEVICE_BOARD;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
 }
 
 #if defined(CONFIG_MX6)
@@ -111,7 +148,7 @@ u32 spl_boot_device(void)
 	return BOOT_DEVICE_NONE;
 }
 
-#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
+#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) || defined(CONFIG_IMX9)
 /* Translate iMX7/i.MX8M boot device to the SPL boot device enumeration */
 u32 spl_boot_device(void)
 {
@@ -140,54 +177,14 @@ u32 spl_boot_device(void)
 
 	enum boot_device boot_device_spl = get_boot_device();
 
-	if (IS_ENABLED(CONFIG_IMX8MM) || IS_ENABLED(CONFIG_IMX8MN) ||
-	    IS_ENABLED(CONFIG_IMX8MP))
-		return spl_board_boot_device(boot_device_spl);
-
-	switch (boot_device_spl) {
-#if defined(CONFIG_MX7)
-	case SD1_BOOT:
-	case MMC1_BOOT:
-	case SD2_BOOT:
-	case MMC2_BOOT:
-	case SD3_BOOT:
-	case MMC3_BOOT:
-		return BOOT_DEVICE_MMC1;
-#elif defined(CONFIG_IMX8)
-	case MMC1_BOOT:
-		return BOOT_DEVICE_MMC1;
-	case SD2_BOOT:
-		return BOOT_DEVICE_MMC2_2;
-	case SD3_BOOT:
-		return BOOT_DEVICE_MMC1;
-	case FLEXSPI_BOOT:
-		return BOOT_DEVICE_SPI;
-#elif defined(CONFIG_IMX8M)
-	case SD1_BOOT:
-	case MMC1_BOOT:
-		return BOOT_DEVICE_MMC1;
-	case SD2_BOOT:
-	case MMC2_BOOT:
-		return BOOT_DEVICE_MMC2;
-#endif
-	case NAND_BOOT:
-		return BOOT_DEVICE_NAND;
-	case SPI_NOR_BOOT:
-		return BOOT_DEVICE_SPI;
-	case QSPI_BOOT:
-		return BOOT_DEVICE_NOR;
-	case USB_BOOT:
-		return BOOT_DEVICE_USB;
-	default:
-		return BOOT_DEVICE_NONE;
-	}
+	return spl_board_boot_device(boot_device_spl);
 }
 #endif /* CONFIG_MX7 || CONFIG_IMX8M || CONFIG_IMX8 */
 
 #ifdef CONFIG_SPL_USB_GADGET
 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
 {
-	put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM + 0xfff, &dev->idProduct);
+	put_unaligned(0x0151, &dev->idProduct);
 
 	return 0;
 }
@@ -322,16 +319,6 @@ ulong board_spl_fit_size_align(ulong size)
 	return size;
 }
 
-void board_spl_fit_post_load(const void *fit)
-{
-	u32 offset = ALIGN(fdt_totalsize(fit), 0x1000);
-
-	if (imx_hab_authenticate_image((uintptr_t)fit,
-				       offset + IVT_SIZE + CSF_PAD_SIZE,
-				       offset)) {
-		panic("spl: ERROR:  image authentication unsuccessful\n");
-	}
-}
 #endif
 
 void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
@@ -392,3 +379,95 @@ void *spl_load_simple_fit_fix_load(const void *fit)
 
 	return (void *)new;
 }
+
+#if defined(CONFIG_IMX8MP) || defined(CONFIG_IMX8MN)
+int board_handle_rdc_config(void *fdt_addr, const char *config_name, void *dst_addr)
+{
+	int node = -1, size = 0, ret = 0;
+	uint32_t *data = NULL;
+	const struct fdt_property *prop;
+
+	node = fdt_node_offset_by_compatible(fdt_addr, -1, "imx8m,mcu_rdc");
+	if (node < 0) {
+		printf("Failed to find node!, err: %d!\n", node);
+		ret = -1;
+		goto exit;
+	}
+
+	/*
+	 * Before MCU core starts we should set the rdc config for it,
+	 * then restore the rdc config after it stops.
+	 */
+	prop = fdt_getprop(fdt_addr, node, config_name, &size);
+	if (!prop) {
+		printf("Failed to find property %s!\n", config_name);
+		ret = -1;
+		goto exit;
+	}
+	if (!size || size % (5 * sizeof(uint32_t))) {
+		printf("Config size is wrong! size:%d\n", size);
+		ret = -1;
+		goto exit;
+	}
+	data = malloc(size);
+	if (fdtdec_get_int_array(fdt_addr, node, config_name,
+				 data, size/sizeof(int))) {
+		printf("Failed to parse rdc config!\n");
+		ret = -1;
+		goto exit;
+	} else {
+		/* copy the rdc config */
+		memcpy(dst_addr, data, size);
+		ret = 0;
+	}
+
+exit:
+	if (data)
+		free(data);
+
+	/* Invalidate the buffer if no valid config found. */
+	if (ret < 0)
+		memset(dst_addr, 0, sizeof(uint32_t));
+
+	return ret;
+}
+#endif
+
+void board_spl_fit_post_load(const void *fit, struct spl_image_info *spl_image)
+{
+	if (IS_ENABLED(CONFIG_IMX_HAB) && !(spl_image->flags & SPL_FIT_BYPASS_POST_LOAD)) {
+		u32 offset = ALIGN(fdt_totalsize(fit), 0x1000);
+
+		if (imx_hab_authenticate_image((uintptr_t)fit,
+					       offset + IVT_SIZE + CSF_PAD_SIZE,
+					       offset)) {
+			panic("spl: ERROR:  image authentication unsuccessful\n");
+		}
+	}
+#if defined(CONFIG_IMX8MP) || defined(CONFIG_IMX8MN)
+#define MCU_RDC_MAGIC "mcu_rdc"
+	if (!(spl_image->flags & SPL_FIT_BYPASS_POST_LOAD)) {
+		memcpy((void *)CONFIG_IMX8M_MCU_RDC_START_CONFIG_ADDR, MCU_RDC_MAGIC, ALIGN(strlen(MCU_RDC_MAGIC), 4));
+		memcpy((void *)CONFIG_IMX8M_MCU_RDC_STOP_CONFIG_ADDR, MCU_RDC_MAGIC, ALIGN(strlen(MCU_RDC_MAGIC), 4));
+		board_handle_rdc_config(spl_image->fdt_addr, "start-config",
+					(void *)(CONFIG_IMX8M_MCU_RDC_START_CONFIG_ADDR + ALIGN(strlen(MCU_RDC_MAGIC), 4)));
+		board_handle_rdc_config(spl_image->fdt_addr, "stop-config",
+					(void *)(CONFIG_IMX8M_MCU_RDC_STOP_CONFIG_ADDR + ALIGN(strlen(MCU_RDC_MAGIC), 4)));
+	}
+#endif
+}
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+int check_rollback_index(struct spl_image_info *spl_image, struct mmc *mmc);
+int check_rpmb_blob(struct mmc *mmc);
+
+int mmc_image_load_late(struct spl_image_info *spl_image, struct mmc *mmc)
+{
+	/* Check the rollback index of next stage image */
+	if (check_rollback_index(spl_image, mmc) < 0)
+		return -1;
+
+	/* Check the rpmb key blob for trusty enabled platfrom. */
+	return check_rpmb_blob(mmc);
+}
+#endif
diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c
index d827de375a6..ff4a87132bf 100644
--- a/arch/arm/mach-imx/spl_imx_romapi.c
+++ b/arch/arm/mach-imx/spl_imx_romapi.c
@@ -12,6 +12,8 @@
 #include <spl.h>
 #include <asm/mach-imx/image.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/cache.h>
+#include <malloc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -72,6 +74,38 @@ static ulong spl_romapi_read_seekable(struct spl_load_info *load,
 
 	offset = sector * pagesize;
 
+	/* Handle corner case for ocram 0x980000 to 0x98ffff ecc region, ROM does not allow to access it */
+	if (is_imx8mp()) {
+		ulong ret;
+		void *new_buf;
+		if (((ulong)buf >= 0x980000 && (ulong)buf <= 0x98ffff)) {
+			new_buf = memalign(ARCH_DMA_MINALIGN, byte);
+			if (!new_buf) {
+				printf("Fail to allocate read buffer\n");
+				return 0;
+			}
+			ret = spl_romapi_raw_seekable_read(offset, byte, new_buf);
+			memcpy(buf, new_buf, ret);
+			free(new_buf);
+			return ret / pagesize;
+		} else if ((ulong)(buf + byte) >= 0x980000 && (ulong)(buf + byte) <= 0x98ffff) {
+			u32 over_size = (ulong)(buf + byte) - 0x97ffff;
+			over_size = (over_size + pagesize - 1) / pagesize * pagesize;
+
+			ret = spl_romapi_raw_seekable_read(offset, byte - over_size, buf);
+			new_buf = memalign(ARCH_DMA_MINALIGN, over_size);
+			if (!new_buf) {
+				printf("Fail to allocate read buffer\n");
+				return 0;
+			}
+
+			ret += spl_romapi_raw_seekable_read(offset + byte - over_size, over_size, new_buf);
+			memcpy(buf + byte - over_size, new_buf, ret);
+			free(new_buf);
+			return ret / pagesize;
+		}
+	}
+
 	return spl_romapi_raw_seekable_read(offset, byte, buf) / pagesize;
 }
 
@@ -171,6 +205,10 @@ static ulong get_fit_image_size(void *fit)
 	spl_load_info.read = spl_ram_load_read;
 	spl_load_info.priv = &last;
 
+        /* We call load_simple_fit is just to get total size, the image is not downloaded,
+         * so should bypass authentication
+         */
+	spl_image.flags = SPL_FIT_BYPASS_POST_LOAD;
 	spl_load_simple_fit(&spl_image, &spl_load_info,
 			    (uintptr_t)fit, fit);
 
diff --git a/arch/arm/mach-imx/trusty.S b/arch/arm/mach-imx/trusty.S
new file mode 100644
index 00000000000..2ca9b3c83ad
--- /dev/null
+++ b/arch/arm/mach-imx/trusty.S
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2009-2016 Freescale Semiconductor, Inc.
+ *
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/gic.h>
+#include <asm/armv7.h>
+_regs_save:
+	.word 0
+	.word 0
+	.word 0
+	.word 0
+	.word 0
+	.word 0
+	.word 0
+	.word 0
+	.word 0
+	.word 0
+	.word 0
+	.word 0
+	.word 0
+	.word 0
+	.word 0
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+ENTRY(trusty_os_init)
+	isb
+
+	/* Save current registers */
+	mov     ip, r0
+	adr     r0, _regs_save
+	str     ip, [r0]
+	add     r0, r0, #4		@ Get _regs_save from instruction offset
+
+	str     sp, [r0]
+	add     r0, r0, #4
+
+	stmia   r0!, {r1-r12}		@ Save r1 - r12
+
+	str     lr, [r0]
+	adr     lr, end_init_tee	@ save return address to lr
+
+	dsb
+
+	ldr     r1, =TRUSTY_OS_ENTRY
+	ldr     r0, =TRUSTY_OS_RAM_SIZE
+	movs    pc, r1			@ Go to TEE codes
+end_init_tee:
+	/* Restore saved registers */
+	adr     lr, _regs_save
+	ldr     r0, [lr]
+	add     lr, lr, #4
+
+	ldr     sp, [lr]
+	add     lr, lr, #4
+
+	ldmfd   lr!, {r1-r12}
+	ldr     lr, [lr]
+
+	dsb
+
+	bx      lr
+ENDPROC(trusty_os_init)
+#endif
diff --git a/arch/arm/mach-imx/video.c b/arch/arm/mach-imx/video.c
index 1bc9b7cc7e1..177f1713497 100644
--- a/arch/arm/mach-imx/video.c
+++ b/arch/arm/mach-imx/video.c
@@ -1,4 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ */
 
 #include <common.h>
 #include <env.h>
@@ -44,8 +48,14 @@ int board_video_skip(void)
 	}
 
 	if (i < display_count) {
+#if defined(CONFIG_VIDEO_IPUV3)
 		ret = ipuv3_fb_init(&displays[i].mode, displays[i].di ? 1 : 0,
 				    displays[i].pixfmt);
+#elif defined(CONFIG_VIDEO_MXS)
+		ret = mxs_lcd_panel_setup(displays[i].mode,
+					displays[i].pixfmt,
+				    displays[i].bus);
+#endif
 		if (!ret) {
 			if (displays[i].enable)
 				displays[i].enable(displays + i);
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index e920e01b254..0e992701879 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -56,6 +56,7 @@
 #ifdef CONFIG_U_QE
 #include <fsl_qe.h>
 #endif
+#include <dm.h>
 
 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 /*
@@ -974,8 +975,6 @@ int cpu_init_r(void)
 #endif
 
 #ifdef CONFIG_FSL_CAAM
-	sec_init();
-
 #if defined(CONFIG_ARCH_C29X)
 	if ((SVR_SOC_VER(svr) == SVR_C292) ||
 	    (SVR_SOC_VER(svr) == SVR_C293))
@@ -1014,6 +1013,22 @@ int cpu_init_r(void)
 	return 0;
 }
 
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+		struct udevice *dev;
+		int ret;
+
+		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+		if (ret)
+			printf("Failed to initialize caam_jr: %d\n", ret);
+	}
+
+	return 0;
+}
+#endif
+
 void arch_preboot_os(void)
 {
 	u32 msr;
diff --git a/arch/powerpc/dts/p2041si-post.dtsi b/arch/powerpc/dts/p2041si-post.dtsi
index 01ab3959505..8819199646f 100644
--- a/arch/powerpc/dts/p2041si-post.dtsi
+++ b/arch/powerpc/dts/p2041si-post.dtsi
@@ -11,6 +11,7 @@
 
 /include/ "qoriq-clockgen1.dtsi"
 /include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec4.2-0.dtsi"
 
 /* include used FMan blocks */
 /include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/p3041si-post.dtsi b/arch/powerpc/dts/p3041si-post.dtsi
index 21f322f06f8..a3e8088d25b 100644
--- a/arch/powerpc/dts/p3041si-post.dtsi
+++ b/arch/powerpc/dts/p3041si-post.dtsi
@@ -11,6 +11,7 @@
 
 /include/ "qoriq-clockgen1.dtsi"
 /include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec4.2-0.dtsi"
 
 /* include used FMan blocks */
 /include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/p4080si-post.dtsi b/arch/powerpc/dts/p4080si-post.dtsi
index 7c3f2fb92e2..56b79b14f4a 100644
--- a/arch/powerpc/dts/p4080si-post.dtsi
+++ b/arch/powerpc/dts/p4080si-post.dtsi
@@ -11,6 +11,7 @@
 
 /include/ "qoriq-clockgen1.dtsi"
 /include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec4.0-0.dtsi"
 
 /* include used FMan blocks */
 /include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/p5040si-post.dtsi b/arch/powerpc/dts/p5040si-post.dtsi
index 1efad2d0170..fae3ed31a5d 100644
--- a/arch/powerpc/dts/p5040si-post.dtsi
+++ b/arch/powerpc/dts/p5040si-post.dtsi
@@ -11,6 +11,7 @@
 
 /include/ "qoriq-clockgen1.dtsi"
 /include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec5.2-0.dtsi"
 
 /* include used FMan blocks */
 /include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/qoriq-sec4.0-0.dtsi b/arch/powerpc/dts/qoriq-sec4.0-0.dtsi
new file mode 100644
index 00000000000..ff348d70f1c
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-sec4.0-0.dtsi
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+crypto: crypto@300000 {
+	compatible = "fsl,sec-v4.0";
+	fsl,sec-era = <1>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+	reg = <0x300000 0x10000>;
+	ranges = <0 0x300000 0x10000>;
+	interrupts = <92 2 0 0>;
+
+	sec_jr0: jr@1000 {
+		compatible = "fsl,sec-v4.0-job-ring";
+		reg = <0x1000 0x1000>;
+		interrupts = <88 2 0 0>;
+	};
+
+	sec_jr1: jr@2000 {
+		compatible = "fsl,sec-v4.0-job-ring";
+		reg = <0x2000 0x1000>;
+		interrupts = <89 2 0 0>;
+	};
+
+	sec_jr2: jr@3000 {
+		compatible = "fsl,sec-v4.0-job-ring";
+		reg = <0x3000 0x1000>;
+		interrupts = <90 2 0 0>;
+	};
+
+	sec_jr3: jr@4000 {
+		compatible = "fsl,sec-v4.0-job-ring";
+		reg = <0x4000 0x1000>;
+		interrupts = <91 2 0 0>;
+	};
+
+	rtic@6000 {
+		compatible = "fsl,sec-v4.0-rtic";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x6000 0x100>;
+		ranges = <0x0 0x6100 0xe00>;
+
+		rtic_a: rtic-a@0 {
+			compatible = "fsl,sec-v4.0-rtic-memory";
+			reg = <0x00 0x20 0x100 0x80>;
+		};
+
+		rtic_b: rtic-b@20 {
+			compatible = "fsl,sec-v4.0-rtic-memory";
+			reg = <0x20 0x20 0x200 0x80>;
+		};
+
+		rtic_c: rtic-c@40 {
+			compatible = "fsl,sec-v4.0-rtic-memory";
+			reg = <0x40 0x20 0x300 0x80>;
+		};
+
+		rtic_d: rtic-d@60 {
+			compatible = "fsl,sec-v4.0-rtic-memory";
+			reg = <0x60 0x20 0x500 0x80>;
+		};
+	};
+};
+
+sec_mon: sec_mon@314000 {
+	compatible = "fsl,sec-v4.0-mon";
+	reg = <0x314000 0x1000>;
+	interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/dts/qoriq-sec4.2-0.dtsi b/arch/powerpc/dts/qoriq-sec4.2-0.dtsi
new file mode 100644
index 00000000000..57a0bc5c569
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-sec4.2-0.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+crypto: crypto@300000 {
+	compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
+	fsl,sec-era = <3>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+	reg		 = <0x300000 0x10000>;
+	ranges		 = <0 0x300000 0x10000>;
+	interrupts	 = <92 2 0 0>;
+
+	sec_jr0: jr@1000 {
+		compatible = "fsl,sec-v4.2-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg = <0x1000 0x1000>;
+		interrupts = <88 2 0 0>;
+	};
+
+	sec_jr1: jr@2000 {
+		compatible = "fsl,sec-v4.2-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg = <0x2000 0x1000>;
+		interrupts = <89 2 0 0>;
+	};
+
+	sec_jr2: jr@3000 {
+		compatible = "fsl,sec-v4.2-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg = <0x3000 0x1000>;
+		interrupts = <90 2 0 0>;
+	};
+
+	sec_jr3: jr@4000 {
+		compatible = "fsl,sec-v4.2-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg = <0x4000 0x1000>;
+		interrupts = <91 2 0 0>;
+	};
+
+	rtic@6000 {
+		compatible = "fsl,sec-v4.2-rtic",
+			     "fsl,sec-v4.0-rtic";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x6000 0x100>;
+		ranges = <0x0 0x6100 0xe00>;
+
+		rtic_a: rtic-a@0 {
+			compatible = "fsl,sec-v4.2-rtic-memory",
+				     "fsl,sec-v4.0-rtic-memory";
+			reg = <0x00 0x20 0x100 0x80>;
+		};
+
+		rtic_b: rtic-b@20 {
+			compatible = "fsl,sec-v4.2-rtic-memory",
+				     "fsl,sec-v4.0-rtic-memory";
+			reg = <0x20 0x20 0x200 0x80>;
+		};
+
+		rtic_c: rtic-c@40 {
+			compatible = "fsl,sec-v4.2-rtic-memory",
+				     "fsl,sec-v4.0-rtic-memory";
+			reg = <0x40 0x20 0x300 0x80>;
+		};
+
+		rtic_d: rtic-d@60 {
+			compatible = "fsl,sec-v4.2-rtic-memory",
+				     "fsl,sec-v4.0-rtic-memory";
+			reg = <0x60 0x20 0x500 0x80>;
+		};
+	};
+};
+
+sec_mon: sec_mon@314000 {
+	compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
+	reg = <0x314000 0x1000>;
+	interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/dts/qoriq-sec5.2-0.dtsi b/arch/powerpc/dts/qoriq-sec5.2-0.dtsi
new file mode 100644
index 00000000000..e5f87effd31
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-sec5.2-0.dtsi
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ */
+
+crypto: crypto@300000 {
+	compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
+	fsl,sec-era = <5>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+	reg		 = <0x300000 0x10000>;
+	ranges		 = <0 0x300000 0x10000>;
+	interrupts	 = <92 2 0 0>;
+
+	sec_jr0: jr@1000 {
+		compatible = "fsl,sec-v5.2-job-ring",
+			     "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg = <0x1000 0x1000>;
+		interrupts = <88 2 0 0>;
+	};
+
+	sec_jr1: jr@2000 {
+		compatible = "fsl,sec-v5.2-job-ring",
+			     "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg = <0x2000 0x1000>;
+		interrupts = <89 2 0 0>;
+	};
+
+	sec_jr2: jr@3000 {
+		compatible = "fsl,sec-v5.2-job-ring",
+			     "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg = <0x3000 0x1000>;
+		interrupts = <90 2 0 0>;
+	};
+
+	sec_jr3: jr@4000 {
+		compatible = "fsl,sec-v5.2-job-ring",
+			     "fsl,sec-v5.0-job-ring",
+			     "fsl,sec-v4.0-job-ring";
+		reg = <0x4000 0x1000>;
+		interrupts = <91 2 0 0>;
+	};
+
+	rtic@6000 {
+		compatible = "fsl,sec-v5.2-rtic",
+			     "fsl,sec-v5.0-rtic",
+			     "fsl,sec-v4.0-rtic";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x6000 0x100>;
+		ranges = <0x0 0x6100 0xe00>;
+
+		rtic_a: rtic-a@0 {
+			compatible = "fsl,sec-v5.2-rtic-memory",
+				     "fsl,sec-v5.0-rtic-memory",
+				     "fsl,sec-v4.0-rtic-memory";
+			reg = <0x00 0x20 0x100 0x80>;
+		};
+
+		rtic_b: rtic-b@20 {
+			compatible = "fsl,sec-v5.2-rtic-memory",
+				     "fsl,sec-v5.0-rtic-memory",
+				     "fsl,sec-v4.0-rtic-memory";
+			reg = <0x20 0x20 0x200 0x80>;
+		};
+
+		rtic_c: rtic-c@40 {
+			compatible = "fsl,sec-v5.2-rtic-memory",
+				     "fsl,sec-v5.0-rtic-memory",
+				     "fsl,sec-v4.0-rtic-memory";
+			reg = <0x40 0x20 0x300 0x80>;
+		};
+
+		rtic_d: rtic-d@60 {
+			compatible = "fsl,sec-v5.2-rtic-memory",
+				     "fsl,sec-v5.0-rtic-memory",
+				     "fsl,sec-v4.0-rtic-memory";
+			reg = <0x60 0x20 0x500 0x80>;
+		};
+	};
+};
+
+sec_mon: sec_mon@314000 {
+	compatible = "fsl,sec-v5.2-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
+	reg = <0x314000 0x1000>;
+	interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/dts/t1023si-post.dtsi b/arch/powerpc/dts/t1023si-post.dtsi
index 7284eb97910..6f666a15547 100644
--- a/arch/powerpc/dts/t1023si-post.dtsi
+++ b/arch/powerpc/dts/t1023si-post.dtsi
@@ -14,6 +14,7 @@
 /include/ "qoriq-gpio-1.dtsi"
 /include/ "qoriq-gpio-2.dtsi"
 /include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.0-0.dtsi"
 
 /* include used FMan blocks */
 /include/ "qoriq-fman3l-0.dtsi"
diff --git a/arch/powerpc/dts/t1042si-post.dtsi b/arch/powerpc/dts/t1042si-post.dtsi
index 5c60944e607..eebbbaf0e19 100644
--- a/arch/powerpc/dts/t1042si-post.dtsi
+++ b/arch/powerpc/dts/t1042si-post.dtsi
@@ -12,6 +12,7 @@
 /include/ "qoriq-gpio-1.dtsi"
 /include/ "qoriq-gpio-2.dtsi"
 /include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.0-0.dtsi"
 
 /include/ "qoriq-fman3l-0.dtsi"
 /include/ "qoriq-fman3-0-1g-0.dtsi"
diff --git a/arch/powerpc/dts/t2080si-post.dtsi b/arch/powerpc/dts/t2080si-post.dtsi
index d8ef579cb7c..c06526b3dba 100644
--- a/arch/powerpc/dts/t2080si-post.dtsi
+++ b/arch/powerpc/dts/t2080si-post.dtsi
@@ -13,6 +13,7 @@
 /include/ "qoriq-gpio-1.dtsi"
 /include/ "qoriq-gpio-2.dtsi"
 /include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.2-0.dtsi"
 
 /include/ "qoriq-fman3-0.dtsi"
 /include/ "qoriq-fman3-0-10g-0-best-effort.dtsi"
diff --git a/arch/powerpc/dts/t4240si-post.dtsi b/arch/powerpc/dts/t4240si-post.dtsi
index a596f48b54f..9fa99ae771b 100644
--- a/arch/powerpc/dts/t4240si-post.dtsi
+++ b/arch/powerpc/dts/t4240si-post.dtsi
@@ -12,6 +12,7 @@
 /include/ "qoriq-gpio-1.dtsi"
 /include/ "qoriq-gpio-2.dtsi"
 /include/ "qoriq-gpio-3.dtsi"
+/include/ "qoriq-sec5.0-0.dtsi"
 
 /include/ "qoriq-fman3-0.dtsi"
 /include/ "qoriq-fman3-0-1g-0.dtsi"
diff --git a/arch/powerpc/include/asm/u-boot-ppc.h b/arch/powerpc/include/asm/u-boot-ppc.h
new file mode 100644
index 00000000000..372ca3e0370
--- /dev/null
+++ b/arch/powerpc/include/asm/u-boot-ppc.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2021 NXP
+ *
+ * Gaurav Jain <gaurav.jain@nxp.com>
+ */
+
+#ifndef _U_BOOT_PPC_H_
+#define _U_BOOT_PPC_H_
+
+#ifndef __ASSEMBLY__
+
+int arch_misc_init(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _U_BOOT_PPC_H_ */
diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h
index 19b3c0db5fa..36af8e5403a 100644
--- a/arch/powerpc/include/asm/u-boot.h
+++ b/arch/powerpc/include/asm/u-boot.h
@@ -21,5 +21,6 @@
 /* Use the generic board which requires a unified bd_info */
 #include <asm-generic/u-boot.h>
 #include <asm/ppc.h>
+#include <asm/u-boot-ppc.h>
 
 #endif	/* __U_BOOT_H__ */
diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig
index 37ad1175e39..f4ceb214698 100644
--- a/board/freescale/common/Kconfig
+++ b/board/freescale/common/Kconfig
@@ -28,6 +28,12 @@ config FSL_USE_PCA9547_MUX
 	help
 	 This option enables the PCA9547 I2C mux on Freescale boards.
 
+config USB_TCPC
+	bool "USB Typec port controller simple driver"
+	default n
+	help
+	  Enable USB type-c port controller (TCPC) driver
+
 config VID
 	bool "Enable Freescale VID"
 	depends on I2C || DM_I2C
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 76979ac5620..18854df2532 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -67,6 +67,13 @@ obj-$(CONFIG_ZM7300)		+= zm7300.o
 obj-$(CONFIG_POWER_PFUZE100)	+= pfuze.o
 obj-$(CONFIG_DM_PMIC_PFUZE100)	+= pfuze.o
 obj-$(CONFIG_POWER_MC34VR500)	+= mc34vr500.o
+obj-$(CONFIG_MXC_EPDC)		+= epdc_setup.o
+ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 mx7ulp imx8 imx8m vf610 imx8ulp imx9))
+obj-y				+= mmc.o
+endif
+ifdef CONFIG_FSL_FASTBOOT
+obj-${CONFIG_ANDROID_RECOVERY} += recovery_keypad.o
+endif
 
 obj-$(CONFIG_LS102XA_STREAM_ID)	+= ls102xa_stream_id.o
 
@@ -87,4 +94,8 @@ obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o
 endif
 obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o
 
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_USB_TCPC) += tcpc.o
+endif
+
 endif
diff --git a/board/freescale/common/epdc_setup.c b/board/freescale/common/epdc_setup.c
new file mode 100644
index 00000000000..78935c6ff71
--- /dev/null
+++ b/board/freescale/common/epdc_setup.c
@@ -0,0 +1,226 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Peng Fan <Peng.Fan@freescale.com>
+ */
+#include <common.h>
+#include <lcd.h>
+#include <linux/err.h>
+#include <linux/types.h>
+#include <malloc.h>
+#include <mxc_epdc_fb.h>
+#include <fs.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <asm/cache.h>
+
+#define is_digit(c)	((c) >= '0' && (c) <= '9')
+__weak int mmc_get_env_devno(void)
+{
+	return 0;
+}
+__weak int check_mmc_autodetect(void)
+{
+	return 0;
+}
+
+int board_setup_waveform_file(ulong waveform_buf)
+{
+	char *fs_argv[5];
+	char addr[17];
+	ulong file_len, mmc_dev;
+
+	if (!check_mmc_autodetect())
+		mmc_dev = env_get_ulong("mmcdev", 10, 0);
+	else
+		mmc_dev = mmc_get_env_devno();
+
+	sprintf(addr, "%lx", (ulong)CONFIG_SYS_LOAD_ADDR);
+
+	fs_argv[0] = "fatload";
+	fs_argv[1] = "mmc";
+	fs_argv[2] = simple_itoa(mmc_dev);
+	fs_argv[3] = addr;
+	fs_argv[4] = env_get("epdc_waveform");
+
+	if (!fs_argv[4])
+		fs_argv[4] = "epdc_splash.bin";
+
+	if (do_fat_fsload(NULL, 0, 5, fs_argv)) {
+		printf("File %s not found on MMC Device %lu!\n", fs_argv[4], mmc_dev);
+		return -1;
+	}
+
+	file_len = env_get_hex("filesize", 0);
+	if (!file_len)
+		return -1;
+
+	memcpy((void *)waveform_buf, (const void *)CONFIG_SYS_LOAD_ADDR, file_len);
+
+	flush_cache(waveform_buf, roundup(file_len, ARCH_DMA_MINALIGN));
+
+	return 0;
+}
+
+int board_setup_logo_file(void *display_buf)
+{
+	int logo_width, logo_height;
+	char *fs_argv[5];
+	char addr[17];
+	int array[3];
+	ulong file_len, mmc_dev;
+	char *buf, *s;
+	int arg = 0, val = 0, pos = 0;
+	int i, j, max_check_length;
+	int row, col, row_end, col_end;
+
+	if (!display_buf)
+		return -EINVAL;
+
+	/* Assume PGM header not exceeds 128 bytes */
+	max_check_length = 128;
+
+	if (!check_mmc_autodetect())
+		mmc_dev = env_get_ulong("mmcdev", 10, 0);
+	else
+		mmc_dev = mmc_get_env_devno();
+
+	memset(display_buf, 0xFF, panel_info.vl_col * panel_info.vl_row);
+
+	fs_argv[0] = "fatsize";
+	fs_argv[1] = "mmc";
+	fs_argv[2] = simple_itoa(mmc_dev);
+	fs_argv[3] = env_get("epdc_logo");
+	if (!fs_argv[3])
+		fs_argv[3] = "epdc_logo.pgm";
+	if (do_fat_size(NULL, 0, 4, fs_argv)) {
+		debug("File %s not found on MMC Device %lu, use black border\n", fs_argv[3], mmc_dev);
+		/* Draw black border around framebuffer*/
+		memset(display_buf, 0x0, 24 * panel_info.vl_col);
+		for (i = 24; i < (panel_info.vl_row - 24); i++) {
+			memset((u8 *)display_buf + i * panel_info.vl_col,
+			       0x00, 24);
+			memset((u8 *)display_buf + i * panel_info.vl_col
+				+ panel_info.vl_col - 24, 0x00, 24);
+		}
+		memset((u8 *)display_buf +
+		       panel_info.vl_col * (panel_info.vl_row - 24),
+		       0x00, 24 * panel_info.vl_col);
+		return 0;
+	}
+
+	file_len = env_get_hex("filesize", 0);
+	if (!file_len)
+		return -EINVAL;
+
+	buf = memalign(ARCH_DMA_MINALIGN, file_len);
+	if (!buf)
+		return -ENOMEM;
+
+	sprintf(addr, "%lx", (ulong)CONFIG_SYS_LOAD_ADDR);
+
+	fs_argv[0] = "fatload";
+	fs_argv[1] = "mmc";
+	fs_argv[2] = simple_itoa(mmc_dev);
+	fs_argv[3] = addr;
+	fs_argv[4] = env_get("epdc_logo");
+
+	if (!fs_argv[4])
+		fs_argv[4] = "epdc_logo.pgm";
+
+	if (do_fat_fsload(NULL, 0, 5, fs_argv)) {
+		printf("File %s not found on MMC Device %lu!\n", fs_argv[4], mmc_dev);
+		free(buf);
+		return -1;
+	}
+
+	memcpy((void *)buf, (const void *)CONFIG_SYS_LOAD_ADDR, file_len);
+
+	if (strncmp(buf, "P5", 2)) {
+		printf("Wrong format for epdc logo, use PGM-P5 format.\n");
+		free(buf);
+		return -EINVAL;
+	}
+	/* Skip P5\n */
+	pos += 3;
+	arg = 0;
+	for (i = 3; i < max_check_length; ) {
+		/* skip \n \t and space */
+		if ((buf[i] == '\n') || (buf[i] == '\t') || (buf[i] == ' ')) {
+			i++;
+			continue;
+		}
+		/* skip comment */
+		if (buf[i] == '#') {
+			while (buf[i++] != '\n')
+				;
+			continue;
+		}
+
+		/* HEIGTH, WIDTH, MAX PIXEL VLAUE total 3 args */
+		if (arg > 2)
+			break;
+		val = 0;
+		while (is_digit(buf[i])) {
+			val = val * 10 + buf[i] - '0';
+			i++;
+		}
+		array[arg++] = val;
+
+		i++;
+	}
+
+	/* Point to data area */
+	pos = i;
+
+	logo_width = array[0];
+	logo_height = array[1];
+
+	if ((logo_width > panel_info.vl_col) ||
+	    (logo_height > panel_info.vl_row)) {
+		printf("Picture: too big\n");
+		free(buf);
+		return -EINVAL;
+	}
+
+	/* m,m means center of screen */
+	row = 0;
+	col = 0;
+	s = env_get("splashpos");
+	if (s) {
+		if (s[0] == 'm')
+			col = (panel_info.vl_col  - logo_width) >> 1;
+		else
+			col = simple_strtol(s, NULL, 0);
+		s = strchr(s + 1, ',');
+		if (s != NULL) {
+			if (s[1] == 'm')
+				row = (panel_info.vl_row  - logo_height) >> 1;
+			else
+				row = simple_strtol(s + 1, NULL, 0);
+		}
+	}
+	if ((col + logo_width > panel_info.vl_col) ||
+	    (row + logo_height > panel_info.vl_row)) {
+		printf("Incorrect pos, use (0, 0)\n");
+		row = 0;
+		col = 0;
+	}
+
+	/* Draw picture at the center of screen */
+	row_end = row + logo_height;
+	col_end = col + logo_width;
+	for (i = row; i < row_end; i++) {
+		for (j = col; j < col_end; j++) {
+			*((u8 *)display_buf + i * (panel_info.vl_col) + j) =
+				 buf[pos++];
+		}
+	}
+
+	free(buf);
+
+	flush_cache((ulong)display_buf, file_len - pos - 1);
+
+	return 0;
+}
diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c
index 7ffb315bc93..1b9733cf837 100644
--- a/board/freescale/common/fsl_chain_of_trust.c
+++ b/board/freescale/common/fsl_chain_of_trust.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2022 NXP
  */
 
 #include <common.h>
@@ -113,11 +114,6 @@ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr)
 		fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-	if (sec_init() < 0)
-		fsl_secboot_handle_error(ERROR_ESBC_SEC_INIT);
-#endif
-
 /*
  * dm_init_and_scan() is called as part of common SPL framework, so no
  * need to call it again but in case of powerpc platforms which currently
diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c
index 34875d0b8f2..569a8c4655d 100644
--- a/board/freescale/common/fsl_validate.c
+++ b/board/freescale/common/fsl_validate.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015 Freescale Semiconductor, Inc.
- * Copyright 2021 NXP
+ * Copyright 2021-2022 NXP
  */
 
 #include <common.h>
@@ -20,6 +20,7 @@
 #ifdef CONFIG_ARCH_LS1021A
 #include <asm/arch/immap_ls102xa.h>
 #endif
+#include <dm/lists.h>
 
 #define SHA256_BITS	256
 #define SHA256_BYTES	(256/8)
@@ -806,6 +807,13 @@ static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img)
 	prop.num_bits = key_len * 8;
 	prop.exp_len = key_len;
 
+#if defined(CONFIG_SPL_BUILD)
+	ret = device_bind_driver(NULL, "fsl_rsa_mod_exp", "fsl_rsa_mod_exp", NULL);
+	if (ret) {
+		printf("Couldn't bind fsl_rsa_mod_exp driver (%d)\n", ret);
+		return -EINVAL;
+	}
+#endif
 	ret = uclass_get_device(UCLASS_MOD_EXP, 0, &mod_exp_dev);
 	if (ret) {
 		printf("RSA: Can't find Modular Exp implementation\n");
diff --git a/board/freescale/common/mmc.c b/board/freescale/common/mmc.c
new file mode 100644
index 00000000000..ab1652d6972
--- /dev/null
+++ b/board/freescale/common/mmc.c
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
+ */
+#include <common.h>
+#include <command.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <stdbool.h>
+#include <mmc.h>
+#include <env.h>
+
+static int check_mmc_autodetect(void)
+{
+	char *autodetect_str = env_get("mmcautodetect");
+
+	if ((autodetect_str != NULL) &&
+		(strcmp(autodetect_str, "yes") == 0)) {
+		return 1;
+	}
+
+	return 0;
+}
+
+/* This should be defined for each board */
+__weak int mmc_map_to_kernel_blk(int dev_no)
+{
+	return dev_no;
+}
+
+void board_late_mmc_env_init(void)
+{
+	char cmd[32];
+	char mmcblk[32];
+	u32 dev_no = mmc_get_env_dev();
+
+	if (!check_mmc_autodetect())
+		return;
+
+	env_set_ulong("mmcdev", dev_no);
+
+	/* Set mmcblk env */
+	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
+		mmc_map_to_kernel_blk(dev_no));
+	env_set("mmcroot", mmcblk);
+
+	sprintf(cmd, "mmc dev %d", dev_no);
+	run_command(cmd, 0);
+}
diff --git a/board/freescale/common/qspi_header b/board/freescale/common/qspi_header
new file mode 100644
index 00000000000..d4f3c12d418
--- /dev/null
+++ b/board/freescale/common/qspi_header
@@ -0,0 +1,128 @@
+0			/*dqs_loopback=0 or 1*/
+0			/*hold_delay=0 to 3*/
+0			/*hsphs=0 (Half Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/
+0			/*hsdly=0 (Half Speed Delay one clk delay) or 1 (two clk cycle delay)*/
+0			/*device_quad_mode_en=1 to enable sending command to SPI device*/
+0			/*device_cmd=command to device for enableing Quad I/O mode*/
+0			/*write_cmd_ipcr=hex value to be written to IPCR register for write cmd of device*/
+2000000			/*write_enable_ipcr=hex value to be written to IPCR register for write enable of device*/
+3			/*cs_hold_time=0 to 0xF*/
+3			/*cs_setup_time=0 to 0xF*/
+8000000		/*sflash_A1_size=size in byte(hex)*/
+0		/*sflash_A2_size=size in byte(hex)*/
+8000000		/*sflash_B1_size=size in byte(hex)*/
+0		/*sflash_B2_size=size in byte(hex)*/
+0			/*sclk_freq=0 to 6*/
+0			/*busy_bit_offset=bit position of device BUSY in device status register*/
+1			/*sflash_type=1 (Single), 2 (Dual), 4 (Quad mode of operation)*/
+0			/*sflash_port=0 or 1 (Port B used)*/
+0			/*ddr_mode_enable=0 or 1*/
+0			/*dqs_enable=0 or 1*/
+0			/*parallel_mode_enable=0 or 1*/
+0			/*portA_cs1=0 or 1*/
+0			/*portB_cs1=0 or 1*/
+0			/*fsphs=0 (Full Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/
+0			/*fsdly=0 (Full Speed Delay One clk delay) or 1 (two clk cycle delay)*/
+0			/*ddrsmp=0 to 7 (sampling point for incoming data in DDR mode)*/
+08180403		/*lut[0] command sequence*/
+24001c00		/*lut[1] command sequence*/
+0			/*lut[2] command sequence*/
+0			/*lut[3] command sequence*/
+0			/*lut[4] command sequence*/
+0			/*lut[5] command sequence*/
+0			/*lut[6] command sequence*/
+0			/*lut[7] command sequence*/
+0			/*lut[8] command sequence*/
+0			/*lut[9] command sequence*/
+0			/*lut[10] command sequence*/
+0			/*lut[11] command sequence*/
+0			/*lut[12] command sequence*/
+0			/*lut[13] command sequence*/
+0			/*lut[14] command sequence*/
+0			/*lut[15] command sequence*/
+0			/*lut[16] command sequence*/
+0			/*lut[17] command sequence*/
+0			/*lut[18] command sequence*/
+0			/*lut[19] command sequence*/
+0			/*lut[20] command sequence*/
+0			/*lut[21] command sequence*/
+0			/*lut[22] command sequence*/
+0			/*lut[23] command sequence*/
+0			/*lut[24] command sequence*/
+0			/*lut[25] command sequence*/
+0			/*lut[26] command sequence*/
+0			/*lut[27] command sequence*/
+0			/*lut[28] command sequence*/
+0			/*lut[29] command sequence*/
+0			/*lut[30] command sequence*/
+0			/*lut[31] command sequence*/
+0			/*lut[32] command sequence*/
+0			/*lut[33] command sequence*/
+0			/*lut[34] command sequence*/
+0			/*lut[35] command sequence*/
+0			/*lut[36] command sequence*/
+0			/*lut[37] command sequence*/
+0			/*lut[38] command sequence*/
+0			/*lut[39] command sequence*/
+0			/*lut[40] command sequence*/
+0			/*lut[41] command sequence*/
+0			/*lut[42] command sequence*/
+0			/*lut[43] command sequence*/
+0			/*lut[44] command sequence*/
+0			/*lut[45] command sequence*/
+0			/*lut[46] command sequence*/
+0			/*lut[47] command sequence*/
+0			/*lut[48] command sequence*/
+0			/*lut[49] command sequence*/
+0			/*lut[50] command sequence*/
+0			/*lut[51] command sequence*/
+0			/*lut[52] command sequence*/
+0			/*lut[53] command sequence*/
+0			/*lut[54] command sequence*/
+0			/*lut[55] command sequence*/
+0			/*lut[56] command sequence*/
+0			/*lut[57] command sequence*/
+0			/*lut[58] command sequence*/
+0			/*lut[59] command sequence*/
+0			/*lut[60] command sequence*/
+0			/*lut[61] command sequence*/
+0			/*lut[62] command sequence*/
+0			/*lut[63] command sequence*/
+1000001			/*read_status_ipcr=hex value to be written to IPCR register for reading status reg of device*/
+0			/*enable_dqs_phase=0 or 1*/
+0			/*config_cmds_en, enable config command*/
+0			/*config_cmds[0]*/
+0			/*config_cmds[1]*/
+0			/*config_cmds[2]*/
+0			/*config_cmds[3]*/
+0			/*config_cmds_args[0]*/
+0			/*config_cmds_args[1]*/
+0			/*config_cmds_args[2]*/
+0			/*config_cmds_args[3]*/
+0			/*io_pad_override_setting QSPI pins override setting*/
+0			/*reserve[0], 25 byte reserved area*/
+0			/*reserve[1], 25 byte reserved area*/
+0			/*reserve[2], 25 byte reserved area*/
+0			/*reserve[3], 25 byte reserved area*/
+0			/*reserve[4], 25 byte reserved area*/
+0			/*reserve[5], 25 byte reserved area*/
+0			/*reserve[6], 25 byte reserved area*/
+0			/*reserve[7], 25 byte reserved area*/
+0			/*reserve[8], 25 byte reserved area*/
+0			/*reserve[9], 25 byte reserved area*/
+0			/*reserve[10], 25 byte reserved area*/
+0			/*reserve[11], 25 byte reserved area*/
+0			/*reserve[12], 25 byte reserved area*/
+0			/*reserve[13], 25 byte reserved area*/
+0			/*reserve[14], 25 byte reserved area*/
+0			/*reserve[15], 25 byte reserved area*/
+0			/*reserve[16], 25 byte reserved area*/
+0			/*reserve[17], 25 byte reserved area*/
+0			/*reserve[18], 25 byte reserved area*/
+0			/*reserve[19], 25 byte reserved area*/
+0			/*reserve[20], 25 byte reserved area*/
+0			/*reserve[21], 25 byte reserved area*/
+0			/*reserve[22], 25 byte reserved area*/
+0			/*reserve[23], 25 byte reserved area*/
+0			/*reserve[24], 25 byte reserved area*/
+c0ffee01	/*tag, QSPI configuration tag, should be 0xc0ffee01*/
diff --git a/board/freescale/common/recovery_keypad.c b/board/freescale/common/recovery_keypad.c
new file mode 100644
index 00000000000..2f5a58a92d8
--- /dev/null
+++ b/board/freescale/common/recovery_keypad.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier:	GPL-2.0+
+/*
+ * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2017 NXP
+ *
+ */
+#include <common.h>
+#include <malloc.h>
+#include <recovery.h>
+#ifdef CONFIG_MXC_KPD
+#include <mxc_keyb.h>
+#endif
+#include <asm/mach-imx/boot_mode.h>
+
+#ifdef CONFIG_MXC_KPD
+#define PRESSED_VOL_DOWN	0x01
+#define PRESSED_POWER	    0x02
+#define RECOVERY_KEY_MASK (PRESSED_VOL_DOWN | PRESSED_POWER)
+
+inline int test_key(int value, struct kpp_key_info *ki)
+{
+	return (ki->val == value) && (ki->evt == KDepress);
+}
+
+int is_recovery_keypad_pressing(void)
+{
+	struct kpp_key_info *key_info = NULL;
+	int state = 0, keys, i;
+
+	int ret = 0;
+
+	mxc_kpp_init();
+	/* due to glitch suppression circuit,
+	   wait sometime to let all keys scanned. */
+	udelay(1000);
+	keys = mxc_kpp_getc(&key_info);
+
+	printf("Detecting VOL_DOWN+POWER key for recovery(%d:%d) ...\n",
+		keys, keys ? key_info->val : 0);
+	if (keys > 1) {
+		for (i = 0; i < keys; i++) {
+			if (test_key(CONFIG_POWER_KEY, &key_info[i]))
+				state |= PRESSED_POWER;
+			else if (test_key(CONFIG_VOL_DOWN_KEY, &key_info[i]))
+				state |= PRESSED_VOL_DOWN;
+		}
+	}
+	if ((state & RECOVERY_KEY_MASK) == RECOVERY_KEY_MASK)
+		ret = 1;
+	if (key_info)
+		free(key_info);
+	return ret;
+}
+#else
+/* If not using mxc keypad, currently we will detect power key on board */
+int is_recovery_keypad_pressing(void)
+{
+	return 0;
+}
+#endif
diff --git a/board/freescale/common/recovery_keypad.h b/board/freescale/common/recovery_keypad.h
new file mode 100644
index 00000000000..9adf2243e88
--- /dev/null
+++ b/board/freescale/common/recovery_keypad.h
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier:	GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2017 NXP
+ *
+ */
+
+#ifndef __RECOVERY_KEYPAD_H_
+#define __RECOVERY_KEYPAD_H_
+
+int is_recovery_keypad_pressing(void);
+
+#endif
diff --git a/board/freescale/common/tcpc.c b/board/freescale/common/tcpc.c
new file mode 100644
index 00000000000..3726ba978b0
--- /dev/null
+++ b/board/freescale/common/tcpc.c
@@ -0,0 +1,1053 @@
+/*
+ * Copyright 2017,2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <i2c.h>
+#include <time.h>
+#include <linux/delay.h>
+#include "tcpc.h"
+
+#ifdef DEBUG
+#define tcpc_debug_log(port, fmt, args...) tcpc_log(port, fmt, ##args)
+#else
+#define tcpc_debug_log(port, fmt, args...)
+#endif
+
+static int tcpc_log(struct tcpc_port *port, const char *fmt, ...)
+{
+	va_list args;
+	int i;
+
+	va_start(args, fmt);
+	i = vscnprintf(port->log_p, port->log_size, fmt, args);
+	va_end(args);
+
+	port->log_size -= i;
+	port->log_p += i;
+
+	return i;
+}
+
+int tcpc_set_cc_to_source(struct tcpc_port *port)
+{
+	uint8_t valb;
+	int err;
+
+	if (port == NULL || port->i2c_dev == NULL)
+		return -EINVAL;
+
+	valb = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) |
+			(TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT) |
+			(TCPC_ROLE_CTRL_RP_VAL_DEF <<
+			 TCPC_ROLE_CTRL_RP_VAL_SHIFT) | TCPC_ROLE_CTRL_DRP;
+
+	err = dm_i2c_write(port->i2c_dev, TCPC_ROLE_CTRL, &valb, 1);
+	if (err)
+		tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err);
+	return err;
+}
+
+int tcpc_set_cc_to_sink(struct tcpc_port *port)
+{
+	uint8_t valb;
+	int err;
+
+	if (port == NULL || port->i2c_dev == NULL)
+		return -EINVAL;
+
+	valb = (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) |
+			(TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT) | TCPC_ROLE_CTRL_DRP;
+
+	err = dm_i2c_write(port->i2c_dev, TCPC_ROLE_CTRL, &valb, 1);
+	if (err)
+		tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err);
+	return err;
+}
+
+
+int tcpc_set_plug_orientation(struct tcpc_port *port, enum typec_cc_polarity polarity)
+{
+	uint8_t valb;
+	int err;
+
+	if (port == NULL || port->i2c_dev == NULL)
+		return -EINVAL;
+
+	err = dm_i2c_read(port->i2c_dev, TCPC_TCPC_CTRL, &valb, 1);
+	if (err) {
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err);
+		return -EIO;
+	}
+
+	if (polarity == TYPEC_POLARITY_CC2)
+		valb |= TCPC_TCPC_CTRL_ORIENTATION;
+	else
+		valb &= ~TCPC_TCPC_CTRL_ORIENTATION;
+
+	err = dm_i2c_write(port->i2c_dev, TCPC_TCPC_CTRL, &valb, 1);
+	if (err) {
+		tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+int tcpc_get_cc_status(struct tcpc_port *port, enum typec_cc_polarity *polarity, enum typec_cc_state *state)
+{
+
+	uint8_t valb_cc, cc2, cc1;
+	int err;
+
+	if (port == NULL || port->i2c_dev == NULL || polarity == NULL || state == NULL)
+		return -EINVAL;
+
+	err = dm_i2c_read(port->i2c_dev, TCPC_CC_STATUS, (uint8_t *)&valb_cc, 1);
+	if (err) {
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err);
+		return -EIO;
+	}
+
+	tcpc_debug_log(port, "cc status 0x%x\n", valb_cc);
+
+	cc2 = (valb_cc >> TCPC_CC_STATUS_CC2_SHIFT) & TCPC_CC_STATUS_CC2_MASK;
+	cc1 = (valb_cc >> TCPC_CC_STATUS_CC1_SHIFT) & TCPC_CC_STATUS_CC1_MASK;
+
+	if (valb_cc & TCPC_CC_STATUS_LOOK4CONN)
+		return -EFAULT;
+
+	*state = TYPEC_STATE_OPEN;
+
+	if (valb_cc & TCPC_CC_STATUS_TERM) {
+		if (cc2) {
+			*polarity = TYPEC_POLARITY_CC2;
+
+			switch (cc2) {
+			case 0x1:
+				*state = TYPEC_STATE_SNK_DEFAULT;
+				tcpc_log(port, "SNK.Default on CC2\n");
+				break;
+			case 0x2:
+				*state = TYPEC_STATE_SNK_POWER15;
+				tcpc_log(port, "SNK.Power1.5 on CC2\n");
+				break;
+			case 0x3:
+				*state = TYPEC_STATE_SNK_POWER30;
+				tcpc_log(port, "SNK.Power3.0 on CC2\n");
+				break;
+			}
+		} else if (cc1) {
+			*polarity = TYPEC_POLARITY_CC1;
+
+			switch (cc1) {
+			case 0x1:
+				*state = TYPEC_STATE_SNK_DEFAULT;
+				tcpc_log(port, "SNK.Default on CC1\n");
+				break;
+			case 0x2:
+				*state = TYPEC_STATE_SNK_POWER15;
+				tcpc_log(port, "SNK.Power1.5 on CC1\n");
+				break;
+			case 0x3:
+				*state = TYPEC_STATE_SNK_POWER30;
+				tcpc_log(port, "SNK.Power3.0 on CC1\n");
+				break;
+			}
+		} else {
+			*state = TYPEC_STATE_OPEN;
+			return -EPERM;
+		}
+
+	} else {
+		if (cc2) {
+			*polarity = TYPEC_POLARITY_CC2;
+
+			switch (cc2) {
+			case 0x1:
+				if (cc1 == 0x1) {
+					*state = TYPEC_STATE_SRC_BOTH_RA;
+					tcpc_log(port, "SRC.Ra on both CC1 and CC2\n");
+				} else if (cc1 == 0x2) {
+					*state = TYPEC_STATE_SRC_RD_RA;
+					tcpc_log(port, "SRC.Ra on CC2, SRC.Rd on CC1\n");
+				} else if (cc1 == 0x0) {
+					tcpc_log(port, "SRC.Ra only on CC2\n");
+					return -EFAULT;
+				} else
+					return -EFAULT;
+				break;
+			case 0x2:
+				if (cc1 == 0x1) {
+					*state = TYPEC_STATE_SRC_RD_RA;
+					tcpc_log(port, "SRC.Ra on CC1, SRC.Rd on CC2\n");
+				} else if (cc1 == 0x0) {
+					*state = TYPEC_STATE_SRC_RD;
+					tcpc_log(port, "SRC.Rd on CC2\n");
+				} else
+					return -EFAULT;
+				break;
+			case 0x3:
+				*state = TYPEC_STATE_SRC_RESERVED;
+				return -EFAULT;
+			}
+		} else if (cc1) {
+			*polarity = TYPEC_POLARITY_CC1;
+
+			switch (cc1) {
+			case 0x1:
+				tcpc_log(port, "SRC.Ra only on CC1\n");
+				return -EFAULT;
+			case 0x2:
+				*state = TYPEC_STATE_SRC_RD;
+				tcpc_log(port, "SRC.Rd on CC1\n");
+				break;
+			case 0x3:
+				*state = TYPEC_STATE_SRC_RESERVED;
+				return -EFAULT;
+			}
+		} else {
+			*state = TYPEC_STATE_OPEN;
+			return -EPERM;
+		}
+	}
+
+	return 0;
+}
+
+int tcpc_clear_alert(struct tcpc_port *port, uint16_t clear_mask)
+{
+	int err;
+
+	if (port == NULL || port->i2c_dev == NULL)
+		return -EINVAL;
+
+	err = dm_i2c_write(port->i2c_dev, TCPC_ALERT, (const uint8_t *)&clear_mask, 2);
+	if (err) {
+		tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+int tcpc_fault_status_mask(struct tcpc_port *port, uint8_t fault_mask)
+{
+	int err = 0;
+
+	if (!port || port->i2c_dev == NULL)
+		return -EINVAL;
+
+	err = dm_i2c_write(port->i2c_dev, TCPC_FAULT_STATUS_MASK, &fault_mask, 1);
+	if (err)
+		tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err);
+
+	return err;
+}
+
+int tcpc_send_command(struct tcpc_port *port, uint8_t command)
+{
+	int err;
+
+	if (port == NULL || port->i2c_dev == NULL)
+		return -EINVAL;
+
+	err = dm_i2c_write(port->i2c_dev, TCPC_COMMAND, (const uint8_t *)&command, 1);
+	if (err) {
+		tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+int tcpc_polling_reg(struct tcpc_port *port, uint8_t reg,
+	uint8_t reg_width, uint16_t mask, uint16_t value, ulong timeout_ms)
+{
+	uint16_t val = 0;
+	int err;
+	ulong start;
+
+	if (port == NULL || port->i2c_dev == NULL)
+		return -EINVAL;
+
+	tcpc_debug_log(port, "%s reg 0x%x, mask 0x%x, value 0x%x\n", __func__, reg, mask, value);
+
+	/* TCPC registers is 8 bits or 16 bits */
+	if (reg_width != 1 && reg_width != 2)
+		return -EINVAL;
+
+	start = get_timer(0);	/* Get current timestamp */
+	do {
+		err = dm_i2c_read(port->i2c_dev, reg, (uint8_t *)&val, reg_width);
+		if (err)
+			return -EIO;
+
+		if ((val & mask) == value)
+			return 0;
+	} while (get_timer(0) < (start + timeout_ms));
+
+	return -ETIME;
+}
+
+void tcpc_print_log(struct tcpc_port *port)
+{
+	if (port == NULL)
+		return;
+
+	if (port->log_print == port->log_p) /*nothing to output*/
+		return;
+
+	printf("%s", port->log_print);
+
+	port->log_print = port->log_p;
+}
+
+int tcpc_setup_dfp_mode(struct tcpc_port *port)
+{
+	enum typec_cc_polarity pol;
+	enum typec_cc_state state;
+	int ret;
+
+	if (port == NULL)
+		return -EINVAL;
+
+	if (tcpc_pd_sink_check_charging(port)) {
+		tcpc_log(port, "%s: Can't apply DFP mode when PD is charging\n",
+			__func__);
+		return -EPERM;
+	}
+
+	tcpc_set_cc_to_source(port);
+
+	ret = tcpc_send_command(port, TCPC_CMD_LOOK4CONNECTION);
+	if (ret)
+		return ret;
+
+	/* At least wait tCcStatusDelay + tTCPCFilter + tCcTCPCSampleRate (max) = 200us + 500us + ?ms
+	 * PTN5110 datasheet does not contain the sample rate value, according other productions,
+	 * the sample rate is at ms level, about 2 ms -10ms. So wait 100ms should be enough.
+	 */
+	mdelay(100);
+
+	ret = tcpc_polling_reg(port, TCPC_ALERT, 2, TCPC_ALERT_CC_STATUS, TCPC_ALERT_CC_STATUS, 100);
+	if (ret) {
+		tcpc_log(port, "%s: Polling ALERT register, TCPC_ALERT_CC_STATUS bit failed, ret = %d\n",
+			__func__, ret);
+		return ret;
+	}
+
+	ret = tcpc_get_cc_status(port, &pol, &state);
+	tcpc_clear_alert(port, TCPC_ALERT_CC_STATUS);
+
+	if (!ret) {
+		/* If presenting as Rd/audio mode/open, return */
+		if (state != TYPEC_STATE_SRC_RD_RA && state != TYPEC_STATE_SRC_RD)
+			return -EPERM;
+
+		if (pol == TYPEC_POLARITY_CC1)
+			tcpc_debug_log(port, "polarity cc1\n");
+		else
+			tcpc_debug_log(port, "polarity cc2\n");
+
+		if (port->ss_sel_func)
+			port->ss_sel_func(pol);
+
+		ret = tcpc_set_plug_orientation(port, pol);
+		if (ret)
+			return ret;
+
+		/* Enable source vbus default voltage */
+		ret = tcpc_send_command(port, TCPC_CMD_SRC_VBUS_DEFAULT);
+		if (ret)
+			return ret;
+
+		/* The max vbus on time is 200ms, we add margin 100ms */
+		mdelay(300);
+
+	}
+
+	return 0;
+}
+
+int tcpc_setup_ufp_mode(struct tcpc_port *port)
+{
+	enum typec_cc_polarity pol;
+	enum typec_cc_state state;
+	int ret;
+
+	if (port == NULL)
+		return -EINVAL;
+
+	/* Check if the PD charge is working. If not, need to configure CC role for UFP */
+	if (!tcpc_pd_sink_check_charging(port)) {
+
+		/* Disable the source vbus once it is enabled by DFP mode */
+		tcpc_disable_src_vbus(port);
+
+		tcpc_set_cc_to_sink(port);
+
+		ret = tcpc_send_command(port, TCPC_CMD_LOOK4CONNECTION);
+		if (ret)
+			return ret;
+
+		/* At least wait tCcStatusDelay + tTCPCFilter + tCcTCPCSampleRate (max) = 200us + 500us + ?ms
+		 * PTN5110 datasheet does not contain the sample rate value, according other productions,
+		 * the sample rate is at ms level, about 2 ms -10ms. So wait 100ms should be enough.
+		 */
+		mdelay(100);
+
+		ret = tcpc_polling_reg(port, TCPC_ALERT, 2, TCPC_ALERT_CC_STATUS, TCPC_ALERT_CC_STATUS, 100);
+		if (ret) {
+			tcpc_log(port, "%s: Polling ALERT register, TCPC_ALERT_CC_STATUS bit failed, ret = %d\n",
+				__func__, ret);
+			return ret;
+		}
+
+		ret = tcpc_get_cc_status(port, &pol, &state);
+		tcpc_clear_alert(port, TCPC_ALERT_CC_STATUS);
+
+	} else {
+		ret = tcpc_get_cc_status(port, &pol, &state);
+	}
+
+	if (!ret) {
+		/* If presenting not as sink, then return */
+		if (state != TYPEC_STATE_SNK_DEFAULT && state != TYPEC_STATE_SNK_POWER15 &&
+			state != TYPEC_STATE_SNK_POWER30)
+			return -EPERM;
+
+		if (pol == TYPEC_POLARITY_CC1)
+			tcpc_debug_log(port, "polarity cc1\n");
+		else
+			tcpc_debug_log(port, "polarity cc2\n");
+
+		if (port->ss_sel_func)
+			port->ss_sel_func(pol);
+
+		ret = tcpc_set_plug_orientation(port, pol);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int tcpc_disable_src_vbus(struct tcpc_port *port)
+{
+	int ret;
+
+	if (port == NULL)
+		return -EINVAL;
+
+	/* Disable VBUS*/
+	ret = tcpc_send_command(port, TCPC_CMD_DISABLE_SRC_VBUS);
+	if (ret)
+		return ret;
+
+	/* The max vbus off time is 0.5ms, we add margin 0.5 ms */
+	mdelay(1);
+
+	return 0;
+}
+
+int tcpc_disable_sink_vbus(struct tcpc_port *port)
+{
+	int ret;
+
+	if (port == NULL)
+		return -EINVAL;
+
+	/* Disable SINK VBUS*/
+	ret = tcpc_send_command(port, TCPC_CMD_DISABLE_SINK_VBUS);
+	if (ret)
+		return ret;
+
+	/* The max vbus off time is 0.5ms, we add margin 0.5 ms */
+	mdelay(1);
+
+	return 0;
+}
+
+
+static int tcpc_pd_receive_message(struct tcpc_port *port, struct pd_message *msg)
+{
+	int ret;
+	uint8_t cnt;
+	uint16_t val;
+
+	if (port == NULL || port->i2c_dev == NULL)
+		return -EINVAL;
+
+	/* Generally the max tSenderResponse is 30ms, max tTypeCSendSourceCap is 200ms, we set the timeout to 500ms */
+	ret = tcpc_polling_reg(port, TCPC_ALERT, 2, TCPC_ALERT_RX_STATUS, TCPC_ALERT_RX_STATUS, 500);
+	if (ret) {
+		tcpc_log(port, "%s: Polling ALERT register, TCPC_ALERT_RX_STATUS bit failed, ret = %d\n",
+			__func__, ret);
+		return ret;
+	}
+
+	cnt = 0;
+	ret = dm_i2c_read(port->i2c_dev, TCPC_RX_BYTE_CNT, (uint8_t *)&cnt, 1);
+	if (ret)
+		return -EIO;
+
+	if (cnt > 0) {
+		ret = dm_i2c_read(port->i2c_dev, TCPC_RX_BUF_FRAME_TYPE, (uint8_t *)msg, cnt);
+		if (ret)
+			return -EIO;
+
+		/* Clear RX status alert bit */
+		val = TCPC_ALERT_RX_STATUS;
+		ret = dm_i2c_write(port->i2c_dev, TCPC_ALERT, (const uint8_t *)&val, 2);
+		if (ret)
+			return -EIO;
+	}
+
+	return cnt;
+}
+
+static int tcpc_pd_transmit_message(struct tcpc_port *port, struct pd_message *msg_p, uint8_t bytes)
+{
+	int ret;
+	uint8_t valb;
+	uint16_t val = 0;
+
+	if (port == NULL || port->i2c_dev == NULL)
+		return -EINVAL;
+
+	if (msg_p == NULL || bytes <= 0)
+		return -EINVAL;
+
+	ret = dm_i2c_write(port->i2c_dev, TCPC_TX_BYTE_CNT, (const uint8_t *)&bytes, 1);
+	if (ret)
+		return -EIO;
+
+	ret = dm_i2c_write(port->i2c_dev, TCPC_TX_HDR, (const uint8_t *)&(msg_p->header), bytes);
+	if (ret)
+		return -EIO;
+
+	valb = (3 << TCPC_TRANSMIT_RETRY_SHIFT) | (TCPC_TX_SOP << TCPC_TRANSMIT_TYPE_SHIFT);
+	ret = dm_i2c_write(port->i2c_dev, TCPC_TRANSMIT, (const uint8_t *)&valb, 1);
+	if (ret)
+		return -EIO;
+
+	/* Max tReceive is 1.1ms, we set to 5ms timeout */
+	ret = tcpc_polling_reg(port, TCPC_ALERT, 2, TCPC_ALERT_TX_SUCCESS, TCPC_ALERT_TX_SUCCESS, 5);
+	if (ret) {
+		if (ret == -ETIME) {
+			ret = dm_i2c_read(port->i2c_dev, TCPC_ALERT, (uint8_t *)&val, 2);
+			if (ret)
+				return -EIO;
+
+			if (val & TCPC_ALERT_TX_FAILED)
+				tcpc_log(port, "%s: PD TX FAILED, ALERT = 0x%x\n", __func__, val);
+
+			if (val & TCPC_ALERT_TX_DISCARDED)
+				tcpc_log(port, "%s: PD TX DISCARDED, ALERT = 0x%x\n", __func__, val);
+
+		} else {
+			tcpc_log(port, "%s: Polling ALERT register, TCPC_ALERT_TX_SUCCESS bit failed, ret = %d\n",
+				__func__, ret);
+		}
+	} else {
+		port->tx_msg_id = (port->tx_msg_id + 1) & PD_HEADER_ID_MASK;
+	}
+
+	/* Clear ALERT status */
+	val &= (TCPC_ALERT_TX_FAILED | TCPC_ALERT_TX_DISCARDED | TCPC_ALERT_TX_SUCCESS);
+	ret = dm_i2c_write(port->i2c_dev, TCPC_ALERT, (const uint8_t *)&val, 2);
+	if (ret)
+		return -EIO;
+
+	return ret;
+}
+
+static void tcpc_log_source_caps(struct tcpc_port *port, struct pd_message *msg, unsigned int capcount)
+{
+	int i;
+
+	for (i = 0; i < capcount; i++) {
+		u32 pdo = msg->payload[i];
+		enum pd_pdo_type type = pdo_type(pdo);
+
+		tcpc_log(port, "PDO %d: type %d, ",
+			 i, type);
+
+		switch (type) {
+		case PDO_TYPE_FIXED:
+			tcpc_log(port, "%u mV, %u mA [%s%s%s%s%s%s]\n",
+				  pdo_fixed_voltage(pdo),
+				  pdo_max_current(pdo),
+				  (pdo & PDO_FIXED_DUAL_ROLE) ?
+							"R" : "",
+				  (pdo & PDO_FIXED_SUSPEND) ?
+							"S" : "",
+				  (pdo & PDO_FIXED_HIGHER_CAP) ?
+							"H" : "",
+				  (pdo & PDO_FIXED_USB_COMM) ?
+							"U" : "",
+				  (pdo & PDO_FIXED_DATA_SWAP) ?
+							"D" : "",
+				  (pdo & PDO_FIXED_EXTPOWER) ?
+							"E" : "");
+			break;
+		case PDO_TYPE_VAR:
+			tcpc_log(port, "%u-%u mV, %u mA\n",
+				  pdo_min_voltage(pdo),
+				  pdo_max_voltage(pdo),
+				  pdo_max_current(pdo));
+			break;
+		case PDO_TYPE_BATT:
+			tcpc_log(port, "%u-%u mV, %u mW\n",
+				  pdo_min_voltage(pdo),
+				  pdo_max_voltage(pdo),
+				  pdo_max_power(pdo));
+			break;
+		default:
+			tcpc_log(port, "undefined\n");
+			break;
+		}
+	}
+}
+
+static int tcpc_pd_select_pdo(struct pd_message *msg, uint32_t capcount, uint32_t max_snk_mv, uint32_t max_snk_ma)
+{
+	unsigned int i, max_mw = 0, max_mv = 0;
+	int ret = -EINVAL;
+
+	/*
+	 * Select the source PDO providing the most power while staying within
+	 * the board's voltage limits. Prefer PDO providing exp
+	 */
+	for (i = 0; i < capcount; i++) {
+		u32 pdo = msg->payload[i];
+		enum pd_pdo_type type = pdo_type(pdo);
+		unsigned int mv, ma, mw;
+
+		if (type == PDO_TYPE_FIXED)
+			mv = pdo_fixed_voltage(pdo);
+		else
+			mv = pdo_min_voltage(pdo);
+
+		if (type == PDO_TYPE_BATT) {
+			mw = pdo_max_power(pdo);
+		} else {
+			ma = min(pdo_max_current(pdo),
+				 max_snk_ma);
+			mw = ma * mv / 1000;
+		}
+
+		/* Perfer higher voltages if available */
+		if ((mw > max_mw || (mw == max_mw && mv > max_mv)) &&
+		    mv <= max_snk_mv) {
+			ret = i;
+			max_mw = mw;
+			max_mv = mv;
+		}
+	}
+
+	return ret;
+}
+
+static int tcpc_pd_build_request(struct tcpc_port *port,
+										struct pd_message *msg,
+										uint32_t capcount,
+										uint32_t max_snk_mv,
+										uint32_t max_snk_ma,
+										uint32_t max_snk_mw,
+										uint32_t operating_snk_mw,
+										uint32_t *rdo)
+{
+	unsigned int mv, ma, mw, flags;
+	unsigned int max_ma, max_mw;
+	enum pd_pdo_type type;
+	int index;
+	u32 pdo;
+
+	index = tcpc_pd_select_pdo(msg, capcount, max_snk_mv, max_snk_ma);
+	if (index < 0)
+		return -EINVAL;
+
+	pdo = msg->payload[index];
+	type = pdo_type(pdo);
+
+	if (type == PDO_TYPE_FIXED)
+		mv = pdo_fixed_voltage(pdo);
+	else
+		mv = pdo_min_voltage(pdo);
+
+	/* Select maximum available current within the board's power limit */
+	if (type == PDO_TYPE_BATT) {
+		mw = pdo_max_power(pdo);
+		ma = 1000 * min(mw, max_snk_mw) / mv;
+	} else {
+		ma = min(pdo_max_current(pdo),
+			 1000 * max_snk_mw / mv);
+	}
+	ma = min(ma, max_snk_ma);
+
+	/* XXX: Any other flags need to be set? */
+	flags = 0;
+
+	/* Set mismatch bit if offered power is less than operating power */
+	mw = ma * mv / 1000;
+	max_ma = ma;
+	max_mw = mw;
+	if (mw < operating_snk_mw) {
+		flags |= RDO_CAP_MISMATCH;
+		max_mw = operating_snk_mw;
+		max_ma = max_mw * 1000 / mv;
+	}
+
+	if (type == PDO_TYPE_BATT) {
+		*rdo = RDO_BATT(index + 1, mw, max_mw, flags);
+
+		tcpc_log(port, "Requesting PDO %d: %u mV, %u mW%s\n",
+			 index, mv, mw,
+			 flags & RDO_CAP_MISMATCH ? " [mismatch]" : "");
+	} else {
+		*rdo = RDO_FIXED(index + 1, ma, max_ma, flags);
+
+		tcpc_log(port, "Requesting PDO %d: %u mV, %u mA%s\n",
+			 index, mv, ma,
+			 flags & RDO_CAP_MISMATCH ? " [mismatch]" : "");
+	}
+
+	return 0;
+}
+
+static void tcpc_pd_sink_process(struct tcpc_port *port)
+{
+	int ret;
+	uint8_t msgtype;
+	uint32_t objcnt;
+	struct pd_message msg;
+	enum pd_sink_state pd_state = WAIT_SOURCE_CAP;
+
+	while (tcpc_pd_receive_message(port, &msg) > 0) {
+
+		msgtype = pd_header_type(msg.header);
+		objcnt = pd_header_cnt_le(msg.header);
+
+		tcpc_debug_log(port, "get msg, type %d, cnt %d\n", msgtype, objcnt);
+
+		switch (pd_state) {
+		case WAIT_SOURCE_CAP:
+		case SINK_READY:
+			if (msgtype != PD_DATA_SOURCE_CAP)
+				continue;
+
+			uint32_t rdo = 0;
+
+			tcpc_log_source_caps(port, &msg, objcnt);
+
+			tcpc_pd_build_request(port, &msg, objcnt,
+				port->cfg.max_snk_mv, port->cfg.max_snk_ma,
+				port->cfg.max_snk_mw, port->cfg.op_snk_mv,
+				&rdo);
+
+			memset(&msg, 0, sizeof(msg));
+			msg.header = PD_HEADER(PD_DATA_REQUEST, 0, 0, port->tx_msg_id, 1);  /* power sink, data device, id 0, len 1 */
+			msg.payload[0] = rdo;
+
+			ret = tcpc_pd_transmit_message(port, &msg, 6);
+			if (ret)
+				tcpc_log(port, "send request failed\n");
+			else
+				pd_state = WAIT_SOURCE_ACCEPT;
+
+			break;
+		case WAIT_SOURCE_ACCEPT:
+			if (objcnt > 0) /* Should be ctrl message */
+				continue;
+
+			if (msgtype == PD_CTRL_ACCEPT) {
+				pd_state = WAIT_SOURCE_READY;
+				tcpc_log(port, "Source accept request\n");
+			} else if (msgtype == PD_CTRL_REJECT) {
+				tcpc_log(port, "Source reject request\n");
+				return;
+			}
+
+			break;
+		case WAIT_SOURCE_READY:
+			if (objcnt > 0) /* Should be ctrl message */
+				continue;
+
+			if (msgtype == PD_CTRL_PS_RDY) {
+				tcpc_log(port, "PD source ready!\n");
+				pd_state = SINK_READY;
+			}
+
+			break;
+		default:
+			tcpc_log(port, "unexpect status: %u\n", pd_state);
+			break;
+		}
+	}
+}
+
+bool tcpc_pd_sink_check_charging(struct tcpc_port *port)
+{
+	uint8_t valb;
+	int err;
+	enum typec_cc_polarity pol;
+	enum typec_cc_state state;
+
+	if (port == NULL || port->i2c_dev == NULL)
+		return false;
+
+	/* Check the CC status, must be sink */
+	err = tcpc_get_cc_status(port, &pol, &state);
+	if (err || (state != TYPEC_STATE_SNK_POWER15
+		&& state != TYPEC_STATE_SNK_POWER30
+		&& state != TYPEC_STATE_SNK_DEFAULT)) {
+		tcpc_debug_log(port, "TCPC wrong state for PD charging, err = %d, CC = 0x%x\n",
+			err, state);
+		return false;
+	}
+
+	/* Check the VBUS PRES and SINK VBUS for dead battery */
+	err = dm_i2c_read(port->i2c_dev, TCPC_POWER_STATUS, &valb, 1);
+	if (err) {
+		tcpc_debug_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err);
+		return false;
+	}
+
+	if (!(valb & TCPC_POWER_STATUS_VBUS_PRES)) {
+		tcpc_debug_log(port, "VBUS NOT PRES \n");
+		return false;
+	}
+
+	if (!(valb & TCPC_POWER_STATUS_SINKING_VBUS)) {
+		tcpc_debug_log(port, "SINK VBUS is not enabled for dead battery\n");
+		return false;
+	}
+
+	return true;
+}
+
+static int tcpc_pd_sink_disable(struct tcpc_port *port)
+{
+	uint8_t valb;
+	int err;
+
+	if (port == NULL || port->i2c_dev == NULL)
+		return -EINVAL;
+
+	port->pd_state = UNATTACH;
+
+	/* Check the VBUS PRES and SINK VBUS for dead battery */
+	err = dm_i2c_read(port->i2c_dev, TCPC_POWER_STATUS, &valb, 1);
+	if (err) {
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err);
+		return -EIO;
+	}
+
+	if ((valb & TCPC_POWER_STATUS_VBUS_PRES) && (valb & TCPC_POWER_STATUS_SINKING_VBUS)) {
+		err = dm_i2c_read(port->i2c_dev, TCPC_POWER_CTRL, (uint8_t *)&valb, 1);
+		if (err) {
+			tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err);
+			return -EIO;
+		}
+
+		valb &= ~TCPC_POWER_CTRL_AUTO_DISCH_DISCO; /* disable AutoDischargeDisconnect */
+		err = dm_i2c_write(port->i2c_dev, TCPC_POWER_CTRL, (const uint8_t *)&valb, 1);
+		if (err) {
+			tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err);
+			return -EIO;
+		}
+
+		tcpc_disable_sink_vbus(port);
+	}
+
+	if (port->cfg.switch_setup_func)
+		port->cfg.switch_setup_func(port);
+
+	return 0;
+}
+
+static int tcpc_pd_sink_init(struct tcpc_port *port)
+{
+	uint8_t valb;
+	uint16_t val;
+	int err;
+	enum typec_cc_polarity pol;
+	enum typec_cc_state state;
+
+	if (port == NULL || port->i2c_dev == NULL)
+		return -EINVAL;
+
+	port->pd_state = UNATTACH;
+
+	/* Check the VBUS PRES and SINK VBUS for dead battery */
+	err = dm_i2c_read(port->i2c_dev, TCPC_POWER_STATUS, &valb, 1);
+	if (err) {
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err);
+		return -EIO;
+	}
+
+	if (!(valb & TCPC_POWER_STATUS_VBUS_PRES)) {
+		tcpc_debug_log(port, "VBUS NOT PRES \n");
+		return -EPERM;
+	}
+
+	if (!(valb & TCPC_POWER_STATUS_SINKING_VBUS)) {
+		tcpc_debug_log(port, "SINK VBUS is not enabled for dead battery\n");
+		return -EPERM;
+	}
+
+	err = dm_i2c_read(port->i2c_dev, TCPC_ALERT, (uint8_t *)&val, 2);
+	if (err) {
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err);
+		return -EIO;
+	}
+
+	if (!(val & TCPC_ALERT_CC_STATUS)) {
+		tcpc_debug_log(port, "CC STATUS not detected for dead battery\n");
+		return -EPERM;
+	}
+
+	err = tcpc_get_cc_status(port, &pol, &state);
+	if (err || (state != TYPEC_STATE_SNK_POWER15
+		&& state != TYPEC_STATE_SNK_POWER30
+		&& state != TYPEC_STATE_SNK_DEFAULT)) {
+		tcpc_log(port, "TCPC wrong state for dead battery, err = %d, CC = 0x%x\n",
+			err, state);
+		return -EPERM;
+	} else {
+		err = tcpc_set_plug_orientation(port, pol);
+		if (err) {
+			tcpc_log(port, "TCPC set plug orientation failed, err = %d\n", err);
+			return err;
+		}
+		port->pd_state = ATTACHED;
+	}
+
+	err = dm_i2c_read(port->i2c_dev, TCPC_POWER_CTRL, (uint8_t *)&valb, 1);
+	if (err) {
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err);
+		return -EIO;
+	}
+
+	valb &= ~TCPC_POWER_CTRL_AUTO_DISCH_DISCO; /* disable AutoDischargeDisconnect */
+	err = dm_i2c_write(port->i2c_dev, TCPC_POWER_CTRL, (const uint8_t *)&valb, 1);
+	if (err) {
+		tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err);
+		return -EIO;
+	}
+
+	if (port->cfg.switch_setup_func)
+		port->cfg.switch_setup_func(port);
+
+	/* As sink role */
+	valb = 0x00;
+	err = dm_i2c_write(port->i2c_dev, TCPC_MSG_HDR_INFO, (const uint8_t *)&valb, 1);
+	if (err) {
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err);
+		return -EIO;
+	}
+
+	/* Enable rx */
+	valb = TCPC_RX_DETECT_SOP | TCPC_RX_DETECT_HARD_RESET;
+	err = dm_i2c_write(port->i2c_dev, TCPC_RX_DETECT, (const uint8_t *)&valb, 1);
+	if (err) {
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err);
+		return -EIO;
+	}
+
+	tcpc_pd_sink_process(port);
+
+	return 0;
+}
+
+int tcpc_init(struct tcpc_port *port, struct tcpc_port_config config, ss_mux_sel ss_sel_func)
+{
+	int ret;
+	uint8_t valb;
+	uint16_t vid, pid;
+	struct udevice *bus;
+	struct udevice *i2c_dev = NULL;
+
+	memset(port, 0, sizeof(struct tcpc_port));
+
+	if (port == NULL)
+		return -EINVAL;
+
+	port->cfg = config;
+	port->tx_msg_id = 0;
+	port->ss_sel_func = ss_sel_func;
+	port->log_p = (char *)&(port->logbuffer);
+	port->log_size = TCPC_LOG_BUFFER_SIZE;
+	port->log_print = port->log_p;
+	memset(&(port->logbuffer), 0, TCPC_LOG_BUFFER_SIZE);
+
+	ret = uclass_get_device_by_seq(UCLASS_I2C, port->cfg.i2c_bus, &bus);
+	if (ret) {
+		printf("%s: Can't find bus\n", __func__);
+		return -EINVAL;
+	}
+
+	ret = dm_i2c_probe(bus, port->cfg.addr, 0, &i2c_dev);
+	if (ret) {
+		printf("%s: Can't find device id=0x%x\n",
+			__func__, config.addr);
+		return -ENODEV;
+	}
+
+	port->i2c_dev = i2c_dev;
+
+	/* Check the Initialization Status bit in 1s */
+	ret = tcpc_polling_reg(port, TCPC_POWER_STATUS, 1, TCPC_POWER_STATUS_UNINIT, 0, 1000);
+	if (ret) {
+		tcpc_log(port, "%s: Polling TCPC POWER STATUS Initialization Status bit failed, ret = %d\n",
+			__func__, ret);
+		return ret;
+	}
+
+	dm_i2c_read(port->i2c_dev, TCPC_POWER_STATUS, &valb, 1);
+	tcpc_debug_log(port, "POWER STATUS: 0x%x\n", valb);
+
+	/* Clear AllRegistersResetToDefault */
+	valb = 0x80;
+	ret = dm_i2c_write(port->i2c_dev, TCPC_FAULT_STATUS, (const uint8_t *)&valb, 1);
+	if (ret) {
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+
+	/* Read Vendor ID and Product ID */
+	ret = dm_i2c_read(port->i2c_dev, TCPC_VENDOR_ID, (uint8_t *)&vid, 2);
+	if (ret) {
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+
+	ret = dm_i2c_read(port->i2c_dev, TCPC_PRODUCT_ID, (uint8_t *)&pid, 2);
+	if (ret) {
+		tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+
+	tcpc_log(port, "TCPC:  Vendor ID [0x%x], Product ID [0x%x], Addr [I2C%u 0x%x]\n",
+		vid, pid, port->cfg.i2c_bus, port->cfg.addr);
+
+	if (!port->cfg.disable_pd) {
+		if  (port->cfg.port_type == TYPEC_PORT_UFP
+			|| port->cfg.port_type == TYPEC_PORT_DRP)
+			tcpc_pd_sink_init(port);
+	} else {
+		tcpc_pd_sink_disable(port);
+	}
+
+	/* Mask all fault status */
+	tcpc_fault_status_mask(port, 0);
+
+	tcpc_clear_alert(port, 0xffff);
+
+	tcpc_print_log(port);
+
+	return 0;
+}
diff --git a/board/freescale/common/tcpc.h b/board/freescale/common/tcpc.h
new file mode 100644
index 00000000000..564a5cf21e0
--- /dev/null
+++ b/board/freescale/common/tcpc.h
@@ -0,0 +1,471 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __TCPCI_H
+#define __TCPCI_H
+
+#include <dm.h>
+
+#define TCPC_VENDOR_ID			0x0
+#define TCPC_PRODUCT_ID			0x2
+
+#define TCPC_ALERT					0x10
+#define TCPC_ALERT_VBUS_DISCNCT		BIT(11)
+#define TCPC_ALERT_RX_BUF_OVF		BIT(10)
+#define TCPC_ALERT_FAULT			BIT(9)
+#define TCPC_ALERT_V_ALARM_LO		BIT(8)
+#define TCPC_ALERT_V_ALARM_HI		BIT(7)
+#define TCPC_ALERT_TX_SUCCESS		BIT(6)
+#define TCPC_ALERT_TX_DISCARDED		BIT(5)
+#define TCPC_ALERT_TX_FAILED		BIT(4)
+#define TCPC_ALERT_RX_HARD_RST		BIT(3)
+#define TCPC_ALERT_RX_STATUS		BIT(2)
+#define TCPC_ALERT_POWER_STATUS		BIT(1)
+#define TCPC_ALERT_CC_STATUS		BIT(0)
+
+#define TCPC_FAULT_STATUS_MASK		0x15
+
+#define TCPC_TCPC_CTRL				0x19
+#define TCPC_TCPC_CTRL_BIST_MODE	BIT(1)
+#define TCPC_TCPC_CTRL_ORIENTATION	BIT(0)
+
+#define TCPC_ROLE_CTRL				0x1a
+#define TCPC_ROLE_CTRL_DRP			BIT(6)
+#define TCPC_ROLE_CTRL_RP_VAL_SHIFT	4
+#define TCPC_ROLE_CTRL_RP_VAL_MASK	0x3
+#define TCPC_ROLE_CTRL_RP_VAL_DEF	0x0
+#define TCPC_ROLE_CTRL_RP_VAL_1_5	0x1
+#define TCPC_ROLE_CTRL_RP_VAL_3_0	0x2
+#define TCPC_ROLE_CTRL_CC2_SHIFT	2
+#define TCPC_ROLE_CTRL_CC2_MASK		0x3
+#define TCPC_ROLE_CTRL_CC1_SHIFT	0
+#define TCPC_ROLE_CTRL_CC1_MASK		0x3
+#define TCPC_ROLE_CTRL_CC_RA		0x0
+#define TCPC_ROLE_CTRL_CC_RP		0x1
+#define TCPC_ROLE_CTRL_CC_RD		0x2
+#define TCPC_ROLE_CTRL_CC_OPEN		0x3
+
+#define TCPC_POWER_CTRL						0x1c
+#define TCPC_POWER_CTRL_EN_VCONN			BIT(0)
+#define TCPC_POWER_CTRL_VCONN_POWER			BIT(1)
+#define TCPC_POWER_CTRL_FORCE_DISCH			BIT(2)
+#define TCPC_POWER_CTRL_EN_BLEED_CH			BIT(3)
+#define TCPC_POWER_CTRL_AUTO_DISCH_DISCO	BIT(4)
+#define TCPC_POWER_CTRL_DIS_V_ALARMS		BIT(5)
+#define TCPC_POWER_CTRL_VBUS_V_MONITOR		BIT(6)
+
+#define TCPC_CC_STATUS					0x1d
+#define TCPC_CC_STATUS_LOOK4CONN		BIT(5)
+#define TCPC_CC_STATUS_TERM				BIT(4)
+#define TCPC_CC_STATUS_CC2_SHIFT		2
+#define TCPC_CC_STATUS_CC2_MASK			0x3
+#define TCPC_CC_STATUS_CC1_SHIFT		0
+#define TCPC_CC_STATUS_CC1_MASK			0x3
+
+#define TCPC_POWER_STATUS				0x1e
+#define TCPC_POWER_STATUS_UNINIT		BIT(6)
+#define TCPC_POWER_STATUS_VBUS_DET		BIT(3)
+#define TCPC_POWER_STATUS_VBUS_PRES		BIT(2)
+#define TCPC_POWER_STATUS_SINKING_VBUS	BIT(0)
+
+#define TCPC_FAULT_STATUS               0x1f
+
+#define TCPC_COMMAND					0x23
+#define TCPC_CMD_WAKE_I2C				0x11
+#define TCPC_CMD_DISABLE_VBUS_DETECT	0x22
+#define TCPC_CMD_ENABLE_VBUS_DETECT		0x33
+#define TCPC_CMD_DISABLE_SINK_VBUS		0x44
+#define TCPC_CMD_SINK_VBUS				0x55
+#define TCPC_CMD_DISABLE_SRC_VBUS		0x66
+#define TCPC_CMD_SRC_VBUS_DEFAULT		0x77
+#define TCPC_CMD_SRC_VBUS_HIGH			0x88
+#define TCPC_CMD_LOOK4CONNECTION		0x99
+#define TCPC_CMD_RXONEMORE				0xAA
+#define TCPC_CMD_I2C_IDLE				0xFF
+
+#define TCPC_DEV_CAP_1					0x24
+#define TCPC_DEV_CAP_2					0x26
+#define TCPC_STD_INPUT_CAP				0x28
+#define TCPC_STD_OUTPUT_CAP				0x29
+
+#define TCPC_MSG_HDR_INFO				0x2e
+#define TCPC_MSG_HDR_INFO_DATA_ROLE		BIT(3)
+#define TCPC_MSG_HDR_INFO_PWR_ROLE		BIT(0)
+#define TCPC_MSG_HDR_INFO_REV_SHIFT		1
+#define TCPC_MSG_HDR_INFO_REV_MASK		0x3
+
+#define TCPC_RX_DETECT					0x2f
+#define TCPC_RX_DETECT_HARD_RESET		BIT(5)
+#define TCPC_RX_DETECT_SOP				BIT(0)
+
+#define TCPC_RX_BYTE_CNT				0x30
+#define TCPC_RX_BUF_FRAME_TYPE			0x31
+#define TCPC_RX_HDR						0x32
+#define TCPC_RX_DATA					0x34 /* through 0x4f */
+
+#define TCPC_TRANSMIT					0x50
+#define TCPC_TRANSMIT_RETRY_SHIFT		4
+#define TCPC_TRANSMIT_RETRY_MASK		0x3
+#define TCPC_TRANSMIT_TYPE_SHIFT		0
+#define TCPC_TRANSMIT_TYPE_MASK			0x7
+
+#define TCPC_TX_BYTE_CNT				0x51
+#define TCPC_TX_HDR						0x52
+#define TCPC_TX_DATA					0x54 /* through 0x6f */
+
+#define TCPC_VBUS_VOLTAGE					0x70
+#define TCPC_VBUS_VOL_MASK					0x3ff
+#define TCPC_VBUS_VOL_SCALE_FACTOR_MASK		0xc00
+#define TCPC_VBUS_VOL_SCALE_FACTOR_SHIFT	10
+#define TCPC_VBUS_VOL_MV_UNIT				25
+
+#define TCPC_VBUS_SINK_DISCONNECT_THRESH	0x72
+#define TCPC_VBUS_STOP_DISCHARGE_THRESH		0x74
+#define TCPC_VBUS_VOLTAGE_ALARM_HI_CFG		0x76
+#define TCPC_VBUS_VOLTAGE_ALARM_LO_CFG		0x78
+
+enum typec_role {
+	TYPEC_SINK,
+	TYPEC_SOURCE,
+	TYPEC_ROLE_UNKNOWN,
+};
+
+enum typec_data_role {
+	TYPEC_DEVICE,
+	TYPEC_HOST,
+};
+
+enum typec_cc_polarity {
+	TYPEC_POLARITY_CC1,
+	TYPEC_POLARITY_CC2,
+};
+
+enum typec_cc_state {
+	TYPEC_STATE_OPEN,
+	TYPEC_STATE_SRC_BOTH_RA,
+	TYPEC_STATE_SRC_RD_RA,
+	TYPEC_STATE_SRC_RD,
+	TYPEC_STATE_SRC_RESERVED,
+	TYPEC_STATE_SNK_DEFAULT,
+	TYPEC_STATE_SNK_POWER15,
+	TYPEC_STATE_SNK_POWER30,
+};
+
+
+/* USB PD Messages */
+enum pd_ctrl_msg_type {
+	/* 0 Reserved */
+	PD_CTRL_GOOD_CRC = 1,
+	PD_CTRL_GOTO_MIN = 2,
+	PD_CTRL_ACCEPT = 3,
+	PD_CTRL_REJECT = 4,
+	PD_CTRL_PING = 5,
+	PD_CTRL_PS_RDY = 6,
+	PD_CTRL_GET_SOURCE_CAP = 7,
+	PD_CTRL_GET_SINK_CAP = 8,
+	PD_CTRL_DR_SWAP = 9,
+	PD_CTRL_PR_SWAP = 10,
+	PD_CTRL_VCONN_SWAP = 11,
+	PD_CTRL_WAIT = 12,
+	PD_CTRL_SOFT_RESET = 13,
+	/* 14-15 Reserved */
+};
+
+enum pd_data_msg_type {
+	/* 0 Reserved */
+	PD_DATA_SOURCE_CAP = 1,
+	PD_DATA_REQUEST = 2,
+	PD_DATA_BIST = 3,
+	PD_DATA_SINK_CAP = 4,
+	/* 5-14 Reserved */
+	PD_DATA_VENDOR_DEF = 15,
+};
+
+enum tcpc_transmit_type {
+	TCPC_TX_SOP = 0,
+	TCPC_TX_SOP_PRIME = 1,
+	TCPC_TX_SOP_PRIME_PRIME = 2,
+	TCPC_TX_SOP_DEBUG_PRIME = 3,
+	TCPC_TX_SOP_DEBUG_PRIME_PRIME = 4,
+	TCPC_TX_HARD_RESET = 5,
+	TCPC_TX_CABLE_RESET = 6,
+	TCPC_TX_BIST_MODE_2 = 7
+};
+
+enum pd_sink_state{
+	UNATTACH = 0,
+	ATTACHED,
+	WAIT_SOURCE_CAP,
+	WAIT_SOURCE_ACCEPT,
+	WAIT_SOURCE_READY,
+	SINK_READY,
+};
+
+
+#define PD_REV10        0x0
+#define PD_REV20        0x1
+
+#define PD_HEADER_CNT_SHIFT     12
+#define PD_HEADER_CNT_MASK      0x7
+#define PD_HEADER_ID_SHIFT      9
+#define PD_HEADER_ID_MASK       0x7
+#define PD_HEADER_PWR_ROLE      BIT(8)
+#define PD_HEADER_REV_SHIFT     6
+#define PD_HEADER_REV_MASK      0x3
+#define PD_HEADER_DATA_ROLE     BIT(5)
+#define PD_HEADER_TYPE_SHIFT    0
+#define PD_HEADER_TYPE_MASK     0xf
+
+#define PD_HEADER(type, pwr, data, id, cnt)                             \
+	((((type) & PD_HEADER_TYPE_MASK) << PD_HEADER_TYPE_SHIFT) |     \
+	 ((pwr) == TYPEC_SOURCE ? PD_HEADER_PWR_ROLE : 0) |             \
+	 ((data) == TYPEC_HOST ? PD_HEADER_DATA_ROLE : 0) |             \
+	 (PD_REV20 << PD_HEADER_REV_SHIFT) |                            \
+	 (((id) & PD_HEADER_ID_MASK) << PD_HEADER_ID_SHIFT) |           \
+	 (((cnt) & PD_HEADER_CNT_MASK) << PD_HEADER_CNT_SHIFT))
+
+
+static inline unsigned int pd_header_cnt(uint16_t header)
+{
+	return (header >> PD_HEADER_CNT_SHIFT) & PD_HEADER_CNT_MASK;
+}
+
+static inline unsigned int pd_header_cnt_le(__le16 header)
+{
+	return pd_header_cnt(le16_to_cpu(header));
+}
+
+static inline unsigned int pd_header_type(uint16_t header)
+{
+	return (header >> PD_HEADER_TYPE_SHIFT) & PD_HEADER_TYPE_MASK;
+}
+
+static inline unsigned int pd_header_type_le(__le16 header)
+{
+	return pd_header_type(le16_to_cpu(header));
+}
+
+#define PD_MAX_PAYLOAD          7
+
+struct pd_message {
+	uint8_t   frametype;
+	uint16_t  header;
+	uint32_t  payload[PD_MAX_PAYLOAD];
+} __packed;
+
+enum pd_pdo_type {
+	PDO_TYPE_FIXED = 0,
+	PDO_TYPE_BATT = 1,
+	PDO_TYPE_VAR = 2,
+};
+
+
+#define PDO_TYPE_SHIFT          30
+#define PDO_TYPE_MASK           0x3
+
+#define PDO_TYPE(t)     ((t) << PDO_TYPE_SHIFT)
+
+#define PDO_VOLT_MASK           0x3ff
+#define PDO_CURR_MASK           0x3ff
+#define PDO_PWR_MASK            0x3ff
+
+#define PDO_FIXED_DUAL_ROLE     BIT(29) /* Power role swap supported */
+#define PDO_FIXED_SUSPEND       BIT(28) /* USB Suspend supported (Source) */
+#define PDO_FIXED_HIGHER_CAP    BIT(28) /* Requires more than vSafe5V (Sink) */
+#define PDO_FIXED_EXTPOWER      BIT(27) /* Externally powered */
+#define PDO_FIXED_USB_COMM      BIT(26) /* USB communications capable */
+#define PDO_FIXED_DATA_SWAP     BIT(25) /* Data role swap supported */
+#define PDO_FIXED_VOLT_SHIFT    10      /* 50mV units */
+#define PDO_FIXED_CURR_SHIFT    0       /* 10mA units */
+
+#define PDO_FIXED_VOLT(mv)      ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT)
+#define PDO_FIXED_CURR(ma)      ((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT)
+
+#define PDO_FIXED(mv, ma, flags)                        \
+	(PDO_TYPE(PDO_TYPE_FIXED) | (flags) |           \
+	 PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma))
+
+#define PDO_BATT_MAX_VOLT_SHIFT 20      /* 50mV units */
+#define PDO_BATT_MIN_VOLT_SHIFT 10      /* 50mV units */
+#define PDO_BATT_MAX_PWR_SHIFT  0       /* 250mW units */
+
+#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT)
+#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT)
+#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT)
+
+#define PDO_BATT(min_mv, max_mv, max_mw)                        \
+	(PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) |  \
+	 PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw))
+
+#define PDO_VAR_MAX_VOLT_SHIFT  20      /* 50mV units */
+#define PDO_VAR_MIN_VOLT_SHIFT  10      /* 50mV units */
+#define PDO_VAR_MAX_CURR_SHIFT  0       /* 10mA units */
+
+#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT)
+#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT)
+#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT)
+
+#define PDO_VAR(min_mv, max_mv, max_ma)                         \
+	(PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) |    \
+	 PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma))
+
+static inline enum pd_pdo_type pdo_type(uint32_t pdo)
+{
+	return (pdo >> PDO_TYPE_SHIFT) & PDO_TYPE_MASK;
+}
+
+static inline unsigned int pdo_fixed_voltage(uint32_t pdo)
+{
+	return ((pdo >> PDO_FIXED_VOLT_SHIFT) & PDO_VOLT_MASK) * 50;
+}
+
+static inline unsigned int pdo_min_voltage(uint32_t pdo)
+{
+	return ((pdo >> PDO_VAR_MIN_VOLT_SHIFT) & PDO_VOLT_MASK) * 50;
+}
+
+static inline unsigned int pdo_max_voltage(uint32_t pdo)
+{
+	return ((pdo >> PDO_VAR_MAX_VOLT_SHIFT) & PDO_VOLT_MASK) * 50;
+}
+
+static inline unsigned int pdo_max_current(uint32_t pdo)
+{
+	return ((pdo >> PDO_VAR_MAX_CURR_SHIFT) & PDO_CURR_MASK) * 10;
+}
+
+static inline unsigned int pdo_max_power(uint32_t pdo)
+{
+	return ((pdo >> PDO_BATT_MAX_PWR_SHIFT) & PDO_PWR_MASK) * 250;
+}
+
+/* RDO: Request Data Object */
+#define RDO_OBJ_POS_SHIFT       28
+#define RDO_OBJ_POS_MASK        0x7
+#define RDO_GIVE_BACK           BIT(27) /* Supports reduced operating current */
+#define RDO_CAP_MISMATCH        BIT(26) /* Not satisfied by source caps */
+#define RDO_USB_COMM            BIT(25) /* USB communications capable */
+#define RDO_NO_SUSPEND          BIT(24) /* USB Suspend not supported */
+
+#define RDO_PWR_MASK                    0x3ff
+#define RDO_CURR_MASK                   0x3ff
+
+#define RDO_FIXED_OP_CURR_SHIFT         10
+#define RDO_FIXED_MAX_CURR_SHIFT        0
+
+#define RDO_OBJ(idx) (((idx) & RDO_OBJ_POS_MASK) << RDO_OBJ_POS_SHIFT)
+
+#define PDO_FIXED_OP_CURR(ma) ((((ma) / 10) & RDO_CURR_MASK) << RDO_FIXED_OP_CURR_SHIFT)
+#define PDO_FIXED_MAX_CURR(ma) ((((ma) / 10) & RDO_CURR_MASK) << RDO_FIXED_MAX_CURR_SHIFT)
+
+#define RDO_FIXED(idx, op_ma, max_ma, flags)                    \
+	(RDO_OBJ(idx) | (flags) |                               \
+	 PDO_FIXED_OP_CURR(op_ma) | PDO_FIXED_MAX_CURR(max_ma))
+
+#define RDO_BATT_OP_PWR_SHIFT           10      /* 250mW units */
+#define RDO_BATT_MAX_PWR_SHIFT          0       /* 250mW units */
+
+#define RDO_BATT_OP_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_OP_PWR_SHIFT)
+#define RDO_BATT_MAX_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_MAX_PWR_SHIFT)
+
+#define RDO_BATT(idx, op_mw, max_mw, flags)                     \
+	(RDO_OBJ(idx) | (flags) |                               \
+	 RDO_BATT_OP_PWR(op_mw) | RDO_BATT_MAX_PWR(max_mw))
+
+static inline unsigned int rdo_index(u32 rdo)
+{
+	return (rdo >> RDO_OBJ_POS_SHIFT) & RDO_OBJ_POS_MASK;
+}
+
+static inline unsigned int rdo_op_current(u32 rdo)
+{
+	return ((rdo >> RDO_FIXED_OP_CURR_SHIFT) & RDO_CURR_MASK) * 10;
+}
+
+static inline unsigned int rdo_max_current(u32 rdo)
+{
+	return ((rdo >> RDO_FIXED_MAX_CURR_SHIFT) &
+			RDO_CURR_MASK) * 10;
+}
+
+static inline unsigned int rdo_op_power(u32 rdo)
+{
+	return ((rdo >> RDO_BATT_OP_PWR_SHIFT) & RDO_PWR_MASK) * 250;
+}
+
+static inline unsigned int rdo_max_power(u32 rdo)
+{
+	return ((rdo >> RDO_BATT_MAX_PWR_SHIFT) & RDO_PWR_MASK) * 250;
+}
+
+#define TCPC_LOG_BUFFER_SIZE 1024
+
+struct tcpc_port;
+
+typedef void (*ss_mux_sel)(enum typec_cc_polarity pol);
+typedef int (*ext_pd_switch_setup)(struct tcpc_port *port_p);
+
+enum tcpc_port_type {
+	TYPEC_PORT_DFP,
+	TYPEC_PORT_UFP,
+	TYPEC_PORT_DRP,
+};
+
+struct tcpc_port_config {
+	uint8_t i2c_bus;
+	uint8_t addr;
+	enum tcpc_port_type port_type;
+	uint32_t max_snk_mv;
+	uint32_t max_snk_ma;
+	uint32_t max_snk_mw;
+	uint32_t op_snk_mv;
+	bool disable_pd;
+	ext_pd_switch_setup switch_setup_func;
+};
+
+struct tcpc_port {
+	struct tcpc_port_config cfg;
+	struct udevice *i2c_dev;
+	ss_mux_sel ss_sel_func;
+	enum pd_sink_state pd_state;
+	uint32_t tx_msg_id;
+	uint32_t log_size;
+	char logbuffer[TCPC_LOG_BUFFER_SIZE];
+	char *log_p;
+	char *log_print;
+};
+
+int tcpc_set_cc_to_source(struct tcpc_port *port);
+int tcpc_set_cc_to_sink(struct tcpc_port *port);
+int tcpc_set_plug_orientation(struct tcpc_port *port, enum typec_cc_polarity polarity);
+int tcpc_get_cc_status(struct tcpc_port *port, enum typec_cc_polarity *polarity, enum typec_cc_state *state);
+int tcpc_clear_alert(struct tcpc_port *port, uint16_t clear_mask);
+int tcpc_send_command(struct tcpc_port *port, uint8_t command);
+int tcpc_polling_reg(struct tcpc_port *port, uint8_t reg,
+	uint8_t reg_width, uint16_t mask, uint16_t value, ulong timeout_ms);
+int tcpc_setup_dfp_mode(struct tcpc_port *port);
+int tcpc_setup_ufp_mode(struct tcpc_port *port);
+int tcpc_disable_src_vbus(struct tcpc_port *port);
+int tcpc_init(struct tcpc_port *port, struct tcpc_port_config config, ss_mux_sel ss_sel_func);
+bool tcpc_pd_sink_check_charging(struct tcpc_port *port);
+void tcpc_print_log(struct tcpc_port *port);
+
+#ifdef CONFIG_SPL_BUILD
+int tcpc_setup_ufp_mode(struct tcpc_port *port)
+{
+	return 0;
+}
+int tcpc_setup_dfp_mode(struct tcpc_port *port)
+{
+	return 0;
+}
+
+int tcpc_disable_src_vbus(struct tcpc_port *port)
+{
+	return 0;
+}
+#endif
+#endif /* __TCPCI_H */
diff --git a/board/freescale/imx8dxl_evk/Kconfig b/board/freescale/imx8dxl_evk/Kconfig
new file mode 100644
index 00000000000..b5009f19ca5
--- /dev/null
+++ b/board/freescale/imx8dxl_evk/Kconfig
@@ -0,0 +1,17 @@
+if  TARGET_IMX8DXL_EVK || TARGET_IMX8DXL_DDR3_EVK
+
+config SYS_BOARD
+	default "imx8dxl_evk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx8dxl_evk"
+
+config IMX_CONFIG
+	default "board/freescale/imx8dxl_evk/imximage.cfg"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/imx8dxl_evk/Makefile b/board/freescale/imx8dxl_evk/Makefile
new file mode 100644
index 00000000000..f031c5fb500
--- /dev/null
+++ b/board/freescale/imx8dxl_evk/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += imx8dxl_evk.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/freescale/imx8dxl_evk/imx8dxl_evk.c b/board/freescale/imx8dxl_evk/imx8dxl_evk.c
new file mode 100644
index 00000000000..55f1e1ee777
--- /dev/null
+++ b/board/freescale/imx8dxl_evk/imx8dxl_evk.c
@@ -0,0 +1,345 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <fsl_esdhc_imx.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/snvs_security_sc.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <usb.h>
+#include "../common/tcpc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ENET_INPUT_PAD_CTRL	((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_NORMAL_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define GPMI_NAND_PAD_CTRL	 ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) \
+				  | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart0_pads[] = {
+	SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
+}
+
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_NAND_MXS
+static iomux_cfg_t gpmi_nand_pads[] = {
+	SC_P_EMMC0_DATA0 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA1 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA2 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA3 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA4 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA5 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA6 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA7 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_STROBE | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_RESET_B | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_CLK | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_CMD | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+
+	SC_P_USDHC1_RESET_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_USDHC1_WP | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_USDHC1_VSELECT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+
+};
+
+static void setup_iomux_gpmi_nand(void)
+{
+	imx8_iomux_setup_multiple_pads(gpmi_nand_pads, ARRAY_SIZE(gpmi_nand_pads));
+}
+
+static void imx8dxl_gpmi_nand_initialize(void)
+{
+	int ret;
+
+	ret = sc_pm_set_resource_power_mode(-1, SC_R_NAND, SC_PM_PW_MODE_ON);
+	if (ret)
+		return;
+
+	init_clk_gpmi_nand();
+	setup_iomux_gpmi_nand();
+}
+#endif
+#endif
+
+
+int board_early_init_f(void)
+{
+	sc_pm_clock_rate_t rate = SC_80MHZ;
+	int ret;
+
+	/* Set UART0 clock root to 80 MHz */
+	ret = sc_pm_setup_uart(SC_R_UART_0, rate);
+	if (ret)
+		return ret;
+
+	setup_iomux_uart();
+
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_NAND_MXS
+	imx8dxl_gpmi_nand_initialize();
+#endif
+#endif
+	return 0;
+}
+
+#if CONFIG_IS_ENABLED(DM_GPIO)
+static void board_gpio_init(void)
+{
+#if defined(CONFIG_DM_VIDEO)
+	int ret;
+	struct gpio_desc desc;
+
+	/* M40_DEBUG_UART_SEL */
+	ret = dm_gpio_lookup_name("gpio@20_3", &desc);
+	if (ret) {
+		printf("%s lookup gpio@20_3 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "M40_DEBUG_UART_SEL");
+	if (ret) {
+		printf("%s request M40_DEBUG_UART_SEL failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW);
+
+	/* SPI0_SEL */
+	ret = dm_gpio_lookup_name("gpio@20_8", &desc);
+	if (ret) {
+		printf("%s lookup gpio@20_8 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "SPI0_SEL");
+	if (ret) {
+		printf("%s request SPI0_SEL failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW);
+
+	/* UART1_SEL */
+	ret = dm_gpio_lookup_name("gpio@20_6", &desc);
+	if (ret) {
+		printf("%s lookup gpio@20_6 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "UART1_SEL");
+	if (ret) {
+		printf("%s request UART1_SEL failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW);
+
+	/* MUX3_EN */
+	ret = dm_gpio_lookup_name("gpio@21_8", &desc);
+	if (ret) {
+		printf("%s lookup gpio@21_8 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "MUX3_EN");
+	if (ret) {
+		printf("%s request MUX3_EN failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW);
+
+	/* SPI3_CS0_SEL */
+	ret = dm_gpio_lookup_name("gpio@20_4", &desc);
+	if (ret) {
+		printf("%s lookup gpio@20_4 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "SPI3_CS0_SEL");
+	if (ret) {
+		printf("%s request SPI3_CS0_SEL failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW);
+
+	/* SPI3_SEL */
+	ret = dm_gpio_lookup_name("gpio@20_7", &desc);
+	if (ret) {
+		printf("%s lookup gpio@20_7 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "SPI3_SEL");
+	if (ret) {
+		printf("%s request SPI3_SEL failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW);
+
+	/* BL_CTR */
+	ret = dm_gpio_lookup_name("gpio@20_5", &desc);
+	if (ret) {
+		printf("%s lookup gpio@20_5 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "BL_CTR");
+	if (ret) {
+		printf("%s request BL_CTR failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+#endif
+}
+#else
+static inline void board_gpio_init(void) {}
+#endif
+
+int checkboard(void)
+{
+	puts("Board: iMX8DXL EVK\n");
+
+	print_bootinfo();
+
+	return 0;
+}
+
+#ifdef CONFIG_DWC_ETH_QOS
+static int setup_eqos(void)
+{
+	int err;
+
+	/* set GPR14:12 to b'001: RGMII mode */
+	err = sc_misc_set_control(-1, SC_R_ENET_1, SC_C_INTF_SEL, 0x1);
+	if (err)
+		printf("SC_R_ENET_1 INTF_SEL failed! (error = %d)\n", err);
+
+	/* enable GPR11: CLK_GEN_EN */
+	err = sc_misc_set_control(-1, SC_R_ENET_1, SC_C_CLK_GEN_EN, 1);
+	if (err)
+		printf("SC_R_ENET_1 CLK_GEN_EN failed! (error = %d)\n", err);
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	board_gpio_init();
+#ifdef CONFIG_DWC_ETH_QOS
+	/* clock, phy interface mode */
+	setup_eqos();
+#endif
+
+#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO
+	{
+		int ret = snvs_security_sc_init();
+
+		if (ret)
+			return ret;
+	}
+#endif
+
+	return 0;
+}
+
+void board_quiesce_devices(void)
+{
+	const char *power_on_devices[] = {
+		"dma_lpuart0",
+	};
+
+	imx8_power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices));
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(void)
+{
+	/* TODO */
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return 0;
+}
+#endif
+
+int board_late_init(void)
+{
+	char *fdt_file;
+	bool __maybe_unused m4_booted;
+
+	build_info();
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "EVK");
+	env_set("board_rev", "iMX8DXL");
+#endif
+
+	env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+	env_set("sec_boot", "yes");
+#endif
+
+	fdt_file = env_get("fdt_file");
+	m4_booted = m4_parts_booted();
+
+	if (fdt_file && !strcmp(fdt_file, "undefined")) {
+#if defined(CONFIG_TARGET_IMX8DXL_DDR3_EVK)
+		env_set("fdt_file", "imx8dxl-ddr3l-evk.dtb");
+#else
+		if (m4_booted)
+			env_set("fdt_file", "imx8dxl-evk-rpmsg.dtb");
+		else
+			env_set("fdt_file", "imx8dxl-evk.dtb");
+#endif
+	}
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	return 0;
+}
diff --git a/board/freescale/imx8dxl_evk/imximage.cfg b/board/freescale/imx8dxl_evk/imximage.cfg
new file mode 100644
index 00000000000..e5f2a9e817f
--- /dev/null
+++ b/board/freescale/imx8dxl_evk/imximage.cfg
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ *
+ * Refer doc/README.imx8image for more details about how-to configure
+ * and create imx8image boot image
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM SD 0x400
+/* SoC type IMX8DXL */
+SOC_TYPE IMX8DXL
+/* Append seco container image */
+APPEND ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8dxl-evk-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 spl/u-boot-spl.bin 0x00100000
diff --git a/board/freescale/imx8dxl_evk/spl.c b/board/freescale/imx8dxl_evk/spl.c
new file mode 100644
index 00000000000..cb78ecf512a
--- /dev/null
+++ b/board/freescale/imx8dxl_evk/spl.c
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <bootm.h>
+#include <asm/mach-imx/boot_mode.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	switch (boot_dev_spl) {
+	case MMC1_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD2_BOOT:
+#ifdef CONFIG_TARGET_IMX8DXL_DDR3_EVK
+		return BOOT_DEVICE_MMC1;
+#else
+		return BOOT_DEVICE_MMC2_2;
+#endif
+	case FLEXSPI_BOOT:
+		return BOOT_DEVICE_SPI;
+	case NAND_BOOT:
+		return BOOT_DEVICE_NAND;
+	case USB_BOOT:
+		return BOOT_DEVICE_BOARD;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+}
+
+void spl_board_init(void)
+{
+	struct udevice *dev;
+	
+	uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev);
+
+	uclass_find_first_device(UCLASS_MISC, &dev);
+
+	for (; dev; uclass_find_next_device(&dev)) {
+		if (device_probe(dev))
+			continue;
+	}
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	puts("Normal Boot\n");
+}
+
+void spl_board_prepare_for_boot(void)
+{
+	board_quiesce_devices();
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	arch_cpu_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/board/freescale/imx8dxl_evk/uboot-container.cfg b/board/freescale/imx8dxl_evk/uboot-container.cfg
new file mode 100644
index 00000000000..9ef26331c13
--- /dev/null
+++ b/board/freescale/imx8dxl_evk/uboot-container.cfg
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#define __ASSEMBLY__
+
+/* This file is to create a container image could be loaded by SPL */
+BOOT_FROM SD 0x400
+SOC_TYPE IMX8DXL
+CONTAINER
+IMAGE A35 bl31.bin	0x80000000
+IMAGE A35 u-boot.bin	CONFIG_SYS_TEXT_BASE
diff --git a/board/freescale/imx8dxl_phantom_mek/Kconfig b/board/freescale/imx8dxl_phantom_mek/Kconfig
new file mode 100644
index 00000000000..053096eb299
--- /dev/null
+++ b/board/freescale/imx8dxl_phantom_mek/Kconfig
@@ -0,0 +1,17 @@
+if  TARGET_IMX8DXL_PHANTOM_MEK
+
+config SYS_BOARD
+	default "imx8dxl_phantom_mek"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx8dxl_phantom_mek"
+
+config IMX_CONFIG
+	default "board/freescale/imx8dxl_phantom_mek/imximage.cfg"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/imx8dxl_phantom_mek/Makefile b/board/freescale/imx8dxl_phantom_mek/Makefile
new file mode 100644
index 00000000000..a2684eb555c
--- /dev/null
+++ b/board/freescale/imx8dxl_phantom_mek/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2019 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += imx8dxl_phantom_mek.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/freescale/imx8dxl_phantom_mek/imx8dxl_phantom_mek.c b/board/freescale/imx8dxl_phantom_mek/imx8dxl_phantom_mek.c
new file mode 100644
index 00000000000..7ebb19b9534
--- /dev/null
+++ b/board/freescale/imx8dxl_phantom_mek/imx8dxl_phantom_mek.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <fsl_esdhc_imx.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/snvs_security_sc.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <usb.h>
+#include <power-domain.h>
+#include "../common/tcpc.h"
+#include <asm/arch/lpcg.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ENET_INPUT_PAD_CTRL	((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_NORMAL_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart0_pads[] = {
+	SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
+}
+
+int board_early_init_f(void)
+{
+	sc_pm_clock_rate_t rate = SC_80MHZ;
+	int ret;
+
+	/* Set UART0 clock root to 80 MHz */
+	ret = sc_pm_setup_uart(SC_R_UART_0, rate);
+	if (ret)
+		return ret;
+
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#if CONFIG_IS_ENABLED(DM_GPIO)
+static void board_gpio_init(void)
+{
+}
+#else
+static inline void board_gpio_init(void) {}
+#endif
+
+int checkboard(void)
+{
+	puts("Board: iMX8DXL Phantom MEK\n");
+
+	print_bootinfo();
+
+	return 0;
+}
+
+#ifdef CONFIG_USB
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	if (index == 0) {
+		if (init == USB_INIT_DEVICE) {
+#if !CONFIG_IS_ENABLED(DM_USB_GADGET) && !CONFIG_IS_ENABLED(DM_USB)
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0, SC_PM_PW_MODE_ON);
+			if (ret)
+				printf("conn_usb0 Power up failed! (error = %d)\n", ret);
+
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0_PHY, SC_PM_PW_MODE_ON);
+			if (ret)
+				printf("conn_usb0_phy Power up failed! (error = %d)\n", ret);
+#endif
+		}
+	}
+	return ret;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	if (index == 0) {
+		if (init == USB_INIT_DEVICE) {
+#if !CONFIG_IS_ENABLED(DM_USB_GADGET) && !CONFIG_IS_ENABLED(DM_USB)
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0, SC_PM_PW_MODE_OFF);
+			if (ret)
+				printf("conn_usb0 Power down failed! (error = %d)\n", ret);
+
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0_PHY, SC_PM_PW_MODE_OFF);
+			if (ret)
+				printf("conn_usb0_phy Power down failed! (error = %d)\n", ret);
+#endif
+		}
+	}
+	return ret;
+}
+#endif
+
+int board_init(void)
+{
+	board_gpio_init();
+
+#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO
+	{
+		int ret = snvs_security_sc_init();
+
+		if (ret)
+			return ret;
+	}
+#endif
+
+	return 0;
+}
+
+void board_quiesce_devices(void)
+{
+	const char *power_on_devices[] = {
+		"dma_lpuart0",
+
+		/* HIFI DSP boot */
+		"audio_sai0",
+		"audio_ocram",
+	};
+
+	imx8_power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices));
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(void)
+{
+	/* TODO */
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return 0;
+}
+#endif
+
+int board_late_init(void)
+{
+	char *fdt_file;
+	bool m4_booted;
+
+	build_info();
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "MEK");
+	env_set("board_rev", "iMX8DXL Phantom");
+#endif
+
+	env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+	env_set("sec_boot", "yes");
+#endif
+
+	fdt_file = env_get("fdt_file");
+	m4_booted = m4_parts_booted();
+
+	if (fdt_file && !strcmp(fdt_file, "undefined")) {
+		if (m4_booted)
+			env_set("fdt_file", "imx8dxl-phantom-mek-rpmsg.dtb");
+		else
+			env_set("fdt_file", "imx8dxl-phantom-mek.dtb");
+	}
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	return 0;
+}
diff --git a/board/freescale/imx8dxl_phantom_mek/imximage.cfg b/board/freescale/imx8dxl_phantom_mek/imximage.cfg
new file mode 100644
index 00000000000..c203eace229
--- /dev/null
+++ b/board/freescale/imx8dxl_phantom_mek/imximage.cfg
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ *
+ * Refer doc/README.imx8image for more details about how-to configure
+ * and create imx8image boot image
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM SD 0x400
+/* SoC type IMX8QX */
+SOC_TYPE IMX8QX
+/* Append seco container image */
+APPEND ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qx-mek-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 spl/u-boot-spl.bin 0x00100000
diff --git a/board/freescale/imx8dxl_phantom_mek/spl.c b/board/freescale/imx8dxl_phantom_mek/spl.c
new file mode 100644
index 00000000000..278d4f1baa7
--- /dev/null
+++ b/board/freescale/imx8dxl_phantom_mek/spl.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <bootm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_board_init(void)
+{
+	struct udevice *dev;
+
+	uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev);
+
+	uclass_find_first_device(UCLASS_MISC, &dev);
+
+	for (; dev; uclass_find_next_device(&dev)) {
+		if (device_probe(dev))
+			continue;
+	}
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	puts("Normal Boot\n");
+}
+
+void spl_board_prepare_for_boot(void)
+{
+	board_quiesce_devices();
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	arch_cpu_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/board/freescale/imx8dxl_phantom_mek/uboot-container.cfg b/board/freescale/imx8dxl_phantom_mek/uboot-container.cfg
new file mode 100644
index 00000000000..81658118185
--- /dev/null
+++ b/board/freescale/imx8dxl_phantom_mek/uboot-container.cfg
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#define __ASSEMBLY__
+
+/* This file is to create a container image could be loaded by SPL */
+BOOT_FROM SD 0x400
+SOC_TYPE IMX8QX
+CONTAINER
+IMAGE A35 bl31.bin	0x80000000
+IMAGE A35 u-boot.bin	CONFIG_SYS_TEXT_BASE
diff --git a/board/freescale/imx8mm_ab2/Kconfig b/board/freescale/imx8mm_ab2/Kconfig
new file mode 100644
index 00000000000..dbc7cbbebfc
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/Kconfig
@@ -0,0 +1,29 @@
+if TARGET_IMX8MM_AB2 || TARGET_IMX8MM_DDR4_AB2 || \
+	TARGET_IMX8MN_AB2 || TARGET_IMX8MN_DDR4_AB2 || \
+	TARGET_IMX8MN_DDR3L_AB2
+
+config SYS_BOARD
+	default "imx8mm_ab2"
+
+config SYS_VENDOR
+	default "freescale"
+
+if IMX8MM
+config SYS_CONFIG_NAME
+	default "imx8mm_ab2"
+
+config IMX_CONFIG
+	default "board/freescale/imx8mm_ab2/imximage-8mm.cfg"
+endif
+
+if IMX8MN
+config SYS_CONFIG_NAME
+	default "imx8mn_ab2"
+
+config IMX_CONFIG
+	default "board/freescale/imx8mm_ab2/imximage-8mn.cfg"
+endif
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/imx8mm_ab2/MAINTAINERS b/board/freescale/imx8mm_ab2/MAINTAINERS
new file mode 100644
index 00000000000..a8b847bcd28
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/MAINTAINERS
@@ -0,0 +1,8 @@
+i.MX8M Mini and Nano Audio Board 2.0
+M:	Adrian Alonso <adrian.alonso@nxp.com>
+S:	Maintained
+F:	board/freescale/imx8mm_ab2/
+F:	include/configs/imx8mm_ab2.h
+F:	include/configs/imx8mn_ab2.h
+F:	configs/imx8mm_ab2_defconfig
+F:	configs/imx8mn_ab2_defconfig
diff --git a/board/freescale/imx8mm_ab2/Makefile b/board/freescale/imx8mm_ab2/Makefile
new file mode 100644
index 00000000000..0a540e2a1c6
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/Makefile
@@ -0,0 +1,21 @@
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mm_ab2.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_TARGET_IMX8MM_AB2) += lpddr4_imx8mm_som.o
+obj-$(CONFIG_TARGET_IMX8MM_DDR4_AB2) += ddr4_imx8mm_som.o
+ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
+obj-$(CONFIG_TARGET_IMX8MN_AB2) += lpddr4_imx8mn_som_ld.o
+obj-$(CONFIG_TARGET_IMX8MN_DDR4_AB2) += ddr4_imx8mn_som_ld.o
+else
+obj-$(CONFIG_TARGET_IMX8MN_AB2) += lpddr4_imx8mn_som.o
+obj-$(CONFIG_TARGET_IMX8MN_DDR4_AB2) += ddr4_imx8mn_som.o
+obj-$(CONFIG_TARGET_IMX8MN_DDR3L_AB2) += ddr3l_imx8mn_som.o
+endif
+endif
diff --git a/board/freescale/imx8mm_ab2/ddr3l_imx8mn_som.c b/board/freescale/imx8mm_ab2/ddr3l_imx8mn_som.c
new file mode 100644
index 00000000000..14d18cb491f
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/ddr3l_imx8mn_som.c
@@ -0,0 +1,944 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga
+ * For imx_v2019.04_5.4.x and above version:
+ * please replace #include <asm/arch/imx8m_ddr.h> with #include <asm/arch/ddr.h>
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x20 },
+	{ 0x3d400000, 0xa1040001 },
+	{ 0x3d400064, 0x61008c },
+	{ 0x3d4000d0, 0xc00200c5 },
+	{ 0x3d4000d4, 0x1000b },
+	{ 0x3d4000dc, 0x1d700004 },
+	{ 0x3d4000e0, 0x180000 },
+	{ 0x3d4000e4, 0x90000 },
+	{ 0x3d4000f0, 0x0 },
+	{ 0x3d4000f4, 0xee5 },
+	{ 0x3d400100, 0xc101b0e },
+	{ 0x3d400104, 0x30314 },
+	{ 0x3d400108, 0x4060509 },
+	{ 0x3d40010c, 0x2006 },
+	{ 0x3d400110, 0x6020306 },
+	{ 0x3d400114, 0x4040302 },
+	{ 0x3d400120, 0x909 },
+	{ 0x3d400180, 0x40800020 },
+	{ 0x3d400184, 0xc350 },
+	{ 0x3d400190, 0x3868203 },
+	{ 0x3d400194, 0x20303 },
+	{ 0x3d4001b4, 0x603 },
+	{ 0x3d400198, 0x7000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001a0, 0x400018 },
+	{ 0x3d4001a4, 0x5003c },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001c4, 0x0 },
+	{ 0x3d400200, 0x1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400208, 0x0 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d400240, 0x600060c },
+	{ 0x3d400244, 0x1323 },
+	{ 0x3d400400, 0x100 },
+	{ 0x3d400250, 0x7ab50b07 },
+	{ 0x3d400254, 0x22 },
+	{ 0x3d40025c, 0x7b00665e },
+	{ 0x3d400264, 0xb0000040 },
+	{ 0x3d40026c, 0x50000a0c },
+	{ 0x3d400300, 0x17 },
+	{ 0x3d40036c, 0x10000 },
+	{ 0x3d400404, 0x3051 },
+	{ 0x3d400408, 0x61d2 },
+	{ 0x3d400494, 0xe00 },
+	{ 0x3d400498, 0x7ff },
+	{ 0x3d40049c, 0xe00 },
+	{ 0x3d4004a0, 0x7ff },
+	{ 0x3d402064, 0x28003b },
+	{ 0x3d4020dc, 0x12200004 },
+	{ 0x3d4020e0, 0x0 },
+	{ 0x3d402100, 0x7090b07 },
+	{ 0x3d402104, 0x20209 },
+	{ 0x3d402108, 0x3030407 },
+	{ 0x3d40210c, 0x2006 },
+	{ 0x3d402110, 0x3020203 },
+	{ 0x3d402114, 0x3030202 },
+	{ 0x3d402120, 0x909 },
+	{ 0x3d402180, 0x40800020 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x20303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d402240, 0x6000604 },
+	{ 0x3d4020f4, 0xee5 },
+	{ 0x3d400028, 0x1 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x1005f, 0x3ff },
+	{ 0x1015f, 0x3ff },
+	{ 0x1105f, 0x3ff },
+	{ 0x1115f, 0x3ff },
+	{ 0x11005f, 0x3ff },
+	{ 0x11015f, 0x3ff },
+	{ 0x11105f, 0x3ff },
+	{ 0x11115f, 0x3ff },
+	{ 0x55, 0x3ff },
+	{ 0x1055, 0x3ff },
+	{ 0x2055, 0x3ff },
+	{ 0x3055, 0x3ff },
+	{ 0x4055, 0xff },
+	{ 0x5055, 0xff },
+	{ 0x6055, 0x3ff },
+	{ 0x7055, 0x3ff },
+	{ 0x8055, 0x3ff },
+	{ 0x9055, 0x3ff },
+	{ 0x200c5, 0xb },
+	{ 0x1200c5, 0x7 },
+	{ 0x2002e, 0x1 },
+	{ 0x12002e, 0x1 },
+	{ 0x20024, 0x0 },
+	{ 0x2003a, 0x0 },
+	{ 0x120024, 0x0 },
+	{ 0x2003a, 0x0 },
+	{ 0x20056, 0xa },
+	{ 0x120056, 0xa },
+	{ 0x1004d, 0x208 },
+	{ 0x1014d, 0x208 },
+	{ 0x1104d, 0x208 },
+	{ 0x1114d, 0x208 },
+	{ 0x11004d, 0x208 },
+	{ 0x11014d, 0x208 },
+	{ 0x11104d, 0x208 },
+	{ 0x11114d, 0x208 },
+	{ 0x10049, 0xe38 },
+	{ 0x10149, 0xe38 },
+	{ 0x11049, 0xe38 },
+	{ 0x11149, 0xe38 },
+	{ 0x110049, 0xe38 },
+	{ 0x110149, 0xe38 },
+	{ 0x111049, 0xe38 },
+	{ 0x111149, 0xe38 },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x1 },
+	{ 0x20075, 0x0 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x190 },
+	{ 0x120008, 0xa7 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x32c },
+	{ 0x10043, 0x581 },
+	{ 0x10143, 0x581 },
+	{ 0x11043, 0x581 },
+	{ 0x11143, 0x581 },
+	{ 0x1200b2, 0x32c },
+	{ 0x110043, 0x581 },
+	{ 0x110143, 0x581 },
+	{ 0x111043, 0x581 },
+	{ 0x111143, 0x581 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x20019, 0x5 },
+	{ 0x120019, 0x5 },
+	{ 0x200f0, 0x5555 },
+	{ 0x200f1, 0x5555 },
+	{ 0x200f2, 0x5555 },
+	{ 0x200f3, 0x5555 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0x5555 },
+	{ 0x200f6, 0x5555 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{0x0200b2,0x0},
+	{0x1200b2,0x0},
+	{0x2200b2,0x0},
+	{0x0200cb,0x0},
+	{0x010043,0x0},
+	{0x110043,0x0},
+	{0x210043,0x0},
+	{0x010143,0x0},
+	{0x110143,0x0},
+	{0x210143,0x0},
+	{0x011043,0x0},
+	{0x111043,0x0},
+	{0x211043,0x0},
+	{0x011143,0x0},
+	{0x111143,0x0},
+	{0x211143,0x0},
+	{0x000080,0x0},
+	{0x100080,0x0},
+	{0x200080,0x0},
+	{0x001080,0x0},
+	{0x101080,0x0},
+	{0x201080,0x0},
+	{0x002080,0x0},
+	{0x102080,0x0},
+	{0x202080,0x0},
+	{0x003080,0x0},
+	{0x103080,0x0},
+	{0x203080,0x0},
+	{0x004080,0x0},
+	{0x104080,0x0},
+	{0x204080,0x0},
+	{0x005080,0x0},
+	{0x105080,0x0},
+	{0x205080,0x0},
+	{0x006080,0x0},
+	{0x106080,0x0},
+	{0x206080,0x0},
+	{0x007080,0x0},
+	{0x107080,0x0},
+	{0x207080,0x0},
+	{0x008080,0x0},
+	{0x108080,0x0},
+	{0x208080,0x0},
+	{0x009080,0x0},
+	{0x109080,0x0},
+	{0x209080,0x0},
+	{0x010080,0x0},
+	{0x110080,0x0},
+	{0x210080,0x0},
+	{0x010180,0x0},
+	{0x110180,0x0},
+	{0x210180,0x0},
+	{0x010081,0x0},
+	{0x110081,0x0},
+	{0x210081,0x0},
+	{0x010181,0x0},
+	{0x110181,0x0},
+	{0x210181,0x0},
+	{0x010082,0x0},
+	{0x110082,0x0},
+	{0x210082,0x0},
+	{0x010182,0x0},
+	{0x110182,0x0},
+	{0x210182,0x0},
+	{0x010083,0x0},
+	{0x110083,0x0},
+	{0x210083,0x0},
+	{0x010183,0x0},
+	{0x110183,0x0},
+	{0x210183,0x0},
+	{0x011080,0x0},
+	{0x111080,0x0},
+	{0x211080,0x0},
+	{0x011180,0x0},
+	{0x111180,0x0},
+	{0x211180,0x0},
+	{0x011081,0x0},
+	{0x111081,0x0},
+	{0x211081,0x0},
+	{0x011181,0x0},
+	{0x111181,0x0},
+	{0x211181,0x0},
+	{0x011082,0x0},
+	{0x111082,0x0},
+	{0x211082,0x0},
+	{0x011182,0x0},
+	{0x111182,0x0},
+	{0x211182,0x0},
+	{0x011083,0x0},
+	{0x111083,0x0},
+	{0x211083,0x0},
+	{0x011183,0x0},
+	{0x111183,0x0},
+	{0x211183,0x0},
+	{0x0100d0,0x0},
+	{0x1100d0,0x0},
+	{0x2100d0,0x0},
+	{0x0101d0,0x0},
+	{0x1101d0,0x0},
+	{0x2101d0,0x0},
+	{0x0100d1,0x0},
+	{0x1100d1,0x0},
+	{0x2100d1,0x0},
+	{0x0101d1,0x0},
+	{0x1101d1,0x0},
+	{0x2101d1,0x0},
+	{0x0100d2,0x0},
+	{0x1100d2,0x0},
+	{0x2100d2,0x0},
+	{0x0101d2,0x0},
+	{0x1101d2,0x0},
+	{0x2101d2,0x0},
+	{0x0100d3,0x0},
+	{0x1100d3,0x0},
+	{0x2100d3,0x0},
+	{0x0101d3,0x0},
+	{0x1101d3,0x0},
+	{0x2101d3,0x0},
+	{0x0110d0,0x0},
+	{0x1110d0,0x0},
+	{0x2110d0,0x0},
+	{0x0111d0,0x0},
+	{0x1111d0,0x0},
+	{0x2111d0,0x0},
+	{0x0110d1,0x0},
+	{0x1110d1,0x0},
+	{0x2110d1,0x0},
+	{0x0111d1,0x0},
+	{0x1111d1,0x0},
+	{0x2111d1,0x0},
+	{0x0110d2,0x0},
+	{0x1110d2,0x0},
+	{0x2110d2,0x0},
+	{0x0111d2,0x0},
+	{0x1111d2,0x0},
+	{0x2111d2,0x0},
+	{0x0110d3,0x0},
+	{0x1110d3,0x0},
+	{0x2110d3,0x0},
+	{0x0111d3,0x0},
+	{0x1111d3,0x0},
+	{0x2111d3,0x0},
+	{0x010068,0x0},
+	{0x010168,0x0},
+	{0x010268,0x0},
+	{0x010368,0x0},
+	{0x010468,0x0},
+	{0x010568,0x0},
+	{0x010668,0x0},
+	{0x010768,0x0},
+	{0x010868,0x0},
+	{0x010069,0x0},
+	{0x010169,0x0},
+	{0x010269,0x0},
+	{0x010369,0x0},
+	{0x010469,0x0},
+	{0x010569,0x0},
+	{0x010669,0x0},
+	{0x010769,0x0},
+	{0x010869,0x0},
+	{0x01006a,0x0},
+	{0x01016a,0x0},
+	{0x01026a,0x0},
+	{0x01036a,0x0},
+	{0x01046a,0x0},
+	{0x01056a,0x0},
+	{0x01066a,0x0},
+	{0x01076a,0x0},
+	{0x01086a,0x0},
+	{0x01006b,0x0},
+	{0x01016b,0x0},
+	{0x01026b,0x0},
+	{0x01036b,0x0},
+	{0x01046b,0x0},
+	{0x01056b,0x0},
+	{0x01066b,0x0},
+	{0x01076b,0x0},
+	{0x01086b,0x0},
+	{0x011068,0x0},
+	{0x011168,0x0},
+	{0x011268,0x0},
+	{0x011368,0x0},
+	{0x011468,0x0},
+	{0x011568,0x0},
+	{0x011668,0x0},
+	{0x011768,0x0},
+	{0x011868,0x0},
+	{0x011069,0x0},
+	{0x011169,0x0},
+	{0x011269,0x0},
+	{0x011369,0x0},
+	{0x011469,0x0},
+	{0x011569,0x0},
+	{0x011669,0x0},
+	{0x011769,0x0},
+	{0x011869,0x0},
+	{0x01106a,0x0},
+	{0x01116a,0x0},
+	{0x01126a,0x0},
+	{0x01136a,0x0},
+	{0x01146a,0x0},
+	{0x01156a,0x0},
+	{0x01166a,0x0},
+	{0x01176a,0x0},
+	{0x01186a,0x0},
+	{0x01106b,0x0},
+	{0x01116b,0x0},
+	{0x01126b,0x0},
+	{0x01136b,0x0},
+	{0x01146b,0x0},
+	{0x01156b,0x0},
+	{0x01166b,0x0},
+	{0x01176b,0x0},
+	{0x01186b,0x0},
+	{0x01008c,0x0},
+	{0x11008c,0x0},
+	{0x21008c,0x0},
+	{0x01018c,0x0},
+	{0x11018c,0x0},
+	{0x21018c,0x0},
+	{0x01008d,0x0},
+	{0x11008d,0x0},
+	{0x21008d,0x0},
+	{0x01018d,0x0},
+	{0x11018d,0x0},
+	{0x21018d,0x0},
+	{0x01008e,0x0},
+	{0x11008e,0x0},
+	{0x21008e,0x0},
+	{0x01018e,0x0},
+	{0x11018e,0x0},
+	{0x21018e,0x0},
+	{0x01008f,0x0},
+	{0x11008f,0x0},
+	{0x21008f,0x0},
+	{0x01018f,0x0},
+	{0x11018f,0x0},
+	{0x21018f,0x0},
+	{0x01108c,0x0},
+	{0x11108c,0x0},
+	{0x21108c,0x0},
+	{0x01118c,0x0},
+	{0x11118c,0x0},
+	{0x21118c,0x0},
+	{0x01108d,0x0},
+	{0x11108d,0x0},
+	{0x21108d,0x0},
+	{0x01118d,0x0},
+	{0x11118d,0x0},
+	{0x21118d,0x0},
+	{0x01108e,0x0},
+	{0x11108e,0x0},
+	{0x21108e,0x0},
+	{0x01118e,0x0},
+	{0x11118e,0x0},
+	{0x21118e,0x0},
+	{0x01108f,0x0},
+	{0x11108f,0x0},
+	{0x21108f,0x0},
+	{0x01118f,0x0},
+	{0x11118f,0x0},
+	{0x21118f,0x0},
+	{0x0100c0,0x0},
+	{0x1100c0,0x0},
+	{0x2100c0,0x0},
+	{0x0101c0,0x0},
+	{0x1101c0,0x0},
+	{0x2101c0,0x0},
+	{0x0102c0,0x0},
+	{0x1102c0,0x0},
+	{0x2102c0,0x0},
+	{0x0103c0,0x0},
+	{0x1103c0,0x0},
+	{0x2103c0,0x0},
+	{0x0104c0,0x0},
+	{0x1104c0,0x0},
+	{0x2104c0,0x0},
+	{0x0105c0,0x0},
+	{0x1105c0,0x0},
+	{0x2105c0,0x0},
+	{0x0106c0,0x0},
+	{0x1106c0,0x0},
+	{0x2106c0,0x0},
+	{0x0107c0,0x0},
+	{0x1107c0,0x0},
+	{0x2107c0,0x0},
+	{0x0108c0,0x0},
+	{0x1108c0,0x0},
+	{0x2108c0,0x0},
+	{0x0100c1,0x0},
+	{0x1100c1,0x0},
+	{0x2100c1,0x0},
+	{0x0101c1,0x0},
+	{0x1101c1,0x0},
+	{0x2101c1,0x0},
+	{0x0102c1,0x0},
+	{0x1102c1,0x0},
+	{0x2102c1,0x0},
+	{0x0103c1,0x0},
+	{0x1103c1,0x0},
+	{0x2103c1,0x0},
+	{0x0104c1,0x0},
+	{0x1104c1,0x0},
+	{0x2104c1,0x0},
+	{0x0105c1,0x0},
+	{0x1105c1,0x0},
+	{0x2105c1,0x0},
+	{0x0106c1,0x0},
+	{0x1106c1,0x0},
+	{0x2106c1,0x0},
+	{0x0107c1,0x0},
+	{0x1107c1,0x0},
+	{0x2107c1,0x0},
+	{0x0108c1,0x0},
+	{0x1108c1,0x0},
+	{0x2108c1,0x0},
+	{0x0100c2,0x0},
+	{0x1100c2,0x0},
+	{0x2100c2,0x0},
+	{0x0101c2,0x0},
+	{0x1101c2,0x0},
+	{0x2101c2,0x0},
+	{0x0102c2,0x0},
+	{0x1102c2,0x0},
+	{0x2102c2,0x0},
+	{0x0103c2,0x0},
+	{0x1103c2,0x0},
+	{0x2103c2,0x0},
+	{0x0104c2,0x0},
+	{0x1104c2,0x0},
+	{0x2104c2,0x0},
+	{0x0105c2,0x0},
+	{0x1105c2,0x0},
+	{0x2105c2,0x0},
+	{0x0106c2,0x0},
+	{0x1106c2,0x0},
+	{0x2106c2,0x0},
+	{0x0107c2,0x0},
+	{0x1107c2,0x0},
+	{0x2107c2,0x0},
+	{0x0108c2,0x0},
+	{0x1108c2,0x0},
+	{0x2108c2,0x0},
+	{0x0100c3,0x0},
+	{0x1100c3,0x0},
+	{0x2100c3,0x0},
+	{0x0101c3,0x0},
+	{0x1101c3,0x0},
+	{0x2101c3,0x0},
+	{0x0102c3,0x0},
+	{0x1102c3,0x0},
+	{0x2102c3,0x0},
+	{0x0103c3,0x0},
+	{0x1103c3,0x0},
+	{0x2103c3,0x0},
+	{0x0104c3,0x0},
+	{0x1104c3,0x0},
+	{0x2104c3,0x0},
+	{0x0105c3,0x0},
+	{0x1105c3,0x0},
+	{0x2105c3,0x0},
+	{0x0106c3,0x0},
+	{0x1106c3,0x0},
+	{0x2106c3,0x0},
+	{0x0107c3,0x0},
+	{0x1107c3,0x0},
+	{0x2107c3,0x0},
+	{0x0108c3,0x0},
+	{0x1108c3,0x0},
+	{0x2108c3,0x0},
+	{0x0110c0,0x0},
+	{0x1110c0,0x0},
+	{0x2110c0,0x0},
+	{0x0111c0,0x0},
+	{0x1111c0,0x0},
+	{0x2111c0,0x0},
+	{0x0112c0,0x0},
+	{0x1112c0,0x0},
+	{0x2112c0,0x0},
+	{0x0113c0,0x0},
+	{0x1113c0,0x0},
+	{0x2113c0,0x0},
+	{0x0114c0,0x0},
+	{0x1114c0,0x0},
+	{0x2114c0,0x0},
+	{0x0115c0,0x0},
+	{0x1115c0,0x0},
+	{0x2115c0,0x0},
+	{0x0116c0,0x0},
+	{0x1116c0,0x0},
+	{0x2116c0,0x0},
+	{0x0117c0,0x0},
+	{0x1117c0,0x0},
+	{0x2117c0,0x0},
+	{0x0118c0,0x0},
+	{0x1118c0,0x0},
+	{0x2118c0,0x0},
+	{0x0110c1,0x0},
+	{0x1110c1,0x0},
+	{0x2110c1,0x0},
+	{0x0111c1,0x0},
+	{0x1111c1,0x0},
+	{0x2111c1,0x0},
+	{0x0112c1,0x0},
+	{0x1112c1,0x0},
+	{0x2112c1,0x0},
+	{0x0113c1,0x0},
+	{0x1113c1,0x0},
+	{0x2113c1,0x0},
+	{0x0114c1,0x0},
+	{0x1114c1,0x0},
+	{0x2114c1,0x0},
+	{0x0115c1,0x0},
+	{0x1115c1,0x0},
+	{0x2115c1,0x0},
+	{0x0116c1,0x0},
+	{0x1116c1,0x0},
+	{0x2116c1,0x0},
+	{0x0117c1,0x0},
+	{0x1117c1,0x0},
+	{0x2117c1,0x0},
+	{0x0118c1,0x0},
+	{0x1118c1,0x0},
+	{0x2118c1,0x0},
+	{0x0110c2,0x0},
+	{0x1110c2,0x0},
+	{0x2110c2,0x0},
+	{0x0111c2,0x0},
+	{0x1111c2,0x0},
+	{0x2111c2,0x0},
+	{0x0112c2,0x0},
+	{0x1112c2,0x0},
+	{0x2112c2,0x0},
+	{0x0113c2,0x0},
+	{0x1113c2,0x0},
+	{0x2113c2,0x0},
+	{0x0114c2,0x0},
+	{0x1114c2,0x0},
+	{0x2114c2,0x0},
+	{0x0115c2,0x0},
+	{0x1115c2,0x0},
+	{0x2115c2,0x0},
+	{0x0116c2,0x0},
+	{0x1116c2,0x0},
+	{0x2116c2,0x0},
+	{0x0117c2,0x0},
+	{0x1117c2,0x0},
+	{0x2117c2,0x0},
+	{0x0118c2,0x0},
+	{0x1118c2,0x0},
+	{0x2118c2,0x0},
+	{0x0110c3,0x0},
+	{0x1110c3,0x0},
+	{0x2110c3,0x0},
+	{0x0111c3,0x0},
+	{0x1111c3,0x0},
+	{0x2111c3,0x0},
+	{0x0112c3,0x0},
+	{0x1112c3,0x0},
+	{0x2112c3,0x0},
+	{0x0113c3,0x0},
+	{0x1113c3,0x0},
+	{0x2113c3,0x0},
+	{0x0114c3,0x0},
+	{0x1114c3,0x0},
+	{0x2114c3,0x0},
+	{0x0115c3,0x0},
+	{0x1115c3,0x0},
+	{0x2115c3,0x0},
+	{0x0116c3,0x0},
+	{0x1116c3,0x0},
+	{0x2116c3,0x0},
+	{0x0117c3,0x0},
+	{0x1117c3,0x0},
+	{0x2117c3,0x0},
+	{0x0118c3,0x0},
+	{0x1118c3,0x0},
+	{0x2118c3,0x0},
+	{0x010020,0x0},
+	{0x110020,0x0},
+	{0x210020,0x0},
+	{0x011020,0x0},
+	{0x111020,0x0},
+	{0x211020,0x0},
+	{0x02007d,0x0},
+	{0x12007d,0x0},
+	{0x22007d,0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x640 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x283c },
+	{ 0x54006, 0x140 },
+	{ 0x54007, 0x1000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x31f },
+	{ 0x5400c, 0xc8 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x1d70 },
+	{ 0x54030, 0x4 },
+	{ 0x54031, 0x18 },
+	{ 0x5403a, 0x1323 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x1 },
+	{ 0x54003, 0x29c },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x283c },
+	{ 0x54006, 0x140 },
+	{ 0x54007, 0x1000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x21f },
+	{ 0x5400c, 0xc8 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x1220 },
+	{ 0x54030, 0x4 },
+	{ 0x5403a, 0x1323 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x2 },
+	{ 0x90033, 0x10 },
+	{ 0x90034, 0x139 },
+	{ 0x90035, 0xb },
+	{ 0x90036, 0x7c0 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0x44 },
+	{ 0x90039, 0x633 },
+	{ 0x9003a, 0x159 },
+	{ 0x9003b, 0x14f },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x47 },
+	{ 0x9003f, 0x633 },
+	{ 0x90040, 0x149 },
+	{ 0x90041, 0x4f },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x179 },
+	{ 0x90044, 0x8 },
+	{ 0x90045, 0xe0 },
+	{ 0x90046, 0x109 },
+	{ 0x90047, 0x0 },
+	{ 0x90048, 0x7c8 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x1 },
+	{ 0x9004c, 0x8 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x45a },
+	{ 0x9004f, 0x9 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x448 },
+	{ 0x90052, 0x109 },
+	{ 0x90053, 0x40 },
+	{ 0x90054, 0x633 },
+	{ 0x90055, 0x179 },
+	{ 0x90056, 0x1 },
+	{ 0x90057, 0x618 },
+	{ 0x90058, 0x109 },
+	{ 0x90059, 0x40c0 },
+	{ 0x9005a, 0x633 },
+	{ 0x9005b, 0x149 },
+	{ 0x9005c, 0x8 },
+	{ 0x9005d, 0x4 },
+	{ 0x9005e, 0x48 },
+	{ 0x9005f, 0x4040 },
+	{ 0x90060, 0x633 },
+	{ 0x90061, 0x149 },
+	{ 0x90062, 0x0 },
+	{ 0x90063, 0x4 },
+	{ 0x90064, 0x48 },
+	{ 0x90065, 0x40 },
+	{ 0x90066, 0x633 },
+	{ 0x90067, 0x149 },
+	{ 0x90068, 0x10 },
+	{ 0x90069, 0x4 },
+	{ 0x9006a, 0x18 },
+	{ 0x9006b, 0x0 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x78 },
+	{ 0x9006e, 0x549 },
+	{ 0x9006f, 0x633 },
+	{ 0x90070, 0x159 },
+	{ 0x90071, 0xd49 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0x94a },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x441 },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x149 },
+	{ 0x9007a, 0x42 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x1 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x0 },
+	{ 0x90081, 0xe0 },
+	{ 0x90082, 0x109 },
+	{ 0x90083, 0xa },
+	{ 0x90084, 0x10 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0x9 },
+	{ 0x90087, 0x3c0 },
+	{ 0x90088, 0x149 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x159 },
+	{ 0x9008c, 0x18 },
+	{ 0x9008d, 0x10 },
+	{ 0x9008e, 0x109 },
+	{ 0x9008f, 0x0 },
+	{ 0x90090, 0x3c0 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x18 },
+	{ 0x90093, 0x4 },
+	{ 0x90094, 0x48 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x58 },
+	{ 0x90098, 0xb },
+	{ 0x90099, 0x10 },
+	{ 0x9009a, 0x109 },
+	{ 0x9009b, 0x1 },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x5 },
+	{ 0x9009f, 0x7c0 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x0 },
+	{ 0x900a2, 0x8140 },
+	{ 0x900a3, 0x10c },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x8138 },
+	{ 0x900a6, 0x10c },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7c8 },
+	{ 0x900a9, 0x101 },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x448 },
+	{ 0x900ac, 0x109 },
+	{ 0x900ad, 0xf },
+	{ 0x900ae, 0x7c0 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x47 },
+	{ 0x900b1, 0x630 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x8 },
+	{ 0x900b4, 0x618 },
+	{ 0x900b5, 0x109 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0xe0 },
+	{ 0x900b8, 0x109 },
+	{ 0x900b9, 0x0 },
+	{ 0x900ba, 0x7c8 },
+	{ 0x900bb, 0x109 },
+	{ 0x900bc, 0x8 },
+	{ 0x900bd, 0x8140 },
+	{ 0x900be, 0x10c },
+	{ 0x900bf, 0x0 },
+	{ 0x900c0, 0x1 },
+	{ 0x900c1, 0x8 },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x8 },
+	{ 0x900c5, 0x8 },
+	{ 0x900c6, 0x7c8 },
+	{ 0x900c7, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x90026, 0x2b },
+	{ 0x2000b, 0x32 },
+	{ 0x2000c, 0x64 },
+	{ 0x2000d, 0x3e8 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x14 },
+	{ 0x12000c, 0x26 },
+	{ 0x12000d, 0x1a1 },
+	{ 0x12000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0xffff },
+	{ 0x90013, 0x6152 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x0 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 1600mts 1D */
+		.drate = 1600,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 1600, 667, },
+};
+
diff --git a/board/freescale/imx8mm_ab2/ddr4_imx8mm_som.c b/board/freescale/imx8mm_ab2/ddr4_imx8mm_som.c
new file mode 100644
index 00000000000..2f80b9832b2
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/ddr4_imx8mm_som.c
@@ -0,0 +1,1265 @@
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0x81040010 },
+	{ 0x3d400030, 0xaa },
+	{ 0x3d400034, 0x221306 },
+	{ 0x3d400050, 0x210070 },
+	{ 0x3d400054, 0x10008 },
+	{ 0x3d400060, 0x0 },
+	{ 0x3d400064, 0x9200d2 },
+	{ 0x3d4000c0, 0x0 },
+	{ 0x3d4000c4, 0x1000 },
+	{ 0x3d4000d0, 0xc0030126 },
+	{ 0x3d4000d4, 0x770000 },
+	{ 0x3d4000dc, 0x8340105 },
+	{ 0x3d4000e0, 0x180200 },
+	{ 0x3d4000e4, 0x110000 },
+	{ 0x3d4000e8, 0x2000600 },
+	{ 0x3d4000ec, 0x814 },
+	{ 0x3d4000f0, 0x20 },
+	{ 0x3d4000f4, 0xec7 },
+	{ 0x3d400100, 0x11122914 },
+	{ 0x3d400104, 0x4051c },
+	{ 0x3d400108, 0x608050d },
+	{ 0x3d40010c, 0x400c },
+	{ 0x3d400110, 0x8030409 },
+	{ 0x3d400114, 0x6060403 },
+	{ 0x3d40011c, 0x606 },
+	{ 0x3d400120, 0x5050d08 },
+	{ 0x3d400124, 0x2040a },
+	{ 0x3d40012c, 0x1409010e },
+	{ 0x3d400130, 0x8 },
+	{ 0x3d40013c, 0x0 },
+	{ 0x3d400180, 0x1000040 },
+	{ 0x3d400184, 0x493e },
+	{ 0x3d400190, 0x38b8207 },
+	{ 0x3d400194, 0x2020303 },
+	{ 0x3d400198, 0x7f04011 },
+	{ 0x3d40019c, 0xb0 },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0x48005a },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x1 },
+	{ 0x3d4001b4, 0xb07 },
+	{ 0x3d4001b8, 0x4 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x0 },
+	{ 0x3d400200, 0x3f1f },
+	{ 0x3d400204, 0x3f0909 },
+	{ 0x3d400208, 0x700 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf0f },
+	{ 0x3d400220, 0x3f01 },
+	{ 0x3d400240, 0x6000610 },
+	{ 0x3d400244, 0x1323 },
+	{ 0x3d402050, 0x210070 },
+	{ 0x3d402064, 0x40005e },
+	{ 0x3d4020dc, 0x40105 },
+	{ 0x3d4020e0, 0x0 },
+	{ 0x3d4020e8, 0x2000600 },
+	{ 0x3d4020ec, 0x14 },
+	{ 0x3d402100, 0xb081209 },
+	{ 0x3d402104, 0x2020d },
+	{ 0x3d402108, 0x5050309 },
+	{ 0x3d40210c, 0x400c },
+	{ 0x3d402110, 0x4030205 },
+	{ 0x3d402114, 0x3030202 },
+	{ 0x3d40211c, 0x303 },
+	{ 0x3d402120, 0x3030d04 },
+	{ 0x3d402124, 0x20208 },
+	{ 0x3d40212c, 0x1005010e },
+	{ 0x3d402130, 0x8 },
+	{ 0x3d40213c, 0x0 },
+	{ 0x3d402180, 0x1000040 },
+	{ 0x3d402190, 0x3858204 },
+	{ 0x3d402194, 0x2020303 },
+	{ 0x3d4021b4, 0x504 },
+	{ 0x3d4021b8, 0x4 },
+	{ 0x3d402240, 0x6000604 },
+	{ 0x3d4020f4, 0xec7 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x1005f, 0x2fd },
+	{ 0x1015f, 0x2fd },
+	{ 0x1105f, 0x2fd },
+	{ 0x1115f, 0x2fd },
+	{ 0x1205f, 0x2fd },
+	{ 0x1215f, 0x2fd },
+	{ 0x1305f, 0x2fd },
+	{ 0x1315f, 0x2fd },
+	{ 0x11005f, 0x2fd },
+	{ 0x11015f, 0x2fd },
+	{ 0x11105f, 0x2fd },
+	{ 0x11115f, 0x2fd },
+	{ 0x11205f, 0x2fd },
+	{ 0x11215f, 0x2fd },
+	{ 0x11305f, 0x2fd },
+	{ 0x11315f, 0x2fd },
+	{ 0x55, 0x355 },
+	{ 0x1055, 0x355 },
+	{ 0x2055, 0x355 },
+	{ 0x3055, 0x355 },
+	{ 0x4055, 0x55 },
+	{ 0x5055, 0x55 },
+	{ 0x6055, 0x355 },
+	{ 0x7055, 0x355 },
+	{ 0x8055, 0x355 },
+	{ 0x9055, 0x355 },
+	{ 0x200c5, 0xa },
+	{ 0x1200c5, 0x6 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x1 },
+	{ 0x20024, 0x8 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x8 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x6 },
+	{ 0x120056, 0xa },
+	{ 0x1004d, 0x1a },
+	{ 0x1014d, 0x1a },
+	{ 0x1104d, 0x1a },
+	{ 0x1114d, 0x1a },
+	{ 0x1204d, 0x1a },
+	{ 0x1214d, 0x1a },
+	{ 0x1304d, 0x1a },
+	{ 0x1314d, 0x1a },
+	{ 0x11004d, 0x1a },
+	{ 0x11014d, 0x1a },
+	{ 0x11104d, 0x1a },
+	{ 0x11114d, 0x1a },
+	{ 0x11204d, 0x1a },
+	{ 0x11214d, 0x1a },
+	{ 0x11304d, 0x1a },
+	{ 0x11314d, 0x1a },
+	{ 0x10049, 0xe38 },
+	{ 0x10149, 0xe38 },
+	{ 0x11049, 0xe38 },
+	{ 0x11149, 0xe38 },
+	{ 0x12049, 0xe38 },
+	{ 0x12149, 0xe38 },
+	{ 0x13049, 0xe38 },
+	{ 0x13149, 0xe38 },
+	{ 0x110049, 0xe38 },
+	{ 0x110149, 0xe38 },
+	{ 0x111049, 0xe38 },
+	{ 0x111149, 0xe38 },
+	{ 0x112049, 0xe38 },
+	{ 0x112149, 0xe38 },
+	{ 0x113049, 0xe38 },
+	{ 0x113149, 0xe38 },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x5 },
+	{ 0x20075, 0x2 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x258 },
+	{ 0x120008, 0x10a },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x268 },
+	{ 0x10043, 0x5b1 },
+	{ 0x10143, 0x5b1 },
+	{ 0x11043, 0x5b1 },
+	{ 0x11143, 0x5b1 },
+	{ 0x12043, 0x5b1 },
+	{ 0x12143, 0x5b1 },
+	{ 0x13043, 0x5b1 },
+	{ 0x13143, 0x5b1 },
+	{ 0x1200b2, 0x268 },
+	{ 0x110043, 0x5b1 },
+	{ 0x110143, 0x5b1 },
+	{ 0x111043, 0x5b1 },
+	{ 0x111143, 0x5b1 },
+	{ 0x112043, 0x5b1 },
+	{ 0x112143, 0x5b1 },
+	{ 0x113043, 0x5b1 },
+	{ 0x113143, 0x5b1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x20019, 0x5 },
+	{ 0x120019, 0x5 },
+	{ 0x200f0, 0x5555 },
+	{ 0x200f1, 0x5555 },
+	{ 0x200f2, 0x5555 },
+	{ 0x200f3, 0x5555 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0x5555 },
+	{ 0x200f6, 0x5555 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x200c7, 0x21 },
+	{ 0x1200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x1200ca, 0x24 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
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+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x960 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x31f },
+	{ 0x5400c, 0xc8 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x834 },
+	{ 0x54030, 0x105 },
+	{ 0x54031, 0x18 },
+	{ 0x54032, 0x200 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x814 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1323 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x1 },
+	{ 0x54003, 0x42a },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x21f },
+	{ 0x5400c, 0xc8 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x4 },
+	{ 0x54030, 0x105 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x14 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1323 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x960 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x61 },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400e, 0x1f7f },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x834 },
+	{ 0x54030, 0x105 },
+	{ 0x54031, 0x18 },
+	{ 0x54032, 0x200 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x814 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1323 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x2 },
+	{ 0x90033, 0x10 },
+	{ 0x90034, 0x139 },
+	{ 0x90035, 0xf },
+	{ 0x90036, 0x7c0 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0x44 },
+	{ 0x90039, 0x630 },
+	{ 0x9003a, 0x159 },
+	{ 0x9003b, 0x14f },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x47 },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x149 },
+	{ 0x90041, 0x4f },
+	{ 0x90042, 0x630 },
+	{ 0x90043, 0x179 },
+	{ 0x90044, 0x8 },
+	{ 0x90045, 0xe0 },
+	{ 0x90046, 0x109 },
+	{ 0x90047, 0x0 },
+	{ 0x90048, 0x7c8 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x1 },
+	{ 0x9004c, 0x8 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x45a },
+	{ 0x9004f, 0x9 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x448 },
+	{ 0x90052, 0x109 },
+	{ 0x90053, 0x40 },
+	{ 0x90054, 0x630 },
+	{ 0x90055, 0x179 },
+	{ 0x90056, 0x1 },
+	{ 0x90057, 0x618 },
+	{ 0x90058, 0x109 },
+	{ 0x90059, 0x40c0 },
+	{ 0x9005a, 0x630 },
+	{ 0x9005b, 0x149 },
+	{ 0x9005c, 0x8 },
+	{ 0x9005d, 0x4 },
+	{ 0x9005e, 0x48 },
+	{ 0x9005f, 0x4040 },
+	{ 0x90060, 0x630 },
+	{ 0x90061, 0x149 },
+	{ 0x90062, 0x0 },
+	{ 0x90063, 0x4 },
+	{ 0x90064, 0x48 },
+	{ 0x90065, 0x40 },
+	{ 0x90066, 0x630 },
+	{ 0x90067, 0x149 },
+	{ 0x90068, 0x10 },
+	{ 0x90069, 0x4 },
+	{ 0x9006a, 0x18 },
+	{ 0x9006b, 0x0 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x78 },
+	{ 0x9006e, 0x549 },
+	{ 0x9006f, 0x630 },
+	{ 0x90070, 0x159 },
+	{ 0x90071, 0xd49 },
+	{ 0x90072, 0x630 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0x94a },
+	{ 0x90075, 0x630 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x441 },
+	{ 0x90078, 0x630 },
+	{ 0x90079, 0x149 },
+	{ 0x9007a, 0x42 },
+	{ 0x9007b, 0x630 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x1 },
+	{ 0x9007e, 0x630 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x0 },
+	{ 0x90081, 0xe0 },
+	{ 0x90082, 0x109 },
+	{ 0x90083, 0xa },
+	{ 0x90084, 0x10 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0x9 },
+	{ 0x90087, 0x3c0 },
+	{ 0x90088, 0x149 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x159 },
+	{ 0x9008c, 0x18 },
+	{ 0x9008d, 0x10 },
+	{ 0x9008e, 0x109 },
+	{ 0x9008f, 0x0 },
+	{ 0x90090, 0x3c0 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x18 },
+	{ 0x90093, 0x4 },
+	{ 0x90094, 0x48 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x58 },
+	{ 0x90098, 0xa },
+	{ 0x90099, 0x10 },
+	{ 0x9009a, 0x109 },
+	{ 0x9009b, 0x2 },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x7 },
+	{ 0x9009f, 0x7c0 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x10 },
+	{ 0x900a2, 0x10 },
+	{ 0x900a3, 0x109 },
+	{ 0x900a4, 0x0 },
+	{ 0x900a5, 0x8140 },
+	{ 0x900a6, 0x10c },
+	{ 0x900a7, 0x10 },
+	{ 0x900a8, 0x8138 },
+	{ 0x900a9, 0x10c },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x7c8 },
+	{ 0x900ac, 0x101 },
+	{ 0x900ad, 0x8 },
+	{ 0x900ae, 0x0 },
+	{ 0x900af, 0x8 },
+	{ 0x900b0, 0x8 },
+	{ 0x900b1, 0x448 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0xf },
+	{ 0x900b4, 0x7c0 },
+	{ 0x900b5, 0x109 },
+	{ 0x900b6, 0x47 },
+	{ 0x900b7, 0x630 },
+	{ 0x900b8, 0x109 },
+	{ 0x900b9, 0x8 },
+	{ 0x900ba, 0x618 },
+	{ 0x900bb, 0x109 },
+	{ 0x900bc, 0x8 },
+	{ 0x900bd, 0xe0 },
+	{ 0x900be, 0x109 },
+	{ 0x900bf, 0x0 },
+	{ 0x900c0, 0x7c8 },
+	{ 0x900c1, 0x109 },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x8140 },
+	{ 0x900c4, 0x10c },
+	{ 0x900c5, 0x0 },
+	{ 0x900c6, 0x1 },
+	{ 0x900c7, 0x8 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x4 },
+	{ 0x900ca, 0x8 },
+	{ 0x900cb, 0x8 },
+	{ 0x900cc, 0x7c8 },
+	{ 0x900cd, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x90026, 0x2c },
+	{ 0x2000b, 0x4b },
+	{ 0x2000c, 0x96 },
+	{ 0x2000d, 0x5dc },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x21 },
+	{ 0x12000c, 0x42 },
+	{ 0x12000d, 0x29a },
+	{ 0x12000e, 0x21 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0xffff },
+	{ 0x90013, 0x6152 },
+	{ 0xc0080, 0x0 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 2400mts 1D */
+		.drate = 2400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 1066mts 1D */
+		.drate = 1066,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P0 2400mts 2D */
+		.drate = 2400,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 2400, 1066, },
+};
diff --git a/board/freescale/imx8mm_ab2/ddr4_imx8mn_som.c b/board/freescale/imx8mm_ab2/ddr4_imx8mn_som.c
new file mode 100644
index 00000000000..84114a3e8aa
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/ddr4_imx8mn_som.c
@@ -0,0 +1,1057 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400000, 0x81040010 },
+	{ 0x3d400030, 0x20 },
+	{ 0x3d400034, 0x221306 },
+	{ 0x3d400050, 0x210070 },
+	{ 0x3d400054, 0x10008 },
+	{ 0x3d400060, 0x0 },
+	{ 0x3d400064, 0x92014a },
+	{ 0x3d4000c0, 0x0 },
+	{ 0x3d4000c4, 0x1000 },
+	{ 0x3d4000d0, 0xc0030126 },
+	{ 0x3d4000d4, 0x770000 },
+	{ 0x3d4000dc, 0x8340105 },
+	{ 0x3d4000e0, 0x180200 },
+	{ 0x3d4000e4, 0x110000 },
+	{ 0x3d4000e8, 0x2000600 },
+	{ 0x3d4000ec, 0x810 },
+	{ 0x3d4000f0, 0x20 },
+	{ 0x3d4000f4, 0xec7 },
+	{ 0x3d400100, 0x11122914 },
+	{ 0x3d400104, 0x4051c },
+	{ 0x3d400108, 0x608050d },
+	{ 0x3d40010c, 0x400c },
+	{ 0x3d400110, 0x8030409 },
+	{ 0x3d400114, 0x6060403 },
+	{ 0x3d40011c, 0x606 },
+	{ 0x3d400120, 0x7070d0c },
+	{ 0x3d400124, 0x2040a },
+	{ 0x3d40012c, 0x1809010e },
+	{ 0x3d400130, 0x8 },
+	{ 0x3d40013c, 0x0 },
+	{ 0x3d400180, 0x1000040 },
+	{ 0x3d400184, 0x493e },
+	{ 0x3d400190, 0x38b8207 },
+	{ 0x3d400194, 0x2020303 },
+	{ 0x3d400198, 0x7f04011 },
+	{ 0x3d40019c, 0xb0 },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0x48005a },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x1 },
+	{ 0x3d4001b4, 0xb07 },
+	{ 0x3d4001b8, 0x4 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x0 },
+	{ 0x3d400200, 0x3f1f },
+	{ 0x3d400204, 0x3f0909 },
+	{ 0x3d400208, 0x700 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf07 },
+	{ 0x3d400220, 0x3f01 },
+	{ 0x3d400240, 0x6000610 },
+	{ 0x3d400244, 0x1323 },
+	{ 0x3d400400, 0x100 },
+
+	/* performance setting */
+	{ 0x3d400250, 0x00001f05 },
+	{ 0x3d400254, 0x1f },
+	{ 0x3d400264, 0x900003ff },
+	{ 0x3d40026c, 0x200003ff },
+	{ 0x3d400494, 0x01000e00 },
+	{ 0x3d400498, 0x03ff0000 },
+	{ 0x3d40049c, 0x01000e00 },
+	{ 0x3d4004a0, 0x03ff0000 },
+
+	{ 0x3d402050, 0x210070 },
+	{ 0x3d402064, 0x400093 },
+	{ 0x3d4020dc, 0x105 },
+	{ 0x3d4020e0, 0x0 },
+	{ 0x3d4020e8, 0x2000600 },
+	{ 0x3d4020ec, 0x10 },
+	{ 0x3d402100, 0xb081209 },
+	{ 0x3d402104, 0x2020d },
+	{ 0x3d402108, 0x5050309 },
+	{ 0x3d40210c, 0x400c },
+	{ 0x3d402110, 0x5030206 },
+	{ 0x3d402114, 0x3030202 },
+	{ 0x3d40211c, 0x303 },
+	{ 0x3d402120, 0x4040d06 },
+	{ 0x3d402124, 0x20208 },
+	{ 0x3d40212c, 0x1205010e },
+	{ 0x3d402130, 0x8 },
+	{ 0x3d40213c, 0x0 },
+	{ 0x3d402180, 0x1000040 },
+	{ 0x3d402190, 0x3848204 },
+	{ 0x3d402194, 0x2020303 },
+	{ 0x3d4021b4, 0x404 },
+	{ 0x3d4021b8, 0x4 },
+	{ 0x3d402240, 0x6000600 },
+	{ 0x3d4020f4, 0xec7 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x1005f, 0x2fd },
+	{ 0x1015f, 0x2fd },
+	{ 0x1105f, 0x2fd },
+	{ 0x1115f, 0x2fd },
+	{ 0x11005f, 0x2fd },
+	{ 0x11015f, 0x2fd },
+	{ 0x11105f, 0x2fd },
+	{ 0x11115f, 0x2fd },
+	{ 0x55, 0x355 },
+	{ 0x1055, 0x355 },
+	{ 0x2055, 0x355 },
+	{ 0x3055, 0x355 },
+	{ 0x4055, 0x55 },
+	{ 0x5055, 0x55 },
+	{ 0x6055, 0x355 },
+	{ 0x7055, 0x355 },
+	{ 0x8055, 0x355 },
+	{ 0x9055, 0x355 },
+	{ 0x200c5, 0xa },
+	{ 0x1200c5, 0x6 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x1 },
+	{ 0x20024, 0x8 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x8 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x6 },
+	{ 0x120056, 0xa },
+	{ 0x1004d, 0x1a },
+	{ 0x1014d, 0x1a },
+	{ 0x1104d, 0x1a },
+	{ 0x1114d, 0x1a },
+	{ 0x11004d, 0x1a },
+	{ 0x11014d, 0x1a },
+	{ 0x11104d, 0x1a },
+	{ 0x11114d, 0x1a },
+	{ 0x10049, 0xe38 },
+	{ 0x10149, 0xe38 },
+	{ 0x11049, 0xe38 },
+	{ 0x11149, 0xe38 },
+	{ 0x110049, 0xe38 },
+	{ 0x110149, 0xe38 },
+	{ 0x111049, 0xe38 },
+	{ 0x111149, 0xe38 },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x1 },
+	{ 0x20075, 0x2 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x258 },
+	{ 0x120008, 0x10a },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x268 },
+	{ 0x10043, 0x5b1 },
+	{ 0x10143, 0x5b1 },
+	{ 0x11043, 0x5b1 },
+	{ 0x11143, 0x5b1 },
+	{ 0x1200b2, 0x268 },
+	{ 0x110043, 0x5b1 },
+	{ 0x110143, 0x5b1 },
+	{ 0x111043, 0x5b1 },
+	{ 0x111143, 0x5b1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x20019, 0x5 },
+	{ 0x120019, 0x5 },
+	{ 0x200f0, 0x5555 },
+	{ 0x200f1, 0x5555 },
+	{ 0x200f2, 0x5555 },
+	{ 0x200f3, 0x5555 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0x5555 },
+	{ 0x200f6, 0x5555 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x2005b, 0x7529 },
+	{ 0x2005c, 0x0 },
+	{ 0x200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x200cc, 0x1f7 },
+	{ 0x1200c7, 0x21 },
+	{ 0x1200ca, 0x24 },
+	{ 0x1200cc, 0x1f7 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{0x0200b2, 0x0},
+	{0x1200b2, 0x0},
+	{0x2200b2, 0x0},
+	{0x0200cb, 0x0},
+	{0x010043, 0x0},
+	{0x110043, 0x0},
+	{0x210043, 0x0},
+	{0x010143, 0x0},
+	{0x110143, 0x0},
+	{0x210143, 0x0},
+	{0x011043, 0x0},
+	{0x111043, 0x0},
+	{0x211043, 0x0},
+	{0x011143, 0x0},
+	{0x111143, 0x0},
+	{0x211143, 0x0},
+	{0x000080, 0x0},
+	{0x100080, 0x0},
+	{0x200080, 0x0},
+	{0x001080, 0x0},
+	{0x101080, 0x0},
+	{0x201080, 0x0},
+	{0x002080, 0x0},
+	{0x102080, 0x0},
+	{0x202080, 0x0},
+	{0x003080, 0x0},
+	{0x103080, 0x0},
+	{0x203080, 0x0},
+	{0x004080, 0x0},
+	{0x104080, 0x0},
+	{0x204080, 0x0},
+	{0x005080, 0x0},
+	{0x105080, 0x0},
+	{0x205080, 0x0},
+	{0x006080, 0x0},
+	{0x106080, 0x0},
+	{0x206080, 0x0},
+	{0x007080, 0x0},
+	{0x107080, 0x0},
+	{0x207080, 0x0},
+	{0x008080, 0x0},
+	{0x108080, 0x0},
+	{0x208080, 0x0},
+	{0x009080, 0x0},
+	{0x109080, 0x0},
+	{0x209080, 0x0},
+	{0x010080, 0x0},
+	{0x110080, 0x0},
+	{0x210080, 0x0},
+	{0x010180, 0x0},
+	{0x110180, 0x0},
+	{0x210180, 0x0},
+	{0x010081, 0x0},
+	{0x110081, 0x0},
+	{0x210081, 0x0},
+	{0x010181, 0x0},
+	{0x110181, 0x0},
+	{0x210181, 0x0},
+	{0x010082, 0x0},
+	{0x110082, 0x0},
+	{0x210082, 0x0},
+	{0x010182, 0x0},
+	{0x110182, 0x0},
+	{0x210182, 0x0},
+	{0x010083, 0x0},
+	{0x110083, 0x0},
+	{0x210083, 0x0},
+	{0x010183, 0x0},
+	{0x110183, 0x0},
+	{0x210183, 0x0},
+	{0x011080, 0x0},
+	{0x111080, 0x0},
+	{0x211080, 0x0},
+	{0x011180, 0x0},
+	{0x111180, 0x0},
+	{0x211180, 0x0},
+	{0x011081, 0x0},
+	{0x111081, 0x0},
+	{0x211081, 0x0},
+	{0x011181, 0x0},
+	{0x111181, 0x0},
+	{0x211181, 0x0},
+	{0x011082, 0x0},
+	{0x111082, 0x0},
+	{0x211082, 0x0},
+	{0x011182, 0x0},
+	{0x111182, 0x0},
+	{0x211182, 0x0},
+	{0x011083, 0x0},
+	{0x111083, 0x0},
+	{0x211083, 0x0},
+	{0x011183, 0x0},
+	{0x111183, 0x0},
+	{0x211183, 0x0},
+	{0x0100d0, 0x0},
+	{0x1100d0, 0x0},
+	{0x2100d0, 0x0},
+	{0x0101d0, 0x0},
+	{0x1101d0, 0x0},
+	{0x2101d0, 0x0},
+	{0x0100d1, 0x0},
+	{0x1100d1, 0x0},
+	{0x2100d1, 0x0},
+	{0x0101d1, 0x0},
+	{0x1101d1, 0x0},
+	{0x2101d1, 0x0},
+	{0x0100d2, 0x0},
+	{0x1100d2, 0x0},
+	{0x2100d2, 0x0},
+	{0x0101d2, 0x0},
+	{0x1101d2, 0x0},
+	{0x2101d2, 0x0},
+	{0x0100d3, 0x0},
+	{0x1100d3, 0x0},
+	{0x2100d3, 0x0},
+	{0x0101d3, 0x0},
+	{0x1101d3, 0x0},
+	{0x2101d3, 0x0},
+	{0x0110d0, 0x0},
+	{0x1110d0, 0x0},
+	{0x2110d0, 0x0},
+	{0x0111d0, 0x0},
+	{0x1111d0, 0x0},
+	{0x2111d0, 0x0},
+	{0x0110d1, 0x0},
+	{0x1110d1, 0x0},
+	{0x2110d1, 0x0},
+	{0x0111d1, 0x0},
+	{0x1111d1, 0x0},
+	{0x2111d1, 0x0},
+	{0x0110d2, 0x0},
+	{0x1110d2, 0x0},
+	{0x2110d2, 0x0},
+	{0x0111d2, 0x0},
+	{0x1111d2, 0x0},
+	{0x2111d2, 0x0},
+	{0x0110d3, 0x0},
+	{0x1110d3, 0x0},
+	{0x2110d3, 0x0},
+	{0x0111d3, 0x0},
+	{0x1111d3, 0x0},
+	{0x2111d3, 0x0},
+	{0x010068, 0x0},
+	{0x010168, 0x0},
+	{0x010268, 0x0},
+	{0x010368, 0x0},
+	{0x010468, 0x0},
+	{0x010568, 0x0},
+	{0x010668, 0x0},
+	{0x010768, 0x0},
+	{0x010868, 0x0},
+	{0x010069, 0x0},
+	{0x010169, 0x0},
+	{0x010269, 0x0},
+	{0x010369, 0x0},
+	{0x010469, 0x0},
+	{0x010569, 0x0},
+	{0x010669, 0x0},
+	{0x010769, 0x0},
+	{0x010869, 0x0},
+	{0x01006a, 0x0},
+	{0x01016a, 0x0},
+	{0x01026a, 0x0},
+	{0x01036a, 0x0},
+	{0x01046a, 0x0},
+	{0x01056a, 0x0},
+	{0x01066a, 0x0},
+	{0x01076a, 0x0},
+	{0x01086a, 0x0},
+	{0x01006b, 0x0},
+	{0x01016b, 0x0},
+	{0x01026b, 0x0},
+	{0x01036b, 0x0},
+	{0x01046b, 0x0},
+	{0x01056b, 0x0},
+	{0x01066b, 0x0},
+	{0x01076b, 0x0},
+	{0x01086b, 0x0},
+	{0x011068, 0x0},
+	{0x011168, 0x0},
+	{0x011268, 0x0},
+	{0x011368, 0x0},
+	{0x011468, 0x0},
+	{0x011568, 0x0},
+	{0x011668, 0x0},
+	{0x011768, 0x0},
+	{0x011868, 0x0},
+	{0x011069, 0x0},
+	{0x011169, 0x0},
+	{0x011269, 0x0},
+	{0x011369, 0x0},
+	{0x011469, 0x0},
+	{0x011569, 0x0},
+	{0x011669, 0x0},
+	{0x011769, 0x0},
+	{0x011869, 0x0},
+	{0x01106a, 0x0},
+	{0x01116a, 0x0},
+	{0x01126a, 0x0},
+	{0x01136a, 0x0},
+	{0x01146a, 0x0},
+	{0x01156a, 0x0},
+	{0x01166a, 0x0},
+	{0x01176a, 0x0},
+	{0x01186a, 0x0},
+	{0x01106b, 0x0},
+	{0x01116b, 0x0},
+	{0x01126b, 0x0},
+	{0x01136b, 0x0},
+	{0x01146b, 0x0},
+	{0x01156b, 0x0},
+	{0x01166b, 0x0},
+	{0x01176b, 0x0},
+	{0x01186b, 0x0},
+	{0x01008c, 0x0},
+	{0x11008c, 0x0},
+	{0x21008c, 0x0},
+	{0x01018c, 0x0},
+	{0x11018c, 0x0},
+	{0x21018c, 0x0},
+	{0x01008d, 0x0},
+	{0x11008d, 0x0},
+	{0x21008d, 0x0},
+	{0x01018d, 0x0},
+	{0x11018d, 0x0},
+	{0x21018d, 0x0},
+	{0x01008e, 0x0},
+	{0x11008e, 0x0},
+	{0x21008e, 0x0},
+	{0x01018e, 0x0},
+	{0x11018e, 0x0},
+	{0x21018e, 0x0},
+	{0x01008f, 0x0},
+	{0x11008f, 0x0},
+	{0x21008f, 0x0},
+	{0x01018f, 0x0},
+	{0x11018f, 0x0},
+	{0x21018f, 0x0},
+	{0x01108c, 0x0},
+	{0x11108c, 0x0},
+	{0x21108c, 0x0},
+	{0x01118c, 0x0},
+	{0x11118c, 0x0},
+	{0x21118c, 0x0},
+	{0x01108d, 0x0},
+	{0x11108d, 0x0},
+	{0x21108d, 0x0},
+	{0x01118d, 0x0},
+	{0x11118d, 0x0},
+	{0x21118d, 0x0},
+	{0x01108e, 0x0},
+	{0x11108e, 0x0},
+	{0x21108e, 0x0},
+	{0x01118e, 0x0},
+	{0x11118e, 0x0},
+	{0x21118e, 0x0},
+	{0x01108f, 0x0},
+	{0x11108f, 0x0},
+	{0x21108f, 0x0},
+	{0x01118f, 0x0},
+	{0x11118f, 0x0},
+	{0x21118f, 0x0},
+	{0x0100c0, 0x0},
+	{0x1100c0, 0x0},
+	{0x2100c0, 0x0},
+	{0x0101c0, 0x0},
+	{0x1101c0, 0x0},
+	{0x2101c0, 0x0},
+	{0x0102c0, 0x0},
+	{0x1102c0, 0x0},
+	{0x2102c0, 0x0},
+	{0x0103c0, 0x0},
+	{0x1103c0, 0x0},
+	{0x2103c0, 0x0},
+	{0x0104c0, 0x0},
+	{0x1104c0, 0x0},
+	{0x2104c0, 0x0},
+	{0x0105c0, 0x0},
+	{0x1105c0, 0x0},
+	{0x2105c0, 0x0},
+	{0x0106c0, 0x0},
+	{0x1106c0, 0x0},
+	{0x2106c0, 0x0},
+	{0x0107c0, 0x0},
+	{0x1107c0, 0x0},
+	{0x2107c0, 0x0},
+	{0x0108c0, 0x0},
+	{0x1108c0, 0x0},
+	{0x2108c0, 0x0},
+	{0x0100c1, 0x0},
+	{0x1100c1, 0x0},
+	{0x2100c1, 0x0},
+	{0x0101c1, 0x0},
+	{0x1101c1, 0x0},
+	{0x2101c1, 0x0},
+	{0x0102c1, 0x0},
+	{0x1102c1, 0x0},
+	{0x2102c1, 0x0},
+	{0x0103c1, 0x0},
+	{0x1103c1, 0x0},
+	{0x2103c1, 0x0},
+	{0x0104c1, 0x0},
+	{0x1104c1, 0x0},
+	{0x2104c1, 0x0},
+	{0x0105c1, 0x0},
+	{0x1105c1, 0x0},
+	{0x2105c1, 0x0},
+	{0x0106c1, 0x0},
+	{0x1106c1, 0x0},
+	{0x2106c1, 0x0},
+	{0x0107c1, 0x0},
+	{0x1107c1, 0x0},
+	{0x2107c1, 0x0},
+	{0x0108c1, 0x0},
+	{0x1108c1, 0x0},
+	{0x2108c1, 0x0},
+	{0x0100c2, 0x0},
+	{0x1100c2, 0x0},
+	{0x2100c2, 0x0},
+	{0x0101c2, 0x0},
+	{0x1101c2, 0x0},
+	{0x2101c2, 0x0},
+	{0x0102c2, 0x0},
+	{0x1102c2, 0x0},
+	{0x2102c2, 0x0},
+	{0x0103c2, 0x0},
+	{0x1103c2, 0x0},
+	{0x2103c2, 0x0},
+	{0x0104c2, 0x0},
+	{0x1104c2, 0x0},
+	{0x2104c2, 0x0},
+	{0x0105c2, 0x0},
+	{0x1105c2, 0x0},
+	{0x2105c2, 0x0},
+	{0x0106c2, 0x0},
+	{0x1106c2, 0x0},
+	{0x2106c2, 0x0},
+	{0x0107c2, 0x0},
+	{0x1107c2, 0x0},
+	{0x2107c2, 0x0},
+	{0x0108c2, 0x0},
+	{0x1108c2, 0x0},
+	{0x2108c2, 0x0},
+	{0x0100c3, 0x0},
+	{0x1100c3, 0x0},
+	{0x2100c3, 0x0},
+	{0x0101c3, 0x0},
+	{0x1101c3, 0x0},
+	{0x2101c3, 0x0},
+	{0x0102c3, 0x0},
+	{0x1102c3, 0x0},
+	{0x2102c3, 0x0},
+	{0x0103c3, 0x0},
+	{0x1103c3, 0x0},
+	{0x2103c3, 0x0},
+	{0x0104c3, 0x0},
+	{0x1104c3, 0x0},
+	{0x2104c3, 0x0},
+	{0x0105c3, 0x0},
+	{0x1105c3, 0x0},
+	{0x2105c3, 0x0},
+	{0x0106c3, 0x0},
+	{0x1106c3, 0x0},
+	{0x2106c3, 0x0},
+	{0x0107c3, 0x0},
+	{0x1107c3, 0x0},
+	{0x2107c3, 0x0},
+	{0x0108c3, 0x0},
+	{0x1108c3, 0x0},
+	{0x2108c3, 0x0},
+	{0x0110c0, 0x0},
+	{0x1110c0, 0x0},
+	{0x2110c0, 0x0},
+	{0x0111c0, 0x0},
+	{0x1111c0, 0x0},
+	{0x2111c0, 0x0},
+	{0x0112c0, 0x0},
+	{0x1112c0, 0x0},
+	{0x2112c0, 0x0},
+	{0x0113c0, 0x0},
+	{0x1113c0, 0x0},
+	{0x2113c0, 0x0},
+	{0x0114c0, 0x0},
+	{0x1114c0, 0x0},
+	{0x2114c0, 0x0},
+	{0x0115c0, 0x0},
+	{0x1115c0, 0x0},
+	{0x2115c0, 0x0},
+	{0x0116c0, 0x0},
+	{0x1116c0, 0x0},
+	{0x2116c0, 0x0},
+	{0x0117c0, 0x0},
+	{0x1117c0, 0x0},
+	{0x2117c0, 0x0},
+	{0x0118c0, 0x0},
+	{0x1118c0, 0x0},
+	{0x2118c0, 0x0},
+	{0x0110c1, 0x0},
+	{0x1110c1, 0x0},
+	{0x2110c1, 0x0},
+	{0x0111c1, 0x0},
+	{0x1111c1, 0x0},
+	{0x2111c1, 0x0},
+	{0x0112c1, 0x0},
+	{0x1112c1, 0x0},
+	{0x2112c1, 0x0},
+	{0x0113c1, 0x0},
+	{0x1113c1, 0x0},
+	{0x2113c1, 0x0},
+	{0x0114c1, 0x0},
+	{0x1114c1, 0x0},
+	{0x2114c1, 0x0},
+	{0x0115c1, 0x0},
+	{0x1115c1, 0x0},
+	{0x2115c1, 0x0},
+	{0x0116c1, 0x0},
+	{0x1116c1, 0x0},
+	{0x2116c1, 0x0},
+	{0x0117c1, 0x0},
+	{0x1117c1, 0x0},
+	{0x2117c1, 0x0},
+	{0x0118c1, 0x0},
+	{0x1118c1, 0x0},
+	{0x2118c1, 0x0},
+	{0x0110c2, 0x0},
+	{0x1110c2, 0x0},
+	{0x2110c2, 0x0},
+	{0x0111c2, 0x0},
+	{0x1111c2, 0x0},
+	{0x2111c2, 0x0},
+	{0x0112c2, 0x0},
+	{0x1112c2, 0x0},
+	{0x2112c2, 0x0},
+	{0x0113c2, 0x0},
+	{0x1113c2, 0x0},
+	{0x2113c2, 0x0},
+	{0x0114c2, 0x0},
+	{0x1114c2, 0x0},
+	{0x2114c2, 0x0},
+	{0x0115c2, 0x0},
+	{0x1115c2, 0x0},
+	{0x2115c2, 0x0},
+	{0x0116c2, 0x0},
+	{0x1116c2, 0x0},
+	{0x2116c2, 0x0},
+	{0x0117c2, 0x0},
+	{0x1117c2, 0x0},
+	{0x2117c2, 0x0},
+	{0x0118c2, 0x0},
+	{0x1118c2, 0x0},
+	{0x2118c2, 0x0},
+	{0x0110c3, 0x0},
+	{0x1110c3, 0x0},
+	{0x2110c3, 0x0},
+	{0x0111c3, 0x0},
+	{0x1111c3, 0x0},
+	{0x2111c3, 0x0},
+	{0x0112c3, 0x0},
+	{0x1112c3, 0x0},
+	{0x2112c3, 0x0},
+	{0x0113c3, 0x0},
+	{0x1113c3, 0x0},
+	{0x2113c3, 0x0},
+	{0x0114c3, 0x0},
+	{0x1114c3, 0x0},
+	{0x2114c3, 0x0},
+	{0x0115c3, 0x0},
+	{0x1115c3, 0x0},
+	{0x2115c3, 0x0},
+	{0x0116c3, 0x0},
+	{0x1116c3, 0x0},
+	{0x2116c3, 0x0},
+	{0x0117c3, 0x0},
+	{0x1117c3, 0x0},
+	{0x2117c3, 0x0},
+	{0x0118c3, 0x0},
+	{0x1118c3, 0x0},
+	{0x2118c3, 0x0},
+	{0x010020, 0x0},
+	{0x110020, 0x0},
+	{0x210020, 0x0},
+	{0x011020, 0x0},
+	{0x111020, 0x0},
+	{0x211020, 0x0},
+	{0x02007d, 0x0},
+	{0x12007d, 0x0},
+	{0x22007d, 0x0},
+	{0x010040, 0x0},
+	{0x010140, 0x0},
+	{0x010240, 0x0},
+	{0x010340, 0x0},
+	{0x010440, 0x0},
+	{0x010540, 0x0},
+	{0x010640, 0x0},
+	{0x010740, 0x0},
+	{0x010840, 0x0},
+	{0x010030, 0x0},
+	{0x010130, 0x0},
+	{0x010230, 0x0},
+	{0x010330, 0x0},
+	{0x010430, 0x0},
+	{0x010530, 0x0},
+	{0x010630, 0x0},
+	{0x010730, 0x0},
+	{0x010830, 0x0},
+	{0x011040, 0x0},
+	{0x011140, 0x0},
+	{0x011240, 0x0},
+	{0x011340, 0x0},
+	{0x011440, 0x0},
+	{0x011540, 0x0},
+	{0x011640, 0x0},
+	{0x011740, 0x0},
+	{0x011840, 0x0},
+	{0x011030, 0x0},
+	{0x011130, 0x0},
+	{0x011230, 0x0},
+	{0x011330, 0x0},
+	{0x011430, 0x0},
+	{0x011530, 0x0},
+	{0x011630, 0x0},
+	{0x011730, 0x0},
+	{0x011830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x960 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x1000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x31f },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x834 },
+	{ 0x54030, 0x105 },
+	{ 0x54031, 0x18 },
+	{ 0x54032, 0x200 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x810 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x1 },
+	{ 0x54003, 0x42a },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x1000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x21f },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x54012, 0x1 },
+	{ 0x54030, 0x105 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x10 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x960 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x1000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x61 },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400e, 0x1f7f },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x834 },
+	{ 0x54030, 0x105 },
+	{ 0x54031, 0x18 },
+	{ 0x54032, 0x200 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x810 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x2 },
+	{ 0x90033, 0x10 },
+	{ 0x90034, 0x139 },
+	{ 0x90035, 0xb },
+	{ 0x90036, 0x7c0 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0x44 },
+	{ 0x90039, 0x633 },
+	{ 0x9003a, 0x159 },
+	{ 0x9003b, 0x14f },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x47 },
+	{ 0x9003f, 0x633 },
+	{ 0x90040, 0x149 },
+	{ 0x90041, 0x4f },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x179 },
+	{ 0x90044, 0x8 },
+	{ 0x90045, 0xe0 },
+	{ 0x90046, 0x109 },
+	{ 0x90047, 0x0 },
+	{ 0x90048, 0x7c8 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x1 },
+	{ 0x9004c, 0x8 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x45a },
+	{ 0x9004f, 0x9 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x448 },
+	{ 0x90052, 0x109 },
+	{ 0x90053, 0x40 },
+	{ 0x90054, 0x633 },
+	{ 0x90055, 0x179 },
+	{ 0x90056, 0x1 },
+	{ 0x90057, 0x618 },
+	{ 0x90058, 0x109 },
+	{ 0x90059, 0x40c0 },
+	{ 0x9005a, 0x633 },
+	{ 0x9005b, 0x149 },
+	{ 0x9005c, 0x8 },
+	{ 0x9005d, 0x4 },
+	{ 0x9005e, 0x48 },
+	{ 0x9005f, 0x4040 },
+	{ 0x90060, 0x633 },
+	{ 0x90061, 0x149 },
+	{ 0x90062, 0x0 },
+	{ 0x90063, 0x4 },
+	{ 0x90064, 0x48 },
+	{ 0x90065, 0x40 },
+	{ 0x90066, 0x633 },
+	{ 0x90067, 0x149 },
+	{ 0x90068, 0x10 },
+	{ 0x90069, 0x4 },
+	{ 0x9006a, 0x18 },
+	{ 0x9006b, 0x0 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x78 },
+	{ 0x9006e, 0x549 },
+	{ 0x9006f, 0x633 },
+	{ 0x90070, 0x159 },
+	{ 0x90071, 0xd49 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0x94a },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x441 },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x149 },
+	{ 0x9007a, 0x42 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x1 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x0 },
+	{ 0x90081, 0xe0 },
+	{ 0x90082, 0x109 },
+	{ 0x90083, 0xa },
+	{ 0x90084, 0x10 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0x9 },
+	{ 0x90087, 0x3c0 },
+	{ 0x90088, 0x149 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x159 },
+	{ 0x9008c, 0x18 },
+	{ 0x9008d, 0x10 },
+	{ 0x9008e, 0x109 },
+	{ 0x9008f, 0x0 },
+	{ 0x90090, 0x3c0 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x18 },
+	{ 0x90093, 0x4 },
+	{ 0x90094, 0x48 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x58 },
+	{ 0x90098, 0xb },
+	{ 0x90099, 0x10 },
+	{ 0x9009a, 0x109 },
+	{ 0x9009b, 0x1 },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x5 },
+	{ 0x9009f, 0x7c0 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x0 },
+	{ 0x900a2, 0x8140 },
+	{ 0x900a3, 0x10c },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x8138 },
+	{ 0x900a6, 0x10c },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7c8 },
+	{ 0x900a9, 0x101 },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x448 },
+	{ 0x900ac, 0x109 },
+	{ 0x900ad, 0xf },
+	{ 0x900ae, 0x7c0 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x47 },
+	{ 0x900b1, 0x630 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x8 },
+	{ 0x900b4, 0x618 },
+	{ 0x900b5, 0x109 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0xe0 },
+	{ 0x900b8, 0x109 },
+	{ 0x900b9, 0x0 },
+	{ 0x900ba, 0x7c8 },
+	{ 0x900bb, 0x109 },
+	{ 0x900bc, 0x8 },
+	{ 0x900bd, 0x8140 },
+	{ 0x900be, 0x10c },
+	{ 0x900bf, 0x0 },
+	{ 0x900c0, 0x1 },
+	{ 0x900c1, 0x8 },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x8 },
+	{ 0x900c5, 0x8 },
+	{ 0x900c6, 0x7c8 },
+	{ 0x900c7, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x90026, 0x2b },
+	{ 0x2000b, 0x4b },
+	{ 0x2000c, 0x96 },
+	{ 0x2000d, 0x5dc },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x21 },
+	{ 0x12000c, 0x42 },
+	{ 0x12000d, 0x29a },
+	{ 0x12000e, 0x21 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0xffff },
+	{ 0x90013, 0x6152 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x0 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 2400mts 1D */
+		.drate = 2400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 1066mts 1D */
+		.drate = 1066,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P0 2400mts 2D */
+		.drate = 2400,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 2400, 1066, },
+};
+
diff --git a/board/freescale/imx8mm_ab2/ddr4_imx8mn_som_ld.c b/board/freescale/imx8mm_ab2/ddr4_imx8mn_som_ld.c
new file mode 100644
index 00000000000..a3577efd0b2
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/ddr4_imx8mn_som_ld.c
@@ -0,0 +1,1056 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400000, 0x81040010 },
+	{ 0x3d400030, 0x20 },
+	{ 0x3d400034, 0x221306 },
+	{ 0x3d400050, 0x210070 },
+	{ 0x3d400054, 0x10008 },
+	{ 0x3d400060, 0x0 },
+	{ 0x3d400064, 0x6100dc },
+	{ 0x3d4000c0, 0x0 },
+	{ 0x3d4000c4, 0x1000 },
+	{ 0x3d4000d0, 0xc00200c5 },
+	{ 0x3d4000d4, 0x500000 },
+	{ 0x3d4000dc, 0x2340105 },
+	{ 0x3d4000e0, 0x0 },
+	{ 0x3d4000e4, 0x110000 },
+	{ 0x3d4000e8, 0x2000600 },
+	{ 0x3d4000ec, 0x410 },
+	{ 0x3d4000f0, 0x20 },
+	{ 0x3d4000f4, 0xec7 },
+	{ 0x3d400100, 0xd0c1b0d },
+	{ 0x3d400104, 0x30313 },
+	{ 0x3d400108, 0x508060a },
+	{ 0x3d40010c, 0x400c },
+	{ 0x3d400110, 0x6030306 },
+	{ 0x3d400114, 0x4040302 },
+	{ 0x3d40011c, 0x404 },
+	{ 0x3d400120, 0x5050d08 },
+	{ 0x3d400124, 0x20308 },
+	{ 0x3d40012c, 0x1406010e },
+	{ 0x3d400130, 0x8 },
+	{ 0x3d40013c, 0x0 },
+	{ 0x3d400180, 0x1000040 },
+	{ 0x3d400184, 0x30d4 },
+	{ 0x3d400190, 0x38b8204 },
+	{ 0x3d400194, 0x2020303 },
+	{ 0x3d400198, 0x7f04011 },
+	{ 0x3d40019c, 0xb0 },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0x48005a },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x1 },
+	{ 0x3d4001b4, 0xb04 },
+	{ 0x3d4001b8, 0x4 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x0 },
+	{ 0x3d400200, 0x3f1f },
+	{ 0x3d400204, 0x3f0909 },
+	{ 0x3d400208, 0x700 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf07 },
+	{ 0x3d400220, 0x3f01 },
+	{ 0x3d400240, 0x600061c },
+	{ 0x3d400244, 0x1323 },
+	{ 0x3d400400, 0x100 },
+	{ 0x3d400250, 0x317d1a07 },
+	{ 0x3d400254, 0xf },
+	{ 0x3d40025c, 0x2a001b76 },
+	{ 0x3d400264, 0x7300b473 },
+	{ 0x3d40026c, 0x30000e06 },
+	{ 0x3d400300, 0x14 },
+	{ 0x3d40036c, 0x10 },
+	{ 0x3d400404, 0x13193 },
+	{ 0x3d400408, 0x6096 },
+	{ 0x3d400490, 0x1 },
+	{ 0x3d400494, 0x2000c00 },
+	{ 0x3d400498, 0x3c00db },
+	{ 0x3d40049c, 0x100009 },
+	{ 0x3d4004a0, 0x2 },
+	{ 0x3d402050, 0x210070 },
+	{ 0x3d402064, 0x400093 },
+	{ 0x3d4020dc, 0x40105 },
+	{ 0x3d4020e0, 0x0 },
+	{ 0x3d4020e8, 0x2000600 },
+	{ 0x3d4020ec, 0x10 },
+	{ 0x3d402100, 0xb081209 },
+	{ 0x3d402104, 0x2020d },
+	{ 0x3d402108, 0x5050309 },
+	{ 0x3d40210c, 0x400c },
+	{ 0x3d402110, 0x5030206 },
+	{ 0x3d402114, 0x3030202 },
+	{ 0x3d40211c, 0x303 },
+	{ 0x3d402120, 0x4040d06 },
+	{ 0x3d402124, 0x20208 },
+	{ 0x3d40212c, 0x1205010e },
+	{ 0x3d402130, 0x8 },
+	{ 0x3d40213c, 0x0 },
+	{ 0x3d402180, 0x1000040 },
+	{ 0x3d402190, 0x3858204 },
+	{ 0x3d402194, 0x2020303 },
+	{ 0x3d4021b4, 0x504 },
+	{ 0x3d4021b8, 0x4 },
+	{ 0x3d402240, 0x6000604 },
+	{ 0x3d4020f4, 0xec7 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x1005f, 0x2fd },
+	{ 0x1015f, 0x2fd },
+	{ 0x1105f, 0x2fd },
+	{ 0x1115f, 0x2fd },
+	{ 0x11005f, 0x2fd },
+	{ 0x11015f, 0x2fd },
+	{ 0x11105f, 0x2fd },
+	{ 0x11115f, 0x2fd },
+	{ 0x55, 0x355 },
+	{ 0x1055, 0x355 },
+	{ 0x2055, 0x355 },
+	{ 0x3055, 0x355 },
+	{ 0x4055, 0x55 },
+	{ 0x5055, 0x55 },
+	{ 0x6055, 0x355 },
+	{ 0x7055, 0x355 },
+	{ 0x8055, 0x355 },
+	{ 0x9055, 0x355 },
+	{ 0x200c5, 0xb },
+	{ 0x1200c5, 0x6 },
+	{ 0x2002e, 0x1 },
+	{ 0x12002e, 0x1 },
+	{ 0x20024, 0x8 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x8 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0xa },
+	{ 0x120056, 0xa },
+	{ 0x1004d, 0x1a },
+	{ 0x1014d, 0x1a },
+	{ 0x1104d, 0x1a },
+	{ 0x1114d, 0x1a },
+	{ 0x11004d, 0x1a },
+	{ 0x11014d, 0x1a },
+	{ 0x11104d, 0x1a },
+	{ 0x11114d, 0x1a },
+	{ 0x10049, 0xe38 },
+	{ 0x10149, 0xe38 },
+	{ 0x11049, 0xe38 },
+	{ 0x11149, 0xe38 },
+	{ 0x110049, 0xe38 },
+	{ 0x110149, 0xe38 },
+	{ 0x111049, 0xe38 },
+	{ 0x111149, 0xe38 },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x1 },
+	{ 0x20075, 0x2 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x190 },
+	{ 0x120008, 0x10a },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x268 },
+	{ 0x10043, 0x5b1 },
+	{ 0x10143, 0x5b1 },
+	{ 0x11043, 0x5b1 },
+	{ 0x11143, 0x5b1 },
+	{ 0x1200b2, 0x268 },
+	{ 0x110043, 0x5b1 },
+	{ 0x110143, 0x5b1 },
+	{ 0x111043, 0x5b1 },
+	{ 0x111143, 0x5b1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x20019, 0x5 },
+	{ 0x120019, 0x5 },
+	{ 0x200f0, 0x5555 },
+	{ 0x200f1, 0x5555 },
+	{ 0x200f2, 0x5555 },
+	{ 0x200f3, 0x5555 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0x5555 },
+	{ 0x200f6, 0x5555 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x2005b, 0x7529 },
+	{ 0x2005c, 0x0 },
+	{ 0x200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x200cc, 0x1f7 },
+	{ 0x1200c7, 0x21 },
+	{ 0x1200ca, 0x24 },
+	{ 0x1200cc, 0x1f7 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{0x0200b2, 0x0},
+	{0x1200b2, 0x0},
+	{0x2200b2, 0x0},
+	{0x0200cb, 0x0},
+	{0x010043, 0x0},
+	{0x110043, 0x0},
+	{0x210043, 0x0},
+	{0x010143, 0x0},
+	{0x110143, 0x0},
+	{0x210143, 0x0},
+	{0x011043, 0x0},
+	{0x111043, 0x0},
+	{0x211043, 0x0},
+	{0x011143, 0x0},
+	{0x111143, 0x0},
+	{0x211143, 0x0},
+	{0x000080, 0x0},
+	{0x100080, 0x0},
+	{0x200080, 0x0},
+	{0x001080, 0x0},
+	{0x101080, 0x0},
+	{0x201080, 0x0},
+	{0x002080, 0x0},
+	{0x102080, 0x0},
+	{0x202080, 0x0},
+	{0x003080, 0x0},
+	{0x103080, 0x0},
+	{0x203080, 0x0},
+	{0x004080, 0x0},
+	{0x104080, 0x0},
+	{0x204080, 0x0},
+	{0x005080, 0x0},
+	{0x105080, 0x0},
+	{0x205080, 0x0},
+	{0x006080, 0x0},
+	{0x106080, 0x0},
+	{0x206080, 0x0},
+	{0x007080, 0x0},
+	{0x107080, 0x0},
+	{0x207080, 0x0},
+	{0x008080, 0x0},
+	{0x108080, 0x0},
+	{0x208080, 0x0},
+	{0x009080, 0x0},
+	{0x109080, 0x0},
+	{0x209080, 0x0},
+	{0x010080, 0x0},
+	{0x110080, 0x0},
+	{0x210080, 0x0},
+	{0x010180, 0x0},
+	{0x110180, 0x0},
+	{0x210180, 0x0},
+	{0x010081, 0x0},
+	{0x110081, 0x0},
+	{0x210081, 0x0},
+	{0x010181, 0x0},
+	{0x110181, 0x0},
+	{0x210181, 0x0},
+	{0x010082, 0x0},
+	{0x110082, 0x0},
+	{0x210082, 0x0},
+	{0x010182, 0x0},
+	{0x110182, 0x0},
+	{0x210182, 0x0},
+	{0x010083, 0x0},
+	{0x110083, 0x0},
+	{0x210083, 0x0},
+	{0x010183, 0x0},
+	{0x110183, 0x0},
+	{0x210183, 0x0},
+	{0x011080, 0x0},
+	{0x111080, 0x0},
+	{0x211080, 0x0},
+	{0x011180, 0x0},
+	{0x111180, 0x0},
+	{0x211180, 0x0},
+	{0x011081, 0x0},
+	{0x111081, 0x0},
+	{0x211081, 0x0},
+	{0x011181, 0x0},
+	{0x111181, 0x0},
+	{0x211181, 0x0},
+	{0x011082, 0x0},
+	{0x111082, 0x0},
+	{0x211082, 0x0},
+	{0x011182, 0x0},
+	{0x111182, 0x0},
+	{0x211182, 0x0},
+	{0x011083, 0x0},
+	{0x111083, 0x0},
+	{0x211083, 0x0},
+	{0x011183, 0x0},
+	{0x111183, 0x0},
+	{0x211183, 0x0},
+	{0x0100d0, 0x0},
+	{0x1100d0, 0x0},
+	{0x2100d0, 0x0},
+	{0x0101d0, 0x0},
+	{0x1101d0, 0x0},
+	{0x2101d0, 0x0},
+	{0x0100d1, 0x0},
+	{0x1100d1, 0x0},
+	{0x2100d1, 0x0},
+	{0x0101d1, 0x0},
+	{0x1101d1, 0x0},
+	{0x2101d1, 0x0},
+	{0x0100d2, 0x0},
+	{0x1100d2, 0x0},
+	{0x2100d2, 0x0},
+	{0x0101d2, 0x0},
+	{0x1101d2, 0x0},
+	{0x2101d2, 0x0},
+	{0x0100d3, 0x0},
+	{0x1100d3, 0x0},
+	{0x2100d3, 0x0},
+	{0x0101d3, 0x0},
+	{0x1101d3, 0x0},
+	{0x2101d3, 0x0},
+	{0x0110d0, 0x0},
+	{0x1110d0, 0x0},
+	{0x2110d0, 0x0},
+	{0x0111d0, 0x0},
+	{0x1111d0, 0x0},
+	{0x2111d0, 0x0},
+	{0x0110d1, 0x0},
+	{0x1110d1, 0x0},
+	{0x2110d1, 0x0},
+	{0x0111d1, 0x0},
+	{0x1111d1, 0x0},
+	{0x2111d1, 0x0},
+	{0x0110d2, 0x0},
+	{0x1110d2, 0x0},
+	{0x2110d2, 0x0},
+	{0x0111d2, 0x0},
+	{0x1111d2, 0x0},
+	{0x2111d2, 0x0},
+	{0x0110d3, 0x0},
+	{0x1110d3, 0x0},
+	{0x2110d3, 0x0},
+	{0x0111d3, 0x0},
+	{0x1111d3, 0x0},
+	{0x2111d3, 0x0},
+	{0x010068, 0x0},
+	{0x010168, 0x0},
+	{0x010268, 0x0},
+	{0x010368, 0x0},
+	{0x010468, 0x0},
+	{0x010568, 0x0},
+	{0x010668, 0x0},
+	{0x010768, 0x0},
+	{0x010868, 0x0},
+	{0x010069, 0x0},
+	{0x010169, 0x0},
+	{0x010269, 0x0},
+	{0x010369, 0x0},
+	{0x010469, 0x0},
+	{0x010569, 0x0},
+	{0x010669, 0x0},
+	{0x010769, 0x0},
+	{0x010869, 0x0},
+	{0x01006a, 0x0},
+	{0x01016a, 0x0},
+	{0x01026a, 0x0},
+	{0x01036a, 0x0},
+	{0x01046a, 0x0},
+	{0x01056a, 0x0},
+	{0x01066a, 0x0},
+	{0x01076a, 0x0},
+	{0x01086a, 0x0},
+	{0x01006b, 0x0},
+	{0x01016b, 0x0},
+	{0x01026b, 0x0},
+	{0x01036b, 0x0},
+	{0x01046b, 0x0},
+	{0x01056b, 0x0},
+	{0x01066b, 0x0},
+	{0x01076b, 0x0},
+	{0x01086b, 0x0},
+	{0x011068, 0x0},
+	{0x011168, 0x0},
+	{0x011268, 0x0},
+	{0x011368, 0x0},
+	{0x011468, 0x0},
+	{0x011568, 0x0},
+	{0x011668, 0x0},
+	{0x011768, 0x0},
+	{0x011868, 0x0},
+	{0x011069, 0x0},
+	{0x011169, 0x0},
+	{0x011269, 0x0},
+	{0x011369, 0x0},
+	{0x011469, 0x0},
+	{0x011569, 0x0},
+	{0x011669, 0x0},
+	{0x011769, 0x0},
+	{0x011869, 0x0},
+	{0x01106a, 0x0},
+	{0x01116a, 0x0},
+	{0x01126a, 0x0},
+	{0x01136a, 0x0},
+	{0x01146a, 0x0},
+	{0x01156a, 0x0},
+	{0x01166a, 0x0},
+	{0x01176a, 0x0},
+	{0x01186a, 0x0},
+	{0x01106b, 0x0},
+	{0x01116b, 0x0},
+	{0x01126b, 0x0},
+	{0x01136b, 0x0},
+	{0x01146b, 0x0},
+	{0x01156b, 0x0},
+	{0x01166b, 0x0},
+	{0x01176b, 0x0},
+	{0x01186b, 0x0},
+	{0x01008c, 0x0},
+	{0x11008c, 0x0},
+	{0x21008c, 0x0},
+	{0x01018c, 0x0},
+	{0x11018c, 0x0},
+	{0x21018c, 0x0},
+	{0x01008d, 0x0},
+	{0x11008d, 0x0},
+	{0x21008d, 0x0},
+	{0x01018d, 0x0},
+	{0x11018d, 0x0},
+	{0x21018d, 0x0},
+	{0x01008e, 0x0},
+	{0x11008e, 0x0},
+	{0x21008e, 0x0},
+	{0x01018e, 0x0},
+	{0x11018e, 0x0},
+	{0x21018e, 0x0},
+	{0x01008f, 0x0},
+	{0x11008f, 0x0},
+	{0x21008f, 0x0},
+	{0x01018f, 0x0},
+	{0x11018f, 0x0},
+	{0x21018f, 0x0},
+	{0x01108c, 0x0},
+	{0x11108c, 0x0},
+	{0x21108c, 0x0},
+	{0x01118c, 0x0},
+	{0x11118c, 0x0},
+	{0x21118c, 0x0},
+	{0x01108d, 0x0},
+	{0x11108d, 0x0},
+	{0x21108d, 0x0},
+	{0x01118d, 0x0},
+	{0x11118d, 0x0},
+	{0x21118d, 0x0},
+	{0x01108e, 0x0},
+	{0x11108e, 0x0},
+	{0x21108e, 0x0},
+	{0x01118e, 0x0},
+	{0x11118e, 0x0},
+	{0x21118e, 0x0},
+	{0x01108f, 0x0},
+	{0x11108f, 0x0},
+	{0x21108f, 0x0},
+	{0x01118f, 0x0},
+	{0x11118f, 0x0},
+	{0x21118f, 0x0},
+	{0x0100c0, 0x0},
+	{0x1100c0, 0x0},
+	{0x2100c0, 0x0},
+	{0x0101c0, 0x0},
+	{0x1101c0, 0x0},
+	{0x2101c0, 0x0},
+	{0x0102c0, 0x0},
+	{0x1102c0, 0x0},
+	{0x2102c0, 0x0},
+	{0x0103c0, 0x0},
+	{0x1103c0, 0x0},
+	{0x2103c0, 0x0},
+	{0x0104c0, 0x0},
+	{0x1104c0, 0x0},
+	{0x2104c0, 0x0},
+	{0x0105c0, 0x0},
+	{0x1105c0, 0x0},
+	{0x2105c0, 0x0},
+	{0x0106c0, 0x0},
+	{0x1106c0, 0x0},
+	{0x2106c0, 0x0},
+	{0x0107c0, 0x0},
+	{0x1107c0, 0x0},
+	{0x2107c0, 0x0},
+	{0x0108c0, 0x0},
+	{0x1108c0, 0x0},
+	{0x2108c0, 0x0},
+	{0x0100c1, 0x0},
+	{0x1100c1, 0x0},
+	{0x2100c1, 0x0},
+	{0x0101c1, 0x0},
+	{0x1101c1, 0x0},
+	{0x2101c1, 0x0},
+	{0x0102c1, 0x0},
+	{0x1102c1, 0x0},
+	{0x2102c1, 0x0},
+	{0x0103c1, 0x0},
+	{0x1103c1, 0x0},
+	{0x2103c1, 0x0},
+	{0x0104c1, 0x0},
+	{0x1104c1, 0x0},
+	{0x2104c1, 0x0},
+	{0x0105c1, 0x0},
+	{0x1105c1, 0x0},
+	{0x2105c1, 0x0},
+	{0x0106c1, 0x0},
+	{0x1106c1, 0x0},
+	{0x2106c1, 0x0},
+	{0x0107c1, 0x0},
+	{0x1107c1, 0x0},
+	{0x2107c1, 0x0},
+	{0x0108c1, 0x0},
+	{0x1108c1, 0x0},
+	{0x2108c1, 0x0},
+	{0x0100c2, 0x0},
+	{0x1100c2, 0x0},
+	{0x2100c2, 0x0},
+	{0x0101c2, 0x0},
+	{0x1101c2, 0x0},
+	{0x2101c2, 0x0},
+	{0x0102c2, 0x0},
+	{0x1102c2, 0x0},
+	{0x2102c2, 0x0},
+	{0x0103c2, 0x0},
+	{0x1103c2, 0x0},
+	{0x2103c2, 0x0},
+	{0x0104c2, 0x0},
+	{0x1104c2, 0x0},
+	{0x2104c2, 0x0},
+	{0x0105c2, 0x0},
+	{0x1105c2, 0x0},
+	{0x2105c2, 0x0},
+	{0x0106c2, 0x0},
+	{0x1106c2, 0x0},
+	{0x2106c2, 0x0},
+	{0x0107c2, 0x0},
+	{0x1107c2, 0x0},
+	{0x2107c2, 0x0},
+	{0x0108c2, 0x0},
+	{0x1108c2, 0x0},
+	{0x2108c2, 0x0},
+	{0x0100c3, 0x0},
+	{0x1100c3, 0x0},
+	{0x2100c3, 0x0},
+	{0x0101c3, 0x0},
+	{0x1101c3, 0x0},
+	{0x2101c3, 0x0},
+	{0x0102c3, 0x0},
+	{0x1102c3, 0x0},
+	{0x2102c3, 0x0},
+	{0x0103c3, 0x0},
+	{0x1103c3, 0x0},
+	{0x2103c3, 0x0},
+	{0x0104c3, 0x0},
+	{0x1104c3, 0x0},
+	{0x2104c3, 0x0},
+	{0x0105c3, 0x0},
+	{0x1105c3, 0x0},
+	{0x2105c3, 0x0},
+	{0x0106c3, 0x0},
+	{0x1106c3, 0x0},
+	{0x2106c3, 0x0},
+	{0x0107c3, 0x0},
+	{0x1107c3, 0x0},
+	{0x2107c3, 0x0},
+	{0x0108c3, 0x0},
+	{0x1108c3, 0x0},
+	{0x2108c3, 0x0},
+	{0x0110c0, 0x0},
+	{0x1110c0, 0x0},
+	{0x2110c0, 0x0},
+	{0x0111c0, 0x0},
+	{0x1111c0, 0x0},
+	{0x2111c0, 0x0},
+	{0x0112c0, 0x0},
+	{0x1112c0, 0x0},
+	{0x2112c0, 0x0},
+	{0x0113c0, 0x0},
+	{0x1113c0, 0x0},
+	{0x2113c0, 0x0},
+	{0x0114c0, 0x0},
+	{0x1114c0, 0x0},
+	{0x2114c0, 0x0},
+	{0x0115c0, 0x0},
+	{0x1115c0, 0x0},
+	{0x2115c0, 0x0},
+	{0x0116c0, 0x0},
+	{0x1116c0, 0x0},
+	{0x2116c0, 0x0},
+	{0x0117c0, 0x0},
+	{0x1117c0, 0x0},
+	{0x2117c0, 0x0},
+	{0x0118c0, 0x0},
+	{0x1118c0, 0x0},
+	{0x2118c0, 0x0},
+	{0x0110c1, 0x0},
+	{0x1110c1, 0x0},
+	{0x2110c1, 0x0},
+	{0x0111c1, 0x0},
+	{0x1111c1, 0x0},
+	{0x2111c1, 0x0},
+	{0x0112c1, 0x0},
+	{0x1112c1, 0x0},
+	{0x2112c1, 0x0},
+	{0x0113c1, 0x0},
+	{0x1113c1, 0x0},
+	{0x2113c1, 0x0},
+	{0x0114c1, 0x0},
+	{0x1114c1, 0x0},
+	{0x2114c1, 0x0},
+	{0x0115c1, 0x0},
+	{0x1115c1, 0x0},
+	{0x2115c1, 0x0},
+	{0x0116c1, 0x0},
+	{0x1116c1, 0x0},
+	{0x2116c1, 0x0},
+	{0x0117c1, 0x0},
+	{0x1117c1, 0x0},
+	{0x2117c1, 0x0},
+	{0x0118c1, 0x0},
+	{0x1118c1, 0x0},
+	{0x2118c1, 0x0},
+	{0x0110c2, 0x0},
+	{0x1110c2, 0x0},
+	{0x2110c2, 0x0},
+	{0x0111c2, 0x0},
+	{0x1111c2, 0x0},
+	{0x2111c2, 0x0},
+	{0x0112c2, 0x0},
+	{0x1112c2, 0x0},
+	{0x2112c2, 0x0},
+	{0x0113c2, 0x0},
+	{0x1113c2, 0x0},
+	{0x2113c2, 0x0},
+	{0x0114c2, 0x0},
+	{0x1114c2, 0x0},
+	{0x2114c2, 0x0},
+	{0x0115c2, 0x0},
+	{0x1115c2, 0x0},
+	{0x2115c2, 0x0},
+	{0x0116c2, 0x0},
+	{0x1116c2, 0x0},
+	{0x2116c2, 0x0},
+	{0x0117c2, 0x0},
+	{0x1117c2, 0x0},
+	{0x2117c2, 0x0},
+	{0x0118c2, 0x0},
+	{0x1118c2, 0x0},
+	{0x2118c2, 0x0},
+	{0x0110c3, 0x0},
+	{0x1110c3, 0x0},
+	{0x2110c3, 0x0},
+	{0x0111c3, 0x0},
+	{0x1111c3, 0x0},
+	{0x2111c3, 0x0},
+	{0x0112c3, 0x0},
+	{0x1112c3, 0x0},
+	{0x2112c3, 0x0},
+	{0x0113c3, 0x0},
+	{0x1113c3, 0x0},
+	{0x2113c3, 0x0},
+	{0x0114c3, 0x0},
+	{0x1114c3, 0x0},
+	{0x2114c3, 0x0},
+	{0x0115c3, 0x0},
+	{0x1115c3, 0x0},
+	{0x2115c3, 0x0},
+	{0x0116c3, 0x0},
+	{0x1116c3, 0x0},
+	{0x2116c3, 0x0},
+	{0x0117c3, 0x0},
+	{0x1117c3, 0x0},
+	{0x2117c3, 0x0},
+	{0x0118c3, 0x0},
+	{0x1118c3, 0x0},
+	{0x2118c3, 0x0},
+	{0x010020, 0x0},
+	{0x110020, 0x0},
+	{0x210020, 0x0},
+	{0x011020, 0x0},
+	{0x111020, 0x0},
+	{0x211020, 0x0},
+	{0x02007d, 0x0},
+	{0x12007d, 0x0},
+	{0x22007d, 0x0},
+	{0x010040, 0x0},
+	{0x010140, 0x0},
+	{0x010240, 0x0},
+	{0x010340, 0x0},
+	{0x010440, 0x0},
+	{0x010540, 0x0},
+	{0x010640, 0x0},
+	{0x010740, 0x0},
+	{0x010840, 0x0},
+	{0x010030, 0x0},
+	{0x010130, 0x0},
+	{0x010230, 0x0},
+	{0x010330, 0x0},
+	{0x010430, 0x0},
+	{0x010530, 0x0},
+	{0x010630, 0x0},
+	{0x010730, 0x0},
+	{0x010830, 0x0},
+	{0x011040, 0x0},
+	{0x011140, 0x0},
+	{0x011240, 0x0},
+	{0x011340, 0x0},
+	{0x011440, 0x0},
+	{0x011540, 0x0},
+	{0x011640, 0x0},
+	{0x011740, 0x0},
+	{0x011840, 0x0},
+	{0x011030, 0x0},
+	{0x011130, 0x0},
+	{0x011230, 0x0},
+	{0x011330, 0x0},
+	{0x011430, 0x0},
+	{0x011530, 0x0},
+	{0x011630, 0x0},
+	{0x011730, 0x0},
+	{0x011830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x640 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x1000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x31f },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x234 },
+	{ 0x54030, 0x105 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x410 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x1 },
+	{ 0x54003, 0x42a },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x1000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x21f },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x4 },
+	{ 0x54030, 0x105 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x10 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x640 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x1000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x61 },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400e, 0x1f7f },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x234 },
+	{ 0x54030, 0x105 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x410 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x2 },
+	{ 0x90033, 0x10 },
+	{ 0x90034, 0x139 },
+	{ 0x90035, 0xb },
+	{ 0x90036, 0x7c0 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0x44 },
+	{ 0x90039, 0x633 },
+	{ 0x9003a, 0x159 },
+	{ 0x9003b, 0x14f },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x47 },
+	{ 0x9003f, 0x633 },
+	{ 0x90040, 0x149 },
+	{ 0x90041, 0x4f },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x179 },
+	{ 0x90044, 0x8 },
+	{ 0x90045, 0xe0 },
+	{ 0x90046, 0x109 },
+	{ 0x90047, 0x0 },
+	{ 0x90048, 0x7c8 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x1 },
+	{ 0x9004c, 0x8 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x45a },
+	{ 0x9004f, 0x9 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x448 },
+	{ 0x90052, 0x109 },
+	{ 0x90053, 0x40 },
+	{ 0x90054, 0x633 },
+	{ 0x90055, 0x179 },
+	{ 0x90056, 0x1 },
+	{ 0x90057, 0x618 },
+	{ 0x90058, 0x109 },
+	{ 0x90059, 0x40c0 },
+	{ 0x9005a, 0x633 },
+	{ 0x9005b, 0x149 },
+	{ 0x9005c, 0x8 },
+	{ 0x9005d, 0x4 },
+	{ 0x9005e, 0x48 },
+	{ 0x9005f, 0x4040 },
+	{ 0x90060, 0x633 },
+	{ 0x90061, 0x149 },
+	{ 0x90062, 0x0 },
+	{ 0x90063, 0x4 },
+	{ 0x90064, 0x48 },
+	{ 0x90065, 0x40 },
+	{ 0x90066, 0x633 },
+	{ 0x90067, 0x149 },
+	{ 0x90068, 0x10 },
+	{ 0x90069, 0x4 },
+	{ 0x9006a, 0x18 },
+	{ 0x9006b, 0x0 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x78 },
+	{ 0x9006e, 0x549 },
+	{ 0x9006f, 0x633 },
+	{ 0x90070, 0x159 },
+	{ 0x90071, 0xd49 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0x94a },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x441 },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x149 },
+	{ 0x9007a, 0x42 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x1 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x0 },
+	{ 0x90081, 0xe0 },
+	{ 0x90082, 0x109 },
+	{ 0x90083, 0xa },
+	{ 0x90084, 0x10 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0x9 },
+	{ 0x90087, 0x3c0 },
+	{ 0x90088, 0x149 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x159 },
+	{ 0x9008c, 0x18 },
+	{ 0x9008d, 0x10 },
+	{ 0x9008e, 0x109 },
+	{ 0x9008f, 0x0 },
+	{ 0x90090, 0x3c0 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x18 },
+	{ 0x90093, 0x4 },
+	{ 0x90094, 0x48 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x58 },
+	{ 0x90098, 0xb },
+	{ 0x90099, 0x10 },
+	{ 0x9009a, 0x109 },
+	{ 0x9009b, 0x1 },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x5 },
+	{ 0x9009f, 0x7c0 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x0 },
+	{ 0x900a2, 0x8140 },
+	{ 0x900a3, 0x10c },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x8138 },
+	{ 0x900a6, 0x10c },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7c8 },
+	{ 0x900a9, 0x101 },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x448 },
+	{ 0x900ac, 0x109 },
+	{ 0x900ad, 0xf },
+	{ 0x900ae, 0x7c0 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x47 },
+	{ 0x900b1, 0x630 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x8 },
+	{ 0x900b4, 0x618 },
+	{ 0x900b5, 0x109 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0xe0 },
+	{ 0x900b8, 0x109 },
+	{ 0x900b9, 0x0 },
+	{ 0x900ba, 0x7c8 },
+	{ 0x900bb, 0x109 },
+	{ 0x900bc, 0x8 },
+	{ 0x900bd, 0x8140 },
+	{ 0x900be, 0x10c },
+	{ 0x900bf, 0x0 },
+	{ 0x900c0, 0x1 },
+	{ 0x900c1, 0x8 },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x8 },
+	{ 0x900c5, 0x8 },
+	{ 0x900c6, 0x7c8 },
+	{ 0x900c7, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x90026, 0x2b },
+	{ 0x2000b, 0x32 },
+	{ 0x2000c, 0x64 },
+	{ 0x2000d, 0x3e8 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x21 },
+	{ 0x12000c, 0x42 },
+	{ 0x12000d, 0x29a },
+	{ 0x12000e, 0x21 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0xffff },
+	{ 0x90013, 0x6152 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x0 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 1600mts 1D */
+		.drate = 1600,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 1066mts 1D */
+		.drate = 1066,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P0 1600mts 2D */
+		.drate = 1600,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 1600, 1066, },
+};
diff --git a/board/freescale/imx8mm_ab2/imx8mm_ab2.c b/board/freescale/imx8mm_ab2/imx8mm_ab2.c
new file mode 100644
index 00000000000..e788bff3e1c
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/imx8mm_ab2.c
@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <power/regulator.h>
+#if defined(CONFIG_IMX8MM)
+#include <asm/arch/imx8mm_pins.h>
+#else
+#include <asm/arch/imx8mn_pins.h>
+#endif
+#include <asm/global_data.h>
+#include <asm/arch/sys_proto.h>
+#include <asm-generic/gpio.h>
+#include <asm/mach-imx/dma.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <spl.h>
+#include <usb.h>
+#include "../common/tcpc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PWR_EN_5V0	IMX_GPIO_NR(1, 7)
+#define PWR_EN_ANA	IMX_GPIO_NR(1, 10)
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+#if defined(CONFIG_IMX8MM)
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const pwr_en_5v0[] = {
+	IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const pwr_en_ana[] = {
+	IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#endif
+
+#if defined(CONFIG_IMX8MN)
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const pwr_en_5v0[] = {
+	IMX8MN_PAD_GPIO1_IO07__GPIO1_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const pwr_en_ana[] = {
+	IMX8MN_PAD_GPIO1_IO10__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#endif
+
+#ifdef CONFIG_NAND_MXS
+static void setup_gpmi_nand(void)
+{
+	init_nand_clk();
+}
+#endif
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	init_uart_clk(1);
+
+	imx_iomux_v3_setup_multiple_pads(pwr_en_5v0, ARRAY_SIZE(pwr_en_5v0));
+	gpio_request(PWR_EN_5V0, "pwr_en_5v0");
+	gpio_direction_output(PWR_EN_5V0, 1);
+
+	imx_iomux_v3_setup_multiple_pads(pwr_en_ana, ARRAY_SIZE(pwr_en_ana));
+	gpio_request(PWR_EN_ANA, "pwr_en_ana");
+	gpio_direction_output(PWR_EN_ANA, 0);
+
+	return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1],
+			IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0);
+
+	return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_TCPC
+struct tcpc_port port1;
+
+struct tcpc_port_config port1_config = {
+	.i2c_bus = 1, /* i2c2*/
+	.addr = 0x1d,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 5000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 15000,
+	.op_snk_mv = 9000,
+};
+
+static int setup_typec(void)
+{
+	int ret;
+
+	ret = tcpc_init(&port1, port1_config, NULL);
+	if (ret) {
+		printf("%s: tcpc port1 init failed, err=%d\n", __func__, ret);
+	}
+
+	return ret;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	imx8m_usb_power(index, true);
+
+	if (init == USB_INIT_HOST)
+		tcpc_setup_dfp_mode(&port1);
+	else
+		tcpc_setup_ufp_mode(&port1);
+
+	return ret;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	if (init == USB_INIT_HOST)
+		ret = tcpc_disable_src_vbus(&port1);
+
+	imx8m_usb_power(index, false);
+
+	return ret;
+}
+
+int board_ehci_usb_phy_mode(struct udevice *dev)
+{
+	enum typec_cc_polarity pol;
+	enum typec_cc_state state;
+	int ret = 0;
+
+	tcpc_setup_ufp_mode(&port1);
+	ret = tcpc_get_cc_status(&port1, &pol, &state);
+	if (!ret) {
+		if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD)
+			return USB_INIT_HOST;
+	}
+
+	return USB_INIT_DEVICE;
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_DM_REGULATOR
+	regulators_enable_boot_on(false);
+#endif
+
+#ifdef CONFIG_USB_TCPC
+	setup_typec();
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+#ifdef CONFIG_NAND_MXS
+		setup_gpmi_nand();
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
+		board_late_mmc_env_init();
+
+	if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
+		env_set("board_name", "AB2");
+
+	if (IS_ENABLED(CONFIG_IMX8MM))
+		env_set("board_rev", "iMX8MM");
+	else {
+		env_set("board_rev", "iMX8MN");
+		env_set("board", "imx8mn_ab2");
+	}
+
+	return 0;
+}
diff --git a/board/freescale/imx8mm_ab2/imximage-8mm-fspi.cfg b/board/freescale/imx8mm_ab2/imximage-8mm-fspi.cfg
new file mode 100644
index 00000000000..fcace8a93a0
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/imximage-8mm-fspi.cfg
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+BOOT_FROM	fspi
+LOADER		u-boot-spl-ddr.bin	0x7E2000
diff --git a/board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg b/board/freescale/imx8mm_ab2/imximage-8mm.cfg
index 20061521f22..20061521f22 100644
--- a/board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg
+++ b/board/freescale/imx8mm_ab2/imximage-8mm.cfg
diff --git a/board/freescale/imx8mm_ab2/imximage-8mn.cfg b/board/freescale/imx8mm_ab2/imximage-8mn.cfg
new file mode 100644
index 00000000000..0edda9c5e06
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/imximage-8mn.cfg
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+
+ROM_VERSION	v2
+BOOT_FROM	sd
+LOADER		u-boot-spl-ddr.bin	0x912000
diff --git a/board/freescale/imx8mm_ab2/lpddr4_imx8mm_som.c b/board/freescale/imx8mm_ab2/lpddr4_imx8mm_som.c
new file mode 100644
index 00000000000..664c08e718a
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/lpddr4_imx8mm_som.c
@@ -0,0 +1,1855 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/* Initialize DDRC registers */
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa1080020 },
+	{ 0x3d400020, 0x223 },
+	{ 0x3d400024, 0x16e3600 },
+	{ 0x3d400064, 0x5b00d2 },
+	{ 0x3d4000d0, 0xc00305ba },
+	{ 0x3d4000d4, 0x940000 },
+	{ 0x3d4000dc, 0xd4002d },
+	{ 0x3d4000e0, 0x310000 },
+	{ 0x3d4000e8, 0x66004d },
+	{ 0x3d4000ec, 0x16004d },
+	{ 0x3d400100, 0x191e1920 },
+	{ 0x3d400104, 0x60630 },
+	{ 0x3d40010c, 0xb0b000 },
+	{ 0x3d400110, 0xe04080e },
+	{ 0x3d400114, 0x2040c0c },
+	{ 0x3d400118, 0x1010007 },
+	{ 0x3d40011c, 0x401 },
+	{ 0x3d400130, 0x20600 },
+	{ 0x3d400134, 0xc100002 },
+	{ 0x3d400138, 0xd8 },
+	{ 0x3d400144, 0x96004b },
+	{ 0x3d400180, 0x2ee0017 },
+	{ 0x3d400184, 0x2605b8e },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x497820a },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x170a },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x0 },
+	{ 0x3d4000f4, 0xc99 },
+	{ 0x3d400108, 0x70e1617 },
+	{ 0x3d400200, 0x1f },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+
+	/* performance setting */
+	{ 0x3d400250, 0x29001701 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+
+	/* P1: 400mts */
+	{ 0x3d402020, 0x21 },
+	{ 0x3d402024, 0x30d400 },
+	{ 0x3d402050, 0x20d040 },
+	{ 0x3d402064, 0xc001c },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x310000 },
+	{ 0x3d4020e8, 0x66004d },
+	{ 0x3d4020ec, 0x16004d },
+	{ 0x3d402100, 0xa040305 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x1d },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+
+	/* p2: 100mts */
+	{ 0x3d403020, 0x21 },
+	{ 0x3d403024, 0xc3500 },
+	{ 0x3d403050, 0x20d040 },
+	{ 0x3d403064, 0x30007 },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x310000 },
+	{ 0x3d4030e8, 0x66004d },
+	{ 0x3d4030ec, 0x16004d },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x301 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0x8 },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+
+	/* default boot point */
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x3 },
+	{ 0x110a3, 0x4 },
+	{ 0x110a4, 0x5 },
+	{ 0x110a5, 0x2 },
+	{ 0x110a6, 0x7 },
+	{ 0x110a7, 0x6 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x3 },
+	{ 0x120a3, 0x2 },
+	{ 0x120a4, 0x5 },
+	{ 0x120a5, 0x4 },
+	{ 0x120a6, 0x7 },
+	{ 0x120a7, 0x6 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x2 },
+	{ 0x130a3, 0x3 },
+	{ 0x130a4, 0x4 },
+	{ 0x130a5, 0x5 },
+	{ 0x130a6, 0x6 },
+	{ 0x130a7, 0x7 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x120024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x220024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0xa },
+	{ 0x220056, 0xa },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x212049, 0xeba },
+	{ 0x212149, 0xeba },
+	{ 0x213049, 0xeba },
+	{ 0x213149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x2ee },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0xdc },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0xdc },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x200c7, 0x21 },
+	{ 0x1200c7, 0x21 },
+	{ 0x2200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x1200ca, 0x24 },
+	{ 0x2200ca, 0x24 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
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+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400d, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400d, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400d, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x1 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xf },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x630 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x630 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x630 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x630 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x630 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x630 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x630 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x630 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x630 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x630 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x630 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x630 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xa },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x2 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x623 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x623 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a7, 0x0 },
+	{ 0x900a8, 0x790 },
+	{ 0x900a9, 0x11a },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x7aa },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x10 },
+	{ 0x900ae, 0x7b2 },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0x0 },
+	{ 0x900b1, 0x7c8 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xc },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x0 },
+	{ 0x90159, 0x400 },
+	{ 0x9015a, 0x10e },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x10c },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x7c8 },
+	{ 0x90166, 0x101 },
+	{ 0x90167, 0x8 },
+	{ 0x90168, 0x0 },
+	{ 0x90169, 0x8 },
+	{ 0x9016a, 0x8 },
+	{ 0x9016b, 0x448 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0xf },
+	{ 0x9016e, 0x7c0 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x0 },
+	{ 0x90171, 0xe8 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x47 },
+	{ 0x90174, 0x630 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x618 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x8 },
+	{ 0x9017a, 0xe0 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x7c8 },
+	{ 0x9017e, 0x109 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x8140 },
+	{ 0x90181, 0x10c },
+	{ 0x90182, 0x0 },
+	{ 0x90183, 0x1 },
+	{ 0x90184, 0x8 },
+	{ 0x90185, 0x8 },
+	{ 0x90186, 0x4 },
+	{ 0x90187, 0x8 },
+	{ 0x90188, 0x8 },
+	{ 0x90189, 0x7c8 },
+	{ 0x9018a, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x2a },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x2000b, 0x5d },
+	{ 0x2000c, 0xbb },
+	{ 0x2000d, 0x753 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x120010, 0x5a },
+	{ 0x120011, 0x3 },
+	{ 0x220010, 0x5a },
+	{ 0x220011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x2003a, 0x2 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3000, 400, 100, },
+};
diff --git a/board/freescale/imx8mm_ab2/lpddr4_imx8mn_som.c b/board/freescale/imx8mm_ab2/lpddr4_imx8mn_som.c
new file mode 100644
index 00000000000..8929bc6d263
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/lpddr4_imx8mn_som.c
@@ -0,0 +1,1585 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	{0x3d400020, 0x00000213},
+	{0x3d400024, 0x0003e800},
+	{0x3d400030, 0x00000120},
+	{0x3d400000, 0xa3080020},
+	{0x3d400064, 0x006100e0},
+	{0x3d4000d0, 0xc003061c},
+	{0x3d4000d4, 0x009e0000},
+	{0x3d4000dc, 0x00d4002d},
+	{0x3d4000e0, 0x00310000},
+	{0x3d4000e8, 0x0066004d},
+	{0x3d4000ec, 0x0016004a},
+	{0x3d400100, 0x1a201b22},
+	{0x3d400104, 0x00060633},
+	{0x3d40010c, 0x00c0c000},
+	{0x3d400110, 0x0f04080f},
+	{0x3d400114, 0x02040c0c},
+	{0x3d400118, 0x01010007},
+	{0x3d40011c, 0x00000401},
+	{0x3d400130, 0x00020600},
+	{0x3d400134, 0x0c100002},
+	{0x3d400138, 0x000000e6},
+	{0x3d400144, 0x00a00050},
+	{0x3d400180, 0x03200018},
+	{0x3d400184, 0x028061a8},
+	{0x3d400188, 0x00000000},
+	{0x3d400190, 0x0497820a},
+	{0x3d4001b4, 0x0000170a},
+	{0x3d400108, 0x070e1617},
+	{0x3d4001c0, 0x00000001},
+	{0x3d400194, 0x00080303},
+	{0x3d4001a0, 0xe0400018},
+	{0x3d4001a4, 0x00df00e4},
+	{0x3d4001a8, 0x80000000},
+	{0x3d4001b0, 0x00000011},
+	{0x3d4001c4, 0x00000001},
+	{0x3d4000f4, 0x00000c99},
+	{0x3d400200, 0x00000017},
+	{0x3d400204, 0x00080808},
+	{0x3d400208, 0x00000000},
+	{0x3d40020c, 0x00000000},
+	{0x3d400210, 0x00001f1f},
+	{0x3d400214, 0x07070707},
+	{0x3d400218, 0x07070707},
+	{0x3d40021c, 0x00000f0f},
+	{0x3d400250, 0x29001701},
+	{0x3d400254, 0x0000002c},
+	{0x3d40025c, 0x04000030},
+	{0x3d400264, 0x900093e7},
+	{0x3d40026c, 0x20005574},
+	{0x3d400400, 0x00000111},
+	{0x3d400408, 0x000072ff},
+	{0x3d400494, 0x02100e07},
+	{0x3d400498, 0x00620096},
+	{0x3d40049c, 0x01100e07},
+	{0x3d4004a0, 0x00c8012c},
+	{0x3d402020, 0x00000011},
+	{0x3d402024, 0x00007d00},
+	{0x3d402050, 0x0020d040},
+	{0x3d402064, 0x000c001d},
+	{0x3d4020f4, 0x00000c99},
+	{0x3d402100, 0x0a040305},
+	{0x3d402104, 0x00030407},
+	{0x3d402108, 0x0203060b},
+	{0x3d40210c, 0x00505000},
+	{0x3d402110, 0x02040202},
+	{0x3d402114, 0x02030202},
+	{0x3d402118, 0x01010004},
+	{0x3d40211c, 0x00000301},
+	{0x3d402130, 0x00020300},
+	{0x3d402134, 0x0a100002},
+	{0x3d402138, 0x0000001d},
+	{0x3d402144, 0x0014000a},
+	{0x3d402180, 0x00650004},
+	{0x3d402190, 0x03818200},
+	{0x3d402194, 0x00080303},
+	{0x3d4021b4, 0x00000100},
+	{0x3d4020dc, 0x00840000},
+	{0x3d4020e0, 0x00310000},
+	{0x3d4020e8, 0x0066004d},
+	{0x3d4020ec, 0x0016004a},
+	{0x3d403020, 0x00000011},
+	{0x3d403024, 0x00001f40},
+	{0x3d403050, 0x0020d040},
+	{0x3d403064, 0x00030007},
+	{0x3d4030f4, 0x00000c99},
+	{0x3d403100, 0x0a010102},
+	{0x3d403104, 0x00030404},
+	{0x3d403108, 0x0203060b},
+	{0x3d40310c, 0x00505000},
+	{0x3d403110, 0x02040202},
+	{0x3d403114, 0x02030202},
+	{0x3d403118, 0x01010004},
+	{0x3d40311c, 0x00000301},
+	{0x3d403130, 0x00020300},
+	{0x3d403134, 0x0a100002},
+	{0x3d403138, 0x00000008},
+	{0x3d403144, 0x00050003},
+	{0x3d403180, 0x00190004},
+	{0x3d403190, 0x03818200},
+	{0x3d403194, 0x00080303},
+	{0x3d4031b4, 0x00000100},
+	{0x3d4030dc, 0x00840000},
+	{0x3d4030e0, 0x00310000},
+	{0x3d4030e8, 0x0066004d},
+	{0x3d4030ec, 0x0016004a},
+
+	/* default boot point */
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x000100a0, 0x00000000},
+	{0x000100a1, 0x00000001},
+	{0x000100a2, 0x00000002},
+	{0x000100a3, 0x00000003},
+	{0x000100a4, 0x00000004},
+	{0x000100a5, 0x00000005},
+	{0x000100a6, 0x00000006},
+	{0x000100a7, 0x00000007},
+	{0x000110a0, 0x00000000},
+	{0x000110a1, 0x00000001},
+	{0x000110a2, 0x00000003},
+	{0x000110a3, 0x00000004},
+	{0x000110a4, 0x00000005},
+	{0x000110a5, 0x00000002},
+	{0x000110a6, 0x00000007},
+	{0x000110a7, 0x00000006},
+	{0x0001005f, 0x0000015f},
+	{0x0001015f, 0x0000015f},
+	{0x0001105f, 0x0000015f},
+	{0x0001115f, 0x0000015f},
+	{0x0011005f, 0x0000015f},
+	{0x0011015f, 0x0000015f},
+	{0x0011105f, 0x0000015f},
+	{0x0011115f, 0x0000015f},
+	{0x0021005f, 0x0000015f},
+	{0x0021015f, 0x0000015f},
+	{0x0021105f, 0x0000015f},
+	{0x0021115f, 0x0000015f},
+	{0x00000055, 0x0000016f},
+	{0x00001055, 0x0000016f},
+	{0x00002055, 0x0000016f},
+	{0x00003055, 0x0000016f},
+	{0x00004055, 0x0000016f},
+	{0x00005055, 0x0000016f},
+	{0x00006055, 0x0000016f},
+	{0x00007055, 0x0000016f},
+	{0x00008055, 0x0000016f},
+	{0x00009055, 0x0000016f},
+	{0x000200c5, 0x00000019},
+	{0x001200c5, 0x00000007},
+	{0x002200c5, 0x00000007},
+	{0x0002002e, 0x00000002},
+	{0x0012002e, 0x00000002},
+	{0x0022002e, 0x00000002},
+	{0x00090204, 0x00000000},
+	{0x00190204, 0x00000000},
+	{0x00290204, 0x00000000},
+	{0x00020024, 0x000001a3},
+	{0x0002003a, 0x00000002},
+	{0x0002007d, 0x00000212},
+	{0x0002007c, 0x00000061},
+	{0x00120024, 0x000001a3},
+	{0x0002003a, 0x00000002},
+	{0x0012007d, 0x00000212},
+	{0x0012007c, 0x00000061},
+	{0x00220024, 0x000001a3},
+	{0x0002003a, 0x00000002},
+	{0x0022007d, 0x00000212},
+	{0x0022007c, 0x00000061},
+	{0x00020056, 0x00000003},
+	{0x00120056, 0x00000003},
+	{0x00220056, 0x00000003},
+	{0x0001004d, 0x00000f80},
+	{0x0001014d, 0x00000f80},
+	{0x0001104d, 0x00000f80},
+	{0x0001114d, 0x00000f80},
+	{0x0011004d, 0x00000f80},
+	{0x0011014d, 0x00000f80},
+	{0x0011104d, 0x00000f80},
+	{0x0011114d, 0x00000f80},
+	{0x0021004d, 0x00000f80},
+	{0x0021014d, 0x00000f80},
+	{0x0021104d, 0x00000f80},
+	{0x0021114d, 0x00000f80},
+	{0x00010049, 0x00000fbe},
+	{0x00010149, 0x00000fbe},
+	{0x00011049, 0x00000fbe},
+	{0x00011149, 0x00000fbe},
+	{0x00110049, 0x00000fbe},
+	{0x00110149, 0x00000fbe},
+	{0x00111049, 0x00000fbe},
+	{0x00111149, 0x00000fbe},
+	{0x00210049, 0x00000fbe},
+	{0x00210149, 0x00000fbe},
+	{0x00211049, 0x00000fbe},
+	{0x00211149, 0x00000fbe},
+	{0x00000043, 0x00000063},
+	{0x00001043, 0x00000063},
+	{0x00002043, 0x00000063},
+	{0x00003043, 0x00000063},
+	{0x00004043, 0x00000063},
+	{0x00005043, 0x00000063},
+	{0x00006043, 0x00000063},
+	{0x00007043, 0x00000063},
+	{0x00008043, 0x00000063},
+	{0x00009043, 0x00000063},
+	{0x00020018, 0x00000001},
+	{0x00020075, 0x00000004},
+	{0x00020050, 0x00000000},
+	{0x00020008, 0x00000320},
+	{0x00120008, 0x00000064},
+	{0x00220008, 0x00000019},
+	{0x00020088, 0x00000009},
+	{0x000200b2, 0x000000dc},
+	{0x00010043, 0x000005a1},
+	{0x00010143, 0x000005a1},
+	{0x00011043, 0x000005a1},
+	{0x00011143, 0x000005a1},
+	{0x001200b2, 0x000000dc},
+	{0x00110043, 0x000005a1},
+	{0x00110143, 0x000005a1},
+	{0x00111043, 0x000005a1},
+	{0x00111143, 0x000005a1},
+	{0x002200b2, 0x000000dc},
+	{0x00210043, 0x000005a1},
+	{0x00210143, 0x000005a1},
+	{0x00211043, 0x000005a1},
+	{0x00211143, 0x000005a1},
+	{0x000200fa, 0x00000001},
+	{0x001200fa, 0x00000001},
+	{0x002200fa, 0x00000001},
+	{0x00020019, 0x00000001},
+	{0x00120019, 0x00000001},
+	{0x00220019, 0x00000001},
+	{0x000200f0, 0x00000660},
+	{0x000200f1, 0x00000000},
+	{0x000200f2, 0x00004444},
+	{0x000200f3, 0x00008888},
+	{0x000200f4, 0x00005665},
+	{0x000200f5, 0x00000000},
+	{0x000200f6, 0x00000000},
+	{0x000200f7, 0x0000f000},
+	{0x0001004a, 0x00000500},
+	{0x0001104a, 0x00000500},
+	{0x00020025, 0x00000000},
+	{0x0002002d, 0x00000000},
+	{0x0012002d, 0x00000000},
+	{0x0022002d, 0x00000000},
+	{0x0002002c, 0x00000000},
+	{0x000200c7, 0x00000021},
+	{0x000200ca, 0x00000024},
+	{0x000200cc, 0x000001f7},
+	{0x001200c7, 0x00000021},
+	{0x001200ca, 0x00000024},
+	{0x001200cc, 0x000001f7},
+	{0x002200c7, 0x00000021},
+	{0x002200ca, 0x00000024},
+	{0x002200cc, 0x000001f7},
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{0x0200b2, 0x0},
+	{0x1200b2, 0x0},
+	{0x2200b2, 0x0},
+	{0x0200cb, 0x0},
+	{0x010043, 0x0},
+	{0x110043, 0x0},
+	{0x210043, 0x0},
+	{0x010143, 0x0},
+	{0x110143, 0x0},
+	{0x210143, 0x0},
+	{0x011043, 0x0},
+	{0x111043, 0x0},
+	{0x211043, 0x0},
+	{0x011143, 0x0},
+	{0x111143, 0x0},
+	{0x211143, 0x0},
+	{0x000080, 0x0},
+	{0x100080, 0x0},
+	{0x200080, 0x0},
+	{0x001080, 0x0},
+	{0x101080, 0x0},
+	{0x201080, 0x0},
+	{0x002080, 0x0},
+	{0x102080, 0x0},
+	{0x202080, 0x0},
+	{0x003080, 0x0},
+	{0x103080, 0x0},
+	{0x203080, 0x0},
+	{0x004080, 0x0},
+	{0x104080, 0x0},
+	{0x204080, 0x0},
+	{0x005080, 0x0},
+	{0x105080, 0x0},
+	{0x205080, 0x0},
+	{0x006080, 0x0},
+	{0x106080, 0x0},
+	{0x206080, 0x0},
+	{0x007080, 0x0},
+	{0x107080, 0x0},
+	{0x207080, 0x0},
+	{0x008080, 0x0},
+	{0x108080, 0x0},
+	{0x208080, 0x0},
+	{0x009080, 0x0},
+	{0x109080, 0x0},
+	{0x209080, 0x0},
+	{0x010080, 0x0},
+	{0x110080, 0x0},
+	{0x210080, 0x0},
+	{0x010180, 0x0},
+	{0x110180, 0x0},
+	{0x210180, 0x0},
+	{0x011080, 0x0},
+	{0x111080, 0x0},
+	{0x211080, 0x0},
+	{0x011180, 0x0},
+	{0x111180, 0x0},
+	{0x211180, 0x0},
+	{0x010081, 0x0},
+	{0x110081, 0x0},
+	{0x210081, 0x0},
+	{0x010181, 0x0},
+	{0x110181, 0x0},
+	{0x210181, 0x0},
+	{0x011081, 0x0},
+	{0x111081, 0x0},
+	{0x211081, 0x0},
+	{0x011181, 0x0},
+	{0x111181, 0x0},
+	{0x211181, 0x0},
+	{0x0100d0, 0x0},
+	{0x1100d0, 0x0},
+	{0x2100d0, 0x0},
+	{0x0101d0, 0x0},
+	{0x1101d0, 0x0},
+	{0x2101d0, 0x0},
+	{0x0110d0, 0x0},
+	{0x1110d0, 0x0},
+	{0x2110d0, 0x0},
+	{0x0111d0, 0x0},
+	{0x1111d0, 0x0},
+	{0x2111d0, 0x0},
+	{0x0100d1, 0x0},
+	{0x1100d1, 0x0},
+	{0x2100d1, 0x0},
+	{0x0101d1, 0x0},
+	{0x1101d1, 0x0},
+	{0x2101d1, 0x0},
+	{0x0110d1, 0x0},
+	{0x1110d1, 0x0},
+	{0x2110d1, 0x0},
+	{0x0111d1, 0x0},
+	{0x1111d1, 0x0},
+	{0x2111d1, 0x0},
+	{0x010068, 0x0},
+	{0x010168, 0x0},
+	{0x010268, 0x0},
+	{0x010368, 0x0},
+	{0x010468, 0x0},
+	{0x010568, 0x0},
+	{0x010668, 0x0},
+	{0x010768, 0x0},
+	{0x010868, 0x0},
+	{0x011068, 0x0},
+	{0x011168, 0x0},
+	{0x011268, 0x0},
+	{0x011368, 0x0},
+	{0x011468, 0x0},
+	{0x011568, 0x0},
+	{0x011668, 0x0},
+	{0x011768, 0x0},
+	{0x011868, 0x0},
+	{0x010069, 0x0},
+	{0x010169, 0x0},
+	{0x010269, 0x0},
+	{0x010369, 0x0},
+	{0x010469, 0x0},
+	{0x010569, 0x0},
+	{0x010669, 0x0},
+	{0x010769, 0x0},
+	{0x010869, 0x0},
+	{0x011069, 0x0},
+	{0x011169, 0x0},
+	{0x011269, 0x0},
+	{0x011369, 0x0},
+	{0x011469, 0x0},
+	{0x011569, 0x0},
+	{0x011669, 0x0},
+	{0x011769, 0x0},
+	{0x011869, 0x0},
+	{0x01008c, 0x0},
+	{0x11008c, 0x0},
+	{0x21008c, 0x0},
+	{0x01018c, 0x0},
+	{0x11018c, 0x0},
+	{0x21018c, 0x0},
+	{0x01108c, 0x0},
+	{0x11108c, 0x0},
+	{0x21108c, 0x0},
+	{0x01118c, 0x0},
+	{0x11118c, 0x0},
+	{0x21118c, 0x0},
+	{0x01008d, 0x0},
+	{0x11008d, 0x0},
+	{0x21008d, 0x0},
+	{0x01018d, 0x0},
+	{0x11018d, 0x0},
+	{0x21018d, 0x0},
+	{0x01108d, 0x0},
+	{0x11108d, 0x0},
+	{0x21108d, 0x0},
+	{0x01118d, 0x0},
+	{0x11118d, 0x0},
+	{0x21118d, 0x0},
+	{0x0100c0, 0x0},
+	{0x1100c0, 0x0},
+	{0x2100c0, 0x0},
+	{0x0101c0, 0x0},
+	{0x1101c0, 0x0},
+	{0x2101c0, 0x0},
+	{0x0102c0, 0x0},
+	{0x1102c0, 0x0},
+	{0x2102c0, 0x0},
+	{0x0103c0, 0x0},
+	{0x1103c0, 0x0},
+	{0x2103c0, 0x0},
+	{0x0104c0, 0x0},
+	{0x1104c0, 0x0},
+	{0x2104c0, 0x0},
+	{0x0105c0, 0x0},
+	{0x1105c0, 0x0},
+	{0x2105c0, 0x0},
+	{0x0106c0, 0x0},
+	{0x1106c0, 0x0},
+	{0x2106c0, 0x0},
+	{0x0107c0, 0x0},
+	{0x1107c0, 0x0},
+	{0x2107c0, 0x0},
+	{0x0108c0, 0x0},
+	{0x1108c0, 0x0},
+	{0x2108c0, 0x0},
+	{0x0110c0, 0x0},
+	{0x1110c0, 0x0},
+	{0x2110c0, 0x0},
+	{0x0111c0, 0x0},
+	{0x1111c0, 0x0},
+	{0x2111c0, 0x0},
+	{0x0112c0, 0x0},
+	{0x1112c0, 0x0},
+	{0x2112c0, 0x0},
+	{0x0113c0, 0x0},
+	{0x1113c0, 0x0},
+	{0x2113c0, 0x0},
+	{0x0114c0, 0x0},
+	{0x1114c0, 0x0},
+	{0x2114c0, 0x0},
+	{0x0115c0, 0x0},
+	{0x1115c0, 0x0},
+	{0x2115c0, 0x0},
+	{0x0116c0, 0x0},
+	{0x1116c0, 0x0},
+	{0x2116c0, 0x0},
+	{0x0117c0, 0x0},
+	{0x1117c0, 0x0},
+	{0x2117c0, 0x0},
+	{0x0118c0, 0x0},
+	{0x1118c0, 0x0},
+	{0x2118c0, 0x0},
+	{0x0100c1, 0x0},
+	{0x1100c1, 0x0},
+	{0x2100c1, 0x0},
+	{0x0101c1, 0x0},
+	{0x1101c1, 0x0},
+	{0x2101c1, 0x0},
+	{0x0102c1, 0x0},
+	{0x1102c1, 0x0},
+	{0x2102c1, 0x0},
+	{0x0103c1, 0x0},
+	{0x1103c1, 0x0},
+	{0x2103c1, 0x0},
+	{0x0104c1, 0x0},
+	{0x1104c1, 0x0},
+	{0x2104c1, 0x0},
+	{0x0105c1, 0x0},
+	{0x1105c1, 0x0},
+	{0x2105c1, 0x0},
+	{0x0106c1, 0x0},
+	{0x1106c1, 0x0},
+	{0x2106c1, 0x0},
+	{0x0107c1, 0x0},
+	{0x1107c1, 0x0},
+	{0x2107c1, 0x0},
+	{0x0108c1, 0x0},
+	{0x1108c1, 0x0},
+	{0x2108c1, 0x0},
+	{0x0110c1, 0x0},
+	{0x1110c1, 0x0},
+	{0x2110c1, 0x0},
+	{0x0111c1, 0x0},
+	{0x1111c1, 0x0},
+	{0x2111c1, 0x0},
+	{0x0112c1, 0x0},
+	{0x1112c1, 0x0},
+	{0x2112c1, 0x0},
+	{0x0113c1, 0x0},
+	{0x1113c1, 0x0},
+	{0x2113c1, 0x0},
+	{0x0114c1, 0x0},
+	{0x1114c1, 0x0},
+	{0x2114c1, 0x0},
+	{0x0115c1, 0x0},
+	{0x1115c1, 0x0},
+	{0x2115c1, 0x0},
+	{0x0116c1, 0x0},
+	{0x1116c1, 0x0},
+	{0x2116c1, 0x0},
+	{0x0117c1, 0x0},
+	{0x1117c1, 0x0},
+	{0x2117c1, 0x0},
+	{0x0118c1, 0x0},
+	{0x1118c1, 0x0},
+	{0x2118c1, 0x0},
+	{0x010020, 0x0},
+	{0x110020, 0x0},
+	{0x210020, 0x0},
+	{0x011020, 0x0},
+	{0x111020, 0x0},
+	{0x211020, 0x0},
+	{0x020072, 0x0},
+	{0x020073, 0x0},
+	{0x020074, 0x0},
+	{0x0100aa, 0x0},
+	{0x0110aa, 0x0},
+	{0x020010, 0x0},
+	{0x120010, 0x0},
+	{0x220010, 0x0},
+	{0x020011, 0x0},
+	{0x120011, 0x0},
+	{0x220011, 0x0},
+	{0x0100ae, 0x0},
+	{0x1100ae, 0x0},
+	{0x2100ae, 0x0},
+	{0x0100af, 0x0},
+	{0x1100af, 0x0},
+	{0x2100af, 0x0},
+	{0x0110ae, 0x0},
+	{0x1110ae, 0x0},
+	{0x2110ae, 0x0},
+	{0x0110af, 0x0},
+	{0x1110af, 0x0},
+	{0x2110af, 0x0},
+	{0x020020, 0x0},
+	{0x120020, 0x0},
+	{0x220020, 0x0},
+	{0x0100a0, 0x0},
+	{0x0100a1, 0x0},
+	{0x0100a2, 0x0},
+	{0x0100a3, 0x0},
+	{0x0100a4, 0x0},
+	{0x0100a5, 0x0},
+	{0x0100a6, 0x0},
+	{0x0100a7, 0x0},
+	{0x0110a0, 0x0},
+	{0x0110a1, 0x0},
+	{0x0110a2, 0x0},
+	{0x0110a3, 0x0},
+	{0x0110a4, 0x0},
+	{0x0110a5, 0x0},
+	{0x0110a6, 0x0},
+	{0x0110a7, 0x0},
+	{0x02007c, 0x0},
+	{0x12007c, 0x0},
+	{0x22007c, 0x0},
+	{0x02007d, 0x0},
+	{0x12007d, 0x0},
+	{0x22007d, 0x0},
+	{0x0400fd, 0x0},
+	{0x0400c0, 0x0},
+	{0x090201, 0x0},
+	{0x190201, 0x0},
+	{0x290201, 0x0},
+	{0x090202, 0x0},
+	{0x190202, 0x0},
+	{0x290202, 0x0},
+	{0x090203, 0x0},
+	{0x190203, 0x0},
+	{0x290203, 0x0},
+	{0x090204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x090205, 0x0},
+	{0x190205, 0x0},
+	{0x290205, 0x0},
+	{0x090206, 0x0},
+	{0x190206, 0x0},
+	{0x290206, 0x0},
+	{0x090207, 0x0},
+	{0x190207, 0x0},
+	{0x290207, 0x0},
+	{0x090208, 0x0},
+	{0x190208, 0x0},
+	{0x290208, 0x0},
+	{0x010062, 0x0},
+	{0x010162, 0x0},
+	{0x010262, 0x0},
+	{0x010362, 0x0},
+	{0x010462, 0x0},
+	{0x010562, 0x0},
+	{0x010662, 0x0},
+	{0x010762, 0x0},
+	{0x010862, 0x0},
+	{0x011062, 0x0},
+	{0x011162, 0x0},
+	{0x011262, 0x0},
+	{0x011362, 0x0},
+	{0x011462, 0x0},
+	{0x011562, 0x0},
+	{0x011662, 0x0},
+	{0x011762, 0x0},
+	{0x011862, 0x0},
+	{0x020077, 0x0},
+	{0x010001, 0x0},
+	{0x011001, 0x0},
+	{0x010040, 0x0},
+	{0x010140, 0x0},
+	{0x010240, 0x0},
+	{0x010340, 0x0},
+	{0x010440, 0x0},
+	{0x010540, 0x0},
+	{0x010640, 0x0},
+	{0x010740, 0x0},
+	{0x010840, 0x0},
+	{0x010030, 0x0},
+	{0x010130, 0x0},
+	{0x010230, 0x0},
+	{0x010330, 0x0},
+	{0x010430, 0x0},
+	{0x010530, 0x0},
+	{0x010630, 0x0},
+	{0x010730, 0x0},
+	{0x010830, 0x0},
+	{0x011040, 0x0},
+	{0x011140, 0x0},
+	{0x011240, 0x0},
+	{0x011340, 0x0},
+	{0x011440, 0x0},
+	{0x011540, 0x0},
+	{0x011640, 0x0},
+	{0x011740, 0x0},
+	{0x011840, 0x0},
+	{0x011030, 0x0},
+	{0x011130, 0x0},
+	{0x011230, 0x0},
+	{0x011330, 0x0},
+	{0x011430, 0x0},
+	{0x011530, 0x0},
+	{0x011630, 0x0},
+	{0x011730, 0x0},
+	{0x011830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0x000d0000, 0x00000000},
+	{0x00054000, 0x00000000},
+	{0x00054001, 0x00000000},
+	{0x00054002, 0x00000000},
+	{0x00054003, 0x00000c80},
+	{0x00054004, 0x00000002},
+	{0x00054005, 0x00000000},
+	{0x00054006, 0x00000011},
+	{0x00054007, 0x00000000},
+	{0x00054008, 0x0000131f},
+	{0x00054009, 0x000000c8},
+	{0x0005400a, 0x00000000},
+	{0x0005400b, 0x00000002},
+	{0x0005400c, 0x00000000},
+	{0x0005400d, 0x00000000},
+	{0x0005400e, 0x00000000},
+	{0x0005400f, 0x00000100},
+	{0x00054010, 0x00000000},
+	{0x00054011, 0x00000000},
+	{0x00054012, 0x00000310},
+	{0x00054013, 0x00000000},
+	{0x00054014, 0x00000000},
+	{0x00054015, 0x00000000},
+	{0x00054016, 0x00000000},
+	{0x00054017, 0x00000000},
+	{0x00054018, 0x00000000},
+	{0x00054019, 0x00002dd4},
+	{0x0005401a, 0x00000031},
+	{0x0005401b, 0x00004d66},
+	{0x0005401c, 0x00004a00},
+	{0x0005401d, 0x00000000},
+	{0x0005401e, 0x00000016},
+	{0x0005401f, 0x00002dd4},
+	{0x00054020, 0x00000031},
+	{0x00054021, 0x00004d66},
+	{0x00054022, 0x00004a00},
+	{0x00054023, 0x00000000},
+	{0x00054024, 0x0000002e},
+	{0x00054025, 0x00000000},
+	{0x00054026, 0x00000000},
+	{0x00054027, 0x00000000},
+	{0x00054028, 0x00000000},
+	{0x00054029, 0x00000000},
+	{0x0005402a, 0x00000000},
+	{0x0005402b, 0x00000000},
+	{0x0005402c, 0x00000000},
+	{0x0005402d, 0x00000000},
+	{0x0005402e, 0x00000000},
+	{0x0005402f, 0x00000000},
+	{0x00054030, 0x00000000},
+	{0x00054031, 0x00000000},
+	{0x00054032, 0x0000d400},
+	{0x00054033, 0x0000312d},
+	{0x00054034, 0x00006600},
+	{0x00054035, 0x0000004d},
+	{0x00054036, 0x0000004a},
+	{0x00054037, 0x00001600},
+	{0x00054038, 0x0000d400},
+	{0x00054039, 0x0000312d},
+	{0x0005403a, 0x00006600},
+	{0x0005403b, 0x0000004d},
+	{0x0005403c, 0x0000004a},
+	{0x0005403d, 0x00002e00},
+	{0x0005403e, 0x00000000},
+	{0x0005403f, 0x00000000},
+	{0x00054040, 0x00000000},
+	{0x00054041, 0x00000000},
+	{0x00054042, 0x00000000},
+	{0x00054043, 0x00000000},
+	{0x00054044, 0x00000000},
+	{0x000d0000, 0x00000001},
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0x000d0000, 0x00000000},
+	{0x00054000, 0x00000000},
+	{0x00054001, 0x00000000},
+	{0x00054002, 0x00000101},
+	{0x00054003, 0x00000190},
+	{0x00054004, 0x00000002},
+	{0x00054005, 0x00000000},
+	{0x00054006, 0x00000011},
+	{0x00054007, 0x00000000},
+	{0x00054008, 0x0000121f},
+	{0x00054009, 0x000000c8},
+	{0x0005400a, 0x00000000},
+	{0x0005400b, 0x00000002},
+	{0x0005400c, 0x00000000},
+	{0x0005400d, 0x00000000},
+	{0x0005400e, 0x00000000},
+	{0x0005400f, 0x00000100},
+	{0x00054010, 0x00000000},
+	{0x00054011, 0x00000000},
+	{0x00054012, 0x00000310},
+	{0x00054013, 0x00000000},
+	{0x00054014, 0x00000000},
+	{0x00054015, 0x00000000},
+	{0x00054016, 0x00000000},
+	{0x00054017, 0x00000000},
+	{0x00054018, 0x00000000},
+	{0x00054019, 0x00000084},
+	{0x0005401a, 0x00000031},
+	{0x0005401b, 0x00004d66},
+	{0x0005401c, 0x00004a00},
+	{0x0005401d, 0x00000000},
+	{0x0005401e, 0x00000016},
+	{0x0005401f, 0x00000084},
+	{0x00054020, 0x00000031},
+	{0x00054021, 0x00004d66},
+	{0x00054022, 0x00004a00},
+	{0x00054023, 0x00000000},
+	{0x00054024, 0x0000002e},
+	{0x00054025, 0x00000000},
+	{0x00054026, 0x00000000},
+	{0x00054027, 0x00000000},
+	{0x00054028, 0x00000000},
+	{0x00054029, 0x00000000},
+	{0x0005402a, 0x00000000},
+	{0x0005402b, 0x00000000},
+	{0x0005402c, 0x00000000},
+	{0x0005402d, 0x00000000},
+	{0x0005402e, 0x00000000},
+	{0x0005402f, 0x00000000},
+	{0x00054030, 0x00000000},
+	{0x00054031, 0x00000000},
+	{0x00054032, 0x00008400},
+	{0x00054033, 0x00003100},
+	{0x00054034, 0x00006600},
+	{0x00054035, 0x0000004d},
+	{0x00054036, 0x0000004a},
+	{0x00054037, 0x00001600},
+	{0x00054038, 0x00008400},
+	{0x00054039, 0x00003100},
+	{0x0005403a, 0x00006600},
+	{0x0005403b, 0x0000004d},
+	{0x0005403c, 0x0000004a},
+	{0x0005403d, 0x00002e00},
+	{0x0005403e, 0x00000000},
+	{0x0005403f, 0x00000000},
+	{0x00054040, 0x00000000},
+	{0x00054041, 0x00000000},
+	{0x00054042, 0x00000000},
+	{0x00054043, 0x00000000},
+	{0x00054044, 0x00000000},
+	{0x000d0000, 0x00000001},
+};
+
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{0x000d0000, 0x00000000},
+	{0x00054000, 0x00000000},
+	{0x00054001, 0x00000000},
+	{0x00054002, 0x00000102},
+	{0x00054003, 0x00000064},
+	{0x00054004, 0x00000002},
+	{0x00054005, 0x00000000},
+	{0x00054006, 0x00000011},
+	{0x00054007, 0x00000000},
+	{0x00054008, 0x0000121f},
+	{0x00054009, 0x000000c8},
+	{0x0005400a, 0x00000000},
+	{0x0005400b, 0x00000002},
+	{0x0005400c, 0x00000000},
+	{0x0005400d, 0x00000000},
+	{0x0005400e, 0x00000000},
+	{0x0005400f, 0x00000100},
+	{0x00054010, 0x00000000},
+	{0x00054011, 0x00000000},
+	{0x00054012, 0x00000310},
+	{0x00054013, 0x00000000},
+	{0x00054014, 0x00000000},
+	{0x00054015, 0x00000000},
+	{0x00054016, 0x00000000},
+	{0x00054017, 0x00000000},
+	{0x00054018, 0x00000000},
+	{0x00054019, 0x00000084},
+	{0x0005401a, 0x00000031},
+	{0x0005401b, 0x00004d66},
+	{0x0005401c, 0x00004a00},
+	{0x0005401d, 0x00000000},
+	{0x0005401e, 0x00000016},
+	{0x0005401f, 0x00000084},
+	{0x00054020, 0x00000031},
+	{0x00054021, 0x00004d66},
+	{0x00054022, 0x00004a00},
+	{0x00054023, 0x00000000},
+	{0x00054024, 0x0000002e},
+	{0x00054025, 0x00000000},
+	{0x00054026, 0x00000000},
+	{0x00054027, 0x00000000},
+	{0x00054028, 0x00000000},
+	{0x00054029, 0x00000000},
+	{0x0005402a, 0x00000000},
+	{0x0005402b, 0x00000000},
+	{0x0005402c, 0x00000000},
+	{0x0005402d, 0x00000000},
+	{0x0005402e, 0x00000000},
+	{0x0005402f, 0x00000000},
+	{0x00054030, 0x00000000},
+	{0x00054031, 0x00000000},
+	{0x00054032, 0x00008400},
+	{0x00054033, 0x00003100},
+	{0x00054034, 0x00006600},
+	{0x00054035, 0x0000004d},
+	{0x00054036, 0x0000004a},
+	{0x00054037, 0x00001600},
+	{0x00054038, 0x00008400},
+	{0x00054039, 0x00003100},
+	{0x0005403a, 0x00006600},
+	{0x0005403b, 0x0000004d},
+	{0x0005403c, 0x0000004a},
+	{0x0005403d, 0x00002e00},
+	{0x0005403e, 0x00000000},
+	{0x0005403f, 0x00000000},
+	{0x00054040, 0x00000000},
+	{0x00054041, 0x00000000},
+	{0x00054042, 0x00000000},
+	{0x00054043, 0x00000000},
+	{0x00054044, 0x00000000},
+	{0x000d0000, 0x00000001},
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0x000d0000, 0x00000000},
+	{0x00054000, 0x00000000},
+	{0x00054001, 0x00000000},
+	{0x00054002, 0x00000000},
+	{0x00054003, 0x00000c80},
+	{0x00054004, 0x00000002},
+	{0x00054005, 0x00000000},
+	{0x00054006, 0x00000011},
+	{0x00054007, 0x00000000},
+	{0x00054008, 0x00000061},
+	{0x00054009, 0x000000c8},
+	{0x0005400a, 0x00000000},
+	{0x0005400b, 0x00000002},
+	{0x0005400c, 0x00000000},
+	{0x0005400d, 0x00000000},
+	{0x0005400e, 0x00000000},
+	{0x0005400f, 0x00000100},
+	{0x00054010, 0x00001f7f},
+	{0x00054011, 0x00000000},
+	{0x00054012, 0x00000310},
+	{0x00054013, 0x00000000},
+	{0x00054014, 0x00000000},
+	{0x00054015, 0x00000000},
+	{0x00054016, 0x00000000},
+	{0x00054017, 0x00000000},
+	{0x00054018, 0x00000000},
+	{0x00054019, 0x00002dd4},
+	{0x0005401a, 0x00000031},
+	{0x0005401b, 0x00004d66},
+	{0x0005401c, 0x00004a00},
+	{0x0005401d, 0x00000000},
+	{0x0005401e, 0x00000016},
+	{0x0005401f, 0x00002dd4},
+	{0x00054020, 0x00000031},
+	{0x00054021, 0x00004d66},
+	{0x00054022, 0x00004a00},
+	{0x00054023, 0x00000000},
+	{0x00054024, 0x0000002e},
+	{0x00054025, 0x00000000},
+	{0x00054026, 0x00000000},
+	{0x00054027, 0x00000000},
+	{0x00054028, 0x00000000},
+	{0x00054029, 0x00000000},
+	{0x0005402a, 0x00000000},
+	{0x0005402b, 0x00000000},
+	{0x0005402c, 0x00000000},
+	{0x0005402d, 0x00000000},
+	{0x0005402e, 0x00000000},
+	{0x0005402f, 0x00000000},
+	{0x00054030, 0x00000000},
+	{0x00054031, 0x00000000},
+	{0x00054032, 0x0000d400},
+	{0x00054033, 0x0000312d},
+	{0x00054034, 0x00006600},
+	{0x00054035, 0x0000004d},
+	{0x00054036, 0x0000004a},
+	{0x00054037, 0x00001600},
+	{0x00054038, 0x0000d400},
+	{0x00054039, 0x0000312d},
+	{0x0005403a, 0x00006600},
+	{0x0005403b, 0x0000004d},
+	{0x0005403c, 0x0000004a},
+	{0x0005403d, 0x00002e00},
+	{0x0005403e, 0x00000000},
+	{0x0005403f, 0x00000000},
+	{0x00054040, 0x00000000},
+	{0x00054041, 0x00000000},
+	{0x00054042, 0x00000000},
+	{0x00054043, 0x00000000},
+	{0x00054044, 0x00000000},
+	{0x000d0000, 0x00000001},
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xb},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x633},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x633},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x633},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x0},
+	{0x90051, 0x45a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x448},
+	{0x90055, 0x109},
+	{0x90056, 0x40},
+	{0x90057, 0x633},
+	{0x90058, 0x179},
+	{0x90059, 0x1},
+	{0x9005a, 0x618},
+	{0x9005b, 0x109},
+	{0x9005c, 0x40c0},
+	{0x9005d, 0x633},
+	{0x9005e, 0x149},
+	{0x9005f, 0x8},
+	{0x90060, 0x4},
+	{0x90061, 0x48},
+	{0x90062, 0x4040},
+	{0x90063, 0x633},
+	{0x90064, 0x149},
+	{0x90065, 0x0},
+	{0x90066, 0x4},
+	{0x90067, 0x48},
+	{0x90068, 0x40},
+	{0x90069, 0x633},
+	{0x9006a, 0x149},
+	{0x9006b, 0x10},
+	{0x9006c, 0x4},
+	{0x9006d, 0x18},
+	{0x9006e, 0x0},
+	{0x9006f, 0x4},
+	{0x90070, 0x78},
+	{0x90071, 0x549},
+	{0x90072, 0x633},
+	{0x90073, 0x159},
+	{0x90074, 0xd49},
+	{0x90075, 0x633},
+	{0x90076, 0x159},
+	{0x90077, 0x94a},
+	{0x90078, 0x633},
+	{0x90079, 0x159},
+	{0x9007a, 0x441},
+	{0x9007b, 0x633},
+	{0x9007c, 0x149},
+	{0x9007d, 0x42},
+	{0x9007e, 0x633},
+	{0x9007f, 0x149},
+	{0x90080, 0x1},
+	{0x90081, 0x633},
+	{0x90082, 0x149},
+	{0x90083, 0x0},
+	{0x90084, 0xe0},
+	{0x90085, 0x109},
+	{0x90086, 0xa},
+	{0x90087, 0x10},
+	{0x90088, 0x109},
+	{0x90089, 0x9},
+	{0x9008a, 0x3c0},
+	{0x9008b, 0x149},
+	{0x9008c, 0x9},
+	{0x9008d, 0x3c0},
+	{0x9008e, 0x159},
+	{0x9008f, 0x18},
+	{0x90090, 0x10},
+	{0x90091, 0x109},
+	{0x90092, 0x0},
+	{0x90093, 0x3c0},
+	{0x90094, 0x109},
+	{0x90095, 0x18},
+	{0x90096, 0x4},
+	{0x90097, 0x48},
+	{0x90098, 0x18},
+	{0x90099, 0x4},
+	{0x9009a, 0x58},
+	{0x9009b, 0xb},
+	{0x9009c, 0x10},
+	{0x9009d, 0x109},
+	{0x9009e, 0x1},
+	{0x9009f, 0x10},
+	{0x900a0, 0x109},
+	{0x900a1, 0x5},
+	{0x900a2, 0x7c0},
+	{0x900a3, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x625},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x625},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900a4, 0x0},
+	{0x900a5, 0x790},
+	{0x900a6, 0x11a},
+	{0x900a7, 0x8},
+	{0x900a8, 0x7aa},
+	{0x900a9, 0x2a},
+	{0x900aa, 0x10},
+	{0x900ab, 0x7b2},
+	{0x900ac, 0x2a},
+	{0x900ad, 0x0},
+	{0x900ae, 0x7c8},
+	{0x900af, 0x109},
+	{0x900b0, 0x10},
+	{0x900b1, 0x10},
+	{0x900b2, 0x109},
+	{0x900b3, 0x10},
+	{0x900b4, 0x2a8},
+	{0x900b5, 0x129},
+	{0x900b6, 0x8},
+	{0x900b7, 0x370},
+	{0x900b8, 0x129},
+	{0x900b9, 0xa},
+	{0x900ba, 0x3c8},
+	{0x900bb, 0x1a9},
+	{0x900bc, 0xc},
+	{0x900bd, 0x408},
+	{0x900be, 0x199},
+	{0x900bf, 0x14},
+	{0x900c0, 0x790},
+	{0x900c1, 0x11a},
+	{0x900c2, 0x8},
+	{0x900c3, 0x4},
+	{0x900c4, 0x18},
+	{0x900c5, 0xe},
+	{0x900c6, 0x408},
+	{0x900c7, 0x199},
+	{0x900c8, 0x8},
+	{0x900c9, 0x8568},
+	{0x900ca, 0x108},
+	{0x900cb, 0x18},
+	{0x900cc, 0x790},
+	{0x900cd, 0x16a},
+	{0x900ce, 0x8},
+	{0x900cf, 0x1d8},
+	{0x900d0, 0x169},
+	{0x900d1, 0x10},
+	{0x900d2, 0x8558},
+	{0x900d3, 0x168},
+	{0x900d4, 0x70},
+	{0x900d5, 0x788},
+	{0x900d6, 0x16a},
+	{0x900d7, 0x1ff8},
+	{0x900d8, 0x85a8},
+	{0x900d9, 0x1e8},
+	{0x900da, 0x50},
+	{0x900db, 0x798},
+	{0x900dc, 0x16a},
+	{0x900dd, 0x60},
+	{0x900de, 0x7a0},
+	{0x900df, 0x16a},
+	{0x900e0, 0x8},
+	{0x900e1, 0x8310},
+	{0x900e2, 0x168},
+	{0x900e3, 0x8},
+	{0x900e4, 0xa310},
+	{0x900e5, 0x168},
+	{0x900e6, 0xa},
+	{0x900e7, 0x408},
+	{0x900e8, 0x169},
+	{0x900e9, 0x6e},
+	{0x900ea, 0x0},
+	{0x900eb, 0x68},
+	{0x900ec, 0x0},
+	{0x900ed, 0x408},
+	{0x900ee, 0x169},
+	{0x900ef, 0x0},
+	{0x900f0, 0x8310},
+	{0x900f1, 0x168},
+	{0x900f2, 0x0},
+	{0x900f3, 0xa310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x1ff8},
+	{0x900f6, 0x85a8},
+	{0x900f7, 0x1e8},
+	{0x900f8, 0x68},
+	{0x900f9, 0x798},
+	{0x900fa, 0x16a},
+	{0x900fb, 0x78},
+	{0x900fc, 0x7a0},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x68},
+	{0x900ff, 0x790},
+	{0x90100, 0x16a},
+	{0x90101, 0x8},
+	{0x90102, 0x8b10},
+	{0x90103, 0x168},
+	{0x90104, 0x8},
+	{0x90105, 0xab10},
+	{0x90106, 0x168},
+	{0x90107, 0xa},
+	{0x90108, 0x408},
+	{0x90109, 0x169},
+	{0x9010a, 0x58},
+	{0x9010b, 0x0},
+	{0x9010c, 0x68},
+	{0x9010d, 0x0},
+	{0x9010e, 0x408},
+	{0x9010f, 0x169},
+	{0x90110, 0x0},
+	{0x90111, 0x8b10},
+	{0x90112, 0x168},
+	{0x90113, 0x1},
+	{0x90114, 0xab10},
+	{0x90115, 0x168},
+	{0x90116, 0x0},
+	{0x90117, 0x1d8},
+	{0x90118, 0x169},
+	{0x90119, 0x80},
+	{0x9011a, 0x790},
+	{0x9011b, 0x16a},
+	{0x9011c, 0x18},
+	{0x9011d, 0x7aa},
+	{0x9011e, 0x6a},
+	{0x9011f, 0xa},
+	{0x90120, 0x0},
+	{0x90121, 0x1e9},
+	{0x90122, 0x8},
+	{0x90123, 0x8080},
+	{0x90124, 0x108},
+	{0x90125, 0xf},
+	{0x90126, 0x408},
+	{0x90127, 0x169},
+	{0x90128, 0xc},
+	{0x90129, 0x0},
+	{0x9012a, 0x68},
+	{0x9012b, 0x9},
+	{0x9012c, 0x0},
+	{0x9012d, 0x1a9},
+	{0x9012e, 0x0},
+	{0x9012f, 0x408},
+	{0x90130, 0x169},
+	{0x90131, 0x0},
+	{0x90132, 0x8080},
+	{0x90133, 0x108},
+	{0x90134, 0x8},
+	{0x90135, 0x7aa},
+	{0x90136, 0x6a},
+	{0x90137, 0x0},
+	{0x90138, 0x8568},
+	{0x90139, 0x108},
+	{0x9013a, 0xb7},
+	{0x9013b, 0x790},
+	{0x9013c, 0x16a},
+	{0x9013d, 0x1f},
+	{0x9013e, 0x0},
+	{0x9013f, 0x68},
+	{0x90140, 0x8},
+	{0x90141, 0x8558},
+	{0x90142, 0x168},
+	{0x90143, 0xf},
+	{0x90144, 0x408},
+	{0x90145, 0x169},
+	{0x90146, 0xd},
+	{0x90147, 0x0},
+	{0x90148, 0x68},
+	{0x90149, 0x0},
+	{0x9014a, 0x408},
+	{0x9014b, 0x169},
+	{0x9014c, 0x0},
+	{0x9014d, 0x8558},
+	{0x9014e, 0x168},
+	{0x9014f, 0x8},
+	{0x90150, 0x3c8},
+	{0x90151, 0x1a9},
+	{0x90152, 0x3},
+	{0x90153, 0x370},
+	{0x90154, 0x129},
+	{0x90155, 0x20},
+	{0x90156, 0x2aa},
+	{0x90157, 0x9},
+	{0x90158, 0x0},
+	{0x90159, 0x400},
+	{0x9015a, 0x10e},
+	{0x9015b, 0x8},
+	{0x9015c, 0xe8},
+	{0x9015d, 0x109},
+	{0x9015e, 0x0},
+	{0x9015f, 0x8140},
+	{0x90160, 0x10c},
+	{0x90161, 0x10},
+	{0x90162, 0x8138},
+	{0x90163, 0x10c},
+	{0x90164, 0x8},
+	{0x90165, 0x7c8},
+	{0x90166, 0x101},
+	{0x90167, 0x8},
+	{0x90168, 0x448},
+	{0x90169, 0x109},
+	{0x9016a, 0xf},
+	{0x9016b, 0x7c0},
+	{0x9016c, 0x109},
+	{0x9016d, 0x0},
+	{0x9016e, 0xe8},
+	{0x9016f, 0x109},
+	{0x90170, 0x47},
+	{0x90171, 0x630},
+	{0x90172, 0x109},
+	{0x90173, 0x8},
+	{0x90174, 0x618},
+	{0x90175, 0x109},
+	{0x90176, 0x8},
+	{0x90177, 0xe0},
+	{0x90178, 0x109},
+	{0x90179, 0x0},
+	{0x9017a, 0x7c8},
+	{0x9017b, 0x109},
+	{0x9017c, 0x8},
+	{0x9017d, 0x8140},
+	{0x9017e, 0x10c},
+	{0x9017f, 0x0},
+	{0x90180, 0x1},
+	{0x90181, 0x8},
+	{0x90182, 0x8},
+	{0x90183, 0x4},
+	{0x90184, 0x8},
+	{0x90185, 0x8},
+	{0x90186, 0x7c8},
+	{0x90187, 0x101},
+	{0x90006, 0x0},
+	{0x90007, 0x0},
+	{0x90008, 0x8},
+	{0x90009, 0x0},
+	{0x9000a, 0x0},
+	{0x9000b, 0x0},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x29},
+	{0x90026, 0x6a},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x2000b, 0x64},
+	{0x2000c, 0xc8},
+	{0x2000d, 0x7d0},
+	{0x2000e, 0x2c},
+	{0x12000b, 0xc},
+	{0x12000c, 0x19},
+	{0x12000d, 0xfa},
+	{0x12000e, 0x10},
+	{0x22000b, 0x3},
+	{0x22000c, 0x6},
+	{0x22000d, 0x3e},
+	{0x22000e, 0x10},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x2060},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x140080, 0xe0},
+	{0x140081, 0x12},
+	{0x140082, 0xe0},
+	{0x140083, 0x12},
+	{0x140084, 0xe0},
+	{0x140085, 0x12},
+	{0x240080, 0xe0},
+	{0x240081, 0x12},
+	{0x240082, 0xe0},
+	{0x240083, 0x12},
+	{0x240084, 0xe0},
+	{0x240085, 0x12},
+	{0x400fd, 0xf},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x20089, 0x1},
+	{0x20088, 0x19},
+	{0xc0080, 0x2},
+	{0xd0000, 0x1},
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3200, 400, 100, },
+};
diff --git a/board/freescale/imx8mm_ab2/lpddr4_imx8mn_som_ld.c b/board/freescale/imx8mm_ab2/lpddr4_imx8mn_som_ld.c
new file mode 100644
index 00000000000..aa23c350945
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/lpddr4_imx8mn_som_ld.c
@@ -0,0 +1,1440 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa3080020 },
+	{ 0x3d400020, 0x111 },
+	{ 0x3d400024, 0x1f400 },
+	{ 0x3d400064, 0x300070 },
+	{ 0x3d4000d0, 0xc002030f },
+	{ 0x3d4000d4, 0x500000 },
+	{ 0x3d4000dc, 0xa40012 },
+	{ 0x3d4000e0, 0x310000 },
+	{ 0x3d4000e8, 0x66004d },
+	{ 0x3d4000ec, 0x16004d },
+	{ 0x3d400100, 0x10100d11 },
+	{ 0x3d400104, 0x3041a },
+	{ 0x3d40010c, 0x606000 },
+	{ 0x3d400110, 0x8040408 },
+	{ 0x3d400114, 0x2030606 },
+	{ 0x3d400118, 0x1010004 },
+	{ 0x3d40011c, 0x301 },
+	{ 0x3d400130, 0x20300 },
+	{ 0x3d400134, 0xa100002 },
+	{ 0x3d400138, 0x73 },
+	{ 0x3d400144, 0x500028 },
+	{ 0x3d400180, 0x190000c },
+	{ 0x3d400184, 0x14030d4 },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x4898204 },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x904 },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0xc99 },
+	{ 0x3d400108, 0x4070f0f },
+	{ 0x3d400200, 0x17 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d400250, 0x29001701 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+	{ 0x3d402020, 0x11 },
+	{ 0x3d402024, 0x7d00 },
+	{ 0x3d402050, 0x20d040 },
+	{ 0x3d402064, 0xc001c },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x310000 },
+	{ 0x3d4020e8, 0x66004d },
+	{ 0x3d4020ec, 0x16004d },
+	{ 0x3d402100, 0xa040305 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x1d },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d4020f4, 0xc99 },
+	{ 0x3d403020, 0x11 },
+	{ 0x3d403024, 0x1f40 },
+	{ 0x3d403050, 0x20d040 },
+	{ 0x3d403064, 0x30007 },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x310000 },
+	{ 0x3d4030e8, 0x66004d },
+	{ 0x3d4030ec, 0x16004d },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x301 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0x8 },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+	{ 0x3d4030f4, 0xc99 },
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x3 },
+	{ 0x110a3, 0x4 },
+	{ 0x110a4, 0x5 },
+	{ 0x110a5, 0x2 },
+	{ 0x110a6, 0x7 },
+	{ 0x110a7, 0x6 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0xb },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x1 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1a3 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x1a3 },
+	{ 0x2003a, 0x2 },
+	{ 0x220024, 0x1a3 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x1 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x190 },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0xdc },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x2200b2, 0xdc },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x2005b, 0x7529 },
+	{ 0x2005c, 0x0 },
+	{ 0x200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x200cc, 0x1f7 },
+	{ 0x1200c7, 0x21 },
+	{ 0x1200ca, 0x24 },
+	{ 0x1200cc, 0x1f7 },
+	{ 0x2200c7, 0x21 },
+	{ 0x2200ca, 0x24 },
+	{ 0x2200cc, 0x1f7 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x22007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x22007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{0x0200b2, 0x0},
+	{0x1200b2, 0x0},
+	{0x2200b2, 0x0},
+	{0x0200cb, 0x0},
+	{0x010043, 0x0},
+	{0x110043, 0x0},
+	{0x210043, 0x0},
+	{0x010143, 0x0},
+	{0x110143, 0x0},
+	{0x210143, 0x0},
+	{0x011043, 0x0},
+	{0x111043, 0x0},
+	{0x211043, 0x0},
+	{0x011143, 0x0},
+	{0x111143, 0x0},
+	{0x211143, 0x0},
+	{0x000080, 0x0},
+	{0x100080, 0x0},
+	{0x200080, 0x0},
+	{0x001080, 0x0},
+	{0x101080, 0x0},
+	{0x201080, 0x0},
+	{0x002080, 0x0},
+	{0x102080, 0x0},
+	{0x202080, 0x0},
+	{0x003080, 0x0},
+	{0x103080, 0x0},
+	{0x203080, 0x0},
+	{0x004080, 0x0},
+	{0x104080, 0x0},
+	{0x204080, 0x0},
+	{0x005080, 0x0},
+	{0x105080, 0x0},
+	{0x205080, 0x0},
+	{0x006080, 0x0},
+	{0x106080, 0x0},
+	{0x206080, 0x0},
+	{0x007080, 0x0},
+	{0x107080, 0x0},
+	{0x207080, 0x0},
+	{0x008080, 0x0},
+	{0x108080, 0x0},
+	{0x208080, 0x0},
+	{0x009080, 0x0},
+	{0x109080, 0x0},
+	{0x209080, 0x0},
+	{0x010080, 0x0},
+	{0x110080, 0x0},
+	{0x210080, 0x0},
+	{0x010180, 0x0},
+	{0x110180, 0x0},
+	{0x210180, 0x0},
+	{0x011080, 0x0},
+	{0x111080, 0x0},
+	{0x211080, 0x0},
+	{0x011180, 0x0},
+	{0x111180, 0x0},
+	{0x211180, 0x0},
+	{0x010081, 0x0},
+	{0x110081, 0x0},
+	{0x210081, 0x0},
+	{0x010181, 0x0},
+	{0x110181, 0x0},
+	{0x210181, 0x0},
+	{0x011081, 0x0},
+	{0x111081, 0x0},
+	{0x211081, 0x0},
+	{0x011181, 0x0},
+	{0x111181, 0x0},
+	{0x211181, 0x0},
+	{0x0100d0, 0x0},
+	{0x1100d0, 0x0},
+	{0x2100d0, 0x0},
+	{0x0101d0, 0x0},
+	{0x1101d0, 0x0},
+	{0x2101d0, 0x0},
+	{0x0110d0, 0x0},
+	{0x1110d0, 0x0},
+	{0x2110d0, 0x0},
+	{0x0111d0, 0x0},
+	{0x1111d0, 0x0},
+	{0x2111d0, 0x0},
+	{0x0100d1, 0x0},
+	{0x1100d1, 0x0},
+	{0x2100d1, 0x0},
+	{0x0101d1, 0x0},
+	{0x1101d1, 0x0},
+	{0x2101d1, 0x0},
+	{0x0110d1, 0x0},
+	{0x1110d1, 0x0},
+	{0x2110d1, 0x0},
+	{0x0111d1, 0x0},
+	{0x1111d1, 0x0},
+	{0x2111d1, 0x0},
+	{0x010068, 0x0},
+	{0x010168, 0x0},
+	{0x010268, 0x0},
+	{0x010368, 0x0},
+	{0x010468, 0x0},
+	{0x010568, 0x0},
+	{0x010668, 0x0},
+	{0x010768, 0x0},
+	{0x010868, 0x0},
+	{0x011068, 0x0},
+	{0x011168, 0x0},
+	{0x011268, 0x0},
+	{0x011368, 0x0},
+	{0x011468, 0x0},
+	{0x011568, 0x0},
+	{0x011668, 0x0},
+	{0x011768, 0x0},
+	{0x011868, 0x0},
+	{0x010069, 0x0},
+	{0x010169, 0x0},
+	{0x010269, 0x0},
+	{0x010369, 0x0},
+	{0x010469, 0x0},
+	{0x010569, 0x0},
+	{0x010669, 0x0},
+	{0x010769, 0x0},
+	{0x010869, 0x0},
+	{0x011069, 0x0},
+	{0x011169, 0x0},
+	{0x011269, 0x0},
+	{0x011369, 0x0},
+	{0x011469, 0x0},
+	{0x011569, 0x0},
+	{0x011669, 0x0},
+	{0x011769, 0x0},
+	{0x011869, 0x0},
+	{0x01008c, 0x0},
+	{0x11008c, 0x0},
+	{0x21008c, 0x0},
+	{0x01018c, 0x0},
+	{0x11018c, 0x0},
+	{0x21018c, 0x0},
+	{0x01108c, 0x0},
+	{0x11108c, 0x0},
+	{0x21108c, 0x0},
+	{0x01118c, 0x0},
+	{0x11118c, 0x0},
+	{0x21118c, 0x0},
+	{0x01008d, 0x0},
+	{0x11008d, 0x0},
+	{0x21008d, 0x0},
+	{0x01018d, 0x0},
+	{0x11018d, 0x0},
+	{0x21018d, 0x0},
+	{0x01108d, 0x0},
+	{0x11108d, 0x0},
+	{0x21108d, 0x0},
+	{0x01118d, 0x0},
+	{0x11118d, 0x0},
+	{0x21118d, 0x0},
+	{0x0100c0, 0x0},
+	{0x1100c0, 0x0},
+	{0x2100c0, 0x0},
+	{0x0101c0, 0x0},
+	{0x1101c0, 0x0},
+	{0x2101c0, 0x0},
+	{0x0102c0, 0x0},
+	{0x1102c0, 0x0},
+	{0x2102c0, 0x0},
+	{0x0103c0, 0x0},
+	{0x1103c0, 0x0},
+	{0x2103c0, 0x0},
+	{0x0104c0, 0x0},
+	{0x1104c0, 0x0},
+	{0x2104c0, 0x0},
+	{0x0105c0, 0x0},
+	{0x1105c0, 0x0},
+	{0x2105c0, 0x0},
+	{0x0106c0, 0x0},
+	{0x1106c0, 0x0},
+	{0x2106c0, 0x0},
+	{0x0107c0, 0x0},
+	{0x1107c0, 0x0},
+	{0x2107c0, 0x0},
+	{0x0108c0, 0x0},
+	{0x1108c0, 0x0},
+	{0x2108c0, 0x0},
+	{0x0110c0, 0x0},
+	{0x1110c0, 0x0},
+	{0x2110c0, 0x0},
+	{0x0111c0, 0x0},
+	{0x1111c0, 0x0},
+	{0x2111c0, 0x0},
+	{0x0112c0, 0x0},
+	{0x1112c0, 0x0},
+	{0x2112c0, 0x0},
+	{0x0113c0, 0x0},
+	{0x1113c0, 0x0},
+	{0x2113c0, 0x0},
+	{0x0114c0, 0x0},
+	{0x1114c0, 0x0},
+	{0x2114c0, 0x0},
+	{0x0115c0, 0x0},
+	{0x1115c0, 0x0},
+	{0x2115c0, 0x0},
+	{0x0116c0, 0x0},
+	{0x1116c0, 0x0},
+	{0x2116c0, 0x0},
+	{0x0117c0, 0x0},
+	{0x1117c0, 0x0},
+	{0x2117c0, 0x0},
+	{0x0118c0, 0x0},
+	{0x1118c0, 0x0},
+	{0x2118c0, 0x0},
+	{0x0100c1, 0x0},
+	{0x1100c1, 0x0},
+	{0x2100c1, 0x0},
+	{0x0101c1, 0x0},
+	{0x1101c1, 0x0},
+	{0x2101c1, 0x0},
+	{0x0102c1, 0x0},
+	{0x1102c1, 0x0},
+	{0x2102c1, 0x0},
+	{0x0103c1, 0x0},
+	{0x1103c1, 0x0},
+	{0x2103c1, 0x0},
+	{0x0104c1, 0x0},
+	{0x1104c1, 0x0},
+	{0x2104c1, 0x0},
+	{0x0105c1, 0x0},
+	{0x1105c1, 0x0},
+	{0x2105c1, 0x0},
+	{0x0106c1, 0x0},
+	{0x1106c1, 0x0},
+	{0x2106c1, 0x0},
+	{0x0107c1, 0x0},
+	{0x1107c1, 0x0},
+	{0x2107c1, 0x0},
+	{0x0108c1, 0x0},
+	{0x1108c1, 0x0},
+	{0x2108c1, 0x0},
+	{0x0110c1, 0x0},
+	{0x1110c1, 0x0},
+	{0x2110c1, 0x0},
+	{0x0111c1, 0x0},
+	{0x1111c1, 0x0},
+	{0x2111c1, 0x0},
+	{0x0112c1, 0x0},
+	{0x1112c1, 0x0},
+	{0x2112c1, 0x0},
+	{0x0113c1, 0x0},
+	{0x1113c1, 0x0},
+	{0x2113c1, 0x0},
+	{0x0114c1, 0x0},
+	{0x1114c1, 0x0},
+	{0x2114c1, 0x0},
+	{0x0115c1, 0x0},
+	{0x1115c1, 0x0},
+	{0x2115c1, 0x0},
+	{0x0116c1, 0x0},
+	{0x1116c1, 0x0},
+	{0x2116c1, 0x0},
+	{0x0117c1, 0x0},
+	{0x1117c1, 0x0},
+	{0x2117c1, 0x0},
+	{0x0118c1, 0x0},
+	{0x1118c1, 0x0},
+	{0x2118c1, 0x0},
+	{0x010020, 0x0},
+	{0x110020, 0x0},
+	{0x210020, 0x0},
+	{0x011020, 0x0},
+	{0x111020, 0x0},
+	{0x211020, 0x0},
+	{0x020072, 0x0},
+	{0x020073, 0x0},
+	{0x020074, 0x0},
+	{0x0100aa, 0x0},
+	{0x0110aa, 0x0},
+	{0x020010, 0x0},
+	{0x120010, 0x0},
+	{0x220010, 0x0},
+	{0x020011, 0x0},
+	{0x120011, 0x0},
+	{0x220011, 0x0},
+	{0x0100ae, 0x0},
+	{0x1100ae, 0x0},
+	{0x2100ae, 0x0},
+	{0x0100af, 0x0},
+	{0x1100af, 0x0},
+	{0x2100af, 0x0},
+	{0x0110ae, 0x0},
+	{0x1110ae, 0x0},
+	{0x2110ae, 0x0},
+	{0x0110af, 0x0},
+	{0x1110af, 0x0},
+	{0x2110af, 0x0},
+	{0x020020, 0x0},
+	{0x120020, 0x0},
+	{0x220020, 0x0},
+	{0x0100a0, 0x0},
+	{0x0100a1, 0x0},
+	{0x0100a2, 0x0},
+	{0x0100a3, 0x0},
+	{0x0100a4, 0x0},
+	{0x0100a5, 0x0},
+	{0x0100a6, 0x0},
+	{0x0100a7, 0x0},
+	{0x0110a0, 0x0},
+	{0x0110a1, 0x0},
+	{0x0110a2, 0x0},
+	{0x0110a3, 0x0},
+	{0x0110a4, 0x0},
+	{0x0110a5, 0x0},
+	{0x0110a6, 0x0},
+	{0x0110a7, 0x0},
+	{0x02007c, 0x0},
+	{0x12007c, 0x0},
+	{0x22007c, 0x0},
+	{0x02007d, 0x0},
+	{0x12007d, 0x0},
+	{0x22007d, 0x0},
+	{0x0400fd, 0x0},
+	{0x0400c0, 0x0},
+	{0x090201, 0x0},
+	{0x190201, 0x0},
+	{0x290201, 0x0},
+	{0x090202, 0x0},
+	{0x190202, 0x0},
+	{0x290202, 0x0},
+	{0x090203, 0x0},
+	{0x190203, 0x0},
+	{0x290203, 0x0},
+	{0x090204, 0x0},
+	{0x190204, 0x0},
+	{0x290204, 0x0},
+	{0x090205, 0x0},
+	{0x190205, 0x0},
+	{0x290205, 0x0},
+	{0x090206, 0x0},
+	{0x190206, 0x0},
+	{0x290206, 0x0},
+	{0x090207, 0x0},
+	{0x190207, 0x0},
+	{0x290207, 0x0},
+	{0x090208, 0x0},
+	{0x190208, 0x0},
+	{0x290208, 0x0},
+	{0x010062, 0x0},
+	{0x010162, 0x0},
+	{0x010262, 0x0},
+	{0x010362, 0x0},
+	{0x010462, 0x0},
+	{0x010562, 0x0},
+	{0x010662, 0x0},
+	{0x010762, 0x0},
+	{0x010862, 0x0},
+	{0x011062, 0x0},
+	{0x011162, 0x0},
+	{0x011262, 0x0},
+	{0x011362, 0x0},
+	{0x011462, 0x0},
+	{0x011562, 0x0},
+	{0x011662, 0x0},
+	{0x011762, 0x0},
+	{0x011862, 0x0},
+	{0x020077, 0x0},
+	{0x010001, 0x0},
+	{0x011001, 0x0},
+	{0x010040, 0x0},
+	{0x010140, 0x0},
+	{0x010240, 0x0},
+	{0x010340, 0x0},
+	{0x010440, 0x0},
+	{0x010540, 0x0},
+	{0x010640, 0x0},
+	{0x010740, 0x0},
+	{0x010840, 0x0},
+	{0x010030, 0x0},
+	{0x010130, 0x0},
+	{0x010230, 0x0},
+	{0x010330, 0x0},
+	{0x010430, 0x0},
+	{0x010530, 0x0},
+	{0x010630, 0x0},
+	{0x010730, 0x0},
+	{0x010830, 0x0},
+	{0x011040, 0x0},
+	{0x011140, 0x0},
+	{0x011240, 0x0},
+	{0x011340, 0x0},
+	{0x011440, 0x0},
+	{0x011540, 0x0},
+	{0x011640, 0x0},
+	{0x011740, 0x0},
+	{0x011840, 0x0},
+	{0x011030, 0x0},
+	{0x011130, 0x0},
+	{0x011230, 0x0},
+	{0x011330, 0x0},
+	{0x011430, 0x0},
+	{0x011530, 0x0},
+	{0x011630, 0x0},
+	{0x011730, 0x0},
+	{0x011830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x640 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x12a4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x12a4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x54032, 0xa400 },
+	{ 0x54033, 0x3112 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xa400 },
+	{ 0x54039, 0x3112 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x640 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x12a4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d00 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x12a4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d00 },
+	{ 0x54024, 0x16 },
+	{ 0x54032, 0xa400 },
+	{ 0x54033, 0x3112 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x4d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xa400 },
+	{ 0x54039, 0x3112 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x4d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xb },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x633 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x633 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x633 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x633 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x633 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x633 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x633 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xb },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x1 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x625 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x625 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a4, 0x0 },
+	{ 0x900a5, 0x790 },
+	{ 0x900a6, 0x11a },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7aa },
+	{ 0x900a9, 0x2a },
+	{ 0x900aa, 0x10 },
+	{ 0x900ab, 0x7b2 },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x0 },
+	{ 0x900ae, 0x7c8 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x10 },
+	{ 0x900b1, 0x10 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xd },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x0 },
+	{ 0x90159, 0x400 },
+	{ 0x9015a, 0x10e },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x10c },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x7c8 },
+	{ 0x90166, 0x101 },
+	{ 0x90167, 0x8 },
+	{ 0x90168, 0x448 },
+	{ 0x90169, 0x109 },
+	{ 0x9016a, 0xf },
+	{ 0x9016b, 0x7c0 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0x0 },
+	{ 0x9016e, 0xe8 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x47 },
+	{ 0x90171, 0x630 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x8 },
+	{ 0x90174, 0x618 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0xe0 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x0 },
+	{ 0x9017a, 0x7c8 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x8 },
+	{ 0x9017d, 0x8140 },
+	{ 0x9017e, 0x10c },
+	{ 0x9017f, 0x0 },
+	{ 0x90180, 0x1 },
+	{ 0x90181, 0x8 },
+	{ 0x90182, 0x8 },
+	{ 0x90183, 0x4 },
+	{ 0x90184, 0x8 },
+	{ 0x90185, 0x8 },
+	{ 0x90186, 0x7c8 },
+	{ 0x90187, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x29 },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x2000b, 0x32 },
+	{ 0x2000c, 0x64 },
+	{ 0x2000d, 0x3e8 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x2060 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x120010, 0x5a },
+	{ 0x120011, 0x3 },
+	{ 0x220010, 0x5a },
+	{ 0x220011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 1600mts 1D */
+		.drate = 1600,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 1600mts 2D */
+		.drate = 1600,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 1600, 400, 100, },
+};
diff --git a/board/freescale/imx8mm_ab2/spl.c b/board/freescale/imx8mm_ab2/spl.c
new file mode 100644
index 00000000000..fe38a2a04ac
--- /dev/null
+++ b/board/freescale/imx8mm_ab2/spl.c
@@ -0,0 +1,473 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/clock.h>
+#if defined(CONFIG_IMX8MM)
+#include <asm/arch/imx8mm_pins.h>
+#endif
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/ddr.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
+#include <power/bd71837.h>
+#include <power/bd71837.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <linux/delay.h>
+#include <fsl_sec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+#ifdef CONFIG_SPL_BOOTROM_SUPPORT
+	return BOOT_DEVICE_BOOTROM;
+#else
+	switch (boot_dev_spl) {
+	case SD1_BOOT:
+	case MMC1_BOOT:
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD3_BOOT:
+	case MMC3_BOOT:
+		return BOOT_DEVICE_MMC2;
+	case QSPI_BOOT:
+		return BOOT_DEVICE_NOR;
+	case NAND_BOOT:
+		return BOOT_DEVICE_NAND;
+	case USB_BOOT:
+		return BOOT_DEVICE_BOARD;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+#endif
+}
+
+void spl_dram_init(void)
+{
+	ddr_init(&dram_timing);
+}
+
+#if defined(CONFIG_IMX8MM)
+
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
+#define USDHC_CD_PAD_CTRL (PAD_CTL_PE |PAD_CTL_PUE |PAD_CTL_HYS | PAD_CTL_DSE4)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC2_PWR_GPIO	IMX_GPIO_NR(2, 19)
+
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MM_PAD_I2C1_SCL_I2C1_SCL | PC,
+		.gpio_mode = IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MM_PAD_I2C1_SDA_I2C1_SDA | PC,
+		.gpio_mode = IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IMX8MM_PAD_NAND_WE_B_USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_WP_B_USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+	IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC2_BASE_ADDR, 0, 4},
+	{USDHC3_BASE_ADDR, 0, 8},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			init_clk_usdhc(1);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+			gpio_direction_output(USDHC2_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
+			gpio_direction_input(USDHC2_CD_GPIO);
+			break;
+		case 1:
+			init_clk_usdhc(2);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC3_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		return ret;
+	}
+
+	return 1;
+}
+#endif
+
+#if CONFIG_IS_ENABLED(POWER_LEGACY)
+#define I2C_PMIC	0
+#ifdef CONFIG_POWER_PCA9450
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+
+	ret = power_pca9450_init(I2C_PMIC, 0x25);
+	if (ret)
+		printf("power init failed");
+	p = pmic_get("PCA9450");
+	pmic_probe(p);
+
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
+
+	/* Buck 1 DVS control through PMIC_STBY_REQ */
+	pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
+
+	/* Set DVS1 to 0.8v for suspend */
+	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x10);
+
+	/* increase VDD_DRAM to 0.95v for 3Ghz DDR */
+	pmic_reg_write(p, PCA9450_BUCK3OUT_DVS0, 0x1C);
+
+	/* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */
+	pmic_reg_write(p, PCA9450_BUCK3CTRL, 0x4a);
+
+	/* set VDD_SNVS_0V8 from default 0.85V */
+	pmic_reg_write(p, PCA9450_LDO2CTRL, 0xC0);
+
+	/* set WDOG_B_CFG to cold reset */
+	pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
+
+	return 0;
+}
+#else
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+
+	ret = power_bd71837_init(I2C_PMIC);
+	if (ret)
+		printf("power init failed");
+
+	p = pmic_get("BD71837");
+	pmic_probe(p);
+
+
+	/* decrease RESET key long push time from the default 10s to 10ms */
+	pmic_reg_write(p, BD718XX_PWRONCONFIG1, 0x0);
+
+	/* unlock the PMIC regs */
+	pmic_reg_write(p, BD718XX_REGLOCK, 0x1);
+
+	/* increase VDD_SOC to typical value 0.85v before first DRAM access */
+	pmic_reg_write(p, BD718XX_BUCK1_VOLT_RUN, 0x0f);
+
+	/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
+	pmic_reg_write(p, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
+
+#ifndef CONFIG_IMX8M_LPDDR4
+	/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
+	pmic_reg_write(p, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
+#endif
+
+	/* lock the PMIC regs */
+	pmic_reg_write(p, BD718XX_REGLOCK, 0x11);
+
+	return 0;
+}
+#endif
+#endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */
+
+#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("pca9450@25", &dev);
+	if (ret == -ENODEV) {
+		puts("No pca9450@25\n");
+		return 0;
+	}
+	if (ret != 0)
+		return ret;
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+#if defined(CONFIG_IMX8MM)
+	/* Buck 1 DVS control through PMIC_STBY_REQ */
+	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+	/* Set DVS1 to 0.8v for suspend */
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10);
+	/* increase VDD_DRAM to 0.95v for 3Ghz DDR */
+	pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C);
+	/* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */
+	pmic_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a);
+	/* set VDD_SNVS_0V8 from default 0.85V */
+	pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
+#endif /* CONFIG_IMX8MM */
+
+#if defined(CONFIG_IMX8MN)
+#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
+	/* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10);
+#elif defined(CONFIG_TARGET_IMX8MN_DDR3L_AB2)
+	/* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
+
+	/* Disable the BUCK2 */
+	pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48);
+
+	/* Set NVCC_DRAM to 1.35v */
+	pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E);
+#else
+	/* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
+#endif
+	/* Set DVS1 to 0.75v for low-v suspend */
+	/* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0xC);
+	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+	/* set VDD_SNVS_0V8 from default 0.85V */
+	pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
+
+	/* enable LDO4 to 1.2v */
+	pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x44);
+#endif /* CONFIG_IMX8MN */
+
+	/* set WDOG_B_CFG to cold reset */
+	pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
+
+	return 0;
+}
+#endif /* DM_PMIC_PCA9450 */
+
+#if CONFIG_IS_ENABLED(DM_PMIC_BD71837)
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("pmic@4b", &dev);
+	if (ret == -ENODEV) {
+		puts("No pmic@4b\n");
+		return 0;
+	}
+	if (ret != 0)
+		return ret;
+
+	/* decrease RESET key long push time from the default 10s to 10ms */
+	pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
+	/* unlock the PMIC regs */
+	pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
+
+#if defined(CONFIG_IMX8MM)
+	/* increase VDD_SOC to typical value 0.85v before first DRAM access */
+	pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
+	/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
+	pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
+#ifdef CONFIG_IMX8M_DDR4
+	/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
+	pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
+#endif
+#endif /* CONFIG_IMX8MM */
+
+#if defined(CONFIG_IMX8MN)
+	/* Set VDD_ARM to typical value 0.85v for 1.2Ghz */
+	pmic_reg_write(dev, BD718XX_BUCK2_VOLT_RUN, 0xf);
+#ifdef CONFIG_IMX8M_DDR4
+	/* Set VDD_SOC/VDD_DRAM to typical value 0.85v for nominal mode */
+	pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0xf);
+#endif
+	/* Set VDD_SOC 0.85v for suspend */
+	pmic_reg_write(dev, BD718XX_BUCK1_VOLT_SUSP, 0xf);
+#ifdef CONFIG_IMX8M_DDR4
+	/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
+	pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
+#endif
+#endif /* CONFIG_IMX8MN */
+
+	/* lock the PMIC regs */
+	pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
+
+	return 0;
+}
+#endif /* DM_PMIC_BD71837 */
+
+void spl_board_init(void)
+{
+#if defined(CONFIG_IMX8MN)
+	struct udevice *dev;
+	int ret;
+
+	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+		if (ret)
+			printf("Failed to initialize %d\n", ret);
+	}
+#else
+	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+		if (sec_init())
+			printf("\nsec_init failed!\n");
+	}
+#endif
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+#if defined(CONFIG_IMX8MN)
+	struct udevice *dev;
+
+	ret = uclass_get_device_by_name(UCLASS_CLK,
+					"clock-controller@30380000",
+					&dev);
+	if (ret < 0) {
+		printf("Failed to find clock node. Check device tree\n");
+		hang();
+	}
+#endif
+
+	enable_tzc380();
+
+#if defined(CONFIG_IMX8MM)
+	/* Adjust pmic voltage to 1.0V for 800M */
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
+
+#if defined(CONFIG_IMX8MN)
+#ifdef CONFIG_SPL_MMC
+#define UBOOT_RAW_SECTOR_OFFSET 0x40
+unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc)
+{
+	u32 boot_dev = spl_boot_device();
+	switch (boot_dev) {
+		case BOOT_DEVICE_MMC1:
+			return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
+		case BOOT_DEVICE_MMC2:
+			return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET;
+	}
+	return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
+}
+#endif
+#endif
diff --git a/board/freescale/imx8mm_evk/Kconfig b/board/freescale/imx8mm_evk/Kconfig
index 24cc526b0ab..f8789fceb21 100644
--- a/board/freescale/imx8mm_evk/Kconfig
+++ b/board/freescale/imx8mm_evk/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_IMX8MM_EVK
+if TARGET_IMX8MM_EVK || TARGET_IMX8MM_DDR4_EVK
 
 config SYS_BOARD
 	default "imx8mm_evk"
@@ -10,6 +10,11 @@ config SYS_CONFIG_NAME
 	default "imx8mm_evk"
 
 config IMX_CONFIG
-	default "board/freescale/imx8mm_evk/imximage-8mm-lpddr4.cfg"
+	default "board/freescale/imx8mm_evk/imximage-8mm.cfg"
+
+config IMX8M_1G_MEMORY
+	bool "imx8m 1GB memory size"
+
+source "board/freescale/common/Kconfig"
 
 endif
diff --git a/board/freescale/imx8mm_evk/Makefile b/board/freescale/imx8mm_evk/Makefile
index 1db7b62cafc..b3f1c185a3f 100644
--- a/board/freescale/imx8mm_evk/Makefile
+++ b/board/freescale/imx8mm_evk/Makefile
@@ -8,5 +8,10 @@ obj-y += imx8mm_evk.o
 
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
+ifdef CONFIG_IMX8M_4G_LPDDR4
+obj-y += lpddr4_timing_4g.o
+else
 obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
+endif
 endif
diff --git a/board/freescale/imx8mm_evk/ddr4_timing.c b/board/freescale/imx8mm_evk/ddr4_timing.c
new file mode 100644
index 00000000000..2f80b9832b2
--- /dev/null
+++ b/board/freescale/imx8mm_evk/ddr4_timing.c
@@ -0,0 +1,1265 @@
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0x81040010 },
+	{ 0x3d400030, 0xaa },
+	{ 0x3d400034, 0x221306 },
+	{ 0x3d400050, 0x210070 },
+	{ 0x3d400054, 0x10008 },
+	{ 0x3d400060, 0x0 },
+	{ 0x3d400064, 0x9200d2 },
+	{ 0x3d4000c0, 0x0 },
+	{ 0x3d4000c4, 0x1000 },
+	{ 0x3d4000d0, 0xc0030126 },
+	{ 0x3d4000d4, 0x770000 },
+	{ 0x3d4000dc, 0x8340105 },
+	{ 0x3d4000e0, 0x180200 },
+	{ 0x3d4000e4, 0x110000 },
+	{ 0x3d4000e8, 0x2000600 },
+	{ 0x3d4000ec, 0x814 },
+	{ 0x3d4000f0, 0x20 },
+	{ 0x3d4000f4, 0xec7 },
+	{ 0x3d400100, 0x11122914 },
+	{ 0x3d400104, 0x4051c },
+	{ 0x3d400108, 0x608050d },
+	{ 0x3d40010c, 0x400c },
+	{ 0x3d400110, 0x8030409 },
+	{ 0x3d400114, 0x6060403 },
+	{ 0x3d40011c, 0x606 },
+	{ 0x3d400120, 0x5050d08 },
+	{ 0x3d400124, 0x2040a },
+	{ 0x3d40012c, 0x1409010e },
+	{ 0x3d400130, 0x8 },
+	{ 0x3d40013c, 0x0 },
+	{ 0x3d400180, 0x1000040 },
+	{ 0x3d400184, 0x493e },
+	{ 0x3d400190, 0x38b8207 },
+	{ 0x3d400194, 0x2020303 },
+	{ 0x3d400198, 0x7f04011 },
+	{ 0x3d40019c, 0xb0 },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0x48005a },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x1 },
+	{ 0x3d4001b4, 0xb07 },
+	{ 0x3d4001b8, 0x4 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x0 },
+	{ 0x3d400200, 0x3f1f },
+	{ 0x3d400204, 0x3f0909 },
+	{ 0x3d400208, 0x700 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf0f },
+	{ 0x3d400220, 0x3f01 },
+	{ 0x3d400240, 0x6000610 },
+	{ 0x3d400244, 0x1323 },
+	{ 0x3d402050, 0x210070 },
+	{ 0x3d402064, 0x40005e },
+	{ 0x3d4020dc, 0x40105 },
+	{ 0x3d4020e0, 0x0 },
+	{ 0x3d4020e8, 0x2000600 },
+	{ 0x3d4020ec, 0x14 },
+	{ 0x3d402100, 0xb081209 },
+	{ 0x3d402104, 0x2020d },
+	{ 0x3d402108, 0x5050309 },
+	{ 0x3d40210c, 0x400c },
+	{ 0x3d402110, 0x4030205 },
+	{ 0x3d402114, 0x3030202 },
+	{ 0x3d40211c, 0x303 },
+	{ 0x3d402120, 0x3030d04 },
+	{ 0x3d402124, 0x20208 },
+	{ 0x3d40212c, 0x1005010e },
+	{ 0x3d402130, 0x8 },
+	{ 0x3d40213c, 0x0 },
+	{ 0x3d402180, 0x1000040 },
+	{ 0x3d402190, 0x3858204 },
+	{ 0x3d402194, 0x2020303 },
+	{ 0x3d4021b4, 0x504 },
+	{ 0x3d4021b8, 0x4 },
+	{ 0x3d402240, 0x6000604 },
+	{ 0x3d4020f4, 0xec7 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x1005f, 0x2fd },
+	{ 0x1015f, 0x2fd },
+	{ 0x1105f, 0x2fd },
+	{ 0x1115f, 0x2fd },
+	{ 0x1205f, 0x2fd },
+	{ 0x1215f, 0x2fd },
+	{ 0x1305f, 0x2fd },
+	{ 0x1315f, 0x2fd },
+	{ 0x11005f, 0x2fd },
+	{ 0x11015f, 0x2fd },
+	{ 0x11105f, 0x2fd },
+	{ 0x11115f, 0x2fd },
+	{ 0x11205f, 0x2fd },
+	{ 0x11215f, 0x2fd },
+	{ 0x11305f, 0x2fd },
+	{ 0x11315f, 0x2fd },
+	{ 0x55, 0x355 },
+	{ 0x1055, 0x355 },
+	{ 0x2055, 0x355 },
+	{ 0x3055, 0x355 },
+	{ 0x4055, 0x55 },
+	{ 0x5055, 0x55 },
+	{ 0x6055, 0x355 },
+	{ 0x7055, 0x355 },
+	{ 0x8055, 0x355 },
+	{ 0x9055, 0x355 },
+	{ 0x200c5, 0xa },
+	{ 0x1200c5, 0x6 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x1 },
+	{ 0x20024, 0x8 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x8 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x6 },
+	{ 0x120056, 0xa },
+	{ 0x1004d, 0x1a },
+	{ 0x1014d, 0x1a },
+	{ 0x1104d, 0x1a },
+	{ 0x1114d, 0x1a },
+	{ 0x1204d, 0x1a },
+	{ 0x1214d, 0x1a },
+	{ 0x1304d, 0x1a },
+	{ 0x1314d, 0x1a },
+	{ 0x11004d, 0x1a },
+	{ 0x11014d, 0x1a },
+	{ 0x11104d, 0x1a },
+	{ 0x11114d, 0x1a },
+	{ 0x11204d, 0x1a },
+	{ 0x11214d, 0x1a },
+	{ 0x11304d, 0x1a },
+	{ 0x11314d, 0x1a },
+	{ 0x10049, 0xe38 },
+	{ 0x10149, 0xe38 },
+	{ 0x11049, 0xe38 },
+	{ 0x11149, 0xe38 },
+	{ 0x12049, 0xe38 },
+	{ 0x12149, 0xe38 },
+	{ 0x13049, 0xe38 },
+	{ 0x13149, 0xe38 },
+	{ 0x110049, 0xe38 },
+	{ 0x110149, 0xe38 },
+	{ 0x111049, 0xe38 },
+	{ 0x111149, 0xe38 },
+	{ 0x112049, 0xe38 },
+	{ 0x112149, 0xe38 },
+	{ 0x113049, 0xe38 },
+	{ 0x113149, 0xe38 },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x5 },
+	{ 0x20075, 0x2 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x258 },
+	{ 0x120008, 0x10a },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x268 },
+	{ 0x10043, 0x5b1 },
+	{ 0x10143, 0x5b1 },
+	{ 0x11043, 0x5b1 },
+	{ 0x11143, 0x5b1 },
+	{ 0x12043, 0x5b1 },
+	{ 0x12143, 0x5b1 },
+	{ 0x13043, 0x5b1 },
+	{ 0x13143, 0x5b1 },
+	{ 0x1200b2, 0x268 },
+	{ 0x110043, 0x5b1 },
+	{ 0x110143, 0x5b1 },
+	{ 0x111043, 0x5b1 },
+	{ 0x111143, 0x5b1 },
+	{ 0x112043, 0x5b1 },
+	{ 0x112143, 0x5b1 },
+	{ 0x113043, 0x5b1 },
+	{ 0x113143, 0x5b1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x20019, 0x5 },
+	{ 0x120019, 0x5 },
+	{ 0x200f0, 0x5555 },
+	{ 0x200f1, 0x5555 },
+	{ 0x200f2, 0x5555 },
+	{ 0x200f3, 0x5555 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0x5555 },
+	{ 0x200f6, 0x5555 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x200c7, 0x21 },
+	{ 0x1200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x1200ca, 0x24 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x960 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x31f },
+	{ 0x5400c, 0xc8 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x834 },
+	{ 0x54030, 0x105 },
+	{ 0x54031, 0x18 },
+	{ 0x54032, 0x200 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x814 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1323 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x1 },
+	{ 0x54003, 0x42a },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x21f },
+	{ 0x5400c, 0xc8 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x4 },
+	{ 0x54030, 0x105 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x14 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1323 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x960 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2830 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x61 },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400e, 0x1f7f },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x834 },
+	{ 0x54030, 0x105 },
+	{ 0x54031, 0x18 },
+	{ 0x54032, 0x200 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x814 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1323 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x2 },
+	{ 0x90033, 0x10 },
+	{ 0x90034, 0x139 },
+	{ 0x90035, 0xf },
+	{ 0x90036, 0x7c0 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0x44 },
+	{ 0x90039, 0x630 },
+	{ 0x9003a, 0x159 },
+	{ 0x9003b, 0x14f },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x47 },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x149 },
+	{ 0x90041, 0x4f },
+	{ 0x90042, 0x630 },
+	{ 0x90043, 0x179 },
+	{ 0x90044, 0x8 },
+	{ 0x90045, 0xe0 },
+	{ 0x90046, 0x109 },
+	{ 0x90047, 0x0 },
+	{ 0x90048, 0x7c8 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x1 },
+	{ 0x9004c, 0x8 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x45a },
+	{ 0x9004f, 0x9 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x448 },
+	{ 0x90052, 0x109 },
+	{ 0x90053, 0x40 },
+	{ 0x90054, 0x630 },
+	{ 0x90055, 0x179 },
+	{ 0x90056, 0x1 },
+	{ 0x90057, 0x618 },
+	{ 0x90058, 0x109 },
+	{ 0x90059, 0x40c0 },
+	{ 0x9005a, 0x630 },
+	{ 0x9005b, 0x149 },
+	{ 0x9005c, 0x8 },
+	{ 0x9005d, 0x4 },
+	{ 0x9005e, 0x48 },
+	{ 0x9005f, 0x4040 },
+	{ 0x90060, 0x630 },
+	{ 0x90061, 0x149 },
+	{ 0x90062, 0x0 },
+	{ 0x90063, 0x4 },
+	{ 0x90064, 0x48 },
+	{ 0x90065, 0x40 },
+	{ 0x90066, 0x630 },
+	{ 0x90067, 0x149 },
+	{ 0x90068, 0x10 },
+	{ 0x90069, 0x4 },
+	{ 0x9006a, 0x18 },
+	{ 0x9006b, 0x0 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x78 },
+	{ 0x9006e, 0x549 },
+	{ 0x9006f, 0x630 },
+	{ 0x90070, 0x159 },
+	{ 0x90071, 0xd49 },
+	{ 0x90072, 0x630 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0x94a },
+	{ 0x90075, 0x630 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x441 },
+	{ 0x90078, 0x630 },
+	{ 0x90079, 0x149 },
+	{ 0x9007a, 0x42 },
+	{ 0x9007b, 0x630 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x1 },
+	{ 0x9007e, 0x630 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x0 },
+	{ 0x90081, 0xe0 },
+	{ 0x90082, 0x109 },
+	{ 0x90083, 0xa },
+	{ 0x90084, 0x10 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0x9 },
+	{ 0x90087, 0x3c0 },
+	{ 0x90088, 0x149 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x159 },
+	{ 0x9008c, 0x18 },
+	{ 0x9008d, 0x10 },
+	{ 0x9008e, 0x109 },
+	{ 0x9008f, 0x0 },
+	{ 0x90090, 0x3c0 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x18 },
+	{ 0x90093, 0x4 },
+	{ 0x90094, 0x48 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x58 },
+	{ 0x90098, 0xa },
+	{ 0x90099, 0x10 },
+	{ 0x9009a, 0x109 },
+	{ 0x9009b, 0x2 },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x7 },
+	{ 0x9009f, 0x7c0 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x10 },
+	{ 0x900a2, 0x10 },
+	{ 0x900a3, 0x109 },
+	{ 0x900a4, 0x0 },
+	{ 0x900a5, 0x8140 },
+	{ 0x900a6, 0x10c },
+	{ 0x900a7, 0x10 },
+	{ 0x900a8, 0x8138 },
+	{ 0x900a9, 0x10c },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x7c8 },
+	{ 0x900ac, 0x101 },
+	{ 0x900ad, 0x8 },
+	{ 0x900ae, 0x0 },
+	{ 0x900af, 0x8 },
+	{ 0x900b0, 0x8 },
+	{ 0x900b1, 0x448 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0xf },
+	{ 0x900b4, 0x7c0 },
+	{ 0x900b5, 0x109 },
+	{ 0x900b6, 0x47 },
+	{ 0x900b7, 0x630 },
+	{ 0x900b8, 0x109 },
+	{ 0x900b9, 0x8 },
+	{ 0x900ba, 0x618 },
+	{ 0x900bb, 0x109 },
+	{ 0x900bc, 0x8 },
+	{ 0x900bd, 0xe0 },
+	{ 0x900be, 0x109 },
+	{ 0x900bf, 0x0 },
+	{ 0x900c0, 0x7c8 },
+	{ 0x900c1, 0x109 },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x8140 },
+	{ 0x900c4, 0x10c },
+	{ 0x900c5, 0x0 },
+	{ 0x900c6, 0x1 },
+	{ 0x900c7, 0x8 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x4 },
+	{ 0x900ca, 0x8 },
+	{ 0x900cb, 0x8 },
+	{ 0x900cc, 0x7c8 },
+	{ 0x900cd, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x90026, 0x2c },
+	{ 0x2000b, 0x4b },
+	{ 0x2000c, 0x96 },
+	{ 0x2000d, 0x5dc },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x21 },
+	{ 0x12000c, 0x42 },
+	{ 0x12000d, 0x29a },
+	{ 0x12000e, 0x21 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0xffff },
+	{ 0x90013, 0x6152 },
+	{ 0xc0080, 0x0 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 2400mts 1D */
+		.drate = 2400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 1066mts 1D */
+		.drate = 1066,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P0 2400mts 2D */
+		.drate = 2400,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 2400, 1066, },
+};
diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c
index e0975fcda70..d3ef12bf5b6 100644
--- a/board/freescale/imx8mm_evk/imx8mm_evk.c
+++ b/board/freescale/imx8mm_evk/imx8mm_evk.c
@@ -2,20 +2,93 @@
 /*
  * Copyright 2018 NXP
  */
-
 #include <common.h>
 #include <env.h>
 #include <init.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/global_data.h>
-
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/imx8mm_pins.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <i2c.h>
 #include <asm/io.h>
+#include "../common/tcpc.h"
+#include <usb.h>
+#include <imx_sip.h>
+#include <linux/arm-smccc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+#ifdef CONFIG_NAND_MXS
+#ifdef CONFIG_SPL_BUILD
+#define NAND_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS)
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE)
+static iomux_v3_cfg_t const gpmi_pads[] = {
+	IMX8MM_PAD_NAND_ALE_RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_CE1_B_RAWNAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_CLE_RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
+	IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+};
+#endif
+
+static void setup_gpmi_nand(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+#endif
+
+	init_nand_clk();
+}
+#endif
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	init_uart_clk(1);
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand(); /* SPL will call the board_early_init_f */
+#endif
+
+	return 0;
+}
+
 #if IS_ENABLED(CONFIG_FEC_MXC)
 static int setup_fec(void)
 {
@@ -30,6 +103,10 @@ static int setup_fec(void)
 
 int board_phy_config(struct phy_device *phydev)
 {
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+#ifndef CONFIG_DM_ETH
 	/* enable rgmii rxc skew and phy mode select to RGMII copper */
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
@@ -38,28 +115,214 @@ int board_phy_config(struct phy_device *phydev)
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+#endif
 
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
 	return 0;
 }
 #endif
 
-int board_init(void)
+#ifdef CONFIG_USB_TCPC
+struct tcpc_port port1;
+struct tcpc_port port2;
+
+static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr)
 {
-	if (IS_ENABLED(CONFIG_FEC_MXC))
-		setup_fec();
+	struct udevice *bus;
+	struct udevice *i2c_dev = NULL;
+	int ret;
+	uint8_t valb;
+
+	ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus);
+	if (ret) {
+		printf("%s: Can't find bus\n", __func__);
+		return -EINVAL;
+	}
+
+	ret = dm_i2c_probe(bus, addr, 0, &i2c_dev);
+	if (ret) {
+		printf("%s: Can't find device id=0x%x\n",
+			__func__, addr);
+		return -ENODEV;
+	}
+
+	ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_read failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+	valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */
+	ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+
+	/* Set OVP threshold to 23V */
+	valb = 0x6;
+	ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
 
 	return 0;
 }
 
-int board_mmc_get_env_dev(int devno)
+int pd_switch_snk_enable(struct tcpc_port *port)
 {
-	return devno;
+	if (port == &port1) {
+		debug("Setup pd switch on port 1\n");
+		return setup_pd_switch(1, 0x72);
+	} else if (port == &port2) {
+		debug("Setup pd switch on port 2\n");
+		return setup_pd_switch(1, 0x73);
+	} else
+		return -EINVAL;
+}
+
+struct tcpc_port_config port1_config = {
+	.i2c_bus = 1, /*i2c2*/
+	.addr = 0x50,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 5000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 40000,
+	.op_snk_mv = 9000,
+	.switch_setup_func = &pd_switch_snk_enable,
+};
+
+struct tcpc_port_config port2_config = {
+	.i2c_bus = 1, /*i2c2*/
+	.addr = 0x52,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 9000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 40000,
+	.op_snk_mv = 9000,
+	.switch_setup_func = &pd_switch_snk_enable,
+};
+
+static int setup_typec(void)
+{
+	int ret;
+
+	debug("tcpc_init port 2\n");
+	ret = tcpc_init(&port2, port2_config, NULL);
+	if (ret) {
+		printf("%s: tcpc port2 init failed, err=%d\n",
+		       __func__, ret);
+	} else if (tcpc_pd_sink_check_charging(&port2)) {
+		/* Disable PD for USB1, since USB2 has priority */
+		port1_config.disable_pd = true;
+		printf("Power supply on USB2\n");
+	}
+
+	debug("tcpc_init port 1\n");
+	ret = tcpc_init(&port1, port1_config, NULL);
+	if (ret) {
+		printf("%s: tcpc port1 init failed, err=%d\n",
+		       __func__, ret);
+	} else {
+		if (!port1_config.disable_pd)
+			printf("Power supply on USB1\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int ret = 0;
+	struct tcpc_port *port_ptr;
+
+	debug("board_usb_init %d, type %d\n", index, init);
+
+	if (index == 0)
+		port_ptr = &port1;
+	else
+		port_ptr = &port2;
+
+	imx8m_usb_power(index, true);
+
+	if (init == USB_INIT_HOST)
+		tcpc_setup_dfp_mode(port_ptr);
+	else
+		tcpc_setup_ufp_mode(port_ptr);
+
+	return ret;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	debug("board_usb_cleanup %d, type %d\n", index, init);
+
+	if (init == USB_INIT_HOST) {
+		if (index == 0)
+			ret = tcpc_disable_src_vbus(&port1);
+		else
+			ret = tcpc_disable_src_vbus(&port2);
+	}
+
+	imx8m_usb_power(index, false);
+	return ret;
+}
+
+int board_ehci_usb_phy_mode(struct udevice *dev)
+{
+	int ret = 0;
+	enum typec_cc_polarity pol;
+	enum typec_cc_state state;
+	struct tcpc_port *port_ptr;
+
+	if (dev_seq(dev) == 0)
+		port_ptr = &port1;
+	else
+		port_ptr = &port2;
+
+	tcpc_setup_ufp_mode(port_ptr);
+
+	ret = tcpc_get_cc_status(port_ptr, &pol, &state);
+	if (!ret) {
+		if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD)
+			return USB_INIT_HOST;
+	}
+
+	return USB_INIT_DEVICE;
+}
+
+#endif
+
+#define DISPMIX				9
+#define MIPI				10
+
+int board_init(void)
+{
+	struct arm_smccc_res res;
+
+#ifdef CONFIG_USB_TCPC
+	setup_typec();
+#endif
+
+	if (IS_ENABLED(CONFIG_FEC_MXC))
+		setup_fec();
+
+	arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN,
+		      DISPMIX, true, 0, 0, 0, 0, &res);
+	arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN,
+		      MIPI, true, 0, 0, 0, 0, &res);
+
+	return 0;
 }
 
 int board_late_init(void)
 {
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
 	if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
 		env_set("board_name", "EVK");
 		env_set("board_rev", "iMX8MM");
@@ -67,3 +330,18 @@ int board_late_init(void)
 
 	return 0;
 }
+
+#ifdef CONFIG_ANDROID_SUPPORT
+bool is_power_key_pressed(void) {
+	return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6)));
+}
+#endif
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+int is_recovery_key_pressing(void)
+{
+	return 0; /* TODO */
+}
+#endif /* CONFIG_ANDROID_RECOVERY */
+#endif /* CONFIG_FSL_FASTBOOT */
diff --git a/board/freescale/imx8mm_evk/imximage-8mm-fspi.cfg b/board/freescale/imx8mm_evk/imximage-8mm-fspi.cfg
new file mode 100644
index 00000000000..fcace8a93a0
--- /dev/null
+++ b/board/freescale/imx8mm_evk/imximage-8mm-fspi.cfg
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+BOOT_FROM	fspi
+LOADER		u-boot-spl-ddr.bin	0x7E2000
diff --git a/board/freescale/imx8mm_evk/imximage-8mm.cfg b/board/freescale/imx8mm_evk/imximage-8mm.cfg
new file mode 100644
index 00000000000..20061521f22
--- /dev/null
+++ b/board/freescale/imx8mm_evk/imximage-8mm.cfg
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+
+BOOT_FROM	sd
+LOADER		u-boot-spl-ddr.bin	0x7E1000
diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c b/board/freescale/imx8mm_evk/lpddr4_timing.c
index 4373ca624e4..3495b9c931e 100644
--- a/board/freescale/imx8mm_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mm_evk/lpddr4_timing.c
@@ -1,7 +1,8 @@
-// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2018-2019 NXP
  *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
  * Generated code from MX8M_DDR_tool
  */
 
@@ -1087,6 +1088,7 @@ struct dram_cfg_param ddr_fsp0_cfg[] = {
 	{ 0xd0000, 0x1 },
 };
 
+
 /* P1 message block paremeter for training firmware */
 struct dram_cfg_param ddr_fsp1_cfg[] = {
 	{ 0xd0000, 0x0 },
@@ -1126,6 +1128,7 @@ struct dram_cfg_param ddr_fsp1_cfg[] = {
 	{ 0xd0000, 0x1 },
 };
 
+
 /* P2 message block paremeter for training firmware */
 struct dram_cfg_param ddr_fsp2_cfg[] = {
 	{ 0xd0000, 0x0 },
@@ -1165,6 +1168,7 @@ struct dram_cfg_param ddr_fsp2_cfg[] = {
 	{ 0xd0000, 0x1 },
 };
 
+
 /* P0 2D message block paremeter for training firmware */
 struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{ 0xd0000, 0x0 },
diff --git a/board/freescale/imx8mm_evk/lpddr4_timing_4g.c b/board/freescale/imx8mm_evk/lpddr4_timing_4g.c
new file mode 100755
index 00000000000..d32ecbf905b
--- /dev/null
+++ b/board/freescale/imx8mm_evk/lpddr4_timing_4g.c
@@ -0,0 +1,1842 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{0x3d400304,0x1},
+	{0x3d400030,0x1},
+	{0x3d400000,0xa3080020},
+	{0x3d400020,0x223},
+	{0x3d400024,0x16e3600},
+	{0x3d400064,0x5b00d2},
+	{0x3d4000d0,0xc00305ba},
+	{0x3d4000d4,0x940000},
+	{0x3d4000dc,0xd4002d},
+	{0x3d4000e0,0x310000},
+	{0x3d4000e8,0x66004d},
+	{0x3d4000ec,0x16004d},
+	{0x3d400100,0x191e1920},
+	{0x3d400104,0x60630},
+	{0x3d40010c,0xb0b000},
+	{0x3d400110,0xe04080e},
+	{0x3d400114,0x2040c0c},
+	{0x3d400118,0x1010007},
+	{0x3d40011c,0x401},
+	{0x3d400130,0x20600},
+	{0x3d400134,0xc100002},
+	{0x3d400138,0xd8},
+	{0x3d400144,0x96004b},
+	{0x3d400180,0x2ee0017},
+	{0x3d400184,0x2605b8e},
+	{0x3d400188,0x0},
+	{0x3d400190,0x497820a},
+	{0x3d400194,0x80303},
+	{0x3d4001b4,0x170a},
+	{0x3d4001a0,0xe0400018},
+	{0x3d4001a4,0xdf00e4},
+	{0x3d4001a8,0x80000000},
+	{0x3d4001b0,0x11},
+	{0x3d4001c0,0x1},
+	{0x3d4001c4,0x0},
+	{0x3d4000f4,0xc99},
+	{0x3d400108,0x70e1617},
+	{0x3d400200,0x17},
+	{0x3d40020c,0x0},
+	{0x3d400210,0x1f1f},
+	{0x3d400204,0x80808},
+	{0x3d400214,0x7070707},
+	{0x3d400218,0x7070707},
+	{0x3d400250,0x29001701},
+	{0x3d400254,0x2c},
+	{0x3d40025c,0x4000030},
+	{0x3d400264,0x900093e7},
+	{0x3d40026c,0x2005574},
+	{0x3d400400,0x111},
+	{0x3d400408,0x72ff},
+	{0x3d400494,0x2100e07},
+	{0x3d400498,0x620096},
+	{0x3d40049c,0x1100e07},
+	{0x3d4004a0,0xc8012c},
+	{0x3d402020,0x21},
+	{0x3d402024,0x30d400},
+	{0x3d402050,0x20d040},
+	{0x3d402064,0xc001c},
+	{0x3d4020dc,0x840000},
+	{0x3d4020e0,0x310000},
+	{0x3d4020e8,0x66004d},
+	{0x3d4020ec,0x16004d},
+	{0x3d402100,0xa040305},
+	{0x3d402104,0x30407},
+	{0x3d402108,0x203060b},
+	{0x3d40210c,0x505000},
+	{0x3d402110,0x2040202},
+	{0x3d402114,0x2030202},
+	{0x3d402118,0x1010004},
+	{0x3d40211c,0x301},
+	{0x3d402130,0x20300},
+	{0x3d402134,0xa100002},
+	{0x3d402138,0x1d},
+	{0x3d402144,0x14000a},
+	{0x3d402180,0x640004},
+	{0x3d402190,0x3818200},
+	{0x3d402194,0x80303},
+	{0x3d4021b4,0x100},
+	{0x3d403020,0x21},
+	{0x3d403024,0xc3500},
+	{0x3d403050,0x20d040},
+	{0x3d403064,0x30007},
+	{0x3d4030dc,0x840000},
+	{0x3d4030e0,0x310000},
+	{0x3d4030e8,0x66004d},
+	{0x3d4030ec,0x16004d},
+	{0x3d403100,0xa010102},
+	{0x3d403104,0x30404},
+	{0x3d403108,0x203060b},
+	{0x3d40310c,0x505000},
+	{0x3d403110,0x2040202},
+	{0x3d403114,0x2030202},
+	{0x3d403118,0x1010004},
+	{0x3d40311c,0x301},
+	{0x3d403130,0x20300},
+	{0x3d403134,0xa100002},
+	{0x3d403138,0x8},
+	{0x3d403144,0x50003},
+	{0x3d403180,0x190004},
+	{0x3d403190,0x3818200},
+	{0x3d403194,0x80303},
+	{0x3d4031b4,0x100},
+	{0x3d400028,0x0},
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0,0x0},
+	{0x100a1,0x1},
+	{0x100a2,0x2},
+	{0x100a3,0x3},
+	{0x100a4,0x4},
+	{0x100a5,0x5},
+	{0x100a6,0x6},
+	{0x100a7,0x7},
+	{0x110a0,0x0},
+	{0x110a1,0x1},
+	{0x110a2,0x3},
+	{0x110a3,0x4},
+	{0x110a4,0x5},
+	{0x110a5,0x2},
+	{0x110a6,0x7},
+	{0x110a7,0x6},
+	{0x120a0,0x0},
+	{0x120a1,0x1},
+	{0x120a2,0x3},
+	{0x120a3,0x2},
+	{0x120a4,0x5},
+	{0x120a5,0x4},
+	{0x120a6,0x7},
+	{0x120a7,0x6},
+	{0x130a0,0x0},
+	{0x130a1,0x1},
+	{0x130a2,0x2},
+	{0x130a3,0x3},
+	{0x130a4,0x4},
+	{0x130a5,0x5},
+	{0x130a6,0x6},
+	{0x130a7,0x7},
+	{0x1005f,0x1ff},
+	{0x1015f,0x1ff},
+	{0x1105f,0x1ff},
+	{0x1115f,0x1ff},
+	{0x1205f,0x1ff},
+	{0x1215f,0x1ff},
+	{0x1305f,0x1ff},
+	{0x1315f,0x1ff},
+	{0x11005f,0x1ff},
+	{0x11015f,0x1ff},
+	{0x11105f,0x1ff},
+	{0x11115f,0x1ff},
+	{0x11205f,0x1ff},
+	{0x11215f,0x1ff},
+	{0x11305f,0x1ff},
+	{0x11315f,0x1ff},
+	{0x21005f,0x1ff},
+	{0x21015f,0x1ff},
+	{0x21105f,0x1ff},
+	{0x21115f,0x1ff},
+	{0x21205f,0x1ff},
+	{0x21215f,0x1ff},
+	{0x21305f,0x1ff},
+	{0x21315f,0x1ff},
+	{0x55,0x1ff},
+	{0x1055,0x1ff},
+	{0x2055,0x1ff},
+	{0x3055,0x1ff},
+	{0x4055,0x1ff},
+	{0x5055,0x1ff},
+	{0x6055,0x1ff},
+	{0x7055,0x1ff},
+	{0x8055,0x1ff},
+	{0x9055,0x1ff},
+	{0x200c5,0x19},
+	{0x1200c5,0x7},
+	{0x2200c5,0x7},
+	{0x2002e,0x2},
+	{0x12002e,0x2},
+	{0x22002e,0x2},
+	{0x90204,0x0},
+	{0x190204,0x0},
+	{0x290204,0x0},
+	{0x20024,0x1ab},
+	{0x2003a,0x0},
+	{0x120024,0x1ab},
+	{0x2003a,0x0},
+	{0x220024,0x1ab},
+	{0x2003a,0x0},
+	{0x20056,0x3},
+	{0x120056,0xa},
+	{0x220056,0xa},
+	{0x1004d,0xe00},
+	{0x1014d,0xe00},
+	{0x1104d,0xe00},
+	{0x1114d,0xe00},
+	{0x1204d,0xe00},
+	{0x1214d,0xe00},
+	{0x1304d,0xe00},
+	{0x1314d,0xe00},
+	{0x11004d,0xe00},
+	{0x11014d,0xe00},
+	{0x11104d,0xe00},
+	{0x11114d,0xe00},
+	{0x11204d,0xe00},
+	{0x11214d,0xe00},
+	{0x11304d,0xe00},
+	{0x11314d,0xe00},
+	{0x21004d,0xe00},
+	{0x21014d,0xe00},
+	{0x21104d,0xe00},
+	{0x21114d,0xe00},
+	{0x21204d,0xe00},
+	{0x21214d,0xe00},
+	{0x21304d,0xe00},
+	{0x21314d,0xe00},
+	{0x10049,0xeba},
+	{0x10149,0xeba},
+	{0x11049,0xeba},
+	{0x11149,0xeba},
+	{0x12049,0xeba},
+	{0x12149,0xeba},
+	{0x13049,0xeba},
+	{0x13149,0xeba},
+	{0x110049,0xeba},
+	{0x110149,0xeba},
+	{0x111049,0xeba},
+	{0x111149,0xeba},
+	{0x112049,0xeba},
+	{0x112149,0xeba},
+	{0x113049,0xeba},
+	{0x113149,0xeba},
+	{0x210049,0xeba},
+	{0x210149,0xeba},
+	{0x211049,0xeba},
+	{0x211149,0xeba},
+	{0x212049,0xeba},
+	{0x212149,0xeba},
+	{0x213049,0xeba},
+	{0x213149,0xeba},
+	{0x43,0x63},
+	{0x1043,0x63},
+	{0x2043,0x63},
+	{0x3043,0x63},
+	{0x4043,0x63},
+	{0x5043,0x63},
+	{0x6043,0x63},
+	{0x7043,0x63},
+	{0x8043,0x63},
+	{0x9043,0x63},
+	{0x20018,0x3},
+	{0x20075,0x4},
+	{0x20050,0x0},
+	{0x20008,0x2ee},
+	{0x120008,0x64},
+	{0x220008,0x19},
+	{0x20088,0x9},
+	{0x200b2,0xdc},
+	{0x10043,0x5a1},
+	{0x10143,0x5a1},
+	{0x11043,0x5a1},
+	{0x11143,0x5a1},
+	{0x12043,0x5a1},
+	{0x12143,0x5a1},
+	{0x13043,0x5a1},
+	{0x13143,0x5a1},
+	{0x1200b2,0xdc},
+	{0x110043,0x5a1},
+	{0x110143,0x5a1},
+	{0x111043,0x5a1},
+	{0x111143,0x5a1},
+	{0x112043,0x5a1},
+	{0x112143,0x5a1},
+	{0x113043,0x5a1},
+	{0x113143,0x5a1},
+	{0x2200b2,0xdc},
+	{0x210043,0x5a1},
+	{0x210143,0x5a1},
+	{0x211043,0x5a1},
+	{0x211143,0x5a1},
+	{0x212043,0x5a1},
+	{0x212143,0x5a1},
+	{0x213043,0x5a1},
+	{0x213143,0x5a1},
+	{0x200fa,0x1},
+	{0x1200fa,0x1},
+	{0x2200fa,0x1},
+	{0x20019,0x1},
+	{0x120019,0x1},
+	{0x220019,0x1},
+	{0x200f0,0x660},
+	{0x200f1,0x0},
+	{0x200f2,0x4444},
+	{0x200f3,0x8888},
+	{0x200f4,0x5665},
+	{0x200f5,0x0},
+	{0x200f6,0x0},
+	{0x200f7,0xf000},
+	{0x20025,0x0},
+	{0x2002d,0x0},
+	{0x12002d,0x0},
+	{0x22002d,0x0},
+	{0x200c7,0x21},
+	{0x1200c7,0x21},
+	{0x2200c7,0x21},
+	{0x200ca,0x24},
+	{0x1200ca,0x24},
+	{0x2200ca,0x24},
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },  
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },  
+	{ 0x10043, 0x0 },  
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },  
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },  
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },  
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },  
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },  
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },  
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },  
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },       
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },    
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },    
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },    
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },    
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },    
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },    
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },    
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },    
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },    
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },  
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },  
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },  
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },  
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },  
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },  
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },  
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },  
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },  
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },  
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },  
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },  
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },  
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },  
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },  
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },  
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+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003,0xbb8},
+	{0x54004,0x2},
+	{0x54006,0x11},
+	{0x54008,0x131f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x54012,0x310},
+	{0x54019,0x2dd4},
+	{0x5401a,0x31},
+	{0x5401b,0x4d66},
+	{0x5401c,0x4d00},
+	{0x5401e,0x16},
+	{0x5401f,0x2dd4},
+	{0x54020,0x31},
+	{0x54021,0x4d66},
+	{0x54022,0x4d00},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x3},
+	{0x54032,0xd400},
+	{0x54033,0x312d},
+	{0x54034,0x6600},
+	{0x54035,0x4d},
+	{0x54036,0x4d},
+	{0x54037,0x1600},
+	{0x54038,0xd400},
+	{0x54039,0x312d},
+	{0x5403a,0x6600},
+	{0x5403b,0x4d},
+	{0x5403c,0x4d},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002,0x101},
+	{0x54003,0x190},
+	{0x54004,0x2},
+	{0x54006,0x11},
+	{0x54008,0x121f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x54012,0x310},
+	{0x54019,0x84},
+	{0x5401a,0x31},
+	{0x5401b,0x4d66},
+	{0x5401c,0x4d00},
+	{0x5401e,0x16},
+	{0x5401f,0x84},
+	{0x54020,0x31},
+	{0x54021,0x4d66},
+	{0x54022,0x4d00},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x3},
+	{0x54032,0x8400},
+	{0x54033,0x3100},
+	{0x54034,0x6600},
+	{0x54035,0x4d},
+	{0x54036,0x4d},
+	{0x54037,0x1600},
+	{0x54038,0x8400},
+	{0x54039,0x3100},
+	{0x5403a,0x6600},
+	{0x5403b,0x4d},
+	{0x5403c,0x4d},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54002,0x102},
+	{0x54003,0x64},
+	{0x54004,0x2},
+	{0x54006,0x11},
+	{0x54008,0x121f},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x54012,0x310},
+	{0x54019,0x84},
+	{0x5401a,0x31},
+	{0x5401b,0x4d66},
+	{0x5401c,0x4d00},
+	{0x5401e,0x16},
+	{0x5401f,0x84},
+	{0x54020,0x31},
+	{0x54021,0x4d66},
+	{0x54022,0x4d00},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x3},
+	{0x54032,0x8400},
+	{0x54033,0x3100},
+	{0x54034,0x6600},
+	{0x54035,0x4d},
+	{0x54036,0x4d},
+	{0x54037,0x1600},
+	{0x54038,0x8400},
+	{0x54039,0x3100},
+	{0x5403a,0x6600},
+	{0x5403b,0x4d},
+	{0x5403c,0x4d},
+	{0x5403d,0x1600},
+	{0xd0000, 0x1},
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003,0xbb8},
+	{0x54004,0x2},
+	{0x54006,0x11},
+	{0x54008,0x61},
+	{0x54009,0xc8},
+	{0x5400b,0x2},
+	{0x5400f,0x100},
+	{0x54010,0x1f7f},
+	{0x54012,0x310},
+	{0x54019,0x2dd4},
+	{0x5401a,0x31},
+	{0x5401b,0x4d66},
+	{0x5401c,0x4d00},
+	{0x5401e,0x16},
+	{0x5401f,0x2dd4},
+	{0x54020,0x31},
+	{0x54021,0x4d66},
+	{0x54022,0x4d00},
+	{0x54024,0x16},
+	{0x5402b,0x1000},
+	{0x5402c,0x3},
+	{0x54032,0xd400},
+	{0x54033,0x312d},
+	{0x54034,0x6600},
+	{0x54035,0x4d},
+	{0x54036,0x4d},
+	{0x54037,0x1600},
+	{0x54038,0xd400},
+	{0x54039,0x312d},
+	{0x5403a,0x6600},
+	{0x5403b,0x4d},
+	{0x5403c,0x4d},
+	{0x5403d,0x1600},
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000,0x10},
+	{0x90001,0x400},
+	{0x90002,0x10e},
+	{0x90003,0x0},
+	{0x90004,0x0},
+	{0x90005,0x8},
+	{0x90029,0xb},
+	{0x9002a,0x480},
+	{0x9002b,0x109},
+	{0x9002c,0x8},
+	{0x9002d,0x448},
+	{0x9002e,0x139},
+	{0x9002f,0x8},
+	{0x90030,0x478},
+	{0x90031,0x109},
+	{0x90032,0x0},
+	{0x90033,0xe8},
+	{0x90034,0x109},
+	{0x90035,0x2},
+	{0x90036,0x10},
+	{0x90037,0x139},
+	{0x90038,0xf},
+	{0x90039,0x7c0},
+	{0x9003a,0x139},
+	{0x9003b,0x44},
+	{0x9003c,0x630},
+	{0x9003d,0x159},
+	{0x9003e,0x14f},
+	{0x9003f,0x630},
+	{0x90040,0x159},
+	{0x90041,0x47},
+	{0x90042,0x630},
+	{0x90043,0x149},
+	{0x90044,0x4f},
+	{0x90045,0x630},
+	{0x90046,0x179},
+	{0x90047,0x8},
+	{0x90048,0xe0},
+	{0x90049,0x109},
+	{0x9004a,0x0},
+	{0x9004b,0x7c8},
+	{0x9004c,0x109},
+	{0x9004d,0x0},
+	{0x9004e,0x1},
+	{0x9004f,0x8},
+	{0x90050,0x0},
+	{0x90051,0x45a},
+	{0x90052,0x9},
+	{0x90053,0x0},
+	{0x90054,0x448},
+	{0x90055,0x109},
+	{0x90056,0x40},
+	{0x90057,0x630},
+	{0x90058,0x179},
+	{0x90059,0x1},
+	{0x9005a,0x618},
+	{0x9005b,0x109},
+	{0x9005c,0x40c0},
+	{0x9005d,0x630},
+	{0x9005e,0x149},
+	{0x9005f,0x8},
+	{0x90060,0x4},
+	{0x90061,0x48},
+	{0x90062,0x4040},
+	{0x90063,0x630},
+	{0x90064,0x149},
+	{0x90065,0x0},
+	{0x90066,0x4},
+	{0x90067,0x48},
+	{0x90068,0x40},
+	{0x90069,0x630},
+	{0x9006a,0x149},
+	{0x9006b,0x10},
+	{0x9006c,0x4},
+	{0x9006d,0x18},
+	{0x9006e,0x0},
+	{0x9006f,0x4},
+	{0x90070,0x78},
+	{0x90071,0x549},
+	{0x90072,0x630},
+	{0x90073,0x159},
+	{0x90074,0xd49},
+	{0x90075,0x630},
+	{0x90076,0x159},
+	{0x90077,0x94a},
+	{0x90078,0x630},
+	{0x90079,0x159},
+	{0x9007a,0x441},
+	{0x9007b,0x630},
+	{0x9007c,0x149},
+	{0x9007d,0x42},
+	{0x9007e,0x630},
+	{0x9007f,0x149},
+	{0x90080,0x1},
+	{0x90081,0x630},
+	{0x90082,0x149},
+	{0x90083,0x0},
+	{0x90084,0xe0},
+	{0x90085,0x109},
+	{0x90086,0xa},
+	{0x90087,0x10},
+	{0x90088,0x109},
+	{0x90089,0x9},
+	{0x9008a,0x3c0},
+	{0x9008b,0x149},
+	{0x9008c,0x9},
+	{0x9008d,0x3c0},
+	{0x9008e,0x159},
+	{0x9008f,0x18},
+	{0x90090,0x10},
+	{0x90091,0x109},
+	{0x90092,0x0},
+	{0x90093,0x3c0},
+	{0x90094,0x109},
+	{0x90095,0x18},
+	{0x90096,0x4},
+	{0x90097,0x48},
+	{0x90098,0x18},
+	{0x90099,0x4},
+	{0x9009a,0x58},
+	{0x9009b,0xa},
+	{0x9009c,0x10},
+	{0x9009d,0x109},
+	{0x9009e,0x2},
+	{0x9009f,0x10},
+	{0x900a0,0x109},
+	{0x900a1,0x5},
+	{0x900a2,0x7c0},
+	{0x900a3,0x109},
+	{0x900a4,0x10},
+	{0x900a5,0x10},
+	{0x900a6,0x109},
+	{0x40000,0x811},
+	{0x40020,0x880},
+	{0x40040,0x0},
+	{0x40060,0x0},
+	{0x40001,0x4008},
+	{0x40021,0x83},
+	{0x40041,0x4f},
+	{0x40061,0x0},
+	{0x40002,0x4040},
+	{0x40022,0x83},
+	{0x40042,0x51},
+	{0x40062,0x0},
+	{0x40003,0x811},
+	{0x40023,0x880},
+	{0x40043,0x0},
+	{0x40063,0x0},
+	{0x40004,0x720},
+	{0x40024,0xf},
+	{0x40044,0x1740},
+	{0x40064,0x0},
+	{0x40005,0x16},
+	{0x40025,0x83},
+	{0x40045,0x4b},
+	{0x40065,0x0},
+	{0x40006,0x716},
+	{0x40026,0xf},
+	{0x40046,0x2001},
+	{0x40066,0x0},
+	{0x40007,0x716},
+	{0x40027,0xf},
+	{0x40047,0x2800},
+	{0x40067,0x0},
+	{0x40008,0x716},
+	{0x40028,0xf},
+	{0x40048,0xf00},
+	{0x40068,0x0},
+	{0x40009,0x720},
+	{0x40029,0xf},
+	{0x40049,0x1400},
+	{0x40069,0x0},
+	{0x4000a,0xe08},
+	{0x4002a,0xc15},
+	{0x4004a,0x0},
+	{0x4006a,0x0},
+	{0x4000b,0x623},
+	{0x4002b,0x15},
+	{0x4004b,0x0},
+	{0x4006b,0x0},
+	{0x4000c,0x4028},
+	{0x4002c,0x80},
+	{0x4004c,0x0},
+	{0x4006c,0x0},
+	{0x4000d,0xe08},
+	{0x4002d,0xc1a},
+	{0x4004d,0x0},
+	{0x4006d,0x0},
+	{0x4000e,0x623},
+	{0x4002e,0x1a},
+	{0x4004e,0x0},
+	{0x4006e,0x0},
+	{0x4000f,0x4040},
+	{0x4002f,0x80},
+	{0x4004f,0x0},
+	{0x4006f,0x0},
+	{0x40010,0x2604},
+	{0x40030,0x15},
+	{0x40050,0x0},
+	{0x40070,0x0},
+	{0x40011,0x708},
+	{0x40031,0x5},
+	{0x40051,0x0},
+	{0x40071,0x2002},
+	{0x40012,0x8},
+	{0x40032,0x80},
+	{0x40052,0x0},
+	{0x40072,0x0},
+	{0x40013,0x2604},
+	{0x40033,0x1a},
+	{0x40053,0x0},
+	{0x40073,0x0},
+	{0x40014,0x708},
+	{0x40034,0xa},
+	{0x40054,0x0},
+	{0x40074,0x2002},
+	{0x40015,0x4040},
+	{0x40035,0x80},
+	{0x40055,0x0},
+	{0x40075,0x0},
+	{0x40016,0x60a},
+	{0x40036,0x15},
+	{0x40056,0x1200},
+	{0x40076,0x0},
+	{0x40017,0x61a},
+	{0x40037,0x15},
+	{0x40057,0x1300},
+	{0x40077,0x0},
+	{0x40018,0x60a},
+	{0x40038,0x1a},
+	{0x40058,0x1200},
+	{0x40078,0x0},
+	{0x40019,0x642},
+	{0x40039,0x1a},
+	{0x40059,0x1300},
+	{0x40079,0x0},
+	{0x4001a,0x4808},
+	{0x4003a,0x880},
+	{0x4005a,0x0},
+	{0x4007a,0x0},
+	{0x900a7,0x0},
+	{0x900a8,0x790},
+	{0x900a9,0x11a},
+	{0x900aa,0x8},
+	{0x900ab,0x7aa},
+	{0x900ac,0x2a},
+	{0x900ad,0x10},
+	{0x900ae,0x7b2},
+	{0x900af,0x2a},
+	{0x900b0,0x0},
+	{0x900b1,0x7c8},
+	{0x900b2,0x109},
+	{0x900b3,0x10},
+	{0x900b4,0x2a8},
+	{0x900b5,0x129},
+	{0x900b6,0x8},
+	{0x900b7,0x370},
+	{0x900b8,0x129},
+	{0x900b9,0xa},
+	{0x900ba,0x3c8},
+	{0x900bb,0x1a9},
+	{0x900bc,0xc},
+	{0x900bd,0x408},
+	{0x900be,0x199},
+	{0x900bf,0x14},
+	{0x900c0,0x790},
+	{0x900c1,0x11a},
+	{0x900c2,0x8},
+	{0x900c3,0x4},
+	{0x900c4,0x18},
+	{0x900c5,0xe},
+	{0x900c6,0x408},
+	{0x900c7,0x199},
+	{0x900c8,0x8},
+	{0x900c9,0x8568},
+	{0x900ca,0x108},
+	{0x900cb,0x18},
+	{0x900cc,0x790},
+	{0x900cd,0x16a},
+	{0x900ce,0x8},
+	{0x900cf,0x1d8},
+	{0x900d0,0x169},
+	{0x900d1,0x10},
+	{0x900d2,0x8558},
+	{0x900d3,0x168},
+	{0x900d4,0x70},
+	{0x900d5,0x788},
+	{0x900d6,0x16a},
+	{0x900d7,0x1ff8},
+	{0x900d8,0x85a8},
+	{0x900d9,0x1e8},
+	{0x900da,0x50},
+	{0x900db,0x798},
+	{0x900dc,0x16a},
+	{0x900dd,0x60},
+	{0x900de,0x7a0},
+	{0x900df,0x16a},
+	{0x900e0,0x8},
+	{0x900e1,0x8310},
+	{0x900e2,0x168},
+	{0x900e3,0x8},
+	{0x900e4,0xa310},
+	{0x900e5,0x168},
+	{0x900e6,0xa},
+	{0x900e7,0x408},
+	{0x900e8,0x169},
+	{0x900e9,0x6e},
+	{0x900ea,0x0},
+	{0x900eb,0x68},
+	{0x900ec,0x0},
+	{0x900ed,0x408},
+	{0x900ee,0x169},
+	{0x900ef,0x0},
+	{0x900f0,0x8310},
+	{0x900f1,0x168},
+	{0x900f2,0x0},
+	{0x900f3,0xa310},
+	{0x900f4,0x168},
+	{0x900f5,0x1ff8},
+	{0x900f6,0x85a8},
+	{0x900f7,0x1e8},
+	{0x900f8,0x68},
+	{0x900f9,0x798},
+	{0x900fa,0x16a},
+	{0x900fb,0x78},
+	{0x900fc,0x7a0},
+	{0x900fd,0x16a},
+	{0x900fe,0x68},
+	{0x900ff,0x790},
+	{0x90100,0x16a},
+	{0x90101,0x8},
+	{0x90102,0x8b10},
+	{0x90103,0x168},
+	{0x90104,0x8},
+	{0x90105,0xab10},
+	{0x90106,0x168},
+	{0x90107,0xa},
+	{0x90108,0x408},
+	{0x90109,0x169},
+	{0x9010a,0x58},
+	{0x9010b,0x0},
+	{0x9010c,0x68},
+	{0x9010d,0x0},
+	{0x9010e,0x408},
+	{0x9010f,0x169},
+	{0x90110,0x0},
+	{0x90111,0x8b10},
+	{0x90112,0x168},
+	{0x90113,0x0},
+	{0x90114,0xab10},
+	{0x90115,0x168},
+	{0x90116,0x0},
+	{0x90117,0x1d8},
+	{0x90118,0x169},
+	{0x90119,0x80},
+	{0x9011a,0x790},
+	{0x9011b,0x16a},
+	{0x9011c,0x18},
+	{0x9011d,0x7aa},
+	{0x9011e,0x6a},
+	{0x9011f,0xa},
+	{0x90120,0x0},
+	{0x90121,0x1e9},
+	{0x90122,0x8},
+	{0x90123,0x8080},
+	{0x90124,0x108},
+	{0x90125,0xf},
+	{0x90126,0x408},
+	{0x90127,0x169},
+	{0x90128,0xc},
+	{0x90129,0x0},
+	{0x9012a,0x68},
+	{0x9012b,0x9},
+	{0x9012c,0x0},
+	{0x9012d,0x1a9},
+	{0x9012e,0x0},
+	{0x9012f,0x408},
+	{0x90130,0x169},
+	{0x90131,0x0},
+	{0x90132,0x8080},
+	{0x90133,0x108},
+	{0x90134,0x8},
+	{0x90135,0x7aa},
+	{0x90136,0x6a},
+	{0x90137,0x0},
+	{0x90138,0x8568},
+	{0x90139,0x108},
+	{0x9013a,0xb7},
+	{0x9013b,0x790},
+	{0x9013c,0x16a},
+	{0x9013d,0x1f},
+	{0x9013e,0x0},
+	{0x9013f,0x68},
+	{0x90140,0x8},
+	{0x90141,0x8558},
+	{0x90142,0x168},
+	{0x90143,0xf},
+	{0x90144,0x408},
+	{0x90145,0x169},
+	{0x90146,0xc},
+	{0x90147,0x0},
+	{0x90148,0x68},
+	{0x90149,0x0},
+	{0x9014a,0x408},
+	{0x9014b,0x169},
+	{0x9014c,0x0},
+	{0x9014d,0x8558},
+	{0x9014e,0x168},
+	{0x9014f,0x8},
+	{0x90150,0x3c8},
+	{0x90151,0x1a9},
+	{0x90152,0x3},
+	{0x90153,0x370},
+	{0x90154,0x129},
+	{0x90155,0x20},
+	{0x90156,0x2aa},
+	{0x90157,0x9},
+	{0x90158,0x0},
+	{0x90159,0x400},
+	{0x9015a,0x10e},
+	{0x9015b,0x8},
+	{0x9015c,0xe8},
+	{0x9015d,0x109},
+	{0x9015e,0x0},
+	{0x9015f,0x8140},
+	{0x90160,0x10c},
+	{0x90161,0x10},
+	{0x90162,0x8138},
+	{0x90163,0x10c},
+	{0x90164,0x8},
+	{0x90165,0x7c8},
+	{0x90166,0x101},
+	{0x90167,0x8},
+	{0x90168,0x0},
+	{0x90169,0x8},
+	{0x9016a,0x8},
+	{0x9016b,0x448},
+	{0x9016c,0x109},
+	{0x9016d,0xf},
+	{0x9016e,0x7c0},
+	{0x9016f,0x109},
+	{0x90170,0x0},
+	{0x90171,0xe8},
+	{0x90172,0x109},
+	{0x90173,0x47},
+	{0x90174,0x630},
+	{0x90175,0x109},
+	{0x90176,0x8},
+	{0x90177,0x618},
+	{0x90178,0x109},
+	{0x90179,0x8},
+	{0x9017a,0xe0},
+	{0x9017b,0x109},
+	{0x9017c,0x0},
+	{0x9017d,0x7c8},
+	{0x9017e,0x109},
+	{0x9017f,0x8},
+	{0x90180,0x8140},
+	{0x90181,0x10c},
+	{0x90182,0x0},
+	{0x90183,0x1},
+	{0x90184,0x8},
+	{0x90185,0x8},
+	{0x90186,0x4},
+	{0x90187,0x8},
+	{0x90188,0x8},
+	{0x90189,0x7c8},
+	{0x9018a,0x101},
+	{0x90006,0x0},
+	{0x90007,0x0},
+	{0x90008,0x8},
+	{0x90009,0x0},
+	{0x9000a,0x0},
+	{0x9000b,0x0},
+	{0xd00e7,0x400},
+	{0x90017,0x0},
+	{0x9001f,0x2a},
+	{0x90026,0x6a},
+	{0x400d0,0x0},
+	{0x400d1,0x101},
+	{0x400d2,0x105},
+	{0x400d3,0x107},
+	{0x400d4,0x10f},
+	{0x400d5,0x202},
+	{0x400d6,0x20a},
+	{0x400d7,0x20b},
+	{0x2003a,0x2},
+	{0x2000b,0x5d},
+	{0x2000c,0xbb},
+	{0x2000d,0x753},
+	{0x2000e,0x2c},
+	{0x12000b,0xc},
+	{0x12000c,0x19},
+	{0x12000d,0xfa},
+	{0x12000e,0x10},
+	{0x22000b,0x3},
+	{0x22000c,0x6},
+	{0x22000d,0x3e},
+	{0x22000e,0x10},
+	{0x9000c,0x0},
+	{0x9000d,0x173},
+	{0x9000e,0x60},
+	{0x9000f,0x6110},
+	{0x90010,0x2152},
+	{0x90011,0xdfbd},
+	{0x90012,0x60},
+	{0x90013,0x6152},
+	{0x20010,0x5a},
+	{0x20011,0x3},
+	{0x120010,0x5a},
+	{0x120011,0x3},
+	{0x220010,0x5a},
+	{0x220011,0x3},
+	{0x40080,0xe0},
+	{0x40081,0x12},
+	{0x40082,0xe0},
+	{0x40083,0x12},
+	{0x40084,0xe0},
+	{0x40085,0x12},
+	{0x140080,0xe0},
+	{0x140081,0x12},
+	{0x140082,0xe0},
+	{0x140083,0x12},
+	{0x140084,0xe0},
+	{0x140085,0x12},
+	{0x240080,0xe0},
+	{0x240081,0x12},
+	{0x240082,0xe0},
+	{0x240083,0x12},
+	{0x240084,0xe0},
+	{0x240085,0x12},
+	{0x400fd,0xf},
+	{0x10011,0x1},
+	{0x10012,0x1},
+	{0x10013,0x180},
+	{0x10018,0x1},
+	{0x10002,0x6209},
+	{0x100b2,0x1},
+	{0x101b4,0x1},
+	{0x102b4,0x1},
+	{0x103b4,0x1},
+	{0x104b4,0x1},
+	{0x105b4,0x1},
+	{0x106b4,0x1},
+	{0x107b4,0x1},
+	{0x108b4,0x1},
+	{0x11011,0x1},
+	{0x11012,0x1},
+	{0x11013,0x180},
+	{0x11018,0x1},
+	{0x11002,0x6209},
+	{0x110b2,0x1},
+	{0x111b4,0x1},
+	{0x112b4,0x1},
+	{0x113b4,0x1},
+	{0x114b4,0x1},
+	{0x115b4,0x1},
+	{0x116b4,0x1},
+	{0x117b4,0x1},
+	{0x118b4,0x1},
+	{0x12011,0x1},
+	{0x12012,0x1},
+	{0x12013,0x180},
+	{0x12018,0x1},
+	{0x12002,0x6209},
+	{0x120b2,0x1},
+	{0x121b4,0x1},
+	{0x122b4,0x1},
+	{0x123b4,0x1},
+	{0x124b4,0x1},
+	{0x125b4,0x1},
+	{0x126b4,0x1},
+	{0x127b4,0x1},
+	{0x128b4,0x1},
+	{0x13011,0x1},
+	{0x13012,0x1},
+	{0x13013,0x180},
+	{0x13018,0x1},
+	{0x13002,0x6209},
+	{0x130b2,0x1},
+	{0x131b4,0x1},
+	{0x132b4,0x1},
+	{0x133b4,0x1},
+	{0x134b4,0x1},
+	{0x135b4,0x1},
+	{0x136b4,0x1},
+	{0x137b4,0x1},
+	{0x138b4,0x1},
+	{0x2003a,0x2},
+	{0xc0080,0x2},
+	{0xd0000, 0x1}
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3000, 400, 100, },
+};
+
diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c
index 4ef7f6f1806..c93fbd42ed6 100644
--- a/board/freescale/imx8mm_evk/spl.c
+++ b/board/freescale/imx8mm_evk/spl.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
  */
 
 #include <common.h>
@@ -20,13 +20,18 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/arch/ddr.h>
 
-#include <dm/uclass.h>
-#include <dm/device.h>
-#include <dm/uclass-internal.h>
-#include <dm/device-internal.h>
-
 #include <power/pmic.h>
+#ifdef CONFIG_POWER_PCA9450
 #include <power/pca9450.h>
+#else
+#include <power/bd71837.h>
+#endif
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <linux/delay.h>
+#include <fsl_sec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -39,101 +44,263 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
 	case SD3_BOOT:
 	case MMC3_BOOT:
 		return BOOT_DEVICE_MMC2;
+	case QSPI_BOOT:
+		return BOOT_DEVICE_NOR;
+	case NAND_BOOT:
+		return BOOT_DEVICE_NAND;
+	case USB_BOOT:
+		return BOOT_DEVICE_BOARD;
 	default:
 		return BOOT_DEVICE_NONE;
 	}
 }
 
-static void spl_dram_init(void)
+void spl_dram_init(void)
 {
 	ddr_init(&dram_timing);
 }
 
-void spl_board_init(void)
-{
-	puts("Normal Boot\n");
-}
+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MM_PAD_I2C1_SCL_I2C1_SCL | PC,
+		.gpio_mode = IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MM_PAD_I2C1_SDA_I2C1_SDA | PC,
+		.gpio_mode = IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
 
-#ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
-{
-	/* Just empty function now - can't decide what to choose */
-	debug("%s: %s\n", __func__, name);
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 18)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IMX8MM_PAD_NAND_WE_B_USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_WP_B_USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
 
-	return 0;
-}
-#endif
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
 
-#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+/*
+ * The evk board uses DAT3 to detect CD card plugin,
+ * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
+ */
+static iomux_v3_cfg_t const usdhc2_cd_pad =
+	IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL);
 
-static iomux_v3_cfg_t const uart_pads[] = {
-	IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
+static iomux_v3_cfg_t const usdhc2_dat3_pad =
+	IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
+	MUX_PAD_CTRL(USDHC_PAD_CTRL);
 
-static iomux_v3_cfg_t const wdog_pads[] = {
-	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC2_BASE_ADDR, 0, 4},
+	{USDHC3_BASE_ADDR, 0, 8},
 };
 
-int board_early_init_f(void)
+int board_mmc_init(struct bd_info *bis)
 {
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
-	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			init_clk_usdhc(1);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+			gpio_direction_output(USDHC2_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			break;
+		case 1:
+			init_clk_usdhc(2);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
 
-	set_wdog_reset(wdog);
+	return 0;
+}
 
-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC3_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		imx_iomux_v3_setup_pad(usdhc2_cd_pad);
+		gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
+		gpio_direction_input(USDHC2_CD_GPIO);
+
+		/*
+		 * Since it is the DAT3 pin, this pin is pulled to
+		 * low voltage if no card
+		 */
+		ret = gpio_get_value(USDHC2_CD_GPIO);
+
+		imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
+		return ret;
+	}
 
-	return 0;
+	return 1;
 }
 
-static int power_init_board(void)
+#if CONFIG_IS_ENABLED(POWER_LEGACY)
+#define I2C_PMIC	0
+#ifdef CONFIG_POWER_PCA9450
+int power_init_board(void)
 {
-	struct udevice *dev;
+	struct pmic *p;
 	int ret;
 
-	ret = pmic_get("pca9450@25", &dev);
-	if (ret == -ENODEV) {
-		puts("No pmic\n");
-		return 0;
-	}
-	if (ret != 0)
-		return ret;
+	ret = power_pca9450_init(I2C_PMIC, 0x25);
+	if (ret)
+		printf("power init failed");
+	p = pmic_get("PCA9450");
+	pmic_probe(p);
 
 	/* BUCKxOUT_DVS0/1 control BUCK123 output */
-	pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+	pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
 
 	/* Buck 1 DVS control through PMIC_STBY_REQ */
-	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+	pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
 
 	/* Set DVS1 to 0.8v for suspend */
-	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x10);
+	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x10);
 
 	/* increase VDD_DRAM to 0.95v for 3Ghz DDR */
-	pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1C);
+	pmic_reg_write(p, PCA9450_BUCK3OUT_DVS0, 0x1C);
 
 	/* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */
-	pmic_reg_write(dev, PCA9450_BUCK3CTRL, 0x4a);
+	pmic_reg_write(p, PCA9450_BUCK3CTRL, 0x4a);
 
 	/* set VDD_SNVS_0V8 from default 0.85V */
-	pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
+	pmic_reg_write(p, PCA9450_LDO2CTRL, 0xC0);
 
 	/* set WDOG_B_CFG to cold reset */
-	pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
+	pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
+
+	return 0;
+}
+#else
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+
+	ret = power_bd71837_init(I2C_PMIC);
+	if (ret)
+		printf("power init failed");
+
+	p = pmic_get("BD71837");
+	pmic_probe(p);
+
+
+	/* decrease RESET key long push time from the default 10s to 10ms */
+	pmic_reg_write(p, BD718XX_PWRONCONFIG1, 0x0);
+
+	/* unlock the PMIC regs */
+	pmic_reg_write(p, BD718XX_REGLOCK, 0x1);
+
+	/* increase VDD_SOC to typical value 0.85v before first DRAM access */
+	pmic_reg_write(p, BD718XX_BUCK1_VOLT_RUN, 0x0f);
+
+	/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
+	pmic_reg_write(p, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
+
+#ifndef CONFIG_IMX8M_LPDDR4
+	/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
+	pmic_reg_write(p, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
+#endif
+
+	/* lock the PMIC regs */
+	pmic_reg_write(p, BD718XX_REGLOCK, 0x11);
 
 	return 0;
 }
+#endif
+#endif
+
+void spl_board_init(void)
+{
+	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+		if (sec_init())
+			printf("\nsec_init failed!\n");
+	}
+
+#ifndef CONFIG_SPL_USB_SDP_SUPPORT
+	/* Serial download mode */
+	if (is_usb_boot()) {
+		puts("Back to ROM, SDP\n");
+		restore_boot_params();
+	}
+#endif
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
 
 void board_init_f(ulong dummy)
 {
-	struct udevice *dev;
 	int ret;
 
-	arch_cpu_init();
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
 
-	init_uart_clk(1);
+	arch_cpu_init();
 
 	board_early_init_f();
 
@@ -141,25 +308,17 @@ void board_init_f(ulong dummy)
 
 	preloader_console_init();
 
-	/* Clear the BSS. */
-	memset(__bss_start, 0, __bss_end - __bss_start);
-
-	ret = spl_early_init();
+	ret = spl_init();
 	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
-	ret = uclass_get_device_by_name(UCLASS_CLK,
-					"clock-controller@30380000",
-					&dev);
-	if (ret < 0) {
-		printf("Failed to find clock node. Check device tree\n");
+		debug("spl_init() failed: %d\n", ret);
 		hang();
 	}
 
 	enable_tzc380();
 
+	/* Adjust pmic voltage to 1.0V for 800M */
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
 	power_init_board();
 
 	/* DDR initialization */
diff --git a/board/freescale/imx8mm_val/Kconfig b/board/freescale/imx8mm_val/Kconfig
new file mode 100644
index 00000000000..ebffc883636
--- /dev/null
+++ b/board/freescale/imx8mm_val/Kconfig
@@ -0,0 +1,17 @@
+ if TARGET_IMX8MM_DDR4_VAL || TARGET_IMX8MM_DDR3L_VAL
+
+config SYS_BOARD
+	default "imx8mm_val"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx8mm_val"
+
+config IMX_CONFIG
+	default "board/freescale/imx8mm_val/imximage-8mm.cfg"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/imx8mm_val/Makefile b/board/freescale/imx8mm_val/Makefile
new file mode 100644
index 00000000000..1871b53a3d5
--- /dev/null
+++ b/board/freescale/imx8mm_val/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mm_val.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
+obj-$(CONFIG_IMX8M_DDR3L) += ddr3l_timing.o
+endif
diff --git a/board/freescale/imx8mm_val/ddr3l_timing.c b/board/freescale/imx8mm_val/ddr3l_timing.c
new file mode 100644
index 00000000000..467476d788c
--- /dev/null
+++ b/board/freescale/imx8mm_val/ddr3l_timing.c
@@ -0,0 +1,1384 @@
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr3l_ddrc_cfg[] = {
+	{ DDRC_MSTR(0), 0xa3040001 },
+	{ DDRC_PWRCTL(0), 0x000000a8 },
+	{ DDRC_PWRTMG(0), 0x00532203 },
+	{ DDRC_RFSHCTL0(0), 0x00203020 },
+	{ DDRC_RFSHCTL1(0), 0x0001000d },
+	{ DDRC_RFSHCTL3(0), 0x00000000 },
+	{ DDRC_RFSHTMG(0), 0x0061008c },
+	{ DDRC_CRCPARCTL0(0), 0x00000000 },
+	{ DDRC_CRCPARCTL1(0), 0x00000000 },
+	{ DDRC_INIT0(0), 0xc0030002 },
+	{ DDRC_INIT1(0), 0x0001000b },
+	{ DDRC_INIT2(0), 0x00006303 },
+	{ DDRC_INIT3(0), 0x0d700004 },/* MR1, MR0 */
+	{ DDRC_INIT4(0), 0x00180000 },/* MR2 */
+	{ DDRC_INIT5(0), 0x00090071 },
+	{ DDRC_INIT6(0), 0x00000000 },
+	{ DDRC_INIT7(0), 0x00000000 },
+	{ DDRC_DIMMCTL(0), 0x00000032 }, /* [1] dimm_addr_mirr_en, it will effect the MRS if use umctl2 to initi dram. */
+	{ DDRC_RANKCTL(0), 0x00000ee5 },
+	{ DDRC_DRAMTMG0(0), 0x0c101a0e },
+	{ DDRC_DRAMTMG1(0), 0x000a0314 },
+	{ DDRC_DRAMTMG2(0), 0x04060509 },
+	{ DDRC_DRAMTMG3(0), 0x00002006 },
+	{ DDRC_DRAMTMG4(0), 0x06020306 },
+	{ DDRC_DRAMTMG5(0), 0x0b060202 },
+	{ DDRC_DRAMTMG6(0), 0x060a0009 },
+	{ DDRC_DRAMTMG7(0), 0x0000060b },
+	{ DDRC_DRAMTMG8(0), 0x01017c0a },
+	{ DDRC_DRAMTMG9(0), 0x4000000e },
+	{ DDRC_DRAMTMG10(0), 0x00070803 },
+	{ DDRC_DRAMTMG11(0), 0x0101000b },
+	{ DDRC_DRAMTMG12(0), 0x00000000 },
+	{ DDRC_DRAMTMG13(0), 0x5d000000 },
+	{ DDRC_DRAMTMG14(0), 0x00000b39 },
+	{ DDRC_DRAMTMG15(0), 0x80000000 },
+	{ DDRC_DRAMTMG17(0), 0x00f1006a },
+	{ DDRC_ZQCTL0(0), 0x50800020 },
+	{ DDRC_ZQCTL1(0), 0x00000070 },
+	{ DDRC_ZQCTL2(0), 0x00000000 },
+	{ DDRC_DFITMG0(0), 0x03868203 },
+	{ DDRC_DFITMG1(0), 0x00020103 },
+	{ DDRC_DFILPCFG0(0), 0x07713021 },
+	{ DDRC_DFILPCFG1(0), 0x00000010 },
+	{ DDRC_DFIUPD0(0), 0xe0400018 },
+	{ DDRC_DFIUPD1(0), 0x0005003c },
+	{ DDRC_DFIUPD2(0), 0x80000000 },
+	{ DDRC_DFIMISC(0), 0x00000001 },
+	{ DDRC_DFITMG2(0), 0x00000603 },
+	{ DDRC_DFITMG3(0), 0x00000001 },
+	{ DDRC_DBICTL(0), 0x00000001 },
+	{ DDRC_DFIPHYMSTR(0), 0x00000000 },
+
+	{ DDRC_ADDRMAP0(0), 0x00000016 }, /* [4:0] cs-bit0: 6+22=28; [12:8] cs-bit1: 7+0 */
+	{ DDRC_ADDRMAP1(0), 0x00080808 }, /* [5:0] bank b0: 2+8; [13:8] b1: P3+8 ; [21:16] b2: 4+8 */
+	{ DDRC_ADDRMAP2(0), 0x00000000 }, /* [3:0] col-b2: 2;  [11:8] col-b3: 3; [19:16] col-b4: 4 ; [27:24] col-b5: 5 */
+	{ DDRC_ADDRMAP3(0), 0x00000000 }, /* [3:0] col-b6: 6;  [11:8] col-b7: 7; [19:16] col-b8: 8 ; [27:24] col-b9: 9 */
+	{ DDRC_ADDRMAP4(0), 0x00001f1f }, /* col-b10, col-b11 not used */
+	{ DDRC_ADDRMAP5(0), 0x07070707 }, /* [3:0] row-b0: 6;  [11:8] row-b1: 7; [19:16] row-b2_b10 ; [27:24] row-b11: 17 */
+	{ DDRC_ADDRMAP6(0), 0x0f070707 }, /* [3:0] row-b12:18; [11:8] row-b13: 19; [19:16] row-b14:20 */
+	{ DDRC_ADDRMAP7(0), 0x00000f0f },
+	{ DDRC_ADDRMAP8(0), 0x00000000 }, /* [5:0] bg-b0; [13:8]bg-b1 */
+	{ DDRC_ADDRMAP9(0), 0x0a020b06 }, /*  it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
+	{ DDRC_ADDRMAP10(0), 0x0a0a0a0a },/*  it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
+	{ DDRC_ADDRMAP11(0), 0x00000000 },
+
+	{ DDRC_ODTCFG(0), 0x041d0f5c },
+	{ DDRC_ODTMAP(0), 0x00000201 },
+	{ DDRC_SCHED(0), 0x7ab50b07 },
+	{ DDRC_SCHED1(0), 0x00000022 },
+	{ DDRC_PERFHPR1(0), 0x7b00665e },
+	{ DDRC_PERFLPR1(0), 0x2b00c4e1 },
+	{ DDRC_PERFWR1(0), 0xb700c9fe },
+	{ DDRC_DBG0(0), 0x00000017 },
+	{ DDRC_DBG1(0), 0x00000000 },
+	{ DDRC_DBGCMD(0), 0x00000000 },
+	{ DDRC_SWCTL(0), 0x00000001 },
+	{ DDRC_POISONCFG(0), 0x00010000 },
+	{ DDRC_PCCFG(0), 0x00000100 },
+	{ DDRC_PCFGR_0(0), 0x00003051 },
+	{ DDRC_PCFGW_0(0), 0x000061d2 },
+	{ DDRC_PCTRL_0(0), 0x00000001 },
+	{ DDRC_PCFGQOS0_0(0), 0x02100b04 },
+	{ DDRC_PCFGQOS1_0(0), 0x003f0353 },
+	{ DDRC_PCFGWQOS0_0(0), 0x00000002 },
+	{ DDRC_PCFGWQOS1_0(0), 0x000005fd },
+
+	{ DDRC_FREQ1_RFSHCTL0(0), 0x00d19034 },
+	{ DDRC_FREQ1_RFSHTMG(0), 0x0040805e },
+	{ DDRC_FREQ1_INIT3(0), 0x09300004 },
+	{ DDRC_FREQ1_INIT4(0), 0x00080000 },
+	{ DDRC_FREQ1_INIT6(0), 0x00000000 },
+	{ DDRC_FREQ1_INIT7(0), 0x00000000 },
+	{ DDRC_FREQ1_DRAMTMG0(0), 0x090e110a },
+	{ DDRC_FREQ1_DRAMTMG1(0), 0x0007020e },
+	{ DDRC_FREQ1_DRAMTMG2(0), 0x03040407 },
+	{ DDRC_FREQ1_DRAMTMG3(0), 0x00002006 },
+	{ DDRC_FREQ1_DRAMTMG4(0), 0x04020304 }, /*  tRP=6 --> 7 */
+	{ DDRC_FREQ1_DRAMTMG5(0), 0x09030202 },
+	{ DDRC_FREQ1_DRAMTMG6(0), 0x0c020000 },
+	{ DDRC_FREQ1_DRAMTMG7(0), 0x00000309 },
+	{ DDRC_FREQ1_DRAMTMG8(0), 0x01010a06 },
+	{ DDRC_FREQ1_DRAMTMG9(0), 0x00000003 },
+	{ DDRC_FREQ1_DRAMTMG10(0), 0x00090906 },
+	{ DDRC_FREQ1_DRAMTMG11(0), 0x01010011 },
+	{ DDRC_FREQ1_DRAMTMG12(0), 0x00000000 },
+	{ DDRC_FREQ1_DRAMTMG13(0), 0x40000000 },
+	{ DDRC_FREQ1_DRAMTMG14(0), 0x000000f3 },
+	{ DDRC_FREQ1_DRAMTMG15(0), 0x80000000 },
+	{ DDRC_FREQ1_DRAMTMG17(0), 0x001a0046 },
+	{ DDRC_FREQ1_ZQCTL0(0),  0x50800020 },
+	{ DDRC_FREQ1_DFITMG0(0), 0x03828201 },
+	{ DDRC_FREQ1_DFITMG1(0), 0x00020103 },
+	{ DDRC_FREQ1_DFITMG2(0), 0x00000201 },
+	{ DDRC_FREQ1_DFITMG3(0), 0x00000001 },
+	{ DDRC_FREQ1_ODTCFG(0),  0x0a1a0768 },
+
+	{ DDRC_FREQ2_RFSHCTL0(0), 0x00208014 },
+	{ DDRC_FREQ2_RFSHTMG(0), 0x00308046 },
+	{ DDRC_FREQ2_INIT3(0), 0x05200004 },
+	{ DDRC_FREQ2_INIT4(0), 0x00000000 },
+	{ DDRC_FREQ2_INIT6(0), 0x00000000 },
+	{ DDRC_FREQ2_INIT7(0), 0x00000000 },
+	{ DDRC_FREQ2_DRAMTMG0(0), 0x070a0c07 },
+	{ DDRC_FREQ2_DRAMTMG1(0), 0x0005020b },
+	{ DDRC_FREQ2_DRAMTMG2(0), 0x03030407 },
+	{ DDRC_FREQ2_DRAMTMG3(0), 0x00002006 },
+	{ DDRC_FREQ2_DRAMTMG4(0), 0x03020204 },
+	{ DDRC_FREQ2_DRAMTMG5(0), 0x04070302 },
+	{ DDRC_FREQ2_DRAMTMG6(0), 0x07080000 },
+	{ DDRC_FREQ2_DRAMTMG7(0), 0x00000704 },
+	{ DDRC_FREQ2_DRAMTMG8(0), 0x02026804 },
+	{ DDRC_FREQ2_DRAMTMG9(0), 0x40000006 },
+	{ DDRC_FREQ2_DRAMTMG10(0), 0x000c0b08 },
+	{ DDRC_FREQ2_DRAMTMG11(0), 0x01010015 },
+	{ DDRC_FREQ2_DRAMTMG12(0), 0x00000000 },
+	{ DDRC_FREQ2_DRAMTMG13(0), 0x51000000 },
+	{ DDRC_FREQ2_DRAMTMG14(0), 0x000002a0 },
+	{ DDRC_FREQ2_DRAMTMG15(0), 0x00000000 },
+	{ DDRC_FREQ2_DRAMTMG17(0), 0x008c0039 },
+	{ DDRC_FREQ2_ZQCTL0(0), 0x50800020 },
+	{ DDRC_FREQ2_DFITMG0(0), 0x03818200 },
+	{ DDRC_FREQ2_DFITMG1(0), 0x00020103 },
+	{ DDRC_FREQ2_DFITMG2(0), 0x00000100 },
+	{ DDRC_FREQ2_DFITMG3(0), 0x00000001 },
+	{ DDRC_FREQ2_ODTCFG(0), 0x04050800 },
+
+	/* default start freq point */
+	{ DDRC_MSTR2(0), 0x2},
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr3l_ddrphy_cfg[] = {
+	{ 0x1005f, 0x3cf },
+	{ 0x1015f, 0x3cf },
+	{ 0x1105f, 0x3cf },
+	{ 0x1115f, 0x3cf },
+	{ 0x1205f, 0x3cf },
+	{ 0x1215f, 0x3cf },
+	{ 0x1305f, 0x3cf },
+	{ 0x1315f, 0x3cf },
+
+	{ 0x11005f, 0x3cf },
+	{ 0x11015f, 0x3cf },
+	{ 0x11105f, 0x3cf },
+	{ 0x11115f, 0x3cf },
+	{ 0x11205f, 0x3cf },
+	{ 0x11215f, 0x3cf },
+	{ 0x11305f, 0x3cf },
+	{ 0x11315f, 0x3cf },
+
+	{ 0x21005f, 0x3cf },
+	{ 0x21015f, 0x3cf },
+	{ 0x21105f, 0x3cf },
+	{ 0x21115f, 0x3cf },
+	{ 0x21205f, 0x3cf },
+	{ 0x21215f, 0x3cf },
+	{ 0x21305f, 0x3cf },
+	{ 0x21315f, 0x3cf },
+
+	{ 0x55, 0x365 },
+	{ 0x1055, 0x365 },
+	{ 0x2055, 0x365 },
+	{ 0x3055, 0x365 },
+	{ 0x4055, 0x65 },
+	{ 0x5055, 0x65 },
+	{ 0x6055, 0x365 },
+	{ 0x7055, 0x365 },
+	{ 0x8055, 0x365 },
+	{ 0x9055, 0x365 },
+	{ 0x200c5, 0xb },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x1 },
+	{ 0x12002e, 0x1 },
+	{ 0x22002e, 0x1 },
+	{ 0x20024, 0x8 },
+	{ 0x2003a, 0x0 },
+	{ 0x120024, 0x8 },
+	{ 0x2003a, 0x0 },
+	{ 0x220024, 0x8 },
+	{ 0x2003a, 0x0 },
+	{ 0x20056, 0xa },
+	{ 0x120056, 0xa },
+	{ 0x220056, 0xa },
+	{ 0x1004d, 0x618 },
+	{ 0x1014d, 0x618 },
+	{ 0x1104d, 0x618 },
+	{ 0x1114d, 0x618 },
+	{ 0x1204d, 0x618 },
+	{ 0x1214d, 0x618 },
+	{ 0x1304d, 0x618 },
+	{ 0x1314d, 0x618 },
+	{ 0x11004d, 0x618 },
+	{ 0x11014d, 0x618 },
+	{ 0x11104d, 0x618 },
+	{ 0x11114d, 0x618 },
+	{ 0x11204d, 0x618 },
+	{ 0x11214d, 0x618 },
+	{ 0x11304d, 0x618 },
+	{ 0x11314d, 0x618 },
+	{ 0x21004d, 0x618 },
+	{ 0x21014d, 0x618 },
+	{ 0x21104d, 0x618 },
+	{ 0x21114d, 0x618 },
+	{ 0x21204d, 0x618 },
+	{ 0x21214d, 0x618 },
+	{ 0x21304d, 0x618 },
+	{ 0x21314d, 0x618 },
+	{ 0x10049, 0xe38 },
+	{ 0x10149, 0xe38 },
+	{ 0x11049, 0xe38 },
+	{ 0x11149, 0xe38 },
+	{ 0x12049, 0xe38 },
+	{ 0x12149, 0xe38 },
+	{ 0x13049, 0xe38 },
+	{ 0x13149, 0xe38 },
+	{ 0x110049, 0xe38 },
+	{ 0x110149, 0xe38 },
+	{ 0x111049, 0xe38 },
+	{ 0x111149, 0xe38 },
+	{ 0x112049, 0xe38 },
+	{ 0x112149, 0xe38 },
+	{ 0x113049, 0xe38 },
+	{ 0x113149, 0xe38 },
+	{ 0x210049, 0xe38 },
+	{ 0x210149, 0xe38 },
+	{ 0x211049, 0xe38 },
+	{ 0x211149, 0xe38 },
+	{ 0x212049, 0xe38 },
+	{ 0x212149, 0xe38 },
+	{ 0x213049, 0xe38 },
+	{ 0x213149, 0xe38 },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x5 },
+	{ 0x20075, 0x0 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x190 },
+	{ 0x120008, 0x85 },
+	{ 0x220008, 0x53 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0xf8 },
+	{ 0x10043, 0x581 },
+	{ 0x10143, 0x581 },
+	{ 0x11043, 0x581 },
+	{ 0x11143, 0x581 },
+	{ 0x12043, 0x581 },
+	{ 0x12143, 0x581 },
+	{ 0x13043, 0x581 },
+	{ 0x13143, 0x581 },
+	{ 0x1200b2, 0xf8 },
+	{ 0x110043, 0x581 },
+	{ 0x110143, 0x581 },
+	{ 0x111043, 0x581 },
+	{ 0x111143, 0x581 },
+	{ 0x112043, 0x581 },
+	{ 0x112143, 0x581 },
+	{ 0x113043, 0x581 },
+	{ 0x113143, 0x581 },
+	{ 0x2200b2, 0xf8 },
+	{ 0x210043, 0x581 },
+	{ 0x210143, 0x581 },
+	{ 0x211043, 0x581 },
+	{ 0x211143, 0x581 },
+	{ 0x212043, 0x581 },
+	{ 0x212143, 0x581 },
+	{ 0x213043, 0x581 },
+	{ 0x213143, 0x581 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x5 },
+	{ 0x120019, 0x5 },
+	{ 0x220019, 0x5 },
+	{ 0x200f0, 0x5555 },
+	{ 0x200f1, 0x5555 },
+	{ 0x200f2, 0x5555 },
+	{ 0x200f3, 0x5555 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0x5555 },
+	{ 0x200f6, 0x5555 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+};
+
+/* ddr phy trained CSR */
+struct dram_cfg_param ddr3l_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr3l_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0x640 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x0 },
+	{ 0x54006, 0x140 },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x303 },
+	{ 0x54009, 0x200 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x31f },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0xd70 },
+	{ 0x54030, 0x4 },
+	{ 0x54031, 0x18 },
+	{ 0x5403a, 0x1221 },
+	{ 0x5403b, 0x4884 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr3l_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x1 },
+	{ 0x54003, 0x214 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x0 },
+	{ 0x54006, 0x140 },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x303 },
+	{ 0x54009, 0x200 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x21f },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x930 },
+	{ 0x54030, 0x4 },
+	{ 0x54031, 0x8 },
+	{ 0x5403a, 0x1221 },
+	{ 0x5403b, 0x4884 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr3l_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x2 },
+	{ 0x54003, 0x14c },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x0 },
+	{ 0x54006, 0x140 },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x303 },
+	{ 0x54009, 0x200 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x21f },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x520 },
+	{ 0x54030, 0x4 },
+	{ 0x54031, 0x0 },
+	{ 0x5403a, 0x1221 },
+	{ 0x5403b, 0x4884 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr3l_phy_pie[] = {
+	{ 0xd0000, 0x0 }, /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	{ 0x90000, 0x10 }, /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */
+	{ 0x90001, 0x400 }, /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */
+	{ 0x90002, 0x10e }, /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */
+	{ 0x90003, 0x0 }, /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */
+	{ 0x90004, 0x0 }, /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */
+	{ 0x90005, 0x8 }, /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */
+	{ 0x90029, 0xb }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */
+	{ 0x9002a, 0x480 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */
+	{ 0x9002b, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */
+	{ 0x9002c, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */
+	{ 0x9002d, 0x448 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */
+	{ 0x9002e, 0x139 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */
+	{ 0x9002f, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */
+	{ 0x90030, 0x478 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */
+	{ 0x90031, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */
+	{ 0x90032, 0x2 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */
+	{ 0x90033, 0x10 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */
+	{ 0x90034, 0x139 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */
+	{ 0x90035, 0xf }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */
+	{ 0x90036, 0x7c0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */
+	{ 0x90037, 0x139 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */
+	{ 0x90038, 0x44 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */
+	{ 0x90039, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */
+	{ 0x9003a, 0x159 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */
+	{ 0x9003b, 0x14f }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */
+	{ 0x9003c, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */
+	{ 0x9003d, 0x159 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */
+	{ 0x9003e, 0x47 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */
+	{ 0x9003f, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */
+	{ 0x90040, 0x149 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */
+	{ 0x90041, 0x4f }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */
+	{ 0x90042, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */
+	{ 0x90043, 0x179 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */
+	{ 0x90044, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */
+	{ 0x90045, 0xe0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */
+	{ 0x90046, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */
+	{ 0x90047, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */
+	{ 0x90048, 0x7c8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */
+	{ 0x90049, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */
+	{ 0x9004a, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */
+	{ 0x9004b, 0x1 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */
+	{ 0x9004c, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */
+	{ 0x9004d, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */
+	{ 0x9004e, 0x45a }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */
+	{ 0x9004f, 0x9 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */
+	{ 0x90050, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */
+	{ 0x90051, 0x448 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */
+	{ 0x90052, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */
+	{ 0x90053, 0x40 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */
+	{ 0x90054, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */
+	{ 0x90055, 0x179 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */
+	{ 0x90056, 0x1 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */
+	{ 0x90057, 0x618 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */
+	{ 0x90058, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */
+	{ 0x90059, 0x40c0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */
+	{ 0x9005a, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */
+	{ 0x9005b, 0x149 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */
+	{ 0x9005c, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */
+	{ 0x9005d, 0x4 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */
+	{ 0x9005e, 0x48 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */
+	{ 0x9005f, 0x4040 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */
+	{ 0x90060, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */
+	{ 0x90061, 0x149 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */
+	{ 0x90062, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */
+	{ 0x90063, 0x4 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */
+	{ 0x90064, 0x48 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */
+	{ 0x90065, 0x40 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */
+	{ 0x90066, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */
+	{ 0x90067, 0x149 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */
+	{ 0x90068, 0x10 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */
+	{ 0x90069, 0x4 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */
+	{ 0x9006a, 0x18 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */
+	{ 0x9006b, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */
+	{ 0x9006c, 0x4 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */
+	{ 0x9006d, 0x78 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */
+	{ 0x9006e, 0x549 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */
+	{ 0x9006f, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */
+	{ 0x90070, 0x159 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */
+	{ 0x90071, 0xd49 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */
+	{ 0x90072, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */
+	{ 0x90073, 0x159 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */
+	{ 0x90074, 0x94a }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */
+	{ 0x90075, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */
+	{ 0x90076, 0x159 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */
+	{ 0x90077, 0x441 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */
+	{ 0x90078, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */
+	{ 0x90079, 0x149 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */
+	{ 0x9007a, 0x42 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */
+	{ 0x9007b, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */
+	{ 0x9007c, 0x149 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */
+	{ 0x9007d, 0x1 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */
+	{ 0x9007e, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */
+	{ 0x9007f, 0x149 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */
+	{ 0x90080, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */
+	{ 0x90081, 0xe0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */
+	{ 0x90082, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */
+	{ 0x90083, 0xa }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */
+	{ 0x90084, 0x10 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */
+	{ 0x90085, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */
+	{ 0x90086, 0x9 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */
+	{ 0x90087, 0x3c0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */
+	{ 0x90088, 0x149 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */
+	{ 0x90089, 0x9 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */
+	{ 0x9008a, 0x3c0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */
+	{ 0x9008b, 0x159 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */
+	{ 0x9008c, 0x18 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */
+	{ 0x9008d, 0x10 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */
+	{ 0x9008e, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */
+	{ 0x9008f, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */
+	{ 0x90090, 0x3c0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */
+	{ 0x90091, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */
+	{ 0x90092, 0x18 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */
+	{ 0x90093, 0x4 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */
+	{ 0x90094, 0x48 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */
+	{ 0x90095, 0x18 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */
+	{ 0x90096, 0x4 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */
+	{ 0x90097, 0x58 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */
+	{ 0x90098, 0xa }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */
+	{ 0x90099, 0x10 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */
+	{ 0x9009a, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */
+	{ 0x9009b, 0x2 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */
+	{ 0x9009c, 0x10 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */
+	{ 0x9009d, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */
+	{ 0x9009e, 0x7 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */
+	{ 0x9009f, 0x7c0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */
+	{ 0x900a0, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */
+	{ 0x900a1, 0x10 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */
+	{ 0x900a2, 0x10 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */
+	{ 0x900a3, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */
+	{ 0x900a4, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */
+	{ 0x900a5, 0x8140 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */
+	{ 0x900a6, 0x10c }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */
+	{ 0x900a7, 0x10 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */
+	{ 0x900a8, 0x8138 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */
+	{ 0x900a9, 0x10c }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */
+	{ 0x900aa, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */
+	{ 0x900ab, 0x7c8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */
+	{ 0x900ac, 0x101 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */
+	{ 0x900ad, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */
+	{ 0x900ae, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */
+	{ 0x900af, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */
+	{ 0x900b0, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */
+	{ 0x900b1, 0x448 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */
+	{ 0x900b2, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */
+	{ 0x900b3, 0xf }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */
+	{ 0x900b4, 0x7c0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */
+	{ 0x900b5, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */
+	{ 0x900b6, 0x47 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */
+	{ 0x900b7, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */
+	{ 0x900b8, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */
+	{ 0x900b9, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */
+	{ 0x900ba, 0x618 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */
+	{ 0x900bb, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */
+	{ 0x900bc, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */
+	{ 0x900bd, 0xe0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */
+	{ 0x900be, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */
+	{ 0x900bf, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */
+	{ 0x900c0, 0x7c8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */
+	{ 0x900c1, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */
+	{ 0x900c2, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */
+	{ 0x900c3, 0x8140 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */
+	{ 0x900c4, 0x10c }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */
+	{ 0x900c5, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */
+	{ 0x900c6, 0x1 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */
+	{ 0x900c7, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */
+	{ 0x900c8, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */
+	{ 0x900c9, 0x4 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */
+	{ 0x900ca, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */
+	{ 0x900cb, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */
+	{ 0x900cc, 0x7c8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */
+	{ 0x900cd, 0x101 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */
+	{ 0x90006, 0x0 }, /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */
+	{ 0x90007, 0x0 }, /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */
+	{ 0x90008, 0x8 }, /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */
+	{ 0x90009, 0x0 }, /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */
+	{ 0x9000a, 0x0 }, /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */
+	{ 0x9000b, 0x0 }, /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */
+	{ 0xd00e7, 0x400 }, /*  DWC_DDRPHYA_APBONLY0_SequencerOverride */
+	{ 0x90017, 0x0 }, /*  DWC_DDRPHYA_INITENG0_StartVector0b0 */
+	{ 0x90026, 0x2c }, /*  DWC_DDRPHYA_INITENG0_StartVector0b15 */
+	{ 0x2000b, 0x32 }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */
+	{ 0x2000c, 0x64 }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */
+	{ 0x2000d, 0x3e8 }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */
+	{ 0x2000e, 0x2c }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */
+	{ 0x12000b, 0x10 }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY0_p1 */
+	{ 0x12000c, 0x21 }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY1_p1 */
+	{ 0x12000d, 0x14c }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY2_p1 */
+	{ 0x12000e, 0x10 }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY3_p1 */
+	{ 0x22000b, 0xa }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY0_p2 */
+	{ 0x22000c, 0x14 }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY1_p2 */
+	{ 0x22000d, 0xcf }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY2_p2 */
+	{ 0x22000e, 0x10 }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY3_p2 */
+	{ 0x9000c, 0x0 }, /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */
+	{ 0x9000d, 0x173 }, /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */
+	{ 0x9000e, 0x60 }, /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */
+	{ 0x9000f, 0x6110 }, /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */
+	{ 0x90010, 0x2152 }, /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */
+	{ 0x90011, 0xdfbd }, /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */
+	{ 0x90012, 0xffff }, /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */
+	{ 0x90013, 0x6152 }, /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */
+	{ 0xc0080, 0x0 }, /*  DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */
+	{ 0xd0000, 0x1 }, /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+};
+
+struct dram_fsp_msg ddr3l_dram_fsp_msg[] = {
+	{
+		/* P0 2400mts 1D */
+		.drate = 1600,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr3l_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr3l_fsp0_cfg),
+	},
+#if 1
+	{
+		/* P1 1066mts 1D */
+		.drate = 1066,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr3l_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr3l_fsp1_cfg),
+	},
+	{
+		/* P2 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr3l_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr3l_fsp2_cfg),
+	},
+#endif
+};
+
+/* ddr3l timing config params on VAL board */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr3l_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr3l_ddrc_cfg),
+	.ddrphy_cfg = ddr3l_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr3l_ddrphy_cfg),
+	.fsp_msg = ddr3l_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr3l_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr3l_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr3l_ddrphy_trained_csr),
+	.ddrphy_pie = ddr3l_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr3l_phy_pie),
+	.fsp_table = { 1600, 1066, 667 },
+};
diff --git a/board/freescale/imx8mm_val/ddr4_timing.c b/board/freescale/imx8mm_val/ddr4_timing.c
new file mode 100644
index 00000000000..c4c800f7dda
--- /dev/null
+++ b/board/freescale/imx8mm_val/ddr4_timing.c
@@ -0,0 +1,1496 @@
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr4_ddrc_cfg[] = {
+	{ DDRC_MSTR(0), 0x83040010 },
+	{ DDRC_PWRCTL(0), 0x000000aa },
+	{ DDRC_PWRTMG(0), 0x00221306 },
+	{ DDRC_RFSHCTL0(0), 0x00c0a070 },
+	{ DDRC_RFSHCTL1(0), 0x00010008 },
+	{ DDRC_RFSHCTL3(0), 0x00000010 },
+	{ DDRC_RFSHTMG(0), 0x004980f4 },
+	{ DDRC_CRCPARCTL0(0), 0x00000000 },
+	{ DDRC_CRCPARCTL1(0), 0x00001010 },
+	{ DDRC_INIT0(0), 0xc0030002 },
+	{ DDRC_INIT1(0), 0x00020009 },
+	{ DDRC_INIT2(0), 0x0000350f },
+//	{ DDRC_INIT3(0), (mr_value[0][0]<<16) | (mr_value[0][1]) },
+	{ DDRC_INIT3(0), (0xa34 << 16) | 0x105 },
+//	{ DDRC_INIT4(0), (mr_value[0][2]<<16) | (mr_value[0][3]) },
+	{ DDRC_INIT4(0), (0x1028 << 16) | 0x240 },
+	{ DDRC_INIT5(0), 0x001103cb },
+//	{ DDRC_INIT6(0), (mr_value[0][4]<<16) | (mr_value[0][5]) },
+	{ DDRC_INIT6(0), (0x200 << 16) | 0x200 },
+//	{ DDRC_INIT7(0), mr_value[0][6] },
+	{ DDRC_INIT7(0), 0x814 },
+	{ DDRC_DIMMCTL(0), 0x00000032 },
+	{ DDRC_RANKCTL(0), 0x00000fc7 },
+	{ DDRC_DRAMTMG0(0), 0x14132813 },
+	{ DDRC_DRAMTMG1(0), 0x0004051b },
+	{ DDRC_DRAMTMG2(0), 0x0808030f },
+	{ DDRC_DRAMTMG3(0), 0x0000400c },
+	{ DDRC_DRAMTMG4(0), 0x08030409 },
+	{ DDRC_DRAMTMG5(0), 0x0e090504 },
+	{ DDRC_DRAMTMG6(0), 0x05030000 },
+	{ DDRC_DRAMTMG7(0), 0x0000090e },
+	{ DDRC_DRAMTMG8(0), 0x0606700c },
+	{ DDRC_DRAMTMG9(0), 0x0002040c },
+	{ DDRC_DRAMTMG10(0), 0x000f0c07 },
+	{ DDRC_DRAMTMG11(0), 0x1809011d },
+	{ DDRC_DRAMTMG12(0), 0x0000000d },
+	{ DDRC_DRAMTMG13(0), 0x2b000000 },
+	{ DDRC_DRAMTMG14(0), 0x000000a4 },
+	{ DDRC_DRAMTMG15(0), 0x00000000 },
+	{ DDRC_DRAMTMG17(0), 0x00250078 },
+	{ DDRC_ZQCTL0(0), 0x51000040 },
+	{ DDRC_ZQCTL1(0), 0x00000070 },
+	{ DDRC_ZQCTL2(0), 0x00000000 },
+	{ DDRC_DFITMG0(0), 0x038b820b },
+	{ DDRC_DFITMG1(0), 0x02020103 },
+	{ DDRC_DFILPCFG0(0), 0x07f04011 }, /*  [8]dfi_lp_en_sr = 0 */
+	{ DDRC_DFILPCFG1(0), 0x000000b0 },
+	{ DDRC_DFIUPD0(0), 0xe0400018 },
+	{ DDRC_DFIUPD1(0), 0x0048005a },
+	{ DDRC_DFIUPD2(0), 0x80000000 },
+	{ DDRC_DFIMISC(0), 0x00000001 },
+	{ DDRC_DFITMG2(0), 0x00000b0b },
+	{ DDRC_DFITMG3(0), 0x00000001 },
+	{ DDRC_DBICTL(0), 0x00000000 },
+	{ DDRC_DFIPHYMSTR(0), 0x00000000 },
+
+	{ DDRC_ADDRMAP0(0), 0x00000017 }, /* [4:0]cs0: 6+23 */
+	{ DDRC_ADDRMAP1(0), 0x003F0909 }, /* [5:0] bank b0: 2+9; [13:8] b1: P3+9 ; [21:16] b2: 4+, unused */
+	{ DDRC_ADDRMAP2(0), 0x01010100 }, /* [3:0] col-b2: 2;  [11:8] col-b3: 3+1; [19:16] col-b4: 4+1 ; [27:24] col-b5: 5+1 */
+	{ DDRC_ADDRMAP3(0), 0x01010101 }, /* [3:0] col-b6: 6+1;  [11:8] col-b7: 7+1; [19:16] col-b8: 8+1 ; [27:24] col-b9: 9+1 */
+	{ DDRC_ADDRMAP4(0), 0x00001f1f }, /* col-b10, col-b11 not used */
+	{ DDRC_ADDRMAP5(0), 0x07070707 }, /* [3:0] row-b0: 6+7;  [11:8] row-b1: 7+7; [19:16] row-b2_b10: 8~16+7; [27:24] row-b11: 17+7 */
+	{ DDRC_ADDRMAP6(0), 0x07070707 }, /* [3:0] row-b12:18+7; [11:8] row-b13: 19+7; [19:16] row-b14:20+7; [27:24] row-b15: 21+7 */
+	{ DDRC_ADDRMAP7(0), 0x00000f0f }, /* col-b10, col-b11 not used */
+	{ DDRC_ADDRMAP8(0), 0x00003F01 }, /* [5:0] bg-b0: 2+1; [13:8]bg-b1:3+, unused */
+	{ DDRC_ADDRMAP9(0), 0x0a020b06 }, /*  it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
+	{ DDRC_ADDRMAP10(0), 0x0a0a0a0a },/*  it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
+	{ DDRC_ADDRMAP11(0), 0x00000000 },
+
+	/* FREQ0: BL8, CL=16, CWL=16, WR_PREAMBLE = 1,RD_PREAMBLE = 1, CRC_MODE = 1, so wr_odt_hold=5+1+1=7 */
+	/* wr_odt_delay=DFITMG1.dfi_t_cmd_lat=0 */
+	{ DDRC_ODTCFG(0), 0x07000600 },
+	{ DDRC_ODTMAP(0), 0x0201 },/* disable ODT0x00001120 , */
+	{ DDRC_SCHED(0), 0x317d1a07 },
+	{ DDRC_SCHED1(0), 0x0000000f },
+	{ DDRC_PERFHPR1(0), 0x2a001b76 },
+	{ DDRC_PERFLPR1(0), 0x7300b473 },
+	{ DDRC_PERFWR1(0), 0x30000e06 },
+	{ DDRC_DBG0(0), 0x00000014 },
+	{ DDRC_DBG1(0), 0x00000000 },
+	{ DDRC_DBGCMD(0), 0x00000000 },
+	{ DDRC_SWCTL(0), 0x00000001 },
+	{ DDRC_POISONCFG(0), 0x00000010 },
+	{ DDRC_PCCFG(0), 0x00000100 },/* bl_exp_mode=1 */
+	{ DDRC_PCFGR_0(0), 0x00013193 },
+	{ DDRC_PCFGW_0(0), 0x00006096 },
+	{ DDRC_PCTRL_0(0), 0x00000001 },
+	{ DDRC_PCFGQOS0_0(0), 0x02000c00 },
+	{ DDRC_PCFGQOS1_0(0), 0x003c00db },
+	{ DDRC_PCFGWQOS0_0(0), 0x00100009 },
+	{ DDRC_PCFGWQOS1_0(0), 0x00000002 },
+
+	{ DDRC_FREQ1_RFSHCTL0(0), 0x0021a0c0 },
+	{ DDRC_FREQ1_RFSHTMG(0), 0x0018001a },/* tREFI=7.8us */
+//	{ DDRC_FREQ1_INIT3(0), (mr_value[1][0]<<16) | (mr_value[1][1]) },
+//	{ DDRC_FREQ1_INIT4(0), (mr_value[1][2]<<16) | (mr_value[1][3]) },
+//	{ DDRC_FREQ1_INIT6(0), (mr_value[1][4]<<16) | (mr_value[1][5]) },
+//	{ DDRC_FREQ1_INIT7(0),  mr_value[1][6] },
+	{ DDRC_FREQ1_INIT3(0), (0x204 << 16) | 0x104 },
+	{ DDRC_FREQ1_INIT4(0), (0x1000 << 16) | 0x040 },
+	{ DDRC_FREQ1_INIT6(0), (0x200 << 16) | 0x200 },
+	{ DDRC_FREQ1_INIT7(0),  0x014 },
+	{ DDRC_FREQ1_DRAMTMG0(0), 0x0c0e0604 },/* t_ras_max=9*7.8us, t_ras_min=35ns */
+	{ DDRC_FREQ1_DRAMTMG1(0), 0x00030314 },
+	{ DDRC_FREQ1_DRAMTMG2(0), 0x0505040a },
+	{ DDRC_FREQ1_DRAMTMG3(0), 0x0000400c },
+	{ DDRC_FREQ1_DRAMTMG4(0), 0x06040307 }, /*  tRP=6 --> 7 */
+	{ DDRC_FREQ1_DRAMTMG5(0), 0x090d0202 },
+	{ DDRC_FREQ1_DRAMTMG6(0), 0x0a070008 },
+	{ DDRC_FREQ1_DRAMTMG7(0), 0x00000d09 },
+	{ DDRC_FREQ1_DRAMTMG8(0), 0x08084b09 },
+	{ DDRC_FREQ1_DRAMTMG9(0), 0x00020308 },
+	{ DDRC_FREQ1_DRAMTMG10(0), 0x000f0d06 },
+	{ DDRC_FREQ1_DRAMTMG11(0), 0x12060111 },
+	{ DDRC_FREQ1_DRAMTMG12(0), 0x00000008 },
+	{ DDRC_FREQ1_DRAMTMG13(0), 0x21000000 },
+	{ DDRC_FREQ1_DRAMTMG14(0), 0x00000000 },
+	{ DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
+	{ DDRC_FREQ1_DRAMTMG17(0), 0x00c6007d },
+	{ DDRC_FREQ1_ZQCTL0(0), 0x51000040 },
+	{ DDRC_FREQ1_DFITMG0(0), 0x03858204 },
+	{ DDRC_FREQ1_DFITMG1(0), 0x00020103 },
+	{ DDRC_FREQ1_DFITMG2(0), 0x00000504 },
+	{ DDRC_FREQ1_DFITMG3(0), 0x00000001 },
+	/* FREQ1: BL8, CL=10, CWL=9, WR_PREAMBLE = 1,RD_PREAMBLE = 1, CRC_MODE = 1 */
+	/* wr_odt_delay=DFITMG1.dfi_t_cmd_lat=0 */
+	{ DDRC_FREQ1_ODTCFG(0), 0x07000601 },
+
+	{ DDRC_FREQ2_RFSHCTL0(0), 0x0021a0c0 },
+	{ DDRC_FREQ2_RFSHTMG(0), 0x0006000e },/* tREFI=7.8us */
+//	{ DDRC_FREQ2_INIT3(0), (mr_value[2][0]<<16) | (mr_value[2][1]) },
+//	{ DDRC_FREQ2_INIT4(0), (mr_value[2][2]<<16) | (mr_value[2][3]) },
+//	{ DDRC_FREQ2_INIT6(0), (mr_value[2][4]<<16) | (mr_value[2][5]) },
+//	{ DDRC_FREQ2_INIT7(0),  mr_value[2][6] },
+	{ DDRC_FREQ2_INIT3(0), (0x204 << 16) | 0x104 },
+	{ DDRC_FREQ2_INIT4(0), (0x1000 << 16) | 0x40 },
+	{ DDRC_FREQ2_INIT6(0), (0x200 << 16) | 0x200 },
+	{ DDRC_FREQ2_INIT7(0),  0x14 },
+	{ DDRC_FREQ2_DRAMTMG0(0), 0x0c0e0101 },/* t_ras_max=9*7.8us, t_ras_min=35ns */
+	{ DDRC_FREQ2_DRAMTMG1(0), 0x00030314 },
+	{ DDRC_FREQ2_DRAMTMG2(0), 0x0505040a },
+	{ DDRC_FREQ2_DRAMTMG3(0), 0x0000400c },
+	{ DDRC_FREQ2_DRAMTMG4(0), 0x06040307 }, /*  tRP=6 --> 7 */
+	{ DDRC_FREQ2_DRAMTMG5(0), 0x090d0202 },
+	{ DDRC_FREQ2_DRAMTMG6(0), 0x0a070008 },
+	{ DDRC_FREQ2_DRAMTMG7(0), 0x00000d09 },
+	{ DDRC_FREQ2_DRAMTMG8(0), 0x08084b09 },
+	{ DDRC_FREQ2_DRAMTMG9(0), 0x00020308 },
+	{ DDRC_FREQ2_DRAMTMG10(0), 0x000f0d06 },
+	{ DDRC_FREQ2_DRAMTMG11(0), 0x12060111 },
+	{ DDRC_FREQ2_DRAMTMG12(0), 0x00000008 },
+	{ DDRC_FREQ2_DRAMTMG13(0), 0x21000000 },
+	{ DDRC_FREQ2_DRAMTMG14(0), 0x00000000 },
+	{ DDRC_FREQ2_DRAMTMG15(0), 0x00000000 },
+	{ DDRC_FREQ2_DRAMTMG17(0), 0x00c6007d },
+	{ DDRC_FREQ2_ZQCTL0(0), 0x51000040 },
+	{ DDRC_FREQ2_DFITMG0(0), 0x03858204 },
+	{ DDRC_FREQ2_DFITMG1(0), 0x00020103 },
+	{ DDRC_FREQ2_DFITMG2(0), 0x00000504 },
+	{ DDRC_FREQ2_DFITMG3(0), 0x00000001 },
+	/* FREQ1: BL8, CL=10, CWL=9, WR_PREAMBLE = 1,RD_PREAMBLE = 1, CRC_MODE = 1 */
+	/* wr_odt_delay=DFITMG1.dfi_t_cmd_lat=0 */
+	{ DDRC_FREQ2_ODTCFG(0), 0x07000601 },
+
+	/* default start freq point */
+	{ DDRC_MSTR2(0), 0x0},
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr4_ddrphy_cfg[] = {
+	{ 0x1005f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 */
+	{ 0x1015f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 */
+	{ 0x1105f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 */
+	{ 0x1115f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 */
+	{ 0x1205f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 */
+	{ 0x1215f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 */
+	{ 0x1305f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 */
+	{ 0x1315f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 */
+
+	{ 0x11005f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p1 */
+	{ 0x11015f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p1 */
+	{ 0x11105f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p1 */
+	{ 0x11115f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p1 */
+	{ 0x11205f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p1 */
+	{ 0x11215f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p1 */
+	{ 0x11305f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p1 */
+	{ 0x11315f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p1 */
+
+	{ 0x21005f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p2 */
+	{ 0x21015f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p2 */
+	{ 0x21105f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p2 */
+	{ 0x21115f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p2 */
+	{ 0x21205f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p2 */
+	{ 0x21215f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p2 */
+	{ 0x21305f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p2 */
+	{ 0x21315f, 0x2fd }, /*  DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p2 */
+
+	{ 0x55, 0x355 }, /*  DWC_DDRPHYA_ANIB0_ATxSlewRate */
+	{ 0x1055, 0x355 }, /*  DWC_DDRPHYA_ANIB1_ATxSlewRate */
+	{ 0x2055, 0x355 }, /*  DWC_DDRPHYA_ANIB2_ATxSlewRate */
+	{ 0x3055, 0x355 }, /*  DWC_DDRPHYA_ANIB3_ATxSlewRate */
+	{ 0x4055, 0x55 }, /*  DWC_DDRPHYA_ANIB4_ATxSlewRate */
+	{ 0x5055, 0x55 }, /*  DWC_DDRPHYA_ANIB5_ATxSlewRate */
+	{ 0x6055, 0x355 }, /*  DWC_DDRPHYA_ANIB6_ATxSlewRate */
+	{ 0x7055, 0x355 }, /*  DWC_DDRPHYA_ANIB7_ATxSlewRate */
+	{ 0x8055, 0x355 }, /*  DWC_DDRPHYA_ANIB8_ATxSlewRate */
+	{ 0x9055, 0x355 }, /*  DWC_DDRPHYA_ANIB9_ATxSlewRate */
+	{ 0x200c5, 0xa }, /*  DWC_DDRPHYA_MASTER0_PllCtrl2_p0 */
+	{ 0x1200c5, 0x7 }, /*  DWC_DDRPHYA_MASTER0_PllCtrl2_p1 */
+	{ 0x2200c5, 0x7 }, /*  DWC_DDRPHYA_MASTER0_PllCtrl2_p2 */
+	{ 0x2002e, 0x2 }, /*  DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 */
+	{ 0x12002e, 0x2 }, /*  DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p1 */
+	{ 0x22002e, 0x2 }, /*  DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p2 */
+	{ 0x20024, 0x8 }, /*  DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 */
+	{ 0x2003a, 0x2 }, /*  DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
+	{ 0x120024, 0x8 }, /*  DWC_DDRPHYA_MASTER0_DqsPreambleControl_p1 */
+	{ 0x2003a, 0x2 }, /*  DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
+	{ 0x220024, 0x8 }, /*  DWC_DDRPHYA_MASTER0_DqsPreambleControl_p2 */
+	{ 0x2003a, 0x2 }, /*  DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
+	{ 0x20056, 0x6 }, /*  DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 */
+	{ 0x120056, 0xa }, /*  DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p1 */
+	{ 0x220056, 0xa }, /*  DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p2 */
+	{ 0x1004d, 0x1a }, /*  DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 */
+	{ 0x1014d, 0x1a }, /*  DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 */
+	{ 0x1104d, 0x1a }, /*  DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 */
+	{ 0x1114d, 0x1a }, /*  DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 */
+	{ 0x1204d, 0x1a }, /*  DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 */
+	{ 0x1214d, 0x1a }, /*  DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 */
+	{ 0x1304d, 0x1a }, /*  DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 */
+	{ 0x1314d, 0x1a }, /*  DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 */
+	{ 0x11004d, 0x1a }, /*  DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p1 */
+	{ 0x11014d, 0x1a }, /*  DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p1 */
+	{ 0x11104d, 0x1a }, /*  DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p1 */
+	{ 0x11114d, 0x1a }, /*  DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p1 */
+	{ 0x11204d, 0x1a }, /*  DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p1 */
+	{ 0x11214d, 0x1a }, /*  DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p1 */
+	{ 0x11304d, 0x1a }, /*  DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p1 */
+	{ 0x11314d, 0x1a }, /*  DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p1 */
+	{ 0x21004d, 0x1a }, /*  DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p2 */
+	{ 0x21014d, 0x1a }, /*  DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p2 */
+	{ 0x21104d, 0x1a }, /*  DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p2 */
+	{ 0x21114d, 0x1a }, /*  DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p2 */
+	{ 0x21204d, 0x1a }, /*  DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p2 */
+	{ 0x21214d, 0x1a }, /*  DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p2 */
+	{ 0x21304d, 0x1a }, /*  DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p2 */
+	{ 0x21314d, 0x1a }, /*  DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p2 */
+	{ 0x10049, 0xe38 }, /*  DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 */
+	{ 0x10149, 0xe38 }, /*  DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 */
+	{ 0x11049, 0xe38 }, /*  DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 */
+	{ 0x11149, 0xe38 }, /*  DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 */
+	{ 0x12049, 0xe38 }, /*  DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 */
+	{ 0x12149, 0xe38 }, /*  DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 */
+	{ 0x13049, 0xe38 }, /*  DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 */
+	{ 0x13149, 0xe38 }, /*  DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 */
+	{ 0x110049, 0xe38 }, /*  DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p1 */
+	{ 0x110149, 0xe38 }, /*  DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p1 */
+	{ 0x111049, 0xe38 }, /*  DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p1 */
+	{ 0x111149, 0xe38 }, /*  DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p1 */
+	{ 0x112049, 0xe38 }, /*  DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p1 */
+	{ 0x112149, 0xe38 }, /*  DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p1 */
+	{ 0x113049, 0xe38 }, /*  DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p1 */
+	{ 0x113149, 0xe38 }, /*  DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p1 */
+	{ 0x210049, 0xe38 }, /*  DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p2 */
+	{ 0x210149, 0xe38 }, /*  DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p2 */
+	{ 0x211049, 0xe38 }, /*  DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p2 */
+	{ 0x211149, 0xe38 }, /*  DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p2 */
+	{ 0x212049, 0xe38 }, /*  DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p2 */
+	{ 0x212149, 0xe38 }, /*  DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p2 */
+	{ 0x213049, 0xe38 }, /*  DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p2 */
+	{ 0x213149, 0xe38 }, /*  DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p2 */
+	{ 0x43, 0x63 }, /*  DWC_DDRPHYA_ANIB0_ATxImpedance */
+	{ 0x1043, 0x63 }, /*  DWC_DDRPHYA_ANIB1_ATxImpedance */
+	{ 0x2043, 0x63 }, /*  DWC_DDRPHYA_ANIB2_ATxImpedance */
+	{ 0x3043, 0x63 }, /*  DWC_DDRPHYA_ANIB3_ATxImpedance */
+	{ 0x4043, 0x63 }, /*  DWC_DDRPHYA_ANIB4_ATxImpedance */
+	{ 0x5043, 0x63 }, /*  DWC_DDRPHYA_ANIB5_ATxImpedance */
+	{ 0x6043, 0x63 }, /*  DWC_DDRPHYA_ANIB6_ATxImpedance */
+	{ 0x7043, 0x63 }, /*  DWC_DDRPHYA_ANIB7_ATxImpedance */
+	{ 0x8043, 0x63 }, /*  DWC_DDRPHYA_ANIB8_ATxImpedance */
+	{ 0x9043, 0x63 }, /*  DWC_DDRPHYA_ANIB9_ATxImpedance */
+	{ 0x20018, 0x5 }, /*  DWC_DDRPHYA_MASTER0_DfiMode */
+	{ 0x20075, 0x2 }, /*  DWC_DDRPHYA_MASTER0_DfiCAMode */
+	{ 0x20050, 0x0 }, /*  DWC_DDRPHYA_MASTER0_CalDrvStr0 */
+	{ 0x20008, 0x258 }, /*  DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 */
+	{ 0x120008, 0x64 }, /*  DWC_DDRPHYA_MASTER0_CalUclkInfo_p1 */
+	{ 0x220008, 0x19 }, /*  DWC_DDRPHYA_MASTER0_CalUclkInfo_p2 */
+	{ 0x20088, 0x9 }, /*  DWC_DDRPHYA_MASTER0_CalRate */
+	{ 0x200b2, 0x268 }, /*  DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 */
+	{ 0x10043, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 */
+	{ 0x10143, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 */
+	{ 0x11043, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 */
+	{ 0x11143, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 */
+	{ 0x12043, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 */
+	{ 0x12143, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 */
+	{ 0x13043, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 */
+	{ 0x13143, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 */
+	{ 0x1200b2, 0x268 }, /*  DWC_DDRPHYA_MASTER0_VrefInGlobal_p1 */
+	{ 0x110043, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p1 */
+	{ 0x110143, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p1 */
+	{ 0x111043, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p1 */
+	{ 0x111143, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p1 */
+	{ 0x112043, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p1 */
+	{ 0x112143, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p1 */
+	{ 0x113043, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p1 */
+	{ 0x113143, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p1 */
+	{ 0x2200b2, 0x268 }, /*  DWC_DDRPHYA_MASTER0_VrefInGlobal_p2 */
+	{ 0x210043, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p2 */
+	{ 0x210143, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p2 */
+	{ 0x211043, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p2 */
+	{ 0x211143, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p2 */
+	{ 0x212043, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p2 */
+	{ 0x212143, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p2 */
+	{ 0x213043, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p2 */
+	{ 0x213143, 0x5b1 }, /*  DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p2 */
+	{ 0x2005b, 0x7529 }, /*  DWC_DDRPHYA_MASTER0_MemAlertControl */
+	{ 0x2005c, 0x0 }, /*  DWC_DDRPHYA_MASTER0_MemAlertControl2 */
+	{ 0x200fa, 0x1 }, /*  DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 */
+	{ 0x1200fa, 0x1 }, /*  DWC_DDRPHYA_MASTER0_DfiFreqRatio_p1 */
+	{ 0x2200fa, 0x1 }, /*  DWC_DDRPHYA_MASTER0_DfiFreqRatio_p2 */
+	{ 0x20019, 0x5 }, /*  DWC_DDRPHYA_MASTER0_TristateModeCA_p0 */
+	{ 0x120019, 0x5 }, /*  DWC_DDRPHYA_MASTER0_TristateModeCA_p1 */
+	{ 0x220019, 0x5 }, /*  DWC_DDRPHYA_MASTER0_TristateModeCA_p2 */
+	{ 0x200f0, 0x5665 }, /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */
+	{ 0x200f1, 0x5555 }, /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat1 */
+	{ 0x200f2, 0x5555 }, /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat2 */
+	{ 0x200f3, 0x5555 }, /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat3 */
+	{ 0x200f4, 0x5555 }, /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat4 */
+	{ 0x200f5, 0x5555 }, /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat5 */
+	{ 0x200f6, 0x5555 }, /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat6 */
+	{ 0x200f7, 0xf000 }, /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat7 */
+	{ 0x20025, 0x0 }, /*  DWC_DDRPHYA_MASTER0_MasterX4Config */
+	{ 0x2002d, 0x0 }, /*  DWC_DDRPHYA_MASTER0_DMIPinPresent_p0 */
+	{ 0x12002d, 0x0 }, /*  DWC_DDRPHYA_MASTER0_DMIPinPresent_p1 */
+	{ 0x22002d, 0x0 }, /*  DWC_DDRPHYA_MASTER0_DMIPinPresent_p2 */
+	{ 0x200c7, 0x21 }, /*  DWC_DDRPHYA_MASTER0_PllCtrl1_p0 */
+	{ 0x200ca, 0x24 }, /*  DWC_DDRPHYA_MASTER0_PllTestMode_p0 */
+};
+
+/* ddr phy trained CSR */
+struct dram_cfg_param ddr4_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
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+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr4_fsp0_cfg[] = {
+	{ 0x20060, 0x2 },
+	{ 0xd0000, 0x0 }, /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0x960 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x0 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x303 },
+	{ 0x54009, 0x200 },/* no addr mirror, 0x200 addr mirror */
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x31f },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0xa34 },
+	{ 0x54030, 0x105 },
+	{ 0x54031, 0x1028 },
+	{ 0x54032, 0x240 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x200 },
+	{ 0x54035, 0x814 },
+	{ 0x54036, 0x103 },
+	{ 0x54037, 0x0 },
+	{ 0x54038, 0x0 },
+	{ 0x54039, 0x0 },
+	{ 0x5403a, 0x0 },
+	{ 0x5403b, 0x0 },
+	{ 0x5403c, 0x0 },
+	{ 0x5403d, 0x0 },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 }, /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr4_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 }, /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x0 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x303 },
+	{ 0x54009, 0x200 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x21f },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x204 },
+	{ 0x54030, 0x104 },
+	{ 0x54031, 0x1000 },
+	{ 0x54032, 0x40 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x200 },
+	{ 0x54035, 0x14 },
+	{ 0x54036, 0x103 },
+	{ 0x54037, 0x0 },
+	{ 0x54038, 0x0 },
+	{ 0x54039, 0x0 },
+	{ 0x5403a, 0x0 },
+	{ 0x5403b, 0x0 },
+	{ 0x5403c, 0x0 },
+	{ 0x5403d, 0x0 },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 }, /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr4_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 }, /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x0 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x303 },
+	{ 0x54009, 0x200 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x21f },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x204 },
+	{ 0x54030, 0x104 },
+	{ 0x54031, 0x1000 },
+	{ 0x54032, 0x40 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x200 },
+	{ 0x54035, 0x14 },
+	{ 0x54036, 0x103 },
+	{ 0x54037, 0x0 },
+	{ 0x54038, 0x0 },
+	{ 0x54039, 0x0 },
+	{ 0x5403a, 0x0 },
+	{ 0x5403b, 0x0 },
+	{ 0x5403c, 0x0 },
+	{ 0x5403d, 0x0 },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 }, /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+};
+
+struct dram_cfg_param ddr4_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 }, /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0x960 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x0 },
+	{ 0x54006, 0x25e },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x303 },
+	{ 0x54009, 0x200 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x61 },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400e, 0x1f7f },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0xa34 },
+	{ 0x54030, 0x105 },
+	{ 0x54031, 0x1028 },
+	{ 0x54032, 0x240 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x200 },
+	{ 0x54035, 0x814 },
+	{ 0x54036, 0x103 },
+	{ 0x54037, 0x0 },
+	{ 0x54038, 0x0 },
+	{ 0x54039, 0x0 },
+	{ 0x5403a, 0x0 },
+	{ 0x5403b, 0x0 },
+	{ 0x5403c, 0x0 },
+	{ 0x5403d, 0x0 },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 }, /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+};
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr4_phy_pie[] = {
+	{ 0xd0000, 0x0 }, /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	{ 0x90000, 0x10 }, /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */
+	{ 0x90001, 0x400 }, /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */
+	{ 0x90002, 0x10e }, /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */
+	{ 0x90003, 0x0 }, /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */
+	{ 0x90004, 0x0 }, /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */
+	{ 0x90005, 0x8 }, /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */
+	{ 0x90029, 0xb }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */
+	{ 0x9002a, 0x480 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */
+	{ 0x9002b, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */
+	{ 0x9002c, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */
+	{ 0x9002d, 0x448 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */
+	{ 0x9002e, 0x139 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */
+	{ 0x9002f, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */
+	{ 0x90030, 0x478 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */
+	{ 0x90031, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */
+	{ 0x90032, 0x2 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */
+	{ 0x90033, 0x10 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */
+	{ 0x90034, 0x139 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */
+	{ 0x90035, 0xf }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */
+	{ 0x90036, 0x7c0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */
+	{ 0x90037, 0x139 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */
+	{ 0x90038, 0x44 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */
+	{ 0x90039, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */
+	{ 0x9003a, 0x159 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */
+	{ 0x9003b, 0x14f }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */
+	{ 0x9003c, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */
+	{ 0x9003d, 0x159 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */
+	{ 0x9003e, 0x47 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */
+	{ 0x9003f, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */
+	{ 0x90040, 0x149 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */
+	{ 0x90041, 0x4f }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */
+	{ 0x90042, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */
+	{ 0x90043, 0x179 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */
+	{ 0x90044, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */
+	{ 0x90045, 0xe0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */
+	{ 0x90046, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */
+	{ 0x90047, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */
+	{ 0x90048, 0x7c8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */
+	{ 0x90049, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */
+	{ 0x9004a, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */
+	{ 0x9004b, 0x1 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */
+	{ 0x9004c, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */
+	{ 0x9004d, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */
+	{ 0x9004e, 0x45a }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */
+	{ 0x9004f, 0x9 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */
+	{ 0x90050, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */
+	{ 0x90051, 0x448 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */
+	{ 0x90052, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */
+	{ 0x90053, 0x40 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */
+	{ 0x90054, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */
+	{ 0x90055, 0x179 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */
+	{ 0x90056, 0x1 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */
+	{ 0x90057, 0x618 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */
+	{ 0x90058, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */
+	{ 0x90059, 0x40c0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */
+	{ 0x9005a, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */
+	{ 0x9005b, 0x149 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */
+	{ 0x9005c, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */
+	{ 0x9005d, 0x4 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */
+	{ 0x9005e, 0x48 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */
+	{ 0x9005f, 0x4040 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */
+	{ 0x90060, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */
+	{ 0x90061, 0x149 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */
+	{ 0x90062, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */
+	{ 0x90063, 0x4 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */
+	{ 0x90064, 0x48 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */
+	{ 0x90065, 0x40 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */
+	{ 0x90066, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */
+	{ 0x90067, 0x149 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */
+	{ 0x90068, 0x10 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */
+	{ 0x90069, 0x4 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */
+	{ 0x9006a, 0x18 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */
+	{ 0x9006b, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */
+	{ 0x9006c, 0x4 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */
+	{ 0x9006d, 0x78 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */
+	{ 0x9006e, 0x549 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */
+	{ 0x9006f, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */
+	{ 0x90070, 0x159 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */
+	{ 0x90071, 0xd49 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */
+	{ 0x90072, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */
+	{ 0x90073, 0x159 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */
+	{ 0x90074, 0x94a }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */
+	{ 0x90075, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */
+	{ 0x90076, 0x159 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */
+	{ 0x90077, 0x441 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */
+	{ 0x90078, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */
+	{ 0x90079, 0x149 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */
+	{ 0x9007a, 0x42 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */
+	{ 0x9007b, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */
+	{ 0x9007c, 0x149 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */
+	{ 0x9007d, 0x1 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */
+	{ 0x9007e, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */
+	{ 0x9007f, 0x149 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */
+	{ 0x90080, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */
+	{ 0x90081, 0xe0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */
+	{ 0x90082, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */
+	{ 0x90083, 0xa }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */
+	{ 0x90084, 0x10 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */
+	{ 0x90085, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */
+	{ 0x90086, 0x9 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */
+	{ 0x90087, 0x3c0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */
+	{ 0x90088, 0x149 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */
+	{ 0x90089, 0x9 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */
+	{ 0x9008a, 0x3c0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */
+	{ 0x9008b, 0x159 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */
+	{ 0x9008c, 0x18 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */
+	{ 0x9008d, 0x10 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */
+	{ 0x9008e, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */
+	{ 0x9008f, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */
+	{ 0x90090, 0x3c0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */
+	{ 0x90091, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */
+	{ 0x90092, 0x18 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */
+	{ 0x90093, 0x4 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */
+	{ 0x90094, 0x48 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */
+	{ 0x90095, 0x18 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */
+	{ 0x90096, 0x4 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */
+	{ 0x90097, 0x58 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */
+	{ 0x90098, 0xa }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */
+	{ 0x90099, 0x10 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */
+	{ 0x9009a, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */
+	{ 0x9009b, 0x2 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */
+	{ 0x9009c, 0x10 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */
+	{ 0x9009d, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */
+	{ 0x9009e, 0x7 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */
+	{ 0x9009f, 0x7c0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */
+	{ 0x900a0, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */
+	{ 0x900a1, 0x10 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */
+	{ 0x900a2, 0x10 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */
+	{ 0x900a3, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */
+	{ 0x900a4, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */
+	{ 0x900a5, 0x8140 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */
+	{ 0x900a6, 0x10c }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */
+	{ 0x900a7, 0x10 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */
+	{ 0x900a8, 0x8138 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */
+	{ 0x900a9, 0x10c }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */
+	{ 0x900aa, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */
+	{ 0x900ab, 0x7c8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */
+	{ 0x900ac, 0x101 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */
+	{ 0x900ad, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */
+	{ 0x900ae, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */
+	{ 0x900af, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */
+	{ 0x900b0, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */
+	{ 0x900b1, 0x448 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */
+	{ 0x900b2, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */
+	{ 0x900b3, 0xf }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */
+	{ 0x900b4, 0x7c0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */
+	{ 0x900b5, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */
+	{ 0x900b6, 0x47 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */
+	{ 0x900b7, 0x630 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */
+	{ 0x900b8, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */
+	{ 0x900b9, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */
+	{ 0x900ba, 0x618 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */
+	{ 0x900bb, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */
+	{ 0x900bc, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */
+	{ 0x900bd, 0xe0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */
+	{ 0x900be, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */
+	{ 0x900bf, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */
+	{ 0x900c0, 0x7c8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */
+	{ 0x900c1, 0x109 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */
+	{ 0x900c2, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */
+	{ 0x900c3, 0x8140 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */
+	{ 0x900c4, 0x10c }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */
+	{ 0x900c5, 0x0 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */
+	{ 0x900c6, 0x1 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */
+	{ 0x900c7, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */
+	{ 0x900c8, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */
+	{ 0x900c9, 0x4 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */
+	{ 0x900ca, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */
+	{ 0x900cb, 0x8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */
+	{ 0x900cc, 0x7c8 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */
+	{ 0x900cd, 0x101 }, /*  DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */
+	{ 0x90006, 0x0 }, /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */
+	{ 0x90007, 0x0 }, /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */
+	{ 0x90008, 0x8 }, /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */
+	{ 0x90009, 0x0 }, /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */
+	{ 0x9000a, 0x0 }, /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */
+	{ 0x9000b, 0x0 }, /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */
+	{ 0xd00e7, 0x400 }, /*  DWC_DDRPHYA_APBONLY0_SequencerOverride */
+	{ 0x90017, 0x0 }, /*  DWC_DDRPHYA_INITENG0_StartVector0b0 */
+	{ 0x90026, 0x2c }, /*  DWC_DDRPHYA_INITENG0_StartVector0b15 */
+	{ 0x2000b, 0x4b }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */
+	{ 0x2000c, 0x96 }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */
+	{ 0x2000d, 0x5dc }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */
+	{ 0x2000e, 0x2c }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */
+	{ 0x12000b, 0xc }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY0_p1 */
+	{ 0x12000c, 0x19 }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY1_p1 */
+	{ 0x12000d, 0xfa }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY2_p1 */
+	{ 0x12000e, 0x10 }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY3_p1 */
+	{ 0x22000b, 0x3 }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY0_p2 */
+	{ 0x22000c, 0x6 }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY1_p2 */
+	{ 0x22000d, 0x3e }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY2_p2 */
+	{ 0x22000e, 0x10 }, /*  DWC_DDRPHYA_MASTER0_Seq0BDLY3_p2 */
+	{ 0x9000c, 0x0 }, /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */
+	{ 0x9000d, 0x173 }, /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */
+	{ 0x9000e, 0x60 }, /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */
+	{ 0x9000f, 0x6110 }, /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */
+	{ 0x90010, 0x2152 }, /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */
+	{ 0x90011, 0xdfbd }, /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */
+	{ 0x90012, 0xffff }, /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */
+	{ 0x90013, 0x6152 }, /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */
+	{ 0xc0080, 0x0 }, /*  DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */
+	{ 0xd0000, 0x1 }, /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+};
+
+struct dram_fsp_msg ddr4_dram_fsp_msg[] = {
+	{
+		/* P0 2400mts 1D */
+		.drate = 2400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr4_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr4_fsp0_cfg),
+	},
+#if 1
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr4_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr4_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr4_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr4_fsp2_cfg),
+	},
+	{
+		/* P0 2400mts 2D */
+		.drate = 2400,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr4_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr4_fsp0_2d_cfg),
+	},
+#endif
+};
+
+/* ddr4 timing config params on VAL board */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr4_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr4_ddrc_cfg),
+	.ddrphy_cfg = ddr4_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr4_ddrphy_cfg),
+	.fsp_msg = ddr4_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr4_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr4_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr4_ddrphy_trained_csr),
+	.ddrphy_pie = ddr4_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr4_phy_pie),
+};
diff --git a/board/freescale/imx8mm_val/imx8mm_val.c b/board/freescale/imx8mm_val/imx8mm_val.c
new file mode 100644
index 00000000000..fe07b66df48
--- /dev/null
+++ b/board/freescale/imx8mm_val/imx8mm_val.c
@@ -0,0 +1,389 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+#include <common.h>
+#include <env.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <i2c.h>
+#include <asm/mach-imx/dma.h>
+#include "../common/tcpc.h"
+#include <usb.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#ifndef CONFIG_TARGET_IMX8MM_DDR3L_VAL
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#define SPI_PAD_CTRL	(PAD_CTL_DSE2 | PAD_CTL_HYS)
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+	IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_spi(void)
+{
+	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+	gpio_request(IMX_GPIO_NR(5, 9), "ECSPI1 CS");
+
+	init_clk_ecspi(0);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return IMX_GPIO_NR(5, 9);
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+#define NAND_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS)
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE)
+static iomux_v3_cfg_t const gpmi_pads[] = {
+	IMX8MM_PAD_NAND_ALE_RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_CLE_RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
+	IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+};
+
+static void setup_gpmi_nand(void)
+{
+	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+
+	init_nand_clk();
+}
+#endif
+
+int board_early_init_f(void)
+{
+#ifndef CONFIG_TARGET_IMX8MM_DDR3L_VAL
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+#endif
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	init_uart_clk(1);
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand(); /* SPL will call the board_early_init_f */
+#endif
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#ifndef CONFIG_TARGET_IMX8MM_DDR3L_VAL
+#define FEC_RST_PAD IMX_GPIO_NR(4, 22)
+static iomux_v3_cfg_t const fec1_rst_pads[] = {
+	IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+	imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
+					 ARRAY_SIZE(fec1_rst_pads));
+
+	gpio_request(FEC_RST_PAD, "fec1_rst");
+	gpio_direction_output(FEC_RST_PAD, 0);
+	udelay(500);
+	gpio_direction_output(FEC_RST_PAD, 1);
+}
+#endif
+
+static int setup_fec(void)
+{
+#ifdef CONFIG_TARGET_IMX8MM_DDR3L_VAL
+	struct iomuxc_gpr_base_regs *gpr
+		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+	/*
+	* GPR1 bit 13:
+	* 1:enet1 rmii clock comes from ccm->pad->loopback, SION bit for the pad (iomuxc_sw_input_on_pad_enet_td2) should be set also;
+	* 0:enet1 rmii clock comes from external phy or osc
+	*/
+
+	setbits_le32(&gpr->gpr[1],
+			IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
+	return set_clk_enet(ENET_50MHZ);
+#else
+
+	struct iomuxc_gpr_base_regs *gpr
+		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+
+	setup_iomux_fec();
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1],
+			IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0);
+	return set_clk_enet(ENET_125MHZ);
+#endif
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+#ifndef CONFIG_TARGET_IMX8MM_DDR3L_VAL
+	/* enable rgmii rxc skew and phy mode select to RGMII copper */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+#endif
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_TCPC
+struct tcpc_port port1;
+struct tcpc_port port2;
+
+static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr)
+{
+	struct udevice *bus;
+	struct udevice *i2c_dev = NULL;
+	int ret;
+	uint8_t valb;
+
+	ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus);
+	if (ret) {
+		printf("%s: Can't find bus\n", __func__);
+		return -EINVAL;
+	}
+
+	ret = dm_i2c_probe(bus, addr, 0, &i2c_dev);
+	if (ret) {
+		printf("%s: Can't find device id=0x%x\n",
+			__func__, addr);
+		return -ENODEV;
+	}
+
+	ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_read failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+	valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */
+	ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+
+	/* Set OVP threshold to 23V */
+	valb = 0x6;
+	ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+int pd_switch_snk_enable(struct tcpc_port *port)
+{
+	if (port == &port1) {
+		debug("Setup pd switch on port 1\n");
+		return setup_pd_switch(1, 0x72);
+	} else if (port == &port2) {
+		debug("Setup pd switch on port 2\n");
+		return setup_pd_switch(1, 0x73);
+	} else
+		return -EINVAL;
+}
+
+struct tcpc_port_config port1_config = {
+	.i2c_bus = 1, /*i2c2*/
+	.addr = 0x50,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 5000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 40000,
+	.op_snk_mv = 9000,
+	.switch_setup_func = &pd_switch_snk_enable,
+};
+
+struct tcpc_port_config port2_config = {
+	.i2c_bus = 1, /*i2c2*/
+	.addr = 0x52,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 9000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 40000,
+	.op_snk_mv = 9000,
+	.switch_setup_func = &pd_switch_snk_enable,
+};
+
+static int setup_typec(void)
+{
+	int ret;
+
+	debug("tcpc_init port 2\n");
+	ret = tcpc_init(&port2, port2_config, NULL);
+	if (ret) {
+		printf("%s: tcpc port2 init failed, err=%d\n",
+		       __func__, ret);
+	} else if (tcpc_pd_sink_check_charging(&port2)) {
+		/* Disable PD for USB1, since USB2 has priority */
+		port1_config.disable_pd = true;
+		printf("Power supply on USB2\n");
+	}
+
+	debug("tcpc_init port 1\n");
+	ret = tcpc_init(&port1, port1_config, NULL);
+	if (ret) {
+		printf("%s: tcpc port1 init failed, err=%d\n",
+		       __func__, ret);
+	} else {
+		if (!port1_config.disable_pd)
+			printf("Power supply on USB1\n");
+		return ret;
+	}
+
+	return ret;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_HCD
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int ret = 0;
+#ifdef CONFIG_USB_TCPC
+	struct tcpc_port *port_ptr;
+#endif
+
+	debug("board_usb_init %d, type %d\n", index, init);
+
+	imx8m_usb_power(index, true);
+
+#ifdef CONFIG_USB_TCPC
+	if (index == 0)
+		port_ptr = &port1;
+	else
+		port_ptr = &port2;
+
+	if (init == USB_INIT_HOST)
+		tcpc_setup_dfp_mode(port_ptr);
+	else
+		tcpc_setup_ufp_mode(port_ptr);
+#endif
+
+	return ret;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	debug("board_usb_cleanup %d, type %d\n", index, init);
+
+#ifdef CONFIG_USB_TCPC
+	if (init == USB_INIT_HOST) {
+		if (index == 0)
+			ret = tcpc_disable_src_vbus(&port1);
+		else
+			ret = tcpc_disable_src_vbus(&port2);
+	}
+#endif
+
+	imx8m_usb_power(index, false);
+	return ret;
+}
+
+#ifdef CONFIG_USB_TCPC
+int board_ehci_usb_phy_mode(struct udevice *dev)
+{
+	int ret = 0;
+	enum typec_cc_polarity pol;
+	enum typec_cc_state state;
+	struct tcpc_port *port_ptr;
+
+	if (dev_seq(dev) == 0)
+		port_ptr = &port1;
+	else
+		port_ptr = &port2;
+
+	tcpc_setup_ufp_mode(port_ptr);
+
+	ret = tcpc_get_cc_status(port_ptr, &pol, &state);
+	if (!ret) {
+		if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD)
+			return USB_INIT_HOST;
+	}
+
+	return USB_INIT_DEVICE;
+}
+#endif
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_USB_TCPC
+	setup_typec();
+#endif
+
+#ifdef CONFIG_MXC_SPI
+	setup_spi();
+#endif
+
+	if (IS_ENABLED(CONFIG_FEC_MXC))
+		setup_fec();
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "VAL");
+	env_set("board_rev", "iMX8MM");
+#endif
+	return 0;
+}
diff --git a/board/freescale/imx8mm_val/imximage-8mm.cfg b/board/freescale/imx8mm_val/imximage-8mm.cfg
new file mode 100644
index 00000000000..5dcb8ae72f0
--- /dev/null
+++ b/board/freescale/imx8mm_val/imximage-8mm.cfg
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+BOOT_FROM	sd
+LOADER		u-boot-spl-ddr.bin	0x7E1000
diff --git a/board/freescale/imx8mm_val/spl.c b/board/freescale/imx8mm_val/spl.c
new file mode 100644
index 00000000000..9fdd33d6bb0
--- /dev/null
+++ b/board/freescale/imx8mm_val/spl.c
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/ddr.h>
+
+#include <power/pmic.h>
+#include <power/bd71837.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	switch (boot_dev_spl) {
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD3_BOOT:
+	case MMC3_BOOT:
+		return BOOT_DEVICE_MMC2;
+	case QSPI_BOOT:
+		return BOOT_DEVICE_NOR;
+	case NAND_BOOT:
+		return BOOT_DEVICE_NAND;
+	case USB_BOOT:
+		return BOOT_DEVICE_BOARD;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+}
+
+void spl_dram_init(void)
+{
+	/* ddr train */
+	ddr_init(&dram_timing);
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MM_PAD_I2C1_SCL_I2C1_SCL | PC,
+		.gpio_mode = IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MM_PAD_I2C1_SDA_I2C1_SDA | PC,
+		.gpio_mode = IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 18)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IMX8MM_PAD_NAND_WE_B_USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_WP_B_USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+/*
+ * The evk board uses DAT3 to detect CD card plugin,
+ * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
+ */
+static iomux_v3_cfg_t const usdhc2_cd_pad =
+	IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL);
+
+static iomux_v3_cfg_t const usdhc2_dat3_pad =
+	IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
+	MUX_PAD_CTRL(USDHC_PAD_CTRL);
+
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC2_BASE_ADDR, 0, 4},
+	{USDHC3_BASE_ADDR, 0, 8},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			init_clk_usdhc(1);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+			gpio_direction_output(USDHC2_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			break;
+		case 1:
+			init_clk_usdhc(2);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC3_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		imx_iomux_v3_setup_pad(usdhc2_cd_pad);
+		gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
+		gpio_direction_input(USDHC2_CD_GPIO);
+
+		/*
+		 * Since it is the DAT3 pin, this pin is pulled to
+		 * low voltage if no card
+		 */
+		ret = gpio_get_value(USDHC2_CD_GPIO);
+
+		imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
+		return ret;
+	}
+
+	return 1;
+}
+
+#if CONFIG_IS_ENABLED(POWER_LEGACY)
+#define I2C_PMIC	0
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+
+	ret = power_bd71837_init(I2C_PMIC);
+	if (ret)
+		printf("power init failed");
+
+	p = pmic_get("BD71837");
+	pmic_probe(p);
+
+
+	/* decrease RESET key long push time from the default 10s to 10ms */
+	pmic_reg_write(p, BD718XX_PWRONCONFIG1, 0x0);
+
+	/* unlock the PMIC regs */
+	pmic_reg_write(p, BD718XX_REGLOCK, 0x1);
+
+	/* increase VDD_SOC to typical value 0.85v before first DRAM access */
+	pmic_reg_write(p, BD718XX_BUCK1_VOLT_RUN, 0x0f);
+
+	/* increase VDD_DRAM to 0.9v for 3Ghz DDR */
+	pmic_reg_write(p, BD718XX_1ST_NODVS_BUCK_VOLT, 0x2);
+
+#ifdef CONFIG_TARGET_IMX8MM_DDR4_VAL
+	/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
+	pmic_reg_write(p, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
+#elif defined(CONFIG_TARGET_IMX8MM_DDR3L_VAL)
+	/* increase NVCC_DRAM_1V35 to 1.35v for DDR3L */
+	pmic_reg_write(p, BD718XX_4TH_NODVS_BUCK_VOLT, 0x37);
+#endif
+
+	/* lock the PMIC regs */
+	pmic_reg_write(p, BD718XX_REGLOCK, 0x11);
+
+	return 0;
+}
+#endif
+
+void spl_board_init(void)
+{
+#ifndef CONFIG_SPL_USB_SDP_SUPPORT
+	/* Serial download mode */
+	if (is_usb_boot()) {
+		puts("Back to ROM, SDP\n");
+		restore_boot_params();
+	}
+#endif
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	/* Adjust pmic voltage to 1.0V for 800M */
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/board/freescale/imx8mn_evk/Kconfig b/board/freescale/imx8mn_evk/Kconfig
index 0adf87bd42a..c64189d8437 100644
--- a/board/freescale/imx8mn_evk/Kconfig
+++ b/board/freescale/imx8mn_evk/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_IMX8MN_EVK || TARGET_IMX8MN_DDR4_EVK
+if TARGET_IMX8MN_EVK || TARGET_IMX8MN_DDR4_EVK || TARGET_IMX8MN_DDR3_EVK
 
 config SYS_BOARD
 	default "imx8mn_evk"
diff --git a/board/freescale/imx8mn_evk/Makefile b/board/freescale/imx8mn_evk/Makefile
index 42d1179724d..ad3ef8edd64 100644
--- a/board/freescale/imx8mn_evk/Makefile
+++ b/board/freescale/imx8mn_evk/Makefile
@@ -14,5 +14,6 @@ obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing_ld.o
 else
 obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
 obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
+obj-$(CONFIG_IMX8M_DDR3L) += ddr3l_timing.o
 endif
 endif
diff --git a/board/freescale/imx8mn_evk/ddr3l_timing.c b/board/freescale/imx8mn_evk/ddr3l_timing.c
new file mode 100644
index 00000000000..14d18cb491f
--- /dev/null
+++ b/board/freescale/imx8mn_evk/ddr3l_timing.c
@@ -0,0 +1,944 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga
+ * For imx_v2019.04_5.4.x and above version:
+ * please replace #include <asm/arch/imx8m_ddr.h> with #include <asm/arch/ddr.h>
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x20 },
+	{ 0x3d400000, 0xa1040001 },
+	{ 0x3d400064, 0x61008c },
+	{ 0x3d4000d0, 0xc00200c5 },
+	{ 0x3d4000d4, 0x1000b },
+	{ 0x3d4000dc, 0x1d700004 },
+	{ 0x3d4000e0, 0x180000 },
+	{ 0x3d4000e4, 0x90000 },
+	{ 0x3d4000f0, 0x0 },
+	{ 0x3d4000f4, 0xee5 },
+	{ 0x3d400100, 0xc101b0e },
+	{ 0x3d400104, 0x30314 },
+	{ 0x3d400108, 0x4060509 },
+	{ 0x3d40010c, 0x2006 },
+	{ 0x3d400110, 0x6020306 },
+	{ 0x3d400114, 0x4040302 },
+	{ 0x3d400120, 0x909 },
+	{ 0x3d400180, 0x40800020 },
+	{ 0x3d400184, 0xc350 },
+	{ 0x3d400190, 0x3868203 },
+	{ 0x3d400194, 0x20303 },
+	{ 0x3d4001b4, 0x603 },
+	{ 0x3d400198, 0x7000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001a0, 0x400018 },
+	{ 0x3d4001a4, 0x5003c },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001c4, 0x0 },
+	{ 0x3d400200, 0x1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400208, 0x0 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d400240, 0x600060c },
+	{ 0x3d400244, 0x1323 },
+	{ 0x3d400400, 0x100 },
+	{ 0x3d400250, 0x7ab50b07 },
+	{ 0x3d400254, 0x22 },
+	{ 0x3d40025c, 0x7b00665e },
+	{ 0x3d400264, 0xb0000040 },
+	{ 0x3d40026c, 0x50000a0c },
+	{ 0x3d400300, 0x17 },
+	{ 0x3d40036c, 0x10000 },
+	{ 0x3d400404, 0x3051 },
+	{ 0x3d400408, 0x61d2 },
+	{ 0x3d400494, 0xe00 },
+	{ 0x3d400498, 0x7ff },
+	{ 0x3d40049c, 0xe00 },
+	{ 0x3d4004a0, 0x7ff },
+	{ 0x3d402064, 0x28003b },
+	{ 0x3d4020dc, 0x12200004 },
+	{ 0x3d4020e0, 0x0 },
+	{ 0x3d402100, 0x7090b07 },
+	{ 0x3d402104, 0x20209 },
+	{ 0x3d402108, 0x3030407 },
+	{ 0x3d40210c, 0x2006 },
+	{ 0x3d402110, 0x3020203 },
+	{ 0x3d402114, 0x3030202 },
+	{ 0x3d402120, 0x909 },
+	{ 0x3d402180, 0x40800020 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x20303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d402240, 0x6000604 },
+	{ 0x3d4020f4, 0xee5 },
+	{ 0x3d400028, 0x1 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x1005f, 0x3ff },
+	{ 0x1015f, 0x3ff },
+	{ 0x1105f, 0x3ff },
+	{ 0x1115f, 0x3ff },
+	{ 0x11005f, 0x3ff },
+	{ 0x11015f, 0x3ff },
+	{ 0x11105f, 0x3ff },
+	{ 0x11115f, 0x3ff },
+	{ 0x55, 0x3ff },
+	{ 0x1055, 0x3ff },
+	{ 0x2055, 0x3ff },
+	{ 0x3055, 0x3ff },
+	{ 0x4055, 0xff },
+	{ 0x5055, 0xff },
+	{ 0x6055, 0x3ff },
+	{ 0x7055, 0x3ff },
+	{ 0x8055, 0x3ff },
+	{ 0x9055, 0x3ff },
+	{ 0x200c5, 0xb },
+	{ 0x1200c5, 0x7 },
+	{ 0x2002e, 0x1 },
+	{ 0x12002e, 0x1 },
+	{ 0x20024, 0x0 },
+	{ 0x2003a, 0x0 },
+	{ 0x120024, 0x0 },
+	{ 0x2003a, 0x0 },
+	{ 0x20056, 0xa },
+	{ 0x120056, 0xa },
+	{ 0x1004d, 0x208 },
+	{ 0x1014d, 0x208 },
+	{ 0x1104d, 0x208 },
+	{ 0x1114d, 0x208 },
+	{ 0x11004d, 0x208 },
+	{ 0x11014d, 0x208 },
+	{ 0x11104d, 0x208 },
+	{ 0x11114d, 0x208 },
+	{ 0x10049, 0xe38 },
+	{ 0x10149, 0xe38 },
+	{ 0x11049, 0xe38 },
+	{ 0x11149, 0xe38 },
+	{ 0x110049, 0xe38 },
+	{ 0x110149, 0xe38 },
+	{ 0x111049, 0xe38 },
+	{ 0x111149, 0xe38 },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x1 },
+	{ 0x20075, 0x0 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x190 },
+	{ 0x120008, 0xa7 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x32c },
+	{ 0x10043, 0x581 },
+	{ 0x10143, 0x581 },
+	{ 0x11043, 0x581 },
+	{ 0x11143, 0x581 },
+	{ 0x1200b2, 0x32c },
+	{ 0x110043, 0x581 },
+	{ 0x110143, 0x581 },
+	{ 0x111043, 0x581 },
+	{ 0x111143, 0x581 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x20019, 0x5 },
+	{ 0x120019, 0x5 },
+	{ 0x200f0, 0x5555 },
+	{ 0x200f1, 0x5555 },
+	{ 0x200f2, 0x5555 },
+	{ 0x200f3, 0x5555 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0x5555 },
+	{ 0x200f6, 0x5555 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{0x0200b2,0x0},
+	{0x1200b2,0x0},
+	{0x2200b2,0x0},
+	{0x0200cb,0x0},
+	{0x010043,0x0},
+	{0x110043,0x0},
+	{0x210043,0x0},
+	{0x010143,0x0},
+	{0x110143,0x0},
+	{0x210143,0x0},
+	{0x011043,0x0},
+	{0x111043,0x0},
+	{0x211043,0x0},
+	{0x011143,0x0},
+	{0x111143,0x0},
+	{0x211143,0x0},
+	{0x000080,0x0},
+	{0x100080,0x0},
+	{0x200080,0x0},
+	{0x001080,0x0},
+	{0x101080,0x0},
+	{0x201080,0x0},
+	{0x002080,0x0},
+	{0x102080,0x0},
+	{0x202080,0x0},
+	{0x003080,0x0},
+	{0x103080,0x0},
+	{0x203080,0x0},
+	{0x004080,0x0},
+	{0x104080,0x0},
+	{0x204080,0x0},
+	{0x005080,0x0},
+	{0x105080,0x0},
+	{0x205080,0x0},
+	{0x006080,0x0},
+	{0x106080,0x0},
+	{0x206080,0x0},
+	{0x007080,0x0},
+	{0x107080,0x0},
+	{0x207080,0x0},
+	{0x008080,0x0},
+	{0x108080,0x0},
+	{0x208080,0x0},
+	{0x009080,0x0},
+	{0x109080,0x0},
+	{0x209080,0x0},
+	{0x010080,0x0},
+	{0x110080,0x0},
+	{0x210080,0x0},
+	{0x010180,0x0},
+	{0x110180,0x0},
+	{0x210180,0x0},
+	{0x010081,0x0},
+	{0x110081,0x0},
+	{0x210081,0x0},
+	{0x010181,0x0},
+	{0x110181,0x0},
+	{0x210181,0x0},
+	{0x010082,0x0},
+	{0x110082,0x0},
+	{0x210082,0x0},
+	{0x010182,0x0},
+	{0x110182,0x0},
+	{0x210182,0x0},
+	{0x010083,0x0},
+	{0x110083,0x0},
+	{0x210083,0x0},
+	{0x010183,0x0},
+	{0x110183,0x0},
+	{0x210183,0x0},
+	{0x011080,0x0},
+	{0x111080,0x0},
+	{0x211080,0x0},
+	{0x011180,0x0},
+	{0x111180,0x0},
+	{0x211180,0x0},
+	{0x011081,0x0},
+	{0x111081,0x0},
+	{0x211081,0x0},
+	{0x011181,0x0},
+	{0x111181,0x0},
+	{0x211181,0x0},
+	{0x011082,0x0},
+	{0x111082,0x0},
+	{0x211082,0x0},
+	{0x011182,0x0},
+	{0x111182,0x0},
+	{0x211182,0x0},
+	{0x011083,0x0},
+	{0x111083,0x0},
+	{0x211083,0x0},
+	{0x011183,0x0},
+	{0x111183,0x0},
+	{0x211183,0x0},
+	{0x0100d0,0x0},
+	{0x1100d0,0x0},
+	{0x2100d0,0x0},
+	{0x0101d0,0x0},
+	{0x1101d0,0x0},
+	{0x2101d0,0x0},
+	{0x0100d1,0x0},
+	{0x1100d1,0x0},
+	{0x2100d1,0x0},
+	{0x0101d1,0x0},
+	{0x1101d1,0x0},
+	{0x2101d1,0x0},
+	{0x0100d2,0x0},
+	{0x1100d2,0x0},
+	{0x2100d2,0x0},
+	{0x0101d2,0x0},
+	{0x1101d2,0x0},
+	{0x2101d2,0x0},
+	{0x0100d3,0x0},
+	{0x1100d3,0x0},
+	{0x2100d3,0x0},
+	{0x0101d3,0x0},
+	{0x1101d3,0x0},
+	{0x2101d3,0x0},
+	{0x0110d0,0x0},
+	{0x1110d0,0x0},
+	{0x2110d0,0x0},
+	{0x0111d0,0x0},
+	{0x1111d0,0x0},
+	{0x2111d0,0x0},
+	{0x0110d1,0x0},
+	{0x1110d1,0x0},
+	{0x2110d1,0x0},
+	{0x0111d1,0x0},
+	{0x1111d1,0x0},
+	{0x2111d1,0x0},
+	{0x0110d2,0x0},
+	{0x1110d2,0x0},
+	{0x2110d2,0x0},
+	{0x0111d2,0x0},
+	{0x1111d2,0x0},
+	{0x2111d2,0x0},
+	{0x0110d3,0x0},
+	{0x1110d3,0x0},
+	{0x2110d3,0x0},
+	{0x0111d3,0x0},
+	{0x1111d3,0x0},
+	{0x2111d3,0x0},
+	{0x010068,0x0},
+	{0x010168,0x0},
+	{0x010268,0x0},
+	{0x010368,0x0},
+	{0x010468,0x0},
+	{0x010568,0x0},
+	{0x010668,0x0},
+	{0x010768,0x0},
+	{0x010868,0x0},
+	{0x010069,0x0},
+	{0x010169,0x0},
+	{0x010269,0x0},
+	{0x010369,0x0},
+	{0x010469,0x0},
+	{0x010569,0x0},
+	{0x010669,0x0},
+	{0x010769,0x0},
+	{0x010869,0x0},
+	{0x01006a,0x0},
+	{0x01016a,0x0},
+	{0x01026a,0x0},
+	{0x01036a,0x0},
+	{0x01046a,0x0},
+	{0x01056a,0x0},
+	{0x01066a,0x0},
+	{0x01076a,0x0},
+	{0x01086a,0x0},
+	{0x01006b,0x0},
+	{0x01016b,0x0},
+	{0x01026b,0x0},
+	{0x01036b,0x0},
+	{0x01046b,0x0},
+	{0x01056b,0x0},
+	{0x01066b,0x0},
+	{0x01076b,0x0},
+	{0x01086b,0x0},
+	{0x011068,0x0},
+	{0x011168,0x0},
+	{0x011268,0x0},
+	{0x011368,0x0},
+	{0x011468,0x0},
+	{0x011568,0x0},
+	{0x011668,0x0},
+	{0x011768,0x0},
+	{0x011868,0x0},
+	{0x011069,0x0},
+	{0x011169,0x0},
+	{0x011269,0x0},
+	{0x011369,0x0},
+	{0x011469,0x0},
+	{0x011569,0x0},
+	{0x011669,0x0},
+	{0x011769,0x0},
+	{0x011869,0x0},
+	{0x01106a,0x0},
+	{0x01116a,0x0},
+	{0x01126a,0x0},
+	{0x01136a,0x0},
+	{0x01146a,0x0},
+	{0x01156a,0x0},
+	{0x01166a,0x0},
+	{0x01176a,0x0},
+	{0x01186a,0x0},
+	{0x01106b,0x0},
+	{0x01116b,0x0},
+	{0x01126b,0x0},
+	{0x01136b,0x0},
+	{0x01146b,0x0},
+	{0x01156b,0x0},
+	{0x01166b,0x0},
+	{0x01176b,0x0},
+	{0x01186b,0x0},
+	{0x01008c,0x0},
+	{0x11008c,0x0},
+	{0x21008c,0x0},
+	{0x01018c,0x0},
+	{0x11018c,0x0},
+	{0x21018c,0x0},
+	{0x01008d,0x0},
+	{0x11008d,0x0},
+	{0x21008d,0x0},
+	{0x01018d,0x0},
+	{0x11018d,0x0},
+	{0x21018d,0x0},
+	{0x01008e,0x0},
+	{0x11008e,0x0},
+	{0x21008e,0x0},
+	{0x01018e,0x0},
+	{0x11018e,0x0},
+	{0x21018e,0x0},
+	{0x01008f,0x0},
+	{0x11008f,0x0},
+	{0x21008f,0x0},
+	{0x01018f,0x0},
+	{0x11018f,0x0},
+	{0x21018f,0x0},
+	{0x01108c,0x0},
+	{0x11108c,0x0},
+	{0x21108c,0x0},
+	{0x01118c,0x0},
+	{0x11118c,0x0},
+	{0x21118c,0x0},
+	{0x01108d,0x0},
+	{0x11108d,0x0},
+	{0x21108d,0x0},
+	{0x01118d,0x0},
+	{0x11118d,0x0},
+	{0x21118d,0x0},
+	{0x01108e,0x0},
+	{0x11108e,0x0},
+	{0x21108e,0x0},
+	{0x01118e,0x0},
+	{0x11118e,0x0},
+	{0x21118e,0x0},
+	{0x01108f,0x0},
+	{0x11108f,0x0},
+	{0x21108f,0x0},
+	{0x01118f,0x0},
+	{0x11118f,0x0},
+	{0x21118f,0x0},
+	{0x0100c0,0x0},
+	{0x1100c0,0x0},
+	{0x2100c0,0x0},
+	{0x0101c0,0x0},
+	{0x1101c0,0x0},
+	{0x2101c0,0x0},
+	{0x0102c0,0x0},
+	{0x1102c0,0x0},
+	{0x2102c0,0x0},
+	{0x0103c0,0x0},
+	{0x1103c0,0x0},
+	{0x2103c0,0x0},
+	{0x0104c0,0x0},
+	{0x1104c0,0x0},
+	{0x2104c0,0x0},
+	{0x0105c0,0x0},
+	{0x1105c0,0x0},
+	{0x2105c0,0x0},
+	{0x0106c0,0x0},
+	{0x1106c0,0x0},
+	{0x2106c0,0x0},
+	{0x0107c0,0x0},
+	{0x1107c0,0x0},
+	{0x2107c0,0x0},
+	{0x0108c0,0x0},
+	{0x1108c0,0x0},
+	{0x2108c0,0x0},
+	{0x0100c1,0x0},
+	{0x1100c1,0x0},
+	{0x2100c1,0x0},
+	{0x0101c1,0x0},
+	{0x1101c1,0x0},
+	{0x2101c1,0x0},
+	{0x0102c1,0x0},
+	{0x1102c1,0x0},
+	{0x2102c1,0x0},
+	{0x0103c1,0x0},
+	{0x1103c1,0x0},
+	{0x2103c1,0x0},
+	{0x0104c1,0x0},
+	{0x1104c1,0x0},
+	{0x2104c1,0x0},
+	{0x0105c1,0x0},
+	{0x1105c1,0x0},
+	{0x2105c1,0x0},
+	{0x0106c1,0x0},
+	{0x1106c1,0x0},
+	{0x2106c1,0x0},
+	{0x0107c1,0x0},
+	{0x1107c1,0x0},
+	{0x2107c1,0x0},
+	{0x0108c1,0x0},
+	{0x1108c1,0x0},
+	{0x2108c1,0x0},
+	{0x0100c2,0x0},
+	{0x1100c2,0x0},
+	{0x2100c2,0x0},
+	{0x0101c2,0x0},
+	{0x1101c2,0x0},
+	{0x2101c2,0x0},
+	{0x0102c2,0x0},
+	{0x1102c2,0x0},
+	{0x2102c2,0x0},
+	{0x0103c2,0x0},
+	{0x1103c2,0x0},
+	{0x2103c2,0x0},
+	{0x0104c2,0x0},
+	{0x1104c2,0x0},
+	{0x2104c2,0x0},
+	{0x0105c2,0x0},
+	{0x1105c2,0x0},
+	{0x2105c2,0x0},
+	{0x0106c2,0x0},
+	{0x1106c2,0x0},
+	{0x2106c2,0x0},
+	{0x0107c2,0x0},
+	{0x1107c2,0x0},
+	{0x2107c2,0x0},
+	{0x0108c2,0x0},
+	{0x1108c2,0x0},
+	{0x2108c2,0x0},
+	{0x0100c3,0x0},
+	{0x1100c3,0x0},
+	{0x2100c3,0x0},
+	{0x0101c3,0x0},
+	{0x1101c3,0x0},
+	{0x2101c3,0x0},
+	{0x0102c3,0x0},
+	{0x1102c3,0x0},
+	{0x2102c3,0x0},
+	{0x0103c3,0x0},
+	{0x1103c3,0x0},
+	{0x2103c3,0x0},
+	{0x0104c3,0x0},
+	{0x1104c3,0x0},
+	{0x2104c3,0x0},
+	{0x0105c3,0x0},
+	{0x1105c3,0x0},
+	{0x2105c3,0x0},
+	{0x0106c3,0x0},
+	{0x1106c3,0x0},
+	{0x2106c3,0x0},
+	{0x0107c3,0x0},
+	{0x1107c3,0x0},
+	{0x2107c3,0x0},
+	{0x0108c3,0x0},
+	{0x1108c3,0x0},
+	{0x2108c3,0x0},
+	{0x0110c0,0x0},
+	{0x1110c0,0x0},
+	{0x2110c0,0x0},
+	{0x0111c0,0x0},
+	{0x1111c0,0x0},
+	{0x2111c0,0x0},
+	{0x0112c0,0x0},
+	{0x1112c0,0x0},
+	{0x2112c0,0x0},
+	{0x0113c0,0x0},
+	{0x1113c0,0x0},
+	{0x2113c0,0x0},
+	{0x0114c0,0x0},
+	{0x1114c0,0x0},
+	{0x2114c0,0x0},
+	{0x0115c0,0x0},
+	{0x1115c0,0x0},
+	{0x2115c0,0x0},
+	{0x0116c0,0x0},
+	{0x1116c0,0x0},
+	{0x2116c0,0x0},
+	{0x0117c0,0x0},
+	{0x1117c0,0x0},
+	{0x2117c0,0x0},
+	{0x0118c0,0x0},
+	{0x1118c0,0x0},
+	{0x2118c0,0x0},
+	{0x0110c1,0x0},
+	{0x1110c1,0x0},
+	{0x2110c1,0x0},
+	{0x0111c1,0x0},
+	{0x1111c1,0x0},
+	{0x2111c1,0x0},
+	{0x0112c1,0x0},
+	{0x1112c1,0x0},
+	{0x2112c1,0x0},
+	{0x0113c1,0x0},
+	{0x1113c1,0x0},
+	{0x2113c1,0x0},
+	{0x0114c1,0x0},
+	{0x1114c1,0x0},
+	{0x2114c1,0x0},
+	{0x0115c1,0x0},
+	{0x1115c1,0x0},
+	{0x2115c1,0x0},
+	{0x0116c1,0x0},
+	{0x1116c1,0x0},
+	{0x2116c1,0x0},
+	{0x0117c1,0x0},
+	{0x1117c1,0x0},
+	{0x2117c1,0x0},
+	{0x0118c1,0x0},
+	{0x1118c1,0x0},
+	{0x2118c1,0x0},
+	{0x0110c2,0x0},
+	{0x1110c2,0x0},
+	{0x2110c2,0x0},
+	{0x0111c2,0x0},
+	{0x1111c2,0x0},
+	{0x2111c2,0x0},
+	{0x0112c2,0x0},
+	{0x1112c2,0x0},
+	{0x2112c2,0x0},
+	{0x0113c2,0x0},
+	{0x1113c2,0x0},
+	{0x2113c2,0x0},
+	{0x0114c2,0x0},
+	{0x1114c2,0x0},
+	{0x2114c2,0x0},
+	{0x0115c2,0x0},
+	{0x1115c2,0x0},
+	{0x2115c2,0x0},
+	{0x0116c2,0x0},
+	{0x1116c2,0x0},
+	{0x2116c2,0x0},
+	{0x0117c2,0x0},
+	{0x1117c2,0x0},
+	{0x2117c2,0x0},
+	{0x0118c2,0x0},
+	{0x1118c2,0x0},
+	{0x2118c2,0x0},
+	{0x0110c3,0x0},
+	{0x1110c3,0x0},
+	{0x2110c3,0x0},
+	{0x0111c3,0x0},
+	{0x1111c3,0x0},
+	{0x2111c3,0x0},
+	{0x0112c3,0x0},
+	{0x1112c3,0x0},
+	{0x2112c3,0x0},
+	{0x0113c3,0x0},
+	{0x1113c3,0x0},
+	{0x2113c3,0x0},
+	{0x0114c3,0x0},
+	{0x1114c3,0x0},
+	{0x2114c3,0x0},
+	{0x0115c3,0x0},
+	{0x1115c3,0x0},
+	{0x2115c3,0x0},
+	{0x0116c3,0x0},
+	{0x1116c3,0x0},
+	{0x2116c3,0x0},
+	{0x0117c3,0x0},
+	{0x1117c3,0x0},
+	{0x2117c3,0x0},
+	{0x0118c3,0x0},
+	{0x1118c3,0x0},
+	{0x2118c3,0x0},
+	{0x010020,0x0},
+	{0x110020,0x0},
+	{0x210020,0x0},
+	{0x011020,0x0},
+	{0x111020,0x0},
+	{0x211020,0x0},
+	{0x02007d,0x0},
+	{0x12007d,0x0},
+	{0x22007d,0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0x640 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x283c },
+	{ 0x54006, 0x140 },
+	{ 0x54007, 0x1000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x31f },
+	{ 0x5400c, 0xc8 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x1d70 },
+	{ 0x54030, 0x4 },
+	{ 0x54031, 0x18 },
+	{ 0x5403a, 0x1323 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x1 },
+	{ 0x54003, 0x29c },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x283c },
+	{ 0x54006, 0x140 },
+	{ 0x54007, 0x1000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x21f },
+	{ 0x5400c, 0xc8 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x1220 },
+	{ 0x54030, 0x4 },
+	{ 0x5403a, 0x1323 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x2 },
+	{ 0x90033, 0x10 },
+	{ 0x90034, 0x139 },
+	{ 0x90035, 0xb },
+	{ 0x90036, 0x7c0 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0x44 },
+	{ 0x90039, 0x633 },
+	{ 0x9003a, 0x159 },
+	{ 0x9003b, 0x14f },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x47 },
+	{ 0x9003f, 0x633 },
+	{ 0x90040, 0x149 },
+	{ 0x90041, 0x4f },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x179 },
+	{ 0x90044, 0x8 },
+	{ 0x90045, 0xe0 },
+	{ 0x90046, 0x109 },
+	{ 0x90047, 0x0 },
+	{ 0x90048, 0x7c8 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x1 },
+	{ 0x9004c, 0x8 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x45a },
+	{ 0x9004f, 0x9 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x448 },
+	{ 0x90052, 0x109 },
+	{ 0x90053, 0x40 },
+	{ 0x90054, 0x633 },
+	{ 0x90055, 0x179 },
+	{ 0x90056, 0x1 },
+	{ 0x90057, 0x618 },
+	{ 0x90058, 0x109 },
+	{ 0x90059, 0x40c0 },
+	{ 0x9005a, 0x633 },
+	{ 0x9005b, 0x149 },
+	{ 0x9005c, 0x8 },
+	{ 0x9005d, 0x4 },
+	{ 0x9005e, 0x48 },
+	{ 0x9005f, 0x4040 },
+	{ 0x90060, 0x633 },
+	{ 0x90061, 0x149 },
+	{ 0x90062, 0x0 },
+	{ 0x90063, 0x4 },
+	{ 0x90064, 0x48 },
+	{ 0x90065, 0x40 },
+	{ 0x90066, 0x633 },
+	{ 0x90067, 0x149 },
+	{ 0x90068, 0x10 },
+	{ 0x90069, 0x4 },
+	{ 0x9006a, 0x18 },
+	{ 0x9006b, 0x0 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x78 },
+	{ 0x9006e, 0x549 },
+	{ 0x9006f, 0x633 },
+	{ 0x90070, 0x159 },
+	{ 0x90071, 0xd49 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0x94a },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x441 },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x149 },
+	{ 0x9007a, 0x42 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x1 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x0 },
+	{ 0x90081, 0xe0 },
+	{ 0x90082, 0x109 },
+	{ 0x90083, 0xa },
+	{ 0x90084, 0x10 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0x9 },
+	{ 0x90087, 0x3c0 },
+	{ 0x90088, 0x149 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x159 },
+	{ 0x9008c, 0x18 },
+	{ 0x9008d, 0x10 },
+	{ 0x9008e, 0x109 },
+	{ 0x9008f, 0x0 },
+	{ 0x90090, 0x3c0 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x18 },
+	{ 0x90093, 0x4 },
+	{ 0x90094, 0x48 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x58 },
+	{ 0x90098, 0xb },
+	{ 0x90099, 0x10 },
+	{ 0x9009a, 0x109 },
+	{ 0x9009b, 0x1 },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x5 },
+	{ 0x9009f, 0x7c0 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x0 },
+	{ 0x900a2, 0x8140 },
+	{ 0x900a3, 0x10c },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x8138 },
+	{ 0x900a6, 0x10c },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7c8 },
+	{ 0x900a9, 0x101 },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x448 },
+	{ 0x900ac, 0x109 },
+	{ 0x900ad, 0xf },
+	{ 0x900ae, 0x7c0 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x47 },
+	{ 0x900b1, 0x630 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x8 },
+	{ 0x900b4, 0x618 },
+	{ 0x900b5, 0x109 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0xe0 },
+	{ 0x900b8, 0x109 },
+	{ 0x900b9, 0x0 },
+	{ 0x900ba, 0x7c8 },
+	{ 0x900bb, 0x109 },
+	{ 0x900bc, 0x8 },
+	{ 0x900bd, 0x8140 },
+	{ 0x900be, 0x10c },
+	{ 0x900bf, 0x0 },
+	{ 0x900c0, 0x1 },
+	{ 0x900c1, 0x8 },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x8 },
+	{ 0x900c5, 0x8 },
+	{ 0x900c6, 0x7c8 },
+	{ 0x900c7, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x90026, 0x2b },
+	{ 0x2000b, 0x32 },
+	{ 0x2000c, 0x64 },
+	{ 0x2000d, 0x3e8 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x14 },
+	{ 0x12000c, 0x26 },
+	{ 0x12000d, 0x1a1 },
+	{ 0x12000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0xffff },
+	{ 0x90013, 0x6152 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x0 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 1600mts 1D */
+		.drate = 1600,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 1600, 667, },
+};
+
diff --git a/board/freescale/imx8mn_evk/ddr4_timing.c b/board/freescale/imx8mn_evk/ddr4_timing.c
index 77611ea0260..06897031a20 100644
--- a/board/freescale/imx8mn_evk/ddr4_timing.c
+++ b/board/freescale/imx8mn_evk/ddr4_timing.c
@@ -763,6 +763,7 @@ struct dram_cfg_param ddr_fsp0_cfg[] = {
 	{ 0xd0000, 0x1 },
 };
 
+
 /* P1 message block paremeter for training firmware */
 struct dram_cfg_param ddr_fsp1_cfg[] = {
 	{ 0xd0000, 0x0 },
diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c b/board/freescale/imx8mn_evk/imx8mn_evk.c
index b24342fd5ca..92601393cb1 100644
--- a/board/freescale/imx8mn_evk/imx8mn_evk.c
+++ b/board/freescale/imx8mn_evk/imx8mn_evk.c
@@ -9,26 +9,104 @@
 #include <asm/global_data.h>
 #include <miiphy.h>
 #include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/imx8mn_pins.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <i2c.h>
 #include <asm/io.h>
+#include "../common/tcpc.h"
+#include <usb.h>
+#include <imx_sip.h>
+#include <linux/arm-smccc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int board_mmc_get_env_dev(int devno)
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+#ifdef CONFIG_NAND_MXS
+#ifdef CONFIG_SPL_BUILD
+#define NAND_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS)
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE)
+static iomux_v3_cfg_t const gpmi_pads[] = {
+	IMX8MN_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MN_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MN_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MN_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MN_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MN_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MN_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MN_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MN_PAD_NAND_DATA05__RAWNAND_DATA05	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MN_PAD_NAND_DATA06__RAWNAND_DATA06	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MN_PAD_NAND_DATA07__RAWNAND_DATA07	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MN_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MN_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
+	IMX8MN_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MN_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+};
+#endif
+
+static void setup_gpmi_nand(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+#endif
+
+	init_nand_clk();
+}
+#endif
+
+int board_early_init_f(void)
 {
-	return devno;
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	init_uart_clk(1);
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand(); /* SPL will call the board_early_init_f */
+#endif
+
+	return 0;
 }
 
-static void setup_fec(void)
+#if IS_ENABLED(CONFIG_FEC_MXC)
+static int setup_fec(void)
 {
 	struct iomuxc_gpr_base_regs *gpr =
 		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 
 	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
 	clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+
+	return 0;
 }
 
 int board_phy_config(struct phy_device *phydev)
 {
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+#ifndef CONFIG_DM_ETH
 	/* enable rgmii rxc skew and phy mode select to RGMII copper */
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
@@ -37,24 +115,235 @@ int board_phy_config(struct phy_device *phydev)
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+#endif
 
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
 	return 0;
 }
+#endif
+
+#ifdef CONFIG_USB_TCPC
+struct tcpc_port port1;
+struct tcpc_port port2;
+
+static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr)
+{
+	struct udevice *bus;
+	struct udevice *i2c_dev = NULL;
+	int ret;
+	uint8_t valb;
+
+	ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus);
+	if (ret) {
+		printf("%s: Can't find bus\n", __func__);
+		return -EINVAL;
+	}
+
+	ret = dm_i2c_probe(bus, addr, 0, &i2c_dev);
+	if (ret) {
+		printf("%s: Can't find device id=0x%x\n",
+			__func__, addr);
+		return -ENODEV;
+	}
+
+	ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_read failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+	valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */
+	ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+
+	/* Set OVP threshold to 23V */
+	valb = 0x6;
+	ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+int pd_switch_snk_enable(struct tcpc_port *port)
+{
+	if (port == &port1) {
+		debug("Setup pd switch on port 1\n");
+		return setup_pd_switch(1, 0x72);
+	} else if (port == &port2) {
+		debug("Setup pd switch on port 2\n");
+		return setup_pd_switch(1, 0x73);
+	} else
+		return -EINVAL;
+}
+
+struct tcpc_port_config port1_config = {
+	.i2c_bus = 1, /*i2c2*/
+	.addr = 0x50,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 5000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 40000,
+	.op_snk_mv = 9000,
+	.switch_setup_func = &pd_switch_snk_enable,
+};
+
+struct tcpc_port_config port2_config = {
+	.i2c_bus = 1, /*i2c2*/
+	.addr = 0x52,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 9000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 40000,
+	.op_snk_mv = 9000,
+	.switch_setup_func = &pd_switch_snk_enable,
+};
+
+static int setup_typec(void)
+{
+	int ret;
+
+	debug("tcpc_init port 2\n");
+	ret = tcpc_init(&port2, port2_config, NULL);
+	if (ret) {
+		printf("%s: tcpc port2 init failed, err=%d\n",
+		       __func__, ret);
+	} else if (tcpc_pd_sink_check_charging(&port2)) {
+		/* Disable PD for USB1, since USB2 has priority */
+		port1_config.disable_pd = true;
+		printf("Power supply on USB2\n");
+	}
+
+	debug("tcpc_init port 1\n");
+	ret = tcpc_init(&port1, port1_config, NULL);
+	if (ret) {
+		printf("%s: tcpc port1 init failed, err=%d\n",
+		       __func__, ret);
+	} else {
+		if (!port1_config.disable_pd)
+			printf("Power supply on USB1\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int ret = 0;
+	struct tcpc_port *port_ptr;
+
+	debug("board_usb_init %d, type %d\n", index, init);
+
+	if (index == 0)
+		port_ptr = &port1;
+	else
+		port_ptr = &port2;
+
+	imx8m_usb_power(index, true);
+
+	if (init == USB_INIT_HOST)
+		tcpc_setup_dfp_mode(port_ptr);
+	else
+		tcpc_setup_ufp_mode(port_ptr);
+
+	return ret;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	debug("board_usb_cleanup %d, type %d\n", index, init);
+
+	if (init == USB_INIT_HOST) {
+		if (index == 0)
+			ret = tcpc_disable_src_vbus(&port1);
+		else
+			ret = tcpc_disable_src_vbus(&port2);
+	}
+
+	imx8m_usb_power(index, false);
+	return ret;
+}
+
+int board_ehci_usb_phy_mode(struct udevice *dev)
+{
+	int ret = 0;
+	enum typec_cc_polarity pol;
+	enum typec_cc_state state;
+	struct tcpc_port *port_ptr;
+
+	if (dev_seq(dev) == 0)
+		port_ptr = &port1;
+	else
+		port_ptr = &port2;
+
+	tcpc_setup_ufp_mode(port_ptr);
+
+	ret = tcpc_get_cc_status(port_ptr, &pol, &state);
+	if (!ret) {
+		if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD)
+			return USB_INIT_HOST;
+	}
+
+	return USB_INIT_DEVICE;
+}
+
+#endif
+
+#define DISPMIX				9
+#define MIPI				10
 
 int board_init(void)
 {
-	setup_fec();
+	struct arm_smccc_res res;
+
+#ifdef CONFIG_USB_TCPC
+	setup_typec();
+
+	/* Enable Power by default for SR-IR usage */
+	imx8m_usb_power(0, true);
+#endif
+
+	if (IS_ENABLED(CONFIG_FEC_MXC))
+		setup_fec();
+
+	arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN,
+		      DISPMIX, true, 0, 0, 0, 0, &res);
+	arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN,
+		      MIPI, true, 0, 0, 0, 0, &res);
 
 	return 0;
 }
 
 int board_late_init(void)
 {
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	env_set("board_name", "DDR4 EVK");
 	env_set("board_rev", "iMX8MN");
 #endif
 	return 0;
 }
+
+#ifdef CONFIG_ANDROID_SUPPORT
+bool is_power_key_pressed(void) {
+	return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6)));
+}
+#endif
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+int is_recovery_key_pressing(void)
+{
+	return 0; /* TODO */
+}
+#endif /* CONFIG_ANDROID_RECOVERY */
+#endif /* CONFIG_FSL_FASTBOOT */
diff --git a/board/freescale/imx8mn_evk/lpddr4_timing.c b/board/freescale/imx8mn_evk/lpddr4_timing.c
index 671e924132a..0ce039a95fb 100644
--- a/board/freescale/imx8mn_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mn_evk/lpddr4_timing.c
@@ -122,7 +122,6 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
 
 /* PHY Initialize Configuration */
 struct dram_cfg_param ddr_ddrphy_cfg[] = {
-	{0x000d0000, 0x00000000},
 	{0x000100a0, 0x00000000},
 	{0x000100a1, 0x00000001},
 	{0x000100a2, 0x00000002},
@@ -271,8 +270,6 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
 	{0x002200c7, 0x00000021},
 	{0x002200ca, 0x00000024},
 	{0x002200cc, 0x000001f7},
-	{0x00020060, 0x00000002},
-	{0x000d0000, 0x00000001},
 };
 
 /* ddr phy trained csr */
diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c
index 03f2a56e805..fee5db8cf0f 100644
--- a/board/freescale/imx8mn_evk/spl.c
+++ b/board/freescale/imx8mn_evk/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
 /*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2019, 2021 NXP
  *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -27,16 +27,39 @@
 #include <dm/device-internal.h>
 #include <power/pmic.h>
 #include <power/pca9450.h>
+#include <power/bd71837.h>
 #include <asm/mach-imx/gpio.h>
 #include <asm/mach-imx/mxc_i2c.h>
 #include <fsl_esdhc_imx.h>
 #include <mmc.h>
+#include <linux/delay.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int spl_board_boot_device(enum boot_device boot_dev_spl)
 {
+#ifdef CONFIG_SPL_BOOTROM_SUPPORT
 	return BOOT_DEVICE_BOOTROM;
+#else
+	switch (boot_dev_spl) {
+	case SD1_BOOT:
+	case MMC1_BOOT:
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD3_BOOT:
+	case MMC3_BOOT:
+		return BOOT_DEVICE_MMC2;
+	case QSPI_BOOT:
+		return BOOT_DEVICE_NOR;
+	case NAND_BOOT:
+		return BOOT_DEVICE_NAND;
+	case USB_BOOT:
+		return BOOT_DEVICE_BOARD;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+#endif
 }
 
 void spl_dram_init(void)
@@ -44,19 +67,49 @@ void spl_dram_init(void)
 	ddr_init(&dram_timing);
 }
 
-void spl_board_init(void)
+#if CONFIG_IS_ENABLED(DM_PMIC_BD71837)
+int power_init_board(void)
 {
 	struct udevice *dev;
 	int ret;
 
-	puts("Normal Boot\n");
+	ret = pmic_get("pmic@4b", &dev);
+	if (ret == -ENODEV) {
+		puts("No pmic@4b\n");
+		return 0;
+	}
+	if (ret != 0)
+		return ret;
 
-	ret = uclass_get_device_by_name(UCLASS_CLK,
-					"clock-controller@30380000",
-					&dev);
-	if (ret < 0)
-		printf("Failed to find clock node. Check device tree\n");
+	/* decrease RESET key long push time from the default 10s to 10ms */
+	pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
+
+	/* unlock the PMIC regs */
+	pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
+
+	/* Set VDD_ARM to typical value 0.85v for 1.2Ghz */
+	pmic_reg_write(dev, BD718XX_BUCK2_VOLT_RUN, 0xf);
+
+#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
+	/* Set VDD_SOC/VDD_DRAM to typical value 0.8v for low drive mode */
+	pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0xa);
+#else
+	/* Set VDD_SOC/VDD_DRAM to typical value 0.85v for nominal mode */
+	pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0xf);
+#endif /* CONFIG_IMX8MN_LOW_DRIVE_MODE */
+
+	/* Set VDD_SOC 0.75v for low-v suspend */
+	pmic_reg_write(dev, BD718XX_BUCK1_VOLT_SUSP, 0x5);
+
+	/* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
+	pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
+
+	/* lock the PMIC regs */
+	pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
+
+	return 0;
 }
+#endif
 
 #if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
 int power_init_board(void)
@@ -78,13 +131,22 @@ int power_init_board(void)
 #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
 	/* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */
 	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10);
+#elif defined(CONFIG_TARGET_IMX8MN_DDR3_EVK)
+	/* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
+
+	/* Disable the BUCK2 */
+	pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48);
+
+	/* Set NVCC_DRAM to 1.35v */
+	pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E);
 #else
 	/* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */
 	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
 #endif
-	/* Set DVS1 to 0.85v for suspend */
+	/* Set DVS1 to 0.75v for low-v suspend */
 	/* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */
-	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0xC);
 	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
 
 	/* set VDD_SNVS_0V8 from default 0.85V */
@@ -100,6 +162,19 @@ int power_init_board(void)
 }
 #endif
 
+void spl_board_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+		if (ret)
+			printf("Failed to initialize caam_jr: %d\n", ret);
+	}
+	puts("Normal Boot\n");
+}
+
 #ifdef CONFIG_SPL_LOAD_FIT
 int board_fit_config_name_match(const char *name)
 {
@@ -110,38 +185,15 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
-#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
-#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
-
-static iomux_v3_cfg_t const uart_pads[] = {
-	IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const wdog_pads[] = {
-	IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-
-int board_early_init_f(void)
-{
-	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
-
-	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
-
-	set_wdog_reset(wdog);
-
-	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
-	return 0;
-}
-
 void board_init_f(ulong dummy)
 {
+	struct udevice *dev;
 	int ret;
 
-	arch_cpu_init();
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
 
-	init_uart_clk(1);
+	arch_cpu_init();
 
 	board_early_init_f();
 
@@ -149,19 +201,41 @@ void board_init_f(ulong dummy)
 
 	preloader_console_init();
 
-	/* Clear the BSS. */
-	memset(__bss_start, 0, __bss_end - __bss_start);
-
-	ret = spl_init();
+	ret = spl_early_init();
 	if (ret) {
-		debug("spl_init() failed: %d\n", ret);
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	ret = uclass_get_device_by_name(UCLASS_CLK,
+					"clock-controller@30380000",
+					&dev);
+	if (ret < 0) {
+		printf("Failed to find clock node. Check device tree\n");
 		hang();
 	}
 
 	enable_tzc380();
 
+	power_init_board();
+
 	/* DDR initialization */
 	spl_dram_init();
 
 	board_init_r(NULL, 0);
 }
+
+#ifdef CONFIG_SPL_MMC
+#define UBOOT_RAW_SECTOR_OFFSET 0x40
+unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc)
+{
+	u32 boot_dev = spl_boot_device();
+	switch (boot_dev) {
+		case BOOT_DEVICE_MMC1:
+			return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
+		case BOOT_DEVICE_MMC2:
+			return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET;
+	}
+	return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
+}
+#endif
diff --git a/board/freescale/imx8mp_evk/Kconfig b/board/freescale/imx8mp_evk/Kconfig
index 42625fd5888..e2901707858 100644
--- a/board/freescale/imx8mp_evk/Kconfig
+++ b/board/freescale/imx8mp_evk/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_IMX8MP_EVK
+if TARGET_IMX8MP_EVK || TARGET_IMX8MP_DDR4_EVK
 
 config SYS_BOARD
 	default "imx8mp_evk"
diff --git a/board/freescale/imx8mp_evk/Makefile b/board/freescale/imx8mp_evk/Makefile
index 106bf9a1edf..1421e46628a 100644
--- a/board/freescale/imx8mp_evk/Makefile
+++ b/board/freescale/imx8mp_evk/Makefile
@@ -8,5 +8,10 @@ obj-y += imx8mp_evk.o
 
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
+ifdef CONFIG_IMX8M_LPDDR4_FREQ0_3200MTS
+obj-y += lpddr4_timing_ndm.o
+else
 obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
+endif
 endif
diff --git a/board/freescale/imx8mp_evk/ddr4_timing.c b/board/freescale/imx8mp_evk/ddr4_timing.c
new file mode 100644
index 00000000000..3e3cc01bcca
--- /dev/null
+++ b/board/freescale/imx8mp_evk/ddr4_timing.c
@@ -0,0 +1,1311 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga
+ * For imx_v2019.04_5.4.x and above version:
+ * please replace #include <asm/arch/imx8m_ddr.h> with #include <asm/arch/ddr.h>
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0x81040010 },
+	{ 0x3d400030, 0xaa },
+	{ 0x3d400034, 0x221306 },
+	{ 0x3d400050, 0x210070 },
+	{ 0x3d400054, 0x10008 },
+	{ 0x3d400060, 0x0 },
+	{ 0x3d400064, 0xc30118 },
+	{ 0x3d4000c0, 0x0 },
+	{ 0x3d4000c4, 0x1000 },
+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
+	{ 0x3d400070, 0x1027f54 },
+#else
+	{ 0x3d400070, 0x1027f10 },
+#endif
+	{ 0x3d400074, 0x7b0 },
+	{ 0x3d4000d0, 0xc0030188 },
+	{ 0x3d4000d4, 0x9e0000 },
+	{ 0x3d4000dc, 0xc500501 },
+	{ 0x3d4000e0, 0x280400 },
+	{ 0x3d4000e4, 0x110000 },
+	{ 0x3d4000e8, 0x2000600 },
+	{ 0x3d4000ec, 0x1010 },
+	{ 0x3d4000f0, 0x20 },
+	{ 0x3d4000f4, 0xec7 },
+	{ 0x3d400100, 0x1618361a },
+	{ 0x3d400104, 0x50626 },
+	{ 0x3d400108, 0x80b0610 },
+	{ 0x3d40010c, 0x400c },
+	{ 0x3d400110, 0xc04060d },
+	{ 0x3d400114, 0x8080504 },
+	{ 0x3d40011c, 0x808 },
+	{ 0x3d400120, 0x6060d0a },
+	{ 0x3d400124, 0x2050c },
+	{ 0x3d40012c, 0x160b010e },
+	{ 0x3d400130, 0x8 },
+	{ 0x3d40013c, 0x0 },
+	{ 0x3d400180, 0x1000040 },
+	{ 0x3d400184, 0x61a8 },
+	{ 0x3d400190, 0x391820b },
+	{ 0x3d400194, 0x2020303 },
+	{ 0x3d400198, 0x7f04011 },
+	{ 0x3d40019c, 0xb0 },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0x48005a },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x1 },
+	{ 0x3d4001b4, 0x110b },
+	{ 0x3d4001b8, 0x4 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x0 },
+	{ 0x3d400200, 0x1f },
+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
+	{ 0x3d400204, 0x3f0505 },
+	{ 0x3d400208, 0x700 },
+	{ 0x3d40020c, 0x14141400 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400214, 0x4040403 },
+	{ 0x3d400218, 0x4040404 },
+	{ 0x3d40021c, 0xf04 },
+#else
+	{ 0x3d400204, 0x3f0909 },
+	{ 0x3d400208, 0x700 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf07 },
+#endif
+	{ 0x3d400220, 0x3f01 },
+	{ 0x3d400240, 0x6000618 },
+	{ 0x3d400244, 0x1323 },
+	{ 0x3d400250, 0x00001a05 },
+	{ 0x3d400254, 0x1f },
+	{ 0x3d40025c, 0x10000010 },
+	{ 0x3d400264, 0x100000ff },
+	{ 0x3d40026c, 0x100002ff },
+	{ 0x3d40036c, 0x0 },
+	{ 0x3d400400, 0x100 },
+	{ 0x3d400404, 0x72ff },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+	{ 0x3d402050, 0x210070 },
+	{ 0x3d402064, 0x40005e },
+	{ 0x3d4020dc, 0x40501 },
+	{ 0x3d4020e0, 0x0 },
+	{ 0x3d4020e8, 0x2000600 },
+	{ 0x3d4020ec, 0x10 },
+	{ 0x3d402100, 0xb081209 },
+	{ 0x3d402104, 0x2020d },
+	{ 0x3d402108, 0x5050309 },
+	{ 0x3d40210c, 0x400c },
+	{ 0x3d402110, 0x4030205 },
+	{ 0x3d402114, 0x3030202 },
+	{ 0x3d40211c, 0x303 },
+	{ 0x3d402120, 0x3030d04 },
+	{ 0x3d402124, 0x20208 },
+	{ 0x3d40212c, 0x1005010e },
+	{ 0x3d402130, 0x8 },
+	{ 0x3d40213c, 0x0 },
+	{ 0x3d402180, 0x1000040 },
+	{ 0x3d402190, 0x3858204 },
+	{ 0x3d402194, 0x2020303 },
+	{ 0x3d4021b4, 0x504 },
+	{ 0x3d4021b8, 0x4 },
+	{ 0x3d402240, 0x6000604 },
+	{ 0x3d4020f4, 0xec7 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x1005f, 0x2df },
+	{ 0x1015f, 0x2df },
+	{ 0x1105f, 0x2df },
+	{ 0x1115f, 0x2df },
+	{ 0x1205f, 0x2df },
+	{ 0x1215f, 0x2df },
+	{ 0x1305f, 0x2df },
+	{ 0x1315f, 0x2df },
+	{ 0x11005f, 0x2df },
+	{ 0x11015f, 0x2df },
+	{ 0x11105f, 0x2df },
+	{ 0x11115f, 0x2df },
+	{ 0x11205f, 0x2df },
+	{ 0x11215f, 0x2df },
+	{ 0x11305f, 0x2df },
+	{ 0x11315f, 0x2df },
+	{ 0x55, 0x355 },
+	{ 0x1055, 0x355 },
+	{ 0x2055, 0x355 },
+	{ 0x3055, 0x355 },
+	{ 0x4055, 0x55 },
+	{ 0x5055, 0x55 },
+	{ 0x6055, 0x355 },
+	{ 0x7055, 0x355 },
+	{ 0x8055, 0x355 },
+	{ 0x9055, 0x355 },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x6 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x1 },
+	{ 0x20024, 0x8 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x8 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x7 },
+	{ 0x120056, 0xa },
+	{ 0x1004d, 0x1a },
+	{ 0x1014d, 0x1a },
+	{ 0x1104d, 0x1a },
+	{ 0x1114d, 0x1a },
+	{ 0x1204d, 0x1a },
+	{ 0x1214d, 0x1a },
+	{ 0x1304d, 0x1a },
+	{ 0x1314d, 0x1a },
+	{ 0x11004d, 0x1a },
+	{ 0x11014d, 0x1a },
+	{ 0x11104d, 0x1a },
+	{ 0x11114d, 0x1a },
+	{ 0x11204d, 0x1a },
+	{ 0x11214d, 0x1a },
+	{ 0x11304d, 0x1a },
+	{ 0x11314d, 0x1a },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x43, 0xe7 },
+	{ 0x1043, 0xe7 },
+	{ 0x2043, 0xe7 },
+	{ 0x3043, 0xe7 },
+	{ 0x4043, 0xe7 },
+	{ 0x5043, 0xe7 },
+	{ 0x6043, 0xe7 },
+	{ 0x7043, 0xe7 },
+	{ 0x8043, 0xe7 },
+	{ 0x9043, 0xe7 },
+	{ 0x20018, 0x5 },
+	{ 0x20075, 0x2 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x320 },
+	{ 0x120008, 0x10a },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x248 },
+	{ 0x10043, 0x5b1 },
+	{ 0x10143, 0x5b1 },
+	{ 0x11043, 0x5b1 },
+	{ 0x11143, 0x5b1 },
+	{ 0x12043, 0x5b1 },
+	{ 0x12143, 0x5b1 },
+	{ 0x13043, 0x5b1 },
+	{ 0x13143, 0x5b1 },
+	{ 0x1200b2, 0x248 },
+	{ 0x110043, 0x5b1 },
+	{ 0x110143, 0x5b1 },
+	{ 0x111043, 0x5b1 },
+	{ 0x111143, 0x5b1 },
+	{ 0x112043, 0x5b1 },
+	{ 0x112143, 0x5b1 },
+	{ 0x113043, 0x5b1 },
+	{ 0x113143, 0x5b1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x20019, 0x5 },
+	{ 0x120019, 0x5 },
+	{ 0x200f0, 0x5555 },
+	{ 0x200f1, 0x5555 },
+	{ 0x200f2, 0x5555 },
+	{ 0x200f3, 0x5555 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0x5555 },
+	{ 0x200f6, 0x5555 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x1204a, 0x500 },
+	{ 0x1304a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2230 },
+	{ 0x54006, 0x25b },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x31f },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0xc50 },
+	{ 0x54030, 0x501 },
+	{ 0x54031, 0x28 },
+	{ 0x54032, 0x400 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x1010 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x1 },
+	{ 0x54003, 0x42a },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2230 },
+	{ 0x54006, 0x25b },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x21f },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x4 },
+	{ 0x54030, 0x501 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x10 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2230 },
+	{ 0x54006, 0x25b },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x101 },
+	{ 0x5400b, 0x61 },
+	{ 0x5400c, 0xc8 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400e, 0x1f7f },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0xc50 },
+	{ 0x54030, 0x501 },
+	{ 0x54031, 0x28 },
+	{ 0x54032, 0x400 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x600 },
+	{ 0x54035, 0x1010 },
+	{ 0x54036, 0x101 },
+	{ 0x5403f, 0x1221 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x2 },
+	{ 0x90033, 0x10 },
+	{ 0x90034, 0x139 },
+	{ 0x90035, 0xb },
+	{ 0x90036, 0x7c0 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0x44 },
+	{ 0x90039, 0x633 },
+	{ 0x9003a, 0x159 },
+	{ 0x9003b, 0x14f },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x47 },
+	{ 0x9003f, 0x633 },
+	{ 0x90040, 0x149 },
+	{ 0x90041, 0x4f },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x179 },
+	{ 0x90044, 0x8 },
+	{ 0x90045, 0xe0 },
+	{ 0x90046, 0x109 },
+	{ 0x90047, 0x0 },
+	{ 0x90048, 0x7c8 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x1 },
+	{ 0x9004c, 0x8 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x45a },
+	{ 0x9004f, 0x9 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x448 },
+	{ 0x90052, 0x109 },
+	{ 0x90053, 0x40 },
+	{ 0x90054, 0x633 },
+	{ 0x90055, 0x179 },
+	{ 0x90056, 0x1 },
+	{ 0x90057, 0x618 },
+	{ 0x90058, 0x109 },
+	{ 0x90059, 0x40c0 },
+	{ 0x9005a, 0x633 },
+	{ 0x9005b, 0x149 },
+	{ 0x9005c, 0x8 },
+	{ 0x9005d, 0x4 },
+	{ 0x9005e, 0x48 },
+	{ 0x9005f, 0x4040 },
+	{ 0x90060, 0x633 },
+	{ 0x90061, 0x149 },
+	{ 0x90062, 0x0 },
+	{ 0x90063, 0x4 },
+	{ 0x90064, 0x48 },
+	{ 0x90065, 0x40 },
+	{ 0x90066, 0x633 },
+	{ 0x90067, 0x149 },
+	{ 0x90068, 0x10 },
+	{ 0x90069, 0x4 },
+	{ 0x9006a, 0x18 },
+	{ 0x9006b, 0x0 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x78 },
+	{ 0x9006e, 0x549 },
+	{ 0x9006f, 0x633 },
+	{ 0x90070, 0x159 },
+	{ 0x90071, 0xd49 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0x94a },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x441 },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x149 },
+	{ 0x9007a, 0x42 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x1 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x0 },
+	{ 0x90081, 0xe0 },
+	{ 0x90082, 0x109 },
+	{ 0x90083, 0xa },
+	{ 0x90084, 0x10 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0x9 },
+	{ 0x90087, 0x3c0 },
+	{ 0x90088, 0x149 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x159 },
+	{ 0x9008c, 0x18 },
+	{ 0x9008d, 0x10 },
+	{ 0x9008e, 0x109 },
+	{ 0x9008f, 0x0 },
+	{ 0x90090, 0x3c0 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x18 },
+	{ 0x90093, 0x4 },
+	{ 0x90094, 0x48 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x58 },
+	{ 0x90098, 0xb },
+	{ 0x90099, 0x10 },
+	{ 0x9009a, 0x109 },
+	{ 0x9009b, 0x1 },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x5 },
+	{ 0x9009f, 0x7c0 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x0 },
+	{ 0x900a2, 0x8140 },
+	{ 0x900a3, 0x10c },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x8138 },
+	{ 0x900a6, 0x104 },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x448 },
+	{ 0x900a9, 0x109 },
+	{ 0x900aa, 0xf },
+	{ 0x900ab, 0x7c0 },
+	{ 0x900ac, 0x109 },
+	{ 0x900ad, 0x47 },
+	{ 0x900ae, 0x630 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x8 },
+	{ 0x900b1, 0x618 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x8 },
+	{ 0x900b4, 0xe0 },
+	{ 0x900b5, 0x109 },
+	{ 0x900b6, 0x0 },
+	{ 0x900b7, 0x7c8 },
+	{ 0x900b8, 0x109 },
+	{ 0x900b9, 0x8 },
+	{ 0x900ba, 0x8140 },
+	{ 0x900bb, 0x10c },
+	{ 0x900bc, 0x0 },
+	{ 0x900bd, 0x478 },
+	{ 0x900be, 0x109 },
+	{ 0x900bf, 0x0 },
+	{ 0x900c0, 0x1 },
+	{ 0x900c1, 0x8 },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x0 },
+	{ 0x90006, 0x8 },
+	{ 0x90007, 0x7c8 },
+	{ 0x90008, 0x109 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x400 },
+	{ 0x9000b, 0x106 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x90026, 0x2a },
+	{ 0x2000b, 0x64 },
+	{ 0x2000c, 0xc8 },
+	{ 0x2000d, 0x7d0 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x21 },
+	{ 0x12000c, 0x42 },
+	{ 0x12000d, 0x29a },
+	{ 0x12000e, 0x21 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0xffff },
+	{ 0x90013, 0x6152 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x0 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 1066mts 1D */
+		.drate = 1066,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3200, 1066, },
+};
+
+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
+void board_dram_ecc_scrub(void)
+{
+	ddrc_inline_ecc_scrub(0x0,0x7ffffff);
+	ddrc_inline_ecc_scrub(0x8000000,0xfffffff);
+	ddrc_inline_ecc_scrub(0x10000000,0x17ffffff);
+	ddrc_inline_ecc_scrub(0x18000000,0x1fffffff);
+	ddrc_inline_ecc_scrub(0x20000000,0x27ffffff);
+	ddrc_inline_ecc_scrub(0x28000000,0x2fffffff);
+	ddrc_inline_ecc_scrub(0x30000000,0x37ffffff);
+	ddrc_inline_ecc_scrub_end(0x0,0x3fffffff);
+}
+#endif
diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c
index 62096c24fb7..346ea167445 100644
--- a/board/freescale/imx8mp_evk/imx8mp_evk.c
+++ b/board/freescale/imx8mp_evk/imx8mp_evk.c
@@ -11,12 +11,23 @@
 #include <netdev.h>
 #include <linux/delay.h>
 #include <asm/global_data.h>
+#include <asm/io.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm-generic/gpio.h>
 #include <asm/arch/imx8mp_pins.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <spl.h>
+#include <asm/mach-imx/dma.h>
+#include <power/pmic.h>
+#include "../common/tcpc.h"
+#include <usb.h>
+#include <dwc3-uboot.h>
+#include <imx_sip.h>
+#include <linux/arm-smccc.h>
+#include <mmc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -32,6 +43,14 @@ static iomux_v3_cfg_t const wdog_pads[] = {
 	MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 };
 
+#ifdef CONFIG_NAND_MXS
+
+static void setup_gpmi_nand(void)
+{
+	init_nand_clk();
+}
+#endif
+
 int board_early_init_f(void)
 {
 	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
@@ -42,9 +61,344 @@ int board_early_init_f(void)
 
 	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 
+	init_uart_clk(1);
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
+#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK
+	int rc;
+	phys_addr_t ecc_start = 0x120000000;
+	size_t ecc_size = 0x20000000;
+
+	rc = add_res_mem_dt_node(blob, "ecc", ecc_start, ecc_size);
+	if (rc < 0) {
+		printf("Could not create ecc reserved-memory node.\n");
+		return rc;
+	}
+#else
+	int rc;
+	phys_addr_t ecc0_start = 0xb0000000;
+	phys_addr_t ecc1_start = 0x130000000;
+	phys_addr_t ecc2_start = 0x1b0000000;
+	size_t ecc_size = 0x10000000;
+
+	rc = add_res_mem_dt_node(blob, "ecc", ecc0_start, ecc_size);
+	if (rc < 0) {
+		printf("Could not create ecc0 reserved-memory node.\n");
+		return rc;
+	}
+
+	rc = add_res_mem_dt_node(blob, "ecc", ecc1_start, ecc_size);
+	if (rc < 0) {
+		printf("Could not create ecc1 reserved-memory node.\n");
+		return rc;
+	}
+
+	rc = add_res_mem_dt_node(blob, "ecc", ecc2_start, ecc_size);
+	if (rc < 0) {
+		printf("Could not create ecc2 reserved-memory node.\n");
+		return rc;
+	}
+#endif
+#endif
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_TCPC
+struct tcpc_port port1;
+struct tcpc_port port2;
+
+static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr)
+{
+	struct udevice *bus;
+	struct udevice *i2c_dev = NULL;
+	int ret;
+	uint8_t valb;
+
+	ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus);
+	if (ret) {
+		printf("%s: Can't find bus\n", __func__);
+		return -EINVAL;
+	}
+
+	ret = dm_i2c_probe(bus, addr, 0, &i2c_dev);
+	if (ret) {
+		printf("%s: Can't find device id=0x%x\n",
+			__func__, addr);
+		return -ENODEV;
+	}
+
+	ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_read failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+	valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */
+	ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+
+	/* Set OVP threshold to 23V */
+	valb = 0x6;
+	ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+int pd_switch_snk_enable(struct tcpc_port *port)
+{
+	if (port == &port1) {
+		debug("Setup pd switch on port 1\n");
+		return setup_pd_switch(1, 0x72);
+	} else
+		return -EINVAL;
+}
+
+/* Port2 is the power supply, port 1 does not support power */
+struct tcpc_port_config port1_config = {
+	.i2c_bus = 1, /*i2c2*/
+	.addr = 0x50,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 20000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 45000,
+	.op_snk_mv = 15000,
+	.switch_setup_func = &pd_switch_snk_enable,
+	.disable_pd = true,
+};
+
+struct tcpc_port_config port2_config = {
+	.i2c_bus = 2, /*i2c3*/
+	.addr = 0x50,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 20000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 45000,
+	.op_snk_mv = 15000,
+};
+
+#define USB_TYPEC_SEL IMX_GPIO_NR(4, 20)
+#define USB_TYPEC_EN IMX_GPIO_NR(2, 20)
+
+static iomux_v3_cfg_t ss_mux_gpio[] = {
+	MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX8MP_PAD_SD2_WP__GPIO2_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void ss_mux_select(enum typec_cc_polarity pol)
+{
+	if (pol == TYPEC_POLARITY_CC1)
+		gpio_direction_output(USB_TYPEC_SEL, 0);
+	else
+		gpio_direction_output(USB_TYPEC_SEL, 1);
+}
+
+static int setup_typec(void)
+{
+	int ret;
+	struct gpio_desc per_12v_desc;
+
+	debug("tcpc_init port 2\n");
+	ret = tcpc_init(&port2, port2_config, NULL);
+	if (ret) {
+		printf("%s: tcpc port2 init failed, err=%d\n",
+		       __func__, ret);
+	} else if (tcpc_pd_sink_check_charging(&port2)) {
+		printf("Power supply on USB2\n");
+
+		/* Enable PER 12V, any check before it? */
+		ret = dm_gpio_lookup_name("gpio@20_1", &per_12v_desc);
+		if (ret) {
+			printf("%s lookup gpio@20_1 failed ret = %d\n", __func__, ret);
+			return -ENODEV;
+		}
+
+		ret = dm_gpio_request(&per_12v_desc, "per_12v_en");
+		if (ret) {
+			printf("%s request per_12v failed ret = %d\n", __func__, ret);
+			return -EIO;
+		}
+
+		/* Enable PER 12V regulator */
+		dm_gpio_set_dir_flags(&per_12v_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+	}
+
+	debug("tcpc_init port 1\n");
+	imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
+	gpio_request(USB_TYPEC_SEL, "typec_sel");
+	gpio_request(USB_TYPEC_EN, "typec_en");
+	gpio_direction_output(USB_TYPEC_EN, 0);
+
+	ret = tcpc_init(&port1, port1_config, &ss_mux_select);
+	if (ret) {
+		printf("%s: tcpc port1 init failed, err=%d\n",
+		       __func__, ret);
+	} else {
+		return ret;
+	}
+
+	return ret;
+}
+#endif
+
+#ifdef CONFIG_USB_DWC3
+
+#define USB_PHY_CTRL0			0xF0040
+#define USB_PHY_CTRL0_REF_SSP_EN	BIT(2)
+
+#define USB_PHY_CTRL1			0xF0044
+#define USB_PHY_CTRL1_RESET		BIT(0)
+#define USB_PHY_CTRL1_COMMONONN		BIT(1)
+#define USB_PHY_CTRL1_ATERESET		BIT(3)
+#define USB_PHY_CTRL1_VDATSRCENB0	BIT(19)
+#define USB_PHY_CTRL1_VDATDETENB0	BIT(20)
+
+#define USB_PHY_CTRL2			0xF0048
+#define USB_PHY_CTRL2_TXENABLEN0	BIT(8)
+
+#define USB_PHY_CTRL6			0xF0058
+
+#define HSIO_GPR_BASE                               (0x32F10000U)
+#define HSIO_GPR_REG_0                              (HSIO_GPR_BASE)
+#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT    (1)
+#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN          (0x1U << HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT)
+
+
+static struct dwc3_device dwc3_device_data = {
+#ifdef CONFIG_SPL_BUILD
+	.maximum_speed = USB_SPEED_HIGH,
+#else
+	.maximum_speed = USB_SPEED_SUPER,
+#endif
+	.base = USB1_BASE_ADDR,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 0,
+	.power_down_scale = 2,
+};
+
+int usb_gadget_handle_interrupts(int index)
+{
+	dwc3_uboot_handle_interrupt(index);
+	return 0;
+}
+
+static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
+{
+	u32 RegData;
+
+	/* enable usb clock via hsio gpr */
+	RegData = readl(HSIO_GPR_REG_0);
+	RegData |= HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN;
+	writel(RegData, HSIO_GPR_REG_0);
+
+	/* USB3.0 PHY signal fsel for 100M ref */
+	RegData = readl(dwc3->base + USB_PHY_CTRL0);
+	RegData = (RegData & 0xfffff81f) | (0x2a<<5);
+	writel(RegData, dwc3->base + USB_PHY_CTRL0);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL6);
+	RegData &=~0x1;
+	writel(RegData, dwc3->base + USB_PHY_CTRL6);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL1);
+	RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
+			USB_PHY_CTRL1_COMMONONN);
+	RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
+	writel(RegData, dwc3->base + USB_PHY_CTRL1);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL0);
+	RegData |= USB_PHY_CTRL0_REF_SSP_EN;
+	writel(RegData, dwc3->base + USB_PHY_CTRL0);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL2);
+	RegData |= USB_PHY_CTRL2_TXENABLEN0;
+	writel(RegData, dwc3->base + USB_PHY_CTRL2);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL1);
+	RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
+	writel(RegData, dwc3->base + USB_PHY_CTRL1);
+}
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+#define USB2_PWR_EN IMX_GPIO_NR(1, 14)
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int ret = 0;
+	imx8m_usb_power(index, true);
+
+	if (index == 0 && init == USB_INIT_DEVICE) {
+#ifdef CONFIG_USB_TCPC
+		ret = tcpc_setup_ufp_mode(&port1);
+		if (ret)
+			return ret;
+#endif
+		dwc3_nxp_usb_phy_init(&dwc3_device_data);
+		return dwc3_uboot_init(&dwc3_device_data);
+	} else if (index == 0 && init == USB_INIT_HOST) {
+#ifdef CONFIG_USB_TCPC
+		ret = tcpc_setup_dfp_mode(&port1);
+#endif
+		return ret;
+	}
+
 	return 0;
 }
 
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	int ret = 0;
+	if (index == 0 && init == USB_INIT_DEVICE) {
+		dwc3_uboot_exit(index);
+	} else if (index == 0 && init == USB_INIT_HOST) {
+#ifdef CONFIG_USB_TCPC
+		ret = tcpc_disable_src_vbus(&port1);
+#endif
+	}
+
+	imx8m_usb_power(index, false);
+
+	return ret;
+}
+
+#ifdef CONFIG_USB_TCPC
+/* Not used so far */
+int board_typec_get_mode(int index)
+{
+	int ret = 0;
+	enum typec_cc_polarity pol;
+	enum typec_cc_state state;
+
+	if (index == 0) {
+		tcpc_setup_ufp_mode(&port1);
+
+		ret = tcpc_get_cc_status(&port1, &pol, &state);
+		if (!ret) {
+			if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD)
+				return USB_INIT_HOST;
+		}
+
+		return USB_INIT_DEVICE;
+	} else {
+		return USB_INIT_HOST;
+	}
+}
+#endif
+#endif
+
 static void setup_fec(void)
 {
 	struct iomuxc_gpr_base_regs *gpr =
@@ -76,23 +430,51 @@ int board_phy_config(struct phy_device *phydev)
 }
 #endif
 
+#define DISPMIX				13
+#define MIPI				15
+
 int board_init(void)
 {
-	int ret = 0;
+	struct arm_smccc_res res;
+
+#ifdef CONFIG_USB_TCPC
+	setup_typec();
+
+	/* Enable USB power default */
+	imx8m_usb_power(0, true);
+	imx8m_usb_power(1, true);
+#endif
 
 	if (CONFIG_IS_ENABLED(FEC_MXC)) {
 		setup_fec();
 	}
 
 	if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) {
-		ret = setup_eqos();
+		setup_eqos();
 	}
 
-	return ret;
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+	init_usb_clk();
+#endif
+
+	/* enable the dispmix & mipi phy power domain */
+	arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN,
+		      DISPMIX, true, 0, 0, 0, 0, &res);
+	arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN,
+		      MIPI, true, 0, 0, 0, 0, &res);
+
+	return 0;
 }
 
 int board_late_init(void)
 {
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	env_set("board_name", "EVK");
 	env_set("board_rev", "iMX8MP");
@@ -100,3 +482,32 @@ int board_late_init(void)
 
 	return 0;
 }
+
+#ifdef CONFIG_ANDROID_SUPPORT
+bool is_power_key_pressed(void) {
+	return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6)));
+}
+#endif
+
+#ifdef CONFIG_SPL_MMC
+#define UBOOT_RAW_SECTOR_OFFSET 0x40
+unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc)
+{
+	u32 boot_dev = spl_boot_device();
+	switch (boot_dev) {
+		case BOOT_DEVICE_MMC2:
+			return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET;
+		default:
+			return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
+	}
+}
+#endif
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+int is_recovery_key_pressing(void)
+{
+	return 0; /* TODO */
+}
+#endif /* CONFIG_ANDROID_RECOVERY */
+#endif /* CONFIG_FSL_FASTBOOT */
diff --git a/board/freescale/imx8mp_evk/lpddr4_timing_ndm.c b/board/freescale/imx8mp_evk/lpddr4_timing_ndm.c
new file mode 100644
index 00000000000..4765618afde
--- /dev/null
+++ b/board/freescale/imx8mp_evk/lpddr4_timing_ndm.c
@@ -0,0 +1,1853 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2019.04_5.4.x and above version
+ * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga:
+ * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h>
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa3080020 },
+	{ 0x3d400020, 0x1223 },
+	{ 0x3d400024, 0x186a000 },
+	{ 0x3d400064, 0x610130 },
+	{ 0x3d400070, 0x1027f10 },
+	{ 0x3d400074, 0x7b0 },
+	{ 0x3d4000d0, 0xc003061c },
+	{ 0x3d4000d4, 0x9e0000 },
+	{ 0x3d4000dc, 0xd4002d },
+	{ 0x3d4000e0, 0x330000 },
+	{ 0x3d4000e8, 0x660048 },
+	{ 0x3d4000ec, 0x160048 },
+	{ 0x3d400100, 0x1a201b22 },
+	{ 0x3d400104, 0x60633 },
+	{ 0x3d40010c, 0xc0c000 },
+	{ 0x3d400110, 0xf04080f },
+	{ 0x3d400114, 0x2040c0c },
+	{ 0x3d400118, 0x1010007 },
+	{ 0x3d40011c, 0x401 },
+	{ 0x3d400130, 0x20600 },
+	{ 0x3d400134, 0xe100002 },
+	{ 0x3d400138, 0x136 },
+	{ 0x3d400144, 0xa00050 },
+	{ 0x3d400180, 0x3200018 },
+	{ 0x3d400184, 0x28061a8 },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x497820a },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001b4, 0x170a },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0xc99 },
+	{ 0x3d400108, 0x70e1617 },
+	{ 0x3d400200, 0x16 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x68070707 },
+	{ 0x3d40021c, 0xf08 },
+	{ 0x3d400250, 0x1705 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x4000030 },
+	{ 0x3d400264, 0x900093e7 },
+	{ 0x3d40026c, 0x2005574 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400404, 0x72ff },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400494, 0x2100e07 },
+	{ 0x3d400498, 0x620096 },
+	{ 0x3d40049c, 0x1100e07 },
+	{ 0x3d4004a0, 0xc8012c },
+	{ 0x3d402020, 0x1021 },
+	{ 0x3d402024, 0x30d400 },
+	{ 0x3d402050, 0x20d000 },
+	{ 0x3d402064, 0xc0026 },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x330000 },
+	{ 0x3d4020e8, 0x660048 },
+	{ 0x3d4020ec, 0x160048 },
+	{ 0x3d402100, 0xa040305 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x27 },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0x640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d4020f4, 0xc99 },
+	{ 0x3d403020, 0x1021 },
+	{ 0x3d403024, 0xc3500 },
+	{ 0x3d403050, 0x20d000 },
+	{ 0x3d403064, 0x3000a },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x330000 },
+	{ 0x3d4030e8, 0x660048 },
+	{ 0x3d4030ec, 0x160048 },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x301 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0xa },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0x190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+	{ 0x3d4030f4, 0xc99 },
+	{ 0x3d400028, 0x0 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x3 },
+	{ 0x110a3, 0x4 },
+	{ 0x110a4, 0x5 },
+	{ 0x110a5, 0x2 },
+	{ 0x110a6, 0x7 },
+	{ 0x110a7, 0x6 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x3 },
+	{ 0x120a3, 0x2 },
+	{ 0x120a4, 0x5 },
+	{ 0x120a5, 0x4 },
+	{ 0x120a6, 0x7 },
+	{ 0x120a7, 0x6 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x2 },
+	{ 0x130a3, 0x3 },
+	{ 0x130a4, 0x4 },
+	{ 0x130a5, 0x5 },
+	{ 0x130a6, 0x6 },
+	{ 0x130a7, 0x7 },
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x20024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x220024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x212049, 0xeba },
+	{ 0x212149, 0xeba },
+	{ 0x213049, 0xeba },
+	{ 0x213149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x320 },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x104 },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+	{ 0x1200b2, 0x104 },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+	{ 0x2200b2, 0x104 },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x2007d, 0x212 },
+	{ 0x12007d, 0x212 },
+	{ 0x22007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x12007c, 0x61 },
+	{ 0x22007c, 0x61 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x1204a, 0x500 },
+	{ 0x1304a, 0x500 },
+	{ 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x332d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x332d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3300 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3300 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, 0x3300 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, 0x3300 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xc80 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x14 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x310 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x33 },
+	{ 0x5401b, 0x4866 },
+	{ 0x5401c, 0x4800 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x33 },
+	{ 0x54021, 0x4866 },
+	{ 0x54022, 0x4800 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, 0x3 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x332d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x48 },
+	{ 0x54036, 0x48 },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x332d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x48 },
+	{ 0x5403c, 0x48 },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xb },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x633 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x633 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x633 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x633 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x633 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x633 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x633 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x633 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x633 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xb },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x1 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x625 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x625 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a4, 0x0 },
+	{ 0x900a5, 0x790 },
+	{ 0x900a6, 0x11a },
+	{ 0x900a7, 0x8 },
+	{ 0x900a8, 0x7aa },
+	{ 0x900a9, 0x2a },
+	{ 0x900aa, 0x10 },
+	{ 0x900ab, 0x7b2 },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x0 },
+	{ 0x900ae, 0x7c8 },
+	{ 0x900af, 0x109 },
+	{ 0x900b0, 0x10 },
+	{ 0x900b1, 0x10 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x1 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xd },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x8 },
+	{ 0x90159, 0xe8 },
+	{ 0x9015a, 0x109 },
+	{ 0x9015b, 0x0 },
+	{ 0x9015c, 0x8140 },
+	{ 0x9015d, 0x10c },
+	{ 0x9015e, 0x10 },
+	{ 0x9015f, 0x8138 },
+	{ 0x90160, 0x104 },
+	{ 0x90161, 0x8 },
+	{ 0x90162, 0x448 },
+	{ 0x90163, 0x109 },
+	{ 0x90164, 0xf },
+	{ 0x90165, 0x7c0 },
+	{ 0x90166, 0x109 },
+	{ 0x90167, 0x0 },
+	{ 0x90168, 0xe8 },
+	{ 0x90169, 0x109 },
+	{ 0x9016a, 0x47 },
+	{ 0x9016b, 0x630 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0x8 },
+	{ 0x9016e, 0x618 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x8 },
+	{ 0x90171, 0xe0 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x0 },
+	{ 0x90174, 0x7c8 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x8140 },
+	{ 0x90178, 0x10c },
+	{ 0x90179, 0x0 },
+	{ 0x9017a, 0x478 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x1 },
+	{ 0x9017e, 0x8 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x4 },
+	{ 0x90181, 0x0 },
+	{ 0x90006, 0x8 },
+	{ 0x90007, 0x7c8 },
+	{ 0x90008, 0x109 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x400 },
+	{ 0x9000b, 0x106 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x29 },
+	{ 0x90026, 0x68 },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x200be, 0x3 },
+	{ 0x2000b, 0x64 },
+	{ 0x2000c, 0xc8 },
+	{ 0x2000d, 0x7d0 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x2060 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3200, 400, 100, },
+};
diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c
index eca42c756e4..913e2868b98 100644
--- a/board/freescale/imx8mp_evk/spl.c
+++ b/board/freescale/imx8mp_evk/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
 /*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2019, 2021 NXP
  *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -10,22 +10,50 @@
 #include <log.h>
 #include <spl.h>
 #include <asm/global_data.h>
-#include <asm/arch/clock.h>
 #include <asm/arch/imx8mp_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/boot_mode.h>
+#include <power/pmic.h>
+
+#include <power/pca9450.h>
+#include <asm/arch/clock.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
 #include <asm/mach-imx/gpio.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
 #include <asm/arch/ddr.h>
-#include <power/pmic.h>
-#include <power/pca9450.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int spl_board_boot_device(enum boot_device boot_dev_spl)
 {
+#ifdef CONFIG_SPL_BOOTROM_SUPPORT
 	return BOOT_DEVICE_BOOTROM;
+#else
+	switch (boot_dev_spl) {
+	case SD1_BOOT:
+	case MMC1_BOOT:
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD3_BOOT:
+	case MMC3_BOOT:
+		return BOOT_DEVICE_MMC2;
+	case QSPI_BOOT:
+		return BOOT_DEVICE_NOR;
+	case NAND_BOOT:
+		return BOOT_DEVICE_NAND;
+	case USB_BOOT:
+		return BOOT_DEVICE_BOARD;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+#endif
 }
 
 void spl_dram_init(void)
@@ -35,50 +63,47 @@ void spl_dram_init(void)
 
 void spl_board_init(void)
 {
+	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+		struct udevice *dev;
+		int ret;
+
+		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+		if (ret)
+			printf("Failed to initialize caam_jr: %d\n", ret);
+	}
 	/*
 	 * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
 	 * not allow to change it. Should set the clock after PMIC
 	 * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
 	 * set by ROM for ND VDD_SOC
 	 */
+#if defined(CONFIG_IMX8M_LPDDR4) && !defined(CONFIG_IMX8M_VDD_SOC_850MV)
 	clock_enable(CCGR_GIC, 0);
 	clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
 	clock_enable(CCGR_GIC, 1);
 
 	puts("Normal Boot\n");
+#endif
 }
 
-#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
-		.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
-		.gp = IMX_GPIO_NR(5, 14),
-	},
-	.sda = {
-		.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
-		.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
-		.gp = IMX_GPIO_NR(5, 15),
-	},
-};
-
-#if CONFIG_IS_ENABLED(POWER_LEGACY)
-#define I2C_PMIC	0
+#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
 int power_init_board(void)
 {
-	struct pmic *p;
+	struct udevice *dev;
 	int ret;
 
-	ret = power_pca9450_init(I2C_PMIC, 0x25);
-	if (ret)
-		printf("power init failed");
-	p = pmic_get("PCA9450");
-	pmic_probe(p);
+	ret = pmic_get("pca9450@25", &dev);
+	if (ret == -ENODEV) {
+		puts("No pca9450@25\n");
+		return 0;
+	}
+	if (ret != 0)
+		return ret;
 
 	/* BUCKxOUT_DVS0/1 control BUCK123 output */
-	pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
+	pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
 
+#ifdef CONFIG_IMX8M_LPDDR4
 	/*
 	 * increase VDD_SOC to typical value 0.95V before first
 	 * DRAM access, set DVS1 to 0.85v for suspend.
@@ -87,19 +112,26 @@ int power_init_board(void)
 	 */
 #ifdef CONFIG_IMX8M_VDD_SOC_850MV
 	/* set DVS0 to 0.85v for special case*/
-	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
 #else
-	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
 #endif
-	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
-	pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
+	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
 
 	/* Kernel uses OD/OD freq for SOC */
 	/* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
-	pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
+	pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
+#elif defined(CONFIG_IMX8M_DDR4)
+	/* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */
+	pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
+
+	/* Set NVCC_DRAM to 1.2v for DDR4 */
+	pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x18);
+#endif
 
 	/* set WDOG_B_CFG to cold reset */
-	pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
+	pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
 
 	return 0;
 }
@@ -115,31 +147,42 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
-/* Do not use BSS area in this phase */
 void board_init_f(ulong dummy)
 {
+	struct udevice *dev;
 	int ret;
 
-	arch_cpu_init();
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
 
-	init_uart_clk(1);
+	arch_cpu_init();
 
 	board_early_init_f();
 
+	timer_init();
+
+	preloader_console_init();
+
 	ret = spl_early_init();
 	if (ret) {
-		debug("spl_init() failed: %d\n", ret);
+		debug("spl_early_init() failed: %d\n", ret);
 		hang();
 	}
 
-	preloader_console_init();
+	ret = uclass_get_device_by_name(UCLASS_CLK,
+					"clock-controller@30380000",
+					&dev);
+	if (ret < 0) {
+		printf("Failed to find clock node. Check device tree\n");
+		hang();
+	}
 
 	enable_tzc380();
 
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-
 	power_init_board();
 
 	/* DDR initialization */
 	spl_dram_init();
+
+	board_init_r(NULL, 0);
 }
diff --git a/board/freescale/imx8mq_evk/Kconfig b/board/freescale/imx8mq_evk/Kconfig
index c4d20ad7c7d..0b481040490 100644
--- a/board/freescale/imx8mq_evk/Kconfig
+++ b/board/freescale/imx8mq_evk/Kconfig
@@ -12,4 +12,6 @@ config SYS_CONFIG_NAME
 config IMX_CONFIG
 	default "arch/arm/mach-imx/imx8m/imximage.cfg"
 
+source "board/freescale/common/Kconfig"
+
 endif
diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c
index e3948058560..81a961883f1 100644
--- a/board/freescale/imx8mq_evk/imx8mq_evk.c
+++ b/board/freescale/imx8mq_evk/imx8mq_evk.c
@@ -25,7 +25,10 @@
 #include <linux/bitops.h>
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
+#include "../common/tcpc.h"
 #include "../common/pfuze.h"
+#include <usb.h>
+#include <dwc3-uboot.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -54,6 +57,15 @@ int board_early_init_f(void)
 	return 0;
 }
 
+#ifdef CONFIG_FSL_QSPI
+int board_qspi_init(void)
+{
+	set_clk_qspi();
+
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_FEC_MXC
 static int setup_fec(void)
 {
@@ -61,43 +73,199 @@ static int setup_fec(void)
 		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
 
 	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
-	clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
+	clrsetbits_le32(&gpr->gpr[1],
+		IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0);
 	return set_clk_enet(ENET_125MHZ);
 }
 
 int board_phy_config(struct phy_device *phydev)
 {
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+#ifndef CONFIG_DM_ETH
 	/* enable rgmii rxc skew and phy mode select to RGMII copper */
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
 
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+#endif
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_DWC3
+
+#define USB_PHY_CTRL0			0xF0040
+#define USB_PHY_CTRL0_REF_SSP_EN	BIT(2)
+
+#define USB_PHY_CTRL1			0xF0044
+#define USB_PHY_CTRL1_RESET		BIT(0)
+#define USB_PHY_CTRL1_COMMONONN		BIT(1)
+#define USB_PHY_CTRL1_ATERESET		BIT(3)
+#define USB_PHY_CTRL1_VDATSRCENB0	BIT(19)
+#define USB_PHY_CTRL1_VDATDETENB0	BIT(20)
+
+#define USB_PHY_CTRL2			0xF0048
+#define USB_PHY_CTRL2_TXENABLEN0	BIT(8)
+
+static struct dwc3_device dwc3_device_data = {
+#ifdef CONFIG_SPL_BUILD
+	.maximum_speed = USB_SPEED_HIGH,
+#else
+	.maximum_speed = USB_SPEED_SUPER,
+#endif
+	.base = USB1_BASE_ADDR,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 0,
+	.power_down_scale = 2,
+};
+
+int usb_gadget_handle_interrupts(int index)
+{
+	dwc3_uboot_handle_interrupt(index);
+	return 0;
+}
+
+static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
+{
+	u32 RegData;
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL1);
+	RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
+			USB_PHY_CTRL1_COMMONONN);
+	RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
+	writel(RegData, dwc3->base + USB_PHY_CTRL1);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL0);
+	RegData |= USB_PHY_CTRL0_REF_SSP_EN;
+	writel(RegData, dwc3->base + USB_PHY_CTRL0);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL2);
+	RegData |= USB_PHY_CTRL2_TXENABLEN0;
+	writel(RegData, dwc3->base + USB_PHY_CTRL2);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL1);
+	RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
+	writel(RegData, dwc3->base + USB_PHY_CTRL1);
+}
+#endif
+
+#ifdef CONFIG_USB_TCPC
+struct tcpc_port port;
+struct tcpc_port_config port_config = {
+	.i2c_bus = 0,
+	.addr = 0x50,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 20000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 15000,
+	.op_snk_mv = 9000,
+};
+
+struct gpio_desc type_sel_desc;
+static iomux_v3_cfg_t ss_mux_gpio[] = {
+	IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void ss_mux_select(enum typec_cc_polarity pol)
+{
+	if (pol == TYPEC_POLARITY_CC1)
+		dm_gpio_set_value(&type_sel_desc, 1);
+	else
+		dm_gpio_set_value(&type_sel_desc, 0);
+}
+
+static int setup_typec(void)
+{
+	int ret;
+
+	imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
+
+	ret = dm_gpio_lookup_name("GPIO3_15", &type_sel_desc);
+	if (ret) {
+		printf("%s lookup GPIO3_15 failed ret = %d\n", __func__, ret);
+		return -ENODEV;
+	}
+
+	ret = dm_gpio_request(&type_sel_desc, "typec_sel");
+	if (ret) {
+		printf("%s request typec_sel failed ret = %d\n", __func__, ret);
+		return -ENODEV;
+	}
+
+	dm_gpio_set_dir_flags(&type_sel_desc, GPIOD_IS_OUT);
+
+	ret = tcpc_init(&port, port_config, &ss_mux_select);
+	if (ret) {
+		printf("%s: tcpc init failed, err=%d\n",
+		       __func__, ret);
+	}
+
+	return ret;
+}
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	if (index == 0 && init == USB_INIT_DEVICE) {
+		imx8m_usb_power(index, true);
+#ifdef CONFIG_USB_TCPC
+		ret = tcpc_setup_ufp_mode(&port);
+#endif
+		dwc3_nxp_usb_phy_init(&dwc3_device_data);
+		return dwc3_uboot_init(&dwc3_device_data);
+	} else if (index == 0 && init == USB_INIT_HOST) {
+#ifdef CONFIG_USB_TCPC
+		ret = tcpc_setup_dfp_mode(&port);
+#endif
+		return ret;
+	}
 
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
 	return 0;
 }
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	int ret = 0;
+	if (index == 0 && init == USB_INIT_DEVICE) {
+		dwc3_uboot_exit(index);
+		imx8m_usb_power(index, false);
+	} else if (index == 0 && init == USB_INIT_HOST) {
+#ifdef CONFIG_USB_TCPC
+		ret = tcpc_disable_src_vbus(&port);
+#endif
+	}
+
+	return ret;
+}
 #endif
 
 int board_init(void)
 {
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
 #ifdef CONFIG_FEC_MXC
 	setup_fec();
 #endif
 
-#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3)
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
 	init_usb_clk();
 #endif
 
+#ifdef CONFIG_USB_TCPC
+	setup_typec();
+#endif
 	return 0;
 }
 
-int board_mmc_get_env_dev(int devno)
-{
-	return devno;
-}
-
 int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
@@ -105,5 +273,24 @@ int board_late_init(void)
 	env_set("board_rev", "iMX8MQ");
 #endif
 
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
 	return 0;
 }
+
+#ifdef CONFIG_ANDROID_SUPPORT
+bool is_power_key_pressed(void) {
+	return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6)));
+}
+#endif
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+int is_recovery_key_pressing(void)
+{
+	return 0; /* TODO */
+}
+#endif /* CONFIG_ANDROID_RECOVERY */
+#endif /* CONFIG_FSL_FASTBOOT */
diff --git a/board/freescale/imx8mq_evk/lpddr4_timing.c b/board/freescale/imx8mq_evk/lpddr4_timing.c
index 46bc7f8591c..1dccc07fb92 100644
--- a/board/freescale/imx8mq_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mq_evk/lpddr4_timing.c
@@ -1,148 +1,168 @@
-// SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2019.04_5.4.x and above version
+ * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga:
+ * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h>
  */
 
 #include <linux/kernel.h>
-#include <common.h>
 #include <asm/arch/ddr.h>
-#include <asm/arch/lpddr4_define.h>
 
-#define WR_POST_EXT_3200	/* recommened to define */
-
-struct dram_cfg_param lpddr4_ddrc_cfg[] = {
-	/* Start to config, default 3200mbps */
-	{ DDRC_DBG1(0), 0x00000001 },
-	{ DDRC_PWRCTL(0), 0x00000001 },
-	{ DDRC_MSTR(0), 0xa3080020 },
-	{ DDRC_MSTR2(0), 0x00000000 },
-	{ DDRC_RFSHTMG(0), 0x006100E0 },
-	{ DDRC_INIT0(0), 0xC003061B },
-	{ DDRC_INIT1(0), 0x009D0000 },
-	{ DDRC_INIT3(0), 0x00D4002D },
-#ifdef WR_POST_EXT_3200
-	{ DDRC_INIT4(0), 0x00330008 },
-#else
-	{ DDRC_INIT4(0), 0x00310008 },
-#endif
-	{ DDRC_INIT6(0), 0x0066004a },
-	{ DDRC_INIT7(0), 0x0006004a },
-
-	{ DDRC_DRAMTMG0(0), 0x1A201B22 },
-	{ DDRC_DRAMTMG1(0), 0x00060633 },
-	{ DDRC_DRAMTMG3(0), 0x00C0C000 },
-	{ DDRC_DRAMTMG4(0), 0x0F04080F },
-	{ DDRC_DRAMTMG5(0), 0x02040C0C },
-	{ DDRC_DRAMTMG6(0), 0x01010007 },
-	{ DDRC_DRAMTMG7(0), 0x00000401 },
-	{ DDRC_DRAMTMG12(0), 0x00020600 },
-	{ DDRC_DRAMTMG13(0), 0x0C100002 },
-	{ DDRC_DRAMTMG14(0), 0x000000E6 },
-	{ DDRC_DRAMTMG17(0), 0x00A00050 },
-
-	{ DDRC_ZQCTL0(0), 0x03200018 },
-	{ DDRC_ZQCTL1(0), 0x028061A8 },
-	{ DDRC_ZQCTL2(0), 0x00000000 },
-
-	{ DDRC_DFITMG0(0), 0x0497820A },
-	{ DDRC_DFITMG1(0), 0x00080303 },
-	{ DDRC_DFIUPD0(0), 0xE0400018 },
-	{ DDRC_DFIUPD1(0), 0x00DF00E4 },
-	{ DDRC_DFIUPD2(0), 0x80000000 },
-	{ DDRC_DFIMISC(0), 0x00000011 },
-	{ DDRC_DFITMG2(0), 0x0000170A },
-
-	{ DDRC_DBICTL(0), 0x00000001 },
-	{ DDRC_DFIPHYMSTR(0), 0x00000001 },
-	{ DDRC_RANKCTL(0), 0x00000c99 },
-	{ DDRC_DRAMTMG2(0), 0x070E171a },
-
-	/* address mapping */
-	{ DDRC_ADDRMAP0(0), 0x00000015 },
-	{ DDRC_ADDRMAP3(0), 0x00000000 },
-	{ DDRC_ADDRMAP4(0), 0x00001F1F },
-	/* bank interleave */
-	{ DDRC_ADDRMAP1(0), 0x00080808 },
-	{ DDRC_ADDRMAP5(0), 0x07070707 },
-	{ DDRC_ADDRMAP6(0), 0x08080707 },
-
-	/* performance setting */
-	{ DDRC_ODTCFG(0), 0x0b060908 },
-	{ DDRC_ODTMAP(0), 0x00000000 },
-	{ DDRC_SCHED(0), 0x29511505 },
-	{ DDRC_SCHED1(0), 0x0000002c },
-	{ DDRC_PERFHPR1(0), 0x5900575b },
-	/* 150T starve and 0x90 max tran len */
-	{ DDRC_PERFLPR1(0), 0x90000096 },
-	/* 300T starve and 0x10 max tran len */
-	{ DDRC_PERFWR1(0), 0x1000012c },
-	{ DDRC_DBG0(0), 0x00000016 },
-	{ DDRC_DBG1(0), 0x00000000 },
-	{ DDRC_DBGCMD(0), 0x00000000 },
-	{ DDRC_SWCTL(0), 0x00000001 },
-	{ DDRC_POISONCFG(0), 0x00000011 },
-	{ DDRC_PCCFG(0), 0x00000111 },
-	{ DDRC_PCFGR_0(0), 0x000010f3 },
-	{ DDRC_PCFGW_0(0), 0x000072ff },
-	{ DDRC_PCTRL_0(0), 0x00000001 },
-	/* disable Read Qos*/
-	{ DDRC_PCFGQOS0_0(0), 0x00000e00 },
-	{ DDRC_PCFGQOS1_0(0), 0x0062ffff },
-	/* disable Write Qos*/
-	{ DDRC_PCFGWQOS0_0(0), 0x00000e00 },
-	{ DDRC_PCFGWQOS1_0(0), 0x0000ffff },
-
-	/* Frequency 1: 400mbps */
-	{ DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
-	{ DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
-	{ DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
-	{ DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
-	{ DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
-	{ DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
-	{ DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
-	{ DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
-	{ DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
-	{ DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
-	{ DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
-	{ DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
-	{ DDRC_FREQ1_DFITMG0(0), 0x03818200 },
-	{ DDRC_FREQ1_DFITMG2(0), 0x00000000 },
-	{ DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
-	{ DDRC_FREQ1_INIT3(0), 0x00840000 },
-	{ DDRC_FREQ1_INIT4(0), 0x00310008 },
-	{ DDRC_FREQ1_INIT6(0), 0x0066004a },
-	{ DDRC_FREQ1_INIT7(0), 0x0006004a },
-
-	/* Frequency 2: 100mbps */
-	{ DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
-	{ DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
-	{ DDRC_FREQ2_DRAMTMG2(0), 0x0305090c },
-	{ DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
-	{ DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
-	{ DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
-	{ DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
-	{ DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
-	{ DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
-	{ DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
-	{ DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
-	{ DDRC_FREQ2_DFITMG0(0), 0x03818200 },
-	{ DDRC_FREQ2_DFITMG2(0), 0x00000000 },
-	{ DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
-	{ DDRC_FREQ2_INIT3(0), 0x00840000 },
-	{ DDRC_FREQ2_INIT4(0), 0x00310008 },
-	{ DDRC_FREQ2_INIT6(0), 0x0066004a },
-	{ DDRC_FREQ2_INIT7(0), 0x0006004a },
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa3080020 },
+	{ 0x3d400028, 0x0 },
+	{ 0x3d400020, 0x203 },
+	{ 0x3d400024, 0x3e800 },
+	{ 0x3d400064, 0x6100e0 },
+	{ 0x3d4000d0, 0xc003061c },
+	{ 0x3d4000d4, 0x9e0000 },
+	{ 0x3d4000dc, 0xd4002d },
+	{ 0x3d4000e0, 0x310008 },
+	{ 0x3d4000e8, 0x66004a },
+	{ 0x3d4000ec, 0x16004a },
+	{ 0x3d400100, 0x1a201b22 },
+	{ 0x3d400104, 0x60633 },
+	{ 0x3d40010c, 0xc0c000 },
+	{ 0x3d400110, 0xf04080f },
+	{ 0x3d400114, 0x2040c0c },
+	{ 0x3d400118, 0x1010007 },
+	{ 0x3d40011c, 0x401 },
+	{ 0x3d400130, 0x20600 },
+	{ 0x3d400134, 0xc100002 },
+	{ 0x3d400138, 0xe6 },
+	{ 0x3d400144, 0xa00050 },
+	{ 0x3d400180, 0xc3200018 },
+	{ 0x3d400184, 0x28061a8 },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x497820a },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001b4, 0x170a },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x0 },
+	{ 0x3d4000f4, 0x639 },
+	{ 0x3d400108, 0x70e1617 },
+	{ 0x3d400200, 0x15 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x48080707 },
+	{ 0x3d402020, 0x1 },
+	{ 0x3d402024, 0x7d00 },
+	{ 0x3d402050, 0x20d040 },
+	{ 0x3d402064, 0xc001c },
+	{ 0x3d4020dc, 0x840000 },
+	{ 0x3d4020e0, 0x310000 },
+	{ 0x3d4020e8, 0x66004a },
+	{ 0x3d4020ec, 0x16004a },
+	{ 0x3d402100, 0xa040305 },
+	{ 0x3d402104, 0x30407 },
+	{ 0x3d402108, 0x203060b },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x2040202 },
+	{ 0x3d402114, 0x2030202 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x1d },
+	{ 0x3d402144, 0x14000a },
+	{ 0x3d402180, 0xc0640004 },
+	{ 0x3d402190, 0x3818200 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x100 },
+	{ 0x3d403020, 0x1 },
+	{ 0x3d403024, 0x1f40 },
+	{ 0x3d403050, 0x20d040 },
+	{ 0x3d403064, 0x30007 },
+	{ 0x3d4030dc, 0x840000 },
+	{ 0x3d4030e0, 0x310000 },
+	{ 0x3d4030e8, 0x66004a },
+	{ 0x3d4030ec, 0x16004a },
+	{ 0x3d403100, 0xa010102 },
+	{ 0x3d403104, 0x30404 },
+	{ 0x3d403108, 0x203060b },
+	{ 0x3d40310c, 0x505000 },
+	{ 0x3d403110, 0x2040202 },
+	{ 0x3d403114, 0x2030202 },
+	{ 0x3d403118, 0x1010004 },
+	{ 0x3d40311c, 0x301 },
+	{ 0x3d403130, 0x20300 },
+	{ 0x3d403134, 0xa100002 },
+	{ 0x3d403138, 0x8 },
+	{ 0x3d403144, 0x50003 },
+	{ 0x3d403180, 0xc0190004 },
+	{ 0x3d403190, 0x3818200 },
+	{ 0x3d403194, 0x80303 },
+	{ 0x3d4031b4, 0x100 },
+	{ 0x3d400244, 0x0 },
+	{ 0x3d400250, 0x29001505 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x5900575b },
+	{ 0x3d400264, 0x90000096 },
+	{ 0x3d40026c, 0x1000012c },
+	{ 0x3d400300, 0x16 },
+	{ 0x3d400304, 0x0 },
+	{ 0x3d40030c, 0x0 },
+	{ 0x3d400320, 0x1 },
+	{ 0x3d40036c, 0x11 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400404, 0x10f3 },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400490, 0x1 },
+	{ 0x3d400494, 0xe00 },
+	{ 0x3d400498, 0x62ffff },
+	{ 0x3d40049c, 0xe00 },
+	{ 0x3d4004a0, 0xffff },
 };
 
 /* PHY Initialize Configuration */
-struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
-	{ 0x20110, 0x02 },
-	{ 0x20111, 0x03 },
-	{ 0x20112, 0x04 },
-	{ 0x20113, 0x05 },
-	{ 0x20114, 0x00 },
-	{ 0x20115, 0x01 },
-
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x2 },
+	{ 0x110a3, 0x3 },
+	{ 0x110a4, 0x4 },
+	{ 0x110a5, 0x5 },
+	{ 0x110a6, 0x6 },
+	{ 0x110a7, 0x7 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x2 },
+	{ 0x120a3, 0x3 },
+	{ 0x120a4, 0x4 },
+	{ 0x120a5, 0x5 },
+	{ 0x120a6, 0x6 },
+	{ 0x120a7, 0x7 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x2 },
+	{ 0x130a3, 0x3 },
+	{ 0x130a4, 0x4 },
+	{ 0x130a5, 0x5 },
+	{ 0x130a6, 0x6 },
+	{ 0x130a7, 0x7 },
 	{ 0x1005f, 0x1ff },
 	{ 0x1015f, 0x1ff },
 	{ 0x1105f, 0x1ff },
@@ -151,7 +171,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x1215f, 0x1ff },
 	{ 0x1305f, 0x1ff },
 	{ 0x1315f, 0x1ff },
-
 	{ 0x11005f, 0x1ff },
 	{ 0x11015f, 0x1ff },
 	{ 0x11105f, 0x1ff },
@@ -160,7 +179,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x11215f, 0x1ff },
 	{ 0x11305f, 0x1ff },
 	{ 0x11315f, 0x1ff },
-
 	{ 0x21005f, 0x1ff },
 	{ 0x21015f, 0x1ff },
 	{ 0x21105f, 0x1ff },
@@ -169,7 +187,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x21215f, 0x1ff },
 	{ 0x21305f, 0x1ff },
 	{ 0x21315f, 0x1ff },
-
 	{ 0x55, 0x1ff },
 	{ 0x1055, 0x1ff },
 	{ 0x2055, 0x1ff },
@@ -180,32 +197,24 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x7055, 0x1ff },
 	{ 0x8055, 0x1ff },
 	{ 0x9055, 0x1ff },
-
 	{ 0x200c5, 0x19 },
 	{ 0x1200c5, 0x7 },
 	{ 0x2200c5, 0x7 },
-
 	{ 0x2002e, 0x2 },
 	{ 0x12002e, 0x2 },
 	{ 0x22002e, 0x2 },
-
 	{ 0x90204, 0x0 },
 	{ 0x190204, 0x0 },
 	{ 0x290204, 0x0 },
-
-#ifdef WR_POST_EXT_3200
-	{ 0x20024, 0xeb },
-#else
-	{ 0x20024, 0xab },
-#endif
+	{ 0x20024, 0x1ab },
 	{ 0x2003a, 0x0 },
-	{ 0x120024, 0xab },
+	{ 0x120024, 0x1ab },
 	{ 0x2003a, 0x0 },
-	{ 0x220024, 0xab },
+	{ 0x220024, 0x1ab },
 	{ 0x2003a, 0x0 },
 	{ 0x20056, 0x3 },
-	{ 0x120056, 0xa },
-	{ 0x220056, 0xa },
+	{ 0x120056, 0x3 },
+	{ 0x220056, 0x3 },
 	{ 0x1004d, 0xe00 },
 	{ 0x1014d, 0xe00 },
 	{ 0x1104d, 0xe00 },
@@ -230,43 +239,40 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x21214d, 0xe00 },
 	{ 0x21304d, 0xe00 },
 	{ 0x21314d, 0xe00 },
-
-	{ 0x10049, 0xfbe },
-	{ 0x10149, 0xfbe },
-	{ 0x11049, 0xfbe },
-	{ 0x11149, 0xfbe },
-	{ 0x12049, 0xfbe },
-	{ 0x12149, 0xfbe },
-	{ 0x13049, 0xfbe },
-	{ 0x13149, 0xfbe },
-	{ 0x110049, 0xfbe },
-	{ 0x110149, 0xfbe },
-	{ 0x111049, 0xfbe },
-	{ 0x111149, 0xfbe },
-	{ 0x112049, 0xfbe },
-	{ 0x112149, 0xfbe },
-	{ 0x113049, 0xfbe },
-	{ 0x113149, 0xfbe },
-	{ 0x210049, 0xfbe },
-	{ 0x210149, 0xfbe },
-	{ 0x211049, 0xfbe },
-	{ 0x211149, 0xfbe },
-	{ 0x212049, 0xfbe },
-	{ 0x212149, 0xfbe },
-	{ 0x213049, 0xfbe },
-	{ 0x213149, 0xfbe },
-
-	{ 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
-	{ 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
-	{ 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
-	{ 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
-	{ 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
-	{ 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
-	{ 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
-	{ 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
-	{ 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
-	{ 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
-
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x212049, 0xeba },
+	{ 0x212149, 0xeba },
+	{ 0x213049, 0xeba },
+	{ 0x213149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
 	{ 0x20018, 0x3 },
 	{ 0x20075, 0x4 },
 	{ 0x20050, 0x0 },
@@ -274,7 +280,7 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x120008, 0x64 },
 	{ 0x220008, 0x19 },
 	{ 0x20088, 0x9 },
-	{ 0x200b2, 0x104 },
+	{ 0x200b2, 0xdc },
 	{ 0x10043, 0x5a1 },
 	{ 0x10143, 0x5a1 },
 	{ 0x11043, 0x5a1 },
@@ -283,7 +289,7 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x12143, 0x5a1 },
 	{ 0x13043, 0x5a1 },
 	{ 0x13143, 0x5a1 },
-	{ 0x1200b2, 0x104 },
+	{ 0x1200b2, 0xdc },
 	{ 0x110043, 0x5a1 },
 	{ 0x110143, 0x5a1 },
 	{ 0x111043, 0x5a1 },
@@ -292,7 +298,7 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x112143, 0x5a1 },
 	{ 0x113043, 0x5a1 },
 	{ 0x113143, 0x5a1 },
-	{ 0x2200b2, 0x104 },
+	{ 0x2200b2, 0xdc },
 	{ 0x210043, 0x5a1 },
 	{ 0x210143, 0x5a1 },
 	{ 0x211043, 0x5a1 },
@@ -319,376 +325,904 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x2002d, 0x0 },
 	{ 0x12002d, 0x0 },
 	{ 0x22002d, 0x0 },
-
 	{ 0x200c7, 0x80 },
 	{ 0x1200c7, 0x80 },
 	{ 0x2200c7, 0x80 },
 	{ 0x200ca, 0x106 },
 	{ 0x1200ca, 0x106 },
 	{ 0x2200ca, 0x106 },
+	{ 0x20110, 0x2 },
+	{ 0x20111, 0x3 },
+	{ 0x20112, 0x4 },
+	{ 0x20113, 0x5 },
+	{ 0x20114, 0x0 },
+	{ 0x20115, 0x1 },
+	{ 0x20021, 0x0 },
 };
 
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
 /* P0 message block paremeter for training firmware */
-struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+struct dram_cfg_param ddr_fsp0_cfg[] = {
 	{ 0xd0000, 0x0 },
-	{ 0x54000, 0x0 },
-	{ 0x54001, 0x0 },
-	{ 0x54002, 0x0 },
 	{ 0x54003, 0xc80 },
 	{ 0x54004, 0x2 },
-	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, /* PHY Ron/Rtt */
-	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
-	{ 0x54007, 0x0 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
 	{ 0x54008, 0x131f },
-	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
-	{ 0x5400a, 0x0 },
+	{ 0x54009, 0xc8 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400c, 0x0 },
-	{ 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) },
-	{ 0x5400e, 0x0 },
-	{ 0x5400f, 0x0 },
-	{ 0x54010, 0x0 },
-	{ 0x54011, 0x0 },
 	{ 0x54012, 0x310 },
-	{ 0x54013, 0x0 },
-	{ 0x54014, 0x0 },
-	{ 0x54015, 0x0 },
-	{ 0x54016, 0x0 },
-	{ 0x54017, 0x0 },
-	{ 0x54018, 0x0 },
-
 	{ 0x54019, 0x2dd4 },
-#ifdef WR_POST_EXT_3200
-	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
-#else
-	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
-#endif
-	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
-		    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
-	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
-	{ 0x5401d, 0x0 },
-	{ 0x5401e, LPDDR4_MR22_RANK0 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x2dd4 },
-#ifdef WR_POST_EXT_3200
-	{ 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
-#else
-	{ 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
-#endif
-	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
-		    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
-	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
-	{ 0x54023, 0x0 },
-	{ 0x54024, LPDDR4_MR22_RANK1 },
-
-	{ 0x54025, 0x0 },
-	{ 0x54026, 0x0 },
-	{ 0x54027, 0x0 },
-	{ 0x54028, 0x0 },
-	{ 0x54029, 0x0 },
-	{ 0x5402a, 0x0 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x3 },
-	{ 0x5402d, 0x0 },
-	{ 0x5402e, 0x0 },
-	{ 0x5402f, 0x0 },
-	{ 0x54030, 0x0 },
-	{ 0x54031, 0x0 },
 	{ 0x54032, 0xd400 },
-	/* MR3/MR2 */
-#ifdef WR_POST_EXT_3200
-	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d /*0x312d*/ },
-#else
-	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },
-#endif
-	/* MR11/MR4 */
-	{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
-	/* self:0x284d//MR13/MR12 */
-	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
-	/* MR16/MR14*/
-	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/ },
-	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x500*/ },
-	/* MR1 */
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
 	{ 0x54038, 0xd400 },
-	/* MR3/MR2 */
-#ifdef WR_POST_EXT_3200
-	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d/*0x312d*/ },
-#else
-	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },
-#endif
-	/* MR11/MR4 */
-	{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
-	/* self:0x284d//MR13/MR12 */
-	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
-	/* MR16/MR14 */
-	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/ },
-	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
-	/* { 0x5403d, 0x500 } */
-	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
-	{ 0x5403e, 0x0 },
-	{ 0x5403f, 0x0 },
-	{ 0x54040, 0x0 },
-	{ 0x54041, 0x0 },
-	{ 0x54042, 0x0 },
-	{ 0x54043, 0x0 },
-	{ 0x54044, 0x0 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
 	{ 0xd0000, 0x1 },
 };
 
+
 /* P1 message block paremeter for training firmware */
-struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+struct dram_cfg_param ddr_fsp1_cfg[] = {
 	{ 0xd0000, 0x0 },
-	{ 0x54000, 0x0 },
-	{ 0x54001, 0x0 },
 	{ 0x54002, 0x101 },
 	{ 0x54003, 0x190 },
 	{ 0x54004, 0x2 },
-	/* PHY Ron/Rtt */
-	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)/*0x2828*/ },
-	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
-	{ 0x54007, 0x0 },
-	{ 0x54008, LPDDR4_TRAIN_SEQ_400 },
-	{ 0x54009, LPDDR4_HDT_CTL_400_1D },
-	{ 0x5400a, 0x0 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400c, 0x0 },
-	{ 0x5400d, (LPDDR4_CATRAIN_400 << 8) },
-	{ 0x5400e, 0x0 },
-	{ 0x5400f, 0x0 },
-	{ 0x54010, 0x0 },
-	{ 0x54011, 0x0 },
 	{ 0x54012, 0x310 },
-	{ 0x54013, 0x0 },
-	{ 0x54014, 0x0 },
-	{ 0x54015, 0x0 },
-	{ 0x54016, 0x0 },
-	{ 0x54017, 0x0 },
-	{ 0x54018, 0x0 },
 	{ 0x54019, 0x84 },
-	/* MR4/MR3 */
-	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ },
-	/* MR12/MR11 */
-	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
-		    LPDDR4_RTT_DQ)/*0x4d46*/ },
-	/* self:0x4d28//MR14/MR13 */
-	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)/*0x4d08*/ },
-	{ 0x5401d, 0x0 },
-	{ 0x5401e, LPDDR4_MR22_RANK0/*0x5*/ },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x84 },
-	{ 0x54020, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, /* MR4/MR3 */
-	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
-		    LPDDR4_RTT_DQ)/*0x4d46*/ },/* MR12/MR11 */
-	/* self:0x4d28//MR14/MR13 */
-	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)/*0x4d08*/ },
-	{ 0x54023, 0x0 },
-	{ 0x54024, LPDDR4_MR22_RANK1 },
-	{ 0x54025, 0x0 },
-	{ 0x54026, 0x0 },
-	{ 0x54027, 0x0 },
-	{ 0x54028, 0x0 },
-	{ 0x54029, 0x0 },
-	{ 0x5402a, 0x0 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x3 },
-	{ 0x5402d, 0x0 },
-	{ 0x5402e, 0x0 },
-	{ 0x5402f, 0x0 },
-	{ 0x54030, 0x0 },
-	{ 0x54031, 0x0 },
 	{ 0x54032, 0x8400 },
-	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
-	{ 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
-	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
-	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
-	{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
 	{ 0x54038, 0x8400 },
-	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
-	{ 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
-	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
-	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
-	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
-	{ 0x5403e, 0x0 },
-	{ 0x5403f, 0x0 },
-	{ 0x54040, 0x0 },
-	{ 0x54041, 0x0 },
-	{ 0x54042, 0x0 },
-	{ 0x54043, 0x0 },
-	{ 0x54044, 0x0 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
 	{ 0xd0000, 0x1 },
 };
 
+
 /* P2 message block paremeter for training firmware */
-struct dram_cfg_param lpddr4_fsp2_cfg[] = {
+struct dram_cfg_param ddr_fsp2_cfg[] = {
 	{ 0xd0000, 0x0 },
-	{ 0x54000, 0x0 },
-	{ 0x54001, 0x0 },
 	{ 0x54002, 0x102 },
 	{ 0x54003, 0x64 },
 	{ 0x54004, 0x2 },
-	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
-	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
-	{ 0x54007, 0x0 },
-	{ 0x54008, LPDDR4_TRAIN_SEQ_100 },
-	{ 0x54009, LPDDR4_HDT_CTL_100_1D },
-	{ 0x5400a, 0x0 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400c, 0x0 },
-	{ 0x5400d, (LPDDR4_CATRAIN_100 << 8) },
-	{ 0x5400e, 0x0 },
-	{ 0x5400f, 0x0 },
-	{ 0x54010, 0x0 },
-	{ 0x54011, 0x0 },
 	{ 0x54012, 0x310 },
-	{ 0x54013, 0x0 },
-	{ 0x54014, 0x0 },
-	{ 0x54015, 0x0 },
-	{ 0x54016, 0x0 },
-	{ 0x54017, 0x0 },
-	{ 0x54018, 0x0 },
 	{ 0x54019, 0x84 },
-	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
-	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
-		    LPDDR4_RTT_DQ) },
-	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
-	{ 0x5401d, 0x0 },
-	{ 0x5401e, LPDDR4_MR22_RANK0 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x84 },
-	{ 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
-	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
-		    LPDDR4_RTT_DQ) },
-	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
-	{ 0x54023, 0x0 },
-	{ 0x54024, LPDDR4_MR22_RANK1 },
-	{ 0x54025, 0x0 },
-	{ 0x54026, 0x0 },
-	{ 0x54027, 0x0 },
-	{ 0x54028, 0x0 },
-	{ 0x54029, 0x0 },
-	{ 0x5402a, 0x0 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x3 },
-	{ 0x5402d, 0x0 },
-	{ 0x5402e, 0x0 },
-	{ 0x5402f, 0x0 },
-	{ 0x54030, 0x0 },
-	{ 0x54031, 0x0 },
 	{ 0x54032, 0x8400 },
-	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
-	{ 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
-	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
-	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
-	{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
+	{ 0x54033, 0x3100 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
 	{ 0x54038, 0x8400 },
-	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
-	{ 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
-	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
-	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
-	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
-	{ 0x5403e, 0x0 },
-	{ 0x5403f, 0x0 },
-	{ 0x54040, 0x0 },
-	{ 0x54041, 0x0 },
-	{ 0x54042, 0x0 },
-	{ 0x54043, 0x0 },
-	{ 0x54044, 0x0 },
+	{ 0x54039, 0x3100 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
 	{ 0xd0000, 0x1 },
 };
 
+
 /* P0 2D message block paremeter for training firmware */
-struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{ 0xd0000, 0x0 },
-	{ 0x54000, 0x0 },
-	{ 0x54001, 0x0 },
-	{ 0x54002, 0x0 },
 	{ 0x54003, 0xc80 },
 	{ 0x54004, 0x2 },
-	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
-	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
-	{ 0x54007, 0x0 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
 	{ 0x54008, 0x61 },
-	{ 0x54009, LPDDR4_HDT_CTL_2D },
-	{ 0x5400a, 0x0 },
+	{ 0x54009, 0xc8 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400c, 0x0 },
-	{ 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
-	{ 0x5400e, 0x0 },
-	{ 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
-	{ 0x54010, LPDDR4_2D_WEIGHT },
-	{ 0x54011, 0x0 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
 	{ 0x54012, 0x310 },
-	{ 0x54013, 0x0 },
-	{ 0x54014, 0x0 },
-	{ 0x54015, 0x0 },
-	{ 0x54016, 0x0 },
-	{ 0x54017, 0x0 },
-	{ 0x54018, 0x0 },
 	{ 0x54019, 0x2dd4 },
-#ifdef WR_POST_EXT_3200
-	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
-#else
-	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
-#endif
-	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
-		    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
-	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
-	{ 0x5401d, 0x0 },
-	{ 0x5401e, LPDDR4_MR22_RANK0 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x2dd4 },
-#ifdef WR_POST_EXT_3200
-	{ 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
-#else
-	{ 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
-#endif
-	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
-		    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
-	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
-	{ 0x54023, 0x0 },
-	{ 0x54024, LPDDR4_MR22_RANK1 },
-	{ 0x54025, 0x0 },
-	{ 0x54026, 0x0 },
-	{ 0x54027, 0x0 },
-	{ 0x54028, 0x0 },
-	{ 0x54029, 0x0 },
-	{ 0x5402a, 0x0 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x3 },
-	{ 0x5402d, 0x0 },
-	{ 0x5402e, 0x0 },
-	{ 0x5402f, 0x0 },
-	{ 0x54030, 0x0 },
-	{ 0x54031, 0x0 },
-
 	{ 0x54032, 0xd400 },
-#ifdef WR_POST_EXT_3200
-	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
-#else
-	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },
-#endif
-	{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
-	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
-	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
-	{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
 	{ 0x54038, 0xd400 },
-#ifdef WR_POST_EXT_3200
-	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
-#else
-	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },
-#endif
-	{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
-	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
-	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
-	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
-	{ 0x5403e, 0x0 },
-	{ 0x5403f, 0x0 },
-	{ 0x54040, 0x0 },
-	{ 0x54041, 0x0 },
-	{ 0x54042, 0x0 },
-	{ 0x54043, 0x0 },
-	{ 0x54044, 0x0 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
 	{ 0xd0000, 0x1 },
 };
 
 /* DRAM PHY init engine image */
-struct dram_cfg_param lpddr4_phy_pie[] = {
+struct dram_cfg_param ddr_phy_pie[] = {
 	{ 0xd0000, 0x0 },
 	{ 0x90000, 0x10 },
 	{ 0x90001, 0x400 },
@@ -1197,8 +1731,12 @@ struct dram_cfg_param lpddr4_phy_pie[] = {
 	{ 0x90011, 0xdfbd },
 	{ 0x90012, 0x60 },
 	{ 0x90013, 0x6152 },
-	{ 0x20010, 0x5a },
-	{ 0x20011, 0x3 },
+	{ 0x20010, 0x00 },
+	{ 0x20011, 0x0 },
+	{ 0x120010, 0x00 },
+	{ 0x120011, 0x0 },
+	{ 0x220010, 0x00 },
+	{ 0x220011, 0x0 },
 	{ 0x40080, 0xe0 },
 	{ 0x40081, 0x12 },
 	{ 0x40082, 0xe0 },
@@ -1276,49 +1814,52 @@ struct dram_cfg_param lpddr4_phy_pie[] = {
 	{ 0x138b4, 0x1 },
 	{ 0x2003a, 0x2 },
 	{ 0xc0080, 0x2 },
-	{ 0xd0000, 0x1 },
+	{ 0xd0000, 0x1 }
 };
 
-struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
 	{
 		/* P0 3200mts 1D */
 		.drate = 3200,
 		.fw_type = FW_1D_IMAGE,
-		.fsp_cfg = lpddr4_fsp0_cfg,
-		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
 	},
 	{
 		/* P1 400mts 1D */
 		.drate = 400,
 		.fw_type = FW_1D_IMAGE,
-		.fsp_cfg = lpddr4_fsp1_cfg,
-		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
 	},
 	{
-		/* P1 100mts 1D */
+		/* P2 100mts 1D */
 		.drate = 100,
 		.fw_type = FW_1D_IMAGE,
-		.fsp_cfg = lpddr4_fsp2_cfg,
-		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
 	},
 	{
 		/* P0 3200mts 2D */
 		.drate = 3200,
 		.fw_type = FW_2D_IMAGE,
-		.fsp_cfg = lpddr4_fsp0_2d_cfg,
-		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
 	},
 };
 
-/* lpddr4 timing config params on EVK board */
+/* ddr timing config params */
 struct dram_timing_info dram_timing = {
-	.ddrc_cfg = lpddr4_ddrc_cfg,
-	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
-	.ddrphy_cfg = lpddr4_ddrphy_cfg,
-	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
-	.fsp_msg = lpddr4_dram_fsp_msg,
-	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
-	.ddrphy_pie = lpddr4_phy_pie,
-	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
 	.fsp_table = { 3200, 400, 100, },
 };
+
diff --git a/board/freescale/imx8mq_evk/lpddr4_timing_b0.c b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c
index ec68edaf690..b8a147d3bb7 100644
--- a/board/freescale/imx8mq_evk/lpddr4_timing_b0.c
+++ b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c
@@ -1,147 +1,144 @@
-// SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2019.04_5.4.x and above version
+ * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga:
+ * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h>
  */
 
 #include <linux/kernel.h>
-#include <common.h>
 #include <asm/arch/ddr.h>
-#include <asm/arch/lpddr4_define.h>
 
-#define WR_POST_EXT_3200  /* recommened to define */
-
-static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
-	/* Start to config, default 3200mbps */
-	/* dis_dq=1, indicates no reads or writes are issued to SDRAM */
-	{ DDRC_DBG1(0), 0x00000001 },
-	/* selfref_en=1, SDRAM enter self-refresh state */
-	{ DDRC_PWRCTL(0), 0x00000001 },
-	{ DDRC_MSTR(0), 0xa3080020 },
-	{ DDRC_MSTR2(0), 0x00000000 },
-	{ DDRC_RFSHTMG(0), 0x006100E0 },
-	{ DDRC_INIT0(0), 0xC003061B },
-	{ DDRC_INIT1(0), 0x009D0000 },
-	{ DDRC_INIT3(0), 0x00D4002D },
-#ifdef WR_POST_EXT_3200  /* recommened to define */
-	{ DDRC_INIT4(0), 0x00330008 },
-#else
-	{ DDRC_INIT4(0), 0x00310008 },
-#endif
-	{ DDRC_INIT6(0), 0x0066004a },
-	{ DDRC_INIT7(0), 0x0006004a },
-
-	{ DDRC_DRAMTMG0(0), 0x1A201B22 },
-	{ DDRC_DRAMTMG1(0), 0x00060633 },
-	{ DDRC_DRAMTMG3(0), 0x00C0C000 },
-	{ DDRC_DRAMTMG4(0), 0x0F04080F },
-	{ DDRC_DRAMTMG5(0), 0x02040C0C },
-	{ DDRC_DRAMTMG6(0), 0x01010007 },
-	{ DDRC_DRAMTMG7(0), 0x00000401 },
-	{ DDRC_DRAMTMG12(0), 0x00020600 },
-	{ DDRC_DRAMTMG13(0), 0x0C100002 },
-	{ DDRC_DRAMTMG14(0), 0x000000E6 },
-	{ DDRC_DRAMTMG17(0), 0x00A00050 },
-
-	{ DDRC_ZQCTL0(0), 0x03200018 },
-	{ DDRC_ZQCTL1(0), 0x028061A8 },
-	{ DDRC_ZQCTL2(0), 0x00000000 },
-
-	{ DDRC_DFITMG0(0), 0x0497820A },
-	{ DDRC_DFITMG1(0), 0x00080303 },
-	{ DDRC_DFIUPD0(0), 0xE0400018 },
-	{ DDRC_DFIUPD1(0), 0x00DF00E4 },
-	{ DDRC_DFIUPD2(0), 0x80000000 },
-	{ DDRC_DFIMISC(0), 0x00000011 },
-	{ DDRC_DFITMG2(0), 0x0000170A },
-
-	{ DDRC_DBICTL(0), 0x00000001 },
-	{ DDRC_DFIPHYMSTR(0), 0x00000001 },
-
-	/* need be refined by ddrphy trained value */
-	{ DDRC_RANKCTL(0), 0x00000c99 },
-	{ DDRC_DRAMTMG2(0), 0x070E171a },
-
-	/* address mapping */
-	/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
-	{ DDRC_ADDRMAP0(0), 0x00000015 },
-	{ DDRC_ADDRMAP3(0), 0x00000000 },
-	/* addrmap_col_b10 addrmap_col_b11 set to de-activated (5-bit width) */
-	{ DDRC_ADDRMAP4(0), 0x00001F1F },
-	/* bank interleave */
-	/* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
-	{ DDRC_ADDRMAP1(0), 0x00080808 },
-	/* addrmap_row_b11 addrmap_row_b10_b2 addrmap_row_b1 addrmap_row_b0 */
-	{ DDRC_ADDRMAP5(0), 0x07070707 },
-	/* addrmap_row_b15 addrmap_row_b14 addrmap_row_b13 addrmap_row_b12 */
-	{ DDRC_ADDRMAP6(0), 0x08080707 },
-
-	/* 667mts frequency setting */
-	{ DDRC_FREQ1_DERATEEN(0), 0x0000000 },
-	{ DDRC_FREQ1_DERATEINT(0), 0x0800000 },
-	{ DDRC_FREQ1_RFSHCTL0(0), 0x0210000 },
-	{ DDRC_FREQ1_RFSHTMG(0), 0x014001E },
-	{ DDRC_FREQ1_INIT3(0), 0x0140009 },
-	{ DDRC_FREQ1_INIT4(0), 0x00310008 },
-	{ DDRC_FREQ1_INIT6(0), 0x0066004a },
-	{ DDRC_FREQ1_INIT7(0), 0x0006004a },
-	{ DDRC_FREQ1_DRAMTMG0(0), 0xB070A07 },
-	{ DDRC_FREQ1_DRAMTMG1(0), 0x003040A },
-	{ DDRC_FREQ1_DRAMTMG2(0), 0x305080C },
-	{ DDRC_FREQ1_DRAMTMG3(0), 0x0505000 },
-	{ DDRC_FREQ1_DRAMTMG4(0), 0x3040203 },
-	{ DDRC_FREQ1_DRAMTMG5(0), 0x2030303 },
-	{ DDRC_FREQ1_DRAMTMG6(0), 0x2020004 },
-	{ DDRC_FREQ1_DRAMTMG7(0), 0x0000302 },
-	{ DDRC_FREQ1_DRAMTMG12(0), 0x0020310 },
-	{ DDRC_FREQ1_DRAMTMG13(0), 0xA100002 },
-	{ DDRC_FREQ1_DRAMTMG14(0), 0x0000020 },
-	{ DDRC_FREQ1_DRAMTMG17(0), 0x0220011 },
-	{ DDRC_FREQ1_ZQCTL0(0), 0x0A70005 },
-	{ DDRC_FREQ1_DFITMG0(0), 0x3858202 },
-	{ DDRC_FREQ1_DFITMG1(0), 0x0000404 },
-	{ DDRC_FREQ1_DFITMG2(0), 0x0000502 },
-
-	/* performance setting */
-	{ DDRC_ODTCFG(0), 0x0b060908 },
-	{ DDRC_ODTMAP(0), 0x00000000 },
-	{ DDRC_SCHED(0), 0x29511505 },
-	{ DDRC_SCHED1(0), 0x0000002c },
-	{ DDRC_PERFHPR1(0), 0x5900575b },
-	/* 150T starve and 0x90 max tran len */
-	{ DDRC_PERFLPR1(0), 0x90000096 },
-	/* 300T starve and 0x10 max tran len */
-	{ DDRC_PERFWR1(0), 0x1000012c },
-	{ DDRC_DBG0(0), 0x00000016 },
-	{ DDRC_DBG1(0), 0x00000000 },
-	{ DDRC_DBGCMD(0), 0x00000000 },
-	{ DDRC_SWCTL(0), 0x00000001 },
-	{ DDRC_POISONCFG(0), 0x00000011 },
-	{ DDRC_PCCFG(0), 0x00000111 },
-	{ DDRC_PCFGR_0(0), 0x000010f3 },
-	{ DDRC_PCFGW_0(0), 0x000072ff },
-	{ DDRC_PCTRL_0(0), 0x00000001 },
-	/* disable Read Qos*/
-	{ DDRC_PCFGQOS0_0(0), 0x00000e00 },
-	{ DDRC_PCFGQOS1_0(0), 0x0062ffff },
-	/* disable Write Qos*/
-	{ DDRC_PCFGWQOS0_0(0), 0x00000e00 },
-	{ DDRC_PCFGWQOS1_0(0), 0x0000ffff },
-	{ DDRC_FREQ1_DERATEEN(0), 0x00000202 },
-	{ DDRC_FREQ1_DERATEINT(0), 0xec78f4b5 },
-	{ DDRC_FREQ1_RFSHCTL0(0), 0x00618040 },
-	{ DDRC_FREQ1_RFSHTMG(0), 0x00610090 },
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0xa3080020 },
+	{ 0x3d400028, 0x0 },
+	{ 0x3d400020, 0x203 },
+	{ 0x3d400024, 0x3e800 },
+	{ 0x3d400064, 0x6100e0 },
+	{ 0x3d4000d0, 0xc003061c },
+	{ 0x3d4000d4, 0x9e0000 },
+	{ 0x3d4000dc, 0xd4002d },
+	{ 0x3d4000e0, 0x310008 },
+	{ 0x3d4000e8, 0x66004a },
+	{ 0x3d4000ec, 0x16004a },
+	{ 0x3d400100, 0x1a201b22 },
+	{ 0x3d400104, 0x60633 },
+	{ 0x3d40010c, 0xc0c000 },
+	{ 0x3d400110, 0xf04080f },
+	{ 0x3d400114, 0x2040c0c },
+	{ 0x3d400118, 0x1010007 },
+	{ 0x3d40011c, 0x401 },
+	{ 0x3d400130, 0x20600 },
+	{ 0x3d400134, 0xc100002 },
+	{ 0x3d400138, 0xe6 },
+	{ 0x3d400144, 0xa00050 },
+	{ 0x3d400180, 0xc3200018 },
+	{ 0x3d400184, 0x28061a8 },
+	{ 0x3d400188, 0x0 },
+	{ 0x3d400190, 0x497820a },
+	{ 0x3d400194, 0x80303 },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0xdf00e4 },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x11 },
+	{ 0x3d4001b4, 0x170a },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x1 },
+	{ 0x3d4000f4, 0x639 },
+	{ 0x3d400108, 0x70e1617 },
+	{ 0x3d400200, 0x15 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400204, 0x80808 },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x48080707 },
+	{ 0x3d402020, 0x1 },
+	{ 0x3d402024, 0xd0c0 },
+	{ 0x3d402050, 0x20d040 },
+	{ 0x3d402064, 0x14002f },
+	{ 0x3d4020dc, 0x940009 },
+	{ 0x3d4020e0, 0x310000 },
+	{ 0x3d4020e8, 0x66004a },
+	{ 0x3d4020ec, 0x16004a },
+	{ 0x3d402100, 0xb070508 },
+	{ 0x3d402104, 0x3040b },
+	{ 0x3d402108, 0x305090c },
+	{ 0x3d40210c, 0x505000 },
+	{ 0x3d402110, 0x4040204 },
+	{ 0x3d402114, 0x2030303 },
+	{ 0x3d402118, 0x1010004 },
+	{ 0x3d40211c, 0x301 },
+	{ 0x3d402130, 0x20300 },
+	{ 0x3d402134, 0xa100002 },
+	{ 0x3d402138, 0x31 },
+	{ 0x3d402144, 0x220011 },
+	{ 0x3d402180, 0xc0a70006 },
+	{ 0x3d402190, 0x3858202 },
+	{ 0x3d402194, 0x80303 },
+	{ 0x3d4021b4, 0x502 },
+	{ 0x3d400244, 0x0 },
+	{ 0x3d400250, 0x29001505 },
+	{ 0x3d400254, 0x2c },
+	{ 0x3d40025c, 0x5900575b },
+	{ 0x3d400264, 0x90000096 },
+	{ 0x3d40026c, 0x1000012c },
+	{ 0x3d400300, 0x16 },
+	{ 0x3d400304, 0x0 },
+	{ 0x3d40030c, 0x0 },
+	{ 0x3d400320, 0x1 },
+	{ 0x3d40036c, 0x11 },
+	{ 0x3d400400, 0x111 },
+	{ 0x3d400404, 0x10f3 },
+	{ 0x3d400408, 0x72ff },
+	{ 0x3d400490, 0x1 },
+	{ 0x3d400494, 0xe00 },
+	{ 0x3d400498, 0x62ffff },
+	{ 0x3d40049c, 0xe00 },
+	{ 0x3d4004a0, 0xffff },
 };
 
 /* PHY Initialize Configuration */
-static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
-	{ 0x20110, 0x02 }, /* MapCAB0toDFI */
-	{ 0x20111, 0x03 }, /* MapCAB1toDFI */
-	{ 0x20112, 0x04 }, /* MapCAB2toDFI */
-	{ 0x20113, 0x05 }, /* MapCAB3toDFI */
-	{ 0x20114, 0x00 }, /* MapCAB4toDFI */
-	{ 0x20115, 0x01 }, /* MapCAB5toDFI */
-
-	/* Initialize PHY Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x1 },
+	{ 0x100a2, 0x2 },
+	{ 0x100a3, 0x3 },
+	{ 0x100a4, 0x4 },
+	{ 0x100a5, 0x5 },
+	{ 0x100a6, 0x6 },
+	{ 0x100a7, 0x7 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x1 },
+	{ 0x110a2, 0x2 },
+	{ 0x110a3, 0x3 },
+	{ 0x110a4, 0x4 },
+	{ 0x110a5, 0x5 },
+	{ 0x110a6, 0x6 },
+	{ 0x110a7, 0x7 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x1 },
+	{ 0x120a2, 0x2 },
+	{ 0x120a3, 0x3 },
+	{ 0x120a4, 0x4 },
+	{ 0x120a5, 0x5 },
+	{ 0x120a6, 0x6 },
+	{ 0x120a7, 0x7 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x1 },
+	{ 0x130a2, 0x2 },
+	{ 0x130a3, 0x3 },
+	{ 0x130a4, 0x4 },
+	{ 0x130a5, 0x5 },
+	{ 0x130a6, 0x6 },
+	{ 0x130a7, 0x7 },
 	{ 0x1005f, 0x1ff },
 	{ 0x1015f, 0x1ff },
 	{ 0x1105f, 0x1ff },
@@ -150,7 +147,6 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x1215f, 0x1ff },
 	{ 0x1305f, 0x1ff },
 	{ 0x1315f, 0x1ff },
-
 	{ 0x11005f, 0x1ff },
 	{ 0x11015f, 0x1ff },
 	{ 0x11105f, 0x1ff },
@@ -159,16 +155,6 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x11215f, 0x1ff },
 	{ 0x11305f, 0x1ff },
 	{ 0x11315f, 0x1ff },
-
-	{ 0x21005f, 0x1ff },
-	{ 0x21015f, 0x1ff },
-	{ 0x21105f, 0x1ff },
-	{ 0x21115f, 0x1ff },
-	{ 0x21205f, 0x1ff },
-	{ 0x21215f, 0x1ff },
-	{ 0x21305f, 0x1ff },
-	{ 0x21315f, 0x1ff },
-
 	{ 0x55, 0x1ff },
 	{ 0x1055, 0x1ff },
 	{ 0x2055, 0x1ff },
@@ -181,25 +167,16 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x9055, 0x1ff },
 	{ 0x200c5, 0x19 },
 	{ 0x1200c5, 0x7 },
-	{ 0x2200c5, 0x7 },
 	{ 0x2002e, 0x2 },
 	{ 0x12002e, 0x1 },
-	{ 0x22002e, 0x2 },
 	{ 0x90204, 0x0 },
 	{ 0x190204, 0x0 },
-	{ 0x290204, 0x0 },
-
-	{ 0x20024, 0xe3 },
-	{ 0x2003a, 0x2 },
-	{ 0x120024, 0xa3 },
-	{ 0x2003a, 0x2 },
-	{ 0x220024, 0xa3 },
-	{ 0x2003a, 0x2 },
-
+	{ 0x20024, 0x1ab },
+	{ 0x2003a, 0x0 },
+	{ 0x120024, 0x1ab },
+	{ 0x2003a, 0x0 },
 	{ 0x20056, 0x3 },
-	{ 0x120056, 0xa },
-	{ 0x220056, 0xa },
-
+	{ 0x120056, 0x3 },
 	{ 0x1004d, 0xe00 },
 	{ 0x1014d, 0xe00 },
 	{ 0x1104d, 0xe00 },
@@ -216,42 +193,22 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x11214d, 0xe00 },
 	{ 0x11304d, 0xe00 },
 	{ 0x11314d, 0xe00 },
-	{ 0x21004d, 0xe00 },
-	{ 0x21014d, 0xe00 },
-	{ 0x21104d, 0xe00 },
-	{ 0x21114d, 0xe00 },
-	{ 0x21204d, 0xe00 },
-	{ 0x21214d, 0xe00 },
-	{ 0x21304d, 0xe00 },
-	{ 0x21314d, 0xe00 },
-
-	{ 0x10049, 0xfbe },
-	{ 0x10149, 0xfbe },
-	{ 0x11049, 0xfbe },
-	{ 0x11149, 0xfbe },
-	{ 0x12049, 0xfbe },
-	{ 0x12149, 0xfbe },
-	{ 0x13049, 0xfbe },
-	{ 0x13149, 0xfbe },
-
-	{ 0x110049, 0xfbe },
-	{ 0x110149, 0xfbe },
-	{ 0x111049, 0xfbe },
-	{ 0x111149, 0xfbe },
-	{ 0x112049, 0xfbe },
-	{ 0x112149, 0xfbe },
-	{ 0x113049, 0xfbe },
-	{ 0x113149, 0xfbe },
-
-	{ 0x210049, 0xfbe },
-	{ 0x210149, 0xfbe },
-	{ 0x211049, 0xfbe },
-	{ 0x211149, 0xfbe },
-	{ 0x212049, 0xfbe },
-	{ 0x212149, 0xfbe },
-	{ 0x213049, 0xfbe },
-	{ 0x213149, 0xfbe },
-
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
 	{ 0x43, 0x63 },
 	{ 0x1043, 0x63 },
 	{ 0x2043, 0x63 },
@@ -262,15 +219,13 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x7043, 0x63 },
 	{ 0x8043, 0x63 },
 	{ 0x9043, 0x63 },
-
 	{ 0x20018, 0x3 },
 	{ 0x20075, 0x4 },
 	{ 0x20050, 0x0 },
 	{ 0x20008, 0x320 },
 	{ 0x120008, 0xa7 },
-	{ 0x220008, 0x19 },
 	{ 0x20088, 0x9 },
-	{ 0x200b2, 0x104 },
+	{ 0x200b2, 0xdc },
 	{ 0x10043, 0x5a1 },
 	{ 0x10143, 0x5a1 },
 	{ 0x11043, 0x5a1 },
@@ -279,7 +234,7 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x12143, 0x5a1 },
 	{ 0x13043, 0x5a1 },
 	{ 0x13143, 0x5a1 },
-	{ 0x1200b2, 0x104 },
+	{ 0x1200b2, 0xdc },
 	{ 0x110043, 0x5a1 },
 	{ 0x110143, 0x5a1 },
 	{ 0x111043, 0x5a1 },
@@ -288,270 +243,876 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
 	{ 0x112143, 0x5a1 },
 	{ 0x113043, 0x5a1 },
 	{ 0x113143, 0x5a1 },
-	{ 0x2200b2, 0x104 },
-	{ 0x210043, 0x5a1 },
-	{ 0x210143, 0x5a1 },
-	{ 0x211043, 0x5a1 },
-	{ 0x211143, 0x5a1 },
-	{ 0x212043, 0x5a1 },
-	{ 0x212143, 0x5a1 },
-	{ 0x213043, 0x5a1 },
-	{ 0x213143, 0x5a1 },
 	{ 0x200fa, 0x1 },
 	{ 0x1200fa, 0x1 },
-	{ 0x2200fa, 0x1 },
 	{ 0x20019, 0x1 },
 	{ 0x120019, 0x1 },
-	{ 0x220019, 0x1 },
-	{ 0x200f0, 0x600 },
+	{ 0x200f0, 0x0 },
 	{ 0x200f1, 0x0 },
 	{ 0x200f2, 0x4444 },
 	{ 0x200f3, 0x8888 },
-	{ 0x200f4, 0x5655 },
+	{ 0x200f4, 0x5555 },
 	{ 0x200f5, 0x0 },
 	{ 0x200f6, 0x0 },
 	{ 0x200f7, 0xf000 },
 	{ 0x20025, 0x0 },
 	{ 0x2002d, 0x0 },
 	{ 0x12002d, 0x0 },
-	{ 0x22002d, 0x0 },
+	{ 0x200c7, 0x80 },
+	{ 0x1200c7, 0x80 },
+	{ 0x200ca, 0x106 },
+	{ 0x1200ca, 0x106 },
+	{ 0x20110, 0x2 },
+	{ 0x20111, 0x3 },
+	{ 0x20112, 0x4 },
+	{ 0x20113, 0x5 },
+	{ 0x20114, 0x0 },
+	{ 0x20115, 0x1 },
 };
 
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
 /* P0 message block paremeter for training firmware */
-static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
 	{ 0xd0000, 0x0 },
-	{ 0x54000, 0x0 },
-	{ 0x54001, 0x0 },
-	{ 0x54002, 0x0 },
 	{ 0x54003, 0xc80 },
 	{ 0x54004, 0x2 },
-	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
-	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
-	{ 0x54007, 0x0 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
 	{ 0x54008, 0x131f },
-	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
-	{ 0x5400a, 0x0 },
+	{ 0x54009, 0xc8 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400c, 0x0 },
-	{ 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) },
-	{ 0x5400e, 0x0 },
-	{ 0x5400f, 0x0 },
-	{ 0x54010, 0x0 },
-	{ 0x54011, 0x0 },
 	{ 0x54012, 0x310 },
-	{ 0x54013, 0x0 },
-	{ 0x54014, 0x0 },
-	{ 0x54015, 0x0 },
-	{ 0x54016, 0x0 },
-	{ 0x54017, 0x0 },
-	{ 0x54018, 0x0 },
 	{ 0x54019, 0x2dd4 },
-	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
-	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
-		    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
-	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
-	{ 0x5401d, 0x0 },
-	{ 0x5401e, LPDDR4_MR22_RANK0 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x2dd4 },
-	{ 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
-	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
-		    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
-	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
-	{ 0x54023, 0x0 },
-	{ 0x54024, LPDDR4_MR22_RANK1 },
-	{ 0x54025, 0x0 },
-	{ 0x54026, 0x0 },
-	{ 0x54027, 0x0 },
-	{ 0x54028, 0x0 },
-	{ 0x54029, 0x0 },
-	{ 0x5402a, 0x0 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x3 },
-	{ 0x5402d, 0x0 },
-	{ 0x5402e, 0x0 },
-	{ 0x5402f, 0x0 },
-	{ 0x54030, 0x0 },
-	{ 0x54031, 0x0 },
 	{ 0x54032, 0xd400 },
-	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
-	{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
-	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
-	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
-	{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
 	{ 0x54038, 0xd400 },
-	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
-	{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
-	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
-	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
-	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
-	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
-	{ 0x5403e, 0x0 },
-	{ 0x5403f, 0x0 },
-	{ 0x54040, 0x0 },
-	{ 0x54041, 0x0 },
-	{ 0x54042, 0x0 },
-	{ 0x54043, 0x0 },
-	{ 0x54044, 0x0 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
 	{ 0xd0000, 0x1 },
 };
 
+
 /* P1 message block paremeter for training firmware */
-static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
 	{ 0xd0000, 0x0 },
-	{ 0x54000, 0x0 },
-	{ 0x54001, 0x0 },
 	{ 0x54002, 0x1 },
 	{ 0x54003, 0x29c },
 	{ 0x54004, 0x2 },
-	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
-	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
-	{ 0x54007, 0x0 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
 	{ 0x54008, 0x121f },
 	{ 0x54009, 0xc8 },
-	{ 0x5400a, 0x0 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400c, 0x0 },
-	{ 0x5400d, 0x0 },
-	{ 0x5400e, 0x0 },
-	{ 0x5400f, 0x0 },
-	{ 0x54010, 0x0 },
-	{ 0x54011, 0x0 },
 	{ 0x54012, 0x310 },
-	{ 0x54013, 0x0 },
-	{ 0x54014, 0x0 },
-	{ 0x54015, 0x0 },
-	{ 0x54016, 0x0 },
-	{ 0x54017, 0x0 },
-	{ 0x54018, 0x0 },
-	{ 0x54019, 0x914 },
-	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
-	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
-		    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
-	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
-	{ 0x5401e, 0x6 },
-	{ 0x5401f, 0x914 },
-	{ 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
-	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
-		    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
-	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
-	{ 0x54023, 0x0 },
-	{ 0x54024, LPDDR4_MR22_RANK1 },
-	{ 0x54025, 0x0 },
-	{ 0x54026, 0x0 },
-	{ 0x54027, 0x0 },
-	{ 0x54028, 0x0 },
-	{ 0x54029, 0x0 },
-	{ 0x5402a, 0x0 },
+	{ 0x54019, 0x994 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x994 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x3 },
-	{ 0x5402d, 0x0 },
-	{ 0x5402e, 0x0 },
-	{ 0x5402f, 0x0 },
-	{ 0x54030, 0x0 },
-	{ 0x54031, 0x0 },
-	{ 0x54032, 0x1400 },
-	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 },
-	{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
-	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
-	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
-	{ 0x54037, 0x600 },
-	{ 0x54038, 0x1400 },
-	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 },
-	{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
-	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
-	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
-	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
-	{ 0x5403e, 0x0 },
-	{ 0x5403f, 0x0 },
-	{ 0x54040, 0x0 },
-	{ 0x54041, 0x0 },
-	{ 0x54042, 0x0 },
-	{ 0x54043, 0x0 },
+	{ 0x54032, 0x9400 },
+	{ 0x54033, 0x3109 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x9400 },
+	{ 0x54039, 0x3109 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
 	{ 0xd0000, 0x1 },
-
 };
 
+
 /* P0 2D message block paremeter for training firmware */
-static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
 	{ 0xd0000, 0x0 },
-	{ 0x54000, 0x0 },
-	{ 0x54001, 0x0 },
-	{ 0x54002, 0x0 },
 	{ 0x54003, 0xc80 },
 	{ 0x54004, 0x2 },
-	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
-	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
-	{ 0x54007, 0x0 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x11 },
 	{ 0x54008, 0x61 },
-	{ 0x54009, LPDDR4_HDT_CTL_2D },
-	{ 0x5400a, 0x0 },
+	{ 0x54009, 0xc8 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400c, 0x0 },
-	{ 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
-	{ 0x5400e, 0x0 },
-	{ 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
-	{ 0x54010, LPDDR4_2D_WEIGHT },
-	{ 0x54011, 0x0 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
 	{ 0x54012, 0x310 },
-	{ 0x54013, 0x0 },
-	{ 0x54014, 0x0 },
-	{ 0x54015, 0x0 },
-	{ 0x54016, 0x0 },
-	{ 0x54017, 0x0 },
-	{ 0x54018, 0x0 },
-	{ 0x54024, 0x5 },
 	{ 0x54019, 0x2dd4 },
-	{ 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
-	{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
-		    (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
-	{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
-	{ 0x5401d, 0x0 },
-	{ 0x5401e, LPDDR4_MR22_RANK0 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x2dd4 },
-	{ 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
-	{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
-		    (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
-	{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
-	{ 0x54023, 0x0 },
-	{ 0x54024, LPDDR4_MR22_RANK1 },
-	{ 0x54025, 0x0 },
-	{ 0x54026, 0x0 },
-	{ 0x54027, 0x0 },
-	{ 0x54028, 0x0 },
-	{ 0x54029, 0x0 },
-	{ 0x5402a, 0x0 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x3 },
-	{ 0x5402d, 0x0 },
-	{ 0x5402e, 0x0 },
-	{ 0x5402f, 0x0 },
-	{ 0x54030, 0x0 },
-	{ 0x54031, 0x0 },
 	{ 0x54032, 0xd400 },
-	{ 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
-	{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
-	{ 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
-	{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
-	{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
 	{ 0x54038, 0xd400 },
-	{ 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
-	{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
-	{ 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
-	{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
-	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
-	{ 0x5403e, 0x0 },
-	{ 0x5403f, 0x0 },
-	{ 0x54040, 0x0 },
-	{ 0x54041, 0x0 },
-	{ 0x54042, 0x0 },
-	{ 0x54043, 0x0 },
-	{ 0x54044, 0x0 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
 	{ 0xd0000, 0x1 },
-
 };
 
 /* DRAM PHY init engine image */
-static struct dram_cfg_param lpddr4_phy_pie[] = {
+static struct dram_cfg_param ddr_phy_pie[] = {
 	{ 0xd0000, 0x0 },
 	{ 0x90000, 0x10 },
 	{ 0x90001, 0x400 },
@@ -574,7 +1135,7 @@ static struct dram_cfg_param lpddr4_phy_pie[] = {
 	{ 0x90035, 0x2 },
 	{ 0x90036, 0x10 },
 	{ 0x90037, 0x139 },
-	{ 0x90038, 0xb },
+	{ 0x90038, 0xf },
 	{ 0x90039, 0x7c0 },
 	{ 0x9003a, 0x139 },
 	{ 0x9003b, 0x44 },
@@ -682,12 +1243,9 @@ static struct dram_cfg_param lpddr4_phy_pie[] = {
 	{ 0x900a1, 0x5 },
 	{ 0x900a2, 0x7c0 },
 	{ 0x900a3, 0x109 },
-	{ 0x900a4, 0xd },
-	{ 0x900a5, 0x7c0 },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x10 },
 	{ 0x900a6, 0x109 },
-	{ 0x900a7, 0x4 },
-	{ 0x900a8, 0x7c0 },
-	{ 0x900a9, 0x109 },
 	{ 0x40000, 0x811 },
 	{ 0x40020, 0x880 },
 	{ 0x40040, 0x0 },
@@ -796,237 +1354,234 @@ static struct dram_cfg_param lpddr4_phy_pie[] = {
 	{ 0x4003a, 0x880 },
 	{ 0x4005a, 0x0 },
 	{ 0x4007a, 0x0 },
-	{ 0x900aa, 0x0 },
-	{ 0x900ab, 0x790 },
-	{ 0x900ac, 0x11a },
-	{ 0x900ad, 0x8 },
-	{ 0x900ae, 0x7aa },
+	{ 0x900a7, 0x0 },
+	{ 0x900a8, 0x790 },
+	{ 0x900a9, 0x11a },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x7aa },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x10 },
+	{ 0x900ae, 0x7b2 },
 	{ 0x900af, 0x2a },
-	{ 0x900b0, 0x10 },
-	{ 0x900b1, 0x7b2 },
-	{ 0x900b2, 0x2a },
-	{ 0x900b3, 0x0 },
-	{ 0x900b4, 0x7c8 },
-	{ 0x900b5, 0x109 },
-	{ 0x900b6, 0x10 },
-	{ 0x900b7, 0x10 },
-	{ 0x900b8, 0x109 },
-	{ 0x900b9, 0x10 },
-	{ 0x900ba, 0x2a8 },
-	{ 0x900bb, 0x129 },
-	{ 0x900bc, 0x8 },
-	{ 0x900bd, 0x370 },
-	{ 0x900be, 0x129 },
-	{ 0x900bf, 0xa },
-	{ 0x900c0, 0x3c8 },
-	{ 0x900c1, 0x1a9 },
-	{ 0x900c2, 0xc },
-	{ 0x900c3, 0x408 },
-	{ 0x900c4, 0x199 },
-	{ 0x900c5, 0x14 },
-	{ 0x900c6, 0x790 },
-	{ 0x900c7, 0x11a },
+	{ 0x900b0, 0x0 },
+	{ 0x900b1, 0x7c8 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
 	{ 0x900c8, 0x8 },
-	{ 0x900c9, 0x4 },
-	{ 0x900ca, 0x18 },
-	{ 0x900cb, 0xe },
-	{ 0x900cc, 0x408 },
-	{ 0x900cd, 0x199 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
 	{ 0x900ce, 0x8 },
-	{ 0x900cf, 0x8568 },
-	{ 0x900d0, 0x108 },
-	{ 0x900d1, 0x18 },
-	{ 0x900d2, 0x790 },
-	{ 0x900d3, 0x16a },
-	{ 0x900d4, 0x8 },
-	{ 0x900d5, 0x1d8 },
-	{ 0x900d6, 0x169 },
-	{ 0x900d7, 0x10 },
-	{ 0x900d8, 0x8558 },
-	{ 0x900d9, 0x168 },
-	{ 0x900da, 0x70 },
-	{ 0x900db, 0x788 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
 	{ 0x900dc, 0x16a },
-	{ 0x900dd, 0x1ff8 },
-	{ 0x900de, 0x85a8 },
-	{ 0x900df, 0x1e8 },
-	{ 0x900e0, 0x50 },
-	{ 0x900e1, 0x798 },
-	{ 0x900e2, 0x16a },
-	{ 0x900e3, 0x60 },
-	{ 0x900e4, 0x7a0 },
-	{ 0x900e5, 0x16a },
-	{ 0x900e6, 0x8 },
-	{ 0x900e7, 0x8310 },
-	{ 0x900e8, 0x168 },
-	{ 0x900e9, 0x8 },
-	{ 0x900ea, 0xa310 },
-	{ 0x900eb, 0x168 },
-	{ 0x900ec, 0xa },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
 	{ 0x900ed, 0x408 },
 	{ 0x900ee, 0x169 },
-	{ 0x900ef, 0x6e },
-	{ 0x900f0, 0x0 },
-	{ 0x900f1, 0x68 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
 	{ 0x900f2, 0x0 },
-	{ 0x900f3, 0x408 },
-	{ 0x900f4, 0x169 },
-	{ 0x900f5, 0x0 },
-	{ 0x900f6, 0x8310 },
-	{ 0x900f7, 0x168 },
-	{ 0x900f8, 0x0 },
-	{ 0x900f9, 0xa310 },
-	{ 0x900fa, 0x168 },
-	{ 0x900fb, 0x1ff8 },
-	{ 0x900fc, 0x85a8 },
-	{ 0x900fd, 0x1e8 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
 	{ 0x900fe, 0x68 },
-	{ 0x900ff, 0x798 },
+	{ 0x900ff, 0x790 },
 	{ 0x90100, 0x16a },
-	{ 0x90101, 0x78 },
-	{ 0x90102, 0x7a0 },
-	{ 0x90103, 0x16a },
-	{ 0x90104, 0x68 },
-	{ 0x90105, 0x790 },
-	{ 0x90106, 0x16a },
-	{ 0x90107, 0x8 },
-	{ 0x90108, 0x8b10 },
-	{ 0x90109, 0x168 },
-	{ 0x9010a, 0x8 },
-	{ 0x9010b, 0xab10 },
-	{ 0x9010c, 0x168 },
-	{ 0x9010d, 0xa },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
 	{ 0x9010e, 0x408 },
 	{ 0x9010f, 0x169 },
-	{ 0x90110, 0x58 },
-	{ 0x90111, 0x0 },
-	{ 0x90112, 0x68 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
 	{ 0x90113, 0x0 },
-	{ 0x90114, 0x408 },
-	{ 0x90115, 0x169 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
 	{ 0x90116, 0x0 },
-	{ 0x90117, 0x8b10 },
-	{ 0x90118, 0x168 },
-	{ 0x90119, 0x0 },
-	{ 0x9011a, 0xab10 },
-	{ 0x9011b, 0x168 },
-	{ 0x9011c, 0x0 },
-	{ 0x9011d, 0x1d8 },
-	{ 0x9011e, 0x169 },
-	{ 0x9011f, 0x80 },
-	{ 0x90120, 0x790 },
-	{ 0x90121, 0x16a },
-	{ 0x90122, 0x18 },
-	{ 0x90123, 0x7aa },
-	{ 0x90124, 0x6a },
-	{ 0x90125, 0xa },
-	{ 0x90126, 0x0 },
-	{ 0x90127, 0x1e9 },
-	{ 0x90128, 0x8 },
-	{ 0x90129, 0x8080 },
-	{ 0x9012a, 0x108 },
-	{ 0x9012b, 0xf },
-	{ 0x9012c, 0x408 },
-	{ 0x9012d, 0x169 },
-	{ 0x9012e, 0xc },
-	{ 0x9012f, 0x0 },
-	{ 0x90130, 0x68 },
-	{ 0x90131, 0x9 },
-	{ 0x90132, 0x0 },
-	{ 0x90133, 0x1a9 },
-	{ 0x90134, 0x0 },
-	{ 0x90135, 0x408 },
-	{ 0x90136, 0x169 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
 	{ 0x90137, 0x0 },
-	{ 0x90138, 0x8080 },
+	{ 0x90138, 0x8568 },
 	{ 0x90139, 0x108 },
-	{ 0x9013a, 0x8 },
-	{ 0x9013b, 0x7aa },
-	{ 0x9013c, 0x6a },
-	{ 0x9013d, 0x0 },
-	{ 0x9013e, 0x8568 },
-	{ 0x9013f, 0x108 },
-	{ 0x90140, 0xb7 },
-	{ 0x90141, 0x790 },
-	{ 0x90142, 0x16a },
-	{ 0x90143, 0x1f },
-	{ 0x90144, 0x0 },
-	{ 0x90145, 0x68 },
-	{ 0x90146, 0x8 },
-	{ 0x90147, 0x8558 },
-	{ 0x90148, 0x168 },
-	{ 0x90149, 0xf },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xc },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
 	{ 0x9014a, 0x408 },
 	{ 0x9014b, 0x169 },
-	{ 0x9014c, 0xc },
-	{ 0x9014d, 0x0 },
-	{ 0x9014e, 0x68 },
-	{ 0x9014f, 0x0 },
-	{ 0x90150, 0x408 },
-	{ 0x90151, 0x169 },
-	{ 0x90152, 0x0 },
-	{ 0x90153, 0x8558 },
-	{ 0x90154, 0x168 },
-	{ 0x90155, 0x8 },
-	{ 0x90156, 0x3c8 },
-	{ 0x90157, 0x1a9 },
-	{ 0x90158, 0x3 },
-	{ 0x90159, 0x370 },
-	{ 0x9015a, 0x129 },
-	{ 0x9015b, 0x20 },
-	{ 0x9015c, 0x2aa },
-	{ 0x9015d, 0x9 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x0 },
+	{ 0x90159, 0x400 },
+	{ 0x9015a, 0x10e },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
 	{ 0x9015e, 0x0 },
-	{ 0x9015f, 0x400 },
-	{ 0x90160, 0x10e },
-	{ 0x90161, 0x8 },
-	{ 0x90162, 0xe8 },
-	{ 0x90163, 0x109 },
-	{ 0x90164, 0x0 },
-	{ 0x90165, 0x8140 },
-	{ 0x90166, 0x10c },
-	{ 0x90167, 0x10 },
-	{ 0x90168, 0x8138 },
-	{ 0x90169, 0x10c },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x10c },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x7c8 },
+	{ 0x90166, 0x101 },
+	{ 0x90167, 0x8 },
+	{ 0x90168, 0x0 },
+	{ 0x90169, 0x8 },
 	{ 0x9016a, 0x8 },
-	{ 0x9016b, 0x7c8 },
-	{ 0x9016c, 0x101 },
-	{ 0x9016d, 0x8 },
-	{ 0x9016e, 0x0 },
-	{ 0x9016f, 0x8 },
-	{ 0x90170, 0x8 },
-	{ 0x90171, 0x448 },
+	{ 0x9016b, 0x448 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0xf },
+	{ 0x9016e, 0x7c0 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x0 },
+	{ 0x90171, 0xe8 },
 	{ 0x90172, 0x109 },
-	{ 0x90173, 0xf },
-	{ 0x90174, 0x7c0 },
+	{ 0x90173, 0x47 },
+	{ 0x90174, 0x630 },
 	{ 0x90175, 0x109 },
-	{ 0x90176, 0x0 },
-	{ 0x90177, 0xe8 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x618 },
 	{ 0x90178, 0x109 },
-	{ 0x90179, 0x47 },
-	{ 0x9017a, 0x630 },
+	{ 0x90179, 0x8 },
+	{ 0x9017a, 0xe0 },
 	{ 0x9017b, 0x109 },
-	{ 0x9017c, 0x8 },
-	{ 0x9017d, 0x618 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x7c8 },
 	{ 0x9017e, 0x109 },
 	{ 0x9017f, 0x8 },
-	{ 0x90180, 0xe0 },
-	{ 0x90181, 0x109 },
+	{ 0x90180, 0x8140 },
+	{ 0x90181, 0x10c },
 	{ 0x90182, 0x0 },
-	{ 0x90183, 0x7c8 },
-	{ 0x90184, 0x109 },
+	{ 0x90183, 0x1 },
+	{ 0x90184, 0x8 },
 	{ 0x90185, 0x8 },
-	{ 0x90186, 0x8140 },
-	{ 0x90187, 0x10c },
-	{ 0x90188, 0x0 },
-	{ 0x90189, 0x1 },
-	{ 0x9018a, 0x8 },
-	{ 0x9018b, 0x8 },
-	{ 0x9018c, 0x4 },
-	{ 0x9018d, 0x8 },
-	{ 0x9018e, 0x8 },
-	{ 0x9018f, 0x7c8 },
-	{ 0x90190, 0x101 },
+	{ 0x90186, 0x4 },
+	{ 0x90187, 0x8 },
+	{ 0x90188, 0x8 },
+	{ 0x90189, 0x7c8 },
+	{ 0x9018a, 0x101 },
 	{ 0x90006, 0x0 },
 	{ 0x90007, 0x0 },
 	{ 0x90008, 0x8 },
@@ -1035,8 +1590,8 @@ static struct dram_cfg_param lpddr4_phy_pie[] = {
 	{ 0x9000b, 0x0 },
 	{ 0xd00e7, 0x400 },
 	{ 0x90017, 0x0 },
-	{ 0x9001f, 0x2b },
-	{ 0x90026, 0x6c },
+	{ 0x9001f, 0x2a },
+	{ 0x90026, 0x6a },
 	{ 0x400d0, 0x0 },
 	{ 0x400d1, 0x101 },
 	{ 0x400d2, 0x105 },
@@ -1054,10 +1609,6 @@ static struct dram_cfg_param lpddr4_phy_pie[] = {
 	{ 0x12000c, 0x29 },
 	{ 0x12000d, 0x1a1 },
 	{ 0x12000e, 0x10 },
-	{ 0x22000b, 0x3 },
-	{ 0x22000c, 0x6 },
-	{ 0x22000d, 0x3e },
-	{ 0x22000e, 0x10 },
 	{ 0x9000c, 0x0 },
 	{ 0x9000d, 0x173 },
 	{ 0x9000e, 0x60 },
@@ -1068,6 +1619,8 @@ static struct dram_cfg_param lpddr4_phy_pie[] = {
 	{ 0x90013, 0x6152 },
 	{ 0x20010, 0x5a },
 	{ 0x20011, 0x3 },
+	{ 0x120010, 0x5a },
+	{ 0x120011, 0x3 },
 	{ 0x40080, 0xe0 },
 	{ 0x40081, 0x12 },
 	{ 0x40082, 0xe0 },
@@ -1080,12 +1633,6 @@ static struct dram_cfg_param lpddr4_phy_pie[] = {
 	{ 0x140083, 0x12 },
 	{ 0x140084, 0xe0 },
 	{ 0x140085, 0x12 },
-	{ 0x240080, 0xe0 },
-	{ 0x240081, 0x12 },
-	{ 0x240082, 0xe0 },
-	{ 0x240083, 0x12 },
-	{ 0x240084, 0xe0 },
-	{ 0x240085, 0x12 },
 	{ 0x400fd, 0xf },
 	{ 0x10011, 0x1 },
 	{ 0x10012, 0x1 },
@@ -1143,49 +1690,47 @@ static struct dram_cfg_param lpddr4_phy_pie[] = {
 	{ 0x136b4, 0x1 },
 	{ 0x137b4, 0x1 },
 	{ 0x138b4, 0x1 },
-	{ 0x20089, 0x1 },
-	{ 0x20088, 0x19 },
+	{ 0x2003a, 0x2 },
 	{ 0xc0080, 0x2 },
-	{ 0xd0000, 0x1 },
+	{ 0xd0000, 0x1 }
 };
 
-static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
 	{
 		/* P0 3200mts 1D */
 		.drate = 3200,
 		.fw_type = FW_1D_IMAGE,
-		.fsp_cfg = lpddr4_fsp0_cfg,
-		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
 	},
 	{
 		/* P1 667mts 1D */
 		.drate = 667,
 		.fw_type = FW_1D_IMAGE,
-		.fsp_cfg = lpddr4_fsp1_cfg,
-		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
 	},
 	{
 		/* P0 3200mts 2D */
 		.drate = 3200,
 		.fw_type = FW_2D_IMAGE,
-		.fsp_cfg = lpddr4_fsp0_2d_cfg,
-		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
 	},
 };
 
-/* lpddr4 timing config params on EVK board */
+/* ddr timing config params */
 struct dram_timing_info dram_timing_b0 = {
-	.ddrc_cfg = lpddr4_ddrc_cfg,
-	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
-	.ddrphy_cfg = lpddr4_ddrphy_cfg,
-	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
-	.fsp_msg = lpddr4_dram_fsp_msg,
-	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
-	.ddrphy_pie = lpddr4_phy_pie,
-	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
-	/*
-	 * this table must be initialized if DDRPHY bypass mode is
-	 * not used: all fsp drate > 666MTS.
-	 */
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
 	.fsp_table = { 3200, 667, },
 };
+
diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c
index 67d069b2b05..3632e535444 100644
--- a/board/freescale/imx8mq_evk/spl.c
+++ b/board/freescale/imx8mq_evk/spl.c
@@ -1,11 +1,11 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
+#include <cpu_func.h>
 #include <hang.h>
 #include <image.h>
 #include <init.h>
@@ -22,12 +22,16 @@
 #include <asm/mach-imx/gpio.h>
 #include <asm/mach-imx/mxc_i2c.h>
 #include <fsl_esdhc_imx.h>
+#include <fsl_sec.h>
 #include <mmc.h>
 #include <linux/delay.h>
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 #include <spl.h>
 #include "../common/pfuze.h"
+#include <asm/arch/imx8mq_sec_def.h>
+#include <asm/arch/imx8m_csu.h>
+#include <asm/arch/imx8m_rdc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -125,7 +129,7 @@ int board_mmc_init(struct bd_info *bis)
 		switch (i) {
 		case 0:
 			init_clk_usdhc(0);
-			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 			imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
 							 ARRAY_SIZE(usdhc1_pads));
 			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
@@ -135,7 +139,7 @@ int board_mmc_init(struct bd_info *bis)
 			break;
 		case 1:
 			init_clk_usdhc(1);
-			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
 							 ARRAY_SIZE(usdhc2_pads));
 			gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
@@ -199,6 +203,21 @@ int power_init_board(void)
 
 void spl_board_init(void)
 {
+	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+		if (sec_init())
+			printf("\nsec_init failed!\n");
+	}
+
+#ifndef CONFIG_SPL_USB_SDP_SUPPORT
+	/* Serial download mode */
+	if (is_usb_boot()) {
+		puts("Back to ROM, SDP\n");
+		restore_boot_params();
+	}
+#endif
+
+	init_usb_clk();
+
 	puts("Normal Boot\n");
 }
 
@@ -212,12 +231,30 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
+#define GPR_PCIE_VREG_BYPASS	BIT(12)
+static void enable_pcie_vreg(bool enable)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	if (!enable) {
+		setbits_le32(&gpr->gpr[14], GPR_PCIE_VREG_BYPASS);
+		setbits_le32(&gpr->gpr[16], GPR_PCIE_VREG_BYPASS);
+	} else {
+		clrbits_le32(&gpr->gpr[14], GPR_PCIE_VREG_BYPASS);
+		clrbits_le32(&gpr->gpr[16], GPR_PCIE_VREG_BYPASS);
+	}
+}
+
 void board_init_f(ulong dummy)
 {
 	int ret;
 
-	/* Clear global data */
-	memset((void *)gd, 0, sizeof(gd_t));
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* PCIE_VPH connects to 3.3v on EVK, enable VREG to generate 1.8V to PHY */
+	enable_pcie_vreg(true);
 
 	arch_cpu_init();
 
@@ -229,9 +266,6 @@ void board_init_f(ulong dummy)
 
 	preloader_console_init();
 
-	/* Clear the BSS. */
-	memset(__bss_start, 0, __bss_end - __bss_start);
-
 	ret = spl_init();
 	if (ret) {
 		debug("spl_init() failed: %d\n", ret);
@@ -249,3 +283,53 @@ void board_init_f(ulong dummy)
 
 	board_init_r(NULL, 0);
 }
+
+#ifdef CONFIG_ANDROID_SUPPORT
+void spl_board_prepare_for_boot(void)
+{
+	uint32_t val;
+	struct imx_csu_cfg csu_cfg[] = {
+		/* peripherals csl setting */
+		CSU_CSLx(CSU_CSL_OCRAM, CSU_SEC_LEVEL_2, LOCKED),
+		CSU_CSLx(CSU_CSL_OCRAM_S, CSU_SEC_LEVEL_2, LOCKED),
+		CSU_CSLx(CSU_CSL_RDC, CSU_SEC_LEVEL_3, LOCKED),
+		CSU_CSLx(CSU_CSL_TZASC, CSU_SEC_LEVEL_4, LOCKED),
+
+		/* SA setting */
+		CSU_SA(CSU_SA_M4, 1, LOCKED),
+		CSU_SA(CSU_SA_SDMA1, 1, LOCKED),
+		CSU_SA(CSU_SA_LCDIF, 1, LOCKED),
+		CSU_SA(CSU_SA_USB, 1, LOCKED),
+		CSU_SA(CSU_SA_PCIE_CTRL, 1, LOCKED),
+		CSU_SA(CSU_SA_VPU_DECODER, 1, LOCKED),
+		CSU_SA(CSU_SA_GPU, 1, LOCKED),
+		CSU_SA(CSU_SA_ENET1, 1, LOCKED),
+		CSU_SA(CSU_SA_USDHC1, 1, LOCKED),
+		CSU_SA(CSU_SA_USDHC2, 1, LOCKED),
+		CSU_SA(CSU_SA_DISPLAY_CONTROLLER, 1, LOCKED),
+		CSU_SA(CSU_SA_HUGO, 1, LOCKED),
+		CSU_SA(CSU_SA_DAP, 1, LOCKED),
+		CSU_SA(CSU_SA_SDMA2, 1, LOCKED),
+#ifdef CONFIG_IMX_TRUSTY_OS
+		CSU_CSLx(CSU_CSL_VPU_SEC, CSU_SEC_LEVEL_5, LOCKED),
+#endif
+		{0}
+	};
+
+	struct imx_rdc_cfg rdc_cfg[] = {
+		RDC_MDAn(RDC_MDA_DCSS, DID2),
+		{0},
+	};
+
+	/* csu config */
+	imx_csu_init(csu_cfg);
+
+	/* rdc config */
+	imx_rdc_init(rdc_cfg);
+
+	/* config the ocram memory range for secure access */
+	setbits_le32(IOMUXC_GPR_BASE_ADDR + 0x2c, 0x421);
+	val = readl(IOMUXC_GPR_BASE_ADDR + 0x2c);
+	setbits_le32(IOMUXC_GPR_BASE_ADDR + 0x2c, val | 0x3C3F0000);
+}
+#endif
diff --git a/board/freescale/imx8mq_val/Kconfig b/board/freescale/imx8mq_val/Kconfig
new file mode 100644
index 00000000000..0b74a66fe99
--- /dev/null
+++ b/board/freescale/imx8mq_val/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX8MQ_DDR3L_VAL || TARGET_IMX8MQ_DDR4_VAL
+
+config SYS_BOARD
+	default "imx8mq_val"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx8mq_val"
+
+config IMX_CONFIG
+	default "arch/arm/mach-imx/imx8m/imximage.cfg"
+
+endif
diff --git a/board/freescale/imx8mq_val/Makefile b/board/freescale/imx8mq_val/Makefile
new file mode 100644
index 00000000000..3681638bd7f
--- /dev/null
+++ b/board/freescale/imx8mq_val/Makefile
@@ -0,0 +1,17 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mq_val.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += ddr/helper.o
+ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL
+obj-y += ddr/ddr3l/ddr_init.o ddr/ddr3l/ddrphy_train.o
+else
+obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
+endif
+endif
diff --git a/board/freescale/imx8mq_val/ddr/ddr.h b/board/freescale/imx8mq_val/ddr/ddr.h
new file mode 100644
index 00000000000..b42b04c1ebe
--- /dev/null
+++ b/board/freescale/imx8mq_val/ddr/ddr.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef SRC_DDRC_RCR_ADDR
+#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000
+#endif
+#ifndef DDR_CSD1_BASE_ADDR
+#define DDR_CSD1_BASE_ADDR 0x40000000
+#endif
+
+void ddr_load_train_code(enum fw_type type);
+int wait_ddrphy_training_complete(void);
+void ddr3_phyinit_train_1600mts(void);
+void ddr4_phyinit_train_2400mts(void);
diff --git a/board/freescale/imx8mq_val/ddr/ddr3l/ddr_init.c b/board/freescale/imx8mq_val/ddr/ddr3l/ddr_init.c
new file mode 100644
index 00000000000..0dfbb4a4a00
--- /dev/null
+++ b/board/freescale/imx8mq_val/ddr/ddr3l/ddr_init.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/clock.h>
+#include "../ddr.h"
+
+#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG
+#define ddr_printf(args...) printf(args)
+#else
+#define ddr_printf(args...)
+#endif
+
+#include "../wait_ddrphy_training_complete.c"
+
+static inline void reg32clrbit(unsigned long addr, u32 bit)
+{
+	clrbits_le32(addr, (1 << bit));
+}
+
+volatile unsigned int tmp;
+void umctl2_cfg(void){
+	reg32_write(DDRC_DBG1(0), 0x00000001);
+	reg32_write(DDRC_PWRCTL(0), 0x00000001);
+	do{
+	  tmp = 0x7 & (reg32_read(DDRC_STAT(0)));
+	} while (tmp);/* wait init state */
+
+	reg32_write(DDRC_MSTR(0), 0x83040001);/* two rank */
+
+	reg32_write(DDRC_MRCTRL0(0), 0x40004030);
+	reg32_write(DDRC_MRCTRL1(0), 0x0001c68e);
+	reg32_write(DDRC_MRCTRL2(0), 0x921b7e95);
+	reg32_write(DDRC_DERATEEN(0), 0x00000506);
+	reg32_write(DDRC_DERATEINT(0), 0x9a4fbdf1);
+	reg32_write(DDRC_MSTR2(0), 0x00000001);
+	reg32_write(DDRC_PWRCTL(0), 0x000000a8);
+	reg32_write(DDRC_PWRTMG(0), 0x00532203);
+	reg32_write(DDRC_HWLPCTL(0), 0x0b6d0000);
+	reg32_write(DDRC_HWFFCCTL(0), 0x00000030);
+	reg32_write(DDRC_RFSHCTL0(0), 0x00203020);
+	reg32_write(DDRC_RFSHCTL1(0), 0x0001000d);
+	reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
+	reg32_write(DDRC_RFSHTMG(0), 0x0061008c);
+	reg32_write(DDRC_CRCPARCTL0(0), 0x00000000);
+	reg32_write(DDRC_CRCPARCTL1(0), 0x00000000);
+	reg32_write(DDRC_INIT0(0), 0xc0030002);
+	reg32_write(DDRC_INIT1(0), 0x0001000b);
+	reg32_write(DDRC_INIT2(0), 0x00006303);
+	reg32_write(DDRC_INIT3(0), 0x0d700044);/* MR1, MR0 */
+	reg32_write(DDRC_INIT4(0), 0x00180000);/* MR2 */
+	reg32_write(DDRC_INIT5(0), 0x00090071);
+	reg32_write(DDRC_INIT6(0), 0x00000000);
+	reg32_write(DDRC_INIT7(0), 0x00000000);
+	reg32_write(DDRC_DIMMCTL(0), 0x00000032);
+	reg32_write(DDRC_RANKCTL(0), 0x00000ee5);
+	reg32_write(DDRC_DRAMTMG0(0), 0x0c101a0e);
+	reg32_write(DDRC_DRAMTMG1(0), 0x000a0314);
+	reg32_write(DDRC_DRAMTMG2(0), 0x04060509);
+	reg32_write(DDRC_DRAMTMG3(0), 0x00002006);
+	reg32_write(DDRC_DRAMTMG4(0), 0x06020306);
+	reg32_write(DDRC_DRAMTMG5(0), 0x0b060202);
+	reg32_write(DDRC_DRAMTMG6(0), 0x060a0009);
+	reg32_write(DDRC_DRAMTMG7(0), 0x0000060b);
+	reg32_write(DDRC_DRAMTMG8(0), 0x01017c0a);
+	reg32_write(DDRC_DRAMTMG9(0), 0x4000000e);
+	reg32_write(DDRC_DRAMTMG10(0), 0x00070803);
+	reg32_write(DDRC_DRAMTMG11(0), 0x0101000b);
+	reg32_write(DDRC_DRAMTMG12(0), 0x00000000);
+	reg32_write(DDRC_DRAMTMG13(0), 0x5d000000);
+	reg32_write(DDRC_DRAMTMG14(0), 0x00000b39);
+	reg32_write(DDRC_DRAMTMG15(0), 0x80000000);
+	reg32_write(DDRC_DRAMTMG17(0), 0x00f1006a);
+	reg32_write(DDRC_ZQCTL0(0), 0x50800020);
+	reg32_write(DDRC_ZQCTL1(0), 0x00000070);
+	reg32_write(DDRC_ZQCTL2(0), 0x00000000);
+	reg32_write(DDRC_DFITMG0(0), 0x03868203);
+	reg32_write(DDRC_DFITMG1(0), 0x00020103);
+	reg32_write(DDRC_DFILPCFG0(0), 0x07713121);
+	reg32_write(DDRC_DFILPCFG1(0), 0x00000010);
+	reg32_write(DDRC_DFIUPD0(0), 0xe0400018);
+	reg32_write(DDRC_DFIUPD1(0), 0x0005003c);
+	reg32_write(DDRC_DFIUPD2(0), 0x00000000);
+	reg32_write(DDRC_DFIMISC(0), 0x00000011);
+	reg32_write(DDRC_DFITMG2(0), 0x00000603);
+	reg32_write(DDRC_DFITMG3(0), 0x00000001);
+	reg32_write(DDRC_DBICTL(0), 0x00000001);
+	reg32_write(DDRC_DFIPHYMSTR(0), 0x00000000);
+
+	reg32_write(DDRC_ADDRMAP0(0), 0x00000016); /* [4:0] cs-bit0: 6+22=28; [12:8] cs-bit1: 7+0 */
+	reg32_write(DDRC_ADDRMAP1(0), 0x00080808); /* [5:0] bank b0: 2+8; [13:8] b1: P3+8 ; [21:16] b2: 4+8 */
+	reg32_write(DDRC_ADDRMAP2(0), 0x00000000); /* [3:0] col-b2: 2;  [11:8] col-b3: 3; [19:16] col-b4: 4 ; [27:24] col-b5: 5 */
+	reg32_write(DDRC_ADDRMAP3(0), 0x00000000); /* [3:0] col-b6: 6;  [11:8] col-b7: 7; [19:16] col-b8: 8 ; [27:24] col-b9: 9 */
+	reg32_write(DDRC_ADDRMAP4(0), 0x00001f1f); /* col-b10, col-b11 not used */
+	reg32_write(DDRC_ADDRMAP5(0), 0x07070707); /* [3:0] row-b0: 6;  [11:8] row-b1: 7; [19:16] row-b2_b10 ; [27:24] row-b11: 17 */
+	reg32_write(DDRC_ADDRMAP6(0), 0x0f070707); /* [3:0] row-b12:18; [11:8] row-b13: 19; [19:16] row-b14:20 */
+	reg32_write(DDRC_ADDRMAP7(0), 0x00000f0f);
+	reg32_write(DDRC_ADDRMAP8(0), 0x00000000); /* [5:0] bg-b0; [13:8]bg-b1 */
+	reg32_write(DDRC_ADDRMAP9(0), 0x0a020b06); /*  it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
+	reg32_write(DDRC_ADDRMAP10(0), 0x0a0a0a0a);/*  it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */
+	reg32_write(DDRC_ADDRMAP11(0), 0x00000000);
+
+
+	reg32_write(DDRC_ODTCFG(0), 0x041d0f5c);
+	reg32_write(DDRC_ODTMAP(0), 0x00000201);
+	reg32_write(DDRC_SCHED(0), 0x7ab50b07);
+	reg32_write(DDRC_SCHED1(0), 0x00000022);
+	reg32_write(DDRC_PERFHPR1(0), 0x7b00665e);
+	reg32_write(DDRC_PERFLPR1(0), 0x2b00c4e1);
+	reg32_write(DDRC_PERFWR1(0), 0xb700c9fe);
+	reg32_write(DDRC_DBG0(0), 0x00000017);
+	reg32_write(DDRC_DBG1(0), 0x00000000);
+	reg32_write(DDRC_DBGCMD(0), 0x00000000);
+	reg32_write(DDRC_SWCTL(0), 0x00000001);
+	reg32_write(DDRC_POISONCFG(0), 0x00010000);
+	reg32_write(DDRC_PCCFG(0), 0x00000100);
+	reg32_write(DDRC_PCFGR_0(0), 0x00003051);
+	reg32_write(DDRC_PCFGW_0(0), 0x000061d2);
+	reg32_write(DDRC_PCTRL_0(0), 0x00000001);
+	reg32_write(DDRC_PCFGQOS0_0(0), 0x02100b04);
+	reg32_write(DDRC_PCFGQOS1_0(0), 0x003f0353);
+	reg32_write(DDRC_PCFGWQOS0_0(0), 0x00000002);
+	reg32_write(DDRC_PCFGWQOS1_0(0), 0x000005fd);
+}
+
+int ddr_init(struct dram_timing_info *timing_info)
+{
+	/* change the clock source of dram_apb_clk_root  */
+	clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
+		     CLK_ROOT_SOURCE_SEL(4) |
+		     CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
+
+	/* disable the clock gating */
+	reg32_write(0x303A00EC,0x0000ffff);
+	reg32setbit(0x303A00F8,5);
+	reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
+
+	dram_pll_init(MHZ(400));
+
+	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
+
+	/* Configure uMCTL2's registers */
+	umctl2_cfg();
+
+	reg32setbit(DDRC_RFSHCTL3(0),0); /* dis_auto_refresh */
+	reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
+
+	ddr_load_train_code(FW_1D_IMAGE);
+
+	reg32_write(DDRC_DBG1(0), 0x00000000); /* ('b00000000_00000000_00000000_00000000) ('d0) */
+	reg32setbit(DDRC_PWRCTL(0),5); /* selfref_sw=1, self-refresh */
+	reg32clrbit(DDRC_SWCTL(0), 0); /* sw_done=0, enable quasi-dynamic programming */
+	reg32_write(DDRC_DFIMISC(0), 0x00000000);
+
+	/* Configure DDR3L PHY's registers */
+	ddr3_phyinit_train_1600mts();
+
+	do {
+		tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0x00020097);
+	} while (tmp != 0);
+
+	reg32setbit(DDRC_DFIMISC(0),5);/* dfi_init_start=1 */
+	do{
+		tmp = 0x1 & (reg32_read(DDRC_DFISTAT(0)));
+	} while (!tmp);/*  wait DFISTAT.dfi_init_complete to 1 */
+
+	reg32clrbit(DDRC_DFIMISC(0),5);/* dfi_init_start=0 */
+	reg32setbit(DDRC_DFIMISC(0),0);/* dfi_init_complete_en=1 */
+
+	reg32clrbit(DDRC_PWRCTL(0),5);/* selfref_sw=0, exit self-refresh */
+
+	reg32setbit(DDRC_SWCTL(0), 0);/* sw_done=1, disable quasi-dynamic programming */
+
+	/* wait SWSTAT.sw_done_ack to 1 */
+	do{
+		tmp = 0x1 & (reg32_read(DDRC_SWSTAT(0)));
+	} while (!tmp);
+
+	/* wait STAT to normal state */
+	do{
+		tmp = 0x7 & (reg32_read(DDRC_STAT(0)));
+	} while (tmp != 0x1);
+
+	reg32_write(DDRC_PCTRL_0(0), 0x00000001); /* enable port 0 */
+
+	reg32clrbit(DDRC_RFSHCTL3(0), 0); /* auto-refresh enable */
+
+	return 0;
+}
diff --git a/board/freescale/imx8mq_val/ddr/ddr3l/ddrphy_train.c b/board/freescale/imx8mq_val/ddr/ddr3l/ddrphy_train.c
new file mode 100644
index 00000000000..066ca7ff4b5
--- /dev/null
+++ b/board/freescale/imx8mq_val/ddr/ddr3l/ddrphy_train.c
@@ -0,0 +1,352 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include "../ddr.h"
+
+#define DDR3_MR1_RTT120_RON40   ((0L << 9) | (1L << 6) | (0L << 2) | (0L << 5) | (0L << 1)) /* RTT(NOM):M[9,6,2]=010:120ohm;Ron:M[5,1]=00:40ohm */
+#define DDR3_MR1_RTT120_RON34   ((0L << 9) | (1L << 6) | (0L << 2) | (0L << 5) | (1L << 1)) /* RTT(NOM):M[9,6,2]=010:120ohm;Ron:M[5,1]=01:34ohm */
+#define DDR3_MR1_RTT60_RON40    ((0L << 9) | (0L << 6) | (1L << 2) | (0L << 5) | (0L << 1)) /* RTT(NOM):M[9,6,2]=001:60ohm;Ron:M[5,1]=00:40ohm */
+#define DDR3_MR1_RTT60_RON34    ((0L << 9) | (0L << 6) | (1L << 2) | (0L << 5) | (1L << 1)) /* RTT(NOM):M[9,6,2]=001:60ohm;Ron:M[5,1]=01:34ohm */
+#define DDR3_MR1_RTT40_RON34    ((0L << 9) | (1L << 6) | (1L << 2) | (0L << 5) | (1L << 1)) /* RTT(NOM):M[9,6,2]=011:40ohm;Ron:M[5,1]=01:34ohm */
+#define DDR3_MR1_RTT_DIS_RON40  ((0L << 9) | (0L << 6) | (0L << 2) | (0L << 5) | (0L << 1)) /* RTT(NOM):M[9,6,2]=000:disable;Ron:M[5,1]=00:40ohm */
+
+#define DDR3_PHY_RON40    40 /* 40ohm */
+#define DDR3_PHY_RON34    34 /* 34ohm */
+
+#define DDR3_PHY_RTT120   120 /* 120ohm */
+#define DDR3_PHY_RTT60    60 /* 60ohm */
+#define DDR3_PHY_RTT40    40 /* 40ohm */
+#define DDR3_PHY_RTT48    48 /* 48ohm */
+
+#define DDR3_RTT_WR_DIS   0UL
+#define DDR3_RTT_WR_60    1UL
+#define DDR3_RTT_WR_120   2UL
+
+#define DDR3_MR1_VAL            DDR3_MR1_RTT120_RON40
+#define DDR3_MR2_RTT_WR_VAL     DDR3_RTT_WR_DIS
+
+#define DDR3_PHY_RON            DDR3_PHY_RON40
+#define DDR3_PHY_RTT            DDR3_PHY_RTT120
+
+
+void ddr3_phyinit_train_1600mts(void){
+	dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0x1005f,0x3ff); /*  DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1015f,0x3ff); /*  DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 */
+	dwc_ddrphy_apb_wr(0x1105f,0x3ff); /*  DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1115f,0x3ff); /*  DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 */
+	dwc_ddrphy_apb_wr(0x1205f,0x3ff); /*  DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1215f,0x3ff); /*  DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 */
+	dwc_ddrphy_apb_wr(0x1305f,0x3ff); /*  DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1315f,0x3ff); /*  DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 */
+
+	dwc_ddrphy_apb_wr(0x55,0x3ff); /*  DWC_DDRPHYA_ANIB0_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x1055,0x3ff); /*  DWC_DDRPHYA_ANIB1_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x2055,0x3ff); /*  DWC_DDRPHYA_ANIB2_ATxSlewRat */
+	dwc_ddrphy_apb_wr(0x3055,0x3ff); /*  DWC_DDRPHYA_ANIB3_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x4055,0xff); /*  DWC_DDRPHYA_ANIB4_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x5055,0xff); /*  DWC_DDRPHYA_ANIB5_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x6055,0x3ff); /*  DWC_DDRPHYA_ANIB6_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x7055,0x3ff); /*  DWC_DDRPHYA_ANIB7_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x8055,0x3ff); /*  DWC_DDRPHYA_ANIB8_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x9055,0x3ff); /*  DWC_DDRPHYA_ANIB9_ATxSlewRate */
+	dwc_ddrphy_apb_wr(0x200c5,0xb); /*  DWC_DDRPHYA_MASTER0_PllCtrl2_p0 */
+	dwc_ddrphy_apb_wr(0x2002e,0x1); /*  DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 */
+
+	dwc_ddrphy_apb_wr(0x20024,0x8); /*  DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 */
+	dwc_ddrphy_apb_wr(0x2003a,0x0); /*  DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */
+	dwc_ddrphy_apb_wr(0x20056,0xa); /*  DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 */
+	dwc_ddrphy_apb_wr(0x1004d,0x208); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1014d,0x208); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 */
+	dwc_ddrphy_apb_wr(0x1104d,0x208); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1114d,0x208); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 */
+	dwc_ddrphy_apb_wr(0x1204d,0x208); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1214d,0x208); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 */
+	dwc_ddrphy_apb_wr(0x1304d,0x208); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 */
+	dwc_ddrphy_apb_wr(0x1314d,0x208); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 */
+	dwc_ddrphy_apb_wr(0x10049,0xe38); /*  DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 */
+	dwc_ddrphy_apb_wr(0x10149,0xe38); /*  DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 */
+	dwc_ddrphy_apb_wr(0x11049,0xe38); /*  DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 */
+	dwc_ddrphy_apb_wr(0x11149,0xe38); /*  DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 */
+	dwc_ddrphy_apb_wr(0x12049,0xe38); /*  DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 */
+	dwc_ddrphy_apb_wr(0x12149,0xe38); /*  DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 */
+	dwc_ddrphy_apb_wr(0x13049,0xe38); /*  DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 */
+	dwc_ddrphy_apb_wr(0x13149,0xe38); /*  DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 */
+	dwc_ddrphy_apb_wr(0x43,0x63); /* DWC_DDRPHYA_ANIB0_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x1043,0x63); /* DWC_DDRPHYA_ANIB1_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x2043,0x63); /* DWC_DDRPHYA_ANIB2_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x3043,0x63); /* DWC_DDRPHYA_ANIB3_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x4043,0x63); /* DWC_DDRPHYA_ANIB4_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x5043,0x63); /* DWC_DDRPHYA_ANIB5_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x6043,0x63); /* DWC_DDRPHYA_ANIB6_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x7043,0x63); /* DWC_DDRPHYA_ANIB7_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x8043,0x63); /* DWC_DDRPHYA_ANIB8_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x9043,0x63); /* DWC_DDRPHYA_ANIB9_ATxImpedance */
+	dwc_ddrphy_apb_wr(0x20018,0x5); /*  DWC_DDRPHYA_MASTER0_DfiMode */
+	dwc_ddrphy_apb_wr(0x20075,0x0); /*  DWC_DDRPHYA_MASTER0_DfiCAMode */
+	dwc_ddrphy_apb_wr(0x20050,0x0); /*  DWC_DDRPHYA_MASTER0_CalDrvStr0 */
+	dwc_ddrphy_apb_wr(0x20008,0x190); /*  DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 */
+	dwc_ddrphy_apb_wr(0x20088,0x9); /*  DWC_DDRPHYA_MASTER0_CalRate */
+	dwc_ddrphy_apb_wr(0x200b2,0xf8); /*  DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 */
+	dwc_ddrphy_apb_wr(0x10043,0x581); /*  DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 */
+	dwc_ddrphy_apb_wr(0x10143,0x581); /*  DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 */
+	dwc_ddrphy_apb_wr(0x11043,0x581); /*  DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 */
+	dwc_ddrphy_apb_wr(0x11143,0x581); /*  DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 */
+	dwc_ddrphy_apb_wr(0x12043,0x581); /*  DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 */
+	dwc_ddrphy_apb_wr(0x12143,0x581); /*  DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 */
+	dwc_ddrphy_apb_wr(0x13043,0x581); /*  DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 */
+	dwc_ddrphy_apb_wr(0x13143,0x581); /*  DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 */
+	dwc_ddrphy_apb_wr(0x200fa,0x1); /*  DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 */
+	dwc_ddrphy_apb_wr(0x20019,0x5); /*  DWC_DDRPHYA_MASTER0_TristateModeCA_p0 */
+	dwc_ddrphy_apb_wr(0x200f0,0x5555); /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */
+	dwc_ddrphy_apb_wr(0x200f1,0x5555); /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat1 */
+	dwc_ddrphy_apb_wr(0x200f2,0x5555); /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat2 */
+	dwc_ddrphy_apb_wr(0x200f3,0x5555); /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat3 */
+	dwc_ddrphy_apb_wr(0x200f4,0x5555); /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat4 */
+	dwc_ddrphy_apb_wr(0x200f5,0x5555); /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat5 */
+	dwc_ddrphy_apb_wr(0x200f6,0x5555); /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat6 */
+	dwc_ddrphy_apb_wr(0x200f7,0xf000); /*  DWC_DDRPHYA_MASTER0_DfiFreqXlat7 */
+	dwc_ddrphy_apb_wr(0x2000b,0x33); /*  DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */
+	dwc_ddrphy_apb_wr(0x2000c,0x65); /*  DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */
+	dwc_ddrphy_apb_wr(0x2000d,0x3e9); /*  DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */
+	dwc_ddrphy_apb_wr(0x2000e,0x2c); /*  DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */
+	dwc_ddrphy_apb_wr(0x20025,0x0); /*  DWC_DDRPHYA_MASTER0_MasterX4Config */
+	dwc_ddrphy_apb_wr(0x2002d,0x0); /*  DWC_DDRPHYA_MASTER0_DMIPinPresent_p0 */
+
+	dwc_ddrphy_apb_wr(0x20060,0x2); /*  DWC_DDRPHYA_MASTER0_MemResetL */
+	dwc_ddrphy_apb_wr(0xd0000,0x0); /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0000,0x1); /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0000,0x0); /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0x54000,0x0);
+	dwc_ddrphy_apb_wr(0x54001,0x0);
+	dwc_ddrphy_apb_wr(0x54002,0x0);
+	dwc_ddrphy_apb_wr(0x54003,0x640);
+	dwc_ddrphy_apb_wr(0x54004,0x2);
+	dwc_ddrphy_apb_wr(0x54005,((DDR3_PHY_RON << 8) | (DDR3_PHY_RTT << 0)));
+	dwc_ddrphy_apb_wr(0x54006,0x13b);
+	dwc_ddrphy_apb_wr(0x54007,0x2000);
+
+	dwc_ddrphy_apb_wr(0x54008,0x303); /* two ranks */
+
+	dwc_ddrphy_apb_wr(0x54009,0x200);
+	dwc_ddrphy_apb_wr(0x5400a,0x0);
+	dwc_ddrphy_apb_wr(0x5400b,0x31f);
+	dwc_ddrphy_apb_wr(0x5400c,0xc8);
+
+	dwc_ddrphy_apb_wr(0x54012,0x1);
+	dwc_ddrphy_apb_wr(0x5402f,0xd70); /* MR0 */
+	dwc_ddrphy_apb_wr(0x54030,DDR3_MR1_VAL); /* MR1=6:Ron=34ohm/Rtt(NOM)=60ohm */
+	dwc_ddrphy_apb_wr(0x54031,(0x18 | (DDR3_MR2_RTT_WR_VAL << 9))); /*MR2 */
+	dwc_ddrphy_apb_wr(0x5403a,0x1221);
+	dwc_ddrphy_apb_wr(0x5403b,0x4884);
+	dwc_ddrphy_apb_wr(0xd0000,0x1); /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0000,0x1); /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0099,0x9); /*  DWC_DDRPHYA_APBONLY0_MicroReset */
+	dwc_ddrphy_apb_wr(0xd0099,0x1); /*  DWC_DDRPHYA_APBONLY0_MicroReset */
+	dwc_ddrphy_apb_wr(0xd0099,0x0); /*  DWC_DDRPHYA_APBONLY0_MicroReset */
+
+	wait_ddrphy_training_complete();
+
+	dwc_ddrphy_apb_wr(0xd0099,0x1); /*  DWC_DDRPHYA_APBONLY0_MicroReset */
+	dwc_ddrphy_apb_wr(0xd0000,0x0); /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0xd0000,0x1); /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+
+	dwc_ddrphy_apb_wr(0xd0000,0x0); /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+	dwc_ddrphy_apb_wr(0x90000,0x10); /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */
+	dwc_ddrphy_apb_wr(0x90001,0x400); /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */
+	dwc_ddrphy_apb_wr(0x90002,0x10e); /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */
+	dwc_ddrphy_apb_wr(0x90003,0x0); /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */
+	dwc_ddrphy_apb_wr(0x90004,0x0); /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */
+	dwc_ddrphy_apb_wr(0x90005,0x8); /*  DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */
+	dwc_ddrphy_apb_wr(0x90029,0xb); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */
+	dwc_ddrphy_apb_wr(0x9002a,0x480); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */
+	dwc_ddrphy_apb_wr(0x9002b,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */
+	dwc_ddrphy_apb_wr(0x9002c,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */
+	dwc_ddrphy_apb_wr(0x9002d,0x448); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */
+	dwc_ddrphy_apb_wr(0x9002e,0x139); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */
+	dwc_ddrphy_apb_wr(0x9002f,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */
+	dwc_ddrphy_apb_wr(0x90030,0x478); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */
+	dwc_ddrphy_apb_wr(0x90031,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */
+	dwc_ddrphy_apb_wr(0x90032,0x2); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */
+	dwc_ddrphy_apb_wr(0x90033,0x10); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */
+	dwc_ddrphy_apb_wr(0x90034,0x139); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */
+	dwc_ddrphy_apb_wr(0x90035,0xf); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */
+	dwc_ddrphy_apb_wr(0x90036,0x7c0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */
+	dwc_ddrphy_apb_wr(0x90037,0x139); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */
+	dwc_ddrphy_apb_wr(0x90038,0x44); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */
+	dwc_ddrphy_apb_wr(0x90039,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */
+	dwc_ddrphy_apb_wr(0x9003a,0x159); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */
+	dwc_ddrphy_apb_wr(0x9003b,0x14f); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */
+	dwc_ddrphy_apb_wr(0x9003c,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */
+	dwc_ddrphy_apb_wr(0x9003d,0x159); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */
+	dwc_ddrphy_apb_wr(0x9003e,0x47); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */
+	dwc_ddrphy_apb_wr(0x9003f,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */
+	dwc_ddrphy_apb_wr(0x90040,0x149); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */
+	dwc_ddrphy_apb_wr(0x90041,0x4f); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */
+	dwc_ddrphy_apb_wr(0x90042,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */
+	dwc_ddrphy_apb_wr(0x90043,0x179); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */
+	dwc_ddrphy_apb_wr(0x90044,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */
+	dwc_ddrphy_apb_wr(0x90045,0xe0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */
+	dwc_ddrphy_apb_wr(0x90046,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */
+	dwc_ddrphy_apb_wr(0x90047,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */
+	dwc_ddrphy_apb_wr(0x90048,0x7c8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */
+	dwc_ddrphy_apb_wr(0x90049,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */
+	dwc_ddrphy_apb_wr(0x9004a,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */
+	dwc_ddrphy_apb_wr(0x9004b,0x1); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */
+	dwc_ddrphy_apb_wr(0x9004c,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */
+	dwc_ddrphy_apb_wr(0x9004d,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */
+	dwc_ddrphy_apb_wr(0x9004e,0x45a); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */
+	dwc_ddrphy_apb_wr(0x9004f,0x9); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */
+	dwc_ddrphy_apb_wr(0x90050,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */
+	dwc_ddrphy_apb_wr(0x90051,0x448); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */
+	dwc_ddrphy_apb_wr(0x90052,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */
+	dwc_ddrphy_apb_wr(0x90053,0x40); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */
+	dwc_ddrphy_apb_wr(0x90054,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */
+	dwc_ddrphy_apb_wr(0x90055,0x179); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */
+	dwc_ddrphy_apb_wr(0x90056,0x1); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */
+	dwc_ddrphy_apb_wr(0x90057,0x618); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */
+	dwc_ddrphy_apb_wr(0x90058,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */
+	dwc_ddrphy_apb_wr(0x90059,0x40c0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */
+	dwc_ddrphy_apb_wr(0x9005a,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */
+	dwc_ddrphy_apb_wr(0x9005b,0x149); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */
+	dwc_ddrphy_apb_wr(0x9005c,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */
+	dwc_ddrphy_apb_wr(0x9005d,0x4); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */
+	dwc_ddrphy_apb_wr(0x9005e,0x48); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */
+	dwc_ddrphy_apb_wr(0x9005f,0x4040); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */
+	dwc_ddrphy_apb_wr(0x90060,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */
+	dwc_ddrphy_apb_wr(0x90061,0x149); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */
+	dwc_ddrphy_apb_wr(0x90062,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */
+	dwc_ddrphy_apb_wr(0x90063,0x4); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */
+	dwc_ddrphy_apb_wr(0x90064,0x48); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */
+	dwc_ddrphy_apb_wr(0x90065,0x40); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */
+	dwc_ddrphy_apb_wr(0x90066,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */
+	dwc_ddrphy_apb_wr(0x90067,0x149); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */
+	dwc_ddrphy_apb_wr(0x90068,0x10); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */
+	dwc_ddrphy_apb_wr(0x90069,0x4); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */
+	dwc_ddrphy_apb_wr(0x9006a,0x18); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */
+	dwc_ddrphy_apb_wr(0x9006b,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */
+	dwc_ddrphy_apb_wr(0x9006c,0x4); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */
+	dwc_ddrphy_apb_wr(0x9006d,0x78); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */
+	dwc_ddrphy_apb_wr(0x9006e,0x549); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */
+	dwc_ddrphy_apb_wr(0x9006f,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */
+	dwc_ddrphy_apb_wr(0x90070,0x159); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */
+	dwc_ddrphy_apb_wr(0x90071,0xd49); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */
+	dwc_ddrphy_apb_wr(0x90072,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */
+	dwc_ddrphy_apb_wr(0x90073,0x159); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */
+	dwc_ddrphy_apb_wr(0x90074,0x94a); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */
+	dwc_ddrphy_apb_wr(0x90075,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */
+	dwc_ddrphy_apb_wr(0x90076,0x159); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */
+	dwc_ddrphy_apb_wr(0x90077,0x441); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */
+	dwc_ddrphy_apb_wr(0x90078,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */
+	dwc_ddrphy_apb_wr(0x90079,0x149); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */
+	dwc_ddrphy_apb_wr(0x9007a,0x42); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */
+	dwc_ddrphy_apb_wr(0x9007b,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */
+	dwc_ddrphy_apb_wr(0x9007c,0x149); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */
+	dwc_ddrphy_apb_wr(0x9007d,0x1); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */
+	dwc_ddrphy_apb_wr(0x9007e,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */
+	dwc_ddrphy_apb_wr(0x9007f,0x149); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */
+	dwc_ddrphy_apb_wr(0x90080,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */
+	dwc_ddrphy_apb_wr(0x90081,0xe0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */
+	dwc_ddrphy_apb_wr(0x90082,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */
+	dwc_ddrphy_apb_wr(0x90083,0xa); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */
+	dwc_ddrphy_apb_wr(0x90084,0x10); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */
+	dwc_ddrphy_apb_wr(0x90085,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */
+	dwc_ddrphy_apb_wr(0x90086,0x9); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */
+	dwc_ddrphy_apb_wr(0x90087,0x3c0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */
+	dwc_ddrphy_apb_wr(0x90088,0x149); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */
+	dwc_ddrphy_apb_wr(0x90089,0x9); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */
+	dwc_ddrphy_apb_wr(0x9008a,0x3c0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */
+	dwc_ddrphy_apb_wr(0x9008b,0x159); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */
+	dwc_ddrphy_apb_wr(0x9008c,0x18); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */
+	dwc_ddrphy_apb_wr(0x9008d,0x10); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */
+	dwc_ddrphy_apb_wr(0x9008e,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */
+	dwc_ddrphy_apb_wr(0x9008f,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */
+	dwc_ddrphy_apb_wr(0x90090,0x3c0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */
+	dwc_ddrphy_apb_wr(0x90091,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */
+	dwc_ddrphy_apb_wr(0x90092,0x18); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */
+	dwc_ddrphy_apb_wr(0x90093,0x4); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */
+	dwc_ddrphy_apb_wr(0x90094,0x48); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */
+	dwc_ddrphy_apb_wr(0x90095,0x18); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */
+	dwc_ddrphy_apb_wr(0x90096,0x4); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */
+	dwc_ddrphy_apb_wr(0x90097,0x58); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */
+	dwc_ddrphy_apb_wr(0x90098,0xa); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */
+	dwc_ddrphy_apb_wr(0x90099,0x10); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */
+	dwc_ddrphy_apb_wr(0x9009a,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */
+	dwc_ddrphy_apb_wr(0x9009b,0x2); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */
+	dwc_ddrphy_apb_wr(0x9009c,0x10); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */
+	dwc_ddrphy_apb_wr(0x9009d,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */
+	dwc_ddrphy_apb_wr(0x9009e,0x7); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */
+	dwc_ddrphy_apb_wr(0x9009f,0x7c0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */
+	dwc_ddrphy_apb_wr(0x900a0,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */
+	dwc_ddrphy_apb_wr(0x900a1,0x10); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */
+	dwc_ddrphy_apb_wr(0x900a2,0x10); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */
+	dwc_ddrphy_apb_wr(0x900a3,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */
+	dwc_ddrphy_apb_wr(0x900a4,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */
+	dwc_ddrphy_apb_wr(0x900a5,0x8140); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */
+	dwc_ddrphy_apb_wr(0x900a6,0x10c); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */
+	dwc_ddrphy_apb_wr(0x900a7,0x10); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */
+	dwc_ddrphy_apb_wr(0x900a8,0x8138); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */
+	dwc_ddrphy_apb_wr(0x900a9,0x10c); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */
+	dwc_ddrphy_apb_wr(0x900aa,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */
+	dwc_ddrphy_apb_wr(0x900ab,0x7c8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */
+	dwc_ddrphy_apb_wr(0x900ac,0x101); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */
+	dwc_ddrphy_apb_wr(0x900ad,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */
+	dwc_ddrphy_apb_wr(0x900ae,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */
+	dwc_ddrphy_apb_wr(0x900af,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */
+	dwc_ddrphy_apb_wr(0x900b0,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */
+	dwc_ddrphy_apb_wr(0x900b1,0x448); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */
+	dwc_ddrphy_apb_wr(0x900b2,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */
+	dwc_ddrphy_apb_wr(0x900b3,0xf); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */
+	dwc_ddrphy_apb_wr(0x900b4,0x7c0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */
+	dwc_ddrphy_apb_wr(0x900b5,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */
+	dwc_ddrphy_apb_wr(0x900b6,0x47); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */
+	dwc_ddrphy_apb_wr(0x900b7,0x630); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */
+	dwc_ddrphy_apb_wr(0x900b8,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */
+	dwc_ddrphy_apb_wr(0x900b9,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */
+	dwc_ddrphy_apb_wr(0x900ba,0x618); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */
+	dwc_ddrphy_apb_wr(0x900bb,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */
+	dwc_ddrphy_apb_wr(0x900bc,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */
+	dwc_ddrphy_apb_wr(0x900bd,0xe0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */
+	dwc_ddrphy_apb_wr(0x900be,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */
+	dwc_ddrphy_apb_wr(0x900bf,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */
+	dwc_ddrphy_apb_wr(0x900c0,0x7c8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */
+	dwc_ddrphy_apb_wr(0x900c1,0x109); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */
+	dwc_ddrphy_apb_wr(0x900c2,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */
+	dwc_ddrphy_apb_wr(0x900c3,0x8140); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */
+	dwc_ddrphy_apb_wr(0x900c4,0x10c); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */
+	dwc_ddrphy_apb_wr(0x900c5,0x0); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */
+	dwc_ddrphy_apb_wr(0x900c6,0x1); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */
+	dwc_ddrphy_apb_wr(0x900c7,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */
+	dwc_ddrphy_apb_wr(0x900c8,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */
+	dwc_ddrphy_apb_wr(0x900c9,0x4); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */
+	dwc_ddrphy_apb_wr(0x900ca,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */
+	dwc_ddrphy_apb_wr(0x900cb,0x8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */
+	dwc_ddrphy_apb_wr(0x900cc,0x7c8); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */
+	dwc_ddrphy_apb_wr(0x900cd,0x101); /*  DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */
+	dwc_ddrphy_apb_wr(0x90006,0x0); /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */
+	dwc_ddrphy_apb_wr(0x90007,0x0); /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */
+	dwc_ddrphy_apb_wr(0x90008,0x8); /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */
+	dwc_ddrphy_apb_wr(0x90009,0x0); /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */
+	dwc_ddrphy_apb_wr(0x9000a,0x0); /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */
+	dwc_ddrphy_apb_wr(0x9000b,0x0); /*  DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */
+	dwc_ddrphy_apb_wr(0xd00e7,0x400); /*  DWC_DDRPHYA_APBONLY0_SequencerOverride */
+	dwc_ddrphy_apb_wr(0x90017,0x0); /*  DWC_DDRPHYA_INITENG0_StartVector0b0 */
+	dwc_ddrphy_apb_wr(0x90026,0x2c); /*  DWC_DDRPHYA_INITENG0_StartVector0b15 */
+	dwc_ddrphy_apb_wr(0x9000c,0x0); /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */
+	dwc_ddrphy_apb_wr(0x9000d,0x173); /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */
+	dwc_ddrphy_apb_wr(0x9000e,0x60); /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */
+	dwc_ddrphy_apb_wr(0x9000f,0x6110); /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */
+	dwc_ddrphy_apb_wr(0x90010,0x2152); /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */
+	dwc_ddrphy_apb_wr(0x90011,0xdfbd); /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */
+	dwc_ddrphy_apb_wr(0x90012,0xffff); /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */
+	dwc_ddrphy_apb_wr(0x90013,0x6152); /*  DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */
+	dwc_ddrphy_apb_wr(0xc0080,0x0); /*  DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */
+	dwc_ddrphy_apb_wr(0xd0000,0x1); /*  DWC_DDRPHYA_APBONLY0_MicroContMuxSel */
+}
diff --git a/board/freescale/imx8mq_val/ddr/helper.c b/board/freescale/imx8mq_val/ddr/helper.c
new file mode 100644
index 00000000000..b9a9bd24635
--- /dev/null
+++ b/board/freescale/imx8mq_val/ddr/helper.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/sections.h>
+
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMEM_LEN 32768
+#define DMEM_LEN 16384
+#define IMEM_2D_OFFSET 	49152
+
+#define IMEM_OFFSET_ADDR 0x00050000
+#define DMEM_OFFSET_ADDR 0x00054000
+#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
+
+/* We need PHY iMEM PHY is 32KB padded */
+void ddr_load_train_code(enum fw_type type)
+{
+	u32 tmp32, i;
+	u32 error = 0;
+	unsigned long pr_to32, pr_from32;
+	unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
+	unsigned long imem_start = (unsigned long)&_end + fw_offset;
+	unsigned long dmem_start = imem_start + IMEM_LEN;
+
+	pr_from32 = imem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+	for(i = 0x0; i < IMEM_LEN; ){
+		tmp32 = readl(pr_from32);
+		writew(tmp32 & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		pr_from32 += 4;
+		i += 4;
+	}
+
+	pr_from32 = dmem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+	for(i = 0x0; i < DMEM_LEN;){
+		tmp32 = readl(pr_from32);
+		writew(tmp32 & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
+		pr_to32 += 4;
+		pr_from32 += 4;
+		i += 4;
+	}
+
+	printf("check ddr_imem code\n");
+	pr_from32 = imem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+	for(i = 0x0; i < IMEM_LEN;){
+		tmp32 = (readw(pr_to32) & 0x0000ffff);
+		pr_to32 += 4;
+		tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+
+		if(tmp32 != readl(pr_from32)){
+			printf("%lx %lx\n", pr_from32, pr_to32);
+			error++;
+		}
+		pr_from32 += 4;
+		pr_to32 += 4;
+		i += 4;
+	}
+	if(error){
+		printf("check ddr_imem code fail=%d\n",error);
+	}else{
+		printf("check ddr_imem code pass\n");
+	}
+
+	printf("check ddr_dmem code\n");
+	pr_from32 = dmem_start;
+	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+	for(i = 0x0; i < DMEM_LEN;){
+		tmp32 = (readw(pr_to32) & 0x0000ffff);
+		pr_to32 += 4;
+		tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+		if(tmp32 != readl(pr_from32)){
+			printf("%lx %lx\n", pr_from32, pr_to32);
+			error++;
+		}
+		pr_from32 += 4;
+		pr_to32 += 4;
+		i += 4;
+	}
+
+	if(error){
+		printf("check ddr_dmem code fail=%d",error);
+	}else{
+		printf("check ddr_dmem code pass\n");
+	}
+}
diff --git a/board/freescale/imx8mq_val/ddr/wait_ddrphy_training_complete.c b/board/freescale/imx8mq_val/ddr/wait_ddrphy_training_complete.c
new file mode 100644
index 00000000000..e44072280ee
--- /dev/null
+++ b/board/freescale/imx8mq_val/ddr/wait_ddrphy_training_complete.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+static inline void poll_pmu_message_ready(void)
+{
+	unsigned int reg;
+
+	do {
+		reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
+	} while (reg & 0x1);
+}
+
+static inline void ack_pmu_message_recieve(void)
+{
+	unsigned int reg;
+
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x0);
+
+	do {
+		reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
+	} while (!(reg & 0x1));
+
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x1);
+}
+
+static inline unsigned int get_mail(void)
+{
+	unsigned int reg;
+
+	poll_pmu_message_ready();
+
+	reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
+
+	ack_pmu_message_recieve();
+
+	return reg;
+}
+
+static inline unsigned int get_stream_message(void)
+{
+	unsigned int reg, reg2;
+
+	poll_pmu_message_ready();
+
+	reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
+
+	reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034);
+
+	reg2 = (reg2 << 16) | reg;
+
+	ack_pmu_message_recieve();
+
+	return reg2;
+}
+
+static inline void decode_major_message(unsigned int mail)
+{
+	ddr_printf("[PMU Major message = 0x%08x]\n", mail);
+}
+
+static inline void decode_streaming_message(void)
+{
+	unsigned int string_index, arg __maybe_unused;
+	int i = 0;
+
+	string_index = get_stream_message();
+	ddr_printf("	PMU String index = 0x%08x\n", string_index);
+	while (i < (string_index & 0xffff)){
+		arg = get_stream_message();
+		ddr_printf("	arg[%d] = 0x%08x\n", i, arg);
+		i++;
+	}
+
+	ddr_printf("\n");
+}
+
+int wait_ddrphy_training_complete(void)
+{
+	unsigned int mail;
+	while (1) {
+		mail = get_mail();
+		decode_major_message(mail);
+		if (mail == 0x08) {
+			decode_streaming_message();
+		} else if (mail == 0x07) {
+			printf("Training PASS\n");
+			return 0;
+		} else if (mail == 0xff) {
+			printf("Training FAILED\n");
+			return -1;
+		}
+	}
+}
diff --git a/board/freescale/imx8mq_val/ddr4_timing.c b/board/freescale/imx8mq_val/ddr4_timing.c
new file mode 100644
index 00000000000..5c8c3dcfe18
--- /dev/null
+++ b/board/freescale/imx8mq_val/ddr4_timing.c
@@ -0,0 +1,1409 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga
+ * For imx_v2019.04_5.4.x and above version:
+ * please replace #include <asm/arch/imx8m_ddr.h> with #include <asm/arch/ddr.h>
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x3d400304, 0x1 },
+	{ 0x3d400030, 0x1 },
+	{ 0x3d400000, 0x83040010 },
+	{ 0x3d400028, 0x1 },
+	{ 0x3d400030, 0xaa },
+	{ 0x3d400034, 0x221306 },
+	{ 0x3d400038, 0x840000 },
+	{ 0x3d40003c, 0x30 },
+	{ 0x3d400050, 0x210070 },
+	{ 0x3d400054, 0x10008 },
+	{ 0x3d400060, 0x10 },
+	{ 0x3d400064, 0x49009c },
+	{ 0x3d4000c0, 0x0 },
+	{ 0x3d4000c4, 0x1000 },
+	{ 0x3d4000d0, 0xc0030126 },
+	{ 0x3d4000d4, 0x770000 },
+	{ 0x3d4000dc, 0x8340001 },
+	{ 0x3d4000e0, 0x180240 },
+	{ 0x3d4000e4, 0x110000 },
+	{ 0x3d4000e8, 0x2000640 },
+	{ 0x3d4000ec, 0x816 },
+	{ 0x3d4000f0, 0x22 },
+	{ 0x3d4000f4, 0x527 },
+	{ 0x3d400100, 0x11122914 },
+	{ 0x3d400104, 0x4051c },
+	{ 0x3d400108, 0x608050d },
+	{ 0x3d40010c, 0x400c },
+	{ 0x3d400110, 0x8030409 },
+	{ 0x3d400114, 0x6060403 },
+	{ 0x3d40011c, 0x606 },
+	{ 0x3d400120, 0x5050d08 },
+	{ 0x3d400124, 0x2040a },
+	{ 0x3d40012c, 0x1409010e },
+	{ 0x3d400130, 0x8 },
+	{ 0x3d40013c, 0x0 },
+	{ 0x3d400180, 0x1000040 },
+	{ 0x3d400184, 0x493e },
+	{ 0x3d400190, 0x38b8207 },
+	{ 0x3d400194, 0x2020303 },
+	{ 0x3d400198, 0x7f04011 },
+	{ 0x3d40019c, 0xb0 },
+	{ 0x3d4001a0, 0xe0400018 },
+	{ 0x3d4001a4, 0x48005a },
+	{ 0x3d4001a8, 0x80000000 },
+	{ 0x3d4001b0, 0x1 },
+	{ 0x3d4001b4, 0xb07 },
+	{ 0x3d4001b8, 0x4 },
+	{ 0x3d4001c0, 0x1 },
+	{ 0x3d4001c4, 0x0 },
+	{ 0x3d400200, 0x3f17 },
+	{ 0x3d400204, 0x3f0909 },
+	{ 0x3d400208, 0x700 },
+	{ 0x3d40020c, 0x0 },
+	{ 0x3d400210, 0x1f1f },
+	{ 0x3d400214, 0x7070707 },
+	{ 0x3d400218, 0x7070707 },
+	{ 0x3d40021c, 0xf0f },
+	{ 0x3d400220, 0x3f01 },
+	{ 0x3d400240, 0x6000610 },
+	{ 0x3d400244, 0x1323 },
+	{ 0x3d400250, 0x317d1a07 },
+	{ 0x3d400254, 0xf },
+	{ 0x3d40025c, 0x2a001b76 },
+	{ 0x3d400264, 0x9 },
+	{ 0x3d40026c, 0x30000e06 },
+	{ 0x3d400300, 0x14 },
+	{ 0x3d400304, 0x0 },
+	{ 0x3d40030c, 0x0 },
+	{ 0x3d400320, 0x1 },
+	{ 0x3d40036c, 0x10 },
+	{ 0x3d400400, 0x11 },
+	{ 0x3d400404, 0x13193 },
+	{ 0x3d400408, 0x6096 },
+	{ 0x3d400490, 0x1 },
+	{ 0x3d400494, 0x2000c00 },
+	{ 0x3d400498, 0x3c00db },
+	{ 0x3d40049c, 0x100001 },
+	{ 0x3d4004a0, 0x41f },
+	{ 0x3d402050, 0x210070 },
+	{ 0x3d402064, 0x300068 },
+	{ 0x3d4020dc, 0x2100001 },
+	{ 0x3d4020e0, 0x40 },
+	{ 0x3d4020e8, 0x2000640 },
+	{ 0x3d4020ec, 0x416 },
+	{ 0x3d402100, 0xd0c1b0d },
+	{ 0x3d402104, 0x30313 },
+	{ 0x3d402108, 0x506040a },
+	{ 0x3d40210c, 0x400c },
+	{ 0x3d402110, 0x6030306 },
+	{ 0x3d402114, 0x4040302 },
+	{ 0x3d40211c, 0x404 },
+	{ 0x3d402120, 0x4040d06 },
+	{ 0x3d402124, 0x20308 },
+	{ 0x3d40212c, 0x1206010e },
+	{ 0x3d402130, 0x8 },
+	{ 0x3d40213c, 0x0 },
+	{ 0x3d402180, 0x1000040 },
+	{ 0x3d402190, 0x3868204 },
+	{ 0x3d402194, 0x2020303 },
+	{ 0x3d4021b4, 0x604 },
+	{ 0x3d4021b8, 0x4 },
+	{ 0x3d402240, 0x6000608 },
+	{ 0x3d403050, 0x210070 },
+	{ 0x3d403064, 0x200045 },
+	{ 0x3d4030dc, 0x1 },
+	{ 0x3d4030e0, 0x40 },
+	{ 0x3d4030e8, 0x2000640 },
+	{ 0x3d4030ec, 0x16 },
+	{ 0x3d403100, 0xb081209 },
+	{ 0x3d403104, 0x2020d },
+	{ 0x3d403108, 0x5050309 },
+	{ 0x3d40310c, 0x400c },
+	{ 0x3d403110, 0x4030205 },
+	{ 0x3d403114, 0x3030202 },
+	{ 0x3d40311c, 0x303 },
+	{ 0x3d403120, 0x3040d04 },
+	{ 0x3d403124, 0x20208 },
+	{ 0x3d40312c, 0x1005010e },
+	{ 0x3d403130, 0x8 },
+	{ 0x3d40313c, 0x0 },
+	{ 0x3d403180, 0x1000040 },
+	{ 0x3d403190, 0x3848204 },
+	{ 0x3d403194, 0x2020303 },
+	{ 0x3d4031b4, 0x404 },
+	{ 0x3d4031b8, 0x4 },
+	{ 0x3d403240, 0x6000600 },
+	{ 0x3d400060, 0x11 },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x1005f, 0x2ff },
+	{ 0x1015f, 0x2ff },
+	{ 0x1105f, 0x2ff },
+	{ 0x1115f, 0x2ff },
+	{ 0x1205f, 0x2ff },
+	{ 0x1215f, 0x2ff },
+	{ 0x1305f, 0x2ff },
+	{ 0x1315f, 0x2ff },
+	{ 0x11005f, 0x2ff },
+	{ 0x11015f, 0x2ff },
+	{ 0x11105f, 0x2ff },
+	{ 0x11115f, 0x2ff },
+	{ 0x11205f, 0x2ff },
+	{ 0x11215f, 0x2ff },
+	{ 0x11305f, 0x2ff },
+	{ 0x11315f, 0x2ff },
+	{ 0x21005f, 0x2ff },
+	{ 0x21015f, 0x2ff },
+	{ 0x21105f, 0x2ff },
+	{ 0x21115f, 0x2ff },
+	{ 0x21205f, 0x2ff },
+	{ 0x21215f, 0x2ff },
+	{ 0x21305f, 0x2ff },
+	{ 0x21315f, 0x2ff },
+	{ 0x55, 0x3ff },
+	{ 0x1055, 0x3ff },
+	{ 0x2055, 0x3ff },
+	{ 0x3055, 0x3ff },
+	{ 0x4055, 0xff },
+	{ 0x5055, 0xff },
+	{ 0x6055, 0x3ff },
+	{ 0x7055, 0x3ff },
+	{ 0x8055, 0x3ff },
+	{ 0x9055, 0x3ff },
+	{ 0x200c5, 0xa },
+	{ 0x1200c5, 0xb },
+	{ 0x2200c5, 0x6 },
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x1 },
+	{ 0x22002e, 0x1 },
+	{ 0x20024, 0x8 },
+	{ 0x2003a, 0x2 },
+	{ 0x120024, 0x8 },
+	{ 0x2003a, 0x2 },
+	{ 0x220024, 0x8 },
+	{ 0x2003a, 0x2 },
+	{ 0x20056, 0x6 },
+	{ 0x120056, 0xa },
+	{ 0x220056, 0xa },
+	{ 0x1004d, 0x38 },
+	{ 0x1014d, 0x38 },
+	{ 0x1104d, 0x38 },
+	{ 0x1114d, 0x38 },
+	{ 0x1204d, 0x38 },
+	{ 0x1214d, 0x38 },
+	{ 0x1304d, 0x38 },
+	{ 0x1314d, 0x38 },
+	{ 0x11004d, 0x38 },
+	{ 0x11014d, 0x38 },
+	{ 0x11104d, 0x38 },
+	{ 0x11114d, 0x38 },
+	{ 0x11204d, 0x38 },
+	{ 0x11214d, 0x38 },
+	{ 0x11304d, 0x38 },
+	{ 0x11314d, 0x38 },
+	{ 0x21004d, 0x38 },
+	{ 0x21014d, 0x38 },
+	{ 0x21104d, 0x38 },
+	{ 0x21114d, 0x38 },
+	{ 0x21204d, 0x38 },
+	{ 0x21214d, 0x38 },
+	{ 0x21304d, 0x38 },
+	{ 0x21314d, 0x38 },
+	{ 0x10049, 0xeba },
+	{ 0x10149, 0xeba },
+	{ 0x11049, 0xeba },
+	{ 0x11149, 0xeba },
+	{ 0x12049, 0xeba },
+	{ 0x12149, 0xeba },
+	{ 0x13049, 0xeba },
+	{ 0x13149, 0xeba },
+	{ 0x110049, 0xeba },
+	{ 0x110149, 0xeba },
+	{ 0x111049, 0xeba },
+	{ 0x111149, 0xeba },
+	{ 0x112049, 0xeba },
+	{ 0x112149, 0xeba },
+	{ 0x113049, 0xeba },
+	{ 0x113149, 0xeba },
+	{ 0x210049, 0xeba },
+	{ 0x210149, 0xeba },
+	{ 0x211049, 0xeba },
+	{ 0x211149, 0xeba },
+	{ 0x212049, 0xeba },
+	{ 0x212149, 0xeba },
+	{ 0x213049, 0xeba },
+	{ 0x213149, 0xeba },
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 0x5 },
+	{ 0x20075, 0x2 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x258 },
+	{ 0x120008, 0x190 },
+	{ 0x220008, 0x10a },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x78 },
+	{ 0x10043, 0x5b1 },
+	{ 0x10143, 0x5b1 },
+	{ 0x11043, 0x5b1 },
+	{ 0x11143, 0x5b1 },
+	{ 0x12043, 0x5b1 },
+	{ 0x12143, 0x5b1 },
+	{ 0x13043, 0x5b1 },
+	{ 0x13143, 0x5b1 },
+	{ 0x1200b2, 0x78 },
+	{ 0x110043, 0x5b1 },
+	{ 0x110143, 0x5b1 },
+	{ 0x111043, 0x5b1 },
+	{ 0x111143, 0x5b1 },
+	{ 0x112043, 0x5b1 },
+	{ 0x112143, 0x5b1 },
+	{ 0x113043, 0x5b1 },
+	{ 0x113143, 0x5b1 },
+	{ 0x2200b2, 0x78 },
+	{ 0x210043, 0x5b1 },
+	{ 0x210143, 0x5b1 },
+	{ 0x211043, 0x5b1 },
+	{ 0x211143, 0x5b1 },
+	{ 0x212043, 0x5b1 },
+	{ 0x212143, 0x5b1 },
+	{ 0x213043, 0x5b1 },
+	{ 0x213143, 0x5b1 },
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+	{ 0x20019, 0x5 },
+	{ 0x120019, 0x5 },
+	{ 0x220019, 0x5 },
+	{ 0x200f0, 0x5555 },
+	{ 0x200f1, 0x5555 },
+	{ 0x200f2, 0x5555 },
+	{ 0x200f3, 0x5555 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0x5555 },
+	{ 0x200f6, 0x5555 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x12002d, 0x0 },
+	{ 0x22002d, 0x0 },
+	{ 0x200c7, 0x80 },
+	{ 0x1200c7, 0x80 },
+	{ 0x2200c7, 0x80 },
+	{ 0x200ca, 0x106 },
+	{ 0x1200ca, 0x106 },
+	{ 0x2200ca, 0x106 },
+	{ 0x20110, 0x2 },
+	{ 0x20111, 0x3 },
+	{ 0x20112, 0x4 },
+	{ 0x20113, 0x5 },
+	{ 0x20114, 0x0 },
+	{ 0x20115, 0x1 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x80 },
+	{ 0x54003, 0x960 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x236 },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x303 },
+	{ 0x54009, 0x200 },
+	{ 0x5400b, 0x31f },
+	{ 0x5400c, 0xc8 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x834 },
+	{ 0x54030, 0x1 },
+	{ 0x54031, 0x18 },
+	{ 0x54032, 0x240 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x640 },
+	{ 0x54035, 0x816 },
+	{ 0x54036, 0x103 },
+	{ 0x5403f, 0x1323 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x80 },
+	{ 0x54002, 0x1 },
+	{ 0x54003, 0x640 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x236 },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x303 },
+	{ 0x54009, 0x200 },
+	{ 0x5400b, 0x21f },
+	{ 0x5400c, 0xc8 },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x210 },
+	{ 0x54030, 0x1 },
+	{ 0x54032, 0x40 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x640 },
+	{ 0x54035, 0x416 },
+	{ 0x54036, 0x103 },
+	{ 0x5403f, 0x1323 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x80 },
+	{ 0x54002, 0x2 },
+	{ 0x54003, 0x428 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x236 },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x303 },
+	{ 0x54009, 0x200 },
+	{ 0x5400b, 0x21f },
+	{ 0x5400c, 0xc8 },
+	{ 0x54012, 0x1 },
+	{ 0x54030, 0x1 },
+	{ 0x54032, 0x40 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x640 },
+	{ 0x54035, 0x16 },
+	{ 0x54036, 0x103 },
+	{ 0x5403f, 0x1323 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x80 },
+	{ 0x54003, 0x960 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, 0x236 },
+	{ 0x54007, 0x2000 },
+	{ 0x54008, 0x303 },
+	{ 0x54009, 0x200 },
+	{ 0x5400b, 0x61 },
+	{ 0x5400c, 0x1c8 },
+	{ 0x5400d, 0x101 },
+	{ 0x5400e, 0x1f7f },
+	{ 0x54012, 0x1 },
+	{ 0x5402f, 0x834 },
+	{ 0x54030, 0x1 },
+	{ 0x54031, 0x18 },
+	{ 0x54032, 0x240 },
+	{ 0x54033, 0x200 },
+	{ 0x54034, 0x640 },
+	{ 0x54035, 0x816 },
+	{ 0x54036, 0x103 },
+	{ 0x5403f, 0x1323 },
+	{ 0x541fc, 0x100 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x2 },
+	{ 0x90033, 0x10 },
+	{ 0x90034, 0x139 },
+	{ 0x90035, 0xf },
+	{ 0x90036, 0x7c0 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0x44 },
+	{ 0x90039, 0x630 },
+	{ 0x9003a, 0x159 },
+	{ 0x9003b, 0x14f },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x47 },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x149 },
+	{ 0x90041, 0x4f },
+	{ 0x90042, 0x630 },
+	{ 0x90043, 0x179 },
+	{ 0x90044, 0x8 },
+	{ 0x90045, 0xe0 },
+	{ 0x90046, 0x109 },
+	{ 0x90047, 0x0 },
+	{ 0x90048, 0x7c8 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x1 },
+	{ 0x9004c, 0x8 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x45a },
+	{ 0x9004f, 0x9 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x448 },
+	{ 0x90052, 0x109 },
+	{ 0x90053, 0x40 },
+	{ 0x90054, 0x630 },
+	{ 0x90055, 0x179 },
+	{ 0x90056, 0x1 },
+	{ 0x90057, 0x618 },
+	{ 0x90058, 0x109 },
+	{ 0x90059, 0x40c0 },
+	{ 0x9005a, 0x630 },
+	{ 0x9005b, 0x149 },
+	{ 0x9005c, 0x8 },
+	{ 0x9005d, 0x4 },
+	{ 0x9005e, 0x48 },
+	{ 0x9005f, 0x4040 },
+	{ 0x90060, 0x630 },
+	{ 0x90061, 0x149 },
+	{ 0x90062, 0x0 },
+	{ 0x90063, 0x4 },
+	{ 0x90064, 0x48 },
+	{ 0x90065, 0x40 },
+	{ 0x90066, 0x630 },
+	{ 0x90067, 0x149 },
+	{ 0x90068, 0x10 },
+	{ 0x90069, 0x4 },
+	{ 0x9006a, 0x18 },
+	{ 0x9006b, 0x0 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x78 },
+	{ 0x9006e, 0x549 },
+	{ 0x9006f, 0x630 },
+	{ 0x90070, 0x159 },
+	{ 0x90071, 0xd49 },
+	{ 0x90072, 0x630 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0x94a },
+	{ 0x90075, 0x630 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x441 },
+	{ 0x90078, 0x630 },
+	{ 0x90079, 0x149 },
+	{ 0x9007a, 0x42 },
+	{ 0x9007b, 0x630 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x1 },
+	{ 0x9007e, 0x630 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x0 },
+	{ 0x90081, 0xe0 },
+	{ 0x90082, 0x109 },
+	{ 0x90083, 0xa },
+	{ 0x90084, 0x10 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0x9 },
+	{ 0x90087, 0x3c0 },
+	{ 0x90088, 0x149 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x159 },
+	{ 0x9008c, 0x18 },
+	{ 0x9008d, 0x10 },
+	{ 0x9008e, 0x109 },
+	{ 0x9008f, 0x0 },
+	{ 0x90090, 0x3c0 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x18 },
+	{ 0x90093, 0x4 },
+	{ 0x90094, 0x48 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x58 },
+	{ 0x90098, 0xa },
+	{ 0x90099, 0x10 },
+	{ 0x9009a, 0x109 },
+	{ 0x9009b, 0x2 },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x7 },
+	{ 0x9009f, 0x7c0 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x10 },
+	{ 0x900a2, 0x10 },
+	{ 0x900a3, 0x109 },
+	{ 0x900a4, 0x0 },
+	{ 0x900a5, 0x8140 },
+	{ 0x900a6, 0x10c },
+	{ 0x900a7, 0x10 },
+	{ 0x900a8, 0x8138 },
+	{ 0x900a9, 0x10c },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x7c8 },
+	{ 0x900ac, 0x101 },
+	{ 0x900ad, 0x8 },
+	{ 0x900ae, 0x0 },
+	{ 0x900af, 0x8 },
+	{ 0x900b0, 0x8 },
+	{ 0x900b1, 0x448 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0xf },
+	{ 0x900b4, 0x7c0 },
+	{ 0x900b5, 0x109 },
+	{ 0x900b6, 0x47 },
+	{ 0x900b7, 0x630 },
+	{ 0x900b8, 0x109 },
+	{ 0x900b9, 0x8 },
+	{ 0x900ba, 0x618 },
+	{ 0x900bb, 0x109 },
+	{ 0x900bc, 0x8 },
+	{ 0x900bd, 0xe0 },
+	{ 0x900be, 0x109 },
+	{ 0x900bf, 0x0 },
+	{ 0x900c0, 0x7c8 },
+	{ 0x900c1, 0x109 },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x8140 },
+	{ 0x900c4, 0x10c },
+	{ 0x900c5, 0x0 },
+	{ 0x900c6, 0x1 },
+	{ 0x900c7, 0x8 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x4 },
+	{ 0x900ca, 0x8 },
+	{ 0x900cb, 0x8 },
+	{ 0x900cc, 0x7c8 },
+	{ 0x900cd, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x90026, 0x2c },
+	{ 0x2000b, 0x4b },
+	{ 0x2000c, 0x96 },
+	{ 0x2000d, 0x5dc },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x32 },
+	{ 0x12000c, 0x64 },
+	{ 0x12000d, 0x3e8 },
+	{ 0x12000e, 0x2c },
+	{ 0x22000b, 0x21 },
+	{ 0x22000c, 0x42 },
+	{ 0x22000d, 0x299 },
+	{ 0x22000e, 0x21 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0xffff },
+	{ 0x90013, 0x6152 },
+	{ 0xc0080, 0x0 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 2400mts 1D */
+		.drate = 2400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P1 1600mts 1D */
+		.drate = 1600,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+	},
+	{
+		/* P2 1064mts 1D */
+		.drate = 1064,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+	},
+	{
+		/* P0 2400mts 2D */
+		.drate = 2400,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 2400, 1600, 1064, },
+};
+
diff --git a/board/freescale/imx8mq_val/imx8mq_val.c b/board/freescale/imx8mq_val/imx8mq_val.c
new file mode 100644
index 00000000000..afda2f926ca
--- /dev/null
+++ b/board/freescale/imx8mq_val/imx8mq_val.c
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2019 NXP
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+#include <usb.h>
+#include <dwc3-uboot.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define NAND_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS)
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE)
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_QSPI
+int board_qspi_init(void)
+{
+	set_clk_qspi();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+#ifdef CONFIG_SPL_BUILD
+static iomux_v3_cfg_t const gpmi_pads[] = {
+	IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
+	IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
+};
+#endif
+
+static void setup_gpmi_nand(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+#endif
+
+	init_nand_clk();
+}
+#endif
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand(); /* SPL will call the board_early_init_f */
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+static int setup_fec(void)
+{
+#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+	/*
+	* GPR1 bit 13:
+	* 1:enet1 rmii clock comes from ccm->pad->loopback, SION bit for the pad (iomuxc_sw_input_on_pad_enet_td2) should be set also;
+	* 0:enet1 rmii clock comes from external phy or osc
+	*/
+
+	setbits_le32(&gpr->gpr[1],
+			IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
+	return set_clk_enet(ENET_50MHZ);
+#else
+	return set_clk_enet(ENET_125MHZ);
+#endif
+}
+
+
+int board_phy_config(struct phy_device *phydev)
+{
+#ifndef CONFIG_TARGET_IMX8MQ_DDR3L_VAL
+
+	/* enable rgmii rxc skew and phy mode select to RGMII copper */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+#endif
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_DWC3
+
+#define USB_PHY_CTRL0			0xF0040
+#define USB_PHY_CTRL0_REF_SSP_EN	BIT(2)
+
+#define USB_PHY_CTRL1			0xF0044
+#define USB_PHY_CTRL1_RESET		BIT(0)
+#define USB_PHY_CTRL1_COMMONONN		BIT(1)
+#define USB_PHY_CTRL1_ATERESET		BIT(3)
+#define USB_PHY_CTRL1_VDATSRCENB0	BIT(19)
+#define USB_PHY_CTRL1_VDATDETENB0	BIT(20)
+
+#define USB_PHY_CTRL2			0xF0048
+#define USB_PHY_CTRL2_TXENABLEN0	BIT(8)
+
+static struct dwc3_device dwc3_device_data = {
+#ifdef CONFIG_SPL_BUILD
+	.maximum_speed = USB_SPEED_HIGH,
+#else
+	.maximum_speed = USB_SPEED_SUPER,
+#endif
+	.base = USB1_BASE_ADDR,
+	.dr_mode = USB_DR_MODE_PERIPHERAL,
+	.index = 0,
+	.power_down_scale = 2,
+};
+
+int usb_gadget_handle_interrupts(int index)
+{
+	dwc3_uboot_handle_interrupt(index);
+	return 0;
+}
+
+static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
+{
+	u32 RegData;
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL1);
+	RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
+			USB_PHY_CTRL1_COMMONONN);
+	RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
+	writel(RegData, dwc3->base + USB_PHY_CTRL1);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL0);
+	RegData |= USB_PHY_CTRL0_REF_SSP_EN;
+	writel(RegData, dwc3->base + USB_PHY_CTRL0);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL2);
+	RegData |= USB_PHY_CTRL2_TXENABLEN0;
+	writel(RegData, dwc3->base + USB_PHY_CTRL2);
+
+	RegData = readl(dwc3->base + USB_PHY_CTRL1);
+	RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
+	writel(RegData, dwc3->base + USB_PHY_CTRL1);
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	if (index == 0 && init == USB_INIT_DEVICE) {
+		imx8m_usb_power(index, true);
+		dwc3_nxp_usb_phy_init(&dwc3_device_data);
+		return dwc3_uboot_init(&dwc3_device_data);
+	}
+	
+	return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	if (index == 0 && init == USB_INIT_DEVICE) {
+		dwc3_uboot_exit(index);
+		imx8m_usb_power(index, false);
+	}
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+	init_usb_clk();
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL
+	env_set("board_name", "DDR3L-VAL");
+#else
+	env_set("board_name", "DDR4-VAL");
+#endif
+	env_set("board_rev", "iMX8MQ");
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	return 0;
+}
diff --git a/board/freescale/imx8mq_val/spl.c b/board/freescale/imx8mq_val/spl.c
new file mode 100644
index 00000000000..0e57ab9fa0d
--- /dev/null
+++ b/board/freescale/imx8mq_val/spl.c
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <spl.h>
+#include "../common/pfuze.h"
+#include <nand.h>
+
+#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL
+#include "ddr/ddr.h"
+#else
+#include <asm/arch/ddr.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_dram_init(void)
+{
+	/* ddr init */
+#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL
+	ddr_init(NULL);
+#else
+	ddr_init(&dram_timing);
+#endif
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+#else
+		ret = gpio_get_value(USDHC2_CD_GPIO);
+#endif
+		return ret;
+	}
+
+	return 1;
+}
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+	IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			init_clk_usdhc(0);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+		case 1:
+			init_clk_usdhc(1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+			gpio_direction_output(USDHC2_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#if CONFIG_IS_ENABLED(POWER_LEGACY)
+#define I2C_PMIC	0
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+	unsigned int reg;
+
+	ret = power_pfuze100_init(I2C_PMIC);
+	if (ret)
+		return -ENODEV;
+
+	p = pmic_get("PFUZE100");
+	ret = pmic_probe(p);
+	if (ret)
+		return -ENODEV;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+	pmic_reg_read(p, PFUZE100_SW1ABVOL, &reg);
+	if ((reg & 0x3f) != 0x1c) {
+		reg &= ~0x3f;
+		reg |= 0x1c;
+		pmic_reg_write(p, PFUZE100_SW1ABVOL, reg);
+	}
+
+	pmic_reg_read(p, PFUZE100_SW1CVOL, &reg);
+	if ((reg & 0x3f) != 0x1c) {
+		reg &= ~0x3f;
+		reg |= 0x1c;
+		pmic_reg_write(p, PFUZE100_SW1CVOL, reg);
+	}
+
+	ret = pfuze_mode_init(p, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+#endif
+
+void spl_board_init(void)
+{
+#ifndef CONFIG_SPL_USB_SDP_SUPPORT
+	/* Serial download mode */
+	if (is_usb_boot()) {
+		puts("Back to ROM, SDP\n");
+		restore_boot_params();
+	}
+#endif
+
+	init_usb_clk();
+
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	arch_cpu_init();
+
+	init_uart_clk(0); /* Init UART0 clock */
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	/* Adjust pmic voltage VDD_DRAM to 1.0V for DRAM RUN >= 2400MHZ */
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/board/freescale/imx8qm_mek/Kconfig b/board/freescale/imx8qm_mek/Kconfig
index aed6ab25ce1..6dfdc3bd092 100644
--- a/board/freescale/imx8qm_mek/Kconfig
+++ b/board/freescale/imx8qm_mek/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_IMX8QM_MEK
+if TARGET_IMX8QM_MEK || TARGET_IMX8QM_MEK_A53_ONLY || TARGET_IMX8QM_MEK_A72_ONLY
 
 config SYS_BOARD
 	default "imx8qm_mek"
diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c
index 682099ad9cf..c06bc78ef1f 100644
--- a/board/freescale/imx8qm_mek/imx8qm_mek.c
+++ b/board/freescale/imx8qm_mek/imx8qm_mek.c
@@ -16,24 +16,48 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sci/sci.h>
 #include <asm/arch/imx8-pins.h>
+#include <asm/arch/snvs_security_sc.h>
+#include <usb.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/sys_proto.h>
+#include "../common/tcpc.h"
+#include "command.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
-			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
-			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
-			 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+#define ENET_INPUT_PAD_CTRL	((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
 
+#define ENET_NORMAL_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+
+#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#ifdef CONFIG_TARGET_IMX8QM_MEK_A72_ONLY
+static iomux_cfg_t uart2_pads[] = {
+	SC_P_UART0_RTS_B | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART0_CTS_B | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+#else
 static iomux_cfg_t uart0_pads[] = {
 	SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 	SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
+#endif
 
 static void setup_iomux_uart(void)
 {
+#ifdef CONFIG_TARGET_IMX8QM_MEK_A72_ONLY
+	imx8_iomux_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+#else
 	imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
+#endif
 }
 
 int board_early_init_f(void)
@@ -41,32 +65,110 @@ int board_early_init_f(void)
 	sc_pm_clock_rate_t rate = SC_80MHZ;
 	int ret;
 
+	/* When start u-boot in XEN VM, directly return */
+	if (IS_ENABLED(CONFIG_XEN)) {
+		writel(0xF53535F5, (void __iomem *)0x80000000);
+		return 0;
+	}
+
+#ifdef CONFIG_TARGET_IMX8QM_MEK_A72_ONLY
+	/* Set UART2 clock root to 80 MHz */
+	ret = sc_pm_setup_uart(SC_R_UART_2, rate);
+	if (ret)
+		return ret;
+#else
 	/* Set UART0 clock root to 80 MHz */
 	ret = sc_pm_setup_uart(SC_R_UART_0, rate);
 	if (ret)
 		return ret;
+#endif	/* CONFIG_TARGET_IMX8QM_MEK_A72_ONLY */
 
 	setup_iomux_uart();
 
-	sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON);
-
 	return 0;
 }
 
-#if CONFIG_IS_ENABLED(DM_GPIO)
-static void board_gpio_init(void)
-{
-	/* TODO */
-}
-#else
-static inline void board_gpio_init(void) {}
-#endif
 
 #if IS_ENABLED(CONFIG_FEC_MXC)
 #include <miiphy.h>
 
+#ifndef CONFIG_DM_ETH
+static iomux_cfg_t pad_enet1[] = {
+	SC_P_ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET1_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET1_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET1_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET1_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET1_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET1_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET1_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET1_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+
+	/* Shared MDIO */
+	SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+};
+
+static iomux_cfg_t pad_enet0[] = {
+	SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+
+	/* Shared MDIO */
+	SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+	if (0 == CONFIG_FEC_ENET_DEV)
+		imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0));
+	else
+		imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1));
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int ret;
+	struct power_domain pd;
+
+	printf("[%s] %d\n", __func__, __LINE__);
+
+	if (CONFIG_FEC_ENET_DEV) {
+		if (!power_domain_lookup_name("conn_enet1", &pd))
+			power_domain_on(&pd);
+	} else {
+		if (!power_domain_lookup_name("conn_enet0", &pd))
+			power_domain_on(&pd);
+	}
+
+	setup_iomux_fec();
+
+	ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
+		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+	if (ret)
+		printf("FEC1 MXC: %s:failed\n", __func__);
+
+	return ret;
+}
+
 int board_phy_config(struct phy_device *phydev)
 {
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
 
@@ -75,39 +177,263 @@ int board_phy_config(struct phy_device *phydev)
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
 
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
 	return 0;
 }
 #endif
+#endif
+
+#define BB_GPIO_3V3_1 IMX_GPIO_NR(4, 20)
+#define BB_GPIO_3V3_2 IMX_GPIO_NR(4, 24)
+#define BB_GPIO_3V3_3 IMX_GPIO_NR(4, 23)
+
+static void board_gpio_init(void)
+{
+#if defined(CONFIG_TARGET_IMX8QM_MEK) || defined(CONFIG_TARGET_IMX8QM_MEK_A53_ONLY)
+	int ret;
+	struct gpio_desc desc;
+
+	ret = dm_gpio_lookup_name("GPIO4_20", &desc);
+	if (ret) {
+		printf("%s lookup GPIO@4_20 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "bb_3v3_1");
+	if (ret) {
+		printf("%s request bb_3v3_1 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	ret = dm_gpio_lookup_name("GPIO4_24", &desc);
+	if (ret) {
+		printf("%s lookup GPIO@4_24 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "bb_3v3_2");
+	if (ret) {
+		printf("%s request bb_3v3_2 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 
+	ret = dm_gpio_lookup_name("GPIO4_23", &desc);
+	if (ret) {
+		printf("%s lookup GPIO@4_23 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "bb_3v3_3");
+	if (ret) {
+		printf("%s request bb_3v3_3 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	/* enable LVDS SAS boards */
+	ret = dm_gpio_lookup_name("GPIO1_6", &desc);
+	if (ret) {
+		printf("%s lookup GPIO1_6 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "lvds_enable");
+	if (ret) {
+		printf("%s request lvds_enable failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	/* enable MIPI SAS boards */
+	ret = dm_gpio_lookup_name("GPIO1_7", &desc);
+	if (ret) {
+		printf("%s lookup GPIO1_7 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "mipi_enable");
+	if (ret) {
+		printf("%s request mipi_enable failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+#endif
+
+}
 int checkboard(void)
 {
 	puts("Board: iMX8QM MEK\n");
 
-	build_info();
 	print_bootinfo();
 
 	return 0;
 }
 
+#ifdef CONFIG_USB
+
+#ifdef CONFIG_USB_TCPC
+struct gpio_desc type_sel_desc;
+
+static iomux_cfg_t ss_mux_gpio[] = {
+	SC_P_USB_SS3_TC3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+	SC_P_QSPI1A_SS0_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+struct tcpc_port port;
+struct tcpc_port_config port_config = {
+	.i2c_bus = 0,
+	.addr = 0x51,
+	.port_type = TYPEC_PORT_DFP,
+};
+
+void ss_mux_select(enum typec_cc_polarity pol)
+{
+	if (pol == TYPEC_POLARITY_CC1)
+		dm_gpio_set_value(&type_sel_desc, 0);
+	else
+		dm_gpio_set_value(&type_sel_desc, 1);
+}
+
+static void setup_typec(void)
+{
+	int ret;
+	struct gpio_desc typec_en_desc;
+
+	imx8_iomux_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
+	ret = dm_gpio_lookup_name("GPIO4_6", &type_sel_desc);
+	if (ret) {
+		printf("%s lookup GPIO4_6 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&type_sel_desc, "typec_sel");
+	if (ret) {
+		printf("%s request typec_sel failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&type_sel_desc, GPIOD_IS_OUT);
+
+	ret = dm_gpio_lookup_name("GPIO4_19", &typec_en_desc);
+	if (ret) {
+		printf("%s lookup GPIO4_19 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&typec_en_desc, "typec_en");
+	if (ret) {
+		printf("%s request typec_en failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	/* Enable SS MUX */
+	dm_gpio_set_dir_flags(&typec_en_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	ret = tcpc_init(&port, port_config, &ss_mux_select);
+	if (ret) {
+		printf("%s: tcpc init failed, err=%d\n", __func__, ret);
+		return;
+	}
+}
+#endif
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	if (index == 1) {
+		if (init == USB_INIT_HOST) {
+#ifdef CONFIG_USB_TCPC
+			ret = tcpc_setup_dfp_mode(&port);
+#endif
+#ifdef CONFIG_USB_CDNS3_GADGET
+		} else {
+#ifdef CONFIG_USB_TCPC
+			ret = tcpc_setup_ufp_mode(&port);
+			printf("%d setufp mode %d\n", index, ret);
+#endif
+#endif
+		}
+	}
+
+	return ret;
+
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	if (index == 1) {
+		if (init == USB_INIT_HOST) {
+#ifdef CONFIG_USB_TCPC
+			ret = tcpc_disable_src_vbus(&port);
+#endif
+		}
+	}
+
+	return ret;
+}
+#endif
+
 int board_init(void)
 {
-	/* Power up base board */
-	sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON);
+	if (IS_ENABLED(CONFIG_XEN))
+		return 0;
 
 	board_gpio_init();
 
+
+#if defined(CONFIG_USB) && defined(CONFIG_USB_TCPC)
+	setup_typec();
+#endif
+
+#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO
+	{
+		int ret = snvs_security_sc_init();
+
+		if (ret)
+			return ret;
+	}
+#endif
+
 	return 0;
 }
 
+void board_quiesce_devices(void)
+{
+	const char *power_on_devices[] = {
+#ifdef CONFIG_TARGET_IMX8QM_MEK_A72_ONLY
+		"dma_lpuart2",
+		"PD_UART2_TX",
+		"PD_UART2_RX",
+#else
+		"dma_lpuart0",
+#endif
+	};
+
+	if (IS_ENABLED(CONFIG_XEN)) {
+		/* Clear magic number to let xen know uboot is over */
+		writel(0x0, (void __iomem *)0x80000000);
+		return;
+	}
+
+	imx8_power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices));
+}
+
 /*
  * Board specific reset that is system reset.
  */
 void reset_cpu(void)
 {
-	/* TODO */
+	sc_pm_reboot(-1, SC_PM_RESET_TYPE_COLD);
+	while(1);
 }
 
 #ifdef CONFIG_OF_BOARD_SETUP
@@ -119,28 +445,100 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 
 int board_mmc_get_env_dev(int devno)
 {
+	/* Use EMMC */
+	if (IS_ENABLED(CONFIG_XEN))
+		return 0;
+
 	return devno;
 }
 
+int mmc_map_to_kernel_blk(int dev_no)
+{
+	/* Use EMMC */
+	if (IS_ENABLED(CONFIG_XEN))
+		return 0;
+
+	return dev_no;
+}
+
+extern uint32_t _end_ofs;
 int board_late_init(void)
 {
 	char *fdt_file;
+#if !defined(CONFIG_TARGET_IMX8QM_MEK_A53_ONLY) && !defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY)
 	bool m4_booted;
+#endif
+
+	build_info();
 
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	env_set("board_name", "MEK");
 	env_set("board_rev", "iMX8QM");
 #endif
 
+	env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+	env_set("sec_boot", "yes");
+#endif
+
 	fdt_file = env_get("fdt_file");
-	m4_booted = m4_parts_booted();
 
 	if (fdt_file && !strcmp(fdt_file, "undefined")) {
+#if defined(CONFIG_TARGET_IMX8QM_MEK_A53_ONLY)
+		env_set("fdt_file", "imx8qm-mek-cockpit-ca53.dtb");
+#elif defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY)
+		env_set("fdt_file", "imx8qm-mek-cockpit-ca72.dtb");
+#else
+		m4_booted = m4_parts_booted();
 		if (m4_booted)
 			env_set("fdt_file", "imx8qm-mek-rpmsg.dtb");
 		else
 			env_set("fdt_file", "imx8qm-mek.dtb");
+#endif
 	}
 
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+#if defined(CONFIG_IMX_LOAD_HDMI_FIMRWARE_RX) || defined(CONFIG_IMX_LOAD_HDMI_FIMRWARE_TX)
+	char *end_of_uboot;
+	char command[256];
+	end_of_uboot = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs + fdt_totalsize(gd->fdt_blob));
+	end_of_uboot += 9;
+
+	/* load hdmitxfw.bin and hdmirxfw.bin*/
+	memcpy((void *)IMX_HDMI_FIRMWARE_LOAD_ADDR, end_of_uboot,
+			IMX_HDMITX_FIRMWARE_SIZE + IMX_HDMIRX_FIRMWARE_SIZE);
+
+#ifdef CONFIG_IMX_LOAD_HDMI_FIMRWARE_TX
+	sprintf(command, "hdp load 0x%x", IMX_HDMI_FIRMWARE_LOAD_ADDR);
+	run_command(command, 0);
+#endif
+#ifdef CONFIG_IMX_LOAD_HDMI_FIMRWARE_RX
+	sprintf(command, "hdprx load 0x%x",
+			IMX_HDMI_FIRMWARE_LOAD_ADDR + IMX_HDMITX_FIRMWARE_SIZE);
+	run_command(command, 0);
+#endif
+#endif /* CONFIG_IMX_LOAD_HDMI_FIMRWARE_RX || CONFIG_IMX_LOAD_HDMI_FIMRWARE_TX */
+
 	return 0;
 }
+
+#ifdef CONFIG_ANDROID_SUPPORT
+bool is_power_key_pressed(void) {
+	sc_bool_t status = SC_FALSE;
+
+	sc_misc_get_button_status(-1, &status);
+	return (bool)status;
+}
+#endif
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+int is_recovery_key_pressing(void)
+{
+	return 0; /* TODO */
+}
+#endif /* CONFIG_ANDROID_RECOVERY */
+#endif /* CONFIG_FSL_FASTBOOT */
diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c
index 944ba745c09..dea80ed3726 100644
--- a/board/freescale/imx8qm_mek/spl.c
+++ b/board/freescale/imx8qm_mek/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -16,7 +16,7 @@
 #include <dm/uclass-internal.h>
 #include <dm/device-internal.h>
 #include <dm/lists.h>
-#include <asm/arch/sys_proto.h>
+#include <bootm.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -24,6 +24,8 @@ void spl_board_init(void)
 {
 	struct udevice *dev;
 
+	uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev);
+
 	uclass_find_first_device(UCLASS_MISC, &dev);
 
 	for (; dev; uclass_find_next_device(&dev)) {
@@ -31,20 +33,21 @@ void spl_board_init(void)
 			continue;
 	}
 
-	arch_cpu_init();
-
 	board_early_init_f();
 
 	timer_init();
 
+#ifdef CONFIG_SPL_SERIAL
 	preloader_console_init();
 
 	puts("Normal Boot\n");
+#endif
+
 }
 
 void spl_board_prepare_for_boot(void)
 {
-	imx8_power_off_pd_devices(NULL, 0);
+	board_quiesce_devices();
 }
 
 #ifdef CONFIG_SPL_LOAD_FIT
@@ -59,11 +62,10 @@ int board_fit_config_name_match(const char *name)
 
 void board_init_f(ulong dummy)
 {
-	/* Clear global data */
-	memset((void *)gd, 0, sizeof(gd_t));
-
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
+	arch_cpu_init();
+
 	board_init_r(NULL, 0);
 }
diff --git a/board/freescale/imx8qm_val/Kconfig b/board/freescale/imx8qm_val/Kconfig
new file mode 100644
index 00000000000..56c3040ae3d
--- /dev/null
+++ b/board/freescale/imx8qm_val/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX8QM_LPDDR4_VAL || TARGET_IMX8QM_DDR4_VAL
+
+config SYS_BOARD
+	default "imx8qm_val"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx8qm_val"
+
+config IMX_CONFIG
+	default "board/freescale/imx8qm_val/imximage.cfg"
+
+endif
diff --git a/board/freescale/imx8qm_val/Makefile b/board/freescale/imx8qm_val/Makefile
new file mode 100644
index 00000000000..706bd9a966a
--- /dev/null
+++ b/board/freescale/imx8qm_val/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += imx8qm_val.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/freescale/imx8qm_val/imx8qm_val.c b/board/freescale/imx8qm_val/imx8qm_val.c
new file mode 100644
index 00000000000..3f8721f4288
--- /dev/null
+++ b/board/freescale/imx8qm_val/imx8qm_val.c
@@ -0,0 +1,395 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2018 NXP
+ */
+#include <common.h>
+#include <cpu_func.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ifc.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <env.h>
+#include <i2c.h>
+#include "pca953x.h"
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/snvs_security_sc.h>
+#include <dm.h>
+#include <usb.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <power-domain.h>
+#include <asm/arch/lpcg.h>
+#include <bootm.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ENET_INPUT_PAD_CTRL	((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_NORMAL_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart0_pads[] = {
+	SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
+}
+
+int board_early_init_f(void)
+{
+	sc_pm_clock_rate_t rate = SC_80MHZ;
+	int ret;
+
+	/* Set UART0 clock root to 80 MHz */
+	ret = sc_pm_setup_uart(SC_R_UART_0, rate);
+	if (ret)
+		return ret;
+
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+
+#ifndef CONFIG_DM_ETH
+static iomux_cfg_t pad_enet1[] = {
+	SC_P_ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET1_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET1_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET1_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET1_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET1_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET1_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET1_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET1_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+
+	/* Shared MDIO */
+	SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+};
+
+static iomux_cfg_t pad_enet0[] = {
+	SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+
+	/* Shared MDIO */
+	SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+	if (0 == CONFIG_FEC_ENET_DEV)
+		imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0));
+	else
+		imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1));
+}
+
+static void enet_device_phy_reset(void)
+{
+	struct gpio_desc desc_enet0;
+	struct gpio_desc desc_enet1;
+	int ret;
+
+	ret = dm_gpio_lookup_name("gpio@18_1", &desc_enet0);
+	if (ret)
+		return;
+
+	ret = dm_gpio_request(&desc_enet0, "enet0_reset");
+	if (ret)
+		return;
+	ret = dm_gpio_lookup_name("gpio@18_4", &desc_enet1);
+	if (ret)
+		return;
+
+	ret = dm_gpio_request(&desc_enet1, "enet1_reset");
+	if (ret)
+		return;
+
+	dm_gpio_set_dir_flags(&desc_enet0, GPIOD_IS_OUT);
+	dm_gpio_set_value(&desc_enet0, 0);
+	udelay(50);
+	dm_gpio_set_value(&desc_enet0, 1);
+
+	dm_gpio_set_dir_flags(&desc_enet1, GPIOD_IS_OUT);
+	dm_gpio_set_value(&desc_enet1, 0);
+	udelay(50);
+	dm_gpio_set_value(&desc_enet1, 1);
+
+	/* The board has a long delay for this reset to become stable */
+	mdelay(200);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int ret;
+	struct power_domain pd;
+
+	printf("[%s] %d\n", __func__, __LINE__);
+
+	/* Reset ENET PHY */
+	enet_device_phy_reset();
+
+	if (CONFIG_FEC_ENET_DEV) {
+		if (!power_domain_lookup_name("conn_enet1", &pd))
+			power_domain_on(&pd);
+	} else {
+		if (!power_domain_lookup_name("conn_enet0", &pd))
+			power_domain_on(&pd);
+	}
+
+	setup_iomux_fec();
+
+	ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
+		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+	if (ret)
+		printf("FEC1 MXC: %s:failed\n", __func__);
+
+	return ret;
+}
+#endif
+
+#define MAX7322_I2C_ADDR		0x68
+#define MAX7322_I2C_BUS		2 /* I2C2 */
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->addr == 1) {
+		/* This is needed to drive the pads to 1.8V instead of 1.5V */
+		uint8_t value;
+		struct udevice *bus;
+		struct udevice *i2c_dev = NULL;
+		int ret;
+
+		ret = uclass_get_device_by_seq(UCLASS_I2C, MAX7322_I2C_BUS, &bus);
+		if (ret) {
+			printf("%s: Can't find bus\n", __func__);
+			return -EINVAL;
+		}
+
+		ret = dm_i2c_probe(bus, MAX7322_I2C_ADDR, 0, &i2c_dev);
+		if (ret) {
+			printf("%s: Can't find device id=0x%x\n",
+				__func__, MAX7322_I2C_ADDR);
+			return -ENODEV;
+		}
+
+		i2c_set_chip_offset_len(i2c_dev, 0);
+
+		value = 0x1;
+
+		ret = dm_i2c_write(i2c_dev, 0x0, (const uint8_t *)&value, 1);
+		if (ret) {
+			printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
+			return -EIO;
+		}
+
+		mdelay(1);
+	}
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+#ifndef CONFIG_DM_ETH
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+#endif
+	return 0;
+}
+
+#endif
+
+#define LVDS_ENABLE IMX_GPIO_NR(1, 6)
+#define MIPI_ENABLE IMX_GPIO_NR(1, 7)
+#define DEBUG_LED   IMX_GPIO_NR(2, 15)
+#define IOEXP_RESET IMX_GPIO_NR(1, 12)
+
+
+static void board_gpio_init(void)
+{
+	int ret;
+	struct gpio_desc desc;
+	struct udevice *dev;
+
+	/* enable i2c port expander assert reset line first */
+	/* we can't use dm_gpio_lookup_name for GPIO1_12, because the func will probe the
+	 * uclass list until find the device. The expander device is at begin of the list due to
+	 * I2c nodes is prior than gpio in the DTS. So if the func goes through the uclass list,
+	 * probe to expander will fail, and exit the dm_gpio_lookup_name func. Thus, we always
+	 * fail to get the device
+	*/
+	ret = uclass_get_device_by_seq(UCLASS_GPIO, 1, &dev);
+	if (ret) {
+		printf("%s failed to find GPIO1 device, ret = %d\n", __func__, ret);
+		return;
+	}
+
+	desc.dev = dev;
+	desc.offset = 12;
+	desc.flags = 0;
+
+	ret = dm_gpio_request(&desc, "ioexp_rst");
+	if (ret) {
+		printf("%s request ioexp_rst failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+
+	ret = dm_gpio_lookup_name("GPIO2_15", &desc);
+	if (ret) {
+		printf("%s lookup GPIO@2_15 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "debug_led");
+	if (ret) {
+		printf("%s request debug_led failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+
+	ret = dm_gpio_lookup_name("GPIO1_6", &desc);
+	if (ret) {
+		printf("%s lookup GPIO@1_6 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "lvds_enable");
+	if (ret) {
+		printf("%s request lvds_enable failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	ret = dm_gpio_lookup_name("GPIO1_7", &desc);
+	if (ret) {
+		printf("%s lookup GPIO@1_7 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "mipi_enable");
+	if (ret) {
+		printf("%s request mipi_enable failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+}
+
+int checkboard(void)
+{
+#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_VAL
+	puts("Board: iMX8QM LPDDR4 VAL\n");
+#else
+	puts("Board: iMX8QM DDR4 VAL\n");
+#endif
+
+	print_bootinfo();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	board_gpio_init();
+
+
+#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO
+	{
+		int ret = snvs_security_sc_init();
+
+		if (ret)
+			return ret;
+	}
+#endif
+
+	return 0;
+}
+
+void board_quiesce_devices(void)
+{
+	const char *power_on_devices[] = {
+		"dma_lpuart0",
+	};
+
+	imx8_power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices));
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(void)
+{
+	/* TODO */
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return 0;
+}
+#endif
+
+int board_late_init(void)
+{
+	build_info();
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "VAL");
+	env_set("board_rev", "iMX8QM");
+#endif
+
+	env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+	env_set("sec_boot", "yes");
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	return 0;
+}
diff --git a/board/freescale/imx8qm_val/imximage.cfg b/board/freescale/imx8qm_val/imximage.cfg
new file mode 100644
index 00000000000..7dc6b93eb58
--- /dev/null
+++ b/board/freescale/imx8qm_val/imximage.cfg
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM SD 0x400
+/* SoC type IMX8QM */
+SOC_TYPE IMX8QM
+/* Append seco container image */
+APPEND mx8qm-ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qm-mek-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 spl/u-boot-spl.bin 0x00100000
diff --git a/board/freescale/imx8qm_val/spl.c b/board/freescale/imx8qm_val/spl.c
new file mode 100644
index 00000000000..1d930304872
--- /dev/null
+++ b/board/freescale/imx8qm_val/spl.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <bootm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_board_init(void)
+{
+	struct udevice *dev;
+
+	uclass_find_first_device(UCLASS_MISC, &dev);
+
+	for (; dev; uclass_find_next_device(&dev)) {
+		if (device_probe(dev))
+			continue;
+	}
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	puts("Normal Boot\n");
+}
+
+void spl_board_prepare_for_boot(void)
+{
+	board_quiesce_devices();
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	arch_cpu_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/board/freescale/imx8qm_val/uboot-container.cfg b/board/freescale/imx8qm_val/uboot-container.cfg
new file mode 100644
index 00000000000..6cc47cd1027
--- /dev/null
+++ b/board/freescale/imx8qm_val/uboot-container.cfg
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#define __ASSEMBLY__
+
+/* This file is to create a container image could be loaded by SPL */
+BOOT_FROM SD 0x400
+SOC_TYPE IMX8QM
+CONTAINER
+IMAGE A35 bl31.bin	0x80000000
+IMAGE A35 u-boot.bin	CONFIG_SYS_TEXT_BASE
diff --git a/board/freescale/imx8qxp_mek/Kconfig b/board/freescale/imx8qxp_mek/Kconfig
index b9aab3789ee..cbde73d4ee6 100644
--- a/board/freescale/imx8qxp_mek/Kconfig
+++ b/board/freescale/imx8qxp_mek/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_IMX8QXP_MEK
+if TARGET_IMX8QXP_MEK || TARGET_IMX8DX_MEK
 
 config SYS_BOARD
 	default "imx8qxp_mek"
diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
index 21cfa142f3b..80c079a7896 100644
--- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c
+++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
@@ -21,9 +21,17 @@
 #include <asm/arch/snvs_security_sc.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/sys_proto.h>
+#include <usb.h>
+#include "../common/tcpc.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define ENET_INPUT_PAD_CTRL	((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_NORMAL_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
 #define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
 			 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
 			 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
@@ -85,35 +93,250 @@ static inline void board_gpio_init(void) {}
 #if IS_ENABLED(CONFIG_FEC_MXC)
 #include <miiphy.h>
 
+#ifndef CONFIG_DM_ETH
+static iomux_cfg_t pad_enet1[] = {
+	SC_P_SPDIF0_TX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_SPDIF0_RX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ESAI0_TX3_RX2 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ESAI0_TX2_RX3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ESAI0_TX1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ESAI0_TX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ESAI0_SCKR | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ESAI0_TX4_RX1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ESAI0_TX5_RX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ESAI0_FST  | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ESAI0_SCKT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ESAI0_FSR  | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+
+	/* Shared MDIO */
+	SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+};
+
+static iomux_cfg_t pad_enet0[] = {
+	SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+
+	/* Shared MDIO */
+	SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+	if (0 == CONFIG_FEC_ENET_DEV)
+		imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0));
+	else
+		imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1));
+}
+
+static void enet_device_phy_reset(void)
+{
+	struct gpio_desc desc;
+	int ret;
+
+	/* The BB_PER_RST_B will reset the ENET1 PHY */
+	if (0 == CONFIG_FEC_ENET_DEV) {
+		ret = dm_gpio_lookup_name("gpio@1a_4", &desc);
+		if (ret)
+			return;
+
+		ret = dm_gpio_request(&desc, "enet0_reset");
+		if (ret)
+			return;
+
+		dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+		dm_gpio_set_value(&desc, 0);
+		udelay(50);
+		dm_gpio_set_value(&desc, 1);
+	}
+
+	/* The board has a long delay for this reset to become stable */
+	mdelay(200);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int ret;
+	struct power_domain pd;
+
+	printf("[%s] %d\n", __func__, __LINE__);
+
+	/* Reset ENET PHY */
+	enet_device_phy_reset();
+
+	if (CONFIG_FEC_ENET_DEV) {
+		if (!power_domain_lookup_name("conn_enet1", &pd))
+			power_domain_on(&pd);
+	} else {
+		if (!power_domain_lookup_name("conn_enet0", &pd))
+			power_domain_on(&pd);
+	}
+
+	setup_iomux_fec();
+
+	ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
+		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+	if (ret)
+		printf("FEC1 MXC: %s:failed\n", __func__);
+
+	return ret;
+}
+
 int board_phy_config(struct phy_device *phydev)
 {
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
 
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
 
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
 	return 0;
 }
 #endif
+#endif
 
 int checkboard(void)
 {
+#ifdef CONFIG_TARGET_IMX8DX_MEK
+	puts("Board: iMX8DX MEK\n");
+#else
 	puts("Board: iMX8QXP MEK\n");
+#endif
 
-	build_info();
 	print_bootinfo();
 
 	return 0;
 }
 
+#ifdef CONFIG_USB
+
+#ifdef CONFIG_USB_TCPC
+struct gpio_desc type_sel_desc;
+static iomux_cfg_t ss_mux_gpio[] = {
+	SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+struct tcpc_port port;
+struct tcpc_port_config port_config = {
+	.i2c_bus = 1,
+	.addr = 0x50,
+	.port_type = TYPEC_PORT_DFP,
+};
+
+void ss_mux_select(enum typec_cc_polarity pol)
+{
+	if (pol == TYPEC_POLARITY_CC1)
+		dm_gpio_set_value(&type_sel_desc, 0);
+	else
+		dm_gpio_set_value(&type_sel_desc, 1);
+}
+
+static void setup_typec(void)
+{
+	int ret;
+	struct gpio_desc typec_en_desc;
+
+	imx8_iomux_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
+	ret = dm_gpio_lookup_name("GPIO5_9", &type_sel_desc);
+	if (ret) {
+		printf("%s lookup GPIO5_9 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&type_sel_desc, "typec_sel");
+	if (ret) {
+		printf("%s request typec_sel failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&type_sel_desc, GPIOD_IS_OUT);
+
+	ret = dm_gpio_lookup_name("gpio@1a_7", &typec_en_desc);
+	if (ret) {
+		printf("%s lookup gpio@1a_7 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&typec_en_desc, "typec_en");
+	if (ret) {
+		printf("%s request typec_en failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	/* Enable SS MUX */
+	dm_gpio_set_dir_flags(&typec_en_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	ret = tcpc_init(&port, port_config, &ss_mux_select);
+	if (ret) {
+		printf("%s: tcpc init failed, err=%d\n", __func__, ret);
+		return;
+	}
+}
+#endif
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	if (index == 1) {
+		if (init == USB_INIT_HOST) {
+#ifdef CONFIG_USB_TCPC
+			ret = tcpc_setup_dfp_mode(&port);
+#endif
+#ifdef CONFIG_USB_CDNS3_GADGET
+		} else {
+#ifdef CONFIG_USB_TCPC
+			ret = tcpc_setup_ufp_mode(&port);
+			printf("%d setufp mode %d\n", index, ret);
+#endif
+#endif
+		}
+	}
+
+	return ret;
+
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	if (index == 1) {
+		if (init == USB_INIT_HOST) {
+#ifdef CONFIG_USB_TCPC
+			ret = tcpc_disable_src_vbus(&port);
+#endif
+		}
+	}
+
+	return ret;
+}
+#endif
+
 int board_init(void)
 {
 	board_gpio_init();
 
+#if defined(CONFIG_USB) && defined(CONFIG_USB_TCPC)
+	setup_typec();
+#endif
+
 #ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO
 	{
 		int ret = snvs_security_sc_init();
@@ -126,12 +349,27 @@ int board_init(void)
 	return 0;
 }
 
+void board_quiesce_devices(void)
+{
+	const char *power_on_devices[] = {
+		"dma_lpuart0",
+
+		/* HIFI DSP boot */
+		"audio_sai0",
+		"audio_ocram",
+	};
+
+	imx8_power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices));
+}
+
 /*
  * Board specific reset that is system reset.
  */
 void reset_cpu(void)
 {
-	/* TODO */
+	sc_pm_reboot(-1, SC_PM_RESET_TYPE_COLD);
+	while(1);
+
 }
 
 #ifdef CONFIG_OF_BOARD_SETUP
@@ -141,30 +379,65 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 }
 #endif
 
-int board_mmc_get_env_dev(int devno)
-{
-	return devno;
-}
-
 int board_late_init(void)
 {
 	char *fdt_file;
 	bool m4_booted;
 
+	build_info();
+
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	env_set("board_name", "MEK");
+#ifdef CONFIG_TARGET_IMX8DX_MEK
+	env_set("board_rev", "iMX8DX");
+#else
 	env_set("board_rev", "iMX8QXP");
 #endif
+#endif
+
+	env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+	env_set("sec_boot", "yes");
+#endif
 
 	fdt_file = env_get("fdt_file");
 	m4_booted = m4_parts_booted();
 
 	if (fdt_file && !strcmp(fdt_file, "undefined")) {
+#ifdef CONFIG_TARGET_IMX8DX_MEK
+		if (m4_booted)
+			env_set("fdt_file", "imx8dx-mek-rpmsg.dtb");
+		else
+			env_set("fdt_file", "imx8dx-mek.dtb");
+#else
 		if (m4_booted)
 			env_set("fdt_file", "imx8qxp-mek-rpmsg.dtb");
 		else
 			env_set("fdt_file", "imx8qxp-mek.dtb");
+#endif
 	}
 
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
 	return 0;
 }
+
+#ifdef CONFIG_ANDROID_SUPPORT
+bool is_power_key_pressed(void) {
+	sc_bool_t status = SC_FALSE;
+
+	sc_misc_get_button_status(-1, &status);
+	return (bool)status;
+}
+#endif
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+int is_recovery_key_pressing(void)
+{
+	return 0; /* TODO */
+}
+#endif /* CONFIG_ANDROID_RECOVERY */
+#endif /* CONFIG_FSL_FASTBOOT */
diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c
index ae6b64ff6ea..2ea710cb08c 100644
--- a/board/freescale/imx8qxp_mek/spl.c
+++ b/board/freescale/imx8qxp_mek/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -22,6 +22,7 @@
 #include <asm/arch/imx8-pins.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/sys_proto.h>
+#include <bootm.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -39,6 +40,8 @@ void spl_board_init(void)
 {
 	struct udevice *dev;
 
+	uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev);
+
 	uclass_find_first_device(UCLASS_MISC, &dev);
 
 	for (; dev; uclass_find_next_device(&dev)) {
@@ -46,8 +49,6 @@ void spl_board_init(void)
 			continue;
 	}
 
-	arch_cpu_init();
-
 	board_early_init_f();
 
 	timer_init();
@@ -55,14 +56,16 @@ void spl_board_init(void)
 	imx8_iomux_setup_multiple_pads(usdhc2_sd_pwr, ARRAY_SIZE(usdhc2_sd_pwr));
 	gpio_direction_output(USDHC2_SD_PWR, 0);
 
+#ifdef CONFIG_SPL_SERIAL
 	preloader_console_init();
 
 	puts("Normal Boot\n");
+#endif
 }
 
 void spl_board_prepare_for_boot(void)
 {
-	imx8_power_off_pd_devices(NULL, 0);
+	board_quiesce_devices();
 }
 
 #ifdef CONFIG_SPL_LOAD_FIT
@@ -77,11 +80,10 @@ int board_fit_config_name_match(const char *name)
 
 void board_init_f(ulong dummy)
 {
-	/* Clear global data */
-	memset((void *)gd, 0, sizeof(gd_t));
-
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
+	arch_cpu_init();
+
 	board_init_r(NULL, 0);
 }
diff --git a/board/freescale/imx8qxp_val/Kconfig b/board/freescale/imx8qxp_val/Kconfig
new file mode 100644
index 00000000000..549020e98de
--- /dev/null
+++ b/board/freescale/imx8qxp_val/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX8QXP_LPDDR4_VAL || TARGET_IMX8QXP_DDR3_VAL || TARGET_IMX8X_17X17_VAL
+
+config SYS_BOARD
+	default "imx8qxp_val"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx8qxp_val"
+
+config IMX_CONFIG
+	default "board/freescale/imx8qxp_val/imximage.cfg"
+
+endif
diff --git a/board/freescale/imx8qxp_val/Makefile b/board/freescale/imx8qxp_val/Makefile
new file mode 100644
index 00000000000..0b4e005a69c
--- /dev/null
+++ b/board/freescale/imx8qxp_val/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2017-2019 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += imx8qxp_val.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/freescale/imx8qxp_val/imx8qxp_val.c b/board/freescale/imx8qxp_val/imx8qxp_val.c
new file mode 100644
index 00000000000..9a93e2f4c7f
--- /dev/null
+++ b/board/freescale/imx8qxp_val/imx8qxp_val.c
@@ -0,0 +1,499 @@
+/*
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ifc.h>
+#include <fdt_support.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <cpu_func.h>
+#include <env.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include "pca953x.h"
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/snvs_security_sc.h>
+#include <dm.h>
+#include <usb.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/dma.h>
+#include <power-domain.h>
+#include <asm/arch/lpcg.h>
+#include <bootm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ESDHC_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define GPMI_NAND_PAD_CTRL	 ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) \
+				  | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ESDHC_CLK_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+
+#define ENET_INPUT_PAD_CTRL	((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_NORMAL_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+
+#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define I2C_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
+						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_NAND_MXS
+static iomux_cfg_t gpmi_nand_pads[] = {
+	SC_P_EMMC0_CLK | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA0 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA1 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA2 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA3 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA4 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA5 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA6 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_DATA7 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_STROBE | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_EMMC0_RESET_B | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_USDHC1_CMD | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_USDHC1_DATA2 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_USDHC1_DATA3 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_USDHC1_DATA0 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+
+	/* i.MX8QXP NAND use nand_re_dqs_pins */
+	SC_P_USDHC1_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+	SC_P_USDHC1_VSELECT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL),
+
+};
+
+static void setup_iomux_gpmi_nand(void)
+{
+	imx8_iomux_setup_multiple_pads(gpmi_nand_pads, ARRAY_SIZE(gpmi_nand_pads));
+}
+
+static void imx8qxp_gpmi_nand_initialize(void)
+{
+	int ret;
+
+	ret = sc_pm_set_resource_power_mode(-1, SC_R_NAND, SC_PM_PW_MODE_ON);
+	if (ret)
+		return;
+
+	init_clk_gpmi_nand();
+	setup_iomux_gpmi_nand();
+}
+#endif
+#endif
+
+static iomux_cfg_t uart0_pads[] = {
+	SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
+}
+
+int board_early_init_f(void)
+{
+	sc_pm_clock_rate_t rate = SC_80MHZ;
+	int ret;
+
+	/* Set UART0 clock root to 80 MHz */
+	ret = sc_pm_setup_uart(SC_R_UART_0, rate);
+	if (ret)
+		return ret;
+
+	setup_iomux_uart();
+
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_NAND_MXS
+	imx8qxp_gpmi_nand_initialize();
+#endif
+#endif
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+
+#ifndef CONFIG_DM_ETH
+static iomux_cfg_t pad_enet1[] = {
+	SC_P_SPDIF0_TX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_SPDIF0_RX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ESAI0_TX3_RX2 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ESAI0_TX2_RX3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ESAI0_TX1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ESAI0_TX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ESAI0_SCKR | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ESAI0_TX4_RX1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ESAI0_TX5_RX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ESAI0_FST  | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ESAI0_SCKT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ESAI0_FSR  | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+
+	/* Shared MDIO */
+	SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+};
+
+static iomux_cfg_t pad_enet0[] = {
+	SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
+	SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+
+	/* Shared MDIO */
+	SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+	SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+	if (0 == CONFIG_FEC_ENET_DEV)
+		imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0));
+	else
+		imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1));
+}
+
+static void enet_device_phy_reset(void)
+{
+	struct gpio_desc desc_enet0;
+	struct gpio_desc desc_enet1;
+	int ret;
+
+	ret = dm_gpio_lookup_name("gpio@18_1", &desc_enet0);
+	if (ret)
+		return;
+
+	ret = dm_gpio_request(&desc_enet0, "enet0_reset");
+	if (ret)
+		return;
+
+	ret = dm_gpio_lookup_name("gpio@18_4", &desc_enet1);
+	if (ret)
+		return;
+
+	ret = dm_gpio_request(&desc_enet1, "enet1_reset");
+	if (ret)
+		return;
+
+	dm_gpio_set_dir_flags(&desc_enet0, GPIOD_IS_OUT);
+	dm_gpio_set_value(&desc_enet0, 0);
+	udelay(50);
+	dm_gpio_set_value(&desc_enet0, 1);
+
+	dm_gpio_set_dir_flags(&desc_enet1, GPIOD_IS_OUT);
+	dm_gpio_set_value(&desc_enet1, 0);
+	udelay(50);
+	dm_gpio_set_value(&desc_enet1, 1);
+
+	/* The board has a long delay for this reset to become stable */
+	mdelay(200);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int ret;
+	struct power_domain pd;
+
+	printf("[%s] %d\n", __func__, __LINE__);
+
+	/* Reset ENET PHY */
+	enet_device_phy_reset();
+
+	if (CONFIG_FEC_ENET_DEV) {
+		if (!power_domain_lookup_name("conn_enet1", &pd))
+			power_domain_on(&pd);
+	} else {
+		if (!power_domain_lookup_name("conn_enet0", &pd))
+			power_domain_on(&pd);
+	}
+
+	setup_iomux_fec();
+
+	ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
+		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+	if (ret)
+		printf("FEC1 MXC: %s:failed\n", __func__);
+
+	return ret;
+}
+#endif
+
+#define MAX7322_I2C_ADDR		0x68
+#define MAX7322_I2C_BUS		0 /* I2C1 */
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->addr == 1) {
+		/* This is needed to drive the pads to 1.8V instead of 1.5V */
+		uint8_t value;
+		struct udevice *bus;
+		struct udevice *i2c_dev = NULL;
+		int ret;
+
+		ret = uclass_get_device_by_seq(UCLASS_I2C, MAX7322_I2C_BUS, &bus);
+		if (ret) {
+			printf("%s: Can't find bus\n", __func__);
+			return -EINVAL;
+		}
+
+		ret = dm_i2c_probe(bus, MAX7322_I2C_ADDR, 0, &i2c_dev);
+		if (ret) {
+			printf("%s: Can't find device id=0x%x\n",
+				__func__, MAX7322_I2C_ADDR);
+			return -ENODEV;
+		}
+
+		i2c_set_chip_offset_len(i2c_dev, 0);
+
+		value = 0x1;
+
+		ret = dm_i2c_write(i2c_dev, 0x0, (const uint8_t *)&value, 1);
+		if (ret) {
+			printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
+			return -EIO;
+		}
+
+		mdelay(1);
+	}
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+#ifndef CONFIG_DM_ETH
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+#endif
+
+	return 0;
+}
+#endif
+
+#define DEBUG_LED   IMX_GPIO_NR(3, 23)
+#define IOEXP_RESET IMX_GPIO_NR(0, 19)
+#define BB_PWR_EN IMX_GPIO_NR(5, 9)
+
+static iomux_cfg_t board_gpios[] = {
+	SC_P_QSPI0B_SS0_B | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+	SC_P_MCLK_IN0 | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+	SC_P_ENET0_REFCLK_125M_25M |  MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+static void board_gpio_init(void)
+{
+	int ret;
+	struct gpio_desc desc;
+	struct udevice *dev;
+
+	imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios));
+
+	/* enable i2c port expander assert reset line first */
+	/* we can't use dm_gpio_lookup_name for GPIO1_12, because the func will probe the
+	 * uclass list until find the device. The expander device is at begin of the list due to
+	 * I2c nodes is prior than gpio in the DTS. So if the func goes through the uclass list,
+	 * probe to expander will fail, and exit the dm_gpio_lookup_name func. Thus, we always
+	 * fail to get the device
+	*/
+	ret = uclass_get_device_by_seq(UCLASS_GPIO, 0, &dev);
+	if (ret) {
+		printf("%s failed to find GPIO1 device, ret = %d\n", __func__, ret);
+		return;
+	}
+
+	desc.dev = dev;
+	desc.offset = 19;
+	desc.flags = 0;
+
+	ret = dm_gpio_request(&desc, "ioexp_rst");
+	if (ret) {
+		printf("%s request ioexp_rst failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	ret = dm_gpio_lookup_name("GPIO3_23", &desc);
+	if (ret) {
+		printf("%s lookup GPIO@3_23 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "debug_led");
+	if (ret) {
+		printf("%s request debug_led failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	ret = dm_gpio_lookup_name("GPIO5_9", &desc);
+	if (ret) {
+		printf("%s lookup GPIO@5_9 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "bb_pwr_en");
+	if (ret) {
+		printf("%s request bb_pwr_en failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+}
+
+int checkboard(void)
+{
+#if defined(CONFIG_TARGET_IMX8QXP_DDR3_VAL)
+	puts("Board: iMX8QXP DDR3 VAL\n");
+#elif defined(CONFIG_TARGET_IMX8X_17X17_VAL)
+	puts("Board: iMX8X(QXP/DX) 17x17 Validation Board\n");
+#else
+	puts("Board: iMX8QXP LPDDR4 VAL\n");
+#endif
+
+	print_bootinfo();
+
+	return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	if (index == 0) {
+		if (init == USB_INIT_DEVICE) {
+#if !CONFIG_IS_ENABLED(DM_USB_GADGET) && !CONFIG_IS_ENABLED(DM_USB)
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0, SC_PM_PW_MODE_ON);
+			if (ret)
+				printf("conn_usb0 Power up failed! (error = %d)\n", ret);
+
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0_PHY, SC_PM_PW_MODE_ON);
+			if (ret)
+				printf("conn_usb0_phy Power up failed! (error = %d)\n", ret);
+#endif
+		}
+	}
+	return ret;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	if (index == 0) {
+		if (init == USB_INIT_DEVICE) {
+#if !CONFIG_IS_ENABLED(DM_USB_GADGET) && !CONFIG_IS_ENABLED(DM_USB)
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0, SC_PM_PW_MODE_OFF);
+			if (ret)
+				printf("conn_usb0 Power down failed! (error = %d)\n", ret);
+
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0_PHY, SC_PM_PW_MODE_OFF);
+			if (ret)
+				printf("conn_usb0_phy Power down failed! (error = %d)\n", ret);
+#endif
+		}
+	}
+	return ret;
+}
+
+int board_init(void)
+{
+	board_gpio_init();
+
+#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO
+	{
+		int ret = snvs_security_sc_init();
+
+		if (ret)
+			return ret;
+	}
+#endif
+
+	return 0;
+}
+
+void board_quiesce_devices(void)
+{
+	const char *power_on_devices[] = {
+		"dma_lpuart0",
+
+		/* HIFI DSP boot */
+		"audio_sai0",
+		"audio_ocram",
+	};
+
+	imx8_power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices));
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(void)
+{
+	/* TODO */
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return 0;
+}
+#endif
+
+
+int board_late_init(void)
+{
+	build_info();
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "VAL");
+	env_set("board_rev", "iMX8QXP");
+#endif
+
+	env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+	env_set("sec_boot", "yes");
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	return 0;
+}
diff --git a/board/freescale/imx8qxp_val/imximage.cfg b/board/freescale/imx8qxp_val/imximage.cfg
new file mode 100644
index 00000000000..259a1646bf9
--- /dev/null
+++ b/board/freescale/imx8qxp_val/imximage.cfg
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ *
+ * Refer doc/README.imx8image for more details about how-to configure
+ * and create imx8image boot image
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+BOOT_FROM SD 0x400
+/* SoC type IMX8QX */
+SOC_TYPE IMX8QX
+/* Append seco container image */
+APPEND ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qx-mek-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 spl/u-boot-spl.bin 0x00100000
diff --git a/board/freescale/imx8qxp_val/spl.c b/board/freescale/imx8qxp_val/spl.c
new file mode 100644
index 00000000000..1d930304872
--- /dev/null
+++ b/board/freescale/imx8qxp_val/spl.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <bootm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_board_init(void)
+{
+	struct udevice *dev;
+
+	uclass_find_first_device(UCLASS_MISC, &dev);
+
+	for (; dev; uclass_find_next_device(&dev)) {
+		if (device_probe(dev))
+			continue;
+	}
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	puts("Normal Boot\n");
+}
+
+void spl_board_prepare_for_boot(void)
+{
+	board_quiesce_devices();
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	arch_cpu_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/board/freescale/imx8qxp_val/uboot-container.cfg b/board/freescale/imx8qxp_val/uboot-container.cfg
new file mode 100644
index 00000000000..81658118185
--- /dev/null
+++ b/board/freescale/imx8qxp_val/uboot-container.cfg
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#define __ASSEMBLY__
+
+/* This file is to create a container image could be loaded by SPL */
+BOOT_FROM SD 0x400
+SOC_TYPE IMX8QX
+CONTAINER
+IMAGE A35 bl31.bin	0x80000000
+IMAGE A35 u-boot.bin	CONFIG_SYS_TEXT_BASE
diff --git a/board/freescale/imx8ulp_evk/Kconfig b/board/freescale/imx8ulp_evk/Kconfig
index 1e461ee1da7..351f54c2460 100644
--- a/board/freescale/imx8ulp_evk/Kconfig
+++ b/board/freescale/imx8ulp_evk/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_IMX8ULP_EVK
+if TARGET_IMX8ULP_EVK || TARGET_IMX8ULP_9X9_EVK
 
 config SYS_BOARD
 	default "imx8ulp_evk"
diff --git a/board/freescale/imx8ulp_evk/Makefile b/board/freescale/imx8ulp_evk/Makefile
index b2e72b4e85d..4444fb8c6fe 100644
--- a/board/freescale/imx8ulp_evk/Makefile
+++ b/board/freescale/imx8ulp_evk/Makefile
@@ -3,5 +3,11 @@
 obj-y   += imx8ulp_evk.o
 
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o ddr_init.o lpddr4_timing.o
+obj-y += spl.o
+obj-$(CONFIG_TARGET_IMX8ULP_9X9_EVK) += lpddr4_timing_9x9.o
+ifdef CONFIG_IMX8ULP_ND_MODE
+obj-$(CONFIG_TARGET_IMX8ULP_EVK) += lpddr4_timing_266.o
+else
+obj-$(CONFIG_TARGET_IMX8ULP_EVK) += lpddr4_timing.o
+endif
 endif
diff --git a/board/freescale/imx8ulp_evk/ddr_init.c b/board/freescale/imx8ulp_evk/ddr_init.c
deleted file mode 100644
index f4238d29b3a..00000000000
--- a/board/freescale/imx8ulp_evk/ddr_init.c
+++ /dev/null
@@ -1,207 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-/*
- * Copyright 2021 NXP
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/ddr.h>
-#include <asm/arch/imx-regs.h>
-
-#define DENALI_CTL_00		(DDR_CTL_BASE_ADDR)
-#define CTL_START		0x1
-
-#define DENALI_CTL_03		(DDR_CTL_BASE_ADDR + 4 * 3)
-#define DENALI_CTL_197		(DDR_CTL_BASE_ADDR + 4 * 197)
-#define DENALI_CTL_250		(DDR_CTL_BASE_ADDR + 4 * 250)
-#define DENALI_CTL_251		(DDR_CTL_BASE_ADDR + 4 * 251)
-#define DENALI_CTL_266		(DDR_CTL_BASE_ADDR + 4 * 266)
-#define DFI_INIT_COMPLETE	0x2
-
-#define DENALI_CTL_614		(DDR_CTL_BASE_ADDR + 4 * 614)
-#define DENALI_CTL_615		(DDR_CTL_BASE_ADDR + 4 * 615)
-
-#define DENALI_PI_00		(DDR_PI_BASE_ADDR)
-#define PI_START		0x1
-
-#define DENALI_PI_04		(DDR_PI_BASE_ADDR + 4 * 4)
-#define DENALI_PI_11		(DDR_PI_BASE_ADDR + 4 * 11)
-#define DENALI_PI_12		(DDR_PI_BASE_ADDR + 4 * 12)
-#define DENALI_CTL_23		(DDR_CTL_BASE_ADDR + 4 * 23)
-#define DENALI_CTL_25		(DDR_CTL_BASE_ADDR + 4 * 25)
-
-#define DENALI_PHY_1624		(DDR_PHY_BASE_ADDR + 4 * 1624)
-#define DENALI_PHY_1537		(DDR_PHY_BASE_ADDR + 4 * 1537)
-#define PHY_FREQ_SEL_MULTICAST_EN(X)	((X) << 8)
-#define PHY_FREQ_SEL_INDEX(X)		((X) << 16)
-
-#define DENALI_PHY_1547		(DDR_PHY_BASE_ADDR + 4 * 1547)
-#define DENALI_PHY_1555		(DDR_PHY_BASE_ADDR + 4 * 1555)
-#define DENALI_PHY_1564		(DDR_PHY_BASE_ADDR + 4 * 1564)
-#define DENALI_PHY_1565		(DDR_PHY_BASE_ADDR + 4 * 1565)
-
-int ddr_calibration(unsigned int fsp_table[3])
-{
-	u32 reg_val;
-	u32 int_status_init, phy_freq_req, phy_freq_type;
-	u32 lock_0, lock_1, lock_2;
-	u32 freq_chg_pt, freq_chg_cnt;
-
-	reg_val = readl(DENALI_CTL_250);
-	if (((reg_val >> 16) & 0x3) == 1)
-		freq_chg_cnt = 2;
-	else
-		freq_chg_cnt = 3;
-
-	reg_val = readl(DENALI_PI_12);
-	if (reg_val == 0x3) {
-		freq_chg_pt = 1;
-	} else if (reg_val == 0x7) {
-		freq_chg_pt = 2;
-	} else {
-		printf("frequency map(0x%x) is wrong, please check!\r\n", reg_val);
-		return -1;
-	}
-
-	debug("%s\n", __func__);
-
-	/* Assert PI_START parameter and then assert START parameter in Controller. */
-	reg_val = readl(DENALI_PI_00) | PI_START;
-	writel(reg_val, DENALI_PI_00);
-
-	reg_val = readl(DENALI_CTL_00) | CTL_START;
-	writel(reg_val, DENALI_CTL_00);
-
-	/* Poll for init_done_bit in Controller interrupt status register (INT_STATUS_INIT) */
-	do {
-		if (!freq_chg_cnt) {
-			int_status_init = (readl(DENALI_CTL_266) >> 8) & 0xff;
-			/* DDR subsystem is ready for traffic. */
-			if (int_status_init & DFI_INIT_COMPLETE) {
-				printf("complete\n");
-				break;
-			}
-		}
-
-		/*
-		 * During leveling, PHY will request for freq change and SoC clock
-		 * logic should provide requested frequency, Polling SIM LPDDR_CTRL2
-		 * Bit phy_freq_chg_req until be 1'b1
-		 */
-		reg_val = readl(AVD_SIM_LPDDR_CTRL2);
-		phy_freq_req = (reg_val >> 7) & 0x1;
-
-		if (phy_freq_req) {
-			phy_freq_type = reg_val & 0x1F;
-			if (!phy_freq_type) {
-				printf("Poll for freq_chg_req on SIM register and change to F0 frequency.\n");
-				set_ddr_clk(fsp_table[phy_freq_type] >> 1);
-
-				/* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */
-				reg_val = readl(AVD_SIM_LPDDR_CTRL2);
-				writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2);
-			} else if (phy_freq_type == 0x01) {
-				printf("Poll for freq_chg_req on SIM register and change to F1 frequency.\n");
-				set_ddr_clk(fsp_table[phy_freq_type] >> 1);
-
-				/* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */
-				reg_val = readl(AVD_SIM_LPDDR_CTRL2);
-				writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2);
-				if (freq_chg_pt == 1)
-					freq_chg_cnt--;
-			} else if (phy_freq_type == 0x02) {
-				printf("Poll for freq_chg_req on SIM register and change to F2 frequency.\n");
-				set_ddr_clk(fsp_table[phy_freq_type] >> 1);
-
-				/* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */
-				reg_val = readl(AVD_SIM_LPDDR_CTRL2);
-				writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2);
-				if (freq_chg_pt == 2)
-					freq_chg_cnt--;
-			}
-			reg_val = readl(AVD_SIM_LPDDR_CTRL2);
-		}
-	} while (1);
-
-	/* Check PLL lock status */
-	lock_0 = readl(DENALI_PHY_1564) & 0xffff;
-	lock_1 = (readl(DENALI_PHY_1564) >> 16) & 0xffff;
-	lock_2 = readl(DENALI_PHY_1565) & 0xffff;
-
-	if ((lock_0 & 0x3) != 0x3 || (lock_1 & 0x3) != 0x3 || (lock_2 & 0x3) != 0x3) {
-		printf("De-Skew PLL failed to lock\n");
-		printf("lock_0=0x%x, lock_1=0x%x, lock_2=0x%x\n", lock_0, lock_1, lock_2);
-		return -1;
-	}
-
-	printf("De-Skew PLL is locked and ready\n");
-	return 0;
-}
-
-int ddr_init(struct dram_timing_info2 *dram_timing)
-{
-	int i;
-
-	debug("%s\n", __func__);
-
-	set_ddr_clk(dram_timing->fsp_table[0] >> 1); /* Set to boot freq */
-
-	/* Initialize CTL registers */
-	for (i = 0; i < dram_timing->ctl_cfg_num; i++)
-		writel(dram_timing->ctl_cfg[i].val, (ulong)dram_timing->ctl_cfg[i].reg);
-
-	/* Initialize PI registers */
-	for (i = 0; i < dram_timing->pi_cfg_num; i++)
-		writel(dram_timing->pi_cfg[i].val, (ulong)dram_timing->pi_cfg[i].reg);
-
-	/* Write PHY regiters for all 3 frequency points (48Mhz/384Mhz/528Mhz): f1_index=0 */
-	writel(PHY_FREQ_SEL_MULTICAST_EN(1) | PHY_FREQ_SEL_INDEX(0), DENALI_PHY_1537);
-	for (i = 0; i < dram_timing->phy_f1_cfg_num; i++)
-		writel(dram_timing->phy_f1_cfg[i].val, (ulong)dram_timing->phy_f1_cfg[i].reg);
-
-	/* Write PHY regiters for freqency point 2 (528Mhz): f2_index=1 */
-	writel(PHY_FREQ_SEL_MULTICAST_EN(0) | PHY_FREQ_SEL_INDEX(1), DENALI_PHY_1537);
-	for (i = 0; i < dram_timing->phy_f2_cfg_num; i++)
-		writel(dram_timing->phy_f2_cfg[i].val, (ulong)dram_timing->phy_f2_cfg[i].reg);
-
-	/* Re-enable MULTICAST mode */
-	writel(PHY_FREQ_SEL_MULTICAST_EN(1) | PHY_FREQ_SEL_INDEX(0), DENALI_PHY_1537);
-
-	return ddr_calibration(dram_timing->fsp_table);
-}
-
-void enable_bypass_mode(void)
-{
-	u32 reg_val;
-
-	/* PI_INIT_LVL_EN=0x0 (DENALI_PI_04) */
-	reg_val = readl(DENALI_PI_04) & ~0x1;
-	writel(reg_val, DENALI_PI_04);
-
-	/* PI_FREQ_MAP=0x1 (DENALI_PI_12) */
-	writel(0x1, DENALI_PI_12);
-
-	/* PI_INIT_WORK_FREQ=0x0 (DENALI_PI_11) */
-	reg_val = readl(DENALI_PI_11) & ~(0x1f << 8);
-	writel(reg_val, DENALI_PI_11);
-
-	/* DFIBUS_FREQ_INIT=0x0 (DENALI_CTL_23) */
-	reg_val = readl(DENALI_CTL_23) & ~(0x3 << 24);
-	writel(reg_val, DENALI_CTL_23);
-
-	/* PHY_LP4_BOOT_DISABLE=0x0 (DENALI_PHY_1547) */
-	reg_val = readl(DENALI_PHY_1547) & ~(0x1 << 8);
-	writel(reg_val, DENALI_PHY_1547);
-
-	/* PHY_PLL_BYPASS=0x1 (DENALI_PHY_1624) */
-	reg_val = readl(DENALI_PHY_1624) | 0x1;
-	writel(reg_val, DENALI_PHY_1624);
-
-	/* PHY_LP4_BOOT_PLL_BYPASS to 0x1 (DENALI_PHY_1555) */
-	reg_val = readl(DENALI_PHY_1555) | 0x1;
-	writel(reg_val, DENALI_PHY_1555);
-
-	/* FREQ_CHANGE_TYPE_F0 = 0x0/FREQ_CHANGE_TYPE_F1 = 0x1/FREQ_CHANGE_TYPE_F2 = 0x2 */
-	reg_val = 0x020100;
-	writel(reg_val, DENALI_CTL_25);
-}
diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
index 1502e4dbb66..3b0c57e497c 100644
--- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c
+++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
@@ -13,8 +13,40 @@
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/gpio.h>
+#include <i2c.h>
+#include <power-domain.h>
+#include <dt-bindings/power/imx8ulp-power.h>
 
 DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_NXP_FSPI) || defined(CONFIG_FSL_FSPI_NAND)
+#define FSPI_PAD_CTRL	(PAD_CTL_PUS_UP | PAD_CTL_DSE)
+static iomux_cfg_t const flexspi0_pads[] = {
+	IMX8ULP_PAD_PTC5__FLEXSPI0_A_SS0_b | MUX_PAD_CTRL(FSPI_PAD_CTRL),
+	IMX8ULP_PAD_PTC6__FLEXSPI0_A_SCLK | MUX_PAD_CTRL(FSPI_PAD_CTRL),
+	IMX8ULP_PAD_PTC10__FLEXSPI0_A_DATA0 | MUX_PAD_CTRL(FSPI_PAD_CTRL),
+	IMX8ULP_PAD_PTC9__FLEXSPI0_A_DATA1 | MUX_PAD_CTRL(FSPI_PAD_CTRL),
+	IMX8ULP_PAD_PTC8__FLEXSPI0_A_DATA2 | MUX_PAD_CTRL(FSPI_PAD_CTRL),
+	IMX8ULP_PAD_PTC7__FLEXSPI0_A_DATA3 | MUX_PAD_CTRL(FSPI_PAD_CTRL),
+	IMX8ULP_PAD_PTC4__FLEXSPI0_A_DATA4 | MUX_PAD_CTRL(FSPI_PAD_CTRL),
+	IMX8ULP_PAD_PTC3__FLEXSPI0_A_DATA5 | MUX_PAD_CTRL(FSPI_PAD_CTRL),
+	IMX8ULP_PAD_PTC2__FLEXSPI0_A_DATA6 | MUX_PAD_CTRL(FSPI_PAD_CTRL),
+	IMX8ULP_PAD_PTC1__FLEXSPI0_A_DATA7 | MUX_PAD_CTRL(FSPI_PAD_CTRL),
+};
+
+static void setup_flexspi(void)
+{
+	init_clk_fspi(0);
+}
+
+static void setup_rtd_flexspi0(void)
+{
+	imx8ulp_iomux_setup_multiple_pads(flexspi0_pads, ARRAY_SIZE(flexspi0_pads));
+
+	/* Set PCC of flexspi0, 192Mhz % 4 = 48Mhz */
+	writel(0xD6000003, 0x280300e4);
+}
+
+#endif
 
 #if IS_ENABLED(CONFIG_FEC_MXC)
 #define ENET_CLK_PAD_CTRL	(PAD_CTL_PUS_UP | PAD_CTL_DSE | PAD_CTL_IBE_ENABLE)
@@ -99,12 +131,53 @@ void mipi_dsi_panel_backlight(void)
 	writel(0x20, 0x28095030);
 }
 
+void reset_lsm6dsx(uint8_t i2c_bus, uint8_t addr)
+{
+	struct udevice *bus;
+	struct udevice *i2c_dev = NULL;
+	int ret;
+	struct i2c_msg msg;
+	u8 i2c_buf[2] = { 0x12, 0x1 };
+
+	ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus);
+	if (ret) {
+		printf("%s: Can't find bus\n", __func__);
+		return;
+	}
+
+	ret = dm_i2c_probe(bus, addr, 0, &i2c_dev);
+	if (ret) {
+		printf("%s: Can't find device id=0x%x\n",
+			__func__, addr);
+		return;
+	}
+
+	msg.addr = addr;
+	msg.flags = 0;
+	msg.len = 2;
+	msg.buf = i2c_buf;
+
+	ret = dm_i2c_xfer(i2c_dev, &msg, 1);
+	if (!ret)
+		printf("%s: Reset device 0x%x successfully.\n", __func__, addr);
+}
+
 int board_init(void)
 {
-	if (IS_ENABLED(CONFIG_FEC_MXC))
-		setup_fec();
+#if defined(CONFIG_NXP_FSPI) || defined(CONFIG_FSL_FSPI_NAND)
+	setup_flexspi();
 
-	if (IS_ENABLED(CONFIG_DM_VIDEO)) {
+	if (get_boot_mode() == SINGLE_BOOT) {
+		setup_rtd_flexspi0();
+	}
+#endif
+
+#if defined(CONFIG_FEC_MXC)
+	setup_fec();
+#endif
+
+	/* When sync with M33 is failed, use local driver to set for video */
+	if (!is_m33_handshake_necessary() && IS_ENABLED(CONFIG_DM_VIDEO)) {
 		mipi_dsi_mux_panel();
 		mipi_dsi_panel_backlight();
 	}
@@ -119,5 +192,57 @@ int board_early_init_f(void)
 
 int board_late_init(void)
 {
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+	env_set("sec_boot", "yes");
+#endif
+
+#ifdef CONFIG_SYS_I2C_IMX_I3C
+	reset_lsm6dsx(8, 0x9);
+#endif
+
 	return 0;
 }
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+int is_recovery_key_pressing(void)
+{
+	return 0; /*TODO*/
+}
+#endif /*CONFIG_ANDROID_RECOVERY*/
+#endif /*CONFIG_FSL_FASTBOOT*/
+
+
+void board_quiesce_devices(void)
+{
+	/* Disable the power domains may used in u-boot before entering kernel */
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+	struct udevice *scmi_devpd;
+	int ret, i;
+	struct power_domain pd;
+	ulong ids[] = {
+		IMX8ULP_PD_FLEXSPI2, IMX8ULP_PD_USB0, IMX8ULP_PD_USDHC0,
+		IMX8ULP_PD_USDHC1, IMX8ULP_PD_USDHC2_USB1, IMX8ULP_PD_DCNANO,
+		IMX8ULP_PD_MIPI_DSI};
+
+	ret = uclass_get_device(UCLASS_POWER_DOMAIN, 0, &scmi_devpd);
+	if (ret) {
+		printf("Cannot get scmi devpd: err=%d\n", ret);
+		return;
+	}
+
+	pd.dev = scmi_devpd;
+
+	for (i = 0; i < ARRAY_SIZE(ids); i++) {
+		pd.id = ids[i];
+		ret = power_domain_off(&pd);
+		if (ret)
+			printf("power_domain_off %lu failed: err=%d\n", ids[i], ret);
+	}
+#endif
+}
diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c b/board/freescale/imx8ulp_evk/lpddr4_timing.c
index 4546e92b01f..1878ca593a0 100644
--- a/board/freescale/imx8ulp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing.c
@@ -2,7 +2,7 @@
 /*
  * Copyright 2021 NXP
  *
- * Generated code from MX8M_DDR_tool
+ * Generated code from MX8ULP_DDR_tool
  *
  */
 
@@ -16,10 +16,10 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e06002c, 0x17702 },	/* 11 */
 	{ 0x2e060030, 0x5 },	/* 12 */
 	{ 0x2e060034, 0x61 },	/* 13 */
-	{ 0x2e060038, 0xce3f },	/* 14 */
-	{ 0x2e06003c, 0x80e70 },	/* 15 */
+	{ 0x2e060038, 0x4b00 },	/* 14 */
+	{ 0x2e06003c, 0x2edfa },	/* 15 */
 	{ 0x2e060040, 0x5 },	/* 16 */
-	{ 0x2e060044, 0x210 },	/* 17 */
+	{ 0x2e060044, 0xc0 },	/* 17 */
 	{ 0x2e060048, 0x19c7d },	/* 18 */
 	{ 0x2e06004c, 0x101cdf },	/* 19 */
 	{ 0x2e060050, 0x5 },	/* 20 */
@@ -31,56 +31,56 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e060068, 0xa },	/* 26 */
 	{ 0x2e06006c, 0x19 },	/* 27 */
 	{ 0x2e060078, 0x2020200 },	/* 30 */
-	{ 0x2e06007c, 0x160b },	/* 31 */
+	{ 0x2e06007c, 0x1604 },	/* 31 */
 	{ 0x2e060090, 0x10 },	/* 36 */
 	{ 0x2e0600a4, 0x40c040c },	/* 41 */
 	{ 0x2e0600a8, 0x8040614 },	/* 42 */
 	{ 0x2e0600ac, 0x604 },	/* 43 */
 	{ 0x2e0600b0, 0x3090003 },	/* 44 */
 	{ 0x2e0600b4, 0x40002 },	/* 45 */
-	{ 0x2e0600b8, 0xc0011 },	/* 46 */
-	{ 0x2e0600bc, 0xb0509 },	/* 47 */
+	{ 0x2e0600b8, 0x50008 },	/* 46 */
+	{ 0x2e0600bc, 0x40309 },	/* 47 */
 	{ 0x2e0600c0, 0x2106 },	/* 48 */
 	{ 0x2e0600c4, 0xa090017 },	/* 49 */
 	{ 0x2e0600c8, 0x8200016 },	/* 50 */
 	{ 0x2e0600cc, 0xa0a },	/* 51 */
 	{ 0x2e0600d0, 0x4000694 },	/* 52 */
 	{ 0x2e0600d4, 0xa0a0804 },	/* 53 */
-	{ 0x2e0600d8, 0x4002432 },	/* 54 */
+	{ 0x2e0600d8, 0x4000d29 },	/* 54 */
 	{ 0x2e0600dc, 0xa0a0804 },	/* 55 */
 	{ 0x2e0600e0, 0x4004864 },	/* 56 */
 	{ 0x2e0600e4, 0x2030404 },	/* 57 */
-	{ 0x2e0600e8, 0x5040400 },	/* 58 */
-	{ 0x2e0600ec, 0x80b0a06 },	/* 59 */
+	{ 0x2e0600e8, 0x4040400 },	/* 58 */
+	{ 0x2e0600ec, 0x80b0a04 },	/* 59 */
 	{ 0x2e0600f0, 0x7010100 },	/* 60 */
-	{ 0x2e0600f4, 0x4150b },	/* 61 */
+	{ 0x2e0600f4, 0x41507 },	/* 61 */
 	{ 0x2e0600fc, 0x1010000 },	/* 63 */
 	{ 0x2e060100, 0x1000000 },	/* 64 */
 	{ 0x2e060104, 0xe0403 },	/* 65 */
 	{ 0x2e060108, 0xb3 },	/* 66 */
-	{ 0x2e06010c, 0x4a },	/* 67 */
-	{ 0x2e060110, 0x3fd },	/* 68 */
+	{ 0x2e06010c, 0x1b },	/* 67 */
+	{ 0x2e060110, 0x16e },	/* 68 */
 	{ 0x2e060114, 0x94 },	/* 69 */
 	{ 0x2e060118, 0x803 },	/* 70 */
 	{ 0x2e06011c, 0x5 },	/* 71 */
 	{ 0x2e060120, 0x70000 },	/* 72 */
-	{ 0x2e060124, 0x25000f },	/* 73 */
-	{ 0x2e060128, 0x4a0078 },	/* 74 */
+	{ 0x2e060124, 0xe000f },	/* 73 */
+	{ 0x2e060128, 0x4a0026 },	/* 74 */
 	{ 0x2e06012c, 0x4000f9 },	/* 75 */
 	{ 0x2e060130, 0x120103 },	/* 76 */
 	{ 0x2e060134, 0x50005 },	/* 77 */
-	{ 0x2e060138, 0x8070005 },	/* 78 */
+	{ 0x2e060138, 0x7070005 },	/* 78 */
 	{ 0x2e06013c, 0x505010d },	/* 79 */
 	{ 0x2e060140, 0x101030a },	/* 80 */
 	{ 0x2e060144, 0x30a0505 },	/* 81 */
 	{ 0x2e060148, 0x5050101 },	/* 82 */
 	{ 0x2e06014c, 0x1030a },	/* 83 */
 	{ 0x2e060150, 0xe000e },	/* 84 */
-	{ 0x2e060154, 0x4c004c },	/* 85 */
+	{ 0x2e060154, 0x1c001c },	/* 85 */
 	{ 0x2e060158, 0x980098 },	/* 86 */
 	{ 0x2e06015c, 0x3050505 },	/* 87 */
 	{ 0x2e060160, 0x3010403 },	/* 88 */
-	{ 0x2e060164, 0x4050505 },	/* 89 */
+	{ 0x2e060164, 0x3050505 },	/* 89 */
 	{ 0x2e060168, 0x3010403 },	/* 90 */
 	{ 0x2e06016c, 0x8050505 },	/* 91 */
 	{ 0x2e060170, 0x3010403 },	/* 92 */
@@ -101,12 +101,12 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e0601b4, 0x2cc0 },	/* 109 */
 	{ 0x2e0601b8, 0x2cc0 },	/* 110 */
 	{ 0x2e0601c0, 0x4e5 },	/* 112 */
-	{ 0x2e0601c4, 0xff40 },	/* 113 */
-	{ 0x2e0601c8, 0xff40 },	/* 114 */
-	{ 0x2e0601cc, 0xff40 },	/* 115 */
-	{ 0x2e0601d0, 0xff40 },	/* 116 */
-	{ 0x2e0601d4, 0xff40 },	/* 117 */
-	{ 0x2e0601dc, 0x1beb },	/* 119 */
+	{ 0x2e0601c4, 0x5b80 },	/* 113 */
+	{ 0x2e0601c8, 0x5b80 },	/* 114 */
+	{ 0x2e0601cc, 0x5b80 },	/* 115 */
+	{ 0x2e0601d0, 0x5b80 },	/* 116 */
+	{ 0x2e0601d4, 0x5b80 },	/* 117 */
+	{ 0x2e0601dc, 0xa02 },	/* 119 */
 	{ 0x2e0601e0, 0x200c0 },	/* 120 */
 	{ 0x2e0601e4, 0x200c0 },	/* 121 */
 	{ 0x2e0601e8, 0x200c0 },	/* 122 */
@@ -138,9 +138,9 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e0602a8, 0xd0005 },	/* 170 */
 	{ 0x2e0602ac, 0x404 },	/* 171 */
 	{ 0x2e0602b0, 0xd },	/* 172 */
-	{ 0x2e0602b4, 0x1b0035 },	/* 173 */
-	{ 0x2e0602b8, 0x4040042 },	/* 174 */
-	{ 0x2e0602bc, 0x42 },	/* 175 */
+	{ 0x2e0602b4, 0xa0014 },	/* 173 */
+	{ 0x2e0602b8, 0x4040018 },	/* 174 */
+	{ 0x2e0602bc, 0x18 },	/* 175 */
 	{ 0x2e0602c0, 0x35006a },	/* 176 */
 	{ 0x2e0602c4, 0x4040084 },	/* 177 */
 	{ 0x2e0602c8, 0x84 },	/* 178 */
@@ -168,13 +168,13 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e060390, 0x30000 },	/* 228 */
 	{ 0x2e060394, 0x1000200 },	/* 229 */
 	{ 0x2e060398, 0x310040 },	/* 230 */
-	{ 0x2e06039c, 0x20002 },	/* 231 */
+	{ 0x2e06039c, 0x20008 },	/* 231 */
 	{ 0x2e0603a0, 0x400100 },	/* 232 */
-	{ 0x2e0603a4, 0x80108 },	/* 233 */
+	{ 0x2e0603a4, 0x80060 },	/* 233 */
 	{ 0x2e0603a8, 0x1000200 },	/* 234 */
 	{ 0x2e0603ac, 0x2100040 },	/* 235 */
 	{ 0x2e0603b0, 0x10 },	/* 236 */
-	{ 0x2e0603b4, 0xe0003 },	/* 237 */
+	{ 0x2e0603b4, 0x50003 },	/* 237 */
 	{ 0x2e0603b8, 0x100001b },	/* 238 */
 	{ 0x2e0603d8, 0xffff0b00 },	/* 246 */
 	{ 0x2e0603dc, 0x1010001 },	/* 247 */
@@ -399,7 +399,7 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e0608ec, 0x1320001 },	/* 571 */
 	{ 0x2e0608f0, 0x13200 },	/* 572 */
 	{ 0x2e0608f4, 0x132 },	/* 573 */
-	{ 0x2e0608fc, 0x1d1b0000 },	/* 575 */
+	{ 0x2e0608fc, 0x1b1b0000 },	/* 575 */
 	{ 0x2e060900, 0x21 },	/* 576 */
 	{ 0x2e060904, 0xa },	/* 577 */
 	{ 0x2e060908, 0x166 },	/* 578 */
@@ -410,13 +410,13 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e06091c, 0x432 },	/* 583 */
 	{ 0x2e060920, 0xdfc },	/* 584 */
 	{ 0x2e060924, 0x204 },	/* 585 */
-	{ 0x2e060928, 0x7fa },	/* 586 */
+	{ 0x2e060928, 0x2dc },	/* 586 */
 	{ 0x2e06092c, 0x200 },	/* 587 */
 	{ 0x2e060930, 0x200 },	/* 588 */
 	{ 0x2e060934, 0x200 },	/* 589 */
 	{ 0x2e060938, 0x200 },	/* 590 */
-	{ 0x2e06093c, 0x17ee },	/* 591 */
-	{ 0x2e060940, 0x4fc4 },	/* 592 */
+	{ 0x2e06093c, 0x894 },	/* 591 */
+	{ 0x2e060940, 0x1c98 },	/* 592 */
 	{ 0x2e060944, 0x204 },	/* 593 */
 	{ 0x2e060948, 0x1006 },	/* 594 */
 	{ 0x2e06094c, 0x200 },	/* 595 */
@@ -438,7 +438,7 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e06098c, 0x2010000 },	/* 611 */
 	{ 0x2e060990, 0x6000200 },	/* 612 */
 	{ 0x2e060994, 0x3000a06 },	/* 613 */
-	{ 0x2e060998, 0x2000c06 },	/* 614 */
+	{ 0x2e060998, 0x2000c03 },	/* 614 */
 };
 
 /** PI settings **/
@@ -518,22 +518,22 @@ struct dram_cfg_param ddr_pi_cfg[] = {
 	{ 0x2e062260, 0x10001 },	/* 152 */
 	{ 0x2e062274, 0x401 },	/* 157 */
 	{ 0x2e06227c, 0x10000 },	/* 159 */
-	{ 0x2e062284, 0x6010000 },	/* 161 */
+	{ 0x2e062284, 0x2010000 },	/* 161 */
 	{ 0x2e062288, 0xb },	/* 162 */
 	{ 0x2e06228c, 0x34 },	/* 163 */
-	{ 0x2e062290, 0x36 },	/* 164 */
+	{ 0x2e062290, 0x34 },	/* 164 */
 	{ 0x2e062294, 0x2003c },	/* 165 */
 	{ 0x2e062298, 0x2000200 },	/* 166 */
 	{ 0x2e06229c, 0xc040c04 },	/* 167 */
 	{ 0x2e0622a0, 0xe1406 },	/* 168 */
 	{ 0x2e0622a4, 0xb3 },	/* 169 */
-	{ 0x2e0622a8, 0x4a },	/* 170 */
-	{ 0x2e0622ac, 0x3fd },	/* 171 */
+	{ 0x2e0622a8, 0x1b },	/* 170 */
+	{ 0x2e0622ac, 0x16e },	/* 171 */
 	{ 0x2e0622b0, 0x94 },	/* 172 */
 	{ 0x2e0622b4, 0x4000803 },	/* 173 */
 	{ 0x2e0622b8, 0x1010404 },	/* 174 */
 	{ 0x2e0622bc, 0x1501 },	/* 175 */
-	{ 0x2e0622c0, 0x1a0018 },	/* 176 */
+	{ 0x2e0622c0, 0x1a0016 },	/* 176 */
 	{ 0x2e0622c4, 0x1000100 },	/* 177 */
 	{ 0x2e0622c8, 0x100 },	/* 178 */
 	{ 0x2e0622d0, 0x5040303 },	/* 180 */
@@ -542,15 +542,15 @@ struct dram_cfg_param ddr_pi_cfg[] = {
 	{ 0x2e0622e8, 0x2060404 },	/* 186 */
 	{ 0x2e0622ec, 0x2020402 },	/* 187 */
 	{ 0x2e0622f0, 0x3102 },	/* 188 */
-	{ 0x2e0622f4, 0x340009 },	/* 189 */
-	{ 0x2e0622f8, 0x36000c },	/* 190 */
+	{ 0x2e0622f4, 0x320009 },	/* 189 */
+	{ 0x2e0622f8, 0x36000a },	/* 190 */
 	{ 0x2e0622fc, 0x101000e },	/* 191 */
 	{ 0x2e062300, 0xd0101 },	/* 192 */
-	{ 0x2e062304, 0x1004201 },	/* 193 */
+	{ 0x2e062304, 0x1001801 },	/* 193 */
 	{ 0x2e062308, 0x1000084 },	/* 194 */
 	{ 0x2e06230c, 0xe000e },	/* 195 */
-	{ 0x2e062310, 0x430100 },	/* 196 */
-	{ 0x2e062314, 0x1000043 },	/* 197 */
+	{ 0x2e062310, 0x190100 },	/* 196 */
+	{ 0x2e062314, 0x1000019 },	/* 197 */
 	{ 0x2e062318, 0x850085 },	/* 198 */
 	{ 0x2e06231c, 0x220f220f },	/* 199 */
 	{ 0x2e062320, 0x101220f },	/* 200 */
@@ -561,8 +561,8 @@ struct dram_cfg_param ddr_pi_cfg[] = {
 	{ 0x2e062334, 0xc01000 },	/* 205 */
 	{ 0x2e062338, 0xc01000 },	/* 206 */
 	{ 0x2e06233c, 0x21000 },	/* 207 */
-	{ 0x2e062340, 0x11000d },	/* 208 */
-	{ 0x2e062344, 0x140042 },	/* 209 */
+	{ 0x2e062340, 0x2000d },	/* 208 */
+	{ 0x2e062344, 0x140018 },	/* 209 */
 	{ 0x2e062348, 0x190084 },	/* 210 */
 	{ 0x2e06234c, 0x220f0056 },	/* 211 */
 	{ 0x2e062350, 0x101 },	/* 212 */
@@ -575,40 +575,40 @@ struct dram_cfg_param ddr_pi_cfg[] = {
 	{ 0x2e06236c, 0x5eb },	/* 219 */
 	{ 0x2e062370, 0x20010003 },	/* 220 */
 	{ 0x2e062374, 0x80a0a03 },	/* 221 */
-	{ 0x2e062378, 0x6090506 },	/* 222 */
-	{ 0x2e06237c, 0x2093 },	/* 223 */
-	{ 0x2e062380, 0x2001000c },	/* 224 */
-	{ 0x2e062384, 0x80a0a04 },	/* 225 */
+	{ 0x2e062378, 0x4090403 },	/* 222 */
+	{ 0x2e06237c, 0xbd8 },	/* 223 */
+	{ 0x2e062380, 0x20010005 },	/* 224 */
+	{ 0x2e062384, 0x80a0a03 },	/* 225 */
 	{ 0x2e062388, 0xb090a0c },	/* 226 */
 	{ 0x2e06238c, 0x4126 },	/* 227 */
 	{ 0x2e062390, 0x20020017 },	/* 228 */
 	{ 0x2e062394, 0xa0a08 },	/* 229 */
 	{ 0x2e062398, 0x166 },	/* 230 */
 	{ 0x2e06239c, 0xdfc },	/* 231 */
-	{ 0x2e0623a0, 0x7fa },	/* 232 */
-	{ 0x2e0623a4, 0x4fc4 },	/* 233 */
+	{ 0x2e0623a0, 0x2dc },	/* 232 */
+	{ 0x2e0623a4, 0x1c98 },	/* 233 */
 	{ 0x2e0623a8, 0x1006 },	/* 234 */
 	{ 0x2e0623ac, 0xa03c },	/* 235 */
-	{ 0x2e0623b0, 0x4c000e },	/* 236 */
+	{ 0x2e0623b0, 0x1c000e },	/* 236 */
 	{ 0x2e0623b4, 0x3030098 },	/* 237 */
 	{ 0x2e0623b8, 0x258103 },	/* 238 */
 	{ 0x2e0623bc, 0x17702 },	/* 239 */
 	{ 0x2e0623c0, 0x5 },	/* 240 */
 	{ 0x2e0623c4, 0x61 },	/* 241 */
 	{ 0x2e0623c8, 0xe },	/* 242 */
-	{ 0x2e0623cc, 0xce3f },	/* 243 */
-	{ 0x2e0623d0, 0x80e70 },	/* 244 */
+	{ 0x2e0623cc, 0x4b00 },	/* 243 */
+	{ 0x2e0623d0, 0x17702 },	/* 244 */
 	{ 0x2e0623d4, 0x5 },	/* 245 */
-	{ 0x2e0623d8, 0x210 },	/* 246 */
-	{ 0x2e0623dc, 0x4c },	/* 247 */
+	{ 0x2e0623d8, 0xc0 },	/* 246 */
+	{ 0x2e0623dc, 0x1c },	/* 247 */
 	{ 0x2e0623e0, 0x19c7d },	/* 248 */
-	{ 0x2e0623e4, 0x101cdf },	/* 249 */
+	{ 0x2e0623e4, 0x17702 },	/* 249 */
 	{ 0x2e0623e8, 0x5 },	/* 250 */
 	{ 0x2e0623ec, 0x420 },	/* 251 */
 	{ 0x2e0623f0, 0x1000098 },	/* 252 */
 	{ 0x2e0623f4, 0x310040 },	/* 253 */
-	{ 0x2e0623f8, 0x10002 },	/* 254 */
-	{ 0x2e0623fc, 0x1080040 },	/* 255 */
+	{ 0x2e0623f8, 0x10008 },	/* 254 */
+	{ 0x2e0623fc, 0x600040 },	/* 255 */
 	{ 0x2e062400, 0x10008 },	/* 256 */
 	{ 0x2e062404, 0x2100040 },	/* 257 */
 	{ 0x2e062408, 0x310 },	/* 258 */
@@ -701,23 +701,23 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e064154, 0x2000000 },	/* 85 */
 	{ 0x2e064158, 0x51515042 },	/* 86 */
 	{ 0x2e06415c, 0x31c06000 },	/* 87 */
-	{ 0x2e064160, 0x9bf000a },	/* 88 */
+	{ 0x2e064160, 0x6bf000a },	/* 88 */
 	{ 0x2e064164, 0xc0c000 },	/* 89 */
 	{ 0x2e064168, 0x1000000 },	/* 90 */
 	{ 0x2e06416c, 0x10001000 },	/* 91 */
 	{ 0x2e064170, 0xc043242 },	/* 92 */
-	{ 0x2e064174, 0xf0c1201 },	/* 93 */
+	{ 0x2e064174, 0xf0c0e01 },	/* 93 */
 	{ 0x2e064178, 0x1000140 },	/* 94 */
 	{ 0x2e06417c, 0xc000120 },	/* 95 */
-	{ 0x2e064180, 0x143 },	/* 96 */
+	{ 0x2e064180, 0x118 },	/* 96 */
 	{ 0x2e064184, 0x1000203 },	/* 97 */
 	{ 0x2e064188, 0x56417032 },	/* 98 */
 	{ 0x2e06418c, 0x8 },	/* 99 */
-	{ 0x2e064190, 0x2c302c3 },	/* 100 */
-	{ 0x2e064194, 0x2c302c3 },	/* 101 */
-	{ 0x2e064198, 0x2c302c3 },	/* 102 */
-	{ 0x2e06419c, 0x2c302c3 },	/* 103 */
-	{ 0x2e0641a0, 0x2c3 },	/* 104 */
+	{ 0x2e064190, 0x2980298 },	/* 100 */
+	{ 0x2e064194, 0x2980298 },	/* 101 */
+	{ 0x2e064198, 0x2980298 },	/* 102 */
+	{ 0x2e06419c, 0x2980298 },	/* 103 */
+	{ 0x2e0641a0, 0x298 },	/* 104 */
 	{ 0x2e0641a4, 0x8000 },	/* 105 */
 	{ 0x2e0641a8, 0x800080 },	/* 106 */
 	{ 0x2e0641ac, 0x800080 },	/* 107 */
@@ -727,7 +727,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e0641bc, 0x800080 },	/* 111 */
 	{ 0x2e0641c0, 0x800080 },	/* 112 */
 	{ 0x2e0641c4, 0x800080 },	/* 113 */
-	{ 0x2e0641c8, 0x6b0080 },	/* 114 */
+	{ 0x2e0641c8, 0x1940080 },	/* 114 */
 	{ 0x2e0641cc, 0x1a00001 },	/* 115 */
 	{ 0x2e0641d4, 0x10000 },	/* 117 */
 	{ 0x2e0641d8, 0x80200 },	/* 118 */
@@ -777,23 +777,23 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e064554, 0x2000000 },	/* 341 */
 	{ 0x2e064558, 0x51515042 },	/* 342 */
 	{ 0x2e06455c, 0x31c06000 },	/* 343 */
-	{ 0x2e064560, 0x9bf000a },	/* 344 */
+	{ 0x2e064560, 0x6bf000a },	/* 344 */
 	{ 0x2e064564, 0xc0c000 },	/* 345 */
 	{ 0x2e064568, 0x1000000 },	/* 346 */
 	{ 0x2e06456c, 0x10001000 },	/* 347 */
 	{ 0x2e064570, 0xc043242 },	/* 348 */
-	{ 0x2e064574, 0xf0c1201 },	/* 349 */
+	{ 0x2e064574, 0xf0c0e01 },	/* 349 */
 	{ 0x2e064578, 0x1000140 },	/* 350 */
 	{ 0x2e06457c, 0xc000120 },	/* 351 */
-	{ 0x2e064580, 0x143 },	/* 352 */
+	{ 0x2e064580, 0x118 },	/* 352 */
 	{ 0x2e064584, 0x1000203 },	/* 353 */
 	{ 0x2e064588, 0x30217465 },	/* 354 */
 	{ 0x2e06458c, 0x8 },	/* 355 */
-	{ 0x2e064590, 0x2c302c3 },	/* 356 */
-	{ 0x2e064594, 0x2c302c3 },	/* 357 */
-	{ 0x2e064598, 0x2c302c3 },	/* 358 */
-	{ 0x2e06459c, 0x2c302c3 },	/* 359 */
-	{ 0x2e0645a0, 0x2c3 },	/* 360 */
+	{ 0x2e064590, 0x2980298 },	/* 356 */
+	{ 0x2e064594, 0x2980298 },	/* 357 */
+	{ 0x2e064598, 0x2980298 },	/* 358 */
+	{ 0x2e06459c, 0x2980298 },	/* 359 */
+	{ 0x2e0645a0, 0x298 },	/* 360 */
 	{ 0x2e0645a4, 0x8000 },	/* 361 */
 	{ 0x2e0645a8, 0x800080 },	/* 362 */
 	{ 0x2e0645ac, 0x800080 },	/* 363 */
@@ -803,7 +803,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e0645bc, 0x800080 },	/* 367 */
 	{ 0x2e0645c0, 0x800080 },	/* 368 */
 	{ 0x2e0645c4, 0x800080 },	/* 369 */
-	{ 0x2e0645c8, 0x6b0080 },	/* 370 */
+	{ 0x2e0645c8, 0x1940080 },	/* 370 */
 	{ 0x2e0645cc, 0x1a00001 },	/* 371 */
 	{ 0x2e0645d4, 0x10000 },	/* 373 */
 	{ 0x2e0645d8, 0x80200 },	/* 374 */
@@ -854,23 +854,23 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e064954, 0x2000000 },	/* 597 */
 	{ 0x2e064958, 0x51515042 },	/* 598 */
 	{ 0x2e06495c, 0x31c06000 },	/* 599 */
-	{ 0x2e064960, 0x9bf000a },	/* 600 */
+	{ 0x2e064960, 0x6bf000a },	/* 600 */
 	{ 0x2e064964, 0xc0c000 },	/* 601 */
 	{ 0x2e064968, 0x1000000 },	/* 602 */
 	{ 0x2e06496c, 0x10001000 },	/* 603 */
 	{ 0x2e064970, 0xc043242 },	/* 604 */
-	{ 0x2e064974, 0xf0c1201 },	/* 605 */
+	{ 0x2e064974, 0xf0c0e01 },	/* 605 */
 	{ 0x2e064978, 0x1000140 },	/* 606 */
 	{ 0x2e06497c, 0xc000120 },	/* 607 */
-	{ 0x2e064980, 0x143 },	/* 608 */
+	{ 0x2e064980, 0x118 },	/* 608 */
 	{ 0x2e064984, 0x1000203 },	/* 609 */
 	{ 0x2e064988, 0x75436012 },	/* 610 */
 	{ 0x2e06498c, 0x8 },	/* 611 */
-	{ 0x2e064990, 0x2c302c3 },	/* 612 */
-	{ 0x2e064994, 0x2c302c3 },	/* 613 */
-	{ 0x2e064998, 0x2c302c3 },	/* 614 */
-	{ 0x2e06499c, 0x2c302c3 },	/* 615 */
-	{ 0x2e0649a0, 0x2c3 },	/* 616 */
+	{ 0x2e064990, 0x2980298 },	/* 612 */
+	{ 0x2e064994, 0x2980298 },	/* 613 */
+	{ 0x2e064998, 0x2980298 },	/* 614 */
+	{ 0x2e06499c, 0x2980298 },	/* 615 */
+	{ 0x2e0649a0, 0x298 },	/* 616 */
 	{ 0x2e0649a4, 0x8000 },	/* 617 */
 	{ 0x2e0649a8, 0x800080 },	/* 618 */
 	{ 0x2e0649ac, 0x800080 },	/* 619 */
@@ -880,7 +880,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e0649bc, 0x800080 },	/* 623 */
 	{ 0x2e0649c0, 0x800080 },	/* 624 */
 	{ 0x2e0649c4, 0x800080 },	/* 625 */
-	{ 0x2e0649c8, 0x6b0080 },	/* 626 */
+	{ 0x2e0649c8, 0x1940080 },	/* 626 */
 	{ 0x2e0649cc, 0x1a00001 },	/* 627 */
 	{ 0x2e0649d4, 0x10000 },	/* 629 */
 	{ 0x2e0649d8, 0x80200 },	/* 630 */
@@ -930,23 +930,23 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e064d54, 0x2000000 },	/* 853 */
 	{ 0x2e064d58, 0x51515042 },	/* 854 */
 	{ 0x2e064d5c, 0x31c06000 },	/* 855 */
-	{ 0x2e064d60, 0x9bf000a },	/* 856 */
+	{ 0x2e064d60, 0x6bf000a },	/* 856 */
 	{ 0x2e064d64, 0xc0c000 },	/* 857 */
 	{ 0x2e064d68, 0x1000000 },	/* 858 */
 	{ 0x2e064d6c, 0x10001000 },	/* 859 */
 	{ 0x2e064d70, 0xc043242 },	/* 860 */
-	{ 0x2e064d74, 0xf0c1201 },	/* 861 */
+	{ 0x2e064d74, 0xf0c0e01 },	/* 861 */
 	{ 0x2e064d78, 0x1000140 },	/* 862 */
 	{ 0x2e064d7c, 0xc000120 },	/* 863 */
-	{ 0x2e064d80, 0x143 },	/* 864 */
+	{ 0x2e064d80, 0x118 },	/* 864 */
 	{ 0x2e064d84, 0x1000203 },	/* 865 */
 	{ 0x2e064d88, 0x32017465 },	/* 866 */
 	{ 0x2e064d8c, 0x8 },	/* 867 */
-	{ 0x2e064d90, 0x2c302c3 },	/* 868 */
-	{ 0x2e064d94, 0x2c302c3 },	/* 869 */
-	{ 0x2e064d98, 0x2c302c3 },	/* 870 */
-	{ 0x2e064d9c, 0x2c302c3 },	/* 871 */
-	{ 0x2e064da0, 0x2c3 },	/* 872 */
+	{ 0x2e064d90, 0x2980298 },	/* 868 */
+	{ 0x2e064d94, 0x2980298 },	/* 869 */
+	{ 0x2e064d98, 0x2980298 },	/* 870 */
+	{ 0x2e064d9c, 0x2980298 },	/* 871 */
+	{ 0x2e064da0, 0x298 },	/* 872 */
 	{ 0x2e064da4, 0x8000 },	/* 873 */
 	{ 0x2e064da8, 0x800080 },	/* 874 */
 	{ 0x2e064dac, 0x800080 },	/* 875 */
@@ -956,7 +956,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e064dbc, 0x800080 },	/* 879 */
 	{ 0x2e064dc0, 0x800080 },	/* 880 */
 	{ 0x2e064dc4, 0x800080 },	/* 881 */
-	{ 0x2e064dc8, 0x6b0080 },	/* 882 */
+	{ 0x2e064dc8, 0x1940080 },	/* 882 */
 	{ 0x2e064dcc, 0x1a00001 },	/* 883 */
 	{ 0x2e064dd4, 0x10000 },	/* 885 */
 	{ 0x2e064dd8, 0x80200 },	/* 886 */
@@ -1032,9 +1032,9 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e065860, 0x8040201 },	/* 1560 */
 	{ 0x2e065864, 0x2010201 },	/* 1561 */
 	{ 0x2e065868, 0xf0f0f },	/* 1562 */
-	{ 0x2e06586c, 0x241b42 },	/* 1563 */
+	{ 0x2e06586c, 0x241342 },	/* 1563 */
 	{ 0x2e065874, 0x1020000 },	/* 1565 */
-	{ 0x2e065878, 0x701 },	/* 1566 */
+	{ 0x2e065878, 0x10701 },	/* 1566 */
 	{ 0x2e06587c, 0x54 },	/* 1567 */
 	{ 0x2e065880, 0x4102000 },	/* 1568 */
 	{ 0x2e065884, 0x24410 },	/* 1569 */
@@ -1047,7 +1047,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e0658a0, 0x4410 },	/* 1576 */
 	{ 0x2e0658a4, 0x4410 },	/* 1577 */
 	{ 0x2e0658b0, 0x60000 },	/* 1580 */
-	{ 0x2e0658b8, 0x96 },	/* 1582 */
+	{ 0x2e0658b8, 0x64 },	/* 1582 */
 	{ 0x2e0658bc, 0x10000 },	/* 1583 */
 	{ 0x2e0658c0, 0x8 },	/* 1584 */
 	{ 0x2e0658d8, 0x3000000 },	/* 1590 */
@@ -1064,8 +1064,8 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e065934, 0x40700 },	/* 1613 */
 	{ 0x2e06594c, 0x2 },	/* 1619 */
 	{ 0x2e065958, 0xf3c3 },	/* 1622 */
-	{ 0x2e065964, 0x11542 },	/* 1625 */
-	{ 0x2e065968, 0x30209bf },	/* 1626 */
+	{ 0x2e065964, 0x11742 },	/* 1625 */
+	{ 0x2e065968, 0x3020600 },	/* 1626 */
 	{ 0x2e06596c, 0x30000 },	/* 1627 */
 	{ 0x2e065970, 0x3000300 },	/* 1628 */
 	{ 0x2e065974, 0x3000300 },	/* 1629 */
@@ -1074,20 +1074,20 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e065980, 0x300 },	/* 1632 */
 	{ 0x2e065984, 0x300 },	/* 1633 */
 	{ 0x2e065988, 0x300 },	/* 1634 */
-	{ 0x2e06598c, 0x4bf77 },	/* 1635 */
-	{ 0x2e065990, 0x77 },	/* 1636 */
-	{ 0x2e065994, 0x27f },	/* 1637 */
-	{ 0x2e06599c, 0x27f },	/* 1639 */
-	{ 0x2e0659a4, 0x27f00 },	/* 1641 */
+	{ 0x2e06598c, 0x337cc },	/* 1635 */
+	{ 0x2e065990, 0x8 },	/* 1636 */
+	{ 0x2e065994, 0x1b7 },	/* 1637 */
+	{ 0x2e06599c, 0x1b7 },	/* 1639 */
+	{ 0x2e0659a4, 0x1b700 },	/* 1641 */
 	{ 0x2e0659a8, 0x1980000 },	/* 1642 */
-	{ 0x2e0659ac, 0x27fcc },	/* 1643 */
-	{ 0x2e0659b4, 0x27f00 },	/* 1645 */
+	{ 0x2e0659ac, 0x1b7cc },	/* 1643 */
+	{ 0x2e0659b4, 0x1b700 },	/* 1645 */
 	{ 0x2e0659b8, 0x1980000 },	/* 1646 */
-	{ 0x2e0659bc, 0x27f00 },	/* 1647 */
+	{ 0x2e0659bc, 0x1b700 },	/* 1647 */
 	{ 0x2e0659c0, 0x1980000 },	/* 1648 */
-	{ 0x2e0659c4, 0x27f00 },	/* 1649 */
+	{ 0x2e0659c4, 0x1b700 },	/* 1649 */
 	{ 0x2e0659c8, 0x1980000 },	/* 1650 */
-	{ 0x2e0659cc, 0x27f00 },	/* 1651 */
+	{ 0x2e0659cc, 0x1b700 },	/* 1651 */
 	{ 0x2e0659d0, 0x1980000 },	/* 1652 */
 	{ 0x2e0659d4, 0x20040003 },	/* 1653 */
 };
@@ -1098,7 +1098,7 @@ struct dram_cfg_param ddr_phy_f2_cfg[] = {
 	{ 0x2e064170, 0xc043e42 },	/* 92 */
 	{ 0x2e064174, 0xf0c1701 },	/* 93 */
 	{ 0x2e064180, 0x187 },	/* 96 */
-	{ 0x2e064184, 0x3010203 },	/* 97 */
+	{ 0x2e064184, 0x3200203 },	/* 97 */
 	{ 0x2e064190, 0x3070307 },	/* 100 */
 	{ 0x2e064194, 0x3070307 },	/* 101 */
 	{ 0x2e064198, 0x3070307 },	/* 102 */
@@ -1109,7 +1109,7 @@ struct dram_cfg_param ddr_phy_f2_cfg[] = {
 	{ 0x2e064570, 0xc043e42 },	/* 348 */
 	{ 0x2e064574, 0xf0c1701 },	/* 349 */
 	{ 0x2e064580, 0x187 },	/* 352 */
-	{ 0x2e064584, 0x3010203 },	/* 353 */
+	{ 0x2e064584, 0x3200203 },	/* 353 */
 	{ 0x2e064590, 0x3070307 },	/* 356 */
 	{ 0x2e064594, 0x3070307 },	/* 357 */
 	{ 0x2e064598, 0x3070307 },	/* 358 */
@@ -1120,7 +1120,7 @@ struct dram_cfg_param ddr_phy_f2_cfg[] = {
 	{ 0x2e064970, 0xc043e42 },	/* 604 */
 	{ 0x2e064974, 0xf0c1701 },	/* 605 */
 	{ 0x2e064980, 0x187 },	/* 608 */
-	{ 0x2e064984, 0x3010203 },	/* 609 */
+	{ 0x2e064984, 0x3200203 },	/* 609 */
 	{ 0x2e064990, 0x3070307 },	/* 612 */
 	{ 0x2e064994, 0x3070307 },	/* 613 */
 	{ 0x2e064998, 0x3070307 },	/* 614 */
@@ -1131,7 +1131,7 @@ struct dram_cfg_param ddr_phy_f2_cfg[] = {
 	{ 0x2e064d70, 0xc043e42 },	/* 860 */
 	{ 0x2e064d74, 0xf0c1701 },	/* 861 */
 	{ 0x2e064d80, 0x187 },	/* 864 */
-	{ 0x2e064d84, 0x3010203 },	/* 865 */
+	{ 0x2e064d84, 0x3200203 },	/* 865 */
 	{ 0x2e064d90, 0x3070307 },	/* 868 */
 	{ 0x2e064d94, 0x3070307 },	/* 869 */
 	{ 0x2e064d98, 0x3070307 },	/* 870 */
@@ -1154,5 +1154,5 @@ struct dram_timing_info2 dram_timing = {
 	.phy_f1_cfg_num = ARRAY_SIZE(ddr_phy_f1_cfg),
 	.phy_f2_cfg = ddr_phy_f2_cfg,
 	.phy_f2_cfg_num = ARRAY_SIZE(ddr_phy_f2_cfg),
-	.fsp_table = { 96, 528, 1056 },
+	.fsp_table = { 96, 192, 1056 },
 };
diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
new file mode 100644
index 00000000000..4240eaa44b4
--- /dev/null
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
@@ -0,0 +1,1109 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2021 NXP
+ *
+ * Generated code from MX8ULP_DDR_tool
+ *
+ */
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+/** CTL settings **/
+struct dram_cfg_param ddr_ctl_cfg[] = {
+	{ 0x2e060000, 0xb00 },	/* 0 */
+	{ 0x2e060028, 0x258100 },	/* 10 */
+	{ 0x2e06002c, 0x17702 },	/* 11 */
+	{ 0x2e060030, 0x5 },	/* 12 */
+	{ 0x2e060034, 0x61 },	/* 13 */
+	{ 0x2e060038, 0xce3f },	/* 14 */
+	{ 0x2e06003c, 0x80e70 },	/* 15 */
+	{ 0x2e060040, 0x5 },	/* 16 */
+	{ 0x2e060044, 0x210 },	/* 17 */
+	{ 0x2e060048, 0x19c7d },	/* 18 */
+	{ 0x2e06004c, 0x101cdf },	/* 19 */
+	{ 0x2e060050, 0x5 },	/* 20 */
+	{ 0x2e060054, 0x420 },	/* 21 */
+	{ 0x2e060058, 0x1010000 },	/* 22 */
+	{ 0x2e06005c, 0x1011001 },	/* 23 */
+	{ 0x2e060060, 0x10000 },	/* 24 */
+	{ 0x2e060064, 0x102 },	/* 25 */
+	{ 0x2e060068, 0xa },	/* 26 */
+	{ 0x2e06006c, 0x19 },	/* 27 */
+	{ 0x2e060078, 0x2020200 },	/* 30 */
+	{ 0x2e06007c, 0x160b },	/* 31 */
+	{ 0x2e060090, 0x10 },	/* 36 */
+	{ 0x2e0600a4, 0x40c040c },	/* 41 */
+	{ 0x2e0600a8, 0x8040614 },	/* 42 */
+	{ 0x2e0600ac, 0x604 },	/* 43 */
+	{ 0x2e0600b0, 0x3090003 },	/* 44 */
+	{ 0x2e0600b4, 0x40002 },	/* 45 */
+	{ 0x2e0600b8, 0xc0011 },	/* 46 */
+	{ 0x2e0600bc, 0xb0509 },	/* 47 */
+	{ 0x2e0600c0, 0x2106 },	/* 48 */
+	{ 0x2e0600c4, 0xa090017 },	/* 49 */
+	{ 0x2e0600c8, 0x8200016 },	/* 50 */
+	{ 0x2e0600cc, 0xa0a },	/* 51 */
+	{ 0x2e0600d0, 0x4000694 },	/* 52 */
+	{ 0x2e0600d4, 0xa0a0804 },	/* 53 */
+	{ 0x2e0600d8, 0x4002432 },	/* 54 */
+	{ 0x2e0600dc, 0xa0a0804 },	/* 55 */
+	{ 0x2e0600e0, 0x4004864 },	/* 56 */
+	{ 0x2e0600e4, 0x2030404 },	/* 57 */
+	{ 0x2e0600e8, 0x5040400 },	/* 58 */
+	{ 0x2e0600ec, 0x80b0a06 },	/* 59 */
+	{ 0x2e0600f0, 0x7010100 },	/* 60 */
+	{ 0x2e0600f4, 0x4150b },	/* 61 */
+	{ 0x2e0600fc, 0x1010000 },	/* 63 */
+	{ 0x2e060100, 0x1000000 },	/* 64 */
+	{ 0x2e060104, 0xe0403 },	/* 65 */
+	{ 0x2e060108, 0xb3 },	/* 66 */
+	{ 0x2e06010c, 0x4a },	/* 67 */
+	{ 0x2e060110, 0x3fd },	/* 68 */
+	{ 0x2e060114, 0x94 },	/* 69 */
+	{ 0x2e060118, 0x803 },	/* 70 */
+	{ 0x2e06011c, 0x5 },	/* 71 */
+	{ 0x2e060120, 0x70000 },	/* 72 */
+	{ 0x2e060124, 0x25000f },	/* 73 */
+	{ 0x2e060128, 0x4a0078 },	/* 74 */
+	{ 0x2e06012c, 0x4000f9 },	/* 75 */
+	{ 0x2e060130, 0x120103 },	/* 76 */
+	{ 0x2e060134, 0x50005 },	/* 77 */
+	{ 0x2e060138, 0x8070005 },	/* 78 */
+	{ 0x2e06013c, 0x505010d },	/* 79 */
+	{ 0x2e060140, 0x101030a },	/* 80 */
+	{ 0x2e060144, 0x30a0505 },	/* 81 */
+	{ 0x2e060148, 0x5050101 },	/* 82 */
+	{ 0x2e06014c, 0x1030a },	/* 83 */
+	{ 0x2e060150, 0xe000e },	/* 84 */
+	{ 0x2e060154, 0x4c004c },	/* 85 */
+	{ 0x2e060158, 0x980098 },	/* 86 */
+	{ 0x2e06015c, 0x3050505 },	/* 87 */
+	{ 0x2e060160, 0x3010403 },	/* 88 */
+	{ 0x2e060164, 0x4050505 },	/* 89 */
+	{ 0x2e060168, 0x3010403 },	/* 90 */
+	{ 0x2e06016c, 0x8050505 },	/* 91 */
+	{ 0x2e060170, 0x3010403 },	/* 92 */
+	{ 0x2e060174, 0x3010000 },	/* 93 */
+	{ 0x2e060178, 0x10000 },	/* 94 */
+	{ 0x2e060180, 0x1000000 },	/* 96 */
+	{ 0x2e060184, 0x80104002 },	/* 97 */
+	{ 0x2e060188, 0x40003 },	/* 98 */
+	{ 0x2e06018c, 0x40005 },	/* 99 */
+	{ 0x2e060190, 0x30000 },	/* 100 */
+	{ 0x2e060194, 0x50004 },	/* 101 */
+	{ 0x2e060198, 0x4 },	/* 102 */
+	{ 0x2e06019c, 0x40003 },	/* 103 */
+	{ 0x2e0601a0, 0x40005 },	/* 104 */
+	{ 0x2e0601a8, 0x2cc0 },	/* 106 */
+	{ 0x2e0601ac, 0x2cc0 },	/* 107 */
+	{ 0x2e0601b0, 0x2cc0 },	/* 108 */
+	{ 0x2e0601b4, 0x2cc0 },	/* 109 */
+	{ 0x2e0601b8, 0x2cc0 },	/* 110 */
+	{ 0x2e0601c0, 0x4e5 },	/* 112 */
+	{ 0x2e0601c4, 0xff40 },	/* 113 */
+	{ 0x2e0601c8, 0xff40 },	/* 114 */
+	{ 0x2e0601cc, 0xff40 },	/* 115 */
+	{ 0x2e0601d0, 0xff40 },	/* 116 */
+	{ 0x2e0601d4, 0xff40 },	/* 117 */
+	{ 0x2e0601dc, 0x1beb },	/* 119 */
+	{ 0x2e0601e0, 0x200c0 },	/* 120 */
+	{ 0x2e0601e4, 0x200c0 },	/* 121 */
+	{ 0x2e0601e8, 0x200c0 },	/* 122 */
+	{ 0x2e0601ec, 0x200c0 },	/* 123 */
+	{ 0x2e0601f0, 0x200c0 },	/* 124 */
+	{ 0x2e0601f8, 0x3815 },	/* 126 */
+	{ 0x2e06021c, 0x5000000 },	/* 135 */
+	{ 0x2e060220, 0x5030503 },	/* 136 */
+	{ 0x2e060224, 0x3 },	/* 137 */
+	{ 0x2e060228, 0x7010a09 },	/* 138 */
+	{ 0x2e06022c, 0xe0a09 },	/* 139 */
+	{ 0x2e060230, 0x10a0900 },	/* 140 */
+	{ 0x2e060234, 0xe0a0907 },	/* 141 */
+	{ 0x2e060238, 0xa090000 },	/* 142 */
+	{ 0x2e06023c, 0xa090701 },	/* 143 */
+	{ 0x2e060240, 0x101000e },	/* 144 */
+	{ 0x2e060244, 0x40003 },	/* 145 */
+	{ 0x2e060248, 0x7 },	/* 146 */
+	{ 0x2e060264, 0x4040100 },	/* 153 */
+	{ 0x2e060268, 0x1000000 },	/* 154 */
+	{ 0x2e06026c, 0x100000c0 },	/* 155 */
+	{ 0x2e060270, 0x100000c0 },	/* 156 */
+	{ 0x2e060274, 0x100000c0 },	/* 157 */
+	{ 0x2e06027c, 0x1600 },	/* 159 */
+	{ 0x2e060284, 0x1 },	/* 161 */
+	{ 0x2e060288, 0x2 },	/* 162 */
+	{ 0x2e06028c, 0x100e },	/* 163 */
+	{ 0x2e0602a4, 0xa0000 },	/* 169 */
+	{ 0x2e0602a8, 0xd0005 },	/* 170 */
+	{ 0x2e0602ac, 0x404 },	/* 171 */
+	{ 0x2e0602b0, 0xd },	/* 172 */
+	{ 0x2e0602b4, 0x1b0035 },	/* 173 */
+	{ 0x2e0602b8, 0x4040042 },	/* 174 */
+	{ 0x2e0602bc, 0x42 },	/* 175 */
+	{ 0x2e0602c0, 0x35006a },	/* 176 */
+	{ 0x2e0602c4, 0x4040084 },	/* 177 */
+	{ 0x2e0602c8, 0x84 },	/* 178 */
+	{ 0x2e0602d8, 0x40004 },	/* 182 */
+	{ 0x2e0602dc, 0x30000914 },	/* 183 */
+	{ 0x2e0602e0, 0x3030 },	/* 184 */
+	{ 0x2e0602e4, 0x44440000 },	/* 185 */
+	{ 0x2e0602e8, 0x19191944 },	/* 186 */
+	{ 0x2e0602ec, 0x19191908 },	/* 187 */
+	{ 0x2e0602f0, 0x4000000 },	/* 188 */
+	{ 0x2e0602f4, 0x40404 },	/* 189 */
+	{ 0x2e0602f8, 0x9140004 },	/* 190 */
+	{ 0x2e0602fc, 0x30303000 },	/* 191 */
+	{ 0x2e060304, 0x19444444 },	/* 193 */
+	{ 0x2e060308, 0x19081919 },	/* 194 */
+	{ 0x2e06030c, 0x1919 },	/* 195 */
+	{ 0x2e060310, 0x4040400 },	/* 196 */
+	{ 0x2e060314, 0x1010120 },	/* 197 */
+	{ 0x2e060318, 0x1000100 },	/* 198 */
+	{ 0x2e06031c, 0x1 },	/* 199 */
+	{ 0x2e060324, 0x1000000 },	/* 201 */
+	{ 0x2e060328, 0x1 },	/* 202 */
+	{ 0x2e060354, 0x11000000 },	/* 213 */
+	{ 0x2e060358, 0x40c1815 },	/* 214 */
+	{ 0x2e060390, 0x30000 },	/* 228 */
+	{ 0x2e060394, 0x1000200 },	/* 229 */
+	{ 0x2e060398, 0x310040 },	/* 230 */
+	{ 0x2e06039c, 0x20002 },	/* 231 */
+	{ 0x2e0603a0, 0x400100 },	/* 232 */
+	{ 0x2e0603a4, 0x80108 },	/* 233 */
+	{ 0x2e0603a8, 0x1000200 },	/* 234 */
+	{ 0x2e0603ac, 0x2100040 },	/* 235 */
+	{ 0x2e0603b0, 0x10 },	/* 236 */
+	{ 0x2e0603b4, 0xe0003 },	/* 237 */
+	{ 0x2e0603b8, 0x100001b },	/* 238 */
+	{ 0x2e0603d8, 0xffff0b00 },	/* 246 */
+	{ 0x2e0603dc, 0x1010001 },	/* 247 */
+	{ 0x2e0603e0, 0x1010101 },	/* 248 */
+	{ 0x2e0603e4, 0x10b0101 },	/* 249 */
+	{ 0x2e0603e8, 0x10000 },	/* 250 */
+	{ 0x2e0603ec, 0x4010101 },	/* 251 */
+	{ 0x2e0603f0, 0x1010000 },	/* 252 */
+	{ 0x2e0603f4, 0x4 },	/* 253 */
+	{ 0x2e0603fc, 0x3030101 },	/* 255 */
+	{ 0x2e060400, 0x103 },	/* 256 */
+	{ 0x2e0604a4, 0x2020101 },	/* 297 */
+	{ 0x2e0604a8, 0x10100 },	/* 298 */
+	{ 0x2e0604ac, 0x1000101 },	/* 299 */
+	{ 0x2e0604b0, 0x1010101 },	/* 300 */
+	{ 0x2e0604b4, 0x4030300 },	/* 301 */
+	{ 0x2e0604b8, 0x8080505 },	/* 302 */
+	{ 0x2e0604bc, 0x8020808 },	/* 303 */
+	{ 0x2e0604c0, 0x8020e00 },	/* 304 */
+	{ 0x2e0604c4, 0xa020e00 },	/* 305 */
+	{ 0x2e0604c8, 0x8000f00 },	/* 306 */
+	{ 0x2e0604cc, 0xa08 },	/* 307 */
+	{ 0x2e0604d0, 0x1010101 },	/* 308 */
+	{ 0x2e0604d4, 0x102 },	/* 309 */
+	{ 0x2e0604d8, 0x404 },	/* 310 */
+	{ 0x2e0604dc, 0x40400 },	/* 311 */
+	{ 0x2e0604e0, 0x4040000 },	/* 312 */
+	{ 0x2e0604e4, 0x4000000 },	/* 313 */
+	{ 0x2e0604e8, 0x10004 },	/* 314 */
+	{ 0x2e0604f0, 0xfffff },	/* 316 */
+	{ 0x2e0604f8, 0xfffff },	/* 318 */
+	{ 0x2e060500, 0xfffff },	/* 320 */
+	{ 0x2e060508, 0xfffff },	/* 322 */
+	{ 0x2e060510, 0xfffff },	/* 324 */
+	{ 0x2e060518, 0xfffff },	/* 326 */
+	{ 0x2e060520, 0xfffff },	/* 328 */
+	{ 0x2e060528, 0xfffff },	/* 330 */
+	{ 0x2e060530, 0xfffff },	/* 332 */
+	{ 0x2e060538, 0xfffff },	/* 334 */
+	{ 0x2e060540, 0xfffff },	/* 336 */
+	{ 0x2e060548, 0xfffff },	/* 338 */
+	{ 0x2e060550, 0xfffff },	/* 340 */
+	{ 0x2e060558, 0xfffff },	/* 342 */
+	{ 0x2e060560, 0xfffff },	/* 344 */
+	{ 0x2e060568, 0xfffff },	/* 346 */
+	{ 0x2e060570, 0xfffff },	/* 348 */
+	{ 0x2e060578, 0xfffff },	/* 350 */
+	{ 0x2e060580, 0xfffff },	/* 352 */
+	{ 0x2e060588, 0xfffff },	/* 354 */
+	{ 0x2e060590, 0xfffff },	/* 356 */
+	{ 0x2e060598, 0xfffff },	/* 358 */
+	{ 0x2e0605a0, 0xfffff },	/* 360 */
+	{ 0x2e0605a8, 0xfffff },	/* 362 */
+	{ 0x2e0605b0, 0xfffff },	/* 364 */
+	{ 0x2e0605b8, 0xfffff },	/* 366 */
+	{ 0x2e0605c0, 0xfffff },	/* 368 */
+	{ 0x2e0605c8, 0xfffff },	/* 370 */
+	{ 0x2e0605d0, 0xfffff },	/* 372 */
+	{ 0x2e0605d8, 0xfffff },	/* 374 */
+	{ 0x2e0605e0, 0xfffff },	/* 376 */
+	{ 0x2e0605e8, 0xfffff },	/* 378 */
+	{ 0x2e0605f0, 0xfffff },	/* 380 */
+	{ 0x2e0605f8, 0xfffff },	/* 382 */
+	{ 0x2e060600, 0xfffff },	/* 384 */
+	{ 0x2e060608, 0xfffff },	/* 386 */
+	{ 0x2e060610, 0xfffff },	/* 388 */
+	{ 0x2e060618, 0xfffff },	/* 390 */
+	{ 0x2e060620, 0xfffff },	/* 392 */
+	{ 0x2e060628, 0xfffff },	/* 394 */
+	{ 0x2e060630, 0xfffff },	/* 396 */
+	{ 0x2e060638, 0xfffff },	/* 398 */
+	{ 0x2e060640, 0xfffff },	/* 400 */
+	{ 0x2e060648, 0xfffff },	/* 402 */
+	{ 0x2e060650, 0xfffff },	/* 404 */
+	{ 0x2e060658, 0xfffff },	/* 406 */
+	{ 0x2e060660, 0xfffff },	/* 408 */
+	{ 0x2e060668, 0xfffff },	/* 410 */
+	{ 0x2e060670, 0xfffff },	/* 412 */
+	{ 0x2e060678, 0xfffff },	/* 414 */
+	{ 0x2e060680, 0xfffff },	/* 416 */
+	{ 0x2e060688, 0xfffff },	/* 418 */
+	{ 0x2e060690, 0xfffff },	/* 420 */
+	{ 0x2e060698, 0xfffff },	/* 422 */
+	{ 0x2e0606a0, 0xfffff },	/* 424 */
+	{ 0x2e0606a8, 0xfffff },	/* 426 */
+	{ 0x2e0606b0, 0xfffff },	/* 428 */
+	{ 0x2e0606b8, 0xfffff },	/* 430 */
+	{ 0x2e0606c0, 0xfffff },	/* 432 */
+	{ 0x2e0606c8, 0xfffff },	/* 434 */
+	{ 0x2e0606d0, 0xfffff },	/* 436 */
+	{ 0x2e0606d8, 0xfffff },	/* 438 */
+	{ 0x2e0606e0, 0xfffff },	/* 440 */
+	{ 0x2e0606e8, 0x30fffff },	/* 442 */
+	{ 0x2e0606ec, 0xffffffff },	/* 443 */
+	{ 0x2e0606f0, 0x30f0f },	/* 444 */
+	{ 0x2e0606f4, 0xffffffff },	/* 445 */
+	{ 0x2e0606f8, 0x30f0f },	/* 446 */
+	{ 0x2e0606fc, 0xffffffff },	/* 447 */
+	{ 0x2e060700, 0x30f0f },	/* 448 */
+	{ 0x2e060704, 0xffffffff },	/* 449 */
+	{ 0x2e060708, 0x30f0f },	/* 450 */
+	{ 0x2e06070c, 0xffffffff },	/* 451 */
+	{ 0x2e060710, 0x30f0f },	/* 452 */
+	{ 0x2e060714, 0xffffffff },	/* 453 */
+	{ 0x2e060718, 0x30f0f },	/* 454 */
+	{ 0x2e06071c, 0xffffffff },	/* 455 */
+	{ 0x2e060720, 0x30f0f },	/* 456 */
+	{ 0x2e060724, 0xffffffff },	/* 457 */
+	{ 0x2e060728, 0x30f0f },	/* 458 */
+	{ 0x2e06072c, 0xffffffff },	/* 459 */
+	{ 0x2e060730, 0x30f0f },	/* 460 */
+	{ 0x2e060734, 0xffffffff },	/* 461 */
+	{ 0x2e060738, 0x30f0f },	/* 462 */
+	{ 0x2e06073c, 0xffffffff },	/* 463 */
+	{ 0x2e060740, 0x30f0f },	/* 464 */
+	{ 0x2e060744, 0xffffffff },	/* 465 */
+	{ 0x2e060748, 0x30f0f },	/* 466 */
+	{ 0x2e06074c, 0xffffffff },	/* 467 */
+	{ 0x2e060750, 0x30f0f },	/* 468 */
+	{ 0x2e060754, 0xffffffff },	/* 469 */
+	{ 0x2e060758, 0x30f0f },	/* 470 */
+	{ 0x2e06075c, 0xffffffff },	/* 471 */
+	{ 0x2e060760, 0x30f0f },	/* 472 */
+	{ 0x2e060764, 0xffffffff },	/* 473 */
+	{ 0x2e060768, 0x30f0f },	/* 474 */
+	{ 0x2e06076c, 0xffffffff },	/* 475 */
+	{ 0x2e060770, 0x30f0f },	/* 476 */
+	{ 0x2e060774, 0xffffffff },	/* 477 */
+	{ 0x2e060778, 0x30f0f },	/* 478 */
+	{ 0x2e06077c, 0xffffffff },	/* 479 */
+	{ 0x2e060780, 0x30f0f },	/* 480 */
+	{ 0x2e060784, 0xffffffff },	/* 481 */
+	{ 0x2e060788, 0x30f0f },	/* 482 */
+	{ 0x2e06078c, 0xffffffff },	/* 483 */
+	{ 0x2e060790, 0x30f0f },	/* 484 */
+	{ 0x2e060794, 0xffffffff },	/* 485 */
+	{ 0x2e060798, 0x30f0f },	/* 486 */
+	{ 0x2e06079c, 0xffffffff },	/* 487 */
+	{ 0x2e0607a0, 0x30f0f },	/* 488 */
+	{ 0x2e0607a4, 0xffffffff },	/* 489 */
+	{ 0x2e0607a8, 0x30f0f },	/* 490 */
+	{ 0x2e0607ac, 0xffffffff },	/* 491 */
+	{ 0x2e0607b0, 0x30f0f },	/* 492 */
+	{ 0x2e0607b4, 0xffffffff },	/* 493 */
+	{ 0x2e0607b8, 0x30f0f },	/* 494 */
+	{ 0x2e0607bc, 0xffffffff },	/* 495 */
+	{ 0x2e0607c0, 0x30f0f },	/* 496 */
+	{ 0x2e0607c4, 0xffffffff },	/* 497 */
+	{ 0x2e0607c8, 0x30f0f },	/* 498 */
+	{ 0x2e0607cc, 0xffffffff },	/* 499 */
+	{ 0x2e0607d0, 0x30f0f },	/* 500 */
+	{ 0x2e0607d4, 0xffffffff },	/* 501 */
+	{ 0x2e0607d8, 0x30f0f },	/* 502 */
+	{ 0x2e0607dc, 0xffffffff },	/* 503 */
+	{ 0x2e0607e0, 0x30f0f },	/* 504 */
+	{ 0x2e0607e4, 0xffffffff },	/* 505 */
+	{ 0x2e0607e8, 0x30f0f },	/* 506 */
+	{ 0x2e0607ec, 0xffffffff },	/* 507 */
+	{ 0x2e0607f0, 0x30f0f },	/* 508 */
+	{ 0x2e0607f4, 0xffffffff },	/* 509 */
+	{ 0x2e0607f8, 0x30f0f },	/* 510 */
+	{ 0x2e0607fc, 0xffffffff },	/* 511 */
+	{ 0x2e060800, 0x30f0f },	/* 512 */
+	{ 0x2e060804, 0xffffffff },	/* 513 */
+	{ 0x2e060808, 0x30f0f },	/* 514 */
+	{ 0x2e06080c, 0xffffffff },	/* 515 */
+	{ 0x2e060810, 0x30f0f },	/* 516 */
+	{ 0x2e060814, 0xffffffff },	/* 517 */
+	{ 0x2e060818, 0x30f0f },	/* 518 */
+	{ 0x2e06081c, 0xffffffff },	/* 519 */
+	{ 0x2e060820, 0x30f0f },	/* 520 */
+	{ 0x2e060824, 0xffffffff },	/* 521 */
+	{ 0x2e060828, 0x30f0f },	/* 522 */
+	{ 0x2e06082c, 0xffffffff },	/* 523 */
+	{ 0x2e060830, 0x30f0f },	/* 524 */
+	{ 0x2e060834, 0xffffffff },	/* 525 */
+	{ 0x2e060838, 0x30f0f },	/* 526 */
+	{ 0x2e06083c, 0xffffffff },	/* 527 */
+	{ 0x2e060840, 0x30f0f },	/* 528 */
+	{ 0x2e060844, 0xffffffff },	/* 529 */
+	{ 0x2e060848, 0x30f0f },	/* 530 */
+	{ 0x2e06084c, 0xffffffff },	/* 531 */
+	{ 0x2e060850, 0x30f0f },	/* 532 */
+	{ 0x2e060854, 0xffffffff },	/* 533 */
+	{ 0x2e060858, 0x30f0f },	/* 534 */
+	{ 0x2e06085c, 0xffffffff },	/* 535 */
+	{ 0x2e060860, 0x30f0f },	/* 536 */
+	{ 0x2e060864, 0xffffffff },	/* 537 */
+	{ 0x2e060868, 0x30f0f },	/* 538 */
+	{ 0x2e06086c, 0xffffffff },	/* 539 */
+	{ 0x2e060870, 0x30f0f },	/* 540 */
+	{ 0x2e060874, 0xffffffff },	/* 541 */
+	{ 0x2e060878, 0x30f0f },	/* 542 */
+	{ 0x2e06087c, 0xffffffff },	/* 543 */
+	{ 0x2e060880, 0x30f0f },	/* 544 */
+	{ 0x2e060884, 0xffffffff },	/* 545 */
+	{ 0x2e060888, 0x30f0f },	/* 546 */
+	{ 0x2e06088c, 0xffffffff },	/* 547 */
+	{ 0x2e060890, 0x30f0f },	/* 548 */
+	{ 0x2e060894, 0xffffffff },	/* 549 */
+	{ 0x2e060898, 0x30f0f },	/* 550 */
+	{ 0x2e06089c, 0xffffffff },	/* 551 */
+	{ 0x2e0608a0, 0x30f0f },	/* 552 */
+	{ 0x2e0608a4, 0xffffffff },	/* 553 */
+	{ 0x2e0608a8, 0x30f0f },	/* 554 */
+	{ 0x2e0608ac, 0xffffffff },	/* 555 */
+	{ 0x2e0608b0, 0x30f0f },	/* 556 */
+	{ 0x2e0608b4, 0xffffffff },	/* 557 */
+	{ 0x2e0608b8, 0x30f0f },	/* 558 */
+	{ 0x2e0608bc, 0xffffffff },	/* 559 */
+	{ 0x2e0608c0, 0x30f0f },	/* 560 */
+	{ 0x2e0608c4, 0xffffffff },	/* 561 */
+	{ 0x2e0608c8, 0x30f0f },	/* 562 */
+	{ 0x2e0608cc, 0xffffffff },	/* 563 */
+	{ 0x2e0608d0, 0x30f0f },	/* 564 */
+	{ 0x2e0608d4, 0xffffffff },	/* 565 */
+	{ 0x2e0608d8, 0x30f0f },	/* 566 */
+	{ 0x2e0608dc, 0xffffffff },	/* 567 */
+	{ 0x2e0608e0, 0x30f0f },	/* 568 */
+	{ 0x2e0608e4, 0xffffffff },	/* 569 */
+	{ 0x2e0608e8, 0x32070f0f },	/* 570 */
+	{ 0x2e0608ec, 0x1320001 },	/* 571 */
+	{ 0x2e0608f0, 0x13200 },	/* 572 */
+	{ 0x2e0608f4, 0x132 },	/* 573 */
+	{ 0x2e0608fc, 0x1d1b0000 },	/* 575 */
+	{ 0x2e060900, 0x21 },	/* 576 */
+	{ 0x2e060904, 0xa },	/* 577 */
+	{ 0x2e060908, 0x166 },	/* 578 */
+	{ 0x2e06090c, 0x200 },	/* 579 */
+	{ 0x2e060910, 0x200 },	/* 580 */
+	{ 0x2e060914, 0x200 },	/* 581 */
+	{ 0x2e060918, 0x200 },	/* 582 */
+	{ 0x2e06091c, 0x432 },	/* 583 */
+	{ 0x2e060920, 0xdfc },	/* 584 */
+	{ 0x2e060924, 0x204 },	/* 585 */
+	{ 0x2e060928, 0x7fa },	/* 586 */
+	{ 0x2e06092c, 0x200 },	/* 587 */
+	{ 0x2e060930, 0x200 },	/* 588 */
+	{ 0x2e060934, 0x200 },	/* 589 */
+	{ 0x2e060938, 0x200 },	/* 590 */
+	{ 0x2e06093c, 0x17ee },	/* 591 */
+	{ 0x2e060940, 0x4fc4 },	/* 592 */
+	{ 0x2e060944, 0x204 },	/* 593 */
+	{ 0x2e060948, 0x1006 },	/* 594 */
+	{ 0x2e06094c, 0x200 },	/* 595 */
+	{ 0x2e060950, 0x200 },	/* 596 */
+	{ 0x2e060954, 0x200 },	/* 597 */
+	{ 0x2e060958, 0x200 },	/* 598 */
+	{ 0x2e06095c, 0x3012 },	/* 599 */
+	{ 0x2e060960, 0xa03c },	/* 600 */
+	{ 0x2e060964, 0x2020406 },	/* 601 */
+	{ 0x2e060968, 0x2030202 },	/* 602 */
+	{ 0x2e06096c, 0x1000202 },	/* 603 */
+	{ 0x2e060970, 0x3040100 },	/* 604 */
+	{ 0x2e060974, 0x10105 },	/* 605 */
+	{ 0x2e060978, 0x10101 },	/* 606 */
+	{ 0x2e06097c, 0x10101 },	/* 607 */
+	{ 0x2e060980, 0x10001 },	/* 608 */
+	{ 0x2e060984, 0x101 },	/* 609 */
+	{ 0x2e060988, 0x2000201 },	/* 610 */
+	{ 0x2e06098c, 0x2010000 },	/* 611 */
+	{ 0x2e060990, 0x6000200 },	/* 612 */
+	{ 0x2e060994, 0x3000a06 },	/* 613 */
+	{ 0x2e060998, 0x2000c06 },	/* 614 */
+};
+
+/** PI settings **/
+struct dram_cfg_param ddr_pi_cfg[] = {
+	{ 0x2e062000, 0xb00 },	/* 0 */
+	{ 0x2e062004, 0xbeedb66f },	/* 1 */
+	{ 0x2e062008, 0xabef6bd },	/* 2 */
+	{ 0x2e06200c, 0x1001387 },	/* 3 */
+	{ 0x2e062010, 0x1 },	/* 4 */
+	{ 0x2e062014, 0x10064 },	/* 5 */
+	{ 0x2e06202c, 0x101 },	/* 11 */
+	{ 0x2e062030, 0x3 },	/* 12 */
+	{ 0x2e062034, 0x50001 },	/* 13 */
+	{ 0x2e062038, 0x3030800 },	/* 14 */
+	{ 0x2e06203c, 0x1 },	/* 15 */
+	{ 0x2e062040, 0x5 },	/* 16 */
+	{ 0x2e062064, 0x1000000 },	/* 25 */
+	{ 0x2e062068, 0xa000001 },	/* 26 */
+	{ 0x2e06206c, 0x28 },	/* 27 */
+	{ 0x2e062070, 0x1 },	/* 28 */
+	{ 0x2e062074, 0x320005 },	/* 29 */
+	{ 0x2e062080, 0x10102 },	/* 32 */
+	{ 0x2e062084, 0x1 },	/* 33 */
+	{ 0x2e062088, 0xaa },	/* 34 */
+	{ 0x2e06208c, 0x55 },	/* 35 */
+	{ 0x2e062090, 0xb5 },	/* 36 */
+	{ 0x2e062094, 0x4a },	/* 37 */
+	{ 0x2e062098, 0x56 },	/* 38 */
+	{ 0x2e06209c, 0xa9 },	/* 39 */
+	{ 0x2e0620a0, 0xa9 },	/* 40 */
+	{ 0x2e0620a4, 0xb5 },	/* 41 */
+	{ 0x2e0620a8, 0x10000 },	/* 42 */
+	{ 0x2e0620ac, 0x100 },	/* 43 */
+	{ 0x2e0620b0, 0x5050000 },	/* 44 */
+	{ 0x2e0620b4, 0x13 },	/* 45 */
+	{ 0x2e0620b8, 0x7d0 },	/* 46 */
+	{ 0x2e0620bc, 0x300 },	/* 47 */
+	{ 0x2e0620c8, 0x1000000 },	/* 50 */
+	{ 0x2e0620cc, 0x10101 },	/* 51 */
+	{ 0x2e0620d8, 0x10003 },	/* 54 */
+	{ 0x2e0620dc, 0x170500 },	/* 55 */
+	{ 0x2e0620ec, 0xa140a01 },	/* 59 */
+	{ 0x2e0620f0, 0x204010a },	/* 60 */
+	{ 0x2e0620f4, 0x21010 },	/* 61 */
+	{ 0x2e0620f8, 0x40401 },	/* 62 */
+	{ 0x2e0620fc, 0x10e0005 },	/* 63 */
+	{ 0x2e062100, 0x5000001 },	/* 64 */
+	{ 0x2e062104, 0x204 },	/* 65 */
+	{ 0x2e062108, 0x34 },	/* 66 */
+	{ 0x2e062114, 0x1000000 },	/* 69 */
+	{ 0x2e062118, 0x1000000 },	/* 70 */
+	{ 0x2e06211c, 0x80200 },	/* 71 */
+	{ 0x2e062120, 0x2000200 },	/* 72 */
+	{ 0x2e062124, 0x1000100 },	/* 73 */
+	{ 0x2e062128, 0x1000000 },	/* 74 */
+	{ 0x2e06212c, 0x2000200 },	/* 75 */
+	{ 0x2e062130, 0x200 },	/* 76 */
+	{ 0x2e062164, 0x400 },	/* 89 */
+	{ 0x2e062168, 0x2010000 },	/* 90 */
+	{ 0x2e06216c, 0x80103 },	/* 91 */
+	{ 0x2e062174, 0x10008 },	/* 93 */
+	{ 0x2e06217c, 0xaa00 },	/* 95 */
+	{ 0x2e062188, 0x10000 },	/* 98 */
+	{ 0x2e0621ec, 0x8 },	/* 123 */
+	{ 0x2e062218, 0xf0000 },	/* 134 */
+	{ 0x2e06221c, 0xa },	/* 135 */
+	{ 0x2e062220, 0x19 },	/* 136 */
+	{ 0x2e062224, 0x100 },	/* 137 */
+	{ 0x2e062228, 0x100 },	/* 138 */
+	{ 0x2e062238, 0x1000000 },	/* 142 */
+	{ 0x2e06223c, 0x10003 },	/* 143 */
+	{ 0x2e062240, 0x2000101 },	/* 144 */
+	{ 0x2e062244, 0x1030001 },	/* 145 */
+	{ 0x2e062248, 0x10400 },	/* 146 */
+	{ 0x2e06224c, 0x6000105 },	/* 147 */
+	{ 0x2e062250, 0x1070001 },	/* 148 */
+	{ 0x2e062260, 0x10001 },	/* 152 */
+	{ 0x2e062274, 0x401 },	/* 157 */
+	{ 0x2e06227c, 0x10000 },	/* 159 */
+	{ 0x2e062284, 0x6010000 },	/* 161 */
+	{ 0x2e062288, 0xb },	/* 162 */
+	{ 0x2e06228c, 0x34 },	/* 163 */
+	{ 0x2e062290, 0x36 },	/* 164 */
+	{ 0x2e062294, 0x2003c },	/* 165 */
+	{ 0x2e062298, 0x2000200 },	/* 166 */
+	{ 0x2e06229c, 0xc040c04 },	/* 167 */
+	{ 0x2e0622a0, 0xe1406 },	/* 168 */
+	{ 0x2e0622a4, 0xb3 },	/* 169 */
+	{ 0x2e0622a8, 0x4a },	/* 170 */
+	{ 0x2e0622ac, 0x3fd },	/* 171 */
+	{ 0x2e0622b0, 0x94 },	/* 172 */
+	{ 0x2e0622b4, 0x4000803 },	/* 173 */
+	{ 0x2e0622b8, 0x1010404 },	/* 174 */
+	{ 0x2e0622bc, 0x1501 },	/* 175 */
+	{ 0x2e0622c0, 0x1a0018 },	/* 176 */
+	{ 0x2e0622c4, 0x1000100 },	/* 177 */
+	{ 0x2e0622c8, 0x100 },	/* 178 */
+	{ 0x2e0622d0, 0x5040303 },	/* 180 */
+	{ 0x2e0622d4, 0x1010805 },	/* 181 */
+	{ 0x2e0622d8, 0x1010101 },	/* 182 */
+	{ 0x2e0622e8, 0x2060404 },	/* 186 */
+	{ 0x2e0622ec, 0x2020402 },	/* 187 */
+	{ 0x2e0622f0, 0x3102 },	/* 188 */
+	{ 0x2e0622f4, 0x340009 },	/* 189 */
+	{ 0x2e0622f8, 0x36000c },	/* 190 */
+	{ 0x2e0622fc, 0x101000e },	/* 191 */
+	{ 0x2e062300, 0xd0101 },	/* 192 */
+	{ 0x2e062304, 0x1004201 },	/* 193 */
+	{ 0x2e062308, 0x1000084 },	/* 194 */
+	{ 0x2e06230c, 0xe000e },	/* 195 */
+	{ 0x2e062310, 0x430100 },	/* 196 */
+	{ 0x2e062314, 0x1000043 },	/* 197 */
+	{ 0x2e062318, 0x850085 },	/* 198 */
+	{ 0x2e06231c, 0x220f220f },	/* 199 */
+	{ 0x2e062320, 0x101220f },	/* 200 */
+	{ 0x2e062324, 0xa070601 },	/* 201 */
+	{ 0x2e062328, 0xa07060d },	/* 202 */
+	{ 0x2e06232c, 0xa07070d },	/* 203 */
+	{ 0x2e062330, 0xc00d },	/* 204 */
+	{ 0x2e062334, 0xc01000 },	/* 205 */
+	{ 0x2e062338, 0xc01000 },	/* 206 */
+	{ 0x2e06233c, 0x21000 },	/* 207 */
+	{ 0x2e062340, 0x11000d },	/* 208 */
+	{ 0x2e062344, 0x140042 },	/* 209 */
+	{ 0x2e062348, 0x190084 },	/* 210 */
+	{ 0x2e06234c, 0x220f0056 },	/* 211 */
+	{ 0x2e062350, 0x101 },	/* 212 */
+	{ 0x2e062354, 0x560019 },	/* 213 */
+	{ 0x2e062358, 0x101220f },	/* 214 */
+	{ 0x2e06235c, 0x1b00 },	/* 215 */
+	{ 0x2e062360, 0x220f0056 },	/* 216 */
+	{ 0x2e062364, 0x8000101 },	/* 217 */
+	{ 0x2e062368, 0x4090403 },	/* 218 */
+	{ 0x2e06236c, 0x5eb },	/* 219 */
+	{ 0x2e062370, 0x20010003 },	/* 220 */
+	{ 0x2e062374, 0x80a0a03 },	/* 221 */
+	{ 0x2e062378, 0x6090506 },	/* 222 */
+	{ 0x2e06237c, 0x2093 },	/* 223 */
+	{ 0x2e062380, 0x2001000c },	/* 224 */
+	{ 0x2e062384, 0x80a0a04 },	/* 225 */
+	{ 0x2e062388, 0xb090a0c },	/* 226 */
+	{ 0x2e06238c, 0x4126 },	/* 227 */
+	{ 0x2e062390, 0x20020017 },	/* 228 */
+	{ 0x2e062394, 0xa0a08 },	/* 229 */
+	{ 0x2e062398, 0x166 },	/* 230 */
+	{ 0x2e06239c, 0xdfc },	/* 231 */
+	{ 0x2e0623a0, 0x7fa },	/* 232 */
+	{ 0x2e0623a4, 0x4fc4 },	/* 233 */
+	{ 0x2e0623a8, 0x1006 },	/* 234 */
+	{ 0x2e0623ac, 0xa03c },	/* 235 */
+	{ 0x2e0623b0, 0x4c000e },	/* 236 */
+	{ 0x2e0623b4, 0x3030098 },	/* 237 */
+	{ 0x2e0623b8, 0x258103 },	/* 238 */
+	{ 0x2e0623bc, 0x17702 },	/* 239 */
+	{ 0x2e0623c0, 0x5 },	/* 240 */
+	{ 0x2e0623c4, 0x61 },	/* 241 */
+	{ 0x2e0623c8, 0xe },	/* 242 */
+	{ 0x2e0623cc, 0xce3f },	/* 243 */
+	{ 0x2e0623d0, 0x80e70 },	/* 244 */
+	{ 0x2e0623d4, 0x5 },	/* 245 */
+	{ 0x2e0623d8, 0x210 },	/* 246 */
+	{ 0x2e0623dc, 0x4c },	/* 247 */
+	{ 0x2e0623e0, 0x19c7d },	/* 248 */
+	{ 0x2e0623e4, 0x101cdf },	/* 249 */
+	{ 0x2e0623e8, 0x5 },	/* 250 */
+	{ 0x2e0623ec, 0x420 },	/* 251 */
+	{ 0x2e0623f0, 0x1000098 },	/* 252 */
+	{ 0x2e0623f4, 0x310040 },	/* 253 */
+	{ 0x2e0623f8, 0x10002 },	/* 254 */
+	{ 0x2e0623fc, 0x1080040 },	/* 255 */
+	{ 0x2e062400, 0x10008 },	/* 256 */
+	{ 0x2e062404, 0x2100040 },	/* 257 */
+	{ 0x2e062408, 0x310 },	/* 258 */
+	{ 0x2e06240c, 0x1b000e },	/* 259 */
+	{ 0x2e062410, 0x1010101 },	/* 260 */
+	{ 0x2e062414, 0x2020101 },	/* 261 */
+	{ 0x2e062418, 0x8080404 },	/* 262 */
+	{ 0x2e06241c, 0x5508 },	/* 263 */
+	{ 0x2e062420, 0x83c5a00 },	/* 264 */
+	{ 0x2e062424, 0x55 },	/* 265 */
+	{ 0x2e062428, 0x55083c5a },	/* 266 */
+	{ 0x2e06242c, 0x5a000000 },	/* 267 */
+	{ 0x2e062430, 0x55083c },	/* 268 */
+	{ 0x2e062434, 0x3c5a0000 },	/* 269 */
+	{ 0x2e062438, 0xf0e0d0c },	/* 270 */
+	{ 0x2e06243c, 0xb0a0908 },	/* 271 */
+	{ 0x2e062440, 0x7060504 },	/* 272 */
+	{ 0x2e062444, 0x3020100 },	/* 273 */
+	{ 0x2e06244c, 0x2020101 },	/* 275 */
+	{ 0x2e062450, 0x8080404 },	/* 276 */
+	{ 0x2e062454, 0x44300004 },	/* 277 */
+	{ 0x2e062458, 0x4041919 },	/* 278 */
+	{ 0x2e06245c, 0x19443000 },	/* 279 */
+	{ 0x2e062460, 0x9140419 },	/* 280 */
+	{ 0x2e062464, 0x19194430 },	/* 281 */
+	{ 0x2e062468, 0x30000404 },	/* 282 */
+	{ 0x2e06246c, 0x4191944 },	/* 283 */
+	{ 0x2e062470, 0x44300004 },	/* 284 */
+	{ 0x2e062474, 0x14041919 },	/* 285 */
+	{ 0x2e062478, 0x19443009 },	/* 286 */
+	{ 0x2e06247c, 0x40419 },	/* 287 */
+	{ 0x2e062480, 0x19194430 },	/* 288 */
+	{ 0x2e062484, 0x30000404 },	/* 289 */
+	{ 0x2e062488, 0x4191944 },	/* 290 */
+	{ 0x2e06248c, 0x44300914 },	/* 291 */
+	{ 0x2e062490, 0x44041919 },	/* 292 */
+	{ 0x2e062494, 0x19443000 },	/* 293 */
+	{ 0x2e062498, 0x40419 },	/* 294 */
+	{ 0x2e06249c, 0x19194430 },	/* 295 */
+	{ 0x2e0624a0, 0x30091404 },	/* 296 */
+	{ 0x2e0624a4, 0x4191944 },	/* 297 */
+};
+
+/** PHY_F1 settings **/
+struct dram_cfg_param ddr_phy_f1_cfg[] = {
+	{ 0x2e064000, 0x4f0 },	/* 0 */
+	{ 0x2e064008, 0x1030200 },	/* 2 */
+	{ 0x2e064014, 0x3000000 },	/* 5 */
+	{ 0x2e064018, 0x1000001 },	/* 6 */
+	{ 0x2e06401c, 0x3000400 },	/* 7 */
+	{ 0x2e064020, 0x1 },	/* 8 */
+	{ 0x2e064024, 0x1 },	/* 9 */
+	{ 0x2e064030, 0x10000 },	/* 12 */
+	{ 0x2e064038, 0xc00004 },	/* 14 */
+	{ 0x2e06403c, 0xcc0008 },	/* 15 */
+	{ 0x2e064040, 0x660601 },	/* 16 */
+	{ 0x2e064044, 0x3 },	/* 17 */
+	{ 0x2e06404c, 0x1 },	/* 19 */
+	{ 0x2e064050, 0xaaaa },	/* 20 */
+	{ 0x2e064054, 0x5555 },	/* 21 */
+	{ 0x2e064058, 0xb5b5 },	/* 22 */
+	{ 0x2e06405c, 0x4a4a },	/* 23 */
+	{ 0x2e064060, 0x5656 },	/* 24 */
+	{ 0x2e064064, 0xa9a9 },	/* 25 */
+	{ 0x2e064068, 0xb7b7 },	/* 26 */
+	{ 0x2e06406c, 0x4848 },	/* 27 */
+	{ 0x2e064078, 0x8000000 },	/* 30 */
+	{ 0x2e06407c, 0x4010008 },	/* 31 */
+	{ 0x2e064080, 0x408 },	/* 32 */
+	{ 0x2e064084, 0x3102000 },	/* 33 */
+	{ 0x2e064088, 0xc0020 },	/* 34 */
+	{ 0x2e06408c, 0x10000 },	/* 35 */
+	{ 0x2e064090, 0x55555555 },	/* 36 */
+	{ 0x2e064094, 0xaaaaaaaa },	/* 37 */
+	{ 0x2e064098, 0x55555555 },	/* 38 */
+	{ 0x2e06409c, 0xaaaaaaaa },	/* 39 */
+	{ 0x2e0640a0, 0x5555 },	/* 40 */
+	{ 0x2e0640a4, 0x1000100 },	/* 41 */
+	{ 0x2e0640a8, 0x800180 },	/* 42 */
+	{ 0x2e0640ac, 0x1 },	/* 43 */
+	{ 0x2e064100, 0x4 },	/* 64 */
+	{ 0x2e06411c, 0x41f07ff },	/* 71 */
+	{ 0x2e064120, 0x1 },	/* 72 */
+	{ 0x2e064124, 0x1cc0800 },	/* 73 */
+	{ 0x2e064128, 0x3003cc08 },	/* 74 */
+	{ 0x2e06412c, 0x2000014e },	/* 75 */
+	{ 0x2e064130, 0x7ff0200 },	/* 76 */
+	{ 0x2e064134, 0x301 },	/* 77 */
+	{ 0x2e064140, 0x30000 },	/* 80 */
+	{ 0x2e064154, 0x2000000 },	/* 85 */
+	{ 0x2e064158, 0x51515042 },	/* 86 */
+	{ 0x2e06415c, 0x31c06000 },	/* 87 */
+	{ 0x2e064160, 0x6bf000a },	/* 88 */
+	{ 0x2e064164, 0xc0c000 },	/* 89 */
+	{ 0x2e064168, 0x1000000 },	/* 90 */
+	{ 0x2e06416c, 0x10001000 },	/* 91 */
+	{ 0x2e064170, 0xc043242 },	/* 92 */
+	{ 0x2e064174, 0xf0c1201 },	/* 93 */
+	{ 0x2e064178, 0x1000140 },	/* 94 */
+	{ 0x2e06417c, 0xc000120 },	/* 95 */
+	{ 0x2e064180, 0x143 },	/* 96 */
+	{ 0x2e064184, 0x1000203 },	/* 97 */
+	{ 0x2e064188, 0x56417032 },	/* 98 */
+	{ 0x2e06418c, 0x8 },	/* 99 */
+	{ 0x2e064190, 0x2c302c3 },	/* 100 */
+	{ 0x2e064194, 0x2c302c3 },	/* 101 */
+	{ 0x2e064198, 0x2c302c3 },	/* 102 */
+	{ 0x2e06419c, 0x2c302c3 },	/* 103 */
+	{ 0x2e0641a0, 0x2c3 },	/* 104 */
+	{ 0x2e0641a4, 0x8000 },	/* 105 */
+	{ 0x2e0641a8, 0x800080 },	/* 106 */
+	{ 0x2e0641ac, 0x800080 },	/* 107 */
+	{ 0x2e0641b0, 0x800080 },	/* 108 */
+	{ 0x2e0641b4, 0x800080 },	/* 109 */
+	{ 0x2e0641b8, 0x800080 },	/* 110 */
+	{ 0x2e0641bc, 0x800080 },	/* 111 */
+	{ 0x2e0641c0, 0x800080 },	/* 112 */
+	{ 0x2e0641c4, 0x800080 },	/* 113 */
+	{ 0x2e0641c8, 0x6b0080 },	/* 114 */
+	{ 0x2e0641cc, 0x1a00001 },	/* 115 */
+	{ 0x2e0641d4, 0x10000 },	/* 117 */
+	{ 0x2e0641d8, 0x80200 },	/* 118 */
+	{ 0x2e064400, 0x4f0 },	/* 256 */
+	{ 0x2e064408, 0x1030200 },	/* 258 */
+	{ 0x2e064414, 0x3000000 },	/* 261 */
+	{ 0x2e064418, 0x1000001 },	/* 262 */
+	{ 0x2e06441c, 0x3000400 },	/* 263 */
+	{ 0x2e064420, 0x1 },	/* 264 */
+	{ 0x2e064424, 0x1 },	/* 265 */
+	{ 0x2e064430, 0x10000 },	/* 268 */
+	{ 0x2e064438, 0xc00004 },	/* 270 */
+	{ 0x2e06443c, 0xcc0008 },	/* 271 */
+	{ 0x2e064440, 0x660601 },	/* 272 */
+	{ 0x2e064444, 0x3 },	/* 273 */
+	{ 0x2e06444c, 0x1 },	/* 275 */
+	{ 0x2e064450, 0xaaaa },	/* 276 */
+	{ 0x2e064454, 0x5555 },	/* 277 */
+	{ 0x2e064458, 0xb5b5 },	/* 278 */
+	{ 0x2e06445c, 0x4a4a },	/* 279 */
+	{ 0x2e064460, 0x5656 },	/* 280 */
+	{ 0x2e064464, 0xa9a9 },	/* 281 */
+	{ 0x2e064468, 0xb7b7 },	/* 282 */
+	{ 0x2e06446c, 0x4848 },	/* 283 */
+	{ 0x2e064478, 0x8000000 },	/* 286 */
+	{ 0x2e06447c, 0x4010008 },	/* 287 */
+	{ 0x2e064480, 0x408 },	/* 288 */
+	{ 0x2e064484, 0x3102000 },	/* 289 */
+	{ 0x2e064488, 0xc0020 },	/* 290 */
+	{ 0x2e06448c, 0x10000 },	/* 291 */
+	{ 0x2e064490, 0x55555555 },	/* 292 */
+	{ 0x2e064494, 0xaaaaaaaa },	/* 293 */
+	{ 0x2e064498, 0x55555555 },	/* 294 */
+	{ 0x2e06449c, 0xaaaaaaaa },	/* 295 */
+	{ 0x2e0644a0, 0x5555 },	/* 296 */
+	{ 0x2e0644a4, 0x1000100 },	/* 297 */
+	{ 0x2e0644a8, 0x800180 },	/* 298 */
+	{ 0x2e064500, 0x4 },	/* 320 */
+	{ 0x2e06451c, 0x41f07ff },	/* 327 */
+	{ 0x2e064520, 0x1 },	/* 328 */
+	{ 0x2e064524, 0x1cc0800 },	/* 329 */
+	{ 0x2e064528, 0x3003cc08 },	/* 330 */
+	{ 0x2e06452c, 0x2000014e },	/* 331 */
+	{ 0x2e064530, 0x7ff0200 },	/* 332 */
+	{ 0x2e064534, 0x301 },	/* 333 */
+	{ 0x2e064540, 0x30000 },	/* 336 */
+	{ 0x2e064554, 0x2000000 },	/* 341 */
+	{ 0x2e064558, 0x51515042 },	/* 342 */
+	{ 0x2e06455c, 0x31c06000 },	/* 343 */
+	{ 0x2e064560, 0x6bf000a },	/* 344 */
+	{ 0x2e064564, 0xc0c000 },	/* 345 */
+	{ 0x2e064568, 0x1000000 },	/* 346 */
+	{ 0x2e06456c, 0x10001000 },	/* 347 */
+	{ 0x2e064570, 0xc043242 },	/* 348 */
+	{ 0x2e064574, 0xf0c1201 },	/* 349 */
+	{ 0x2e064578, 0x1000140 },	/* 350 */
+	{ 0x2e06457c, 0xc000120 },	/* 351 */
+	{ 0x2e064580, 0x143 },	/* 352 */
+	{ 0x2e064584, 0x1000203 },	/* 353 */
+	{ 0x2e064588, 0x30217465 },	/* 354 */
+	{ 0x2e06458c, 0x8 },	/* 355 */
+	{ 0x2e064590, 0x2c302c3 },	/* 356 */
+	{ 0x2e064594, 0x2c302c3 },	/* 357 */
+	{ 0x2e064598, 0x2c302c3 },	/* 358 */
+	{ 0x2e06459c, 0x2c302c3 },	/* 359 */
+	{ 0x2e0645a0, 0x2c3 },	/* 360 */
+	{ 0x2e0645a4, 0x8000 },	/* 361 */
+	{ 0x2e0645a8, 0x800080 },	/* 362 */
+	{ 0x2e0645ac, 0x800080 },	/* 363 */
+	{ 0x2e0645b0, 0x800080 },	/* 364 */
+	{ 0x2e0645b4, 0x800080 },	/* 365 */
+	{ 0x2e0645b8, 0x800080 },	/* 366 */
+	{ 0x2e0645bc, 0x800080 },	/* 367 */
+	{ 0x2e0645c0, 0x800080 },	/* 368 */
+	{ 0x2e0645c4, 0x800080 },	/* 369 */
+	{ 0x2e0645c8, 0x6b0080 },	/* 370 */
+	{ 0x2e0645cc, 0x1a00001 },	/* 371 */
+	{ 0x2e0645d4, 0x10000 },	/* 373 */
+	{ 0x2e0645d8, 0x80200 },	/* 374 */
+	{ 0x2e064800, 0x4f0 },	/* 512 */
+	{ 0x2e064808, 0x1030200 },	/* 514 */
+	{ 0x2e064814, 0x3000000 },	/* 517 */
+	{ 0x2e064818, 0x1000001 },	/* 518 */
+	{ 0x2e06481c, 0x3000400 },	/* 519 */
+	{ 0x2e064820, 0x1 },	/* 520 */
+	{ 0x2e064824, 0x1 },	/* 521 */
+	{ 0x2e064830, 0x10000 },	/* 524 */
+	{ 0x2e064838, 0xc00004 },	/* 526 */
+	{ 0x2e06483c, 0xcc0008 },	/* 527 */
+	{ 0x2e064840, 0x660601 },	/* 528 */
+	{ 0x2e064844, 0x3 },	/* 529 */
+	{ 0x2e06484c, 0x1 },	/* 531 */
+	{ 0x2e064850, 0xaaaa },	/* 532 */
+	{ 0x2e064854, 0x5555 },	/* 533 */
+	{ 0x2e064858, 0xb5b5 },	/* 534 */
+	{ 0x2e06485c, 0x4a4a },	/* 535 */
+	{ 0x2e064860, 0x5656 },	/* 536 */
+	{ 0x2e064864, 0xa9a9 },	/* 537 */
+	{ 0x2e064868, 0xb7b7 },	/* 538 */
+	{ 0x2e06486c, 0x4848 },	/* 539 */
+	{ 0x2e064878, 0x8000000 },	/* 542 */
+	{ 0x2e06487c, 0x4010008 },	/* 543 */
+	{ 0x2e064880, 0x408 },	/* 544 */
+	{ 0x2e064884, 0x3102000 },	/* 545 */
+	{ 0x2e064888, 0xc0020 },	/* 546 */
+	{ 0x2e06488c, 0x10000 },	/* 547 */
+	{ 0x2e064890, 0x55555555 },	/* 548 */
+	{ 0x2e064894, 0xaaaaaaaa },	/* 549 */
+	{ 0x2e064898, 0x55555555 },	/* 550 */
+	{ 0x2e06489c, 0xaaaaaaaa },	/* 551 */
+	{ 0x2e0648a0, 0x5555 },	/* 552 */
+	{ 0x2e0648a4, 0x1000100 },	/* 553 */
+	{ 0x2e0648a8, 0x800180 },	/* 554 */
+	{ 0x2e0648ac, 0x1 },	/* 555 */
+	{ 0x2e064900, 0x4 },	/* 576 */
+	{ 0x2e06491c, 0x41f07ff },	/* 583 */
+	{ 0x2e064920, 0x1 },	/* 584 */
+	{ 0x2e064924, 0x1cc0800 },	/* 585 */
+	{ 0x2e064928, 0x3003cc08 },	/* 586 */
+	{ 0x2e06492c, 0x2000014e },	/* 587 */
+	{ 0x2e064930, 0x7ff0200 },	/* 588 */
+	{ 0x2e064934, 0x301 },	/* 589 */
+	{ 0x2e064940, 0x30000 },	/* 592 */
+	{ 0x2e064954, 0x2000000 },	/* 597 */
+	{ 0x2e064958, 0x51515042 },	/* 598 */
+	{ 0x2e06495c, 0x31c06000 },	/* 599 */
+	{ 0x2e064960, 0x6bf000a },	/* 600 */
+	{ 0x2e064964, 0xc0c000 },	/* 601 */
+	{ 0x2e064968, 0x1000000 },	/* 602 */
+	{ 0x2e06496c, 0x10001000 },	/* 603 */
+	{ 0x2e064970, 0xc043242 },	/* 604 */
+	{ 0x2e064974, 0xf0c1201 },	/* 605 */
+	{ 0x2e064978, 0x1000140 },	/* 606 */
+	{ 0x2e06497c, 0xc000120 },	/* 607 */
+	{ 0x2e064980, 0x143 },	/* 608 */
+	{ 0x2e064984, 0x1000203 },	/* 609 */
+	{ 0x2e064988, 0x75436012 },	/* 610 */
+	{ 0x2e06498c, 0x8 },	/* 611 */
+	{ 0x2e064990, 0x2c302c3 },	/* 612 */
+	{ 0x2e064994, 0x2c302c3 },	/* 613 */
+	{ 0x2e064998, 0x2c302c3 },	/* 614 */
+	{ 0x2e06499c, 0x2c302c3 },	/* 615 */
+	{ 0x2e0649a0, 0x2c3 },	/* 616 */
+	{ 0x2e0649a4, 0x8000 },	/* 617 */
+	{ 0x2e0649a8, 0x800080 },	/* 618 */
+	{ 0x2e0649ac, 0x800080 },	/* 619 */
+	{ 0x2e0649b0, 0x800080 },	/* 620 */
+	{ 0x2e0649b4, 0x800080 },	/* 621 */
+	{ 0x2e0649b8, 0x800080 },	/* 622 */
+	{ 0x2e0649bc, 0x800080 },	/* 623 */
+	{ 0x2e0649c0, 0x800080 },	/* 624 */
+	{ 0x2e0649c4, 0x800080 },	/* 625 */
+	{ 0x2e0649c8, 0x6b0080 },	/* 626 */
+	{ 0x2e0649cc, 0x1a00001 },	/* 627 */
+	{ 0x2e0649d4, 0x10000 },	/* 629 */
+	{ 0x2e0649d8, 0x80200 },	/* 630 */
+	{ 0x2e064c00, 0x4f0 },	/* 768 */
+	{ 0x2e064c08, 0x1030200 },	/* 770 */
+	{ 0x2e064c14, 0x3000000 },	/* 773 */
+	{ 0x2e064c18, 0x1000001 },	/* 774 */
+	{ 0x2e064c1c, 0x3000400 },	/* 775 */
+	{ 0x2e064c20, 0x1 },	/* 776 */
+	{ 0x2e064c24, 0x1 },	/* 777 */
+	{ 0x2e064c30, 0x10000 },	/* 780 */
+	{ 0x2e064c38, 0xc00004 },	/* 782 */
+	{ 0x2e064c3c, 0xcc0008 },	/* 783 */
+	{ 0x2e064c40, 0x660601 },	/* 784 */
+	{ 0x2e064c44, 0x3 },	/* 785 */
+	{ 0x2e064c4c, 0x1 },	/* 787 */
+	{ 0x2e064c50, 0xaaaa },	/* 788 */
+	{ 0x2e064c54, 0x5555 },	/* 789 */
+	{ 0x2e064c58, 0xb5b5 },	/* 790 */
+	{ 0x2e064c5c, 0x4a4a },	/* 791 */
+	{ 0x2e064c60, 0x5656 },	/* 792 */
+	{ 0x2e064c64, 0xa9a9 },	/* 793 */
+	{ 0x2e064c68, 0xb7b7 },	/* 794 */
+	{ 0x2e064c6c, 0x4848 },	/* 795 */
+	{ 0x2e064c78, 0x8000000 },	/* 798 */
+	{ 0x2e064c7c, 0x4010008 },	/* 799 */
+	{ 0x2e064c80, 0x408 },	/* 800 */
+	{ 0x2e064c84, 0x3102000 },	/* 801 */
+	{ 0x2e064c88, 0xc0020 },	/* 802 */
+	{ 0x2e064c8c, 0x10000 },	/* 803 */
+	{ 0x2e064c90, 0x55555555 },	/* 804 */
+	{ 0x2e064c94, 0xaaaaaaaa },	/* 805 */
+	{ 0x2e064c98, 0x55555555 },	/* 806 */
+	{ 0x2e064c9c, 0xaaaaaaaa },	/* 807 */
+	{ 0x2e064ca0, 0x5555 },	/* 808 */
+	{ 0x2e064ca4, 0x1000100 },	/* 809 */
+	{ 0x2e064ca8, 0x800180 },	/* 810 */
+	{ 0x2e064d00, 0x4 },	/* 832 */
+	{ 0x2e064d1c, 0x41f07ff },	/* 839 */
+	{ 0x2e064d20, 0x1 },	/* 840 */
+	{ 0x2e064d24, 0x1cc0800 },	/* 841 */
+	{ 0x2e064d28, 0x3003cc08 },	/* 842 */
+	{ 0x2e064d2c, 0x2000014e },	/* 843 */
+	{ 0x2e064d30, 0x7ff0200 },	/* 844 */
+	{ 0x2e064d34, 0x301 },	/* 845 */
+	{ 0x2e064d40, 0x30000 },	/* 848 */
+	{ 0x2e064d54, 0x2000000 },	/* 853 */
+	{ 0x2e064d58, 0x51515042 },	/* 854 */
+	{ 0x2e064d5c, 0x31c06000 },	/* 855 */
+	{ 0x2e064d60, 0x6bf000a },	/* 856 */
+	{ 0x2e064d64, 0xc0c000 },	/* 857 */
+	{ 0x2e064d68, 0x1000000 },	/* 858 */
+	{ 0x2e064d6c, 0x10001000 },	/* 859 */
+	{ 0x2e064d70, 0xc043242 },	/* 860 */
+	{ 0x2e064d74, 0xf0c1201 },	/* 861 */
+	{ 0x2e064d78, 0x1000140 },	/* 862 */
+	{ 0x2e064d7c, 0xc000120 },	/* 863 */
+	{ 0x2e064d80, 0x143 },	/* 864 */
+	{ 0x2e064d84, 0x1000203 },	/* 865 */
+	{ 0x2e064d88, 0x32017465 },	/* 866 */
+	{ 0x2e064d8c, 0x8 },	/* 867 */
+	{ 0x2e064d90, 0x2c302c3 },	/* 868 */
+	{ 0x2e064d94, 0x2c302c3 },	/* 869 */
+	{ 0x2e064d98, 0x2c302c3 },	/* 870 */
+	{ 0x2e064d9c, 0x2c302c3 },	/* 871 */
+	{ 0x2e064da0, 0x2c3 },	/* 872 */
+	{ 0x2e064da4, 0x8000 },	/* 873 */
+	{ 0x2e064da8, 0x800080 },	/* 874 */
+	{ 0x2e064dac, 0x800080 },	/* 875 */
+	{ 0x2e064db0, 0x800080 },	/* 876 */
+	{ 0x2e064db4, 0x800080 },	/* 877 */
+	{ 0x2e064db8, 0x800080 },	/* 878 */
+	{ 0x2e064dbc, 0x800080 },	/* 879 */
+	{ 0x2e064dc0, 0x800080 },	/* 880 */
+	{ 0x2e064dc4, 0x800080 },	/* 881 */
+	{ 0x2e064dc8, 0x6b0080 },	/* 882 */
+	{ 0x2e064dcc, 0x1a00001 },	/* 883 */
+	{ 0x2e064dd4, 0x10000 },	/* 885 */
+	{ 0x2e064dd8, 0x80200 },	/* 886 */
+	{ 0x2e065014, 0x100 },	/* 1029 */
+	{ 0x2e065018, 0x201 },	/* 1030 */
+	{ 0x2e06502c, 0x400000 },	/* 1035 */
+	{ 0x2e065030, 0x80 },	/* 1036 */
+	{ 0x2e065034, 0xdcba98 },	/* 1037 */
+	{ 0x2e065038, 0x3000000 },	/* 1038 */
+	{ 0x2e06504c, 0x2a },	/* 1043 */
+	{ 0x2e065050, 0x15 },	/* 1044 */
+	{ 0x2e065054, 0x15 },	/* 1045 */
+	{ 0x2e065058, 0x2a },	/* 1046 */
+	{ 0x2e06505c, 0x33 },	/* 1047 */
+	{ 0x2e065060, 0xc },	/* 1048 */
+	{ 0x2e065064, 0xc },	/* 1049 */
+	{ 0x2e065068, 0x33 },	/* 1050 */
+	{ 0x2e06506c, 0x543210 },	/* 1051 */
+	{ 0x2e065070, 0x3f0000 },	/* 1052 */
+	{ 0x2e065074, 0xf013f },	/* 1053 */
+	{ 0x2e065078, 0xf },	/* 1054 */
+	{ 0x2e06507c, 0x3cc },	/* 1055 */
+	{ 0x2e065080, 0x30000 },	/* 1056 */
+	{ 0x2e065084, 0x300 },	/* 1057 */
+	{ 0x2e065088, 0x300 },	/* 1058 */
+	{ 0x2e06508c, 0x300 },	/* 1059 */
+	{ 0x2e065090, 0x300 },	/* 1060 */
+	{ 0x2e065094, 0x300 },	/* 1061 */
+	{ 0x2e065098, 0x42080010 },	/* 1062 */
+	{ 0x2e06509c, 0x332 },	/* 1063 */
+	{ 0x2e0650a0, 0x2 },	/* 1064 */
+	{ 0x2e065414, 0x100 },	/* 1285 */
+	{ 0x2e065418, 0x201 },	/* 1286 */
+	{ 0x2e06542c, 0x400000 },	/* 1291 */
+	{ 0x2e065430, 0x80 },	/* 1292 */
+	{ 0x2e065434, 0xdcba98 },	/* 1293 */
+	{ 0x2e065438, 0x3000000 },	/* 1294 */
+	{ 0x2e06544c, 0x2a },	/* 1299 */
+	{ 0x2e065450, 0x15 },	/* 1300 */
+	{ 0x2e065454, 0x15 },	/* 1301 */
+	{ 0x2e065458, 0x2a },	/* 1302 */
+	{ 0x2e06545c, 0x33 },	/* 1303 */
+	{ 0x2e065460, 0xc },	/* 1304 */
+	{ 0x2e065464, 0xc },	/* 1305 */
+	{ 0x2e065468, 0x33 },	/* 1306 */
+	{ 0x2e06546c, 0x543210 },	/* 1307 */
+	{ 0x2e065470, 0x3f0000 },	/* 1308 */
+	{ 0x2e065474, 0xf013f },	/* 1309 */
+	{ 0x2e065478, 0xf },	/* 1310 */
+	{ 0x2e06547c, 0x3cc },	/* 1311 */
+	{ 0x2e065480, 0x30000 },	/* 1312 */
+	{ 0x2e065484, 0x300 },	/* 1313 */
+	{ 0x2e065488, 0x300 },	/* 1314 */
+	{ 0x2e06548c, 0x300 },	/* 1315 */
+	{ 0x2e065490, 0x300 },	/* 1316 */
+	{ 0x2e065494, 0x300 },	/* 1317 */
+	{ 0x2e065498, 0x42080010 },	/* 1318 */
+	{ 0x2e06549c, 0x332 },	/* 1319 */
+	{ 0x2e0654a0, 0x2 },	/* 1320 */
+	{ 0x2e065804, 0x100 },	/* 1537 */
+	{ 0x2e065814, 0x50000 },	/* 1541 */
+	{ 0x2e065818, 0x4000100 },	/* 1542 */
+	{ 0x2e06581c, 0x55 },	/* 1543 */
+	{ 0x2e06582c, 0xf0001 },	/* 1547 */
+	{ 0x2e065830, 0x280040 },	/* 1548 */
+	{ 0x2e065834, 0x5002 },	/* 1549 */
+	{ 0x2e065838, 0x10101 },	/* 1550 */
+	{ 0x2e065840, 0x90e0000 },	/* 1552 */
+	{ 0x2e065844, 0x101010f },	/* 1553 */
+	{ 0x2e065848, 0x10f0004 },	/* 1554 */
+	{ 0x2e065854, 0x64 },	/* 1557 */
+	{ 0x2e06585c, 0x1000000 },	/* 1559 */
+	{ 0x2e065860, 0x8040201 },	/* 1560 */
+	{ 0x2e065864, 0x2010201 },	/* 1561 */
+	{ 0x2e065868, 0xf0f0f },	/* 1562 */
+	{ 0x2e06586c, 0x241342 },	/* 1563 */
+	{ 0x2e065874, 0x1020000 },	/* 1565 */
+	{ 0x2e065878, 0x701 },	/* 1566 */
+	{ 0x2e06587c, 0x54 },	/* 1567 */
+	{ 0x2e065880, 0x4102000 },	/* 1568 */
+	{ 0x2e065884, 0x24410 },	/* 1569 */
+	{ 0x2e065888, 0x4410 },	/* 1570 */
+	{ 0x2e06588c, 0x4410 },	/* 1571 */
+	{ 0x2e065890, 0x4410 },	/* 1572 */
+	{ 0x2e065894, 0x4410 },	/* 1573 */
+	{ 0x2e065898, 0x4410 },	/* 1574 */
+	{ 0x2e06589c, 0x4410 },	/* 1575 */
+	{ 0x2e0658a0, 0x4410 },	/* 1576 */
+	{ 0x2e0658a4, 0x4410 },	/* 1577 */
+	{ 0x2e0658b0, 0x60000 },	/* 1580 */
+	{ 0x2e0658b8, 0x66 },	/* 1582 */
+	{ 0x2e0658bc, 0x10000 },	/* 1583 */
+	{ 0x2e0658c0, 0x8 },	/* 1584 */
+	{ 0x2e0658d8, 0x3000000 },	/* 1590 */
+	{ 0x2e0658e8, 0x4102006 },	/* 1594 */
+	{ 0x2e0658ec, 0x41020 },	/* 1595 */
+	{ 0x2e0658f0, 0x1c98c98 },	/* 1596 */
+	{ 0x2e0658f4, 0x3f400000 },	/* 1597 */
+	{ 0x2e0658f8, 0x3f3f1f3f },	/* 1598 */
+	{ 0x2e0658fc, 0x1f },	/* 1599 */
+	{ 0x2e06590c, 0x1 },	/* 1603 */
+	{ 0x2e06591c, 0x1 },	/* 1607 */
+	{ 0x2e065920, 0x76543210 },	/* 1608 */
+	{ 0x2e065924, 0x10198 },	/* 1609 */
+	{ 0x2e065934, 0x40700 },	/* 1613 */
+	{ 0x2e06594c, 0x2 },	/* 1619 */
+	{ 0x2e065958, 0xf3c3 },	/* 1622 */
+	{ 0x2e065964, 0x11542 },	/* 1625 */
+	{ 0x2e065968, 0x30209bf },	/* 1626 */
+	{ 0x2e06596c, 0x30000 },	/* 1627 */
+	{ 0x2e065970, 0x3000300 },	/* 1628 */
+	{ 0x2e065974, 0x3000300 },	/* 1629 */
+	{ 0x2e065978, 0x3000300 },	/* 1630 */
+	{ 0x2e06597c, 0x3000300 },	/* 1631 */
+	{ 0x2e065980, 0x300 },	/* 1632 */
+	{ 0x2e065984, 0x300 },	/* 1633 */
+	{ 0x2e065988, 0x300 },	/* 1634 */
+	{ 0x2e06598c, 0x337cc },	/* 1635 */
+	{ 0x2e065990, 0x8 },	/* 1636 */
+	{ 0x2e065994, 0x1b7 },	/* 1637 */
+	{ 0x2e06599c, 0x1b7 },	/* 1639 */
+	{ 0x2e0659a4, 0x1b700 },	/* 1641 */
+	{ 0x2e0659a8, 0x1980000 },	/* 1642 */
+	{ 0x2e0659ac, 0x1b7cc },	/* 1643 */
+	{ 0x2e0659b4, 0x1b700 },	/* 1645 */
+	{ 0x2e0659b8, 0x1980000 },	/* 1646 */
+	{ 0x2e0659bc, 0x1b700 },	/* 1647 */
+	{ 0x2e0659c0, 0x1980000 },	/* 1648 */
+	{ 0x2e0659c4, 0x1b700 },	/* 1649 */
+	{ 0x2e0659c8, 0x1980000 },	/* 1650 */
+	{ 0x2e0659cc, 0x1b700 },	/* 1651 */
+	{ 0x2e0659d0, 0x1980000 },	/* 1652 */
+	{ 0x2e0659d4, 0x20040003 },	/* 1653 */
+};
+
+/** PHY_F2 settings **/
+struct dram_cfg_param ddr_phy_f2_cfg[] = {
+};
+
+/* ddr timing config params */
+struct dram_timing_info2 dram_timing = {
+	.ctl_cfg = ddr_ctl_cfg,
+	.ctl_cfg_num = ARRAY_SIZE(ddr_ctl_cfg),
+	.pi_cfg = ddr_pi_cfg,
+	.pi_cfg_num = ARRAY_SIZE(ddr_pi_cfg),
+	.phy_f1_cfg = ddr_phy_f1_cfg,
+	.phy_f1_cfg_num = ARRAY_SIZE(ddr_phy_f1_cfg),
+	.phy_f2_cfg = ddr_phy_f2_cfg,
+	.phy_f2_cfg_num = ARRAY_SIZE(ddr_phy_f2_cfg),
+	.fsp_table = { 96, 528 },
+};
diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing_9x9.c b/board/freescale/imx8ulp_evk/lpddr4_timing_9x9.c
new file mode 100644
index 00000000000..2dc4031d989
--- /dev/null
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing_9x9.c
@@ -0,0 +1,1158 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2021 NXP
+ *
+ * Generated code from MX8ULP_DDR_tool
+ *
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+/** CTL settings **/
+struct dram_cfg_param ddr_ctl_cfg[] = {
+	{ 0x2e060000, 0xb00 },	/* 0 */
+	{ 0x2e060028, 0x258100 },	/* 10 */
+	{ 0x2e06002c, 0x17702 },	/* 11 */
+	{ 0x2e060030, 0x5 },	/* 12 */
+	{ 0x2e060034, 0x61 },	/* 13 */
+	{ 0x2e060038, 0xce3f },	/* 14 */
+	{ 0x2e06003c, 0x80e70 },	/* 15 */
+	{ 0x2e060040, 0x5 },	/* 16 */
+	{ 0x2e060044, 0x210 },	/* 17 */
+	{ 0x2e060048, 0x19c7d },	/* 18 */
+	{ 0x2e06004c, 0x101cdf },	/* 19 */
+	{ 0x2e060050, 0x5 },	/* 20 */
+	{ 0x2e060054, 0x420 },	/* 21 */
+	{ 0x2e060058, 0x1010000 },	/* 22 */
+	{ 0x2e06005c, 0x2011001 },	/* 23 */
+	{ 0x2e060060, 0x2010000 },	/* 24 */
+	{ 0x2e060064, 0x102 },	/* 25 */
+	{ 0x2e060068, 0xa },	/* 26 */
+	{ 0x2e06006c, 0x19 },	/* 27 */
+	{ 0x2e060078, 0x2020200 },	/* 30 */
+	{ 0x2e06007c, 0x160b },	/* 31 */
+	{ 0x2e060090, 0x10 },	/* 36 */
+	{ 0x2e0600a4, 0x40c040c },	/* 41 */
+	{ 0x2e0600a8, 0x8040614 },	/* 42 */
+	{ 0x2e0600ac, 0x604 },	/* 43 */
+	{ 0x2e0600b0, 0x3090003 },	/* 44 */
+	{ 0x2e0600b4, 0x40002 },	/* 45 */
+	{ 0x2e0600b8, 0xc0011 },	/* 46 */
+	{ 0x2e0600bc, 0xb0509 },	/* 47 */
+	{ 0x2e0600c0, 0x2106 },	/* 48 */
+	{ 0x2e0600c4, 0xa090017 },	/* 49 */
+	{ 0x2e0600c8, 0x8200016 },	/* 50 */
+	{ 0x2e0600cc, 0xa0a },	/* 51 */
+	{ 0x2e0600d0, 0x4000694 },	/* 52 */
+	{ 0x2e0600d4, 0xa0a0804 },	/* 53 */
+	{ 0x2e0600d8, 0x4002432 },	/* 54 */
+	{ 0x2e0600dc, 0xa0a0804 },	/* 55 */
+	{ 0x2e0600e0, 0x4004864 },	/* 56 */
+	{ 0x2e0600e4, 0x2030404 },	/* 57 */
+	{ 0x2e0600e8, 0x5040400 },	/* 58 */
+	{ 0x2e0600ec, 0x80b0a06 },	/* 59 */
+	{ 0x2e0600f0, 0x7010100 },	/* 60 */
+	{ 0x2e0600f4, 0x4150b },	/* 61 */
+	{ 0x2e0600fc, 0x1010000 },	/* 63 */
+	{ 0x2e060100, 0x1000000 },	/* 64 */
+	{ 0x2e060104, 0xe0403 },	/* 65 */
+	{ 0x2e060108, 0xb3 },	/* 66 */
+	{ 0x2e06010c, 0x4a },	/* 67 */
+	{ 0x2e060110, 0x3fd },	/* 68 */
+	{ 0x2e060114, 0x94 },	/* 69 */
+	{ 0x2e060118, 0x803 },	/* 70 */
+	{ 0x2e06011c, 0x5 },	/* 71 */
+	{ 0x2e060120, 0x70000 },	/* 72 */
+	{ 0x2e060124, 0x25000f },	/* 73 */
+	{ 0x2e060128, 0x4a0078 },	/* 74 */
+	{ 0x2e06012c, 0x4000f9 },	/* 75 */
+	{ 0x2e060130, 0x120103 },	/* 76 */
+	{ 0x2e060134, 0x50005 },	/* 77 */
+	{ 0x2e060138, 0x8070005 },	/* 78 */
+	{ 0x2e06013c, 0x505010d },	/* 79 */
+	{ 0x2e060140, 0x101030a },	/* 80 */
+	{ 0x2e060144, 0x30a0505 },	/* 81 */
+	{ 0x2e060148, 0x5050101 },	/* 82 */
+	{ 0x2e06014c, 0x1030a },	/* 83 */
+	{ 0x2e060150, 0xe000e },	/* 84 */
+	{ 0x2e060154, 0x4c004c },	/* 85 */
+	{ 0x2e060158, 0x980098 },	/* 86 */
+	{ 0x2e06015c, 0x3050505 },	/* 87 */
+	{ 0x2e060160, 0x3010403 },	/* 88 */
+	{ 0x2e060164, 0x4050505 },	/* 89 */
+	{ 0x2e060168, 0x3010403 },	/* 90 */
+	{ 0x2e06016c, 0x8050505 },	/* 91 */
+	{ 0x2e060170, 0x3010403 },	/* 92 */
+	{ 0x2e060174, 0x3010000 },	/* 93 */
+	{ 0x2e060178, 0x10000 },	/* 94 */
+	{ 0x2e060180, 0x1000000 },	/* 96 */
+	{ 0x2e060184, 0x80104002 },	/* 97 */
+	{ 0x2e060188, 0x40003 },	/* 98 */
+	{ 0x2e06018c, 0x40005 },	/* 99 */
+	{ 0x2e060190, 0x30000 },	/* 100 */
+	{ 0x2e060194, 0x50004 },	/* 101 */
+	{ 0x2e060198, 0x4 },	/* 102 */
+	{ 0x2e06019c, 0x40003 },	/* 103 */
+	{ 0x2e0601a0, 0x40005 },	/* 104 */
+	{ 0x2e0601a8, 0x2cc0 },	/* 106 */
+	{ 0x2e0601ac, 0x2cc0 },	/* 107 */
+	{ 0x2e0601b0, 0x2cc0 },	/* 108 */
+	{ 0x2e0601b4, 0x2cc0 },	/* 109 */
+	{ 0x2e0601b8, 0x2cc0 },	/* 110 */
+	{ 0x2e0601c0, 0x4e5 },	/* 112 */
+	{ 0x2e0601c4, 0xff40 },	/* 113 */
+	{ 0x2e0601c8, 0xff40 },	/* 114 */
+	{ 0x2e0601cc, 0xff40 },	/* 115 */
+	{ 0x2e0601d0, 0xff40 },	/* 116 */
+	{ 0x2e0601d4, 0xff40 },	/* 117 */
+	{ 0x2e0601dc, 0x1beb },	/* 119 */
+	{ 0x2e0601e0, 0x200c0 },	/* 120 */
+	{ 0x2e0601e4, 0x200c0 },	/* 121 */
+	{ 0x2e0601e8, 0x200c0 },	/* 122 */
+	{ 0x2e0601ec, 0x200c0 },	/* 123 */
+	{ 0x2e0601f0, 0x200c0 },	/* 124 */
+	{ 0x2e0601f8, 0x3815 },	/* 126 */
+	{ 0x2e06021c, 0x5000000 },	/* 135 */
+	{ 0x2e060220, 0x5030503 },	/* 136 */
+	{ 0x2e060224, 0x3 },	/* 137 */
+	{ 0x2e060228, 0x7010a09 },	/* 138 */
+	{ 0x2e06022c, 0xe0a09 },	/* 139 */
+	{ 0x2e060230, 0x10a0900 },	/* 140 */
+	{ 0x2e060234, 0xe0a0907 },	/* 141 */
+	{ 0x2e060238, 0xa090000 },	/* 142 */
+	{ 0x2e06023c, 0xa090701 },	/* 143 */
+	{ 0x2e060240, 0x101000e },	/* 144 */
+	{ 0x2e060244, 0x40003 },	/* 145 */
+	{ 0x2e060248, 0x7 },	/* 146 */
+	{ 0x2e060264, 0x4040100 },	/* 153 */
+	{ 0x2e060268, 0x1000000 },	/* 154 */
+	{ 0x2e06026c, 0x100000c0 },	/* 155 */
+	{ 0x2e060270, 0x100000c0 },	/* 156 */
+	{ 0x2e060274, 0x100000c0 },	/* 157 */
+	{ 0x2e06027c, 0x1600 },	/* 159 */
+	{ 0x2e060284, 0x1 },	/* 161 */
+	{ 0x2e060288, 0x2 },	/* 162 */
+	{ 0x2e06028c, 0x100e },	/* 163 */
+	{ 0x2e0602a4, 0xa0000 },	/* 169 */
+	{ 0x2e0602a8, 0xd0005 },	/* 170 */
+	{ 0x2e0602ac, 0x404 },	/* 171 */
+	{ 0x2e0602b0, 0xd },	/* 172 */
+	{ 0x2e0602b4, 0x1b0035 },	/* 173 */
+	{ 0x2e0602b8, 0x4040042 },	/* 174 */
+	{ 0x2e0602bc, 0x42 },	/* 175 */
+	{ 0x2e0602c0, 0x35006a },	/* 176 */
+	{ 0x2e0602c4, 0x4040084 },	/* 177 */
+	{ 0x2e0602c8, 0x84 },	/* 178 */
+	{ 0x2e0602d8, 0x40004 },	/* 182 */
+	{ 0x2e0602dc, 0x30000914 },	/* 183 */
+	{ 0x2e0602e0, 0x3030 },	/* 184 */
+	{ 0x2e0602e4, 0x44440000 },	/* 185 */
+	{ 0x2e0602e8, 0x19191944 },	/* 186 */
+	{ 0x2e0602ec, 0x19191908 },	/* 187 */
+	{ 0x2e0602f0, 0x4000000 },	/* 188 */
+	{ 0x2e0602f4, 0x40404 },	/* 189 */
+	{ 0x2e0602f8, 0x9140004 },	/* 190 */
+	{ 0x2e0602fc, 0x30303000 },	/* 191 */
+	{ 0x2e060304, 0x19444444 },	/* 193 */
+	{ 0x2e060308, 0x19081919 },	/* 194 */
+	{ 0x2e06030c, 0x1919 },	/* 195 */
+	{ 0x2e060310, 0x4040400 },	/* 196 */
+	{ 0x2e060314, 0x1010120 },	/* 197 */
+	{ 0x2e060318, 0x1000100 },	/* 198 */
+	{ 0x2e06031c, 0x1 },	/* 199 */
+	{ 0x2e060324, 0x1000000 },	/* 201 */
+	{ 0x2e060328, 0x1 },	/* 202 */
+	{ 0x2e060354, 0x11000000 },	/* 213 */
+	{ 0x2e060358, 0x40c1815 },	/* 214 */
+	{ 0x2e060390, 0x30000 },	/* 228 */
+	{ 0x2e060394, 0x1000200 },	/* 229 */
+	{ 0x2e060398, 0x310040 },	/* 230 */
+	{ 0x2e06039c, 0x20008 },	/* 231 */
+	{ 0x2e0603a0, 0x400100 },	/* 232 */
+	{ 0x2e0603a4, 0x80108 },	/* 233 */
+	{ 0x2e0603a8, 0x1000200 },	/* 234 */
+	{ 0x2e0603ac, 0x2100040 },	/* 235 */
+	{ 0x2e0603b0, 0x10 },	/* 236 */
+	{ 0x2e0603b4, 0xe0003 },	/* 237 */
+	{ 0x2e0603b8, 0x100001b },	/* 238 */
+	{ 0x2e0603d8, 0xffff0b00 },	/* 246 */
+	{ 0x2e0603dc, 0x1010001 },	/* 247 */
+	{ 0x2e0603e0, 0x1010101 },	/* 248 */
+	{ 0x2e0603e4, 0x10b0101 },	/* 249 */
+	{ 0x2e0603e8, 0x10000 },	/* 250 */
+	{ 0x2e0603ec, 0x4010101 },	/* 251 */
+	{ 0x2e0603f0, 0x1010000 },	/* 252 */
+	{ 0x2e0603f4, 0x4 },	/* 253 */
+	{ 0x2e0603fc, 0x3030101 },	/* 255 */
+	{ 0x2e060400, 0x103 },	/* 256 */
+	{ 0x2e0604a4, 0x2020101 },	/* 297 */
+	{ 0x2e0604a8, 0x10100 },	/* 298 */
+	{ 0x2e0604ac, 0x1000101 },	/* 299 */
+	{ 0x2e0604b0, 0x1010101 },	/* 300 */
+	{ 0x2e0604b4, 0x4030300 },	/* 301 */
+	{ 0x2e0604b8, 0x8080505 },	/* 302 */
+	{ 0x2e0604bc, 0x8020808 },	/* 303 */
+	{ 0x2e0604c0, 0x8020e00 },	/* 304 */
+	{ 0x2e0604c4, 0xa020e00 },	/* 305 */
+	{ 0x2e0604c8, 0x8000f00 },	/* 306 */
+	{ 0x2e0604cc, 0xa08 },	/* 307 */
+	{ 0x2e0604d0, 0x1010101 },	/* 308 */
+	{ 0x2e0604d4, 0x102 },	/* 309 */
+	{ 0x2e0604d8, 0x404 },	/* 310 */
+	{ 0x2e0604dc, 0x40400 },	/* 311 */
+	{ 0x2e0604e0, 0x4040000 },	/* 312 */
+	{ 0x2e0604e4, 0x4000000 },	/* 313 */
+	{ 0x2e0604e8, 0x10004 },	/* 314 */
+	{ 0x2e0604f0, 0xfffff },	/* 316 */
+	{ 0x2e0604f8, 0xfffff },	/* 318 */
+	{ 0x2e060500, 0xfffff },	/* 320 */
+	{ 0x2e060508, 0xfffff },	/* 322 */
+	{ 0x2e060510, 0xfffff },	/* 324 */
+	{ 0x2e060518, 0xfffff },	/* 326 */
+	{ 0x2e060520, 0xfffff },	/* 328 */
+	{ 0x2e060528, 0xfffff },	/* 330 */
+	{ 0x2e060530, 0xfffff },	/* 332 */
+	{ 0x2e060538, 0xfffff },	/* 334 */
+	{ 0x2e060540, 0xfffff },	/* 336 */
+	{ 0x2e060548, 0xfffff },	/* 338 */
+	{ 0x2e060550, 0xfffff },	/* 340 */
+	{ 0x2e060558, 0xfffff },	/* 342 */
+	{ 0x2e060560, 0xfffff },	/* 344 */
+	{ 0x2e060568, 0xfffff },	/* 346 */
+	{ 0x2e060570, 0xfffff },	/* 348 */
+	{ 0x2e060578, 0xfffff },	/* 350 */
+	{ 0x2e060580, 0xfffff },	/* 352 */
+	{ 0x2e060588, 0xfffff },	/* 354 */
+	{ 0x2e060590, 0xfffff },	/* 356 */
+	{ 0x2e060598, 0xfffff },	/* 358 */
+	{ 0x2e0605a0, 0xfffff },	/* 360 */
+	{ 0x2e0605a8, 0xfffff },	/* 362 */
+	{ 0x2e0605b0, 0xfffff },	/* 364 */
+	{ 0x2e0605b8, 0xfffff },	/* 366 */
+	{ 0x2e0605c0, 0xfffff },	/* 368 */
+	{ 0x2e0605c8, 0xfffff },	/* 370 */
+	{ 0x2e0605d0, 0xfffff },	/* 372 */
+	{ 0x2e0605d8, 0xfffff },	/* 374 */
+	{ 0x2e0605e0, 0xfffff },	/* 376 */
+	{ 0x2e0605e8, 0xfffff },	/* 378 */
+	{ 0x2e0605f0, 0xfffff },	/* 380 */
+	{ 0x2e0605f8, 0xfffff },	/* 382 */
+	{ 0x2e060600, 0xfffff },	/* 384 */
+	{ 0x2e060608, 0xfffff },	/* 386 */
+	{ 0x2e060610, 0xfffff },	/* 388 */
+	{ 0x2e060618, 0xfffff },	/* 390 */
+	{ 0x2e060620, 0xfffff },	/* 392 */
+	{ 0x2e060628, 0xfffff },	/* 394 */
+	{ 0x2e060630, 0xfffff },	/* 396 */
+	{ 0x2e060638, 0xfffff },	/* 398 */
+	{ 0x2e060640, 0xfffff },	/* 400 */
+	{ 0x2e060648, 0xfffff },	/* 402 */
+	{ 0x2e060650, 0xfffff },	/* 404 */
+	{ 0x2e060658, 0xfffff },	/* 406 */
+	{ 0x2e060660, 0xfffff },	/* 408 */
+	{ 0x2e060668, 0xfffff },	/* 410 */
+	{ 0x2e060670, 0xfffff },	/* 412 */
+	{ 0x2e060678, 0xfffff },	/* 414 */
+	{ 0x2e060680, 0xfffff },	/* 416 */
+	{ 0x2e060688, 0xfffff },	/* 418 */
+	{ 0x2e060690, 0xfffff },	/* 420 */
+	{ 0x2e060698, 0xfffff },	/* 422 */
+	{ 0x2e0606a0, 0xfffff },	/* 424 */
+	{ 0x2e0606a8, 0xfffff },	/* 426 */
+	{ 0x2e0606b0, 0xfffff },	/* 428 */
+	{ 0x2e0606b8, 0xfffff },	/* 430 */
+	{ 0x2e0606c0, 0xfffff },	/* 432 */
+	{ 0x2e0606c8, 0xfffff },	/* 434 */
+	{ 0x2e0606d0, 0xfffff },	/* 436 */
+	{ 0x2e0606d8, 0xfffff },	/* 438 */
+	{ 0x2e0606e0, 0xfffff },	/* 440 */
+	{ 0x2e0606e8, 0x30fffff },	/* 442 */
+	{ 0x2e0606ec, 0xffffffff },	/* 443 */
+	{ 0x2e0606f0, 0x30f0f },	/* 444 */
+	{ 0x2e0606f4, 0xffffffff },	/* 445 */
+	{ 0x2e0606f8, 0x30f0f },	/* 446 */
+	{ 0x2e0606fc, 0xffffffff },	/* 447 */
+	{ 0x2e060700, 0x30f0f },	/* 448 */
+	{ 0x2e060704, 0xffffffff },	/* 449 */
+	{ 0x2e060708, 0x30f0f },	/* 450 */
+	{ 0x2e06070c, 0xffffffff },	/* 451 */
+	{ 0x2e060710, 0x30f0f },	/* 452 */
+	{ 0x2e060714, 0xffffffff },	/* 453 */
+	{ 0x2e060718, 0x30f0f },	/* 454 */
+	{ 0x2e06071c, 0xffffffff },	/* 455 */
+	{ 0x2e060720, 0x30f0f },	/* 456 */
+	{ 0x2e060724, 0xffffffff },	/* 457 */
+	{ 0x2e060728, 0x30f0f },	/* 458 */
+	{ 0x2e06072c, 0xffffffff },	/* 459 */
+	{ 0x2e060730, 0x30f0f },	/* 460 */
+	{ 0x2e060734, 0xffffffff },	/* 461 */
+	{ 0x2e060738, 0x30f0f },	/* 462 */
+	{ 0x2e06073c, 0xffffffff },	/* 463 */
+	{ 0x2e060740, 0x30f0f },	/* 464 */
+	{ 0x2e060744, 0xffffffff },	/* 465 */
+	{ 0x2e060748, 0x30f0f },	/* 466 */
+	{ 0x2e06074c, 0xffffffff },	/* 467 */
+	{ 0x2e060750, 0x30f0f },	/* 468 */
+	{ 0x2e060754, 0xffffffff },	/* 469 */
+	{ 0x2e060758, 0x30f0f },	/* 470 */
+	{ 0x2e06075c, 0xffffffff },	/* 471 */
+	{ 0x2e060760, 0x30f0f },	/* 472 */
+	{ 0x2e060764, 0xffffffff },	/* 473 */
+	{ 0x2e060768, 0x30f0f },	/* 474 */
+	{ 0x2e06076c, 0xffffffff },	/* 475 */
+	{ 0x2e060770, 0x30f0f },	/* 476 */
+	{ 0x2e060774, 0xffffffff },	/* 477 */
+	{ 0x2e060778, 0x30f0f },	/* 478 */
+	{ 0x2e06077c, 0xffffffff },	/* 479 */
+	{ 0x2e060780, 0x30f0f },	/* 480 */
+	{ 0x2e060784, 0xffffffff },	/* 481 */
+	{ 0x2e060788, 0x30f0f },	/* 482 */
+	{ 0x2e06078c, 0xffffffff },	/* 483 */
+	{ 0x2e060790, 0x30f0f },	/* 484 */
+	{ 0x2e060794, 0xffffffff },	/* 485 */
+	{ 0x2e060798, 0x30f0f },	/* 486 */
+	{ 0x2e06079c, 0xffffffff },	/* 487 */
+	{ 0x2e0607a0, 0x30f0f },	/* 488 */
+	{ 0x2e0607a4, 0xffffffff },	/* 489 */
+	{ 0x2e0607a8, 0x30f0f },	/* 490 */
+	{ 0x2e0607ac, 0xffffffff },	/* 491 */
+	{ 0x2e0607b0, 0x30f0f },	/* 492 */
+	{ 0x2e0607b4, 0xffffffff },	/* 493 */
+	{ 0x2e0607b8, 0x30f0f },	/* 494 */
+	{ 0x2e0607bc, 0xffffffff },	/* 495 */
+	{ 0x2e0607c0, 0x30f0f },	/* 496 */
+	{ 0x2e0607c4, 0xffffffff },	/* 497 */
+	{ 0x2e0607c8, 0x30f0f },	/* 498 */
+	{ 0x2e0607cc, 0xffffffff },	/* 499 */
+	{ 0x2e0607d0, 0x30f0f },	/* 500 */
+	{ 0x2e0607d4, 0xffffffff },	/* 501 */
+	{ 0x2e0607d8, 0x30f0f },	/* 502 */
+	{ 0x2e0607dc, 0xffffffff },	/* 503 */
+	{ 0x2e0607e0, 0x30f0f },	/* 504 */
+	{ 0x2e0607e4, 0xffffffff },	/* 505 */
+	{ 0x2e0607e8, 0x30f0f },	/* 506 */
+	{ 0x2e0607ec, 0xffffffff },	/* 507 */
+	{ 0x2e0607f0, 0x30f0f },	/* 508 */
+	{ 0x2e0607f4, 0xffffffff },	/* 509 */
+	{ 0x2e0607f8, 0x30f0f },	/* 510 */
+	{ 0x2e0607fc, 0xffffffff },	/* 511 */
+	{ 0x2e060800, 0x30f0f },	/* 512 */
+	{ 0x2e060804, 0xffffffff },	/* 513 */
+	{ 0x2e060808, 0x30f0f },	/* 514 */
+	{ 0x2e06080c, 0xffffffff },	/* 515 */
+	{ 0x2e060810, 0x30f0f },	/* 516 */
+	{ 0x2e060814, 0xffffffff },	/* 517 */
+	{ 0x2e060818, 0x30f0f },	/* 518 */
+	{ 0x2e06081c, 0xffffffff },	/* 519 */
+	{ 0x2e060820, 0x30f0f },	/* 520 */
+	{ 0x2e060824, 0xffffffff },	/* 521 */
+	{ 0x2e060828, 0x30f0f },	/* 522 */
+	{ 0x2e06082c, 0xffffffff },	/* 523 */
+	{ 0x2e060830, 0x30f0f },	/* 524 */
+	{ 0x2e060834, 0xffffffff },	/* 525 */
+	{ 0x2e060838, 0x30f0f },	/* 526 */
+	{ 0x2e06083c, 0xffffffff },	/* 527 */
+	{ 0x2e060840, 0x30f0f },	/* 528 */
+	{ 0x2e060844, 0xffffffff },	/* 529 */
+	{ 0x2e060848, 0x30f0f },	/* 530 */
+	{ 0x2e06084c, 0xffffffff },	/* 531 */
+	{ 0x2e060850, 0x30f0f },	/* 532 */
+	{ 0x2e060854, 0xffffffff },	/* 533 */
+	{ 0x2e060858, 0x30f0f },	/* 534 */
+	{ 0x2e06085c, 0xffffffff },	/* 535 */
+	{ 0x2e060860, 0x30f0f },	/* 536 */
+	{ 0x2e060864, 0xffffffff },	/* 537 */
+	{ 0x2e060868, 0x30f0f },	/* 538 */
+	{ 0x2e06086c, 0xffffffff },	/* 539 */
+	{ 0x2e060870, 0x30f0f },	/* 540 */
+	{ 0x2e060874, 0xffffffff },	/* 541 */
+	{ 0x2e060878, 0x30f0f },	/* 542 */
+	{ 0x2e06087c, 0xffffffff },	/* 543 */
+	{ 0x2e060880, 0x30f0f },	/* 544 */
+	{ 0x2e060884, 0xffffffff },	/* 545 */
+	{ 0x2e060888, 0x30f0f },	/* 546 */
+	{ 0x2e06088c, 0xffffffff },	/* 547 */
+	{ 0x2e060890, 0x30f0f },	/* 548 */
+	{ 0x2e060894, 0xffffffff },	/* 549 */
+	{ 0x2e060898, 0x30f0f },	/* 550 */
+	{ 0x2e06089c, 0xffffffff },	/* 551 */
+	{ 0x2e0608a0, 0x30f0f },	/* 552 */
+	{ 0x2e0608a4, 0xffffffff },	/* 553 */
+	{ 0x2e0608a8, 0x30f0f },	/* 554 */
+	{ 0x2e0608ac, 0xffffffff },	/* 555 */
+	{ 0x2e0608b0, 0x30f0f },	/* 556 */
+	{ 0x2e0608b4, 0xffffffff },	/* 557 */
+	{ 0x2e0608b8, 0x30f0f },	/* 558 */
+	{ 0x2e0608bc, 0xffffffff },	/* 559 */
+	{ 0x2e0608c0, 0x30f0f },	/* 560 */
+	{ 0x2e0608c4, 0xffffffff },	/* 561 */
+	{ 0x2e0608c8, 0x30f0f },	/* 562 */
+	{ 0x2e0608cc, 0xffffffff },	/* 563 */
+	{ 0x2e0608d0, 0x30f0f },	/* 564 */
+	{ 0x2e0608d4, 0xffffffff },	/* 565 */
+	{ 0x2e0608d8, 0x30f0f },	/* 566 */
+	{ 0x2e0608dc, 0xffffffff },	/* 567 */
+	{ 0x2e0608e0, 0x30f0f },	/* 568 */
+	{ 0x2e0608e4, 0xffffffff },	/* 569 */
+	{ 0x2e0608e8, 0x32070f0f },	/* 570 */
+	{ 0x2e0608ec, 0x1320001 },	/* 571 */
+	{ 0x2e0608f0, 0x13200 },	/* 572 */
+	{ 0x2e0608f4, 0x132 },	/* 573 */
+	{ 0x2e0608fc, 0x1d1b0000 },	/* 575 */
+	{ 0x2e060900, 0x21 },	/* 576 */
+	{ 0x2e060904, 0xa },	/* 577 */
+	{ 0x2e060908, 0x166 },	/* 578 */
+	{ 0x2e06090c, 0x200 },	/* 579 */
+	{ 0x2e060910, 0x200 },	/* 580 */
+	{ 0x2e060914, 0x200 },	/* 581 */
+	{ 0x2e060918, 0x200 },	/* 582 */
+	{ 0x2e06091c, 0x432 },	/* 583 */
+	{ 0x2e060920, 0xdfc },	/* 584 */
+	{ 0x2e060924, 0x204 },	/* 585 */
+	{ 0x2e060928, 0x7fa },	/* 586 */
+	{ 0x2e06092c, 0x200 },	/* 587 */
+	{ 0x2e060930, 0x200 },	/* 588 */
+	{ 0x2e060934, 0x200 },	/* 589 */
+	{ 0x2e060938, 0x200 },	/* 590 */
+	{ 0x2e06093c, 0x17ee },	/* 591 */
+	{ 0x2e060940, 0x4fc4 },	/* 592 */
+	{ 0x2e060944, 0x204 },	/* 593 */
+	{ 0x2e060948, 0x1006 },	/* 594 */
+	{ 0x2e06094c, 0x200 },	/* 595 */
+	{ 0x2e060950, 0x200 },	/* 596 */
+	{ 0x2e060954, 0x200 },	/* 597 */
+	{ 0x2e060958, 0x200 },	/* 598 */
+	{ 0x2e06095c, 0x3012 },	/* 599 */
+	{ 0x2e060960, 0xa03c },	/* 600 */
+	{ 0x2e060964, 0x2020406 },	/* 601 */
+	{ 0x2e060968, 0x2030202 },	/* 602 */
+	{ 0x2e06096c, 0x1000202 },	/* 603 */
+	{ 0x2e060970, 0x3040100 },	/* 604 */
+	{ 0x2e060974, 0x10105 },	/* 605 */
+	{ 0x2e060978, 0x10101 },	/* 606 */
+	{ 0x2e06097c, 0x10101 },	/* 607 */
+	{ 0x2e060980, 0x10001 },	/* 608 */
+	{ 0x2e060984, 0x101 },	/* 609 */
+	{ 0x2e060988, 0x2000201 },	/* 610 */
+	{ 0x2e06098c, 0x2010000 },	/* 611 */
+	{ 0x2e060990, 0x6000200 },	/* 612 */
+	{ 0x2e060994, 0x3000a06 },	/* 613 */
+	{ 0x2e060998, 0x2000c06 },	/* 614 */
+};
+
+/** PI settings **/
+struct dram_cfg_param ddr_pi_cfg[] = {
+	{ 0x2e062000, 0xb00 },	/* 0 */
+	{ 0x2e062004, 0xbeedb66f },	/* 1 */
+	{ 0x2e062008, 0xabef6bd },	/* 2 */
+	{ 0x2e06200c, 0x1001387 },	/* 3 */
+	{ 0x2e062010, 0x1 },	/* 4 */
+	{ 0x2e062014, 0x10064 },	/* 5 */
+	{ 0x2e06202c, 0x201 },	/* 11 */
+	{ 0x2e062030, 0x7 },	/* 12 */
+	{ 0x2e062034, 0x50001 },	/* 13 */
+	{ 0x2e062038, 0x3030800 },	/* 14 */
+	{ 0x2e06203c, 0x1 },	/* 15 */
+	{ 0x2e062040, 0x5 },	/* 16 */
+	{ 0x2e062064, 0x1000000 },	/* 25 */
+	{ 0x2e062068, 0xa000001 },	/* 26 */
+	{ 0x2e06206c, 0x28 },	/* 27 */
+	{ 0x2e062070, 0x1 },	/* 28 */
+	{ 0x2e062074, 0x320005 },	/* 29 */
+	{ 0x2e062080, 0x10102 },	/* 32 */
+	{ 0x2e062084, 0x1 },	/* 33 */
+	{ 0x2e062088, 0xaa },	/* 34 */
+	{ 0x2e06208c, 0x55 },	/* 35 */
+	{ 0x2e062090, 0xb5 },	/* 36 */
+	{ 0x2e062094, 0x4a },	/* 37 */
+	{ 0x2e062098, 0x56 },	/* 38 */
+	{ 0x2e06209c, 0xa9 },	/* 39 */
+	{ 0x2e0620a0, 0xa9 },	/* 40 */
+	{ 0x2e0620a4, 0xb5 },	/* 41 */
+	{ 0x2e0620a8, 0x10000 },	/* 42 */
+	{ 0x2e0620ac, 0x100 },	/* 43 */
+	{ 0x2e0620b0, 0x5050000 },	/* 44 */
+	{ 0x2e0620b4, 0x13 },	/* 45 */
+	{ 0x2e0620b8, 0x7d0 },	/* 46 */
+	{ 0x2e0620bc, 0x300 },	/* 47 */
+	{ 0x2e0620c8, 0x1000000 },	/* 50 */
+	{ 0x2e0620cc, 0x10101 },	/* 51 */
+	{ 0x2e0620d8, 0x10003 },	/* 54 */
+	{ 0x2e0620dc, 0x170500 },	/* 55 */
+	{ 0x2e0620ec, 0xa140a01 },	/* 59 */
+	{ 0x2e0620f0, 0x204010a },	/* 60 */
+	{ 0x2e0620f4, 0x21010 },	/* 61 */
+	{ 0x2e0620f8, 0x40401 },	/* 62 */
+	{ 0x2e0620fc, 0x10e0005 },	/* 63 */
+	{ 0x2e062100, 0x5000001 },	/* 64 */
+	{ 0x2e062104, 0x204 },	/* 65 */
+	{ 0x2e062108, 0x34 },	/* 66 */
+	{ 0x2e062114, 0x1000000 },	/* 69 */
+	{ 0x2e062118, 0x1000000 },	/* 70 */
+	{ 0x2e06211c, 0x80200 },	/* 71 */
+	{ 0x2e062120, 0x2000200 },	/* 72 */
+	{ 0x2e062124, 0x1000100 },	/* 73 */
+	{ 0x2e062128, 0x1000000 },	/* 74 */
+	{ 0x2e06212c, 0x2000200 },	/* 75 */
+	{ 0x2e062130, 0x200 },	/* 76 */
+	{ 0x2e062164, 0x400 },	/* 89 */
+	{ 0x2e062168, 0x2010000 },	/* 90 */
+	{ 0x2e06216c, 0x80103 },	/* 91 */
+	{ 0x2e062174, 0x10008 },	/* 93 */
+	{ 0x2e06217c, 0xaa00 },	/* 95 */
+	{ 0x2e062188, 0x10000 },	/* 98 */
+	{ 0x2e0621ec, 0x8 },	/* 123 */
+	{ 0x2e062218, 0xf0000 },	/* 134 */
+	{ 0x2e06221c, 0xa },	/* 135 */
+	{ 0x2e062220, 0x19 },	/* 136 */
+	{ 0x2e062224, 0x100 },	/* 137 */
+	{ 0x2e062228, 0x100 },	/* 138 */
+	{ 0x2e062238, 0x1000000 },	/* 142 */
+	{ 0x2e06223c, 0x10003 },	/* 143 */
+	{ 0x2e062240, 0x2000101 },	/* 144 */
+	{ 0x2e062244, 0x1030001 },	/* 145 */
+	{ 0x2e062248, 0x10400 },	/* 146 */
+	{ 0x2e06224c, 0x6000105 },	/* 147 */
+	{ 0x2e062250, 0x1070001 },	/* 148 */
+	{ 0x2e062260, 0x10001 },	/* 152 */
+	{ 0x2e062274, 0x401 },	/* 157 */
+	{ 0x2e06227c, 0x10000 },	/* 159 */
+	{ 0x2e062284, 0x6010000 },	/* 161 */
+	{ 0x2e062288, 0xb },	/* 162 */
+	{ 0x2e06228c, 0x34 },	/* 163 */
+	{ 0x2e062290, 0x36 },	/* 164 */
+	{ 0x2e062294, 0x2003c },	/* 165 */
+	{ 0x2e062298, 0x2000200 },	/* 166 */
+	{ 0x2e06229c, 0xc040c04 },	/* 167 */
+	{ 0x2e0622a0, 0xe1406 },	/* 168 */
+	{ 0x2e0622a4, 0xb3 },	/* 169 */
+	{ 0x2e0622a8, 0x4a },	/* 170 */
+	{ 0x2e0622ac, 0x3fd },	/* 171 */
+	{ 0x2e0622b0, 0x94 },	/* 172 */
+	{ 0x2e0622b4, 0x4000803 },	/* 173 */
+	{ 0x2e0622b8, 0x1010404 },	/* 174 */
+	{ 0x2e0622bc, 0x1501 },	/* 175 */
+	{ 0x2e0622c0, 0x1a0018 },	/* 176 */
+	{ 0x2e0622c4, 0x1000100 },	/* 177 */
+	{ 0x2e0622c8, 0x100 },	/* 178 */
+	{ 0x2e0622d0, 0x5040303 },	/* 180 */
+	{ 0x2e0622d4, 0x1010805 },	/* 181 */
+	{ 0x2e0622d8, 0x1010101 },	/* 182 */
+	{ 0x2e0622e8, 0x2060404 },	/* 186 */
+	{ 0x2e0622ec, 0x2020402 },	/* 187 */
+	{ 0x2e0622f0, 0x3102 },	/* 188 */
+	{ 0x2e0622f4, 0x340009 },	/* 189 */
+	{ 0x2e0622f8, 0x36000c },	/* 190 */
+	{ 0x2e0622fc, 0x101000e },	/* 191 */
+	{ 0x2e062300, 0xd0101 },	/* 192 */
+	{ 0x2e062304, 0x1004201 },	/* 193 */
+	{ 0x2e062308, 0x1000084 },	/* 194 */
+	{ 0x2e06230c, 0xe000e },	/* 195 */
+	{ 0x2e062310, 0x430100 },	/* 196 */
+	{ 0x2e062314, 0x1000043 },	/* 197 */
+	{ 0x2e062318, 0x850085 },	/* 198 */
+	{ 0x2e06231c, 0x220f220f },	/* 199 */
+	{ 0x2e062320, 0x101220f },	/* 200 */
+	{ 0x2e062324, 0xa070601 },	/* 201 */
+	{ 0x2e062328, 0xa07060d },	/* 202 */
+	{ 0x2e06232c, 0xa07070d },	/* 203 */
+	{ 0x2e062330, 0xc00d },	/* 204 */
+	{ 0x2e062334, 0xc01000 },	/* 205 */
+	{ 0x2e062338, 0xc01000 },	/* 206 */
+	{ 0x2e06233c, 0x21000 },	/* 207 */
+	{ 0x2e062340, 0x11000d },	/* 208 */
+	{ 0x2e062344, 0x140042 },	/* 209 */
+	{ 0x2e062348, 0x190084 },	/* 210 */
+	{ 0x2e06234c, 0x220f0056 },	/* 211 */
+	{ 0x2e062350, 0x101 },	/* 212 */
+	{ 0x2e062354, 0x560019 },	/* 213 */
+	{ 0x2e062358, 0x101220f },	/* 214 */
+	{ 0x2e06235c, 0x1b00 },	/* 215 */
+	{ 0x2e062360, 0x220f0056 },	/* 216 */
+	{ 0x2e062364, 0x8000101 },	/* 217 */
+	{ 0x2e062368, 0x4090403 },	/* 218 */
+	{ 0x2e06236c, 0x5eb },	/* 219 */
+	{ 0x2e062370, 0x20010003 },	/* 220 */
+	{ 0x2e062374, 0x80a0a03 },	/* 221 */
+	{ 0x2e062378, 0x6090506 },	/* 222 */
+	{ 0x2e06237c, 0x2093 },	/* 223 */
+	{ 0x2e062380, 0x2001000c },	/* 224 */
+	{ 0x2e062384, 0x80a0a04 },	/* 225 */
+	{ 0x2e062388, 0xb090a0c },	/* 226 */
+	{ 0x2e06238c, 0x4126 },	/* 227 */
+	{ 0x2e062390, 0x20020017 },	/* 228 */
+	{ 0x2e062394, 0xa0a08 },	/* 229 */
+	{ 0x2e062398, 0x166 },	/* 230 */
+	{ 0x2e06239c, 0xdfc },	/* 231 */
+	{ 0x2e0623a0, 0x7fa },	/* 232 */
+	{ 0x2e0623a4, 0x4fc4 },	/* 233 */
+	{ 0x2e0623a8, 0x1006 },	/* 234 */
+	{ 0x2e0623ac, 0xa03c },	/* 235 */
+	{ 0x2e0623b0, 0x4c000e },	/* 236 */
+	{ 0x2e0623b4, 0x3030098 },	/* 237 */
+	{ 0x2e0623b8, 0x258103 },	/* 238 */
+	{ 0x2e0623bc, 0x17702 },	/* 239 */
+	{ 0x2e0623c0, 0x5 },	/* 240 */
+	{ 0x2e0623c4, 0x61 },	/* 241 */
+	{ 0x2e0623c8, 0xe },	/* 242 */
+	{ 0x2e0623cc, 0xce3f },	/* 243 */
+	{ 0x2e0623d0, 0x17702 },	/* 244 */
+	{ 0x2e0623d4, 0x5 },	/* 245 */
+	{ 0x2e0623d8, 0x210 },	/* 246 */
+	{ 0x2e0623dc, 0x4c },	/* 247 */
+	{ 0x2e0623e0, 0x19c7d },	/* 248 */
+	{ 0x2e0623e4, 0x17702 },	/* 249 */
+	{ 0x2e0623e8, 0x5 },	/* 250 */
+	{ 0x2e0623ec, 0x420 },	/* 251 */
+	{ 0x2e0623f0, 0x1000098 },	/* 252 */
+	{ 0x2e0623f4, 0x310040 },	/* 253 */
+	{ 0x2e0623f8, 0x10008 },	/* 254 */
+	{ 0x2e0623fc, 0x1080040 },	/* 255 */
+	{ 0x2e062400, 0x10008 },	/* 256 */
+	{ 0x2e062404, 0x2100040 },	/* 257 */
+	{ 0x2e062408, 0x310 },	/* 258 */
+	{ 0x2e06240c, 0x1b000e },	/* 259 */
+	{ 0x2e062410, 0x1010101 },	/* 260 */
+	{ 0x2e062414, 0x2020101 },	/* 261 */
+	{ 0x2e062418, 0x8080404 },	/* 262 */
+	{ 0x2e06241c, 0x5508 },	/* 263 */
+	{ 0x2e062420, 0x83c5a00 },	/* 264 */
+	{ 0x2e062424, 0x55 },	/* 265 */
+	{ 0x2e062428, 0x55083c5a },	/* 266 */
+	{ 0x2e06242c, 0x5a000000 },	/* 267 */
+	{ 0x2e062430, 0x55083c },	/* 268 */
+	{ 0x2e062434, 0x3c5a0000 },	/* 269 */
+	{ 0x2e062438, 0xf0e0d0c },	/* 270 */
+	{ 0x2e06243c, 0xb0a0908 },	/* 271 */
+	{ 0x2e062440, 0x7060504 },	/* 272 */
+	{ 0x2e062444, 0x3020100 },	/* 273 */
+	{ 0x2e06244c, 0x2020101 },	/* 275 */
+	{ 0x2e062450, 0x8080404 },	/* 276 */
+	{ 0x2e062454, 0x44300004 },	/* 277 */
+	{ 0x2e062458, 0x4041919 },	/* 278 */
+	{ 0x2e06245c, 0x19443000 },	/* 279 */
+	{ 0x2e062460, 0x9140419 },	/* 280 */
+	{ 0x2e062464, 0x19194430 },	/* 281 */
+	{ 0x2e062468, 0x30000404 },	/* 282 */
+	{ 0x2e06246c, 0x4191944 },	/* 283 */
+	{ 0x2e062470, 0x44300004 },	/* 284 */
+	{ 0x2e062474, 0x14041919 },	/* 285 */
+	{ 0x2e062478, 0x19443009 },	/* 286 */
+	{ 0x2e06247c, 0x40419 },	/* 287 */
+	{ 0x2e062480, 0x19194430 },	/* 288 */
+	{ 0x2e062484, 0x30000404 },	/* 289 */
+	{ 0x2e062488, 0x4191944 },	/* 290 */
+	{ 0x2e06248c, 0x44300914 },	/* 291 */
+	{ 0x2e062490, 0x44041919 },	/* 292 */
+	{ 0x2e062494, 0x19443000 },	/* 293 */
+	{ 0x2e062498, 0x40419 },	/* 294 */
+	{ 0x2e06249c, 0x19194430 },	/* 295 */
+	{ 0x2e0624a0, 0x30091404 },	/* 296 */
+	{ 0x2e0624a4, 0x4191944 },	/* 297 */
+};
+
+/** PHY_F1 settings **/
+struct dram_cfg_param ddr_phy_f1_cfg[] = {
+	{ 0x2e064000, 0x4f0 },	/* 0 */
+	{ 0x2e064008, 0x1030200 },	/* 2 */
+	{ 0x2e064014, 0x3000000 },	/* 5 */
+	{ 0x2e064018, 0x1000001 },	/* 6 */
+	{ 0x2e06401c, 0x3000400 },	/* 7 */
+	{ 0x2e064020, 0x1 },	/* 8 */
+	{ 0x2e064024, 0x1 },	/* 9 */
+	{ 0x2e064030, 0x10000 },	/* 12 */
+	{ 0x2e064038, 0xc00004 },	/* 14 */
+	{ 0x2e06403c, 0xcc0008 },	/* 15 */
+	{ 0x2e064040, 0x660601 },	/* 16 */
+	{ 0x2e064044, 0x3 },	/* 17 */
+	{ 0x2e06404c, 0x1 },	/* 19 */
+	{ 0x2e064050, 0xaaaa },	/* 20 */
+	{ 0x2e064054, 0x5555 },	/* 21 */
+	{ 0x2e064058, 0xb5b5 },	/* 22 */
+	{ 0x2e06405c, 0x4a4a },	/* 23 */
+	{ 0x2e064060, 0x5656 },	/* 24 */
+	{ 0x2e064064, 0xa9a9 },	/* 25 */
+	{ 0x2e064068, 0xb7b7 },	/* 26 */
+	{ 0x2e06406c, 0x4848 },	/* 27 */
+	{ 0x2e064078, 0x8000000 },	/* 30 */
+	{ 0x2e06407c, 0x4010008 },	/* 31 */
+	{ 0x2e064080, 0x408 },	/* 32 */
+	{ 0x2e064084, 0x3102000 },	/* 33 */
+	{ 0x2e064088, 0xc0020 },	/* 34 */
+	{ 0x2e06408c, 0x10000 },	/* 35 */
+	{ 0x2e064090, 0x55555555 },	/* 36 */
+	{ 0x2e064094, 0xaaaaaaaa },	/* 37 */
+	{ 0x2e064098, 0x55555555 },	/* 38 */
+	{ 0x2e06409c, 0xaaaaaaaa },	/* 39 */
+	{ 0x2e0640a0, 0x5555 },	/* 40 */
+	{ 0x2e0640a4, 0x1000100 },	/* 41 */
+	{ 0x2e0640a8, 0x800180 },	/* 42 */
+	{ 0x2e0640ac, 0x1 },	/* 43 */
+	{ 0x2e064100, 0x4 },	/* 64 */
+	{ 0x2e06411c, 0x41f07ff },	/* 71 */
+	{ 0x2e064120, 0x1 },	/* 72 */
+	{ 0x2e064124, 0x1cc0800 },	/* 73 */
+	{ 0x2e064128, 0x3003cc08 },	/* 74 */
+	{ 0x2e06412c, 0x2000014e },	/* 75 */
+	{ 0x2e064130, 0x7ff0200 },	/* 76 */
+	{ 0x2e064134, 0x301 },	/* 77 */
+	{ 0x2e064140, 0x30000 },	/* 80 */
+	{ 0x2e064154, 0x2000000 },	/* 85 */
+	{ 0x2e064158, 0x51515042 },	/* 86 */
+	{ 0x2e06415c, 0x31c06000 },	/* 87 */
+	{ 0x2e064160, 0x6bf000a },	/* 88 */
+	{ 0x2e064164, 0xc0c000 },	/* 89 */
+	{ 0x2e064168, 0x1000000 },	/* 90 */
+	{ 0x2e06416c, 0x10001000 },	/* 91 */
+	{ 0x2e064170, 0xc043242 },	/* 92 */
+	{ 0x2e064174, 0xf0c1201 },	/* 93 */
+	{ 0x2e064178, 0x1000140 },	/* 94 */
+	{ 0x2e06417c, 0xc000120 },	/* 95 */
+	{ 0x2e064180, 0x143 },	/* 96 */
+	{ 0x2e064184, 0x1000203 },	/* 97 */
+	{ 0x2e064188, 0x32107654 },	/* 98 */
+	{ 0x2e06418c, 0x8 },	/* 99 */
+	{ 0x2e064190, 0x2c302c3 },	/* 100 */
+	{ 0x2e064194, 0x2c302c3 },	/* 101 */
+	{ 0x2e064198, 0x2c302c3 },	/* 102 */
+	{ 0x2e06419c, 0x2c302c3 },	/* 103 */
+	{ 0x2e0641a0, 0x2c3 },	/* 104 */
+	{ 0x2e0641a4, 0x8000 },	/* 105 */
+	{ 0x2e0641a8, 0x800080 },	/* 106 */
+	{ 0x2e0641ac, 0x800080 },	/* 107 */
+	{ 0x2e0641b0, 0x800080 },	/* 108 */
+	{ 0x2e0641b4, 0x800080 },	/* 109 */
+	{ 0x2e0641b8, 0x800080 },	/* 110 */
+	{ 0x2e0641bc, 0x800080 },	/* 111 */
+	{ 0x2e0641c0, 0x800080 },	/* 112 */
+	{ 0x2e0641c4, 0x800080 },	/* 113 */
+	{ 0x2e0641c8, 0x6b0080 },	/* 114 */
+	{ 0x2e0641cc, 0x1a00001 },	/* 115 */
+	{ 0x2e0641d4, 0x10000 },	/* 117 */
+	{ 0x2e0641d8, 0x80200 },	/* 118 */
+	{ 0x2e064400, 0x4f0 },	/* 256 */
+	{ 0x2e064408, 0x1030200 },	/* 258 */
+	{ 0x2e064414, 0x3000000 },	/* 261 */
+	{ 0x2e064418, 0x1000001 },	/* 262 */
+	{ 0x2e06441c, 0x3000400 },	/* 263 */
+	{ 0x2e064420, 0x1 },	/* 264 */
+	{ 0x2e064424, 0x1 },	/* 265 */
+	{ 0x2e064430, 0x10000 },	/* 268 */
+	{ 0x2e064438, 0xc00004 },	/* 270 */
+	{ 0x2e06443c, 0xcc0008 },	/* 271 */
+	{ 0x2e064440, 0x660601 },	/* 272 */
+	{ 0x2e064444, 0x3 },	/* 273 */
+	{ 0x2e06444c, 0x1 },	/* 275 */
+	{ 0x2e064450, 0xaaaa },	/* 276 */
+	{ 0x2e064454, 0x5555 },	/* 277 */
+	{ 0x2e064458, 0xb5b5 },	/* 278 */
+	{ 0x2e06445c, 0x4a4a },	/* 279 */
+	{ 0x2e064460, 0x5656 },	/* 280 */
+	{ 0x2e064464, 0xa9a9 },	/* 281 */
+	{ 0x2e064468, 0xb7b7 },	/* 282 */
+	{ 0x2e06446c, 0x4848 },	/* 283 */
+	{ 0x2e064478, 0x8000000 },	/* 286 */
+	{ 0x2e06447c, 0x4010008 },	/* 287 */
+	{ 0x2e064480, 0x408 },	/* 288 */
+	{ 0x2e064484, 0x3102000 },	/* 289 */
+	{ 0x2e064488, 0xc0020 },	/* 290 */
+	{ 0x2e06448c, 0x10000 },	/* 291 */
+	{ 0x2e064490, 0x55555555 },	/* 292 */
+	{ 0x2e064494, 0xaaaaaaaa },	/* 293 */
+	{ 0x2e064498, 0x55555555 },	/* 294 */
+	{ 0x2e06449c, 0xaaaaaaaa },	/* 295 */
+	{ 0x2e0644a0, 0x5555 },	/* 296 */
+	{ 0x2e0644a4, 0x1000100 },	/* 297 */
+	{ 0x2e0644a8, 0x800180 },	/* 298 */
+	{ 0x2e064500, 0x4 },	/* 320 */
+	{ 0x2e06451c, 0x41f07ff },	/* 327 */
+	{ 0x2e064520, 0x1 },	/* 328 */
+	{ 0x2e064524, 0x1cc0800 },	/* 329 */
+	{ 0x2e064528, 0x3003cc08 },	/* 330 */
+	{ 0x2e06452c, 0x2000014e },	/* 331 */
+	{ 0x2e064530, 0x7ff0200 },	/* 332 */
+	{ 0x2e064534, 0x301 },	/* 333 */
+	{ 0x2e064540, 0x30000 },	/* 336 */
+	{ 0x2e064554, 0x2000000 },	/* 341 */
+	{ 0x2e064558, 0x51515042 },	/* 342 */
+	{ 0x2e06455c, 0x31c06000 },	/* 343 */
+	{ 0x2e064560, 0x6bf000a },	/* 344 */
+	{ 0x2e064564, 0xc0c000 },	/* 345 */
+	{ 0x2e064568, 0x1000000 },	/* 346 */
+	{ 0x2e06456c, 0x10001000 },	/* 347 */
+	{ 0x2e064570, 0xc043242 },	/* 348 */
+	{ 0x2e064574, 0xf0c1201 },	/* 349 */
+	{ 0x2e064578, 0x1000140 },	/* 350 */
+	{ 0x2e06457c, 0xc000120 },	/* 351 */
+	{ 0x2e064580, 0x143 },	/* 352 */
+	{ 0x2e064584, 0x1000203 },	/* 353 */
+	{ 0x2e064588, 0x45670123 },	/* 354 */
+	{ 0x2e06458c, 0x8 },	/* 355 */
+	{ 0x2e064590, 0x2c302c3 },	/* 356 */
+	{ 0x2e064594, 0x2c302c3 },	/* 357 */
+	{ 0x2e064598, 0x2c302c3 },	/* 358 */
+	{ 0x2e06459c, 0x2c302c3 },	/* 359 */
+	{ 0x2e0645a0, 0x2c3 },	/* 360 */
+	{ 0x2e0645a4, 0x8000 },	/* 361 */
+	{ 0x2e0645a8, 0x800080 },	/* 362 */
+	{ 0x2e0645ac, 0x800080 },	/* 363 */
+	{ 0x2e0645b0, 0x800080 },	/* 364 */
+	{ 0x2e0645b4, 0x800080 },	/* 365 */
+	{ 0x2e0645b8, 0x800080 },	/* 366 */
+	{ 0x2e0645bc, 0x800080 },	/* 367 */
+	{ 0x2e0645c0, 0x800080 },	/* 368 */
+	{ 0x2e0645c4, 0x800080 },	/* 369 */
+	{ 0x2e0645c8, 0x6b0080 },	/* 370 */
+	{ 0x2e0645cc, 0x1a00001 },	/* 371 */
+	{ 0x2e0645d4, 0x10000 },	/* 373 */
+	{ 0x2e0645d8, 0x80200 },	/* 374 */
+	{ 0x2e064800, 0x4f0 },	/* 512 */
+	{ 0x2e064808, 0x1030200 },	/* 514 */
+	{ 0x2e064814, 0x3000000 },	/* 517 */
+	{ 0x2e064818, 0x1000001 },	/* 518 */
+	{ 0x2e06481c, 0x3000400 },	/* 519 */
+	{ 0x2e064820, 0x1 },	/* 520 */
+	{ 0x2e064824, 0x1 },	/* 521 */
+	{ 0x2e064830, 0x10000 },	/* 524 */
+	{ 0x2e064838, 0xc00004 },	/* 526 */
+	{ 0x2e06483c, 0xcc0008 },	/* 527 */
+	{ 0x2e064840, 0x660601 },	/* 528 */
+	{ 0x2e064844, 0x3 },	/* 529 */
+	{ 0x2e06484c, 0x1 },	/* 531 */
+	{ 0x2e064850, 0xaaaa },	/* 532 */
+	{ 0x2e064854, 0x5555 },	/* 533 */
+	{ 0x2e064858, 0xb5b5 },	/* 534 */
+	{ 0x2e06485c, 0x4a4a },	/* 535 */
+	{ 0x2e064860, 0x5656 },	/* 536 */
+	{ 0x2e064864, 0xa9a9 },	/* 537 */
+	{ 0x2e064868, 0xb7b7 },	/* 538 */
+	{ 0x2e06486c, 0x4848 },	/* 539 */
+	{ 0x2e064878, 0x8000000 },	/* 542 */
+	{ 0x2e06487c, 0x4010008 },	/* 543 */
+	{ 0x2e064880, 0x408 },	/* 544 */
+	{ 0x2e064884, 0x3102000 },	/* 545 */
+	{ 0x2e064888, 0xc0020 },	/* 546 */
+	{ 0x2e06488c, 0x10000 },	/* 547 */
+	{ 0x2e064890, 0x55555555 },	/* 548 */
+	{ 0x2e064894, 0xaaaaaaaa },	/* 549 */
+	{ 0x2e064898, 0x55555555 },	/* 550 */
+	{ 0x2e06489c, 0xaaaaaaaa },	/* 551 */
+	{ 0x2e0648a0, 0x5555 },	/* 552 */
+	{ 0x2e0648a4, 0x1000100 },	/* 553 */
+	{ 0x2e0648a8, 0x800180 },	/* 554 */
+	{ 0x2e0648ac, 0x1 },	/* 555 */
+	{ 0x2e064900, 0x4 },	/* 576 */
+	{ 0x2e06491c, 0x41f07ff },	/* 583 */
+	{ 0x2e064920, 0x1 },	/* 584 */
+	{ 0x2e064924, 0x1cc0800 },	/* 585 */
+	{ 0x2e064928, 0x3003cc08 },	/* 586 */
+	{ 0x2e06492c, 0x2000014e },	/* 587 */
+	{ 0x2e064930, 0x7ff0200 },	/* 588 */
+	{ 0x2e064934, 0x301 },	/* 589 */
+	{ 0x2e064940, 0x30000 },	/* 592 */
+	{ 0x2e064954, 0x2000000 },	/* 597 */
+	{ 0x2e064958, 0x51515042 },	/* 598 */
+	{ 0x2e06495c, 0x31c06000 },	/* 599 */
+	{ 0x2e064960, 0x6bf000a },	/* 600 */
+	{ 0x2e064964, 0xc0c000 },	/* 601 */
+	{ 0x2e064968, 0x1000000 },	/* 602 */
+	{ 0x2e06496c, 0x10001000 },	/* 603 */
+	{ 0x2e064970, 0xc043242 },	/* 604 */
+	{ 0x2e064974, 0xf0c1201 },	/* 605 */
+	{ 0x2e064978, 0x1000140 },	/* 606 */
+	{ 0x2e06497c, 0xc000120 },	/* 607 */
+	{ 0x2e064980, 0x143 },	/* 608 */
+	{ 0x2e064984, 0x1000203 },	/* 609 */
+	{ 0x2e064988, 0x32107654 },	/* 610 */
+	{ 0x2e06498c, 0x8 },	/* 611 */
+	{ 0x2e064990, 0x2c302c3 },	/* 612 */
+	{ 0x2e064994, 0x2c302c3 },	/* 613 */
+	{ 0x2e064998, 0x2c302c3 },	/* 614 */
+	{ 0x2e06499c, 0x2c302c3 },	/* 615 */
+	{ 0x2e0649a0, 0x2c3 },	/* 616 */
+	{ 0x2e0649a4, 0x8000 },	/* 617 */
+	{ 0x2e0649a8, 0x800080 },	/* 618 */
+	{ 0x2e0649ac, 0x800080 },	/* 619 */
+	{ 0x2e0649b0, 0x800080 },	/* 620 */
+	{ 0x2e0649b4, 0x800080 },	/* 621 */
+	{ 0x2e0649b8, 0x800080 },	/* 622 */
+	{ 0x2e0649bc, 0x800080 },	/* 623 */
+	{ 0x2e0649c0, 0x800080 },	/* 624 */
+	{ 0x2e0649c4, 0x800080 },	/* 625 */
+	{ 0x2e0649c8, 0x6b0080 },	/* 626 */
+	{ 0x2e0649cc, 0x1a00001 },	/* 627 */
+	{ 0x2e0649d4, 0x10000 },	/* 629 */
+	{ 0x2e0649d8, 0x80200 },	/* 630 */
+	{ 0x2e064c00, 0x4f0 },	/* 768 */
+	{ 0x2e064c08, 0x1030200 },	/* 770 */
+	{ 0x2e064c14, 0x3000000 },	/* 773 */
+	{ 0x2e064c18, 0x1000001 },	/* 774 */
+	{ 0x2e064c1c, 0x3000400 },	/* 775 */
+	{ 0x2e064c20, 0x1 },	/* 776 */
+	{ 0x2e064c24, 0x1 },	/* 777 */
+	{ 0x2e064c30, 0x10000 },	/* 780 */
+	{ 0x2e064c38, 0xc00004 },	/* 782 */
+	{ 0x2e064c3c, 0xcc0008 },	/* 783 */
+	{ 0x2e064c40, 0x660601 },	/* 784 */
+	{ 0x2e064c44, 0x3 },	/* 785 */
+	{ 0x2e064c4c, 0x1 },	/* 787 */
+	{ 0x2e064c50, 0xaaaa },	/* 788 */
+	{ 0x2e064c54, 0x5555 },	/* 789 */
+	{ 0x2e064c58, 0xb5b5 },	/* 790 */
+	{ 0x2e064c5c, 0x4a4a },	/* 791 */
+	{ 0x2e064c60, 0x5656 },	/* 792 */
+	{ 0x2e064c64, 0xa9a9 },	/* 793 */
+	{ 0x2e064c68, 0xb7b7 },	/* 794 */
+	{ 0x2e064c6c, 0x4848 },	/* 795 */
+	{ 0x2e064c78, 0x8000000 },	/* 798 */
+	{ 0x2e064c7c, 0x4010008 },	/* 799 */
+	{ 0x2e064c80, 0x408 },	/* 800 */
+	{ 0x2e064c84, 0x3102000 },	/* 801 */
+	{ 0x2e064c88, 0xc0020 },	/* 802 */
+	{ 0x2e064c8c, 0x10000 },	/* 803 */
+	{ 0x2e064c90, 0x55555555 },	/* 804 */
+	{ 0x2e064c94, 0xaaaaaaaa },	/* 805 */
+	{ 0x2e064c98, 0x55555555 },	/* 806 */
+	{ 0x2e064c9c, 0xaaaaaaaa },	/* 807 */
+	{ 0x2e064ca0, 0x5555 },	/* 808 */
+	{ 0x2e064ca4, 0x1000100 },	/* 809 */
+	{ 0x2e064ca8, 0x800180 },	/* 810 */
+	{ 0x2e064d00, 0x4 },	/* 832 */
+	{ 0x2e064d1c, 0x41f07ff },	/* 839 */
+	{ 0x2e064d20, 0x1 },	/* 840 */
+	{ 0x2e064d24, 0x1cc0800 },	/* 841 */
+	{ 0x2e064d28, 0x3003cc08 },	/* 842 */
+	{ 0x2e064d2c, 0x2000014e },	/* 843 */
+	{ 0x2e064d30, 0x7ff0200 },	/* 844 */
+	{ 0x2e064d34, 0x301 },	/* 845 */
+	{ 0x2e064d40, 0x30000 },	/* 848 */
+	{ 0x2e064d54, 0x2000000 },	/* 853 */
+	{ 0x2e064d58, 0x51515042 },	/* 854 */
+	{ 0x2e064d5c, 0x31c06000 },	/* 855 */
+	{ 0x2e064d60, 0x6bf000a },	/* 856 */
+	{ 0x2e064d64, 0xc0c000 },	/* 857 */
+	{ 0x2e064d68, 0x1000000 },	/* 858 */
+	{ 0x2e064d6c, 0x10001000 },	/* 859 */
+	{ 0x2e064d70, 0xc043242 },	/* 860 */
+	{ 0x2e064d74, 0xf0c1201 },	/* 861 */
+	{ 0x2e064d78, 0x1000140 },	/* 862 */
+	{ 0x2e064d7c, 0xc000120 },	/* 863 */
+	{ 0x2e064d80, 0x143 },	/* 864 */
+	{ 0x2e064d84, 0x1000203 },	/* 865 */
+	{ 0x2e064d88, 0x45670123 },	/* 866 */
+	{ 0x2e064d8c, 0x8 },	/* 867 */
+	{ 0x2e064d90, 0x2c302c3 },	/* 868 */
+	{ 0x2e064d94, 0x2c302c3 },	/* 869 */
+	{ 0x2e064d98, 0x2c302c3 },	/* 870 */
+	{ 0x2e064d9c, 0x2c302c3 },	/* 871 */
+	{ 0x2e064da0, 0x2c3 },	/* 872 */
+	{ 0x2e064da4, 0x8000 },	/* 873 */
+	{ 0x2e064da8, 0x800080 },	/* 874 */
+	{ 0x2e064dac, 0x800080 },	/* 875 */
+	{ 0x2e064db0, 0x800080 },	/* 876 */
+	{ 0x2e064db4, 0x800080 },	/* 877 */
+	{ 0x2e064db8, 0x800080 },	/* 878 */
+	{ 0x2e064dbc, 0x800080 },	/* 879 */
+	{ 0x2e064dc0, 0x800080 },	/* 880 */
+	{ 0x2e064dc4, 0x800080 },	/* 881 */
+	{ 0x2e064dc8, 0x6b0080 },	/* 882 */
+	{ 0x2e064dcc, 0x1a00001 },	/* 883 */
+	{ 0x2e064dd4, 0x10000 },	/* 885 */
+	{ 0x2e064dd8, 0x80200 },	/* 886 */
+	{ 0x2e065014, 0x100 },	/* 1029 */
+	{ 0x2e065018, 0x201 },	/* 1030 */
+	{ 0x2e06502c, 0x400000 },	/* 1035 */
+	{ 0x2e065030, 0x80 },	/* 1036 */
+	{ 0x2e065034, 0xdcba98 },	/* 1037 */
+	{ 0x2e065038, 0x3000000 },	/* 1038 */
+	{ 0x2e06504c, 0x2a },	/* 1043 */
+	{ 0x2e065050, 0x15 },	/* 1044 */
+	{ 0x2e065054, 0x15 },	/* 1045 */
+	{ 0x2e065058, 0x2a },	/* 1046 */
+	{ 0x2e06505c, 0x33 },	/* 1047 */
+	{ 0x2e065060, 0xc },	/* 1048 */
+	{ 0x2e065064, 0xc },	/* 1049 */
+	{ 0x2e065068, 0x33 },	/* 1050 */
+	{ 0x2e06506c, 0x543210 },	/* 1051 */
+	{ 0x2e065070, 0x3f0000 },	/* 1052 */
+	{ 0x2e065074, 0xf013f },	/* 1053 */
+	{ 0x2e065078, 0xf },	/* 1054 */
+	{ 0x2e06507c, 0x3cc },	/* 1055 */
+	{ 0x2e065080, 0x30000 },	/* 1056 */
+	{ 0x2e065084, 0x300 },	/* 1057 */
+	{ 0x2e065088, 0x300 },	/* 1058 */
+	{ 0x2e06508c, 0x300 },	/* 1059 */
+	{ 0x2e065090, 0x300 },	/* 1060 */
+	{ 0x2e065094, 0x300 },	/* 1061 */
+	{ 0x2e065098, 0x42080010 },	/* 1062 */
+	{ 0x2e06509c, 0x332 },	/* 1063 */
+	{ 0x2e0650a0, 0x2 },	/* 1064 */
+	{ 0x2e065414, 0x100 },	/* 1285 */
+	{ 0x2e065418, 0x201 },	/* 1286 */
+	{ 0x2e06542c, 0x400000 },	/* 1291 */
+	{ 0x2e065430, 0x80 },	/* 1292 */
+	{ 0x2e065434, 0xdcba98 },	/* 1293 */
+	{ 0x2e065438, 0x3000000 },	/* 1294 */
+	{ 0x2e06544c, 0x2a },	/* 1299 */
+	{ 0x2e065450, 0x15 },	/* 1300 */
+	{ 0x2e065454, 0x15 },	/* 1301 */
+	{ 0x2e065458, 0x2a },	/* 1302 */
+	{ 0x2e06545c, 0x33 },	/* 1303 */
+	{ 0x2e065460, 0xc },	/* 1304 */
+	{ 0x2e065464, 0xc },	/* 1305 */
+	{ 0x2e065468, 0x33 },	/* 1306 */
+	{ 0x2e06546c, 0x543210 },	/* 1307 */
+	{ 0x2e065470, 0x3f0000 },	/* 1308 */
+	{ 0x2e065474, 0xf013f },	/* 1309 */
+	{ 0x2e065478, 0xf },	/* 1310 */
+	{ 0x2e06547c, 0x3cc },	/* 1311 */
+	{ 0x2e065480, 0x30000 },	/* 1312 */
+	{ 0x2e065484, 0x300 },	/* 1313 */
+	{ 0x2e065488, 0x300 },	/* 1314 */
+	{ 0x2e06548c, 0x300 },	/* 1315 */
+	{ 0x2e065490, 0x300 },	/* 1316 */
+	{ 0x2e065494, 0x300 },	/* 1317 */
+	{ 0x2e065498, 0x42080010 },	/* 1318 */
+	{ 0x2e06549c, 0x332 },	/* 1319 */
+	{ 0x2e0654a0, 0x2 },	/* 1320 */
+	{ 0x2e065804, 0x100 },	/* 1537 */
+	{ 0x2e065814, 0x50000 },	/* 1541 */
+	{ 0x2e065818, 0x4000100 },	/* 1542 */
+	{ 0x2e06581c, 0x55 },	/* 1543 */
+	{ 0x2e06582c, 0xf0001 },	/* 1547 */
+	{ 0x2e065830, 0x280040 },	/* 1548 */
+	{ 0x2e065834, 0x5002 },	/* 1549 */
+	{ 0x2e065838, 0x10101 },	/* 1550 */
+	{ 0x2e065840, 0x90e0000 },	/* 1552 */
+	{ 0x2e065844, 0x101010f },	/* 1553 */
+	{ 0x2e065848, 0x10f0004 },	/* 1554 */
+	{ 0x2e065854, 0x64 },	/* 1557 */
+	{ 0x2e06585c, 0x1000000 },	/* 1559 */
+	{ 0x2e065860, 0x8040201 },	/* 1560 */
+	{ 0x2e065864, 0x2010201 },	/* 1561 */
+	{ 0x2e065868, 0xf0f0f },	/* 1562 */
+	{ 0x2e06586c, 0x241342 },	/* 1563 */
+	{ 0x2e065874, 0x1020000 },	/* 1565 */
+	{ 0x2e065878, 0x10701 },	/* 1566 */
+	{ 0x2e06587c, 0x54 },	/* 1567 */
+	{ 0x2e065880, 0x4102000 },	/* 1568 */
+	{ 0x2e065884, 0x24410 },	/* 1569 */
+	{ 0x2e065888, 0x4410 },	/* 1570 */
+	{ 0x2e06588c, 0x4410 },	/* 1571 */
+	{ 0x2e065890, 0x4410 },	/* 1572 */
+	{ 0x2e065894, 0x4410 },	/* 1573 */
+	{ 0x2e065898, 0x4410 },	/* 1574 */
+	{ 0x2e06589c, 0x4410 },	/* 1575 */
+	{ 0x2e0658a0, 0x4410 },	/* 1576 */
+	{ 0x2e0658a4, 0x4410 },	/* 1577 */
+	{ 0x2e0658b0, 0x60000 },	/* 1580 */
+	{ 0x2e0658b8, 0x64 },	/* 1582 */
+	{ 0x2e0658bc, 0x10000 },	/* 1583 */
+	{ 0x2e0658c0, 0x8 },	/* 1584 */
+	{ 0x2e0658d8, 0x3000000 },	/* 1590 */
+	{ 0x2e0658e8, 0x4102006 },	/* 1594 */
+	{ 0x2e0658ec, 0x41020 },	/* 1595 */
+	{ 0x2e0658f0, 0x1c98c98 },	/* 1596 */
+	{ 0x2e0658f4, 0x3f400000 },	/* 1597 */
+	{ 0x2e0658f8, 0x3f3f1f3f },	/* 1598 */
+	{ 0x2e0658fc, 0x1f },	/* 1599 */
+	{ 0x2e06590c, 0x1 },	/* 1603 */
+	{ 0x2e06591c, 0x1 },	/* 1607 */
+	{ 0x2e065920, 0x76543210 },	/* 1608 */
+	{ 0x2e065924, 0x10198 },	/* 1609 */
+	{ 0x2e065934, 0x40700 },	/* 1613 */
+	{ 0x2e06594c, 0x2 },	/* 1619 */
+	{ 0x2e065958, 0xf3c3 },	/* 1622 */
+	{ 0x2e065964, 0x11542 },	/* 1625 */
+	{ 0x2e065968, 0x3020600 },	/* 1626 */
+	{ 0x2e06596c, 0x30000 },	/* 1627 */
+	{ 0x2e065970, 0x3000300 },	/* 1628 */
+	{ 0x2e065974, 0x3000300 },	/* 1629 */
+	{ 0x2e065978, 0x3000300 },	/* 1630 */
+	{ 0x2e06597c, 0x3000300 },	/* 1631 */
+	{ 0x2e065980, 0x300 },	/* 1632 */
+	{ 0x2e065984, 0x300 },	/* 1633 */
+	{ 0x2e065988, 0x300 },	/* 1634 */
+	{ 0x2e06598c, 0x337cc },	/* 1635 */
+	{ 0x2e065990, 0x8 },	/* 1636 */
+	{ 0x2e065994, 0x1b7 },	/* 1637 */
+	{ 0x2e06599c, 0x1b7 },	/* 1639 */
+	{ 0x2e0659a4, 0x1b700 },	/* 1641 */
+	{ 0x2e0659a8, 0x1980000 },	/* 1642 */
+	{ 0x2e0659ac, 0x1b7cc },	/* 1643 */
+	{ 0x2e0659b4, 0x1b700 },	/* 1645 */
+	{ 0x2e0659b8, 0x1980000 },	/* 1646 */
+	{ 0x2e0659bc, 0x1b700 },	/* 1647 */
+	{ 0x2e0659c0, 0x1980000 },	/* 1648 */
+	{ 0x2e0659c4, 0x1b700 },	/* 1649 */
+	{ 0x2e0659c8, 0x1980000 },	/* 1650 */
+	{ 0x2e0659cc, 0x1b700 },	/* 1651 */
+	{ 0x2e0659d0, 0x1980000 },	/* 1652 */
+	{ 0x2e0659d4, 0x20040003 },	/* 1653 */
+};
+
+/** PHY_F2 settings **/
+struct dram_cfg_param ddr_phy_f2_cfg[] = {
+	{ 0x2e064168, 0x3020000 },	/* 90 */
+	{ 0x2e064170, 0xc043e42 },	/* 92 */
+	{ 0x2e064174, 0xf0c1701 },	/* 93 */
+	{ 0x2e064180, 0x187 },	/* 96 */
+	{ 0x2e064184, 0x3200203 },	/* 97 */
+	{ 0x2e064190, 0x3070307 },	/* 100 */
+	{ 0x2e064194, 0x3070307 },	/* 101 */
+	{ 0x2e064198, 0x3070307 },	/* 102 */
+	{ 0x2e06419c, 0x3070307 },	/* 103 */
+	{ 0x2e0641a0, 0x307 },	/* 104 */
+	{ 0x2e0641c8, 0x1bd0080 },	/* 114 */
+	{ 0x2e064568, 0x3020000 },	/* 346 */
+	{ 0x2e064570, 0xc043e42 },	/* 348 */
+	{ 0x2e064574, 0xf0c1701 },	/* 349 */
+	{ 0x2e064580, 0x187 },	/* 352 */
+	{ 0x2e064584, 0x3200203 },	/* 353 */
+	{ 0x2e064590, 0x3070307 },	/* 356 */
+	{ 0x2e064594, 0x3070307 },	/* 357 */
+	{ 0x2e064598, 0x3070307 },	/* 358 */
+	{ 0x2e06459c, 0x3070307 },	/* 359 */
+	{ 0x2e0645a0, 0x307 },	/* 360 */
+	{ 0x2e0645c8, 0x1bd0080 },	/* 370 */
+	{ 0x2e064968, 0x3020000 },	/* 602 */
+	{ 0x2e064970, 0xc043e42 },	/* 604 */
+	{ 0x2e064974, 0xf0c1701 },	/* 605 */
+	{ 0x2e064980, 0x187 },	/* 608 */
+	{ 0x2e064984, 0x3200203 },	/* 609 */
+	{ 0x2e064990, 0x3070307 },	/* 612 */
+	{ 0x2e064994, 0x3070307 },	/* 613 */
+	{ 0x2e064998, 0x3070307 },	/* 614 */
+	{ 0x2e06499c, 0x3070307 },	/* 615 */
+	{ 0x2e0649a0, 0x307 },	/* 616 */
+	{ 0x2e0649c8, 0x1bd0080 },	/* 626 */
+	{ 0x2e064d68, 0x3020000 },	/* 858 */
+	{ 0x2e064d70, 0xc043e42 },	/* 860 */
+	{ 0x2e064d74, 0xf0c1701 },	/* 861 */
+	{ 0x2e064d80, 0x187 },	/* 864 */
+	{ 0x2e064d84, 0x3200203 },	/* 865 */
+	{ 0x2e064d90, 0x3070307 },	/* 868 */
+	{ 0x2e064d94, 0x3070307 },	/* 869 */
+	{ 0x2e064d98, 0x3070307 },	/* 870 */
+	{ 0x2e064d9c, 0x3070307 },	/* 871 */
+	{ 0x2e064da0, 0x307 },	/* 872 */
+	{ 0x2e064dc8, 0x1bd0080 },	/* 882 */
+	{ 0x2e06509c, 0x33e },	/* 1063 */
+	{ 0x2e06549c, 0x33e },	/* 1319 */
+	{ 0x2e065878, 0x10703 },	/* 1566 */
+	{ 0x2e065964, 0x1342 },	/* 1625 */
+};
+
+/* ddr timing config params */
+struct dram_timing_info2 dram_timing = {
+	.ctl_cfg = ddr_ctl_cfg,
+	.ctl_cfg_num = ARRAY_SIZE(ddr_ctl_cfg),
+	.pi_cfg = ddr_pi_cfg,
+	.pi_cfg_num = ARRAY_SIZE(ddr_pi_cfg),
+	.phy_f1_cfg = ddr_phy_f1_cfg,
+	.phy_f1_cfg_num = ARRAY_SIZE(ddr_phy_f1_cfg),
+	.phy_f2_cfg = ddr_phy_f2_cfg,
+	.phy_f2_cfg_num = ARRAY_SIZE(ddr_phy_f2_cfg),
+	.fsp_table = { 96, 528, 1056 },
+};
diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c
index c17d5eff7dc..40555f45bed 100644
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@@ -11,6 +11,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx8ulp-pins.h>
+#include <fsl_sec.h>
 #include <dm/uclass.h>
 #include <dm/device.h>
 #include <dm/uclass-internal.h>
@@ -19,55 +20,114 @@
 #include <asm/arch/ddr.h>
 #include <asm/arch/rdc.h>
 #include <asm/arch/upower.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/s400_api.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pcc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 void spl_dram_init(void)
 {
-	init_clk_ddr();
-	ddr_init(&dram_timing);
+	/* Reboot in dual boot setting no need to init ddr again */
+	bool ddr_enable = pcc_clock_is_enable(5, LPDDR4_PCC5_SLOT);
+	if (!ddr_enable) {
+		init_clk_ddr();
+		ddr_init(&dram_timing);
+	} else {
+		/* reinit pfd/pfddiv and lpavnic except pll4*/
+		cgc2_pll4_init(false);
+	}
 }
 
 u32 spl_boot_device(void)
 {
+#ifdef CONFIG_SPL_BOOTROM_SUPPORT
 	return BOOT_DEVICE_BOOTROM;
+#else
+	enum boot_device boot_device_spl = get_boot_device();
+
+	switch (boot_device_spl) {
+	case SD1_BOOT:
+	case MMC1_BOOT:
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD3_BOOT:
+	case MMC3_BOOT:
+		return BOOT_DEVICE_MMC2;
+	case QSPI_BOOT:
+		return BOOT_DEVICE_NOR;
+	case NAND_BOOT:
+		return BOOT_DEVICE_NAND;
+	case USB_BOOT:
+	case USB2_BOOT:
+		return BOOT_DEVICE_BOARD;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+#endif
+}
+
+#define PMIC_I2C_PAD_CTRL	(PAD_CTL_PUS_UP | PAD_CTL_SRE_SLOW | PAD_CTL_ODE)
+#define PMIC_MODE_PAD_CTRL	(PAD_CTL_PUS_UP)
+
+static iomux_cfg_t const pmic_pads[] = {
+	IMX8ULP_PAD_PTB7__PMIC0_MODE2 | MUX_PAD_CTRL(PMIC_MODE_PAD_CTRL),
+	IMX8ULP_PAD_PTB8__PMIC0_MODE1 | MUX_PAD_CTRL(PMIC_MODE_PAD_CTRL),
+	IMX8ULP_PAD_PTB9__PMIC0_MODE0 | MUX_PAD_CTRL(PMIC_MODE_PAD_CTRL),
+	IMX8ULP_PAD_PTB11__PMIC0_SCL | MUX_PAD_CTRL(PMIC_I2C_PAD_CTRL),
+	IMX8ULP_PAD_PTB10__PMIC0_SDA | MUX_PAD_CTRL(PMIC_I2C_PAD_CTRL),
+};
+
+void setup_iomux_pmic(void)
+{
+	imx8ulp_iomux_setup_multiple_pads(pmic_pads, ARRAY_SIZE(pmic_pads));
 }
 
 int power_init_board(void)
 {
-	u32 pmic_reg;
-
-	/* PMIC set bucks1-4 to PWM mode */
-	upower_pmic_i2c_read(0x10, &pmic_reg);
-	upower_pmic_i2c_read(0x14, &pmic_reg);
-	upower_pmic_i2c_read(0x21, &pmic_reg);
-	upower_pmic_i2c_read(0x2e, &pmic_reg);
-
-	upower_pmic_i2c_write(0x10, 0x3d);
-	upower_pmic_i2c_write(0x14, 0x7d);
-	upower_pmic_i2c_write(0x21, 0x7d);
-	upower_pmic_i2c_write(0x2e, 0x3d);
-
-	upower_pmic_i2c_read(0x10, &pmic_reg);
-	upower_pmic_i2c_read(0x14, &pmic_reg);
-	upower_pmic_i2c_read(0x21, &pmic_reg);
-	upower_pmic_i2c_read(0x2e, &pmic_reg);
-
-	/* Set buck3 to 1.1v OD */
-	upower_pmic_i2c_write(0x22, 0x28);
+	if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
+		/* Set buck3 to 0.9v LD */
+		upower_pmic_i2c_write(0x22, 0x18);
+	} else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
+		/* Set buck3 to 1.0v ND */
+		upower_pmic_i2c_write(0x22, 0x20);
+	} else {
+		/* Set buck3 to 1.1v OD */
+		upower_pmic_i2c_write(0x22, 0x28);
+
+	}
+
 	return 0;
 }
 
+void display_ele_fw_version(void)
+{
+	u32 fw_version, sha1, res;
+	int ret;
+
+	ret = ahab_get_fw_version(&fw_version, &sha1, &res);
+	if (ret) {
+		printf("ahab get firmware version failed %d, 0x%x\n", ret, res);
+	} else {
+		printf("ELE firmware version %u.%u.%u-%x",
+		       (fw_version & (0x00ff0000)) >> 16,
+		       (fw_version & (0x0000ff00)) >> 8,
+		       (fw_version & (0x000000ff)), sha1);
+		((fw_version & (0x80000000)) >> 31) == 1 ? puts("-dirty\n") : puts("\n");
+	}
+}
+
 void spl_board_init(void)
 {
 	struct udevice *dev;
+	u32 res;
+	int ret;
 
-	uclass_find_first_device(UCLASS_MISC, &dev);
-
-	for (; dev; uclass_find_next_device(&dev)) {
-		if (device_probe(dev))
-			continue;
-	}
+	ret = arch_cpu_init_dm();
+	if (ret)
+		return;
 
 	board_early_init_f();
 
@@ -75,18 +135,24 @@ void spl_board_init(void)
 
 	puts("Normal Boot\n");
 
-	/* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */
+	display_ele_fw_version();
+
+	/* Set iomuxc0 for pmic when m33 is not booted */
+	if (!m33_image_booted())
+		setup_iomux_pmic();
 
-	/* Load the lposc fuse for single boot to work around ROM issue,
+	/* Load the lposc fuse to work around ROM issue,
 	 *  The fuse depends on S400 to read.
 	 */
-	if (is_soc_rev(CHIP_REV_1_0) && get_boot_mode() == SINGLE_BOOT)
+	if (is_soc_rev(CHIP_REV_1_0))
 		load_lposc_fuse();
 
 	upower_init();
 
 	power_init_board();
 
+	clock_init_late();
+
 	/* DDR initialization */
 	spl_dram_init();
 
@@ -99,6 +165,31 @@ void spl_board_init(void)
 
 	/* Call it after PS16 power up */
 	set_lpav_qos();
+
+	/* Asks S400 to release CAAM for A35 core */
+	ret = ahab_release_caam(7, &res);
+	if (!ret) {
+
+		/* Only two UCLASS_MISC devicese are present on the platform. There
+		 * are MU and CAAM. Here we initialize CAAM once it's released by
+		 * S400 firmware..
+		 */
+		if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+			ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+			if (ret)
+				printf("Failed to initialize caam_jr: %d\n", ret);
+		}
+	}
+
+	/*
+	 * RNG start only available on the A1 soc revision.
+	 * Check some JTAG register for the SoC revision.
+	 */
+	if (!is_soc_rev(CHIP_REV_1_0)) {
+		ret = ahab_start_rng();
+		if (ret)
+			printf("Fail to start RNG: %d\n", ret);
+	}
 }
 
 void board_init_f(ulong dummy)
diff --git a/board/freescale/imx93_evk/Kconfig b/board/freescale/imx93_evk/Kconfig
new file mode 100644
index 00000000000..032e523198d
--- /dev/null
+++ b/board/freescale/imx93_evk/Kconfig
@@ -0,0 +1,21 @@
+if TARGET_IMX93_11X11_EVK
+
+config SYS_BOARD
+	default "imx93_evk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx93_evk"
+
+config IMX93_EVK_LPDDR4X
+	bool "Using LPDDR4X Timing and PMIC voltage"
+	default y
+	select IMX9_LPDDR4X
+	help
+	  Select the LPDDR4X timing and 0.6V VDDQ
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/imx93_evk/Makefile b/board/freescale/imx93_evk/Makefile
new file mode 100644
index 00000000000..575f8e94604
--- /dev/null
+++ b/board/freescale/imx93_evk/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2022 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx93_evk.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o
+endif
diff --git a/board/freescale/imx93_evk/imx93_evk.c b/board/freescale/imx93_evk/imx93_evk.c
new file mode 100644
index 00000000000..e8db9202009
--- /dev/null
+++ b/board/freescale/imx93_evk/imx93_evk.c
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/global_data.h>
+#include <asm/arch-imx9/ccm_regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch-imx9/imx93_pins.h>
+#include <asm/arch/clock.h>
+#include <power/pmic.h>
+#include "../common/tcpc.h"
+#include <dm/device.h>
+#include <dm/uclass.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE(6) | PAD_CTL_FSEL2)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE(6) | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	MX93_PAD_UART1_RXD__LPUART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX93_PAD_UART1_TXD__LPUART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	init_uart_clk(LPUART1_CLK_ROOT);
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_TCPC
+struct tcpc_port port1;
+struct tcpc_port port2;
+struct tcpc_port portpd;
+
+static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr)
+{
+	struct udevice *bus;
+	struct udevice *i2c_dev = NULL;
+	int ret;
+	uint8_t valb;
+
+	ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus);
+	if (ret) {
+		printf("%s: Can't find bus\n", __func__);
+		return -EINVAL;
+	}
+
+	ret = dm_i2c_probe(bus, addr, 0, &i2c_dev);
+	if (ret) {
+		printf("%s: Can't find device id=0x%x\n",
+			__func__, addr);
+		return -ENODEV;
+	}
+
+	ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_read failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+	valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */
+	ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+
+	/* Set OVP threshold to 23V */
+	valb = 0x6;
+	ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1);
+	if (ret) {
+		printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+int pd_switch_snk_enable(struct tcpc_port *port)
+{
+	if (port == &port1) {
+		debug("Setup pd switch on port 1\n");
+		return setup_pd_switch(2, 0x71);
+	} else if (port == &port2) {
+		debug("Setup pd switch on port 2\n");
+		return setup_pd_switch(2, 0x73);
+	} else
+		return -EINVAL;
+}
+
+struct tcpc_port_config portpd_config = {
+	.i2c_bus = 2, /*i2c3*/
+	.addr = 0x52,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 20000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 15000,
+	.op_snk_mv = 9000,
+};
+
+struct tcpc_port_config port1_config = {
+	.i2c_bus = 2, /*i2c3*/
+	.addr = 0x50,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 5000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 40000,
+	.op_snk_mv = 9000,
+	.switch_setup_func = &pd_switch_snk_enable,
+	.disable_pd = true,
+};
+
+struct tcpc_port_config port2_config = {
+	.i2c_bus = 2, /*i2c3*/
+	.addr = 0x51,
+	.port_type = TYPEC_PORT_UFP,
+	.max_snk_mv = 9000,
+	.max_snk_ma = 3000,
+	.max_snk_mw = 40000,
+	.op_snk_mv = 9000,
+	.switch_setup_func = &pd_switch_snk_enable,
+	.disable_pd = true,
+};
+
+static int setup_typec(void)
+{
+	int ret;
+
+	debug("tcpc_init port pd\n");
+	ret = tcpc_init(&portpd, portpd_config, NULL);
+	if (ret) {
+		printf("%s: tcpc portpd init failed, err=%d\n",
+		       __func__, ret);
+	}
+
+	debug("tcpc_init port 2\n");
+	ret = tcpc_init(&port2, port2_config, NULL);
+	if (ret) {
+		printf("%s: tcpc port2 init failed, err=%d\n",
+		       __func__, ret);
+	}
+
+	debug("tcpc_init port 1\n");
+	ret = tcpc_init(&port1, port1_config, NULL);
+	if (ret) {
+		printf("%s: tcpc port1 init failed, err=%d\n",
+		       __func__, ret);
+	}
+
+	return ret;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int ret = 0;
+	struct tcpc_port *port_ptr;
+
+	debug("board_usb_init %d, type %d\n", index, init);
+
+	if (index == 0)
+		port_ptr = &port1;
+	else
+		port_ptr = &port2;
+
+	if (init == USB_INIT_HOST)
+		tcpc_setup_dfp_mode(port_ptr);
+	else
+		tcpc_setup_ufp_mode(port_ptr);
+
+	return ret;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	int ret = 0;
+
+	debug("board_usb_cleanup %d, type %d\n", index, init);
+
+	if (init == USB_INIT_HOST) {
+		if (index == 0)
+			ret = tcpc_disable_src_vbus(&port1);
+		else
+			ret = tcpc_disable_src_vbus(&port2);
+	}
+
+	return ret;
+}
+
+int board_ehci_usb_phy_mode(struct udevice *dev)
+{
+	int ret = 0;
+	enum typec_cc_polarity pol;
+	enum typec_cc_state state;
+	struct tcpc_port *port_ptr;
+
+	debug("%s %d\n", __func__, dev_seq(dev));
+
+	if (dev_seq(dev) == 0)
+		port_ptr = &port1;
+	else
+		port_ptr = &port2;
+
+	tcpc_setup_ufp_mode(port_ptr);
+
+	ret = tcpc_get_cc_status(port_ptr, &pol, &state);
+
+	tcpc_print_log(port_ptr);
+	if (!ret) {
+		if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD)
+			return USB_INIT_HOST;
+	}
+
+	return USB_INIT_DEVICE;
+}
+#endif
+
+static int setup_fec(void)
+{
+	return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+static int setup_eqos(void)
+{
+	struct blk_ctrl_wakeupmix_regs *bctrl =
+		(struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR;
+
+	/* set INTF as RGMII, enable RGMII TXC clock */
+	clrsetbits_le32(&bctrl->eqos_gpr,
+			BCTRL_GPR_ENET_QOS_INTF_MODE_MASK,
+			BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN);
+
+	return set_clk_eqos(ENET_125MHZ);
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_USB_TCPC
+	setup_typec();
+#endif
+
+	if (CONFIG_IS_ENABLED(FEC_MXC))
+		setup_fec();
+
+	if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
+		setup_eqos();
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+	env_set("sec_boot", "yes");
+#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "11X11_EVK");
+	env_set("board_rev", "iMX93");
+#endif
+	return 0;
+}
+
diff --git a/board/freescale/imx93_evk/lpddr4x_timing.c b/board/freescale/imx93_evk/lpddr4x_timing.c
new file mode 100644
index 00000000000..59c9f274f22
--- /dev/null
+++ b/board/freescale/imx93_evk/lpddr4x_timing.c
@@ -0,0 +1,1488 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * Generated code from NXP_DDR_tool
+ *
+ * Align with uboot version:
+ * imx_v2019.04_5.4.x and above version
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ 0x4e300110, 0x44140001 },
+	{ 0x4e300000, 0x8000ff },
+	{ 0x4e300008, 0x0 },
+	{ 0x4e300080, 0x80000512 },
+	{ 0x4e300084, 0x0 },
+	{ 0x4e300114, 0x2 },
+	{ 0x4e300260, 0x0 },
+	{ 0x4e30017c, 0x0 },
+	{ 0x4e300f04, 0x80 },
+	{ 0x4e300104, 0xaaee001b },
+	{ 0x4e300108, 0x626ee273 },
+	{ 0x4e30010c, 0x5e18b },
+	{ 0x4e300100, 0x25ab321b },
+	{ 0x4e300160, 0x9002 },
+	{ 0x4e30016c, 0x35f00000 },
+	{ 0x4e300250, 0x2b },
+	{ 0x4e300254, 0x015b015b },
+	{ 0x4e30025c, 0x400 },
+	{ 0x4e300300, 0x16291314 },
+	{ 0x4e300304, 0x163110c },
+	{ 0x4e300308, 0xa200e3c },
+	{ 0x4e300170, 0x8b0b0608 },
+	{ 0x4e300124, 0x1c770000 },
+	{ 0x4e300800, 0x43930002 },
+	{ 0x4e300804, 0x1f1f1f1f },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{ 0x100a0, 0x4 },
+	{ 0x100a1, 0x5 },
+	{ 0x100a2, 0x6 },
+	{ 0x100a3, 0x7 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x1 },
+	{ 0x100a6, 0x2 },
+	{ 0x100a7, 0x3 },
+	{ 0x110a0, 0x3 },
+	{ 0x110a1, 0x2 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x1 },
+	{ 0x110a4, 0x7 },
+	{ 0x110a5, 0x6 },
+	{ 0x110a6, 0x4 },
+	{ 0x110a7, 0x5 },
+	{ 0x1005f, 0x5ff },
+	{ 0x1015f, 0x5ff },
+	{ 0x1105f, 0x5ff },
+	{ 0x1115f, 0x5ff },
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x200c5, 0x19 },
+	{ 0x2002e, 0x2 },
+	{ 0x90204, 0x0 },
+	{ 0x20024, 0x1e3 },
+	{ 0x2003a, 0x2 },
+	{ 0x2007d, 0x212 },
+	{ 0x2007c, 0x61 },
+	{ 0x20056, 0x3 },
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x10049, 0xe00 },
+	{ 0x10149, 0xe00 },
+	{ 0x11049, 0xe00 },
+	{ 0x11149, 0xe00 },
+	{ 0x43, 0x60 },
+	{ 0x1043, 0x60 },
+	{ 0x2043, 0x60 },
+	{ 0x20018, 0x1 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x2009b, 0x2 },
+	{ 0x20008, 0x3a5 },
+	{ 0x20088, 0x9 },
+	{ 0x200b2, 0x10c },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x200fa, 0x2 },
+	{ 0x20019, 0x1 },
+	{ 0x200f0, 0x0 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x1004a, 0x500 },
+	{ 0x1104a, 0x500 },
+	{ 0x20025, 0x0 },
+	{ 0x2002d, 0x0 },
+	{ 0x20021, 0x0 },
+	{ 0x2002c, 0x0 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
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+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xe94 },
+	{ 0x54004, 0x4 },
+	{ 0x54006, 0x15 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x4 },
+	{ 0x5400c, 0x1 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400f, 0x100 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x36e4 },
+	{ 0x5401a, 0x32 },
+	{ 0x5401b, 0x1146 },
+	{ 0x5401c, 0x1108 },
+	{ 0x5401e, 0x4 },
+	{ 0x5401f, 0x36e4 },
+	{ 0x54020, 0x32 },
+	{ 0x54021, 0x1146 },
+	{ 0x54022, 0x1108 },
+	{ 0x54024, 0x4 },
+	{ 0x54032, 0xe400 },
+	{ 0x54033, 0x3236 },
+	{ 0x54034, 0x4600 },
+	{ 0x54035, 0x811 },
+	{ 0x54036, 0x11 },
+	{ 0x54037, 0x400 },
+	{ 0x54038, 0xe400 },
+	{ 0x54039, 0x3236 },
+	{ 0x5403a, 0x4600 },
+	{ 0x5403b, 0x811 },
+	{ 0x5403c, 0x11 },
+	{ 0x5403d, 0x400 },
+	{ 0xd0000, 0x1 },
+};
+
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54003, 0xe94 },
+	{ 0x54004, 0x4 },
+	{ 0x54006, 0x15 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400b, 0x4 },
+	{ 0x5400c, 0x1 },
+	{ 0x5400d, 0x100 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x2080 },
+	{ 0x54012, 0x110 },
+	{ 0x54019, 0x36e4 },
+	{ 0x5401a, 0x32 },
+	{ 0x5401b, 0x1146 },
+	{ 0x5401c, 0x1108 },
+	{ 0x5401e, 0x4 },
+	{ 0x5401f, 0x36e4 },
+	{ 0x54020, 0x32 },
+	{ 0x54021, 0x1146 },
+	{ 0x54022, 0x1108 },
+	{ 0x54024, 0x4 },
+	{ 0x54032, 0xe400 },
+	{ 0x54033, 0x3236 },
+	{ 0x54034, 0x4600 },
+	{ 0x54035, 0x811 },
+	{ 0x54036, 0x11 },
+	{ 0x54037, 0x400 },
+	{ 0x54038, 0xe400 },
+	{ 0x54039, 0x3236 },
+	{ 0x5403a, 0x4600 },
+	{ 0x5403b, 0x811 },
+	{ 0x5403c, 0x11 },
+	{ 0x5403d, 0x400 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xb },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x633 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x633 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x633 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x30 },
+	{ 0x90051, 0x65a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x45a },
+	{ 0x90055, 0x9 },
+	{ 0x90056, 0x0 },
+	{ 0x90057, 0x448 },
+	{ 0x90058, 0x109 },
+	{ 0x90059, 0x40 },
+	{ 0x9005a, 0x633 },
+	{ 0x9005b, 0x179 },
+	{ 0x9005c, 0x1 },
+	{ 0x9005d, 0x618 },
+	{ 0x9005e, 0x109 },
+	{ 0x9005f, 0x40c0 },
+	{ 0x90060, 0x633 },
+	{ 0x90061, 0x149 },
+	{ 0x90062, 0x8 },
+	{ 0x90063, 0x4 },
+	{ 0x90064, 0x48 },
+	{ 0x90065, 0x4040 },
+	{ 0x90066, 0x633 },
+	{ 0x90067, 0x149 },
+	{ 0x90068, 0x0 },
+	{ 0x90069, 0x4 },
+	{ 0x9006a, 0x48 },
+	{ 0x9006b, 0x40 },
+	{ 0x9006c, 0x633 },
+	{ 0x9006d, 0x149 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x658 },
+	{ 0x90070, 0x109 },
+	{ 0x90071, 0x10 },
+	{ 0x90072, 0x4 },
+	{ 0x90073, 0x18 },
+	{ 0x90074, 0x0 },
+	{ 0x90075, 0x4 },
+	{ 0x90076, 0x78 },
+	{ 0x90077, 0x549 },
+	{ 0x90078, 0x633 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0xd49 },
+	{ 0x9007b, 0x633 },
+	{ 0x9007c, 0x159 },
+	{ 0x9007d, 0x94a },
+	{ 0x9007e, 0x633 },
+	{ 0x9007f, 0x159 },
+	{ 0x90080, 0x441 },
+	{ 0x90081, 0x633 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x42 },
+	{ 0x90084, 0x633 },
+	{ 0x90085, 0x149 },
+	{ 0x90086, 0x1 },
+	{ 0x90087, 0x633 },
+	{ 0x90088, 0x149 },
+	{ 0x90089, 0x0 },
+	{ 0x9008a, 0xe0 },
+	{ 0x9008b, 0x109 },
+	{ 0x9008c, 0xa },
+	{ 0x9008d, 0x10 },
+	{ 0x9008e, 0x109 },
+	{ 0x9008f, 0x9 },
+	{ 0x90090, 0x3c0 },
+	{ 0x90091, 0x149 },
+	{ 0x90092, 0x9 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x159 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x10 },
+	{ 0x90097, 0x109 },
+	{ 0x90098, 0x0 },
+	{ 0x90099, 0x3c0 },
+	{ 0x9009a, 0x109 },
+	{ 0x9009b, 0x18 },
+	{ 0x9009c, 0x4 },
+	{ 0x9009d, 0x48 },
+	{ 0x9009e, 0x18 },
+	{ 0x9009f, 0x4 },
+	{ 0x900a0, 0x58 },
+	{ 0x900a1, 0xb },
+	{ 0x900a2, 0x10 },
+	{ 0x900a3, 0x109 },
+	{ 0x900a4, 0x1 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x109 },
+	{ 0x900a7, 0x5 },
+	{ 0x900a8, 0x7c0 },
+	{ 0x900a9, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x625 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x625 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900aa, 0x0 },
+	{ 0x900ab, 0x790 },
+	{ 0x900ac, 0x11a },
+	{ 0x900ad, 0x8 },
+	{ 0x900ae, 0x7aa },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0x10 },
+	{ 0x900b1, 0x7b2 },
+	{ 0x900b2, 0x2a },
+	{ 0x900b3, 0x0 },
+	{ 0x900b4, 0x7c8 },
+	{ 0x900b5, 0x109 },
+	{ 0x900b6, 0x10 },
+	{ 0x900b7, 0x10 },
+	{ 0x900b8, 0x109 },
+	{ 0x900b9, 0x10 },
+	{ 0x900ba, 0x2a8 },
+	{ 0x900bb, 0x129 },
+	{ 0x900bc, 0x8 },
+	{ 0x900bd, 0x370 },
+	{ 0x900be, 0x129 },
+	{ 0x900bf, 0xa },
+	{ 0x900c0, 0x3c8 },
+	{ 0x900c1, 0x1a9 },
+	{ 0x900c2, 0xc },
+	{ 0x900c3, 0x408 },
+	{ 0x900c4, 0x199 },
+	{ 0x900c5, 0x14 },
+	{ 0x900c6, 0x790 },
+	{ 0x900c7, 0x11a },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x4 },
+	{ 0x900ca, 0x18 },
+	{ 0x900cb, 0xe },
+	{ 0x900cc, 0x408 },
+	{ 0x900cd, 0x199 },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x8568 },
+	{ 0x900d0, 0x108 },
+	{ 0x900d1, 0x18 },
+	{ 0x900d2, 0x790 },
+	{ 0x900d3, 0x16a },
+	{ 0x900d4, 0x8 },
+	{ 0x900d5, 0x1d8 },
+	{ 0x900d6, 0x169 },
+	{ 0x900d7, 0x10 },
+	{ 0x900d8, 0x8558 },
+	{ 0x900d9, 0x168 },
+	{ 0x900da, 0x1ff8 },
+	{ 0x900db, 0x85a8 },
+	{ 0x900dc, 0x1e8 },
+	{ 0x900dd, 0x50 },
+	{ 0x900de, 0x798 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x60 },
+	{ 0x900e1, 0x7a0 },
+	{ 0x900e2, 0x16a },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0x8310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0x8 },
+	{ 0x900e7, 0xa310 },
+	{ 0x900e8, 0x168 },
+	{ 0x900e9, 0xa },
+	{ 0x900ea, 0x408 },
+	{ 0x900eb, 0x169 },
+	{ 0x900ec, 0x6e },
+	{ 0x900ed, 0x0 },
+	{ 0x900ee, 0x68 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x408 },
+	{ 0x900f1, 0x169 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0x8310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x0 },
+	{ 0x900f6, 0xa310 },
+	{ 0x900f7, 0x168 },
+	{ 0x900f8, 0x1ff8 },
+	{ 0x900f9, 0x85a8 },
+	{ 0x900fa, 0x1e8 },
+	{ 0x900fb, 0x68 },
+	{ 0x900fc, 0x798 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x78 },
+	{ 0x900ff, 0x7a0 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x68 },
+	{ 0x90102, 0x790 },
+	{ 0x90103, 0x16a },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0x8b10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0x8 },
+	{ 0x90108, 0xab10 },
+	{ 0x90109, 0x168 },
+	{ 0x9010a, 0xa },
+	{ 0x9010b, 0x408 },
+	{ 0x9010c, 0x169 },
+	{ 0x9010d, 0x58 },
+	{ 0x9010e, 0x0 },
+	{ 0x9010f, 0x68 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x408 },
+	{ 0x90112, 0x169 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0x8b10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x1 },
+	{ 0x90117, 0xab10 },
+	{ 0x90118, 0x168 },
+	{ 0x90119, 0x0 },
+	{ 0x9011a, 0x1d8 },
+	{ 0x9011b, 0x169 },
+	{ 0x9011c, 0x80 },
+	{ 0x9011d, 0x790 },
+	{ 0x9011e, 0x16a },
+	{ 0x9011f, 0x18 },
+	{ 0x90120, 0x7aa },
+	{ 0x90121, 0x6a },
+	{ 0x90122, 0xa },
+	{ 0x90123, 0x0 },
+	{ 0x90124, 0x1e9 },
+	{ 0x90125, 0x8 },
+	{ 0x90126, 0x8080 },
+	{ 0x90127, 0x108 },
+	{ 0x90128, 0xf },
+	{ 0x90129, 0x408 },
+	{ 0x9012a, 0x169 },
+	{ 0x9012b, 0xc },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x68 },
+	{ 0x9012e, 0x9 },
+	{ 0x9012f, 0x0 },
+	{ 0x90130, 0x1a9 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x408 },
+	{ 0x90133, 0x169 },
+	{ 0x90134, 0x0 },
+	{ 0x90135, 0x8080 },
+	{ 0x90136, 0x108 },
+	{ 0x90137, 0x8 },
+	{ 0x90138, 0x7aa },
+	{ 0x90139, 0x6a },
+	{ 0x9013a, 0x0 },
+	{ 0x9013b, 0x8568 },
+	{ 0x9013c, 0x108 },
+	{ 0x9013d, 0xb7 },
+	{ 0x9013e, 0x790 },
+	{ 0x9013f, 0x16a },
+	{ 0x90140, 0x1f },
+	{ 0x90141, 0x0 },
+	{ 0x90142, 0x68 },
+	{ 0x90143, 0x8 },
+	{ 0x90144, 0x8558 },
+	{ 0x90145, 0x168 },
+	{ 0x90146, 0xf },
+	{ 0x90147, 0x408 },
+	{ 0x90148, 0x169 },
+	{ 0x90149, 0xd },
+	{ 0x9014a, 0x0 },
+	{ 0x9014b, 0x68 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x408 },
+	{ 0x9014e, 0x169 },
+	{ 0x9014f, 0x0 },
+	{ 0x90150, 0x8558 },
+	{ 0x90151, 0x168 },
+	{ 0x90152, 0x8 },
+	{ 0x90153, 0x3c8 },
+	{ 0x90154, 0x1a9 },
+	{ 0x90155, 0x3 },
+	{ 0x90156, 0x370 },
+	{ 0x90157, 0x129 },
+	{ 0x90158, 0x20 },
+	{ 0x90159, 0x2aa },
+	{ 0x9015a, 0x9 },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x104 },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x448 },
+	{ 0x90166, 0x109 },
+	{ 0x90167, 0xf },
+	{ 0x90168, 0x7c0 },
+	{ 0x90169, 0x109 },
+	{ 0x9016a, 0x0 },
+	{ 0x9016b, 0xe8 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0x47 },
+	{ 0x9016e, 0x630 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x8 },
+	{ 0x90171, 0x618 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x8 },
+	{ 0x90174, 0xe0 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x0 },
+	{ 0x90177, 0x7c8 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x8 },
+	{ 0x9017a, 0x8140 },
+	{ 0x9017b, 0x10c },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x478 },
+	{ 0x9017e, 0x109 },
+	{ 0x9017f, 0x0 },
+	{ 0x90180, 0x1 },
+	{ 0x90181, 0x8 },
+	{ 0x90182, 0x8 },
+	{ 0x90183, 0x4 },
+	{ 0x90184, 0x0 },
+	{ 0x90006, 0x8 },
+	{ 0x90007, 0x7c8 },
+	{ 0x90008, 0x109 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x400 },
+	{ 0x9000b, 0x106 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x2b },
+	{ 0x90026, 0x69 },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x200be, 0x0 },
+	{ 0x2000b, 0x419 },
+	{ 0x2000c, 0xe9 },
+	{ 0x2000d, 0x91c },
+	{ 0x2000e, 0x2c },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x2060 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x400f1, 0xe },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x20089, 0x1 },
+	{ 0x20088, 0x19 },
+	{ 0xc0080, 0x0 },
+	{ 0xd0000, 0x1 }
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 3733mts 1D */
+		.drate = 3733,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P0 3733mts 1D */
+		.drate = 3733,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 3733, },
+};
+
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
new file mode 100644
index 00000000000..e0a9df1e5a9
--- /dev/null
+++ b/board/freescale/imx93_evk/spl.c
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/imx93_pins.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch-mx7ulp/gpio.h>
+#include <asm/mach-imx/syscounter.h>
+#include <asm/mach-imx/s400_api.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <linux/delay.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ccm_regs.h>
+#include <asm/arch/ddr.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
+#include <asm/arch/trdc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_board_init(void)
+{
+	puts("Normal Boot\n");
+}
+
+void spl_dram_init(void)
+{
+	ddr_init(&dram_timing);
+}
+
+#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("pmic@25", &dev);
+	if (ret == -ENODEV) {
+		puts("No pca9450@25\n");
+		return 0;
+	}
+	if (ret != 0)
+		return ret;
+
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
+
+	/* 0.9v
+	 */
+	pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18);
+	pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18);
+
+	/* I2C_LT_EN*/
+	pmic_reg_write(dev, 0xa, 0x3);
+
+	/* set WDOG_B_CFG to cold reset */
+	pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	timer_init();
+
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	spl_early_init();
+
+	preloader_console_init();
+
+	ret = arch_cpu_init_dm();
+	if (ret) {
+		printf("Fail to init Sentinel API\n");
+	} else {
+		printf("SOC: 0x%x\n", gd->arch.soc_rev);
+		printf("LC: 0x%x\n", gd->arch.lifecycle);
+	}
+	power_init_board();
+
+	/* Increase ARM clock to 1.7Ghz */
+	ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM);
+	configure_intpll(ARM_PLL_CLK, 1700000000); /* 1.7Ghz */
+	ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL);
+
+	/* Init power of mix */
+	soc_power_init();
+
+	/* Setup TRDC for DDR access */
+	trdc_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Put M33 into CPUWAIT for following kick */
+	ret = m33_prepare();
+	if (!ret)
+		printf("M33 prepare ok\n");
+
+	board_init_r(NULL, 0);
+}
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index 5dd19cfcd9a..bc37c553a5b 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2018, 2021 NXP
  */
 
 #include <common.h>
@@ -22,7 +22,6 @@
 #include <env_internal.h>
 #include <fsl_mmdc.h>
 #include <netdev.h>
-#include <fsl_sec.h>
 #include <net/pfe_eth/pfe/pfe_hw.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -172,10 +171,6 @@ int board_init(void)
 	if (current_el() == 3)
 		out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
 
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
-
 #ifdef CONFIG_FSL_LS_PPA
 	ppa_init();
 #endif
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 68578e81a5d..361bd5c582a 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -28,7 +29,6 @@
 #include <fsl_mmdc.h>
 #include <spl.h>
 #include <netdev.h>
-#include <fsl_sec.h>
 #include "../common/qixis.h"
 #include "ls1012aqds_qixis.h"
 #include "ls1012aqds_pfe.h"
@@ -150,10 +150,6 @@ int board_init(void)
 	erratum_a010315();
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
-
 #ifdef CONFIG_FSL_LS_PPA
 	ppa_init();
 #endif
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index 064fb4d39fa..456609d9932 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -27,7 +28,6 @@
 #include <env_internal.h>
 #include <fsl_mmdc.h>
 #include <netdev.h>
-#include <fsl_sec.h>
 #include <net/pfe_eth/pfe/pfe_hw.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -173,10 +173,6 @@ int board_init(void)
 	erratum_a010315();
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
-
 #ifdef CONFIG_FSL_LS_PPA
 	ppa_init();
 #endif
diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c
index bfe61376042..5ab03b33404 100644
--- a/board/freescale/ls1021aiot/ls1021aiot.c
+++ b/board/freescale/ls1021aiot/ls1021aiot.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -209,10 +210,7 @@ int misc_init_r(void)
 	device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
 
 #endif
-
-#ifdef CONFIG_FSL_CAAM
-	return sec_init();
-#endif
+	return 0;
 }
 #endif
 
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 0647622cde5..2eaad9e7424 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
  */
 
 #include <common.h>
@@ -20,7 +20,6 @@
 #include <mmc.h>
 #include <fsl_csu.h>
 #include <fsl_ifc.h>
-#include <fsl_sec.h>
 #include <spl.h>
 #include <fsl_devdis.h>
 #include <fsl_validate.h>
@@ -389,9 +388,6 @@ int misc_init_r(void)
 #ifdef CONFIG_FSL_DEVICE_DISABLE
 	device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
 #endif
-#ifdef CONFIG_FSL_CAAM
-	return sec_init();
-#endif
 	return 0;
 }
 
diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c
index f31e16c419a..f016088670f 100644
--- a/board/freescale/ls1021atsn/ls1021atsn.c
+++ b/board/freescale/ls1021atsn/ls1021atsn.c
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0
-/* Copyright 2016-2019 NXP
+/* Copyright 2016-2019, 2021 NXP
  */
 #include <common.h>
 #include <clock_legacy.h>
@@ -238,10 +238,7 @@ int misc_init_r(void)
 #ifdef CONFIG_FSL_DEVICE_DISABLE
 	device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
 #endif
-
-#ifdef CONFIG_FSL_CAAM
-	return sec_init();
-#endif
+	return 0;
 }
 #endif
 
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index f0b441db638..8e874bebf75 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
+ * Copyright 2019, 2021-2022 NXP
  */
 
 #include <common.h>
@@ -26,7 +26,6 @@
 #include <netdev.h>
 #include <fsl_mdio.h>
 #include <tsec.h>
-#include <fsl_sec.h>
 #include <fsl_devdis.h>
 #include <spl.h>
 #include <linux/delay.h>
@@ -35,7 +34,7 @@
 #include <fsl_qe.h>
 #endif
 #include <fsl_validate.h>
-
+#include <dm/uclass.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -531,6 +530,15 @@ int board_init(void)
 #if defined(CONFIG_SPL_BUILD)
 void spl_board_init(void)
 {
+	if (IS_ENABLED(CONFIG_FSL_CAAM)) {
+		struct udevice *dev;
+		int ret;
+
+		ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
+		if (ret)
+			printf("Failed to initialize caam_jr: %d\n", ret);
+	}
+
 	ls102xa_smmu_stream_id_init();
 }
 #endif
@@ -555,10 +563,7 @@ int misc_init_r(void)
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 	config_board_mux();
 #endif
-
-#ifdef CONFIG_FSL_CAAM
-	return sec_init();
-#endif
+	return 0;
 }
 #endif
 
diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c
index 809dbbaa0a5..1a7806fad77 100644
--- a/board/freescale/ls1028a/ls1028a.c
+++ b/board/freescale/ls1028a/ls1028a.c
@@ -73,10 +73,6 @@ u32 get_lpuart_clk(void)
 
 int board_init(void)
 {
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
-
 #ifdef CONFIG_FSL_LS_PPA
 	ppa_init();
 #endif
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index 97080277551..98f08954a6b 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -21,7 +21,6 @@
 #include <fm_eth.h>
 #include <fsl_esdhc.h>
 #include <fsl_ifc.h>
-#include <fsl_sec.h>
 #include "cpld.h"
 #ifdef CONFIG_U_QE
 #include <fsl_qe.h>
@@ -212,10 +211,6 @@ int board_init(void)
 	out_le32(SMMU_NSCR0, val);
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
-
 #ifdef CONFIG_FSL_LS_PPA
 	ppa_init();
 #endif
diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c
index f1c08a13f7b..5a298cd311e 100644
--- a/board/freescale/ls1046afrwy/ls1046afrwy.c
+++ b/board/freescale/ls1046afrwy/ls1046afrwy.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
  */
 
 #include <common.h>
@@ -20,7 +20,6 @@
 #include <fm_eth.h>
 #include <fsl_csu.h>
 #include <fsl_esdhc.h>
-#include <fsl_sec.h>
 #include <fsl_dspi.h>
 #include "../common/i2c_mux.h"
 
@@ -135,10 +134,6 @@ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 	out_le32(SMMU_NSCR0, val);
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
-
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 	return 0;
 }
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index 8481c45a583..e5b5441e2c3 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2021 NXP
  */
 
 #include <common.h>
@@ -28,7 +28,6 @@
 #include <fsl_csu.h>
 #include <fsl_esdhc.h>
 #include <fsl_ifc.h>
-#include <fsl_sec.h>
 #include <spl.h>
 #include "../common/i2c_mux.h"
 
@@ -421,10 +420,6 @@ int board_init(void)
 	out_le32(SMMU_NSCR0, val);
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
-
 	return 0;
 }
 
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
index d0abfe8869f..25f728b9b3c 100644
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #include <common.h>
@@ -23,7 +24,6 @@
 #include <fsl_esdhc.h>
 #include <power/mc34vr500_pmic.h>
 #include "cpld.h"
-#include <fsl_sec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -85,10 +85,6 @@ int board_init(void)
 	out_le32(SMMU_NSCR0, val);
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
-
 #ifdef CONFIG_FSL_LS_PPA
 	ppa_init();
 #endif
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index 63e824c3743..5bf13dcdeb3 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -13,7 +13,6 @@
 #include <netdev.h>
 #include <fsl_ifc.h>
 #include <fsl_ddr.h>
-#include <fsl_sec.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <fdt_support.h>
@@ -820,9 +819,6 @@ int board_init(void)
 	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
 #ifdef CONFIG_FSL_LS_PPA
 	ppa_init();
 #endif
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 297629d5efb..5bdafebb6b1 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015 Freescale Semiconductor
+ * Copyright 2021 NXP
  */
 #include <common.h>
 #include <clock_legacy.h>
@@ -21,7 +22,6 @@
 #include <rtc.h>
 #include <asm/arch/soc.h>
 #include <hwconfig.h>
-#include <fsl_sec.h>
 #include <asm/arch/ppa.h>
 #include <asm/arch-fsl-layerscape/fsl_icid.h>
 #include "../common/i2c_mux.h"
@@ -222,10 +222,6 @@ int board_init(void)
 #endif
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
-
 #ifdef CONFIG_FSL_LS_PPA
 	ppa_init();
 #endif
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 1975b0f47dd..f5ebb934eb9 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2015 Freescale Semiconductor
- * Copyright 2017 NXP
+ * Copyright 2017, 2021 NXP
  */
 #include <common.h>
 #include <clock_legacy.h>
@@ -24,7 +24,6 @@
 #include <asm/arch/mmu.h>
 #include <asm/arch/soc.h>
 #include <asm/arch/ppa.h>
-#include <fsl_sec.h>
 #include <asm/arch-fsl-layerscape/fsl_icid.h>
 #include "../common/i2c_mux.h"
 
@@ -288,9 +287,6 @@ int board_init(void)
 	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
 #ifdef CONFIG_FSL_LS_PPA
 	ppa_init();
 #endif
@@ -299,9 +295,6 @@ int board_init(void)
 	/* invert AQR405 IRQ pins polarity */
 	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
 #endif
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
 
 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
 	pci_init();
diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c
index 22cc4fcf056..6bee724896d 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -14,7 +14,6 @@
 #include <errno.h>
 #include <netdev.h>
 #include <fsl_ddr.h>
-#include <fsl_sec.h>
 #include <asm/io.h>
 #include <fdt_support.h>
 #include <linux/bitops.h>
@@ -639,10 +638,6 @@ int board_init(void)
 #endif
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
-
 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
 	pci_init();
 #endif
diff --git a/board/freescale/mx6sabreauto/Kconfig b/board/freescale/mx6sabreauto/Kconfig
index 5b4faf6d5fd..0486b5e9453 100644
--- a/board/freescale/mx6sabreauto/Kconfig
+++ b/board/freescale/mx6sabreauto/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_MX6SABREAUTO
+if TARGET_MX6SABREAUTO || TARGET_MX6SABREAUTO_COMMON
 
 config SYS_BOARD
 	default "mx6sabreauto"
@@ -9,4 +9,12 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "mx6sabreauto"
 
+config SYS_TEXT_BASE
+    default 0x17800000
+
+config NOR
+	bool "Support for NOR flash"
+	help
+	  The i.MX SoC supports having a NOR flash connected to the WEIM.
+	  Need to set this for NOR_BOOT.
 endif
diff --git a/board/freescale/mx6sabreauto/imximage.cfg b/board/freescale/mx6sabreauto/imximage.cfg
new file mode 100644
index 00000000000..c8d0c7dc514
--- /dev/null
+++ b/board/freescale/mx6sabreauto/imximage.cfg
@@ -0,0 +1,156 @@
+/*
+ * Copyright (C) 2012-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of spi, sd, eimnor, nand, sata:
+ * spinor: flash_offset: 0x0400
+ * nand:   flash_offset: 0x0400
+ * sata:   flash_offset: 0x0400
+ * sd/mmc: flash_offset: 0x0400
+ * eimnor: flash_offset: 0x1000
+ */
+
+#if defined(CONFIG_NOR_BOOT)
+BOOT_FROM	nor
+#else /* others has the same flash_offset as sd */
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+#ifdef CONFIG_IMX_OPTEE
+SET_BIT 4 0x20c4070 0x3c00000
+DATA 4 0x20e0024 0x00000003
+CHECK_BITS_SET 4 0x20e0024 0x3
+#endif
+DATA 4 0x020e0798 0x000C0000
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0588 0x00000030
+DATA 4 0x020e0594 0x00000030
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e058c 0x00000000
+DATA 4 0x020e059c 0x00000030
+DATA 4 0x020e05a0 0x00000030
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e05a8 0x00000028
+DATA 4 0x020e05b0 0x00000028
+DATA 4 0x020e0524 0x00000028
+DATA 4 0x020e051c 0x00000028
+DATA 4 0x020e0518 0x00000028
+DATA 4 0x020e050c 0x00000028
+DATA 4 0x020e05b8 0x00000028
+DATA 4 0x020e05c0 0x00000028
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e0784 0x00000028
+DATA 4 0x020e0788 0x00000028
+DATA 4 0x020e0794 0x00000028
+DATA 4 0x020e079c 0x00000028
+DATA 4 0x020e07a0 0x00000028
+DATA 4 0x020e07a4 0x00000028
+DATA 4 0x020e07a8 0x00000028
+DATA 4 0x020e0748 0x00000028
+DATA 4 0x020e05ac 0x00000028
+DATA 4 0x020e05b4 0x00000028
+DATA 4 0x020e0528 0x00000028
+DATA 4 0x020e0520 0x00000028
+DATA 4 0x020e0514 0x00000028
+DATA 4 0x020e0510 0x00000028
+DATA 4 0x020e05bc 0x00000028
+DATA 4 0x020e05c4 0x00000028
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+DATA 4 0x021b480c 0x001F001F
+DATA 4 0x021b4810 0x001F001F
+DATA 4 0x021b083c 0x43260335
+DATA 4 0x021b0840 0x031A030B
+DATA 4 0x021b483c 0x4323033B
+DATA 4 0x021b4840 0x0323026F
+DATA 4 0x021b0848 0x483D4545
+DATA 4 0x021b4848 0x44433E48
+DATA 4 0x021b0850 0x41444840
+DATA 4 0x021b4850 0x4835483E
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b000c 0x8A8F7955
+DATA 4 0x021b0010 0xFF328F64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x008F1023
+DATA 4 0x021b0040 0x00000047
+DATA 4 0x021b0000 0x841A0000
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x09408030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFF000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0xFFFFF300
+DATA 4 0x020c407c 0x0F0000F3
+DATA 4 0x020c4080 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+#endif
diff --git a/board/freescale/mx6sabreauto/mx6dl.cfg b/board/freescale/mx6sabreauto/mx6dl.cfg
new file mode 100644
index 00000000000..62e295655c1
--- /dev/null
+++ b/board/freescale/mx6sabreauto/mx6dl.cfg
@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of spi, sd, eimnor, nand, sata:
+ * spinor: flash_offset: 0x0400
+ * nand:   flash_offset: 0x0400
+ * sata:   flash_offset: 0x0400
+ * sd/mmc: flash_offset: 0x0400
+ * eimnor: flash_offset: 0x1000
+ */
+
+#if defined(CONFIG_NOR_BOOT)
+BOOT_FROM       nor
+#else /* others has the same flash_offset as sd */
+BOOT_FROM       sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+#ifdef CONFIG_IMX_OPTEE
+SET_BIT 4 0x20c4070 0x3c00000
+DATA 4 0x20e0024 0x00000003
+CHECK_BITS_SET 4 0x20e0024 0x3
+#endif
+DATA 4 0x020e0774 0x000C0000
+DATA 4 0x020e0754 0x00000000
+DATA 4 0x020e04ac 0x00000030
+DATA 4 0x020e04b0 0x00000030
+DATA 4 0x020e0464 0x00000030
+DATA 4 0x020e0490 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e0494 0x00000030
+DATA 4 0x020e04a0 0x00000000
+DATA 4 0x020e04b4 0x00000030
+DATA 4 0x020e04b8 0x00000030
+DATA 4 0x020e076c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e04bc 0x00000028
+DATA 4 0x020e04c0 0x00000028
+DATA 4 0x020e04c4 0x00000028
+DATA 4 0x020e04c8 0x00000028
+DATA 4 0x020e04cc 0x00000028
+DATA 4 0x020e04d0 0x00000028
+DATA 4 0x020e04d4 0x00000028
+DATA 4 0x020e04d8 0x00000028
+DATA 4 0x020e0760 0x00020000
+DATA 4 0x020e0764 0x00000028
+DATA 4 0x020e0770 0x00000028
+DATA 4 0x020e0778 0x00000028
+DATA 4 0x020e077c 0x00000028
+DATA 4 0x020e0780 0x00000028
+DATA 4 0x020e0784 0x00000028
+DATA 4 0x020e078c 0x00000028
+DATA 4 0x020e0748 0x00000028
+DATA 4 0x020e0470 0x00000028
+DATA 4 0x020e0474 0x00000028
+DATA 4 0x020e0478 0x00000028
+DATA 4 0x020e047c 0x00000028
+DATA 4 0x020e0480 0x00000028
+DATA 4 0x020e0484 0x00000028
+DATA 4 0x020e0488 0x00000028
+DATA 4 0x020e048c 0x00000028
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+DATA 4 0x021b480c 0x001F001F
+DATA 4 0x021b4810 0x001F001F
+DATA 4 0x021b083c 0x42190217
+DATA 4 0x021b0840 0x017B017B
+DATA 4 0x021b483c 0x4176017B
+DATA 4 0x021b4840 0x015F016C
+DATA 4 0x021b0848 0x4C4C4D4C
+DATA 4 0x021b4848 0x4A4D4C48
+DATA 4 0x021b0850 0x3F3F3F40
+DATA 4 0x021b4850 0x3538382E
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x00020025
+DATA 4 0x021b0008 0x00333030
+DATA 4 0x021b000c 0x676B5313
+DATA 4 0x021b0010 0xB66E8B63
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006B1023
+DATA 4 0x021b0040 0x00000047
+DATA 4 0x021b0000 0x841A0000
+DATA 4 0x021b001c 0x04008032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x05208030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
+DATA 4 0x021b0004 0x00025565
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFF000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0xFFFFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+#endif
diff --git a/board/freescale/mx6sabreauto/mx6qp.cfg b/board/freescale/mx6sabreauto/mx6qp.cfg
new file mode 100644
index 00000000000..e339b31fbfa
--- /dev/null
+++ b/board/freescale/mx6sabreauto/mx6qp.cfg
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
+
+#include <config.h>
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of spi, sd, eimnor, nand, sata:
+ * spinor: flash_offset: 0x0400
+ * nand:   flash_offset: 0x0400
+ * sata:   flash_offset: 0x0400
+ * sd/mmc: flash_offset: 0x0400
+ * eimnor: flash_offset: 0x1000
+ */
+
+#if defined(CONFIG_NOR_BOOT)
+BOOT_FROM       nor
+#else /* others has the same flash_offset as sd */
+BOOT_FROM       sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4 0x020e0798 0x000C0000
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0588 0x00000030
+DATA 4 0x020e0594 0x00000030
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e058c 0x00000000
+DATA 4 0x020e059c 0x00000030
+DATA 4 0x020e05a0 0x00000030
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e05ac 0x00000030
+DATA 4 0x020e05b4 0x00000030
+DATA 4 0x020e0528 0x00000030
+DATA 4 0x020e0520 0x00000030
+DATA 4 0x020e0514 0x00000030
+DATA 4 0x020e0510 0x00000030
+DATA 4 0x020e05bc 0x00000030
+DATA 4 0x020e05c4 0x00000030
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001b001e
+DATA 4 0x021b0810 0x002e0029
+DATA 4 0x021b480c 0x001b002a
+DATA 4 0x021b4810 0x0019002c
+DATA 4 0x021b083c 0x43240334
+DATA 4 0x021b0840 0x0324031a
+DATA 4 0x021b483c 0x43340344
+DATA 4 0x021b4840 0x03280276
+DATA 4 0x021b0848 0x44383A3E
+DATA 4 0x021b4848 0x3C3C3846
+DATA 4 0x021b0850 0x2e303230
+DATA 4 0x021b4850 0x38283E34
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+DATA 4 0x021b08c0 0x24912249
+DATA 4 0x021b48c0 0x24914289
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0008 0x24444040
+DATA 4 0x021b000c 0x898E7955
+DATA 4 0x021b0010 0xFF320F64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x008E1023
+DATA 4 0x021b0040 0x00000047
+DATA 4 0x021b0400 0x14420000
+DATA 4 0x021b0000 0x841A0000
+DATA 4 0x021b0890 0x00400C58
+DATA 4 0x00bb0008 0x00000000
+DATA 4 0x00bb000c 0x2891E41A
+DATA 4 0x00bb0038 0x00000564
+DATA 4 0x00bb0014 0x00000040
+DATA 4 0x00bb0028 0x00000020
+DATA 4 0x00bb002c 0x00000020
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x09408030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+/* set the default clock gate to save power */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFF000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0xFFFFF300
+DATA 4, 0x020c407c, 0x0F0000F3
+DATA 4, 0x020c4080, 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+DATA 4, 0x020e0018, 0x77177717
+DATA 4, 0x020e001c, 0x77177717
+#endif
diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c
index 9155dcfbd09..fa1bc29b675 100644
--- a/board/freescale/mx6sabreauto/mx6sabreauto.c
+++ b/board/freescale/mx6sabreauto/mx6sabreauto.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  *
  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  */
@@ -35,6 +36,12 @@
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 #include "../common/pfuze.h"
+#ifdef CONFIG_FSL_FASTBOOT
+#include <fb_fsl.h>
+#ifdef CONFIG_ANDROID_RECOVERY
+#include <recovery.h>
+#endif
+#endif /*CONFIG_FSL_FASTBOOT*/
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -46,6 +53,11 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
+/*Need more drive strength for SD1 slot on base board*/
+#define USDHC1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 
@@ -60,10 +72,18 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 
+#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
+
 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |          \
 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
 
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
 #define I2C_PMIC	1
 
 int dram_init(void)
@@ -78,30 +98,17 @@ static iomux_v3_cfg_t const uart4_pads[] = {
 	IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 };
 
-
+#ifdef CONFIG_SYS_I2C_LEGACY
 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
-static struct i2c_pads_info mx6q_i2c_pad_info1 = {
+static struct i2c_pads_info i2c_pad_info1 = {
 	.scl = {
-		.i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC,
-		.gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC,
+		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
 		.gp = IMX_GPIO_NR(2, 30)
 	},
 	.sda = {
-		.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
-		.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
-		.gp = IMX_GPIO_NR(4, 13)
-	}
-};
-
-static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC,
-		.gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC,
-		.gp = IMX_GPIO_NR(2, 30)
-	},
-	.sda = {
-		.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
-		.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
+		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 		.gp = IMX_GPIO_NR(4, 13)
 	}
 };
@@ -111,36 +118,20 @@ static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
  * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
  * Compass Sensor, Accelerometer, Res Touch
  */
-static struct i2c_pads_info mx6q_i2c_pad_info2 = {
-	.scl = {
-		.i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
-		.gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
-		.gp = IMX_GPIO_NR(1, 3)
-	},
-	.sda = {
-		.i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC,
-		.gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC,
-		.gp = IMX_GPIO_NR(3, 18)
-	}
-};
-
-static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
+static struct i2c_pads_info i2c_pad_info2 = {
 	.scl = {
-		.i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
-		.gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
+		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
 		.gp = IMX_GPIO_NR(1, 3)
 	},
 	.sda = {
-		.i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC,
-		.gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC,
+		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+		.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
 		.gp = IMX_GPIO_NR(3, 18)
 	}
 };
 #endif
-
-static iomux_v3_cfg_t const i2c3_pads[] = {
-	IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04	| MUX_PAD_CTRL(NO_PAD_CTRL)),
-};
+#endif
 
 static iomux_v3_cfg_t const port_exp[] = {
 	IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15	| MUX_PAD_CTRL(NO_PAD_CTRL)),
@@ -236,15 +227,48 @@ static void eim_clk_setup(void)
 
 static void setup_iomux_eimnor(void)
 {
+	int ret;
+	struct gpio_desc desc;
+
 	SETUP_IOMUX_PADS(eimnor_pads);
 
-	gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+	ret = dm_gpio_lookup_name("GPIO5_4", &desc);
+	if (ret) {
+		printf("%s lookup GPIO5_4 failed ret = %d\n", __func__, ret);
+		return;
+	}
+	ret = dm_gpio_request(&desc, "steer ctrl");
+	if (ret) {
+		printf("%s request steer logic failed ret = %d\n", __func__, ret);
+		return;
+	}
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW);
 
 	eimnor_cs_setup();
 }
 #endif
 
 
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart4_pads);
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	/*To avoid pin conflict with NAND, set usdhc1 to 4 pins*/
+	IOMUX_PADS(PAD_SD1_CLK__SD1_CLK	| MUX_PAD_CTRL(USDHC1_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CMD__SD1_CMD	| MUX_PAD_CTRL(USDHC1_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0	| MUX_PAD_CTRL(USDHC1_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1	| MUX_PAD_CTRL(USDHC1_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2	| MUX_PAD_CTRL(USDHC1_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3	| MUX_PAD_CTRL(USDHC1_PAD_CTRL)),
+
+	/*CD pin*/
+	IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
 static iomux_v3_cfg_t const usdhc3_pads[] = {
 	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
@@ -260,30 +284,71 @@ static iomux_v3_cfg_t const usdhc3_pads[] = {
 	IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15	| MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
-static void setup_iomux_uart(void)
-{
-	SETUP_IOMUX_PADS(uart4_pads);
-}
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 1)
+#define USDHC3_CD_GPIO	IMX_GPIO_NR(6, 15)
 
-#ifdef CONFIG_FSL_ESDHC_IMX
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 4},
 	{USDHC3_BASE_ADDR},
 };
 
 int board_mmc_getcd(struct mmc *mmc)
 {
-	gpio_direction_input(IMX_GPIO_NR(6, 15));
-	return !gpio_get_value(IMX_GPIO_NR(6, 15));
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		gpio_direction_input(USDHC1_CD_GPIO);
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		gpio_direction_input(USDHC3_CD_GPIO);
+		ret = !gpio_get_value(USDHC3_CD_GPIO);
+		break;
+	}
+
+	return ret;
 }
 
 int board_mmc_init(struct bd_info *bis)
 {
-	SETUP_IOMUX_PADS(usdhc3_pads);
+	int i;
 
-	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+	/*
+	* According to the board_mmc_init() the following map is done:
+	* (U-boot device node)    (Physical Port)
+	* mmc0				USDHC1
+	* mmc1				USDHC3
+	*/
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc1_pads);
+			gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
+			gpio_direction_input(USDHC1_CD_GPIO);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		case 1:
+			SETUP_IOMUX_PADS(usdhc3_pads);
+			gpio_request(USDHC3_CD_GPIO, "usdhc3 cd");
+			gpio_direction_input(USDHC3_CD_GPIO);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return 0;
+			}
+
+		if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+	}
+
+	return 0;
 }
 #endif
+#endif
 
 #ifdef CONFIG_NAND_MXS
 static iomux_v3_cfg_t gpmi_pads[] = {
@@ -321,6 +386,24 @@ static void setup_gpmi_nand(void)
 }
 #endif
 
+static void setup_fec(void)
+{
+	int ret;
+
+	if (is_mx6dqp()) {
+		/*
+		 * select ENET MAC0 TX clock from PLL
+		 */
+		imx_iomux_set_gpr_register(5, 9, 1, 1);
+	} else {
+		imx_iomux_set_gpr_register(1, 21, 1, 1);
+	}
+
+	ret = enable_fec_anatop_clock(0, ENET_125MHZ);
+	if (ret)
+		printf("Error fec anatop clock settings!\n");
+}
+
 #ifdef CONFIG_REVISION_TAG
 u32 get_board_rev(void)
 {
@@ -403,7 +486,7 @@ struct display_info_t const displays[] = {{
 	.bus	= -1,
 	.addr	= 0,
 	.pixfmt	= IPU_PIX_FMT_RGB24,
-	.detect	= detect_hdmi,
+	.detect	= NULL,
 	.enable	= do_enable_hdmi,
 	.mode	= {
 		.name           = "HDMI",
@@ -428,8 +511,22 @@ iomux_v3_cfg_t const backlight_pads[] = {
 
 static void setup_iomux_backlight(void)
 {
-	gpio_request(IMX_GPIO_NR(2, 9), "backlight");
-	gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
+	int ret;
+	struct gpio_desc desc;
+
+	ret = dm_gpio_lookup_name("GPIO2_9", &desc);
+	if (ret) {
+		printf("%s lookup GPIO2_9 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "backlight");
+	if (ret) {
+		printf("%s request backlight failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 	SETUP_IOMUX_PADS(backlight_pads);
 }
 
@@ -497,6 +594,37 @@ int overwrite_console(void)
 	return 1;
 }
 
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t const ecspi1_pads[] = {
+	IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	/* Steer logic */
+	IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+void setup_spinor(void)
+{
+	int ret;
+	struct gpio_desc desc;
+
+	SETUP_IOMUX_PADS(ecspi1_pads);
+
+	ret = dm_gpio_lookup_name("GPIO5_4", &desc);
+	if (ret) {
+		printf("%s lookup GPIO5_4 failed ret = %d\n", __func__, ret);
+		return;
+	}
+	ret = dm_gpio_request(&desc, "steer ctrl");
+	if (ret) {
+		printf("%s request steer logic failed ret = %d\n", __func__, ret);
+		return;
+	}
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW);
+}
+#endif
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -513,64 +641,262 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
+	int ret;
+	struct gpio_desc desc;
+
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_SYS_I2C_LEGACY
 	/* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
-	if (is_mx6dq() || is_mx6dqp())
-		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
-	else
-		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
-	/* I2C 3 Steer */
-	gpio_request(IMX_GPIO_NR(5, 4), "steer logic");
-	gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
-	SETUP_IOMUX_PADS(i2c3_pads);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 #ifndef CONFIG_SYS_FLASH_CFI
-	if (is_mx6dq() || is_mx6dqp())
-		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
-	else
-		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 #endif
-	gpio_request(IMX_GPIO_NR(1, 15), "expander en");
-	gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
+#endif
+
+	ret = dm_gpio_lookup_name("GPIO1_15", &desc);
+	if (ret) {
+		printf("%s lookup GPIO1_15 failed ret = %d\n", __func__, ret);
+		return -ENODEV;
+	}
+	ret = dm_gpio_request(&desc, "expander en");
+	if (ret) {
+		printf("%s request steer logic failed ret = %d\n", __func__, ret);
+		return -ENODEV;
+	}
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 	SETUP_IOMUX_PADS(port_exp);
 
 #ifdef CONFIG_VIDEO_IPUV3
 	setup_display();
 #endif
 
+#ifdef CONFIG_MXC_SPI
+	setup_spinor();
+#endif
+
 #ifdef CONFIG_MTD_NOR_FLASH
 	setup_iomux_eimnor();
 #endif
-	return 0;
-}
 
-#ifdef CONFIG_MXC_SPI
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
-	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
-}
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
 #endif
 
+	return 0;
+}
+
+#ifdef CONFIG_POWER_LEGACY
 int power_init_board(void)
 {
-	struct pmic *p;
+	struct pmic *pfuze;
 	unsigned int value;
+	int ret;
 
-	p = pfuze_common_init(I2C_PMIC);
-	if (!p)
+	pfuze = pfuze_common_init(I2C_PMIC);
+	if (!pfuze)
 		return -ENODEV;
 
+	if (is_mx6dqp())
+		ret = pfuze_mode_init(pfuze, APS_APS);
+	else
+		ret = pfuze_mode_init(pfuze, APS_PFM);
+
+	if (ret < 0)
+		return ret;
+
 	if (is_mx6dqp()) {
+		/* set SW1C staby volatage 1.075V*/
+		pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value);
+		value &= ~0x3f;
+		value |= 0x1f;
+		pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value);
+
+		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+		pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value);
+		value &= ~0xc0;
+		value |= 0x40;
+		pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value);
+
 		/* set SW2 staby volatage 0.975V*/
-		pmic_reg_read(p, PFUZE100_SW2STBY, &value);
+		pmic_reg_read(pfuze, PFUZE100_SW2STBY, &value);
 		value &= ~0x3f;
 		value |= 0x17;
-		pmic_reg_write(p, PFUZE100_SW2STBY, value);
+		pmic_reg_write(pfuze, PFUZE100_SW2STBY, value);
+
+		/* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */
+		pmic_reg_read(pfuze, PFUZE100_SW2CONF, &value);
+		value &= ~0xc0;
+		value |= 0x40;
+		pmic_reg_write(pfuze, PFUZE100_SW2CONF, value);
+	} else {
+		/* set SW1AB staby volatage 0.975V*/
+		pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value);
+		value &= ~0x3f;
+		value |= 0x1b;
+		pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value);
+
+		/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+		pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value);
+		value &= ~0xc0;
+		value |= 0x40;
+		pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value);
+
+		/* set SW1C staby volatage 0.975V*/
+		pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value);
+		value &= ~0x3f;
+		value |= 0x1b;
+		pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value);
+
+		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+		pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value);
+		value &= ~0xc0;
+		value |= 0x40;
+		pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value);
+	}
+
+	return 0;
+}
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+int power_init_board(void)
+{
+	struct udevice *dev;
+	unsigned int reg;
+	int ret;
+
+	dev = pfuze_common_init();
+	if (!dev)
+		return -ENODEV;
+
+	if (is_mx6dqp())
+		ret = pfuze_mode_init(dev, APS_APS);
+	else
+		ret = pfuze_mode_init(dev, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	if (is_mx6dqp()) {
+		/* set SW1C staby volatage 1.075V*/
+		reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
+		reg &= ~0x3f;
+		reg |= 0x1f;
+		pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
+
+		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+		reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
+
+		/* set SW2/VDDARM staby volatage 0.975V*/
+		reg = pmic_reg_read(dev, PFUZE100_SW2STBY);
+		reg &= ~0x3f;
+		reg |= 0x17;
+		pmic_reg_write(dev, PFUZE100_SW2STBY, reg);
+
+		/* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */
+		reg = pmic_reg_read(dev, PFUZE100_SW2CONF);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(dev, PFUZE100_SW2CONF, reg);
+	} else {
+		/* set SW1AB staby volatage 0.975V*/
+		reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
+		reg &= ~0x3f;
+		reg |= 0x1b;
+		pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
+
+		/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+		reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
+
+		/* set SW1C staby volatage 0.975V*/
+		reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
+		reg &= ~0x3f;
+		reg |= 0x1b;
+		pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
+
+		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+		reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
 	}
 
-	return pfuze_mode_init(p, APS_PFM);
+	return 0;
 }
+#endif
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+#ifdef CONFIG_POWER_LEGACY
+void ldo_mode_set(int ldo_bypass)
+{
+	unsigned int value;
+	struct pmic *p = pmic_get("PFUZE100");
+
+	if (!p) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* increase VDDARM/VDDSOC to support 1.2G chip */
+	if (check_1_2G()) {
+		ldo_bypass = 0;	/* ldo_enable on 1.2G chip */
+		printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
+
+		if (is_mx6dqp()) {
+			/* increase VDDARM to 1.425V */
+			pmic_reg_read(p, PFUZE100_SW2VOL, &value);
+			value &= ~0x3f;
+			value |= 0x29;
+			pmic_reg_write(p, PFUZE100_SW2VOL, value);
+		} else {
+			/* increase VDDARM to 1.425V */
+			pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+			value &= ~0x3f;
+			value |= 0x2d;
+			pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+		}
+		/* increase VDDSOC to 1.425V */
+		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+		value &= ~0x3f;
+		value |= 0x2d;
+		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+	}
+}
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+void ldo_mode_set(int ldo_bypass)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("pfuze100@8", &dev);
+	if (ret == -ENODEV) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* increase VDDARM/VDDSOC to support 1.2G chip */
+	if (check_1_2G()) {
+		ldo_bypass = 0; /* ldo_enable on 1.2G chip */
+		printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
+
+		if (is_mx6dqp()) {
+			/* increase VDDARM to 1.425V */
+			pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x29);
+		} else {
+			/* increase VDDARM to 1.425V */
+			pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x2d);
+		}
+		/* increase VDDSOC to 1.425V */
+		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x2d);
+	}
+}
+#endif
+#endif
 
 #ifdef CONFIG_CMD_BMODE
 static const struct boot_mode board_boot_modes[] = {
@@ -586,6 +912,11 @@ int board_late_init(void)
 	add_board_boot_modes(board_boot_modes);
 #endif
 
+	env_set("tee", "no");
+#ifdef CONFIG_IMX_OPTEE
+	env_set("tee", "yes");
+#endif
+
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	env_set("board_name", "SABREAUTO");
 
@@ -597,6 +928,10 @@ int board_late_init(void)
 		env_set("board_rev", "MX6DL");
 #endif
 
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
 	return 0;
 }
 
@@ -628,6 +963,49 @@ int board_ehci_hcd_init(int port)
 }
 #endif
 
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+
+iomux_v3_cfg_t const recovery_key_pads[] = {
+	IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+int is_recovery_key_pressing(void)
+{
+	int button_pressed = 0;
+	int ret;
+	struct gpio_desc desc;
+
+	/* Check Recovery Combo Button press or not. */
+	SETUP_IOMUX_PADS(recovery_key_pads);
+
+	ret = dm_gpio_lookup_name("GPIO5_14", &desc);
+	if (ret) {
+		printf("%s lookup GPIO5_14 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "volume_dn_key");
+	if (ret) {
+		printf("%s request volume_dn_key failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN);
+
+	if (dm_gpio_get_value(&desc) == 0) { /* VOL_DN key is low assert */
+		button_pressed = 1;
+		printf("Recovery key pressed\n");
+	}
+
+	return  button_pressed;
+}
+
+#endif /*CONFIG_ANDROID_RECOVERY*/
+
+#endif /*CONFIG_FSL_FASTBOOT*/
+
+
 #ifdef CONFIG_SPL_BUILD
 #include <asm/arch/mx6-ddr.h>
 #include <spl.h>
diff --git a/board/freescale/mx6sabreauto/mx6solo.cfg b/board/freescale/mx6sabreauto/mx6solo.cfg
new file mode 100644
index 00000000000..36faa082569
--- /dev/null
+++ b/board/freescale/mx6sabreauto/mx6solo.cfg
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of spi, sd, eimnor, nand, sata:
+ * spinor: flash_offset: 0x0400
+ * nand:   flash_offset: 0x0400
+ * sata:   flash_offset: 0x0400
+ * sd/mmc: flash_offset: 0x0400
+ * eimnor: flash_offset: 0x1000
+ */
+
+#if defined(CONFIG_NOR_BOOT)
+BOOT_FROM       nor
+#else /* others has the same flash_offset as sd */
+BOOT_FROM       sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6sabreauto/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+#ifdef CONFIG_IMX_OPTEE
+SET_BIT 4 0x20c4070 0x3c00000
+DATA 4 0x20e0024 0x00000003
+CHECK_BITS_SET 4 0x20e0024 0x3
+#endif
+DATA 4, 0x020e0774, 0x000C0000
+DATA 4, 0x020e0754, 0x00000000
+DATA 4, 0x020e04ac, 0x00000030
+DATA 4, 0x020e04b0, 0x00000030
+DATA 4, 0x020e0464, 0x00000030
+DATA 4, 0x020e0490, 0x00000030
+DATA 4, 0x020e074c, 0x00000030
+DATA 4, 0x020e0494, 0x00000030
+DATA 4, 0x020e04a0, 0x00000000
+DATA 4, 0x020e04b4, 0x00000030
+DATA 4, 0x020e04b8, 0x00000030
+DATA 4, 0x020e076c, 0x00000030
+DATA 4, 0x020e0750, 0x00020000
+DATA 4, 0x020e04bc, 0x00000028
+DATA 4, 0x020e04c0, 0x00000028
+DATA 4, 0x020e04c4, 0x00000028
+DATA 4, 0x020e04c8, 0x00000028
+DATA 4, 0x020e0760, 0x00020000
+DATA 4, 0x020e0764, 0x00000028
+DATA 4, 0x020e0770, 0x00000028
+DATA 4, 0x020e0778, 0x00000028
+DATA 4, 0x020e077c, 0x00000028
+DATA 4, 0x020e0470, 0x00000028
+DATA 4, 0x020e0474, 0x00000028
+DATA 4, 0x020e0478, 0x00000028
+DATA 4, 0x020e047c, 0x00000028
+DATA 4, 0x021b0800, 0xa1390003
+DATA 4, 0x021b080c, 0x001F001F
+DATA 4, 0x021b0810, 0x001F001F
+DATA 4, 0x021b083c, 0x421C0216
+DATA 4, 0x021b0840, 0x017B017A
+DATA 4, 0x021b0848, 0x4B4A4E4C
+DATA 4, 0x021b0850, 0x3F3F3334
+DATA 4, 0x021b081c, 0x33333333
+DATA 4, 0x021b0820, 0x33333333
+DATA 4, 0x021b0824, 0x33333333
+DATA 4, 0x021b0828, 0x33333333
+DATA 4, 0x021b08b8, 0x00000800
+DATA 4, 0x021b0004, 0x00020025
+DATA 4, 0x021b0008, 0x00333030
+DATA 4, 0x021b000c, 0x676B5313
+DATA 4, 0x021b0010, 0xB66E8B63
+DATA 4, 0x021b0014, 0x01FF00DB
+DATA 4, 0x021b0018, 0x00001740
+DATA 4, 0x021b001c, 0x00008000
+DATA 4, 0x021b002c, 0x000026d2
+DATA 4, 0x021b0030, 0x006B1023
+DATA 4, 0x021b0040, 0x00000027
+DATA 4, 0x021b0000, 0x84190000
+DATA 4, 0x021b001c, 0x04008032
+DATA 4, 0x021b001c, 0x00008033
+DATA 4, 0x021b001c, 0x00048031
+DATA 4, 0x021b001c, 0x05208030
+DATA 4, 0x021b001c, 0x04008040
+DATA 4, 0x021b0020, 0x00005800
+DATA 4, 0x021b0818, 0x00011117
+DATA 4, 0x021b0004, 0x00025565
+DATA 4, 0x021b0404, 0x00011006
+DATA 4, 0x021b001c, 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFF000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0xFFFFF300
+DATA 4, 0x020c407c, 0x0F0000C3
+DATA 4, 0x020c4080, 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, 0x020e0018, 0x007F007F
+DATA 4, 0x020e001c, 0x007F007F
+#endif
diff --git a/board/freescale/mx6sabreauto/plugin.S b/board/freescale/mx6sabreauto/plugin.S
new file mode 100644
index 00000000000..6301ae1990f
--- /dev/null
+++ b/board/freescale/mx6sabreauto/plugin.S
@@ -0,0 +1,675 @@
+/*
+ * Copyright (C) 2012-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6dqpsabreauto_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x798]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x758]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x588]
+	str r1, [r0, #0x594]
+	str r1, [r0, #0x56c]
+	str r1, [r0, #0x578]
+	str r1, [r0, #0x74c]
+	str r1, [r0, #0x57c]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x58c]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x59c]
+	str r1, [r0, #0x5a0]
+	str r1, [r0, #0x78c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x5a8]
+	str r1, [r0, #0x5b0]
+	str r1, [r0, #0x524]
+	str r1, [r0, #0x51c]
+	str r1, [r0, #0x518]
+	str r1, [r0, #0x50c]
+	str r1, [r0, #0x5b8]
+	str r1, [r0, #0x5c0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x774]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x784]
+	str r1, [r0, #0x788]
+	str r1, [r0, #0x794]
+	str r1, [r0, #0x79c]
+	str r1, [r0, #0x7a0]
+	str r1, [r0, #0x7a4]
+	str r1, [r0, #0x7a8]
+	str r1, [r0, #0x748]
+	str r1, [r0, #0x5ac]
+	str r1, [r0, #0x5b4]
+	str r1, [r0, #0x528]
+	str r1, [r0, #0x520]
+	str r1, [r0, #0x514]
+	str r1, [r0, #0x510]
+	str r1, [r0, #0x5bc]
+	str r1, [r0, #0x5c4]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x001b001e
+	str r2, [r0, #0x80c]
+	ldr r2, =0x002e0029
+	str r2, [r0, #0x810]
+	ldr r1, =MMDC_P1_BASE_ADDR
+	ldr r2, =0x001b002a
+	str r2, [r1, #0x80c]
+	ldr r2, =0x0019002c
+	str r2, [r1, #0x810]
+
+	ldr r2, =0x43240334
+	str r2, [r0, #0x83c]
+	ldr r2, =0x0324031a
+	str r2, [r0, #0x840]
+
+	ldr r2, =0x43340344
+	str r2, [r1, #0x83c]
+	ldr r2, =0x03280276
+	str r2, [r1, #0x840]
+
+	ldr r2, =0x44383A3E
+	str r2, [r0, #0x848]
+	ldr r2, =0x3C3C3846
+	str r2, [r1, #0x848]
+
+	ldr r2, =0x2e303230
+	str r2, [r0, #0x850]
+	ldr r2, =0x38283E34
+	str r2, [r1, #0x850]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+	str r2, [r1, #0x81c]
+	str r2, [r1, #0x820]
+	str r2, [r1, #0x824]
+	str r2, [r1, #0x828]
+
+	ldr r2, =0x24912249
+	str r2, [r0, #0x8c0]
+	ldr r2, =0x24914289
+	str r2, [r1, #0x8c0]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x00020036
+	str r2, [r0, #0x004]
+	ldr r2, =0x24444040
+	str r2, [r0, #0x008]
+
+	ldr r2, =0x898E7955
+	str r2, [r0, #0x00c]
+	ldr r2, =0xFF320F64
+	str r2, [r0, #0x010]
+
+	ldr r2, =0x01FF00DB
+	str r2, [r0, #0x014]
+	ldr r2, =0x00001740
+	str r2, [r0, #0x018]
+
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x008E1023
+	str r2, [r0, #0x030]
+	ldr r2, =0x00000047
+	str r2, [r0, #0x040]
+
+	ldr r2, =0x14420000
+	str r2, [r0, #0x400]
+	ldr r2, =0x841A0000
+	str r2, [r0, #0x000]
+
+	ldr r2, =0x00400C58
+	str r2, [r0, #0x890]
+
+	ldr r3, =0x00bb0000
+	ldr r2, =0x00000000
+	str r2, [r3, #0x008]
+	ldr r2, =0x2891E41A
+	str r2, [r3, #0x00c]
+	ldr r2, =0x00000564
+	str r2, [r3, #0x038]
+	ldr r2, =0x00000040
+	str r2, [r3, #0x014]
+	ldr r2, =0x00000020
+	str r2, [r3, #0x028]
+	str r2, [r3, #0x02c]
+
+	ldr r2, =0x04088032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00048031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x09408030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00005800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00011117
+	str r2, [r0, #0x818]
+	str r2, [r1, #0x818]
+	ldr r2, =0x00025576
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+.endm
+
+.macro imx6dqsabreauto_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x798]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x758]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x588]
+	str r1, [r0, #0x594]
+	str r1, [r0, #0x56c]
+	str r1, [r0, #0x578]
+	str r1, [r0, #0x74c]
+	str r1, [r0, #0x57c]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x58c]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x59c]
+	str r1, [r0, #0x5a0]
+	str r1, [r0, #0x78c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+
+	ldr r1, =0x00000028
+	str r1, [r0, #0x5a8]
+	str r1, [r0, #0x5b0]
+	str r1, [r0, #0x524]
+	str r1, [r0, #0x51c]
+	str r1, [r0, #0x518]
+	str r1, [r0, #0x50c]
+	str r1, [r0, #0x5b8]
+	str r1, [r0, #0x5c0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x774]
+
+	ldr r1, =0x00000028
+	str r1, [r0, #0x784]
+	str r1, [r0, #0x788]
+	str r1, [r0, #0x794]
+	str r1, [r0, #0x79c]
+	str r1, [r0, #0x7a0]
+	str r1, [r0, #0x7a4]
+	str r1, [r0, #0x7a8]
+	str r1, [r0, #0x748]
+	str r1, [r0, #0x5ac]
+	str r1, [r0, #0x5b4]
+	str r1, [r0, #0x528]
+	str r1, [r0, #0x520]
+	str r1, [r0, #0x514]
+	str r1, [r0, #0x510]
+	str r1, [r0, #0x5bc]
+	str r1, [r0, #0x5c4]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x001F001F
+	str r2, [r0, #0x80c]
+	str r2, [r0, #0x810]
+	ldr r1, =MMDC_P1_BASE_ADDR
+	str r2, [r1, #0x80c]
+	str r2, [r1, #0x810]
+
+	ldr r2, =0x43260335
+	str r2, [r0, #0x83c]
+	ldr r2, =0x031A030B
+	str r2, [r0, #0x840]
+
+	ldr r2, =0x4323033B
+	str r2, [r1, #0x83c]
+	ldr r2, =0x0323026F
+	str r2, [r1, #0x840]
+
+	ldr r2, =0x483D4545
+	str r2, [r0, #0x848]
+	ldr r2, =0x44433E48
+	str r2, [r1, #0x848]
+
+	ldr r2, =0x41444840
+	str r2, [r0, #0x850]
+	ldr r2, =0x4835483E
+	str r2, [r1, #0x850]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+	str r2, [r1, #0x81c]
+	str r2, [r1, #0x820]
+	str r2, [r1, #0x824]
+	str r2, [r1, #0x828]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x00020036
+	str r2, [r0, #0x004]
+	ldr r2, =0x09444040
+	str r2, [r0, #0x008]
+
+	ldr r2, =0x8A8F7955
+	str r2, [r0, #0x00c]
+	ldr r2, =0xFF328F64
+	str r2, [r0, #0x010]
+
+	ldr r2, =0x01FF00DB
+	str r2, [r0, #0x014]
+	ldr r2, =0x00001740
+	str r2, [r0, #0x018]
+
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x008F1023
+	str r2, [r0, #0x030]
+	ldr r2, =0x00000047
+	str r2, [r0, #0x040]
+
+	ldr r2, =0x841A0000
+	str r2, [r0, #0x000]
+
+	ldr r2, =0x04088032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00048031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x09408030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00005800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00011117
+	str r2, [r0, #0x818]
+	str r2, [r1, #0x818]
+	ldr r2, =0x00025576
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+.endm
+
+.macro imx6dlsabreauto_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x774]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x754]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4ac]
+	str r1, [r0, #0x4b0]
+	str r1, [r0, #0x464]
+	str r1, [r0, #0x490]
+	str r1, [r0, #0x74c]
+	str r1, [r0, #0x494]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4a0]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4b4]
+	str r1, [r0, #0x4b8]
+	str r1, [r0, #0x76c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+
+	ldr r1, =0x00000028
+	str r1, [r0, #0x4bc]
+	str r1, [r0, #0x4c0]
+	str r1, [r0, #0x4c4]
+	str r1, [r0, #0x4c8]
+	str r1, [r0, #0x4cc]
+	str r1, [r0, #0x4d0]
+	str r1, [r0, #0x4d4]
+	str r1, [r0, #0x4d8]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x760]
+
+	ldr r1, =0x00000028
+	str r1, [r0, #0x764]
+	str r1, [r0, #0x770]
+	str r1, [r0, #0x778]
+	str r1, [r0, #0x77c]
+	str r1, [r0, #0x780]
+	str r1, [r0, #0x784]
+	str r1, [r0, #0x78c]
+	str r1, [r0, #0x748]
+	str r1, [r0, #0x470]
+	str r1, [r0, #0x474]
+	str r1, [r0, #0x478]
+	str r1, [r0, #0x47c]
+	str r1, [r0, #0x480]
+	str r1, [r0, #0x484]
+	str r1, [r0, #0x488]
+	str r1, [r0, #0x48c]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x001f001f
+	str r2, [r0, #0x80c]
+	str r2, [r0, #0x810]
+	ldr r1, =MMDC_P1_BASE_ADDR
+	str r2, [r1, #0x80c]
+	str r2, [r1, #0x810]
+
+	ldr r2, =0x42190217
+	str r2, [r0, #0x83c]
+	ldr r2, =0x017b017b
+	str r2, [r0, #0x840]
+
+	ldr r2, =0x4176017b
+	str r2, [r1, #0x83c]
+	ldr r2, =0x015f016c
+	str r2, [r1, #0x840]
+
+	ldr r2, =0x4c4c4d4c
+	str r2, [r0, #0x848]
+	ldr r2, =0x4a4d4c48
+	str r2, [r1, #0x848]
+
+	ldr r2, =0x3f3f3f40
+	str r2, [r0, #0x850]
+	ldr r2, =0x3538382e
+	str r2, [r1, #0x850]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+	str r2, [r1, #0x81c]
+	str r2, [r1, #0x820]
+	str r2, [r1, #0x824]
+	str r2, [r1, #0x828]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x00020025
+	str r2, [r0, #0x004]
+	ldr r2, =0x00333030
+	str r2, [r0, #0x008]
+
+	ldr r2, =0x676b5313
+	str r2, [r0, #0x00c]
+	ldr r2, =0xb66e8b63
+	str r2, [r0, #0x010]
+
+	ldr r2, =0x01ff00db
+	str r2, [r0, #0x014]
+	ldr r2, =0x00001740
+	str r2, [r0, #0x018]
+
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x006b1023
+	str r2, [r0, #0x030]
+	ldr r2, =0x00000047
+	str r2, [r0, #0x040]
+
+	ldr r2, =0x841a0000
+	str r2, [r0, #0x000]
+
+	ldr r2, =0x04008032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00048031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x05208030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00005800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00011117
+	str r2, [r0, #0x818]
+	str r2, [r1, #0x818]
+	ldr r2, =0x00025565
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+.endm
+
+.macro imx6solosabreauto_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x774]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x754]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4ac]
+	str r1, [r0, #0x4b0]
+	str r1, [r0, #0x464]
+	str r1, [r0, #0x490]
+	str r1, [r0, #0x74c]
+	str r1, [r0, #0x494]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4a0]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4b4]
+	str r1, [r0, #0x4b8]
+	str r1, [r0, #0x76c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+
+	ldr r1, =0x00000028
+	str r1, [r0, #0x4bc]
+	str r1, [r0, #0x4c0]
+	str r1, [r0, #0x4c4]
+	str r1, [r0, #0x4c8]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x760]
+
+	ldr r1, =0x00000028
+	str r1, [r0, #0x764]
+	str r1, [r0, #0x770]
+	str r1, [r0, #0x778]
+	str r1, [r0, #0x77c]
+	str r1, [r0, #0x470]
+	str r1, [r0, #0x474]
+	str r1, [r0, #0x478]
+	str r1, [r0, #0x47c]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x001F001F
+	str r2, [r0, #0x80c]
+	str r2, [r0, #0x810]
+
+	ldr r2, =0x421C0216
+	str r2, [r0, #0x83c]
+	ldr r2, =0x017B017A
+	str r2, [r0, #0x840]
+
+	ldr r2, =0x4B4A4E4C
+	str r2, [r0, #0x848]
+
+	ldr r2, =0x3F3F3334
+	str r2, [r0, #0x850]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+
+	ldr r2, =0x00020025
+	str r2, [r0, #0x004]
+	ldr r2, =0x00333030
+	str r2, [r0, #0x008]
+
+	ldr r2, =0x676B5313
+	str r2, [r0, #0x00c]
+	ldr r2, =0xB66E8B63
+	str r2, [r0, #0x010]
+
+	ldr r2, =0x01FF00DB
+	str r2, [r0, #0x014]
+	ldr r2, =0x00001740
+	str r2, [r0, #0x018]
+
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x006B1023
+	str r2, [r0, #0x030]
+	ldr r2, =0x00000027
+	str r2, [r0, #0x040]
+
+	ldr r2, =0x84190000
+	str r2, [r0, #0x000]
+
+	ldr r2, =0x04008032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00048031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x05208030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00005800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00011117
+	str r2, [r0, #0x818]
+	ldr r2, =0x00025565
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+.endm
+
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0x00C03F3F
+	str r1, [r0, #0x068]
+	ldr r1, =0x0030FC03
+	str r1, [r0, #0x06c]
+	ldr r1, =0x0FFFF000
+	str r1, [r0, #0x070]
+	ldr r1, =0x3FF00000
+	str r1, [r0, #0x074]
+	ldr r1, =0xFFFFF300
+	str r1, [r0, #0x078]
+	ldr r1, =0x0F0000C3
+	str r1, [r0, #0x07c]
+	ldr r1, =0x00000FFF
+	str r1, [r0, #0x080]
+
+#ifdef CONFIG_IMX_OPTEE
+#ifndef CONFIG_MX6QP
+	ldr r0, =0x20e0024
+	ldr r1, =0x3
+	str r1, [r0]
+#endif
+#endif
+.endm
+
+.macro imx6_qos_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0xF00000CF
+	str r1, [r0, #0x10]
+
+#if defined(CONFIG_MX6QP)
+	ldr r1, =0x77177717
+	str r1, [r0, #0x18]
+	str r1, [r0, #0x1c]
+#else
+	ldr r1, =0x007F007F
+	str r1, [r0, #0x18]
+	str r1, [r0, #0x1c]
+#endif
+.endm
+
+.macro imx6_ddr_setting
+#if defined (CONFIG_MX6S)
+	imx6solosabreauto_ddr_setting
+#elif defined (CONFIG_MX6DL)
+	imx6dlsabreauto_ddr_setting
+#elif defined (CONFIG_MX6QP)
+	imx6dqpsabreauto_ddr_setting
+#elif defined (CONFIG_MX6Q)
+	imx6dqsabreauto_ddr_setting
+#else
+	#error "SOC not configured"
+#endif
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/board/freescale/mx6sabresd/Kconfig b/board/freescale/mx6sabresd/Kconfig
index e87dea0d7a2..124ba8b48fe 100644
--- a/board/freescale/mx6sabresd/Kconfig
+++ b/board/freescale/mx6sabresd/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_MX6SABRESD
+if TARGET_MX6SABRESD || TARGET_MX6SABRESD_COMMON
 
 config SYS_BOARD
 	default "mx6sabresd"
@@ -9,4 +9,7 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "mx6sabresd"
 
+config SYS_TEXT_BASE
+    default 0x17800000
+
 endif
diff --git a/board/freescale/mx6sabresd/mx6dlsabresd.cfg b/board/freescale/mx6sabresd/mx6dlsabresd.cfg
new file mode 100644
index 00000000000..320901e36c4
--- /dev/null
+++ b/board/freescale/mx6sabresd/mx6dlsabresd.cfg
@@ -0,0 +1,149 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+#ifdef CONFIG_IMX_OPTEE
+SET_BIT 4 0x20c4070 0x3c00000
+DATA 4 0x20e0024 0x00000003
+CHECK_BITS_SET 4 0x20e0024 0x3
+#endif
+DATA 4	0x020e0774 0x000C0000
+DATA 4	0x020e0754 0x00000000
+DATA 4	0x020e04ac 0x00000030
+DATA 4	0x020e04b0 0x00000030
+DATA 4	0x020e0464 0x00000030
+DATA 4	0x020e0490 0x00000030
+DATA 4	0x020e074c 0x00000030
+DATA 4	0x020e0494 0x00000030
+DATA 4	0x020e04a0 0x00000000
+DATA 4	0x020e04b4 0x00000030
+DATA 4	0x020e04b8 0x00000030
+DATA 4	0x020e076c 0x00000030
+DATA 4	0x020e0750 0x00020000
+DATA 4	0x020e04bc 0x00000030
+DATA 4	0x020e04c0 0x00000030
+DATA 4	0x020e04c4 0x00000030
+DATA 4	0x020e04c8 0x00000030
+DATA 4	0x020e04cc 0x00000030
+DATA 4	0x020e04d0 0x00000030
+DATA 4	0x020e04d4 0x00000030
+DATA 4	0x020e04d8 0x00000030
+DATA 4	0x020e0760 0x00020000
+DATA 4	0x020e0764 0x00000030
+DATA 4	0x020e0770 0x00000030
+DATA 4	0x020e0778 0x00000030
+DATA 4	0x020e077c 0x00000030
+DATA 4	0x020e0780 0x00000030
+DATA 4	0x020e0784 0x00000030
+DATA 4	0x020e078c 0x00000030
+DATA 4	0x020e0748 0x00000030
+DATA 4	0x020e0470 0x00000030
+DATA 4	0x020e0474 0x00000030
+DATA 4	0x020e0478 0x00000030
+DATA 4	0x020e047c 0x00000030
+DATA 4	0x020e0480 0x00000030
+DATA 4	0x020e0484 0x00000030
+DATA 4	0x020e0488 0x00000030
+DATA 4	0x020e048c 0x00000030
+DATA 4	0x021b0800 0xa1390003
+DATA 4	0x021b080c 0x001F001F
+DATA 4	0x021b0810 0x001F001F
+DATA 4	0x021b480c 0x001F001F
+DATA 4	0x021b4810 0x001F001F
+DATA 4	0x021b083c 0x4220021F
+DATA 4	0x021b0840 0x0207017E
+DATA 4	0x021b483c 0x4201020C
+DATA 4	0x021b4840 0x01660172
+DATA 4	0x021b0848 0x4A4D4E4D
+DATA 4	0x021b4848 0x4A4F5049
+DATA 4	0x021b0850 0x3F3C3D31
+DATA 4	0x021b4850 0x3238372B
+DATA 4	0x021b081c 0x33333333
+DATA 4	0x021b0820 0x33333333
+DATA 4	0x021b0824 0x33333333
+DATA 4	0x021b0828 0x33333333
+DATA 4	0x021b481c 0x33333333
+DATA 4	0x021b4820 0x33333333
+DATA 4	0x021b4824 0x33333333
+DATA 4	0x021b4828 0x33333333
+DATA 4	0x021b08b8 0x00000800
+DATA 4	0x021b48b8 0x00000800
+DATA 4	0x021b0004 0x0002002D
+DATA 4	0x021b0008 0x00333030
+DATA 4	0x021b000c 0x3F435313
+DATA 4	0x021b0010 0xB66E8B63
+DATA 4	0x021b0014 0x01FF00DB
+DATA 4	0x021b0018 0x00001740
+DATA 4	0x021b001c 0x00008000
+DATA 4	0x021b002c 0x000026d2
+DATA 4	0x021b0030 0x00431023
+DATA 4	0x021b0040 0x00000027
+DATA 4	0x021b0000 0x831A0000
+DATA 4	0x021b001c 0x04008032
+DATA 4	0x021b001c 0x00008033
+DATA 4	0x021b001c 0x00048031
+DATA 4	0x021b001c 0x05208030
+DATA 4 0x021b001c 0x04008040
+DATA 4	0x021b0020 0x00005800
+DATA 4	0x021b0818 0x00011117
+DATA 4	0x021b4818 0x00011117
+DATA 4	0x021b0004 0x0002556D
+DATA 4	0x021b0404 0x00011006
+DATA 4	0x021b001c 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFF000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+#endif
diff --git a/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
new file mode 100644
index 00000000000..5aafb4d3ae0
--- /dev/null
+++ b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2011-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+#ifdef CONFIG_IMX_OPTEE
+SET_BIT 4 0x20c4070 0x3c00000
+DATA 4 0x20e0024 0x00000003
+CHECK_BITS_SET 4 0x20e0024 0x3
+#endif
+DATA 4 0x020e0798 0x000C0000
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0588 0x00000030
+DATA 4 0x020e0594 0x00000030
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e058c 0x00000000
+DATA 4 0x020e059c 0x00000030
+DATA 4 0x020e05a0 0x00000030
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e05ac 0x00000030
+DATA 4 0x020e05b4 0x00000030
+DATA 4 0x020e0528 0x00000030
+DATA 4 0x020e0520 0x00000030
+DATA 4 0x020e0514 0x00000030
+DATA 4 0x020e0510 0x00000030
+DATA 4 0x020e05bc 0x00000030
+DATA 4 0x020e05c4 0x00000030
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+DATA 4 0x021b480c 0x001F001F
+DATA 4 0x021b4810 0x001F001F
+DATA 4 0x021b083c 0x43270338
+DATA 4 0x021b0840 0x03200314
+DATA 4 0x021b483c 0x431A032F
+DATA 4 0x021b4840 0x03200263
+DATA 4 0x021b0848 0x4B434748
+DATA 4 0x021b4848 0x4445404C
+DATA 4 0x021b0850 0x38444542
+DATA 4 0x021b4850 0x4935493A
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b000c 0x555A7975
+DATA 4 0x021b0010 0xFF538F64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x005A1023
+DATA 4 0x021b0040 0x00000027
+DATA 4 0x021b0000 0x831A0000
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x09408030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFF000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000F3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1	   --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4 0x020c4060 0x000000fb
+#endif
diff --git a/board/freescale/mx6sabresd/mx6qp.cfg b/board/freescale/mx6sabresd/mx6qp.cfg
new file mode 100644
index 00000000000..57bf74d7412
--- /dev/null
+++ b/board/freescale/mx6sabresd/mx6qp.cfg
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6sabresd/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+DATA 4, 0x020e0798, 0x000c0000
+DATA 4, 0x020e0758, 0x00000000
+DATA 4, 0x020e0588, 0x00000030
+DATA 4, 0x020e0594, 0x00000030
+DATA 4, 0x020e056c, 0x00000030
+DATA 4, 0x020e0578, 0x00000030
+DATA 4, 0x020e074c, 0x00000030
+DATA 4, 0x020e057c, 0x00000030
+DATA 4, 0x020e058c, 0x00000000
+DATA 4, 0x020e059c, 0x00000030
+DATA 4, 0x020e05a0, 0x00000030
+DATA 4, 0x020e078c, 0x00000030
+DATA 4, 0x020e0750, 0x00020000
+DATA 4, 0x020e05a8, 0x00000030
+DATA 4, 0x020e05b0, 0x00000030
+DATA 4, 0x020e0524, 0x00000030
+DATA 4, 0x020e051c, 0x00000030
+DATA 4, 0x020e0518, 0x00000030
+DATA 4, 0x020e050c, 0x00000030
+DATA 4, 0x020e05b8, 0x00000030
+DATA 4, 0x020e05c0, 0x00000030
+
+DATA 4, 0x020e0534, 0x00018200
+DATA 4, 0x020e0538, 0x00008000
+DATA 4, 0x020e053c, 0x00018200
+DATA 4, 0x020e0540, 0x00018200
+DATA 4, 0x020e0544, 0x00018200
+DATA 4, 0x020e0548, 0x00018200
+DATA 4, 0x020e054c, 0x00018200
+DATA 4, 0x020e0550, 0x00018200
+
+DATA 4, 0x020e0774, 0x00020000
+DATA 4, 0x020e0784, 0x00000030
+DATA 4, 0x020e0788, 0x00000030
+DATA 4, 0x020e0794, 0x00000030
+DATA 4, 0x020e079c, 0x00000030
+DATA 4, 0x020e07a0, 0x00000030
+DATA 4, 0x020e07a4, 0x00000030
+DATA 4, 0x020e07a8, 0x00000030
+DATA 4, 0x020e0748, 0x00000030
+DATA 4, 0x020e05ac, 0x00000030
+DATA 4, 0x020e05b4, 0x00000030
+DATA 4, 0x020e0528, 0x00000030
+DATA 4, 0x020e0520, 0x00000030
+DATA 4, 0x020e0514, 0x00000030
+DATA 4, 0x020e0510, 0x00000030
+DATA 4, 0x020e05bc, 0x00000030
+DATA 4, 0x020e05c4, 0x00000030
+DATA 4, 0x021b0800, 0xa1390003
+DATA 4, 0x021b080c, 0x001b001e
+DATA 4, 0x021b0810, 0x002e0029
+DATA 4, 0x021b480c, 0x001b002a
+DATA 4, 0x021b4810, 0x0019002c
+DATA 4, 0x021b083c, 0x43240334
+DATA 4, 0x021b0840, 0x0324031a
+DATA 4, 0x021b483c, 0x43340344
+DATA 4, 0x021b4840, 0x03280276
+DATA 4, 0x021b0848, 0x44383A3E
+DATA 4, 0x021b4848, 0x3C3C3846
+DATA 4, 0x021b0850, 0x2e303230
+DATA 4, 0x021b4850, 0x38283E34
+DATA 4, 0x021b081c, 0x33333333
+DATA 4, 0x021b0820, 0x33333333
+DATA 4, 0x021b0824, 0x33333333
+DATA 4, 0x021b0828, 0x33333333
+DATA 4, 0x021b481c, 0x33333333
+DATA 4, 0x021b4820, 0x33333333
+DATA 4, 0x021b4824, 0x33333333
+DATA 4, 0x021b4828, 0x33333333
+DATA 4, 0x021b08c0, 0x24912489
+DATA 4, 0x021b48c0, 0x24914452
+DATA 4, 0x021b08b8, 0x00000800
+DATA 4, 0x021b48b8, 0x00000800
+DATA 4, 0x021b0004, 0x00020036
+DATA 4, 0x021b0008, 0x24444040
+DATA 4, 0x021b000c, 0x555A7955
+DATA 4, 0x021b0010, 0xFF320F64
+DATA 4, 0x021b0014, 0x01ff00db
+DATA 4, 0x021b0018, 0x00011740
+DATA 4, 0x021b001c, 0x00008000
+DATA 4, 0x021b002c, 0x000026d2
+DATA 4, 0x021b0030, 0x005A1023
+DATA 4, 0x021b0040, 0x00000027
+DATA 4, 0x021b0400, 0x14420000
+DATA 4, 0x021b0000, 0x831A0000
+DATA 4, 0x021b0890, 0x00400C58
+DATA 4, 0x00bb0008, 0x00000000
+DATA 4, 0x00bb000c, 0x2891E41A
+DATA 4, 0x00bb0038, 0x00000564
+DATA 4, 0x00bb0014, 0x00000040
+DATA 4, 0x00bb0028, 0x00000020
+DATA 4, 0x00bb002c, 0x00000020
+DATA 4, 0x021b001c, 0x04088032
+DATA 4, 0x021b001c, 0x00008033
+DATA 4, 0x021b001c, 0x00048031
+DATA 4, 0x021b001c, 0x09408030
+DATA 4, 0x021b001c, 0x04008040
+DATA 4, 0x021b0020, 0x00005800
+DATA 4, 0x021b0818, 0x00011117
+DATA 4, 0x021b4818, 0x00011117
+DATA 4, 0x021b0004, 0x00025576
+DATA 4, 0x021b0404, 0x00011006
+DATA 4, 0x021b001c, 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFF000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0x00FFF300
+DATA 4, 0x020c407c, 0x0F0000F3
+DATA 4, 0x020c4080, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+DATA 4, 0x020e0018, 0x77177717
+DATA 4, 0x020e001c, 0x77177717
+#endif
diff --git a/board/freescale/mx6sabresd/mx6qp_optee.cfg b/board/freescale/mx6sabresd/mx6qp_optee.cfg
new file mode 100644
index 00000000000..6d3cfd4f678
--- /dev/null
+++ b/board/freescale/mx6sabresd/mx6qp_optee.cfg
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6sabresd/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+#ifdef CONFIG_IMX_OPTEE
+SET_BIT 4 0x20c4070 0x3c00000
+DATA 4 0x20e0024 0x00000003
+CHECK_BITS_SET 4 0x20e0024 0x3
+#endif
+DATA 4, 0x020e0798, 0x000c0000
+DATA 4, 0x020e0758, 0x00000000
+DATA 4, 0x020e0588, 0x00000030
+DATA 4, 0x020e0594, 0x00000030
+DATA 4, 0x020e056c, 0x00000030
+DATA 4, 0x020e0578, 0x00000030
+DATA 4, 0x020e074c, 0x00000030
+DATA 4, 0x020e057c, 0x00000030
+DATA 4, 0x020e058c, 0x00000000
+DATA 4, 0x020e059c, 0x00000030
+DATA 4, 0x020e05a0, 0x00000030
+DATA 4, 0x020e078c, 0x00000030
+DATA 4, 0x020e0750, 0x00020000
+DATA 4, 0x020e05a8, 0x00000030
+DATA 4, 0x020e05b0, 0x00000030
+DATA 4, 0x020e0524, 0x00000030
+DATA 4, 0x020e051c, 0x00000030
+DATA 4, 0x020e0518, 0x00000030
+DATA 4, 0x020e050c, 0x00000030
+DATA 4, 0x020e05b8, 0x00000030
+DATA 4, 0x020e05c0, 0x00000030
+
+DATA 4, 0x020e0534, 0x00018200
+DATA 4, 0x020e0538, 0x00008000
+DATA 4, 0x020e053c, 0x00018200
+DATA 4, 0x020e0540, 0x00018200
+DATA 4, 0x020e0544, 0x00018200
+DATA 4, 0x020e0548, 0x00018200
+DATA 4, 0x020e054c, 0x00018200
+DATA 4, 0x020e0550, 0x00018200
+
+DATA 4, 0x020e0774, 0x00020000
+DATA 4, 0x020e0784, 0x00000030
+DATA 4, 0x020e0788, 0x00000030
+DATA 4, 0x020e0794, 0x00000030
+DATA 4, 0x020e079c, 0x00000030
+DATA 4, 0x020e07a0, 0x00000030
+DATA 4, 0x020e07a4, 0x00000030
+DATA 4, 0x020e07a8, 0x00000030
+DATA 4, 0x020e0748, 0x00000030
+DATA 4, 0x020e05ac, 0x00000030
+DATA 4, 0x020e05b4, 0x00000030
+DATA 4, 0x020e0528, 0x00000030
+DATA 4, 0x020e0520, 0x00000030
+DATA 4, 0x020e0514, 0x00000030
+DATA 4, 0x020e0510, 0x00000030
+DATA 4, 0x020e05bc, 0x00000030
+DATA 4, 0x020e05c4, 0x00000030
+DATA 4, 0x021b0800, 0xa1390003
+DATA 4, 0x021b080c, 0x001b001e
+DATA 4, 0x021b0810, 0x002e0029
+DATA 4, 0x021b480c, 0x001b002a
+DATA 4, 0x021b4810, 0x0019002c
+DATA 4, 0x021b083c, 0x43240334
+DATA 4, 0x021b0840, 0x0324031a
+DATA 4, 0x021b483c, 0x43340344
+DATA 4, 0x021b4840, 0x03280276
+DATA 4, 0x021b0848, 0x44383A3E
+DATA 4, 0x021b4848, 0x3C3C3846
+DATA 4, 0x021b0850, 0x2e303230
+DATA 4, 0x021b4850, 0x38283E34
+DATA 4, 0x021b081c, 0x33333333
+DATA 4, 0x021b0820, 0x33333333
+DATA 4, 0x021b0824, 0x33333333
+DATA 4, 0x021b0828, 0x33333333
+DATA 4, 0x021b481c, 0x33333333
+DATA 4, 0x021b4820, 0x33333333
+DATA 4, 0x021b4824, 0x33333333
+DATA 4, 0x021b4828, 0x33333333
+DATA 4, 0x021b08c0, 0x24912489
+DATA 4, 0x021b48c0, 0x24914452
+DATA 4, 0x021b08b8, 0x00000800
+DATA 4, 0x021b48b8, 0x00000800
+DATA 4, 0x021b0004, 0x00020036
+DATA 4, 0x021b0008, 0x24444040
+DATA 4, 0x021b000c, 0x555A7955
+DATA 4, 0x021b0010, 0xFF320F64
+DATA 4, 0x021b0014, 0x01ff00db
+DATA 4, 0x021b0018, 0x00011740
+DATA 4, 0x021b001c, 0x00008000
+DATA 4, 0x021b002c, 0x000026d2
+DATA 4, 0x021b0030, 0x005A1023
+DATA 4, 0x021b0040, 0x00000027
+DATA 4, 0x021b0400, 0x10420000
+DATA 4, 0x021b0000, 0x831A0000
+DATA 4, 0x021b0890, 0x00400C58
+DATA 4, 0x021b001c, 0x04088032
+DATA 4, 0x021b001c, 0x00008033
+DATA 4, 0x021b001c, 0x00048031
+DATA 4, 0x021b001c, 0x09408030
+DATA 4, 0x021b001c, 0x04008040
+DATA 4, 0x021b0020, 0x00005800
+DATA 4, 0x021b0818, 0x00011117
+DATA 4, 0x021b4818, 0x00011117
+DATA 4, 0x021b0004, 0x00025576
+DATA 4, 0x021b0404, 0x00011006
+DATA 4, 0x021b001c, 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFF000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0x00FFF300
+DATA 4, 0x020c407c, 0x0F0000F3
+DATA 4, 0x020c4080, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+DATA 4, 0x020e0018, 0x77177717
+DATA 4, 0x020e001c, 0x77177717
+#endif
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 8c352308553..238f3b3d2a9 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
  *
  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  */
@@ -16,6 +17,7 @@
 #include <asm/mach-imx/spi.h>
 #include <env.h>
 #include <linux/errno.h>
+#include <linux/delay.h>
 #include <asm/gpio.h>
 #include <asm/mach-imx/mxc_i2c.h>
 #include <asm/mach-imx/iomux-v3.h>
@@ -35,6 +37,18 @@
 #include "../common/pfuze.h"
 #include <usb.h>
 #include <usb/ehci-ci.h>
+#include <asm/arch/mx6-ddr.h>
+#include <power/regulator.h>
+#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
+#include <lcd.h>
+#include <mxc_epdc_fb.h>
+#endif
+#ifdef CONFIG_FSL_FASTBOOT
+#include <fb_fsl.h>
+#ifdef CONFIG_ANDROID_RECOVERY
+#include <recovery.h>
+#endif
+#endif /*CONFIG_FSL_FASTBOOT*/
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -53,12 +67,18 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 
+#define EPDC_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+
 #define I2C_PMIC	1
 
 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
 
-#define DISP0_PWR_EN	IMX_GPIO_NR(1, 21)
-
 #define KEY_VOL_UP	IMX_GPIO_NR(1, 4)
 
 int dram_init(void)
@@ -72,47 +92,7 @@ static iomux_v3_cfg_t const uart1_pads[] = {
 	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 };
 
-static iomux_v3_cfg_t const usdhc2_pads[] = {
-	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02	| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
-	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
-};
-
-static iomux_v3_cfg_t const usdhc4_pads[] = {
-	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
+#ifdef CONFIG_MXC_SPI
 static iomux_v3_cfg_t const ecspi1_pads[] = {
 	IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 	IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
@@ -120,6 +100,12 @@ static iomux_v3_cfg_t const ecspi1_pads[] = {
 	IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 
+static void setup_spi(void)
+{
+	SETUP_IOMUX_PADS(ecspi1_pads);
+}
+#endif
+
 static iomux_v3_cfg_t const rgb_pads[] = {
 	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
 	IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
@@ -158,9 +144,20 @@ static iomux_v3_cfg_t const bl_pads[] = {
 
 static void enable_backlight(void)
 {
+	struct gpio_desc desc;
+	int ret;
+
 	SETUP_IOMUX_PADS(bl_pads);
-	gpio_request(DISP0_PWR_EN, "Display Power Enable");
-	gpio_direction_output(DISP0_PWR_EN, 1);
+
+	ret = dm_gpio_lookup_name("GPIO1_21", &desc);
+	if (ret)
+		return;
+
+	ret = dm_gpio_request(&desc, "Display Power Enable");
+	if (ret)
+		return;
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 }
 
 static void enable_rgb(struct display_info_t const *dev)
@@ -174,36 +171,20 @@ static void enable_lvds(struct display_info_t const *dev)
 	enable_backlight();
 }
 
-static struct i2c_pads_info mx6q_i2c_pad_info1 = {
+#ifdef CONFIG_SYS_I2C_LEGACY
+static struct i2c_pads_info i2c_pad_info1 = {
 	.scl = {
-		.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
-		.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
+		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
+		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 		.gp = IMX_GPIO_NR(4, 12)
 	},
 	.sda = {
-		.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
-		.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 		.gp = IMX_GPIO_NR(4, 13)
 	}
 };
-
-static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
-		.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
-		.gp = IMX_GPIO_NR(4, 12)
-	},
-	.sda = {
-		.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
-		.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
-		.gp = IMX_GPIO_NR(4, 13)
-	}
-};
-
-static void setup_spi(void)
-{
-	SETUP_IOMUX_PADS(ecspi1_pads);
-}
+#endif
 
 iomux_v3_cfg_t const di0_pads[] = {
 	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),	/* DISP0_CLK */
@@ -216,7 +197,97 @@ static void setup_iomux_uart(void)
 	SETUP_IOMUX_PADS(uart1_pads);
 }
 
+#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
+static iomux_v3_cfg_t const epdc_enable_pads[] = {
+	IOMUX_PADS(PAD_EIM_A16__EPDC_DATA00	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA10__EPDC_DATA01	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA12__EPDC_DATA02	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA11__EPDC_DATA03	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_LBA__EPDC_DATA04	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_EB2__EPDC_DATA05	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_CS0__EPDC_DATA06	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_RW__EPDC_DATA07	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A21__EPDC_GDCLK	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A22__EPDC_GDSP	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A23__EPDC_GDOE	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A24__EPDC_GDRL	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D31__EPDC_SDCLK_P	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D27__EPDC_SDOE	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA1__EPDC_SDLE	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_EB1__EPDC_SDSHR	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA2__EPDC_BDR0	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA4__EPDC_SDCE0	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA5__EPDC_SDCE1	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA6__EPDC_SDCE2	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const epdc_disable_pads[] = {
+	IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22),
+	IOMUX_PADS(PAD_EIM_DA10__GPIO3_IO10),
+	IOMUX_PADS(PAD_EIM_DA12__GPIO3_IO12),
+	IOMUX_PADS(PAD_EIM_DA11__GPIO3_IO11),
+	IOMUX_PADS(PAD_EIM_LBA__GPIO2_IO27),
+	IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30),
+	IOMUX_PADS(PAD_EIM_CS0__GPIO2_IO23),
+	IOMUX_PADS(PAD_EIM_RW__GPIO2_IO26),
+	IOMUX_PADS(PAD_EIM_A21__GPIO2_IO17),
+	IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16),
+	IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06),
+	IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04),
+	IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31),
+	IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27),
+	IOMUX_PADS(PAD_EIM_DA1__GPIO3_IO01),
+	IOMUX_PADS(PAD_EIM_EB1__GPIO2_IO29),
+	IOMUX_PADS(PAD_EIM_DA2__GPIO3_IO02),
+	IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04),
+	IOMUX_PADS(PAD_EIM_DA5__GPIO3_IO05),
+	IOMUX_PADS(PAD_EIM_DA6__GPIO3_IO06),
+};
+#endif
+
 #ifdef CONFIG_FSL_ESDHC_IMX
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02	| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 	{USDHC2_BASE_ADDR},
 	{USDHC3_BASE_ADDR},
@@ -226,11 +297,6 @@ struct fsl_esdhc_cfg usdhc_cfg[3] = {
 #define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 2)
 #define USDHC3_CD_GPIO	IMX_GPIO_NR(2, 0)
 
-int board_mmc_get_env_dev(int devno)
-{
-	return devno - 1;
-}
-
 int board_mmc_getcd(struct mmc *mmc)
 {
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
@@ -288,20 +354,27 @@ int board_mmc_init(struct bd_info *bis)
 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 }
 #endif
+#endif
 
 static int ar8031_phy_fixup(struct phy_device *phydev)
 {
 	unsigned short val;
 
 	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+	if (!is_mx6dqp()) {
+		phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+		val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+		val &= 0xffe3;
+		val |= 0x18;
+		phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+	}
 
-	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
-	val &= 0xffe3;
-	val |= 0x18;
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+	/* set the IO voltage to 1.8v */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
 
 	/* introduce tx clock delay */
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
@@ -322,6 +395,227 @@ int board_phy_config(struct phy_device *phydev)
 	return 0;
 }
 
+#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
+vidinfo_t panel_info = {
+	.vl_refresh = 85,
+	.vl_col = 800,
+	.vl_row = 600,
+	.vl_pixclock = 26666667,
+	.vl_left_margin = 8,
+	.vl_right_margin = 100,
+	.vl_upper_margin = 4,
+	.vl_lower_margin = 8,
+	.vl_hsync = 4,
+	.vl_vsync = 1,
+	.vl_sync = 0,
+	.vl_mode = 0,
+	.vl_flag = 0,
+	.vl_bpix = 3,
+	.cmap = 0,
+};
+
+struct epdc_timing_params panel_timings = {
+	.vscan_holdoff = 4,
+	.sdoed_width = 10,
+	.sdoed_delay = 20,
+	.sdoez_width = 10,
+	.sdoez_delay = 20,
+	.gdclk_hp_offs = 419,
+	.gdsp_offs = 20,
+	.gdoe_offs = 0,
+	.gdclk_offs = 5,
+	.num_ce = 1,
+};
+
+static iomux_v3_cfg_t const epdc_pwr_ctrl_pads[] = {
+	IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D17__GPIO3_IO17	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A18__GPIO2_IO20	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+};
+
+struct gpio_desc epd_pwrstat_desc;
+struct gpio_desc epd_vcom_desc;
+struct gpio_desc epd_wakeup_desc;
+struct gpio_desc epd_pwr_ctl0_desc;
+
+static void setup_epdc_power(void)
+{
+	int ret;
+
+	SETUP_IOMUX_PADS(epdc_pwr_ctrl_pads);
+
+	/* Setup epdc voltage */
+
+	/* EIM_A17 - GPIO2[21] for PWR_GOOD status */
+	/* Set as input */
+	ret = dm_gpio_lookup_name("GPIO2_21", &epd_pwrstat_desc);
+	if (ret) {
+		printf("%s lookup GPIO2_21 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&epd_pwrstat_desc, "EPDC PWRSTAT");
+	if (ret) {
+		printf("%s request EPDC PWRSTAT failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&epd_pwrstat_desc, GPIOD_IS_IN);
+
+	/* EIM_D17 - GPIO3[17] for VCOM control */
+	/* Set as output */
+	ret = dm_gpio_lookup_name("GPIO3_17", &epd_vcom_desc);
+	if (ret) {
+		printf("%s lookup GPIO3_17 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&epd_vcom_desc, "EPDC VCOM0");
+	if (ret) {
+		printf("%s request EPDC VCOM0 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&epd_vcom_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	/* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */
+	/* Set as output */
+	ret = dm_gpio_lookup_name("GPIO3_20", &epd_wakeup_desc);
+	if (ret) {
+		printf("%s lookup GPIO3_20 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&epd_wakeup_desc, "EPDC PWR WAKEUP");
+	if (ret) {
+		printf("%s request EPDC PWR WAKEUP failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&epd_wakeup_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	/* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */
+	/* Set as output */
+	ret = dm_gpio_lookup_name("GPIO2_20", &epd_pwr_ctl0_desc);
+	if (ret) {
+		printf("%s lookup GPIO2_20 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&epd_pwr_ctl0_desc, "EPDC PWR CTRL0");
+	if (ret) {
+		printf("%s request EPDC PWR CTRL0 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&epd_pwr_ctl0_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+}
+
+static void epdc_enable_pins(void)
+{
+	/* epdc iomux settings */
+	SETUP_IOMUX_PADS(epdc_enable_pads);
+}
+
+static void epdc_disable_pins(void)
+{
+	/* Configure MUX settings for EPDC pins to GPIO */
+	SETUP_IOMUX_PADS(epdc_disable_pads);
+}
+
+static void setup_epdc(void)
+{
+	unsigned int reg;
+	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/*** Set pixel clock rates for EPDC ***/
+
+	/* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */
+	reg = readl(&ccm_regs->cscdr3);
+	reg &= ~0x7C000;
+	reg |= (1 << 16) | (1 << 14);
+	writel(reg, &ccm_regs->cscdr3);
+
+	/* EPDC AXI clk enable */
+	reg = readl(&ccm_regs->CCGR3);
+	reg |= 0x00C0;
+	writel(reg, &ccm_regs->CCGR3);
+
+	/* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */
+	reg = readl(&ccm_regs->cscdr2);
+	reg &= ~0x3FE00;
+	reg |= (2 << 15) | (5 << 12);
+	writel(reg, &ccm_regs->cscdr2);
+
+	/* PLL5 enable (defaults to 650) */
+	reg = readl(&ccm_regs->analog_pll_video);
+	reg &= ~((1 << 16) | (1 << 12));
+	reg |= (1 << 13);
+	writel(reg, &ccm_regs->analog_pll_video);
+
+	/* EPDC PIX clk enable */
+	reg = readl(&ccm_regs->CCGR3);
+	reg |= 0x0C00;
+	writel(reg, &ccm_regs->CCGR3);
+
+	panel_info.epdc_data.wv_modes.mode_init = 0;
+	panel_info.epdc_data.wv_modes.mode_du = 1;
+	panel_info.epdc_data.wv_modes.mode_gc4 = 3;
+	panel_info.epdc_data.wv_modes.mode_gc8 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc16 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc32 = 2;
+
+	panel_info.epdc_data.epdc_timings = panel_timings;
+
+	setup_epdc_power();
+}
+
+void epdc_power_on(void)
+{
+	unsigned int reg;
+	struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
+
+	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
+	dm_gpio_set_value(&epd_pwr_ctl0_desc, 1);
+	udelay(1000);
+
+	/* Enable epdc signal pin */
+	epdc_enable_pins();
+
+	/* Set PMIC Wakeup to high - enable Display power */
+	dm_gpio_set_value(&epd_wakeup_desc, 1);
+
+	/* Wait for PWRGOOD == 1 */
+	while (1) {
+		reg = readl(&gpio_regs->gpio_psr);
+		if (!(reg & (1 << 21)))
+			break;
+
+		udelay(100);
+	}
+
+	/* Enable VCOM */
+	dm_gpio_set_value(&epd_vcom_desc, 1);
+
+	udelay(500);
+}
+
+void epdc_power_off(void)
+{
+	/* Set PMIC Wakeup to low - disable Display power */
+	dm_gpio_set_value(&epd_wakeup_desc, 0);
+
+	/* Disable VCOM */
+	dm_gpio_set_value(&epd_vcom_desc, 0);
+
+	epdc_disable_pins();
+
+	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
+	dm_gpio_set_value(&epd_pwr_ctl0_desc, 0);
+}
+#endif
+
 #if defined(CONFIG_VIDEO_IPUV3)
 static void disable_lvds(struct display_info_t const *dev)
 {
@@ -365,21 +659,21 @@ struct display_info_t const displays[] = {{
 	.bus	= -1,
 	.addr	= 0,
 	.pixfmt	= IPU_PIX_FMT_RGB24,
-	.detect	= detect_hdmi,
+	.detect	= NULL,
 	.enable	= do_enable_hdmi,
 	.mode	= {
 		.name           = "HDMI",
 		.refresh        = 60,
-		.xres           = 1024,
-		.yres           = 768,
-		.pixclock       = 15384,
-		.left_margin    = 160,
-		.right_margin   = 24,
-		.upper_margin   = 29,
-		.lower_margin   = 3,
-		.hsync_len      = 136,
-		.vsync_len      = 6,
-		.sync           = FB_SYNC_EXT,
+		.xres           = 640,
+		.yres           = 480,
+		.pixclock       = 39721,
+		.left_margin    = 48,
+		.right_margin   = 16,
+		.upper_margin   = 33,
+		.lower_margin   = 10,
+		.hsync_len      = 96,
+		.vsync_len      = 2,
+		.sync           = 0,
 		.vmode          = FB_VMODE_NONINTERLACED
 } }, {
 	.bus	= 0,
@@ -469,20 +763,46 @@ int overwrite_console(void)
 	return 1;
 }
 
+static void setup_fec(void)
+{
+	if (is_mx6dqp()) {
+		int ret;
+
+		/* select ENET MAC0 TX clock from PLL */
+		imx_iomux_set_gpr_register(5, 9, 1, 1);
+		ret = enable_fec_anatop_clock(0, ENET_125MHZ);
+		if (ret)
+		    printf("Error fec anatop clock settings!\n");
+	}
+}
+
 #ifdef CONFIG_USB_EHCI_MX6
-static void setup_usb(void)
+int board_ehci_hcd_init(int port)
 {
-	/*
-	 * set daisy chain for otg_pin_id on 6q.
-	 * for 6dl, this bit is reserved
-	 */
-	imx_iomux_set_gpr_register(1, 13, 1, 0);
+	switch (port) {
+	case 0:
+		/*
+		  * Set daisy chain for otg_pin_id on 6q.
+		 *  For 6dl, this bit is reserved.
+		 */
+		imx_iomux_set_gpr_register(1, 13, 1, 0);
+		break;
+	case 1:
+		break;
+	default:
+		printf("MXC USB port %d not yet supported\n", port);
+		return -EINVAL;
+	}
+	return 0;
 }
 #endif
 
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
 
 	return 0;
 }
@@ -492,58 +812,392 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#if defined(CONFIG_DM_REGULATOR)
+	regulators_enable_boot_on(false);
+#endif
+
 #ifdef CONFIG_MXC_SPI
 	setup_spi();
 #endif
-	if (is_mx6dq() || is_mx6dqp())
-		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
-	else
-		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
-#if defined(CONFIG_VIDEO_IPUV3)
-	setup_display();
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 #endif
-#ifdef CONFIG_USB_EHCI_MX6
-	setup_usb();
+
+#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
+	setup_epdc();
 #endif
 
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_POWER_LEGACY
+int power_init_board(void)
+{
+	struct pmic *pfuze;
+	unsigned int reg;
+	int ret;
+
+	pfuze = pfuze_common_init(I2C_PMIC);
+	if (!pfuze)
+		return -ENODEV;
+
+	if (is_mx6dqp())
+		ret = pfuze_mode_init(pfuze, APS_APS);
+	else
+		ret = pfuze_mode_init(pfuze, APS_PFM);
+
+	if (ret < 0)
+		return ret;
+	/* VGEN3 and VGEN5 corrected on i.mx6qp board */
+	if (!is_mx6dqp()) {
+		/* Increase VGEN3 from 2.5 to 2.8V */
+		pmic_reg_read(pfuze, PFUZE100_VGEN3VOL, &reg);
+		reg &= ~LDO_VOL_MASK;
+		reg |= LDOB_2_80V;
+		pmic_reg_write(pfuze, PFUZE100_VGEN3VOL, reg);
+
+		/* Increase VGEN5 from 2.8 to 3V */
+		pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &reg);
+		reg &= ~LDO_VOL_MASK;
+		reg |= LDOB_3_00V;
+		pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg);
+	}
+
+	if (is_mx6dqp()) {
+		/* set SW1C staby volatage 1.075V*/
+		pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);
+		reg &= ~0x3f;
+		reg |= 0x1f;
+		pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
+
+		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+		pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
+
+		/* set SW2/VDDARM staby volatage 0.975V*/
+		pmic_reg_read(pfuze, PFUZE100_SW2STBY, &reg);
+		reg &= ~0x3f;
+		reg |= 0x17;
+		pmic_reg_write(pfuze, PFUZE100_SW2STBY, reg);
+
+		/* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */
+		pmic_reg_read(pfuze, PFUZE100_SW2CONF, &reg);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(pfuze, PFUZE100_SW2CONF, reg);
+	} else {
+		/* set SW1AB staby volatage 0.975V*/
+		pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &reg);
+		reg &= ~0x3f;
+		reg |= 0x1b;
+		pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);
+
+		/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+		pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &reg);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);
+
+		/* set SW1C staby volatage 0.975V*/
+		pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);
+		reg &= ~0x3f;
+		reg |= 0x1b;
+		pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
+
+		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+		pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
+	}
+
 	return 0;
 }
 
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
 int power_init_board(void)
 {
-	struct pmic *p;
+	struct udevice *dev;
 	unsigned int reg;
 	int ret;
 
-	p = pfuze_common_init(I2C_PMIC);
-	if (!p)
+	dev = pfuze_common_init();
+	if (!dev)
 		return -ENODEV;
 
-	ret = pfuze_mode_init(p, APS_PFM);
+	if (is_mx6dqp())
+		ret = pfuze_mode_init(dev, APS_APS);
+	else
+		ret = pfuze_mode_init(dev, APS_PFM);
 	if (ret < 0)
 		return ret;
 
-	/* Increase VGEN3 from 2.5 to 2.8V */
-	pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
-	reg &= ~LDO_VOL_MASK;
-	reg |= LDOB_2_80V;
-	pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
+	/* VGEN3 and VGEN5 corrected on i.mx6qp board */
+	if (!is_mx6dqp()) {
+		/* Increase VGEN3 from 2.5 to 2.8V */
+		reg = pmic_reg_read(dev, PFUZE100_VGEN3VOL);
+		reg &= ~LDO_VOL_MASK;
+		reg |= LDOB_2_80V;
+		pmic_reg_write(dev, PFUZE100_VGEN3VOL, reg);
+
+		/* Increase VGEN5 from 2.8 to 3V */
+		reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
+		reg &= ~LDO_VOL_MASK;
+		reg |= LDOB_3_00V;
+		pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
+	}
 
-	/* Increase VGEN5 from 2.8 to 3V */
-	pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
-	reg &= ~LDO_VOL_MASK;
-	reg |= LDOB_3_00V;
-	pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
+	if (is_mx6dqp()) {
+		/* set SW1C staby volatage 1.075V*/
+		reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
+		reg &= ~0x3f;
+		reg |= 0x1f;
+		pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
+
+		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+		reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
+
+		/* set SW2/VDDARM staby volatage 0.975V*/
+		reg = pmic_reg_read(dev, PFUZE100_SW2STBY);
+		reg &= ~0x3f;
+		reg |= 0x17;
+		pmic_reg_write(dev, PFUZE100_SW2STBY, reg);
+
+		/* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */
+		reg = pmic_reg_read(dev, PFUZE100_SW2CONF);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(dev, PFUZE100_SW2CONF, reg);
+	} else {
+		/* set SW1AB staby volatage 0.975V*/
+		reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
+		reg &= ~0x3f;
+		reg |= 0x1b;
+		pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
+
+		/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+		reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
+
+		/* set SW1C staby volatage 0.975V*/
+		reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
+		reg &= ~0x3f;
+		reg |= 0x1b;
+		pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
+
+		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+		reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
+	}
 
 	return 0;
 }
+#endif
 
-#ifdef CONFIG_MXC_SPI
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
+#ifdef CONFIG_LDO_BYPASS_CHECK
+#ifdef CONFIG_POWER_LEGACY
+void ldo_mode_set(int ldo_bypass)
 {
-	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
+	unsigned int value;
+	int is_400M;
+	unsigned char vddarm;
+	struct pmic *p = pmic_get("PFUZE100");
+
+	if (!p) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* increase VDDARM/VDDSOC to support 1.2G chip */
+	if (check_1_2G()) {
+		ldo_bypass = 0;	/* ldo_enable on 1.2G chip */
+		printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
+		if (is_mx6dqp()) {
+			/* increase VDDARM to 1.425V */
+			pmic_reg_read(p, PFUZE100_SW2VOL, &value);
+			value &= ~0x3f;
+			value |= 0x29;
+			pmic_reg_write(p, PFUZE100_SW2VOL, value);
+		} else {
+			/* increase VDDARM to 1.425V */
+			pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+			value &= ~0x3f;
+			value |= 0x2d;
+			pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+		}
+		/* increase VDDSOC to 1.425V */
+		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+		value &= ~0x3f;
+		value |= 0x2d;
+		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+	}
+	/* switch to ldo_bypass mode , boot on 800Mhz */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+		if (is_mx6dqp()) {
+			/* decrease VDDARM for 400Mhz DQP:1.1V*/
+			pmic_reg_read(p, PFUZE100_SW2VOL, &value);
+			value &= ~0x3f;
+			value |= 0x1c;
+			pmic_reg_write(p, PFUZE100_SW2VOL, value);
+		} else {
+			/* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
+			pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+			value &= ~0x3f;
+			if (is_mx6dl())
+				value |= 0x27;
+			else
+				value |= 0x20;
+
+			pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+		}
+		/* increase VDDSOC to 1.3V */
+		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+		value &= ~0x3f;
+		value |= 0x28;
+		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+		/*
+		 * MX6Q/DQP:
+		 * VDDARM:1.15V@800M; VDDSOC:1.175V@800M
+		 * VDDARM:0.975V@400M; VDDSOC:1.175V@400M
+		 * MX6DL:
+		 * VDDARM:1.175V@800M; VDDSOC:1.175V@800M
+		 * VDDARM:1.15V@400M; VDDSOC:1.175V@400M
+		 */
+		is_400M = set_anatop_bypass(2);
+		if (is_mx6dqp()) {
+			pmic_reg_read(p, PFUZE100_SW2VOL, &value);
+			value &= ~0x3f;
+			if (is_400M)
+				value |= 0x17;
+			else
+				value |= 0x1e;
+			pmic_reg_write(p, PFUZE100_SW2VOL, value);
+		}
+
+		if (is_400M) {
+			if (is_mx6dl())
+				vddarm = 0x22;
+			else
+				vddarm = 0x1b;
+		} else {
+			if (is_mx6dl())
+				vddarm = 0x23;
+			else
+				vddarm = 0x22;
+		}
+		pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+		value &= ~0x3f;
+		value |= vddarm;
+		pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+
+		/* decrease VDDSOC to 1.175V */
+		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+		value &= ~0x3f;
+		value |= 0x23;
+		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+		finish_anatop_bypass();
+		printf("switch to ldo_bypass mode!\n");
+	}
+}
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+void ldo_mode_set(int ldo_bypass)
+{
+	int is_400M;
+	unsigned char vddarm;
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("pfuze100@8", &dev);
+	if (ret == -ENODEV) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* increase VDDARM/VDDSOC to support 1.2G chip */
+	if (check_1_2G()) {
+		ldo_bypass = 0; /* ldo_enable on 1.2G chip */
+		printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
+		if (is_mx6dqp()) {
+			/* increase VDDARM to 1.425V */
+			pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x29);
+		} else {
+			/* increase VDDARM to 1.425V */
+			pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x2d);
+		}
+		/* increase VDDSOC to 1.425V */
+		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x2d);
+	}
+	/* switch to ldo_bypass mode , boot on 800Mhz */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+		if (is_mx6dqp()) {
+			/* decrease VDDARM for 400Mhz DQP:1.1V*/
+			pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x1c);
+		} else {
+			/* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
+			if (is_mx6dl())
+				pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x27);
+			else
+				pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x20);
+		}
+		/* increase VDDSOC to 1.3V */
+		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x28);
+
+		/*
+		 * MX6Q/DQP:
+		 * VDDARM:1.15V@800M; VDDSOC:1.175V@800M
+		 * VDDARM:0.975V@400M; VDDSOC:1.175V@400M
+		 * MX6DL:
+		 * VDDARM:1.175V@800M; VDDSOC:1.175V@800M
+		 * VDDARM:1.15V@400M; VDDSOC:1.175V@400M
+		 */
+		is_400M = set_anatop_bypass(2);
+		if (is_mx6dqp()) {
+			if (is_400M)
+				pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x17);
+			else
+				pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x1e);
+		}
+
+		if (is_400M) {
+			if (is_mx6dl())
+				vddarm = 0x22;
+			else
+				vddarm = 0x1b;
+		} else {
+			if (is_mx6dl())
+				vddarm = 0x23;
+			else
+				vddarm = 0x22;
+		}
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
+
+		/* decrease VDDSOC to 1.175V */
+		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x23);
+
+		finish_anatop_bypass();
+		printf("switch to ldo_bypass mode!\n");
+	}
 }
 #endif
+#endif
 
 #ifdef CONFIG_CMD_BMODE
 static const struct boot_mode board_boot_modes[] = {
@@ -562,6 +1216,11 @@ int board_late_init(void)
 	add_board_boot_modes(board_boot_modes);
 #endif
 
+	env_set("tee", "no");
+#ifdef CONFIG_IMX_OPTEE
+	env_set("tee", "yes");
+#endif
+
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	env_set("board_name", "SABRESD");
 
@@ -573,9 +1232,56 @@ int board_late_init(void)
 		env_set("board_rev", "MX6DL");
 #endif
 
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
 	return 0;
 }
 
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+
+#define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5)
+iomux_v3_cfg_t const recovery_key_pads[] = {
+	IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+int is_recovery_key_pressing(void)
+{
+	int button_pressed = 0;
+	int ret;
+	struct gpio_desc desc;
+
+	/* Check Recovery Combo Button press or not. */
+	SETUP_IOMUX_PADS(recovery_key_pads);
+
+	ret = dm_gpio_lookup_name("GPIO1_5", &desc);
+	if (ret) {
+		printf("%s lookup GPIO1_5 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "volume_dn_key");
+	if (ret) {
+		printf("%s request volume_dn_key failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN);
+
+	if (dm_gpio_get_value(&desc) == 0) { /* VOL_DN key is low assert */
+		button_pressed = 1;
+		printf("Recovery key pressed\n");
+	}
+
+	return  button_pressed;
+}
+
+#endif /*CONFIG_ANDROID_RECOVERY*/
+
+#endif /*CONFIG_FSL_FASTBOOT*/
+
 #ifdef CONFIG_SPL_BUILD
 #include <asm/arch/mx6-ddr.h>
 #include <spl.h>
diff --git a/board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg b/board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg
new file mode 100644
index 00000000000..b0ab501a63b
--- /dev/null
+++ b/board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+#ifdef CONFIG_IMX_OPTEE
+SET_BIT 4 0x20c4070 0x3c00000
+DATA 4 0x20e0024 0x00000003
+CHECK_BITS_SET 4 0x20e0024 0x3
+#endif
+DATA 4, 0x020e0774, 0x000C0000
+DATA 4, 0x020e0754, 0x00000000
+DATA 4, 0x020e04ac, 0x00000030
+DATA 4, 0x020e04b0, 0x00000030
+DATA 4, 0x020e0464, 0x00000030
+DATA 4, 0x020e0490, 0x00000030
+DATA 4, 0x020e074c, 0x00000030
+DATA 4, 0x020e0494, 0x00000030
+DATA 4, 0x020e04a0, 0x00000000
+DATA 4, 0x020e04b4, 0x00000030
+DATA 4, 0x020e04b8, 0x00000030
+DATA 4, 0x020e076c, 0x00000030
+DATA 4, 0x020e0750, 0x00020000
+DATA 4, 0x020e04bc, 0x00000030
+DATA 4, 0x020e04c0, 0x00000030
+DATA 4, 0x020e04c4, 0x00000030
+DATA 4, 0x020e04c8, 0x00000030
+DATA 4, 0x020e0760, 0x00020000
+DATA 4, 0x020e0764, 0x00000030
+DATA 4, 0x020e0770, 0x00000030
+DATA 4, 0x020e0778, 0x00000030
+DATA 4, 0x020e077c, 0x00000030
+DATA 4, 0x020e0470, 0x00000030
+DATA 4, 0x020e0474, 0x00000030
+DATA 4, 0x020e0478, 0x00000030
+DATA 4, 0x020e047c, 0x00000030
+DATA 4, 0x021b0800, 0xa1390003
+DATA 4, 0x021b080c, 0x001F001F
+DATA 4, 0x021b0810, 0x001F001F
+DATA 4, 0x021b083c, 0x42190219
+DATA 4, 0x021b0840, 0x017B0177
+DATA 4, 0x021b0848, 0x4B4D4E4D
+DATA 4, 0x021b0850, 0x3F3E2D36
+DATA 4, 0x021b081c, 0x33333333
+DATA 4, 0x021b0820, 0x33333333
+DATA 4, 0x021b0824, 0x33333333
+DATA 4, 0x021b0828, 0x33333333
+DATA 4, 0x021b08b8, 0x00000800
+DATA 4, 0x021b0004, 0x0002002D
+DATA 4, 0x021b0008, 0x00333030
+DATA 4, 0x021b000c, 0x3F435313
+DATA 4, 0x021b0010, 0xB66E8B63
+DATA 4, 0x021b0014, 0x01FF00DB
+DATA 4, 0x021b0018, 0x00001740
+DATA 4, 0x021b001c, 0x00008000
+DATA 4, 0x021b002c, 0x000026d2
+DATA 4, 0x021b0030, 0x00431023
+DATA 4, 0x021b0040, 0x00000017
+DATA 4, 0x021b0000, 0x83190000
+DATA 4, 0x021b001c, 0x04008032
+DATA 4, 0x021b001c, 0x00008033
+DATA 4, 0x021b001c, 0x00048031
+DATA 4, 0x021b001c, 0x05208030
+DATA 4, 0x021b001c, 0x04008040
+DATA 4, 0x021b0020, 0x00005800
+DATA 4, 0x021b0818, 0x00011117
+DATA 4, 0x021b0004, 0x0002556D
+DATA 4, 0x021b0404, 0x00011006
+DATA 4, 0x021b001c, 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFF000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0x00FFF300
+DATA 4, 0x020c407c, 0x0F0000C3
+DATA 4, 0x020c4080, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, 0x020e0018, 0x007F007F
+DATA 4, 0x020e001c, 0x007F007F
+#endif
diff --git a/board/freescale/mx6sabresd/plugin.S b/board/freescale/mx6sabresd/plugin.S
new file mode 100644
index 00000000000..d99349f48e0
--- /dev/null
+++ b/board/freescale/mx6sabresd/plugin.S
@@ -0,0 +1,690 @@
+/*
+ * Copyright (C) 2012-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6dqpsabresd_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x798]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x758]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x588]
+	str r1, [r0, #0x594]
+	str r1, [r0, #0x56c]
+	str r1, [r0, #0x578]
+	str r1, [r0, #0x74c]
+	str r1, [r0, #0x57c]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x58c]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x59c]
+	str r1, [r0, #0x5a0]
+	str r1, [r0, #0x78c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x5a8]
+	str r1, [r0, #0x5b0]
+	str r1, [r0, #0x524]
+	str r1, [r0, #0x51c]
+	str r1, [r0, #0x518]
+	str r1, [r0, #0x50c]
+	str r1, [r0, #0x5b8]
+	str r1, [r0, #0x5c0]
+
+	ldr r1, =0x00018200
+	str r1, [r0, #0x534]
+	ldr r1, =0x00008000
+	str r1, [r0, #0x538]
+	ldr r1, =0x00018200
+	str r1, [r0, #0x53c]
+	str r1, [r0, #0x540]
+	str r1, [r0, #0x544]
+	str r1, [r0, #0x548]
+	str r1, [r0, #0x54c]
+	str r1, [r0, #0x550]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x774]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x784]
+	str r1, [r0, #0x788]
+	str r1, [r0, #0x794]
+	str r1, [r0, #0x79c]
+	str r1, [r0, #0x7a0]
+	str r1, [r0, #0x7a4]
+	str r1, [r0, #0x7a8]
+	str r1, [r0, #0x748]
+	str r1, [r0, #0x5ac]
+	str r1, [r0, #0x5b4]
+	str r1, [r0, #0x528]
+	str r1, [r0, #0x520]
+	str r1, [r0, #0x514]
+	str r1, [r0, #0x510]
+	str r1, [r0, #0x5bc]
+	str r1, [r0, #0x5c4]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x001b001e
+	str r2, [r0, #0x80c]
+	ldr r2, =0x002e0029
+	str r2, [r0, #0x810]
+
+	ldr r1, =MMDC_P1_BASE_ADDR
+	ldr r2, =0x001b002a
+	str r2, [r1, #0x80c]
+	ldr r2, =0x0019002c
+	str r2, [r1, #0x810]
+
+	ldr r2, =0x43240334
+	str r2, [r0, #0x83c]
+	ldr r2, =0x0324031a
+	str r2, [r0, #0x840]
+
+	ldr r2, =0x43340344
+	str r2, [r1, #0x83c]
+	ldr r2, =0x03280276
+	str r2, [r1, #0x840]
+
+	ldr r2, =0x44383A3E
+	str r2, [r0, #0x848]
+	ldr r2, =0x3C3C3846
+	str r2, [r1, #0x848]
+
+	ldr r2, =0x2e303230
+	str r2, [r0, #0x850]
+	ldr r2, =0x38283E34
+	str r2, [r1, #0x850]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+	str r2, [r1, #0x81c]
+	str r2, [r1, #0x820]
+	str r2, [r1, #0x824]
+	str r2, [r1, #0x828]
+
+	ldr r2, =0x24912489
+	str r2, [r0, #0x8c0]
+	ldr r2, =0x24914452
+	str r2, [r1, #0x8c0]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x00020036
+	str r2, [r0, #0x004]
+	ldr r2, =0x24444040
+	str r2, [r0, #0x008]
+
+	ldr r2, =0x555A7955
+	str r2, [r0, #0x00c]
+	ldr r2, =0xFF320F64
+	str r2, [r0, #0x010]
+
+	ldr r2, =0x01FF00DB
+	str r2, [r0, #0x014]
+	ldr r2, =0x00011740
+	str r2, [r0, #0x018]
+
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x005A1023
+	str r2, [r0, #0x030]
+	ldr r2, =0x00000027
+	str r2, [r0, #0x040]
+
+	ldr r2, =0x14420000
+	str r2, [r0, #0x400]
+
+	ldr r2, =0x831A0000
+	str r2, [r0, #0x000]
+
+	ldr r2, =0x00400C58
+	str r2, [r0, #0x890]
+
+	ldr r3, =0x00bb0000
+	ldr r2, =0x00000000
+	str r2, [r3, #0x008]
+	ldr r2, =0x2891E41A
+	str r2, [r3, #0x00C]
+	ldr r2, =0x00000564
+	str r2, [r3, #0x038]
+	ldr r2, =0x00000040
+	str r2, [r3, #0x014]
+	ldr r2, =0x00000020
+	str r2, [r3, #0x028]
+	ldr r2, =0x00000020
+	str r2, [r3, #0x02c]
+
+	ldr r2, =0x04088032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00048031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x09408030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00005800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00011117
+	str r2, [r0, #0x818]
+	str r2, [r1, #0x818]
+	ldr r2, =0x00025576
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+.endm
+
+.macro imx6dqsabresd_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x798]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x758]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x588]
+	str r1, [r0, #0x594]
+	str r1, [r0, #0x56c]
+	str r1, [r0, #0x578]
+	str r1, [r0, #0x74c]
+	str r1, [r0, #0x57c]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x58c]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x59c]
+	str r1, [r0, #0x5a0]
+	str r1, [r0, #0x78c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x5a8]
+	str r1, [r0, #0x5b0]
+	str r1, [r0, #0x524]
+	str r1, [r0, #0x51c]
+	str r1, [r0, #0x518]
+	str r1, [r0, #0x50c]
+	str r1, [r0, #0x5b8]
+	str r1, [r0, #0x5c0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x774]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x784]
+	str r1, [r0, #0x788]
+	str r1, [r0, #0x794]
+	str r1, [r0, #0x79c]
+	str r1, [r0, #0x7a0]
+	str r1, [r0, #0x7a4]
+	str r1, [r0, #0x7a8]
+	str r1, [r0, #0x748]
+	str r1, [r0, #0x5ac]
+	str r1, [r0, #0x5b4]
+	str r1, [r0, #0x528]
+	str r1, [r0, #0x520]
+	str r1, [r0, #0x514]
+	str r1, [r0, #0x510]
+	str r1, [r0, #0x5bc]
+	str r1, [r0, #0x5c4]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x001F001F
+	str r2, [r0, #0x80c]
+	str r2, [r0, #0x810]
+	ldr r1, =MMDC_P1_BASE_ADDR
+	str r2, [r1, #0x80c]
+	str r2, [r1, #0x810]
+
+	ldr r2, =0x43270338
+	str r2, [r0, #0x83c]
+	ldr r2, =0x03200314
+	str r2, [r0, #0x840]
+
+	ldr r2, =0x431A032F
+	str r2, [r1, #0x83c]
+	ldr r2, =0x03200263
+	str r2, [r1, #0x840]
+
+	ldr r2, =0x4B434748
+	str r2, [r0, #0x848]
+	ldr r2, =0x4445404C
+	str r2, [r1, #0x848]
+
+	ldr r2, =0x38444542
+	str r2, [r0, #0x850]
+	ldr r2, =0x4935493A
+	str r2, [r1, #0x850]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+	str r2, [r1, #0x81c]
+	str r2, [r1, #0x820]
+	str r2, [r1, #0x824]
+	str r2, [r1, #0x828]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x00020036
+	str r2, [r0, #0x004]
+	ldr r2, =0x09444040
+	str r2, [r0, #0x008]
+
+	ldr r2, =0x555A7975
+	str r2, [r0, #0x00c]
+	ldr r2, =0xFF538F64
+	str r2, [r0, #0x010]
+
+	ldr r2, =0x01FF00DB
+	str r2, [r0, #0x014]
+	ldr r2, =0x00001740
+	str r2, [r0, #0x018]
+
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x005A1023
+	str r2, [r0, #0x030]
+	ldr r2, =0x00000027
+	str r2, [r0, #0x040]
+
+	ldr r2, =0x831A0000
+	str r2, [r0, #0x000]
+
+	ldr r2, =0x04088032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00048031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x09408030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00005800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00011117
+	str r2, [r0, #0x818]
+	str r2, [r1, #0x818]
+	ldr r2, =0x00025576
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+.endm
+
+.macro imx6dlsabresd_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x774]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x754]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4ac]
+	str r1, [r0, #0x4b0]
+	str r1, [r0, #0x464]
+	str r1, [r0, #0x490]
+	str r1, [r0, #0x74c]
+	str r1, [r0, #0x494]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4a0]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4b4]
+	str r1, [r0, #0x4b8]
+	str r1, [r0, #0x76c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4bc]
+	str r1, [r0, #0x4c0]
+	str r1, [r0, #0x4c4]
+	str r1, [r0, #0x4c8]
+	str r1, [r0, #0x4cc]
+	str r1, [r0, #0x4d0]
+	str r1, [r0, #0x4d4]
+	str r1, [r0, #0x4d8]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x760]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x764]
+	str r1, [r0, #0x770]
+	str r1, [r0, #0x778]
+	str r1, [r0, #0x77c]
+	str r1, [r0, #0x780]
+	str r1, [r0, #0x784]
+	str r1, [r0, #0x78c]
+	str r1, [r0, #0x748]
+	str r1, [r0, #0x470]
+	str r1, [r0, #0x474]
+	str r1, [r0, #0x478]
+	str r1, [r0, #0x47c]
+	str r1, [r0, #0x480]
+	str r1, [r0, #0x484]
+	str r1, [r0, #0x488]
+	str r1, [r0, #0x48c]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x001f001f
+	str r2, [r0, #0x80c]
+	str r2, [r0, #0x810]
+	ldr r1, =MMDC_P1_BASE_ADDR
+	str r2, [r1, #0x80c]
+	str r2, [r1, #0x810]
+
+	ldr r2, =0x4220021F
+	str r2, [r0, #0x83c]
+	ldr r2, =0x0207017E
+	str r2, [r0, #0x840]
+
+	ldr r2, =0x4201020C
+	str r2, [r1, #0x83c]
+	ldr r2, =0x01660172
+	str r2, [r1, #0x840]
+
+	ldr r2, =0x4A4D4E4D
+	str r2, [r0, #0x848]
+	ldr r2, =0x4A4F5049
+	str r2, [r1, #0x848]
+
+	ldr r2, =0x3F3C3D31
+	str r2, [r0, #0x850]
+	ldr r2, =0x3238372B
+	str r2, [r1, #0x850]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+	str r2, [r1, #0x81c]
+	str r2, [r1, #0x820]
+	str r2, [r1, #0x824]
+	str r2, [r1, #0x828]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x0002002D
+	str r2, [r0, #0x004]
+	ldr r2, =0x00333030
+	str r2, [r0, #0x008]
+
+	ldr r2, =0x3F435313
+	str r2, [r0, #0x00c]
+	ldr r2, =0xB66E8B63
+	str r2, [r0, #0x010]
+
+	ldr r2, =0x01FF00DB
+	str r2, [r0, #0x014]
+	ldr r2, =0x00001740
+	str r2, [r0, #0x018]
+
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x00431023
+	str r2, [r0, #0x030]
+	ldr r2, =0x00000027
+	str r2, [r0, #0x040]
+
+	ldr r2, =0x831A0000
+	str r2, [r0, #0x000]
+
+	ldr r2, =0x04008032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00048031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x05208030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00005800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00011117
+	str r2, [r0, #0x818]
+	str r2, [r1, #0x818]
+	ldr r2, =0x0002556D
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+.endm
+
+.macro imx6solosabresd_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x774]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x754]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4ac]
+	str r1, [r0, #0x4b0]
+	str r1, [r0, #0x464]
+	str r1, [r0, #0x490]
+	str r1, [r0, #0x74c]
+	str r1, [r0, #0x494]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4a0]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4b4]
+	str r1, [r0, #0x4b8]
+	str r1, [r0, #0x76c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4bc]
+	str r1, [r0, #0x4c0]
+	str r1, [r0, #0x4c4]
+	str r1, [r0, #0x4c8]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x760]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x764]
+	str r1, [r0, #0x770]
+	str r1, [r0, #0x778]
+	str r1, [r0, #0x77c]
+	str r1, [r0, #0x470]
+	str r1, [r0, #0x474]
+	str r1, [r0, #0x478]
+	str r1, [r0, #0x47c]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x001F001F
+	str r2, [r0, #0x80c]
+	str r2, [r0, #0x810]
+
+	ldr r2, =0x42190219
+	str r2, [r0, #0x83c]
+	ldr r2, =0x017B0177
+	str r2, [r0, #0x840]
+
+	ldr r2, =0x4B4D4E4D
+	str r2, [r0, #0x848]
+
+	ldr r2, =0x3F3E2D36
+	str r2, [r0, #0x850]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+
+	ldr r2, =0x0002002D
+	str r2, [r0, #0x004]
+	ldr r2, =0x00333030
+	str r2, [r0, #0x008]
+
+	ldr r2, =0x3F435313
+	str r2, [r0, #0x00c]
+	ldr r2, =0xB66E8B63
+	str r2, [r0, #0x010]
+
+	ldr r2, =0x01FF00DB
+	str r2, [r0, #0x014]
+	ldr r2, =0x00001740
+	str r2, [r0, #0x018]
+
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x00431023
+	str r2, [r0, #0x030]
+	ldr r2, =0x00000017
+	str r2, [r0, #0x040]
+
+	ldr r2, =0x83190000
+	str r2, [r0, #0x000]
+
+	ldr r2, =0x04008032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00048031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x05208030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00005800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00011117
+	str r2, [r0, #0x818]
+	ldr r2, =0x0002556D
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+.endm
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0x00C03F3F
+	str r1, [r0, #0x068]
+	ldr r1, =0x0030FC03
+	str r1, [r0, #0x06c]
+	ldr r1, =0x0FFFF000
+	str r1, [r0, #0x070]
+	ldr r1, =0x3FF00000
+	str r1, [r0, #0x074]
+	ldr r1, =0x00FFF300
+	str r1, [r0, #0x078]
+	ldr r1, =0x0F0000C3
+	str r1, [r0, #0x07c]
+	ldr r1, =0x000003FF
+	str r1, [r0, #0x080]
+#ifdef CONFIG_IMX_OPTEE
+#ifndef CONFIG_MX6QP
+	ldr r0, =0x20e0024
+	ldr r1, =0x3
+	str r1, [r0]
+#endif
+#endif
+.endm
+
+.macro imx6_qos_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0xF00000CF
+	str r1, [r0, #0x10]
+
+#if defined(CONFIG_MX6QP)
+	ldr r1, =0x77177717
+	str r1, [r0, #0x18]
+	str r1, [r0, #0x1c]
+#else
+	ldr r1, =0x007F007F
+	str r1, [r0, #0x18]
+	str r1, [r0, #0x1c]
+#endif
+.endm
+
+.macro imx6_ddr_setting
+#if defined (CONFIG_MX6S)
+	imx6solosabresd_ddr_setting
+#elif defined (CONFIG_MX6DL)
+	imx6dlsabresd_ddr_setting
+#elif defined (CONFIG_MX6QP)
+	imx6dqpsabresd_ddr_setting
+#elif defined (CONFIG_MX6Q)
+	imx6dqsabresd_ddr_setting
+#else
+	#error "SOC not configured"
+#endif
+
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/board/freescale/mx6slevk/Kconfig b/board/freescale/mx6slevk/Kconfig
index e6bbb4194f4..da156dccad7 100644
--- a/board/freescale/mx6slevk/Kconfig
+++ b/board/freescale/mx6slevk/Kconfig
@@ -12,4 +12,6 @@ config SYS_CONFIG_NAME
 config IMX_CONFIG
 	default "board/freescale/mx6slevk/imximage.cfg"
 
+config SYS_TEXT_BASE
+	default 0x87800000
 endif
diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg
index 64be101d6ec..89a07958eef 100644
--- a/board/freescale/mx6slevk/imximage.cfg
+++ b/board/freescale/mx6slevk/imximage.cfg
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
  *
  * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
  * and create imximage boot image
@@ -20,9 +21,11 @@ IMAGE_VERSION 2
 
 BOOT_FROM	sd
 
-/*
- * Secure boot support
- */
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN  board/freescale/mx6slevk/plugin.bin 0x00907000
+#else
+
 #ifdef CONFIG_IMX_HAB
 CSF CONFIG_CSF_SIZE
 #endif
@@ -48,6 +51,11 @@ DATA 4 0x020c4078 0xffffffff
 DATA 4 0x020c407c 0xffffffff
 DATA 4 0x020c4080 0xffffffff
 
+#ifdef CONFIG_IMX_OPTEE
+DATA 4 0x020e0024 0x00000001
+CHECK_BITS_SET 4 0x020e0024 0x1
+#endif
+
 DATA 4 0x020e0344 0x00003030
 DATA 4 0x020e0348 0x00003030
 DATA 4 0x020e034c 0x00003030
@@ -104,6 +112,7 @@ DATA 4 0x021b0038 0x00190778
 DATA 4 0x021b0008 0x00000000
 DATA 4 0x021b0040 0x0000004f
 DATA 4 0x021b0000 0xc3110000
+DATA 4 0x021b001c 0x00008010
 DATA 4 0x021b001c 0x003f8030
 DATA 4 0x021b001c 0xff0a8030
 DATA 4 0x021b001c 0x82018030
@@ -120,3 +129,4 @@ DATA 4 0x021b08b8 0x00000800
 DATA 4 0x021b0004 0x00025564
 DATA 4 0x021b0404 0x00011006
 DATA 4 0x021b001c 0x00000000
+#endif
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 2c90a35e2c9..6a9189b9d74 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -16,10 +16,12 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/global_data.h>
 #include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/mxc_i2c.h>
 #include <asm/io.h>
 #include <linux/sizes.h>
+#include <linux/delay.h>
 #include <common.h>
 #include <fsl_esdhc_imx.h>
 #include <i2c.h>
@@ -27,6 +29,12 @@
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 #include "../common/pfuze.h"
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#if defined(CONFIG_MXC_EPDC)
+#include <lcd.h>
+#include <mxc_epdc_fb.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -42,11 +50,22 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
 	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
 
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+		      PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
+		      PAD_CTL_DSE_40ohm | PAD_CTL_HYS |		\
+		      PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
 			PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
 			PAD_CTL_DSE_80ohm | PAD_CTL_HYS |	\
 			PAD_CTL_SRE_FAST)
 
+#define ELAN_INTR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+			    PAD_CTL_PUS_47K_UP | PAD_CTL_HYS)
+
+#define EPDC_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
 #define ETH_PHY_POWER	IMX_GPIO_NR(4, 21)
 
 int dram_init(void)
@@ -56,6 +75,19 @@ int dram_init(void)
 	return 0;
 }
 
+phys_size_t get_effective_memsize(void)
+{
+	return SZ_512M;
+}
+
+int dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+
+	return 0;
+}
+
 static iomux_v3_cfg_t const uart1_pads[] = {
 	MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
 	MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
@@ -104,60 +136,263 @@ static iomux_v3_cfg_t const usdhc3_pads[] = {
 };
 #endif
 
+static iomux_v3_cfg_t const elan_pads[] = {
+	MX6_PAD_EPDC_PWRCTRL2__GPIO_2_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EPDC_PWRCTRL3__GPIO_2_10 | MUX_PAD_CTRL(ELAN_INTR_PAD_CTRL),
+	MX6_PAD_KEY_COL6__GPIO_4_4 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
+};
+
+#ifdef CONFIG_MXC_EPDC
+static iomux_v3_cfg_t const epdc_enable_pads[] = {
+	MX6_PAD_EPDC_D0__EPDC_SDDO_0	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_D1__EPDC_SDDO_1	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_D2__EPDC_SDDO_2	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_D3__EPDC_SDDO_3	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_D4__EPDC_SDDO_4	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_D5__EPDC_SDDO_5	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_D6__EPDC_SDDO_6	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_D7__EPDC_SDDO_7	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_GDCLK__EPDC_GDCLK	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_GDSP__EPDC_GDSP	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_GDOE__EPDC_GDOE	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_GDRL__EPDC_GDRL	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDCLK__EPDC_SDCLK	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDOE__EPDC_SDOE	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDLE__EPDC_SDLE	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDSHR__EPDC_SDSHR	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_BDR0__EPDC_BDR_0	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDCE0__EPDC_SDCE_0	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDCE1__EPDC_SDCE_1	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDCE2__EPDC_SDCE_2	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const epdc_disable_pads[] = {
+	MX6_PAD_EPDC_D0__GPIO_1_7,
+	MX6_PAD_EPDC_D1__GPIO_1_8,
+	MX6_PAD_EPDC_D2__GPIO_1_9,
+	MX6_PAD_EPDC_D3__GPIO_1_10,
+	MX6_PAD_EPDC_D4__GPIO_1_11,
+	MX6_PAD_EPDC_D5__GPIO_1_12,
+	MX6_PAD_EPDC_D6__GPIO_1_13,
+	MX6_PAD_EPDC_D7__GPIO_1_14,
+	MX6_PAD_EPDC_GDCLK__GPIO_1_31,
+	MX6_PAD_EPDC_GDSP__GPIO_2_2,
+	MX6_PAD_EPDC_GDOE__GPIO_2_0,
+	MX6_PAD_EPDC_GDRL__GPIO_2_1,
+	MX6_PAD_EPDC_SDCLK__GPIO_1_23,
+	MX6_PAD_EPDC_SDOE__GPIO_1_25,
+	MX6_PAD_EPDC_SDLE__GPIO_1_24,
+	MX6_PAD_EPDC_SDSHR__GPIO_1_26,
+	MX6_PAD_EPDC_BDR0__GPIO_2_5,
+	MX6_PAD_EPDC_SDCE0__GPIO_1_27,
+	MX6_PAD_EPDC_SDCE1__GPIO_1_28,
+	MX6_PAD_EPDC_SDCE2__GPIO_1_29,
+};
+#endif
+
 static void setup_iomux_uart(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 
-int board_mmc_get_env_dev(int devno)
-{
-	return devno;
-}
+#ifdef CONFIG_SYS_I2C_LEGACY
+#define PC	MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+struct i2c_pads_info i2c_pad_info1 = {
+	.sda = {
+		.i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
+		.gp = IMX_GPIO_NR(3, 13),
+	},
+	.scl = {
+		.i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
+		.gp = IMX_GPIO_NR(3, 12),
+	},
+};
+#endif
 
-#ifdef CONFIG_DM_PMIC_PFUZE100
+#ifdef CONFIG_POWER_LEGACY
 int power_init_board(void)
 {
-	struct udevice *dev;
+	struct pmic *pfuze;
+	unsigned int reg;
 	int ret;
-	u32 dev_id, rev_id, i;
-	u32 switch_num = 6;
-	u32 offset = PFUZE100_SW1CMODE;
 
-	ret = pmic_get("pfuze100@08", &dev);
-	if (ret == -ENODEV)
-		return 0;
+	pfuze = pfuze_common_init(I2C_PMIC);
+	if (!pfuze)
+		return -ENODEV;
 
-	if (ret != 0)
+	ret = pfuze_mode_init(pfuze, APS_PFM);
+	if (ret < 0)
 		return ret;
 
-	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
-	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
-	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
-
 	/* set SW1AB staby volatage 0.975V */
-	pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
+	pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);
 
 	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
-	pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
+	pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);
 
 	/* set SW1C staby volatage 0.975V */
-	pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b);
+	pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
 
 	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
-	pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
+	pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
+
+	return 0;
+}
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+int power_init_board(void)
+{
+	struct udevice *dev;
+	unsigned int reg;
+	int ret;
+
+	dev = pfuze_common_init();
+	if (!dev)
+		return -ENODEV;
+
+	ret = pfuze_mode_init(dev, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	/* set SW1AB staby volatage 0.975V*/
+	reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
+
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
 
-	/* Init mode to APS_PFM */
-	pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
+	/* set SW1C staby volatage 0.975V*/
+	reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
+	reg &= ~0x3f;
+	reg |= 0x1b;
+	pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
 
-	for (i = 0; i < switch_num - 1; i++)
-		pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
+	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+	reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
 
 	return 0;
 }
 #endif
 
-#ifdef CONFIG_FEC_MXC
+#ifdef CONFIG_LDO_BYPASS_CHECK
+#ifdef CONFIG_POWER_LEGACY
+void ldo_mode_set(int ldo_bypass)
+{
+	u32 value;
+	int is_400M;
+	struct pmic *p = pmic_get("PFUZE100");
+
+	if (!p) {
+		printf("No pmic!\n");
+		return;
+	}
+
+	/* swith to ldo_bypass mode */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+
+		/* decrease VDDARM to 1.1V */
+		pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+		value &= ~0x3f;
+		value |= 0x20;
+		pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+
+		/* increase VDDSOC to 1.3V */
+		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+		value &= ~0x3f;
+		value |= 0x28;
+		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+		is_400M = set_anatop_bypass(0);
+
+		/*
+		 * MX6SL: VDDARM:1.175V@800M; VDDSOC:1.175V@800M
+		 *        VDDARM:0.975V@400M; VDDSOC:1.175V@400M
+		 */
+		pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+		value &= ~0x3f;
+		if (is_400M)
+			value |= 0x1b;
+		else
+			value |= 0x23;
+		pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+
+		/* decrease VDDSOC to 1.175V */
+		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+		value &= ~0x3f;
+		value |= 0x23;
+		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+		finish_anatop_bypass();
+		printf("switch to ldo_bypass mode!\n");
+	}
+}
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+void ldo_mode_set(int ldo_bypass)
+{
+	struct udevice *dev;
+	int ret;
+	int is_400M;
+	u32 vddarm;
+
+	ret = pmic_get("pfuze100@8", &dev);
+	if (ret == -ENODEV) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* switch to ldo_bypass mode , boot on 800Mhz */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+
+		/* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x20);
+
+		/* increase VDDSOC to 1.3V */
+		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x28);
+
+		is_400M = set_anatop_bypass(0);
+		if (is_400M)
+			vddarm = 0x1b;
+		else
+			vddarm = 0x23;
+
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
+
+		/* decrease VDDSOC to 1.175V */
+		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x23);
 
+		finish_anatop_bypass();
+		printf("switch to ldo_bypass mode!\n");
+	}
+}
+#endif
+
+#endif
+
+#ifdef CONFIG_FEC_MXC
 static int setup_fec(void)
 {
 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
@@ -169,6 +404,52 @@ static int setup_fec(void)
 }
 #endif
 
+#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+	/* OTG1 */
+	MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
+	/* OTG2 */
+	MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+					 ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+	if (port == 1)
+		return USB_INIT_HOST;
+	else
+		return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	/* Set Power polarity */
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
+}
+#endif
+#endif
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -176,15 +457,257 @@ int board_early_init_f(void)
 	return 0;
 }
 
+#ifdef CONFIG_MXC_EPDC
+vidinfo_t panel_info = {
+	.vl_refresh = 85,
+	.vl_col = 800,
+	.vl_row = 600,
+	.vl_rot = 0,
+	.vl_pixclock = 26666667,
+	.vl_left_margin = 8,
+	.vl_right_margin = 100,
+	.vl_upper_margin = 4,
+	.vl_lower_margin = 8,
+	.vl_hsync = 4,
+	.vl_vsync = 1,
+	.vl_sync = 0,
+	.vl_mode = 0,
+	.vl_flag = 0,
+	.vl_bpix = 3,
+	.cmap = 0,
+};
+
+struct epdc_timing_params panel_timings = {
+	.vscan_holdoff = 4,
+	.sdoed_width = 10,
+	.sdoed_delay = 20,
+	.sdoez_width = 10,
+	.sdoez_delay = 20,
+	.gdclk_hp_offs = 419,
+	.gdsp_offs = 20,
+	.gdoe_offs = 0,
+	.gdclk_offs = 5,
+	.num_ce = 1,
+};
+
+static void setup_epdc_power(void)
+{
+	/* Setup epdc voltage */
+
+	/* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */
+	imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRSTAT__GPIO_2_13 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+	gpio_request(IMX_GPIO_NR(2, 13), "EPDC PWRSTAT");
+	gpio_direction_input(IMX_GPIO_NR(2, 13));
+
+	/* EPDC_VCOM0 - GPIO2[3] for VCOM control */
+	imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO_2_3 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* Set as output */
+	gpio_request(IMX_GPIO_NR(2, 3), "EPDC VCOM0");
+	gpio_direction_output(IMX_GPIO_NR(2, 3), 1);
+
+	/* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */
+	imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+	/* Set as output */
+	gpio_request(IMX_GPIO_NR(2, 14), "EPDC PWR WAKEUP");
+	gpio_direction_output(IMX_GPIO_NR(2, 14), 1);
+
+	/* EPDC_PWRCTRL0 - GPIO2[7] for EPD PWR CTL0 */
+	imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+	/* Set as output */
+	gpio_request(IMX_GPIO_NR(2, 7), "EPDC PWRCTRL0");
+	gpio_direction_output(IMX_GPIO_NR(2, 7), 1);
+}
+
+static void epdc_enable_pins(void)
+{
+	/* epdc iomux settings */
+	imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
+				ARRAY_SIZE(epdc_enable_pads));
+}
+
+static void epdc_disable_pins(void)
+{
+	/* Configure MUX settings for EPDC pins to GPIO  and drive to 0 */
+	imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
+				ARRAY_SIZE(epdc_disable_pads));
+}
+
+static void setup_epdc(void)
+{
+	unsigned int reg;
+	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/*** Set pixel clock rates for EPDC ***/
+
+	/* EPDC AXI clk from PFD_400M, set to 396/2 = 198MHz */
+	reg = readl(&ccm_regs->chsccdr);
+	reg &= ~0x3F000;
+	reg |= (0x4 << 15) | (1 << 12);
+	writel(reg, &ccm_regs->chsccdr);
+
+	/* EPDC AXI clk enable */
+	reg = readl(&ccm_regs->CCGR3);
+	reg |= 0x0030;
+	writel(reg, &ccm_regs->CCGR3);
+
+	/* EPDC PIX clk from PFD_540M, set to 540/4/5 = 27MHz */
+	reg = readl(&ccm_regs->cscdr2);
+	reg &= ~0x03F000;
+	reg |= (0x5 << 15) | (4 << 12);
+	writel(reg, &ccm_regs->cscdr2);
+
+	reg = readl(&ccm_regs->cbcmr);
+	reg &= ~0x03800000;
+	reg |= (0x3 << 23);
+	writel(reg, &ccm_regs->cbcmr);
+
+	/* EPDC PIX clk enable */
+	reg = readl(&ccm_regs->CCGR3);
+	reg |= 0x0C00;
+	writel(reg, &ccm_regs->CCGR3);
+
+	panel_info.epdc_data.wv_modes.mode_init = 0;
+	panel_info.epdc_data.wv_modes.mode_du = 1;
+	panel_info.epdc_data.wv_modes.mode_gc4 = 3;
+	panel_info.epdc_data.wv_modes.mode_gc8 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc16 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc32 = 2;
+
+	panel_info.epdc_data.epdc_timings = panel_timings;
+
+	setup_epdc_power();
+}
+
+void epdc_power_on(void)
+{
+	unsigned int reg;
+	struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
+
+	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
+	gpio_set_value(IMX_GPIO_NR(2, 7), 1);
+	udelay(1000);
+
+	/* Enable epdc signal pin */
+	epdc_enable_pins();
+
+	/* Set PMIC Wakeup to high - enable Display power */
+	gpio_set_value(IMX_GPIO_NR(2, 14), 1);
+
+	/* Wait for PWRGOOD == 1 */
+	while (1) {
+		reg = readl(&gpio_regs->gpio_psr);
+		if (!(reg & (1 << 13)))
+			break;
+
+		udelay(100);
+	}
+
+	/* Enable VCOM */
+	gpio_set_value(IMX_GPIO_NR(2, 3), 1);
+
+	udelay(500);
+}
+
+void epdc_power_off(void)
+{
+	/* Set PMIC Wakeup to low - disable Display power */
+	gpio_set_value(IMX_GPIO_NR(2, 14), 0);
+
+	/* Disable VCOM */
+	gpio_set_value(IMX_GPIO_NR(2, 3), 0);
+
+	epdc_disable_pins();
+
+	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
+	gpio_set_value(IMX_GPIO_NR(2, 7), 0);
+}
+#endif
+
+void setup_elan_pads(void)
+{
+#define TOUCH_CS	IMX_GPIO_NR(2, 9)
+#define TOUCH_INT   IMX_GPIO_NR(2, 10)
+#define TOUCH_RST	IMX_GPIO_NR(4, 4)
+	imx_iomux_v3_setup_multiple_pads(elan_pads, ARRAY_SIZE(elan_pads));
+	gpio_request(TOUCH_CS, "TOUCH CS");
+	gpio_request(TOUCH_INT, "TOUCH Interrupt");
+	gpio_request(TOUCH_RST, "TOUCH Reset");
+}
+
 int board_init(void)
 {
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_SYS_I2C_LEGACY
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+	setup_elan_pads();
+
 #ifdef	CONFIG_FEC_MXC
 	setup_fec();
 #endif
 
+#ifdef	CONFIG_MXC_EPDC
+	setup_epdc();
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+	setup_usb();
+#endif
+#endif
+
+	return 0;
+}
+
+void elan_init(void)
+{
+	gpio_direction_input(TOUCH_INT);
+	/*
+	 * If epdc panel not plugged in, gpio_get_value(TOUCH_INT) will
+	 * return 1. And no need to mdelay, which will make i2c operation
+	 * slow.
+	 * If epdc panel plugged in, gpio_get_value(TOUCH_INT) will
+	 * return 0. And elan init flow will be executed.
+	 */
+	if (gpio_get_value(TOUCH_INT))
+		return;
+	gpio_direction_output(TOUCH_CS , 1);
+	gpio_set_value(TOUCH_CS, 0);
+	gpio_direction_output(TOUCH_RST , 1);
+	gpio_set_value(TOUCH_RST, 0);
+	mdelay(10);
+	gpio_set_value(TOUCH_RST, 1);
+	gpio_set_value(TOUCH_CS, 1);
+	mdelay(100);
+}
+
+/*
+ * This function overwrite the function defined in
+ * drivers/i2c/mxc_i2c.c, which is a weak symbol
+ */
+void i2c_force_reset_slave(void)
+{
+	elan_init();
+}
+
+int board_late_init(void)
+{
+	env_set("tee", "no");
+#ifdef CONFIG_IMX_OPTEE
+	env_set("tee", "yes");
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
 	return 0;
 }
 
@@ -195,6 +718,30 @@ int checkboard(void)
 	return 0;
 }
 
+#ifdef CONFIG_MXC_KPD
+#define MX6SL_KEYPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+			   PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_120ohm)
+
+iomux_v3_cfg_t const mxc_kpd_pads[] = {
+	(MX6_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	(MX6_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	(MX6_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	(MX6_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+
+	(MX6_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)),
+	(MX6_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)),
+	(MX6_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)),
+	(MX6_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)),
+};
+int setup_mxc_kpd(void)
+{
+	imx_iomux_v3_setup_multiple_pads(mxc_kpd_pads,
+					 ARRAY_SIZE(mxc_kpd_pads));
+
+	return 0;
+}
+#endif /*CONFIG_MXC_KPD*/
+
 #ifdef CONFIG_SPL_BUILD
 #include <spl.h>
 #include <linux/libfdt.h>
diff --git a/board/freescale/mx6slevk/plugin.S b/board/freescale/mx6slevk/plugin.S
new file mode 100644
index 00000000000..e23146d74a4
--- /dev/null
+++ b/board/freescale/mx6slevk/plugin.S
@@ -0,0 +1,189 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6slevk_ddr_setting
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0x00260324
+	str r1, [r0, #0x018]
+
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x00020000
+	str r1, [r0, #0x5c0]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x5b4]
+
+	ldr r1, =0x00000028
+	str r1, [r0, #0x338]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x300]
+	str r1, [r0, #0x31c]
+	str r1, [r0, #0x320]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x32c]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x5ac]
+	str r1, [r0, #0x5c8]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x5b0]
+
+	ldr r1, =0x00003030
+	str r1, [r0, #0x344]
+	str r1, [r0, #0x348]
+	str r1, [r0, #0x34c]
+	str r1, [r0, #0x350]
+
+	ldr r1, =0x00080000
+	str r1, [r0, #0x5d0]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x5c4]
+	str r1, [r0, #0x5cc]
+	str r1, [r0, #0x5d4]
+	str r1, [r0, #0x5d8]
+
+	str r1, [r0, #0x30c]
+	str r1, [r0, #0x310]
+	str r1, [r0, #0x314]
+	str r1, [r0, #0x318]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x1b4700c7
+	str r2, [r0, #0x85c]
+
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x00300000
+	str r2, [r0, #0x890]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+	str r2, [r0, #0x82c]
+	str r2, [r0, #0x830]
+	str r2, [r0, #0x834]
+	str r2, [r0, #0x838]
+
+	ldr r2, =0x4241444a
+	str r2, [r0, #0x848]
+
+	ldr r2, =0x3030312b
+	str r2, [r0, #0x850]
+
+	ldr r2, =0x20000000
+	str r2, [r0, #0x83c]
+
+	ldr r2, =0x00000000
+	str r2, [r0, #0x840]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+
+	ldr r2, =0x33374133
+	str r2, [r0, #0x00c]
+
+	ldr r2, =0x00020024
+	str r2, [r0, #0x004]
+
+	ldr r2, =0x00100A82
+	str r2, [r0, #0x010]
+	ldr r2, =0x00000093
+	str r2, [r0, #0x014]
+	ldr r2, =0x00001688
+	str r2, [r0, #0x018]
+	ldr r2, =0x0F9F26D2
+	str r2, [r0, #0x02c]
+
+	ldr r2, =0x0000020E
+	str r2, [r0, #0x030]
+	ldr r2, =0x00190778
+	str r2, [r0, #0x038]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x008]
+	ldr r2, =0x0000004F
+	str r2, [r0, #0x040]
+	ldr r2, =0xC3110000
+	str r2, [r0, #0x000]
+
+	ldr r2, =0x00008010
+	str r2, [r0, #0x01c]
+	ldr r2, =0x003F8030
+	str r2, [r0, #0x01c]
+	ldr r2, =0xFF0A8030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x82018030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04028030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x02038030
+	str r2, [r0, #0x01c]
+	ldr r2, =0xFF0A8038
+	str r2, [r0, #0x01c]
+	ldr r2, =0x82018038
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04028038
+	str r2, [r0, #0x01c]
+	ldr r2, =0x02038038
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0xa1310003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x00001800
+	str r2, [r0, #0x020]
+
+	ldr r2, =0x00000000
+	str r2, [r0, #0x818]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+
+	ldr r2, =0x00025564
+	str r2, [r0, #0x004]
+
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+.endm
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x068]
+	str r1, [r0, #0x06c]
+	str r1, [r0, #0x070]
+	str r1, [r0, #0x074]
+	str r1, [r0, #0x078]
+	str r1, [r0, #0x07c]
+	str r1, [r0, #0x080]
+	str r1, [r0, #0x084]
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+	imx6slevk_ddr_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/board/freescale/mx6sll_val/Kconfig b/board/freescale/mx6sll_val/Kconfig
new file mode 100644
index 00000000000..9964eccf895
--- /dev/null
+++ b/board/freescale/mx6sll_val/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_MX6SLL_VAL
+
+config SYS_BOARD
+	default "mx6sll_val"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx6sll_val"
+
+config LPDDR2_BOARD
+	bool "set if the board uses the LPDDR2 not default LPDDR3" 
+
+config SYS_TEXT_BASE
+	default 0x87800000
+
+endif
diff --git a/board/freescale/mx6sll_val/Makefile b/board/freescale/mx6sll_val/Makefile
new file mode 100644
index 00000000000..f3d2f83728f
--- /dev/null
+++ b/board/freescale/mx6sll_val/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx6sll_val.o
diff --git a/board/freescale/mx6sll_val/imximage.cfg b/board/freescale/mx6sll_val/imximage.cfg
new file mode 100644
index 00000000000..733aedd3b0a
--- /dev/null
+++ b/board/freescale/mx6sll_val/imximage.cfg
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6sll_val/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E0550 0x00080000
+DATA 4 0x020E0534 0x00000000
+DATA 4 0x020E02AC 0x00000030
+DATA 4 0x020E0548 0x00000030
+DATA 4 0x020E052C 0x00000030
+DATA 4 0x020E0530 0x00020000
+DATA 4 0x020E02B0 0x00003030
+DATA 4 0x020E02B4 0x00003030
+DATA 4 0x020E02B8 0x00003030
+DATA 4 0x020E02BC 0x00003030
+DATA 4 0x020E0540 0x00020000
+DATA 4 0x020E0544 0x00000030
+DATA 4 0x020E054C 0x00000030
+DATA 4 0x020E0554 0x00000030
+DATA 4 0x020E0558 0x00000030
+DATA 4 0x020E0294 0x00000030
+DATA 4 0x020E0298 0x00000030
+DATA 4 0x020E029C 0x00000030
+DATA 4 0x020E02A0 0x00000030
+DATA 4 0x020E02C0 0x00082030
+
+DATA 4 0x021B001C 0x00008000
+
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B085c 0x084700C7
+DATA 4 0x021B0890 0x00400000
+DATA 4 0x021B0848 0x3C3A3C3C
+DATA 4 0x021B0850 0x24293625
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B0824 0x33333333
+DATA 4 0x021B0828 0x33333333
+
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B0834 0xf3333333
+DATA 4 0x021B0838 0xf3333333
+DATA 4 0x021B08C0 0x24922492
+DATA 4 0x021B08b8 0x00000800
+
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B000C 0x53574333
+DATA 4 0x021B0010 0x00100B22
+DATA 4 0x021B0038 0x00170778
+DATA 4 0x021B0014 0x00C700DB
+DATA 4 0x021B0018 0x00201718
+DATA 4 0x021B002C 0x0F9F26D2
+DATA 4 0x021B0030 0x009F0E10
+DATA 4 0x021B0040 0x0000005F
+DATA 4 0x021B0000 0xC4190000
+
+DATA 4 0x021B001C 0x00008050
+DATA 4 0x021B001C 0x00008058
+DATA 4 0x021B001C 0x003F8030
+DATA 4 0x021B001C 0x003F8038
+DATA 4 0x021B001C 0xFF0A8030
+DATA 4 0x021B001C 0xFF0A8038
+DATA 4 0x021B001C 0x04028030
+DATA 4 0x021B001C 0x04028038
+DATA 4 0x021B001C 0x83018030
+DATA 4 0x021B001C 0x83018038
+DATA 4 0x021B001C 0x01038030
+DATA 4 0x021B001C 0x01038038
+
+DATA 4 0x021B083C 0x20000000
+
+DATA 4 0x021B0020 0x00001800
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+#endif
diff --git a/board/freescale/mx6sll_val/imximage_lpddr2.cfg b/board/freescale/mx6sll_val/imximage_lpddr2.cfg
new file mode 100644
index 00000000000..e6c52b73a5d
--- /dev/null
+++ b/board/freescale/mx6sll_val/imximage_lpddr2.cfg
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6sll_val/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E0550 0x00080000
+DATA 4 0x020E0534 0x00000000
+DATA 4 0x020E02AC 0x00000030
+DATA 4 0x020E0548 0x00000030
+DATA 4 0x020E052C 0x00000030
+DATA 4 0x020E0530 0x00020000
+DATA 4 0x020E02B0 0x00003030
+DATA 4 0x020E02B4 0x00003030
+DATA 4 0x020E02B8 0x00003030
+DATA 4 0x020E02BC 0x00003030
+DATA 4 0x020E0540 0x00020000
+DATA 4 0x020E0544 0x00000030
+DATA 4 0x020E054C 0x00000030
+DATA 4 0x020E0554 0x00000030
+DATA 4 0x020E0558 0x00000030
+DATA 4 0x020E0294 0x00000030
+DATA 4 0x020E0298 0x00000030
+DATA 4 0x020E029C 0x00000030
+DATA 4 0x020E02A0 0x00000030
+DATA 4 0x020E02C0 0x00082030
+
+DATA 4 0x021B001C 0x00008000
+
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B085c 0x084700C7
+DATA 4 0x021B0890 0x00400000
+DATA 4 0x021B0848 0x3A383C40
+DATA 4 0x021B0850 0x242C3020
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B0824 0x33333333
+DATA 4 0x021B0828 0x33333333
+
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B0834 0xf3333333
+DATA 4 0x021B0838 0xf3333333
+DATA 4 0x021B08C0 0x24922492
+DATA 4 0x021B08b8 0x00000800
+
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B000C 0x53574333
+DATA 4 0x021B0010 0x00100A82
+DATA 4 0x021B0038 0x00170777
+DATA 4 0x021B0014 0x00C70093
+DATA 4 0x021B0018 0x00201708
+DATA 4 0x021B002C 0x0F9F26D2
+DATA 4 0x021B0030 0x009F0E10
+DATA 4 0x021B0040 0x0000004F
+DATA 4 0x021B0000 0xC3110000
+
+DATA 4 0x021B001C 0x00008050
+DATA 4 0x021B001C 0x00008058
+DATA 4 0x021B001C 0x003F8030
+DATA 4 0x021B001C 0x003F8038
+DATA 4 0x021B001C 0xFF0A8030
+DATA 4 0x021B001C 0xFF0A8038
+DATA 4 0x021B001C 0x04028030
+DATA 4 0x021B001C 0x04028038
+DATA 4 0x021B001C 0x82018030
+DATA 4 0x021B001C 0x82018038
+DATA 4 0x021B001C 0x01038030
+DATA 4 0x021B001C 0x01038038
+
+DATA 4 0x021B083C 0x20000000
+
+DATA 4 0x021B0020 0x00001800
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+#endif
diff --git a/board/freescale/mx6sll_val/mx6sll_val.c b/board/freescale/mx6sll_val/mx6sll_val.c
new file mode 100644
index 00000000000..6acd73cec68
--- /dev/null
+++ b/board/freescale/mx6sll_val/mx6sll_val.c
@@ -0,0 +1,751 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch-mx6/clock.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc_imx.h>
+#include <i2c.h>
+#include <linux/sizes.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <mxsfb.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#if defined(CONFIG_MXC_EPDC)
+#include <lcd.h>
+#include <mxc_epdc_fb.h>
+#endif
+#include <asm/mach-imx/video.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE)
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#define EPDC_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC and EPD */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		/* conflict with usb_otg2_pwr */
+		.i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_I2C1_SCL__GPIO3_IO12 | PC,
+		.gp = IMX_GPIO_NR(3, 12),
+	},
+	.sda = {
+		/* conflict with usb_otg2_oc */
+		.i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_I2C1_SDA__GPIO3_IO13 | PC,
+		.gp = IMX_GPIO_NR(3, 13),
+	},
+};
+
+/* I2C2 for LCD and ADV */
+struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_I2C2_SCL__I2C2_SCL | PC,
+		.gpio_mode = MX6_PAD_I2C2_SCL__GPIO3_IO14 | PC,
+		.gp = IMX_GPIO_NR(3, 14),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_I2C2_SDA__I2C2_SDA | PC,
+		.gpio_mode = MX6_PAD_I2C2_SDA__GPIO3_IO15 | PC,
+		.gp = IMX_GPIO_NR(3, 15),
+	},
+};
+
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const led_pads[] = {
+	MX6_PAD_EPDC_VCOM1__GPIO2_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+/* 8bit SD1 */
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA4__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA5__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA6__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA7__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/* CD */
+	MX6_PAD_KEY_ROW7__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* WP */
+	MX6_PAD_GPIO4_IO22__SD1_WP   | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/* EMMC */
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/* DQS */
+	MX6_PAD_GPIO4_IO21__SD2_STROBE | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* RST_B */
+	MX6_PAD_SD2_RESET__GPIO4_IO27 | MUX_PAD_CTRL(USDHC_PAD_CTRL | PAD_CTL_LVE),
+};
+
+/* Wifi SD */
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/* CD */
+	MX6_PAD_REF_CLK_32K__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+
+	SETUP_IOMUX_PADS(led_pads);
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
+	{USDHC1_BASE_ADDR, 0, 8, 1},
+	{USDHC2_BASE_ADDR, 0, 8, 0, 1}, /* fixed 1.8v IO voltage for eMMC chip */
+	{USDHC3_BASE_ADDR, 0, 4},
+};
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(4, 7)
+#define USDHC2_PWR_GPIO	IMX_GPIO_NR(4, 27)
+#define USDHC3_CD_GPIO	IMX_GPIO_NR(3, 22)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC3_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 * mmc2                    USDHC3
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc1_pads);
+			gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
+			gpio_direction_input(USDHC1_CD_GPIO);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		case 1:
+			SETUP_IOMUX_PADS(usdhc2_pads);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr");
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			break;
+		case 2:
+			SETUP_IOMUX_PADS(usdhc3_pads);
+			gpio_request(USDHC3_CD_GPIO, "usdhc3 cd");
+			gpio_direction_input(USDHC3_CD_GPIO);
+			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
+			return 0;
+		}
+
+		if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_POWER_LEGACY
+#define I2C_PMIC	0
+static struct pmic *pfuze;
+int power_init_board(void)
+{
+	int ret;
+	u32 rev_id, value;
+
+	ret = power_pfuze100_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	pfuze = pmic_get("PFUZE100");
+	if (!pfuze)
+		return -ENODEV;
+
+	ret = pmic_probe(pfuze);
+	if (ret)
+		return ret;
+
+	ret = pfuze_mode_init(pfuze, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value);
+	pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id);
+	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id);
+
+	/* set SW1AB standby volatage 0.975V */
+	pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value);
+	value &= ~0x3f;
+	value |= PFUZE100_SW1ABC_SETP(9750);
+	pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value);
+
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value);
+	value &= ~0xc0;
+	value |= 0x40;
+	pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value);
+
+	/* set SW1C staby volatage 0.975V */
+	pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value);
+	value &= ~0x3f;
+	value |= 0x1b;
+	pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value);
+
+	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+	pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value);
+	value &= ~0xc0;
+	value |= 0x40;
+	pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value);
+
+	return 0;
+}
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	dev = pfuze_common_init();
+	if (!dev)
+		return -ENODEV;
+
+	ret = pfuze_mode_init(dev, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#ifndef CONFIG_DM_SPI
+iomux_v3_cfg_t const ecspi1_pads[] = {
+	MX6_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+
+	/* CS0 */
+	MX6_PAD_ECSPI1_SS0__GPIO4_IO11   | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void setup_spinor(void)
+{
+	SETUP_IOMUX_PADS(ecspi1_pads);
+	gpio_request(IMX_GPIO_NR(4, 11), "escpi cs");
+	gpio_direction_output(IMX_GPIO_NR(4, 11), 0);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
+}
+#endif
+#endif
+
+#ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lcd_pads[] = {
+	MX6_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA00__LCD_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA01__LCD_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA02__LCD_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA03__LCD_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA04__LCD_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA05__LCD_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA06__LCD_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA07__LCD_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA08__LCD_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA09__LCD_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_ECSPI1_SCLK__GPIO4_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_LCD_RESET__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* Use GPIO for Brightness adjustment, duty cycle = period */
+	MX6_PAD_PWM1__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void do_enable_parallel_lcd(struct display_info_t const *dev)
+
+{
+	int ret;
+
+	ret = enable_lcdif_clock(dev->bus, 1);
+	if (ret) {
+		printf("Enable LCDIF clock failed, %d\n", ret);
+		return;
+	}
+
+	SETUP_IOMUX_PADS(lcd_pads);
+
+	/* Reset the LCD */
+	gpio_request(IMX_GPIO_NR(2, 19), "lcd reset");
+	gpio_direction_output(IMX_GPIO_NR(2, 19) , 0);
+	udelay(500);
+	gpio_direction_output(IMX_GPIO_NR(2, 19) , 1);
+
+	gpio_request(IMX_GPIO_NR(4, 8), "lcd pwr en");
+	gpio_direction_output(IMX_GPIO_NR(4, 8) , 1);
+
+	/* Set Brightness to high */
+	gpio_request(IMX_GPIO_NR(3, 23), "backlight");
+	gpio_direction_output(IMX_GPIO_NR(3, 23) , 1);
+}
+
+struct display_info_t const displays[] = {{
+	.bus = MX6SLL_LCDIF_BASE_ADDR,
+	.addr = 0,
+	.pixfmt = 24,
+	.detect = NULL,
+	.enable	= do_enable_parallel_lcd,
+	.mode	= {
+		.name			= "MCIMX28LCD",
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 29850,
+		.left_margin    = 89,
+		.right_margin   = 164,
+		.upper_margin   = 23,
+		.lower_margin   = 10,
+		.hsync_len      = 10,
+		.vsync_len      = 10,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+#endif
+
+#ifdef CONFIG_MXC_EPDC
+static iomux_v3_cfg_t const epdc_enable_pads[] = {
+	MX6_PAD_EPDC_DATA00__EPDC_DATA00	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA01__EPDC_DATA01	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA02__EPDC_DATA02	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA03__EPDC_DATA03	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA04__EPDC_DATA04	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA05__EPDC_DATA05	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA06__EPDC_DATA06	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA07__EPDC_DATA07	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA08__EPDC_DATA08	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA09__EPDC_DATA09	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA10__EPDC_DATA10	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA11__EPDC_DATA11	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA12__EPDC_DATA12	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA13__EPDC_DATA13	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA14__EPDC_DATA14	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA15__EPDC_DATA15	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDCLK__EPDC_SDCLK_P	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDLE__EPDC_SDLE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDOE__EPDC_SDOE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDSHR__EPDC_SDSHR		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDCE0__EPDC_SDCE0		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_GDCLK__EPDC_GDCLK		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_GDOE__EPDC_GDOE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_GDRL__EPDC_GDRL		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_GDSP__EPDC_GDSP		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const epdc_disable_pads[] = {
+	MX6_PAD_EPDC_DATA01__GPIO1_IO08,
+	MX6_PAD_EPDC_DATA02__GPIO1_IO09,
+	MX6_PAD_EPDC_DATA03__GPIO1_IO10,
+	MX6_PAD_EPDC_DATA04__GPIO1_IO11,
+	MX6_PAD_EPDC_DATA05__GPIO1_IO12,
+	MX6_PAD_EPDC_DATA06__GPIO1_IO13,
+	MX6_PAD_EPDC_DATA07__GPIO1_IO14,
+	MX6_PAD_EPDC_DATA08__GPIO1_IO15,
+	MX6_PAD_EPDC_DATA09__GPIO1_IO16,
+	MX6_PAD_EPDC_DATA10__GPIO1_IO17,
+	MX6_PAD_EPDC_DATA11__GPIO1_IO18,
+	MX6_PAD_EPDC_DATA12__GPIO1_IO19,
+	MX6_PAD_EPDC_DATA13__GPIO1_IO20,
+	MX6_PAD_EPDC_DATA14__GPIO1_IO21,
+	MX6_PAD_EPDC_DATA15__GPIO1_IO22,
+	MX6_PAD_EPDC_SDCLK__GPIO1_IO23,
+	MX6_PAD_EPDC_SDLE__GPIO1_IO24,
+	MX6_PAD_EPDC_SDOE__GPIO1_IO25,
+	MX6_PAD_EPDC_SDSHR__GPIO1_IO26,
+	MX6_PAD_EPDC_SDCE0__GPIO1_IO27,
+	MX6_PAD_EPDC_GDCLK__GPIO1_IO31,
+	MX6_PAD_EPDC_GDOE__GPIO2_IO00,
+	MX6_PAD_EPDC_GDRL__GPIO2_IO01,
+	MX6_PAD_EPDC_GDSP__GPIO2_IO02,
+};
+
+vidinfo_t panel_info = {
+	.vl_refresh = 85,
+	.vl_col = 1024,
+	.vl_row = 758,
+	.vl_pixclock = 40000000,
+	.vl_left_margin = 12,
+	.vl_right_margin = 76,
+	.vl_upper_margin = 4,
+	.vl_lower_margin = 5,
+	.vl_hsync = 12,
+	.vl_vsync = 2,
+	.vl_sync = 0,
+	.vl_mode = 0,
+	.vl_flag = 0,
+	.vl_bpix = 3,
+	.cmap = 0,
+};
+
+struct epdc_timing_params panel_timings = {
+	.vscan_holdoff = 4,
+	.sdoed_width = 10,
+	.sdoed_delay = 20,
+	.sdoez_width = 10,
+	.sdoez_delay = 20,
+	.gdclk_hp_offs = 524,
+	.gdsp_offs = 327,
+	.gdoe_offs = 0,
+	.gdclk_offs = 19,
+	.num_ce = 1,
+};
+
+static iomux_v3_cfg_t const epdc_pwr_ctrl_pads[] = {
+	IOMUX_PADS(PAD_EPDC_PWR_STAT__GPIO2_IO13	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EPDC_VCOM0__GPIO2_IO03		| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EPDC_PWR_WAKE__GPIO2_IO14	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EPDC_PWR_CTRL0__GPIO2_IO07	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+};
+
+static void setup_epdc_power(void)
+{
+	SETUP_IOMUX_PADS(epdc_pwr_ctrl_pads);
+	/* Setup epdc voltage */
+
+	/* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */
+	gpio_request(IMX_GPIO_NR(2, 13), "EPDC_PWRSTAT");
+	gpio_direction_input(IMX_GPIO_NR(2, 13));
+
+	/* EPDC_VCOM0 - GPIO2[03] for VCOM control */
+	/* Set as output */
+	gpio_request(IMX_GPIO_NR(2, 3), "EPDC_VCOM0");
+	gpio_direction_output(IMX_GPIO_NR(2, 3), 1);
+
+	/* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */
+	/* Set as output */
+	gpio_request(IMX_GPIO_NR(2, 14), "EPDC_PWRWAKEUP");
+	gpio_direction_output(IMX_GPIO_NR(2, 14), 1);
+
+	/* EPDC_PWRCTRL0 - GPIO2[07] for EPD PWR CTL0 */
+	/* Set as output */
+	gpio_request(IMX_GPIO_NR(2, 7), "EPDC_PWRCTRL0");
+	gpio_direction_output(IMX_GPIO_NR(2, 7), 1);
+}
+
+static void epdc_enable_pins(void)
+{
+	/* epdc iomux settings */
+	SETUP_IOMUX_PADS(epdc_enable_pads);
+}
+
+static void epdc_disable_pins(void)
+{
+	/* Configure MUX settings for EPDC pins to GPIO  and drive to 0 */
+	SETUP_IOMUX_PADS(epdc_disable_pads);
+}
+
+static void setup_epdc(void)
+{
+	/* Set pixel clock rates for EPDC in clock.c */
+
+	panel_info.epdc_data.wv_modes.mode_init = 0;
+	panel_info.epdc_data.wv_modes.mode_du = 1;
+	panel_info.epdc_data.wv_modes.mode_gc4 = 3;
+	panel_info.epdc_data.wv_modes.mode_gc8 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc16 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc32 = 2;
+
+	panel_info.epdc_data.epdc_timings = panel_timings;
+
+	setup_epdc_power();
+}
+
+void epdc_power_on(void)
+{
+	unsigned int reg;
+	struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
+
+	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
+	gpio_set_value(IMX_GPIO_NR(2, 7), 1);
+	udelay(1000);
+
+	/* Enable epdc signal pin */
+	epdc_enable_pins();
+
+	/* Set PMIC Wakeup to high - enable Display power */
+	gpio_set_value(IMX_GPIO_NR(2, 14), 1);
+
+	/* Wait for PWRGOOD == 1 */
+	while (1) {
+		reg = readl(&gpio_regs->gpio_psr);
+		if (!(reg & (1 << 13)))
+			break;
+
+		udelay(100);
+	}
+
+	/* Enable VCOM */
+	gpio_set_value(IMX_GPIO_NR(2, 3), 1);
+
+	udelay(500);
+}
+
+void epdc_power_off(void)
+{
+	/* Set PMIC Wakeup to low - disable Display power */
+	gpio_set_value(IMX_GPIO_NR(2, 14), 0);
+
+	/* Disable VCOM */
+	gpio_set_value(IMX_GPIO_NR(2, 3), 0);
+
+	epdc_disable_pins();
+
+	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
+	gpio_set_value(IMX_GPIO_NR(2, 7), 0);
+}
+#endif
+
+
+#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+iomux_v3_cfg_t const usb_otg1_pads[] = {
+	MX6_PAD_KEY_COL4__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_KEY_ROW4__USB_OTG1_OC  | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EPDC_PWR_COM__USB_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usb_otg2_pads[] = {
+	MX6_PAD_KEY_COL5__USB_OTG2_PWR   | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_ECSPI2_SCLK__USB_OTG2_OC | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_EPDC_PWR_IRQ__USB_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+};
+
+int board_usb_phy_mode(int port)
+{
+	return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+
+	switch (port) {
+	case 0:
+		SETUP_IOMUX_PADS(usb_otg1_pads);
+		break;
+	case 1:
+		SETUP_IOMUX_PADS(usb_otg2_pads);
+		break;
+	default:
+		printf("MXC USB port %d not yet supported\n", port);
+		return 1;
+	}
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	/* Set Power polarity */
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
+}
+#endif
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	enable_uart_clk(true);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#ifndef CONFIG_DM_SPI
+	setup_spinor();
+#endif
+#endif
+
+#ifdef	CONFIG_MXC_EPDC
+	enable_epdc_clock();
+	setup_epdc();
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	SETUP_IOMUX_PADS(wdog_pads);
+
+	set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return get_cpu_rev();
+}
+
+int checkboard(void)
+{
+#ifdef CONFIG_LPDDR2_BOARD
+	puts("Board: MX6SLL LPDDR2 VAL\n");
+#else
+	puts("Board: MX6SLL LPDDR3 VAL\n");
+#endif
+
+	return 0;
+}
diff --git a/board/freescale/mx6sll_val/plugin.S b/board/freescale/mx6sll_val/plugin.S
new file mode 100644
index 00000000000..61bc34e5c77
--- /dev/null
+++ b/board/freescale/mx6sll_val/plugin.S
@@ -0,0 +1,285 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6sll_lpddr3_val_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x00080000
+	str r1, [r0, #0x550]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x534]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x2AC]
+	str r1, [r0, #0x548]
+	str r1, [r0, #0x52C]
+	ldr r1, =0x00020000
+	str r1, [r0, #0x530]
+	ldr r1, =0x00003030
+	str r1, [r0, #0x2B0]
+	str r1, [r0, #0x2B4]
+	str r1, [r0, #0x2B8]
+	str r1, [r0, #0x2BC]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x540]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x544]
+	str r1, [r0, #0x54C]
+	str r1, [r0, #0x554]
+	str r1, [r0, #0x558]
+	str r1, [r0, #0x294]
+	str r1, [r0, #0x298]
+	str r1, [r0, #0x29C]
+	str r1, [r0, #0x2A0]
+
+	ldr r1, =0x00082030
+	str r1, [r0, #0x2C0]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1C]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x084700C7
+	str r1, [r0, #0x85C]
+	ldr r1, =0x00400000
+	str r1, [r0, #0x890]
+
+	ldr r1, =0x3C3A3C3C
+	str r1, [r0, #0x848]
+	ldr r1, =0x24293625
+	str r1, [r0, #0x850]
+
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81C]
+	str r1, [r0, #0x820]
+	str r1, [r0, #0x824]
+	str r1, [r0, #0x828]
+
+	ldr r1, =0xf3333333
+	str r1, [r0, #0x82C]
+	str r1, [r0, #0x830]
+	str r1, [r0, #0x834]
+	str r1, [r0, #0x838]
+
+	ldr r1, =0x24922492
+	str r1, [r0, #0x8C0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8B8]
+
+	ldr r1, =0x00020052
+	str r1, [r0, #0x004]
+	ldr r1, =0x53574333
+	str r1, [r0, #0x00C]
+	ldr r1, =0x00100B22
+	str r1, [r0, #0x010]
+	ldr r1, =0x00170778
+	str r1, [r0, #0x038]
+	ldr r1, =0x00C700DB
+	str r1, [r0, #0x014]
+	ldr r1, =0x00201718
+	str r1, [r0, #0x018]
+	ldr r1, =0x0F9F26D2
+	str r1, [r0, #0x02C]
+	ldr r1, =0x009F0E10
+	str r1, [r0, #0x030]
+	ldr r1, =0x0000005F
+	str r1, [r0, #0x040]
+	ldr r1, =0xC4190000
+	str r1, [r0, #0x000]
+
+	ldr r1, =0x00008050
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00008058
+	str r1, [r0, #0x01C]
+	ldr r1, =0x003F8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x003F8038
+	str r1, [r0, #0x01C]
+	ldr r1, =0xFF0A8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0xFF0A8038
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04028030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04028038
+	str r1, [r0, #0x01C]
+	ldr r1, =0x83018030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x83018038
+	str r1, [r0, #0x01C]
+	ldr r1, =0x01038030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x01038038
+	str r1, [r0, #0x01C]
+
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83C]
+
+	ldr r1, =0x00001800
+	str r1, [r0, #0x020]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00020052
+	str r1, [r0, #0x004]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x01C]
+.endm
+
+.macro imx6sll_lpddr2_val_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x00080000
+	str r1, [r0, #0x550]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x534]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x2AC]
+	str r1, [r0, #0x548]
+	str r1, [r0, #0x52C]
+	ldr r1, =0x00020000
+	str r1, [r0, #0x530]
+	ldr r1, =0x00003030
+	str r1, [r0, #0x2B0]
+	str r1, [r0, #0x2B4]
+	str r1, [r0, #0x2B8]
+	str r1, [r0, #0x2BC]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x540]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x544]
+	str r1, [r0, #0x54C]
+	str r1, [r0, #0x554]
+	str r1, [r0, #0x558]
+	str r1, [r0, #0x294]
+	str r1, [r0, #0x298]
+	str r1, [r0, #0x29C]
+	str r1, [r0, #0x2A0]
+
+	ldr r1, =0x00082030
+	str r1, [r0, #0x2C0]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1C]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x084700C7
+	str r1, [r0, #0x85C]
+	ldr r1, =0x00400000
+	str r1, [r0, #0x890]
+
+	ldr r1, =0x3A383C40
+	str r1, [r0, #0x848]
+	ldr r1, =0x242C3020
+	str r1, [r0, #0x850]
+
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81C]
+	str r1, [r0, #0x820]
+	str r1, [r0, #0x824]
+	str r1, [r0, #0x828]
+
+	ldr r1, =0xf3333333
+	str r1, [r0, #0x82C]
+	str r1, [r0, #0x830]
+	str r1, [r0, #0x834]
+	str r1, [r0, #0x838]
+
+	ldr r1, =0x24922492
+	str r1, [r0, #0x8C0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8B8]
+
+	ldr r1, =0x00020052
+	str r1, [r0, #0x004]
+	ldr r1, =0x53574333
+	str r1, [r0, #0x00C]
+	ldr r1, =0x00100A82
+	str r1, [r0, #0x010]
+	ldr r1, =0x00170777
+	str r1, [r0, #0x038]
+	ldr r1, =0x00C70093
+	str r1, [r0, #0x014]
+	ldr r1, =0x00201708
+	str r1, [r0, #0x018]
+	ldr r1, =0x0F9F26D2
+	str r1, [r0, #0x02C]
+	ldr r1, =0x009F0E10
+	str r1, [r0, #0x030]
+	ldr r1, =0x0000004F
+	str r1, [r0, #0x040]
+	ldr r1, =0xC3110000
+	str r1, [r0, #0x000]
+
+	ldr r1, =0x00008050
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00008058
+	str r1, [r0, #0x01C]
+	ldr r1, =0x003F8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x003F8038
+	str r1, [r0, #0x01C]
+	ldr r1, =0xFF0A8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0xFF0A8038
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04028030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04028038
+	str r1, [r0, #0x01C]
+	ldr r1, =0x82018030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x82018038
+	str r1, [r0, #0x01C]
+	ldr r1, =0x01038030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x01038038
+	str r1, [r0, #0x01C]
+
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83C]
+
+	ldr r1, =0x00001800
+	str r1, [r0, #0x020]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00020052
+	str r1, [r0, #0x004]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x01C]
+.endm
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x068]
+	str r1, [r0, #0x06c]
+	str r1, [r0, #0x070]
+	str r1, [r0, #0x074]
+	str r1, [r0, #0x078]
+	str r1, [r0, #0x07c]
+	str r1, [r0, #0x080]
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+#if defined (CONFIG_LPDDR2_BOARD)
+	imx6sll_lpddr2_val_setting
+#else
+	imx6sll_lpddr3_val_setting
+#endif
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/board/freescale/mx6sllevk/Kconfig b/board/freescale/mx6sllevk/Kconfig
index d47f1fa9096..9d1f8c25e5d 100644
--- a/board/freescale/mx6sllevk/Kconfig
+++ b/board/freescale/mx6sllevk/Kconfig
@@ -12,4 +12,6 @@ config SYS_CONFIG_NAME
 config IMX_CONFIG
 	default "board/freescale/mx6sllevk/imximage.cfg"
 
+config SYS_TEXT_BASE
+	default 0x87800000
 endif
diff --git a/board/freescale/mx6sllevk/imximage.cfg b/board/freescale/mx6sllevk/imximage.cfg
index 550be3f6c12..87db25a016a 100644
--- a/board/freescale/mx6sllevk/imximage.cfg
+++ b/board/freescale/mx6sllevk/imximage.cfg
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  *
  * Refer docs/README.imxmage for more details about how-to configure
  * and create imximage boot image
@@ -51,6 +52,11 @@ DATA 4 0x020c4078 0xffffffff
 DATA 4 0x020c407c 0xffffffff
 DATA 4 0x020c4080 0xffffffff
 
+#ifdef CONFIG_IMX_OPTEE
+DATA 4 0x20e4024 0x00000001
+CHECK_BITS_SET 4 0x20e4024 0x1
+#endif
+
 DATA 4 0x020E0550 0x00080000
 DATA 4 0x020E0534 0x00000000
 DATA 4 0x020E02AC 0x00000030
diff --git a/board/freescale/mx6sllevk/mx6sllevk.c b/board/freescale/mx6sllevk/mx6sllevk.c
index b4fddafe640..22e43dffe7c 100644
--- a/board/freescale/mx6sllevk/mx6sllevk.c
+++ b/board/freescale/mx6sllevk/mx6sllevk.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
  */
 
 #include <init.h>
@@ -17,17 +18,32 @@
 #include <asm/io.h>
 #include <common.h>
 #include <linux/sizes.h>
+#include <linux/delay.h>
 #include <mmc.h>
+#include <mxsfb.h>
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 #include "../common/pfuze.h"
 
+#if defined(CONFIG_MXC_EPDC)
+#include <lcd.h>
+#include <mxc_epdc_fb.h>
+#endif
+#include <asm/mach-imx/video.h>
+#include <env.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#define EPDC_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
@@ -58,7 +74,7 @@ int power_init_board(void)
 	u32 switch_num = 6;
 	u32 offset = PFUZE100_SW1CMODE;
 
-	ret = pmic_get("pfuze100@08", &dev);
+	ret = pmic_get("pfuze100@8", &dev);
 	if (ret == -ENODEV)
 		return 0;
 
@@ -92,6 +108,259 @@ int power_init_board(void)
 }
 #endif
 
+#ifdef CONFIG_DM_VIDEO
+static iomux_v3_cfg_t const lcd_pads[] = {
+	MX6_PAD_KEY_ROW5__GPIO4_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_LCD_RESET__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* Use GPIO for Brightness adjustment, duty cycle = period */
+	MX6_PAD_PWM1__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static int setup_lcd(void)
+{
+	int ret;
+
+	ret = enable_lcdif_clock(MX6SLL_LCDIF_BASE_ADDR, 1);
+	if (ret) {
+		printf("Enable LCDIF clock failed, %d\n", ret);
+		return -EPERM;
+	}
+
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+
+	/* Reset the LCD */
+	gpio_request(IMX_GPIO_NR(2, 19), "lcd reset");
+	gpio_direction_output(IMX_GPIO_NR(2, 19) , 0);
+	udelay(500);
+	gpio_direction_output(IMX_GPIO_NR(2, 19) , 1);
+
+	gpio_request(IMX_GPIO_NR(4, 3), "lcd pwr en");
+	gpio_direction_output(IMX_GPIO_NR(4, 3) , 1);
+
+	/* Set Brightness to high */
+	gpio_request(IMX_GPIO_NR(3, 23), "backlight");
+	gpio_direction_output(IMX_GPIO_NR(3, 23) , 1);
+
+	return 0;
+}
+#else
+static inline int setup_lcd(void) { return 0; }
+#endif
+
+#ifdef CONFIG_MXC_EPDC
+static iomux_v3_cfg_t const epdc_enable_pads[] = {
+	MX6_PAD_EPDC_DATA00__EPDC_DATA00	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA01__EPDC_DATA01	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA02__EPDC_DATA02	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA03__EPDC_DATA03	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA04__EPDC_DATA04	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA05__EPDC_DATA05	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA06__EPDC_DATA06	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA07__EPDC_DATA07	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA08__EPDC_DATA08	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA09__EPDC_DATA09	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA10__EPDC_DATA10	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA11__EPDC_DATA11	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA12__EPDC_DATA12	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA13__EPDC_DATA13	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA14__EPDC_DATA14	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_DATA15__EPDC_DATA15	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDCLK__EPDC_SDCLK_P	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDLE__EPDC_SDLE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDOE__EPDC_SDOE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDSHR__EPDC_SDSHR		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_SDCE0__EPDC_SDCE0		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_GDCLK__EPDC_GDCLK		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_GDOE__EPDC_GDOE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_GDRL__EPDC_GDRL		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_EPDC_GDSP__EPDC_GDSP		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const epdc_disable_pads[] = {
+	MX6_PAD_EPDC_DATA01__GPIO1_IO08,
+	MX6_PAD_EPDC_DATA02__GPIO1_IO09,
+	MX6_PAD_EPDC_DATA03__GPIO1_IO10,
+	MX6_PAD_EPDC_DATA04__GPIO1_IO11,
+	MX6_PAD_EPDC_DATA05__GPIO1_IO12,
+	MX6_PAD_EPDC_DATA06__GPIO1_IO13,
+	MX6_PAD_EPDC_DATA07__GPIO1_IO14,
+	MX6_PAD_EPDC_DATA08__GPIO1_IO15,
+	MX6_PAD_EPDC_DATA09__GPIO1_IO16,
+	MX6_PAD_EPDC_DATA10__GPIO1_IO17,
+	MX6_PAD_EPDC_DATA11__GPIO1_IO18,
+	MX6_PAD_EPDC_DATA12__GPIO1_IO19,
+	MX6_PAD_EPDC_DATA13__GPIO1_IO20,
+	MX6_PAD_EPDC_DATA14__GPIO1_IO21,
+	MX6_PAD_EPDC_DATA15__GPIO1_IO22,
+	MX6_PAD_EPDC_SDCLK__GPIO1_IO23,
+	MX6_PAD_EPDC_SDLE__GPIO1_IO24,
+	MX6_PAD_EPDC_SDOE__GPIO1_IO25,
+	MX6_PAD_EPDC_SDSHR__GPIO1_IO26,
+	MX6_PAD_EPDC_SDCE0__GPIO1_IO27,
+	MX6_PAD_EPDC_GDCLK__GPIO1_IO31,
+	MX6_PAD_EPDC_GDOE__GPIO2_IO00,
+	MX6_PAD_EPDC_GDRL__GPIO2_IO01,
+	MX6_PAD_EPDC_GDSP__GPIO2_IO02,
+};
+
+vidinfo_t panel_info = {
+	.vl_refresh = 85,
+	.vl_col = 1024,
+	.vl_row = 758,
+	.vl_pixclock = 40000000,
+	.vl_left_margin = 12,
+	.vl_right_margin = 76,
+	.vl_upper_margin = 4,
+	.vl_lower_margin = 5,
+	.vl_hsync = 12,
+	.vl_vsync = 2,
+	.vl_sync = 0,
+	.vl_mode = 0,
+	.vl_flag = 0,
+	.vl_bpix = 3,
+	.cmap = 0,
+};
+
+struct epdc_timing_params panel_timings = {
+	.vscan_holdoff = 4,
+	.sdoed_width = 10,
+	.sdoed_delay = 20,
+	.sdoez_width = 10,
+	.sdoez_delay = 20,
+	.gdclk_hp_offs = 524,
+	.gdsp_offs = 327,
+	.gdoe_offs = 0,
+	.gdclk_offs = 19,
+	.num_ce = 1,
+};
+
+static void setup_epdc_power(void)
+{
+	/* Setup epdc voltage */
+
+	/* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */
+	imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_STAT__GPIO2_IO13 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+	gpio_request(IMX_GPIO_NR(2, 13), "epdc_pwrstat");
+	gpio_direction_input(IMX_GPIO_NR(2, 13));
+
+	/* EPDC_VCOM0 - GPIO2[03] for VCOM control */
+	imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO2_IO03 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* Set as output */
+	gpio_request(IMX_GPIO_NR(2, 3), "epdc_vcom0");
+	gpio_direction_output(IMX_GPIO_NR(2, 3), 1);
+
+	/* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */
+	imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_WAKE__GPIO2_IO14 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+	/* Set as output */
+	gpio_request(IMX_GPIO_NR(2, 14), "epdc_pwr_wake");
+	gpio_direction_output(IMX_GPIO_NR(2, 14), 1);
+
+	/* EPDC_PWRCTRL0 - GPIO2[07] for EPD PWR CTL0 */
+	imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+	/* Set as output */
+	gpio_request(IMX_GPIO_NR(2, 7), "epdc_pwr_ctrl0");
+	gpio_direction_output(IMX_GPIO_NR(2, 7), 1);
+}
+
+static void epdc_enable_pins(void)
+{
+	/* epdc iomux settings */
+	imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
+				ARRAY_SIZE(epdc_enable_pads));
+}
+
+static void epdc_disable_pins(void)
+{
+	/* Configure MUX settings for EPDC pins to GPIO  and drive to 0 */
+	imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
+				ARRAY_SIZE(epdc_disable_pads));
+}
+
+static void setup_epdc(void)
+{
+	/*** epdc Maxim PMIC settings ***/
+
+	/* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */
+	imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_STAT__GPIO2_IO13 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* EPDC_VCOM0 - GPIO2[03] for VCOM control */
+	imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO2_IO03 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */
+	imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_WAKE__GPIO2_IO14 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* EPDC_PWRCTRL0 - GPIO2[07] for EPD PWR CTL0 */
+	imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* Set pixel clock rates for EPDC in clock.c */
+
+	panel_info.epdc_data.wv_modes.mode_init = 0;
+	panel_info.epdc_data.wv_modes.mode_du = 1;
+	panel_info.epdc_data.wv_modes.mode_gc4 = 3;
+	panel_info.epdc_data.wv_modes.mode_gc8 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc16 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc32 = 2;
+
+	panel_info.epdc_data.epdc_timings = panel_timings;
+
+	setup_epdc_power();
+}
+
+void epdc_power_on(void)
+{
+	unsigned int reg;
+	struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
+
+	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
+	gpio_set_value(IMX_GPIO_NR(2, 7), 1);
+	udelay(1000);
+
+	/* Enable epdc signal pin */
+	epdc_enable_pins();
+
+	/* Set PMIC Wakeup to high - enable Display power */
+	gpio_set_value(IMX_GPIO_NR(2, 14), 1);
+
+	/* Wait for PWRGOOD == 1 */
+	while (1) {
+		reg = readl(&gpio_regs->gpio_psr);
+		if (!(reg & (1 << 13)))
+			break;
+
+		udelay(100);
+	}
+
+	/* Enable VCOM */
+	gpio_set_value(IMX_GPIO_NR(2, 3), 1);
+
+	udelay(500);
+}
+
+void epdc_power_off(void)
+{
+	/* Set PMIC Wakeup to low - disable Display power */
+	gpio_set_value(IMX_GPIO_NR(2, 14), 0);
+
+	/* Disable VCOM */
+	gpio_set_value(IMX_GPIO_NR(2, 3), 0);
+
+	epdc_disable_pins();
+
+	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
+	gpio_set_value(IMX_GPIO_NR(2, 7), 0);
+}
+#endif
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -104,13 +373,32 @@ int board_init(void)
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef	CONFIG_MXC_EPDC
+	enable_epdc_clock();
+	setup_epdc();
+#endif
+
 	return 0;
 }
 
 int board_late_init(void)
 {
+
+	env_set("tee", "no");
+#ifdef CONFIG_IMX_OPTEE
+	env_set("tee", "yes");
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	setup_lcd();
+
 	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 
+	set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
+
 	return 0;
 }
 
@@ -120,13 +408,3 @@ int checkboard(void)
 
 	return 0;
 }
-
-int board_mmc_get_env_dev(int devno)
-{
-	return devno;
-}
-
-int mmc_map_to_kernel_blk(int devno)
-{
-	return devno;
-}
diff --git a/board/freescale/mx6sx_17x17_val/Kconfig b/board/freescale/mx6sx_17x17_val/Kconfig
new file mode 100644
index 00000000000..07a3e7a5def
--- /dev/null
+++ b/board/freescale/mx6sx_17x17_val/Kconfig
@@ -0,0 +1,23 @@
+if TARGET_MX6SX_17X17_VAL || TARGET_MX6SX_14X14_VAL
+
+config SYS_BOARD
+	default "mx6sx_17x17_val"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx6sx_17x17_val"
+
+config SYS_TEXT_BASE
+	default 0x87800000
+
+config LPDDR2_BOARD
+	bool "Select for the board using LPDDR2 not default DDR3"
+
+config NOR
+	bool "Support for NOR flash"
+	help
+	  The i.MX SoC supports having a NOR flash connected to the WEIM.
+	  Need to set this for NOR_BOOT.
+endif
diff --git a/board/freescale/mx6sx_17x17_val/Makefile b/board/freescale/mx6sx_17x17_val/Makefile
new file mode 100644
index 00000000000..b44bb36c4fd
--- /dev/null
+++ b/board/freescale/mx6sx_17x17_val/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx6sx_17x17_val.o
diff --git a/board/freescale/mx6sx_17x17_val/imximage.cfg b/board/freescale/mx6sx_17x17_val/imximage.cfg
new file mode 100644
index 00000000000..27e1946500e
--- /dev/null
+++ b/board/freescale/mx6sx_17x17_val/imximage.cfg
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_QSPI_BOOT
+BOOT_FROM	qspi
+#elif defined(CONFIG_NOR_BOOT)
+BOOT_FROM	nor
+#else
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6sx_17x17_val/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+DATA 4 0x020e0618 0x000c0000
+DATA 4 0x020e05fc 0x00000000
+DATA 4 0x020e032c 0x00000030
+
+DATA 4 0x020e0300 0x00000030
+DATA 4 0x020e02fc 0x00000030
+DATA 4 0x020e05f4 0x00000030
+DATA 4 0x020e0340 0x00000030
+
+DATA 4 0x020e0320 0x00000000
+DATA 4 0x020e0310 0x00000030
+DATA 4 0x020e0314 0x00000030
+DATA 4 0x020e0614 0x00000030
+
+DATA 4 0x020e05f8 0x00020000
+DATA 4 0x020e0330 0x00000030
+DATA 4 0x020e0334 0x00000030
+DATA 4 0x020e0338 0x00000030
+DATA 4 0x020e033c 0x00000030
+DATA 4 0x020e0608 0x00020000
+DATA 4 0x020e060c 0x00000030
+DATA 4 0x020e0610 0x00000030
+DATA 4 0x020e061c 0x00000030
+DATA 4 0x020e0620 0x00000030
+DATA 4 0x020e02ec 0x00000030
+DATA 4 0x020e02f0 0x00000030
+DATA 4 0x020e02f4 0x00000030
+DATA 4 0x020e02f8 0x00000030
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x00270025
+DATA 4 0x021b0810 0x001B001E
+DATA 4 0x021b083c 0x4144013C
+DATA 4 0x021b0840 0x01300128
+DATA 4 0x021b0848 0x4044464A
+DATA 4 0x021b0850 0x3A383C34
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x00333030
+DATA 4 0x021b000c 0x676b52f3
+DATA 4 0x021b0010 0xb66d8b63
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00011740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006b1023
+DATA 4 0x021b0040 0x0000005f
+DATA 4 0x021b0000 0x84190000
+DATA 4 0x021b001c 0x04008032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00068031
+DATA 4 0x021b001c 0x05208030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00000800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b001c 0x00000000
+
+#endif
diff --git a/board/freescale/mx6sx_17x17_val/imximage_wp.cfg b/board/freescale/mx6sx_17x17_val/imximage_wp.cfg
new file mode 100644
index 00000000000..710c705d10e
--- /dev/null
+++ b/board/freescale/mx6sx_17x17_val/imximage_wp.cfg
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_QSPI_BOOT
+BOOT_FROM	qspi
+#elif defined(CONFIG_NOR_BOOT)
+BOOT_FROM	nor
+#else
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+DATA 4 0x020e0618 0x000c0000
+DATA 4 0x020e05fc 0x00000000
+DATA 4 0x020e032c 0x00000030
+
+DATA 4 0x020e0300 0x00000030
+DATA 4 0x020e02fc 0x00000030
+DATA 4 0x020e05f4 0x00000030
+DATA 4 0x020e0340 0x00000030
+
+DATA 4 0x020e0320 0x00000000
+DATA 4 0x020e0310 0x00000030
+DATA 4 0x020e0314 0x00000030
+DATA 4 0x020e0614 0x00000030
+
+DATA 4 0x020e05f8 0x00020000
+DATA 4 0x020e0330 0x00000030
+DATA 4 0x020e0334 0x00000030
+DATA 4 0x020e0338 0x00000030
+DATA 4 0x020e033c 0x00000030
+DATA 4 0x020e0608 0x00020000
+DATA 4 0x020e060c 0x00000030
+DATA 4 0x020e0610 0x00000030
+DATA 4 0x020e061c 0x00000030
+DATA 4 0x020e0620 0x00000030
+DATA 4 0x020e02ec 0x00000030
+DATA 4 0x020e02f0 0x00000030
+DATA 4 0x020e02f4 0x00000030
+DATA 4 0x020e02f8 0x00000030
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x002E003C
+DATA 4 0x021b0810 0x001A003F
+DATA 4 0x021b083c 0x41480150
+DATA 4 0x021b0840 0x012C0150
+DATA 4 0x021b0848 0x40404646
+DATA 4 0x021b0850 0x38363C32
+DATA 4 0x021b08c0 0x2492244A
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x00333030
+DATA 4 0x021b000c 0x676b52f3
+DATA 4 0x021b0010 0xb66d8b63
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00011740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006b1023
+DATA 4 0x021b0040 0x0000005f
+DATA 4 0x021b0000 0x84190000
+DATA 4 0x021b001c 0x04008032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00068031
+DATA 4 0x021b001c 0x05208030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00000800
+DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b0004 0x0002556d
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
diff --git a/board/freescale/mx6sx_17x17_val/mx6sx_14x14_lpddr2_val.cfg b/board/freescale/mx6sx_17x17_val/mx6sx_14x14_lpddr2_val.cfg
new file mode 100644
index 00000000000..dcc9a14ab63
--- /dev/null
+++ b/board/freescale/mx6sx_17x17_val/mx6sx_14x14_lpddr2_val.cfg
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_QSPI_BOOT
+BOOT_FROM	qspi
+#elif defined(CONFIG_NOR_BOOT)
+BOOT_FROM	nor
+#else
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6sx_17x17_val/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+DATA 4 0x020c4018 0x00260324
+
+DATA 4 0x020e0618 0x00080000
+DATA 4 0x020e05fc 0x00000000
+DATA 4 0x020e032c 0x00000030
+
+DATA 4 0x020e0300 0x00000028
+DATA 4 0x020e02fc 0x00000028
+DATA 4 0x020e05f4 0x00000028
+DATA 4 0x020e0340 0x00000028
+
+DATA 4 0x020e0320 0x00000000
+DATA 4 0x020e0310 0x00000000
+DATA 4 0x020e0314 0x00000000
+DATA 4 0x020e0614 0x00000028
+
+DATA 4 0x020e05f8 0x00020000
+DATA 4 0x020e0330 0x00003028
+DATA 4 0x020e0334 0x00003028
+DATA 4 0x020e0338 0x00003028
+DATA 4 0x020e033c 0x00003028
+
+DATA 4 0x020e0608 0x00020000
+DATA 4 0x020e060c 0x00000028
+DATA 4 0x020e0610 0x00000028
+DATA 4 0x020e061c 0x00000028
+DATA 4 0x020e0620 0x00000028
+
+DATA 4 0x020e02ec 0x00000028
+DATA 4 0x020e02f0 0x00000028
+DATA 4 0x020e02f4 0x00000028
+DATA 4 0x020e02f8 0x00000028
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b085c 0x1b4700c7
+
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b0890 0x00380000
+DATA 4 0x021b08b8 0x00000800
+
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+DATA 4 0x021b082c 0x51111111
+DATA 4 0x021b0830 0x51111111
+DATA 4 0x021b0834 0x51111111
+DATA 4 0x021b0838 0x51111111
+
+DATA 4 0x021b0848 0x42424244
+
+DATA 4 0x021b0850 0x2E30322E
+DATA 4 0x021b08c0 0x2492244A
+DATA 4 0x021b083c 0x20000000
+DATA 4 0x021b0840 0x0
+
+DATA 4 0x021b08b8 0x00000800
+
+DATA 4 0x021b000c 0x33374133
+DATA 4 0x021b0004 0x00020024
+DATA 4 0x021b0010 0x00100A42
+DATA 4 0x021b0014 0x00000093
+DATA 4 0x021b0018 0x00001748
+DATA 4 0x021b002c 0x0f9f26d2
+DATA 4 0x021b0030 0x0000020e
+DATA 4 0x021b0038 0x00190778
+DATA 4 0x021b0008 0x00000000
+DATA 4 0x021b0040 0x0000004f
+DATA 4 0x021b0000 0xc3110000
+
+DATA 4 0x021b001c 0x00008010
+DATA 4 0x021b001c 0x003f8030
+DATA 4 0x021b001c 0xff0a8030
+DATA 4 0x021b001c 0x82018030
+DATA 4 0x021b001c 0x04028030
+DATA 4 0x021b001c 0x01038030
+
+DATA 4 0x021b001c 0x00008018
+DATA 4 0x021b001c 0x003f8038
+DATA 4 0x021b001c 0xff0a8038
+DATA 4 0x021b001c 0x82018038
+DATA 4 0x021b001c 0x04028038
+DATA 4 0x021b001c 0x01038038
+
+DATA 4 0x021b0020 0x00001800
+DATA 4 0x021b0818 0x00000000
+
+DATA 4 0x021b0800 0xa1310003
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+
+#endif
diff --git a/board/freescale/mx6sx_17x17_val/mx6sx_17x17_val.c b/board/freescale/mx6sx_17x17_val/mx6sx_17x17_val.c
new file mode 100644
index 00000000000..3eb7830e711
--- /dev/null
+++ b/board/freescale/mx6sx_17x17_val/mx6sx_17x17_val.c
@@ -0,0 +1,803 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#ifdef CONFIG_SYS_I2C_MXC
+#include <i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#endif
+#include <asm/arch/crm_regs.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#include <dm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_SPEED_MED   |                                   \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
+	PAD_CTL_SPEED_MED   | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE)
+
+#define EPDC_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+			PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
+	PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define WEIM_NOR_PAD_CTRL2 (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm)
+
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
+		.gp = IMX_GPIO_NR(1, 0),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
+		.gp = IMX_GPIO_NR(1, 1),
+	},
+};
+
+/* I2C2 */
+struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
+		.gp = IMX_GPIO_NR(1, 2),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
+		.gp = IMX_GPIO_NR(1, 3),
+	},
+};
+#endif
+
+#ifdef CONFIG_POWER_LEGACY
+#define I2C_PMIC 0
+int power_init_board(void)
+{
+	struct pmic *pfuze;
+	unsigned int reg;
+	int ret;
+
+	pfuze = pfuze_common_init(I2C_PMIC);
+	if (!pfuze)
+		return -ENODEV;
+
+	ret = pfuze_mode_init(pfuze, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	/* set SW1AB staby volatage 0.975V */
+	pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= PFUZE100_SW1ABC_SETP(9750);
+	pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);
+
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);
+
+	/* set SW1C staby volatage 0.975V */
+	pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= PFUZE100_SW1ABC_SETP(9750);
+	pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
+
+	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+	pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
+
+	return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+	unsigned int value;
+	int is_400M;
+	u32 vddarm;
+	struct pmic *p = pmic_get("PFUZE100");
+
+	if (!p) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* switch to ldo_bypass mode */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+		/* decrease VDDARM to 1.275V */
+		pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+		value &= ~0x3f;
+		value |= PFUZE100_SW1ABC_SETP(12750);
+		pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+
+		/* decrease VDDSOC to 1.3V */
+		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+		value &= ~0x3f;
+		value |= PFUZE100_SW1ABC_SETP(13000);
+		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+		is_400M = set_anatop_bypass(1);
+		if (is_400M)
+			vddarm = PFUZE100_SW1ABC_SETP(10750);
+		else
+			vddarm = PFUZE100_SW1ABC_SETP(11750);
+
+		pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+		value &= ~0x3f;
+		value |= vddarm;
+		pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+
+		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+		value &= ~0x3f;
+		value |= PFUZE100_SW1ABC_SETP(11750);
+		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+		finish_anatop_bypass();
+		printf("switch to ldo_bypass mode!\n");
+	}
+
+}
+#endif
+
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	dev = pfuze_common_init();
+	if (!dev)
+		return -ENODEV;
+
+	ret = pfuze_mode_init(dev, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+	struct udevice *dev;
+	int ret;
+	int is_400M;
+	u32 vddarm;
+
+	ret = pmic_get("pfuze100@8", &dev);
+	if (ret == -ENODEV) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* switch to ldo_bypass mode , boot on 800Mhz */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+
+		/* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750));
+
+		/* increase VDDSOC to 1.3V */
+		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(13000));
+
+		is_400M = set_anatop_bypass(1);
+		if (is_400M)
+			vddarm = PFUZE100_SW1ABC_SETP(10750);
+		else
+			vddarm = PFUZE100_SW1ABC_SETP(11750);
+
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
+
+		/* decrease VDDSOC to 1.175V */
+		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(11750));
+
+		finish_anatop_bypass();
+		printf("switch to ldo_bypass mode!\n");
+	}
+}
+#endif
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#ifndef CONFIG_MXC_SPI
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+#endif
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/*CD pin*/
+	MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+	MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+#ifdef CONFIG_FEC_MXC
+static iomux_v3_cfg_t const fec1_pads[] = {
+	MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	/* AR8031 PHY Reset. For validation board, silder the resistance */
+	MX6_PAD_QSPI1A_SS0_B__GPIO4_IO_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_fec1(void)
+{
+	SETUP_IOMUX_PADS(fec1_pads);
+}
+#endif
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+}
+
+#ifdef CONFIG_FSL_QSPI
+#ifndef CONFIG_DM_SPI
+#define QSPI_PAD_CTRL1  \
+		(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
+		PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
+
+#define QSPI_PAD_CTRL2 (QSPI_PAD_CTRL1 | PAD_CTL_DSE_34ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+	MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2		| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3		| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA02__QSPI2_B_SCLK		| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+
+};
+#endif
+
+int board_qspi_init(void)
+{
+#ifndef CONFIG_DM_SPI
+	/* Set the iomux */
+	SETUP_IOMUX_PADS(quadspi_pads);
+#endif
+
+	/* Set the clock */
+	enable_qspi_clk(1);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+	{USDHC2_BASE_ADDR, 0, 4},
+	{USDHC3_BASE_ADDR},
+	{USDHC4_BASE_ADDR},
+};
+
+#define USDHC3_CD_GPIO	IMX_GPIO_NR(2, 10)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC2_BASE_ADDR:
+		ret = 1; /*always present */
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC3_CD_GPIO);
+		break;
+	case USDHC4_BASE_ADDR:
+		ret = 1; /*always present */
+		break;
+	}
+
+	return ret;
+}
+
+#ifdef CONFIG_MXC_SPI
+int board_mmc_init(struct bd_info *bis)
+{
+	int i;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * mmc0                    SD3 (SDB)
+	 * mmc1                    eMMC
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc3_pads);
+			gpio_request(USDHC3_CD_GPIO, "usdhc3 cd");
+			gpio_direction_input(USDHC3_CD_GPIO);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			break;
+		case 1:
+			SETUP_IOMUX_PADS(usdhc4_pads);
+			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return 0;
+		}
+
+		if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+	}
+
+	return 0;
+}
+
+#else
+int board_mmc_init(struct bd_info *bis)
+{
+	int i;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * mmc0                    SD2 (SDA)
+	 * mmc1                    SD3 (SDB)
+	 * mmc2                    eMMC
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc2_pads);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			break;
+		case 1:
+			SETUP_IOMUX_PADS(usdhc3_pads);
+			gpio_request(USDHC3_CD_GPIO, "usdhc3 cd");
+			gpio_direction_input(USDHC3_CD_GPIO);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			break;
+		case 2:
+			SETUP_IOMUX_PADS(usdhc4_pads);
+			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return 0;
+		}
+
+		if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+	}
+
+	return 0;
+}
+#endif
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+iomux_v3_cfg_t eimnor_pads[] = {
+	MX6_PAD_NAND_DATA00__WEIM_AD_0     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA01__WEIM_AD_1     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA02__WEIM_AD_2     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA03__WEIM_AD_3     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA04__WEIM_AD_4     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA05__WEIM_AD_5     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA06__WEIM_AD_6     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA07__WEIM_AD_7     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA08__WEIM_AD_8     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA09__WEIM_AD_9     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA10__WEIM_AD_10    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA11__WEIM_AD_11    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
+	MX6_PAD_LCD1_DATA12__WEIM_AD_12    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA13__WEIM_AD_13    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA14__WEIM_AD_14    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA15__WEIM_AD_15    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA16__WEIM_ADDR_16  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA17__WEIM_ADDR_17  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA18__WEIM_ADDR_18  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA19__WEIM_ADDR_19  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA20__WEIM_ADDR_20  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA21__WEIM_ADDR_21  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA22__WEIM_ADDR_22  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA23__WEIM_ADDR_23  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA03__WEIM_ADDR_24  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA04__WEIM_ADDR_25  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+
+	MX6_PAD_NAND_CE0_B__WEIM_LBA_B     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_CE1_B__WEIM_OE        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_RE_B__WEIM_RW         | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_WE_B__WEIM_WAIT       | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	MX6_PAD_NAND_ALE__WEIM_CS0_B       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+};
+static void eimnor_cs_setup(void)
+{
+	writel(0x00000120, WEIM_BASE_ADDR + 0x090);
+	writel(0x00610089, WEIM_BASE_ADDR + 0x000);
+	writel(0x00000001, WEIM_BASE_ADDR + 0x004);
+	writel(0x1c022000, WEIM_BASE_ADDR + 0x008);
+	writel(0x00000000, WEIM_BASE_ADDR + 0x00c);
+	writel(0x1404a38e, WEIM_BASE_ADDR + 0x010);
+}
+
+static void setup_eimnor(void)
+{
+	SETUP_IOMUX_PADS(eimnor_pads);
+
+	eimnor_cs_setup();
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+iomux_v3_cfg_t gpmi_pads[] = {
+	MX6_PAD_NAND_CLE__RAWNAND_CLE		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_ALE__RAWNAND_ALE		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WP_B__RAWNAND_WP_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_READY_B__RAWNAND_READY_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL0),
+	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_RE_B__RAWNAND_RE_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WE_B__RAWNAND_WE_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA00__RAWNAND_DATA00	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA01__RAWNAND_DATA01	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA02__RAWNAND_DATA02	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA03__RAWNAND_DATA03	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA04__RAWNAND_DATA04	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA05__RAWNAND_DATA05	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA06__RAWNAND_DATA06	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA07__RAWNAND_DATA07	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+};
+
+static void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	SETUP_IOMUX_PADS(gpmi_pads);
+
+	setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
+			MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |
+			MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+int board_eth_init(struct bd_info *bis)
+{
+	int ret;
+
+	setup_iomux_fec1();
+
+	ret = fecmxc_initialize_multi(bis, 0,
+		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+	if (ret)
+		printf("FEC1 MXC: %s:failed\n", __func__);
+
+	return 0;
+}
+
+#define MAX7322_I2C_ADDR		0x68
+#define MAX7322_I2C_BUS		1
+
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+	int ret;
+	unsigned char value = 1;
+
+	/* clear gpr1[13], gpr1[17] to select anatop clock */
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
+
+	ret = enable_fec_anatop_clock(0, ENET_125MHZ);
+	if (ret)
+		return ret;
+
+/* Reset AR8031 PHY */
+	gpio_request(IMX_GPIO_NR(4, 22), "ar8031 reset");
+	gpio_direction_output(IMX_GPIO_NR(4, 22) , 0);
+	udelay(500);
+	gpio_set_value(IMX_GPIO_NR(4, 22), 1);
+
+#ifdef CONFIG_DM_I2C
+	struct udevice *bus, *dev;
+	ret = uclass_get_device_by_seq(UCLASS_I2C, MAX7322_I2C_BUS - 1, &bus);
+	if (ret) {
+		printf("Get i2c bus %u failed, ret = %d\n", MAX7322_I2C_BUS - 1, ret);
+		return ret;
+	}
+
+	ret = dm_i2c_probe(bus, MAX7322_I2C_ADDR, 0, &dev);
+	if (ret) {
+		printf("MAX7322 Not found, ret = %d\n", ret);
+		return ret;
+	}
+
+	/* Write 0x1 to enable O0 output, this device has no addr */
+	/* hence addr length is 0 */
+	value = 0x1;
+	ret = dm_i2c_write(dev, 0, &value, 1);
+	if (ret) {
+		printf("MAX7322 write failed, ret = %d\n", ret);
+		return ret;
+	}
+#else
+	/* This is needed to drive the pads to 1.8V instead of 1.5V */
+	i2c_set_bus_num(MAX7322_I2C_BUS);
+
+	if (!i2c_probe(MAX7322_I2C_ADDR)) {
+		/* Write 0x1 to enable O0 output, this device has no addr */
+		/* hence addr length is 0 */
+		value = 0x1;
+		if (i2c_write(MAX7322_I2C_ADDR, 0, 0, &value, 1))
+			printf("MAX7322 write failed\n");
+	} else {
+		printf("MAX7322 Not found\n");
+	}
+#endif
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+#ifdef CONFIG_FEC_ENABLE_MAX7322
+	/* Enable 1.8V(SEL_1P5_1P8_POS_REG) on
+	   Phy control debug reg 0 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+#endif
+
+	/* rgmii tx clock delay enable */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+
+iomux_v3_cfg_t const usb_otg_pads[] = {
+	/*Only enable OTG1, the OTG2 has pin conflicts with PWM and WDOG*/
+	MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+};
+
+static void setup_usb(void)
+{
+	SETUP_IOMUX_PADS(usb_otg_pads);
+}
+
+int board_usb_phy_mode(int port)
+{
+	return USB_INIT_HOST;
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port >= 1)
+		return -EINVAL;
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	/* Set Power polarity */
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
+}
+#endif
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+	setup_eimnor();
+#endif
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+	setup_usb();
+#endif
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	{"emmc", MAKE_CFGVAL(0x60, 0x38, 0x00, 0x00)},
+	{"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)},
+	{"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x0B)},
+	{"nand", MAKE_CFGVAL(0x80, 0x00, 0x00, 0x00)},
+	{NULL,   0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return get_cpu_rev();
+}
+
+int checkboard(void)
+{
+#ifdef CONFIG_TARGET_MX6SX_14X14_VAL
+	puts("Board: MX6SX 14x14 VAL\n");
+#else
+	puts("Board: MX6SX 17x17 VAL\n");
+#endif
+
+	return 0;
+}
diff --git a/board/freescale/mx6sx_17x17_val/plugin.S b/board/freescale/mx6sx_17x17_val/plugin.S
new file mode 100644
index 00000000000..1b739b3fae3
--- /dev/null
+++ b/board/freescale/mx6sx_17x17_val/plugin.S
@@ -0,0 +1,281 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6sx_17x17_ddr3_evk_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x618]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x5fc]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x32c]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x300]
+	str r1, [r0, #0x2fc]
+	str r1, [r0, #0x5f4]
+	str r1, [r0, #0x340]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x320]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x310]
+	str r1, [r0, #0x314]
+	str r1, [r0, #0x614]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x5f8]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x330]
+	str r1, [r0, #0x334]
+	str r1, [r0, #0x338]
+	str r1, [r0, #0x33c]
+	ldr r1, =0x00020000
+	str r1, [r0, #0x608]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x60c]
+	str r1, [r0, #0x610]
+	str r1, [r0, #0x61c]
+	str r1, [r0, #0x620]
+	str r1, [r0, #0x2ec]
+	str r1, [r0, #0x2f0]
+	str r1, [r0, #0x2f4]
+	str r1, [r0, #0x2f8]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+	ldr r2, =0x00270025
+	str r2, [r0, #0x80c]
+	ldr r2, =0x001B001E
+	str r2, [r0, #0x810]
+	ldr r2, =0x4144013C
+	str r2, [r0, #0x83c]
+	ldr r2, =0x01300128
+	str r2, [r0, #0x840]
+	ldr r2, =0x4044464A
+	str r2, [r0, #0x848]
+	ldr r2, =0x3A383C34
+	str r2, [r0, #0x850]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	ldr r2, =0x0002002d
+	str r2, [r0, #0x004]
+	ldr r2, =0x00333030
+	str r2, [r0, #0x008]
+	ldr r2, =0x676b52f3
+	str r2, [r0, #0x00c]
+	ldr r2, =0xb66d8b63
+	str r2, [r0, #0x010]
+	ldr r2, =0x01ff00db
+	str r2, [r0, #0x014]
+	ldr r2, =0x00011740
+	str r2, [r0, #0x018]
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x006b1023
+	str r2, [r0, #0x030]
+	ldr r2, =0x0000005f
+	str r2, [r0, #0x040]
+	ldr r2, =0x84190000
+	str r2, [r0, #0x000]
+	ldr r2, =0x04008032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00068031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x05208030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00000800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00011117
+	str r2, [r0, #0x818]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+
+.endm
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x068]
+	str r1, [r0, #0x06c]
+	str r1, [r0, #0x070]
+	str r1, [r0, #0x074]
+	str r1, [r0, #0x078]
+	str r1, [r0, #0x07c]
+	str r1, [r0, #0x080]
+	str r1, [r0, #0x084]
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6sx_14x14_lpddr2_val_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x00080000
+	str r1, [r0, #0x618]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x5fc]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x32c]
+
+	ldr r1, =0x00000028
+	str r1, [r0, #0x300]
+	str r1, [r0, #0x2fc]
+	str r1, [r0, #0x5f4]
+	str r1, [r0, #0x340]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x320]
+	str r1, [r0, #0x310]
+	str r1, [r0, #0x314]
+	ldr r1, =0x00000028
+	str r1, [r0, #0x614]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x5f8]
+	ldr r1, =0x00003028
+	str r1, [r0, #0x330]
+	str r1, [r0, #0x334]
+	str r1, [r0, #0x338]
+	str r1, [r0, #0x33c]
+	ldr r1, =0x00020000
+	str r1, [r0, #0x608]
+	ldr r1, =0x00000028
+	str r1, [r0, #0x60c]
+	str r1, [r0, #0x610]
+	str r1, [r0, #0x61c]
+	str r1, [r0, #0x620]
+	str r1, [r0, #0x2ec]
+	str r1, [r0, #0x2f0]
+	str r1, [r0, #0x2f4]
+	str r1, [r0, #0x2f8]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0x00008000
+	str r2, [r0, #0x1c]
+	ldr r2, =0x1b4700c7
+	str r2, [r0, #0x85c]
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+	ldr r2, =0x00380000
+	str r2, [r0, #0x890]
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+
+	ldr r2, =0x51111111
+	str r2, [r0, #0x82c]
+	str r2, [r0, #0x830]
+	str r2, [r0, #0x834]
+	str r2, [r0, #0x838]
+
+	ldr r2, =0x42424244
+	str r2, [r0, #0x848]
+	ldr r2, =0x2E30322E
+	str r2, [r0, #0x850]
+	ldr r2, =0x2492244A
+	str r2, [r0, #0x8c0]
+	ldr r2, =0x20000000
+	str r2, [r0, #0x83c]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x840]
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+
+	ldr r2, =0x33374133
+	str r2, [r0, #0x00c]
+	ldr r2, =0x00020024
+	str r2, [r0, #0x004]
+	ldr r2, =0x00100A42
+	str r2, [r0, #0x010]
+	ldr r2, =0x00000093
+	str r2, [r0, #0x014]
+	ldr r2, =0x00001748
+	str r2, [r0, #0x018]
+	ldr r2, =0x0f9f26d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x0000020e
+	str r2, [r0, #0x030]
+	ldr r2, =0x00190778
+	str r2, [r0, #0x038]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x008]
+	ldr r2, =0x0000004f
+	str r2, [r0, #0x040]
+	ldr r2, =0xc3110000
+	str r2, [r0, #0x000]
+
+	ldr r2, =0x00008010
+	str r2, [r0, #0x01c]
+	ldr r2, =0x003f8030
+	str r2, [r0, #0x01c]
+	ldr r2, =0xff0a8030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x82018030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04028030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x01038030
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00008018
+	str r2, [r0, #0x01c]
+	ldr r2, =0x003f8038
+	str r2, [r0, #0x01c]
+	ldr r2, =0xff0a8038
+	str r2, [r0, #0x01c]
+	ldr r2, =0x82018038
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04028038
+	str r2, [r0, #0x01c]
+	ldr r2, =0x01038038
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00001800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x818]
+	ldr r2, =0xa1310003
+	str r2, [r0, #0x800]
+	ldr r2, =0x00025576
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+.endm
+
+.macro imx6_ddr_setting
+#if defined(CONFIG_TARGET_MX6SX_14X14_VAL) && defined (CONFIG_LPDDR2_BOARD)
+	imx6sx_14x14_lpddr2_val_ddr_setting
+#else
+	imx6sx_17x17_ddr3_evk_ddr_setting
+#endif
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/board/freescale/mx6sx_19x19_val/Kconfig b/board/freescale/mx6sx_19x19_val/Kconfig
new file mode 100644
index 00000000000..2e3f14fc252
--- /dev/null
+++ b/board/freescale/mx6sx_19x19_val/Kconfig
@@ -0,0 +1,23 @@
+if TARGET_MX6SX_19X19_VAL
+
+config SYS_BOARD
+	default "mx6sx_19x19_val"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx6sx_19x19_val"
+
+config SYS_TEXT_BASE
+	default 0x87800000
+
+config LPDDR2_BOARD
+	bool "Select for the board using LPDDR2 not default DDR3"
+
+config NOR
+	bool "Support for NOR flash"
+	help
+	  The i.MX SoC supports having a NOR flash connected to the WEIM.
+	  Need to set this for NOR_BOOT.
+endif
diff --git a/board/freescale/mx6sx_19x19_val/Makefile b/board/freescale/mx6sx_19x19_val/Makefile
new file mode 100644
index 00000000000..eec06e97eba
--- /dev/null
+++ b/board/freescale/mx6sx_19x19_val/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx6sx_19x19_val.o
diff --git a/board/freescale/mx6sx_19x19_val/imximage.cfg b/board/freescale/mx6sx_19x19_val/imximage.cfg
new file mode 100644
index 00000000000..c3d7a2bd729
--- /dev/null
+++ b/board/freescale/mx6sx_19x19_val/imximage.cfg
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_QSPI_BOOT
+BOOT_FROM	qspi
+#elif defined(CONFIG_NOR_BOOT)
+BOOT_FROM	nor
+#else
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6sx_19x19_val/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+/* IOMUX */
+/* DDR IO TYPE */
+DATA 4 0x020e0618 0x000c0000
+DATA 4 0x020e05fc 0x00000000
+
+/* CLOCK */
+DATA 4 0x020e032c 0x00000030
+
+/* ADDRESS */
+DATA 4 0x020e0300 0x00000030
+DATA 4 0x020e02fc 0x00000030
+DATA 4 0x020e05f4 0x00000030
+
+/* CONTROL */
+DATA 4 0x020e0340 0x00000030
+
+DATA 4 0x020e0320 0x00000000
+DATA 4 0x020e0310 0x00000030
+DATA 4 0x020e0314 0x00000030
+DATA 4 0x020e0614 0x00000030
+
+/* DATA STROBE */
+DATA 4 0x020e05f8 0x00020000
+DATA 4 0x020e0330 0x00000030
+DATA 4 0x020e0334 0x00000030
+DATA 4 0x020e0338 0x00000030
+DATA 4 0x020e033c 0x00000030
+
+/* DATA */
+DATA 4 0x020e0608 0x00020000
+DATA 4 0x020e060c 0x00000030
+DATA 4 0x020e0610 0x00000030
+DATA 4 0x020e061c 0x00000030
+DATA 4 0x020e0620 0x00000030
+DATA 4 0x020e02ec 0x00000030
+DATA 4 0x020e02f0 0x00000030
+DATA 4 0x020e02f4 0x00000030
+DATA 4 0x020e02f8 0x00000030
+
+/* Calibrations */
+/* ZQ */
+DATA 4 0x021b0800 0xa1390003
+/* write leveling */
+DATA 4 0x021b080c 0x002C003D
+DATA 4 0x021b0810 0x00110046
+
+/* DQS Read Gate */
+DATA 4 0x021b083c 0x4160016C
+DATA 4 0x021b0840 0x013C016C
+
+/* Read/Write Delay */
+DATA 4 0x021b0848 0x46424446
+DATA 4 0x021b0850 0x3A3C3C3A
+
+DATA 4 0x021b08c0 0x2492244A
+
+/* read data bit delay */
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+/* Complete calibration by forced measurment */
+DATA 4 0x021b08b8 0x00000800
+
+/* MMDC init */
+/* in DDR3, 64-bit mode, only MMDC0 is initiated */
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x00333030
+DATA 4 0x021b000c 0x676b52f3
+DATA 4 0x021b0010 0xb66d8b63
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00011740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006b1023
+DATA 4 0x021b0040 0x0000007f
+DATA 4 0x021b0000 0x85190000
+
+/* Initialize CS0: MT41K256M16HA-125 */
+/* MR2 */
+DATA 4 0x021b001c 0x04008032
+/* MR3 */
+DATA 4 0x021b001c 0x00008033
+/* MR1 */
+DATA 4 0x021b001c 0x00068031
+/* MR0 */
+DATA 4 0x021b001c 0x05208030
+/* DDR device ZQ calibration */
+DATA 4 0x021b001c 0x04008040
+
+/* final DDR setup, before operation start */
+DATA 4 0x021b0020 0x00000800
+DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b0004 0x0002556d
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+
+#endif
diff --git a/board/freescale/mx6sx_19x19_val/imximage_lpddr2.cfg b/board/freescale/mx6sx_19x19_val/imximage_lpddr2.cfg
new file mode 100644
index 00000000000..218c3d7de6d
--- /dev/null
+++ b/board/freescale/mx6sx_19x19_val/imximage_lpddr2.cfg
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_QSPI_BOOT
+BOOT_FROM	qspi
+#elif defined(CONFIG_NOR_BOOT)
+BOOT_FROM	nor
+#else
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6sx_19x19_val/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+DATA 4 0x020e0618 0x00080000
+DATA 4 0x020e05fc 0x00000000
+DATA 4 0x020e032c 0x00000030
+
+DATA 4 0x020e0300 0x00000028
+DATA 4 0x020e02fc 0x00000028
+DATA 4 0x020e05f4 0x00000028
+DATA 4 0x020e0340 0x00000028
+DATA 4 0x020e0320 0x00000000
+DATA 4 0x020e0310 0x00000000
+DATA 4 0x020e0314 0x00000000
+DATA 4 0x020e0614 0x00000028
+
+DATA 4 0x020e05f8 0x00020000
+DATA 4 0x020e0330 0x00003028
+DATA 4 0x020e0334 0x00003028
+DATA 4 0x020e0338 0x00003028
+DATA 4 0x020e033c 0x00003028
+DATA 4 0x020e0608 0x00020000
+DATA 4 0x020e060c 0x00000028
+DATA 4 0x020e0610 0x00000028
+DATA 4 0x020e061c 0x00000028
+DATA 4 0x020e0620 0x00000028
+DATA 4 0x020e02ec 0x00000028
+DATA 4 0x020e02f0 0x00000028
+DATA 4 0x020e02f4 0x00000028
+DATA 4 0x020e02f8 0x00000028
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b085c 0x1b4700c7
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b0890 0x00380000
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b082c 0x51111111
+DATA 4 0x021b0830 0x51111111
+DATA 4 0x021b0834 0x51111111
+DATA 4 0x021b0838 0x51111111
+DATA 4 0x021b0848 0x42424244
+DATA 4 0x021b0850 0x2E30322E
+DATA 4 0x021b08c0 0x2492244A
+DATA 4 0x021b083c 0x20000000
+DATA 4 0x021b0840 0x00000000
+DATA 4 0x021b08b8 0x00000800
+
+DATA 4 0x021b000c 0x33374133
+DATA 4 0x021b0004 0x00020024
+DATA 4 0x021b0010 0x00100A42
+DATA 4 0x021b0014 0x00000093
+DATA 4 0x021b0018 0x00001748
+DATA 4 0x021b002c 0x0f9f26d2
+DATA 4 0x021b0030 0x0000020e
+DATA 4 0x021b0038 0x00190778
+DATA 4 0x021b0008 0x00000000
+DATA 4 0x021b0040 0x0000004f
+DATA 4 0x021b0000 0xc3110000
+
+DATA 4 0x021b001c 0x00008010
+DATA 4 0x021b001c 0x003f8030
+DATA 4 0x021b001c 0xff0a8030
+DATA 4 0x021b001c 0x82018030
+DATA 4 0x021b001c 0x04028030
+DATA 4 0x021b001c 0x01038030
+
+DATA 4 0x021b001c 0x00008018
+DATA 4 0x021b001c 0x003f8038
+DATA 4 0x021b001c 0xff0a8038
+DATA 4 0x021b001c 0x82018038
+DATA 4 0x021b001c 0x04028038
+DATA 4 0x021b001c 0x01038038
+
+DATA 4 0x021b0020 0x00001800
+DATA 4 0x021b0818 0x00000000
+DATA 4 0x021b0800 0xa1310003
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+
+#endif
diff --git a/board/freescale/mx6sx_19x19_val/mx6sx_19x19_val.c b/board/freescale/mx6sx_19x19_val/mx6sx_19x19_val.c
new file mode 100644
index 00000000000..d5f911c289d
--- /dev/null
+++ b/board/freescale/mx6sx_19x19_val/mx6sx_19x19_val.c
@@ -0,0 +1,705 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#ifdef CONFIG_SYS_I2C_MXC
+#include <i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#endif
+#include <asm/arch/crm_regs.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#include <asm/mach-imx/video.h>
+#include <dm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_SPEED_MED   |                                   \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
+	PAD_CTL_SPEED_MED   | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE)
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+			PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
+	PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define WEIM_NOR_PAD_CTRL2 (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm)
+
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
+		.gp = IMX_GPIO_NR(1, 0),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
+		.gp = IMX_GPIO_NR(1, 1),
+	},
+};
+
+/* I2C2 */
+struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
+		.gp = IMX_GPIO_NR(1, 2),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
+		.gp = IMX_GPIO_NR(1, 3),
+	},
+};
+#endif
+
+#ifdef CONFIG_POWER_LEGACY
+#define I2C_PMIC 0
+int power_init_board(void)
+{
+	struct pmic *pfuze;
+	unsigned int reg;
+	int ret;
+
+	pfuze = pfuze_common_init(I2C_PMIC);
+	if (!pfuze)
+		return -ENODEV;
+
+	ret = pfuze_mode_init(pfuze, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	/* set SW1AB staby volatage 0.975V */
+	pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= PFUZE100_SW1ABC_SETP(9750);
+	pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);
+
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);
+
+	/* set SW1C staby volatage 0.975V */
+	pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= PFUZE100_SW1ABC_SETP(9750);
+	pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
+
+	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+	pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
+
+	return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+	unsigned int value;
+	int is_400M;
+	u32 vddarm;
+	struct pmic *p = pmic_get("PFUZE100");
+
+	if (!p) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* switch to ldo_bypass mode */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+		/* decrease VDDARM to 1.275V */
+		pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+		value &= ~0x3f;
+		value |= PFUZE100_SW1ABC_SETP(12750);
+		pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+
+		/* decrease VDDSOC to 1.3V */
+		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+		value &= ~0x3f;
+		value |= PFUZE100_SW1ABC_SETP(13000);
+		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+		is_400M = set_anatop_bypass(1);
+		if (is_400M)
+			vddarm = PFUZE100_SW1ABC_SETP(10750);
+		else
+			vddarm = PFUZE100_SW1ABC_SETP(11750);
+
+		pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+		value &= ~0x3f;
+		value |= vddarm;
+		pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+
+		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+		value &= ~0x3f;
+		value |= PFUZE100_SW1ABC_SETP(11750);
+		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+		finish_anatop_bypass();
+		printf("switch to ldo_bypass mode!\n");
+	}
+
+}
+#endif
+
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	dev = pfuze_common_init();
+	if (!dev)
+		return -ENODEV;
+
+	ret = pfuze_mode_init(dev, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+	struct udevice *dev;
+	int ret;
+	int is_400M;
+	u32 vddarm;
+
+	ret = pmic_get("pfuze100@8", &dev);
+	if (ret == -ENODEV) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* switch to ldo_bypass mode , boot on 800Mhz */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+
+		/* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750));
+
+		/* increase VDDSOC to 1.3V */
+		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(13000));
+
+		is_400M = set_anatop_bypass(1);
+		if (is_400M)
+			vddarm = PFUZE100_SW1ABC_SETP(10750);
+		else
+			vddarm = PFUZE100_SW1ABC_SETP(11750);
+
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
+
+		/* decrease VDDSOC to 1.175V */
+		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(11750));
+
+		finish_anatop_bypass();
+		printf("switch to ldo_bypass mode!\n");
+	}
+}
+#endif
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+#ifdef CONFIG_FEC_MXC
+static iomux_v3_cfg_t const fec1_pads[] = {
+	MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	/* AR8031 PHY Reset. For arm2 board, silder the resistance */
+	MX6_PAD_SD4_DATA4__GPIO6_IO_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_fec1(void)
+{
+	SETUP_IOMUX_PADS(fec1_pads);
+}
+#endif
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+}
+
+#ifdef CONFIG_FSL_QSPI
+#ifndef CONFIG_DM_SPI
+#define QSPI_PAD_CTRL1	\
+		(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
+		PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
+
+#define QSPI_PAD_CTRL2 (QSPI_PAD_CTRL1 | PAD_CTL_DSE_34ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+	MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2		| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3		| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA02__QSPI2_B_SCLK		| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+
+};
+#endif
+
+int board_qspi_init(void)
+{
+#ifndef CONFIG_DM_SPI
+	/* Set the iomux */
+	SETUP_IOMUX_PADS(quadspi_pads);
+#endif
+
+	/* Set the clock */
+	enable_qspi_clk(1);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC1_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	return 1;	/* Assume boot SD always present */
+}
+int board_mmc_init(struct bd_info *bis)
+{
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * mmc0                    USDHC1 (SDA)
+	 */
+	SETUP_IOMUX_PADS(usdhc1_pads);
+
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+iomux_v3_cfg_t eimnor_pads[] = {
+	MX6_PAD_QSPI1A_SCLK__WEIM_DATA_0   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
+	MX6_PAD_QSPI1A_SS0_B__WEIM_DATA_1  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
+	MX6_PAD_QSPI1A_SS1_B__WEIM_DATA_2  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
+	MX6_PAD_QSPI1A_DATA3__WEIM_DATA_3  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
+	MX6_PAD_QSPI1A_DATA2__WEIM_DATA_4  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
+	MX6_PAD_QSPI1A_DATA1__WEIM_DATA_5  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
+	MX6_PAD_QSPI1A_DATA0__WEIM_DATA_6  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
+	MX6_PAD_QSPI1A_DQS__WEIM_DATA_7    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
+	MX6_PAD_QSPI1B_SCLK__WEIM_DATA_8   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
+	MX6_PAD_QSPI1B_SS0_B__WEIM_DATA_9  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
+	MX6_PAD_QSPI1B_SS1_B__WEIM_DATA_10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
+	MX6_PAD_QSPI1B_DATA3__WEIM_DATA_11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
+	MX6_PAD_QSPI1B_DATA2__WEIM_DATA_12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
+	MX6_PAD_QSPI1B_DATA1__WEIM_DATA_13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
+	MX6_PAD_QSPI1B_DATA0__WEIM_DATA_14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
+	MX6_PAD_QSPI1B_DQS__WEIM_DATA_15   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2),
+
+	MX6_PAD_NAND_DATA00__WEIM_AD_0     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA01__WEIM_AD_1     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA02__WEIM_AD_2     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA03__WEIM_AD_3     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA04__WEIM_AD_4     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA05__WEIM_AD_5     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA06__WEIM_AD_6     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA07__WEIM_AD_7     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA08__WEIM_AD_8     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA09__WEIM_AD_9     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA10__WEIM_AD_10    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA11__WEIM_AD_11    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
+	MX6_PAD_LCD1_DATA12__WEIM_AD_12    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA13__WEIM_AD_13    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA14__WEIM_AD_14    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA15__WEIM_AD_15    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA16__WEIM_ADDR_16  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA17__WEIM_ADDR_17  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA18__WEIM_ADDR_18  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA19__WEIM_ADDR_19  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA20__WEIM_ADDR_20  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA21__WEIM_ADDR_21  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA22__WEIM_ADDR_22  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA23__WEIM_ADDR_23  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA03__WEIM_ADDR_24  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA04__WEIM_ADDR_25  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD1_DATA05__WEIM_ADDR_26  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+
+	MX6_PAD_NAND_CE1_B__WEIM_OE        | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_RE_B__WEIM_RW         | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_WE_B__WEIM_WAIT       | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	MX6_PAD_NAND_ALE__WEIM_CS0_B       | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+};
+static void eimnor_cs_setup(void)
+{
+	writel(0x00000120, WEIM_BASE_ADDR + 0x090);
+	writel(0x00010181, WEIM_BASE_ADDR + 0x000);
+	writel(0x00000001, WEIM_BASE_ADDR + 0x004);
+	writel(0x0a020000, WEIM_BASE_ADDR + 0x008);
+	writel(0x0000c000, WEIM_BASE_ADDR + 0x00c);
+	writel(0x0804a240, WEIM_BASE_ADDR + 0x010);
+}
+
+static void setup_eimnor(void)
+{
+	SETUP_IOMUX_PADS(eimnor_pads);
+
+	eimnor_cs_setup();
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+iomux_v3_cfg_t gpmi_pads[] = {
+	MX6_PAD_NAND_CLE__RAWNAND_CLE		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_ALE__RAWNAND_ALE		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WP_B__RAWNAND_WP_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_READY_B__RAWNAND_READY_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL0),
+	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_RE_B__RAWNAND_RE_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WE_B__RAWNAND_WE_B		| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA00__RAWNAND_DATA00	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA01__RAWNAND_DATA01	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA02__RAWNAND_DATA02	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA03__RAWNAND_DATA03	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA04__RAWNAND_DATA04	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA05__RAWNAND_DATA05	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA06__RAWNAND_DATA06	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA07__RAWNAND_DATA07	| MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+};
+
+static void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	SETUP_IOMUX_PADS(gpmi_pads);
+
+	setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
+			MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |
+			MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+
+#define MAX7322_I2C_ADDR		0x68
+#define MAX7322_I2C_BUS		1
+
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+	int ret;
+	unsigned char value = 1;
+
+	/* clear gpr1[13], gpr1[17] to select anatop clock */
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
+
+	ret = enable_fec_anatop_clock(0, ENET_125MHZ);
+	if (ret)
+		return ret;
+
+	/* Reset AR8031 PHY */
+	gpio_request(IMX_GPIO_NR(6, 18), "ar8031 reset");
+	gpio_direction_output(IMX_GPIO_NR(6, 18) , 0);
+	udelay(500);
+	gpio_set_value(IMX_GPIO_NR(6, 18), 1);
+
+#ifdef CONFIG_DM_I2C
+	struct udevice *bus, *dev;
+	ret = uclass_get_device_by_seq(UCLASS_I2C, MAX7322_I2C_BUS - 1, &bus);
+	if (ret) {
+		printf("Get i2c bus %u failed, ret = %d\n", MAX7322_I2C_BUS - 1, ret);
+		return ret;
+	}
+
+	ret = dm_i2c_probe(bus, MAX7322_I2C_ADDR, 0, &dev);
+	if (ret) {
+		printf("MAX7322 Not found, ret = %d\n", ret);
+		return ret;
+	}
+
+	/* Write 0x1 to enable O0 output, this device has no addr */
+	/* hence addr length is 0 */
+	value = 0x1;
+	ret = dm_i2c_write(dev, 0, &value, 1);
+	if (ret) {
+		printf("MAX7322 write failed, ret = %d\n", ret);
+		return ret;
+	}
+#else
+	/* This is needed to drive the pads to 1.8V instead of 1.5V */
+	i2c_set_bus_num(MAX7322_I2C_BUS);
+
+	if (!i2c_probe(MAX7322_I2C_ADDR)) {
+		/* Write 0x1 to enable O0 output, this device has no addr */
+		/* hence addr length is 0 */
+		value = 0x1;
+		if (i2c_write(MAX7322_I2C_ADDR, 0, 0, &value, 1))
+			printf("MAX7322 write failed\n");
+	} else {
+		printf("MAX7322 Not found\n");
+	}
+#endif
+
+	return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+	int ret;
+
+	setup_iomux_fec1();
+
+	ret = fecmxc_initialize_multi(bis, 0,
+		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+	if (ret)
+		printf("FEC1 MXC: %s:failed\n", __func__);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+#ifdef CONFIG_FEC_ENABLE_MAX7322
+	/* Enable 1.8V(SEL_1P5_1P8_POS_REG) on
+	   Phy control debug reg 0 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+#endif
+
+	/* rgmii tx clock delay enable */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+
+iomux_v3_cfg_t const usb_otg_pads[] = {
+	MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+	MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_usb(void)
+{
+	SETUP_IOMUX_PADS(usb_otg_pads);
+}
+
+int board_usb_phy_mode(int port)
+{
+	if (port == 1)
+		return USB_INIT_HOST;
+	else
+		return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port >= 1)
+		return -EINVAL;
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	/* Set Power polarity */
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
+}
+#endif
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+	setup_eimnor();
+#endif
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+	setup_usb();
+#endif
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+	{"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)},
+	{"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x0B)},
+	{"eimnor", MAKE_CFGVAL(0x00, 0x80, 0x00, 0x00)},
+	{NULL,   0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return get_cpu_rev();
+}
+
+int checkboard(void)
+{
+	puts("Board: MX6SX 19x19 ARM2\n");
+
+	return 0;
+}
diff --git a/board/freescale/mx6sx_19x19_val/plugin.S b/board/freescale/mx6sx_19x19_val/plugin.S
new file mode 100644
index 00000000000..0e6b8066247
--- /dev/null
+++ b/board/freescale/mx6sx_19x19_val/plugin.S
@@ -0,0 +1,289 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6sx_19x19_ddr3_val_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x618]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x5fc]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x32c]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x300]
+	str r1, [r0, #0x2fc]
+	str r1, [r0, #0x5f4]
+	str r1, [r0, #0x340]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x320]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x310]
+	str r1, [r0, #0x314]
+	str r1, [r0, #0x614]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x5f8]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x330]
+	str r1, [r0, #0x334]
+	str r1, [r0, #0x338]
+	str r1, [r0, #0x33c]
+	ldr r1, =0x00020000
+	str r1, [r0, #0x608]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x60c]
+	str r1, [r0, #0x610]
+	str r1, [r0, #0x61c]
+	str r1, [r0, #0x620]
+	str r1, [r0, #0x2ec]
+	str r1, [r0, #0x2f0]
+	str r1, [r0, #0x2f4]
+	str r1, [r0, #0x2f8]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+	ldr r2, =0x002C003D
+	str r2, [r0, #0x80c]
+	ldr r2, =0x00110046
+	str r2, [r0, #0x810]
+	ldr r2, =0x4160016C
+	str r2, [r0, #0x83c]
+	ldr r2, =0x013C016C
+	str r2, [r0, #0x840]
+	ldr r2, =0x46424446
+	str r2, [r0, #0x848]
+	ldr r2, =0x3A3C3C3A
+	str r2, [r0, #0x850]
+	ldr r2, =0x2492244A
+	str r2, [r0, #0x8c0]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	ldr r2, =0x0002002d
+	str r2, [r0, #0x004]
+	ldr r2, =0x00333030
+	str r2, [r0, #0x008]
+	ldr r2, =0x676b52f3
+	str r2, [r0, #0x00c]
+	ldr r2, =0xb66d8b63
+	str r2, [r0, #0x010]
+	ldr r2, =0x01ff00db
+	str r2, [r0, #0x014]
+	ldr r2, =0x00011740
+	str r2, [r0, #0x018]
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x006b1023
+	str r2, [r0, #0x030]
+	ldr r2, =0x0000007f
+	str r2, [r0, #0x040]
+	ldr r2, =0x85190000
+	str r2, [r0, #0x000]
+	ldr r2, =0x04008032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00068031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x05208030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00000800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00022227
+	str r2, [r0, #0x818]
+	ldr r2, =0x0002556d
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+
+.endm
+
+.macro imx6sx_19x19_lpddr2_val_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x00080000
+	str r1, [r0, #0x618]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x5fc]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x32c]
+
+	ldr r1, =0x00000028
+	str r1, [r0, #0x300]
+	str r1, [r0, #0x2fc]
+	str r1, [r0, #0x5f4]
+	str r1, [r0, #0x340]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x320]
+	str r1, [r0, #0x310]
+	str r1, [r0, #0x314]
+	ldr r1, =0x00000028
+	str r1, [r0, #0x614]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x5f8]
+	ldr r1, =0x00003028
+	str r1, [r0, #0x330]
+	str r1, [r0, #0x334]
+	str r1, [r0, #0x338]
+	str r1, [r0, #0x33c]
+	ldr r1, =0x00020000
+	str r1, [r0, #0x608]
+	ldr r1, =0x00000028
+	str r1, [r0, #0x60c]
+	str r1, [r0, #0x610]
+	str r1, [r0, #0x61c]
+	str r1, [r0, #0x620]
+	str r1, [r0, #0x2ec]
+	str r1, [r0, #0x2f0]
+	str r1, [r0, #0x2f4]
+	str r1, [r0, #0x2f8]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0x00008000
+	str r2, [r0, #0x1c]
+	ldr r2, =0x1b4700c7
+	str r2, [r0, #0x85c]
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+	ldr r2, =0x00380000
+	str r2, [r0, #0x890]
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+
+	ldr r2, =0x51111111
+	str r2, [r0, #0x82c]
+	str r2, [r0, #0x830]
+	str r2, [r0, #0x834]
+	str r2, [r0, #0x838]
+
+	ldr r2, =0x42424244
+	str r2, [r0, #0x848]
+	ldr r2, =0x2E30322E
+	str r2, [r0, #0x850]
+	ldr r2, =0x2492244A
+	str r2, [r0, #0x8c0]
+	ldr r2, =0x20000000
+	str r2, [r0, #0x83c]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x840]
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+
+	ldr r2, =0x33374133
+	str r2, [r0, #0x00c]
+	ldr r2, =0x00020024
+	str r2, [r0, #0x004]
+	ldr r2, =0x00100A42
+	str r2, [r0, #0x010]
+	ldr r2, =0x00000093
+	str r2, [r0, #0x014]
+	ldr r2, =0x00001748
+	str r2, [r0, #0x018]
+	ldr r2, =0x0f9f26d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x0000020e
+	str r2, [r0, #0x030]
+	ldr r2, =0x00190778
+	str r2, [r0, #0x038]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x008]
+	ldr r2, =0x0000004f
+	str r2, [r0, #0x040]
+	ldr r2, =0xc3110000
+	str r2, [r0, #0x000]
+
+	ldr r2, =0x00008010
+	str r2, [r0, #0x01c]
+	ldr r2, =0x003f8030
+	str r2, [r0, #0x01c]
+	ldr r2, =0xff0a8030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x82018030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04028030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x01038030
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00008018
+	str r2, [r0, #0x01c]
+	ldr r2, =0x003f8038
+	str r2, [r0, #0x01c]
+	ldr r2, =0xff0a8038
+	str r2, [r0, #0x01c]
+	ldr r2, =0x82018038
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04028038
+	str r2, [r0, #0x01c]
+	ldr r2, =0x01038038
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00001800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x818]
+	ldr r2, =0xa1310003
+	str r2, [r0, #0x800]
+	ldr r2, =0x00025576
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+
+.endm
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x068]
+	str r1, [r0, #0x06c]
+	str r1, [r0, #0x070]
+	str r1, [r0, #0x074]
+	str r1, [r0, #0x078]
+	str r1, [r0, #0x07c]
+	str r1, [r0, #0x080]
+	str r1, [r0, #0x084]
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+#if defined (CONFIG_LPDDR2_BOARD)
+	imx6sx_19x19_lpddr2_val_ddr_setting
+#else
+	imx6sx_19x19_ddr3_val_ddr_setting
+#endif
+
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/board/freescale/mx6sxsabreauto/Kconfig b/board/freescale/mx6sxsabreauto/Kconfig
index e6da7b38f91..e2c054640da 100644
--- a/board/freescale/mx6sxsabreauto/Kconfig
+++ b/board/freescale/mx6sxsabreauto/Kconfig
@@ -12,4 +12,6 @@ config SYS_CONFIG_NAME
 config IMX_CONFIG
 	default "board/freescale/mx6sxsabreauto/imximage.cfg"
 
+config SYS_TEXT_BASE
+	default 0x87800000
 endif
diff --git a/board/freescale/mx6sxsabreauto/imximage.cfg b/board/freescale/mx6sxsabreauto/imximage.cfg
index da703093aa6..0c55eedb9f2 100644
--- a/board/freescale/mx6sxsabreauto/imximage.cfg
+++ b/board/freescale/mx6sxsabreauto/imximage.cfg
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  */
 
 #include <config.h>
@@ -14,7 +14,22 @@ IMAGE_VERSION 2
  * spi/sd/nand/onenand, qspi/nor
  */
 
+#ifdef CONFIG_QSPI_BOOT
+BOOT_FROM	qspi
+#elif defined(CONFIG_NOR_BOOT)
+BOOT_FROM	nor
+#else
 BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN  board/freescale/mx6sxsabreauto/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
 
 /*
  * Device Configuration Data (DCD)
@@ -38,6 +53,11 @@ DATA 4 0x020c407c 0xffffffff
 DATA 4 0x020c4080 0xffffffff
 DATA 4 0x020c4084 0xffffffff
 
+#ifdef CONFIG_IMX_OPTEE
+DATA 4 0x20e4024 0x00000001
+CHECK_BITS_SET 4 0x20e4024 0x1
+#endif
+
 /* IOMUX - DDR IO Type */
 DATA 4 0x020e0618 0x000c0000
 DATA 4 0x020e05fc 0x00000000
@@ -132,3 +152,4 @@ DATA 4 0x021b0818 0x00022227
 DATA 4 0x021b0004 0x0002556d
 DATA 4 0x021b0404 0x00011006
 DATA 4 0x021b001c 0x00000000
+#endif
diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
index 7340a344023..9c355e4e231 100644
--- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
+++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 nxp
  *
  * Author: Ye Li <ye.li@nxp.com>
  */
@@ -30,6 +31,7 @@
 #include <usb.h>
 #include <usb/ehci-ci.h>
 #include <pca953x.h>
+#include <asm/mach-imx/video.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -52,6 +54,13 @@ DECLARE_GLOBAL_DATA_PTR;
 			PAD_CTL_SRE_FAST)
 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
 
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
@@ -64,23 +73,6 @@ static iomux_v3_cfg_t const uart1_pads[] = {
 	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-static iomux_v3_cfg_t const fec2_pads[] = {
-	MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
 static void setup_iomux_uart(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
@@ -88,27 +80,28 @@ static void setup_iomux_uart(void)
 
 static int setup_fec(void)
 {
+	int ret;
 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 
-	/* Use 125MHz anatop loopback REF_CLK1 for ENET2 */
-	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
-
-	return enable_fec_anatop_clock(1, ENET_125MHZ);
-}
+	/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
 
-int board_eth_init(struct bd_info *bis)
-{
-	int ret;
+	/* Use 125M anatop REF_CLK1 for ENET2, clear gpr1[14], gpr1[18]*/
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
 
-	imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
-	setup_fec();
+	ret = enable_fec_anatop_clock(0, ENET_125MHZ);
+	if (ret) {
+		printf("enable fec0 clock failed\n");
+		return ret;
+	}
 
-	ret = fecmxc_initialize_multi(bis, 1,
-		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
-	if (ret)
-		printf("FEC%d MXC: %s:failed\n", 1, __func__);
+	ret = enable_fec_anatop_clock(1, ENET_125MHZ);
+	if (ret) {
+		printf("enable fec0 clock failed\n");
+		return ret;
+	}
 
-	return ret;
+	return 0;
 }
 
 int board_phy_config(struct phy_device *phydev)
@@ -134,51 +127,64 @@ int power_init_board(void)
 {
 	struct udevice *dev;
 	int ret;
-	u32 dev_id, rev_id, i;
-	u32 switch_num = 6;
-	u32 offset = PFUZE100_SW1CMODE;
 
-	ret = pmic_get("pfuze100", &dev);
-	if (ret == -ENODEV)
-		return 0;
+	dev = pfuze_common_init();
+	if (!dev)
+		return -ENODEV;
 
-	if (ret != 0)
+	ret = pfuze_mode_init(dev, APS_PFM);
+	if (ret < 0)
 		return ret;
 
-	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
-	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
-	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+	/* set SW1C staby volatage 1.10V */
+	pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20);
+
+	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+	pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
 
+	/* Enable power of VGEN5 3V3, needed for SD3 */
+	pmic_clrsetbits(dev, PFUZE100_SW1CCONF, LDO_VOL_MASK, (LDOB_3_30V | (1 << LDO_EN)));
 
-	/* Init mode to APS_PFM */
-	pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
+	return 0;
+}
 
-	for (i = 0; i < switch_num - 1; i++)
-		pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+	struct udevice *dev;
+	int ret;
 
-	/* set SW1AB staby volatage 0.975V */
-	pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
+	ret = pmic_get("pfuze100@8", &dev);
+	if (ret == -ENODEV) {
+		printf("No PMIC found!\n");
+		return;
+	}
 
-	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
-	pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
+	/* switch to ldo_bypass mode */
+	if (ldo_bypass) {
+		/* decrease VDDARM to 1.15V */
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, SW1x_1_150V);
 
-	/* set SW1C staby volatage 1.10V */
-	pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20);
+		/* decrease VDDSOC to 1.15V */
+		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, SW1x_1_150V);
 
-	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
-	pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
+		set_anatop_bypass(1);
 
-	return 0;
+		printf("switch to ldo_bypass mode!\n");
+	}
 }
+#endif
 
 #ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
 #define USB_OTHERREGS_OFFSET	0x800
 #define UCTRL_PWR_POL		(1 << 9)
 
 static iomux_v3_cfg_t const usb_otg_pads[] = {
 	/* OGT1 */
 	MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
-	MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
 	/* OTG2 */
 	MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
 };
@@ -213,6 +219,7 @@ int board_ehci_hcd_init(int port)
 	return 0;
 }
 #endif
+#endif
 
 int board_early_init_f(void)
 {
@@ -221,6 +228,95 @@ int board_early_init_f(void)
 	return 0;
 }
 
+#ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lvds_ctrl_pads[] = {
+	/* Use GPIO for Brightness adjustment, duty cycle = period */
+	MX6_PAD_SD1_DATA1__GPIO6_IO_3 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const lcd_pads[] = {
+	MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void setup_lvds(void)
+{
+	struct gpio_desc desc;
+	int ret;
+
+	enable_lcdif_clock(LCDIF2_BASE_ADDR, 1);
+	enable_lvds_clock(LCDIF2_BASE_ADDR);
+
+	imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads,
+							ARRAY_SIZE(lvds_ctrl_pads));
+
+	/* LVDS Enable pin */
+	ret = dm_gpio_lookup_name("gpio@30_7", &desc);
+	if (ret)
+		return;
+
+	ret = dm_gpio_request(&desc, "lvds_en");
+	if (ret)
+		return;
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+	dm_gpio_set_value(&desc, 1);
+
+	/* Set Brightness to high */
+	ret = dm_gpio_lookup_name("GPIO6_3", &desc);
+	if (ret)
+		return;
+
+	ret = dm_gpio_request(&desc, "lcd backlight");
+	if (ret)
+		return;
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+}
+
+void setup_lcd(void)
+{
+	struct gpio_desc desc;
+	int ret;
+
+	enable_lcdif_clock(MX6SX_LCDIF1_BASE_ADDR, 1);
+
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+
+	/* Power up the LCD */
+	ret = dm_gpio_lookup_name("GPIO3_27", &desc);
+	if (ret)
+		return;
+
+	ret = dm_gpio_request(&desc, "lcd reset");
+	if (ret)
+		return;
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+}
+#endif
+
 #ifdef CONFIG_FSL_QSPI
 int board_qspi_init(void)
 {
@@ -300,8 +396,10 @@ int board_init(void)
 	dm_gpio_set_value(&desc, 0);
 
 #ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
 	setup_usb();
 #endif
+#endif
 
 #ifdef CONFIG_FSL_QSPI
 	board_qspi_init();
@@ -311,6 +409,15 @@ int board_init(void)
 	setup_gpmi_nand();
 #endif
 
+	/* Also used for OF_CONTROL enabled */
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+#ifdef CONFIG_VIDEO_MXS
+	setup_lvds();
+	setup_lcd();
+#endif
 	return 0;
 }
 
@@ -330,6 +437,18 @@ int board_late_init(void)
 	add_board_boot_modes(board_boot_modes);
 #endif
 
+	env_set("tee", "no");
+#ifdef CONFIG_IMX_OPTEE
+	env_set("tee", "yes");
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	/* set WDOG_B to reset whole system */
+	set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
+
 	return 0;
 }
 
diff --git a/board/freescale/mx6sxsabreauto/plugin.S b/board/freescale/mx6sxsabreauto/plugin.S
new file mode 100644
index 00000000000..ea5640ca15d
--- /dev/null
+++ b/board/freescale/mx6sxsabreauto/plugin.S
@@ -0,0 +1,148 @@
+/*
+ * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6sx_sabreauto_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x618]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x5fc]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x32c]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x300]
+	str r1, [r0, #0x2fc]
+	str r1, [r0, #0x5f4]
+	str r1, [r0, #0x340]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x320]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x310]
+	str r1, [r0, #0x314]
+	str r1, [r0, #0x614]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x5f8]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x330]
+	str r1, [r0, #0x334]
+	str r1, [r0, #0x338]
+	str r1, [r0, #0x33c]
+	ldr r1, =0x00020000
+	str r1, [r0, #0x608]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x60c]
+	str r1, [r0, #0x610]
+	str r1, [r0, #0x61c]
+	str r1, [r0, #0x620]
+	str r1, [r0, #0x2ec]
+	str r1, [r0, #0x2f0]
+	str r1, [r0, #0x2f4]
+	str r1, [r0, #0x2f8]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+	ldr r2, =0x002C003D
+	str r2, [r0, #0x80c]
+	ldr r2, =0x00110046
+	str r2, [r0, #0x810]
+	ldr r2, =0x4160016C
+	str r2, [r0, #0x83c]
+	ldr r2, =0x013C016C
+	str r2, [r0, #0x840]
+	ldr r2, =0x46424446
+	str r2, [r0, #0x848]
+	ldr r2, =0x3A3C3C3A
+	str r2, [r0, #0x850]
+	ldr r2, =0x2492244A
+	str r2, [r0, #0x8c0]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	ldr r2, =0x0002002d
+	str r2, [r0, #0x004]
+	ldr r2, =0x00333030
+	str r2, [r0, #0x008]
+	ldr r2, =0x676b52f3
+	str r2, [r0, #0x00c]
+	ldr r2, =0xb66d8b63
+	str r2, [r0, #0x010]
+	ldr r2, =0x01ff00db
+	str r2, [r0, #0x014]
+	ldr r2, =0x00011740
+	str r2, [r0, #0x018]
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x006b1023
+	str r2, [r0, #0x030]
+	ldr r2, =0x0000007f
+	str r2, [r0, #0x040]
+	ldr r2, =0x85190000
+	str r2, [r0, #0x000]
+	ldr r2, =0x04008032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00068031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x05208030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00000800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00022227
+	str r2, [r0, #0x818]
+	ldr r2, =0x0002556d
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+
+.endm
+
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x068]
+	str r1, [r0, #0x06c]
+	str r1, [r0, #0x070]
+	str r1, [r0, #0x074]
+	str r1, [r0, #0x078]
+	str r1, [r0, #0x07c]
+	str r1, [r0, #0x080]
+	str r1, [r0, #0x084]
+#ifdef CONFIG_IMX_OPTEE
+	ldr r0, =0x20e4024
+	ldr r1, =0x1
+	str r1, [r0]
+#endif
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+	imx6sx_sabreauto_ddr_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/board/freescale/mx6sxsabresd/Kconfig b/board/freescale/mx6sxsabresd/Kconfig
index 88ac7ee8050..e59c1bbab13 100644
--- a/board/freescale/mx6sxsabresd/Kconfig
+++ b/board/freescale/mx6sxsabresd/Kconfig
@@ -12,4 +12,9 @@ config SYS_CONFIG_NAME
 config IMX_CONFIG
 	default "board/freescale/mx6sxsabresd/imximage.cfg"
 
+config MX6SXSABRESD_EMMC_REWORK
+	bool "Select for the board with eMMC rework"
+
+config SYS_TEXT_BASE
+	default 0x87800000
 endif
diff --git a/board/freescale/mx6sxsabresd/imximage.cfg b/board/freescale/mx6sxsabresd/imximage.cfg
index 313ab589505..7aaf6dd362a 100644
--- a/board/freescale/mx6sxsabresd/imximage.cfg
+++ b/board/freescale/mx6sxsabresd/imximage.cfg
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  */
 
 #include <config.h>
@@ -14,7 +14,16 @@ IMAGE_VERSION 2
  * spi/sd/nand/onenand, qspi/nor
  */
 
+#ifdef CONFIG_QSPI_BOOT
+BOOT_FROM	qspi
+#else
 BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN  board/freescale/mx6sxsabresd/plugin.bin 0x00907000
+#else
 
 /*
  * Secure boot support
@@ -45,6 +54,11 @@ DATA 4 0x020c407c 0xffffffff
 DATA 4 0x020c4080 0xffffffff
 DATA 4 0x020c4084 0xffffffff
 
+#ifdef CONFIG_IMX_OPTEE
+DATA 4 0x20e4024 0x00000001
+CHECK_BITS_SET 4 0x20e4024 0x1
+#endif
+
 /* IOMUX - DDR IO Type */
 DATA 4 0x020e0618 0x000c0000
 DATA 4 0x020e05fc 0x00000000
@@ -135,3 +149,4 @@ DATA 4 0x021b001c 0x04008040
 DATA 4 0x021b0020 0x00000800
 DATA 4 0x021b0818 0x00011117
 DATA 4 0x021b001c 0x00000000
+#endif
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index e7958df4024..7e1c538677c 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  *
  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  */
@@ -16,6 +17,7 @@
 #include <asm/global_data.h>
 #include <asm/gpio.h>
 #include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
 #include <asm/io.h>
 #include <asm/mach-imx/mxc_i2c.h>
 #include <env.h>
@@ -30,7 +32,15 @@
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 #include "../common/pfuze.h"
-
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#include <asm/mach-imx/video.h>
+#include <power/regulator.h>
+
+#ifdef CONFIG_IMX_RDC
+#include <asm/mach-imx/rdc-sema.h>
+#include <asm/arch/imx-rdc.h>
+#endif
 DECLARE_GLOBAL_DATA_PTR;
 
 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
@@ -41,6 +51,11 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
+#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE)
+
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
 	PAD_CTL_SPEED_HIGH   |                                   \
 	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
@@ -51,12 +66,21 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
 	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
 
+#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE)
+
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
 	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
 
 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED |	\
 	PAD_CTL_DSE_40ohm)
 
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
@@ -69,39 +93,66 @@ static iomux_v3_cfg_t const uart1_pads[] = {
 	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
-static iomux_v3_cfg_t const wdog_b_pad = {
-	MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
-};
-static iomux_v3_cfg_t const fec1_pads[] = {
-	MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
-	MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 
-static iomux_v3_cfg_t const peri_3v3_pads[] = {
-	MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/* CD pin */
+	MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* RST_B, used for power reset cycle */
+	MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
-static iomux_v3_cfg_t const phy_control_pads[] = {
-	/* 25MHz Ethernet PHY Clock */
-	MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
+static iomux_v3_cfg_t const usdhc4_emmc_pads[] = {
+	MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_RESET_B__USDHC4_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#else
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+	MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#endif
 
-	/* ENET PHY Power */
-	MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
+static iomux_v3_cfg_t const wdog_b_pad = {
+	MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
 
-	/* AR8031 PHY Reset */
-	MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
+static iomux_v3_cfg_t const peri_3v3_pads[] = {
+	MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
 static void setup_iomux_uart(void)
@@ -115,25 +166,19 @@ static int setup_fec(void)
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 	int reg, ret;
 
-	/* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
+	/* Use 125M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
 	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
 
+	/* Use 125M anatop loopback REF_CLK1 for ENET2, clear gpr1[14], gpr1[18]*/
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
+
 	ret = enable_fec_anatop_clock(0, ENET_125MHZ);
 	if (ret)
 		return ret;
 
-	imx_iomux_v3_setup_multiple_pads(phy_control_pads,
-					 ARRAY_SIZE(phy_control_pads));
-
-	/* Enable the ENET power, active low */
-	gpio_request(IMX_GPIO_NR(2, 6), "enet_rst");
-	gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
-
-	/* Reset AR8031 PHY */
-	gpio_request(IMX_GPIO_NR(2, 7), "phy_rst");
-	gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
-	mdelay(10);
-	gpio_set_value(IMX_GPIO_NR(2, 7), 1);
+	ret = enable_fec_anatop_clock(1, ENET_125MHZ);
+	if (ret)
+		return ret;
 
 	reg = readl(&anatop->pll_enet);
 	reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
@@ -142,14 +187,85 @@ static int setup_fec(void)
 	return 0;
 }
 
-int board_eth_init(struct bd_info *bis)
+#ifdef CONFIG_SYS_I2C_LEGACY
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
+		.gp = IMX_GPIO_NR(1, 0),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
+		.gp = IMX_GPIO_NR(1, 1),
+	},
+};
+
+/* I2C2 */
+struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
+		.gp = IMX_GPIO_NR(1, 2),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
+		.gp = IMX_GPIO_NR(1, 3),
+	},
+};
+#endif
+
+#ifdef CONFIG_POWER_LEGACY
+int power_init_board(void)
 {
-	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
-	setup_fec();
+	struct pmic *pfuze;
+	unsigned int reg;
+	int ret;
 
-	return cpu_eth_init(bis);
-}
+	pfuze = pfuze_common_init(I2C_PMIC);
+	if (!pfuze)
+		return -ENODEV;
 
+	ret = pfuze_mode_init(pfuze, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	/* set SW1AB standby volatage 1.10V */
+	pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= PFUZE100_SW1ABC_SETP(11000);
+	pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);
+
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);
+
+	/* set SW1C standby volatage 1.10V */
+	pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);
+	reg &= ~0x3f;
+	reg |= PFUZE100_SW1ABC_SETP(11000);
+	pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
+
+	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+	pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
+
+	/* Enable power of VGEN5 3V3, needed for SD3 */
+	pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &reg);
+	reg &= ~LDO_VOL_MASK;
+	reg |= (LDOB_3_30V | (1 << LDO_EN));
+	pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg);
+
+	return 0;
+}
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
 int power_init_board(void)
 {
 	struct udevice *dev;
@@ -164,14 +280,176 @@ int power_init_board(void)
 	if (ret < 0)
 		return ret;
 
+	/* set SW1AB staby volatage 0.975V*/
+	reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
+	reg &= ~0x3f;
+	reg |= PFUZE100_SW1ABC_SETP(11000);
+	pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
+
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
+
+	/* set SW1C staby volatage 0.975V*/
+	reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
+	reg &= ~0x3f;
+	reg |= PFUZE100_SW1ABC_SETP(11000);
+	pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
+
+	/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+	reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
+	reg &= ~0xc0;
+	reg |= 0x40;
+	pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
+
 	/* Enable power of VGEN5 3V3, needed for SD3 */
 	reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
 	reg &= ~LDO_VOL_MASK;
 	reg |= (LDOB_3_30V | (1 << LDO_EN));
 	pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+#ifdef CONFIG_POWER_LEGACY
+void ldo_mode_set(int ldo_bypass)
+{
+	unsigned int value;
+	int is_400M;
+	u32 vddarm;
+	struct pmic *p = pmic_get("PFUZE100");
+
+	if (!p) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* switch to ldo_bypass mode */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+		/* decrease VDDARM to 1.275V */
+		pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+		value &= ~0x3f;
+		value |= PFUZE100_SW1ABC_SETP(12750);
+		pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+
+		/* decrease VDDSOC to 1.3V */
+		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+		value &= ~0x3f;
+		value |= PFUZE100_SW1ABC_SETP(13000);
+		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+		is_400M = set_anatop_bypass(1);
+		if (is_400M)
+			vddarm = PFUZE100_SW1ABC_SETP(10750);
+		else
+			vddarm = PFUZE100_SW1ABC_SETP(11750);
+
+		pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+		value &= ~0x3f;
+		value |= vddarm;
+		pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+
+		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+		value &= ~0x3f;
+		value |= PFUZE100_SW1ABC_SETP(11750);
+		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+		finish_anatop_bypass();
+		printf("switch to ldo_bypass mode!\n");
+	}
+
+}
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+void ldo_mode_set(int ldo_bypass)
+{
+	struct udevice *dev;
+	int ret;
+	int is_400M;
+	u32 vddarm;
+
+	ret = pmic_get("pfuze100@8", &dev);
+	if (ret == -ENODEV) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* switch to ldo_bypass mode , boot on 800Mhz */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+
+		/* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750));
+
+		/* increase VDDSOC to 1.3V */
+		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(13000));
+
+		is_400M = set_anatop_bypass(1);
+		if (is_400M)
+			vddarm = PFUZE100_SW1ABC_SETP(10750);
+		else
+			vddarm = PFUZE100_SW1ABC_SETP(11750);
+
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
+
+		/* decrease VDDSOC to 1.175V */
+		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(11750));
+
+		finish_anatop_bypass();
+		printf("switch to ldo_bypass mode!\n");
+	}
+}
+#endif
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+	/* OGT1 */
+	MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+	/* OTG2 */
+	MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+					 ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+	if (port == 1)
+		return USB_INIT_HOST;
+	else
+		return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	/* Set Power polarity */
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
 
 	return 0;
 }
+#endif
+#endif
 
 int board_phy_config(struct phy_device *phydev)
 {
@@ -192,8 +470,22 @@ int board_phy_config(struct phy_device *phydev)
 	return 0;
 }
 
+#ifdef CONFIG_IMX_RDC
+static rdc_peri_cfg_t const shared_resources[] = {
+	(RDC_PER_GPIO1 | RDC_DOMAIN(0) | RDC_DOMAIN(1)),
+};
+#endif
+
 int board_early_init_f(void)
 {
+#ifdef CONFIG_IMX_RDC
+	imx_rdc_setup_peripherals(shared_resources, ARRAY_SIZE(shared_resources));
+#endif
+
+#ifdef CONFIG_SYS_AUXCORE_FASTUP
+	arch_auxiliary_core_up(0, CONFIG_SYS_AUXCORE_BOOTDATA);
+#endif
+
 	setup_iomux_uart();
 
 	/* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
@@ -203,9 +495,105 @@ int board_early_init_f(void)
 	return 0;
 }
 
-int board_mmc_get_env_dev(int devno)
+#ifdef CONFIG_IMX_BOOTAUX
+ulong board_get_usable_ram_top(ulong total_size)
 {
-	return devno;
+	/* Reserve top 1M memory used by M core vring/buffer */
+	return gd->ram_top - SZ_1M;
+}
+#endif
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+	{USDHC2_BASE_ADDR, 0, 4},
+	{USDHC3_BASE_ADDR},
+#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
+	{USDHC4_BASE_ADDR, 0, 8},
+#else
+	{USDHC4_BASE_ADDR},
+#endif
+};
+
+#define USDHC3_CD_GPIO	IMX_GPIO_NR(2, 10)
+#define USDHC3_PWR_GPIO	IMX_GPIO_NR(2, 11)
+#define USDHC4_CD_GPIO	IMX_GPIO_NR(6, 21)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC2_BASE_ADDR:
+		ret = 1; /* Assume uSDHC2 is always present */
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC3_CD_GPIO);
+		break;
+	case USDHC4_BASE_ADDR:
+#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
+		ret = 1;
+#else
+		ret = !gpio_get_value(USDHC4_CD_GPIO);
+#endif
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC2
+	 * mmc1                    USDHC3
+	 * mmc2                    USDHC4
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			break;
+		case 1:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+			gpio_request(USDHC3_CD_GPIO, "usdhc3 cd");
+			gpio_request(USDHC3_PWR_GPIO, "usdhc3 pwr");
+			gpio_direction_input(USDHC3_CD_GPIO);
+			gpio_direction_output(USDHC3_PWR_GPIO, 1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			break;
+		case 2:
+#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc4_emmc_pads, ARRAY_SIZE(usdhc4_emmc_pads));
+#else
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+			gpio_request(USDHC4_CD_GPIO, "usdhc4 cd");
+			gpio_direction_input(USDHC4_CD_GPIO);
+#endif
+			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+			}
+
+			ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+			if (ret) {
+				printf("Warning: failed to initialize mmc dev %d\n", i);
+				return ret;
+			}
+	}
+
+	return 0;
 }
 
 #ifdef CONFIG_FSL_QSPI
@@ -219,7 +607,25 @@ int board_qspi_init(void)
 }
 #endif
 
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd3", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)},
+	{"sd4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+	{"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
 #ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lvds_ctrl_pads[] = {
+	/* CABC enable */
+	MX6_PAD_QSPI1A_DATA2__GPIO4_IO_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/* Use GPIO for Brightness adjustment, duty cycle = period */
+	MX6_PAD_SD1_DATA1__GPIO6_IO_3 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
 static iomux_v3_cfg_t const lcd_pads[] = {
 	MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
 	MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
@@ -255,9 +661,42 @@ static iomux_v3_cfg_t const lcd_pads[] = {
 	MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
-static int setup_lcd(void)
+void setup_lvds(void)
 {
-	enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
+	int ret;
+
+	ret = enable_lcdif_clock(LCDIF2_BASE_ADDR, 1);
+	if (ret) {
+		printf("Enable LCDIF clock failed, %d\n", ret);
+		return;
+	}
+	ret = enable_lvds_clock(LCDIF2_BASE_ADDR);
+	if (ret) {
+		printf("Enable LVDS bridge failed, %d\n", ret);
+		return;
+	}
+
+	imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads,
+							ARRAY_SIZE(lvds_ctrl_pads));
+
+	/* Enable CABC */
+	gpio_request(IMX_GPIO_NR(4, 18), "CABC enable");
+	gpio_direction_output(IMX_GPIO_NR(4, 18) , 1);
+
+	/* Set Brightness to high */
+	gpio_request(IMX_GPIO_NR(6, 3), "lvds backlight");
+	gpio_direction_output(IMX_GPIO_NR(6, 3) , 1);
+}
+
+void setup_lcd(void)
+{
+	int ret;
+
+	ret = enable_lcdif_clock(MX6SX_LCDIF1_BASE_ADDR, 1);
+	if (ret) {
+		printf("Enable LCDIF clock failed, %d\n", ret);
+		return;
+	}
 
 	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 
@@ -270,8 +709,6 @@ static int setup_lcd(void)
 	/* Set Brightness to high */
 	gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright");
 	gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
-
-	return 0;
 }
 #endif
 
@@ -289,15 +726,32 @@ int board_init(void)
 	 */
 	imx_iomux_v3_setup_pad(wdog_b_pad);
 
-	/* Active high for ncp692 */
-	gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en");
-	gpio_direction_output(IMX_GPIO_NR(4, 16), 1);
+#if defined(CONFIG_DM_REGULATOR)
+	regulators_enable_boot_on(false);
+#endif
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+	setup_usb();
+#endif
+#endif
 
 #ifdef CONFIG_FSL_QSPI
 	board_qspi_init();
 #endif
 
+	/* Also used for OF_CONTROL enabled */
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
 #ifdef CONFIG_VIDEO_MXS
+	setup_lvds();
 	setup_lcd();
 #endif
 
@@ -315,6 +769,19 @@ int board_late_init(void)
 	if (is_reva())
 		env_set("board_rev", "REVA");
 #endif
+
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+	env_set("tee", "no");
+#ifdef CONFIG_IMX_OPTEE
+	env_set("tee", "yes");
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
 	return 0;
 }
 
diff --git a/board/freescale/mx6sxsabresd/plugin.S b/board/freescale/mx6sxsabresd/plugin.S
new file mode 100644
index 00000000000..afdb781c749
--- /dev/null
+++ b/board/freescale/mx6sxsabresd/plugin.S
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6sx_sabresd_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x618]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x5fc]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x32c]
+
+	ldr r1, =0x00000020
+	str r1, [r0, #0x300]
+	str r1, [r0, #0x2fc]
+	str r1, [r0, #0x5f4]
+	str r1, [r0, #0x340]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x320]
+	ldr r1, =0x00000020
+	str r1, [r0, #0x310]
+	str r1, [r0, #0x314]
+	str r1, [r0, #0x614]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x5f8]
+	ldr r1, =0x00000028
+	str r1, [r0, #0x330]
+	str r1, [r0, #0x334]
+	str r1, [r0, #0x338]
+	str r1, [r0, #0x33c]
+	ldr r1, =0x00020000
+	str r1, [r0, #0x608]
+	ldr r1, =0x00000028
+	str r1, [r0, #0x60c]
+	str r1, [r0, #0x610]
+	str r1, [r0, #0x61c]
+	str r1, [r0, #0x620]
+	str r1, [r0, #0x2ec]
+	str r1, [r0, #0x2f0]
+	str r1, [r0, #0x2f4]
+	str r1, [r0, #0x2f8]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+	ldr r2, =0x00290025
+	str r2, [r0, #0x80c]
+	ldr r2, =0x00220022
+	str r2, [r0, #0x810]
+	ldr r2, =0x41480144
+	str r2, [r0, #0x83c]
+	ldr r2, =0x01340130
+	str r2, [r0, #0x840]
+	ldr r2, =0x3C3E4244
+	str r2, [r0, #0x848]
+	ldr r2, =0x34363638
+	str r2, [r0, #0x850]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	ldr r2, =0x0002002d
+	str r2, [r0, #0x004]
+	ldr r2, =0x00333030
+	str r2, [r0, #0x008]
+	ldr r2, =0x676b52f3
+	str r2, [r0, #0x00c]
+	ldr r2, =0xb66d8b63
+	str r2, [r0, #0x010]
+	ldr r2, =0x01ff00db
+	str r2, [r0, #0x014]
+	ldr r2, =0x00011740
+	str r2, [r0, #0x018]
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x006b1023
+	str r2, [r0, #0x030]
+	ldr r2, =0x0000005f
+	str r2, [r0, #0x040]
+	ldr r2, =0x84190000
+	str r2, [r0, #0x000]
+	ldr r2, =0x04008032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00048031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x05208030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00000800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00011117
+	str r2, [r0, #0x818]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+.endm
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xffffffff
+	str r1, [r0, #0x068]
+	str r1, [r0, #0x06c]
+	str r1, [r0, #0x070]
+	str r1, [r0, #0x074]
+	str r1, [r0, #0x078]
+	str r1, [r0, #0x07c]
+	str r1, [r0, #0x080]
+	str r1, [r0, #0x084]
+
+#ifdef CONFIG_IMX_OPTEE
+	ldr r0, =0x20e4024
+	ldr r1, =0x1
+	str r1, [r0]
+#endif
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+	imx6sx_sabresd_ddr_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/board/freescale/mx6ul_14x14_ddr3_val/Kconfig b/board/freescale/mx6ul_14x14_ddr3_val/Kconfig
new file mode 100644
index 00000000000..2f057ef8c6e
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_ddr3_val/Kconfig
@@ -0,0 +1,26 @@
+if TARGET_MX6UL_14X14_DDR3_VAL
+
+config SYS_BOARD
+       default "mx6ul_14x14_ddr3_val"
+
+config SYS_VENDOR
+       default "freescale"
+
+config SYS_CONFIG_NAME
+       default "mx6ul_14x14_ddr3_val"
+
+config MX6UL_DDR3_VAL_EMMC_REWORK
+	bool "Select this for the board with eMMC rework"
+
+config SYS_TEXT_BASE
+	default 0x87800000
+
+config MX6UL_DDR3_VAL_USDHC2_REWORK
+	bool "Select this for the board with 8bits USDHC2 rework"
+
+config NOR
+	bool "Support for NOR flash"
+	help
+	  The i.MX SoC supports having a NOR flash connected to the WEIM.
+	  Need to set this for NOR_BOOT.
+endif
diff --git a/board/freescale/mx6ul_14x14_ddr3_val/Makefile b/board/freescale/mx6ul_14x14_ddr3_val/Makefile
new file mode 100644
index 00000000000..e9f6edc422a
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_ddr3_val/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx6ul_14x14_ddr3_val.o
diff --git a/board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg b/board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg
new file mode 100644
index 00000000000..f21992fd582
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg
@@ -0,0 +1,114 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_QSPI_BOOT
+BOOT_FROM	qspi
+#elif defined(CONFIG_NOR_BOOT)
+BOOT_FROM	nor
+#else
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6ul_14x14_ddr3_val/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+DATA 4 0x020E04B4 0x000C0000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000030
+DATA 4 0x020E0250 0x00000030
+DATA 4 0x020E024C 0x00000030
+DATA 4 0x020E0490 0x00000030
+DATA 4 0x020E0288 0x00000030
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000030
+DATA 4 0x020E0264 0x00000030
+DATA 4 0x020E04A0 0x00000030
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00000030
+DATA 4 0x020E0284 0x00000030
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000030
+DATA 4 0x020E04A4 0x00000030
+DATA 4 0x020E0244 0x00000030
+DATA 4 0x020E0248 0x00000030
+
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B080C 0x0013000F
+DATA 4 0x021B083C 0x415D0159
+DATA 4 0x021B0848 0x4040484F
+DATA 4 0x021B0850 0x40405247
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B08C0 0x00922012
+DATA 4 0x021B08b8 0x00000800
+DATA 4 0x021B0004 0x0002002D
+DATA 4 0x021B0008 0x1B333000
+DATA 4 0x021B000C 0x676B54B3
+DATA 4 0x021B0010 0xB68E0A83
+DATA 4 0x021B0014 0x01FF00DB
+DATA 4 0x021B0018 0x00211740
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B002C 0x000026D2
+DATA 4 0x021B0030 0x006B1023
+DATA 4 0x021B0040 0x0000005F
+DATA 4 0x021B0000 0x85180000
+DATA 4 0x021B001C 0x02008032
+DATA 4 0x021B001C 0x00008033
+DATA 4 0x021B001C 0x00048031
+DATA 4 0x021B001C 0x15208030
+DATA 4 0x021B001C 0x04008040
+DATA 4 0x021B0020 0x00000800
+DATA 4 0x021B0818 0x00000227
+DATA 4 0x021B0004 0x0002552D
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+#endif
diff --git a/board/freescale/mx6ul_14x14_ddr3_val/mx6ul_14x14_ddr3_val.c b/board/freescale/mx6ul_14x14_ddr3_val/mx6ul_14x14_ddr3_val.c
new file mode 100644
index 00000000000..b5ac790e41f
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_ddr3_val/mx6ul_14x14_ddr3_val.c
@@ -0,0 +1,1066 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <env.h>
+#include <fsl_esdhc_imx.h>
+#include <i2c.h>
+#include <linux/sizes.h>
+#include <linux/fb.h>
+#include <miiphy.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+#include <mxsfb.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#include <asm/mach-imx/video.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_SPEED_HIGH   |                                   \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
+	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE)
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+			PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+		PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+		PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
+	PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC and EEPROM */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		/* conflict with usb_otg2_pwr */
+		.i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
+		.gp = IMX_GPIO_NR(1, 2),
+	},
+	.sda = {
+		/* conflict with usb_otg2_oc */
+		.i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
+		.gp = IMX_GPIO_NR(1, 3),
+	},
+};
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+#ifdef CONFIG_MX6UL_DDR3_VAL_EMMC_REWORK
+static iomux_v3_cfg_t const usdhc1_emmc_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/*
+	 * The following 4 pins conflicts with qspi.
+	 * You can comment out the following 4 pins and  change
+	 * {USDHC1_BASE_ADDR, 0, 8}  -> {USDHC1_BASE_ADDR, 0, 4}
+	 * to make emmc and qspi coexists.
+	 */
+	MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/* Default NO WP for emmc, since we use pull down */
+	MX6_PAD_UART1_CTS_B__USDHC1_WP  | MUX_PAD_CTRL(USDHC_PAD_CTRL_WP),
+	/* RST_B */
+	MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#else
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_UART1_CTS_B__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/* VSELECT */
+	MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/* CD */
+	MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* RST_B */
+	MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#endif
+
+#if !defined(CONFIG_CMD_NAND)
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_CSI_VSYNC__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_CSI_HSYNC__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_CSI_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_CSI_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_CSI_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_CSI_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+#ifdef CONFIG_MX6UL_DDR3_VAL_USDHC2_REWORK
+#if defined(CONFIG_MTD_NOR_FLASH) || defined(CONFIG_MXC_SPI)
+#error "Pin conflicts!"
+#endif
+	/* conflict with eimnor/spinor */
+	MX6_PAD_CSI_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_CSI_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_CSI_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_CSI_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+#endif
+	/* VSELECT */
+	MX6_PAD_GPIO1_IO08__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/* CD */
+	MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/*
+	 * Pin conflicts with NAND ALE, if want to test nand,
+	 * Connect R169(B), disconnect R169(A).
+	 *
+	 * RST_B
+	 */
+	MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#endif
+#endif
+
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const nand_pads[] = {
+	MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_CSI_MCLK__RAWNAND_CE2_B   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+};
+
+static void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	SETUP_IOMUX_PADS(nand_pads);
+
+	setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#ifndef CONFIG_DM_SPI
+/* pin conflicts with eim nor */
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+	MX6_PAD_CSI_DATA06__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_CSI_DATA04__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_CSI_DATA07__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+
+	/* CS Pin */
+	MX6_PAD_CSI_DATA05__GPIO4_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_spinor(void)
+{
+	SETUP_IOMUX_PADS(ecspi1_pads);
+	gpio_request(IMX_GPIO_NR(4, 26), "escpi cs");
+	gpio_direction_output(IMX_GPIO_NR(4, 26), 0);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 26)) : -1;
+}
+#endif
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+/* pin conflicts with nand usdhc2 lcd enet, ecspi */
+static iomux_v3_cfg_t const eimnor_pads[] = {
+	MX6_PAD_CSI_DATA00__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_CSI_DATA01__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_CSI_DATA02__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_CSI_DATA03__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_CSI_DATA04__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_CSI_DATA05__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_CSI_DATA06__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_CSI_DATA07__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA00__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA01__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA02__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA03__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA04__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA05__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA06__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA07__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_CLE__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_ALE__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_CE1_B__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_SD1_CMD__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_SD1_CLK__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_ENET2_RX_ER__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_ENET2_RX_EN__EIM_ADDR26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+
+	MX6_PAD_CSI_PIXCLK__EIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_CSI_VSYNC__EIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+
+	MX6_PAD_LCD_DATA08__EIM_DATA00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD_DATA09__EIM_DATA01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD_DATA10__EIM_DATA02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD_DATA11__EIM_DATA03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD_DATA12__EIM_DATA04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD_DATA13__EIM_DATA05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD_DATA14__EIM_DATA06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD_DATA15__EIM_DATA07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD_DATA16__EIM_DATA08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD_DATA17__EIM_DATA09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD_DATA18__EIM_DATA10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD_DATA19__EIM_DATA11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD_DATA20__EIM_DATA12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD_DATA21__EIM_DATA13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD_DATA22__EIM_DATA14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_LCD_DATA23__EIM_DATA15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+
+	MX6_PAD_CSI_MCLK__EIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DQS__EIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void eimnor_cs_setup(void)
+{
+	writel(0x00000120, WEIM_BASE_ADDR + 0x090);
+	writel(0x00010181, WEIM_BASE_ADDR + 0x000);
+	writel(0x00000001, WEIM_BASE_ADDR + 0x004);
+	writel(0x0a020000, WEIM_BASE_ADDR + 0x008);
+	writel(0x0000c000, WEIM_BASE_ADDR + 0x00c);
+	writel(0x0804a240, WEIM_BASE_ADDR + 0x010);
+}
+
+static void setup_eimnor(void)
+{
+	if (check_module_fused(MODULE_EIM)) {
+		printf("WEIM@0x%x is fused, disable it\n", WEIM_BASE_ADDR);
+		return;
+	}
+
+	SETUP_IOMUX_PADS(eimnor_pads);
+
+	eimnor_cs_setup();
+}
+
+int board_flash_wp_on(void)
+{
+	if (check_module_fused(MODULE_EIM))
+		return 1; /* Skip flash init */
+
+	return 0;
+}
+
+#endif
+
+#ifdef CONFIG_FEC_MXC
+/*
+ * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
+ * be used for ENET1 or ENET2, cannot be used for both.
+ */
+static iomux_v3_cfg_t const fec1_pads[] = {
+	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+	/* Pin conflicts with LCD PWM1 */
+	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec1_phy_rst[] = {
+	/*
+	 * ALT5 mode is only valid when TAMPER pin is used for GPIO.
+	 * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0].
+	 *
+	 * ENET1_RST
+	 */
+	MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec2_pads[] = {
+	MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART4_TX_DATA__ENET2_TDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART4_RX_DATA__ENET2_TDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART3_TX_DATA__ENET2_RDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART3_RX_DATA__ENET2_RDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART3_CTS_B__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART5_RX_DATA__ENET2_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART5_TX_DATA__ENET2_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec2_phy_rst[] = {
+	MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_fec(int fec_id)
+{
+	if (fec_id == 0) {
+		SETUP_IOMUX_PADS(fec1_pads);
+	} else {
+		SETUP_IOMUX_PADS(fec2_pads);
+	}
+}
+#endif
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+}
+
+#ifdef CONFIG_FSL_QSPI
+
+#ifndef CONFIG_DM_SPI
+#define QSPI_PAD_CTRL1	\
+	(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
+	 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+	MX6_PAD_NAND_WP_B__QSPI_A_SCLK	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_READY_B__QSPI_A_DATA00	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CE0_B__QSPI_A_DATA01	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CE1_B__QSPI_A_DATA02	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CLE__QSPI_A_DATA03	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DQS__QSPI_A_SS0_B	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA07__QSPI_A_SS1_B	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+
+	MX6_PAD_NAND_RE_B__QSPI_B_SCLK	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_WE_B__QSPI_B_SS0_B	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA00__QSPI_B_SS1_B	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA02__QSPI_B_DATA00	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA03__QSPI_B_DATA01	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA04__QSPI_B_DATA02	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA05__QSPI_B_DATA03	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+#endif
+
+int board_qspi_init(void)
+{
+#ifndef CONFIG_DM_SPI
+	/* Set the iomux */
+	SETUP_IOMUX_PADS(quadspi_pads);
+#endif
+	/* Set the clock */
+	enable_qspi_clk(0);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+#ifdef CONFIG_MX6UL_DDR3_VAL_EMMC_REWORK
+	/* If want to use qspi, should change to 4 bit width */
+	{USDHC1_BASE_ADDR, 0, 8},
+#else
+	{USDHC1_BASE_ADDR, 0, 4},
+#endif
+#if !defined(CONFIG_CMD_NAND)
+	{USDHC2_BASE_ADDR, 0, 4},
+#endif
+};
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 19)
+#define USDHC1_PWR_GPIO	IMX_GPIO_NR(1, 9)
+#define USDHC1_VSELECT IMX_GPIO_NR(1, 5)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(4, 17)
+#define USDHC2_PWR_GPIO	IMX_GPIO_NR(4, 10)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+#ifdef CONFIG_MX6UL_DDR3_VAL_EMMC_REWORK
+		ret = 1;
+#else
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+#endif
+		break;
+#if !defined(CONFIG_CMD_NAND)
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+#endif
+	}
+
+	return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+#ifdef CONFIG_MX6UL_DDR3_VAL_EMMC_REWORK
+			SETUP_IOMUX_PADS(usdhc1_emmc_pads);
+#else
+			SETUP_IOMUX_PADS(usdhc1_pads);
+			gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
+			gpio_direction_input(USDHC1_CD_GPIO);
+#endif
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			/* 3.3V */
+			gpio_request(USDHC1_VSELECT, "usdhc1 vsel");
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1 pwr");
+			gpio_direction_output(USDHC1_VSELECT, 0);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+#if !defined(CONFIG_CMD_NAND)
+		case 1:
+			SETUP_IOMUX_PADS(usdhc2_pads);
+			gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr");
+			gpio_direction_input(USDHC2_CD_GPIO);
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			break;
+#endif
+		default:
+			printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
+			return 0;
+			}
+
+			if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
+				printf("Warning: failed to initialize mmc dev %d\n", i);
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lcd_pads[] = {
+	MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/*
+	 * PWM1, pin conflicts with ENET1_RX_DATA0
+	 * Use GPIO for Brightness adjustment, duty cycle = period.
+	 */
+	/* MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),*/
+};
+
+struct lcd_panel_info_t {
+	unsigned int lcdif_base_addr;
+	int depth;
+	void (*enable)(struct lcd_panel_info_t const *dev);
+	struct fb_videomode mode;
+};
+
+void do_enable_parallel_lcd(struct display_info_t const *dev)
+{
+	enable_lcdif_clock(dev->bus, 1);
+
+	SETUP_IOMUX_PADS(lcd_pads);
+
+	/* Power up the LCD */
+	gpio_request(IMX_GPIO_NR(3, 4), "lcd power");
+	gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
+
+	/* Set Brightness to high */
+	/* gpio_direction_output(IMX_GPIO_NR(2, 0) , 1); */
+}
+
+struct display_info_t const displays[] = {{
+	.bus = MX6UL_LCDIF1_BASE_ADDR,
+	.addr = 0,
+	.pixfmt = 24,
+	.detect = NULL,
+	.enable	= do_enable_parallel_lcd,
+	.mode	= {
+		.name		= "MCIMX28LCD",
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 29850,
+		.left_margin    = 89,
+		.right_margin   = 164,
+		.upper_margin   = 23,
+		.lower_margin   = 10,
+		.hsync_len      = 10,
+		.vsync_len      = 10,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+#endif
+
+#ifdef CONFIG_FEC_MXC
+int board_eth_init(struct bd_info *bis)
+{
+	int ret;
+
+	setup_iomux_fec(CONFIG_FEC_ENET_DEV);
+
+	ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
+		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+	if (ret)
+		printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__);
+
+	return 0;
+}
+
+static int setup_fec(int fec_id)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+	int ret;
+
+	if (0 == fec_id) {
+		if (check_module_fused(MODULE_ENET1))
+			return -1;
+
+		/*
+		 * Use 50M anatop loopback REF_CLK1 for ENET1,
+		 * clear gpr1[13], set gpr1[17]
+		 */
+		clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+		ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
+		if (ret)
+			return ret;
+
+		SETUP_IOMUX_PADS(fec1_phy_rst);
+		gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset");
+		gpio_direction_output(IMX_GPIO_NR(5, 2), 0);
+		udelay(50);
+		gpio_direction_output(IMX_GPIO_NR(5, 2), 1);
+
+	} else {
+		if (check_module_fused(MODULE_ENET2))
+			return -1;
+
+		/* clk from phy, set gpr1[14], clear gpr1[18]*/
+		clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+				IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK);
+
+		SETUP_IOMUX_PADS(fec2_phy_rst);
+		gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset");
+		gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+		udelay(50);
+		gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
+	}
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (CONFIG_FEC_ENET_DEV == 0) {
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x202);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+	} else if (CONFIG_FEC_ENET_DEV == 1) {
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x201);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8110);
+	}
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_POWER_LEGACY
+#define I2C_PMIC	0
+int power_init_board(void)
+{
+	int ret;
+	u32 rev_id, value;
+	static struct pmic *pfuze;
+
+	ret = power_pfuze100_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	pfuze = pmic_get("PFUZE100");
+	if (!pfuze)
+		return -ENODEV;
+
+	ret = pmic_probe(pfuze);
+	if (ret)
+		return ret;
+
+	ret = pfuze_mode_init(pfuze, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value);
+	pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id);
+	printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id);
+
+	/*
+	 * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP
+	 * Configuration is F0.
+	 * Default VOLT:
+	 * VSNVS_VOLT	|	3.0V
+	 * SW1AB	|	1.375V
+	 * SW2		|	3.3V
+	 * SW3A		|	1.5V
+	 * SW3B		|	1.5V
+	 * VGEN1	|	1.5V
+	 * VGEN2	|	1.5V
+	 * VGEN3	|	2.5V
+	 * VGEN4	|	1.8V
+	 * VGEN5	|	2.8V
+	 * VGEN6	|	3.3V
+	 *
+	 * According to schematic, we need SW3A 1.35V, SW3B 3.3V,
+	 * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V,
+	 * VGEN5 3.3V, VGEN6 3.0V.
+	 *
+	 * Here we just use the default VOLT, but not configure
+	 * them, when needed, configure them to our requested voltage.
+	 */
+
+	/* set SW1AB standby volatage 0.975V */
+	pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value);
+	value &= ~0x3f;
+	value |= PFUZE100_SW1ABC_SETP(9750);
+	pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value);
+
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value);
+	value &= ~0xc0;
+	value |= 0x40;
+	pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value);
+
+	/* Enable power of VGEN5 3V3 */
+	pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &value);
+	value &= ~0x1F;
+	value |= 0x1F;
+	pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, value);
+
+	return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+	unsigned int value;
+	int is_400M;
+	u32 vddarm;
+
+	struct pmic *p = pmic_get("PFUZE100");
+
+	if (!p) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* switch to ldo_bypass mode */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+		/* decrease VDDARM to 1.275V */
+		pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value);
+		value &= ~0x3f;
+		value |= PFUZE100_SW1ABC_SETP(12750);
+		pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value);
+
+		is_400M = set_anatop_bypass(1);
+		if (is_400M)
+			vddarm = PFUZE100_SW1ABC_SETP(10750);
+		else
+			vddarm = PFUZE100_SW1ABC_SETP(11750);
+
+		pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value);
+		value &= ~0x3f;
+		value |= vddarm;
+		pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value);
+
+		finish_anatop_bypass();
+
+		printf("switch to ldo_bypass mode!\n");
+	}
+}
+#endif
+
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+	unsigned int reg, dev_id, rev_id;
+
+	ret = pmic_get("pfuze100@8", &dev);
+	if (ret == -ENODEV)
+		return ret;
+
+	ret = pfuze_mode_init(dev, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
+	printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+	/*
+	 * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP
+	 * Configuration is F0.
+	 * Default VOLT:
+	 * VSNVS_VOLT	|	3.0V
+	 * SW1AB	|	1.375V
+	 * SW2		|	3.3V
+	 * SW3A		|	1.5V
+	 * SW3B		|	1.5V
+	 * VGEN1	|	1.5V
+	 * VGEN2	|	1.5V
+	 * VGEN3	|	2.5V
+	 * VGEN4	|	1.8V
+	 * VGEN5	|	2.8V
+	 * VGEN6	|	3.3V
+	 *
+	 * According to schematic, we need SW3A 1.35V, SW3B 3.3V,
+	 * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V,
+	 * VGEN5 3.3V, VGEN6 3.0V.
+	 *
+	 * Here we just use the default VOLT, but not configure
+	 * them, when needed, configure them to our requested voltage.
+	 */
+
+	/* Set SW1AB stanby volage to 0.975V */
+	reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
+	reg &= ~SW1x_STBY_MASK;
+	reg |= SW1x_0_975V;
+	pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
+
+	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
+	reg &= ~SW1xCONF_DVSSPEED_MASK;
+	reg |= SW1xCONF_DVSSPEED_4US;
+	pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
+
+	/* Enable power of VGEN5 3V3 */
+	reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
+	reg &= ~0x1F;
+	reg |= 0x1F;
+	pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
+
+	return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+	struct udevice *dev;
+	int ret;
+	int is_400M;
+	u32 vddarm;
+
+	ret = pmic_get("pfuze100", &dev);
+	if (ret == -ENODEV) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* switch to ldo_bypass mode */
+	if (ldo_bypass) {
+		/* decrease VDDARM to 1.275V */
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750));
+
+		is_400M = set_anatop_bypass(1);
+		if (is_400M)
+			vddarm = PFUZE100_SW1ABC_SETP(10750);
+		else
+			vddarm = PFUZE100_SW1ABC_SETP(11750);
+
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
+
+		set_anatop_bypass(1);
+
+		printf("switch to ldo_bypass mode!\n");
+	}
+}
+#endif
+
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/*
+	 * Because kernel set WDOG_B mux before pad with the commone pinctrl
+	 * framwork now and wdog reset will be triggered once set WDOG_B mux
+	 * with default pad setting, we set pad setting here to workaround this.
+	 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
+	 * as GPIO mux firstly here to workaround it.
+	 *
+	 * Here we can not set this, since SD1_RST_B conflicts with GWDOG.
+	 * We use SD1, so will not set WDOG pads, also GWDOG default is
+	 * DNP.
+	 */
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec(CONFIG_FEC_ENET_DEV);
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#ifndef CONFIG_DM_SPI
+	setup_spinor();
+#endif
+#endif
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+	setup_eimnor();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
+	{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return get_cpu_rev();
+}
+
+int checkboard(void)
+{
+	puts("Board: MX6UL 14X14 DDR3 Validation\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+iomux_v3_cfg_t const usb_otg1_pads[] = {
+	MX6_PAD_GPIO1_IO04__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+};
+
+/*
+ * Leave it here, but default configuration only supports 1 port now,
+ * because we need sd1 and i2c1
+ */
+iomux_v3_cfg_t const usb_otg2_pads[] = {
+	/* conflict with i2c1_scl */
+	MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* conflict with sd1_vselect */
+	MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+};
+
+int board_usb_phy_mode(int port)
+{
+	return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+
+	switch (port) {
+	case 0:
+		SETUP_IOMUX_PADS(usb_otg1_pads);
+		break;
+	case 1:
+		SETUP_IOMUX_PADS(usb_otg2_pads);
+		break;
+	default:
+		printf("MXC USB port %d not yet supported\n", port);
+		return 1;
+	}
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	/* Set Power polarity */
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
+}
+#endif
+#endif
diff --git a/board/freescale/mx6ul_14x14_ddr3_val/plugin.S b/board/freescale/mx6ul_14x14_ddr3_val/plugin.S
new file mode 100644
index 00000000000..06b939fc244
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_ddr3_val/plugin.S
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6ul_ddr3_val_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000C0000
+	str r1, [r0, #0x4B4]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4AC]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x27C]
+	str r1, [r0, #0x250]
+	str r1, [r0, #0x24C]
+	str r1, [r0, #0x490]
+	str r1, [r0, #0x288]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x270]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x260]
+	str r1, [r0, #0x264]
+	str r1, [r0, #0x4A0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x494]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x280]
+	str r1, [r0, #0x284]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x4B0]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x498]
+	str r1, [r0, #0x4A4]
+	str r1, [r0, #0x244]
+	str r1, [r0, #0x248]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1C]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x0013000F
+	str r1, [r0, #0x80C]
+	ldr r1, =0x415D0159
+	str r1, [r0, #0x83C]
+	ldr r1, =0x4040484F
+	str r1, [r0, #0x848]
+	ldr r1, =0x40405247
+	str r1, [r0, #0x850]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81C]
+	str r1, [r0, #0x820]
+	ldr r1, =0xF3333333
+	str r1, [r0, #0x82C]
+	str r1, [r0, #0x830]
+	ldr r1, =0x00922012
+	str r1, [r0, #0x8C0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8B8]
+	ldr r1, =0x0002002D
+	str r1, [r0, #0x004]
+	ldr r1, =0x1B333000
+	str r1, [r0, #0x008]
+	ldr r1, =0x676B54B3
+	str r1, [r0, #0x00C]
+	ldr r1, =0xB68E0A83
+	str r1, [r0, #0x010]
+	ldr r1, =0x01FF00DB
+	str r1, [r0, #0x014]
+	ldr r1, =0x00211740
+	str r1, [r0, #0x018]
+	ldr r1, =0x00008000
+	str r1, [r0, #0x01C]
+	ldr r1, =0x000026D2
+	str r1, [r0, #0x02C]
+	ldr r1, =0x006B1023
+	str r1, [r0, #0x030]
+	ldr r1, =0x0000005F
+	str r1, [r0, #0x040]
+	ldr r1, =0x85180000
+	str r1, [r0, #0x000]
+	ldr r1, =0x02008032
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00008033
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00048031
+	str r1, [r0, #0x01C]
+	ldr r1, =0x15208030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04008040
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x020]
+	ldr r1, =0x00000227
+	str r1, [r0, #0x818]
+	ldr r1, =0x0002552D
+	str r1, [r0, #0x004]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x01C]
+.endm
+
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #0x68]
+	str r1, [r0, #0x6C]
+	str r1, [r0, #0x70]
+	str r1, [r0, #0x74]
+	str r1, [r0, #0x78]
+	str r1, [r0, #0x7C]
+	str r1, [r0, #0x80]
+	str r1, [r0, #0x84]
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+	imx6ul_ddr3_val_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/board/freescale/mx6ul_14x14_evk/Kconfig b/board/freescale/mx6ul_14x14_evk/Kconfig
index 8210cd3cb88..c81a613d853 100644
--- a/board/freescale/mx6ul_14x14_evk/Kconfig
+++ b/board/freescale/mx6ul_14x14_evk/Kconfig
@@ -9,4 +9,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "mx6ul_14x14_evk"
 
+config SYS_TEXT_BASE
+	default 0x87800000
 endif
diff --git a/board/freescale/mx6ul_14x14_evk/imximage.cfg b/board/freescale/mx6ul_14x14_evk/imximage.cfg
new file mode 100644
index 00000000000..b3c5fc9f5f7
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_evk/imximage.cfg
@@ -0,0 +1,196 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_QSPI_BOOT
+BOOT_FROM	qspi
+#elif defined(CONFIG_NOR_BOOT)
+BOOT_FROM	nor
+#else
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6ul_14x14_evk/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+#ifdef CONFIG_DDR3L_MT41K256M16HA
+
+/* DDR type MT41K256M16HA-125 which is EOL */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+#ifdef CONFIG_IMX_OPTEE
+DATA 4 0x20e4024 0x00000001
+CHECK_BITS_SET 4 0x20e4024 0x1
+#endif
+
+DATA 4 0x020E04B4 0x000C0000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000030
+DATA 4 0x020E0250 0x00000030
+DATA 4 0x020E024C 0x00000030
+DATA 4 0x020E0490 0x00000030
+DATA 4 0x020E0288 0x00000030
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000030
+DATA 4 0x020E0264 0x00000030
+DATA 4 0x020E04A0 0x00000030
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00000030
+DATA 4 0x020E0284 0x00000030
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000030
+DATA 4 0x020E04A4 0x00000030
+DATA 4 0x020E0244 0x00000030
+DATA 4 0x020E0248 0x00000030
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B080C 0x00000000
+DATA 4 0x021B083C 0x41490145
+DATA 4 0x021B0848 0x40404546
+DATA 4 0x021B0850 0x4040524D
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B08C0 0x00921012
+DATA 4 0x021B08b8 0x00000800
+DATA 4 0x021B0004 0x0002002D
+DATA 4 0x021B0008 0x00333030
+DATA 4 0x021B000C 0x676B52F3
+DATA 4 0x021B0010 0xB66D8B63
+DATA 4 0x021B0014 0x01FF00DB
+DATA 4 0x021B0018 0x00201740
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B002C 0x000026D2
+DATA 4 0x021B0030 0x006B1023
+DATA 4 0x021B0040 0x0000004F
+DATA 4 0x021B0000 0x84180000
+DATA 4 0x021B001C 0x02008032
+DATA 4 0x021B001C 0x00008033
+DATA 4 0x021B001C 0x00048031
+DATA 4 0x021B001C 0x15208030
+DATA 4 0x021B001C 0x04008040
+DATA 4 0x021B0020 0x00000800
+DATA 4 0x021B0818 0x00000227
+DATA 4 0x021B0004 0x0002552D
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+
+#else
+
+/* New DDR type MT41K256M16TW-107 */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+#ifdef CONFIG_IMX_OPTEE
+DATA 4 0x20e4024 0x00000001
+CHECK_BITS_SET 4 0x20e4024 0x1
+#endif
+
+DATA 4 0x020E04B4 0x000C0000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000030
+DATA 4 0x020E0250 0x00000030
+DATA 4 0x020E024C 0x00000030
+DATA 4 0x020E0490 0x00000030
+DATA 4 0x020E0288 0x00000030
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000030
+DATA 4 0x020E0264 0x00000030
+DATA 4 0x020E04A0 0x00000030
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00000030
+DATA 4 0x020E0284 0x00000030
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000030
+DATA 4 0x020E04A4 0x00000030
+DATA 4 0x020E0244 0x00000030
+DATA 4 0x020E0248 0x00000030
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B080C 0x00000000
+DATA 4 0x021B083C 0x41570155
+DATA 4 0x021B0848 0x4040474A
+DATA 4 0x021B0850 0x40405550
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B08C0 0x00921012
+DATA 4 0x021B08b8 0x00000800
+DATA 4 0x021B0004 0x0002002D
+DATA 4 0x021B0008 0x1B333030
+DATA 4 0x021B000C 0x676B52F3
+DATA 4 0x021B0010 0xB66D0B63
+DATA 4 0x021B0014 0x01FF00DB
+DATA 4 0x021B0018 0x00201740
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B002C 0x000026D2
+DATA 4 0x021B0030 0x006B1023
+DATA 4 0x021B0040 0x0000004F
+DATA 4 0x021B0000 0x84180000
+DATA 4 0x021B0890 0x23400A38
+DATA 4 0x021B001C 0x02008032
+DATA 4 0x021B001C 0x00008033
+DATA 4 0x021B001C 0x00048031
+DATA 4 0x021B001C 0x15208030
+DATA 4 0x021B001C 0x04008040
+DATA 4 0x021B0020 0x00000800
+DATA 4 0x021B0818 0x00000227
+DATA 4 0x021B0004 0x0002552D
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+#endif
+#endif
diff --git a/board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg b/board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg
new file mode 100644
index 00000000000..e5c8c9d44f2
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_QSPI_BOOT
+BOOT_FROM       qspi
+#elif defined(CONFIG_NOR_BOOT)
+BOOT_FROM       nor
+#else
+BOOT_FROM       sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6ul_14x14_evk/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+#ifdef CONFIG_IMX_OPTEE
+DATA 4 0x20e4024 0x00000001
+CHECK_BITS_SET 4 0x20e4024 0x1
+#endif
+
+DATA 4 0x020E04B4 0x00080000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000030
+DATA 4 0x020E0250 0x00000030
+DATA 4 0x020E024C 0x00000030
+DATA 4 0x020E0490 0x00000030
+DATA 4 0x020E0288 0x00000030
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000000
+DATA 4 0x020E0264 0x00000000
+DATA 4 0x020E04A0 0x00000030
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00003030
+DATA 4 0x020E0284 0x00003030
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000030
+DATA 4 0x020E04A4 0x00000030
+DATA 4 0x020E0244 0x00000030
+DATA 4 0x020E0248 0x00000030
+
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B085C 0x1b4700c7
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B0890 0x00470000
+DATA 4 0x021B08b8 0x00000800
+
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B083C 0x20000000
+DATA 4 0x021B0848 0x4040484F
+DATA 4 0x021B0850 0x40405247
+DATA 4 0x021B08C0 0x00922012
+DATA 4 0x021B08b8 0x00000800
+
+DATA 4 0x021B0004 0x00020012
+DATA 4 0x021B0008 0x00000000
+DATA 4 0x021B000C 0x33374133
+DATA 4 0x021B0010 0x00100A82
+DATA 4 0x021B0038 0x00170557
+DATA 4 0x021B0014 0x00000093
+DATA 4 0x021B0018 0x00001748
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B002C 0x0F9F0682
+DATA 4 0x021B0030 0x009F0010
+DATA 4 0x021B0040 0x00000047
+DATA 4 0x021B0000 0x83100000
+DATA 4 0x021B001C 0x00008010
+DATA 4 0x021B001C 0x003F8030
+DATA 4 0x021B001C 0xFF0A8030
+DATA 4 0x021B001C 0x82018030
+DATA 4 0x021B001C 0x04028030
+DATA 4 0x021B001C 0x01038030
+DATA 4 0x021B0020 0x00001800
+DATA 4 0x021B0818 0x00000000
+DATA 4 0x021B0800 0xA1310003
+DATA 4 0x021B0004 0x00025576
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+#endif
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index b916ea01029..221a1ba791e 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -48,6 +48,11 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SPEED_HIGH   |                                  \
 	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
 
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+			PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
 	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
 
@@ -67,7 +72,7 @@ int power_init_board(void)
 	int ret, dev_id, rev_id;
 	unsigned int reg;
 
-	ret = pmic_get("pfuze3000", &dev);
+	ret = pmic_get("pfuze3000@8", &dev);
 	if (ret == -ENODEV)
 		return 0;
 	if (ret != 0)
@@ -93,6 +98,44 @@ int power_init_board(void)
 
 	return 0;
 }
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+	unsigned int value;
+	u32 vddarm;
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("pfuze3000@8", &dev);
+	if (ret == -ENODEV) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* switch to ldo_bypass mode */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+		/* decrease VDDARM to 1.275V */
+		value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
+		value &= ~0x1f;
+		value |= PFUZE3000_SW1AB_SETP(12750);
+		pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value);
+
+		set_anatop_bypass(1);
+		vddarm = PFUZE3000_SW1AB_SETP(11750);
+
+		value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
+		value &= ~0x1f;
+		value |= vddarm;
+		pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value);
+
+		finish_anatop_bypass();
+
+		printf("switch to ldo_bypass mode!\n");
+	}
+}
+#endif
 #endif
 
 int dram_init(void)
@@ -198,32 +241,74 @@ int board_ehci_hcd_init(int port)
 #endif
 #endif
 
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const nand_pads[] = {
+	MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+};
+
+static void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+
+	setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
 #ifdef CONFIG_FEC_MXC
-static int setup_fec(int fec_id)
+static int setup_fec(void)
 {
 	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	int ret;
 
-	if (fec_id == 0) {
-		/*
-		 * Use 50M anatop loopback REF_CLK1 for ENET1,
-		 * clear gpr1[13], set gpr1[17].
-		 */
-		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
-				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
-	} else {
-		/*
-		 * Use 50M anatop loopback REF_CLK2 for ENET2,
-		 * clear gpr1[14], set gpr1[18].
-		 */
+	/*
+	 * Use 50M anatop loopback REF_CLK1 for ENET1,
+	 * clear gpr1[13], set gpr1[17].
+	 */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+	/*
+	 * Use 50M anatop loopback REF_CLK2 for ENET2,
+	 * clear gpr1[14], set gpr1[18].
+	 */
+	if (!check_module_fused(MODULE_ENET2)) {
 		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
 				IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
 	}
 
-	ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
+	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 	if (ret)
 		return ret;
 
+	if (!check_module_fused(MODULE_ENET2)) {
+		ret = enable_fec_anatop_clock(1, ENET_50MHZ);
+		if (ret)
+			return ret;
+	}
+
 	enable_enet_clk(1);
 
 	return 0;
@@ -280,8 +365,8 @@ int board_init(void)
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-#ifdef	CONFIG_FEC_MXC
-	setup_fec(CONFIG_FEC_ENET_DEV);
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
 #endif
 
 #ifdef CONFIG_USB_EHCI_MX6
@@ -294,6 +379,10 @@ int board_init(void)
 	board_qspi_init();
 #endif
 
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+
 	return 0;
 }
 
@@ -313,6 +402,11 @@ int board_late_init(void)
 	add_board_boot_modes(board_boot_modes);
 #endif
 
+	env_set("tee", "no");
+#ifdef CONFIG_IMX_OPTEE
+	env_set("tee", "yes");
+#endif
+
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	env_set("board_name", "EVK");
 
@@ -324,6 +418,12 @@ int board_late_init(void)
 
 	setup_lcd();
 
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
+
 	return 0;
 }
 
diff --git a/board/freescale/mx6ul_14x14_evk/plugin.S b/board/freescale/mx6ul_14x14_evk/plugin.S
new file mode 100644
index 00000000000..e420d5d2d33
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_evk/plugin.S
@@ -0,0 +1,373 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6ul_ddr3_evk_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000C0000
+	str r1, [r0, #0x4B4]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4AC]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x27C]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x250]
+	str r1, [r0, #0x24C]
+	str r1, [r0, #0x490]
+	str r1, [r0, #0x288]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x270]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x260]
+	str r1, [r0, #0x264]
+	str r1, [r0, #0x4A0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x494]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x280]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x284]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x4B0]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x498]
+	str r1, [r0, #0x4A4]
+	str r1, [r0, #0x244]
+	str r1, [r0, #0x248]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1C]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x80C]
+	ldr r1, =0x41570155
+	str r1, [r0, #0x83C]
+	ldr r1, =0x4040474A
+	str r1, [r0, #0x848]
+	ldr r1, =0x40405550
+	str r1, [r0, #0x850]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81C]
+	str r1, [r0, #0x820]
+	ldr r1, =0xF3333333
+	str r1, [r0, #0x82C]
+	str r1, [r0, #0x830]
+	ldr r1, =0x00921012
+	str r1, [r0, #0x8C0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8B8]
+	ldr r1, =0x0002002D
+	str r1, [r0, #0x004]
+	ldr r1, =0x1B333030
+	str r1, [r0, #0x008]
+	ldr r1, =0x676B52F3
+	str r1, [r0, #0x00C]
+	ldr r1, =0xB66D0B63
+	str r1, [r0, #0x010]
+	ldr r1, =0x01FF00DB
+	str r1, [r0, #0x014]
+	ldr r1, =0x00201740
+	str r1, [r0, #0x018]
+	ldr r1, =0x00008000
+	str r1, [r0, #0x01C]
+	ldr r1, =0x000026D2
+	str r1, [r0, #0x02C]
+	ldr r1, =0x006B1023
+	str r1, [r0, #0x030]
+	ldr r1, =0x0000004F
+	str r1, [r0, #0x040]
+	ldr r1, =0x84180000
+	str r1, [r0, #0x000]
+	ldr r1, =0x23400A38
+	str r1, [r0, #0x890]
+	ldr r1, =0x02008032
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00008033
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00048031
+	str r1, [r0, #0x01C]
+	ldr r1, =0x15208030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04008040
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x020]
+	ldr r1, =0x00000227
+	str r1, [r0, #0x818]
+	ldr r1, =0x0002552D
+	str r1, [r0, #0x004]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x01C]
+.endm
+
+.macro imx6ul_ddr3_eol_evk_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000C0000
+	str r1, [r0, #0x4B4]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4AC]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x27C]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x250]
+	str r1, [r0, #0x24C]
+	str r1, [r0, #0x490]
+	str r1, [r0, #0x288]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x270]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x260]
+	str r1, [r0, #0x264]
+	str r1, [r0, #0x4A0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x494]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x280]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x284]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x4B0]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x498]
+	str r1, [r0, #0x4A4]
+	str r1, [r0, #0x244]
+	str r1, [r0, #0x248]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1C]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x80C]
+	ldr r1, =0x41490145
+	str r1, [r0, #0x83C]
+	ldr r1, =0x40404546
+	str r1, [r0, #0x848]
+	ldr r1, =0x4040524D
+	str r1, [r0, #0x850]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81C]
+	str r1, [r0, #0x820]
+	ldr r1, =0xF3333333
+	str r1, [r0, #0x82C]
+	str r1, [r0, #0x830]
+	ldr r1, =0x00921012
+	str r1, [r0, #0x8C0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8B8]
+	ldr r1, =0x0002002D
+	str r1, [r0, #0x004]
+	ldr r1, =0x00333030
+	str r1, [r0, #0x008]
+	ldr r1, =0x676B52F3
+	str r1, [r0, #0x00C]
+	ldr r1, =0xB66D8B63
+	str r1, [r0, #0x010]
+	ldr r1, =0x01FF00DB
+	str r1, [r0, #0x014]
+	ldr r1, =0x00201740
+	str r1, [r0, #0x018]
+	ldr r1, =0x00008000
+	str r1, [r0, #0x01C]
+	ldr r1, =0x000026D2
+	str r1, [r0, #0x02C]
+	ldr r1, =0x006B1023
+	str r1, [r0, #0x030]
+	ldr r1, =0x0000004F
+	str r1, [r0, #0x040]
+	ldr r1, =0x84180000
+	str r1, [r0, #0x000]
+	ldr r1, =0x02008032
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00008033
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00048031
+	str r1, [r0, #0x01C]
+	ldr r1, =0x15208030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04008040
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x020]
+	ldr r1, =0x00000227
+	str r1, [r0, #0x818]
+	ldr r1, =0x0002552D
+	str r1, [r0, #0x004]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x01C]
+.endm
+
+.macro imx6ul_lpddr2_evk_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x00080000
+	str r1, [r0, #0x4B4]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4AC]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x27C]
+	str r1, [r0, #0x250]
+	str r1, [r0, #0x24C]
+	str r1, [r0, #0x490]
+	str r1, [r0, #0x288]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x270]
+	str r1, [r0, #0x260]
+	str r1, [r0, #0x264]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4A0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x494]
+
+	ldr r1, =0x00003030
+	str r1, [r0, #0x280]
+	ldr r1, =0x00003030
+	str r1, [r0, #0x284]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x4B0]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x498]
+	str r1, [r0, #0x4A4]
+	str r1, [r0, #0x244]
+	str r1, [r0, #0x248]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1C]
+	ldr r1, =0x1b4700c7
+	str r1, [r0, #0x85c]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00470000
+	str r1, [r0, #0x890]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8b8]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81C]
+	str r1, [r0, #0x820]
+	ldr r1, =0xF3333333
+	str r1, [r0, #0x82C]
+	str r1, [r0, #0x830]
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83C]
+	ldr r1, =0x4040484F
+	str r1, [r0, #0x848]
+	ldr r1, =0x40405247
+	str r1, [r0, #0x850]
+	ldr r1, =0x00922012
+	str r1, [r0, #0x8C0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8B8]
+
+	ldr r1, =0x00020012
+	str r1, [r0, #0x004]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x008]
+	ldr r1, =0x33374133
+	str r1, [r0, #0x00C]
+	ldr r1, =0x00100A82
+	str r1, [r0, #0x010]
+	ldr r1, =0x00170557
+	str r1, [r0, #0x038]
+	ldr r1, =0x00000093
+	str r1, [r0, #0x014]
+	ldr r1, =0x00001748
+	str r1, [r0, #0x018]
+	ldr r1, =0x00008000
+	str r1, [r0, #0x01C]
+	ldr r1, =0x0F9F0682
+	str r1, [r0, #0x02C]
+	ldr r1, =0x009F0010
+	str r1, [r0, #0x030]
+	ldr r1, =0x00000047
+	str r1, [r0, #0x040]
+	ldr r1, =0x83100000
+	str r1, [r0, #0x000]
+	ldr r1, =0x00008010
+	str r1, [r0, #0x01C]
+	ldr r1, =0x003F8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0xFF0A8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x82018030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04028030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x01038030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00001800
+	str r1, [r0, #0x020]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x818]
+	ldr r1, =0xA1310003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00025576
+	str r1, [r0, #0x004]
+	ldr r1, =0x00010106
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x01C]
+.endm
+
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #0x68]
+	str r1, [r0, #0x6C]
+	str r1, [r0, #0x70]
+	str r1, [r0, #0x74]
+	str r1, [r0, #0x78]
+	str r1, [r0, #0x7C]
+	str r1, [r0, #0x80]
+
+#ifdef CONFIG_IMX_OPTEE
+	ldr r0, =0x20e4024
+	ldr r1, =1
+	str r1, [r0]
+#endif
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+#if defined (CONFIG_TARGET_MX6UL_9X9_EVK)
+	imx6ul_lpddr2_evk_setting
+#elif defined(CONFIG_DDR3L_MT41K256M16HA)
+	imx6ul_ddr3_eol_evk_setting
+#else
+	imx6ul_ddr3_evk_setting
+#endif
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/board/freescale/mx6ul_14x14_lpddr2_val/Kconfig b/board/freescale/mx6ul_14x14_lpddr2_val/Kconfig
new file mode 100644
index 00000000000..28c4515b73c
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_lpddr2_val/Kconfig
@@ -0,0 +1,24 @@
+if TARGET_MX6UL_14X14_LPDDR2_VAL
+
+config SYS_BOARD
+       default "mx6ul_14x14_lpddr2_val"
+
+config SYS_VENDOR
+       default "freescale"
+
+config SYS_CONFIG_NAME
+       default "mx6ul_14x14_lpddr2_val"
+
+config SYS_TEXT_BASE
+	default 0x87800000
+
+config MX6UL_LPDDR2_VAL_USDHC2_REWORK
+	bool "Select this for the board with 8bits USDHC2 rework"
+
+config NOR
+	bool "Support for NOR flash"
+	help
+	  The i.MX SoC supports having a NOR flash connected to the WEIM.
+	  Need to set this for NOR_BOOT.
+
+endif
diff --git a/board/freescale/mx6ul_14x14_lpddr2_val/Makefile b/board/freescale/mx6ul_14x14_lpddr2_val/Makefile
new file mode 100644
index 00000000000..e056bae1572
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_lpddr2_val/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx6ul_14x14_lpddr2_val.o
diff --git a/board/freescale/mx6ul_14x14_lpddr2_val/imximage.cfg b/board/freescale/mx6ul_14x14_lpddr2_val/imximage.cfg
new file mode 100644
index 00000000000..abf12a84c7e
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_lpddr2_val/imximage.cfg
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_QSPI_BOOT
+BOOT_FROM	qspi
+#elif defined(CONFIG_NOR_BOOT)
+BOOT_FROM	nor
+#else
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6ul_14x14_lpddr2_val/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+DATA 4 0x020E04B4 0x00080000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000028
+DATA 4 0x020E0250 0x00000028
+DATA 4 0x020E024C 0x00000028
+DATA 4 0x020E0490 0x00000028
+DATA 4 0x020E0288 0x00000028
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000000
+DATA 4 0x020E0264 0x00000000
+DATA 4 0x020E04A0 0x00000028
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00003028
+DATA 4 0x020E0284 0x00003028
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000028
+DATA 4 0x020E04A4 0x00000028
+DATA 4 0x020E0244 0x00000028
+DATA 4 0x020E0248 0x00000028
+
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B085C 0x1b4700c7
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B0890 0x00470000
+DATA 4 0x021B08b8 0x00000800
+
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B083C 0x20000000
+DATA 4 0x021B0848 0x4040484F
+DATA 4 0x021B0850 0x40405247
+DATA 4 0x021B08C0 0x00922012
+DATA 4 0x021B08b8 0x00000800
+
+DATA 4 0x021B0004 0x00020012
+DATA 4 0x021B0008 0x00000000
+DATA 4 0x021B000C 0x33374133
+DATA 4 0x021B0010 0x00100A82
+DATA 4 0x021B0038 0x00170557
+DATA 4 0x021B0014 0x00000093
+DATA 4 0x021B0018 0x00001748
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B002C 0x0F9F0682
+DATA 4 0x021B0030 0x009F0010
+DATA 4 0x021B0040 0x00000047
+DATA 4 0x021B0000 0x83100000
+DATA 4 0x021B001C 0x00008010
+DATA 4 0x021B001C 0x003F8030
+DATA 4 0x021B001C 0xFF0A8030
+DATA 4 0x021B001C 0x82018030
+DATA 4 0x021B001C 0x04028030
+DATA 4 0x021B001C 0x01038030
+DATA 4 0x021B0020 0x00001800
+DATA 4 0x021B0818 0x00000000
+DATA 4 0x021B0800 0xA1310003
+DATA 4 0x021B0004 0x00025576
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+#endif
diff --git a/board/freescale/mx6ul_14x14_lpddr2_val/mx6ul_14x14_lpddr2_val.c b/board/freescale/mx6ul_14x14_lpddr2_val/mx6ul_14x14_lpddr2_val.c
new file mode 100644
index 00000000000..f2ea14eddec
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_lpddr2_val/mx6ul_14x14_lpddr2_val.c
@@ -0,0 +1,1022 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <env.h>
+#include <fsl_esdhc_imx.h>
+#include <i2c.h>
+#include <linux/sizes.h>
+#include <linux/fb.h>
+#include <miiphy.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <mmc.h>
+#include <mxsfb.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#include <asm/mach-imx/video.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_SPEED_HIGH   |                                   \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
+	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE)
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+			PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+		PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+		PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
+	PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC and EEPROM */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		/* conflict with usb_otg2_pwr */
+		.i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
+		.gp = IMX_GPIO_NR(1, 2),
+	},
+	.sda = {
+		/* conflict with usb_otg2_oc */
+		.i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
+		.gp = IMX_GPIO_NR(1, 3),
+	},
+};
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+#if !defined(CONFIG_CMD_NAND)
+	MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+#endif
+
+	MX6_PAD_CSI_DATA04__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/* VSELECT */
+	MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/* CD */
+	MX6_PAD_CSI_DATA05__GPIO4_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* RST_B */
+	MX6_PAD_NAND_WP_B__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#if !defined(CONFIG_CMD_NAND)
+
+#ifdef CONFIG_MX6UL_LPDDR2_VAL_USDHC2_REWORK
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	MX6_PAD_UART1_CTS_B__USDHC2_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/* VSELECT */
+	MX6_PAD_GPIO1_IO08__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/* CD */
+	MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* RST_B */
+	MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#else
+static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
+	MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/* Default NO WP for emmc, since we use pull down */
+	MX6_PAD_UART1_CTS_B__USDHC2_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL_WP),
+
+	/* RST_B */
+	MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#endif
+#endif
+
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const nand_pads[] = {
+	MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_CSI_MCLK__RAWNAND_CE2_B   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+};
+
+static void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	SETUP_IOMUX_PADS(nand_pads);
+
+	setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#ifndef CONFIG_DM_SPI
+/* pin conflicts with eim nor */
+static iomux_v3_cfg_t const ecspi2_pads[] = {
+	MX6_PAD_CSI_DATA02__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_CSI_DATA00__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_CSI_DATA03__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+
+	/* CS Pin */
+	MX6_PAD_CSI_DATA01__GPIO4_IO22  | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_spinor(void)
+{
+	SETUP_IOMUX_PADS(ecspi1_pads);
+	gpio_request(IMX_GPIO_NR(4, 22), "escpi cs");
+	gpio_direction_output(IMX_GPIO_NR(4, 22), 0);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 1 && cs == 0) ? (IMX_GPIO_NR(4, 22)) : -1;
+}
+#endif
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+/* pin conflicts with ECSIP2, USDHC1, USDCH2, NAND, SIM, ENET2 */
+static iomux_v3_cfg_t const eimnor_pads[] = {
+	MX6_PAD_NAND_CLE__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_ALE__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_CE1_B__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_SD1_CMD__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_SD1_CLK__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_ENET2_RX_ER__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+
+	MX6_PAD_CSI_PIXCLK__EIM_OE   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_CSI_VSYNC__EIM_RW    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_CSI_HSYNC__EIM_LBA_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+
+	MX6_PAD_CSI_DATA00__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_CSI_DATA01__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_CSI_DATA02__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_CSI_DATA03__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_CSI_DATA04__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_CSI_DATA05__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_CSI_DATA06__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_CSI_DATA07__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA00__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA01__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA02__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA03__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA04__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA05__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA06__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DATA07__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+
+	MX6_PAD_CSI_MCLK__EIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_WP_B__EIM_BCLK | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX6_PAD_NAND_DQS__EIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void eimnor_cs_setup(void)
+{
+	writel(0x00000120, WEIM_BASE_ADDR + 0x090);
+	writel(0x00610089, WEIM_BASE_ADDR + 0x000);
+	writel(0x00000001, WEIM_BASE_ADDR + 0x004);
+	writel(0x1c022000, WEIM_BASE_ADDR + 0x008);
+	writel(0x00000000, WEIM_BASE_ADDR + 0x00c);
+	writel(0x1404a38e, WEIM_BASE_ADDR + 0x010);
+}
+
+static void setup_eimnor(void)
+{
+	SETUP_IOMUX_PADS(eimnor_pads);
+
+	eimnor_cs_setup();
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+/*
+ * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
+ * be used for ENET1 or ENET2, cannot be used for both.
+ */
+static iomux_v3_cfg_t const fec2_pads[] = {
+	MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+
+	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec1_phy_rst[] = {
+	/*
+	 * ALT5 mode is only valid when TAMPER pin is used for GPIO.
+	 * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0].
+	 *
+	 * ENET1_RST
+	 */
+	MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/* Conflict with UART1 */
+static iomux_v3_cfg_t const fec1_pads[] = {
+	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART2_TX_DATA__ENET1_TDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART2_RX_DATA__ENET1_TDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART1_TX_DATA__ENET1_RDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__ENET1_RDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART1_CTS_B__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART2_RTS_B__ENET1_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART2_CTS_B__ENET1_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec2_phy_rst[] = {
+	MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_fec(int fec_id)
+{
+	if (fec_id == 0) {
+		SETUP_IOMUX_PADS(fec1_pads);
+	} else {
+		SETUP_IOMUX_PADS(fec2_pads);
+	}
+}
+#endif
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+}
+
+#ifdef CONFIG_FSL_QSPI
+
+#ifndef CONFIG_DM_SPI
+#define QSPI_PAD_CTRL1	\
+	(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
+	 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+	MX6_PAD_NAND_WP_B__QSPI_A_SCLK	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_READY_B__QSPI_A_DATA00	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CE0_B__QSPI_A_DATA01	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CE1_B__QSPI_A_DATA02	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CLE__QSPI_A_DATA03	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DQS__QSPI_A_SS0_B	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA07__QSPI_A_SS1_B	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+
+	MX6_PAD_NAND_RE_B__QSPI_B_SCLK	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_WE_B__QSPI_B_SS0_B	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA00__QSPI_B_SS1_B	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA02__QSPI_B_DATA00	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA03__QSPI_B_DATA01	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA04__QSPI_B_DATA02	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA05__QSPI_B_DATA03	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+#endif
+
+int board_qspi_init(void)
+{
+#ifndef CONFIG_DM_SPI
+	/* Set the iomux */
+	SETUP_IOMUX_PADS(quadspi_pads);
+#endif
+	/* Set the clock */
+	enable_qspi_clk(0);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+#if !defined(CONFIG_CMD_NAND)
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 1},
+	{USDHC2_BASE_ADDR, 0, 8},
+};
+#else
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC1_BASE_ADDR, 0, 4},
+};
+#endif
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(4, 26)
+#define USDHC1_PWR_GPIO	IMX_GPIO_NR(4, 11)
+#define USDHC1_VSELECT IMX_GPIO_NR(1, 5)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(1, 19)
+#define USDHC2_PWR_GPIO	IMX_GPIO_NR(4, 10)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+#if !defined(CONFIG_CMD_NAND)
+	case USDHC2_BASE_ADDR:
+#ifdef CONFIG_MX6UL_LPDDR2_VAL_USDHC2_REWORK
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+#else
+		ret = 1;
+#endif
+		break;
+#endif
+	}
+
+	return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc1_pads);
+			gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
+			gpio_direction_input(USDHC1_CD_GPIO);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1 pwr");
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+#if !defined(CONFIG_CMD_NAND)
+		case 1:
+#ifdef CONFIG_MX6UL_LPDDR2_VAL_USDHC2_REWORK
+			SETUP_IOMUX_PADS(usdhc2_pads);
+			gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr");
+			gpio_direction_input(USDHC2_CD_GPIO);
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#else
+			SETUP_IOMUX_PADS(usdhc2_emmc_pads);
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr");
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#endif
+			break;
+#endif
+		default:
+			printf("Warning: you configured more USDHC controllers (%d)"
+				" than supported by the board\n", i + 1);
+			return 0;
+		}
+
+		if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lcd_pads[] = {
+	MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/*
+	 * PWM1, pin conflicts with ENET1_RX_DATA0
+	 * Use GPIO for Brightness adjustment, duty cycle = period.
+	 */
+	MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+struct lcd_panel_info_t {
+	unsigned int lcdif_base_addr;
+	int depth;
+	void (*enable)(struct lcd_panel_info_t const *dev);
+	struct fb_videomode mode;
+};
+
+void do_enable_parallel_lcd(struct display_info_t const *dev)
+{
+	enable_lcdif_clock(dev->bus, 1);
+
+	SETUP_IOMUX_PADS(lcd_pads);
+
+	/* Power up the LCD */
+	gpio_request(IMX_GPIO_NR(3, 4), "lcd power");
+	gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
+
+	/* Set Brightness to high */
+	gpio_request(IMX_GPIO_NR(4, 16), "backlight");
+	gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
+}
+
+struct display_info_t const displays[] = {{
+	.bus = MX6UL_LCDIF1_BASE_ADDR,
+	.addr = 0,
+	.pixfmt = 24,
+	.detect = NULL,
+	.enable	= do_enable_parallel_lcd,
+	.mode	= {
+		.name		= "MCIMX28LCD",
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 29850,
+		.left_margin    = 89,
+		.right_margin   = 164,
+		.upper_margin   = 23,
+		.lower_margin   = 10,
+		.hsync_len      = 10,
+		.vsync_len      = 10,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+#endif
+
+#ifdef CONFIG_FEC_MXC
+int board_eth_init(struct bd_info *bis)
+{
+	int ret;
+
+	setup_iomux_fec(CONFIG_FEC_ENET_DEV);
+
+	ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
+		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+	if (ret)
+		printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__);
+
+	return 0;
+}
+
+static int setup_fec(int fec_id)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+	int ret;
+
+	if (1 == fec_id) {
+		if (check_module_fused(MODULE_ENET2))
+			return -1;
+
+		/*
+		 * Use 50M anatop loopback REF_CLK2 for ENET2,
+		 * clear gpr1[14], set gpr1[18]
+		 */
+		clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+				IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+		ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
+		if (ret)
+			return ret;
+
+		SETUP_IOMUX_PADS(fec1_phy_rst);
+		gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset");
+		gpio_direction_output(IMX_GPIO_NR(5, 2), 0);
+		udelay(50);
+		gpio_direction_output(IMX_GPIO_NR(5, 2), 1);
+	} else {
+		if (check_module_fused(MODULE_ENET1))
+			return -1;
+
+		/* clk from phy, set gpr1[13], clear gpr1[17]*/
+		clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+				IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK);
+
+		SETUP_IOMUX_PADS(fec2_phy_rst);
+		gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset");
+		gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+		udelay(50);
+		gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
+	}
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (CONFIG_FEC_ENET_DEV == 1) {
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x202);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+	} else if (CONFIG_FEC_ENET_DEV == 0) {
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x201);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8110);
+	}
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_POWER_LEGACY
+#define I2C_PMIC	0
+static struct pmic *pfuze;
+int power_init_board(void)
+{
+	int ret;
+	u32 rev_id, value;
+
+	ret = power_pfuze100_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	pfuze = pmic_get("PFUZE100");
+	if (!pfuze)
+		return -ENODEV;
+
+	ret = pmic_probe(pfuze);
+	if (ret)
+		return ret;
+
+	ret = pfuze_mode_init(pfuze, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value);
+	pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id);
+	printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id);
+
+	/*
+	 * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP
+	 * Configuration is F0.
+	 * Default VOLT:
+	 * VSNVS_VOLT	|	3.0V
+	 * SW1AB	|	1.375V
+	 * SW2		|	3.3V
+	 * SW3A		|	1.5V
+	 * SW3B		|	1.5V
+	 * VGEN1	|	1.5V
+	 * VGEN2	|	1.5V
+	 * VGEN3	|	2.5V
+	 * VGEN4	|	1.8V
+	 * VGEN5	|	2.8V
+	 * VGEN6	|	3.3V
+	 *
+	 * According to schematic, we need SW3A 1.35V, SW3B 3.3V,
+	 * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V,
+	 * VGEN5 3.3V, VGEN6 3.0V.
+	 *
+	 * Here we just use the default VOLT, but not configure
+	 * them, when needed, configure them to our requested voltage.
+	 */
+
+	/* set SW1AB standby volatage 1.3V */
+	pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value);
+	value &= ~0x3f;
+	value |= PFUZE100_SW1ABC_SETP(13000);
+	pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value);
+
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value);
+	value &= ~0xc0;
+	value |= 0x40;
+	pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value);
+
+	/* Enable power of VGEN5 3V3 */
+	pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &value);
+	value &= ~0x1F;
+	value |= 0x1F;
+	pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, value);
+
+	return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+	unsigned int value;
+	int is_400M;
+	u32 vddarm;
+
+	struct pmic *p = pfuze;
+
+	if (!p) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* switch to ldo_bypass mode */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+		/* decrease VDDARM to 1.275V */
+		pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value);
+		value &= ~0x3f;
+		value |= PFUZE100_SW1ABC_SETP(12750);
+		pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value);
+
+		is_400M = set_anatop_bypass(1);
+		if (is_400M)
+			vddarm = PFUZE100_SW1ABC_SETP(10750);
+		else
+			vddarm = PFUZE100_SW1ABC_SETP(11750);
+
+		pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value);
+		value &= ~0x3f;
+		value |= vddarm;
+		pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value);
+
+		finish_anatop_bypass();
+
+		printf("switch to ldo_bypass mode!\n");
+	}
+}
+#endif
+
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+	unsigned int reg, dev_id, rev_id;
+
+	ret = pmic_get("pfuze100@8", &dev);
+	if (ret == -ENODEV)
+		return ret;
+
+	ret = pfuze_mode_init(dev, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
+	printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+	/*
+	 * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP
+	 * Configuration is F0.
+	 * Default VOLT:
+	 * VSNVS_VOLT	|	3.0V
+	 * SW1AB	|	1.375V
+	 * SW2		|	3.3V
+	 * SW3A		|	1.5V
+	 * SW3B		|	1.5V
+	 * VGEN1	|	1.5V
+	 * VGEN2	|	1.5V
+	 * VGEN3	|	2.5V
+	 * VGEN4	|	1.8V
+	 * VGEN5	|	2.8V
+	 * VGEN6	|	3.3V
+	 *
+	 * According to schematic, we need SW3A 1.35V, SW3B 3.3V,
+	 * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V,
+	 * VGEN5 3.3V, VGEN6 3.0V.
+	 *
+	 * Here we just use the default VOLT, but not configure
+	 * them, when needed, configure them to our requested voltage.
+	 */
+
+	/* Set SW1AB stanby volage to 1.3V */
+	reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
+	reg &= ~SW1x_STBY_MASK;
+	reg |= PFUZE100_SW1ABC_SETP(13000);
+	pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
+
+	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
+	reg &= ~SW1xCONF_DVSSPEED_MASK;
+	reg |= SW1xCONF_DVSSPEED_4US;
+	pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
+
+	/* Enable power of VGEN5 3V3 */
+	reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
+	reg &= ~0x1F;
+	reg |= 0x1F;
+	pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
+
+	return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+	struct udevice *dev;
+	int ret;
+	int is_400M;
+	u32 vddarm;
+
+	ret = pmic_get("pfuze100", &dev);
+	if (ret == -ENODEV) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* switch to ldo_bypass mode */
+	if (ldo_bypass) {
+		/* decrease VDDARM to 1.275V */
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750));
+
+		is_400M = set_anatop_bypass(1);
+		if (is_400M)
+			vddarm = PFUZE100_SW1ABC_SETP(10750);
+		else
+			vddarm = PFUZE100_SW1ABC_SETP(11750);
+
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
+
+		set_anatop_bypass(1);
+
+		printf("switch to ldo_bypass mode!\n");
+	}
+}
+#endif
+
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec(CONFIG_FEC_ENET_DEV);
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#ifndef CONFIG_DM_SPI
+	setup_spinor();
+#endif
+#endif
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+	/*
+	 * This function should be invoked after setup_fec,
+	 * because ENET2_RX_ER conflicts. However, we rarely need
+	 * ENET2_RX_ER for enet, and when use eimnor, we do not
+	 * have sd1/sd2, enet is a must to boot kernel and nfsrootfs.
+	 */
+	setup_eimnor();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return get_cpu_rev();
+}
+
+int checkboard(void)
+{
+	puts("Board: MX6UL 14X14 LPDDR2 Validation\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+iomux_v3_cfg_t const usb_otg1_pads[] = {
+	MX6_PAD_GPIO1_IO04__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+};
+
+/*
+ * Leave it here, but default configuration only supports 1 port now,
+ * because we need sd1 and i2c1
+ */
+iomux_v3_cfg_t const usb_otg2_pads[] = {
+	/* conflict with i2c1_scl */
+	MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* conflict with sd1_vselect */
+	MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+};
+
+int board_usb_phy_mode(int port)
+{
+	return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+
+	switch (port) {
+	case 0:
+		SETUP_IOMUX_PADS(usb_otg1_pads);
+		break;
+	case 1:
+		SETUP_IOMUX_PADS(usb_otg2_pads);
+		break;
+	default:
+		printf("MXC USB port %d not yet supported\n", port);
+		return 1;
+	}
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	/* Set Power polarity */
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
+}
+#endif
+#endif
diff --git a/board/freescale/mx6ul_14x14_lpddr2_val/plugin.S b/board/freescale/mx6ul_14x14_lpddr2_val/plugin.S
new file mode 100644
index 00000000000..6ef2013eece
--- /dev/null
+++ b/board/freescale/mx6ul_14x14_lpddr2_val/plugin.S
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6ul_lpddr2_val_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x00080000
+	str r1, [r0, #0x4B4]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4AC]
+	ldr r1, =0x00000028
+	str r1, [r0, #0x27C]
+	str r1, [r0, #0x250]
+	str r1, [r0, #0x24C]
+	str r1, [r0, #0x490]
+	str r1, [r0, #0x288]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x270]
+	str r1, [r0, #0x260]
+	str r1, [r0, #0x264]
+
+	ldr r1, =0x00000028
+	str r1, [r0, #0x4A0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x494]
+
+	ldr r1, =0x00003028
+	str r1, [r0, #0x280]
+	str r1, [r0, #0x284]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x4B0]
+
+	ldr r1, =0x00000028
+	str r1, [r0, #0x498]
+	str r1, [r0, #0x4A4]
+	str r1, [r0, #0x244]
+	str r1, [r0, #0x248]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1C]
+	ldr r1, =0x1b4700c7
+	str r1, [r0, #0x5C]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00470000
+	str r1, [r0, #0x890]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8b8]
+
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81C]
+	str r1, [r0, #0x820]
+	ldr r1, =0xF3333333
+	str r1, [r0, #0x82C]
+	str r1, [r0, #0x830]
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83C]
+	ldr r1, =0x4040484F
+	str r1, [r0, #0x848]
+	ldr r1, =0x40405247
+	str r1, [r0, #0x850]
+	ldr r1, =0x00922012
+	str r1, [r0, #0x8C0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8b8]
+
+	ldr r1, =0x00020012
+	str r1, [r0, #0x004]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x008]
+	ldr r1, =0x33374133
+	str r1, [r0, #0x00C]
+	ldr r1, =0x00100A82
+	str r1, [r0, #0x010]
+	ldr r1, =0x00170557
+	str r1, [r0, #0x038]
+	ldr r1, =0x00000093
+	str r1, [r0, #0x014]
+	ldr r1, =0x00001748
+	str r1, [r0, #0x018]
+	ldr r1, =0x00008000
+	str r1, [r0, #0x01C]
+	ldr r1, =0x0F9F0682
+	str r1, [r0, #0x02C]
+	ldr r1, =0x009F0010
+	str r1, [r0, #0x030]
+	ldr r1, =0x0000004F
+	str r1, [r0, #0x040]
+	ldr r1, =0x83100000
+	str r1, [r0, #0x000]
+	ldr r1, =0x00008010
+	str r1, [r0, #0x01C]
+	ldr r1, =0x003F8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0xFF0A8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x82018030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04028030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x01038030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00001800
+	str r1, [r0, #0x020]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x818]
+	ldr r1, =0xA1310003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00025576
+	str r1, [r0, #0x004]
+	ldr r1, =0x00010106
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x01C]
+.endm
+
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #0x68]
+	str r1, [r0, #0x6C]
+	str r1, [r0, #0x70]
+	str r1, [r0, #0x74]
+	str r1, [r0, #0x78]
+	str r1, [r0, #0x7C]
+	str r1, [r0, #0x80]
+	str r1, [r0, #0x84]
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+	imx6ul_lpddr2_val_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/board/freescale/mx6ull_ddr3_val/Kconfig b/board/freescale/mx6ull_ddr3_val/Kconfig
new file mode 100644
index 00000000000..26903c37939
--- /dev/null
+++ b/board/freescale/mx6ull_ddr3_val/Kconfig
@@ -0,0 +1,24 @@
+if TARGET_MX6ULL_DDR3_VAL
+
+config SYS_BOARD
+       default "mx6ull_ddr3_val"
+
+config SYS_VENDOR
+       default "freescale"
+
+config SYS_CONFIG_NAME
+       default "mx6ull_ddr3_val"
+
+config MX6ULL_DDR3_VAL_EMMC_REWORK
+	bool "Select this for the board with eMMC rework"
+
+config SYS_TEXT_BASE
+	default 0x87800000
+
+config MX6ULL_DDR3_VAL_TSC_REWORK
+        bool "Select this for the board with screen touch rework"
+
+config MX6ULL_DDR3_VAL_QSPIB_REWORK
+        bool "Select this for the board with flash on QSPI-B port rework"
+
+endif
diff --git a/board/freescale/mx6ull_ddr3_val/Makefile b/board/freescale/mx6ull_ddr3_val/Makefile
new file mode 100644
index 00000000000..f7d79a77039
--- /dev/null
+++ b/board/freescale/mx6ull_ddr3_val/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx6ull_ddr3_val.o
diff --git a/board/freescale/mx6ull_ddr3_val/imximage.cfg b/board/freescale/mx6ull_ddr3_val/imximage.cfg
new file mode 100644
index 00000000000..eded67fa85d
--- /dev/null
+++ b/board/freescale/mx6ull_ddr3_val/imximage.cfg
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_QSPI_BOOT
+BOOT_FROM	qspi
+#elif defined(CONFIG_NOR_BOOT)
+BOOT_FROM	nor
+#else
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6ull_ddr3_val/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+DATA 4 0x020E04B4 0x000C0000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000030
+DATA 4 0x020E0250 0x00000030
+DATA 4 0x020E024C 0x00000030
+DATA 4 0x020E0490 0x00000030
+DATA 4 0x020E0288 0x000C0030
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000030
+DATA 4 0x020E0264 0x00000030
+DATA 4 0x020E04A0 0x00000030
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00000030
+DATA 4 0x020E0284 0x00000030
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000030
+DATA 4 0x020E04A4 0x00000030
+DATA 4 0x020E0244 0x00000030
+DATA 4 0x020E0248 0x00000030
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B080C 0x00150019
+DATA 4 0x021B083C 0x41550153
+DATA 4 0x021B0848 0x40403A3E
+DATA 4 0x021B0850 0x40402F2A
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B08C0 0x00944009
+DATA 4 0x021B08b8 0x00000800
+DATA 4 0x021B0004 0x0002002D
+DATA 4 0x021B0008 0x1B333030
+DATA 4 0x021B000C 0x676B52F3
+DATA 4 0x021B0010 0xB66D0B63
+DATA 4 0x021B0014 0x01FF00DB
+DATA 4 0x021B0018 0x00211740
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B002C 0x000026D2
+DATA 4 0x021B0030 0x006B1023
+DATA 4 0x021B0040 0x0000005F
+DATA 4 0x021B0000 0x85180000
+DATA 4 0x021B0890 0x00400000
+DATA 4 0x021B001C 0x02008032
+DATA 4 0x021B001C 0x00008033
+DATA 4 0x021B001C 0x00048031
+DATA 4 0x021B001C 0x15208030
+DATA 4 0x021B001C 0x04008040
+DATA 4 0x021B0020 0x00000800
+DATA 4 0x021B0818 0x00000227
+DATA 4 0x021B0004 0x0002552D
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+#endif
diff --git a/board/freescale/mx6ull_ddr3_val/mx6ull_ddr3_val.c b/board/freescale/mx6ull_ddr3_val/mx6ull_ddr3_val.c
new file mode 100644
index 00000000000..a17fad2407f
--- /dev/null
+++ b/board/freescale/mx6ull_ddr3_val/mx6ull_ddr3_val.c
@@ -0,0 +1,1168 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc_imx.h>
+#include <i2c.h>
+#include <linux/sizes.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <mxsfb.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "../common/pfuze.h"
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#if defined(CONFIG_MXC_EPDC)
+#include <lcd.h>
+#include <mxc_epdc_fb.h>
+#endif
+#include <asm/mach-imx/video.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_SPEED_HIGH   |                                   \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL  (PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_120ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
+	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE)
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+			PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+		PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+		PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
+	PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define EPDC_PAD_CTRL	0x010b1
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC and EEPROM */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		/* conflict with usb_otg2_pwr */
+		.i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC,
+		.gp = IMX_GPIO_NR(1, 2),
+	},
+	.sda = {
+		/* conflict with usb_otg2_oc */
+		.i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC,
+		.gp = IMX_GPIO_NR(1, 3),
+	},
+};
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#ifdef CONFIG_MX6ULL_DDR3_VAL_EMMC_REWORK
+static iomux_v3_cfg_t const usdhc1_emmc_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/*
+	 * The following 4 pins conflicts with qspi and nand flash.
+	 * You can comment out the following 4 pins and change
+	 * {USDHC1_BASE_ADDR, 0, 8}  -> {USDHC1_BASE_ADDR, 0, 4}
+	 * to make emmc and qspi coexists.
+	 */
+	MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/* Default NO WP for emmc, since we use pull down */
+	MX6_PAD_UART1_CTS_B__USDHC1_WP  | MUX_PAD_CTRL(USDHC_PAD_CTRL_WP),
+	/* RST_B */
+	MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#else
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_UART1_CTS_B__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/* VSELECT */
+	MX6_PAD_GPIO1_IO05__GPIO1_IO05 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/* CD */
+	MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* RST_B */
+	MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#endif
+
+#if !defined(CONFIG_NAND_MXS) && !defined(CONFIG_MX6ULL_DDR3_VAL_QSPIB_REWORK)
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	/* usdhc2_clk, nand_re_b, qspi1b_clk */
+	MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/* usdhc2_cmd, nand_we_b, qspi1b_cs0_b */
+	MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/* usdhc2_data0, nand_data0, qspi1b_cs1_b */
+	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/* usdhc2_data1, nand_data1 */
+	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/* usdhc2_data2, nand_data2, qspi1b_dat0 */
+	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/* usdhc2_data3, nand_data3, qspi1b_dat1 */
+	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/*
+	 * VSELECT
+	 * Conflicts with WDOG1, so default disabled.
+	 * MX6_PAD_GPIO1_IO08__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	 */
+	/*
+	 * CD
+	 * Share with sdhc1
+	 * MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	 */
+	/*
+	 * RST_B
+	 * Pin conflicts with NAND ALE, if want to test nand,
+	 * Connect R169(B), disconnect R169(A).
+	 */
+	MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+#endif
+
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const nand_pads[] = {
+	MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_CSI_MCLK__RAWNAND_CE2_B   | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+};
+
+static void setup_gpmi_nand(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* config gpmi nand iomux */
+	SETUP_IOMUX_PADS(nand_pads);
+
+	setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#ifndef CONFIG_DM_SPI
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+	MX6_PAD_CSI_DATA06__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_CSI_DATA04__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_CSI_DATA07__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+
+	/* CS Pin */
+	MX6_PAD_CSI_DATA05__GPIO4_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_spinor(void)
+{
+	SETUP_IOMUX_PADS(ecspi1_pads);
+	gpio_request(IMX_GPIO_NR(4, 26), "escpi cs");
+	gpio_direction_output(IMX_GPIO_NR(4, 26), 0);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 26)) : -1;
+}
+#endif
+#endif
+
+#ifdef CONFIG_FEC_MXC
+/*
+ * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
+ * be used for ENET1 or ENET2, cannot be used for both.
+ */
+static iomux_v3_cfg_t const fec1_pads[] = {
+	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+	/* Pin conflicts with LCD PWM1 */
+	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec1_phy_rst[] = {
+	/*
+	 * ALT5 mode is only valid when TAMPER pin is used for GPIO.
+	 * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0].
+	 *
+	 * ENET1_RST
+	 */
+	MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec2_pads[] = {
+	MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART3_TX_DATA__ENET2_RDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART3_RX_DATA__ENET2_RDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART3_CTS_B__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART4_TX_DATA__ENET2_TDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART4_RX_DATA__ENET2_TDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	MX6_PAD_UART5_RX_DATA__ENET2_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_UART5_TX_DATA__ENET2_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec2_phy_rst[] = {
+	/*
+	 * ENET2_RST
+	 *
+	 * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0]
+	 */
+	MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_fec(int fec_id)
+{
+	if (fec_id == 0) {
+		SETUP_IOMUX_PADS(fec1_pads);
+	} else {
+		SETUP_IOMUX_PADS(fec2_pads);
+	}
+}
+#endif
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+}
+
+#ifdef CONFIG_FSL_QSPI
+
+#ifndef CONFIG_DM_SPI
+#define QSPI_PAD_CTRL1	\
+	(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
+	 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+	MX6_PAD_NAND_WP_B__QSPI_A_SCLK	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_READY_B__QSPI_A_DATA00	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CE0_B__QSPI_A_DATA01	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CE1_B__QSPI_A_DATA02	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CLE__QSPI_A_DATA03	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DQS__QSPI_A_SS0_B	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA07__QSPI_A_SS1_B	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+
+#ifdef CONFIG_MX6ULL_DDR3_VAL_QSPIB_REWORK
+	MX6_PAD_NAND_RE_B__QSPI_B_SCLK	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_WE_B__QSPI_B_SS0_B	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA00__QSPI_B_SS1_B	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA02__QSPI_B_DATA00	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA03__QSPI_B_DATA01	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA04__QSPI_B_DATA02	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DATA05__QSPI_B_DATA03	| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+#endif
+};
+#endif
+
+int board_qspi_init(void)
+{
+#ifndef CONFIG_DM_SPI
+	/* Set the iomux */
+	SETUP_IOMUX_PADS(quadspi_pads);
+#endif
+	/* Set the clock */
+	enable_qspi_clk(0);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+#ifdef CONFIG_MX6ULL_DDR3_VAL_EMMC_REWORK
+	/* If want to use qspi, should change to 4 bit width */
+	{USDHC1_BASE_ADDR, 0, 8},
+#else
+	{USDHC1_BASE_ADDR, 0, 4},
+#endif
+#if !defined(CONFIG_NAND_MXS) && !defined(CONFIG_MX6ULL_DDR3_VAL_QSPIB_REWORK)
+	{USDHC2_BASE_ADDR, 0, 4},
+#endif
+};
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 19)
+#define USDHC1_PWR_GPIO	IMX_GPIO_NR(1, 9)
+#define USDHC1_VSELECT IMX_GPIO_NR(1, 5)
+#define USDHC2_PWR_GPIO	IMX_GPIO_NR(4, 10)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+#ifdef CONFIG_MX6ULL_DDR3_VAL_EMMC_REWORK
+		ret = 1;
+#else
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+#endif
+		break;
+#if !defined(CONFIG_NAND_MXS) && !defined(CONFIG_MX6ULL_DDR3_VAL_QSPIB_REWORK)
+	case USDHC2_BASE_ADDR:
+		ret = 1;
+		break;
+#endif
+	}
+
+	return ret;
+}
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+#ifdef CONFIG_MX6ULL_DDR3_VAL_EMMC_REWORK
+			SETUP_IOMUX_PADS(usdhc1_emmc_pads);
+#else
+			SETUP_IOMUX_PADS(usdhc1_pads);
+			gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
+			gpio_direction_input(USDHC1_CD_GPIO);
+#endif
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			/* 3.3V */
+			gpio_request(USDHC1_VSELECT, "usdhc1 vsel");
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1 pwr");
+			gpio_direction_output(USDHC1_VSELECT, 0);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+#if !defined(CONFIG_NAND_MXS) && !defined(CONFIG_MX6ULL_DDR3_VAL_QSPIB_REWORK)
+		case 1:
+			SETUP_IOMUX_PADS(usdhc2_pads);
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr");
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			break;
+#endif
+		default:
+			printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
+			return 0;
+			}
+
+			if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
+				printf("Warning: failed to initialize mmc dev %d\n", i);
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lcd_pads[] = {
+	MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+	/*
+	 * PWM1, pin conflicts with ENET1_RX_DATA0
+	 * Use GPIO for Brightness adjustment, duty cycle = period.
+	 */
+	/* MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),*/
+};
+
+struct lcd_panel_info_t {
+	unsigned int lcdif_base_addr;
+	int depth;
+	void (*enable)(struct lcd_panel_info_t const *dev);
+	struct fb_videomode mode;
+};
+
+void do_enable_parallel_lcd(struct display_info_t const *dev)
+{
+	enable_lcdif_clock(dev->bus, 1);
+
+	SETUP_IOMUX_PADS(lcd_pads);
+
+	/* Power up the LCD */
+	gpio_request(IMX_GPIO_NR(3, 4), "lcd power");
+	gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
+
+	/* Set Brightness to high */
+	/* gpio_direction_output(IMX_GPIO_NR(2, 0) , 1); */
+}
+
+struct display_info_t const displays[] = {{
+	.bus = MX6ULL_LCDIF1_BASE_ADDR,
+	.addr = 0,
+	.pixfmt = 24,
+	.detect = NULL,
+	.enable	= do_enable_parallel_lcd,
+	.mode	= {
+		.name		= "MCIMX28LCD",
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 29850,
+		.left_margin    = 89,
+		.right_margin   = 164,
+		.upper_margin   = 23,
+		.lower_margin   = 10,
+		.hsync_len      = 10,
+		.vsync_len      = 10,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+#endif
+
+#ifdef CONFIG_MXC_EPDC
+static iomux_v3_cfg_t const epdc_enable_pads[] = {
+	MX6_PAD_ENET2_RX_DATA0__EPDC_SDDO08	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_ENET2_RX_DATA1__EPDC_SDDO09	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_ENET2_RX_EN__EPDC_SDDO10	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_ENET2_TX_DATA0__EPDC_SDDO11	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_ENET2_TX_DATA1__EPDC_SDDO12	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_ENET2_TX_EN__EPDC_SDDO13	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_ENET2_TX_CLK__EPDC_SDDO14	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_ENET2_RX_ER__EPDC_SDDO15	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_CLK__EPDC_SDCLK		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_ENABLE__EPDC_SDLE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_HSYNC__EPDC_SDOE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_VSYNC__EPDC_SDCE0		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA00__EPDC_SDDO00	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA01__EPDC_SDDO01	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA02__EPDC_SDDO02	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA03__EPDC_SDDO03	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA04__EPDC_SDDO04	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA05__EPDC_SDDO05	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA06__EPDC_SDDO06	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA07__EPDC_SDDO07	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA14__EPDC_SDSHR	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA15__EPDC_GDRL		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA16__EPDC_GDCLK	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_DATA17__EPDC_GDSP		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX6_PAD_LCD_RESET__EPDC_GDOE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const epdc_disable_pads[] = {
+	MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08,
+	MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09,
+	MX6_PAD_ENET2_RX_EN__GPIO2_IO10,
+	MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11,
+	MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12,
+	MX6_PAD_ENET2_TX_EN__GPIO2_IO13,
+	MX6_PAD_ENET2_TX_CLK__GPIO2_IO14,
+	MX6_PAD_ENET2_RX_ER__GPIO2_IO15,
+	MX6_PAD_LCD_CLK__GPIO3_IO00,
+	MX6_PAD_LCD_ENABLE__GPIO3_IO01,
+	MX6_PAD_LCD_HSYNC__GPIO3_IO02,
+	MX6_PAD_LCD_VSYNC__GPIO3_IO03,
+	MX6_PAD_LCD_DATA00__GPIO3_IO05,
+	MX6_PAD_LCD_DATA01__GPIO3_IO06,
+	MX6_PAD_LCD_DATA02__GPIO3_IO07,
+	MX6_PAD_LCD_DATA03__GPIO3_IO08,
+	MX6_PAD_LCD_DATA04__GPIO3_IO09,
+	MX6_PAD_LCD_DATA05__GPIO3_IO10,
+	MX6_PAD_LCD_DATA06__GPIO3_IO11,
+	MX6_PAD_LCD_DATA07__GPIO3_IO12,
+	MX6_PAD_LCD_DATA14__GPIO3_IO19,
+	MX6_PAD_LCD_DATA15__GPIO3_IO20,
+	MX6_PAD_LCD_DATA16__GPIO3_IO21,
+	MX6_PAD_LCD_DATA17__GPIO3_IO22,
+	MX6_PAD_LCD_RESET__GPIO3_IO04,
+};
+
+vidinfo_t panel_info = {
+	.vl_refresh = 85,
+	.vl_col = 1024,
+	.vl_row = 758,
+	.vl_pixclock = 40000000,
+	.vl_left_margin = 12,
+	.vl_right_margin = 76,
+	.vl_upper_margin = 4,
+	.vl_lower_margin = 5,
+	.vl_hsync = 12,
+	.vl_vsync = 2,
+	.vl_sync = 0,
+	.vl_mode = 0,
+	.vl_flag = 0,
+	.vl_bpix = 3,
+	.cmap = 0,
+};
+
+struct epdc_timing_params panel_timings = {
+	.vscan_holdoff = 4,
+	.sdoed_width = 10,
+	.sdoed_delay = 20,
+	.sdoez_width = 10,
+	.sdoez_delay = 20,
+	.gdclk_hp_offs = 524,
+	.gdsp_offs = 327,
+	.gdoe_offs = 0,
+	.gdclk_offs = 19,
+	.num_ce = 1,
+};
+
+static iomux_v3_cfg_t const epdc_pwr_ctrl_pads[] = {
+	IOMUX_PADS(PAD_LCD_DATA11__GPIO3_IO16	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_LCD_DATA19__GPIO3_IO24	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_LCD_DATA09__GPIO3_IO14	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_LCD_DATA12__GPIO3_IO17	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+};
+
+static void setup_epdc_power(void)
+{
+	SETUP_IOMUX_PADS(epdc_pwr_ctrl_pads);
+
+	/* Setup epdc voltage */
+
+	/* EPDC_PWRSTAT - GPIO3[16] for PWR_GOOD status */
+	gpio_request(IMX_GPIO_NR(3, 16), "EPDC_PWRSTAT");
+	gpio_direction_input(IMX_GPIO_NR(3, 16));
+
+	/* EPDC_VCOM0 - GPIO3[24] for VCOM control */
+	/* Set as output */
+	gpio_request(IMX_GPIO_NR(3, 24), "EPDC_VCOM0");
+	gpio_direction_output(IMX_GPIO_NR(3, 24), 1);
+
+	/* EPDC_PWRWAKEUP - GPIO3[14] for EPD PMIC WAKEUP */
+	/* Set as output */
+	gpio_request(IMX_GPIO_NR(3, 14), "EPDC_PWRWAKEUP");
+	gpio_direction_output(IMX_GPIO_NR(3, 14), 1);
+
+	/* EPDC_PWRCTRL0 - GPIO3[17] for EPD PWR CTL0 */
+	/* Set as output */
+	gpio_request(IMX_GPIO_NR(3, 17), "EPDC_PWRCTRL0");
+	gpio_direction_output(IMX_GPIO_NR(3, 17), 1);
+}
+
+static void epdc_enable_pins(void)
+{
+	/* epdc iomux settings */
+	SETUP_IOMUX_PADS(epdc_enable_pads);
+}
+
+static void epdc_disable_pins(void)
+{
+	/* Configure MUX settings for EPDC pins to GPIO  and drive to 0 */
+	SETUP_IOMUX_PADS(epdc_disable_pads);
+}
+
+static void setup_epdc(void)
+{
+	/* Set pixel clock rates for EPDC in clock.c */
+
+	panel_info.epdc_data.wv_modes.mode_init = 0;
+	panel_info.epdc_data.wv_modes.mode_du = 1;
+	panel_info.epdc_data.wv_modes.mode_gc4 = 3;
+	panel_info.epdc_data.wv_modes.mode_gc8 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc16 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc32 = 2;
+
+	panel_info.epdc_data.epdc_timings = panel_timings;
+
+	setup_epdc_power();
+}
+
+void epdc_power_on(void)
+{
+	unsigned int reg;
+	struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO3_BASE_ADDR;
+
+	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
+	gpio_set_value(IMX_GPIO_NR(3, 17), 1);
+	udelay(1000);
+
+	/* Enable epdc signal pin */
+	epdc_enable_pins();
+
+	/* Set PMIC Wakeup to high - enable Display power */
+	gpio_set_value(IMX_GPIO_NR(3, 14), 1);
+
+	/* Wait for PWRGOOD == 1 */
+	while (1) {
+		reg = readl(&gpio_regs->gpio_psr);
+		if (!(reg & (1 << 16)))
+			break;
+
+		udelay(100);
+	}
+
+	/* Enable VCOM */
+	gpio_set_value(IMX_GPIO_NR(3, 24), 1);
+
+	udelay(500);
+}
+
+void epdc_power_off(void)
+{
+	/* Set PMIC Wakeup to low - disable Display power */
+	gpio_set_value(IMX_GPIO_NR(3, 14), 0);
+
+	/* Disable VCOM */
+	gpio_set_value(IMX_GPIO_NR(3, 24), 0);
+
+	epdc_disable_pins();
+
+	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
+	gpio_set_value(IMX_GPIO_NR(3, 17), 0);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+int board_eth_init(struct bd_info *bis)
+{
+	int ret;
+
+	setup_iomux_fec(CONFIG_FEC_ENET_DEV);
+
+	ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
+		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+	if (ret)
+		printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__);
+
+	return 0;
+}
+
+static int setup_fec(int fec_id)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+	int ret;
+
+	if (0 == fec_id) {
+		if (check_module_fused(MODULE_ENET1))
+			return -1;
+		/*
+		 * Use 50M anatop loopback REF_CLK1 for ENET1,
+		 * clear gpr1[13], set gpr1[17]
+		 */
+		clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+		ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
+		if (ret)
+			return ret;
+
+		SETUP_IOMUX_PADS(fec1_phy_rst);
+		gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset");
+		gpio_direction_output(IMX_GPIO_NR(5, 2), 0);
+		udelay(50);
+		gpio_direction_output(IMX_GPIO_NR(5, 2), 1);
+
+	} else {
+		if (check_module_fused(MODULE_ENET2))
+			return -1;
+
+		/* clk from phy, set gpr1[14], clear gpr1[18]*/
+		clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+				IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK);
+
+		SETUP_IOMUX_PADS(fec2_phy_rst);
+		gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset");
+		gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+		udelay(50);
+		gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
+	}
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	if (CONFIG_FEC_ENET_DEV == 0) {
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x202);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+	} else if (CONFIG_FEC_ENET_DEV == 1) {
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x201);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8110);
+	}
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_POWER_LEGACY
+#define I2C_PMIC	0
+static struct pmic *pfuze;
+int power_init_board(void)
+{
+	int ret;
+	u32 rev_id, value;
+
+	ret = power_pfuze100_init(I2C_PMIC);
+	if (ret)
+		return ret;
+
+	pfuze = pmic_get("PFUZE100");
+	if (!pfuze)
+		return -ENODEV;
+
+	ret = pmic_probe(pfuze);
+	if (ret)
+		return ret;
+
+	ret = pfuze_mode_init(pfuze, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value);
+	pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id);
+	printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id);
+
+	/*
+	 * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP
+	 * Configuration is F0.
+	 * Default VOLT:
+	 * VSNVS_VOLT	|	3.0V
+	 * SW1AB	|	1.375V
+	 * SW2		|	3.3V
+	 * SW3A		|	1.5V
+	 * SW3B		|	1.5V
+	 * VGEN1	|	1.5V
+	 * VGEN2	|	1.5V
+	 * VGEN3	|	2.5V
+	 * VGEN4	|	1.8V
+	 * VGEN5	|	2.8V
+	 * VGEN6	|	3.3V
+	 *
+	 * According to schematic, we need SW3A 1.35V, SW3B 3.3V,
+	 * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V,
+	 * VGEN5 3.3V, VGEN6 3.0V.
+	 *
+	 * Here we just use the default VOLT, but not configure
+	 * them, when needed, configure them to our requested voltage.
+	 */
+
+	/* set SW1AB standby volatage 0.975V */
+	pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value);
+	value &= ~0x3f;
+	value |= PFUZE100_SW1ABC_SETP(9750);
+	pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value);
+
+	/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value);
+	value &= ~0xc0;
+	value |= 0x40;
+	pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value);
+
+	/* Enable power of VGEN5 3V3 */
+	pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &value);
+	value &= ~0x1F;
+	value |= 0x1F;
+	pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, value);
+
+	return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+	unsigned int value;
+	int is_400M;
+	u32 vddarm;
+
+	struct pmic *p = pfuze;
+
+	if (!p) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* switch to ldo_bypass mode */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+		/* decrease VDDARM to 1.275V */
+		pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value);
+		value &= ~0x3f;
+		value |= PFUZE100_SW1ABC_SETP(12750);
+		pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value);
+
+		is_400M = set_anatop_bypass(1);
+		if (is_400M)
+			vddarm = PFUZE100_SW1ABC_SETP(10750);
+		else
+			vddarm = PFUZE100_SW1ABC_SETP(11750);
+
+		pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value);
+		value &= ~0x3f;
+		value |= vddarm;
+		pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value);
+
+		finish_anatop_bypass();
+
+		printf("switch to ldo_bypass mode!\n");
+	}
+}
+#endif
+
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret;
+	unsigned int reg, dev_id, rev_id;
+
+	ret = pmic_get("pfuze100@8", &dev);
+	if (ret == -ENODEV)
+		return ret;
+
+	ret = pfuze_mode_init(dev, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
+	printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+	/*
+	 * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP
+	 * Configuration is F0.
+	 * Default VOLT:
+	 * VSNVS_VOLT	|	3.0V
+	 * SW1AB	|	1.375V
+	 * SW2		|	3.3V
+	 * SW3A		|	1.5V
+	 * SW3B		|	1.5V
+	 * VGEN1	|	1.5V
+	 * VGEN2	|	1.5V
+	 * VGEN3	|	2.5V
+	 * VGEN4	|	1.8V
+	 * VGEN5	|	2.8V
+	 * VGEN6	|	3.3V
+	 *
+	 * According to schematic, we need SW3A 1.35V, SW3B 3.3V,
+	 * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V,
+	 * VGEN5 3.3V, VGEN6 3.0V.
+	 *
+	 * Here we just use the default VOLT, but not configure
+	 * them, when needed, configure them to our requested voltage.
+	 */
+
+	/* Set SW1AB stanby volage to 0.975V */
+	reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
+	reg &= ~SW1x_STBY_MASK;
+	reg |= SW1x_0_975V;
+	pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
+
+	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
+	reg &= ~SW1xCONF_DVSSPEED_MASK;
+	reg |= SW1xCONF_DVSSPEED_4US;
+	pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
+
+	/* Enable power of VGEN5 3V3 */
+	reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
+	reg &= ~0x1F;
+	reg |= 0x1F;
+	pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
+
+	return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+	struct udevice *dev;
+	int ret;
+	int is_400M;
+	u32 vddarm;
+
+	ret = pmic_get("pfuze100", &dev);
+	if (ret == -ENODEV) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* switch to ldo_bypass mode */
+	if (ldo_bypass) {
+		/* decrease VDDARM to 1.275V */
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750));
+
+		is_400M = set_anatop_bypass(1);
+		if (is_400M)
+			vddarm = PFUZE100_SW1ABC_SETP(10750);
+		else
+			vddarm = PFUZE100_SW1ABC_SETP(11750);
+
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
+
+		set_anatop_bypass(1);
+
+		printf("switch to ldo_bypass mode!\n");
+	}
+}
+#endif
+
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec(CONFIG_FEC_ENET_DEV);
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#ifndef CONFIG_DM_SPI
+	setup_spinor();
+#endif
+#endif
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+#ifdef	CONFIG_MXC_EPDC
+	enable_epdc_clock();
+	setup_epdc();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
+	{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return get_cpu_rev();
+}
+
+int checkboard(void)
+{
+	puts("Board: MX6ULL 14X14 DDR3 Validation\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+#ifndef CONFIG_DM_USB
+
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+iomux_v3_cfg_t const usb_otg1_pads[] = {
+	MX6_PAD_GPIO1_IO04__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+};
+
+/*
+ * Leave it here, but default configuration only supports 1 port now,
+ * because we need sd1 and i2c1
+ */
+iomux_v3_cfg_t const usb_otg2_pads[] = {
+	/* conflict with i2c1_scl */
+	MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* conflict with sd1_vselect */
+	MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
+};
+
+int board_usb_phy_mode(int port)
+{
+	return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+
+	switch (port) {
+	case 0:
+		SETUP_IOMUX_PADS(usb_otg1_pads);
+		break;
+	case 1:
+		SETUP_IOMUX_PADS(usb_otg2_pads);
+		break;
+	default:
+		printf("MXC USB port %d not yet supported\n", port);
+		return 1;
+	}
+
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+				 port * 4);
+
+	/* Set Power polarity */
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+	return 0;
+}
+#endif
+#endif
diff --git a/board/freescale/mx6ull_ddr3_val/plugin.S b/board/freescale/mx6ull_ddr3_val/plugin.S
new file mode 100644
index 00000000000..0538d1d5713
--- /dev/null
+++ b/board/freescale/mx6ull_ddr3_val/plugin.S
@@ -0,0 +1,137 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6ull_ddr3_val_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000C0000
+	str r1, [r0, #0x4B4]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4AC]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x27C]
+	str r1, [r0, #0x250]
+	str r1, [r0, #0x24C]
+	str r1, [r0, #0x490]
+	ldr r1, =0x000C0030
+	str r1, [r0, #0x288]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x270]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x260]
+	str r1, [r0, #0x264]
+	str r1, [r0, #0x4A0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x494]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x280]
+	str r1, [r0, #0x284]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x4B0]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x498]
+	str r1, [r0, #0x4A4]
+	str r1, [r0, #0x244]
+	str r1, [r0, #0x248]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1C]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00150019
+	str r1, [r0, #0x80C]
+	ldr r1, =0x41550153
+	str r1, [r0, #0x83C]
+	ldr r1, =0x40403A3E
+	str r1, [r0, #0x848]
+	ldr r1, =0x40402F2A
+	str r1, [r0, #0x850]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81C]
+	str r1, [r0, #0x820]
+	ldr r1, =0xF3333333
+	str r1, [r0, #0x82C]
+	str r1, [r0, #0x830]
+	ldr r1, =0x00944009
+	str r1, [r0, #0x8C0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8B8]
+	ldr r1, =0x0002002D
+	str r1, [r0, #0x004]
+	ldr r1, =0x1B333030
+	str r1, [r0, #0x008]
+	ldr r1, =0x676B52F3
+	str r1, [r0, #0x00C]
+	ldr r1, =0xB66D0B63
+	str r1, [r0, #0x010]
+	ldr r1, =0x01FF00DB
+	str r1, [r0, #0x014]
+	ldr r1, =0x00211740
+	str r1, [r0, #0x018]
+	ldr r1, =0x00008000
+	str r1, [r0, #0x01C]
+	ldr r1, =0x000026D2
+	str r1, [r0, #0x02C]
+	ldr r1, =0x006B1023
+	str r1, [r0, #0x030]
+	ldr r1, =0x0000005F
+	str r1, [r0, #0x040]
+	ldr r1, =0x85180000
+	str r1, [r0, #0x000]
+	ldr r1, =0x00400000
+	str r1, [r0, #0x890]
+	ldr r1, =0x02008032
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00008033
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00048031
+	str r1, [r0, #0x01C]
+	ldr r1, =0x15208030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04008040
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x020]
+	ldr r1, =0x00000227
+	str r1, [r0, #0x818]
+	ldr r1, =0x0002552D
+	str r1, [r0, #0x004]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x01C]
+.endm
+
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0xFFFFFFFF
+	str r1, [r0, #0x68]
+	str r1, [r0, #0x6C]
+	str r1, [r0, #0x70]
+	str r1, [r0, #0x74]
+	str r1, [r0, #0x78]
+	str r1, [r0, #0x7C]
+	str r1, [r0, #0x80]
+.endm
+
+.macro imx6_qos_setting
+.endm
+
+.macro imx6_ddr_setting
+	imx6ull_ddr3_val_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
diff --git a/board/freescale/mx6ullevk/Kconfig b/board/freescale/mx6ullevk/Kconfig
index 49aa302553e..0372eea05ef 100644
--- a/board/freescale/mx6ullevk/Kconfig
+++ b/board/freescale/mx6ullevk/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_MX6ULL_14X14_EVK
+if TARGET_MX6ULL_14X14_EVK || TARGET_MX6ULL_9X9_EVK
 
 config SYS_BOARD
 	default "mx6ullevk"
@@ -12,4 +12,6 @@ config SYS_CONFIG_NAME
 config IMX_CONFIG
 	default "board/freescale/mx6ullevk/imximage.cfg"
 
+config SYS_TEXT_BASE
+	default 0x87800000
 endif
diff --git a/board/freescale/mx6ullevk/imximage.cfg b/board/freescale/mx6ullevk/imximage.cfg
index 0c6f444a7a3..6e8a9187dcf 100644
--- a/board/freescale/mx6ullevk/imximage.cfg
+++ b/board/freescale/mx6ullevk/imximage.cfg
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  *
  * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
  * and create imximage boot image
@@ -57,6 +58,11 @@ DATA 4 0x020c4078 0xffffffff
 DATA 4 0x020c407c 0xffffffff
 DATA 4 0x020c4080 0xffffffff
 
+#ifdef CONFIG_IMX_OPTEE
+DATA 4 0x20e4024 0x00000001
+CHECK_BITS_SET 4 0x20e4024 0x1
+#endif
+
 DATA 4 0x020E04B4 0x000C0000
 DATA 4 0x020E04AC 0x00000000
 DATA 4 0x020E027C 0x00000030
diff --git a/board/freescale/mx6ullevk/imximage_lpddr2.cfg b/board/freescale/mx6ullevk/imximage_lpddr2.cfg
new file mode 100644
index 00000000000..23d770eb564
--- /dev/null
+++ b/board/freescale/mx6ullevk/imximage_lpddr2.cfg
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_QSPI_BOOT
+BOOT_FROM	qspi
+#elif defined(CONFIG_NOR_BOOT)
+BOOT_FROM	nor
+#else
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6ullevk/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+
+#ifdef CONFIG_IMX_OPTEE
+DATA 4 0x20e4024 0x00000001
+CHECK_BITS_SET 4 0x20e4024 0x1
+#endif
+
+DATA 4 0x020E04B4 0x00080000
+DATA 4 0x020E04AC 0x00000000
+DATA 4 0x020E027C 0x00000030
+DATA 4 0x020E0250 0x00000030
+DATA 4 0x020E024C 0x00000030
+DATA 4 0x020E0490 0x00000030
+DATA 4 0x020E0288 0x00000030
+DATA 4 0x020E0270 0x00000000
+DATA 4 0x020E0260 0x00000000
+DATA 4 0x020E0264 0x00000000
+DATA 4 0x020E04A0 0x00000030
+DATA 4 0x020E0494 0x00020000
+DATA 4 0x020E0280 0x00003030
+DATA 4 0x020E0284 0x00003030
+DATA 4 0x020E04B0 0x00020000
+DATA 4 0x020E0498 0x00000030
+DATA 4 0x020E04A4 0x00000030
+DATA 4 0x020E0244 0x00000030
+DATA 4 0x020E0248 0x00000030
+
+DATA 4 0x021B001C 0x00008000
+DATA 4 0x021B085C 0x1b4700c7
+DATA 4 0x021B0800 0xA1390003
+DATA 4 0x021B0890 0x23400A38
+DATA 4 0x021B08b8 0x00000800
+
+DATA 4 0x021B081C 0x33333333
+DATA 4 0x021B0820 0x33333333
+DATA 4 0x021B082C 0xf3333333
+DATA 4 0x021B0830 0xf3333333
+DATA 4 0x021B083C 0x20000000
+DATA 4 0x021B0848 0x40403439
+DATA 4 0x021B0850 0x4040342D
+DATA 4 0x021B08C0 0x00921012
+DATA 4 0x021B08b8 0x00000800
+
+DATA 4 0x021B0004 0x00020052
+DATA 4 0x021B0008 0x00000000
+DATA 4 0x021B000C 0x33374133
+DATA 4 0x021B0010 0x00100A82
+DATA 4 0x021B0038 0x00170557
+DATA 4 0x021B0014 0x00000093
+DATA 4 0x021B0018 0x00201748
+DATA 4 0x021B002C 0x0F9F26D2
+DATA 4 0x021B0030 0x009F0010
+DATA 4 0x021B0040 0x00000047
+DATA 4 0x021B0000 0x83100000
+DATA 4 0x021B001C 0x00008010
+DATA 4 0x021B001C 0x003F8030
+DATA 4 0x021B001C 0xFF0A8030
+DATA 4 0x021B001C 0x82018030
+DATA 4 0x021B001C 0x04028030
+DATA 4 0x021B001C 0x01038030
+DATA 4 0x021B0020 0x00001800
+DATA 4 0x021B0818 0x00000000
+DATA 4 0x021B0800 0xA1310003
+DATA 4 0x021B0004 0x00025552
+DATA 4 0x021B0404 0x00011006
+DATA 4 0x021B001C 0x00000000
+#endif
diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c
index 86c11c7bd3a..72e4898ae86 100644
--- a/board/freescale/mx6ullevk/mx6ullevk.c
+++ b/board/freescale/mx6ullevk/mx6ullevk.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  */
 
 #include <init.h>
@@ -14,13 +15,20 @@
 #include <asm/gpio.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
 #include <asm/io.h>
 #include <common.h>
 #include <env.h>
 #include <fsl_esdhc_imx.h>
+#include <i2c.h>
+#include <miiphy.h>
 #include <linux/sizes.h>
+#include <linux/delay.h>
 #include <mmc.h>
 #include <miiphy.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../common/pfuze.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -28,6 +36,93 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
+#define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE)
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
+	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+			PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+
+#ifdef CONFIG_DM_PMIC
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret, dev_id, rev_id;
+	unsigned int reg;
+
+	ret = pmic_get("pfuze3000@8", &dev);
+	if (ret == -ENODEV)
+		return 0;
+	if (ret != 0)
+		return ret;
+
+	dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
+	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+	/* disable Low Power Mode during standby mode */
+	reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
+	reg |= 0x1;
+	pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
+
+	/* SW1B step ramp up time from 2us to 4us/25mV */
+	pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
+
+	/* SW1B mode to APS/PFM */
+	pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
+
+	/* SW1B standby voltage set to 0.975V */
+	pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
+
+	return 0;
+}
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+void ldo_mode_set(int ldo_bypass)
+{
+	unsigned int value;
+	u32 vddarm;
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("pfuze3000@8", &dev);
+	if (ret == -ENODEV) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* switch to ldo_bypass mode */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+		/* decrease VDDARM to 1.275V */
+		value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
+		value &= ~0x1f;
+		value |= PFUZE3000_SW1AB_SETP(12750);
+		pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value);
+
+		set_anatop_bypass(1);
+		vddarm = PFUZE3000_SW1AB_SETP(11750);
+
+		value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
+		value &= ~0x1f;
+		value |= vddarm;
+		pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value);
+
+		finish_anatop_bypass();
+
+		printf("switch to ldo_bypass mode!\n");
+	}
+}
+#endif
+#endif
+
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
@@ -45,49 +140,105 @@ static void setup_iomux_uart(void)
 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 
-int board_mmc_get_env_dev(int devno)
-{
-	return devno;
-}
+#ifdef CONFIG_FSL_QSPI
+
+#ifndef CONFIG_DM_SPI
+#define QSPI_PAD_CTRL1	\
+	(PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
+	 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+	MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+#endif
 
-int mmc_map_to_kernel_blk(int devno)
+static int board_qspi_init(void)
 {
-	return devno;
+#ifndef CONFIG_DM_SPI
+	/* Set the iomux */
+	imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+					 ARRAY_SIZE(quadspi_pads));
+#endif
+	/* Set the clock */
+	enable_qspi_clk(0);
+
+	return 0;
 }
+#endif
 
-int board_early_init_f(void)
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const nand_pads[] = {
+	MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+	MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+};
+
+static void setup_gpmi_nand(void)
 {
-	setup_iomux_uart();
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
-	return 0;
+	/* config gpmi nand iomux */
+	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+
+	setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
+
+	/* enable apbh clock gating */
+	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 }
+#endif
 
 #ifdef CONFIG_FEC_MXC
-static int setup_fec(int fec_id)
+static int setup_fec(void)
 {
 	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	int ret;
 
-	if (fec_id == 0) {
-		/*
-		 * Use 50MHz anatop loopback REF_CLK1 for ENET1,
-		 * clear gpr1[13], set gpr1[17].
-		 */
-		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
-				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
-	} else {
-		/*
-		 * Use 50MHz anatop loopback REF_CLK2 for ENET2,
-		 * clear gpr1[14], set gpr1[18].
-		 */
+	/*
+	 * Use 50M anatop loopback REF_CLK1 for ENET1,
+	 * clear gpr1[13], set gpr1[17].
+	 */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+	/*
+	 * Use 50M anatop loopback REF_CLK2 for ENET2,
+	 * clear gpr1[14], set gpr1[18].
+	 */
+	if (!check_module_fused(MODULE_ENET2)) {
 		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
 				IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
 	}
 
-	ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
+	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 	if (ret)
 		return ret;
 
+	if (!check_module_fused(MODULE_ENET2)) {
+		ret = enable_fec_anatop_clock(1, ENET_50MHZ);
+		if (ret)
+			return ret;
+	}
+
 	enable_enet_clk(1);
 
 	return 0;
@@ -104,13 +255,56 @@ int board_phy_config(struct phy_device *phydev)
 }
 #endif
 
+#ifdef CONFIG_DM_VIDEO
+static iomux_v3_cfg_t const lcd_pads[] = {
+	/* Use GPIO for Brightness adjustment, duty cycle = period. */
+	MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static int setup_lcd(void)
+{
+	enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
+
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+
+	/* Reset the LCD */
+	gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
+	gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
+	udelay(500);
+	gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
+
+	/* Set Brightness to high */
+	gpio_request(IMX_GPIO_NR(1, 8), "backlight");
+	gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
+
+	return 0;
+}
+#else
+static inline int setup_lcd(void) { return 0; }
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
 int board_init(void)
 {
 	/* Address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
 #ifdef	CONFIG_FEC_MXC
-	setup_fec(CONFIG_FEC_ENET_DEV);
+	setup_fec();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
 #endif
 
 	return 0;
@@ -132,20 +326,41 @@ int board_late_init(void)
 	add_board_boot_modes(board_boot_modes);
 #endif
 
+	env_set("tee", "no");
+#ifdef CONFIG_IMX_OPTEE
+	env_set("tee", "yes");
+#endif
+
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-	if (is_cpu_type(MXC_CPU_MX6ULZ))
-		env_set("board_name", "ULZ-EVK");
+	env_set("board_name", "EVK");
+
+	if (is_mx6ull_9x9_evk())
+		env_set("board_rev", "9X9");
 	else
-		env_set("board_name", "EVK");
-	env_set("board_rev", "14X14");
+		env_set("board_rev", "14X14");
+
+	if (is_cpu_type(MXC_CPU_MX6ULZ)) {
+		env_set("board_name", "ULZ-EVK");
+		env_set("usb_net_cmd", "usb start");
+    }
 #endif
 
+	setup_lcd();
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
+
 	return 0;
 }
 
 int checkboard(void)
 {
-	if (is_cpu_type(MXC_CPU_MX6ULZ))
+	if (is_mx6ull_9x9_evk())
+		puts("Board: MX6ULL 9x9 EVK\n");
+	else if (is_cpu_type(MXC_CPU_MX6ULZ))
 		puts("Board: MX6ULZ 14x14 EVK\n");
 	else
 		puts("Board: MX6ULL 14x14 EVK\n");
diff --git a/board/freescale/mx6ullevk/plugin.S b/board/freescale/mx6ullevk/plugin.S
index 1f631ff5e3e..812088d13c1 100644
--- a/board/freescale/mx6ullevk/plugin.S
+++ b/board/freescale/mx6ullevk/plugin.S
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  */
 
 #include <config.h>
@@ -115,6 +116,120 @@
 	str r1, [r0, #0x01C]
 .endm
 
+.macro imx6ull_lpddr2_evk_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x00080000
+	str r1, [r0, #0x4B4]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4AC]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x27C]
+	str r1, [r0, #0x250]
+	str r1, [r0, #0x24C]
+	str r1, [r0, #0x490]
+	str r1, [r0, #0x288]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x270]
+	str r1, [r0, #0x260]
+	str r1, [r0, #0x264]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4A0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x494]
+
+	ldr r1, =0x00003030
+	str r1, [r0, #0x280]
+	ldr r1, =0x00003030
+	str r1, [r0, #0x284]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x4B0]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x498]
+	str r1, [r0, #0x4A4]
+	str r1, [r0, #0x244]
+	str r1, [r0, #0x248]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1C]
+	ldr r1, =0x1b4700c7
+	str r1, [r0, #0x85c]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x23400A38
+	str r1, [r0, #0x890]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8b8]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81C]
+	str r1, [r0, #0x820]
+	ldr r1, =0xF3333333
+	str r1, [r0, #0x82C]
+	str r1, [r0, #0x830]
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83C]
+	ldr r1, =0x40403439
+	str r1, [r0, #0x848]
+	ldr r1, =0x4040342D
+	str r1, [r0, #0x850]
+	ldr r1, =0x00921012
+	str r1, [r0, #0x8C0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8B8]
+
+	ldr r1, =0x00020052
+	str r1, [r0, #0x004]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x008]
+	ldr r1, =0x33374133
+	str r1, [r0, #0x00C]
+	ldr r1, =0x00100A82
+	str r1, [r0, #0x010]
+	ldr r1, =0x00170557
+	str r1, [r0, #0x038]
+	ldr r1, =0x00000093
+	str r1, [r0, #0x014]
+	ldr r1, =0x00201748
+	str r1, [r0, #0x018]
+	ldr r1, =0x0F9F26D2
+	str r1, [r0, #0x02C]
+	ldr r1, =0x009F0010
+	str r1, [r0, #0x030]
+	ldr r1, =0x00000047
+	str r1, [r0, #0x040]
+	ldr r1, =0x83100000
+	str r1, [r0, #0x000]
+	ldr r1, =0x00008010
+	str r1, [r0, #0x01C]
+	ldr r1, =0x003F8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0xFF0A8030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x82018030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x04028030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x01038030
+	str r1, [r0, #0x01C]
+	ldr r1, =0x00001800
+	str r1, [r0, #0x020]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x818]
+	ldr r1, =0xA1310003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00025552
+	str r1, [r0, #0x004]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x01C]
+.endm
+
 .macro imx6_clock_gating
 	ldr r0, =CCM_BASE_ADDR
 	ldr r1, =0xFFFFFFFF
@@ -125,13 +240,23 @@
 	str r1, [r0, #0x78]
 	str r1, [r0, #0x7C]
 	str r1, [r0, #0x80]
+
+#ifdef CONFIG_IMX_OPTEE
+	ldr r0, =0x20e4024
+	ldr r1, =0x1
+	str r1, [r0]
+#endif
 .endm
 
 .macro imx6_qos_setting
 .endm
 
 .macro imx6_ddr_setting
+#if defined (CONFIG_TARGET_MX6ULL_9X9_EVK)
+	imx6ull_lpddr2_evk_setting
+#else
 	imx6ull_ddr3_evk_setting
+#endif
 .endm
 
 /* include the common plugin code here */
diff --git a/board/freescale/mx7d_12x12_ddr3_val/Kconfig b/board/freescale/mx7d_12x12_ddr3_val/Kconfig
new file mode 100644
index 00000000000..efe29ed8bec
--- /dev/null
+++ b/board/freescale/mx7d_12x12_ddr3_val/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_MX7D_12X12_DDR3_VAL
+
+config SYS_BOARD
+	default "mx7d_12x12_ddr3_val"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx7d_12x12_ddr3_val"
+
+config SYS_TEXT_BASE
+	default 0x87800000
+endif
diff --git a/board/freescale/mx7d_12x12_ddr3_val/Makefile b/board/freescale/mx7d_12x12_ddr3_val/Makefile
new file mode 100644
index 00000000000..21985cfe56a
--- /dev/null
+++ b/board/freescale/mx7d_12x12_ddr3_val/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx7d_12x12_ddr3_val.o
diff --git a/board/freescale/mx7d_12x12_ddr3_val/imximage.cfg b/board/freescale/mx7d_12x12_ddr3_val/imximage.cfg
new file mode 100644
index 00000000000..b4f45846299
--- /dev/null
+++ b/board/freescale/mx7d_12x12_ddr3_val/imximage.cfg
@@ -0,0 +1,110 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * sd/onenand, nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7d_12x12_ddr3_arm2/plugin.bin 0x00910000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005
+/* Clear then set bit30 to ensure exit from DDR retention */
+DATA 4 0x30360388 0x40000000
+DATA 4 0x30360384 0x40000000
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x01040001
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0064 0x00400046
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00020083
+DATA 4 0x307a00d4 0x00690000
+DATA 4 0x307a00dc 0x09300004
+DATA 4 0x307a00e0 0x04080000
+DATA 4 0x307a00e4 0x00100004
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x09081109
+DATA 4 0x307a0104 0x0007020d
+DATA 4 0x307a0108 0x03040407
+DATA 4 0x307a010c 0x00002006
+DATA 4 0x307a0110 0x04020205
+DATA 4 0x307a0114 0x03030202
+DATA 4 0x307a0120 0x00000803
+DATA 4 0x307a0180 0x00800020
+DATA 4 0x307a0184 0x02000100
+DATA 4 0x307a0190 0x02098204
+DATA 4 0x307a0194 0x00030303
+DATA 4 0x307a0200 0x00000016
+DATA 4 0x307a0204 0x00080808
+DATA 4 0x307a0210 0x00000f0f
+DATA 4 0x307a0214 0x07070707
+DATA 4 0x307a0218 0x0f070707
+DATA 4 0x307a0240 0x06000604
+DATA 4 0x307a0244 0x00000001
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17420f40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790010 0x00060807
+DATA 4 0x307900b0 0x1010007e
+DATA 4 0x3079009c 0x00000b24
+DATA 4 0x30790020 0x08080808
+DATA 4 0x30790030 0x08080808
+DATA 4 0x30790050 0x01000010
+DATA 4 0x30790050 0x00000010
+
+DATA 4 0x307900c0 0x0e407304
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e447306
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e407304
+
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+DATA 4 0x30790018 0x0000000f
+
+CHECK_BITS_SET 4 0x307a0004 0x1
+
+#endif
diff --git a/board/freescale/mx7d_12x12_ddr3_val/imximage_TO_1_1.cfg b/board/freescale/mx7d_12x12_ddr3_val/imximage_TO_1_1.cfg
new file mode 100644
index 00000000000..7473e02a59f
--- /dev/null
+++ b/board/freescale/mx7d_12x12_ddr3_val/imximage_TO_1_1.cfg
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * sd/onenand, nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7d_12x12_ddr3_val/plugin.bin 0x00910000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x30360070 0x00703021
+DATA 4 0x30360090 0x0
+DATA 4 0x30360070 0x00603021
+CHECK_BITS_SET 4 0x30360070 0x80000000
+DATA 4 0x30389880 0x1
+
+DATA 4 0x30340004 0x4F400005
+/* Clear then set bit30 to ensure exit from DDR retention */
+DATA 4 0x30360388 0x40000000
+DATA 4 0x30360384 0x40000000
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x01040001
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0064 0x00400046
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00020083
+DATA 4 0x307a00d4 0x00690000
+DATA 4 0x307a00dc 0x09300004
+DATA 4 0x307a00e0 0x04080000
+DATA 4 0x307a00e4 0x00100004
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x09081109
+DATA 4 0x307a0104 0x0007020d
+DATA 4 0x307a0108 0x03040407
+DATA 4 0x307a010c 0x00002006
+DATA 4 0x307a0110 0x04020205
+DATA 4 0x307a0114 0x03030202
+DATA 4 0x307a0120 0x00000803
+DATA 4 0x307a0180 0x00800020
+DATA 4 0x307a0184 0x02000100
+DATA 4 0x307a0190 0x02098204
+DATA 4 0x307a0194 0x00030303
+DATA 4 0x307a0200 0x00000016
+DATA 4 0x307a0204 0x00080808
+DATA 4 0x307a0210 0x00000f0f
+DATA 4 0x307a0214 0x07070707
+DATA 4 0x307a0218 0x0f070707
+DATA 4 0x307a0240 0x06000604
+DATA 4 0x307a0244 0x00000001
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17420f40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790010 0x00060807
+DATA 4 0x307900b0 0x1010007e
+DATA 4 0x3079009c 0x00000dee
+DATA 4 0x3079007c 0x18181818
+DATA 4 0x30790080 0x18181818
+DATA 4 0x30790084 0x40401818
+DATA 4 0x30790088 0x00000040
+DATA 4 0x3079006c 0x40404040
+DATA 4 0x30790020 0x08080808
+DATA 4 0x30790030 0x08080808
+DATA 4 0x30790050 0x01000010
+DATA 4 0x30790050 0x00000010
+
+DATA 4 0x307900c0 0x0e407304
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e447306
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e407304
+
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+DATA 4 0x30790018 0x0000000f
+
+CHECK_BITS_SET 4 0x307a0004 0x1
+
+#endif
diff --git a/board/freescale/mx7d_12x12_ddr3_val/mx7d_12x12_ddr3_val.c b/board/freescale/mx7d_12x12_ddr3_val/mx7d_12x12_ddr3_val.c
new file mode 100644
index 00000000000..cb83f835742
--- /dev/null
+++ b/board/freescale/mx7d_12x12_ddr3_val/mx7d_12x12_ddr3_val.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../common/pfuze.h"
+#include <asm/arch/crm_regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
+	PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+
+#ifdef CONFIG_MXC_SPI
+#ifndef CONFIG_DM_SPI
+iomux_v3_cfg_t const ecspi1_pads[] = {
+	MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX7D_PAD_SD1_WP__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX7D_PAD_SD1_CD_B__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	/* Chip selects CS0:CS3 */
+	MX7D_PAD_SD1_CLK__GPIO5_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX7D_PAD_SD1_CMD__GPIO5_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX7D_PAD_SD1_DATA0__GPIO5_IO5 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX7D_PAD_SD1_DATA1__GPIO5_IO6 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void setup_spinor(void)
+{
+	imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+					 ARRAY_SIZE(ecspi1_pads));
+	gpio_request(IMX_GPIO_NR(5, 3), "ecspi1_cs");
+	gpio_direction_output(IMX_GPIO_NR(5, 3), 0);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 3 && cs == 0) ? (IMX_GPIO_NR(5, 3)) : -1;
+}
+#endif
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_MXC_SPI
+#ifndef CONFIG_DM_SPI
+	setup_spinor();
+#endif
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"emmc", MAKE_CFGVAL(0x10, 0x22, 0x00, 0x00)},
+	{"sd3", MAKE_CFGVAL(0x10, 0x1a, 0x00, 0x00)},
+	{NULL,   0},
+};
+#endif
+
+#ifdef CONFIG_DM_PMIC
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret, dev_id, rev_id, reg;
+
+	ret = pmic_get("pfuze3000@8", &dev);
+	if (ret == -ENODEV)
+		return 0;
+	if (ret != 0)
+		return ret;
+
+	dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
+	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+	/* disable Low Power Mode during standby mode */
+	reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
+	reg |= 0x1;
+	pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
+
+	/* SW1A/1B mode set to APS/APS */
+	reg = 0x8;
+	pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg);
+	pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
+
+	/* SW1A/1B standby voltage set to 0.975V */
+	reg = 0xb;
+	pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg);
+	pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
+
+	/* set SW1B normal voltage to 0.975V */
+	reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
+	reg &= ~0x1f;
+	reg |= PFUZE3000_SW1AB_SETP(9750);
+	pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg);
+
+	return 0;
+}
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return get_cpu_rev();
+}
+
+int checkboard(void)
+{
+	puts("Board: MX7D 12x12 DDR3 VAL\n");
+
+	return 0;
+}
diff --git a/board/freescale/mx7d_12x12_ddr3_val/plugin.S b/board/freescale/mx7d_12x12_ddr3_val/plugin.S
new file mode 100644
index 00000000000..f1980b8879e
--- /dev/null
+++ b/board/freescale/mx7d_12x12_ddr3_val/plugin.S
@@ -0,0 +1,227 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx7d_ddrphy_latency_setting
+	ldr r2, =ANATOP_BASE_ADDR
+	ldr r3, [r2, #0x800]
+	and r3, r3, #0xFF
+	cmp r3, #0x11
+	bne NO_DELAY
+
+	/*TO 1.1*/
+	ldr r1, =0x00000dee
+	str r1, [r0, #0x9c]
+	ldr r1, =0x18181818
+	str r1, [r0, #0x7c]
+	ldr r1, =0x18181818
+	str r1, [r0, #0x80]
+	ldr r1, =0x40401818
+	str r1, [r0, #0x84]
+	ldr r1, =0x00000040
+	str r1, [r0, #0x88]
+	ldr r1, =0x40404040
+	str r1, [r0, #0x6c]
+	b TUNE_END
+
+NO_DELAY:
+	/*TO 1.0*/
+	ldr r1, =0x00000b24
+	str r1, [r0, #0x9c]
+
+TUNE_END:
+.endm
+
+.macro imx7d_ddr_freq_setting
+	ldr r2, =ANATOP_BASE_ADDR
+	ldr r3, [r2, #0x800]
+	and r3, r3, #0xFF
+	cmp r3, #0x11
+	bne FREQ_DEFAULT_533
+
+	/* Change to 400Mhz for TO1.1 */
+	ldr r0, =ANATOP_BASE_ADDR
+	ldr r1, =0x70
+	ldr r2, =0x00703021
+	str r2, [r0, r1]
+	ldr r1, =0x90
+	ldr r2, =0x0
+	str r2, [r0, r1]
+	ldr r1, =0x70
+	ldr r2, =0x00603021
+	str r2, [r0, r1]
+
+	ldr r3, =0x80000000
+wait_lock:
+	ldr r2, [r0, r1]
+	and r2, r3
+	cmp r2, r3
+	bne wait_lock
+
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0x9880
+	ldr r2, =0x1
+	str r2, [r0, r1]
+
+FREQ_DEFAULT_533:
+.endm
+
+.macro imx7d_12x12_ddr3_val_ddr_setting
+	imx7d_ddr_freq_setting
+
+	/* Configure ocram_epdc */
+	ldr r0, =IOMUXC_GPR_BASE_ADDR
+	ldr r1, =0x4f400005
+	str r1, [r0, #0x4]
+
+	/* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
+	ldr r0, =ANATOP_BASE_ADDR
+	ldr r1, =(0x1 << 30)
+	str r1, [r0, #0x388]
+	str r1, [r0, #0x384]
+
+	ldr r0, =SRC_BASE_ADDR
+	ldr r1, =0x2
+	ldr r2, =0x1000
+	str r1, [r0, r2]
+
+	ldr r0, =DDRC_IPS_BASE_ADDR
+	ldr r1, =0x01040001
+	str r1, [r0]
+	ldr r1, =0x80400003
+	str r1, [r0, #0x1a0]
+	ldr r1, =0x00100020
+	str r1, [r0, #0x1a4]
+	ldr r1, =0x80100004
+	str r1, [r0, #0x1a8]
+	ldr r1, =0x00400046
+	str r1, [r0, #0x64]
+	ldr r1, =0x1
+	str r1, [r0, #0x490]
+	ldr r1, =0x00020001
+	str r1, [r0, #0xd0]
+	ldr r1, =0x00690000
+	str r1, [r0, #0xd4]
+	ldr r1, =0x09300004
+	str r1, [r0, #0xdc]
+	ldr r1, =0x04080000
+	str r1, [r0, #0xe0]
+	ldr r1, =0x00100004
+	str r1, [r0, #0xe4]
+	ldr r1, =0x33f
+	str r1, [r0, #0xf4]
+	ldr r1, =0x09081109
+	str r1, [r0, #0x100]
+	ldr r1, =0x0007020d
+	str r1, [r0, #0x104]
+	ldr r1, =0x03040407
+	str r1, [r0, #0x108]
+	ldr r1, =0x00002006
+	str r1, [r0, #0x10c]
+	ldr r1, =0x04020205
+	str r1, [r0, #0x110]
+	ldr r1, =0x03030202
+	str r1, [r0, #0x114]
+	ldr r1, =0x00000803
+	str r1, [r0, #0x120]
+	ldr r1, =0x00800020
+	str r1, [r0, #0x180]
+	ldr r1, =0x02000100
+	str r1, [r0, #0x184]
+	ldr r1, =0x02098204
+	str r1, [r0, #0x190]
+	ldr r1, =0x00030303
+	str r1, [r0, #0x194]
+
+	ldr r1, =0x00000016
+	str r1, [r0, #0x200]
+	ldr r1, =0x00080808
+	str r1, [r0, #0x204]
+	ldr r1, =0x00000f0f
+	str r1, [r0, #0x210]
+	ldr r1, =0x07070707
+	str r1, [r0, #0x214]
+	ldr r1, =0x0f070707
+	str r1, [r0, #0x218]
+
+	ldr r1, =0x06000604
+	str r1, [r0, #0x240]
+	ldr r1, =0x00000001
+	str r1, [r0, #0x244]
+
+	ldr r0, =SRC_BASE_ADDR
+	mov r1, #0x0
+	ldr r2, =0x1000
+	str r1, [r0, r2]
+
+	ldr r0, =DDRPHY_IPS_BASE_ADDR
+	ldr r1, =0x17420f40
+	str r1, [r0]
+	ldr r1, =0x10210100
+	str r1, [r0, #0x4]
+	ldr r1, =0x00060807
+	str r1, [r0, #0x10]
+	ldr r1, =0x1010007e
+	str r1, [r0, #0xb0]
+	imx7d_ddrphy_latency_setting
+	ldr r1, =0x08080808
+	str r1, [r0, #0x20]
+	ldr r1, =0x08080808
+	str r1, [r0, #0x30]
+	ldr r1, =0x01000010
+	str r1, [r0, #0x50]
+
+	ldr r1, =0x0e407304
+	str r1, [r0, #0xc0]
+	ldr r1, =0x0e447304
+	str r1, [r0, #0xc0]
+	ldr r1, =0x0e447306
+	str r1, [r0, #0xc0]
+
+wait_zq:
+	ldr r1, [r0, #0xc4]
+	tst r1, #0x1
+	beq wait_zq
+
+	ldr r1, =0x0e407304
+	str r1, [r0, #0xc0]
+
+	ldr r0, =CCM_BASE_ADDR
+	mov r1, #0x0
+	ldr r2, =0x4130
+	str r1, [r0, r2]
+	ldr r0, =IOMUXC_GPR_BASE_ADDR
+	mov r1, #0x178
+	str r1, [r0, #0x20]
+	ldr r0, =CCM_BASE_ADDR
+	mov r1, #0x2
+	ldr r2, =0x4130
+	str r1, [r0, r2]
+	ldr r0, =DDRPHY_IPS_BASE_ADDR
+	ldr r1, =0x0000000f
+	str r1, [r0, #0x18]
+
+	ldr r0, =DDRC_IPS_BASE_ADDR
+wait_stat:
+	ldr r1, [r0, #0x4]
+	tst r1, #0x1
+	beq wait_stat
+.endm
+
+.macro imx7_clock_gating
+.endm
+
+.macro imx7_qos_setting
+.endm
+
+.macro imx7_ddr_setting
+	imx7d_12x12_ddr3_val_ddr_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx7_plugin.S>
diff --git a/board/freescale/mx7d_12x12_lpddr3_val/Kconfig b/board/freescale/mx7d_12x12_lpddr3_val/Kconfig
new file mode 100644
index 00000000000..31ede4d88cf
--- /dev/null
+++ b/board/freescale/mx7d_12x12_lpddr3_val/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_MX7D_12X12_LPDDR3_VAL
+
+config SYS_BOARD
+	default "mx7d_12x12_lpddr3_val"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx7d_12x12_lpddr3_val"
+
+config SYS_TEXT_BASE
+	default 0x87800000
+endif
diff --git a/board/freescale/mx7d_12x12_lpddr3_val/Makefile b/board/freescale/mx7d_12x12_lpddr3_val/Makefile
new file mode 100644
index 00000000000..ca48fa0b950
--- /dev/null
+++ b/board/freescale/mx7d_12x12_lpddr3_val/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx7d_12x12_lpddr3_val.o
diff --git a/board/freescale/mx7d_12x12_lpddr3_val/imximage.cfg b/board/freescale/mx7d_12x12_lpddr3_val/imximage.cfg
new file mode 100644
index 00000000000..36fd4738998
--- /dev/null
+++ b/board/freescale/mx7d_12x12_lpddr3_val/imximage.cfg
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7d_12x12_lpddr3_val/plugin.bin 0x00910000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005
+/* Clear then set bit30 to ensure exit from DDR retention */
+DATA 4 0x30360388 0x40000000
+DATA 4 0x30360384 0x40000000
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x03040008
+DATA 4 0x307a0064 0x00200038
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00350001
+DATA 4 0x307a00dc 0x00c3000a
+DATA 4 0x307a00e0 0x00010000
+DATA 4 0x307a00e4 0x00110006
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x0a0e110b
+DATA 4 0x307a0104 0x00020211
+DATA 4 0x307a0108 0x03060708
+DATA 4 0x307a010c 0x00a0500c
+DATA 4 0x307a0110 0x05020307
+DATA 4 0x307a0114 0x02020404
+DATA 4 0x307a0118 0x02020003
+DATA 4 0x307a011c 0x00000202
+DATA 4 0x307a0120 0x00000202
+
+DATA 4 0x307a0180 0x00600018
+DATA 4 0x307a0184 0x00e00100
+DATA 4 0x307a0190 0x02098205
+DATA 4 0x307a0194 0x00060303
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+
+DATA 4 0x307a0200 0x00000016
+DATA 4 0x307a0204 0x00090909
+DATA 4 0x307a0210 0x00000f00
+DATA 4 0x307a0214 0x08080808
+DATA 4 0x307a0218 0x0f0f0808
+
+DATA 4 0x307a0240 0x06000600
+DATA 4 0x307a0244 0x00000000
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17421e40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790008 0x00010000
+DATA 4 0x30790010 0x0007080c
+DATA 4 0x307900b0 0x1010007e
+
+DATA 4 0x3079001C 0x01010000
+DATA 4 0x3079009c 0x00000b24
+
+DATA 4 0x30790030 0x06060606
+DATA 4 0x30790020 0x0a0a0a0a
+DATA 4 0x30790050 0x01000008
+DATA 4 0x30790050 0x00000008
+DATA 4 0x30790018 0x0000000f
+DATA 4 0x307900c0 0x0e487304
+DATA 4 0x307900c0 0x0e4c7304
+DATA 4 0x307900c0 0x0e4c7306
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e487304
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+
+CHECK_BITS_SET 4 0x307a0004 0x1
+#endif
diff --git a/board/freescale/mx7d_12x12_lpddr3_val/imximage_TO_1_1.cfg b/board/freescale/mx7d_12x12_lpddr3_val/imximage_TO_1_1.cfg
new file mode 100644
index 00000000000..b9fb26654df
--- /dev/null
+++ b/board/freescale/mx7d_12x12_lpddr3_val/imximage_TO_1_1.cfg
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7d_12x12_lpddr3_val/plugin.bin 0x00910000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005
+/* Clear then set bit30 to ensure exit from DDR retention */
+DATA 4 0x30360388 0x40000000
+DATA 4 0x30360384 0x40000000
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x03040008
+DATA 4 0x307a0064 0x00200038
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00350001
+DATA 4 0x307a00dc 0x00c3000a
+DATA 4 0x307a00e0 0x00010000
+DATA 4 0x307a00e4 0x00110006
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x0a0e110b
+DATA 4 0x307a0104 0x00020211
+DATA 4 0x307a0108 0x03060708
+DATA 4 0x307a010c 0x00a0500c
+DATA 4 0x307a0110 0x05020307
+DATA 4 0x307a0114 0x02020404
+DATA 4 0x307a0118 0x02020003
+DATA 4 0x307a011c 0x00000202
+DATA 4 0x307a0120 0x00000202
+
+DATA 4 0x307a0180 0x00600018
+DATA 4 0x307a0184 0x00e00100
+DATA 4 0x307a0190 0x02098205
+DATA 4 0x307a0194 0x00060303
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+
+DATA 4 0x307a0200 0x00000016
+DATA 4 0x307a0204 0x00090909
+DATA 4 0x307a0210 0x00000f00
+DATA 4 0x307a0214 0x08080808
+DATA 4 0x307a0218 0x0f0f0808
+
+DATA 4 0x307a0240 0x06000601
+DATA 4 0x307a0244 0x00000000
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17421e40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790008 0x00010000
+DATA 4 0x30790010 0x0007080c
+DATA 4 0x3079007c 0x1c1c1c1c
+DATA 4 0x30790080 0x1c1c1c1c
+DATA 4 0x30790084 0x30301c1c
+DATA 4 0x30790088 0x00000030
+DATA 4 0x3079006c 0x30303030
+DATA 4 0x307900b0 0x1010007e
+
+DATA 4 0x3079001C 0x01010000
+DATA 4 0x3079009c 0x0db60d6e
+
+DATA 4 0x30790030 0x06060606
+DATA 4 0x30790020 0x0a0a0a0a
+DATA 4 0x30790050 0x01000008
+DATA 4 0x30790050 0x00000008
+DATA 4 0x30790018 0x0000000f
+DATA 4 0x307900c0 0x1e487304
+DATA 4 0x307900c0 0x1e487304
+DATA 4 0x307900c0 0x1e487306
+DATA 4 0x307900c0 0x1e4c7304
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x1e487304
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+
+CHECK_BITS_SET 4 0x307a0004 0x1
+#endif
diff --git a/board/freescale/mx7d_12x12_lpddr3_val/mx7d_12x12_lpddr3_val.c b/board/freescale/mx7d_12x12_lpddr3_val/mx7d_12x12_lpddr3_val.c
new file mode 100644
index 00000000000..195b43a1609
--- /dev/null
+++ b/board/freescale/mx7d_12x12_lpddr3_val/mx7d_12x12_lpddr3_val.c
@@ -0,0 +1,654 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../common/pfuze.h"
+#include <asm/arch/crm_regs.h>
+#include <asm/mach-imx/video.h>
+#include <linux/delay.h>
+
+#ifdef CONFIG_VIDEO_MXS
+#include <linux/fb.h>
+#endif
+#if defined(CONFIG_MXC_EPDC)
+#include <lcd.h>
+#include <mxc_epdc_fb.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
+	PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
+#define ENET_PAD_CTRL_MII  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
+	PAD_CTL_DSE_3P3V_49OHM)
+
+#define QSPI_PAD_CTRL	\
+		(PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
+#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+
+#define EPDC_PAD_CTRL	0x0
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lcd_pads[] = {
+	MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+
+	MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const pwm_pads[] = {
+	/* Use GPIO for Brightness adjustment, duty cycle = period */
+	MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void do_enable_parallel_lcd(struct display_info_t const *dev)
+{
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+
+	imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
+
+	/* Power up the LCD */
+	gpio_request(IMX_GPIO_NR(3, 4), "lcd_pwr");
+	gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
+
+	/* Set Brightness to high */
+	gpio_request(IMX_GPIO_NR(1, 1), "lcd_backlight");
+	gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
+}
+
+struct display_info_t const displays[] = {{
+	.bus = ELCDIF1_IPS_BASE_ADDR,
+	.addr = 0,
+	.pixfmt = 24,
+	.detect = NULL,
+	.enable	= do_enable_parallel_lcd,
+	.mode	= {
+		.name			= "MCIMX28LCD",
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 29850,
+		.left_margin    = 89,
+		.right_margin   = 164,
+		.upper_margin   = 23,
+		.lower_margin   = 10,
+		.hsync_len      = 10,
+		.vsync_len      = 10,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+#endif
+
+
+static iomux_v3_cfg_t const per_rst_pads[] = {
+	MX7D_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_FEC_MXC
+static iomux_v3_cfg_t const fec1_pads[] = {
+	MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
+	MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
+	MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_fec1(void)
+{
+	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+}
+#endif
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FSL_QSPI
+#ifndef CONFIG_DM_SPI
+static iomux_v3_cfg_t const quadspi_pads[] = {
+	MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA04__QSPI_A_DQS   | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+
+	MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA12__QSPI_B_DQS   | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+
+};
+#endif
+
+int board_qspi_init(void)
+{
+#ifndef CONFIG_DM_SPI
+	/* Set the iomux */
+	imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
+#endif
+
+	/* Set the clock */
+	set_clk_qspi();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+int board_eth_init(struct bd_info *bis)
+{
+	int ret;
+
+	setup_iomux_fec1();
+
+	ret = fecmxc_initialize_multi(bis, 0,
+		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+	if (ret)
+		printf("FEC1 MXC: %s:failed\n", __func__);
+
+	return 0;
+}
+
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+	int ret;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+		(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
+		 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
+
+	ret = set_clk_enet(ENET_125MHZ);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* Enable 1.8V(SEL_1P5_1P8_POS_REG) on
+	   Phy control debug reg 0 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	/* rgmii tx clock delay enable */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#ifndef CONFIG_DM_SPI
+iomux_v3_cfg_t const ecspi1_pads[] = {
+	MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+
+	/* CS0 */
+	MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void setup_spinor(void)
+{
+	imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+					 ARRAY_SIZE(ecspi1_pads));
+	gpio_request(IMX_GPIO_NR(4, 19), "ecspi1_cs");
+	gpio_direction_output(IMX_GPIO_NR(4, 19), 0);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 19)) : -1;
+}
+#endif
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#ifdef CONFIG_MXC_EPDC
+static iomux_v3_cfg_t const epdc_enable_pads[] = {
+	MX7D_PAD_EPDC_DATA00__EPDC_DATA0	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA01__EPDC_DATA1	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA02__EPDC_DATA2	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA03__EPDC_DATA3	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA04__EPDC_DATA4	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA05__EPDC_DATA5	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA06__EPDC_DATA6	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA07__EPDC_DATA7	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_SDLE__EPDC_SDLE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_SDOE__EPDC_SDOE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_GDOE__EPDC_GDOE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_GDRL__EPDC_GDRL		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_GDSP__EPDC_GDSP		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_BDR0__EPDC_BDR0		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_BDR1__EPDC_BDR1		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const epdc_disable_pads[] = {
+	MX7D_PAD_EPDC_DATA00__GPIO2_IO0,
+	MX7D_PAD_EPDC_DATA01__GPIO2_IO1,
+	MX7D_PAD_EPDC_DATA02__GPIO2_IO2,
+	MX7D_PAD_EPDC_DATA03__GPIO2_IO3,
+	MX7D_PAD_EPDC_DATA04__GPIO2_IO4,
+	MX7D_PAD_EPDC_DATA05__GPIO2_IO5,
+	MX7D_PAD_EPDC_DATA06__GPIO2_IO6,
+	MX7D_PAD_EPDC_DATA07__GPIO2_IO7,
+	MX7D_PAD_EPDC_SDCLK__GPIO2_IO16,
+	MX7D_PAD_EPDC_SDLE__GPIO2_IO17,
+	MX7D_PAD_EPDC_SDOE__GPIO2_IO18,
+	MX7D_PAD_EPDC_SDSHR__GPIO2_IO19,
+	MX7D_PAD_EPDC_SDCE0__GPIO2_IO20,
+	MX7D_PAD_EPDC_SDCE1__GPIO2_IO21,
+	MX7D_PAD_EPDC_SDCE2__GPIO2_IO22,
+	MX7D_PAD_EPDC_SDCE3__GPIO2_IO23,
+	MX7D_PAD_EPDC_GDCLK__GPIO2_IO24,
+	MX7D_PAD_EPDC_GDOE__GPIO2_IO25,
+	MX7D_PAD_EPDC_GDRL__GPIO2_IO26,
+	MX7D_PAD_EPDC_GDSP__GPIO2_IO27,
+	MX7D_PAD_EPDC_BDR0__GPIO2_IO28,
+	MX7D_PAD_EPDC_BDR1__GPIO2_IO29,
+};
+
+vidinfo_t panel_info = {
+	.vl_refresh = 85,
+	.vl_col = 1024,
+	.vl_row = 758,
+	.vl_pixclock = 40000000,
+	.vl_left_margin = 12,
+	.vl_right_margin = 76,
+	.vl_upper_margin = 4,
+	.vl_lower_margin = 5,
+	.vl_hsync = 12,
+	.vl_vsync = 2,
+	.vl_sync = 0,
+	.vl_mode = 0,
+	.vl_flag = 0,
+	.vl_bpix = 3,
+	.cmap = 0,
+};
+
+struct epdc_timing_params panel_timings = {
+	.vscan_holdoff = 4,
+	.sdoed_width = 10,
+	.sdoed_delay = 20,
+	.sdoez_width = 10,
+	.sdoez_delay = 20,
+	.gdclk_hp_offs = 524,
+	.gdsp_offs = 327,
+	.gdoe_offs = 0,
+	.gdclk_offs = 19,
+	.num_ce = 1,
+};
+
+static void setup_epdc_power(void)
+{
+	/* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+		IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0);
+
+	/* Setup epdc voltage */
+
+	/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
+	imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+	gpio_request(IMX_GPIO_NR(2, 31), "epdc_pwrstat");
+	gpio_direction_input(IMX_GPIO_NR(2, 31));
+
+	/* EPDC_VCOM0 - GPIO4[14] for VCOM control */
+	imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* Set as output */
+	gpio_request(IMX_GPIO_NR(4, 14), "epdc_vcom0");
+	gpio_direction_output(IMX_GPIO_NR(4, 14), 1);
+
+	/* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */
+	imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+	/* Set as output */
+	gpio_request(IMX_GPIO_NR(4, 23), "epdc_pwrwakeup");
+	gpio_direction_output(IMX_GPIO_NR(4, 23), 1);
+
+	/* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */
+	imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+	/* Set as output */
+	gpio_request(IMX_GPIO_NR(4, 20), "epdc_pwrctrl0");
+	gpio_direction_output(IMX_GPIO_NR(4, 20), 1);
+}
+
+static void epdc_enable_pins(void)
+{
+	/* epdc iomux settings */
+	imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
+				ARRAY_SIZE(epdc_enable_pads));
+}
+
+static void epdc_disable_pins(void)
+{
+	/* Configure MUX settings for EPDC pins to GPIO  and drive to 0 */
+	imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
+				ARRAY_SIZE(epdc_disable_pads));
+}
+
+static void setup_epdc(void)
+{
+	/*** epdc Maxim PMIC settings ***/
+
+	/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
+	imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* EPDC_VCOM0 - GPIO4[14] for VCOM control */
+	imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */
+	imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */
+	imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* Set pixel clock rates for EPDC in clock.c */
+
+	panel_info.epdc_data.wv_modes.mode_init = 0;
+	panel_info.epdc_data.wv_modes.mode_du = 1;
+	panel_info.epdc_data.wv_modes.mode_gc4 = 3;
+	panel_info.epdc_data.wv_modes.mode_gc8 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc16 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc32 = 2;
+
+	panel_info.epdc_data.epdc_timings = panel_timings;
+
+	setup_epdc_power();
+}
+
+void epdc_power_on(void)
+{
+	unsigned int reg;
+	struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
+
+	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
+	gpio_set_value(IMX_GPIO_NR(4, 20), 1);
+	udelay(1000);
+
+	/* Enable epdc signal pin */
+	epdc_enable_pins();
+
+	/* Set PMIC Wakeup to high - enable Display power */
+	gpio_set_value(IMX_GPIO_NR(4, 23), 1);
+
+	/* Wait for PWRGOOD == 1 */
+	while (1) {
+		reg = readl(&gpio_regs->gpio_psr);
+		if (!(reg & (1 << 31)))
+			break;
+
+		udelay(100);
+	}
+
+	/* Enable VCOM */
+	gpio_set_value(IMX_GPIO_NR(4, 14), 1);
+
+	udelay(500);
+}
+
+void epdc_power_off(void)
+{
+	/* Set PMIC Wakeup to low - disable Display power */
+	gpio_set_value(IMX_GPIO_NR(4, 23), 0);
+
+	/* Disable VCOM */
+	gpio_set_value(IMX_GPIO_NR(4, 14), 0);
+
+	epdc_disable_pins();
+
+	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
+	gpio_set_value(IMX_GPIO_NR(4, 20), 0);
+}
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/* Reset peripherals */
+	imx_iomux_v3_setup_multiple_pads(per_rst_pads, ARRAY_SIZE(per_rst_pads));
+
+	gpio_request(IMX_GPIO_NR(1, 3), "per_rst");
+	gpio_direction_output(IMX_GPIO_NR(1, 3) , 0);
+	udelay(500);
+	gpio_set_value(IMX_GPIO_NR(1, 3), 1);
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#ifndef CONFIG_DM_SPI
+	setup_spinor();
+#endif
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+#ifdef	CONFIG_MXC_EPDC
+	setup_epdc();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd1", MAKE_CFGVAL(0x10, 0x12, 0x00, 0x00)},
+	{"sd2", MAKE_CFGVAL(0x10, 0x16, 0x00, 0x00)},
+	{"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)},
+	{"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},
+	{NULL,   0},
+};
+#endif
+
+#ifdef CONFIG_DM_PMIC
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret, dev_id, rev_id, reg;
+
+	ret = pmic_get("pfuze3000@8", &dev);
+	if (ret == -ENODEV)
+		return 0;
+	if (ret != 0)
+		return ret;
+
+	dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
+	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+	/* disable Low Power Mode during standby mode */
+	reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
+	reg |= 0x1;
+	pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
+
+	/* SW1A/1B mode set to APS/APS */
+	reg = 0x8;
+	pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg);
+	pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
+
+	/* SW1A/1B standby voltage set to 0.975V */
+	reg = 0xb;
+	pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg);
+	pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
+
+	/* below are for LPSR mode support */
+	reg = pmic_reg_read(dev, PFUZE3000_SW3MODE);
+	reg |= 0x20;
+	pmic_reg_write(dev, PFUZE3000_SW3MODE, reg);
+
+	reg = pmic_reg_read(dev, PFUZE3000_VLDO1CTL);
+	reg |= 0x80;
+	pmic_reg_write(dev, PFUZE3000_VLDO1CTL, reg);
+
+	reg = pmic_reg_read(dev, PFUZE3000_VLDO3CTL);
+	reg |= 0x80;
+	pmic_reg_write(dev, PFUZE3000_VLDO3CTL, reg);
+
+	reg = pmic_reg_read(dev, PFUZE3000_SW2MODE);
+	reg |= 0x20;
+	pmic_reg_write(dev, PFUZE3000_SW2MODE, reg);
+
+	/* set SW1B normal voltage to 0.975V */
+	reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
+	reg &= ~0x1f;
+	reg |= PFUZE3000_SW1AB_SETP(9750);
+	pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg);
+
+	return 0;
+}
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return get_cpu_rev();
+}
+
+int checkboard(void)
+{
+	puts("Board: MX7D 12x12 LPDDR3 VAL\n");
+
+	return 0;
+}
diff --git a/board/freescale/mx7d_12x12_lpddr3_val/plugin.S b/board/freescale/mx7d_12x12_lpddr3_val/plugin.S
new file mode 100644
index 00000000000..ff629c865a5
--- /dev/null
+++ b/board/freescale/mx7d_12x12_lpddr3_val/plugin.S
@@ -0,0 +1,657 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx7d_ddrphy_latency_setting
+	ldr r2, =ANATOP_BASE_ADDR
+	ldr r3, [r2, #0x800]
+	and r3, r3, #0xFF
+	cmp r3, #0x11
+	bne TUNE_END
+
+	/*TO 1.1*/
+	ldr r1, =0x1c1c1c1c
+	str r1, [r0, #0x7c]
+	ldr r1, =0x1c1c1c1c
+	str r1, [r0, #0x80]
+	ldr r1, =0x30301c1c
+	str r1, [r0, #0x84]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x88]
+	ldr r1, =0x30303030
+	str r1, [r0, #0x6c]
+
+TUNE_END:
+.endm
+
+.macro imx7d_12x12_lpddr3_val_setting
+
+	/* check whether it is a LPSR resume */
+	ldr	r1, =0x30270000
+	ldr	r7, [r1]
+	cmp	r7, #0
+	beq	16f
+
+	/* disable wdog powerdown counter */
+	ldr	r0, =0x30280000
+	ldrh	r1, =0x0
+	strh	r1, [r0, #0x8]
+
+	/* initialize AIPs 1-3 port */
+	ldr	r0, =0x301f0000
+	ldr	r1, =0x77777777
+	str	r1, [r0]
+	str	r1, [r0, #0x4]
+	ldr	r1, =0x0
+	str	r1, [r0, #0x40]
+	str	r1, [r0, #0x44]
+	str	r1, [r0, #0x48]
+	str	r1, [r0, #0x4c]
+	str	r1, [r0, #0x50]
+
+	ldr	r0, =0x305f0000
+	ldr	r1, =0x77777777
+	str	r1, [r0]
+	str	r1, [r0, #0x4]
+	ldr	r1, =0x0
+	str	r1, [r0, #0x40]
+	str	r1, [r0, #0x44]
+	str	r1, [r0, #0x48]
+	str	r1, [r0, #0x4c]
+	str	r1, [r0, #0x50]
+
+	ldr	r0, =0x309f0000
+	ldr	r1, =0x77777777
+	str	r1, [r0]
+	str	r1, [r0, #0x4]
+	ldr	r1, =0x0
+	str	r1, [r0, #0x40]
+	str	r1, [r0, #0x44]
+	str	r1, [r0, #0x48]
+	str	r1, [r0, #0x4c]
+	str	r1, [r0, #0x50]
+
+	ldr	r1, =0x30360000
+	ldr	r2, =0x30390000
+	ldr	r3, =0x307a0000
+	ldr	r4, =0x30790000
+	ldr	r10, =0x30380000
+	ldr	r11, =0x30340000
+
+	/* turn on ddr power */
+	ldr	r7, =(0x1 << 29)
+	str	r7, [r1, #0x388]
+
+	ldr	r6, =50
+1:
+	subs	r6, r6, #0x1
+	bne	1b
+
+	/* clear ddr_phy reset */
+	ldr	r6, =0x1000
+	ldr	r7, [r2, r6]
+	orr	r7, r7, #0x3
+	str	r7, [r2, r6]
+	ldr	r7, [r2, r6]
+	bic	r7, r7, #0x1
+	str	r7, [r2, r6]
+
+	/* restore DDRC */
+	ldr	r6, =0x0
+	ldr	r7, =0x03040008
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x1a0
+	ldr	r7, =0x80400003
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x1a4
+	ldr	r7, =0x00100020
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x1a8
+	ldr	r7, =0x80100004
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x64
+	ldr	r7, =0x00200038
+	str	r7, [r3, r6]
+
+	ldr	r6, =0xd0
+	ldr	r7, =0xc0350001
+	str	r7, [r3, r6]
+
+	ldr	r6, =0xdc
+	ldr	r7, =0x00C3000A
+	str	r7, [r3, r6]
+
+	ldr	r6, =0xe0
+	ldr	r7, =0x00010000
+	str	r7, [r3, r6]
+
+	ldr	r6, =0xe4
+	ldr	r7, =0x00110006
+	str	r7, [r3, r6]
+
+	ldr	r6, =0xf4
+	ldr	r7, =0x0000033F
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x100
+	ldr	r7, =0x0A0E110B
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x104
+	ldr	r7, =0x00020211
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x108
+	ldr	r7, =0x03060708
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x10c
+	ldr	r7, =0x00A0500C
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x110
+	ldr	r7, =0x05020307
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x114
+	ldr	r7, =0x02020404
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x118
+	ldr	r7, =0x02020003
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x11c
+	ldr	r7, =0x00000202
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x120
+	ldr	r7, =0x00000202
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x180
+	ldr	r7, =0x00600018
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x184
+	ldr	r7, =0x00e00100
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x190
+	ldr	r7, =0x02098205
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x194
+	ldr	r7, =0x00060303
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x200
+	ldr	r7, =0x00000016
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x204
+	ldr	r7, =0x00090909
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x210
+	ldr	r7, =0xF00
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x214
+	ldr	r7, =0x08080808
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x218
+	ldr	r7, =0x0f0f0808
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x240
+	ldr	r7, =0x06000600
+	str	r7, [r3, r6]
+
+	ldr	r6, =0x244
+	ldr	r7, =0x00000000
+	str	r7, [r3, r6]
+
+	ldr	r7, =0x20
+	str	r7, [r3, #0x30]
+	ldr	r7, =0x0
+	str	r7, [r3, #0x1b0]
+
+	/* do PHY, clear ddr_phy reset */
+	ldr	r6, =0x1000
+	ldr	r7, [r2, r6]
+	bic	r7, r7, #0x2
+	str	r7, [r2, r6]
+
+	ldr	r7, [r1, #0x800]
+	and	r7, r7, #0xFF
+	cmp	r7, #0x11
+	bne	2f
+
+	/* for TO1.1 */
+	ldr	r7, [r11]
+	bic	r7, r7, #(1 << 27)
+	str	r7, [r11]
+	ldr	r7, [r11]
+	bic	r7, r7, #(1 << 29)
+	str	r7, [r11]
+2:
+	/* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
+	ldr	r7, =(0x1 << 30)
+	str	r7, [r1, #0x388]
+	ldr	r7, =(0x1 << 30)
+	str	r7, [r1, #0x384]
+
+	/* need to delay ~5mS */
+	ldr	r6, =0x100000
+3:
+	subs	r6, r6, #0x1
+	bne	3b
+
+	/* restore DDR PHY */
+	ldr	r6, =0x0
+	ldr	r7, =0x17421E40
+	str	r7, [r4, r6]
+
+	ldr	r6, =0x4
+	ldr	r7, =0x10210100
+	str	r7, [r4, r6]
+
+	ldr	r6, =0x8
+	ldr	r7, =0x00010000
+	str	r7, [r4, r6]
+
+	ldr	r6, =0x10
+	ldr	r7, =0x0007080C
+	str	r7, [r4, r6]
+
+	ldr	r6, =0xb0
+	ldr	r7, =0x1010007e
+	str	r7, [r4, r6]
+
+	ldr     r7, [r1, #0x800]
+	and     r7, r7, #0xFF
+	cmp     r7, #0x11
+	bne     4f
+
+	ldr	r6, =0x7c
+	ldr	r7, =0x1c1c1c1c
+	str	r7, [r4, r6]
+
+	ldr	r6, =0x80
+	ldr	r7, =0x1c1c1c1c
+	str	r7, [r4, r6]
+
+	ldr	r6, =0x84
+	ldr	r7, =0x30301c1c
+	str	r7, [r4, r6]
+
+	ldr	r6, =0x88
+	ldr	r7, =0x00000030
+	str	r7, [r4, r6]
+
+	ldr	r6, =0x6c
+	ldr	r7, =0x30303030
+	str	r7, [r4, r6]
+
+	ldr	r6, =0x1c
+	ldr	r7, =0x01010000
+	str	r7, [r4, r6]
+
+	ldr	r6, =0x9c
+	ldr	r7, =0x0DB60D6E
+	str	r7, [r4, r6]
+
+	b	5f
+
+4:
+	ldr	r6, =0x1c
+	ldr	r7, =0x01010000
+	str	r7, [r4, r6]
+
+	ldr	r6, =0x9c
+	ldr	r7, =0x00000b24
+	str	r7, [r4, r6]
+
+5:
+	ldr	r6, =0x20
+	ldr	r7, =0x0a0a0a0a
+	str	r7, [r4, r6]
+
+	ldr	r6, =0x30
+	ldr	r7, =0x06060606
+	str	r7, [r4, r6]
+
+	ldr	r6, =0x50
+	ldr	r7, =0x01000008
+	str	r7, [r4, r6]
+
+	ldr	r6, =0x50
+	ldr	r7, =0x00000008
+	str	r7, [r4, r6]
+
+	ldr	r6, =0xc0
+	ldr	r7, =0x0e487304
+	str	r7, [r4, r6]
+
+	ldr	r6, =0xc0
+	ldr	r7, =0x0e4c7304
+	str	r7, [r4, r6]
+
+	ldr	r6, =0xc0
+	ldr	r7, =0x0e4c7306
+	str	r7, [r4, r6]
+
+6:
+	ldr	r7, [r4, #0xc4]
+	tst	r7, #0x1
+	beq	6b
+
+	ldr	r6, =0xc0
+	ldr	r7, =0x0e487304
+	str	r7, [r4, r6]
+
+	ldr	r7, =0x0
+	add	r9, r10, #0x4000
+	str	r7, [r9, #0x130]
+
+	ldr	r7, =0x170
+	orr	r7, r7, #0x8
+	str	r7, [r11, #0x20]
+
+	ldr	r7, =0x2
+	add	r9, r10, #0x4000
+	str	r7, [r9, #0x130]
+
+	ldr	r7, =0xf
+	str	r7, [r4, #0x18]
+
+	/* wait until self-refresh mode entered */
+11:
+	ldr	r7, [r3, #0x4]
+	and	r7, r7, #0x3
+	cmp	r7, #0x3
+	bne	11b
+	ldr	r7, =0x0
+	str	r7, [r3, #0x320]
+	ldr	r7, =0x1
+	str	r7, [r3, #0x1b0]
+	ldr	r7, =0x1
+	str	r7, [r3, #0x320]
+12:
+	ldr	r7, [r3, #0x324]
+	and	r7, r7, #0x1
+	cmp	r7, #0x1
+	bne	12b
+13:
+	ldr	r7, [r3, #0x4]
+	and	r7, r7, #0x20
+	cmp	r7, #0x20
+	bne	13b
+
+	/* let DDR out of self-refresh */
+	ldr	r7, =0x0
+	str	r7, [r3, #0x30]
+14:
+	ldr	r7, [r3, #0x4]
+	and	r7, r7, #0x30
+	cmp	r7, #0x0
+	bne	14b
+
+15:
+	ldr	r7, [r3, #0x4]
+	and	r7, r7, #0x3
+	cmp	r7, #0x1
+	bne	15b
+
+	imx7_qos_setting
+
+	/* enable port */
+	ldr	r7, =0x1
+	str	r7, [r3, #0x490]
+
+	/* jump to kernel resume */
+	ldr	r1, =0x30270000
+	ldr	r7, [r1]
+
+	mov	pc, r7
+16:
+	/* Configure ocram_epdc */
+	ldr r0, =IOMUXC_GPR_BASE_ADDR
+	ldr r1, =0x4f400005
+	str r1, [r0, #0x4]
+
+	/* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
+	ldr r0, =ANATOP_BASE_ADDR
+	ldr r1, =(0x1 << 30)
+	str r1, [r0, #0x388]
+	str r1, [r0, #0x384]
+
+	ldr r0, =SRC_BASE_ADDR
+	ldr r1, =0x2
+	ldr r2, =0x1000
+	str r1, [r0, r2]
+
+	ldr r0, =DDRC_IPS_BASE_ADDR
+	ldr r1, =0x03040008
+	str r1, [r0]
+	ldr r1, =0x00200038
+	str r1, [r0, #0x64]
+	ldr r1, =0x1
+	str r1, [r0, #0x490]
+	ldr r1, =0x00350001
+	str r1, [r0, #0xd0]
+	ldr r1, =0x00c3000a
+	str r1, [r0, #0xdc]
+	ldr r1, =0x00010000
+	str r1, [r0, #0xe0]
+	ldr r1, =0x00110006
+	str r1, [r0, #0xe4]
+	ldr r1, =0x33f
+	str r1, [r0, #0xf4]
+	ldr r1, =0x0a0e110b
+	str r1, [r0, #0x100]
+	ldr r1, =0x00020211
+	str r1, [r0, #0x104]
+	ldr r1, =0x03060708
+	str r1, [r0, #0x108]
+	ldr r1, =0x00a0500c
+	str r1, [r0, #0x10c]
+	ldr r1, =0x05020307
+	str r1, [r0, #0x110]
+	ldr r1, =0x02020404
+	str r1, [r0, #0x114]
+	ldr r1, =0x02020003
+	str r1, [r0, #0x118]
+	ldr r1, =0x00000202
+	str r1, [r0, #0x11c]
+	ldr r1, =0x00000202
+	str r1, [r0, #0x120]
+	ldr r1, =0x00600018
+	str r1, [r0, #0x180]
+	ldr r1, =0x00e00100
+	str r1, [r0, #0x184]
+	ldr r1, =0x02098205
+	str r1, [r0, #0x190]
+	ldr r1, =0x00060303
+	str r1, [r0, #0x194]
+	ldr r1, =0x80400003
+	str r1, [r0, #0x1a0]
+	ldr r1, =0x00100020
+	str r1, [r0, #0x1a4]
+	ldr r1, =0x80100004
+	str r1, [r0, #0x1a8]
+
+	ldr r1, =0x00000016
+	str r1, [r0, #0x200]
+	ldr r1, =0x00090909
+	str r1, [r0, #0x204]
+	ldr r1, =0x00000f00
+	str r1, [r0, #0x210]
+	ldr r1, =0x08080808
+	str r1, [r0, #0x214]
+	ldr r1, =0x0f0f0808
+	str r1, [r0, #0x218]
+
+	ldr r1, =0x06000600
+	str r1, [r0, #0x240]
+	mov r1, #0x0
+	str r1, [r0, #0x244]
+
+	ldr r0, =SRC_BASE_ADDR
+	mov r1, #0x0
+	ldr r2, =0x1000
+	str r1, [r0, r2]
+
+	ldr r0, =DDRPHY_IPS_BASE_ADDR
+	ldr r1, =0x17421e40
+	str r1, [r0]
+	ldr r1, =0x10210100
+	str r1, [r0, #0x4]
+	ldr r1, =0x00010000
+	str r1, [r0, #0x8]
+	ldr r1, =0x0007080c
+	str r1, [r0, #0x10]
+	imx7d_ddrphy_latency_setting
+	ldr r1, =0x1010007e
+	str r1, [r0, #0xb0]
+	ldr r1, =0x01010000
+	str r1, [r0, #0x1c]
+
+	ldr r2, =ANATOP_BASE_ADDR
+	ldr r3, [r2, #0x800]
+	and r3, r3, #0xFF
+	cmp r3, #0x11
+	bne	17f
+
+	ldr r1, =0x0db60d6e
+	str r1, [r0, #0x9c]
+	b	18f
+17:
+	ldr r1, =0x00000b24
+	str r1, [r0, #0x9c]
+18:
+	ldr r1, =0x06060606
+	str r1, [r0, #0x30]
+	ldr r1, =0x0a0a0a0a
+	str r1, [r0, #0x20]
+	ldr r1, =0x01000008
+	str r1, [r0, #0x50]
+	ldr r1, =0x00000008
+	str r1, [r0, #0x50]
+
+	ldr r1, =0x0000000f
+	str r1, [r0, #0x18]
+	ldr r1, =0x0e487304
+	str r1, [r0, #0xc0]
+	ldr r1, =0x0e4c7304
+	str r1, [r0, #0xc0]
+	ldr r1, =0x0e4c7306
+	str r1, [r0, #0xc0]
+
+wait_zq:
+	ldr r1, [r0, #0xc4]
+	tst r1, #0x1
+	beq wait_zq
+
+	ldr r1, =0x0e487304
+	str r1, [r0, #0xc0]
+
+	ldr r0, =CCM_BASE_ADDR
+	mov r1, #0x0
+	ldr r2, =0x4130
+	str r1, [r0, r2]
+	ldr r0, =IOMUXC_GPR_BASE_ADDR
+	mov r1, #0x178
+	str r1, [r0, #0x20]
+	ldr r0, =CCM_BASE_ADDR
+	mov r1, #0x2
+	ldr r2, =0x4130
+	str r1, [r0, r2]
+
+	ldr r0, =DDRC_IPS_BASE_ADDR
+wait_stat:
+	ldr r1, [r0, #0x4]
+	tst r1, #0x1
+	beq wait_stat
+.endm
+
+.macro imx7_clock_gating
+#ifdef CONFIG_IMX_OPTEE
+	ldr r0, =0x30340024
+	ldr r1, =0x1
+	str r1, [r0]
+#endif
+.endm
+
+.macro imx7_qos_setting
+	ldr r0, =REGS_QOS_BASE
+	ldr r1, =0
+	str r1, [r0, #0]
+
+	ldr r1, =0
+	str r1, [r0, #0x60]
+
+	ldr r0, =REGS_QOS_EPDC
+	ldr r1, =0
+	str r1, [r0, #0]
+
+	ldr r0, =REGS_QOS_PXP0
+	ldr r1, =0
+	str r1, [r0, #0]
+
+	ldr r0, =REGS_QOS_PXP1
+	ldr r1, =0
+	str r1, [r0, #0]
+
+	ldr r0, =REGS_QOS_EPDC
+	ldr r1, =0x0f020f22
+	str r1, [r0, #0xd0]
+	str r1, [r0, #0xe0]
+
+	ldr r0, =REGS_QOS_PXP0
+	ldr r1, =0x1
+	str r1, [r0, #0]
+	ldr r0, =REGS_QOS_PXP1
+	str r1, [r0, #0]
+
+	ldr r0, =REGS_QOS_PXP0
+	ldr r1, =0x0f020222
+	str r1, [r0, #0x50]
+	ldr r0, =REGS_QOS_PXP1
+	str r1, [r0, #0x50]
+
+	ldr r0, =REGS_QOS_PXP0
+	ldr r1, =0x0f020222
+	str r1, [r0, #0x60]
+	ldr r0, =REGS_QOS_PXP1
+	str r1, [r0, #0x60]
+
+	ldr r0, =REGS_QOS_PXP0
+	ldr r1, =0x0f020422
+	str r1, [r0, #0x70]
+	ldr r0, =REGS_QOS_PXP1
+	str r1, [r0, #0x70]
+
+	ldr r0, =IOMUXC_GPR_BASE_ADDR
+	ldr r1, =0xe080
+	str r1, [r0, #0x34]
+.endm
+
+.macro imx7_ddr_setting
+	imx7d_12x12_lpddr3_val_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx7_plugin.S>
diff --git a/board/freescale/mx7d_19x19_ddr3_val/Kconfig b/board/freescale/mx7d_19x19_ddr3_val/Kconfig
new file mode 100644
index 00000000000..52c8c49001a
--- /dev/null
+++ b/board/freescale/mx7d_19x19_ddr3_val/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_MX7D_19X19_DDR3_VAL
+
+config SYS_BOARD
+	default "mx7d_19x19_ddr3_val"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx7d_19x19_ddr3_val"
+
+config SYS_TEXT_BASE
+	default 0x87800000
+endif
diff --git a/board/freescale/mx7d_19x19_ddr3_val/Makefile b/board/freescale/mx7d_19x19_ddr3_val/Makefile
new file mode 100644
index 00000000000..5e48257e15e
--- /dev/null
+++ b/board/freescale/mx7d_19x19_ddr3_val/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx7d_19x19_ddr3_val.o
diff --git a/board/freescale/mx7d_19x19_ddr3_val/imximage.cfg b/board/freescale/mx7d_19x19_ddr3_val/imximage.cfg
new file mode 100644
index 00000000000..b8f40b18c86
--- /dev/null
+++ b/board/freescale/mx7d_19x19_ddr3_val/imximage.cfg
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7d_19x19_ddr3_val/plugin.bin 0x00910000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005
+/* Clear then set bit30 to ensure exit from DDR retention */
+DATA 4 0x30360388 0x40000000
+DATA 4 0x30360384 0x40000000
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x01040001
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0064 0x00400046
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00020083
+DATA 4 0x307a00d4 0x00690000
+DATA 4 0x307a00dc 0x09300004
+DATA 4 0x307a00e0 0x04080000
+DATA 4 0x307a00e4 0x00100004
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x09081109
+DATA 4 0x307a0104 0x0007020d
+DATA 4 0x307a0108 0x03040407
+DATA 4 0x307a010c 0x00002006
+DATA 4 0x307a0110 0x04020205
+DATA 4 0x307a0114 0x03030202
+DATA 4 0x307a0120 0x00000803
+DATA 4 0x307a0180 0x00800020
+DATA 4 0x307a0184 0x02000100
+DATA 4 0x307a0190 0x02098204
+DATA 4 0x307a0194 0x00030303
+DATA 4 0x307a0200 0x00000016
+DATA 4 0x307a0204 0x00080808
+DATA 4 0x307a0210 0x00000f0f
+DATA 4 0x307a0214 0x07070707
+DATA 4 0x307a0218 0x0f070707
+DATA 4 0x307a0240 0x06000604
+DATA 4 0x307a0244 0x00000001
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17420f40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790010 0x00060807
+DATA 4 0x307900b0 0x1010007e
+DATA 4 0x3079009c 0x00000b24
+DATA 4 0x30790020 0x08080808
+DATA 4 0x30790030 0x08080808
+DATA 4 0x30790050 0x01000010
+DATA 4 0x30790050 0x00000010
+
+DATA 4 0x307900c0 0x0e407304
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e447306
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e407304
+
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+DATA 4 0x30790018 0x0000000f
+
+CHECK_BITS_SET 4 0x307a0004 0x1
+
+#endif
diff --git a/board/freescale/mx7d_19x19_ddr3_val/imximage_TO_1_1.cfg b/board/freescale/mx7d_19x19_ddr3_val/imximage_TO_1_1.cfg
new file mode 100644
index 00000000000..a938fcf0f69
--- /dev/null
+++ b/board/freescale/mx7d_19x19_ddr3_val/imximage_TO_1_1.cfg
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7d_19x19_ddr3_val/plugin.bin 0x00910000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x30360070 0x00703021
+DATA 4 0x30360090 0x0
+DATA 4 0x30360070 0x00603021
+CHECK_BITS_SET 4 0x30360070 0x80000000
+DATA 4 0x30389880 0x1
+
+DATA 4 0x30340004 0x4F400005
+/* Clear then set bit30 to ensure exit from DDR retention */
+DATA 4 0x30360388 0x40000000
+DATA 4 0x30360384 0x40000000
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x01040001
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0064 0x00400046
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00020083
+DATA 4 0x307a00d4 0x00690000
+DATA 4 0x307a00dc 0x09300004
+DATA 4 0x307a00e0 0x04080000
+DATA 4 0x307a00e4 0x00100004
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x09081109
+DATA 4 0x307a0104 0x0007020d
+DATA 4 0x307a0108 0x03040407
+DATA 4 0x307a010c 0x00002006
+DATA 4 0x307a0110 0x04020205
+DATA 4 0x307a0114 0x03030202
+DATA 4 0x307a0120 0x00000803
+DATA 4 0x307a0180 0x00800020
+DATA 4 0x307a0184 0x02000100
+DATA 4 0x307a0190 0x02098204
+DATA 4 0x307a0194 0x00030303
+DATA 4 0x307a0200 0x00000016
+DATA 4 0x307a0204 0x00080808
+DATA 4 0x307a0210 0x00000f0f
+DATA 4 0x307a0214 0x07070707
+DATA 4 0x307a0218 0x0f070707
+DATA 4 0x307a0240 0x06000604
+DATA 4 0x307a0244 0x00000001
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17420f40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790010 0x00060807
+DATA 4 0x307900b0 0x1010007e
+DATA 4 0x3079009c 0x00000dee
+DATA 4 0x3079007c 0x18181818
+DATA 4 0x30790080 0x18181818
+DATA 4 0x30790084 0x40401818
+DATA 4 0x30790088 0x00000040
+DATA 4 0x3079006c 0x40404040
+DATA 4 0x30790020 0x08080808
+DATA 4 0x30790030 0x08080808
+DATA 4 0x30790050 0x01000010
+DATA 4 0x30790050 0x00000010
+
+DATA 4 0x307900c0 0x0e407304
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e447306
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e407304
+
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+DATA 4 0x30790018 0x0000000f
+
+CHECK_BITS_SET 4 0x307a0004 0x1
+
+#endif
diff --git a/board/freescale/mx7d_19x19_ddr3_val/mx7d_19x19_ddr3_val.c b/board/freescale/mx7d_19x19_ddr3_val/mx7d_19x19_ddr3_val.c
new file mode 100644
index 00000000000..51927ac0611
--- /dev/null
+++ b/board/freescale/mx7d_19x19_ddr3_val/mx7d_19x19_ddr3_val.c
@@ -0,0 +1,611 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <linux/delay.h>
+#include <common.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../common/pfuze.h"
+#ifdef CONFIG_SYS_I2C_MXC
+#include <i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#endif
+#include <asm/arch/crm_regs.h>
+#include <asm/mach-imx/video.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
+	PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
+#define ENET_PAD_CTRL_MII  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
+
+#define I2C_PAD_CTRL    (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
+	PAD_CTL_DSE_3P3V_49OHM)
+
+#define QSPI_PAD_CTRL	\
+		(PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
+#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
+		.gp = IMX_GPIO_NR(4, 8),
+	},
+	.sda = {
+		.i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
+		.gp = IMX_GPIO_NR(4, 9),
+	},
+};
+
+/* I2C2 */
+struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX7D_PAD_I2C2_SCL__I2C2_SCL | PC,
+		.gpio_mode = MX7D_PAD_I2C2_SCL__GPIO4_IO10 | PC,
+		.gp = IMX_GPIO_NR(4, 10),
+	},
+	.sda = {
+		.i2c_mode = MX7D_PAD_I2C2_SDA__I2C2_SDA | PC,
+		.gpio_mode = MX7D_PAD_I2C2_SDA__GPIO4_IO11 | PC,
+		.gp = IMX_GPIO_NR(4, 11),
+	},
+};
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc1_emmc_pads[] = {
+	MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_ECSPI2_MISO__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_ECSPI2_SS0__SD1_DATA7  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX7D_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	MX7D_PAD_GPIO1_IO12__SD2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	MX7D_PAD_SD2_CD_B__GPIO5_IO9 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	MX7D_PAD_GPIO1_IO13__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	MX7D_PAD_GPIO1_IO14__GPIO1_IO14  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+
+#ifdef CONFIG_VIDEO_MXS
+static iomux_v3_cfg_t const lcd_pads[] = {
+	MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+	MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+
+	MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const pwm_pads[] = {
+	/* Use GPIO for Brightness adjustment, duty cycle = period */
+	MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void do_enable_parallel_lcd(struct display_info_t const *dev)
+{
+	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
+
+	imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
+
+	/* Power up the LCD */
+	gpio_request(IMX_GPIO_NR(3, 4), "lcd_pwr");
+	gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
+
+	/* Set Brightness to high */
+	gpio_request(IMX_GPIO_NR(1, 1), "lcd_backlight");
+	gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
+}
+
+struct display_info_t const displays[] = {{
+	.bus = ELCDIF1_IPS_BASE_ADDR,
+	.addr = 0,
+	.pixfmt = 24,
+	.detect = NULL,
+	.enable	= do_enable_parallel_lcd,
+	.mode	= {
+		.name			= "MCIMX28LCD",
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 29850,
+		.left_margin    = 89,
+		.right_margin   = 164,
+		.upper_margin   = 23,
+		.lower_margin   = 10,
+		.hsync_len      = 10,
+		.vsync_len      = 10,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+#endif
+
+static iomux_v3_cfg_t const per_rst_pads[] = {
+	MX7D_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_FEC_MXC
+static iomux_v3_cfg_t const fec2_pads[] = {
+	MX7D_PAD_GPIO1_IO11__ENET1_MDC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1  | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2  | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_fec2(void)
+{
+	imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
+}
+#endif
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FSL_QSPI
+#ifndef CONFIG_DM_SPI
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+	MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA04__QSPI_A_DQS   | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+
+	MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA12__QSPI_B_DQS   | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+
+};
+#endif
+
+int board_qspi_init(void)
+{
+#ifndef CONFIG_DM_SPI
+	/* Set the iomux */
+	imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
+#endif
+
+	/* Set the clock */
+	set_clk_qspi();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(5, 9)
+#define USDHC3_CD_GPIO	IMX_GPIO_NR(1, 14)
+
+#define USDHC1_PWR_GPIO	IMX_GPIO_NR(5, 2)
+#define USDHC2_PWR_GPIO	IMX_GPIO_NR(5, 11)
+#define USDHC3_PWR_GPIO	IMX_GPIO_NR(6, 11)
+
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+	{USDHC1_BASE_ADDR},
+	{USDHC2_BASE_ADDR, 0, 4},
+	{USDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1; /* Assume uSDHC1 emmc is always present */
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC3_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+int board_mmc_init(struct bd_info *bis)
+{
+	int i;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * mmc0                    USDHC1 (eMMC)
+	 * mmc1                    USDHC2
+	 * mmc2                    USDHC3
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc1_emmc_pads, ARRAY_SIZE(usdhc1_emmc_pads));
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		case 1:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2_pwr");
+			gpio_request(USDHC2_CD_GPIO, "usdhc2_cd");
+			gpio_direction_input(USDHC2_CD_GPIO);
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			break;
+		case 2:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+			gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");
+			gpio_request(USDHC3_CD_GPIO, "usdhc3_cd");
+			gpio_direction_input(USDHC3_CD_GPIO);
+			gpio_direction_output(USDHC3_PWR_GPIO, 1);
+			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return 0;
+			}
+
+			if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
+				printf("Warning: failed to initialize mmc dev %d\n", i);
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+int board_eth_init(struct bd_info *bis)
+{
+	int ret;
+
+	setup_iomux_fec2();
+
+	ret = fecmxc_initialize_multi(bis, 0,
+		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+	if (ret)
+		printf("FEC1 MXC: %s:failed\n", __func__);
+
+	return 0;
+}
+
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+	int ret;
+
+	/* Use 125M anatop REF_CLK for ENET2, clear gpr1[14], gpr1[18]*/
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+		(IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |
+		 IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0);
+
+	ret = set_clk_enet(ENET_125MHZ);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* Enable 1.8V(SEL_1P5_1P8_POS_REG) on
+	   Phy control debug reg 0 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	/* rgmii tx clock delay enable */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#ifndef CONFIG_DM_SPI
+iomux_v3_cfg_t const ecspi1_pads[] = {
+	MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+
+	/* CS0 */
+	MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void setup_spinor(void)
+{
+	imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+					 ARRAY_SIZE(ecspi1_pads));
+	gpio_request(IMX_GPIO_NR(4, 19), "ecspi1_cs");
+	gpio_direction_output(IMX_GPIO_NR(4, 19), 0);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 19)) : -1;
+}
+#endif
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX7
+#ifndef CONFIG_DM_USB
+iomux_v3_cfg_t const usb_otg1_pads[] = {
+	MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usb_otg2_pads[] = {
+	MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, ARRAY_SIZE(usb_otg1_pads));
+	imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, ARRAY_SIZE(usb_otg2_pads));
+}
+#endif
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX7
+#ifndef CONFIG_DM_USB
+	setup_usb();
+#endif
+#endif
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/* Reset peripherals */
+	imx_iomux_v3_setup_multiple_pads(per_rst_pads, ARRAY_SIZE(per_rst_pads));
+
+	gpio_request(IMX_GPIO_NR(1, 3), "per_rst");
+	gpio_direction_output(IMX_GPIO_NR(1, 3), 0);
+	udelay(500);
+	gpio_set_value(IMX_GPIO_NR(1, 3), 1);
+
+#ifdef CONFIG_MXC_SPI
+#ifndef CONFIG_DM_SPI
+	setup_spinor();
+#endif
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"emmc", MAKE_CFGVAL(0x10, 0x22, 0x00, 0x00)},
+	{"sd2", MAKE_CFGVAL(0x10, 0x16, 0x00, 0x00)},
+	{"sd3", MAKE_CFGVAL(0x10, 0x1a, 0x00, 0x00)},
+	{"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},
+	{NULL,   0},
+};
+#endif
+
+#ifdef CONFIG_DM_PMIC
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret, dev_id, rev_id, reg;
+
+	ret = pmic_get("pfuze3000@8", &dev);
+	if (ret == -ENODEV)
+		return 0;
+	if (ret != 0)
+		return ret;
+
+	dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
+	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+	/* disable Low Power Mode during standby mode */
+	reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
+	reg |= 0x1;
+	pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
+
+	/* SW1A/1B mode set to APS/APS */
+	reg = 0x8;
+	pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg);
+	pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
+
+	/* SW1A/1B standby voltage set to 0.975V */
+	reg = 0xb;
+	pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg);
+	pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
+
+	/* set SW1B normal voltage to 0.975V */
+	reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
+	reg &= ~0x1f;
+	reg |= PFUZE3000_SW1AB_SETP(9750);
+	pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg);
+
+	return 0;
+}
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return get_cpu_rev();
+}
+
+int checkboard(void)
+{
+	puts("Board: MX7D 19x19 DDR3 VAL\n");
+
+	return 0;
+}
diff --git a/board/freescale/mx7d_19x19_ddr3_val/plugin.S b/board/freescale/mx7d_19x19_ddr3_val/plugin.S
new file mode 100644
index 00000000000..26914e41eba
--- /dev/null
+++ b/board/freescale/mx7d_19x19_ddr3_val/plugin.S
@@ -0,0 +1,227 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx7d_ddrphy_latency_setting
+	ldr r2, =ANATOP_BASE_ADDR
+	ldr r3, [r2, #0x800]
+	and r3, r3, #0xFF
+	cmp r3, #0x11
+	bne NO_DELAY
+
+	/*TO 1.1*/
+	ldr r1, =0x00000dee
+	str r1, [r0, #0x9c]
+	ldr r1, =0x18181818
+	str r1, [r0, #0x7c]
+	ldr r1, =0x18181818
+	str r1, [r0, #0x80]
+	ldr r1, =0x40401818
+	str r1, [r0, #0x84]
+	ldr r1, =0x00000040
+	str r1, [r0, #0x88]
+	ldr r1, =0x40404040
+	str r1, [r0, #0x6c]
+	b TUNE_END
+
+NO_DELAY:
+	/*TO 1.0*/
+	ldr r1, =0x00000b24
+	str r1, [r0, #0x9c]
+
+TUNE_END:
+.endm
+
+.macro imx7d_ddr_freq_setting
+	ldr r2, =ANATOP_BASE_ADDR
+	ldr r3, [r2, #0x800]
+	and r3, r3, #0xFF
+	cmp r3, #0x11
+	bne FREQ_DEFAULT_533
+
+	/* Change to 400Mhz for TO1.1 */
+	ldr r0, =ANATOP_BASE_ADDR
+	ldr r1, =0x70
+	ldr r2, =0x00703021
+	str r2, [r0, r1]
+	ldr r1, =0x90
+	ldr r2, =0x0
+	str r2, [r0, r1]
+	ldr r1, =0x70
+	ldr r2, =0x00603021
+	str r2, [r0, r1]
+
+	ldr r3, =0x80000000
+wait_lock:
+	ldr r2, [r0, r1]
+	and r2, r3
+	cmp r2, r3
+	bne wait_lock
+
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0x9880
+	ldr r2, =0x1
+	str r2, [r0, r1]
+
+FREQ_DEFAULT_533:
+.endm
+
+.macro imx7d_19x19_ddr3_val_ddr_setting
+	imx7d_ddr_freq_setting
+
+	/* Configure ocram_epdc */
+	ldr r0, =IOMUXC_GPR_BASE_ADDR
+	ldr r1, =0x4f400005
+	str r1, [r0, #0x4]
+
+	/* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
+	ldr r0, =ANATOP_BASE_ADDR
+	ldr r1, =(0x1 << 30)
+	str r1, [r0, #0x388]
+	str r1, [r0, #0x384]
+
+	ldr r0, =SRC_BASE_ADDR
+	ldr r1, =0x2
+	ldr r2, =0x1000
+	str r1, [r0, r2]
+
+	ldr r0, =DDRC_IPS_BASE_ADDR
+	ldr r1, =0x01040001
+	str r1, [r0]
+	ldr r1, =0x80400003
+	str r1, [r0, #0x1a0]
+	ldr r1, =0x00100020
+	str r1, [r0, #0x1a4]
+	ldr r1, =0x80100004
+	str r1, [r0, #0x1a8]
+	ldr r1, =0x00400046
+	str r1, [r0, #0x64]
+	ldr r1, =0x1
+	str r1, [r0, #0x490]
+	ldr r1, =0x00020001
+	str r1, [r0, #0xd0]
+	ldr r1, =0x00690000
+	str r1, [r0, #0xd4]
+	ldr r1, =0x09300004
+	str r1, [r0, #0xdc]
+	ldr r1, =0x04080000
+	str r1, [r0, #0xe0]
+	ldr r1, =0x00100004
+	str r1, [r0, #0xe4]
+	ldr r1, =0x33f
+	str r1, [r0, #0xf4]
+	ldr r1, =0x09081109
+	str r1, [r0, #0x100]
+	ldr r1, =0x0007020d
+	str r1, [r0, #0x104]
+	ldr r1, =0x03040407
+	str r1, [r0, #0x108]
+	ldr r1, =0x00002006
+	str r1, [r0, #0x10c]
+	ldr r1, =0x04020205
+	str r1, [r0, #0x110]
+	ldr r1, =0x03030202
+	str r1, [r0, #0x114]
+	ldr r1, =0x00000803
+	str r1, [r0, #0x120]
+	ldr r1, =0x00800020
+	str r1, [r0, #0x180]
+	ldr r1, =0x02000100
+	str r1, [r0, #0x184]
+	ldr r1, =0x02098204
+	str r1, [r0, #0x190]
+	ldr r1, =0x00030303
+	str r1, [r0, #0x194]
+
+	ldr r1, =0x00000016
+	str r1, [r0, #0x200]
+	ldr r1, =0x00080808
+	str r1, [r0, #0x204]
+	ldr r1, =0x00000f0f
+	str r1, [r0, #0x210]
+	ldr r1, =0x07070707
+	str r1, [r0, #0x214]
+	ldr r1, =0x0f070707
+	str r1, [r0, #0x218]
+
+	ldr r1, =0x06000604
+	str r1, [r0, #0x240]
+	ldr r1, =0x00000001
+	str r1, [r0, #0x244]
+
+	ldr r0, =SRC_BASE_ADDR
+	mov r1, #0x0
+	ldr r2, =0x1000
+	str r1, [r0, r2]
+
+	ldr r0, =DDRPHY_IPS_BASE_ADDR
+	ldr r1, =0x17420f40
+	str r1, [r0]
+	ldr r1, =0x10210100
+	str r1, [r0, #0x4]
+	ldr r1, =0x00060807
+	str r1, [r0, #0x10]
+	ldr r1, =0x1010007e
+	str r1, [r0, #0xb0]
+	imx7d_ddrphy_latency_setting
+	ldr r1, =0x08080808
+	str r1, [r0, #0x20]
+	ldr r1, =0x08080808
+	str r1, [r0, #0x30]
+	ldr r1, =0x01000010
+	str r1, [r0, #0x50]
+
+	ldr r1, =0x0e407304
+	str r1, [r0, #0xc0]
+	ldr r1, =0x0e447304
+	str r1, [r0, #0xc0]
+	ldr r1, =0x0e447306
+	str r1, [r0, #0xc0]
+
+wait_zq:
+	ldr r1, [r0, #0xc4]
+	tst r1, #0x1
+	beq wait_zq
+
+	ldr r1, =0x0e407304
+	str r1, [r0, #0xc0]
+
+	ldr r0, =CCM_BASE_ADDR
+	mov r1, #0x0
+	ldr r2, =0x4130
+	str r1, [r0, r2]
+	ldr r0, =IOMUXC_GPR_BASE_ADDR
+	mov r1, #0x178
+	str r1, [r0, #0x20]
+	ldr r0, =CCM_BASE_ADDR
+	mov r1, #0x2
+	ldr r2, =0x4130
+	str r1, [r0, r2]
+	ldr r0, =DDRPHY_IPS_BASE_ADDR
+	ldr r1, =0x0000000f
+	str r1, [r0, #0x18]
+
+	ldr r0, =DDRC_IPS_BASE_ADDR
+wait_stat:
+	ldr r1, [r0, #0x4]
+	tst r1, #0x1
+	beq wait_stat
+.endm
+
+.macro imx7_clock_gating
+.endm
+
+.macro imx7_qos_setting
+.endm
+
+.macro imx7_ddr_setting
+	imx7d_19x19_ddr3_val_ddr_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx7_plugin.S>
diff --git a/board/freescale/mx7d_19x19_lpddr3_val/Kconfig b/board/freescale/mx7d_19x19_lpddr3_val/Kconfig
new file mode 100644
index 00000000000..a5db2d220da
--- /dev/null
+++ b/board/freescale/mx7d_19x19_lpddr3_val/Kconfig
@@ -0,0 +1,20 @@
+if TARGET_MX7D_19X19_LPDDR3_VAL || TARGET_MX7D_19X19_LPDDR2_VAL
+
+config SYS_BOARD
+	default "mx7d_19x19_lpddr3_val"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx7d_19x19_lpddr3_val"
+
+config SYS_TEXT_BASE
+	default 0x87800000
+
+config NOR
+	bool "Support for NOR flash"
+	help
+	  The i.MX SoC supports having a NOR flash connected to the WEIM.
+	  Need to set this for NOR_BOOT.
+endif
diff --git a/board/freescale/mx7d_19x19_lpddr3_val/Makefile b/board/freescale/mx7d_19x19_lpddr3_val/Makefile
new file mode 100644
index 00000000000..48148c17717
--- /dev/null
+++ b/board/freescale/mx7d_19x19_lpddr3_val/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx7d_19x19_lpddr3_val.o
diff --git a/board/freescale/mx7d_19x19_lpddr3_val/imximage.cfg b/board/freescale/mx7d_19x19_lpddr3_val/imximage.cfg
new file mode 100644
index 00000000000..2ad6b679841
--- /dev/null
+++ b/board/freescale/mx7d_19x19_lpddr3_val/imximage.cfg
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7d_19x19_lpddr3_val/plugin.bin 0x00910000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x03040008
+DATA 4 0x307a0064 0x00200038
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00350001
+DATA 4 0x307a00dc 0x00c3000a
+DATA 4 0x307a00e0 0x00010000
+DATA 4 0x307a00e4 0x00110006
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x0a0e110b
+DATA 4 0x307a0104 0x00020211
+DATA 4 0x307a0108 0x03060708
+DATA 4 0x307a010c 0x00a0500c
+DATA 4 0x307a0110 0x05020307
+DATA 4 0x307a0114 0x02020404
+DATA 4 0x307a0118 0x02020003
+DATA 4 0x307a011c 0x00000202
+DATA 4 0x307a0120 0x00000202
+
+DATA 4 0x307a0180 0x00600018
+DATA 4 0x307a0184 0x00e00100
+DATA 4 0x307a0190 0x02098205
+DATA 4 0x307a0194 0x00060303
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+
+DATA 4 0x307a0200 0x00000016
+DATA 4 0x307a0204 0x00090909
+DATA 4 0x307a0210 0x00000f00
+DATA 4 0x307a0214 0x08080808
+DATA 4 0x307a0218 0x0f0f0808
+
+DATA 4 0x307a0240 0x06000600
+DATA 4 0x307a0244 0x00000000
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17421e40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790008 0x00010000
+DATA 4 0x30790010 0x0007080c
+DATA 4 0x307900b0 0x1010007e
+
+DATA 4 0x3079001C 0x01010000
+DATA 4 0x3079009c 0x00000b24
+
+DATA 4 0x30790030 0x06060606
+DATA 4 0x30790020 0x0a0a0a0a
+DATA 4 0x30790050 0x01000008
+DATA 4 0x30790050 0x00000008
+DATA 4 0x30790018 0x0000000f
+DATA 4 0x307900c0 0x0e487304
+DATA 4 0x307900c0 0x0e4c7304
+DATA 4 0x307900c0 0x0e4c7306
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e487304
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+
+CHECK_BITS_SET 4 0x307a0004 0x1
+#endif
diff --git a/board/freescale/mx7d_19x19_lpddr3_val/imximage_TO_1_1.cfg b/board/freescale/mx7d_19x19_lpddr3_val/imximage_TO_1_1.cfg
new file mode 100644
index 00000000000..90c689a89de
--- /dev/null
+++ b/board/freescale/mx7d_19x19_lpddr3_val/imximage_TO_1_1.cfg
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7d_19x19_lpddr3_val/plugin.bin 0x00910000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x03040008
+DATA 4 0x307a0064 0x00200038
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00350001
+DATA 4 0x307a00dc 0x00c3000a
+DATA 4 0x307a00e0 0x00010000
+DATA 4 0x307a00e4 0x00110006
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x0a0e110b
+DATA 4 0x307a0104 0x00020211
+DATA 4 0x307a0108 0x03060708
+DATA 4 0x307a010c 0x00a0500c
+DATA 4 0x307a0110 0x05020307
+DATA 4 0x307a0114 0x02020404
+DATA 4 0x307a0118 0x02020003
+DATA 4 0x307a011c 0x00000202
+DATA 4 0x307a0120 0x00000202
+
+DATA 4 0x307a0180 0x00600018
+DATA 4 0x307a0184 0x00e00100
+DATA 4 0x307a0190 0x02098205
+DATA 4 0x307a0194 0x00060303
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+
+DATA 4 0x307a0200 0x00000016
+DATA 4 0x307a0204 0x00090909
+DATA 4 0x307a0210 0x00000f00
+DATA 4 0x307a0214 0x08080808
+DATA 4 0x307a0218 0x0f0f0808
+
+DATA 4 0x307a0240 0x06000601
+DATA 4 0x307a0244 0x00000000
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17421e40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790008 0x00010000
+DATA 4 0x30790010 0x0007080c
+DATA 4 0x3079007c 0x1c1c1c1c
+DATA 4 0x30790080 0x1c1c1c1c
+DATA 4 0x30790084 0x30301c1c
+DATA 4 0x30790088 0x00000030
+DATA 4 0x3079006c 0x30303030
+DATA 4 0x307900b0 0x1010007e
+
+DATA 4 0x3079001C 0x01010000
+DATA 4 0x3079009c 0x0db60d6e
+
+DATA 4 0x30790030 0x06060606
+DATA 4 0x30790020 0x0a0a0a0a
+DATA 4 0x30790050 0x01000008
+DATA 4 0x30790050 0x00000008
+DATA 4 0x30790018 0x0000000f
+DATA 4 0x307900c0 0x1e487304
+DATA 4 0x307900c0 0x1e487304
+DATA 4 0x307900c0 0x1e487306
+DATA 4 0x307900c0 0x1e4c7304
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x1e487304
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+
+CHECK_BITS_SET 4 0x307a0004 0x1
+#endif
diff --git a/board/freescale/mx7d_19x19_lpddr3_val/imximage_lpddr2.cfg b/board/freescale/mx7d_19x19_lpddr3_val/imximage_lpddr2.cfg
new file mode 100644
index 00000000000..970df054be6
--- /dev/null
+++ b/board/freescale/mx7d_19x19_lpddr3_val/imximage_lpddr2.cfg
@@ -0,0 +1,118 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_SYS_BOOT_QSPI
+BOOT_FROM	qspi
+#elif defined(CONFIG_SYS_BOOT_EIMNOR)
+BOOT_FROM	nor
+#else
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7d_19x19_lpddr3_val/plugin.bin 0x00910000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x03020004
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0064 0x00200023
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00350001
+DATA 4 0x307a00d8 0x00001105
+DATA 4 0x307a00dc 0x00c20006
+DATA 4 0x307a00e0 0x00020000
+DATA 4 0x307a00e4 0x00110006
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x080e110b
+DATA 4 0x307a0104 0x00020211
+DATA 4 0x307a0108 0x02040706
+DATA 4 0x307a010c 0x00504000
+DATA 4 0x307a0110 0x05010307
+DATA 4 0x307a0114 0x02020404
+DATA 4 0x307a0118 0x02020003
+DATA 4 0x307a011c 0x00000202
+DATA 4 0x307a0120 0x00000202
+
+DATA 4 0x307a0180 0x00600018
+DATA 4 0x307a0184 0x00e00100
+DATA 4 0x307a0190 0x02098203
+DATA 4 0x307a0194 0x00060303
+
+DATA 4 0x307a0200 0x00000015
+DATA 4 0x307a0204 0x00161616
+DATA 4 0x307a0210 0x00000f0f
+DATA 4 0x307a0214 0x04040404
+DATA 4 0x307a0218 0x0f0f0404
+
+DATA 4 0x307a0240 0x06000600
+DATA 4 0x307a0244 0x00000000
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17421640
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790008 0x00010000
+DATA 4 0x30790010 0x00050408
+DATA 4 0x307900b0 0x1010007e
+
+DATA 4 0x3079001C 0x01010000
+DATA 4 0x3079009C 0x00000d6e
+DATA 4 0x30790018 0x0000000f
+
+DATA 4 0x30790030 0x06060606
+DATA 4 0x30790020 0x0a0a0a0a
+DATA 4 0x30790050 0x01000008
+DATA 4 0x30790050 0x00000008
+DATA 4 0x307900c0 0x0e487304
+DATA 4 0x307900c0 0x0e4c7304
+DATA 4 0x307900c0 0x0e4c7306
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e4c7304
+DATA 4 0x307900c0 0x0e487304
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x000001f8
+DATA 4 0x30384130 0x00000002
+
+CHECK_BITS_SET 4 0x307a0004 0x1
+#endif
diff --git a/board/freescale/mx7d_19x19_lpddr3_val/imximage_lpddr2_TO_1_1.cfg b/board/freescale/mx7d_19x19_lpddr3_val/imximage_lpddr2_TO_1_1.cfg
new file mode 100644
index 00000000000..06953b2b5d3
--- /dev/null
+++ b/board/freescale/mx7d_19x19_lpddr3_val/imximage_lpddr2_TO_1_1.cfg
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_SYS_BOOT_QSPI
+BOOT_FROM	qspi
+#elif defined(CONFIG_SYS_BOOT_EIMNOR)
+BOOT_FROM	nor
+#else
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7d_19x19_lpddr3_val/plugin.bin 0x00910000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x03020004
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0064 0x00200023
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00350001
+DATA 4 0x307a00d8 0x00001105
+DATA 4 0x307a00dc 0x00c20006
+DATA 4 0x307a00e0 0x00020000
+DATA 4 0x307a00e4 0x00110006
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x080e110b
+DATA 4 0x307a0104 0x00020211
+DATA 4 0x307a0108 0x02040706
+DATA 4 0x307a010c 0x00504000
+DATA 4 0x307a0110 0x05010307
+DATA 4 0x307a0114 0x02020404
+DATA 4 0x307a0118 0x02020003
+DATA 4 0x307a011c 0x00000202
+DATA 4 0x307a0120 0x00000202
+
+DATA 4 0x307a0180 0x00600018
+DATA 4 0x307a0184 0x00e00100
+DATA 4 0x307a0190 0x02098203
+DATA 4 0x307a0194 0x00060303
+
+DATA 4 0x307a0200 0x00000015
+DATA 4 0x307a0204 0x00161616
+DATA 4 0x307a0210 0x00000f0f
+DATA 4 0x307a0214 0x04040404
+DATA 4 0x307a0218 0x0f0f0404
+
+DATA 4 0x307a0240 0x06000600
+DATA 4 0x307a0244 0x00000000
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17421640
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790008 0x00010000
+DATA 4 0x30790010 0x00050408
+DATA 4 0x307900b0 0x1010007e
+
+DATA 4 0x3079001C 0x01010000
+DATA 4 0x3079009C 0x00000dee
+DATA 4 0x3079007c 0x08080808
+DATA 4 0x30790080 0x08080808
+DATA 4 0x30790084 0x0a0a0808
+DATA 4 0x30790088 0x0000000a
+DATA 4 0x3079006c 0x0a0a0a0a
+DATA 4 0x30790018 0x0000000f
+
+DATA 4 0x30790030 0x06060606
+DATA 4 0x30790020 0x0a0a0a0a
+DATA 4 0x30790050 0x01000008
+DATA 4 0x30790050 0x00000008
+DATA 4 0x307900c0 0x0e487304
+DATA 4 0x307900c0 0x0e4c7304
+DATA 4 0x307900c0 0x0e4c7306
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e4c7304
+DATA 4 0x307900c0 0x0e487304
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x000001f8
+DATA 4 0x30384130 0x00000002
+
+CHECK_BITS_SET 4 0x307a0004 0x1
+#endif
diff --git a/board/freescale/mx7d_19x19_lpddr3_val/mx7d_19x19_lpddr3_val.c b/board/freescale/mx7d_19x19_lpddr3_val/mx7d_19x19_lpddr3_val.c
new file mode 100644
index 00000000000..d01b33d118e
--- /dev/null
+++ b/board/freescale/mx7d_19x19_lpddr3_val/mx7d_19x19_lpddr3_val.c
@@ -0,0 +1,603 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <linux/delay.h>
+#include <common.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../common/pfuze.h"
+#ifdef CONFIG_SYS_I2C_MXC
+#include <i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#endif
+#include <asm/arch/crm_regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
+	PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
+#define ENET_PAD_CTRL_MII  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
+
+#define I2C_PAD_CTRL    (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
+
+#define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
+	PAD_CTL_DSE_3P3V_49OHM)
+
+#define QSPI_PAD_CTRL	\
+		(PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
+#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+
+#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
+
+#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
+
+#define WEIM_NOR_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | \
+	PAD_CTL_PUS_PU100KOHM)
+
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
+		.gp = IMX_GPIO_NR(4, 8),
+	},
+	.sda = {
+		.i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
+		.gp = IMX_GPIO_NR(4, 9),
+	},
+};
+
+/* I2C2 */
+struct i2c_pads_info i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode = MX7D_PAD_I2C2_SCL__I2C2_SCL | PC,
+		.gpio_mode = MX7D_PAD_I2C2_SCL__GPIO4_IO10 | PC,
+		.gp = IMX_GPIO_NR(4, 10),
+	},
+	.sda = {
+		.i2c_mode = MX7D_PAD_I2C2_SDA__I2C2_SDA | PC,
+		.gpio_mode = MX7D_PAD_I2C2_SDA__GPIO4_IO11 | PC,
+		.gp = IMX_GPIO_NR(4, 11),
+	},
+};
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	MX7D_PAD_GPIO1_IO08__SD1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	MX7D_PAD_SD1_CD_B__GPIO5_IO0    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+#ifdef CONFIG_MTD_NOR_FLASH
+static iomux_v3_cfg_t const eimnor_pads[] = {
+	MX7D_PAD_LCD_DATA00__EIM_DATA0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_LCD_DATA01__EIM_DATA1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_LCD_DATA02__EIM_DATA2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_LCD_DATA03__EIM_DATA3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_LCD_DATA04__EIM_DATA4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_LCD_DATA05__EIM_DATA5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_LCD_DATA06__EIM_DATA6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_LCD_DATA07__EIM_DATA7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_LCD_DATA08__EIM_DATA8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_LCD_DATA09__EIM_DATA9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_LCD_DATA10__EIM_DATA10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_LCD_DATA11__EIM_DATA11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_LCD_DATA12__EIM_DATA12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_LCD_DATA13__EIM_DATA13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_LCD_DATA14__EIM_DATA14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_LCD_DATA15__EIM_DATA15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+
+	MX7D_PAD_EPDC_DATA00__EIM_AD0   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA01__EIM_AD1   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA02__EIM_AD2   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA03__EIM_AD3   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA04__EIM_AD4   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA05__EIM_AD5   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA06__EIM_AD6   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA07__EIM_AD7   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_BDR1__EIM_AD8     | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_PWR_COM__EIM_AD9  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCLK__EIM_AD10   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_SDLE__EIM_AD11    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_SDOE__EIM_AD12    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_SDSHR__EIM_AD13   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCE0__EIM_AD14   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCE1__EIM_AD15   | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_GDOE__EIM_ADDR19  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_GDRL__EIM_ADDR20  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_GDSP__EIM_ADDR21  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_BDR0__EIM_ADDR22  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_LCD_DATA20__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_LCD_DATA21__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_LCD_DATA22__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+
+	MX7D_PAD_EPDC_DATA08__EIM_OE    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA09__EIM_RW    | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA10__EIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA12__EIM_LBA_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA13__EIM_WAIT  | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
+};
+
+static void eimnor_cs_setup(void)
+{
+	writel(0x00000120, WEIM_IPS_BASE_ADDR + 0x090);
+	writel(0x00210081, WEIM_IPS_BASE_ADDR + 0x000);
+	writel(0x00000001, WEIM_IPS_BASE_ADDR + 0x004);
+	writel(0x0e020000, WEIM_IPS_BASE_ADDR + 0x008);
+	writel(0x00000000, WEIM_IPS_BASE_ADDR + 0x00c);
+	writel(0x0704a040, WEIM_IPS_BASE_ADDR + 0x010);
+}
+
+static void setup_eimnor(void)
+{
+	imx_iomux_v3_setup_multiple_pads(eimnor_pads,
+			ARRAY_SIZE(eimnor_pads));
+
+	eimnor_cs_setup();
+}
+#endif
+
+static iomux_v3_cfg_t const per_rst_pads[] = {
+	MX7D_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_FEC_MXC
+static iomux_v3_cfg_t const fec2_pads[] = {
+	MX7D_PAD_GPIO1_IO11__ENET1_MDC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1  | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2  | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_fec2(void)
+{
+	imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
+}
+#endif
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FSL_QSPI
+#ifndef CONFIG_DM_SPI
+static iomux_v3_cfg_t const quadspi_pads[] = {
+	MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA04__QSPI_A_DQS   | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+
+	MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA12__QSPI_B_DQS   | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
+
+};
+#endif
+
+int board_qspi_init(void)
+{
+#ifndef CONFIG_DM_SPI
+	/* Set the iomux */
+	imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
+#endif
+
+	/* Set the clock */
+	set_clk_qspi();
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t const gpmi_pads[] = {
+	MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_CLK__NAND_CLE	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_CMD__NAND_ALE	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_STROBE__NAND_RE_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SD3_RESET_B__NAND_WE_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_MCLK__NAND_WP_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_TX_SYNC__NAND_DQS	| MUX_PAD_CTRL(NAND_PAD_CTRL),
+	MX7D_PAD_SAI1_TX_DATA__NAND_READY_B	| MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
+};
+
+static void setup_gpmi_nand(void)
+{
+	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+
+	/*
+	 * NAND_USDHC_BUS_CLK is set in rom
+	 */
+
+	set_clk_nand();
+
+	/*
+	 * APBH clock root is set in init_esdhc, USDHC3_CLK.
+	 * There is no clk gate for APBHDMA.
+	 * No touch here.
+	 */
+}
+#endif
+
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(5, 0)
+#define USDHC1_PWR_GPIO	IMX_GPIO_NR(5, 2)
+
+
+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC1_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
+			gpio_direction_input(USDHC1_CD_GPIO);
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+			}
+
+			ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+			if (ret) {
+				printf("Warning: failed to initialize mmc dev %d\n", i);
+				return ret;
+			}
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+int board_eth_init(struct bd_info *bis)
+{
+	int ret;
+
+	setup_iomux_fec2();
+
+	ret = fecmxc_initialize_multi(bis, 0,
+		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+	if (ret)
+		printf("FEC1 MXC: %s:failed\n", __func__);
+
+	return 0;
+}
+
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+	int ret;
+
+	/* Use 125M anatop REF_CLK for ENET2, clear gpr1[14], gpr1[18]*/
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+		(IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |
+		 IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0);
+
+	ret = set_clk_enet(ENET_125MHZ);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+
+int board_phy_config(struct phy_device *phydev)
+{
+	/* Enable 1.8V(SEL_1P5_1P8_POS_REG) on
+	   Phy control debug reg 0 */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	/* rgmii tx clock delay enable */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#ifndef CONFIG_DM_SPI
+iomux_v3_cfg_t const ecspi1_pads[] = {
+	MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK   | MUX_PAD_CTRL(SPI_PAD_CTRL),
+
+	/* CS0 */
+	MX7D_PAD_UART3_CTS_B__GPIO4_IO7   | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+void setup_spinor(void)
+{
+	imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+					 ARRAY_SIZE(ecspi1_pads));
+	gpio_direction_output(IMX_GPIO_NR(4, 7), 0);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 7)) : -1;
+}
+#endif
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX7
+#ifndef CONFIG_DM_USB
+
+iomux_v3_cfg_t const usb_otg1_pads[] = {
+	MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usb_otg2_pads[] = {
+	MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, ARRAY_SIZE(usb_otg1_pads));
+	imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, ARRAY_SIZE(usb_otg2_pads));
+}
+#endif
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX7
+#ifndef CONFIG_DM_USB
+	setup_usb();
+#endif
+#endif
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/* Reset peripherals */
+	imx_iomux_v3_setup_multiple_pads(per_rst_pads, ARRAY_SIZE(per_rst_pads));
+
+	gpio_request(IMX_GPIO_NR(1, 3), "per rst");
+	gpio_direction_output(IMX_GPIO_NR(1, 3) , 0);
+	udelay(500);
+	gpio_set_value(IMX_GPIO_NR(1, 3), 1);
+
+#ifdef CONFIG_MXC_SPI
+#ifndef CONFIG_DM_SPI
+	setup_spinor();
+#endif
+#endif
+
+#ifdef CONFIG_MTD_NOR_FLASH
+	setup_eimnor();
+#endif
+
+#ifdef CONFIG_NAND_MXS
+	setup_gpmi_nand();
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd1", MAKE_CFGVAL(0x10, 0x12, 0x00, 0x00)},
+	{"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},
+	{NULL,   0},
+};
+#endif
+
+#ifdef CONFIG_DM_PMIC
+int power_init_board(void)
+{
+	struct udevice *dev;
+	int ret, dev_id, rev_id, reg;
+
+	ret = pmic_get("pfuze3000@8", &dev);
+	if (ret == -ENODEV)
+		return 0;
+	if (ret != 0)
+		return ret;
+
+	dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
+	printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+	/* disable Low Power Mode during standby mode */
+	reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
+	reg |= 0x1;
+	pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
+
+	/* SW1A/1B mode set to APS/APS */
+	reg = 0x8;
+	pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg);
+	pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
+
+	/* SW1A/1B standby voltage set to 0.975V */
+	reg = 0xb;
+	pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg);
+	pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
+
+	/* set SW1B normal voltage to 0.975V */
+	reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
+	reg &= ~0x1f;
+	reg |= PFUZE3000_SW1AB_SETP(9750);
+	pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg);
+
+	return 0;
+}
+#endif
+
+int board_late_init(void)
+{
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
+
+	return 0;
+}
+
+u32 get_board_rev(void)
+{
+	return get_cpu_rev();
+}
+
+int checkboard(void)
+{
+#ifdef CONFIG_TARGET_MX7D_19X19_LPDDR2_VAL
+	puts("Board: MX7D 19x19 LPDDR2 VAL\n");
+#else
+	puts("Board: MX7D 19x19 LPDDR3 VAL\n");
+#endif
+	return 0;
+}
diff --git a/board/freescale/mx7d_19x19_lpddr3_val/plugin.S b/board/freescale/mx7d_19x19_lpddr3_val/plugin.S
new file mode 100644
index 00000000000..29d76d5daf1
--- /dev/null
+++ b/board/freescale/mx7d_19x19_lpddr3_val/plugin.S
@@ -0,0 +1,378 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx7d_ddrphy_lpddr3_latency_setting
+	ldr r2, =ANATOP_BASE_ADDR
+	ldr r3, [r2, #0x800]
+	and r3, r3, #0xFF
+	cmp r3, #0x11
+	bne TUNE_END
+
+	/*TO 1.1*/
+	ldr r1, =0x1c1c1c1c
+	str r1, [r0, #0x7c]
+	ldr r1, =0x1c1c1c1c
+	str r1, [r0, #0x80]
+	ldr r1, =0x30301c1c
+	str r1, [r0, #0x84]
+	ldr r1, =0x00000030
+	str r1, [r0, #0x88]
+	ldr r1, =0x30303030
+	str r1, [r0, #0x6c]
+
+TUNE_END:
+.endm
+
+.macro imx7d_ddrphy_lpddr2_latency_setting
+	ldr r2, =ANATOP_BASE_ADDR
+	ldr r3, [r2, #0x800]
+	and r3, r3, #0xFF
+	cmp r3, #0x11
+	bne NO_DELAY
+
+	/*TO 1.1*/
+	ldr r1, =0x00000dee
+	str r1, [r0, #0x9c]
+	ldr r1, =0x08080808
+	str r1, [r0, #0x7c]
+	ldr r1, =0x08080808
+	str r1, [r0, #0x80]
+	ldr r1, =0x0a0a0808
+	str r1, [r0, #0x84]
+	ldr r1, =0x0000000a
+	str r1, [r0, #0x88]
+	ldr r1, =0x0a0a0a0a
+	str r1, [r0, #0x6c]
+	b TUNE_END
+
+NO_DELAY:
+	/*TO 1.0*/
+	ldr r1, =0x00000d6e
+	str r1, [r0, #0x9c]
+
+TUNE_END:
+.endm
+
+.macro imx7d_19x19_lpddr3_val_setting
+	/* Configure ocram_epdc */
+	ldr r0, =IOMUXC_GPR_BASE_ADDR
+	ldr r1, =0x4f400005
+	str r1, [r0, #0x4]
+
+	ldr r0, =SRC_BASE_ADDR
+	ldr r1, =0x2
+	ldr r2, =0x1000
+	str r1, [r0, r2]
+
+	ldr r0, =DDRC_IPS_BASE_ADDR
+	ldr r1, =0x03040008
+	str r1, [r0]
+	ldr r1, =0x00200038
+	str r1, [r0, #0x64]
+	ldr r1, =0x1
+	str r1, [r0, #0x490]
+	ldr r1, =0x00350001
+	str r1, [r0, #0xd0]
+	ldr r1, =0x00c3000a
+	str r1, [r0, #0xdc]
+	ldr r1, =0x00010000
+	str r1, [r0, #0xe0]
+	ldr r1, =0x00110006
+	str r1, [r0, #0xe4]
+	ldr r1, =0x33f
+	str r1, [r0, #0xf4]
+	ldr r1, =0x0a0e110b
+	str r1, [r0, #0x100]
+	ldr r1, =0x00020211
+	str r1, [r0, #0x104]
+	ldr r1, =0x03060708
+	str r1, [r0, #0x108]
+	ldr r1, =0x00a0500c
+	str r1, [r0, #0x10c]
+	ldr r1, =0x05020307
+	str r1, [r0, #0x110]
+	ldr r1, =0x02020404
+	str r1, [r0, #0x114]
+	ldr r1, =0x02020003
+	str r1, [r0, #0x118]
+	ldr r1, =0x00000202
+	str r1, [r0, #0x11c]
+	ldr r1, =0x00000202
+	str r1, [r0, #0x120]
+	ldr r1, =0x00600018
+	str r1, [r0, #0x180]
+	ldr r1, =0x00e00100
+	str r1, [r0, #0x184]
+	ldr r1, =0x02098205
+	str r1, [r0, #0x190]
+	ldr r1, =0x00060303
+	str r1, [r0, #0x194]
+	ldr r1, =0x80400003
+	str r1, [r0, #0x1a0]
+	ldr r1, =0x00100020
+	str r1, [r0, #0x1a4]
+	ldr r1, =0x80100004
+	str r1, [r0, #0x1a8]
+
+	ldr r1, =0x00000016
+	str r1, [r0, #0x200]
+	ldr r1, =0x00090909
+	str r1, [r0, #0x204]
+	ldr r1, =0x00000f00
+	str r1, [r0, #0x210]
+	ldr r1, =0x08080808
+	str r1, [r0, #0x214]
+	ldr r1, =0x0f0f0808
+	str r1, [r0, #0x218]
+
+	ldr r1, =0x06000600
+	str r1, [r0, #0x240]
+	mov r1, #0x0
+	str r1, [r0, #0x244]
+
+	ldr r0, =SRC_BASE_ADDR
+	mov r1, #0x0
+	ldr r2, =0x1000
+	str r1, [r0, r2]
+
+	ldr r0, =DDRPHY_IPS_BASE_ADDR
+	ldr r1, =0x17421e40
+	str r1, [r0]
+	ldr r1, =0x10210100
+	str r1, [r0, #0x4]
+	ldr r1, =0x00010000
+	str r1, [r0, #0x8]
+	ldr r1, =0x0007080c
+	str r1, [r0, #0x10]
+	imx7d_ddrphy_lpddr3_latency_setting
+	ldr r1, =0x1010007e
+	str r1, [r0, #0xb0]
+	ldr r1, =0x01010000
+	str r1, [r0, #0x1c]
+
+	ldr r2, =ANATOP_BASE_ADDR
+	ldr r3, [r2, #0x800]
+	and r3, r3, #0xFF
+	cmp r3, #0x11
+	bne	1f
+
+	ldr r1, =0x0db60d6e
+	str r1, [r0, #0x9c]
+	b	2f
+1:
+	ldr r1, =0x00000b24
+	str r1, [r0, #0x9c]
+2:
+	ldr r1, =0x06060606
+	str r1, [r0, #0x30]
+	ldr r1, =0x0a0a0a0a
+	str r1, [r0, #0x20]
+	ldr r1, =0x01000008
+	str r1, [r0, #0x50]
+	ldr r1, =0x00000008
+	str r1, [r0, #0x50]
+
+	ldr r1, =0x0000000f
+	str r1, [r0, #0x18]
+	ldr r1, =0x0e487304
+	str r1, [r0, #0xc0]
+	ldr r1, =0x0e4c7304
+	str r1, [r0, #0xc0]
+	ldr r1, =0x0e4c7306
+	str r1, [r0, #0xc0]
+
+wait_zq:
+	ldr r1, [r0, #0xc4]
+	tst r1, #0x1
+	beq wait_zq
+
+	ldr r1, =0x0e487304
+	str r1, [r0, #0xc0]
+
+	ldr r0, =CCM_BASE_ADDR
+	mov r1, #0x0
+	ldr r2, =0x4130
+	str r1, [r0, r2]
+	ldr r0, =IOMUXC_GPR_BASE_ADDR
+	mov r1, #0x178
+	str r1, [r0, #0x20]
+	ldr r0, =CCM_BASE_ADDR
+	mov r1, #0x2
+	ldr r2, =0x4130
+	str r1, [r0, r2]
+
+	ldr r0, =DDRC_IPS_BASE_ADDR
+wait_stat:
+	ldr r1, [r0, #0x4]
+	tst r1, #0x1
+	beq wait_stat
+.endm
+
+.macro imx7d_19x19_lpddr2_val_setting
+	/* Configure ocram_epdc */
+	ldr r0, =IOMUXC_GPR_BASE_ADDR
+	ldr r1, =0x4f400005
+	str r1, [r0, #0x4]
+
+	ldr r0, =SRC_BASE_ADDR
+	ldr r1, =0x2
+	ldr r2, =0x1000
+	str r1, [r0, r2]
+
+	ldr r0, =DDRC_IPS_BASE_ADDR
+	ldr r1, =0x03020004
+	str r1, [r0]
+	ldr r1, =0x80400003
+	str r1, [r0, #0x1a0]
+	ldr r1, =0x00100020
+	str r1, [r0, #0x1a4]
+	ldr r1, =0x80100004
+	str r1, [r0, #0x1a8]
+	ldr r1, =0x00200023
+	str r1, [r0, #0x64]
+	ldr r1, =0x1
+	str r1, [r0, #0x490]
+	ldr r1, =0x00350001
+	str r1, [r0, #0xd0]
+	ldr r1, =0x00001105
+	str r1, [r0, #0xd8]
+	ldr r1, =0x00c20006
+	str r1, [r0, #0xdc]
+	ldr r1, =0x00020000
+	str r1, [r0, #0xe0]
+	ldr r1, =0x00110006
+	str r1, [r0, #0xe4]
+	ldr r1, =0x33f
+	str r1, [r0, #0xf4]
+	ldr r1, =0x080e110b
+	str r1, [r0, #0x100]
+	ldr r1, =0x00020211
+	str r1, [r0, #0x104]
+	ldr r1, =0x02040706
+	str r1, [r0, #0x108]
+	ldr r1, =0x00504000
+	str r1, [r0, #0x10c]
+	ldr r1, =0x05010307
+	str r1, [r0, #0x110]
+	ldr r1, =0x02020404
+	str r1, [r0, #0x114]
+	ldr r1, =0x02020003
+	str r1, [r0, #0x118]
+	ldr r1, =0x00000202
+	str r1, [r0, #0x11c]
+	ldr r1, =0x00000202
+	str r1, [r0, #0x120]
+	ldr r1, =0x00600018
+	str r1, [r0, #0x180]
+	ldr r1, =0x00e00100
+	str r1, [r0, #0x184]
+	ldr r1, =0x02098203
+	str r1, [r0, #0x190]
+	ldr r1, =0x00060303
+	str r1, [r0, #0x194]
+
+	ldr r1, =0x00000015
+	str r1, [r0, #0x200]
+	ldr r1, =0x00161616
+	str r1, [r0, #0x204]
+	ldr r1, =0x00000f0f
+	str r1, [r0, #0x210]
+	ldr r1, =0x04040404
+	str r1, [r0, #0x214]
+	ldr r1, =0x0f0f0404
+	str r1, [r0, #0x218]
+
+	ldr r1, =0x06000600
+	str r1, [r0, #0x240]
+	mov r1, #0x0
+	str r1, [r0, #0x244]
+
+	ldr r0, =SRC_BASE_ADDR
+	mov r1, #0x0
+	ldr r2, =0x1000
+	str r1, [r0, r2]
+
+	ldr r0, =DDRPHY_IPS_BASE_ADDR
+	ldr r1, =0x17421640
+	str r1, [r0]
+	ldr r1, =0x10210100
+	str r1, [r0, #0x4]
+	ldr r1, =0x00010000
+	str r1, [r0, #0x8]
+	ldr r1, =0x00050408
+	str r1, [r0, #0x10]
+	ldr r1, =0x1010007e
+	str r1, [r0, #0xb0]
+	ldr r1, =0x01010000
+	str r1, [r0, #0x1c]
+	imx7d_ddrphy_lpddr2_latency_setting
+	ldr r1, =0x0000000f
+	str r1, [r0, #0x18]
+
+	ldr r1, =0x06060606
+	str r1, [r0, #0x30]
+	ldr r1, =0x0a0a0a0a
+	str r1, [r0, #0x20]
+	ldr r1, =0x01000008
+	str r1, [r0, #0x50]
+	ldr r1, =0x00000008
+	str r1, [r0, #0x50]
+
+	ldr r1, =0x0e487304
+	str r1, [r0, #0xc0]
+	ldr r1, =0x0e4c7304
+	str r1, [r0, #0xc0]
+	ldr r1, =0x0e4c7306
+	str r1, [r0, #0xc0]
+
+wait_zq:
+	ldr r1, [r0, #0xc4]
+	tst r1, #0x1
+	beq wait_zq
+
+	ldr r1, =0x0e4c7304
+	str r1, [r0, #0xc0]
+	ldr r1, =0x0e487304
+	str r1, [r0, #0xc0]
+
+	ldr r0, =CCM_BASE_ADDR
+	mov r1, #0x0
+	ldr r2, =0x4130
+	str r1, [r0, r2]
+	ldr r0, =IOMUXC_GPR_BASE_ADDR
+	mov r1, #0x1f8
+	str r1, [r0, #0x20]
+	ldr r0, =CCM_BASE_ADDR
+	mov r1, #0x2
+	ldr r2, =0x4130
+	str r1, [r0, r2]
+
+	ldr r0, =DDRC_IPS_BASE_ADDR
+wait_stat:
+	ldr r1, [r0, #0x4]
+	tst r1, #0x1
+	beq wait_stat
+.endm
+
+.macro imx7_clock_gating
+.endm
+
+.macro imx7_qos_setting
+.endm
+
+.macro imx7_ddr_setting
+#if defined (TARGET_MX7D_19X19_LPDDR2_VAL)
+	imx7d_19x19_lpddr2_val_setting
+#else
+	imx7d_19x19_lpddr3_val_setting
+#endif
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx7_plugin.S>
diff --git a/board/freescale/mx7dsabresd/Kconfig b/board/freescale/mx7dsabresd/Kconfig
index bf3ceafe2b4..0f1d12a5264 100644
--- a/board/freescale/mx7dsabresd/Kconfig
+++ b/board/freescale/mx7dsabresd/Kconfig
@@ -12,4 +12,6 @@ config SYS_CONFIG_NAME
 config IMX_CONFIG
 	default "board/freescale/mx7dsabresd/imximage.cfg"
 
+config SYS_TEXT_BASE
+	default 0x87800000
 endif
diff --git a/board/freescale/mx7dsabresd/imximage.cfg b/board/freescale/mx7dsabresd/imximage.cfg
index 59e66fbda16..430f92820b4 100644
--- a/board/freescale/mx7dsabresd/imximage.cfg
+++ b/board/freescale/mx7dsabresd/imximage.cfg
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  *
  * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
  * and create imximage boot image
@@ -20,6 +21,10 @@ IMAGE_VERSION 2
 
 BOOT_FROM	sd
 
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7dsabresd/plugin.bin 0x00910000
+#else
 /*
  * Secure boot support
  */
@@ -39,7 +44,14 @@ CSF CONFIG_CSF_SIZE
  *	value	  value to be stored in the register
  */
 
+#ifdef CONFIG_IMX_OPTEE
+DATA 4 0x30340024 0x1
+CHECK_BITS_SET 4 0x30340024 0x1
+#endif
 DATA 4 0x30340004 0x4F400005
+/* Clear then set bit30 to ensure exit from DDR retention */
+DATA 4 0x30360388 0x40000000
+DATA 4 0x30360384 0x40000000
 
 DATA 4 0x30391000 0x00000002
 DATA 4 0x307a0000 0x01040001
@@ -66,9 +78,10 @@ DATA 4 0x307a0184 0x02000100
 DATA 4 0x307a0190 0x02098204
 DATA 4 0x307a0194 0x00030303
 DATA 4 0x307a0200 0x00000016
-DATA 4 0x307a0204 0x00171717
-DATA 4 0x307a0214 0x04040404
-DATA 4 0x307a0218 0x0f040404
+DATA 4 0x307a0204 0x00080808
+DATA 4 0x307a0210 0x00000f0f
+DATA 4 0x307a0214 0x07070707
+DATA 4 0x307a0218 0x0f070707
 DATA 4 0x307a0240 0x06000604
 DATA 4 0x307a0244 0x00000001
 DATA 4 0x30391000 0x00000000
@@ -76,7 +89,7 @@ DATA 4 0x30790000 0x17420f40
 DATA 4 0x30790004 0x10210100
 DATA 4 0x30790010 0x00060807
 DATA 4 0x307900b0 0x1010007e
-DATA 4 0x3079009c 0x00000d6e
+DATA 4 0x3079009c 0x00000b24
 DATA 4 0x30790020 0x08080808
 DATA 4 0x30790030 0x08080808
 DATA 4 0x30790050 0x01000010
@@ -88,7 +101,6 @@ DATA 4 0x307900c0 0x0e447306
 
 CHECK_BITS_SET 4 0x307900c4 0x1
 
-DATA 4 0x307900c0 0x0e447304
 DATA 4 0x307900c0 0x0e407304
 
 DATA 4 0x30384130 0x00000000
@@ -97,3 +109,5 @@ DATA 4 0x30384130 0x00000002
 DATA 4 0x30790018 0x0000000f
 
 CHECK_BITS_SET 4 0x307a0004 0x1
+
+#endif
diff --git a/board/freescale/mx7dsabresd/imximage_TO_1_1.cfg b/board/freescale/mx7dsabresd/imximage_TO_1_1.cfg
new file mode 100644
index 00000000000..854e3e552db
--- /dev/null
+++ b/board/freescale/mx7dsabresd/imximage_TO_1_1.cfg
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * Refer doc/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7dsabresd/plugin.bin 0x00910000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+#ifdef CONFIG_IMX_OPTEE
+DATA 4 0x30340024 0x1
+CHECK_BITS_SET 4 0x30340024 0x1
+#endif
+DATA 4 0x30360070 0x00703021
+DATA 4 0x30360090 0x0
+DATA 4 0x30360070 0x00603021
+CHECK_BITS_SET 4 0x30360070 0x80000000
+DATA 4 0x30389880 0x1
+
+DATA 4 0x30340004 0x4F400005
+/* Clear then set bit30 to ensure exit from DDR retention */
+DATA 4 0x30360388 0x40000000
+DATA 4 0x30360384 0x40000000
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x01040001
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0064 0x00400046
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00020083
+DATA 4 0x307a00d4 0x00690000
+DATA 4 0x307a00dc 0x09300004
+DATA 4 0x307a00e0 0x04080000
+DATA 4 0x307a00e4 0x00100004
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x09081109
+DATA 4 0x307a0104 0x0007020d
+DATA 4 0x307a0108 0x03040407
+DATA 4 0x307a010c 0x00002006
+DATA 4 0x307a0110 0x04020205
+DATA 4 0x307a0114 0x03030202
+DATA 4 0x307a0120 0x00000803
+DATA 4 0x307a0180 0x00800020
+DATA 4 0x307a0184 0x02000100
+DATA 4 0x307a0190 0x02098204
+DATA 4 0x307a0194 0x00030303
+DATA 4 0x307a0200 0x00000016
+DATA 4 0x307a0204 0x00080808
+DATA 4 0x307a0210 0x00000f0f
+DATA 4 0x307a0214 0x07070707
+DATA 4 0x307a0218 0x0f070707
+DATA 4 0x307a0240 0x06000604
+DATA 4 0x307a0244 0x00000001
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17420f40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790010 0x00060807
+DATA 4 0x307900b0 0x1010007e
+DATA 4 0x3079009c 0x00000dee
+DATA 4 0x3079007c 0x18181818
+DATA 4 0x30790080 0x18181818
+DATA 4 0x30790084 0x40401818
+DATA 4 0x30790088 0x00000040
+DATA 4 0x3079006c 0x40404040
+DATA 4 0x30790020 0x08080808
+DATA 4 0x30790030 0x08080808
+DATA 4 0x30790050 0x01000010
+DATA 4 0x30790050 0x00000010
+
+DATA 4 0x307900c0 0x0e407304
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e447306
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e407304
+
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+DATA 4 0x30790018 0x0000000f
+
+CHECK_BITS_SET 4 0x307a0004 0x1
+
+#endif
diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
index 2777ae13bce..c418b13a366 100644
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  */
 
 #include <init.h>
@@ -12,6 +13,7 @@
 #include <asm/global_data.h>
 #include <asm/gpio.h>
 #include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
 #include <asm/io.h>
 #include <linux/delay.h>
 #include <linux/sizes.h>
@@ -25,6 +27,11 @@
 #include <i2c.h>
 #include <asm/mach-imx/mxc_i2c.h>
 #include <asm/arch/crm_regs.h>
+#if defined(CONFIG_MXC_EPDC)
+#include <lcd.h>
+#include <mxc_epdc_fb.h>
+#endif
+#include <asm/mach-imx/video.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -41,6 +48,8 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
 
+#define EPDC_PAD_CTRL	0x0
+
 #ifdef CONFIG_MXC_SPI
 static iomux_v3_cfg_t const ecspi3_pads[] = {
     MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
@@ -76,6 +85,55 @@ static iomux_v3_cfg_t const uart1_pads[] = {
 	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
+#define BOARD_REV_C  0x300
+#define BOARD_REV_B  0x200
+#define BOARD_REV_A  0x100
+
+static int mx7sabre_rev(void)
+{
+	/*
+	 * Get Board ID information from OCOTP_GP1[15:8]
+	 * i.MX7D SDB RevA: 0x41
+	 * i.MX7D SDB RevB: 0x42
+	 */
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[14];
+	int reg = readl(&bank->fuse_regs[0]);
+	int ret;
+
+	if (reg != 0) {
+		switch (reg >> 8 & 0x0F) {
+		case 0x3:
+			ret = BOARD_REV_C;
+			break;
+		case 0x02:
+			ret = BOARD_REV_B;
+			break;
+		case 0x01:
+		default:
+			ret = BOARD_REV_A;
+			break;
+		}
+	} else {
+		/* If the gp1 fuse is not burn, we have to use TO rev for the board rev */
+		if (is_soc_rev(CHIP_REV_1_0))
+			ret = BOARD_REV_A;
+		else if (is_soc_rev(CHIP_REV_1_1))
+			ret = BOARD_REV_B;
+		else
+			ret = BOARD_REV_C;
+	}
+
+	return ret;
+}
+
+u32 get_board_rev(void)
+{
+	int rev = mx7sabre_rev();
+
+	return (get_cpu_rev() & ~(0xF << 8)) | rev;
+}
+
 #ifdef CONFIG_NAND_MXS
 static iomux_v3_cfg_t const gpmi_pads[] = {
 	MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
@@ -108,37 +166,8 @@ static void setup_gpmi_nand(void)
 }
 #endif
 
-#ifdef CONFIG_VIDEO_MXS
+#ifdef CONFIG_DM_VIDEO
 static iomux_v3_cfg_t const lcd_pads[] = {
-	MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-	MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
-
 	MX7D_PAD_LCD_RESET__GPIO3_IO4	| MUX_PAD_CTRL(LCD_PAD_CTRL),
 };
 
@@ -149,22 +178,50 @@ static iomux_v3_cfg_t const pwm_pads[] = {
 
 static int setup_lcd(void)
 {
+	int ret;
+	struct gpio_desc desc;
+
 	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
 
 	imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
 
 	/* Reset LCD */
-	gpio_request(IMX_GPIO_NR(3, 4), "lcd reset");
-	gpio_direction_output(IMX_GPIO_NR(3, 4) , 0);
+	ret = dm_gpio_lookup_name("GPIO3_4", &desc);
+	if (ret) {
+		printf("%s lookup GPIO3_4 failed ret = %d\n", __func__, ret);
+		return -ENODEV;
+	}
+
+	ret = dm_gpio_request(&desc, "lcd reset");
+	if (ret) {
+		printf("%s request lcd reset failed ret = %d\n", __func__, ret);
+		return -ENODEV;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+	dm_gpio_set_value(&desc, 0);
 	udelay(500);
-	gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
+	dm_gpio_set_value(&desc, 1);
 
 	/* Set Brightness to high */
-	gpio_request(IMX_GPIO_NR(1, 1), "lcd backlight");
-	gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
+	ret = dm_gpio_lookup_name("GPIO1_1", &desc);
+	if (ret) {
+		printf("%s lookup GPIO1_1 failed ret = %d\n", __func__, ret);
+		return -ENODEV;
+	}
+
+	ret = dm_gpio_request(&desc, "lcd backlight");
+	if (ret) {
+		printf("%s request lcd backlight failed ret = %d\n", __func__, ret);
+		return -ENODEV;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 
 	return 0;
 }
+#else
+static inline int setup_lcd(void) { return 0; }
 #endif
 
 static void setup_iomux_uart(void)
@@ -172,21 +229,13 @@ static void setup_iomux_uart(void)
 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 
-int board_mmc_get_env_dev(int devno)
-{
-	if (devno == 2)
-		devno--;
-
-	return devno;
-}
-
-int mmc_map_to_kernel_blk(int dev_no)
+#ifdef CONFIG_IMX_BOOTAUX
+ulong board_get_usable_ram_top(ulong total_size)
 {
-	if (dev_no == 1)
-		dev_no++;
-
-	return dev_no;
+	/* Reserve top 1M memory used by M core vring/buffer */
+	return gd->ram_top - SZ_1M;
 }
+#endif
 
 #ifdef CONFIG_FEC_MXC
 static int setup_fec(void)
@@ -199,6 +248,10 @@ static int setup_fec(void)
 		(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
 		 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
 
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+			(IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |
+			 IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0);
+
 	return set_clk_enet(ENET_125MHZ);
 }
 
@@ -226,6 +279,263 @@ int board_qspi_init(void)
 }
 #endif
 
+#ifdef CONFIG_MXC_EPDC
+iomux_v3_cfg_t const epdc_en_pads[] = {
+	MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const epdc_enable_pads[] = {
+	MX7D_PAD_EPDC_DATA00__EPDC_DATA0	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA01__EPDC_DATA1	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA02__EPDC_DATA2	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA03__EPDC_DATA3	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA04__EPDC_DATA4	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA05__EPDC_DATA5	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA06__EPDC_DATA6	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_DATA07__EPDC_DATA7	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_SDLE__EPDC_SDLE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_SDOE__EPDC_SDOE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_GDOE__EPDC_GDOE		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_GDRL__EPDC_GDRL		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_GDSP__EPDC_GDSP		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_BDR0__EPDC_BDR0		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+	MX7D_PAD_EPDC_BDR1__EPDC_BDR1		| MUX_PAD_CTRL(EPDC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const epdc_disable_pads[] = {
+	MX7D_PAD_EPDC_DATA00__GPIO2_IO0,
+	MX7D_PAD_EPDC_DATA01__GPIO2_IO1,
+	MX7D_PAD_EPDC_DATA02__GPIO2_IO2,
+	MX7D_PAD_EPDC_DATA03__GPIO2_IO3,
+	MX7D_PAD_EPDC_DATA04__GPIO2_IO4,
+	MX7D_PAD_EPDC_DATA05__GPIO2_IO5,
+	MX7D_PAD_EPDC_DATA06__GPIO2_IO6,
+	MX7D_PAD_EPDC_DATA07__GPIO2_IO7,
+	MX7D_PAD_EPDC_SDCLK__GPIO2_IO16,
+	MX7D_PAD_EPDC_SDLE__GPIO2_IO17,
+	MX7D_PAD_EPDC_SDOE__GPIO2_IO18,
+	MX7D_PAD_EPDC_SDSHR__GPIO2_IO19,
+	MX7D_PAD_EPDC_SDCE0__GPIO2_IO20,
+	MX7D_PAD_EPDC_SDCE1__GPIO2_IO21,
+	MX7D_PAD_EPDC_GDCLK__GPIO2_IO24,
+	MX7D_PAD_EPDC_GDOE__GPIO2_IO25,
+	MX7D_PAD_EPDC_GDRL__GPIO2_IO26,
+	MX7D_PAD_EPDC_GDSP__GPIO2_IO27,
+	MX7D_PAD_EPDC_BDR0__GPIO2_IO28,
+	MX7D_PAD_EPDC_BDR1__GPIO2_IO29,
+};
+
+vidinfo_t panel_info = {
+	.vl_refresh = 85,
+	.vl_col = 1024,
+	.vl_row = 758,
+	.vl_pixclock = 40000000,
+	.vl_left_margin = 12,
+	.vl_right_margin = 76,
+	.vl_upper_margin = 4,
+	.vl_lower_margin = 5,
+	.vl_hsync = 12,
+	.vl_vsync = 2,
+	.vl_sync = 0,
+	.vl_mode = 0,
+	.vl_flag = 0,
+	.vl_bpix = 3,
+	.cmap = 0,
+};
+
+struct epdc_timing_params panel_timings = {
+	.vscan_holdoff = 4,
+	.sdoed_width = 10,
+	.sdoed_delay = 20,
+	.sdoez_width = 10,
+	.sdoez_delay = 20,
+	.gdclk_hp_offs = 524,
+	.gdsp_offs = 327,
+	.gdoe_offs = 0,
+	.gdclk_offs = 19,
+	.num_ce = 1,
+};
+
+struct gpio_desc epd_pwrstat_desc;
+struct gpio_desc epd_vcom_desc;
+struct gpio_desc epd_wakeup_desc;
+struct gpio_desc epd_pwr_ctl0_desc;
+
+static void setup_epdc_power(void)
+{
+	int ret;
+
+	/* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+		IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0);
+
+	/* Setup epdc voltage */
+
+	/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
+	ret = dm_gpio_lookup_name("GPIO2_31", &epd_pwrstat_desc);
+	if (ret) {
+		printf("%s lookup GPIO2_31 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&epd_pwrstat_desc, "epdc_pwrstat");
+	if (ret) {
+		printf("%s request epdc_pwrstat failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&epd_pwrstat_desc, GPIOD_IS_IN);
+
+	/* EPDC_VCOM0 - GPIO4[14] for VCOM control */
+	/* Set as output */
+	ret = dm_gpio_lookup_name("GPIO4_14", &epd_vcom_desc);
+	if (ret) {
+		printf("%s lookup GPIO4_14 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&epd_vcom_desc, "epdc_vcom");
+	if (ret) {
+		printf("%s request epdc_vcom failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&epd_vcom_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	/* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */
+	/* Set as output */
+	ret = dm_gpio_lookup_name("GPIO2_23", &epd_wakeup_desc);
+	if (ret) {
+		printf("%s lookup GPIO2_23 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&epd_wakeup_desc, "epdc_pmic");
+	if (ret) {
+		printf("%s request epdc_pmic failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&epd_wakeup_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	/* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */
+	/* Set as output */
+	ret = dm_gpio_lookup_name("GPIO2_30", &epd_pwr_ctl0_desc);
+	if (ret) {
+		printf("%s lookup GPIO2_30 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&epd_pwr_ctl0_desc, "epdc_pwr_ctl0");
+	if (ret) {
+		printf("%s request epdc_pwr_ctl0 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&epd_pwr_ctl0_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+}
+
+static void epdc_enable_pins(void)
+{
+	/* epdc iomux settings */
+	imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
+				ARRAY_SIZE(epdc_enable_pads));
+}
+
+static void epdc_disable_pins(void)
+{
+	/* Configure MUX settings for EPDC pins to GPIO  and drive to 0 */
+	imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
+				ARRAY_SIZE(epdc_disable_pads));
+}
+
+static void setup_epdc(void)
+{
+	/*** epdc Maxim PMIC settings ***/
+
+	/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
+	imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* EPDC_VCOM0 - GPIO4[14] for VCOM control */
+	imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */
+	imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */
+	imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |
+				MUX_PAD_CTRL(EPDC_PAD_CTRL));
+
+	/* Set pixel clock rates for EPDC in clock.c */
+
+	panel_info.epdc_data.wv_modes.mode_init = 0;
+	panel_info.epdc_data.wv_modes.mode_du = 1;
+	panel_info.epdc_data.wv_modes.mode_gc4 = 3;
+	panel_info.epdc_data.wv_modes.mode_gc8 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc16 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc32 = 2;
+
+	panel_info.epdc_data.epdc_timings = panel_timings;
+
+	setup_epdc_power();
+}
+
+void epdc_power_on(void)
+{
+	unsigned int reg;
+	struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
+
+	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
+	dm_gpio_set_value(&epd_pwr_ctl0_desc, 1);
+	udelay(1000);
+
+	/* Enable epdc signal pin */
+	epdc_enable_pins();
+
+	/* Set PMIC Wakeup to high - enable Display power */
+	dm_gpio_set_value(&epd_wakeup_desc, 1);
+
+	/* Wait for PWRGOOD == 1 */
+	while (1) {
+		reg = readl(&gpio_regs->gpio_psr);
+		if (!(reg & (1 << 31)))
+			break;
+
+		udelay(100);
+	}
+
+	/* Enable VCOM */
+	dm_gpio_set_value(&epd_vcom_desc, 1);
+
+	udelay(500);
+}
+
+void epdc_power_off(void)
+{
+	/* Set PMIC Wakeup to low - disable Display power */
+	dm_gpio_set_value(&epd_wakeup_desc, 0);
+
+	/* Disable VCOM */
+	dm_gpio_set_value(&epd_vcom_desc, 0);
+
+	epdc_disable_pins();
+
+	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
+	dm_gpio_set_value(&epd_pwr_ctl0_desc, 0);
+}
+#endif
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -246,14 +556,39 @@ int board_init(void)
 	setup_gpmi_nand();
 #endif
 
-#ifdef CONFIG_VIDEO_MXS
-	setup_lcd();
-#endif
-
 #ifdef CONFIG_FSL_QSPI
 	board_qspi_init();
 #endif
 
+#ifdef CONFIG_MXC_EPDC
+	if (mx7sabre_rev() >= BOARD_REV_B) {
+		int ret;
+		struct gpio_desc desc;
+		/*
+		 * From RevB, GPIO1_IO04 is used for ENET2 EN,
+		 * so set its output to high to isolate the
+		 * ENET2 signals for EPDC
+		 */
+		imx_iomux_v3_setup_multiple_pads(epdc_en_pads,
+			ARRAY_SIZE(epdc_en_pads));
+
+		ret = dm_gpio_lookup_name("GPIO1_4", &desc);
+		if (ret) {
+			printf("%s lookup GPIO1_4 failed ret = %d\n", __func__, ret);
+			return -ENODEV;
+		}
+
+		ret = dm_gpio_request(&desc, "epdc_en");
+		if (ret) {
+			printf("%s request epdc_en failed ret = %d\n", __func__, ret);
+			return -ENODEV;
+		}
+
+		dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+	}
+	setup_epdc();
+#endif
+
 #ifdef CONFIG_MXC_SPI
        setup_spi();
 #endif
@@ -261,11 +596,13 @@ int board_init(void)
 	return 0;
 }
 
+
 #ifdef CONFIG_DM_PMIC
 int power_init_board(void)
 {
 	struct udevice *dev;
 	int ret, dev_id, rev_id;
+	u32 sw3mode;
 
 	ret = pmic_get("pfuze3000@8", &dev);
 	if (ret == -ENODEV)
@@ -285,6 +622,12 @@ int power_init_board(void)
 	 */
 	pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA);
 
+	/* change sw3 mode to avoid DDR power off */
+	sw3mode = pmic_reg_read(dev, PFUZE3000_SW3MODE);
+	ret = pmic_reg_write(dev, PFUZE3000_SW3MODE, sw3mode | 0x20);
+	if (ret < 0)
+		printf("PMIC: PFUZE3000 change sw3 mode failed\n");
+
 	return 0;
 }
 #endif
@@ -293,29 +636,49 @@ int board_late_init(void)
 {
 	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
 
+	env_set("tee", "no");
+#ifdef CONFIG_IMX_OPTEE
+	env_set("tee", "yes");
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+	setup_lcd();
+
 	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 
 	set_wdog_reset(wdog);
 
-	/*
-	 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
-	 * since we use PMIC_PWRON to reset the board.
-	 */
-	clrsetbits_le16(&wdog->wcr, 0, 0x10);
-
 	return 0;
 }
 
 int checkboard(void)
 {
+	int rev = mx7sabre_rev();
 	char *mode;
+	char *revname;
 
 	if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
 		mode = "secure";
 	else
 		mode = "non-secure";
 
-	printf("Board: i.MX7D SABRESD in %s mode\n", mode);
+	switch (rev) {
+	case BOARD_REV_C:
+		revname = "C";
+		break;
+	case BOARD_REV_B:
+		revname = "B";
+		break;
+	case BOARD_REV_A:
+	default:
+		revname = "A";
+		break;
+	}
+
+	printf("Board: i.MX7D SABRESD Rev%s in %s mode\n", revname, mode);
 
 	return 0;
 }
diff --git a/board/freescale/mx7dsabresd/plugin.S b/board/freescale/mx7dsabresd/plugin.S
new file mode 100644
index 00000000000..1f64e468350
--- /dev/null
+++ b/board/freescale/mx7dsabresd/plugin.S
@@ -0,0 +1,233 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx7d_ddrphy_latency_setting
+	ldr r2, =ANATOP_BASE_ADDR
+	ldr r3, [r2, #0x800]
+	and r3, r3, #0xFF
+	cmp r3, #0x11
+	bne NO_DELAY
+
+	/*TO 1.1*/
+	ldr r1, =0x00000dee
+	str r1, [r0, #0x9c]
+	ldr r1, =0x18181818
+	str r1, [r0, #0x7c]
+	ldr r1, =0x18181818
+	str r1, [r0, #0x80]
+	ldr r1, =0x40401818
+	str r1, [r0, #0x84]
+	ldr r1, =0x00000040
+	str r1, [r0, #0x88]
+	ldr r1, =0x40404040
+	str r1, [r0, #0x6c]
+	b TUNE_END
+
+NO_DELAY:
+	/*TO 1.0*/
+	ldr r1, =0x00000b24
+	str r1, [r0, #0x9c]
+
+TUNE_END:
+.endm
+
+.macro imx7d_ddr_freq_setting
+	ldr r2, =ANATOP_BASE_ADDR
+	ldr r3, [r2, #0x800]
+	and r3, r3, #0xFF
+	cmp r3, #0x11
+	bne FREQ_DEFAULT_533
+
+	/* Change to 400Mhz for TO1.1 */
+	ldr r0, =ANATOP_BASE_ADDR
+	ldr r1, =0x70
+	ldr r2, =0x00703021
+	str r2, [r0, r1]
+	ldr r1, =0x90
+	ldr r2, =0x0
+	str r2, [r0, r1]
+	ldr r1, =0x70
+	ldr r2, =0x00603021
+	str r2, [r0, r1]
+
+	ldr r3, =0x80000000
+wait_lock:
+	ldr r2, [r0, r1]
+	and r2, r3
+	cmp r2, r3
+	bne wait_lock
+
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0x9880
+	ldr r2, =0x1
+	str r2, [r0, r1]
+
+FREQ_DEFAULT_533:
+.endm
+
+.macro imx7d_sabresd_ddr_setting
+	imx7d_ddr_freq_setting
+
+	/* Configure ocram_epdc */
+	ldr r0, =IOMUXC_GPR_BASE_ADDR
+	ldr r1, =0x4f400005
+	str r1, [r0, #0x4]
+
+	/* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
+	ldr r0, =ANATOP_BASE_ADDR
+	ldr r1, =(0x1 << 30)
+	str r1, [r0, #0x388]
+	str r1, [r0, #0x384]
+
+	ldr r0, =SRC_BASE_ADDR
+	ldr r1, =0x2
+	ldr r2, =0x1000
+	str r1, [r0, r2]
+
+	ldr r0, =DDRC_IPS_BASE_ADDR
+	ldr r1, =0x01040001
+	str r1, [r0]
+	ldr r1, =0x80400003
+	str r1, [r0, #0x1a0]
+	ldr r1, =0x00100020
+	str r1, [r0, #0x1a4]
+	ldr r1, =0x80100004
+	str r1, [r0, #0x1a8]
+	ldr r1, =0x00400046
+	str r1, [r0, #0x64]
+	ldr r1, =0x1
+	str r1, [r0, #0x490]
+	ldr r1, =0x00020001
+	str r1, [r0, #0xd0]
+	ldr r1, =0x00690000
+	str r1, [r0, #0xd4]
+	ldr r1, =0x09300004
+	str r1, [r0, #0xdc]
+	ldr r1, =0x04080000
+	str r1, [r0, #0xe0]
+	ldr r1, =0x00100004
+	str r1, [r0, #0xe4]
+	ldr r1, =0x33f
+	str r1, [r0, #0xf4]
+	ldr r1, =0x09081109
+	str r1, [r0, #0x100]
+	ldr r1, =0x0007020d
+	str r1, [r0, #0x104]
+	ldr r1, =0x03040407
+	str r1, [r0, #0x108]
+	ldr r1, =0x00002006
+	str r1, [r0, #0x10c]
+	ldr r1, =0x04020205
+	str r1, [r0, #0x110]
+	ldr r1, =0x03030202
+	str r1, [r0, #0x114]
+	ldr r1, =0x00000803
+	str r1, [r0, #0x120]
+	ldr r1, =0x00800020
+	str r1, [r0, #0x180]
+	ldr r1, =0x02000100
+	str r1, [r0, #0x184]
+	ldr r1, =0x02098204
+	str r1, [r0, #0x190]
+	ldr r1, =0x00030303
+	str r1, [r0, #0x194]
+
+	ldr r1, =0x00000016
+	str r1, [r0, #0x200]
+	ldr r1, =0x00080808
+	str r1, [r0, #0x204]
+	ldr r1, =0x00000f0f
+	str r1, [r0, #0x210]
+	ldr r1, =0x07070707
+	str r1, [r0, #0x214]
+	ldr r1, =0x0f070707
+	str r1, [r0, #0x218]
+
+	ldr r1, =0x06000604
+	str r1, [r0, #0x240]
+	ldr r1, =0x00000001
+	str r1, [r0, #0x244]
+
+	ldr r0, =SRC_BASE_ADDR
+	mov r1, #0x0
+	ldr r2, =0x1000
+	str r1, [r0, r2]
+
+	ldr r0, =DDRPHY_IPS_BASE_ADDR
+	ldr r1, =0x17420f40
+	str r1, [r0]
+	ldr r1, =0x10210100
+	str r1, [r0, #0x4]
+	ldr r1, =0x00060807
+	str r1, [r0, #0x10]
+	ldr r1, =0x1010007e
+	str r1, [r0, #0xb0]
+	imx7d_ddrphy_latency_setting
+	ldr r1, =0x08080808
+	str r1, [r0, #0x20]
+	ldr r1, =0x08080808
+	str r1, [r0, #0x30]
+	ldr r1, =0x01000010
+	str r1, [r0, #0x50]
+
+	ldr r1, =0x0e407304
+	str r1, [r0, #0xc0]
+	ldr r1, =0x0e447304
+	str r1, [r0, #0xc0]
+	ldr r1, =0x0e447306
+	str r1, [r0, #0xc0]
+
+wait_zq:
+	ldr r1, [r0, #0xc4]
+	tst r1, #0x1
+	beq wait_zq
+
+	ldr r1, =0x0e407304
+	str r1, [r0, #0xc0]
+
+	ldr r0, =CCM_BASE_ADDR
+	mov r1, #0x0
+	ldr r2, =0x4130
+	str r1, [r0, r2]
+	ldr r0, =IOMUXC_GPR_BASE_ADDR
+	mov r1, #0x178
+	str r1, [r0, #0x20]
+	ldr r0, =CCM_BASE_ADDR
+	mov r1, #0x2
+	ldr r2, =0x4130
+	str r1, [r0, r2]
+	ldr r0, =DDRPHY_IPS_BASE_ADDR
+	ldr r1, =0x0000000f
+	str r1, [r0, #0x18]
+
+	ldr r0, =DDRC_IPS_BASE_ADDR
+wait_stat:
+	ldr r1, [r0, #0x4]
+	tst r1, #0x1
+	beq wait_stat
+.endm
+
+.macro imx7_clock_gating
+#ifdef CONFIG_IMX_OPTEE
+	ldr r0, =0x30340024
+	ldr r1, =0x1
+	str r1, [r0]
+#endif
+.endm
+
+.macro imx7_qos_setting
+.endm
+
+.macro imx7_ddr_setting
+	imx7d_sabresd_ddr_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx7_plugin.S>
diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg
index 62fd79afd6c..72b05e737c9 100644
--- a/board/freescale/mx7ulp_evk/imximage.cfg
+++ b/board/freescale/mx7ulp_evk/imximage.cfg
@@ -79,51 +79,52 @@ DATA 4   0x40AD0098 0x00000180
 DATA 4   0x40AD009C 0x00000180
 
 DATA 4   0x40AD00E0 0x00040000
-DATA 4   0x40AD00E4 0x00040000
 
 DATA 4   0x40AB001C 0x00008000
+DATA 4   0x40AB085C 0x1B3E80AF
 DATA 4   0x40AB0800 0xA1390003
-DATA 4   0x40AB085C 0x0D3900A0
 DATA 4   0x40AB0890 0x00400000
 
-DATA 4   0x40AB0848 0x40404040
-DATA 4   0x40AB0850 0x40404040
 DATA 4   0x40AB081C 0x33333333
 DATA 4   0x40AB0820 0x33333333
 DATA 4   0x40AB0824 0x33333333
 DATA 4   0x40AB0828 0x33333333
 
 DATA 4   0x40AB08C0 0x24922492
+DATA 4   0x40AB0848 0x36363838
+DATA 4   0x40AB0850 0x34323C36
+DATA 4   0x40AB083C 0x20000000
+DATA 4   0x40AB0840 0x00000000
 DATA 4   0x40AB08B8 0x00000800
 
-DATA 4   0x40AB0004 0x00020052
-DATA 4   0x40AB000C 0x292C42F3
-DATA 4   0x40AB0010 0x00100A22
-DATA 4   0x40AB0038 0x00120556
-DATA 4   0x40AB0014 0x00C700DB
+DATA 4   0x40AB000C 0x2D314313
+DATA 4   0x40AB0004 0x00020012
+DATA 4   0x40AB0010 0xB6AE0B22
+DATA 4   0x40AB0014 0x00C70123
 DATA 4   0x40AB0018 0x00211718
 DATA 4   0x40AB002C 0x0F9F26D2
 DATA 4   0x40AB0030 0x009F0E10
+DATA 4   0x40AB0038 0x00150667
 DATA 4   0x40AB0040 0x0000003F
 DATA 4   0x40AB0000 0xC3190000
 
 DATA 4   0x40AB001C 0x00008010
 DATA 4   0x40AB001C 0x00008018
 DATA 4   0x40AB001C 0x003F8030
-DATA 4   0x40AB001C 0x003F8038
 DATA 4   0x40AB001C 0xFF0A8030
-DATA 4   0x40AB001C 0xFF0A8038
-DATA 4   0x40AB001C 0x04028030
-DATA 4   0x40AB001C 0x04028038
 DATA 4   0x40AB001C 0x83018030
-DATA 4   0x40AB001C 0x83018038
+DATA 4   0x40AB001C 0x04028030
 DATA 4   0x40AB001C 0x01038030
+DATA 4   0x40AB001C 0x003F8038
+DATA 4   0x40AB001C 0xFF0A8038
+DATA 4   0x40AB001C 0x83018038
+DATA 4   0x40AB001C 0x04028038
 DATA 4   0x40AB001C 0x01038038
 
-DATA 4   0x40AB083C 0x20000000
+DATA 4   0x40AB083C 0xA0000000
+DATA 4   0x40AB083C 0xA0000000
 
 DATA 4   0x40AB0020 0x00001800
-DATA 4   0x40AB0800 0xA1310000
 DATA 4   0x40AB0004 0x00020052
 DATA 4   0x40AB0404 0x00011006
 DATA 4   0x40AB001C 0x00000000
diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c
index 01e32136532..9887aeee692 100644
--- a/board/freescale/mx7ulp_evk/mx7ulp_evk.c
+++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c
@@ -12,10 +12,24 @@
 #include <asm/arch/mx7ulp-pins.h>
 #include <asm/arch/iomux.h>
 #include <asm/mach-imx/boot_mode.h>
+#include <asm/gpio.h>
+#include <usb.h>
+#include <dm.h>
+#include <env.h>
+
+#ifdef CONFIG_BOOTLOADER_MENU
+#include "video.h"
+#include "dm/uclass.h"
+#include "video_font_data.h"
+#include "video_console.h"
+#include "recovery.h"
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #define UART_PAD_CTRL	(PAD_CTL_PUS_UP)
+#define QSPI_PAD_CTRL1	(PAD_CTL_PUS_UP | PAD_CTL_DSE)
+#define OTG_ID_GPIO_PAD_CTRL	(PAD_CTL_IBE_ENABLE)
 
 int dram_init(void)
 {
@@ -24,6 +38,12 @@ int dram_init(void)
 	return 0;
 }
 
+ulong board_get_usable_ram_top(ulong total_size)
+{
+	/* Reserve top 1M memory used by M core vring/buffer */
+	return gd->ram_top - SZ_1M;
+}
+
 static iomux_cfg_t const lpuart4_pads[] = {
 	MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
 	MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
@@ -35,6 +55,40 @@ static void setup_iomux_uart(void)
 					 ARRAY_SIZE(lpuart4_pads));
 }
 
+#ifdef CONFIG_FSL_QSPI
+#ifndef CONFIG_DM_SPI
+static iomux_cfg_t const quadspi_pads[] = {
+	MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB15__QSPIA_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+#endif
+
+int board_qspi_init(void)
+{
+	u32 val;
+#ifndef CONFIG_DM_SPI
+	mx7ulp_iomux_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
+#endif
+
+	/* enable clock */
+	val = readl(PCC1_RBASE + 0x94);
+
+	if (!(val & 0x20000000)) {
+		writel(0x03000003, (PCC1_RBASE + 0x94));
+		writel(0x43000003, (PCC1_RBASE + 0x94));
+	}
+
+	/* Enable QSPI as a wakeup source on B0 */
+	if (soc_rev() >= CHIP_REV_2_0)
+		setbits_le32(SIM0_RBASE + WKPU_WAKEUP_EN, WKPU_QSPI_CHANNEL);
+	return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -47,6 +101,10 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
 	return 0;
 }
 
@@ -94,3 +152,124 @@ add:
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_BOOTLOADER_MENU
+static iomux_cfg_t const vol_pad[] = {
+	MX7ULP_PAD_PTA3__PTA3 | MUX_PAD_CTRL(PAD_CTL_IBE_ENABLE),
+};
+#define VOLP_GPIO	IMX_GPIO_NR(1, 3)
+bool is_vol_key_pressed(void);
+int show_bootloader_menu(void);
+#endif
+
+int board_late_init(void)
+{
+	env_set("tee", "no");
+#ifdef CONFIG_IMX_OPTEE
+	env_set("tee", "yes");
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_env_init();
+#endif
+
+#ifdef CONFIG_BOOTLOADER_MENU
+	mx7ulp_iomux_setup_multiple_pads(vol_pad, ARRAY_SIZE(vol_pad));
+	if (gpio_request(VOLP_GPIO, "volp"))
+		printf("request error\n");
+	gpio_direction_input(VOLP_GPIO);
+
+	if (is_vol_key_pressed())
+		show_bootloader_menu();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_ANDROID_SUPPORT
+bool is_power_key_pressed(void) {
+	/* the onoff button is 'pressed' by default on evk board */
+	return (bool)(!(readl(SNVS_HPSR_REVB) & (0x1 << 6)));
+}
+
+#ifdef CONFIG_BOOTLOADER_MENU
+char bootloader_menu[4][40] = {
+	"   * Power off the device\n",
+	"   * Start the device normally\n",
+	"   * Restart the bootloader\n",
+	"   * Boot into recovery mode\n"
+};
+
+bool is_vol_key_pressed(void) {
+	int ret = 0;
+	ret = gpio_get_value(VOLP_GPIO);
+	return (bool)(!!ret);
+}
+
+int show_bootloader_menu(void) {
+	struct udevice *dev, *dev_console;
+	uint32_t focus = 0, i;
+	bool stop_menu = false;
+
+	/* clear screen first */
+	if (uclass_first_device_err(UCLASS_VIDEO, &dev)) {
+		printf("no video device found!\n");
+		return -1;
+	}
+	video_clear(dev);
+
+	if (uclass_first_device_err(UCLASS_VIDEO_CONSOLE, &dev_console)) {
+		printf("no text console device found!\n");
+		return -1;
+	}
+
+	vidconsole_position_cursor(dev_console, 0, 1);
+	vidconsole_put_string(dev_console, "Press 'vol+' to choose an item, press\n");
+	vidconsole_put_string(dev_console, "power key to confirm:\n");
+	while (!stop_menu) {
+		/* reset the cursor position. */
+		vidconsole_position_cursor(dev_console, 0, 4);
+		/* show menu */
+		for (i = 0; i < 4; i++) {
+			/* reverse color for the 'focus' line. */
+			if (i == focus)
+				vidconsole_put_string(dev_console, "\x1b[7m");
+			/* show text */
+			vidconsole_put_string(dev_console, bootloader_menu[i]);
+			/* reset color back for the 'next' line. */
+			if (i == focus)
+				vidconsole_put_string(dev_console, "\x1b[0m");
+		}
+		/* check button status */
+		while (1) {
+			if (is_power_key_pressed()) {
+				switch (focus) {
+					case 0: /*TODO*/
+					case 1:
+						break;
+					case 2:
+						do_reset(NULL, 0, 0, NULL);
+					case 3:
+						board_recovery_setup();
+						break;
+					default:
+						break;
+				}
+				stop_menu = true;
+				break;
+			} else if (is_vol_key_pressed()) {
+				focus++;
+				if (focus > 3)
+					focus = 0;
+				mdelay(400);
+				break;
+			}
+		}
+	}
+
+	/* clear screen before exit */
+	video_clear(dev);
+	return 0;
+}
+#endif /* CONFIG_BOOTLOADER_MENU */
+#endif /* CONFIG_ANDROID_SUPPORT*/
diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S
index 2cc93dbdd57..411716435ea 100644
--- a/board/freescale/mx7ulp_evk/plugin.S
+++ b/board/freescale/mx7ulp_evk/plugin.S
@@ -108,23 +108,17 @@ wait2:
 	str r1, [r0, #0x9c]
 	ldr r1, =0x00040000
 	str r1, [r0, #0xe0]
-	ldr r1, =0x00040000
-	str r1, [r0, #0xe4]
 
 	ldr r0, =0x40ab0000
 	ldr r1, =0x00008000
 	str r1, [r0, #0x1c]
+	ldr r1, =0x1B3E80AF
+	str r1, [r0, #0x85c]
 	ldr r1, =0xA1390003
 	str r1, [r0, #0x800]
-	ldr r1, =0x0D3900A0
-	str r1, [r0, #0x85c]
 	ldr r1, =0x00400000
 	str r1, [r0, #0x890]
 
-	ldr r1, =0x40404040
-	str r1, [r0, #0x848]
-	ldr r1, =0x40404040
-	str r1, [r0, #0x850]
 	ldr r1, =0x33333333
 	str r1, [r0, #0x81c]
 	ldr r1, =0x33333333
@@ -136,18 +130,24 @@ wait2:
 
 	ldr r1, =0x24922492
 	str r1, [r0, #0x8c0]
+	ldr r1, =0x36363838
+	str r1, [r0, #0x848]
+	ldr r1, =0x34323C36
+	str r1, [r0, #0x850]
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83c]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x840]
 	ldr r1, =0x00000800
 	str r1, [r0, #0x8b8]
 
-	ldr r1, =0x00020052
-	str r1, [r0, #0x4]
-	ldr r1, =0x292C42F3
+	ldr r1, =0x2D314313
 	str r1, [r0, #0xc]
-	ldr r1, =0x00100A22
+	ldr r1, =0x00020012
+	str r1, [r0, #0x4]
+	ldr r1, =0xB6AE0B22
 	str r1, [r0, #0x10]
-	ldr r1, =0x00120556
-	str r1, [r0, #0x38]
-	ldr r1, =0x00C700DB
+	ldr r1, =0x00C70123
 	str r1, [r0, #0x14]
 	ldr r1, =0x00211718
 	str r1, [r0, #0x18]
@@ -156,6 +156,8 @@ wait2:
 	str r1, [r0, #0x2c]
 	ldr r1, =0x009F0E10
 	str r1, [r0, #0x30]
+	ldr r1, =0x00150667
+	str r1, [r0, #0x38]
 	ldr r1, =0x0000003F
 	str r1, [r0, #0x40]
 	ldr r1, =0xC3190000
@@ -167,35 +169,35 @@ wait2:
 	str r1, [r0, #0x1c]
 	ldr r1, =0x003F8030
 	str r1, [r0, #0x1c]
-	ldr r1, =0x003F8038
-	str r1, [r0, #0x1c]
 	ldr r1, =0xFF0A8030
 	str r1, [r0, #0x1c]
-	ldr r1, =0xFF0A8038
+	ldr r1, =0x83018030
 	str r1, [r0, #0x1c]
 	ldr r1, =0x04028030
 	str r1, [r0, #0x1c]
-	ldr r1, =0x04028038
+	ldr r1, =0x01038030
 	str r1, [r0, #0x1c]
-	ldr r1, =0x83018030
+	ldr r1, =0x003F8038
+	str r1, [r0, #0x1c]
+	ldr r1, =0xFF0A8038
 	str r1, [r0, #0x1c]
 	ldr r1, =0x83018038
 	str r1, [r0, #0x1c]
-	ldr r1, =0x01038030
+	ldr r1, =0x04028038
 	str r1, [r0, #0x1c]
 	ldr r1, =0x01038038
 	str r1, [r0, #0x1c]
 
-	ldr r1, =0x20000000
+	ldr r1, =0xA0000000
+	str r1, [r0, #0x83c]
+	ldr r1, =0xA0000000
 	str r1, [r0, #0x83c]
 
 	ldr r1, =0x00001800
 	str r1, [r0, #0x20]
-	ldr r1, =0xA1310000
-	str r1, [r0, #0x800]
 	ldr r1, =0x00020052
 	str r1, [r0, #0x4]
-	ldr r1, =0x00011006
+	ldr r1, =0x00010106
 	str r1, [r0, #0x404]
 	ldr r1, =0x00000000
 	str r1, [r0, #0x1c]
diff --git a/board/freescale/mx7ulp_val/Kconfig b/board/freescale/mx7ulp_val/Kconfig
new file mode 100644
index 00000000000..b68cb6f2594
--- /dev/null
+++ b/board/freescale/mx7ulp_val/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX7ULP_10X10_VAL || TARGET_MX7ULP_14X14_VAL
+
+config SYS_BOARD
+	default "mx7ulp_val"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx7ulp_val"
+
+endif
diff --git a/board/freescale/mx7ulp_val/Makefile b/board/freescale/mx7ulp_val/Makefile
new file mode 100644
index 00000000000..ce82e631c80
--- /dev/null
+++ b/board/freescale/mx7ulp_val/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx7ulp_val.o
diff --git a/board/freescale/mx7ulp_val/imximage.cfg b/board/freescale/mx7ulp_val/imximage.cfg
new file mode 100644
index 00000000000..d0cd033aa4a
--- /dev/null
+++ b/board/freescale/mx7ulp_val/imximage.cfg
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7ulp_val/plugin.bin 0x2F020000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4   0x403f00e0 0x00000000
+DATA 4   0x403e0040 0x01000020
+DATA 4   0x403e0500 0x01000000
+DATA 4   0x403e050c 0x80808080
+DATA 4   0x403e0508 0x00160002
+DATA 4   0x403E0510 0x00000000
+DATA 4   0x403E0514 0x00000001
+DATA 4   0x403e0500 0x00000001
+CHECK_BITS_SET 4 0x403e0500 0x01000000
+DATA 4   0x403e050c 0x80808019
+CHECK_BITS_SET 4 0x403e050c 0x00000040
+DATA 4   0x403E0030 0x00000001
+DATA 4   0x403e0040 0x11000020
+DATA 4   0x403f00e0 0x42000000
+
+DATA 4   0x40B300AC 0x40000000
+
+DATA 4   0x40AD0128 0x00040000
+DATA 4   0x40AD00F8 0x00000000
+DATA 4   0x40AD00D8 0x00000180
+DATA 4   0x40AD0108 0x00000180
+DATA 4   0x40AD0104 0x00000180
+DATA 4   0x40AD0124 0x00010000
+DATA 4   0x40AD0080 0x0000018C
+DATA 4   0x40AD0084 0x0000018C
+DATA 4   0x40AD0088 0x0000018C
+DATA 4   0x40AD008C 0x0000018C
+
+DATA 4   0x40AD0120 0x00010000
+DATA 4   0x40AD010C 0x00000180
+DATA 4   0x40AD0110 0x00000180
+DATA 4   0x40AD0114 0x00000180
+DATA 4   0x40AD0118 0x00000180
+DATA 4   0x40AD0090 0x00000180
+DATA 4   0x40AD0094 0x00000180
+DATA 4   0x40AD0098 0x00000180
+DATA 4   0x40AD009C 0x00000180
+
+DATA 4   0x40AD00E0 0x00040000
+DATA 4   0x40AD00E4 0x00040000
+
+DATA 4   0x40AB001C 0x00008000
+DATA 4   0x40AB0800 0xA1390003
+DATA 4   0x40AB085C 0x0D3900A0
+DATA 4   0x40AB0890 0x00400000
+
+DATA 4   0x40AB0848 0x39373939
+DATA 4   0x40AB0850 0x2F313D36
+DATA 4   0x40AB081C 0x33333333
+DATA 4   0x40AB0820 0x33333333
+DATA 4   0x40AB0824 0x33333333
+DATA 4   0x40AB0828 0x33333333
+
+DATA 4   0x40AB08C0 0x24922492
+DATA 4   0x40AB08B8 0x00000800
+
+DATA 4   0x40AB0004 0x00020052
+DATA 4   0x40AB000C 0x424642F3
+DATA 4   0x40AB0010 0x00100A22
+DATA 4   0x40AB0038 0x00120556
+DATA 4   0x40AB0014 0x00C700DA
+DATA 4   0x40AB0018 0x00211718
+DATA 4   0x40AB002C 0x0F9F26D2
+DATA 4   0x40AB0030 0x009F0E10
+DATA 4   0x40AB0040 0x0000004F
+DATA 4   0x40AB0000 0x84190000
+
+DATA 4   0x40AB001C 0x00008010
+DATA 4   0x40AB001C 0x003F8030
+DATA 4   0x40AB001C 0xFF0A8030
+DATA 4   0x40AB001C 0x04028030
+DATA 4   0x40AB001C 0x83018030
+DATA 4   0x40AB001C 0x01038030
+
+DATA 4   0x40AB083C 0x20000000
+
+DATA 4   0x40AB0020 0x00001800
+DATA 4   0x40AB0800 0xA1310003
+DATA 4   0x40AB001C 0x00000000
+
+#endif
diff --git a/board/freescale/mx7ulp_val/imximage_lpddr2.cfg b/board/freescale/mx7ulp_val/imximage_lpddr2.cfg
new file mode 100644
index 00000000000..7393ff363ed
--- /dev/null
+++ b/board/freescale/mx7ulp_val/imximage_lpddr2.cfg
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7ulp_val/plugin.bin 0x2F020000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4   0x403f00e0 0x00000000
+DATA 4   0x403e0040 0x01000020
+DATA 4   0x403e0500 0x01000000
+DATA 4   0x403e050c 0x80808080
+DATA 4   0x403e0508 0x00160002
+DATA 4   0x403E0510 0x00000000
+DATA 4   0x403E0514 0x00000001
+DATA 4   0x403e0500 0x00000001
+CHECK_BITS_SET 4 0x403e0500 0x01000000
+DATA 4   0x403e050c 0x80808019
+CHECK_BITS_SET 4 0x403e050c 0x00000040
+DATA 4   0x403E0030 0x00000001
+DATA 4   0x403e0040 0x11000020
+DATA 4   0x403f00e0 0x42000000
+
+DATA 4   0x40B300AC 0x40000000
+
+DATA 4   0x40AD0128 0x00040000
+DATA 4   0x40AD00F8 0x00000000
+DATA 4   0x40AD00D8 0x0000018C
+DATA 4   0x40AD0108 0x00000180
+DATA 4   0x40AD0104 0x00000180
+DATA 4   0x40AD0124 0x00010000
+DATA 4   0x40AD0080 0x0000018C
+DATA 4   0x40AD0084 0x0000018C
+DATA 4   0x40AD0088 0x0000018C
+DATA 4   0x40AD008C 0x0000018C
+
+DATA 4   0x40AD0120 0x00010000
+DATA 4   0x40AD010C 0x00000180
+DATA 4   0x40AD0110 0x00000180
+DATA 4   0x40AD0114 0x00000180
+DATA 4   0x40AD0118 0x00000180
+DATA 4   0x40AD0090 0x00000180
+DATA 4   0x40AD0094 0x00000180
+DATA 4   0x40AD0098 0x00000180
+DATA 4   0x40AD009C 0x00000180
+
+DATA 4   0x40AD00E0 0x00040000
+DATA 4   0x40AD00E4 0x00040000
+
+DATA 4   0x40AB001C 0x00008000
+DATA 4   0x40AB0800 0xA1390003
+DATA 4   0x40AB085C 0x0D3900A0
+DATA 4   0x40AB0890 0x00400000
+
+DATA 4   0x40AB0848 0x40404040
+DATA 4   0x40AB0850 0x40404040
+DATA 4   0x40AB081C 0x33333333
+DATA 4   0x40AB0820 0x33333333
+DATA 4   0x40AB0824 0x33333333
+DATA 4   0x40AB0828 0x33333333
+
+DATA 4   0x40AB08C0 0x24922492
+DATA 4   0x40AB08B8 0x00000800
+
+DATA 4   0x40AB0004 0x00020052
+DATA 4   0x40AB000C 0x292C42F3
+DATA 4   0x40AB0010 0x00100A22
+DATA 4   0x40AB0038 0x00120556
+DATA 4   0x40AB0014 0x00C700DB
+DATA 4   0x40AB0018 0x00211708
+DATA 4   0x40AB002C 0x0F9F26D2
+DATA 4   0x40AB0030 0x009F0E10
+DATA 4   0x40AB0040 0x0000003F
+DATA 4   0x40AB0000 0xC3110000
+
+DATA 4   0x40AB001C 0x00008010
+DATA 4   0x40AB001C 0x00008018
+DATA 4   0x40AB001C 0x003F8030
+DATA 4   0x40AB001C 0x003F8038
+DATA 4   0x40AB001C 0xFF0A8030
+DATA 4   0x40AB001C 0xFF0A8038
+DATA 4   0x40AB001C 0x04028030
+DATA 4   0x40AB001C 0x04028038
+DATA 4   0x40AB001C 0x82018030
+DATA 4   0x40AB001C 0x82018038
+DATA 4   0x40AB001C 0x01038030
+DATA 4   0x40AB001C 0x01038038
+
+DATA 4   0x40AB083C 0x20000000
+
+DATA 4   0x40AB0020 0x00001800
+DATA 4   0x40AB0800 0xA1390003
+DATA 4   0x40AB0004 0x00020052
+DATA 4   0x40AB0404 0x00011006
+DATA 4   0x40AB001C 0x00000000
+
+#endif
diff --git a/board/freescale/mx7ulp_val/mx7ulp_val.c b/board/freescale/mx7ulp_val/mx7ulp_val.c
new file mode 100644
index 00000000000..d1e03a20183
--- /dev/null
+++ b/board/freescale/mx7ulp_val/mx7ulp_val.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mx7ulp-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/gpio.h>
+#include <usb.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_PUS_UP)
+
+#define GPIO_PAD_CTRL	(PAD_CTL_OBE_ENABLE | PAD_CTL_IBE_ENABLE)
+
+#define OTG_ID_GPIO_PAD_CTRL	(PAD_CTL_IBE_ENABLE)
+#define OTG_PWR_GPIO_PAD_CTRL	(PAD_CTL_OBE_ENABLE)
+
+#define QSPI_PAD_CTRL1	(PAD_CTL_PUS_UP | PAD_CTL_DSE)
+
+#define QSPI_PAD_CTRL0	(PAD_CTL_PUS_UP | PAD_CTL_DSE \
+	| PAD_CTL_OBE_ENABLE)
+
+
+int dram_init(void)
+{
+    gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL
+/* PTF11 and PTF10 also can mux to LPUART6 on 10x10 validation, depends on rework*/
+static iomux_cfg_t const lpuart6_pads[] = {
+    MX7ULP_PAD_PTE11__LPUART6_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+    MX7ULP_PAD_PTE10__LPUART6_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+#else
+static iomux_cfg_t const lpuart4_pads[] = {
+    MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+    MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+#endif
+
+static void setup_iomux_uart(void)
+{
+#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL
+	mx7ulp_iomux_setup_multiple_pads(lpuart6_pads, ARRAY_SIZE(lpuart6_pads));
+#else
+    mx7ulp_iomux_setup_multiple_pads(lpuart4_pads, ARRAY_SIZE(lpuart4_pads));
+#endif
+}
+
+#ifdef CONFIG_USB_EHCI_MX7
+
+static iomux_cfg_t const usb_otg1_pads[] = {
+
+#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
+	MX7ULP_PAD_PTC0__PTC0 | MUX_PAD_CTRL(OTG_ID_GPIO_PAD_CTRL),  /* gpio for otgid */
+	MX7ULP_PAD_PTC1__PTC1 | MUX_PAD_CTRL(OTG_PWR_GPIO_PAD_CTRL),  /* gpio for power en */
+#else
+	/*Need rework for ID and PWR_EN pins on 14x14 ARM2*/
+	MX7ULP_PAD_PTC18__PTC18 | MUX_PAD_CTRL(OTG_ID_GPIO_PAD_CTRL),  /* gpio for otgid */
+	MX7ULP_PAD_PTA31__PTA31 | MUX_PAD_CTRL(OTG_PWR_GPIO_PAD_CTRL),  /* gpio for power en */
+#endif
+};
+
+#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL
+#define OTG0_ID_GPIO	IMX_GPIO_NR(3, 0)
+#define OTG0_PWR_EN		IMX_GPIO_NR(3, 1)
+#else
+#define OTG0_ID_GPIO	IMX_GPIO_NR(3, 18)
+#define OTG0_PWR_EN		IMX_GPIO_NR(1, 31)
+#endif
+static void setup_usb(void)
+{
+	mx7ulp_iomux_setup_multiple_pads(usb_otg1_pads,
+						 ARRAY_SIZE(usb_otg1_pads));
+
+	gpio_request(OTG0_ID_GPIO, "otg_id");
+	gpio_direction_input(OTG0_ID_GPIO);
+}
+
+/*Needs to override the ehci power if controlled by GPIO */
+int board_ehci_power(int port, int on)
+{
+	switch (port) {
+	case 0:
+		if (on)
+			gpio_direction_output(OTG0_PWR_EN, 1);
+		else
+			gpio_direction_output(OTG0_PWR_EN, 0);
+		break;
+	default:
+		printf("MXC USB port %d not yet supported\n", port);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int board_usb_phy_mode(int port)
+{
+	int ret = 0;
+
+	if (port == 0) {
+		ret = gpio_get_value(OTG0_ID_GPIO);
+
+		if (ret)
+			return USB_INIT_DEVICE;
+		else
+			return USB_INIT_HOST;
+	}
+
+	return USB_INIT_HOST;
+}
+
+#endif
+
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_QSPI
+#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL
+static iomux_cfg_t const quadspi_pads[] = {
+	MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
+	MX7ULP_PAD_PTB14__QSPIA_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
+	MX7ULP_PAD_PTB15__QSPIA_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
+	MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+
+	MX7ULP_PAD_PTB5__PTB5 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+#define QSPI_RST_GPIO	IMX_GPIO_NR(2, 5)
+#else
+/* MT35XU512ABA supports 8 bits I/O, since our driver only support 4, so mux 4 data pins*/
+static iomux_cfg_t const quadspi_pads[] = {
+	MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
+	MX7ULP_PAD_PTB9__QSPIA_DQS   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB15__QSPIA_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
+	MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+
+	MX7ULP_PAD_PTB12__PTB12 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+#define QSPI_RST_GPIO	IMX_GPIO_NR(2, 12)
+
+#endif
+int board_qspi_init(void)
+{
+	u32 val;
+	mx7ulp_iomux_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
+	/* enable clock */
+	val = readl(PCC1_RBASE + 0x94);
+
+	if (!(val & 0x20000000)) {
+		writel(0x03000003, (PCC1_RBASE + 0x94));
+		writel(0x43000003, (PCC1_RBASE + 0x94));
+	}
+
+	/* Enable QSPI as a wakeup source on B0 */
+	if (soc_rev() >= CHIP_REV_2_0)
+		setbits_le32(SIM0_RBASE + WKPU_WAKEUP_EN, WKPU_QSPI_CHANNEL);
+
+	gpio_request(QSPI_RST_GPIO, "qspi_reset");
+	gpio_direction_output(QSPI_RST_GPIO, 0);
+	mdelay(10);
+	gpio_direction_output(QSPI_RST_GPIO, 1);
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_USB_EHCI_MX7
+	setup_usb();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+    return 0;
+}
+
+int checkboard(void)
+{
+#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL
+	printf("Board: i.MX7ULP 10x10 Validation board\n");
+#else
+	printf("Board: i.MX7ULP 14x14 Validation board\n");
+#endif
+	return 0;
+}
diff --git a/board/freescale/mx7ulp_val/plugin.S b/board/freescale/mx7ulp_val/plugin.S
new file mode 100644
index 00000000000..554ee8fe828
--- /dev/null
+++ b/board/freescale/mx7ulp_val/plugin.S
@@ -0,0 +1,352 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+.macro imx7ulp_ddr_freq_decrease
+	ldr r2, =0x403f0000
+	ldr r3, =0x00000000
+	str r3, [r2, #0xe0]
+
+	ldr r2, =0x403e0000
+	ldr r3, =0x01000020
+	str r3, [r2, #0x40]
+	ldr r3, =0x01000000
+	str r3, [r2, #0x500]
+
+	ldr r3, =0x80808080
+	str r3, [r2, #0x50c]
+	ldr r3, =0x00160002
+	str r3, [r2, #0x508]
+	ldr r3, =0x00000000
+	str r3, [r2, #0x510]
+	ldr r3, =0x00000001
+	str r3, [r2, #0x514]
+	ldr r3, =0x00000001
+	str r3, [r2, #0x500]
+
+	ldr r3, =0x01000000
+wait1:
+	ldr r4, [r2, #0x500]
+	and r4, r3
+	cmp r4, r3
+	bne wait1
+
+	ldr r3, =0x80808019
+	str r3, [r2, #0x50c]
+
+	ldr r3, =0x00000040
+wait2:
+	ldr r4, [r2, #0x50c]
+	and r4, r3
+	cmp r4, r3
+	bne wait2
+
+	ldr r3, =0x00000001
+	str r3, [r2, #0x30]
+	ldr r3, =0x11000020
+	str r3, [r2, #0x40]
+
+	ldr r2, =0x403f0000
+	ldr r3, =0x42000000
+	str r3, [r2, #0xe0]
+
+.endm
+
+.macro imx7ulp_arm2_lpddr3_setting
+
+	imx7ulp_ddr_freq_decrease
+
+	/* Enable MMDC PCC clock */
+	ldr r2, =0x40b30000
+	ldr r3, =0x40000000
+	str r3, [r2, #0xac]
+
+	/* Configure DDR pad */
+	ldr r0, =0x40ad0000
+	ldr r1, =0x00040000
+	str r1, [r0, #0x128]
+	ldr r1, =0x0
+	str r1, [r0, #0xf8]
+	ldr r1, =0x00000180
+	str r1, [r0, #0xd8]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x108]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x104]
+	ldr r1, =0x00010000
+	str r1, [r0, #0x124]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x80]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x84]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x88]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x8c]
+
+	ldr r1, =0x00010000
+	str r1, [r0, #0x120]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x10c]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x110]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x114]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x118]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x90]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x94]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x98]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x9c]
+	ldr r1, =0x00040000
+	str r1, [r0, #0xe0]
+	ldr r1, =0x00040000
+	str r1, [r0, #0xe4]
+
+	ldr r0, =0x40ab0000
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1c]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x0D3900A0
+	str r1, [r0, #0x85c]
+	ldr r1, =0x00400000
+	str r1, [r0, #0x890]
+
+	ldr r1, =0x39373939
+	str r1, [r0, #0x848]
+	ldr r1, =0x2F313D36
+	str r1, [r0, #0x850]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81c]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x820]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x824]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x828]
+
+	ldr r1, =0x24922492
+	str r1, [r0, #0x8c0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8b8]
+
+	ldr r1, =0x00020052
+	str r1, [r0, #0x4]
+	ldr r1, =0x424642F3
+	str r1, [r0, #0xc]
+	ldr r1, =0x00100A22
+	str r1, [r0, #0x10]
+	ldr r1, =0x00120556
+	str r1, [r0, #0x38]
+	ldr r1, =0x00C700DA
+	str r1, [r0, #0x14]
+	ldr r1, =0x00211718
+	str r1, [r0, #0x18]
+
+	ldr r1, =0x0F9F26D2
+	str r1, [r0, #0x2c]
+	ldr r1, =0x009F0E10
+	str r1, [r0, #0x30]
+	ldr r1, =0x0000004F
+	str r1, [r0, #0x40]
+	ldr r1, =0x84190000
+	str r1, [r0, #0x0]
+
+	ldr r1, =0x00008010
+	str r1, [r0, #0x1c]
+	ldr r1, =0x003F8030
+	str r1, [r0, #0x1c]
+	ldr r1, =0xFF0A8030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x04028030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x83018030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x01038030
+	str r1, [r0, #0x1c]
+
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83c]
+
+	ldr r1, =0x00001800
+	str r1, [r0, #0x20]
+	ldr r1, =0xA1310003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x1c]
+
+.endm
+
+.macro imx7ulp_arm2_lpddr2_setting
+
+	imx7ulp_ddr_freq_decrease
+
+	/* Enable MMDC PCC clock */
+	ldr r2, =0x40b30000
+	ldr r3, =0x40000000
+	str r3, [r2, #0xac]
+
+	/* Configure DDR pad */
+	ldr r0, =0x40ad0000
+	ldr r1, =0x00040000
+	str r1, [r0, #0x128]
+	ldr r1, =0x0
+	str r1, [r0, #0xf8]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0xd8]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x108]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x104]
+	ldr r1, =0x00010000
+	str r1, [r0, #0x124]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x80]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x84]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x88]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x8c]
+
+	ldr r1, =0x00010000
+	str r1, [r0, #0x120]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x10c]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x110]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x114]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x118]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x90]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x94]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x98]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x9c]
+	ldr r1, =0x00040000
+	str r1, [r0, #0xe0]
+	ldr r1, =0x00040000
+	str r1, [r0, #0xe4]
+
+	ldr r0, =0x40ab0000
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1c]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x0D3900A0
+	str r1, [r0, #0x85c]
+	ldr r1, =0x00400000
+	str r1, [r0, #0x890]
+
+	ldr r1, =0x40404040
+	str r1, [r0, #0x848]
+	ldr r1, =0x40404040
+	str r1, [r0, #0x850]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81c]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x820]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x824]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x828]
+
+	ldr r1, =0x24922492
+	str r1, [r0, #0x8c0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8b8]
+
+	ldr r1, =0x00020052
+	str r1, [r0, #0x4]
+	ldr r1, =0x292C42F3
+	str r1, [r0, #0xc]
+	ldr r1, =0x00100A22
+	str r1, [r0, #0x10]
+	ldr r1, =0x00120556
+	str r1, [r0, #0x38]
+	ldr r1, =0x00C700DB
+	str r1, [r0, #0x14]
+	ldr r1, =0x00211708
+	str r1, [r0, #0x18]
+
+	ldr r1, =0x0F9F26D2
+	str r1, [r0, #0x2c]
+	ldr r1, =0x009F0E10
+	str r1, [r0, #0x30]
+	ldr r1, =0x0000003F
+	str r1, [r0, #0x40]
+	ldr r1, =0xC3110000
+	str r1, [r0, #0x0]
+
+	ldr r1, =0x00008010
+	str r1, [r0, #0x1c]
+	ldr r1, =0x00008018
+	str r1, [r0, #0x1c]
+	ldr r1, =0x003F8030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x003F8038
+	str r1, [r0, #0x1c]
+	ldr r1, =0xFF0A8030
+	str r1, [r0, #0x1c]
+	ldr r1, =0xFF0A8038
+	str r1, [r0, #0x1c]
+	ldr r1, =0x04028030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x04028038
+	str r1, [r0, #0x1c]
+	ldr r1, =0x82018030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x82018038
+	str r1, [r0, #0x1c]
+	ldr r1, =0x01038030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x01038038
+	str r1, [r0, #0x1c]
+
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83c]
+
+	ldr r1, =0x00001800
+	str r1, [r0, #0x20]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00020052
+	str r1, [r0, #0x4]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x1c]
+
+.endm
+
+
+.macro imx7ulp_clock_gating
+.endm
+
+.macro imx7ulp_qos_setting
+.endm
+
+.macro imx7ulp_ddr_setting
+#if defined (CONFIG_TARGET_MX7ULP_10X10_VAL)
+	imx7ulp_arm2_lpddr2_setting
+#else
+	imx7ulp_arm2_lpddr3_setting
+#endif
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx7ulp_plugin.S>
diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c
index 3c48a9141d0..17bb4577363 100644
--- a/board/kontron/sl28/sl28.c
+++ b/board/kontron/sl28/sl28.c
@@ -31,9 +31,6 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-	if (CONFIG_IS_ENABLED(FSL_CAAM))
-		sec_init();
-
 	return 0;
 }
 
diff --git a/boot/image-android.c b/boot/image-android.c
index 1fbbbba1eb0..70adca82c9d 100644
--- a/boot/image-android.c
+++ b/boot/image-android.c
@@ -1,6 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (c) 2011 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
+ *
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  */
 
 #include <common.h>
@@ -13,11 +16,92 @@
 #include <asm/unaligned.h>
 #include <mapmem.h>
 #include <linux/libfdt.h>
+#include <asm/bootm.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/sys_proto.h>
+#include <fb_fsl.h>
+#include <asm/setup.h>
+#include <dm.h>
+#include <init.h>
+#include <mmc.h>
 
 #define ANDROID_IMAGE_DEFAULT_KERNEL_ADDR	0x10008000
+#define COMMANDLINE_LENGTH			2048
+#define BOOTCONFIG_MAGIC "#BOOTCONFIG\n"
+#define BOOTCONFIG_MAGIC_SIZE 12
+#define BOOTCONFIG_SIZE_SIZE 4
+#define BOOTCONFIG_CHECKSUM_SIZE 4
+#define BOOTCONFIG_TRAILER_SIZE BOOTCONFIG_MAGIC_SIZE + \
+				BOOTCONFIG_SIZE_SIZE + \
+				BOOTCONFIG_CHECKSUM_SIZE
 
 static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1];
 
+/*
+ * Simple checksum for a buffer.
+ *
+ * @param addr pointer to the start of the buffer.
+ * @param size size of the buffer in bytes.
+ * @return check sum result.
+ */
+static uint32_t checksum(const unsigned char* const buffer, uint32_t size)
+{
+	uint32_t sum = 0;
+	for (uint32_t i = 0; i < size; i++) {
+		sum += buffer[i];
+	}
+	return sum;
+}
+
+/*
+ * Check if the bootconfig trailer is present within the bootconfig section.
+ *
+ */
+static bool trailer_exist(uint64_t bootconfig_end_addr)
+{
+	return !strncmp((char*)(ulong)(bootconfig_end_addr - BOOTCONFIG_MAGIC_SIZE),
+			BOOTCONFIG_MAGIC, BOOTCONFIG_MAGIC_SIZE);
+}
+
+/*
+ * Insert the bootconfig trailer. The trailer should have:
+ * parameter size - 4 bytes
+ * checksum of the section - 4 bytes
+ * magic #BOOTCONFIG\n - 12 bytes
+ */
+int32_t add_bootconfig_trailer(uint64_t bootconfig_start_addr, uint32_t bootconfig_size)
+{
+	uint64_t end;
+	uint32_t sum;
+
+	if (bootconfig_start_addr == 0) {
+		return -1;
+	}
+	if (bootconfig_size == 0) {
+		return 0;
+	}
+
+	end = bootconfig_start_addr + bootconfig_size;
+
+	if (trailer_exist(end)) {
+	// do nothing.
+		return 0;
+	}
+
+	// copy the size
+	memcpy((void *)(ulong)(end), &bootconfig_size, BOOTCONFIG_SIZE_SIZE);
+
+	// add checksum
+	sum = checksum((unsigned char*)(ulong)bootconfig_start_addr, bootconfig_size);
+	memcpy((void *)(ulong)(end + BOOTCONFIG_SIZE_SIZE), &sum, BOOTCONFIG_CHECKSUM_SIZE);
+
+	// add the magic
+	memcpy((void *)(ulong)(end + BOOTCONFIG_SIZE_SIZE + BOOTCONFIG_CHECKSUM_SIZE),
+		BOOTCONFIG_MAGIC, BOOTCONFIG_MAGIC_SIZE);
+
+	return BOOTCONFIG_TRAILER_SIZE;
+}
+
 static ulong android_image_get_kernel_addr(const struct andr_img_hdr *hdr)
 {
 	/*
@@ -44,6 +128,215 @@ static ulong android_image_get_kernel_addr(const struct andr_img_hdr *hdr)
 	return hdr->kernel_addr;
 }
 
+/*
+ * The parameters start with androidboot.* should be used
+ * by android userspace, let's handle them here.
+ * */
+static int append_androidboot_args(char *args, uint32_t *len, void *fdt_addr)
+{
+	char args_buf[512] = {0};
+	extern boot_metric metrics;
+
+#ifdef CONFIG_SERIAL_TAG
+	struct tag_serialnr serialnr;
+	get_board_serial(&serialnr);
+
+	sprintf(args_buf, " androidboot.serialno=%08x%08x", serialnr.high, serialnr.low);
+	strncat(args, args_buf, *len - strlen(args));
+
+	if (serialnr.high + serialnr.low != 0) {
+		char bd_addr[16]={0};
+		sprintf(bd_addr,
+			"%08x%08x",
+			serialnr.high,
+			serialnr.low);
+		sprintf(args_buf,
+			" androidboot.btmacaddr=%c%c:%c%c:%c%c:%c%c:%c%c:%c%c",
+			bd_addr[0],bd_addr[1],bd_addr[2],bd_addr[3],bd_addr[4],bd_addr[5],
+			bd_addr[6],bd_addr[7],bd_addr[8],bd_addr[9],bd_addr[10],bd_addr[11]);
+	} else {
+		/* Some boards have serial number as all zeros (imx8mp),
+		 * hard code the bt mac address for such case. */
+		sprintf(args_buf, " androidboot.btmacaddr=22:22:67:C6:69:73");
+	}
+
+	strncat(args, args_buf, *len - strlen(args));
+#endif
+
+	/* append soc type into bootargs */
+	char *soc_type = env_get("soc_type");
+	if (soc_type) {
+		sprintf(args_buf,
+			" androidboot.soc_type=%s",
+			soc_type);
+		strncat(args, args_buf, *len - strlen(args));
+	}
+	/* append soc rev into bootargs */
+	char *soc_rev = env_get("soc_rev");
+	if (soc_rev) {
+		sprintf(args_buf,
+			" androidboot.soc_rev=%s",
+			soc_rev);
+		strncat(args, args_buf, *len - strlen(args));
+	}
+
+	if (!fdt_addr) {
+		sprintf(args_buf,
+			" androidboot.boot_device_root=mmcblk%d", mmc_map_to_kernel_blk(mmc_get_env_dev()));
+		strncat(args, args_buf, *len - strlen(args));
+	} else {
+		char mmcblk[30];
+		char *boot_device = NULL;
+		int offset = -1;
+
+		/* The boot device should locates at "/firmware/android/"boot_devices_mmcblkX" */
+		offset = fdt_path_offset(fdt_addr, "/firmware/android");
+		if (offset > 0) {
+			sprintf(mmcblk, "boot_devices_mmcblk%d", mmc_map_to_kernel_blk(mmc_get_env_dev()));
+			boot_device = (char *)fdt_getprop(fdt_addr, offset, mmcblk, NULL);
+			if (boot_device) {
+				sprintf(args_buf,
+					" androidboot.boot_devices=%s", boot_device);
+				strncat(args, args_buf, *len - strlen(args));
+			} else {
+				printf("failed to get boot device from device tree!\n");
+				return -1;
+			}
+		} else {
+			printf("failed to get boot device from device tree!\n");
+			return -1;
+		}
+	}
+
+	/* boot metric variables */
+	metrics.ble_1 = get_timer(0);
+	sprintf(args_buf,
+		" androidboot.boottime=1BLL:%d,1BLE:%d,KL:%d,KD:%d,AVB:%d,ODT:%d,SW:%d",
+		metrics.bll_1, metrics.ble_1, metrics.kl, metrics.kd, metrics.avb,
+		metrics.odt, metrics.sw);
+	strncat(args, args_buf, *len - strlen(args));
+
+#if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) || \
+	defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8M)
+	char cause[18];
+
+	memset(cause, '\0', sizeof(cause));
+	get_reboot_reason(cause);
+	if (strstr(cause, "POR"))
+		sprintf(args_buf," androidboot.bootreason=cold,powerkey");
+	else if (strstr(cause, "WDOG") || strstr(cause, "WDG"))
+		sprintf(args_buf," androidboot.bootreason=watchdog");
+	else
+		sprintf(args_buf," androidboot.bootreason=reboot");
+#else
+	sprintf(args_buf," androidboot.bootreason=reboot");
+#endif
+	strncat(args, args_buf, *len - strlen(args));
+
+	/* VTS need this commandline to verify fdt overlay. Pass the
+	 * dtb index as "0" here since we only have one dtb in dtbo
+	 * partition and haven't enabled the dtb overlay.
+	 */
+#if defined(CONFIG_ANDROID_SUPPORT) || defined(CONFIG_ANDROID_AUTO_SUPPORT)
+	sprintf(args_buf," androidboot.dtbo_idx=0");
+	strncat(args, args_buf, *len - strlen(args));
+#endif
+
+	char *keystore = env_get("keystore");
+	char *bootargs_trusty;
+	if ((keystore == NULL) || strncmp(keystore, "trusty", sizeof("trusty"))) {
+		bootargs_trusty = " androidboot.keystore=software";
+	} else {
+		bootargs_trusty = " androidboot.keystore=trusty";
+	}
+	strncat(args, bootargs_trusty, *len - strlen(args));
+
+
+#ifdef CONFIG_AVB_SUPPORT
+	/* secondary cmdline added by avb */
+	char *bootargs_sec = env_get("bootargs_sec");
+	if (bootargs_sec) {
+		strncat(args, " ", *len - strlen(args));
+		strncat(args, bootargs_sec, *len - strlen(args));
+	}
+#endif
+
+	*len = strlen(args);
+
+	return 0;
+}
+
+static void append_kernel_cmdline(char *commandline)
+{
+	/* Add 'bootargs_ram_capacity' to hold the parameters based on different ram capacity */
+	char *bootargs_ram_capacity = env_get("bootargs_ram_capacity");
+	if (bootargs_ram_capacity) {
+		strncat(commandline, " ", COMMANDLINE_LENGTH - strlen(commandline));
+		strncat(commandline, bootargs_ram_capacity,
+			COMMANDLINE_LENGTH - strlen(commandline));
+	}
+
+#ifdef CONFIG_SYSTEM_RAMDISK_SUPPORT
+	/* Normal boot:
+	 * cmdline to bypass ramdisk in boot.img, but use the system.img
+	 * Recovery boot:
+	 * Use the ramdisk in boot.img
+	 */
+	char *bootargs_3rd = env_get("bootargs_3rd");
+	if (bootargs_3rd) {
+		strncat(commandline, " ", COMMANDLINE_LENGTH - strlen(commandline));
+		strncat(commandline, bootargs_3rd, COMMANDLINE_LENGTH - strlen(commandline));
+	}
+#endif
+
+#ifdef CONFIG_APPEND_BOOTARGS
+	/* Add 'append_bootargs' to hold some paramemters which need to be appended
+	 * to bootargs */
+	char *append_bootargs = env_get("append_bootargs");
+	if (append_bootargs) {
+		if (strlen(append_bootargs) + 2 >
+				(COMMANDLINE_LENGTH - strlen(commandline))) {
+			printf("The 'append_bootargs' is too long to be appended to bootargs\n");
+		} else {
+			strncat(commandline, " ", COMMANDLINE_LENGTH - strlen(commandline));
+			strncat(commandline, append_bootargs, COMMANDLINE_LENGTH - strlen(commandline));
+		}
+	}
+#endif
+}
+
+int append_runtime_bootconfig(char *bootconfig, uint32_t *size, void *fdt_addr)
+{
+	char buffer[COMMANDLINE_LENGTH] = {0};
+	char *ptr = buffer;
+	uint32_t len = COMMANDLINE_LENGTH;
+	int i = 0;
+
+	if (append_androidboot_args(buffer, &len, fdt_addr) < 0)
+		return -1;
+	/* +1 because we will append "\n" to the buffer end */
+	if (len + 1 > COMMANDLINE_LENGTH) {
+		printf("Error - buffer overflow!\n");
+		return -1;
+	}
+	/*
+	 * The parameters in bootconfig should be separated by
+	 * newline escape sequence '\n' instead of space. Replace
+	 * all space with "\n" here
+	 */
+	for (i = 0; i < len; i++) {
+		if (*ptr == ' ')
+			*ptr = '\n';
+		ptr++;
+	}
+	*ptr = '\n';
+
+	/* append bootconfig */
+	memcpy(bootconfig, buffer, strlen(buffer));
+	*size = strlen(buffer);
+	return 0;
+}
+
 /**
  * android_image_get_kernel() - processes kernel part of Android boot images
  * @hdr:	Pointer to image header, which is at the start
@@ -62,6 +355,7 @@ static ulong android_image_get_kernel_addr(const struct andr_img_hdr *hdr)
 int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
 			     ulong *os_data, ulong *os_len)
 {
+	u32 len;
 	u32 kernel_addr = android_image_get_kernel_addr(hdr);
 	const struct image_header *ihdr = (const struct image_header *)
 		((uintptr_t)hdr + hdr->page_size);
@@ -79,31 +373,44 @@ int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
 	printf("Kernel load addr 0x%08x size %u KiB\n",
 	       kernel_addr, DIV_ROUND_UP(hdr->kernel_size, 1024));
 
-	int len = 0;
-	if (*hdr->cmdline) {
-		printf("Kernel command line: %s\n", hdr->cmdline);
-		len += strlen(hdr->cmdline);
-	}
-
+	char commandline[COMMANDLINE_LENGTH] = {0};
+	int offset;
 	char *bootargs = env_get("bootargs");
-	if (bootargs)
-		len += strlen(bootargs);
-
-	char *newbootargs = malloc(len + 2);
-	if (!newbootargs) {
-		puts("Error: malloc in android_image_get_kernel failed!\n");
-		return -ENOMEM;
-	}
-	*newbootargs = '\0';
 
 	if (bootargs) {
-		strcpy(newbootargs, bootargs);
-		strcat(newbootargs, " ");
+		if (strlen(bootargs) + 1 > sizeof(commandline)) {
+			printf("bootargs is too long!\n");
+			return -1;
+		}
+		else
+			strncpy(commandline, bootargs, sizeof(commandline) - 1);
+	} else {
+		offset = fdt_path_offset(gd->fdt_blob, "/chosen");
+		if (offset > 0) {
+			bootargs = (char *)fdt_getprop(gd->fdt_blob, offset,
+							"bootargs", NULL);
+			if (bootargs)
+				sprintf(commandline, "%s ", bootargs);
+		}
+
+		if (*hdr->cmdline) {
+			if (strlen(hdr->cmdline) + 1 >
+				COMMANDLINE_LENGTH - strlen(commandline)) {
+				printf("cmdline in bootimg is too long!\n");
+				return -1;
+			}
+			else
+				strncat(commandline, hdr->cmdline, COMMANDLINE_LENGTH - strlen(commandline));
+		}
 	}
-	if (*hdr->cmdline)
-		strcat(newbootargs, hdr->cmdline);
 
-	env_set("bootargs", newbootargs);
+	append_kernel_cmdline(commandline);
+	len = COMMANDLINE_LENGTH - strlen(commandline);
+	if (append_androidboot_args(commandline, &len, NULL) < 0)
+		return -1;
+
+	debug("Kernel command line: %s\n", commandline);
+	env_set("bootargs", commandline);
 
 	if (os_data) {
 		if (image_get_magic(ihdr) == IH_MAGIC) {
@@ -119,6 +426,91 @@ int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
 		else
 			*os_len = hdr->kernel_size;
 	}
+
+	return 0;
+}
+
+/**
+ * android_image_get_kernel_v3() - processes kernel part of Android boot images
+ * @hdr:	Pointer to boot image header, which is at the start
+ *			of the image.
+ * @vendor_hdr:	Pointer to vendor_boot image header, which is at the start
+ *			of the image.
+ * @bootconfig: bootconfig flag
+ * This function appends the kernel command line to the bootargs env variable.
+ *
+ * Return: Zero on success, otherwise on failure.
+ */
+int android_image_get_kernel_v3(const struct boot_img_hdr_v3 *hdr,
+				const struct vendor_boot_img_hdr_v3 *vendor_hdr, bool bootconfig)
+{
+	u32 len;
+	u32 kernel_addr = vendor_hdr->kernel_addr;
+
+	/*
+	 * Not all Android tools use the id field for signing the image with
+	 * sha1 (or anything) so we don't check it. It is not obvious that the
+	 * string is null terminated so we take care of this.
+	 */
+	strncpy(andr_tmp_str, (char *)(vendor_hdr->name), ANDR_VENDOR_BOOT_NAME_SIZE);
+	andr_tmp_str[ANDR_VENDOR_BOOT_NAME_SIZE] = '\0';
+	if (strlen(andr_tmp_str))
+		printf("Android's image name: %s\n", andr_tmp_str);
+
+	printf("Kernel load addr 0x%08x size %u KiB\n",
+	       kernel_addr, DIV_ROUND_UP(hdr->kernel_size, 1024));
+
+	char commandline[COMMANDLINE_LENGTH] = {0};
+	int offset;
+	char *bootargs = env_get("bootargs");
+
+	if (bootargs) {
+		if (strlen(bootargs) + 1 > sizeof(commandline)) {
+			printf("bootargs is too long!\n");
+			return -1;
+		}
+		else
+			strncpy(commandline, bootargs, sizeof(commandline) - 1);
+	} else {
+		offset = fdt_path_offset(gd->fdt_blob, "/chosen");
+		if (offset > 0) {
+			bootargs = (char *)fdt_getprop(gd->fdt_blob, offset,
+							"bootargs", NULL);
+			if (bootargs)
+				sprintf(commandline, "%s ", bootargs);
+		}
+
+		if (*vendor_hdr->cmdline) {
+			if (strlen((char *)vendor_hdr->cmdline) + 1 >
+				COMMANDLINE_LENGTH - strlen(commandline)) {
+				printf("cmdline in vendor_boot image is too long!\n");
+				return -1;
+			}
+			else
+				strncat(commandline, (char *)(vendor_hdr->cmdline), COMMANDLINE_LENGTH - strlen(commandline));
+		}
+
+		if (*hdr->cmdline) {
+			if (strlen((char *)hdr->cmdline) + 1 >
+				COMMANDLINE_LENGTH - strlen(commandline)) {
+				printf("cmdline in bootimg is too long!\n");
+				return -1;
+			}
+			else
+				strncat(commandline, (char *)hdr->cmdline, COMMANDLINE_LENGTH - strlen(commandline));
+		}
+	}
+
+	append_kernel_cmdline(commandline);
+	if (!bootconfig) {
+		len = COMMANDLINE_LENGTH - strlen(commandline);
+		if (append_androidboot_args(commandline, &len, NULL) < 0)
+			return -1;
+	}
+
+	debug("Kernel command line: %s\n", commandline);
+	env_set("bootargs", commandline);
+
 	return 0;
 }
 
@@ -127,6 +519,12 @@ int android_image_check_header(const struct andr_img_hdr *hdr)
 	return memcmp(ANDR_BOOT_MAGIC, hdr->magic, ANDR_BOOT_MAGIC_SIZE);
 }
 
+int android_image_check_header_v3(uint8_t *boot_magic, uint8_t * vendor_boot_magic)
+{
+	return memcmp(ANDR_BOOT_MAGIC, boot_magic, ANDR_BOOT_MAGIC_SIZE) ||
+		memcmp(ANDR_VENDOR_BOOT_MAGIC, vendor_boot_magic, ANDR_VENDOR_BOOT_MAGIC_SIZE);
+}
+
 ulong android_image_get_end(const struct andr_img_hdr *hdr)
 {
 	ulong end;
@@ -537,3 +935,44 @@ bool android_image_print_dtb_contents(ulong hdr_addr)
 	return true;
 }
 #endif
+
+#define ARM64_IMAGE_MAGIC      0x644d5241
+bool image_arm64(void *images)
+{
+	struct header_image *ih;
+
+	ih = (struct header_image *)images;
+	debug("image magic: %x\n", ih->magic);
+	if (ih->magic == le32_to_cpu(ARM64_IMAGE_MAGIC))
+		return true;
+	return false;
+}
+
+uint32_t kernel_size(void *images)
+{
+	struct header_image *ih;
+	uint32_t image_size;
+
+	ih = (struct header_image *)images;
+	image_size = le64_to_cpu(ih->image_size);
+
+	return image_size;
+}
+
+ulong kernel_relocate_addr(ulong images)
+{
+	struct header_image *ih;
+	ulong relocated_addr, text_offset;
+
+	ih = (struct header_image *)images;
+	text_offset = le64_to_cpu(ih->text_offset);
+
+	if (le64_to_cpu(ih->res1) & BIT(3))
+		relocated_addr = images - text_offset;
+	else
+		relocated_addr = gd->bd->bi_dram[0].start;
+
+	relocated_addr = ALIGN(relocated_addr, SZ_2M) + text_offset;
+
+	return relocated_addr;
+}
diff --git a/boot/image-fdt.c b/boot/image-fdt.c
index 692a9ad3e42..e86218d7903 100644
--- a/boot/image-fdt.c
+++ b/boot/image-fdt.c
@@ -79,7 +79,7 @@ static void boot_fdt_reserve_region(struct lmb *lmb, uint64_t addr,
 {
 	long ret;
 
-	ret = lmb_reserve_flags(lmb, addr, size, flags);
+	ret = lmb_reserve_overlap(lmb, addr, size, flags);
 	if (ret >= 0) {
 		debug("   reserving fdt memory region: addr=%llx size=%llx flags=%x\n",
 		      (unsigned long long)addr,
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 5e25e45fd28..f6bd71451bc 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -2017,6 +2017,7 @@ config CMD_AES
 
 config CMD_BLOB
 	bool "Enable the 'blob' command"
+	select FSL_BLOB
 	depends on !MX6ULL && !MX6SLL && !MX6SL
 	select IMX_HAB if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_IMX8M
 	help
@@ -2290,6 +2291,12 @@ config MTDPARTS_DEFAULT
 	  Defines a default MTD partitioning scheme in the Linux MTD command
 	  line partitions format
 
+config MTDPARTS_SKIP_INVALID
+	bool "Skip invalid devices and keep checking the next one"
+	depends on CMD_MTDPARTS
+	help
+	  Enable this feature will look for next device rather than quit.
+
 config CMD_REISER
 	bool "reiser - Access to reiserfs filesystems"
 	help
diff --git a/cmd/blob.c b/cmd/blob.c
index e2efae7a115..5c459b6f19f 100644
--- a/cmd/blob.c
+++ b/cmd/blob.c
@@ -21,10 +21,12 @@
  * @src:	- Address of data to be decapsulated
  * @dst:	- Address of data to be decapsulated
  * @len:	- Size of data to be decapsulated
+ * @keycolor    - Determines if the source data is covered (black key) or
+ *                plaintext.
  *
  * Returns zero on success,and negative on error.
  */
-__weak int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
+__weak int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len, u8 keycolor)
 {
 	return 0;
 }
@@ -35,10 +37,12 @@ __weak int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
  * @src:	- Address of data to be encapsulated
  * @dst:	- Address of data to be encapsulated
  * @len:	- Size of data to be encapsulated
+ * @keycolor    - Determines if the source data is covered (black key) or
+ *                plaintext.
  *
  * Returns zero on success,and negative on error.
  */
-__weak int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
+__weak int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len, u8 keycolor)
 {
 	return 0;
 }
@@ -91,9 +95,9 @@ static int do_blob(struct cmd_tbl *cmdtp, int flag, int argc,
 #endif
 
 	if (enc)
-		ret = blob_encap(km_ptr, src_ptr, dst_ptr, len);
+		ret = blob_encap(km_ptr, src_ptr, dst_ptr, len, 0);
 	else
-		ret = blob_decap(km_ptr, src_ptr, dst_ptr, len);
+		ret = blob_decap(km_ptr, src_ptr, dst_ptr, len, 0);
 
 	return ret;
 }
diff --git a/cmd/bmp.c b/cmd/bmp.c
index 071ba90b435..986a843958b 100644
--- a/cmd/bmp.c
+++ b/cmd/bmp.c
@@ -20,6 +20,7 @@
 #include <mapmem.h>
 #include <splash.h>
 #include <video.h>
+#include <video_link.h>
 #include <asm/byteorder.h>
 
 static int bmp_info (ulong addr);
@@ -255,8 +256,15 @@ int bmp_display(ulong addr, int x, int y)
 	addr = map_to_sysmem(bmp);
 
 #ifdef CONFIG_DM_VIDEO
+#ifdef CONFIG_VIDEO_LINK
+	dev = video_link_get_video_device();
+	if (!dev) {
+		ret = -ENODEV;
+	} else {
+#else
 	ret = uclass_first_device_err(UCLASS_VIDEO, &dev);
 	if (!ret) {
+#endif
 		bool align = false;
 
 		if (CONFIG_IS_ENABLED(SPLASH_SCREEN_ALIGN) ||
diff --git a/cmd/booti.c b/cmd/booti.c
index 397d4b83236..d820930fe8c 100644
--- a/cmd/booti.c
+++ b/cmd/booti.c
@@ -78,6 +78,16 @@ static int booti_start(struct cmd_tbl *cmdtp, int flag, int argc,
 	if (ret != 0)
 		return 1;
 
+#if defined(CONFIG_IMX_HAB) && !defined(CONFIG_AVB_SUPPORT)
+	extern int authenticate_image(
+		uint32_t ddr_start, uint32_t raw_image_size);
+	if (authenticate_image(ld, image_size) != 0) {
+		printf("Authenticate Image Fail, Please check\n");
+		return 1;
+	}
+
+#endif
+
 	/* Handle BOOTM_STATE_LOADOS */
 	if (relocated_addr != ld) {
 		printf("Moving Image from 0x%lx to 0x%lx, end=%lx\n", ld,
diff --git a/cmd/bootm.c b/cmd/bootm.c
index e8b70668882..0c5585b123a 100644
--- a/cmd/bootm.c
+++ b/cmd/bootm.c
@@ -125,6 +125,67 @@ int do_bootm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 			return do_bootm_subcommand(cmdtp, flag, argc, argv);
 	}
 
+#ifdef CONFIG_IMX_HAB
+	extern int authenticate_image(
+			uint32_t ddr_start, uint32_t raw_image_size);
+
+#ifdef CONFIG_IMX_OPTEE
+	ulong tee_addr = 0;
+	int ret;
+	ulong zi_start, zi_end;
+
+	tee_addr = env_get_ulong("tee_addr", 16, tee_addr);
+	if (!tee_addr) {
+		printf("Not valid tee_addr, Please check\n");
+		return 1;
+	}
+
+	switch (genimg_get_format((const void *)tee_addr)) {
+	case IMAGE_FORMAT_LEGACY:
+		if (authenticate_image(tee_addr,
+		       image_get_image_size((image_header_t *)tee_addr)) != 0) {
+		       printf("Authenticate uImage Fail, Please check\n");
+		       return 1;
+		}
+		break;
+	default:
+		printf("Not valid image format for Authentication, Please check\n");
+		return 1;
+	};
+
+	ret = bootz_setup(image_load_addr, &zi_start, &zi_end);
+	if (ret != 0)
+		return 1;
+
+	if (authenticate_image(image_load_addr, zi_end - zi_start) != 0) {
+		printf("Authenticate zImage Fail, Please check\n");
+		return 1;
+	}
+
+#else
+
+	switch (genimg_get_format((const void *)image_load_addr)) {
+#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
+	case IMAGE_FORMAT_LEGACY:
+		if (authenticate_image(image_load_addr,
+			image_get_image_size((image_header_t *)image_load_addr)) != 0) {
+			printf("Authenticate uImage Fail, Please check\n");
+			return 1;
+		}
+		break;
+#endif
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+	case IMAGE_FORMAT_ANDROID:
+		/* Do this authentication in boota command */
+		break;
+#endif
+	default:
+		printf("Not valid image format for Authentication, Please check\n");
+		return 1;
+	}
+#endif
+#endif
+
 	return do_bootm_states(cmdtp, flag, argc, argv, BOOTM_STATE_START |
 		BOOTM_STATE_FINDOS | BOOTM_STATE_FINDOTHER |
 		BOOTM_STATE_LOADOS |
diff --git a/cmd/bootz.c b/cmd/bootz.c
index 4f024bde5fe..78c21d47400 100644
--- a/cmd/bootz.c
+++ b/cmd/bootz.c
@@ -57,6 +57,14 @@ static int bootz_start(struct cmd_tbl *cmdtp, int flag, int argc,
 	if (bootm_find_images(flag, argc, argv, images->ep, zi_end - zi_start))
 		return 1;
 
+#ifdef CONFIG_IMX_HAB
+	extern int authenticate_image(
+			uint32_t ddr_start, uint32_t raw_image_size);
+	if (authenticate_image(images->ep, zi_end - zi_start) != 0) {
+		printf("Authenticate zImage Fail, Please check\n");
+		return 1;
+	}
+#endif
 	return 0;
 }
 
diff --git a/cmd/fastboot.c b/cmd/fastboot.c
index 033a2c95e8f..7d3dbb1bf48 100644
--- a/cmd/fastboot.c
+++ b/cmd/fastboot.c
@@ -42,15 +42,27 @@ static int do_fastboot_usb(int argc, char *const argv[],
 	char *usb_controller;
 	char *endp;
 	int ret;
+	int index;
 
 	if (argc < 2)
 		return CMD_RET_USAGE;
 
-	usb_controller = argv[1];
-	controller_index = simple_strtoul(usb_controller, &endp, 0);
-	if (*endp != '\0') {
-		pr_err("Error: Wrong USB controller index format\n");
-		return CMD_RET_FAILURE;
+	if (!strcmp(argv[1], "auto")) {
+		index = board_usb_gadget_port_auto();
+		if (index >= 0)
+			controller_index = index;
+		else
+			return CMD_RET_USAGE;
+	} else {
+		usb_controller = argv[1];
+		controller_index = simple_strtoul(usb_controller, &endp, 0);
+		if (*endp != '\0') {
+			pr_err("Error: Wrong USB controller index format\n");
+			return CMD_RET_FAILURE;
+		}
+#ifdef CONFIG_FASTBOOT_USB_DEV
+		controller_index = CONFIG_FASTBOOT_USB_DEV;
+#endif
 	}
 
 	ret = usb_gadget_initialize(controller_index);
diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c
index bab75a262f3..83a7de4b3e6 100644
--- a/cmd/mtdparts.c
+++ b/cmd/mtdparts.c
@@ -160,6 +160,40 @@ static struct part_info* mtd_part_info(struct mtd_device *dev, unsigned int part
 static struct mtdids* id_find_by_mtd_id(const char *mtd_id, unsigned int mtd_id_len);
 static int device_del(struct mtd_device *dev);
 
+#ifdef CONFIG_MTDPARTS_SKIP_INVALID
+int skip_counter = 0;
+/*
+ * find a seperator to locate the next entry
+ * @param p pointer of the pointer of input char string
+ * @param sp seperator charactor
+ * @param n find the nth seperator
+ * @param limit the looking scope
+ * @return 1 on success, otherwise 0
+ */
+static int find_seperator(const char **p, char sp, int n, int limit)
+{
+	int i, j;
+
+	/* n = 0 means do nothing */
+	if (!n)
+		return 1;
+
+	i = j = 0;
+
+	while (*p && (**p != '\0') && (i < limit)) {
+		if (**p == sp) {
+			(*p)++;
+			j++;
+			if (j == n)
+				return 1;
+		}
+		(*p)++;
+		i++;
+	}
+
+	return 0;
+}
+#endif
 /**
  * Parses a string into a number.  The number stored at ptr is
  * potentially suffixed with K (for kilobytes, or 1024 bytes),
@@ -1578,6 +1612,12 @@ static int parse_mtdparts(const char *const mtdparts)
 
 	while (*p != '\0') {
 		err = 1;
+#ifdef CONFIG_MTDPARTS_SKIP_INVALID
+		if (!find_seperator(&p, ';', skip_counter, MTDPARTS_MAXLEN)) {
+			printf("goes wrong when skip invalid parts\n");
+			return 1;
+		}
+#endif
 		if ((device_parse(p, &p, &dev) != 0) || (!dev))
 			break;
 
@@ -1648,8 +1688,20 @@ static int parse_mtdids(const char *const ids)
 		p++;
 
 		/* check if requested device exists */
-		if (mtd_device_validate(type, num, &size) != 0)
+		if (mtd_device_validate(type, num, &size) != 0) {
+#ifdef CONFIG_MTDPARTS_SKIP_INVALID
+			if (find_seperator(&p, ',', 1, MTDIDS_MAXLEN)) {
+				printf("current device is invalid, skip it and check the next one\n");
+				skip_counter++;
+				continue;
+			} else {
+				printf("the only deivce is invalid\n");
+				return 1;
+			}
+#else
 			return 1;
+#endif
+		}
 
 		/* locate <mtd-id> */
 		mtd_id = p;
diff --git a/cmd/read.c b/cmd/read.c
index 99c7e3854e1..e573073a19b 100644
--- a/cmd/read.c
+++ b/cmd/read.c
@@ -12,7 +12,7 @@
 #include <command.h>
 #include <part.h>
 
-int do_read(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+int do_raw_read(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
 	char *ep;
 	struct blk_desc *dev_desc = NULL;
@@ -75,7 +75,7 @@ int do_read(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 }
 
 U_BOOT_CMD(
-	read,	6,	0,	do_read,
+	read,	6,	0,	do_raw_read,
 	"Load binary data from a partition",
 	"<interface> <dev[:part]> addr blk# cnt"
 );
diff --git a/cmd/sata.c b/cmd/sata.c
index 76da1906b7f..6a31d012a53 100644
--- a/cmd/sata.c
+++ b/cmd/sata.c
@@ -89,8 +89,10 @@ static int do_sata(struct cmd_tbl *cmdtp, int flag, int argc,
 
 		if (argc == 3)
 			devnum = (int)dectoul(argv[2], NULL);
-		if (!strcmp(argv[1], "stop"))
+		if (!strcmp(argv[1], "stop")) {
+			sata_curr_device = -1;
 			return sata_remove(devnum);
+		}
 
 		if (!strcmp(argv[1], "init")) {
 			if (sata_curr_device != -1) {
@@ -99,7 +101,11 @@ static int do_sata(struct cmd_tbl *cmdtp, int flag, int argc,
 					return rc;
 			}
 
-			return sata_probe(devnum);
+			rc = sata_probe(devnum);
+			if (rc < 0)
+				return CMD_RET_FAILURE;
+			sata_curr_device = rc;
+			return CMD_RET_SUCCESS;
 		}
 	}
 
diff --git a/common/autoboot.c b/common/autoboot.c
index b8861d56218..bb7511d4d5a 100644
--- a/common/autoboot.c
+++ b/common/autoboot.c
@@ -25,6 +25,9 @@
 #include <bootcount.h>
 #include <crypt.h>
 #include <dm/ofnode.h>
+#ifdef is_boot_from_usb
+#include <env.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -449,6 +452,21 @@ const char *bootdelay_process(void)
 	if (IS_ENABLED(CONFIG_OF_CONTROL))
 		bootdelay = ofnode_conf_read_int("bootdelay", bootdelay);
 
+#if defined(is_boot_from_usb)
+	if (is_boot_from_usb() && env_get("bootcmd_mfg")) {
+		disconnect_from_pc();
+		printf("Boot from USB for mfgtools\n");
+		bootdelay = 0;
+		env_set_default("Use default environment for \
+				 mfgtools\n", 0);
+	} else if (is_boot_from_usb()) {
+		printf("Boot from USB for uuu\n");
+		env_set("bootcmd", "fastboot 0");
+	} else {
+		printf("Normal Boot\n");
+	}
+#endif
+
 	debug("### main_loop entered: bootdelay=%d\n\n", bootdelay);
 
 	if (IS_ENABLED(CONFIG_AUTOBOOT_MENU_SHOW))
@@ -465,6 +483,13 @@ const char *bootdelay_process(void)
 	else
 		s = env_get("bootcmd");
 
+#if defined(is_boot_from_usb)
+	if (is_boot_from_usb() && env_get("bootcmd_mfg")) {
+		s = env_get("bootcmd_mfg");
+		printf("Run bootcmd_mfg: %s\n", s);
+	}
+#endif
+
 	if (IS_ENABLED(CONFIG_OF_CONTROL))
 		process_fdt_options(gd->fdt_blob);
 	stored_bootdelay = bootdelay;
diff --git a/common/board_f.c b/common/board_f.c
index a68760092ac..1a08b4676f2 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -857,7 +857,9 @@ static const init_fnc_t init_sequence_f[] = {
 #endif
 	env_init,		/* initialize environment */
 	init_baud_rate,		/* initialze baudrate settings */
+#ifndef CONFIG_ANDROID_AUTO_SUPPORT
 	serial_init,		/* serial communications setup */
+#endif
 	console_init_f,		/* stage 1 init of console */
 	display_options,	/* say that we are here */
 	display_text_info,	/* show debugging info if required */
diff --git a/common/board_r.c b/common/board_r.c
index c24d9b4e220..72e171a8229 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -61,6 +61,9 @@
 #include <wdt.h>
 #include <asm-generic/gpio.h>
 #include <efi_loader.h>
+#ifdef CONFIG_FSL_FASTBOOT
+#include <fb_fsl.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -574,6 +577,46 @@ static int dm_announce(void)
 	return 0;
 }
 
+#if defined(AVB_RPMB) && !defined(CONFIG_SPL)
+extern int init_avbkey(void);
+static int initr_avbkey(void)
+{
+	return init_avbkey();
+}
+#endif
+
+#ifdef CONFIG_FSL_FASTBOOT
+static int initr_fastboot_setup(void)
+{
+	fastboot_setup();
+	return 0;
+}
+
+static int initr_check_fastboot(void)
+{
+	fastboot_run_bootmode();
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+extern void tee_setup(void);
+static int initr_tee_setup(void)
+{
+	tee_setup();
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_DUAL_BOOTLOADER
+extern void check_spl_recovery(void);
+static int initr_check_spl_recovery(void)
+{
+	check_spl_recovery();
+	return 0;
+}
+#endif
+
 static int run_main_loop(void)
 {
 #ifdef CONFIG_SANDBOX
@@ -756,6 +799,9 @@ static init_fnc_t init_sequence_r[] = {
 #ifdef CONFIG_BOARD_LATE_INIT
 	board_late_init,
 #endif
+#ifdef CONFIG_FSL_FASTBOOT
+	initr_fastboot_setup,
+#endif
 #if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI)
 	INIT_FUNC_WATCHDOG_RESET
 	initr_scsi,
@@ -791,6 +837,18 @@ static init_fnc_t init_sequence_r[] = {
 #ifdef CONFIG_EFI_SETUP_EARLY
 	(init_fnc_t)efi_init_obj_list,
 #endif
+#if defined(AVB_RPMB) && !defined(CONFIG_SPL)
+	initr_avbkey,
+#endif
+#ifdef CONFIG_IMX_TRUSTY_OS
+	initr_tee_setup,
+#endif
+#ifdef CONFIG_FSL_FASTBOOT
+	initr_check_fastboot,
+#endif
+#ifdef CONFIG_DUAL_BOOTLOADER
+	initr_check_spl_recovery,
+#endif
 	run_main_loop,
 };
 
diff --git a/common/lcd.c b/common/lcd.c
index 16a0a7cea8f..9fc8ceba8cb 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -39,11 +39,6 @@
 #define CONFIG_LCD_ALIGNMENT PAGE_SIZE
 #endif
 
-#if (LCD_BPP != LCD_COLOR8) && (LCD_BPP != LCD_COLOR16) && \
-	(LCD_BPP != LCD_COLOR32)
-#error Unsupported LCD BPP.
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 static int lcd_init(void *lcdbase);
@@ -175,10 +170,13 @@ int drv_lcd_init(void)
 
 void lcd_clear(void)
 {
-	int bg_color;
 	__maybe_unused ulong addr;
 	static int do_splash = 1;
-#if LCD_BPP == LCD_COLOR8
+#if LCD_BPP == LCD_MONOCHROME
+	/* Setting the palette */
+	lcd_initcolregs();
+
+#elif LCD_BPP == LCD_COLOR8
 	/* Setting the palette */
 	lcd_setcolreg(CONSOLE_COLOR_BLACK, 0, 0, 0);
 	lcd_setcolreg(CONSOLE_COLOR_RED, 0xFF, 0, 0);
@@ -194,11 +192,9 @@ void lcd_clear(void)
 #ifndef CONFIG_SYS_WHITE_ON_BLACK
 	lcd_setfgcolor(CONSOLE_COLOR_BLACK);
 	lcd_setbgcolor(CONSOLE_COLOR_WHITE);
-	bg_color = CONSOLE_COLOR_WHITE;
 #else
 	lcd_setfgcolor(CONSOLE_COLOR_WHITE);
 	lcd_setbgcolor(CONSOLE_COLOR_BLACK);
-	bg_color = CONSOLE_COLOR_BLACK;
 #endif	/* CONFIG_SYS_WHITE_ON_BLACK */
 
 #ifdef	LCD_TEST_PATTERN
@@ -206,14 +202,15 @@ void lcd_clear(void)
 #else
 	/* set framebuffer to background color */
 #if (LCD_BPP != LCD_COLOR32)
-	memset((char *)lcd_base, bg_color, lcd_line_length * panel_info.vl_row);
+	memset((char *)lcd_base, COLOR_MASK(lcd_getbgcolor()),
+	       lcd_line_length * panel_info.vl_row);
 #else
 	u32 *ppix = lcd_base;
 	u32 i;
 	for (i = 0;
 	   i < (lcd_line_length * panel_info.vl_row)/NBYTES(panel_info.vl_bpix);
 	   i++) {
-		*ppix++ = bg_color;
+		*ppix++ = COLOR_MASK(lcd_getbgcolor());
 	}
 #endif
 #endif
@@ -286,7 +283,7 @@ ulong lcd_setmem(ulong addr)
 	ulong size;
 	int line_length;
 
-	debug("LCD panel info: %d x %d, %d bit/pix\n", panel_info.vl_col,
+	debug("LCD panel info: %lu x %lu, %d bit/pix\n", panel_info.vl_col,
 		panel_info.vl_row, NBITS(panel_info.vl_bpix));
 
 	size = lcd_get_size(&line_length);
diff --git a/common/lcd_console.c b/common/lcd_console.c
index ed36c78440c..2a08992d9aa 100644
--- a/common/lcd_console.c
+++ b/common/lcd_console.c
@@ -48,17 +48,34 @@ static void lcd_putc_xy0(struct console_t *pcons, ushort x, ushort y, char c)
 {
 	int fg_color = lcd_getfgcolor();
 	int bg_color = lcd_getbgcolor();
-	int i, row;
+	int row;
+#if LCD_BPP == LCD_MONOCHROME
+	ushort off  = x * (1 << LCD_BPP) % 8;
+#else
+	int i;
+#endif
+
 	fbptr_t *dst = (fbptr_t *)pcons->fbbase +
 				  y * pcons->lcdsizex +
 				  x;
 
 	for (row = 0; row < VIDEO_FONT_HEIGHT; row++) {
 		uchar bits = video_fontdata[c * VIDEO_FONT_HEIGHT + row];
+#if LCD_BPP == LCD_MONOCHROME
+		uchar rest = *dst & -(1 << (8 - off));
+		uchar sym;
+
+		sym  = (COLOR_MASK(fg_color) & bits) |
+			(COLOR_MASK(bg_color) & ~bits);
+		*dst++ = rest | (sym >> off);
+		rest = sym << (8 - off);
+		*dst  = rest | (*dst & ((1 << (8 - off)) - 1));
+#else /* LCD_BPP == LCD_COLOR8 or LCD_COLOR16 or LCD_COLOR32 */
 		for (i = 0; i < VIDEO_FONT_WIDTH; ++i) {
 			*dst++ = (bits & 0x80) ? fg_color : bg_color;
 			bits <<= 1;
 		}
+#endif
 		dst += (pcons->lcdsizex - VIDEO_FONT_WIDTH);
 	}
 }
@@ -116,7 +133,7 @@ static inline void console_newline(void)
 		for (i = 0; i < cons.rows-rows; i++)
 			cons.fp_console_moverow(&cons, i, i+rows);
 		for (i = 0; i < rows; i++)
-			cons.fp_console_setrow(&cons, cons.rows-i-1, bg_color);
+			cons.fp_console_setrow(&cons, cons.rows-i-1, COLOR_MASK(bg_color));
 		cons.curr_row -= rows;
 	}
 	lcd_sync();
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 9418d37b2e2..90b1ef4148d 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -208,7 +208,7 @@ config SPL_BOOTCOUNT_LIMIT
 
 config SPL_RAW_IMAGE_SUPPORT
 	bool "Support SPL loading and booting of RAW images"
-	default n if (ARCH_MX6 && (SPL_MMC || SPL_SATA))
+	default n if ((ARCH_MX6 && (SPL_MMC || SPL_SATA)) || ARCH_IMX8 || ARCH_IMX8M)
 	default y if !TI_SECURE_DEVICE
 	help
 	  SPL will support loading and booting a RAW image when this option
@@ -457,6 +457,7 @@ config SPL_FIT_IMAGE_TINY
 	depends on SPL_FIT
 	default y if MACH_SUN50I || MACH_SUN50I_H5 || SUN50I_GEN_H6
 	default y if ARCH_IMX8M
+	default y if ARCH_IMX9
 	help
 	  Enable this to reduce the size of the FIT image loading code
 	  in SPL, if space for the SPL binary is very tight.
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 1bbf824684a..9d5a6dccec2 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -35,7 +35,7 @@ struct spl_fit_info {
 	int conf_node;		/* FDT offset to selected configuration node */
 };
 
-__weak void board_spl_fit_post_load(const void *fit)
+__weak void board_spl_fit_post_load(const void *fit, struct spl_image_info *spl_image)
 {
 }
 
@@ -67,6 +67,10 @@ static int find_node_from_desc(const void *fit, int node, const char *str)
 	return -ENOENT;
 }
 
+#ifdef CONFIG_IMX_TRUSTY_OS
+extern int spl_fit_get_rbindex(const void *fit);
+#endif
+
 /**
  * spl_fit_get_image_name(): By using the matching configuration subnode,
  * retrieve the name of an image, specified by a property name and an index
@@ -218,6 +222,15 @@ static int get_aligned_image_size(struct spl_load_info *info, int data_size,
 	return (data_size + info->bl_len - 1) / info->bl_len;
 }
 
+#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_IMX_TRUSTY_OS)
+__weak int get_tee_load(ulong *load)
+{
+	/* default return ok */
+	return 0;
+}
+
+#endif
+
 /**
  * spl_load_fit_image(): load the image described in a certain FIT node
  * @info:	points to information about the device to load data from
@@ -272,6 +285,21 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector,
 		load_addr = image_info->load_addr;
 	}
 
+#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_IMX_TRUSTY_OS)
+	char *desc = NULL;
+
+	if (fit_get_desc(fit, node, &desc)) {
+		printf("can't found node description!\n");
+		return -ENOENT;
+	} else if (!strncmp(desc, "TEE firmware",
+				strlen("TEE firmware"))) {
+		if (get_tee_load(&load_addr)) {
+			printf("Failed to get TEE load address!\n");
+			return -ENOENT;
+		}
+	}
+#endif
+
 	if (!fit_image_get_data_position(fit, node, &offset)) {
 		external_data = true;
 	} else if (!fit_image_get_data_offset(fit, node, &offset)) {
@@ -713,6 +741,16 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
 	if (ret < 0)
 		return ret;
 
+#ifdef CONFIG_IMX_TRUSTY_OS
+	int rbindex;
+	rbindex = spl_fit_get_rbindex(ctx.fit);
+	if (rbindex < 0) {
+		printf("Error! Can't get rollback index!\n");
+		return -1;
+	} else
+		spl_image->rbindex = rbindex;
+#endif
+
 	if (IS_ENABLED(CONFIG_SPL_FPGA))
 		spl_fit_load_fpga(&ctx, info, sector);
 
@@ -828,8 +866,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
 
 	spl_image->flags |= SPL_FIT_FOUND;
 
-	if (IS_ENABLED(CONFIG_IMX_HAB))
-		board_spl_fit_post_load(ctx.fit);
+	board_spl_fit_post_load(ctx.fit, spl_image);
 
 	return 0;
 }
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 1c41d24ff45..cbbd166eb3f 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -59,7 +59,7 @@ static int mmc_load_legacy(struct spl_image_info *spl_image,
 	return 0;
 }
 
-static ulong h_spl_load_read(struct spl_load_info *load, ulong sector,
+ulong h_spl_load_read(struct spl_load_info *load, ulong sector,
 			     ulong count, void *buf)
 {
 	struct mmc *mmc = load->dev;
@@ -77,6 +77,16 @@ static __maybe_unused unsigned long spl_mmc_raw_uboot_offset(int part)
 	return 0;
 }
 
+#if defined(CONFIG_DUAL_BOOTLOADER)
+int mmc_load_image_raw_sector_dual_uboot(struct spl_image_info *spl_image,
+					 struct mmc *mmc);
+#endif
+
+int __weak mmc_image_load_late(struct spl_image_info *spl_image, struct mmc *mmc)
+{
+	return 0;
+}
+
 static __maybe_unused
 int mmc_load_image_raw_sector(struct spl_image_info *spl_image,
 			      struct spl_boot_device *bootdev,
@@ -130,7 +140,8 @@ end:
 		return -1;
 	}
 
-	return 0;
+	ret = mmc_image_load_late(spl_image, mmc);
+	return ret;
 }
 
 static int spl_mmc_get_device_index(u32 boot_device)
@@ -362,10 +373,18 @@ int default_spl_mmc_emmc_boot_partition(struct mmc *mmc)
 	 * 1 and 2 match up to boot0 / boot1 and 7 is user data
 	 * which is the first physical partition (0).
 	 */
+#ifdef CONFIG_DUAL_BOOTLOADER
+		/* Bootloader is stored in eMMC user partition for
+		 * dual bootloader.
+		 */
+		part = 0;
+#else
 	part = (mmc->part_config >> 3) & PART_ACCESS_MASK;
 	if (part == 7)
 		part = 0;
 #endif
+#endif
+
 	return part;
 }
 
@@ -428,7 +447,9 @@ int spl_mmc_load(struct spl_image_info *spl_image,
 				return err;
 		}
 
+#ifndef CONFIG_DUAL_BOOTLOADER
 		raw_sect = spl_mmc_get_uboot_raw_sector(mmc, raw_sect);
+#endif
 
 #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
 		err = mmc_load_image_raw_partition(spl_image, bootdev,
@@ -438,8 +459,12 @@ int spl_mmc_load(struct spl_image_info *spl_image,
 			return err;
 #endif
 #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#ifdef CONFIG_DUAL_BOOTLOADER
+		err = mmc_load_image_raw_sector_dual_uboot(spl_image, mmc);
+#else
 		err = mmc_load_image_raw_sector(spl_image, bootdev, mmc,
 				raw_sect + spl_mmc_raw_uboot_offset(part));
+#endif
 		if (!err)
 			return err;
 #endif
@@ -476,7 +501,11 @@ int spl_mmc_load_image(struct spl_image_info *spl_image,
 			    0,
 #endif
 #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
-			    CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
+			    CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
+#ifdef CONFIG_SECONDARY_BOOT_SECTOR_OFFSET
+			    + CONFIG_SECONDARY_BOOT_SECTOR_OFFSET
+#endif
+			    );
 #else
 			    0);
 #endif
diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c
index 3f7f7accc11..20931354037 100644
--- a/common/spl/spl_ram.c
+++ b/common/spl/spl_ram.c
@@ -21,12 +21,17 @@
 # define CONFIG_SPL_LOAD_FIT_ADDRESS	0
 #endif
 
+unsigned long __weak spl_ram_get_uboot_base(void)
+{
+	return CONFIG_SPL_LOAD_FIT_ADDRESS;
+}
+
 static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector,
 			       ulong count, void *buf)
 {
 	debug("%s: sector %lx, count %lx, buf %lx\n",
 	      __func__, sector, count, (ulong)buf);
-	memcpy(buf, (void *)(CONFIG_SPL_LOAD_FIT_ADDRESS + sector), count);
+	memcpy(buf, (void *)(sector), count);
 	return count;
 }
 
@@ -35,7 +40,7 @@ static int spl_ram_load_image(struct spl_image_info *spl_image,
 {
 	struct image_header *header;
 
-	header = (struct image_header *)CONFIG_SPL_LOAD_FIT_ADDRESS;
+	header = (struct image_header *)spl_ram_get_uboot_base();
 
 #if CONFIG_IS_ENABLED(DFU)
 	if (bootdev->boot_device == BOOT_DEVICE_DFU)
@@ -49,7 +54,15 @@ static int spl_ram_load_image(struct spl_image_info *spl_image,
 		debug("Found FIT\n");
 		load.bl_len = 1;
 		load.read = spl_ram_load_read;
-		spl_load_simple_fit(spl_image, &load, 0, header);
+		spl_load_simple_fit(spl_image, &load, (ulong)header, header);
+	} else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) {
+		struct spl_load_info load;
+
+		memset(&load, 0, sizeof(load));
+		load.bl_len = 1;
+		load.read = spl_ram_load_read;
+
+		spl_load_imx_container(spl_image, &load, (ulong)header);
 	} else {
 		ulong u_boot_pos = binman_sym(ulong, u_boot_any, image_pos);
 
diff --git a/common/spl/spl_sdp.c b/common/spl/spl_sdp.c
index 36c31aff099..4c5aa07d531 100644
--- a/common/spl/spl_sdp.c
+++ b/common/spl/spl_sdp.c
@@ -15,11 +15,14 @@ static int spl_sdp_load_image(struct spl_image_info *spl_image,
 			      struct spl_boot_device *bootdev)
 {
 	int ret;
-	const int controller_index = CONFIG_SPL_SDP_USB_DEV;
+	int index;
+	int controller_index = CONFIG_SPL_SDP_USB_DEV;
 
-	usb_gadget_initialize(controller_index);
+	index = board_usb_gadget_port_auto();
+	if (index >= 0)
+		controller_index = index;
 
-	board_usb_init(0, USB_INIT_DEVICE);
+	usb_gadget_initialize(controller_index);
 
 	g_dnl_clear_detach();
 	ret = g_dnl_register("usb_dnl_sdp");
diff --git a/common/stdio.c b/common/stdio.c
index 063c659bbc3..2cc22e801a9 100644
--- a/common/stdio.c
+++ b/common/stdio.c
@@ -18,6 +18,8 @@
 #include <stdio_dev.h>
 #include <serial.h>
 #include <splash.h>
+#include <video_link.h>
+
 #include <i2c.h>
 #include <asm/global_data.h>
 #include <dm/device-internal.h>
@@ -340,6 +342,9 @@ int stdio_add_devices(void)
 	i2c_init_all();
 #endif
 	if (IS_ENABLED(CONFIG_DM_VIDEO)) {
+#ifdef CONFIG_VIDEO_LINK
+		video_link_init();
+#endif
 		/*
 		 * If the console setting is not in environment variables then
 		 * console_init_r() will not be calling iomux_doenv() (which
diff --git a/common/usb_hub.c b/common/usb_hub.c
index ba11a188ca6..990993aa2fa 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -950,7 +950,7 @@ U_BOOT_DRIVER(usb_generic_hub) = {
 	.name	= "usb_hub",
 	.id	= UCLASS_USB_HUB,
 	.of_match = usb_hub_ids,
-	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
+	.flags	= DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_DEFAULT_PD_CTRL_OFF,
 };
 
 UCLASS_DRIVER(usb_hub) = {
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 01d61928a3d..1e5cf7d874f 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -42,6 +42,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xFFA00C21
 CONFIG_SYS_OR0_PRELIM=0xFFFC0796
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index dc56c791d1f..d8ebd3f989a 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -43,6 +43,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xE8001001
 CONFIG_SYS_OR0_PRELIM=0xF8000F85
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 78a24503a49..b6b0d516c5b 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -44,6 +44,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xE8001001
 CONFIG_SYS_OR0_PRELIM=0xF8000F85
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index f6bf4daf23b..64c44a125f7 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -39,6 +39,7 @@ CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
 CONFIG_SYS_BR0_PRELIM=0xE8001001
 CONFIG_SYS_OR0_PRELIM=0xF8000F85
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index ec5850017d6..790c8f7d7b5 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -40,6 +40,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index 58a3eaea72f..1f3a2b322a3 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -41,6 +41,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index c48976b3d07..a3f6d2dadbc 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -42,6 +42,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index fcc73610af8..435ea1924f0 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -37,6 +37,7 @@ CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index 25f7861791d..def492978ce 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -40,6 +40,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index c32c394530b..915eecbb9f1 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -41,6 +41,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index e3c41c316f2..2e0171acf38 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -36,6 +36,7 @@ CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index 279976c04d4..bf6ef1885cf 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -41,6 +41,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index 34ebc51922e..21d8a39b88a 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -41,6 +41,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index ea8b6733040..9b765e5c3fd 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -42,6 +42,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index e9bf7ff0144..53196434a8c 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -37,6 +37,7 @@ CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_BR0_PRELIM_BOOL=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index 20ded48a351..a5ddcd8cda3 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -63,6 +63,7 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index 8a82082968c..ab59d4e1734 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -62,6 +62,7 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 87d40831d9c..e5b71813db0 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -64,6 +64,7 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index de34ba7a68a..f0c07249d5c 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -47,6 +47,7 @@ CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index a755d9c7029..fb7f14cc89a 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -54,6 +54,7 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index efb46b3bf2f..65e25d06458 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -53,6 +53,7 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index 1568c797bf3..ecaec29612d 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -55,6 +55,7 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 3abd079dc68..27b44c4e9f2 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -38,6 +38,7 @@ CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_CLK_FREQ=66666666
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 1b6ef8aaa1f..4e888c9510a 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -58,6 +58,7 @@ CONFIG_ENV_IS_IN_NAND=y
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index 8ab1c5d6809..7900670c98f 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -57,6 +57,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 8fd024848ad..882e1599890 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -59,6 +59,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index f9dbc84f922..5b574946de6 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -39,6 +39,7 @@ CONFIG_ENV_ADDR=0xFFE20000
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index 424b3f2cdb8..1ecf12bc91a 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -42,6 +42,7 @@ CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 1c55d30b5e1..de6969fc14f 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -62,6 +62,7 @@ CONFIG_ENV_IS_IN_NAND=y
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_CLK_FREQ=133330000
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index ea9c479825c..fbd72313bb2 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -61,6 +61,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_CLK_FREQ=133330000
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 5e08b82406a..ae6b4443513 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -63,6 +63,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_CLK_FREQ=133330000
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 1c1fea60b58..e197995e852 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -46,6 +46,7 @@ CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_CLK_FREQ=133330000
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig
index ae924b18173..bec2d1529a5 100644
--- a/configs/T2080RDB_revD_NAND_defconfig
+++ b/configs/T2080RDB_revD_NAND_defconfig
@@ -63,6 +63,7 @@ CONFIG_ENV_IS_IN_NAND=y
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_CLK_FREQ=133330000
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig
index fef08931d0d..3bc08f7b9cb 100644
--- a/configs/T2080RDB_revD_SDCARD_defconfig
+++ b/configs/T2080RDB_revD_SDCARD_defconfig
@@ -62,6 +62,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_CLK_FREQ=133330000
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig
index 0b7e71567da..0dc2b2f77f4 100644
--- a/configs/T2080RDB_revD_SPIFLASH_defconfig
+++ b/configs/T2080RDB_revD_SPIFLASH_defconfig
@@ -64,6 +64,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_CLK_FREQ=133330000
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig
index c78b21dd245..7c196e62146 100644
--- a/configs/T2080RDB_revD_defconfig
+++ b/configs/T2080RDB_revD_defconfig
@@ -47,6 +47,7 @@ CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_CLK_FREQ=133330000
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index ea6a5284959..ec66247ec22 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -53,6 +53,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index e17e8b129ff..042039713a4 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -38,6 +38,7 @@ CONFIG_ENV_ADDR=0xEFF20000
 CONFIG_DM=y
 CONFIG_SYS_SATA_MAX_DEVICE=2
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig
index ae27857e6fa..294d580b911 100644
--- a/configs/imx6dl_mamoj_defconfig
+++ b/configs/imx6dl_mamoj_defconfig
@@ -58,6 +58,6 @@ CONFIG_USB=y
 # CONFIG_SPL_DM_USB is not set
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
 CONFIG_CI_UDC=y
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
index bd5853c2fd6..a29cc254d93 100644
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -107,7 +107,7 @@ CONFIG_USB=y
 # CONFIG_SPL_DM_USB is not set
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/imx8dx_17x17_val_defconfig b/configs/imx8dx_17x17_val_defconfig
new file mode 100644
index 00000000000..882905225ad
--- /dev/null
+++ b/configs/imx8dx_17x17_val_defconfig
@@ -0,0 +1,161 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dx-17x17-val"
+CONFIG_DEFAULT_FDT_FILE="imx8dx-17x17-val.dtb"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8X_17X17_VAL=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_val/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+# CONFIG_USB_CDNS3=y
+# CONFIG_USB_CDNS3_GADGET=y
+# CONFIG_USB_GADGET_DUALSPEED=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=0
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=0
+
+CONFIG_USB_PORT_AUTO=y
diff --git a/configs/imx8dx_mek_android_defconfig b/configs/imx8dx_mek_android_defconfig
new file mode 100644
index 00000000000..06e65a44807
--- /dev/null
+++ b/configs/imx8dx_mek_android_defconfig
@@ -0,0 +1,189 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dx-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8DX_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_SYS_I2C_IMX_VIRT_I2C=y
+CONFIG_I2C_MUX_IMX_VIRT=y
+CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
diff --git a/configs/imx8dx_mek_android_uuu_defconfig b/configs/imx8dx_mek_android_uuu_defconfig
new file mode 100644
index 00000000000..47a4ac5550d
--- /dev/null
+++ b/configs/imx8dx_mek_android_uuu_defconfig
@@ -0,0 +1,186 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dx-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8DX_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_SYS_I2C_IMX_VIRT_I2C=y
+CONFIG_I2C_MUX_IMX_VIRT=y
+CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_CMD_BOOTA=n
diff --git a/configs/imx8dx_mek_defconfig b/configs/imx8dx_mek_defconfig
new file mode 100644
index 00000000000..083b8197772
--- /dev/null
+++ b/configs/imx8dx_mek_defconfig
@@ -0,0 +1,182 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dx-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8DX_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_SYS_I2C_IMX_VIRT_I2C=y
+CONFIG_I2C_MUX_IMX_VIRT=y
+CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8dx_mek_fspi_defconfig b/configs/imx8dx_mek_fspi_defconfig
new file mode 100644
index 00000000000..df26f991e7f
--- /dev/null
+++ b/configs/imx8dx_mek_fspi_defconfig
@@ -0,0 +1,187 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dx-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8DX_MEK=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_SPI_FLASH_TINY=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x200000
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_SYS_I2C_IMX_VIRT_I2C=y
+CONFIG_I2C_MUX_IMX_VIRT=y
+CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8dxl_ddr3l_evk_defconfig b/configs/imx8dxl_ddr3l_evk_defconfig
new file mode 100644
index 00000000000..421d3e1181f
--- /dev/null
+++ b/configs/imx8dxl_ddr3l_evk_defconfig
@@ -0,0 +1,173 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dxl-ddr3l-evk"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8DXL_DDR3_EVK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8dxl_evk/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_MII=y
+
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_EHCI_HCD=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=0
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_DM_USB=y
+CONFIG_SPL_SDP_USB_DEV=0
+CONFIG_SDP_LOADADDR=0x80400000
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_CMD_RNG=y
+CONFIG_DM_RNG=y
+CONFIG_FSL_CAAM_RNG=y
diff --git a/configs/imx8dxl_ddr3l_evk_fspi_defconfig b/configs/imx8dxl_ddr3l_evk_fspi_defconfig
new file mode 100644
index 00000000000..9f4856954e3
--- /dev/null
+++ b/configs/imx8dxl_ddr3l_evk_fspi_defconfig
@@ -0,0 +1,180 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dxl-ddr3l-evk"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8DXL_DDR3_EVK=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_SPI_FLASH_TINY=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x200000
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8dxl_evk/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_MII=y
+
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_EHCI_HCD=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=0
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_DM_USB=y
+CONFIG_SPL_SDP_USB_DEV=0
+CONFIG_SDP_LOADADDR=0x80400000
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_CMD_RNG=y
+CONFIG_DM_RNG=y
+CONFIG_FSL_CAAM_RNG=y
diff --git a/configs/imx8dxl_ddr3l_evk_nand_defconfig b/configs/imx8dxl_ddr3l_evk_nand_defconfig
new file mode 100644
index 00000000000..7a92c318ce0
--- /dev/null
+++ b/configs/imx8dxl_ddr3l_evk_nand_defconfig
@@ -0,0 +1,184 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x7800000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dxl-ddr3l-evk"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8DXL_DDR3_EVK=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8dxl_evk/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read ${loadaddr} 0x9000000 0x2000000; nand read ${fdt_addr} 0xB000000 0x100000; booti ${loadaddr} - ${fdt_addr}"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_MII=y
+
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_EHCI_HCD=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_NAND_BOOT=y
+CONFIG_CMD_UBI=y
+
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
+CONFIG_MTDPARTS_SKIP_INVALID=y
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=0
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_DM_USB=y
+CONFIG_SPL_SDP_USB_DEV=0
+CONFIG_SDP_LOADADDR=0x80400000
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_CMD_RNG=y
+CONFIG_DM_RNG=y
+CONFIG_FSL_CAAM_RNG=y
diff --git a/configs/imx8dxl_evk_defconfig b/configs/imx8dxl_evk_defconfig
new file mode 100644
index 00000000000..4341d7f9193
--- /dev/null
+++ b/configs/imx8dxl_evk_defconfig
@@ -0,0 +1,179 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dxl-evk"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8DXL_EVK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8dxl_evk/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_MII=y
+
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_FSL_LPSPI=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_EHCI_HCD=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x01fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=0
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_DM_USB=y
+CONFIG_SPL_SDP_USB_DEV=0
+CONFIG_SDP_LOADADDR=0x80400000
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_CMD_RNG=y
+CONFIG_DM_RNG=y
+CONFIG_FSL_CAAM_RNG=y
diff --git a/configs/imx8dxl_evk_fspi_defconfig b/configs/imx8dxl_evk_fspi_defconfig
new file mode 100644
index 00000000000..8248dcd8392
--- /dev/null
+++ b/configs/imx8dxl_evk_fspi_defconfig
@@ -0,0 +1,183 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dxl-evk"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8DXL_EVK=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_SPI_FLASH_TINY=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x200000
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8dxl_evk/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_MII=y
+
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_EHCI_HCD=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=0
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_DM_USB=y
+CONFIG_SPL_SDP_USB_DEV=0
+CONFIG_SDP_LOADADDR=0x80400000
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_CMD_RNG=y
+CONFIG_DM_RNG=y
+CONFIG_FSL_CAAM_RNG=y
diff --git a/configs/imx8dxl_evk_lcd_defconfig b/configs/imx8dxl_evk_lcd_defconfig
new file mode 100644
index 00000000000..f2091fed798
--- /dev/null
+++ b/configs/imx8dxl_evk_lcd_defconfig
@@ -0,0 +1,183 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dxl-evk-lcdif"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8DXL_EVK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8dxl_evk/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_EHCI_HCD=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=0
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_DM_USB=y
+CONFIG_SPL_SDP_USB_DEV=0
+CONFIG_SDP_LOADADDR=0x80400000
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_IMX_SNVS_SEC_SC=y
+
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_RNG=y
+CONFIG_DM_RNG=y
+CONFIG_FSL_CAAM_RNG=y
diff --git a/configs/imx8dxl_phantom_mek_defconfig b/configs/imx8dxl_phantom_mek_defconfig
new file mode 100644
index 00000000000..87eb60cf593
--- /dev/null
+++ b/configs/imx8dxl_phantom_mek_defconfig
@@ -0,0 +1,171 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dxl-phantom-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8DXL_PHANTOM_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8dxl_phantom_mek/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_EHCI_HCD=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+# CONFIG_USB_CDNS3=y
+# CONFIG_USB_CDNS3_GADGET=y
+# CONFIG_USB_GADGET_DUALSPEED=y
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=0
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_DM_USB=y
+CONFIG_SPL_SDP_USB_DEV=0
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_IMX_SNVS_SEC_SC=y
diff --git a/configs/imx8dxl_phantom_mek_fspi_defconfig b/configs/imx8dxl_phantom_mek_fspi_defconfig
new file mode 100644
index 00000000000..25a666c8fd6
--- /dev/null
+++ b/configs/imx8dxl_phantom_mek_fspi_defconfig
@@ -0,0 +1,178 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dxl-phantom-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8DXL_PHANTOM_MEK=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_SPI_FLASH_TINY=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x200000
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8dxl_phantom_mek/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_EHCI_HCD=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+# CONFIG_USB_CDNS3=y
+# CONFIG_USB_CDNS3_GADGET=y
+# CONFIG_USB_GADGET_DUALSPEED=y
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=0
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_DM_USB=y
+CONFIG_SPL_SDP_USB_DEV=0
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_IMX_SNVS_SEC_SC=y
diff --git a/configs/imx8mm_ab2_defconfig b/configs/imx8mm_ab2_defconfig
new file mode 100644
index 00000000000..d0e5193ec6c
--- /dev/null
+++ b/configs/imx8mm_ab2_defconfig
@@ -0,0 +1,194 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_AB2=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-ab2"
+CONFIG_CSF_SIZE=0x2000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-ab2.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_SYS_MMC_IMG_LOAD_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+CONFIG_SPL_RSA=y
+CONFIG_SHA384=y
+CONFIG_EFI_VAR_BUF_SIZE=139264
+CONFIG_EFI_IGNORE_OSINDICATIONS=y
+CONFIG_EFI_CAPSULE_AUTHENTICATE=y
+CONFIG_OPTEE=y
+CONFIG_CMD_OPTEE_RPMB=y
+CONFIG_EFI_MM_COMM_TEE=y
+CONFIG_TEE=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_HAVE_CAPSULE_UPDATE=y
+CONFIG_FIT_SIGNATURE=y
diff --git a/configs/imx8mm_ddr3l_val_defconfig b/configs/imx8mm_ddr3l_val_defconfig
new file mode 100644
index 00000000000..9b84bd1bec8
--- /dev/null
+++ b/configs/imx8mm_ddr3l_val_defconfig
@@ -0,0 +1,147 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_DDR3L_VAL=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-ddr3l-val"
+CONFIG_CSF_SIZE=0x2000
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-ddr3l-val.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_MXC_SPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=8000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_CMD_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
diff --git a/configs/imx8mm_ddr4_ab2_defconfig b/configs/imx8mm_ddr4_ab2_defconfig
new file mode 100644
index 00000000000..5d4357c8cd5
--- /dev/null
+++ b/configs/imx8mm_ddr4_ab2_defconfig
@@ -0,0 +1,163 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_DDR4_AB2=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-ddr4-ab2"
+CONFIG_CSF_SIZE=0x2000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-ddr4-ab2.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_SYS_MMC_IMG_LOAD_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_CMD_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
diff --git a/configs/imx8mm_ddr4_evk_android_defconfig b/configs/imx8mm_ddr4_evk_android_defconfig
new file mode 100644
index 00000000000..80e0d937759
--- /dev/null
+++ b/configs/imx8mm_ddr4_evk_android_defconfig
@@ -0,0 +1,172 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_DDR4_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-ddr4-evk"
+CONFIG_CSF_SIZE=0x2000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-ddr4-evk.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x44800000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_CMD_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
diff --git a/configs/imx8mm_ddr4_evk_android_uuu_defconfig b/configs/imx8mm_ddr4_evk_android_uuu_defconfig
new file mode 100644
index 00000000000..d6c5cb11d11
--- /dev/null
+++ b/configs/imx8mm_ddr4_evk_android_uuu_defconfig
@@ -0,0 +1,167 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_DDR4_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-ddr4-evk"
+CONFIG_CSF_SIZE=0x2000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-ddr4-evk.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x44800000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_CMD_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_CMD_BOOTA=n
diff --git a/configs/imx8mm_ddr4_evk_defconfig b/configs/imx8mm_ddr4_evk_defconfig
new file mode 100644
index 00000000000..a70a9519926
--- /dev/null
+++ b/configs/imx8mm_ddr4_evk_defconfig
@@ -0,0 +1,162 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_DDR4_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-ddr4-evk"
+CONFIG_CSF_SIZE=0x2000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-ddr4-evk.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_CMD_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
diff --git a/configs/imx8mm_ddr4_evk_nand_defconfig b/configs/imx8mm_ddr4_evk_nand_defconfig
new file mode 100644
index 00000000000..f4e93d0ab07
--- /dev/null
+++ b/configs/imx8mm_ddr4_evk_nand_defconfig
@@ -0,0 +1,167 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x3C00000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_DDR4_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-ddr4-evk"
+CONFIG_CSF_SIZE=0x2000
+CONFIG_BOOTCOMMAND="run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-ddr4-evk.dtb"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_CMD_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BOOT=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
+CONFIG_MTDPARTS_SKIP_INVALID=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
diff --git a/configs/imx8mm_ddr4_val_defconfig b/configs/imx8mm_ddr4_val_defconfig
new file mode 100644
index 00000000000..6a369e750a7
--- /dev/null
+++ b/configs/imx8mm_ddr4_val_defconfig
@@ -0,0 +1,141 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_DDR4_VAL=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-ddr4-val"
+CONFIG_CSF_SIZE=0x2000
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-ddr4-val.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
diff --git a/configs/imx8mm_evk_1g_ddr_android_defconfig b/configs/imx8mm_evk_1g_ddr_android_defconfig
new file mode 100644
index 00000000000..5133f38cd34
--- /dev/null
+++ b/configs/imx8mm_evk_1g_ddr_android_defconfig
@@ -0,0 +1,206 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
+CONFIG_CSF_SIZE=0x2000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x44800000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_LZ4=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_IMX8M_1G_MEMORY=y
diff --git a/configs/imx8mm_evk_4g_android_defconfig b/configs/imx8mm_evk_4g_android_defconfig
new file mode 100644
index 00000000000..7f2882c5a66
--- /dev/null
+++ b/configs/imx8mm_evk_4g_android_defconfig
@@ -0,0 +1,206 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
+CONFIG_CSF_SIZE=0x2000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x44800000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_LZ4=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_IMX8M_4G_LPDDR4=y
diff --git a/configs/imx8mm_evk_4g_android_trusty_defconfig b/configs/imx8mm_evk_4g_android_trusty_defconfig
new file mode 100644
index 00000000000..bf48059cc7d
--- /dev/null
+++ b/configs/imx8mm_evk_4g_android_trusty_defconfig
@@ -0,0 +1,212 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
+CONFIG_CSF_SIZE=0x2000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x44800000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_LZ4=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_IMX8M_4G_LPDDR4=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="evk_8mm"
+CONFIG_ATTESTATION_ID_PRODUCT="evk_8mm"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="EVK_8MM"
diff --git a/configs/imx8mm_evk_4g_android_uuu_defconfig b/configs/imx8mm_evk_4g_android_uuu_defconfig
new file mode 100644
index 00000000000..bbe331da0a7
--- /dev/null
+++ b/configs/imx8mm_evk_4g_android_uuu_defconfig
@@ -0,0 +1,201 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
+CONFIG_CSF_SIZE=0x2000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x44800000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_CMD_BOOTA=n
+CONFIG_IMX8M_4G_LPDDR4=y
diff --git a/configs/imx8mm_evk_android_defconfig b/configs/imx8mm_evk_android_defconfig
new file mode 100644
index 00000000000..d7ffc14bec5
--- /dev/null
+++ b/configs/imx8mm_evk_android_defconfig
@@ -0,0 +1,205 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
+CONFIG_CSF_SIZE=0x2000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x44800000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_LZ4=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
diff --git a/configs/imx8mm_evk_android_dual_defconfig b/configs/imx8mm_evk_android_dual_defconfig
new file mode 100644
index 00000000000..adad43db543
--- /dev/null
+++ b/configs/imx8mm_evk_android_dual_defconfig
@@ -0,0 +1,206 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
+CONFIG_CSF_SIZE=0x2000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x44800000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_LZ4=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/imx8mm_evk_android_trusty_defconfig b/configs/imx8mm_evk_android_trusty_defconfig
new file mode 100644
index 00000000000..e5023f7521b
--- /dev/null
+++ b/configs/imx8mm_evk_android_trusty_defconfig
@@ -0,0 +1,211 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
+CONFIG_CSF_SIZE=0x2000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x44800000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_LZ4=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="evk_8mm"
+CONFIG_ATTESTATION_ID_PRODUCT="evk_8mm"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="EVK_8MM"
diff --git a/configs/imx8mm_evk_android_trusty_dual_defconfig b/configs/imx8mm_evk_android_trusty_dual_defconfig
new file mode 100644
index 00000000000..a609d53ff35
--- /dev/null
+++ b/configs/imx8mm_evk_android_trusty_dual_defconfig
@@ -0,0 +1,212 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
+CONFIG_CSF_SIZE=0x2000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x44800000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_LZ4=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="evk_8mm"
+CONFIG_ATTESTATION_ID_PRODUCT="evk_8mm"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="EVK_8MM"
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/imx8mm_evk_android_trusty_secure_unlock_defconfig b/configs/imx8mm_evk_android_trusty_secure_unlock_defconfig
new file mode 100644
index 00000000000..50c5a068724
--- /dev/null
+++ b/configs/imx8mm_evk_android_trusty_secure_unlock_defconfig
@@ -0,0 +1,213 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
+CONFIG_CSF_SIZE=0x2000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x44800000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_LZ4=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="evk_8mm"
+CONFIG_ATTESTATION_ID_PRODUCT="evk_8mm"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="EVK_8MM"
+CONFIG_SECURE_UNLOCK=y
+CONFIG_IMX_HAB=y
diff --git a/configs/imx8mm_evk_android_uuu_defconfig b/configs/imx8mm_evk_android_uuu_defconfig
new file mode 100644
index 00000000000..7a6c245d179
--- /dev/null
+++ b/configs/imx8mm_evk_android_uuu_defconfig
@@ -0,0 +1,200 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
+CONFIG_CSF_SIZE=0x2000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x44800000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_CMD_BOOTA=n
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index 01395fc7eb7..ca1c4a268a0 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -6,24 +6,33 @@ CONFIG_SYS_MALLOC_F_LEN=0x10000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
 CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MM_EVK=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
+CONFIG_CSF_SIZE=0x2000
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
 # CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
@@ -31,38 +40,92 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
 CONFIG_SPL_I2C=y
 CONFIG_SPL_POWER=y
 CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_SYS_PROMPT="u-boot=> "
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 # CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_NVEDIT_EFI=y
 CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
 CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_HASH=y
 CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_SPL_DM=y
-CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_CLK_COMPOSITE_CCF=y
-CONFIG_SPL_CLK_IMX8MM=y
 CONFIG_CLK_IMX8MM=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
 CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
 CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_ES_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
 CONFIG_PHYLIB=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
@@ -70,17 +133,76 @@ CONFIG_PHY_GIGE=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
-CONFIG_DM_PMIC=y
-CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_SPL_POWER_LEGACY=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
-CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
-CONFIG_IMX_WATCHDOG=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+CONFIG_SPL_RSA=y
+CONFIG_SHA384=y
+CONFIG_EFI_VAR_BUF_SIZE=139264
+CONFIG_EFI_IGNORE_OSINDICATIONS=y
+CONFIG_EFI_CAPSULE_AUTHENTICATE=y
+CONFIG_OPTEE=y
+CONFIG_CMD_OPTEE_RPMB=y
+CONFIG_EFI_MM_COMM_TEE=y
+CONFIG_TEE=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_HAVE_CAPSULE_UPDATE=y
+CONFIG_FIT_SIGNATURE=y
diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig
new file mode 100644
index 00000000000..cef425149f8
--- /dev/null
+++ b/configs/imx8mm_evk_fspi_defconfig
@@ -0,0 +1,171 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E2000
+CONFIG_TARGET_IMX8MM_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
+CONFIG_CSF_SIZE=0x2000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_IMX_CONFIG="board/freescale/imx8mm_evk/imximage-8mm-fspi.cfg"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SDP_LOADADDR=0x40400000
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
diff --git a/configs/imx8mn_ab2_defconfig b/configs/imx8mn_ab2_defconfig
new file mode 100644
index 00000000000..3bf4cf2a36e
--- /dev/null
+++ b/configs/imx8mn_ab2_defconfig
@@ -0,0 +1,159 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MN_AB2=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ab2"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8mn-ab2.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
+CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_SYS_MMC_IMG_LOAD_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig
index 5e92cb597b6..f2604ca7586 100644
--- a/configs/imx8mn_beacon_2g_defconfig
+++ b/configs/imx8mn_beacon_2g_defconfig
@@ -126,8 +126,8 @@ CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
 CONFIG_CI_UDC=y
 CONFIG_SDP_LOADADDR=0x0
 CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
index a69977d0335..d22a721964e 100644
--- a/configs/imx8mn_beacon_defconfig
+++ b/configs/imx8mn_beacon_defconfig
@@ -133,8 +133,8 @@ CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
 CONFIG_CI_UDC=y
 CONFIG_SDP_LOADADDR=0x0
 CONFIG_IMX_WATCHDOG=y
diff --git a/configs/imx8mn_ddr3l_ab2_defconfig b/configs/imx8mn_ddr3l_ab2_defconfig
new file mode 100644
index 00000000000..db6236f2428
--- /dev/null
+++ b/configs/imx8mn_ddr3l_ab2_defconfig
@@ -0,0 +1,141 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x70000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MN_DDR3L_AB2=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr3l-ab2"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr3l-ab2.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_SYS_MMC_IMG_LOAD_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
diff --git a/configs/imx8mn_ddr3l_evk_defconfig b/configs/imx8mn_ddr3l_evk_defconfig
new file mode 100644
index 00000000000..fef1be50275
--- /dev/null
+++ b/configs/imx8mn_ddr3l_evk_defconfig
@@ -0,0 +1,138 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x70000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MN_DDR3_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr3l-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr3l-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/imx8mn_ddr4_ab2_defconfig b/configs/imx8mn_ddr4_ab2_defconfig
new file mode 100644
index 00000000000..dd4bd5fcda3
--- /dev/null
+++ b/configs/imx8mn_ddr4_ab2_defconfig
@@ -0,0 +1,154 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_TARGET_IMX8MN_DDR4_AB2=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-ab2"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-ab2.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_SYS_MMC_IMG_LOAD_PART=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
diff --git a/configs/imx8mn_ddr4_evk_android_defconfig b/configs/imx8mn_ddr4_evk_android_defconfig
new file mode 100644
index 00000000000..2dd5016d027
--- /dev/null
+++ b/configs/imx8mn_ddr4_evk_android_defconfig
@@ -0,0 +1,173 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_TARGET_IMX8MN_DDR4_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
diff --git a/configs/imx8mn_ddr4_evk_android_uuu_defconfig b/configs/imx8mn_ddr4_evk_android_uuu_defconfig
new file mode 100644
index 00000000000..3e2137e5c32
--- /dev/null
+++ b/configs/imx8mn_ddr4_evk_android_uuu_defconfig
@@ -0,0 +1,168 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_TARGET_IMX8MN_DDR4_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_CMD_BOOTA=n
diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig
index 27bf5ec05a2..097ff4f5f10 100644
--- a/configs/imx8mn_ddr4_evk_defconfig
+++ b/configs/imx8mn_ddr4_evk_defconfig
@@ -6,50 +6,74 @@ CONFIG_SYS_MALLOC_F_LEN=0x10000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-evk"
 CONFIG_SPL_TEXT_BASE=0x912000
 CONFIG_TARGET_IMX8MN_DDR4_EVK=y
-CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-evk"
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
 # CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
 CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
 CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="u-boot=> "
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 CONFIG_CMD_ERASEENV=y
 # CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
 CONFIG_CMD_CLK=y
 CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_IS_NOWHERE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
@@ -57,30 +81,83 @@ CONFIG_SPL_DM=y
 CONFIG_SPL_CLK_IMX8MN=y
 CONFIG_CLK_IMX8MN=y
 CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
 CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_EFI_PARTITION=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_ES_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
 CONFIG_PHYLIB=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
-CONFIG_DM_ETH_PHY=y
 CONFIG_PHY_GIGE=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_BD71837=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_MXC_UART=y
 CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
-CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
-CONFIG_IMX_WATCHDOG=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
diff --git a/configs/imx8mn_ddr4_evk_ld_defconfig b/configs/imx8mn_ddr4_evk_ld_defconfig
new file mode 100644
index 00000000000..0db9422123f
--- /dev/null
+++ b/configs/imx8mn_ddr4_evk_ld_defconfig
@@ -0,0 +1,167 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_TARGET_IMX8MN_DDR4_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_MXC_GPIO=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+CONFIG_CI_UDC=y
+CONFIG_USB_EHCI_HCD=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_IMX8MN_LOW_DRIVE_MODE=y
diff --git a/configs/imx8mn_evk_android_defconfig b/configs/imx8mn_evk_android_defconfig
new file mode 100644
index 00000000000..3094542a352
--- /dev/null
+++ b/configs/imx8mn_evk_android_defconfig
@@ -0,0 +1,180 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MN_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
+CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
diff --git a/configs/imx8mn_evk_android_dual_defconfig b/configs/imx8mn_evk_android_dual_defconfig
new file mode 100644
index 00000000000..57b5688fa7c
--- /dev/null
+++ b/configs/imx8mn_evk_android_dual_defconfig
@@ -0,0 +1,181 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MN_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
+CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/imx8mn_evk_android_trusty_defconfig b/configs/imx8mn_evk_android_trusty_defconfig
new file mode 100644
index 00000000000..c49bb91d038
--- /dev/null
+++ b/configs/imx8mn_evk_android_trusty_defconfig
@@ -0,0 +1,187 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MN_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
+CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="evk_8mn"
+CONFIG_ATTESTATION_ID_PRODUCT="evk_8mn"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="EVK_8MN"
diff --git a/configs/imx8mn_evk_android_trusty_dual_defconfig b/configs/imx8mn_evk_android_trusty_dual_defconfig
new file mode 100644
index 00000000000..4486041a115
--- /dev/null
+++ b/configs/imx8mn_evk_android_trusty_dual_defconfig
@@ -0,0 +1,188 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MN_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
+CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="evk_8mn"
+CONFIG_ATTESTATION_ID_PRODUCT="evk_8mn"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="EVK_8MN"
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/imx8mn_evk_android_trusty_secure_unlock_defconfig b/configs/imx8mn_evk_android_trusty_secure_unlock_defconfig
new file mode 100644
index 00000000000..f9424aada20
--- /dev/null
+++ b/configs/imx8mn_evk_android_trusty_secure_unlock_defconfig
@@ -0,0 +1,189 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MN_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
+CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="evk_8mn"
+CONFIG_ATTESTATION_ID_PRODUCT="evk_8mn"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="EVK_8MN"
+CONFIG_SECURE_UNLOCK=y
+CONFIG_IMX_HAB=y
diff --git a/configs/imx8mn_evk_android_uuu_defconfig b/configs/imx8mn_evk_android_uuu_defconfig
new file mode 100644
index 00000000000..a718ea529dd
--- /dev/null
+++ b/configs/imx8mn_evk_android_uuu_defconfig
@@ -0,0 +1,174 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MN_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
+CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_CMD_BOOTA=n
diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig
index 807d126b21e..20c2ff2a529 100644
--- a/configs/imx8mn_evk_defconfig
+++ b/configs/imx8mn_evk_defconfig
@@ -1,6 +1,4 @@
 CONFIG_ARM=y
-CONFIG_SPL_SYS_ICACHE_OFF=y
-CONFIG_SPL_SYS_DCACHE_OFF=y
 CONFIG_ARCH_IMX8M=y
 CONFIG_SYS_TEXT_BASE=0x40200000
 CONFIG_SYS_MALLOC_LEN=0x2000000
@@ -8,26 +6,35 @@ CONFIG_SYS_MALLOC_F_LEN=0x10000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x1000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk"
 CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_USB_TCPC=y
 CONFIG_TARGET_IMX8MN_EVK=y
-CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk"
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_SYS_LOAD_ADDR=0x40400000
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
 # CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
 CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb"
 CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
@@ -41,40 +48,76 @@ CONFIG_SPL_I2C=y
 CONFIG_SPL_POWER=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
 CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
 # CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPL_CLK_IMX8MN=y
 CONFIG_CLK_IMX8MN=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
 CONFIG_MXC_GPIO=y
 CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_IO_VOLTAGE=y
-CONFIG_SPL_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
-CONFIG_SPL_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_ES_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_SPL_MMC_HS400_SUPPORT=y
 CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
@@ -84,10 +127,56 @@ CONFIG_DM_REGULATOR=y
 CONFIG_SPL_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
 CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
 CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
-CONFIG_SYSRESET_WATCHDOG=y
 CONFIG_DM_THERMAL=y
-CONFIG_IMX_WATCHDOG=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+CONFIG_SPL_RSA=y
+CONFIG_SHA384=y
+CONFIG_EFI_VAR_BUF_SIZE=139264
+CONFIG_EFI_IGNORE_OSINDICATIONS=y
+CONFIG_EFI_CAPSULE_AUTHENTICATE=y
+CONFIG_OPTEE=y
+CONFIG_CMD_OPTEE_RPMB=y
+CONFIG_EFI_MM_COMM_TEE=y
+CONFIG_TEE=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_HAVE_CAPSULE_UPDATE=y
+CONFIG_FIT_SIGNATURE=y
diff --git a/configs/imx8mn_evk_ld_defconfig b/configs/imx8mn_evk_ld_defconfig
new file mode 100644
index 00000000000..b2d30247aba
--- /dev/null
+++ b/configs/imx8mn_evk_ld_defconfig
@@ -0,0 +1,158 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x912000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MN_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MN=y
+CONFIG_CLK_IMX8MN=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_DISPMIX=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_IMX8MN_LOW_DRIVE_MODE=y
diff --git a/configs/imx8mp_ddr4_evk_defconfig b/configs/imx8mp_ddr4_evk_defconfig
new file mode 100644
index 00000000000..028a5b82d33
--- /dev/null
+++ b/configs/imx8mp_ddr4_evk_defconfig
@@ -0,0 +1,177 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0xC0000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_TARGET_IMX8MP_DDR4_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-ddr4-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-ddr4-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_OF_BOARD_SETUP=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_LCDIFV3=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_CMD_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
+CONFIG_MTDPARTS_SKIP_INVALID=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
diff --git a/configs/imx8mp_ddr4_evk_inline_ecc_defconfig b/configs/imx8mp_ddr4_evk_inline_ecc_defconfig
new file mode 100644
index 00000000000..920fa8ee06e
--- /dev/null
+++ b/configs/imx8mp_ddr4_evk_inline_ecc_defconfig
@@ -0,0 +1,179 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0xC0000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_TARGET_IMX8MP_DDR4_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-ddr4-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-ddr4-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_OF_BOARD_SETUP=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_LCDIFV3=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_CMD_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
+CONFIG_MTDPARTS_SKIP_INVALID=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+
+CONFIG_IMX8M_DRAM_INLINE_ECC=y
diff --git a/configs/imx8mp_ddr4_evk_nand_defconfig b/configs/imx8mp_ddr4_evk_nand_defconfig
new file mode 100644
index 00000000000..8aaf3fad389
--- /dev/null
+++ b/configs/imx8mp_ddr4_evk_nand_defconfig
@@ -0,0 +1,176 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x3C00000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0xC0000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_TARGET_IMX8MP_DDR4_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-ddr4-evk"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-ddr4-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_OF_BOARD_SETUP=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_LCDIFV3=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_CMD_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
+CONFIG_MTDPARTS_SKIP_INVALID=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_NAND_BOOT=y
diff --git a/configs/imx8mp_evk_android_defconfig b/configs/imx8mp_evk_android_defconfig
new file mode 100644
index 00000000000..aa8bd1f7c06
--- /dev/null
+++ b/configs/imx8mp_evk_android_defconfig
@@ -0,0 +1,187 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0xC0000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MP_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_LED=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_VIDEO_IMX_LCDIFV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
diff --git a/configs/imx8mp_evk_android_dual_defconfig b/configs/imx8mp_evk_android_dual_defconfig
new file mode 100644
index 00000000000..63e84078a77
--- /dev/null
+++ b/configs/imx8mp_evk_android_dual_defconfig
@@ -0,0 +1,188 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0xC0000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MP_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_LED=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_VIDEO_IMX_LCDIFV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/imx8mp_evk_android_powersave_defconfig b/configs/imx8mp_evk_android_powersave_defconfig
new file mode 100644
index 00000000000..6bd4b16562a
--- /dev/null
+++ b/configs/imx8mp_evk_android_powersave_defconfig
@@ -0,0 +1,189 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0xC0000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MP_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_LED=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_VIDEO_IMX_LCDIFV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_IMX8M_VDD_SOC_850MV=y
+CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS=y
diff --git a/configs/imx8mp_evk_android_trusty_defconfig b/configs/imx8mp_evk_android_trusty_defconfig
new file mode 100644
index 00000000000..9895325e27d
--- /dev/null
+++ b/configs/imx8mp_evk_android_trusty_defconfig
@@ -0,0 +1,193 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0xC0000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MP_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_LED=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_VIDEO_IMX_LCDIFV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="evk_8mp"
+CONFIG_ATTESTATION_ID_PRODUCT="evk_8mp"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="EVK_8MP"
diff --git a/configs/imx8mp_evk_android_trusty_dual_defconfig b/configs/imx8mp_evk_android_trusty_dual_defconfig
new file mode 100644
index 00000000000..a40d2de27d9
--- /dev/null
+++ b/configs/imx8mp_evk_android_trusty_dual_defconfig
@@ -0,0 +1,195 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0xC0000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MP_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_LED=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_VIDEO_IMX_LCDIFV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_DUAL_BOOTLOADER=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="evk_8mp"
+CONFIG_ATTESTATION_ID_PRODUCT="evk_8mp"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="EVK_8MP"
diff --git a/configs/imx8mp_evk_android_trusty_powersave_dual_defconfig b/configs/imx8mp_evk_android_trusty_powersave_dual_defconfig
new file mode 100644
index 00000000000..ac6a1998fd8
--- /dev/null
+++ b/configs/imx8mp_evk_android_trusty_powersave_dual_defconfig
@@ -0,0 +1,197 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0xC0000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MP_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_LED=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_VIDEO_IMX_LCDIFV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="evk_8mp"
+CONFIG_ATTESTATION_ID_PRODUCT="evk_8mp"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="EVK_8MP"
+CONFIG_IMX8M_VDD_SOC_850MV=y
+CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS=y
+CONFIG_DUAL_BOOTLOADER=y
+CONFIG_SPL_ENV_SUPPORT=y
diff --git a/configs/imx8mp_evk_android_trusty_secure_unlock_defconfig b/configs/imx8mp_evk_android_trusty_secure_unlock_defconfig
new file mode 100644
index 00000000000..b1f62640ed3
--- /dev/null
+++ b/configs/imx8mp_evk_android_trusty_secure_unlock_defconfig
@@ -0,0 +1,195 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0xC0000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MP_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_LED=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_VIDEO_IMX_LCDIFV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x320
+CONFIG_AVB_WARNING_LOGO_ROWS=0xc0
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="evk_8mp"
+CONFIG_ATTESTATION_ID_PRODUCT="evk_8mp"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="EVK_8MP"
+CONFIG_SECURE_UNLOCK=y
+CONFIG_IMX_HAB=y
diff --git a/configs/imx8mp_evk_android_uuu_defconfig b/configs/imx8mp_evk_android_uuu_defconfig
new file mode 100644
index 00000000000..e5cf363a0cd
--- /dev/null
+++ b/configs/imx8mp_evk_android_uuu_defconfig
@@ -0,0 +1,181 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0xC0000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MP_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_LED=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_VIDEO_IMX_LCDIFV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_CMD_BOOTA=n
diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index 0ff549f0beb..393e9b8aba7 100644
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -6,33 +6,39 @@ CONFIG_SYS_MALLOC_F_LEN=0x10000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x1000
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0xC0000000
+CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk"
 CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_USB_TCPC=y
 CONFIG_TARGET_IMX8MP_EVK=y
-CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk"
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
-# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
@@ -40,44 +46,83 @@ CONFIG_SPL_I2C=y
 CONFIG_SPL_POWER=y
 CONFIG_SPL_WATCHDOG=y
 CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
 # CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_LED=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
 CONFIG_CLK_IMX8MP=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
 CONFIG_MXC_GPIO=y
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
-# CONFIG_SPL_DM_I2C is not set
-CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS400_ES_SUPPORT=y
 CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHY_REALTEK=y
 CONFIG_DM_ETH=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_PHY_GIGE=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
 CONFIG_DWC_ETH_QOS=y
 CONFIG_DWC_ETH_QOS_IMX=y
 CONFIG_FEC_MXC=y
@@ -85,14 +130,60 @@ CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
-CONFIG_SPL_POWER_LEGACY=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
 CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
 CONFIG_SYSRESET=y
-CONFIG_SPL_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_IMX_WATCHDOG=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_VIDEO_IMX_LCDIFV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+CONFIG_SPL_RSA=y
+CONFIG_SHA384=y
+CONFIG_EFI_VAR_BUF_SIZE=139264
+CONFIG_EFI_IGNORE_OSINDICATIONS=y
+CONFIG_EFI_CAPSULE_AUTHENTICATE=y
+CONFIG_OPTEE=y
+CONFIG_CMD_OPTEE_RPMB=y
+CONFIG_EFI_MM_COMM_TEE=y
+CONFIG_TEE=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_HAVE_CAPSULE_UPDATE=y
+CONFIG_FIT_SIGNATURE=y
diff --git a/configs/imx8mp_evk_inline_ecc_defconfig b/configs/imx8mp_evk_inline_ecc_defconfig
new file mode 100644
index 00000000000..b8a82849ab0
--- /dev/null
+++ b/configs/imx8mp_evk_inline_ecc_defconfig
@@ -0,0 +1,177 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0xC0000000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_TARGET_IMX8MP_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_TCPC=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_USB=y
+
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_IMX8M_DRAM_INLINE_ECC=y
+
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_LCDIFV3=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
diff --git a/configs/imx8mp_evk_ndm_defconfig b/configs/imx8mp_evk_ndm_defconfig
new file mode 100644
index 00000000000..ae66220d747
--- /dev/null
+++ b/configs/imx8mp_evk_ndm_defconfig
@@ -0,0 +1,180 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0xC0000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x920000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MP_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_LED=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MP=y
+CONFIG_CLK_IMX8MP=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_IMX_SEC_DSI=y
+CONFIG_VIDEO_IMX_LCDIFV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_IMX8M_VDD_SOC_850MV=y
+CONFIG_IMX8M_LPDDR4_FREQ0_3200MTS=y
diff --git a/configs/imx8mq_ddr3l_val_defconfig b/configs/imx8mq_ddr3l_val_defconfig
new file mode 100644
index 00000000000..d655205f7f1
--- /dev/null
+++ b/configs/imx8mq_ddr3l_val_defconfig
@@ -0,0 +1,142 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0xA0000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MQ_DDR3L_VAL=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_DEFAULT_FDT_FILE="imx8mq-ddr3l-val.dtb"
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_CSF_SIZE=0x2000
+CONFIG_IMX_BOOTAUX=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-ddr3l-val"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RESET=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_FSL_QSPI=y
+CONFIG_CMD_SF=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=1
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/imx8mq_ddr4_val_defconfig b/configs/imx8mq_ddr4_val_defconfig
new file mode 100644
index 00000000000..8daa255b14d
--- /dev/null
+++ b/configs/imx8mq_ddr4_val_defconfig
@@ -0,0 +1,143 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0xA0000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MQ_DDR4_VAL=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_DEFAULT_FDT_FILE="imx8mq-ddr4-val.dtb"
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_CSF_SIZE=0x2000
+CONFIG_IMX_BOOTAUX=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-ddr4-val"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RESET=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+
+CONFIG_CMD_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
diff --git a/configs/imx8mq_ddr4_val_nand_defconfig b/configs/imx8mq_ddr4_val_nand_defconfig
new file mode 100644
index 00000000000..8aea6570475
--- /dev/null
+++ b/configs/imx8mq_ddr4_val_nand_defconfig
@@ -0,0 +1,143 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x3C00000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0xA0000000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MQ_DDR4_VAL=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_SERIAL=y
+CONFIG_DEFAULT_FDT_FILE="imx8mq-ddr4-val.dtb"
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_CSF_SIZE=0x2000
+CONFIG_IMX_BOOTAUX=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-ddr4-val"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RESET=y
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8M=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+
+CONFIG_CMD_NAND=y
+CONFIG_NAND_BOOT=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
diff --git a/configs/imx8mq_evk_android_defconfig b/configs/imx8mq_evk_android_defconfig
new file mode 100644
index 00000000000..b74492e9f94
--- /dev/null
+++ b/configs/imx8mq_evk_android_defconfig
@@ -0,0 +1,169 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0xA0000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MQ_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x44800000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IMX8M_DCSS=y
+CONFIG_VIDEO_IMX8M_HDMI=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x1E0
+CONFIG_AVB_WARNING_LOGO_ROWS=0x60
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
diff --git a/configs/imx8mq_evk_android_dual_defconfig b/configs/imx8mq_evk_android_dual_defconfig
new file mode 100644
index 00000000000..4c428fc569d
--- /dev/null
+++ b/configs/imx8mq_evk_android_dual_defconfig
@@ -0,0 +1,170 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0xA0000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MQ_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x44800000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IMX8M_DCSS=y
+CONFIG_VIDEO_IMX8M_HDMI=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x1E0
+CONFIG_AVB_WARNING_LOGO_ROWS=0x60
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/imx8mq_evk_android_trusty_defconfig b/configs/imx8mq_evk_android_trusty_defconfig
new file mode 100644
index 00000000000..075e9e887de
--- /dev/null
+++ b/configs/imx8mq_evk_android_trusty_defconfig
@@ -0,0 +1,175 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0xA0000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MQ_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x44800000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IMX8M_DCSS=y
+CONFIG_VIDEO_IMX8M_HDMI=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x1E0
+CONFIG_AVB_WARNING_LOGO_ROWS=0x60
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="evk_8mq"
+CONFIG_ATTESTATION_ID_PRODUCT="evk_8mq"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="EVK_8MQ"
diff --git a/configs/imx8mq_evk_android_trusty_dual_defconfig b/configs/imx8mq_evk_android_trusty_dual_defconfig
new file mode 100644
index 00000000000..4763648ba77
--- /dev/null
+++ b/configs/imx8mq_evk_android_trusty_dual_defconfig
@@ -0,0 +1,174 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0xA0000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MQ_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x44800000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IMX8M_DCSS=y
+CONFIG_VIDEO_IMX8M_HDMI=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x1E0
+CONFIG_AVB_WARNING_LOGO_ROWS=0x60
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="evk_8mq"
+CONFIG_ATTESTATION_ID_PRODUCT="evk_8mq"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="EVK_8MQ"
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/imx8mq_evk_android_trusty_secure_unlock_defconfig b/configs/imx8mq_evk_android_trusty_secure_unlock_defconfig
new file mode 100644
index 00000000000..5a00d4e7c95
--- /dev/null
+++ b/configs/imx8mq_evk_android_trusty_secure_unlock_defconfig
@@ -0,0 +1,177 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0xA0000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MQ_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_USB_GADGET=n
+CONFIG_SPL_USB_SDP_SUPPORT=n
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x44800000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IMX8M_DCSS=y
+CONFIG_VIDEO_IMX8M_HDMI=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x1E0
+CONFIG_AVB_WARNING_LOGO_ROWS=0x60
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="evk_8mq"
+CONFIG_ATTESTATION_ID_PRODUCT="evk_8mq"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="EVK_8MQ"
+CONFIG_SECURE_UNLOCK=y
+CONFIG_IMX_HAB=y
diff --git a/configs/imx8mq_evk_android_uuu_defconfig b/configs/imx8mq_evk_android_uuu_defconfig
new file mode 100644
index 00000000000..ed696565b76
--- /dev/null
+++ b/configs/imx8mq_evk_android_uuu_defconfig
@@ -0,0 +1,163 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0xA0000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX8MQ_EVK=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x44800000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RESET=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IMX8M_DCSS=y
+CONFIG_VIDEO_IMX8M_HDMI=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_CMD_BOOTA=n
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index 323a0f3996d..dc2c5003f29 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -1,27 +1,33 @@
 CONFIG_ARM=y
 CONFIG_ARCH_IMX8M=y
 CONFIG_SYS_TEXT_BASE=0x40200000
-CONFIG_SYS_MALLOC_LEN=0x600000
+CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x1000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_MEMTEST_START=0x40000000
+CONFIG_SYS_MEMTEST_END=0xA0000000
+CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk"
 CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_USB_TCPC=y
 CONFIG_TARGET_IMX8MQ_EVK=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_IMX_BOOTAUX=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk"
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_SYS_LOAD_ADDR=0x40400000
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
@@ -35,18 +41,32 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
 CONFIG_SPL_I2C=y
 CONFIG_SPL_POWER=y
 CONFIG_SPL_WATCHDOG=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
 CONFIG_SYS_PROMPT="u-boot=> "
 # CONFIG_BOOTM_NETBSD is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_NVEDIT_EFI=y
 # CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
 CONFIG_CMD_USB=y
-# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_OF_CONTROL=y
@@ -54,12 +74,32 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
 CONFIG_MXC_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_DM_ETH=y
@@ -78,9 +118,54 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPL_POWER_I2C=y
 CONFIG_DM_RESET=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
 CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
 CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IMX8M_DCSS=y
+CONFIG_VIDEO_IMX8M_HDMI=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
+CONFIG_EFI_SECURE_BOOT=y
+CONFIG_SPL_RSA=y
+CONFIG_SHA384=y
+CONFIG_EFI_VAR_BUF_SIZE=139264
+CONFIG_EFI_IGNORE_OSINDICATIONS=y
+CONFIG_EFI_CAPSULE_AUTHENTICATE=y
+CONFIG_OPTEE=y
+CONFIG_CMD_OPTEE_RPMB=y
+CONFIG_EFI_MM_COMM_TEE=y
+CONFIG_TEE=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_HAVE_CAPSULE_UPDATE=y
+CONFIG_FIT_SIGNATURE=y
diff --git a/configs/imx8qm_ddr4_val_defconfig b/configs/imx8qm_ddr4_val_defconfig
new file mode 100644
index 00000000000..3ad81fc695c
--- /dev/null
+++ b/configs/imx8qm_ddr4_val_defconfig
@@ -0,0 +1,171 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-ddr4-val"
+CONFIG_DEFAULT_FDT_FILE="imx8qm-ddr4-val.dtb"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QM_DDR4_VAL=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_val/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+
+CONFIG_VIDEO_IMX_HDP_LOAD=y
diff --git a/configs/imx8qm_lpddr4_val_defconfig b/configs/imx8qm_lpddr4_val_defconfig
new file mode 100644
index 00000000000..ff7855d1a0f
--- /dev/null
+++ b/configs/imx8qm_lpddr4_val_defconfig
@@ -0,0 +1,174 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-lpddr4-val"
+CONFIG_DEFAULT_FDT_FILE="imx8qm-lpddr4-val.dtb"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QM_LPDDR4_VAL=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_val/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+
+CONFIG_VIDEO_IMX_HDP_LOAD=y
diff --git a/configs/imx8qm_lpddr4_val_fspi_defconfig b/configs/imx8qm_lpddr4_val_fspi_defconfig
new file mode 100644
index 00000000000..4da05191c13
--- /dev/null
+++ b/configs/imx8qm_lpddr4_val_fspi_defconfig
@@ -0,0 +1,180 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-lpddr4-val"
+CONFIG_DEFAULT_FDT_FILE="imx8qm-lpddr4-val.dtb"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QM_LPDDR4_VAL=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_SPI_FLASH_TINY=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x200000
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_val/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_QSPI_BOOT=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+
+CONFIG_VIDEO_IMX_HDP_LOAD=y
diff --git a/configs/imx8qm_mek_android_defconfig b/configs/imx8qm_mek_android_defconfig
new file mode 100644
index 00000000000..4ae8b05fcfd
--- /dev/null
+++ b/configs/imx8qm_mek_android_defconfig
@@ -0,0 +1,208 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QM_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+
+CONFIG_VIDEO_IMX_HDP_LOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x1E0
+CONFIG_AVB_WARNING_LOGO_ROWS=0x60
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
diff --git a/configs/imx8qm_mek_android_dual_defconfig b/configs/imx8qm_mek_android_dual_defconfig
new file mode 100644
index 00000000000..7e465d0e031
--- /dev/null
+++ b/configs/imx8qm_mek_android_dual_defconfig
@@ -0,0 +1,209 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QM_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=y
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+
+CONFIG_VIDEO_IMX_HDP_LOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x1E0
+CONFIG_AVB_WARNING_LOGO_ROWS=0x60
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/imx8qm_mek_android_hdmi_defconfig b/configs/imx8qm_mek_android_hdmi_defconfig
new file mode 100644
index 00000000000..0551b0826c4
--- /dev/null
+++ b/configs/imx8qm_mek_android_hdmi_defconfig
@@ -0,0 +1,210 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QM_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+
+CONFIG_VIDEO_IMX_HDP_LOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x1E0
+CONFIG_AVB_WARNING_LOGO_ROWS=0x60
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_IMX_LOAD_HDMI_FIMRWARE_TX=y
+CONFIG_IMX_LOAD_HDMI_FIMRWARE_RX=y
diff --git a/configs/imx8qm_mek_android_trusty_defconfig b/configs/imx8qm_mek_android_trusty_defconfig
new file mode 100644
index 00000000000..ea93c9ce768
--- /dev/null
+++ b/configs/imx8qm_mek_android_trusty_defconfig
@@ -0,0 +1,215 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QM_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=y
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+
+CONFIG_VIDEO_IMX_HDP_LOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x1E0
+CONFIG_AVB_WARNING_LOGO_ROWS=0x60
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="mek_8q"
+CONFIG_ATTESTATION_ID_PRODUCT="mek_8q"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q"
+CONFIG_SHA256=y
diff --git a/configs/imx8qm_mek_android_trusty_dual_defconfig b/configs/imx8qm_mek_android_trusty_dual_defconfig
new file mode 100644
index 00000000000..7a8a7a3c1c5
--- /dev/null
+++ b/configs/imx8qm_mek_android_trusty_dual_defconfig
@@ -0,0 +1,216 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QM_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=y
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+
+CONFIG_VIDEO_IMX_HDP_LOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x1E0
+CONFIG_AVB_WARNING_LOGO_ROWS=0x60
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="mek_8q"
+CONFIG_ATTESTATION_ID_PRODUCT="mek_8q"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q"
+CONFIG_SHA256=y
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/imx8qm_mek_android_trusty_secure_unlock_defconfig b/configs/imx8qm_mek_android_trusty_secure_unlock_defconfig
new file mode 100644
index 00000000000..f46457629a3
--- /dev/null
+++ b/configs/imx8qm_mek_android_trusty_secure_unlock_defconfig
@@ -0,0 +1,217 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QM_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=y
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+
+CONFIG_VIDEO_IMX_HDP_LOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x1E0
+CONFIG_AVB_WARNING_LOGO_ROWS=0x60
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="mek_8q"
+CONFIG_ATTESTATION_ID_PRODUCT="mek_8q"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q"
+CONFIG_SHA256=y
+CONFIG_SECURE_UNLOCK=y
+CONFIG_AHAB_BOOT=y
diff --git a/configs/imx8qm_mek_android_uuu_defconfig b/configs/imx8qm_mek_android_uuu_defconfig
new file mode 100644
index 00000000000..6a558b16aa0
--- /dev/null
+++ b/configs/imx8qm_mek_android_uuu_defconfig
@@ -0,0 +1,202 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QM_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+
+CONFIG_VIDEO_IMX_HDP_LOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_CMD_BOOTA=n
diff --git a/configs/imx8qm_mek_androidauto2_trusty_defconfig b/configs/imx8qm_mek_androidauto2_trusty_defconfig
new file mode 100644
index 00000000000..0cd969bb527
--- /dev/null
+++ b/configs/imx8qm_mek_androidauto2_trusty_defconfig
@@ -0,0 +1,213 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QM_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=y
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+
+CONFIG_VIDEO_IMX_HDP_LOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_SHA256=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="mek_8q"
+CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car2"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q"
+CONFIG_ANDROID_AUTO_SUPPORT=y
+CONFIG_LOAD_KEY_FROM_RPMB=n
diff --git a/configs/imx8qm_mek_androidauto2_trusty_md_defconfig b/configs/imx8qm_mek_androidauto2_trusty_md_defconfig
new file mode 100644
index 00000000000..de51e6e6663
--- /dev/null
+++ b/configs/imx8qm_mek_androidauto2_trusty_md_defconfig
@@ -0,0 +1,214 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QM_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=y
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+
+CONFIG_VIDEO_IMX_HDP_LOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_SHA256=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="mek_8q"
+CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car2"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q"
+CONFIG_ANDROID_AUTO_SUPPORT=y
+CONFIG_LOAD_KEY_FROM_RPMB=n
+CONFIG_IMX_LOAD_HDMI_FIMRWARE_TX=y
diff --git a/configs/imx8qm_mek_androidauto_trusty_defconfig b/configs/imx8qm_mek_androidauto_trusty_defconfig
new file mode 100644
index 00000000000..9fcbc53e449
--- /dev/null
+++ b/configs/imx8qm_mek_androidauto_trusty_defconfig
@@ -0,0 +1,212 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QM_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=y
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88800000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x02000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+
+CONFIG_VIDEO_IMX_HDP_LOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_SHA256=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_DUAL_BOOTLOADER=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="mek_8q"
+CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q"
+CONFIG_ANDROID_AUTO_SUPPORT=y
diff --git a/configs/imx8qm_mek_androidauto_trusty_secure_unlock_defconfig b/configs/imx8qm_mek_androidauto_trusty_secure_unlock_defconfig
new file mode 100644
index 00000000000..2010ba1aa23
--- /dev/null
+++ b/configs/imx8qm_mek_androidauto_trusty_secure_unlock_defconfig
@@ -0,0 +1,214 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QM_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=y
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88800000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x02000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+
+CONFIG_VIDEO_IMX_HDP_LOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_SHA256=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_DUAL_BOOTLOADER=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="mek_8q"
+CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q"
+CONFIG_ANDROID_AUTO_SUPPORT=y
+CONFIG_SECURE_UNLOCK=y
+CONFIG_AHAB_BOOT=y
diff --git a/configs/imx8qm_mek_androidauto_xen_defconfig b/configs/imx8qm_mek_androidauto_xen_defconfig
new file mode 100644
index 00000000000..0cd969bb527
--- /dev/null
+++ b/configs/imx8qm_mek_androidauto_xen_defconfig
@@ -0,0 +1,213 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QM_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=y
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+
+CONFIG_VIDEO_IMX_HDP_LOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_SHA256=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="mek_8q"
+CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car2"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q"
+CONFIG_ANDROID_AUTO_SUPPORT=y
+CONFIG_LOAD_KEY_FROM_RPMB=n
diff --git a/configs/imx8qm_mek_cockpit_a53_defconfig b/configs/imx8qm_mek_cockpit_a53_defconfig
new file mode 100644
index 00000000000..a7d7fd4d1eb
--- /dev/null
+++ b/configs/imx8qm_mek_cockpit_a53_defconfig
@@ -0,0 +1,173 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_TARGET_IMX8QM_MEK_A53_ONLY=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_ENV_IS_NOWHERE=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-cockpit-a53"
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_IMX_HDP_LOAD=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
diff --git a/configs/imx8qm_mek_cockpit_a72_android_defconfig b/configs/imx8qm_mek_cockpit_a72_android_defconfig
new file mode 100644
index 00000000000..2db5bbedb4b
--- /dev/null
+++ b/configs/imx8qm_mek_cockpit_a72_android_defconfig
@@ -0,0 +1,152 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0xC0020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_MU_BASE_SPL=0x5d1e0000
+CONFIG_TARGET_IMX8QM_MEK_A72_ONLY=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0xC0200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_FIT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-cockpit-a72"
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_VIDEO=n
+CONFIG_VIDEO_IMX_HDP_LOAD=n
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0xC0400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FSL_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0xD8000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0xC8000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_LIBAVB=y
+CONFIG_CMD_MMC_RPMB=y
+CONFIG_SUPPORT_EMMC_RPMB=y
diff --git a/configs/imx8qm_mek_cockpit_a72_defconfig b/configs/imx8qm_mek_cockpit_a72_defconfig
new file mode 100644
index 00000000000..a34a2779c83
--- /dev/null
+++ b/configs/imx8qm_mek_cockpit_a72_defconfig
@@ -0,0 +1,168 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0xC0020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_MU_BASE_SPL=0x5d1e0000
+CONFIG_TARGET_IMX8QM_MEK_A72_ONLY=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_ENV_IS_NOWHERE=y
+CONFIG_SYS_LOAD_ADDR=0xC0200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-cockpit-a72"
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_IMX_HDP_LOAD=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=n
+CONFIG_USB_XHCI_IMX8=n
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_TCPC=n
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=n
+CONFIG_USB_CDNS3_GADGET=n
+CONFIG_USB_GADGET_DUALSPEED=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0xC0400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0xC2800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0xC8000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig
index 6a593f8480b..29e9d796a6b 100644
--- a/configs/imx8qm_mek_defconfig
+++ b/configs/imx8qm_mek_defconfig
@@ -3,25 +3,31 @@ CONFIG_ARCH_IMX8=y
 CONFIG_SYS_TEXT_BASE=0x80020000
 CONFIG_SYS_MALLOC_LEN=0x2400000
 CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=3
-CONFIG_ENV_SIZE=0x1000
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
 CONFIG_SPL_TEXT_BASE=0x100000
 CONFIG_TARGET_IMX8QM_MEK=y
 CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_SPL_LOAD_IMX_CONTAINER=y
 CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
 CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x80280000
-CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTCOMMAND=y
@@ -29,12 +35,11 @@ CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript
 CONFIG_LOG=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
 CONFIG_SPL_POWER_DOMAIN=y
-CONFIG_SPL_WATCHDOG=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_BOOTM_NETBSD is not set
@@ -50,13 +55,19 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_CLK=y
 CONFIG_CLK_IMX8=y
@@ -70,6 +81,10 @@ CONFIG_I2C_MUX_PCA954x=y
 CONFIG_MISC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ADDR_ENABLE=y
 CONFIG_PHY_ATHEROS=y
@@ -88,8 +103,96 @@ CONFIG_DM_REGULATOR=y
 CONFIG_SPL_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
 CONFIG_SPL_TINY_MEMSET=y
 # CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+
+CONFIG_VIDEO_IMX_HDP_LOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
diff --git a/configs/imx8qm_mek_fspi_defconfig b/configs/imx8qm_mek_fspi_defconfig
new file mode 100644
index 00000000000..52841941387
--- /dev/null
+++ b/configs/imx8qm_mek_fspi_defconfig
@@ -0,0 +1,197 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QM_MEK=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_SPI_FLASH_TINY=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x200000
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+
+CONFIG_VIDEO_IMX_HDP_LOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
diff --git a/configs/imx8qm_mek_trusty_xen_defconfig b/configs/imx8qm_mek_trusty_xen_defconfig
new file mode 100644
index 00000000000..0cd969bb527
--- /dev/null
+++ b/configs/imx8qm_mek_trusty_xen_defconfig
@@ -0,0 +1,213 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QM_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=y
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
+
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+
+CONFIG_VIDEO_IMX_HDP_LOAD=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_SHA256=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="mek_8q"
+CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car2"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q"
+CONFIG_ANDROID_AUTO_SUPPORT=y
+CONFIG_LOAD_KEY_FROM_RPMB=n
diff --git a/configs/imx8qxp_17x17_val_defconfig b/configs/imx8qxp_17x17_val_defconfig
new file mode 100644
index 00000000000..181a6696eb9
--- /dev/null
+++ b/configs/imx8qxp_17x17_val_defconfig
@@ -0,0 +1,161 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-17x17-val"
+CONFIG_DEFAULT_FDT_FILE="imx8qxp-17x17-val.dtb"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8X_17X17_VAL=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_val/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+# CONFIG_USB_CDNS3=y
+# CONFIG_USB_CDNS3_GADGET=y
+# CONFIG_USB_GADGET_DUALSPEED=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=0
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=0
+
+CONFIG_USB_PORT_AUTO=y
diff --git a/configs/imx8qxp_ddr3_val_defconfig b/configs/imx8qxp_ddr3_val_defconfig
new file mode 100644
index 00000000000..d2cc47f6306
--- /dev/null
+++ b/configs/imx8qxp_ddr3_val_defconfig
@@ -0,0 +1,173 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-val"
+CONFIG_DEFAULT_FDT_FILE="imx8qxp-ddr3l-val.dtb"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QXP_DDR3_VAL=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_val/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
diff --git a/configs/imx8qxp_lpddr4_val_defconfig b/configs/imx8qxp_lpddr4_val_defconfig
new file mode 100644
index 00000000000..fcc6f7a275d
--- /dev/null
+++ b/configs/imx8qxp_lpddr4_val_defconfig
@@ -0,0 +1,175 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-val"
+CONFIG_DEFAULT_FDT_FILE="imx8qxp-lpddr4-val.dtb"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QXP_LPDDR4_VAL=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_val/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_FSL_LPSPI=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
diff --git a/configs/imx8qxp_lpddr4_val_fspi_defconfig b/configs/imx8qxp_lpddr4_val_fspi_defconfig
new file mode 100644
index 00000000000..aba96c898b9
--- /dev/null
+++ b/configs/imx8qxp_lpddr4_val_fspi_defconfig
@@ -0,0 +1,179 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-val"
+CONFIG_DEFAULT_FDT_FILE="imx8qxp-lpddr4-val.dtb"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QXP_LPDDR4_VAL=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_SPI_FLASH_TINY=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x200000
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_val/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_QSPI_BOOT=y
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
diff --git a/configs/imx8qxp_lpddr4_val_nand_defconfig b/configs/imx8qxp_lpddr4_val_nand_defconfig
new file mode 100644
index 00000000000..7e3c6066199
--- /dev/null
+++ b/configs/imx8qxp_lpddr4_val_nand_defconfig
@@ -0,0 +1,175 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x7800000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-val-gpmi-nand"
+CONFIG_DEFAULT_FDT_FILE="imx8qxp-lpddr4-val-gpmi-nand.dtb"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QXP_LPDDR4_VAL=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_val/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="nand read ${loadaddr} 0x9000000 0x2000000; nand read ${fdt_addr} 0xB000000 0x100000; booti ${loadaddr} - ${fdt_addr}"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_NAND_BOOT=y
+CONFIG_CMD_UBI=y
+
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
+CONFIG_MTDPARTS_SKIP_INVALID=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
diff --git a/configs/imx8qxp_mek_android_defconfig b/configs/imx8qxp_mek_android_defconfig
new file mode 100644
index 00000000000..ef8f3fffb93
--- /dev/null
+++ b/configs/imx8qxp_mek_android_defconfig
@@ -0,0 +1,206 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QXP_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_SYS_I2C_IMX_VIRT_I2C=y
+CONFIG_I2C_MUX_IMX_VIRT=y
+CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x1E0
+CONFIG_AVB_WARNING_LOGO_ROWS=0x60
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
diff --git a/configs/imx8qxp_mek_android_dual_defconfig b/configs/imx8qxp_mek_android_dual_defconfig
new file mode 100644
index 00000000000..119c94f0493
--- /dev/null
+++ b/configs/imx8qxp_mek_android_dual_defconfig
@@ -0,0 +1,207 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QXP_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=y
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_SYS_I2C_IMX_VIRT_I2C=y
+CONFIG_I2C_MUX_IMX_VIRT=y
+CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x1E0
+CONFIG_AVB_WARNING_LOGO_ROWS=0x60
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/imx8qxp_mek_android_trusty_defconfig b/configs/imx8qxp_mek_android_trusty_defconfig
new file mode 100644
index 00000000000..65452853d90
--- /dev/null
+++ b/configs/imx8qxp_mek_android_trusty_defconfig
@@ -0,0 +1,213 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QXP_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=y
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_SYS_I2C_IMX_VIRT_I2C=y
+CONFIG_I2C_MUX_IMX_VIRT=y
+CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x1E0
+CONFIG_AVB_WARNING_LOGO_ROWS=0x60
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_SHA256=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="mek_8q"
+CONFIG_ATTESTATION_ID_PRODUCT="mek_8q"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q"
diff --git a/configs/imx8qxp_mek_android_trusty_dual_defconfig b/configs/imx8qxp_mek_android_trusty_dual_defconfig
new file mode 100644
index 00000000000..6363bc47a5e
--- /dev/null
+++ b/configs/imx8qxp_mek_android_trusty_dual_defconfig
@@ -0,0 +1,214 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QXP_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=y
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_SYS_I2C_IMX_VIRT_I2C=y
+CONFIG_I2C_MUX_IMX_VIRT=y
+CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x1E0
+CONFIG_AVB_WARNING_LOGO_ROWS=0x60
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_SHA256=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="mek_8q"
+CONFIG_ATTESTATION_ID_PRODUCT="mek_8q"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q"
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/imx8qxp_mek_android_trusty_secure_unlock_defconfig b/configs/imx8qxp_mek_android_trusty_secure_unlock_defconfig
new file mode 100644
index 00000000000..4fc4dba90b1
--- /dev/null
+++ b/configs/imx8qxp_mek_android_trusty_secure_unlock_defconfig
@@ -0,0 +1,215 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QXP_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=y
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_SYS_I2C_IMX_VIRT_I2C=y
+CONFIG_I2C_MUX_IMX_VIRT=y
+CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0x1E0
+CONFIG_AVB_WARNING_LOGO_ROWS=0x60
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_SHA256=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="mek_8q"
+CONFIG_ATTESTATION_ID_PRODUCT="mek_8q"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q"
+CONFIG_SECURE_UNLOCK=y
+CONFIG_AHAB_BOOT=y
diff --git a/configs/imx8qxp_mek_android_uuu_defconfig b/configs/imx8qxp_mek_android_uuu_defconfig
new file mode 100644
index 00000000000..80ff2f8cec1
--- /dev/null
+++ b/configs/imx8qxp_mek_android_uuu_defconfig
@@ -0,0 +1,200 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QXP_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_SYS_I2C_IMX_VIRT_I2C=y
+CONFIG_I2C_MUX_IMX_VIRT=y
+CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_CMD_BOOTA=n
diff --git a/configs/imx8qxp_mek_androidauto2_trusty_defconfig b/configs/imx8qxp_mek_androidauto2_trusty_defconfig
new file mode 100644
index 00000000000..1a9ecc88490
--- /dev/null
+++ b/configs/imx8qxp_mek_androidauto2_trusty_defconfig
@@ -0,0 +1,212 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QXP_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=y
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_SYS_I2C_IMX_VIRT_I2C=y
+CONFIG_I2C_MUX_IMX_VIRT=y
+CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+
+CONFIG_SHA256=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="mek_8q"
+CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car2"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q"
+CONFIG_ANDROID_AUTO_SUPPORT=y
+CONFIG_LOAD_KEY_FROM_RPMB=n
diff --git a/configs/imx8qxp_mek_androidauto_trusty_defconfig b/configs/imx8qxp_mek_androidauto_trusty_defconfig
new file mode 100644
index 00000000000..bae43783916
--- /dev/null
+++ b/configs/imx8qxp_mek_androidauto_trusty_defconfig
@@ -0,0 +1,211 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QXP_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=y
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_SYS_I2C_IMX_VIRT_I2C=y
+CONFIG_I2C_MUX_IMX_VIRT=y
+CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+
+CONFIG_SHA256=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_DUAL_BOOTLOADER=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="mek_8q"
+CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q"
+CONFIG_ANDROID_AUTO_SUPPORT=y
diff --git a/configs/imx8qxp_mek_androidauto_trusty_secure_unlock_defconfig b/configs/imx8qxp_mek_androidauto_trusty_secure_unlock_defconfig
new file mode 100644
index 00000000000..10989c26c52
--- /dev/null
+++ b/configs/imx8qxp_mek_androidauto_trusty_secure_unlock_defconfig
@@ -0,0 +1,213 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QXP_MEK=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=y
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT_BUF_ADDR=0x98000000
+CONFIG_FASTBOOT_BUF_SIZE=0x19000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_SYS_I2C_IMX_VIRT_I2C=y
+CONFIG_I2C_MUX_IMX_VIRT=y
+CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_LZ4=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_PSCI_BOARD_REBOOT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+
+CONFIG_SHA256=y
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_DUAL_BOOTLOADER=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="mek_8q"
+CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="MEK-MX8Q"
+CONFIG_ANDROID_AUTO_SUPPORT=y
+CONFIG_SECURE_UNLOCK=y
+CONFIG_AHAB_BOOT=y
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index 0d5c3f5a7a5..eda9d2cc00c 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -2,25 +2,32 @@ CONFIG_ARM=y
 CONFIG_ARCH_IMX8=y
 CONFIG_SYS_TEXT_BASE=0x80020000
 CONFIG_SYS_MALLOC_LEN=0x2400000
-CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=3
-CONFIG_ENV_SIZE=0x1000
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x400000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
 CONFIG_SPL_TEXT_BASE=0x100000
 CONFIG_TARGET_IMX8QXP_MEK=y
 CONFIG_SPL_MMC=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL=y
 CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
 CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
 CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x80280000
+CONFIG_SYS_LOAD_ADDR=0x80200000
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_BOOTDELAY=3
@@ -29,10 +36,10 @@ CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript
 CONFIG_LOG=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL_BOARD_INIT=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
@@ -42,7 +49,6 @@ CONFIG_CMD_CPU=y
 # CONFIG_CMD_CRC32 is not set
 CONFIG_CMD_CLK=y
 CONFIG_CMD_DM=y
-CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -50,7 +56,12 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
@@ -71,6 +82,10 @@ CONFIG_I2C_MUX_PCA954x=y
 CONFIG_MISC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ADDR_ENABLE=y
 CONFIG_PHY_ATHEROS=y
@@ -89,10 +104,93 @@ CONFIG_DM_REGULATOR=y
 CONFIG_SPL_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
-CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
-CONFIG_DM_THERMAL=y
-CONFIG_IMX_SCU_THERMAL=y
 CONFIG_SPL_TINY_MEMSET=y
 # CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_SYS_I2C_IMX_VIRT_I2C=y
+CONFIG_I2C_MUX_IMX_VIRT=y
+CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
diff --git a/configs/imx8qxp_mek_fspi_defconfig b/configs/imx8qxp_mek_fspi_defconfig
new file mode 100644
index 00000000000..56e3334828f
--- /dev/null
+++ b/configs/imx8qxp_mek_fspi_defconfig
@@ -0,0 +1,200 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_SYS_MALLOC_LEN=0x2400000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
+CONFIG_SPL_TEXT_BASE=0x100000
+CONFIG_TARGET_IMX8QXP_MEK=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_SPI_FLASH_TINY=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x200000
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_EFI_PARTITION=n
+CONFIG_SPL_DOS_PARTITION=n
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_PANIC_HANG=y
+CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg"
+CONFIG_SYS_LOAD_ADDR=0x80200000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if test ${sec_boot} = yes; then if run loadcntr; then run mmcboot; else run netboot; fi; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPL_TINY_MEMSET=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_MEMTEST=y
+
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_SCU_THERMAL=y
+
+CONFIG_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_CMD_SF=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_IMX8=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_TCPC=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_CDNS3_USB_PHY=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_SDP_USB_DEV=1
+CONFIG_SDP_LOADADDR=0x80400000
+
+CONFIG_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_USB_DEV=1
+
+CONFIG_SYS_I2C_IMX_VIRT_I2C=y
+CONFIG_I2C_MUX_IMX_VIRT=y
+CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000
+
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PCI=y
+
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_IMX_SNVS_SEC_SC=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+
+CONFIG_VIDEO_IMXDPUV1=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_IMX8_LVDS=y
+CONFIG_VIDEO_IT6263_BRIDGE=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
diff --git a/configs/imx8ulp_9x9_evk_android_defconfig b/configs/imx8ulp_9x9_evk_android_defconfig
new file mode 100644
index 00000000000..939de54baca
--- /dev/null
+++ b/configs/imx8ulp_9x9_evk_android_defconfig
@@ -0,0 +1,150 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8ULP=y
+CONFIG_SYS_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x1002000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_IMX_CONFIG=""
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-9x9-evk"
+CONFIG_SPL_TEXT_BASE=0x22020000
+CONFIG_TARGET_IMX8ULP_9X9_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8ulp-9x9-evk.dtb"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_ULP_WATCHDOG=y
+
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_FASTBOOT_USB_DEV=0
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_DCNANO=y
+CONFIG_VIDEO_IMX_NW_DSI=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_SCMI_POWER_DOMAIN=y
+CONFIG_POWER_DOMAIN=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_SCMI_THERMAL=y
+
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0xC8
+CONFIG_AVB_WARNING_LOGO_ROWS=0xC0
diff --git a/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig b/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig
new file mode 100644
index 00000000000..2154d9ad676
--- /dev/null
+++ b/configs/imx8ulp_9x9_evk_android_trusty_dual_defconfig
@@ -0,0 +1,157 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8ULP=y
+CONFIG_SYS_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x1002000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_IMX_CONFIG=""
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-9x9-evk"
+CONFIG_SPL_TEXT_BASE=0x22020000
+CONFIG_TARGET_IMX8ULP_9X9_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8ulp-9x9-evk.dtb"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_ULP_WATCHDOG=y
+
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_FASTBOOT_USB_DEV=0
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_DCNANO=y
+CONFIG_VIDEO_IMX_NW_DSI=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_SCMI_POWER_DOMAIN=y
+CONFIG_POWER_DOMAIN=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_SCMI_THERMAL=y
+
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0xC8
+CONFIG_AVB_WARNING_LOGO_ROWS=0xC0
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="evk_8ulp"
+CONFIG_ATTESTATION_ID_PRODUCT="evk_8ulp"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP"
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/imx8ulp_9x9_evk_android_uuu_defconfig b/configs/imx8ulp_9x9_evk_android_uuu_defconfig
new file mode 100644
index 00000000000..d816b90bb94
--- /dev/null
+++ b/configs/imx8ulp_9x9_evk_android_uuu_defconfig
@@ -0,0 +1,145 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8ULP=y
+CONFIG_SYS_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x1002000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_IMX_CONFIG=""
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-9x9-evk"
+CONFIG_SPL_TEXT_BASE=0x22020000
+CONFIG_TARGET_IMX8ULP_9X9_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8ulp-9x9-evk.dtb"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_ULP_WATCHDOG=y
+
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_FASTBOOT_USB_DEV=0
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_DCNANO=y
+CONFIG_VIDEO_IMX_NW_DSI=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_SCMI_POWER_DOMAIN=y
+CONFIG_POWER_DOMAIN=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_SCMI_THERMAL=y
+
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_CMD_BOOTA=n
diff --git a/configs/imx8ulp_9x9_evk_defconfig b/configs/imx8ulp_9x9_evk_defconfig
new file mode 100644
index 00000000000..48e88924177
--- /dev/null
+++ b/configs/imx8ulp_9x9_evk_defconfig
@@ -0,0 +1,140 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8ULP=y
+CONFIG_SYS_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x1002000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_IMX_CONFIG=""
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-9x9-evk"
+CONFIG_SPL_TEXT_BASE=0x22020000
+CONFIG_TARGET_IMX8ULP_9X9_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8ulp-9x9-evk.dtb"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_ULP_WATCHDOG=y
+
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_FASTBOOT_USB_DEV=0
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_DCNANO=y
+CONFIG_VIDEO_IMX_NW_DSI=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_SCMI_POWER_DOMAIN=y
+CONFIG_POWER_DOMAIN=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_SCMI_THERMAL=y
diff --git a/configs/imx8ulp_9x9_evk_i3c_defconfig b/configs/imx8ulp_9x9_evk_i3c_defconfig
new file mode 100644
index 00000000000..c5a53008a75
--- /dev/null
+++ b/configs/imx8ulp_9x9_evk_i3c_defconfig
@@ -0,0 +1,140 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8ULP=y
+CONFIG_SYS_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x1002000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_IMX_CONFIG=""
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-9x9-evk-i3c"
+CONFIG_SPL_TEXT_BASE=0x22020000
+CONFIG_TARGET_IMX8ULP_9X9_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8ulp-9x9-evk-i3c.dtb"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_SYS_I2C_IMX_I3C=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_ULP_WATCHDOG=y
+
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_FASTBOOT_USB_DEV=0
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_DCNANO=y
+CONFIG_VIDEO_IMX_NW_DSI=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_SCMI_POWER_DOMAIN=y
+CONFIG_POWER_DOMAIN=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_SCMI_THERMAL=y
diff --git a/configs/imx8ulp_evk_android_defconfig b/configs/imx8ulp_evk_android_defconfig
new file mode 100644
index 00000000000..b944e8cc6bc
--- /dev/null
+++ b/configs/imx8ulp_evk_android_defconfig
@@ -0,0 +1,150 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8ULP=y
+CONFIG_SYS_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x1002000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_IMX_CONFIG=""
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk"
+CONFIG_SPL_TEXT_BASE=0x22020000
+CONFIG_TARGET_IMX8ULP_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk.dtb"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_ULP_WATCHDOG=y
+
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_FASTBOOT_USB_DEV=0
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_DCNANO=y
+CONFIG_VIDEO_IMX_NW_DSI=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_SCMI_POWER_DOMAIN=y
+CONFIG_POWER_DOMAIN=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_SCMI_THERMAL=y
+
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0xC8
+CONFIG_AVB_WARNING_LOGO_ROWS=0xC0
diff --git a/configs/imx8ulp_evk_android_dual_defconfig b/configs/imx8ulp_evk_android_dual_defconfig
new file mode 100644
index 00000000000..84f31a638d2
--- /dev/null
+++ b/configs/imx8ulp_evk_android_dual_defconfig
@@ -0,0 +1,151 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8ULP=y
+CONFIG_SYS_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x1002000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_IMX_CONFIG=""
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk"
+CONFIG_SPL_TEXT_BASE=0x22020000
+CONFIG_TARGET_IMX8ULP_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk.dtb"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_ULP_WATCHDOG=y
+
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_FASTBOOT_USB_DEV=0
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_DCNANO=y
+CONFIG_VIDEO_IMX_NW_DSI=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_SCMI_POWER_DOMAIN=y
+CONFIG_POWER_DOMAIN=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_SCMI_THERMAL=y
+
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0xC8
+CONFIG_AVB_WARNING_LOGO_ROWS=0xC0
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/imx8ulp_evk_android_trusty_defconfig b/configs/imx8ulp_evk_android_trusty_defconfig
new file mode 100644
index 00000000000..c6e2378b824
--- /dev/null
+++ b/configs/imx8ulp_evk_android_trusty_defconfig
@@ -0,0 +1,156 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8ULP=y
+CONFIG_SYS_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x1002000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_IMX_CONFIG=""
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk"
+CONFIG_SPL_TEXT_BASE=0x22020000
+CONFIG_TARGET_IMX8ULP_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk.dtb"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_ULP_WATCHDOG=y
+
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_FASTBOOT_USB_DEV=0
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_DCNANO=y
+CONFIG_VIDEO_IMX_NW_DSI=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_SCMI_POWER_DOMAIN=y
+CONFIG_POWER_DOMAIN=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_SCMI_THERMAL=y
+
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0xC8
+CONFIG_AVB_WARNING_LOGO_ROWS=0xC0
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="evk_8ulp"
+CONFIG_ATTESTATION_ID_PRODUCT="evk_8ulp"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP"
diff --git a/configs/imx8ulp_evk_android_trusty_dual_defconfig b/configs/imx8ulp_evk_android_trusty_dual_defconfig
new file mode 100644
index 00000000000..1f345e8d1f3
--- /dev/null
+++ b/configs/imx8ulp_evk_android_trusty_dual_defconfig
@@ -0,0 +1,157 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8ULP=y
+CONFIG_SYS_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x1002000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_IMX_CONFIG=""
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk"
+CONFIG_SPL_TEXT_BASE=0x22020000
+CONFIG_TARGET_IMX8ULP_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk.dtb"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_ULP_WATCHDOG=y
+
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_FASTBOOT_USB_DEV=0
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_DCNANO=y
+CONFIG_VIDEO_IMX_NW_DSI=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_SCMI_POWER_DOMAIN=y
+CONFIG_POWER_DOMAIN=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_SCMI_THERMAL=y
+
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0xC8
+CONFIG_AVB_WARNING_LOGO_ROWS=0xC0
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="evk_8ulp"
+CONFIG_ATTESTATION_ID_PRODUCT="evk_8ulp"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP"
+CONFIG_DUAL_BOOTLOADER=y
diff --git a/configs/imx8ulp_evk_android_trusty_secure_unlock_defconfig b/configs/imx8ulp_evk_android_trusty_secure_unlock_defconfig
new file mode 100644
index 00000000000..cbf8db32ce8
--- /dev/null
+++ b/configs/imx8ulp_evk_android_trusty_secure_unlock_defconfig
@@ -0,0 +1,158 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8ULP=y
+CONFIG_SYS_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x1002000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_IMX_CONFIG=""
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk"
+CONFIG_SPL_TEXT_BASE=0x22020000
+CONFIG_TARGET_IMX8ULP_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk.dtb"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_ULP_WATCHDOG=y
+
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=n
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0xc800000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_FASTBOOT_USB_DEV=0
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_DCNANO=y
+CONFIG_VIDEO_IMX_NW_DSI=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_SCMI_POWER_DOMAIN=y
+CONFIG_POWER_DOMAIN=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_SCMI_THERMAL=y
+
+CONFIG_LZ4=y
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_APPEND_BOOTARGS=y
+CONFIG_SPL_MMC=y
+CONFIG_VIRTUAL_AB_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_AVB_WARNING_LOGO=y
+CONFIG_AVB_WARNING_LOGO_COLS=0xC8
+CONFIG_AVB_WARNING_LOGO_ROWS=0xC0
+CONFIG_IMX_TRUSTY_OS=y
+CONFIG_ATTESTATION_ID_BRAND="Android"
+CONFIG_ATTESTATION_ID_DEVICE="evk_8ulp"
+CONFIG_ATTESTATION_ID_PRODUCT="evk_8ulp"
+CONFIG_ATTESTATION_ID_MANUFACTURER="nxp"
+CONFIG_ATTESTATION_ID_MODEL="EVK_8ULP"
+CONFIG_SECURE_UNLOCK=y
+CONFIG_AHAB_BOOT=y
diff --git a/configs/imx8ulp_evk_android_uuu_defconfig b/configs/imx8ulp_evk_android_uuu_defconfig
new file mode 100644
index 00000000000..966f40d1694
--- /dev/null
+++ b/configs/imx8ulp_evk_android_uuu_defconfig
@@ -0,0 +1,145 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8ULP=y
+CONFIG_SYS_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x1002000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_IMX_CONFIG=""
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk"
+CONFIG_SPL_TEXT_BASE=0x22020000
+CONFIG_TARGET_IMX8ULP_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk.dtb"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_ULP_WATCHDOG=y
+
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_FASTBOOT_USB_DEV=0
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_DCNANO=y
+CONFIG_VIDEO_IMX_NW_DSI=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_SCMI_POWER_DOMAIN=y
+CONFIG_POWER_DOMAIN=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_SCMI_THERMAL=y
+
+CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y
+CONFIG_ANDROID_SUPPORT=y
+CONFIG_ANDROID_AB_SUPPORT=y
+CONFIG_CMD_BOOTA=n
diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig
index 0e2a646ebf1..98ed956a206 100644
--- a/configs/imx8ulp_evk_defconfig
+++ b/configs/imx8ulp_evk_defconfig
@@ -5,9 +5,11 @@ CONFIG_SYS_MALLOC_LEN=0x1002000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MMC_ENV_DEV=0
 CONFIG_IMX_CONFIG=""
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk"
@@ -20,12 +22,11 @@ CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
 CONFIG_SPL_LOAD_IMX_CONTAINER=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_REMAKE_ELF=y
-CONFIG_SYS_LOAD_ADDR=0x80480000
+CONFIG_SYS_LOAD_ADDR=0x80400000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
-CONFIG_BOOTDELAY=0
 CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
-CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk"
+CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk.dtb"
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_BOARD_INIT=y
@@ -43,9 +44,13 @@ CONFIG_CMD_READ=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_SYSTEM_SETUP=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM=y
@@ -56,10 +61,17 @@ CONFIG_SYS_I2C_IMX_LPI2C=y
 CONFIG_MISC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_FSL_USDHC=y
 CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
@@ -74,7 +86,55 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_NXP_FSPI=y
 CONFIG_ULP_WATCHDOG=y
+
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_FASTBOOT_USB_DEV=0
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_DCNANO=y
+CONFIG_VIDEO_IMX_NW_DSI=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_SCMI_POWER_DOMAIN=y
+CONFIG_POWER_DOMAIN=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_SCMI_THERMAL=y
diff --git a/configs/imx8ulp_evk_i3c_defconfig b/configs/imx8ulp_evk_i3c_defconfig
new file mode 100644
index 00000000000..ce6e7d14ee4
--- /dev/null
+++ b/configs/imx8ulp_evk_i3c_defconfig
@@ -0,0 +1,141 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8ULP=y
+CONFIG_SYS_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x1002000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_IMX_CONFIG=""
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk-i3c"
+CONFIG_SPL_TEXT_BASE=0x22020000
+CONFIG_TARGET_IMX8ULP_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=0
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk-i3c.dtb"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_SYS_I2C_IMX_I3C=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_ULP_WATCHDOG=y
+
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_FASTBOOT_USB_DEV=0
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_DCNANO=y
+CONFIG_VIDEO_IMX_NW_DSI=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_SCMI_POWER_DOMAIN=y
+CONFIG_POWER_DOMAIN=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_SCMI_THERMAL=y
diff --git a/configs/imx8ulp_evk_nd_defconfig b/configs/imx8ulp_evk_nd_defconfig
new file mode 100644
index 00000000000..800f2c26c7f
--- /dev/null
+++ b/configs/imx8ulp_evk_nd_defconfig
@@ -0,0 +1,142 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8ULP=y
+CONFIG_SYS_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x1002000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_IMX_CONFIG=""
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk"
+CONFIG_SPL_TEXT_BASE=0x22020000
+CONFIG_TARGET_IMX8ULP_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=0
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk.dtb"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_NXP_FSPI=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SF_DEFAULT_BUS=2
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_ULP_WATCHDOG=y
+
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_FASTBOOT_USB_DEV=0
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_DCNANO=y
+CONFIG_VIDEO_IMX_NW_DSI=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_SCMI_POWER_DOMAIN=y
+CONFIG_POWER_DOMAIN=y
+
+CONFIG_DM_THERMAL=y
+CONFIG_SCMI_THERMAL=y
+CONFIG_IMX8ULP_ND_MODE=y
diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig
new file mode 100644
index 00000000000..9ea7b851afa
--- /dev/null
+++ b/configs/imx93_11x11_evk_defconfig
@@ -0,0 +1,172 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX9=y
+CONFIG_SYS_TEXT_BASE=0x80200000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x18000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x90000000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_IMX_CONFIG=""
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk"
+CONFIG_SPL_TEXT_BASE=0x2049A000
+CONFIG_USB_TCPC=y
+CONFIG_TARGET_IMX93_11X11_EVK=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
+CONFIG_SPL_LOAD_IMX_CONTAINER=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_LOAD_ADDR=0x80400000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_NVEDIT_EFI=y
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_FASTBOOT_USB_DEV=0
+CONFIG_USB_PORT_AUTO=y
+
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX93=y
+CONFIG_DM_PMIC=y
+CONFIG_SPL_DM_PMIC_PCA9450=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_ULP_WATCHDOG=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_IMX_RGPIO2P=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CLK_IMX93=y
+CONFIG_SPL_CLK_IMX93=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_ADP5585_GPIO=y
+
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX93_BLK_CTRL=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX93_MIPI_DPHY=y
+CONFIG_MIPI_DPHY_HELPERS=y
+CONFIG_VIDEO_IMX_LCDIFV3=y
+CONFIG_VIDEO_IMX_DW_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
+CONFIG_VIDEO_ADV7535=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig
index 911b4dba3a2..f8de2af5945 100644
--- a/configs/ls1021aiot_qspi_defconfig
+++ b/configs/ls1021aiot_qspi_defconfig
@@ -40,6 +40,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig
index f72f2b1bb50..8834e4490b5 100644
--- a/configs/ls1021aiot_sdcard_defconfig
+++ b/configs/ls1021aiot_sdcard_defconfig
@@ -57,6 +57,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index 925d68db8e1..33ef9e871c7 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -53,6 +53,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index c71c8649d92..2a639e82f23 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -54,6 +54,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index 58629beb0c7..e13e24a24fd 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -74,6 +74,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index fb9f457b74d..d9002390e95 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -53,6 +53,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index 1d6d88ff372..a3d08886158 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -54,6 +54,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index f629080be23..40a9211dde8 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -52,6 +52,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index 38b17048c4f..dea751e245c 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -71,6 +71,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index eb97c18fdd6..679b169f019 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -69,6 +69,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig
index 45b05adbb49..328912e111e 100644
--- a/configs/ls1021atsn_qspi_defconfig
+++ b/configs/ls1021atsn_qspi_defconfig
@@ -38,6 +38,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig
index 7bc1963b2f3..cd2ce844ce7 100644
--- a/configs/ls1021atsn_sdcard_defconfig
+++ b/configs/ls1021atsn_sdcard_defconfig
@@ -54,6 +54,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index c1adc6e23fa..2dd9a81849b 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -47,6 +47,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index 150179d6334..c86843b39b6 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -48,6 +48,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index 016771a8f6d..79b8bdc63ff 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -48,6 +48,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index a8288e9fb6a..18336c77b01 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -62,6 +62,7 @@ CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
+CONFIG_SPL_OF_CONTROL=y
 # CONFIG_SPL_BLK is not set
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index 695505a9752..efb0432b3f8 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -65,6 +65,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 19e7751e785..2bf7550ebaa 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -65,6 +65,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index ef1a591ec09..ce5ff579991 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -53,6 +53,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index 8dd6ce41d6c..9e73c42c459 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -54,6 +54,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index 3e548031071..bb8891fedc3 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -73,6 +73,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index 97fe2ce8bd6..f0a7bc8de26 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -53,6 +53,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_DDR_ECC=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index dd0a726502d..b97c5e9ac93 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -54,6 +54,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index be40f49f6e1..87e68f1ce30 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -72,6 +72,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index 58204444043..e1f994d1768 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -71,6 +71,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig
index 6a897948850..e5cdb183d5f 100644
--- a/configs/ls1043aqds_tfa_defconfig
+++ b/configs/ls1043aqds_tfa_defconfig
@@ -61,6 +61,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 4812f59f227..0387716a027 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -40,6 +40,7 @@ CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0x60300000
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 # CONFIG_DDR_SPD is not set
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_MPC8XXX_GPIO=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index 6662c6c6bad..7e68e25c225 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -61,6 +61,7 @@ CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index cccd9849205..4e3f436db02 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -60,6 +60,7 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SPL_SYS_I2C_LEGACY=y
diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig
index 3a3edabf338..c4fd4193268 100644
--- a/configs/ls1043ardb_tfa_defconfig
+++ b/configs/ls1043ardb_tfa_defconfig
@@ -45,6 +45,7 @@ CONFIG_ENV_IS_IN_NAND=y
 CONFIG_ENV_ADDR=0x60500000
 CONFIG_DM=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 # CONFIG_DDR_SPD is not set
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_MPC8XXX_GPIO=y
diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig
index 0fbd1f27ff6..a3780623481 100644
--- a/configs/ls1046afrwy_tfa_defconfig
+++ b/configs/ls1046afrwy_tfa_defconfig
@@ -42,6 +42,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 # CONFIG_DDR_SPD is not set
 CONFIG_MPC8XXX_GPIO=y
 CONFIG_DM_I2C=y
diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig
index bc326114cd1..9a9d79b1099 100644
--- a/configs/ls1046aqds_defconfig
+++ b/configs/ls1046aqds_defconfig
@@ -54,6 +54,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig
index 52855d12e51..51ddd7f28ac 100644
--- a/configs/ls1046aqds_lpuart_defconfig
+++ b/configs/ls1046aqds_lpuart_defconfig
@@ -55,6 +55,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig
index ab780c16221..f2b16ddd718 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -73,6 +73,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig
index 8111ce6432b..cadd0161607 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -55,6 +55,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig
index b5b501c9a95..ca3c4047266 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -74,6 +74,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig
index 01451930e6b..616558acdb8 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -73,6 +73,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig
index 11de0d40afa..8295682d99f 100644
--- a/configs/ls1046aqds_tfa_defconfig
+++ b/configs/ls1046aqds_tfa_defconfig
@@ -62,6 +62,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
index a319bf39fc7..926df893c14 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -63,6 +63,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_MPC8XXX_GPIO=y
diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
index 506b32c2487..691c72862a3 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -49,6 +49,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_MPC8XXX_GPIO=y
diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig
index 87ab8ac4215..b1a59b83572 100644
--- a/configs/ls1046ardb_qspi_spl_defconfig
+++ b/configs/ls1046ardb_qspi_spl_defconfig
@@ -68,6 +68,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_MPC8XXX_GPIO=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index 033ccc24e69..2e3ed3c3e23 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -62,6 +62,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_MPC8XXX_GPIO=y
diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig
index 72a3a0f5f2a..c9278ce4ff5 100644
--- a/configs/ls1046ardb_tfa_defconfig
+++ b/configs/ls1046ardb_tfa_defconfig
@@ -47,6 +47,7 @@ CONFIG_DM=y
 CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
+CONFIG_ARCH_MISC_INIT=y
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_MPC8XXX_GPIO=y
diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig
new file mode 100644
index 00000000000..d469fa1462d
--- /dev/null
+++ b/configs/mx6dlsabreauto_defconfig
@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6DL=y
+CONFIG_TARGET_MX6DLSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/mx6dl.cfg"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6dlsabreauto_eimnor_defconfig b/configs/mx6dlsabreauto_eimnor_defconfig
new file mode 100644
index 00000000000..2c9180c86d1
--- /dev/null
+++ b/configs/mx6dlsabreauto_eimnor_defconfig
@@ -0,0 +1,102 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6DL=y
+CONFIG_TARGET_MX6DLSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_ENV_ADDR=0x080E0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/mx6dl.cfg"
+CONFIG_NOR=y
+CONFIG_NOR_BOOT=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto-gpmi-weim"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_MAX_FLASH_BANKS=1
+CONFIG_CMD_FLASH=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6dlsabreauto_nand_defconfig b/configs/mx6dlsabreauto_nand_defconfig
new file mode 100644
index 00000000000..7990e0a32bc
--- /dev/null
+++ b/configs/mx6dlsabreauto_nand_defconfig
@@ -0,0 +1,105 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6DL=y
+CONFIG_TARGET_MX6DLSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x3C00000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/mx6dl.cfg"
+CONFIG_NAND_BOOT=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor,nand0=gpmi-nand"
+CONFIG_MTDPARTS_SKIP_INVALID=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto-gpmi-weim"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6dlsabreauto_optee_defconfig b/configs/mx6dlsabreauto_optee_defconfig
new file mode 100644
index 00000000000..a50f156465c
--- /dev/null
+++ b/configs/mx6dlsabreauto_optee_defconfig
@@ -0,0 +1,99 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6DL=y
+CONFIG_TARGET_MX6DLSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/mx6dl.cfg"
+CONFIG_IMX_OPTEE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;run findtee;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6dlsabreauto_plugin_defconfig b/configs/mx6dlsabreauto_plugin_defconfig
new file mode 100644
index 00000000000..78b0d346cfa
--- /dev/null
+++ b/configs/mx6dlsabreauto_plugin_defconfig
@@ -0,0 +1,99 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6DL=y
+CONFIG_TARGET_MX6DLSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/mx6dl.cfg"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6dlsabreauto_spinor_defconfig b/configs/mx6dlsabreauto_spinor_defconfig
new file mode 100644
index 00000000000..162a98dde0e
--- /dev/null
+++ b/configs/mx6dlsabreauto_spinor_defconfig
@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6DL=y
+CONFIG_TARGET_MX6DLSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/mx6dl.cfg"
+CONFIG_SPI_BOOT=y
+CONFIG_CMD_SF=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_MXC_SPI=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto-ecspi"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig
new file mode 100644
index 00000000000..b23a524fb20
--- /dev/null
+++ b/configs/mx6dlsabresd_defconfig
@@ -0,0 +1,109 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6DL=y
+CONFIG_TARGET_MX6DLSABRESD=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabresd/mx6dlsabresd.cfg"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6dlsabresd_epdc_defconfig b/configs/mx6dlsabresd_epdc_defconfig
new file mode 100644
index 00000000000..79d5742e1e2
--- /dev/null
+++ b/configs/mx6dlsabresd_epdc_defconfig
@@ -0,0 +1,104 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6DL=y
+CONFIG_TARGET_MX6DLSABRESD=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabresd/mx6dlsabresd.cfg"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_MXC_EPDC=y
+CONFIG_LCD=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6dlsabresd_optee_defconfig b/configs/mx6dlsabresd_optee_defconfig
new file mode 100644
index 00000000000..aca36d95df9
--- /dev/null
+++ b/configs/mx6dlsabresd_optee_defconfig
@@ -0,0 +1,110 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6DL=y
+CONFIG_TARGET_MX6DLSABRESD=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabresd/mx6dlsabresd.cfg"
+CONFIG_IMX_OPTEE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;run findtee;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6dlsabresd_plugin_defconfig b/configs/mx6dlsabresd_plugin_defconfig
new file mode 100644
index 00000000000..417607a2912
--- /dev/null
+++ b/configs/mx6dlsabresd_plugin_defconfig
@@ -0,0 +1,110 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6DL=y
+CONFIG_TARGET_MX6DLSABRESD=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabresd/mx6dlsabresd.cfg"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig
new file mode 100644
index 00000000000..553bc99c717
--- /dev/null
+++ b/configs/mx6qpsabreauto_defconfig
@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6QP=y
+CONFIG_TARGET_MX6QPSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/mx6qp.cfg"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6qpsabreauto_eimnor_defconfig b/configs/mx6qpsabreauto_eimnor_defconfig
new file mode 100644
index 00000000000..8bd43ffb72e
--- /dev/null
+++ b/configs/mx6qpsabreauto_eimnor_defconfig
@@ -0,0 +1,102 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6QP=y
+CONFIG_TARGET_MX6QPSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_ENV_ADDR=0x080E0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/mx6qp.cfg"
+CONFIG_NOR=y
+CONFIG_NOR_BOOT=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto-gpmi-weim"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_MAX_FLASH_BANKS=1
+CONFIG_CMD_FLASH=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6qpsabreauto_nand_defconfig b/configs/mx6qpsabreauto_nand_defconfig
new file mode 100644
index 00000000000..7eebfcab1e4
--- /dev/null
+++ b/configs/mx6qpsabreauto_nand_defconfig
@@ -0,0 +1,105 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6QP=y
+CONFIG_TARGET_MX6QPSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x3C00000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/mx6qp.cfg"
+CONFIG_NAND_BOOT=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor,nand0=gpmi-nand"
+CONFIG_MTDPARTS_SKIP_INVALID=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto-gpmi-weim"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6qpsabreauto_optee_defconfig b/configs/mx6qpsabreauto_optee_defconfig
new file mode 100644
index 00000000000..a53cac34e87
--- /dev/null
+++ b/configs/mx6qpsabreauto_optee_defconfig
@@ -0,0 +1,99 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6QP=y
+CONFIG_TARGET_MX6QPSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/mx6qp.cfg"
+CONFIG_IMX_OPTEE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;run findtee;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6qpsabreauto_plugin_defconfig b/configs/mx6qpsabreauto_plugin_defconfig
new file mode 100644
index 00000000000..6075500b55a
--- /dev/null
+++ b/configs/mx6qpsabreauto_plugin_defconfig
@@ -0,0 +1,99 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6QP=y
+CONFIG_TARGET_MX6QPSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/mx6qp.cfg"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6qpsabreauto_sata_defconfig b/configs/mx6qpsabreauto_sata_defconfig
new file mode 100644
index 00000000000..472eb10c8e5
--- /dev/null
+++ b/configs/mx6qpsabreauto_sata_defconfig
@@ -0,0 +1,104 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6QP=y
+CONFIG_TARGET_MX6QPSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/mx6qp.cfg"
+CONFIG_SATA_BOOT=y
+CONFIG_ENV_IS_IN_SATA=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
diff --git a/configs/mx6qpsabreauto_spinor_defconfig b/configs/mx6qpsabreauto_spinor_defconfig
new file mode 100644
index 00000000000..229494f00e4
--- /dev/null
+++ b/configs/mx6qpsabreauto_spinor_defconfig
@@ -0,0 +1,109 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6QP=y
+CONFIG_TARGET_MX6QPSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/mx6qp.cfg"
+CONFIG_SPI_BOOT=y
+CONFIG_CMD_SF=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_MXC_SPI=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto-ecspi"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6qpsabresd_defconfig b/configs/mx6qpsabresd_defconfig
new file mode 100644
index 00000000000..ba364999106
--- /dev/null
+++ b/configs/mx6qpsabresd_defconfig
@@ -0,0 +1,109 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6QP=y
+CONFIG_TARGET_MX6QPSABRESD=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabresd/mx6qp.cfg"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabresd"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6qpsabresd_optee_defconfig b/configs/mx6qpsabresd_optee_defconfig
new file mode 100644
index 00000000000..77978c9561d
--- /dev/null
+++ b/configs/mx6qpsabresd_optee_defconfig
@@ -0,0 +1,110 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6QP=y
+CONFIG_TARGET_MX6QPSABRESD=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabresd/mx6qp.cfg"
+CONFIG_IMX_OPTEE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;run findtee;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabresd"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6qpsabresd_sata_defconfig b/configs/mx6qpsabresd_sata_defconfig
new file mode 100644
index 00000000000..19e72e2b177
--- /dev/null
+++ b/configs/mx6qpsabresd_sata_defconfig
@@ -0,0 +1,113 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6QP=y
+CONFIG_TARGET_MX6QPSABRESD=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabresd/mx6qp.cfg"
+CONFIG_SATA_BOOT=y
+CONFIG_ENV_IS_IN_SATA=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabresd"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PCI=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig
new file mode 100644
index 00000000000..c2e92a947ed
--- /dev/null
+++ b/configs/mx6qsabreauto_defconfig
@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6Q=y
+CONFIG_TARGET_MX6QSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/imximage.cfg"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6qsabreauto_eimnor_defconfig b/configs/mx6qsabreauto_eimnor_defconfig
new file mode 100644
index 00000000000..82058608653
--- /dev/null
+++ b/configs/mx6qsabreauto_eimnor_defconfig
@@ -0,0 +1,102 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6Q=y
+CONFIG_TARGET_MX6QSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_ENV_ADDR=0x080E0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/imximage.cfg"
+CONFIG_NOR=y
+CONFIG_NOR_BOOT=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto-gpmi-weim"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_MAX_FLASH_BANKS=1
+CONFIG_CMD_FLASH=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6qsabreauto_nand_defconfig b/configs/mx6qsabreauto_nand_defconfig
new file mode 100644
index 00000000000..d1479557f0f
--- /dev/null
+++ b/configs/mx6qsabreauto_nand_defconfig
@@ -0,0 +1,105 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6Q=y
+CONFIG_TARGET_MX6QSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x3C00000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/imximage.cfg"
+CONFIG_NAND_BOOT=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor,nand0=gpmi-nand"
+CONFIG_MTDPARTS_SKIP_INVALID=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto-gpmi-weim"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6qsabreauto_optee_defconfig b/configs/mx6qsabreauto_optee_defconfig
new file mode 100644
index 00000000000..7ba7d641d7c
--- /dev/null
+++ b/configs/mx6qsabreauto_optee_defconfig
@@ -0,0 +1,99 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6Q=y
+CONFIG_TARGET_MX6QSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/imximage.cfg"
+CONFIG_IMX_OPTEE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;run findtee;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6qsabreauto_plugin_defconfig b/configs/mx6qsabreauto_plugin_defconfig
new file mode 100644
index 00000000000..5d90ecde91f
--- /dev/null
+++ b/configs/mx6qsabreauto_plugin_defconfig
@@ -0,0 +1,99 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6Q=y
+CONFIG_TARGET_MX6QSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/imximage.cfg"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6qsabreauto_sata_defconfig b/configs/mx6qsabreauto_sata_defconfig
new file mode 100644
index 00000000000..9b71e45b166
--- /dev/null
+++ b/configs/mx6qsabreauto_sata_defconfig
@@ -0,0 +1,104 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6Q=y
+CONFIG_TARGET_MX6QSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/imximage.cfg"
+CONFIG_SATA_BOOT=y
+CONFIG_ENV_IS_IN_SATA=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
diff --git a/configs/mx6qsabreauto_spinor_defconfig b/configs/mx6qsabreauto_spinor_defconfig
new file mode 100644
index 00000000000..5c51939b4f6
--- /dev/null
+++ b/configs/mx6qsabreauto_spinor_defconfig
@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6Q=y
+CONFIG_TARGET_MX6QSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/imximage.cfg"
+CONFIG_SPI_BOOT=y
+CONFIG_CMD_SF=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_MXC_SPI=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto-ecspi"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index 2b77a46badd..6817c6f88a8 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -76,8 +76,8 @@ CONFIG_USB_KEYBOARD=y
 CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Boundary"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
 CONFIG_CI_UDC=y
 CONFIG_USB_ETHER=y
 CONFIG_USB_ETH_CDC=y
diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig
new file mode 100644
index 00000000000..986fab886d2
--- /dev/null
+++ b/configs/mx6qsabresd_defconfig
@@ -0,0 +1,109 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_TARGET_MX6QSABRESD=y
+CONFIG_MX6Q=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6qsabresd_optee_defconfig b/configs/mx6qsabresd_optee_defconfig
new file mode 100644
index 00000000000..93187e1f411
--- /dev/null
+++ b/configs/mx6qsabresd_optee_defconfig
@@ -0,0 +1,110 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_TARGET_MX6QSABRESD=y
+CONFIG_MX6Q=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg"
+CONFIG_IMX_OPTEE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;run findtee;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6qsabresd_plugin_defconfig b/configs/mx6qsabresd_plugin_defconfig
new file mode 100644
index 00000000000..f2e85177b95
--- /dev/null
+++ b/configs/mx6qsabresd_plugin_defconfig
@@ -0,0 +1,110 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_TARGET_MX6QSABRESD=y
+CONFIG_MX6Q=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6qsabresd_sata_defconfig b/configs/mx6qsabresd_sata_defconfig
new file mode 100644
index 00000000000..11c7c1d8daa
--- /dev/null
+++ b/configs/mx6qsabresd_sata_defconfig
@@ -0,0 +1,113 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_TARGET_MX6QSABRESD=y
+CONFIG_MX6Q=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg"
+CONFIG_SATA_BOOT=y
+CONFIG_ENV_IS_IN_SATA=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PCI=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_AHCI=y
+CONFIG_IMX_AHCI=y
+CONFIG_DM_SCSI=y
+CONFIG_SCSI=y
+CONFIG_CMD_SCSI=y
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index 1bf86d01373..fe3ec767486 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -62,10 +62,8 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIST="imx6dl-sabreauto imx6q-sabreauto imx6qp-sabreauto"
 CONFIG_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -106,8 +104,8 @@ CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_DM_VIDEO=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 233a1652a6e..d2f5f8df157 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -65,12 +65,8 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_EFI_PARTITION=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
-CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIST="imx6q-sabresd imx6qp-sabresd imx6dl-sabresd"
 CONFIG_MULTI_DTB_FIT=y
-CONFIG_SPL_MULTI_DTB_FIT=y
-CONFIG_SPL_OF_LIST="imx6dl-sabresd imx6q-sabresd imx6qp-sabresd"
-CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -114,8 +110,8 @@ CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
 CONFIG_CI_UDC=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_LOGO=y
diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig
index 12789c934c0..2cc16e21109 100644
--- a/configs/mx6slevk_defconfig
+++ b/configs/mx6slevk_defconfig
@@ -1,22 +1,26 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_SYS_MALLOC_LEN=0x300000
+CONFIG_SYS_MALLOC_LEN=0x1000000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x80000
+CONFIG_ENV_OFFSET=0xE0000
 CONFIG_MX6SL=y
 CONFIG_TARGET_MX6SLEVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
-# CONFIG_CMD_BMODE is not set
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
 CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -69,3 +73,20 @@ CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6slevk_epdc_defconfig b/configs/mx6slevk_epdc_defconfig
new file mode 100644
index 00000000000..638afd52080
--- /dev/null
+++ b/configs/mx6slevk_epdc_defconfig
@@ -0,0 +1,97 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SL=y
+CONFIG_TARGET_MX6SLEVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_DM=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_SMSC=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_LCD=y
+CONFIG_MXC_EPDC=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6slevk_optee_defconfig b/configs/mx6slevk_optee_defconfig
new file mode 100644
index 00000000000..779b1a47716
--- /dev/null
+++ b/configs/mx6slevk_optee_defconfig
@@ -0,0 +1,93 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SL=y
+CONFIG_TARGET_MX6SLEVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_IMX_OPTEE=y
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_DM=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_SMSC=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6slevk_plugin_defconfig b/configs/mx6slevk_plugin_defconfig
new file mode 100644
index 00000000000..642543e142a
--- /dev/null
+++ b/configs/mx6slevk_plugin_defconfig
@@ -0,0 +1,93 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SL=y
+CONFIG_TARGET_MX6SLEVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_DM=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_SMSC=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig
index 2bfeac35877..3f8a2ddd3d8 100644
--- a/configs/mx6slevk_spinor_defconfig
+++ b/configs/mx6slevk_spinor_defconfig
@@ -1,27 +1,32 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_SYS_MALLOC_LEN=0x300000
+CONFIG_SYS_MALLOC_LEN=0x1000000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_OFFSET=0xE0000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_MX6SL=y
 CONFIG_TARGET_MX6SLEVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk"
-# CONFIG_CMD_BMODE is not set
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_SPI_BOOT=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
 CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
@@ -37,6 +42,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_DM=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_DM_I2C=y
@@ -69,3 +75,20 @@ CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6sll_lpddr2_val_defconfig b/configs/mx6sll_lpddr2_val_defconfig
new file mode 100644
index 00000000000..2b1f0434b72
--- /dev/null
+++ b/configs/mx6sll_lpddr2_val_defconfig
@@ -0,0 +1,65 @@
+CONFIG_IMX_CONFIG="board/freescale/mx6sll_val/imximage_lpddr2.cfg"
+CONFIG_LPDDR2_BOARD=y
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_MX6SLL_VAL=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SLL=y
+CONFIG_DM_GPIO=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr2-val"
+CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr2-val.dtb"
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
diff --git a/configs/mx6sll_lpddr3_val_defconfig b/configs/mx6sll_lpddr3_val_defconfig
new file mode 100644
index 00000000000..5cad2d77756
--- /dev/null
+++ b/configs/mx6sll_lpddr3_val_defconfig
@@ -0,0 +1,64 @@
+CONFIG_IMX_CONFIG="board/freescale/mx6sll_val/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_MX6SLL_VAL=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SLL=y
+CONFIG_DM_GPIO=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr3-val"
+CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr3-val.dtb"
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
diff --git a/configs/mx6sll_lpddr3_val_epdc_defconfig b/configs/mx6sll_lpddr3_val_epdc_defconfig
new file mode 100644
index 00000000000..497480d9e99
--- /dev/null
+++ b/configs/mx6sll_lpddr3_val_epdc_defconfig
@@ -0,0 +1,69 @@
+CONFIG_IMX_CONFIG="board/freescale/mx6sll_val/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_MX6SLL_VAL=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SLL=y
+CONFIG_DM_GPIO=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_LCD=y
+CONFIG_MXC_EPDC=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr3-val"
+CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr3-val.dtb"
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
diff --git a/configs/mx6sll_lpddr3_val_plugin_defconfig b/configs/mx6sll_lpddr3_val_plugin_defconfig
new file mode 100644
index 00000000000..a88e1e403e6
--- /dev/null
+++ b/configs/mx6sll_lpddr3_val_plugin_defconfig
@@ -0,0 +1,65 @@
+CONFIG_IMX_CONFIG="board/freescale/mx6sll_val/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_MX6SLL_VAL=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SLL=y
+CONFIG_DM_GPIO=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr3-val"
+CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr3-val.dtb"
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
diff --git a/configs/mx6sll_lpddr3_val_spinor_defconfig b/configs/mx6sll_lpddr3_val_spinor_defconfig
new file mode 100644
index 00000000000..4590d781eb4
--- /dev/null
+++ b/configs/mx6sll_lpddr3_val_spinor_defconfig
@@ -0,0 +1,77 @@
+CONFIG_IMX_CONFIG="board/freescale/mx6sll_val/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_MX6SLL_VAL=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SLL=y
+CONFIG_DM_GPIO=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SPI_BOOT=y
+CONFIG_MXC_SPI=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr3-val-ecspi"
+CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr3-val.dtb"
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig
index 48162fc2e58..56e57552233 100644
--- a/configs/mx6sllevk_defconfig
+++ b/configs/mx6sllevk_defconfig
@@ -1,30 +1,37 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SYS_MALLOC_LEN=0x1000000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x88000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_OFFSET=0xE0000
 CONFIG_MX6SLL=y
 CONFIG_TARGET_MX6SLLEVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk"
-# CONFIG_CMD_BMODE is not set
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
@@ -36,6 +43,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
@@ -53,6 +61,33 @@ CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6sllevk_epdc_defconfig b/configs/mx6sllevk_epdc_defconfig
new file mode 100644
index 00000000000..87ace8ad3e3
--- /dev/null
+++ b/configs/mx6sllevk_epdc_defconfig
@@ -0,0 +1,89 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SLL=y
+CONFIG_TARGET_MX6SLLEVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_LCD=y
+CONFIG_MXC_EPDC=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6sllevk_optee_defconfig b/configs/mx6sllevk_optee_defconfig
new file mode 100644
index 00000000000..7978739bf35
--- /dev/null
+++ b/configs/mx6sllevk_optee_defconfig
@@ -0,0 +1,94 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SLL=y
+CONFIG_TARGET_MX6SLLEVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_OPTEE=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig
index 70969438897..602cb48baa2 100644
--- a/configs/mx6sllevk_plugin_defconfig
+++ b/configs/mx6sllevk_plugin_defconfig
@@ -1,31 +1,38 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SYS_MALLOC_LEN=0x1000000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x88000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_OFFSET=0xE0000
 CONFIG_MX6SLL=y
 CONFIG_TARGET_MX6SLLEVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk"
 CONFIG_USE_IMXIMG_PLUGIN=y
-# CONFIG_CMD_BMODE is not set
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
 CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
@@ -37,6 +44,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
@@ -54,6 +62,33 @@ CONFIG_MXC_UART=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
 CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6solosabreauto_defconfig b/configs/mx6solosabreauto_defconfig
new file mode 100644
index 00000000000..bdf51036380
--- /dev/null
+++ b/configs/mx6solosabreauto_defconfig
@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6S=y
+CONFIG_TARGET_MX6SOLOSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/mx6solo.cfg"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6solosabreauto_eimnor_defconfig b/configs/mx6solosabreauto_eimnor_defconfig
new file mode 100644
index 00000000000..dc764a2f1a4
--- /dev/null
+++ b/configs/mx6solosabreauto_eimnor_defconfig
@@ -0,0 +1,99 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6S=y
+CONFIG_TARGET_MX6SOLOSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_ENV_ADDR=0x080E0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/mx6solo.cfg"
+CONFIG_NOR=y
+CONFIG_NOR_BOOT=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto-gpmi-weim"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CMD_FLASH=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6solosabreauto_nand_defconfig b/configs/mx6solosabreauto_nand_defconfig
new file mode 100644
index 00000000000..8f6816c0f7f
--- /dev/null
+++ b/configs/mx6solosabreauto_nand_defconfig
@@ -0,0 +1,105 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6S=y
+CONFIG_TARGET_MX6SOLOSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x3C00000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/mx6solo.cfg"
+CONFIG_NAND_BOOT=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor,nand0=gpmi-nand"
+CONFIG_MTDPARTS_SKIP_INVALID=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto-gpmi-weim"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6solosabreauto_optee_defconfig b/configs/mx6solosabreauto_optee_defconfig
new file mode 100644
index 00000000000..d18fc606d81
--- /dev/null
+++ b/configs/mx6solosabreauto_optee_defconfig
@@ -0,0 +1,99 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6S=y
+CONFIG_TARGET_MX6SOLOSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/mx6solo.cfg"
+CONFIG_IMX_OPTEE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;run findtee;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6solosabreauto_spinor_defconfig b/configs/mx6solosabreauto_spinor_defconfig
new file mode 100644
index 00000000000..4de754b0b6e
--- /dev/null
+++ b/configs/mx6solosabreauto_spinor_defconfig
@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6S=y
+CONFIG_TARGET_MX6SOLOSABREAUTO=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabreauto/mx6solo.cfg"
+CONFIG_SPI_BOOT=y
+CONFIG_CMD_SF=y
+CONFIG_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_MXC_SPI=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto-ecspi"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6solosabresd_defconfig b/configs/mx6solosabresd_defconfig
new file mode 100644
index 00000000000..9b5843a13d0
--- /dev/null
+++ b/configs/mx6solosabresd_defconfig
@@ -0,0 +1,109 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6S=y
+CONFIG_TARGET_MX6SOLOSABRESD=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6solosabresd_optee_defconfig b/configs/mx6solosabresd_optee_defconfig
new file mode 100644
index 00000000000..731e6f28d0f
--- /dev/null
+++ b/configs/mx6solosabresd_optee_defconfig
@@ -0,0 +1,110 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_MX6S=y
+CONFIG_TARGET_MX6SOLOSABRESD=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+# CONFIG_VIDEO_BPP8 is not set
+# CONFIG_VIDEO_BPP32 is not set
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_IPUV3=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_IMX_CONFIG="board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg"
+CONFIG_IMX_OPTEE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;run findtee;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+# CONFIG_OF_LIBFDT=y
+
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd"
+CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12C00000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6sx_14x14_lpddr2_val_defconfig b/configs/mx6sx_14x14_lpddr2_val_defconfig
new file mode 100644
index 00000000000..bea729b6d93
--- /dev/null
+++ b/configs/mx6sx_14x14_lpddr2_val_defconfig
@@ -0,0 +1,81 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SX_14X14_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-14x14-val"
+CONFIG_IMX_CONFIG="board/freescale/mx6sx_17x17_val/mx6sx_14x14_lpddr2_val.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx6sx-14x14-val.dtb"
+CONFIG_LPDDR2_BOARD=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_ETH=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sx_14x14_lpddr2_val_nand_defconfig b/configs/mx6sx_14x14_lpddr2_val_nand_defconfig
new file mode 100644
index 00000000000..04ea9c8bd22
--- /dev/null
+++ b/configs/mx6sx_14x14_lpddr2_val_nand_defconfig
@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x3C00000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SX_14X14_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-14x14-val"
+CONFIG_IMX_CONFIG="board/freescale/mx6sx_17x17_val/mx6sx_14x14_lpddr2_val.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx6sx-14x14-val.dtb"
+CONFIG_LPDDR2_BOARD=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_NAND_BOOT=y
+CONFIG_ENV_IS_IN_NAND=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
+CONFIG_MTDPARTS_SKIP_INVALID=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_DM_ETH=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sx_14x14_lpddr2_val_plugin_defconfig b/configs/mx6sx_14x14_lpddr2_val_plugin_defconfig
new file mode 100644
index 00000000000..f2a56d271e3
--- /dev/null
+++ b/configs/mx6sx_14x14_lpddr2_val_plugin_defconfig
@@ -0,0 +1,82 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SX_14X14_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-14x14-val"
+CONFIG_IMX_CONFIG="board/freescale/mx6sx_17x17_val/mx6sx_14x14_lpddr2_val.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx6sx-14x14-val.dtb"
+CONFIG_LPDDR2_BOARD=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_ETH=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sx_17x17_val_defconfig b/configs/mx6sx_17x17_val_defconfig
new file mode 100644
index 00000000000..8427cc704d1
--- /dev/null
+++ b/configs/mx6sx_17x17_val_defconfig
@@ -0,0 +1,80 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SX_17X17_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val"
+CONFIG_IMX_CONFIG="board/freescale/mx6sx_17x17_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_ETH=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sx_17x17_val_eimnor_defconfig b/configs/mx6sx_17x17_val_eimnor_defconfig
new file mode 100644
index 00000000000..092e73a7c23
--- /dev/null
+++ b/configs/mx6sx_17x17_val_eimnor_defconfig
@@ -0,0 +1,74 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_ENV_ADDR=0x501C0000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SX_17X17_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val"
+CONFIG_IMX_CONFIG="board/freescale/mx6sx_17x17_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb"
+CONFIG_NOR=y
+CONFIG_NOR_BOOT=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_ENV_IS_IN_FLASH=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_DM_ETH=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sx_17x17_val_nand_defconfig b/configs/mx6sx_17x17_val_nand_defconfig
new file mode 100644
index 00000000000..1478027ece1
--- /dev/null
+++ b/configs/mx6sx_17x17_val_nand_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x3C00000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SX_17X17_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val-gpmi-weim"
+CONFIG_IMX_CONFIG="board/freescale/mx6sx_17x17_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_NAND_BOOT=y
+CONFIG_ENV_IS_IN_NAND=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
+CONFIG_MTDPARTS_SKIP_INVALID=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_DM_ETH=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sx_17x17_val_plugin_defconfig b/configs/mx6sx_17x17_val_plugin_defconfig
new file mode 100644
index 00000000000..454aec8da6a
--- /dev/null
+++ b/configs/mx6sx_17x17_val_plugin_defconfig
@@ -0,0 +1,81 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SX_17X17_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val"
+CONFIG_IMX_CONFIG="board/freescale/mx6sx_17x17_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb"
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_ETH=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sx_17x17_val_qspi2_defconfig b/configs/mx6sx_17x17_val_qspi2_defconfig
new file mode 100644
index 00000000000..d614d181b4b
--- /dev/null
+++ b/configs/mx6sx_17x17_val_qspi2_defconfig
@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SX_17X17_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val"
+CONFIG_IMX_CONFIG="board/freescale/mx6sx_17x17_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_ETH=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sx_17x17_val_spinor_defconfig b/configs/mx6sx_17x17_val_spinor_defconfig
new file mode 100644
index 00000000000..3e4ab08a619
--- /dev/null
+++ b/configs/mx6sx_17x17_val_spinor_defconfig
@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SX_17X17_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val-ecspi"
+CONFIG_IMX_CONFIG="board/freescale/mx6sx_17x17_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_ETH=y
+CONFIG_MXC_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sx_17x17wp_val_defconfig b/configs/mx6sx_17x17wp_val_defconfig
new file mode 100644
index 00000000000..c4f9ff3fa8b
--- /dev/null
+++ b/configs/mx6sx_17x17wp_val_defconfig
@@ -0,0 +1,80 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SX_17X17_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val"
+CONFIG_IMX_CONFIG="board/freescale/mx6sx_17x17_val/imximage_wp.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_ETH=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sx_19x19_ddr3_val_defconfig b/configs/mx6sx_19x19_ddr3_val_defconfig
new file mode 100644
index 00000000000..365c4266e97
--- /dev/null
+++ b/configs/mx6sx_19x19_ddr3_val_defconfig
@@ -0,0 +1,79 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SX_19X19_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val"
+CONFIG_IMX_CONFIG="board/freescale/mx6sx_19x19_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_ETH=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sx_19x19_ddr3_val_eimnor_defconfig b/configs/mx6sx_19x19_ddr3_val_eimnor_defconfig
new file mode 100644
index 00000000000..ea6389c6f69
--- /dev/null
+++ b/configs/mx6sx_19x19_ddr3_val_eimnor_defconfig
@@ -0,0 +1,73 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_ENV_ADDR=0x500E0000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SX_19X19_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val"
+CONFIG_IMX_CONFIG="board/freescale/mx6sx_19x19_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb"
+CONFIG_NOR=y
+CONFIG_NOR_BOOT=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_ENV_IS_IN_FLASH=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_DM_ETH=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sx_19x19_ddr3_val_nand_defconfig b/configs/mx6sx_19x19_ddr3_val_nand_defconfig
new file mode 100644
index 00000000000..57b57efbae9
--- /dev/null
+++ b/configs/mx6sx_19x19_ddr3_val_nand_defconfig
@@ -0,0 +1,82 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x3C00000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SX_19X19_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val-gpmi-weim"
+CONFIG_IMX_CONFIG="board/freescale/mx6sx_19x19_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_NAND_BOOT=y
+CONFIG_ENV_IS_IN_NAND=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
+CONFIG_MTDPARTS_SKIP_INVALID=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_DM_ETH=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sx_19x19_ddr3_val_plugin_defconfig b/configs/mx6sx_19x19_ddr3_val_plugin_defconfig
new file mode 100644
index 00000000000..8568c358e69
--- /dev/null
+++ b/configs/mx6sx_19x19_ddr3_val_plugin_defconfig
@@ -0,0 +1,80 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SX_19X19_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val"
+CONFIG_IMX_CONFIG="board/freescale/mx6sx_19x19_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb"
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_ETH=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sx_19x19_ddr3_val_qspi2_defconfig b/configs/mx6sx_19x19_ddr3_val_qspi2_defconfig
new file mode 100644
index 00000000000..cccdbc8d139
--- /dev/null
+++ b/configs/mx6sx_19x19_ddr3_val_qspi2_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SX_19X19_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val"
+CONFIG_IMX_CONFIG="board/freescale/mx6sx_19x19_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_ETH=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sx_19x19_ddr3_val_spinor_defconfig b/configs/mx6sx_19x19_ddr3_val_spinor_defconfig
new file mode 100644
index 00000000000..b3439bc3a77
--- /dev/null
+++ b/configs/mx6sx_19x19_ddr3_val_spinor_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SX_19X19_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val-ecspi"
+CONFIG_IMX_CONFIG="board/freescale/mx6sx_19x19_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=5
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_ETH=y
+CONFIG_MXC_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sx_19x19_lpddr2_val_defconfig b/configs/mx6sx_19x19_lpddr2_val_defconfig
new file mode 100644
index 00000000000..79ae5deebd1
--- /dev/null
+++ b/configs/mx6sx_19x19_lpddr2_val_defconfig
@@ -0,0 +1,80 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SX_19X19_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val"
+CONFIG_IMX_CONFIG="board/freescale/mx6sx_19x19_val/imximage_lpddr2.cfg"
+CONFIG_LPDDR2_BOARD=y
+CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_ETH=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sx_19x19_lpddr2_val_plugin_defconfig b/configs/mx6sx_19x19_lpddr2_val_plugin_defconfig
new file mode 100644
index 00000000000..0e16c6ae682
--- /dev/null
+++ b/configs/mx6sx_19x19_lpddr2_val_plugin_defconfig
@@ -0,0 +1,81 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SX_19X19_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val"
+CONFIG_IMX_CONFIG="board/freescale/mx6sx_19x19_val/imximage_lpddr2.cfg"
+CONFIG_LPDDR2_BOARD=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_ETH=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sx_19x19_lpddr2_val_qspi2_defconfig b/configs/mx6sx_19x19_lpddr2_val_qspi2_defconfig
new file mode 100644
index 00000000000..a515ad66736
--- /dev/null
+++ b/configs/mx6sx_19x19_lpddr2_val_qspi2_defconfig
@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SX_19X19_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val"
+CONFIG_IMX_CONFIG="board/freescale/mx6sx_19x19_val/imximage_lpddr2.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_QSPI_BOOT=y
+CONFIG_LPDDR2_BOARD=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_ETH=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index 6d3895f2d54..3cd1254f8f0 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -1,25 +1,34 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_SYS_MALLOC_LEN=0x300000
+CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x80000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
 CONFIG_MX6SX=y
 CONFIG_TARGET_MX6SXSABREAUTO=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto"
-# CONFIG_CMD_BMODE is not set
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTCOMMAND="run findfdt; mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
@@ -42,16 +51,15 @@ CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
+CONFIG_DM_MTD=y
 CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_MXS=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_FEC_MXC=y
-CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_PMIC=y
@@ -69,3 +77,38 @@ CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+CONFIG_VIDEO_IMX6SX_LVDS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_CMD_BMP=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6sxsabreauto_nand_defconfig b/configs/mx6sxsabreauto_nand_defconfig
new file mode 100644
index 00000000000..0dc30d8475a
--- /dev/null
+++ b/configs/mx6sxsabreauto_nand_defconfig
@@ -0,0 +1,119 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x3C00000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SXSABREAUTO=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_NAND_BOOT=y
+CONFIG_ENV_IS_IN_NAND=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
+CONFIG_MTDPARTS_SKIP_INVALID=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+CONFIG_VIDEO_IMX6SX_LVDS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_CMD_BMP=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6sxsabreauto_optee_defconfig b/configs/mx6sxsabreauto_optee_defconfig
new file mode 100644
index 00000000000..b246eff6d9e
--- /dev/null
+++ b/configs/mx6sxsabreauto_optee_defconfig
@@ -0,0 +1,115 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SXSABREAUTO=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt; mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_IMX_OPTEE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+CONFIG_VIDEO_IMX6SX_LVDS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_CMD_BMP=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6sxsabreauto_plugin_defconfig b/configs/mx6sxsabreauto_plugin_defconfig
new file mode 100644
index 00000000000..8c4a158a7d6
--- /dev/null
+++ b/configs/mx6sxsabreauto_plugin_defconfig
@@ -0,0 +1,115 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SXSABREAUTO=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt; mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+CONFIG_VIDEO_IMX6SX_LVDS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_CMD_BMP=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6sxsabreauto_qspi1_defconfig b/configs/mx6sxsabreauto_qspi1_defconfig
new file mode 100644
index 00000000000..08788275934
--- /dev/null
+++ b/configs/mx6sxsabreauto_qspi1_defconfig
@@ -0,0 +1,119 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SXSABREAUTO=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt; mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_QSPI_BOOT=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+CONFIG_VIDEO_IMX6SX_LVDS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_CMD_BMP=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index 03670c73f8e..7d2a7995e01 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -1,23 +1,28 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x87800000
-CONFIG_SYS_MALLOC_LEN=0x300000
+CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xE0000
 CONFIG_MX6SX=y
 CONFIG_TARGET_MX6SXSABRESD=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb"
-# CONFIG_CMD_BMODE is not set
 CONFIG_NXP_BOARD_REVISION=y
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run findfdt; mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -30,6 +35,7 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -38,7 +44,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_MMC_ENV_DEV=3
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_DM_I2C=y
@@ -50,11 +56,9 @@ CONFIG_SF_DEFAULT_BUS=1
 CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_FEC_MXC=y
-CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_PMIC=y
@@ -72,5 +76,38 @@ CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+CONFIG_VIDEO_IMX6SX_LVDS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_CMD_BMP=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6sxsabresd_emmc_defconfig b/configs/mx6sxsabresd_emmc_defconfig
new file mode 100644
index 00000000000..5b41f86a307
--- /dev/null
+++ b/configs/mx6sxsabresd_emmc_defconfig
@@ -0,0 +1,114 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SXSABRESD=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_NXP_BOARD_REVISION=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb-emmc"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt; mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_MX6SXSABRESD_EMMC_REWORK=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=3
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PCI=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+CONFIG_VIDEO_IMX6SX_LVDS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_CMD_BMP=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6sxsabresd_m4fastup_defconfig b/configs/mx6sxsabresd_m4fastup_defconfig
new file mode 100644
index 00000000000..fbcb9066923
--- /dev/null
+++ b/configs/mx6sxsabresd_m4fastup_defconfig
@@ -0,0 +1,89 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SXSABRESD=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb"
+CONFIG_NXP_BOARD_REVISION=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt; mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_CONFIG=¡°board/freescale/mx6sxsabresd/imximage.cfg,SYS_AUXCORE_FASTUP"
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=3
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PCI=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+CONFIG_VIDEO_IMX6SX_LVDS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_CMD_BMP=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_IMX_BOOTAUX=y
diff --git a/configs/mx6sxsabresd_optee_defconfig b/configs/mx6sxsabresd_optee_defconfig
new file mode 100644
index 00000000000..572ab0cebbf
--- /dev/null
+++ b/configs/mx6sxsabresd_optee_defconfig
@@ -0,0 +1,114 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SXSABRESD=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb"
+CONFIG_NXP_BOARD_REVISION=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt; mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+CONFIG_IMX_OPTEE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=3
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PCI=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+CONFIG_VIDEO_IMX6SX_LVDS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_CMD_BMP=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6sxsabresd_plugin_defconfig b/configs/mx6sxsabresd_plugin_defconfig
new file mode 100644
index 00000000000..c7ae5c7e4cb
--- /dev/null
+++ b/configs/mx6sxsabresd_plugin_defconfig
@@ -0,0 +1,114 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SXSABRESD=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb"
+CONFIG_NXP_BOARD_REVISION=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt; mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=3
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PCI=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+CONFIG_VIDEO_IMX6SX_LVDS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_CMD_BMP=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6sxsabresd_qspi2_defconfig b/configs/mx6sxsabresd_qspi2_defconfig
new file mode 100644
index 00000000000..a5e1fcedb47
--- /dev/null
+++ b/configs/mx6sxsabresd_qspi2_defconfig
@@ -0,0 +1,118 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6SX=y
+CONFIG_TARGET_MX6SXSABRESD=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb"
+CONFIG_NXP_BOARD_REVISION=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt; mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=3
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PCI=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_BMP_16BPP=y
+CONFIG_VIDEO_IMX6SX_LVDS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_CMD_BMP=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_IMX_BOOTAUX=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6ul_14x14_ddr3_val_defconfig b/configs/mx6ul_14x14_ddr3_val_defconfig
new file mode 100644
index 00000000000..ad0cc2698e9
--- /dev/null
+++ b/configs/mx6ul_14x14_ddr3_val_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6UL=y
+CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val"
+CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_CONFIG="board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx6ul_14x14_ddr3_val_eimnor_defconfig b/configs/mx6ul_14x14_ddr3_val_eimnor_defconfig
new file mode 100644
index 00000000000..a75a381f8a9
--- /dev/null
+++ b/configs/mx6ul_14x14_ddr3_val_eimnor_defconfig
@@ -0,0 +1,66 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_ENV_ADDR=0x501C0000
+CONFIG_MX6UL=y
+CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val"
+CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_CONFIG="board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg"
+CONFIG_NOR=y
+CONFIG_NOR_BOOT=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_MMC=n
diff --git a/configs/mx6ul_14x14_ddr3_val_emmc_defconfig b/configs/mx6ul_14x14_ddr3_val_emmc_defconfig
new file mode 100644
index 00000000000..0d68ad1298b
--- /dev/null
+++ b/configs/mx6ul_14x14_ddr3_val_emmc_defconfig
@@ -0,0 +1,69 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6UL=y
+CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val-emmc"
+CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_CONFIG="board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg"
+CONFIG_MX6UL_DDR3_VAL_EMMC_REWORK=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx6ul_14x14_ddr3_val_nand_defconfig b/configs/mx6ul_14x14_ddr3_val_nand_defconfig
new file mode 100644
index 00000000000..8f1483cd05a
--- /dev/null
+++ b/configs/mx6ul_14x14_ddr3_val_nand_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x3c00000
+CONFIG_MX6UL=y
+CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val-gpmi-weim"
+CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_IMX_CONFIG="board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg"
+CONFIG_NAND_BOOT=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx6ul_14x14_ddr3_val_plugin_defconfig b/configs/mx6ul_14x14_ddr3_val_plugin_defconfig
new file mode 100644
index 00000000000..fdd8315a679
--- /dev/null
+++ b/configs/mx6ul_14x14_ddr3_val_plugin_defconfig
@@ -0,0 +1,78 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6UL=y
+CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val"
+CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_CONFIG="board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg"
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx6ul_14x14_ddr3_val_qspi1_defconfig b/configs/mx6ul_14x14_ddr3_val_qspi1_defconfig
new file mode 100644
index 00000000000..15c0e6e3b10
--- /dev/null
+++ b/configs/mx6ul_14x14_ddr3_val_qspi1_defconfig
@@ -0,0 +1,79 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6UL=y
+CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val"
+CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_CONFIG="board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg"
+CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx6ul_14x14_ddr3_val_spinor_defconfig b/configs/mx6ul_14x14_ddr3_val_spinor_defconfig
new file mode 100644
index 00000000000..a82bed66e20
--- /dev/null
+++ b/configs/mx6ul_14x14_ddr3_val_spinor_defconfig
@@ -0,0 +1,80 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6UL=y
+CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val"
+CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_CONFIG="board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg"
+CONFIG_SPI_BOOT=y
+CONFIG_MXC_SPI=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index 70a40acffe2..1aa455f1200 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -1,44 +1,33 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x88000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_OFFSET=0xE0000
 CONFIG_MX6UL=y
 CONFIG_TARGET_MX6UL_14X14_EVK=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk"
-CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_CONFIG="board/freescale/mx6ul_14x14_evk/imximage.cfg"
+CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_FS_EXT4=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_USB_HOST=y
-CONFIG_SPL_USB_GADGET=y
-CONFIG_SPL_USB_SDP_SUPPORT=y
-CONFIG_SPL_WATCHDOG=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_SDP=y
 CONFIG_CMD_USB_MASS_STORAGE=y
@@ -46,6 +35,7 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -58,10 +48,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_BOUNCE_BUFFER=y
-CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_DM_74X164=y
 CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
@@ -88,11 +76,8 @@ CONFIG_SOFT_SPI=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="FSL"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
-CONFIG_CI_UDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_LOGO=y
 CONFIG_SYS_WHITE_ON_BLACK=y
@@ -100,3 +85,19 @@ CONFIG_VIDEO_MXS=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6ul_14x14_evk_emmc_defconfig b/configs/mx6ul_14x14_evk_emmc_defconfig
new file mode 100644
index 00000000000..19baa475e09
--- /dev/null
+++ b/configs/mx6ul_14x14_evk_emmc_defconfig
@@ -0,0 +1,103 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6UL=y
+CONFIG_TARGET_MX6UL_14X14_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk-emmc"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_CONFIG="board/freescale/mx6ul_14x14_evk/imximage.cfg"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6ul_14x14_evk_nand_defconfig b/configs/mx6ul_14x14_evk_nand_defconfig
new file mode 100644
index 00000000000..7b99e89be6f
--- /dev/null
+++ b/configs/mx6ul_14x14_evk_nand_defconfig
@@ -0,0 +1,107 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x3c00000
+CONFIG_MX6UL=y
+CONFIG_TARGET_MX6UL_14X14_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk-gpmi-weim"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_IMX_CONFIG="board/freescale/mx6ul_14x14_evk/imximage.cfg"
+CONFIG_NAND_BOOT=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6ul_14x14_evk_optee_defconfig b/configs/mx6ul_14x14_evk_optee_defconfig
new file mode 100644
index 00000000000..885f25e7b26
--- /dev/null
+++ b/configs/mx6ul_14x14_evk_optee_defconfig
@@ -0,0 +1,104 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6UL=y
+CONFIG_TARGET_MX6UL_14X14_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;run findtee;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_CONFIG="board/freescale/mx6ul_14x14_evk/imximage.cfg"
+CONFIG_IMX_OPTEE=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6ul_14x14_evk_plugin_defconfig b/configs/mx6ul_14x14_evk_plugin_defconfig
new file mode 100644
index 00000000000..6555f224b39
--- /dev/null
+++ b/configs/mx6ul_14x14_evk_plugin_defconfig
@@ -0,0 +1,104 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6UL=y
+CONFIG_TARGET_MX6UL_14X14_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_CONFIG="board/freescale/mx6ul_14x14_evk/imximage.cfg"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6ul_14x14_evk_qspi1_defconfig b/configs/mx6ul_14x14_evk_qspi1_defconfig
new file mode 100644
index 00000000000..608bd156f3a
--- /dev/null
+++ b/configs/mx6ul_14x14_evk_qspi1_defconfig
@@ -0,0 +1,106 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6UL=y
+CONFIG_TARGET_MX6UL_14X14_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_CONFIG="board/freescale/mx6ul_14x14_evk/imximage.cfg"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_QSPI_BOOT=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6ul_14x14_evk_spl_defconfig b/configs/mx6ul_14x14_evk_spl_defconfig
new file mode 100644
index 00000000000..dfc1bc2fd4c
--- /dev/null
+++ b/configs/mx6ul_14x14_evk_spl_defconfig
@@ -0,0 +1,102 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xC0000
+CONFIG_MX6UL=y
+CONFIG_TARGET_MX6UL_14X14_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk"
+CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_FS_EXT4=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_USB_HOST=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
diff --git a/configs/mx6ul_14x14_lpddr2_val_defconfig b/configs/mx6ul_14x14_lpddr2_val_defconfig
new file mode 100644
index 00000000000..6a80b0e6d40
--- /dev/null
+++ b/configs/mx6ul_14x14_lpddr2_val_defconfig
@@ -0,0 +1,68 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6UL=y
+CONFIG_TARGET_MX6UL_14X14_LPDDR2_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-lpddr2-val"
+CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-lpddr2-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_CONFIG="board/freescale/mx6ul_14x14_lpddr2_val/imximage.cfg"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx6ul_14x14_lpddr2_val_eimnor_defconfig b/configs/mx6ul_14x14_lpddr2_val_eimnor_defconfig
new file mode 100644
index 00000000000..22b88418ca6
--- /dev/null
+++ b/configs/mx6ul_14x14_lpddr2_val_eimnor_defconfig
@@ -0,0 +1,69 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_ENV_ADDR=0x501C0000
+CONFIG_MX6UL=y
+CONFIG_TARGET_MX6UL_14X14_LPDDR2_VAL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-lpddr2-val"
+CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-lpddr2-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_CONFIG="board/freescale/mx6ul_14x14_lpddr2_val/imximage.cfg"
+CONFIG_NOR=y
+CONFIG_NOR_BOOT=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_SYS_FLASH_PROTECTION=y
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index a121e966037..7afd4456946 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -1,46 +1,40 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SPL_GPIO=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x88000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x80000
+CONFIG_ENV_OFFSET=0xE0000
 CONFIG_MX6UL=y
 CONFIG_TARGET_MX6UL_9X9_EVK=y
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk"
-CONFIG_SPL_TEXT_BASE=0x00908000
-CONFIG_SPL_MMC=y
-CONFIG_SPL_SERIAL=y
-CONFIG_SPL=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_CONFIG="board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg"
+CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_SPL_FS_EXT4=y
-CONFIG_SPL_I2C=y
-CONFIG_SPL_WATCHDOG=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -53,8 +47,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
 CONFIG_DM_I2C=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
@@ -66,6 +60,7 @@ CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
 CONFIG_DM_ETH=y
 CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
@@ -83,6 +78,8 @@ CONFIG_SOFT_SPI=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_LOGO=y
 CONFIG_SYS_WHITE_ON_BLACK=y
@@ -90,3 +87,19 @@ CONFIG_VIDEO_MXS=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6ul_9x9_evk_optee_defconfig b/configs/mx6ul_9x9_evk_optee_defconfig
new file mode 100644
index 00000000000..bfb3cb6c75c
--- /dev/null
+++ b/configs/mx6ul_9x9_evk_optee_defconfig
@@ -0,0 +1,106 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6UL=y
+CONFIG_TARGET_MX6UL_9X9_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;run findtee;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_CONFIG="board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg"
+CONFIG_IMX_OPTEE=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6ul_9x9_evk_plugin_defconfig b/configs/mx6ul_9x9_evk_plugin_defconfig
new file mode 100644
index 00000000000..3ca556a36fc
--- /dev/null
+++ b/configs/mx6ul_9x9_evk_plugin_defconfig
@@ -0,0 +1,106 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6UL=y
+CONFIG_TARGET_MX6UL_9X9_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_CONFIG="board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6ul_9x9_evk_qspi1_defconfig b/configs/mx6ul_9x9_evk_qspi1_defconfig
new file mode 100644
index 00000000000..55f5efb4650
--- /dev/null
+++ b/configs/mx6ul_9x9_evk_qspi1_defconfig
@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6UL=y
+CONFIG_TARGET_MX6UL_9X9_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_CONFIG="board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_QSPI_BOOT=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx6ul_9x9_evk_spl_defconfig b/configs/mx6ul_9x9_evk_spl_defconfig
new file mode 100644
index 00000000000..a121e966037
--- /dev/null
+++ b/configs/mx6ul_9x9_evk_spl_defconfig
@@ -0,0 +1,92 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x80000
+CONFIG_MX6UL=y
+CONFIG_TARGET_MX6UL_9X9_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk"
+CONFIG_SPL_TEXT_BASE=0x00908000
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_FS_EXT4=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
diff --git a/configs/mx6ull_14x14_ddr3_val_defconfig b/configs/mx6ull_14x14_ddr3_val_defconfig
new file mode 100644
index 00000000000..18879920ac9
--- /dev/null
+++ b/configs/mx6ull_14x14_ddr3_val_defconfig
@@ -0,0 +1,77 @@
+CONFIG_IMX_CONFIG="board/freescale/mx6ull_ddr3_val/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_MX6ULL_DDR3_VAL=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6ULL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val"
+CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx6ull_14x14_ddr3_val_emmc_defconfig b/configs/mx6ull_14x14_ddr3_val_emmc_defconfig
new file mode 100644
index 00000000000..c7f75c035a7
--- /dev/null
+++ b/configs/mx6ull_14x14_ddr3_val_emmc_defconfig
@@ -0,0 +1,69 @@
+CONFIG_IMX_CONFIG="board/freescale/mx6ull_ddr3_val/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_MX6ULL_DDR3_VAL=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6ULL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val-emmc"
+CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb"
+CONFIG_MX6ULL_DDR3_VAL_EMMC_REWORK=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx6ull_14x14_ddr3_val_epdc_defconfig b/configs/mx6ull_14x14_ddr3_val_epdc_defconfig
new file mode 100644
index 00000000000..ac06caeffe8
--- /dev/null
+++ b/configs/mx6ull_14x14_ddr3_val_epdc_defconfig
@@ -0,0 +1,81 @@
+CONFIG_IMX_CONFIG="board/freescale/mx6ull_ddr3_val/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_MX6ULL_DDR3_VAL=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6ULL=y
+CONFIG_DM_GPIO=y
+CONFIG_LCD=y
+CONFIG_MXC_EPDC=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val-epdc"
+CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx6ull_14x14_ddr3_val_nand_defconfig b/configs/mx6ull_14x14_ddr3_val_nand_defconfig
new file mode 100644
index 00000000000..2ccdd61e4a1
--- /dev/null
+++ b/configs/mx6ull_14x14_ddr3_val_nand_defconfig
@@ -0,0 +1,77 @@
+CONFIG_IMX_CONFIG="board/freescale/mx6ull_ddr3_val/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_MX6ULL_DDR3_VAL=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x3c00000
+CONFIG_MX6ULL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val-gpmi-weim"
+CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_NAND_BOOT=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx6ull_14x14_ddr3_val_plugin_defconfig b/configs/mx6ull_14x14_ddr3_val_plugin_defconfig
new file mode 100644
index 00000000000..77a643e5603
--- /dev/null
+++ b/configs/mx6ull_14x14_ddr3_val_plugin_defconfig
@@ -0,0 +1,78 @@
+CONFIG_IMX_CONFIG="board/freescale/mx6ull_ddr3_val/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_MX6ULL_DDR3_VAL=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6ULL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val"
+CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb"
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx6ull_14x14_ddr3_val_qspi1_defconfig b/configs/mx6ull_14x14_ddr3_val_qspi1_defconfig
new file mode 100644
index 00000000000..e04d76179a3
--- /dev/null
+++ b/configs/mx6ull_14x14_ddr3_val_qspi1_defconfig
@@ -0,0 +1,79 @@
+CONFIG_IMX_CONFIG="board/freescale/mx6ull_ddr3_val/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_MX6ULL_DDR3_VAL=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6ULL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val"
+CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx6ull_14x14_ddr3_val_spinor_defconfig b/configs/mx6ull_14x14_ddr3_val_spinor_defconfig
new file mode 100644
index 00000000000..36eb1576599
--- /dev/null
+++ b/configs/mx6ull_14x14_ddr3_val_spinor_defconfig
@@ -0,0 +1,80 @@
+CONFIG_IMX_CONFIG="board/freescale/mx6ull_ddr3_val/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_MX6ULL_DDR3_VAL=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6ULL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val"
+CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_SPI_BOOT=y
+CONFIG_MXC_SPI=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx6ull_14x14_ddr3_val_tsc_defconfig b/configs/mx6ull_14x14_ddr3_val_tsc_defconfig
new file mode 100644
index 00000000000..5b266463cfa
--- /dev/null
+++ b/configs/mx6ull_14x14_ddr3_val_tsc_defconfig
@@ -0,0 +1,78 @@
+CONFIG_IMX_CONFIG="board/freescale/mx6ull_ddr3_val/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_TARGET_MX6ULL_DDR3_VAL=y
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6ULL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val-tsc"
+CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb"
+CONFIG_MX6ULL_DDR3_VAL_TSC_REWORK=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=0
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig
index a053d2f7610..79964b3ccf5 100644
--- a/configs/mx6ull_14x14_evk_defconfig
+++ b/configs/mx6ull_14x14_evk_defconfig
@@ -1,29 +1,38 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SYS_MALLOC_LEN=0x1000000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x88000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_OFFSET=0xE0000
 CONFIG_MX6ULL=y
 CONFIG_TARGET_MX6ULL_14X14_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk"
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -62,3 +71,35 @@ CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_SOFT_SPI=y
 CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_14x14_evk_emmc_defconfig b/configs/mx6ull_14x14_evk_emmc_defconfig
new file mode 100644
index 00000000000..f4bcc40544f
--- /dev/null
+++ b/configs/mx6ull_14x14_evk_emmc_defconfig
@@ -0,0 +1,105 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6ULL=y
+CONFIG_TARGET_MX6ULL_14X14_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk-emmc"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_14x14_evk_nand_defconfig b/configs/mx6ull_14x14_evk_nand_defconfig
new file mode 100644
index 00000000000..1931293bc64
--- /dev/null
+++ b/configs/mx6ull_14x14_evk_nand_defconfig
@@ -0,0 +1,112 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x3c00000
+CONFIG_MX6ULL=y
+CONFIG_TARGET_MX6ULL_14X14_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk-gpmi-weim"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_NAND_BOOT=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
+CONFIG_MTDPARTS_SKIP_INVALID=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_14x14_evk_optee_defconfig b/configs/mx6ull_14x14_evk_optee_defconfig
new file mode 100644
index 00000000000..ba1c8e02a43
--- /dev/null
+++ b/configs/mx6ull_14x14_evk_optee_defconfig
@@ -0,0 +1,106 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6ULL=y
+CONFIG_TARGET_MX6ULL_14X14_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;run findtee;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_IMX_OPTEE=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig
index 07e5e235757..9c1354981eb 100644
--- a/configs/mx6ull_14x14_evk_plugin_defconfig
+++ b/configs/mx6ull_14x14_evk_plugin_defconfig
@@ -1,30 +1,39 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SYS_MALLOC_LEN=0x1000000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x88000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_OFFSET=0xE0000
 CONFIG_MX6ULL=y
 CONFIG_TARGET_MX6ULL_14X14_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk"
 CONFIG_USE_IMXIMG_PLUGIN=y
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -55,9 +64,43 @@ CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_SOFT_SPI=y
 CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_14x14_evk_qspi1_defconfig b/configs/mx6ull_14x14_evk_qspi1_defconfig
new file mode 100644
index 00000000000..13a1eec75e3
--- /dev/null
+++ b/configs/mx6ull_14x14_evk_qspi1_defconfig
@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6ULL=y
+CONFIG_TARGET_MX6ULL_14X14_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_QSPI_BOOT=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_9x9_evk_defconfig b/configs/mx6ull_9x9_evk_defconfig
new file mode 100644
index 00000000000..3f73c5e6978
--- /dev/null
+++ b/configs/mx6ull_9x9_evk_defconfig
@@ -0,0 +1,110 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6ULL=y
+CONFIG_TARGET_MX6ULL_9X9_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-9x9-evk"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_IMX_CONFIG="board/freescale/mx6ullevk/imximage_lpddr2.cfg"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_9x9_evk_plugin_defconfig b/configs/mx6ull_9x9_evk_plugin_defconfig
new file mode 100644
index 00000000000..41468f2d384
--- /dev/null
+++ b/configs/mx6ull_9x9_evk_plugin_defconfig
@@ -0,0 +1,110 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6ULL=y
+CONFIG_TARGET_MX6ULL_9X9_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-9x9-evk"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_IMX_CONFIG="board/freescale/mx6ullevk/imximage_lpddr2.cfg"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ull_9x9_evk_qspi1_defconfig b/configs/mx6ull_9x9_evk_qspi1_defconfig
new file mode 100644
index 00000000000..f1446ef8e03
--- /dev/null
+++ b/configs/mx6ull_9x9_evk_qspi1_defconfig
@@ -0,0 +1,112 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6ULL=y
+CONFIG_TARGET_MX6ULL_9X9_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ull-9x9-evk"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_IMX_CONFIG="board/freescale/mx6ullevk/imximage_lpddr2.cfg"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_QSPI_BOOT=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ8XXX=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_DM_RNG=y
+CONFIG_CMD_RNG=y
+CONFIG_FSL_DCP_RNG=y
diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig
index 2f9c7a2b595..438af0a0657 100644
--- a/configs/mx6ulz_14x14_evk_defconfig
+++ b/configs/mx6ulz_14x14_evk_defconfig
@@ -1,27 +1,38 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
-CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SYS_MALLOC_LEN=0x1000000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x88000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_OFFSET=0xE0000
 CONFIG_MX6ULL=y
 CONFIG_TARGET_MX6ULL_14X14_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk"
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
@@ -33,22 +44,47 @@ CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-# CONFIG_NET is not set
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_DM_74X164=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC_IMX=y
+CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_SOFT_SPI=y
 CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
\ No newline at end of file
diff --git a/configs/mx6ulz_14x14_evk_emmc_defconfig b/configs/mx6ulz_14x14_evk_emmc_defconfig
new file mode 100644
index 00000000000..7595c54ee86
--- /dev/null
+++ b/configs/mx6ulz_14x14_evk_emmc_defconfig
@@ -0,0 +1,90 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6ULL=y
+CONFIG_TARGET_MX6ULL_14X14_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk-emmc"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
\ No newline at end of file
diff --git a/configs/mx6ulz_14x14_evk_nand_defconfig b/configs/mx6ulz_14x14_evk_nand_defconfig
new file mode 100644
index 00000000000..6526b172001
--- /dev/null
+++ b/configs/mx6ulz_14x14_evk_nand_defconfig
@@ -0,0 +1,94 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x3c00000
+CONFIG_MX6ULL=y
+CONFIG_TARGET_MX6ULL_14X14_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk-gpmi-weim"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_NAND_BOOT=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
\ No newline at end of file
diff --git a/configs/mx6ulz_14x14_evk_optee_defconfig b/configs/mx6ulz_14x14_evk_optee_defconfig
new file mode 100644
index 00000000000..ebb71c06848
--- /dev/null
+++ b/configs/mx6ulz_14x14_evk_optee_defconfig
@@ -0,0 +1,91 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_MX6ULL=y
+CONFIG_TARGET_MX6ULL_14X14_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;run findtee;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_IMX_OPTEE=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
\ No newline at end of file
diff --git a/configs/mx6ulz_14x14_evk_qspi1_defconfig b/configs/mx6ulz_14x14_evk_qspi1_defconfig
new file mode 100644
index 00000000000..d6af77381fb
--- /dev/null
+++ b/configs/mx6ulz_14x14_evk_qspi1_defconfig
@@ -0,0 +1,93 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_MALLOC_LEN=0x1000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0x88000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_MX6ULL=y
+CONFIG_TARGET_MX6ULL_14X14_EVK=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk"
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_QSPI_BOOT=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_PHYLIB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx7d_12x12_ddr3_val_defconfig b/configs/mx7d_12x12_ddr3_val_defconfig
new file mode 100644
index 00000000000..c37b5239c11
--- /dev/null
+++ b/configs/mx7d_12x12_ddr3_val_defconfig
@@ -0,0 +1,81 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7D_12X12_DDR3_VAL=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-ddr3-val"
+CONFIG_IMX_CONFIG="board/freescale/mx7d_12x12_ddr3_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-ddr3-val.dtb"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/mx7d_12x12_lpddr3_val_defconfig b/configs/mx7d_12x12_lpddr3_val_defconfig
new file mode 100644
index 00000000000..92e621aff38
--- /dev/null
+++ b/configs/mx7d_12x12_lpddr3_val_defconfig
@@ -0,0 +1,85 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7D_12X12_LPDDR3_VAL=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-val"
+CONFIG_IMX_CONFIG="board/freescale/mx7d_12x12_lpddr3_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-val.dtb"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_ERRNO_STR=y
+CONFIG_DM_ETH=y
diff --git a/configs/mx7d_12x12_lpddr3_val_epdc_defconfig b/configs/mx7d_12x12_lpddr3_val_epdc_defconfig
new file mode 100644
index 00000000000..2b1232167f1
--- /dev/null
+++ b/configs/mx7d_12x12_lpddr3_val_epdc_defconfig
@@ -0,0 +1,87 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7D_12X12_LPDDR3_VAL=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-val"
+CONFIG_IMX_CONFIG="board/freescale/mx7d_12x12_lpddr3_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-val.dtb"
+CONFIG_LCD=y
+CONFIG_MXC_EPDC=y
+CONFIG_CMD_BMP=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_ERRNO_STR=y
+CONFIG_DM_ETH=y
diff --git a/configs/mx7d_12x12_lpddr3_val_optee_defconfig b/configs/mx7d_12x12_lpddr3_val_optee_defconfig
new file mode 100644
index 00000000000..a1e02aad1cb
--- /dev/null
+++ b/configs/mx7d_12x12_lpddr3_val_optee_defconfig
@@ -0,0 +1,86 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7D_12X12_LPDDR3_VAL=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-val"
+CONFIG_IMX_CONFIG="board/freescale/mx7d_12x12_lpddr3_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-val.dtb"
+CONFIG_BOOTDELAY=3
+CONFIG_IMX_OPTEE=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_ERRNO_STR=y
+CONFIG_DM_ETH=y
diff --git a/configs/mx7d_12x12_lpddr3_val_qspi1_defconfig b/configs/mx7d_12x12_lpddr3_val_qspi1_defconfig
new file mode 100644
index 00000000000..915394213ec
--- /dev/null
+++ b/configs/mx7d_12x12_lpddr3_val_qspi1_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7D_12X12_LPDDR3_VAL=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-val-qspi"
+CONFIG_IMX_CONFIG="board/freescale/mx7d_12x12_lpddr3_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-val.dtb"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_FSL_QSPI=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_ERRNO_STR=y
+CONFIG_QSPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_DM_ETH=y
diff --git a/configs/mx7d_12x12_lpddr3_val_spinor_defconfig b/configs/mx7d_12x12_lpddr3_val_spinor_defconfig
new file mode 100644
index 00000000000..2a95569fae6
--- /dev/null
+++ b/configs/mx7d_12x12_lpddr3_val_spinor_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7D_12X12_LPDDR3_VAL=y
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-val-ecspi"
+CONFIG_IMX_CONFIG="board/freescale/mx7d_12x12_lpddr3_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-val.dtb"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_MXC_SPI=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_ERRNO_STR=y
+CONFIG_DM_ETH=y
+CONFIG_SPI_BOOT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+# CONFIG_ENV_IS_IN_MMC is not set
diff --git a/configs/mx7d_19x19_ddr3_val_defconfig b/configs/mx7d_19x19_ddr3_val_defconfig
new file mode 100644
index 00000000000..72ba4818273
--- /dev/null
+++ b/configs/mx7d_19x19_ddr3_val_defconfig
@@ -0,0 +1,95 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7D_19X19_DDR3_VAL=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-19x19-ddr3-val"
+CONFIG_IMX_CONFIG="board/freescale/mx7d_19x19_ddr3_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx7d-19x19-ddr3-val.dtb"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_FSL_QSPI=y
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/mx7d_19x19_lpddr2_val_defconfig b/configs/mx7d_19x19_lpddr2_val_defconfig
new file mode 100644
index 00000000000..05ac6be96ef
--- /dev/null
+++ b/configs/mx7d_19x19_lpddr2_val_defconfig
@@ -0,0 +1,82 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7D_19X19_LPDDR2_VAL=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-19x19-lpddr2-val"
+CONFIG_IMX_CONFIG="board/freescale/mx7d_19x19_lpddr3_val/imximage_lpddr2.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx7d-19x19-lpddr2-val.dtb"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_ERRNO_STR=y
diff --git a/configs/mx7d_19x19_lpddr3_val_defconfig b/configs/mx7d_19x19_lpddr3_val_defconfig
new file mode 100644
index 00000000000..b1e0cfd0b2a
--- /dev/null
+++ b/configs/mx7d_19x19_lpddr3_val_defconfig
@@ -0,0 +1,84 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7D_19X19_LPDDR3_VAL=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-19x19-lpddr3-val"
+CONFIG_IMX_CONFIG="board/freescale/mx7d_19x19_lpddr3_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx7d-19x19-lpddr3-val.dtb"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_ERRNO_STR=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_CMD_FLASH=y
diff --git a/configs/mx7d_19x19_lpddr3_val_eimnor_defconfig b/configs/mx7d_19x19_lpddr3_val_eimnor_defconfig
new file mode 100644
index 00000000000..2de216f5ac6
--- /dev/null
+++ b/configs/mx7d_19x19_lpddr3_val_eimnor_defconfig
@@ -0,0 +1,89 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_ENV_ADDR=0x281C0000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7D_19X19_LPDDR3_VAL=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-19x19-lpddr3-val"
+CONFIG_IMX_CONFIG="board/freescale/mx7d_19x19_lpddr3_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx7d-19x19-lpddr3-val.dtb"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_ERRNO_STR=y
+CONFIG_NOR=y
+CONFIG_NOR_BOOT=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_ENV_IS_IN_FLASH=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_CMD_FLASH=y
diff --git a/configs/mx7d_19x19_lpddr3_val_nand_defconfig b/configs/mx7d_19x19_lpddr3_val_nand_defconfig
new file mode 100644
index 00000000000..737f6b98490
--- /dev/null
+++ b/configs/mx7d_19x19_lpddr3_val_nand_defconfig
@@ -0,0 +1,97 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x3C00000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7D_19X19_LPDDR3_VAL=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-19x19-lpddr3-val"
+CONFIG_IMX_CONFIG="board/freescale/mx7d_19x19_lpddr3_val/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx7d-19x19-lpddr3-val.dtb"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_ERRNO_STR=y
+CONFIG_NAND_BOOT=y
+CONFIG_ENV_IS_IN_NAND=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
+CONFIG_MTDPARTS_SKIP_INVALID=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_UBI=y
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index af387626443..4b7eaae3c4a 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -5,22 +5,25 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0xa0000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_OFFSET=0xE0000
 CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb"
 CONFIG_TARGET_MX7DSABRESD=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
 # CONFIG_ARMV7_VIRT is not set
 CONFIG_IMX_RDC=y
 CONFIG_IMX_BOOTAUX=y
-CONFIG_IMX_HAB=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_CMD_BOOTD is not set
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_BOOTM_NETBSD is not set
 # CONFIG_BOOTM_PLAN9 is not set
 # CONFIG_BOOTM_RTEMS is not set
-# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
@@ -29,18 +32,24 @@ CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_BOUNCE_BUFFER=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_DM_74X164=y
@@ -54,8 +63,7 @@ CONFIG_FSL_USDHC=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_DM_ETH=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_FEC_MXC=y
 CONFIG_RGMII=y
 CONFIG_MII=y
@@ -77,12 +85,27 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_VENDOR_NUM=0x1FC9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
 CONFIG_ERRNO_STR=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_epdc_defconfig
index b896ce7a7f4..b5143516409 100644
--- a/configs/mx7dsabresd_qspi_defconfig
+++ b/configs/mx7dsabresd_epdc_defconfig
@@ -5,21 +5,27 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0xa0000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_OFFSET=0xE0000
 CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-qspi"
 CONFIG_TARGET_MX7DSABRESD=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
 # CONFIG_ARMV7_VIRT is not set
 CONFIG_IMX_RDC=y
 CONFIG_IMX_BOOTAUX=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_MXC_EPDC=y
+CONFIG_LCD=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-# CONFIG_CMD_BOOTD is not set
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 # CONFIG_BOOTM_NETBSD is not set
 # CONFIG_BOOTM_PLAN9 is not set
 # CONFIG_BOOTM_RTEMS is not set
-# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_EXPORTENV is not set
 # CONFIG_CMD_IMPORTENV is not set
@@ -28,18 +34,24 @@ CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
-# CONFIG_ISO_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
+CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-epdc"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_BOUNCE_BUFFER=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_DM_74X164=y
@@ -50,16 +62,10 @@ CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS200_SUPPORT=y
 CONFIG_FSL_USDHC=y
-CONFIG_MTD=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=40000000
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_BROADCOM=y
 CONFIG_DM_ETH=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_FEC_MXC=y
 CONFIG_RGMII=y
 CONFIG_MII=y
@@ -74,7 +80,6 @@ CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
-CONFIG_FSL_QSPI=y
 CONFIG_SOFT_SPI=y
 CONFIG_IMX_THERMAL=y
 CONFIG_USB=y
@@ -82,12 +87,22 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_MXC_USB_OTG_HACTIVE=y
 CONFIG_USB_HOST_ETHER=y
 CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_SPLASH_SCREEN=y
 CONFIG_SPLASH_SCREEN_ALIGN=y
 CONFIG_ERRNO_STR=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx7dsabresd_nand_defconfig b/configs/mx7dsabresd_nand_defconfig
new file mode 100644
index 00000000000..788c7e712c4
--- /dev/null
+++ b/configs/mx7dsabresd_nand_defconfig
@@ -0,0 +1,119 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x3C00000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7DSABRESD=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_NAND_BOOT=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_UBI=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
+CONFIG_MTDPARTS_SKIP_INVALID=y
+CONFIG_NAND=y
+CONFIG_NAND_MXS=y
+CONFIG_NAND_MXS_DT=y
+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_ENV_IS_IN_NAND=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-gpmi-weim"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_ERRNO_STR=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx7dsabresd_optee_defconfig b/configs/mx7dsabresd_optee_defconfig
new file mode 100644
index 00000000000..b12448cb648
--- /dev/null
+++ b/configs/mx7dsabresd_optee_defconfig
@@ -0,0 +1,112 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7DSABRESD=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_IMX_OPTEE=y
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+CONFIG_ERRNO_STR=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx7dsabresd_plugin_defconfig b/configs/mx7dsabresd_plugin_defconfig
new file mode 100644
index 00000000000..79c73ccbdd1
--- /dev/null
+++ b/configs/mx7dsabresd_plugin_defconfig
@@ -0,0 +1,112 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7DSABRESD=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+CONFIG_ERRNO_STR=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx7dsabresd_qspi1_defconfig b/configs/mx7dsabresd_qspi1_defconfig
new file mode 100644
index 00000000000..19834cade3a
--- /dev/null
+++ b/configs/mx7dsabresd_qspi1_defconfig
@@ -0,0 +1,123 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7DSABRESD=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_QSPI_BOOT=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+# CONFIG_ENV_IS_IN_MMC is not set
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-qspi"
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+CONFIG_ERRNO_STR=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx7dsabresd_reva_defconfig b/configs/mx7dsabresd_reva_defconfig
new file mode 100644
index 00000000000..964dee9a0ad
--- /dev/null
+++ b/configs/mx7dsabresd_reva_defconfig
@@ -0,0 +1,111 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7DSABRESD=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-reva"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+CONFIG_ERRNO_STR=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx7dsabresd_revb_defconfig b/configs/mx7dsabresd_revb_defconfig
new file mode 100644
index 00000000000..9cf04f3f60e
--- /dev/null
+++ b/configs/mx7dsabresd_revb_defconfig
@@ -0,0 +1,112 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xa0000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7DSABRESD=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+# CONFIG_ARMV7_VIRT is not set
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_IMX_CONFIG="board/freescale/mx7dsabresd/imximage_TO_1_1.cfg"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
+CONFIG_BOOTDELAY=3
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DM_74X164=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_BROADCOM=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_MXS=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_BMP_16BPP=y
+CONFIG_ERRNO_STR=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
diff --git a/configs/mx7ulp_10x10_val_defconfig b/configs/mx7ulp_10x10_val_defconfig
new file mode 100644
index 00000000000..609e595d399
--- /dev/null
+++ b/configs/mx7ulp_10x10_val_defconfig
@@ -0,0 +1,82 @@
+CONFIG_IMX_CONFIG="board/freescale/mx7ulp_val/imximage_lpddr2.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX7ULP=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+CONFIG_SYS_TEXT_BASE=0x67800000
+CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x9E000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7ULP_10X10_VAL=y
+CONFIG_SYS_LOAD_ADDR=0x60800000
+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-10x10-val"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi"
+CONFIG_DEFAULT_FDT_FILE="imx7ulp-10x10-val.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_IMX_RGPIO2P=y
+# CONFIG_MXC_GPIO is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_CMD_SF=y
+CONFIG_FSL_QSPI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_ULP_WATCHDOG=y
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
diff --git a/configs/mx7ulp_14x14_val_defconfig b/configs/mx7ulp_14x14_val_defconfig
new file mode 100644
index 00000000000..255edc3f2bf
--- /dev/null
+++ b/configs/mx7ulp_14x14_val_defconfig
@@ -0,0 +1,82 @@
+CONFIG_IMX_CONFIG="board/freescale/mx7ulp_val/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX7ULP=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+CONFIG_SYS_TEXT_BASE=0x67800000
+CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x7E000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7ULP_14X14_VAL=y
+CONFIG_SYS_LOAD_ADDR=0x60800000
+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-14x14-val"
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi"
+CONFIG_DEFAULT_FDT_FILE="imx7ulp-14x14-val.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_IMX_RGPIO2P=y
+# CONFIG_MXC_GPIO is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_CMD_SF=y
+CONFIG_FSL_QSPI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_ULP_WATCHDOG=y
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
diff --git a/configs/mx7ulp_com_defconfig b/configs/mx7ulp_com_defconfig
index 2f860f61fda..05241d7dcd1 100644
--- a/configs/mx7ulp_com_defconfig
+++ b/configs/mx7ulp_com_defconfig
@@ -53,8 +53,8 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="FSL"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_ULP_WATCHDOG=y
diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig
index 4f641471acb..a21c1100852 100644
--- a/configs/mx7ulp_evk_defconfig
+++ b/configs/mx7ulp_evk_defconfig
@@ -1,19 +1,22 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX7ULP=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
 CONFIG_SYS_TEXT_BASE=0x67800000
 CONFIG_SYS_MALLOC_LEN=0x800000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_MEMTEST_START=0x60000000
-CONFIG_SYS_MEMTEST_END=0x9e000000
+CONFIG_SYS_MEMTEST_END=0x80000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_OFFSET=0xE0000
 CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
 CONFIG_TARGET_MX7ULP_EVK=y
 CONFIG_SYS_LOAD_ADDR=0x60800000
+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi"
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi"
+CONFIG_DEFAULT_FDT_FILE="imx7ulp-evkb"
+CONFIG_BOARD_LATE_INIT=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
@@ -24,11 +27,12 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
 CONFIG_DM=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_IMX_RGPIO2P=y
@@ -45,3 +49,60 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
+CONFIG_CMD_SF=y
+CONFIG_FSL_QSPI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FSL_LPSPI=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_ULP_WATCHDOG=y
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x60800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_NW_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_DM=y
diff --git a/configs/mx7ulp_evk_emmc_defconfig b/configs/mx7ulp_evk_emmc_defconfig
new file mode 100644
index 00000000000..7d7c12b3643
--- /dev/null
+++ b/configs/mx7ulp_evk_emmc_defconfig
@@ -0,0 +1,107 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7ULP=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+CONFIG_SYS_TEXT_BASE=0x67800000
+CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7ULP_EVK=y
+CONFIG_SYS_LOAD_ADDR=0x60800000
+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-emmc"
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi"
+CONFIG_DEFAULT_FDT_FILE="imx7ulp-evkb-emmc"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_IMX_RGPIO2P=y
+# CONFIG_MXC_GPIO is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_CMD_SF=y
+CONFIG_FSL_QSPI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_ULP_WATCHDOG=y
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x60800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_NW_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_DM=y
diff --git a/configs/mx7ulp_evk_m4boot_defconfig b/configs/mx7ulp_evk_m4boot_defconfig
new file mode 100644
index 00000000000..46ee29e2029
--- /dev/null
+++ b/configs/mx7ulp_evk_m4boot_defconfig
@@ -0,0 +1,107 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7ULP=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+CONFIG_SYS_TEXT_BASE=0x67800000
+CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7ULP_EVK=y
+CONFIG_SYS_LOAD_ADDR=0x60800000
+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi"
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi"
+CONFIG_DEFAULT_FDT_FILE="imx7ulp-evkb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_IMX_RGPIO2P=y
+# CONFIG_MXC_GPIO is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_CMD_SF=y
+CONFIG_FSL_QSPI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_ULP_WATCHDOG=y
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+CONFIG_IMX_M4_BIND=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x60800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_NW_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_DM=y
diff --git a/configs/mx7ulp_evk_optee_defconfig b/configs/mx7ulp_evk_optee_defconfig
new file mode 100644
index 00000000000..0b914a6f7e5
--- /dev/null
+++ b/configs/mx7ulp_evk_optee_defconfig
@@ -0,0 +1,108 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7ULP=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+CONFIG_SYS_TEXT_BASE=0x67800000
+CONFIG_SYS_MALLOC_LEN=0x800000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_MEMTEST_START=0x60000000
+CONFIG_SYS_MEMTEST_END=0x80000000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xE0000
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_MX7ULP_EVK=y
+CONFIG_SYS_LOAD_ADDR=0x60800000
+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi"
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi"
+CONFIG_DEFAULT_FDT_FILE="imx7ulp-evkb"
+CONFIG_IMX_OPTEE=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_IMX_RGPIO2P=y
+# CONFIG_MXC_GPIO is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_CMD_SF=y
+CONFIG_FSL_QSPI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_ULP_WATCHDOG=y
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x60800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_NW_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_DM=y
diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig
index 0f8e9e886ed..f90b2e5d09c 100644
--- a/configs/mx7ulp_evk_plugin_defconfig
+++ b/configs/mx7ulp_evk_plugin_defconfig
@@ -1,20 +1,25 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX7ULP=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
 CONFIG_SYS_TEXT_BASE=0x67800000
 CONFIG_SYS_MALLOC_LEN=0x800000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_MEMTEST_START=0x60000000
-CONFIG_SYS_MEMTEST_END=0x9e000000
+CONFIG_SYS_MEMTEST_END=0x80000000
 CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
+CONFIG_ENV_OFFSET=0xE0000
 CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
 CONFIG_TARGET_MX7ULP_EVK=y
 CONFIG_SYS_LOAD_ADDR=0x60800000
+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi"
+CONFIG_USE_IMXIMG_PLUGIN=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; fi; fi; fi"
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; fi"
+CONFIG_DEFAULT_FDT_FILE="imx7ulp-evkb"
+CONFIG_BOARD_LATE_INIT=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
@@ -22,11 +27,12 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
 CONFIG_DM=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_IMX_RGPIO2P=y
@@ -43,3 +49,59 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
+CONFIG_CMD_SF=y
+CONFIG_FSL_QSPI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SF_DEFAULT_BUS=0
+CONFIG_SF_DEFAULT_CS=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_ULP_WATCHDOG=y
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_DM_ETH=y
+
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
+CONFIG_CI_UDC=y
+
+CONFIG_CMD_FASTBOOT=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x60800000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_EFI_PARTITION=y
+
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_VIDEO_IMX_NW_DSI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BMP_16BPP=y
+CONFIG_BMP_24BPP=y
+CONFIG_BMP_32BPP=y
+CONFIG_VIDEO_MXS=y
+CONFIG_VIDEO_LOGO=y
+CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_DM=y
diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig
index 5f5caceb8d4..e6a5870cd46 100644
--- a/configs/opos6uldev_defconfig
+++ b/configs/opos6uldev_defconfig
@@ -100,8 +100,8 @@ CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Armadeus Systems"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0525
-CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_DM_VIDEO=y
diff --git a/disk/part_efi.c b/disk/part_efi.c
index f1f3e5bceff..e1d9dced033 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -151,6 +151,25 @@ static int validate_gpt_header(gpt_header *gpt_h, lbaint_t lba,
 	return 0;
 }
 
+static void prepare_last_lba_gpt_header(struct blk_desc *dev_desc, gpt_header *gpt_h)
+{
+	uint32_t calc_crc32;
+	uint64_t val;
+
+	/* recalculate the values for the Backup GPT Header */
+	val = le64_to_cpu(gpt_h->my_lba);
+	gpt_h->my_lba = cpu_to_le64(dev_desc->lba - 1);;
+	gpt_h->alternate_lba = cpu_to_le64(val);
+	gpt_h->last_usable_lba = cpu_to_le64(dev_desc->lba - 34);
+	gpt_h->partition_entry_lba =
+			cpu_to_le64(le64_to_cpu(gpt_h->last_usable_lba) + 1);
+	gpt_h->header_crc32 = 0;
+
+	calc_crc32 = efi_crc32((const unsigned char *)gpt_h,
+			       le32_to_cpu(gpt_h->header_size));
+	gpt_h->header_crc32 = cpu_to_le32(calc_crc32);
+}
+
 static int validate_gpt_entries(gpt_header *gpt_h, gpt_entry *gpt_e)
 {
 	uint32_t calc_crc32;
@@ -161,7 +180,7 @@ static int validate_gpt_entries(gpt_header *gpt_h, gpt_entry *gpt_e)
 		le32_to_cpu(gpt_h->sizeof_partition_entry));
 
 	if (calc_crc32 != le32_to_cpu(gpt_h->partition_entry_array_crc32)) {
-		printf("%s: 0x%x != 0x%x\n",
+		debug("%s: 0x%x != 0x%x\n",
 		       "GUID Partition Table Entry Array CRC is wrong",
 		       le32_to_cpu(gpt_h->partition_entry_array_crc32),
 		       calc_crc32);
@@ -253,8 +272,10 @@ void part_print_efi(struct blk_desc *dev_desc)
 		printf("\tguid:\t%pUl\n", uuid);
 	}
 
+#if !(defined(CONFIG_DUAL_BOOTLOADER) || defined(CONFIG_IMX_TRUSTY_OS)) || !defined(CONFIG_SPL_BUILD)
 	/* Remember to free pte */
 	free(gpt_pte);
+#endif
 	return;
 }
 
@@ -278,7 +299,9 @@ int part_get_info_efi(struct blk_desc *dev_desc, int part,
 	    !is_pte_valid(&gpt_pte[part - 1])) {
 		debug("%s: *** ERROR: Invalid partition number %d ***\n",
 			__func__, part);
+#if !(defined(CONFIG_DUAL_BOOTLOADER) || defined(CONFIG_IMX_TRUSTY_OS)) || !defined(CONFIG_SPL_BUILD)
 		free(gpt_pte);
+#endif
 		return -1;
 	}
 
@@ -305,11 +328,73 @@ int part_get_info_efi(struct blk_desc *dev_desc, int part,
 	debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s\n", __func__,
 	      info->start, info->size, info->name);
 
-	/* Remember to free pte */
+#if !(defined(CONFIG_DUAL_BOOTLOADER) || defined(CONFIG_IMX_TRUSTY_OS)) || !defined(CONFIG_SPL_BUILD)
+	/* Heap memory is very limited in SPL, if the dual bootloader is
+	 * enabled, just load pte to dram instead of oc-ram. In such case,
+	 * this part of  memory shouldn't be freed. But in common routine,
+	 * don't forget to free the memory after use.
+	 */
 	free(gpt_pte);
+#endif
 	return 0;
 }
 
+#if (defined(CONFIG_DUAL_BOOTLOADER) || defined(CONFIG_IMX_TRUSTY_OS)) && defined(CONFIG_SPL_BUILD)
+int part_get_info_efi_by_name(struct blk_desc *dev_desc, const char *name,
+		      struct disk_partition *info)
+{
+	ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz);
+	/* We don't free gpt_pte because the memory is allocated at
+	 * CONFIG_SYS_SPL_PTE_RAM_BASE due to the limited memory at
+	 * SPL stage.
+	 */
+	gpt_entry *gpt_pte = NULL;
+	int i = 0;
+
+	if (name == NULL) {
+		printf("%s: Invalid Argument(s)\n", __func__);
+		return -1;
+	}
+
+	/* This function validates AND fills in the GPT header and PTE */
+	if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1)
+		return -1;
+
+	/* Search PTE to find matched partition. */
+	for (i = 0; i < le32_to_cpu(gpt_head->num_partition_entries); i++) {
+		if (is_pte_valid(&gpt_pte[i]) &&
+			strcmp(name, print_efiname(&gpt_pte[i])) == 0) {
+			/* Matched partition found, copy it. */
+			/* The 'lbaint_t' casting may limit the maximum disk size to 2 TB */
+			info->start = (lbaint_t)le64_to_cpu(gpt_pte[i].starting_lba);
+			/* The ending LBA is inclusive, to calculate size, add 1 to it */
+			info->size = (lbaint_t)le64_to_cpu(gpt_pte[i].ending_lba) + 1
+				     - info->start;
+			info->blksz = dev_desc->blksz;
+
+			snprintf((char *)info->name, sizeof(info->name), "%s", name);
+			strcpy((char *)info->type, "U-Boot");
+			info->bootable = get_bootable(&gpt_pte[i]);
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
+			uuid_bin_to_str(gpt_pte[i].unique_partition_guid.b, info->uuid,
+					UUID_STR_FORMAT_GUID);
+#endif
+#ifdef CONFIG_PARTITION_TYPE_GUID
+			uuid_bin_to_str(gpt_pte[i].partition_type_guid.b,
+					info->type_guid, UUID_STR_FORMAT_GUID);
+#endif
+
+			debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s\n", __func__,
+			      info->start, info->size, info->name);
+
+			return i;
+		}
+	}
+
+	return -1;
+}
+#endif /* (CONFIG_DUAL_BOOTLOADER || CONFIG_IMX_TRUSTY_OS) && CONFIG_SPL_BUILD */
+
 static int part_test_efi(struct blk_desc *dev_desc)
 {
 	ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, legacymbr, 1, dev_desc->blksz);
@@ -876,6 +961,58 @@ int write_mbr_and_gpt_partitions(struct blk_desc *dev_desc, void *buf)
 
 	return 0;
 }
+int write_backup_gpt_partitions(struct blk_desc *dev_desc, void *buf)
+{
+	gpt_header *gpt_h;
+	gpt_entry *gpt_e;
+	int gpt_e_blk_cnt;
+	lbaint_t lba;
+	int cnt;
+
+	if (is_valid_gpt_buf(dev_desc, buf))
+		return -1;
+
+	/* determine start of GPT Header in the buffer */
+	gpt_h = buf + (GPT_PRIMARY_PARTITION_TABLE_LBA *
+		       dev_desc->blksz);
+
+	/* determine start of GPT Entries in the buffer */
+	gpt_e = buf + (le64_to_cpu(gpt_h->partition_entry_lba) *
+		       dev_desc->blksz);
+	gpt_e_blk_cnt = BLOCK_CNT((le32_to_cpu(gpt_h->num_partition_entries) *
+				   le32_to_cpu(gpt_h->sizeof_partition_entry)),
+				  dev_desc);
+
+	/* write MBR */
+	lba = 0;	/* MBR is always at 0 */
+	cnt = 1;	/* MBR (1 block) */
+	if (blk_dwrite(dev_desc, lba, cnt, buf) != cnt) {
+		printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
+		       __func__, "MBR", cnt, lba);
+		return 1;
+	}
+
+	prepare_last_lba_gpt_header(dev_desc, gpt_h);
+
+	/* write Backup GPT */
+	lba = le64_to_cpu(gpt_h->partition_entry_lba);
+	cnt = gpt_e_blk_cnt;
+	if (blk_dwrite(dev_desc, lba, cnt, gpt_e) != cnt) {
+		printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
+		       __func__, "Backup GPT Entries", cnt, lba);
+		return 1;
+	}
+
+	lba = le64_to_cpu(gpt_h->my_lba);
+	cnt = 1;	/* GPT Header (1 block) */
+	if (blk_dwrite(dev_desc, lba, cnt, gpt_h) != cnt) {
+		printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
+		       __func__, "Backup GPT Header", cnt, lba);
+		return 1;
+	}
+
+	return 0;
+}
 #endif
 
 /*
@@ -1008,7 +1145,7 @@ static int find_valid_gpt(struct blk_desc *dev_desc, gpt_header *gpt_head,
 
 	if (r != 1) {
 		if (r != 2)
-			printf("%s: *** ERROR: Invalid GPT ***\n", __func__);
+			debug("%s: *** ERROR: Invalid GPT ***\n", __func__);
 
 		if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), gpt_head,
 				 pgpt_pte) != 1) {
@@ -1017,7 +1154,7 @@ static int find_valid_gpt(struct blk_desc *dev_desc, gpt_header *gpt_head,
 			return 0;
 		}
 		if (r != 2)
-			printf("%s: ***        Using Backup GPT ***\n",
+			debug("%s: ***        Using Backup GPT ***\n",
 			       __func__);
 	}
 	return 1;
@@ -1052,10 +1189,19 @@ static gpt_entry *alloc_read_gpt_entries(struct blk_desc *dev_desc,
 	      (u32) le32_to_cpu(pgpt_head->sizeof_partition_entry),
 	      (ulong)count);
 
-	/* Allocate memory for PTE, remember to FREE */
+	/* Allocate memory for PTE.
+	 * Heap memory is very limited in SPL, if the dual bootloader is
+	 * enabled, just load pte to dram instead of oc-ram. In such case,
+	 * this part of  memory shouldn't be freed. But in common routine,
+	 * don't forget to free the memory after use.
+	 */
 	if (count != 0) {
+#if (defined(CONFIG_DUAL_BOOTLOADER) || defined(CONFIG_IMX_TRUSTY_OS)) && defined(CONFIG_SPL_BUILD)
+		pte = (gpt_entry *)CONFIG_SYS_SPL_PTE_RAM_BASE;
+#else
 		pte = memalign(ARCH_DMA_MINALIGN,
 			       PAD_TO_BLOCKSIZE(count, dev_desc));
+#endif
 	}
 
 	if (count == 0 || pte == NULL) {
@@ -1069,7 +1215,9 @@ static gpt_entry *alloc_read_gpt_entries(struct blk_desc *dev_desc,
 	blk_cnt = BLOCK_CNT(count, dev_desc);
 	if (blk_dread(dev_desc, blk, (lbaint_t)blk_cnt, pte) != blk_cnt) {
 		printf("*** ERROR: Can't read GPT Entries ***\n");
+#if !(defined(CONFIG_DUAL_BOOTLOADER) || defined(CONFIG_IMX_TRUSTY_OS)) || !defined(CONFIG_SPL_BUILD)
 		free(pte);
+#endif
 		return NULL;
 	}
 	return pte;
diff --git a/doc/device-tree-bindings/usb/cdns-usb3.txt b/doc/device-tree-bindings/usb/cdns-usb3.txt
new file mode 100644
index 00000000000..8aba13b88ad
--- /dev/null
+++ b/doc/device-tree-bindings/usb/cdns-usb3.txt
@@ -0,0 +1,53 @@
+* Cadence USB3 Controller
+
+Required properties:
+- compatible: should contain: "cdns,usb3-1.0.0"
+- reg: physical base address and size of the controller's register areas
+	Controller has 5 different regions:
+	region 1 - NONE-CORE registers area
+	region 2 - HOST registers area
+	region 3 - DEVICE registers area
+	region 4 - PHY registers area
+	region 5 - OTG registers area
+- reg-names - register memory area names:
+	"none-core" - for NONE-CORE registers space
+	"xhci" - for HOST registers space
+	"dev" - for DEVICE registers space
+	"phy" - for PHY registers space
+	"otg" - for OTG registers space
+- interrupts: interrupts used by cdns3 controller
+- interrupt-parent: the interrupt parent for this module
+- clocks: reference to the USB clock
+- clock-names: the name of clocks
+- phys: reference to the USB PHY
+
+Optional properties:
+- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
+- extcon: extcon phandler for cdns3 device
+- power-domains: the power domain for cdns3 controller and phy
+
+Examples:
+
+usbotg3: cdns3@5b110000 {
+	compatible = "cdns,usb3-1.0.0";
+	reg = <0x0 0x5B110000 0x0 0x10000>,
+		<0x0 0x5B130000 0x0 0x10000>,
+		<0x0 0x5B140000 0x0 0x10000>,
+		<0x0 0x5B160000 0x0 0x40000>,
+		<0x0 0x5B120000 0x0 0x10000>;
+	reg-names = "none-core", "xhci", "dev", "phy", "otg";
+	interrupt-parent = <&gic>;
+	interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&clk IMX8QM_USB3_LPM_CLK>,
+		<&clk IMX8QM_USB3_BUS_CLK>,
+		<&clk IMX8QM_USB3_ACLK>,
+		<&clk IMX8QM_USB3_IPG_CLK>,
+		<&clk IMX8QM_USB3_CORE_PCLK>;
+	clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk",
+		"usb3_ipg_clk", "usb3_core_pclk";
+	power-domains = <&pd_conn_usb2>;
+	phys = <&usbphy1>;
+	dr_mode = "otg";
+	extcon = <&typec_ptn5150>;
+	status = "disabled";
+};
diff --git a/doc/imx/ahab/csf_examples/csf_boot_image.txt b/doc/imx/ahab/csf_examples/csf_boot_image.txt
new file mode 100644
index 00000000000..1f296f09007
--- /dev/null
+++ b/doc/imx/ahab/csf_examples/csf_boot_image.txt
@@ -0,0 +1,21 @@
+[Header]
+Target = AHAB
+Version = 1.0
+
+[Install SRK]
+# SRK table generated by srktool
+File = "./release/crts/SRK_1_2_3_4_table.bin"
+# Public key certificate in PEM format
+Source = "./release/crts/SRK1_sha384_secp384r1_v3_usr_crt.pem"
+# Index of the public key certificate within the SRK table (0 .. 3)
+Source index = 0
+# Type of SRK set (NXP or OEM)
+Source set = OEM
+# bitmask of the revoked SRKs
+Revocations = 0x0
+
+[Authenticate Data]
+# Binary to be signed generated by mkimage
+File = "flash.bin"
+# Offsets = Container header  Signature block (printed out by mkimage)
+Offsets   = 0x400             0x590
diff --git a/doc/imx/ahab/csf_examples/csf_boot_image_sgk.txt b/doc/imx/ahab/csf_examples/csf_boot_image_sgk.txt
new file mode 100644
index 00000000000..ec42f4f09ea
--- /dev/null
+++ b/doc/imx/ahab/csf_examples/csf_boot_image_sgk.txt
@@ -0,0 +1,28 @@
+[Header]
+Target = AHAB
+Version = 1.0
+
+[Install SRK]
+# SRK table generated by srktool
+File = "./release/crts/SRK_1_2_3_4_table.bin"
+# Public key certificate in PEM format
+Source = "./release/crts/SRK1_sha384_secp384r1_v3_ca_crt.pem"
+# Index of the public key certificate within the SRK table (0 .. 3)
+Source index = 0
+# Type of SRK set (NXP or OEM)
+Source set = OEM
+# bitmask of the revoked SRKs
+Revocations = 0x0
+
+# Optional subordinate SGK key
+[Install Certificate]
+# Public key certificate in PEM format
+File = "./release/crts/SGK1_sha384_secp384r1_v3_usr_crt.pem"
+# bitmask of the permissions
+Permissions = 0x1
+
+[Authenticate Data]
+# Binary to be signed generated by mkimage
+File = "flash.bin"
+# Offsets = Container header  Signature block (printed out by mkimage)
+Offsets   = 0x400             0x590
diff --git a/doc/imx/ahab/csf_examples/csf_linux_img.txt b/doc/imx/ahab/csf_examples/csf_linux_img.txt
new file mode 100644
index 00000000000..b5aa5238023
--- /dev/null
+++ b/doc/imx/ahab/csf_examples/csf_linux_img.txt
@@ -0,0 +1,21 @@
+[Header]
+Target = AHAB
+Version = 1.0
+
+[Install SRK]
+# SRK table generated by srktool
+File = "./release/crts/SRK_1_2_3_4_table.bin"
+# Public key certificate in PEM format
+Source = "./release/crts/SRK1_sha384_secp384r1_v3_usr_crt.pem"
+# Index of the public key certificate within the SRK table (0 .. 3)
+Source index = 0
+# Type of SRK set (NXP or OEM)
+Source set = OEM
+# bitmask of the revoked SRKs
+Revocations = 0x0
+
+[Authenticate Data]
+# Binary to be signed generated by mkimage
+File = "flash_os.bin"
+# Offsets = Container header  Signature block (printed out by mkimage)
+Offsets   = 0x0             0x110
diff --git a/doc/imx/ahab/csf_examples/csf_uboot_atf.txt b/doc/imx/ahab/csf_examples/csf_uboot_atf.txt
new file mode 100644
index 00000000000..c4d23bcce4b
--- /dev/null
+++ b/doc/imx/ahab/csf_examples/csf_uboot_atf.txt
@@ -0,0 +1,21 @@
+[Header]
+Target = AHAB
+Version = 1.0
+
+[Install SRK]
+# SRK table generated by srktool
+File = "../crts/SRK_1_2_3_4_table.bin"
+# Public key certificate in PEM format on this example only using SRK key
+Source = "../crts/SRK1_sha384_secp384r1_v3_usr_crt.pem"
+# Index of the public key certificate within the SRK table (0 .. 3)
+Source index = 0
+# Type of SRK set (NXP or OEM)
+Source set = OEM
+# bitmask of the revoked SRKs
+Revocations = 0x0
+
+[Authenticate Data]
+# Binary to be signed generated by mkimage
+File = "u-boot-atf-container.img"
+# Offsets = Container header  Signature block (printed out by mkimage)
+Offsets   = 0x0             0x110
diff --git a/doc/imx/ahab/guides/mx8_mx8x_encrypted_boot.txt b/doc/imx/ahab/guides/mx8_mx8x_encrypted_boot.txt
index dfea4c8277c..23a78a1b529 100644
--- a/doc/imx/ahab/guides/mx8_mx8x_encrypted_boot.txt
+++ b/doc/imx/ahab/guides/mx8_mx8x_encrypted_boot.txt
@@ -290,4 +290,4 @@ os_cntr_signed.bin.
   $ sudo cp enc_flash_os.bin /media/UserID/Boot\ imx8/os_cntr_signed.bin
 
 References:
-[1] SCFW API guide: "System Controller Firmware API Reference Guide - Rev 1.5"
+[1] SCFW API guide: "System Controller Firmware API Reference Guide"
diff --git a/doc/imx/ahab/guides/mx8_mx8x_secure_boot.txt b/doc/imx/ahab/guides/mx8_mx8x_secure_boot.txt
new file mode 100644
index 00000000000..37f2c2a251c
--- /dev/null
+++ b/doc/imx/ahab/guides/mx8_mx8x_secure_boot.txt
@@ -0,0 +1,314 @@
+     +=========================================================+
+     +       i.MX 8, i.MX 8X Secure Boot guide using AHAB      +
+     +=========================================================+
+
+1. AHAB secure boot process
+----------------------------
+
+This document describes a step-by-step procedure on how to sign and
+securely boot a flash.bin image. It is assumed that the reader is
+familiar with basic AHAB concepts and with the PKI tree generation.
+
+It is also assumed that the reader is familiar with all pieces of software
+needed. The procedure to build SCFW, ATF and download the firmwares are out of
+scope of this document, please refer to the Linux BSP Release Notes and
+AN12212[1] for further details.
+
+Details about AHAB can be found in the introduction_ahab.txt document
+and in processors Security Reference Manual Document (SRM).
+
+1.1 Preparing the environment to build a secure boot image
+-----------------------------------------------------------
+
+Before continuing, be sure to have already downloaded and built the
+following:
+
+- imx-mkimage downloaded and built with i.MX 8 container support.
+- SECO firmware downloaded.
+- U-Boot downloaded and built. Please check section 1.2.
+- ARM Trusted Firmware (ATF) downloaded and built for your target.
+- System Controller Firmware (SCFW).
+- Kernel image.
+
+You should also have downloaded the Code Signing Tool, available on NXP
+website.
+
+In the following sections, <work> designates the repository where all
+parts have been downloaded and built.
+
+1.2 Preparing U-Boot to support AHAB secure boot features
+----------------------------------------------------------
+
+The U-Boot provides extra functions for AHAB, such as the ability to
+authenticate additional container images by calling the SCU API
+sc_misc_seco_authenticate() function.
+
+The support is enabled by adding CONFIG_AHAB_BOOT to the defconfig file used
+for your target:
+
+  - Defconfig:
+    CONFIG_AHAB_BOOT=y
+  - Kconfig:
+    ARM architecture -> Support i.MX 8 AHAB features
+
+1.3 Building an image supporting secure boot
+---------------------------------------------
+
+The boot image is composed of different layers:
+
+             +---------------------------+ <-- *start
+             |   1st Container header    |
+             |       and signature       |
+             +---------------------------+
+             | Padding for 1kB alignment |
+             +---------------------------+ <-- *start + 0x400
+             |   2nd Container header    |
+             |       and signature       |
+             +---------------------------+
+             |          Padding          |
+             +---------------------------+
+             |          SECO FW          |
+             +---------------------------+
+             |          Padding          |
+             +---------------------------+
+             |      SCU FW with DDR      |
+             |   initialization Image    |
+             |         embedded          |
+             +---------------------------+
+             |      Cortex-M4 Image      |
+             +---------------------------+
+             |    Cortex-A bootloader    |
+             +---------------------------+
+
+It contains two containers, one for the SECO firmware (AHAB), and one for
+the SCFW, the ATF, U-Boot and M4 Image. They are preceded by their headers.
+The first one, containing the SECO firmware image, is padded to 0x1000 to
+fix the start address of the second one, which can contain one or multiple
+images.
+
+If you are familiar with secure boot process with HABv4, you will notice
+there is no need for CSF in this architecture. The CST is responsible to
+handle the Signature block:
+
+             +----------------------------+  ^
+             |                            |  |
+             |                            |  |
+             |      Container header      |  |
+             |                            |  |
+             |                            |  |
+             +---+------------------------+  |
+             | S | Signature block header |  | Signed
+             | i +------------------------+  |
+             | g |                        |  |
+             | n |                        |  |
+             | a |        SRK table       |  |
+             | t |                        |  |
+             | u |                        |  |
+             | r +------------------------+  v
+             | e |       Signature        |
+             |   +------------------------+
+             | b |                        |
+             | l |        SGK Key         |
+             | o | Certificate (optional) |
+             | c |                        |
+             | k |                        |
+             +---+------------------------+
+
+The certificate block is divided into:
+
+                    +---------------+ ^
+                    |  Public key   | | Signed
+                    |  Permission   | |
+                    +---------------+ v
+                    |   Signature   |
+                    +---------------+
+
+The first block (public key permission) verify the Signature block
+preceding (between SRK table and Certificate blocks), while the second
+block (signature) is verified by the SRK table block.
+
+1.4 Prepare the boot image layout
+----------------------------------
+
+To generate the flash.bin file:
+
+- On i.MX 8 QXP:
+
+  $ cd <work>/imx-mkimage
+  $ make SOC=iMX8QX flash
+
+- On i.MX 8 QM:
+
+  $ cd <work>/imx-mkimage
+  $ make SOC=iMX8QM flash
+
+If the command ends successfully, the end of the result should look
+like:
+
+  CST: CONTAINER 0 offset: 0x400
+  CST: CONTAINER 0: Signature Block: offset is at 0x590
+  DONE.
+  Note: Please copy image to offset: IVT_OFFSET + IMAGE_OFFSET
+
+Keep in mind the offsets above to be used with CST/CSF.
+
+Please note that on this example we not including an Cortex-M4 Image, on
+i.MX8/8x MEK boards the SCU console may be replaced by the M4 console not
+being possible to run the steps documented in section "1.5.5 Verify SECO
+events".
+
+1.5 Secure boot setup with the CST
+-----------------------------------
+
+1.5.1 Creating the CSF description file for the second container
+-----------------------------------------------------------------
+
+The CSF contains all the commands that the AHAB executes during the secure
+boot. These commands instruct the AHAB on which memory areas of the image
+to authenticate, which keys to install, use and etc.
+
+CSF examples are available under doc/imx/hab/ahab/csf_examples/
+directory.
+
+This csf_boot_image.txt file example should be updated with the offset values
+of the 1.4 section and the path to your flash.bin file. It is the last part
+of the file:
+
+  [Authenticate Data]
+  # Binary to be signed generated by mkimage
+  File = "flash.bin"
+  # Offsets = Container header  Signature block (printed out by mkimage)
+  Offsets   = 0x400             0x590
+
+1.5.2 Signing the boot image
+-----------------------------
+
+Now you use the CST to generate the signed boot image from the previously
+created csf_boot_image.txt Commands Sequence File:
+
+  $ cd <work>
+  $ ./release/linux64/bin/cst -i csf_boot_image.txt -o flash.signed.bin
+
+1.5.3 Flash the signed image
+-----------------------------
+
+Write the signed U-Boot image:
+
+  $ sudo dd if=flash.signed.bin of=/dev/sdX bs=1k seek=32 ; sync
+
+Then insert the SD Card into the board and plug your device to your computer
+with an USB serial cable.
+
+1.5.4 Programming SRK Hash
+---------------------------
+
+As explained in introduction_ahab.txt document the SRK Hash fuse values are
+generated by the srktool and should be programmed in the SoC SRK_HASH[511:0]
+fuses.
+
+Be careful when programming these values, as this data is the basis for the
+root of trust. An error in SRK Hash results in a part that does not boot.
+
+The U-Boot fuse tool can be used for programming eFuses on i.MX SoCs.
+
+- Dump SRK Hash fuses values in host machine:
+
+  $ od -t x4 SRK_1_2_3_4_fuse.bin
+  0000000 d436cc46 8ecccda9 b89e1601 5fada3db
+  0000020 d454114a b6cd51f4 77384870 c50ee4b2
+  0000040 a27e5132 eba887cf 592c1e2b bb501799
+  0000060 ee702e07 cf8ce73e fb55e2d5 eba6bbd2
+
+- Program SRK_HASH[511:0] fuses:
+
+  * On i.MX 8 QXP:
+
+  => fuse prog 0 730 0xd436cc46
+  => fuse prog 0 731 0x8ecccda9
+  => fuse prog 0 732 0xb89e1601
+  => fuse prog 0 733 0x5fada3db
+  => fuse prog 0 734 0xd454114a
+  => fuse prog 0 735 0xb6cd51f4
+  => fuse prog 0 736 0x77384870
+  => fuse prog 0 737 0xc50ee4b2
+  => fuse prog 0 738 0xa27e5132
+  => fuse prog 0 739 0xeba887cf
+  => fuse prog 0 740 0x592c1e2b
+  => fuse prog 0 741 0xbb501799
+  => fuse prog 0 742 0xee702e07
+  => fuse prog 0 743 0xcf8ce73e
+  => fuse prog 0 744 0xfb55e2d5
+  => fuse prog 0 745 0xeba6bbd2
+
+  * On i.MX 8 QM:
+
+  => fuse prog 0 722 0xd436cc46
+  => fuse prog 0 723 0x8ecccda9
+  => fuse prog 0 724 0xb89e1601
+  => fuse prog 0 725 0x5fada3db
+  => fuse prog 0 726 0xd454114a
+  => fuse prog 0 727 0xb6cd51f4
+  => fuse prog 0 728 0x77384870
+  => fuse prog 0 729 0xc50ee4b2
+  => fuse prog 0 730 0xa27e5132
+  => fuse prog 0 731 0xeba887cf
+  => fuse prog 0 732 0x592c1e2b
+  => fuse prog 0 733 0xbb501799
+  => fuse prog 0 734 0xee702e07
+  => fuse prog 0 735 0xcf8ce73e
+  => fuse prog 0 736 0xfb55e2d5
+  => fuse prog 0 737 0xeba6bbd2
+
+1.5.5 Verify SECO events
+-------------------------
+
+If the fuses have been written properly, there should be no SECO events after
+boot. To validate this, power on the board, and run ahab_status command on
+U-Boot terminal.
+
+No events should be returned after this command:
+
+  => ahab_status
+  Lifecycle: 0x0020, NXP closed
+
+  No SECO Events Found!
+
+U-Boot will decode the SECO events and provide more details on the failure,
+for example in case container is not signed (signature is missing), but the
+device is not OEM closed:
+
+  => ahab_status
+  Lifecycle: 0x0020, NXP closed
+
+  SECO Event[0] = 0x0087EE00
+          CMD = AHAB_AUTH_CONTAINER_REQ (0x87)
+          IND = AHAB_NO_AUTHENTICATION_IND (0xEE)
+
+Note: In case the signature is incorrect (signed with wrong keys which are not
+matching the OTP SRK hashes) the event 0x0087FA00 is also displayed.
+
+1.5.6 Close the device
+-----------------------
+
+After the device successfully boots a signed image without generating any
+SECO security events, it is safe to close the device. The SECO lifecycle
+should be changed from 0x20 NXP closed to 0x80 OEM closed. Be aware this
+step can damage your board if a previous step failed. It is also
+irreversible. Run on the U-Boot terminal:
+
+  => ahab_close
+
+Now reboot the target, and run:
+
+  => ahab_status
+
+The lifecycle value should now be 0x80 OEM closed.
+
+2. Authenticating the OS container
+-----------------------------------
+
+The procedure for authenticating the OS container can be found in
+doc/imx/ahab/guides/sign_os_cntr.txt file.
+
+References:
+[1] AN12212: "Software Solutions for Migration Guide from Aarch32 to Aarch64"
diff --git a/doc/imx/ahab/guides/mx8_mx8x_spl_secure_boot.txt b/doc/imx/ahab/guides/mx8_mx8x_spl_secure_boot.txt
new file mode 100644
index 00000000000..3d8ef71264a
--- /dev/null
+++ b/doc/imx/ahab/guides/mx8_mx8x_spl_secure_boot.txt
@@ -0,0 +1,376 @@
+     +=========================================================+
+     +        i.MX 8, i.MX 8X AHAB guide on SPL targets        +
+     +=========================================================+
+
+1. AHAB secure boot process
+----------------------------
+
+This document provides a step-by-step guide on how securely boot a flash.bin
+image generated by Secondary Program Loader (SPL) targets. It is assumed that
+the reader is familiar with basic AHAB concepts and with the PKI tree
+generation.
+
+Details about AHAB can be found in the introduction_ahab.txt document and in
+processors Security Reference Manual Document (SRM).
+
+1.1 Preparing the environment to build a secure boot image
+-----------------------------------------------------------
+
+The following files and projects are used to prepare a secure boot image
+for i.MX8/8x device:
+
+- imx-mkimage.
+- SECO Firmware.
+- U-Boot proper and SPL. (Please refer to section 1.2)
+- ARM Trusted Firmware (ATF).
+- System Controller Firmware (SCFW).
+- Cortex M binary. (Optional)
+- Kernel image. (Optional)
+- Code signing tools (CST).
+
+The procedure to download the SECO firmware and build U-Boot, SCFW and ATF are
+out of the scope of this document, please refer to the Linux BSP Release Notes
+and AN12212[1] for further details.
+
+1.2 Preparing U-Boot to support AHAB secure boot features
+----------------------------------------------------------
+
+The U-Boot provides an alternative SPL target for i.MX8 and i.MX8x devices. The
+SPL is intended to be used by applications that requires a initial bootloader
+prior to initialize the ARM Trusted Firmware (ATF) and the U-Boot proper.
+
+The U-Boot support AHAB functions that are essential to completely authenticate
+the flash.bin image. On SPL targets only the SCFW, SPL and M4 IMG are
+authenticated at SCU ROM level, in order to authenticate the ATF and U-Boot
+proper it's necessary to call the SCU API sc_misc_seco_authenticate() function
+at SPL level.
+
+The support is enabled by adding CONFIG_AHAB_BOOT to the defconfig file used
+by your target:
+
+  - Defconfig:
+    CONFIG_AHAB_BOOT=y
+  - Kconfig:
+    ARM architecture -> Support i.MX 8 AHAB features
+
+1.3 Building a SPL image supporting secure boot
+------------------------------------------------
+
+The boot image generated by SPL targets has three containers:
+
+             +---------------------------+ ---------
+             |   1st Container header    |   ^
+             |       and signature       |   |
+             +---------------------------+   |
+             | Padding for 1kB alignment |   |
+             +---------------------------+   |
+             |   2nd Container header    |   |
+             |       and signature       |   |
+             +---------------------------+   |
+             |          Padding          |   |  Authenticated at
+             +---------------------------+   |   SCU ROM Level
+             |          SECO FW          |   |
+             +---------------------------+   |
+             |          Padding          |   |
+             +---------------------------+   |
+             |      SCU FW + DCD Table   |   |
+             +---------------------------+   |
+             |       Cortex-M Image      |   |
+             +---------------------------+   |
+             |         SPL Image         |   v
+             +---------------------------+ ---------
+             |   3rd Container header    |   ^
+             |       and signature       |   |
+             +---------------------------+   |
+             |          Padding          |   | Authenticated
+             +---------------------------+   |  at SPL Level
+             |     U-Boot Proper IMG     |   |
+             +---------------------------+   |
+             |    ARM Trusted FW (ATF)   |   v
+             +---------------------------+ ---------
+
+The first container includes the SECO firmware which is signed using NXP keys,
+this container is authenticated by SECO ROM at SCU ROM level.
+
+The second container includes the SCFW, SPL and Cortex M SW images which are
+signed using OEM keys, this container is authenticated by SECO FW at SCU ROM
+level.
+
+The third container includes the U-Boot proper and the ATF. The SPL is in
+charge to load this container and also to interface with SCU requesting
+SECO FW to authenticate the additional container.
+
+The signing procedure is slightly different when compared with HABv4 series. On
+AHAB the signature is directly included in the container, the CST is
+responsible to sign and handle the "Signature Block":
+
+             +----------------------------+ ---------
+             |                            |  ^
+             |                            |  |
+             |      Container header      |  |
+             |                            |  |
+             |                            |  |
+             +---+----------------------- +  |
+             | S | Signature block header |  | Signed
+             | i +------------------------+  |
+             | g |                        |  |
+             | n |                        |  |
+             | a |        SRK table       |  |
+             | t |                        |  |
+             | u |                        |  v
+             | r +------------------------+ ---------
+             | e |       Signature        |
+             |   +------------------------+
+             | B |                        |
+             | l |        SGK Key         |
+             | o | Certificate (optional) |
+             | c |                        |
+             | k |                        |
+             +---+------------------------+
+
+In case using the optional subordinate SGK key, the container signature is
+verified against the SGK key certificate. This certificate is verified
+against the SRK table.
+
+In case not using the subordinate key, the container signature is verified
+against the SRK keys directly.
+
+1.4 Preparing the boot image
+-----------------------------
+
+1.4.1 Preparing the 3rd container
+----------------------------------
+
+The first step is to generate the third container including the U-Boot proper
+and ATF images.
+
+The imx-mkimage project includes a target which only generates this third
+container:
+
+- Generating the U-Boot proper + ATF container:
+
+  $ make SOC=<SoC Name> u-boot-atf-container.img
+
+The mkimage log provides the container and signature block offsets used by the
+CSF description file:
+
+  CST: CONTAINER 0 offset: 0x0
+  CST: CONTAINER 0: Signature Block: offset is at 0x110
+
+The u-boot-atf-container.img file is the third container which have to be
+signed using the Code Signing Tool (CST).
+
+1.4.2 Signing the 3rd container
+--------------------------------
+
+The CSF description file contains all the commands that the SECO executes
+during the secure boot procedure. These commands instruct the AHAB code on
+which memory areas of the image to authenticate, which keys to install, use
+and etc.
+
+CSF examples are available under doc/imx/hab/ahab/csf_examples/ directory.
+
+As explained in section above the mkimage log provides the container and
+signature block offsets used by the CSF description file:
+
+- "Authenticate Data" command in csf_uboot_atf.txt file:
+
+  [Authenticate Data]
+  # Binary to be signed generated by mkimage
+  File = "u-boot-atf-container.img"
+  # Offsets = Container header  Signature block
+  Offsets   = 0x0               0x110
+
+- Sign the third container:
+
+  $ ./cst -i csf_uboot_atf.txt -o signed-u-boot-atf-container.img
+
+The signed-u-boot-atf-container.img have to be copied to imx-mkimage directory
+and renamed to u-boot-atf-container.img.
+
+1.4.3 Preparing the flash.bin image
+------------------------------------
+
+The signed 3rd container can be now used to create the final flash.bin image,
+be sure that your signed container were successfully replaced and is named
+as u-boot-atf-container.img.
+
+- Generating the flash.bin image:
+
+  $ make SOC=<SoC Name> flash_spl
+
+  Or use below command for i.MX8ULP
+
+  $ make SOC=<SoC Name> flash_singleboot_m33
+
+The mkimage log provides the container and signature block offsets used by the
+CSF description file:
+
+  CST: CONTAINER 0 offset: 0x400
+  CST: CONTAINER 0: Signature Block: offset is at 0x510
+
+The flash.bin file include three containers and the second container have to be
+signed using the Code Signing Tool (CST).
+
+1.4.4 Signing the flash.bin image
+----------------------------------
+
+As mentioned above the CSF description file contains all the commands that
+the SECO executes during the secure boot procedure.
+
+The procedure for signing the flash.bin image is similar as documented in
+mx8_mx8x_secure_boot.txt guide.
+
+- "Authenticate Data" command in csf_boot_image.txt file:
+
+  [Authenticate Data]
+  # Binary to be signed generated by mkimage
+  File = "flash.bin"
+  # Offsets = Container header  Signature block
+  Offsets   = 0x400             0x510
+
+- Sign the flash.bin container:
+
+ $ ./cst -i csf_boot_image.txt -o signed-flash.bin
+
+The signed-flash.bin image contains all the signatures and can be flashed in
+the device.
+
+1.5 Flashing the signed image
+------------------------------
+
+After completing all steps in section "1.4 Preparing the boot image" the
+signed flash.bin image can be flashed in the device:
+
+  $ sudo dd if=signed-flash.bin of=/dev/sd<X> bs=1k seek=32 && sync
+
+1.6 Programming SRK Hash
+-------------------------
+
+As explained in introduction_ahab.txt document the SRK Hash fuse values are
+generated by the srktool and should be programmed in the SoC SRK_HASH[511:0]
+fuses.
+
+Be careful when programming these values, as this data is the basis
+for the root of trust. An error in SRK Hash results in a part that
+does not boot.
+
+The U-Boot fuse tool can be used for programming eFuses on i.MX SoCs.
+
+- Dump SRK Hash fuses values in host machine:
+
+  $ od -t x4 SRK_1_2_3_4_fuse.bin
+  0000000 d436cc46 8ecccda9 b89e1601 5fada3db
+  0000020 d454114a b6cd51f4 77384870 c50ee4b2
+  0000040 a27e5132 eba887cf 592c1e2b bb501799
+  0000060 ee702e07 cf8ce73e fb55e2d5 eba6bbd2
+
+  On i.MX8ULP, the SRK Hash uses sha256 and dump 8 words fuses
+  $ od -t x4 SRK_1_2_3_4_fuse.bin
+  0000000 db2959f2 90dfc39c 53394566 e0b75829
+  0000020 85e6f3b1 af00983d e5e804fe 7a451024
+
+- Program SRK_HASH[511:0] fuses:
+
+  * On i.MX 8 QXP:
+
+  => fuse prog 0 730 0xd436cc46
+  => fuse prog 0 731 0x8ecccda9
+  => fuse prog 0 732 0xb89e1601
+  => fuse prog 0 733 0x5fada3db
+  => fuse prog 0 734 0xd454114a
+  => fuse prog 0 735 0xb6cd51f4
+  => fuse prog 0 736 0x77384870
+  => fuse prog 0 737 0xc50ee4b2
+  => fuse prog 0 738 0xa27e5132
+  => fuse prog 0 739 0xeba887cf
+  => fuse prog 0 740 0x592c1e2b
+  => fuse prog 0 741 0xbb501799
+  => fuse prog 0 742 0xee702e07
+  => fuse prog 0 743 0xcf8ce73e
+  => fuse prog 0 744 0xfb55e2d5
+  => fuse prog 0 745 0xeba6bbd2
+
+  * On i.MX 8 QM:
+
+  => fuse prog 0 722 0xd436cc46
+  => fuse prog 0 723 0x8ecccda9
+  => fuse prog 0 724 0xb89e1601
+  => fuse prog 0 725 0x5fada3db
+  => fuse prog 0 726 0xd454114a
+  => fuse prog 0 727 0xb6cd51f4
+  => fuse prog 0 728 0x77384870
+  => fuse prog 0 729 0xc50ee4b2
+  => fuse prog 0 730 0xa27e5132
+  => fuse prog 0 731 0xeba887cf
+  => fuse prog 0 732 0x592c1e2b
+  => fuse prog 0 733 0xbb501799
+  => fuse prog 0 734 0xee702e07
+  => fuse prog 0 735 0xcf8ce73e
+  => fuse prog 0 736 0xfb55e2d5
+  => fuse prog 0 737 0xeba6bbd2
+
+  * On i.MX 8 ULP:
+
+  => fuse prog 15 0 0xdb2959f2
+  => fuse prog 15 1 0x90dfc39c
+  => fuse prog 15 2 0x53394566
+  => fuse prog 15 3 0xe0b75829
+  => fuse prog 15 4 0x85e6f3b1
+  => fuse prog 15 5 0xaf00983d
+  => fuse prog 15 6 0xe5e804fe
+  => fuse prog 15 7 0x7a451024
+
+1.7 Verify SECO events
+-----------------------
+
+If the fuses have been written properly, there should be no SECO events after
+boot. To validate this, power on the board, and run ahab_status command on
+U-Boot terminal.
+
+No events should be returned after this command:
+
+  => ahab_status
+  Lifecycle: 0x0020, NXP closed
+
+  No SECO Events Found!
+
+U-Boot will decode the SECO events and provide more details on the failure,
+for example in case container image was signed with wrong keys and are not
+matching the OTP SRK hashes:
+
+  => ahab_status
+  Lifecycle: 0x0020, NXP closed
+
+  SECO Event[0] = 0x0087EE00
+          CMD = AHAB_AUTH_CONTAINER_REQ (0x87)
+          IND = AHAB_NO_AUTHENTICATION_IND (0xEE)
+
+Note: In case your SRK fuses are not programmed yet the event 0x0087FA00 may
+also be displayed.
+
+1.8 Close the device
+---------------------
+
+After the device successfully boots a signed image without generating any
+SECO security events, it is safe to close the device. The SECO lifecycle
+should be changed from 0x20 NXP closed to 0x80 OEM closed. Be aware this
+step can damage your board if a previous step failed. It is also
+irreversible. Run on the U-Boot terminal:
+
+  => ahab_close
+
+Now reboot the target, and run:
+
+  => ahab_status
+
+The lifecycle value should now be 0x80 OEM closed.
+
+2. Authenticating the OS container
+-----------------------------------
+
+The procedure for authenticating the OS container can be found in
+doc/imx/ahab/guides/sign_os_cntr.txt file.
+
+References:
+[1] AN12212: "Software Solutions for Migration Guide from Aarch32 to Aarch64"
diff --git a/doc/imx/ahab/guides/mx8ulp_secure_boot.txt b/doc/imx/ahab/guides/mx8ulp_secure_boot.txt
new file mode 100644
index 00000000000..a909ef0f97b
--- /dev/null
+++ b/doc/imx/ahab/guides/mx8ulp_secure_boot.txt
@@ -0,0 +1,421 @@
+     +=========================================================+
+     +             i.MX 8ULP AHAB guide using AHAB             +
+     +=========================================================+
+
+1. AHAB secure boot process
+----------------------------
+
+This document provides a step-by-step guide on how to securely boot a boot
+image. It is assumed that the reader is familiar with basic AHAB concepts and
+with the PKI tree generation.
+
+It is also assumed that the reader is familiar with all pieces of software
+needed. The procedure to build uboot, ATF, OPTEE and download the firmwares are
+ out of scope of this document, please refer to the Linux BSP user guide for
+further details.
+
+Details about AHAB can be found in the introduction_ahab.txt document and in
+processors Security Reference Manual Document (SRM).
+
+1.1 Preparing the environment to build a secure boot image
+-----------------------------------------------------------
+
+Secure boot image preparation requires mkimage to build and Code Signing tool
+to sign the image.
+
+Based on bootmode, following files are needed to prepare the boot image:
+- All boot modes
+  - Edgelock secure enclave Firmware (ELke).
+  - uPower Firmware.
+
+- Dualboot mode / Singleboot mode
+  - U-Boot proper and SPL.
+  - ARM Trusted Firmware (ATF).
+  - OPTEE (Optional)
+  - Cortex M binary (Optional in Singleboot mode)
+
+- LPboot mode
+  - Cortex M binary
+
+- Root of trust extension (Optional)
+  - Kernel image.
+
+In the following sections, <work> designates the repository where all
+parts have been downloaded and built.
+
+1.2 Preparing U-Boot to support AHAB secure boot features
+----------------------------------------------------------
+
+The U-Boot/SPL provides extra AHAB supported functionalities that include
+extension of Root of Trust, checking any events(issues) after image
+authentication, chip lifecycle status, securing the target etc.
+
+The support is enabled by adding CONFIG_AHAB_BOOT to the defconfig file used
+by your target:
+
+  - Defconfig:
+    CONFIG_AHAB_BOOT=y
+  - Kconfig:
+    ARM architecture -> Support i.MX 8 AHAB features
+
+Enabling this feature allows the SPL and uboot image to extend the Root of
+Trust by using the AHAB API call via ELke FW.
+
+1.3 Building an image supporting secure boot
+------------------------------------------------
+
+A typical singleboot mode image with Cortex-M support contains three containers:
+
+            *start ----> +---------------------------+ ---------
+                         |   1st Container header    |   ^
+                         |       and signature       |   |
+                         +---------------------------+   |
+                         | Padding for 1kB alignment |   |
+    *start + 0x400 ----> +---------------------------+   |
+                         |   2nd Container header    |   |
+                         |       and signature       |   |
+                         +---------------------------+   |
+                         |          Padding          |   |  Authenticated at
+                         +---------------------------+   |  ELke ROM/FW Level
+                         |          ELke FW          |   |
+                         +---------------------------+   |
+                         |          Padding          |   |
+                         +---------------------------+   |
+                         |         uPower FW         |   |
+                         +---------------------------+   |
+                         |       Cortex-M Image      |   |
+                         +---------------------------+   |
+                         |         SPL Image         |   v
+                         +---------------------------+ ---------
+                         |   3rd Container header    |   ^
+                         |       and signature       |   |
+                         +---------------------------+   |
+                         |          Padding          |   | Authenticated
+                         +---------------------------+   | at SPL Level
+                         |     U-Boot Proper IMG     |   |
+                         +---------------------------+   |
+                         |    ARM Trusted FW (ATF)   |   v
+                         +---------------------------+ ---------
+
+The first container includes the ELke FW which is signed using NXP keys, this
+container is authenticated by ELke ROM.
+
+The second container includes the SPL (in dualboot mode) or SPL and uPower FW
+(in singleboot mode) which are signed using OEM keys, this container is
+authenticated at ELke FW level.
+
+The third container includes the U-Boot proper and the ATF. The SPL is in
+charge to load this container and also to interface with ELke FW to authenticate
+ the additional container.
+
+The signing procedure is slightly different when compared with HABv4 series. On
+AHAB the signature is directly included in the container, the CST is
+responsible to sign and handle the "Signature Block":
+
+             +----------------------------+ ---------
+             |                            |  ^
+             |                            |  |
+             |      Container header      |  |
+             |                            |  |
+             |                            |  |
+             +---+----------------------- +  |
+             | S | Signature block header |  | Signed
+             | i +------------------------+  |
+             | g |                        |  |
+             | n |                        |  |
+             | a |        SRK table       |  |
+             | t |                        |  |
+             | u |                        |  v
+             | r +------------------------+ ---------
+             | e |       Signature        |
+             |   +------------------------+
+             | B |                        |
+             | l |        SGK Key         |
+             | o | Certificate (optional) |
+             | c |                        |
+             | k |                        |
+             +---+------------------------+
+
+The certificate block is divided into:
+
+                    +---------------+ ^
+                    |  Public key   | | Signed
+                    |  Permission   | |
+                    +---------------+ v
+                    |   Signature   |
+                    +---------------+
+
+The first block (public key permission) verify the Signature block preceding
+(between SRK table and Certificate blocks), while the second block (signature)
+is verified by the SRK table block.
+
+In case not using the subordinate key, the container signature is verified
+against the SRK keys directly.
+
+1.4 Preparing the signed boot image
+------------------------------------
+
+The imx-mkimage tool, provided as part of the BSP release, supports generating
+boot images for all the different boot modes supported by i.MX 8ULP. For more
+details on how to build image for each boot mode please refer to the Linux BSP
+user guide.
+
+Each boot mode constructs the boot image in different ways that are targeted
+for Cortex-A or Cortex-M or both.
+
+In the following sections building and signing a Cortex-A and Cortex-M image is
+ described.
+
+1.4.1 Signing Cortex-A core image
+---------------------------------------
+
+The boot modes that target Cortex-A core (dualboot and singleboot modes) also
+build the uboot and ATF container called "u-boot-atf-container". Please refer
+to "soc.mk" file in "<imx-mkimage>/iMX8ULP" for more details. This container is
+ needed to be signed first before signing the SPL container.
+
+1.4.1.1 Preparing the u-boot-atf-container
+-----------------------------------------
+
+The first step is to generate the u-boot-atf-container container which includes
+ the U-Boot proper and ATF images (including optionally OP-TEE).
+
+The imx-mkimage project includes a target which only generates this container:
+
+- Generating the U-Boot proper + ATF container:
+
+  $ make SOC=<SoC Name> u-boot-atf-container.img
+
+The mkimage log provides the container and signature block offsets used by the
+CSF description file:
+
+  CST: CONTAINER 0 offset: 0x0
+  CST: CONTAINER 0: Signature Block: offset is at 0x110
+
+Keep a note of the offsets above to be used with CST/CSF.
+
+The u-boot-atf-container.img file generated is needed to be signed using the
+Code Signing Tool (CST).
+
+1.4.1.2 Signing the u-boot-atf-container container
+-------------------------------------------------
+
+The CSF description file contains all the commands that the AHAB executes
+during the secure boot procedure. These commands instruct the AHAB code on
+which memory areas of the image to authenticate, which keys to install, use
+and etc.
+
+CSF examples are available under doc/imx/hab/ahab/csf_examples/ directory.
+
+As explained in section above, the mkimage log provides the container and
+signature block offsets used by the CSF description file (example provided in
+csf_uboot_atf.txt). These offsets need to be updated in the CSF file at
+"Authenticate Data" command along with the path to the flash.bin file:
+
+- "Authenticate Data" command in csf_uboot_atf.txt file:
+
+  [Authenticate Data]
+  # Binary to be signed generated by mkimage
+  File = "u-boot-atf-container.img"
+  # Offsets = Container header  Signature block
+  Offsets   = 0x0               0x110
+
+- Sign the container:
+
+  $ ./cst -i csf_uboot_atf.txt -o signed-u-boot-atf-container.img
+
+The signed-u-boot-atf-container.img will then have to be copied to the target's
+ directory in imx-mkimage and renamed to u-boot-atf-container.img.
+
+1.4.1.3 Preparing the flash.bin image with u-boot-atf-container
+----------------------------------------------------------------
+
+The signed u-boot-atf-container container can be now used to create the final
+flash.bin image, be sure that the signed u-boot-atf-container container was
+successfully replaced and is named as u-boot-atf-container.img in target's
+directory.
+
+- Generating the flash.bin image:
+
+  $ make SOC=<SoC Name> flash_<boot mode>
+
+The mkimage log provides the container and signature block offsets used by the
+CSF description file:
+
+  CST: CONTAINER 0 offset: 0x400
+  CST: CONTAINER 0: Signature Block: offset is at 0x510
+
+Keep a note of the offsets above to be used with CST/CSF.
+
+The final flash.bin image would include the container with SPL and the
+u-boot-atf-container container out of which the SPL container would have to be
+signed using the Code Signing Tool (CST).
+
+1.4.1.4 Signing the flash.bin image with u-boot-atf-container
+--------------------------------------------------------------
+
+As mentioned above the CSF description file contains all the commands that AHAB
+ executes during the secure boot procedure.
+
+CSF examples are available under doc/imx/hab/ahab/csf_examples/ directory.
+
+As explained in section above, the mkimage log provides the container and
+signature block offsets used by the CSF description file (example provided in
+csf_boot_image.txt). These offsets need to be updated in the CSF file at
+"Authenticate Data" command along with the path to the flash.bin file:
+
+
+- "Authenticate Data" command in csf_boot_image.txt file:
+
+  [Authenticate Data]
+  # Binary to be signed generated by mkimage
+  File = "flash.bin"
+  # Offsets = Container header  Signature block
+  Offsets   = 0x400             0x510
+
+- Sign the flash.bin image:
+
+ $ ./cst -i csf_boot_image.txt -o signed-flash.bin
+
+The signed-flash.bin image contains all the signatures and can be flashed in
+the device.
+
+1.4.2 Signing Cortex-M core image
+---------------------------------------
+
+The boot modes that target Cortex-M core (dualboot and LPboot modes) have one
+container to sign which contains the Cortex-M image along with uPower FW.
+Please refer to "soc.mk" file in "<imx-mkimage>/iMX8ULP" directory for more
+details.
+
+1.4.2.1 Preparing the Cortex-M core image
+------------------------------------------
+
+The final flash.bin image created using the imx-mkimage tool contains 2
+containers. 1st container consists of the NXP signed ELke FW and thus doesnt
+need signing. The 2nd container consists of the Cortex-M image and uPower FW at
+ the minimum.
+
+- Generating the flash.bin image:
+
+  $ make SOC=<SoC Name> flash_<boot mode>
+
+The mkimage log provides the container and signature block offsets used by the
+CSF description file:
+
+  CST: CONTAINER 0 offset: 0x400
+  CST: CONTAINER 0: Signature Block: offset is at 0x510
+
+Keep a note of the offsets above to be used with CST/CSF.
+
+Note: The flash.bin image created for Cortex-M core targetting FlexSPI NOR
+flash has the 1st container at an offset of 0x1000. This offset can be found in
+ "soc.mk" file in "<imx-mkimage>/iMX8ULP" directory. Thus the offsets provided
+by mkimage tool need to have 0x1000 added to them.
+
+1.4.2.2 Signing the Cortex-M core flash.bin image
+--------------------------------------------------
+
+As mentioned above, the CSF description file contains all the commands that AHAB
+ executes during the secure boot procedure.
+
+CSF examples are available under doc/imx/hab/ahab/csf_examples/ directory.
+
+As explained in section above, the mkimage log provides the container and
+signature block offsets used by the CSF description file (example provided in
+csf_boot_image.txt). These offsets need to be updated in the CSF file at
+"Authenticate Data" command along with the path to the flash.bin file:
+
+
+- "Authenticate Data" command in csf_boot_image.txt file:
+
+  [Authenticate Data]
+  # Binary to be signed generated by mkimage
+  File = "flash.bin"
+  # Offsets = Container header  Signature block
+  Offsets   = 0x1400             0x1510
+
+Note: The offsets have been incremented by 0x1000, as described above.
+
+- Sign the flash.bin image:
+
+ $ ./cst -i csf_boot_image.txt -o signed-flash.bin
+
+The signed-flash.bin image contains all the signatures and can be flashed in
+the device.
+
+1.5 Flashing the signed image
+------------------------------
+
+After completing all steps in Section 1.4 the signed flash.bin image can be
+flashed in the device using UUU. Please refer to UUU documentation for more
+details on programming the flash devices on the target.
+
+1.6 Programming SRK Hash
+-------------------------
+
+As explained in introduction_ahab.txt document the SRK Hash fuse values are
+generated by the srktool and should be programmed in the SoC SRK_HASH[255:0]
+fuses.
+
+Be careful when programming these values, as this data is the basis for the
+root of trust. An error in SRK Hash results in a part that does not boot.
+
+The U-Boot fuse tool can be used for programming eFuses on i.MX SoCs.
+
+- Dump SRK Hash fuses values in host machine:
+
+  On i.MX8ULP, the SRK Hash uses sha256 and dump 8 words fuses
+  $ od -t x4 SRK_1_2_3_4_fuse.bin
+  0000000 db2959f2 90dfc39c 53394566 e0b75829
+  0000020 85e6f3b1 af00983d e5e804fe 7a451024
+
+- Program SRK_HASH[255:0] fuses:
+
+  * On i.MX 8 ULP:
+
+  => fuse prog 15 0 0xdb2959f2
+  => fuse prog 15 1 0x90dfc39c
+  => fuse prog 15 2 0x53394566
+  => fuse prog 15 3 0xe0b75829
+  => fuse prog 15 4 0x85e6f3b1
+  => fuse prog 15 5 0xaf00983d
+  => fuse prog 15 6 0xe5e804fe
+  => fuse prog 15 7 0x7a451024
+
+1.7 Verify AHAB events
+-----------------------
+
+If the fuses have been burned properly, there should be no AHAB events after
+boot. To validate this, power on the board, and run ahab_status command on
+U-Boot terminal.
+
+No events should be returned after this command:
+
+  => ahab_status
+  Lifecycle: 0x0020, NXP closed
+
+
+1.8 Close the device
+---------------------
+
+After the device successfully boots a signed image without generating any AHAB
+security events, it is safe to close the device. The chip lifecycle should be
+changed from 0x20 NXP closed to 0x80 OEM closed. Be aware this step can damage
+your board if a previous step failed. It is also irreversible. Run on the
+U-Boot terminal:
+
+  => ahab_close
+
+Now reboot the target, and run:
+
+  => ahab_status
+
+The lifecycle value should now be 0x80 OEM closed.
+
+2. Authenticating the OS container
+-----------------------------------
+
+The procedure for authenticating the OS container can be found in
+doc/imx/ahab/guides/sign_os_cntr.txt file.
+
diff --git a/doc/imx/ahab/guides/sign_os_cntr.txt b/doc/imx/ahab/guides/sign_os_cntr.txt
new file mode 100644
index 00000000000..7fad69b548a
--- /dev/null
+++ b/doc/imx/ahab/guides/sign_os_cntr.txt
@@ -0,0 +1,102 @@
+     +=========================================================+
+     +       i.MX 8/8x/8ULP Extend RoT guide using AHAB      +
+     +=========================================================+
+
+1. Extension of Root of Trust
+------------------------------
+
+The Root of Trust established by enabling secure boot in boot image can be
+extended by authenticating the OS by an authentic uboot image. Following
+sections describes ways to build and sign an OS container.
+
+2. Signing the OS container
+-----------------------------------
+
+The OS container needs to be prepared with proper container header in order to
+sign the OS image. Using imx-mkimage tool provided by NXP, the OS image can be
+wrapped into a container format.
+
+Note: Signing OS container is not mandatory. If you do not plan to authenticate
+ the kernel image, you can disable this behavior by setting sec_boot=no in
+U-Boot environment variable.
+
+Note: OS image can also be authenticated by running a U-Boot command:
+
+  => auth_cntr <Container address>
+
+2.1 Prepare the OS container image
+-----------------------------------
+
+Note: As the final OS container image is also generated as flash.bin, make sure
+ to save any other flash.bin image previously generated.
+
+- Build the kernel image for the target
+
+  $ make SOC=<SoC name> flash_kernel
+  $ mv <SoC name>/flash.bin <SoC name>/flash_os.bin
+
+Note: flash.bin has been renamed to flash_os.bin for clarity.
+
+If the make command ends successfully, the end of the result should look
+like:
+
+  CST: CONTAINER 0 offset: 0x0
+  CST: CONTAINER 0: Signature Block: offset is at 0x110
+  DONE.
+  Note: Please copy image to offset: IVT_OFFSET + IMAGE_OFFSET
+
+Keep a note of the offsets above to be used with CST/CSF
+
+2.2 Creating the CSF description file for OS container image
+-------------------------------------------------------------
+
+CSF examples are available under doc/imx/hab/ahab/csf_examples/ directory.
+
+The csf_linux_img.txt file example should be updated with the offset values
+of the 2.1 chapter and the path to the flash_os.bin file. It is the last
+part of the file:
+
+  [Authenticate Data]
+  # Binary to be signed generated by mkimage
+  File = "flash_os.bin"
+  # Offsets = Container header  Signature block (printed out by mkimage)
+  Offsets   = 0x0             0x110
+
+2.3 Authenticating container image
+-----------------------------------
+
+Now CST can be used to sign the OS image using the previously created
+csf_linux_img.txt Commands Sequence File:
+
+  $ cd <work>
+  $ ./release/linux64/bin/cst -i csf_linux_img.txt -o os_cntr_signed.bin
+
+2.4 Copy OS container
+----------------------
+
+- For i.MX 8 QXP/QM/DXL
+
+Mount the SD Card:
+
+  $ sudo mount /dev/sdX1 partition
+
+Copy the OS signed image on the SD Card:
+
+  $ sudo cp os_cntr_signed.bin /media/UserID/Boot\ <soc>
+
+Finally:
+
+  $ sudo umount partition
+
+- For i.MX 8ULP
+
+Goto fastboot mode from uboot:
+
+  => fastboot auto
+  auto usb 0
+
+Use UUU to download signed OS container:
+
+  $ sudo ./uuu ucmd setenv fastboot_buffer ${cntr_addr}
+  $ sudo ./uuu download -i os_cntr_signed.bin
+  $ sudo ./uuu FB: ucmd fatwrite mmc 0:1 ${fastboot_buffer} os_cntr_signed.bin <size in hex>
diff --git a/doc/imx/ahab/introduction_ahab.txt b/doc/imx/ahab/introduction_ahab.txt
new file mode 100644
index 00000000000..7f7ebe0eb45
--- /dev/null
+++ b/doc/imx/ahab/introduction_ahab.txt
@@ -0,0 +1,402 @@
+          +=======================================================+
+          +       i.MX Secure and Encrypted Boot using AHAB       +
+          +=======================================================+
+
+1. Introduction
+----------------
+
+The i.MX 8/8x/8ULP family of applications processors introduce a new secure
+boot concept. Due to the multi-core architecture, the Security Controller (SECO)
+ and System Control Unit (SCU) in i.MX 8/8x, and Edgelock secure enclave in i.MX
+ 8ULP are heavily involved in the secure boot process.
+
+Step-by-step guides are available under doc/imx/hab/ahab/guides/ directory,
+users familiar with AHAB architecture and CST PKI tree generation should
+refer to these documents instead.
+
+1.1 The AHAB Secure Boot Architecture
+--------------------------------------
+
+The Advanced High Assurance Boot (AHAB) feature relies in digital signatures to
+prevent unauthorized software execution during the device boot sequence. In
+case a malware takes control of the boot sequence, sensitive data, services and
+network can be impacted.
+
+The AHAB authentication is based on public key cryptography in which image
+data is signed offline using one or more private keys. The resulting signed
+image data is then verified on the i.MX processor using the corresponding
+public keys. The public keys are included in the final binary and the SRK
+Hash is programmed in the SoC fuses for establishing the root of trust.
+
+In i.MX8 and i.MX8x families the SCU is responsible to interface with the boot
+media, managing the process of loading the firmware and software images in
+different partitions of the SoC. The SECO is responsible to authenticate the
+images and authorize the execution of them.
+
+1.1.1 [i.MX 8/8x] The System Control Unit (SCU)
+------------------------------------
+
+The System Control Unit SCU is a subsystem equipped with a programmable M4
+core, which is responsible to handle the resource allocation, power, clocking,
+IO configuration and muxing.
+
+The SCU is also responsible to interface between the rest of the system. In the
+secure boot flow the SCU interfaces with the Security Controller (SECO),
+requesting the image authentication.
+
+The System Control Unit FW (SCFW) is responsible to control all the
+functionalities of the SCU. This firmware is distributed in a porting kit form.
+Instructions to download the SCFW Porting Kit are available in the Linux BSP
+Release Notes.
+
+Details about SCU can be found in the processors Reference Manual (RM).
+
+1.1.2 [i.MX 8/8x] The Security Controller (SECO)
+-------------------------------------
+
+The SECO is a M0+ core dedicated to handle the SoC security subsystem. The
+controller communicates with SCU domain through a dedicate message unit (MU).
+
+The SECO has a dedicate ROM which is responsible to initialize low level
+security features and to authenticate the SECO firmware previously loaded by
+the SCU ROM.
+
+The SECO firmware provides security services at run-time to different domains
+of the SoC, one of these being the capability of authenticate images.
+
+The SECO firmware is signed and distributed by NXP and is always authenticated
+in OEM open and closed configuration, instructions to download the SECO FW are
+available in the Linux BSP Release Notes.
+
+Details about SECO can be found in the processors Security Reference Manual
+(SRM).
+
+1.1.3 [i.MX 8ULP] The Edgelock secure enclave
+-------------------------------------
+
+EdgeLockâ„¢ Secure Enclave is the security subsystem based on a dedicated core
+(RISC-V) to manage security tasks with a tight control on security resources
+along with other enhancements.
+
+The secure enclave has a dedicate ROM which is responsible to initialize low
+level security features and to authenticate the secure enclave firmware
+previously loaded by the boot management core.
+
+The secure enclave firmware provides security services at run-time to different
+ domains of the SoC, one of these being the capability of authenticate images.
+
+The secure enclave firmware is signed and distributed by NXP and is always
+authenticated in OEM open and closed configuration, instructions to download
+this FW are available in the Linux BSP Release Notes.
+
+Details about Edgelock secure enclave can be found in the processors Security
+Reference Manual (SRM).
+
+NOTE: The terms Sentinel, S400, and EdgeLock secure enclave (ELke), and ELke
+are used interchangeably throughout the document.
+
+1.2 The image container
+------------------------
+
+Due to the new architecture, multiple firmwares and softwares are required to
+boot AHAB supporting devices. In order to store all the images in a single
+binary the container image structure is used.
+
+At least two containers are needed for the boot process, the first container
+must include only the Security Subsystem FW (SECO/ELke FW provided by NXP).
+Additional containers can contain one or multiple images, depending on the
+users specific application.
+
+The final binary is generated by the imx-mkimage tool.
+
+1.3 The i.MX8/8x secure boot flow
+----------------------------------
+
+As mentioned in the introduction, due to the multiple cores architecture the
+i.MX8 boot sequence involves SCU ROM, SCFW, SECO ROM, and SECO FW.
+
+The diagram below illustrate the secure boot flow overview:
+
+System Controller   │  Security Controller  │     Cortex-M     │   Cortex-A
+      (SCU)         │        (SECO)         │                  │
+                    │                       │                  │
+ ╔�������������╗    │   ╔�������������╗  ┌───────────�       ┌─────────�
+ ║   SCU INIT  ║    │   ║  SECO INIT  ║  │  │        │       │ │       │
+ ╚������╤�������    │   ╚������╤�������  │  │        v       │ │       v
+        │           │          │         │  │  ┌──────────�  │ │ ┌────────────�
+ ╔������╧������╗    │          │         │  │  │ Start M4 │  │ │ │  Start AP  │
+ ║Load SECO FW ║    │          │         │  │  │   IMG    │  │ │ │    IMG     │
+ ╚������╤�������    │   ╔������╧������╗  │  │  └──────────┘  │ │ └─────┬──────┘
+        ├──────────────>║Auth SECO FW ║  │  │                │ │       │
+ ╔������╧������╗    │   ╚������╤�������  │  │   ┌────────────┘ │       │
+ ║ Load SCU FW ║    │          │         │  │   │              │       │
+ ║   and DCD   ║    │          │         │  │   │              │ ┌─────┴──────�
+ ╚������╤�������    │   ┌──────┴──────�  │  │   │              │ │    Load    │
+        ├──────────────>│ Auth SCU FW │  │  │   │              │ │ Add AP IMG │
+        │           │   │   and DCD   │  │  │   │              │ └─────┬──────┘
+ ╔������╧������╗    │   └──────┬──────┘  │  │   │              │       │
+ ║   Run DCD   ║<──────────────┤         │  │   │              │       │
+ ╚������╤�������    │          │         │  │   │      ┌───────────────┤
+        │           │          │         │  │   │      │       │       │
+ ╔������╧������╗    │          │         │  │   │      │       │       │
+ ║ Load M4 IMG ║    │          │         │  │   │      │       │       │
+ ╚������╤�������    │   ┌──────┴──────�  │  │   │      │       │       │
+        ├──────────────>│ Auth M4 IMG │  │  │   │      │       │       │
+ ╔������╧������╗    │   └──────┬──────┘  │  │   │      │       │ ┌─────┴──────�
+ ║ Load AP IMG ║    │          │         │  │   │      │       │ │     Run    │
+ ╚������╤�������    │   ┌──────┴──────�  │  │   │      │       │ │ Add AP IMG │
+        ├──────────────>│ Auth AP IMG │  │  │   │      │       │ └────────────┘
+ ╔������╧������╗    │   └─────────────┘  │  │   │      │       │
+ ║Start SCU FW ║    │ ┌──────────────────┘  │   │      │       │
+ ╚������╤�������    │ │                     │   │      │       │
+        │           │ │   ┌─────────────────────┘      │       │
+ ┌──────┴──────�    │ │   │                 │          │       │
+ │  Start M4   ├──────┘   │     ┌──────────────────────┘       │
+ └──────┬──────┘    │     │     │           │                  │
+        │           │     │     │           │                  │
+ ┌──────┴──────�    │     │     │           │                  │
+ │  Start AP   ├──────────┘     │           │                  │
+ └─────────────┘    │           │           │                  │
+        ┌───────────────────────┘           │                  │
+        │           │                       │                  │
+        v           │                       │                  │
+ ┌─────────────�    │   ┌─────────────�     │                  │
+ │Request SECO ├───────>│ Auth AP IMG │     │                  │
+ └─────────────┘    │   └─────────────┘     │                  │
+                    │                       │                  │
+
+
+Notes:
+All boxes enclosed by double dash (�) are performed at SCU/SECO ROM level.
+
+The sequence below explains the i.MX8 and i.MX8x boot flow:
+
+1  - At reset, the SCU ROM and SECO ROM both start execution.
+2  - The SCU ROM reads the boot configuration and loads the SECO FW (First
+     container) from the boot media to the SECO TCM.
+3  - A message is sent by the SCU ROM via MU requesting the SECO ROM to
+     authenticate the SECO FW which is signed using NXP key.
+4  - The SCU ROM loads the second container from the boot media, this container
+     must contain at least the SCFW which is signed using the OEM keys.
+5  - The SCU ROM loads the SCFW to the SCU TCM, a message is sent via MU
+     requesting the SECO FW to authenticate the SCFW and DCD table.
+6  - The SCU ROM configures the DDR and loads the M4 and AP images included in
+     the second container to their respective load addresses.
+7  - The SCU ROM request the SECO FW to authenticate the M4 image.
+8  - The SCU ROM request the SECO FW to authenticate the AP image. This image
+     is the initial AP core software, depending in the U-Boot target it can
+     be the U-Boot and ATF or only SPL.
+9  - The SCFW is initialized and starts the ARM Cortex-M and Cortex-A cores.
+10 - From this point additional containers can be loaded by Cortex-M and
+     Cortex-A cores and authenticated by SECO, the AP SW must interface with
+     SCU by calling the sc_misc_seco_authenticate() API function. In current
+     U-Boot implementation the additional image can be the Linux Kernel binary
+     or the U-Boot proper and ATF. Details about current U-Boot implementation
+     can be found in AHAB guides included in doc/imx/hab/ahab/guides/ directory.
+
+1.4 The i.MX 8ULP secure boot flow
+----------------------------------
+
+i.MX8ULP boot sequence involves multiple cores booting up at same time and
+Edgelock secure enclave ensure authentication of any boot software being loaded.
+
+The diagram below illustrate the secure boot flow overview for dual boot
+scenario:
+
+
+    Cortex-M(CM)     │   Edgelock Secure   │    Cortex-A(CA)   │   uPower(uP)
+                     │    Enclave(ELke)     │                   │
+          │          │          │          │         │         │        │
+   ┌┬─────┴─────┬�   │   ┌┬─────┴─────┬�   │         │         │ ┌┬─────┴─────┬�
+   ││   INIT    ││   │   ││   INIT    ││   │         │         │ ││   INIT    ││
+   └┴─────┬─────┴┘   │   └┴─────┬─────┴┘   │         │         │ └┴─────┬─────┴┘
+          │          │          │          │  ┌┬─────┴─────┬�  │        │
+   ┌┬─────┴─────┬�   │          │          │  ││Load CA FW ││ ┌──────�  │
+   ││Load uP FW ││   │          │          │  └┴─────┬─────┴┘ ││     │  │
+   └┴─────┬─────┴┘   │          │          │         │        ││ ┌┬──v──┴─────┬�
+          │          │   ┌┬─────┴─────┬�   │┌────────┤        ││ ││Load &Start││
+          ├─────────────>├│Auth uP FW ││   ││        │        ││ ││   uP FW   ││
+          │          │   └┴─────┬─────┴┘   ││        │        ││ └┴───────────┴┘
+   ┌┬─────┴─────┬�   │          │          ││        │        ││
+   ││Load CM  FW││   │          ├────────────────────┼────────┘│
+   └┴─────┬─────┴┘   │          │          ││        │         │
+          │          │   ┌┬─────┴─────┬�   ││        │         │
+          ├─────────────>├│Auth CM FW ││   ││ ┌┬─────┴─────┬�  │
+          │          │   └┴─────┬─────┴┘   ││ ││Start CA FW││  │
+   ┌┬─────┴─────┬�   │          │          ││ └┴─────┬─────┴┘  │
+   ││Load ELkeFW││   │          │          ││        │         │
+   └┴─────┬─────┴┘   │          │          ││        │         │
+          │          │   ┌┬─────┴─────┬�   ││        │         │
+          ├─────────────>├│Auth ELkeFW││   ││        │         │
+          │          │   └┴─────┬─────┴┘   ││ ┌┬─────┴─────┬�  │
+   ┌┬─────┴─────┬�   │          │          ││ ││ Load SPL  ││  │
+   ││Start CM FW││   │          │          ││ └┴─────┬─────┴┘  │
+   └┴─────┬─────┴┘   │          │          ││        │         │
+          │          │   ┌┬─────┴─────┬�   ││   ┌────┤         │
+          │          │   ││Auth CA FW │┤<───┘   │    │         │
+          │          │   └┴─────┬─────┴┘   │    │    │         │
+          │          │          │          │    │    │         │
+          │          │   ┌┬─────┴─────┬�   │    │    │         │
+          │          │   ││ Auth SPL  │┤<───────┘    │         │
+          │          │   └┴─────┬─────┴┘   │         │         │
+          │          │          ├─────────────────�  │         │
+          │          │          │          │      │  │         │
+          │          │          │          │  ┌┬──v──v─────┬�  │
+          │          │          │          │  ││  Run SPL  ││  │
+          │          │          │          │  └┴───────────┴┘  │
+
+More details on the boot flow can be found in respective Security Reference
+Manual (SRM).
+
+2. Generating a PKI tree
+-------------------------
+
+The first step is to generate the private keys and public keys certificates.
+The AHAB architecture is based on a Public Key Infrastructure (PKI) tree.
+
+The Code Signing Tools package contains an OpenSSL based key generation script
+under keys/ directory. The ahab_pki_tree.sh script generates a PKI tree
+containing 4 Super Root Keys (SRK), possible to also include a subordinate
+SGK key.
+
+The AHAB supports both RSA and ECC keys, a new PKI tree can be generated by
+following the example below:
+
+- Generating a P384 ECC PKI tree on CST (starting from v3.1.0):
+
+  $ ./ahab_pki_tree.sh
+  ...
+  Do you want to use an existing CA key (y/n)?: n
+  Do you want to use Elliptic Curve Cryptography (y/n)?: y
+  Enter length for elliptic curve to be used for PKI tree:
+  Possible values p256, p384, p521:  p384
+  Enter the digest algorithm to use: sha384
+  Enter PKI tree duration (years): 5
+  Do you want the SRK certificates to have the CA flag set? (y/n)?: n
+
+The diagram below illustrate the PKI tree generated:
+
+                             ┌─────────�
+                             │   CA    │
+                             └────┬────┘
+                                  │
+                                  │
+         ┌───────────────┬────────┴────────┬───────────────�
+         │               │                 │               │
+         │               │                 │               │
+         v               v                 v               v
+    ┌────────�       ┌────────�       ┌────────�       ┌────────�
+    │  SRK1  │       │  SRK2  │       │  SRK3  │       │  SRK4  │
+    └────────┘       └────────┘       └────────┘       └────────┘
+
+2.1 Generating a PKI tree including a subordinate SGK key
+----------------------------------------------------------
+
+The ahab_pki_tree.sh script is also able to generate a PKI tree containing a
+subordinate key of the SRK, this key can be used to verify the signature
+included in the final signed image.
+
+Users should set the CA flag when generating the SRK certificates.
+
+- Generating a P384 ECC PKI tree with a subordinate SGK key on CST (starting
+from v3.1.0):
+
+  $ ./ahab_pki_tree.sh
+  ...
+  Do you want to use an existing CA key (y/n)?: n
+  Do you want to use Elliptic Curve Cryptography (y/n)?: y
+  Enter length for elliptic curve to be used for PKI tree:
+  Possible values p256, p384, p521:  p384
+  Enter the digest algorithm to use: sha384
+  Enter PKI tree duration (years): 5
+  Do you want the SRK certificates to have the CA flag set? (y/n)?: y
+
+The diagram below illustrate the PKI tree generated:
+
+                             ┌─────────�
+                             │   CA    │
+                             └────┬────┘
+                                  │
+                                  │
+         ┌───────────────┬────────┴────────┬───────────────�
+         │               │                 │               │
+         v               v                 v               v
+    ┌────────�       ┌────────�       ┌────────�       ┌────────�
+    │  SRK1  │       │  SRK2  │       │  SRK3  │       │  SRK4  │
+    └────┬───┘       └───┬────┘       └────┬───┘       └───┬────┘
+         │               │                 │               │
+         v               v                 v               v
+    ┌────────�       ┌────────�       ┌────────�       ┌────────�
+    │  SGK1  │       │  SGK2  │       │  SGK3  │       │  SGK4  │
+    └────────┘       └────────┘       └────────┘       └────────┘
+
+2.2 Generating a SRK Table and SRK Hash
+----------------------------------------
+
+The next step is to generated the SRK Table and its respective SRK Table Hash
+from the SRK public key certificates created in one of the steps above.
+
+In the AHAB architecture, the SRK Table is included in the signed image and the
+SRK Hash is programmed in the SoC SRK_HASH[511:0] fuses.
+
+On the target device during the authentication process the AHAB code verify the
+SRK Table against the SoC SRK_HASH fuses, in case the verification is successful
+the root of trust is established and the AHAB code can progress with the image
+authentication.
+
+The srktool can be used to generate the SRK Table and its respective SRK
+Table Hash.
+
+- Generating SRK Table and SRK Hash in Linux 64-bit machines:
+  - In i.MX 8/8x family, the expected SRK HASH is of 512 bit.
+    $ cd ../crts/
+    $ ../linux64/bin/srktool -a -s sha384 -t SRK_1_2_3_4_table.bin \
+	  -e SRK_1_2_3_4_fuse.bin -f 1 -c \
+	  SRK1_sha384_secp384r1_v3_usr_crt.pem,\
+	  SRK2_sha384_secp384r1_v3_usr_crt.pem,\
+	  SRK3_sha384_secp384r1_v3_usr_crt.pem,\
+	  SRK4_sha384_secp384r1_v3_usr_crt.pem
+
+  - In i.MX 8ULP, the expected SRK HASH is of 256 bit.
+    $ cd ../crts/
+    $ ../linux64/bin/srktool -a -d sha256 -s sha384 -t SRK_1_2_3_4_table.bin \
+	  -e SRK_1_2_3_4_fuse.bin -f 1 -c \
+	  SRK1_sha384_secp384r1_v3_usr_crt.pem,\
+	  SRK2_sha384_secp384r1_v3_usr_crt.pem,\
+	  SRK3_sha384_secp384r1_v3_usr_crt.pem,\
+	  SRK4_sha384_secp384r1_v3_usr_crt.pem
+
+    Regenerate the SRK HASH (SRK_1_2_3_4_fuse.bin) by using SHA256 with
+    SRK_1_2_3_4_table.bin.
+    $ openssl dgst -binary -sha256 SRK_1_2_3_4_table.bin
+
+
+
+- Optionally users can check if the sha512sum/sha256sum of SRK_1_2_3_4_table
+matches with the SRK_1_2_3_4_fuse.bin:
+
+  $ od -t x4 --endian=big SRK_1_2_3_4_fuse.bin
+  0000000 01b04697 0253376b 2066fe56 aaef9a91
+  0000020 e62e09d8 14fb7e36 d5b38d05 0982edab
+  0000040 7ada6576 2f6b4f59 1fd9347e 46e7305d
+  0000060 46e34bf0 89780bd1 c809e714 a17e2f4e
+
+  $ sha512sum SRK_1_2_3_4_table.bin
+  01b046970253376b2066fe56aaef9a91\
+  e62e09d814fb7e36d5b38d050982edab\
+  7ada65762f6b4f591fd9347e46e7305d\
+  46e34bf089780bd1c809e714a17e2f4e\
+  SRK_1_2_3_4_table.bin
+
+NOTE: The commands above cannot be used as reference to program the SoC
+      SRK_HASH fuses.
+
+The SRK_1_2_3_4_table.bin and SRK_1_2_3_4_fuse.bin files can be used in further
+steps as explained in AHAB guides available under doc/imx/hab/ahab/guides/
+directory.
+
+3 Known limitations
+----------------------------------------
+
+- Due to a limitation in i.MX8QXP B0 silicon it's not possible to use RSA
+4096-bit SRK keys with an additional subordinate SGK key.
diff --git a/doc/imx/habv4/csf_examples/additional_images/csf_additional_images.txt b/doc/imx/habv4/csf_examples/additional_images/csf_additional_images.txt
index bbe489714bc..589fd56f068 100644
--- a/doc/imx/habv4/csf_examples/additional_images/csf_additional_images.txt
+++ b/doc/imx/habv4/csf_examples/additional_images/csf_additional_images.txt
@@ -29,6 +29,6 @@
     # Key slot index used to authenticate the image data
     Verification index = 2
     # Authenticate Start Address, Offset, Length and file
-    Blocks = 0x80800000 0x00000000 0x80EEA020 "zImage", \
-	     0x83800000 0x00000000 0x8380B927 "imx7d-sdb.dtb", \
-	     0x84000000 0x00000000 0x840425B8 "uTee-7dsdb"
+    Blocks = 0x80800000 0x00000000 0x006EA000 "zImage", \
+	     0x83800000 0x00000000 0x0000B927 "imx7d-sdb.dtb", \
+	     0x84000000 0x00000000 0x000425B8 "uTee-7dsdb"
diff --git a/doc/imx/habv4/csf_examples/mx6_mx7/csf_u-boot_enc.txt b/doc/imx/habv4/csf_examples/mx6_mx7/csf_u-boot_enc.txt
new file mode 100644
index 00000000000..96083a6a589
--- /dev/null
+++ b/doc/imx/habv4/csf_examples/mx6_mx7/csf_u-boot_enc.txt
@@ -0,0 +1,50 @@
+[Header]
+    Version = 4.2
+    Hash Algorithm = sha256
+    Engine Configuration = 0
+    Certificate Format = X509
+    Signature Format = CMS
+    Engine = CAAM
+
+[Install SRK]
+    # Index of the key location in the SRK table to be installed
+    File = "../crts/SRK_1_2_3_4_table.bin"
+    Source index = 0
+
+[Install CSFK]
+    # Key used to authenticate the CSF data
+    File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem"
+
+[Authenticate CSF]
+
+[Install Key]
+    # Key slot index used to authenticate the key to be installed
+    Verification index = 0
+    # Target key slot in HAB key store where key will be installed
+    Target Index = 2
+    # Key to install
+    File= "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem"
+
+[Authenticate Data]
+    # Key slot index used to authenticate the image data
+    Verification index = 2
+    # This Authenticate Data command covers the IVT and DCD Data
+    # The image file referenced will remain unmodified by CST
+    Blocks = 0x877ff400 0x000 0xc00 "u-boot-dtb.imx"
+
+[Install Secret Key]
+    # Install the blob
+    Verification Index = 0
+    Target Index = 0
+    Key = "dek.bin"
+    Key Length = 128
+    # Start address + padding 0x2000 + length
+    Blob Address = 0x878a0000
+
+[Decrypt Data]
+    # The decrypt data command below causes CST to modify the input
+    # file and encrypt the specified block of data. This image file
+    # is a copy of the file used for the authentication command above
+    Verification Index = 0
+    Mac Bytes = 16
+    Blocks = 0x87800000 0x00000c00 0x9e000 "u-boot-dtb.imx-enc"
diff --git a/doc/imx/habv4/csf_examples/mx6_mx7/csf_u-boot_sign_enc.txt b/doc/imx/habv4/csf_examples/mx6_mx7/csf_u-boot_sign_enc.txt
new file mode 100644
index 00000000000..7e508020af3
--- /dev/null
+++ b/doc/imx/habv4/csf_examples/mx6_mx7/csf_u-boot_sign_enc.txt
@@ -0,0 +1,53 @@
+[Header]
+    Version = 4.2
+    Hash Algorithm = sha256
+    Engine Configuration = 0
+    Certificate Format = X509
+    Signature Format = CMS
+    Engine = CAAM
+
+[Install SRK]
+    # Index of the key location in the SRK table to be installed
+    File = "../crts/SRK_1_2_3_4_table.bin"
+    Source index = 0
+
+[Install CSFK]
+    # Key used to authenticate the CSF data
+    File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem"
+
+[Authenticate CSF]
+
+[Install Key]
+    # Key slot index used to authenticate the key to be installed
+    Verification index = 0
+    # Target key slot in HAB key store where key will be installed
+    Target Index = 2
+    # Key to install
+    File= "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem"
+
+[Authenticate Data]
+    # This Authenticate Data commandcovers both clear and encrypted data.
+    # The image file referenced will remain unmodified by CST.
+    # Key slot index used to authenticate the image data
+    Verification index = 2
+    # Authenticate Start Address, Offset, Length and file
+    Blocks = 0x877ff400 0x000 0x0009ec00 "u-boot-dtb.imx-enc"
+
+[Install Secret Key]
+    # Install the blob - This will manage a new key that will not be used in
+    # the final image, so the file name has to be different
+    Verification Index = 0
+    Target Index = 0
+    Key = "dek-dummy.bin"
+    Key Length = 128
+    # Start address + padding 0x2000 + length
+    Blob Address = 0x878a000
+
+[Decrypt Data]
+    # The decrypt Data command is a place holder to ensure the
+    # CSF includes the decrypt data command from the first pass.
+    # The file that CST will encrypt will not be used, so the file
+    # name has to be different.
+    Verification Index = 0
+    Mac Bytes = 16
+    Blocks = 0x87800000 0x00000c00 0x9e000 "u-boot-dtb.imx-dummy"
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
new file mode 100644
index 00000000000..d9218ab4311
--- /dev/null
+++ b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt
@@ -0,0 +1,36 @@
+[Header]
+    Version = 4.3
+    Hash Algorithm = sha256
+    Engine = CAAM
+    Engine Configuration = 0
+    Certificate Format = X509
+    Signature Format = CMS
+
+[Install SRK]
+    # Index of the key location in the SRK table to be installed
+    File = "../crts/SRK_1_2_3_4_table.bin"
+    Source index = 0
+
+[Install CSFK]
+    # Key used to authenticate the CSF data
+    File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem"
+
+[Authenticate CSF]
+
+[Install Key]
+    # Key slot index used to authenticate the key to be installed
+    Verification index = 0
+    # Target key slot in HAB key store where key will be installed
+    Target index = 2
+    # Key to install
+    File = "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem"
+
+[Authenticate Data]
+    # Key slot index used to authenticate the image data
+    Verification index = 2
+    # Authenticate Start Address, Offset, Length and file
+    Blocks = 0x401fcdc0 0x057c00 0x01020 "flash.bin", \
+             0x40200000 0x05AC00 0x9AAC8 "flash.bin", \
+             0x00910000 0x0F56C8 0x09139 "flash.bin", \
+             0xFE000000 0x0FE804 0x4D268 "flash.bin", \
+             0x4029AAC8 0x14BA6C 0x06DCF "flash.bin"
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit_enc.txt b/doc/imx/habv4/csf_examples/mx8m/csf_fit_enc.txt
new file mode 100644
index 00000000000..be0b353084d
--- /dev/null
+++ b/doc/imx/habv4/csf_examples/mx8m/csf_fit_enc.txt
@@ -0,0 +1,49 @@
+[Header]
+    Version = 4.3
+    Hash Algorithm = sha256
+    Engine = CAAM
+    Engine Configuration = 0
+    Certificate Format = X509
+    Signature Format = CMS
+
+[Install SRK]
+    File = "../crts/SRK_1_2_3_4_table.bin"
+    Source index = 0
+
+[Install CSFK]
+    File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem"
+
+[Authenticate CSF]
+
+[Unlock]
+    Engine = CAAM
+    Features = MID
+
+[Install Key]
+    Verification index = 0
+    Target index = 2
+    File = "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem"
+
+[Authenticate Data]
+    Verification index = 2
+    Blocks = 0x401fcdc0 0x57c00 0x1020 "flash-spl-enc.bin"
+
+[Install Secret Key]
+    # Install the blob
+    Verification Index = 0
+    Target Index = 0
+    Key = "dek_fit.bin"
+    Key Length = 128
+    # Fixed address defined in imx-mkimage project in iMX8M/soc.mak file
+    # DEK_BLOB_LOAD_ADDR = 0x40400000
+    Blob Address = 0x40400000
+
+[Decrypt Data]
+    # The decrypt data command below causes CST to modify the input
+    # file and encrypt the specified block of data. This image file
+    # is a copy of the file used for the authentication command above
+    Verification Index = 0
+    Mac Bytes = 16
+    Blocks = 0x40200000 0x5AC00 0xB8940 "flash-spl-fit-enc.bin", \
+             0x920000 0x113540 0xA160 "flash-spl-fit-enc.bin", \
+             0xBE000000 0x11D6A0 0x48520 "flash-spl-fit-enc.bin"
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit_sign_enc.txt b/doc/imx/habv4/csf_examples/mx8m/csf_fit_sign_enc.txt
new file mode 100644
index 00000000000..9a41c8bb400
--- /dev/null
+++ b/doc/imx/habv4/csf_examples/mx8m/csf_fit_sign_enc.txt
@@ -0,0 +1,53 @@
+[Header]
+    Version = 4.3
+    Hash Algorithm = sha256
+    Engine = CAAM
+    Engine Configuration = 0
+    Certificate Format = X509
+    Signature Format = CMS
+
+[Install SRK]
+    File = "../crts/SRK_1_2_3_4_table.bin"
+    Source index = 0
+
+[Install CSFK]
+    File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem"
+
+[Authenticate CSF]
+
+[Unlock]
+    Engine = CAAM
+    Features = MID
+
+[Install Key]
+    Verification index = 0
+    Target index = 2
+    File = "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem"
+
+[Authenticate Data]
+    Verification index = 2
+    Blocks = 0x401fcdc0 0x57c00 0x1020 "flash-spl-fit-enc.bin", \
+             0x40200000 0x5AC00 0xB8940 "flash-spl-fit-enc.bin", \
+             0x920000 0x113540 0xA160 "flash-spl-fit-enc.bin", \
+             0xBE000000 0x11D6A0 0x48520 "flash-spl-fit-enc.bin"
+
+[Install Secret Key]
+    # Install the blob
+    Verification Index = 0
+    Target Index = 0
+    Key = "dek_fit_dummy.bin"
+    Key Length = 128
+    # Fixed address defined in imx-mkimage project in iMX8M/soc.mak file
+    # DEK_BLOB_LOAD_ADDR = 0x40400000
+    Blob Address = 0x40400000
+
+[Decrypt Data]
+    # The decrypt data command below causes CST to modify the input
+    # file and encrypt the specified block of data. This image file
+    # is a copy of the file used for the authentication command above
+    Verification Index = 0
+    Mac Bytes = 16
+    Blocks = 0x40200000 0x5AC00 0xB8940 "flash-spl-fit-enc-dummy.bin", \
+             0x920000 0x113540 0xA160 "flash-spl-fit-enc-dummy.bin", \
+             0xBE000000 0x11D6A0 0x48520 "flash-spl-fit-enc-dummy.bin"
+
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt b/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt
new file mode 100644
index 00000000000..39adf7a3eb8
--- /dev/null
+++ b/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt
@@ -0,0 +1,37 @@
+[Header]
+    Version = 4.3
+    Hash Algorithm = sha256
+    Engine = CAAM
+    Engine Configuration = 0
+    Certificate Format = X509
+    Signature Format = CMS
+
+[Install SRK]
+    # Index of the key location in the SRK table to be installed
+    File = "../crts/SRK_1_2_3_4_table.bin"
+    Source index = 0
+
+[Install CSFK]
+    # Key used to authenticate the CSF data
+    File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem"
+
+[Authenticate CSF]
+
+[Unlock]
+    # Leave Job Ring and DECO master ID registers Unlocked
+    Engine = CAAM
+    Features = MID
+
+[Install Key]
+    # Key slot index used to authenticate the key to be installed
+    Verification index = 0
+    # Target key slot in HAB key store where key will be installed
+    Target index = 2
+    # Key to install
+    File = "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem"
+
+[Authenticate Data]
+    # Key slot index used to authenticate the image data
+    Verification index = 2
+    # Authenticate Start Address, Offset, Length and file
+    Blocks = 0x7e0fc0 0x1a000 0x2a600 "flash.bin"
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_spl_enc.txt b/doc/imx/habv4/csf_examples/mx8m/csf_spl_enc.txt
new file mode 100644
index 00000000000..de71710e6c1
--- /dev/null
+++ b/doc/imx/habv4/csf_examples/mx8m/csf_spl_enc.txt
@@ -0,0 +1,50 @@
+[Header]
+    Version = 4.3
+    Hash Algorithm = sha256
+    Engine = CAAM
+    Engine Configuration = 0
+    Certificate Format = X509
+    Signature Format = CMS
+
+[Install SRK]
+    File = "../crts/SRK_1_2_3_4_table.bin"
+    Source index = 0
+
+[Install CSFK]
+    File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem"
+
+[Authenticate CSF]
+
+[Unlock]
+    Engine = CAAM
+    Features = MID
+
+[Install Key]
+    Verification index = 0
+    Target index = 2
+    File = "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem"
+
+[Authenticate Data]
+    Verification index = 2
+    Blocks = 0x7e0fc0 0x0 0x40 "flash.bin"
+
+[Install Secret Key]
+    # Install the blob
+    Verification Index = 0
+    Target Index = 0
+    Key = "dek_spl.bin"
+    Key Length = 128
+    # Authenticate Start Address +  SPL & DDR FW image length + CSF Padding
+    # 0x7E0FC0 + 0x2c400 + 0x2000
+    Blob Address = 0x80F3C0
+
+[Decrypt Data]
+    # The decrypt data command below causes CST to modify the input
+    # file and encrypt the specified block of data. This image file
+    # is a copy of the file used for the authentication command above
+    Verification Index = 0
+    Mac Bytes = 16
+    # Start Address = Start Address + SPL header = 0x7E0FC0 + 0x40 = 0x7E1000
+    # Offset = Image offset (image_off) = 0x40
+    # Decrypt size = Image length - SPL header = 0x2c400 - 0x40 = 0x2C3C0
+    Blocks = 0x7E1000 0x40 0x2C3C0 "flash-spl-enc.bin"
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_spl_sign_enc.txt b/doc/imx/habv4/csf_examples/mx8m/csf_spl_sign_enc.txt
new file mode 100644
index 00000000000..b1b8db1a62f
--- /dev/null
+++ b/doc/imx/habv4/csf_examples/mx8m/csf_spl_sign_enc.txt
@@ -0,0 +1,47 @@
+[Header]
+    Version = 4.3
+    Hash Algorithm = sha256
+    Engine = CAAM
+    Engine Configuration = 0
+    Certificate Format = X509
+    Signature Format = CMS
+
+[Install SRK]
+    File = "../crts/SRK_1_2_3_4_table.bin"
+    Source index = 0
+
+[Install CSFK]
+    File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem"
+
+[Authenticate CSF]
+
+[Unlock]
+    Engine = CAAM
+    Features = MID
+
+[Install Key]
+    Verification index = 0
+    Target index = 2
+    File = "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem"
+
+[Authenticate Data]
+    Verification index = 2
+    Blocks = 0x7E0FC0 0x0 0x2C400 "flash-spl-enc.bin"
+
+[Install Secret Key]
+    # Install the blob
+    Verification Index = 0
+    Target Index = 0
+    Key = "dek_spl_dummy.bin"
+    Key Length = 128
+    # Authenticate Start Address +  Image length + CSF Padding
+    # 0x7E0FC0 + 0x2c400 + 0x2000
+    Blob Address = 0x80F3C0
+
+[Decrypt Data]
+    # The decrypt data command below causes CST to modify the input
+    # file and encrypt the specified block of data. This image file
+    # is a copy of the file used for the authentication command above
+    Verification Index = 0
+    Mac Bytes = 16
+    Blocks = 0x7E1000 0x40 0x2C3C0 "flash-spl-enc-dummy.bin"
diff --git a/doc/imx/habv4/guides/encrypted_boot.txt b/doc/imx/habv4/guides/encrypted_boot.txt
index e2b435749e3..5e1ea3ac5d7 100644
--- a/doc/imx/habv4/guides/encrypted_boot.txt
+++ b/doc/imx/habv4/guides/encrypted_boot.txt
@@ -30,8 +30,9 @@ example: dek_blob 0x10800000 0x10801000 192
 
 The resulting DEK blob then is used to construct the encrypted
 U-Boot image. Note that the blob needs to be transferred back
-to the host.Then the following commands are used to construct
-the final image.
+to the host. This process and additional configuration enablement
+needed is detailed in the target board's encrypted_boot documentation.
+Then the following commands are used to construct the final image.
 
 cat u-boot-dtb.imx csf-u-boot.bin > u-boot-signed.imx
 objcopy -I binary -O binary --pad-to <blob_dst> --gap-fill=0x00 \
diff --git a/doc/imx/habv4/guides/mx6_mx7_encrypted_boot.txt b/doc/imx/habv4/guides/mx6_mx7_encrypted_boot.txt
new file mode 100644
index 00000000000..f1a8406379a
--- /dev/null
+++ b/doc/imx/habv4/guides/mx6_mx7_encrypted_boot.txt
@@ -0,0 +1,281 @@
++==========================================================+
++   i.MX6, i.MX7 U-Boot Encrypted Boot guide using HABv4   +
++==========================================================+
+
+1. HABv4 Encrypted Boot process
+-------------------------------
+
+This document describes a step-by-step procedure on how to encrypt and
+sign an U-Boot image. It is assumed that the reader is familiar
+with basic HAB concepts and has already followed the mx6_mx7_secure_boot.txt
+guide and got a working closed device.
+
+Details about HAB and encrypted boot process can be found in application
+notes AN4581[1] and AN12056[2] and in the introduction_habv4.txt document.
+
+Before continuing, be sure to have fatwrite and dek_blob commands
+available in U-Boot. If not, enable them in Kconfig and rebuild
+U-Boot:
+
+- Defconfig
+
+  CONFIG_FAT_WRITE=y
+  CONFIG_CMD_DEKBLOB=y
+  CONFIG_CMD_PRIBLOB=y
+
+- Kconfig
+
+  File systems -> Enable FAT filesystem support-> Enable FAT filesystem
+  write support
+  ARM architecture -> Support the 'dek_blob' command
+  ARM architecture -> Support the set_priblob_bitfield command
+
+1.1 Building an encrypted U-Boot image
+--------------------------------------
+
+This U-Boot is built the same way the one from the secure document is,
+so it provides the same access the the HAB APIs, extra functions
+for HAB, etc...
+
+However, the layout of the new image is different, as a part of it is
+encrypted, and a DEK blob is appended at the end. The diagram below
+illustrates an encrypted u-boot-dtb.imx image layout:
+
+  ----------------------- +-----------------------------+ <--- *start
+         ^            ^   |      Image Vector Table     |
+         |            |   +-----------------------------+ <--- *boot_data
+         |            |   |          Boot Data          |
+         |      Plain |   +-----------------------------+ <--- *dcd
+         |       text |   |          DCD Table          |
+         |            |   +-----------------------------+
+  Signed |            v   |           Padding           |
+   data  |        ------- +-----------------------------+ <--- *entry
+         |            ^   |                             |
+         |            |   |                             |
+         |  Encrypted |   |        u-boot-dtb.bin       |
+         |       data |   |                             |
+         |            |   |                             |
+         |            |   +-----------------------------+
+         v            v   |           Padding           |
+  ----------------------- +-----------------------------+ <--- *csf
+                      ^   |    Command Sequence File    |
+               0x2000 |   |   (commands + SRK table +   |
+           (in bytes) |   | signatures + certificates + |
+                      v   |        Nonce + MAC)         |
+                  ------- +-----------------------------+
+                          |           Padding           |
+                          +-----------------------------+ <--- *csf + 0x2000
+                          |           DEK Blob          |
+                          +-----------------------------+
+                          |           Padding           |
+                          +-----------------------------+
+
+1.2 Get a secure boot working
+-----------------------------
+
+You need to go through all the steps described into the
+mx6_mx7_secure_boot.txt guide, and get a signed U-Boot which can
+boot successfully on a closed target. Otherwise, the following
+steps will not work.
+
+1.3 Compile the CST to enable the encrypting feature
+----------------------------------------------------
+
+CST version 3.0.0 and later have the encryption feature enabled by default.
+If using an earlier version, the encryption feature must be explicitly
+enabled.
+
+For CST versions <3.0.0, the CST backend must be recompiled, execute the
+following commands to enable encryption support in CST:
+
+  $ sudo apt-get install libssl-dev openssl
+  $ cd <CST install directory>/code/back_end/src
+  $ gcc -o cst_encrypted -I ../hdr -L ../../../linux64/lib *.c
+    -lfrontend -lcrypto
+  $ cp cst_encrypted ../../../<where your original CST executable is>
+
+1.4 Creating the CSF description files
+--------------------------------------
+
+The CSF contains all the commands that the ROM executes during the
+secure boot. These commands instruct the HAB on which memory areas
+of the image to authenticate, which keys to install, use, etc...
+
+CSF examples for encrypted boot are available under
+doc/imx/hab/habv4/csf_examples/ directory.
+
+For both CSF, first part is same compared to the CSF used for
+the secure boot step.
+Here we describe how to encrypt the U-Boot image and then sign it.
+
+1.4.1 csf_u-boot_enc.txt
+-------------------------
+
+This first CSF is used to encrypt the U-Boot image and generate the
+dek.bin file. The Authenticate Data command has to be modified, and
+two new commands have to be added:
+
+- Modify the Authenticate Data command to only cover IVT and DCD:
+
+  Blocks = 0x877ff400 0x00000000 0x00000c00 "u-boot-dtb.imx"
+
+- Add the new Install Secret Key command to generate the dek.bin
+  file and install the blob. The parameter which depends of your
+  configuration is the Blob Address. Padding of 0x2000 is
+  recommended. Following the csf_uboot.txt data for instance:
+
+  Blob Address = Authenticate Start Address + Padding + length
+               = 0x877ff400 + 0x2000 + 0x9ec00 = 0x878a0000
+
+- Add the new Decrypt Data command to encrypt the file. As the file
+  specified in parameter will be modified, we suggest to copy it.
+  Then modify the Blocks command depending of your U-Boot image.
+  In our example:
+
+  $ cp u-boot-dtb.imx u-boot-dtb.imx-enc
+  Block = (Authenticate start addr + 0xc00) 0xc00 (length - 0xc00)
+          u-boot-dtb.imx-enc
+        = (0x877ff400 + 0xc00) 0xc00 (0x9ec00 - 0xc00)
+          u-boot-dtb.imx-enc
+        = 0x87800000 0xc00 0x9e000 u-boot-dtb.imx-enc
+
+1.4.2 csf_u-boot_sign_enc.txt
+-----------------------------
+
+This second CSF is used to sign the encrypted U-Boot image previously
+generated (u-boot-dtb.imx-enc). The Authenticate Data part has also
+to be changed, the modifications are the following:
+
+- The Authenticate Data command is same compared to the one in
+  csf_uboot.txt file, except that this time, the file parameter
+  is the file previously encrypted: u-boot-dtb.imx-enc.
+
+  Blocks = 0x877ff400 0x000 0x0009ec00 "u-boot-dtb.imx-enc"
+
+- For the two new commands, we do not want to they modify our previously
+  signed/generated files. Therefore, for the Key parameter of the
+  Install Secret Key command, the value is now dek-dummy.bin, which
+  will generate a new dek file instead of erasing the previous one.
+  About the decrypt data command, you need to copy the u-boot-dtb.imx
+  file again in a u-boot-dtb.imx-dummy file, to not replace the
+  original encrypted file with an encrypted one:
+
+  Key = "dek-dummy.bin"
+  Blocks = 0x87800000 0x00000c00 0x9e000 "u-boot-dtb.imx-dummy"
+
+1.5 Encrypt the U-Boot image
+----------------------------
+
+The image is encrypted using the Code Signing Tool. It generates also
+a CSF binary and a dek.bin file, which will be used on the future
+steps below.
+
+- Create the CSF binary file and encrypt the U-Boot image
+
+  $ ./cst_encrypted -i csf_u-boot_enc.txt -o csf_u-boot_enc.bin
+
+1.6 Sign the encrypted U-Boot image
+-----------------------------------
+
+The image is then signed using the Code Signing Tool. It also
+generate a CSF binary, which will be used on the future steps below.
+
+- Create the CSF binary file and sign the encrypted U-Boot image
+
+  $ ./cst_encrypted -i csf_u-boot_sign_enc.txt -o csf_u-boot_sign_enc.bin
+
+1.7 Swap Nonce/MAC from csf_u-boot_enc.bin to csf_u-boot_sign_enc.bin
+---------------------------------------------------------------------
+
+First, calculate Nonce/MAC size based on MAC bytes value
+in CSF. As Mac bytes is 16:
+
+  Nonce/MAC size = Nonce size + MAC bytes + CSF header for Nonce/Mac
+                 = 12 + 16 + 8 = 36 bytes
+
+Then, calculate Nonce/MAC offset in CSF:
+
+  MAC offset = csf_u-boot-enc.bin size - Nonce/MAC size
+             = 3972 - 36 = 3936 Bytes
+
+In the next step, extract Nonce/NAC from the first CSF:
+
+  $ dd if=csf_u-boot_enc.bin of=noncemac.bin bs=1 skip=3936 count=36
+
+Finally, replace the MAC of csf_u-boot_sign_enc.bin with the extracted
+one:
+
+  $ dd if=noncemac.bin of=csf_u-boot_sign_enc.bin bs=1 seek=3936 count=36
+
+1.8 Generate encryptedu-boot with no dek
+----------------------------------------
+
+As described in the layout in the first part of this document, the
+final image is composed of these different parts padded to known
+values, to make it compliant with the CSF.
+
+First, pad the CSF to 0x2000:
+
+  $ objcopy -I binary -O binary --pad-to 0x2000 --gap-fill=0xff
+  csf_u-boot_sign_enc.bin csf_u-boot_sign_enc_padded.bin
+
+Then, append this file to the encrypted U-Boot image:
+
+  $ cat u-boot-dtb.imx-enc csf_u-boot_sign_enc_padded.bin >
+  u-boot_encrypted_no_dek.bin
+
+Pad this new file to width+offset (0x9ec00 + 0x2000 = 0xa0c00):
+
+  $ objcopy -I binary -O binary --pad-to 0xa0c00 --gap-fill=0x00
+  u-boot_encrypted_no_dek.bin u-boot_encrypted_no_dek_padded.bin
+
+1.9 Generate the DEK Blob
+-------------------------
+The missing part to get our final U-Boot encrypted image is a DEK
+blob. To generate it, copy the dek.bin file generated at step 1.5
+on the Boot partition of your SD Card. Then interrupt the boot
+and your chip. You need the fatwrite and dek_blob command, which
+should be enabled by the secure boot. If not, you have to enable
+them in Kconfig and recompile U-Boot
+
+Run the following commands:
+
+  => mmc list
+  FSL_SDHC: 0 (SD)   #index to use for mmc in following commands
+  => fatload mmc 0 0x80800000 dek.bin
+  => dek_blob 0x80800000 0x80801000 128
+  => fatwrite mmc 0 0x80801000 dek_blob.bin 0x48
+
+1.10 Finalize the encrypted U-Boot image
+----------------------------------------
+
+Finally, copy the generated dek_blob.bin file from your SDCard to
+your CST repository. Append it with the last padded file to get your
+final image:
+
+  $ cat u-boot_encrypted_no_dek_padded.bin dek_blob.bin >
+  u-boot_encrypted.bin
+
+If the image does not boot, please verify the size of your
+U-Boot image, the length specified into CSF and the padding values.
+
+2. About the PRIBLOB bitfield from CAAM SCFGR register
+------------------------------------------------------
+
+It is highly recommended to set the PRIBLOB bitfield from the CAAM
+SCFGR register to 0x3 once your encrypted U-Boot image is completed.
+To do so, a command has been implemented in u-boot:
+
+  => set_priblob_bitfield
+
+Once this bitfield is set to 0x3, it ensures cryptographic separation
+of private blob types avoiding any modification or replacement of
+DEK blobs. Newly created blobs will be incompatible with blobs
+required to decrypt an encrypted boot image. When the HAB later
+executes the command to decrypt the DEK, an incompatible DEK blob
+will be detected and cause an error. A substitute encrypted boot image
+will not be decrypted, and will not be executed.
+
+References:
+[1] AN4581: "i.MX Secure Boot on HABv4 Supported Devices"
+[2] AN12056: "Encrypted Boot on HABv4 and CAAM Enabled Devices"
diff --git a/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt b/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt
index 53f71fbc3e2..e7a7317303d 100644
--- a/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt
+++ b/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt
@@ -68,12 +68,20 @@ build configuration:
 
   ARM architecture -> Support i.MX HAB features
 
+The U-Boot image must then be recompiled after these changes are made.
+
 1.3 Creating the CSF description file
 --------------------------------------
 
 The CSF contains all the commands that the HAB executes during the secure
 boot. These commands instruct the HAB on which memory areas of the image
-to authenticate, which keys to install, use and etc.
+to authenticate, which keys to install, use and etc. More information
+on constructing a CSF file can be found in the CST User Guide, located
+within the CST package's doc directory.
+
+Key and Certificate generation done by the CST is out of the scope of
+this document. Please refer to introduction_habv4.txt for keys,
+certificates, SRK table, and SRK hash generation.
 
 CSF examples are available under doc/imx/habv4/csf_examples/ directory.
 
@@ -108,7 +116,28 @@ the U-Boot build, the example below is a log for mx7dsabresd_defconfig target:
 - In "Authenticate Data" CSF command users can copy and past the output
   addresses:
 
-  Block = 0x877ff400 0x00000000 0x0009ec00 "u-boot-dtb.imx"
+  For example:
+
+  [Authenticate Data]
+    ...
+    Block = 0x877ff400 0x00000000 0x0009ec00 "u-boot-dtb.imx"
+
+1.3.1 Avoiding Kernel crash when OP-TEE is enabled
+---------------------------------------------------
+
+For devices prior to HAB v4.4.0, the HAB code locks the Job Ring and DECO
+master ID registers in HAB closed configuration. In case the user specific
+application requires any changes in CAAM MID registers it's necessary to
+add the "Unlock CAAM MID" command in CSF file.
+
+The current NXP OP-TEE implementation expects the CAAM registers to be unlocked
+when configuring CAAM to operate in non-secure TrustZone world.
+
+- Add Unlock MID command in CSF:
+
+  [Unlock]
+      Engine = CAAM
+      Features = MID
 
 1.4 Signing the U-Boot binary
 ------------------------------
@@ -133,6 +162,10 @@ media.
 
   $ sudo dd if=u-boot-signed.imx of=/dev/sd<x> bs=1K seek=1 && sync
 
+Note: The Universal Update Utility (UUU) can also be used to flash the
+image to the target board's eMMC. Details on UUU installation and help
+can be found in the supporting UUU documentation[3].
+
 1.5 Programming SRK Hash
 -------------------------
 
@@ -142,6 +175,9 @@ SoC SRK_HASH[255:0] fuses.
 
 Be careful when programming these values, as this data is the basis for the
 root of trust. An error in SRK Hash results in a part that does not boot.
+More information and full details regarding fuses can be found in the
+Security Reference Manual of the target board. Contact an NXP Representative
+for access.
 
 The U-Boot fuse tool can be used for programming eFuses on i.MX SoCs.
 
@@ -325,7 +361,13 @@ and word according to the i.MX device:
               | i.MX7ULP     | bank 1 word 1 | 0x000000C0 |
               +--------------+---------------+------------+
 
-2. Extending the root of trust
+2. Secure boot in SDP mode
+---------------------------
+
+For secure boot in SDP mode, please refer to the "HABv4 closed chip support"
+chapter in the UUU documentation[3].
+
+3. Extending the root of trust
 -------------------------------
 
 The High Assurance Boot (HAB) code located in the on-chip ROM provides an
@@ -359,7 +401,7 @@ The diagram below illustrate the zImage layout:
                     |     Padding (optional)      |
                     +-----------------------------+
 
-2.1 Padding the image
+3.1 Padding the image
 ----------------------
 
 The zImage must be padded to the next boundary address (0x1000), for instance
@@ -372,7 +414,7 @@ The tool objcopy can be used for padding the image.
   $ objcopy -I binary -O binary --pad-to 0x64A000 --gap-fill=0x00 \
 	zImage zImage_pad.bin
 
-2.2 Generating Image Vector Table
+3.2 Generating Image Vector Table
 ----------------------------------
 
 The HAB code requires an Image Vector Table (IVT) for determining the image
@@ -390,7 +432,7 @@ Note: The load Address may change depending on the device.
 
   $ cat zImage_pad.bin ivt.bin > zImage_pad_ivt.bin
 
-2.3 Signing the image
+3.3 Signing the image
 ----------------------
 
 A CSF file has to be created to sign the image. HAB does not allow to change
@@ -408,7 +450,7 @@ directory.
 
   $ cat zImage_pad_ivt.bin csf_zImage.bin > zImage_signed.bin
 
-2.4 Verifying HAB events
+3.4 Verifying HAB events
 -------------------------
 
 The U-Boot includes the hab_auth_img command which can be used for
@@ -422,6 +464,6 @@ loaded at the load address specified in the IVT.
 If no HAB events were found the zImage is successfully signed.
 
 References:
-[1] AN4581: "Secure Boot on i.MX 50, i.MX 53, i.MX 6 and i.MX 7 Series using
- HABv4" - Rev 2.
-[2] AN12263: "HABv4 RVT Guidelines and Recommendations" - Rev 0.
+[1] AN4581: "i.MX Secure Boot on HABv4 Supported Devices"
+[2] AN12263: "HABv4 RVT Guidelines and Recommendations"
+[3] https://github.com/NXPmicro/mfgtools/releases/
diff --git a/doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt b/doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt
index fde0f27efdc..b0232384717 100644
--- a/doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt
+++ b/doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt
@@ -93,12 +93,20 @@ build configuration:
 
   ARM architecture -> Support i.MX HAB features
 
+The U-Boot image must then be recompiled after these changes are made.
+
 1.3 Creating the CSF description file
 --------------------------------------
 
 The CSF contains all the commands that the HAB executes during the secure
 boot. These commands instruct the HAB code on which memory areas of the image
-to authenticate, which keys to install, use and etc.
+to authenticate, which keys to install, use etc. More information
+on constructing a CSF file can be found in the CST User Guide, located
+within the CST package's doc directory.
+
+Key and Certificate generation done by the CST is out of the scope of
+this document. Please refer to introduction_habv4.txt for keys,
+certificates, SRK table, and SRK hash generation.
 
 CSF examples are available under doc/imx/habv4/csf_examples/ directory.
 
@@ -136,11 +144,19 @@ addresses, the csf_uboot.txt can be used as example:
 
 - In csf_SPL.txt:
 
-  Block = 0x00907400 0x00000000 0x0000ec00 "SPL"
+  For example:
+
+  [Authenticate Data]
+    ...
+    Block = 0x00907400 0x00000000 0x0000ec00 "SPL"
 
 - In csf_uboot-ivt.txt:
 
-  Block = 0x177fffc0 0x0000 0x0006e020 "u-boot-ivt.img"
+  For example:
+
+  [Authenticate Data]
+    ...
+    Block = 0x177fffc0 0x0000 0x0006e020 "u-boot-ivt.img"
 
 1.4 Signing the images
 -----------------------
@@ -176,6 +192,12 @@ complete procedure please refer to section "1.5 Programming SRK Hash" in
 mx6_mx7_secure_boot.txt document available under doc/imx/habv4/guides/
 directory.
 
+2. Secure boot in SDP mode
+---------------------------
+
+For secure boot in SDP mode, please refer to the "HABv4 closed chip support"
+chapter in the UUU documentation[2].
+
 References:
-[1] AN4581: "Secure Boot on i.MX 50, i.MX 53, i.MX 6 and i.MX 7 Series using
- HABv4" - Rev 2.
+[1] AN4581: "i.MX Secure Boot on HABv4 Supported Devices"
+[2] https://github.com/NXPmicro/mfgtools/releases/
diff --git a/doc/imx/habv4/guides/mx8m_encrypted_boot.txt b/doc/imx/habv4/guides/mx8m_encrypted_boot.txt
new file mode 100644
index 00000000000..bb9b6b80f05
--- /dev/null
+++ b/doc/imx/habv4/guides/mx8m_encrypted_boot.txt
@@ -0,0 +1,567 @@
+         +======================================================+
+         +    i.MX8M family Encrypted Boot guide using HABv4    +
+         +======================================================+
+
+1. HABv4 Encrypted Boot process
+-------------------------------
+
+This document describes a step-by-step procedure on how to encrypt and sign a
+bootloader image for i.MX8M family devices. It is assumed that the reader is
+familiar with basic HAB concepts and has already closed the device, step-by-step
+procedure can be found in mx8m_secure_boot.txt guide.
+
+Details about encrypted boot can be found in application note AN12056[1] and
+in the introduction_habv4.txt document.
+
+The steps described in this document were based in i.MX8MM device, the same
+concept can be applied to other i.MX8M family devices.
+
+1.1 Understanding the encrypted flash.bin image layout
+------------------------------------------------------
+
+As described in mx8m_secure_boot.txt guide a single binary is used to boot the
+device, the imx-mkimage tool combines all the input images in a FIT structure,
+generating a flash.bin binary.
+
+The encrypted boot image requires a DEK (Data Encryption Key) blob on each time
+HABv4 is used to decrypt an image. The DEK blob is used as a security layer to
+wrap and store the DEK off-chip using the OTPMK which is unique per device.
+More details can be found in AN12056 application note.
+
+The diagram below illustrates an encrypted flash.bin image layout:
+
+                     +-----------------------------+
+                     |                             |
+                     |     *Signed HDMI/DP FW      |
+                     |                             |
+                     +-----------------------------+
+                     |           Padding           |
+  ------------------ +-----------------------------+ --------
+        ^            |          IVT - SPL          |   ^
+ Signed |    ------- +-----------------------------+   |
+  Data  |    Enc  ^  |        u-boot-spl.bin       |   |
+        |    Data |  |              +              |   |  SPL
+        v         v  |           DDR FW            |   | Image
+  ------------------ +-----------------------------+   |
+                     |      CSF - SPL + DDR FW     |   v
+                     +-----------------------------+ --------
+                     |           DEK Blob          |
+                     +-----------------------------+
+                     |           Padding           |
+             ------- +-----------------------------+ --------
+          Signed ^   |          FDT - FIT          |   ^
+           Data  |   +-----------------------------+   |
+                 v   |          IVT - FIT          |   |
+             ------- +-----------------------------+   |
+                     |          CSF - FIT          |   |
+  ------------------ +-----------------------------+   |
+                ^    |       u-boot-nodtb.bin      |   | FIT
+                |    +-----------------------------+   | Image
+    Signed and  |    |          u-boot.dtb         |   |
+     Encrypted  |    +-----------------------------+   |
+          Data  |    |        bl31.bin (ATF)       |   |
+                |    +-----------------------------+   |
+                v    |            OP-TEE           |   |
+  ------------------ +-----------------------------+   |
+                     |           DEK Blob          |   v
+                     +-----------------------------+ --------
+  * Only supported on i.MX8M series
+
+1.2 Enabling the encrypted boot support in U-Boot
+--------------------------------------------------
+
+For deploying an encrypted boot image additional U-Boot tools are needed,
+please be sure to have the following features enabled, this can be achieved
+by following one of the methods below:
+
+- Defconfig
+
+  CONFIG_IMX_HAB=y
+  CONFIG_FAT_WRITE=y
+  CONFIG_CMD_DEKBLOB=y
+  CONFIG_IMX_OPTEE_DEK_ENCAP=y
+  CONFIG_CMD_PRIBLOB=y
+
+- Kconfig
+
+  ARM architecture -> Support i.MX HAB features
+  ARM architecture -> Support the 'dek_blob' command
+  ARM architecture -> Support the set_priblob_bitfield command
+  File systems -> Enable FAT filesystem support-> Enable FAT filesystem
+                  write support
+
+The U-Boot image must then be recompiled after these changes are made.
+
+1.3 Enabling the encrypted boot support in CST
+----------------------------------------------
+CST version 3.0.0 and later have the encryption feature enabled by default.
+If using an earlier version, the encryption feature must be explicitly
+enabled.
+
+For CST versions <3.0.0, the CST backend must be recompiled, execute the
+following commands to enable encryption support in CST:
+
+  $ sudo apt-get install libssl-dev openssl
+  $ cd <CST install directory>/code/back_end/src
+  $ gcc -o cst_encrypted -I ../hdr -L ../../../linux64/lib *.c
+    -lfrontend -lcrypto
+  $ cp cst_encrypted ../../../linux64/bin/
+
+1.4 Building OP-TEE and ATF to support DEK blob tool
+-----------------------------------------------------
+
+The DEK blob must be created by a software running in Arm TrustZone Secure
+World, the CAAM block takes into consideration the TrustZone configuration
+when encapsulating the DEK and the resulting blob can be only decapsulated
+by a SW running in the same configuration. As ROM code is running in ARM
+TrustZone secure world we must encapsulate the blobs using OP-TEE.
+
+- Building ATF to support OP-TEE:
+
+  $ make PLAT=<SoC Name> SPD=opteed bl31
+
+- Building OP-TEE to support DEK blob encapsulation:
+
+  $ CFG_NXPCRYPT=y CFG_GEN_DEK_BLOB=y source ./scripts/nxp_build.sh <Board Name>
+
+* OP-TEE debug logs can be enabled by adding CFG_TEE_CORE_LOG_LEVEL=4 in
+  command line above.
+
+Note: If a Make error is encountered while building ATF, make sure the compilation
+environment is set up properly and then try the following command to resolve
+persistent errors:
+
+  $ unset LDFLAGS
+
+1.5 Preparing the fit image
+----------------------------
+
+As explained in mx8m_secure_boot.txt document the imx-mkimage project is used to
+combine all the images in a single flash.bin binary.
+
+Copy all the binaries generated (U-Boot images, bl31.bin, tee.bin and Firmware)
+into iMX8M directory and run the following commands according to the target
+device:
+
+- Create a dummy DEK blob:
+
+  $ dd if=/dev/zero of=iMX8M/dek_blob_fit_dummy.bin bs=96 count=1 && sync
+
+- Assembly flash.bin binary:
+
+  $ make SOC=<SoC Name> flash_spl_uboot
+
+The mkimage log will be used during the encrypted boot procedure to create the
+Command Sequence File (CSF):
+
+- imx-mkimage build log:
+
+  Loader IMAGE:
+   header_image_off 	0x0
+   dcd_off 		0x0
+   image_off 		0x40
+   csf_off 		0x2c400
+   spl hab block: 	0x7e0fc0 0x0 0x2c400
+
+  Second Loader IMAGE:
+   sld_header_off 	0x57c00
+   sld_csf_off 		0x58c20
+   sld hab block: 	0x401fcdc0 0x57c00 0x1020
+
+- Additional HAB information is provided by running the following command:
+
+  $ make SOC=<SoC Name> print_fit_hab
+
+  ./../scripts/pad_image.sh bl31.bin
+  ./../scripts/pad_image.sh u-boot-nodtb.bin fsl-imx8mm-evk.dtb
+  TEE_LOAD_ADDR=0xbe000000 ATF_LOAD_ADDR=0x00920000 VERSION=v1 \
+  ./print_fit_hab.sh 0x60000 fsl-imx8mm-evk.dtb
+  0x40200000 0x5AC00 0xB0318
+  0x402B0318 0x10AF18 0x8628
+  0x920000 0x113540 0xA160
+  0xBE000000 0x11D6A0 0x48520
+
+1.6 Creating the CSF description file for SPL + DDR FW image
+-------------------------------------------------------------
+
+The CSF contains all the commands that the ROM executes during the secure boot.
+These commands instruct the HAB on which memory areas of the image to
+authenticate and/or decrypt, which keys to install, use, etc...
+
+CSF examples for encrypted boot are available under
+doc/imx/hab/habv4/csf_examples/ directory.
+
+With current CST implementation is not possible to encrypt and sign an image
+at the same time, hence two CSF files are required on each time HAB is used.
+
+1.6.1 csf_spl_enc.txt
+----------------------
+
+The first CSF is used to encrypt the SPL and DDR FW images and generate the
+dek_spl.bin file. The Authenticate Data command has to cover only the image
+header and two commands have to be added to encrypt the image.
+
+- Add the Authenticate Data command to only cover SPL IVT and boot data:
+
+  For example:
+
+  [Authenticate Data]
+    ...
+    Blocks = 0x7E0FC0 0x0 0x40 "flash.bin"
+
+- Add the Install Secret Key command to generate the dek_spl.bin file and
+  install the blob. The Blob Address depends on your image layout and can
+  be calculated as following:
+
+  For example:
+
+  [Install Secret Key]
+    ...
+    Key = "dek_spl.bin"
+    # Blob Address = Authenticate Start Address +  Image length + CSF Padding
+    #              = 0x7E0FC0 + 0x2c400 + 0x2000 = 0x80F3C0
+    Blob Address = 0x80F3C0
+
+- Add the Decrypt Data command to encrypt the file. As SPL image header
+  cannot be encrypted we need to calculate the Block as following:
+
+  Start Address = Start Address + SPL header = 0x7E0FC0 + 0x40 = 0x7E1000
+  Offset = Image offset (image_off) = 0x40
+  Decrypt size = Image length - SPL header = 0x2C400 - 0x40 = 0x2C3C0
+
+  For example:
+
+  [Decrypt Data]
+    ...
+    Blocks = 0x7E1000 0x40 0x2C3C0 "flash-spl-enc.bin"
+
+1.6.2 csf_spl_sign_enc.txt
+---------------------------
+
+The second CSF is used to sign the encrypted SPL image previously generated
+(flash-spl-enc.bin).
+
+- The Authenticate Data command should cover the entire SPL and DDR FW image,
+  the file parameter is the encrypted image flash-spl-enc.bin:
+
+  For example:
+
+  [Authenticate Data]
+    ...
+    Blocks = 0x7E0FC0 0x0 0x2C400 "flash-spl-enc.bin"
+
+- Add the Install Secret Key command to generate a dummy DEK blob file,
+  the blob address should be the same as used in csf_spl_enc.txt:
+
+  For example:
+
+  [Install Secret Key]
+    ...
+    Key = "dek_spl_dummy.bin"
+    Blob Address = 0x80F3C0
+
+- Add the Decrypt Data command to encrypt the file. As image was encrypted
+  in CSF above we need to encrypt a dummy file, the block addresses should be
+  the same as used in csf_spl_enc.txt:
+
+  For example:
+
+  [Decrypt Data]
+    ...
+    Blocks = 0x7E1000 0x40 0x2C3C0 "flash-spl-enc-dummy.bin"
+
+1.7 Encrypting and signing the SPL + DDR FW image
+--------------------------------------------------
+
+The CST is used to encrypt the image and regenerate a random DEK. During this
+step two CSF binaries are generated but only one will be included in final
+image.
+
+- Encrypt the SPL + DDR FW image:
+
+  $ cp flash.bin flash-spl-enc.bin
+  $ ./cst_encrypted -i csf_spl_enc.txt -o csf_spl_enc.bin
+
+- Sign the encrypted SPL + DDR FW image:
+
+  $ cp flash-spl-enc.bin flash-spl-enc-dummy.bin
+  $ ./cst_encrypted -i csf_spl_sign_enc.txt -o csf_spl_sign_enc.bin
+
+1.7.1 Create final CSF binary for SPL + DDR FW image
+-----------------------------------------------------
+
+As only one CSF binary will be included in final image it's necessary to
+swap Nonce/MAC from csf_spl_enc.bin to csf_spl_sign_enc.bin.
+
+- Calculate Nonce/MAC size based on MAC bytes value in CSF:
+
+  Nonce/MAC size = Nonce size + MAC bytes + CSF header for Nonce/Mac
+                 = 12 + 16 + 8 = 36 bytes
+
+- Calculate Nonce/MAC offset in CSF:
+
+  MAC offset = csf_spl_enc.bin size - Nonce/MAC size
+             = 3980 - 36 = 3944 Bytes
+
+- Extract Nonce/MAC from csf_spl_enc.bin:
+
+  $ dd if=csf_spl_enc.bin of=noncemac.bin bs=1 skip=3944 count=36
+
+- Replace the MAC of csf_spl_sign_enc with the one extracted above:
+
+  $ dd if=noncemac.bin of=csf_spl_sign_enc.bin bs=1 seek=3944 count=36
+
+1.8 Creating the CSF description file for FIT image
+----------------------------------------------------
+
+Similar to SPL image two CSF files are required encrypt and sign the FIT
+image.
+
+Please note that the steps below are using the flash-spl-enc.bin image created
+in steps above.
+
+1.8.1 csf_fit_enc.txt
+----------------------
+
+The first CSF is used to encrypt the FIT image and generate the dek_fit.bin
+file.
+
+- Modify the Authenticate Data command to only cover FIT image FDT header:
+
+  For example:
+
+  [Authenticate Data]
+    ...
+    Blocks = 0x401FCDC0 0x57C00 0x1020 "flash-spl-enc.bin"
+
+- Add the Install Secret Key command to generate the dek_fit.bin file and
+  install the blob. The Blob Address is a fixed address defined in imx-mkimage
+  project in iMX8M/soc.mak file:
+
+  iMX8M/soc.mak:
+    DEK_BLOB_LOAD_ADDR = 0x40400000
+
+  For example:
+
+  [Install Secret Key]
+    ...
+    Key = "dek_fit.bin"
+    Blob Address = 0x40400000
+
+- Add the Decrypt Data command to encrypt the file.
+
+  The CST can only encrypt images that are 16 bytes aligned, as u-boot-nodtb.bin
+  and u-boot.dtb are together 16 bytes aligned we should consider the first two
+  lines provided in print_fit_hab as a single block.
+
+  imx-mkimage output:
+
+    0x40200000 0x5AC00 0xB0318 ──┬── Total length = 0xB0318 + 0x8628 = 0xB8940
+    0x402B0318 0x10AF18 0x8628 ──┘
+    0x920000 0x113540 0xA160
+    0xBE000000 0x11D6A0 0x48520
+
+  Decrypt data in csf_fit_enc.txt:
+
+  For example:
+
+  [Decrypt Data]
+    ...
+    Blocks = 0x40200000 0x5AC00 0xB8940 "flash-spl-fit-enc.bin", \
+             0x920000 0x113540 0xA160 "flash-spl-fit-enc.bin", \
+             0xBE000000 0x11D6A0 0x48520 "flash-spl-fit-enc.bin"
+
+1.8.2 csf_fit_sign_enc.txt
+---------------------------
+
+The second CSF is used to sign the encrypted FIT image previously generated
+(flash-spl-fit-enc.bin).
+
+- The Authenticate Data command should cover the entire FIT image,
+  the file parameter is the encrypted FIT image flash-spl-fit-enc.bin:
+
+  For example:
+
+  [Authenticate Data]
+    ...
+    Blocks = 0x401fcdc0 0x57c00 0x1020 "flash-spl-fit-enc.bin"
+	     0x40200000 0x5AC00 0xB8940 "flash-spl-fit-enc.bin", \
+             0x920000 0x113540 0xA160 "flash-spl-fit-enc.bin", \
+             0xBE000000 0x11D6A0 0x48520 "flash-spl-fit-enc.bin"
+
+
+- Add the Install Secret Key command to generate a dummy DEK blob file,
+  the blob address should be the same as used in csf_spl_enc.txt:
+
+  For example:
+
+  [Install Secret Key]
+    ...
+    Key = "dek_fit_dummy.bin"
+    Blob Address = 0x40400000
+
+- Add the Decrypt Data command to encrypt the file. As image was encrypted
+  in CSF above we need to encrypt a dummy file, the block address should be
+  the same as used in csf_fit_enc.txt:
+
+  For example:
+
+  [Decrypt Data]
+    ...
+    Blocks = 0x40200000 0x5AC00 0xB8940 "flash-spl-fit-enc-dummy.bin", \
+             0x920000 0x113540 0xA160"flash-spl-fit-enc-dummy.bin", \
+             0xBE000000 0x11D6A0 0x48520 "flash-spl-fit-enc-dummy.bin"
+
+1.9 Encrypting and signing the FIT image
+-----------------------------------------
+
+The CST is used to encrypt the image and regenerate a random DEK. During this
+step two CSF binaries are generated but only one will be included in final
+image.
+
+- Encrypt the FIT image:
+
+  $ cp flash-spl-enc.bin flash-spl-fit-enc.bin
+  $ ./cst_encrypted -i csf_fit_enc.txt -o csf_fit_enc.bin
+
+- Sign the encrypted FIT image:
+
+  $ cp flash-spl-fit-enc.bin flash-spl-fit-enc-dummy.bin
+  $ ./cst_encrypted -i csf_fit_sign_enc.txt -o csf_fit_sign_enc.bin
+
+1.9.1 Create final CSF binary for FIT image
+-----------------------------------------------------
+
+As only one CSF binary will be included in final image it's necessary to swap
+Nonce/MAC from csf_fit_enc.bin to csf_fit_sign_enc.bin.
+
+- Calculate Nonce/MAC size based on MAC bytes value in CSF:
+
+  Nonce/MAC size = Nonce size + MAC bytes + CSF header for Nonce/Mac
+                 = 12 + 16 + 8 = 36 bytes
+
+- Calculate Nonce/MAC offset in csf_fit_enc.bin:
+
+  MAC offset = csf_fit_enc.bin size - Nonce/MAC size
+             = 3996 - 36 = 3960 Bytes
+
+- Extract Nonce/MAC from csf_fit_enc.bin:
+
+  $ dd if=csf_fit_enc.bin of=noncemac.bin bs=1 skip=3960 count=36
+
+- Calculate Nonce/MAC offset in csf_fit_sign_enc.bin:
+
+  MAC offset = csf_fit_enc.bin size - Nonce/MAC size
+             = 4020 - 36 = 3984 Bytes
+
+- Replace the MAC of csf_fit_sign_enc.bin with the one extracted above:
+
+  $ dd if=noncemac.bin of=csf_fit_sign_enc.bin bs=1 seek=3984 count=36
+
+1.10 Generate the DEK Blob
+---------------------------
+
+The DEK must be encapsulated into a CAAM blob so it can be included into
+the final encrypted binary. The U-Boot provides a tool called dek_blob
+which is calling the CAAM implementation included in OP-TEE.  The
+dek_blob tool is only functional on a board with a closed configuration.
+
+Copy the dek_spl.bin and dek_fit.bin in SDCard FAT partition and run
+the following commands from U-Boot prompt:
+
+  => mmc list
+     FSL_SDHC: 1 (SD)
+     FSL_SDHC: 2
+  => fatload mmc 1:1 0x40400000 dek_spl.bin
+  => dek_blob 0x40400000 0x40401000 128
+  => fatwrite mmc 1:1 0x40401000 dek_spl_blob.bin 0x48
+  => reset
+  ...
+  => fatload mmc 1:1 0x40402000 dek_fit.bin
+  => dek_blob 0x40402000 0x40403000 128
+  => fatwrite mmc 1:1 0x40403000 dek_fit_blob.bin 0x48
+
+In host PC copy the generated dek_spl_blob.bin and dek_fit_blob.bin to the
+CST directory.
+
+Note: Prior to OPTEE version 3.13.0, the target 8M board must be reset
+between dek_blob calls, due to a known cache issue.
+
+1.11 Assembly the encrypted image
+----------------------------------
+
+The CSF binaries generated in the steps above have to be inserted into the
+encrypted image.
+
+The CSF offsets can be obtained from the flash.bin build log:
+
+- SPL CSF offset:
+
+  csf_off 0x2c400
+
+- FIT CSF offset:
+
+  sld_csf_off 0x58c20
+
+The encrypted flash.bin image can be then assembled:
+
+- Create a flash-spl-fit-enc.bin copy:
+
+  $ cp flash-spl-fit-enc.bin encrypted-flash.bin
+
+1.11.1 Insert SPL CSF and DEK blob
+-----------------------------------
+
+- Insert csf_spl_sign_enc.bin in encrypted-flash.bin at 0x2c400 offset:
+
+  $ dd if=csf_spl_sign_enc.bin of=encrypted-flash.bin seek=$((0x2c400)) bs=1 conv=notrunc
+
+- Insert dek_spl_blob.bin in encrypted-flash.bin at 0x2c400 + 0x2000 offset:
+
+  $ dd if=dek_spl_blob.bin of=encrypted-flash.bin seek=$((0x2e400)) bs=1 conv=notrunc
+
+1.11.2 Insert FIT CSF and DEK blob
+-----------------------------------
+
+- Insert csf_fit_sign_enc.bin in encrypted-flash.bin at 0x58c20 offset:
+
+  $ dd if=csf_fit_sign_enc.bin of=encrypted-flash.bin seek=$((0x58c20)) bs=1 conv=notrunc
+
+- The DEK blob must be inserted in last image entry on FIT image, the last line
+  provided by print_fit_hab taget log target can be used:
+
+    0x40200000 0x5AC00 0xB0318
+    0x402B0318 0x10AF18 0x8628
+    0x920000 0x113540 0xA160
+    0xBE000000 0x11D6A0 0x48520 -> Last line in print_fit_hab log
+
+- Insert dek_fit_blob.bin encrypted-flash.bin at 0x11D6A0 + 0x48520 offset:
+
+  $ dd if=dek_fit_blob.bin of=encrypted-flash.bin seek=$((0x165BC0)) bs=1 conv=notrunc
+
+1.11.3 Flash encrypted boot image
+-----------------------------------
+
+- Flash encrypted image in SDCard:
+
+  $ sudo dd if=encrypted-flash.bin of=/dev/sd<x> bs=1K seek=33* && sync
+  * Offset in i.MX8MN device is 32K.
+
+2.0 Setting the PRIBLOB in CAAM SCFGR register
+-----------------------------------------------
+
+It is highly recommended to advance the PRIBLOB field in CAAM SCFGR register to
+0x3, a command is available in U-Boot that should be called after all images in
+boot flow has been decrypted by HAB:
+
+  => set_priblob_bitfield
+
+The PRIBLOB configuration ensures cryptographic separation of private blob
+types avoiding any modification or replacement of DEK blobs. Newly created
+blobs will be incompatible with blobs required to decrypt an encrypted boot
+image. When the HAB later executes the command to decrypt the DEK, an
+incompatible DEK blob will be detected and cause an error. A substitute
+encrypted boot image will not be decrypted, and will not be executed.
+
+References:
+[1] AN12056: "Encrypted Boot on HABv4 and CAAM Enabled Devices"
diff --git a/doc/imx/habv4/guides/mx8m_secure_boot.txt b/doc/imx/habv4/guides/mx8m_secure_boot.txt
new file mode 100644
index 00000000000..dbc8bcd1d55
--- /dev/null
+++ b/doc/imx/habv4/guides/mx8m_secure_boot.txt
@@ -0,0 +1,572 @@
+            +=====================================================+
+            +     i.MX8M family Secure Boot guide using HABv4     +
+            +=====================================================+
+
+1. HABv4 secure boot process
+-----------------------------
+
+This document describes a step-by-step procedure on how to sign and securely
+boot a bootloader image on i.MX8M family devices. It is assumed that the reader
+is familiar with basic HAB concepts and with the PKI tree generation.
+
+Details about HAB can be found in the application note AN4581[1] and in the
+introduction_habv4.txt document.
+
+1.1 Understanding the i.MX8M family flash.bin image layout
+----------------------------------------------------------
+
+Due to the new the architecture, multiple firmwares and softwares are required
+to boot i.MX8M family devices. In order to store all the images in a single
+binary the FIT (Flattened Image Tree) image structure is used.
+
+The final image is generated by the imx-mkimage project, the tool combines all
+the input images in a FIT structure, generating a flash.bin image with an
+appropriate IVT set.
+
+For a secure boot process users should ensure all images included in flash.bin
+file are covered by a digital signature.
+
+- The diagram below illustrate a signed flash.bin image layout:
+
+                     +-----------------------------+
+                     |                             |
+                     |     *Signed HDMI/DP FW      |
+                     |                             |
+                     +-----------------------------+
+                     |           Padding           |
+             ------- +-----------------------------+ --------
+                 ^   |          IVT - SPL          |   ^
+          Signed |   +-----------------------------+   |
+           Data  |   |        u-boot-spl.bin       |   |
+                 |   |              +              |   |  SPL
+                 v   |           DDR FW            |   | Image
+             ------- +-----------------------------+   |
+                     |      CSF - SPL + DDR FW     |   v
+                     +-----------------------------+ --------
+                     |           Padding           |
+             ------- +-----------------------------+ --------
+          Signed ^   |          FDT - FIT          |   ^
+           Data  |   +-----------------------------+   |
+                 v   |          IVT - FIT          |   |
+             ------- +-----------------------------+   |
+                     |          CSF - FIT          |   |
+             ------- +-----------------------------+   |  FIT
+                 ^   |       u-boot-nodtb.bin      |   | Image
+                 |   +-----------------------------+   |
+          Signed |   |       OP-TEE (Optional)     |   |
+           Data  |   +-----------------------------+   |
+                 |   |        bl31.bin (ATF)       |   |
+                 |   +-----------------------------+   |
+                 v   |          u-boot.dtb         |   v
+             ------- +-----------------------------+ --------
+  * Only supported on i.MX8M series
+
+The boot flow on i.MX8M devices are slightly different when compared with i.MX6
+and i.MX7 series, the diagram below illustrate the boot sequence overview:
+
+- i.MX8M boot flow:
+
+                  Secure World                     Non-Secure World
+                                         |
+                                         |
+  +------------+      +------------+     |
+  |     SPL    |      |  i.MX 8M   |     |
+  |      +     | ---> |    ROM     |     |
+  |   DDR FW   |      |   + HAB    |     |
+  +------------+      +------------+     |
+                             |           |
+                             v           |
+                      +------------+     |
+                      |  *Signed   |     |
+                      | HDMI/DP FW |     |
+                      +------------+     |
+                             |           |
+                             v           |
+  +------------+      +------------+     |
+  | FIT Image: |      |     SPL    |     |
+  | ATF + TEE  | ---> |      +     |     |
+  |  + U-Boot  |      |   DDR FW   |     |      +-----------+
+  +------------+      +------------+     |      |   Linux   |
+                             |           |      +-----------+
+                             v           |            ^
+                      +------------+     |            |             +-------+
+                      |    ARM     |     |      +-----------+       | Linux |
+                      |  Trusted   | ----+--->  |   U-Boot  |  <--- |   +   |
+                      |  Firmware  |     |      +-----------+       |  DTB  |
+                      +------------+     |                          +-------+
+                             |           |
+                             v           |
+                       +----------+      |
+                       | **OP-TEE |      |
+                       +----------+      |
+  * Only supported on i.MX8M series
+  ** Optional
+
+Particularly on the i.MX8M, the HDMI firmware or DisplayPort firmware are the
+first image to boot on the device. These firmwares are signed and distributed by
+NXP, and are always authenticated regardless of security configuration. In case
+not required by the application the HDMI or DisplayPort controllers can be
+disabled by eFuses and the firmwares are not required anymore.
+
+The next images are not signed by NXP and users should follow the signing
+procedure as described in this document.
+
+The Second Program Loader (SPL) and DDR firmware are loaded and authenticated
+by the ROM code, these images are executed in the internal RAM and responsible
+for initializing essential features such as DDR, UART, PMIC and clock
+enablement.
+
+Once the DDR is available, the SPL code loads all the images included in the
+FIT structure to their specific execution addresses, the HAB APIs are called
+to extend the root of trust, authenticating the U-Boot, ARM trusted firmware
+(ATF) and OP-TEE (If included).
+
+The root of trust can be extended again at U-Boot level to authenticate Kernel
+and M4 images.
+
+1.2 Enabling the secure boot support in U-Boot
+-----------------------------------------------
+
+The first step is to generate an U-Boot image supporting the HAB features,
+similar to i.MX6 and i.MX7 series the U-Boot provides extra functions for
+HAB, such as the HAB status logs retrievement through the hab_status command
+and support to extend the root of trust.
+
+The support is enabled by adding the CONFIG_IMX_HAB to the build
+configuration:
+
+- Defconfig:
+
+  CONFIG_IMX_HAB=y
+
+- Kconfig:
+
+  ARM architecture -> Support i.MX HAB features
+
+The U-Boot image must then be recompiled after these changes are made.
+
+1.3 Preparing the fit image
+----------------------------
+
+The imx-mkimage project is used to combines all the images in a single
+flash.bin binary, the following files are required:
+
+- U-Boot:
+  u-boot.bin
+  u-boot-nodtb.bin
+  u-boot-spl.bin
+  U-Boot DTB file (e.g. imx8mp-evk.dtb)
+
+- ATF image:
+  bl31.bin
+
+- DDR firmware:
+  lpddr4_pmu_train_1d_dmem.bin
+  lpddr4_pmu_train_1d_imem.bin
+  lpddr4_pmu_train_2d_dmem.bin
+  lpddr4_pmu_train_2d_imem.bin
+
+- HDMI firmware (Only in i.MX8M):
+  signed_hdmi_imx8m.bin
+
+- DisplayPort firmware (Only in i.MX8M):
+  signed_dp_imx8m.bin
+
+- OP-TEE (Optional):
+  tee.bin
+
+The procedure to build ATF and download the firmwares are out of the scope
+of this document, please refer to the Linux BSP Release Notes and AN12212[2]
+for further details.
+
+Note: Depending on the version of firmware being used, the lpddr4
+filenames may need to be appended or changed if Make errors are encountered.
+(e.g. lpddr4_*mem.bin -> lpddr4_*mem_202006.bin)
+
+Copy all files to iMX8M directory and run the following command according to
+the target device, on this example we are building a HDMI target and also
+including the OP-TEE binary:
+
+- Assembly flash.bin binary:
+
+  $ make SOC=<SoC Name> flash_hdmi_spl_uboot
+
+The mkimage log can be used to calculate the authenticate image command
+parameters and CSF offsets:
+
+- imx-mkimage build log:
+
+  Loader IMAGE:
+   header_image_off 	0x1a000
+   dcd_off 		0x0
+   image_off 		0x1a040
+   csf_off 		0x44600
+   spl hab block: 	0x7e0fd0 0x1a000 0x2e600
+
+  Second Loader IMAGE:
+   sld_header_off 	0x57c00
+   sld_csf_off 		0x58c20
+   sld hab block: 	0x401fcdc0 0x57c00 0x1020
+
+Additional HAB information is provided by running the following command:
+
+- Printing HAB FIT information:
+
+  $ make SOC=<SoC Name> print_fit_hab
+
+  TEE_LOAD_ADDR=0xfe000000 ATF_LOAD_ADDR=0x00910000 ./print_fit_hab.sh \
+  0x60000 fsl-imx8mq-evk.dtb
+  0x40200000 0x5AC00 0x9AAC8
+  0x910000 0xF56C8 0x9139
+  0xFE000000 0xFE804 0x4D268
+  0x4029AAC8 0x14BA6C 0x6DCF
+
+If problems are encountered while using mkimage, please refer to the Linux
+User Guide which can be found alongside the latest Linux BSP release.
+
+1.4 Creating the CSF description file
+--------------------------------------
+
+The CSF contains all the commands that the ROM executes during the secure
+boot. These commands instruct the HAB code on which memory areas of the image
+to authenticate, which keys to install, use and etc. More information
+on constructing a CSF file can be found in the CST User Guide, located
+within the CST package's doc directory.
+
+Key and Certificate generation done by the CST is out of the scope of
+this document. Please refer to introduction_habv4.txt for keys,
+certificates, SRK table, and SRK hash generation.
+The resulting file locations should be inserted into the CSF files like this:
+
+- Insertion into both csf_spl.txt and csf_fit.txt
+
+For Example:
+
+  [Install SRK]
+    File = "<relative_path>/crts/SRK_1_2_3_4_table.bin"
+    ...
+
+  [Install CSFK]
+    File = "<relative_path>/crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem"
+
+  [Install Key]
+    ...
+    File = "<relative_path>/crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem"
+
+CSF examples are available under doc/imx/hab/habv4/csf_examples/ directory.
+
+As explained in sections above the SPL is first authenticated by the ROM code
+and the root of trust is extended to the FIT image, hence two CSF files are
+necessary to completely sign an flash.bin image.
+
+The build log provided by imx-mkimage can be used to define the "Authenticate
+Data" parameter in CSF. The addresses supplied in the build log will be
+needed again for binary insertion.
+
+- SPL "Authenticate Data" addresses in flash.bin build log:
+
+  spl hab block: 0x7e0fd0 0x1a000 0x2e600
+
+- "Authenticate Data" command in csf_spl.txt file:
+
+  For example:
+
+  [Authenticate Data]
+    ...
+    Blocks = 0x7e0fd0 0x1a000 0x2e600 "flash.bin"
+
+- FIT image "Authenticate Data" addresses in flash.bin build log:
+
+  sld hab block: 0x401fcdc0 0x57c00 0x1020
+
+- FIT image "Authenticate Data" addresses in print_fit_hab build log:
+
+  0x40200000 0x5AC00 0x9AAC8
+  0x910000 0xF56C8 0x9139
+  0xFE000000 0xFE804 0x4D268
+  0x4029AAC8 0x14BA6C 0x6DCF
+
+- "Authenticate Data" command in csf_fit.txt file:
+
+  For example:
+
+  [Authenticate Data]
+    ...
+    Blocks = 0x401fcdc0 0x057c00 0x01020 "flash.bin", \
+           0x40200000 0x05AC00 0x9AAC8 "flash.bin", \
+           0x00910000 0x0F56C8 0x09139 "flash.bin", \
+           0xFE000000 0x0FE804 0x4D268 "flash.bin", \
+           0x4029AAC8 0x14BA6C 0x06DCF "flash.bin"
+
+1.4.1 Avoiding Kernel crash in closed devices
+----------------------------------------------
+
+For devices prior to HAB v4.4.0, the HAB code locks the Job Ring and DECO
+master ID registers in closed configuration. In case the user specific
+application requires any changes in CAAM MID registers it's necessary to
+add the "Unlock CAAM MID" command in CSF file.
+
+The current NXP BSP implementation expects the CAAM registers to be unlocked
+when configuring CAAM to operate in non-secure TrustZone world.
+
+The Unlock command is already included by default in the signed HDMI and
+DisplayPort firmwares. On i.MX8MM, i.MX8MN and i.MX8MP devices or in case the
+HDMI or DisplayPort controllers are disabled in i.MX8M, users must ensure this
+command is included in SPL CSF.
+
+- Add Unlock MID command in csf_spl.txt:
+
+  [Unlock]
+      Engine = CAAM
+      Features = MID
+
+1.5 Signing the flash.bin binary
+---------------------------------
+
+The CST tool is used for singing the flash.bin image and generating the CSF
+binary. Users should input the CSF description file created in the step above
+and receive a CSF binary, which contains the CSF commands, SRK table,
+signatures and certificates.
+
+- Create SPL CSF binary file:
+
+ $ ./cst -i csf_spl.txt -o csf_spl.bin
+
+- Create FIT CSF binary file:
+
+ $ ./cst -i csf_fit.txt -o csf_fit.bin
+
+1.6 Assembling the CSF in flash.bin binary
+-------------------------------------------
+
+The CSF binaries generated in the step above have to be inserted into the
+flash.bin image.
+
+The CSF offsets can be obtained from the flash.bin build log:
+
+- SPL CSF offset:
+
+  csf_off 0x44600
+
+- FIT CSF offset:
+
+  sld_csf_off 0x58c20
+
+The signed flash.bin image can be then assembled:
+
+- Create a flash.bin copy:
+
+  $ cp flash.bin signed_flash.bin
+
+- Insert csf_spl.bin in signed_flash.bin at 0x44600 offset:
+
+  $ dd if=csf_spl.bin of=signed_flash.bin seek=$((0x44600)) bs=1 conv=notrunc
+
+- Insert csf_fit.bin in signed_flash.bin at 0x58c20 offset:
+
+  $ dd if=csf_fit.bin of=signed_flash.bin seek=$((0x58c20)) bs=1 conv=notrunc
+
+- Flash signed flash.bin image:
+
+  $ sudo dd if=signed_flash.bin of=/dev/sd<x> bs=1K seek=33 && sync
+
+Note: The Universal Update Utility (UUU) can also be used to flash the
+image to the target board's eMMC. Details on UUU installation and help
+can be found in the supporting UUU documentation[3].
+
+1.7 Programming SRK Hash
+-------------------------
+
+As explained in AN4581[1] and in introduction_habv4.txt document the SRK Hash
+fuse values are generated by the srktool and should be programmed in the
+SoC SRK_HASH[255:0] fuses.
+
+Be careful when programming these values, as this data is the basis for the
+root of trust. An error in SRK Hash results in a part that does not boot.
+More information and full details regarding fuses can be found in the
+Security Reference Manual of the target board. Contact an NXP Representative
+for access.
+
+The U-Boot fuse tool can be used for programming eFuses on i.MX SoCs.
+
+- Dump SRK Hash fuses values in host machine:
+
+  $ hexdump -e '/4 "0x"' -e '/4 "%X""\n"' SRK_1_2_3_4_fuse.bin
+  0x20593752
+  0x6ACE6962
+  0x26E0D06C
+  0xFC600661
+  0x1240E88F
+  0x1209F144
+  0x831C8117
+  0x1190FD4D
+
+- Program SRK_HASH[255:0] fuses on i.MX8M family devices:
+
+  => fuse prog 6 0 0x20593752
+  => fuse prog 6 1 0x6ACE6962
+  => fuse prog 6 2 0x26E0D06C
+  => fuse prog 6 3 0xFC600661
+  => fuse prog 7 0 0x1240E88F
+  => fuse prog 7 1 0x1209F144
+  => fuse prog 7 2 0x831C8117
+  => fuse prog 7 3 0x1190FD4D
+
+
+1.8 Verifying HAB events
+-------------------------
+
+The next step is to verify that the signatures included in flash.bin image is
+successfully processed without errors. HAB generates events when processing
+the commands if it encounters issues.
+
+The hab_status U-Boot command call the hab_report_event() and hab_status()
+HAB API functions to verify the processor security configuration and status.
+This command displays any events that were generated during the process.
+
+Prior to closing the device users should ensure no HAB events were found, as
+the example below:
+
+- Verify HAB events:
+
+  => hab_status
+
+  Secure boot disabled
+
+  HAB Configuration: 0xf0, HAB State: 0x66
+
+1.9 Closing the device
+-----------------------
+
+After the device successfully boots a signed image without generating any HAB
+events, it is safe to close the device. This is the last step in the HAB
+process, and is achieved by programming the SEC_CONFIG[1] fuse bit.
+
+Once the fuse is programmed, the chip does not load an image that has not been
+signed using the correct PKI tree.
+
+- Program SEC_CONFIG[1] fuse on i.MX8M family devices:
+
+  => fuse prog 1 3 0x2000000
+
+1.10 Completely secure the device
+----------------------------------
+
+Additional fuses can be programmed for completely secure the device, more
+details about these fuses and their possible impact can be found at AN4581[1].
+
+2. Secure boot in SDP mode
+---------------------------
+
+For secure boot in SDP mode, please refer to the "HABv4 closed chip support"
+chapter in the UUU documentation[3].
+
+3. Authenticating additional boot images
+-----------------------------------------
+
+The High Assurance Boot (HAB) code located in the on-chip ROM provides an
+Application Programming Interface (API) making it possible to call back
+into the HAB code for authenticating additional boot images.
+
+The U-Boot is running in non-secure TrustZone world and to make use of this
+feature it's necessary to use a SIP call to the ATF, this is already
+implemented in hab.c code and it's transparent to the user.
+
+The process of signing an additional image is similar as in i.MX6 and i.MX7
+series devices, the steps below are using the Linux Kernel image as example.
+
+The diagram below illustrate the Image layout:
+
+            ------- +-----------------------------+ <-- *load_address
+                ^   |                             |
+                |   |                             |
+                |   |                             |
+                |   |                             |
+                |   |            Image            |
+         Signed |   |                             |
+          Data  |   |                             |
+                |   |                             |
+                |   +-----------------------------+
+                |   |    Padding to Image size    |
+                |   |          in header          |
+                |   +-----------------------------+ <-- *ivt
+                v   |     Image Vector Table      |
+            ------- +-----------------------------+ <-- *csf
+                    |                             |
+                    | Command Sequence File (CSF) |
+                    |                             |
+                    +-----------------------------+
+                    |     Padding (optional)      |
+                    +-----------------------------+
+
+3.1 Padding the image
+----------------------
+
+The Image must be padded to the size specified in the Image header, this can be
+achieved by using the od command.
+
+- Read Image size:
+
+  $ od -x -j 0x10 -N 0x4 --endian=little Image
+  0000020 5000 0145
+  0000024
+
+The tool objcopy can be used for padding the image.
+
+- Pad the Image:
+
+  $ objcopy -I binary -O binary --pad-to 0x1455000 --gap-fill=0x00 \
+	Image Image_pad.bin
+
+3.2 Generating Image Vector Table
+----------------------------------
+
+The HAB code requires an Image Vector Table (IVT) for determining the image
+length and the CSF location. Since Image does not include an IVT this has
+to be manually created and appended to the end of the padded Image, the
+script genIVT.pl in script_examples directory can be used as reference.
+
+- Generate IVT:
+
+  $ genIVT.pl
+
+Note: The load Address may change depending on the device.
+
+- Append the ivt.bin at the end of the padded Image:
+
+  $ cat Image_pad.bin ivt.bin > Image_pad_ivt.bin
+
+3.3 Signing the image
+----------------------
+
+A CSF file has to be created to sign the image. HAB does not allow to change
+the SRK once the first image is authenticated, so the same SRK key used in
+the initial image must be used when extending the root of trust.
+
+CSF examples are available in ../csf_examples/additional_images/ directory.
+
+- Create CSF binary file:
+
+  $ ./cst --i csf_additional_images.txt --o csf_Image.bin
+
+- Attach the CSF binary to the end of the image:
+
+  $ cat Image_pad_ivt.bin csf_Image.bin > Image_signed.bin
+
+3.4 Verifying HAB events
+-------------------------
+
+The U-Boot includes the hab_auth_img command which can be used for
+authenticating and troubleshooting the signed image, the Image must be
+loaded at the load address specified in the IVT.
+
+- Authenticate additional image:
+
+  => hab_auth_img <Load Address> <Image Size> <IVT Offset>
+
+If no HAB events were found the Image is successfully signed.
+
+References:
+[1] AN4581: "i.MX Secure Boot on HABv4 Supported Devices"
+[2] AN12212: "Software Solutions for Migration Guide from Aarch32 to Aarch64"
+[3] https://github.com/NXPmicro/mfgtools/releases/
diff --git a/doc/imx/habv4/introduction_habv4.txt b/doc/imx/habv4/introduction_habv4.txt
index 25711bbe95a..f600f734ba9 100644
--- a/doc/imx/habv4/introduction_habv4.txt
+++ b/doc/imx/habv4/introduction_habv4.txt
@@ -12,7 +12,7 @@ to authenticate and/or decrypt the program image by using cryptography
 operations.
 
 This feature is supported in i.MX 50, i.MX 53, i.MX 6, i.MX 7 series and
- i.MX 8M, i.MX 8MM devices.
+i.MX 8M family (i.MX 8M, i.MX 8MM, i.MX 8MN, i.MX 8MP devices).
 
 Step-by-step guides are available under doc/imx/habv4/guides/ directory,
 users familiar with HAB and CST PKI tree generation should refer to these
@@ -66,7 +66,9 @@ The CSF structure contains the commands, SRK table, signatures and
 certificates.
 
 Details about the Secure Boot and Code Signing Tool (CST) can be found in
-the application note AN4581[2] and in the secure boot guides.
+the application note AN4581[2] and in the secure boot guides. Syntax and
+details about CSF can be found in the CST User Guide which is packaged with
+the CST tool and located in the doc directory.
 
 1.2 The HABv4 Encrypted Boot Architecture
 ------------------------------------------
@@ -153,7 +155,7 @@ IMG and CSF keys.
 
 A new PKI tree can be generated by following the example below:
 
-- Generating 2048-bit PKI tree on CST v3.1.0:
+- Generating 2048-bit PKI tree on CST (starting from v3.1.0):
 
   $ ./hab4_pki_tree.sh
   ...
@@ -199,7 +201,8 @@ The script hab4_pki_tree.sh is also able to generate a Public Key Infrastructure
 (PKI) tree which only contains SRK Keys, users should not set the CA flag when
 generating the SRK certificates.
 
-- Generating 2048-bit fast authentication PKI tree on CST v3.1.0:
+- Generating 2048-bit fast authentication PKI tree on CST (starting from
+v3.1.0):
 
   $ ./hab4_pki_tree.sh
   ...
@@ -257,6 +260,5 @@ directory.
 
 References:
 [1] CST: i.MX High Assurance Boot Reference Code Signing Tool.
-[2] AN4581: "Secure Boot on i.MX 50, i.MX 53, i.MX 6 and i.MX 7 Series using
- HABv4" - Rev 2.
-[3] AN12056: "Encrypted Boot on HABv4 and CAAM Enabled Devices" - Rev. 1
+[2] AN4581: "i.MX Secure Boot on HABv4 Supported Devices"
+[3] AN12056: "Encrypted Boot on HABv4 and CAAM Enabled Devices"
diff --git a/drivers/Makefile b/drivers/Makefile
index 4e7cf284405..d886187e18c 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
 obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/
 obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/
 obj-$(CONFIG_IMX8ULP_DRAM) += ddr/imx/imx8ulp/
+obj-$(CONFIG_ARCH_IMX9) += ddr/imx/imx9/
 obj-$(CONFIG_SPL_DM_RESET) += reset/
 obj-$(CONFIG_SPL_MUSB_NEW) += usb/musb-new/
 obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index ce6907e6900..1930f003354 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -59,6 +59,15 @@ config DWC_AHCI
 	  Enable this driver to support Sata devices through
 	  Synopsys DWC AHCI module.
 
+config IMX_AHCI
+	bool "Enable IMX AHCI driver support"
+	select SCSI_AHCI
+	depends on AHCI
+	depends on DM_SCSI
+	help
+	  Enable this driver to support Sata devices through
+	  i.MX AHCI module.
+
 config DWC_AHSATA
 	bool "Enable DWC AHSATA driver support"
 	select LIBATA
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 6e30180b8b4..a0fcd7b1640 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_FSL_SATA) += fsl_sata.o
 obj-$(CONFIG_LIBATA) += libata.o
 obj-$(CONFIG_SATA) += sata.o
 obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
+obj-$(CONFIG_IMX_AHCI) += imx_ahci.o
 obj-$(CONFIG_SATA_MV) += sata_mv.o
 obj-$(CONFIG_SATA_SIL) += sata_sil.o
 obj-$(CONFIG_SANDBOX) += sata_sandbox.o
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 2062197afcd..92d639932cb 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -596,8 +596,8 @@ static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
 
 	debug("Enter %s: for port %d\n", __func__, port);
 
-	if (port > uc_priv->n_ports) {
-		printf("Invalid port number %d\n", port);
+	if (port >= uc_priv->n_ports) {
+		debug("Invalid port number %d\n", port);
 		return -1;
 	}
 
diff --git a/drivers/ata/imx_ahci.c b/drivers/ata/imx_ahci.c
new file mode 100644
index 00000000000..9d9da96e850
--- /dev/null
+++ b/drivers/ata/imx_ahci.c
@@ -0,0 +1,857 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ahci.h>
+#include <scsi.h>
+#include <sata.h>
+#include <asm/io.h>
+#if CONFIG_IS_ENABLED(CLK)
+#include <clk.h>
+#else
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#endif
+#include <asm/arch-mx6/iomux.h>
+#include <syscon.h>
+#include <regmap.h>
+#include <asm-generic/gpio.h>
+#include <dm/device_compat.h>
+
+enum {
+	/* Timer 1-ms Register */
+	IMX_TIMER1MS				= 0x00e0,
+	/* Port0 PHY Control Register */
+	IMX_P0PHYCR				= 0x0178,
+	IMX_P0PHYCR_TEST_PDDQ			= 1 << 20,
+	IMX_P0PHYCR_CR_READ			= 1 << 19,
+	IMX_P0PHYCR_CR_WRITE			= 1 << 18,
+	IMX_P0PHYCR_CR_CAP_DATA			= 1 << 17,
+	IMX_P0PHYCR_CR_CAP_ADDR			= 1 << 16,
+	/* Port0 PHY Status Register */
+	IMX_P0PHYSR				= 0x017c,
+	IMX_P0PHYSR_CR_ACK			= 1 << 18,
+	IMX_P0PHYSR_CR_DATA_OUT			= 0xffff << 0,
+	/* Lane0 Output Status Register */
+	IMX_LANE0_OUT_STAT			= 0x2003,
+	IMX_LANE0_OUT_STAT_RX_PLL_STATE		= 1 << 1,
+	/* Clock Reset Register */
+	IMX_CLOCK_RESET				= 0x7f3f,
+	IMX_CLOCK_RESET_RESET			= 1 << 0,
+	/* IMX8QM HSIO AHCI definitions */
+	IMX8QM_SATA_PHY_REG03_RX_IMPED_RATIO		= 0x03,
+	IMX8QM_SATA_PHY_REG09_TX_IMPED_RATIO		= 0x09,
+	IMX8QM_SATA_PHY_REG10_TX_POST_CURSOR_RATIO	= 0x0a,
+	IMX8QM_SATA_PHY_GEN1_TX_POST_CURSOR_RATIO	= 0x15,
+	IMX8QM_SATA_PHY_IMPED_RATIO_85OHM		= 0x6c,
+	IMX8QM_SATA_PHY_REG22_TX_POST_CURSOR_RATIO	= 0x16,
+	IMX8QM_SATA_PHY_GEN2_TX_POST_CURSOR_RATIO	= 0x00,
+	IMX8QM_SATA_PHY_REG24_TX_AMP_RATIO_MARGIN0	= 0x18,
+	IMX8QM_SATA_PHY_TX_AMP_RATIO_MARGIN0		= 0x64,
+	IMX8QM_SATA_PHY_REG25_TX_AMP_RATIO_MARGIN1	= 0x19,
+	IMX8QM_SATA_PHY_TX_AMP_RATIO_MARGIN1		= 0x70,
+	IMX8QM_SATA_PHY_REG26_TX_AMP_RATIO_MARGIN2	= 0x1a,
+	IMX8QM_SATA_PHY_TX_AMP_RATIO_MARGIN2		= 0x69,
+	IMX8QM_SATA_PHY_REG48_PMA_STATUS		= 0x30,
+	IMX8QM_SATA_PHY_REG48_PMA_RDY			= BIT(7),
+	IMX8QM_SATA_PHY_REG128_UPDATE_SETTING		= 0x80,
+	IMX8QM_SATA_PHY_UPDATE_SETTING			= 0x01,
+	IMX8QM_LPCG_PHYX2_OFFSET		= 0x00000,
+	IMX8QM_CSR_PHYX2_OFFSET			= 0x90000,
+	IMX8QM_CSR_PHYX1_OFFSET			= 0xa0000,
+	IMX8QM_CSR_PHYX_STTS0_OFFSET		= 0x4,
+	IMX8QM_CSR_PCIEA_OFFSET			= 0xb0000,
+	IMX8QM_CSR_PCIEB_OFFSET			= 0xc0000,
+	IMX8QM_CSR_SATA_OFFSET			= 0xd0000,
+	IMX8QM_CSR_PCIE_CTRL2_OFFSET		= 0x8,
+	IMX8QM_CSR_MISC_OFFSET			= 0xe0000,
+	/* IMX8QM SATA specific control registers */
+	IMX8QM_SATA_PPCFG_OFFSET			= 0xa8,
+	IMX8QM_SATA_PPCFG_FORCE_PHY_RDY			= BIT(20),
+	IMX8QM_SATA_PPCFG_BIST_PATTERN_MASK		= 0x7 << 21,
+	IMX8QM_SATA_PPCFG_BIST_PATTERN_OFFSET		= 21,
+	IMX8QM_SATA_PPCFG_BIST_PATTERN_EN		= BIT(24),
+	IMX8QM_SATA_PPCFG_BIST_PATTERN_NOALIGNS		= BIT(26),
+	IMX8QM_SATA_PP2CFG_OFFSET			= 0xac,
+	IMX8QM_SATA_PP2CFG_COMINIT_NEGATE_MIN		= 0x28 << 24,
+	IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP		= 0x18 << 16,
+	IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP_MAX		= 0x2b << 8,
+	IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP_MIN		= 0x1b << 0,
+	IMX8QM_SATA_PP3CFG_OFFSET			= 0xb0,
+	IMX8QM_SATA_PP3CFG_COMWAKE_NEGATE_MIN		= 0x0e << 24,
+	IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP		= 0x08 << 16,
+	IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP_MAX	= 0x0f << 8,
+	IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP_MIN	= 0x01 << 0,
+
+	IMX8QM_LPCG_PHYX2_PCLK0_MASK		= (0x3 << 16),
+	IMX8QM_LPCG_PHYX2_PCLK1_MASK		= (0x3 << 20),
+	IMX8QM_PHY_APB_RSTN_0			= BIT(0),
+	IMX8QM_PHY_MODE_SATA			= BIT(19),
+	IMX8QM_PHY_MODE_MASK			= (0xf << 17),
+	IMX8QM_PHY_PIPE_RSTN_0			= BIT(24),
+	IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0		= BIT(25),
+	IMX8QM_PHY_PIPE_RSTN_1			= BIT(26),
+	IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1		= BIT(27),
+	IMX8QM_STTS0_LANE0_TX_PLL_LOCK		= BIT(4),
+	IMX8QM_MISC_IOB_RXENA			= BIT(0),
+	IMX8QM_MISC_IOB_TXENA			= BIT(1),
+	IMX8QM_MISC_PHYX1_EPCS_SEL		= BIT(12),
+	IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1	= BIT(24),
+	IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0	= BIT(25),
+	IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1	= BIT(28),
+	IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0	= BIT(29),
+	IMX8QM_SATA_CTRL_RESET_N		= BIT(12),
+	IMX8QM_SATA_CTRL_EPCS_PHYRESET_N	= BIT(7),
+	IMX8QM_SATA_CTRL_EPCS_TXDEEMP_SEL	= BIT(6),
+	IMX8QM_SATA_CTRL_EPCS_TXDEEMP		= BIT(5),
+	IMX8QM_CTRL_BUTTON_RST_N		= BIT(21),
+	IMX8QM_CTRL_POWER_UP_RST_N		= BIT(23),
+	IMX8QM_CTRL_LTSSM_ENABLE		= BIT(4),
+};
+
+enum ahci_imx_type {
+	AHCI_IMX6Q,
+	AHCI_IMX6QP,
+	AHCI_IMX8QM,
+};
+
+struct imx_ahci_priv {
+#if CONFIG_IS_ENABLED(CLK)
+	struct clk sata_clk;
+	struct clk sata_ref_clk;
+	struct clk ahb_clk;
+	struct clk epcs_tx_clk;
+	struct clk epcs_rx_clk;
+	struct clk phy_apbclk;
+	struct clk phy_pclk0;
+	struct clk phy_pclk1;
+#endif
+	enum ahci_imx_type type;
+	void __iomem *phy_base;
+	void __iomem *mmio;
+	struct regmap *gpr;
+	struct gpio_desc clkreq_gpio;
+	u32 phy_params;
+	u32 imped_ratio;
+	u32 ext_osc;
+};
+
+static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
+{
+	int timeout = 10;
+	u32 crval;
+	u32 srval;
+
+	/* Assert or deassert the bit */
+	crval = readl(mmio + IMX_P0PHYCR);
+	if (assert)
+		crval |= bit;
+	else
+		crval &= ~bit;
+	writel(crval, mmio + IMX_P0PHYCR);
+
+	/* Wait for the cr_ack signal */
+	do {
+		srval = readl(mmio + IMX_P0PHYSR);
+		if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
+			break;
+		udelay(100);
+	} while (--timeout);
+
+	return timeout ? 0 : -ETIMEDOUT;
+}
+
+static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
+{
+	u32 crval = addr;
+	int ret;
+
+	/* Supply the address on cr_data_in */
+	writel(crval, mmio + IMX_P0PHYCR);
+
+	/* Assert the cr_cap_addr signal */
+	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
+	if (ret)
+		return ret;
+
+	/* Deassert cr_cap_addr */
+	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int imx_phy_reg_write(u16 val, void __iomem *mmio)
+{
+	u32 crval = val;
+	int ret;
+
+	/* Supply the data on cr_data_in */
+	writel(crval, mmio + IMX_P0PHYCR);
+
+	/* Assert the cr_cap_data signal */
+	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
+	if (ret)
+		return ret;
+
+	/* Deassert cr_cap_data */
+	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
+	if (ret)
+		return ret;
+
+	if (val & IMX_CLOCK_RESET_RESET) {
+		/*
+		 * In case we're resetting the phy, it's unable to acknowledge,
+		 * so we return immediately here.
+		 */
+		crval |= IMX_P0PHYCR_CR_WRITE;
+		writel(crval, mmio + IMX_P0PHYCR);
+		goto out;
+	}
+
+	/* Assert the cr_write signal */
+	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
+	if (ret)
+		return ret;
+
+	/* Deassert cr_write */
+	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
+	if (ret)
+		return ret;
+
+out:
+	return 0;
+}
+
+static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
+{
+	int ret;
+
+	/* Assert the cr_read signal */
+	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
+	if (ret)
+		return ret;
+
+	/* Capture the data from cr_data_out[] */
+	*val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;
+
+	/* Deassert cr_read */
+	ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int imx_sata_phy_reset(struct imx_ahci_priv *priv)
+{
+	void __iomem *mmio = priv->mmio;
+	int timeout = 10;
+	u16 val;
+	int ret;
+
+	/* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
+	ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
+	if (ret)
+		return ret;
+	ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
+	if (ret)
+		return ret;
+
+	/* Wait for PHY RX_PLL to be stable */
+	do {
+		udelay(100);
+		ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
+		if (ret)
+			return ret;
+		ret = imx_phy_reg_read(&val, mmio);
+		if (ret)
+			return ret;
+		if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
+			break;
+	} while (--timeout);
+
+	return timeout ? 0 : -ETIMEDOUT;
+}
+
+static int imx8_sata_enable(struct udevice *dev)
+{
+	u32 val, reg;
+	int i, ret;
+	struct imx_ahci_priv *imxpriv = dev_get_priv(dev);
+
+#if CONFIG_IS_ENABLED(CLK)
+	/* configure the hsio for sata */
+	ret = clk_enable(&imxpriv->phy_pclk0);
+	if (ret < 0) {
+		dev_err(dev, "can't enable phy pclk0.\n");
+		return ret;
+	}
+	ret = clk_enable(&imxpriv->phy_pclk1);
+	if (ret < 0) {
+		dev_err(dev, "can't enable phy pclk1.\n");
+		goto disable_phy_pclk0;
+	}
+	ret = clk_enable(&imxpriv->epcs_tx_clk);
+	if (ret < 0) {
+		dev_err(dev, "can't enable epcs tx clk.\n");
+		goto disable_phy_pclk1;
+	}
+	ret = clk_enable(&imxpriv->epcs_rx_clk);
+	if (ret < 0) {
+		dev_err(dev, "can't enable epcs rx clk.\n");
+		goto disable_epcs_tx_clk;
+	}
+	ret = clk_enable(&imxpriv->phy_apbclk);
+	if (ret < 0) {
+		dev_err(dev, "can't enable phy pclk1.\n");
+		goto disable_epcs_rx_clk;
+	}
+#endif
+
+	/* Configure PHYx2 PIPE_RSTN */
+	regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEA_OFFSET
+			+ IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val);
+	if ((val & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
+		 /* PCIEA of HSIO is down too */
+		regmap_update_bits(imxpriv->gpr,
+				IMX8QM_CSR_PHYX2_OFFSET,
+				IMX8QM_PHY_PIPE_RSTN_0
+				| IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0,
+				IMX8QM_PHY_PIPE_RSTN_0
+				| IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0);
+	}
+	regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEB_OFFSET
+			+ IMX8QM_CSR_PCIE_CTRL2_OFFSET, &reg);
+	if ((reg & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
+		 /* PCIEB of HSIO is down */
+		regmap_update_bits(imxpriv->gpr,
+				IMX8QM_CSR_PHYX2_OFFSET,
+				IMX8QM_PHY_PIPE_RSTN_1
+				| IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1,
+				IMX8QM_PHY_PIPE_RSTN_1
+				| IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1);
+	}
+
+	/* set PWR_RST and BT_RST of csr_pciea */
+	val = IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET;
+	regmap_update_bits(imxpriv->gpr,
+			val,
+			IMX8QM_CTRL_BUTTON_RST_N,
+			IMX8QM_CTRL_BUTTON_RST_N);
+	regmap_update_bits(imxpriv->gpr,
+			val,
+			IMX8QM_CTRL_POWER_UP_RST_N,
+			IMX8QM_CTRL_POWER_UP_RST_N);
+
+	/* PHYX1_MODE to SATA */
+	regmap_update_bits(imxpriv->gpr,
+			IMX8QM_CSR_PHYX1_OFFSET,
+			IMX8QM_PHY_MODE_MASK,
+			IMX8QM_PHY_MODE_SATA);
+
+	if (imxpriv->ext_osc) {
+		dev_info(dev, "external osc is used.\n");
+		/*
+		 * bit0 rx ena 1, bit1 tx ena 0
+		 * bit12 PHY_X1_EPCS_SEL 1.
+		 */
+		regmap_update_bits(imxpriv->gpr,
+				IMX8QM_CSR_MISC_OFFSET,
+				IMX8QM_MISC_IOB_RXENA,
+				IMX8QM_MISC_IOB_RXENA);
+		regmap_update_bits(imxpriv->gpr,
+				IMX8QM_CSR_MISC_OFFSET,
+				IMX8QM_MISC_IOB_TXENA,
+				0);
+	} else {
+		dev_info(dev, "internal pll is used.\n");
+		regmap_update_bits(imxpriv->gpr,
+				IMX8QM_CSR_MISC_OFFSET,
+				IMX8QM_MISC_IOB_RXENA,
+				0);
+		regmap_update_bits(imxpriv->gpr,
+				IMX8QM_CSR_MISC_OFFSET,
+				IMX8QM_MISC_IOB_TXENA,
+				IMX8QM_MISC_IOB_TXENA);
+
+	}
+	regmap_update_bits(imxpriv->gpr,
+			IMX8QM_CSR_MISC_OFFSET,
+			IMX8QM_MISC_PHYX1_EPCS_SEL,
+			IMX8QM_MISC_PHYX1_EPCS_SEL);
+	/*
+	 * It is possible, for PCIe and SATA are sharing
+	 * the same clock source, HPLL or external oscillator.
+	 * When PCIe is in low power modes (L1.X or L2 etc),
+	 * the clock source can be turned off. In this case,
+	 * if this clock source is required to be toggling by
+	 * SATA, then SATA functions will be abnormal.
+	 */
+	regmap_update_bits(imxpriv->gpr,
+			IMX8QM_CSR_MISC_OFFSET,
+			IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1
+			| IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0
+			| IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1
+			| IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0,
+			IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1
+			| IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0
+			| IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1
+			| IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0);
+
+	/* clear PHY RST, then set it */
+	regmap_update_bits(imxpriv->gpr,
+			IMX8QM_CSR_SATA_OFFSET,
+			IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
+			0);
+
+	regmap_update_bits(imxpriv->gpr,
+			IMX8QM_CSR_SATA_OFFSET,
+			IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
+			IMX8QM_SATA_CTRL_EPCS_PHYRESET_N);
+	regmap_update_bits(imxpriv->gpr,
+			IMX8QM_CSR_SATA_OFFSET,
+			IMX8QM_SATA_CTRL_EPCS_TXDEEMP,
+			IMX8QM_SATA_CTRL_EPCS_TXDEEMP);
+	regmap_update_bits(imxpriv->gpr,
+			IMX8QM_CSR_SATA_OFFSET,
+			IMX8QM_SATA_CTRL_EPCS_TXDEEMP_SEL,
+			IMX8QM_SATA_CTRL_EPCS_TXDEEMP_SEL);
+
+	/* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
+	regmap_update_bits(imxpriv->gpr,
+			IMX8QM_CSR_SATA_OFFSET,
+			IMX8QM_SATA_CTRL_RESET_N,
+			IMX8QM_SATA_CTRL_RESET_N);
+	udelay(1);
+	regmap_update_bits(imxpriv->gpr,
+			IMX8QM_CSR_SATA_OFFSET,
+			IMX8QM_SATA_CTRL_RESET_N,
+			0);
+	regmap_update_bits(imxpriv->gpr,
+			IMX8QM_CSR_SATA_OFFSET,
+			IMX8QM_SATA_CTRL_RESET_N,
+			IMX8QM_SATA_CTRL_RESET_N);
+
+	/* APB reset */
+	regmap_update_bits(imxpriv->gpr,
+			IMX8QM_CSR_PHYX1_OFFSET,
+			IMX8QM_PHY_APB_RSTN_0,
+			IMX8QM_PHY_APB_RSTN_0);
+
+	for (i = 0; i < 100; i++) {
+		reg = IMX8QM_CSR_PHYX1_OFFSET
+			+ IMX8QM_CSR_PHYX_STTS0_OFFSET;
+		regmap_read(imxpriv->gpr, reg, &val);
+		val &= IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
+		if (val == IMX8QM_STTS0_LANE0_TX_PLL_LOCK)
+			break;
+		udelay(1);
+	}
+
+	if (val != IMX8QM_STTS0_LANE0_TX_PLL_LOCK) {
+		dev_err(dev, "TX PLL of the PHY is not locked\n");
+		ret = -ENODEV;
+	} else {
+		for (i = 0; i < 1000; i++) {
+			reg = readb(imxpriv->phy_base +
+					IMX8QM_SATA_PHY_REG48_PMA_STATUS);
+			if (reg & IMX8QM_SATA_PHY_REG48_PMA_RDY)
+				break;
+			udelay(10);
+		}
+		if ((reg & IMX8QM_SATA_PHY_REG48_PMA_RDY) == 0) {
+			dev_err(dev, "Calibration is NOT finished.\n");
+			ret = -ENODEV;
+			goto err_out;
+		}
+
+		writeb(imxpriv->imped_ratio, imxpriv->phy_base
+				+ IMX8QM_SATA_PHY_REG03_RX_IMPED_RATIO);
+		writeb(imxpriv->imped_ratio, imxpriv->phy_base
+				+ IMX8QM_SATA_PHY_REG09_TX_IMPED_RATIO);
+		reg = readb(imxpriv->phy_base
+				+ IMX8QM_SATA_PHY_REG03_RX_IMPED_RATIO);
+		if (unlikely(reg != imxpriv->imped_ratio))
+			dev_info(dev, "Can't set PHY RX impedance ratio.\n");
+		reg = readb(imxpriv->phy_base
+				+ IMX8QM_SATA_PHY_REG09_TX_IMPED_RATIO);
+		if (unlikely(reg != imxpriv->imped_ratio))
+			dev_info(dev, "Can't set PHY TX impedance ratio.\n");
+
+		/* Configure the tx_amplitude to pass the tests. */
+		writeb(IMX8QM_SATA_PHY_TX_AMP_RATIO_MARGIN0, imxpriv->phy_base +
+				IMX8QM_SATA_PHY_REG24_TX_AMP_RATIO_MARGIN0);
+		writeb(IMX8QM_SATA_PHY_TX_AMP_RATIO_MARGIN1, imxpriv->phy_base +
+				IMX8QM_SATA_PHY_REG25_TX_AMP_RATIO_MARGIN1);
+		writeb(IMX8QM_SATA_PHY_TX_AMP_RATIO_MARGIN2, imxpriv->phy_base +
+				IMX8QM_SATA_PHY_REG26_TX_AMP_RATIO_MARGIN2);
+
+		/* Adjust the OOB COMINIT/COMWAKE to pass the tests. */
+		writeb(IMX8QM_SATA_PHY_GEN1_TX_POST_CURSOR_RATIO,
+				imxpriv->phy_base +
+				IMX8QM_SATA_PHY_REG10_TX_POST_CURSOR_RATIO);
+		writeb(IMX8QM_SATA_PHY_GEN2_TX_POST_CURSOR_RATIO,
+				imxpriv->phy_base +
+				IMX8QM_SATA_PHY_REG22_TX_POST_CURSOR_RATIO);
+
+		writeb(IMX8QM_SATA_PHY_UPDATE_SETTING, imxpriv->phy_base +
+				IMX8QM_SATA_PHY_REG128_UPDATE_SETTING);
+
+		reg = IMX8QM_SATA_PP2CFG_COMINIT_NEGATE_MIN |
+			IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP |
+			IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP_MAX |
+			IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP_MIN;
+		writel(reg, imxpriv->mmio + IMX8QM_SATA_PP2CFG_OFFSET);
+		reg = IMX8QM_SATA_PP3CFG_COMWAKE_NEGATE_MIN |
+			IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP |
+			IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP_MAX |
+			IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP_MIN;
+		writel(reg, imxpriv->mmio + IMX8QM_SATA_PP3CFG_OFFSET);
+
+		udelay(100);
+
+		/*
+		 * To reduce the power consumption, gate off
+		 * the PHY clks
+		 */
+#if CONFIG_IS_ENABLED(CLK)
+		clk_disable(&imxpriv->phy_apbclk);
+		clk_disable(&imxpriv->phy_pclk1);
+		clk_disable(&imxpriv->phy_pclk0);
+#endif
+		return ret;
+	}
+
+err_out:
+#if CONFIG_IS_ENABLED(CLK)
+		clk_disable(&imxpriv->phy_apbclk);
+disable_epcs_rx_clk:
+		clk_disable(&imxpriv->epcs_rx_clk);
+disable_epcs_tx_clk:
+		clk_disable(&imxpriv->epcs_tx_clk);
+disable_phy_pclk1:
+		clk_disable(&imxpriv->phy_pclk1);
+disable_phy_pclk0:
+		clk_disable(&imxpriv->phy_pclk0);
+#endif
+	return ret;
+}
+
+static int imx8_sata_probe(struct udevice *dev, struct imx_ahci_priv *imxpriv)
+{
+	int ret = 0;
+	fdt_addr_t addr;
+
+	if (dev_read_u32u(dev, "ext_osc", &imxpriv->ext_osc)) {
+		dev_info(dev, "ext_osc is not specified.\n");
+		/* Use the external osc as ref clk defaultly. */
+		imxpriv->ext_osc = 1;
+	}
+
+	if (dev_read_u32u(dev, "fsl,phy-imp", &imxpriv->imped_ratio)) {
+		/*
+		 * Regarding to the differnet Hw designs,
+		 * Set the impedance ratio to 0x6c when 85OHM is used.
+		 * Keep it to default value 0x80, when 100OHM is used.
+		 */
+		dev_info(dev, "phy impedance ratio is not specified.\n");
+		imxpriv->imped_ratio = IMX8QM_SATA_PHY_IMPED_RATIO_85OHM;
+	}
+
+	addr = dev_read_addr_name(dev, "phy");
+	if (addr == FDT_ADDR_T_NONE){
+		dev_err(dev, "no phy space\n");
+		return -ENOMEM;
+	}
+
+	imxpriv->phy_base = (void __iomem *)addr;
+
+	imxpriv->gpr =
+		 syscon_regmap_lookup_by_phandle(dev, "hsio");
+	if (IS_ERR(imxpriv->gpr)) {
+		dev_err(dev, "unable to find gpr registers\n");
+		return PTR_ERR(imxpriv->gpr);
+	}
+
+#if CONFIG_IS_ENABLED(CLK)
+	ret = clk_get_by_name(dev, "epcs_tx", &imxpriv->epcs_tx_clk);
+	if (ret) {
+		dev_err(dev, "can't get sata_epcs tx clock.\n");
+		return ret;
+	}
+
+	ret = clk_get_by_name(dev, "epcs_rx", &imxpriv->epcs_rx_clk);
+	if (ret) {
+		dev_err(dev, "can't get sata_epcs rx clock.\n");
+		return ret;
+	}
+
+	ret = clk_get_by_name(dev, "phy_pclk0", &imxpriv->phy_pclk0);
+	if (ret) {
+		dev_err(dev, "can't get sata_phy_pclk0 clock.\n");
+		return ret;
+	}
+
+	ret = clk_get_by_name(dev, "phy_pclk1", &imxpriv->phy_pclk1);
+	if (ret) {
+		dev_err(dev, "can't get sata_phy_pclk1 clock.\n");
+		return ret;
+	}
+
+	ret = clk_get_by_name(dev, "phy_apbclk", &imxpriv->phy_apbclk);
+	if (ret) {
+		dev_err(dev, "can't get sata_phy_apbclk clock.\n");
+		return ret;
+	}
+#endif
+
+	/* Fetch GPIO, then enable the external OSC */
+	ret = gpio_request_by_name(dev, "clkreq-gpio", 0, &imxpriv->clkreq_gpio,
+				   (GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE));
+	if (ret) {
+		dev_err(dev, "%d unable to get clkreq.\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+
+static int imx_sata_enable(struct udevice *dev)
+{
+	struct imx_ahci_priv *imxpriv = dev_get_priv(dev);
+	int ret = 0;
+
+	if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
+		/*
+		 * set PHY Paremeters, two steps to configure the GPR13,
+		 * one write for rest of parameters, mask of first write
+		 * is 0x07ffffff, and the other one write for setting
+		 * the mpll_clk_en.
+		 */
+		regmap_update_bits(imxpriv->gpr, 0x34,
+				   IOMUXC_GPR13_SATA_MASK,
+				   imxpriv->phy_params);
+		regmap_update_bits(imxpriv->gpr, 0x34,
+				   IOMUXC_GPR13_SATA_PHY_1_MASK,
+				   IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+		udelay(200);
+	}
+
+	if (imxpriv->type == AHCI_IMX6Q) {
+		ret = imx_sata_phy_reset(imxpriv);
+	} else if (imxpriv->type == AHCI_IMX6QP) {
+		/* 6qp adds the sata reset mechanism, use it for 6qp sata */
+		regmap_update_bits(imxpriv->gpr, 0x14,
+				   BIT(10), 0);
+
+		regmap_update_bits(imxpriv->gpr, 0x14,
+				   BIT(11), 0);
+		udelay(50);
+		regmap_update_bits(imxpriv->gpr, 0x14,
+				   BIT(11), BIT(11));
+	} else if (imxpriv->type == AHCI_IMX8QM) {
+		ret = imx8_sata_enable(dev);
+	}
+
+	if (ret) {
+		dev_err(dev, "failed to reset phy: %d\n", ret);
+		return ret;
+	}
+
+	udelay(2000);
+
+	return 0;
+}
+
+static void imx_sata_disable(struct udevice *dev)
+{
+	struct imx_ahci_priv *imxpriv = dev_get_priv(dev);
+
+	if (imxpriv->type == AHCI_IMX6QP)
+		regmap_update_bits(imxpriv->gpr, 0x14,
+				   BIT(10), BIT(10));
+
+	if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
+		regmap_update_bits(imxpriv->gpr, 0x34,
+				   IOMUXC_GPR13_SATA_PHY_1_MASK,
+				   0);
+	}
+
+	if (imxpriv->type == AHCI_IMX8QM) {
+#if CONFIG_IS_ENABLED(CLK)
+		clk_disable(&imxpriv->epcs_rx_clk);
+		clk_disable(&imxpriv->epcs_tx_clk);
+#endif
+	}
+}
+
+
+static int imx_ahci_bind(struct udevice *dev)
+{
+	struct udevice *scsi_dev;
+
+	return ahci_bind_scsi(dev, &scsi_dev);
+}
+
+static int imx_ahci_probe(struct udevice *dev)
+{
+	int ret = 0;
+	struct imx_ahci_priv *priv = dev_get_priv(dev);
+	fdt_addr_t addr;
+	unsigned int reg_val;
+
+	priv->type = (enum ahci_imx_type)dev_get_driver_data(dev);
+
+#if CONFIG_IS_ENABLED(CLK)
+	ret = clk_get_by_name(dev, "sata", &priv->sata_clk);
+	if (ret) {
+		printf("Failed to get sata clk\n");
+		return ret;
+	}
+
+	ret = clk_get_by_name(dev, "sata_ref", &priv->sata_ref_clk);
+	if (ret) {
+		printf("Failed to get sata_ref clk\n");
+		return ret;
+	}
+#endif
+
+	addr = dev_read_addr(dev);
+	if (addr == FDT_ADDR_T_NONE) {
+		dev_err(dev, "no mmio space\n");
+		return -EINVAL;
+	}
+
+	priv->mmio = (void __iomem *)addr;
+
+	if (priv->type == AHCI_IMX6Q || priv->type == AHCI_IMX6QP) {
+		priv->gpr = syscon_regmap_lookup_by_phandle(dev, "gpr");
+		if (IS_ERR(priv->gpr)) {
+			dev_err(dev,
+				"failed to find fsl,imx6q-iomux-gpr regmap\n");
+			return PTR_ERR(priv->gpr);
+		}
+
+		priv->phy_params =
+				   IOMUXC_GPR13_SATA_PHY_7_SATA2M |
+				   (3 << IOMUXC_GPR13_SATA_PHY_6_SHIFT) |
+				   IOMUXC_GPR13_SATA_SPEED_3G |
+				   IOMUXC_GPR13_SATA_PHY_2_TX_1P025V |
+				   IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB |
+				   IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 |
+				   IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB |
+				   IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED;
+	} else if (priv->type == AHCI_IMX8QM) {
+		ret =  imx8_sata_probe(dev, priv);
+		if (ret)
+			return ret;
+	}
+
+#if CONFIG_IS_ENABLED(CLK)
+	ret = clk_enable(&priv->sata_clk);
+	if (ret)
+		return ret;
+
+	ret = clk_enable(&priv->sata_ref_clk);
+	if (ret)
+		return ret;
+#else
+	enable_sata_clock();
+#endif
+
+	ret = imx_sata_enable(dev);
+	if (ret)
+		goto disable_clk;
+
+	/*
+	 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
+	 * and IP vendor specific register IMX_TIMER1MS.
+	 * Configure CAP_SSS (support stagered spin up).
+	 * Implement the port0.
+	 * Get the ahb clock rate, and configure the TIMER1MS register.
+	 */
+	reg_val = readl(priv->mmio + HOST_CAP);
+	if (!(reg_val & (1 << 27))) {
+		reg_val |= (1 << 27);
+		writel(reg_val, priv->mmio + HOST_CAP);
+	}
+	reg_val = readl(priv->mmio + HOST_PORTS_IMPL);
+	if (!(reg_val & 0x1)) {
+		reg_val |= 0x1;
+		writel(reg_val, priv->mmio + HOST_PORTS_IMPL);
+	}
+
+#if CONFIG_IS_ENABLED(CLK)
+	ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
+	if (ret) {
+		dev_info(dev, "no ahb clock.\n");
+	} else {
+		/*
+		 * AHB clock is only used to configure the vendor specified
+		 * TIMER1MS register. Set it if the AHB clock is defined.
+		 */
+		reg_val = clk_get_rate(&priv->ahb_clk) / 1000;
+		writel(reg_val, priv->mmio + IMX_TIMER1MS);
+	}
+#else
+	reg_val = mxc_get_clock(MXC_AHB_CLK) / 1000;
+	writel(reg_val, priv->mmio + IMX_TIMER1MS);
+#endif
+
+	ret = ahci_probe_scsi(dev, (ulong)priv->mmio);
+	if (ret)
+		goto disable_sata;
+
+	return ret;
+
+disable_sata:
+	imx_sata_disable(dev);
+disable_clk:
+#if CONFIG_IS_ENABLED(CLK)
+	clk_disable(&priv->sata_ref_clk);
+	clk_disable(&priv->sata_clk);
+#else
+	disable_sata_clock();
+#endif
+	return ret;
+}
+
+static int imx_ahci_remove(struct udevice *dev)
+{
+	imx_sata_disable(dev);
+
+#if CONFIG_IS_ENABLED(CLK)
+	struct imx_ahci_priv *priv = dev_get_priv(dev);
+	clk_disable(&priv->sata_ref_clk);
+	clk_disable(&priv->sata_clk);
+#else
+	disable_sata_clock();
+#endif
+
+	return 0;
+}
+
+
+static const struct udevice_id imx_ahci_ids[] = {
+	{ .compatible = "fsl,imx6q-ahci", .data = (ulong)AHCI_IMX6Q },
+	{ .compatible = "fsl,imx6qp-ahci", .data = (ulong)AHCI_IMX6QP },
+	{ .compatible = "fsl,imx8qm-ahci", .data = (ulong)AHCI_IMX8QM },
+	{ }
+};
+
+U_BOOT_DRIVER(imx_ahci) = {
+	.name	= "imx_ahci",
+	.id	= UCLASS_AHCI,
+	.of_match = imx_ahci_ids,
+	.bind	= imx_ahci_bind,
+	.probe	= imx_ahci_probe,
+	.remove	= imx_ahci_remove,
+	.priv_auto = sizeof(struct imx_ahci_priv),
+};
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index eff0fa134f7..58ee17062c5 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -18,17 +18,19 @@
 int clk_register(struct clk *clk, const char *drv_name,
 		 const char *name, const char *parent_name)
 {
-	struct udevice *parent;
+	struct udevice *parent = NULL;
 	struct driver *drv;
 	int ret;
 
-	ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent);
-	if (ret) {
-		log_err("%s: failed to get %s device (parent of %s)\n",
-			__func__, parent_name, name);
-	} else {
-		log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name,
-			  parent->name, parent);
+	if (parent_name) {
+		ret = uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent);
+		if (ret) {
+			log_err("%s: failed to get %s device (parent of %s)\n",
+				__func__, parent_name, name);
+		} else {
+			log_debug("%s: name: %s parent: %s [0x%p]\n", __func__, name,
+				  parent->name, parent);
+		}
 	}
 
 	drv = lists_driver_lookup_name(drv_name);
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index cdd348020b0..b892b953cd4 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -26,6 +26,7 @@ config SPL_CLK_IMX8MM
 	depends on ARCH_IMX8M && SPL
 	select SPL_CLK
 	select SPL_CLK_CCF
+	select SPL_CLK_COMPOSITE_CCF
 	help
 	  This enables SPL DM/DTS support for clock driver in i.MX8MM
 
@@ -34,6 +35,7 @@ config CLK_IMX8MM
 	depends on ARCH_IMX8M
 	select CLK
 	select CLK_CCF
+	select CLK_COMPOSITE_CCF
 	help
 	  This enables support clock driver for i.MX8MM platforms.
 
@@ -106,3 +108,21 @@ config CLK_IMXRT1050
 	select CLK_COMPOSITE_CCF
 	help
 	  This enables support clock driver for i.MXRT1050 platforms.
+
+config SPL_CLK_IMX93
+	bool "Enable i.MX93 clock driver"
+	depends on ARCH_IMX9 && SPL
+	select SPL_CLK
+	select SPL_CLK_CCF
+	select SPL_CLK_COMPOSITE_CCF
+	help
+	  Enable support for i.MX93 clocks.
+
+config CLK_IMX93
+	bool "Enable i.MX93 clock driver"
+	depends on ARCH_IMX9
+	select CLK
+	select CLK_CCF
+	select CLK_COMPOSITE_CCF
+	help
+	  Enable support for i.MX93 clocks.
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 01bbbdf3aea..2e44b249cbb 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
 
 ifdef CONFIG_CLK_IMX8
 obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
+obj-$(CONFIG_IMX8DXL) += clk-imx8qxp.o
 obj-$(CONFIG_IMX8QM) += clk-imx8qm.o
 endif
 obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \
@@ -19,3 +20,4 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \
 
 obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1020) += clk-imxrt1020.o
 obj-$(CONFIG_$(SPL_TPL_)CLK_IMXRT1050) += clk-imxrt1050.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_IMX93) += clk-imx93.o clk-fracn-gppll.o
diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
new file mode 100644
index 00000000000..fa2c2007606
--- /dev/null
+++ b/drivers/clk/imx/clk-fracn-gppll.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * Author: Alice Guo <alice.guo@nxp.com>
+ */
+
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <linux/bitfield.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+
+#include "clk.h"
+
+#define PLL_CTRL	0x00
+#define CLKMUX_BYPASS	BIT(2)
+#define CLKMUX_EN	BIT(1)
+#define POWERUP		BIT(0)
+#define PLL_NUMERATOR	0x40
+#define PLL_MFN_MASK	GENMASK(31, 2)
+#define PLL_DENOMINATOR	0x50
+#define PLL_MFD_MASK	GENMASK(29, 0)
+#define PLL_DIV		0x60
+#define PLL_MFI_MASK	GENMASK(24, 16)
+#define PLL_RDIV_MASK	GENMASK(15, 13)
+#define PLL_ODIV_MASK	GENMASK(7, 0)
+#define PLL_STATUS	0xf0
+#define PLL_LOCK	BIT(0)
+
+#define PLL_FRACN_GP(_rate, _mfi, _mfn, _mfd, _rdiv, _odiv)	\
+	{							\
+		.rate	=	(_rate),			\
+		.mfi	=	(_mfi),				\
+		.mfn	=	(_mfn),				\
+		.mfd	=	(_mfd),				\
+		.rdiv	=	(_rdiv),			\
+		.odiv	=	(_odiv),			\
+	}
+
+static const struct imx93_pll_fracn_gp fracn_tbl[] = {
+	PLL_FRACN_GP(650000000U, 81, 0, 1, 0, 3),
+	PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
+	PLL_FRACN_GP(560000000U, 70, 0, 1, 0, 3),
+	PLL_FRACN_GP(498000000U, 83, 0, 1, 0, 4),
+	PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
+	PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
+	PLL_FRACN_GP(400000000U, 50, 0, 1, 0, 3),
+	PLL_FRACN_GP(393216000U, 81, 92, 100, 0, 5),
+	PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)
+};
+
+struct imx93_pll {
+	struct clk	clk;
+	void __iomem	*base;
+	const struct imx93_pll_fracn_gp	*tbl;
+};
+
+#define to_imx93_pll(_c) container_of(_c, struct imx93_pll, clk)
+
+static int imx93_wait_pll_lock(struct imx93_pll *pll)
+{
+	u32 val;
+
+	return readl_poll_timeout(pll->base + PLL_STATUS, val, (val & PLL_LOCK), 200);
+}
+
+static const struct imx93_pll_fracn_gp *imx93_pll_get_cfg(struct imx93_pll *pll, ulong rate)
+{
+	const struct imx93_pll_fracn_gp	*tbl = pll->tbl;
+
+	for (int i = 0; i < ARRAY_SIZE(fracn_tbl); i++)
+		if (tbl[i].rate == rate)
+			return &tbl[i];
+
+	return NULL;
+}
+
+static ulong imx93_pll_set_rate(struct clk *clk, ulong rate)
+{
+	struct imx93_pll *pll = to_imx93_pll(clk);
+	const struct imx93_pll_fracn_gp	*cfg = NULL;
+	u32 tmp, pll_div, ana_mfn;
+	int ret;
+
+	cfg = imx93_pll_get_cfg(pll, rate);
+	if (!cfg)
+		return -EINVAL;
+
+	tmp = readl_relaxed(pll->base + PLL_CTRL);
+	tmp &= ~CLKMUX_EN;
+	writel_relaxed(tmp, pll->base + PLL_CTRL);
+	tmp &= ~POWERUP;
+	writel_relaxed(tmp, pll->base + PLL_CTRL);
+	tmp &= ~CLKMUX_BYPASS;
+	writel_relaxed(tmp, pll->base + PLL_CTRL);
+
+	pll_div = FIELD_PREP(PLL_MFI_MASK, cfg->mfi) |
+		  FIELD_PREP(PLL_RDIV_MASK, cfg->rdiv) | cfg->odiv;
+	writel_relaxed(pll_div, pll->base + PLL_DIV);
+	writel_relaxed(cfg->mfd, pll->base + PLL_DENOMINATOR);
+	writel_relaxed(FIELD_PREP(PLL_MFN_MASK, cfg->mfn), pll->base + PLL_NUMERATOR);
+
+	udelay(5);
+
+	tmp |= POWERUP;
+	writel_relaxed(tmp, pll->base + PLL_CTRL);
+
+	ret = imx93_wait_pll_lock(pll);
+	if (ret)
+		return ret;
+
+	tmp |= CLKMUX_EN;
+	writel_relaxed(tmp, pll->base + PLL_CTRL);
+
+	ana_mfn = FIELD_GET(PLL_MFN_MASK, readl_relaxed(pll->base + PLL_STATUS));
+	WARN(ana_mfn != cfg->mfn, "ana_mfn != cfg->mfn\n");
+
+	return 0;
+}
+
+static ulong imx93_pll_get_rate(struct clk *clk)
+{
+	struct imx93_pll *pll = to_imx93_pll(clk);
+	const struct imx93_pll_fracn_gp	*tbl = pll->tbl;
+	u32 pll_numerator, pll_denominator, pll_div;
+	u32 mfn, mfd, mfi, rdiv, odiv;
+	u64 fvco = clk_get_parent_rate(clk);
+
+	pll_numerator = readl_relaxed(pll->base + PLL_NUMERATOR);
+	mfn = FIELD_GET(PLL_MFN_MASK, pll_numerator);
+
+	pll_denominator = readl_relaxed(pll->base + PLL_DENOMINATOR);
+	mfd = FIELD_GET(PLL_MFD_MASK, pll_denominator);
+
+	pll_div = readl_relaxed(pll->base + PLL_DIV);
+	mfi = FIELD_GET(PLL_MFI_MASK, pll_div);
+	rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div);
+	odiv = FIELD_GET(PLL_ODIV_MASK, pll_div);
+
+	for (int i = 0; i < ARRAY_SIZE(fracn_tbl); i++)
+		if (tbl[i].mfn == mfn && tbl[i].mfd == mfd &&
+		    tbl[i].rdiv == rdiv && tbl[i].odiv == odiv)
+			return tbl[i].rate;
+
+	if (rdiv == 0)
+		rdiv = 1;
+
+	switch (odiv) {
+	case 0 /* 00000000b */:
+		odiv = 2;
+		break;
+	case 1 /* 00000001b */:
+		odiv = 3;
+		break;
+	case 127 /* 01111111b */:
+		odiv = 255;
+		break;
+	default:
+		break;
+	}
+
+	fvco = fvco * mfi * mfd + fvco * mfn;
+	do_div(fvco, mfd * rdiv * odiv);
+
+	return (ulong)fvco;
+}
+
+static int imx93_pll_enable(struct clk *clk)
+{
+	struct imx93_pll *pll = to_imx93_pll(clk);
+	u32 val;
+	int ret;
+
+	val = readl_relaxed(pll->base + PLL_CTRL);
+	if (val & POWERUP)
+		return 0;
+
+	val |= CLKMUX_BYPASS;
+	writel_relaxed(val, pll->base + PLL_CTRL);
+	val |= POWERUP;
+	writel_relaxed(val, pll->base + PLL_CTRL);
+	val |= CLKMUX_EN;
+	writel_relaxed(val, pll->base + PLL_CTRL);
+
+	ret = imx93_wait_pll_lock(pll);
+	if (ret)
+		return ret;
+
+	val &= ~CLKMUX_BYPASS;
+	writel_relaxed(val, pll->base + PLL_CTRL);
+
+	return 0;
+}
+
+static int imx93_pll_disable(struct clk *clk)
+{
+	struct imx93_pll *pll = to_imx93_pll(clk);
+	u32 val;
+
+	val = readl_relaxed(pll->base + PLL_CTRL);
+	val &= ~POWERUP;
+	writel_relaxed(val, pll->base + PLL_CTRL);
+
+	return 0;
+}
+
+static struct clk_ops imx93_pll_ops = {
+	.set_rate = imx93_pll_set_rate,
+	.get_rate = imx93_pll_get_rate,
+	.enable = imx93_pll_enable,
+	.disable = imx93_pll_disable,
+};
+
+struct clk *clk_register_imx93_pll(const char *name, const char *parent_name,
+				   void __iomem *base)
+{
+	struct imx93_pll *pll;
+	int ret;
+
+	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+	if (!pll)
+		return ERR_PTR(-ENOMEM);
+
+	pll->base = base;
+	pll->tbl = fracn_tbl;
+
+	ret = clk_register(&pll->clk, "imx93_pll", name, parent_name);
+	if (ret) {
+		printf("%s: failed to register pll: %d\n", __func__, ret);
+		kfree(pll);
+		return ERR_PTR(ret);
+	}
+
+	return &pll->clk;
+}
+
+U_BOOT_DRIVER(imx93_pll) = {
+	.name = "imx93_pll",
+	.id = UCLASS_CLK,
+	.ops = &imx93_pll_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c
index b3dc138c4bb..dc836bbc61b 100644
--- a/drivers/clk/imx/clk-imx8.c
+++ b/drivers/clk/imx/clk-imx8.c
@@ -14,32 +14,309 @@
 #include <dt-bindings/clock/imx8qxp-clock.h>
 #include <dt-bindings/soc/imx_rsrc.h>
 #include <misc.h>
+#include <asm/arch/lpcg.h>
 
 #include "clk-imx8.h"
 
-__weak ulong imx8_clk_get_rate(struct clk *clk)
+struct imx8_clks_collect *soc_data[] = {
+#if defined(CONFIG_IMX8QXP) || defined(CONFIG_IMX8DXL)
+	&imx8qxp_clk_collect,
+#endif
+#ifdef CONFIG_IMX8QM
+	&imx8qm_clk_collect,
+#endif
+};
+
+static ulong __imx8_clk_get_rate(struct udevice *dev, ulong id);
+static int __imx8_clk_enable(struct udevice *dev, ulong id, bool enable);
+static ulong __imx8_clk_set_rate(struct udevice *dev, ulong id, unsigned long rate);
+
+static struct imx8_clks_collect * find_clks_collect(struct udevice *dev)
+{
+	ulong data = (ulong)dev_get_driver_data(dev);
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(soc_data); i++) {
+		if (soc_data[i]->match_flag == data)
+			return soc_data[i];
+	}
+
+	return NULL;
+}
+
+static void * check_imx8_clk(struct udevice *dev, enum imx8_clk_type type, ulong id, u32 size_of_clk)
+{
+	u32 i, size;
+	struct imx8_clks_collect *clks_col = find_clks_collect(dev);
+	struct imx8_clk_header *hdr;
+	ulong clks;
+
+	if (!clks_col || !(clks_col->clks[type].type_clks)) {
+		printf("%s fails to get clks for type %d\n",
+		       __func__, type);
+		return NULL;
+	}
+
+	clks = (ulong)(clks_col->clks[type].type_clks);
+	size = clks_col->clks[type].num;
+
+	for (i = 0; i < size; i++) {
+		hdr = (struct imx8_clk_header *)clks;
+		if (id == hdr->id)
+			return (void *)hdr;
+
+		clks += size_of_clk;
+	}
+
+	return NULL;
+}
+
+static ulong imx8_get_rate_lpcg(struct udevice *dev, struct imx8_lpcg_clks *lpcg_clk)
+{
+	if (lpcg_clk->parent_id != 0) {
+		if (lpcg_is_clock_on(lpcg_clk->lpcg, lpcg_clk->bit_idx >> 2)) {
+			return __imx8_clk_get_rate(dev, lpcg_clk->parent_id);
+		} else {
+			return 0;
+		}
+	} else {
+		return -ENOSYS;
+	}
+}
+
+static ulong imx8_get_rate_slice(struct udevice *dev, struct imx8_clks *slice_clk)
+{
+	int ret;
+	u32 rate;
+
+	ret = sc_pm_get_clock_rate(-1, slice_clk->rsrc, slice_clk->pm_clk,
+				   (sc_pm_clock_rate_t *)&rate);
+	if (ret) {
+		printf("%s err %d\n", __func__, ret);
+		return ret;
+	}
+
+	return rate;
+}
+
+static ulong imx8_get_rate_fixed(struct udevice *dev, struct imx8_fixed_clks *fixed_clk)
+{
+	return fixed_clk->rate;
+}
+
+static ulong __imx8_clk_get_rate(struct udevice *dev, ulong id)
+{
+	void* clkdata;
+
+	clkdata = check_imx8_clk(dev, IMX8_CLK_LPCG, id, sizeof(struct imx8_lpcg_clks));
+	if (clkdata) {
+		return imx8_get_rate_lpcg(dev, (struct imx8_lpcg_clks *)clkdata);
+	}
+
+	clkdata = check_imx8_clk(dev, IMX8_CLK_SLICE, id, sizeof(struct imx8_clks));
+	if (clkdata) {
+		return imx8_get_rate_slice(dev, (struct imx8_clks *)clkdata);
+	}
+
+	clkdata = check_imx8_clk(dev, IMX8_CLK_FIXED, id, sizeof(struct imx8_fixed_clks));
+	if (clkdata) {
+		return imx8_get_rate_fixed(dev, (struct imx8_fixed_clks *)clkdata);
+	}
+
+	return -ENOSYS;
+}
+
+static ulong imx8_clk_get_rate(struct clk *clk)
+{
+	if (clk->id == 0)
+		return 0;
+
+	return __imx8_clk_get_rate(clk->dev, clk->id);
+}
+
+static ulong imx8_set_rate_lpcg(struct udevice *dev, struct imx8_lpcg_clks *lpcg_clk, unsigned long rate)
+{
+	if (lpcg_clk->parent_id != 0) {
+		return __imx8_clk_set_rate(dev, lpcg_clk->parent_id, rate);
+	} else {
+		return -ENOSYS;
+	}
+}
+
+static ulong imx8_set_rate_slice(struct udevice *dev, struct imx8_clks *slice_clk, unsigned long rate)
+{
+	int ret;
+	u32 new_rate = rate;
+
+	ret = sc_pm_set_clock_rate(-1, slice_clk->rsrc, slice_clk->pm_clk, &new_rate);
+	if (ret) {
+		printf("%s err %d\n", __func__, ret);
+		return ret;
+	}
+
+	return new_rate;
+}
+
+static ulong imx8_set_rate_gpr(struct udevice *dev, struct imx8_gpr_clks *gpr_clk, unsigned long rate)
+{
+	ulong parent_rate;
+	u32 val;
+	int ret;
+
+	if (gpr_clk->parent_id == 0)
+		return -ENOSYS;
+
+	parent_rate = __imx8_clk_get_rate(dev, gpr_clk->parent_id);
+	if (parent_rate > 0) {
+		val = (rate < parent_rate) ? 1 : 0;
+
+		ret = sc_misc_set_control(-1, gpr_clk->rsrc,
+			gpr_clk->gpr_id, val);
+		if (ret) {
+			printf("%s err %d\n", __func__, ret);
+			return ret;
+		}
+
+		return rate;
+	}
+
+	return -ENOSYS;
+}
+
+static ulong __imx8_clk_set_rate(struct udevice *dev, ulong id, unsigned long rate)
 {
+	void* clkdata;
+
+	clkdata = check_imx8_clk(dev, IMX8_CLK_SLICE, id, sizeof(struct imx8_clks));
+	if (clkdata) {
+		return imx8_set_rate_slice(dev, (struct imx8_clks *)clkdata, rate);
+	}
+
+	clkdata = check_imx8_clk(dev, IMX8_CLK_LPCG, id, sizeof(struct imx8_lpcg_clks));
+	if (clkdata) {
+		return imx8_set_rate_lpcg(dev, (struct imx8_lpcg_clks *)clkdata, rate);
+	}
+
+	clkdata = check_imx8_clk(dev, IMX8_CLK_GPR, id, sizeof(struct imx8_gpr_clks));
+	if (clkdata) {
+		return imx8_set_rate_gpr(dev, (struct imx8_gpr_clks *)clkdata, rate);
+	}
+
+	return -ENOSYS;
+}
+
+static ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	if (clk->id == 0)
+		return 0;
+
+	return __imx8_clk_set_rate(clk->dev, clk->id, rate);
+
+}
+
+static int imx8_enable_slice(struct udevice *dev, struct imx8_clks *slice_clk, bool enable)
+{
+	int ret;
+
+	ret = sc_pm_clock_enable(-1, slice_clk->rsrc, slice_clk->pm_clk, enable, 0);
+	if (ret) {
+		printf("%s err %d\n", __func__, ret);
+		return ret;
+	}
+
 	return 0;
 }
 
-__weak ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
+static int imx8_enable_lpcg(struct udevice *dev, struct imx8_lpcg_clks *lpcg_clk, bool enable)
 {
+	if (enable) {
+		if (lpcg_clk->parent_id != 0) {
+			__imx8_clk_enable(dev, lpcg_clk->parent_id, enable);
+		}
+
+		lpcg_clock_on(lpcg_clk->lpcg, lpcg_clk->bit_idx >> 2);
+	} else {
+		lpcg_clock_off(lpcg_clk->lpcg, lpcg_clk->bit_idx >> 2);
+
+		if (lpcg_clk->parent_id != 0) {
+			__imx8_clk_enable(dev, lpcg_clk->parent_id, enable);
+		}
+	}
+
 	return 0;
 }
 
-__weak int __imx8_clk_enable(struct clk *clk, bool enable)
+static int __imx8_clk_enable(struct udevice *dev, ulong id, bool enable)
 {
-	return -EINVAL;
+	void* clkdata;
+
+	clkdata = check_imx8_clk(dev, IMX8_CLK_LPCG, id, sizeof(struct imx8_lpcg_clks));
+	if (clkdata) {
+		return imx8_enable_lpcg(dev, (struct imx8_lpcg_clks *)clkdata, enable);
+	}
+
+	clkdata = check_imx8_clk(dev, IMX8_CLK_SLICE, id, sizeof(struct imx8_clks));
+	if (clkdata) {
+		return imx8_enable_slice(dev, (struct imx8_clks *)clkdata, enable);
+	}
+
+	return -ENOSYS;
 }
 
 static int imx8_clk_disable(struct clk *clk)
 {
-	return __imx8_clk_enable(clk, 0);
+	if (clk->id == 0)
+		return 0;
+
+	return __imx8_clk_enable(clk->dev, clk->id, 0);
 }
 
 static int imx8_clk_enable(struct clk *clk)
 {
-	return __imx8_clk_enable(clk, 1);
+	if (clk->id == 0)
+		return 0;
+
+	return __imx8_clk_enable(clk->dev, clk->id, 1);
+}
+
+static int imx8_set_parent_mux(struct udevice *dev, struct imx8_mux_clks *mux_clk, ulong pid)
+{
+	u32 i;
+	int ret;
+	struct imx8_clks *slice_clkdata;
+
+	slice_clkdata = check_imx8_clk(dev, IMX8_CLK_SLICE, mux_clk->slice_clk_id, sizeof(struct imx8_clks));
+	if (!slice_clkdata) {
+		printf("Error: fail to find slice clk %lu for this mux %lu\n", mux_clk->slice_clk_id, mux_clk->hdr.id);
+		return -EINVAL;
+	}
+
+	for (i = 0; i< CLK_IMX8_MAX_MUX_SEL; i++) {
+		if (pid == mux_clk->parent_clks[i]) {
+			ret = sc_pm_set_clock_parent(-1, slice_clkdata->rsrc,  slice_clkdata->pm_clk, i);
+			if (ret)
+				printf("Error: fail to set clock parent rsrc %d, pm_clk %d, parent clk %d\n",
+					slice_clkdata->rsrc,  slice_clkdata->pm_clk, i);
+			return ret;
+		}
+	}
+
+	return -ENOSYS;
+}
+
+static int imx8_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	void* clkdata;
+
+	if (clk->id == 0)
+		return 0;
+
+	clkdata = check_imx8_clk(clk->dev, IMX8_CLK_MUX, clk->id, sizeof(struct imx8_mux_clks));
+	if (clkdata) {
+		return imx8_set_parent_mux(clk->dev, (struct imx8_mux_clks *)clkdata, parent->id);
+	}
+
+	return -ENOSYS;
 }
 
 #if CONFIG_IS_ENABLED(CMD_CLK)
@@ -49,6 +326,9 @@ int soc_clk_dump(void)
 	struct clk clk;
 	unsigned long rate;
 	int i, ret;
+	u32 size;
+	struct imx8_clks *clks;
+	struct imx8_clks_collect *clks_col;
 
 	ret = uclass_get_device_by_driver(UCLASS_CLK,
 					  DM_DRIVER_GET(imx8_clk), &dev);
@@ -57,8 +337,19 @@ int soc_clk_dump(void)
 
 	printf("Clk\t\tHz\n");
 
-	for (i = 0; i < num_clks; i++) {
-		clk.id = imx8_clk_names[i].id;
+	clks_col = find_clks_collect(dev);
+
+	if (!clks_col || !(clks_col->clks[IMX8_CLK_SLICE].type_clks)) {
+		printf("%s fails to get clks for type %d\n",
+		       __func__, IMX8_CLK_SLICE);
+		return -ENODEV;
+	}
+
+	clks = (struct imx8_clks *)(clks_col->clks[IMX8_CLK_SLICE].type_clks);
+	size = clks_col->clks[IMX8_CLK_SLICE].num;
+
+	for (i = 0; i < size; i++) {
+		clk.id = clks[i].hdr.id;
 		ret = clk_request(dev, &clk);
 		if (ret < 0) {
 			debug("%s clk_request() failed: %d\n", __func__, ret);
@@ -72,21 +363,22 @@ int soc_clk_dump(void)
 
 		if (ret == -EINVAL) {
 			printf("clk ID %lu not supported yet\n",
-			       imx8_clk_names[i].id);
+			       clks[i].hdr.id);
 			continue;
 		}
 		if (ret < 0) {
 			printf("%s %lu: get_rate err: %d\n",
-			       __func__, imx8_clk_names[i].id, ret);
+			       __func__, clks[i].hdr.id, ret);
 			continue;
 		}
 
 		printf("%s(%3lu):\t%lu\n",
-		       imx8_clk_names[i].name, imx8_clk_names[i].id, rate);
+		       clks[i].hdr.name, clks[i].hdr.id, rate);
 	}
 
 	return 0;
 }
+
 #endif
 
 static struct clk_ops imx8_clk_ops = {
@@ -94,6 +386,7 @@ static struct clk_ops imx8_clk_ops = {
 	.get_rate = imx8_clk_get_rate,
 	.enable = imx8_clk_enable,
 	.disable = imx8_clk_disable,
+	.set_parent = imx8_clk_set_parent,
 };
 
 static int imx8_clk_probe(struct udevice *dev)
@@ -102,8 +395,8 @@ static int imx8_clk_probe(struct udevice *dev)
 }
 
 static const struct udevice_id imx8_clk_ids[] = {
-	{ .compatible = "fsl,imx8qxp-clk" },
-	{ .compatible = "fsl,imx8qm-clk" },
+	{ .compatible = "fsl,imx8qxp-clk", .data = FLAG_CLK_IMX8_IMX8QXP, },
+	{ .compatible = "fsl,imx8qm-clk", .data = FLAG_CLK_IMX8_IMX8QM, },
 	{ },
 };
 
diff --git a/drivers/clk/imx/clk-imx8.h b/drivers/clk/imx/clk-imx8.h
index 68ad6755e80..c0566f81171 100644
--- a/drivers/clk/imx/clk-imx8.h
+++ b/drivers/clk/imx/clk-imx8.h
@@ -4,16 +4,87 @@
  * Peng Fan <peng.fan@nxp.com>
  */
 
-struct imx8_clks {
+#define CLK_IMX8_MAX_MUX_SEL 5
+
+#define FLAG_CLK_IMX8_IMX8QM	BIT(0)
+#define FLAG_CLK_IMX8_IMX8QXP	BIT(1)
+
+struct imx8_clk_header {
 	ulong id;
+#if CONFIG_IS_ENABLED(CMD_CLK)
 	const char *name;
+#endif
+};
+
+struct imx8_clks {
+	struct imx8_clk_header hdr;
+	u16 rsrc;
+	sc_pm_clk_t pm_clk;
+};
+
+struct imx8_fixed_clks {
+	struct imx8_clk_header hdr;
+	ulong rate;
+};
+
+struct imx8_gpr_clks {
+	struct imx8_clk_header hdr;
+	u16 rsrc;
+	sc_ctrl_t gpr_id;
+	ulong parent_id;
+};
+
+struct imx8_lpcg_clks {
+	struct imx8_clk_header hdr;
+	u8 bit_idx;
+	u32 lpcg;
+	ulong parent_id;
+};
+
+struct imx8_mux_clks {
+	struct imx8_clk_header hdr;
+	ulong slice_clk_id;
+	ulong parent_clks[CLK_IMX8_MAX_MUX_SEL];
+};
+
+enum imx8_clk_type {
+	IMX8_CLK_SLICE 		= 0,
+	IMX8_CLK_FIXED 	= 1,
+	IMX8_CLK_GPR 		= 2,
+	IMX8_CLK_LPCG 		= 3,
+	IMX8_CLK_MUX 		= 4,
+	IMX8_CLK_END		= 5,
+};
+
+struct imx8_clk_pair {
+	void *type_clks;
+	u32 num;
+};
+
+struct imx8_clks_collect {
+	struct imx8_clk_pair clks[IMX8_CLK_END];
+	ulong match_flag;
 };
 
 #if CONFIG_IS_ENABLED(CMD_CLK)
-extern struct imx8_clks imx8_clk_names[];
-extern int num_clks;
+#define CLK_3(ID, NAME, MEM2) \
+	{ { ID, NAME, }, MEM2, }
+#define CLK_4(ID, NAME, MEM2, MEM3) \
+	{ { ID, NAME, }, MEM2, MEM3, }
+#define CLK_5(ID, NAME, MEM2, MEM3, MEM4) \
+	{ { ID, NAME, }, MEM2, MEM3, MEM4, }
+#define CLK_MUX(ID, NAME, MEM2, MUX0, MUX1, MUX2, MUX3, MUX4) \
+	{ { ID, NAME, }, MEM2, { MUX0, MUX1, MUX2, MUX3, MUX4} }
+#else
+#define CLK_3(ID, NAME, MEM2) \
+	{ { ID, }, MEM2, }
+#define CLK_4(ID, NAME, MEM2, MEM3) \
+	{ { ID, }, MEM2, MEM3, }
+#define CLK_5(ID, NAME, MEM2, MEM3, MEM4) \
+	{ { ID, }, MEM2, MEM3, MEM4, }
+#define CLK_MUX(ID, NAME, MEM2, MUX0, MUX1, MUX2, MUX3, MUX4) \
+	{ { ID, }, MEM2, { MUX0, MUX1, MUX2, MUX3, MUX4} }
 #endif
 
-ulong imx8_clk_get_rate(struct clk *clk);
-ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate);
-int __imx8_clk_enable(struct clk *clk, bool enable);
+extern struct imx8_clks_collect imx8qxp_clk_collect;
+extern struct imx8_clks_collect imx8qm_clk_collect;
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index c77500bcce0..435d5dc46b6 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -76,6 +76,10 @@ static const char *imx8mp_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll
 					"sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m",
 					"audio_pll1_out", "sys_pll3_out", };
 
+static const char * const imx8mp_hsio_axi_sels[] = {"clock-osc-24m", "sys_pll2_500m", "sys_pll1_800m",
+						    "sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
+						    "clk_ext4", "audio_pll2_out", };
+
 static const char *imx8mp_main_axi_sels[] = {"clock-osc-24m", "sys_pll2_333m", "sys_pll1_800m",
 					     "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
 					     "video_pll1_out", "sys_pll1_100m",};
@@ -156,6 +160,14 @@ static const char *imx8mp_uart4_sels[] = {"clock-osc-24m", "sys_pll1_80m", "sys_
 					  "sys_pll2_100m", "sys_pll3_out", "clk_ext2",
 					  "clk_ext3", "audio_pll2_out", };
 
+static const char * const imx8mp_usb_core_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+					"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
+					"clk_ext3", "audio_pll2_out", };
+
+static const char * const imx8mp_usb_phy_ref_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m",
+					"sys_pll2_100m", "sys_pll2_200m", "clk_ext2",
+					"clk_ext3", "audio_pll2_out", };
+
 static const char *imx8mp_gic_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
 					"sys_pll2_100m", "sys_pll1_800m",
 					"sys_pll2_500m", "clk_ext4", "audio_pll2_out" };
@@ -277,9 +289,17 @@ static struct clk_ops imx8mp_clk_ops = {
 static int imx8mp_clk_probe(struct udevice *dev)
 {
 	void __iomem *base;
+	struct clk osc_24m_clk;
+	int ret;
 
 	base = (void *)ANATOP_BASE_ADDR;
 
+	ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk);
+	if (ret)
+		return ret;
+
+	clk_dm(IMX8MP_CLK_24M, dev_get_clk_ptr(osc_24m_clk.dev));
+
 	clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
 	clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
@@ -332,6 +352,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
 	clk_dm(IMX8MP_CLK_A53_CG, imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
 	clk_dm(IMX8MP_CLK_A53_DIV, imx_clk_divider2("arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3));
 
+	clk_dm(IMX8MP_CLK_HSIO_AXI, imx8m_clk_composite("hsio_axi", imx8mp_hsio_axi_sels, base + 0x8380));
+
 	clk_dm(IMX8MP_CLK_MAIN_AXI, imx8m_clk_composite_critical("main_axi", imx8mp_main_axi_sels, base + 0x8800));
 	clk_dm(IMX8MP_CLK_ENET_AXI, imx8m_clk_composite_critical("enet_axi", imx8mp_enet_axi_sels, base + 0x8880));
 	clk_dm(IMX8MP_CLK_NAND_USDHC_BUS, imx8m_clk_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, base + 0x8900));
@@ -361,6 +383,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
 	clk_dm(IMX8MP_CLK_UART2, imx8m_clk_composite("uart2", imx8mp_uart2_sels, base + 0xaf80));
 	clk_dm(IMX8MP_CLK_UART3, imx8m_clk_composite("uart3", imx8mp_uart3_sels, base + 0xb000));
 	clk_dm(IMX8MP_CLK_UART4, imx8m_clk_composite("uart4", imx8mp_uart4_sels, base + 0xb080));
+	clk_dm(IMX8MP_CLK_USB_CORE_REF, imx8m_clk_composite("usb_core_ref", imx8mp_usb_core_ref_sels, base + 0xb100));
+	clk_dm(IMX8MP_CLK_USB_PHY_REF, imx8m_clk_composite("usb_phy_ref", imx8mp_usb_phy_ref_sels, base + 0xb180));
 	clk_dm(IMX8MP_CLK_GIC, imx8m_clk_composite_critical("gic", imx8mp_gic_sels, base + 0xb200));
 
 	clk_dm(IMX8MP_CLK_WDOG, imx8m_clk_composite("wdog", imx8mp_wdog_sels, base + 0xb900));
@@ -389,6 +413,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
 	clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0));
 	clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0));
 	clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk", "uart4", base + 0x44c0, 0));
+	clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk", "clock-osc-32k", base + 0x44d0, 0));
+	clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
 	clk_dm(IMX8MP_CLK_USDHC1_ROOT, imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
 	clk_dm(IMX8MP_CLK_USDHC2_ROOT, imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
 	clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c
index 7759dc63ee1..848b8aff737 100644
--- a/drivers/clk/imx/clk-imx8qm.c
+++ b/drivers/clk/imx/clk-imx8qm.c
@@ -13,338 +13,217 @@
 #include <dt-bindings/clock/imx8qm-clock.h>
 #include <dt-bindings/soc/imx_rsrc.h>
 #include <misc.h>
+#include <asm/arch/lpcg.h>
 
 #include "clk-imx8.h"
 
-#if CONFIG_IS_ENABLED(CMD_CLK)
-struct imx8_clks imx8_clk_names[] = {
-	{ IMX8QM_A53_DIV, "A53_DIV" },
-	{ IMX8QM_UART0_CLK, "UART0" },
-	{ IMX8QM_UART1_CLK, "UART1" },
-	{ IMX8QM_UART2_CLK, "UART2" },
-	{ IMX8QM_UART3_CLK, "UART3" },
-	{ IMX8QM_SDHC0_CLK, "SDHC0" },
-	{ IMX8QM_SDHC1_CLK, "SDHC1" },
-	{ IMX8QM_SDHC2_CLK, "SDHC2" },
-	{ IMX8QM_ENET0_AHB_CLK, "ENET0_AHB" },
-	{ IMX8QM_ENET0_IPG_CLK, "ENET0_IPG" },
-	{ IMX8QM_ENET0_REF_DIV, "ENET0_REF" },
-	{ IMX8QM_ENET0_PTP_CLK, "ENET0_PTP" },
-	{ IMX8QM_ENET1_AHB_CLK, "ENET1_AHB" },
-	{ IMX8QM_ENET1_IPG_CLK, "ENET1_IPG" },
-	{ IMX8QM_ENET1_REF_DIV, "ENET1_REF" },
-	{ IMX8QM_ENET1_PTP_CLK, "ENET1_PTP" },
+static struct imx8_clks imx8qm_clks[] = {
+	CLK_4( IMX8QM_A53_DIV, "A53_DIV", SC_R_A53, SC_PM_CLK_CPU ),
+	CLK_4( IMX8QM_A72_DIV, "A72_DIV", SC_R_A72, SC_PM_CLK_CPU ),
+	CLK_4( IMX8QM_I2C0_DIV, "I2C0_DIV", SC_R_I2C_0, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_I2C1_DIV, "I2C1_DIV", SC_R_I2C_1, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_I2C2_DIV, "I2C2_DIV", SC_R_I2C_2, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_I2C3_DIV, "I2C3_DIV", SC_R_I2C_3, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_LVDS0_I2C0_DIV, "LVDS0 I2C0 DIV", SC_R_LVDS_0_I2C_0, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_LVDS0_I2C1_DIV, "LVDS0 I2C1 DIV", SC_R_LVDS_0_I2C_1, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_LVDS1_I2C0_DIV, "LVDS1 I2C0 DIV", SC_R_LVDS_1_I2C_0, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_LVDS1_I2C1_DIV, "LVDS1 I2C1 DIV", SC_R_LVDS_1_I2C_1, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_MIPI0_I2C0_DIV, "MIPI0 I2C0_DIV", SC_R_MIPI_0_I2C_0, SC_PM_CLK_MISC2 ),
+	CLK_4( IMX8QM_MIPI0_I2C1_DIV, "MIPI0 I2C1_DIV", SC_R_MIPI_0_I2C_1, SC_PM_CLK_MISC2 ),
+	CLK_4( IMX8QM_MIPI1_I2C0_DIV, "MIPI1 I2C0_DIV", SC_R_MIPI_1_I2C_0, SC_PM_CLK_MISC2 ),
+	CLK_4( IMX8QM_MIPI1_I2C1_DIV, "MIPI1 I2C1_DIV", SC_R_MIPI_1_I2C_1, SC_PM_CLK_MISC2 ),
+	CLK_4( IMX8QM_CSI0_I2C0_DIV, "CSI0 I2C0_DIV", SC_R_CSI_0_I2C_0, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_CSI1_I2C0_DIV, "CSI1 I2C0_DIV", SC_R_CSI_1_I2C_0, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_HDMI_I2C0_DIV, "HDMI I2C0_DIV", SC_R_HDMI_I2C_0, SC_PM_CLK_MISC2 ),
+	CLK_4( IMX8QM_HDMI_IPG_CLK, "HDMI IPG_CLK", SC_R_HDMI, SC_PM_CLK_MISC ),
+	CLK_4( IMX8QM_HDMI_RX_I2C0_DIV, "HDMI RX I2C_DIV", SC_R_HDMI_RX_I2C_0, SC_PM_CLK_MISC2 ),
+	CLK_4( IMX8QM_UART0_DIV, "UART0_DIV", SC_R_UART_0, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_UART1_DIV, "UART1_DIV", SC_R_UART_1, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_UART2_DIV, "UART2_DIV", SC_R_UART_2, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_UART3_DIV, "UART3_DIV", SC_R_UART_3, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_SDHC0_DIV, "SDHC0_DIV", SC_R_SDHC_0, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_SDHC1_DIV, "SDHC1_DIV", SC_R_SDHC_1, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_SDHC2_DIV, "SDHC2_DIV", SC_R_SDHC_2, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_ENET0_ROOT_DIV, "ENET0_ROOT_DIV", SC_R_ENET_0, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_ENET0_RGMII_DIV, "ENET0_RGMII_DIV", SC_R_ENET_0, SC_PM_CLK_MISC0 ),
+	CLK_4( IMX8QM_ENET1_ROOT_DIV, "ENET1_ROOT_DIV", SC_R_ENET_1, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_ENET1_RGMII_DIV, "ENET1_RGMII_DIV", SC_R_ENET_1, SC_PM_CLK_MISC0 ),
+
+	CLK_4( IMX8QM_USB3_ACLK_DIV, "USB3_ACLK_DIV", SC_R_USB_2, SC_PM_CLK_PER ),
+	CLK_4( IMX8QM_USB3_BUS_DIV, "USB3_BUS_DIV", SC_R_USB_2, SC_PM_CLK_MST_BUS ),
+	CLK_4( IMX8QM_USB3_LPM_DIV, "USB3_LPM_DIV", SC_R_USB_2, SC_PM_CLK_MISC ),
+
+	CLK_4( IMX8QM_FSPI0_DIV, "FSPI0_DIV", SC_R_FSPI_0, SC_PM_CLK_PER ),
+
+	CLK_4( IMX8QM_GPMI_BCH_IO_DIV, "GPMI_IO_DIV", SC_R_NAND, SC_PM_CLK_MST_BUS ),
+	CLK_4( IMX8QM_GPMI_BCH_DIV, "GPMI_BCH_DIV", SC_R_NAND, SC_PM_CLK_PER ),
 };
 
-int num_clks = ARRAY_SIZE(imx8_clk_names);
-#endif
-
-ulong imx8_clk_get_rate(struct clk *clk)
-{
-	sc_pm_clk_t pm_clk;
-	ulong rate;
-	u16 resource;
-	int ret;
-
-	debug("%s(#%lu)\n", __func__, clk->id);
-
-	switch (clk->id) {
-	case IMX8QM_A53_DIV:
-		resource = SC_R_A53;
-		pm_clk = SC_PM_CLK_CPU;
-		break;
-	case IMX8QM_I2C0_IPG_CLK:
-	case IMX8QM_I2C0_CLK:
-	case IMX8QM_I2C0_DIV:
-		resource = SC_R_I2C_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_I2C1_IPG_CLK:
-	case IMX8QM_I2C1_CLK:
-	case IMX8QM_I2C1_DIV:
-		resource = SC_R_I2C_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_I2C2_IPG_CLK:
-	case IMX8QM_I2C2_CLK:
-	case IMX8QM_I2C2_DIV:
-		resource = SC_R_I2C_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_I2C3_IPG_CLK:
-	case IMX8QM_I2C3_CLK:
-	case IMX8QM_I2C3_DIV:
-		resource = SC_R_I2C_3;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_SDHC0_IPG_CLK:
-	case IMX8QM_SDHC0_CLK:
-	case IMX8QM_SDHC0_DIV:
-		resource = SC_R_SDHC_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_SDHC1_IPG_CLK:
-	case IMX8QM_SDHC1_CLK:
-	case IMX8QM_SDHC1_DIV:
-		resource = SC_R_SDHC_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_SDHC2_IPG_CLK:
-	case IMX8QM_SDHC2_CLK:
-	case IMX8QM_SDHC2_DIV:
-		resource = SC_R_SDHC_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_UART0_IPG_CLK:
-	case IMX8QM_UART0_CLK:
-		resource = SC_R_UART_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_UART1_CLK:
-		resource = SC_R_UART_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_UART2_CLK:
-		resource = SC_R_UART_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_UART3_CLK:
-		resource = SC_R_UART_3;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_ENET0_IPG_CLK:
-	case IMX8QM_ENET0_AHB_CLK:
-	case IMX8QM_ENET0_REF_DIV:
-	case IMX8QM_ENET0_PTP_CLK:
-		resource = SC_R_ENET_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_ENET1_IPG_CLK:
-	case IMX8QM_ENET1_AHB_CLK:
-	case IMX8QM_ENET1_REF_DIV:
-	case IMX8QM_ENET1_PTP_CLK:
-		resource = SC_R_ENET_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	default:
-		if (clk->id < IMX8QM_UART0_IPG_CLK ||
-		    clk->id >= IMX8QM_CLK_END) {
-			printf("%s(Invalid clk ID #%lu)\n",
-			       __func__, clk->id);
-			return -EINVAL;
-		}
-		return -EINVAL;
-	};
-
-	ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
-				   (sc_pm_clock_rate_t *)&rate);
-	if (ret) {
-		printf("%s err %d\n", __func__, ret);
-		return ret;
-	}
-
-	return rate;
-}
-
-ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
-{
-	sc_pm_clk_t pm_clk;
-	u32 new_rate = rate;
-	u16 resource;
-	int ret;
-
-	debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
-
-	switch (clk->id) {
-	case IMX8QM_I2C0_IPG_CLK:
-	case IMX8QM_I2C0_CLK:
-	case IMX8QM_I2C0_DIV:
-		resource = SC_R_I2C_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_I2C1_IPG_CLK:
-	case IMX8QM_I2C1_CLK:
-	case IMX8QM_I2C1_DIV:
-		resource = SC_R_I2C_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_I2C2_IPG_CLK:
-	case IMX8QM_I2C2_CLK:
-	case IMX8QM_I2C2_DIV:
-		resource = SC_R_I2C_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_I2C3_IPG_CLK:
-	case IMX8QM_I2C3_CLK:
-	case IMX8QM_I2C3_DIV:
-		resource = SC_R_I2C_3;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_UART0_CLK:
-		resource = SC_R_UART_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_UART1_CLK:
-		resource = SC_R_UART_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_UART2_CLK:
-		resource = SC_R_UART_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_UART3_CLK:
-		resource = SC_R_UART_3;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_SDHC0_IPG_CLK:
-	case IMX8QM_SDHC0_CLK:
-	case IMX8QM_SDHC0_DIV:
-		resource = SC_R_SDHC_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_SDHC1_IPG_CLK:
-	case IMX8QM_SDHC1_CLK:
-	case IMX8QM_SDHC1_DIV:
-		resource = SC_R_SDHC_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_SDHC2_IPG_CLK:
-	case IMX8QM_SDHC2_CLK:
-	case IMX8QM_SDHC2_DIV:
-		resource = SC_R_SDHC_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_ENET0_IPG_CLK:
-	case IMX8QM_ENET0_AHB_CLK:
-	case IMX8QM_ENET0_REF_DIV:
-	case IMX8QM_ENET0_PTP_CLK:
-	case IMX8QM_ENET0_ROOT_DIV:
-		resource = SC_R_ENET_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_ENET1_IPG_CLK:
-	case IMX8QM_ENET1_AHB_CLK:
-	case IMX8QM_ENET1_REF_DIV:
-	case IMX8QM_ENET1_PTP_CLK:
-	case IMX8QM_ENET1_ROOT_DIV:
-		resource = SC_R_ENET_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	default:
-		if (clk->id < IMX8QM_UART0_IPG_CLK ||
-		    clk->id >= IMX8QM_CLK_END) {
-			printf("%s(Invalid clk ID #%lu)\n",
-			       __func__, clk->id);
-			return -EINVAL;
-		}
-		return -EINVAL;
-	};
-
-	ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate);
-	if (ret) {
-		printf("%s err %d\n", __func__, ret);
-		return ret;
-	}
-
-	return new_rate;
-}
-
-int __imx8_clk_enable(struct clk *clk, bool enable)
-{
-	sc_pm_clk_t pm_clk;
-	u16 resource;
-	int ret;
+static struct imx8_fixed_clks imx8qm_fixed_clks[] = {
+	CLK_3( IMX8QM_IPG_CONN_CLK_ROOT, "IPG_CONN_CLK", SC_83MHZ ),
+	CLK_3( IMX8QM_AHB_CONN_CLK_ROOT, "AHB_CONN_CLK", SC_166MHZ ),
+	CLK_3( IMX8QM_AXI_CONN_CLK_ROOT, "AXI_CONN_CLK", SC_333MHZ ),
+	CLK_3( IMX8QM_IPG_DMA_CLK_ROOT, "IPG_DMA_CLK", SC_120MHZ ),
+	CLK_3( IMX8QM_IPG_MIPI_CSI_CLK_ROOT, "IPG_MIPI_CLK", SC_120MHZ ),
+	CLK_3( IMX8QM_LVDS_IPG_CLK, "IPG_LVDS_CLK", SC_24MHZ ),
+	CLK_3( IMX8QM_LSIO_BUS_CLK, "LSIO_BUS_CLK", SC_100MHZ ),
+	CLK_3( IMX8QM_LSIO_MEM_CLK, "LSIO_MEM_CLK", SC_200MHZ ),
+	CLK_3( IMX8QM_MIPI0_CLK_ROOT, "MIPI0_CLK", SC_120MHZ ),
+	CLK_3( IMX8QM_MIPI1_CLK_ROOT, "MIPI1_CLK", SC_120MHZ ),
+	CLK_3( IMX8QM_HDMI_RX_IPG_CLK, "HDMI_RX_IPG_CLK", SC_200MHZ ),
+	CLK_3( IMX8QM_HSIO_PER_CLK, "HSIO_CLK", SC_133MHZ ),
+	CLK_3( IMX8QM_HSIO_AXI_CLK, "HSIO_AXI", SC_400MHZ ),
+};
 
-	debug("%s(#%lu)\n", __func__, clk->id);
+static struct imx8_gpr_clks imx8qm_gpr_clks[] = {
+	CLK_5( IMX8QM_ENET0_REF_DIV, "ENET0_REF_DIV", SC_R_ENET_0, SC_C_CLKDIV, IMX8QM_ENET0_ROOT_DIV ),
+	CLK_4( IMX8QM_ENET0_REF_25MHZ_125MHZ_SEL, "ENET0_REF_25_125", SC_R_ENET_0, SC_C_SEL_125 ),
+	CLK_4( IMX8QM_ENET0_RMII_TX_SEL, "ENET0_RMII_TX", SC_R_ENET_0, SC_C_TXCLK ),
+	CLK_4( IMX8QM_ENET0_REF_25MHZ_125MHZ_CLK, "ENET0_REF_25_125_CLK", SC_R_ENET_0, SC_C_DISABLE_125 ),
+	CLK_4( IMX8QM_ENET0_REF_50MHZ_CLK, "ENET0_REF_50", SC_R_ENET_0, SC_C_DISABLE_50 ),
+
+	CLK_5( IMX8QM_ENET1_REF_DIV, "ENET1_REF_DIV", SC_R_ENET_1, SC_C_CLKDIV, IMX8QM_ENET1_ROOT_DIV ),
+	CLK_4( IMX8QM_ENET1_REF_25MHZ_125MHZ_SEL, "ENET1_REF_25_125", SC_R_ENET_1, SC_C_SEL_125 ),
+	CLK_4( IMX8QM_ENET1_RMII_TX_SEL, "ENET1_RMII_TX", SC_R_ENET_1, SC_C_TXCLK ),
+	CLK_4( IMX8QM_ENET1_REF_25MHZ_125MHZ_CLK, "ENET1_REF_25_125_CLK", SC_R_ENET_1, SC_C_DISABLE_125 ),
+	CLK_4( IMX8QM_ENET1_REF_50MHZ_CLK, "ENET1_REF_50", SC_R_ENET_1, SC_C_DISABLE_50 ),
+};
 
-	switch (clk->id) {
-	case IMX8QM_I2C0_IPG_CLK:
-	case IMX8QM_I2C0_CLK:
-	case IMX8QM_I2C0_DIV:
-		resource = SC_R_I2C_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_I2C1_IPG_CLK:
-	case IMX8QM_I2C1_CLK:
-	case IMX8QM_I2C1_DIV:
-		resource = SC_R_I2C_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_I2C2_IPG_CLK:
-	case IMX8QM_I2C2_CLK:
-	case IMX8QM_I2C2_DIV:
-		resource = SC_R_I2C_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_I2C3_IPG_CLK:
-	case IMX8QM_I2C3_CLK:
-	case IMX8QM_I2C3_DIV:
-		resource = SC_R_I2C_3;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_UART0_CLK:
-		resource = SC_R_UART_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_UART1_CLK:
-		resource = SC_R_UART_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_UART2_CLK:
-		resource = SC_R_UART_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_UART3_CLK:
-		resource = SC_R_UART_3;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_SDHC0_IPG_CLK:
-	case IMX8QM_SDHC0_CLK:
-	case IMX8QM_SDHC0_DIV:
-		resource = SC_R_SDHC_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_SDHC1_IPG_CLK:
-	case IMX8QM_SDHC1_CLK:
-	case IMX8QM_SDHC1_DIV:
-		resource = SC_R_SDHC_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_SDHC2_IPG_CLK:
-	case IMX8QM_SDHC2_CLK:
-	case IMX8QM_SDHC2_DIV:
-		resource = SC_R_SDHC_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_ENET0_IPG_CLK:
-	case IMX8QM_ENET0_AHB_CLK:
-	case IMX8QM_ENET0_REF_DIV:
-	case IMX8QM_ENET0_PTP_CLK:
-		resource = SC_R_ENET_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QM_ENET1_IPG_CLK:
-	case IMX8QM_ENET1_AHB_CLK:
-	case IMX8QM_ENET1_REF_DIV:
-	case IMX8QM_ENET1_PTP_CLK:
-		resource = SC_R_ENET_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	default:
-		if (clk->id < IMX8QM_UART0_IPG_CLK ||
-		    clk->id >= IMX8QM_CLK_END) {
-			printf("%s(Invalid clk ID #%lu)\n",
-			       __func__, clk->id);
-			return -EINVAL;
-		}
-		return -EINVAL;
-	}
+static struct imx8_lpcg_clks imx8qm_lpcg_clks[] = {
+	CLK_5( IMX8QM_I2C0_CLK, "I2C0_CLK", 0, LPI2C_0_LPCG, IMX8QM_I2C0_DIV ),
+	CLK_5( IMX8QM_I2C0_IPG_CLK, "I2C0_IPG", 16, LPI2C_0_LPCG, IMX8QM_IPG_DMA_CLK_ROOT ),
+	CLK_5( IMX8QM_I2C1_CLK, "I2C1_CLK", 0, LPI2C_1_LPCG, IMX8QM_I2C1_DIV ),
+	CLK_5( IMX8QM_I2C1_IPG_CLK, "I2C1_IPG", 16, LPI2C_1_LPCG, IMX8QM_IPG_DMA_CLK_ROOT ),
+	CLK_5( IMX8QM_I2C2_CLK, "I2C2_CLK", 0, LPI2C_2_LPCG, IMX8QM_I2C2_DIV ),
+	CLK_5( IMX8QM_I2C2_IPG_CLK, "I2C2_IPG", 16, LPI2C_2_LPCG, IMX8QM_IPG_DMA_CLK_ROOT ),
+	CLK_5( IMX8QM_I2C3_CLK, "I2C3_CLK", 0, LPI2C_3_LPCG, IMX8QM_I2C3_DIV ),
+	CLK_5( IMX8QM_I2C3_IPG_CLK, "I2C3_IPG", 16, LPI2C_3_LPCG, IMX8QM_IPG_DMA_CLK_ROOT ),
+
+	CLK_5( IMX8QM_LVDS0_I2C0_CLK, "LVDS0_I2C0_CLK", 0, DI_LVDS_0_LPCG + 0x10, IMX8QM_LVDS0_I2C0_DIV ),
+	CLK_5( IMX8QM_LVDS0_I2C0_IPG_CLK, "LVDS0_I2C0_IPG", 16, DI_LVDS_0_LPCG + 0x10, IMX8QM_LVDS_IPG_CLK ),
+	CLK_5( IMX8QM_LVDS0_I2C1_CLK, "LVDS0_I2C1_CLK", 0, DI_LVDS_0_LPCG + 0x14, IMX8QM_LVDS0_I2C1_DIV ),
+	CLK_5( IMX8QM_LVDS0_I2C1_IPG_CLK, "LVDS0_I2C1_IPG", 16, DI_LVDS_0_LPCG + 0x14, IMX8QM_LVDS_IPG_CLK ),
+	CLK_5( IMX8QM_LVDS1_I2C0_CLK, "LVDS1_I2C0_CLK", 0, DI_LVDS_1_LPCG + 0x10, IMX8QM_LVDS1_I2C0_DIV ),
+	CLK_5( IMX8QM_LVDS1_I2C0_IPG_CLK, "LVDS1_I2C0_IPG", 16, DI_LVDS_1_LPCG + 0x10, IMX8QM_LVDS_IPG_CLK ),
+	CLK_5( IMX8QM_LVDS1_I2C1_CLK, "LVDS1_I2C1_CLK", 0, DI_LVDS_1_LPCG + 0x14, IMX8QM_LVDS1_I2C1_DIV ),
+	CLK_5( IMX8QM_LVDS1_I2C1_IPG_CLK, "LVDS1_I2C1_IPG", 16, DI_LVDS_1_LPCG + 0x14, IMX8QM_LVDS_IPG_CLK ),
+
+	CLK_5( IMX8QM_MIPI0_I2C0_CLK, "MIPI0_I2C0_CLK", 0, MIPI_DSI_0_LPCG + 0x1c, IMX8QM_MIPI0_I2C0_DIV ),
+	CLK_5( IMX8QM_MIPI0_I2C0_IPG_CLK, "MIPI0_I2C0_IPG", 0, MIPI_DSI_0_LPCG + 0x14,  IMX8QM_MIPI0_I2C0_IPG_S_CLK),
+	CLK_5( IMX8QM_MIPI0_I2C0_IPG_S_CLK, "MIPI0_I2C0_IPG_S", 0, MIPI_DSI_0_LPCG + 0x18, IMX8QM_MIPI0_CLK_ROOT ),
+	CLK_5( IMX8QM_MIPI0_I2C1_CLK, "MIPI0_I2C1_CLK", 0, MIPI_DSI_0_LPCG + 0x2c, IMX8QM_MIPI0_I2C1_DIV ),
+	CLK_5( IMX8QM_MIPI0_I2C1_IPG_CLK, "MIPI0_I2C1_IPG", 0, MIPI_DSI_0_LPCG + 0x24,  IMX8QM_MIPI0_I2C1_IPG_S_CLK),
+	CLK_5( IMX8QM_MIPI0_I2C1_IPG_S_CLK, "MIPI0_I2C1_IPG_S", 0, MIPI_DSI_0_LPCG + 0x28, IMX8QM_MIPI0_CLK_ROOT ),
+	CLK_5( IMX8QM_MIPI1_I2C0_CLK, "MIPI1_I2C0_CLK", 0, MIPI_DSI_1_LPCG + 0x1c, IMX8QM_MIPI1_I2C0_DIV ),
+	CLK_5( IMX8QM_MIPI1_I2C0_IPG_CLK, "MIPI1_I2C0_IPG", 0, MIPI_DSI_1_LPCG + 0x14, IMX8QM_MIPI1_I2C0_IPG_S_CLK),
+	CLK_5( IMX8QM_MIPI1_I2C0_IPG_S_CLK, "MIPI1_I2C0_IPG_S", 0, MIPI_DSI_1_LPCG + 0x18, IMX8QM_MIPI1_CLK_ROOT ),
+	CLK_5( IMX8QM_MIPI1_I2C1_CLK, "MIPI1_I2C1_CLK", 0, MIPI_DSI_1_LPCG + 0x2c, IMX8QM_MIPI1_I2C1_DIV ),
+	CLK_5( IMX8QM_MIPI1_I2C1_IPG_CLK, "MIPI1_I2C1_IPG", 0, MIPI_DSI_1_LPCG + 0x24, IMX8QM_MIPI1_I2C1_IPG_S_CLK),
+	CLK_5( IMX8QM_MIPI1_I2C1_IPG_S_CLK, "MIPI1_I2C1_IPG_S", 0, MIPI_DSI_1_LPCG + 0x28, IMX8QM_MIPI1_CLK_ROOT ),
+
+	CLK_5( IMX8QM_CSI0_I2C0_CLK, "CSI0_I2C0_CLK", 0, MIPI_CSI_0_LPCG + 0x14, IMX8QM_CSI0_I2C0_DIV ),
+	CLK_5( IMX8QM_CSI0_I2C0_IPG_CLK, "CSI0_I2C0_IPG", 16, MIPI_CSI_0_LPCG + 0x14, IMX8QM_IPG_MIPI_CSI_CLK_ROOT ),
+	CLK_5( IMX8QM_CSI1_I2C0_CLK, "CSI1_I2C0_CLK", 0, MIPI_CSI_1_LPCG + 0x14, IMX8QM_CSI1_I2C0_DIV ),
+	CLK_5( IMX8QM_CSI1_I2C0_IPG_CLK, "CSI1_I2C0_IPG", 16, MIPI_CSI_1_LPCG + 0x14, IMX8QM_IPG_MIPI_CSI_CLK_ROOT ),
+	CLK_5( IMX8QM_HDMI_I2C0_CLK, "HDMI_I2C0_CLK", 0, DI_HDMI_LPCG, IMX8QM_HDMI_I2C0_DIV ),
+	CLK_5( IMX8QM_HDMI_I2C_IPG_CLK, "HDMI_I2C0_IPG", 16, DI_HDMI_LPCG, IMX8QM_HDMI_IPG_CLK ),
+	CLK_5( IMX8QM_HDMI_RX_I2C_DIV_CLK, "HDMI RX_I2C_DIV_CLK", 0, MIPI_DSI_0_LPCG + 0x14, IMX8QM_MIPI0_I2C0_DIV ),
+	CLK_5( IMX8QM_HDMI_RX_I2C0_CLK, "HDMI RX_I2C_CLK", 0, MIPI_DSI_0_LPCG + 0x10, IMX8QM_HDMI_RX_I2C_DIV_CLK ),
+	CLK_5( IMX8QM_HDMI_RX_I2C_IPG_CLK, "HDMI_RX_I2C_IPG", 0, RX_HDMI_LPCG + 0x18,  IMX8QM_HDMI_RX_I2C_IPG_S_CLK),
+	CLK_5( IMX8QM_HDMI_RX_I2C_IPG_S_CLK, "HDMI_I2C_IPG_S", 0, RX_HDMI_LPCG + 0x1c, IMX8QM_HDMI_RX_IPG_CLK ),
+
+	CLK_5( IMX8QM_UART0_CLK, "UART0_CLK", 0, LPUART_0_LPCG, IMX8QM_UART0_DIV ),
+	CLK_5( IMX8QM_UART0_IPG_CLK, "UART0_IPG", 16, LPUART_0_LPCG, IMX8QM_IPG_DMA_CLK_ROOT ),
+	CLK_5( IMX8QM_UART1_CLK, "UART1_CLK", 0, LPUART_1_LPCG, IMX8QM_UART1_DIV ),
+	CLK_5( IMX8QM_UART1_IPG_CLK, "UART1_IPG", 16, LPUART_1_LPCG, IMX8QM_IPG_DMA_CLK_ROOT ),
+	CLK_5( IMX8QM_UART2_CLK, "UART2_CLK", 0, LPUART_2_LPCG, IMX8QM_UART2_DIV ),
+	CLK_5( IMX8QM_UART2_IPG_CLK, "UART2_IPG", 16, LPUART_2_LPCG, IMX8QM_IPG_DMA_CLK_ROOT ),
+	CLK_5( IMX8QM_UART3_CLK, "UART3_CLK", 0, LPUART_3_LPCG, IMX8QM_UART3_DIV ),
+	CLK_5( IMX8QM_UART3_IPG_CLK, "UART3_IPG", 16, LPUART_3_LPCG, IMX8QM_IPG_DMA_CLK_ROOT ),
+
+	CLK_5( IMX8QM_SDHC0_CLK, "SDHC0_CLK", 0, USDHC_0_LPCG, IMX8QM_SDHC0_DIV ),
+	CLK_5( IMX8QM_SDHC0_IPG_CLK, "SDHC0_IPG", 16, USDHC_0_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ),
+	CLK_5( IMX8QM_SDHC0_AHB_CLK, "SDHC0_AHB", 20, USDHC_0_LPCG, IMX8QM_AHB_CONN_CLK_ROOT ),
+	CLK_5( IMX8QM_SDHC1_CLK, "SDHC1_CLK", 0, USDHC_1_LPCG, IMX8QM_SDHC1_DIV ),
+	CLK_5( IMX8QM_SDHC1_IPG_CLK, "SDHC1_IPG", 16, USDHC_1_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ),
+	CLK_5( IMX8QM_SDHC1_AHB_CLK, "SDHC1_AHB", 20, USDHC_1_LPCG, IMX8QM_AHB_CONN_CLK_ROOT ),
+	CLK_5( IMX8QM_SDHC2_CLK, "SDHC2_CLK", 0, USDHC_2_LPCG, IMX8QM_SDHC2_DIV ),
+	CLK_5( IMX8QM_SDHC2_IPG_CLK, "SDHC2_IPG", 16, USDHC_2_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ),
+	CLK_5( IMX8QM_SDHC2_AHB_CLK, "SDHC2_AHB", 20, USDHC_2_LPCG, IMX8QM_AHB_CONN_CLK_ROOT ),
+
+	CLK_5( IMX8QM_ENET0_IPG_S_CLK, "ENET0_IPG_S", 20, ENET_0_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ),
+	CLK_5( IMX8QM_ENET0_IPG_CLK, "ENET0_IPG", 16, ENET_0_LPCG, IMX8QM_ENET0_IPG_S_CLK ),
+	CLK_5( IMX8QM_ENET0_AHB_CLK, "ENET0_AHB", 8, ENET_0_LPCG, IMX8QM_AXI_CONN_CLK_ROOT ),
+	CLK_5( IMX8QM_ENET0_TX_CLK, "ENET0_TX", 4, ENET_0_LPCG, IMX8QM_ENET0_ROOT_DIV ),
+	CLK_5( IMX8QM_ENET0_PTP_CLK, "ENET0_PTP", 0, ENET_0_LPCG, IMX8QM_ENET0_ROOT_DIV  ),
+	CLK_5( IMX8QM_ENET0_RGMII_TX_CLK, "ENET0_RGMII_TX", 12, ENET_0_LPCG, IMX8QM_ENET0_RMII_TX_SEL  ),
+	CLK_5( IMX8QM_ENET0_RMII_RX_CLK, "ENET0_RMII_RX", 0, ENET_0_LPCG + 0x4, IMX8QM_ENET0_RGMII_DIV  ),
+
+	CLK_5( IMX8QM_ENET1_IPG_S_CLK, "ENET1_IPG_S", 20, ENET_1_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ),
+	CLK_5( IMX8QM_ENET1_IPG_CLK, "ENET1_IPG", 16, ENET_1_LPCG, IMX8QM_ENET1_IPG_S_CLK ),
+	CLK_5( IMX8QM_ENET1_AHB_CLK, "ENET1_AHB", 8, ENET_1_LPCG, IMX8QM_AXI_CONN_CLK_ROOT ),
+	CLK_5( IMX8QM_ENET1_TX_CLK, "ENET1_TX", 4, ENET_1_LPCG, IMX8QM_ENET1_ROOT_DIV ),
+	CLK_5( IMX8QM_ENET1_PTP_CLK, "ENET1_PTP", 0, ENET_1_LPCG, IMX8QM_ENET1_ROOT_DIV  ),
+	CLK_5( IMX8QM_ENET1_RGMII_TX_CLK, "ENET1_RGMII_TX", 12, ENET_1_LPCG, IMX8QM_ENET1_RMII_TX_SEL  ),
+	CLK_5( IMX8QM_ENET1_RMII_RX_CLK, "ENET1_RMII_RX", 0, ENET_1_LPCG + 0x4, IMX8QM_ENET1_RGMII_DIV  ),
+
+	CLK_5( IMX8QM_FSPI0_IPG_S_CLK, "FSPI0_IPG_S", 0x18, FSPI_0_LPCG, IMX8QM_LSIO_BUS_CLK ),
+	CLK_5( IMX8QM_FSPI0_IPG_CLK, "FSPI0_IPG", 0x14, FSPI_0_LPCG, IMX8QM_FSPI0_IPG_S_CLK ),
+	CLK_5( IMX8QM_FSPI0_HCLK, "FSPI0_HCLK", 0x10, FSPI_0_LPCG, IMX8QM_LSIO_MEM_CLK ),
+	CLK_5( IMX8QM_FSPI0_CLK, "FSPI0_CLK", 0, FSPI_0_LPCG, IMX8QM_FSPI0_DIV ),
+
+	CLK_5( IMX8QM_USB2_OH_AHB_CLK, "USB2_OH_AHB", 24, USB_2_LPCG, IMX8QM_AHB_CONN_CLK_ROOT ),
+	CLK_5( IMX8QM_USB2_OH_IPG_S_CLK, "USB2_OH_IPG_S", 16, USB_2_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ),
+	CLK_5( IMX8QM_USB2_OH_IPG_S_PL301_CLK, "USB2_OH_IPG_S_PL301", 20, USB_2_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ),
+	CLK_5( IMX8QM_USB2_PHY_IPG_CLK, "USB2_PHY_IPG", 28, USB_2_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ),
+
+	CLK_5( IMX8QM_USB3_IPG_CLK, "USB3_IPG", 16, USB_3_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ),
+	CLK_5( IMX8QM_USB3_CORE_PCLK, "USB3_CORE", 20, USB_3_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ),
+	CLK_5( IMX8QM_USB3_PHY_CLK, "USB3_PHY", 24, USB_3_LPCG, IMX8QM_USB3_IPG_CLK ),
+	CLK_5( IMX8QM_USB3_ACLK, "USB3_ACLK", 28, USB_3_LPCG, IMX8QM_USB3_ACLK_DIV ),
+	CLK_5( IMX8QM_USB3_BUS_CLK, "USB3_BUS", 0, USB_3_LPCG, IMX8QM_USB3_BUS_DIV ),
+	CLK_5( IMX8QM_USB3_LPM_CLK, "USB3_LPM", 4, USB_3_LPCG, IMX8QM_USB3_LPM_DIV ),
+
+	CLK_5( IMX8QM_GPMI_APB_CLK, "GPMI_APB", 16, NAND_LPCG, IMX8QM_AXI_CONN_CLK_ROOT ),
+	CLK_5( IMX8QM_GPMI_APB_BCH_CLK, "GPMI_APB_BCH", 20, NAND_LPCG, IMX8QM_AXI_CONN_CLK_ROOT ),
+	CLK_5( IMX8QM_GPMI_BCH_IO_CLK, "GPMI_IO_CLK", 4, NAND_LPCG, IMX8QM_GPMI_BCH_IO_DIV ),
+	CLK_5( IMX8QM_GPMI_BCH_CLK, "GPMI_BCH_CLK", 0, NAND_LPCG, IMX8QM_GPMI_BCH_DIV ),
+	CLK_5( IMX8QM_APBHDMA_CLK, "GPMI_CLK", 16, NAND_LPCG + 0x4, IMX8QM_AXI_CONN_CLK_ROOT ),
+
+	CLK_5( IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK, "HSIO_PCIE_A_MSTR_AXI_CLK", 16, HSIO_PCIE_X2_LPCG, IMX8QM_HSIO_AXI_CLK ),
+	CLK_5( IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK, "HSIO_PCIE_A_SLV_AXI_CLK", 20, HSIO_PCIE_X2_LPCG, IMX8QM_HSIO_AXI_CLK ),
+	CLK_5( IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK, "HSIO_PCIE_A_DBI_AXI_CLK", 24, HSIO_PCIE_X2_LPCG, IMX8QM_HSIO_AXI_CLK ),
+	CLK_5( IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK, "HSIO_PCIE_B_MSTR_AXI_CLK", 16, HSIO_PCIE_X1_LPCG, IMX8QM_HSIO_AXI_CLK ),
+	CLK_5( IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK, "HSIO_PCIE_B_SLV_AXI_CLK", 20, HSIO_PCIE_X1_LPCG, IMX8QM_HSIO_AXI_CLK ),
+	CLK_5( IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK, "HSIO_PCIE_B_DBI_AXI_CLK", 24, HSIO_PCIE_X1_LPCG, IMX8QM_HSIO_AXI_CLK ),
+	CLK_5( IMX8QM_HSIO_PCIE_X1_PER_CLK, "HSIO_PCIE_X1_PER_CLK", 16, HSIO_PCIE_X1_CRR3_LPCG, IMX8QM_HSIO_PER_CLK ),
+	CLK_5( IMX8QM_HSIO_PCIE_X2_PER_CLK, "HSIO_PCIE_X2_PER_CLK", 16, HSIO_PCIE_X2_CRR2_LPCG, IMX8QM_HSIO_PER_CLK ),
+	CLK_5( IMX8QM_HSIO_SATA_PER_CLK, "HSIO_SATA_PER_CLK", 16, HSIO_SATA_CRR4_LPCG, IMX8QM_HSIO_PER_CLK ),
+	CLK_5( IMX8QM_HSIO_PHY_X1_PER_CLK, "HSIO_PHY_X1_PER_CLK", 16, HSIO_PHY_X1_CRR1_LPCG, IMX8QM_HSIO_PER_CLK ),
+	CLK_5( IMX8QM_HSIO_PHY_X2_PER_CLK, "HSIO_PHY_X2_PER_CLK", 16, HSIO_PHY_X2_CRR0_LPCG, IMX8QM_HSIO_PER_CLK ),
+	CLK_5( IMX8QM_HSIO_MISC_PER_CLK, "HSIO_MISC_PER_CLK", 16, HSIO_MISC_LPCG, IMX8QM_HSIO_PER_CLK ),
+	CLK_5( IMX8QM_HSIO_PHY_X1_APB_CLK, "HSIO_PHY_X1_APB_CLK", 16, HSIO_PHY_X1_LPCG, IMX8QM_HSIO_PER_CLK ),
+	CLK_5( IMX8QM_HSIO_PHY_X2_APB_0_CLK, "HSIO_PHY_X2_APB_0_CLK", 16, HSIO_PHY_X2_LPCG, IMX8QM_HSIO_PER_CLK ),
+	CLK_5( IMX8QM_HSIO_PHY_X2_APB_1_CLK, "HSIO_PHY_X2_APB_1_CLK", 20, HSIO_PHY_X2_LPCG, IMX8QM_HSIO_PER_CLK ),
+	CLK_5( IMX8QM_HSIO_SATA_CLK, "HSIO_SATA_CLK", 16, HSIO_SATA_LPCG, IMX8QM_HSIO_AXI_CLK ),
+	CLK_5( IMX8QM_HSIO_GPIO_CLK, "HSIO_GPIO_CLK", 16, HSIO_GPIO_LPCG, IMX8QM_HSIO_PER_CLK ),
+	CLK_5( IMX8QM_HSIO_PHY_X1_PCLK, "HSIO_PHY_X1_PCLK", 0, HSIO_PHY_X1_LPCG, 0 ),
+	CLK_5( IMX8QM_HSIO_PHY_X2_PCLK_0, "HSIO_PHY_X2_PCLK_0", 0, HSIO_PHY_X2_LPCG, 0 ),
+	CLK_5( IMX8QM_HSIO_PHY_X2_PCLK_1, "HSIO_PHY_X2_PCLK_1", 4, HSIO_PHY_X2_LPCG, 0 ),
+	CLK_5( IMX8QM_HSIO_SATA_EPCS_RX_CLK, "HSIO_SATA_EPCS_RX_CLK", 8, HSIO_PHY_X1_LPCG, 0 ),
+	CLK_5( IMX8QM_HSIO_SATA_EPCS_TX_CLK, "HSIO_SATA_EPCS_TX_CLK", 4, HSIO_PHY_X1_LPCG, 0 ),
+};
 
-	ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
-	if (ret) {
-		printf("%s err %d\n", __func__, ret);
-		return ret;
-	}
+struct imx8_mux_clks imx8qm_mux_clks[] = {
+};
 
-	return 0;
-}
+struct imx8_clks_collect imx8qm_clk_collect = {
+	{
+		{&imx8qm_clks, ARRAY_SIZE(imx8qm_clks)},
+		{&imx8qm_fixed_clks, ARRAY_SIZE(imx8qm_fixed_clks)},
+		{&imx8qm_gpr_clks, ARRAY_SIZE(imx8qm_gpr_clks)},
+		{&imx8qm_lpcg_clks, ARRAY_SIZE(imx8qm_lpcg_clks)},
+		{&imx8qm_mux_clks, ARRAY_SIZE(imx8qm_mux_clks)},
+	},
+	FLAG_CLK_IMX8_IMX8QM,
+};
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
index ffa2fcee0b2..4fe44343578 100644
--- a/drivers/clk/imx/clk-imx8qxp.c
+++ b/drivers/clk/imx/clk-imx8qxp.c
@@ -13,312 +13,219 @@
 #include <dt-bindings/clock/imx8qxp-clock.h>
 #include <dt-bindings/soc/imx_rsrc.h>
 #include <misc.h>
+#include <asm/arch/lpcg.h>
 
 #include "clk-imx8.h"
 
-#if CONFIG_IS_ENABLED(CMD_CLK)
-struct imx8_clks imx8_clk_names[] = {
-	{ IMX8QXP_A35_DIV, "A35_DIV" },
-	{ IMX8QXP_I2C0_CLK, "I2C0" },
-	{ IMX8QXP_I2C1_CLK, "I2C1" },
-	{ IMX8QXP_I2C2_CLK, "I2C2" },
-	{ IMX8QXP_I2C3_CLK, "I2C3" },
-	{ IMX8QXP_UART0_CLK, "UART0" },
-	{ IMX8QXP_UART1_CLK, "UART1" },
-	{ IMX8QXP_UART2_CLK, "UART2" },
-	{ IMX8QXP_UART3_CLK, "UART3" },
-	{ IMX8QXP_SDHC0_CLK, "SDHC0" },
-	{ IMX8QXP_SDHC1_CLK, "SDHC1" },
-	{ IMX8QXP_ENET0_AHB_CLK, "ENET0_AHB" },
-	{ IMX8QXP_ENET0_IPG_CLK, "ENET0_IPG" },
-	{ IMX8QXP_ENET0_REF_DIV, "ENET0_REF" },
-	{ IMX8QXP_ENET0_PTP_CLK, "ENET0_PTP" },
-	{ IMX8QXP_ENET1_AHB_CLK, "ENET1_AHB" },
-	{ IMX8QXP_ENET1_IPG_CLK, "ENET1_IPG" },
-	{ IMX8QXP_ENET1_REF_DIV, "ENET1_REF" },
-	{ IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP" },
+static struct imx8_clks imx8qxp_clks[] = {
+	CLK_4( IMX8QXP_A35_DIV, "A35_DIV", SC_R_A35, SC_PM_CLK_CPU ),
+	CLK_4( IMX8QXP_I2C0_DIV, "I2C0_DIV", SC_R_I2C_0, SC_PM_CLK_PER ),
+	CLK_4( IMX8QXP_I2C1_DIV, "I2C1_DIV", SC_R_I2C_1, SC_PM_CLK_PER ),
+	CLK_4( IMX8QXP_I2C2_DIV, "I2C2_DIV", SC_R_I2C_2, SC_PM_CLK_PER ),
+	CLK_4( IMX8QXP_I2C3_DIV, "I2C3_DIV", SC_R_I2C_3, SC_PM_CLK_PER ),
+#if !defined(CONFIG_IMX8DXL)
+	CLK_4( IMX8QXP_MIPI0_I2C0_DIV, "MIPI0 I2C0_DIV", SC_R_MIPI_0_I2C_0, SC_PM_CLK_MISC2 ),
+	CLK_4( IMX8QXP_MIPI0_I2C1_DIV, "MIPI0 I2C1_DIV", SC_R_MIPI_0_I2C_1, SC_PM_CLK_MISC2 ),
+	CLK_4( IMX8QXP_MIPI1_I2C0_DIV, "MIPI1 I2C0_DIV", SC_R_MIPI_1_I2C_0, SC_PM_CLK_MISC2 ),
+	CLK_4( IMX8QXP_MIPI1_I2C1_DIV, "MIPI1 I2C1_DIV", SC_R_MIPI_1_I2C_1, SC_PM_CLK_MISC2 ),
+	CLK_4( IMX8QXP_CSI0_I2C0_DIV, "CSI0 I2C0_DIV", SC_R_CSI_0_I2C_0, SC_PM_CLK_PER ),
+#endif
+	CLK_4( IMX8QXP_SPI0_DIV, "SPI0_DIV", SC_R_SPI_0, SC_PM_CLK_PER ),
+	CLK_4( IMX8QXP_SPI1_DIV, "SPI1_DIV", SC_R_SPI_1, SC_PM_CLK_PER ),
+	CLK_4( IMX8QXP_SPI2_DIV, "SPI2_DIV", SC_R_SPI_2, SC_PM_CLK_PER ),
+	CLK_4( IMX8QXP_SPI3_DIV, "SPI3_DIV", SC_R_SPI_3, SC_PM_CLK_PER ),
+	CLK_4( IMX8QXP_UART0_DIV, "UART0_DIV", SC_R_UART_0, SC_PM_CLK_PER ),
+	CLK_4( IMX8QXP_UART1_DIV, "UART1_DIV", SC_R_UART_1, SC_PM_CLK_PER ),
+	CLK_4( IMX8QXP_UART2_DIV, "UART2_DIV", SC_R_UART_2, SC_PM_CLK_PER ),
+	CLK_4( IMX8QXP_UART3_DIV, "UART3_DIV", SC_R_UART_3, SC_PM_CLK_PER ),
+	CLK_4( IMX8QXP_SDHC0_DIV, "SDHC0_DIV", SC_R_SDHC_0, SC_PM_CLK_PER ),
+	CLK_4( IMX8QXP_SDHC1_DIV, "SDHC1_DIV", SC_R_SDHC_1, SC_PM_CLK_PER ),
+	CLK_4( IMX8QXP_SDHC2_DIV, "SDHC2_DIV", SC_R_SDHC_2, SC_PM_CLK_PER ),
+#if !defined(CONFIG_IMX8DXL)
+	CLK_4( IMX8QXP_ENET0_ROOT_DIV, "ENET0_ROOT_DIV", SC_R_ENET_0, SC_PM_CLK_PER ),
+	CLK_4( IMX8QXP_ENET0_RGMII_DIV, "ENET0_RGMII_DIV", SC_R_ENET_0, SC_PM_CLK_MISC0 ),
+#endif
+	CLK_4( IMX8QXP_ENET1_ROOT_DIV, "ENET1_ROOT_DIV", SC_R_ENET_1, SC_PM_CLK_PER ),
+#if !defined(CONFIG_IMX8DXL)
+	CLK_4( IMX8QXP_ENET1_RGMII_DIV, "ENET1_RGMII_DIV", SC_R_ENET_1, SC_PM_CLK_MISC0 ),
+	CLK_4( IMX8QXP_USB3_ACLK_DIV, "USB3_ACLK_DIV", SC_R_USB_2, SC_PM_CLK_PER ),
+	CLK_4( IMX8QXP_USB3_BUS_DIV, "USB3_BUS_DIV", SC_R_USB_2, SC_PM_CLK_MST_BUS ),
+	CLK_4( IMX8QXP_USB3_LPM_DIV, "USB3_LPM_DIV", SC_R_USB_2, SC_PM_CLK_MISC ),
+#endif
+	CLK_4( IMX8QXP_LSIO_FSPI0_DIV, "FSPI0_DIV", SC_R_FSPI_0, SC_PM_CLK_PER ),
+	CLK_4( IMX8QXP_GPMI_BCH_IO_DIV, "GPMI_IO_DIV", SC_R_NAND, SC_PM_CLK_MST_BUS ),
+	CLK_4( IMX8QXP_GPMI_BCH_DIV, "GPMI_BCH_DIV", SC_R_NAND, SC_PM_CLK_PER ),
+
+	CLK_4( IMX8QXP_ELCDIF_PLL_DIV, "ELCDIF_PLL_DIV", SC_R_ELCDIF_PLL, SC_PM_CLK_PLL ),
+	CLK_4( IMX8QXP_LCD_PXL_DIV, "LCD_PXL_DIV", SC_R_LCD_0, SC_PM_CLK_MISC0 ),
+	CLK_4( IMX8QXP_LCD_DIV, "LCD_DIV", SC_R_LCD_0, SC_PM_CLK_PER ),
+	CLK_4( IMX8QXP_LCD_PXL_BYPASS_DIV, "LCD_PXL_BYPASS_DIV", SC_R_LCD_0, SC_PM_CLK_BYPASS ),
 };
 
-int num_clks = ARRAY_SIZE(imx8_clk_names);
+static struct imx8_fixed_clks imx8qxp_fixed_clks[] = {
+	CLK_3( IMX8QXP_IPG_CONN_CLK_ROOT, "IPG_CONN_CLK", SC_83MHZ ),
+	CLK_3( IMX8QXP_AHB_CONN_CLK_ROOT, "AHB_CONN_CLK", SC_166MHZ ),
+	CLK_3( IMX8QXP_AXI_CONN_CLK_ROOT, "AXI_CONN_CLK", SC_333MHZ ),
+	CLK_3( IMX8QXP_IPG_DMA_CLK_ROOT, "IPG_DMA_CLK", SC_120MHZ ),
+	CLK_3( IMX8QXP_MIPI_IPG_CLK, "IPG_MIPI_CLK", SC_120MHZ ),
+	CLK_3( IMX8QXP_LSIO_BUS_CLK, "LSIO_BUS_CLK", SC_100MHZ ),
+	CLK_3( IMX8QXP_LSIO_MEM_CLK, "LSIO_MEM_CLK", SC_200MHZ ),
+	CLK_3( IMX8QXP_HSIO_PER_CLK, "HSIO_CLK", SC_133MHZ ),
+	CLK_3( IMX8QXP_HSIO_AXI_CLK, "HSIO_AXI", SC_400MHZ ),
+#if defined(CONFIG_IMX8DXL)
+	CLK_3( IMX8QXP_ENET0_ROOT_DIV, "ENET0_ROOT_DIV", SC_250MHZ ),
 #endif
+};
 
-ulong imx8_clk_get_rate(struct clk *clk)
-{
-	sc_pm_clk_t pm_clk;
-	ulong rate;
-	u16 resource;
-	int ret;
-
-	debug("%s(#%lu)\n", __func__, clk->id);
-
-	switch (clk->id) {
-	case IMX8QXP_A35_DIV:
-		resource = SC_R_A35;
-		pm_clk = SC_PM_CLK_CPU;
-		break;
-	case IMX8QXP_I2C0_CLK:
-	case IMX8QXP_I2C0_IPG_CLK:
-		resource = SC_R_I2C_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_I2C1_CLK:
-	case IMX8QXP_I2C1_IPG_CLK:
-		resource = SC_R_I2C_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_I2C2_CLK:
-	case IMX8QXP_I2C2_IPG_CLK:
-		resource = SC_R_I2C_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_I2C3_CLK:
-	case IMX8QXP_I2C3_IPG_CLK:
-		resource = SC_R_I2C_3;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_SDHC0_IPG_CLK:
-	case IMX8QXP_SDHC0_CLK:
-	case IMX8QXP_SDHC0_DIV:
-		resource = SC_R_SDHC_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_SDHC1_IPG_CLK:
-	case IMX8QXP_SDHC1_CLK:
-	case IMX8QXP_SDHC1_DIV:
-		resource = SC_R_SDHC_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART0_IPG_CLK:
-	case IMX8QXP_UART0_CLK:
-		resource = SC_R_UART_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART1_CLK:
-		resource = SC_R_UART_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART2_CLK:
-		resource = SC_R_UART_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART3_CLK:
-		resource = SC_R_UART_3;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_ENET0_IPG_CLK:
-	case IMX8QXP_ENET0_AHB_CLK:
-	case IMX8QXP_ENET0_REF_DIV:
-	case IMX8QXP_ENET0_PTP_CLK:
-		resource = SC_R_ENET_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_ENET1_IPG_CLK:
-	case IMX8QXP_ENET1_AHB_CLK:
-	case IMX8QXP_ENET1_REF_DIV:
-	case IMX8QXP_ENET1_PTP_CLK:
-		resource = SC_R_ENET_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	default:
-		if (clk->id < IMX8QXP_UART0_IPG_CLK ||
-		    clk->id >= IMX8QXP_CLK_END) {
-			printf("%s(Invalid clk ID #%lu)\n",
-			       __func__, clk->id);
-			return -EINVAL;
-		}
-		return -EINVAL;
-	};
-
-	ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
-				   (sc_pm_clock_rate_t *)&rate);
-	if (ret) {
-		printf("%s err %d\n", __func__, ret);
-		return ret;
-	}
-
-	return rate;
-}
-
-ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
-{
-	sc_pm_clk_t pm_clk;
-	u32 new_rate = rate;
-	u16 resource;
-	int ret;
-
-	debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
-
-	switch (clk->id) {
-	case IMX8QXP_I2C0_CLK:
-	case IMX8QXP_I2C0_IPG_CLK:
-		resource = SC_R_I2C_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_I2C1_CLK:
-	case IMX8QXP_I2C1_IPG_CLK:
-		resource = SC_R_I2C_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_I2C2_CLK:
-	case IMX8QXP_I2C2_IPG_CLK:
-		resource = SC_R_I2C_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_I2C3_CLK:
-	case IMX8QXP_I2C3_IPG_CLK:
-		resource = SC_R_I2C_3;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART0_CLK:
-		resource = SC_R_UART_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART1_CLK:
-		resource = SC_R_UART_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART2_CLK:
-		resource = SC_R_UART_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART3_CLK:
-		resource = SC_R_UART_3;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_SDHC0_IPG_CLK:
-	case IMX8QXP_SDHC0_CLK:
-	case IMX8QXP_SDHC0_DIV:
-		resource = SC_R_SDHC_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_SDHC1_SEL:
-	case IMX8QXP_SDHC0_SEL:
-		return 0;
-	case IMX8QXP_SDHC1_IPG_CLK:
-	case IMX8QXP_SDHC1_CLK:
-	case IMX8QXP_SDHC1_DIV:
-		resource = SC_R_SDHC_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_ENET0_IPG_CLK:
-	case IMX8QXP_ENET0_AHB_CLK:
-	case IMX8QXP_ENET0_REF_DIV:
-	case IMX8QXP_ENET0_PTP_CLK:
-		resource = SC_R_ENET_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_ENET1_IPG_CLK:
-	case IMX8QXP_ENET1_AHB_CLK:
-	case IMX8QXP_ENET1_REF_DIV:
-	case IMX8QXP_ENET1_PTP_CLK:
-		resource = SC_R_ENET_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	default:
-		if (clk->id < IMX8QXP_UART0_IPG_CLK ||
-		    clk->id >= IMX8QXP_CLK_END) {
-			printf("%s(Invalid clk ID #%lu)\n",
-			       __func__, clk->id);
-			return -EINVAL;
-		}
-		return -EINVAL;
-	};
+static struct imx8_gpr_clks imx8qxp_gpr_clks[] = {
+	CLK_5( IMX8QXP_ENET0_REF_DIV, "ENET0_REF_DIV", SC_R_ENET_0, SC_C_CLKDIV, IMX8QXP_ENET0_ROOT_DIV ),
+	CLK_4( IMX8QXP_ENET0_REF_25MHZ_125MHZ_SEL, "ENET0_REF_25_125", SC_R_ENET_0, SC_C_SEL_125 ),
+	CLK_4( IMX8QXP_ENET0_RMII_TX_SEL, "ENET0_RMII_TX", SC_R_ENET_0, SC_C_TXCLK ),
+	CLK_4( IMX8QXP_ENET0_REF_25MHZ_125MHZ_CLK, "ENET0_REF_25_125_CLK", SC_R_ENET_0, SC_C_DISABLE_125 ),
+	CLK_4( IMX8QXP_ENET0_REF_50MHZ_CLK, "ENET0_REF_50", SC_R_ENET_0, SC_C_DISABLE_50 ),
+
+	CLK_5( IMX8QXP_ENET1_REF_DIV, "ENET1_REF_DIV", SC_R_ENET_1, SC_C_CLKDIV, IMX8QXP_ENET1_ROOT_DIV ),
+	CLK_4( IMX8QXP_ENET1_REF_25MHZ_125MHZ_SEL, "ENET1_REF_25_125", SC_R_ENET_1, SC_C_SEL_125 ),
+	CLK_4( IMX8QXP_ENET1_RMII_TX_SEL, "ENET1_RMII_TX", SC_R_ENET_1, SC_C_TXCLK ),
+	CLK_4( IMX8QXP_ENET1_REF_25MHZ_125MHZ_CLK, "ENET1_REF_25_125_CLK", SC_R_ENET_1, SC_C_DISABLE_125 ),
+	CLK_4( IMX8QXP_ENET1_REF_50MHZ_CLK, "ENET1_REF_50", SC_R_ENET_1, SC_C_DISABLE_50 ),
+};
 
-	ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate);
-	if (ret) {
-		printf("%s err %d\n", __func__, ret);
-		return ret;
-	}
+static struct imx8_lpcg_clks imx8qxp_lpcg_clks[] = {
+	CLK_5( IMX8QXP_I2C0_CLK, "I2C0_CLK", 0, LPI2C_0_LPCG, IMX8QXP_I2C0_DIV ),
+	CLK_5( IMX8QXP_I2C0_IPG_CLK, "I2C0_IPG", 16, LPI2C_0_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ),
+	CLK_5( IMX8QXP_I2C1_CLK, "I2C1_CLK", 0, LPI2C_1_LPCG, IMX8QXP_I2C1_DIV ),
+	CLK_5( IMX8QXP_I2C1_IPG_CLK, "I2C1_IPG", 16, LPI2C_1_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ),
+	CLK_5( IMX8QXP_I2C2_CLK, "I2C2_CLK", 0, LPI2C_2_LPCG, IMX8QXP_I2C2_DIV ),
+	CLK_5( IMX8QXP_I2C2_IPG_CLK, "I2C2_IPG", 16, LPI2C_2_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ),
+	CLK_5( IMX8QXP_I2C3_CLK, "I2C3_CLK", 0, LPI2C_3_LPCG, IMX8QXP_I2C3_DIV ),
+	CLK_5( IMX8QXP_I2C3_IPG_CLK, "I2C3_IPG", 16, LPI2C_3_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ),
+	CLK_5( IMX8QXP_MIPI0_I2C0_CLK, "MIPI0_I2C0_CLK", 0, DI_MIPI0_LPCG + 0x10, IMX8QXP_MIPI0_I2C0_DIV ),
+	CLK_5( IMX8QXP_MIPI0_I2C0_IPG_CLK, "MIPI0_I2C0_IPG", 16, DI_MIPI0_LPCG + 0x10, IMX8QXP_MIPI_IPG_CLK ),
+	CLK_5( IMX8QXP_MIPI0_I2C1_CLK, "MIPI0_I2C1_CLK", 0, DI_MIPI0_LPCG + 0x14, IMX8QXP_MIPI0_I2C1_DIV ),
+	CLK_5( IMX8QXP_MIPI0_I2C1_IPG_CLK, "MIPI0_I2C1_IPG", 16, DI_MIPI0_LPCG + 0x14, IMX8QXP_MIPI_IPG_CLK ),
+	CLK_5( IMX8QXP_MIPI1_I2C0_CLK, "MIPI1_I2C0_CLK", 0, DI_MIPI1_LPCG + 0x10, IMX8QXP_MIPI1_I2C0_DIV ),
+	CLK_5( IMX8QXP_MIPI1_I2C0_IPG_CLK, "MIPI1_I2C0_IPG", 16, DI_MIPI1_LPCG + 0x10, IMX8QXP_MIPI_IPG_CLK ),
+	CLK_5( IMX8QXP_MIPI1_I2C1_CLK, "MIPI1_I2C1_CLK", 0, DI_MIPI1_LPCG + 0x14, IMX8QXP_MIPI1_I2C1_DIV ),
+	CLK_5( IMX8QXP_MIPI1_I2C1_IPG_CLK, "MIPI1_I2C1_IPG", 16, DI_MIPI1_LPCG + 0x14, IMX8QXP_MIPI_IPG_CLK ),
+	CLK_5( IMX8QXP_CSI0_I2C0_CLK, "CSI0_I2C0_CLK", 0, MIPI_CSI_0_LPCG + 0x14, IMX8QXP_CSI0_I2C0_DIV ),
+	CLK_5( IMX8QXP_CSI0_I2C0_IPG_CLK, "CSI0_I2C0_IPG", 16, MIPI_CSI_0_LPCG + 0x14, IMX8QXP_MIPI_IPG_CLK ),
+
+	CLK_5( IMX8QXP_SPI0_CLK, "SPI0_CLK", 0, LPSPI_0_LPCG, IMX8QXP_SPI0_DIV ),
+	CLK_5( IMX8QXP_SPI0_IPG_CLK, "SPI0_IPG", 16, LPSPI_0_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ),
+	CLK_5( IMX8QXP_SPI1_CLK, "SPI1_CLK", 0, LPSPI_1_LPCG, IMX8QXP_SPI1_DIV ),
+	CLK_5( IMX8QXP_SPI1_IPG_CLK, "SPI1_IPG", 16, LPSPI_1_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ),
+	CLK_5( IMX8QXP_SPI2_CLK, "SPI2_CLK", 0, LPSPI_2_LPCG, IMX8QXP_SPI2_DIV ),
+	CLK_5( IMX8QXP_SPI2_IPG_CLK, "SPI2_IPG", 16, LPSPI_2_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ),
+	CLK_5( IMX8QXP_SPI3_CLK, "SPI3_CLK", 0, LPSPI_3_LPCG, IMX8QXP_SPI3_DIV ),
+	CLK_5( IMX8QXP_SPI3_IPG_CLK, "SPI3_IPG", 16, LPSPI_3_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ),
+
+	CLK_5( IMX8QXP_UART0_CLK, "UART0_CLK", 0, LPUART_0_LPCG, IMX8QXP_UART0_DIV ),
+	CLK_5( IMX8QXP_UART0_IPG_CLK, "UART0_IPG", 16, LPUART_0_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ),
+	CLK_5( IMX8QXP_UART1_CLK, "UART1_CLK", 0, LPUART_1_LPCG, IMX8QXP_UART1_DIV ),
+	CLK_5( IMX8QXP_UART1_IPG_CLK, "UART1_IPG", 16, LPUART_1_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ),
+	CLK_5( IMX8QXP_UART2_CLK, "UART2_CLK", 0, LPUART_2_LPCG, IMX8QXP_UART2_DIV ),
+	CLK_5( IMX8QXP_UART2_IPG_CLK, "UART2_IPG", 16, LPUART_2_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ),
+	CLK_5( IMX8QXP_UART3_CLK, "UART3_CLK", 0, LPUART_3_LPCG, IMX8QXP_UART3_DIV ),
+	CLK_5( IMX8QXP_UART3_IPG_CLK, "UART3_IPG", 16, LPUART_3_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ),
+
+	CLK_5( IMX8QXP_SDHC0_CLK, "SDHC0_CLK", 0, USDHC_0_LPCG, IMX8QXP_SDHC0_DIV ),
+	CLK_5( IMX8QXP_SDHC0_IPG_CLK, "SDHC0_IPG", 16, USDHC_0_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ),
+	CLK_5( IMX8QXP_SDHC0_AHB_CLK, "SDHC0_AHB", 20, USDHC_0_LPCG, IMX8QXP_AHB_CONN_CLK_ROOT ),
+	CLK_5( IMX8QXP_SDHC1_CLK, "SDHC1_CLK", 0, USDHC_1_LPCG, IMX8QXP_SDHC1_DIV ),
+	CLK_5( IMX8QXP_SDHC1_IPG_CLK, "SDHC1_IPG", 16, USDHC_1_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ),
+	CLK_5( IMX8QXP_SDHC1_AHB_CLK, "SDHC1_AHB", 20, USDHC_1_LPCG, IMX8QXP_AHB_CONN_CLK_ROOT ),
+	CLK_5( IMX8QXP_SDHC2_CLK, "SDHC2_CLK", 0, USDHC_2_LPCG, IMX8QXP_SDHC2_DIV ),
+	CLK_5( IMX8QXP_SDHC2_IPG_CLK, "SDHC2_IPG", 16, USDHC_2_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ),
+	CLK_5( IMX8QXP_SDHC2_AHB_CLK, "SDHC2_AHB", 20, USDHC_2_LPCG, IMX8QXP_AHB_CONN_CLK_ROOT ),
+
+	CLK_5( IMX8QXP_ENET0_IPG_S_CLK, "ENET0_IPG_S", 20, ENET_0_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ),
+	CLK_5( IMX8QXP_ENET0_IPG_CLK, "ENET0_IPG", 16, ENET_0_LPCG, IMX8QXP_ENET0_IPG_S_CLK ),
+	CLK_5( IMX8QXP_ENET0_AHB_CLK, "ENET0_AHB", 8, ENET_0_LPCG, IMX8QXP_AXI_CONN_CLK_ROOT ),
+	CLK_5( IMX8QXP_ENET0_TX_CLK, "ENET0_TX", 4, ENET_0_LPCG, IMX8QXP_ENET0_ROOT_DIV ),
+	CLK_5( IMX8QXP_ENET0_PTP_CLK, "ENET0_PTP", 0, ENET_0_LPCG, IMX8QXP_ENET0_ROOT_DIV  ),
+	CLK_5( IMX8QXP_ENET0_RGMII_TX_CLK, "ENET0_RGMII_TX", 12, ENET_0_LPCG, IMX8QXP_ENET0_RMII_TX_SEL  ),
+	CLK_5( IMX8QXP_ENET0_RMII_RX_CLK, "ENET0_RMII_RX", 0, ENET_0_LPCG + 0x4, IMX8QXP_ENET0_RGMII_DIV  ),
+
+	CLK_5( IMX8QXP_ENET1_IPG_S_CLK, "ENET1_IPG_S", 20, ENET_1_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ),
+	CLK_5( IMX8QXP_ENET1_IPG_CLK, "ENET1_IPG", 16, ENET_1_LPCG, IMX8QXP_ENET1_IPG_S_CLK ),
+	CLK_5( IMX8QXP_ENET1_AHB_CLK, "ENET1_AHB", 8, ENET_1_LPCG, IMX8QXP_AXI_CONN_CLK_ROOT ),
+	CLK_5( IMX8QXP_ENET1_TX_CLK, "ENET1_TX", 4, ENET_1_LPCG, IMX8QXP_ENET1_ROOT_DIV ),
+	CLK_5( IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP", 0, ENET_1_LPCG, IMX8QXP_ENET1_ROOT_DIV  ),
+	CLK_5( IMX8QXP_ENET1_RGMII_TX_CLK, "ENET1_RGMII_TX", 12, ENET_1_LPCG, IMX8QXP_ENET1_RMII_TX_SEL  ),
+	CLK_5( IMX8QXP_ENET1_RMII_RX_CLK, "ENET1_RMII_RX", 0, ENET_1_LPCG + 0x4, IMX8QXP_ENET1_RGMII_DIV  ),
+
+#if defined(CONFIG_IMX8DXL)
+	CLK_5( IMX8DXL_EQOS_MEM_CLK, "EQOS_MEM_CLK", 8, ENET_1_LPCG, IMX8QXP_AXI_CONN_CLK_ROOT ),
+	CLK_5( IMX8DXL_EQOS_ACLK, "EQOS_ACLK", 16, ENET_1_LPCG, IMX8DXL_EQOS_MEM_CLK ),
+	CLK_5( IMX8DXL_EQOS_CSR_CLK, "EQOS_CSR_CLK", 24, ENET_1_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ),
+	CLK_5( IMX8DXL_EQOS_CLK, "EQOS_CLK", 20, ENET_1_LPCG, IMX8QXP_ENET1_ROOT_DIV ),
+	CLK_5( IMX8DXL_EQOS_PTP_CLK_S, "EQOS_PTP_S", 8, ENET_1_LPCG, IMX8QXP_ENET0_ROOT_DIV  ),
+	CLK_5( IMX8DXL_EQOS_PTP_CLK, "EQOS_PTP", 0, ENET_1_LPCG, IMX8DXL_EQOS_PTP_CLK_S  ),
+#endif
 
-	return new_rate;
-}
+	CLK_5( IMX8QXP_LSIO_FSPI0_IPG_S_CLK, "FSPI0_IPG_S", 0x18, FSPI_0_LPCG, IMX8QXP_LSIO_BUS_CLK ),
+	CLK_5( IMX8QXP_LSIO_FSPI0_IPG_CLK, "FSPI0_IPG", 0x14, FSPI_0_LPCG, IMX8QXP_LSIO_FSPI0_IPG_S_CLK ),
+	CLK_5( IMX8QXP_LSIO_FSPI0_HCLK, "FSPI0_HCLK", 0x10, FSPI_0_LPCG, IMX8QXP_LSIO_MEM_CLK ),
+	CLK_5( IMX8QXP_LSIO_FSPI0_CLK, "FSPI0_CLK", 0, FSPI_0_LPCG, IMX8QXP_LSIO_FSPI0_DIV ),
 
-int __imx8_clk_enable(struct clk *clk, bool enable)
-{
-	sc_pm_clk_t pm_clk;
-	u16 resource;
-	int ret;
+#if !defined(CONFIG_IMX8DXL)
+	CLK_5( IMX8QXP_USB2_OH_AHB_CLK, "USB2_OH_AHB", 24, USB_2_LPCG, IMX8QXP_AHB_CONN_CLK_ROOT ),
+	CLK_5( IMX8QXP_USB2_OH_IPG_S_CLK, "USB2_OH_IPG_S", 16, USB_2_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ),
+	CLK_5( IMX8QXP_USB2_OH_IPG_S_PL301_CLK, "USB2_OH_IPG_S_PL301", 20, USB_2_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ),
+#endif
+	CLK_5( IMX8QXP_USB2_PHY_IPG_CLK, "USB2_PHY_IPG", 28, USB_2_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ),
 
-	debug("%s(#%lu)\n", __func__, clk->id);
+	CLK_5( IMX8QXP_USB3_IPG_CLK, "USB3_IPG", 16, USB_3_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ),
+	CLK_5( IMX8QXP_USB3_CORE_PCLK, "USB3_CORE", 20, USB_3_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ),
+	CLK_5( IMX8QXP_USB3_PHY_CLK, "USB3_PHY", 24, USB_3_LPCG, IMX8QXP_USB3_IPG_CLK ),
 
-	switch (clk->id) {
-	case IMX8QXP_I2C0_CLK:
-	case IMX8QXP_I2C0_IPG_CLK:
-		resource = SC_R_I2C_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_I2C1_CLK:
-	case IMX8QXP_I2C1_IPG_CLK:
-		resource = SC_R_I2C_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_I2C2_CLK:
-	case IMX8QXP_I2C2_IPG_CLK:
-		resource = SC_R_I2C_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_I2C3_CLK:
-	case IMX8QXP_I2C3_IPG_CLK:
-		resource = SC_R_I2C_3;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART0_CLK:
-		resource = SC_R_UART_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART1_CLK:
-		resource = SC_R_UART_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART2_CLK:
-		resource = SC_R_UART_2;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_UART3_CLK:
-		resource = SC_R_UART_3;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_SDHC0_IPG_CLK:
-	case IMX8QXP_SDHC0_CLK:
-	case IMX8QXP_SDHC0_DIV:
-		resource = SC_R_SDHC_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_SDHC1_IPG_CLK:
-	case IMX8QXP_SDHC1_CLK:
-	case IMX8QXP_SDHC1_DIV:
-		resource = SC_R_SDHC_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_ENET0_IPG_CLK:
-	case IMX8QXP_ENET0_AHB_CLK:
-	case IMX8QXP_ENET0_REF_DIV:
-	case IMX8QXP_ENET0_PTP_CLK:
-		resource = SC_R_ENET_0;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	case IMX8QXP_ENET1_IPG_CLK:
-	case IMX8QXP_ENET1_AHB_CLK:
-	case IMX8QXP_ENET1_REF_DIV:
-	case IMX8QXP_ENET1_PTP_CLK:
-		resource = SC_R_ENET_1;
-		pm_clk = SC_PM_CLK_PER;
-		break;
-	default:
-		if (clk->id < IMX8QXP_UART0_IPG_CLK ||
-		    clk->id >= IMX8QXP_CLK_END) {
-			printf("%s(Invalid clk ID #%lu)\n",
-			       __func__, clk->id);
-			return -EINVAL;
-		}
-		return -EINVAL;
-	}
+#if defined(CONFIG_IMX8DXL)
+	CLK_5( IMX8DXL_USB2_PHY2_IPG_CLK, "USB3_ACLK", 28, USB_3_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ),
+#endif
+	CLK_5( IMX8QXP_USB3_ACLK, "USB3_ACLK", 28, USB_3_LPCG, IMX8QXP_USB3_ACLK_DIV ),
+	CLK_5( IMX8QXP_USB3_BUS_CLK, "USB3_BUS", 0, USB_3_LPCG, IMX8QXP_USB3_BUS_DIV ),
+	CLK_5( IMX8QXP_USB3_LPM_CLK, "USB3_LPM", 4, USB_3_LPCG, IMX8QXP_USB3_LPM_DIV ),
+
+	CLK_5( IMX8QXP_GPMI_APB_CLK, "GPMI_APB", 16, NAND_LPCG, IMX8QXP_AXI_CONN_CLK_ROOT ),
+	CLK_5( IMX8QXP_GPMI_APB_BCH_CLK, "GPMI_APB_BCH", 20, NAND_LPCG, IMX8QXP_AXI_CONN_CLK_ROOT ),
+	CLK_5( IMX8QXP_GPMI_BCH_IO_CLK, "GPMI_IO_CLK", 4, NAND_LPCG, IMX8QXP_GPMI_BCH_IO_DIV ),
+	CLK_5( IMX8QXP_GPMI_BCH_CLK, "GPMI_BCH_CLK", 0, NAND_LPCG, IMX8QXP_GPMI_BCH_DIV ),
+	CLK_5( IMX8QXP_APBHDMA_CLK, "GPMI_CLK", 16, NAND_LPCG + 0x4, IMX8QXP_AXI_CONN_CLK_ROOT ),
+
+	CLK_5( IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK, "HSIO_PCIE_A_MSTR_AXI_CLK", 16, HSIO_PCIE_X1_LPCG, IMX8QXP_HSIO_AXI_CLK ),
+	CLK_5( IMX8QXP_HSIO_PCIE_SLV_AXI_CLK, "HSIO_PCIE_A_SLV_AXI_CLK", 20, HSIO_PCIE_X1_LPCG, IMX8QXP_HSIO_AXI_CLK ),
+	CLK_5( IMX8QXP_HSIO_PCIE_DBI_AXI_CLK, "HSIO_PCIE_A_DBI_AXI_CLK", 24, HSIO_PCIE_X1_LPCG, IMX8QXP_HSIO_AXI_CLK ),
+	CLK_5( IMX8QXP_HSIO_PCIE_X1_PER_CLK, "HSIO_PCIE_X1_PER_CLK", 16, HSIO_PCIE_X1_CRR3_LPCG, IMX8QXP_HSIO_PER_CLK ),
+	CLK_5( IMX8QXP_HSIO_PHY_X1_PER_CLK, "HSIO_PHY_X1_PER_CLK", 16, HSIO_PHY_X1_CRR1_LPCG, IMX8QXP_HSIO_PER_CLK ),
+	CLK_5( IMX8QXP_HSIO_MISC_PER_CLK, "HSIO_MISC_PER_CLK", 16, HSIO_MISC_LPCG, IMX8QXP_HSIO_PER_CLK ),
+	CLK_5( IMX8QXP_HSIO_PHY_X1_APB_CLK, "HSIO_PHY_X1_APB_CLK", 16, HSIO_PHY_X1_LPCG, IMX8QXP_HSIO_PER_CLK ),
+	CLK_5( IMX8QXP_HSIO_GPIO_CLK, "HSIO_GPIO_CLK", 16, HSIO_GPIO_LPCG, IMX8QXP_HSIO_PER_CLK ),
+	CLK_5( IMX8QXP_HSIO_PHY_X1_PCLK, "HSIO_PHY_X1_PCLK", 0, HSIO_PHY_X1_LPCG, 0 ),
+	CLK_5( IMX8QXP_LCD_IPG_CLK, "LCD_IPG_CLK", 16, LCD_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ),
+};
 
-	ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
-	if (ret) {
-		printf("%s err %d\n", __func__, ret);
-		return ret;
-	}
+struct imx8_mux_clks imx8qxp_mux_clks[] = {
+	CLK_MUX( IMX8QXP_SDHC0_SEL, "SDHC0_SEL", IMX8QXP_SDHC0_DIV, IMX8QXP_CLK_DUMMY, IMX8QXP_CONN_PLL0_CLK,
+		IMX8QXP_CONN_PLL1_CLK, IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY ),
+	CLK_MUX( IMX8QXP_SDHC1_SEL, "SDHC1_SEL", IMX8QXP_SDHC1_DIV, IMX8QXP_CLK_DUMMY, IMX8QXP_CONN_PLL0_CLK,
+		IMX8QXP_CONN_PLL1_CLK, IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY ),
+	CLK_MUX( IMX8QXP_SDHC2_SEL, "SDHC2_SEL", IMX8QXP_SDHC2_DIV, IMX8QXP_CLK_DUMMY, IMX8QXP_CONN_PLL0_CLK,
+		IMX8QXP_CONN_PLL1_CLK, IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY ),
+
+	CLK_MUX( IMX8QXP_LCD_PXL_SEL, "LCD_PXL_SEL", IMX8QXP_LCD_PXL_DIV, IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY,
+		IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY, IMX8QXP_LCD_PXL_BYPASS_DIV ),
+	CLK_MUX( IMX8QXP_LCD_SEL, "LCD_SEL", IMX8QXP_LCD_DIV, IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY,
+		IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY, IMX8QXP_ELCDIF_PLL_DIV ),
+};
 
-	return 0;
-}
+struct imx8_clks_collect imx8qxp_clk_collect = {
+	{
+		{&imx8qxp_clks, ARRAY_SIZE(imx8qxp_clks)},
+		{&imx8qxp_fixed_clks, ARRAY_SIZE(imx8qxp_fixed_clks)},
+		{&imx8qxp_gpr_clks, ARRAY_SIZE(imx8qxp_gpr_clks)},
+		{&imx8qxp_lpcg_clks, ARRAY_SIZE(imx8qxp_lpcg_clks)},
+		{&imx8qxp_mux_clks, ARRAY_SIZE(imx8qxp_mux_clks)},
+	},
+	FLAG_CLK_IMX8_IMX8QXP,
+};
diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c
new file mode 100644
index 00000000000..87ba829841f
--- /dev/null
+++ b/drivers/clk/imx/clk-imx93.c
@@ -0,0 +1,430 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * Author: Alice Guo <alice.guo@nxp.com>
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <dt-bindings/clock/imx93-clock.h>
+#include <linux/delay.h>
+
+#include "clk.h"
+
+/* Low-speed clocks operating at <=133Mhz */
+static const char *const low_speed_sels[] = { "clock-osc-24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "video_pll" };
+/* Non-IO clocks operating at 133-399MHz */
+static const char *const non_io_sels[] = { "clock-osc-24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "sys_pll_pfd2_div2" };
+/* Clocks for IP with max frequency in the range 400-1000MHz */
+static const char *const fast_speed_sels[] = { "clock-osc-24m", "sys_pll_pfd0", "sys_pll_pfd1", "sys_pll_pfd2" };
+/* Audio interface-related clocks, such as SAI, MQS and SPDIF */
+static const char *const audio_sels[] = { "clock-osc-24m", "audio_pll", "video_pll", "clk_ext" };
+/* Video interface-related clocks */
+static const char *const video_sels[] = { "clock-osc-24m", "audio_pll", "video_pll", "sys_pll_pfd0" };
+/* Special case CKO1 and CKO2 clocks */
+static const char *const cko1_sels[] = { "clock-osc-24m", "sys_pll_pfd0", "sys_pll_pfd1", "audio_pll" };
+static const char *const cko2_sels[] = { "clock-osc-24m", "sys_pll_pfd0", "sys_pll_pfd1", "video_pll" };
+/* Special case TPM clocks */
+static const char *const tpm_sels[] = { "clock-osc-24m", "sys_pll_pfd0", "audio_pll", "clk_ext" };
+static const char *const misc_sels[] = { "clock-osc-24m", "audio_pll", "video_pll", "sys_pll_pfd2" };
+
+struct imx93_clk_root {
+	u32 clk_id;
+	char *name;
+	const char * const *parent_names;
+	u32 off;
+	unsigned long flags;
+};
+
+static struct imx93_clk_root clk_roots[] = {
+	{ IMX93_CLK_A55_PERIPH, "a55_periph_root", fast_speed_sels, 0x0000, CLK_IS_CRITICAL },
+	{ IMX93_CLK_A55_MTR_BUS, "a55_mtr_bus_root", low_speed_sels, 0x0080, CLK_IS_CRITICAL },
+	{ IMX93_CLK_A55, "a55_root", fast_speed_sels, 0x0100, CLK_IS_CRITICAL },
+	{ IMX93_CLK_M33, "m33_root", low_speed_sels, 0x0180, CLK_IS_CRITICAL },
+	{ IMX93_CLK_BUS_WAKEUP, "bus_wakeup_root", low_speed_sels, 0x0280, CLK_IS_CRITICAL },
+	{ IMX93_CLK_BUS_AON, "bus_aon_root", low_speed_sels, 0x0300, CLK_IS_CRITICAL },
+	{ IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", fast_speed_sels, 0x0380, CLK_IS_CRITICAL },
+	{ IMX93_CLK_SWO_TRACE, "swo_trace_root", low_speed_sels, 0x0400, },
+	{ IMX93_CLK_M33_SYSTICK, "m33_systick_root", low_speed_sels, 0x0480, },
+	{ IMX93_CLK_FLEXIO1, "flexio1_root", low_speed_sels, 0x0500, },
+	{ IMX93_CLK_FLEXIO2, "flexio2_root", low_speed_sels, 0x0580, },
+	{ IMX93_CLK_LPIT1, "lpit1_root", low_speed_sels, 0x0600, },
+	{ IMX93_CLK_LPIT2, "lpit2_root", low_speed_sels, 0x0680, },
+	{ IMX93_CLK_LPTMR1, "lptmr1_root", low_speed_sels, 0x0700, },
+	{ IMX93_CLK_LPTMR2, "lptmr2_root", low_speed_sels, 0x0780, },
+	{ IMX93_CLK_TPM1, "tpm1_root", tpm_sels, 0x0800, },
+	{ IMX93_CLK_TPM2, "tpm2_root", tpm_sels, 0x0880, },
+	{ IMX93_CLK_TPM3, "tpm3_root", tpm_sels, 0x0900, },
+	{ IMX93_CLK_TPM4, "tpm4_root", tpm_sels, 0x0980, },
+	{ IMX93_CLK_TPM5, "tpm5_root", tpm_sels, 0x0a00, },
+	{ IMX93_CLK_TPM6, "tpm6_root", tpm_sels, 0x0a80, },
+	{ IMX93_CLK_FLEXSPI1, "flexspi1_root", fast_speed_sels, 0x0b00, },
+	{ IMX93_CLK_CAN1, "can1_root", low_speed_sels, 0x0b80, },
+	{ IMX93_CLK_CAN2, "can2_root", low_speed_sels, 0x0c00, },
+	{ IMX93_CLK_LPUART1, "lpuart1_root", low_speed_sels, 0x0c80, },
+	{ IMX93_CLK_LPUART2, "lpuart2_root", low_speed_sels, 0x0d00, },
+	{ IMX93_CLK_LPUART3, "lpuart3_root", low_speed_sels, 0x0d80, },
+	{ IMX93_CLK_LPUART4, "lpuart4_root", low_speed_sels, 0x0e00, },
+	{ IMX93_CLK_LPUART5, "lpuart5_root", low_speed_sels, 0x0e80, },
+	{ IMX93_CLK_LPUART6, "lpuart6_root", low_speed_sels, 0x0f00, },
+	{ IMX93_CLK_LPUART7, "lpuart7_root", low_speed_sels, 0x0f80, },
+	{ IMX93_CLK_LPUART8, "lpuart8_root", low_speed_sels, 0x1000, },
+	{ IMX93_CLK_LPI2C1, "lpi2c1_root", low_speed_sels, 0x1080, },
+	{ IMX93_CLK_LPI2C2, "lpi2c2_root", low_speed_sels, 0x1100, },
+	{ IMX93_CLK_LPI2C3, "lpi2c3_root", low_speed_sels, 0x1180, },
+	{ IMX93_CLK_LPI2C4, "lpi2c4_root", low_speed_sels, 0x1200, },
+	{ IMX93_CLK_LPI2C5, "lpi2c5_root", low_speed_sels, 0x1280, },
+	{ IMX93_CLK_LPI2C6, "lpi2c6_root", low_speed_sels, 0x1300, },
+	{ IMX93_CLK_LPI2C7, "lpi2c7_root", low_speed_sels, 0x1380, },
+	{ IMX93_CLK_LPI2C8, "lpi2c8_root", low_speed_sels, 0x1400, },
+	{ IMX93_CLK_LPSPI1, "lpspi1_root", low_speed_sels, 0x1480, },
+	{ IMX93_CLK_LPSPI2, "lpspi2_root", low_speed_sels, 0x1500, },
+	{ IMX93_CLK_LPSPI3, "lpspi3_root", low_speed_sels, 0x1580, },
+	{ IMX93_CLK_LPSPI4, "lpspi4_root", low_speed_sels, 0x1600, },
+	{ IMX93_CLK_LPSPI5, "lpspi5_root", low_speed_sels, 0x1680, },
+	{ IMX93_CLK_LPSPI6, "lpspi6_root", low_speed_sels, 0x1700, },
+	{ IMX93_CLK_LPSPI7, "lpspi7_root", low_speed_sels, 0x1780, },
+	{ IMX93_CLK_LPSPI8, "lpspi8_root", low_speed_sels, 0x1800, },
+	{ IMX93_CLK_I3C1, "i3c1_root", low_speed_sels, 0x1880, },
+	{ IMX93_CLK_I3C2, "i3c2_root", low_speed_sels, 0x1900, },
+	{ IMX93_CLK_USDHC1, "usdhc1_root", fast_speed_sels, 0x1980, },
+	{ IMX93_CLK_USDHC2, "usdhc2_root", fast_speed_sels, 0x1a00, },
+	{ IMX93_CLK_USDHC3, "usdhc3_root", fast_speed_sels, 0x1a80, },
+	{ IMX93_CLK_SAI1, "sai1_root", audio_sels, 0x1b00, },
+	{ IMX93_CLK_SAI2, "sai2_root", audio_sels, 0x1b80, },
+	{ IMX93_CLK_SAI3, "sai3_root", audio_sels, 0x1c00, },
+	{ IMX93_CLK_CCM_CKO1, "ccm_cko1_root", cko1_sels, 0x1c80, },
+	{ IMX93_CLK_CCM_CKO2, "ccm_cko2_root", cko2_sels, 0x1d00, },
+	{ IMX93_CLK_CCM_CKO3, "ccm_cko3_root", cko1_sels, 0x1d80, },
+	{ IMX93_CLK_CCM_CKO4, "ccm_cko4_root", cko2_sels, 0x1e00, },
+	{ IMX93_CLK_HSIO, "hsio_root", low_speed_sels, 0x1e80, },
+	{ IMX93_CLK_HSIO_USB_TEST_60M, "hsio_usb_test_60m_root", low_speed_sels, 0x1f00, },
+	{ IMX93_CLK_HSIO_ACSCAN_80M, "hsio_acscan_80m_root", low_speed_sels, 0x1f80, },
+	{ IMX93_CLK_HSIO_ACSCAN_480M, "hsio_acscan_480m_root", misc_sels, 0x2000, },
+	{ IMX93_CLK_ML_APB, "ml_apb_root", low_speed_sels, 0x2180, },
+	{ IMX93_CLK_ML, "ml_root", fast_speed_sels, 0x2200, },
+	{ IMX93_CLK_MEDIA_AXI, "media_axi_root", fast_speed_sels, 0x2280, },
+	{ IMX93_CLK_MEDIA_APB, "media_apb_root", low_speed_sels, 0x2300, },
+	{ IMX93_CLK_MEDIA_LDB, "media_ldb_root", video_sels, 0x2380, },
+	{ IMX93_CLK_MEDIA_DISP_PIX, "media_disp_pix_root", video_sels, 0x2400, },
+	{ IMX93_CLK_CAM_PIX, "cam_pix_root", video_sels, 0x2480, },
+	{ IMX93_CLK_MIPI_TEST_BYTE, "mipi_test_byte_root", video_sels, 0x2500, },
+	{ IMX93_CLK_MIPI_PHY_CFG, "mipi_phy_cfg_root", video_sels, 0x2580, },
+	{ IMX93_CLK_ADC, "adc_root", low_speed_sels, 0x2700, },
+	{ IMX93_CLK_PDM, "pdm_root", audio_sels, 0x2780, },
+	{ IMX93_CLK_TSTMR1, "tstmr1_root", low_speed_sels, 0x2800, },
+	{ IMX93_CLK_TSTMR2, "tstmr2_root", low_speed_sels, 0x2880, },
+	{ IMX93_CLK_MQS1, "mqs1_root", audio_sels, 0x2900, },
+	{ IMX93_CLK_MQS2, "mqs2_root", audio_sels, 0x2980, },
+	{ IMX93_CLK_AUDIO_XCVR, "audio_xcvr_root", non_io_sels, 0x2a00, },
+	{ IMX93_CLK_SPDIF, "spdif_root", audio_sels, 0x2a80, },
+	{ IMX93_CLK_ENET, "enet_root", non_io_sels, 0x2b00, },
+	{ IMX93_CLK_ENET_TIMER1, "enet_timer1_root", low_speed_sels, 0x2b80, },
+	{ IMX93_CLK_ENET_TIMER2, "enet_timer2_root", low_speed_sels, 0x2c00, },
+	{ IMX93_CLK_ENET_REF, "enet_ref_root", non_io_sels, 0x2c80, },
+	{ IMX93_CLK_ENET_REF_PHY, "enet_ref_phy_root", low_speed_sels, 0x2d00, },
+	{ IMX93_CLK_I3C1_SLOW, "i3c1_slow_root", low_speed_sels, 0x2d80, },
+	{ IMX93_CLK_I3C2_SLOW, "i3c2_slow_root", low_speed_sels, 0x2e00, },
+	{ IMX93_CLK_USB_PHY_BURUNIN, "usb_phy_root", low_speed_sels, 0x2e80, },
+	{ IMX93_CLK_PAL_CAME_SCAN, "pal_came_scan_root", misc_sels, 0x2f00, }
+};
+
+struct imx93_clk_ccgr {
+	u32 clk_id;
+	char *name;
+	char *parent_names;
+	u32 off;
+	unsigned long flags;
+};
+
+static struct imx93_clk_ccgr clk_ccgrs[] = {
+	{ IMX93_CLK_A55_GATE, "a55", "a55_root", 0x8000, CLK_IS_CRITICAL },
+	{ IMX93_CLK_CM33_GATE, "cm33", "m33_root", 0x8040, CLK_IS_CRITICAL },
+	{ IMX93_CLK_ADC1_GATE, "adc1", "clock-osc-24m", 0x82c0, },
+	{ IMX93_CLK_WDOG1_GATE, "wdog1", "clock-osc-24m", 0x8300, },
+	{ IMX93_CLK_WDOG2_GATE, "wdog2", "clock-osc-24m", 0x8340, },
+	{ IMX93_CLK_WDOG3_GATE, "wdog3", "clock-osc-24m", 0x8380, },
+	{ IMX93_CLK_WDOG4_GATE, "wdog4", "clock-osc-24m", 0x83c0, },
+	{ IMX93_CLK_WDOG5_GATE, "wdog5", "clock-osc-24m", 0x8400, },
+	{ IMX93_CLK_SEMA1_GATE, "sema1", "bus_aon_root", 0x8440, },
+	{ IMX93_CLK_SEMA2_GATE, "sema2", "bus_wakeup_root", 0x8480, },
+	{ IMX93_CLK_MU_A_GATE, "mu_a", "bus_aon_root", 0x84c0, },
+	{ IMX93_CLK_MU_B_GATE, "mu_b", "bus_aon_root", 0x8500, },
+	{ IMX93_CLK_EDMA1_GATE, "edma1", "wakeup_axi_root", 0x8540, },
+	{ IMX93_CLK_EDMA2_GATE, "edma2", "wakeup_axi_root", 0x8580, },
+	{ IMX93_CLK_FLEXSPI1_GATE, "flexspi1", "flexspi1_root", 0x8640, },
+	{ IMX93_CLK_GPIO1_GATE, "gpio1", "m33_root", 0x8880, },
+	{ IMX93_CLK_GPIO2_GATE, "gpio2", "bus_wakeup_root", 0x88c0, },
+	{ IMX93_CLK_GPIO3_GATE, "gpio3", "bus_wakeup_root", 0x8900, },
+	{ IMX93_CLK_GPIO4_GATE, "gpio4", "bus_wakeup_root", 0x8940, },
+	{ IMX93_CLK_FLEXIO1_GATE, "flexio1", "flexio1_root", 0x8980, },
+	{ IMX93_CLK_FLEXIO2_GATE, "flexio2", "flexio2_root", 0x89c0, },
+	{ IMX93_CLK_LPIT1_GATE, "lpit1", "lpit1_root", 0x8a00, },
+	{ IMX93_CLK_LPIT2_GATE, "lpit2", "lpit2_root", 0x8a40, },
+	{ IMX93_CLK_LPTMR1_GATE, "lptmr1", "lptmr1_root", 0x8a80, },
+	{ IMX93_CLK_LPTMR2_GATE, "lptmr2", "lptmr2_root", 0x8ac0, },
+	{ IMX93_CLK_TPM1_GATE, "tpm1", "tpm1_root", 0x8b00, },
+	{ IMX93_CLK_TPM2_GATE, "tpm2", "tpm2_root", 0x8b40, },
+	{ IMX93_CLK_TPM3_GATE, "tpm3", "tpm3_root", 0x8b80, },
+	{ IMX93_CLK_TPM4_GATE, "tpm4", "tpm4_root", 0x8bc0, },
+	{ IMX93_CLK_TPM5_GATE, "tpm5", "tpm5_root", 0x8c00, },
+	{ IMX93_CLK_TPM6_GATE, "tpm6", "tpm6_root", 0x8c40, },
+	{ IMX93_CLK_CAN1_GATE, "can1", "can1_root", 0x8c80, },
+	{ IMX93_CLK_CAN2_GATE, "can2", "can2_root", 0x8cc0, },
+	{ IMX93_CLK_LPUART1_GATE, "lpuart1", "lpuart1_root", 0x8d00, },
+	{ IMX93_CLK_LPUART2_GATE, "lpuart2", "lpuart2_root", 0x8d40, },
+	{ IMX93_CLK_LPUART3_GATE, "lpuart3", "lpuart3_root", 0x8d80, },
+	{ IMX93_CLK_LPUART4_GATE, "lpuart4", "lpuart4_root", 0x8dc0, },
+	{ IMX93_CLK_LPUART5_GATE, "lpuart5", "lpuart5_root", 0x8e00, },
+	{ IMX93_CLK_LPUART6_GATE, "lpuart6", "lpuart6_root", 0x8e40, },
+	{ IMX93_CLK_LPUART7_GATE, "lpuart7", "lpuart7_root", 0x8e80, },
+	{ IMX93_CLK_LPUART8_GATE, "lpuart8", "lpuart8_root", 0x8ec0, },
+	{ IMX93_CLK_LPI2C1_GATE, "lpi2c1", "lpi2c1_root", 0x8f00, },
+	{ IMX93_CLK_LPI2C2_GATE, "lpi2c2", "lpi2c2_root", 0x8f40, },
+	{ IMX93_CLK_LPI2C3_GATE, "lpi2c3", "lpi2c3_root", 0x8f80, },
+	{ IMX93_CLK_LPI2C4_GATE, "lpi2c4", "lpi2c4_root", 0x8fc0, },
+	{ IMX93_CLK_LPI2C5_GATE, "lpi2c5", "lpi2c5_root", 0x9000, },
+	{ IMX93_CLK_LPI2C6_GATE, "lpi2c6", "lpi2c6_root", 0x9040, },
+	{ IMX93_CLK_LPI2C7_GATE, "lpi2c7", "lpi2c7_root", 0x9080, },
+	{ IMX93_CLK_LPI2C8_GATE, "lpi2c8", "lpi2c8_root", 0x90c0, },
+	{ IMX93_CLK_LPSPI1_GATE, "lpspi1", "lpspi1_root", 0x9100, },
+	{ IMX93_CLK_LPSPI2_GATE, "lpspi2", "lpspi2_root", 0x9140, },
+	{ IMX93_CLK_LPSPI3_GATE, "lpspi3", "lpspi3_root", 0x9180, },
+	{ IMX93_CLK_LPSPI4_GATE, "lpspi4", "lpspi4_root", 0x91c0, },
+	{ IMX93_CLK_LPSPI5_GATE, "lpspi5", "lpspi5_root", 0x9200, },
+	{ IMX93_CLK_LPSPI6_GATE, "lpspi6", "lpspi6_root", 0x9240, },
+	{ IMX93_CLK_LPSPI7_GATE, "lpspi7", "lpspi7_root", 0x9280, },
+	{ IMX93_CLK_LPSPI8_GATE, "lpspi8", "lpspi8_root", 0x92c0, },
+	{ IMX93_CLK_I3C1_GATE, "i3c1", "i3c1_root", 0x9300, },
+	{ IMX93_CLK_I3C2_GATE, "i3c2", "i3c2_root", 0x9340, },
+	{ IMX93_CLK_USDHC1_GATE, "usdhc1", "usdhc1_root", 0x9380, },
+	{ IMX93_CLK_USDHC2_GATE, "usdhc2", "usdhc2_root", 0x93c0, },
+	{ IMX93_CLK_USDHC3_GATE, "usdhc3", "usdhc3_root", 0x9400, },
+	{ IMX93_CLK_SAI1_GATE, "sai1", "sai1_root", 0x9440, },
+	{ IMX93_CLK_SAI2_GATE, "sai2", "sai2_root", 0x9480, },
+	{ IMX93_CLK_SAI3_GATE, "sai3", "sai3_root", 0x94c0, },
+	{ IMX93_CLK_MIPI_CSI_GATE, "mipi_csi", "media_apb_root", 0x9580, },
+	{ IMX93_CLK_MIPI_DSI_GATE, "mipi_dsi", "media_apb_root", 0x95c0, },
+	{ IMX93_CLK_LVDS_GATE, "lvds", "media_ldb_root", 0x9600, },
+	{ IMX93_CLK_LCDIF_GATE, "lcdif", "media_apb_root", 0x9640, },
+	{ IMX93_CLK_PXP_GATE, "pxp", "media_apb_root", 0x9680, },
+	{ IMX93_CLK_ISI_GATE, "isi", "media_apb_root", 0x96c0, },
+	{ IMX93_CLK_NIC_MEDIA_GATE, "nic_media", "media_apb_root", 0x9700, },
+	{ IMX93_CLK_USB_CONTROLLER_GATE, "usb_controller", "hsio_root", 0x9a00, },
+	{ IMX93_CLK_USB_TEST_60M_GATE, "usb_test_60m", "hsio_usb_test_60m_root", 0x9a40, },
+	{ IMX93_CLK_HSIO_TROUT_24M_GATE, "hsio_trout_24m", "clock-osc-24m", 0x9a80, },
+	{ IMX93_CLK_PDM_GATE, "pdm", "pdm_root", 0x9ac0, },
+	{ IMX93_CLK_MQS1_GATE, "mqs1", "sai1_root", 0x9b00, },
+	{ IMX93_CLK_MQS2_GATE, "mqs2", "sai3_root", 0x9b40, },
+	{ IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, },
+	{ IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, },
+	{ IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "clock-osc-32k", 0x9dc0, },
+	{ IMX93_CLK_ENET1_GATE, "enet1", "enet_root", 0x9e00, },
+	{ IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, },
+	{ IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "clock-osc-24m", 0x9e80, },
+	{ IMX93_CLK_TSTMR1_GATE, "tstmr1", "bus_aon_root", 0x9ec0, },
+	{ IMX93_CLK_TSTMR2_GATE, "tstmr2", "bus_wakeup_root", 0x9f00, },
+	{ IMX93_CLK_TMC_GATE, "tmc", "clock-osc-24m", 0x9f40, },
+	{ IMX93_CLK_PMRO_GATE, "pmro", "clock-osc-24m", 0x9f80, }
+};
+
+static ulong imx93_clk_set_rate(struct clk *clk, ulong rate)
+{
+	struct clk *c;
+	int err = clk_get_by_id(clk->id, &c);
+
+	if (err)
+		return err;
+	return clk_set_rate(c, rate);
+}
+
+static ulong imx93_clk_get_rate(struct clk *clk)
+{
+	struct clk *c;
+	int err = clk_get_by_id(clk->id, &c);
+
+	if (err)
+		return err;
+	return clk_get_rate(c);
+}
+
+static int imx93_clk_enable(struct clk *clk)
+{
+	struct clk *c;
+	int err = clk_get_by_id(clk->id, &c);
+
+	if (err)
+		return err;
+	return clk_enable(c);
+}
+
+static int imx93_clk_disable(struct clk *clk)
+{
+	struct clk *c;
+	int err = clk_get_by_id(clk->id, &c);
+
+	if (err)
+		return err;
+	return clk_disable(c);
+}
+
+static int imx93_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct clk *c, *p;
+	int err = clk_get_by_id(clk->id, &c);
+
+	if (err)
+		return err;
+
+	err = clk_get_by_id(parent->id, &p);
+	if (err)
+		return err;
+
+	return clk_set_parent(c, p);
+}
+
+static struct clk_ops imx93_clk_ops = {
+	.set_rate = imx93_clk_set_rate,
+	.get_rate = imx93_clk_get_rate,
+	.enable = imx93_clk_enable,
+	.disable = imx93_clk_disable,
+	.set_parent = imx93_clk_set_parent,
+};
+
+struct clk *imx93_clk_composite(const char *name, const char * const *parent_names,
+				int num_parents, void __iomem *reg, unsigned long flags)
+{
+	struct clk *clk = ERR_PTR(-ENOMEM);
+	struct clk_divider *div = NULL;
+	struct clk_gate *gate = NULL;
+	struct clk_mux *mux = NULL;
+
+	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+	if (!mux)
+		goto fail;
+
+	mux->reg = reg;
+	mux->shift = 8;
+	mux->mask = 3;
+	mux->num_parents = num_parents;
+	mux->flags = flags;
+	mux->parent_names = parent_names;
+
+	div = kzalloc(sizeof(*div), GFP_KERNEL);
+	if (!div)
+		goto fail;
+
+	div->reg = reg;
+	div->shift = 0;
+	div->width = 8;
+	div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
+
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	if (!gate)
+		goto fail;
+
+	gate->reg = reg;
+	gate->bit_idx = 24;
+	gate->flags = CLK_GATE_SET_TO_DISABLE | flags;
+
+	clk = clk_register_composite(NULL, name, parent_names, num_parents,
+				     &mux->clk, &clk_mux_ops,
+				     &div->clk, &clk_divider_ops,
+				     &gate->clk, &clk_gate_ops, flags);
+	if (IS_ERR(clk))
+		goto fail;
+
+	return clk;
+
+fail:
+	kfree(gate);
+	kfree(div);
+	kfree(mux);
+	return ERR_CAST(clk);
+}
+
+static int imx93_clk_probe(struct udevice *dev)
+{
+	void __iomem *ccm_base;
+	struct imx93_clk_root *root;
+	struct imx93_clk_ccgr *ccgr;
+	struct clk *clk;
+	struct clk fixed_clock;
+	int ret;
+
+	clk_dm(IMX93_CLK_DUMMY, clk_register_fixed_rate(NULL, "dummy", 0UL));
+
+	ret = clk_get_by_name(dev, "osc_24m", &fixed_clock);
+	if (ret)
+		return ret;
+	clk_dm(IMX93_CLK_24M, dev_get_clk_ptr(fixed_clock.dev));
+
+	ret = clk_get_by_name(dev, "clk_ext1", &fixed_clock);
+	if (ret)
+		return ret;
+	clk_dm(IMX93_CLK_EXT1, dev_get_clk_ptr(fixed_clock.dev));
+
+	ret = clk_get_by_name(dev, "osc_32k", &fixed_clock);
+	if (ret)
+		return ret;
+	clk_dm(IMX93_CLK_32K, dev_get_clk_ptr(fixed_clock.dev));
+
+	clk_dm(IMX93_CLK_SYS_PLL_PFD0,
+	       clk_register_fixed_rate(NULL, "sys_pll_pfd0", 1000000000UL));
+	clk_dm(IMX93_CLK_SYS_PLL_PFD0_DIV2,
+	       imx_clk_fixed_factor("sys_pll_pfd0_div2", "sys_pll_pfd0", 1, 2));
+
+	clk_dm(IMX93_CLK_SYS_PLL_PFD1,
+	       clk_register_fixed_rate(NULL, "sys_pll_pfd1", 800000000UL));
+	clk_dm(IMX93_CLK_SYS_PLL_PFD1_DIV2,
+	       imx_clk_fixed_factor("sys_pll_pfd1_div2", "sys_pll_pfd1", 1, 2));
+
+	clk_dm(IMX93_CLK_SYS_PLL_PFD2,
+	       clk_register_fixed_rate(NULL, "sys_pll_pfd2", 625000000UL));
+	clk_dm(IMX93_CLK_SYS_PLL_PFD2_DIV2,
+	       imx_clk_fixed_factor("sys_pll_pfd2_div2", "sys_pll_pfd2", 1, 2));
+
+#ifndef CONFIG_SPL_BUILD
+	clk_dm(IMX93_CLK_VIDEO_PLL,
+	       clk_register_imx93_pll("video_pll", "clock-osc-24m", (void __iomem *)0x44481400));
+#endif
+
+	ccm_base = dev_read_addr_ptr(dev);
+	if (ccm_base == (void *)FDT_ADDR_T_NONE) {
+		debug("%s: No CCM register base address\n", __func__);
+		return -EINVAL;
+	}
+
+	for (int i = 0; i < ARRAY_SIZE(clk_roots); i++) {
+		root = &clk_roots[i];
+		clk = imx93_clk_composite(root->name, root->parent_names, 4,
+					  ccm_base + root->off, root->flags);
+		clk_dm(root->clk_id, clk);
+	}
+
+	for (int i = 0; i < ARRAY_SIZE(clk_ccgrs); i++) {
+		ccgr = &clk_ccgrs[i];
+		clk = imx_clk_gate4_flags(ccgr->name, ccgr->parent_names,
+					  ccm_base + ccgr->off, 0, ccgr->flags);
+		clk_dm(ccgr->clk_id, clk);
+	}
+
+	return 0;
+}
+
+static const struct udevice_id imx93_clk_ids[] = {
+	{ .compatible = "fsl,imx93-ccm" },
+	{ },
+};
+
+U_BOOT_DRIVER(imx93_clk) = {
+	.name = "imx93_clk",
+	.id = UCLASS_CLK,
+	.of_match = imx93_clk_ids,
+	.ops = &imx93_clk_ops,
+	.probe = imx93_clk_probe,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 60f287046b9..dd4df821250 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -41,6 +41,18 @@ struct imx_pll14xx_clk {
 	int flags;
 };
 
+struct imx93_pll_fracn_gp {
+	unsigned int rate;
+	unsigned int mfi;
+	unsigned int mfn;
+	unsigned int mfd;
+	unsigned int rdiv;
+	unsigned int odiv;
+};
+
+struct clk *clk_register_imx93_pll(const char *name, const char *parent_name,
+				   void __iomem *reg);
+
 struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
 			    void __iomem *base,
 			    const struct imx_pll14xx_clk *pll_clk);
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 901c1e2f7db..b12f5949637 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -570,7 +570,7 @@ int device_probe(struct udevice *dev)
 	}
 
 	/* Only handle devices that have a valid ofnode */
-	if (dev_has_ofnode(dev)) {
+	if (dev_has_ofnode(dev) && !(dev->driver->flags & DM_FLAG_IGNORE_DEFAULT_CLKS)) {
 		/*
 		 * Process 'assigned-{clocks/clock-parents/clock-rates}'
 		 * properties
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index abddbef57b8..c39c3adfe7b 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -35,6 +35,8 @@ const char *get_imx8_type(u32 imxtype)
 		return "QXP";
 	case MXC_CPU_IMX8QM:
 		return "QM";
+	case MXC_CPU_IMX8DXL:
+		return "DXL";
 	default:
 		return "??";
 	}
@@ -49,6 +51,10 @@ const char *get_imx8_rev(u32 rev)
 		return "B";
 	case CHIP_REV_C:
 		return "C";
+	case CHIP_REV_A1:
+		return "A1";
+	case CHIP_REV_A2:
+		return "A2";
 	default:
 		return "?";
 	}
@@ -209,6 +215,7 @@ static int imx8_cpu_probe(struct udevice *dev)
 {
 	struct cpu_imx_plat *plat = dev_get_plat(dev);
 	u32 cpurev;
+	fdt_addr_t addr;
 
 	set_core_data(dev);
 	cpurev = get_cpu_rev();
@@ -216,12 +223,14 @@ static int imx8_cpu_probe(struct udevice *dev)
 	plat->rev = get_imx8_rev(cpurev & 0xFFF);
 	plat->type = get_imx8_type((cpurev & 0xFF000) >> 12);
 	plat->freq_mhz = imx8_get_cpu_rate(dev) / 1000000;
-	plat->mpidr = dev_read_addr(dev);
-	if (plat->mpidr == FDT_ADDR_T_NONE) {
+	addr = dev_read_addr(dev);
+	if (addr == FDT_ADDR_T_NONE) {
 		printf("%s: Failed to get CPU reg property\n", __func__);
 		return -EINVAL;
 	}
 
+	plat->mpidr = (u32)addr;
+
 	return 0;
 }
 
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index 94ff5401119..da5955e31de 100644
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -2,6 +2,7 @@ config FSL_CAAM
 	bool "Freescale Crypto Driver Support"
 	select SHA_HW_ACCEL
 	# hw_sha1() under drivers/crypto, and needed with SHA_HW_ACCEL
+	select MISC if DM
 	imply SPL_CRYPTO if (ARM && SPL)
 	imply CMD_HASH
 	help
@@ -11,7 +12,7 @@ config FSL_CAAM
 
 config CAAM_64BIT
 	bool
-	default y if PHYS_64BIT && !ARCH_IMX8M
+	default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8 && !ARCH_IMX8ULP
 	help
 	  Select Crypto driver for 64 bits CAAM version
 
@@ -66,4 +67,42 @@ config FSL_CAAM_RNG
 	  using the prediction resistance flag which means the DRGB is
 	  reseeded from the TRNG every time random data is generated.
 
+config FSL_BLOB
+	bool "Enable Blob Encap/Decap, Blob KEK support"
+
+config RNG_SELF_TEST
+	bool "RNG self test"
+	help
+	 Enable RNG self test.
+	 Following is the typical warning message when ROM/HAB fails rng self test
+	 ------------+----+------+----+----------------------------------------
+	 Persistent  | T  |  L   | P  | Contents
+	 Memory      | a  |  e   | a  |
+	 Record      | g  |  n   | r  |
+	 Type        |    |  g   |    |
+	             |    |  t   |    |
+	             |    |  h   |    |
+	 ------------+----+------+----+-------------------------------------------------
+	 Event       |0xdb|0x0024|0x42| SRCE Field: 69 30 e1 1d
+	             |    |      |    |             STS = HAB_WARNING (0x69)
+	             |    |      |    |             RSN = HAB_ENG_FAIL (0x30)
+	             |    |      |    |             CTX = HAB_CTX_ENTRY (0xE1)
+	             |    |      |    |             ENG = HAB_ENG_CAAM (0x1d)
+	             |    |      |    | Evt Data (hex):
+	             |    |      |    |  00 04 00 02 40 00 36 06 55 55 00 03 00 00 00 00
+	             |    |      |    |  00 00 00 00 00 00 00 00 00 00 00 01
+	 ------------+----+------+----+-------------------------------------------------
+	 In this scenario RNG self test needs to be run explicitly and
+	 must be run before running any RNG based crypto implementation.
+
 endif
+
+config FSL_DCP_RNG
+	bool "Enable Random Number Generator support"
+	depends on DM_RNG
+	default n
+	help
+	Enable support for the hardware based random number generator
+	module of the DCP.It uses the True Random Number Generator (TRNG)
+	and a Pseudo-Random Number Generator (PRNG) to achieve a true
+	randomness and cryptographic strength.
diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile
index f9c3ccecfc2..c653208d23a 100644
--- a/drivers/crypto/fsl/Makefile
+++ b/drivers/crypto/fsl/Makefile
@@ -4,7 +4,10 @@
 
 obj-y += sec.o
 obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o
-obj-$(CONFIG_CMD_BLOB)$(CONFIG_IMX_CAAM_DEK_ENCAP) += fsl_blob.o
+obj-$(CONFIG_FSL_BLOB) += fsl_blob.o
 obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o
 obj-$(CONFIG_FSL_CAAM_RNG) += rng.o
-obj-$(CONFIG_FSL_MFGPROT) += fsl_mfgprot.o
+obj-$(CONFIG_FSL_DCP_RNG) += dcp_rng.o
+obj-$(CONFIG_IMX_CAAM_MFG_PROT) += fsl_mfgprot.o
+obj-$(CONFIG_RNG_SELF_TEST) += rng_self_test.o
+obj-$(CONFIG_CMD_PROVISION_KEY) += fsl_aes.o tag_object.o
diff --git a/drivers/crypto/fsl/dcp_rng.c b/drivers/crypto/fsl/dcp_rng.c
new file mode 100644
index 00000000000..a797710c2e9
--- /dev/null
+++ b/drivers/crypto/fsl/dcp_rng.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * RNG driver for Freescale RNGC
+ *
+ * Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 Martin Kaiser <martin@kaiser.cx>
+ *	Copyright 2022 NXP
+ *
+ * Based on RNGC driver in drivers/char/hw_random/imx-rngc.c in Linux
+ */
+
+#include <asm/cache.h>
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <rng.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include <dm/root.h>
+
+#define DCP_RNG_MAX_FIFO_STORE_SIZE	4
+#define RNGC_VER_ID			0x0000
+#define RNGC_COMMAND			0x0004
+#define RNGC_CONTROL			0x0008
+#define RNGC_STATUS			0x000C
+#define RNGC_ERROR			0x0010
+#define RNGC_FIFO			0x0014
+
+/* the fields in the ver id register */
+#define RNGC_TYPE_SHIFT			28
+
+/* the rng_type field */
+#define RNGC_TYPE_RNGB			0x1
+#define RNGC_TYPE_RNGC			0x2
+
+#define RNGC_CMD_CLR_ERR		0x00000020
+#define RNGC_CMD_SEED			0x00000002
+
+#define RNGC_CTRL_AUTO_SEED		0x00000010
+
+#define RNGC_STATUS_ERROR		0x00010000
+#define RNGC_STATUS_FIFO_LEVEL_MASK	0x00000f00
+#define RNGC_STATUS_FIFO_LEVEL_SHIFT	8
+#define RNGC_STATUS_SEED_DONE		0x00000020
+#define RNGC_STATUS_ST_DONE		0x00000010
+
+#define RNGC_ERROR_STATUS_STAT_ERR	0x00000008
+
+#define RNGC_TIMEOUT			3000000U /* 3 sec */
+
+struct imx_rngc {
+	unsigned long base;
+};
+
+static int rngc_read(struct udevice *dev, void *data, size_t len)
+{
+	struct imx_rngc *rngc = dev_get_priv(dev);
+	u8 buffer[DCP_RNG_MAX_FIFO_STORE_SIZE];
+	u32 status, level;
+	size_t size;
+
+	while (len) {
+		status = readl(rngc->base + RNGC_STATUS);
+
+		/* is there some error while reading this random number? */
+		if (status & RNGC_STATUS_ERROR)
+			break;
+		/* how many random numbers are in FIFO? [0-16] */
+		level = (status & RNGC_STATUS_FIFO_LEVEL_MASK) >>
+			RNGC_STATUS_FIFO_LEVEL_SHIFT;
+
+		if (level) {
+			/* retrieve a random number from FIFO */
+			*(u32 *)buffer = readl(rngc->base + RNGC_FIFO);
+			size = min(len, sizeof(u32));
+			memcpy(data, buffer, size);
+			data += size;
+			len -= size;
+		}
+	}
+
+	return len ? -EIO : 0;
+}
+
+static int rngc_init(struct imx_rngc *rngc)
+{
+	u32 cmd, ctrl, status, err_reg = 0;
+	unsigned long long timeval = 0;
+	unsigned long long timeout = RNGC_TIMEOUT;
+
+	/* clear error */
+	cmd = readl(rngc->base + RNGC_COMMAND);
+	writel(cmd | RNGC_CMD_CLR_ERR, rngc->base + RNGC_COMMAND);
+
+	/* create seed, repeat while there is some statistical error */
+	do {
+		/* seed creation */
+		cmd = readl(rngc->base + RNGC_COMMAND);
+		writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND);
+
+		udelay(1);
+		timeval += 1;
+
+		status = readl(rngc->base + RNGC_STATUS);
+		err_reg = readl(rngc->base + RNGC_ERROR);
+
+		if (status & (RNGC_STATUS_SEED_DONE | RNGC_STATUS_ST_DONE))
+			break;
+
+		if (timeval > timeout) {
+			debug("rngc timed out\n");
+			return -ETIMEDOUT;
+		}
+	} while (err_reg == RNGC_ERROR_STATUS_STAT_ERR);
+
+	if (err_reg)
+		return -EIO;
+
+	/*
+	 * enable automatic seeding, the rngc creates a new seed automatically
+	 * after serving 2^20 random 160-bit words
+	 */
+	ctrl = readl(rngc->base + RNGC_CONTROL);
+	ctrl |= RNGC_CTRL_AUTO_SEED;
+	writel(ctrl, rngc->base + RNGC_CONTROL);
+	return 0;
+}
+
+static int rngc_probe(struct udevice *dev)
+{
+	struct imx_rngc *rngc = dev_get_priv(dev);
+	fdt_addr_t addr;
+	u32 ver_id;
+	u8  rng_type;
+	int ret;
+
+	addr = dev_read_addr(dev);
+	if (addr == FDT_ADDR_T_NONE) {
+		ret = -EINVAL;
+		goto err;
+	}
+
+	rngc->base = addr;
+	ver_id = readl(rngc->base + RNGC_VER_ID);
+	rng_type = ver_id >> RNGC_TYPE_SHIFT;
+	/*
+	 * This driver supports only RNGC and RNGB. (There's a different
+	 * driver for RNGA.)
+	 */
+	if (rng_type != RNGC_TYPE_RNGC && rng_type != RNGC_TYPE_RNGB) {
+		ret = -ENODEV;
+		goto err;
+	}
+
+	ret = rngc_init(rngc);
+	if (ret)
+		goto err;
+
+	return 0;
+
+err:
+	printf("%s error = %d\n", __func__, ret);
+	return ret;
+}
+
+static const struct dm_rng_ops rngc_ops = {
+	.read = rngc_read,
+};
+
+static const struct udevice_id rngc_dt_ids[] = {
+	{ .compatible = "fsl,imx25-rngb" },
+	{ }
+};
+
+U_BOOT_DRIVER(dcp_rng) = {
+	.name = "dcp_rng",
+	.id = UCLASS_RNG,
+	.of_match = rngc_dt_ids,
+	.ops = &rngc_ops,
+	.probe = rngc_probe,
+	.priv_auto  = sizeof(struct imx_rngc),
+	.flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h
index 5705c4f9447..9e81f24afca 100644
--- a/drivers/crypto/fsl/desc.h
+++ b/drivers/crypto/fsl/desc.h
@@ -15,6 +15,7 @@
 
 #define KEY_BLOB_SIZE		32
 #define MAC_SIZE			16
+#define BKEK_SIZE		32
 
 /* Max size of any CAAM descriptor in 32-bit words, inclusive of header */
 #define MAX_CAAM_DESCSIZE	64
@@ -435,6 +436,7 @@
 /* Assuming OP_TYPE = OP_TYPE_UNI_PROTOCOL */
 #define OP_PCLID_SECMEM		0x08
 #define OP_PCLID_BLOB		(0x0d << OP_PCLID_SHIFT)
+#define OP_PCL_BLOB_BLACK	0x0004
 #define OP_PCLID_SECRETKEY	(0x11 << OP_PCLID_SHIFT)
 #define OP_PCLID_PUBLICKEYPAIR	(0x14 << OP_PCLID_SHIFT)
 #define OP_PCLID_DSA_SIGN	(0x15 << OP_PCLID_SHIFT)
@@ -463,6 +465,9 @@
 #define OP_PROTINFO_HASH_SHA384	0x00000200
 #define OP_PROTINFO_HASH_SHA512	0x00000280
 
+/* PROTINFO fields for Blob Operations */
+#define OP_PROTINFO_MKVB	0x00000002
+
 /* For non-protocol/alg-only op commands */
 #define OP_ALG_TYPE_SHIFT	24
 #define OP_ALG_TYPE_MASK	(0x7 << OP_ALG_TYPE_SHIFT)
@@ -492,6 +497,9 @@
 #define OP_ALG_AAI_SHIFT	4
 #define OP_ALG_AAI_MASK		(0x1ff << OP_ALG_AAI_SHIFT)
 
+/* block cipher AAI set */
+#define OP_ALG_AAI_ECB		(0x20 << OP_ALG_AAI_SHIFT)
+
 /* randomizer AAI set */
 #define OP_ALG_AAI_RNG		(0x00 << OP_ALG_AAI_SHIFT)
 #define OP_ALG_AAI_RNG_NZB	(0x10 << OP_ALG_AAI_SHIFT)
diff --git a/drivers/crypto/fsl/fsl_aes.c b/drivers/crypto/fsl/fsl_aes.c
new file mode 100644
index 00000000000..d23573baff4
--- /dev/null
+++ b/drivers/crypto/fsl/fsl_aes.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2021 NXP
+ *
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <fsl_sec.h>
+#include <linux/errno.h>
+#include "jobdesc.h"
+#include "desc.h"
+#include "desc_constr.h"
+#include "jr.h"
+
+/**
+ * aesecb_decrypt() - Decrypt data using AES-256-ECB
+ * @key_mod:    - Key address
+ * @key_len:    - Key length
+ * @src:        - Source address (Encrypted key)
+ * @dst:        - Destination address (decrypted key in black)
+ * @len:        - Size of data to be decrypted
+ *
+ * Note: Start and end of the key, src and dst buffers have to be aligned to
+ * the cache line size (ARCH_DMA_MINALIGN) for the CAAM operation to succeed.
+ *
+ * Returns zero on success, negative on error.
+ */
+int aesecb_decrypt(u8 *key, u32 key_len, u8 *src, u8 *dst, u32 len)
+{
+	int ret, size, i = 0;
+	u32 *desc;
+	u8 len_desc;
+
+	if (!IS_ALIGNED((uintptr_t)key, ARCH_DMA_MINALIGN) ||
+	    !IS_ALIGNED((uintptr_t)src, ARCH_DMA_MINALIGN) ||
+	    !IS_ALIGNED((uintptr_t)dst, ARCH_DMA_MINALIGN)) {
+		printf("%s: Address arguments are not aligned!\n", __func__);
+		return -EINVAL;
+	}
+
+	debug("\nAES ECB decryption Operation\n");
+	desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
+	if (!desc) {
+		debug("Not enough memory for descriptor allocation\n");
+		return -ENOMEM;
+	}
+
+	size = ALIGN(key_len, ARCH_DMA_MINALIGN);
+	flush_dcache_range((unsigned long)key, (unsigned long)key + size);
+	size = ALIGN(len, ARCH_DMA_MINALIGN);
+	flush_dcache_range((unsigned long)src, (unsigned long)src + size);
+
+	inline_cnstr_jobdesc_aes_ecb_decrypt(desc, key, key_len, src, dst, len);
+
+	debug("Descriptor dump:\n");
+	len_desc = desc_len(desc);
+	for (i = 0; i < len_desc; i++)
+		debug("Word[%d]: %08x\n", i, *(desc + i));
+
+	size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN);
+	flush_dcache_range((unsigned long)desc, (unsigned long)desc + size);
+	size = ALIGN(len, ARCH_DMA_MINALIGN);
+	invalidate_dcache_range((unsigned long)dst, (unsigned long)dst + size);
+
+	ret = run_descriptor_jr(desc);
+
+	if (ret) {
+		printf("%s: error: %d\n", __func__, ret);
+	} else {
+		invalidate_dcache_range((unsigned long)dst, (unsigned long)dst + size);
+		debug("%s: success.\n", __func__);
+	}
+
+	free(desc);
+	return ret;
+}
diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c
index e8202cc5697..1391b3ffbfe 100644
--- a/drivers/crypto/fsl/fsl_blob.c
+++ b/drivers/crypto/fsl/fsl_blob.c
@@ -22,13 +22,15 @@
  * @src:        - Source address (blob)
  * @dst:        - Destination address (data)
  * @len:        - Size of decapsulated data
+ * @keycolor    - Determines if the source data is covered (black key) or
+ *                plaintext.
  *
  * Note: Start and end of the key_mod, src and dst buffers have to be aligned to
  * the cache line size (ARCH_DMA_MINALIGN) for the CAAM operation to succeed.
  *
  * Returns zero on success, negative on error.
  */
-int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
+int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len, u8 keycolor)
 {
 	int ret, size, i = 0;
 	u32 *desc;
@@ -40,7 +42,7 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
 		return -EINVAL;
 	}
 
-	printf("\nDecapsulating blob to get data\n");
+	debug("\nDecapsulating blob to get data\n");
 	desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
 	if (!desc) {
 		debug("Not enough memory for descriptor allocation\n");
@@ -55,7 +57,7 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
 	flush_dcache_range((unsigned long)src,
 			   (unsigned long)src + size);
 
-	inline_cnstr_jobdesc_blob_decap(desc, key_mod, src, dst, len);
+	inline_cnstr_jobdesc_blob_decap(desc, key_mod, src, dst, len, keycolor);
 
 	debug("Descriptor dump:\n");
 	for (i = 0; i < 14; i++)
@@ -65,19 +67,24 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
 	flush_dcache_range((unsigned long)desc,
 			   (unsigned long)desc + size);
 
-	flush_dcache_range((unsigned long)dst,
-			   (unsigned long)dst + size);
+	size = ALIGN(len, ARCH_DMA_MINALIGN);
+	invalidate_dcache_range((unsigned long)dst,
+				(unsigned long)dst + size);
 
 	ret = run_descriptor_jr(desc);
 
 	if (ret) {
+		/* clear the blob data output buffer */
+		memset(dst, 0x00, len);
+		size = ALIGN(len, ARCH_DMA_MINALIGN);
+		flush_dcache_range((unsigned long)dst, (unsigned long)dst + size);
 		printf("Error in blob decapsulation: %d\n", ret);
 	} else {
 		size = ALIGN(len, ARCH_DMA_MINALIGN);
 		invalidate_dcache_range((unsigned long)dst,
 					(unsigned long)dst + size);
 
-		puts("Blob decapsulation successful.\n");
+		debug("Blob decapsulation successful.\n");
 	}
 
 	free(desc);
@@ -90,13 +97,15 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
  * @src:        - Source address (data)
  * @dst:        - Destination address (blob)
  * @len:        - Size of data to be encapsulated
+ * @keycolor    - Determines if the source data is covered (black key) or
+ *                plaintext.
  *
  * Note: Start and end of the key_mod, src and dst buffers have to be aligned to
  * the cache line size (ARCH_DMA_MINALIGN) for the CAAM operation to succeed.
  *
  * Returns zero on success, negative on error.
  */
-int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
+int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len, u8 keycolor)
 {
 	int ret, size, i = 0;
 	u32 *desc;
@@ -108,7 +117,7 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
 		return -EINVAL;
 	}
 
-	printf("\nEncapsulating data to form blob\n");
+	debug("\nEncapsulating data to form blob\n");
 	desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
 	if (!desc) {
 		debug("Not enough memory for descriptor allocation\n");
@@ -123,7 +132,7 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
 	flush_dcache_range((unsigned long)src,
 			   (unsigned long)src + size);
 
-	inline_cnstr_jobdesc_blob_encap(desc, key_mod, src, dst, len);
+	inline_cnstr_jobdesc_blob_encap(desc, key_mod, src, dst, len, keycolor);
 
 	debug("Descriptor dump:\n");
 	for (i = 0; i < 14; i++)
@@ -133,8 +142,9 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
 	flush_dcache_range((unsigned long)desc,
 			   (unsigned long)desc + size);
 
-	flush_dcache_range((unsigned long)dst,
-			   (unsigned long)dst + size);
+	size = ALIGN(BLOB_SIZE(len), ARCH_DMA_MINALIGN);
+	invalidate_dcache_range((unsigned long)dst,
+				(unsigned long)dst + size);
 
 	ret = run_descriptor_jr(desc);
 
@@ -145,7 +155,88 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
 		invalidate_dcache_range((unsigned long)dst,
 					(unsigned long)dst + size);
 
-		puts("Blob encapsulation successful.\n");
+		debug("Blob encapsulation successful.\n");
+	}
+
+	free(desc);
+	return ret;
+}
+
+int derive_blob_kek(u8 *bkek_buf, u8 *key_mod, u32 key_sz)
+{
+	int ret, size;
+	u32 *desc;
+
+	if (!IS_ALIGNED((uintptr_t)bkek_buf, ARCH_DMA_MINALIGN) ||
+	    !IS_ALIGNED((uintptr_t)key_mod, ARCH_DMA_MINALIGN)) {
+		puts("Error: derive_bkek: Address arguments are not aligned!\n");
+		return -EINVAL;
+	}
+
+	debug("\nBlob key encryption key(bkek)\n");
+	desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
+	if (!desc) {
+		printf("Not enough memory for descriptor allocation\n");
+		return -ENOMEM;
+	}
+
+	size = ALIGN(key_sz, ARCH_DMA_MINALIGN);
+	flush_dcache_range((unsigned long)key_mod, (unsigned long)key_mod + size);
+
+	/* construct blob key encryption key(bkek) derive descriptor */
+	inline_cnstr_jobdesc_derive_bkek(desc, bkek_buf, key_mod, key_sz);
+
+	size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN);
+	flush_dcache_range((unsigned long)desc, (unsigned long)desc + size);
+	size = ALIGN(BKEK_SIZE, ARCH_DMA_MINALIGN);
+	flush_dcache_range((unsigned long)bkek_buf,
+			   (unsigned long)bkek_buf + size);
+
+	/* run descriptor */
+	ret = run_descriptor_jr(desc);
+	if (ret < 0) {
+		printf("Error: derive_blob_kek failed 0x%x\n", ret);
+	} else {
+		invalidate_dcache_range((unsigned long)bkek_buf,
+					(unsigned long)bkek_buf + size);
+		debug("derive bkek successful.\n");
+	}
+
+	free(desc);
+	return ret;
+}
+
+int hwrng_generate(u8 *dst, u32 len)
+{
+	int ret, size;
+	u32 *desc;
+
+	if (!IS_ALIGNED((uintptr_t)dst, ARCH_DMA_MINALIGN)) {
+		puts("Error: caam_hwrng: Address arguments are not aligned!\n");
+		return -EINVAL;
+	}
+
+	debug("\nRNG generate\n");
+	desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
+	if (!desc) {
+		printf("Not enough memory for descriptor allocation\n");
+		return -ENOMEM;
+	}
+
+	inline_cnstr_jobdesc_rng(desc, dst ,len);
+
+	size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN);
+	flush_dcache_range((unsigned long)desc, (unsigned long)desc + size);
+	size = ALIGN(len, ARCH_DMA_MINALIGN);
+	flush_dcache_range((unsigned long)dst, (unsigned long)dst + size);
+
+	ret = run_descriptor_jr(desc);
+	if (ret < 0) {
+		printf("Error: RNG generate failed 0x%x\n", ret);
+	} else {
+		invalidate_dcache_range((unsigned long)dst,
+					(unsigned long)dst + size);
+		debug("RNG generation successful.\n");
 	}
 
 	free(desc);
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
index 2379b70c2da..66249f27074 100644
--- a/drivers/crypto/fsl/fsl_hash.c
+++ b/drivers/crypto/fsl/fsl_hash.c
@@ -131,30 +131,48 @@ static int caam_hash_update(void *hash_ctx, const void *buf,
 static int caam_hash_finish(void *hash_ctx, void *dest_buf,
 			    int size, enum caam_hash_algos caam_algo)
 {
-	uint32_t len = 0;
+	uint32_t len = 0, sg_entry_len;
 	struct sha_ctx *ctx = hash_ctx;
 	int i = 0, ret = 0;
+	ulong addr;
 
 	if (size < driver_hash[caam_algo].digestsize) {
 		return -EINVAL;
 	}
 
-	for (i = 0; i < ctx->sg_num; i++)
-		len += (sec_in32(&ctx->sg_tbl[i].len_flag) &
-			SG_ENTRY_LENGTH_MASK);
-
+	flush_dcache_range((ulong)ctx->sg_tbl,
+			   (ulong)(ctx->sg_tbl) + (ctx->sg_num * sizeof(struct sg_entry)));
+	for (i = 0; i < ctx->sg_num; i++) {
+		sg_entry_len = (sec_in32(&ctx->sg_tbl[i].len_flag) &
+				SG_ENTRY_LENGTH_MASK);
+		len += sg_entry_len;
+#ifdef CONFIG_CAAM_64BIT
+		addr = sec_in32(&ctx->sg_tbl[i].addr_hi);
+		addr = (addr << 32) | sec_in32(&ctx->sg_tbl[i].addr_lo);
+#else
+		addr = sec_in32(&ctx->sg_tbl[i].addr_lo);
+#endif
+		flush_dcache_range(addr, addr + sg_entry_len);
+	}
 	inline_cnstr_jobdesc_hash(ctx->sha_desc, (uint8_t *)ctx->sg_tbl, len,
 				  ctx->hash,
 				  driver_hash[caam_algo].alg_type,
 				  driver_hash[caam_algo].digestsize,
 				  1);
 
+	flush_dcache_range((ulong)ctx->sha_desc,
+			   (ulong)(ctx->sha_desc) + (sizeof(uint32_t) * MAX_CAAM_DESCSIZE));
+	flush_dcache_range((ulong)ctx->hash,
+			   (ulong)(ctx->hash) + driver_hash[caam_algo].digestsize);
+
 	ret = run_descriptor_jr(ctx->sha_desc);
 
 	if (ret) {
 		debug("Error %x\n", ret);
 		return ret;
 	} else {
+		invalidate_dcache_range((ulong)ctx->hash,
+					(ulong)(ctx->hash) + driver_hash[caam_algo].digestsize);
 		memcpy(dest_buf, ctx->hash, sizeof(ctx->hash));
 	}
 	free(ctx);
@@ -168,18 +186,19 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len,
 	uint32_t *desc;
 	unsigned int size;
 
-	desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
-	if (!desc) {
-		debug("Not enough memory for descriptor allocation\n");
-		return -ENOMEM;
-	}
-
 	if (!IS_ALIGNED((uintptr_t)pbuf, ARCH_DMA_MINALIGN) ||
 	    !IS_ALIGNED((uintptr_t)pout, ARCH_DMA_MINALIGN)) {
 		puts("Error: Address arguments are not aligned\n");
 		return -EINVAL;
 	}
 
+	debug("\ncaam hash\n");
+	desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE);
+	if (!desc) {
+		debug("Not enough memory for descriptor allocation\n");
+		return -ENOMEM;
+	}
+
 	size = ALIGN(buf_len, ARCH_DMA_MINALIGN);
 	flush_dcache_range((unsigned long)pbuf, (unsigned long)pbuf + size);
 
@@ -190,6 +209,8 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len,
 
 	size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN);
 	flush_dcache_range((unsigned long)desc, (unsigned long)desc + size);
+	size = ALIGN(driver_hash[algo].digestsize, ARCH_DMA_MINALIGN);
+	invalidate_dcache_range((unsigned long)pout, (unsigned long)pout + size);
 
 	ret = run_descriptor_jr(desc);
 
diff --git a/drivers/crypto/fsl/fsl_mfgprot.c b/drivers/crypto/fsl/fsl_mfgprot.c
index 29af79f577d..a9b40e84a67 100644
--- a/drivers/crypto/fsl/fsl_mfgprot.c
+++ b/drivers/crypto/fsl/fsl_mfgprot.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <cpu_func.h>
 #include <errno.h>
 #include <fsl_sec.h>
 #include <memalign.h>
@@ -93,7 +94,7 @@ int gen_mppubk(u8 *dst)
 	flush_dcache_range((unsigned long)dst, (unsigned long)dst + size);
 
 	/* Execute Job Descriptor */
-	puts("\nGenerating Manufacturing Protection Public Key\n");
+	debug("\nGenerating Manufacturing Protection Public Key\n");
 
 	ret = run_descriptor_jr(dsc);
 	if (ret) {
diff --git a/drivers/crypto/fsl/fsl_rsa.c b/drivers/crypto/fsl/fsl_rsa.c
index 897ee855ead..cfe6332e88b 100644
--- a/drivers/crypto/fsl/fsl_rsa.c
+++ b/drivers/crypto/fsl/fsl_rsa.c
@@ -6,6 +6,7 @@
 
 #include <config.h>
 #include <common.h>
+#include <cpu_func.h>
 #include <dm.h>
 #include <log.h>
 #include <asm/types.h>
@@ -36,12 +37,20 @@ int fsl_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t sig_len,
 
 	inline_cnstr_jobdesc_pkha_rsaexp(desc, &pkin, out, sig_len);
 
+	flush_dcache_range((ulong)sig, (ulong)sig + sig_len);
+	flush_dcache_range((ulong)prop->modulus, (ulong)(prop->modulus) + keylen);
+	flush_dcache_range((ulong)prop->public_exponent, (ulong)(prop->public_exponent) + prop->exp_len);
+	flush_dcache_range((ulong)desc, (ulong)desc + (sizeof(uint32_t) * MAX_CAAM_DESCSIZE));
+	flush_dcache_range((ulong)out, (ulong)out + sig_len);
+
 	ret = run_descriptor_jr(desc);
 	if (ret) {
 		debug("%s: RSA failed to verify: %d\n", __func__, ret);
 		return -EFAULT;
 	}
 
+	invalidate_dcache_range((ulong)out, (ulong)out + sig_len);
+
 	return 0;
 }
 
diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c
index 542b1652d80..c6cd065b1b3 100644
--- a/drivers/crypto/fsl/jobdesc.c
+++ b/drivers/crypto/fsl/jobdesc.c
@@ -4,7 +4,7 @@
  * Basic job descriptor construction
  *
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  *
  */
 
@@ -207,16 +207,17 @@ void inline_cnstr_jobdesc_hash(uint32_t *desc,
 	append_store(desc, dma_addr_out, storelen,
 		     LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_CONTEXT);
 }
-#ifndef CONFIG_SPL_BUILD
+
 void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr,
 				     uint8_t *plain_txt, uint8_t *enc_blob,
-				     uint32_t in_sz)
+				     uint32_t in_sz, uint8_t keycolor)
 {
 	caam_dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out;
 	uint32_t key_sz = KEY_IDNFR_SZ_BYTES;
 	/* output blob will have 32 bytes key blob in beginning and
 	 * 16 byte HMAC identifier at end of data blob */
 	uint32_t out_sz = in_sz + KEY_BLOB_SIZE + MAC_SIZE;
+	uint32_t bk_store;
 
 	dma_addr_key_idnfr = virt_to_phys((void *)key_idnfr);
 	dma_addr_in	= virt_to_phys((void *)plain_txt);
@@ -230,16 +231,23 @@ void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr,
 
 	append_seq_out_ptr(desc, dma_addr_out, out_sz, 0);
 
-	append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB);
+	bk_store = OP_PCLID_BLOB;
+
+	/* An input black key cannot be stored in a red blob */
+	if (keycolor == BLACK_KEY)
+		bk_store |= OP_PCL_BLOB_BLACK;
+
+	append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | bk_store);
 }
 
 void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr,
 				     uint8_t *enc_blob, uint8_t *plain_txt,
-				     uint32_t out_sz)
+				     uint32_t out_sz, uint8_t keycolor)
 {
 	caam_dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out;
 	uint32_t key_sz = KEY_IDNFR_SZ_BYTES;
 	uint32_t in_sz = out_sz + KEY_BLOB_SIZE + MAC_SIZE;
+	uint32_t bk_store;
 
 	dma_addr_key_idnfr = virt_to_phys((void *)key_idnfr);
 	dma_addr_in	= virt_to_phys((void *)enc_blob);
@@ -253,9 +261,15 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr,
 
 	append_seq_out_ptr(desc, dma_addr_out, out_sz, 0);
 
-	append_operation(desc, OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB);
+	bk_store = OP_PCLID_BLOB;
+
+	/* An input black key cannot be stored in a red blob */
+	if (keycolor == BLACK_KEY)
+		bk_store |= OP_PCL_BLOB_BLACK;
+
+	append_operation(desc, OP_TYPE_DECAP_PROTOCOL | bk_store);
 }
-#endif
+
 /*
  * Descriptor to instantiate RNG State Handle 0 in normal mode and
  * load the JDKEK, TDKEK and TDSK registers
@@ -334,3 +348,45 @@ void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc,
 	append_fifo_store(desc, dma_addr_out, out_siz,
 			  LDST_CLASS_1_CCB | FIFOST_TYPE_PKHA_B);
 }
+
+void inline_cnstr_jobdesc_derive_bkek(uint32_t *desc, void *bkek_out, void *key_mod, uint32_t key_sz)
+{
+	dma_addr_t dma_key_mod = virt_to_phys(key_mod);
+	dma_addr_t dma_bkek_out = virt_to_phys(bkek_out);
+
+	init_job_desc(desc, 0);
+	append_load(desc, dma_key_mod, key_sz,	LDST_CLASS_2_CCB |
+						LDST_SRCDST_BYTE_KEY);
+	append_seq_out_ptr_intlen(desc, dma_bkek_out, BKEK_SIZE, 0);
+	append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB |
+							OP_PROTINFO_MKVB);
+}
+
+void inline_cnstr_jobdesc_aes_ecb_decrypt(uint32_t *desc, uint8_t *key, uint32_t key_len,
+					  uint8_t *src, uint8_t *dst, uint32_t len)
+{
+	caam_dma_addr_t dma_addr_key, dma_addr_src, dma_addr_dst;
+
+	dma_addr_key = virt_to_phys(key);
+	dma_addr_src = virt_to_phys(src);
+	dma_addr_dst = virt_to_phys(dst);
+
+	init_job_desc(desc, 0);
+
+	/* Key command: Load key in class 1 key register. */
+	append_key(desc, dma_addr_key, key_len, CLASS_1 | KEY_DEST_CLASS_REG);
+
+	/* AES ECB Decrypt Operation command. */
+	append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_AES | OP_ALG_AAI_ECB
+				| OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT);
+
+	/* Fifoload command: load input data. */
+	append_fifo_load(desc, dma_addr_src, len, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_MSG
+						| FIFOLD_TYPE_LAST1);
+
+	/* Fifostore command: store decrypted key in black. */
+	append_jump(desc, JUMP_CLASS_CLASS1 | 1);
+	append_move(desc, MOVE_SRC_OUTFIFO | MOVE_DEST_CLASS2KEY | MOVE_WAITCOMP | len);
+	append_load_imm_u32(desc, len, CLASS_2 | LDST_SRCDST_WORD_KEYSZ_REG | LDST_IMM);
+	append_fifo_store(desc, dma_addr_dst, len, CLASS_2 | FIFOST_TYPE_KEY_KEK);
+}
diff --git a/drivers/crypto/fsl/jobdesc.h b/drivers/crypto/fsl/jobdesc.h
index c4501abd26b..3395b4b75e4 100644
--- a/drivers/crypto/fsl/jobdesc.h
+++ b/drivers/crypto/fsl/jobdesc.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  *
  */
 
@@ -13,6 +14,9 @@
 
 #define KEY_IDNFR_SZ_BYTES		16
 
+/* Encrypted key */
+#define BLACK_KEY	1
+
 #ifdef CONFIG_CMD_DEKBLOB
 /* inline_cnstr_jobdesc_blob_dek:
  * Intializes and constructs the job descriptor for DEK encapsulation
@@ -33,11 +37,11 @@ void inline_cnstr_jobdesc_hash(uint32_t *desc,
 
 void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr,
 				     uint8_t *plain_txt, uint8_t *enc_blob,
-				     uint32_t in_sz);
+				     uint32_t in_sz, uint8_t keycolor);
 
 void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr,
 				     uint8_t *enc_blob, uint8_t *plain_txt,
-				     uint32_t out_sz);
+				     uint32_t out_sz, uint8_t keycolor);
 
 void inline_cnstr_jobdesc_rng_instantiation(u32 *desc, int handle, int do_sk);
 
@@ -49,4 +53,10 @@ void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc,
 				      struct pk_in_params *pkin, uint8_t *out,
 				      uint32_t out_siz);
 
+void inline_cnstr_jobdesc_derive_bkek(uint32_t *desc, void *bkek_out,
+				      void *key_mod, uint32_t key_sz);
+
+void inline_cnstr_jobdesc_aes_ecb_decrypt(uint32_t *desc, uint8_t *key,
+					  uint32_t key_len, uint8_t *src,
+					  uint8_t *dst, uint32_t len);
 #endif
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 22b649219e8..31a6002252d 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2008-2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  *
  * Based on CAAM driver in drivers/crypto/caam in Linux
  */
@@ -11,7 +11,7 @@
 #include <linux/kernel.h>
 #include <log.h>
 #include <malloc.h>
-#include "fsl_sec.h"
+#include <power-domain.h>
 #include "jr.h"
 #include "jobdesc.h"
 #include "desc_constr.h"
@@ -21,7 +21,10 @@
 #include <asm/cache.h>
 #include <asm/fsl_pamu.h>
 #endif
+#include <dm.h>
 #include <dm/lists.h>
+#include <dm/root.h>
+#include <dm/device-internal.h>
 #include <linux/delay.h>
 
 #define CIRC_CNT(head, tail, size)	(((head) - (tail)) & (size - 1))
@@ -35,20 +38,37 @@ uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
 #endif
 };
 
+#if CONFIG_IS_ENABLED(DM)
+struct udevice *caam_dev;
+#else
 #define SEC_ADDR(idx)	\
 	(ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
 
-#define SEC_JR0_ADDR(idx)	\
+#ifndef CONFIG_IMX8M
+#define SEC_JR_ADDR(idx)	\
 	(ulong)(SEC_ADDR(idx) +	\
 	 (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+#define JR_ID 0
+#else
+#define SEC_JR_ADDR(idx)	\
+	(ulong)(SEC_ADDR(idx) + \
+	 (CONFIG_SYS_FSL_JR1_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+#define JR_ID 1
+#endif
+struct caam_regs caam_st;
+#endif
 
-struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
+static inline u32 jr_start_reg(u8 jrid)
+{
+	return (1 << jrid);
+}
 
-static inline void start_jr0(uint8_t sec_idx)
+static inline void start_jr(struct caam_regs *caam)
 {
-	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
+	ccsr_sec_t *sec = caam->sec;
 	u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
 	u32 scfgr = sec_in32(&sec->scfgr);
+	u32 jrstart = jr_start_reg(caam->jrid);
 
 	if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
 		/* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
@@ -56,23 +76,16 @@ static inline void start_jr0(uint8_t sec_idx)
 		 */
 		if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
 		    (scfgr & SEC_SCFGR_VIRT_EN))
-			sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
+			sec_out32(&sec->jrstartr, jrstart);
 	} else {
 		/* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
 		if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
-			sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
+			sec_out32(&sec->jrstartr, jrstart);
 	}
 }
 
-static inline void jr_reset_liodn(uint8_t sec_idx)
+static inline void jr_disable_irq(struct jr_regs *regs)
 {
-	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
-	sec_out32(&sec->jrliodnr[0].ls, 0);
-}
-
-static inline void jr_disable_irq(uint8_t sec_idx)
-{
-	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
 	uint32_t jrcfg = sec_in32(&regs->jrcfg1);
 
 	jrcfg = jrcfg | JR_INTMASK;
@@ -80,10 +93,10 @@ static inline void jr_disable_irq(uint8_t sec_idx)
 	sec_out32(&regs->jrcfg1, jrcfg);
 }
 
-static void jr_initregs(uint8_t sec_idx)
+static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam)
 {
-	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
-	struct jobring *jr = &jr0[sec_idx];
+	struct jr_regs *regs = caam->regs;
+	struct jobring *jr = &caam->jr[sec_idx];
 	caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
 	caam_dma_addr_t op_base = virt_to_phys((void *)jr->output_ring);
 
@@ -103,16 +116,18 @@ static void jr_initregs(uint8_t sec_idx)
 	sec_out32(&regs->irs, JR_SIZE);
 
 	if (!jr->irq)
-		jr_disable_irq(sec_idx);
+		jr_disable_irq(regs);
 }
 
-static int jr_init(uint8_t sec_idx)
+static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
 {
-	struct jobring *jr = &jr0[sec_idx];
-
+	struct jobring *jr = &caam->jr[sec_idx];
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+	ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
+#endif
 	memset(jr, 0, sizeof(struct jobring));
 
-	jr->jq_id = DEFAULT_JR_ID;
+	jr->jq_id = caam->jrid;
 	jr->irq = DEFAULT_IRQ;
 
 #ifdef CONFIG_FSL_CORENET
@@ -134,53 +149,12 @@ static int jr_init(uint8_t sec_idx)
 	memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
 	memset(jr->output_ring, 0, jr->op_size);
 
-	start_jr0(sec_idx);
-
-	jr_initregs(sec_idx);
-
-	return 0;
-}
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+	if (!ofnode_valid(scu_node))
+#endif
+	start_jr(caam);
 
-static int jr_sw_cleanup(uint8_t sec_idx)
-{
-	struct jobring *jr = &jr0[sec_idx];
-
-	jr->head = 0;
-	jr->tail = 0;
-	jr->read_idx = 0;
-	jr->write_idx = 0;
-	memset(jr->info, 0, sizeof(jr->info));
-	memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
-	memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
-
-	return 0;
-}
-
-static int jr_hw_reset(uint8_t sec_idx)
-{
-	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
-	uint32_t timeout = 100000;
-	uint32_t jrint, jrcr;
-
-	sec_out32(&regs->jrcr, JRCR_RESET);
-	do {
-		jrint = sec_in32(&regs->jrint);
-	} while (((jrint & JRINT_ERR_HALT_MASK) ==
-		  JRINT_ERR_HALT_INPROGRESS) && --timeout);
-
-	jrint = sec_in32(&regs->jrint);
-	if (((jrint & JRINT_ERR_HALT_MASK) !=
-	     JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
-		return -1;
-
-	timeout = 100000;
-	sec_out32(&regs->jrcr, JRCR_RESET);
-	do {
-		jrcr = sec_in32(&regs->jrcr);
-	} while ((jrcr & JRCR_RESET) && --timeout);
-
-	if (timeout == 0)
-		return -1;
+	jr_initregs(sec_idx, caam);
 
 	return 0;
 }
@@ -188,10 +162,10 @@ static int jr_hw_reset(uint8_t sec_idx)
 /* -1 --- error, can't enqueue -- no space available */
 static int jr_enqueue(uint32_t *desc_addr,
 	       void (*callback)(uint32_t status, void *arg),
-	       void *arg, uint8_t sec_idx)
+	       void *arg, uint8_t sec_idx, struct caam_regs *caam)
 {
-	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
-	struct jobring *jr = &jr0[sec_idx];
+	struct jr_regs *regs = caam->regs;
+	struct jobring *jr = &caam->jr[sec_idx];
 	int head = jr->head;
 	uint32_t desc_word;
 	int length = desc_len(desc_addr);
@@ -263,10 +237,10 @@ static int jr_enqueue(uint32_t *desc_addr,
 	return 0;
 }
 
-static int jr_dequeue(int sec_idx)
+static int jr_dequeue(int sec_idx, struct caam_regs *caam)
 {
-	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
-	struct jobring *jr = &jr0[sec_idx];
+	struct jr_regs *regs = caam->regs;
+	struct jobring *jr = &caam->jr[sec_idx];
 	int head = jr->head;
 	int tail = jr->tail;
 	int idx, i, found;
@@ -349,14 +323,18 @@ static void desc_done(uint32_t status, void *arg)
 {
 	struct result *x = arg;
 	x->status = status;
-#ifndef CONFIG_SPL_BUILD
 	caam_jr_strstatus(status);
-#endif
 	x->done = 1;
 }
 
 static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
 {
+	struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+	caam = dev_get_priv(caam_dev);
+#else
+	caam = &caam_st;
+#endif
 	unsigned long long timeval = 0;
 	unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT;
 	struct result op;
@@ -364,7 +342,7 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
 
 	memset(&op, 0, sizeof(op));
 
-	ret = jr_enqueue(desc, desc_done, &op, sec_idx);
+	ret = jr_enqueue(desc, desc_done, &op, sec_idx, caam);
 	if (ret) {
 		debug("Error in SEC enq\n");
 		ret = JQ_ENQ_ERR;
@@ -375,7 +353,7 @@ static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
 		udelay(1);
 		timeval += 1;
 
-		ret = jr_dequeue(sec_idx);
+		ret = jr_dequeue(sec_idx, caam);
 		if (ret) {
 			debug("Error in SEC deq\n");
 			ret = JQ_DEQ_ERR;
@@ -402,13 +380,62 @@ int run_descriptor_jr(uint32_t *desc)
 	return run_descriptor_jr_idx(desc, 0);
 }
 
+static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam)
+{
+	struct jobring *jr = &caam->jr[sec_idx];
+
+	jr->head = 0;
+	jr->tail = 0;
+	jr->read_idx = 0;
+	jr->write_idx = 0;
+	memset(jr->info, 0, sizeof(jr->info));
+	memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
+	memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
+
+	return 0;
+}
+
+static int jr_hw_reset(struct jr_regs *regs)
+{
+	uint32_t timeout = 100000;
+	uint32_t jrint, jrcr;
+
+	sec_out32(&regs->jrcr, JRCR_RESET);
+	do {
+		jrint = sec_in32(&regs->jrint);
+	} while (((jrint & JRINT_ERR_HALT_MASK) ==
+		  JRINT_ERR_HALT_INPROGRESS) && --timeout);
+
+	jrint = sec_in32(&regs->jrint);
+	if (((jrint & JRINT_ERR_HALT_MASK) !=
+	     JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
+		return -1;
+
+	timeout = 100000;
+	sec_out32(&regs->jrcr, JRCR_RESET);
+	do {
+		jrcr = sec_in32(&regs->jrcr);
+	} while ((jrcr & JRCR_RESET) && --timeout);
+
+	if (timeout == 0)
+		return -1;
+
+	return 0;
+}
+
 static inline int jr_reset_sec(uint8_t sec_idx)
 {
-	if (jr_hw_reset(sec_idx) < 0)
+	struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+	caam = dev_get_priv(caam_dev);
+#else
+	caam = &caam_st;
+#endif
+	if (jr_hw_reset(caam->regs) < 0)
 		return -1;
 
 	/* Clean up the jobring structure maintained by software */
-	jr_sw_cleanup(sec_idx);
+	jr_sw_cleanup(sec_idx, caam);
 
 	return 0;
 }
@@ -418,9 +445,15 @@ int jr_reset(void)
 	return jr_reset_sec(0);
 }
 
-static inline int sec_reset_idx(uint8_t sec_idx)
+int sec_reset(void)
 {
-	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
+	struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+	caam = dev_get_priv(caam_dev);
+#else
+	caam = &caam_st;
+#endif
+	ccsr_sec_t *sec = caam->sec;
 	uint32_t mcfgr = sec_in32(&sec->mcfgr);
 	uint32_t timeout = 100000;
 
@@ -446,11 +479,7 @@ static inline int sec_reset_idx(uint8_t sec_idx)
 
 	return 0;
 }
-int sec_reset(void)
-{
-	return sec_reset_idx(0);
-}
-#ifndef CONFIG_SPL_BUILD
+
 static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
 {
 	u32 *desc;
@@ -496,12 +525,11 @@ static int deinstantiate_rng(u8 sec_idx, int state_handle_mask)
 	return ret;
 }
 
-static int instantiate_rng(u8 sec_idx, int gen_sk)
+static int instantiate_rng(uint8_t sec_idx, ccsr_sec_t *sec, int gen_sk)
 {
 	u32 *desc;
 	u32 rdsta_val;
 	int ret = 0, sh_idx, size;
-	ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
 	struct rng4tst __iomem *rng =
 			(struct rng4tst __iomem *)&sec->rng;
 
@@ -554,9 +582,8 @@ static int instantiate_rng(u8 sec_idx, int gen_sk)
 	return ret;
 }
 
-static u8 get_rng_vid(uint8_t sec_idx)
+static u8 get_rng_vid(ccsr_sec_t *sec)
 {
-	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
 	u8 vid;
 
 	if (caam_get_era() < 10) {
@@ -570,13 +597,121 @@ static u8 get_rng_vid(uint8_t sec_idx)
 	return vid;
 }
 
+#if defined(CONFIG_ARCH_IMX8M) || defined(CONFIG_ARCH_MX7ULP) || \
+	defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) || defined(CONFIG_ARCH_IMX8ULP)
+
+static void kick_trng(u32 ent_delay, ccsr_sec_t *sec)
+{
+	u32 samples  = 512; /* number of bits to generate and test */
+	u32 mono_min = 195;
+	u32 mono_max = 317;
+	u32 mono_range  = mono_max - mono_min;
+	u32 poker_min = 1031;
+	u32 poker_max = 1600;
+	u32 poker_range = poker_max - poker_min + 1;
+	u32 retries    = 2;
+	u32 lrun_max   = 32;
+	s32 run_1_min   = 27;
+	s32 run_1_max   = 107;
+	s32 run_1_range = run_1_max - run_1_min;
+	s32 run_2_min   = 7;
+	s32 run_2_max   = 62;
+	s32 run_2_range = run_2_max - run_2_min;
+	s32 run_3_min   = 0;
+	s32 run_3_max   = 39;
+	s32 run_3_range = run_3_max - run_3_min;
+	s32 run_4_min   = -1;
+	s32 run_4_max   = 26;
+	s32 run_4_range = run_4_max - run_4_min;
+	s32 run_5_min   = -1;
+	s32 run_5_max   = 18;
+	s32 run_5_range = run_5_max - run_5_min;
+	s32 run_6_min   = -1;
+	s32 run_6_max   = 17;
+	s32 run_6_range = run_6_max - run_6_min;
+	u32 val;
+
+	struct rng4tst __iomem *rng =
+			(struct rng4tst __iomem *)&sec->rng;
+
+	/* Put RNG in program mode */
+	/* Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to
+	 * properly invalidate the entropy in the entropy register and
+	 * force re-generation.
+	 */
+	sec_setbits32(&rng->rtmctl, RTMCTL_PRGM | RTMCTL_ACC);
+
+	/* Configure the RNG Entropy Delay
+	 * Performance-wise, it does not make sense to
+	 * set the delay to a value that is lower
+	 * than the last one that worked (i.e. the state handles
+	 * were instantiated properly. Thus, instead of wasting
+	 * time trying to set the values controlling the sample
+	 * frequency, the function simply returns.
+	 */
+	val = sec_in32(&rng->rtsdctl);
+	val &= RTSDCTL_ENT_DLY_MASK;
+	val >>= RTSDCTL_ENT_DLY_SHIFT;
+	if (ent_delay < val) {
+		/* Put RNG4 into run mode */
+		sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM | RTMCTL_ACC);
+		return;
+	}
+
+	val = (ent_delay << RTSDCTL_ENT_DLY_SHIFT) | samples;
+	sec_out32(&rng->rtsdctl, val);
+
+	/*
+	 * Recommended margins (min,max) for freq. count:
+	 *   freq_mul = RO_freq / TRNG_clk_freq
+	 *   rtfrqmin = (ent_delay x freq_mul) >> 1;
+	 *   rtfrqmax = (ent_delay x freq_mul) << 3;
+	 * Given current deployments of CAAM in i.MX SoCs, and to simplify
+	 * the configuration, we consider [1,16] to be a safe interval
+	 * for the freq_mul and the limits of the interval are used to compute
+	 * rtfrqmin, rtfrqmax
+	 */
+	sec_out32(&rng->rtfreqmin, ent_delay >> 1);
+	sec_out32(&rng->rtfreqmax, ent_delay << 7);
+
+	sec_out32(&rng->rtscmisc, (retries << 16) | lrun_max);
+	sec_out32(&rng->rtpkrmax, poker_max);
+	sec_out32(&rng->rtpkrrng, poker_range);
+	sec_out32(&rng->rsvd1[0], (mono_range << 16) | mono_max);
+	sec_out32(&rng->rsvd1[1], (run_1_range << 16) | run_1_max);
+	sec_out32(&rng->rsvd1[2], (run_2_range << 16) | run_2_max);
+	sec_out32(&rng->rsvd1[3], (run_3_range << 16) | run_3_max);
+	sec_out32(&rng->rsvd1[4], (run_4_range << 16) | run_4_max);
+	sec_out32(&rng->rsvd1[5], (run_5_range << 16) | run_5_max);
+	sec_out32(&rng->rsvd1[6], (run_6_range << 16) | run_6_max);
+
+	val = sec_in32(&rng->rtmctl);
+	/*
+	 * Select raw sampling in both entropy shifter
+	 * and statistical checker
+	 */
+	val &= ~RTMCTL_SAMP_MODE_INVALID;
+	val |= RTMCTL_SAMP_MODE_RAW_ES_SC;
+	/* Put RNG4 into run mode */
+	val &= ~(RTMCTL_PRGM | RTMCTL_ACC);
+	/*test with sample mode only */
+	sec_out32(&rng->rtmctl, val);
+
+	/* Clear the ERR bit in RTMCTL if set. The TRNG error can occur when the
+	 * RNG clock is not within 1/2x to 8x the system clock.
+	 * This error is possible if ROM code does not initialize the system PLLs
+	 * immediately after PoR.
+	 */
+	/* setbits_le32(CAAM_RTMCTL, RTMCTL_ERR); */
+}
+
+#else
 /*
  * By default, the TRNG runs for 200 clocks per sample;
  * 1200 clocks per sample generates better entropy.
  */
-static void kick_trng(int ent_delay, uint8_t sec_idx)
+static void kick_trng(int ent_delay, ccsr_sec_t *sec)
 {
-	ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
 	struct rng4tst __iomem *rng =
 			(struct rng4tst __iomem *)&sec->rng;
 	u32 val;
@@ -602,11 +737,11 @@ static void kick_trng(int ent_delay, uint8_t sec_idx)
 	/* put RNG4 into run mode */
 	sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
 }
+#endif
 
-static int rng_init(uint8_t sec_idx)
+static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec)
 {
-	int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
-	ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
+	int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY;
 	struct rng4tst __iomem *rng =
 			(struct rng4tst __iomem *)&sec->rng;
 	u32 inst_handles;
@@ -624,7 +759,7 @@ static int rng_init(uint8_t sec_idx)
 		 * the TRNG parameters.
 		 */
 		if (!inst_handles) {
-			kick_trng(ent_delay, sec_idx);
+			kick_trng(ent_delay, sec);
 			ent_delay += 400;
 		}
 		/*
@@ -634,7 +769,16 @@ static int rng_init(uint8_t sec_idx)
 		 * interval, leading to a sucessful initialization of
 		 * the RNG.
 		 */
-		ret = instantiate_rng(sec_idx, gen_sk);
+		ret = instantiate_rng(sec_idx, sec, gen_sk);
+		/*
+		 * entropy delay is calculated via self-test method.
+		 * self-test are run across different volatge, temp.
+		 * if worst case value for ent_dly is identified,
+		 * loop can be skipped for that platform.
+		 */
+		if (IS_ENABLED(CONFIG_MX6SX))
+			break;
+
 	} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
 	if (ret) {
 		printf("SEC%u:  Failed to instantiate RNG\n", sec_idx);
@@ -646,13 +790,35 @@ static int rng_init(uint8_t sec_idx)
 
 	return ret;
 }
-#endif
+
 int sec_init_idx(uint8_t sec_idx)
 {
-	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
-	uint32_t mcr = sec_in32(&sec->mcfgr);
 	int ret = 0;
+	struct caam_regs *caam;
+#if CONFIG_IS_ENABLED(DM)
+	if (!caam_dev) {
+		printf("caam_jr: caam not found\n");
+		return -1;
+	}
+	caam = dev_get_priv(caam_dev);
+#else
+	caam_st.sec = (void *)SEC_ADDR(sec_idx);
+	caam_st.regs = (struct jr_regs *)SEC_JR_ADDR(sec_idx);
+	caam_st.jrid = JR_ID;
+	caam = &caam_st;
+#endif
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+	ofnode scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
 
+	if (ofnode_valid(scu_node))
+		goto init;
+#endif
+
+	ccsr_sec_t *sec = caam->sec;
+	uint32_t mcr = sec_in32(&sec->mcfgr);
+#if defined(CONFIG_SPL_BUILD) && (defined(CONFIG_IMX8M) || defined(CONFIG_IMX8ULP))
+	uint32_t jrdid_ms = 0;
+#endif
 #ifdef CONFIG_FSL_CORENET
 	uint32_t liodnr;
 	uint32_t liodn_ns;
@@ -682,6 +848,14 @@ int sec_init_idx(uint8_t sec_idx)
 	mcr |= (1 << MCFGR_PS_SHIFT);
 #endif
 	sec_out32(&sec->mcfgr, mcr);
+#ifdef CONFIG_IMX8ULP
+	sec_reset();
+#endif
+#if defined(CONFIG_SPL_BUILD) && (defined(CONFIG_IMX8M) || defined(CONFIG_IMX8ULP))
+	jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ | JRDID_MS_PRIM_DID;
+	sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms);
+#endif
+	jr_reset();
 
 #ifdef CONFIG_FSL_CORENET
 #ifdef CONFIG_SPL_BUILD
@@ -693,24 +867,37 @@ int sec_init_idx(uint8_t sec_idx)
 	liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK;
 	liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK;
 
-	liodnr = sec_in32(&sec->jrliodnr[0].ls) &
+	liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls) &
 		 ~(JRNSLIODN_MASK | JRSLIODN_MASK);
 	liodnr = liodnr |
 		 (liodn_ns << JRNSLIODN_SHIFT) |
 		 (liodn_s << JRSLIODN_SHIFT);
-	sec_out32(&sec->jrliodnr[0].ls, liodnr);
+	sec_out32(&sec->jrliodnr[caam->jrid].ls, liodnr);
 #else
-	liodnr = sec_in32(&sec->jrliodnr[0].ls);
+	liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls);
 	liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
 	liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
 #endif
 #endif
-
-	ret = jr_init(sec_idx);
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+init:
+#endif
+	ret = jr_init(sec_idx, caam);
 	if (ret < 0) {
 		printf("SEC%u:  initialization failed\n", sec_idx);
 		return -1;
 	}
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+	if (ofnode_valid(scu_node)) {
+		if (IS_ENABLED(CONFIG_DM_RNG)) {
+			ret = device_bind_driver(NULL, "caam-rng", "caam-rng", NULL);
+			if (ret)
+				printf("Couldn't bind rng driver (%d)\n", ret);
+		}
+
+		return ret;
+	}
+#endif
 
 #ifdef CONFIG_FSL_CORENET
 	ret = sec_config_pamu_table(liodn_ns, liodn_s);
@@ -719,23 +906,25 @@ int sec_init_idx(uint8_t sec_idx)
 
 	pamu_enable();
 #endif
-#ifndef CONFIG_SPL_BUILD
-	if (get_rng_vid(sec_idx) >= 4) {
-		if (rng_init(sec_idx) < 0) {
+
+#ifdef CONFIG_RNG_SELF_TEST
+	rng_self_test();
+#endif
+	if (get_rng_vid(caam->sec) >= 4) {
+		if (rng_init(sec_idx, caam->sec) < 0) {
 			printf("SEC%u:  RNG instantiation failed\n", sec_idx);
 			return -1;
 		}
 
-		if (IS_ENABLED(CONFIG_DM_RNG)) {
-			ret = device_bind_driver(NULL, "caam-rng", "caam-rng",
-						 NULL);
-			if (ret)
-				printf("Couldn't bind rng driver (%d)\n", ret);
-		}
-
 		printf("SEC%u:  RNG instantiated\n", sec_idx);
 	}
-#endif
+
+	if (IS_ENABLED(CONFIG_DM_RNG)) {
+		ret = device_bind_driver(NULL, "caam-rng", "caam-rng", NULL);
+		if (ret)
+			printf("Couldn't bind rng driver (%d)\n", ret);
+	}
+
 	return ret;
 }
 
@@ -743,3 +932,98 @@ int sec_init(void)
 {
 	return sec_init_idx(0);
 }
+
+#if CONFIG_IS_ENABLED(DM)
+static int jr_power_on(ofnode node)
+{
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+	struct udevice __maybe_unused jr_dev;
+	struct power_domain pd;
+
+	dev_set_ofnode(&jr_dev, node);
+
+	/* Power on Job Ring before access it */
+	if (!power_domain_get(&jr_dev, &pd)) {
+		if (power_domain_on(&pd))
+			return -EINVAL;
+	}
+#endif
+	return 0;
+}
+
+static int caam_jr_ioctl(struct udevice *dev, unsigned long request, void *buf)
+{
+	if (request != CAAM_JR_RUN_DESC)
+		return -ENOSYS;
+
+	return run_descriptor_jr(buf);
+}
+
+static int caam_jr_probe(struct udevice *dev)
+{
+	struct caam_regs *caam = dev_get_priv(dev);
+	fdt_addr_t addr;
+	ofnode node, scu_node;
+	unsigned int jr_node = 0;
+
+	caam_dev = dev;
+
+	addr = dev_read_addr(dev);
+	if (addr == FDT_ADDR_T_NONE) {
+		printf("caam_jr: crypto not found\n");
+		return -EINVAL;
+	}
+	caam->sec = (ccsr_sec_t *)(uintptr_t)addr;
+	caam->regs = (struct jr_regs *)caam->sec;
+
+	/* Check for enabled job ring node */
+	ofnode_for_each_subnode(node, dev_ofnode(dev)) {
+		if (!ofnode_is_available(node))
+			continue;
+
+		jr_node = ofnode_read_u32_default(node, "reg", -1);
+		if (jr_node > 0) {
+			caam->regs = (struct jr_regs *)((ulong)caam->sec + jr_node);
+			while (!(jr_node & 0x0F))
+				jr_node = jr_node >> 4;
+
+			caam->jrid = jr_node - 1;
+			scu_node = ofnode_by_compatible(ofnode_null(), "fsl,imx8-mu");
+			if (ofnode_valid(scu_node)) {
+				if (jr_power_on(node))
+					return -EINVAL;
+			}
+			break;
+		}
+	}
+
+	if (sec_init())
+		printf("\nsec_init failed!\n");
+
+	return 0;
+}
+
+static int caam_jr_bind(struct udevice *dev)
+{
+	return 0;
+}
+
+static const struct misc_ops caam_jr_ops = {
+	.ioctl = caam_jr_ioctl,
+};
+
+static const struct udevice_id caam_jr_match[] = {
+	{ .compatible = "fsl,sec-v4.0" },
+	{ }
+};
+
+U_BOOT_DRIVER(caam_jr) = {
+	.name		= "caam_jr",
+	.id		= UCLASS_MISC,
+	.of_match	= caam_jr_match,
+	.ops		= &caam_jr_ops,
+	.bind		= caam_jr_bind,
+	.probe		= caam_jr_probe,
+	.priv_auto	= sizeof(struct caam_regs),
+};
+#endif
diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
index 1047aa772c4..2b6b5b7239b 100644
--- a/drivers/crypto/fsl/jr.h
+++ b/drivers/crypto/fsl/jr.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2008-2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  *
  */
 
@@ -8,7 +9,9 @@
 #define __JR_H
 
 #include <linux/compiler.h>
+#include "fsl_sec.h"
 #include "type.h"
+#include <misc.h>
 
 #define JR_SIZE 4
 /* Timeout currently defined as 10 sec */
@@ -35,12 +38,25 @@
 #define JRSLIODN_SHIFT		0
 #define JRSLIODN_MASK		0x00000fff
 
-#define JQ_DEQ_ERR		-1
-#define JQ_DEQ_TO_ERR		-2
-#define JQ_ENQ_ERR		-3
+#ifdef CONFIG_IMX8ULP
+#define JRDID_MS_PRIM_DID	7
+#else
+#define JRDID_MS_PRIM_DID	BIT(0)
+#endif
+#define JRDID_MS_PRIM_TZ	BIT(4)
+#define JRDID_MS_TZ_OWN		BIT(15)
+
+#define JQ_DEQ_ERR		(-1)
+#define JQ_DEQ_TO_ERR		(-2)
+#define JQ_ENQ_ERR		(-3)
 
 #define RNG4_MAX_HANDLES	2
 
+enum {
+	/* Run caam jobring descriptor(in buf) */
+	CAAM_JR_RUN_DESC,
+};
+
 struct op_ring {
 	caam_dma_addr_t desc;
 	uint32_t status;
@@ -102,7 +118,23 @@ struct result {
 	uint32_t status;
 };
 
+/*
+ * struct caam_regs - CAAM initialization register interface
+ *
+ * Interface to caam memory map, jobring register, jobring storage.
+ */
+struct caam_regs {
+	ccsr_sec_t *sec;	/*caam initialization registers*/
+	struct jr_regs *regs;	/*jobring configuration registers*/
+	u8 jrid;		/*id to identify a jobring*/
+	/*Private sub-storage for a single JobR*/
+	struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
+};
+
 void caam_jr_strstatus(u32 status);
 int run_descriptor_jr(uint32_t *desc);
 
+#ifdef CONFIG_RNG_SELF_TEST
+void rng_self_test(void);
+#endif
 #endif
diff --git a/drivers/crypto/fsl/rng_self_test.c b/drivers/crypto/fsl/rng_self_test.c
new file mode 100644
index 00000000000..d30fe4f5f0b
--- /dev/null
+++ b/drivers/crypto/fsl/rng_self_test.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright 2018, 2021 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <malloc.h>
+#include <asm/byteorder.h>
+#include <linux/compiler.h>
+#include <asm/arch/clock.h>
+#include <asm/global_data.h>
+#include <asm/arch/sys_proto.h>
+#include <memalign.h>
+#include <fsl_sec.h>
+#include "jobdesc.h"
+#include "desc.h"
+#include "jr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+uint32_t rng_dsc[] = {
+	0xb0800036, 0x04800010, 0x3c85a15b, 0x50a9d0b1,
+	0x71a09fee, 0x2eecf20b, 0x02800020, 0xb267292e,
+	0x85bf712d, 0xe85ff43a, 0xa716b7fb, 0xc40bb528,
+	0x27b6f564, 0x8821cb5d, 0x9b5f6c26, 0x12a00020,
+	0x0a20de17, 0x6529357e, 0x316277ab, 0x2846254e,
+	0x34d23ba5, 0x6f5e9c32, 0x7abdc1bb, 0x0197a385,
+	0x82500405, 0xa2000001, 0x10880004, 0x00000005,
+	0x12820004, 0x00000020, 0x82500001, 0xa2000001,
+	0x10880004, 0x40000045, 0x02800020, 0x8f389cc7,
+	0xe7f7cbb0, 0x6bf2073d, 0xfc380b6d, 0xb22e9d1a,
+	0xee64fcb7, 0xa2b48d49, 0xdf9bc3a4, 0x82500009,
+	0xa2000001, 0x10880004, 0x00000005, 0x82500001,
+	0x60340020, 0xFFFFFFFF, 0xa2000001, 0x10880004,
+	0x00000005, 0x8250000d
+};
+
+uint8_t rng_result[] = {
+	0x3a, 0xfe, 0x2c, 0x87, 0xcc, 0xb6, 0x44, 0x49,
+	0x19, 0x16, 0x9a, 0x74, 0xa1, 0x31, 0x8b, 0xef,
+	0xf4, 0x86, 0x0b, 0xb9, 0x5e, 0xee, 0xae, 0x91,
+	0x92, 0xf4, 0xa9, 0x8f, 0xb0, 0x37, 0x18, 0xa4
+};
+
+#define DSCSIZE 0x36
+#define KAT_SIZE 32
+#define INTEGRAL(x) ((x & 0x000F0) >> 4)
+#define FRACTIONAL(x) (x & 0x0000F)
+/*
+ * construct_rng_self_test_jobdesc() - Implement destination address in RNG self test descriptors
+ * @desc:	RNG descriptors address
+ *
+ * Returns zero on success,and negative on error.
+ */
+int construct_rng_self_test_jobdesc(u32 *desc, int desc_size, u8 *res_addr)
+{
+	u32 *rng_st_dsc = (uint32_t *)rng_dsc;
+	int result_addr_idx = desc_size - 5;
+	int i = 0;
+
+	/* Replace destination address in the descriptor */
+	rng_st_dsc[result_addr_idx] = (u32)res_addr;
+
+	for (i = 0; i < desc_size; i++)
+		desc[i] = rng_st_dsc[i];
+
+	debug("RNG SELF TEST DESCRIPTOR:\n");
+	for (i = 0; i < desc_size; i++)
+		debug("0x%08X\n", desc[i]);
+	debug("\n");
+
+	if (!desc) {
+		puts("RNG self test descriptor construction failed\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+/*
+ * rng_test() - Perform RNG self test
+ *
+ */
+void rng_test(void)
+{
+	int ret, size, i;
+	int desc_size = DSCSIZE;
+	u8 *result;
+	u32 *desc;
+
+	result = memalign(ARCH_DMA_MINALIGN, KAT_SIZE);
+	if(!result) {
+		puts("Not enough memory for RNG result\n");
+		return;
+	}
+
+	desc = memalign(ARCH_DMA_MINALIGN, sizeof(uint32_t) * desc_size);
+	if (!desc) {
+		puts("Not enough memory for descriptor allocation\n");
+		free(result);
+		return;
+	}
+
+	ret = construct_rng_self_test_jobdesc(desc, desc_size, result);
+	if (ret) {
+		puts("Error in Job Descriptor Construction\n");
+		goto err;
+	} else {
+		size = roundup(sizeof(uint32_t) * desc_size, ARCH_DMA_MINALIGN);
+		flush_dcache_range((unsigned long)desc, (unsigned long)desc + size);
+		size = roundup(sizeof(uint8_t) * KAT_SIZE, ARCH_DMA_MINALIGN);
+		flush_dcache_range((unsigned long)result, (unsigned long)result + size);
+
+		ret = run_descriptor_jr(desc);
+	}
+
+	if (ret) {
+		printf("Error while running RNG self-test descriptor: %d\n", ret);
+		goto err;
+	}
+
+	size = roundup(KAT_SIZE, ARCH_DMA_MINALIGN);
+	invalidate_dcache_range((unsigned long)result, (unsigned long)result + size);
+
+	debug("Result\n");
+	for (i = 0; i < KAT_SIZE; i++)
+		debug("%02X", result[i]);
+	debug("\n");
+
+	debug("Expected Result\n");
+	for (i = 0; i < KAT_SIZE; i++)
+		debug("%02X", rng_result[i]);
+	debug("\n");
+
+	for (i = 0; i < KAT_SIZE; i++) {
+		if (result[i] != rng_result[i]) {
+			printf("!!!WARNING!!!\nRNG self test failed.");
+			printf("If it keeps failing, do not perform any further crypto operations with RNG.\n");
+			printf("!!!!!!!!!!!!!\n");
+			goto err;
+		}
+	}
+	puts("RNG self test passed\n");
+
+err:
+	free(desc);
+	free(result);
+	return;
+}
+
+/*
+ * rng_self_test(void) - Check affected board and call RNG self test
+ */
+void rng_self_test(void)
+{
+	u32 cpurev;
+	cpurev = get_cpu_rev();
+#if defined(CONFIG_MX6QP)
+	if ((INTEGRAL(cpurev) == 1) && (FRACTIONAL(cpurev) == 1)) {
+		rng_test();
+	}
+#elif defined(CONFIG_MX6Q)
+	if ((INTEGRAL(cpurev) == 1) && (FRACTIONAL(cpurev) == 6)) {
+		rng_test();
+	}
+#elif defined(CONFIG_MX6S) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6SX)
+	if ((INTEGRAL(cpurev) == 1) && (FRACTIONAL(cpurev) == 4)) {
+		rng_test();
+	}
+#endif
+	return;
+}
diff --git a/drivers/crypto/fsl/tag_object.c b/drivers/crypto/fsl/tag_object.c
new file mode 100644
index 00000000000..c9c807a4a74
--- /dev/null
+++ b/drivers/crypto/fsl/tag_object.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * Copyright 2021 NXP
+ *
+ * Based on Tag object in drivers/crypto/caam in Linux
+ */
+
+#include <common.h>
+#include "tag_object.h"
+
+/**
+ * init_tag_object_header - Initialize the tag object header by setting up
+ *			the TAG_OBJECT_MAGIC number, tag object version,
+ *			a valid type and the object's length
+ * @header:		The header configuration to initialize
+ * @version:		The tag object version
+ * @type:		The tag object type
+ * @red_key_len:	The red key length
+ * @obj_len:		The object (actual data) length
+ */
+void init_tag_object_header(struct header_conf *header, u32 version,
+			    u32 type, size_t red_key_len, size_t obj_len)
+{
+	header->_magic_number = TAG_OBJECT_MAGIC;
+	header->version = version;
+	header->type = type;
+	header->red_key_len = red_key_len;
+	header->obj_len = obj_len;
+}
+
+/**
+ * set_tag_object_header_conf - Set tag object header configuration
+ * @header:			The tag object header configuration to set
+ * @buffer:			The buffer needed to be tagged
+ * @buf_size:			The buffer size
+ * @tag_obj_size:		The tagged object size
+ *
+ * Return:			'0' on success, error code otherwise
+ */
+int set_tag_object_header_conf(const struct header_conf *header,
+			       void *buffer, size_t buf_size, u32 *tag_obj_size)
+{
+	/* Retrieve the tag object */
+	struct tagged_object *tag_obj = (struct tagged_object *)buffer;
+	/*
+	 * Requested size for the tagged object is the buffer size
+	 * and the header configuration size (TAG_OVERHEAD_SIZE)
+	 */
+	size_t req_size = buf_size + TAG_OVERHEAD_SIZE;
+
+	/*
+	 * Check if the configuration can be set,
+	 * based on the size of the tagged object
+	 */
+	if (*tag_obj_size < req_size)
+		return -EINVAL;
+
+	/*
+	 * Buffers might overlap, use memmove to
+	 * copy the buffer into the tagged object
+	 */
+	memmove(&tag_obj->object, buffer, buf_size);
+	/* Copy the tag object header configuration into the tagged object */
+	memcpy(&tag_obj->header, header, TAG_OVERHEAD_SIZE);
+	/* Set tagged object size */
+	*tag_obj_size = req_size;
+
+	return 0;
+}
+
+/**
+ * tag_black_obj      - Tag a black object (blob/key) with a tag object header.
+ *
+ * @black_obj         : contains black key/blob,
+ *                      obtained from CAAM, that needs to be tagged
+ * @black_obj_len     : size of black object (blob/key)
+ * @key_len           : size of plain key
+ * @black_max_len     : The maximum size of the black object (blob/key)
+ *
+ * Return             : '0' on success, error code otherwise
+ */
+int tag_black_obj(u8 *black_obj, size_t black_obj_len, size_t key_len, size_t black_max_len)
+{
+	struct header_conf tag;
+	u32 type = 1;				/*ECB encrypted black key*/
+	int ret;
+	u32 size_tagged = black_max_len;
+
+	if (!black_obj)
+		return -EINVAL;
+
+	/* Prepare and set the tag */
+	init_tag_object_header(&tag, 0, type, key_len, black_obj_len);
+	ret = set_tag_object_header_conf(&tag, black_obj, black_obj_len, &size_tagged);
+
+	return ret;
+}
diff --git a/drivers/crypto/fsl/tag_object.h b/drivers/crypto/fsl/tag_object.h
new file mode 100644
index 00000000000..63d348e4c0b
--- /dev/null
+++ b/drivers/crypto/fsl/tag_object.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
+/*
+ * Copyright 2021 NXP
+ *
+ */
+
+#ifndef _TAG_OBJECT_H_
+#define _TAG_OBJECT_H_
+
+#include <linux/compiler.h>
+#include "type.h"
+
+/**
+ * Magic number to identify the tag object structure
+ * 0x54 = 'T'
+ * 0x61 = 'a'
+ * 0x67 = 'g'
+ * 0x4f = 'O'
+ */
+#define TAG_OBJECT_MAGIC	0x5461674f
+#define TAG_OVERHEAD_SIZE	sizeof(struct header_conf)
+
+/**
+ * struct header_conf - Header configuration structure, which represents
+ *			the metadata (or simply a header) applied to the
+ *			actual data (e.g. black key)
+ * @_magic_number     : A magic number to identify the structure
+ * @version           : The version of the data contained (e.g. tag object)
+ * @type              : The type of data contained (e.g. black key, blob, etc.)
+ * @red_key_len       : Length of the red key to be loaded by CAAM (for key
+ *                      generation or blob encapsulation)
+ * @obj_len           : The total length of the (black/red) object (key/blob),
+ *                      after encryption/encapsulation
+ */
+struct header_conf {
+	u32 _magic_number;
+	u32 version;
+	u32 type;
+	u32 red_key_len;
+	u32 obj_len;
+};
+
+/**
+ * struct tagged_object - Tag object structure, which represents the metadata
+ *                        (or simply a header) and the actual data
+ *                        (e.g. black key) obtained from hardware
+ * @tag                 : The configuration of the data (e.g. header)
+ * @object              : The actual data (e.g. black key)
+ */
+struct tagged_object {
+	struct header_conf header;
+	char object;
+};
+
+void init_tag_object_header(struct header_conf *header, u32 version,
+			    u32 type, size_t red_key_len, size_t obj_len);
+
+int set_tag_object_header_conf(const struct header_conf *header,
+			       void *buffer, size_t obj_size, u32 *to_size);
+
+#endif /* _TAG_OBJECT_H_ */
diff --git a/drivers/ddr/imx/Kconfig b/drivers/ddr/imx/Kconfig
index 179f34530d7..328fbabb6db 100644
--- a/drivers/ddr/imx/Kconfig
+++ b/drivers/ddr/imx/Kconfig
@@ -1,2 +1,4 @@
 source "drivers/ddr/imx/imx8m/Kconfig"
 source "drivers/ddr/imx/imx8ulp/Kconfig"
+source "drivers/ddr/imx/imx9/Kconfig"
+source "drivers/ddr/imx/phy/Kconfig"
diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig
index a90b7db4940..15a2b030f8a 100644
--- a/drivers/ddr/imx/imx8m/Kconfig
+++ b/drivers/ddr/imx/imx8m/Kconfig
@@ -3,6 +3,7 @@ menu "i.MX8M DDR controllers"
 
 config IMX8M_DRAM
 	bool "imx8m dram"
+	select IMX_SNPS_DDR_PHY
 
 config IMX8M_LPDDR4
 	bool "imx8m lpddr4"
@@ -32,7 +33,7 @@ config SAVED_DRAM_TIMING_BASE
 
 config IMX8M_DRAM_INLINE_ECC
 	bool "imx8mp inline ECC"
-	depends on IMX8MP && IMX8M_LPDDR4
+	depends on IMX8MP
 	help
 	  Select this config if you want to use inline ecc feature for
 	  imx8mp-evk board.
@@ -44,4 +45,10 @@ config IMX8M_VDD_SOC_850MV
 config IMX8M_LPDDR4_FREQ0_2400MTS
 	bool "imx8m PDDR4 freq0 change from 4000MTS to 2400MTS"
 
+config IMX8M_LPDDR4_FREQ0_3200MTS
+	bool "imx8m LPDDR4 freq0 change from 4000MTS to 3200MTS"
+
+config IMX8M_4G_LPDDR4
+	bool "imx8m 4GB LPDDR4"
+
 endmenu
diff --git a/drivers/ddr/imx/imx8m/Makefile b/drivers/ddr/imx/imx8m/Makefile
index bd9bcb8d53b..aed91dc23f4 100644
--- a/drivers/ddr/imx/imx8m/Makefile
+++ b/drivers/ddr/imx/imx8m/Makefile
@@ -5,5 +5,6 @@
 #
 
 ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_IMX8M_DRAM) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o ddr_init.o
+obj-$(CONFIG_IMX8M_DRAM) += ddr_init.o
+obj-y += ../phy/
 endif
diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c
index b70bcc383fa..d64edc57be0 100644
--- a/drivers/ddr/imx/imx8m/ddr_init.c
+++ b/drivers/ddr/imx/imx8m/ddr_init.c
@@ -11,6 +11,11 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 
+static unsigned int g_cdd_rr_max[4];
+static unsigned int g_cdd_rw_max[4];
+static unsigned int g_cdd_wr_max[4];
+static unsigned int g_cdd_ww_max[4];
+
 void ddr_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
 {
 	int i = 0;
@@ -54,9 +59,9 @@ void ddrc_inline_ecc_scrub(unsigned int start_address,
 	/* Step11: Disable SBR by programming SBRCTL.scrub_en=0 */
 	clrbits_le32(DDRC_SBRCTL(0), 0x1);
 	/* Step12: Prepare for normal scrub operation(Read) and set scrub_interval*/
-	reg32_write(DDRC_SBRCTL(0), 0x100);
+	reg32_write(DDRC_SBRCTL(0), 0xFF20);
 	/* Step13: Enable the SBR by programming SBRCTL.scrub_en=1 */
-	reg32_write(DDRC_SBRCTL(0), 0x101);
+	reg32_write(DDRC_SBRCTL(0), 0xFF21);
 	/* Step14: Enable AXI ports by programming */
 	reg32_write(DDRC_PCTRL_0(0), 0x1);
 	/* Step15: Disable quasi-dynamic programming */
@@ -91,12 +96,215 @@ void __weak board_dram_ecc_scrub(void)
 {
 }
 
+void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr,
+		     unsigned int mr_data)
+{
+	unsigned int tmp;
+	/*
+	 * 1. Poll MRSTAT.mr_wr_busy until it is 0.
+	 * This checks that there is no outstanding MR transaction.
+	 * No writes should be performed to MRCTRL0 and MRCTRL1 if
+	 * MRSTAT.mr_wr_busy = 1.
+	 */
+	do {
+		tmp = reg32_read(DDRC_MRSTAT(0));
+	} while (tmp & 0x1);
+	/*
+	 * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and
+	 * (for MRWs) MRCTRL1.mr_data to define the MR transaction.
+	 */
+	reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4));
+	reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data);
+	reg32setbit(DDRC_MRCTRL0(0), 31);
+}
+
+unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
+{
+	unsigned int tmp;
+
+	reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1);
+	do {
+		tmp = reg32_read(DDRC_MRSTAT(0));
+	} while (tmp & 0x1);
+
+	reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1);
+	reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8));
+	reg32setbit(DDRC_MRCTRL0(0), 31);
+	do {
+		tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
+	} while ((tmp & 0x8) == 0);
+	tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
+	tmp = tmp & 0xff;
+	reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
+
+	return tmp;
+}
+
+static unsigned int look_for_max(unsigned int data[],
+			  unsigned int addr_start, unsigned int addr_end)
+{
+	unsigned int i, imax = 0;
+
+	for (i = addr_start; i <= addr_end; i++) {
+		if (((data[i] >> 7) == 0) && (data[i] > imax))
+			imax = data[i];
+	}
+
+	return imax;
+}
+
+void get_trained_CDD(u32 fsp)
+{
+	unsigned int i, ddr_type, tmp;
+	unsigned int cdd_cha[12], cdd_chb[12];
+	unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max;
+	unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max;
+
+	ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
+	if (ddr_type == 0x20) {
+		for (i = 0; i < 6; i++) {
+			tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54013 + i) * 4);
+			cdd_cha[i * 2] = tmp & 0xff;
+			cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff;
+		}
+
+		for (i = 0; i < 7; i++) {
+			tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x5402c + i) * 4);
+			if (i == 0) {
+				cdd_cha[0] = (tmp >> 8) & 0xff;
+			} else if (i == 6) {
+				cdd_cha[11] = tmp & 0xff;
+			} else {
+				cdd_chb[i * 2 - 1] = tmp & 0xff;
+				cdd_chb[i * 2] = (tmp >> 8) & 0xff;
+			}
+		}
+
+		cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1);
+		cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5);
+		cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9);
+		cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11);
+		cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1);
+		cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5);
+		cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9);
+		cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11);
+		g_cdd_rr_max[fsp] =  cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max;
+		g_cdd_rw_max[fsp] =  cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max;
+		g_cdd_wr_max[fsp] =  cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max;
+		g_cdd_ww_max[fsp] =  cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max;
+	} else {
+		unsigned int ddr4_cdd[64];
+
+		for (i = 0; i < 29; i++) {
+			tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54012 + i) * 4);
+			ddr4_cdd[i * 2] = tmp & 0xff;
+			ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff;
+		}
+
+		g_cdd_rr_max[fsp] = look_for_max(ddr4_cdd, 1, 12);
+		g_cdd_ww_max[fsp] = look_for_max(ddr4_cdd, 13, 24);
+		g_cdd_rw_max[fsp] = look_for_max(ddr4_cdd, 25, 40);
+		g_cdd_wr_max[fsp] = look_for_max(ddr4_cdd, 41, 56);
+	}
+}
+
+void update_umctl2_rank_space_setting(unsigned int pstat_num)
+{
+	unsigned int i, ddr_type;
+	unsigned int addr_slot, rdata, tmp, tmp_t;
+	unsigned int ddrc_w2r, ddrc_r2w, ddrc_wr_gap, ddrc_rd_gap;
+
+	ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
+	for (i = 0; i < pstat_num; i++) {
+		addr_slot = i ? (i + 1) * 0x1000 : 0;
+		if (ddr_type == 0x20) {
+			/* update r2w:[13:8], w2r:[5:0] */
+			rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
+			ddrc_w2r = rdata & 0x3f;
+			if (is_imx8mp())
+				tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
+			else
+				tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
+			ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
+
+			ddrc_r2w = (rdata >> 8) & 0x3f;
+			if (is_imx8mp())
+				tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
+			else
+				tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
+			ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
+
+			tmp_t = (rdata & 0xffffc0c0) | (ddrc_r2w << 8) | ddrc_w2r;
+			reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
+		} else {
+			/* update w2r:[5:0] */
+			rdata = reg32_read(DDRC_DRAMTMG9(0) + addr_slot);
+			ddrc_w2r = rdata & 0x3f;
+			if (is_imx8mp())
+				tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
+			else
+				tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
+			ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
+			tmp_t = (rdata & 0xffffffc0) | ddrc_w2r;
+			reg32_write((DDRC_DRAMTMG9(0) + addr_slot), tmp_t);
+
+			/* update r2w:[13:8] */
+			rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
+			ddrc_r2w = (rdata >> 8) & 0x3f;
+			if (is_imx8mp())
+				tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
+			else
+				tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
+			ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
+
+			tmp_t = (rdata & 0xffffc0ff) | (ddrc_r2w << 8);
+			reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
+		}
+
+		if (!is_imx8mq()) {
+			/* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */
+			rdata = reg32_read(DDRC_RANKCTL(0) + addr_slot);
+			ddrc_wr_gap = (rdata >> 8) & 0xf;
+			if (is_imx8mp())
+				tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1);
+			else
+				tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1) + 1;
+			ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
+
+			ddrc_rd_gap = (rdata >> 4) & 0xf;
+			if (is_imx8mp())
+				tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1);
+			else
+				tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1) + 1;
+			ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
+
+			tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
+			reg32_write((DDRC_RANKCTL(0) + addr_slot), tmp_t);
+		}
+	}
+
+	if (is_imx8mq()) {
+		/* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */
+		rdata = reg32_read(DDRC_RANKCTL(0));
+		ddrc_wr_gap = (rdata >> 8) & 0xf;
+		tmp = ddrc_wr_gap + (g_cdd_ww_max[0] >> 1) + 1;
+		ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
+
+		ddrc_rd_gap = (rdata >> 4) & 0xf;
+		tmp = ddrc_rd_gap + (g_cdd_rr_max[0] >> 1) + 1;
+		ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
+
+		tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
+		reg32_write(DDRC_RANKCTL(0), tmp_t);
+	}
+}
+
 int ddr_init(struct dram_timing_info *dram_timing)
 {
 	unsigned int tmp, initial_drate, target_freq;
 	int ret;
 
-	debug("DDRINFO: start DRAM init\n");
+	printf("DDRINFO: start DRAM init\n");
 
 	/* Step1: Follow the power up procedure */
 	if (is_imx8mq()) {
@@ -119,6 +327,7 @@ int ddr_init(struct dram_timing_info *dram_timing)
 
 	initial_drate = dram_timing->fsp_msg[0].drate;
 	/* default to the frequency point 0 clock */
+	printf("DDRINFO: DRAM rate %dMTS\n", initial_drate);
 	ddrphy_init_set_dfi_clk(initial_drate);
 
 	/* D-aasert the presetn */
@@ -185,7 +394,7 @@ int ddr_init(struct dram_timing_info *dram_timing)
 		tmp = reg32_read(DDRPHY_CalBusy(0));
 	} while ((tmp & 0x1));
 
-	debug("DDRINFO:ddrphy calibration done\n");
+	printf("DDRINFO:ddrphy calibration done\n");
 
 	/* Step15: Set SWCTL.sw_done to 0 */
 	reg32_write(DDRC_SWCTL(0), 0x00000000);
@@ -238,7 +447,7 @@ int ddr_init(struct dram_timing_info *dram_timing)
 
 	/* enable port 0 */
 	reg32_write(DDRC_PCTRL_0(0), 0x00000001);
-	debug("DDRINFO: ddrmix config done\n");
+	printf("DDRINFO: ddrmix config done\n");
 
 	board_dram_ecc_scrub();
 
@@ -250,3 +459,8 @@ int ddr_init(struct dram_timing_info *dram_timing)
 
 	return 0;
 }
+
+ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr)
+{
+	return 4 * paddr_apb_from_ctlr;
+}
diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c
deleted file mode 100644
index 0f8baefb1f8..00000000000
--- a/drivers/ddr/imx/imx8m/ddrphy_utils.c
+++ /dev/null
@@ -1,360 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2018 NXP
- */
-
-#include <common.h>
-#include <errno.h>
-#include <log.h>
-#include <asm/io.h>
-#include <asm/arch/ddr.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/ddr.h>
-#include <asm/arch/lpddr4_define.h>
-#include <asm/arch/sys_proto.h>
-
-static unsigned int g_cdd_rr_max[4];
-static unsigned int g_cdd_rw_max[4];
-static unsigned int g_cdd_wr_max[4];
-static unsigned int g_cdd_ww_max[4];
-
-static inline void poll_pmu_message_ready(void)
-{
-	unsigned int reg;
-
-	do {
-		reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
-	} while (reg & 0x1);
-}
-
-static inline void ack_pmu_message_receive(void)
-{
-	unsigned int reg;
-
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x0);
-
-	do {
-		reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0004);
-	} while (!(reg & 0x1));
-
-	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0031, 0x1);
-}
-
-static inline unsigned int get_mail(void)
-{
-	unsigned int reg;
-
-	poll_pmu_message_ready();
-
-	reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
-
-	ack_pmu_message_receive();
-
-	return reg;
-}
-
-static inline unsigned int get_stream_message(void)
-{
-	unsigned int reg, reg2;
-
-	poll_pmu_message_ready();
-
-	reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0032);
-
-	reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0034);
-
-	reg2 = (reg2 << 16) | reg;
-
-	ack_pmu_message_receive();
-
-	return reg2;
-}
-
-static inline void decode_major_message(unsigned int mail)
-{
-	debug("[PMU Major message = 0x%08x]\n", mail);
-}
-
-static inline void decode_streaming_message(void)
-{
-	unsigned int string_index, arg __maybe_unused;
-	int i = 0;
-
-	string_index = get_stream_message();
-	debug("PMU String index = 0x%08x\n", string_index);
-	while (i < (string_index & 0xffff)) {
-		arg = get_stream_message();
-		debug("arg[%d] = 0x%08x\n", i, arg);
-		i++;
-	}
-
-	debug("\n");
-}
-
-int wait_ddrphy_training_complete(void)
-{
-	unsigned int mail;
-
-	while (1) {
-		mail = get_mail();
-		decode_major_message(mail);
-		if (mail == 0x08) {
-			decode_streaming_message();
-		} else if (mail == 0x07) {
-			debug("Training PASS\n");
-			return 0;
-		} else if (mail == 0xff) {
-			debug("Training FAILED\n");
-			return -1;
-		}
-	}
-}
-
-void ddrphy_init_set_dfi_clk(unsigned int drate)
-{
-	switch (drate) {
-	case 4000:
-		dram_pll_init(MHZ(1000));
-		dram_disable_bypass();
-		break;
-	case 3200:
-		dram_pll_init(MHZ(800));
-		dram_disable_bypass();
-		break;
-	case 3000:
-		dram_pll_init(MHZ(750));
-		dram_disable_bypass();
-		break;
-	case 2400:
-		dram_pll_init(MHZ(600));
-		dram_disable_bypass();
-		break;
-	case 1600:
-		dram_pll_init(MHZ(400));
-		dram_disable_bypass();
-		break;
-	case 1066:
-		dram_pll_init(MHZ(266));
-		dram_disable_bypass();
-		break;
-	case 667:
-		dram_pll_init(MHZ(167));
-		dram_disable_bypass();
-		break;
-	case 400:
-		dram_enable_bypass(MHZ(400));
-		break;
-	case 100:
-		dram_enable_bypass(MHZ(100));
-		break;
-	default:
-		return;
-	}
-}
-
-void ddrphy_init_read_msg_block(enum fw_type type)
-{
-}
-
-void lpddr4_mr_write(unsigned int mr_rank, unsigned int mr_addr,
-		     unsigned int mr_data)
-{
-	unsigned int tmp;
-	/*
-	 * 1. Poll MRSTAT.mr_wr_busy until it is 0.
-	 * This checks that there is no outstanding MR transaction.
-	 * No writes should be performed to MRCTRL0 and MRCTRL1 if
-	 * MRSTAT.mr_wr_busy = 1.
-	 */
-	do {
-		tmp = reg32_read(DDRC_MRSTAT(0));
-	} while (tmp & 0x1);
-	/*
-	 * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank and
-	 * (for MRWs) MRCTRL1.mr_data to define the MR transaction.
-	 */
-	reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4));
-	reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data);
-	reg32setbit(DDRC_MRCTRL0(0), 31);
-}
-
-unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
-{
-	unsigned int tmp;
-
-	reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1);
-	do {
-		tmp = reg32_read(DDRC_MRSTAT(0));
-	} while (tmp & 0x1);
-
-	reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1);
-	reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8));
-	reg32setbit(DDRC_MRCTRL0(0), 31);
-	do {
-		tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
-	} while ((tmp & 0x8) == 0);
-	tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
-	tmp = tmp & 0xff;
-	reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
-
-	return tmp;
-}
-
-unsigned int look_for_max(unsigned int data[],
-			  unsigned int addr_start, unsigned int addr_end)
-{
-	unsigned int i, imax = 0;
-
-	for (i = addr_start; i <= addr_end; i++) {
-		if (((data[i] >> 7) == 0) && (data[i] > imax))
-			imax = data[i];
-	}
-
-	return imax;
-}
-
-void get_trained_CDD(u32 fsp)
-{
-	unsigned int i, ddr_type, tmp;
-	unsigned int cdd_cha[12], cdd_chb[12];
-	unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max;
-	unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max;
-
-	ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
-	if (ddr_type == 0x20) {
-		for (i = 0; i < 6; i++) {
-			tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54013 + i) * 4);
-			cdd_cha[i * 2] = tmp & 0xff;
-			cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff;
-		}
-
-		for (i = 0; i < 7; i++) {
-			tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x5402c + i) * 4);
-			if (i == 0) {
-				cdd_cha[0] = (tmp >> 8) & 0xff;
-			} else if (i == 6) {
-				cdd_cha[11] = tmp & 0xff;
-			} else {
-				cdd_chb[i * 2 - 1] = tmp & 0xff;
-				cdd_chb[i * 2] = (tmp >> 8) & 0xff;
-			}
-		}
-
-		cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1);
-		cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5);
-		cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9);
-		cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11);
-		cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1);
-		cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5);
-		cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9);
-		cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11);
-		g_cdd_rr_max[fsp] =  cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max;
-		g_cdd_rw_max[fsp] =  cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max;
-		g_cdd_wr_max[fsp] =  cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max;
-		g_cdd_ww_max[fsp] =  cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max;
-	} else {
-		unsigned int ddr4_cdd[64];
-
-		for (i = 0; i < 29; i++) {
-			tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54012 + i) * 4);
-			ddr4_cdd[i * 2] = tmp & 0xff;
-			ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff;
-		}
-
-		g_cdd_rr_max[fsp] = look_for_max(ddr4_cdd, 1, 12);
-		g_cdd_ww_max[fsp] = look_for_max(ddr4_cdd, 13, 24);
-		g_cdd_rw_max[fsp] = look_for_max(ddr4_cdd, 25, 40);
-		g_cdd_wr_max[fsp] = look_for_max(ddr4_cdd, 41, 56);
-	}
-}
-
-void update_umctl2_rank_space_setting(unsigned int pstat_num)
-{
-	unsigned int i, ddr_type;
-	unsigned int addr_slot, rdata, tmp, tmp_t;
-	unsigned int ddrc_w2r, ddrc_r2w, ddrc_wr_gap, ddrc_rd_gap;
-
-	ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
-	for (i = 0; i < pstat_num; i++) {
-		addr_slot = i ? (i + 1) * 0x1000 : 0;
-		if (ddr_type == 0x20) {
-			/* update r2w:[13:8], w2r:[5:0] */
-			rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
-			ddrc_w2r = rdata & 0x3f;
-			if (is_imx8mp())
-				tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
-			else
-				tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
-			ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
-
-			ddrc_r2w = (rdata >> 8) & 0x3f;
-			if (is_imx8mp())
-				tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
-			else
-				tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
-			ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
-
-			tmp_t = (rdata & 0xffffc0c0) | (ddrc_r2w << 8) | ddrc_w2r;
-			reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
-		} else {
-			/* update w2r:[5:0] */
-			rdata = reg32_read(DDRC_DRAMTMG9(0) + addr_slot);
-			ddrc_w2r = rdata & 0x3f;
-			if (is_imx8mp())
-				tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
-			else
-				tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
-			ddrc_w2r = (tmp > 0x3f) ? 0x3f : tmp;
-			tmp_t = (rdata & 0xffffffc0) | ddrc_w2r;
-			reg32_write((DDRC_DRAMTMG9(0) + addr_slot), tmp_t);
-
-			/* update r2w:[13:8] */
-			rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
-			ddrc_r2w = (rdata >> 8) & 0x3f;
-			if (is_imx8mp())
-				tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
-			else
-				tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
-			ddrc_r2w = (tmp > 0x3f) ? 0x3f : tmp;
-
-			tmp_t = (rdata & 0xffffc0ff) | (ddrc_r2w << 8);
-			reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
-		}
-
-		if (!is_imx8mq()) {
-			/* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */
-			rdata = reg32_read(DDRC_RANKCTL(0) + addr_slot);
-			ddrc_wr_gap = (rdata >> 8) & 0xf;
-			if (is_imx8mp())
-				tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1);
-			else
-				tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1) + 1;
-			ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
-
-			ddrc_rd_gap = (rdata >> 4) & 0xf;
-			if (is_imx8mp())
-				tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1);
-			else
-				tmp = ddrc_rd_gap + (g_cdd_rr_max[i] >> 1) + 1;
-			ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
-
-			tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
-			reg32_write((DDRC_RANKCTL(0) + addr_slot), tmp_t);
-		}
-	}
-
-	if (is_imx8mq()) {
-		/* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */
-		rdata = reg32_read(DDRC_RANKCTL(0));
-		ddrc_wr_gap = (rdata >> 8) & 0xf;
-		tmp = ddrc_wr_gap + (g_cdd_ww_max[0] >> 1) + 1;
-		ddrc_wr_gap = (tmp > 0xf) ? 0xf : tmp;
-
-		ddrc_rd_gap = (rdata >> 4) & 0xf;
-		tmp = ddrc_rd_gap + (g_cdd_rr_max[0] >> 1) + 1;
-		ddrc_rd_gap = (tmp > 0xf) ? 0xf : tmp;
-
-		tmp_t = (rdata & 0xfffff00f) | (ddrc_wr_gap << 8) | (ddrc_rd_gap << 4);
-		reg32_write(DDRC_RANKCTL(0), tmp_t);
-	}
-}
diff --git a/drivers/ddr/imx/imx8ulp/ddr_init.c b/drivers/ddr/imx/imx8ulp/ddr_init.c
index a5a9fd8d7c8..c362a2da338 100644
--- a/drivers/ddr/imx/imx8ulp/ddr_init.c
+++ b/drivers/ddr/imx/imx8ulp/ddr_init.c
@@ -31,6 +31,7 @@
 #define DENALI_CTL_25		(DDR_CTL_BASE_ADDR + 4 * 25)
 
 #define DENALI_PHY_1624		(DDR_PHY_BASE_ADDR + 4 * 1624)
+#define DENALI_PHY_1625  	(DDR_PHY_BASE_ADDR + 4 * 1625)
 #define DENALI_PHY_1537		(DDR_PHY_BASE_ADDR + 4 * 1537)
 #define PHY_FREQ_SEL_MULTICAST_EN(X)	((X) << 8)
 #define PHY_FREQ_SEL_INDEX(X)		((X) << 16)
@@ -82,25 +83,39 @@ int ddr_calibration(unsigned int fsp_table[3])
 	u32 int_status_init, phy_freq_req, phy_freq_type;
 	u32 lock_0, lock_1, lock_2;
 	u32 freq_chg_pt, freq_chg_cnt;
+	u32 is_lpddr4 = 0;
 
 	if (IS_ENABLED(CONFIG_IMX8ULP_DRAM_PHY_PLL_BYPASS)) {
 		ddr_enable_pll_bypass();
 		freq_chg_cnt = 0;
 		freq_chg_pt = 0;
 	} else {
-		reg_val = readl(DENALI_CTL_250);
-		if (((reg_val >> 16) & 0x3) == 1)
-			freq_chg_cnt = 2;
-		else
-			freq_chg_cnt = 3;
-
-		reg_val = readl(DENALI_PI_12);
-		if (reg_val == 0x3) {
-			freq_chg_pt = 1;
-		} else if (reg_val == 0x7) {
-			freq_chg_pt = 2;
+		reg_val = (readl(DENALI_CTL_00)>>8)&0xf;
+		if(reg_val == 0x7) {
+			/* LPDDR3 type */
+			set_ddr_clk(fsp_table[1] >> 1);
+			freq_chg_cnt = 0;
+			freq_chg_pt = 0;
+		} else if(reg_val == 0xb) {
+			/* LPDDR4/4x type */
+			is_lpddr4 = 1;
+			reg_val = readl(DENALI_CTL_250);
+			if (((reg_val >> 16) & 0x3) == 1)
+				freq_chg_cnt = 2;
+			else
+				freq_chg_cnt = 3;
+
+			reg_val = readl(DENALI_PI_12);
+			if(reg_val == 0x3)
+				freq_chg_pt = 1;
+			else if(reg_val == 0x7)
+				freq_chg_pt = 2;
+			else {
+				printf("frequency map(0x%x) is wrong, please check!\r\n", reg_val);
+				return -1;
+			}
 		} else {
-			printf("frequency map(0x%x) is wrong, please check!\r\n", reg_val);
+			printf("Incorrect DDR type configured!\r\n");
 			return -1;
 		}
 	}
@@ -179,6 +194,22 @@ int ddr_calibration(unsigned int fsp_table[3])
 	}
 
 	debug("De-Skew PLL is locked and ready\n");
+
+	/* Change LPDDR4 FREQ1 to bypass mode if it is lower than 200MHz */
+	if(is_lpddr4 && fsp_table[1] < 400) {
+		/* Set FREQ1 to bypass mode */
+		reg_val = PHY_FREQ_SEL_MULTICAST_EN(0) | PHY_FREQ_SEL_INDEX(0);
+		writel(reg_val, DENALI_PHY_1537);
+
+		/* PHY_PLL_BYPASS=0x1 (DENALI_PHY_1624) */
+		reg_val =readl(DENALI_PHY_1624) | 0x1;
+		writel(reg_val, DENALI_PHY_1624);
+
+		/* DENALI_PHY_1625: bypass mode in PHY PLL */
+		reg_val =readl(DENALI_PHY_1625) & ~0xf;
+		writel(reg_val, DENALI_PHY_1625);
+	}
+
 	return 0;
 }
 
diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig
new file mode 100644
index 00000000000..123ad173cfc
--- /dev/null
+++ b/drivers/ddr/imx/imx9/Kconfig
@@ -0,0 +1,27 @@
+menu "i.MX9 DDR controllers"
+	depends on ARCH_IMX9
+
+config IMX9_DRAM
+	bool "imx9 dram"
+	select IMX_SNPS_DDR_PHY
+
+config IMX9_LPDDR4X
+	bool "imx9 lpddr4 and lpddr4x"
+	select IMX9_DRAM
+	help
+	  Select the i.MX9 LPDDR4/4X driver support on i.MX9 SOC.
+
+config IMX9_DRAM_PM_COUNTER
+	bool "imx9 DDRC performance monitor counter"
+	default y
+	help
+	  Enable DDR controller performance monitor counter for reference events.
+
+config SAVED_DRAM_TIMING_BASE
+	hex "Define the base address for saved dram timing"
+	help
+	  after DRAM is trained, need to save the dram related timming
+	  info into memory for low power use.
+	default 0x204DC000
+
+endmenu
diff --git a/drivers/ddr/imx/imx9/Makefile b/drivers/ddr/imx/imx9/Makefile
new file mode 100644
index 00000000000..9403f988b32
--- /dev/null
+++ b/drivers/ddr/imx/imx9/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_IMX9_DRAM) += ddr_init.o
+obj-y += ../phy/
+endif
diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c
new file mode 100644
index 00000000000..7cf1142f9ab
--- /dev/null
+++ b/drivers/ddr/imx/imx9/ddr_init.c
@@ -0,0 +1,386 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/delay.h>
+
+static unsigned int g_cdd_rr_max[4];
+static unsigned int g_cdd_rw_max[4];
+static unsigned int g_cdd_wr_max[4];
+static unsigned int g_cdd_ww_max[4];
+
+#define MAX(a, b)	(((a) > (b)) ? (a) : (b))
+
+void ddrphy_coldreset(void)
+{
+	/* dramphy_apb_n default 1 , assert -> 0, de_assert -> 1 */
+	/* dramphy_reset_n default 0 , assert -> 0, de_assert -> 1 */
+	/* dramphy_PwrOKIn default 0 , assert -> 1, de_assert -> 0 */
+
+	/* src_gen_dphy_apb_sw_rst_de_assert */
+	clrbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0));
+	/* src_gen_dphy_sw_rst_de_assert */
+	clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2));
+	/* src_gen_dphy_PwrOKIn_sw_rst_de_assert() */
+	setbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(0));
+	mdelay(10);
+
+	/* src_gen_dphy_apb_sw_rst_assert */
+	setbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0));
+	/* src_gen_dphy_sw_rst_assert */
+	setbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2));
+	mdelay(10);
+	/* src_gen_dphy_PwrOKIn_sw_rst_assert */
+	clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(0));
+	mdelay(10);
+
+	/* src_gen_dphy_apb_sw_rst_de_assert */
+	clrbits_le32(REG_SRC_DPHY_SW_CTRL, BIT(0));
+	/* src_gen_dphy_sw_rst_de_assert() */
+	clrbits_le32(REG_SRC_DPHY_SINGLE_RESET_SW_CTRL, BIT(2));
+}
+
+void check_ddrc_idle(void){
+	uint32_t regval;
+
+	do{
+		regval = readl(REG_DDRDSR_2);
+		if(regval & BIT(31))
+			break;
+	}while(1);
+}
+
+void check_dfi_init_complete(void)
+{
+	uint32_t regval;
+
+	do{
+		regval = readl(REG_DDRDSR_2);
+		if(regval & BIT(2))
+			break;
+	}while(1);
+	setbits_le32(REG_DDRDSR_2, BIT(2));
+}
+
+void ddrc_config(struct dram_cfg_param *ddrc_config, int num)
+{
+	int i = 0;
+
+	for (i = 0; i < num; i++) {
+		writel(ddrc_config->val, (ulong)ddrc_config->reg);
+		ddrc_config++;
+	}
+}
+
+static unsigned int look_for_max(unsigned int data[],
+	unsigned int addr_start, unsigned int addr_end)
+{
+	unsigned int i, imax = 0;
+
+	for (i = addr_start; i <= addr_end; i++) {
+		if (((data[i] >> 7) == 0) && (data[i] > imax))
+			imax = data[i];
+	}
+
+	return imax;
+}
+
+void get_trained_CDD(u32 fsp)
+{
+	unsigned int i, tmp;
+	unsigned int cdd_cha[12], cdd_chb[12];
+	unsigned int cdd_cha_rr_max, cdd_cha_rw_max, cdd_cha_wr_max, cdd_cha_ww_max;
+	unsigned int cdd_chb_rr_max, cdd_chb_rw_max, cdd_chb_wr_max, cdd_chb_ww_max;
+
+	for (i = 0; i < 6; i++) {
+		tmp = dwc_ddrphy_apb_rd(0x54013 + i);
+		cdd_cha[i * 2] = tmp & 0xff;
+		cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff;
+	}
+
+	for (i = 0; i < 7; i++) {
+		tmp = dwc_ddrphy_apb_rd(0x5402c + i);
+
+		if (i == 0) {
+			cdd_chb[0] = (tmp >> 8) & 0xff;
+		} else if (i == 6) {
+			cdd_chb[11] = tmp & 0xff;
+		} else {
+			cdd_chb[i * 2 - 1] = tmp & 0xff;
+			cdd_chb[i * 2] = (tmp >> 8) & 0xff;
+		}
+	}
+
+	cdd_cha_rr_max = look_for_max(cdd_cha, 0, 1);
+	cdd_cha_rw_max = look_for_max(cdd_cha, 2, 5);
+	cdd_cha_wr_max = look_for_max(cdd_cha, 6, 9);
+	cdd_cha_ww_max = look_for_max(cdd_cha, 10, 11);
+	cdd_chb_rr_max = look_for_max(cdd_chb, 0, 1);
+	cdd_chb_rw_max = look_for_max(cdd_chb, 2, 5);
+	cdd_chb_wr_max = look_for_max(cdd_chb, 6, 9);
+	cdd_chb_ww_max = look_for_max(cdd_chb, 10, 11);
+	g_cdd_rr_max[fsp] =  cdd_cha_rr_max > cdd_chb_rr_max ? cdd_cha_rr_max : cdd_chb_rr_max;
+	g_cdd_rw_max[fsp] =  cdd_cha_rw_max > cdd_chb_rw_max ? cdd_cha_rw_max : cdd_chb_rw_max;
+	g_cdd_wr_max[fsp] =  cdd_cha_wr_max > cdd_chb_wr_max ? cdd_cha_wr_max : cdd_chb_wr_max;
+	g_cdd_ww_max[fsp] =  cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max;
+}
+
+void update_umctl2_rank_space_setting(unsigned int pstat_num)
+{
+	u32 tmp, tmp_t;
+
+	int wwt, rrt, wrt, rwt;
+	int ext_wwt, ext_rrt, ext_wrt, ext_rwt;
+	int max_wwt, max_rrt, max_wrt, max_rwt;
+
+	/* read wwt, rrt, wrt, rwt fields from timing_cfg_0 */
+	tmp = readl(REG_DDR_TIMING_CFG_0);
+	wwt = (tmp >> 24) & 0x3;
+	rrt = (tmp >> 26) & 0x3;
+	wrt = (tmp >> 28) & 0x3;
+	rwt = (tmp >> 30) & 0x3;
+
+	/* read rxt_wwt, ext_rrt, ext_wrt, ext_rwt fields from timing_cfg_4 */
+	tmp_t = readl(REG_DDR_TIMING_CFG_4);
+	ext_wwt = (tmp >> 8) & 0x1;
+	ext_rrt = (tmp >> 10) & 0x1;
+	ext_wrt = (tmp >> 12) & 0x1;
+	ext_rwt = (tmp >> 14) & 0x3;
+
+	wwt = (ext_wwt << 2) | wwt;
+	rrt = (ext_rrt << 2) | wwt;
+	wrt = (ext_wrt << 2) | wrt;
+	rwt = (ext_rwt << 2) | rwt;
+
+	/* calculate the maximum between controller and cdd values */
+	max_wwt = MAX(g_cdd_ww_max[0], wwt);
+	max_rrt = MAX(g_cdd_rr_max[0], rrt);
+	max_wrt = MAX(g_cdd_wr_max[0], wrt);
+	max_rwt = MAX(g_cdd_rw_max[0], rwt);
+
+	/* verify values to see if are bigger then 7 or 15 (3 bits or 4 bits) */
+	if (max_wwt > 7)
+		max_wwt = 7;
+	if (max_rrt > 7)
+		max_rrt = 7;
+	if (max_wrt > 7)
+		max_wrt = 7;
+	if (max_rwt > 15)
+		max_rwt = 15;
+
+	/* recalculate timings for controller registers */
+	wwt = max_wwt & 0x3;
+	rrt = max_rrt & 0x3;
+	wrt = max_wrt & 0x3;
+	rwt = max_rwt & 0x3;
+
+	ext_wwt = (max_wwt & 0x4) >> 2;
+	ext_rrt = (max_rrt & 0x4) >> 2;
+	ext_wrt = (max_wrt & 0x4) >> 2;
+	ext_rwt = (max_rwt & 0xC) >> 2;
+
+	/* update timing_cfg_0 and timing_cfg_4 */
+	tmp = (tmp & 0x00ffffff) | (rwt << 30) | (wrt << 28) |
+		(rrt << 26) | (wwt << 24);
+	writel(tmp, REG_DDR_TIMING_CFG_0);
+
+	tmp_t = (tmp_t & 0xFFFF2AFF) | (ext_rwt << 14) |
+		(ext_wrt << 12) | (ext_rrt << 10) | (ext_wwt << 8);
+	writel(tmp_t, REG_DDR_TIMING_CFG_4);
+}
+
+int ddr_init(struct dram_timing_info *dram_timing)
+{
+	unsigned int initial_drate;
+	int ret;
+	u32 regval;
+
+	debug("DDRINFO: start DRAM init\n");
+
+	/* reset ddrphy */
+	ddrphy_coldreset();
+
+	debug("DDRINFO: cfg clk\n");
+
+	initial_drate = dram_timing->fsp_msg[0].drate;
+	/* default to the frequency point 0 clock */
+	ddrphy_init_set_dfi_clk(initial_drate);
+
+	/*
+	 * Start PHY initialization and training by
+	 * accessing relevant PUB registers
+	 */
+	debug("DDRINFO:ddrphy config start\n");
+
+	ret = ddr_cfg_phy(dram_timing);
+	if (ret)
+		return ret;
+
+	debug("DDRINFO: ddrphy config done\n");
+
+	/* rogram the ddrc registers */
+	debug("DDRINFO: ddrc config start\n");
+	ddrc_config(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
+	debug("DDRINFO: ddrc config done\n");
+
+	update_umctl2_rank_space_setting(dram_timing->fsp_msg_num - 1);
+
+#ifdef CONFIG_IMX9_DRAM_PM_COUNTER
+	writel(0x200000, REG_DDR_DEBUG_19);
+#endif
+
+	check_dfi_init_complete();
+
+	regval=readl(REG_DDR_SDRAM_CFG);
+	writel((regval|0x80000000), REG_DDR_SDRAM_CFG);
+
+	check_ddrc_idle();
+
+	/* save the dram timing config into memory */
+	dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
+
+	return 0;
+}
+
+ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr)
+{
+	uint32_t paddr_apb_qual;
+	uint32_t paddr_apb_unqual_dec_22_13;
+	uint32_t paddr_apb_unqual_dec_19_13;
+	uint32_t paddr_apb_unqual_dec_12_1;
+	uint32_t paddr_apb_unqual;
+	uint32_t paddr_apb_phy;
+
+	paddr_apb_qual = (paddr_apb_from_ctlr << 1);
+	paddr_apb_unqual_dec_22_13 = ((paddr_apb_qual & 0x7fe000) >> 13);
+	paddr_apb_unqual_dec_12_1  = ((paddr_apb_qual & 0x1ffe) >> 1);
+
+	switch(paddr_apb_unqual_dec_22_13) {
+		case 0x000 : paddr_apb_unqual_dec_19_13 = 0x00;break;
+		case 0x001 : paddr_apb_unqual_dec_19_13 = 0x01;break;
+		case 0x002 : paddr_apb_unqual_dec_19_13 = 0x02;break;
+		case 0x003 : paddr_apb_unqual_dec_19_13 = 0x03;break;
+		case 0x004 : paddr_apb_unqual_dec_19_13 = 0x04;break;
+		case 0x005 : paddr_apb_unqual_dec_19_13 = 0x05;break;
+		case 0x006 : paddr_apb_unqual_dec_19_13 = 0x06;break;
+		case 0x007 : paddr_apb_unqual_dec_19_13 = 0x07;break;
+		case 0x008 : paddr_apb_unqual_dec_19_13 = 0x08;break;
+		case 0x009 : paddr_apb_unqual_dec_19_13 = 0x09;break;
+		case 0x00a : paddr_apb_unqual_dec_19_13 = 0x0a;break;
+		case 0x00b : paddr_apb_unqual_dec_19_13 = 0x0b;break;
+		case 0x100 : paddr_apb_unqual_dec_19_13 = 0x0c;break;
+		case 0x101 : paddr_apb_unqual_dec_19_13 = 0x0d;break;
+		case 0x102 : paddr_apb_unqual_dec_19_13 = 0x0e;break;
+		case 0x103 : paddr_apb_unqual_dec_19_13 = 0x0f;break;
+		case 0x104 : paddr_apb_unqual_dec_19_13 = 0x10;break;
+		case 0x105 : paddr_apb_unqual_dec_19_13 = 0x11;break;
+		case 0x106 : paddr_apb_unqual_dec_19_13 = 0x12;break;
+		case 0x107 : paddr_apb_unqual_dec_19_13 = 0x13;break;
+		case 0x108 : paddr_apb_unqual_dec_19_13 = 0x14;break;
+		case 0x109 : paddr_apb_unqual_dec_19_13 = 0x15;break;
+		case 0x10a : paddr_apb_unqual_dec_19_13 = 0x16;break;
+		case 0x10b : paddr_apb_unqual_dec_19_13 = 0x17;break;
+		case 0x200 : paddr_apb_unqual_dec_19_13 = 0x18;break;
+		case 0x201 : paddr_apb_unqual_dec_19_13 = 0x19;break;
+		case 0x202 : paddr_apb_unqual_dec_19_13 = 0x1a;break;
+		case 0x203 : paddr_apb_unqual_dec_19_13 = 0x1b;break;
+		case 0x204 : paddr_apb_unqual_dec_19_13 = 0x1c;break;
+		case 0x205 : paddr_apb_unqual_dec_19_13 = 0x1d;break;
+		case 0x206 : paddr_apb_unqual_dec_19_13 = 0x1e;break;
+		case 0x207 : paddr_apb_unqual_dec_19_13 = 0x1f;break;
+		case 0x208 : paddr_apb_unqual_dec_19_13 = 0x20;break;
+		case 0x209 : paddr_apb_unqual_dec_19_13 = 0x21;break;
+		case 0x20a : paddr_apb_unqual_dec_19_13 = 0x22;break;
+		case 0x20b : paddr_apb_unqual_dec_19_13 = 0x23;break;
+		case 0x300 : paddr_apb_unqual_dec_19_13 = 0x24;break;
+		case 0x301 : paddr_apb_unqual_dec_19_13 = 0x25;break;
+		case 0x302 : paddr_apb_unqual_dec_19_13 = 0x26;break;
+		case 0x303 : paddr_apb_unqual_dec_19_13 = 0x27;break;
+		case 0x304 : paddr_apb_unqual_dec_19_13 = 0x28;break;
+		case 0x305 : paddr_apb_unqual_dec_19_13 = 0x29;break;
+		case 0x306 : paddr_apb_unqual_dec_19_13 = 0x2a;break;
+		case 0x307 : paddr_apb_unqual_dec_19_13 = 0x2b;break;
+		case 0x308 : paddr_apb_unqual_dec_19_13 = 0x2c;break;
+		case 0x309 : paddr_apb_unqual_dec_19_13 = 0x2d;break;
+		case 0x30a : paddr_apb_unqual_dec_19_13 = 0x2e;break;
+		case 0x30b : paddr_apb_unqual_dec_19_13 = 0x2f;break;
+		case 0x010 : paddr_apb_unqual_dec_19_13 = 0x30;break;
+		case 0x011 : paddr_apb_unqual_dec_19_13 = 0x31;break;
+		case 0x012 : paddr_apb_unqual_dec_19_13 = 0x32;break;
+		case 0x013 : paddr_apb_unqual_dec_19_13 = 0x33;break;
+		case 0x014 : paddr_apb_unqual_dec_19_13 = 0x34;break;
+		case 0x015 : paddr_apb_unqual_dec_19_13 = 0x35;break;
+		case 0x016 : paddr_apb_unqual_dec_19_13 = 0x36;break;
+		case 0x017 : paddr_apb_unqual_dec_19_13 = 0x37;break;
+		case 0x018 : paddr_apb_unqual_dec_19_13 = 0x38;break;
+		case 0x019 : paddr_apb_unqual_dec_19_13 = 0x39;break;
+		case 0x110 : paddr_apb_unqual_dec_19_13 = 0x3a;break;
+		case 0x111 : paddr_apb_unqual_dec_19_13 = 0x3b;break;
+		case 0x112 : paddr_apb_unqual_dec_19_13 = 0x3c;break;
+		case 0x113 : paddr_apb_unqual_dec_19_13 = 0x3d;break;
+		case 0x114 : paddr_apb_unqual_dec_19_13 = 0x3e;break;
+		case 0x115 : paddr_apb_unqual_dec_19_13 = 0x3f;break;
+		case 0x116 : paddr_apb_unqual_dec_19_13 = 0x40;break;
+		case 0x117 : paddr_apb_unqual_dec_19_13 = 0x41;break;
+		case 0x118 : paddr_apb_unqual_dec_19_13 = 0x42;break;
+		case 0x119 : paddr_apb_unqual_dec_19_13 = 0x43;break;
+		case 0x210 : paddr_apb_unqual_dec_19_13 = 0x44;break;
+		case 0x211 : paddr_apb_unqual_dec_19_13 = 0x45;break;
+		case 0x212 : paddr_apb_unqual_dec_19_13 = 0x46;break;
+		case 0x213 : paddr_apb_unqual_dec_19_13 = 0x47;break;
+		case 0x214 : paddr_apb_unqual_dec_19_13 = 0x48;break;
+		case 0x215 : paddr_apb_unqual_dec_19_13 = 0x49;break;
+		case 0x216 : paddr_apb_unqual_dec_19_13 = 0x4a;break;
+		case 0x217 : paddr_apb_unqual_dec_19_13 = 0x4b;break;
+		case 0x218 : paddr_apb_unqual_dec_19_13 = 0x4c;break;
+		case 0x219 : paddr_apb_unqual_dec_19_13 = 0x4d;break;
+		case 0x310 : paddr_apb_unqual_dec_19_13 = 0x4e;break;
+		case 0x311 : paddr_apb_unqual_dec_19_13 = 0x4f;break;
+		case 0x312 : paddr_apb_unqual_dec_19_13 = 0x50;break;
+		case 0x313 : paddr_apb_unqual_dec_19_13 = 0x51;break;
+		case 0x314 : paddr_apb_unqual_dec_19_13 = 0x52;break;
+		case 0x315 : paddr_apb_unqual_dec_19_13 = 0x53;break;
+		case 0x316 : paddr_apb_unqual_dec_19_13 = 0x54;break;
+		case 0x317 : paddr_apb_unqual_dec_19_13 = 0x55;break;
+		case 0x318 : paddr_apb_unqual_dec_19_13 = 0x56;break;
+		case 0x319 : paddr_apb_unqual_dec_19_13 = 0x57;break;
+		case 0x020 : paddr_apb_unqual_dec_19_13 = 0x58;break;
+		case 0x120 : paddr_apb_unqual_dec_19_13 = 0x59;break;
+		case 0x220 : paddr_apb_unqual_dec_19_13 = 0x5a;break;
+		case 0x320 : paddr_apb_unqual_dec_19_13 = 0x5b;break;
+		case 0x040 : paddr_apb_unqual_dec_19_13 = 0x5c;break;
+		case 0x140 : paddr_apb_unqual_dec_19_13 = 0x5d;break;
+		case 0x240 : paddr_apb_unqual_dec_19_13 = 0x5e;break;
+		case 0x340 : paddr_apb_unqual_dec_19_13 = 0x5f;break;
+		case 0x050 : paddr_apb_unqual_dec_19_13 = 0x60;break;
+		case 0x051 : paddr_apb_unqual_dec_19_13 = 0x61;break;
+		case 0x052 : paddr_apb_unqual_dec_19_13 = 0x62;break;
+		case 0x053 : paddr_apb_unqual_dec_19_13 = 0x63;break;
+		case 0x054 : paddr_apb_unqual_dec_19_13 = 0x64;break;
+		case 0x055 : paddr_apb_unqual_dec_19_13 = 0x65;break;
+		case 0x056 : paddr_apb_unqual_dec_19_13 = 0x66;break;
+		case 0x057 : paddr_apb_unqual_dec_19_13 = 0x67;break;
+		case 0x070 : paddr_apb_unqual_dec_19_13 = 0x68;break;
+		case 0x090 : paddr_apb_unqual_dec_19_13 = 0x69;break;
+		case 0x190 : paddr_apb_unqual_dec_19_13 = 0x6a;break;
+		case 0x290 : paddr_apb_unqual_dec_19_13 = 0x6b;break;
+		case 0x390 : paddr_apb_unqual_dec_19_13 = 0x6c;break;
+		case 0x0c0 : paddr_apb_unqual_dec_19_13 = 0x6d;break;
+		case 0x0d0 : paddr_apb_unqual_dec_19_13 = 0x6e;break;
+		default    : paddr_apb_unqual_dec_19_13 = 0x00;
+	}
+
+	paddr_apb_unqual = ((paddr_apb_unqual_dec_19_13 << 13) | (paddr_apb_unqual_dec_12_1 << 1));
+
+	paddr_apb_phy = (paddr_apb_unqual << 1);
+
+	return paddr_apb_phy;
+}
diff --git a/drivers/ddr/imx/phy/Kconfig b/drivers/ddr/imx/phy/Kconfig
new file mode 100644
index 00000000000..d3e589b23c4
--- /dev/null
+++ b/drivers/ddr/imx/phy/Kconfig
@@ -0,0 +1,4 @@
+config IMX_SNPS_DDR_PHY
+	bool "i.MX Snopsys DDR PHY"
+	help
+	  Select the DDR PHY driver support on i.MX8M and i.MX9 SOC.
diff --git a/drivers/ddr/imx/phy/Makefile b/drivers/ddr/imx/phy/Makefile
new file mode 100644
index 00000000000..bb3d4ee5b74
--- /dev/null
+++ b/drivers/ddr/imx/phy/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_IMX_SNPS_DDR_PHY) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o
+endif
diff --git a/drivers/ddr/imx/imx8m/ddrphy_csr.c b/drivers/ddr/imx/phy/ddrphy_csr.c
index 67dd4e7059f..67dd4e7059f 100644
--- a/drivers/ddr/imx/imx8m/ddrphy_csr.c
+++ b/drivers/ddr/imx/phy/ddrphy_csr.c
diff --git a/drivers/ddr/imx/imx8m/ddrphy_train.c b/drivers/ddr/imx/phy/ddrphy_train.c
index 08fed6178f3..cd905f952c6 100644
--- a/drivers/ddr/imx/imx8m/ddrphy_train.c
+++ b/drivers/ddr/imx/phy/ddrphy_train.c
@@ -7,7 +7,6 @@
 #include <log.h>
 #include <linux/kernel.h>
 #include <asm/arch/ddr.h>
-#include <asm/arch/lpddr4_define.h>
 #include <asm/arch/sys_proto.h>
 
 int ddr_cfg_phy(struct dram_timing_info *dram_timing)
diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c
new file mode 100644
index 00000000000..b852c870f90
--- /dev/null
+++ b/drivers/ddr/imx/phy/ddrphy_utils.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/sys_proto.h>
+
+static inline void poll_pmu_message_ready(void)
+{
+	unsigned int reg;
+
+	do {
+		reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004));
+	} while (reg & 0x1);
+}
+
+static inline void ack_pmu_message_receive(void)
+{
+	unsigned int reg;
+
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x0);
+
+	do {
+		reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004));
+	} while (!(reg & 0x1));
+
+	reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x1);
+}
+
+static inline unsigned int get_mail(void)
+{
+	unsigned int reg;
+
+	poll_pmu_message_ready();
+
+	reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032));
+
+	ack_pmu_message_receive();
+
+	return reg;
+}
+
+static inline unsigned int get_stream_message(void)
+{
+	unsigned int reg, reg2;
+
+	poll_pmu_message_ready();
+
+	reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032));
+
+	reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0034));
+
+	reg2 = (reg2 << 16) | reg;
+
+	ack_pmu_message_receive();
+
+	return reg2;
+}
+
+static inline void decode_major_message(unsigned int mail)
+{
+	debug("[PMU Major message = 0x%08x]\n", mail);
+}
+
+static inline void decode_streaming_message(void)
+{
+	unsigned int string_index, arg __maybe_unused;
+	int i = 0;
+
+	string_index = get_stream_message();
+	debug("PMU String index = 0x%08x\n", string_index);
+	while (i < (string_index & 0xffff)) {
+		arg = get_stream_message();
+		debug("arg[%d] = 0x%08x\n", i, arg);
+		i++;
+	}
+
+	debug("\n");
+}
+
+int wait_ddrphy_training_complete(void)
+{
+	unsigned int mail;
+
+	while (1) {
+		mail = get_mail();
+		decode_major_message(mail);
+		if (mail == 0x08) {
+			decode_streaming_message();
+		} else if (mail == 0x07) {
+			debug("Training PASS\n");
+			return 0;
+		} else if (mail == 0xff) {
+			printf("Training FAILED\n");
+			return -1;
+		}
+	}
+}
+
+void ddrphy_init_set_dfi_clk(unsigned int drate)
+{
+	switch (drate) {
+	case 4000:
+		dram_pll_init(MHZ(1000));
+		dram_disable_bypass();
+		break;
+	case 3733:
+		dram_pll_init(MHZ(933));
+		dram_disable_bypass();
+		break;
+	case 3200:
+		dram_pll_init(MHZ(800));
+		dram_disable_bypass();
+		break;
+	case 3000:
+		dram_pll_init(MHZ(750));
+		dram_disable_bypass();
+		break;
+	case 2800:
+		dram_pll_init(MHZ(700));
+		dram_disable_bypass();
+		break;
+	case 2400:
+		dram_pll_init(MHZ(600));
+		dram_disable_bypass();
+		break;
+	case 1866:
+		dram_pll_init(MHZ(466));
+		dram_disable_bypass();
+		break;
+	case 1600:
+		dram_pll_init(MHZ(400));
+		dram_disable_bypass();
+		break;
+	case 1066:
+		dram_pll_init(MHZ(266));
+		dram_disable_bypass();
+		break;
+	case 667:
+		dram_pll_init(MHZ(167));
+		dram_disable_bypass();
+		break;
+	case 400:
+		dram_enable_bypass(MHZ(400));
+		break;
+	case 333:
+		dram_enable_bypass(MHZ(333));
+		break;
+	case 200:
+		dram_enable_bypass(MHZ(200));
+		break;
+	case 100:
+		dram_enable_bypass(MHZ(100));
+		break;
+	default:
+		return;
+	}
+}
+
+void ddrphy_init_read_msg_block(enum fw_type type)
+{
+}
diff --git a/drivers/ddr/imx/imx8m/helper.c b/drivers/ddr/imx/phy/helper.c
index f23904bf712..43b40a8029c 100644
--- a/drivers/ddr/imx/imx8m/helper.c
+++ b/drivers/ddr/imx/phy/helper.c
@@ -12,7 +12,6 @@
 #include <asm/io.h>
 #include <asm/arch/ddr.h>
 #include <asm/arch/ddr.h>
-#include <asm/arch/lpddr4_define.h>
 #include <asm/sections.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -46,43 +45,43 @@ void ddr_load_train_firmware(enum fw_type type)
 	dmem_start = imem_start + IMEM_LEN;
 
 	pr_from32 = imem_start;
-	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+	pr_to32 = IMEM_OFFSET_ADDR;
 	for (i = 0x0; i < IMEM_LEN; ) {
 		tmp32 = readl(pr_from32);
-		writew(tmp32 & 0x0000ffff, pr_to32);
-		pr_to32 += 4;
-		writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
-		pr_to32 += 4;
+		writew(tmp32 & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32));
+		pr_to32 += 1;
+		writew((tmp32 >> 16) & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32));
+		pr_to32 += 1;
 		pr_from32 += 4;
 		i += 4;
 	}
 
 	pr_from32 = dmem_start;
-	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+	pr_to32 = DMEM_OFFSET_ADDR;
 	for (i = 0x0; i < DMEM_LEN; ) {
 		tmp32 = readl(pr_from32);
-		writew(tmp32 & 0x0000ffff, pr_to32);
-		pr_to32 += 4;
-		writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
-		pr_to32 += 4;
+		writew(tmp32 & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32));
+		pr_to32 += 1;
+		writew((tmp32 >> 16) & 0x0000ffff, DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32));
+		pr_to32 += 1;
 		pr_from32 += 4;
 		i += 4;
 	}
 
 	debug("check ddr_pmu_train_imem code\n");
 	pr_from32 = imem_start;
-	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+	pr_to32 = IMEM_OFFSET_ADDR;
 	for (i = 0x0; i < IMEM_LEN; ) {
-		tmp32 = (readw(pr_to32) & 0x0000ffff);
-		pr_to32 += 4;
-		tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+		tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff);
+		pr_to32 += 1;
+		tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff) << 16);
 
 		if (tmp32 != readl(pr_from32)) {
 			debug("%lx %lx\n", pr_from32, pr_to32);
 			error++;
 		}
 		pr_from32 += 4;
-		pr_to32 += 4;
+		pr_to32 += 1;
 		i += 4;
 	}
 	if (error)
@@ -92,17 +91,17 @@ void ddr_load_train_firmware(enum fw_type type)
 
 	debug("check ddr4_pmu_train_dmem code\n");
 	pr_from32 = dmem_start;
-	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+	pr_to32 = DMEM_OFFSET_ADDR;
 	for (i = 0x0; i < DMEM_LEN;) {
-		tmp32 = (readw(pr_to32) & 0x0000ffff);
-		pr_to32 += 4;
-		tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+		tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff);
+		pr_to32 += 1;
+		tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR + ddrphy_addr_remap(pr_to32)) & 0x0000ffff) << 16);
 		if (tmp32 != readl(pr_from32)) {
 			debug("%lx %lx\n", pr_from32, pr_to32);
 			error++;
 		}
 		pr_from32 += 4;
-		pr_to32 += 4;
+		pr_to32 += 1;
 		i += 4;
 	}
 
diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index da988f6bb66..bccb501d84b 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -129,10 +129,10 @@ static int mxs_dma_enable(int channel)
 		return 0;
 	}
 
-	pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node);
-	if (pdesc == NULL)
+	if (list_empty(&pchan->active))
 		return -EFAULT;
 
+	pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node);
 	if (pchan->flags & MXS_DMA_FLAGS_BUSY) {
 		if (!(pdesc->cmd.data & MXS_DMA_DESC_CHAIN))
 			return 0;
@@ -578,6 +578,14 @@ void mxs_dma_init(void)
 	struct mxs_apbh_regs *apbh_regs =
 		(struct mxs_apbh_regs *)MXS_APBH_BASE;
 
+	if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
+		if (check_module_fused(MODULE_APBHDMA)) {
+			printf("NAND APBH-DMA@0x%x is fused, disable it\n",
+				MXS_APBH_BASE);
+			return;
+		}
+	}
+
 	mxs_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);
 
 #ifdef CONFIG_APBH_DMA_BURST8
diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
index b97c67bf609..f38f847d4b0 100644
--- a/drivers/fastboot/Kconfig
+++ b/drivers/fastboot/Kconfig
@@ -11,6 +11,7 @@ config USB_FUNCTION_FASTBOOT
 	default y if ARCH_SUNXI && USB_MUSB_GADGET
 	select FASTBOOT
 	select USB_GADGET_DOWNLOAD
+	select USB_GADGET_OS_DESCRIPTORS
 	help
 	  This enables the USB part of the fastboot gadget.
 
@@ -81,15 +82,63 @@ config FASTBOOT_FLASH
 
 config FASTBOOT_UUU_SUPPORT
 	bool "Enable FASTBOOT i.MX UUU special command"
+	default y if ARCH_MX7 || ARCH_MX6 || ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7ULP
+	select FSL_FASTBOOT
+	select FAT_WRITE
+	select CMD_GPT
+	select RANDOM_UUID
+	select CMD_GPT_RENAME
+	select CONSOLE_MUX
+	select SYS_STDIO_DEREGISTER
 	help
 	  The fastboot protocol includes "UCmd" and "ACmd" command.
 	  Be aware that you provide full access to any U-Boot command,
 	  including working with memory and may open a huge backdoor,
 	  when enabling this option.
 
+config FSL_FASTBOOT
+	bool "Enable FSL fastboot support"
+	depends on FASTBOOT_FLASH
+	help
+	  This enables FSL implementation for Android fastboot.
+
+config ANDROID_RECOVERY
+	bool "Enable the recovery boot function"
+	depends on FSL_FASTBOOT
+	help
+	  This enables the Android Recovery boot function.
+
+config CMD_BOOTA
+	bool "Enable the boota command"
+	default y
+	depends on FSL_FASTBOOT
+	depends on ANDROID_SUPPORT || ANDROID_AUTO_SUPPORT || ANDROID_THINGS_SUPPORT
+	help
+	  This enables the boota command for booting android images.
+
+config BCB_SUPPORT
+	bool "Enable the boot control block support"
+	depends on FSL_FASTBOOT
+	help
+	  This enables the boot control block support for android reboot command
+
+config FASTBOOT_LOCK
+	bool "Enable the lock and unlock feature to the partitions"
+	depends on FSL_FASTBOOT
+	help
+	  This enables the lock support for android flashing command
+
+config FASTBOOT_USB_DEV
+	int "USB controller number"
+	default 0
+	help
+	  Some boards have USB OTG controller other than 0. Define this
+	  option so it can be used in compiled environment (e.g. in
+	  CONFIG_BOOTCOMMAND).
+
 choice
 	prompt "Flash provider for FASTBOOT"
-	depends on FASTBOOT_FLASH
+	depends on FASTBOOT_FLASH && !FSL_FASTBOOT
 
 config FASTBOOT_FLASH_MMC
 	bool "FASTBOOT on MMC"
diff --git a/drivers/fastboot/Makefile b/drivers/fastboot/Makefile
index 048af5aa823..902da22e67e 100644
--- a/drivers/fastboot/Makefile
+++ b/drivers/fastboot/Makefile
@@ -1,7 +1,11 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 obj-y += fb_common.o
-obj-y += fb_getvar.o
+ifndef CONFIG_FSL_FASTBOOT
 obj-y += fb_command.o
+obj-y += fb_getvar.o
 obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fb_mmc.o
 obj-$(CONFIG_FASTBOOT_FLASH_NAND) += fb_nand.o
+else
+obj-y += fb_fsl/
+endif
diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c
index ef399d0c4ab..71f149e64ae 100644
--- a/drivers/fastboot/fb_common.c
+++ b/drivers/fastboot/fb_common.c
@@ -16,6 +16,7 @@
 #include <env.h>
 #include <fastboot.h>
 #include <net/fastboot.h>
+#include <image.h>
 
 /**
  * fastboot_buf_addr - base address of the fastboot download buffer
@@ -136,12 +137,22 @@ void fastboot_boot(void)
 		run_command(s, CMD_FLAG_ENV);
 	} else {
 		static char boot_addr_start[20];
+#ifdef CONFIG_FSL_FASTBOOT
+		static char *const bootm_args[] = {
+			"boota", boot_addr_start, NULL
+		};
+
+		snprintf(boot_addr_start, sizeof(boot_addr_start) - 1,
+			 "0x%p", (void *)image_load_addr);
+#else
 		static char *const bootm_args[] = {
 			"bootm", boot_addr_start, NULL
 		};
 
 		snprintf(boot_addr_start, sizeof(boot_addr_start) - 1,
 			 "0x%p", fastboot_buf_addr);
+#endif
+
 		printf("Booting kernel at %s...\n\n\n", boot_addr_start);
 
 		do_bootm(NULL, 0, 2, bootm_args);
@@ -178,8 +189,13 @@ void fastboot_set_progress_callback(void (*progress)(const char *msg))
  */
 void fastboot_init(void *buf_addr, u32 buf_size)
 {
+#ifdef CONFIG_FSL_FASTBOOT
+	fastboot_buf_addr = buf_addr ? buf_addr :
+				       (void *)env_get_ulong("fastboot_buffer", 16, CONFIG_FASTBOOT_BUF_ADDR);
+#else
 	fastboot_buf_addr = buf_addr ? buf_addr :
 				       (void *)CONFIG_FASTBOOT_BUF_ADDR;
+#endif
 	fastboot_buf_size = buf_size ? buf_size : CONFIG_FASTBOOT_BUF_SIZE;
 	fastboot_set_progress_callback(NULL);
 }
diff --git a/drivers/fastboot/fb_fsl/Makefile b/drivers/fastboot/fb_fsl/Makefile
new file mode 100644
index 00000000000..6a88aee1809
--- /dev/null
+++ b/drivers/fastboot/fb_fsl/Makefile
@@ -0,0 +1,14 @@
+#
+# Copyright 2019 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ccflags-y += -I./lib
+
+ifndef CONFIG_SPL_BUILD
+obj-y += fb_fsl_dev.o fb_fsl_boot.o fb_fsl_command.o fb_fsl_common.o fb_fsl_getvar.o fb_fsl_partitions.o
+obj-$(CONFIG_FASTBOOT_LOCK) += fastboot_lock_unlock.o
+obj-$(CONFIG_BCB_SUPPORT) += command.o bcb.o
+obj-$(CONFIG_VIRTUAL_AB_SUPPORT) += fb_fsl_virtual_ab.o
+endif
diff --git a/drivers/fastboot/fb_fsl/bcb.c b/drivers/fastboot/fb_fsl/bcb.c
new file mode 100644
index 00000000000..7226790ad72
--- /dev/null
+++ b/drivers/fastboot/fb_fsl/bcb.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier:     GPL-2.0+
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ */
+
+#include <fb_fsl.h>
+#include <linux/stat.h>
+#include <linux/types.h>
+#include <common.h>
+#include <g_dnl.h>
+#include <mmc.h>
+#include "bcb.h"
+#include "command.h"
+#define ALIGN_BYTES 64 /*armv7 cache line need 64 bytes aligned */
+
+static ulong get_block_size(char *ifname, int dev)
+{
+	struct blk_desc *dev_desc = NULL;
+
+	dev_desc = blk_get_dev(ifname, dev);
+	if (dev_desc == NULL) {
+		printf("Block device %s %d not supported\n", ifname, dev);
+		return 0;
+	}
+
+	return dev_desc->blksz;
+}
+
+static int do_write(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+	char *ep;
+	struct blk_desc *dev_desc = NULL;
+	int dev;
+	int part = 0;
+	struct disk_partition part_info;
+	ulong offset = 0u;
+	ulong limit = 0u;
+	void *addr;
+	uint blk;
+	uint cnt;
+
+	if (argc != 6) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	dev = (int)simple_strtoul(argv[2], &ep, 16);
+	if (*ep) {
+		if (*ep != ':') {
+			printf("Invalid block device %s\n", argv[2]);
+			return 1;
+		}
+		part = (int)simple_strtoul(++ep, NULL, 16);
+	}
+
+	dev_desc = blk_get_dev(argv[1], dev);
+	if (dev_desc == NULL) {
+		printf("Block device %s %d not supported\n", argv[1], dev);
+		return 1;
+	}
+
+	addr = (void *)simple_strtoul(argv[3], NULL, 16);
+	blk = simple_strtoul(argv[4], NULL, 16);
+	cnt = simple_strtoul(argv[5], NULL, 16);
+
+	if (part != 0) {
+		if (part_get_info(dev_desc, part, &part_info)) {
+			printf("Cannot find partition %d\n", part);
+			return 1;
+		}
+		offset = part_info.start;
+		limit = part_info.size;
+	} else {
+		/* Largest address not available in block_dev_desc_t. */
+		limit = ~0;
+	}
+
+	if (cnt + blk > limit) {
+		printf("Write out of range\n");
+		return 1;
+	}
+
+	if (blk_dwrite(dev_desc, offset + blk, cnt, addr) != cnt) {
+		printf("Error writing blocks\n");
+		return 1;
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	write,	6,	0,	do_write,
+	"write binary data to a partition",
+	"<interface> <dev[:part]> addr blk# cnt"
+);
+
+int bcb_rw_block(bool bread, char **ppblock,
+		uint *pblksize, char *pblock_write, uint offset, uint size)
+{
+	int ret;
+	char *argv[6];
+	char addr_str[20];
+	char cnt_str[8];
+	char devpart_str[8];
+	char block_begin_str[8];
+	ulong blk_size = 0;
+	uint blk_begin = 0;
+	uint blk_end = 0;
+	uint block_cnt = 0;
+	char *p_block = NULL;
+	unsigned int mmc_id;
+
+	if (bread && ((ppblock == NULL) || (pblksize == NULL)))
+		return -1;
+
+	if (!bread && (pblock_write == NULL))
+		return -1;
+
+	mmc_id = mmc_get_env_dev();
+	blk_size = get_block_size("mmc", mmc_id);
+	if (blk_size == 0) {
+		printf("bcb_rw_block, get_block_size return 0\n");
+		return -1;
+	}
+
+	blk_begin = offset/blk_size;
+	blk_end = (offset + size)/blk_size;
+	block_cnt = 1 + (blk_end - blk_begin);
+
+	sprintf(devpart_str, "0x%x:0x%x", mmc_id,
+			fastboot_flash_find_index(FASTBOOT_PARTITION_MISC));
+	sprintf(block_begin_str, "0x%x", blk_begin);
+	sprintf(cnt_str, "0x%x", block_cnt);
+
+	argv[0] = "rw"; /* not care */
+	argv[1] = "mmc";
+	argv[2] = devpart_str;
+	argv[3] = addr_str;
+	argv[4] = block_begin_str;
+	argv[5] = cnt_str;
+
+	if (bread) {
+		p_block = (char *)memalign(ALIGN_BYTES, blk_size * block_cnt);
+		if (NULL == p_block) {
+			printf("bcb_rw_block, memalign %d bytes failed\n",
+			(int)(blk_size * block_cnt));
+			return -1;
+		}
+		sprintf(addr_str, "0x%x", (unsigned int)(uintptr_t)p_block);
+		ret = do_raw_read(NULL, 0, 6, argv);
+		if (ret) {
+			free(p_block);
+			printf("do_raw_read failed, ret %d\n", ret);
+			return -1;
+		}
+
+		*ppblock = p_block;
+		*pblksize = (uint)blk_size;
+	} else {
+		sprintf(addr_str, "0x%x", (unsigned int)(uintptr_t)pblock_write);
+		ret = do_write(NULL, 0, 6, argv);
+		if (ret) {
+			printf("do_write failed, ret %d\n", ret);
+			return -1;
+		}
+	}
+	return 0;
+}
diff --git a/drivers/fastboot/fb_fsl/bcb.h b/drivers/fastboot/fb_fsl/bcb.h
new file mode 100644
index 00000000000..3b72eb15d14
--- /dev/null
+++ b/drivers/fastboot/fb_fsl/bcb.h
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier:     GPL-2.0+
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ */
+
+#ifndef BCB_H
+#define BCB_H
+#include <linux/types.h>
+#include <linux/stat.h>
+#include <android_bootloader_message.h>
+
+#define FASTBOOT_BCB_CMD "bootonce-bootloader"
+#ifdef CONFIG_ANDROID_RECOVERY
+#define RECOVERY_BCB_CMD "boot-recovery"
+#define RECOVERY_FASTBOOT_ARG "recovery\n--fastboot"
+#endif
+
+/* bcb struct is defined in include/android_bootloader_message.h */
+
+/* start from bootloader_message_ab.slot_suffix[BOOTCTRL_IDX] */
+#define BOOTCTRL_IDX                            0
+#define MISC_COMMAND_IDX                        0
+#define BOOTCTRL_OFFSET         \
+	(u32)(&(((struct bootloader_message_ab *)0)->slot_suffix[BOOTCTRL_IDX]))
+#define MISC_COMMAND \
+	(u32)(uintptr_t)(&(((struct bootloader_message *)0)->command[MISC_COMMAND_IDX]))
+
+#ifdef CONFIG_ANDROID_RECOVERY
+#define RECOVERY_OPTIONS\
+	(u32)(uintptr_t)(&(((struct bootloader_message *)0)->recovery[0]))
+#endif
+int bcb_rw_block(bool bread, char **ppblock,
+		uint *pblksize, char *pblock_write, uint offset, uint size);
+
+int bcb_write_command(char *bcb_command);
+int bcb_read_command(char *command);
+
+#ifdef CONFIG_ANDROID_RECOVERY
+int bcb_write_recovery_opt(char *opts);
+#endif
+#endif
diff --git a/drivers/fastboot/fb_fsl/command.c b/drivers/fastboot/fb_fsl/command.c
new file mode 100644
index 00000000000..d3fb9f03dfc
--- /dev/null
+++ b/drivers/fastboot/fb_fsl/command.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier:     GPL-2.0+
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <g_dnl.h>
+#include "bcb.h"
+
+int bcb_read_command(char *command)
+{
+	int ret = 0;
+	char *p_block = NULL;
+	uint offset_in_block = 0;
+	uint blk_size = 0;
+
+	if (command == NULL)
+		return -1;
+
+	ret = bcb_rw_block(true, &p_block, &blk_size, NULL, MISC_COMMAND, 32);
+	if (ret) {
+		printf("read_bootctl, bcb_rw_block read failed\n");
+		return -1;
+	}
+
+	offset_in_block = MISC_COMMAND%blk_size;
+	memcpy(command, p_block + offset_in_block, 32);
+	free(p_block);
+
+	return 0;
+}
+int bcb_write_command(char *bcb_command)
+{
+	int ret = 0;
+	char *p_block = NULL;
+	uint offset_in_block = 0;
+	uint blk_size = 0;
+
+	if (bcb_command == NULL)
+		return -1;
+
+
+	ret = bcb_rw_block(true, &p_block, &blk_size, NULL,  MISC_COMMAND, 32);
+	if (ret) {
+		printf("write_bootctl, bcb_rw_block read failed\n");
+		return -1;
+	}
+
+	offset_in_block = MISC_COMMAND%blk_size;
+	memcpy(p_block + offset_in_block, bcb_command, 32);
+
+	ret = bcb_rw_block(false, NULL, NULL, p_block, MISC_COMMAND, 32);
+	if (ret) {
+		free(p_block);
+		printf("write_bootctl, bcb_rw_block write failed\n");
+		return -1;
+	}
+
+	free(p_block);
+	return 0;
+}
+
+#ifdef CONFIG_ANDROID_RECOVERY
+int bcb_write_recovery_opt(char *opts)
+{
+	int ret = 0;
+	char *p_block = NULL;
+	uint offset_in_block = 0;
+	uint blk_size = 0;
+
+	if (opts == NULL)
+		return -1;
+
+
+	ret = bcb_rw_block(true, &p_block, &blk_size, NULL, RECOVERY_OPTIONS, 32);
+	if (ret) {
+		printf("write_bootctl, bcb_rw_block read failed\n");
+		return -1;
+	}
+
+	offset_in_block = RECOVERY_OPTIONS%blk_size;
+	memcpy(p_block + offset_in_block, opts, 32);
+
+	ret = bcb_rw_block(false, NULL, NULL, p_block, RECOVERY_OPTIONS, 32);
+	if (ret) {
+		free(p_block);
+		printf("write_bootctl, bcb_rw_block write failed\n");
+		return -1;
+	}
+
+	free(p_block);
+	return 0;
+}
+#endif
diff --git a/drivers/fastboot/fb_fsl/fastboot_lock_unlock.c b/drivers/fastboot/fb_fsl/fastboot_lock_unlock.c
new file mode 100644
index 00000000000..ba9921d4935
--- /dev/null
+++ b/drivers/fastboot/fb_fsl/fastboot_lock_unlock.c
@@ -0,0 +1,672 @@
+// SPDX-License-Identifier:     GPL-2.0+
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ */
+#include <common.h>
+#include <mapmem.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <part.h>
+#include <mmc.h>
+#include <ext_common.h>
+#include <stdio_dev.h>
+#include <stdlib.h>
+#include "fastboot_lock_unlock.h"
+#include <fb_fsl.h>
+#include <memalign.h>
+#include <asm/mach-imx/sys_proto.h>
+#ifdef CONFIG_IMX_TRUSTY_OS
+#include <trusty/libtipc.h>
+#include <asm/mach-imx/hab.h>
+#endif
+
+#include <fsl_avb.h>
+
+#ifdef FASTBOOT_ENCRYPT_LOCK
+
+#include <hash.h>
+#include <fsl_sec.h>
+
+//Encrypted data is 80bytes length.
+#define ENDATA_LEN 80
+
+#endif
+
+#ifdef CONFIG_AVB_WARNING_LOGO
+#include "lcd.h"
+#include "video.h"
+#include "dm/uclass.h"
+#include "fsl_avb_logo.h"
+#include "video_link.h"
+#include "video_console.h"
+#include "video_font_data.h"
+#endif
+
+int fastboot_flash_find_index(const char *name);
+
+#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_ARM64)
+#define IVT_HEADER_MAGIC       0xD1
+#define IVT_HDR_LEN       0x20
+#define HAB_MAJ_VER       0x40
+#define HAB_MAJ_MASK      0xF0
+
+bool tos_flashed;
+
+static bool tos_ivt_check(ulong start_addr, int ivt_offset) {
+	const struct ivt *ivt_initial = NULL;
+	const uint8_t *start = (const uint8_t *)start_addr;
+
+	if (start_addr & 0x3) {
+		puts("Error: tos's start address is not 4 byte aligned\n");
+		return false;
+	}
+
+	ivt_initial = (const struct ivt *)(start + ivt_offset);
+
+	const struct ivt_header *ivt_hdr = &ivt_initial->hdr;
+
+	if ((ivt_hdr->magic == IVT_HEADER_MAGIC && \
+		(be16_to_cpu(ivt_hdr->length) == IVT_HDR_LEN) && \
+		(ivt_hdr->version & HAB_MAJ_MASK) == HAB_MAJ_VER) && \
+		(ivt_initial->entry != 0x0) && \
+		(ivt_initial->reserved1 == 0x0) && \
+		(ivt_initial->self == (uint32_t)ivt_initial) && \
+		(ivt_initial->csf != 0x0) && \
+		(ivt_initial->reserved2 == 0x0)) {
+		if (ivt_initial->dcd != 0x0)
+			return false;
+		else
+			return true;
+	}
+
+	return false;
+}
+
+bool valid_tos() {
+	/*
+	 * If enabled SECURE_BOOT then use HAB to verify tos.
+	 * Or check the IVT only.
+	 */
+	bool valid = false;
+#ifdef CONFIG_IMX_HAB
+	if (is_hab_enabled()) {
+		valid = authenticate_image(TRUSTY_OS_ENTRY, TRUSTY_OS_PADDED_SZ);
+	} else
+#endif
+	valid = tos_ivt_check(TRUSTY_OS_ENTRY, TRUSTY_OS_PADDED_SZ);
+
+	if (valid) {
+		tos_flashed = true;
+		return true;
+	} else {
+		tos_flashed = false;
+		return false;
+	}
+}
+
+#endif
+
+#if !defined(FASTBOOT_ENCRYPT_LOCK) || defined(NON_SECURE_FASTBOOT)
+
+/*
+ * This will return FASTBOOT_LOCK, FASTBOOT_UNLOCK or FASTBOOT_ERROR
+ */
+#ifndef CONFIG_IMX_TRUSTY_OS
+static FbLockState decrypt_lock_store(unsigned char* bdata) {
+	if (!strncmp((const char *)bdata, "locked", strlen("locked")))
+		return FASTBOOT_LOCK;
+	else if (!strncmp((const char *)bdata, "unlocked", strlen("unlocked")))
+		return FASTBOOT_UNLOCK;
+	else
+		return FASTBOOT_LOCK_ERROR;
+}
+static inline int encrypt_lock_store(FbLockState lock, unsigned char* bdata) {
+	if (FASTBOOT_LOCK == lock)
+		strncpy((char *)bdata, "locked", strlen("locked") + 1);
+	else if (FASTBOOT_UNLOCK == lock)
+		strncpy((char *)bdata, "unlocked", strlen("unlocked") + 1);
+	else
+		return -1;
+	return 0;
+}
+#endif
+#else
+static u8 skeymod[] = {
+	0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08,
+	0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00
+};
+
+static int sha1sum(unsigned char* data, int len, unsigned char* output) {
+	struct hash_algo *algo;
+	void *buf;
+	if (hash_lookup_algo("sha1", &algo)) {
+		printf("error in lookup sha1 algo!\n");
+		return -1;
+	}
+	buf = map_sysmem((ulong)data, len);
+	algo->hash_func_ws(buf, len, output, algo->chunk_size);
+	unmap_sysmem(buf);
+
+	return algo->digest_size;
+
+}
+
+static int generate_salt(unsigned char* salt) {
+	unsigned long time = get_timer(0);
+	return sha1sum((unsigned char *)&time, sizeof(unsigned long), salt);
+
+}
+
+static __maybe_unused FbLockState decrypt_lock_store(unsigned char *bdata) {
+	int p = 0, ret;
+	ALLOC_CACHE_ALIGN_BUFFER(uint8_t, plain_data, ENDATA_LEN);
+	ALLOC_CACHE_ALIGN_BUFFER(uint8_t, keymod, 16);
+
+	memcpy(keymod, skeymod, sizeof(skeymod));
+	ret = blob_decap(keymod, plain_data, bdata + ROUND(ENDATA_LEN, ARCH_DMA_MINALIGN), ENDATA_LEN);
+	if (ret != 0) {
+		printf("Error during blob decap operation: 0x%x\n",ret);
+		return FASTBOOT_LOCK_ERROR;
+	}
+#ifdef FASTBOOT_LOCK_DEBUG
+	FB_DEBUG("Decrypt data block are:\n \t=======\t\n");
+	for (p = 0; p < ENDATA_LEN; p++) {
+		FB_DEBUG("0x%2x  ", *(bdata + p));
+		if (p % 16 == 0)
+			FB_DEBUG("\n");
+	}
+	FB_DEBUG("\n \t========\t\n");
+	for (p = ENDATA_LEN; p < (ENDATA_LEN + ENDATA_LEN + 48 ); p++) {
+		FB_DEBUG("0x%2x  ", *(bdata + p));
+		if (p % 16 == 0)
+			FB_DEBUG("\n");
+	}
+
+	FB_DEBUG("\n plain text are:\n");
+	for (p = 0; p < ENDATA_LEN; p++) {
+		FB_DEBUG("0x%2x  ", plain_data[p]);
+		if (p % 16 == 0)
+			FB_DEBUG("\n");
+	}
+	FB_DEBUG("\n");
+#endif
+
+	for (p = 0; p < ENDATA_LEN-1; p++) {
+		if (*(bdata+p) != plain_data[p]) {
+			FB_DEBUG("Verify salt in decrypt error on pointer %d\n", p);
+			return FASTBOOT_LOCK_ERROR;
+		}
+	}
+
+	if (plain_data[ENDATA_LEN - 1] >= FASTBOOT_LOCK_NUM)
+		return FASTBOOT_LOCK_ERROR;
+	else
+		return plain_data[ENDATA_LEN-1];
+}
+
+static __maybe_unused int encrypt_lock_store(FbLockState lock, unsigned char* bdata) {
+	ALLOC_CACHE_ALIGN_BUFFER(uint8_t, keymod, 16);
+	unsigned int p = 0;
+	int ret;
+	int salt_len = generate_salt(bdata);
+	if (salt_len < 0)
+		return -1;
+
+    //salt_len cannot be longer than endata block size.
+	if (salt_len >= ENDATA_LEN)
+		salt_len = ENDATA_LEN - 1;
+
+	p = ENDATA_LEN - 1;
+
+	//Set lock value
+	*(bdata + p) = lock;
+
+	memcpy(keymod, skeymod, sizeof(skeymod));
+	ret = blob_encap(keymod, bdata, bdata + ROUND(ENDATA_LEN, ARCH_DMA_MINALIGN), ENDATA_LEN,
+			 0);
+	if (ret != 0) {
+		printf("error in blob_encap:0x%x\n", ret);
+		return -1;
+	}
+
+
+#ifdef FASTBOOT_LOCK_DEBUG
+	int i = 0;
+	FB_DEBUG("encrypt plain_text:\n");
+	for (i = 0; i < ENDATA_LEN; i++) {
+		FB_DEBUG("0x%2x\t", *(bdata+i));
+		if (i % 16 == 0)
+			printf("\n");
+	}
+	printf("\nto:\n");
+	for (i=0; i < ENDATA_LEN + 48; i++) {
+		FB_DEBUG("0x%2x\t", *(bdata + ENDATA_LEN + i));
+		if (i % 16 == 0)
+			printf("\n");
+	}
+	printf("\n");
+
+#endif
+	//protect value
+	*(bdata + p) = 0xff;
+	return 0;
+}
+
+#endif
+
+static char mmc_dev_part[16];
+static char* get_mmc_part(int part) {
+	u32 dev_no = mmc_get_env_dev();
+	sprintf(mmc_dev_part,"%x:%x",dev_no, part);
+	return mmc_dev_part;
+}
+
+static inline void set_lock_disable_data(unsigned char* bdata) {
+	*(bdata + SECTOR_SIZE -1) = 0;
+}
+
+/*
+ * The enabling value is stored in the last byte of target partition.
+ */
+static inline unsigned char lock_enable_parse(unsigned char* bdata) {
+	FB_DEBUG("lock_enable_parse: 0x%x\n", *(bdata + SECTOR_SIZE -1));
+	if (*(bdata + SECTOR_SIZE -1) >= FASTBOOT_UL_NUM)
+		return FASTBOOT_UL_ERROR;
+	else
+		return *(bdata + SECTOR_SIZE -1);
+}
+
+static FbLockState g_lockstat = FASTBOOT_UNLOCK;
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+FbLockState fastboot_get_lock_stat(void) {
+	uint8_t l_status;
+	int ret;
+	/*
+	 * If Trusty OS not flashed, then must return
+	 * unlock status to make device been able
+	 * to flash Trusty OS binary.
+	 */
+#ifndef CONFIG_ARM64
+	if (!tos_flashed)
+		return FASTBOOT_UNLOCK;
+#endif
+	ret = trusty_read_lock_state(&l_status);
+	if (ret < 0)
+		return g_lockstat;
+	else
+		return l_status;
+
+}
+
+int fastboot_set_lock_stat(FbLockState lock) {
+	int ret;
+	/*
+	 * If Trusty OS not flashed, we must prevent set lock
+	 * status. Due the Trusty IPC won't work here.
+	 */
+#ifndef CONFIG_ARM64
+	if (!tos_flashed)
+		return 0;
+#endif
+	ret = trusty_write_lock_state(lock);
+	if (ret < 0) {
+		printf("cannot set lock status due Trusty return %d\n", ret);
+		return ret;
+	}
+	return 0;
+}
+#else
+
+/*
+ * Set status of the lock&unlock to FSL_FASTBOOT_FB_PART
+ * Currently use the very first Byte of FSL_FASTBOOT_FB_PART
+ * to store the fastboot lock&unlock status
+ */
+int fastboot_set_lock_stat(FbLockState lock) {
+	struct blk_desc *fs_dev_desc;
+	struct disk_partition fs_partition;
+	unsigned char *bdata;
+	int mmc_id;
+	int status, ret;
+
+	bdata = (unsigned char *)memalign(ARCH_DMA_MINALIGN, SECTOR_SIZE);
+	if (bdata == NULL)
+		goto fail2;
+	memset(bdata, 0, SECTOR_SIZE);
+
+	mmc_id = fastboot_flash_find_index(FASTBOOT_PARTITION_FBMISC);
+	if (mmc_id < 0) {
+		printf("%s: error in get mmc part\n", __FUNCTION__);
+		ret = -1;
+		goto fail;
+	}
+	status = blk_get_device_part_str(FSL_FASTBOOT_FB_DEV,
+		get_mmc_part(mmc_id),
+		&fs_dev_desc, &fs_partition, 1);
+	if (status < 0) {
+		printf("%s:error in getdevice partition.\n", __FUNCTION__);
+		ret = -1;
+		goto fail;
+	}
+
+	status = encrypt_lock_store(lock, bdata);
+	if (status < 0) {
+		ret = -1;
+		goto fail;
+	}
+	status = blk_dwrite(fs_dev_desc, fs_partition.start, 1, bdata);
+	if (!status) {
+		printf("%s:error in block write.\n", __FUNCTION__);
+		ret = -1;
+		goto fail;
+	}
+	ret = 0;
+fail:
+	free(bdata);
+	return ret;
+fail2:
+	g_lockstat = lock;
+	return 0;
+}
+
+FbLockState fastboot_get_lock_stat(void) {
+	struct blk_desc *fs_dev_desc;
+	struct disk_partition fs_partition;
+	unsigned char *bdata;
+	int mmc_id;
+	FbLockState ret;
+	/* uboot used by uuu will boot from USB, always return UNLOCK state */
+	if (is_boot_from_usb())
+		return g_lockstat;
+
+	bdata = (unsigned char *)memalign(ARCH_DMA_MINALIGN, SECTOR_SIZE);
+	if (bdata == NULL)
+		return g_lockstat;
+
+	int status;
+	mmc_id = fastboot_flash_find_index(FASTBOOT_PARTITION_FBMISC);
+	if (mmc_id < 0) {
+		printf("%s: error in get mmc part\n", __FUNCTION__);
+		ret = g_lockstat;
+		goto fail;
+	}
+	status = blk_get_device_part_str(FSL_FASTBOOT_FB_DEV,
+		get_mmc_part(mmc_id),
+		&fs_dev_desc, &fs_partition, 1);
+
+	if (status < 0) {
+		printf("%s:error in getdevice partition.\n", __FUNCTION__);
+		ret = g_lockstat;
+		goto fail;
+	}
+
+	status = blk_dread(fs_dev_desc, fs_partition.start, 1, bdata);
+	if (!status) {
+		printf("%s:error in block read.\n", __FUNCTION__);
+		ret = FASTBOOT_LOCK_ERROR;
+		goto fail;
+	}
+
+	ret = decrypt_lock_store(bdata);
+fail:
+	free(bdata);
+	return ret;
+}
+#endif
+
+
+/* Return the last byte of of FSL_FASTBOOT_PR_DATA
+ * which is managed by PresistDataService
+ */
+
+#ifdef CONFIG_ENABLE_LOCKSTATUS_SUPPORT
+//Brillo has no presist data partition
+FbLockEnableResult fastboot_lock_enable(void) {
+	return FASTBOOT_UL_ENABLE;
+}
+void set_fastboot_lock_disable(void) {
+}
+#else
+void set_fastboot_lock_disable(void) {
+	struct blk_desc *fs_dev_desc;
+	struct disk_partition fs_partition;
+	unsigned char *bdata;
+	int mmc_id;
+
+	bdata = (unsigned char *)memalign(ALIGN_BYTES, SECTOR_SIZE);
+	if (bdata == NULL)
+		return;
+	set_lock_disable_data(bdata);
+	int status;
+	mmc_id = fastboot_flash_find_index(FASTBOOT_PARTITION_PRDATA);
+	if (mmc_id < 0) {
+		printf("%s: error in get mmc part\n", __FUNCTION__);
+		goto fail;
+	}
+	status = blk_get_device_part_str(FSL_FASTBOOT_FB_DEV,
+		get_mmc_part(mmc_id),
+		&fs_dev_desc, &fs_partition, 1);
+	if (status < 0) {
+		printf("%s:error in getdevice partition.\n", __FUNCTION__);
+		goto fail;
+	}
+
+	lbaint_t target_block = fs_partition.start + fs_partition.size - 1;
+	status = blk_dwrite(fs_dev_desc, target_block, 1, bdata);
+	if (!status) {
+		printf("%s: error in block read\n", __FUNCTION__);
+		goto fail;
+	}
+
+fail:
+	free(bdata);
+	return;
+
+}
+FbLockEnableResult fastboot_lock_enable() {
+#ifdef CONFIG_DUAL_BOOTLOADER
+	/* Always allow unlock device in spl recovery mode. */
+	if (is_spl_recovery())
+		return FASTBOOT_UL_ENABLE;
+#endif
+
+#if defined(CONFIG_IMX_TRUSTY_OS) || defined(CONFIG_TRUSTY_UNLOCK_PERMISSION)
+	int ret;
+	uint8_t oem_device_unlock;
+
+	ret = trusty_read_oem_unlock_device_permission(&oem_device_unlock);
+	if (ret < 0)
+		return FASTBOOT_UL_ERROR;
+	else
+		return oem_device_unlock;
+#else /* CONFIG_IMX_TRUSTY_OS */
+	FbLockEnableResult ret;
+	struct blk_desc *fs_dev_desc;
+	struct disk_partition fs_partition;
+	unsigned char *bdata;
+	int mmc_id;
+
+	bdata = (unsigned char *)memalign(ALIGN_BYTES, SECTOR_SIZE);
+	if (bdata == NULL)
+		return FASTBOOT_UL_ERROR;
+	int status;
+	mmc_id = fastboot_flash_find_index(FASTBOOT_PARTITION_PRDATA);
+	if (mmc_id < 0) {
+		printf("%s: error in get mmc part\n", __FUNCTION__);
+		ret = FASTBOOT_UL_ERROR;
+		goto fail;
+	}
+	status = blk_get_device_part_str(FSL_FASTBOOT_FB_DEV,
+		get_mmc_part(mmc_id),
+		&fs_dev_desc, &fs_partition, 1);
+	if (status < 0) {
+		printf("%s:error in getdevice partition.\n", __FUNCTION__);
+		ret = FASTBOOT_UL_ERROR;
+		goto fail;
+	}
+
+    //The data is stored in the last blcok of this partition.
+	lbaint_t target_block = fs_partition.start + fs_partition.size - 1;
+	status = blk_dread(fs_dev_desc, target_block, 1, bdata);
+	if (!status) {
+		printf("%s: error in block read\n", __FUNCTION__);
+		ret = FASTBOOT_UL_ERROR;
+		goto fail;
+	}
+	int i = 0;
+	FB_DEBUG("\n PRIST last sector is:\n");
+	for (i = 0; i < SECTOR_SIZE; i++) {
+		FB_DEBUG("0x%x  ", *(bdata + i));
+		if (i % 32 == 0)
+			FB_DEBUG("\n");
+	}
+	FB_DEBUG("\n");
+	ret = lock_enable_parse(bdata);
+fail:
+	free(bdata);
+	return ret;
+#endif /* CONFIG_IMX_TRUSTY_OS */
+
+}
+#endif
+
+int display_lock(FbLockState lock, int verify) {
+	struct stdio_dev *disp;
+	disp = stdio_get_by_name("vga");
+	if (disp != NULL) {
+		if (lock == FASTBOOT_UNLOCK) {
+			disp->puts(disp, "\n============= NOTICE ============\n");
+			disp->puts(disp,   "|                               |\n");
+			disp->puts(disp,   "|   Your device is NOT locked.  |\n");
+			disp->puts(disp,   "|                               |\n");
+			disp->puts(disp,   "=================================\n");
+		} else {
+			if (verify == -1) {
+				disp->puts(disp, "\n============= NOTICE ============\n");
+				disp->puts(disp,   "|                               |\n");
+				disp->puts(disp,   "| Your device is NOT protected. |\n");
+				disp->puts(disp,   "|                               |\n");
+				disp->puts(disp,   "=================================\n");
+			} else if (verify == 1) {
+				disp->puts(disp, "\n============= NOTICE ============\n");
+				disp->puts(disp,   "|                               |\n");
+				disp->puts(disp,   "|       Boot verify failed!     |\n");
+				disp->puts(disp,   "|                               |\n");
+				disp->puts(disp,   "=================================\n");
+			}
+		}
+		return 0;
+	} else
+		printf("not found VGA disp console.\n");
+
+	return -1;
+
+}
+
+#ifdef CONFIG_AVB_WARNING_LOGO
+int display_unlock_warning(void) {
+	int ret;
+	struct udevice *dev;
+
+	ret = uclass_first_device_err(UCLASS_VIDEO, &dev);
+	if (!ret) {
+		/* clear screen first */
+		video_clear(dev);
+		/* Draw the orange warning bmp logo */
+		ret = bmp_display((ulong)orange_warning_bmp_bitmap,
+					CONFIG_AVB_WARNING_LOGO_COLS, CONFIG_AVB_WARNING_LOGO_ROWS);
+
+		/* Show warning text. */
+		if (uclass_first_device_err(UCLASS_VIDEO_CONSOLE, &dev)) {
+			printf("no text console device found!\n");
+			return -1;
+		}
+		/* Adjust the cursor postion, the (x, y) are hard-coded here. */
+		vidconsole_position_cursor(dev, CONFIG_AVB_WARNING_LOGO_COLS/VIDEO_FONT_WIDTH,
+						CONFIG_AVB_WARNING_LOGO_ROWS/VIDEO_FONT_HEIGHT + 6);
+		vidconsole_put_string(dev, "The bootloader is unlocked and software");
+		vidconsole_position_cursor(dev, CONFIG_AVB_WARNING_LOGO_COLS/VIDEO_FONT_WIDTH,
+						CONFIG_AVB_WARNING_LOGO_ROWS/VIDEO_FONT_HEIGHT + 7);
+		vidconsole_put_string(dev, "integrity cannot be guaranteed. Any data");
+		vidconsole_position_cursor(dev, CONFIG_AVB_WARNING_LOGO_COLS/VIDEO_FONT_WIDTH,
+						CONFIG_AVB_WARNING_LOGO_ROWS/VIDEO_FONT_HEIGHT + 8);
+		vidconsole_put_string(dev, "stored on the device may be available to");
+		vidconsole_position_cursor(dev, CONFIG_AVB_WARNING_LOGO_COLS/VIDEO_FONT_WIDTH,
+						CONFIG_AVB_WARNING_LOGO_ROWS/VIDEO_FONT_HEIGHT + 9);
+		vidconsole_put_string(dev, "attackers. Do not store any sensitive data");
+		vidconsole_position_cursor(dev, CONFIG_AVB_WARNING_LOGO_COLS/VIDEO_FONT_WIDTH,
+						CONFIG_AVB_WARNING_LOGO_ROWS/VIDEO_FONT_HEIGHT + 10);
+		vidconsole_put_string(dev, "on the device.");
+		/* Jump one line to show the link */
+		vidconsole_position_cursor(dev, CONFIG_AVB_WARNING_LOGO_COLS/VIDEO_FONT_WIDTH,
+						CONFIG_AVB_WARNING_LOGO_ROWS/VIDEO_FONT_HEIGHT + 13);
+		vidconsole_put_string(dev, "Visit this link on another device:");
+		vidconsole_position_cursor(dev, CONFIG_AVB_WARNING_LOGO_COLS/VIDEO_FONT_WIDTH,
+						CONFIG_AVB_WARNING_LOGO_ROWS/VIDEO_FONT_HEIGHT + 14);
+		vidconsole_put_string(dev, "g.co/ABH");
+
+		vidconsole_position_cursor(dev, CONFIG_AVB_WARNING_LOGO_COLS/VIDEO_FONT_WIDTH,
+						CONFIG_AVB_WARNING_LOGO_ROWS/VIDEO_FONT_HEIGHT + 20);
+		vidconsole_put_string(dev, "PRESS POWER BUTTON TO CONTINUE...");
+		/* sync frame buffer */
+		video_sync_all();
+
+		return 0;
+	} else {
+		printf("no video device found!\n");
+		return -1;
+	}
+}
+#endif
+
+int fastboot_wipe_data_partition(void)
+{
+	struct blk_desc *fs_dev_desc;
+	struct disk_partition fs_partition;
+	int status;
+	int mmc_id;
+	mmc_id = fastboot_flash_find_index(FASTBOOT_PARTITION_DATA);
+	if (mmc_id < 0) {
+		printf("%s: error in get mmc part\n", __FUNCTION__);
+		return -1;
+	}
+	status = blk_get_device_part_str(FSL_FASTBOOT_FB_DEV,
+		get_mmc_part(mmc_id), &fs_dev_desc, &fs_partition, 1);
+	if (status < 0) {
+		printf("error in get device partition for wipe /data\n");
+		return -1;
+	}
+	status = blk_derase(fs_dev_desc, fs_partition.start , fs_partition.size );
+	if (status != fs_partition.size ) {
+		printf("erase not complete\n");
+		return -1;
+	}
+	mdelay(2000);
+
+	return 0;
+}
+
+void fastboot_wipe_all(void) {
+	struct blk_desc *fs_dev_desc;
+	struct disk_partition fs_partition;
+	int status;
+	int mmc_id;
+	mmc_id = fastboot_flash_find_index(FASTBOOT_PARTITION_GPT);
+	if (mmc_id < 0) {
+		printf("%s: error in get mmc part\n", __FUNCTION__);
+		return;
+	}
+	status = blk_get_device_part_str(FSL_FASTBOOT_FB_DEV,
+		get_mmc_part(mmc_id), &fs_dev_desc, &fs_partition, 1);
+	if (status < 0) {
+		printf("error in get device partition for wipe user partition\n");
+		return;
+	}
+	status = blk_derase(fs_dev_desc, fs_partition.start , fs_partition.size );
+	if (status != fs_partition.size ) {
+		printf("erase not complete\n");
+		return;
+	}
+	printf("fastboot wiped all.\n");
+}
diff --git a/drivers/fastboot/fb_fsl/fastboot_lock_unlock.h b/drivers/fastboot/fb_fsl/fastboot_lock_unlock.h
new file mode 100644
index 00000000000..890b0de00b5
--- /dev/null
+++ b/drivers/fastboot/fb_fsl/fastboot_lock_unlock.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef FASTBOOT_LOCK_UNLOCK_H
+#define FASTBOOT_LOCK_UNLOCK_H
+
+#define ALIGN_BYTES 64 /*armv7 cache line need 64 bytes aligned */
+
+//#define FASTBOOT_LOCK_DEBUG
+
+#ifdef FASTBOOT_LOCK_DEBUG
+#define FB_DEBUG(format, ...) printf(format, ##__VA_ARGS__)
+#else
+#define FB_DEBUG(format, ...)
+#endif
+
+typedef enum {
+	FASTBOOT_UNLOCK,
+	FASTBOOT_LOCK,
+	FASTBOOT_LOCK_ERROR,
+	FASTBOOT_LOCK_NUM
+}FbLockState;
+
+typedef enum {
+	FASTBOOT_UL_DISABLE,
+	FASTBOOT_UL_ENABLE,
+	FASTBOOT_UL_ERROR,
+	FASTBOOT_UL_NUM
+}FbLockEnableResult;
+
+FbLockState fastboot_get_lock_stat(void);
+
+int fastboot_set_lock_stat(FbLockState lock);
+
+int fastboot_wipe_data_partition(void);
+void fastboot_wipe_all(void);
+
+FbLockEnableResult fastboot_lock_enable(void);
+void set_fastboot_lock_disable(void);
+
+int display_lock(FbLockState lock, int verify);
+
+int display_unlock_warning(void);
+
+bool valid_tos(void);
+#endif
diff --git a/drivers/fastboot/fb_fsl/fb_fsl_boot.c b/drivers/fastboot/fb_fsl/fb_fsl_boot.c
new file mode 100644
index 00000000000..74eb0f21323
--- /dev/null
+++ b/drivers/fastboot/fb_fsl/fb_fsl_boot.c
@@ -0,0 +1,1172 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <asm/mach-imx/sys_proto.h>
+#include <fb_fsl.h>
+#include <fastboot.h>
+#include <mmc.h>
+#include <android_image.h>
+#include <asm/bootm.h>
+#include <nand.h>
+#include <part.h>
+#include <sparse_format.h>
+#include <image-sparse.h>
+#include <image.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/setup.h>
+#include <env.h>
+#include <u-boot/lz4.h>
+#include <linux/delay.h>
+#include "../lib/avb/fsl/utils.h"
+
+#ifdef CONFIG_AVB_SUPPORT
+#include <dt_table.h>
+#include <fsl_avb.h>
+#endif
+
+#ifdef CONFIG_ANDROID_THINGS_SUPPORT
+#include <asm-generic/gpio.h>
+#include <asm/mach-imx/gpio.h>
+#include "../lib/avb/fsl/fsl_avbkey.h"
+#include "../arch/arm/include/asm/mach-imx/hab.h"
+#endif
+
+#if defined(CONFIG_FASTBOOT_LOCK)
+#include "fastboot_lock_unlock.h"
+#endif
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#include "u-boot/sha256.h"
+#include <trusty/libtipc.h>
+#include <trusty/hwcrypto.h>
+
+#ifndef CONFIG_LOAD_KEY_FROM_RPMB
+#include "../lib/avb/fsl/fsl_public_key.h"
+#endif
+
+#endif
+
+#include "fb_fsl_common.h"
+
+/* max kernel image size, used for compressed kernel image */
+#define MAX_KERNEL_LEN (96 * 1024 * 1024)
+
+/* Boot metric variables */
+boot_metric metrics = {
+  .bll_1 = 0,
+  .ble_1 = 0,
+  .kl	 = 0,
+  .kd	 = 0,
+  .avb	 = 0,
+  .odt	 = 0,
+  .sw	 = 0
+};
+
+int read_from_partition_multi(const char* partition,
+		int64_t offset, size_t num_bytes, void* buffer, size_t* out_num_read)
+{
+	struct fastboot_ptentry *pte;
+	unsigned char *bdata;
+	unsigned char *out_buf = (unsigned char *)buffer;
+	unsigned char *dst, *dst64 = NULL;
+	unsigned long blksz;
+	unsigned long s, cnt;
+	size_t num_read = 0;
+	lbaint_t part_start, part_end, bs, be, bm, blk_num;
+	margin_pos_t margin;
+	struct blk_desc *fs_dev_desc = NULL;
+	int dev_no;
+	int ret;
+
+	assert(buffer != NULL && out_num_read != NULL);
+
+	dev_no = mmc_get_env_dev();
+	if ((fs_dev_desc = blk_get_dev("mmc", dev_no)) == NULL) {
+		printf("mmc device not found\n");
+		return -1;
+	}
+
+	pte = fastboot_flash_find_ptn(partition);
+	if (!pte) {
+		printf("no %s partition\n", partition);
+		fastboot_flash_dump_ptn();
+		return -1;
+	}
+
+	blksz = fs_dev_desc->blksz;
+	part_start = pte->start;
+	part_end = pte->start + pte->length - 1;
+
+	if (get_margin_pos((uint64_t)part_start, (uint64_t)part_end, blksz,
+				&margin, offset, num_bytes, true))
+		return -1;
+
+	bs = (lbaint_t)margin.blk_start;
+	be = (lbaint_t)margin.blk_end;
+	s = margin.start;
+	bm = margin.multi;
+
+	/* alloc a blksz mem */
+	bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz);
+	if (bdata == NULL) {
+		printf("Failed to allocate memory!\n");
+		return -1;
+	}
+
+	/* support multi blk read */
+	while (bs <= be) {
+		if (!s && bm > 1) {
+			dst = out_buf;
+			dst64 = PTR_ALIGN(out_buf, 64); /* for mmc blk read alignment */
+			if (dst64 != dst) {
+				dst = dst64;
+				bm--;
+			}
+			blk_num = bm;
+			cnt = bm * blksz;
+			bm = 0; /* no more multi blk */
+		} else {
+			blk_num = 1;
+			cnt = blksz - s;
+			if (num_read + cnt > num_bytes)
+				cnt = num_bytes - num_read;
+			dst = bdata;
+		}
+		if (blk_dread(fs_dev_desc, bs, blk_num, dst) != blk_num) {
+			ret = -1;
+			goto fail;
+		}
+
+		if (dst == bdata)
+			memcpy(out_buf, bdata + s, cnt);
+		else if (dst == dst64)
+			memcpy(out_buf, dst, cnt); /* internal copy */
+
+		s = 0;
+		bs += blk_num;
+		num_read += cnt;
+		out_buf += cnt;
+	}
+	*out_num_read = num_read;
+	ret = 0;
+
+fail:
+	free(bdata);
+	return ret;
+}
+
+
+#if defined(CONFIG_FASTBOOT_LOCK)
+int do_lock_status(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) {
+	FbLockState status = fastboot_get_lock_stat();
+	if (status != FASTBOOT_LOCK_ERROR) {
+		if (status == FASTBOOT_LOCK)
+			printf("fastboot lock status: locked.\n");
+		else
+			printf("fastboot lock status: unlocked.\n");
+	} else
+		printf("fastboot lock status error!\n");
+
+	display_lock(status, -1);
+
+	return 0;
+
+}
+
+U_BOOT_CMD(
+	lock_status, 2, 1, do_lock_status,
+	"lock_status",
+	"lock_status");
+#endif
+
+#if defined(CONFIG_FLASH_MCUFIRMWARE_SUPPORT) && defined(CONFIG_ARCH_IMX8M)
+static int do_bootmcu(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+	int ret;
+	size_t out_num_read;
+	void *mcu_base_addr = (void *)MCU_BOOTROM_BASE_ADDR;
+	char command[32];
+
+	ret = read_from_partition_multi(FASTBOOT_MCU_FIRMWARE_PARTITION,
+			0, ANDROID_MCU_OS_PARTITION_SIZE, (void *)mcu_base_addr, &out_num_read);
+	if ((ret != 0) || (out_num_read != ANDROID_MCU_OS_PARTITION_SIZE)) {
+		printf("Read MCU images failed!\n");
+		return 1;
+	} else {
+		printf("run command: 'bootaux 0x%x'\n",(unsigned int)(ulong)mcu_base_addr);
+
+		sprintf(command, "bootaux 0x%x", (unsigned int)(ulong)mcu_base_addr);
+		ret = run_command(command, 0);
+		if (ret) {
+			printf("run 'bootaux' command failed!\n");
+			return 1;
+		}
+	}
+	return 0;
+}
+
+U_BOOT_CMD(
+	bootmcu, 1, 0, do_bootmcu,
+	"boot mcu images\n",
+	"boot mcu images from 'mcu_os' partition, only support images run from TCM"
+);
+#endif
+
+#ifdef CONFIG_CMD_BOOTA
+
+/* Section for Android bootimage format support */
+
+#if !defined(CONFIG_ANDROID_DYNAMIC_PARTITION) && defined(CONFIG_SYSTEM_RAMDISK_SUPPORT)
+/* Setup booargs for taking the system parition as ramdisk */
+static void fastboot_setup_system_boot_args(const char *slot, bool append_root)
+{
+	const char *system_part_name = NULL;
+#ifdef CONFIG_ANDROID_AB_SUPPORT
+	if(slot == NULL)
+		return;
+	if(!strncmp(slot, "_a", strlen("_a")) || !strncmp(slot, "boot_a", strlen("boot_a"))) {
+		system_part_name = FASTBOOT_PARTITION_SYSTEM_A;
+	}
+	else if(!strncmp(slot, "_b", strlen("_b")) || !strncmp(slot, "boot_b", strlen("boot_b"))) {
+		system_part_name = FASTBOOT_PARTITION_SYSTEM_B;
+	} else {
+		printf("slot invalid!\n");
+		return;
+	}
+#else
+	system_part_name = FASTBOOT_PARTITION_SYSTEM;
+#endif
+
+	struct fastboot_ptentry *ptentry = fastboot_flash_find_ptn(system_part_name);
+	if(ptentry != NULL) {
+		char bootargs_3rd[ANDR_BOOT_ARGS_SIZE] = {'\0'};
+		if (append_root) {
+			u32 dev_no = mmc_map_to_kernel_blk(mmc_get_env_dev());
+			sprintf(bootargs_3rd, "root=/dev/mmcblk%dp%d ",
+					dev_no,
+					ptentry->partition_index);
+		}
+		strcat(bootargs_3rd, "rootwait");
+
+		env_set("bootargs_3rd", bootargs_3rd);
+	} else {
+		printf("Can't find partition: %s\n", system_part_name);
+		fastboot_flash_dump_ptn();
+	}
+}
+#endif
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_AVB_ATX)
+static int sha256_concatenation(uint8_t *hash_buf, uint8_t *vbh, uint8_t *image_hash)
+{
+	if ((hash_buf == NULL) || (vbh == NULL) || (image_hash == NULL)) {
+		printf("sha256_concatenation: null buffer found!\n");
+		return -1;
+	}
+
+	memcpy(hash_buf, vbh, AVB_SHA256_DIGEST_SIZE);
+	memcpy(hash_buf + AVB_SHA256_DIGEST_SIZE,
+	       image_hash, AVB_SHA256_DIGEST_SIZE);
+	sha256_csum_wd((unsigned char *)hash_buf, 2 * AVB_SHA256_DIGEST_SIZE,
+		       (unsigned char *)vbh, CHUNKSZ_SHA256);
+
+	return 0;
+}
+
+/* Since we use fit format to organize the atf, tee, u-boot and u-boot dtb,
+ * so calculate the hash of fit is enough.
+ */
+static int vbh_bootloader(uint8_t *image_hash)
+{
+	char* slot_suffixes[2] = {"_a", "_b"};
+	char partition_name[20];
+	AvbABData ab_data;
+	uint8_t *image_buf = NULL;
+	uint32_t image_size;
+	size_t image_num_read;
+	int target_slot;
+	int ret = 0;
+
+	/* Load A/B metadata and decide which slot we are going to load */
+	if (fsl_avb_ab_ops.read_ab_metadata(&fsl_avb_ab_ops, &ab_data) !=
+					    AVB_IO_RESULT_OK) {
+		ret = -1;
+		goto fail ;
+	}
+	target_slot = get_curr_slot(&ab_data);
+	sprintf(partition_name, "bootloader%s", slot_suffixes[target_slot]);
+
+	/* Read image header to find the image size */
+	image_buf = (uint8_t *)malloc(MMC_SATA_BLOCK_SIZE);
+	if (fsl_avb_ops.read_from_partition(&fsl_avb_ops, partition_name,
+					    0, MMC_SATA_BLOCK_SIZE,
+					    image_buf, &image_num_read)) {
+		printf("bootloader image load error!\n");
+		ret = -1;
+		goto fail;
+	}
+	image_size = fdt_totalsize((struct image_header *)image_buf);
+	image_size = (image_size + 3) & ~3;
+	free(image_buf);
+
+	/* Load full fit image */
+	image_buf = (uint8_t *)malloc(image_size);
+	if (fsl_avb_ops.read_from_partition(&fsl_avb_ops, partition_name,
+					    0, image_size,
+					    image_buf, &image_num_read)) {
+		printf("bootloader image load error!\n");
+		ret = -1;
+		goto fail;
+	}
+	/* Calculate hash */
+	sha256_csum_wd((unsigned char *)image_buf, image_size,
+		       (unsigned char *)image_hash, CHUNKSZ_SHA256);
+
+fail:
+	if (image_buf != NULL)
+		free(image_buf);
+	return ret;
+}
+
+int vbh_calculate(uint8_t *vbh, AvbSlotVerifyData *avb_out_data)
+{
+	uint8_t image_hash[AVB_SHA256_DIGEST_SIZE];
+	uint8_t hash_buf[2 * AVB_SHA256_DIGEST_SIZE];
+	uint8_t* image_buf = NULL;
+	uint32_t image_size;
+	size_t image_num_read;
+	int ret = 0;
+
+	if (vbh == NULL)
+		return -1;
+
+	/* Initial VBH (VBH0) should be 32 bytes 0 */
+	memset(vbh, 0, AVB_SHA256_DIGEST_SIZE);
+	/* Load and calculate the sha256 hash of spl.bin */
+	image_size = (ANDROID_SPL_SIZE + MMC_SATA_BLOCK_SIZE -1) /
+		      MMC_SATA_BLOCK_SIZE;
+	image_buf = (uint8_t *)malloc(image_size);
+	if (fsl_avb_ops.read_from_partition(&fsl_avb_ops,
+					    FASTBOOT_PARTITION_BOOTLOADER,
+					    0, image_size,
+					    image_buf, &image_num_read)) {
+		printf("spl image load error!\n");
+		ret = -1;
+		goto fail;
+	}
+	sha256_csum_wd((unsigned char *)image_buf, image_size,
+		       (unsigned char *)image_hash, CHUNKSZ_SHA256);
+	/* Calculate VBH1 */
+	if (sha256_concatenation(hash_buf, vbh, image_hash)) {
+		ret = -1;
+		goto fail;
+	}
+	free(image_buf);
+
+	/* Load and calculate hash of bootloader.img */
+	if (vbh_bootloader(image_hash)) {
+		ret = -1;
+		goto fail;
+	}
+
+	/* Calculate VBH2 */
+	if (sha256_concatenation(hash_buf, vbh, image_hash)) {
+		ret = -1;
+		goto fail;
+	}
+
+	/* Calculate the hash of vbmeta.img */
+	avb_slot_verify_data_calculate_vbmeta_digest(avb_out_data,
+						     AVB_DIGEST_TYPE_SHA256,
+						     image_hash);
+	/* Calculate VBH3 */
+	if (sha256_concatenation(hash_buf, vbh, image_hash)) {
+		ret = -1;
+		goto fail;
+	}
+
+fail:
+	if (image_buf != NULL)
+		free(image_buf);
+	return ret;
+}
+#endif /* CONFIG_DUAL_BOOTLOADER && CONFIG_AVB_ATX */
+
+int trusty_setbootparameter(uint32_t os_version,
+				AvbABFlowResult avb_result, AvbSlotVerifyData *avb_out_data) {
+	int ret = 0;
+	uint8_t vbh[AVB_SHA256_DIGEST_SIZE];
+	u32 os_ver = os_version >> 11;
+	u32 os_ver_km = (((os_ver >> 14) & 0x7F) * 100 + ((os_ver >> 7) & 0x7F)) * 100
+	    + (os_ver & 0x7F);
+	u32 os_lvl = os_version & ((1U << 11) - 1);
+	u32 os_lvl_km = ((os_lvl >> 4) + 2000) * 100 + (os_lvl & 0x0F);
+	keymaster_verified_boot_t vbstatus;
+	FbLockState lock_status = fastboot_get_lock_stat();
+	uint8_t boot_key_hash[AVB_SHA256_DIGEST_SIZE];
+
+	bool lock = (lock_status == FASTBOOT_LOCK)? true: false;
+	if ((avb_result == AVB_AB_FLOW_RESULT_OK) && lock)
+		vbstatus = KM_VERIFIED_BOOT_VERIFIED;
+	else
+		vbstatus = KM_VERIFIED_BOOT_UNVERIFIED;
+
+#ifdef CONFIG_AVB_ATX
+	if (fsl_read_permanent_attributes_hash(&fsl_avb_atx_ops, boot_key_hash)) {
+		printf("ERROR - failed to read permanent attributes hash for keymaster\n");
+		memset(boot_key_hash, '\0', AVB_SHA256_DIGEST_SIZE);
+	}
+#else
+	uint8_t public_key_buf[AVB_MAX_BUFFER_LENGTH];
+#ifdef CONFIG_LOAD_KEY_FROM_RPMB
+	if (trusty_read_vbmeta_public_key(public_key_buf,
+						AVB_MAX_BUFFER_LENGTH) != 0) {
+		printf("ERROR - failed to read public key for keymaster\n");
+		memset(boot_key_hash, '\0', AVB_SHA256_DIGEST_SIZE);
+	} else
+#else
+	memcpy(public_key_buf, fsl_public_key, AVB_SHA256_DIGEST_SIZE);
+#endif
+		sha256_csum_wd((unsigned char *)public_key_buf, AVB_SHA256_DIGEST_SIZE,
+				(unsigned char *)boot_key_hash, CHUNKSZ_SHA256);
+#endif
+
+	/* All '\0' boot key should be passed if the device is unlocked. */
+	if (!lock)
+		memset(boot_key_hash, '\0', AVB_SHA256_DIGEST_SIZE);
+
+	/* Calculate VBH */
+#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_AVB_ATX)
+	if (vbh_calculate(vbh, avb_out_data)) {
+		ret = -1;
+		goto fail;
+	}
+#else
+	avb_slot_verify_data_calculate_vbmeta_digest(avb_out_data,
+						     AVB_DIGEST_TYPE_SHA256,
+						     vbh);
+#endif
+	trusty_set_boot_params(os_ver_km, os_lvl_km, vbstatus, lock,
+					boot_key_hash, AVB_SHA256_DIGEST_SIZE,
+					vbh, AVB_SHA256_DIGEST_SIZE);
+
+#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_AVB_ATX)
+fail:
+#endif
+	return ret;
+}
+
+int set_boot_patch_level(char *slot)
+{
+	const char * boot_patch_level = NULL;
+	size_t patch_level_size = 0;
+	uint8_t* vbmeta_data = NULL;
+	size_t vbmeta_num_read;
+	uint32_t trimmed_patch_level = 0, year = 0, month = 0, day = 0;
+	AvbFooter footer;
+	size_t footer_num_read;
+	uint8_t footer_buf[AVB_FOOTER_SIZE];
+	char date_buf[10] = {0};
+	char boot_partition_name[16] = {0};
+	int ret = -1;
+
+	/* Get the vbmeta footer of 'boot' partition */
+	snprintf(boot_partition_name, sizeof(boot_partition_name), "boot%s", slot);
+	ret = read_from_partition_multi(boot_partition_name, -AVB_FOOTER_SIZE,
+					AVB_FOOTER_SIZE, footer_buf, &footer_num_read);
+	if ((ret != 0) || (footer_num_read != AVB_FOOTER_SIZE)) {
+		printf("boota: read boot image footer failed!\n");
+		ret = -1;
+		goto end;
+	} else if (!avb_footer_validate_and_byteswap((AvbFooter *)footer_buf, &footer)) {
+		printf("boota: failed to find vbmeta footer!\n");
+		ret = -1;
+		goto end;
+	}
+
+	/* Get vbmeta struct in 'boot' partition */
+	vbmeta_data = malloc(footer.vbmeta_size);
+	if (vbmeta_data == NULL) {
+		printf("boota: failed to allocate memory!\n");
+		ret = -1;
+		goto end;
+	}
+	ret = read_from_partition_multi(boot_partition_name, footer.vbmeta_offset,
+					footer.vbmeta_size, vbmeta_data, &vbmeta_num_read);
+	if ((ret != 0) || (vbmeta_num_read != footer.vbmeta_size)) {
+		printf("boota: read vbmeta struct in boot image failed!\n");
+		ret = -1;
+		goto end;
+	}
+
+	/* Search for the boot security patch level property. */
+	boot_patch_level = avb_property_lookup(vbmeta_data, footer.vbmeta_size,
+						"com.android.build.boot.security_patch",
+						0, &patch_level_size);
+	if (boot_patch_level) {
+		/* Format the security patch level which is YYYY-MM-DD */
+		char *start, *end;
+
+		/* Year */
+		start = (char *)boot_patch_level;
+		end = strchr(boot_patch_level, '-');
+		if (!end) {
+			printf("boota: invalid boot security patch level!\n");
+			ret = -1;
+			goto end;
+		}
+		memcpy(date_buf, start, end - start);
+		year = simple_strtoul(date_buf, NULL, 10);
+		if (year < 1970) {
+			printf("boota: invalid boot security patch level!\n");
+			ret = -1;
+			goto end;
+		}
+
+		/* Month */
+		start = end + 1;
+		end = strchr(start, '-');
+		if (!end) {
+			printf("boota: invalid boot security patch level!\n");
+			ret = -1;
+			goto end;
+		}
+		memset(date_buf, 0, sizeof(date_buf));
+		memcpy(date_buf, start, end - start);
+		month = simple_strtoul(date_buf, NULL, 10);
+		if ((month < 1) || (month > 12)) {
+			printf("boota: invalid boot security patch level!\n");
+			ret = -1;
+			goto end;
+		}
+
+		/* Day */
+		start = end + 1;
+		memset(date_buf, 0, sizeof(date_buf));
+		memcpy(date_buf, start, strlen(start));
+		day = simple_strtoul(date_buf, NULL, 10);
+		if ((day < 1) || (day > 31)) {
+			printf("boota: invalid boot security patch level!\n");
+			ret = -1;
+			goto end;
+		}
+		trimmed_patch_level = year * 10000 + month * 100 + day;
+
+		/* Set the patch level to secure world */
+		if (trusty_set_boot_patch_level(trimmed_patch_level)) {
+			printf("boota: set boot patch level failed.\n");
+			ret = -1;
+			goto end;
+		}
+
+		ret = 0;
+	} else {
+		printf("No boot patch level found!\n");
+		ret = 0;
+	}
+
+end:
+	if (vbmeta_data != NULL)
+		free(vbmeta_data);
+
+	return ret;
+}
+#endif
+
+#if defined(CONFIG_AVB_SUPPORT) && defined(CONFIG_MMC)
+/* we can use avb to verify Trusty if we want */
+const char *requested_partitions_boot[] = {"boot", "dtbo", "vendor_boot", "init_boot", NULL};
+const char *requested_partitions_recovery[] = {"recovery", NULL};
+
+static int get_boot_header_version(void)
+{
+	size_t size;
+	struct andr_img_hdr hdr;
+	char partition_name[20];
+
+#ifdef CONFIG_ANDROID_AB_SUPPORT
+	int target_slot;
+	struct bootloader_control ab_data;
+	char* slot_suffixes[2] = {"_a", "_b"};
+
+	if (fsl_avb_ab_ops.read_ab_metadata(&fsl_avb_ab_ops, &ab_data) !=
+					    AVB_IO_RESULT_OK) {
+		printf("Read A/B metadata fail!\n");
+		return false;
+	}
+	target_slot = get_curr_slot(&ab_data);
+	sprintf(partition_name, "boot%s", slot_suffixes[target_slot]);
+#else
+	sprintf(partition_name, "boot");
+#endif
+
+	/* Read boot header to find the version */
+	if (fsl_avb_ops.read_from_partition(&fsl_avb_ops, partition_name,
+					    0, sizeof(struct andr_img_hdr),
+					    (void *)&hdr, &size)) {
+		printf("%s load error!\n", partition_name);
+		return -1;
+	}
+
+	return hdr.header_version;
+}
+
+static int find_partition_data_by_name(char* part_name,
+		AvbSlotVerifyData* avb_out_data, AvbPartitionData** avb_loadpart)
+{
+	int num = 0;
+	AvbPartitionData* loadpart = NULL;
+
+	for (num = 0; num < avb_out_data->num_loaded_partitions; num++) {
+		loadpart = &(avb_out_data->loaded_partitions[num]);
+		if (!(strncmp(loadpart->partition_name,
+			part_name, strlen(part_name)))) {
+			*avb_loadpart = loadpart;
+			break;
+		}
+	}
+	if (num == avb_out_data->num_loaded_partitions) {
+		printf("Error! Can't find %s partition from avb partition data!\n",
+				part_name);
+		return -1;
+	}
+	else
+		return 0;
+}
+
+bool __weak is_power_key_pressed(void) {
+	return false;
+}
+
+int do_boota(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) {
+
+	u32 avb_metric;
+	u32 kernel_image_size = 0;
+	u32 ramdisk_size;
+	ulong kernel_addr;
+	ulong ramdisk_addr;
+	int boot_header_version = 0;
+	bool check_image_arm64 =  false;
+	bool is_recovery_mode = false;
+	bool with_init_boot = false;
+
+	/* 'hdr' should point to boot.img */
+	struct andr_img_hdr *hdr = NULL;
+	struct boot_img_hdr_v3 *hdr_v3 = NULL;
+	struct vendor_boot_img_hdr_v3 *vendor_boot_hdr_v3 = NULL;
+	struct boot_img_hdr_v4 *hdr_v4 = NULL;
+	struct boot_img_hdr_v4 *init_boot_hdr_v4 = NULL;
+	struct vendor_boot_img_hdr_v4 *vendor_boot_hdr_v4 = NULL;
+
+	AvbABFlowResult avb_result;
+	AvbSlotVerifyData *avb_out_data = NULL;
+	AvbPartitionData *avb_loadpart = NULL;
+	AvbPartitionData *avb_vendorboot = NULL;
+	AvbPartitionData *avb_initboot = NULL;
+
+	/* get bootmode, default to boot "boot" */
+	if (argc > 1) {
+		is_recovery_mode =
+			(strncmp(argv[1], "recovery", sizeof("recovery")) != 0) ? false: true;
+		if (is_recovery_mode)
+			printf("Will boot from recovery!\n");
+	}
+
+	/* check lock state */
+	FbLockState lock_status = fastboot_get_lock_stat();
+	if (lock_status == FASTBOOT_LOCK_ERROR) {
+		printf("In boota get fastboot lock status error. Set lock status\n");
+		fastboot_set_lock_stat(FASTBOOT_LOCK);
+		lock_status = FASTBOOT_LOCK;
+	}
+
+	bool allow_fail = (lock_status == FASTBOOT_UNLOCK ? true : false);
+	avb_metric = get_timer(0);
+
+	/*
+	 * Vendor_boot partition will be present starting from boot header version 3.
+	 */
+	boot_header_version = get_boot_header_version();
+	if (boot_header_version < 0 || boot_header_version > 4) {
+		printf("boot header version not supported!\n");
+		goto fail;
+	} else if (boot_header_version < 3) {
+		requested_partitions_boot[2] = NULL;
+	} else if (boot_header_version == 4) {
+		if (fastboot_flash_find_ptn("init_boot_a") == NULL) {
+			with_init_boot = false;
+			requested_partitions_boot[3] = NULL;
+		} else
+			with_init_boot = true;
+	}
+
+	/* For imx6 on Android, we don't have a/b slot and we want to verify boot/recovery with AVB.
+	 * For imx8 and Android Things we don't have recovery and support a/b slot for boot */
+#ifdef CONFIG_DUAL_BOOTLOADER
+	/* We will only verify single one slot which has been selected in SPL */
+	avb_result = avb_flow_dual_uboot(&fsl_avb_ab_ops, requested_partitions_boot, allow_fail,
+			AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE, &avb_out_data);
+
+	/* Reboot if current slot is not bootable. */
+	if (avb_result == AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS) {
+		printf("boota: slot verify fail!\n");
+		do_reset(NULL, 0, 0, NULL);
+	}
+#else /* CONFIG_DUAL_BOOTLOADER */
+#ifdef CONFIG_ANDROID_AB_SUPPORT
+	/* we can use avb to verify Trusty if we want */
+	avb_result = avb_ab_flow_fast(&fsl_avb_ab_ops, requested_partitions_boot, allow_fail,
+			AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE, &avb_out_data);
+#else /* CONFIG_ANDROID_AB_SUPPORT */
+	/* For imx6/7 devices. */
+	if (is_recovery_mode) {
+		avb_result = avb_single_flow(&fsl_avb_ab_ops, requested_partitions_recovery, allow_fail,
+				AVB_HASHTREE_ERROR_MODE_RESTART, &avb_out_data);
+	} else {
+		avb_result = avb_single_flow(&fsl_avb_ab_ops, requested_partitions_boot, allow_fail,
+				AVB_HASHTREE_ERROR_MODE_RESTART, &avb_out_data);
+	}
+#endif /* CONFIG_ANDROID_AB_SUPPORT */
+#endif /* CONFIG_DUAL_BOOTLOADER */
+
+	/* get the duration of avb */
+	metrics.avb = get_timer(avb_metric);
+
+	/* Parse the avb data */
+	if ((avb_result == AVB_AB_FLOW_RESULT_OK) ||
+			(avb_result == AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR)) {
+		if (avb_out_data == NULL)
+			goto fail;
+		/* We may have more than one partition loaded by AVB, find the boot partition first.*/
+#ifdef CONFIG_SYSTEM_RAMDISK_SUPPORT
+		if (find_partition_data_by_name("boot", avb_out_data, &avb_loadpart))
+			goto fail;
+		if ((boot_header_version >= 3) &&
+			find_partition_data_by_name("vendor_boot", avb_out_data, &avb_vendorboot))
+			goto fail;
+		if (with_init_boot &&
+			find_partition_data_by_name("init_boot", avb_out_data, &avb_initboot))
+			goto fail;
+#else
+		if (is_recovery_mode) {
+			if (find_partition_data_by_name("recovery", avb_out_data, &avb_loadpart))
+				goto fail;
+		} else {
+			if (find_partition_data_by_name("boot", avb_out_data, &avb_loadpart))
+				goto fail;
+		}
+#endif
+
+		assert(avb_loadpart != NULL);
+
+		/* boot image is already read by avb */
+		if (boot_header_version == 4) {
+			assert(avb_vendorboot != NULL);
+			hdr_v4 = (struct boot_img_hdr_v4 *)avb_loadpart->data;
+			vendor_boot_hdr_v4 = (struct vendor_boot_img_hdr_v4 *)avb_vendorboot->data;
+			if (avb_initboot)
+				init_boot_hdr_v4 = (struct boot_img_hdr_v4 *)avb_initboot->data;
+			/* check the header magic, same for boot header v3 and v4 */
+			if (android_image_check_header_v3(hdr_v4->magic, vendor_boot_hdr_v4->magic)) {
+				printf("boota: bad boot/vendor_boot image magic\n");
+				goto fail;
+			}
+		} else if (boot_header_version == 3) {
+			assert(avb_vendorboot != NULL);
+			hdr_v3 = (struct boot_img_hdr_v3 *)avb_loadpart->data;
+			vendor_boot_hdr_v3 = (struct vendor_boot_img_hdr_v3 *)avb_vendorboot->data;
+			if (android_image_check_header_v3(hdr_v3->magic, vendor_boot_hdr_v3->magic)) {
+				printf("boota: bad boot/vendor_boot image magic\n");
+				goto fail;
+			}
+		} else {
+			hdr = (struct andr_img_hdr *)avb_loadpart->data;
+			if (android_image_check_header(hdr)) {
+				printf("boota: bad boot image magic\n");
+				goto fail;
+			}
+		}
+
+		if (avb_result == AVB_AB_FLOW_RESULT_OK)
+			printf(" verify OK, boot '%s%s'\n",
+					avb_loadpart->partition_name, avb_out_data->ab_suffix);
+		else {
+			printf(" verify FAIL, state: UNLOCK\n");
+			printf(" boot '%s%s' still\n",
+					avb_loadpart->partition_name, avb_out_data->ab_suffix);
+		}
+		char bootargs_sec[ANDR_BOOT_EXTRA_ARGS_SIZE];
+		if (lock_status == FASTBOOT_LOCK) {
+			snprintf(bootargs_sec, sizeof(bootargs_sec),
+					"androidboot.verifiedbootstate=green androidboot.flash.locked=1 androidboot.slot_suffix=%s ",
+					avb_out_data->ab_suffix);
+		} else {
+			snprintf(bootargs_sec, sizeof(bootargs_sec),
+					"androidboot.verifiedbootstate=orange androidboot.flash.locked=0 androidboot.slot_suffix=%s ",
+					avb_out_data->ab_suffix);
+		}
+		if (avb_out_data->cmdline != NULL)
+			strcat(bootargs_sec, avb_out_data->cmdline);
+#if defined(CONFIG_ANDROID_DYNAMIC_PARTITION) && defined(CONFIG_SYSTEM_RAMDISK_SUPPORT)
+		/* for the condition dynamic partition is used , recovery ramdisk is used to boot
+		 * up Android, in this condition, "androidboot.force_normal_boot=1" is needed */
+		if(!is_recovery_mode) {
+			strcat(bootargs_sec, " androidboot.force_normal_boot=1");
+		}
+#endif
+		env_set("bootargs_sec", bootargs_sec);
+#if !defined(CONFIG_ANDROID_DYNAMIC_PARTITION) && defined(CONFIG_SYSTEM_RAMDISK_SUPPORT)
+		if(!is_recovery_mode) {
+			if(avb_out_data->cmdline != NULL && strstr(avb_out_data->cmdline, "root="))
+				fastboot_setup_system_boot_args(avb_out_data->ab_suffix, false);
+			else
+				fastboot_setup_system_boot_args(avb_out_data->ab_suffix, true);
+		}
+#endif /* CONFIG_ANDROID_AUTO_SUPPORT */
+	} else {
+		/* Fall into fastboot mode if get unacceptable error from avb
+		 * or verify fail in lock state.
+		 */
+		if (lock_status == FASTBOOT_LOCK)
+			printf(" verify FAIL, state: LOCK\n");
+
+		goto fail;
+	}
+
+	if (boot_header_version == 4) {
+		kernel_addr = vendor_boot_hdr_v4->kernel_addr;
+		ramdisk_addr = vendor_boot_hdr_v4->ramdisk_addr;
+	} else if (boot_header_version == 3) {
+		kernel_addr = vendor_boot_hdr_v3->kernel_addr;
+		ramdisk_addr = vendor_boot_hdr_v3->ramdisk_addr;
+	} else {
+		kernel_addr = hdr->kernel_addr;
+		ramdisk_addr = hdr->ramdisk_addr;
+	}
+
+	/*
+	 * Start decompress & load kernel image. If we are using uncompressed kernel image,
+	 * copy it directly to physical dram address. If we are using compressed lz4 kernel
+	 * image, we need to decompress the kernel image first.
+	 */
+	if (boot_header_version == 4) {
+		if (image_arm64((void *)((ulong)hdr_v4 + 4096))) {
+			memcpy((void *)kernel_addr,
+				(void *)((ulong)hdr_v4 + 4096), hdr_v4->kernel_size);
+		} else if (IS_ENABLED(CONFIG_LZ4)) {
+			size_t lz4_len = MAX_KERNEL_LEN;
+			if (ulz4fn((void *)((ulong)hdr_v4 + 4096),
+				hdr_v4->kernel_size, (void *)kernel_addr, &lz4_len) != 0) {
+				printf("Decompress kernel fail!\n");
+				goto fail;
+			}
+		} else {
+			printf("Wrong kernel image! Please check if you need to enable 'CONFIG_LZ4'\n");
+			goto fail;
+		}
+		kernel_image_size = kernel_size((void *)kernel_addr);
+	} else if (boot_header_version == 3) {
+		if (image_arm64((void *)((ulong)hdr_v3 + 4096))) {
+			memcpy((void *)kernel_addr,
+				(void *)((ulong)hdr_v3 + 4096), hdr_v3->kernel_size);
+		} else if (IS_ENABLED(CONFIG_LZ4)) {
+			size_t lz4_len = MAX_KERNEL_LEN;
+			if (ulz4fn((void *)((ulong)hdr_v3 + 4096),
+				hdr_v3->kernel_size, (void *)kernel_addr, &lz4_len) != 0) {
+				printf("Decompress kernel fail!\n");
+				goto fail;
+			}
+		} else {
+			printf("Wrong kernel image! Please check if you need to enable 'CONFIG_LZ4'\n");
+			goto fail;
+		}
+		kernel_image_size = kernel_size((void *)kernel_addr);
+	} else {
+#if defined (CONFIG_ARCH_IMX8) || defined (CONFIG_ARCH_IMX8M)
+		if (image_arm64((void *)((ulong)hdr + hdr->page_size))) {
+			memcpy((void *)kernel_addr,
+				(void *)((ulong)hdr + hdr->page_size), hdr->kernel_size);
+		} else if (IS_ENABLED(CONFIG_LZ4)) {
+			size_t lz4_len = MAX_KERNEL_LEN;
+			if (ulz4fn((void *)((ulong)hdr + hdr->page_size),
+				hdr->kernel_size, (void *)kernel_addr, &lz4_len) != 0) {
+				printf("Decompress kernel fail!\n");
+				goto fail;
+			}
+		} else {
+			printf("Wrong kernel image! Please check if you need to enable 'CONFIG_LZ4'\n");
+			goto fail;
+		}
+
+		kernel_image_size = kernel_size((void *)kernel_addr);
+#else /* CONFIG_ARCH_IMX8 || CONFIG_ARCH_IMX8M */
+		/* copy kernel image and boot header to hdr->kernel_addr - hdr->page_size */
+		memcpy((void *)(ulong)(hdr->kernel_addr - hdr->page_size), (void *)hdr,
+				hdr->page_size + ALIGN(hdr->kernel_size, hdr->page_size));
+#endif /* CONFIG_ARCH_IMX8 || CONFIG_ARCH_IMX8M */
+	}
+
+	/* Start loading the dtb file */
+	u32 fdt_addr = 0;
+	u32 fdt_size = 0;
+	struct dt_table_header *dt_img = NULL;
+
+	/* Check arm64 image */
+	check_image_arm64  = image_arm64((void *)kernel_addr);
+
+	/* Kernel addr may need relocatition, put the dtb right after the kernel image. */
+	if (check_image_arm64) {
+		ulong relocated_addr;
+
+		relocated_addr = kernel_relocate_addr(kernel_addr);
+		fdt_addr = relocated_addr + kernel_image_size + 1024; /* 1K gap */
+	} else {
+		/* Let's reserve 64 MB for arm32 case */
+		fdt_addr = (ulong)((ulong)(hdr->kernel_addr) + 64 * 1024 * 1024);
+	}
+
+#ifdef CONFIG_SYSTEM_RAMDISK_SUPPORT
+	/* It means boot.img(recovery) do not include dtb, it need load dtb from partition */
+	if (find_partition_data_by_name("dtbo",
+				avb_out_data, &avb_loadpart)) {
+		goto fail;
+	} else
+		dt_img = (struct dt_table_header *)avb_loadpart->data;
+#else
+	/* recovery.img include dts while boot.img use dtbo */
+	if (is_recovery_mode) {
+		if (hdr->header_version != 1) {
+			printf("boota: boot image header version error!\n");
+			goto fail;
+		}
+
+		dt_img = (struct dt_table_header *)((void *)(ulong)hdr +
+					hdr->page_size +
+					ALIGN(hdr->kernel_size, hdr->page_size) +
+					ALIGN(hdr->ramdisk_size, hdr->page_size) +
+					ALIGN(hdr->second_size, hdr->page_size));
+	} else if (find_partition_data_by_name("dtbo",
+					avb_out_data, &avb_loadpart)) {
+		goto fail;
+	} else
+		dt_img = (struct dt_table_header *)avb_loadpart->data;
+#endif
+
+	if (be32_to_cpu(dt_img->magic) != DT_TABLE_MAGIC) {
+		printf("boota: bad dt table magic %08x\n",
+				be32_to_cpu(dt_img->magic));
+		goto fail;
+	} else if (!be32_to_cpu(dt_img->dt_entry_count)) {
+		printf("boota: no dt entries\n");
+		goto fail;
+	}
+
+	struct dt_table_entry *dt_entry;
+	dt_entry = (struct dt_table_entry *)((ulong)dt_img +
+			be32_to_cpu(dt_img->dt_entries_offset));
+	fdt_size = be32_to_cpu(dt_entry->dt_size);
+	memcpy((void *)(ulong)fdt_addr, (void *)((ulong)dt_img +
+			be32_to_cpu(dt_entry->dt_offset)), fdt_size);
+
+
+	/*
+	 * Start loading ramdisk. */
+	/* Load ramdisk except for Android Auto which doesn't support dynamic partition,
+	 * it will only load ramdisk in recovery mode.
+	 */
+	/* Check if we have overlap between ramdisk, kernel and dtb */
+	if ((ramdisk_addr >= kernel_addr) && (ramdisk_addr < ALIGN(fdt_addr + fdt_size, 4096))) {
+		ulong ramdisk_addr_relocate = (ulong)ALIGN(fdt_addr + fdt_size, 4096);
+
+		printf("boota: ramdisk overlap detected!!! ");
+		printf("redirecting ramdisk from 0x%08x to 0x%08x\n", (uint32_t)ramdisk_addr, (uint32_t)ramdisk_addr_relocate);
+
+		/* relocate ramdisk*/
+		ramdisk_addr = ramdisk_addr_relocate;
+	}
+
+	if (boot_header_version == 4) {
+		/*
+		 * concatenate vendor_boot ramdisk and boot ramdisk, load the
+		 * whole ramdisk directly as we don't have multiple ramdisk.
+		 */
+		memcpy((void *)ramdisk_addr, (void *)(ulong)vendor_boot_hdr_v4 +
+			ALIGN(sizeof(struct vendor_boot_img_hdr_v4), vendor_boot_hdr_v4->page_size),
+			vendor_boot_hdr_v4->vendor_ramdisk_size);
+
+		if (with_init_boot) {
+			memcpy((void *)ramdisk_addr + vendor_boot_hdr_v4->vendor_ramdisk_size,
+				(void *)(ulong)init_boot_hdr_v4 + 4096 + ALIGN(init_boot_hdr_v4->kernel_size, 4096),
+				init_boot_hdr_v4->ramdisk_size);
+			ramdisk_size = vendor_boot_hdr_v4->vendor_ramdisk_size + init_boot_hdr_v4->ramdisk_size;
+		} else {
+			memcpy((void *)ramdisk_addr + vendor_boot_hdr_v4->vendor_ramdisk_size,
+				(void *)(ulong)hdr_v4 + 4096 + ALIGN(hdr_v4->kernel_size, 4096),
+				hdr_v4->ramdisk_size);
+			ramdisk_size = vendor_boot_hdr_v4->vendor_ramdisk_size + hdr_v4->ramdisk_size;
+		}
+
+		/* append build time bootconfig */
+		void *bootconfig_addr = (void *)(ulong)vendor_boot_hdr_v4 +
+					ALIGN(sizeof(struct vendor_boot_img_hdr_v4), vendor_boot_hdr_v4->page_size) +
+					ALIGN(vendor_boot_hdr_v4->vendor_ramdisk_size, vendor_boot_hdr_v4->page_size) +
+					ALIGN(vendor_boot_hdr_v4->dtb_size, vendor_boot_hdr_v4->page_size) +
+					ALIGN(vendor_boot_hdr_v4->vendor_ramdisk_table_size, vendor_boot_hdr_v4->page_size);
+		void *bootconfig_start = (void *)ramdisk_addr + ramdisk_size;
+		memcpy(bootconfig_start, bootconfig_addr, vendor_boot_hdr_v4->bootconfig_size);
+
+		/* append run time bootconfig */
+		uint32_t bootconfig_size;
+		if (append_runtime_bootconfig(bootconfig_start +
+						vendor_boot_hdr_v4->bootconfig_size,
+						&bootconfig_size, (void *)(ulong)fdt_addr) < 0) {
+			printf("boota: append runtime bootconfig failed!\n");
+			goto fail;
+		}
+		bootconfig_size += vendor_boot_hdr_v4->bootconfig_size;
+		bootconfig_size += add_bootconfig_trailer((uint64_t)bootconfig_start, bootconfig_size);
+
+		/* update ramdisk size */
+		ramdisk_size += bootconfig_size;
+	} else if (boot_header_version == 3) {
+		/*
+		 * concatenate vendor_boot ramdisk and boot ramdisk.
+		 */
+		memcpy((void *)ramdisk_addr, (void *)(ulong)vendor_boot_hdr_v3 +
+			ALIGN(sizeof(struct vendor_boot_img_hdr_v3), vendor_boot_hdr_v3->page_size),
+			vendor_boot_hdr_v3->vendor_ramdisk_size);
+		memcpy((void *)ramdisk_addr + vendor_boot_hdr_v3->vendor_ramdisk_size,
+			(void *)(ulong)hdr_v3 + 4096 + ALIGN(hdr_v3->kernel_size, 4096),
+			hdr_v3->ramdisk_size);
+		ramdisk_size = vendor_boot_hdr_v3->vendor_ramdisk_size + hdr_v3->ramdisk_size;
+	} else {
+#if !defined(CONFIG_SYSTEM_RAMDISK_SUPPORT) || defined(CONFIG_ANDROID_DYNAMIC_PARTITION)
+		memcpy((void *)ramdisk_addr, (void *)(ulong)hdr + hdr->page_size +
+			ALIGN(hdr->kernel_size, hdr->page_size), hdr->ramdisk_size);
+#else
+		if (is_recovery_mode)
+			memcpy((void *)ramdisk_addr, (void *)(ulong)hdr + hdr->page_size +
+				ALIGN(hdr->kernel_size, hdr->page_size), hdr->ramdisk_size);
+#endif
+		ramdisk_size = hdr->ramdisk_size;
+	}
+
+	/* Combine cmdline */
+	if (boot_header_version == 4) {
+		android_image_get_kernel_v3((struct boot_img_hdr_v3 *)hdr_v4,
+						(struct vendor_boot_img_hdr_v3 *)vendor_boot_hdr_v4, true);
+	} else if (boot_header_version == 3) {
+		android_image_get_kernel_v3(hdr_v3, vendor_boot_hdr_v3, false);
+	} else {
+		if (check_image_arm64) {
+			android_image_get_kernel(hdr, 0, NULL, NULL);
+		} else {
+			kernel_addr = (ulong)(hdr->kernel_addr - hdr->page_size);
+		}
+	}
+
+	/* Dump image info */
+	printf("kernel   @ %08x (%d)\n", (uint32_t)kernel_addr, kernel_image_size);
+	printf("ramdisk  @ %08x (%d)\n", (uint32_t)ramdisk_addr, ramdisk_size);
+	if (fdt_size)
+		printf("fdt      @ %08x (%d)\n", fdt_addr, fdt_size);
+
+	/* Set boot parameters */
+	char boot_addr_start[12];
+	char ramdisk_addr_start[25];
+	char fdt_addr_start[12];
+
+	char *boot_args[] = { NULL, boot_addr_start, ramdisk_addr_start, fdt_addr_start};
+	if (check_image_arm64)
+		boot_args[0] = "booti";
+	else
+		boot_args[0] = "bootm";
+
+	sprintf(boot_addr_start, "0x%lx", kernel_addr);
+	sprintf(ramdisk_addr_start, "0x%x:0x%x", (uint32_t)ramdisk_addr, ramdisk_size);
+	sprintf(fdt_addr_start, "0x%x", fdt_addr);
+
+	/* Don't pass ramdisk addr for Android Auto if we are not booting from recovery */
+#if !defined(CONFIG_ANDROID_DYNAMIC_PARTITION) && defined(CONFIG_SYSTEM_RAMDISK_SUPPORT)
+	if (!is_recovery_mode)
+		boot_args[2] = NULL;
+#endif
+
+	/* Show orange warning for unlocked device, press power button to skip. */
+#ifdef CONFIG_AVB_WARNING_LOGO
+	if (fastboot_get_lock_stat() == FASTBOOT_UNLOCK) {
+		int count = 0;
+
+		printf("Device is unlocked, press power key to skip warning logo... \n");
+		if (display_unlock_warning())
+			printf("can't show unlock warning.\n");
+		while ( (count < 10 * CONFIG_AVB_WARNING_TIME_LAST) && !is_power_key_pressed()) {
+			mdelay(100);
+			count++;
+		}
+	}
+#endif
+
+	/* Trusty related operations */
+#ifdef CONFIG_IMX_TRUSTY_OS
+	/* Trusty keymaster needs some parameters before it work */
+	uint32_t os_version;
+	if (boot_header_version == 4)
+		os_version = hdr_v4->os_version;
+	else if (boot_header_version == 3)
+		os_version = hdr_v3->os_version;
+	else
+		os_version = hdr->os_version;
+	if (trusty_setbootparameter(os_version, avb_result, avb_out_data))
+		goto fail;
+
+	set_boot_patch_level(avb_out_data->ab_suffix);
+
+	/* lock the boot status and rollback_idx preventing Linux modify it */
+	trusty_lock_boot_state();
+	/* lock the boot state so linux can't use some hwcrypto commands. */
+	hwcrypto_lock_boot_state();
+	/* put ql-tipc to release resource for Linux */
+	trusty_ipc_shutdown();
+#endif
+
+	/* Free AVB data */
+	if (avb_out_data != NULL)
+		avb_slot_verify_data_free(avb_out_data);
+
+	/* Images are loaded, start to boot. */
+	if (check_image_arm64) {
+#ifdef CONFIG_CMD_BOOTI
+		do_booti(NULL, 0, 4, boot_args);
+#else
+		debug("please enable CONFIG_CMD_BOOTI when kernel are Image");
+#endif
+	} else {
+		do_bootm(NULL, 0, 4, boot_args);
+	}
+
+	/* This only happens if image is somehow faulty so we start over */
+	do_reset(NULL, 0, 0, NULL);
+
+	return 1;
+
+fail:
+	/* avb has no recovery */
+	if (avb_out_data != NULL)
+		avb_slot_verify_data_free(avb_out_data);
+
+	return run_command("fastboot 0", 0);
+}
+
+U_BOOT_CMD(
+	boota,	2,	1,	do_boota,
+	"boota   - boot android bootimg \n",
+	"boot from current mmc with avb verify\n"
+);
+
+#endif /* CONFIG_AVB_SUPPORT */
+#endif	/* CONFIG_CMD_BOOTA */
diff --git a/drivers/fastboot/fb_fsl/fb_fsl_command.c b/drivers/fastboot/fb_fsl/fb_fsl_command.c
new file mode 100644
index 00000000000..11224728a84
--- /dev/null
+++ b/drivers/fastboot/fb_fsl/fb_fsl_command.c
@@ -0,0 +1,1162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <asm/mach-imx/sys_proto.h>
+#include <fb_fsl.h>
+#include <fastboot.h>
+#include <fastboot-internal.h>
+#include <mmc.h>
+#include <android_image.h>
+#include <asm/bootm.h>
+#include <nand.h>
+#include <part.h>
+#include <sparse_format.h>
+#include <image-sparse.h>
+#include <image.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/setup.h>
+#include <env.h>
+#ifdef CONFIG_ANDROID_RECOVERY
+#include <recovery.h>
+#endif
+
+#ifdef CONFIG_BCB_SUPPORT
+#include "bcb.h"
+#endif
+
+#ifdef CONFIG_AVB_SUPPORT
+#include <dt_table.h>
+#include <fsl_avb.h>
+#endif
+
+#ifdef CONFIG_ANDROID_THINGS_SUPPORT
+#include <asm-generic/gpio.h>
+#include <asm/mach-imx/gpio.h>
+#include "../lib/avb/fsl/fsl_avbkey.h"
+#include "../arch/arm/include/asm/mach-imx/hab.h"
+#endif
+
+#if defined(CONFIG_FASTBOOT_LOCK)
+#include "fastboot_lock_unlock.h"
+#endif
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#include "u-boot/sha256.h"
+#include "trusty/rpmb.h"
+#include <trusty/libtipc.h>
+#endif
+
+#include "fb_fsl_common.h"
+#include "fb_fsl_virtual_ab.h"
+
+#define EP_BUFFER_SIZE			4096
+
+/**
+ * fastboot_bytes_received - number of bytes received in the current download
+ */
+static u32 fastboot_bytes_received;
+
+/**
+ * fastboot_bytes_expected - number of bytes expected in the current download
+ */
+static u32 fastboot_bytes_expected;
+
+/* Write the bcb with fastboot bootloader commands */
+static void enable_fastboot_command(void)
+{
+#ifdef CONFIG_BCB_SUPPORT
+	char fastboot_command[32] = {0};
+	strncpy(fastboot_command, FASTBOOT_BCB_CMD, 31);
+	bcb_write_command(fastboot_command);
+#endif
+}
+
+#ifdef CONFIG_ANDROID_RECOVERY
+/* Write the recovery options with fastboot bootloader commands */
+static void enable_recovery_fastboot(void)
+{
+#ifdef CONFIG_BCB_SUPPORT
+	char msg[32] = {0};
+	strncpy(msg, RECOVERY_BCB_CMD, 31);
+	bcb_write_command(msg);
+	strncpy(msg, RECOVERY_FASTBOOT_ARG, 31);
+	bcb_write_recovery_opt(msg);
+#endif
+}
+#endif
+
+/* Get the Boot mode from BCB cmd or Key pressed */
+static FbBootMode fastboot_get_bootmode(void)
+{
+	int boot_mode = BOOTMODE_NORMAL;
+#ifdef CONFIG_ANDROID_RECOVERY
+	if(is_recovery_key_pressing()) {
+		boot_mode = BOOTMODE_RECOVERY_KEY_PRESSED;
+		return boot_mode;
+	}
+#endif
+#ifdef CONFIG_BCB_SUPPORT
+	int ret = 0;
+	char command[32];
+	ret = bcb_read_command(command);
+	if (ret < 0) {
+		printf("read command failed\n");
+		return boot_mode;
+	}
+	if (!strcmp(command, FASTBOOT_BCB_CMD)) {
+		boot_mode = BOOTMODE_FASTBOOT_BCB_CMD;
+	}
+#ifdef CONFIG_ANDROID_RECOVERY
+	else if (!strcmp(command, RECOVERY_BCB_CMD)) {
+		boot_mode = BOOTMODE_RECOVERY_BCB_CMD;
+	}
+#endif
+
+	/* Clean the mode once its read out,
+	   no matter what in the mode string */
+	memset(command, 0, 32);
+	bcb_write_command(command);
+#endif
+	return boot_mode;
+}
+
+/* export to lib_arm/board.c */
+void fastboot_run_bootmode(void)
+{
+	FbBootMode boot_mode = fastboot_get_bootmode();
+	switch(boot_mode){
+	case BOOTMODE_FASTBOOT_BCB_CMD:
+		/* Make the boot into fastboot mode*/
+		puts("Fastboot: Got bootloader commands!\n");
+		run_command("fastboot 0", 0);
+		break;
+#ifdef CONFIG_ANDROID_RECOVERY
+	case BOOTMODE_RECOVERY_BCB_CMD:
+	case BOOTMODE_RECOVERY_KEY_PRESSED:
+		/* Make the boot into recovery mode */
+		puts("Fastboot: Got Recovery key pressing or recovery commands!\n");
+		board_recovery_setup();
+		break;
+#endif
+	default:
+		/* skip special mode boot*/
+		puts("Fastboot: Normal\n");
+		break;
+	}
+}
+
+
+
+/**
+ * okay() - Send bare OKAY response
+ *
+ * @cmd_parameter: Pointer to command parameter
+ * @response: Pointer to fastboot response buffer
+ *
+ * Send a bare OKAY fastboot response. This is used where the command is
+ * valid, but all the work is done after the response has been sent (e.g.
+ * boot, reboot etc.)
+ */
+static void okay(char *cmd_parameter, char *response)
+{
+	fastboot_okay(NULL, response);
+}
+
+/**
+ * getvar() - Read a config/version variable
+ *
+ * @cmd_parameter: Pointer to command parameter
+ * @response: Pointer to fastboot response buffer
+ */
+static void getvar(char *cmd_parameter, char *response)
+{
+	fastboot_getvar(cmd_parameter, response);
+}
+
+/**
+ * reboot_bootloader() - Sets reboot bootloader flag.
+ *
+ * @cmd_parameter: Pointer to command parameter
+ * @response: Pointer to fastboot response buffer
+ */
+static void reboot_bootloader(char *cmd_parameter, char *response)
+{
+	enable_fastboot_command();
+
+	if (fastboot_set_reboot_flag(FASTBOOT_REBOOT_REASON_BOOTLOADER))
+		fastboot_fail("Cannot set reboot flag", response);
+	else
+		fastboot_okay(NULL, response);
+}
+
+#ifdef CONFIG_ANDROID_RECOVERY
+/**
+ * reboot_fastboot() - Sets reboot fastboot flag.
+ *
+ * @cmd_parameter: Pointer to command parameter
+ * @response: Pointer to fastboot response buffer
+ */
+static void reboot_fastboot(char *cmd_parameter, char *response)
+{
+	enable_recovery_fastboot();
+
+	if (fastboot_set_reboot_flag(FASTBOOT_REBOOT_REASON_FASTBOOTD))
+		fastboot_fail("Cannot set reboot flag", response);
+	else
+		fastboot_okay(NULL, response);
+}
+#endif
+
+static void upload(char *cmd_parameter, char *response)
+{
+	if (!fastboot_bytes_received || fastboot_bytes_received > (EP_BUFFER_SIZE * 32)) {
+		fastboot_fail("", response);
+		return;
+	}
+
+	printf("Will upload %d bytes.\n", fastboot_bytes_received);
+	snprintf(response, FASTBOOT_RESPONSE_LEN, "DATA%08x", fastboot_bytes_received);
+	fastboot_tx_write_more(response);
+
+	fastboot_tx_write((const char *)(fastboot_buf_addr), fastboot_bytes_received);
+
+	snprintf(response,FASTBOOT_RESPONSE_LEN, "OKAY");
+	fastboot_tx_write_more(response);
+
+	fastboot_none_resp(response);
+}
+
+/**
+ * fastboot_download() - Start a download transfer from the client
+ *
+ * @cmd_parameter: Pointer to command parameter
+ * @response: Pointer to fastboot response buffer
+ */
+static void download(char *cmd_parameter, char *response)
+{
+	char *tmp;
+
+	if (!cmd_parameter) {
+		fastboot_fail("Expected command parameter", response);
+		return;
+	}
+	fastboot_bytes_received = 0;
+	fastboot_bytes_expected = simple_strtoul(cmd_parameter, &tmp, 16);
+	if (fastboot_bytes_expected == 0) {
+		fastboot_fail("Expected nonzero image size", response);
+		return;
+	}
+	/*
+	 * Nothing to download yet. Response is of the form:
+	 * [DATA|FAIL]$cmd_parameter
+	 *
+	 * where cmd_parameter is an 8 digit hexadecimal number
+	 */
+	if (fastboot_bytes_expected > fastboot_buf_size) {
+		fastboot_fail(cmd_parameter, response);
+	} else {
+		printf("Starting download of %d bytes\n",
+		       fastboot_bytes_expected);
+		fastboot_response("DATA", response, "%s", cmd_parameter);
+	}
+}
+
+/**
+ * fastboot_data_remaining() - return bytes remaining in current transfer
+ *
+ * Return: Number of bytes left in the current download
+ */
+u32 fastboot_data_remaining(void)
+{
+	if (fastboot_bytes_received >= fastboot_bytes_expected)
+		return 0;
+
+	return fastboot_bytes_expected - fastboot_bytes_received;
+}
+
+/**
+ * fastboot_data_download() - Copy image data to fastboot_buf_addr.
+ *
+ * @fastboot_data: Pointer to received fastboot data
+ * @fastboot_data_len: Length of received fastboot data
+ * @response: Pointer to fastboot response buffer
+ *
+ * Copies image data from fastboot_data to fastboot_buf_addr. Writes to
+ * response. fastboot_bytes_received is updated to indicate the number
+ * of bytes that have been transferred.
+ *
+ * On completion sets image_size and ${filesize} to the total size of the
+ * downloaded image.
+ */
+void fastboot_data_download(const void *fastboot_data,
+			    unsigned int fastboot_data_len,
+			    char *response)
+{
+#define BYTES_PER_DOT	0x20000
+	u32 pre_dot_num, now_dot_num;
+
+	if (fastboot_data_len == 0 ||
+	    (fastboot_bytes_received + fastboot_data_len) >
+	    fastboot_bytes_expected) {
+		fastboot_fail("Received invalid data length",
+			      response);
+		return;
+	}
+	/* Download data to fastboot_buf_addr */
+	memcpy(fastboot_buf_addr + fastboot_bytes_received,
+	       fastboot_data, fastboot_data_len);
+
+	pre_dot_num = fastboot_bytes_received / BYTES_PER_DOT;
+	fastboot_bytes_received += fastboot_data_len;
+	now_dot_num = fastboot_bytes_received / BYTES_PER_DOT;
+
+	if (pre_dot_num != now_dot_num) {
+		putc('.');
+		if (!(now_dot_num % 74))
+			putc('\n');
+	}
+	*response = '\0';
+}
+
+/**
+ * fastboot_data_complete() - Mark current transfer complete
+ *
+ * @response: Pointer to fastboot response buffer
+ *
+ * Set image_size and ${filesize} to the total size of the downloaded image.
+ */
+void fastboot_data_complete(char *response)
+{
+	/* Download complete. Respond with "OKAY" */
+	fastboot_okay(NULL, response);
+	printf("\ndownloading of %d bytes finished\n", fastboot_bytes_received);
+	env_set_hex("filesize", fastboot_bytes_received);
+	env_set_hex("fastboot_bytes", fastboot_bytes_received);
+	fastboot_bytes_expected = 0;
+}
+
+#if defined(CONFIG_FASTBOOT_LOCK)
+static int partition_table_valid(void)
+{
+	int status, mmc_no;
+	struct blk_desc *dev_desc;
+#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_ARM64)
+	/* Prevent other partition accessing when no TOS flashed. */
+	if (!tos_flashed)
+		return 0;
+#endif
+	struct disk_partition info;
+	mmc_no = fastboot_devinfo.dev_id;
+	dev_desc = blk_get_dev("mmc", mmc_no);
+	if (dev_desc)
+		status = part_get_info(dev_desc, 1, &info);
+	else
+		status = -1;
+	return (status == 0);
+}
+
+static void wipe_all_userdata(void)
+{
+	char response[FASTBOOT_RESPONSE_LEN];
+
+	/* Erase all user data */
+	printf("Start userdata wipe process....\n");
+	/* Erase /data partition */
+	fastboot_wipe_data_partition();
+
+#if defined (CONFIG_ANDROID_SUPPORT) || defined (CONFIG_ANDROID_AUTO_SUPPORT)
+	/* Erase the misc partition. */
+	process_erase_mmc(FASTBOOT_PARTITION_MISC, response);
+#endif
+
+#ifndef CONFIG_ANDROID_AB_SUPPORT
+	/* Erase the cache partition for legacy imx6/7 */
+	process_erase_mmc(FASTBOOT_PARTITION_CACHE, response);
+#endif
+
+#if defined(AVB_RPMB) && !defined(CONFIG_IMX_TRUSTY_OS)
+	printf("Start stored_rollback_index wipe process....\n");
+	rbkidx_erase();
+	printf("Wipe stored_rollback_index completed.\n");
+#endif
+	process_erase_mmc(FASTBOOT_PARTITION_METADATA, response);
+	printf("Wipe userdata completed.\n");
+}
+
+static FbLockState do_fastboot_unlock(bool force)
+{
+	int status;
+
+	if (fastboot_get_lock_stat() == FASTBOOT_UNLOCK) {
+		printf("The device is already unlocked\n");
+		return FASTBOOT_UNLOCK;
+	}
+	if ((fastboot_lock_enable() == FASTBOOT_UL_ENABLE) || force) {
+		printf("It is able to unlock device. %d\n",fastboot_lock_enable());
+
+#if defined(CONFIG_SECURE_UNLOCK) && defined(CONFIG_IMX_TRUSTY_OS)
+		if ((fastboot_bytes_received == 0) || !hab_is_enabled()) {
+			printf("No unlock credential found or hab is not closed!\n");
+			return FASTBOOT_LOCK_ERROR;
+		} else {
+			char *serial = get_serial();
+			status = trusty_verify_secure_unlock(fastboot_buf_addr,
+								fastboot_bytes_received,
+								(uint8_t *)serial, 16);
+			if (status < 0) {
+				printf("verify secure unlock credential fail due Trusty return %d\n", status);
+				return FASTBOOT_LOCK_ERROR;
+			}
+		}
+#endif
+
+#ifdef CONFIG_VIRTUAL_AB_SUPPORT
+		if (virtual_ab_update_is_merging() ||
+			(virtual_ab_update_is_snapshoted() && !virtual_ab_slot_match())) {
+			printf("Can not erase userdata while a snapshot update is in progress!\n");
+			return FASTBOOT_LOCK_ERROR;
+		}
+#endif
+
+		wipe_all_userdata();
+		status = fastboot_set_lock_stat(FASTBOOT_UNLOCK);
+		if (status < 0)
+			return FASTBOOT_LOCK_ERROR;
+	} else {
+		printf("It is not able to unlock device.");
+		return FASTBOOT_LOCK_ERROR;
+	}
+
+	return FASTBOOT_UNLOCK;
+}
+
+static FbLockState do_fastboot_lock(void)
+{
+	int status;
+
+	if (fastboot_get_lock_stat() == FASTBOOT_LOCK) {
+		printf("The device is already locked\n");
+		return FASTBOOT_LOCK;
+	}
+
+#ifdef CONFIG_VIRTUAL_AB_SUPPORT
+		if (virtual_ab_update_is_merging() ||
+			(virtual_ab_update_is_snapshoted() && !virtual_ab_slot_match())) {
+			printf("Can not erase userdata while a snapshot update is in progress!\n");
+			return FASTBOOT_LOCK_ERROR;
+		}
+#endif
+
+	wipe_all_userdata();
+	status = fastboot_set_lock_stat(FASTBOOT_LOCK);
+	if (status < 0)
+		return FASTBOOT_LOCK_ERROR;
+
+	return FASTBOOT_LOCK;
+}
+
+static bool endswith(char* s, char* subs) {
+	if (!s || !subs)
+		return false;
+	uint32_t len = strlen(s);
+	uint32_t sublen = strlen(subs);
+	if (len < sublen) {
+		return false;
+	}
+	if (strncmp(s + len - sublen, subs, sublen)) {
+		return false;
+	}
+	return true;
+}
+
+static void flashing(char *cmd, char *response)
+{
+	FbLockState status;
+	FbLockEnableResult result;
+	if (endswith(cmd, "lock_critical")) {
+		strcpy(response, "OKAY");
+	}
+#ifdef CONFIG_AVB_ATX
+	else if (endswith(cmd, FASTBOOT_AVB_AT_PERM_ATTR)) {
+		if (avb_atx_fuse_perm_attr(fastboot_buf_addr, fastboot_bytes_received))
+			strcpy(response, "FAILInternal error!");
+		else
+			strcpy(response, "OKAY");
+	} else if (endswith(cmd, FASTBOOT_AT_GET_UNLOCK_CHALLENGE)) {
+		if (avb_atx_get_unlock_challenge(fsl_avb_ops.atx_ops,
+						fastboot_buf_addr, &fastboot_bytes_received))
+			strcpy(response, "FAILInternal error!");
+		else
+			strcpy(response, "OKAY");
+	} else if (endswith(cmd, FASTBOOT_AT_UNLOCK_VBOOT)) {
+		if (at_unlock_vboot_is_disabled()) {
+			printf("unlock vboot already disabled, can't unlock the device!\n");
+			strcpy(response, "FAILunlock vboot already disabled!.");
+		} else {
+#ifdef CONFIG_AT_AUTHENTICATE_UNLOCK
+			if (avb_atx_verify_unlock_credential(fsl_avb_ops.atx_ops,
+								fastboot_buf_addr))
+				strcpy(response, "FAILIncorrect unlock credential!");
+			else {
+#endif
+				status = do_fastboot_unlock(true);
+				if (status != FASTBOOT_LOCK_ERROR)
+					strcpy(response, "OKAY");
+				else
+					strcpy(response, "FAILunlock device failed.");
+#ifdef CONFIG_AT_AUTHENTICATE_UNLOCK
+			}
+#endif
+		}
+	} else if (endswith(cmd, FASTBOOT_AT_LOCK_VBOOT)) {
+		if (perm_attr_are_fused()) {
+			status = do_fastboot_lock();
+			if (status != FASTBOOT_LOCK_ERROR)
+				strcpy(response, "OKAY");
+			else
+				strcpy(response, "FAILlock device failed.");
+		} else
+			strcpy(response, "FAILpermanent attributes not fused!");
+	} else if (endswith(cmd, FASTBOOT_AT_DISABLE_UNLOCK_VBOOT)) {
+		/* This command can only be called after 'oem at-lock-vboot' */
+		status = fastboot_get_lock_stat();
+		if (status == FASTBOOT_LOCK) {
+			if (at_unlock_vboot_is_disabled()) {
+				printf("unlock vboot already disabled!\n");
+				strcpy(response, "OKAY");
+			}
+			else {
+				if (!at_disable_vboot_unlock())
+					strcpy(response, "OKAY");
+				else
+					strcpy(response, "FAILdisable unlock vboot fail!");
+			}
+		} else
+			strcpy(response, "FAILplease lock the device first!");
+	}
+#endif /* CONFIG_AVB_ATX */
+#ifdef CONFIG_ANDROID_THINGS_SUPPORT
+	else if (endswith(cmd, FASTBOOT_BOOTLOADER_VBOOT_KEY)) {
+		strcpy(response, "OKAY");
+	}
+#endif /* CONFIG_ANDROID_THINGS_SUPPORT */
+#ifdef CONFIG_IMX_TRUSTY_OS
+	else if (endswith(cmd, FASTBOOT_GET_CA_REQ)) {
+		uint8_t *ca_output;
+		uint32_t ca_length, cp_length;
+		if (trusty_atap_get_ca_request(fastboot_buf_addr, fastboot_bytes_received,
+						&(ca_output), &ca_length)) {
+			printf("ERROR get_ca_request failed!\n");
+			strcpy(response, "FAILInternal error!");
+		} else {
+			cp_length = min((uint32_t)CONFIG_FASTBOOT_BUF_SIZE, ca_length);
+			memcpy(fastboot_buf_addr, ca_output, cp_length);
+			fastboot_bytes_received = ca_length;
+			strcpy(response, "OKAY");
+		}
+
+	} else if (endswith(cmd, FASTBOOT_SET_CA_RESP)) {
+		if (trusty_atap_set_ca_response(fastboot_buf_addr, fastboot_bytes_received)) {
+			printf("ERROR set_ca_response failed!\n");
+			strcpy(response, "FAILInternal error!");
+		} else
+			strcpy(response, "OKAY");
+	} else if (endswith(cmd, FASTBOOT_SET_RSA_ATTESTATION_KEY_ENC)) {
+		if (trusty_set_attestation_key_enc(fastboot_buf_addr,
+							fastboot_bytes_received,
+							KM_ALGORITHM_RSA)) {
+			printf("ERROR set rsa attestation key failed!\n");
+			strcpy(response, "FAILInternal error!");
+		} else {
+			printf("Set rsa attestation key successfully!\n");
+			strcpy(response, "OKAY");
+		}
+	} else if (endswith(cmd, FASTBOOT_SET_EC_ATTESTATION_KEY_ENC)) {
+		if (trusty_set_attestation_key_enc(fastboot_buf_addr,
+							fastboot_bytes_received,
+							KM_ALGORITHM_EC)) {
+			printf("ERROR set ec attestation key failed!\n");
+			strcpy(response, "FAILInternal error!");
+		} else {
+			printf("Set ec attestation key successfully!\n");
+			strcpy(response, "OKAY");
+		}
+	} else if (endswith(cmd, FASTBOOT_APPEND_RSA_ATTESTATION_CERT_ENC)) {
+		if (trusty_append_attestation_cert_chain_enc(fastboot_buf_addr,
+								fastboot_bytes_received,
+								KM_ALGORITHM_RSA)) {
+			printf("ERROR append rsa attestation cert chain failed!\n");
+			strcpy(response, "FAILInternal error!");
+		} else {
+			printf("Append rsa attestation key successfully!\n");
+			strcpy(response, "OKAY");
+		}
+	}  else if (endswith(cmd, FASTBOOT_APPEND_EC_ATTESTATION_CERT_ENC)) {
+		if (trusty_append_attestation_cert_chain_enc(fastboot_buf_addr,
+								fastboot_bytes_received,
+								KM_ALGORITHM_EC)) {
+			printf("ERROR append ec attestation cert chain failed!\n");
+			strcpy(response, "FAILInternal error!");
+		} else {
+			printf("Append ec attestation key successfully!\n");
+			strcpy(response, "OKAY");
+		}
+	} else if (endswith(cmd, FASTBOOT_SET_RSA_ATTESTATION_KEY)) {
+		if (trusty_set_attestation_key(fastboot_buf_addr,
+						fastboot_bytes_received,
+						KM_ALGORITHM_RSA)) {
+			printf("ERROR set rsa attestation key failed!\n");
+			strcpy(response, "FAILInternal error!");
+		} else {
+			printf("Set rsa attestation key successfully!\n");
+			strcpy(response, "OKAY");
+		}
+	} else if (endswith(cmd, FASTBOOT_SET_EC_ATTESTATION_KEY)) {
+		if (trusty_set_attestation_key(fastboot_buf_addr,
+						fastboot_bytes_received,
+						KM_ALGORITHM_EC)) {
+			printf("ERROR set ec attestation key failed!\n");
+			strcpy(response, "FAILInternal error!");
+		} else {
+			printf("Set ec attestation key successfully!\n");
+			strcpy(response, "OKAY");
+		}
+	} else if (endswith(cmd, FASTBOOT_APPEND_RSA_ATTESTATION_CERT)) {
+		if (trusty_append_attestation_cert_chain(fastboot_buf_addr,
+							fastboot_bytes_received,
+							KM_ALGORITHM_RSA)) {
+			printf("ERROR append rsa attestation cert chain failed!\n");
+			strcpy(response, "FAILInternal error!");
+		} else {
+			printf("Append rsa attestation key successfully!\n");
+			strcpy(response, "OKAY");
+		}
+	}  else if (endswith(cmd, FASTBOOT_APPEND_EC_ATTESTATION_CERT)) {
+		if (trusty_append_attestation_cert_chain(fastboot_buf_addr,
+							fastboot_bytes_received,
+							KM_ALGORITHM_EC)) {
+			printf("ERROR append ec attestation cert chain failed!\n");
+			strcpy(response, "FAILInternal error!");
+		} else {
+			printf("Append ec attestation key successfully!\n");
+			strcpy(response, "OKAY");
+		}
+	}
+#ifdef CONFIG_GENERATE_MPPUBK
+	else if (endswith(cmd, FASTBOOT_GET_MPPUBK)) {
+		if (fastboot_get_mppubk(fastboot_buf_addr, &fastboot_bytes_received)) {
+			printf("ERROR Generate mppubk failed!\n");
+			strcpy(response, "FAILGenerate mppubk failed!");
+		} else {
+			printf("mppubk generated!\n");
+			strcpy(response, "OKAY");
+		}
+	}
+#endif
+	else if (endswith(cmd, FASTBOOT_GET_SERIAL_NUMBER)) {
+		char *serial = get_serial();
+
+		if (!serial)
+			strcpy(response, "FAILSerial number not support!");
+		else {
+			/* Serial number will not exceed 16 bytes.*/
+			strncpy(fastboot_buf_addr, serial, 16);
+			fastboot_bytes_received = 16;
+			printf("Serial number generated!\n");
+			strcpy(response, "OKAY");
+		}
+	} else if (endswith(cmd, FASTBOOT_WV_PROVISION)) {
+		if (hwcrypto_provision_wv_key(fastboot_buf_addr, fastboot_bytes_received)) {
+			printf("ERROR provision widevine keybox failed!\n");
+			strcpy(response, "FAILInternal error!");
+		} else {
+			printf("Provision widevine keybox successfully!\n");
+			strcpy(response, "OKAY");
+		}
+	} else if (endswith(cmd, FASTBOOT_WV_PROVISION_ENC)) {
+		if (hwcrypto_provision_wv_key_enc(fastboot_buf_addr, fastboot_bytes_received)) {
+			printf("ERROR provision widevine keybox failed!\n");
+			strcpy(response, "FAILInternal error!");
+		} else {
+			printf("Provision widevine keybox successfully!\n");
+			strcpy(response, "OKAY");
+		}
+	}
+#ifdef CONFIG_ID_ATTESTATION
+	else if (endswith(cmd, FASTBOOT_SET_ATTESTATION_ID)) {
+		if (trusty_set_attestation_id()) {
+			printf("ERROR set device ids failed!\n");
+			strcpy(response, "FAILSet device ids failed!");
+		} else {
+			printf("Set device ids successfully!\n");
+			strcpy(response, "OKAY");
+		}
+	}
+#endif
+#ifndef CONFIG_AVB_ATX
+	else if (endswith(cmd, FASTBOOT_SET_RPMB_STAGED_KEY)) {
+		if (fastboot_set_rpmb_staged_key(fastboot_buf_addr, fastboot_bytes_received)) {
+			printf("ERROR set rpmb staged key failed!\n");
+			strcpy(response, "FAILset rpmb staged key failed!");
+		} else
+			strcpy(response, "OKAY");
+	} else if (endswith(cmd, FASTBOOT_SET_RPMB_HARDWARE_KEY)) {
+		if (fastboot_set_rpmb_hardware_key()) {
+			printf("ERROR set rpmb hardware key failed!\n");
+			strcpy(response, "FAILset rpmb hardware key failed!");
+		} else
+			strcpy(response, "OKAY");
+	} else if (endswith(cmd, FASTBOOT_ERASE_RPMB)) {
+		if (storage_erase_rpmb()) {
+			printf("ERROR erase rpmb storage failed!\n");
+			strcpy(response, "FAILerase rpmb storage failed!");
+		} else {
+			printf("erase rpmb storage succeed!\n");
+			strcpy(response, "OKAY");
+		}
+	} else if (endswith(cmd, FASTBOOT_SET_VBMETA_PUBLIC_KEY)) {
+		if (avb_set_public_key(fastboot_buf_addr,
+					fastboot_bytes_received))
+			strcpy(response, "FAILcan't set public key!");
+		else
+			strcpy(response, "OKAY");
+	}
+#endif /* !CONFIG_AVB_ATX */
+#endif /* CONFIG_IMX_TRUSTY_OS */
+	else if (endswith(cmd, "unlock_critical")) {
+		strcpy(response, "OKAY");
+	} else if (endswith(cmd, "unlock")) {
+		printf("flashing unlock.\n");
+#ifdef CONFIG_AVB_ATX
+		/* We should do nothing here For Android Things which
+		 * enables the authenticated unlock feature.
+		 */
+		strcpy(response, "OKAY");
+#else
+		status = do_fastboot_unlock(false);
+		if (status != FASTBOOT_LOCK_ERROR)
+			strcpy(response, "OKAY");
+		else
+			strcpy(response, "FAILunlock device failed.");
+#endif
+	} else if (endswith(cmd, "lock")) {
+#ifdef CONFIG_AVB_ATX
+		/* We should do nothing here For Android Things which
+		 * enables the at-lock-vboot feature.
+		 */
+		strcpy(response, "OKAY");
+#else
+		printf("flashing lock.\n");
+		status = do_fastboot_lock();
+		if (status != FASTBOOT_LOCK_ERROR)
+			strcpy(response, "OKAY");
+		else
+			strcpy(response, "FAILlock device failed.");
+#endif
+	} else if (endswith(cmd, "get_unlock_ability")) {
+		result = fastboot_lock_enable();
+		if (result == FASTBOOT_UL_ENABLE) {
+			fastboot_tx_write_more("INFO1");
+			strcpy(response, "OKAY");
+		} else if (result == FASTBOOT_UL_DISABLE) {
+			fastboot_tx_write_more("INFO0");
+			strcpy(response, "OKAY");
+		} else {
+			printf("flashing get_unlock_ability fail!\n");
+			strcpy(response, "FAILget unlock ability failed.");
+		}
+	} else {
+		printf("Unknown flashing command:%s\n", cmd);
+		strcpy(response, "FAILcommand not defined");
+	}
+	fastboot_tx_write_more(response);
+
+	/* Must call fastboot_none_resp before returning from the dispatch function
+	 *  which uses fastboot_tx_write_more
+	 */
+	fastboot_none_resp(response);
+}
+#endif /* CONFIG_FASTBOOT_LOCK */
+
+#ifdef CONFIG_AVB_SUPPORT
+static void set_active_avb(char *cmd, char *response)
+{
+	AvbIOResult ret;
+	int slot = 0;
+
+	if (!cmd) {
+		pr_err("missing slot suffix\n");
+		fastboot_fail("missing slot suffix", response);
+		return;
+	}
+
+#ifdef CONFIG_VIRTUAL_AB_SUPPORT
+	if (virtual_ab_update_is_merging()) {
+		printf("Can not switch slot while snapshot merge is in progress!\n");
+		fastboot_fail("Snapshot merge is in progress!", response);
+		return;
+	}
+
+	/* Only output a warning when the image is snapshoted. */
+	if (virtual_ab_update_is_snapshoted())
+		printf("Warning: changing the active slot with a snapshot applied may cancel the update!\n");
+	else
+		printf("Warning: Virtual A/B is enabled, switch slot may make the system fail to boot. \n");
+#endif
+
+	slot = slotidx_from_suffix(cmd);
+
+	if (slot < 0) {
+		fastboot_fail("err slot suffix", response);
+		return;
+	}
+
+	ret = fsl_avb_ab_mark_slot_active(&fsl_avb_ab_ops, slot);
+	if (ret != AVB_IO_RESULT_OK)
+		fastboot_fail("avb IO error", response);
+	else
+		fastboot_okay(NULL, response);
+
+	return;
+}
+#endif /*CONFIG_AVB_SUPPORT*/
+
+#if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
+static void flash(char *cmd, char *response)
+{
+	if (!cmd) {
+		pr_err("missing partition name");
+		fastboot_fail("missing partition name", response);
+		return;
+	}
+
+	/* Always enable image flash for Android Things. */
+#if defined(CONFIG_FASTBOOT_LOCK) && !defined(CONFIG_AVB_ATX)
+	int status;
+	status = fastboot_get_lock_stat();
+
+	if (status == FASTBOOT_LOCK) {
+		pr_err("device is LOCKed!\n");
+		fastboot_fail("device is locked.", response);
+		return;
+
+	} else if (status == FASTBOOT_LOCK_ERROR) {
+		pr_err("write lock status into device!\n");
+		fastboot_set_lock_stat(FASTBOOT_LOCK);
+		fastboot_fail("device is locked.", response);
+		return;
+	}
+#endif
+
+#ifdef CONFIG_VIRTUAL_AB_SUPPORT
+	if (partition_is_protected_during_merge(cmd)) {
+		printf("Can not flash partition %s while a snapshot update is in progress!\n", cmd);
+		fastboot_fail("Snapshot update is in progress", response);
+		return;
+	}
+#endif
+
+	fastboot_process_flash(cmd, fastboot_buf_addr,
+		fastboot_bytes_received, response);
+
+#ifdef CONFIG_VIRTUAL_AB_SUPPORT
+	/* Cancel virtual AB update after image flash */
+	if (virtual_ab_update_is_merging() || virtual_ab_update_is_snapshoted())
+		virtual_ab_cancel_update();
+#endif
+
+#if defined(CONFIG_FASTBOOT_LOCK)
+	if (strncmp(cmd, "gpt", 3) == 0) {
+		int gpt_valid = 0;
+		int mmc_no;
+		struct blk_desc *dev_desc;
+		mmc_no = fastboot_devinfo.dev_id;
+		dev_desc = blk_get_dev("mmc", mmc_no);
+		if (dev_desc) {
+			if (dev_desc->part_type != PART_TYPE_EFI)
+				dev_desc->part_type = PART_TYPE_EFI;
+		}
+		else {
+			fastboot_fail("", response);
+			return;
+		}
+		gpt_valid = partition_table_valid();
+		/* If gpt is valid, load partitons table into memory.
+		   So if the next command is "fastboot reboot bootloader",
+		   it can find the "misc" partition to r/w. */
+		if(gpt_valid) {
+			fastboot_load_partitions();
+			/* Unlock device if the gpt is valid */
+			do_fastboot_unlock(true);
+		}
+	}
+
+#endif
+}
+
+static void erase(char *cmd, char *response)
+{
+	if (!cmd) {
+		pr_err("missing partition name");
+		fastboot_fail("missing partition name", response);
+		return;
+	}
+
+#if defined(CONFIG_FASTBOOT_LOCK) && !defined(CONFIG_AVB_ATX)
+	FbLockState status;
+	status = fastboot_get_lock_stat();
+	if (status == FASTBOOT_LOCK) {
+		pr_err("device is LOCKed!\n");
+		fastboot_fail("device is locked.", response);
+		return;
+	} else if (status == FASTBOOT_LOCK_ERROR) {
+		pr_err("write lock status into device!\n");
+		fastboot_set_lock_stat(FASTBOOT_LOCK);
+		fastboot_fail("device is locked.", response);
+		return;
+	}
+#endif
+
+#ifdef CONFIG_VIRTUAL_AB_SUPPORT
+	if (partition_is_protected_during_merge(cmd)) {
+		printf("Can not erase partition %s while a snapshot update is in progress!", cmd);
+		fastboot_fail("Snapshot update is in progress", response);
+		return;
+	}
+#endif
+
+	fastboot_process_erase(cmd, response);
+}
+#endif
+
+/**
+ * fastboot_set_reboot_flag() - Set flag to indicate reboot-bootloader
+ *
+ * This is a redefinition, since BSP dose not need the function of
+ * "reboot into bootloader", and with BCB support, the flag can be
+ * set with another way. Redefine this function to override the weak
+ * definition to avoid error return value.
+ */
+int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
+{
+	return 0;
+}
+
+#if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT)
+/**
+ * run_ucmd() - Execute the UCmd command
+ *
+ * @cmd_parameter: Pointer to command parameter
+ * @response: Pointer to fastboot response buffer
+ */
+static void run_ucmd(char *cmd_parameter, char *response)
+{
+	if (!cmd_parameter) {
+		pr_err("missing slot suffix\n");
+		fastboot_fail("missing command", response);
+		return;
+	}
+	if(run_command(cmd_parameter, 0)) {
+		fastboot_fail("", response);
+	} else {
+		fastboot_okay(NULL, response);
+		/* cmd may impact fastboot related environment*/
+		fastboot_setup();
+	}
+}
+
+static char g_a_cmd_buff[64];
+
+void fastboot_acmd_complete(void)
+{
+	run_command(g_a_cmd_buff, 0);
+}
+
+/**
+ * run_acmd() - Execute the ACmd command
+ *
+ * @cmd_parameter: Pointer to command parameter
+ * @response: Pointer to fastboot response buffer
+ */
+static void run_acmd(char *cmd_parameter, char *response)
+{
+	if (!cmd_parameter) {
+		pr_err("missing slot suffix\n");
+		fastboot_fail("missing command", response);
+		return;
+	}
+
+	if (strlen(cmd_parameter) >= sizeof(g_a_cmd_buff)) {
+		pr_err("input acmd is too long\n");
+		fastboot_fail("too long command", response);
+		return;
+	}
+
+	strcpy(g_a_cmd_buff, cmd_parameter);
+	fastboot_okay(NULL, response);
+}
+#endif
+
+#ifdef CONFIG_VIRTUAL_AB_SUPPORT
+static void snapshot_update(char *cmd_parameter, char *response)
+{
+	if (endswith(cmd_parameter, "cancel")) {
+		FbLockState status;
+		status = fastboot_get_lock_stat();
+		if ((status == FASTBOOT_LOCK) || (status == FASTBOOT_LOCK_ERROR)) {
+			printf("Can not cancel snapshot update when the device is locked!\n");
+			fastboot_fail("device is locked!", response);
+		} else if (virtual_ab_update_is_merging() || virtual_ab_update_is_snapshoted()) {
+			if (virtual_ab_cancel_update() != -1)
+				fastboot_okay(NULL, response);
+			else
+				fastboot_fail("Can't cancel snapshot update!", response);
+		} else {
+			printf("Device is not in 'merging' or 'snapshotted' state, do nothing...\n");
+			fastboot_okay(NULL, response);
+		}
+
+		return;
+	} else {
+		printf("Error! Only 'cancel' is supported!");
+		strcpy(response, "FAILInternal error!");
+	}
+
+	return;
+}
+#endif
+
+static const struct {
+	const char *command;
+	void (*dispatch)(char *cmd_parameter, char *response);
+} commands[FASTBOOT_COMMAND_COUNT] = {
+		[FASTBOOT_COMMAND_REBOOT_BOOTLOADER] = {
+			.command = "reboot-bootloader",
+			.dispatch = reboot_bootloader,
+		},
+		[FASTBOOT_COMMAND_UPLOAD] = {
+			.command = "upload",
+			.dispatch = upload,
+		},
+		[FASTBOOT_COMMAND_GETSTAGED] = {
+			.command = "get_staged",
+			.dispatch = upload,
+		},
+#if defined(CONFIG_FASTBOOT_LOCK)
+		[FASTBOOT_COMMAND_FLASHING] = {
+			.command = "flashing",
+			.dispatch = flashing,
+		},
+		[FASTBOOT_COMMAND_OEM] = {
+			.command = "oem",
+			.dispatch = flashing,
+		},
+#endif
+#ifdef CONFIG_AVB_SUPPORT
+		[FASTBOOT_COMMAND_SETACTIVE] = {
+			.command = "set_active",
+			.dispatch = set_active_avb,
+		},
+#endif
+#if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT)
+		[FASTBOOT_COMMAND_UCMD] = {
+			.command = "UCmd",
+			.dispatch = run_ucmd,
+		},
+		[FASTBOOT_COMMAND_ACMD] = {
+			.command ="ACmd",
+			.dispatch = run_acmd,
+		},
+#endif
+		[FASTBOOT_COMMAND_REBOOT] = {
+			.command = "reboot",
+			.dispatch = okay,
+		},
+		[FASTBOOT_COMMAND_GETVAR] = {
+			.command = "getvar",
+			.dispatch = getvar,
+		},
+		[FASTBOOT_COMMAND_DOWNLOAD] = {
+			.command = "download",
+			.dispatch = download,
+		},
+		[FASTBOOT_COMMAND_BOOT] = {
+			.command = "boot",
+			.dispatch = okay,
+		},
+		[FASTBOOT_COMMAND_CONTINUE] = {
+			.command = "continue",
+			.dispatch = okay,
+		},
+#ifdef CONFIG_FASTBOOT_FLASH
+		[FASTBOOT_COMMAND_FLASH] = {
+			.command = "flash",
+			.dispatch = flash,
+		},
+		[FASTBOOT_COMMAND_ERASE] = {
+			.command = "erase",
+			.dispatch = erase,
+		},
+#endif
+#ifdef CONFIG_AVB_ATX
+		[FASTBOOT_COMMAND_STAGE] = {
+			.command = "stage",
+			.dispatch = download,
+		},
+#endif
+#ifdef CONFIG_ANDROID_RECOVERY
+		[FASTBOOT_COMMAND_RECOVERY_FASTBOOT] = {
+			.command = "reboot-fastboot",
+			.dispatch = reboot_fastboot,
+		},
+#endif
+#ifdef CONFIG_VIRTUAL_AB_SUPPORT
+		[FASTBOOT_COMMAND_SNAPSHOT_UPDATE] = {
+			.command = "snapshot-update",
+			.dispatch = snapshot_update,
+		},
+#endif
+};
+
+/**
+ * fastboot_handle_command - Handle fastboot command
+ *
+ * @cmd_string: Pointer to command string
+ * @response: Pointer to fastboot response buffer
+ *
+ * Return: Executed command, or -1 if not recognized
+ */
+int fastboot_handle_command(char *cmd_string, char *response)
+{
+	int i;
+	char *cmd_parameter;
+
+	cmd_parameter = cmd_string;
+	strsep(&cmd_parameter, ":");
+	/* separate cmdstring for "fastboot oem/flashing" with a blank */
+	if(cmd_parameter == NULL)
+	{
+		cmd_parameter = cmd_string;
+		strsep(&cmd_parameter, " ");
+	}
+
+	for (i = 0; i < ARRAY_SIZE(commands); i++) {
+		if (commands[i].command != NULL &&
+			!strcmp(commands[i].command, cmd_string)) {
+			if (commands[i].dispatch) {
+				commands[i].dispatch(cmd_parameter,
+							response);
+				return i;
+			} else {
+				break;
+			}
+		}
+	}
+
+	pr_err("command %s not recognized.\n", cmd_string);
+	fastboot_fail("unrecognized command", response);
+	return -1;
+}
diff --git a/drivers/fastboot/fb_fsl/fb_fsl_common.c b/drivers/fastboot/fb_fsl/fb_fsl_common.c
new file mode 100644
index 00000000000..b17c25a55a5
--- /dev/null
+++ b/drivers/fastboot/fb_fsl/fb_fsl_common.c
@@ -0,0 +1,431 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <asm/mach-imx/sys_proto.h>
+#include <fb_fsl.h>
+#include <fastboot.h>
+#include <mmc.h>
+#include <android_image.h>
+#include <asm/bootm.h>
+#include <nand.h>
+#include <part.h>
+#include <sparse_format.h>
+#include <image-sparse.h>
+#include <image.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/setup.h>
+#include <env.h>
+#ifdef CONFIG_ANDROID_RECOVERY
+#include <recovery.h>
+#endif
+
+#ifdef CONFIG_BCB_SUPPORT
+#include "bcb.h"
+#endif
+
+#ifdef CONFIG_AVB_SUPPORT
+#include <dt_table.h>
+#include <fsl_avb.h>
+#endif
+
+#ifdef CONFIG_ANDROID_THINGS_SUPPORT
+#include <asm-generic/gpio.h>
+#include <asm/mach-imx/gpio.h>
+#include "../lib/avb/fsl/fsl_avbkey.h"
+#include "../arch/arm/include/asm/mach-imx/hab.h"
+#endif
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#include "u-boot/sha256.h"
+#include <trusty/libtipc.h>
+
+extern int armv7_init_nonsec(void);
+extern void trusty_os_init(void);
+#endif
+
+#include "fb_fsl_common.h"
+
+#include <serial.h>
+#include <stdio_dev.h>
+
+#if defined(CONFIG_AVB_SUPPORT) && defined(CONFIG_MMC)
+AvbABOps fsl_avb_ab_ops = {
+	.read_ab_metadata = fsl_avb_ab_data_read,
+	.write_ab_metadata = fsl_avb_ab_data_write,
+	.ops = NULL
+};
+#ifdef CONFIG_AVB_ATX
+AvbAtxOps fsl_avb_atx_ops = {
+	.ops = NULL,
+	.read_permanent_attributes = fsl_read_permanent_attributes,
+	.read_permanent_attributes_hash = fsl_read_permanent_attributes_hash,
+#ifdef CONFIG_IMX_TRUSTY_OS
+	.set_key_version = fsl_write_rollback_index_rpmb,
+#else
+	.set_key_version = fsl_set_key_version,
+#endif
+	.get_random = fsl_get_random
+};
+#endif
+AvbOps fsl_avb_ops = {
+	.ab_ops = &fsl_avb_ab_ops,
+#ifdef CONFIG_AVB_ATX
+	.atx_ops = &fsl_avb_atx_ops,
+#endif
+	.read_from_partition = fsl_read_from_partition_multi,
+	.write_to_partition = fsl_write_to_partition,
+#ifdef CONFIG_AVB_ATX
+	.validate_vbmeta_public_key = avb_atx_validate_vbmeta_public_key,
+#else
+	.validate_vbmeta_public_key = fsl_validate_vbmeta_public_key_rpmb,
+#endif
+	.read_rollback_index = fsl_read_rollback_index_rpmb,
+        .write_rollback_index = fsl_write_rollback_index_rpmb,
+	.read_is_device_unlocked = fsl_read_is_device_unlocked,
+	.get_unique_guid_for_partition = fsl_get_unique_guid_for_partition,
+	.get_size_of_partition = fsl_get_size_of_partition
+};
+#endif
+
+int get_block_size(void) {
+        int dev_no = 0;
+        struct blk_desc *dev_desc;
+
+        dev_no = fastboot_devinfo.dev_id;
+        dev_desc = blk_get_dev(fastboot_devinfo.type == DEV_SATA ? "scsi" : "mmc", dev_no);
+        if (NULL == dev_desc) {
+                printf("** Block device %s %d not supported\n",
+                       fastboot_devinfo.type == DEV_SATA ? "scsi" : "mmc",
+                       dev_no);
+                return 0;
+        }
+        return dev_desc->blksz;
+}
+
+struct fastboot_device_info fastboot_devinfo = {0xff, 0xff};
+
+#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT
+struct fastboot_device_info fastboot_firmwareinfo;
+#endif
+
+/**
+ * fastboot_none() - Skip the common write operation, nothing output.
+ *
+ * @response: Pointer to fastboot response buffer
+ */
+void fastboot_none_resp(char *response)
+{
+	*response = 0;
+}
+
+void board_fastboot_setup(void)
+{
+	static char boot_dev_part[32];
+	u32 dev_no;
+
+	switch (get_boot_device()) {
+	case SD1_BOOT:
+	case SD2_BOOT:
+	case SD3_BOOT:
+	case SD4_BOOT:
+	case MMC1_BOOT:
+	case MMC2_BOOT:
+	case MMC3_BOOT:
+	case MMC4_BOOT:
+		dev_no = mmc_get_env_dev();
+		sprintf(boot_dev_part,"mmc%d",dev_no);
+		if (!env_get("fastboot_dev"))
+			env_set("fastboot_dev", boot_dev_part);
+		sprintf(boot_dev_part, "boota mmc%d", dev_no);
+		if (!env_get("bootcmd"))
+			env_set("bootcmd", boot_dev_part);
+		break;
+	case USB_BOOT:
+		printf("Detect USB boot. Will enter fastboot mode!\n");
+		if (!env_get("bootcmd"))
+			env_set("bootcmd", "fastboot 0");
+		break;
+	default:
+		if (!env_get("bootcmd"))
+			printf("unsupported boot devices\n");
+		break;
+	}
+
+	/* add soc type into bootargs */
+	if (is_mx6dqp()) {
+		if (!env_get("soc_type"))
+			env_set("soc_type", "imx6qp");
+	} else if (is_mx6dq()) {
+		if (!env_get("soc_type"))
+			env_set("soc_type", "imx6q");
+	} else if (is_mx6sdl()) {
+		if (!env_get("soc_type"))
+			env_set("soc_type", "imx6dl");
+	} else if (is_mx6sx()) {
+		if (!env_get("soc_type"))
+			env_set("soc_type", "imx6sx");
+	} else if (is_mx6sl()) {
+		if (!env_get("soc_type"))
+			env_set("soc_type", "imx6sl");
+	} else if (is_mx6ul()) {
+		if (!env_get("soc_type"))
+			env_set("soc_type", "imx6ul");
+	} else if (is_mx7()) {
+		if (!env_get("soc_type"))
+			env_set("soc_type", "imx7d");
+	} else if (is_mx7ulp()) {
+		if (!env_get("soc_type"))
+			env_set("soc_type", "imx7ulp");
+	} else if (is_imx8qm()) {
+		if (!env_get("soc_type"))
+			env_set("soc_type", "imx8qm");
+		if (is_soc_rev(CHIP_REV_A))
+			env_set("soc_rev", "reva");
+		else if (is_soc_rev(CHIP_REV_B))
+			env_set("soc_rev", "revb");
+	} else if (is_imx8qxp()) {
+		if (!env_get("soc_type"))
+			env_set("soc_type", "imx8qxp");
+		if (is_soc_rev(CHIP_REV_A))
+			env_set("soc_rev", "reva");
+		else if (is_soc_rev(CHIP_REV_B))
+			env_set("soc_rev", "revb");
+		else if (is_soc_rev(CHIP_REV_C))
+			env_set("soc_rev", "revc");
+	} else if (is_imx8mq()) {
+		if (!env_get("soc_type"))
+			env_set("soc_type", "imx8mq");
+	} else if (is_imx8mm()) {
+		if (!env_get("soc_type"))
+			env_set("soc_type", "imx8mm");
+	} else if (is_imx8mn()) {
+		if (!env_get("soc_type"))
+			env_set("soc_type", "imx8mn");
+	} else if (is_imx8mp()) {
+		if (!env_get("soc_type"))
+			env_set("soc_type", "imx8mp");
+	} else if (is_imx8ulp()) {
+		if (!env_get("soc_type"))
+			env_set("soc_type", "imx8ulp");
+	} else if (is_imx93()) {
+		if (!env_get("soc_type"))
+			env_set("soc_type", "imx93");
+	}
+}
+
+#ifdef CONFIG_ANDROID_RECOVERY
+void board_recovery_setup(void)
+{
+/* boot from current mmc with avb verify */
+#ifdef CONFIG_AVB_SUPPORT
+	if (!env_get("bootcmd_android_recovery"))
+		env_set("bootcmd_android_recovery", "boota recovery");
+#else
+	static char boot_dev_part[32];
+	u32 dev_no;
+
+	int bootdev = get_boot_device();
+	switch (bootdev) {
+	case SD1_BOOT:
+	case SD2_BOOT:
+	case SD3_BOOT:
+	case SD4_BOOT:
+	case MMC1_BOOT:
+	case MMC2_BOOT:
+	case MMC3_BOOT:
+	case MMC4_BOOT:
+		dev_no = mmc_get_env_dev();
+		sprintf(boot_dev_part,"boota mmc%d recovery",dev_no);
+		if (!env_get("bootcmd_android_recovery"))
+			env_set("bootcmd_android_recovery", boot_dev_part);
+		break;
+	default:
+		printf("Unsupported bootup device for recovery: dev: %d\n",
+			bootdev);
+		return;
+	}
+#endif /* CONFIG_AVB_SUPPORT */
+	printf("setup env for recovery..\n");
+	env_set("bootcmd", env_get("bootcmd_android_recovery"));
+}
+#endif /*CONFIG_ANDROID_RECOVERY*/
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#ifdef CONFIG_ARM64
+void tee_setup(void)
+{
+	trusty_ipc_init();
+}
+
+#else
+extern bool tos_flashed;
+
+void tee_setup(void)
+{
+	/* load tee from boot1 of eMMC. */
+	int mmcc = mmc_get_env_dev();
+	struct blk_desc *dev_desc = NULL;
+
+	struct mmc *mmc;
+	mmc = find_mmc_device(mmcc);
+	if (!mmc) {
+	            printf("boota: cannot find '%d' mmc device\n", mmcc);
+		            goto fail;
+	}
+
+	dev_desc = blk_get_dev("mmc", mmcc);
+	if (NULL == dev_desc) {
+	            printf("** Block device MMC %d not supported\n", mmcc);
+		            goto fail;
+	}
+
+	/* below was i.MX mmc operation code */
+	if (mmc_init(mmc)) {
+	            printf("mmc%d init failed\n", mmcc);
+		            goto fail;
+	}
+
+	struct fastboot_ptentry *tee_pte;
+	char *tee_ptn = FASTBOOT_PARTITION_TEE;
+	tee_pte = fastboot_flash_find_ptn(tee_ptn);
+	mmc_switch_part(mmc, TEE_HWPARTITION_ID);
+	if (!tee_pte) {
+		printf("boota: cannot find tee partition!\n");
+		fastboot_flash_dump_ptn();
+	}
+
+	if (blk_dread(dev_desc, tee_pte->start,
+		    tee_pte->length, (void *)TRUSTY_OS_ENTRY) < 0) {
+		printf("Failed to load tee.");
+	}
+	mmc_switch_part(mmc, FASTBOOT_MMC_USER_PARTITION_ID);
+
+	tos_flashed = false;
+	if(!valid_tos()) {
+		printf("TOS not flashed! Will enter TOS recovery mode. Everything will be wiped!\n");
+		fastboot_wipe_all();
+		run_command("fastboot 0", 0);
+		goto fail;
+	}
+#ifdef NON_SECURE_FASTBOOT
+	armv7_init_nonsec();
+	trusty_os_init();
+	trusty_ipc_init();
+#endif
+
+fail:
+	return;
+
+}
+#endif /* CONFIG_ARM64 */
+#endif /* CONFIG_IMX_TRUSTY_OS */
+
+static int _fastboot_setup_dev(int *switched)
+{
+	char *fastboot_env;
+	struct fastboot_device_info devinfo;;
+	fastboot_env = env_get("fastboot_dev");
+
+	if (fastboot_env) {
+		if (!strcmp(fastboot_env, "sata")) {
+			devinfo.type = DEV_SATA;
+			devinfo.dev_id = 0;
+		} else if (!strncmp(fastboot_env, "mmc", 3)) {
+			devinfo.type = DEV_MMC;
+			if(env_get("target_ubootdev"))
+				devinfo.dev_id = simple_strtoul(env_get("target_ubootdev"), NULL, 10);
+			else
+				devinfo.dev_id = mmc_get_env_dev();
+		} else {
+			return 1;
+		}
+	} else {
+		return 1;
+	}
+#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT
+	/* For imx7ulp, flash m4 images directly to spi nor-flash, M4 will
+	 * run automatically after powered on. For imx8mq, flash m4 images to
+	 * physical partition 'mcu_os', m4 will be kicked off by A core. */
+	fastboot_firmwareinfo.type = ANDROID_MCU_FRIMWARE_DEV_TYPE;
+#endif
+
+	if (switched) {
+		if (devinfo.type != fastboot_devinfo.type || devinfo.dev_id != fastboot_devinfo.dev_id)
+			*switched = 1;
+		else
+			*switched = 0;
+	}
+
+	fastboot_devinfo.type	 = devinfo.type;
+	fastboot_devinfo.dev_id = devinfo.dev_id;
+
+	return 0;
+}
+
+void fastboot_setup(void)
+{
+	int sw, ret;
+	struct tag_serialnr serialnr;
+	char serial[17];
+
+	if (!env_get("serial#")) {
+		get_board_serial(&serialnr);
+		sprintf(serial, "%08x%08x", serialnr.high, serialnr.low);
+		env_set("serial#", serial);
+	}
+
+	/*execute board relevant initilizations for preparing fastboot */
+	board_fastboot_setup();
+
+	/*get the fastboot dev*/
+	ret = _fastboot_setup_dev(&sw);
+
+	/*load partitions information for the fastboot dev*/
+	if (!ret && sw)
+		fastboot_load_partitions();
+
+	fastboot_init(NULL, 0);
+#ifdef CONFIG_AVB_SUPPORT
+	fsl_avb_ab_ops.ops = &fsl_avb_ops;
+#ifdef CONFIG_AVB_ATX
+	fsl_avb_atx_ops.ops = &fsl_avb_ops;
+#endif
+#endif
+}
+
+static void fastboot_putc(struct stdio_dev *dev, const char c)
+{
+	char buff[6] = "INFO";
+	buff[4] = c;
+	buff[5] = 0;
+	fastboot_tx_write_more(buff);
+}
+
+#define FASTBOOT_MAX_LEN 64
+
+static void fastboot_puts(struct stdio_dev *dev, const char *s)
+{
+	char buff[FASTBOOT_MAX_LEN + 1] = "INFO";
+	int len = strlen(s);
+	int i, left;
+
+	for (i = 0; i < len; i += FASTBOOT_MAX_LEN - 4) {
+		left = len - i;
+		if (left > FASTBOOT_MAX_LEN - 4)
+			left = FASTBOOT_MAX_LEN - 4;
+
+		memcpy(buff + 4, s + i, left);
+		buff[left + 4] = 0;
+		fastboot_tx_write_more(buff);
+	}
+}
+
+struct stdio_dev g_fastboot_stdio = {
+	.name = "fastboot",
+	.flags = DEV_FLAGS_OUTPUT,
+	.putc = fastboot_putc,
+	.puts = fastboot_puts,
+};
diff --git a/drivers/fastboot/fb_fsl/fb_fsl_common.h b/drivers/fastboot/fb_fsl/fb_fsl_common.h
new file mode 100644
index 00000000000..6b957c43d5d
--- /dev/null
+++ b/drivers/fastboot/fb_fsl/fb_fsl_common.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef FB_FSL_COMMON_H
+#define FB_FSL_COMMON_H
+
+#ifdef CONFIG_AVB_SUPPORT
+#include <dt_table.h>
+#include <fsl_avb.h>
+#endif
+
+#if defined(CONFIG_AVB_SUPPORT) && defined(CONFIG_MMC)
+extern AvbABOps fsl_avb_ab_ops;
+#ifdef CONFIG_AVB_ATX
+extern AvbAtxOps fsl_avb_atx_ops;
+#endif
+extern AvbOps fsl_avb_ops;
+#endif
+
+#define IMX_SERIAL_LEN 32
+
+int get_block_size(void);
+void process_erase_mmc(const char *cmdbuf, char *response);
+char *get_serial(void);
+
+#endif	// FB_FSL_COMMON_H
diff --git a/drivers/fastboot/fb_fsl/fb_fsl_dev.c b/drivers/fastboot/fb_fsl/fb_fsl_dev.c
new file mode 100644
index 00000000000..0ac2de5d72a
--- /dev/null
+++ b/drivers/fastboot/fb_fsl/fb_fsl_dev.c
@@ -0,0 +1,562 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <asm/mach-imx/sys_proto.h>
+#include <fb_fsl.h>
+#include <fastboot.h>
+#include <mmc.h>
+#include <android_image.h>
+#include <asm/bootm.h>
+#include <nand.h>
+#include <part.h>
+#include <sparse_format.h>
+#include <image-sparse.h>
+#include <image.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/setup.h>
+#include <env.h>
+
+#include "fb_fsl_common.h"
+
+static lbaint_t mmc_sparse_write(struct sparse_storage *info,
+		lbaint_t blk, lbaint_t blkcnt, const void *buffer)
+{
+#define SPARSE_FILL_BUF_SIZE (2 * 1024 * 1024)
+
+
+	struct blk_desc *dev_desc = (struct blk_desc *)info->priv;
+	ulong ret = 0;
+	void *data;
+	int fill_buf_num_blks, cnt;
+
+	if ((unsigned long)buffer & (CONFIG_SYS_CACHELINE_SIZE - 1)) {
+
+		fill_buf_num_blks = SPARSE_FILL_BUF_SIZE / info->blksz;
+
+		data = memalign(CONFIG_SYS_CACHELINE_SIZE, fill_buf_num_blks * info->blksz);
+
+		while (blkcnt) {
+
+			if (blkcnt > fill_buf_num_blks)
+				cnt = fill_buf_num_blks;
+			else
+				cnt = blkcnt;
+
+			memcpy(data, buffer, cnt * info->blksz);
+
+			ret += blk_dwrite(dev_desc, blk, cnt, data);
+
+			blk += cnt;
+			blkcnt -= cnt;
+			buffer = (void *)((unsigned long)buffer + cnt * info->blksz);
+
+		}
+
+		free(data);
+	} else {
+		ret = blk_dwrite(dev_desc, blk, blkcnt, buffer);
+	}
+
+	return ret;
+}
+
+static lbaint_t mmc_sparse_reserve(struct sparse_storage *info,
+		lbaint_t blk, lbaint_t blkcnt)
+{
+	return blkcnt;
+}
+
+int write_backup_gpt(void *download_buffer)
+{
+	int mmc_no = 0;
+	struct mmc *mmc;
+	struct blk_desc *dev_desc;
+
+	mmc_no = fastboot_devinfo.dev_id;
+	mmc = find_mmc_device(mmc_no);
+	if (mmc == NULL) {
+		printf("invalid mmc device\n");
+		return -1;
+	}
+	dev_desc = blk_get_dev("mmc", mmc_no);
+	if (dev_desc == NULL) {
+		printf("Can't get Block device MMC %d\n",
+			mmc_no);
+		return -ENODEV;
+	}
+
+	/* write backup get partition */
+	if (write_backup_gpt_partitions(dev_desc, download_buffer)) {
+		printf("writing GPT image fail\n");
+		return -1;
+	}
+
+	printf("flash backup gpt image successfully\n");
+	return 0;
+}
+
+static int get_fastboot_target_dev(char *mmc_dev, struct fastboot_ptentry *ptn)
+{
+	int dev = 0;
+	struct mmc *target_mmc;
+
+	/* Support flash bootloader to mmc 'target_ubootdev' devices, if the
+	* 'target_ubootdev' env is not set just flash bootloader to current
+	* mmc device.
+	*/
+	if ((!strncmp(ptn->name, FASTBOOT_PARTITION_BOOTLOADER,
+					sizeof(FASTBOOT_PARTITION_BOOTLOADER))) &&
+					(env_get("target_ubootdev"))) {
+		dev = simple_strtoul(env_get("target_ubootdev"), NULL, 10);
+
+		/* if target_ubootdev is set, it must be that users want to change
+		 * fastboot device, then fastboot environment need to be updated */
+		fastboot_setup();
+
+		target_mmc = find_mmc_device(dev);
+		if ((target_mmc == NULL) || mmc_init(target_mmc)) {
+			printf("MMC card init failed!\n");
+			return -1;
+		} else {
+			printf("Flash target is mmc%d\n", dev);
+			if (target_mmc->part_config != MMCPART_NOAVAILABLE)
+				sprintf(mmc_dev, "mmc dev %x %x", dev, /*slot no*/
+						FASTBOOT_MMC_BOOT_PARTITION_ID/*part no*/);
+			else
+				sprintf(mmc_dev, "mmc dev %x", dev);
+			}
+	} else if (ptn->partition_id != FASTBOOT_MMC_NONE_PARTITION_ID)
+		sprintf(mmc_dev, "mmc dev %x %x",
+				fastboot_devinfo.dev_id, /*slot no*/
+				ptn->partition_id /*part no*/);
+	else
+		sprintf(mmc_dev, "mmc dev %x",
+				fastboot_devinfo.dev_id /*slot no*/);
+	return 0;
+}
+
+static void process_flash_blkdev(const char *cmdbuf, void *download_buffer,
+			      u32 download_bytes, char *response)
+{
+	if (download_bytes) {
+		struct fastboot_ptentry *ptn;
+
+		/* Next is the partition name */
+		ptn = fastboot_flash_find_ptn(cmdbuf);
+		if (ptn == NULL) {
+			fastboot_fail("partition does not exist", response);
+			fastboot_flash_dump_ptn();
+		} else if ((download_bytes >
+			   ptn->length * MMC_SATA_BLOCK_SIZE) &&
+				!(ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_ENV)) {
+			printf("Image too large for the partition\n");
+			fastboot_fail("image too large for partition", response);
+		} else {
+			unsigned int temp;
+
+			char blk_dev[128];
+			char blk_write[128];
+			int blkret;
+
+			printf("writing to partition '%s'\n", ptn->name);
+			/* Get target flash device. */
+			if (get_fastboot_target_dev(blk_dev, ptn) != 0)
+				return;
+
+			if (!fastboot_parts_is_raw(ptn) &&
+				is_sparse_image(download_buffer)) {
+				int dev_no = 0;
+				struct mmc *mmc;
+				struct blk_desc *dev_desc;
+				struct disk_partition info;
+				struct sparse_storage sparse;
+				int err;
+
+				dev_no = fastboot_devinfo.dev_id;
+
+				printf("sparse flash target is %s:%d\n",
+				       fastboot_devinfo.type == DEV_SATA ? "scsi" : "mmc",
+				       dev_no);
+				if (fastboot_devinfo.type == DEV_MMC) {
+					mmc = find_mmc_device(dev_no);
+					if (mmc && mmc_init(mmc))
+						printf("MMC card init failed!\n");
+				}
+
+				dev_desc = blk_get_dev(fastboot_devinfo.type == DEV_SATA ? "scsi" : "mmc", dev_no);
+				if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+					printf("** Block device %s %d not supported\n",
+					       fastboot_devinfo.type == DEV_SATA ? "scsi" : "mmc",
+					       dev_no);
+					return;
+				}
+
+				if( strncmp(ptn->name, FASTBOOT_PARTITION_ALL,
+					    strlen(FASTBOOT_PARTITION_ALL)) == 0) {
+					info.blksz = dev_desc->blksz;
+					info.size = dev_desc->lba;
+					info.start = 0;
+				} else {
+
+					if (part_get_info(dev_desc,
+							  ptn->partition_index, &info)) {
+						printf("Bad partition index:%d for partition:%s\n",
+						ptn->partition_index, ptn->name);
+						return;
+					}
+				}
+				printf("writing to partition '%s' for sparse, buffer size %d\n",
+						ptn->name, download_bytes);
+
+				sparse.blksz = info.blksz;
+				sparse.start = info.start;
+				sparse.size = info.size;
+				sparse.write = mmc_sparse_write;
+				sparse.reserve = mmc_sparse_reserve;
+				sparse.mssg = fastboot_fail;
+				printf("Flashing sparse image at offset " LBAFU "\n",
+				       sparse.start);
+
+				sparse.priv = dev_desc;
+				err = write_sparse_image(&sparse, ptn->name, download_buffer,
+						   response);
+
+				if (!err)
+					fastboot_okay(NULL, response);
+			} else {
+				/* Will flash images in below case:
+				 * 1. Is not gpt partition.
+				 * 2. Is gpt partition but no overlay detected.
+				 * */
+				if (strncmp(ptn->name, "gpt", 3) || !bootloader_gpt_overlay()) {
+					/* block count */
+					if (strncmp(ptn->name, "gpt", 3) == 0) {
+						temp = (ANDROID_GPT_END +
+								MMC_SATA_BLOCK_SIZE - 1) /
+								MMC_SATA_BLOCK_SIZE;
+					} else {
+						temp = (download_bytes +
+								MMC_SATA_BLOCK_SIZE - 1) /
+								MMC_SATA_BLOCK_SIZE;
+					}
+
+					sprintf(blk_write, "%s write 0x%x 0x%x 0x%x",
+						fastboot_devinfo.type == DEV_SATA ? "scsi" : "mmc",
+						(unsigned int)(uintptr_t)download_buffer, /*source*/
+						ptn->start, /*dest*/
+						temp /*length*/);
+
+					printf("Initializing '%s'\n", ptn->name);
+
+					blkret = run_command(blk_dev, 0);
+					if (blkret)
+						fastboot_fail("Init of BLK device failed", response);
+					else
+						fastboot_okay(NULL, response);
+
+					printf("Writing '%s'\n", ptn->name);
+					if (run_command(blk_write, 0)) {
+						printf("Writing '%s' FAILED!\n", ptn->name);
+						fastboot_fail("Write partition failed", response);
+					} else {
+						printf("Writing '%s' DONE!\n", ptn->name);
+						fastboot_okay(NULL, response);
+					}
+				}
+				/* Write backup gpt image */
+				if (strncmp(ptn->name, "gpt", 3) == 0) {
+					if (write_backup_gpt(download_buffer))
+						fastboot_fail("write backup GPT image fail", response);
+					else
+						fastboot_okay(NULL, response);
+
+					/* will force scan the device,
+					 * so dev_desc can be re-inited
+					 * with the latest data */
+					run_command(blk_dev, 0);
+				}
+			}
+		}
+	} else {
+		fastboot_fail("no image downloaded", response);
+	}
+}
+
+static void process_erase_blkdev(const char *cmdbuf, char *response)
+{
+	int mmc_no = 0;
+	char blk_dev[128];
+	lbaint_t blks, blks_start, blks_size, grp_size;
+	struct mmc *mmc;
+	struct blk_desc *dev_desc;
+	struct fastboot_ptentry *ptn;
+	struct disk_partition info;
+
+	ptn = fastboot_flash_find_ptn(cmdbuf);
+	if ((ptn == NULL) || (ptn->flags & FASTBOOT_PTENTRY_FLAGS_UNERASEABLE)) {
+		fastboot_fail("partition does not exist or uneraseable", response);
+		fastboot_flash_dump_ptn();
+		return;
+	}
+
+	if (fastboot_devinfo.type == DEV_SATA) {
+		printf("Not support erase on SATA\n");
+		return;
+	}
+
+	mmc_no = fastboot_devinfo.dev_id;
+	printf("erase target is MMC:%d\n", mmc_no);
+
+	mmc = find_mmc_device(mmc_no);
+	if ((mmc == NULL) || mmc_init(mmc)) {
+		printf("MMC card init failed!\n");
+		return;
+	}
+
+	dev_desc = blk_get_dev("mmc", mmc_no);
+	if (NULL == dev_desc) {
+		printf("Block device MMC %d not supported\n",
+			mmc_no);
+		fastboot_fail("not valid MMC card", response);
+		return;
+	}
+
+	/* Get and switch target flash device. */
+	if (get_fastboot_target_dev(blk_dev, ptn) != 0) {
+		printf("failed to get target dev!\n");
+		return;
+	} else if (run_command(blk_dev, 0)) {
+		printf("Init of BLK device failed\n");
+		return;
+	}
+
+	if (part_get_info(dev_desc,
+				ptn->partition_index, &info)) {
+		printf("Bad partition index:%d for partition:%s\n",
+		ptn->partition_index, ptn->name);
+		fastboot_fail("erasing of MMC card", response);
+		return;
+	}
+
+	/* Align blocks to erase group size to avoid erasing other partitions */
+	grp_size = mmc->erase_grp_size;
+	blks_start = (info.start + grp_size - 1) & ~(grp_size - 1);
+	if (info.size >= grp_size)
+		blks_size = (info.size - (blks_start - info.start)) &
+				(~(grp_size - 1));
+	else
+		blks_size = 0;
+
+	printf("Erasing blocks " LBAFU " to " LBAFU " due to alignment\n",
+	       blks_start, blks_start + blks_size);
+
+	blks = blk_derase(dev_desc, blks_start, blks_size);
+	if (blks != blks_size) {
+		printf("failed erasing from device %d", dev_desc->devnum);
+		fastboot_fail("erasing of MMC card", response);
+		return;
+	}
+
+	printf("........ erased " LBAFU " bytes from '%s'\n",
+	       blks_size * info.blksz, cmdbuf);
+	fastboot_okay(NULL, response);
+
+    return;
+}
+
+#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT
+static void process_flash_sf(const char *cmdbuf, void *download_buffer,
+			      u32 download_bytes, char *response)
+{
+	int blksz = 0;
+	blksz = get_block_size();
+
+	if (download_bytes) {
+		struct fastboot_ptentry *ptn;
+		ptn = fastboot_flash_find_ptn(cmdbuf);
+		if (ptn == 0) {
+			fastboot_fail("partition does not exist", response);
+			fastboot_flash_dump_ptn();
+		} else if ((download_bytes > ptn->length * blksz)) {
+			fastboot_fail("image too large for partition", response);
+		/* TODO : Improve check for yaffs write */
+		} else {
+			int ret;
+			char sf_command[128];
+			/* Normal case */
+			/* Probe device */
+			sprintf(sf_command, "sf probe");
+			ret = run_command(sf_command, 0);
+			if (ret){
+				fastboot_fail("Probe sf failed", response);
+				return;
+			}
+			/* Erase */
+			sprintf(sf_command, "sf erase 0x%x 0x%lx", ptn->start * blksz, /*start*/
+			ptn->length * blksz /*size*/);
+			ret = run_command(sf_command, 0);
+			if (ret) {
+				fastboot_fail("Erasing sf failed", response);
+				return;
+			}
+			/* Write image */
+			sprintf(sf_command, "sf write 0x%x 0x%x 0x%x",
+					(unsigned int)(ulong)download_buffer, /* source */
+					ptn->start * blksz, /* start */
+					download_bytes /*size*/);
+			printf("sf write '%s'\n", ptn->name);
+			ret = run_command(sf_command, 0);
+			if (ret){
+				fastboot_fail("Writing sf failed", response);
+				return;
+			}
+			printf("sf write finished '%s'\n", ptn->name);
+			fastboot_okay(NULL, response);
+		}
+	} else {
+		fastboot_fail("no image downloaded", response);
+	}
+}
+
+#ifdef CONFIG_ARCH_IMX8M
+/* Check if the mcu image is built for running from TCM */
+static bool is_tcm_image(unsigned char *image_addr)
+{
+	u32 stack;
+
+	stack = *(u32 *)image_addr;
+
+	if ((stack != (u32)ANDROID_MCU_FIRMWARE_HEADER_STACK)) {
+		printf("Please flash mcu firmware images for running from TCM\n");
+		return false;
+	} else
+		return true;
+}
+#endif
+#endif
+
+void fastboot_process_erase(const char *cmdbuf, char *response)
+{
+	switch (fastboot_devinfo.type) {
+	case DEV_SATA:
+	case DEV_MMC:
+		process_erase_blkdev(cmdbuf, response);
+		break;
+	default:
+		printf("Not support flash command for current device %d\n",
+			fastboot_devinfo.type);
+		fastboot_fail("failed to flash device", response);
+		break;
+	}
+}
+
+void fastboot_process_flash(const char *cmdbuf, void *download_buffer,
+			      u32 download_bytes, char *response)
+{
+/* Check if we need to flash mcu firmware */
+#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT
+	if (!strncmp(cmdbuf, FASTBOOT_MCU_FIRMWARE_PARTITION,
+				sizeof(FASTBOOT_MCU_FIRMWARE_PARTITION))) {
+		switch (fastboot_firmwareinfo.type) {
+		case DEV_SF:
+			process_flash_sf(cmdbuf, download_buffer,
+				download_bytes, response);
+			break;
+#ifdef CONFIG_ARCH_IMX8M
+		case DEV_MMC:
+			if (is_tcm_image(download_buffer))
+				process_flash_blkdev(cmdbuf, download_buffer,
+					download_bytes, response);
+			break;
+#endif
+		default:
+			printf("Don't support flash firmware\n");
+		}
+		return;
+	}
+#endif
+	/* Normal case */
+	switch (fastboot_devinfo.type) {
+	case DEV_SATA:
+	case DEV_MMC:
+		process_flash_blkdev(cmdbuf, download_buffer,
+			download_bytes, response);
+		break;
+	default:
+		printf("Not support flash command for current device %d\n",
+			fastboot_devinfo.type);
+		fastboot_fail("failed to flash device", response);
+		break;
+	}
+}
+
+/* erase a partition on mmc */
+void process_erase_mmc(const char *cmdbuf, char *response)
+{
+	int mmc_no = 0;
+	lbaint_t blks, blks_start, blks_size, grp_size;
+	struct mmc *mmc;
+	struct blk_desc *dev_desc;
+	struct fastboot_ptentry *ptn;
+	struct disk_partition info;
+
+	ptn = fastboot_flash_find_ptn(cmdbuf);
+	if ((ptn == NULL) || (ptn->flags & FASTBOOT_PTENTRY_FLAGS_UNERASEABLE)) {
+		sprintf(response, "FAILpartition does not exist or uneraseable");
+		fastboot_flash_dump_ptn();
+		return;
+	}
+
+	mmc_no = fastboot_devinfo.dev_id;
+	printf("erase target is MMC:%d\n", mmc_no);
+
+	mmc = find_mmc_device(mmc_no);
+	if ((mmc == NULL) || mmc_init(mmc)) {
+		printf("MMC card init failed!\n");
+		return;
+	}
+
+	dev_desc = blk_get_dev("mmc", mmc_no);
+	if (NULL == dev_desc) {
+		printf("Block device MMC %d not supported\n",
+			mmc_no);
+		sprintf(response, "FAILnot valid MMC card");
+		return;
+	}
+
+	if (part_get_info(dev_desc,
+				ptn->partition_index, &info)) {
+		printf("Bad partition index:%d for partition:%s\n",
+		ptn->partition_index, ptn->name);
+		sprintf(response, "FAILerasing of MMC card");
+		return;
+	}
+
+	/* Align blocks to erase group size to avoid erasing other partitions */
+	grp_size = mmc->erase_grp_size;
+	blks_start = (info.start + grp_size - 1) & ~(grp_size - 1);
+	if (info.size >= grp_size)
+		blks_size = (info.size - (blks_start - info.start)) &
+				(~(grp_size - 1));
+	else
+		blks_size = 0;
+
+	printf("Erasing blocks " LBAFU " to " LBAFU " due to alignment\n",
+	       blks_start, blks_start + blks_size);
+
+	blks = blk_derase(dev_desc, blks_start, blks_size);
+	if (blks != blks_size) {
+		printf("failed erasing from device %d", dev_desc->devnum);
+		sprintf(response, "FAILerasing of MMC card");
+		return;
+	}
+
+	printf("........ erased " LBAFU " bytes from '%s'\n",
+	       blks_size * info.blksz, cmdbuf);
+	sprintf(response, "OKAY");
+
+    return;
+}
diff --git a/drivers/fastboot/fb_fsl/fb_fsl_getvar.c b/drivers/fastboot/fb_fsl/fb_fsl_getvar.c
new file mode 100644
index 00000000000..49caf3d7eb9
--- /dev/null
+++ b/drivers/fastboot/fb_fsl/fb_fsl_getvar.c
@@ -0,0 +1,607 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <asm/mach-imx/sys_proto.h>
+#include <fb_fsl.h>
+#include <fastboot.h>
+#include <mmc.h>
+#include <android_image.h>
+#include <asm/bootm.h>
+#include <nand.h>
+#include <part.h>
+#include <sparse_format.h>
+#include <image-sparse.h>
+#include <image.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/setup.h>
+#include <env.h>
+#include <version.h>
+
+#ifdef CONFIG_AVB_SUPPORT
+#include <dt_table.h>
+#include <fsl_avb.h>
+#endif
+
+#ifdef CONFIG_ANDROID_THINGS_SUPPORT
+#include <asm-generic/gpio.h>
+#include <asm/mach-imx/gpio.h>
+#include "../lib/avb/fsl/fsl_avbkey.h"
+#include "../arch/arm/include/asm/mach-imx/hab.h"
+#endif
+
+#if defined(CONFIG_FASTBOOT_LOCK)
+#include "fastboot_lock_unlock.h"
+#endif
+
+#include "fb_fsl_common.h"
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#include "u-boot/sha256.h"
+#include <trusty/libtipc.h>
+
+#define ATAP_UUID_SIZE 32
+#define ATAP_UUID_STR_SIZE ((ATAP_UUID_SIZE*2) + 1)
+#endif
+
+#ifdef CONFIG_VIRTUAL_AB_SUPPORT
+#include "fb_fsl_virtual_ab.h"
+#endif
+
+#if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M)
+#define FASTBOOT_COMMON_VAR_NUM 15
+#else
+#define FASTBOOT_COMMON_VAR_NUM 14
+#endif
+
+#define FASTBOOT_VAR_YES    "yes"
+#define FASTBOOT_VAR_NO     "no"
+
+/* common variables of fastboot getvar command */
+char *fastboot_common_var[FASTBOOT_COMMON_VAR_NUM] = {
+	"version",
+	"version-bootloader",
+	"version-baseband",
+	"product",
+	"secure",
+	"max-download-size",
+	"erase-block-size",
+	"logical-block-size",
+	"unlocked",
+	"off-mode-charge",
+	"battery-voltage",
+	"variant",
+	"battery-soc-ok",
+	"is-userspace",
+#if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M)
+	"baseboard_id"
+#endif
+};
+
+/* at-vboot-state variable list */
+#ifdef CONFIG_AVB_ATX
+#define AT_VBOOT_STATE_VAR_NUM 6
+extern struct imx_sec_config_fuse_t const imx_sec_config_fuse;
+extern int fuse_read(u32 bank, u32 word, u32 *val);
+
+char *fastboot_at_vboot_state_var[AT_VBOOT_STATE_VAR_NUM] = {
+	"bootloader-locked",
+	"bootloader-min-versions",
+	"avb-perm-attr-set",
+	"avb-locked",
+	"avb-unlock-disabled",
+	"avb-min-versions"
+};
+#endif
+
+static int strcmp_l1(const char *s1, const char *s2)
+{
+	if (!s1 || !s2)
+		return -1;
+	return strncmp(s1, s2, strlen(s1));
+}
+
+static bool is_slotvar(char *cmd)
+{
+	assert(cmd != NULL);
+	if (!strcmp_l1("has-slot:", cmd) ||
+		!strcmp_l1("slot-successful:", cmd) ||
+		!strcmp_l1("slot-count", cmd) ||
+		!strcmp_l1("slot-suffixes", cmd) ||
+		!strcmp_l1("current-slot", cmd) ||
+		!strcmp_l1("slot-unbootable:", cmd) ||
+		!strcmp_l1("slot-retry-count:", cmd))
+			return true;
+	return false;
+}
+
+static char serial[IMX_SERIAL_LEN];
+
+char *get_serial(void)
+{
+#if defined(CONFIG_SERIAL_TAG) || defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
+	struct tag_serialnr serialnr;
+	memset(serial, 0, IMX_SERIAL_LEN);
+
+	get_board_serial(&serialnr);
+	sprintf(serial, "%08x%08x", serialnr.high, serialnr.low);
+	return serial;
+#else
+	return NULL;
+#endif
+}
+
+#if !defined(PRODUCT_NAME)
+#define PRODUCT_NAME "NXP i.MX"
+#endif
+
+#if !defined(VARIANT_NAME)
+#define VARIANT_NAME "NXP i.MX"
+#endif
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+static void uuid_hex2string(uint8_t *uuid, char* buf, uint32_t uuid_len, uint32_t uuid_strlen) {
+	uint32_t i;
+	if (!uuid || !buf)
+		return;
+	char *cp = buf;
+	char *buf_end = buf + uuid_strlen;
+	for (i = 0; i < uuid_len; i++) {
+		cp += snprintf(cp, buf_end - cp, "%02x", uuid[i]);
+	}
+}
+#endif
+
+#if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M)
+int get_imx8m_baseboard_id(void);
+#endif
+
+static int get_single_var(char *cmd, char *response)
+{
+	char *str = cmd;
+	int chars_left;
+	const char *s;
+	struct mmc *mmc;
+	int mmc_dev_no;
+	int blksz;
+
+	chars_left = FASTBOOT_RESPONSE_LEN - strlen(response) - 1;
+
+	if ((str = strstr(cmd, "partition-size:"))) {
+		str +=strlen("partition-size:");
+		struct fastboot_ptentry* fb_part;
+		fb_part = fastboot_flash_find_ptn(str);
+		if (!fb_part) {
+			strncat(response, "Wrong partition name.", chars_left);
+			fastboot_flash_dump_ptn();
+			return -1;
+		} else {
+			snprintf(response + strlen(response), chars_left,
+				 "0x%llx",
+				 (uint64_t)fb_part->length * get_block_size());
+		}
+	} else if ((str = strstr(cmd, "partition-type:"))) {
+		str +=strlen("partition-type:");
+		struct fastboot_ptentry* fb_part;
+		fb_part = fastboot_flash_find_ptn(str);
+		if (!fb_part) {
+			strncat(response, "Wrong partition name.", chars_left);
+			fastboot_flash_dump_ptn();
+			return -1;
+		} else {
+			strncat(response, fb_part->fstype, chars_left);
+		}
+	} else if ((str = strstr(cmd, "is-logical:"))) {
+		str +=strlen("is-logical:");
+		struct fastboot_ptentry* fb_part;
+		fb_part = fastboot_flash_find_ptn(str);
+		if (!fb_part) {
+			return -1;
+		} else {
+			snprintf(response + strlen(response), chars_left, "no");
+		}
+	} else if (!strcmp_l1("version-baseband", cmd)) {
+		strncat(response, "N/A", chars_left);
+	} else if (!strcmp_l1("version-bootloader", cmd) ||
+		!strcmp_l1("bootloader-version", cmd)) {
+		strncat(response, U_BOOT_VERSION, chars_left);
+	} else if (!strcmp_l1("version", cmd)) {
+		strncat(response, FASTBOOT_VERSION, chars_left);
+	} else if (!strcmp_l1("battery-voltage", cmd)) {
+		strncat(response, "0mV", chars_left);
+	} else if (!strcmp_l1("battery-soc-ok", cmd)) {
+		strncat(response, "yes", chars_left);
+	} else if (!strcmp_l1("variant", cmd)) {
+		strncat(response, VARIANT_NAME, chars_left);
+	} else if (!strcmp_l1("off-mode-charge", cmd)) {
+		strncat(response, "1", chars_left);
+	} else if (!strcmp_l1("is-userspace", cmd)) {
+		strncat(response, FASTBOOT_VAR_NO, chars_left);
+	} else if (!strcmp_l1("downloadsize", cmd) ||
+		!strcmp_l1("max-download-size", cmd)) {
+
+		snprintf(response + strlen(response), chars_left, "0x%x", CONFIG_FASTBOOT_BUF_SIZE);
+	} else if (!strcmp_l1("erase-block-size", cmd)) {
+		mmc_dev_no = mmc_get_env_dev();
+		mmc = find_mmc_device(mmc_dev_no);
+		if (!mmc) {
+			strncat(response, "FAILCannot get dev", chars_left);
+			return -1;
+		}
+		blksz = get_block_size();
+		snprintf(response + strlen(response), chars_left, "0x%x",
+				(blksz * mmc->erase_grp_size));
+	} else if (!strcmp_l1("logical-block-size", cmd)) {
+		blksz = get_block_size();
+		snprintf(response + strlen(response), chars_left, "0x%x", blksz);
+	} else if (!strcmp_l1("serialno", cmd)) {
+		s = get_serial();
+		if (s)
+			strncat(response, s, chars_left);
+		else {
+			strncat(response, "FAILValue not set", chars_left);
+			return -1;
+		}
+	} else if (!strcmp_l1("product", cmd)) {
+		strncat(response, PRODUCT_NAME, chars_left);
+	}
+#ifdef CONFIG_IMX_TRUSTY_OS
+        else if(!strcmp_l1("at-attest-uuid", cmd)) {
+		char *uuid;
+		char uuid_str[ATAP_UUID_STR_SIZE];
+		if (trusty_atap_read_uuid_str(&uuid)) {
+			printf("ERROR read uuid failed!\n");
+			strncat(response, "FAILCannot get uuid!", chars_left);
+			return -1;
+		} else {
+			uuid_hex2string((uint8_t*)uuid, uuid_str,ATAP_UUID_SIZE, ATAP_UUID_STR_SIZE);
+			strncat(response, uuid_str, chars_left);
+			trusty_free(uuid);
+		}
+	}
+	else if(!strcmp_l1("at-attest-dh", cmd)) {
+		strncat(response, "1:P256,2:curve25519", chars_left);
+	}
+#endif
+#if defined(CONFIG_FASTBOOT_LOCK)
+	else if (!strcmp_l1("secure", cmd)) {
+		strncat(response, FASTBOOT_VAR_YES, chars_left);
+	} else if (!strcmp_l1("unlocked",cmd)){
+		int status = fastboot_get_lock_stat();
+		if (status == FASTBOOT_UNLOCK) {
+			strncat(response, FASTBOOT_VAR_YES, chars_left);
+		} else {
+			strncat(response, FASTBOOT_VAR_NO, chars_left);
+		}
+	}
+#else
+	else if (!strcmp_l1("secure", cmd)) {
+		strncat(response, FASTBOOT_VAR_NO, chars_left);
+	} else if (!strcmp_l1("unlocked",cmd)) {
+		strncat(response, FASTBOOT_VAR_NO, chars_left);
+	}
+#endif
+	else if (is_slotvar(cmd)) {
+#ifdef CONFIG_AVB_SUPPORT
+		if (get_slotvar_avb(&fsl_avb_ab_ops, cmd,
+				response + strlen(response), chars_left + 1) < 0)
+			return -1;
+#else
+		strncat(response, FASTBOOT_VAR_NO, chars_left);
+#endif
+	}
+#if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M)
+	else if (!strcmp_l1("baseboard_id", cmd)) {
+		int baseboard_id;
+
+		baseboard_id = get_imx8m_baseboard_id();
+		if (baseboard_id < 0) {
+			printf("Get baseboard id failed!\n");
+			strncat(response, "Get baseboard id failed!", chars_left);
+			return -1;
+		} else
+			snprintf(response + strlen(response), chars_left, "0x%x", baseboard_id);
+	}
+#endif
+#ifdef CONFIG_AVB_ATX
+	else if (!strcmp_l1("bootloader-locked", cmd)) {
+
+		/* Below is basically copied from is_hab_enabled() */
+		struct imx_sec_config_fuse_t *fuse =
+			(struct imx_sec_config_fuse_t *)&imx_sec_config_fuse;
+		uint32_t reg;
+		int ret;
+
+		/* Read the secure boot status from fuse. */
+		ret = fuse_read(fuse->bank, fuse->word, &reg);
+		if (ret) {
+			printf("\nSecure boot fuse read error!\n");
+			strncat(response, "Secure boot fuse read error!", chars_left);
+			return -1;
+		}
+		/* Check if the secure boot bit is enabled */
+		if ((reg & 0x2000000) == 0x2000000)
+			strncat(response, "1", chars_left);
+		else
+			strncat(response, "0", chars_left);
+	} else if (!strcmp_l1("bootloader-min-versions", cmd)) {
+#ifndef CONFIG_ARM64
+		/* We don't support bootloader rbindex protection for
+		 * ARM32(like imx7d) and the format is: "bootloader,tee". */
+		strncat(response, "-1,-1", chars_left);
+
+#elif defined(CONFIG_DUAL_BOOTLOADER)
+		/* Rbindex protection for bootloader is supported only when the
+		 * 'dual bootloader' feature is enabled. U-boot will get the rbindx
+		 * from RAM which is passed by spl because we can only get the rbindex
+		 * at spl stage. The format in this case is: "spl,atf,tee,u-boot".
+		 */
+		struct bl_rbindex_package *bl_rbindex;
+		uint32_t rbindex;
+
+		bl_rbindex = (struct bl_rbindex_package *)BL_RBINDEX_LOAD_ADDR;
+		if (!strncmp(bl_rbindex->magic, BL_RBINDEX_MAGIC,
+				BL_RBINDEX_MAGIC_LEN)) {
+			rbindex = bl_rbindex->rbindex;
+			snprintf(response + strlen(response), chars_left,
+					"-1,%d,%d,%d",rbindex, rbindex, rbindex);
+		} else {
+			printf("Error bootloader rbindex magic!\n");
+			strncat(response, "Get bootloader rbindex fail!", chars_left);
+			return -1;
+		}
+#else
+		/* Return -1 for all partition if 'dual bootloader' feature
+		 * is not enabled */
+		strncat(response, "-1,-1,-1,-1", chars_left);
+#endif
+	} else if (!strcmp_l1("avb-perm-attr-set", cmd)) {
+		if (perm_attr_are_fused())
+			strncat(response, "1", chars_left);
+		else
+			strncat(response, "0", chars_left);
+	} else if (!strcmp_l1("avb-locked", cmd)) {
+		FbLockState status;
+
+		status = fastboot_get_lock_stat();
+		if (status == FASTBOOT_LOCK)
+			strncat(response, "1", chars_left);
+		else if (status == FASTBOOT_UNLOCK)
+			strncat(response, "0", chars_left);
+		else {
+			printf("Get lock state error!\n");
+			strncat(response, "Get lock state failed!", chars_left);
+			return -1;
+		}
+	} else if (!strcmp_l1("avb-unlock-disabled", cmd)) {
+		if (at_unlock_vboot_is_disabled())
+			strncat(response, "1", chars_left);
+		else
+			strncat(response, "0", chars_left);
+	} else if (!strcmp_l1("avb-min-versions", cmd)) {
+		int i = 0;
+		/* rbindex location/value can be very large
+		 * number so we reserve enough space here.
+		 */
+		char buffer[35];
+		uint32_t rbindex_location[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS + 2];
+		uint32_t location;
+		uint64_t rbindex;
+
+		memset(buffer, '\0', sizeof(buffer));
+
+		/* Set rbindex locations. */
+		for (i = 0; i < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; i++)
+			rbindex_location[i] = i;
+
+		/* Set Android Things key version rbindex locations */
+		rbindex_location[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS]
+						= AVB_ATX_PIK_VERSION_LOCATION;
+		rbindex_location[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS + 1]
+						= AVB_ATX_PSK_VERSION_LOCATION;
+
+		/* Read rollback index and set the reponse*/
+		for (i = 0; i < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS + 2; i++) {
+			location = rbindex_location[i];
+			if (fsl_avb_ops.read_rollback_index(&fsl_avb_ops,
+								location, &rbindex)
+								!= AVB_IO_RESULT_OK) {
+				printf("Read rollback index error!\n");
+				snprintf(response, FASTBOOT_RESPONSE_LEN,
+					"INFOread rollback index error when get avb-min-versions");
+				return -1;
+			}
+			/* Generate the "location:value" pair */
+			snprintf(buffer, sizeof(buffer), "%d:%lld", location, rbindex);
+			if (i != AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS + 1)
+				strncat(buffer, ",", strlen(","));
+
+			if ((chars_left - (int)strlen(buffer)) >= 0) {
+				strncat(response, buffer, strlen(buffer));
+				chars_left -= strlen(buffer);
+			} else {
+				strncat(response, buffer, chars_left);
+				/* reponse buffer is full, send it first */
+				fastboot_tx_write_more(response);
+				/* reset the reponse buffer for next round */
+				memset(response, '\0', FASTBOOT_RESPONSE_LEN);
+				strncpy(response, "INFO", 5);
+				/* Copy left strings from 'buffer' to 'response' */
+				strncat(response, buffer + chars_left, strlen(buffer));
+				chars_left = FASTBOOT_RESPONSE_LEN -
+						strlen(response) - 1;
+			}
+		}
+
+	}
+#endif
+#ifdef CONFIG_VIRTUAL_AB_SUPPORT
+	else if (!strcmp_l1("snapshot-update-status", cmd)) {
+		if (virtual_ab_update_is_merging())
+			strncat(response, "merging", chars_left);
+		else if (virtual_ab_update_is_snapshoted())
+			strncat(response, "snapshotted", chars_left);
+		else
+			strncat(response, "none", chars_left);
+	}
+#endif
+	else {
+		char envstr[32];
+
+		snprintf(envstr, sizeof(envstr) - 1, "fastboot.%s", cmd);
+		s = env_get(envstr);
+		if (s) {
+			strncat(response, s, chars_left);
+		} else {
+			snprintf(response, chars_left, "FAILunknown variable:%s",cmd);
+			printf("WARNING: unknown variable: %s\n", cmd);
+			return -1;
+		}
+	}
+	return 0;
+}
+
+void fastboot_getvar(char *cmd, char *response)
+{
+	int n = 0;
+	int status = 0;
+	int count = 0;
+	char var_name[FASTBOOT_RESPONSE_LEN];
+	char partition_base_name[MAX_PTN][20];
+	char slot_suffix[2][5] = {"a","b"};
+
+	if (!cmd) {
+		pr_err("missing variable");
+		fastboot_fail("missing var", response);
+		return;
+	}
+
+	if (!strcmp_l1("all", cmd)) {
+
+		memset(response, '\0', FASTBOOT_RESPONSE_LEN);
+
+
+		/* get common variables */
+		for (n = 0; n < FASTBOOT_COMMON_VAR_NUM; n++) {
+			snprintf(response, FASTBOOT_RESPONSE_LEN, "INFO%s:", fastboot_common_var[n]);
+			get_single_var(fastboot_common_var[n], response);
+			fastboot_tx_write_more(response);
+		}
+
+		/* get at-vboot-state variables */
+#ifdef CONFIG_AVB_ATX
+		for (n = 0; n < AT_VBOOT_STATE_VAR_NUM; n++) {
+			snprintf(response, FASTBOOT_RESPONSE_LEN, "INFO%s:", fastboot_at_vboot_state_var[n]);
+			get_single_var(fastboot_at_vboot_state_var[n], response);
+			fastboot_tx_write_more(response);
+		}
+#endif
+		/* get partition type */
+		for (n = 0; n < g_pcount; n++) {
+			snprintf(response, FASTBOOT_RESPONSE_LEN, "INFOpartition-type:%s:", g_ptable[n].name);
+			snprintf(var_name, sizeof(var_name), "partition-type:%s", g_ptable[n].name);
+			get_single_var(var_name, response);
+			fastboot_tx_write_more(response);
+		}
+		/* get partition size */
+		for (n = 0; n < g_pcount; n++) {
+			snprintf(response, FASTBOOT_RESPONSE_LEN, "INFOpartition-size:%s:", g_ptable[n].name);
+			snprintf(var_name, sizeof(var_name), "partition-size:%s", g_ptable[n].name);
+			get_single_var(var_name,response);
+			fastboot_tx_write_more(response);
+		}
+		/* slot related variables */
+		if (fastboot_parts_is_slot()) {
+			/* get has-slot variables */
+			count = fastboot_parts_get_name(partition_base_name);
+			for (n = 0; n < count; n++) {
+				snprintf(response, FASTBOOT_RESPONSE_LEN, "INFOhas-slot:%s:", partition_base_name[n]);
+				snprintf(var_name, sizeof(var_name), "has-slot:%s", partition_base_name[n]);
+				get_single_var(var_name,response);
+				fastboot_tx_write_more(response);
+			}
+			/* get current slot */
+			strncpy(response, "INFOcurrent-slot:", FASTBOOT_RESPONSE_LEN);
+			get_single_var("current-slot", response);
+			fastboot_tx_write_more(response);
+			/* get slot count */
+			strncpy(response, "INFOslot-count:", FASTBOOT_RESPONSE_LEN);
+			get_single_var("slot-count", response);
+			fastboot_tx_write_more(response);
+			/* get slot-successful variable */
+			for (n = 0; n < 2; n++) {
+				snprintf(response, FASTBOOT_RESPONSE_LEN, "INFOslot-successful:%s:", slot_suffix[n]);
+				snprintf(var_name, sizeof(var_name), "slot-successful:%s", slot_suffix[n]);
+				get_single_var(var_name, response);
+				fastboot_tx_write_more(response);
+			}
+			/*get slot-unbootable variable*/
+			for (n = 0; n < 2; n++) {
+				snprintf(response, FASTBOOT_RESPONSE_LEN, "INFOslot-unbootable:%s:", slot_suffix[n]);
+				snprintf(var_name, sizeof(var_name), "slot-unbootable:%s", slot_suffix[n]);
+				get_single_var(var_name, response);
+				fastboot_tx_write_more(response);
+			}
+			/*get slot-retry-count variable*/
+			for (n = 0; n < 2; n++) {
+				snprintf(response, FASTBOOT_RESPONSE_LEN, "INFOslot-retry-count:%s:", slot_suffix[n]);
+				snprintf(var_name, sizeof(var_name), "slot-retry-count:%s", slot_suffix[n]);
+				get_single_var(var_name, response);
+				fastboot_tx_write_more(response);
+			}
+		}
+
+#ifdef CONFIG_VIRTUAL_AB_SUPPORT
+		strncpy(response, "INFOsnapshot-update-status:", FASTBOOT_RESPONSE_LEN);
+		get_single_var("snapshot-update-status", response);
+		fastboot_tx_write_more(response);
+#endif
+
+		strncpy(response, "OKAYDone!", 10);
+		fastboot_tx_write_more(response);
+		fastboot_none_resp(response);
+
+		return;
+	}
+#ifdef CONFIG_AVB_ATX
+	else if (!strcmp_l1("at-vboot-state", cmd)) {
+			/* get at-vboot-state variables */
+		for (n = 0; n < AT_VBOOT_STATE_VAR_NUM; n++) {
+			snprintf(response, FASTBOOT_RESPONSE_LEN, "INFO%s:", fastboot_at_vboot_state_var[n]);
+			get_single_var(fastboot_at_vboot_state_var[n], response);
+			fastboot_tx_write_more(response);
+		}
+
+		strncpy(response, "OKAY", 5);
+		fastboot_tx_write_more(response);
+		fastboot_none_resp(response);
+
+		return;
+	} else if ((!strcmp_l1("bootloader-locked", cmd)) ||
+			(!strcmp_l1("bootloader-min-versions", cmd)) ||
+			(!strcmp_l1("avb-perm-attr-set", cmd)) ||
+			(!strcmp_l1("avb-locked", cmd)) ||
+			(!strcmp_l1("avb-unlock-disabled", cmd)) ||
+			(!strcmp_l1("avb-min-versions", cmd))) {
+
+		printf("Can't get this variable alone, get 'at-vboot-state' instead!\n");
+		fastboot_fail("Can't get this variable alone, get 'at-vboot-state' instead.", response);
+		return;
+	}
+#endif
+	else {
+		char reason[FASTBOOT_RESPONSE_LEN];
+		memset(reason, '\0', FASTBOOT_RESPONSE_LEN);
+
+		status = get_single_var(cmd, reason);
+		if (status != 0)
+			fastboot_fail(reason, response);
+		else
+			fastboot_okay(reason, response);
+
+		return;
+	}
+}
diff --git a/drivers/fastboot/fb_fsl/fb_fsl_partitions.c b/drivers/fastboot/fb_fsl/fb_fsl_partitions.c
new file mode 100644
index 00000000000..237ae875ab8
--- /dev/null
+++ b/drivers/fastboot/fb_fsl/fb_fsl_partitions.c
@@ -0,0 +1,412 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2020 NXP
+ */
+
+#include <asm/mach-imx/sys_proto.h>
+#include <fb_fsl.h>
+#include <fastboot.h>
+#include <mmc.h>
+#include <android_image.h>
+#include <asm/bootm.h>
+#include <nand.h>
+#include <part.h>
+#include <sparse_format.h>
+#include <image-sparse.h>
+#include <image.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/setup.h>
+#include <env.h>
+#ifdef CONFIG_DM_SCSI
+#include <scsi.h>
+#endif
+
+#if defined(CONFIG_FASTBOOT_LOCK)
+#include "fastboot_lock_unlock.h"
+#endif
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#include "u-boot/sha256.h"
+#include <trusty/libtipc.h>
+#endif
+
+
+#ifndef TRUSTY_OS_MMC_BLKS
+#define TRUSTY_OS_MMC_BLKS 0x7FF
+#endif
+
+#define MEK_8QM_EMMC 0
+
+enum {
+	PTN_GPT_INDEX = 0,
+	PTN_TEE_INDEX,
+#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT
+	PTN_MCU_OS_INDEX,
+#endif
+	PTN_ALL_INDEX,
+	PTN_BOOTLOADER_INDEX,
+};
+
+struct fastboot_ptentry g_ptable[MAX_PTN];
+unsigned int g_pcount;
+
+static ulong bootloader_mmc_offset(void)
+{
+	if (is_imx8mq() || is_imx8mm() || ((is_imx8qm() || is_imx8qxp()) && is_soc_rev(CHIP_REV_A)))
+		return 0x8400;
+	else if (is_imx8qm() || (is_imx8qxp() && !is_soc_rev(CHIP_REV_B))) {
+		if (MEK_8QM_EMMC == fastboot_devinfo.dev_id)
+		/* target device is eMMC boot0 partition, bootloader offset is 0x0 */
+			return 0x0;
+		else
+		/* target device is SD card, bootloader offset is 0x8000 */
+			return 0x8000;
+	} else if (is_imx8mn() || is_imx8mp() || is_imx8dxl() || is_imx8ulp() || is_imx93()) {
+		/* target device is eMMC boot0 partition, bootloader offset is 0x0 */
+		if (env_get_ulong("emmc_dev", 10, 2) == fastboot_devinfo.dev_id)
+			return 0;
+		else
+			return 0x8000;
+	}
+	else if (is_imx8())
+		return 0x8000;
+	else
+		return 0x400;
+}
+
+bool bootloader_gpt_overlay(void)
+{
+	return (g_ptable[PTN_GPT_INDEX].partition_id  == g_ptable[PTN_BOOTLOADER_INDEX].partition_id  &&
+		bootloader_mmc_offset() < ANDROID_GPT_END);
+}
+
+/**
+   @mmc_dos_partition_index: the partition index in mbr.
+   @mmc_partition_index: the boot partition or user partition index,
+   not related to the partition table.
+ */
+static int _fastboot_parts_add_ptable_entry(int ptable_index,
+				      int mmc_dos_partition_index,
+				      int mmc_partition_index,
+				      const char *name,
+				      const char *fstype,
+				      struct blk_desc *dev_desc,
+				      struct fastboot_ptentry *ptable)
+{
+	struct disk_partition info;
+
+	if (part_get_info(dev_desc,
+			       mmc_dos_partition_index, &info)) {
+		debug("Bad partition index:%d for partition:%s\n",
+		       mmc_dos_partition_index, name);
+		return -1;
+	}
+	ptable[ptable_index].start = info.start;
+	ptable[ptable_index].length = info.size;
+	ptable[ptable_index].partition_id = mmc_partition_index;
+	ptable[ptable_index].partition_index = mmc_dos_partition_index;
+	strncpy(ptable[ptable_index].name, (const char *)info.name,
+			sizeof(ptable[ptable_index].name) - 1);
+
+#ifdef CONFIG_PARTITION_UUIDS
+	strcpy(ptable[ptable_index].uuid, (const char *)info.uuid);
+#endif
+#ifdef CONFIG_ANDROID_AB_SUPPORT
+	if (!strcmp((const char *)info.name, FASTBOOT_PARTITION_SYSTEM_A) ||
+	    !strcmp((const char *)info.name, FASTBOOT_PARTITION_SYSTEM_B) ||
+	    !strcmp((const char *)info.name, FASTBOOT_PARTITION_OEM_A) ||
+	    !strcmp((const char *)info.name, FASTBOOT_PARTITION_VENDOR_A) ||
+	    !strcmp((const char *)info.name, FASTBOOT_PARTITION_OEM_B) ||
+	    !strcmp((const char *)info.name, FASTBOOT_PARTITION_VENDOR_B) ||
+	    !strcmp((const char *)info.name, FASTBOOT_PARTITION_DATA) ||
+#else
+	if (!strcmp((const char *)info.name, FASTBOOT_PARTITION_SYSTEM) ||
+	    !strcmp((const char *)info.name, FASTBOOT_PARTITION_DATA) ||
+	    !strcmp((const char *)info.name, FASTBOOT_PARTITION_DEVICE) ||
+	    !strcmp((const char *)info.name, FASTBOOT_PARTITION_CACHE) ||
+#endif
+	    !strcmp((const char *)info.name, FASTBOOT_PARTITION_METADATA))
+		strcpy(ptable[ptable_index].fstype, "ext4");
+	else
+		strcpy(ptable[ptable_index].fstype, "raw");
+	return 0;
+}
+
+static int _fastboot_parts_load_from_ptable(void)
+{
+	int i;
+
+	/* mmc boot partition: -1 means no partition, 0 user part., 1 boot part.
+	 * default is no partition, for emmc default user part, except emmc*/
+	int boot_partition = FASTBOOT_MMC_NONE_PARTITION_ID;
+	int user_partition = FASTBOOT_MMC_NONE_PARTITION_ID;
+
+	unsigned long boot_loader_psize = ANDROID_BOOTLOADER_SIZE;
+
+	struct mmc *mmc;
+	struct blk_desc *dev_desc;
+	struct fastboot_ptentry ptable[MAX_PTN];
+
+	/* sata case in env */
+	if (fastboot_devinfo.type == DEV_SATA) {
+#ifdef CONFIG_DM_SCSI
+		int sata_device_no = fastboot_devinfo.dev_id;
+		puts("flash target is SATA\n");
+		scsi_scan(false);
+		dev_desc = blk_get_dev("scsi", sata_device_no);
+#else /*! CONFIG_SATA*/
+		puts("SATA isn't buildin\n");
+		return -1;
+#endif /*! CONFIG_SATA*/
+	} else if (fastboot_devinfo.type == DEV_MMC) {
+		int mmc_no = fastboot_devinfo.dev_id;
+
+		printf("flash target is MMC:%d\n", mmc_no);
+		mmc = find_mmc_device(mmc_no);
+
+		if (mmc == NULL) {
+			printf("invalid mmc device %d\n", mmc_no);
+			return -1;
+		}
+
+		/* Force to init mmc */
+		mmc->has_init = 0;
+		if (mmc_init(mmc))
+			printf("MMC card init failed!\n");
+
+		dev_desc = blk_get_dev("mmc", mmc_no);
+		if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+			printf("** Block device MMC %d not supported\n",
+				mmc_no);
+			return -1;
+		}
+
+		/* multiple boot paritions for eMMC 4.3 later */
+		if (mmc->part_config != MMCPART_NOAVAILABLE) {
+			boot_partition = FASTBOOT_MMC_BOOT_PARTITION_ID;
+			user_partition = FASTBOOT_MMC_USER_PARTITION_ID;
+			boot_loader_psize = mmc->capacity_boot;
+		}
+	} else {
+		printf("Can't setup partition table on this device %d\n",
+			fastboot_devinfo.type);
+		return -1;
+	}
+
+	memset((char *)ptable, 0,
+		    sizeof(struct fastboot_ptentry) * (MAX_PTN));
+	/* GPT */
+	strcpy(ptable[PTN_GPT_INDEX].name, FASTBOOT_PARTITION_GPT);
+	ptable[PTN_GPT_INDEX].start = ANDROID_GPT_OFFSET / dev_desc->blksz;
+	ptable[PTN_GPT_INDEX].length = ANDROID_GPT_SIZE  / dev_desc->blksz;
+	ptable[PTN_GPT_INDEX].partition_id = user_partition;
+	ptable[PTN_GPT_INDEX].flags = FASTBOOT_PTENTRY_FLAGS_UNERASEABLE;
+	strcpy(ptable[PTN_GPT_INDEX].fstype, "raw");
+
+#ifndef CONFIG_ARM64
+	/* Trusty OS */
+	strcpy(ptable[PTN_TEE_INDEX].name, FASTBOOT_PARTITION_TEE);
+	ptable[PTN_TEE_INDEX].start = 0;
+	ptable[PTN_TEE_INDEX].length = TRUSTY_OS_MMC_BLKS;
+	ptable[PTN_TEE_INDEX].partition_id = TEE_HWPARTITION_ID;
+	strcpy(ptable[PTN_TEE_INDEX].fstype, "raw");
+#endif
+
+	/* Add mcu_os partition if we support mcu firmware image flash */
+#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT
+	strcpy(ptable[PTN_MCU_OS_INDEX].name, FASTBOOT_MCU_FIRMWARE_PARTITION);
+	ptable[PTN_MCU_OS_INDEX].start = ANDROID_MCU_FIRMWARE_START / dev_desc->blksz;
+	ptable[PTN_MCU_OS_INDEX].length = ANDROID_MCU_OS_PARTITION_SIZE / dev_desc->blksz;
+	ptable[PTN_MCU_OS_INDEX].flags = FASTBOOT_PTENTRY_FLAGS_UNERASEABLE;
+	ptable[PTN_MCU_OS_INDEX].partition_id = user_partition;
+	strcpy(ptable[PTN_MCU_OS_INDEX].fstype, "raw");
+#endif
+
+	strcpy(ptable[PTN_ALL_INDEX].name, FASTBOOT_PARTITION_ALL);
+	ptable[PTN_ALL_INDEX].start = 0;
+	ptable[PTN_ALL_INDEX].length = dev_desc->lba;
+	ptable[PTN_ALL_INDEX].partition_id = user_partition;
+	strcpy(ptable[PTN_ALL_INDEX].fstype, "device");
+
+	/* Bootloader */
+	strcpy(ptable[PTN_BOOTLOADER_INDEX].name, FASTBOOT_PARTITION_BOOTLOADER);
+	ptable[PTN_BOOTLOADER_INDEX].start =
+				bootloader_mmc_offset() / dev_desc->blksz;
+	ptable[PTN_BOOTLOADER_INDEX].length =
+				 boot_loader_psize / dev_desc->blksz;
+
+	ptable[PTN_BOOTLOADER_INDEX].partition_id = boot_partition;
+	ptable[PTN_BOOTLOADER_INDEX].flags = FASTBOOT_PTENTRY_FLAGS_UNERASEABLE;
+	strcpy(ptable[PTN_BOOTLOADER_INDEX].fstype, "raw");
+
+	int tbl_idx;
+	int part_idx = 1;
+	int ret;
+	for (tbl_idx = PTN_BOOTLOADER_INDEX + 1; tbl_idx < MAX_PTN; tbl_idx++) {
+		ret = _fastboot_parts_add_ptable_entry(tbl_idx,
+				part_idx++,
+				user_partition,
+				NULL,
+				NULL,
+				dev_desc, ptable);
+		if (ret)
+			break;
+	}
+	for (i = 0; i < tbl_idx; i++)
+		fastboot_flash_add_ptn(&ptable[i]);
+
+	return 0;
+}
+
+void fastboot_load_partitions(void)
+{
+	g_pcount = 0;
+	_fastboot_parts_load_from_ptable();
+}
+
+/*
+ * Android style flash utilties */
+void fastboot_flash_add_ptn(struct fastboot_ptentry *ptn)
+{
+	if (g_pcount < MAX_PTN) {
+		memcpy(g_ptable + g_pcount, ptn, sizeof(struct fastboot_ptentry));
+		g_pcount++;
+	}
+}
+
+void fastboot_flash_dump_ptn(void)
+{
+	unsigned int n;
+	for (n = 0; n < g_pcount; n++) {
+		struct fastboot_ptentry *ptn = g_ptable + n;
+		printf("idx %d, ptn %d name='%s' start=%d len=%ld\n",
+			n, ptn->partition_index, ptn->name, ptn->start, ptn->length);
+	}
+}
+
+
+struct fastboot_ptentry *fastboot_flash_find_ptn(const char *name)
+{
+	unsigned int n;
+
+	for (n = 0; n < g_pcount; n++) {
+		/* Make sure a substring is not accepted */
+		if (strlen(name) == strlen(g_ptable[n].name)) {
+			if (0 == strcmp(g_ptable[n].name, name))
+				return g_ptable + n;
+		}
+	}
+
+	return 0;
+}
+
+int fastboot_flash_find_index(const char *name)
+{
+	struct fastboot_ptentry *ptentry = fastboot_flash_find_ptn(name);
+	if (ptentry == NULL) {
+		printf("cannot get the partion info for %s\n",name);
+		fastboot_flash_dump_ptn();
+		return -1;
+	}
+	return ptentry->partition_index;
+}
+
+struct fastboot_ptentry *fastboot_flash_get_ptn(unsigned int n)
+{
+	if (n < g_pcount)
+		return g_ptable + n;
+	else
+		return 0;
+}
+
+unsigned int fastboot_flash_get_ptn_count(void)
+{
+	return g_pcount;
+}
+
+bool fastboot_parts_is_raw(struct fastboot_ptentry *ptn)
+{
+	if (ptn) {
+		if (!strncmp(ptn->name, FASTBOOT_PARTITION_BOOTLOADER,
+			strlen(FASTBOOT_PARTITION_BOOTLOADER)))
+			return true;
+#ifdef CONFIG_ANDROID_AB_SUPPORT
+		else if (!strncmp(ptn->name, FASTBOOT_PARTITION_GPT,
+			strlen(FASTBOOT_PARTITION_GPT)) ||
+			!strncmp(ptn->name, FASTBOOT_PARTITION_BOOT_A,
+			strlen(FASTBOOT_PARTITION_BOOT_A)) ||
+			!strncmp(ptn->name, FASTBOOT_PARTITION_BOOT_B,
+			strlen(FASTBOOT_PARTITION_BOOT_B)))
+			return true;
+#else
+		else if (!strncmp(ptn->name, FASTBOOT_PARTITION_BOOT,
+			strlen(FASTBOOT_PARTITION_BOOT)))
+			return true;
+#endif
+#if defined(CONFIG_FASTBOOT_LOCK)
+		else if (!strncmp(ptn->name, FASTBOOT_PARTITION_FBMISC,
+			strlen(FASTBOOT_PARTITION_FBMISC)))
+			return true;
+#endif
+		else if (!strncmp(ptn->name, FASTBOOT_PARTITION_MISC,
+			strlen(FASTBOOT_PARTITION_MISC)))
+			return true;
+	}
+
+	 return false;
+}
+
+static bool is_exist(char (*partition_base_name)[20], char *buffer, int count)
+{
+	int n;
+
+	for (n = 0; n < count; n++) {
+		if (!strcmp(partition_base_name[n],buffer))
+			return true;
+	}
+	return false;
+}
+
+/*get partition base name from gpt without "_a/_b"*/
+int fastboot_parts_get_name(char (*partition_base_name)[20])
+{
+	int n = 0;
+	int count = 0;
+	char *ptr1, *ptr2;
+	char buffer[20];
+
+	for (n = 0; n < g_pcount; n++) {
+		strcpy(buffer,g_ptable[n].name);
+		ptr1 = strstr(buffer, "_a");
+		ptr2 = strstr(buffer, "_b");
+		if (ptr1 != NULL) {
+			*ptr1 = '\0';
+			if (!is_exist(partition_base_name,buffer,count)) {
+				strcpy(partition_base_name[count++],buffer);
+			}
+		} else if (ptr2 != NULL) {
+			*ptr2 = '\0';
+			if (!is_exist(partition_base_name,buffer,count)) {
+				strcpy(partition_base_name[count++],buffer);
+			}
+		} else {
+			strcpy(partition_base_name[count++],buffer);
+		}
+	}
+	return count;
+}
+
+bool fastboot_parts_is_slot(void)
+{
+	char slot_suffix[2][5] = {"_a","_b"};
+	int n;
+
+	for (n = 0; n < g_pcount; n++) {
+		if (strstr(g_ptable[n].name, slot_suffix[0]) ||
+		strstr(g_ptable[n].name, slot_suffix[1]))
+			return true;
+	}
+	return false;
+}
+
diff --git a/drivers/fastboot/fb_fsl/fb_fsl_virtual_ab.c b/drivers/fastboot/fb_fsl/fb_fsl_virtual_ab.c
new file mode 100644
index 00000000000..11260e6b251
--- /dev/null
+++ b/drivers/fastboot/fb_fsl/fb_fsl_virtual_ab.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include <part.h>
+#include "android_bootloader_message.h"
+#include "../lib/avb/fsl/utils.h"
+#include "fb_fsl_virtual_ab.h"
+#include "fsl_avb.h"
+#include "fb_fsl.h"
+
+static int read_virtual_ab_message(misc_virtual_ab_message *message)
+{
+	size_t num_bytes;
+	int source_slot;
+
+	if (fsl_read_from_partition_multi(NULL, FASTBOOT_PARTITION_MISC,
+					SYSTEM_SPACE_SIZE_IN_MISC,
+					sizeof(misc_virtual_ab_message),
+					(void *)message, &num_bytes) || (num_bytes != sizeof(misc_virtual_ab_message))) {
+		printf("Error reading virtual AB message from misc!\n");
+		return -1;
+	}
+
+	if ((message->magic != MISC_VIRTUAL_AB_MAGIC_HEADER) ||
+		(message->version != MISC_VIRTUAL_AB_MESSAGE_VERSION)) {
+		printf("Invalid virtual AB status, resetting...\n");
+		message->version = MISC_VIRTUAL_AB_MESSAGE_VERSION;
+		message->magic = MISC_VIRTUAL_AB_MAGIC_HEADER;
+		message->merge_status = VIRTUAL_AB_NONE;
+
+		/* Reset the source slot as the current slot */
+		source_slot = current_slot();
+		if (source_slot != -1)
+			message->source_slot = source_slot;
+		else
+			return -1;
+
+		if (fsl_write_to_partition(NULL, FASTBOOT_PARTITION_MISC,
+						SYSTEM_SPACE_SIZE_IN_MISC,
+						sizeof(misc_virtual_ab_message),
+						(void *)message)) {
+			printf("Error writing virtual AB message to misc!\n");
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+/* Flash or erase shall be prohibited to "misc", "userdata" and "metadata" partitions
+ * when the virtual AB status is VIRTUAL_AB_MERGING or VIRTUAL_AB_SNAPSHOTTED.
+ * */
+bool partition_is_protected_during_merge(char *part)
+{
+	if ((!strncmp(part, "misc", sizeof("misc")) ||
+		!strncmp(part, "userdata", sizeof("userdata")) ||
+		!strncmp(part, "metadata", sizeof("metadata"))) &&
+		(virtual_ab_update_is_merging() ||
+		 (virtual_ab_update_is_snapshoted() && !virtual_ab_slot_match())))
+		return true;
+	else
+		return false;
+}
+
+bool virtual_ab_update_is_merging(void)
+{
+	misc_virtual_ab_message message;
+	read_virtual_ab_message(&message);
+	if (message.merge_status == VIRTUAL_AB_MERGING)
+		return true;
+	else
+		return false;
+}
+
+bool virtual_ab_update_is_snapshoted(void)
+{
+	misc_virtual_ab_message message;
+
+	read_virtual_ab_message(&message);
+	if (message.merge_status == VIRTUAL_AB_SNAPSHOTTED)
+		return true;
+	else
+		return false;
+}
+
+bool virtual_ab_slot_match(void)
+{
+	misc_virtual_ab_message message;
+	read_virtual_ab_message(&message);
+
+	if (message.source_slot == current_slot())
+		return true;
+	else
+		return false;
+}
+
+int virtual_ab_cancel_update(void)
+{
+	misc_virtual_ab_message message;
+
+	read_virtual_ab_message(&message);
+	message.merge_status = VIRTUAL_AB_CANCELLED;
+
+	if (fsl_write_to_partition(NULL, FASTBOOT_PARTITION_MISC,
+					SYSTEM_SPACE_SIZE_IN_MISC,
+					sizeof(misc_virtual_ab_message),
+					(void *)&message)) {
+		printf("Error writing virtual AB message to misc!\n");
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/drivers/fastboot/fb_fsl/fb_fsl_virtual_ab.h b/drivers/fastboot/fb_fsl/fb_fsl_virtual_ab.h
new file mode 100644
index 00000000000..13769fdfb04
--- /dev/null
+++ b/drivers/fastboot/fb_fsl/fb_fsl_virtual_ab.h
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __FB_FSL_VIRTUAL_AB_H__
+#define __FB_FSL_VIRTUAL_AB_H__
+
+typedef enum {
+	VIRTUAL_AB_NONE = 0,
+	VIRTUAL_AB_UNKNOWN,
+	VIRTUAL_AB_SNAPSHOTTED,
+	VIRTUAL_AB_MERGING,
+	VIRTUAL_AB_CANCELLED,
+} Virtual_AB_Status;
+
+bool partition_is_protected_during_merge(char *part);
+bool virtual_ab_update_is_merging(void);
+bool virtual_ab_update_is_snapshoted(void);
+bool virtual_ab_slot_match(void);
+int virtual_ab_cancel_update(void);
+
+#endif
diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c
index 4f5870b4838..78e16d91705 100644
--- a/drivers/firmware/scmi/scmi_agent-uclass.c
+++ b/drivers/firmware/scmi/scmi_agent-uclass.c
@@ -90,6 +90,14 @@ static int scmi_bind_protocols(struct udevice *dev)
 				drv = DM_DRIVER_GET(scmi_voltage_domain);
 			}
 			break;
+		case SCMI_PROTOCOL_ID_POWER_DOMAIN:
+			if (IS_ENABLED(CONFIG_POWER_DOMAIN))
+				drv = DM_DRIVER_GET(scmi_power_domain);
+			break;
+		case SCMI_PROTOCOL_ID_SENSOR:
+			if (IS_ENABLED(CONFIG_DM_THERMAL))
+				drv = DM_DRIVER_GET(scmi_thermal);
+			break;
 		default:
 			break;
 		}
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 522dfc195ec..8ff3070c4e2 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -247,6 +247,12 @@ config MXS_GPIO
 	help
 	  Support GPIO controllers on i.MX23 and i.MX28 platforms
 
+config ADP5585_GPIO
+	bool "ADP5585 GPIO driver"
+	depends on DM_GPIO && DM_I2C
+	help
+	  Support ADP5585 GPIO expander on i.MX93 platform
+
 config OMAP_GPIO
 	bool "TI OMAP GPIO driver"
 	depends on ARCH_OMAP2PLUS
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 33f7d41b7db..8ce13ecb783 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -68,7 +68,4 @@ obj-$(CONFIG_MT7621_GPIO)	+= mt7621_gpio.o
 obj-$(CONFIG_MSCC_SGPIO)	+= mscc_sgpio.o
 obj-$(CONFIG_NX_GPIO)		+= nx_gpio.o
 obj-$(CONFIG_SIFIVE_GPIO)	+= sifive-gpio.o
-obj-$(CONFIG_NOMADIK_GPIO)	+= nmk_gpio.o
-obj-$(CONFIG_MAX7320_GPIO)	+= max7320_gpio.o
-obj-$(CONFIG_SL28CPLD_GPIO)	+= sl28cpld-gpio.o
-obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN)	+= zynqmp_gpio_modepin.o
+obj-$(CONFIG_ADP5585_GPIO)	+= adp5585_gpio.o
diff --git a/drivers/gpio/adp5585_gpio.c b/drivers/gpio/adp5585_gpio.c
new file mode 100644
index 00000000000..69ad9ea40d8
--- /dev/null
+++ b/drivers/gpio/adp5585_gpio.c
@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * ADP5585 I/O Expander Controller
+ *
+ * Author: Alice Guo (alice.guo@nxp.com)
+ */
+
+#include <asm/gpio.h>
+#include <dm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <i2c.h>
+
+#define ADP5585_ID			0x00
+#define ADP5585_INT_STATUS		0x01
+#define ADP5585_STATUS			0x02
+#define ADP5585_FIFO_1			0x03
+#define ADP5585_FIFO_2			0x04
+#define ADP5585_FIFO_3			0x05
+#define ADP5585_FIFO_4			0x06
+#define ADP5585_FIFO_5			0x07
+#define ADP5585_FIFO_6			0x08
+#define ADP5585_FIFO_7			0x09
+#define ADP5585_FIFO_8			0x0A
+#define ADP5585_FIFO_9			0x0B
+#define ADP5585_FIFO_10			0x0C
+#define ADP5585_FIFO_11			0x0D
+#define ADP5585_FIFO_12			0x0E
+#define ADP5585_FIFO_13			0x0F
+#define ADP5585_FIFO_14			0x10
+#define ADP5585_FIFO_15			0x11
+#define ADP5585_FIFO_16			0x12
+#define ADP5585_GPI_INT_STAT_A		0x13
+#define ADP5585_GPI_INT_STAT_B		0x14
+#define ADP5585_GPI_STATUS_A		0x15
+#define ADP5585_GPI_STATUS_B		0x16
+#define ADP5585_RPULL_CONFIG_A		0x17
+#define ADP5585_RPULL_CONFIG_B		0x18
+#define ADP5585_RPULL_CONFIG_C		0x19
+#define ADP5585_RPULL_CONFIG_D		0x1A
+#define ADP5585_GPI_INT_LEVEL_A		0x1B
+#define ADP5585_GPI_INT_LEVEL_B		0x1C
+#define ADP5585_GPI_EVENT_EN_A		0x1D
+#define ADP5585_GPI_EVENT_EN_B		0x1E
+#define ADP5585_GPI_INTERRUPT_EN_A	0x1F
+#define ADP5585_GPI_INTERRUPT_EN_B	0x20
+#define ADP5585_DEBOUNCE_DIS_A		0x21
+#define ADP5585_DEBOUNCE_DIS_B		0x22
+#define ADP5585_GPO_DATA_OUT_A		0x23
+#define ADP5585_GPO_DATA_OUT_B		0x24
+#define ADP5585_GPO_OUT_MODE_A		0x25
+#define ADP5585_GPO_OUT_MODE_B		0x26
+#define ADP5585_GPIO_DIRECTION_A	0x27
+#define ADP5585_GPIO_DIRECTION_B	0x28
+#define ADP5585_RESET1_EVENT_A		0x29
+#define ADP5585_RESET1_EVENT_B		0x2A
+#define ADP5585_RESET1_EVENT_C		0x2B
+#define ADP5585_RESET2_EVENT_A		0x2C
+#define ADP5585_RESET2_EVENT_B		0x2D
+#define ADP5585_RESET_CFG		0x2E
+#define ADP5585_PWM_OFFT_LOW		0x2F
+#define ADP5585_PWM_OFFT_HIGH		0x30
+#define ADP5585_PWM_ONT_LOW		0x31
+#define ADP5585_PWM_ONT_HIGH		0x32
+#define ADP5585_PWM_CFG			0x33
+#define ADP5585_LOGIC_CFG		0x34
+#define ADP5585_LOGIC_FF_CFG		0x35
+#define ADP5585_LOGIC_INT_EVENT_EN	0x36
+#define ADP5585_POLL_PTIME_CFG		0x37
+#define ADP5585_PIN_CONFIG_A		0x38
+#define ADP5585_PIN_CONFIG_B		0x39
+#define ADP5585_PIN_CONFIG_D		0x3A
+#define ADP5585_GENERAL_CFG		0x3B
+#define ADP5585_INT_EN			0x3C
+
+#define ADP5585_MAXGPIO			10
+#define ADP5585_BANK(offs)		((offs) > 4)
+#define ADP5585_BIT(offs)		(offs > 4 ? \
+					1u << (offs - 5) : 1u << (offs))
+
+struct adp5585_plat {
+	fdt_addr_t addr;
+	uint8_t id;
+	uint8_t dat_out[2];
+	uint8_t dir[2];
+};
+
+static int adp5585_direction_input(struct udevice *dev, unsigned offset)
+{
+	int ret;
+	unsigned bank;
+	struct adp5585_plat *plat = dev_get_plat(dev);
+
+	bank = ADP5585_BANK(offset);
+
+	plat->dir[bank] &= ~ADP5585_BIT(offset);
+	ret = dm_i2c_write(dev, ADP5585_GPIO_DIRECTION_A + bank, &plat->dir[bank], 1);
+
+	return ret;
+}
+
+static int adp5585_direction_output(struct udevice *dev, unsigned offset,
+				    int value)
+{
+	int ret;
+	unsigned bank, bit;
+	struct adp5585_plat *plat = dev_get_plat(dev);
+
+	bank =  ADP5585_BANK(offset);
+	bit = ADP5585_BIT(offset);
+
+	plat->dir[bank] |= bit;
+
+	if (value)
+		plat->dat_out[bank] |= bit;
+	else
+		plat->dat_out[bank] &= ~bit;
+
+	ret = dm_i2c_write(dev, ADP5585_GPO_DATA_OUT_A + bank, &plat->dat_out[bank], 1);
+	ret |= dm_i2c_write(dev, ADP5585_GPIO_DIRECTION_A + bank, &plat->dir[bank], 1);
+
+	return ret;
+}
+
+static int adp5585_get_value(struct udevice *dev, unsigned offset)
+{
+	struct adp5585_plat *plat = dev_get_plat(dev);
+	unsigned bank = ADP5585_BANK(offset);
+	unsigned bit = ADP5585_BIT(offset);
+	uint8_t val;
+
+	if (plat->dir[bank] & bit)
+		val = plat->dat_out[bank];
+	else
+		dm_i2c_read(dev, ADP5585_GPI_STATUS_A + bank, &val, 1);
+
+	return !!(val & bit);
+}
+
+static int adp5585_set_value(struct udevice *dev, unsigned offset, int value)
+{
+	int ret;
+	unsigned bank, bit;
+	struct adp5585_plat *plat = dev_get_plat(dev);
+
+	bank =  ADP5585_BANK(offset);
+	bit = ADP5585_BIT(offset);
+
+	if (value)
+		plat->dat_out[bank] |= bit;
+	else
+		plat->dat_out[bank] &= ~bit;
+
+	ret = dm_i2c_write(dev, ADP5585_GPO_DATA_OUT_A + bank, &plat->dat_out[bank], 1);
+
+	return ret;
+}
+
+static int adp5585_get_function(struct udevice *dev, unsigned offset)
+{
+	unsigned bank, bit, dir;
+	struct adp5585_plat *plat = dev_get_plat(dev);
+
+	bank =  ADP5585_BANK(offset);
+	bit = ADP5585_BIT(offset);
+	dir = plat->dir[bank] & bit;
+
+	if (!dir)
+		return GPIOF_INPUT;
+	else
+		return GPIOF_OUTPUT;
+}
+
+static int adp5585_xlate(struct udevice *dev, struct gpio_desc *desc,
+			 struct ofnode_phandle_args *args)
+{
+	desc->offset =  args->args[0];
+	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+	return 0;
+}
+
+static const struct dm_gpio_ops adp5585_ops = {
+	.direction_input	= adp5585_direction_input,
+	.direction_output	= adp5585_direction_output,
+	.get_value		= adp5585_get_value,
+	.set_value		= adp5585_set_value,
+	.get_function		= adp5585_get_function,
+	.xlate			= adp5585_xlate,
+};
+
+static int adp5585_probe(struct udevice *dev)
+{
+	struct adp5585_plat *plat = dev_get_plat(dev);
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	int ret;
+
+	if (!plat)
+		return 0;
+
+	plat->addr = dev_read_addr(dev);
+	if (plat->addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	ret = dm_i2c_read(dev, ADP5585_ID, &plat->id, 1);
+	if (ret < 0)
+		return ret;
+
+	uc_priv->gpio_count = ADP5585_MAXGPIO;
+	uc_priv->bank_name = "adp5585-gpio";
+
+	for(int i = 0; i < 2; i++) {
+		ret = dm_i2c_read(dev, ADP5585_GPO_DATA_OUT_A + i, &plat->dat_out[i], 1);
+		if (ret)
+			return ret;
+
+		ret = dm_i2c_read(dev, ADP5585_GPIO_DIRECTION_A + i, &plat->dir[i], 1);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id adp5585_ids[] = {
+	{ .compatible = "adp5585" },
+	{ }
+};
+
+U_BOOT_DRIVER(adp5585) = {
+        .name           = "adp5585",
+        .id             = UCLASS_GPIO,
+        .of_match       = adp5585_ids,
+        .probe          = adp5585_probe,
+        .ops            = &adp5585_ops,
+        .plat_auto      = sizeof(struct adp5585_plat),
+};
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 03471db9e80..3cc0e7f353e 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -5,6 +5,9 @@
  *
  * Copyright (C) 2011
  * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
+ *
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
  */
 #include <common.h>
 #include <errno.h>
@@ -15,6 +18,10 @@
 #include <asm/io.h>
 #include <dt-structs.h>
 #include <mapmem.h>
+#ifdef CONFIG_IMX_RDC
+#include <asm/mach-imx/rdc-sema.h>
+#include <asm/arch/imx-rdc.h>
+#endif
 
 enum mxc_gpio_direction {
 	MXC_GPIO_DIRECTION_IN,
@@ -70,6 +77,27 @@ static unsigned long gpio_ports[] = {
 #endif
 };
 
+#ifdef CONFIG_IMX_RDC
+static unsigned int gpio_rdc[] = {
+	RDC_PER_GPIO1,
+	RDC_PER_GPIO2,
+	RDC_PER_GPIO3,
+	RDC_PER_GPIO4,
+	RDC_PER_GPIO5,
+	RDC_PER_GPIO6,
+	RDC_PER_GPIO7,
+};
+
+#define RDC_CHECK(x) imx_rdc_check_permission(gpio_rdc[x], 0)
+#define RDC_SPINLOCK_UP(x) imx_rdc_sema_lock(gpio_rdc[x])
+#define RDC_SPINLOCK_DOWN(x) imx_rdc_sema_unlock(gpio_rdc[x])
+#else
+#define RDC_CHECK(x) 0
+#define RDC_SPINLOCK_UP(x)
+#define RDC_SPINLOCK_DOWN(x)
+#endif
+
+
 static int mxc_gpio_direction(unsigned int gpio,
 	enum mxc_gpio_direction direction)
 {
@@ -80,6 +108,11 @@ static int mxc_gpio_direction(unsigned int gpio,
 	if (port >= ARRAY_SIZE(gpio_ports))
 		return -1;
 
+	if (RDC_CHECK(port))
+		return -1;
+
+	RDC_SPINLOCK_UP(port);
+
 	gpio &= 0x1f;
 
 	regs = (struct gpio_regs *)gpio_ports[port];
@@ -95,6 +128,8 @@ static int mxc_gpio_direction(unsigned int gpio,
 	}
 	writel(l, &regs->gpio_dir);
 
+	RDC_SPINLOCK_DOWN(port);
+
 	return 0;
 }
 
@@ -107,6 +142,11 @@ int gpio_set_value(unsigned gpio, int value)
 	if (port >= ARRAY_SIZE(gpio_ports))
 		return -1;
 
+	if (RDC_CHECK(port))
+		return -1;
+
+	RDC_SPINLOCK_UP(port);
+
 	gpio &= 0x1f;
 
 	regs = (struct gpio_regs *)gpio_ports[port];
@@ -118,6 +158,8 @@ int gpio_set_value(unsigned gpio, int value)
 		l &= ~(1 << gpio);
 	writel(l, &regs->gpio_dr);
 
+	RDC_SPINLOCK_DOWN(port);
+
 	return 0;
 }
 
@@ -130,11 +172,18 @@ int gpio_get_value(unsigned gpio)
 	if (port >= ARRAY_SIZE(gpio_ports))
 		return -1;
 
+	if (RDC_CHECK(port))
+		return -1;
+
+	RDC_SPINLOCK_UP(port);
+
 	gpio &= 0x1f;
 
 	regs = (struct gpio_regs *)gpio_ports[port];
 
-	val = (readl(&regs->gpio_psr) >> gpio) & 0x01;
+	val = (readl(&regs->gpio_dr) >> gpio) & 0x01;
+
+	RDC_SPINLOCK_DOWN(port);
 
 	return val;
 }
@@ -144,6 +193,10 @@ int gpio_request(unsigned gpio, const char *label)
 	unsigned int port = GPIO_TO_PORT(gpio);
 	if (port >= ARRAY_SIZE(gpio_ports))
 		return -1;
+
+	if (RDC_CHECK(port))
+		return -1;
+
 	return 0;
 }
 
@@ -211,7 +264,7 @@ static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset,
 
 static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
 {
-	return (readl(&regs->gpio_psr) >> offset) & 0x01;
+	return (readl(&regs->gpio_dr) >> offset) & 0x01;
 }
 
 /* set GPIO pin 'gpio' as an input */
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
index dc8911a8eb9..acbfdfd57d1 100644
--- a/drivers/gpio/pca953x_gpio.c
+++ b/drivers/gpio/pca953x_gpio.c
@@ -37,6 +37,8 @@
 
 #define PCA_GPIO_MASK           0x00FF
 #define PCA_INT                 0x0100
+#define PCA_PCAL		BIT(9)
+#define PCA_LATCH_INT		(PCA_PCAL | PCA_INT)
 #define PCA953X_TYPE            0x1000
 #define PCA957X_TYPE            0x2000
 #define PCA_TYPE_MASK           0xF000
@@ -363,6 +365,8 @@ static const struct udevice_id pca953x_ids[] = {
 	{ .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
 	{ .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
 
+	{ .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
+
 	{ .compatible = "maxim,max7310", .data = OF_953X(8, 0), },
 	{ .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
 	{ .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 5482a4a470b..d710c598ab8 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -239,6 +239,18 @@ config SYS_I2C_LPC32XX
 	help
 	  Enable support for the LPC32xx I2C driver.
 
+config SYS_I2C_IMX_I3C
+	bool "NXP i.MX I3C driver"
+	help
+	  Add support for the NXP i.MX I3C driver.
+
+config SYS_I2C_IMX_VIRT_I2C
+	bool "NXP i.MX Virtual I2C driver"
+	select IMX_VSERVICE
+	help
+	  Add support for the NXP i.MX Virtual I2C which needs AMP communtication
+	  to work with remote core to access i2c bus.
+
 config SYS_I2C_MESON
 	bool "Amlogic Meson I2C driver"
 	depends on DM_I2C && ARCH_MESON
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 9d41f379bbc..fcd1da77249 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -24,6 +24,8 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
 obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
 obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
 obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o
+obj-$(CONFIG_SYS_I2C_IMX_I3C) += imx_i3c.o
+obj-$(CONFIG_SYS_I2C_IMX_VIRT_I2C) += imx_virt_i2c.o
 obj-$(CONFIG_SYS_I2C_IPROC) += iproc_i2c.o
 obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
 obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
diff --git a/drivers/i2c/imx_i3c.c b/drivers/i2c/imx_i3c.c
new file mode 100644
index 00000000000..849af90f32b
--- /dev/null
+++ b/drivers/i2c/imx_i3c.c
@@ -0,0 +1,680 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * I3C controller driver.
+ *
+ * Copyright 2021 NXP
+ * Author: Clark Wang (xiaoning.wang@nxp.com)
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include "imx_i3c.h"
+
+#define I3C_NACK_TOUT_MS	1
+#define I3C_TIMEOUT_MS		100
+
+struct imx_i3c_bus {
+	int index;
+	ulong base;
+	ulong driver_data;
+	int speed;
+	struct gpio_desc switch_gpio;
+	struct i2c_pads_info *pads_info;
+	struct udevice *bus;
+	struct clk per_clk;
+	struct clk ipg_clk;
+};
+
+static int bus_i3c_init(struct udevice *bus);
+
+/* Weak linked function for overridden by some SoC power function */
+int __weak init_i3c_power(unsigned i2c_num)
+{
+	return 0;
+}
+
+int __weak enable_i3c_clk(unsigned char enable, unsigned int i3c_num)
+{
+	return 0;
+}
+
+int __weak imx_get_i3cclk(u32 i3c_num)
+{
+	return 0;
+}
+
+int __weak board_imx_i3c_bind(struct udevice *dev)
+{
+	return 0;
+}
+
+i3c_master_state_t bus_i3c_masterstate(const struct imx_i3c_reg *regs)
+{
+	u32 masterState = (readl(&regs->mstatus) & I3C_MSTATUS_STATE_MASK) >> I3C_MSTATUS_STATE_SHIFT;
+	i3c_master_state_t returnCode;
+
+	switch (masterState) {
+	case (u32)I3C_MASTERSTATE_IDLE:
+		returnCode = I3C_MASTERSTATE_IDLE;
+		break;
+	case (u32)I3C_MASTERSTATE_SLVREQ:
+		returnCode = I3C_MASTERSTATE_SLVREQ;
+		break;
+	case (u32)I3C_MASTERSTATE_MSGSDR:
+		returnCode = I3C_MASTERSTATE_MSGSDR;
+		break;
+	case (u32)I3C_MASTERSTATE_NORMACT:
+		returnCode = I3C_MASTERSTATE_NORMACT;
+		break;
+	case (u32)I3C_MASTERSTATE_DDR:
+		returnCode = I3C_MASTERSTATE_DDR;
+		break;
+	case (u32)I3C_MASTERSTATE_DAA:
+		returnCode = I3C_MASTERSTATE_DAA;
+		break;
+	case (u32)I3C_MASTERSTATE_IBIACK:
+		returnCode = I3C_MASTERSTATE_IBIACK;
+		break;
+	case (u32)I3C_MASTERSTATE_IBIRCV:
+		returnCode = I3C_MASTERSTATE_IBIRCV;
+		break;
+	default:
+		returnCode = I3C_MASTERSTATE_IDLE;
+		break;
+	}
+
+	return returnCode;
+}
+
+static int imx_i3c_check_busy_bus(const struct imx_i3c_reg *regs)
+{
+	u32 status;
+
+	status = bus_i3c_masterstate(regs);
+	if ((status != I3C_MASTERSTATE_IDLE) && (status != I3C_MASTERSTATE_NORMACT))
+		return status;
+
+	return I3C_SUCESS;
+}
+
+static int bus_i3c_check_clear_error(struct imx_i3c_reg *regs)
+{
+	i3c_status_t result = I3C_SUCESS;
+	u32 val, status;
+
+	status = readl(&regs->merrwarn);
+	/* errors to check for */
+	status &= I3C_MERRWARN_NACK_MASK | I3C_MERRWARN_WRABT_MASK |
+		I3C_MERRWARN_TERM_MASK | I3C_MERRWARN_HPAR_MASK | I3C_MERRWARN_HCRC_MASK |
+		I3C_MERRWARN_OREAD_MASK | I3C_MERRWARN_OWRITE_MASK | I3C_MERRWARN_MSGERR_MASK |
+		I3C_MERRWARN_INVREQ_MASK | I3C_MERRWARN_TIMEOUT_MASK;
+
+	if (status) {
+		/* Select the correct error code. Ordered by severity, with bus issues first. */
+		if (0UL != (status & (u32)I3C_MERRWARN_TIMEOUT_MASK))
+			result = I3C_TIMEOUT;
+		else if (0UL != (status & (u32)I3C_MERRWARN_NACK_MASK))
+			result = I3C_NACK;
+		else if (0UL != (status & (u32)I3C_MERRWARN_WRABT_MASK))
+			result = I3C_WRITE_ABORT_ERR;
+		else if (0UL != (status & (u32)I3C_MERRWARN_TERM_MASK))
+			result = I3C_TERM;
+		else if (0UL != (status & (u32)I3C_MERRWARN_HPAR_MASK))
+			result = I3C_HDR_PARITY_ERR;
+		else if (0UL != (status & (u32)I3C_MERRWARN_HCRC_MASK))
+			result = I3C_CRC_ERR;
+		else if (0UL != (status & (u32)I3C_MERRWARN_MSGERR_MASK))
+			result = I3C_MSG_ERR;
+		else if (0UL != (status & (u32)I3C_MERRWARN_OREAD_MASK))
+			result = I3C_READFIFO_ERR;
+		else if (0UL != (status & (u32)I3C_MERRWARN_OWRITE_MASK))
+			result = I3C_WRITEFIFO_ERR;
+		else if (0UL != (status & (u32)I3C_MERRWARN_INVREQ_MASK))
+			result = I3C_INVALID_REQ;
+
+		/* clear status flags */
+		writel(status, &regs->merrwarn);
+
+		/* reset fifos */
+		val = readl(&regs->mdatactrl);
+		val |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK;
+		writel(val, &regs->mdatactrl);
+	}
+
+	return result;
+}
+
+static int bus_i3c_wait_for_tx_ready(struct imx_i3c_reg *regs, int bytecount)
+{
+	i3c_status_t result = I3C_SUCESS;
+	u32 txcount = 0;
+	ulong start_time = get_timer(0);
+	size_t txFifoSize =
+	2UL << ((readl(&regs->scapabilities) & I3C_SCAPABILITIES_FIFOTX_MASK)
+	>> I3C_SCAPABILITIES_FIFOTX_SHIFT);
+
+	do {
+		txcount = (readl(&regs->mdatactrl) & I3C_MDATACTRL_TXCOUNT_MASK)
+			  >> I3C_MDATACTRL_TXCOUNT_SHIFT;
+		txcount = txFifoSize - txcount;
+
+		result = bus_i3c_check_clear_error(regs);
+		if (result) {
+			debug("i3c: wait for tx ready err: result 0x%x\n", result);
+			return result;
+		}
+		if (get_timer(start_time) > I3C_TIMEOUT_MS) {
+			debug("i3c: wait for tx ready err: timeout\n");
+			return I3C_TIMEOUT;
+		}
+	} while (txcount < bytecount);
+
+	return 0;
+}
+
+static int bus_i3c_send(struct udevice *bus, u8 *txbuf, int len)
+{
+	struct imx_i3c_bus *i3c_bus = dev_get_priv(bus);
+	struct imx_i3c_reg *regs = (struct imx_i3c_reg *)(i3c_bus->base);
+	i3c_status_t result = I3C_SUCESS;
+	bool enableWord = false;
+	u8 byteCounts = 1;
+	ulong start_time;
+
+	/* empty tx */
+	if (!len)
+		return result;
+
+	/* Send data buffer */
+	while (0UL != len) {
+		/* Wait until there is room in the fifo. This also checks for errors. */
+		result = bus_i3c_wait_for_tx_ready(regs, byteCounts);
+		if (I3C_SUCESS != result) {
+			return result;
+		}
+
+		/* Write byte into I3C master data register. */
+		if (len > byteCounts) {
+			if (enableWord)
+				writel((uint32_t)txbuf[1] << 8UL | (uint32_t)txbuf[0], &regs->mwdatah);
+			else
+				writel(*txbuf, &regs->mwdatab);
+		} else {
+			if (enableWord)
+				writel((uint32_t)txbuf[1] << 8UL | (uint32_t)txbuf[0], &regs->mwdatahe);
+			else
+				writel(*txbuf, &regs->mwdatabe);
+		}
+
+		txbuf = txbuf + byteCounts;
+		len  = len - byteCounts;
+	}
+
+	start_time = get_timer(0);
+	while (!(readl(&regs->mstatus) & I3C_MSTATUS_COMPLETE_MASK)) {
+		if (get_timer(start_time) > I3C_TIMEOUT_MS) {
+			dev_err(bus, "i3c: xfer: timeout\n");
+			return -1;
+		}
+	}
+	writel(I3C_MSTATUS_COMPLETE_MASK, &regs->mstatus);
+
+	return 0;
+}
+
+static int bus_i3c_receive(struct udevice *bus, u8 *rxbuf, int len)
+{
+	struct imx_i3c_bus *i3c_bus = dev_get_priv(bus);
+	struct imx_i3c_reg *regs = (struct imx_i3c_reg *)(i3c_bus->base);
+	i3c_status_t result = I3C_SUCESS;
+	u32 val;
+	ulong start_time = get_timer(0);
+
+	/* empty read */
+	if (!len)
+		return result;
+
+	result = bus_i3c_wait_for_tx_ready(regs, 1);
+	if (result) {
+		dev_err(bus, "i3c: receive wait for tx ready: %d\n", result);
+		return result;
+	}
+
+	/* clear all status flags */
+	val = readl(&regs->mstatus);
+	writel(val, &regs->mstatus);
+
+	while (len--) {
+		do {
+			result = bus_i3c_check_clear_error(regs);
+			if (result) {
+				dev_err(bus, "i3c: receive check clear error: %d\n",
+				      result);
+				return result;
+			}
+			if (get_timer(start_time) > I3C_TIMEOUT_MS) {
+				dev_err(bus, "i3c: receive mrdr: timeout\n");
+				return -1;
+			}
+			val = readl(&regs->mdatactrl);
+		} while (val & I3C_MDATACTRL_RXEMPTY_MASK);
+		val = readl(&regs->mrdatab);
+		*rxbuf++ = I3C_MRDATAB_VALUE(val);
+	}
+
+	start_time = get_timer(0);
+	while (!(readl(&regs->mstatus) & I3C_MSTATUS_COMPLETE_MASK)) {
+		if (get_timer(start_time) > I3C_TIMEOUT_MS) {
+			dev_err(bus, "i3c: xfer: timeout\n");
+			return -1;
+		}
+	}
+	writel(I3C_MSTATUS_COMPLETE_MASK, &regs->mstatus);
+
+	return 0;
+}
+
+static int bus_i3c_start(struct udevice *bus, u8 addr, u8 dir, u32 rxSize)
+{
+	struct imx_i3c_bus *i3c_bus = dev_get_priv(bus);
+	struct imx_i3c_reg *regs = (struct imx_i3c_reg *)(i3c_bus->base);
+	i3c_status_t result;
+	ulong start_time = get_timer(0);
+	u32 val;
+
+	result = imx_i3c_check_busy_bus(regs);
+	if (result) {
+		/* Try to init the bus then check the bus busy again */
+		bus_i3c_init(bus);
+		result = imx_i3c_check_busy_bus(regs);
+		if (result) {
+			dev_err(bus, "i3c: Error check busy bus: 0x%x\n", result);
+			return result;
+		}
+	}
+
+	/* clear all status flags */
+	val = readl(&regs->mstatus);
+	writel(val, &regs->mstatus);
+
+	/* wait tx fifo ready */
+	result = bus_i3c_wait_for_tx_ready(regs, 1);
+	if (result) {
+		dev_err(bus, "i3c: start wait for tx ready: 0x%x\n", result);
+		return result;
+	}
+
+	/* Issue start command. */
+	val = readl(&regs->mctrl);
+	val &= ~(I3C_MCTRL_TYPE_MASK | I3C_MCTRL_REQUEST_MASK |
+		 I3C_MCTRL_DIR_MASK | I3C_MCTRL_ADDR_MASK |
+		 I3C_MCTRL_RDTERM_MASK);
+	val |= I3C_MCTRL_TYPE(0) | I3C_MCTRL_REQUEST(1) | I3C_MCTRL_DIR(dir) |
+	       I3C_MCTRL_ADDR(addr) | I3C_MCTRL_RDTERM(rxSize);
+	writel(val, &regs->mctrl);
+
+	while (!(readl(&regs->mstatus) & I3C_MSTATUS_MCTRLDONE_MASK)) {
+		if (get_timer(start_time) > I3C_TIMEOUT_MS) {
+			dev_err(bus, "i3c: start: timeout\n");
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+static int bus_i3c_stop(struct udevice *bus)
+{
+	struct imx_i3c_bus *i3c_bus = dev_get_priv(bus);
+	struct imx_i3c_reg *regs = (struct imx_i3c_reg *)(i3c_bus->base);
+	i3c_status_t result;
+	u32 status, val;
+	ulong start_time;
+
+	result = bus_i3c_wait_for_tx_ready(regs, 1);
+	if (result) {
+		dev_err(bus, "i3c: stop wait for tx ready: 0x%x\n", result);
+		return result;
+	}
+
+	/* send stop command */
+	val = readl(&regs->mctrl);
+	val &= ~(I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK |
+		 I3C_MCTRL_RDTERM_MASK);
+	val |= I3C_MCTRL_REQUEST(0x2);
+	writel(val, &regs->mctrl);
+
+	start_time = get_timer(0);
+	while (1) {
+		status = bus_i3c_masterstate(regs);
+		result = bus_i3c_check_clear_error(regs);
+		/* idle detect flag */
+		if (status == I3C_MASTERSTATE_IDLE) {
+			break;
+		}
+
+		if (get_timer(start_time) > I3C_NACK_TOUT_MS) {
+			dev_err(bus, "stop timeout\n");
+			return -ETIMEDOUT;
+		}
+	}
+
+	return 0;
+}
+
+static int bus_i3c_read(struct udevice *bus, u32 chip, u8 *buf, int len)
+{
+	i3c_status_t result;
+
+	result = bus_i3c_start(bus, chip, 1, len);
+	if (result)
+		return result;
+
+	result = bus_i3c_receive(bus, &buf[0], len);
+	if (result)
+		return result;
+
+	return 0;
+}
+
+static int bus_i3c_write(struct udevice *bus, u32 chip, u8 *buf, int len)
+{
+	i3c_status_t result;
+
+	result = bus_i3c_start(bus, chip, 0, 0);
+	if (result)
+		return result;
+
+	result = bus_i3c_send(bus, &buf[0], len);
+	if (result)
+		return result;
+
+	return 0;
+}
+
+static int bus_i3c_config(struct udevice *bus, struct i2c_msg *msg)
+{
+	struct imx_i3c_bus *i3c_bus = dev_get_priv(bus);
+	struct imx_i3c_reg *regs = (struct imx_i3c_reg *)(i3c_bus->base);
+	i3c_status_t result;
+	u32 val;
+
+	result = imx_i3c_check_busy_bus(regs);
+	if (result)
+		return result;
+
+	val = readl(&regs->mctrl);
+	val &= ~I3C_MCTRL_IBIRESP_MASK;
+	writel(val, &regs->mctrl);
+
+	val = readl(&regs->mdatactrl);
+	val |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK;
+	writel(val, &regs->mdatactrl);
+
+	return 0;
+}
+
+static int bus_i3c_set_bus_speed(struct udevice *bus)
+{
+	struct imx_i3c_bus *i3c_bus = dev_get_priv(bus);
+	struct imx_i3c_reg *regs = (struct imx_i3c_reg *)(i3c_bus->base);
+
+	u32 div, freq;
+	u32 ppBaud, odBaud;
+	u32 i3cPPBaud_HZ    = 12500000U;
+	/* max is 1.025*i3cPPBaud_HZ */
+	u32 i3cPPBaudMax_HZ = i3cPPBaud_HZ / 40U + i3cPPBaud_HZ;
+	u32 i3cODBaud_HZ    = 2000000U;
+	/* max is 1.1*i3cODBaud_HZ */
+	u32 i3cODBaudMax_HZ = i3cODBaud_HZ / 10U + i3cODBaud_HZ;
+	u32 sourceClock_Hz, val;
+	u8 mode = 0;
+
+	regs = (struct imx_i3c_reg *)devfdt_get_addr(bus);
+	if (IS_ENABLED(CONFIG_CLK)) {
+		sourceClock_Hz = clk_get_rate(&i3c_bus->per_clk);
+		if (sourceClock_Hz <= 0) {
+			dev_err(bus, "Failed to get i3c clk: %d\n", sourceClock_Hz);
+			return sourceClock_Hz;
+		}
+	} else {
+		sourceClock_Hz = imx_get_i3cclk(dev_seq(bus));
+		if (!sourceClock_Hz)
+			return -EPERM;
+	}
+
+	val = readl(&regs->mconfig);
+	mode = (val & I3C_MCONFIG_MSTENA_MASK) >> I3C_MCONFIG_MSTENA_SHIFT;
+	/* disable master mode */
+	val = val & ~I3C_MCONFIG_MSTENA_MASK;
+	writel(val | I3C_MCONFIG_MSTENA(0), &regs->mconfig);
+	/* Find out the div to generate target freq */
+	freq = sourceClock_Hz / 2;
+	/* ppFreq = FCLK / 2 / (PPBAUD + 1)), 0 <= PPBAUD <= 15 */
+	div = freq / i3cPPBaud_HZ;
+	div = div == 0 ? 1 : div;
+	if (freq / div > i3cPPBaudMax_HZ)
+		div++;
+
+	if (div > (I3C_MCONFIG_PPBAUD_MASK >> I3C_MCONFIG_PPBAUD_SHIFT) + 1)
+		return -EPERM;
+	ppBaud = div - 1;
+	freq /= div;
+	/* odFreq = ppFreq / (ODBAUD + 1), 1 <= ODBAUD <= 255 */
+	div = freq / i3cODBaud_HZ;
+	div = (div < 2) ? 2 : div;
+	if (freq / div > i3cODBaudMax_HZ)
+		div++;
+	odBaud = div - 1;
+	freq /= div;
+
+	val = readl(&regs->mconfig) & ~I3C_MCONFIG_MSTENA_MASK;
+	val &= ~(I3C_MCONFIG_PPBAUD_MASK | I3C_MCONFIG_PPLOW_MASK |
+		 I3C_MCONFIG_ODBAUD_MASK | I3C_MCONFIG_I2CBAUD_MASK);
+	val |= I3C_MCONFIG_PPBAUD(ppBaud) | I3C_MCONFIG_ODBAUD(odBaud) |
+	       I3C_MCONFIG_I2CBAUD(0);
+	writel(val | I3C_MCONFIG_MSTENA(mode), &regs->mconfig);
+
+	debug("ppBaud=%d, odBaud=%d.\n", ppBaud, odBaud);
+	while (readl(&regs->mstatus) & I3C_MSTATUS_SLVSTART_MASK) {
+		val = readl(&regs->mstatus) | I3C_MSTATUS_SLVSTART_MASK;
+		writel(val, &regs->mstatus);
+	}
+	return 0;
+}
+
+static void bus_i3c_reset(struct udevice *bus)
+{
+	struct imx_i3c_bus *i3c_bus = dev_get_priv(bus);
+	struct imx_i3c_reg *regs = (struct imx_i3c_reg *)(i3c_bus->base);
+
+	writel(readl(&regs->mstatus), &regs->mstatus);
+	writel(readl(&regs->merrwarn), &regs->merrwarn);
+
+	/* set watermark */
+	writel(I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK,
+	       &regs->mdatactrl);
+
+	/* reset peripheral */
+	writel(0, &regs->mconfig);
+
+	return;
+}
+
+static int bus_i3c_init(struct udevice *bus)
+{
+	struct imx_i3c_bus *i3c_bus = dev_get_priv(bus);
+	struct imx_i3c_reg *regs = (struct imx_i3c_reg *)(i3c_bus->base);
+	int ret;
+
+	/* reset peripheral */
+	writel(0, &regs->mconfig);
+
+	/* set mconfig */
+	writel(I3C_MCONFIG_MSTENA(1) | I3C_MCONFIG_DISTO(0) |
+		I3C_MCONFIG_HKEEP(0) | I3C_MCONFIG_ODSTOP(1) |
+		I3C_MCONFIG_ODHPP(1), &regs->mconfig);
+
+	/* set watermark */
+	writel(I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK,
+	       &regs->mdatactrl);
+
+	ret = bus_i3c_set_bus_speed(bus);
+	if (ret)
+		return ret;
+
+	dev_dbg(bus, "i3c : controller bus %d, ret:%d:\n", dev_seq(bus), ret);
+
+	return 0;
+}
+
+static int imx_i3c_probe_chip(struct udevice *bus, u32 chip,
+				u32 chip_flags)
+{
+	return 0;
+}
+
+static int imx_i3c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+	int ret = 0, ret_stop;
+
+	bus_i3c_init(bus);
+	bus_i3c_config(bus, msg);
+	if (ret)
+		return ret;
+
+	for (; nmsgs > 0; nmsgs--, msg++) {
+		if (msg->flags & I2C_M_RD)
+			ret = bus_i3c_read(bus, msg->addr, msg->buf, msg->len);
+		else {
+			ret = bus_i3c_write(bus, msg->addr, msg->buf,
+					    msg->len);
+			if (ret)
+				break;
+		}
+	}
+
+	if (ret)
+		dev_dbg(bus, "%s: error sending\n", __func__);
+
+	ret_stop = bus_i3c_stop(bus);
+	if (ret_stop)
+		dev_err(bus, "%s: stop bus error\n", __func__);
+
+	ret |= ret_stop;
+
+	bus_i3c_reset(bus);
+
+	return ret;
+}
+
+static int imx_i3c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+	return bus_i3c_set_bus_speed(bus);
+}
+
+static int imx_i3c_probe(struct udevice *bus)
+{
+	struct imx_i3c_bus *i3c_bus = dev_get_priv(bus);
+	fdt_addr_t addr;
+	int ret;
+
+	i3c_bus->driver_data = dev_get_driver_data(bus);
+
+	addr = dev_read_addr(bus);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	i3c_bus->base = addr;
+	i3c_bus->index = dev_seq(bus);
+	i3c_bus->bus = bus;
+
+	/* power up i3c resource */
+	ret = init_i3c_power(dev_seq(bus));
+	if (ret) {
+		dev_err(bus, "Init i3c power err = %d\n", ret);
+		return ret;
+	}
+
+	/* enable switch */
+	ret = gpio_request_by_name(bus, "switch-gpio", 0, &i3c_bus->switch_gpio,
+				   GPIOD_IS_OUT);
+	if (ret)
+		dev_dbg(bus, "No switch-gpio property\n");
+	dm_gpio_set_value(&i3c_bus->switch_gpio, 1);
+
+	if (IS_ENABLED(CONFIG_CLK)) {
+		ret = clk_get_by_name(bus, "per", &i3c_bus->per_clk);
+		if (ret) {
+			dev_err(bus, "Failed to get per clk\n");
+			return ret;
+		}
+		ret = clk_enable(&i3c_bus->per_clk);
+		if (ret) {
+			dev_err(bus, "Failed to enable per clk\n");
+			return ret;
+		}
+
+		ret = clk_get_by_name(bus, "ipg", &i3c_bus->ipg_clk);
+		if (ret) {
+			dev_err(bus, "Failed to get ipg clk\n");
+			return ret;
+		}
+		ret = clk_enable(&i3c_bus->ipg_clk);
+		if (ret) {
+			dev_err(bus, "Failed to enable ipg clk\n");
+			return ret;
+		}
+	} else {
+		/* To i.MX8ULP, only i3c2 can be handled by A core */
+		ret = enable_i3c_clk(1, dev_seq(bus));
+		if (ret < 0)
+			return ret;
+	}
+
+	ret = bus_i3c_init(bus);
+	if (ret < 0)
+		return ret;
+
+	dev_dbg(bus, "i3c : controller bus %d at 0x%lx\n", dev_seq(bus),
+		i3c_bus->base);
+
+	return 0;
+}
+
+static int imx_i3c_bind(struct udevice *dev)
+{
+	dev_dbg(dev, "imx_i3c_bind, %s, seq %d\n", dev->name, dev_seq(dev));
+
+	return board_imx_i3c_bind(dev);
+}
+
+static const struct dm_i2c_ops imx_i3c_ops = {
+	.xfer		= imx_i3c_xfer,
+	.probe_chip	= imx_i3c_probe_chip,
+	.set_bus_speed	= imx_i3c_set_bus_speed,
+};
+
+static const struct udevice_id imx_i3c_ids[] = {
+	{ .compatible = "fsl,imx8ulp-i3c", },
+	{}
+};
+
+U_BOOT_DRIVER(imx_i3c) = {
+	.name = "imx_i3c",
+	.id = UCLASS_I2C,
+	.of_match = imx_i3c_ids,
+	.bind = imx_i3c_bind,
+	.probe = imx_i3c_probe,
+	.priv_auto = sizeof(struct imx_i3c_bus),
+	.ops = &imx_i3c_ops,
+};
diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c
index 92c500327b4..9a652445aaa 100644
--- a/drivers/i2c/imx_lpi2c.c
+++ b/drivers/i2c/imx_lpi2c.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2016 Freescale Semiconductors, Inc.
+ * Copyright 2019 NXP
  */
 
 #include <common.h>
@@ -282,7 +283,7 @@ static int bus_i2c_set_bus_speed(struct udevice *bus, int speed)
 	bool mode;
 	int i;
 
-	if (IS_ENABLED(CONFIG_CLK)) {
+	if (CONFIG_IS_ENABLED(CLK)) {
 		clock_rate = clk_get_rate(&i2c_bus->per_clk);
 		if (clock_rate <= 0) {
 			dev_err(bus, "Failed to get i2c clk: %d\n", clock_rate);
@@ -462,7 +463,7 @@ static int imx_lpi2c_probe(struct udevice *bus)
 		return ret;
 	}
 
-	if (IS_ENABLED(CONFIG_CLK)) {
+	if (CONFIG_IS_ENABLED(CLK)) {
 		ret = clk_get_by_name(bus, "per", &i2c_bus->per_clk);
 		if (ret) {
 			dev_err(bus, "Failed to get per clk\n");
@@ -502,6 +503,18 @@ static int imx_lpi2c_probe(struct udevice *bus)
 	return 0;
 }
 
+int __weak board_imx_lpi2c_bind(struct udevice *dev)
+{
+	return 0;
+}
+
+static int imx_lpi2c_bind(struct udevice *dev)
+{
+	debug("imx_lpi2c_bind, %s, seq %d\n", dev->name, dev_seq(dev));
+
+	return board_imx_lpi2c_bind(dev);
+}
+
 static const struct dm_i2c_ops imx_lpi2c_ops = {
 	.xfer		= imx_lpi2c_xfer,
 	.probe_chip	= imx_lpi2c_probe_chip,
@@ -518,6 +531,7 @@ U_BOOT_DRIVER(imx_lpi2c) = {
 	.name = "imx_lpi2c",
 	.id = UCLASS_I2C,
 	.of_match = imx_lpi2c_ids,
+	.bind = imx_lpi2c_bind,
 	.probe = imx_lpi2c_probe,
 	.priv_auto	= sizeof(struct imx_lpi2c_bus),
 	.ops = &imx_lpi2c_ops,
diff --git a/drivers/i2c/imx_virt_i2c.c b/drivers/i2c/imx_virt_i2c.c
new file mode 100644
index 00000000000..5e0fc78d510
--- /dev/null
+++ b/drivers/i2c/imx_virt_i2c.c
@@ -0,0 +1,309 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <asm/mach-imx/imx_vservice.h>
+
+#define MAX_SRTM_I2C_BUF_SIZE 16
+#define SRTM_I2C_CATEGORY 0x09
+#define SRTM_VERSION 0x0001
+#define SRTM_TYPE_REQ 0x0
+#define SRTM_TYPE_RESP 0x1
+#define SRTM_CMD_READ 0x0
+#define SRTM_CMD_WRITE 0x1
+
+#define I2C_M_SELECT_MUX_BUS	0x010000
+#define I2C_M_SRTM_STOP       0x0200
+
+struct imx_virt_i2c_bus {
+	int index;
+	ulong base;
+	struct imx_vservice_channel *vservice;
+};
+
+struct imx_srtm_i2c_msg {
+	u8 categary;
+	u8 version[2];
+	u8 type;
+	u8 command;
+	u8 priority;
+	u8 reserved[4];
+
+	u8 i2c_bus;
+	u8 return_val;
+	u16 slave_addr;
+	u16 flag;
+	u16 data_length;
+	u8 data_buf[MAX_SRTM_I2C_BUF_SIZE];
+};
+
+static void imx_virt_i2c_msg_dump(struct imx_srtm_i2c_msg *msg)
+{
+	u32 i = 0;
+	u32 size = sizeof(struct imx_srtm_i2c_msg);
+	u8 *buf = (u8 *)msg;
+
+	for (; i < size; i++) {
+		debug("%02x ", buf[i]);
+		if (i % 16 == 15)
+			debug("\n");
+	}
+}
+
+static int imx_virt_i2c_read(struct udevice *bus, u32 chip, u8 *buf, int len, uint flag)
+{
+	struct imx_srtm_i2c_msg *msg;
+	u32 size;
+	int ret = 0;
+	struct imx_virt_i2c_bus *i2c_bus = dev_get_priv(bus);
+
+	debug("imx_virt_i2c_read, bus %d\n", i2c_bus->index);
+
+	if (len > MAX_SRTM_I2C_BUF_SIZE) {
+		printf("virt_i2c_read exceed the buf length, len=%d\n", len);
+		return -EINVAL;
+	}
+
+	size = sizeof(struct imx_srtm_i2c_msg);
+	msg = imx_vservice_get_buffer(i2c_bus->vservice, size);
+	if (msg == NULL)
+		return -ENOMEM;
+
+	/* Fill buf with SRTM i2c format */
+	msg->categary = SRTM_I2C_CATEGORY;
+	msg->version[0] = SRTM_VERSION & 0xff;
+	msg->version[1] = (SRTM_VERSION >> 8) & 0xff;
+	msg->type = SRTM_TYPE_REQ;
+	msg->command = SRTM_CMD_READ;
+	msg->priority = 1;
+
+	msg->i2c_bus = i2c_bus->index;
+	msg->return_val = 0;
+	msg->slave_addr = (u16)chip;
+	msg->flag = (u16)flag;
+	msg->data_length = len;
+
+	imx_virt_i2c_msg_dump(msg);
+
+	/* Send request and get return data */
+	ret = imx_vservice_blocking_request(i2c_bus->vservice, (u8 *)msg, &size);
+	if (ret) {
+		printf("Vservice request is failed, ret %d\n", ret);
+		return ret;
+	}
+
+	if (msg->type != SRTM_TYPE_RESP || msg->categary != SRTM_I2C_CATEGORY
+		|| msg->command !=SRTM_CMD_READ) {
+		printf("Error read response message\n");
+		return -EIO;
+	}
+
+	if (msg->return_val != 0)
+		return msg->return_val;
+
+	if (len != 0)
+		memcpy(buf, msg->data_buf, msg->data_length);
+
+	return ret;
+}
+
+static int imx_virt_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len, uint flag)
+{
+	struct imx_srtm_i2c_msg *msg;
+	u32 size;
+	int ret = 0;
+	struct imx_virt_i2c_bus *i2c_bus = dev_get_priv(bus);
+
+	debug("imx_virt_i2c_write, bus %d\n", i2c_bus->index);
+
+	if (len > MAX_SRTM_I2C_BUF_SIZE) {
+		printf("virt_i2c_read exceed the buf length, len=%d\n", len);
+		return -EINVAL;
+	}
+
+	size = sizeof(struct imx_srtm_i2c_msg);
+	msg = imx_vservice_get_buffer(i2c_bus->vservice, size);
+	if (msg == NULL)
+		return -ENOMEM;
+
+	/* Fill buf with SRTM i2c format */
+	msg->categary = SRTM_I2C_CATEGORY;
+	msg->version[0] = SRTM_VERSION & 0xff;
+	msg->version[1] = (SRTM_VERSION >> 8) & 0xff;
+	msg->type = SRTM_TYPE_REQ;
+	msg->command = SRTM_CMD_WRITE;
+	msg->priority = 1;
+
+	msg->i2c_bus = i2c_bus->index;
+	msg->return_val = 0;
+	msg->slave_addr = (u16)chip;
+	msg->flag = (u16)flag;
+	msg->data_length = len;
+
+	imx_virt_i2c_msg_dump(msg);
+
+	if (buf) /* probe chip does not have data buffer */
+		memcpy(msg->data_buf, buf, msg->data_length);
+
+	/* Send request and get return data */
+	ret = imx_vservice_blocking_request(i2c_bus->vservice,  (u8 *)msg, &size);
+	if (ret) {
+		printf("Vservice request is failed, ret %d\n", ret);
+		return ret;
+	}
+
+	if (msg->type != SRTM_TYPE_RESP || msg->categary != SRTM_I2C_CATEGORY
+		|| msg->command !=SRTM_CMD_WRITE) {
+		printf("Error write response message\n");
+		return -EIO;
+	}
+
+	if (msg->return_val != 0) {
+		debug("Peer process message, ret %d\n", msg->return_val);
+		return -EACCES;
+	}
+
+	debug("imx_vservice_blocking_request get size = %d\n", size);
+
+	return ret;
+
+}
+
+static int imx_virt_i2c_probe_chip(struct udevice *bus, u32 chip,
+				u32 chip_flags)
+{
+	debug("imx_virt_i2c_probe_chip\n");
+
+	return imx_virt_i2c_write(bus, chip, NULL, 0, I2C_M_SRTM_STOP);
+}
+
+static int imx_virt_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+	int ret = 0;
+	uint flag = 0;
+
+	for (; nmsgs > 0; nmsgs--, msg++) {
+		debug("virt_i2c_xfer: chip=0x%x, len=0x%x, buf=0x%08x\n", msg->addr, msg->len, *msg->buf);
+
+		flag = msg->flags;
+		if (nmsgs == 1)
+			flag |= I2C_M_SRTM_STOP;
+
+		if (flag & I2C_M_RD)
+			ret = imx_virt_i2c_read(bus, msg->addr, msg->buf, msg->len, flag);
+		else {
+			ret = imx_virt_i2c_write(bus, msg->addr, msg->buf,
+					    msg->len, flag);
+			if (ret)
+				break;
+		}
+	}
+
+	if (ret)
+		printf("i2c_xfer: error %d\n", ret);
+
+	return ret;
+}
+
+static int imx_virt_i2c_probe(struct udevice *bus)
+{
+	struct imx_virt_i2c_bus *i2c_bus = dev_get_priv(bus);
+	fdt_addr_t addr;
+
+	addr = dev_read_addr(bus);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	i2c_bus->base = addr;
+	i2c_bus->index = dev_seq(bus);
+
+	debug("virt_i2c : controller bus %d at 0x%lx,  bus udev 0x%lx\n",
+	      dev_seq(bus), i2c_bus->base, (ulong)bus);
+
+	i2c_bus->vservice = imx_vservice_setup(bus);
+	if (i2c_bus->vservice == NULL) {
+		printf("virt_i2c: Faild to setup vservice\n");
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static int imx_virt_i2c_set_flags(struct udevice *child_dev, uint flags)
+{
+#ifdef CONFIG_I2C_MUX_IMX_VIRT
+	if (child_dev->uclass->uc_drv->id == UCLASS_I2C_MUX) {
+		struct udevice *bus = child_dev->parent;
+		struct imx_virt_i2c_bus *i2c_bus = dev_get_priv(bus);
+
+		if (flags == 0) {
+			i2c_bus->index = dev_seq(bus);
+		} else if (flags & I2C_M_SELECT_MUX_BUS) {
+			i2c_bus->index = (flags >> 24) & 0xff;
+		}
+
+		debug("virt_i2c_set_flags bus %d\n", i2c_bus->index);
+	}
+#endif
+	return 0;
+}
+
+int __weak board_imx_virt_i2c_bind(struct udevice *dev)
+{
+	return 0;
+}
+
+static int imx_virt_i2c_bind(struct udevice *dev)
+{
+	debug("imx_virt_i2c_bind, %s, seq %d\n", dev->name, dev_seq(dev));
+
+	return board_imx_virt_i2c_bind(dev);
+}
+
+static int imx_virt_i2c_child_post_bind(struct udevice *child_dev)
+{
+#ifdef CONFIG_I2C_MUX_IMX_VIRT
+	if (child_dev->uclass->uc_drv->id == UCLASS_I2C_MUX) {
+		if (!strcmp(child_dev->driver->name, "imx_virt_i2c_mux"))
+			return 0;
+		else
+			return -ENODEV;
+	}
+#endif
+
+	return 0;
+}
+
+static const struct dm_i2c_ops imx_virt_i2c_ops = {
+	.xfer		= imx_virt_i2c_xfer,
+	.probe_chip	= imx_virt_i2c_probe_chip,
+	.set_flags = imx_virt_i2c_set_flags,
+};
+
+static const struct udevice_id imx_virt_i2c_ids[] = {
+	{ .compatible = "fsl,imx-virt-i2c", },
+	{}
+};
+
+U_BOOT_DRIVER(imx_virt_i2c) = {
+	.name = "imx_virt_i2c",
+	.id = UCLASS_I2C,
+	.of_match = imx_virt_i2c_ids,
+	.bind = imx_virt_i2c_bind,
+	.probe = imx_virt_i2c_probe,
+	.child_post_bind = imx_virt_i2c_child_post_bind,
+	.priv_auto = sizeof(struct imx_virt_i2c_bus),
+	.ops = &imx_virt_i2c_ops,
+	.flags	= DM_FLAG_DEFAULT_PD_CTRL_OFF | DM_FLAG_IGNORE_DEFAULT_CLKS,
+};
diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig
index 39683fc43b4..be8eed17b82 100644
--- a/drivers/i2c/muxes/Kconfig
+++ b/drivers/i2c/muxes/Kconfig
@@ -36,6 +36,12 @@ config I2C_MUX_PCA954x
 	  device. Supported chips are PCA9543, PCA9544, PCA9546, PCA9547,
 	  PCA9548 and PCA9646.
 
+config I2C_MUX_IMX_VIRT
+	bool "i.MX Virtual I2C Mux/switches"
+	depends on I2C_MUX && SYS_I2C_IMX_VIRT_I2C
+	help
+	  If you say yes here you get support for the i.MX Virtual I2C mux
+
 config I2C_MUX_GPIO
         tristate "GPIO-based I2C multiplexer"
 	depends on I2C_MUX && DM_GPIO
diff --git a/drivers/i2c/muxes/Makefile b/drivers/i2c/muxes/Makefile
index b690821199f..795c292cd28 100644
--- a/drivers/i2c/muxes/Makefile
+++ b/drivers/i2c/muxes/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_I2C_ARB_GPIO_CHALLENGE) += i2c-arb-gpio-challenge.o
 obj-$(CONFIG_I2C_MUX) += i2c-mux-uclass.o
 obj-$(CONFIG_I2C_MUX_PCA954x) += pca954x.o
 obj-$(CONFIG_I2C_MUX_GPIO) += i2c-mux-gpio.o
+obj-$(CONFIG_I2C_MUX_IMX_VIRT) += imx_virt_i2c_mux.o
diff --git a/drivers/i2c/muxes/imx_virt_i2c_mux.c b/drivers/i2c/muxes/imx_virt_i2c_mux.c
new file mode 100644
index 00000000000..fb54550333e
--- /dev/null
+++ b/drivers/i2c/muxes/imx_virt_i2c_mux.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <i2c.h>
+
+#include <asm-generic/gpio.h>
+
+#define I2C_M_SELECT_MUX_BUS	0x010000
+
+struct imx_virt_i2c_mux_priv {
+	u32 addr; /* I2C mux address */
+	u32 i2c_bus_alias_off;
+};
+
+static int imx_virt_i2c_mux_deselect(struct udevice *mux, struct udevice *bus,
+			    uint channel)
+{
+	return i2c_set_chip_flags(mux, 0);
+}
+
+static int imx_virt_i2c_mux_select(struct udevice *mux, struct udevice *bus,
+			  uint channel)
+{
+	struct imx_virt_i2c_mux_priv *priv = dev_get_priv(mux);
+	uint flags = I2C_M_SELECT_MUX_BUS;
+
+	flags |= ((priv->i2c_bus_alias_off + channel) << 24);
+
+	return i2c_set_chip_flags(mux, flags);
+}
+
+static const struct i2c_mux_ops imx_virt_i2c_mux_ops = {
+	.select = imx_virt_i2c_mux_select,
+	.deselect = imx_virt_i2c_mux_deselect,
+};
+
+static const struct udevice_id imx_virt_i2c_mux_ids[] = {
+	{ .compatible = "fsl,imx-virt-i2c-mux", },
+	{ }
+};
+
+static int imx_virt_i2c_mux_probe(struct udevice *dev)
+{
+	struct imx_virt_i2c_mux_priv *priv = dev_get_priv(dev);
+
+	priv->addr = dev_read_u32_default(dev, "reg", 0);
+	if (!priv->addr) {
+		debug("MUX not found\n");
+		return -ENODEV;
+	}
+
+	priv->i2c_bus_alias_off = dev_read_u32_default(dev, "virtual-bus-seq", 0);
+
+	debug("Device %s at 0x%x with i2c_bus_alias_off %d\n",
+	      dev->name, priv->addr, priv->i2c_bus_alias_off);
+	return 0;
+}
+
+U_BOOT_DRIVER(imx_virt_i2c_mux) = {
+	.name = "imx_virt_i2c_mux",
+	.id = UCLASS_I2C_MUX,
+	.of_match = imx_virt_i2c_mux_ids,
+	.probe = imx_virt_i2c_mux_probe,
+	.ops = &imx_virt_i2c_mux_ops,
+	.priv_auto = sizeof(struct imx_virt_i2c_mux_priv),
+};
diff --git a/drivers/input/Makefile b/drivers/input/Makefile
index b1133f772f2..fd7a1f99bf4 100644
--- a/drivers/input/Makefile
+++ b/drivers/input/Makefile
@@ -15,4 +15,5 @@ obj-$(CONFIG_I8042_KEYB) += i8042.o
 obj-$(CONFIG_TEGRA_KEYBOARD) += input.o tegra-kbc.o
 obj-$(CONFIG_TWL4030_INPUT) += twl4030.o
 obj-$(CONFIG_TWL6030_INPUT) += twl6030.o
+obj-$(CONFIG_MXC_KPD) += mxc_keyb.o
 endif
diff --git a/drivers/input/mxc_keyb.c b/drivers/input/mxc_keyb.c
new file mode 100644
index 00000000000..09b8ec12bee
--- /dev/null
+++ b/drivers/input/mxc_keyb.c
@@ -0,0 +1,592 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2009-2014 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ */
+
+/*!
+ * @file mxc_keyb.c
+ *
+ * @brief Driver for the Freescale Semiconductor MXC keypad port.
+ *
+ * The keypad driver is designed as a standard Input driver which interacts
+ * with low level keypad port hardware. Upon opening, the Keypad driver
+ * initializes the keypad port. When the keypad interrupt happens the driver
+ * calles keypad polling timer and scans the keypad matrix for key
+ * press/release. If all key press/release happened it comes out of timer and
+ * waits for key press interrupt. The scancode for key press and release events
+ * are passed to Input subsytem.
+ *
+ * @ingroup keypad
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <asm/mach-imx/mxc_key_defs.h>
+#include <malloc.h>
+
+/*
+ *  * Module header file
+ *   */
+#include <mxc_keyb.h>
+
+/*!
+ * Comment KPP_DEBUG to disable debug messages
+ */
+
+#undef	KPP_DEBUG
+
+#ifdef	KPP_DEBUG
+#define	KPP_PRINTF(fmt, args...)	printf(fmt , ##args)
+
+static void mxc_kpp_dump_regs()
+{
+	unsigned short t1, t2, t3;
+
+	t1 = __raw_readw(KPCR);
+	t2 = __raw_readw(KPSR);
+	t3 = __raw_readw(KDDR);
+	/*
+	KPP_PRINTF("KPCR=0x%04x, KPSR=0x%04x, KDDR=0x%04x\n",
+		t1, t2, t3);
+		*/
+}
+#else
+#define KPP_PRINTF(fmt, args...)
+#endif
+
+static u16 mxc_key_mapping[] = CONFIG_MXC_KEYMAPPING;
+
+/*!
+ * This structure holds the keypad private data structure.
+ */
+static struct keypad_priv kpp_dev;
+
+/*! Indicates if the key pad device is enabled. */
+
+/*! This static variable indicates whether a key event is pressed/released. */
+static unsigned short KPress;
+
+/*! cur_rcmap and prev_rcmap array is used to detect key press and release. */
+static unsigned short *cur_rcmap;	/* max 64 bits (8x8 matrix) */
+static unsigned short *prev_rcmap;
+
+/*!
+ * Debounce polling period(10ms) in system ticks.
+ */
+/*static unsigned short KScanRate = (10 * CONFIG_SYS_HZ) / 1000;*/
+
+/*!
+ * These arrays are used to store press and release scancodes.
+ */
+static short **press_scancode;
+static short **release_scancode;
+
+static const unsigned short *mxckpd_keycodes;
+static unsigned short mxckpd_keycodes_size;
+
+/*!
+ * This function is called to scan the keypad matrix to find out the key press
+ * and key release events. Make scancode and break scancode are generated for
+ * key press and key release events.
+ *
+ * The following scanning sequence are done for
+ * keypad row and column scanning,
+ * -# Write 1's to KPDR[15:8], setting column data to 1's
+ * -# Configure columns as totem pole outputs(for quick discharging of keypad
+ * capacitance)
+ * -# Configure columns as open-drain
+ * -# Write a single column to 0, others to 1.
+ * -# Sample row inputs and save data. Multiple key presses can be detected on
+ * a single column.
+ * -# Repeat steps the above steps for remaining columns.
+ * -# Return all columns to 0 in preparation for standby mode.
+ * -# Clear KPKD and KPKR status bit(s) by writing to a 1,
+ *    Set the KPKR synchronizer chain by writing "1" to KRSS register,
+ *    Clear the KPKD synchronizer chain by writing "1" to KDSC register
+ *
+ * @result    Number of key pressed/released.
+ */
+static int mxc_kpp_scan_matrix(void)
+{
+	unsigned short reg_val;
+	int col, row;
+	short scancode = 0;
+	int keycnt = 0;		/* How many keys are still pressed */
+
+	/*
+	 * wmb() linux kernel function which guarantees orderings in write
+	 * operations
+	 */
+	/* wmb(); */
+
+	/* save cur keypad matrix to prev */
+	memcpy(prev_rcmap, cur_rcmap, kpp_dev.kpp_rows * sizeof(prev_rcmap[0]));
+	memset(cur_rcmap, 0, kpp_dev.kpp_rows * sizeof(cur_rcmap[0]));
+
+	/*1. Disable both (depress and release) keypad interrupts.*/
+
+	/* KDIE has been disabled in mxc_kpp_getc before calling scan matrix.
+	  * KRIE is always disabled in this driver.
+	  */
+
+	for (col = 0; col < kpp_dev.kpp_cols; col++) {	/* Col */
+		/* 2. Write 1.s to KPDR[15:8] setting column data to 1.s */
+		reg_val = __raw_readw(KPDR);
+		reg_val |= 0xff00;
+		__raw_writew(reg_val, KPDR);
+
+		/*
+		 * 3. Configure columns as totem pole outputs(for quick
+		 * discharging of keypad capacitance)
+		 */
+		reg_val = __raw_readw(KPCR);
+		reg_val &= 0x00ff;
+		__raw_writew(reg_val, KPCR);
+
+		udelay(2);
+
+#ifdef KPP_DEBUG
+		mxc_kpp_dump_regs();
+#endif
+
+		/*
+		 * 4. Configure columns as open-drain
+		 */
+		reg_val = __raw_readw(KPCR);
+		reg_val |= ((1 << kpp_dev.kpp_cols) - 1) << 8;
+		__raw_writew(reg_val, KPCR);
+
+		/*
+		 * 5. Write a single column to 0, others to 1.
+		 * 6. Sample row inputs and save data. Multiple key presses
+		 * can be detected on a single column.
+		 * 7. Repeat steps 2 - 6 for remaining columns.
+		 */
+
+		/* Col bit starts at 8th bit in KPDR */
+		reg_val = __raw_readw(KPDR);
+		reg_val &= ~(1 << (8 + col));
+		__raw_writew(reg_val, KPDR);
+
+		/* Delay added to avoid propagating the 0 from column to row
+		 * when scanning. */
+
+		udelay(5);
+
+#ifdef KPP_DEBUG
+		mxc_kpp_dump_regs();
+#endif
+
+		/* Read row input */
+		reg_val = __raw_readw(KPDR);
+		for (row = 0; row < kpp_dev.kpp_rows; row++) {	/* sample row */
+			if (TEST_BIT(reg_val, row) == 0) {
+				cur_rcmap[row] = BITSET(cur_rcmap[row], col);
+				keycnt++;
+			}
+		}
+	}
+
+	/*
+	 * 8. Return all columns to 0 in preparation for standby mode.
+	 * 9. Clear KPKD and KPKR status bit(s) by writing to a .1.,
+	 * set the KPKR synchronizer chain by writing "1" to KRSS register,
+	 * clear the KPKD synchronizer chain by writing "1" to KDSC register
+	 */
+	reg_val = 0x00;
+	__raw_writew(reg_val, KPDR);
+	reg_val = __raw_readw(KPDR);
+	reg_val = __raw_readw(KPSR);
+	reg_val |= KBD_STAT_KPKD | KBD_STAT_KPKR | KBD_STAT_KRSS |
+	    KBD_STAT_KDSC;
+	__raw_writew(reg_val, KPSR);
+
+#ifdef KPP_DEBUG
+	mxc_kpp_dump_regs();
+#endif
+
+	/* Check key press status change */
+
+	/*
+	 * prev_rcmap array will contain the previous status of the keypad
+	 * matrix.  cur_rcmap array will contains the present status of the
+	 * keypad matrix. If a bit is set in the array, that (row, col) bit is
+	 * pressed, else it is not pressed.
+	 *
+	 * XORing these two variables will give us the change in bit for
+	 * particular row and column.  If a bit is set in XOR output, then that
+	 * (row, col) has a change of status from the previous state.  From
+	 * the diff variable the key press and key release of row and column
+	 * are found out.
+	 *
+	 * If the key press is determined then scancode for key pressed
+	 * can be generated using the following statement:
+	 *    scancode = ((row * 8) + col);
+	 *
+	 * If the key release is determined then scancode for key release
+	 * can be generated using the following statement:
+	 *    scancode = ((row * 8) + col) + MXC_KEYRELEASE;
+	 */
+	for (row = 0; row < kpp_dev.kpp_rows; row++) {
+		unsigned char diff;
+
+		/*
+		 * Calculate the change in the keypad row status
+		 */
+		diff = prev_rcmap[row] ^ cur_rcmap[row];
+
+		for (col = 0; col < kpp_dev.kpp_cols; col++) {
+			if ((diff >> col) & 0x1) {
+				/* There is a status change on col */
+				if ((prev_rcmap[row] & BITSET(0, col)) == 0) {
+					/*
+					 * Previous state is 0, so now
+					 * a key is pressed
+					 */
+					scancode =
+					    ((row * kpp_dev.kpp_cols) +
+					     col);
+					KPress = 1;
+					kpp_dev.iKeyState = KStateUp;
+
+					KPP_PRINTF("Press   (%d, %d) scan=%d "
+						 "Kpress=%d\n",
+						 row, col, scancode, KPress);
+					press_scancode[row][col] =
+					    (short)scancode;
+				} else {
+					/*
+					 * Previous state is not 0, so
+					 * now a key is released
+					 */
+					scancode =
+					    (row * kpp_dev.kpp_cols) +
+					    col + MXC_KEYRELEASE;
+					KPress = 0;
+					kpp_dev.iKeyState = KStateDown;
+
+					KPP_PRINTF
+					    ("Release (%d, %d) scan=%d Kpress=%d\n",
+					     row, col, scancode, KPress);
+					release_scancode[row][col] =
+					    (short)scancode;
+					keycnt++;
+				}
+			}
+		}
+	}
+
+	return keycnt;
+}
+
+static int mxc_kpp_reset(void)
+{
+	unsigned short reg_val;
+	int i;
+
+	/*
+	* Stop scanning and wait for interrupt.
+	* Enable press interrupt and disable release interrupt.
+	*/
+	__raw_writew(0x00FF, KPDR);
+	reg_val = __raw_readw(KPSR);
+	reg_val |= (KBD_STAT_KPKR | KBD_STAT_KPKD);
+	reg_val |= KBD_STAT_KRSS | KBD_STAT_KDSC;
+	__raw_writew(reg_val, KPSR);
+	reg_val |= KBD_STAT_KDIE;
+	reg_val &= ~KBD_STAT_KRIE;
+	__raw_writew(reg_val, KPSR);
+
+#ifdef KPP_DEBUG
+	mxc_kpp_dump_regs();
+#endif
+
+	/*
+	* No more keys pressed... make sure unwanted key codes are
+	* not given upstairs
+	*/
+	for (i = 0; i < kpp_dev.kpp_rows; i++) {
+		memset(press_scancode[i], -1,
+			sizeof(press_scancode[0][0]) * kpp_dev.kpp_cols);
+		memset(release_scancode[i], -1,
+			sizeof(release_scancode[0][0]) *
+			kpp_dev.kpp_cols);
+	}
+
+	return 0;
+}
+
+int mxc_kpp_getc(struct kpp_key_info **key_info)
+{
+	int col, row;
+	int key_cnt;
+	unsigned short reg_val;
+	short scancode = 0;
+	int index = 0;
+	struct kpp_key_info *keyi;
+
+	reg_val = __raw_readw(KPSR);
+
+	if (reg_val & KBD_STAT_KPKD) {
+		/*
+		* Disable key press(KDIE status bit) interrupt
+		*/
+		reg_val &= ~KBD_STAT_KDIE;
+		__raw_writew(reg_val, KPSR);
+
+#ifdef KPP_DEBUG
+		mxc_kpp_dump_regs();
+#endif
+
+		key_cnt = mxc_kpp_scan_matrix();
+	} else {
+		return 0;
+	}
+
+	if (key_cnt <= 0)
+		return 0;
+
+	*key_info = keyi =
+		(struct kpp_key_info *)malloc
+		(sizeof(struct kpp_key_info) * key_cnt);
+
+	/*
+	* This switch case statement is the
+	* implementation of state machine of debounc
+	* logic for key press/release.
+	* The explaination of state machine is as
+	* follows:
+	*
+	* KStateUp State:
+	* This is in intial state of the state machine
+	* this state it checks for any key presses.
+	* The key press can be checked using the
+	* variable KPress. If KPress is set, then key
+	* press is identified and switches the to
+	* KStateFirstDown state for key press to
+	* debounce.
+	*
+	* KStateFirstDown:
+	* After debounce delay(10ms), if the KPress is
+	* still set then pass scancode generated to
+	* input device and change the state to
+	* KStateDown, else key press debounce is not
+	* satisfied so change the state to KStateUp.
+	*
+	* KStateDown:
+	* In this state it checks for any key release.
+	* If KPress variable is cleared, then key
+	* release is indicated and so, switch the
+	* state to KStateFirstUp else to state
+	* KStateDown.
+	*
+	* KStateFirstUp:
+	* After debounce delay(10ms), if the KPress is
+	* still reset then pass the key release
+	* scancode to input device and change
+	* the state to KStateUp else key release is
+	* not satisfied so change the state to
+	* KStateDown.
+	*/
+
+	for (row = 0; row < kpp_dev.kpp_rows; row++) {
+		for (col = 0; col < kpp_dev.kpp_cols; col++) {
+			if ((press_scancode[row][col] != -1)) {
+				/* Still Down, so add scancode */
+				scancode =
+				    press_scancode[row][col];
+
+				keyi[index].val = mxckpd_keycodes[scancode];
+				keyi[index++].evt = KDepress;
+
+				KPP_PRINTF("KStateFirstDown: scan=%d val=%d\n",
+					scancode, mxckpd_keycodes[scancode]);
+				if (index >= key_cnt)
+					goto key_detect;
+
+				kpp_dev.iKeyState = KStateDown;
+				press_scancode[row][col] = -1;
+			}
+		}
+	}
+
+	for (row = 0; row < kpp_dev.kpp_rows; row++) {
+		for (col = 0; col < kpp_dev.kpp_cols; col++) {
+			if ((release_scancode[row][col] != -1)) {
+				scancode =
+				    release_scancode[row][col];
+				scancode =
+					scancode - MXC_KEYRELEASE;
+
+				keyi[index].val = mxckpd_keycodes[scancode];
+				keyi[index++].evt = KRelease;
+
+				KPP_PRINTF("KStateFirstUp: scan=%d val=%d\n",
+					scancode, mxckpd_keycodes[scancode]);
+				if (index >= key_cnt)
+					goto key_detect;
+
+				kpp_dev.iKeyState = KStateUp;
+				release_scancode[row][col] = -1;
+			}
+		}
+	}
+
+key_detect:
+	mxc_kpp_reset();
+	return key_cnt;
+}
+
+/*!
+ * This function is called to free the allocated memory for local arrays
+ */
+static void mxc_kpp_free_allocated(void)
+{
+	int i;
+
+	if (press_scancode) {
+		for (i = 0; i < kpp_dev.kpp_rows; i++) {
+			if (press_scancode[i])
+				free(press_scancode[i]);
+		}
+		free(press_scancode);
+	}
+
+	if (release_scancode) {
+		for (i = 0; i < kpp_dev.kpp_rows; i++) {
+			if (release_scancode[i])
+				free(release_scancode[i]);
+		}
+		free(release_scancode);
+	}
+
+	if (cur_rcmap)
+		free(cur_rcmap);
+
+	if (prev_rcmap)
+		free(prev_rcmap);
+}
+
+/*!
+ * This function is called during the driver binding process.
+ *
+ * @param   pdev  the device structure used to store device specific
+ *                information that is used by the suspend, resume and remove
+ *                functions.
+ *
+ * @return  The function returns 0 on successful registration. Otherwise returns
+ *          specific error code.
+ */
+int mxc_kpp_init(void)
+{
+	int i;
+	int retval;
+	unsigned int reg_val;
+
+	kpp_dev.kpp_cols = CONFIG_MXC_KPD_COLMAX;
+	kpp_dev.kpp_rows = CONFIG_MXC_KPD_ROWMAX;
+
+	/* clock and IOMUX configuration for keypad */
+	setup_mxc_kpd();
+
+	/* Configure keypad */
+
+	/* Enable number of rows in keypad (KPCR[7:0])
+	 * Configure keypad columns as open-drain (KPCR[15:8])
+	 *
+	 * Configure the rows/cols in KPP
+	 * LSB nibble in KPP is for 8 rows
+	 * MSB nibble in KPP is for 8 cols
+	 */
+	reg_val = __raw_readw(KPCR);
+	reg_val |= (1  << kpp_dev.kpp_rows) - 1;	/* LSB */
+	reg_val |= ((1 << kpp_dev.kpp_cols) - 1) << 8;	/* MSB */
+	__raw_writew(reg_val, KPCR);
+
+	/* Write 0's to KPDR[15:8] */
+	reg_val = __raw_readw(KPDR);
+	reg_val &= 0x00ff;
+	__raw_writew(reg_val, KPDR);
+
+	/* Configure columns as output,
+	 * rows as input (KDDR[15:0]) */
+	reg_val = __raw_readw(KDDR);
+	reg_val |= 0xff00;
+	reg_val &= 0xff00;
+	__raw_writew(reg_val, KDDR);
+
+	/* Clear the KPKD Status Flag
+	 * and Synchronizer chain. */
+	reg_val = __raw_readw(KPSR);
+	reg_val &= ~(KBD_STAT_KPKR | KBD_STAT_KPKD);
+	reg_val |= KBD_STAT_KPKD;
+	reg_val |= KBD_STAT_KRSS | KBD_STAT_KDSC;
+	__raw_writew(reg_val, KPSR);
+	/* Set the KDIE control bit, and clear the KRIE
+	 * control bit (avoid false release events). */
+	reg_val |= KBD_STAT_KDIE;
+	reg_val &= ~KBD_STAT_KRIE;
+	__raw_writew(reg_val, KPSR);
+
+#ifdef KPP_DEBUG
+	mxc_kpp_dump_regs();
+#endif
+
+	mxckpd_keycodes = mxc_key_mapping;
+	mxckpd_keycodes_size = kpp_dev.kpp_cols * kpp_dev.kpp_rows;
+
+	if ((mxckpd_keycodes == (void *)0)
+	    || (mxckpd_keycodes_size == 0)) {
+		retval = -ENODEV;
+		goto err;
+	}
+
+	/* allocate required memory */
+	press_scancode   = (short **)malloc(kpp_dev.kpp_rows * sizeof(press_scancode[0]));
+	release_scancode = (short **)malloc(kpp_dev.kpp_rows * sizeof(release_scancode[0]));
+
+	if (!press_scancode || !release_scancode) {
+		retval = -ENOMEM;
+		goto err;
+	}
+
+	for (i = 0; i < kpp_dev.kpp_rows; i++) {
+		press_scancode[i] = (short *)malloc(kpp_dev.kpp_cols
+					    * sizeof(press_scancode[0][0]));
+		release_scancode[i] =
+		    (short *)malloc(kpp_dev.kpp_cols * sizeof(release_scancode[0][0]));
+
+		if (!press_scancode[i] || !release_scancode[i]) {
+			retval = -ENOMEM;
+			goto err;
+		}
+	}
+
+	cur_rcmap =
+	    (unsigned short *)malloc(kpp_dev.kpp_rows * sizeof(cur_rcmap[0]));
+	prev_rcmap =
+	    (unsigned short *)malloc(kpp_dev.kpp_rows * sizeof(prev_rcmap[0]));
+
+	if (!cur_rcmap || !prev_rcmap) {
+		retval = -ENOMEM;
+		goto err;
+	}
+
+	for (i = 0; i < kpp_dev.kpp_rows; i++) {
+		memset(press_scancode[i], -1,
+		       sizeof(press_scancode[0][0]) * kpp_dev.kpp_cols);
+		memset(release_scancode[i], -1,
+		       sizeof(release_scancode[0][0]) * kpp_dev.kpp_cols);
+	}
+	memset(cur_rcmap, 0, kpp_dev.kpp_rows * sizeof(cur_rcmap[0]));
+	memset(prev_rcmap, 0, kpp_dev.kpp_rows * sizeof(prev_rcmap[0]));
+
+	return 0;
+
+err:
+	mxc_kpp_free_allocated();
+	return retval;
+}
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 73db2af0b81..a23b9033704 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -58,4 +58,12 @@ config ZYNQMP_IPI
 	help
 	  This enables support for the Xilinx ZynqMP Inter Processor Interrupt
 	  communication controller.
+
+config IMX_MU
+    bool "Enable i.MX MU support"
+    depends on DM_MAILBOX
+    help
+      Enable support for i.MX Messaging Unit for communication with other
+      processors on the SoC
+
 endmenu
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 59e8d0de93c..85055436f60 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
 obj-$(CONFIG_TEGRA_HSP) += tegra-hsp.o
 obj-$(CONFIG_K3_SEC_PROXY) += k3-sec-proxy.o
 obj-$(CONFIG_ZYNQMP_IPI) += zynqmp-ipi.o
+obj-$(CONFIG_IMX_MU) += imx-mu.o
diff --git a/drivers/mailbox/imx-mu.c b/drivers/mailbox/imx-mu.c
new file mode 100644
index 00000000000..d08f9d1500d
--- /dev/null
+++ b/drivers/mailbox/imx-mu.c
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <mailbox-uclass.h>
+
+#define NUM_MU_CHANNELS     4
+#define NUM_MU_FLAGS        4
+#define NUM_MU_GIP          4
+
+#define mu_rr(x)            (0x10 + (x * 0x4))
+#define mu_tr(x)            (x * 0x4)
+#define MU_SR_OFFSET        0x20
+#define MU_CR_OFFSET        0x24
+#define CHAN_TE_MASK(x)     (0x00100000 << (x))
+#define CHAN_RF_MASK(x)     (0x01000000 << (x))
+#define MU_CR_INT_MSK       0xFFF00000
+#define MU_FLGS_MSK         0x00000007
+#define MU_GIP_MSK          0xF0000000
+
+
+
+/* This driver only exposes the status bits to keep with the
+ * polling methodology of u-boot.
+ */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct imx_mu_mbox {
+	fdt_addr_t base;
+
+	/* use pointers to channel as a way to reserve channels */
+	void *channels[NUM_MU_CHANNELS];
+	bool flags[NUM_MU_FLAGS];
+
+	/* TODO add support for the reading/setting of flags to
+	 * B side of MU
+	 */
+};
+
+
+/* check that the channel is open or owned by caller */
+static int mu_check_channel(struct mbox_chan *chan)
+{
+	struct imx_mu_mbox *mailbox = dev_get_priv(chan->dev);
+
+	/* use id as number of channel within mbox only */
+	if ((chan->id < 0) || (chan->id >= NUM_MU_CHANNELS)) {
+		debug("nxp mu id out of range: %lu\n", chan->id);
+		return -EINVAL;
+	}
+	if (mailbox->channels[chan->id] != NULL) {
+		/* if reserved check that caller owns */
+		if (mailbox->channels[chan->id] == chan)
+			return 1; /* caller owns the channel */
+
+		return -EACCES;
+	}
+	return 0;/* channel empty */
+}
+
+static int mu_chan_request(struct mbox_chan *chan)
+{
+	struct imx_mu_mbox *mailbox = dev_get_priv(chan->dev);
+
+	debug("%s(chan=%p)\n", __func__, chan);
+
+	int status = mu_check_channel(chan);
+	if (status < 0) {
+		debug("channel not available :%d\n", status);
+		return -EPERM;
+	}
+	mailbox->channels[chan->id] = chan;
+
+	return 0;
+}
+/* currently not dynamically allocated
+ * only change pointer back to NULL */
+static int mu_chan_free(struct mbox_chan *chan)
+{
+	struct imx_mu_mbox *mailbox = dev_get_priv(chan->dev);
+	int status = mu_check_channel(chan);
+
+	debug("%s(chan=%p)\n", __func__, chan);
+	if (status <= 0) { /* check that the channel is also not empty */
+		debug("mu_chan_free() failed exit code: %d\n", status);
+		return status;
+	}
+	/*if you own channel and  channel is NOT empty */
+	mailbox->channels[chan->id] = NULL;
+
+	return 0;
+}
+
+static int mu_send(struct mbox_chan *chan, const void *data)
+{
+	struct imx_mu_mbox *mbox = dev_get_priv(chan->dev);
+	int status = mu_check_channel(chan);
+	uint32_t val = *((uint32_t *)data);
+
+	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+	if (status < 1) {
+		debug("mu_send() failed. mu_chan_status is :%d\n", status);
+		return -EPERM;
+	}
+
+	/*check if transmit register is empty */
+	if (!(readl(mbox->base+MU_SR_OFFSET) & CHAN_TE_MASK(chan->id)))
+		return -EBUSY;
+
+	/* send out on transmit register*/
+	writel(val, mbox->base + mu_tr(chan->id));
+	return 0;
+}
+
+static int mu_recv(struct mbox_chan *chan, void *data)
+{
+	struct imx_mu_mbox *mbox = dev_get_priv(chan->dev);
+	int status = mu_check_channel(chan);
+	uint32_t *buffer =  data;
+
+	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+	if (status < 1)
+		return -EPERM; /* return if channel isnt owned */
+
+	if (readl(mbox->base + MU_SR_OFFSET) & CHAN_RF_MASK(chan->id))
+		return -ENODATA;
+
+	*buffer = readl(mu_rr(chan->id));
+
+	return 0;
+}
+
+static int imx_mu_bind(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+static int imx_mu_probe(struct udevice *dev)
+{
+	struct imx_mu_mbox *mbox = dev_get_priv(dev);
+	uint32_t val;
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	/* get address from device tree */
+	mbox->base = dev_get_addr(dev);
+	if (mbox->base == FDT_ADDR_T_NONE)
+		return -ENODEV;
+
+	val = readl(mbox->base + MU_CR_OFFSET);
+	val = val & ~MU_CR_INT_MSK;/* disable all interrupts */
+	val = val & ~MU_FLGS_MSK; /* clear all flags */
+
+	writel(val, mbox->base + MU_CR_OFFSET);
+
+	val = readl(mbox->base + MU_SR_OFFSET);
+	val = val | MU_GIP_MSK;   /* clear any pending GIP */
+	writel(val, mbox->base + MU_SR_OFFSET);
+
+	return 0;
+}
+
+static const struct udevice_id imx_mu_ids[] = {
+	{ .compatible = "nxp,imx-mu" },
+	{ }
+};
+
+struct mbox_ops imx_mu_mbox_ops = {
+	.request = mu_chan_request,
+	.free = mu_chan_free,
+	.send = mu_send,
+	.recv = mu_recv,
+};
+
+U_BOOT_DRIVER(imx_mu) = {
+	.name = "imx-mu",
+	.id = UCLASS_MAILBOX,
+	.of_match = imx_mu_ids,
+	.bind = imx_mu_bind,
+	.probe = imx_mu_probe,
+	.priv_auto_alloc_size = sizeof(struct imx_mu_mbox),
+	.ops = &imx_mu_mbox_ops,
+};
diff --git a/drivers/mailbox/mailbox-uclass.c b/drivers/mailbox/mailbox-uclass.c
index 85ba8c5fd99..1a9c6918d89 100644
--- a/drivers/mailbox/mailbox-uclass.c
+++ b/drivers/mailbox/mailbox-uclass.c
@@ -115,13 +115,29 @@ int mbox_free(struct mbox_chan *chan)
 	return 0;
 }
 
-int mbox_send(struct mbox_chan *chan, const void *data)
+int mbox_send(struct mbox_chan *chan, const void *data, ulong timeout_us)
 {
 	struct mbox_ops *ops = mbox_dev_ops(chan->dev);
+	ulong start_time;
+	int ret;
 
 	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
 
-	return ops->send(chan, data);
+	start_time = timer_get_us();
+	/*
+	 * Account for partial us ticks, but if timeout_us is 0, ensure we
+	 * still don't wait at all.
+	 */
+	if (timeout_us)
+		timeout_us++;
+
+	for (;;) {
+		ret = ops->send(chan, data);
+		if (ret != -EBUSY)
+			return ret;
+		if ((timer_get_us() - start_time) >= timeout_us)
+			return -ETIMEDOUT;
+	}
 }
 
 int mbox_recv(struct mbox_chan *chan, void *data, ulong timeout_us)
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 7029bb7b5c5..c4ae6f7d803 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -242,6 +242,20 @@ config SPL_MXC_OCOTP
 	  Programmable memory pages, that are stored on some
 	  Freescale i.MX processors, in SPL.
 
+config IMX_M4_MU
+	bool "Enable i.MX MU Driver to communicate with Cortex M4"
+	depends on MISC
+	help
+	  If you say Y here to enable Message Unit driver to work with
+	  Cortex M4 core on AMP Freescale i.MX processors.
+
+config IMX_SENTINEL
+	bool "Enable i.MX Sentinel MU driver and API"
+	depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP)
+	help
+	  If you say Y here to enable Message Unit driver to work with
+	  Sentinel core on some NXP i.MX processors.
+
 config NUVOTON_NCT6102D
 	bool "Enable Nuvoton NCT6102D Super I/O driver"
 	help
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index f22eff601a1..29a1d6762f6 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
 obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
 obj-$(CONFIG_SANDBOX) += p2sb_sandbox.o p2sb_emul.o
 obj-$(CONFIG_SANDBOX) += swap_case.o
+obj-$(CONFIG_IMX_M4_MU) += imx_m4_mu.o
 endif
 
 ifdef CONFIG_$(SPL_)DM_I2C
@@ -46,7 +47,7 @@ obj-$(CONFIG_SANDBOX) += irq_sandbox.o irq_sandbox_test.o
 obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
 obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o
 obj-$(CONFIG_IMX8) += imx8/
-obj-$(CONFIG_IMX8ULP) += imx8ulp/
+obj-$(CONFIG_IMX_SENTINEL) += sentinel/
 obj-$(CONFIG_LED_STATUS) += status_led.o
 obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
 obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
diff --git a/drivers/misc/imx8/fuse.c b/drivers/misc/imx8/fuse.c
index 38111c52548..9de05914284 100644
--- a/drivers/misc/imx8/fuse.c
+++ b/drivers/misc/imx8/fuse.c
@@ -11,6 +11,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/global_data.h>
 #include <linux/arm-smccc.h>
+#include <env.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -20,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_IMX8QM
 #define FSL_ECC_WORD_START_2	 0x1A0
 #define FSL_ECC_WORD_END_2	 0x1FF
-#elif defined(CONFIG_IMX8QXP)
+#elif defined(CONFIG_IMX8QXP) || defined(CONFIG_IMX8DXL)
 #define FSL_ECC_WORD_START_2	 0x220
 #define FSL_ECC_WORD_END_2	 0x31F
 #endif
@@ -55,13 +56,14 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
 int fuse_prog(u32 bank, u32 word, u32 val)
 {
 	struct arm_smccc_res res;
+	int force_prog = 0;
 
 	if (bank != 0) {
 		printf("Invalid bank argument, ONLY bank 0 is supported\n");
 		return -EINVAL;
 	}
 
-	if (IS_ENABLED(CONFIG_IMX8QXP)) {
+	if (IS_ENABLED(CONFIG_IMX8QXP) || IS_ENABLED(CONFIG_IMX8DXL)) {
 		if (word >= FSL_QXP_FUSE_GAP_START &&
 		    word <= FSL_QXP_FUSE_GAP_END) {
 			printf("Invalid word argument for this SoC\n");
@@ -69,16 +71,19 @@ int fuse_prog(u32 bank, u32 word, u32 val)
 		}
 	}
 
-	if ((word >= FSL_ECC_WORD_START_1 && word <= FSL_ECC_WORD_END_1) ||
-	    (word >= FSL_ECC_WORD_START_2 && word <= FSL_ECC_WORD_END_2)) {
-		puts("Warning: Words in this index range have ECC protection\n"
-		     "and can only be programmed once per word. Individual bit\n"
-		     "operations will be rejected after the first one.\n"
-		     "\n\n Really program this word? <y/N>\n");
-
-		if (!confirm_yesno()) {
-			puts("Word programming aborted\n");
-			return -EPERM;
+	force_prog = env_get_yesno("force_prog_ecc");
+	if (force_prog != 1) {
+		if ((word >= FSL_ECC_WORD_START_1 && word <= FSL_ECC_WORD_END_1) ||
+		    (word >= FSL_ECC_WORD_START_2 && word <= FSL_ECC_WORD_END_2)) {
+			puts("Warning: Words in this index range have ECC protection\n"
+			     "and can only be programmed once per word. Individual bit\n"
+			     "operations will be rejected after the first one.\n"
+			     "\n\n Really program this word? <y/N>\n");
+
+			if (!confirm_yesno()) {
+				puts("Word programming aborted\n");
+				return -EPERM;
+			}
 		}
 	}
 
diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c
index 4ab5cb4bf13..f82392cf90f 100644
--- a/drivers/misc/imx8/scu.c
+++ b/drivers/misc/imx8/scu.c
@@ -57,7 +57,7 @@ static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg)
 	assert(reg_index < MU_TR_COUNT);
 
 	/* Wait TX register to be empty. */
-	ret = readl_poll_timeout(&base->sr, val, val & mask, 10000);
+	ret = readl_poll_timeout(&base->sr, val, val & mask, 1000000);
 	if (ret < 0) {
 		printf("%s timeout\n", __func__);
 		return -ETIMEDOUT;
@@ -213,18 +213,6 @@ static int imx8_scu_remove(struct udevice *dev)
 
 static int imx8_scu_bind(struct udevice *dev)
 {
-	int ret;
-	struct udevice *child;
-	ofnode node;
-
-	debug("%s(dev=%p)\n", __func__, dev);
-	ofnode_for_each_subnode(node, dev_ofnode(dev)) {
-		ret = lists_bind_fdt(dev, node, &child, NULL, true);
-		if (ret)
-			return ret;
-		debug("bind child dev %s\n", child->name);
-	}
-
 	return 0;
 }
 
diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c
index 27ecce710fc..1e8b801b1d8 100644
--- a/drivers/misc/imx8/scu_api.c
+++ b/drivers/misc/imx8/scu_api.c
@@ -481,6 +481,24 @@ int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp,
 	return 0;
 }
 
+void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status)
+{
+	struct sc_rpc_msg_s msg;
+	struct udevice *dev = gd->arch.scu_dev;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SIZE(&msg) = 1U;
+	RPC_SVC(&msg) = (u8)(SC_RPC_SVC_MISC);
+	RPC_FUNC(&msg) = (u8)(MISC_FUNC_GET_BUTTON_STATUS);
+
+	misc_call(dev, SC_FALSE, &msg, 1U, &msg, 1U);
+
+	if (status != NULL)
+	{
+		*status = (sc_bool_t)(!!(RPC_U8(&msg, 0U)));
+	}
+}
+
 /* RM */
 sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr)
 {
@@ -788,7 +806,7 @@ sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad)
 	RPC_VER(&msg) = SC_RPC_VERSION;
 	RPC_SVC(&msg) = (u8)SC_RPC_SVC_RM;
 	RPC_FUNC(&msg) = (u8)RM_FUNC_IS_PAD_OWNED;
-	RPC_U8(&msg, 0U) = (u8)pad;
+	RPC_U16(&msg, 0U) = (u16)pad;
 	RPC_SIZE(&msg) = 2U;
 
 	ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
@@ -851,6 +869,21 @@ int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
 	return ret;
 }
 
+void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type)
+{
+	struct udevice *dev = gd->arch.scu_dev;
+	struct sc_rpc_msg_s msg;
+	int size = sizeof(struct sc_rpc_msg_s);
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SVC(&msg) = (u8)(SC_RPC_SVC_PM);
+	RPC_FUNC(&msg) = (u8)(PM_FUNC_REBOOT);
+	RPC_U8(&msg, 0U) = (u8)(type);
+	RPC_SIZE(&msg) = 2U;
+
+	misc_call(dev, SC_TRUE, &msg, size, &msg, size);
+}
+
 int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
 				  sc_pm_power_mode_t *mode)
 {
@@ -877,6 +910,28 @@ int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
 	return ret;
 }
 
+int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window)
+{
+	struct udevice *dev = gd->arch.scu_dev;
+	struct sc_rpc_msg_s msg;
+	int size = sizeof(struct sc_rpc_msg_s);
+	int ret;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SIZE(&msg) = 2U;
+	RPC_SVC(&msg) = (u8)(SC_RPC_SVC_TIMER);
+	RPC_FUNC(&msg) = (u8)(TIMER_FUNC_SET_WDOG_WINDOW);
+
+	RPC_U32(&msg, 0U) = (u32)(window);
+
+	ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+	if (ret)
+		printf("%s: window:%u: res:%d\n",
+		       __func__, window, RPC_R8(&msg));
+
+	return ret;
+}
+
 int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
 			 sc_faddr_t addr)
 {
@@ -974,6 +1029,31 @@ void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit)
 		*commit = RPC_U32(&msg, 4U);
 }
 
+int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit)
+{
+	struct udevice *dev = gd->arch.scu_dev;
+	struct sc_rpc_msg_s msg;
+	int size = sizeof(struct sc_rpc_msg_s);
+	int ret;
+
+	RPC_VER(&msg) = SC_RPC_VERSION;
+	RPC_SIZE(&msg) = 1U;
+	RPC_SVC(&msg) = (u8)(SC_RPC_SVC_SECO);
+	RPC_FUNC(&msg) = (u8)(SECO_FUNC_V2X_BUILD_INFO);
+
+	ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size);
+	if (ret)
+		printf("%s: res:%d\n", __func__, RPC_R8(&msg));
+
+	if (version)
+		*version = RPC_U32(&msg, 0U);
+
+	if (commit)
+		*commit = RPC_U32(&msg, 4U);
+
+	return ret;
+}
+
 int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event)
 {
 	struct udevice *dev = gd->arch.scu_dev;
@@ -1163,8 +1243,7 @@ int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data)
 		printf("%s, id:0x%x, access:%x, res:%d\n",
 		       __func__, id, access, RPC_R8(&msg));
 
-	if (data)
-		*data = RPC_U32(&msg, 0U);
+	*data = RPC_U32(&msg, 0U);
 
 	return ret;
 }
diff --git a/drivers/misc/imx8ulp/s400_api.c b/drivers/misc/imx8ulp/s400_api.c
deleted file mode 100644
index d76a95febe7..00000000000
--- a/drivers/misc/imx8ulp/s400_api.c
+++ /dev/null
@@ -1,244 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2020 NXP
- *
- */
-
-#include <common.h>
-#include <hang.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <dm.h>
-#include <asm/arch/s400_api.h>
-#include <misc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response)
-{
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct imx8ulp_s400_msg);
-	struct imx8ulp_s400_msg msg;
-	int ret;
-
-	if (!dev) {
-		printf("s400 dev is not initialized\n");
-		return -ENODEV;
-	}
-
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
-	msg.size = 2;
-	msg.command = AHAB_RELEASE_RDC_REQ_CID;
-	if (xrdc)
-		msg.data[0] = (0x78 << 8) | core_id;
-	else
-		msg.data[0] = (0x74 << 8) | core_id;
-
-	ret = misc_call(dev, false, &msg, size, &msg, size);
-	if (ret)
-		printf("Error: %s: ret %d, core id %u, response 0x%x\n",
-		       __func__, ret, core_id, msg.data[0]);
-
-	if (response)
-		*response = msg.data[0];
-
-	return ret;
-}
-
-int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response)
-{
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct imx8ulp_s400_msg);
-	struct imx8ulp_s400_msg msg;
-	int ret;
-
-	if (!dev) {
-		printf("s400 dev is not initialized\n");
-		return -ENODEV;
-	}
-
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
-	msg.size = 3;
-	msg.command = AHAB_AUTH_OEM_CTNR_CID;
-	msg.data[0] = upper_32_bits(ctnr_addr);
-	msg.data[1] = lower_32_bits(ctnr_addr);
-
-	ret = misc_call(dev, false, &msg, size, &msg, size);
-	if (ret)
-		printf("Error: %s: ret %d, cntr_addr 0x%lx, response 0x%x\n",
-		       __func__, ret, ctnr_addr, msg.data[0]);
-
-	if (response)
-		*response = msg.data[0];
-
-	return ret;
-}
-
-int ahab_release_container(u32 *response)
-{
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct imx8ulp_s400_msg);
-	struct imx8ulp_s400_msg msg;
-	int ret;
-
-	if (!dev) {
-		printf("s400 dev is not initialized\n");
-		return -ENODEV;
-	}
-
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
-	msg.size = 1;
-	msg.command = AHAB_RELEASE_CTNR_CID;
-
-	ret = misc_call(dev, false, &msg, size, &msg, size);
-	if (ret)
-		printf("Error: %s: ret %d, response 0x%x\n",
-		       __func__, ret, msg.data[0]);
-
-	if (response)
-		*response = msg.data[0];
-
-	return ret;
-}
-
-int ahab_verify_image(u32 img_id, u32 *response)
-{
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct imx8ulp_s400_msg);
-	struct imx8ulp_s400_msg msg;
-	int ret;
-
-	if (!dev) {
-		printf("s400 dev is not initialized\n");
-		return -ENODEV;
-	}
-
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
-	msg.size = 2;
-	msg.command = AHAB_VERIFY_IMG_CID;
-	msg.data[0] = 1 << img_id;
-
-	ret = misc_call(dev, false, &msg, size, &msg, size);
-	if (ret)
-		printf("Error: %s: ret %d, img_id %u, response 0x%x\n",
-		       __func__, ret, img_id, msg.data[0]);
-
-	if (response)
-		*response = msg.data[0];
-
-	return ret;
-}
-
-int ahab_forward_lifecycle(u16 life_cycle, u32 *response)
-{
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct imx8ulp_s400_msg);
-	struct imx8ulp_s400_msg msg;
-	int ret;
-
-	if (!dev) {
-		printf("s400 dev is not initialized\n");
-		return -ENODEV;
-	}
-
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
-	msg.size = 2;
-	msg.command = AHAB_FWD_LIFECYCLE_UP_REQ_CID;
-	msg.data[0] = life_cycle;
-
-	ret = misc_call(dev, false, &msg, size, &msg, size);
-	if (ret)
-		printf("Error: %s: ret %d, life_cycle 0x%x, response 0x%x\n",
-		       __func__, ret, life_cycle, msg.data[0]);
-
-	if (response)
-		*response = msg.data[0];
-
-	return ret;
-}
-
-int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response)
-{
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct imx8ulp_s400_msg);
-	struct imx8ulp_s400_msg msg;
-	int ret;
-
-	if (!dev) {
-		printf("s400 dev is not initialized\n");
-		return -ENODEV;
-	}
-
-	if (!fuse_words) {
-		printf("Invalid parameters for fuse read\n");
-		return -EINVAL;
-	}
-
-	if ((fuse_id != 1 && fuse_num != 1) ||
-	    (fuse_id == 1 && fuse_num != 4)) {
-		printf("Invalid fuse number parameter\n");
-		return -EINVAL;
-	}
-
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
-	msg.size = 2;
-	msg.command = AHAB_READ_FUSE_REQ_CID;
-	msg.data[0] = fuse_id;
-
-	ret = misc_call(dev, false, &msg, size, &msg, size);
-	if (ret)
-		printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n",
-		       __func__, ret, fuse_id, msg.data[0]);
-
-	if (response)
-		*response = msg.data[0];
-
-	fuse_words[0] = msg.data[1];
-	if (fuse_id == 1) {
-		/* OTP_UNIQ_ID */
-		fuse_words[1] = msg.data[2];
-		fuse_words[2] = msg.data[3];
-		fuse_words[3] = msg.data[4];
-	}
-
-	return ret;
-}
-
-int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response)
-{
-	struct udevice *dev = gd->arch.s400_dev;
-	int size = sizeof(struct imx8ulp_s400_msg);
-	struct imx8ulp_s400_msg msg;
-	int ret;
-
-	if (!dev) {
-		printf("s400 dev is not initialized\n");
-		return -ENODEV;
-	}
-
-	msg.version = AHAB_VERSION;
-	msg.tag = AHAB_CMD_TAG;
-	msg.size = 3;
-	msg.command = AHAB_WRITE_FUSE_REQ_CID;
-	msg.data[0] = (32 << 16) | (fuse_id << 5);
-	if (lock)
-		msg.data[0] |= (1 << 31);
-
-	msg.data[1] = fuse_val;
-
-	ret = misc_call(dev, false, &msg, size, &msg, size);
-	if (ret)
-		printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n",
-		       __func__, ret, fuse_id, msg.data[0]);
-
-	if (response)
-		*response = msg.data[0];
-
-	return ret;
-}
diff --git a/drivers/misc/imx_m4_mu.c b/drivers/misc/imx_m4_mu.c
new file mode 100644
index 00000000000..4168d8cdffb
--- /dev/null
+++ b/drivers/misc/imx_m4_mu.c
@@ -0,0 +1,243 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ *
+ */
+
+#include <common.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/lists.h>
+#include <dm/root.h>
+#include <dm/device-internal.h>
+#include <asm/arch/sci/sci.h>
+#include <linux/iopoll.h>
+#include <misc.h>
+#include <imx_m4_mu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct mu_type {
+	u32 tr[4];
+	u32 rr[4];
+	u32 sr;
+	u32 cr;
+};
+
+struct imx_m4_mu {
+	struct mu_type *base;
+};
+
+#define MU_CR_GIE_MASK		0xF0000000u
+#define MU_CR_RIE_MASK		0xF000000u
+#define MU_CR_GIR_MASK		0xF0000u
+#define MU_CR_TIE_MASK		0xF00000u
+#define MU_CR_F_MASK		0x7u
+#define MU_SR_TE0_MASK		BIT(23)
+#define MU_SR_RF0_MASK		BIT(27)
+#define MU_TR_COUNT		4
+#define MU_RR_COUNT		4
+
+static inline void mu_hal_init(struct mu_type *base)
+{
+	/* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
+	clrbits_le32(&base->cr, MU_CR_GIE_MASK | MU_CR_RIE_MASK |
+		     MU_CR_TIE_MASK | MU_CR_GIR_MASK | MU_CR_F_MASK);
+}
+
+static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg)
+{
+	u32 mask = MU_SR_TE0_MASK >> reg_index;
+	u32 val;
+	int ret;
+
+	assert(reg_index < MU_TR_COUNT);
+
+	debug("sendmsg sr 0x%x\n", readl(&base->sr));
+
+	/* Wait TX register to be empty. */
+	ret = readl_poll_timeout(&base->sr, val, val & mask, 10000);
+	if (ret < 0) {
+		debug("%s timeout\n", __func__);
+		return -ETIMEDOUT;
+	}
+
+	debug("tr[%d] 0x%x\n",reg_index,  msg);
+
+	writel(msg, &base->tr[reg_index]);
+
+	return 0;
+}
+
+static int mu_hal_receivemsg(struct mu_type *base, u32 reg_index, u32 *msg)
+{
+	u32 mask = MU_SR_RF0_MASK >> reg_index;
+	u32 val;
+	int ret;
+
+	assert(reg_index < MU_TR_COUNT);
+
+	debug("receivemsg sr 0x%x\n", readl(&base->sr));
+
+	/* Wait RX register to be full. */
+	ret = readl_poll_timeout(&base->sr, val, val & mask, 10000);
+	if (ret < 0) {
+		debug("%s timeout\n", __func__);
+		return -ETIMEDOUT;
+	}
+
+	*msg = readl(&base->rr[reg_index]);
+
+	debug("rr[%d] 0x%x\n",reg_index,  *msg);
+
+	return 0;
+}
+
+static int mu_hal_poll_receive(struct mu_type *base, ulong rx_timeout)
+{
+	u32 mask = MU_SR_RF0_MASK;
+	u32 val;
+	int ret;
+
+	debug("receivemsg sr 0x%x\n", readl(&base->sr));
+
+	/* Wait RX register to be full. */
+	ret = readl_poll_timeout(&base->sr, val, val & mask, rx_timeout);
+	if (ret < 0) {
+		debug("%s timeout\n", __func__);
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static int imx_m4_mu_read(struct mu_type *base, void *data)
+{
+	union imx_m4_msg *msg = (union imx_m4_msg *)data;
+	int ret;
+	u8 count = 0;
+
+	if (!msg)
+		return -EINVAL;
+
+	/* Read 4  words */
+	while (count < 4) {
+		ret = mu_hal_receivemsg(base, count % MU_RR_COUNT,
+					&msg->data[count]);
+		if (ret)
+			return ret;
+		count++;
+	}
+
+	return 0;
+}
+
+static int imx_m4_mu_write(struct mu_type *base, void *data)
+{
+	union imx_m4_msg *msg = (union imx_m4_msg *)data;
+	int ret;
+	u8 count = 0;
+
+	if (!msg)
+		return -EINVAL;
+
+	/* Write 4 words */
+	while (count < 4) {
+		ret = mu_hal_sendmsg(base, count % MU_TR_COUNT,
+				     msg->data[count]);
+		if (ret)
+			return ret;
+		count++;
+	}
+
+	return 0;
+}
+
+/*
+ * Note the function prototype use msgid as the 2nd parameter, here
+ * we take it as no_resp.
+ */
+static int imx_m4_mu_call(struct udevice *dev, int resp_timeout, void *tx_msg,
+			 int tx_size, void *rx_msg, int rx_size)
+{
+	struct imx_m4_mu *priv = dev_get_priv(dev);
+	int ret;
+
+	if (resp_timeout < 0)
+		return -EINVAL;
+
+	if (tx_msg) {
+		ret = imx_m4_mu_write(priv->base, tx_msg);
+		if (ret)
+			return ret;
+	}
+
+	if (rx_msg) {
+		if (resp_timeout) {
+			ret = mu_hal_poll_receive(priv->base, resp_timeout);
+			if (ret)
+				return ret;
+		}
+
+		ret = imx_m4_mu_read(priv->base, rx_msg);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int imx_m4_mu_probe(struct udevice *dev)
+{
+	struct imx_m4_mu *priv = dev_get_priv(dev);
+	fdt_addr_t addr;
+
+	debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv);
+
+	addr = dev_read_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->base = (struct mu_type *)addr;
+
+	debug("mu base 0x%lx\n", (ulong)priv->base);
+
+	/* U-Boot not enable interrupts, so need to enable RX interrupts */
+	mu_hal_init(priv->base);
+
+	return 0;
+}
+
+static int imx_m4_mu_remove(struct udevice *dev)
+{
+	return 0;
+}
+
+static int imx_m4_mu_bind(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+static struct misc_ops imx_m4_mu_ops = {
+	.call = imx_m4_mu_call,
+};
+
+static const struct udevice_id imx_m4_mu_ids[] = {
+	{ .compatible = "fsl,imx-m4-mu" },
+	{ }
+};
+
+U_BOOT_DRIVER(imx_m4_mu) = {
+	.name		= "imx_m4_mu",
+	.id		= UCLASS_MISC,
+	.of_match	= imx_m4_mu_ids,
+	.probe		= imx_m4_mu_probe,
+	.bind		= imx_m4_mu_bind,
+	.remove		= imx_m4_mu_remove,
+	.ops		= &imx_m4_mu_ops,
+	.priv_auto = sizeof(struct imx_m4_mu),
+};
diff --git a/drivers/misc/imx8ulp/Makefile b/drivers/misc/sentinel/Makefile
index 927cc552163..446154cb201 100644
--- a/drivers/misc/imx8ulp/Makefile
+++ b/drivers/misc/sentinel/Makefile
@@ -1,4 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-obj-y += s400_api.o imx8ulp_mu.o
+obj-y += s400_api.o s4mu.o
 obj-$(CONFIG_CMD_FUSE) += fuse.o
diff --git a/drivers/misc/imx8ulp/fuse.c b/drivers/misc/sentinel/fuse.c
index d1feb62ab59..e2b68757664 100644
--- a/drivers/misc/imx8ulp/fuse.c
+++ b/drivers/misc/sentinel/fuse.c
@@ -10,7 +10,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/imx-regs.h>
 #include <env.h>
-#include <asm/arch/s400_api.h>
+#include <asm/mach-imx/s400_api.h>
 #include <asm/global_data.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -31,12 +31,15 @@ struct s400_map_entry {
 	u32 s400_index;
 };
 
+#if defined(CONFIG_IMX8ULP)
+#define FSB_OTP_SHADOW	0x800
+
 struct fsb_map_entry fsb_mapping_table[] = {
 	{ 3, 8 },
 	{ 4, 8 },
+	{ -1, 48 }, /* Reserve 48 words */
 	{ 5, 8 },
 	{ 6, 8 },
-	{ -1, 48 }, /* Reserve 48 words */
 	{ 8,  4, true },
 	{ 24, 4, true },
 	{ 26, 4, true },
@@ -61,8 +64,57 @@ struct s400_map_entry s400_api_mapping_table[] = {
 	{ 1, 8 },	/* LOCK */
 	{ 2, 8 },	/* ECID */
 	{ 7, 4, 0, 1 },	/* OTP_UNIQ_ID */
+	{ 15, 8 }, /* OEM SRK HASH */
 	{ 23, 1, 4, 2 }, /* OTFAD */
+	{ 25, 8 }, /* Test config2 */
+};
+#elif defined(CONFIG_ARCH_IMX9)
+#define FSB_OTP_SHADOW	0x8000
+
+struct fsb_map_entry fsb_mapping_table[] = {
+	{ 0, 8 },
+	{ 1, 8 },
+	{ 2, 8 },
+	{ 3, 8 },
+	{ 4, 8 },
+	{ 5, 8 },
+	{ 6, 4 },
+	{ -1, 260 },
+	{ 39, 8 },
+	{ 40, 8 },
+	{ 41, 8 },
+	{ 42, 8 },
+	{ 43, 8 },
+	{ 44, 8 },
+	{ 45, 8 },
+	{ 46, 8 },
+	{ 47, 8 },
+	{ 48, 8 },
+	{ 49, 8 },
+	{ 50, 8 },
+	{ 51, 8 },
+	{ 52, 8 },
+	{ 53, 8 },
+	{ 54, 8 },
+	{ 55, 8 },
+	{ 56, 8 },
+	{ 57, 8 },
+	{ 58, 8 },
+	{ 59, 8 },
+	{ 60, 8 },
+	{ 61, 8 },
+	{ 62, 8 },
+	{ 63, 8 },
+};
+
+struct s400_map_entry s400_api_mapping_table[] = {
+	{ 7, 1, 7, 63 },
+	{ 16, 8, },
+	{ 17, 8, },
+	{ 22, 1, 6 },
+	{ 23, 1, 4 },
 };
+#endif
 
 static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy)
 {
@@ -72,7 +124,8 @@ static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy)
 	/* map the fuse from ocotp fuse map to FSB*/
 	for (i = 0; i < size; i++) {
 		if (fsb_mapping_table[i].fuse_bank != -1 &&
-		    fsb_mapping_table[i].fuse_bank == bank) {
+		    fsb_mapping_table[i].fuse_bank == bank &&
+		    fsb_mapping_table[i].fuse_words > word) {
 			break;
 		}
 
@@ -116,6 +169,7 @@ static s32 map_s400_fuse_index(u32 bank, u32 word)
 	return s400_api_mapping_table[i].fuse_bank * 8 + word;
 }
 
+#if defined(CONFIG_IMX8ULP)
 int fuse_sense(u32 bank, u32 word, u32 *val)
 {
 	s32 word_index;
@@ -126,7 +180,7 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
 
 	word_index = map_fsb_fuse_index(bank, word, &redundancy);
 	if (word_index >= 0) {
-		*val = readl((ulong)FSB_BASE_ADDR + 0x800 + (word_index << 2));
+		*val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW + (word_index << 2));
 		if (redundancy)
 			*val = (*val >> ((word % 2) * 16)) & 0xFFFF;
 
@@ -168,6 +222,44 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
 
 	return -ENOENT;
 }
+#elif defined(CONFIG_ARCH_IMX9)
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+	s32 word_index;
+	bool redundancy;
+
+	if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
+		return -EINVAL;
+
+	word_index = map_fsb_fuse_index(bank, word, &redundancy);
+	if (word_index >= 0) {
+		*val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW + (word_index << 2));
+		if (redundancy)
+			*val = (*val >> ((word % 2) * 16)) & 0xFFFF;
+
+		return 0;
+	}
+
+	word_index = map_s400_fuse_index(bank, word);
+	if (word_index >= 0) {
+		u32 data;
+		u32 res, size = 1;
+		int ret;
+
+		ret = ahab_read_common_fuse(word_index, &data, size, &res);
+		if (ret) {
+			printf("ahab read fuse failed %d, 0x%x\n", ret, res);
+			return ret;
+		}
+
+		*val = data;
+
+		return 0;
+	}
+
+	return -ENOENT;
+}
+#endif
 
 int fuse_read(u32 bank, u32 word, u32 *val)
 {
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c
new file mode 100644
index 00000000000..271d12191de
--- /dev/null
+++ b/drivers/misc/sentinel/s400_api.c
@@ -0,0 +1,518 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2020 NXP
+ *
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <asm/mach-imx/s400_api.h>
+#include <misc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response)
+{
+	struct udevice *dev = gd->arch.s400_dev;
+	int size = sizeof(struct sentinel_msg);
+	struct sentinel_msg msg;
+	int ret;
+
+	if (!dev) {
+		printf("s400 dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	msg.version = AHAB_VERSION;
+	msg.tag = AHAB_CMD_TAG;
+	msg.size = 2;
+	msg.command = ELE_RELEASE_RDC_REQ;
+	switch (xrdc) {
+	case 0:
+		msg.data[0] = (0x74 << 8) | core_id;
+		break;
+	case 1:
+		msg.data[0] = (0x78 << 8) | core_id;
+		break;
+	case 2:
+		msg.data[0] = (0x82 << 8) | core_id;
+		break;
+	case 3:
+		msg.data[0] = (0x86 << 8) | core_id;
+		break;
+	default:
+		printf("Error: wrong xrdc index %u\n", xrdc);
+		return -EINVAL;
+	}
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, core id %u, response 0x%x\n",
+		       __func__, ret, core_id, msg.data[0]);
+
+	if (response)
+		*response = msg.data[0];
+
+	return ret;
+}
+
+int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response)
+{
+	struct udevice *dev = gd->arch.s400_dev;
+	int size = sizeof(struct sentinel_msg);
+	struct sentinel_msg msg;
+	int ret;
+
+	if (!dev) {
+		printf("s400 dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	msg.version = AHAB_VERSION;
+	msg.tag = AHAB_CMD_TAG;
+	msg.size = 3;
+	msg.command = ELE_OEM_CNTN_AUTH_REQ;
+	msg.data[0] = upper_32_bits(ctnr_addr);
+	msg.data[1] = lower_32_bits(ctnr_addr);
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, cntr_addr 0x%lx, response 0x%x\n",
+		       __func__, ret, ctnr_addr, msg.data[0]);
+
+	if (response)
+		*response = msg.data[0];
+
+	return ret;
+}
+
+int ahab_release_container(u32 *response)
+{
+	struct udevice *dev = gd->arch.s400_dev;
+	int size = sizeof(struct sentinel_msg);
+	struct sentinel_msg msg;
+	int ret;
+
+	if (!dev) {
+		printf("s400 dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	msg.version = AHAB_VERSION;
+	msg.tag = AHAB_CMD_TAG;
+	msg.size = 1;
+	msg.command = ELE_RELEASE_CONTAINER_REQ;
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, response 0x%x\n",
+		       __func__, ret, msg.data[0]);
+
+	if (response)
+		*response = msg.data[0];
+
+	return ret;
+}
+
+int ahab_verify_image(u32 img_id, u32 *response)
+{
+	struct udevice *dev = gd->arch.s400_dev;
+	int size = sizeof(struct sentinel_msg);
+	struct sentinel_msg msg;
+	int ret;
+
+	if (!dev) {
+		printf("s400 dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	msg.version = AHAB_VERSION;
+	msg.tag = AHAB_CMD_TAG;
+	msg.size = 2;
+	msg.command = ELE_VERIFY_IMAGE_REQ;
+	msg.data[0] = 1 << img_id;
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, img_id %u, response 0x%x\n",
+		       __func__, ret, img_id, msg.data[0]);
+
+	if (response)
+		*response = msg.data[0];
+
+	return ret;
+}
+
+int ahab_forward_lifecycle(u16 life_cycle, u32 *response)
+{
+	struct udevice *dev = gd->arch.s400_dev;
+	int size = sizeof(struct sentinel_msg);
+	struct sentinel_msg msg;
+	int ret;
+
+	if (!dev) {
+		printf("s400 dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	msg.version = AHAB_VERSION;
+	msg.tag = AHAB_CMD_TAG;
+	msg.size = 2;
+	msg.command = ELE_FWD_LIFECYCLE_UP_REQ;
+	msg.data[0] = life_cycle;
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, life_cycle 0x%x, response 0x%x\n",
+		       __func__, ret, life_cycle, msg.data[0]);
+
+	if (response)
+		*response = msg.data[0];
+
+	return ret;
+}
+
+int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response)
+{
+	struct udevice *dev = gd->arch.s400_dev;
+	int size = sizeof(struct sentinel_msg);
+	struct sentinel_msg msg;
+	int ret;
+
+	if (!dev) {
+		printf("s400 dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	if (!fuse_words) {
+		printf("Invalid parameters for fuse read\n");
+		return -EINVAL;
+	}
+
+	if ((fuse_id != 1 && fuse_num != 1) ||
+	    (fuse_id == 1 && fuse_num != 4)) {
+		printf("Invalid fuse number parameter\n");
+		return -EINVAL;
+	}
+
+	msg.version = AHAB_VERSION;
+	msg.tag = AHAB_CMD_TAG;
+	msg.size = 2;
+	msg.command = ELE_READ_FUSE_REQ;
+	msg.data[0] = fuse_id;
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n",
+		       __func__, ret, fuse_id, msg.data[0]);
+
+	if (response)
+		*response = msg.data[0];
+
+	fuse_words[0] = msg.data[1];
+	if (fuse_id == 1) {
+		/* OTP_UNIQ_ID */
+		fuse_words[1] = msg.data[2];
+		fuse_words[2] = msg.data[3];
+		fuse_words[3] = msg.data[4];
+	}
+
+	return ret;
+}
+
+int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response)
+{
+	struct udevice *dev = gd->arch.s400_dev;
+	int size = sizeof(struct sentinel_msg);
+	struct sentinel_msg msg;
+	int ret;
+
+	if (!dev) {
+		printf("s400 dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	msg.version = AHAB_VERSION;
+	msg.tag = AHAB_CMD_TAG;
+	msg.size = 3;
+	msg.command = ELE_WRITE_FUSE_REQ;
+	msg.data[0] = (32 << 16) | (fuse_id << 5);
+	if (lock)
+		msg.data[0] |= (1 << 31);
+
+	msg.data[1] = fuse_val;
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, fuse_id 0x%x, response 0x%x\n",
+		       __func__, ret, fuse_id, msg.data[0]);
+
+	if (response)
+		*response = msg.data[0];
+
+	return ret;
+}
+
+int ahab_release_caam(u32 core_did, u32 *response)
+{
+	struct udevice *dev = gd->arch.s400_dev;
+	int size = sizeof(struct sentinel_msg);
+	struct sentinel_msg msg;
+	int ret;
+
+	if (!dev) {
+		printf("s400 dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	msg.version = AHAB_VERSION;
+	msg.tag = AHAB_CMD_TAG;
+	msg.size = 2;
+	msg.command = ELE_RELEASE_CAAM_REQ;
+	msg.data[0] = core_did;
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, response 0x%x\n",
+		       __func__, ret, msg.data[0]);
+
+	if (response)
+		*response = msg.data[0];
+
+	return ret;
+}
+
+int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response)
+{
+	struct udevice *dev = gd->arch.s400_dev;
+	int size = sizeof(struct sentinel_msg);
+	struct sentinel_msg msg;
+	int ret;
+
+	if (!dev) {
+		printf("s400 dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	if (!fw_version) {
+		printf("Invalid parameters for f/w version read\n");
+		return -EINVAL;
+	}
+
+	if (!sha1) {
+		printf("Invalid parameters for commit sha1\n");
+		return -EINVAL;
+	}
+
+	msg.version = AHAB_VERSION;
+	msg.tag = AHAB_CMD_TAG;
+	msg.size = 1;
+	msg.command = ELE_GET_FW_VERSION_REQ;
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, response 0x%x\n",
+		       __func__, ret, msg.data[0]);
+
+	if (response)
+		*response = msg.data[0];
+
+	*fw_version = msg.data[1];
+	*sha1 = msg.data[2];
+
+	return ret;
+}
+
+int ahab_dump_buffer(u32 *buffer, u32 buffer_length)
+{
+	struct udevice *dev = gd->arch.s400_dev;
+	int size = sizeof(struct sentinel_msg);
+	struct sentinel_msg msg;
+	int ret, i = 0;
+
+	if (!dev) {
+		printf("s400 dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	msg.version = AHAB_VERSION;
+	msg.tag = AHAB_CMD_TAG;
+	msg.size = 1;
+	msg.command = ELE_DUMP_DEBUG_BUFFER_REQ;
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret) {
+		printf("Error: %s: ret %d, response 0x%x\n",
+		       __func__, ret, msg.data[0]);
+
+		return ret;
+	}
+
+	if (buffer){
+		buffer[i++] = *(u32 *)&msg; /* Need dump the response header */
+		for (; i < buffer_length && i < msg.size; i++) {
+			buffer[i] = msg.data[i - 1];
+		}
+	}
+
+	return i;
+}
+
+int ahab_get_info(struct sentinel_get_info_data *info, u32 *response)
+{
+	struct udevice *dev = gd->arch.s400_dev;
+	int size = sizeof(struct sentinel_msg);
+	struct sentinel_msg msg;
+	int ret;
+
+	if (!dev) {
+		printf("s400 dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	msg.version = AHAB_VERSION;
+	msg.tag = AHAB_CMD_TAG;
+	msg.size = 4;
+	msg.command = ELE_GET_INFO_REQ;
+	msg.data[0] = upper_32_bits((ulong)info);
+	msg.data[1] = lower_32_bits((ulong)info);
+	msg.data[2] = sizeof(struct sentinel_get_info_data);
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, response 0x%x\n",
+		       __func__, ret, msg.data[0]);
+
+	if (response)
+		*response = msg.data[0];
+
+	return ret;
+}
+
+int ahab_get_fw_status(u32 *status, u32 *response)
+{
+	struct udevice *dev = gd->arch.s400_dev;
+	int size = sizeof(struct sentinel_msg);
+	struct sentinel_msg msg;
+	int ret;
+
+	if (!dev) {
+		printf("s400 dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	msg.version = AHAB_VERSION;
+	msg.tag = AHAB_CMD_TAG;
+	msg.size = 1;
+	msg.command = ELE_GET_FW_STATUS_REQ;
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, response 0x%x\n",
+		       __func__, ret, msg.data[0]);
+
+	if (response)
+		*response = msg.data[0];
+
+	*status = msg.data[1] & 0xF;
+
+	return ret;
+}
+
+int ahab_release_m33_trout(void)
+{
+	struct udevice *dev = gd->arch.s400_dev;
+	int size = sizeof(struct sentinel_msg);
+	struct sentinel_msg msg;
+	int ret;
+
+	if (!dev) {
+		printf("s400 dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	msg.version = AHAB_VERSION;
+	msg.tag = AHAB_CMD_TAG;
+	msg.size = 1;
+	msg.command = ELE_ENABLE_RTC_REQ;
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, response 0x%x\n",
+		       __func__, ret, msg.data[0]);
+
+	return ret;
+}
+
+int ahab_get_events(u32 *events, u32 *events_cnt, u32 *response)
+{
+	struct udevice *dev = gd->arch.s400_dev;
+	int size = sizeof(struct sentinel_msg);
+	struct sentinel_msg msg;
+	int ret, i = 0;
+	u32 actual_events;
+
+	if (!dev) {
+		printf("s400 dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	if (!events || !events_cnt || *events_cnt == 0) {
+		printf("Invalid parameters for %s\n", __func__);
+		return -EINVAL;
+	}
+
+	msg.version = AHAB_VERSION;
+	msg.tag = AHAB_CMD_TAG;
+	msg.size = 1;
+	msg.command = ELE_GET_EVENTS_REQ;
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, response 0x%x\n",
+		       __func__, ret, msg.data[0]);
+
+	if (response)
+		*response = msg.data[0];
+
+	if (!ret) {
+		actual_events = msg.data[1] & 0xffff;
+		if (*events_cnt < actual_events)
+			actual_events = *events_cnt;
+
+		for (; i < actual_events; i++)
+			events[i] = msg.data[i + 2];
+
+		*events_cnt = actual_events;
+	}
+
+	return ret;
+}
+
+int ahab_start_rng(void)
+{
+	struct udevice *dev = gd->arch.s400_dev;
+	int size = sizeof(struct sentinel_msg);
+	struct sentinel_msg msg;
+	int ret;
+
+	if (!dev) {
+		printf("s400 dev is not initialized\n");
+		return -ENODEV;
+	}
+
+	msg.version = AHAB_VERSION;
+	msg.tag = AHAB_CMD_TAG;
+	msg.size = 1;
+	msg.command = ELE_START_RNG;
+
+	ret = misc_call(dev, false, &msg, size, &msg, size);
+	if (ret)
+		printf("Error: %s: ret %d, response 0x%x\n",
+		       __func__, ret, msg.data[0]);
+
+	return ret;
+}
diff --git a/drivers/misc/imx8ulp/imx8ulp_mu.c b/drivers/misc/sentinel/s4mu.c
index 333ebdf5765..bf0f15de246 100644
--- a/drivers/misc/imx8ulp/imx8ulp_mu.c
+++ b/drivers/misc/sentinel/s4mu.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2020 NXP
+ * Copyright 2020-2022 NXP
  */
 
 #include <common.h>
@@ -9,7 +9,7 @@
 #include <dm/lists.h>
 #include <dm/root.h>
 #include <dm/device-internal.h>
-#include <asm/arch/s400_api.h>
+#include <asm/mach-imx/s400_api.h>
 #include <asm/arch/imx-regs.h>
 #include <linux/iopoll.h>
 #include <misc.h>
@@ -42,7 +42,7 @@ int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg)
 
 	assert(reg_index < MU_TR_COUNT);
 
-	debug("sendmsg sr 0x%x\n", readl(&mu_base->sr));
+	debug("sendmsg tsr 0x%x\n", readl(&mu_base->tsr));
 
 	/* Wait TX register to be empty. */
 	ret = readl_poll_timeout(&mu_base->tsr, val, val & mask, 10000);
@@ -64,14 +64,24 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg)
 	u32 mask = MU_SR_RF0_MASK << reg_index;
 	u32 val;
 	int ret;
+	u32 count = 10;
 
 	assert(reg_index < MU_TR_COUNT);
 
-	debug("receivemsg sr 0x%x\n", readl(&mu_base->sr));
+	debug("receivemsg rsr 0x%x\n", readl(&mu_base->rsr));
 
-	/* Wait RX register to be full. */
-	ret = readl_poll_timeout(&mu_base->rsr, val, val & mask, 10000);
-	if (ret < 0) {
+	do {
+		/* Wait RX register to be full. */
+		ret = readl_poll_timeout(&mu_base->rsr, val, val & mask, 1000000);
+		if (ret < 0) {
+			count--;
+			printf("mu receive msg wait %us\n", 10 - count);
+		} else {
+			break;
+		}
+	} while (count > 0);
+
+	if (count == 0) {
 		debug("%s timeout\n", __func__);
 		return -ETIMEDOUT;
 	}
@@ -85,7 +95,7 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg)
 
 static int imx8ulp_mu_read(struct mu_type *base, void *data)
 {
-	struct imx8ulp_s400_msg *msg = (struct imx8ulp_s400_msg *)data;
+	struct sentinel_msg *msg = (struct sentinel_msg *)data;
 	int ret;
 	u8 count = 0;
 
@@ -118,7 +128,7 @@ static int imx8ulp_mu_read(struct mu_type *base, void *data)
 
 static int imx8ulp_mu_write(struct mu_type *base, void *data)
 {
-	struct imx8ulp_s400_msg *msg = (struct imx8ulp_s400_msg *)data;
+	struct sentinel_msg *msg = (struct sentinel_msg *)data;
 	int ret;
 	u8 count = 0;
 
@@ -171,7 +181,7 @@ static int imx8ulp_mu_call(struct udevice *dev, int no_resp, void *tx_msg,
 			return ret;
 	}
 
-	result = ((struct imx8ulp_s400_msg *)rx_msg)->data[0];
+	result = ((struct sentinel_msg *)rx_msg)->data[0];
 	if ((result & 0xff) == 0xd6)
 		return 0;
 
@@ -219,6 +229,7 @@ static struct misc_ops imx8ulp_mu_ops = {
 
 static const struct udevice_id imx8ulp_mu_ids[] = {
 	{ .compatible = "fsl,imx8ulp-mu" },
+	{ .compatible = "fsl,imx93-mu-s4" },
 	{ }
 };
 
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index f04cc44e197..5aca78f25b1 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -107,6 +107,14 @@ config SUPPORT_EMMC_RPMB
 	  Enable support for reading, writing and programming the
 	  key for the Replay Protection Memory Block partition in eMMC.
 
+config SPL_SUPPORT_EMMC_RPMB
+	bool "Support eMMC replay protected memory block (RPMB) in SPL"
+	default n
+	imply CMD_MMC_RPMB
+	help
+	  Enable support for reading, writing and programming the
+	  key for the Replay Protection Memory Block partition in eMMC.
+
 config SUPPORT_EMMC_BOOT
 	bool "Support some additional features of the eMMC boot partitions"
 	help
@@ -834,7 +842,7 @@ config FSL_ESDHC_IMX
 
 config FSL_USDHC
 	bool "Freescale/NXP i.MX uSDHC controller support"
-	depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMX8ULP || IMXRT
+	depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMX8ULP || IMX9 || IMXRT
 	select FSL_ESDHC_IMX
 	help
 	  This enables the Ultra Secured Digital Host Controller enhancements
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index 02208a5ade4..169d0d4df87 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -39,6 +39,9 @@
 #include <dm/ofnode.h>
 #include <linux/iopoll.h>
 #include <linux/dma-mapping.h>
+#if CONFIG_IS_ENABLED(IMX_MODULE_FUSE)
+#include <asm/mach-imx/sys_proto.h>
+#endif
 
 #ifndef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #ifdef CONFIG_FSL_USDHC
@@ -148,6 +151,8 @@ struct fsl_esdhc_priv {
 	struct fsl_esdhc *esdhc_regs;
 	unsigned int sdhc_clk;
 	struct clk per_clk;
+	struct clk ipg_clk;
+	struct clk ahb_clk;
 	unsigned int clock;
 	unsigned int mode;
 #if !CONFIG_IS_ENABLED(DM_MMC)
@@ -1034,6 +1039,11 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
 	/* Set timout to the maximum value */
 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
 
+	/* max 1ms delay with clock on for initialization */
+	esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+	udelay(1000);
+	esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
+
 	return 0;
 }
 
@@ -1263,6 +1273,13 @@ int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
 	if (!cfg)
 		return -EINVAL;
 
+#if CONFIG_IS_ENABLED(IMX_MODULE_FUSE)
+	if (esdhc_fused(cfg->esdhc_base)) {
+		printf("ESDHC@0x%lx is fused, disable it\n", cfg->esdhc_base);
+		return -ENODEV;
+	}
+#endif
+
 	priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
 	if (!priv)
 		return -ENOMEM;
@@ -1291,6 +1308,8 @@ int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
 		break;
 	default:
 		printf("invalid max bus width %u\n", cfg->max_bus_width);
+		free(plat);
+		free(priv);
 		return -EINVAL;
 	}
 
@@ -1371,6 +1390,14 @@ static int fsl_esdhc_of_to_plat(struct udevice *dev)
 	addr = dev_read_addr(dev);
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
+
+#if CONFIG_IS_ENABLED(IMX_MODULE_FUSE)
+	if (esdhc_fused(addr)) {
+		printf("ESDHC@0x%lx is fused, disable it\n", addr);
+		return -ENODEV;
+	}
+#endif
+
 	priv->esdhc_regs = (struct fsl_esdhc *)addr;
 	priv->dev = dev;
 	priv->mode = -1;
@@ -1487,10 +1514,26 @@ static int fsl_esdhc_probe(struct udevice *dev)
 	 * work as expected.
 	 */
 
-	init_clk_usdhc(dev_seq(dev));
-
 #if CONFIG_IS_ENABLED(CLK)
 	/* Assigned clock already set clock */
+	ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
+	if (!ret) {
+		ret = clk_enable(&priv->ipg_clk);
+		if (ret) {
+			printf("Failed to enable ipg_clk\n");
+			return ret;
+		}
+	}
+
+	ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
+	if (!ret) {
+		ret = clk_enable(&priv->ahb_clk);
+		if (ret) {
+			printf("Failed to enable ahb_clk\n");
+			return ret;
+		}
+	}
+
 	ret = clk_get_by_name(dev, "per", &priv->per_clk);
 	if (ret) {
 		printf("Failed to get per_clk\n");
@@ -1504,6 +1547,8 @@ static int fsl_esdhc_probe(struct udevice *dev)
 
 	priv->sdhc_clk = clk_get_rate(&priv->per_clk);
 #else
+	init_clk_usdhc(dev_seq(dev));
+
 	priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev_seq(dev));
 	if (priv->sdhc_clk <= 0) {
 		dev_err(dev, "Unable to get clk for %s\n", dev->name);
@@ -1529,7 +1574,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
 
 	upriv->mmc = mmc;
 
-	return esdhc_init_common(priv, mmc);
+	return 0;
 }
 
 static int fsl_esdhc_get_cd(struct udevice *dev)
@@ -1597,6 +1642,14 @@ static int fsl_esdhc_wait_dat0(struct udevice *dev, int state,
 	return ret;
 }
 
+static int fsl_esdhc_reinit(struct udevice *dev)
+{
+	struct fsl_esdhc_plat *plat = dev_get_plat(dev);
+	struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+
+	return esdhc_init_common(priv, &plat->mmc);
+}
+
 static const struct dm_mmc_ops fsl_esdhc_ops = {
 	.get_cd		= fsl_esdhc_get_cd,
 	.send_cmd	= fsl_esdhc_send_cmd,
@@ -1608,6 +1661,7 @@ static const struct dm_mmc_ops fsl_esdhc_ops = {
 	.set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
 #endif
 	.wait_dat0 = fsl_esdhc_wait_dat0,
+	.reinit = fsl_esdhc_reinit,
 };
 
 static struct esdhc_soc_data usdhc_imx7d_data = {
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index f6ccd837aa4..715e3f0b975 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -833,6 +833,9 @@ static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
 	 * is false, because by now (after 'timeout_ms' ms) the bus should be
 	 * reliable.
 	 */
+	if (!send_status)
+		return 0;
+
 	do {
 		ret = mmc_send_status(mmc, &status);
 
@@ -3080,10 +3083,11 @@ int mmc_init_device(int num)
 	}
 
 	m = mmc_get_mmc_dev(dev);
-	m->user_speed_mode = MMC_MODES_END; /* Initialising user set speed mode */
-
 	if (!m)
 		return 0;
+
+	m->user_speed_mode = MMC_MODES_END; /* Initialising user set speed mode */
+
 	if (m->preinit)
 		mmc_start_init(m);
 
diff --git a/drivers/mmc/rpmb.c b/drivers/mmc/rpmb.c
index b68d98573c9..d2a218c5c33 100644
--- a/drivers/mmc/rpmb.c
+++ b/drivers/mmc/rpmb.c
@@ -41,12 +41,6 @@
 #define RPMB_ERR_CNT_EXPIRED	0x80
 #define RPMB_ERR_MSK		0x7
 
-/* Sizes of RPMB data frame */
-#define RPMB_SZ_STUFF		196
-#define RPMB_SZ_MAC		32
-#define RPMB_SZ_DATA		256
-#define RPMB_SZ_NONCE		16
-
 #define SHA256_BLOCK_SIZE	64
 
 /* Error messages */
@@ -61,20 +55,6 @@ static const char * const rpmb_err_msg[] = {
 	"Authentication key not yet programmed",
 };
 
-
-/* Structure of RPMB data frame. */
-struct s_rpmb {
-	unsigned char stuff[RPMB_SZ_STUFF];
-	unsigned char mac[RPMB_SZ_MAC];
-	unsigned char data[RPMB_SZ_DATA];
-	unsigned char nonce[RPMB_SZ_NONCE];
-	unsigned int write_counter;
-	unsigned short address;
-	unsigned short block_count;
-	unsigned short result;
-	unsigned short request;
-};
-
 static int mmc_set_blockcount(struct mmc *mmc, unsigned int blockcount,
 			      bool is_rel_write)
 {
@@ -88,7 +68,7 @@ static int mmc_set_blockcount(struct mmc *mmc, unsigned int blockcount,
 
 	return mmc_send_cmd(mmc, &cmd, NULL);
 }
-static int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s,
+int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s,
 			    unsigned int count, bool is_rel_write)
 {
 	struct mmc_cmd cmd = {0};
@@ -112,7 +92,7 @@ static int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s,
 		cmd.resp_type = MMC_RSP_R1;
 
 	data.src = (const char *)s;
-	data.blocks = 1;
+	data.blocks = count;
 	data.blocksize = MMC_MAX_BLOCK_LEN;
 	data.flags = MMC_DATA_WRITE;
 
@@ -125,14 +105,14 @@ static int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s,
 	}
 	return 0;
 }
-static int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s,
-			     unsigned short expected)
+int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s,
+			     unsigned int count, unsigned short expected)
 {
 	struct mmc_cmd cmd = {0};
 	struct mmc_data data;
 	int ret;
 
-	ret = mmc_set_blockcount(mmc, 1, false);
+	ret = mmc_set_blockcount(mmc, count, false);
 	if (ret) {
 #ifdef CONFIG_MMC_RPMB_TRACE
 		printf("%s:mmc_set_blockcount-> %d\n", __func__, ret);
@@ -144,7 +124,7 @@ static int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s,
 	cmd.resp_type = MMC_RSP_R1;
 
 	data.dest = (char *)s;
-	data.blocks = 1;
+	data.blocks = count;
 	data.blocksize = MMC_MAX_BLOCK_LEN;
 	data.flags = MMC_DATA_READ;
 
@@ -156,7 +136,7 @@ static int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s,
 		return -1;
 	}
 	/* Check the response and the status */
-	if (be16_to_cpu(s->request) != expected) {
+	if (expected && be16_to_cpu(s->request) != expected) {
 #ifdef CONFIG_MMC_RPMB_TRACE
 		printf("%s:response= %x\n", __func__,
 		       be16_to_cpu(s->request));
@@ -183,7 +163,7 @@ static int mmc_rpmb_status(struct mmc *mmc, unsigned short expected)
 		return -1;
 
 	/* Read the result */
-	return mmc_rpmb_response(mmc, rpmb_frame, expected);
+	return mmc_rpmb_response(mmc, rpmb_frame, 1, expected);
 }
 static void rpmb_hmac(unsigned char *key, unsigned char *buff, int len,
 		      unsigned char *output)
@@ -241,7 +221,7 @@ int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *pcounter)
 		return -1;
 
 	/* Read the result */
-	ret = mmc_rpmb_response(mmc, rpmb_frame, RPMB_RESP_WCOUNTER);
+	ret = mmc_rpmb_response(mmc, rpmb_frame, 1, RPMB_RESP_WCOUNTER);
 	if (ret)
 		return ret;
 
@@ -277,7 +257,7 @@ int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
 			break;
 
 		/* Read the result */
-		if (mmc_rpmb_response(mmc, rpmb_frame, RPMB_RESP_READ_DATA))
+		if (mmc_rpmb_response(mmc, rpmb_frame, 1, RPMB_RESP_READ_DATA))
 			break;
 
 		/* Check the HMAC if key is provided */
diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c
index ee5d7fde9ce..88870fd2a6d 100644
--- a/drivers/mtd/nand/raw/mxs_nand.c
+++ b/drivers/mtd/nand/raw/mxs_nand.c
@@ -1307,6 +1307,13 @@ static int mxs_nand_init_dma(struct mxs_nand_info *info)
 {
 	int i = 0, j, ret = 0;
 
+	if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
+		if (check_module_fused(MODULE_GPMI)) {
+			printf("NAND GPMI@0x%lx is fused, disable it\n", (ulong)info->gpmi_regs);
+			return -EPERM;
+		}
+	}
+
 	info->desc = malloc(sizeof(struct mxs_dma_desc *) *
 				MXS_NAND_DMA_DESCRIPTOR_COUNT);
 	if (!info->desc) {
@@ -1380,6 +1387,9 @@ int mxs_nand_init_spl(struct nand_chip *nand)
 	else
 		nand_info->max_ecc_strength_supported = 40;
 
+	if (IS_ENABLED(CONFIG_NAND_MXS_USE_MINIMUM_ECC))
+		nand_info->use_minimum_ecc = true;
+
 	err = mxs_nand_alloc_buffers(nand_info);
 	if (err)
 		return err;
diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c
index 9e0b8afb522..003250197d7 100644
--- a/drivers/mtd/nand/raw/mxs_nand_spl.c
+++ b/drivers/mtd/nand/raw/mxs_nand_spl.c
@@ -239,7 +239,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf)
 	page_off = offs & (mtd->writesize - 1);
 	nand_page_per_block = mtd->erasesize / mtd->writesize;
 
-	debug("%s offset:0x%08x len:%d page:%x\n", __func__, offs, size, page);
+	debug("%s offset:0x%08x len:%d page:0x%x\n", __func__, offs, size, page);
 
 	while (size) {
 		if (mxs_read_page_ecc(mtd, page_buf, page) < 0)
@@ -283,11 +283,6 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf)
 	return 0;
 }
 
-struct mtd_info *nand_get_mtd(void)
-{
-	return mtd;
-}
-
 int nand_default_bbt(struct mtd_info *mtd)
 {
 	return 0;
diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
index 6bacf14aafe..a039fb66975 100644
--- a/drivers/mtd/nand/spi/micron.c
+++ b/drivers/mtd/nand/spi/micron.c
@@ -48,6 +48,18 @@ static SPINAND_OP_VARIANTS(update_cache_variants,
 		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
 		SPINAND_PROG_LOAD(false, 0, NULL, 0));
 
+static SPINAND_OP_VARIANTS(mt29f4g01_read_cache_variants,
+		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+		SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(mt29f4g01_write_cache_variants,
+		SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(mt29f4g01_update_cache_variants,
+		SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
 static int micron_8_ooblayout_ecc(struct mtd_info *mtd, int section,
 				  struct mtd_oob_region *region)
 {
@@ -66,9 +78,9 @@ static int micron_8_ooblayout_free(struct mtd_info *mtd, int section,
 	if (section)
 		return -ERANGE;
 
-	/* Reserve 2 bytes for the BBM. */
-	region->offset = 2;
-	region->length = (mtd->oobsize / 2) - 2;
+	/* Reserve 4 bytes for the BBM. */
+	region->offset = 4;
+	region->length = (mtd->oobsize / 2) - 4;
 
 	return 0;
 }
@@ -212,6 +224,16 @@ static const struct spinand_info micron_spinand_table[] = {
 		     SPINAND_ECCINFO(&micron_8_ooblayout,
 				     micron_8_ecc_get_status),
 		     SPINAND_SELECT_TARGET(micron_select_target)),
+	SPINAND_INFO("MT29F4G01ADAGD", 0x32,
+			 NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 2),
+			 NAND_ECCREQ(8, 512),
+			 SPINAND_INFO_OP_VARIANTS(&mt29f4g01_read_cache_variants,
+						  &mt29f4g01_write_cache_variants,
+						  &mt29f4g01_update_cache_variants),
+			 0,
+		     SPINAND_ECCINFO(&micron_8_ooblayout,
+				     micron_8_ecc_get_status),
+		     SPINAND_SELECT_TARGET(micron_select_target)),
 };
 
 static int micron_spinand_detect(struct spinand_device *spinand)
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index f350c7e5dc2..2d9c9c09ce2 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -202,6 +202,11 @@ config SPI_FLASH_XTX
 	  Add support for various XTX (XTX Technology Limited)
 	  SPI flash chips (XT25xxx).
 
+config SPI_FLASH_ADESTO
+	bool "Adesto SPI flash support"
+	help
+	  Add support for various Adesto SPI flash chips (ATXPxxx)
+
 endif
 
 config SPI_FLASH_USE_4K_SECTORS
diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
index b59edd152cc..34e2aa63fbd 100644
--- a/drivers/mtd/spi/sf_dataflash.c
+++ b/drivers/mtd/spi/sf_dataflash.c
@@ -136,11 +136,11 @@ static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len)
 	memset(dataflash->command, 0 , sizeof(dataflash->command));
 	command = dataflash->command;
 
-	debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
+	debug("%s: erase addr=0x%x len 0x%lx\n", dev->name, offset, len);
 
 	div_u64_rem(len, spi_flash->page_size, &rem);
 	if (rem) {
-		printf("%s: len(0x%x) isn't the multiple of page size(0x%x)\n",
+		printf("%s: len(0x%lx) isn't the multiple of page size(0x%x)\n",
 		       dev->name, len, spi_flash->page_size);
 		return -EINVAL;
 	}
@@ -227,7 +227,7 @@ static int spi_dataflash_read(struct udevice *dev, u32 offset, size_t len,
 	memset(dataflash->command, 0 , sizeof(dataflash->command));
 	command = dataflash->command;
 
-	debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
+	debug("%s: erase addr=0x%x len 0x%lx\n", dev->name, offset, len);
 	debug("READ: (%x) %x %x %x\n",
 	      command[0], command[1], command[2], command[3]);
 
@@ -285,7 +285,7 @@ int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len,
 	memset(dataflash->command, 0 , sizeof(dataflash->command));
 	command = dataflash->command;
 
-	debug("%s: write 0x%x..0x%x\n", dev->name, offset, (offset + len));
+	debug("%s: write 0x%x..0x%lx\n", dev->name, offset, (offset + len));
 
 	pageaddr = ((unsigned)offset / spi_flash->page_size);
 	to = ((unsigned)offset % spi_flash->page_size);
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index d3ef69ec74f..d03ce417663 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -69,6 +69,7 @@ struct flash_info {
 #define SPI_NOR_HAS_SST26LOCK	BIT(15)	/* Flash supports lock/unlock via BPR */
 #define SPI_NOR_OCTAL_READ	BIT(16)	/* Flash supports Octal Read */
 #define SPI_NOR_OCTAL_DTR_READ	BIT(17)	/* Flash supports Octal DTR Read */
+#define SPI_NOR_OCTAL_DTR_PP    BIT(18) /* Flash supports Octal DTR Page Program */
 };
 
 extern const struct flash_info spi_nor_ids[];
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index a70fbda4bbc..ddf0851414b 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -1329,7 +1329,7 @@ static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
 static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
 {
 	int			tmp;
-	u8			id[SPI_NOR_MAX_ID_LEN];
+	u8			id[SPI_NOR_MAX_ID_LEN * 2];
 	const struct flash_info	*info;
 
 	tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
@@ -1346,8 +1346,28 @@ static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
 		}
 	}
 
+#if defined(CONFIG_SPI_FLASH_ADESTO)
+	tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN * 2);
+	if (tmp < 0) {
+		dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
+		return ERR_PTR(tmp);
+	}
+
+	info = spi_nor_ids;
+	for (; info->name; info++) {
+		if (info->id_len) {
+			if (!memcmp(info->id, &id[7], info->id_len))
+				return info;
+		}
+	}
+
+	dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
+		id[7], id[8], id[9]);
+#endif
+
 	dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
 		id[0], id[1], id[2]);
+
 	return ERR_PTR(-ENODEV);
 }
 
@@ -2682,12 +2702,15 @@ static int spi_nor_init_params(struct spi_nor *nor,
 	spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
 				SPINOR_OP_PP, SNOR_PROTO_1_1_1);
 
-	/*
-	 * Since xSPI Page Program opcode is backward compatible with
-	 * Legacy SPI, use Legacy SPI opcode there as well.
-	 */
-	spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
-				SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR);
+	if (info->flags & SPI_NOR_OCTAL_DTR_PP) {
+		params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
+		/*
+		 * Since xSPI Page Program opcode is backward compatible with
+		 * Legacy SPI, use Legacy SPI opcode there as well.
+		 */
+		spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
+					SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR);
+	}
 
 	if (info->flags & SPI_NOR_QUAD_READ) {
 		params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
@@ -3569,6 +3592,7 @@ static int spi_nor_init(struct spi_nor *nor)
 	    (JEDEC_MFR(nor->info) == SNOR_MFR_ATMEL ||
 	     JEDEC_MFR(nor->info) == SNOR_MFR_INTEL ||
 	     JEDEC_MFR(nor->info) == SNOR_MFR_SST ||
+	     JEDEC_MFR(nor->info) == SNOR_MFR_ADESTO ||
 	     nor->info->flags & SPI_NOR_HAS_LOCK)) {
 		write_enable(nor);
 		write_sr(nor, 0);
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 763bab04c60..75243377467 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -63,6 +63,10 @@
  * old entries may be missing 4K flag.
  */
 const struct flash_info spi_nor_ids[] = {
+#ifdef CONFIG_SPI_FLASH_ADESTO		/* ADESTO */
+	/* Fix to 4 bytes addr width, except 0x03 read, others are using 4 bytes */
+	{ INFO("atxp032",	 0x43a700, 0, 64 * 1024,   64, SECT_4K | SPI_NOR_HAS_LOCK) .addr_width = 4, },
+#endif
 #ifdef CONFIG_SPI_FLASH_ATMEL		/* ATMEL */
 	/* Atmel -- some are (confusingly) marketed as "DataFlash" */
 	{ INFO("at26df321",	0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
@@ -98,6 +102,11 @@ const struct flash_info spi_nor_ids[] = {
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
 	},
 	{
+		INFO("gd25lq16", 0xc86015, 0, 64 * 1024,  32,
+			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+	},
+	{
 		INFO("gd25lq32", 0xc86016, 0, 64 * 1024, 64,
 			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
@@ -178,6 +187,7 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("mx66l1g45g",  0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("mx25l1633e", 0xc22415, 0, 64 * 1024,   32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
 	{ INFO("mx25r6435f", 0xc22817, 0, 64 * 1024,   128,  SECT_4K) },
+	{ INFO("mx25uw51345g", 0xc2843a, 0,  64 * 1024,  1024, SECT_4K | SPI_NOR_4B_OPCODES) },
 	{ INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
 #endif
 
@@ -206,7 +216,10 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("mt25qu02g",   0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ INFO("mt25ql02g",   0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) },
 #ifdef CONFIG_SPI_FLASH_MT35XU
-	{ INFO("mt35xu512aba", 0x2c5b1a, 0,  128 * 1024,  512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
+	{ INFO("mt35xu512aba", 0x2c5b1a, 0,  128 * 1024,  512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) },
+#else
+	/* for platforms that didn't enable DTR read */
+	{ INFO("mt35xu512aba", 0x2c5b1a, 0,  128 * 1024,  512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
 #endif /* CONFIG_SPI_FLASH_MT35XU */
 	{ INFO("mt35xu02g",  0x2c5b1c, 0, 128 * 1024,  2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
 #endif
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 71e0cbafb41..ae7e2fe5bef 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -334,7 +334,7 @@ config FEC_MXC_MDIO_BASE
 
 config FEC_MXC
 	bool "FEC Ethernet controller"
-	depends on MX28 || MX5 || MX6 || MX7 || IMX8 || IMX8M || IMX8ULP || VF610
+	depends on MX28 || MX5 || MX6 || MX7 || IMX8 || IMX8M || IMX8ULP || IMX93 || VF610
 	help
 	  This driver supports the 10/100 Fast Ethernet controller for
 	  NXP i.MX processors.
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 22dad5b2030..fbf207a2e62 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (c) 2016, NVIDIA CORPORATION.
+ * Copyright 2020 NXP
  *
  * Portions based on U-Boot's rtl8169.c.
  */
@@ -47,7 +48,7 @@
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <eth_phy.h>
-#ifdef CONFIG_ARCH_IMX8M
+#if defined(CONFIG_IMX8MP) || defined(CONFIG_IMX8DXL) || defined(CONFIG_IMX93)
 #include <asm/arch/clock.h>
 #include <asm/mach-imx/sys_proto.h>
 #endif
@@ -309,6 +310,7 @@ struct eqos_priv {
 	struct clk clk_slave_bus;
 	struct mii_dev *mii;
 	struct phy_device *phy;
+	ofnode phy_of_node;
 	u32 max_speed;
 	void *descs;
 	int tx_desc_idx, rx_desc_idx;
@@ -615,6 +617,47 @@ err:
 #endif
 }
 
+static int eqos_start_clks_imx(struct udevice *dev)
+{
+#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
+	struct eqos_priv *eqos = dev_get_priv(dev);
+	int ret;
+
+	debug("%s(dev=%p):\n", __func__, dev);
+
+	ret = clk_enable(&eqos->clk_slave_bus);
+	if (ret < 0) {
+		pr_err("clk_enable(clk_slave_bus) failed: %d", ret);
+		goto err;
+	}
+
+	ret = clk_enable(&eqos->clk_master_bus);
+	if (ret < 0) {
+		pr_err("clk_enable(clk_master_bus) failed: %d", ret);
+		goto err_disable_clk_slave_bus;
+	}
+
+	ret = clk_enable(&eqos->clk_tx);
+	if (ret < 0) {
+		pr_err("clk_enable(clk_tx) failed: %d", ret);
+		goto err_disable_clk_master_bus;
+	}
+#endif
+
+	debug("%s: OK\n", __func__);
+	return 0;
+
+#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
+err_disable_clk_master_bus:
+	clk_disable(&eqos->clk_master_bus);
+err_disable_clk_slave_bus:
+	clk_disable(&eqos->clk_slave_bus);
+err:
+	debug("%s: FAILED: %d\n", __func__, ret);
+	return ret;
+#endif
+}
+
 static int eqos_stop_clks_tegra186(struct udevice *dev)
 {
 #ifdef CONFIG_CLK
@@ -649,6 +692,22 @@ static int eqos_stop_clks_stm32(struct udevice *dev)
 	return 0;
 }
 
+static int eqos_stop_clks_imx(struct udevice *dev)
+{
+#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
+	struct eqos_priv *eqos = dev_get_priv(dev);
+
+	debug("%s(dev=%p):\n", __func__, dev);
+
+	clk_disable(&eqos->clk_tx);
+	clk_disable(&eqos->clk_slave_bus);
+	clk_disable(&eqos->clk_master_bus);
+#endif
+
+	debug("%s: OK\n", __func__);
+	return 0;
+}
+
 static int eqos_start_resets_tegra186(struct udevice *dev)
 {
 	struct eqos_priv *eqos = dev_get_priv(dev);
@@ -783,7 +842,12 @@ __weak int imx_eqos_txclk_set_rate(unsigned long rate)
 
 static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
 {
+#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
+	struct eqos_priv *eqos = dev_get_priv(dev);
+	return clk_get_rate(&eqos->clk_slave_bus);
+#else
 	return imx_get_eqos_csr_clk();
+#endif
 }
 
 static int eqos_set_full_duplex(struct udevice *dev)
@@ -886,7 +950,7 @@ static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
 {
 	struct eqos_priv *eqos = dev_get_priv(dev);
 	ulong rate;
-	int ret;
+	int ret = 0;
 
 	debug("%s(dev=%p):\n", __func__, dev);
 
@@ -905,7 +969,12 @@ static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
 		return -EINVAL;
 	}
 
+#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
+	if (!is_imx8dxl())
+		ret = clk_set_rate(&eqos->clk_tx, rate);
+#else
 	ret = imx_eqos_txclk_set_rate(rate);
+#endif
 	if (ret < 0) {
 		pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
 		return ret;
@@ -1025,12 +1094,30 @@ static int eqos_read_rom_hwaddr(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_plat(dev);
 
-#ifdef CONFIG_ARCH_IMX8M
+#if defined(CONFIG_IMX8MP) || defined(CONFIG_IMX8DXL) || defined(CONFIG_IMX93)
 	imx_get_mac_from_fuse(dev_seq(dev), pdata->enetaddr);
 #endif
 	return !is_valid_ethaddr(pdata->enetaddr);
 }
 
+static int eqos_get_phy_addr(struct eqos_priv *priv, struct udevice *dev)
+{
+	struct ofnode_phandle_args phandle_args;
+	int reg;
+
+	if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+				       &phandle_args)) {
+		debug("Failed to find phy-handle");
+		return -ENODEV;
+	}
+
+	priv->phy_of_node = phandle_args.node;
+
+	reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
+
+	return reg;
+}
+
 static int eqos_start(struct udevice *dev)
 {
 	struct eqos_priv *eqos = dev_get_priv(dev);
@@ -1079,9 +1166,7 @@ static int eqos_start(struct udevice *dev)
 	 */
 	if (!eqos->phy) {
 		int addr = -1;
-#ifdef CONFIG_DM_ETH_PHY
-		addr = eth_phy_get_addr(dev);
-#endif
+		addr = eqos_get_phy_addr(eqos, dev);
 #ifdef DWC_NET_PHYADDR
 		addr = DWC_NET_PHYADDR;
 #endif
@@ -1100,6 +1185,7 @@ static int eqos_start(struct udevice *dev)
 			}
 		}
 
+		eqos->phy->node = eqos->phy_of_node;
 		ret = phy_config(eqos->phy);
 		if (ret < 0) {
 			pr_err("phy_config() failed: %d", ret);
@@ -1751,6 +1837,7 @@ static phy_interface_t eqos_get_interface_tegra186(struct udevice *dev)
 static int eqos_probe_resources_imx(struct udevice *dev)
 {
 	struct eqos_priv *eqos = dev_get_priv(dev);
+	__maybe_unused int ret;
 	phy_interface_t interface;
 
 	debug("%s(dev=%p):\n", __func__, dev);
@@ -1762,8 +1849,39 @@ static int eqos_probe_resources_imx(struct udevice *dev)
 		return -EINVAL;
 	}
 
+#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
+	ret = clk_get_by_name(dev, "aclk", &eqos->clk_master_bus);
+	if (ret) {
+		pr_err("clk_get_by_name(csr) failed: %d", ret);
+		goto err_probe;
+	}
+
+	ret = clk_get_by_name(dev, "csr", &eqos->clk_slave_bus);
+	if (ret) {
+		pr_err("clk_get_by_name(aclk) failed: %d", ret);
+		goto err_free_clk_master_bus;
+	}
+
+	ret = clk_get_by_name(dev, "tx_clk", &eqos->clk_tx);
+	if (ret) {
+		pr_err("clk_get_by_name(tx) failed: %d", ret);
+		goto err_free_clk_slave_bus;
+	}
+#endif
+
 	debug("%s: OK\n", __func__);
 	return 0;
+
+#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
+err_free_clk_slave_bus:
+	clk_free(&eqos->clk_slave_bus);
+err_free_clk_master_bus:
+	clk_free(&eqos->clk_master_bus);
+err_probe:
+
+	debug("%s: returns %d\n", __func__, ret);
+	return ret;
+#endif
 }
 
 static phy_interface_t eqos_get_interface_imx(struct udevice *dev)
@@ -1802,9 +1920,10 @@ static int eqos_remove_resources_tegra186(struct udevice *dev)
 
 static int eqos_remove_resources_stm32(struct udevice *dev)
 {
-#ifdef CONFIG_CLK
 	struct eqos_priv *eqos = dev_get_priv(dev);
 
+#ifdef CONFIG_CLK
+
 	debug("%s(dev=%p):\n", __func__, dev);
 
 	clk_free(&eqos->clk_tx);
@@ -1821,6 +1940,20 @@ static int eqos_remove_resources_stm32(struct udevice *dev)
 	return 0;
 }
 
+static int eqos_remove_resources_imx(struct udevice *dev)
+{
+#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
+	struct eqos_priv *eqos = dev_get_priv(dev);
+	debug("%s(dev=%p):\n", __func__, dev);
+	clk_free(&eqos->clk_tx);
+	clk_free(&eqos->clk_slave_bus);
+	clk_free(&eqos->clk_master_bus);
+#endif
+
+	debug("%s: OK\n", __func__);
+	return 0;
+}
+
 static int eqos_probe(struct udevice *dev)
 {
 	struct eqos_priv *eqos = dev_get_priv(dev);
@@ -1995,11 +2128,11 @@ static struct eqos_ops eqos_imx_ops = {
 	.eqos_inval_buffer = eqos_inval_buffer_generic,
 	.eqos_flush_buffer = eqos_flush_buffer_generic,
 	.eqos_probe_resources = eqos_probe_resources_imx,
-	.eqos_remove_resources = eqos_null_ops,
+	.eqos_remove_resources = eqos_remove_resources_imx,
 	.eqos_stop_resets = eqos_null_ops,
 	.eqos_start_resets = eqos_null_ops,
-	.eqos_stop_clks = eqos_null_ops,
-	.eqos_start_clks = eqos_null_ops,
+	.eqos_stop_clks = eqos_stop_clks_imx,
+	.eqos_start_clks = eqos_start_clks_imx,
 	.eqos_calibrate_pads = eqos_null_ops,
 	.eqos_disable_calibration = eqos_null_ops,
 	.eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 985b0384473..84fbc43a37d 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -6,7 +6,6 @@
  * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
  */
-
 #include <common.h>
 #include <cpu_func.h>
 #include <dm.h>
@@ -163,7 +162,7 @@ static int fec_get_clk_rate(void *udev, int idx)
 	}
 }
 
-static void fec_mii_setspeed(struct ethernet_regs *eth)
+static void fec_mii_setspeed(struct ethernet_regs *eth, int idx)
 {
 	/*
 	 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
@@ -185,7 +184,7 @@ static void fec_mii_setspeed(struct ethernet_regs *eth)
 	u32 hold;
 	int ret;
 
-	ret = fec_get_clk_rate(NULL, 0);
+	ret = fec_get_clk_rate(NULL, idx);
 	if (ret < 0) {
 		printf("Can't find FEC0 clk rate: %d\n", ret);
 		return;
@@ -620,7 +619,7 @@ static int fec_init(struct eth_device *dev, struct bd_info *bd)
 	fec_reg_setup(fec);
 
 	if (fec->xcv_type != SEVENWIRE)
-		fec_mii_setspeed(fec->bus->priv);
+		fec_mii_setspeed(fec->bus->priv, fec->dev_id);
 
 	/* Set Opcode/Pause Duration Register */
 	writel(0x00010020, &fec->eth->op_pause);	/* FIXME 0xffff0020; */
@@ -631,7 +630,8 @@ static int fec_init(struct eth_device *dev, struct bd_info *bd)
 	writel(0x00000000, &fec->eth->gaddr2);
 
 	/* Do not access reserved register */
-	if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() && !is_imx8ulp()) {
+	if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() && !is_imx8ulp() &&
+	    !is_imx93()) {
 		/* clear MIB RAM */
 		for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
 			writel(0, i);
@@ -1100,10 +1100,14 @@ struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
 		free(bus);
 		return NULL;
 	}
-	fec_mii_setspeed(eth);
+	fec_mii_setspeed(eth, dev_id);
 	return bus;
 }
 
+__weak void init_clk_fec(int index)
+{
+}
+
 #ifndef CONFIG_DM_ETH
 #ifdef CONFIG_PHYLIB
 int fec_probe(struct bd_info *bd, int dev_id, uint32_t base_addr,
@@ -1169,7 +1173,7 @@ static int fec_probe(struct bd_info *bd, int dev_id, uint32_t base_addr,
 	fec_set_dev_name(edev->name, dev_id);
 	fec->dev_id = (dev_id == -1) ? 0 : dev_id;
 	fec->bus = bus;
-	fec_mii_setspeed(bus->priv);
+	fec_mii_setspeed(bus->priv, fec->dev_id);
 #ifdef CONFIG_PHYLIB
 	fec->phydev = phydev;
 	phy_connect_dev(phydev, edev);
@@ -1229,6 +1233,7 @@ int fecmxc_initialize_multi(struct bd_info *bd, int dev_id, int phy_id,
 #else
 	base_mii = addr;
 #endif
+	init_clk_fec(dev_id);
 	debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
 	bus = fec_get_miibus(base_mii, dev_id);
 	if (!bus)
@@ -1387,6 +1392,7 @@ static int fecmxc_probe(struct udevice *dev)
 	}
 
 	if (IS_ENABLED(CONFIG_IMX8)) {
+		struct clk clk_2x_txclk;
 		ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
 		if (ret < 0) {
 			debug("Can't get FEC ipg clk: %d\n", ret);
@@ -1398,6 +1404,35 @@ static int fecmxc_probe(struct udevice *dev)
 			return ret;
 		}
 
+		ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
+		if (ret < 0) {
+			debug("Can't get FEC ahb clk: %d\n", ret);
+			return ret;
+		}
+		ret = clk_enable(&priv->ahb_clk);
+		if (ret < 0) {
+			debug("Can't enable FEC ahb clk: %d\n", ret);
+			return ret;
+		}
+
+		ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref);
+		if (ret >= 0) {
+			ret = clk_enable(&priv->clk_ref);
+			if (ret < 0) {
+				debug("Can't enable FEC ref clk: %d\n", ret);
+				return ret;
+			}
+		}
+
+		ret = clk_get_by_name(dev, "enet_2x_txclk", &clk_2x_txclk);
+		if (ret >= 0) {
+			ret = clk_enable(&clk_2x_txclk);
+			if (ret < 0) {
+				debug("Can't enable FEC 2x_tx clk: %d\n", ret);
+				return ret;
+			}
+		}
+
 		priv->clk_rate = clk_get_rate(&priv->ipg_clk);
 	} else if (CONFIG_IS_ENABLED(CLK_CCF)) {
 		ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
@@ -1612,6 +1647,8 @@ static const struct udevice_id fecmxc_ids[] = {
 	{ .compatible = "fsl,imx53-fec" },
 	{ .compatible = "fsl,imx7d-fec" },
 	{ .compatible = "fsl,mvf600-fec" },
+	{ .compatible = "fsl,imx8qm-fec" },
+	{ .compatible = "fsl,imx93-fec" },
 	{ }
 };
 
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 24c3ea59bbb..e3e26062751 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -457,6 +457,20 @@ static struct phy_driver RTL8211F_driver = {
 	.writeext = &rtl8211f_phy_extwrite,
 };
 
+/* Support for RTL8211F-VD PHY */
+static struct phy_driver RTL8211FVD_driver = {
+	.name = "RealTek RTL8211F-VD",
+	.uid = 0x1cc878,
+	.mask = 0xffffff,
+	.features = PHY_GBIT_FEATURES,
+	.probe = &rtl8211f_probe,
+	.config = &rtl8211f_config,
+	.startup = &rtl8211f_startup,
+	.shutdown = &genphy_shutdown,
+	.readext = &rtl8211f_phy_extread,
+	.writeext = &rtl8211f_phy_extwrite,
+};
+
 /* Support for RTL8201F PHY */
 static struct phy_driver RTL8201F_driver = {
 	.name = "RealTek RTL8201F 10/100Mbps Ethernet",
@@ -476,6 +490,7 @@ int phy_realtek_init(void)
 	phy_register(&RTL8211F_driver);
 	phy_register(&RTL8211DN_driver);
 	phy_register(&RTL8201F_driver);
+	phy_register(&RTL8211FVD_driver);
 
 	return 0;
 }
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index 756166fd3ea..a4da9e23e3f 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -4,6 +4,9 @@
  *
  * Copyright (C) 2013 Marek Vasut <marex@denx.de>
  *
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2019 NXP
+ *
  * Based on upstream Linux kernel driver:
  * pci-imx6.c:		Sean Cross <xobs@kosagi.com>
  * pcie-designware.c:	Jingoo Han <jg1.han@samsung.com>
@@ -14,35 +17,56 @@
 #include <log.h>
 #include <malloc.h>
 #include <pci.h>
+#if CONFIG_IS_ENABLED(CLK)
+#include <clk.h>
+#else
 #include <asm/arch/clock.h>
+#endif
 #include <asm/arch/iomux.h>
+#ifdef CONFIG_MX6
 #include <asm/arch/crm_regs.h>
+#endif
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <dm.h>
 #include <linux/delay.h>
 #include <linux/sizes.h>
+#include <linux/ioport.h>
 #include <errno.h>
 #include <asm/arch/sys_proto.h>
+#include <syscon.h>
+#include <regmap.h>
+#include <asm-generic/gpio.h>
+#include <dt-bindings/soc/imx8_hsio.h>
+#include <power/regulator.h>
+#include <dm/device_compat.h>
+
+enum imx_pcie_variants {
+	IMX6Q,
+	IMX6SX,
+	IMX6QP,
+	IMX8QM,
+	IMX8QXP,
+};
 
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
 
 #ifdef CONFIG_MX6SX
 #define MX6_DBI_ADDR	0x08ffc000
-#define MX6_IO_ADDR	0x08000000
-#define MX6_MEM_ADDR	0x08100000
+#define MX6_IO_ADDR	0x08f80000
+#define MX6_MEM_ADDR	0x08000000
 #define MX6_ROOT_ADDR	0x08f00000
 #else
 #define MX6_DBI_ADDR	0x01ffc000
-#define MX6_IO_ADDR	0x01000000
-#define MX6_MEM_ADDR	0x01100000
+#define MX6_IO_ADDR	0x01f80000
+#define MX6_MEM_ADDR	0x01000000
 #define MX6_ROOT_ADDR	0x01f00000
 #endif
 #define MX6_DBI_SIZE	0x4000
-#define MX6_IO_SIZE	0x100000
-#define MX6_MEM_SIZE	0xe00000
-#define MX6_ROOT_SIZE	0xfc000
+#define MX6_IO_SIZE	0x10000
+#define MX6_MEM_SIZE	0xf00000
+#define MX6_ROOT_SIZE	0x80000
 
 /* PCIe Port Logic registers (memory-mapped) */
 #define PL_OFFSET 0x700
@@ -54,6 +78,22 @@
 #define PCIE_PHY_DEBUG_R1_LINK_UP		(1 << 4)
 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING	(1 << 29)
 
+#define PCIE_PORT_LINK_CONTROL		0x710
+#define PORT_LINK_MODE_MASK		(0x3f << 16)
+#define PORT_LINK_MODE_1_LANES		(0x1 << 16)
+#define PORT_LINK_MODE_2_LANES		(0x3 << 16)
+#define PORT_LINK_MODE_4_LANES		(0x7 << 16)
+#define PORT_LINK_MODE_8_LANES		(0xf << 16)
+
+
+#define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C
+#define PORT_LOGIC_SPEED_CHANGE		(0x1 << 17)
+#define PORT_LOGIC_LINK_WIDTH_MASK	(0x1f << 8)
+#define PORT_LOGIC_LINK_WIDTH_1_LANES	(0x1 << 8)
+#define PORT_LOGIC_LINK_WIDTH_2_LANES	(0x2 << 8)
+#define PORT_LOGIC_LINK_WIDTH_4_LANES	(0x4 << 8)
+#define PORT_LOGIC_LINK_WIDTH_8_LANES	(0x8 << 8)
+
 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
 #define PCIE_PHY_CTRL_DATA_LOC 0
 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
@@ -78,6 +118,7 @@
 #define PCIE_ATU_VIEWPORT		0x900
 #define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
 #define PCIE_ATU_REGION_OUTBOUND	(0x0 << 31)
+#define PCIE_ATU_REGION_INDEX2		(0x2 << 0)
 #define PCIE_ATU_REGION_INDEX1		(0x1 << 0)
 #define PCIE_ATU_REGION_INDEX0		(0x0 << 0)
 #define PCIE_ATU_CR1			0x904
@@ -97,11 +138,137 @@
 #define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
 #define PCIE_ATU_UPPER_TARGET		0x91C
 
+#define PCIE_MISC_CTRL			(PL_OFFSET + 0x1BC)
+#define PCIE_MISC_DBI_RO_WR_EN		BIT(0)
+
+/* iMX8 HSIO registers */
+#define IMX8QM_LPCG_PHYX2_OFFSET		0x00000
+#define IMX8QM_CSR_PHYX2_OFFSET			0x90000
+#define IMX8QM_CSR_PHYX1_OFFSET			0xA0000
+#define IMX8QM_CSR_PHYX_STTS0_OFFSET		0x4
+#define IMX8QM_CSR_PCIEA_OFFSET			0xB0000
+#define IMX8QM_CSR_PCIEB_OFFSET			0xC0000
+#define IMX8QM_CSR_PCIE_CTRL1_OFFSET		0x4
+#define IMX8QM_CSR_PCIE_CTRL2_OFFSET		0x8
+#define IMX8QM_CSR_PCIE_STTS0_OFFSET		0xC
+#define IMX8QM_CSR_MISC_OFFSET			0xE0000
+
+#define IMX8QM_LPCG_PHY_PCG0			BIT(1)
+#define IMX8QM_LPCG_PHY_PCG1			BIT(5)
+
+#define IMX8QM_CTRL_LTSSM_ENABLE		BIT(4)
+#define IMX8QM_CTRL_READY_ENTR_L23		BIT(5)
+#define IMX8QM_CTRL_PM_XMT_TURNOFF		BIT(9)
+#define IMX8QM_CTRL_BUTTON_RST_N		BIT(21)
+#define IMX8QM_CTRL_PERST_N			BIT(22)
+#define IMX8QM_CTRL_POWER_UP_RST_N		BIT(23)
+
+#define IMX8QM_CTRL_STTS0_PM_LINKST_IN_L2	BIT(13)
+#define IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST	BIT(19)
+#define IMX8QM_STTS0_LANE0_TX_PLL_LOCK		BIT(4)
+#define IMX8QM_STTS0_LANE1_TX_PLL_LOCK		BIT(12)
+
+#define IMX8QM_PCIE_TYPE_MASK			(0xF << 24)
+
+#define IMX8QM_PHYX2_CTRL0_APB_MASK		0x3
+#define IMX8QM_PHY_APB_RSTN_0			BIT(0)
+#define IMX8QM_PHY_APB_RSTN_1			BIT(1)
+
+#define IMX8QM_MISC_IOB_RXENA			BIT(0)
+#define IMX8QM_MISC_IOB_TXENA			BIT(1)
+#define IMX8QM_CSR_MISC_IOB_A_0_TXOE		BIT(2)
+#define IMX8QM_CSR_MISC_IOB_A_0_M1M0_MASK	(0x3 << 3)
+#define IMX8QM_CSR_MISC_IOB_A_0_M1M0_2		BIT(4)
+#define IMX8QM_MISC_PHYX1_EPCS_SEL		BIT(12)
+#define IMX8QM_MISC_PCIE_AB_SELECT		BIT(13)
+
+#define HW_PHYX2_CTRL0_PIPE_LN2LK_MASK	(0xF << 13)
+#define HW_PHYX2_CTRL0_PIPE_LN2LK_0	BIT(13)
+#define HW_PHYX2_CTRL0_PIPE_LN2LK_1	BIT(14)
+#define HW_PHYX2_CTRL0_PIPE_LN2LK_2	BIT(15)
+#define HW_PHYX2_CTRL0_PIPE_LN2LK_3	BIT(16)
+
+#define PHY_PLL_LOCK_WAIT_MAX_RETRIES	2000
+
+#ifdef DEBUG
+
+#ifdef DEBUG_STRESS_WR /* warm-reset stress tests */
+#define SNVS_LPGRP 0x020cc068
+#endif
+
+#define DBGF(x...) printf(x)
+
+static void print_regs(int contain_pcie_reg)
+{
+#ifdef CONFIG_MX6
+	u32 val;
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	val = readl(&iomuxc_regs->gpr[1]);
+	DBGF("GPR01 a:0x%08x v:0x%08x\n", (u32)&iomuxc_regs->gpr[1], val);
+	val = readl(&iomuxc_regs->gpr[5]);
+	DBGF("GPR05 a:0x%08x v:0x%08x\n", (u32)&iomuxc_regs->gpr[5], val);
+	val = readl(&iomuxc_regs->gpr[8]);
+	DBGF("GPR08 a:0x%08x v:0x%08x\n", (u32)&iomuxc_regs->gpr[8], val);
+	val = readl(&iomuxc_regs->gpr[12]);
+	DBGF("GPR12 a:0x%08x v:0x%08x\n", (u32)&iomuxc_regs->gpr[12], val);
+	val = readl(&ccm_regs->analog_pll_enet);
+	DBGF("PLL06 a:0x%08x v:0x%08x\n", (u32)&ccm_regs->analog_pll_enet, val);
+	val = readl(&ccm_regs->ana_misc1);
+	DBGF("MISC1 a:0x%08x v:0x%08x\n", (u32)&ccm_regs->ana_misc1, val);
+	if (contain_pcie_reg) {
+		val = readl(MX6_DBI_ADDR + 0x728);
+		DBGF("dbr0 offset 0x728 %08x\n", val);
+		val = readl(MX6_DBI_ADDR + 0x72c);
+		DBGF("dbr1 offset 0x72c %08x\n", val);
+	}
+#endif
+}
+#else
+#define DBGF(x...)
+static void print_regs(int contain_pcie_reg) {}
+#endif
+
 struct imx_pcie_priv {
 	void __iomem		*dbi_base;
 	void __iomem		*cfg_base;
-	struct gpio_desc	reset_gpio;
-	bool			reset_active_high;
+	void __iomem		*cfg1_base;
+	enum imx_pcie_variants variant;
+	struct regmap		*iomuxc_gpr;
+	u32					hsio_cfg;
+	u32					ctrl_id;
+	u32 					ext_osc;
+	u32					cpu_base;
+	u32 					lanes;
+	u32					cfg_size;
+	int					cpu_addr_offset;
+	struct gpio_desc 		clkreq_gpio;
+	struct gpio_desc 		dis_gpio;
+	struct gpio_desc 		reset_gpio;
+	struct gpio_desc 		power_on_gpio;
+
+	struct pci_region 		*io;
+	struct pci_region 		*mem;
+	struct pci_region 		*pref;
+
+#if CONFIG_IS_ENABLED(CLK)
+	struct clk			pcie_bus;
+	struct clk			pcie_phy;
+	struct clk			pcie_phy_pclk;
+	struct clk			pcie_inbound_axi;
+	struct clk			pcie_per;
+	struct clk			pciex2_per;
+	struct clk			phy_per;
+	struct clk			misc_per;
+	struct clk			pcie;
+	struct clk			pcie_ext_src;
+#endif
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+	struct udevice 		*epdev_on;
+	struct udevice 		*pcie_bus_regulator;
+	struct udevice 		*pcie_phy_regulator;
+#endif
 };
 
 /*
@@ -237,6 +404,16 @@ static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
 	return 0;
 }
 
+void imx_pcie_gpr_read(struct imx_pcie_priv *priv, uint offset, uint *valp)
+{
+	regmap_read(priv->iomuxc_gpr, offset, valp);
+}
+
+void imx_pcie_gpr_update_bits(struct imx_pcie_priv *priv, uint offset, uint mask, uint val)
+{
+	regmap_update_bits(priv->iomuxc_gpr, offset, mask, val);
+}
+
 static int imx6_pcie_link_up(struct imx_pcie_priv *priv)
 {
 	u32 rc, ltssm;
@@ -279,45 +456,122 @@ static int imx6_pcie_link_up(struct imx_pcie_priv *priv)
 	return 0;
 }
 
-/*
- * iATU region setup
- */
-static int imx_pcie_regions_setup(struct imx_pcie_priv *priv)
+/* Fix class value */
+static void imx_pcie_fix_class(struct imx_pcie_priv *priv)
 {
-	/*
-	 * i.MX6 defines 16MB in the AXI address map for PCIe.
-	 *
-	 * That address space excepted the pcie registers is
-	 * split and defined into different regions by iATU,
-	 * with sizes and offsets as follows:
-	 *
-	 * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO
-	 * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM
-	 * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers
-	 */
+	writew(PCI_CLASS_BRIDGE_PCI, priv->dbi_base + PCI_CLASS_DEVICE);
+}
 
-	/* CMD reg:I/O space, MEM space, and Bus Master Enable */
-	setbits_le32(priv->dbi_base + PCI_COMMAND,
-		     PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+/* Clear multi-function bit */
+static void imx_pcie_clear_multifunction(struct imx_pcie_priv *priv)
+{
+	writeb(PCI_HEADER_TYPE_BRIDGE, priv->dbi_base + PCI_HEADER_TYPE);
+}
 
-	/* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
-	setbits_le32(priv->dbi_base + PCI_CLASS_REVISION,
-		     PCI_CLASS_BRIDGE_PCI << 16);
+static void imx_pcie_setup_ctrl(struct imx_pcie_priv *priv)
+{
+	u32 val;
+
+	writel(PCIE_MISC_DBI_RO_WR_EN, priv->dbi_base + PCIE_MISC_CTRL);
+
+	/* Set the number of lanes */
+	val = readl(priv->dbi_base + PCIE_PORT_LINK_CONTROL);
+	val &= ~PORT_LINK_MODE_MASK;
+	switch (priv->lanes) {
+	case 1:
+		val |= PORT_LINK_MODE_1_LANES;
+		break;
+	case 2:
+		val |= PORT_LINK_MODE_2_LANES;
+		break;
+	case 4:
+		val |= PORT_LINK_MODE_4_LANES;
+		break;
+	case 8:
+		val |= PORT_LINK_MODE_8_LANES;
+		break;
+	default:
+		printf("num-lanes %u: invalid value\n", priv->lanes);
+		return;
+	}
+	writel(val, priv->dbi_base + PCIE_PORT_LINK_CONTROL);
+
+	/* Set link width speed control register */
+	val = readl(priv->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
+	val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
+	switch (priv->lanes) {
+	case 1:
+		val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
+		break;
+	case 2:
+		val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
+		break;
+	case 4:
+		val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
+		break;
+	case 8:
+		val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
+		break;
+	}
+	writel(val, priv->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
 
-	/* Region #0 is used for Outbound CFG space access. */
-	writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
+	/* setup RC BARs */
+	writel(0, priv->dbi_base + PCI_BASE_ADDRESS_0);
+	writel(0, priv->dbi_base + PCI_BASE_ADDRESS_1);
 
-	writel(lower_32_bits((uintptr_t)priv->cfg_base),
-	       priv->dbi_base + PCIE_ATU_LOWER_BASE);
-	writel(upper_32_bits((uintptr_t)priv->cfg_base),
-	       priv->dbi_base + PCIE_ATU_UPPER_BASE);
-	writel(lower_32_bits((uintptr_t)priv->cfg_base + MX6_ROOT_SIZE),
-	       priv->dbi_base + PCIE_ATU_LIMIT);
+	/* setup bus numbers */
+	val = readl(priv->dbi_base + PCI_PRIMARY_BUS);
+	val &= 0xff000000;
+	val |= 0x00ff0100;
+	writel(val, priv->dbi_base + PCI_PRIMARY_BUS);
 
-	writel(0, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
-	writel(0, priv->dbi_base + PCIE_ATU_UPPER_TARGET);
-	writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
+	/* setup command register */
+	val = readl(priv->dbi_base + PCI_COMMAND);
+	val &= 0xffff0000;
+	val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+		PCI_COMMAND_MASTER;
+	writel(val, priv->dbi_base + PCI_COMMAND);
+
+	imx_pcie_fix_class(priv);
+	imx_pcie_clear_multifunction(priv);
+
+	writel(0, priv->dbi_base + PCIE_MISC_CTRL);
+}
+
+static void imx_pcie_atu_outbound_set(struct imx_pcie_priv *priv, int idx, int type,
+				      u64 phys, u64 bus_addr, u32 size)
+{
+	writel(PCIE_ATU_REGION_OUTBOUND | idx, priv->dbi_base + PCIE_ATU_VIEWPORT);
+	writel((u32)(phys + priv->cpu_addr_offset), priv->dbi_base + PCIE_ATU_LOWER_BASE);
+	writel((phys + priv->cpu_addr_offset) >> 32, priv->dbi_base + PCIE_ATU_UPPER_BASE);
+	writel((u32)(phys + priv->cpu_addr_offset) + size - 1, priv->dbi_base + PCIE_ATU_LIMIT);
+	writel((u32)bus_addr, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
+	writel(bus_addr >> 32, priv->dbi_base + PCIE_ATU_UPPER_TARGET);
+	writel(type, priv->dbi_base + PCIE_ATU_CR1);
 	writel(PCIE_ATU_ENABLE, priv->dbi_base + PCIE_ATU_CR2);
+}
+
+/*
+ * iATU region setup
+ */
+static int imx_pcie_regions_setup(struct imx_pcie_priv *priv)
+{
+	if (priv->io)
+		/* ATU : OUTBOUND : IO */
+		imx_pcie_atu_outbound_set(priv, PCIE_ATU_REGION_INDEX2,
+					 PCIE_ATU_TYPE_IO,
+					 priv->io->phys_start,
+					 priv->io->bus_start,
+					 priv->io->size);
+
+	if (priv->mem)
+		/* ATU : OUTBOUND : MEM */
+		imx_pcie_atu_outbound_set(priv, PCIE_ATU_REGION_INDEX0,
+					 PCIE_ATU_TYPE_MEM,
+					 priv->mem->phys_start,
+					 priv->mem->bus_start,
+					 priv->mem->size);
+
 
 	return 0;
 }
@@ -330,30 +584,40 @@ static void __iomem *get_bus_address(struct imx_pcie_priv *priv,
 {
 	void __iomem *va_address;
 
-	/* Reconfigure Region #0 */
-	writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
-
-	if (PCI_BUS(d) < 2)
-		writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1);
-	else
-		writel(PCIE_ATU_TYPE_CFG1, priv->dbi_base + PCIE_ATU_CR1);
-
 	if (PCI_BUS(d) == 0) {
+		/* Outbound TLP matched primary interface of the bridge */
 		va_address = priv->dbi_base;
 	} else {
-		writel(d << 8, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
-		va_address = priv->cfg_base;
+		if (PCI_BUS(d) < 2) {
+			/* Outbound TLP matched secondary interface of the bridge changes to CFG0 */
+			imx_pcie_atu_outbound_set(priv, PCIE_ATU_REGION_INDEX1,
+					 PCIE_ATU_TYPE_CFG0,
+					 (ulong)priv->cfg_base,
+					 (u64)d << 8,
+					 priv->cfg_size >> 1);
+			va_address = priv->cfg_base;
+		} else {
+			/* Outbound TLP matched the bus behind the bridge uses type CFG1 */
+			imx_pcie_atu_outbound_set(priv, PCIE_ATU_REGION_INDEX1,
+					 PCIE_ATU_TYPE_CFG1,
+					 (ulong)priv->cfg1_base,
+					 (u64)d << 8,
+					 priv->cfg_size >> 1);
+			va_address = priv->cfg1_base;
+		}
 	}
 
 	va_address += (where & ~0x3);
 
 	return va_address;
+
 }
 
 static int imx_pcie_addr_valid(pci_dev_t d)
 {
-	if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1))
+	if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 0))
 		return -EINVAL;
+	/* ARI forward is not enabled, so non-zero device at downstream must be blocked */
 	if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0))
 		return -EINVAL;
 	return 0;
@@ -374,6 +638,7 @@ static int imx_pcie_addr_valid(pci_dev_t d)
  */
 static void imx_pcie_fix_dabt_handler(bool set)
 {
+#ifdef CONFIG_MX6
 	extern uint32_t *_data_abort;
 	uint32_t *data_abort_addr = (uint32_t *)&_data_abort;
 
@@ -388,6 +653,7 @@ static void imx_pcie_fix_dabt_handler(bool set)
 	} else {
 		*data_abort_addr = data_abort_backup;
 	}
+#endif
 }
 
 static int imx_pcie_read_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
@@ -443,27 +709,427 @@ static int imx_pcie_write_cfg(struct imx_pcie_priv *priv, pci_dev_t d,
 	return 0;
 }
 
+__weak int imx_pcie_toggle_reset(struct gpio_desc *gpio)
+{
+	/*
+	 * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
+	 * for detailed understanding of the PCIe CR reset logic.
+	 *
+	 * The PCIe #PERST reset line _MUST_ be connected, otherwise your
+	 * design does not conform to the specification. You must wait at
+	 * least 20 ms after de-asserting the #PERST so the EP device can
+	 * do self-initialisation.
+	 *
+	 * In case your #PERST pin is connected to a plain GPIO pin of the
+	 * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's
+	 * configuration file and the condition below will handle the rest
+	 * of the reset toggling.
+	 *
+	 * In case your #PERST toggling logic is more complex, for example
+	 * connected via CPLD or somesuch, you can override this function
+	 * in your board file and implement reset logic as needed. You must
+	 * not forget to wait at least 20 ms after de-asserting #PERST in
+	 * this case either though.
+	 *
+	 * In case your #PERST line of the PCIe EP device is not connected
+	 * at all, your design is broken and you should fix your design,
+	 * otherwise you will observe problems like for example the link
+	 * not coming up after rebooting the system back from running Linux
+	 * that uses the PCIe as well OR the PCIe link might not come up in
+	 * Linux at all in the first place since it's in some non-reset
+	 * state due to being previously used in U-Boot.
+	 */
+#ifdef CONFIG_PCIE_IMX_PERST_GPIO
+	gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset");
+	gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
+	mdelay(20);
+	gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
+	mdelay(20);
+	gpio_free(CONFIG_PCIE_IMX_PERST_GPIO);
+#else
+	if (dm_gpio_is_valid(gpio)) {
+		/* Assert PERST# for 20ms then de-assert */
+		dm_gpio_set_value(gpio, 1);
+		mdelay(20);
+		dm_gpio_set_value(gpio, 0);
+		mdelay(20);
+	} else {
+		puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
+	}
+#endif
+
+	return 0;
+}
+
+static int imx8_pcie_assert_core_reset(struct imx_pcie_priv *priv,
+				       bool prepare_for_boot)
+{
+	u32 val;
+
+	switch (priv->variant) {
+	case IMX8QXP:
+			val = IMX8QM_CSR_PCIEB_OFFSET;
+			imx_pcie_gpr_update_bits(priv,
+					val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
+					IMX8QM_CTRL_BUTTON_RST_N,
+					IMX8QM_CTRL_BUTTON_RST_N);
+			imx_pcie_gpr_update_bits(priv,
+					val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
+					IMX8QM_CTRL_PERST_N,
+					IMX8QM_CTRL_PERST_N);
+			imx_pcie_gpr_update_bits(priv,
+					val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
+					IMX8QM_CTRL_POWER_UP_RST_N,
+					IMX8QM_CTRL_POWER_UP_RST_N);
+		break;
+	case IMX8QM:
+			val = IMX8QM_CSR_PCIEA_OFFSET + priv->ctrl_id * SZ_64K;
+			imx_pcie_gpr_update_bits(priv,
+					val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
+					IMX8QM_CTRL_BUTTON_RST_N,
+					IMX8QM_CTRL_BUTTON_RST_N);
+			imx_pcie_gpr_update_bits(priv,
+					val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
+					IMX8QM_CTRL_PERST_N,
+					IMX8QM_CTRL_PERST_N);
+			imx_pcie_gpr_update_bits(priv,
+					val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
+					IMX8QM_CTRL_POWER_UP_RST_N,
+					IMX8QM_CTRL_POWER_UP_RST_N);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int imx8_pcie_init_phy(struct imx_pcie_priv *priv)
+{
+	u32 tmp, val;
+
+	if (priv->variant == IMX8QM
+		|| priv->variant == IMX8QXP) {
+		switch (priv->hsio_cfg) {
+		case PCIEAX2SATA:
+			/*
+			 * bit 0 rx ena 1.
+			 * bit12 PHY_X1_EPCS_SEL 1.
+			 * bit13 phy_ab_select 0.
+			 */
+			imx_pcie_gpr_update_bits(priv,
+				IMX8QM_CSR_PHYX2_OFFSET,
+				IMX8QM_PHYX2_CTRL0_APB_MASK,
+				IMX8QM_PHY_APB_RSTN_0
+				| IMX8QM_PHY_APB_RSTN_1);
+
+			imx_pcie_gpr_update_bits(priv,
+				IMX8QM_CSR_MISC_OFFSET,
+				IMX8QM_MISC_PHYX1_EPCS_SEL,
+				IMX8QM_MISC_PHYX1_EPCS_SEL);
+			imx_pcie_gpr_update_bits(priv,
+				IMX8QM_CSR_MISC_OFFSET,
+				IMX8QM_MISC_PCIE_AB_SELECT,
+				0);
+			break;
+
+		case PCIEAX1PCIEBX1SATA:
+			tmp = IMX8QM_PHY_APB_RSTN_1;
+			tmp |= IMX8QM_PHY_APB_RSTN_0;
+			imx_pcie_gpr_update_bits(priv,
+				IMX8QM_CSR_PHYX2_OFFSET,
+				IMX8QM_PHYX2_CTRL0_APB_MASK, tmp);
+
+			imx_pcie_gpr_update_bits(priv,
+				IMX8QM_CSR_MISC_OFFSET,
+				IMX8QM_MISC_PHYX1_EPCS_SEL,
+				IMX8QM_MISC_PHYX1_EPCS_SEL);
+			imx_pcie_gpr_update_bits(priv,
+				IMX8QM_CSR_MISC_OFFSET,
+				IMX8QM_MISC_PCIE_AB_SELECT,
+				IMX8QM_MISC_PCIE_AB_SELECT);
+
+			imx_pcie_gpr_update_bits(priv,
+				IMX8QM_CSR_PHYX2_OFFSET,
+				HW_PHYX2_CTRL0_PIPE_LN2LK_MASK,
+				HW_PHYX2_CTRL0_PIPE_LN2LK_3 | HW_PHYX2_CTRL0_PIPE_LN2LK_0);
+
+			break;
+
+		case PCIEAX2PCIEBX1:
+			/*
+			 * bit 0 rx ena 1.
+			 * bit12 PHY_X1_EPCS_SEL 0.
+			 * bit13 phy_ab_select 1.
+			 */
+			if (priv->ctrl_id)
+				imx_pcie_gpr_update_bits(priv,
+					IMX8QM_CSR_PHYX1_OFFSET,
+					IMX8QM_PHY_APB_RSTN_0,
+					IMX8QM_PHY_APB_RSTN_0);
+			else
+				imx_pcie_gpr_update_bits(priv,
+					IMX8QM_CSR_PHYX2_OFFSET,
+					IMX8QM_PHYX2_CTRL0_APB_MASK,
+					IMX8QM_PHY_APB_RSTN_0
+					| IMX8QM_PHY_APB_RSTN_1);
+
+			imx_pcie_gpr_update_bits(priv,
+				IMX8QM_CSR_MISC_OFFSET,
+				IMX8QM_MISC_PHYX1_EPCS_SEL,
+				0);
+			imx_pcie_gpr_update_bits(priv,
+				IMX8QM_CSR_MISC_OFFSET,
+				IMX8QM_MISC_PCIE_AB_SELECT,
+				IMX8QM_MISC_PCIE_AB_SELECT);
+			break;
+		}
+
+		if (priv->ext_osc) {
+			imx_pcie_gpr_update_bits(priv,
+				IMX8QM_CSR_MISC_OFFSET,
+				IMX8QM_MISC_IOB_RXENA,
+				IMX8QM_MISC_IOB_RXENA);
+			imx_pcie_gpr_update_bits(priv,
+				IMX8QM_CSR_MISC_OFFSET,
+				IMX8QM_MISC_IOB_TXENA,
+				0);
+		} else {
+			/* Try to used the internal pll as ref clk */
+			imx_pcie_gpr_update_bits(priv,
+				IMX8QM_CSR_MISC_OFFSET,
+				IMX8QM_MISC_IOB_RXENA,
+				0);
+			imx_pcie_gpr_update_bits(priv,
+				IMX8QM_CSR_MISC_OFFSET,
+				IMX8QM_MISC_IOB_TXENA,
+				IMX8QM_MISC_IOB_TXENA);
+			imx_pcie_gpr_update_bits(priv,
+				IMX8QM_CSR_MISC_OFFSET,
+				IMX8QM_CSR_MISC_IOB_A_0_TXOE
+				| IMX8QM_CSR_MISC_IOB_A_0_M1M0_MASK,
+				IMX8QM_CSR_MISC_IOB_A_0_TXOE
+				| IMX8QM_CSR_MISC_IOB_A_0_M1M0_2);
+		}
+
+		val = IMX8QM_CSR_PCIEA_OFFSET
+			+ priv->ctrl_id * SZ_64K;
+		imx_pcie_gpr_update_bits(priv,
+				val, IMX8QM_PCIE_TYPE_MASK,
+				0x4 << 24);
+
+		mdelay(10);
+	}
+
+	return 0;
+}
+
+static int imx8_pcie_wait_for_phy_pll_lock(struct imx_pcie_priv *priv)
+{
+	u32 val, tmp, orig;
+	unsigned int retries = 0;
+
+	if (priv->variant == IMX8QXP
+			|| priv->variant == IMX8QM) {
+		for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES;
+				retries++) {
+			if (priv->hsio_cfg == PCIEAX1PCIEBX1SATA) {
+				imx_pcie_gpr_read(priv,
+					    IMX8QM_CSR_PHYX2_OFFSET + 0x4,
+					    &tmp);
+				if (priv->ctrl_id == 0) /* pciea 1 lanes */
+					orig = IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
+				else /* pcieb 1 lanes */
+					orig = IMX8QM_STTS0_LANE1_TX_PLL_LOCK;
+				tmp &= orig;
+				if (tmp == orig) {
+					imx_pcie_gpr_update_bits(priv,
+						IMX8QM_LPCG_PHYX2_OFFSET,
+						IMX8QM_LPCG_PHY_PCG0
+						| IMX8QM_LPCG_PHY_PCG1,
+						IMX8QM_LPCG_PHY_PCG0
+						| IMX8QM_LPCG_PHY_PCG1);
+					break;
+				}
+			}
+
+			if (priv->hsio_cfg == PCIEAX2PCIEBX1) {
+				val = IMX8QM_CSR_PHYX2_OFFSET
+					+ priv->ctrl_id * SZ_64K;
+				imx_pcie_gpr_read(priv,
+					    val + IMX8QM_CSR_PHYX_STTS0_OFFSET,
+					    &tmp);
+				orig = IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
+				if (priv->ctrl_id == 0) /* pciea 2 lanes */
+					orig |= IMX8QM_STTS0_LANE1_TX_PLL_LOCK;
+				tmp &= orig;
+				if (tmp == orig) {
+					val = IMX8QM_CSR_PHYX2_OFFSET
+						+ priv->ctrl_id * SZ_64K;
+					imx_pcie_gpr_update_bits(priv,
+						val, IMX8QM_LPCG_PHY_PCG0,
+						IMX8QM_LPCG_PHY_PCG0);
+					break;
+				}
+			}
+			udelay(10);
+		}
+	}
+
+	if (retries >= PHY_PLL_LOCK_WAIT_MAX_RETRIES) {
+		printf("pcie phy pll can't be locked.\n");
+		return -ENODEV;
+	} else {
+		debug("pcie phy pll is locked.\n");
+		return 0;
+	}
+}
+
+static int imx8_pcie_deassert_core_reset(struct imx_pcie_priv *priv)
+{
+	int ret, i;
+	u32 val, tmp;
+
+#if CONFIG_IS_ENABLED(CLK)
+	ret = clk_enable(&priv->pcie);
+	if (ret) {
+		printf("unable to enable pcie clock\n");
+		return ret;
+	}
+
+	ret = clk_enable(&priv->pcie_phy);
+	if (ret) {
+		printf("unable to enable pcie_phy clock\n");
+		goto err_pcie;
+	}
+
+	ret = clk_enable(&priv->pcie_bus);
+	if (ret) {
+		printf("unable to enable pcie_bus clock\n");
+		goto err_pcie_phy;
+	}
+
+	ret = clk_enable(&priv->pcie_inbound_axi);
+	if (ret) {
+		printf("unable to enable pcie_axi clock\n");
+		goto err_pcie_bus;
+	}
+	ret = clk_enable(&priv->pcie_per);
+	if (ret) {
+		printf("unable to enable pcie_per clock\n");
+		goto err_pcie_inbound_axi;
+	}
+
+	ret = clk_enable(&priv->phy_per);
+	if (ret) {
+		printf("unable to enable phy_per clock\n");
+		goto err_pcie_per;
+	}
+
+	ret = clk_enable(&priv->misc_per);
+	if (ret) {
+		printf("unable to enable misc_per clock\n");
+		goto err_phy_per;
+	}
+
+	if (priv->variant == IMX8QM && priv->ctrl_id == 1) {
+		ret = clk_enable(&priv->pcie_phy_pclk);
+		if (ret) {
+			printf("unable to enable pcie_phy_pclk clock\n");
+			goto err_misc_per;
+		}
+
+		ret = clk_enable(&priv->pciex2_per);
+		if (ret) {
+			printf("unable to enable pciex2_per clock\n");
+			clk_disable(&priv->pcie_phy_pclk);
+			goto err_misc_per;
+		}
+	}
+#endif
+	/* allow the clocks to stabilize */
+	udelay(200);
+
+	/* bit19 PM_REQ_CORE_RST of pciex#_stts0 should be cleared. */
+	for (i = 0; i < 100; i++) {
+		val = IMX8QM_CSR_PCIEA_OFFSET
+			+ priv->ctrl_id * SZ_64K;
+		imx_pcie_gpr_read(priv,
+				val + IMX8QM_CSR_PCIE_STTS0_OFFSET,
+				&tmp);
+		if ((tmp & IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST) == 0)
+			break;
+		udelay(10);
+	}
+
+	if ((tmp & IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST) != 0)
+		printf("ERROR PM_REQ_CORE_RST is still set.\n");
+
+	/* wait for phy pll lock firstly. */
+	if (imx8_pcie_wait_for_phy_pll_lock(priv)) {
+		ret = -ENODEV;
+		goto err_ref_clk;;
+	}
+
+	if (dm_gpio_is_valid(&priv->reset_gpio)) {
+		dm_gpio_set_value(&priv->reset_gpio, 1);
+		mdelay(20);
+		dm_gpio_set_value(&priv->reset_gpio, 0);
+		mdelay(20);
+	}
+
+	return 0;
+
+err_ref_clk:
+#if CONFIG_IS_ENABLED(CLK)
+	if (priv->variant == IMX8QM && priv->ctrl_id == 1) {
+		clk_disable(&priv->pciex2_per);
+		clk_disable(&priv->pcie_phy_pclk);
+	}
+err_misc_per:
+	clk_disable(&priv->misc_per);
+err_phy_per:
+	clk_disable(&priv->phy_per);
+err_pcie_per:
+	clk_disable(&priv->pcie_per);
+err_pcie_inbound_axi:
+	clk_disable(&priv->pcie_inbound_axi);
+err_pcie_bus:
+	clk_disable(&priv->pcie_bus);
+err_pcie_phy:
+	clk_disable(&priv->pcie_phy);
+err_pcie:
+	clk_disable(&priv->pcie);
+#endif
+
+	return ret;
+}
+
+#ifdef CONFIG_MX6
 /*
  * Initial bus setup
  */
 static int imx6_pcie_assert_core_reset(struct imx_pcie_priv *priv,
 				       bool prepare_for_boot)
 {
-	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	if (is_mx6dqp())
-		setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
+	if (priv->variant == IMX6QP)
+		imx_pcie_gpr_update_bits(priv, 4, IOMUXC_GPR1_PCIE_SW_RST, IOMUXC_GPR1_PCIE_SW_RST);
 
 #if defined(CONFIG_MX6SX)
-	struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
-
-	/* SSP_EN is not used on MX6SX anymore */
-	setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
-	/* Force PCIe PHY reset */
-	setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
-	/* Power up PCIe PHY */
-	setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
-#else
+	if (priv->variant == IMX6SX) {
+		struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
+
+		/* SSP_EN is not used on MX6SX anymore */
+		imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_TEST_POWERDOWN, IOMUXC_GPR12_TEST_POWERDOWN);
+		/* Force PCIe PHY reset */
+		imx_pcie_gpr_update_bits(priv, 20, IOMUXC_GPR5_PCIE_BTNRST, IOMUXC_GPR5_PCIE_BTNRST);
+		/* Power up PCIe PHY */
+		setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
+		pcie_power_up();
+
+		return 0;
+	}
+#endif
 	/*
 	 * If the bootloader already enabled the link we need some special
 	 * handling to get the core back into a state where it is safe to
@@ -475,11 +1141,11 @@ static int imx6_pcie_assert_core_reset(struct imx_pcie_priv *priv,
 	 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
 	 * indication that the bootloader activated the link.
 	 */
-	if ((is_mx6dq() || is_mx6sdl()) && prepare_for_boot) {
+	if (priv->variant == IMX6Q && prepare_for_boot) {
 		u32 val, gpr1, gpr12;
 
-		gpr1 = readl(&iomuxc_regs->gpr[1]);
-		gpr12 = readl(&iomuxc_regs->gpr[12]);
+		imx_pcie_gpr_read(priv, 4, &gpr1);
+		imx_pcie_gpr_read(priv, 48, &gpr12);
 		if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) &&
 		    (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) {
 			val = readl(priv->dbi_base + PCIE_PL_PFLR);
@@ -490,42 +1156,44 @@ static int imx6_pcie_assert_core_reset(struct imx_pcie_priv *priv,
 			writel(val, priv->dbi_base + PCIE_PL_PFLR);
 			imx_pcie_fix_dabt_handler(false);
 
-			gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2;
-			writel(val, &iomuxc_regs->gpr[12]);
+			imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_PCIE_CTL_2, 0);
 		}
 	}
-	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
-	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
-#endif
+
+	if (priv->variant == IMX6QP || priv->variant == IMX6Q) {
+		imx_pcie_gpr_update_bits(priv, 4, IOMUXC_GPR1_TEST_POWERDOWN,
+			IOMUXC_GPR1_TEST_POWERDOWN);
+		imx_pcie_gpr_update_bits(priv, 4, IOMUXC_GPR1_REF_SSP_EN, 0);
+	}
 
 	return 0;
 }
 
-static int imx6_pcie_init_phy(void)
+static int imx6_pcie_init_phy(struct imx_pcie_priv *priv)
 {
-	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
+#ifndef DEBUG
+	imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_APPS_LTSSM_ENABLE, 0);
+#endif
 
-	clrsetbits_le32(&iomuxc_regs->gpr[12],
+	imx_pcie_gpr_update_bits(priv, 48,
 			IOMUXC_GPR12_DEVICE_TYPE_MASK,
 			IOMUXC_GPR12_DEVICE_TYPE_RC);
-	clrsetbits_le32(&iomuxc_regs->gpr[12],
+	imx_pcie_gpr_update_bits(priv, 48,
 			IOMUXC_GPR12_LOS_LEVEL_MASK,
 			IOMUXC_GPR12_LOS_LEVEL_9);
 
-#ifdef CONFIG_MX6SX
-	clrsetbits_le32(&iomuxc_regs->gpr[12],
-			IOMUXC_GPR12_RX_EQ_MASK,
-			IOMUXC_GPR12_RX_EQ_2);
-#endif
+	if (priv->variant == IMX6SX) {
+		imx_pcie_gpr_update_bits(priv, 48,
+				IOMUXC_GPR12_RX_EQ_MASK,
+				IOMUXC_GPR12_RX_EQ_2);
+	}
 
-	writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
+	imx_pcie_gpr_update_bits(priv, 32, 0xffffffff,
+		(0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) |
 	       (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) |
 	       (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) |
 	       (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) |
-	       (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET),
-	       &iomuxc_regs->gpr[8]);
+	       (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET));
 
 	return 0;
 }
@@ -543,67 +1211,14 @@ __weak int imx6_pcie_toggle_power(void)
 	return 0;
 }
 
-__weak int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high)
-{
-	/*
-	 * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
-	 * for detailed understanding of the PCIe CR reset logic.
-	 *
-	 * The PCIe #PERST reset line _MUST_ be connected, otherwise your
-	 * design does not conform to the specification. You must wait at
-	 * least 20 ms after de-asserting the #PERST so the EP device can
-	 * do self-initialisation.
-	 *
-	 * In case your #PERST pin is connected to a plain GPIO pin of the
-	 * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's
-	 * configuration file and the condition below will handle the rest
-	 * of the reset toggling.
-	 *
-	 * In case your #PERST toggling logic is more complex, for example
-	 * connected via CPLD or somesuch, you can override this function
-	 * in your board file and implement reset logic as needed. You must
-	 * not forget to wait at least 20 ms after de-asserting #PERST in
-	 * this case either though.
-	 *
-	 * In case your #PERST line of the PCIe EP device is not connected
-	 * at all, your design is broken and you should fix your design,
-	 * otherwise you will observe problems like for example the link
-	 * not coming up after rebooting the system back from running Linux
-	 * that uses the PCIe as well OR the PCIe link might not come up in
-	 * Linux at all in the first place since it's in some non-reset
-	 * state due to being previously used in U-Boot.
-	 */
-#ifdef CONFIG_PCIE_IMX_PERST_GPIO
-	gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "pcie_reset");
-	gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO, 0);
-	mdelay(20);
-	gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO, 1);
-	mdelay(20);
-	gpio_free(CONFIG_PCIE_IMX_PERST_GPIO);
-#else
-	if (dm_gpio_is_valid(gpio)) {
-		/* Assert PERST# for 20ms then de-assert */
-		dm_gpio_set_value(gpio, active_high ? 0 : 1);
-		mdelay(20);
-		dm_gpio_set_value(gpio, active_high ? 1 : 0);
-		mdelay(20);
-	} else {
-		puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
-	}
-#endif
-	return 0;
-}
-
 static int imx6_pcie_deassert_core_reset(struct imx_pcie_priv *priv)
 {
-	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
 	imx6_pcie_toggle_power();
 
 	enable_pcie_clock();
 
-	if (is_mx6dqp())
-		clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
+	if (priv->variant == IMX6QP)
+		imx_pcie_gpr_update_bits(priv, 4, IOMUXC_GPR1_PCIE_SW_RST, 0);
 
 	/*
 	 * Wait for the clock to settle a bit, when the clock are sourced
@@ -611,32 +1226,126 @@ static int imx6_pcie_deassert_core_reset(struct imx_pcie_priv *priv)
 	 */
 	mdelay(50);
 
-#if defined(CONFIG_MX6SX)
-	/* SSP_EN is not used on MX6SX anymore */
-	clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
-	/* Clear PCIe PHY reset bit */
-	clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
-#else
-	/* Enable PCIe */
-	clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN);
-	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN);
-#endif
+	if (priv->variant == IMX6SX) {
+		/* SSP_EN is not used on MX6SX anymore */
+		imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_TEST_POWERDOWN, 0);
+		/* Clear PCIe PHY reset bit */
+		imx_pcie_gpr_update_bits(priv, 20, IOMUXC_GPR5_PCIE_BTNRST, 0);
+	} else {
+		/* Enable PCIe */
+		imx_pcie_gpr_update_bits(priv, 4, IOMUXC_GPR1_TEST_POWERDOWN, 0);
+		imx_pcie_gpr_update_bits(priv, 4, IOMUXC_GPR1_REF_SSP_EN, IOMUXC_GPR1_REF_SSP_EN);
+	}
 
-	imx6_pcie_toggle_reset(&priv->reset_gpio, priv->reset_active_high);
+	imx_pcie_toggle_reset(&priv->reset_gpio);
 
 	return 0;
 }
+#endif
+
+static int imx_pcie_assert_core_reset(struct imx_pcie_priv *priv,
+				       bool prepare_for_boot)
+{
+	switch (priv->variant) {
+#ifdef CONFIG_MX6
+	case IMX6Q:
+	case IMX6QP:
+	case IMX6SX:
+		return imx6_pcie_assert_core_reset(priv, prepare_for_boot);
+#endif
+	case IMX8QM:
+	case IMX8QXP:
+		return imx8_pcie_assert_core_reset(priv, prepare_for_boot);
+	default:
+		return -EPERM;
+	}
+}
+
+static int imx_pcie_init_phy(struct imx_pcie_priv *priv)
+{
+	switch (priv->variant) {
+#ifdef CONFIG_MX6
+	case IMX6Q:
+	case IMX6QP:
+	case IMX6SX:
+		return imx6_pcie_init_phy(priv);
+#endif
+	case IMX8QM:
+	case IMX8QXP:
+		return imx8_pcie_init_phy(priv);
+	default:
+		return -EPERM;
+	}
+}
+
+static int imx_pcie_deassert_core_reset(struct imx_pcie_priv *priv)
+{
+	switch (priv->variant) {
+#ifdef CONFIG_MX6
+	case IMX6Q:
+	case IMX6QP:
+	case IMX6SX:
+		return imx6_pcie_deassert_core_reset(priv);
+#endif
+	case IMX8QM:
+	case IMX8QXP:
+		return imx8_pcie_deassert_core_reset(priv);
+	default:
+		return -EPERM;
+	}
+}
+
+static void imx_pcie_ltssm_enable(struct imx_pcie_priv *priv, bool enable)
+{
+	u32 val;
+
+	switch (priv->variant) {
+#ifdef CONFIG_MX6
+	case IMX6Q:
+	case IMX6SX:
+	case IMX6QP:
+		if (enable)
+			imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_APPS_LTSSM_ENABLE,
+				IOMUXC_GPR12_APPS_LTSSM_ENABLE); /* LTSSM enable, starting link. */
+		else
+			imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_APPS_LTSSM_ENABLE, 0);
+
+		break;
+#endif
+	case IMX8QXP:
+	case IMX8QM:
+		/* Bit4 of the CTRL2 */
+		val = IMX8QM_CSR_PCIEA_OFFSET
+			+ priv->ctrl_id * SZ_64K;
+		if (enable) {
+			imx_pcie_gpr_update_bits(priv,
+				val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
+				IMX8QM_CTRL_LTSSM_ENABLE,
+				IMX8QM_CTRL_LTSSM_ENABLE);
+		} else {
+			imx_pcie_gpr_update_bits(priv,
+				val + IMX8QM_CSR_PCIE_CTRL2_OFFSET,
+				IMX8QM_CTRL_LTSSM_ENABLE,
+				0);
+		}
+		break;
+	default:
+		break;
+	}
+
+}
+
 
 static int imx_pcie_link_up(struct imx_pcie_priv *priv)
 {
-	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	uint32_t tmp;
 	int count = 0;
 
-	imx6_pcie_assert_core_reset(priv, false);
-	imx6_pcie_init_phy();
-	imx6_pcie_deassert_core_reset(priv);
+	imx_pcie_assert_core_reset(priv, false);
+	imx_pcie_init_phy(priv);
+	imx_pcie_deassert_core_reset(priv);
 
+	imx_pcie_setup_ctrl(priv);
 	imx_pcie_regions_setup(priv);
 
 	/*
@@ -662,11 +1371,28 @@ static int imx_pcie_link_up(struct imx_pcie_priv *priv)
 	writel(tmp, priv->dbi_base + 0x7c);
 
 	/* LTSSM enable, starting link. */
-	setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE);
+	imx_pcie_ltssm_enable(priv, true);
 
 	while (!imx6_pcie_link_up(priv)) {
 		udelay(10);
 		count++;
+		if (count == 1000) {
+			print_regs(1);
+			/* link down, try reset ep, and re-try link here */
+			DBGF("pcie link is down, reset ep, then retry!\n");
+			imx_pcie_toggle_reset(&priv->reset_gpio);
+			continue;
+		}
+#ifdef DEBUG
+		else if (count >= 2000) {
+			print_regs(1);
+			/* link is down, stop here */
+			env_set("bootcmd", "sleep 2;");
+			DBGF("pcie link is down, stop here!\n");
+			imx_pcie_ltssm_enable(priv, false);
+			return -EINVAL;
+		}
+#endif
 		if (count >= 4000) {
 #ifdef CONFIG_PCI_SCAN_SHOW
 			puts("PCI:   pcie phy link never came up\n");
@@ -674,6 +1400,7 @@ static int imx_pcie_link_up(struct imx_pcie_priv *priv)
 			debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
 			      readl(priv->dbi_base + PCIE_PHY_DEBUG_R0),
 			      readl(priv->dbi_base + PCIE_PHY_DEBUG_R1));
+			imx_pcie_ltssm_enable(priv, false);
 			return -EINVAL;
 		}
 	}
@@ -715,17 +1442,152 @@ static int imx_pcie_dm_write_config(struct udevice *dev, pci_dev_t bdf,
 
 static int imx_pcie_dm_probe(struct udevice *dev)
 {
+	int ret = 0;
 	struct imx_pcie_priv *priv = dev_get_priv(dev);
 
-	/* if PERST# valid from dt then assert it */
-	gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio,
-			     GPIOD_IS_OUT);
-	priv->reset_active_high = dev_read_bool(dev, "reset-gpio-active-high");
-	if (dm_gpio_is_valid(&priv->reset_gpio)) {
-		dm_gpio_set_value(&priv->reset_gpio,
-				  priv->reset_active_high ? 0 : 1);
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+	ret = device_get_supply_regulator(dev, "epdev_on", &priv->epdev_on);
+	if (ret) {
+		priv->epdev_on = NULL;
+		dev_dbg(dev, "no epdev_on\n");
+	} else {
+		ret = regulator_set_enable(priv->epdev_on, true);
+		if (ret) {
+			dev_err(dev, "fail to enable epdev_on\n");
+			return ret;
+		}
+	}
+
+	mdelay(100);
+#endif
+
+	/* Enable the osc clk */
+	ret = gpio_request_by_name(dev, "clkreq-gpio", 0, &priv->clkreq_gpio,
+				   (GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE));
+	if (ret) {
+		dev_info(dev, "%d unable to get clkreq.\n", ret);
 	}
 
+	/* enable */
+	ret = gpio_request_by_name(dev, "disable-gpio", 0, &priv->dis_gpio,
+				   (GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE));
+	if (ret) {
+		dev_info(dev, "%d unable to get disable-gpio.\n", ret);
+	}
+
+	/* Set to power on */
+	ret = gpio_request_by_name(dev, "power-on-gpio", 0, &priv->power_on_gpio,
+				   (GPIOD_IS_OUT |GPIOD_IS_OUT_ACTIVE));
+	if (ret) {
+		dev_info(dev, "%d unable to get power-on-gpio.\n", ret);
+	}
+
+	/* Set to reset status */
+	ret = gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio,
+				   (GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE));
+	if (ret) {
+		dev_info(dev, "%d unable to get power-on-gpio.\n", ret);
+	}
+
+#if CONFIG_IS_ENABLED(CLK)
+	ret = clk_get_by_name(dev, "pcie_phy", &priv->pcie_phy);
+	if (ret) {
+		printf("Failed to get pcie_phy clk\n");
+		return ret;
+	}
+
+	ret = clk_get_by_name(dev, "pcie_bus", &priv->pcie_bus);
+	if (ret) {
+		printf("Failed to get pcie_bus clk\n");
+		return ret;
+	}
+
+	ret = clk_get_by_name(dev, "pcie", &priv->pcie);
+	if (ret) {
+		printf("Failed to get pcie clk\n");
+		return ret;
+	}
+#endif
+
+	if (priv->variant == IMX8QM || priv->variant == IMX8QXP) {
+#if CONFIG_IS_ENABLED(CLK)
+		ret = clk_get_by_name(dev, "pcie_per", &priv->pcie_per);
+		if (ret) {
+			printf("Failed to get pcie_per clk\n");
+			return ret;
+		}
+
+		ret = clk_get_by_name(dev, "pcie_inbound_axi", &priv->pcie_inbound_axi);
+		if (ret) {
+			printf("Failed to get pcie_inbound_axi clk\n");
+			return ret;
+		}
+
+		ret = clk_get_by_name(dev, "phy_per", &priv->phy_per);
+		if (ret) {
+			printf("Failed to get phy_per clk\n");
+			return ret;
+		}
+
+		ret = clk_get_by_name(dev, "misc_per", &priv->misc_per);
+		if (ret) {
+			printf("Failed to get misc_per clk\n");
+			return ret;
+		}
+
+		if (priv->variant == IMX8QM && priv->ctrl_id == 1) {
+			ret = clk_get_by_name(dev, "pcie_phy_pclk", &priv->pcie_phy_pclk);
+			if (ret) {
+				printf("Failed to get pcie_phy_pclk clk\n");
+				return ret;
+			}
+
+			ret = clk_get_by_name(dev, "pciex2_per", &priv->pciex2_per);
+			if (ret) {
+				printf("Failed to get pciex2_per clk\n");
+				return ret;
+			}
+		}
+#endif
+		priv->iomuxc_gpr =
+			 syscon_regmap_lookup_by_phandle(dev, "hsio");
+		if (IS_ERR(priv->iomuxc_gpr)) {
+			dev_err(dev, "unable to find gpr registers\n");
+			return PTR_ERR(priv->iomuxc_gpr);
+		}
+	} else {
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+		if (priv->variant == IMX6QP) {
+			ret = device_get_supply_regulator(dev, "pcie-bus", &priv->pcie_bus_regulator);
+			if (ret) {
+				dev_dbg(dev, "no pcie_bus_regulator\n");
+				priv->pcie_bus_regulator = NULL;
+			}
+		} else if (priv->variant == IMX6SX) {
+			ret = device_get_supply_regulator(dev, "pcie-phy", &priv->pcie_phy_regulator);
+			if (ret) {
+				dev_dbg(dev, "no pcie_phy_regulator\n");
+				priv->pcie_phy_regulator = NULL;
+			}
+		}
+#endif
+
+		priv->iomuxc_gpr =
+			 syscon_regmap_lookup_by_phandle(dev, "gpr");
+		if (IS_ERR(priv->iomuxc_gpr)) {
+			dev_err(dev, "unable to find gpr registers\n");
+			return PTR_ERR(priv->iomuxc_gpr);
+		}
+	}
+
+	pci_get_regions(dev, &priv->io, &priv->mem, &priv->pref);
+
+	if (priv->cpu_base)
+		priv->cpu_addr_offset = priv->cpu_base
+				- priv->mem->phys_start;
+	else
+		priv->cpu_addr_offset = 0;
+
 	return imx_pcie_link_up(priv);
 }
 
@@ -733,7 +1595,7 @@ static int imx_pcie_dm_remove(struct udevice *dev)
 {
 	struct imx_pcie_priv *priv = dev_get_priv(dev);
 
-	imx6_pcie_assert_core_reset(priv, true);
+	imx_pcie_assert_core_reset(priv, true);
 
 	return 0;
 }
@@ -741,12 +1603,45 @@ static int imx_pcie_dm_remove(struct udevice *dev)
 static int imx_pcie_of_to_plat(struct udevice *dev)
 {
 	struct imx_pcie_priv *priv = dev_get_priv(dev);
+	int ret;
+	struct resource cfg_res;
 
 	priv->dbi_base = (void __iomem *)devfdt_get_addr_index(dev, 0);
-	priv->cfg_base = (void __iomem *)devfdt_get_addr_index(dev, 1);
-	if (!priv->dbi_base || !priv->cfg_base)
+	if (!priv->dbi_base)
 		return -EINVAL;
 
+	ret = dev_read_resource_byname(dev,  "config", &cfg_res);
+	if (ret) {
+		printf("can't get config resource(ret = %d)\n", ret);
+		return -ENOMEM;
+	}
+
+	priv->cfg_base = map_physmem(cfg_res.start,
+				 resource_size(&cfg_res),
+				 MAP_NOCACHE);
+	priv->cfg1_base = priv->cfg_base + resource_size(&cfg_res) / 2;
+	priv->cfg_size = resource_size(&cfg_res);
+
+	priv->variant = (enum imx_pcie_variants)dev_get_driver_data(dev);
+
+	if (dev_read_u32u(dev, "hsio-cfg", &priv->hsio_cfg))
+		priv->hsio_cfg = 0;
+
+	if (dev_read_u32u(dev, "ctrl-id", &priv->ctrl_id))
+		priv->ctrl_id = 0;
+
+	if (dev_read_u32u(dev, "ext_osc", &priv->ext_osc))
+		priv->ext_osc = 0;
+
+	if (dev_read_u32u(dev, "cpu-base-addr", &priv->cpu_base))
+		priv->cpu_base = 0;
+
+	if (dev_read_u32u(dev, "num-lanes", &priv->lanes))
+		priv->lanes = 1;
+
+	debug("hsio-cfg %u, ctrl-id %u, ext_osc %u, cpu-base 0x%x\n",
+		priv->hsio_cfg, priv->ctrl_id, priv->ext_osc, priv->cpu_base);
+
 	return 0;
 }
 
@@ -756,8 +1651,11 @@ static const struct dm_pci_ops imx_pcie_ops = {
 };
 
 static const struct udevice_id imx_pcie_ids[] = {
-	{ .compatible = "fsl,imx6q-pcie" },
-	{ .compatible = "fsl,imx6sx-pcie" },
+	{ .compatible = "fsl,imx6q-pcie",  .data = (ulong)IMX6Q,  },
+	{ .compatible = "fsl,imx6sx-pcie", .data = (ulong)IMX6SX, },
+	{ .compatible = "fsl,imx6qp-pcie", .data = (ulong)IMX6QP, },
+	{ .compatible = "fsl,imx8qm-pcie", .data = (ulong)IMX8QM, },
+	{ .compatible = "fsl,imx8qxp-pcie", .data = (ulong)IMX8QXP, },
 	{ }
 };
 
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index d79798429b1..6becaaddd4f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -277,10 +277,19 @@ config PHY_MTK_TPHY
 config PHY_IMX8MQ_USB
 	bool "NXP i.MX8MQ USB PHY Driver"
 	depends on PHY
-	depends on IMX8MQ
+	depends on IMX8MQ || IMX8MP
 	help
 	  Support the USB3.0 PHY in NXP i.MX8MQ SoC
 
+config PHY_IMX93_MIPI_DPHY
+	bool "NXP i.MX93 MIPI DPHY Driver"
+	depends on PHY
+	depends on ARCH_IMX9
+	select REGMAP
+	help
+	  Enable this to add support for the Synopsys DW MIPI DPHY as found
+	  on NXP's i.MX93 SoC.
+
 config PHY_XILINX_ZYNQMP
 	tristate "Xilinx ZynqMP PHY driver"
 	depends on PHY && ARCH_ZYNQMP
@@ -288,6 +297,14 @@ config PHY_XILINX_ZYNQMP
 	  Enable this to support ZynqMP High Speed Gigabit Transceiver
 	  that is part of ZynqMP SoC.
 
+config CDNS3_USB_PHY
+	bool "Support CDNS3 USB PHY"
+	depends on PHY
+	help
+	  Support for the USB PHY in CDNS3 IP.
+
+	  This PHY is found on CDNS3 IP devices supporting USB.
+
 source "drivers/phy/rockchip/Kconfig"
 source "drivers/phy/cadence/Kconfig"
 source "drivers/phy/ti/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index bf9b40932fe..5f195daffec 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -35,9 +35,11 @@ obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o
 obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o
 obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o
 obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o
+obj-$(CONFIG_CDNS3_USB_PHY) += cdns3-usb-phy.o
 obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
 obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
 obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o
+obj-$(CONFIG_PHY_IMX93_MIPI_DPHY) += phy-imx93-mipi-dphy.o
 obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o
 obj-y += cadence/
 obj-y += ti/
diff --git a/drivers/phy/cdns3-usb-phy.c b/drivers/phy/cdns3-usb-phy.c
new file mode 100644
index 00000000000..1d397a3114d
--- /dev/null
+++ b/drivers/phy/cdns3-usb-phy.c
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * Cadence3 USB PHY driver
+ *
+ * Author: Sherry Sun <sherry.sun@nxp.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+/* PHY registers */
+#define PHY_PMA_CMN_CTRL1			(0xC800 * 4)
+#define TB_ADDR_CMN_DIAG_HSCLK_SEL		(0x01e0 * 4)
+#define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR	(0x0084 * 4)
+#define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR	(0x0085 * 4)
+#define TB_ADDR_CMN_PLL0_INTDIV	                (0x0094 * 4)
+#define TB_ADDR_CMN_PLL0_FRACDIV		(0x0095 * 4)
+#define TB_ADDR_CMN_PLL0_HIGH_THR		(0x0096 * 4)
+#define TB_ADDR_CMN_PLL0_SS_CTRL1		(0x0098 * 4)
+#define TB_ADDR_CMN_PLL0_SS_CTRL2		(0x0099 * 4)
+#define TB_ADDR_CMN_PLL0_DSM_DIAG		(0x0097 * 4)
+#define TB_ADDR_CMN_DIAG_PLL0_OVRD		(0x01c2 * 4)
+#define TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD		(0x01c0 * 4)
+#define TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD		(0x01c1 * 4)
+#define TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE          (0x01C5 * 4)
+#define TB_ADDR_CMN_DIAG_PLL0_CP_TUNE           (0x01C6 * 4)
+#define TB_ADDR_CMN_DIAG_PLL0_LF_PROG           (0x01C7 * 4)
+#define TB_ADDR_CMN_DIAG_PLL0_TEST_MODE		(0x01c4 * 4)
+#define TB_ADDR_CMN_PSM_CLK_CTRL		(0x0061 * 4)
+#define TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR	(0x40ea * 4)
+#define TB_ADDR_XCVR_PSM_RCTRL	                (0x4001 * 4)
+#define TB_ADDR_TX_PSC_A0		        (0x4100 * 4)
+#define TB_ADDR_TX_PSC_A1		        (0x4101 * 4)
+#define TB_ADDR_TX_PSC_A2		        (0x4102 * 4)
+#define TB_ADDR_TX_PSC_A3		        (0x4103 * 4)
+#define TB_ADDR_TX_DIAG_ECTRL_OVRD		(0x41f5 * 4)
+#define TB_ADDR_TX_PSC_CAL		        (0x4106 * 4)
+#define TB_ADDR_TX_PSC_RDY		        (0x4107 * 4)
+#define TB_ADDR_RX_PSC_A0	                (0x8000 * 4)
+#define TB_ADDR_RX_PSC_A1	                (0x8001 * 4)
+#define TB_ADDR_RX_PSC_A2	                (0x8002 * 4)
+#define TB_ADDR_RX_PSC_A3	                (0x8003 * 4)
+#define TB_ADDR_RX_PSC_CAL	                (0x8006 * 4)
+#define TB_ADDR_RX_PSC_RDY	                (0x8007 * 4)
+#define TB_ADDR_TX_TXCC_MGNLS_MULT_000		(0x4058 * 4)
+#define TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY	(0x41e7 * 4)
+#define TB_ADDR_RX_SLC_CU_ITER_TMR		(0x80e3 * 4)
+#define TB_ADDR_RX_SIGDET_HL_FILT_TMR		(0x8090 * 4)
+#define TB_ADDR_RX_SAMP_DAC_CTRL		(0x8058 * 4)
+#define TB_ADDR_RX_DIAG_SIGDET_TUNE		(0x81dc * 4)
+#define TB_ADDR_RX_DIAG_LFPSDET_TUNE2		(0x81df * 4)
+#define TB_ADDR_RX_DIAG_BS_TM	                (0x81f5 * 4)
+#define TB_ADDR_RX_DIAG_DFE_CTRL1		(0x81d3 * 4)
+#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM4		(0x81c7 * 4)
+#define TB_ADDR_RX_DIAG_ILL_E_TRIM0		(0x81c2 * 4)
+#define TB_ADDR_RX_DIAG_ILL_IQ_TRIM0		(0x81c1 * 4)
+#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM6		(0x81c9 * 4)
+#define TB_ADDR_RX_DIAG_RXFE_TM3		(0x81f8 * 4)
+#define TB_ADDR_RX_DIAG_RXFE_TM4		(0x81f9 * 4)
+#define TB_ADDR_RX_DIAG_LFPSDET_TUNE		(0x81dd * 4)
+#define TB_ADDR_RX_DIAG_DFE_CTRL3		(0x81d5 * 4)
+#define TB_ADDR_RX_DIAG_SC2C_DELAY		(0x81e1 * 4)
+#define TB_ADDR_RX_REE_VGA_GAIN_NODFE		(0x81bf * 4)
+#define TB_ADDR_XCVR_PSM_CAL_TMR		(0x4002 * 4)
+#define TB_ADDR_XCVR_PSM_A0BYP_TMR		(0x4004 * 4)
+#define TB_ADDR_XCVR_PSM_A0IN_TMR		(0x4003 * 4)
+#define TB_ADDR_XCVR_PSM_A1IN_TMR		(0x4005 * 4)
+#define TB_ADDR_XCVR_PSM_A2IN_TMR		(0x4006 * 4)
+#define TB_ADDR_XCVR_PSM_A3IN_TMR		(0x4007 * 4)
+#define TB_ADDR_XCVR_PSM_A4IN_TMR		(0x4008 * 4)
+#define TB_ADDR_XCVR_PSM_A5IN_TMR		(0x4009 * 4)
+#define TB_ADDR_XCVR_PSM_A0OUT_TMR		(0x400a * 4)
+#define TB_ADDR_XCVR_PSM_A1OUT_TMR		(0x400b * 4)
+#define TB_ADDR_XCVR_PSM_A2OUT_TMR		(0x400c * 4)
+#define TB_ADDR_XCVR_PSM_A3OUT_TMR		(0x400d * 4)
+#define TB_ADDR_XCVR_PSM_A4OUT_TMR		(0x400e * 4)
+#define TB_ADDR_XCVR_PSM_A5OUT_TMR		(0x400f * 4)
+#define TB_ADDR_TX_RCVDET_EN_TMR	        (0x4122 * 4)
+#define TB_ADDR_TX_RCVDET_ST_TMR	        (0x4123 * 4)
+#define TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR	(0x40f2 * 4)
+
+struct cdns3_usb_phy {
+	struct clk phy_clk;
+	void __iomem *phy_regs;
+};
+
+static int cdns3_usb_phy_init(struct phy *phy)
+{
+	struct udevice *dev = phy->dev;
+	struct cdns3_usb_phy *priv = dev_get_priv(dev);
+	void __iomem *regs = priv->phy_regs;
+
+	writel(0x0830, regs + PHY_PMA_CMN_CTRL1);
+	writel(0x10, regs + TB_ADDR_CMN_DIAG_HSCLK_SEL);
+	writel(0x00F0, regs + TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR);
+	writel(0x0018, regs + TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR);
+	writel(0x00D0, regs + TB_ADDR_CMN_PLL0_INTDIV);
+	writel(0x4aaa, regs + TB_ADDR_CMN_PLL0_FRACDIV);
+	writel(0x0034, regs + TB_ADDR_CMN_PLL0_HIGH_THR);
+	writel(0x1ee, regs + TB_ADDR_CMN_PLL0_SS_CTRL1);
+	writel(0x7F03, regs + TB_ADDR_CMN_PLL0_SS_CTRL2);
+	writel(0x0020, regs + TB_ADDR_CMN_PLL0_DSM_DIAG);
+	writel(0x0000, regs + TB_ADDR_CMN_DIAG_PLL0_OVRD);
+	writel(0x0000, regs + TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD);
+	writel(0x0000, regs + TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD);
+	writel(0x0007, regs + TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE);
+	writel(0x0027, regs + TB_ADDR_CMN_DIAG_PLL0_CP_TUNE);
+	writel(0x0008, regs + TB_ADDR_CMN_DIAG_PLL0_LF_PROG);
+	writel(0x0022, regs + TB_ADDR_CMN_DIAG_PLL0_TEST_MODE);
+	writel(0x000a, regs + TB_ADDR_CMN_PSM_CLK_CTRL);
+	writel(0x139, regs + TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR);
+	writel(0xbefc, regs + TB_ADDR_XCVR_PSM_RCTRL);
+
+	writel(0x7799, regs + TB_ADDR_TX_PSC_A0);
+	writel(0x7798, regs + TB_ADDR_TX_PSC_A1);
+	writel(0x509b, regs + TB_ADDR_TX_PSC_A2);
+	writel(0x3, regs + TB_ADDR_TX_DIAG_ECTRL_OVRD);
+	writel(0x509b, regs + TB_ADDR_TX_PSC_A3);
+	writel(0x2090, regs + TB_ADDR_TX_PSC_CAL);
+	writel(0x2090, regs + TB_ADDR_TX_PSC_RDY);
+
+	writel(0xA6FD, regs + TB_ADDR_RX_PSC_A0);
+	writel(0xA6FD, regs + TB_ADDR_RX_PSC_A1);
+	writel(0xA410, regs + TB_ADDR_RX_PSC_A2);
+	writel(0x2410, regs + TB_ADDR_RX_PSC_A3);
+
+	writel(0x23FF, regs + TB_ADDR_RX_PSC_CAL);
+	writel(0x2010, regs + TB_ADDR_RX_PSC_RDY);
+
+	writel(0x0020, regs + TB_ADDR_TX_TXCC_MGNLS_MULT_000);
+	writel(0x00ff, regs + TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY);
+	writel(0x0002, regs + TB_ADDR_RX_SLC_CU_ITER_TMR);
+	writel(0x0013, regs + TB_ADDR_RX_SIGDET_HL_FILT_TMR);
+	writel(0x0000, regs + TB_ADDR_RX_SAMP_DAC_CTRL);
+	writel(0x1004, regs + TB_ADDR_RX_DIAG_SIGDET_TUNE);
+	writel(0x4041, regs + TB_ADDR_RX_DIAG_LFPSDET_TUNE2);
+	writel(0x0480, regs + TB_ADDR_RX_DIAG_BS_TM);
+	writel(0x8006, regs + TB_ADDR_RX_DIAG_DFE_CTRL1);
+	writel(0x003f, regs + TB_ADDR_RX_DIAG_ILL_IQE_TRIM4);
+	writel(0x543f, regs + TB_ADDR_RX_DIAG_ILL_E_TRIM0);
+	writel(0x543f, regs + TB_ADDR_RX_DIAG_ILL_IQ_TRIM0);
+	writel(0x0000, regs + TB_ADDR_RX_DIAG_ILL_IQE_TRIM6);
+	writel(0x8000, regs + TB_ADDR_RX_DIAG_RXFE_TM3);
+	writel(0x0003, regs + TB_ADDR_RX_DIAG_RXFE_TM4);
+	writel(0x2408, regs + TB_ADDR_RX_DIAG_LFPSDET_TUNE);
+	writel(0x05ca, regs + TB_ADDR_RX_DIAG_DFE_CTRL3);
+	writel(0x0258, regs + TB_ADDR_RX_DIAG_SC2C_DELAY);
+	writel(0x1fff, regs + TB_ADDR_RX_REE_VGA_GAIN_NODFE);
+
+	writel(0x02c6, regs + TB_ADDR_XCVR_PSM_CAL_TMR);
+	writel(0x0002, regs + TB_ADDR_XCVR_PSM_A0BYP_TMR);
+	writel(0x02c6, regs + TB_ADDR_XCVR_PSM_A0IN_TMR);
+	writel(0x0010, regs + TB_ADDR_XCVR_PSM_A1IN_TMR);
+	writel(0x0010, regs + TB_ADDR_XCVR_PSM_A2IN_TMR);
+	writel(0x0010, regs + TB_ADDR_XCVR_PSM_A3IN_TMR);
+	writel(0x0010, regs + TB_ADDR_XCVR_PSM_A4IN_TMR);
+	writel(0x0010, regs + TB_ADDR_XCVR_PSM_A5IN_TMR);
+
+	writel(0x0002, regs + TB_ADDR_XCVR_PSM_A0OUT_TMR);
+	writel(0x0002, regs + TB_ADDR_XCVR_PSM_A1OUT_TMR);
+	writel(0x0002, regs + TB_ADDR_XCVR_PSM_A2OUT_TMR);
+	writel(0x0002, regs + TB_ADDR_XCVR_PSM_A3OUT_TMR);
+	writel(0x0002, regs + TB_ADDR_XCVR_PSM_A4OUT_TMR);
+	writel(0x0002, regs + TB_ADDR_XCVR_PSM_A5OUT_TMR);
+
+	/* Change rx detect parameter */
+	writel(0x960, regs + TB_ADDR_TX_RCVDET_EN_TMR);
+	writel(0x01e0, regs + TB_ADDR_TX_RCVDET_ST_TMR);
+	writel(0x0090, regs + TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR);
+
+	udelay(10);
+	return 0;
+}
+
+struct phy_ops cdns3_usb_phy_ops = {
+	.init = cdns3_usb_phy_init,
+};
+
+static int cdns3_usb_phy_remove(struct udevice *dev)
+{
+#if CONFIG_IS_ENABLED(CLK)
+	struct cdns3_usb_phy *priv = dev_get_priv(dev);
+	int ret;
+
+	if (priv->phy_clk.dev) {
+		ret = clk_disable(&priv->phy_clk);
+		if (ret)
+			return ret;
+
+		ret = clk_free(&priv->phy_clk);
+		if (ret)
+			return ret;
+	}
+#endif
+
+	return 0;
+}
+
+static int cdns3_usb_phy_probe(struct udevice *dev)
+{
+	struct cdns3_usb_phy *priv = dev_get_priv(dev);
+
+#if CONFIG_IS_ENABLED(CLK)
+	int ret;
+
+	ret = clk_get_by_name(dev, "main_clk", &priv->phy_clk);
+	if (ret) {
+		printf("Failed to get phy_clk\n");
+		return ret;
+	}
+
+	ret = clk_enable(&priv->phy_clk);
+	if (ret) {
+		printf("Failed to enable phy_clk\n");
+		return ret;
+	}
+#endif
+	priv->phy_regs = (void *__iomem)devfdt_get_addr(dev);
+
+	return 0;
+}
+
+static const struct udevice_id cdns3_usb_phy_ids[] = {
+	{ .compatible = "cdns,usb3-phy" },
+	{ }
+};
+
+U_BOOT_DRIVER(cdns3_usb_phy) = {
+	.name = "cdns3_usb_phy",
+	.id = UCLASS_PHY,
+	.of_match = cdns3_usb_phy_ids,
+	.probe = cdns3_usb_phy_probe,
+	.remove = cdns3_usb_phy_remove,
+	.ops = &cdns3_usb_phy_ops,
+	.priv_auto = sizeof(struct cdns3_usb_phy),
+};
diff --git a/drivers/phy/phy-imx8mq-usb.c b/drivers/phy/phy-imx8mq-usb.c
index afbc7ad8dd4..eaeba6012f3 100644
--- a/drivers/phy/phy-imx8mq-usb.c
+++ b/drivers/phy/phy-imx8mq-usb.c
@@ -9,8 +9,10 @@
 #include <dm.h>
 #include <errno.h>
 #include <generic-phy.h>
+#include <linux/bitfield.h>
 #include <linux/bitops.h>
 #include <linux/err.h>
+#include <linux/delay.h>
 #include <clk.h>
 
 #define PHY_CTRL0			0x0
@@ -79,15 +81,62 @@ static const struct udevice_id imx8mq_usb_phy_of_match[] = {
 	{
 		.compatible = "fsl,imx8mq-usb-phy",
 	},
+	{
+		.compatible = "fsl,imx8mp-usb-phy",
+	},
 	{},
 };
 
+static int imx8mp_usb_phy_init(struct phy *usb_phy)
+{
+	struct udevice *dev = usb_phy->dev;
+	struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev);
+	u32 value;
+
+	/* USB3.0 PHY signal fsel for 24M ref */
+	value = readl(imx_phy->base + PHY_CTRL0);
+	value &= ~PHY_CTRL0_FSEL_MASK;
+	value |= FIELD_PREP(PHY_CTRL0_FSEL_MASK, PHY_CTRL0_FSEL_24M);
+	writel(value, imx_phy->base + PHY_CTRL0);
+
+	/* Disable alt_clk_en and use internal MPLL clocks */
+	value = readl(imx_phy->base + PHY_CTRL6);
+	value &= ~(PHY_CTRL6_ALT_CLK_SEL | PHY_CTRL6_ALT_CLK_EN);
+	writel(value, imx_phy->base + PHY_CTRL6);
+
+	value = readl(imx_phy->base + PHY_CTRL1);
+	value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0);
+	value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET;
+	writel(value, imx_phy->base + PHY_CTRL1);
+
+	value = readl(imx_phy->base + PHY_CTRL0);
+	value |= PHY_CTRL0_REF_SSP_EN;
+	writel(value, imx_phy->base + PHY_CTRL0);
+
+	value = readl(imx_phy->base + PHY_CTRL2);
+	value |= PHY_CTRL2_TXENABLEN0 | PHY_CTRL2_OTG_DISABLE;
+	writel(value, imx_phy->base + PHY_CTRL2);
+
+	udelay(10);
+
+	value = readl(imx_phy->base + PHY_CTRL1);
+	value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET);
+	writel(value, imx_phy->base + PHY_CTRL1);
+
+	return 0;
+}
+
 static int imx8mq_usb_phy_init(struct phy *usb_phy)
 {
 	struct udevice *dev = usb_phy->dev;
 	struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev);
 	u32 value;
 
+	if (ofnode_device_is_compatible(dev_ofnode(dev),
+		"fsl,imx8mp-usb-phy")) {
+		return imx8mp_usb_phy_init(usb_phy);
+	}
+
 	value = readl(imx_phy->base + PHY_CTRL1);
 	value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0 |
 		   PHY_CTRL1_COMMONONN);
diff --git a/drivers/phy/phy-imx93-mipi-dphy.c b/drivers/phy/phy-imx93-mipi-dphy.c
new file mode 100644
index 00000000000..54f2d03c1dd
--- /dev/null
+++ b/drivers/phy/phy-imx93-mipi-dphy.c
@@ -0,0 +1,527 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <clk.h>
+#include <regmap.h>
+#include <dm/device_compat.h>
+#include <phy-mipi-dphy.h>
+#include <div64.h>
+
+/* DPHY registers */
+#define DSI_REG			0x4c
+#define  CFGCLKFREQRANGE_MASK	GENMASK(5, 0)
+#define  CFGCLKFREQRANGE(x)	FIELD_PREP(CFGCLKFREQRANGE_MASK, (x))
+#define  CLKSEL_MASK		GENMASK(7, 6)
+#define  CLKSEL_STOP		FIELD_PREP(CLKSEL_MASK, 0)
+#define  CLKSEL_GEN		FIELD_PREP(CLKSEL_MASK, 1)
+#define  CLKSEL_EXT		FIELD_PREP(CLKSEL_MASK, 2)
+#define  HSFREQRANGE_MASK	GENMASK(14, 8)
+#define  HSFREQRANGE(x)		FIELD_PREP(HSFREQRANGE_MASK, (x))
+#define  UPDATE_PLL		BIT(17)
+#define  SHADOW_CLR		BIT(18)
+#define  CLK_EXT		BIT(19)
+
+#define DSI_WRITE_REG0		0x50
+#define  M_MASK			GENMASK(9, 0)
+#define  M(x)			FIELD_PREP(M_MASK, ((x) - 2))
+#define  N_MASK			GENMASK(13, 10)
+#define  N(x)			FIELD_PREP(N_MASK, ((x) - 1))
+#define  VCO_CTRL_MASK		GENMASK(19, 14)
+#define  VCO_CTRL(x)		FIELD_PREP(VCO_CTRL_MASK, (x))
+#define  PROP_CTRL_MASK		GENMASK(25, 20)
+#define  PROP_CTRL(x)		FIELD_PREP(PROP_CTRL_MASK, (x))
+#define  INT_CTRL_MASK		GENMASK(31, 26)
+#define  INT_CTRL(x)		FIELD_PREP(INT_CTRL_MASK, (x))
+
+#define DSI_WRITE_REG1		0x54
+#define  GMP_CTRL_MASK		GENMASK(1, 0)
+#define  GMP_CTRL(x)		FIELD_PREP(GMP_CTRL_MASK, (x))
+#define  CPBIAS_CTRL_MASK	GENMASK(8, 2)
+#define  CPBIAS_CTRL(x)		FIELD_PREP(CPBIAS_CTRL_MASK, (x))
+#define  PLL_SHADOW_CTRL	BIT(9)
+
+#define DSI_READ_REG1		0x5c
+#define  LOCK_PLL		BIT(10)
+
+#define MHZ(x)			((x) * 1000000UL)
+
+#define REF_CLK_RATE_MAX	MHZ(64)
+#define REF_CLK_RATE_MIN	MHZ(2)
+#define FOUT_MAX		MHZ(1250)
+#define FOUT_MIN		MHZ(40)
+#define FVCO_DIV_FACTOR		MHZ(80)
+
+#define MBPS(x)			((x) * 1000000UL)
+
+#define DATA_RATE_MAX_SPEED	MBPS(2500)
+#define DATA_RATE_MIN_SPEED	MBPS(80)
+
+#define M_MAX			625UL
+#define M_MIN			64UL
+
+#define N_MAX			16U
+#define N_MIN			1U
+
+#define PLL_LOCK_SLEEP		10
+#define PLL_LOCK_TIMEOUT	1000
+
+struct dw_dphy_cfg {
+	u32 m;	/* PLL Feedback Multiplication Ratio */
+	u32 n;	/* PLL Input Frequency Division Ratio */
+};
+
+struct dw_dphy_priv {
+	struct regmap *regmap;
+	struct clk ref_clk;
+	struct clk cfg_clk;
+	unsigned long ref_clk_rate;
+};
+
+struct dw_dphy_vco_prop {
+	unsigned int max_fout;
+	u8 vco_cntl;
+	u8 prop_cntl;
+};
+
+struct dw_dphy_hsfreqrange {
+	unsigned int max_mbps;
+	u8 hsfreqrange;
+};
+
+/* Databook Table 3-13 Charge-pump Programmability */
+static const struct dw_dphy_vco_prop vco_prop_map[] = {
+	{   55, 0x3f, 0x0d },
+	{   82, 0x37, 0x0d },
+	{  110, 0x2f, 0x0d },
+	{  165, 0x27, 0x0d },
+	{  220, 0x1f, 0x0d },
+	{  330, 0x17, 0x0d },
+	{  440, 0x0f, 0x0d },
+	{  660, 0x07, 0x0d },
+	{ 1149, 0x03, 0x0d },
+	{ 1152, 0x01, 0x0d },
+	{ 1250, 0x01, 0x0e },
+};
+
+/* Databook Table 5-7 Frequency Ranges and Defaults */
+static const struct dw_dphy_hsfreqrange hsfreqrange_map[] = {
+	{   89, 0x00 },
+	{   99, 0x10 },
+	{  109, 0x20 },
+	{  119, 0x30 },
+	{  129, 0x01 },
+	{  139, 0x11 },
+	{  149, 0x21 },
+	{  159, 0x31 },
+	{  169, 0x02 },
+	{  179, 0x12 },
+	{  189, 0x22 },
+	{  204, 0x32 },
+	{  219, 0x03 },
+	{  234, 0x13 },
+	{  249, 0x23 },
+	{  274, 0x33 },
+	{  299, 0x04 },
+	{  324, 0x14 },
+	{  349, 0x25 },
+	{  399, 0x35 },
+	{  449, 0x05 },
+	{  499, 0x16 },
+	{  549, 0x26 },
+	{  599, 0x37 },
+	{  649, 0x07 },
+	{  699, 0x18 },
+	{  749, 0x28 },
+	{  799, 0x39 },
+	{  849, 0x09 },
+	{  899, 0x19 },
+	{  949, 0x29 },
+	{  999, 0x3a },
+	{ 1049, 0x0a },
+	{ 1099, 0x1a },
+	{ 1149, 0x2a },
+	{ 1199, 0x3b },
+	{ 1249, 0x0b },
+	{ 1299, 0x1b },
+	{ 1349, 0x2b },
+	{ 1399, 0x3c },
+	{ 1449, 0x0c },
+	{ 1499, 0x1c },
+	{ 1549, 0x2c },
+	{ 1599, 0x3d },
+	{ 1649, 0x0d },
+	{ 1699, 0x1d },
+	{ 1749, 0x2e },
+	{ 1799, 0x3e },
+	{ 1849, 0x0e },
+	{ 1899, 0x1e },
+	{ 1949, 0x2f },
+	{ 1999, 0x3f },
+	{ 2049, 0x0f },
+	{ 2099, 0x40 },
+	{ 2149, 0x41 },
+	{ 2199, 0x42 },
+	{ 2249, 0x43 },
+	{ 2299, 0x44 },
+	{ 2349, 0x45 },
+	{ 2399, 0x46 },
+	{ 2449, 0x47 },
+	{ 2499, 0x48 },
+	{ 2500, 0x49 },
+};
+
+static int phy_write(struct phy *phy, u32 value, unsigned int reg)
+{
+	struct dw_dphy_priv *priv = dev_get_priv(phy->dev);
+	int ret;
+
+	ret = regmap_write(priv->regmap, reg, value);
+	if (ret < 0)
+		dev_err(phy->dev, "failed to write reg %u: %d\n", reg, ret);
+	return ret;
+}
+
+static inline unsigned long data_rate_to_fout(unsigned long data_rate)
+{
+	/* Fout is half of data rate */
+	return data_rate / 2;
+}
+
+static int
+dw_dphy_config_from_opts(struct phy *phy,
+			 struct phy_configure_opts_mipi_dphy *dphy_opts,
+			 struct dw_dphy_cfg *cfg)
+{
+	struct dw_dphy_priv *priv = dev_get_priv(phy->dev);
+	unsigned long fin = priv->ref_clk_rate;
+	unsigned long fout;
+	unsigned long best_fout = 0;
+	unsigned int fvco_div;
+	unsigned int min_n, max_n, n, best_n;
+	unsigned long m, best_m;
+	unsigned long min_delta = ULONG_MAX;
+	unsigned long tmp, delta;
+
+	if (dphy_opts->hs_clk_rate < DATA_RATE_MIN_SPEED ||
+	    dphy_opts->hs_clk_rate > DATA_RATE_MAX_SPEED) {
+		dev_dbg(phy->dev, "invalid data rate per lane: %lu\n",
+			dphy_opts->hs_clk_rate);
+		return -EINVAL;
+	}
+
+	fout = data_rate_to_fout(dphy_opts->hs_clk_rate);
+
+	/* Fout = Fvco / Fvco_div = (Fin * M) / (Fvco_div * N) */
+	fvco_div = 8UL / min(DIV_ROUND_UP(fout, FVCO_DIV_FACTOR), 8UL);
+
+	/* limitation: 2MHz <= Fin / N <= 8MHz */
+	min_n = DIV_ROUND_UP(fin, MHZ(8));
+	max_n = DIV_ROUND_DOWN_ULL(fin, MHZ(2));
+
+	/* clamp possible N(s) */
+	min_n = clamp(min_n, N_MIN, N_MAX);
+	max_n = clamp(max_n, N_MIN, N_MAX);
+
+	dev_dbg(phy->dev, "Fout = %lu, Fvco_div = %u, n_range = [%u, %u]\n",
+		fout, fvco_div, min_n, max_n);
+
+	for (n = min_n; n <= max_n; n++) {
+		/* M = (Fout * N * Fvco_div) / Fin */
+		tmp = fout * n * fvco_div;
+		m = DIV_ROUND_CLOSEST(tmp, fin);
+
+		/* check M range */
+		if (m < M_MIN || m > M_MAX)
+			continue;
+
+		/* calculate temporary Fout */
+		tmp = m * fin;
+		do_div(tmp, n * fvco_div);
+		if (tmp < FOUT_MIN || tmp > FOUT_MAX)
+			continue;
+
+		delta = abs(fout - tmp);
+		if (delta < min_delta) {
+			best_n = n;
+			best_m = m;
+			min_delta = delta;
+			best_fout = tmp;
+		}
+	}
+
+	if (best_fout) {
+		cfg->m = best_m;
+		cfg->n = best_n;
+		dphy_opts->hs_clk_rate = best_fout * 2;
+		dev_dbg(phy->dev, "best Fout = %lu, m = %u, n = %u\n",
+			best_fout, cfg->m, cfg->n);
+	} else {
+		dev_dbg(phy->dev, "failed to find best Fout\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void dw_dphy_clear_shadow(struct phy *phy)
+{
+	/* Select clock generation first. */
+	phy_write(phy, CLKSEL_GEN, DSI_REG);
+
+	/* Clear shadow after clock selection is done a while. */
+	udelay(2);
+	phy_write(phy, CLKSEL_GEN | SHADOW_CLR, DSI_REG);
+
+	/*
+	 * A minimum pulse of 5ns on shadow_clear signal,
+	 * according to Databook Figure 3-3 Initialization Timing Diagram.
+	 */
+	udelay(2);
+	phy_write(phy, CLKSEL_GEN, DSI_REG);
+}
+
+static u32 dw_dphy_get_cfgclkrange(struct phy *phy)
+{
+	struct dw_dphy_priv *priv = dev_get_priv(phy->dev);
+
+	return (clk_get_rate(&priv->cfg_clk) / MHZ(1) - 17) * 4;
+}
+
+static u8 dw_dphy_get_hsfreqrange(struct phy_configure_opts_mipi_dphy *dphy_opts)
+{
+	unsigned int mbps = dphy_opts->hs_clk_rate / MHZ(1);
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(hsfreqrange_map); i++)
+		if (mbps <= hsfreqrange_map[i].max_mbps)
+			return hsfreqrange_map[i].hsfreqrange;
+
+	return 0;
+}
+
+static u8 dw_dphy_get_vco(struct phy_configure_opts_mipi_dphy *dphy_opts)
+{
+	unsigned int fout = data_rate_to_fout(dphy_opts->hs_clk_rate) / MHZ(1);
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(vco_prop_map); i++)
+		if (fout <= vco_prop_map[i].max_fout)
+			return vco_prop_map[i].vco_cntl;
+
+	return 0;
+}
+
+static u8 dw_dphy_get_prop(struct phy_configure_opts_mipi_dphy *dphy_opts)
+{
+	unsigned int fout = data_rate_to_fout(dphy_opts->hs_clk_rate) / MHZ(1);
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(vco_prop_map); i++)
+		if (fout <= vco_prop_map[i].max_fout)
+			return vco_prop_map[i].prop_cntl;
+
+	return 0;
+}
+
+static int dw_dphy_configure(struct phy *phy, void *params)
+{
+	struct dw_dphy_cfg cfg = { 0 };
+	u32 val;
+	int ret;
+	struct phy_configure_opts_mipi_dphy *opts = (struct phy_configure_opts_mipi_dphy *)params;
+
+	ret = dw_dphy_config_from_opts(phy, opts, &cfg);
+	if (ret)
+		return ret;
+
+	dw_dphy_clear_shadow(phy);
+
+	/* reg */
+	val = CLKSEL_GEN |
+	      CFGCLKFREQRANGE(dw_dphy_get_cfgclkrange(phy)) |
+	      HSFREQRANGE(dw_dphy_get_hsfreqrange(opts));
+	phy_write(phy, val, DSI_REG);
+
+	/* w_reg0 */
+	val = M(cfg.m) | N(cfg.n) | INT_CTRL(0) |
+	      VCO_CTRL(dw_dphy_get_vco(opts)) |
+	      PROP_CTRL(dw_dphy_get_prop(opts));
+	phy_write(phy, val, DSI_WRITE_REG0);
+
+	/* w_reg1 */
+	phy_write(phy, GMP_CTRL(1) | CPBIAS_CTRL(0x10), DSI_WRITE_REG1);
+
+	return 0;
+}
+
+static void dw_dphy_clear_reg(struct phy *phy)
+{
+	phy_write(phy, 0, DSI_REG);
+	phy_write(phy, 0, DSI_WRITE_REG0);
+	phy_write(phy, 0, DSI_WRITE_REG1);
+}
+
+static int dw_dphy_init(struct phy *phy)
+{
+	struct dw_dphy_priv *priv = dev_get_priv(phy->dev);
+	int ret;
+
+	ret = clk_prepare_enable(&priv->cfg_clk);
+	if (ret < 0) {
+		dev_err(phy->dev, "failed to enable config clock: %d\n", ret);
+		return ret;
+	}
+
+	dw_dphy_clear_reg(phy);
+
+	return 0;
+}
+
+static int dw_dphy_exit(struct phy *phy)
+{
+	struct dw_dphy_priv *priv = dev_get_priv(phy->dev);
+
+	dw_dphy_clear_reg(phy);
+	clk_disable_unprepare(&priv->cfg_clk);
+
+	return 0;
+}
+
+static int dw_dphy_update_pll(struct phy *phy)
+{
+	struct dw_dphy_priv *priv = dev_get_priv(phy->dev);
+	int ret;
+
+	ret = regmap_update_bits(priv->regmap, DSI_REG, UPDATE_PLL, UPDATE_PLL);
+	if (ret < 0) {
+		dev_err(phy->dev, "failed to set UPDATE_PLL: %d\n", ret);
+		return ret;
+	}
+
+	/*
+	 * The updatepll signal should be asserted for a minimum of four clkin
+	 * cycles, according to Databook Figure 3-3 Initialization Timing
+	 * Diagram.
+	 */
+	udelay(10);
+
+	ret = regmap_update_bits(priv->regmap, DSI_REG, UPDATE_PLL, 0);
+	if (ret < 0) {
+		dev_err(phy->dev, "failed to clear UPDATE_PLL: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int dw_dphy_power_on(struct phy *phy)
+{
+	struct dw_dphy_priv *priv = dev_get_priv(phy->dev);
+	int ret;
+
+	ret = clk_prepare_enable(&priv->ref_clk);
+	if (ret < 0) {
+		dev_err(phy->dev, "failed to enable ref clock: %d\n", ret);
+		return ret;
+	}
+
+	/*
+	 * At least 10 refclk cycles are required before updatePLL assertion,
+	 * according to Databook Figure 3-3 Initialization Timing Diagram.
+	 */
+	udelay(10);
+
+	ret = dw_dphy_update_pll(phy);
+	if (ret < 0) {
+		clk_disable_unprepare(&priv->ref_clk);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int dw_dphy_power_off(struct phy *phy)
+{
+	struct dw_dphy_priv *priv = dev_get_priv(phy->dev);
+
+	dw_dphy_clear_reg(phy);
+	clk_disable_unprepare(&priv->ref_clk);
+
+	return 0;
+}
+
+static const struct phy_ops imx_dw_dphy_phy_ops = {
+	.init = dw_dphy_init,
+	.exit = dw_dphy_exit,
+	.power_on = dw_dphy_power_on,
+	.power_off = dw_dphy_power_off,
+	.configure = dw_dphy_configure,
+};
+
+static int imx_dw_dphy_probe(struct udevice *dev)
+{
+	struct dw_dphy_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = regmap_init_mem(ofnode_get_parent(dev_ofnode(dev)), &priv->regmap);
+	if (ret) {
+		dev_err(dev, "failed to get regmap %d\n", ret);
+		return ret;
+	}
+
+#if CONFIG_IS_ENABLED(CLK)
+	ret = clk_get_by_name(dev, "phy_cfg", &priv->cfg_clk);
+	if (ret) {
+		dev_err(dev, "failed to get config clock %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_get_by_name(dev, "phy_ref", &priv->ref_clk);
+	if (ret) {
+		dev_err(dev, "failed to get ref clock %d\n", ret);
+		return ret;
+	}
+
+	priv->ref_clk_rate = clk_get_rate(&priv->ref_clk);
+	if (priv->ref_clk_rate < REF_CLK_RATE_MIN ||
+	    priv->ref_clk_rate > REF_CLK_RATE_MAX) {
+		dev_err(dev, "invalid ref clock rate %lu\n",
+			priv->ref_clk_rate);
+		return -EINVAL;
+	}
+	dev_dbg(dev, "ref clock rate: %lu\n", priv->ref_clk_rate);
+#endif
+
+	return 0;
+}
+
+static int imx_dw_dphy_remove(struct udevice *dev)
+{
+	return 0;
+}
+
+static const struct udevice_id imx_dw_mipi_dphy_of_match[] = {
+	{ .compatible = "fsl,imx93-mipi-dphy" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(imx_dw_mipi_dphy) = {
+	.name = "imx_dw_mipi_dphy",
+	.id = UCLASS_PHY,
+	.of_match = imx_dw_mipi_dphy_of_match,
+	.probe = imx_dw_dphy_probe,
+	.remove = imx_dw_dphy_remove,
+	.ops = &imx_dw_dphy_phy_ops,
+	.priv_auto	= sizeof(struct dw_dphy_priv),
+};
diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index 4fb0916a376..d991d5b5cc1 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -77,7 +77,6 @@ config PINCTRL_IMX8ULP
 config PINCTRL_IMX8
 	bool "IMX8 pinctrl driver"
 	depends on ARCH_IMX8 && PINCTRL_FULL
-	select DEVRES
 	select PINCTRL_IMX
 	select PINCTRL_IMX_SCU
 	help
@@ -92,7 +91,19 @@ config PINCTRL_IMX8
 config PINCTRL_IMX8M
 	bool "IMX8M pinctrl driver"
 	depends on ARCH_IMX8M && PINCTRL_FULL
-	select DEVRES
+	select PINCTRL_IMX
+	help
+	  Say Y here to enable the imx8m pinctrl driver
+
+	  This provides a simple pinctrl driver for i.MX8M SoC familiy.
+	  This feature depends on device tree configuration. This driver
+	  is different from the linux one, this is a simple implementation,
+	  only parses the 'fsl,pins' property and configure related
+	  registers.
+
+config PINCTRL_IMX93
+	bool "IMX8M pinctrl driver"
+	depends on ARCH_IMX9 && PINCTRL_FULL
 	select PINCTRL_IMX
 	help
 	  Say Y here to enable the imx8m pinctrl driver
diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile
index f2fe0d8efa6..331cd633003 100644
--- a/drivers/pinctrl/nxp/Makefile
+++ b/drivers/pinctrl/nxp/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_IMX8ULP)		+= pinctrl-imx8ulp.o
 obj-$(CONFIG_PINCTRL_IMX_SCU)		+= pinctrl-scu.o
 obj-$(CONFIG_PINCTRL_IMX8)		+= pinctrl-imx8.o
 obj-$(CONFIG_PINCTRL_IMX8M)		+= pinctrl-imx8m.o
+obj-$(CONFIG_PINCTRL_IMX93)		+= pinctrl-imx8m.o
 obj-$(CONFIG_PINCTRL_MXS)		+= pinctrl-mxs.o
 obj-$(CONFIG_PINCTRL_VYBRID)		+= pinctrl-vf610.o
 obj-$(CONFIG_PINCTRL_IMXRT)		+= pinctrl-imxrt.o
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8m.c b/drivers/pinctrl/nxp/pinctrl-imx8m.c
index 6ea66a080b2..316fe284d26 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx8m.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx8m.c
@@ -10,6 +10,10 @@
 
 static struct imx_pinctrl_soc_info imx8mq_pinctrl_soc_info __section(".data");
 
+static struct imx_pinctrl_soc_info imx93_pinctrl_soc_info = {
+	.flags = ZERO_OFFSET_VALID,
+};
+
 static int imx8mq_pinctrl_probe(struct udevice *dev)
 {
 	struct imx_pinctrl_soc_info *info =
@@ -23,6 +27,7 @@ static const struct udevice_id imx8m_pinctrl_match[] = {
 	{ .compatible = "fsl,imx8mm-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info },
 	{ .compatible = "fsl,imx8mn-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info },
 	{ .compatible = "fsl,imx8mp-iomuxc", .data = (ulong)&imx8mq_pinctrl_soc_info },
+	{ .compatible = "fsl,imx93-iomuxc", .data = (ulong)&imx93_pinctrl_soc_info },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index 93d2599d83c..2fe1b1d3875 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -39,6 +39,12 @@ config IMX8M_POWER_DOMAIN
 	  Enable support for manipulating NXP i.MX8M on-SoC power domains via
 	  requests to the ATF.
 
+config IMX93_BLK_CTRL
+	bool "Enable i.MX93 block control driver"
+	depends on POWER_DOMAIN && ARCH_IMX9
+	help
+	  Enable support for manipulating NXP i.MX93 on-SoC block control driver
+
 config MTK_POWER_DOMAIN
 	bool "Enable the MediaTek power domain driver"
 	depends on POWER_DOMAIN && ARCH_MEDIATEK
@@ -68,6 +74,23 @@ config SANDBOX_POWER_DOMAIN
 	  simply accepts requests to power on/off various HW modules without
 	  actually doing anything beyond a little error checking.
 
+config RESET_SCMI
+	bool "Enable SCMI reset domain driver"
+	select SCMI_FIRMWARE
+	help
+	  Enable this option if you want to support reset controller
+	  devices exposed by a SCMI agent based on SCMI reset domain
+	  protocol communication with a SCMI server.
+
+config SCMI_POWER_DOMAIN
+	bool "Enable the SCMI power domain driver"
+	depends on POWER_DOMAIN
+	select SCMI_FIRMWARE
+	help
+	  Enable this option if you want to support power domain controller
+	  devices exposed by a SCMI agent based on SCMI power domain
+	  protocol communication with a SCMI server.
+
 config TEGRA186_POWER_DOMAIN
 	bool "Enable Tegra186 BPMP-based power domain driver"
 	depends on TEGRA186_BPMP
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 7c8af67dbd6..17a1e22e0e4 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -8,11 +8,13 @@ obj-$(CONFIG_APPLE_PMGR_POWER_DOMAIN) += apple-pmgr.o
 obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o
 obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain-legacy.o imx8-power-domain.o
 obj-$(CONFIG_IMX8M_POWER_DOMAIN) += imx8m-power-domain.o
+obj-$(CONFIG_IMX93_BLK_CTRL) += imx93-blk-ctrl.o
 obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o
 obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o
 obj-$(CONFIG_MESON_EE_POWER_DOMAIN) += meson-ee-pwrc.o
 obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
 obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
+obj-$(CONFIG_SCMI_POWER_DOMAIN) += scmi-power-domain.o
 obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o
 obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o
 obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o
diff --git a/drivers/power/domain/imx8-power-domain-legacy.c b/drivers/power/domain/imx8-power-domain-legacy.c
index e2fae2dbc86..d10b94dc458 100644
--- a/drivers/power/domain/imx8-power-domain-legacy.c
+++ b/drivers/power/domain/imx8-power-domain-legacy.c
@@ -103,7 +103,6 @@ static int imx8_power_domain_on(struct power_domain *power_domain)
 	struct udevice *dev = power_domain->dev;
 	struct imx8_power_domain_plat *pdata;
 	struct imx8_power_domain_priv *ppriv;
-	sc_err_t ret;
 	int err;
 
 	struct power_domain parent_domain;
@@ -128,14 +127,19 @@ static int imx8_power_domain_on(struct power_domain *power_domain)
 		return 0;
 
 	if (pdata->resource_id != SC_R_NONE) {
-		if (!sc_rm_is_resource_owned(-1, pdata->resource_id))
+		if (!sc_rm_is_resource_owned(-1, pdata->resource_id)) {
 			printf("%s [%d] not owned by curr partition\n", dev->name, pdata->resource_id);
+#if defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY) || defined(CONFIG_TARGET_IMX8QM_MEK_A53_ONLY)
+			/* avoid failing probe, else some group of resources (gpios) may never work */
+			return 0;
+#endif
+		}
 
-		ret = sc_pm_set_resource_power_mode(-1, pdata->resource_id,
+		err = sc_pm_set_resource_power_mode(-1, pdata->resource_id,
 						    SC_PM_PW_MODE_ON);
-		if (ret) {
+		if (err) {
 			printf("Error: %s Power up failed! (error = %d)\n",
-			       dev->name, ret);
+			       dev->name, err);
 			return -EIO;
 		}
 	}
@@ -153,7 +157,7 @@ static int imx8_power_domain_off_node(struct power_domain *power_domain)
 	struct imx8_power_domain_priv *ppriv;
 	struct imx8_power_domain_priv *child_ppriv;
 	struct imx8_power_domain_plat *pdata;
-	sc_err_t ret;
+	int ret;
 
 	ppriv = dev_get_priv(dev);
 	pdata = dev_get_plat(dev);
@@ -204,7 +208,7 @@ static int imx8_power_domain_off_parentnodes(struct power_domain *power_domain)
 	struct imx8_power_domain_priv *ppriv;
 	struct imx8_power_domain_priv *child_ppriv;
 	struct imx8_power_domain_plat *pdata;
-	sc_err_t ret;
+	int ret;
 	struct power_domain parent_pd;
 
 	if (device_get_uclass_id(parent) == UCLASS_POWER_DOMAIN) {
diff --git a/drivers/power/domain/imx93-blk-ctrl.c b/drivers/power/domain/imx93-blk-ctrl.c
new file mode 100644
index 00000000000..71c0d271889
--- /dev/null
+++ b/drivers/power/domain/imx93-blk-ctrl.c
@@ -0,0 +1,259 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <power-domain-uclass.h>
+#include <asm/io.h>
+#include <dm/device-internal.h>
+#include <dm/device.h>
+#include <dt-bindings/power/imx93-power.h>
+#include <clk.h>
+
+#define BLK_SFT_RSTN	0x0
+#define BLK_CLK_EN	0x4
+
+#define BLK_MAX_CLKS 4
+#define DOMAIN_MAX_CLKS 4
+
+struct imx93_blk_ctrl_domain {
+	struct clk clks[DOMAIN_MAX_CLKS];
+};
+
+struct imx93_blk_ctrl {
+	void __iomem *base;
+	struct clk clks[BLK_MAX_CLKS];
+	struct imx93_blk_ctrl_domain *domains;
+};
+
+struct imx93_blk_ctrl_domain_data {
+	const char *name;
+	const char * const *clk_names;
+	int num_clks;
+	u32 rst_mask;
+	u32 clk_mask;
+};
+
+struct imx93_blk_ctrl_data {
+	int max_reg;
+	const struct imx93_blk_ctrl_domain_data *domains;
+	const struct imx93_blk_ctrl_domain_data *bus;
+	int num_domains;
+};
+
+static int imx93_blk_ctrl_request(struct power_domain *power_domain)
+{
+	return 0;
+}
+
+static int imx93_blk_ctrl_free(struct power_domain *power_domain)
+{
+	return 0;
+}
+
+static int imx93_blk_ctrl_enable_bus_clk(struct udevice *dev, bool enable)
+{
+	int ret, i;
+	struct imx93_blk_ctrl *priv = (struct imx93_blk_ctrl *)dev_get_priv(dev);
+	struct imx93_blk_ctrl_data *drv_data =
+		(struct imx93_blk_ctrl_data *)dev_get_driver_data(dev);
+
+	for (i = 0; i < drv_data->bus->num_clks; i++) {
+		if (enable)
+			ret = clk_enable(&priv->clks[i]);
+		else
+			ret = clk_disable(&priv->clks[i]);
+		if (ret) {
+			printf("Failed to %s bus clk %s\n", enable ? "enable" : "disable", drv_data->bus->clk_names[i]);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int imx93_blk_ctrl_enable_domain_clk(struct udevice *dev, ulong domain_id, bool enable)
+{
+	int ret, i;
+	struct imx93_blk_ctrl *priv = (struct imx93_blk_ctrl *)dev_get_priv(dev);
+	struct imx93_blk_ctrl_data *drv_data =
+		(struct imx93_blk_ctrl_data *)dev_get_driver_data(dev);
+
+	debug("%s num_clk %u\n", __func__, drv_data->domains[domain_id].num_clks);
+
+	for (i = 0; i < drv_data->domains[domain_id].num_clks; i++) {
+		debug("%s clk %s\n", __func__, drv_data->domains[domain_id].clk_names[i]);
+		if (enable)
+			ret = clk_enable(&priv->domains[domain_id].clks[i]);
+		else
+			ret = clk_disable(&priv->domains[domain_id].clks[i]);
+		if (ret) {
+			printf("Failed to %s domain clk %s\n", enable ? "enable" : "disable", drv_data->domains[domain_id].clk_names[i]);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int imx93_blk_ctrl_power_on(struct power_domain *power_domain)
+{
+	struct udevice *dev = power_domain->dev;
+	struct imx93_blk_ctrl *priv = (struct imx93_blk_ctrl *)dev_get_priv(dev);
+	struct imx93_blk_ctrl_data *drv_data =
+		(struct imx93_blk_ctrl_data *)dev_get_driver_data(dev);
+
+	debug("%s, id %lu\n", __func__, power_domain->id);
+
+	imx93_blk_ctrl_enable_bus_clk(dev, true);
+	imx93_blk_ctrl_enable_domain_clk(dev, power_domain->id, true);
+
+	/* ungate clk */
+	clrbits_le32(priv->base + BLK_CLK_EN, drv_data->domains[power_domain->id].clk_mask);
+
+	/* release reset */
+	setbits_le32(priv->base + BLK_SFT_RSTN, drv_data->domains[power_domain->id].rst_mask);
+
+	return 0;
+}
+
+static int imx93_blk_ctrl_power_off(struct power_domain *power_domain)
+{
+	struct udevice *dev = power_domain->dev;
+	struct imx93_blk_ctrl *priv = (struct imx93_blk_ctrl *)dev_get_priv(dev);
+	struct imx93_blk_ctrl_data *drv_data =
+		(struct imx93_blk_ctrl_data *)dev_get_driver_data(dev);
+
+	debug("%s, id %lu\n", __func__, power_domain->id);
+
+	/* assert reset */
+	clrbits_le32(priv->base + BLK_SFT_RSTN, drv_data->domains[power_domain->id].rst_mask);
+
+	/* gate clk */
+	setbits_le32(priv->base + BLK_CLK_EN, drv_data->domains[power_domain->id].clk_mask);
+
+	imx93_blk_ctrl_enable_domain_clk(dev, power_domain->id, false);
+
+	imx93_blk_ctrl_enable_bus_clk(dev, false);
+
+	return 0;
+}
+
+static int imx93_blk_ctrl_probe(struct udevice *dev)
+{
+	int ret, i, j;
+	struct imx93_blk_ctrl *priv = (struct imx93_blk_ctrl *)dev_get_priv(dev);
+	struct imx93_blk_ctrl_data *drv_data =
+		(struct imx93_blk_ctrl_data *)dev_get_driver_data(dev);
+
+	priv->base = dev_read_addr_ptr(dev);
+	if (!priv->base)
+		return -EINVAL;
+
+	priv->domains = kcalloc(drv_data->num_domains, sizeof(struct imx93_blk_ctrl_domain), GFP_KERNEL);
+
+	for (i = 0; i < drv_data->bus->num_clks; i++) {
+		ret = clk_get_by_name(dev, drv_data->bus->clk_names[i], &priv->clks[i]);
+		if (ret) {
+			printf("Failed to get clk %s\n", drv_data->bus->clk_names[i]);
+			return ret;
+		}
+	}
+
+	for (j = 0; j < drv_data->num_domains; j++) {
+		for (i = 0; i < drv_data->domains[j].num_clks; i++) {
+			ret = clk_get_by_name(dev, drv_data->domains[j].clk_names[i], &priv->domains[j].clks[i]);
+			if (ret) {
+				printf("Failed to get clk %s\n", drv_data->domains[j].clk_names[i]);
+				return ret;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int imx93_blk_ctrl_remove(struct udevice *dev)
+{
+	struct imx93_blk_ctrl *priv = (struct imx93_blk_ctrl *)dev_get_priv(dev);
+
+	kfree(priv->domains);
+
+	return 0;
+}
+
+static const struct imx93_blk_ctrl_domain_data imx93_media_blk_ctl_bus_data = {
+	.clk_names = (const char *[]){ "axi", "apb", "nic", },
+	.num_clks = 3,
+};
+
+static const struct imx93_blk_ctrl_domain_data imx93_media_blk_ctl_domain_data[] = {
+	[IMX93_MEDIABLK_PD_MIPI_DSI] = {
+		.name = "mediablk-mipi-dsi",
+		.clk_names = (const char *[]){ "dsi" },
+		.num_clks = 1,
+		.rst_mask = BIT(11) | BIT(12),
+		.clk_mask = BIT(11) | BIT(12),
+	},
+	[IMX93_MEDIABLK_PD_MIPI_CSI] = {
+		.name = "mediablk-mipi-csi",
+		.clk_names = (const char *[]){ "cam", "csi" },
+		.num_clks = 2,
+		.rst_mask = BIT(9) | BIT(10),
+		.clk_mask = BIT(9) | BIT(10),
+	},
+	[IMX93_MEDIABLK_PD_PXP] = {
+		.name = "mediablk-pxp",
+		.clk_names = (const char *[]){ "pxp" },
+		.num_clks = 1,
+		.rst_mask = BIT(7) | BIT(8),
+		.clk_mask = BIT(7) | BIT(8),
+	},
+	[IMX93_MEDIABLK_PD_LCDIF] = {
+		.name = "mediablk-lcdif",
+		.clk_names = (const char *[]){ "disp", "lcdif" },
+		.num_clks = 2,
+		.rst_mask = BIT(4) | BIT(5) | BIT(6),
+		.clk_mask = BIT(4) | BIT(5) | BIT(6),
+	},
+	[IMX93_MEDIABLK_PD_ISI] = {
+		.name = "mediablk-isi",
+		.clk_names = (const char *[]){ "isi" },
+		.num_clks = 1,
+		.rst_mask = BIT(2) | BIT(3),
+		.clk_mask = BIT(2) | BIT(3),
+	},
+};
+
+static const struct imx93_blk_ctrl_data imx93_media_blk_ctl_dev_data = {
+	.max_reg = 0x8,
+	.domains = imx93_media_blk_ctl_domain_data,
+	.bus = &imx93_media_blk_ctl_bus_data,
+	.num_domains = ARRAY_SIZE(imx93_media_blk_ctl_domain_data),
+};
+
+static const struct udevice_id imx93_blk_ctrl_ids[] = {
+	{ .compatible = "fsl,imx93-media-blk-ctrl", .data = (ulong)&imx93_media_blk_ctl_dev_data },
+	{ }
+};
+
+struct power_domain_ops imx93_blk_ctrl_ops = {
+	.request = imx93_blk_ctrl_request,
+	.rfree = imx93_blk_ctrl_free,
+	.on = imx93_blk_ctrl_power_on,
+	.off = imx93_blk_ctrl_power_off,
+};
+
+U_BOOT_DRIVER(imx93_blk_ctrl) = {
+	.name = "imx93_blk_ctrl",
+	.id = UCLASS_POWER_DOMAIN,
+	.of_match = imx93_blk_ctrl_ids,
+	.bind = dm_scan_fdt_dev,
+	.probe = imx93_blk_ctrl_probe,
+	.remove = imx93_blk_ctrl_remove,
+	.priv_auto	= sizeof(struct imx93_blk_ctrl),
+	.ops = &imx93_blk_ctrl_ops,
+};
diff --git a/drivers/power/domain/power-domain-uclass.c b/drivers/power/domain/power-domain-uclass.c
index 33f9206bd09..fbc3f212afa 100644
--- a/drivers/power/domain/power-domain-uclass.c
+++ b/drivers/power/domain/power-domain-uclass.c
@@ -11,6 +11,7 @@
 #include <malloc.h>
 #include <power-domain.h>
 #include <power-domain-uclass.h>
+#include <dm/uclass-internal.h>
 #include <dm/device-internal.h>
 
 static inline struct power_domain_ops *power_domain_dev_ops(struct udevice *dev)
@@ -33,6 +34,49 @@ static int power_domain_of_xlate_default(struct power_domain *power_domain,
 	return 0;
 }
 
+int power_domain_lookup_name(const char *name, struct power_domain *power_domain)
+{
+	struct udevice *dev;
+	struct power_domain_ops *ops;
+	int ret;
+
+	debug("%s(power_domain=%p name=%s)\n", __func__, power_domain, name);
+
+	ret = uclass_find_device_by_name(UCLASS_POWER_DOMAIN, name, &dev);
+	if (!ret) {
+		/* Probe the dev */
+		ret = device_probe(dev);
+		if (ret) {
+			printf("Power domain probe device %s failed: %d\n", name, ret);
+			return ret;
+		}
+		ops = power_domain_dev_ops(dev);
+
+		power_domain->dev = dev;
+		if (ops->of_xlate)
+			ret = ops->of_xlate(power_domain, NULL);
+		else
+			ret = power_domain_of_xlate_default(power_domain, NULL);
+		if (ret) {
+			debug("of_xlate() failed: %d\n", ret);
+			return ret;
+		}
+
+		ret = ops->request(power_domain);
+		if (ret) {
+			debug("ops->request() failed: %d\n", ret);
+			return ret;
+		}
+
+		debug("%s ok: %s\n", __func__, dev->name);
+
+		return 0;
+	}
+
+	printf("%s fail: %s, ret = %d\n", __func__, name, ret);
+	return -EINVAL;
+}
+
 int power_domain_get_by_index(struct udevice *dev,
 			      struct power_domain *power_domain, int index)
 {
@@ -137,8 +181,7 @@ static int dev_power_domain_ctrl(struct udevice *dev, bool on)
 	 * off their power-domain parent. So we will get here again and
 	 * again and will be stuck in an endless loop.
 	 */
-	if (!on && dev_get_parent(dev) == pd.dev &&
-	    device_get_uclass_id(dev) == UCLASS_POWER_DOMAIN)
+	if (!on && dev_get_parent(dev) == pd.dev)
 		return ret;
 
 	/*
diff --git a/drivers/power/domain/scmi-power-domain.c b/drivers/power/domain/scmi-power-domain.c
new file mode 100644
index 00000000000..b93dbde156f
--- /dev/null
+++ b/drivers/power/domain/scmi-power-domain.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2021 NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <power-domain-uclass.h>
+#include <scmi_agent.h>
+#include <scmi_protocols.h>
+#include <asm/types.h>
+#include <dm/device-internal.h>
+#include <dm/device.h>
+
+static int scmi_power_domain_request(struct power_domain *power_domain)
+{
+	return 0;
+}
+
+static int scmi_power_domain_free(struct power_domain *power_domain)
+{
+	return 0;
+}
+
+static int scmi_power_state_set(struct power_domain *power_domain, u32 state)
+{
+	struct scmi_power_set_state in = {
+		.domain = power_domain->id,
+		.flags = 0,
+		.state = state,
+	};
+	struct scmi_power_set_state_out out;
+	struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_POWER_DOMAIN,
+					  SCMI_POWER_STATE_SET,
+					  in, out);
+	int ret;
+
+	ret = devm_scmi_process_msg(power_domain->dev->parent, &msg);
+	if (ret)
+		return ret;
+
+	return scmi_to_linux_errno(out.status);
+}
+
+static int scmi_power_state_get(struct power_domain *power_domain, u32 *state)
+{
+	struct scmi_power_get_state in = {
+		.domain = power_domain->id,
+	};
+
+	struct scmi_power_get_state_out out;
+	struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_POWER_DOMAIN,
+					  SCMI_POWER_STATE_GET,
+					  in, out);
+	int ret;
+
+	ret = devm_scmi_process_msg(power_domain->dev->parent, &msg);
+	if (ret)
+		return ret;
+
+	ret = scmi_to_linux_errno(out.status);
+	if (ret < 0)
+		return ret;
+
+	*state = out.state;
+
+	return ret;
+}
+
+static int scmi_power_domain_power(struct power_domain *power_domain, bool power_on)
+{
+	int ret;
+	u32 state, ret_state;
+
+	if (power_on)
+		state = SCMI_POWER_STATE_GENERIC_ON;
+	else
+		state = SCMI_POWER_STATE_GENERIC_OFF;
+
+	ret = scmi_power_state_set(power_domain, state);
+	if (!ret)
+		ret = scmi_power_state_get(power_domain, &ret_state);
+	if (!ret && state != ret_state)
+		return -EIO;
+
+	return ret;
+}
+
+static int scmi_power_domain_on(struct power_domain *power_domain)
+{
+	debug("%s: id %lu\n", __func__, power_domain->id);
+
+	return scmi_power_domain_power(power_domain, true);
+}
+
+static int scmi_power_domain_off(struct power_domain *power_domain)
+{
+	debug("%s: id %lu\n", __func__, power_domain->id);
+
+	return scmi_power_domain_power(power_domain, false);
+}
+
+struct power_domain_ops scmi_power_domain_ops = {
+	.request = scmi_power_domain_request,
+	.rfree = scmi_power_domain_free,
+	.on = scmi_power_domain_on,
+	.off = scmi_power_domain_off,
+};
+
+U_BOOT_DRIVER(scmi_power_domain) = {
+	.name = "scmi_power_domain",
+	.id = UCLASS_POWER_DOMAIN,
+	.ops = &scmi_power_domain_ops,
+};
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 401cde32cf1..9556b13d791 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_$(SPL_)PMIC_LP87565) += lp87565.o
 obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
 
 obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
+obj-$(CONFIG_POWER_BD71837) += pmic_bd71837.o
 obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
 obj-$(CONFIG_POWER_PCA9450) += pmic_pca9450.o
 obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c
index a886647f193..4bd8c00a37d 100644
--- a/drivers/power/pmic/pca9450.c
+++ b/drivers/power/pmic/pca9450.c
@@ -83,6 +83,8 @@ static struct dm_pmic_ops pca9450_ops = {
 static const struct udevice_id pca9450_ids[] = {
 	{ .compatible = "nxp,pca9450a", .data = 0x25, },
 	{ .compatible = "nxp,pca9450b", .data = 0x25, },
+	{ .compatible = "nxp,pca9450c", .data = 0x25, },
+	{ .compatible = "nxp,pca9451a", .data = 0x25, },
 	{ }
 };
 
diff --git a/drivers/power/pmic/pmic_bd71837.c b/drivers/power/pmic/pmic_bd71837.c
new file mode 100644
index 00000000000..4b3cb4a70a8
--- /dev/null
+++ b/drivers/power/pmic/pmic_bd71837.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/bd71837.h>
+
+static const char bd71837_name[] = "BD71837";
+int power_bd71837_init (unsigned char bus) {
+	struct pmic *p = pmic_alloc();
+
+	if (!p) {
+		printf("%s: POWER allocation error!\n", __func__);
+		return -ENOMEM;
+	}
+
+	p->name = bd71837_name;
+	p->interface = PMIC_I2C;
+	p->number_of_regs = BD718XX_MAX_REGISTER;
+	p->hw.i2c.addr = 0x4b;
+	p->hw.i2c.tx_num = 1;
+	p->bus = bus;
+
+	printf("power_bd71837_init\n");
+
+	return 0;
+}
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index b57714111b5..0691f891d1c 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -212,4 +212,11 @@ config RESET_DRA7
 	help
 	  Support for TI DRA7-RESET subsystem. Basic Assert/Deassert
 	  is supported.
+
+config RESET_DISPMIX
+	bool "i.MX8M Display MIX Reset Driver"
+	depends on DM_RESET && ARCH_IMX8M && DM_VIDEO
+	default n
+	help
+	  Support for reset controller on i.MX8M SoCs.
 endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 97e3a782c0d..85f9eacaf43 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -31,3 +31,4 @@ obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
 obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o
 obj-$(CONFIG_RESET_DRA7) += reset-dra7.o
+obj-$(CONFIG_RESET_DISPMIX) += reset-dispmix.o
diff --git a/drivers/reset/reset-dispmix.c b/drivers/reset/reset-dispmix.c
new file mode 100644
index 00000000000..cfc1c5f0e31
--- /dev/null
+++ b/drivers/reset/reset-dispmix.c
@@ -0,0 +1,290 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <regmap.h>
+#include <reset.h>
+#include <reset-uclass.h>
+#include <regmap.h>
+#include <dt-bindings/reset/imx8mm-dispmix.h>
+#include <dt-bindings/reset/imx8mn-dispmix.h>
+
+/* DISPMIX GPR registers */
+#define DISPLAY_MIX_SFT_RSTN_CSR		0x00
+#define DISPLAY_MIX_CLK_EN_CSR		0x00
+#define GPR_MIPI_RESET_DIV			0x00
+
+struct dispmix_reset_priv {
+	struct regmap *map;
+	bool active_low;
+};
+
+struct dispmix_reset_entry {
+	uint32_t reg_off;
+	uint32_t bit_off;
+};
+
+struct dispmix_reset_drvdata {
+	const struct dispmix_reset_entry *resets;
+	ulong nr_resets;
+};
+
+#define RESET_ENTRY(id, reg, bit)			\
+	[id] = { .reg_off = (reg), .bit_off = (bit) }
+
+static const struct dispmix_reset_entry imx8mm_sft_rstn[] = {
+	/* dispmix reset entry */
+	RESET_ENTRY(IMX8MM_CSI_BRIDGE_CHIP_RESET,
+		    DISPLAY_MIX_SFT_RSTN_CSR, 0),
+	RESET_ENTRY(IMX8MM_CSI_BRIDGE_IPG_HARD_ASYNC_RESET,
+		    DISPLAY_MIX_SFT_RSTN_CSR, 1),
+	RESET_ENTRY(IMX8MM_CSI_BRIDGE_CSI_HRESET,
+		    DISPLAY_MIX_SFT_RSTN_CSR, 2),
+	RESET_ENTRY(IMX8MM_CAMERA_PIXEL_RESET,
+		    DISPLAY_MIX_SFT_RSTN_CSR, 3),
+	RESET_ENTRY(IMX8MM_MIPI_CSI_I_PRESET,
+		    DISPLAY_MIX_SFT_RSTN_CSR, 4),
+	RESET_ENTRY(IMX8MM_MIPI_DSI_I_PRESET,
+		    DISPLAY_MIX_SFT_RSTN_CSR, 5),
+	RESET_ENTRY(IMX8MM_BUS_RSTN_BLK_SYNC,
+		    DISPLAY_MIX_SFT_RSTN_CSR, 6),
+};
+
+static const struct dispmix_reset_entry imx8mm_clk_en[] = {
+	/* dispmix clock enable entry */
+	RESET_ENTRY(IMX8MM_CSI_BRIDGE_CSI_HCLK_EN,
+		    DISPLAY_MIX_CLK_EN_CSR,  0),
+	RESET_ENTRY(IMX8MM_CSI_BRIDGE_SPU_CLK_EN,
+		    DISPLAY_MIX_CLK_EN_CSR,  1),
+	RESET_ENTRY(IMX8MM_CSI_BRIDGE_MEM_WRAPPER_CLK_EN,
+		    DISPLAY_MIX_CLK_EN_CSR,  2),
+	RESET_ENTRY(IMX8MM_CSI_BRIDGE_IPG_CLK_EN,
+		    DISPLAY_MIX_CLK_EN_CSR,  3),
+	RESET_ENTRY(IMX8MM_CSI_BRIDGE_IPG_CLK_S_EN,
+		    DISPLAY_MIX_CLK_EN_CSR,  4),
+	RESET_ENTRY(IMX8MM_CSI_BRIDGE_IPG_CLK_S_RAW_EN,
+		    DISPLAY_MIX_CLK_EN_CSR,  5),
+	RESET_ENTRY(IMX8MM_LCDIF_APB_CLK_EN,
+		    DISPLAY_MIX_CLK_EN_CSR,  6),
+	RESET_ENTRY(IMX8MM_LCDIF_PIXEL_CLK_EN,
+		    DISPLAY_MIX_CLK_EN_CSR,  7),
+	RESET_ENTRY(IMX8MM_MIPI_DSI_PCLK_EN,
+		    DISPLAY_MIX_CLK_EN_CSR,  8),
+	RESET_ENTRY(IMX8MM_MIPI_DSI_CLKREF_EN,
+		    DISPLAY_MIX_CLK_EN_CSR,  9),
+	RESET_ENTRY(IMX8MM_MIPI_CSI_ACLK_EN,
+		    DISPLAY_MIX_CLK_EN_CSR, 10),
+	RESET_ENTRY(IMX8MM_MIPI_CSI_PCLK_EN,
+		    DISPLAY_MIX_CLK_EN_CSR, 11),
+	RESET_ENTRY(IMX8MM_BUS_BLK_CLK_EN,
+		    DISPLAY_MIX_CLK_EN_CSR, 12),
+};
+
+static const struct dispmix_reset_entry imx8mm_mipi_rst[] = {
+	/* mipi lanes reset entry */
+	RESET_ENTRY(IMX8MM_MIPI_S_RESET,
+		    GPR_MIPI_RESET_DIV, 16),
+	RESET_ENTRY(IMX8MM_MIPI_M_RESET,
+		    GPR_MIPI_RESET_DIV, 17),
+};
+
+static const struct dispmix_reset_entry imx8mn_sft_rstn[] = {
+	/* dispmix reset entry */
+	RESET_ENTRY(IMX8MN_MIPI_DSI_PCLK_RESET,
+		    DISPLAY_MIX_SFT_RSTN_CSR, 0),
+	RESET_ENTRY(IMX8MN_MIPI_DSI_CLKREF_RESET,
+		    DISPLAY_MIX_SFT_RSTN_CSR, 1),
+	RESET_ENTRY(IMX8MN_MIPI_CSI_PCLK_RESET,
+		    DISPLAY_MIX_SFT_RSTN_CSR, 2),
+	RESET_ENTRY(IMX8MN_MIPI_CSI_ACLK_RESET,
+		    DISPLAY_MIX_SFT_RSTN_CSR, 3),
+	RESET_ENTRY(IMX8MN_LCDIF_PIXEL_CLK_RESET,
+		    DISPLAY_MIX_SFT_RSTN_CSR, 4),
+	RESET_ENTRY(IMX8MN_LCDIF_APB_CLK_RESET,
+		    DISPLAY_MIX_SFT_RSTN_CSR, 5),
+	RESET_ENTRY(IMX8MN_ISI_PROC_CLK_RESET,
+		    DISPLAY_MIX_SFT_RSTN_CSR, 6),
+	RESET_ENTRY(IMX8MN_ISI_APB_CLK_RESET,
+		    DISPLAY_MIX_SFT_RSTN_CSR, 7),
+	RESET_ENTRY(IMX8MN_BUS_BLK_CLK_RESET,
+		    DISPLAY_MIX_SFT_RSTN_CSR, 8),
+};
+
+static const struct dispmix_reset_entry imx8mn_clk_en[] = {
+	/* dispmix clock enable entry */
+	RESET_ENTRY(IMX8MN_MIPI_DSI_PCLK_EN,
+		    DISPLAY_MIX_CLK_EN_CSR,  0),
+	RESET_ENTRY(IMX8MN_MIPI_DSI_CLKREF_EN,
+		    DISPLAY_MIX_CLK_EN_CSR,  1),
+	RESET_ENTRY(IMX8MN_MIPI_CSI_PCLK_EN,
+		    DISPLAY_MIX_CLK_EN_CSR,  2),
+	RESET_ENTRY(IMX8MN_MIPI_CSI_ACLK_EN,
+		    DISPLAY_MIX_CLK_EN_CSR,  3),
+	RESET_ENTRY(IMX8MN_LCDIF_PIXEL_CLK_EN,
+		    DISPLAY_MIX_CLK_EN_CSR,  4),
+	RESET_ENTRY(IMX8MN_LCDIF_APB_CLK_EN,
+		    DISPLAY_MIX_CLK_EN_CSR,  5),
+	RESET_ENTRY(IMX8MN_ISI_PROC_CLK_EN,
+		    DISPLAY_MIX_CLK_EN_CSR,  6),
+	RESET_ENTRY(IMX8MN_ISI_APB_CLK_EN,
+		    DISPLAY_MIX_CLK_EN_CSR,  7),
+	RESET_ENTRY(IMX8MN_BUS_BLK_CLK_EN,
+		    DISPLAY_MIX_CLK_EN_CSR,  8),
+};
+
+static const struct dispmix_reset_entry imx8mn_mipi_rst[] = {
+	/* mipi lanes reset entry */
+	RESET_ENTRY(IMX8MN_MIPI_S_RESET,
+		    GPR_MIPI_RESET_DIV, 16),
+	RESET_ENTRY(IMX8MN_MIPI_M_RESET,
+		    GPR_MIPI_RESET_DIV, 17),
+};
+
+static const struct dispmix_reset_drvdata imx8mm_sft_rstn_pdata = {
+	.resets    = imx8mm_sft_rstn,
+	.nr_resets = IMX8MM_DISPMIX_SFT_RSTN_NUM,
+};
+
+static const struct dispmix_reset_drvdata imx8mm_clk_en_pdata = {
+	.resets    = imx8mm_clk_en,
+	.nr_resets = IMX8MM_DISPMIX_CLK_EN_NUM,
+};
+
+static const struct dispmix_reset_drvdata imx8mm_mipi_rst_pdata = {
+	.resets    = imx8mm_mipi_rst,
+	.nr_resets = IMX8MM_MIPI_RESET_NUM,
+};
+
+static const struct dispmix_reset_drvdata imx8mn_sft_rstn_pdata = {
+	.resets    = imx8mn_sft_rstn,
+	.nr_resets = IMX8MN_DISPMIX_SFT_RSTN_NUM,
+};
+
+static const struct dispmix_reset_drvdata imx8mn_clk_en_pdata = {
+	.resets    = imx8mn_clk_en,
+	.nr_resets = IMX8MN_DISPMIX_CLK_EN_NUM,
+};
+
+static const struct dispmix_reset_drvdata imx8mn_mipi_rst_pdata = {
+	.resets    = imx8mn_mipi_rst,
+	.nr_resets = IMX8MN_MIPI_RESET_NUM,
+};
+
+static const struct udevice_id dispmix_reset_dt_ids[] = {
+	{
+		.compatible = "fsl,imx8mm-dispmix-sft-rstn",
+		.data = (ulong)&imx8mm_sft_rstn_pdata,
+	},
+	{
+		.compatible = "fsl,imx8mm-dispmix-clk-en",
+		.data = (ulong)&imx8mm_clk_en_pdata,
+	},
+	{
+		.compatible = "fsl,imx8mm-dispmix-mipi-rst",
+		.data = (ulong)&imx8mm_mipi_rst_pdata,
+	},
+	{
+		.compatible = "fsl,imx8mn-dispmix-sft-rstn",
+		.data = (ulong)&imx8mn_sft_rstn_pdata,
+	},
+	{
+		.compatible = "fsl,imx8mn-dispmix-clk-en",
+		.data = (ulong)&imx8mn_clk_en_pdata,
+	},
+	{
+		.compatible = "fsl,imx8mn-dispmix-mipi-rst",
+		.data = (ulong)&imx8mn_mipi_rst_pdata,
+	},
+	{ /* sentinel */ }
+};
+
+static int dispmix_reset_assert(struct reset_ctl *rst)
+{
+	const struct dispmix_reset_entry *rstent;
+	struct dispmix_reset_priv *priv = (struct dispmix_reset_priv *)dev_get_priv(rst->dev);
+	const struct dispmix_reset_drvdata *drvdata = (const struct dispmix_reset_drvdata *)dev_get_driver_data(rst->dev);
+
+
+	if (rst->id >= drvdata->nr_resets) {
+		pr_info("dispmix reset: %lu is not a valid line\n", rst->id);
+		return -EINVAL;
+	}
+
+	rstent = &drvdata->resets[rst->id];
+
+	regmap_update_bits(priv->map, rstent->reg_off,
+			   1 << rstent->bit_off,
+			   !priv->active_low << rstent->bit_off);
+
+	return 0;
+}
+
+static int dispmix_reset_deassert(struct reset_ctl *rst)
+{
+	const struct dispmix_reset_entry *rstent;
+	struct dispmix_reset_priv *priv = (struct dispmix_reset_priv *)dev_get_priv(rst->dev);
+	const struct dispmix_reset_drvdata *drvdata =
+		(const struct dispmix_reset_drvdata *)dev_get_driver_data(rst->dev);
+
+
+	if (rst->id >= drvdata->nr_resets) {
+		pr_info("dispmix reset: %lu is not a valid line\n", rst->id);
+		return -EINVAL;
+	}
+
+	rstent = &drvdata->resets[rst->id];
+
+	regmap_update_bits(priv->map, rstent->reg_off,
+			   1 << rstent->bit_off,
+			   !!priv->active_low << rstent->bit_off);
+
+	return 0;
+}
+
+static int dispmix_reset_free(struct reset_ctl *rst)
+{
+	return 0;
+}
+
+static int dispmix_reset_request(struct reset_ctl *rst)
+{
+	return 0;
+}
+
+static const struct reset_ops dispmix_reset_ops = {
+	.request = dispmix_reset_request,
+	.rfree = dispmix_reset_free,
+	.rst_assert   = dispmix_reset_assert,
+	.rst_deassert = dispmix_reset_deassert,
+};
+
+static int dispmix_reset_probe(struct udevice *dev)
+{
+	struct dispmix_reset_priv *priv = (struct dispmix_reset_priv *)dev_get_priv(dev);
+	int ret;
+
+	priv->active_low = dev_read_bool(dev, "active_low");
+
+	ret = regmap_init_mem(dev_ofnode(dev), &priv->map);
+	if (ret) {
+		debug("%s: Could not initialize regmap (err = %d)\n", dev->name,
+		      ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+U_BOOT_DRIVER(dispmix_reset) = {
+	.name = "dispmix_reset",
+	.id = UCLASS_RESET,
+	.of_match = dispmix_reset_dt_ids,
+	.ops = &dispmix_reset_ops,
+	.probe = dispmix_reset_probe,
+	.priv_auto = sizeof(struct dispmix_reset_priv),
+};
diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c
index ca9f00a8f24..2464b7ca860 100644
--- a/drivers/reset/reset-uclass.c
+++ b/drivers/reset/reset-uclass.c
@@ -144,6 +144,42 @@ int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk)
 	return __reset_get_bulk(dev, dev_ofnode(dev), bulk);
 }
 
+int reset_get_bulk_nodev(ofnode node, struct reset_ctl_bulk *bulk)
+{
+	int i, ret, err, count;
+
+	bulk->count = 0;
+
+	count = ofnode_count_phandle_with_args(node, "resets", "#reset-cells",
+					       0);
+	if (count < 1)
+		return count;
+
+	bulk->resets = kzalloc(count * sizeof(struct reset_ctl),
+				    GFP_KERNEL);
+	if (!bulk->resets)
+		return -ENOMEM;
+
+	for (i = 0; i < count; i++) {
+		ret = reset_get_by_index_nodev(node, i, &bulk->resets[i]);
+		if (ret < 0)
+			goto bulk_get_err;
+
+		++bulk->count;
+	}
+
+	return 0;
+
+bulk_get_err:
+	err = reset_release_all(bulk->resets, bulk->count);
+	if (err)
+		debug("%s: could release all resets\n",
+		      __func__);
+
+	return ret;
+}
+
+
 int reset_get_by_name(struct udevice *dev, const char *name,
 		     struct reset_ctl *reset_ctl)
 {
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index f30f352bd7a..6825e88e040 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -200,8 +200,17 @@ static void _serial_putc(struct udevice *dev, char ch)
 
 static void _serial_puts(struct udevice *dev, const char *str)
 {
-	while (*str)
-		_serial_putc(dev, *str++);
+	struct dm_serial_ops *ops = serial_get_ops(dev);
+	int err;
+
+	if (ops->puts) {
+		do {
+			err = ops->puts(dev, str);
+		} while (err == -EAGAIN);
+	} else {
+		while (*str)
+			_serial_putc(dev, *str++);
+	}
 }
 
 static int __serial_getc(struct udevice *dev)
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index ebbd21916d7..38611b00b0d 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -128,6 +128,7 @@ serial_initfunc(pl01x_serial_initialize);
 serial_initfunc(pxa_serial_initialize);
 serial_initfunc(sh_serial_initialize);
 serial_initfunc(mtk_serial_initialize);
+serial_initfunc(xen_debug_serial_initialize);
 
 /**
  * serial_register() - Register serial driver with serial driver core
@@ -182,6 +183,7 @@ int serial_initialize(void)
 	pxa_serial_initialize();
 	sh_serial_initialize();
 	mtk_serial_initialize();
+	xen_debug_serial_initialize();
 
 	serial_assign(default_serial_console()->name);
 
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index ca49ef73723..064c4c7406d 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -54,11 +54,7 @@
 #define FIFO_RXSIZE_MASK	0x7
 #define FIFO_RXSIZE_OFF	0
 #define FIFO_TXFE		0x80
-#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT)
 #define FIFO_RXFE		0x08
-#else
-#define FIFO_RXFE		0x40
-#endif
 
 #define WATER_TXWATER_OFF	0
 #define WATER_RXWATER_OFF	16
@@ -489,18 +485,30 @@ static int lpuart_serial_probe(struct udevice *dev)
 {
 #if CONFIG_IS_ENABLED(CLK)
 	struct clk per_clk;
+	struct clk ipg_clk;
 	int ret;
 
 	ret = clk_get_by_name(dev, "per", &per_clk);
 	if (!ret) {
 		ret = clk_enable(&per_clk);
 		if (ret) {
-			dev_err(dev, "Failed to get per clk: %d\n", ret);
+			dev_err(dev, "Failed to enable per clk: %d\n", ret);
 			return ret;
 		}
 	} else {
 		debug("%s: Failed to get per clk: %d\n", __func__, ret);
 	}
+
+	ret = clk_get_by_name(dev, "ipg", &ipg_clk);
+	if (!ret) {
+		ret = clk_enable(&ipg_clk);
+		if (ret) {
+			dev_err(dev, "Failed to enable ipg clk: %d\n", ret);
+			return ret;
+		}
+	} else {
+		debug("%s: Failed to get ipg clk: %d\n", __func__, ret);
+	}
 #endif
 
 	if (is_lpuart32(dev))
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index e4970a169bd..058f526b2cc 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -217,12 +217,27 @@ static void mxc_serial_putc(const char c)
 		WATCHDOG_RESET();
 }
 
-/* Test whether a character is in the RX buffer */
+/*
+ * Test whether a character is in the RX buffer
+ */
+static int one_time_rx_line_always_low_workaround_needed = 1;
 static int mxc_serial_tstc(void)
 {
 	/* If receive fifo is empty, return false */
 	if (readl(&mxc_base->ts) & UTS_RXEMPTY)
 		return 0;
+
+	/* Empty RX FIFO if receiver is stuck because of RXD line being low */
+	if (one_time_rx_line_always_low_workaround_needed) {
+		one_time_rx_line_always_low_workaround_needed = 0;
+		if (!(readl(&mxc_base->sr2) & USR2_RDR)) {
+			while (!(readl(&mxc_base->ts) & UTS_RXEMPTY)) {
+				(void) readl(&mxc_base->rxd);
+			}
+			return 0;
+		}
+	}
+
 	return 1;
 }
 
diff --git a/drivers/serial/serial_xen.c b/drivers/serial/serial_xen.c
index ab318b06462..039baf43a81 100644
--- a/drivers/serial/serial_xen.c
+++ b/drivers/serial/serial_xen.c
@@ -180,3 +180,63 @@ U_BOOT_DRIVER(serial_xen) = {
 	.flags			= DM_FLAG_PRE_RELOC,
 #endif
 };
+
+#ifndef CONFIG_DM_SERIAL
+extern void xenprintf(const char *buf);
+extern void xenprintc(const char c);
+
+static void xen_debug_serial_putc(const char c)
+{
+	/* If \n, also do \r */
+	if (c == '\n')
+		serial_putc('\r');
+
+	xenprintc(c);
+}
+
+static void xen_debug_serial_puts(const char *buf)
+{
+	xenprintf(buf);
+}
+
+static int xen_debug_serial_start(void)
+{
+	return 0;
+}
+
+static void xen_debug_serial_setbrg(void)
+{
+
+}
+
+static int xen_debug_serial_getc(void)
+{
+	return 0;
+}
+
+static int xen_debug_serial_tstc(void)
+{
+	return 0;
+}
+
+static struct serial_device xen_debug_serial_drv = {
+	.name	= "xen_debug_serial",
+	.start	= xen_debug_serial_start,
+	.stop	= NULL,
+	.setbrg	= xen_debug_serial_setbrg,
+	.putc	= xen_debug_serial_putc,
+	.puts	= xen_debug_serial_puts,
+	.getc	= xen_debug_serial_getc,
+	.tstc	= xen_debug_serial_tstc,
+};
+
+void xen_debug_serial_initialize(void)
+{
+	serial_register(&xen_debug_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+	return &xen_debug_serial_drv;
+}
+#endif
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 423a7571411..c633be584e4 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -497,6 +497,13 @@ config FSL_ESPI
 	  access the SPI interface and SPI NOR flash on platforms embedding
 	  this Freescale eSPI IP core.
 
+config FSL_FSPI_NAND
+	bool "Freescale FlexSPI driver for SPI NAND"
+	help
+	  Enable the Freescale FlexSPI (FSPI) NAND driver. This driver can be
+	  used to access the SPI NAND flash on platforms embedding this
+	  Freescale IP core.
+
 config SH_QSPI
 	bool "Renesas Quad SPI driver"
 	help
@@ -517,4 +524,10 @@ config SYNQUACER_SPI
 	  be used to access the SPI interface and SPI NOR flash on platforms
 	  embedding this HS-SPI IP core.
 
+config FSL_LPSPI
+	bool "FSL LPSPI Driver"
+	help
+	  Enable the FSL LPSPI controller driver. This driver can be used
+	  on various i.MX SoCs such as i.MX7ULP/8QM/8QXP/8DX/8DXL.
+
 endif # menu "SPI Support"
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 7f43f843ca9..2da3bf3bb40 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -33,6 +33,8 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
 obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
 obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
 obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o
+obj-$(CONFIG_FSL_LPSPI) += fsl_lpspi.o
+obj-$(CONFIG_FSL_FSPI_NAND) += fsl_fspi_nand.o
 obj-$(CONFIG_ICH_SPI) +=  ich.o
 obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o
 obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
diff --git a/drivers/spi/fsl_fspi_nand.c b/drivers/spi/fsl_fspi_nand.c
new file mode 100644
index 00000000000..f5551ccc50b
--- /dev/null
+++ b/drivers/spi/fsl_fspi_nand.c
@@ -0,0 +1,1057 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ */
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <dm.h>
+#include <errno.h>
+#include <watchdog.h>
+#include <clk.h>
+#include "fsl_fspi.h"
+#include <spi-mem.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FSL_FSPI_NAND_SIZE SZ_4G
+#define FSL_FSPI_NAND_NUM 1
+
+#ifdef CONFIG_IMX8ULP
+#define RX_BUFFER_SIZE		0x400
+#else
+#define RX_BUFFER_SIZE		0x200
+#endif
+#define TX_BUFFER_SIZE		0x400
+#define AHB_BUFFER_SIZE		0x800
+
+#define FLASH_STATUS_WEL	0x02
+
+#define FSPI_NAND_CAS 12
+
+/* SEQID */
+enum fspi_lut_id {
+	SEQID_RESET = 0,
+	SEQID_WREN = 1,
+	SEQID_READID = 2,
+	SEQID_SET_FEATURE = 3,
+	SEQID_GET_FEATURE = 4,
+	SEQID_BLK_ERASE	= 5,
+	SEQID_PAGE_READ = 6,
+	SEQID_PROG_EXEC = 7,
+	SEQID_READ_FROM_CACHE_COMMON = 8,
+	SEQID_PROG_LOAD_COMMON = 9,
+	SEQID_END,
+};
+
+enum fspi_read_cache_id {
+	ID_READ_FROM_CACHE_NORMAL = 0,
+	ID_READ_FROM_CACHE_FAST = 1,
+	ID_READ_FROM_CACHE_X2 = 2,
+	ID_READ_FROM_CACHE_X4 = 3,
+	ID_READ_FROM_CACHE_DUALIO = 4,
+	ID_READ_FROM_CACHE_QUADIO = 5,
+	ID_READ_FROM_CACHE_END,
+};
+
+enum fspi_prog_load_id {
+	ID_PROG_LOAD = 0,
+	ID_PROG_LOAD_RANDOM = 1,
+	ID_PROG_LOAD_X4 = 2,
+	ID_PROG_LOAD_RANDOM_X4 = 3,
+	ID_PROG_LOAD_END,
+};
+
+/* SPI NAND CMD */
+#define SPINAND_CMD_RESET		0xff
+#define SPINAND_CMD_WREN	0x06
+#define SPINAND_CMD_READID	0x9f
+#define SPINAND_CMD_SET_FEATURE	0x1f
+#define SPINAND_CMD_GET_FEATURE	0x0f
+#define SPINAND_CMD_BLK_ERASE	0xd8
+#define SPINAND_CMD_PAGE_READ	0x13
+#define SPINAND_CMD_PAGE_READ_FROM_CACHE_NORMAL	0x03
+#define SPINAND_CMD_PAGE_READ_FROM_CACHE_FAST	0x0b
+#define SPINAND_CMD_PAGE_READ_FROM_CACHE_X2	0x3b
+#define SPINAND_CMD_PAGE_READ_FROM_CACHE_X4	0x6b
+#define SPINAND_CMD_PAGE_READ_FROM_CACHE_DUALIO	0xbb
+#define SPINAND_CMD_PAGE_READ_FROM_CACHE_QUADIO	0xeb
+#define SPINAND_CMD_PROG_EXEC	0x10
+#define SPINAND_CMD_PROG_LOAD	0x02
+#define SPINAND_CMD_PROG_LOAD_RANDOM	0x84
+#define SPINAND_CMD_PROG_LOAD_X4	0x32
+#define SPINAND_CMD_PROG_LOAD_RANDOM_X4	0x34
+
+/* fsl_fspi_platdata flags */
+#define FSPI_FLAG_REGMAP_ENDIAN_BIG	BIT(0)
+
+/* default SCK frequency, unit: HZ */
+#define FSL_FSPI_DEFAULT_SCK_FREQ	50000000
+
+/* FSPI max chipselect signals number */
+#define FSL_FSPI_MAX_CHIPSELECT_NUM     4
+
+/**
+ * struct fsl_fspi_platdata - platform data for NXP FSPI
+ *
+ * @flags: Flags for FSPI FSPI_FLAG_...
+ * @speed_hz: Default SCK frequency
+ * @reg_base: Base address of FSPI registers
+ * @amba_base: Base address of FSPI memory mapping
+ * @amba_total_size: size of FSPI memory mapping
+ * @flash_num: Number of active slave devices
+ * @num_chipselect: Number of FSPI chipselect signals
+ */
+struct fsl_fspi_platdata {
+	u32 flags;
+	u32 speed_hz;
+	u32 reg_base;
+	u32 amba_base;
+	u32 amba_total_size;
+	u32 flash_num;
+	u32 num_chipselect;
+};
+
+/**
+ * struct fsl_fspi_priv - private data for NXP FSPI
+ *
+ * @flags: Flags for FSPI FSPI_FLAG_...
+ * @bus_clk: FSPI input clk frequency
+ * @speed_hz: Default SCK frequency
+ * @cur_seqid: current LUT table sequence id
+ * @sf_addr: flash access offset
+ * @amba_base: Base address of FSPI memory mapping of every CS
+ * @amba_total_size: size of FSPI memory mapping
+ * @cur_amba_base: Base address of FSPI memory mapping of current CS
+ * @flash_num: Number of active slave devices
+ * @num_chipselect: Number of FSPI chipselect signals
+ * @regs: Point to FSPI register structure for I/O access
+ */
+struct fsl_fspi_priv {
+	u32 flags;
+	u32 bus_clk;
+	u32 speed_hz;
+	u32 cur_seqid;
+	u32 sf_addr;
+	u32 amba_base[FSL_FSPI_MAX_CHIPSELECT_NUM];
+	u32 amba_total_size;
+	u32 cur_amba_base;
+	u32 flash_num;
+	u32 num_chipselect;
+	struct fsl_fspi_regs *regs;
+};
+
+struct fspi_cmd_func_pair {
+	u8 cmd;
+	int (*fspi_op_func)(struct fsl_fspi_priv *priv, u32 seqid, const struct spi_mem_op *op);
+};
+
+const u32 read_cache_lut[ID_READ_FROM_CACHE_END][4] = {
+	/* Read from cache normal */
+	{
+		OPRND0(SPINAND_CMD_PAGE_READ_FROM_CACHE_NORMAL) |
+			PAD0(LUT_PAD1) | INSTR0(LUT_CMD)  | OPRND1(0) |
+			PAD1(LUT_PAD1) | INSTR1(LUT_MODE4),
+		OPRND0(ADDR12BIT) | PAD0(LUT_PAD1) | INSTR0(LUT_CADDR_SDR) |
+			OPRND1(8) | PAD1(LUT_PAD1) | INSTR1(LUT_DUMMY),
+		OPRND0(0) | PAD0(LUT_PAD1) | INSTR0(LUT_READ),
+		0,
+	},
+	/* Read from cache fast */
+	{
+		OPRND0(SPINAND_CMD_PAGE_READ_FROM_CACHE_FAST) |
+			PAD0(LUT_PAD1) | INSTR0(LUT_CMD)  | OPRND1(0) |
+			PAD1(LUT_PAD1) | INSTR1(LUT_MODE4),
+		OPRND0(ADDR12BIT) | PAD0(LUT_PAD1) | INSTR0(LUT_CADDR_SDR) |
+			OPRND1(8) | PAD1(LUT_PAD1) | INSTR1(LUT_DUMMY),
+		OPRND0(0) | PAD0(LUT_PAD1) | INSTR0(LUT_READ),
+		0,
+	},
+	/* Read from cache x2 */
+	{
+		OPRND0(SPINAND_CMD_PAGE_READ_FROM_CACHE_X2) |
+			PAD0(LUT_PAD1) | INSTR0(LUT_CMD)  | OPRND1(0) |
+			PAD1(LUT_PAD1) | INSTR1(LUT_MODE4),
+		OPRND0(ADDR12BIT) | PAD0(LUT_PAD1) | INSTR0(LUT_CADDR_SDR) | OPRND1(8) |
+			PAD1(LUT_PAD1) | INSTR1(LUT_DUMMY),
+		OPRND0(0) | PAD0(LUT_PAD2) | INSTR0(LUT_READ),
+		0,
+	},
+	/* Read from cache x4 */
+	{
+		OPRND0(SPINAND_CMD_PAGE_READ_FROM_CACHE_X4) |
+			PAD0(LUT_PAD1) | INSTR0(LUT_CMD)  | OPRND1(0) |
+			PAD1(LUT_PAD1) | INSTR1(LUT_MODE4),
+		OPRND0(ADDR12BIT) | PAD0(LUT_PAD1) | INSTR0(LUT_CADDR_SDR) | OPRND1(8) |
+			PAD1(LUT_PAD1) | INSTR1(LUT_DUMMY),
+		OPRND0(0) | PAD0(LUT_PAD4) | INSTR0(LUT_READ),
+		0,
+	},
+	/* Read from cache dual IO */
+	{
+		OPRND0(SPINAND_CMD_PAGE_READ_FROM_CACHE_DUALIO) |
+			PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(0) |
+			PAD1(LUT_PAD2) | INSTR1(LUT_MODE4),
+		OPRND0(ADDR12BIT) | PAD0(LUT_PAD2) | INSTR0(LUT_CADDR_SDR) | OPRND1(4) |
+			PAD1(LUT_PAD2) | INSTR1(LUT_DUMMY),
+		OPRND0(0) | PAD0(LUT_PAD2) | INSTR0(LUT_READ),
+		0,
+	},
+	/* Read from cache Quad IO */
+	{
+		OPRND0(SPINAND_CMD_PAGE_READ_FROM_CACHE_QUADIO) |
+			PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(0) |
+			PAD1(LUT_PAD4) | INSTR1(LUT_MODE4),
+		OPRND0(ADDR12BIT) |PAD0(LUT_PAD4) | INSTR0(LUT_CADDR_SDR) |
+			OPRND1(4) | PAD1(LUT_PAD4) | INSTR1(LUT_DUMMY),
+		OPRND0(0) | PAD0(LUT_PAD4) | INSTR0(LUT_READ),
+		0,
+	},
+};
+
+const u32 prog_load_lut[ID_PROG_LOAD_END][4] = {
+	/* Program load */
+	{
+		OPRND0(SPINAND_CMD_PROG_LOAD) |
+			PAD0(LUT_PAD1) | INSTR0(LUT_CMD)  | OPRND1(0) |
+			PAD1(LUT_PAD1) | INSTR1(LUT_MODE4),
+		OPRND0(ADDR12BIT) | PAD0(LUT_PAD1) | INSTR0(LUT_CADDR_SDR) |
+			OPRND1(0) |PAD1(LUT_PAD1) | INSTR1(LUT_WRITE),
+		0, 0,
+	},
+	/* Program load random */
+	{
+		OPRND0(SPINAND_CMD_PROG_LOAD_RANDOM) |
+			PAD0(LUT_PAD1) | INSTR0(LUT_CMD)  | OPRND1(0) |
+			PAD1(LUT_PAD1) | INSTR1(LUT_MODE4),
+		OPRND0(ADDR12BIT) | PAD0(LUT_PAD1) | INSTR0(LUT_CADDR_SDR) |
+			OPRND1(0) | PAD1(LUT_PAD1) | INSTR1(LUT_WRITE),
+		0, 0,
+	},
+	/* Program load x4 */
+	{
+		OPRND0(SPINAND_CMD_PROG_LOAD_X4) |
+			PAD0(LUT_PAD1) | INSTR0(LUT_CMD)  | OPRND1(0) |
+			PAD1(LUT_PAD1) | INSTR1(LUT_MODE4),
+		OPRND0(ADDR12BIT) | PAD0(LUT_PAD1) | INSTR0(LUT_CADDR_SDR) |
+			OPRND1(0) | PAD1(LUT_PAD4) | INSTR1(LUT_WRITE),
+		0, 0,
+	},
+	/* Program load random x4 */
+	{
+		OPRND0(SPINAND_CMD_PROG_LOAD_RANDOM_X4) |
+			PAD0(LUT_PAD1) | INSTR0(LUT_CMD)  | OPRND1(0) |
+			PAD1(LUT_PAD1) | INSTR1(LUT_MODE4),
+		OPRND0(ADDR12BIT) | PAD0(LUT_PAD1) | INSTR0(LUT_CADDR_SDR) |
+			OPRND1(0) | PAD1(LUT_PAD4) | INSTR1(LUT_WRITE),
+		0, 0,
+	},
+};
+
+
+u8 fspi_read_cache_cmds[ID_READ_FROM_CACHE_END] = {
+	SPINAND_CMD_PAGE_READ_FROM_CACHE_NORMAL,
+	SPINAND_CMD_PAGE_READ_FROM_CACHE_FAST,
+	SPINAND_CMD_PAGE_READ_FROM_CACHE_X2,
+	SPINAND_CMD_PAGE_READ_FROM_CACHE_X4,
+	SPINAND_CMD_PAGE_READ_FROM_CACHE_DUALIO,
+	SPINAND_CMD_PAGE_READ_FROM_CACHE_QUADIO,
+};
+
+u8 fspi_prog_load_cmds[ID_PROG_LOAD_END] = {
+	SPINAND_CMD_PROG_LOAD,
+	SPINAND_CMD_PROG_LOAD_RANDOM,
+	SPINAND_CMD_PROG_LOAD_X4,
+	SPINAND_CMD_PROG_LOAD_RANDOM_X4,
+};
+
+static int fsl_fspi_nand_get_read_index(u8 cmd)
+{
+	int i;
+	for (i = 0; i < ID_READ_FROM_CACHE_END; i++) {
+		if (fspi_read_cache_cmds[i] == cmd)
+			break;
+	}
+
+	return i;
+}
+
+static int fsl_fspi_nand_get_progload_index(u8 cmd)
+{
+	int i;
+	for (i = 0; i < ID_PROG_LOAD_END; i++) {
+		if (fspi_prog_load_cmds[i] == cmd)
+			break;
+	}
+
+	return i;
+}
+
+static u32 fspi_read32(u32 flags, u32 *addr)
+{
+	return flags & FSPI_FLAG_REGMAP_ENDIAN_BIG ?
+		in_be32(addr) : in_le32(addr);
+}
+
+static void fspi_write32(u32 flags, u32 *addr, u32 val)
+{
+	flags & FSPI_FLAG_REGMAP_ENDIAN_BIG ?
+		out_be32(addr, val) : out_le32(addr, val);
+}
+
+static void fspi_nand_set_lut(struct fsl_fspi_priv *priv)
+{
+	struct fsl_fspi_regs *regs = priv->regs;
+	u32 lut_base;
+
+	/* Unlock the LUT */
+	fspi_write32(priv->flags, &regs->lutkey, FLEXSPI_LUTKEY_VALUE);
+	fspi_write32(priv->flags, &regs->lutcr, FLEXSPI_LCKER_UNLOCK);
+
+	/* RESET */
+	lut_base = SEQID_RESET * 4;
+	fspi_write32(priv->flags, &regs->lut[lut_base],
+		     OPRND0(SPINAND_CMD_RESET) | PAD0(LUT_PAD1) |
+		     INSTR0(LUT_CMD));
+	fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
+	fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
+	fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
+
+	/* Write Enable */
+	lut_base = SEQID_WREN * 4;
+	fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(SPINAND_CMD_WREN) |
+		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
+	fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
+	fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
+	fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
+
+	/* Read ID*/
+	lut_base = SEQID_READID * 4;
+	fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(SPINAND_CMD_READID) |
+		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(4) |
+		     PAD1(LUT_PAD1) | INSTR1(LUT_READ));
+	fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
+	fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
+	fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
+
+	/* Set Feature */
+	lut_base = SEQID_SET_FEATURE * 4;
+	fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(SPINAND_CMD_SET_FEATURE) |
+		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(0xB0) |
+		     PAD1(LUT_PAD1) | INSTR1(LUT_CMD));
+	fspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(1) |
+		     PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
+	fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
+	fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
+
+	/* Get Feature */
+	lut_base = SEQID_GET_FEATURE * 4;
+	fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(SPINAND_CMD_GET_FEATURE) |
+		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(0xC0) |
+		     PAD1(LUT_PAD1) | INSTR1(LUT_CMD));
+	fspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(1) |
+		     PAD0(LUT_PAD1) | INSTR0(LUT_READ));
+	fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
+	fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
+
+	/* Erase a block */
+	lut_base = SEQID_BLK_ERASE * 4;
+	fspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(SPINAND_CMD_BLK_ERASE) |
+		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
+		     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+	fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
+	fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
+	fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
+
+	/* Page read */
+	lut_base = SEQID_PAGE_READ * 4;
+	fspi_write32(priv->flags, &regs->lut[lut_base],
+		     OPRND0(SPINAND_CMD_PAGE_READ) |
+		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD)  | OPRND1(ADDR24BIT) |
+		     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+	fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
+	fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
+	fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
+
+	/* Program execute */
+	lut_base = SEQID_PROG_EXEC * 4;
+	fspi_write32(priv->flags, &regs->lut[lut_base],
+		     OPRND0(SPINAND_CMD_PROG_EXEC) |
+		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD)  | OPRND1(ADDR24BIT) |
+		     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+	fspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
+	fspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
+	fspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
+
+	/* Lock the LUT */
+	fspi_write32(priv->flags, &regs->lutkey, FLEXSPI_LUTKEY_VALUE);
+	fspi_write32(priv->flags, &regs->lutcr, FLEXSPI_LCKER_LOCK);
+}
+
+static int fspi_nand_op_cmd(struct fsl_fspi_priv *priv, u32 seqid, const struct spi_mem_op *op)
+{
+	struct fsl_fspi_regs *regs = priv->regs;
+	u32 addr = priv->cur_amba_base;
+
+	debug("%s seqid=%u, addr_nbytes = %u, addr_val = %llx\n",
+	      __func__, seqid, op->addr.nbytes, op->addr.val);
+
+	if (op->addr.nbytes != 0)
+		addr = (op->addr.val << FSPI_NAND_CAS) + addr;
+
+	/* invalid the TXFIFO first */
+	fspi_write32(priv->flags, &regs->iptxfcr, FLEXSPI_IPTXFCR_CLR_MASK);
+
+	fspi_write32(priv->flags, &regs->ipcr0, addr);
+
+	fspi_write32(priv->flags, &regs->ipcr1,
+		     (seqid << FLEXSPI_IPCR1_SEQID_SHIFT) | 0);
+
+	/* Trigger the command */
+	fspi_write32(priv->flags, &regs->ipcmd, 1);
+
+	/* Wait for command done */
+	while (!(fspi_read32(priv->flags, &regs->intr)
+		 & FLEXSPI_INTR_IPCMDDONE_MASK))
+		;
+
+	fspi_write32(priv->flags, &regs->intr, FLEXSPI_INTR_IPCMDDONE_MASK);
+
+	return 0;
+}
+
+static void fspi_nand_set_oprnd1(struct fsl_fspi_priv *priv,  u32 seqid, u8 oprnd)
+{
+	struct fsl_fspi_regs *regs = priv->regs;
+	u32 lut_base, val;
+
+	debug("set oprnd1 %u\n", oprnd);
+
+	/* Unlock the LUT */
+	fspi_write32(priv->flags, &regs->lutkey, FLEXSPI_LUTKEY_VALUE);
+	fspi_write32(priv->flags, &regs->lutcr, FLEXSPI_LCKER_UNLOCK);
+
+	lut_base = seqid * 4;
+	val = fspi_read32(priv->flags, &regs->lut[lut_base]);
+	val &= ~(OPRND1(0xff));
+	fspi_write32(priv->flags, &regs->lut[lut_base],
+		     val  | OPRND1(oprnd));
+
+	/* Lock the LUT */
+	fspi_write32(priv->flags, &regs->lutkey, FLEXSPI_LUTKEY_VALUE);
+	fspi_write32(priv->flags, &regs->lutcr, FLEXSPI_LCKER_LOCK);
+}
+
+static void fspi_nand_set_read_write_lut(struct fsl_fspi_priv *priv,  u32 seqid, u8 oprnd, u8 cmd)
+{
+	struct fsl_fspi_regs *regs = priv->regs;
+	u32 lut_base, val;
+	int i = 0;
+	const u32 *lut_buf;
+
+	if (seqid == SEQID_READ_FROM_CACHE_COMMON) {
+		i = fsl_fspi_nand_get_read_index(cmd);
+		lut_buf = &read_cache_lut[i][0];
+	} else {
+		i = fsl_fspi_nand_get_progload_index(cmd);
+		lut_buf = &prog_load_lut[i][0];
+	}
+
+	debug("seqid %u cmd %u oprnd1 %u, id %d\n", seqid, cmd, oprnd, i);
+
+	/* Unlock the LUT */
+	fspi_write32(priv->flags, &regs->lutkey, FLEXSPI_LUTKEY_VALUE);
+	fspi_write32(priv->flags, &regs->lutcr, FLEXSPI_LCKER_UNLOCK);
+
+	lut_base = seqid * 4;
+
+	/* update oprnd1 */
+	val = lut_buf[0];
+	val &= ~(OPRND1(0xff));
+	fspi_write32(priv->flags, &regs->lut[lut_base],
+		val  | OPRND1(oprnd));
+	fspi_write32(priv->flags, &regs->lut[lut_base + 1], lut_buf[1]);
+	fspi_write32(priv->flags, &regs->lut[lut_base + 2], lut_buf[2]);
+	fspi_write32(priv->flags, &regs->lut[lut_base + 3], lut_buf[3]);
+
+	/* Lock the LUT */
+	fspi_write32(priv->flags, &regs->lutkey, FLEXSPI_LUTKEY_VALUE);
+	fspi_write32(priv->flags, &regs->lutcr, FLEXSPI_LCKER_LOCK);
+}
+
+static int fspi_nand_op_read_reg(struct fsl_fspi_priv *priv, u32 seqid, const struct spi_mem_op *op)
+{
+	struct fsl_fspi_regs *regs = priv->regs;
+	u32 data, size, len = op->data.nbytes;
+	int i;
+	u8 *rxbuf = op->data.buf.in;
+
+	debug("%s seqid=%u, data_nbytes = %u, data_buf_in = %lx\n",
+	      __func__, seqid, op->data.nbytes, (ulong)rxbuf);
+
+	if (op->addr.nbytes == 1) {
+		fspi_nand_set_oprnd1(priv, seqid, (u8)op->addr.val);
+	} else if (op->addr.nbytes != 0) {
+		printf("Error: %s seqid=%u, reg addr size is %u\n",
+		       __func__, seqid, op->addr.nbytes);
+		return -EINVAL;
+	}
+
+	/* invalid the RXFIFO first */
+	fspi_write32(priv->flags, &regs->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK);
+
+	fspi_write32(priv->flags, &regs->ipcr0, priv->cur_amba_base);
+
+	fspi_write32(priv->flags, &regs->ipcr1,
+		     (seqid << FLEXSPI_IPCR1_SEQID_SHIFT) | len);
+	/* Trigger the command */
+	fspi_write32(priv->flags, &regs->ipcmd, 1);
+
+	/* Wait for command done */
+	while (!(fspi_read32(priv->flags, &regs->intr)
+		 & FLEXSPI_INTR_IPCMDDONE_MASK))
+		;
+
+	i = 0;
+	while ((32 >= len) && (len > 0)) {
+		data = fspi_read32(priv->flags, &regs->rfdr[i]);
+
+		debug("rfdr 0x%x\n", data);
+		size = (len < 4) ? len : 4;
+		memcpy(rxbuf, &data, size);
+		len -= size;
+		rxbuf += size;
+		i++;
+	}
+	fspi_write32(priv->flags, &regs->intr, FLEXSPI_INTR_IPRXWA_MASK);
+
+	fspi_write32(priv->flags, &regs->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK);
+	fspi_write32(priv->flags, &regs->intr, FLEXSPI_INTR_IPCMDDONE_MASK);
+
+	return 0;
+}
+
+static int fspi_nand_op_write_reg(struct fsl_fspi_priv *priv, u32 seqid, const struct spi_mem_op *op)
+{
+	struct fsl_fspi_regs *regs = priv->regs;
+	u32 data, size, len = op->data.nbytes;
+	int i;
+	u8 *txbuf = (u8 *)(op->data.buf.out);
+
+	debug("%s seqid=%u, data_nbytes = %u, data_buf_out = %lx\n",
+	      __func__, seqid, op->data.nbytes, (ulong)txbuf);
+
+	if (op->addr.nbytes != 1) {
+		printf("Error: fspi_nand_%s seqid=%u, reg addr size is %u\n",
+		       __func__, seqid, op->addr.nbytes);
+		return -EINVAL;
+	}
+
+	fspi_nand_set_oprnd1(priv, seqid, (u8)op->addr.val);
+
+	/* invalid the TXFIFO first */
+	fspi_write32(priv->flags, &regs->iprxfcr, FLEXSPI_IPTXFCR_CLR_MASK);
+
+	fspi_write32(priv->flags, &regs->ipcr0, priv->cur_amba_base);
+
+	i = 0;
+	while ((32 >= len) && (len > 0)) {
+		data = 0;
+		size = (len < 4) ? len : 4;
+		memcpy(&data, txbuf, size);
+		 fspi_write32(priv->flags, &regs->tfdr[i], data);
+		len -= size;
+		txbuf += size;
+		i++;
+	}
+	fspi_write32(priv->flags, &regs->intr, FLEXSPI_INTR_IPTXWE_MASK);
+
+	fspi_write32(priv->flags, &regs->ipcr1,
+		     (seqid << FLEXSPI_IPCR1_SEQID_SHIFT) | len);
+
+	/* Trigger the command */
+	fspi_write32(priv->flags, &regs->ipcmd, 1);
+
+	/* Wait for command done */
+	while (!(fspi_read32(priv->flags, &regs->intr)
+		& FLEXSPI_INTR_IPCMDDONE_MASK))
+		;
+
+	/* invalid the TXFIFO first */
+	fspi_write32(priv->flags, &regs->iptxfcr,
+		     FLEXSPI_IPTXFCR_CLR_MASK);
+	fspi_write32(priv->flags, &regs->intr,
+		     FLEXSPI_INTR_IPCMDDONE_MASK);
+
+	return 0;
+}
+
+static int fspi_nand_op_read(struct fsl_fspi_priv *priv, u32 seqid, const struct spi_mem_op *op)
+{
+	struct fsl_fspi_regs *regs = priv->regs;
+	int i, size;
+	u32 to_or_from;
+	u8 *rxbuf;
+	u8 panel;
+
+	to_or_from = op->addr.val + priv->cur_amba_base;
+	rxbuf = op->data.buf.in;
+	panel = op->addr.val >> FSPI_NAND_CAS;
+
+	/* Update LUT and select plane */
+	fspi_nand_set_read_write_lut(priv, seqid, panel, op->cmd.opcode);
+
+	debug("%s seqid=%u, addr_val = 0x%llx, addr_nbytes = %u, data_buf_in = 0x%lx, data_nbytes = 0x%x\n",
+	      __func__, seqid, op->addr.val, op->addr.nbytes,
+	      (ulong)rxbuf, op->data.nbytes);
+
+	/* invalid the RXFIFO */
+	fspi_write32(priv->flags, &regs->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK);
+
+	fspi_write32(priv->flags, &regs->ipcr0, to_or_from);
+
+	fspi_write32(priv->flags, &regs->ipcr1,
+		     (seqid << FLEXSPI_IPCR1_SEQID_SHIFT) |
+		     op->data.nbytes);
+
+	/* Trigger the command */
+	fspi_write32(priv->flags, &regs->ipcmd, 1);
+
+	size = op->data.nbytes / 8;
+	for (i = 0; i < size; ++i) {
+		/* Wait for RXFIFO available*/
+		while (!(fspi_read32(priv->flags, &regs->intr)
+			 & FLEXSPI_INTR_IPRXWA_MASK))
+			;
+
+		memcpy(rxbuf, &regs->rfdr, 8);
+		rxbuf += 8;
+
+		/* move the FIFO pointer */
+		fspi_write32(priv->flags, &regs->intr,
+			     FLEXSPI_INTR_IPRXWA_MASK);
+	}
+
+	size = op->data.nbytes % 8;
+
+	if (size) {
+		/* Wait for data filled*/
+		while (!(fspi_read32(priv->flags, &regs->iprxfsts)
+			& FLEXSPI_IPRXFSTS_FILL_MASK))
+			;
+		memcpy(rxbuf, &regs->rfdr, size);
+	}
+
+	/* invalid the RXFIFO */
+	fspi_write32(priv->flags, &regs->iprxfcr,
+		     FLEXSPI_IPRXFCR_CLR_MASK);
+	fspi_write32(priv->flags, &regs->intr,
+		     FLEXSPI_INTR_IPCMDDONE_MASK);
+
+	return 0;
+}
+
+static int fspi_nand_op_write(struct fsl_fspi_priv *priv, u32 seqid, const struct spi_mem_op *op)
+{
+	struct fsl_fspi_regs *regs = priv->regs;
+	int i, size;
+	u8 *txbuf;
+	u8 panel;
+	u32 to_or_from = op->addr.val + priv->cur_amba_base;
+
+	txbuf = (u8 *)(op->data.buf.out);
+	panel = op->addr.val >> FSPI_NAND_CAS;
+
+	/* Update LUT and select plane */
+	fspi_nand_set_read_write_lut(priv, seqid, panel, op->cmd.opcode);
+
+	debug("%s seqid=%u, addr_val = 0x%llx, addr_nbytes = %u, data_buf_in = 0x%lx, data_nbytes = 0x%x\n",
+	      __func__, seqid, op->addr.val, op->addr.nbytes,
+	      (ulong)txbuf, op->data.nbytes);
+
+	/* invalid the TXFIFO first */
+	fspi_write32(priv->flags, &regs->iptxfcr, FLEXSPI_IPTXFCR_CLR_MASK);
+
+	fspi_write32(priv->flags, &regs->ipcr0, to_or_from);
+
+	size = op->data.nbytes / 8;
+	for (i = 0; i < size; i++) {
+		/* Wait for TXFIFO empty*/
+		while (!(fspi_read32(priv->flags, &regs->intr)
+			 & FLEXSPI_INTR_IPTXWE_MASK))
+			;
+
+		memcpy(&regs->tfdr, txbuf, 8);
+		txbuf += 8;
+		fspi_write32(priv->flags, &regs->intr,
+			     FLEXSPI_INTR_IPTXWE_MASK);
+	}
+
+	size = op->data.nbytes % 8;
+	if (size) {
+		/* Wait for TXFIFO empty*/
+		while (!(fspi_read32(priv->flags, &regs->intr)
+			 & FLEXSPI_INTR_IPTXWE_MASK))
+			;
+
+		memcpy(&regs->tfdr, txbuf, size);
+		fspi_write32(priv->flags, &regs->intr,
+			     FLEXSPI_INTR_IPTXWE_MASK);
+	}
+
+	fspi_write32(priv->flags, &regs->ipcr1,
+		     (seqid << FLEXSPI_IPCR1_SEQID_SHIFT) | op->data.nbytes);
+
+	/* Trigger the command */
+	fspi_write32(priv->flags, &regs->ipcmd, 1);
+
+	/* Wait for command done */
+	while (!(fspi_read32(priv->flags, &regs->intr)
+		& FLEXSPI_INTR_IPCMDDONE_MASK))
+		;
+
+	/* invalid the TXFIFO first */
+	fspi_write32(priv->flags, &regs->iptxfcr,
+		     FLEXSPI_IPTXFCR_CLR_MASK);
+	fspi_write32(priv->flags, &regs->intr,
+		     FLEXSPI_INTR_IPCMDDONE_MASK);
+
+	return 0;
+}
+
+void fspi_nand_module_disable(struct fsl_fspi_priv *priv, u8 disable)
+{
+	u32 mcr_val;
+
+	mcr_val = fspi_read32(priv->flags, &priv->regs->mcr0);
+	if (disable)
+		mcr_val |= FLEXSPI_MCR0_MDIS_MASK;
+	else
+		mcr_val &= ~FLEXSPI_MCR0_MDIS_MASK;
+	fspi_write32(priv->flags, &priv->regs->mcr0, mcr_val);
+}
+
+__weak void init_clk_fspi(int index)
+{
+}
+
+static int fsl_fspi_nand_child_pre_probe(struct udevice *dev)
+{
+	struct spi_slave *slave = dev_get_parent_priv(dev);
+
+	slave->max_write_size = TX_BUFFER_SIZE;
+	slave->max_read_size = RX_BUFFER_SIZE;
+
+	return 0;
+}
+
+static int fsl_fspi_nand_probe(struct udevice *bus)
+{
+	u32 total_size;
+	struct fsl_fspi_platdata *plat = dev_get_platdata(bus);
+	struct fsl_fspi_priv *priv = dev_get_priv(bus);
+	struct dm_spi_bus *dm_spi_bus;
+	u32 val;
+
+	if (CONFIG_IS_ENABLED(CLK)) {
+		/* Assigned clock already set clock */
+		struct clk fspi_clk;
+		int ret;
+
+		ret = clk_get_by_name(bus, "fspi", &fspi_clk);
+		if (ret < 0) {
+			printf("Can't get fspi clk: %d\n", ret);
+			return ret;
+		}
+
+		ret = clk_enable(&fspi_clk);
+		if (ret < 0) {
+			printf("Can't enable fspi clk: %d\n", ret);
+			return ret;
+		}
+	} else {
+		init_clk_fspi(bus->seq);
+	}
+	dm_spi_bus = bus->uclass_priv;
+
+	dm_spi_bus->max_hz = plat->speed_hz;
+
+	priv->regs = (struct fsl_fspi_regs *)(uintptr_t)plat->reg_base;
+	priv->flags = plat->flags;
+
+	priv->speed_hz = plat->speed_hz;
+	priv->amba_base[0] = plat->amba_base;
+	priv->amba_total_size = plat->amba_total_size;
+	priv->flash_num = plat->flash_num;
+	priv->num_chipselect = plat->num_chipselect;
+
+	fspi_write32(priv->flags, &priv->regs->mcr0,
+		     FLEXSPI_MCR0_SWRST_MASK);
+	do {
+		udelay(1);
+	} while (0x1 & fspi_read32(priv->flags, &priv->regs->mcr0));
+
+	/* Disable the module */
+	fspi_nand_module_disable(priv, 1);
+
+	/* Enable the module and set to proper value*/
+	fspi_write32(priv->flags, &priv->regs->mcr0,
+		     0xFFFF0000);
+
+	/* Reset the DLL register to default value */
+	fspi_write32(priv->flags, &priv->regs->dllacr, 0x0100);
+	fspi_write32(priv->flags, &priv->regs->dllbcr, 0x0100);
+
+	/* Flash Size in KByte */
+	total_size = FSL_FSPI_NAND_SIZE * FSL_FSPI_NAND_NUM >> 10;
+
+	/*
+	 * Any read access to non-implemented addresses will provide
+	 * undefined results.
+	 *
+	 * In case single die flash devices, TOP_ADDR_MEMA2 and
+	 * TOP_ADDR_MEMB2 should be initialized/programmed to
+	 * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
+	 * setting the size of these devices to 0.  This would ensure
+	 * that the complete memory map is assigned to only one flash device.
+	 */
+
+	fspi_write32(priv->flags, &priv->regs->flsha1cr0,
+		     total_size);
+	fspi_write32(priv->flags, &priv->regs->flsha2cr0,
+		     0);
+	fspi_write32(priv->flags, &priv->regs->flshb1cr0,
+		     0);
+	fspi_write32(priv->flags, &priv->regs->flshb2cr0,
+		     0);
+
+	val = fspi_read32(priv->flags, &priv->regs->flsha1cr1);
+	val &= ~FLEXSPI_FLSHXCR1_CAS_MASK;
+	val |= FSPI_NAND_CAS << FLEXSPI_FLSHXCR1_CAS_SHIFT;
+	fspi_write32(priv->flags, &priv->regs->flsha1cr1,
+		     val);
+	fspi_nand_module_disable(priv, 0);
+
+	fspi_nand_set_lut(priv);
+
+	return 0;
+}
+
+static int fsl_fspi_nand_ofdata_to_platdata(struct udevice *bus)
+{
+	struct fdt_resource res_regs, res_mem;
+	struct fsl_fspi_platdata *plat = bus->platdata;
+	const void *blob = gd->fdt_blob;
+	int node = ofnode_to_offset(bus->node);
+	int ret, flash_num = 0, subnode;
+
+	if (fdtdec_get_bool(blob, node, "big-endian"))
+		plat->flags |= FSPI_FLAG_REGMAP_ENDIAN_BIG;
+
+	ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
+				     "FlexSPI", &res_regs);
+	if (ret) {
+		debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
+		return -ENOMEM;
+	}
+	ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
+				     "FlexSPI-memory", &res_mem);
+	if (ret) {
+		debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
+		return -ENOMEM;
+	}
+
+	/* Count flash numbers */
+	fdt_for_each_subnode(subnode, blob, node)
+		++flash_num;
+
+	if (flash_num == 0) {
+		debug("Error: Missing flashes!\n");
+		return -ENODEV;
+	}
+
+	plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
+					FSL_FSPI_DEFAULT_SCK_FREQ);
+	plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
+					      FSL_FSPI_MAX_CHIPSELECT_NUM);
+
+	plat->reg_base = res_regs.start;
+	plat->amba_base = 0;
+	plat->amba_total_size = res_mem.end - res_mem.start + 1;
+	plat->flash_num = flash_num;
+
+	debug("%s: regs=<0x%x> <0x%x, 0x%x>, max-frequency=%d, endianness=%s\n",
+	      __func__,
+	      plat->reg_base,
+	      plat->amba_base,
+	      plat->amba_total_size,
+	      plat->speed_hz,
+	      plat->flags & FSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
+	      );
+
+	return 0;
+}
+
+static int fsl_fspi_nand_claim_bus(struct udevice *dev)
+{
+	struct fsl_fspi_priv *priv;
+	struct udevice *bus;
+	struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+
+	bus = dev->parent;
+	priv = dev_get_priv(bus);
+
+	priv->cur_amba_base =
+		priv->amba_base[0] + FSL_FSPI_NAND_SIZE * slave_plat->cs;
+
+	return 0;
+}
+
+static int fsl_fspi_nand_release_bus(struct udevice *dev)
+{
+	return 0;
+}
+
+static int fsl_fspi_nand_set_speed(struct udevice *bus, uint speed)
+{
+	/* Nothing to do */
+	return 0;
+}
+
+static int fsl_fspi_nand_set_mode(struct udevice *bus, uint mode)
+{
+	/* Nothing to do */
+	return 0;
+}
+
+struct fspi_cmd_func_pair fspi_supported_cmds[SEQID_END] = {
+	{SPINAND_CMD_RESET, &fspi_nand_op_cmd},
+	{SPINAND_CMD_WREN, &fspi_nand_op_cmd},
+	{SPINAND_CMD_READID, &fspi_nand_op_read_reg},
+	{SPINAND_CMD_SET_FEATURE, &fspi_nand_op_write_reg},
+	{SPINAND_CMD_GET_FEATURE, &fspi_nand_op_read_reg},
+	{SPINAND_CMD_BLK_ERASE, &fspi_nand_op_cmd},
+	{SPINAND_CMD_PAGE_READ, &fspi_nand_op_cmd},
+	{SPINAND_CMD_PROG_EXEC, &fspi_nand_op_cmd},
+	{0x0, &fspi_nand_op_read},
+	{0x0, &fspi_nand_op_write},
+};
+
+static int fsl_fspi_nand_get_lut_index(const struct spi_mem_op *op)
+{
+	int i;
+
+	for (i = 0; i < SEQID_END; i++) {
+		if (fspi_supported_cmds[i].cmd == op->cmd.opcode)
+			break;
+
+		if (i == SEQID_READ_FROM_CACHE_COMMON) {
+			if (fsl_fspi_nand_get_read_index(op->cmd.opcode)
+				< ID_READ_FROM_CACHE_END)
+				break;
+		} else if (i == SEQID_PROG_LOAD_COMMON) {
+			if (fsl_fspi_nand_get_progload_index(op->cmd.opcode)
+				< ID_PROG_LOAD_END)
+				break;
+		}
+	}
+
+	return i;
+}
+
+bool fsl_fspi_nand_supports_op(struct spi_slave *slave, const struct spi_mem_op *op)
+{
+	int i;
+
+	if (!op || !slave)
+		return false;
+
+	i = fsl_fspi_nand_get_lut_index(op);
+	if (i == SEQID_END) {
+		printf("fsl_fspi_nand: fail to find cmd %u from lut\n", op->cmd.opcode);
+		return false;
+	}
+
+	debug("fsl_fspi_nand: find seqid %d for cmd %u from lut\n", i, op->cmd.opcode);
+
+	return true;
+}
+
+int fsl_fspi_nand_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
+{
+	int i;
+	struct fsl_fspi_priv *priv;
+	struct udevice *bus;
+
+	bus = slave->dev->parent;
+	priv = dev_get_priv(bus);
+
+	if (!op || !slave)
+		return -EINVAL;
+
+	i = fsl_fspi_nand_get_lut_index(op);
+	if (i == SEQID_END) {
+		printf("fsl_fspi_nand: fail to find cmd %u from lut\n", op->cmd.opcode);
+		return -EPERM;
+	}
+
+	return fspi_supported_cmds[i].fspi_op_func(priv, i, op);
+}
+
+int fsl_fspi_nand_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op)
+{
+	switch (op->cmd.opcode) {
+	case SPINAND_CMD_PAGE_READ_FROM_CACHE_NORMAL:
+	case SPINAND_CMD_PAGE_READ_FROM_CACHE_FAST:
+	case SPINAND_CMD_PAGE_READ_FROM_CACHE_X2:
+	case SPINAND_CMD_PAGE_READ_FROM_CACHE_X4:
+	case SPINAND_CMD_PAGE_READ_FROM_CACHE_DUALIO:
+	case SPINAND_CMD_PAGE_READ_FROM_CACHE_QUADIO:
+		if (op->data.nbytes > RX_BUFFER_SIZE)
+			op->data.nbytes = RX_BUFFER_SIZE;
+		break;
+	case SPINAND_CMD_PROG_LOAD:
+	case SPINAND_CMD_PROG_LOAD_RANDOM:
+	case SPINAND_CMD_PROG_LOAD_X4:
+	case SPINAND_CMD_PROG_LOAD_RANDOM_X4:
+		if (op->data.nbytes > TX_BUFFER_SIZE)
+			op->data.nbytes = TX_BUFFER_SIZE;
+		break;
+	}
+
+	return 0;
+}
+
+static struct spi_controller_mem_ops fspi_nand_mem_ops = {
+	.adjust_op_size = fsl_fspi_nand_adjust_op_size,
+	.supports_op = fsl_fspi_nand_supports_op,
+	.exec_op = fsl_fspi_nand_exec_op,
+};
+
+static const struct dm_spi_ops fsl_fspi_nand_ops = {
+	.claim_bus	= fsl_fspi_nand_claim_bus,
+	.release_bus	= fsl_fspi_nand_release_bus,
+	.set_speed	= fsl_fspi_nand_set_speed,
+	.set_mode	= fsl_fspi_nand_set_mode,
+	.mem_ops	= &fspi_nand_mem_ops,
+};
+
+static const struct udevice_id fsl_fspi_nand_ids[] = {
+	{ .compatible = "fsl,imx8-fspi-nand" },
+	{ }
+};
+
+U_BOOT_DRIVER(fsl_fspi_nand) = {
+	.name	= "fsl_fspi_nand",
+	.id	= UCLASS_SPI,
+	.of_match = fsl_fspi_nand_ids,
+	.ops	= &fsl_fspi_nand_ops,
+	.of_to_plat = fsl_fspi_nand_ofdata_to_platdata,
+	.plat_auto = sizeof(struct fsl_fspi_platdata),
+	.priv_auto = sizeof(struct fsl_fspi_priv),
+	.probe	= fsl_fspi_nand_probe,
+	.child_pre_probe = fsl_fspi_nand_child_pre_probe,
+};
diff --git a/drivers/spi/fsl_lpspi.c b/drivers/spi/fsl_lpspi.c
new file mode 100644
index 00000000000..a5d00e6d144
--- /dev/null
+++ b/drivers/spi/fsl_lpspi.c
@@ -0,0 +1,530 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * LPSPI controller driver.
+ *
+ * Copyright 2020 NXP
+ * Author: Clark Wang (xiaoning.wang@nxp.com)
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <malloc.h>
+#include <spi.h>
+#include <dm/device_compat.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/spi.h>
+#include <asm/arch/sys_proto.h>
+#include "fsl_lpspi.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int enable_lpspi_clk(unsigned char enable, unsigned int spi_num)
+{
+	return 0;
+}
+
+__weak u32 imx_get_spiclk(u32 spi_num)
+{
+	return 0;
+}
+
+#define reg_read readl
+#define reg_write(a, v) writel(v, a)
+
+#define MAX_CS_COUNT	4
+#define MAX_SPI_BYTES	16
+
+struct fsl_lpspi_slave {
+	struct spi_slave slave;
+	unsigned long	base;
+	unsigned int	seq;
+	unsigned int	prescale;
+	unsigned int	max_hz;
+	unsigned int	speed;
+	unsigned int	mode;
+	unsigned int	wordlen;
+	unsigned int	fifolen;
+	struct gpio_desc ss;
+	struct gpio_desc cs_gpios[MAX_CS_COUNT];
+	struct udevice *dev;
+	struct clk per_clk;
+	struct clk ipg_clk;
+
+	/* SPI FiFo accessor */
+	void *rx_buf;
+	const void *tx_buf;
+	void (*rx_fifo)(struct fsl_lpspi_slave *);
+	void (*tx_fifo)(struct fsl_lpspi_slave *);
+};
+
+static inline struct fsl_lpspi_slave *to_fsl_lpspi_slave(struct spi_slave *slave)
+{
+	return container_of(slave, struct fsl_lpspi_slave, slave);
+}
+
+#define BUILD_SPI_FIFO_RW(__name, __type)				\
+static void fsl_lpspi_rx_##__name(struct fsl_lpspi_slave *lpspi)	\
+{									\
+	struct LPSPI_Type *regs = (struct LPSPI_Type *)lpspi->base;	\
+	unsigned int val = reg_read(&regs->RDR);			\
+									\
+	if (lpspi->rx_buf) {						\
+		*(__type *)lpspi->rx_buf = val;				\
+		lpspi->rx_buf += sizeof(__type);			\
+	}								\
+}									\
+									\
+static void fsl_lpspi_tx_##__name(struct fsl_lpspi_slave *lpspi)	\
+{									\
+	__type val = 0;							\
+	struct LPSPI_Type *regs = (struct LPSPI_Type *)lpspi->base;	\
+									\
+	if (lpspi->tx_buf) {						\
+		val = *(__type *)lpspi->tx_buf;				\
+		lpspi->tx_buf += sizeof(__type);			\
+	}								\
+									\
+	reg_write(&regs->TDR, val);					\
+}
+BUILD_SPI_FIFO_RW(byte, u8);
+BUILD_SPI_FIFO_RW(word, u16);
+BUILD_SPI_FIFO_RW(dword, u32);
+
+static int fsl_lpspi_set_word_size(struct fsl_lpspi_slave *lpspi,
+				   unsigned int wordlen)
+{
+	lpspi->wordlen = wordlen;
+
+	switch (wordlen) {
+	case 8:
+		lpspi->rx_fifo = fsl_lpspi_rx_byte;
+		lpspi->tx_fifo = fsl_lpspi_tx_byte;
+		break;
+	case 16:
+		lpspi->rx_fifo = fsl_lpspi_rx_word;
+		lpspi->tx_fifo = fsl_lpspi_tx_word;
+		break;
+	case 32:
+		lpspi->rx_fifo = fsl_lpspi_rx_dword;
+		lpspi->tx_fifo = fsl_lpspi_tx_dword;
+		break;
+	default:
+		dev_err(lpspi->dev, "fsl_lpspi: unsupported wordlen: %d\n",
+				wordlen);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void fsl_lpspi_cs_activate(struct fsl_lpspi_slave *lpspi)
+{
+	struct udevice *dev = lpspi->dev;
+	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+
+	u32 cs = slave_plat->cs;
+
+	if (!dm_gpio_is_valid(&lpspi->cs_gpios[cs]))
+		return;
+
+	dm_gpio_set_value(&lpspi->cs_gpios[cs], 1);
+}
+
+static void fsl_lpspi_cs_deactivate(struct fsl_lpspi_slave *lpspi)
+{
+	struct udevice *dev = lpspi->dev;
+	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+
+	u32 cs = slave_plat->cs;
+
+	if (!dm_gpio_is_valid(&lpspi->cs_gpios[cs]))
+		return;
+
+	dm_gpio_set_value(&lpspi->cs_gpios[cs], 0);
+}
+
+static int clkdivs[] = {1, 2, 4, 8, 16, 32, 64, 128};
+
+static s32 spi_cfg_lpspi(struct fsl_lpspi_slave *lpspi, unsigned int cs)
+{
+	s32 reg_config;
+	unsigned int perclk_rate, scldiv;
+	u8 prescale;
+	struct LPSPI_Type *regs = (struct LPSPI_Type *)lpspi->base;
+	unsigned int speed = lpspi->speed;
+
+	/* Disable all interrupt */
+	reg_write(&regs->IER, 0);
+	/* W1C for all flags in SR */
+	reg_write(&regs->SR, (0x3F << 8));
+	/* Clear FIFO and disable module */
+	reg_write(&regs->CR, (LPSPI_CR_RTF_MASK | LPSPI_CR_RRF_MASK));
+
+	lpspi->fifolen = 1 << (reg_read(&regs->PARAM) & LPSPI_PARAM_TXFIFO_MASK);
+
+	reg_config = reg_read(&regs->CFGR1);
+	reg_config = (reg_config & (~LPSPI_CFGR1_MASTER_MASK)) |
+		     LPSPI_CFGR1_MASTER(1);
+	if (lpspi->mode & SPI_CS_HIGH)
+		reg_config = reg_config |
+			     (1UL << (LPSPI_CFGR1_PCSPOL_SHIFT + (uint32_t)cs));
+	else
+		reg_config = reg_config &
+			    ~(1UL << (LPSPI_CFGR1_PCSPOL_SHIFT + (uint32_t)cs));
+	reg_config = (reg_config & ~(LPSPI_CFGR1_OUTCFG_MASK |
+			LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOSTALL_MASK)) |
+			LPSPI_CFGR1_OUTCFG(0) | LPSPI_CFGR1_PINCFG(0) |
+			LPSPI_CFGR1_NOSTALL(0);
+	reg_write(&regs->CFGR1, reg_config);
+
+	if (IS_ENABLED(CONFIG_CLK)) {
+		perclk_rate = clk_get_rate(&lpspi->per_clk);
+		if (perclk_rate <= 0) {
+			dev_err(lpspi->dev, "Failed to get spi clk: %d\n",
+				perclk_rate);
+			return perclk_rate;
+		}
+	} else {
+		perclk_rate = imx_get_spiclk(lpspi->seq);
+		if (!perclk_rate)
+			return -EPERM;
+	}
+
+	if (speed > perclk_rate / 2) {
+		dev_err(lpspi->dev,
+		      "per-clk should be at least two times of transfer speed, speed=%d", speed);
+		return -EINVAL;
+	}
+
+	for (prescale = 0; prescale < 8; prescale++) {
+		scldiv = perclk_rate /
+			 (clkdivs[prescale] * speed) - 2;
+		if (scldiv < 256) {
+			lpspi->prescale = prescale;
+			break;
+		}
+	}
+
+	if (prescale == 8 && scldiv >= 256)
+		return -EINVAL;
+
+	reg_write(&regs->CCR, (scldiv | (scldiv << 8) | ((scldiv >> 1) << 16)));
+
+	dev_dbg(lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n",
+		perclk_rate, speed, prescale, scldiv);
+
+	return 0;
+}
+
+int spi_xfer_single(struct fsl_lpspi_slave *lpspi, unsigned int bitlen,
+	unsigned long flags)
+{
+	int nbytes = DIV_ROUND_UP(bitlen, 8);
+	u32 ts;
+	struct LPSPI_Type *regs = (struct LPSPI_Type *)lpspi->base;
+	int status;
+
+	dev_dbg(lpspi->dev, "%s: bitlen %d tx_buf 0x%lx rx_buf 0x%lx\n",
+		__func__, bitlen, (ulong)lpspi->tx_buf, (ulong)lpspi->rx_buf);
+
+	while (nbytes > 0) {
+		lpspi->tx_fifo(lpspi);
+		nbytes -= (lpspi->wordlen / 8);
+	}
+
+	reg_write(&regs->TCR, ((lpspi->mode & 0x3) << LPSPI_TCR_CPHA_SHIFT |
+		  LPSPI_TCR_FRAMESZ(lpspi->wordlen - 1) |
+		  LPSPI_TCR_PRESCALE(lpspi->prescale) |
+		  LPSPI_TCR_PCS(1) | LPSPI_TCR_CONT(1) | LPSPI_TCR_CONTC(0)));
+
+	ts = get_timer(0);
+	status = reg_read(&regs->SR);
+	/* Wait until the TC (Transfer completed) bit is set */
+	while ((status & LPSPI_SR_TCF_MASK) != 0) {
+		if (get_timer(ts) > (CONFIG_SYS_HZ / 2)) {
+			dev_err(lpspi->dev, "lpspi_xfer_single: TX Timeout!\n");
+			return -ETIMEDOUT;
+		}
+		status = reg_read(&regs->RSR);
+	}
+	nbytes = DIV_ROUND_UP(bitlen, 8);
+	ts = get_timer(0);
+	while (nbytes > 0) {
+		if (get_timer(ts) > (CONFIG_SYS_HZ / 2)) {
+			dev_err(lpspi->dev, "lpspi_xfer_single: RX Timeout!\n");
+			return -ETIMEDOUT;
+		}
+		if ((reg_read(&regs->FSR) & LPSPI_FSR_RXCOUNT_MASK) > 0) {
+			lpspi->rx_fifo(lpspi);
+			nbytes -= (lpspi->wordlen / 8);
+		}
+	}
+
+	return nbytes;
+}
+
+static int fsl_lpspi_check_trans_len(unsigned int len, unsigned int wordlen)
+{
+	int ret = 0;
+
+	switch (wordlen) {
+	case 32:
+		if (len % 4)
+			ret = -EINVAL;
+		break;
+	case 16:
+		if (len % 2)
+			ret = -EINVAL;
+		break;
+	case 8:
+		break;
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int fsl_lpspi_xfer_internal(struct fsl_lpspi_slave *lpspi,
+				 unsigned int bitlen, const void *dout,
+				 void *din, unsigned long flags)
+{
+	int n_bytes = DIV_ROUND_UP(bitlen, 8);
+	int n_bits;
+	int ret = 0;
+	u32 blk_size;
+	struct LPSPI_Type *regs;
+	u8 watermark = 0;
+	struct udevice *dev;
+	struct dm_spi_slave_plat *slave_plat;
+
+	if (!lpspi)
+		return -EINVAL;
+
+	regs = (struct LPSPI_Type *)lpspi->base;
+	dev = lpspi->dev;
+	slave_plat = dev_get_parent_plat(dev);
+
+	ret = fsl_lpspi_check_trans_len(n_bytes, lpspi->wordlen);
+	if (ret)
+	{
+		dev_err(lpspi->dev, "fsl_lpspi: wordlen(%d) and transfer len(%d) mismatch!\n",
+			DIV_ROUND_UP(lpspi->wordlen, 8), n_bytes);
+		return ret;
+	}
+
+	if (dout)
+		lpspi->tx_buf = dout;
+	if (din)
+		lpspi->rx_buf = din;
+
+	if (n_bytes <= lpspi->fifolen)
+		watermark = n_bytes;
+	else
+		watermark = lpspi->fifolen;
+	reg_write(&regs->FCR, watermark >> 1 | (watermark >> 1) << 16);
+
+	reg_write(&regs->TCR, ((lpspi->mode & 0x3) << LPSPI_TCR_CPHA_SHIFT |
+		  LPSPI_TCR_FRAMESZ(lpspi->wordlen - 1) |
+		  LPSPI_TCR_PRESCALE(lpspi->prescale) |
+		  LPSPI_TCR_PCS(slave_plat->cs) | LPSPI_TCR_CONT(1) |
+		  LPSPI_TCR_CONTC(0)));
+
+	reg_write(&regs->CR, LPSPI_CR_MEN_MASK);
+
+	if (flags & SPI_XFER_BEGIN)
+		fsl_lpspi_cs_activate(lpspi);
+
+	while (n_bytes > 0) {
+		if (n_bytes < lpspi->fifolen * lpspi->wordlen / 8)
+			blk_size = n_bytes;
+		else
+			blk_size = lpspi->fifolen * lpspi->wordlen / 8;
+
+		n_bits = blk_size * 8;
+
+		ret = spi_xfer_single(lpspi, n_bits, 0);
+		if (ret)
+			break;
+
+		n_bytes -= blk_size;
+	}
+
+	/* Disable all interrupt */
+	reg_write(&regs->IER, 0);
+	/* W1C for all flags in SR */
+	reg_write(&regs->SR, (0x3F << 8));
+	/* Clear FIFO and disable module */
+	reg_write(&regs->CR, (LPSPI_CR_RTF_MASK | LPSPI_CR_RRF_MASK));
+
+	if (flags & SPI_XFER_END || ret)
+		fsl_lpspi_cs_deactivate(lpspi);
+
+	lpspi->tx_buf = NULL;
+	lpspi->rx_buf = NULL;
+
+	return ret;
+}
+
+static int fsl_lpspi_claim_bus_internal(struct fsl_lpspi_slave *lpspi, int cs)
+{
+	int ret;
+
+	ret = spi_cfg_lpspi(lpspi, cs);
+	if (ret) {
+		dev_err(lpspi->dev, "fsl_lpspi: cannot setup SPI controller\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int fsl_lpspi_probe(struct udevice *bus)
+{
+	struct fsl_lpspi_slave *lpspi = dev_get_plat(bus);
+	int node = dev_of_offset(bus);
+	const void *blob = gd->fdt_blob;
+	int ret;
+	int i;
+
+	ret = gpio_request_list_by_name(bus, "cs-gpios", lpspi->cs_gpios,
+					ARRAY_SIZE(lpspi->cs_gpios), 0);
+	if (ret < 0) {
+		dev_err(bus, "Can't get %s gpios! Error: %d", bus->name, ret);
+		return ret;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(lpspi->cs_gpios); i++) {
+		if (!dm_gpio_is_valid(&lpspi->cs_gpios[i]))
+			continue;
+
+		ret = dm_gpio_set_dir_flags(&lpspi->cs_gpios[i],
+					    GPIOD_IS_OUT | GPIOD_ACTIVE_LOW);
+		if (ret) {
+			dev_err(bus, "Setting cs %d error\n", i);
+			return ret;
+		}
+	}
+
+	lpspi->base = devfdt_get_addr(bus);
+	if (lpspi->base == FDT_ADDR_T_NONE)
+		return -ENODEV;
+
+	lpspi->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
+				      500000);
+
+	if (IS_ENABLED(CONFIG_CLK)) {
+		//Enable clks
+		ret = clk_get_by_name(bus, "per", &lpspi->per_clk);
+		if (ret) {
+			dev_err(bus, "Failed to get per clk\n");
+			return ret;
+		}
+		ret = clk_enable(&lpspi->per_clk);
+		if (ret) {
+			dev_err(bus, "Failed to enable per clk, ret=%d\n", ret);
+			return ret;
+		}
+
+		ret = clk_get_by_name(bus, "ipg", &lpspi->ipg_clk);
+		if (ret) {
+			dev_err(bus, "Failed to get ipg clk\n");
+			return ret;
+		}
+		ret = clk_enable(&lpspi->ipg_clk);
+		if (ret) {
+			dev_err(bus, "Failed to enable ipg clk\n");
+			return ret;
+		}
+	} else {
+		lpspi->seq = dev_seq(bus);
+		/* To i.MX7ULP, only spi2/3 can be handled by A7 core */
+		ret = enable_lpspi_clk(1, lpspi->seq);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int fsl_lpspi_xfer(struct udevice *dev, unsigned int bitlen,
+		const void *dout, void *din, unsigned long flags)
+{
+	struct fsl_lpspi_slave *lpspi = dev_get_plat(dev->parent);
+
+	return fsl_lpspi_xfer_internal(lpspi, bitlen, dout, din, flags);
+}
+
+static int fsl_lpspi_claim_bus(struct udevice *dev)
+{
+	struct fsl_lpspi_slave *lpspi = dev_get_plat(dev->parent);
+	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+
+	lpspi->dev = dev;
+
+	/* set default configurations */
+	lpspi->mode = 0;
+	lpspi->speed = lpspi->max_hz;
+	lpspi->wordlen = 8;
+	fsl_lpspi_set_word_size(lpspi, lpspi->wordlen);
+
+	return fsl_lpspi_claim_bus_internal(lpspi, slave_plat->cs);
+}
+
+static int fsl_lpspi_release_bus(struct udevice *dev)
+{
+	return 0;
+}
+
+static int fsl_lpspi_set_speed(struct udevice *bus, uint speed)
+{
+	struct fsl_lpspi_slave *lpspi = dev_get_plat(bus);
+
+	lpspi->speed = speed;
+
+	return 0;
+}
+
+static int fsl_lpspi_set_mode(struct udevice *bus, uint mode)
+{
+	struct fsl_lpspi_slave *lpspi = dev_get_plat(bus);
+
+	lpspi->mode = mode;
+
+	return 0;
+}
+
+static int fsl_lpspi_set_wordlen(struct udevice *bus, unsigned int wordlen)
+{
+	struct fsl_lpspi_slave *lpspi = dev_get_plat(bus);
+
+	return fsl_lpspi_set_word_size(lpspi, wordlen);
+}
+
+static const struct dm_spi_ops fsl_lpspi_ops = {
+	.claim_bus	= fsl_lpspi_claim_bus,
+	.release_bus	= fsl_lpspi_release_bus,
+	.xfer		= fsl_lpspi_xfer,
+	.set_speed	= fsl_lpspi_set_speed,
+	.set_mode	= fsl_lpspi_set_mode,
+	.set_wordlen	= fsl_lpspi_set_wordlen,
+};
+
+static const struct udevice_id fsl_lpspi_ids[] = {
+	{ .compatible = "fsl,imx7ulp-spi" },
+	{ }
+};
+
+U_BOOT_DRIVER(fsl_lpspi) = {
+	.name	= "fsl_lpspi",
+	.id	= UCLASS_SPI,
+	.of_match = fsl_lpspi_ids,
+	.ops	= &fsl_lpspi_ops,
+	.plat_auto = sizeof(struct fsl_lpspi_slave),
+	.probe	= fsl_lpspi_probe,
+};
diff --git a/drivers/spi/fsl_lpspi.h b/drivers/spi/fsl_lpspi.h
new file mode 100644
index 00000000000..c9f5811a91b
--- /dev/null
+++ b/drivers/spi/fsl_lpspi.h
@@ -0,0 +1,531 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Register definitions for Freescale QSPI
+ *
+ * Copyright 2020 NXP
+ * Author: Clark Wang (xiaoning.wang@nxp.com)
+ */
+#ifndef _FSL_LPSPI_H_
+#define _FSL_LPSPI_H_
+
+/* ----------------------------------------------------------------------------
+ - LPSPI Peripheral Access Layer
+ * ---------------------------------------------------------------------------- */
+
+/*
+ * LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
+ */
+
+/** LPSPI - Register Layout Typedef */
+struct LPSPI_Type
+{
+	u32 VERID; /**< Version ID Register, offset: 0x0 */
+	u32 PARAM; /**< Parameter Register, offset: 0x4 */
+	u8 RESERVED_0[8];
+	u32 CR;    /**< Control Register, offset: 0x10 */
+	u32 SR;    /**< Status Register, offset: 0x14 */
+	u32 IER;   /**< Interrupt Enable Register, offset: 0x18 */
+	u32 DER;   /**< DMA Enable Register, offset: 0x1C */
+	u32 CFGR0; /**< Configuration Register 0, offset: 0x20 */
+	u32 CFGR1; /**< Configuration Register 1, offset: 0x24 */
+	u8 RESERVED_1[8];
+	u32 DMR0; /**< Data Match Register 0, offset: 0x30 */
+	u32 DMR1; /**< Data Match Register 1, offset: 0x34 */
+	u8 RESERVED_2[8];
+	u32 CCR; /**< Clock Configuration Register, offset: 0x40 */
+	u8 RESERVED_3[20];
+	u32 FCR; /**< FIFO Control Register, offset: 0x58 */
+	u32 FSR;  /**< FIFO Status Register, offset: 0x5C */
+	u32 TCR; /**< Transmit Command Register, offset: 0x60 */
+	u32 TDR;  /**< Transmit Data Register, offset: 0x64 */
+	u8 RESERVED_4[8];
+	u32 RSR; /**< Receive Status Register, offset: 0x70 */
+	u32 RDR; /**< Receive Data Register, offset: 0x74 */
+};
+
+/* ----------------------------------------------------------------------------
+ - LPSPI Register Masks
+ * ---------------------------------------------------------------------------- */
+
+/*
+ * LPSPI_Register_Masks LPSPI Register Masks
+ */
+
+/* VERID - Version ID Register */
+#define LPSPI_VERID_FEATURE_MASK  (0xFFFFU)
+#define LPSPI_VERID_FEATURE_SHIFT (0U)
+/*! FEATURE - Module Identification Number
+ *  0b0000000000000100..Standard feature set supporting a 32-bit shift register.
+ */
+#define LPSPI_VERID_FEATURE(x)  (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
+#define LPSPI_VERID_MINOR_MASK  (0xFF0000U)
+#define LPSPI_VERID_MINOR_SHIFT (16U)
+#define LPSPI_VERID_MINOR(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
+#define LPSPI_VERID_MAJOR_MASK  (0xFF000000U)
+#define LPSPI_VERID_MAJOR_SHIFT (24U)
+#define LPSPI_VERID_MAJOR(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
+
+/* PARAM - Parameter Register */
+#define LPSPI_PARAM_TXFIFO_MASK  (0xFFU)
+#define LPSPI_PARAM_TXFIFO_SHIFT (0U)
+#define LPSPI_PARAM_TXFIFO(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
+#define LPSPI_PARAM_RXFIFO_MASK  (0xFF00U)
+#define LPSPI_PARAM_RXFIFO_SHIFT (8U)
+#define LPSPI_PARAM_RXFIFO(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
+#define LPSPI_PARAM_PCSNUM_MASK  (0xFF0000U)
+#define LPSPI_PARAM_PCSNUM_SHIFT (16U)
+#define LPSPI_PARAM_PCSNUM(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
+
+/* CR - Control Register */
+#define LPSPI_CR_MEN_MASK  (0x1U)
+#define LPSPI_CR_MEN_SHIFT (0U)
+/*! MEN - Module Enable
+ *  0b0..Module is disabled
+ *  0b1..Module is enabled
+ */
+#define LPSPI_CR_MEN(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
+#define LPSPI_CR_RST_MASK  (0x2U)
+#define LPSPI_CR_RST_SHIFT (1U)
+/*! RST - Software Reset
+ *  0b0..Module is not reset
+ *  0b1..Module is reset
+ */
+#define LPSPI_CR_RST(x)      (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
+#define LPSPI_CR_DOZEN_MASK  (0x4U)
+#define LPSPI_CR_DOZEN_SHIFT (2U)
+/*! DOZEN - Doze Mode Enable
+ *  0b0..LPSPI module is enabled in Doze mode
+ *  0b1..LPSPI module is disabled in Doze mode
+ */
+#define LPSPI_CR_DOZEN(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
+#define LPSPI_CR_DBGEN_MASK  (0x8U)
+#define LPSPI_CR_DBGEN_SHIFT (3U)
+/*! DBGEN - Debug Enable
+ *  0b0..LPSPI module is disabled in debug mode
+ *  0b1..LPSPI module is enabled in debug mode
+ */
+#define LPSPI_CR_DBGEN(x)  (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
+#define LPSPI_CR_RTF_MASK  (0x100U)
+#define LPSPI_CR_RTF_SHIFT (8U)
+/*! RTF - Reset Transmit FIFO
+ *  0b0..No effect
+ *  0b1..Transmit FIFO is reset
+ */
+#define LPSPI_CR_RTF(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
+#define LPSPI_CR_RRF_MASK  (0x200U)
+#define LPSPI_CR_RRF_SHIFT (9U)
+/*! RRF - Reset Receive FIFO
+ *  0b0..No effect
+ *  0b1..Receive FIFO is reset
+ */
+#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
+
+/* SR - Status Register */
+#define LPSPI_SR_TDF_MASK  (0x1U)
+#define LPSPI_SR_TDF_SHIFT (0U)
+/*! TDF - Transmit Data Flag
+ *  0b0..Transmit data not requested
+ *  0b1..Transmit data is requested
+ */
+#define LPSPI_SR_TDF(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
+#define LPSPI_SR_RDF_MASK  (0x2U)
+#define LPSPI_SR_RDF_SHIFT (1U)
+/*! RDF - Receive Data Flag
+ *  0b0..Receive Data is not ready
+ *  0b1..Receive data is ready
+ */
+#define LPSPI_SR_RDF(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
+#define LPSPI_SR_WCF_MASK  (0x100U)
+#define LPSPI_SR_WCF_SHIFT (8U)
+/*! WCF - Word Complete Flag
+ *  0b0..Transfer of a received word has not yet completed
+ *  0b1..Transfer of a received word has completed
+ */
+#define LPSPI_SR_WCF(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
+#define LPSPI_SR_FCF_MASK  (0x200U)
+#define LPSPI_SR_FCF_SHIFT (9U)
+/*! FCF - Frame Complete Flag
+ *  0b0..Frame transfer has not completed
+ *  0b1..Frame transfer has completed
+ */
+#define LPSPI_SR_FCF(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
+#define LPSPI_SR_TCF_MASK  (0x400U)
+#define LPSPI_SR_TCF_SHIFT (10U)
+/*! TCF - Transfer Complete Flag
+ *  0b0..All transfers have not completed
+ *  0b1..All transfers have completed
+ */
+#define LPSPI_SR_TCF(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
+#define LPSPI_SR_TEF_MASK  (0x800U)
+#define LPSPI_SR_TEF_SHIFT (11U)
+/*! TEF - Transmit Error Flag
+ *  0b0..Transmit FIFO underrun has not occurred
+ *  0b1..Transmit FIFO underrun has occurred
+ */
+#define LPSPI_SR_TEF(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
+#define LPSPI_SR_REF_MASK  (0x1000U)
+#define LPSPI_SR_REF_SHIFT (12U)
+/*! REF - Receive Error Flag
+ *  0b0..Receive FIFO has not overflowed
+ *  0b1..Receive FIFO has overflowed
+ */
+#define LPSPI_SR_REF(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
+#define LPSPI_SR_DMF_MASK  (0x2000U)
+#define LPSPI_SR_DMF_SHIFT (13U)
+/*! DMF - Data Match Flag
+ *  0b0..Have not received matching data
+ *  0b1..Have received matching data
+ */
+#define LPSPI_SR_DMF(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
+#define LPSPI_SR_MBF_MASK  (0x1000000U)
+#define LPSPI_SR_MBF_SHIFT (24U)
+/*! MBF - Module Busy Flag
+ *  0b0..LPSPI is idle
+ *  0b1..LPSPI is busy
+ */
+#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
+
+/* IER - Interrupt Enable Register */
+#define LPSPI_IER_TDIE_MASK  (0x1U)
+#define LPSPI_IER_TDIE_SHIFT (0U)
+/*! TDIE - Transmit Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_TDIE(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
+#define LPSPI_IER_RDIE_MASK  (0x2U)
+#define LPSPI_IER_RDIE_SHIFT (1U)
+/*! RDIE - Receive Data Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_RDIE(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
+#define LPSPI_IER_WCIE_MASK  (0x100U)
+#define LPSPI_IER_WCIE_SHIFT (8U)
+/*! WCIE - Word Complete Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_WCIE(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
+#define LPSPI_IER_FCIE_MASK  (0x200U)
+#define LPSPI_IER_FCIE_SHIFT (9U)
+/*! FCIE - Frame Complete Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_FCIE(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
+#define LPSPI_IER_TCIE_MASK  (0x400U)
+#define LPSPI_IER_TCIE_SHIFT (10U)
+/*! TCIE - Transfer Complete Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_TCIE(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
+#define LPSPI_IER_TEIE_MASK  (0x800U)
+#define LPSPI_IER_TEIE_SHIFT (11U)
+/*! TEIE - Transmit Error Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_TEIE(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
+#define LPSPI_IER_REIE_MASK  (0x1000U)
+#define LPSPI_IER_REIE_SHIFT (12U)
+/*! REIE - Receive Error Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_REIE(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
+#define LPSPI_IER_DMIE_MASK  (0x2000U)
+#define LPSPI_IER_DMIE_SHIFT (13U)
+/*! DMIE - Data Match Interrupt Enable
+ *  0b0..Disabled
+ *  0b1..Enabled
+ */
+#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
+
+/* DER - DMA Enable Register */
+#define LPSPI_DER_TDDE_MASK  (0x1U)
+#define LPSPI_DER_TDDE_SHIFT (0U)
+/*! TDDE - Transmit Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
+#define LPSPI_DER_TDDE(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
+#define LPSPI_DER_RDDE_MASK  (0x2U)
+#define LPSPI_DER_RDDE_SHIFT (1U)
+/*! RDDE - Receive Data DMA Enable
+ *  0b0..DMA request is disabled
+ *  0b1..DMA request is enabled
+ */
+#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
+
+/* CFGR0 - Configuration Register 0 */
+#define LPSPI_CFGR0_HREN_MASK  (0x1U)
+#define LPSPI_CFGR0_HREN_SHIFT (0U)
+/*! HREN - Host Request Enable
+ *  0b0..Host request is disabled
+ *  0b1..Host request is enabled
+ */
+#define LPSPI_CFGR0_HREN(x)     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK)
+#define LPSPI_CFGR0_HRPOL_MASK  (0x2U)
+#define LPSPI_CFGR0_HRPOL_SHIFT (1U)
+/*! HRPOL - Host Request Polarity
+ *  0b0..LPSPI_HREQ pin is active low
+ *  0b1..LPSPI_HREQ pin is active high
+ */
+#define LPSPI_CFGR0_HRPOL(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
+#define LPSPI_CFGR0_HRSEL_MASK  (0x4U)
+#define LPSPI_CFGR0_HRSEL_SHIFT (2U)
+/*! HRSEL - Host Request Select
+ *  0b0..Host request input is the LPSPI_HREQ pin
+ *  0b1..Host request input is the input trigger
+ */
+#define LPSPI_CFGR0_HRSEL(x)      (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK)
+#define LPSPI_CFGR0_CIRFIFO_MASK  (0x100U)
+#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U)
+/*! CIRFIFO - Circular FIFO Enable
+ *  0b0..Circular FIFO is disabled
+ *  0b1..Circular FIFO is enabled
+ */
+#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
+#define LPSPI_CFGR0_RDMO_MASK  (0x200U)
+#define LPSPI_CFGR0_RDMO_SHIFT (9U)
+/*! RDMO - Receive Data Match Only
+ *  0b0..Received data is stored in the receive FIFO as in normal operations
+ *  0b1..Received data is discarded unless the Data Match Flag (DMF) is set
+ */
+#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
+
+/* CFGR1 - Configuration Register 1 */
+#define LPSPI_CFGR1_MASTER_MASK  (0x1U)
+#define LPSPI_CFGR1_MASTER_SHIFT (0U)
+/*! MASTER - Master Mode
+ *  0b0..Slave mode
+ *  0b1..Master mode
+ */
+#define LPSPI_CFGR1_MASTER(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
+#define LPSPI_CFGR1_SAMPLE_MASK  (0x2U)
+#define LPSPI_CFGR1_SAMPLE_SHIFT (1U)
+/*! SAMPLE - Sample Point
+ *  0b0..Input data is sampled on SCK edge
+ *  0b1..Input data is sampled on delayed SCK edge
+ */
+#define LPSPI_CFGR1_SAMPLE(x)     (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
+#define LPSPI_CFGR1_AUTOPCS_MASK  (0x4U)
+#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U)
+/*! AUTOPCS - Automatic PCS
+ *  0b0..Automatic PCS generation is disabled
+ *  0b1..Automatic PCS generation is enabled
+ */
+#define LPSPI_CFGR1_AUTOPCS(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
+#define LPSPI_CFGR1_NOSTALL_MASK  (0x8U)
+#define LPSPI_CFGR1_NOSTALL_SHIFT (3U)
+/*! NOSTALL - No Stall
+ *  0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full
+ *  0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur
+ */
+#define LPSPI_CFGR1_NOSTALL(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
+#define LPSPI_CFGR1_PCSPOL_MASK  (0xF00U)
+#define LPSPI_CFGR1_PCSPOL_SHIFT (8U)
+#define LPSPI_CFGR1_PCSPOL(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
+#define LPSPI_CFGR1_MATCFG_MASK  (0x70000U)
+#define LPSPI_CFGR1_MATCFG_SHIFT (16U)
+/*! MATCFG - Match Configuration
+ *  0b000..Match is disabled
+ *  0b001..Reserved
+ *  0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1)
+ *  0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1)
+ *  0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st
+ *         data word = MATCH0) * (2nd data word = MATCH1)]
+ *  0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e.,
+ *         [(any data word = MATCH0) * (next data word = MATCH1)]
+ *  0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word *
+ * MATCH1) = (MATCH0 * MATCH1)] 0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND
+ * MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)]
+ */
+#define LPSPI_CFGR1_MATCFG(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
+#define LPSPI_CFGR1_PINCFG_MASK  (0x3000000U)
+#define LPSPI_CFGR1_PINCFG_SHIFT (24U)
+/*! PINCFG - Pin Configuration
+ *  0b00..SIN is used for input data and SOUT is used for output data
+ *  0b01..SIN is used for both input and output data, only half-duplex serial transfers are supported
+ *  0b10..SOUT is used for both input and output data, only half-duplex serial transfers are supported
+ *  0b11..SOUT is used for input data and SIN is used for output data
+ */
+#define LPSPI_CFGR1_PINCFG(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
+#define LPSPI_CFGR1_OUTCFG_MASK  (0x4000000U)
+#define LPSPI_CFGR1_OUTCFG_SHIFT (26U)
+/*! OUTCFG - Output Configuration
+ *  0b0..Output data retains last value when chip select is negated
+ *  0b1..Output data is tristated when chip select is negated
+ */
+#define LPSPI_CFGR1_OUTCFG(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
+#define LPSPI_CFGR1_PCSCFG_MASK  (0x8000000U)
+#define LPSPI_CFGR1_PCSCFG_SHIFT (27U)
+/*! PCSCFG - Peripheral Chip Select Configuration
+ *  0b0..PCS[3:2] are configured for chip select function
+ *  0b1..PCS[3:2] are configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2])
+ */
+#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
+
+/* DMR0 - Data Match Register 0 */
+#define LPSPI_DMR0_MATCH0_MASK  (0xFFFFFFFFU)
+#define LPSPI_DMR0_MATCH0_SHIFT (0U)
+#define LPSPI_DMR0_MATCH0(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
+
+/* DMR1 - Data Match Register 1 */
+#define LPSPI_DMR1_MATCH1_MASK  (0xFFFFFFFFU)
+#define LPSPI_DMR1_MATCH1_SHIFT (0U)
+#define LPSPI_DMR1_MATCH1(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
+
+/* CCR - Clock Configuration Register */
+#define LPSPI_CCR_SCKDIV_MASK  (0xFFU)
+#define LPSPI_CCR_SCKDIV_SHIFT (0U)
+#define LPSPI_CCR_SCKDIV(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
+#define LPSPI_CCR_DBT_MASK     (0xFF00U)
+#define LPSPI_CCR_DBT_SHIFT    (8U)
+#define LPSPI_CCR_DBT(x)       (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
+#define LPSPI_CCR_PCSSCK_MASK  (0xFF0000U)
+#define LPSPI_CCR_PCSSCK_SHIFT (16U)
+#define LPSPI_CCR_PCSSCK(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
+#define LPSPI_CCR_SCKPCS_MASK  (0xFF000000U)
+#define LPSPI_CCR_SCKPCS_SHIFT (24U)
+#define LPSPI_CCR_SCKPCS(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
+
+/* FCR - FIFO Control Register */
+#define LPSPI_FCR_TXWATER_MASK  (0x7U)
+#define LPSPI_FCR_TXWATER_SHIFT (0U)
+#define LPSPI_FCR_TXWATER(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
+#define LPSPI_FCR_RXWATER_MASK  (0x70000U)
+#define LPSPI_FCR_RXWATER_SHIFT (16U)
+#define LPSPI_FCR_RXWATER(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
+
+/* FSR - FIFO Status Register */
+#define LPSPI_FSR_TXCOUNT_MASK  (0xFU)
+#define LPSPI_FSR_TXCOUNT_SHIFT (0U)
+#define LPSPI_FSR_TXCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
+#define LPSPI_FSR_RXCOUNT_MASK  (0xF0000U)
+#define LPSPI_FSR_RXCOUNT_SHIFT (16U)
+#define LPSPI_FSR_RXCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
+
+/* TCR - Transmit Command Register */
+#define LPSPI_TCR_FRAMESZ_MASK  (0xFFFU)
+#define LPSPI_TCR_FRAMESZ_SHIFT (0U)
+#define LPSPI_TCR_FRAMESZ(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
+#define LPSPI_TCR_WIDTH_MASK    (0x30000U)
+#define LPSPI_TCR_WIDTH_SHIFT   (16U)
+/*! WIDTH - Transfer Width
+ *  0b00..1 bit transfer
+ *  0b01..2 bit transfer
+ *  0b10..4 bit transfer
+ *  0b11..Reserved
+ */
+#define LPSPI_TCR_WIDTH(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
+#define LPSPI_TCR_TXMSK_MASK  (0x40000U)
+#define LPSPI_TCR_TXMSK_SHIFT (18U)
+/*! TXMSK - Transmit Data Mask
+ *  0b0..Normal transfer
+ *  0b1..Mask transmit data
+ */
+#define LPSPI_TCR_TXMSK(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
+#define LPSPI_TCR_RXMSK_MASK  (0x80000U)
+#define LPSPI_TCR_RXMSK_SHIFT (19U)
+/*! RXMSK - Receive Data Mask
+ *  0b0..Normal transfer
+ *  0b1..Receive data is masked
+ */
+#define LPSPI_TCR_RXMSK(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
+#define LPSPI_TCR_CONTC_MASK  (0x100000U)
+#define LPSPI_TCR_CONTC_SHIFT (20U)
+/*! CONTC - Continuing Command
+ *  0b0..Command word for start of new transfer
+ *  0b1..Command word for continuing transfer
+ */
+#define LPSPI_TCR_CONTC(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
+#define LPSPI_TCR_CONT_MASK  (0x200000U)
+#define LPSPI_TCR_CONT_SHIFT (21U)
+/*! CONT - Continuous Transfer
+ *  0b0..Continuous transfer is disabled
+ *  0b1..Continuous transfer is enabled
+ */
+#define LPSPI_TCR_CONT(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
+#define LPSPI_TCR_BYSW_MASK  (0x400000U)
+#define LPSPI_TCR_BYSW_SHIFT (22U)
+/*! BYSW - Byte Swap
+ *  0b0..Byte swap is disabled
+ *  0b1..Byte swap is enabled
+ */
+#define LPSPI_TCR_BYSW(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
+#define LPSPI_TCR_LSBF_MASK  (0x800000U)
+#define LPSPI_TCR_LSBF_SHIFT (23U)
+/*! LSBF - LSB First
+ *  0b0..Data is transferred MSB first
+ *  0b1..Data is transferred LSB first
+ */
+#define LPSPI_TCR_LSBF(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
+#define LPSPI_TCR_PCS_MASK  (0x3000000U)
+#define LPSPI_TCR_PCS_SHIFT (24U)
+/*! PCS - Peripheral Chip Select
+ *  0b00..Transfer using LPSPI_PCS[0]
+ *  0b01..Transfer using LPSPI_PCS[1]
+ *  0b10..Transfer using LPSPI_PCS[2]
+ *  0b11..Transfer using LPSPI_PCS[3]
+ */
+#define LPSPI_TCR_PCS(x)         (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
+#define LPSPI_TCR_PRESCALE_MASK  (0x38000000U)
+#define LPSPI_TCR_PRESCALE_SHIFT (27U)
+/*! PRESCALE - Prescaler Value
+ *  0b000..Divide by 1
+ *  0b001..Divide by 2
+ *  0b010..Divide by 4
+ *  0b011..Divide by 8
+ *  0b100..Divide by 16
+ *  0b101..Divide by 32
+ *  0b110..Divide by 64
+ *  0b111..Divide by 128
+ */
+#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
+#define LPSPI_TCR_CPHA_MASK   (0x40000000U)
+#define LPSPI_TCR_CPHA_SHIFT  (30U)
+/*! CPHA - Clock Phase
+ *  0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK
+ *  0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK
+ */
+#define LPSPI_TCR_CPHA(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
+#define LPSPI_TCR_CPOL_MASK  (0x80000000U)
+#define LPSPI_TCR_CPOL_SHIFT (31U)
+/*! CPOL - Clock Polarity
+ *  0b0..The inactive state value of SCK is low
+ *  0b1..The inactive state value of SCK is high
+ */
+#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
+
+/* TDR - Transmit Data Register */
+#define LPSPI_TDR_DATA_MASK  (0xFFFFFFFFU)
+#define LPSPI_TDR_DATA_SHIFT (0U)
+#define LPSPI_TDR_DATA(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
+
+/* RSR - Receive Status Register */
+#define LPSPI_RSR_SOF_MASK  (0x1U)
+#define LPSPI_RSR_SOF_SHIFT (0U)
+/*! SOF - Start Of Frame
+ *  0b0..Subsequent data word received after LPSPI_PCS assertion
+ *  0b1..First data word received after LPSPI_PCS assertion
+ */
+#define LPSPI_RSR_SOF(x)        (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
+#define LPSPI_RSR_RXEMPTY_MASK  (0x2U)
+#define LPSPI_RSR_RXEMPTY_SHIFT (1U)
+/*! RXEMPTY - RX FIFO Empty
+ *  0b0..RX FIFO is not empty
+ *  0b1..RX FIFO is empty
+ */
+#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
+
+/* RDR - Receive Data Register */
+#define LPSPI_RDR_DATA_MASK  (0xFFFFFFFFU)
+#define LPSPI_RDR_DATA_SHIFT (0U)
+#define LPSPI_RDR_DATA(x)    (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
+
+/* end of group LPSPI_Register_Masks */
+
+#endif /* _FSL_LPSPI_H_ */
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 3f97730bad0..c9a92d4acc4 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -39,6 +39,9 @@
 #include <linux/sizes.h>
 #include <linux/err.h>
 #include <asm/io.h>
+#if CONFIG_IS_ENABLED(IMX_MODULE_FUSE)
+#include <asm/mach-imx/sys_proto.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -809,6 +812,13 @@ static int fsl_qspi_probe(struct udevice *bus)
 
 	q->iobase = map_physmem(res.start, res.end - res.start, MAP_NOCACHE);
 
+#if CONFIG_IS_ENABLED(IMX_MODULE_FUSE)
+	if (qspi_fused((ulong)(q->iobase))) {
+		printf("QSPI@0x%lx is fused, disable it\n", (ulong)(q->iobase));
+		return -ENODEV;
+	}
+#endif
+
 	ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
 				     "QuadSPI-memory", &res);
 	if (ret) {
diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 5adfdf8b5fc..61f91bf0509 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -1,6 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
  */
 
 #include <common.h>
@@ -19,6 +21,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 #include <asm/mach-imx/spi.h>
+#include <asm/mach-imx/sys_proto.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -535,6 +538,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 		return NULL;
 	}
 
+	if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
+		if (ecspi_fused(spi_bases[bus])) {
+			printf("ECSPI@0x%lx is fused, disable it\n", spi_bases[bus]);
+			return NULL;
+		}
+	}
+
 	mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
 	if (!mxcs) {
 		puts("mxc_spi: SPI Slave not allocated !\n");
diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c
index b7c922b1dfd..2cab06bdd88 100644
--- a/drivers/spi/nxp_fspi.c
+++ b/drivers/spi/nxp_fspi.c
@@ -56,9 +56,11 @@
 /*
  * The driver only uses one single LUT entry, that is updated on
  * each call of exec_op(). Index 0 is preset at boot with a basic
- * read operation, so let's use the last entry (31).
+ * read operation, so let's use the middle entry (15).
+ * for some platforms, this is the last entry
  */
-#define	SEQID_LUT			31
+#define	SEQID_LUT			15
+#define	SEQID_AHB_LUT			14
 
 /* Registers used by the driver */
 #define FSPI_MCR0			0x00
@@ -209,9 +211,13 @@
 
 #define FSPI_DLLACR			0xC0
 #define FSPI_DLLACR_OVRDEN		BIT(8)
+#define FSPI_DLLACR_SLVDLY(x)          ((x) << 3)
+#define FSPI_DLLACR_DLLEN              BIT(0)
 
 #define FSPI_DLLBCR			0xC4
 #define FSPI_DLLBCR_OVRDEN		BIT(8)
+#define FSPI_DLLBCR_SLVDLY(x)          ((x) << 3)
+#define FSPI_DLLBCR_DLLEN              BIT(0)
 
 #define FSPI_STS0			0xE0
 #define FSPI_STS0_DLPHB(x)		((x) << 8)
@@ -247,6 +253,10 @@
 #define FSPI_LUT_REG(idx) \
 	(FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4)
 
+#define FSPI_AHB_LUT_OFFSET			(SEQID_AHB_LUT * 4 * 4)
+#define FSPI_AHB_LUT_REG(idx) \
+	(FSPI_LUT_BASE + FSPI_AHB_LUT_OFFSET + (idx) * 4)
+
 /* register map end */
 
 /* Instruction set for the LUT register. */
@@ -336,14 +346,41 @@ static struct nxp_fspi_devtype_data imx8mm_data = {
 	.little_endian = true,  /* little-endian    */
 };
 
+static const struct nxp_fspi_devtype_data imx8qxp_data = {
+	.rxfifo = SZ_512,       /* (64  * 64 bits)  */
+	.txfifo = SZ_1K,        /* (128 * 64 bits)  */
+	.ahb_buf_size = SZ_2K,  /* (256 * 64 bits)  */
+	.quirks = 0,
+	.little_endian = true,  /* little-endian    */
+};
+
+static const struct nxp_fspi_devtype_data imx8dxl_data = {
+	.rxfifo = SZ_512,       /* (64  * 64 bits)  */
+	.txfifo = SZ_1K,        /* (128 * 64 bits)  */
+	.ahb_buf_size = SZ_2K,  /* (256 * 64 bits)  */
+	.quirks = FSPI_QUIRK_USE_IP_ONLY,
+	.little_endian = true,  /* little-endian    */
+};
+
+static const struct nxp_fspi_devtype_data imx8ulp_data = {
+	.rxfifo = SZ_1K,       /* (128  * 64 bits)  */
+	.txfifo = SZ_1K,        /* (128 * 64 bits)  */
+	.ahb_buf_size = SZ_2K,  /* (256 * 64 bits)  */
+	.quirks = 0,
+	.little_endian = true,  /* little-endian    */
+};
+
 struct nxp_fspi {
 	struct udevice *dev;
 	void __iomem *iobase;
 	void __iomem *ahb_addr;
 	u32 memmap_phy;
 	u32 memmap_phy_size;
+	u32 dll_slvdly;
 	struct clk clk, clk_en;
 	struct nxp_fspi_devtype_data *devtype_data;
+#define FSPI_DTR_ODD_ADDR       (1 << 0)
+	int flags;
 };
 
 static inline int needs_ip_only(struct nxp_fspi *f)
@@ -489,12 +526,21 @@ static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
 	int lutidx = 1, i;
 
 	/* cmd */
-	lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
-			     op->cmd.opcode);
+	if (op->cmd.dtr) {
+		lutval[0] |= LUT_DEF(0, LUT_CMD_DDR, LUT_PAD(op->cmd.buswidth),
+				     op->cmd.opcode >> 8);
+		lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_CMD_DDR,
+					      LUT_PAD(op->cmd.buswidth),
+					      op->cmd.opcode & 0x00ff);
+		lutidx++;
+	} else {
+		lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
+				     op->cmd.opcode);
+	}
 
 	/* addr bytes */
 	if (op->addr.nbytes) {
-		lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR,
+		lutval[lutidx / 2] |= LUT_DEF(lutidx, op->addr.dtr ? LUT_ADDR_DDR : LUT_ADDR,
 					      LUT_PAD(op->addr.buswidth),
 					      op->addr.nbytes * 8);
 		lutidx++;
@@ -502,7 +548,7 @@ static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
 
 	/* dummy bytes, if needed */
 	if (op->dummy.nbytes) {
-		lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY,
+		lutval[lutidx / 2] |= LUT_DEF(lutidx, op->dummy.dtr ? LUT_DUMMY_DDR : LUT_DUMMY,
 		/*
 		 * Due to FlexSPI controller limitation number of PAD for dummy
 		 * buswidth needs to be programmed as equal to data buswidth.
@@ -517,7 +563,8 @@ static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
 	if (op->data.nbytes) {
 		lutval[lutidx / 2] |= LUT_DEF(lutidx,
 					      op->data.dir == SPI_MEM_DATA_IN ?
-					      LUT_NXP_READ : LUT_NXP_WRITE,
+					      (op->data.dtr ? LUT_READ_DDR : LUT_NXP_READ) :
+					      (op->data.dtr ? LUT_WRITE_DDR : LUT_NXP_WRITE),
 					      LUT_PAD(op->data.buswidth),
 					      0);
 		lutidx++;
@@ -534,6 +581,12 @@ static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
 	for (i = 0; i < ARRAY_SIZE(lutval); i++)
 		fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i));
 
+	if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN &&
+		op->addr.nbytes) {
+		for (i = 0; i < ARRAY_SIZE(lutval); i++)
+			fspi_writel(f, lutval[i], base + FSPI_AHB_LUT_REG(i));
+	}
+
 	dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x], size: 0x%08x\n",
 		op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3], op->data.nbytes);
 
@@ -681,14 +734,45 @@ static void nxp_fspi_read_rxfifo(struct nxp_fspi *f,
 {
 	void __iomem *base = f->iobase;
 	int i, ret;
-	int len = op->data.nbytes;
+	int len, cnt;
 	u8 *buf = (u8 *)op->data.buf.in;
 
+	/* DTR with ODD address need read one more byte */
+	len = (f->flags & FSPI_DTR_ODD_ADDR) ? op->data.nbytes + 1 : op->data.nbytes;
+
+	/* handle the DTR with ODD address case */
+	if (f->flags & FSPI_DTR_ODD_ADDR) {
+		u8 tmp[8];
+		/* Wait for RXFIFO available */
+		ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
+					   FSPI_INTR_IPRXWA, 0,
+					   POLL_TOUT, true);
+		WARN_ON(ret);
+		/*
+		 * DTR read always start from 2bytes alignment address,
+		 * if read from an odd address A, it actually read from
+		 * address A-1, need to discard the first byte here
+		 */
+		*(u32 *)tmp = fspi_readl(f, base + FSPI_RFDR);
+		*(u32 *)(tmp + 4) = fspi_readl(f, base + FSPI_RFDR + 4);
+		cnt = min(len, 8);
+		/* discard the first byte */
+		memcpy(buf, tmp + 1, cnt - 1);
+		len -= cnt;
+		buf = op->data.buf.in + cnt - 1;
+		f->flags &= ~FSPI_DTR_ODD_ADDR;
+
+		/* move the FIFO pointer */
+		fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
+	}
+
 	/*
 	 * Default value of water mark level is 8 bytes, hence in single
 	 * read request controller can read max 8 bytes of data.
 	 */
-	for (i = 0; i < ALIGN_DOWN(len, 8); i += 8) {
+	cnt = ALIGN_DOWN(len, 8);
+
+	for (i = 0; i < cnt;) {
 		/* Wait for RXFIFO available */
 		ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
 					   FSPI_INTR_IPRXWA, 0,
@@ -697,6 +781,7 @@ static void nxp_fspi_read_rxfifo(struct nxp_fspi *f,
 
 		*(u32 *)(buf + i) = fspi_readl(f, base + FSPI_RFDR);
 		*(u32 *)(buf + i + 4) = fspi_readl(f, base + FSPI_RFDR + 4);
+		i += 8;
 		/* move the FIFO pointer */
 		fspi_writel(f, FSPI_INTR_IPRXWA, base + FSPI_INTR);
 	}
@@ -705,14 +790,14 @@ static void nxp_fspi_read_rxfifo(struct nxp_fspi *f,
 		u32 tmp;
 		int size, j;
 
-		buf = op->data.buf.in + i;
+		buf += i;
+		len -= i;
 		/* Wait for RXFIFO available */
 		ret = fspi_readl_poll_tout(f, f->iobase + FSPI_INTR,
 					   FSPI_INTR_IPRXWA, 0,
 					   POLL_TOUT, true);
 		WARN_ON(ret);
 
-		len = op->data.nbytes - i;
 		for (j = 0; j < op->data.nbytes - i; j += 4) {
 			tmp = fspi_readl(f, base + FSPI_RFDR + j);
 			size = min(len, 4);
@@ -746,10 +831,23 @@ static int nxp_fspi_do_op(struct nxp_fspi *f, const struct spi_mem_op *op)
 	 * the LUT at each exec_op() call. And also specify the DATA
 	 * length, since it's has not been specified in the LUT.
 	 */
-	fspi_writel(f, op->data.nbytes |
-		 (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) |
-		 (seqnum << FSPI_IPCR1_SEQNUM_SHIFT),
-		 base + FSPI_IPCR1);
+
+	/*
+	 * DTR read always start from 2bytes alignment address,
+	 * if read from an odd address A, it actually read from
+	 * address A-1, need to read one more byte to get all
+	 * data needed.
+	 */
+	if (f->flags & FSPI_DTR_ODD_ADDR)
+		fspi_writel(f, (op->data.nbytes + 1) |
+			 (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) |
+			 (seqnum << FSPI_IPCR1_SEQNUM_SHIFT),
+			 base + FSPI_IPCR1);
+	else
+		fspi_writel(f, op->data.nbytes |
+			 (SEQID_LUT << FSPI_IPCR1_SEQID_SHIFT) |
+			 (seqnum << FSPI_IPCR1_SEQNUM_SHIFT),
+			 base + FSPI_IPCR1);
 
 	/* Trigger the LUT now. */
 	fspi_writel(f, FSPI_IPCMD_TRG, base + FSPI_IPCMD);
@@ -771,6 +869,8 @@ static int nxp_fspi_exec_op(struct spi_slave *slave,
 	struct nxp_fspi *f;
 	struct udevice *bus;
 	int err = 0;
+	u32 reg;
+
 
 	bus = slave->dev->parent;
 	f = dev_get_priv(bus);
@@ -780,6 +880,12 @@ static int nxp_fspi_exec_op(struct spi_slave *slave,
 				   FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, true);
 	WARN_ON(err);
 
+	if (op->cmd.dtr && op->addr.dtr && op->dummy.dtr && op->data.dtr) {
+		reg = fspi_readl(f, f->iobase + FSPI_MCR0);
+		reg |= FSPI_MCR0_RXCLKSRC(3);
+		fspi_writel(f, reg, f->iobase + FSPI_MCR0);
+	}
+
 	nxp_fspi_prepare_lut(f, op);
 	/*
 	 * If we have large chunks of data, we read them through the AHB bus by
@@ -817,6 +923,12 @@ static int nxp_fspi_adjust_op_size(struct spi_slave *slave,
 		if (op->data.nbytes > f->devtype_data->txfifo)
 			op->data.nbytes = f->devtype_data->txfifo;
 	} else {
+		/* need to handle the OCTAL DTR read with odd dtr case */
+		if ((op->addr.val & 1) && op->cmd.dtr && op->addr.dtr &&
+		    op->dummy.dtr && op->data.dtr) {
+			f->flags |= FSPI_DTR_ODD_ADDR;
+		}
+
 		if (op->data.nbytes > f->devtype_data->ahb_buf_size)
 			op->data.nbytes = f->devtype_data->ahb_buf_size;
 		else if (op->data.nbytes > (f->devtype_data->rxfifo - 4))
@@ -826,8 +938,19 @@ static int nxp_fspi_adjust_op_size(struct spi_slave *slave,
 	/* Limit data bytes to RX FIFO in case of IP read only */
 	if (needs_ip_only(f) &&
 	    op->data.dir == SPI_MEM_DATA_IN &&
-	    op->data.nbytes > f->devtype_data->rxfifo)
-		op->data.nbytes = f->devtype_data->rxfifo;
+	    op->data.nbytes > f->devtype_data->rxfifo) {
+		/*
+		 * adjust size to to odd number so the OCTAL DTR
+		 * read with odd address only triggers once, when
+		 * reading large chunks of data
+		 */
+		if (f->flags & FSPI_DTR_ODD_ADDR) {
+			op->data.nbytes = f->devtype_data->rxfifo
+					  - 4 - 1;
+		} else {
+			op->data.nbytes = f->devtype_data->rxfifo;
+		}
+	}
 
 	return 0;
 }
@@ -903,8 +1026,16 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f)
 	fspi_writel(f, FSPI_DLLACR_OVRDEN, base + FSPI_DLLACR);
 	fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR);
 
+	if (f->dll_slvdly) {
+		fspi_writel(f, FSPI_DLLACR_DLLEN | FSPI_DLLACR_SLVDLY(4),
+			    base + FSPI_DLLACR);
+		fspi_writel(f, FSPI_DLLBCR_DLLEN | FSPI_DLLBCR_SLVDLY(4),
+			    base + FSPI_DLLBCR);
+	}
+
 	/* enable module */
-	fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | FSPI_MCR0_IP_TIMEOUT(0xFF),
+	fspi_writel(f, (u32)FSPI_MCR0_AHB_TIMEOUT(0xFF) |
+		    FSPI_MCR0_IP_TIMEOUT(0xFF) | FSPI_MCR0_OCTCOMB_EN,
 		    base + FSPI_MCR0);
 
 	/*
@@ -931,10 +1062,10 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f)
 		    base + FSPI_AHBCR);
 
 	/* AHB Read - Set lut sequence ID for all CS. */
-	fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2);
-	fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2);
-	fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2);
-	fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2);
+	fspi_writel(f, SEQID_AHB_LUT, base + FSPI_FLSHA1CR2);
+	fspi_writel(f, SEQID_AHB_LUT, base + FSPI_FLSHA2CR2);
+	fspi_writel(f, SEQID_AHB_LUT, base + FSPI_FLSHB1CR2);
+	fspi_writel(f, SEQID_AHB_LUT, base + FSPI_FLSHB2CR2);
 
 	return 0;
 }
@@ -1018,6 +1149,9 @@ static int nxp_fspi_of_to_plat(struct udevice *bus)
 	f->ahb_addr = map_physmem(ahb_addr, ahb_size, MAP_NOCACHE);
 	f->memmap_phy_size = ahb_size;
 
+	/* check if need to set the slave delay line */
+	dev_read_u32(bus, "nxp,fspi-dll-slvdly", &f->dll_slvdly);
+
 #if CONFIG_IS_ENABLED(CLK)
 	ret = clk_get_by_name(bus, "fspi_en", &f->clk_en);
 	if (ret) {
@@ -1053,6 +1187,9 @@ static const struct dm_spi_ops nxp_fspi_ops = {
 static const struct udevice_id nxp_fspi_ids[] = {
 	{ .compatible = "nxp,lx2160a-fspi", .data = (ulong)&lx2160a_data, },
 	{ .compatible = "nxp,imx8mm-fspi", .data = (ulong)&imx8mm_data, },
+	{ .compatible = "nxp,imx8qxp-fspi", .data = (ulong)&imx8qxp_data, },
+	{ .compatible = "nxp,imx8dxl-fspi", .data = (ulong)&imx8dxl_data, },
+	{ .compatible = "nxp,imx8ulp-fspi", .data = (ulong)&imx8ulp_data, },
 	{ }
 };
 
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index f6d60038b89..b271806ad25 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -80,7 +80,7 @@ config SYSRESET_OCTEON
 config SYSRESET_PSCI
 	bool "Enable support for PSCI System Reset"
 	depends on ARM_PSCI_FW
-	select SPL_ARM_PSCI_FW if SPL
+	select SPL_ARM_PSCI_FW if SPL_SYSRESET
 	help
 	  Enable PSCI SYSTEM_RESET function call.  To use this, PSCI firmware
 	  must be running on your system.
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 97d4163e8ed..8666d67483a 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -35,6 +35,19 @@ config IMX_TMU
 	  The boot is hold to the cool device to throttle CPUs when the
 	  passive trip is crossed
 
+config IMX_PMC_TEMPERATURE
+	bool "PMC Temperature Sensor driver for NXP i.MX8ULP"
+	depends on ARCH_IMX8ULP
+	help
+	  Enable PMC Temperature Sensor on NXP i.MX8ULP. The driver supports
+	  reading CPU temperature.
+
+config SCMI_THERMAL
+	bool "SCMI Sensor based thermal driver"
+	select SCMI_FIRMWARE
+	help
+	  Enable SCMI Sensor protocol based thermal driver to get temperature.
+
 config TI_DRA7_THERMAL
         bool "Temperature sensor driver for TI dra7xx SOCs"
         help
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 15fe847d9f7..779f7d96423 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -8,3 +8,5 @@ obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
 obj-$(CONFIG_IMX_SCU_THERMAL) += imx_scu_thermal.o
 obj-$(CONFIG_TI_DRA7_THERMAL) += ti-bandgap.o
 obj-$(CONFIG_IMX_TMU) += imx_tmu.o
+obj-$(CONFIG_IMX_PMC_TEMPERATURE) += imx_pmc_temperature.o
+obj-$(CONFIG_SCMI_THERMAL) += scmi_thermal.o
diff --git a/drivers/thermal/imx_pmc_temperature.c b/drivers/thermal/imx_pmc_temperature.c
new file mode 100644
index 00000000000..3bfe3b49920
--- /dev/null
+++ b/drivers/thermal/imx_pmc_temperature.c
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+
+#include <asm/arch/imx-regs.h>
+#include <asm/arch-imx8ulp/clock.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <thermal.h>
+
+#define ADC_CTRL_ADCEN_MASK	0x1
+#define ADC_CTRL_RST_MASK	0x2
+#define ADC_CTRL_DOZEN_MASK	0x4
+#define ADC_CTRL_RSTFIFO0_MASK	0x100
+
+#define ADC_CFG_PUDLY(x)	(((u32)(((u32)(x)) << 16)) & 0xff0000)
+#define ADC_CFG_PWREN_MASK	0x10000000
+
+#define ADC_CMDL_ADCH(x)	(((u32)(((u32)(x)) << 0)) & 0x1f)
+#define ADC_CMDL_DIFF(x)	(((u32)(((u32)(x)) << 6)) & 0x40)
+#define ADC_CMDL_CSCALE(x)	(((u32)(((u32)(x)) << 13)) & 0x2000)
+
+#define ADC_CMDH_STS(x)		(((u32)(((u32)(x)) << 8)) & 0x700)
+#define ADC_CMDH_AVGS(x)	(((u32)(((u32)(x)) << 12)) & 0x7000)
+
+#define ADC_TCTRL_TCMD(x)	(((u32)(((u32)(x)) << 24)) & 0xf000000)
+
+#define ANACORE_CTRL_OFFSET     0x30
+#define TSENSM_MASK	0xf00000
+#define TSENSM(x)	(((u32)(((u32)(x)) << 20)) & 0xf00000)
+#define TSENSEN_MASK	0x10000
+#define TSENSEN(x)	(((u32)(((u32)(x)) << 16)) & 0x10000)
+
+static int imx_read_pmc_temperature(struct udevice *dev, int *temperature)
+{
+	void __iomem *pmc_reg;
+	void __iomem *pmc_anacore_ctrl_addr;
+	struct adc_regs *regs;
+	struct ofnode_phandle_args args;
+	u8 tsensm[7] = {0, 2, 6, 4, 6, 2, 0};
+	u16 tsensorvalue[7] = {0}, conv_value;
+	u32 val, tmp32, i, cm_000, cm_010, cm_110, c1_temp, c2_temp, cm_temp, vm_temp;
+	int ret;
+	fdt_addr_t addr = devfdt_get_addr_index(dev, 0);
+
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	pmc_reg = (void __iomem *)addr;
+	pmc_anacore_ctrl_addr = (void __iomem *)(addr + ANACORE_CTRL_OFFSET);
+
+	/* enable the ADC1's clock */
+	enable_adc1_clk(true);
+
+	ret = dev_read_phandle_with_args(dev, "adc", NULL, 0, 0, &args);
+	if (ret)
+		return ret;
+	addr = ofnode_get_addr(args.node);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	regs = (struct adc_regs *)addr;
+	/* reset the ADC1's configuration */
+	val = readl(&regs->ctrl);
+	val |= ADC_CTRL_RST_MASK;
+	writel(val, &regs->ctrl);
+	val = readl(&regs->ctrl);
+	val &= ~ADC_CTRL_RST_MASK;
+	writel(val, &regs->ctrl);
+
+	/* reset the conversion FIFO0 */
+	val = readl(&regs->ctrl);
+	val |= ADC_CTRL_RSTFIFO0_MASK;
+	writel(val, &regs->ctrl);
+
+	/* disable the ADC1 */
+	val = readl(&regs->ctrl);
+	val &= ~ADC_CTRL_ADCEN_MASK;
+	writel(val, &regs->ctrl);
+
+	/* ADC1 is enabled in Doze mode */
+	val = readl(&regs->ctrl);
+	val &= ~ADC_CTRL_DOZEN_MASK;
+	writel(val, &regs->ctrl);
+
+	/* ADC1's Configuration Register */
+	val = 0;
+	val |= ADC_CFG_PWREN_MASK;
+	val |= ADC_CFG_PUDLY(0x80);
+	writel(val, &regs->cfg);
+
+	/* enable the ADC1 */
+	val = readl(&regs->ctrl);
+	val |= ADC_CTRL_ADCEN_MASK;
+	writel(val, &regs->ctrl);
+
+	/* reset the conversion FIFO0 */
+	val = readl(&regs->ctrl);
+	val |= ADC_CTRL_RSTFIFO0_MASK;
+	writel(val, &regs->ctrl);
+
+	/* set conversion CMD configuration */
+	val = readl(&regs->cmdl1);
+	val |= ADC_CMDL_ADCH(8);
+	val |= ADC_CMDL_DIFF(1);
+	val |= ADC_CMDL_CSCALE(1);
+	writel(val, &regs->cmdl1);
+
+	val = readl(&regs->cmdh1);
+	val |= ADC_CMDH_STS(7);
+	val |= ADC_CMDH_AVGS(7);
+	writel(val, &regs->cmdh1);
+
+	/* set trigger configuration */
+	val = readl(&regs->tctrl0);
+	val |= ADC_TCTRL_TCMD(1);
+	writel(val, &regs->tctrl0);
+
+	/* enable PMC temperature sensor and wait 40us */
+	val = readl(pmc_anacore_ctrl_addr);
+	val &= ~TSENSEN_MASK;
+	val |= TSENSEN(1);
+	writel(val, pmc_anacore_ctrl_addr);
+	udelay(40);
+
+	for (i = 0; i < 7; i++) {
+		val = readl(pmc_reg);
+		val &= ~TSENSM_MASK;
+		val |= TSENSM(tsensm[i]);
+		writel(val, pmc_reg);
+
+		writel(1, &regs->swtrig);
+		while (((tmp32 = readl(&regs->resfifo0)) & 0x80000000) == 0) {}
+		conv_value = (u16)((tmp32 & 0xffff) >> 3);
+		tsensorvalue[i] = conv_value;
+	}
+
+	cm_000 = (tsensorvalue[0] + tsensorvalue[6]) / 2;
+	cm_010 = (tsensorvalue[1] + tsensorvalue[5]) / 2;
+	cm_110 = (tsensorvalue[2] + tsensorvalue[4]) / 2;
+	c1_temp = (2 * cm_000 - cm_010);
+	c2_temp = (2 * tsensorvalue[3] - cm_110);
+	cm_temp = (c1_temp + c2_temp) / 2;
+	vm_temp = (100 * cm_temp + 80 * cm_temp) / 4096;
+	*temperature = (303 * vm_temp + 105 * vm_temp / 1000 - 27315) / 100;
+
+	return 0;
+}
+
+static const struct dm_thermal_ops temperature_ops = {
+	.get_temp = imx_read_pmc_temperature,
+};
+
+static int imx_pmc_temperature_probe(struct udevice *dev)
+{
+	return 0;
+}
+
+static const struct udevice_id imx_ids[] = {
+	{ .compatible = "fsl,imx8ulp-pmc-temperature", },
+	{ }
+};
+
+U_BOOT_DRIVER(imx_pmc_temperature) = {
+	.name	= "imx_pmc_temperature",
+	.id	= UCLASS_THERMAL,
+	.ops	= &temperature_ops,
+	.of_match = imx_ids,
+	.probe	= imx_pmc_temperature_probe,
+	.flags  = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/thermal/scmi_thermal.c b/drivers/thermal/scmi_thermal.c
new file mode 100644
index 00000000000..bccfd28c2f7
--- /dev/null
+++ b/drivers/thermal/scmi_thermal.c
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <thermal.h>
+#include <scmi_agent.h>
+#include <scmi_protocols.h>
+#include <asm/types.h>
+#include <dm/device-internal.h>
+#include <dm/device.h>
+
+struct scmi_thermal_priv {
+	s16 num_sensors;
+	s16 thermal_id;
+	struct scmi_sensor_descrition_get_p2a *desc_buf;
+	size_t desc_buf_size;
+};
+
+static int scmi_thermal_get_temp(struct udevice *dev, int *temp)
+{
+	struct scmi_thermal_priv *priv = dev_get_priv(dev);
+	struct scmi_sensor_reading_get_a2p in = { priv->thermal_id };
+	struct scmi_sensor_reading_get_p2a out = { 0 };
+	struct scmi_msg msg = {
+		.protocol_id = SCMI_PROTOCOL_ID_SENSOR,
+		.message_id = SCMI_SENSOR_READING_GET,
+		.in_msg = (u8 *)&in,
+		.in_msg_sz = sizeof(in),
+		.out_msg = (u8 *)&out,
+		.out_msg_sz = sizeof(out),
+	};
+	int ret;
+
+	ret = devm_scmi_process_msg(dev->parent, &msg);
+	if (ret)
+		return ret;
+
+	ret = scmi_to_linux_errno(out.status);
+	if (ret < 0)
+		return ret;
+
+	*temp = out.val.value_low;
+
+	return ret;
+}
+
+static int scmi_sensor_attributes_get(struct udevice *dev)
+{
+	struct scmi_protocol_attributes_p2a_sensor out = { 0 };
+	struct scmi_msg msg = {
+		.protocol_id = SCMI_PROTOCOL_ID_SENSOR,
+		.message_id = SCMI_PROTOCOL_ATTRIBUTES,
+		.in_msg = NULL,
+		.in_msg_sz = 0,
+		.out_msg = (u8 *)&out,
+		.out_msg_sz = sizeof(out),
+	};
+	int ret;
+	struct scmi_thermal_priv *priv = dev_get_priv(dev);
+
+	ret = devm_scmi_process_msg(dev->parent, &msg);
+	if (ret)
+		return ret;
+
+	ret = scmi_to_linux_errno(out.status);
+	if (ret < 0)
+		return ret;
+
+	priv->num_sensors = out.num_sensors;
+
+	dev_dbg(dev,"num_sensors %d\n", priv->num_sensors);
+
+	return 0;
+}
+
+static int scmi_sensor_description_get(struct udevice *dev, u32 start_ind,
+	struct scmi_sensor_descrition_get_p2a *desc_buf, size_t desc_buf_size)
+{
+	struct scmi_sensor_description_get_a2p in = { start_ind };
+	struct scmi_msg msg = {
+		.protocol_id = SCMI_PROTOCOL_ID_SENSOR,
+		.message_id = SCMI_SENSOR_DESCRIPTION_GET,
+		.in_msg = (u8 *)&in,
+		.in_msg_sz = sizeof(in),
+		.out_msg = (u8 *)desc_buf,
+		.out_msg_sz = desc_buf_size,
+	};
+	int ret;
+
+	ret = devm_scmi_process_msg(dev->parent, &msg);
+	if (ret)
+		return ret;
+
+	ret = scmi_to_linux_errno(desc_buf->status);
+	if (ret < 0)
+		return ret;
+
+	return ret;
+}
+
+static const struct dm_thermal_ops scmi_thermal_ops = {
+	.get_temp	= scmi_thermal_get_temp,
+};
+
+static int scmi_thermal_probe(struct udevice *dev)
+{
+	int ret;
+	u16 num_returned, num_remaining, cnt;
+	u32 index = 0;
+	bool find = false;
+	struct scmi_sensor_desc *desc;
+	struct scmi_thermal_priv *priv = dev_get_priv(dev);
+
+	ret = scmi_sensor_attributes_get(dev);
+	if (ret){
+		dev_err(dev, "scmi_sensor_attributes_get failure %d\n", ret);
+		return ret;
+	}
+
+	priv->desc_buf_size = sizeof(struct scmi_sensor_descrition_get_p2a) +
+		(priv->num_sensors - 1) * sizeof(struct scmi_sensor_desc);
+	priv->desc_buf = (struct scmi_sensor_descrition_get_p2a *)calloc(1, priv->desc_buf_size);
+	if (!priv->desc_buf) {
+		dev_err(dev, "allocate desc_buffer failure\n");
+		return -ENOMEM;
+	}
+
+	do {
+		ret = scmi_sensor_description_get(dev, index, priv->desc_buf, priv->desc_buf_size);
+		if (ret){
+			dev_err(dev, "scmi_sensor_description_get failure %d\n", ret);
+			return ret;
+		}
+
+		num_returned = priv->desc_buf->num_sensor_flags & 0xffff;
+		num_remaining = (priv->desc_buf->num_sensor_flags >> 16) & 0xffff;
+
+		if (index + num_returned > priv->num_sensors) {
+			dev_err(dev, "Num of sensors can't exceed %d",
+				priv->num_sensors);
+			return -EINVAL;
+		}
+
+		for (cnt = 0; cnt < num_returned; cnt++) {
+			desc = &priv->desc_buf->desc[cnt];
+			if ((desc->attr_high & 0xff) == 0x2) {
+				priv->thermal_id = desc->id; /* Only get one thermal sensor */
+				dev_dbg(dev, "thermal id %u\n", priv->thermal_id);
+				find = true;
+				break;
+			}
+		}
+
+		index += num_returned;
+	} while (num_returned && num_remaining && !find);
+
+	if (!find) {
+		dev_err(dev, "Can't find thermal sensor device\n");
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+U_BOOT_DRIVER(scmi_thermal) = {
+	.name = "scmi_thermal",
+	.id = UCLASS_THERMAL,
+	.ops = &scmi_thermal_ops,
+	.probe = scmi_thermal_probe,
+	.flags = DM_FLAG_PRE_RELOC,
+	.priv_auto	= sizeof(struct scmi_thermal_priv),
+};
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index ab1d061bd0d..f67fa677f51 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -68,12 +68,12 @@ config SPL_DM_USB_GADGET
 
 source "drivers/usb/host/Kconfig"
 
-source "drivers/usb/cdns3/Kconfig"
-
 source "drivers/usb/dwc3/Kconfig"
 
 source "drivers/usb/mtu3/Kconfig"
 
+source "drivers/usb/cdns3/Kconfig"
+
 source "drivers/usb/musb/Kconfig"
 
 source "drivers/usb/musb-new/Kconfig"
diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
index 35b61497d9c..11a7144b050 100644
--- a/drivers/usb/cdns3/Kconfig
+++ b/drivers/usb/cdns3/Kconfig
@@ -1,58 +1,20 @@
 config USB_CDNS3
 	tristate "Cadence USB3 Dual-Role Controller"
-	depends on USB_XHCI_HCD || USB_GADGET
+    depends on (USB && USB_GADGET)
 	help
-	  Say Y here if your system has a Cadence USB3 dual-role controller.
-	  It supports: Host-only, and Peripheral-only.
+	  Say Y here if your system has a cadence USB3 dual-role controller.
+	  It supports: dual-role switch Host-only, and Peripheral-only.
+
+	  When compiled dynamically, the module will be called cdns3.ko.
 
 if USB_CDNS3
 
 config USB_CDNS3_GADGET
 	bool "Cadence USB3 device controller"
 	depends on USB_GADGET
-	select USB_GADGET_DUALSPEED
+    select USB_GADGET_DUALSPEED
 	help
 	  Say Y here to enable device controller functionality of the
-	  Cadence USBSS-DEV driver.
-
-	  This controller supports FF and HS mode. It doesn't support
-	  LS and SSP mode.
-
-config USB_CDNS3_HOST
-	bool "Cadence USB3 host controller"
-	depends on USB_XHCI_HCD
-	help
-	  Say Y here to enable host controller functionality of the
-	  Cadence driver.
+	  cadence usb3 driver.
 
-	  Host controller is compliant with XHCI so it will use
-	  standard XHCI driver.
-
-config SPL_USB_CDNS3_GADGET
-	bool "SPL support for Cadence USB3 device controller"
-	depends on SPL_USB_GADGET
-	select USB_GADGET_DUALSPEED
-	help
-	  Say Y here to enable device controller functionality of the
-	  Cadence USBSS-DEV driver in SPL.
-
-	  This controller supports FF and HS mode. It doesn't support
-	  LS and SSP mode.
-
-config SPL_USB_CDNS3_HOST
-	bool "Cadence USB3 host controller"
-	depends on USB_XHCI_HCD && SPL_USB_HOST
-	help
-	  Say Y here to enable host controller functionality of the
-	  Cadence driver.
-
-	  Host controller is compliant with XHCI so it will use
-	  standard XHCI driver.
-
-config USB_CDNS3_TI
-	tristate "Cadence USB3 support on TI platforms"
-	default USB_CDNS3
-	help
-	  Say 'Y' here if you are building for Texas Instruments
-	  platforms that contain Cadence USB3 controller core. E.g.: J721e.
 endif
diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile
index 18d7190755d..374fa06efa1 100644
--- a/drivers/usb/cdns3/Makefile
+++ b/drivers/usb/cdns3/Makefile
@@ -1,11 +1,5 @@
-# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_USB_CDNS3)		+= cdns3.o
 
-cdns3-y					:= core.o drd.o
-
-obj-$(CONFIG_USB_CDNS3)			+= cdns3.o
-
-cdns3-$(CONFIG_$(SPL_)USB_CDNS3_GADGET)	+= gadget.o ep0.o
-
-cdns3-$(CONFIG_$(SPL_)USB_CDNS3_HOST)	+= host.o
-
-obj-$(CONFIG_USB_CDNS3_TI)		+= cdns3-ti.o
+cdns3-y				:= core.o
+cdns3-$(CONFIG_USB_CDNS3_GADGET)	+= gadget.o
+cdns3-$(CONFIG_$(SPL_)DM_USB_GADGET)	+= cdns3-generic.o
diff --git a/drivers/usb/cdns3/cdns3-generic.c b/drivers/usb/cdns3/cdns3-generic.c
new file mode 100644
index 00000000000..bb9e7f91d0e
--- /dev/null
+++ b/drivers/usb/cdns3/cdns3-generic.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 NXP
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <linux/usb/gadget.h>
+#include <linux/bug.h>
+#include <dm/device-internal.h>
+#include "core.h"
+#include "gadget.h"
+
+static int cdns3_generic_peripheral_clk_init(struct udevice *dev,
+					     struct cdns3_generic_peripheral
+					     *priv)
+{
+#if CONFIG_IS_ENABLED(CLK)
+	int ret;
+
+	ret = clk_get_bulk(dev, &priv->clks);
+	if (ret == -ENOSYS)
+		return 0;
+	if (ret)
+		return ret;
+
+	ret = clk_enable_bulk(&priv->clks);
+	if (ret) {
+		clk_release_bulk(&priv->clks);
+		return ret;
+	}
+#endif
+
+	return 0;
+}
+
+static int cdns3_generic_handle_interrupts(struct udevice *dev)
+{
+	struct cdns3_generic_peripheral *priv = dev_get_priv(dev);
+	struct cdns3 *cdns3 = &priv->cdns3;
+
+	cdns3_role_irq_handler(cdns3);
+
+	return 0;
+}
+
+static int cdns3_generic_peripheral_probe(struct udevice *dev)
+{
+	int ret;
+	struct cdns3_generic_peripheral *priv = dev_get_priv(dev);
+	struct cdns3 *cdns3 = &priv->cdns3;
+
+	cdns3->dev = dev;
+
+	ret = generic_phy_get_by_index(dev, 0, &priv->phy);
+	if (ret && ret != -ENOENT) {
+		printf("Failed to get USB PHY for %s\n", dev->name);
+		return ret;
+	}
+
+	ret = cdns3_generic_peripheral_clk_init(dev, priv);
+	if (ret)
+		return ret;
+
+	ret = cdns3_init(cdns3);
+
+	return 0;
+}
+
+static int cdns3_generic_peripheral_remove(struct udevice *dev)
+{
+	struct cdns3_generic_peripheral *priv = dev_get_priv(dev);
+	struct cdns3 *cdns3 = &priv->cdns3;
+
+	cdns3_exit(cdns3);
+
+	clk_release_bulk(&priv->clks);
+
+	if (generic_phy_valid(&priv->phy))
+		device_remove(priv->phy.dev, DM_REMOVE_NORMAL);
+
+	return 0;
+}
+
+static int cdns3_generic_peripheral_ofdata_to_platdata(struct udevice *dev)
+{
+	struct cdns3_generic_peripheral *priv = dev_get_priv(dev);
+	struct cdns3 *cdns3 = &priv->cdns3;
+
+	cdns3->none_core_regs = (void __iomem *)devfdt_get_addr_name(dev,
+								     "none-core");
+	cdns3->xhci_regs = (void __iomem *)devfdt_get_addr_name(dev, "xhci");
+	cdns3->dev_regs = (void __iomem *)devfdt_get_addr_name(dev, "dev");
+	cdns3->phy_regs = (void __iomem *)devfdt_get_addr_name(dev, "phy");
+	cdns3->otg_regs = (void __iomem *)devfdt_get_addr_name(dev, "otg");
+
+	return 0;
+}
+
+static const struct udevice_id cdns3_generic_peripheral_ids[] = {
+	{ .compatible = "Cadence,usb3" },
+	{},
+};
+
+U_BOOT_DRIVER(cdns3_generic_peripheral) = {
+	.name	= "cdns3-generic-peripheral",
+	.id	= UCLASS_USB_GADGET_GENERIC,
+	.of_match = cdns3_generic_peripheral_ids,
+	.of_to_plat = cdns3_generic_peripheral_ofdata_to_platdata,
+	.probe = cdns3_generic_peripheral_probe,
+	.remove = cdns3_generic_peripheral_remove,
+	.handle_interrupts = cdns3_generic_handle_interrupts,
+	.priv_auto = sizeof(struct cdns3_generic_peripheral),
+};
diff --git a/drivers/usb/cdns3/cdns3-nxp-reg-def.h b/drivers/usb/cdns3/cdns3-nxp-reg-def.h
new file mode 100644
index 00000000000..4819957be4e
--- /dev/null
+++ b/drivers/usb/cdns3/cdns3-nxp-reg-def.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __DRIVERS_USB_CDNS3_NXP_H
+#define __DRIVERS_USB_CDNS3_NXP_H
+
+#define USB3_CORE_CTRL1    0x00
+#define USB3_CORE_CTRL2    0x04
+#define USB3_INT_REG       0x08
+#define USB3_CORE_STATUS   0x0c
+#define XHCI_DEBUG_LINK_ST 0x10
+#define XHCI_DEBUG_BUS     0x14
+#define USB3_SSPHY_CTRL1   0x40
+#define USB3_SSPHY_CTRL2   0x44
+#define USB3_SSPHY_STATUS  0x4c
+#define USB2_PHY_CTRL1     0x50
+#define USB2_PHY_CTRL2     0x54
+#define USB2_PHY_STATUS    0x5c
+
+/* Register bits definition */
+
+/* USB3_CORE_CTRL1 */
+#define SW_RESET_MASK	(0x3f << 26)
+#define PWR_SW_RESET	BIT(31)
+#define APB_SW_RESET	BIT(30)
+#define AXI_SW_RESET	BIT(29)
+#define RW_SW_RESET	BIT(28)
+#define PHY_SW_RESET	BIT(27)
+#define PHYAHB_SW_RESET	BIT(26)
+#define ALL_SW_RESET	(PWR_SW_RESET | APB_SW_RESET | AXI_SW_RESET | \
+		RW_SW_RESET | PHY_SW_RESET | PHYAHB_SW_RESET)
+#define OC_DISABLE	BIT(9)
+#define MDCTRL_CLK_SEL	BIT(7)
+#define MODE_STRAP_MASK	(0x7)
+#define DEV_MODE	BIT(2)
+#define HOST_MODE	BIT(1)
+#define OTG_MODE	BIT(0)
+
+/* USB3_INT_REG */
+#define CLK_125_REQ	BIT(29)
+#define LPM_CLK_REQ	BIT(28)
+#define DEVU3_WAEKUP_EN	BIT(14)
+#define OTG_WAKEUP_EN	BIT(12)
+#define DEV_INT_EN (3 << 8) /* DEV INT b9:8 */
+#define HOST_INT1_EN BIT(0) /* HOST INT b7:0 */
+
+/* USB3_CORE_STATUS */
+#define MDCTRL_CLK_STATUS	BIT(15)
+#define DEV_POWER_ON_READY	BIT(13)
+#define HOST_POWER_ON_READY	BIT(12)
+
+/* USB3_SSPHY_STATUS */
+#define PHY_REFCLK_REQ		BIT(0)
+#define CLK_VLD	0xf0000000
+
+/* PHY register definition */
+#define TB_ADDR_TX_RCVDETSC_CTRL	        (0x4124 * 4)
+#define CDNS3_USB2_PHY_BASE			(0x38000)
+#define USB2_PHY_AFE_BC_REG4			(CDNS3_USB2_PHY_BASE + 0x29 * 4)
+
+/* USB2_PHY_AFE_BC_REG4 */
+#define SET_FORCE_B_SESS_VALID			0x60
+
+/* TB_ADDR_TX_RCVDETSC_CTRL */
+#define RXDET_IN_P3_32KHZ			BIT(0)
+
+/* OTG registers definition */
+#define OTGSTS		0x4
+#define OTGREFCLK	0xc
+
+/* Register bits definition */
+/* OTGSTS */
+#define OTG_NRDY	BIT(11)
+/* OTGREFCLK */
+#define OTG_STB_CLK_SWITCH_EN	BIT(31)
+
+/* xHCI registers definition  */
+#define XECP_PORT_CAP_REG	0x8000
+#define XECP_PM_PMCSR		0x8018
+#define XECP_AUX_CTRL_REG1	0x8120
+
+/* Register bits definition */
+/* XECP_PORT_CAP_REG */
+#define LPM_2_STB_SWITCH_EN	BIT(25)
+
+/* XECP_AUX_CTRL_REG1 */
+#define CFG_RXDET_P3_EN		BIT(15)
+
+/* XECP_PM_PMCSR */
+#define PS_D0			BIT(0)
+#endif /* __DRIVERS_USB_CDNS3_NXP_H */
diff --git a/drivers/usb/cdns3/cdns3-ti.c b/drivers/usb/cdns3/cdns3-ti.c
deleted file mode 100644
index 8958f0166bd..00000000000
--- a/drivers/usb/cdns3/cdns3-ti.c
+++ /dev/null
@@ -1,196 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/**
- * cdns_ti-ti.c - TI specific Glue layer for Cadence USB Controller
- *
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
- */
-
-#include <common.h>
-#include <asm-generic/io.h>
-#include <clk.h>
-#include <dm.h>
-#include <dm/device_compat.h>
-#include <linux/bitops.h>
-#include <linux/io.h>
-#include <linux/usb/otg.h>
-#include <malloc.h>
-
-#include "core.h"
-
-/* USB Wrapper register offsets */
-#define USBSS_PID		0x0
-#define	USBSS_W1		0x4
-#define USBSS_STATIC_CONFIG	0x8
-#define USBSS_PHY_TEST		0xc
-#define	USBSS_DEBUG_CTRL	0x10
-#define	USBSS_DEBUG_INFO	0x14
-#define	USBSS_DEBUG_LINK_STATE	0x18
-#define	USBSS_DEVICE_CTRL	0x1c
-
-/* Wrapper 1 register bits */
-#define USBSS_W1_PWRUP_RST		BIT(0)
-#define USBSS_W1_OVERCURRENT_SEL	BIT(8)
-#define USBSS_W1_MODESTRAP_SEL		BIT(9)
-#define USBSS_W1_OVERCURRENT		BIT(16)
-#define USBSS_W1_MODESTRAP_MASK		GENMASK(18, 17)
-#define USBSS_W1_MODESTRAP_SHIFT	17
-#define USBSS_W1_USB2_ONLY		BIT(19)
-
-/* Static config register bits */
-#define USBSS1_STATIC_PLL_REF_SEL_MASK	GENMASK(8, 5)
-#define USBSS1_STATIC_PLL_REF_SEL_SHIFT	5
-#define USBSS1_STATIC_LOOPBACK_MODE_MASK	GENMASK(4, 3)
-#define USBSS1_STATIC_LOOPBACK_MODE_SHIFT	3
-#define USBSS1_STATIC_VBUS_SEL_MASK	GENMASK(2, 1)
-#define USBSS1_STATIC_VBUS_SEL_SHIFT	1
-#define USBSS1_STATIC_LANE_REVERSE	BIT(0)
-
-/* Modestrap modes */
-enum modestrap_mode { USBSS_MODESTRAP_MODE_NONE,
-		      USBSS_MODESTRAP_MODE_HOST,
-		      USBSS_MODESTRAP_MODE_PERIPHERAL};
-
-struct cdns_ti {
-	struct udevice *dev;
-	void __iomem *usbss;
-	int usb2_only:1;
-	int vbus_divider:1;
-	struct clk *usb2_refclk;
-	struct clk *lpm_clk;
-};
-
-static const int cdns_ti_rate_table[] = {	/* in KHZ */
-	9600,
-	10000,
-	12000,
-	19200,
-	20000,
-	24000,
-	25000,
-	26000,
-	38400,
-	40000,
-	58000,
-	50000,
-	52000,
-};
-
-static inline u32 cdns_ti_readl(struct cdns_ti *data, u32 offset)
-{
-	return readl(data->usbss + offset);
-}
-
-static inline void cdns_ti_writel(struct cdns_ti *data, u32 offset, u32 value)
-{
-	writel(value, data->usbss + offset);
-}
-
-static int cdns_ti_probe(struct udevice *dev)
-{
-	struct cdns_ti *data = dev_get_plat(dev);
-	struct clk usb2_refclk;
-	int modestrap_mode;
-	unsigned long rate;
-	int rate_code, i;
-	u32 reg;
-	int ret;
-
-	data->dev = dev;
-
-	data->usbss = dev_remap_addr_index(dev, 0);
-	if (!data->usbss)
-		return -EINVAL;
-
-	ret = clk_get_by_name(dev, "ref", &usb2_refclk);
-	if (ret) {
-		dev_err(dev, "Failed to get usb2_refclk\n");
-		return ret;
-	}
-
-	rate = clk_get_rate(&usb2_refclk);
-	rate /= 1000;	/* To KHz */
-	for (i = 0; i < ARRAY_SIZE(cdns_ti_rate_table); i++) {
-		if (cdns_ti_rate_table[i] == rate)
-			break;
-	}
-
-	if (i == ARRAY_SIZE(cdns_ti_rate_table)) {
-		dev_err(dev, "unsupported usb2_refclk rate: %lu KHz\n", rate);
-		return -EINVAL;
-	}
-
-	rate_code = i;
-
-	/* assert RESET */
-	reg = cdns_ti_readl(data, USBSS_W1);
-	reg &= ~USBSS_W1_PWRUP_RST;
-	cdns_ti_writel(data, USBSS_W1, reg);
-
-	/* set static config */
-	reg = cdns_ti_readl(data, USBSS_STATIC_CONFIG);
-	reg &= ~USBSS1_STATIC_PLL_REF_SEL_MASK;
-	reg |= rate_code << USBSS1_STATIC_PLL_REF_SEL_SHIFT;
-
-	reg &= ~USBSS1_STATIC_VBUS_SEL_MASK;
-	data->vbus_divider = dev_read_bool(dev, "ti,vbus-divider");
-	if (data->vbus_divider)
-		reg |= 1 << USBSS1_STATIC_VBUS_SEL_SHIFT;
-
-	cdns_ti_writel(data, USBSS_STATIC_CONFIG, reg);
-	reg = cdns_ti_readl(data, USBSS_STATIC_CONFIG);
-
-	/* set USB2_ONLY mode if requested */
-	reg = cdns_ti_readl(data, USBSS_W1);
-	data->usb2_only = dev_read_bool(dev, "ti,usb2-only");
-	if (data->usb2_only)
-		reg |= USBSS_W1_USB2_ONLY;
-
-	/* set modestrap  */
-	if (dev_read_bool(dev, "ti,modestrap-host"))
-		modestrap_mode = USBSS_MODESTRAP_MODE_HOST;
-	else if (dev_read_bool(dev, "ti,modestrap-peripheral"))
-		modestrap_mode = USBSS_MODESTRAP_MODE_PERIPHERAL;
-	else
-		modestrap_mode = USBSS_MODESTRAP_MODE_NONE;
-
-	reg |= USBSS_W1_MODESTRAP_SEL;
-	reg &= ~USBSS_W1_MODESTRAP_MASK;
-	reg |= modestrap_mode << USBSS_W1_MODESTRAP_SHIFT;
-	cdns_ti_writel(data, USBSS_W1, reg);
-
-	/* de-assert RESET */
-	reg |= USBSS_W1_PWRUP_RST;
-	cdns_ti_writel(data, USBSS_W1, reg);
-
-	return 0;
-}
-
-static int cdns_ti_remove(struct udevice *dev)
-{
-	struct cdns_ti *data = dev_get_plat(dev);
-	u32 reg;
-
-	/* put device back to RESET*/
-	reg = cdns_ti_readl(data, USBSS_W1);
-	reg &= ~USBSS_W1_PWRUP_RST;
-	cdns_ti_writel(data, USBSS_W1, reg);
-
-	return 0;
-}
-
-static const struct udevice_id cdns_ti_of_match[] = {
-	{ .compatible = "ti,j721e-usb", },
-	{ .compatible = "ti,am64-usb", },
-	{},
-};
-
-U_BOOT_DRIVER(cdns_ti) = {
-	.name = "cdns-ti",
-	.id = UCLASS_NOP,
-	.of_match = cdns_ti_of_match,
-	.bind = cdns3_bind,
-	.probe = cdns_ti_probe,
-	.remove = cdns_ti_remove,
-	.plat_auto	= sizeof(struct cdns_ti),
-	.flags = DM_FLAG_OS_PREPARE,
-};
diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c
index 644a9791b9c..377e0bd4f31 100644
--- a/drivers/usb/cdns3/core.c
+++ b/drivers/usb/cdns3/core.c
@@ -1,499 +1,205 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * Cadence USBSS DRD Driver.
- *
- * Copyright (C) 2018-2019 Cadence.
- * Copyright (C) 2017-2018 NXP
- * Copyright (C) 2019 Texas Instruments
- *
- * Author: Peter Chen <peter.chen@nxp.com>
- *         Pawel Laszczak <pawell@cadence.com>
- *         Roger Quadros <rogerq@ti.com>
+ * Copyright (C) 2016 Cadence Design Systems - https://www.cadence.com/
+ * Copyright 2019 NXP
  */
-
 #include <common.h>
+#include <malloc.h>
+#include <wait_bit.h>
+#include <asm/dma-mapping.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/list.h>
+#include <linux/compat.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/otg.h>
 #include <dm.h>
-#include <log.h>
-#include <dm/device-internal.h>
 #include <dm/device_compat.h>
-#include <dm/devres.h>
-#include <dm/lists.h>
-#include <linux/bug.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <usb.h>
-#include <usb/xhci.h>
 
+#include "cdns3-nxp-reg-def.h"
 #include "core.h"
-#include "host-export.h"
 #include "gadget-export.h"
-#include "drd.h"
-
-static int cdns3_idle_init(struct cdns3 *cdns);
-
-struct cdns3_host_priv {
-	struct xhci_ctrl xhci_ctrl;
-	struct cdns3 cdns;
-};
-
-struct cdns3_gadget_priv {
-	struct cdns3 cdns;
-};
+#include "gadget.h"
 
-static inline
-struct cdns3_role_driver *cdns3_get_current_role_driver(struct cdns3 *cdns)
+static void cdns3_reset_core(struct cdns3 *cdns)
 {
-	WARN_ON(!cdns->roles[cdns->role]);
-	return cdns->roles[cdns->role];
+	/* Set all Reset bits */
+	setbits_le32(cdns->none_core_regs + USB3_CORE_CTRL1, ALL_SW_RESET);
+	udelay(1);
 }
 
-static int cdns3_role_start(struct cdns3 *cdns, enum usb_role role)
+static int cdns3_host_role_set(struct cdns3 *cdns)
 {
 	int ret;
 
-	if (WARN_ON(role > USB_ROLE_DEVICE))
-		return 0;
-
-	mutex_lock(&cdns->mutex);
-	cdns->role = role;
-	mutex_unlock(&cdns->mutex);
-
-	if (!cdns->roles[role])
-		return -ENXIO;
-
-	if (cdns->roles[role]->state == CDNS3_ROLE_STATE_ACTIVE)
-		return 0;
-
-	mutex_lock(&cdns->mutex);
-	ret = cdns->roles[role]->start(cdns);
-	if (!ret)
-		cdns->roles[role]->state = CDNS3_ROLE_STATE_ACTIVE;
-	mutex_unlock(&cdns->mutex);
+	struct cdns3_generic_peripheral *priv = container_of(cdns,
+			struct cdns3_generic_peripheral, cdns3);
+
+	clrsetbits_le32(cdns->none_core_regs + USB3_CORE_CTRL1,
+			MODE_STRAP_MASK, HOST_MODE | OC_DISABLE);
+	clrbits_le32(cdns->none_core_regs + USB3_CORE_CTRL1,
+		     PHYAHB_SW_RESET);
+	mdelay(1);
+	generic_phy_init(&priv->phy);
+	setbits_le32(cdns->phy_regs + TB_ADDR_TX_RCVDETSC_CTRL,
+		     RXDET_IN_P3_32KHZ);
+	udelay(10);
+	/* Force B Session Valid as 1 */
+	writel(SET_FORCE_B_SESS_VALID, cdns->phy_regs + USB2_PHY_AFE_BC_REG4);
+	mdelay(1);
+
+	setbits_le32(cdns->none_core_regs + USB3_INT_REG, HOST_INT1_EN);
+
+	clrbits_le32(cdns->none_core_regs + USB3_CORE_CTRL1,
+		     ALL_SW_RESET);
+
+	dev_dbg(cdns->dev, "wait xhci_power_on_ready\n");
+	ret = wait_for_bit_le32(cdns->none_core_regs + USB3_CORE_STATUS,
+				HOST_POWER_ON_READY, true, 100, false);
+	if (ret) {
+		dev_err(cdns->dev, "wait xhci_power_on_ready timeout\n");
+		return ret;
+	}
 
-	return ret;
+	return 0;
 }
 
-static void cdns3_role_stop(struct cdns3 *cdns)
+static int cdns3_gadget_role_set(struct cdns3 *cdns)
 {
-	enum usb_role role = cdns->role;
-
-	if (WARN_ON(role > USB_ROLE_DEVICE))
-		return;
-
-	if (cdns->roles[role]->state == CDNS3_ROLE_STATE_INACTIVE)
-		return;
+	int ret;
 
-	mutex_lock(&cdns->mutex);
-	cdns->roles[role]->stop(cdns);
-	cdns->roles[role]->state = CDNS3_ROLE_STATE_INACTIVE;
-	mutex_unlock(&cdns->mutex);
-}
+	struct cdns3_generic_peripheral *priv = container_of(cdns,
+			struct cdns3_generic_peripheral, cdns3);
 
-static void cdns3_exit_roles(struct cdns3 *cdns)
-{
-	cdns3_role_stop(cdns);
-	cdns3_drd_exit(cdns);
-}
+	clrsetbits_le32(cdns->none_core_regs + USB3_CORE_CTRL1,
+			MODE_STRAP_MASK, DEV_MODE);
+	clrbits_le32(cdns->none_core_regs + USB3_CORE_CTRL1,
+		     PHYAHB_SW_RESET);
 
-static enum usb_role cdsn3_hw_role_state_machine(struct cdns3 *cdns);
+	generic_phy_init(&priv->phy);
+	setbits_le32(cdns->phy_regs + TB_ADDR_TX_RCVDETSC_CTRL,
+		     RXDET_IN_P3_32KHZ);
+	udelay(10);
+	/* Force B Session Valid as 1 */
+	writel(SET_FORCE_B_SESS_VALID, cdns->phy_regs + USB2_PHY_AFE_BC_REG4);
+	setbits_le32(cdns->none_core_regs + USB3_INT_REG, DEV_INT_EN);
 
-/**
- * cdns3_core_init_role - initialize role of operation
- * @cdns: Pointer to cdns3 structure
- *
- * Returns 0 on success otherwise negative errno
- */
-static int cdns3_core_init_role(struct cdns3 *cdns)
-{
-	struct udevice *dev = cdns->dev;
-	enum usb_dr_mode best_dr_mode;
-	enum usb_dr_mode dr_mode;
-	int ret = 0;
-
-	dr_mode = usb_get_dr_mode(dev_ofnode(dev));
-	cdns->role = USB_ROLE_NONE;
-
-	/*
-	 * If driver can't read mode by means of usb_get_dr_mode function then
-	 * chooses mode according with Kernel configuration. This setting
-	 * can be restricted later depending on strap pin configuration.
-	 */
-	if (dr_mode == USB_DR_MODE_UNKNOWN) {
-		if (IS_ENABLED(CONFIG_USB_CDNS3_HOST) &&
-		    IS_ENABLED(CONFIG_USB_CDNS3_GADGET))
-			dr_mode = USB_DR_MODE_OTG;
-		else if (IS_ENABLED(CONFIG_USB_CDNS3_HOST))
-			dr_mode = USB_DR_MODE_HOST;
-		else if (IS_ENABLED(CONFIG_USB_CDNS3_GADGET))
-			dr_mode = USB_DR_MODE_PERIPHERAL;
-	}
+	clrbits_le32(cdns->none_core_regs + USB3_CORE_CTRL1,
+		     ALL_SW_RESET);
 
-	/*
-	 * At this point cdns->dr_mode contains strap configuration.
-	 * Driver try update this setting considering kernel configuration
-	 */
-	best_dr_mode = cdns->dr_mode;
-
-	ret = cdns3_idle_init(cdns);
-	if (ret)
+	dev_dbg(cdns->dev, "wait gadget_power_on_ready\n");
+	ret = wait_for_bit_le32(cdns->none_core_regs + USB3_CORE_STATUS,
+				DEV_POWER_ON_READY, true, 100, false);
+	if (ret) {
+		dev_err(cdns->dev, "wait gadget_power_on_ready timeout\n");
 		return ret;
-
-	if (dr_mode == USB_DR_MODE_OTG) {
-		best_dr_mode = cdns->dr_mode;
-	} else if (cdns->dr_mode == USB_DR_MODE_OTG) {
-		best_dr_mode = dr_mode;
-	} else if (cdns->dr_mode != dr_mode) {
-		dev_err(dev, "Incorrect DRD configuration\n");
-		return -EINVAL;
-	}
-
-	dr_mode = best_dr_mode;
-
-#if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_SPL_BUILD)
-	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
-		ret = cdns3_host_init(cdns);
-		if (ret) {
-			dev_err(dev, "Host initialization failed with %d\n",
-				ret);
-			goto err;
-		}
-	}
-#endif
-
-#if CONFIG_IS_ENABLED(DM_USB_GADGET)
-	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
-		ret = cdns3_gadget_init(cdns);
-		if (ret) {
-			dev_err(dev, "Device initialization failed with %d\n",
-				ret);
-			goto err;
-		}
 	}
-#endif
 
-	cdns->dr_mode = dr_mode;
-
-	ret = cdns3_drd_update_mode(cdns);
-	if (ret)
-		goto err;
-
-	if (cdns->dr_mode != USB_DR_MODE_OTG) {
-		ret = cdns3_hw_role_switch(cdns);
-		if (ret)
-			goto err;
-	}
-
-	return ret;
-err:
-	cdns3_exit_roles(cdns);
-	return ret;
+	return 0;
 }
 
-/**
- * cdsn3_hw_role_state_machine - role switch state machine based on hw events
- * @cdns: Pointer to controller structure.
- *
- * Returns next role to be entered based on hw events.
- */
-static enum usb_role cdsn3_hw_role_state_machine(struct cdns3 *cdns)
+static int cdns3_set_role(struct cdns3 *cdns, enum cdns3_roles role)
 {
-	enum usb_role role;
-	int id, vbus;
-
-	if (cdns->dr_mode != USB_DR_MODE_OTG)
-		goto not_otg;
-
-	id = cdns3_get_id(cdns);
-	vbus = cdns3_get_vbus(cdns);
-
-	/*
-	 * Role change state machine
-	 * Inputs: ID, VBUS
-	 * Previous state: cdns->role
-	 * Next state: role
-	 */
-	role = cdns->role;
-
-	switch (role) {
-	case USB_ROLE_NONE:
-		/*
-		 * Driver treats USB_ROLE_NONE synonymous to IDLE state from
-		 * controller specification.
-		 */
-		if (!id)
-			role = USB_ROLE_HOST;
-		else if (vbus)
-			role = USB_ROLE_DEVICE;
-		break;
-	case USB_ROLE_HOST: /* from HOST, we can only change to NONE */
-		if (id)
-			role = USB_ROLE_NONE;
-		break;
-	case USB_ROLE_DEVICE: /* from GADGET, we can only change to NONE*/
-		if (!vbus)
-			role = USB_ROLE_NONE;
-		break;
-	}
+	int ret;
 
-	dev_dbg(cdns->dev, "role %d -> %d\n", cdns->role, role);
+	if (role == CDNS3_ROLE_END)
+		return -EPERM;
 
-	return role;
+	/* Wait clk value */
+	writel(CLK_VLD, cdns->none_core_regs + USB3_SSPHY_STATUS);
+	ret = wait_for_bit_le32(cdns->none_core_regs + USB3_SSPHY_STATUS,
+				CLK_VLD, true, 100, false);
+	if (ret) {
+		dev_err(cdns->dev, "wait clkvld timeout\n");
+		return ret;
+	}
 
-not_otg:
-	if (cdns3_is_host(cdns))
-		role = USB_ROLE_HOST;
-	if (cdns3_is_device(cdns))
-		role = USB_ROLE_DEVICE;
+	cdns3_reset_core(cdns);
 
-	return role;
-}
+	if (role == CDNS3_ROLE_HOST) {
+		cdns3_host_role_set(cdns);
+		dev_dbg(cdns->dev, "switch to host role successfully\n");
+	} else { /* gadget mode */
+		cdns3_gadget_role_set(cdns);
+		dev_dbg(cdns->dev, "switch to gadget role successfully\n");
+	}
 
-static int cdns3_idle_role_start(struct cdns3 *cdns)
-{
 	return 0;
 }
 
-static void cdns3_idle_role_stop(struct cdns3 *cdns)
+static enum cdns3_roles cdns3_get_role(struct cdns3 *cdns)
 {
-	/* Program Lane swap and bring PHY out of RESET */
-	generic_phy_reset(&cdns->usb3_phy);
-}
-
-static int cdns3_idle_init(struct cdns3 *cdns)
-{
-	struct cdns3_role_driver *rdrv;
-
-	rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL);
-	if (!rdrv)
-		return -ENOMEM;
-
-	rdrv->start = cdns3_idle_role_start;
-	rdrv->stop = cdns3_idle_role_stop;
-	rdrv->state = CDNS3_ROLE_STATE_INACTIVE;
-	rdrv->suspend = NULL;
-	rdrv->resume = NULL;
-	rdrv->name = "idle";
-
-	cdns->roles[USB_ROLE_NONE] = rdrv;
-
-	return 0;
+	return cdns->roles[CDNS3_ROLE_HOST]
+		? CDNS3_ROLE_HOST
+		: CDNS3_ROLE_GADGET;
 }
 
 /**
- * cdns3_hw_role_switch - switch roles based on HW state
- * @cdns3: controller
+ * cdns3_core_init_role - initialize role of operation
+ * @cdns: Pointer to cdns3 structure
+ * @dr_mode: Role mode of device
+ *
+ * Returns 0 on success otherwise negative errno
  */
-int cdns3_hw_role_switch(struct cdns3 *cdns)
+static int cdns3_core_init_role(struct cdns3 *cdns, enum usb_dr_mode dr_mode)
 {
-	enum usb_role real_role, current_role;
-	int ret = 0;
-
-	/* Do nothing if role based on syfs. */
-	if (cdns->role_override)
-		return 0;
-
-	current_role = cdns->role;
-	real_role = cdsn3_hw_role_state_machine(cdns);
-
-	/* Do nothing if nothing changed */
-	if (current_role == real_role)
-		goto exit;
+	cdns->role = CDNS3_ROLE_END;
+	if (dr_mode == USB_DR_MODE_UNKNOWN)
+		dr_mode = USB_DR_MODE_OTG;
 
-	cdns3_role_stop(cdns);
-
-	dev_dbg(cdns->dev, "Switching role %d -> %d", current_role, real_role);
-
-	ret = cdns3_role_start(cdns, real_role);
-	if (ret) {
-		/* Back to current role */
-		dev_err(cdns->dev, "set %d has failed, back to %d\n",
-			real_role, current_role);
-		ret = cdns3_role_start(cdns, current_role);
-		if (ret)
-			dev_err(cdns->dev, "back to %d failed too\n",
-				current_role);
+	/* Currently, only support gadget mode */
+	if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
+		dev_err(cdns->dev, "doesn't support host and OTG, only for gadget\n");
+		return -EPERM;
 	}
-exit:
-	return ret;
-}
-
-static int cdns3_probe(struct cdns3 *cdns)
-{
-	struct udevice *dev = cdns->dev;
-	int ret;
-
-	cdns->xhci_regs = dev_remap_addr_name(dev, "xhci");
-	if (!cdns->xhci_regs)
-		return -EINVAL;
-
-	cdns->dev_regs = dev_remap_addr_name(dev, "dev");
-	if (!cdns->dev_regs)
-		return -EINVAL;
-
-	mutex_init(&cdns->mutex);
-
-	ret = generic_phy_get_by_name(dev, "cdns3,usb2-phy", &cdns->usb2_phy);
-	if (ret)
-		dev_warn(dev, "Unable to get USB2 phy (ret %d)\n", ret);
-
-	ret = generic_phy_init(&cdns->usb2_phy);
-	if (ret)
-		return ret;
-
-	ret = generic_phy_get_by_name(dev, "cdns3,usb3-phy", &cdns->usb3_phy);
-	if (ret)
-		dev_warn(dev, "Unable to get USB3 phy (ret %d)\n", ret);
-
-	ret = generic_phy_init(&cdns->usb3_phy);
-	if (ret)
-		return ret;
 
-	ret = generic_phy_power_on(&cdns->usb2_phy);
-	if (ret)
-		return ret;
-
-	ret = generic_phy_power_on(&cdns->usb3_phy);
-	if (ret)
-		return ret;
-
-	ret = cdns3_drd_init(cdns);
-	if (ret)
-		return ret;
-
-	ret = cdns3_core_init_role(cdns);
-	if (ret)
-		return ret;
+	if (dr_mode == USB_DR_MODE_PERIPHERAL) {
+		if (cdns3_gadget_init(cdns))
+			dev_info(cdns->dev, "doesn't support gadget\n");
+	}
 
-	dev_dbg(dev, "Cadence USB3 core: probe succeed\n");
+	if (!cdns->roles[CDNS3_ROLE_HOST] && !cdns->roles[CDNS3_ROLE_GADGET]) {
+		dev_err(cdns->dev, "no supported roles\n");
+		return -ENODEV;
+	}
 
 	return 0;
 }
 
-static int cdns3_remove(struct cdns3 *cdns)
+static void cdns3_remove_roles(struct cdns3 *cdns)
 {
-	cdns3_exit_roles(cdns);
-	generic_phy_power_off(&cdns->usb2_phy);
-	generic_phy_power_off(&cdns->usb3_phy);
-	generic_phy_exit(&cdns->usb2_phy);
-	generic_phy_exit(&cdns->usb3_phy);
-	return 0;
+	/* Only support gadget */
+	cdns3_gadget_remove(cdns);
 }
 
-static const struct udevice_id cdns3_ids[] = {
-	{ .compatible = "cdns,usb3" },
-	{ },
-};
-
-int cdns3_bind(struct udevice *parent)
+int cdns3_init(struct cdns3 *cdns)
 {
-	enum usb_dr_mode dr_mode;
-	struct udevice *dev;
-	const char *driver;
-	const char *name;
-	ofnode node;
 	int ret;
 
-	node = ofnode_by_compatible(dev_ofnode(parent), "cdns,usb3");
-	if (!ofnode_valid(node)) {
-		ret = -ENODEV;
-		goto fail;
-	}
+	ret = cdns3_core_init_role(cdns, USB_DR_MODE_PERIPHERAL);
 
-	name = ofnode_get_name(node);
-	dr_mode = usb_get_dr_mode(node);
-
-	switch (dr_mode) {
-#if defined(CONFIG_SPL_USB_HOST) || \
-	(!defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST))
-	case USB_DR_MODE_HOST:
-		debug("%s: dr_mode: HOST\n", __func__);
-		driver = "cdns-usb3-host";
-		break;
-#endif
-#if CONFIG_IS_ENABLED(DM_USB_GADGET)
-	case USB_DR_MODE_PERIPHERAL:
-		debug("%s: dr_mode: PERIPHERAL\n", __func__);
-		driver = "cdns-usb3-peripheral";
-		break;
-#endif
-	default:
-		printf("%s: unsupported dr_mode\n", __func__);
-		ret = -ENODEV;
-		goto fail;
-	};
-
-	ret = device_bind_driver_to_node(parent, driver, name, node, &dev);
+	cdns->role = cdns3_get_role(cdns);
+	dev_dbg(cdns->dev, "the init role is %d\n", cdns->role);
+	cdns3_set_role(cdns, cdns->role);
+	ret = cdns3_role_start(cdns, cdns->role);
 	if (ret) {
-		printf("%s: not able to bind usb device mode\n",
-		       __func__);
-		goto fail;
+		dev_err(cdns->dev, "can't start %s role\n", cdns3_role(cdns)->name);
+		goto err;
 	}
 
-	return 0;
+	dev_dbg(cdns->dev, "Cadence USB3 core: probe succeed\n");
 
-fail:
-	/* do not return an error: failing to bind would hang the board */
 	return 0;
-}
 
-#if CONFIG_IS_ENABLED(DM_USB_GADGET)
-static int cdns3_gadget_probe(struct udevice *dev)
-{
-	struct cdns3_gadget_priv *priv = dev_get_priv(dev);
-	struct cdns3 *cdns = &priv->cdns;
-
-	cdns->dev = dev;
-
-	return cdns3_probe(cdns);
-}
-
-static int cdns3_gadget_remove(struct udevice *dev)
-{
-	struct cdns3_gadget_priv *priv = dev_get_priv(dev);
-	struct cdns3 *cdns = &priv->cdns;
-
-	return cdns3_remove(cdns);
-}
-
-U_BOOT_DRIVER(cdns_usb3_peripheral) = {
-	.name	= "cdns-usb3-peripheral",
-	.id	= UCLASS_USB_GADGET_GENERIC,
-	.of_match = cdns3_ids,
-	.probe = cdns3_gadget_probe,
-	.remove = cdns3_gadget_remove,
-	.priv_auto	= sizeof(struct cdns3_gadget_priv),
-	.flags = DM_FLAG_ALLOC_PRIV_DMA,
-};
-#endif
-
-#if defined(CONFIG_SPL_USB_HOST) || \
-	(!defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST))
-static int cdns3_host_probe(struct udevice *dev)
-{
-	struct cdns3_host_priv *priv = dev_get_priv(dev);
-	struct cdns3 *cdns = &priv->cdns;
-
-	cdns->dev = dev;
+err:
+	cdns3_remove_roles(cdns);
 
-	return cdns3_probe(cdns);
+	return ret;
 }
 
-static int cdns3_host_remove(struct udevice *dev)
+void cdns3_exit(struct cdns3 *cdns)
 {
-	struct cdns3_host_priv *priv = dev_get_priv(dev);
-	struct cdns3 *cdns = &priv->cdns;
-
-	return cdns3_remove(cdns);
+	cdns3_role_stop(cdns);
+	cdns3_remove_roles(cdns);
+	cdns3_reset_core(cdns);
 }
-
-U_BOOT_DRIVER(cdns_usb3_host) = {
-	.name	= "cdns-usb3-host",
-	.id	= UCLASS_USB,
-	.of_match = cdns3_ids,
-	.probe = cdns3_host_probe,
-	.remove = cdns3_host_remove,
-	.priv_auto	= sizeof(struct cdns3_host_priv),
-	.ops = &xhci_usb_ops,
-	.flags = DM_FLAG_ALLOC_PRIV_DMA,
-};
-#endif
diff --git a/drivers/usb/cdns3/core.h b/drivers/usb/cdns3/core.h
index 0668d646fc4..d097678e52e 100644
--- a/drivers/usb/cdns3/core.h
+++ b/drivers/usb/cdns3/core.h
@@ -1,28 +1,17 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * Cadence USBSS DRD Header File.
- *
- * Copyright (C) 2017-2018 NXP
- * Copyright (C) 2018-2019 Cadence.
- *
- * Authors: Peter Chen <peter.chen@nxp.com>
- *          Pawel Laszczak <pawell@cadence.com>
+ * Copyright 2019 NXP
  */
-#include <linux/compiler.h>
-#include <linux/types.h>
-#include <linux/usb/otg.h>
-#include <generic-phy.h>
-
-#ifndef __LINUX_CDNS3_CORE_H
-#define __LINUX_CDNS3_CORE_H
-
-enum usb_role {
-	USB_ROLE_NONE,
-	USB_ROLE_HOST,
-	USB_ROLE_DEVICE,
-};
+
+#ifndef __DRIVERS_USB_CDNS3_CORE_H
+#define __DRIVERS_USB_CDNS3_CORE_H
 
 struct cdns3;
+enum cdns3_roles {
+	CDNS3_ROLE_HOST = 0,
+	CDNS3_ROLE_GADGET,
+	CDNS3_ROLE_END,
+};
 
 /**
  * struct cdns3_role_driver - host/gadget role driver
@@ -32,77 +21,98 @@ struct cdns3;
  * @resume: resume callback for this role
  * @irq: irq handler for this role
  * @name: role name string (host/gadget)
- * @state: current state
  */
 struct cdns3_role_driver {
 	int (*start)(struct cdns3 *cdns);
 	void (*stop)(struct cdns3 *cdns);
 	int (*suspend)(struct cdns3 *cdns, bool do_wakeup);
 	int (*resume)(struct cdns3 *cdns, bool hibernated);
+	int (*irq)(struct cdns3 *cdns);
 	const char *name;
-#define CDNS3_ROLE_STATE_INACTIVE	0
-#define CDNS3_ROLE_STATE_ACTIVE		1
-	int state;
 };
 
-#define CDNS3_XHCI_RESOURCES_NUM	2
+#define CDNS3_NUM_OF_CLKS	5
 /**
  * struct cdns3 - Representation of Cadence USB3 DRD controller.
  * @dev: pointer to Cadence device struct
  * @xhci_regs: pointer to base of xhci registers
+ * @xhci_res: the resource for xhci
  * @dev_regs: pointer to base of dev registers
- * @otg_v0_regs: pointer to base of v0 otg registers
- * @otg_v1_regs: pointer to base of v1 otg registers
+ * @none_core_regs: pointer to base of nxp wrapper registers
+ * @phy_regs: pointer to base of phy registers
  * @otg_regs: pointer to base of otg registers
- * @otg_irq: irq number for otg controller
- * @dev_irq: irq number for device controller
+ * @irq: irq number for controller
  * @roles: array of supported roles for this controller
  * @role: current role
  * @host_dev: the child host device pointer for cdns3 core
  * @gadget_dev: the child gadget device pointer for cdns3 core
- * @usb2_phy: pointer to USB2 PHY
- * @usb3_phy: pointer to USB3 PHY
- * @mutex: the mutex for concurrent code at driver
- * @dr_mode: supported mode of operation it can be only Host, only Device
- *           or OTG mode that allow to switch between Device and Host mode.
- *           This field based on firmware setting, kernel configuration
- *           and hardware configuration.
- * @role_sw: pointer to role switch object.
- * @role_override: set 1 if role rely on SW.
+ * @usbphy: usbphy for this controller
+ * @cdns3_clks: Clock pointer array for cdns3 core
+ * @extcon: Type-C extern connector
+ * @extcon_nb: notifier block for Type-C extern connector
+ * @role_switch_wq: work queue item for role switch
+ * @in_lpm: the controller in low power mode
+ * @wakeup_int: the wakeup interrupt
  */
 struct cdns3 {
-	struct udevice			*dev;
-	void __iomem			*xhci_regs;
-	struct cdns3_usb_regs __iomem	*dev_regs;
-
-	struct cdns3_otg_legacy_regs	*otg_v0_regs;
-	struct cdns3_otg_regs		*otg_v1_regs;
-	struct cdns3_otg_common_regs	*otg_regs;
-#define CDNS3_CONTROLLER_V0	0
-#define CDNS3_CONTROLLER_V1	1
-	u32				version;
-
-	int				otg_irq;
-	int				dev_irq;
-	struct cdns3_role_driver	*roles[USB_ROLE_DEVICE + 1];
-	enum usb_role			role;
-	struct cdns3_device		*gadget_dev;
-	struct phy			usb2_phy;
-	struct phy			usb3_phy;
-	/* mutext used in workqueue*/
-	struct mutex			mutex;
-	enum usb_dr_mode		dr_mode;
-	int				role_override;
+	struct udevice *dev;
+	void __iomem *xhci_regs;
+	struct resource *xhci_res;
+	struct usbss_dev_register_block_type __iomem *dev_regs;
+	void __iomem *none_core_regs;
+	void __iomem *phy_regs;
+	void __iomem *otg_regs;
+	int irq;
+	struct cdns3_role_driver *roles[CDNS3_ROLE_END];
+	enum cdns3_roles role;
+	struct udevice *host_dev;
+	struct udevice *gadget_dev;
+	struct clk *cdns3_clks[CDNS3_NUM_OF_CLKS];
+
+	int  index;
+	struct list_head list;
 };
 
-int cdns3_hw_role_switch(struct cdns3 *cdns);
+static inline struct cdns3_role_driver *cdns3_role(struct cdns3 *cdns)
+{
+	WARN_ON(cdns->role >= CDNS3_ROLE_END || !cdns->roles[cdns->role]);
+	return cdns->roles[cdns->role];
+}
 
-/**
- * cdns3_bind - generic bind function
- * @parent - pointer to parent udevice of which cdns3 USB controller
- *           node is child of
- *
- * return 0 on success, negative errno otherwise
- */
-int cdns3_bind(struct udevice *dev);
-#endif /* __LINUX_CDNS3_CORE_H */
+static inline int cdns3_role_start(struct cdns3 *cdns, enum cdns3_roles role)
+{
+	if (role >= CDNS3_ROLE_END)
+		return 0;
+
+	if (!cdns->roles[role])
+		return -ENXIO;
+
+	cdns->role = role;
+	return cdns->roles[role]->start(cdns);
+}
+
+static inline void cdns3_role_stop(struct cdns3 *cdns)
+{
+	enum cdns3_roles role = cdns->role;
+
+	if (role == CDNS3_ROLE_END)
+		return;
+
+	cdns->roles[role]->stop(cdns);
+	cdns->role = CDNS3_ROLE_END;
+}
+
+static inline void cdns3_role_irq_handler(struct cdns3 *cdns)
+{
+	enum cdns3_roles role = cdns->role;
+
+	if (role == CDNS3_ROLE_END)
+		return;
+
+	cdns->roles[role]->irq(cdns);
+}
+
+int cdns3_init(struct cdns3 *cdns);
+void cdns3_exit(struct cdns3 *cdns);
+
+#endif /* __DRIVERS_USB_CDNS3_CORE_H */
diff --git a/drivers/usb/cdns3/debug.h b/drivers/usb/cdns3/debug.h
deleted file mode 100644
index 0b4673a3a61..00000000000
--- a/drivers/usb/cdns3/debug.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Cadence USBSS DRD Driver.
- * Debug header file.
- *
- * Copyright (C) 2018-2019 Cadence.
- *
- * Author: Pawel Laszczak <pawell@cadence.com>
- */
-#ifndef __LINUX_CDNS3_DEBUG
-#define __LINUX_CDNS3_DEBUG
-
-#include "core.h"
-#include "gadget.h"
-
-static inline char *cdns3_decode_usb_irq(char *str,
-					 enum usb_device_speed speed,
-					 u32 usb_ists)
-{
-	int ret;
-
-	ret = sprintf(str, "IRQ %08x = ", usb_ists);
-
-	if (usb_ists & (USB_ISTS_CON2I | USB_ISTS_CONI)) {
-		ret += sprintf(str + ret, "Connection %s\n",
-			       usb_speed_string(speed));
-	}
-	if (usb_ists & USB_ISTS_DIS2I || usb_ists & USB_ISTS_DISI)
-		ret += sprintf(str + ret, "Disconnection ");
-	if (usb_ists & USB_ISTS_L2ENTI)
-		ret += sprintf(str + ret, "suspended ");
-	if (usb_ists & USB_ISTS_L1ENTI)
-		ret += sprintf(str + ret, "L1 enter ");
-	if (usb_ists & USB_ISTS_L1EXTI)
-		ret += sprintf(str + ret, "L1 exit ");
-	if (usb_ists & USB_ISTS_L2ENTI)
-		ret += sprintf(str + ret, "L2 enter ");
-	if (usb_ists & USB_ISTS_L2EXTI)
-		ret += sprintf(str + ret, "L2 exit ");
-	if (usb_ists & USB_ISTS_U3EXTI)
-		ret += sprintf(str + ret, "U3 exit ");
-	if (usb_ists & USB_ISTS_UWRESI)
-		ret += sprintf(str + ret, "Warm Reset ");
-	if (usb_ists & USB_ISTS_UHRESI)
-		ret += sprintf(str + ret, "Hot Reset ");
-	if (usb_ists & USB_ISTS_U2RESI)
-		ret += sprintf(str + ret, "Reset");
-
-	return str;
-}
-
-static inline  char *cdns3_decode_ep_irq(char *str,
-					 u32 ep_sts,
-					 const char *ep_name)
-{
-	int ret;
-
-	ret = sprintf(str, "IRQ for %s: %08x ", ep_name, ep_sts);
-
-	if (ep_sts & EP_STS_SETUP)
-		ret += sprintf(str + ret, "SETUP ");
-	if (ep_sts & EP_STS_IOC)
-		ret += sprintf(str + ret, "IOC ");
-	if (ep_sts & EP_STS_ISP)
-		ret += sprintf(str + ret, "ISP ");
-	if (ep_sts & EP_STS_DESCMIS)
-		ret += sprintf(str + ret, "DESCMIS ");
-	if (ep_sts & EP_STS_STREAMR)
-		ret += sprintf(str + ret, "STREAMR ");
-	if (ep_sts & EP_STS_MD_EXIT)
-		ret += sprintf(str + ret, "MD_EXIT ");
-	if (ep_sts & EP_STS_TRBERR)
-		ret += sprintf(str + ret, "TRBERR ");
-	if (ep_sts & EP_STS_NRDY)
-		ret += sprintf(str + ret, "NRDY ");
-	if (ep_sts & EP_STS_PRIME)
-		ret += sprintf(str + ret, "PRIME ");
-	if (ep_sts & EP_STS_SIDERR)
-		ret += sprintf(str + ret, "SIDERRT ");
-	if (ep_sts & EP_STS_OUTSMM)
-		ret += sprintf(str + ret, "OUTSMM ");
-	if (ep_sts & EP_STS_ISOERR)
-		ret += sprintf(str + ret, "ISOERR ");
-	if (ep_sts & EP_STS_IOT)
-		ret += sprintf(str + ret, "IOT ");
-
-	return str;
-}
-
-static inline char *cdns3_decode_epx_irq(char *str,
-					 char *ep_name,
-					 u32 ep_sts)
-{
-	return cdns3_decode_ep_irq(str, ep_sts, ep_name);
-}
-
-static inline char *cdns3_decode_ep0_irq(char *str,
-					 int dir,
-					 u32 ep_sts)
-{
-	return cdns3_decode_ep_irq(str, ep_sts,
-				   dir ? "ep0IN" : "ep0OUT");
-}
-
-/**
- * Debug a transfer ring.
- *
- * Prints out all TRBs in the endpoint ring, even those after the Link TRB.
- *.
- */
-static inline char *cdns3_dbg_ring(struct cdns3_endpoint *priv_ep,
-				   struct cdns3_trb *ring, char *str)
-{
-	dma_addr_t addr = priv_ep->trb_pool_dma;
-	struct cdns3_trb *trb;
-	int trb_per_sector;
-	int ret = 0;
-	int i;
-
-	trb_per_sector = GET_TRBS_PER_SEGMENT(priv_ep->type);
-
-	trb = &priv_ep->trb_pool[priv_ep->dequeue];
-	ret += sprintf(str + ret, "\n\t\tRing contents for %s:", priv_ep->name);
-
-	ret += sprintf(str + ret,
-		       "\n\t\tRing deq index: %d, trb: %p (virt), 0x%llx (dma)\n",
-		       priv_ep->dequeue, trb,
-		       (unsigned long long)cdns3_trb_virt_to_dma(priv_ep, trb));
-
-	trb = &priv_ep->trb_pool[priv_ep->enqueue];
-	ret += sprintf(str + ret,
-		       "\t\tRing enq index: %d, trb: %p (virt), 0x%llx (dma)\n",
-		       priv_ep->enqueue, trb,
-		       (unsigned long long)cdns3_trb_virt_to_dma(priv_ep, trb));
-
-	ret += sprintf(str + ret,
-		       "\t\tfree trbs: %d, CCS=%d, PCS=%d\n",
-		       priv_ep->free_trbs, priv_ep->ccs, priv_ep->pcs);
-
-	if (trb_per_sector > TRBS_PER_SEGMENT)
-		trb_per_sector = TRBS_PER_SEGMENT;
-
-	if (trb_per_sector > TRBS_PER_SEGMENT) {
-		sprintf(str + ret, "\t\tTo big transfer ring %d\n",
-			trb_per_sector);
-		return str;
-	}
-
-	for (i = 0; i < trb_per_sector; ++i) {
-		trb = &ring[i];
-		ret += sprintf(str + ret,
-			"\t\t@%pad %08x %08x %08x\n", &addr,
-			le32_to_cpu(trb->buffer),
-			le32_to_cpu(trb->length),
-			le32_to_cpu(trb->control));
-		addr += sizeof(*trb);
-	}
-
-	return str;
-}
-
-#endif /*__LINUX_CDNS3_DEBUG*/
diff --git a/drivers/usb/cdns3/dev-regs-macro.h b/drivers/usb/cdns3/dev-regs-macro.h
new file mode 100644
index 00000000000..e09d5c28ad1
--- /dev/null
+++ b/drivers/usb/cdns3/dev-regs-macro.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Cadence Design Systems - http://www.cadence.com
+ * Copyright 2019 NXP
+ */
+
+#ifndef __REG_USBSS_DEV_ADDR_MAP_MACRO_H__
+#define __REG_USBSS_DEV_ADDR_MAP_MACRO_H__
+
+/* macros for field CFGRST */
+#define USB_CONF__CFGRST__MASK                                      0x00000001U
+#define USB_CONF__CFGSET__MASK                                      0x00000002U
+#define USB_CONF__USB3DIS__MASK                                     0x00000008U
+#define USB_CONF__DEVEN__MASK                                       0x00004000U
+#define USB_CONF__DEVDS__MASK                                       0x00008000U
+#define USB_CONF__L1EN__MASK                                        0x00010000U
+#define USB_CONF__L1DS__MASK                                        0x00020000U
+#define USB_CONF__CLK2OFFDS__MASK                                   0x00080000U
+#define USB_CONF__U1EN__MASK                                        0x01000000U
+#define USB_CONF__U1DS__MASK                                        0x02000000U
+#define USB_CONF__U2EN__MASK                                        0x04000000U
+#define USB_CONF__U2DS__MASK                                        0x08000000U
+
+/* macros for field CFGSTS */
+#define USB_STS__CFGSTS__MASK                                       0x00000001U
+#define USB_STS__USBSPEED__READ(src)     (((u32)(src) & 0x00000070U) >> 4)
+
+/* macros for field ENDIAN_MIRROR */
+#define USB_STS__LPMST__READ(src)       (((u32)(src) & 0x000c0000U) >> 18)
+
+/* macros for field USB2CONS */
+#define USB_STS__U1ENS__MASK                                        0x01000000U
+#define USB_STS__U2ENS__MASK                                        0x02000000U
+#define USB_STS__LST__READ(src)         (((u32)(src) & 0x3c000000U) >> 26)
+
+/* macros for field SET_ADDR */
+#define USB_CMD__SET_ADDR__MASK                                     0x00000001U
+#define USB_CMD__STMODE						0x00000200U
+#define USB_CMD__TMODE_SEL(x)                                    (x << 10)
+#define USB_CMD__FADDR__WRITE(src)       (((u32)(src) << 1) & 0x000000feU)
+
+/* macros for field CONIEN */
+#define USB_IEN__CONIEN__MASK                                       0x00000001U
+#define USB_IEN__DISIEN__MASK                                       0x00000002U
+#define USB_IEN__UWRESIEN__MASK                                     0x00000004U
+#define USB_IEN__UHRESIEN__MASK                                     0x00000008U
+#define USB_IEN__U3EXTIEN__MASK                                     0x00000020U
+#define USB_IEN__CON2IEN__MASK                                      0x00010000U
+#define USB_IEN__U2RESIEN__MASK                                     0x00040000U
+#define USB_IEN__L2ENTIEN__MASK                                     0x00100000U
+#define USB_IEN__L2EXTIEN__MASK                                     0x00200000U
+
+/* macros for field CONI */
+#define USB_ISTS__CONI__SHIFT                                                 0
+#define USB_ISTS__DISI__SHIFT                                                 1
+#define USB_ISTS__UWRESI__SHIFT                                               2
+#define USB_ISTS__UHRESI__SHIFT                                               3
+#define USB_ISTS__U3EXTI__SHIFT                                               5
+#define USB_ISTS__CON2I__SHIFT                                               16
+#define USB_ISTS__DIS2I__SHIFT                                               17
+#define USB_ISTS__DIS2I__MASK                                       0x00020000U
+#define USB_ISTS__U2RESI__SHIFT                                              18
+#define USB_ISTS__L2ENTI__SHIFT                                              20
+#define USB_ISTS__L2EXTI__SHIFT                                              21
+
+/* macros for field TRADDR */
+#define EP_TRADDR__TRADDR__WRITE(src)           ((u32)(src) & 0xffffffffU)
+
+/* macros for field ENABLE */
+#define EP_CFG__ENABLE__MASK                                        0x00000001U
+#define EP_CFG__EPTYPE__WRITE(src)       (((u32)(src) << 1) & 0x00000006U)
+#define EP_CFG__MAXBURST__WRITE(src)     (((u32)(src) << 8) & 0x00000f00U)
+#define EP_CFG__MAXPKTSIZE__WRITE(src)  (((u32)(src) << 16) & 0x07ff0000U)
+#define EP_CFG__BUFFERING__WRITE(src)   (((u32)(src) << 27) & 0xf8000000U)
+
+/* macros for field EPRST */
+#define EP_CMD__EPRST__MASK                                         0x00000001U
+#define EP_CMD__SSTALL__MASK                                        0x00000002U
+#define EP_CMD__CSTALL__MASK                                        0x00000004U
+#define EP_CMD__ERDY__MASK                                          0x00000008U
+#define EP_CMD__REQ_CMPL__MASK                                      0x00000020U
+#define EP_CMD__DRDY__MASK                                          0x00000040U
+#define EP_CMD__DFLUSH__MASK                                        0x00000080U
+
+/* macros for field SETUP */
+#define EP_STS__SETUP__MASK                                         0x00000001U
+#define EP_STS__STALL__MASK                                         0x00000002U
+#define EP_STS__IOC__MASK                                           0x00000004U
+#define EP_STS__ISP__MASK                                           0x00000008U
+#define EP_STS__DESCMIS__MASK                                       0x00000010U
+#define EP_STS__TRBERR__MASK                                        0x00000080U
+#define EP_STS__NRDY__MASK                                          0x00000100U
+#define EP_STS__DBUSY__MASK                                         0x00000200U
+#define EP_STS__BUFFEMPTY__MASK                                     0x00000400U
+#define EP_STS__OUTSMM__MASK                                        0x00004000U
+#define EP_STS__ISOERR__MASK                                        0x00008000U
+
+/* macros for field SETUPEN */
+#define EP_STS_EN__SETUPEN__MASK                                    0x00000001U
+#define EP_STS_EN__DESCMISEN__MASK                                  0x00000010U
+#define EP_STS_EN__TRBERREN__MASK                                   0x00000080U
+
+/* macros for field EOUTEN0 */
+#define EP_IEN__EOUTEN0__MASK                                       0x00000001U
+#define EP_IEN__EINEN0__MASK                                        0x00010000U
+
+/* macros for field EOUT0 */
+#define EP_ISTS__EOUT0__MASK                                        0x00000001U
+#define EP_ISTS__EIN0__MASK                                         0x00010000U
+
+/* macros for field LFPS_MIN_DET_U1_EXIT */
+#define DBG_LINK1__LFPS_MIN_GEN_U1_EXIT__WRITE(src) \
+			(((u32)(src)\
+			<< 8) & 0x0000ff00U)
+#define DBG_LINK1__LFPS_MIN_GEN_U1_EXIT_SET__MASK                   0x02000000U
+
+#endif /* __REG_USBSS_DEV_ADDR_MAP_MACRO_H__ */
diff --git a/drivers/usb/cdns3/dev-regs-map.h b/drivers/usb/cdns3/dev-regs-map.h
new file mode 100644
index 00000000000..c2d43068b78
--- /dev/null
+++ b/drivers/usb/cdns3/dev-regs-map.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Cadence Design Systems - http://www.cadence.com
+ * Copyright 2019 NXP
+ */
+
+#ifndef __REG_USBSS_DEV_ADDR_MAP_H__
+#define __REG_USBSS_DEV_ADDR_MAP_H__
+
+#include "dev-regs-macro.h"
+
+struct usbss_dev_register_block_type {
+	u32 usb_conf;                     /*        0x0 - 0x4        */
+	u32 usb_sts;                      /*        0x4 - 0x8        */
+	u32 usb_cmd;                      /*        0x8 - 0xc        */
+	u32 usb_iptn;                     /*        0xc - 0x10       */
+	u32 usb_lpm;                      /*       0x10 - 0x14       */
+	u32 usb_ien;                      /*       0x14 - 0x18       */
+	u32 usb_ists;                     /*       0x18 - 0x1c       */
+	u32 ep_sel;                       /*       0x1c - 0x20       */
+	u32 ep_traddr;                    /*       0x20 - 0x24       */
+	u32 ep_cfg;                       /*       0x24 - 0x28       */
+	u32 ep_cmd;                       /*       0x28 - 0x2c       */
+	u32 ep_sts;                       /*       0x2c - 0x30       */
+	u32 ep_sts_sid;                   /*       0x30 - 0x34       */
+	u32 ep_sts_en;                    /*       0x34 - 0x38       */
+	u32 drbl;                         /*       0x38 - 0x3c       */
+	u32 ep_ien;                       /*       0x3c - 0x40       */
+	u32 ep_ists;                      /*       0x40 - 0x44       */
+	u32 usb_pwr;                      /*       0x44 - 0x48       */
+	u32 usb_conf2;                    /*       0x48 - 0x4c       */
+	u32 usb_cap1;                     /*       0x4c - 0x50       */
+	u32 usb_cap2;                     /*       0x50 - 0x54       */
+	u32 usb_cap3;                     /*       0x54 - 0x58       */
+	u32 usb_cap4;                     /*       0x58 - 0x5c       */
+	u32 usb_cap5;                     /*       0x5c - 0x60       */
+	u32 PAD2_73;                     /*       0x60 - 0x64       */
+	u32 usb_cpkt1;                    /*       0x64 - 0x68       */
+	u32 usb_cpkt2;                    /*       0x68 - 0x6c       */
+	u32 usb_cpkt3;                    /*       0x6c - 0x70       */
+	char pad__0[0x90];                     /*       0x70 - 0x100      */
+	u32 PAD2_78;                     /*      0x100 - 0x104      */
+	u32 dbg_link1;                    /*      0x104 - 0x108      */
+	u32 PAD2_80;                    /*      0x108 - 0x10c      */
+	u32 PAD2_81;                     /*      0x10c - 0x110      */
+	u32 PAD2_82;                     /*      0x110 - 0x114      */
+	u32 PAD2_83;                     /*      0x114 - 0x118      */
+	u32 PAD2_84;                     /*      0x118 - 0x11c      */
+	u32 PAD2_85;                     /*      0x11c - 0x120      */
+	u32 PAD2_86;                     /*      0x120 - 0x124      */
+	u32 PAD2_87;                    /*      0x124 - 0x128      */
+	u32 PAD2_88;                    /*      0x128 - 0x12c      */
+	u32 PAD2_89;                    /*      0x12c - 0x130      */
+	u32 PAD2_90;                    /*      0x130 - 0x134      */
+	u32 PAD2_91;                    /*      0x134 - 0x138      */
+	u32 PAD2_92;                    /*      0x138 - 0x13c      */
+	u32 PAD2_93;                    /*      0x13c - 0x140      */
+	u32 PAD2_94;                    /*      0x140 - 0x144      */
+	u32 PAD2_95;                    /*      0x144 - 0x148      */
+	u32 PAD2_96;                    /*      0x148 - 0x14c      */
+	u32 PAD2_97;                    /*      0x14c - 0x150      */
+	u32 PAD2_98;                    /*      0x150 - 0x154      */
+	u32 PAD2_99;                    /*      0x154 - 0x158      */
+	u32 PAD2_100;                    /*      0x158 - 0x15c      */
+	u32 PAD2_101;                    /*      0x15c - 0x160      */
+	u32 PAD2_102;                    /*      0x160 - 0x164      */
+	u32 PAD2_103;                    /*      0x164 - 0x168      */
+	u32 PAD2_104;                    /*      0x168 - 0x16c      */
+	u32 PAD2_105;                    /*      0x16c - 0x170      */
+	u32 PAD2_106;                    /*      0x170 - 0x174      */
+	u32 PAD2_107;                    /*      0x174 - 0x178      */
+	u32 PAD2_108;                    /*      0x178 - 0x17c      */
+	u32 PAD2_109;                    /*      0x17c - 0x180      */
+	u32 PAD2_110;                    /*      0x180 - 0x184      */
+	u32 PAD2_111;                    /*      0x184 - 0x188      */
+	u32 PAD2_112;                    /*      0x188 - 0x18c      */
+	char pad__1[0x20];                     /*      0x18c - 0x1ac      */
+	u32 PAD2_114;                    /*      0x1ac - 0x1b0      */
+	u32 PAD2_115;                    /*      0x1b0 - 0x1b4      */
+	u32 PAD2_116;                    /*      0x1b4 - 0x1b8      */
+	u32 PAD2_117;                    /*      0x1b8 - 0x1bc      */
+	u32 PAD2_118;                    /*      0x1bc - 0x1c0      */
+	u32 PAD2_119;                    /*      0x1c0 - 0x1c4      */
+	u32 PAD2_120;                    /*      0x1c4 - 0x1c8      */
+	u32 PAD2_121;                    /*      0x1c8 - 0x1cc      */
+	u32 PAD2_122;                    /*      0x1cc - 0x1d0      */
+	u32 PAD2_123;                    /*      0x1d0 - 0x1d4      */
+	u32 PAD2_124;                    /*      0x1d4 - 0x1d8      */
+	u32 PAD2_125;                    /*      0x1d8 - 0x1dc      */
+	u32 PAD2_126;                    /*      0x1dc - 0x1e0      */
+	u32 PAD2_127;                    /*      0x1e0 - 0x1e4      */
+	u32 PAD2_128;                    /*      0x1e4 - 0x1e8      */
+	u32 PAD2_129;                    /*      0x1e8 - 0x1ec      */
+	u32 PAD2_130;                    /*      0x1ec - 0x1f0      */
+	u32 PAD2_131;                    /*      0x1f0 - 0x1f4      */
+	u32 PAD2_132;                    /*      0x1f4 - 0x1f8      */
+	u32 PAD2_133;                    /*      0x1f8 - 0x1fc      */
+	u32 PAD2_134;                    /*      0x1fc - 0x200      */
+	u32 PAD2_135;                    /*      0x200 - 0x204      */
+	u32 PAD2_136;                    /*      0x204 - 0x208      */
+	u32 PAD2_137;                    /*      0x208 - 0x20c      */
+	u32 PAD2_138;                    /*      0x20c - 0x210      */
+	u32 PAD2_139;                    /*      0x210 - 0x214      */
+	u32 PAD2_140;                    /*      0x214 - 0x218      */
+	u32 PAD2_141;                    /*      0x218 - 0x21c      */
+	u32 PAD2_142;                    /*      0x21c - 0x220      */
+	u32 PAD2_143;                    /*      0x220 - 0x224      */
+	u32 PAD2_144;                    /*      0x224 - 0x228      */
+	char pad__2[0xd8];                     /*      0x228 - 0x300      */
+	u32 dma_axi_ctrl;                 /*      0x300 - 0x304      */
+	u32 PAD2_147;                   /*      0x304 - 0x308      */
+	u32 PAD2_148;                  /*      0x308 - 0x30c      */
+	u32 PAD2_149;                /*      0x30c - 0x310      */
+	u32 PAD2_150;                /*      0x310 - 0x314      */
+};
+
+#endif /* __REG_USBSS_DEV_ADDR_MAP_H__ */
diff --git a/drivers/usb/cdns3/drd.c b/drivers/usb/cdns3/drd.c
deleted file mode 100644
index 47874fec29e..00000000000
--- a/drivers/usb/cdns3/drd.c
+++ /dev/null
@@ -1,302 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Cadence USBSS DRD Driver.
- *
- * Copyright (C) 2018-2019 Cadence.
- * Copyright (C) 2019 Texas Instruments
- *
- * Author: Pawel Laszczak <pawell@cadence.com>
- *         Roger Quadros <rogerq@ti.com>
- *
- *
- */
-#include <dm.h>
-#include <dm/device_compat.h>
-#include <linux/delay.h>
-#include <linux/iopoll.h>
-#include <linux/kernel.h>
-#include <linux/usb/otg.h>
-
-#include "gadget.h"
-#include "drd.h"
-#include "core.h"
-
-#define readl_poll_timeout_atomic readl_poll_timeout
-#define usleep_range(a, b) udelay((b))
-/**
- * cdns3_set_mode - change mode of OTG Core
- * @cdns: pointer to context structure
- * @mode: selected mode from cdns_role
- *
- * Returns 0 on success otherwise negative errno
- */
-int cdns3_set_mode(struct cdns3 *cdns, enum usb_dr_mode mode)
-{
-	int ret = 0;
-	u32 reg;
-
-	switch (mode) {
-	case USB_DR_MODE_PERIPHERAL:
-		break;
-	case USB_DR_MODE_HOST:
-		break;
-	case USB_DR_MODE_OTG:
-		dev_dbg(cdns->dev, "Set controller to OTG mode\n");
-		if (cdns->version == CDNS3_CONTROLLER_V1) {
-			reg = readl(&cdns->otg_v1_regs->override);
-			reg |= OVERRIDE_IDPULLUP;
-			writel(reg, &cdns->otg_v1_regs->override);
-		} else {
-			reg = readl(&cdns->otg_v0_regs->ctrl1);
-			reg |= OVERRIDE_IDPULLUP_V0;
-			writel(reg, &cdns->otg_v0_regs->ctrl1);
-		}
-
-		/*
-		 * Hardware specification says: "ID_VALUE must be valid within
-		 * 50ms after idpullup is set to '1" so driver must wait
-		 * 50ms before reading this pin.
-		 */
-		usleep_range(50000, 60000);
-		break;
-	default:
-		dev_err(cdns->dev, "Unsupported mode of operation %d\n", mode);
-		return -EINVAL;
-	}
-
-	return ret;
-}
-
-int cdns3_get_id(struct cdns3 *cdns)
-{
-	int id;
-
-	id = readl(&cdns->otg_regs->sts) & OTGSTS_ID_VALUE;
-	dev_dbg(cdns->dev, "OTG ID: %d", id);
-
-	return id;
-}
-
-int cdns3_get_vbus(struct cdns3 *cdns)
-{
-	int vbus;
-
-	vbus = !!(readl(&cdns->otg_regs->sts) & OTGSTS_VBUS_VALID);
-	dev_dbg(cdns->dev, "OTG VBUS: %d", vbus);
-
-	return vbus;
-}
-
-int cdns3_is_host(struct cdns3 *cdns)
-{
-	if (cdns->dr_mode == USB_DR_MODE_HOST)
-		return 1;
-	else if (!cdns3_get_id(cdns))
-		return 1;
-
-	return 0;
-}
-
-int cdns3_is_device(struct cdns3 *cdns)
-{
-	if (cdns->dr_mode == USB_DR_MODE_PERIPHERAL)
-		return 1;
-	else if (cdns->dr_mode == USB_DR_MODE_OTG)
-		if (cdns3_get_id(cdns))
-			return 1;
-
-	return 0;
-}
-
-/**
- * cdns3_drd_switch_host - start/stop host
- * @cdns: Pointer to controller context structure
- * @on: 1 for start, 0 for stop
- *
- * Returns 0 on success otherwise negative errno
- */
-int cdns3_drd_switch_host(struct cdns3 *cdns, int on)
-{
-	int ret, val;
-	u32 reg = OTGCMD_OTG_DIS;
-
-	/* switch OTG core */
-	if (on) {
-		writel(OTGCMD_HOST_BUS_REQ | reg, &cdns->otg_regs->cmd);
-
-		dev_dbg(cdns->dev, "Waiting till Host mode is turned on\n");
-		ret = readl_poll_timeout_atomic(&cdns->otg_regs->sts, val,
-						val & OTGSTS_XHCI_READY,
-						100000);
-		if (ret) {
-			dev_err(cdns->dev, "timeout waiting for xhci_ready\n");
-			return ret;
-		}
-	} else {
-		writel(OTGCMD_HOST_BUS_DROP | OTGCMD_DEV_BUS_DROP |
-		       OTGCMD_DEV_POWER_OFF | OTGCMD_HOST_POWER_OFF,
-		       &cdns->otg_regs->cmd);
-		/* Waiting till H_IDLE state.*/
-		readl_poll_timeout_atomic(&cdns->otg_regs->state, val,
-					  !(val & OTGSTATE_HOST_STATE_MASK),
-					  2000000);
-	}
-
-	return 0;
-}
-
-/**
- * cdns3_drd_switch_gadget - start/stop gadget
- * @cdns: Pointer to controller context structure
- * @on: 1 for start, 0 for stop
- *
- * Returns 0 on success otherwise negative errno
- */
-int cdns3_drd_switch_gadget(struct cdns3 *cdns, int on)
-{
-	int ret, val;
-	u32 reg = OTGCMD_OTG_DIS;
-
-	/* switch OTG core */
-	if (on) {
-		writel(OTGCMD_DEV_BUS_REQ | reg, &cdns->otg_regs->cmd);
-
-		dev_dbg(cdns->dev, "Waiting till Device mode is turned on\n");
-
-		ret = readl_poll_timeout_atomic(&cdns->otg_regs->sts, val,
-						val & OTGSTS_DEV_READY,
-						100000);
-		if (ret) {
-			dev_err(cdns->dev, "timeout waiting for dev_ready\n");
-			return ret;
-		}
-	} else {
-		/*
-		 * driver should wait at least 10us after disabling Device
-		 * before turning-off Device (DEV_BUS_DROP)
-		 */
-		usleep_range(20, 30);
-		writel(OTGCMD_HOST_BUS_DROP | OTGCMD_DEV_BUS_DROP |
-		       OTGCMD_DEV_POWER_OFF | OTGCMD_HOST_POWER_OFF,
-		       &cdns->otg_regs->cmd);
-		/* Waiting till DEV_IDLE state.*/
-		readl_poll_timeout_atomic(&cdns->otg_regs->state, val,
-					  !(val & OTGSTATE_DEV_STATE_MASK),
-					  2000000);
-	}
-
-	return 0;
-}
-
-/**
- * cdns3_init_otg_mode - initialize drd controller
- * @cdns: Pointer to controller context structure
- *
- * Returns 0 on success otherwise negative errno
- */
-static int cdns3_init_otg_mode(struct cdns3 *cdns)
-{
-	int ret = 0;
-
-	/* clear all interrupts */
-	writel(~0, &cdns->otg_regs->ivect);
-
-	ret = cdns3_set_mode(cdns, USB_DR_MODE_OTG);
-	if (ret)
-		return ret;
-
-	return ret;
-}
-
-/**
- * cdns3_drd_update_mode - initialize mode of operation
- * @cdns: Pointer to controller context structure
- *
- * Returns 0 on success otherwise negative errno
- */
-int cdns3_drd_update_mode(struct cdns3 *cdns)
-{
-	int ret = 0;
-
-	switch (cdns->dr_mode) {
-	case USB_DR_MODE_PERIPHERAL:
-		ret = cdns3_set_mode(cdns, USB_DR_MODE_PERIPHERAL);
-		break;
-	case USB_DR_MODE_HOST:
-		ret = cdns3_set_mode(cdns, USB_DR_MODE_HOST);
-		break;
-	case USB_DR_MODE_OTG:
-		ret = cdns3_init_otg_mode(cdns);
-		break;
-	default:
-		dev_err(cdns->dev, "Unsupported mode of operation %d\n",
-			cdns->dr_mode);
-		return -EINVAL;
-	}
-
-	return ret;
-}
-
-int cdns3_drd_init(struct cdns3 *cdns)
-{
-	void __iomem *regs;
-	int ret = 0;
-	u32 state;
-
-	regs = dev_remap_addr_name(cdns->dev, "otg");
-	if (!regs)
-		return -EINVAL;
-
-	/* Detection of DRD version. Controller has been released
-	 * in two versions. Both are similar, but they have same changes
-	 * in register maps.
-	 * The first register in old version is command register and it's read
-	 * only, so driver should read 0 from it. On the other hand, in v1
-	 * the first register contains device ID number which is not set to 0.
-	 * Driver uses this fact to detect the proper version of
-	 * controller.
-	 */
-	cdns->otg_v0_regs = regs;
-	if (!readl(&cdns->otg_v0_regs->cmd)) {
-		cdns->version  = CDNS3_CONTROLLER_V0;
-		cdns->otg_v1_regs = NULL;
-		cdns->otg_regs = regs;
-		writel(1, &cdns->otg_v0_regs->simulate);
-		dev_info(cdns->dev, "DRD version v0 (%08x)\n",
-			 readl(&cdns->otg_v0_regs->version));
-	} else {
-		cdns->otg_v0_regs = NULL;
-		cdns->otg_v1_regs = regs;
-		cdns->otg_regs = (void *)&cdns->otg_v1_regs->cmd;
-		cdns->version  = CDNS3_CONTROLLER_V1;
-		writel(1, &cdns->otg_v1_regs->simulate);
-		dev_info(cdns->dev, "DRD version v1 (ID: %08x, rev: %08x)\n",
-			 readl(&cdns->otg_v1_regs->did),
-			 readl(&cdns->otg_v1_regs->rid));
-	}
-
-	state = OTGSTS_STRAP(readl(&cdns->otg_regs->sts));
-
-	/* Update dr_mode according to STRAP configuration. */
-	cdns->dr_mode = USB_DR_MODE_OTG;
-	if (state == OTGSTS_STRAP_HOST) {
-		dev_dbg(cdns->dev, "Controller strapped to HOST\n");
-		cdns->dr_mode = USB_DR_MODE_HOST;
-	} else if (state == OTGSTS_STRAP_GADGET) {
-		dev_dbg(cdns->dev, "Controller strapped to PERIPHERAL\n");
-		cdns->dr_mode = USB_DR_MODE_PERIPHERAL;
-	}
-
-	state = readl(&cdns->otg_regs->sts);
-	if (OTGSTS_OTG_NRDY(state) != 0) {
-		dev_err(cdns->dev, "Cadence USB3 OTG device not ready\n");
-		return -ENODEV;
-	}
-
-	return ret;
-}
-
-int cdns3_drd_exit(struct cdns3 *cdns)
-{
-	return 0;
-}
diff --git a/drivers/usb/cdns3/drd.h b/drivers/usb/cdns3/drd.h
deleted file mode 100644
index fffda7b43a4..00000000000
--- a/drivers/usb/cdns3/drd.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Cadence USB3 DRD header file.
- *
- * Copyright (C) 2018-2019 Cadence.
- *
- * Author: Pawel Laszczak <pawell@cadence.com>
- */
-#ifndef __LINUX_CDNS3_DRD
-#define __LINUX_CDNS3_DRD
-
-#include <linux/bitops.h>
-#include <linux/types.h>
-#include <linux/usb/otg.h>
-#include "core.h"
-
-/*  DRD register interface for version v1. */
-struct cdns3_otg_regs {
-	__le32 did;
-	__le32 rid;
-	__le32 capabilities;
-	__le32 reserved1;
-	__le32 cmd;
-	__le32 sts;
-	__le32 state;
-	__le32 reserved2;
-	__le32 ien;
-	__le32 ivect;
-	__le32 refclk;
-	__le32 tmr;
-	__le32 reserved3[4];
-	__le32 simulate;
-	__le32 override;
-	__le32 susp_ctrl;
-	__le32 reserved4;
-	__le32 anasts;
-	__le32 adp_ramp_time;
-	__le32 ctrl1;
-	__le32 ctrl2;
-};
-
-/*  DRD register interface for version v0. */
-struct cdns3_otg_legacy_regs {
-	__le32 cmd;
-	__le32 sts;
-	__le32 state;
-	__le32 refclk;
-	__le32 ien;
-	__le32 ivect;
-	__le32 reserved1[3];
-	__le32 tmr;
-	__le32 reserved2[2];
-	__le32 version;
-	__le32 capabilities;
-	__le32 reserved3[2];
-	__le32 simulate;
-	__le32 reserved4[5];
-	__le32 ctrl1;
-};
-
-/*
- * Common registers interface for both version of DRD.
- */
-struct cdns3_otg_common_regs {
-	__le32 cmd;
-	__le32 sts;
-	__le32 state;
-	__le32 different1;
-	__le32 ien;
-	__le32 ivect;
-};
-
-/* CDNS_RID - bitmasks */
-#define CDNS_RID(p)			((p) & GENMASK(15, 0))
-
-/* CDNS_VID - bitmasks */
-#define CDNS_DID(p)			((p) & GENMASK(31, 0))
-
-/* OTGCMD - bitmasks */
-/* "Request the bus for Device mode. */
-#define OTGCMD_DEV_BUS_REQ		BIT(0)
-/* Request the bus for Host mode */
-#define OTGCMD_HOST_BUS_REQ		BIT(1)
-/* Enable OTG mode. */
-#define OTGCMD_OTG_EN			BIT(2)
-/* Disable OTG mode */
-#define OTGCMD_OTG_DIS			BIT(3)
-/*"Configure OTG as A-Device. */
-#define OTGCMD_A_DEV_EN			BIT(4)
-/*"Configure OTG as A-Device. */
-#define OTGCMD_A_DEV_DIS		BIT(5)
-/* Drop the bus for Device mod	e. */
-#define OTGCMD_DEV_BUS_DROP		BIT(8)
-/* Drop the bus for Host mode*/
-#define OTGCMD_HOST_BUS_DROP		BIT(9)
-/* Power Down USBSS-DEV. */
-#define OTGCMD_DEV_POWER_OFF		BIT(11)
-/* Power Down CDNSXHCI. */
-#define OTGCMD_HOST_POWER_OFF		BIT(12)
-
-/* OTGIEN - bitmasks */
-/* ID change interrupt enable */
-#define OTGIEN_ID_CHANGE_INT		BIT(0)
-/* Vbusvalid fall detected interrupt enable.*/
-#define OTGIEN_VBUSVALID_RISE_INT	BIT(4)
-/* Vbusvalid fall detected interrupt enable */
-#define OTGIEN_VBUSVALID_FALL_INT	BIT(5)
-
-/* OTGSTS - bitmasks */
-/*
- * Current value of the ID pin. It is only valid when idpullup in
- *  OTGCTRL1_TYPE register is set to '1'.
- */
-#define OTGSTS_ID_VALUE			BIT(0)
-/* Current value of the vbus_valid */
-#define OTGSTS_VBUS_VALID		BIT(1)
-/* Current value of the b_sess_vld */
-#define OTGSTS_SESSION_VALID		BIT(2)
-/*Device mode is active*/
-#define OTGSTS_DEV_ACTIVE		BIT(3)
-/* Host mode is active. */
-#define OTGSTS_HOST_ACTIVE		BIT(4)
-/* OTG Controller not ready. */
-#define OTGSTS_OTG_NRDY_MASK		BIT(11)
-#define OTGSTS_OTG_NRDY(p)		((p) & OTGSTS_OTG_NRDY_MASK)
-/*
- * Value of the strap pins.
- * 000 - no default configuration
- * 010 - Controller initiall configured as Host
- * 100 - Controller initially configured as Device
- */
-#define OTGSTS_STRAP(p)			(((p) & GENMASK(14, 12)) >> 12)
-#define OTGSTS_STRAP_NO_DEFAULT_CFG	0x00
-#define OTGSTS_STRAP_HOST_OTG		0x01
-#define OTGSTS_STRAP_HOST		0x02
-#define OTGSTS_STRAP_GADGET		0x04
-/* Host mode is turned on. */
-#define OTGSTS_XHCI_READY		BIT(26)
-/* "Device mode is turned on .*/
-#define OTGSTS_DEV_READY		BIT(27)
-
-/* OTGSTATE- bitmasks */
-#define OTGSTATE_DEV_STATE_MASK		GENMASK(2, 0)
-#define OTGSTATE_HOST_STATE_MASK	GENMASK(5, 3)
-#define OTGSTATE_HOST_STATE_IDLE	0x0
-#define OTGSTATE_HOST_STATE_VBUS_FALL	0x7
-#define OTGSTATE_HOST_STATE(p)		(((p) & OTGSTATE_HOST_STATE_MASK) >> 3)
-
-/* OTGREFCLK - bitmasks */
-#define OTGREFCLK_STB_CLK_SWITCH_EN	BIT(31)
-
-/* OVERRIDE - bitmasks */
-#define OVERRIDE_IDPULLUP		BIT(0)
-/* Only for CDNS3_CONTROLLER_V0 version */
-#define OVERRIDE_IDPULLUP_V0		BIT(24)
-
-int cdns3_is_host(struct cdns3 *cdns);
-int cdns3_is_device(struct cdns3 *cdns);
-int cdns3_get_id(struct cdns3 *cdns);
-int cdns3_get_vbus(struct cdns3 *cdns);
-int cdns3_drd_init(struct cdns3 *cdns);
-int cdns3_drd_exit(struct cdns3 *cdns);
-int cdns3_drd_update_mode(struct cdns3 *cdns);
-int cdns3_drd_switch_gadget(struct cdns3 *cdns, int on);
-int cdns3_drd_switch_host(struct cdns3 *cdns, int on);
-
-#endif /* __LINUX_CDNS3_DRD */
diff --git a/drivers/usb/cdns3/ep0.c b/drivers/usb/cdns3/ep0.c
deleted file mode 100644
index acff79ae1ca..00000000000
--- a/drivers/usb/cdns3/ep0.c
+++ /dev/null
@@ -1,920 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Cadence USBSS DRD Driver - gadget side.
- *
- * Copyright (C) 2018 Cadence Design Systems.
- * Copyright (C) 2017-2018 NXP
- *
- * Authors: Pawel Jez <pjez@cadence.com>,
- *          Pawel Laszczak <pawell@cadence.com>
- *          Peter Chen <peter.chen@nxp.com>
- */
-
-#include <cpu_func.h>
-#include <dm.h>
-#include <dm/device_compat.h>
-#include <asm/cache.h>
-#include <linux/bitops.h>
-#include <linux/delay.h>
-#include <linux/usb/composite.h>
-#include <linux/iopoll.h>
-
-#include "gadget.h"
-#include "trace.h"
-
-#define readl_poll_timeout_atomic readl_poll_timeout
-#define usleep_range(a, b) udelay((b))
-
-static struct usb_endpoint_descriptor cdns3_gadget_ep0_desc = {
-	.bLength = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType = USB_DT_ENDPOINT,
-	.bmAttributes =	USB_ENDPOINT_XFER_CONTROL,
-};
-
-/**
- * cdns3_ep0_run_transfer - Do transfer on default endpoint hardware
- * @priv_dev: extended gadget object
- * @dma_addr: physical address where data is/will be stored
- * @length: data length
- * @erdy: set it to 1 when ERDY packet should be sent -
- *        exit from flow control state
- */
-static void cdns3_ep0_run_transfer(struct cdns3_device *priv_dev,
-				   dma_addr_t dma_addr,
-				   unsigned int length, int erdy, int zlp)
-{
-	struct cdns3_usb_regs __iomem *regs = priv_dev->regs;
-	struct cdns3_endpoint *priv_ep = priv_dev->eps[0];
-
-	priv_ep->trb_pool[0].buffer = TRB_BUFFER(dma_addr);
-	priv_ep->trb_pool[0].length = TRB_LEN(length);
-
-	if (zlp) {
-		priv_ep->trb_pool[0].control = TRB_CYCLE | TRB_TYPE(TRB_NORMAL);
-		priv_ep->trb_pool[1].buffer = TRB_BUFFER(dma_addr);
-		priv_ep->trb_pool[1].length = TRB_LEN(0);
-		priv_ep->trb_pool[1].control = TRB_CYCLE | TRB_IOC |
-		    TRB_TYPE(TRB_NORMAL);
-	} else {
-		priv_ep->trb_pool[0].control = TRB_CYCLE | TRB_IOC |
-		    TRB_TYPE(TRB_NORMAL);
-		priv_ep->trb_pool[1].control = 0;
-	}
-
-	/* Flush both TRBs */
-	flush_dcache_range((unsigned long)priv_ep->trb_pool,
-			   (unsigned long)priv_ep->trb_pool +
-			   ROUND(sizeof(struct cdns3_trb) * 2,
-				 CONFIG_SYS_CACHELINE_SIZE));
-
-	trace_cdns3_prepare_trb(priv_ep, priv_ep->trb_pool);
-
-	cdns3_select_ep(priv_dev, priv_dev->ep0_data_dir);
-
-	writel(EP_STS_TRBERR, &regs->ep_sts);
-	writel(EP_TRADDR_TRADDR(priv_ep->trb_pool_dma), &regs->ep_traddr);
-	trace_cdns3_doorbell_ep0(priv_dev->ep0_data_dir ? "ep0in" : "ep0out",
-				 readl(&regs->ep_traddr));
-
-	/* TRB should be prepared before starting transfer. */
-	writel(EP_CMD_DRDY, &regs->ep_cmd);
-
-	/* Resume controller before arming transfer. */
-	__cdns3_gadget_wakeup(priv_dev);
-
-	if (erdy)
-		writel(EP_CMD_ERDY, &priv_dev->regs->ep_cmd);
-}
-
-/**
- * cdns3_ep0_delegate_req - Returns status of handling setup packet
- * Setup is handled by gadget driver
- * @priv_dev: extended gadget object
- * @ctrl_req: pointer to received setup packet
- *
- * Returns zero on success or negative value on failure
- */
-static int cdns3_ep0_delegate_req(struct cdns3_device *priv_dev,
-				  struct usb_ctrlrequest *ctrl_req)
-{
-	int ret;
-
-	spin_unlock(&priv_dev->lock);
-	priv_dev->setup_pending = 1;
-	ret = priv_dev->gadget_driver->setup(&priv_dev->gadget, ctrl_req);
-	priv_dev->setup_pending = 0;
-	spin_lock(&priv_dev->lock);
-	return ret;
-}
-
-static void cdns3_prepare_setup_packet(struct cdns3_device *priv_dev)
-{
-	priv_dev->ep0_data_dir = 0;
-	priv_dev->ep0_stage = CDNS3_SETUP_STAGE;
-	cdns3_ep0_run_transfer(priv_dev, priv_dev->setup_dma,
-			       sizeof(struct usb_ctrlrequest), 0, 0);
-}
-
-static void cdns3_ep0_complete_setup(struct cdns3_device *priv_dev,
-				     u8 send_stall, u8 send_erdy)
-{
-	struct cdns3_endpoint *priv_ep = priv_dev->eps[0];
-	struct usb_request *request;
-
-	request = cdns3_next_request(&priv_ep->pending_req_list);
-	if (request)
-		list_del_init(&request->list);
-
-	if (send_stall) {
-		trace_cdns3_halt(priv_ep, send_stall, 0);
-		/* set_stall on ep0 */
-		cdns3_select_ep(priv_dev, 0x00);
-		writel(EP_CMD_SSTALL, &priv_dev->regs->ep_cmd);
-	} else {
-		cdns3_prepare_setup_packet(priv_dev);
-	}
-
-	priv_dev->ep0_stage = CDNS3_SETUP_STAGE;
-	writel((send_erdy ? EP_CMD_ERDY : 0) | EP_CMD_REQ_CMPL,
-	       &priv_dev->regs->ep_cmd);
-
-	cdns3_allow_enable_l1(priv_dev, 1);
-}
-
-/**
- * cdns3_req_ep0_set_configuration - Handling of SET_CONFIG standard USB request
- * @priv_dev: extended gadget object
- * @ctrl_req: pointer to received setup packet
- *
- * Returns 0 if success, USB_GADGET_DELAYED_STATUS on deferred status stage,
- * error code on error
- */
-static int cdns3_req_ep0_set_configuration(struct cdns3_device *priv_dev,
-					   struct usb_ctrlrequest *ctrl_req)
-{
-	enum usb_device_state device_state = priv_dev->gadget.state;
-	struct cdns3_endpoint *priv_ep;
-	u32 config = le16_to_cpu(ctrl_req->wValue);
-	int result = 0;
-	int i;
-
-	switch (device_state) {
-	case USB_STATE_ADDRESS:
-		/* Configure non-control EPs */
-		for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++) {
-			priv_ep = priv_dev->eps[i];
-			if (!priv_ep)
-				continue;
-
-			if (priv_ep->flags & EP_CLAIMED)
-				cdns3_ep_config(priv_ep);
-		}
-
-		result = cdns3_ep0_delegate_req(priv_dev, ctrl_req);
-
-		if (result)
-			return result;
-
-		if (config) {
-			cdns3_set_hw_configuration(priv_dev);
-		} else {
-			cdns3_hw_reset_eps_config(priv_dev);
-			usb_gadget_set_state(&priv_dev->gadget,
-					     USB_STATE_ADDRESS);
-		}
-		break;
-	case USB_STATE_CONFIGURED:
-		result = cdns3_ep0_delegate_req(priv_dev, ctrl_req);
-
-		if (!config && !result) {
-			cdns3_hw_reset_eps_config(priv_dev);
-			usb_gadget_set_state(&priv_dev->gadget,
-					     USB_STATE_ADDRESS);
-		}
-		break;
-	default:
-		result = -EINVAL;
-	}
-
-	return result;
-}
-
-/**
- * cdns3_req_ep0_set_address - Handling of SET_ADDRESS standard USB request
- * @priv_dev: extended gadget object
- * @ctrl_req: pointer to received setup packet
- *
- * Returns 0 if success, error code on error
- */
-static int cdns3_req_ep0_set_address(struct cdns3_device *priv_dev,
-				     struct usb_ctrlrequest *ctrl_req)
-{
-	enum usb_device_state device_state = priv_dev->gadget.state;
-	u32 reg;
-	u32 addr;
-
-	addr = le16_to_cpu(ctrl_req->wValue);
-
-	if (addr > USB_DEVICE_MAX_ADDRESS) {
-		dev_err(priv_dev->dev,
-			"Device address (%d) cannot be greater than %d\n",
-			addr, USB_DEVICE_MAX_ADDRESS);
-		return -EINVAL;
-	}
-
-	if (device_state == USB_STATE_CONFIGURED) {
-		dev_err(priv_dev->dev,
-			"can't set_address from configured state\n");
-		return -EINVAL;
-	}
-
-	reg = readl(&priv_dev->regs->usb_cmd);
-
-	writel(reg | USB_CMD_FADDR(addr) | USB_CMD_SET_ADDR,
-	       &priv_dev->regs->usb_cmd);
-
-	usb_gadget_set_state(&priv_dev->gadget,
-			     (addr ? USB_STATE_ADDRESS : USB_STATE_DEFAULT));
-
-	return 0;
-}
-
-/**
- * cdns3_req_ep0_get_status - Handling of GET_STATUS standard USB request
- * @priv_dev: extended gadget object
- * @ctrl_req: pointer to received setup packet
- *
- * Returns 0 if success, error code on error
- */
-static int cdns3_req_ep0_get_status(struct cdns3_device *priv_dev,
-				    struct usb_ctrlrequest *ctrl)
-{
-	__le16 *response_pkt;
-	u16 usb_status = 0;
-	u32 recip;
-
-	recip = ctrl->bRequestType & USB_RECIP_MASK;
-
-	switch (recip) {
-	case USB_RECIP_DEVICE:
-		/* self powered */
-		if (priv_dev->is_selfpowered)
-			usb_status = BIT(USB_DEVICE_SELF_POWERED);
-
-		if (priv_dev->wake_up_flag)
-			usb_status |= BIT(USB_DEVICE_REMOTE_WAKEUP);
-
-		if (priv_dev->gadget.speed != USB_SPEED_SUPER)
-			break;
-
-		if (priv_dev->u1_allowed)
-			usb_status |= BIT(USB_DEV_STAT_U1_ENABLED);
-
-		if (priv_dev->u2_allowed)
-			usb_status |= BIT(USB_DEV_STAT_U2_ENABLED);
-
-		break;
-	case USB_RECIP_INTERFACE:
-		return cdns3_ep0_delegate_req(priv_dev, ctrl);
-	case USB_RECIP_ENDPOINT:
-		/* check if endpoint is stalled */
-		cdns3_select_ep(priv_dev, ctrl->wIndex);
-		if (EP_STS_STALL(readl(&priv_dev->regs->ep_sts)))
-			usb_status =  BIT(USB_ENDPOINT_HALT);
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	response_pkt = (__le16 *)priv_dev->setup_buf;
-	*response_pkt = cpu_to_le16(usb_status);
-
-	/* Flush setup response */
-	flush_dcache_range((unsigned long)priv_dev->setup_buf,
-			   (unsigned long)priv_dev->setup_buf +
-			   ROUND(sizeof(struct usb_ctrlrequest),
-				 CONFIG_SYS_CACHELINE_SIZE));
-
-	cdns3_ep0_run_transfer(priv_dev, priv_dev->setup_dma,
-			       sizeof(*response_pkt), 1, 0);
-	return 0;
-}
-
-static int cdns3_ep0_feature_handle_device(struct cdns3_device *priv_dev,
-					   struct usb_ctrlrequest *ctrl,
-					   int set)
-{
-	enum usb_device_state state;
-	enum usb_device_speed speed;
-	int ret = 0;
-	u16 tmode;
-
-	state = priv_dev->gadget.state;
-	speed = priv_dev->gadget.speed;
-
-	switch (ctrl->wValue) {
-	case USB_DEVICE_REMOTE_WAKEUP:
-		priv_dev->wake_up_flag = !!set;
-		break;
-	case USB_DEVICE_U1_ENABLE:
-		if (state != USB_STATE_CONFIGURED || speed != USB_SPEED_SUPER)
-			return -EINVAL;
-
-		priv_dev->u1_allowed = !!set;
-		break;
-	case USB_DEVICE_U2_ENABLE:
-		if (state != USB_STATE_CONFIGURED || speed != USB_SPEED_SUPER)
-			return -EINVAL;
-
-		priv_dev->u2_allowed = !!set;
-		break;
-	case USB_DEVICE_LTM_ENABLE:
-		ret = -EINVAL;
-		break;
-	case USB_DEVICE_TEST_MODE:
-		if (state != USB_STATE_CONFIGURED || speed > USB_SPEED_HIGH)
-			return -EINVAL;
-
-		tmode = le16_to_cpu(ctrl->wIndex);
-
-		if (!set || (tmode & 0xff) != 0)
-			return -EINVAL;
-
-		switch (tmode >> 8) {
-		case TEST_J:
-		case TEST_K:
-		case TEST_SE0_NAK:
-		case TEST_PACKET:
-			cdns3_ep0_complete_setup(priv_dev, 0, 1);
-			/**
-			 *  Little delay to give the controller some time
-			 * for sending status stage.
-			 * This time should be less then 3ms.
-			 */
-			usleep_range(1000, 2000);
-			cdns3_set_register_bit(&priv_dev->regs->usb_cmd,
-					       USB_CMD_STMODE |
-					       USB_STS_TMODE_SEL(tmode - 1));
-			break;
-		default:
-			ret = -EINVAL;
-		}
-		break;
-	default:
-		ret = -EINVAL;
-	}
-
-	return ret;
-}
-
-static int cdns3_ep0_feature_handle_intf(struct cdns3_device *priv_dev,
-					 struct usb_ctrlrequest *ctrl,
-					 int set)
-{
-	u32 wValue;
-	int ret = 0;
-
-	wValue = le16_to_cpu(ctrl->wValue);
-
-	switch (wValue) {
-	case USB_INTRF_FUNC_SUSPEND:
-		break;
-	default:
-		ret = -EINVAL;
-	}
-
-	return ret;
-}
-
-static int cdns3_ep0_feature_handle_endpoint(struct cdns3_device *priv_dev,
-					     struct usb_ctrlrequest *ctrl,
-					     int set)
-{
-	struct cdns3_endpoint *priv_ep;
-	int ret = 0;
-	u8 index;
-
-	if (le16_to_cpu(ctrl->wValue) != USB_ENDPOINT_HALT)
-		return -EINVAL;
-
-	if (!(ctrl->wIndex & ~USB_DIR_IN))
-		return 0;
-
-	index = cdns3_ep_addr_to_index(ctrl->wIndex);
-	priv_ep = priv_dev->eps[index];
-
-	cdns3_select_ep(priv_dev, ctrl->wIndex);
-
-	if (set)
-		__cdns3_gadget_ep_set_halt(priv_ep);
-	else if (!(priv_ep->flags & EP_WEDGE))
-		ret = __cdns3_gadget_ep_clear_halt(priv_ep);
-
-	cdns3_select_ep(priv_dev, 0x00);
-
-	return ret;
-}
-
-/**
- * cdns3_req_ep0_handle_feature -
- * Handling of GET/SET_FEATURE standard USB request
- *
- * @priv_dev: extended gadget object
- * @ctrl_req: pointer to received setup packet
- * @set: must be set to 1 for SET_FEATURE request
- *
- * Returns 0 if success, error code on error
- */
-static int cdns3_req_ep0_handle_feature(struct cdns3_device *priv_dev,
-					struct usb_ctrlrequest *ctrl,
-					int set)
-{
-	int ret = 0;
-	u32 recip;
-
-	recip = ctrl->bRequestType & USB_RECIP_MASK;
-
-	switch (recip) {
-	case USB_RECIP_DEVICE:
-		ret = cdns3_ep0_feature_handle_device(priv_dev, ctrl, set);
-		break;
-	case USB_RECIP_INTERFACE:
-		ret = cdns3_ep0_feature_handle_intf(priv_dev, ctrl, set);
-		break;
-	case USB_RECIP_ENDPOINT:
-		ret = cdns3_ep0_feature_handle_endpoint(priv_dev, ctrl, set);
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	return ret;
-}
-
-/**
- * cdns3_req_ep0_set_sel - Handling of SET_SEL standard USB request
- * @priv_dev: extended gadget object
- * @ctrl_req: pointer to received setup packet
- *
- * Returns 0 if success, error code on error
- */
-static int cdns3_req_ep0_set_sel(struct cdns3_device *priv_dev,
-				 struct usb_ctrlrequest *ctrl_req)
-{
-	if (priv_dev->gadget.state < USB_STATE_ADDRESS)
-		return -EINVAL;
-
-	if (ctrl_req->wLength != 6) {
-		dev_err(priv_dev->dev, "Set SEL should be 6 bytes, got %d\n",
-			ctrl_req->wLength);
-		return -EINVAL;
-	}
-
-	cdns3_ep0_run_transfer(priv_dev, priv_dev->setup_dma, 6, 1, 0);
-	return 0;
-}
-
-/**
- * cdns3_req_ep0_set_isoch_delay -
- * Handling of GET_ISOCH_DELAY standard USB request
- * @priv_dev: extended gadget object
- * @ctrl_req: pointer to received setup packet
- *
- * Returns 0 if success, error code on error
- */
-static int cdns3_req_ep0_set_isoch_delay(struct cdns3_device *priv_dev,
-					 struct usb_ctrlrequest *ctrl_req)
-{
-	if (ctrl_req->wIndex || ctrl_req->wLength)
-		return -EINVAL;
-
-	priv_dev->isoch_delay = ctrl_req->wValue;
-
-	return 0;
-}
-
-/**
- * cdns3_ep0_standard_request - Handling standard USB requests
- * @priv_dev: extended gadget object
- * @ctrl_req: pointer to received setup packet
- *
- * Returns 0 if success, error code on error
- */
-static int cdns3_ep0_standard_request(struct cdns3_device *priv_dev,
-				      struct usb_ctrlrequest *ctrl_req)
-{
-	int ret;
-
-	switch (ctrl_req->bRequest) {
-	case USB_REQ_SET_ADDRESS:
-		ret = cdns3_req_ep0_set_address(priv_dev, ctrl_req);
-		break;
-	case USB_REQ_SET_CONFIGURATION:
-		ret = cdns3_req_ep0_set_configuration(priv_dev, ctrl_req);
-		break;
-	case USB_REQ_GET_STATUS:
-		ret = cdns3_req_ep0_get_status(priv_dev, ctrl_req);
-		break;
-	case USB_REQ_CLEAR_FEATURE:
-		ret = cdns3_req_ep0_handle_feature(priv_dev, ctrl_req, 0);
-		break;
-	case USB_REQ_SET_FEATURE:
-		ret = cdns3_req_ep0_handle_feature(priv_dev, ctrl_req, 1);
-		break;
-	case USB_REQ_SET_SEL:
-		ret = cdns3_req_ep0_set_sel(priv_dev, ctrl_req);
-		break;
-	case USB_REQ_SET_ISOCH_DELAY:
-		ret = cdns3_req_ep0_set_isoch_delay(priv_dev, ctrl_req);
-		break;
-	default:
-		ret = cdns3_ep0_delegate_req(priv_dev, ctrl_req);
-		break;
-	}
-
-	return ret;
-}
-
-static void __pending_setup_status_handler(struct cdns3_device *priv_dev)
-{
-	struct usb_request *request = priv_dev->pending_status_request;
-
-	if (priv_dev->status_completion_no_call && request &&
-	    request->complete) {
-		request->complete(&priv_dev->eps[0]->endpoint, request);
-		priv_dev->status_completion_no_call = 0;
-	}
-}
-
-void cdns3_pending_setup_status_handler(struct work_struct *work)
-{
-	struct cdns3_device *priv_dev = container_of(work, struct cdns3_device,
-			pending_status_wq);
-	unsigned long flags;
-
-	spin_lock_irqsave(&priv_dev->lock, flags);
-	__pending_setup_status_handler(priv_dev);
-	spin_unlock_irqrestore(&priv_dev->lock, flags);
-}
-
-/**
- * cdns3_ep0_setup_phase - Handling setup USB requests
- * @priv_dev: extended gadget object
- */
-static void cdns3_ep0_setup_phase(struct cdns3_device *priv_dev)
-{
-	struct usb_ctrlrequest *ctrl = priv_dev->setup_buf;
-	struct cdns3_endpoint *priv_ep = priv_dev->eps[0];
-	int result;
-
-	/* Invalidate Setup Packet received */
-	invalidate_dcache_range(priv_dev->setup_dma,
-				priv_dev->setup_dma + ARCH_DMA_MINALIGN);
-
-	priv_dev->ep0_data_dir = ctrl->bRequestType & USB_DIR_IN;
-
-	trace_cdns3_ctrl_req(ctrl);
-
-	if (!list_empty(&priv_ep->pending_req_list)) {
-		struct usb_request *request;
-
-		request = cdns3_next_request(&priv_ep->pending_req_list);
-		priv_ep->dir = priv_dev->ep0_data_dir;
-		cdns3_gadget_giveback(priv_ep, to_cdns3_request(request),
-				      -ECONNRESET);
-	}
-
-	if (le16_to_cpu(ctrl->wLength))
-		priv_dev->ep0_stage = CDNS3_DATA_STAGE;
-	else
-		priv_dev->ep0_stage = CDNS3_STATUS_STAGE;
-
-	if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
-		result = cdns3_ep0_standard_request(priv_dev, ctrl);
-	else
-		result = cdns3_ep0_delegate_req(priv_dev, ctrl);
-
-	if (result == USB_GADGET_DELAYED_STATUS)
-		return;
-
-	if (result < 0)
-		cdns3_ep0_complete_setup(priv_dev, 1, 1);
-	else if (priv_dev->ep0_stage == CDNS3_STATUS_STAGE)
-		cdns3_ep0_complete_setup(priv_dev, 0, 1);
-}
-
-static void cdns3_transfer_completed(struct cdns3_device *priv_dev)
-{
-	struct cdns3_endpoint *priv_ep = priv_dev->eps[0];
-
-	if (!list_empty(&priv_ep->pending_req_list)) {
-		struct usb_request *request;
-
-		trace_cdns3_complete_trb(priv_ep, priv_ep->trb_pool);
-		request = cdns3_next_request(&priv_ep->pending_req_list);
-
-		/* Invalidate TRB before accessing it */
-		invalidate_dcache_range((unsigned long)priv_ep->trb_pool,
-					(unsigned long)priv_ep->trb_pool +
-					ROUND(sizeof(struct cdns3_trb),
-					      CONFIG_SYS_CACHELINE_SIZE));
-
-		request->actual =
-			TRB_LEN(le32_to_cpu(priv_ep->trb_pool->length));
-
-		priv_ep->dir = priv_dev->ep0_data_dir;
-		cdns3_gadget_giveback(priv_ep, to_cdns3_request(request), 0);
-	}
-
-	cdns3_ep0_complete_setup(priv_dev, 0, 0);
-}
-
-/**
- * cdns3_check_new_setup - Check if controller receive new SETUP packet.
- * @priv_dev: extended gadget object
- *
- * The SETUP packet can be kept in on-chip memory or in system memory.
- */
-static bool cdns3_check_new_setup(struct cdns3_device *priv_dev)
-{
-	u32 ep_sts_reg;
-
-	cdns3_select_ep(priv_dev, 0 | USB_DIR_OUT);
-	ep_sts_reg = readl(&priv_dev->regs->ep_sts);
-
-	return !!(ep_sts_reg & (EP_STS_SETUP | EP_STS_STPWAIT));
-}
-
-/**
- * cdns3_check_ep0_interrupt_proceed - Processes interrupt related to endpoint 0
- * @priv_dev: extended gadget object
- * @dir: USB_DIR_IN for IN direction, USB_DIR_OUT for OUT direction
- */
-void cdns3_check_ep0_interrupt_proceed(struct cdns3_device *priv_dev, int dir)
-{
-	u32 ep_sts_reg;
-
-	cdns3_select_ep(priv_dev, dir);
-
-	ep_sts_reg = readl(&priv_dev->regs->ep_sts);
-	writel(ep_sts_reg, &priv_dev->regs->ep_sts);
-
-	trace_cdns3_ep0_irq(priv_dev, ep_sts_reg);
-
-	__pending_setup_status_handler(priv_dev);
-
-	if (ep_sts_reg & EP_STS_SETUP)
-		priv_dev->wait_for_setup = 1;
-
-	if (priv_dev->wait_for_setup && ep_sts_reg & EP_STS_IOC) {
-		priv_dev->wait_for_setup = 0;
-		cdns3_allow_enable_l1(priv_dev, 0);
-		cdns3_ep0_setup_phase(priv_dev);
-	} else if ((ep_sts_reg & EP_STS_IOC) || (ep_sts_reg & EP_STS_ISP)) {
-		priv_dev->ep0_data_dir = dir;
-		cdns3_transfer_completed(priv_dev);
-	}
-
-	if (ep_sts_reg & EP_STS_DESCMIS) {
-		if (dir == 0 && !priv_dev->setup_pending)
-			cdns3_prepare_setup_packet(priv_dev);
-	}
-}
-
-/**
- * cdns3_gadget_ep0_enable
- * Function shouldn't be called by gadget driver,
- * endpoint 0 is allways active
- */
-static int cdns3_gadget_ep0_enable(struct usb_ep *ep,
-				   const struct usb_endpoint_descriptor *desc)
-{
-	return -EINVAL;
-}
-
-/**
- * cdns3_gadget_ep0_disable
- * Function shouldn't be called by gadget driver,
- * endpoint 0 is allways active
- */
-static int cdns3_gadget_ep0_disable(struct usb_ep *ep)
-{
-	return -EINVAL;
-}
-
-/**
- * cdns3_gadget_ep0_set_halt
- * @ep: pointer to endpoint zero object
- * @value: 1 for set stall, 0 for clear stall
- *
- * Returns 0
- */
-static int cdns3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
-{
-	/* TODO */
-	return 0;
-}
-
-/**
- * cdns3_gadget_ep0_queue Transfer data on endpoint zero
- * @ep: pointer to endpoint zero object
- * @request: pointer to request object
- * @gfp_flags: gfp flags
- *
- * Returns 0 on success, error code elsewhere
- */
-static int cdns3_gadget_ep0_queue(struct usb_ep *ep,
-				  struct usb_request *request,
-				  gfp_t gfp_flags)
-{
-	struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
-	struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
-	unsigned long flags;
-	int erdy_sent = 0;
-	int ret = 0;
-	u8 zlp = 0;
-
-	trace_cdns3_ep0_queue(priv_dev, request);
-
-	/* cancel the request if controller receive new SETUP packet. */
-	if (cdns3_check_new_setup(priv_dev))
-		return -ECONNRESET;
-
-	/* send STATUS stage. Should be called only for SET_CONFIGURATION */
-	if (priv_dev->ep0_stage == CDNS3_STATUS_STAGE) {
-		spin_lock_irqsave(&priv_dev->lock, flags);
-		cdns3_select_ep(priv_dev, 0x00);
-
-		erdy_sent = !priv_dev->hw_configured_flag;
-		cdns3_set_hw_configuration(priv_dev);
-
-		if (!erdy_sent)
-			cdns3_ep0_complete_setup(priv_dev, 0, 1);
-
-		cdns3_allow_enable_l1(priv_dev, 1);
-
-		request->actual = 0;
-		priv_dev->status_completion_no_call = true;
-		priv_dev->pending_status_request = request;
-		spin_unlock_irqrestore(&priv_dev->lock, flags);
-
-		/*
-		 * Since there is no completion interrupt for status stage,
-		 * it needs to call ->completion in software after
-		 * ep0_queue is back.
-		 */
-#ifndef __UBOOT__
-		queue_work(system_freezable_wq, &priv_dev->pending_status_wq);
-#else
-		__pending_setup_status_handler(priv_dev);
-#endif
-		return 0;
-	}
-
-	spin_lock_irqsave(&priv_dev->lock, flags);
-	if (!list_empty(&priv_ep->pending_req_list)) {
-		dev_err(priv_dev->dev,
-			"can't handle multiple requests for ep0\n");
-		spin_unlock_irqrestore(&priv_dev->lock, flags);
-		return -EBUSY;
-	}
-
-	ret = usb_gadget_map_request(&priv_dev->gadget, request,
-				     priv_dev->ep0_data_dir);
-	if (ret) {
-		spin_unlock_irqrestore(&priv_dev->lock, flags);
-		dev_err(priv_dev->dev, "failed to map request\n");
-		return -EINVAL;
-	}
-
-	request->status = -EINPROGRESS;
-	list_add_tail(&request->list, &priv_ep->pending_req_list);
-
-	if (request->zero && request->length &&
-	    (request->length % ep->maxpacket == 0))
-		zlp = 1;
-
-	cdns3_ep0_run_transfer(priv_dev, request->dma, request->length, 1, zlp);
-
-	spin_unlock_irqrestore(&priv_dev->lock, flags);
-
-	return ret;
-}
-
-/**
- * cdns3_gadget_ep_set_wedge Set wedge on selected endpoint
- * @ep: endpoint object
- *
- * Returns 0
- */
-int cdns3_gadget_ep_set_wedge(struct usb_ep *ep)
-{
-	struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
-
-	dev_dbg(priv_ep->cdns3_dev->dev, "Wedge for %s\n", ep->name);
-	cdns3_gadget_ep_set_halt(ep, 1);
-	priv_ep->flags |= EP_WEDGE;
-
-	return 0;
-}
-
-const struct usb_ep_ops cdns3_gadget_ep0_ops = {
-	.enable = cdns3_gadget_ep0_enable,
-	.disable = cdns3_gadget_ep0_disable,
-	.alloc_request = cdns3_gadget_ep_alloc_request,
-	.free_request = cdns3_gadget_ep_free_request,
-	.queue = cdns3_gadget_ep0_queue,
-	.dequeue = cdns3_gadget_ep_dequeue,
-	.set_halt = cdns3_gadget_ep0_set_halt,
-	.set_wedge = cdns3_gadget_ep_set_wedge,
-};
-
-/**
- * cdns3_ep0_config - Configures default endpoint
- * @priv_dev: extended gadget object
- *
- * Functions sets parameters: maximal packet size and enables interrupts
- */
-void cdns3_ep0_config(struct cdns3_device *priv_dev)
-{
-	struct cdns3_usb_regs __iomem *regs;
-	struct cdns3_endpoint *priv_ep;
-	u32 max_packet_size = 64;
-
-	regs = priv_dev->regs;
-
-	if (priv_dev->gadget.speed == USB_SPEED_SUPER)
-		max_packet_size = 512;
-
-	priv_ep = priv_dev->eps[0];
-
-	if (!list_empty(&priv_ep->pending_req_list)) {
-		struct usb_request *request;
-
-		request = cdns3_next_request(&priv_ep->pending_req_list);
-		list_del_init(&request->list);
-	}
-
-	priv_dev->u1_allowed = 0;
-	priv_dev->u2_allowed = 0;
-
-	priv_dev->gadget.ep0->maxpacket = max_packet_size;
-	cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(max_packet_size);
-
-	/* init ep out */
-	cdns3_select_ep(priv_dev, USB_DIR_OUT);
-
-	if (priv_dev->dev_ver >= DEV_VER_V3) {
-		cdns3_set_register_bit(&priv_dev->regs->dtrans,
-				       BIT(0) | BIT(16));
-		cdns3_set_register_bit(&priv_dev->regs->tdl_from_trb,
-				       BIT(0) | BIT(16));
-	}
-
-	writel(EP_CFG_ENABLE | EP_CFG_MAXPKTSIZE(max_packet_size),
-	       &regs->ep_cfg);
-
-	writel(EP_STS_EN_SETUPEN | EP_STS_EN_DESCMISEN | EP_STS_EN_TRBERREN,
-	       &regs->ep_sts_en);
-
-	/* init ep in */
-	cdns3_select_ep(priv_dev, USB_DIR_IN);
-
-	writel(EP_CFG_ENABLE | EP_CFG_MAXPKTSIZE(max_packet_size),
-	       &regs->ep_cfg);
-
-	writel(EP_STS_EN_SETUPEN | EP_STS_EN_TRBERREN, &regs->ep_sts_en);
-
-	cdns3_set_register_bit(&regs->usb_conf, USB_CONF_U1DS | USB_CONF_U2DS);
-}
-
-/**
- * cdns3_init_ep0 Initializes software endpoint 0 of gadget
- * @priv_dev: extended gadget object
- * @ep_priv: extended endpoint object
- *
- * Returns 0 on success else error code.
- */
-int cdns3_init_ep0(struct cdns3_device *priv_dev,
-		   struct cdns3_endpoint *priv_ep)
-{
-	sprintf(priv_ep->name, "ep0");
-
-	/* fill linux fields */
-	priv_ep->endpoint.ops = &cdns3_gadget_ep0_ops;
-	priv_ep->endpoint.maxburst = 1;
-	usb_ep_set_maxpacket_limit(&priv_ep->endpoint,
-				   CDNS3_EP0_MAX_PACKET_LIMIT);
-#ifndef __UBOOT__
-	priv_ep->endpoint.address = 0;
-#endif
-	priv_ep->endpoint.caps.type_control = 1;
-	priv_ep->endpoint.caps.dir_in = 1;
-	priv_ep->endpoint.caps.dir_out = 1;
-	priv_ep->endpoint.name = priv_ep->name;
-	priv_ep->endpoint.desc = &cdns3_gadget_ep0_desc;
-	priv_dev->gadget.ep0 = &priv_ep->endpoint;
-	priv_ep->type = USB_ENDPOINT_XFER_CONTROL;
-
-	return cdns3_allocate_trb_pool(priv_ep);
-}
diff --git a/drivers/usb/cdns3/gadget-export.h b/drivers/usb/cdns3/gadget-export.h
index 577469eee96..0b011b56c6d 100644
--- a/drivers/usb/cdns3/gadget-export.h
+++ b/drivers/usb/cdns3/gadget-export.h
@@ -1,19 +1,15 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Cadence USBSS DRD Driver - Gadget Export APIs.
- *
- * Copyright (C) 2017 NXP
- * Copyright (C) 2017-2018 NXP
- *
- * Authors: Peter Chen <peter.chen@nxp.com>
+ * Copyright 2019 NXP
  */
-#ifndef __LINUX_CDNS3_GADGET_EXPORT
-#define __LINUX_CDNS3_GADGET_EXPORT
+
+#ifndef __CDNS3_GADGET_EXPORT_H
+#define __CDNS3_GADGET_EXPORT_H
 
 #ifdef CONFIG_USB_CDNS3_GADGET
 
 int cdns3_gadget_init(struct cdns3 *cdns);
-void cdns3_gadget_exit(struct cdns3 *cdns);
+void cdns3_gadget_remove(struct cdns3 *cdns);
 #else
 
 static inline int cdns3_gadget_init(struct cdns3 *cdns)
@@ -21,8 +17,10 @@ static inline int cdns3_gadget_init(struct cdns3 *cdns)
 	return -ENXIO;
 }
 
-static inline void cdns3_gadget_exit(struct cdns3 *cdns) { }
+static inline void cdns3_gadget_remove(struct cdns3 *cdns)
+{
+}
 
 #endif
 
-#endif /* __LINUX_CDNS3_GADGET_EXPORT */
+#endif /* __CDNS3_GADGET_EXPORT_H */
diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c
index fcaeab9cc1d..5bd80cf9868 100644
--- a/drivers/usb/cdns3/gadget.c
+++ b/drivers/usb/cdns3/gadget.c
@@ -1,2717 +1,2219 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * Cadence USBSS DRD Driver - gadget side.
- *
- * Copyright (C) 2018-2019 Cadence Design Systems.
- * Copyright (C) 2017-2018 NXP
- *
- * Authors: Pawel Jez <pjez@cadence.com>,
- *          Pawel Laszczak <pawell@cadence.com>
- *          Peter Chen <peter.chen@nxp.com>
- */
-
-/*
- * Work around 1:
- * At some situations, the controller may get stale data address in TRB
- * at below sequences:
- * 1. Controller read TRB includes data address
- * 2. Software updates TRBs includes data address and Cycle bit
- * 3. Controller read TRB which includes Cycle bit
- * 4. DMA run with stale data address
- *
- * To fix this problem, driver needs to make the first TRB in TD as invalid.
- * After preparing all TRBs driver needs to check the position of DMA and
- * if the DMA point to the first just added TRB and doorbell is 1,
- * then driver must defer making this TRB as valid. This TRB will be make
- * as valid during adding next TRB only if DMA is stopped or at TRBERR
- * interrupt.
- *
- * Issue has been fixed in DEV_VER_V3 version of controller.
- *
- * Work around 2:
- * Controller for OUT endpoints has shared on-chip buffers for all incoming
- * packets, including ep0out. It's FIFO buffer, so packets must be handle by DMA
- * in correct order. If the first packet in the buffer will not be handled,
- * then the following packets directed for other endpoints and  functions
- * will be blocked.
- * Additionally the packets directed to one endpoint can block entire on-chip
- * buffers. In this case transfer to other endpoints also will blocked.
- *
- * To resolve this issue after raising the descriptor missing interrupt
- * driver prepares internal usb_request object and use it to arm DMA transfer.
- *
- * The problematic situation was observed in case when endpoint has been enabled
- * but no usb_request were queued. Driver try detects such endpoints and will
- * use this workaround only for these endpoint.
- *
- * Driver use limited number of buffer. This number can be set by macro
- * CDNS3_WA2_NUM_BUFFERS.
- *
- * Such blocking situation was observed on ACM gadget. For this function
- * host send OUT data packet but ACM function is not prepared for this packet.
- * It's cause that buffer placed in on chip memory block transfer to other
- * endpoints.
- *
- * Issue has been fixed in DEV_VER_V2 version of controller.
- *
+ * Copyright (C) 2016 Cadence Design Systems - https://www.cadence.com/
+ * Copyright 2019 NXP
  */
+#include <common.h>
+#include <malloc.h>
+#include <asm/dma-mapping.h>
+#include <asm/io.h>
+#include <linux/bug.h>
+#include <linux/compat.h>
+#include <linux/list.h>
 
+#include <linux/usb/ch9.h>
+#include <linux/usb/composite.h>
+#include <linux/usb/gadget.h>
 #include <dm.h>
-#include <dm/device_compat.h>
 #include <dm/devres.h>
-#include <linux/bitops.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/usb/gadget.h>
-#include <linux/compat.h>
-#include <linux/iopoll.h>
-#include <linux/dma-mapping.h>
-#include <linux/bitmap.h>
-#include <linux/bug.h>
+#include <dm/device_compat.h>
 
 #include "core.h"
 #include "gadget-export.h"
 #include "gadget.h"
-#include "trace.h"
-#include "drd.h"
-
-#define readl_poll_timeout_atomic readl_poll_timeout
-#define usleep_range(a, b) udelay((b))
-
-static int __cdns3_gadget_ep_queue(struct usb_ep *ep,
-				   struct usb_request *request,
-				   gfp_t gfp_flags);
-
-/**
- * cdns3_set_register_bit - set bit in given register.
- * @ptr: address of device controller register to be read and changed
- * @mask: bits requested to set
- */
-void cdns3_set_register_bit(void __iomem *ptr, u32 mask)
-{
-	mask = readl(ptr) | mask;
-	writel(mask, ptr);
-}
-
-/**
- * cdns3_ep_addr_to_index - Macro converts endpoint address to
- * index of endpoint object in cdns3_device.eps[] container
- * @ep_addr: endpoint address for which endpoint object is required
- *
- */
-u8 cdns3_ep_addr_to_index(u8 ep_addr)
-{
-	return (((ep_addr & 0x7F)) + ((ep_addr & USB_DIR_IN) ? 16 : 0));
-}
-
-static int cdns3_get_dma_pos(struct cdns3_device *priv_dev,
-			     struct cdns3_endpoint *priv_ep)
-{
-	int dma_index;
-
-	dma_index = readl(&priv_dev->regs->ep_traddr) - priv_ep->trb_pool_dma;
-
-	return dma_index / TRB_SIZE;
-}
+#include "io.h"
+#include <linux/iopoll.h>
 
-/**
- * cdns3_next_request - returns next request from list
- * @list: list containing requests
- *
- * Returns request or NULL if no requests in list
- */
-struct usb_request *cdns3_next_request(struct list_head *list)
-{
-	return list_first_entry_or_null(list, struct usb_request, list);
-}
+static void __cdns3_gadget_start(struct usb_ss_dev *usb_ss);
+static void cdns_prepare_setup_packet(struct usb_ss_dev *usb_ss);
+static void cdns_ep_config(struct usb_ss_endpoint *usb_ss_ep);
 
-/**
- * cdns3_next_align_buf - returns next buffer from list
- * @list: list containing buffers
- *
- * Returns buffer or NULL if no buffers in list
- */
-struct cdns3_aligned_buf *cdns3_next_align_buf(struct list_head *list)
-{
-	return list_first_entry_or_null(list, struct cdns3_aligned_buf, list);
-}
+static struct usb_endpoint_descriptor cdns3_gadget_ep0_desc = {
+	.bLength	= USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType = USB_DT_ENDPOINT,
+	.bmAttributes	= USB_ENDPOINT_XFER_CONTROL,
+};
 
 /**
- * cdns3_next_priv_request - returns next request from list
+ * next_request - returns next request from list
  * @list: list containing requests
  *
  * Returns request or NULL if no requests in list
  */
-struct cdns3_request *cdns3_next_priv_request(struct list_head *list)
+static struct usb_request *next_request(struct list_head *list)
 {
-	return list_first_entry_or_null(list, struct cdns3_request, list);
+	if (list_empty(list))
+		return NULL;
+	return list_first_entry(list, struct usb_request, list);
 }
 
 /**
  * select_ep - selects endpoint
- * @priv_dev:  extended gadget object
+ * @usb_ss: extended gadget object
  * @ep: endpoint address
  */
-void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep)
+static void select_ep(struct usb_ss_dev *usb_ss, u32 ep)
 {
-	if (priv_dev->selected_ep == ep)
+	if (!usb_ss || !usb_ss->regs) {
+		dev_err(&usb_ss->dev, "Failed to select endpoint!\n");
 		return;
-
-	priv_dev->selected_ep = ep;
-	writel(ep, &priv_dev->regs->ep_sel);
-}
-
-dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep,
-				 struct cdns3_trb *trb)
-{
-	u32 offset = (char *)trb - (char *)priv_ep->trb_pool;
-
-	return priv_ep->trb_pool_dma + offset;
-}
-
-int cdns3_ring_size(struct cdns3_endpoint *priv_ep)
-{
-	switch (priv_ep->type) {
-	case USB_ENDPOINT_XFER_ISOC:
-		return TRB_ISO_RING_SIZE;
-	case USB_ENDPOINT_XFER_CONTROL:
-		return TRB_CTRL_RING_SIZE;
-	default:
-		return TRB_RING_SIZE;
 	}
+
+	cdns_writel(&usb_ss->regs->ep_sel, ep);
 }
 
 /**
- * cdns3_allocate_trb_pool - Allocates TRB's pool for selected endpoint
- * @priv_ep:  endpoint object
+ * usb_ss_allocate_trb_pool - Allocates TRB's pool for selected endpoint
+ * @usb_ss_ep: extended endpoint object
  *
  * Function will return 0 on success or -ENOMEM on allocation error
  */
-int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep)
+static int usb_ss_allocate_trb_pool(struct usb_ss_endpoint *usb_ss_ep)
 {
-	int ring_size = cdns3_ring_size(priv_ep);
-	struct cdns3_trb *link_trb;
-
-	if (!priv_ep->trb_pool) {
-		priv_ep->trb_pool =
-		dma_alloc_coherent(ring_size,
-				   (unsigned long *)&priv_ep->trb_pool_dma);
-		if (!priv_ep->trb_pool)
-			return -ENOMEM;
-	} else {
-		memset(priv_ep->trb_pool, 0, ring_size);
-	}
-
-	if (!priv_ep->num)
+	if (usb_ss_ep->trb_pool)
 		return 0;
 
-	priv_ep->num_trbs = ring_size / TRB_SIZE;
-	/* Initialize the last TRB as Link TRB. */
-	link_trb = (priv_ep->trb_pool + (priv_ep->num_trbs - 1));
-	link_trb->buffer = TRB_BUFFER(priv_ep->trb_pool_dma);
-	link_trb->control = TRB_CYCLE | TRB_TYPE(TRB_LINK) | TRB_TOGGLE;
+	usb_ss_ep->trb_pool =
+		dma_alloc_coherent(sizeof(struct usb_ss_trb) * USB_SS_TRBS_NUM,
+				   (unsigned long *)&usb_ss_ep->trb_pool_dma);
 
-	return 0;
-}
-
-static void cdns3_free_trb_pool(struct cdns3_endpoint *priv_ep)
-{
-	if (priv_ep->trb_pool) {
-		dma_free_coherent(priv_ep->trb_pool);
-		priv_ep->trb_pool = NULL;
+	if (!usb_ss_ep->trb_pool) {
+		dev_err(&usb_ss_ep->usb_ss->dev,
+			"Failed to allocate TRB pool for endpoint %s\n",
+			usb_ss_ep->name);
+		return -ENOMEM;
 	}
+
+	memset(usb_ss_ep->trb_pool, 0,
+	       sizeof(struct usb_ss_trb) * USB_SS_TRBS_NUM);
+
+	return 0;
 }
 
 /**
- * cdns3_ep_stall_flush - Stalls and flushes selected endpoint
- * @priv_ep: endpoint object
+ * cdns_ep_stall_flush - Stalls and flushes selected endpoint
+ * @usb_ss_ep: extended endpoint object
  *
  * Endpoint must be selected before call to this function
  */
-static void cdns3_ep_stall_flush(struct cdns3_endpoint *priv_ep)
+static void cdns_ep_stall_flush(struct usb_ss_endpoint *usb_ss_ep)
 {
-	struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
-	int val;
-
-	trace_cdns3_halt(priv_ep, 1, 1);
+	struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss;
 
-	writel(EP_CMD_DFLUSH | EP_CMD_ERDY | EP_CMD_SSTALL,
-	       &priv_dev->regs->ep_cmd);
+	cdns_writel(&usb_ss->regs->ep_cmd,
+		    EP_CMD__DFLUSH__MASK | EP_CMD__ERDY__MASK |
+		    EP_CMD__SSTALL__MASK);
 
 	/* wait for DFLUSH cleared */
-	readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
-				  !(val & EP_CMD_DFLUSH), 1000);
-	priv_ep->flags |= EP_STALLED;
-	priv_ep->flags &= ~EP_STALL_PENDING;
-}
-
-/**
- * cdns3_hw_reset_eps_config - reset endpoints configuration kept by controller.
- * @priv_dev: extended gadget object
- */
-void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev)
-{
-	writel(USB_CONF_CFGRST, &priv_dev->regs->usb_conf);
+	while (cdns_readl(&usb_ss->regs->ep_cmd) &
+	       EP_CMD__DFLUSH__MASK)
+		;
 
-	cdns3_allow_enable_l1(priv_dev, 0);
-	priv_dev->hw_configured_flag = 0;
-	priv_dev->onchip_used_size = 0;
-	priv_dev->out_mem_is_allocated = 0;
-	priv_dev->wait_for_setup = 0;
+	usb_ss_ep->stalled_flag = 1;
 }
 
 /**
- * cdns3_ep_inc_trb - increment a trb index.
- * @index: Pointer to the TRB index to increment.
- * @cs: Cycle state
- * @trb_in_seg: number of TRBs in segment
+ * cdns_ep0_config - Configures default endpoint
+ * @usb_ss: extended gadget object
  *
- * The index should never point to the link TRB. After incrementing,
- * if it is point to the link TRB, wrap around to the beginning and revert
- * cycle state bit The
- * link TRB is always at the last TRB entry.
+ * Functions sets parameters: maximal packet size and enables interrupts
  */
-static void cdns3_ep_inc_trb(int *index, u8 *cs, int trb_in_seg)
+static void cdns_ep0_config(struct usb_ss_dev *usb_ss)
 {
-	(*index)++;
-	if (*index == (trb_in_seg - 1)) {
-		*index = 0;
-		*cs ^=  1;
-	}
-}
+	u32 max_packet_size = 0;
 
-/**
- * cdns3_ep_inc_enq - increment endpoint's enqueue pointer
- * @priv_ep: The endpoint whose enqueue pointer we're incrementing
- */
-static void cdns3_ep_inc_enq(struct cdns3_endpoint *priv_ep)
-{
-	priv_ep->free_trbs--;
-	cdns3_ep_inc_trb(&priv_ep->enqueue, &priv_ep->pcs, priv_ep->num_trbs);
-}
+	switch (usb_ss->gadget.speed) {
+	case USB_SPEED_UNKNOWN:
+		max_packet_size = ENDPOINT_MAX_PACKET_SIZE_0;
+		usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_0;
+		cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(0);
+		break;
 
-/**
- * cdns3_ep_inc_deq - increment endpoint's dequeue pointer
- * @priv_ep: The endpoint whose dequeue pointer we're incrementing
- */
-static void cdns3_ep_inc_deq(struct cdns3_endpoint *priv_ep)
-{
-	priv_ep->free_trbs++;
-	cdns3_ep_inc_trb(&priv_ep->dequeue, &priv_ep->ccs, priv_ep->num_trbs);
-}
+	case USB_SPEED_LOW:
+		max_packet_size = ENDPOINT_MAX_PACKET_SIZE_8;
+		usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_8;
+		cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
+		break;
 
-void cdns3_move_deq_to_next_trb(struct cdns3_request *priv_req)
-{
-	struct cdns3_endpoint *priv_ep = priv_req->priv_ep;
-	int current_trb = priv_req->start_trb;
+	case USB_SPEED_FULL:
+	case USB_SPEED_HIGH:
+	case USB_SPEED_WIRELESS:
+		max_packet_size = ENDPOINT_MAX_PACKET_SIZE_64;
+		usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_64;
+		cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
+		break;
 
-	while (current_trb != priv_req->end_trb) {
-		cdns3_ep_inc_deq(priv_ep);
-		current_trb = priv_ep->dequeue;
+	case USB_SPEED_SUPER:
+	case USB_SPEED_SUPER_PLUS:
+		max_packet_size = ENDPOINT_MAX_PACKET_SIZE_512;
+		usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_512;
+		cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
+		break;
 	}
 
-	cdns3_ep_inc_deq(priv_ep);
+	/* init ep out */
+	select_ep(usb_ss, USB_DIR_OUT);
+
+	cdns_writel(&usb_ss->regs->ep_cfg,
+		    EP_CFG__ENABLE__MASK |
+		    EP_CFG__MAXPKTSIZE__WRITE(max_packet_size));
+	cdns_writel(&usb_ss->regs->ep_sts_en,
+		    EP_STS_EN__SETUPEN__MASK |
+		    EP_STS_EN__DESCMISEN__MASK |
+		    EP_STS_EN__TRBERREN__MASK);
+
+	/* init ep in */
+	select_ep(usb_ss, USB_DIR_IN);
+
+	cdns_writel(&usb_ss->regs->ep_cfg,
+		    EP_CFG__ENABLE__MASK |
+		    EP_CFG__MAXPKTSIZE__WRITE(max_packet_size));
+	cdns_writel(&usb_ss->regs->ep_sts_en,
+		    EP_STS_EN__SETUPEN__MASK |
+		    EP_STS_EN__TRBERREN__MASK);
+
+	cdns_prepare_setup_packet(usb_ss);
 }
 
 /**
- * cdns3_allow_enable_l1 - enable/disable permits to transition to L1.
- * @priv_dev: Extended gadget object
- * @enable: Enable/disable permit to transition to L1.
- *
- * If bit USB_CONF_L1EN is set and device receive Extended Token packet,
- * then controller answer with ACK handshake.
- * If bit USB_CONF_L1DS is set and device receive Extended Token packet,
- * then controller answer with NYET handshake.
+ * cdns_gadget_unconfig - Unconfigures device controller
+ * @usb_ss: extended gadget object
  */
-void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable)
+static void cdns_gadget_unconfig(struct usb_ss_dev *usb_ss)
 {
-	if (enable)
-		writel(USB_CONF_L1EN, &priv_dev->regs->usb_conf);
-	else
-		writel(USB_CONF_L1DS, &priv_dev->regs->usb_conf);
-}
+	/* RESET CONFIGURATION */
+	cdns_writel(&usb_ss->regs->usb_conf,
+		    USB_CONF__CFGRST__MASK);
 
-enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev)
-{
-	u32 reg;
-
-	reg = readl(&priv_dev->regs->usb_sts);
-
-	if (DEV_SUPERSPEED(reg))
-		return USB_SPEED_SUPER;
-	else if (DEV_HIGHSPEED(reg))
-		return USB_SPEED_HIGH;
-	else if (DEV_FULLSPEED(reg))
-		return USB_SPEED_FULL;
-	else if (DEV_LOWSPEED(reg))
-		return USB_SPEED_LOW;
-	return USB_SPEED_UNKNOWN;
+	usb_ss->hw_configured_flag = 0;
 }
 
 /**
- * cdns3_start_all_request - add to ring all request not started
- * @priv_dev: Extended gadget object
- * @priv_ep: The endpoint for whom request will be started.
- *
- * Returns return ENOMEM if transfer ring i not enough TRBs to start
- *         all requests.
+ * cdns_ep0_run_transfer - Do transfer on default endpoint hardware
+ * @usb_ss: extended gadget object
+ * @dma_addr: physical address where data is/will be stored
+ * @length: data length
+ * @erdy: set it to 1 when ERDY packet should be sent -
+ *        exit from flow control state
  */
-static int cdns3_start_all_request(struct cdns3_device *priv_dev,
-				   struct cdns3_endpoint *priv_ep)
+static void cdns_ep0_run_transfer(struct usb_ss_dev *usb_ss,
+				  dma_addr_t dma_addr,
+				  unsigned int length, int erdy)
 {
-	struct usb_request *request;
-	int ret = 0;
+	usb_ss->trb_ep0[0] = TRB_SET_DATA_BUFFER_POINTER(dma_addr);
+	usb_ss->trb_ep0[1] = TRB_SET_TRANSFER_LENGTH((u32)length);
+	usb_ss->trb_ep0[2] = TRB_SET_CYCLE_BIT |
+		TRB_SET_INT_ON_COMPLETION | TRB_TYPE_NORMAL;
 
-	while (!list_empty(&priv_ep->deferred_req_list)) {
-		request = cdns3_next_request(&priv_ep->deferred_req_list);
+	cdns_flush_cache((uintptr_t)usb_ss->trb_ep0, 20);
+	cdns_flush_cache((uintptr_t)dma_addr, length);
 
-		ret = cdns3_ep_run_transfer(priv_ep, request);
-		if (ret)
-			return ret;
+	dev_dbg(&usb_ss->dev, "DRBL(%02X)\n",
+		usb_ss->ep0_data_dir ? USB_DIR_IN : USB_DIR_OUT);
 
-		list_del(&request->list);
-		list_add_tail(&request->list,
-			      &priv_ep->pending_req_list);
-	}
+	select_ep(usb_ss, usb_ss->ep0_data_dir
+		? USB_DIR_IN : USB_DIR_OUT);
 
-	priv_ep->flags &= ~EP_RING_FULL;
-	return ret;
-}
+	cdns_writel(&usb_ss->regs->ep_traddr,
+		    EP_TRADDR__TRADDR__WRITE(usb_ss->trb_ep0_dma));
+	cdns_writel(&usb_ss->regs->ep_cmd,
+		    EP_CMD__DRDY__MASK); /* drbl */
 
-/*
- * WA2: Set flag for all not ISOC OUT endpoints. If this flag is set
- * driver try to detect whether endpoint need additional internal
- * buffer for unblocking on-chip FIFO buffer. This flag will be cleared
- * if before first DESCMISS interrupt the DMA will be armed.
- */
-#define cdns3_wa2_enable_detection(priv_dev, ep_priv, reg) do { \
-	if (!priv_ep->dir && priv_ep->type != USB_ENDPOINT_XFER_ISOC) { \
-		priv_ep->flags |= EP_QUIRK_EXTRA_BUF_DET; \
-		(reg) |= EP_STS_EN_DESCMISEN; \
-	} } while (0)
+	if (erdy)
+		cdns_writel(&usb_ss->regs->ep_cmd,
+			    EP_CMD__ERDY__MASK);
+}
 
 /**
- * cdns3_wa2_descmiss_copy_data copy data from internal requests to
- * request queued by class driver.
- * @priv_ep: extended endpoint object
- * @request: request object
+ * cdns_ep_run_transfer - Do transfer on no-default endpoint hardware
+ * @usb_ss_ep: extended endpoint object
+ *
+ * Returns zero on success or negative value on failure
  */
-static void cdns3_wa2_descmiss_copy_data(struct cdns3_endpoint *priv_ep,
-					 struct usb_request *request)
+static int cdns_ep_run_transfer(struct usb_ss_endpoint *usb_ss_ep)
 {
-	struct usb_request *descmiss_req;
-	struct cdns3_request *descmiss_priv_req;
-
-	while (!list_empty(&priv_ep->wa2_descmiss_req_list)) {
-		int chunk_end;
-		int length;
-
-		descmiss_priv_req =
-			cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list);
-		descmiss_req = &descmiss_priv_req->request;
-
-		/* driver can't touch pending request */
-		if (descmiss_priv_req->flags & REQUEST_PENDING)
-			break;
-
-		chunk_end = descmiss_priv_req->flags & REQUEST_INTERNAL_CH;
-		length = request->actual + descmiss_req->actual;
-
-		request->status = descmiss_req->status;
+	dma_addr_t trb_dma;
+	struct usb_request *request = next_request(&usb_ss_ep->request_list);
+	struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss;
+	struct usb_ss_trb *trb;
 
-		if (length <= request->length) {
-			memcpy(&((u8 *)request->buf)[request->actual],
-			       descmiss_req->buf,
-			       descmiss_req->actual);
-			request->actual = length;
-		} else {
-			/* It should never occur */
-			request->status = -ENOMEM;
-		}
+	if (!request)
+		return -EINVAL;
 
-		list_del_init(&descmiss_priv_req->list);
+	dev_dbg(&usb_ss->dev, "DRBL(%02X)\n",
+		usb_ss_ep->endpoint.desc->bEndpointAddress);
 
-		kfree(descmiss_req->buf);
-		cdns3_gadget_ep_free_request(&priv_ep->endpoint, descmiss_req);
-		--priv_ep->wa2_counter;
+	usb_ss_ep->hw_pending_flag = 1;
+	trb_dma = request->dma;
 
-		if (!chunk_end)
-			break;
+	/* must allocate buffer aligned to 8 */
+	if (request->dma % ADDR_MODULO_8) {
+		memcpy(usb_ss_ep->cpu_addr, request->buf, request->length);
+		trb_dma = usb_ss_ep->dma_addr;
 	}
-}
 
-struct usb_request *cdns3_wa2_gadget_giveback(struct cdns3_device *priv_dev,
-					      struct cdns3_endpoint *priv_ep,
-					      struct cdns3_request *priv_req)
-{
-	if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN &&
-	    priv_req->flags & REQUEST_INTERNAL) {
-		struct usb_request *req;
+	cdns_flush_cache((uintptr_t)trb_dma, request->length);
 
-		req = cdns3_next_request(&priv_ep->deferred_req_list);
+	trb = usb_ss_ep->trb_pool;
 
-		priv_ep->descmis_req = NULL;
+	/* fill TRB */
+	trb->offset0 = trb_dma;
 
-		if (!req)
-			return NULL;
+	trb->offset4 = TRB_SET_BURST_LENGTH(16) |
+		TRB_SET_TRANSFER_LENGTH(request->length);
 
-		cdns3_wa2_descmiss_copy_data(priv_ep, req);
-		if (!(priv_ep->flags & EP_QUIRK_END_TRANSFER) &&
-		    req->length != req->actual) {
-			/* wait for next part of transfer */
-			return NULL;
-		}
+	trb->offset8 = TRB_SET_CYCLE_BIT
+		| TRB_SET_INT_ON_COMPLETION
+		| TRB_SET_INT_ON_SHORT_PACKET
+		| TRB_TYPE_NORMAL;
 
-		if (req->status == -EINPROGRESS)
-			req->status = 0;
+	cdns_flush_cache((uintptr_t)trb, sizeof(struct usb_ss_trb));
 
-		list_del_init(&req->list);
-		cdns3_start_all_request(priv_dev, priv_ep);
-		return req;
-	}
+	/* arm transfer on selected endpoint */
+	select_ep(usb_ss_ep->usb_ss,
+		  usb_ss_ep->endpoint.desc->bEndpointAddress);
 
-	return &priv_req->request;
+	cdns_writel(&usb_ss->regs->ep_traddr,
+		    EP_TRADDR__TRADDR__WRITE(usb_ss_ep->trb_pool_dma));
+	cdns_writel(&usb_ss->regs->ep_cmd,
+		    EP_CMD__DRDY__MASK); /* DRDY */
+	return 0;
 }
 
-int cdns3_wa2_gadget_ep_queue(struct cdns3_device *priv_dev,
-			      struct cdns3_endpoint *priv_ep,
-			      struct cdns3_request *priv_req)
+/**
+ * cdns_get_setup_ret - Returns status of handling setup packet
+ * Setup is handled by gadget driver
+ * @usb_ss: extended gadget object
+ * @ctrl_req: pointer to received setup packet
+ *
+ * Returns zero on success or negative value on failure
+ */
+static int cdns_get_setup_ret(struct usb_ss_dev *usb_ss,
+			      struct usb_ctrlrequest *ctrl_req)
 {
-	int deferred = 0;
+	int ret;
 
-	/*
-	 * If transfer was queued before DESCMISS appear than we
-	 * can disable handling of DESCMISS interrupt. Driver assumes that it
-	 * can disable special treatment for this endpoint.
-	 */
-	if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_DET) {
-		u32 reg;
-
-		cdns3_select_ep(priv_dev, priv_ep->num | priv_ep->dir);
-		priv_ep->flags &= ~EP_QUIRK_EXTRA_BUF_DET;
-		reg = readl(&priv_dev->regs->ep_sts_en);
-		reg &= ~EP_STS_EN_DESCMISEN;
-		trace_cdns3_wa2(priv_ep, "workaround disabled\n");
-		writel(reg, &priv_dev->regs->ep_sts_en);
-	}
+	spin_unlock(&usb_ss->lock);
+	usb_ss->setup_pending = 1;
+	ret = usb_ss->gadget_driver->setup(&usb_ss->gadget, ctrl_req);
+	usb_ss->setup_pending = 0;
+	spin_lock(&usb_ss->lock);
+	return ret;
+}
 
-	if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN) {
-		u8 pending_empty = list_empty(&priv_ep->pending_req_list);
-		u8 descmiss_empty = list_empty(&priv_ep->wa2_descmiss_req_list);
+static void cdns_prepare_setup_packet(struct usb_ss_dev *usb_ss)
+{
+	usb_ss->ep0_data_dir = 0;
+	cdns_ep0_run_transfer(usb_ss, usb_ss->setup_dma, 8, 0);
+}
 
-		/*
-		 *  DESCMISS transfer has been finished, so data will be
-		 *  directly copied from internal allocated usb_request
-		 *  objects.
-		 */
-		if (pending_empty && !descmiss_empty &&
-		    !(priv_req->flags & REQUEST_INTERNAL)) {
-			cdns3_wa2_descmiss_copy_data(priv_ep,
-						     &priv_req->request);
-
-			trace_cdns3_wa2(priv_ep, "get internal stored data");
-
-			list_add_tail(&priv_req->request.list,
-				      &priv_ep->pending_req_list);
-			cdns3_gadget_giveback(priv_ep, priv_req,
-					      priv_req->request.status);
-
-			/*
-			 * Intentionally driver returns positive value as
-			 * correct value. It informs that transfer has
-			 * been finished.
-			 */
-			return EINPROGRESS;
-		}
+/**
+ * cdns_req_ep0_set_address - Handling of SET_ADDRESS standard USB request
+ * @usb_ss: extended gadget object
+ * @ctrl_req: pointer to received setup packet
+ *
+ * Returns 0 if success, error code on error
+ */
+static int cdns_req_ep0_set_address(struct usb_ss_dev *usb_ss,
+				    struct usb_ctrlrequest *ctrl_req)
+{
+	enum usb_device_state device_state = usb_ss->gadget.state;
+	u32 reg;
+	u32 addr;
 
-		/*
-		 * Driver will wait for completion DESCMISS transfer,
-		 * before starts new, not DESCMISS transfer.
-		 */
-		if (!pending_empty && !descmiss_empty) {
-			trace_cdns3_wa2(priv_ep, "wait for pending transfer\n");
-			deferred = 1;
-		}
+	addr = le16_to_cpu(ctrl_req->wValue);
 
-		if (priv_req->flags & REQUEST_INTERNAL)
-			list_add_tail(&priv_req->list,
-				      &priv_ep->wa2_descmiss_req_list);
+	if (addr > DEVICE_ADDRESS_MAX) {
+		dev_err(&usb_ss->dev,
+			"Device address (%d) cannot be greater than %d\n",
+				addr, DEVICE_ADDRESS_MAX);
+		return -EINVAL;
 	}
 
-	return deferred;
-}
-
-static void cdns3_wa2_remove_old_request(struct cdns3_endpoint *priv_ep)
-{
-	struct cdns3_request *priv_req;
+	if (device_state == USB_STATE_CONFIGURED) {
+		dev_err(&usb_ss->dev, "USB device already configured\n");
+		return -EINVAL;
+	}
 
-	while (!list_empty(&priv_ep->wa2_descmiss_req_list)) {
-		u8 chain;
+	reg = cdns_readl(&usb_ss->regs->usb_cmd);
 
-		priv_req = cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list);
-		chain = !!(priv_req->flags & REQUEST_INTERNAL_CH);
+	cdns_writel(&usb_ss->regs->usb_cmd, reg
+			| USB_CMD__FADDR__WRITE(addr)
+			| USB_CMD__SET_ADDR__MASK);
 
-		trace_cdns3_wa2(priv_ep, "removes eldest request");
+	usb_gadget_set_state(&usb_ss->gadget,
+			     (addr ? USB_STATE_ADDRESS : USB_STATE_DEFAULT));
 
-		kfree(priv_req->request.buf);
-		cdns3_gadget_ep_free_request(&priv_ep->endpoint,
-					     &priv_req->request);
-		list_del_init(&priv_req->list);
-		--priv_ep->wa2_counter;
+	cdns_prepare_setup_packet(usb_ss);
 
-		if (!chain)
-			break;
-	}
+	cdns_writel(&usb_ss->regs->ep_cmd,
+		    EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK);
+	return 0;
 }
 
 /**
- * cdns3_wa2_descmissing_packet - handles descriptor missing event.
- * @priv_dev: extended gadget object
+ * cdns_req_ep0_get_status - Handling of GET_STATUS standard USB request
+ * @usb_ss: extended gadget object
+ * @ctrl_req: pointer to received setup packet
  *
- * This function is used only for WA2. For more information see Work around 2
- * description.
+ * Returns 0 if success, error code on error
  */
-static void cdns3_wa2_descmissing_packet(struct cdns3_endpoint *priv_ep)
+static int cdns_req_ep0_get_status(struct usb_ss_dev *usb_ss,
+				   struct usb_ctrlrequest *ctrl_req)
 {
-	struct cdns3_request *priv_req;
-	struct usb_request *request;
+	u16 usb_status = 0;
+	unsigned int length = 2;
+	u32 recip = ctrl_req->bRequestType & USB_RECIP_MASK;
+	u32 reg;
 
-	if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_DET) {
-		priv_ep->flags &= ~EP_QUIRK_EXTRA_BUF_DET;
-		priv_ep->flags |= EP_QUIRK_EXTRA_BUF_EN;
-	}
+	switch (recip) {
+	case USB_RECIP_DEVICE:
+		reg = cdns_readl(&usb_ss->regs->usb_sts);
 
-	trace_cdns3_wa2(priv_ep, "Description Missing detected\n");
+		if (reg & USB_STS__U1ENS__MASK)
+			usb_status |= 1uL << USB_DEV_STAT_U1_ENABLED;
 
-	if (priv_ep->wa2_counter >= CDNS3_WA2_NUM_BUFFERS)
-		cdns3_wa2_remove_old_request(priv_ep);
+		if (reg & USB_STS__U2ENS__MASK)
+			usb_status |= 1uL << USB_DEV_STAT_U2_ENABLED;
 
-	request = cdns3_gadget_ep_alloc_request(&priv_ep->endpoint,
-						GFP_ATOMIC);
-	if (!request)
-		goto err;
+		if (usb_ss->wake_up_flag)
+			usb_status |= 1uL << USB_DEVICE_REMOTE_WAKEUP;
 
-	priv_req = to_cdns3_request(request);
-	priv_req->flags |= REQUEST_INTERNAL;
+		/* self powered */
+		usb_status |= 1uL << USB_DEVICE_SELF_POWERED;
+		break;
 
-	/* if this field is still assigned it indicate that transfer related
-	 * with this request has not been finished yet. Driver in this
-	 * case simply allocate next request and assign flag REQUEST_INTERNAL_CH
-	 * flag to previous one. It will indicate that current request is
-	 * part of the previous one.
-	 */
-	if (priv_ep->descmis_req)
-		priv_ep->descmis_req->flags |= REQUEST_INTERNAL_CH;
+	case USB_RECIP_INTERFACE:
+		return cdns_get_setup_ret(usb_ss, ctrl_req);
 
-	priv_req->request.buf = kzalloc(CDNS3_DESCMIS_BUF_SIZE,
-					GFP_ATOMIC);
-	priv_ep->wa2_counter++;
+	case USB_RECIP_ENDPOINT:
+		/* check if endpoint is stalled */
+		select_ep(usb_ss, ctrl_req->wIndex);
+		if (cdns_readl(&usb_ss->regs->ep_sts)
+			& EP_STS__STALL__MASK)
+			usb_status = 1;
+		break;
 
-	if (!priv_req->request.buf) {
-		cdns3_gadget_ep_free_request(&priv_ep->endpoint, request);
-		goto err;
+	default:
+		return -EINVAL;
 	}
 
-	priv_req->request.length = CDNS3_DESCMIS_BUF_SIZE;
-	priv_ep->descmis_req = priv_req;
-
-	__cdns3_gadget_ep_queue(&priv_ep->endpoint,
-				&priv_ep->descmis_req->request,
-				GFP_ATOMIC);
+	*(u16 *)usb_ss->setup = cpu_to_le16(usb_status);
 
-	return;
-
-err:
-	dev_err(priv_ep->cdns3_dev->dev,
-		"Failed: No sufficient memory for DESCMIS\n");
+	usb_ss->actual_ep0_request = NULL;
+	cdns_ep0_run_transfer(usb_ss, usb_ss->setup_dma, length, 1);
+	return 0;
 }
 
 /**
- * cdns3_gadget_giveback - call struct usb_request's ->complete callback
- * @priv_ep: The endpoint to whom the request belongs to
- * @priv_req: The request we're giving back
- * @status: completion code for the request
+ * cdns_req_ep0_handle_feature -
+ * Handling of GET/SET_FEATURE standard USB request
+ *
+ * @usb_ss: extended gadget object
+ * @ctrl_req: pointer to received setup packet
+ * @set: must be set to 1 for SET_FEATURE request
  *
- * Must be called with controller's lock held and interrupts disabled. This
- * function will unmap @req and call its ->complete() callback to notify upper
- * layers that it has completed.
+ * Returns 0 if success, error code on error
  */
-void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep,
-			   struct cdns3_request *priv_req,
-			   int status)
+static int cdns_req_ep0_handle_feature(struct usb_ss_dev *usb_ss,
+				       struct usb_ctrlrequest *ctrl_req,
+				       int set)
 {
-	struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
-	struct usb_request *request = &priv_req->request;
-
-	list_del_init(&request->list);
-
-	if (request->status == -EINPROGRESS)
-		request->status = status;
-
-	usb_gadget_unmap_request(&priv_dev->gadget, request,
-				 priv_ep->dir);
+	u32 recip = ctrl_req->bRequestType & USB_RECIP_MASK;
+	struct usb_ss_endpoint *usb_ss_ep;
+	u32 reg;
+	u8 tmode = 0;
+
+	switch (recip) {
+	case USB_RECIP_DEVICE:
+
+		switch (ctrl_req->wValue) {
+		case USB_DEVICE_U1_ENABLE:
+			if (usb_ss->gadget.state != USB_STATE_CONFIGURED)
+				return -EINVAL;
+			if (usb_ss->gadget.speed != USB_SPEED_SUPER)
+				return -EINVAL;
+
+			reg = cdns_readl(&usb_ss->regs->usb_conf);
+			if (set)
+				/* set U1EN */
+				reg |= USB_CONF__U1EN__MASK;
+			else
+				/* set U1 disable */
+				reg |= USB_CONF__U1DS__MASK;
+			cdns_writel(&usb_ss->regs->usb_conf, reg);
+			break;
 
-	if ((priv_req->flags & REQUEST_UNALIGNED) &&
-	    priv_ep->dir == USB_DIR_OUT && !request->status)
-		memcpy(request->buf, priv_req->aligned_buf->buf,
-		       request->length);
+		case USB_DEVICE_U2_ENABLE:
+			if (usb_ss->gadget.state != USB_STATE_CONFIGURED)
+				return -EINVAL;
+			if (usb_ss->gadget.speed != USB_SPEED_SUPER)
+				return -EINVAL;
 
-	priv_req->flags &= ~(REQUEST_PENDING | REQUEST_UNALIGNED);
-	trace_cdns3_gadget_giveback(priv_req);
+			reg = cdns_readl(&usb_ss->regs->usb_conf);
+			if (set)
+				/* set U2EN */
+				reg |= USB_CONF__U2EN__MASK;
+			else
+				/* set U2 disable */
+				reg |= USB_CONF__U2DS__MASK;
+			cdns_writel(&usb_ss->regs->usb_conf, reg);
+			break;
 
-	if (priv_dev->dev_ver < DEV_VER_V2) {
-		request = cdns3_wa2_gadget_giveback(priv_dev, priv_ep,
-						    priv_req);
-		if (!request)
-			return;
-	}
+		case USB_DEVICE_A_ALT_HNP_SUPPORT:
+			break;
 
-	if (request->complete) {
-		spin_unlock(&priv_dev->lock);
-		usb_gadget_giveback_request(&priv_ep->endpoint,
-					    request);
-		spin_lock(&priv_dev->lock);
-	}
+		case USB_DEVICE_A_HNP_SUPPORT:
+			break;
 
-	if (request->buf == priv_dev->zlp_buf)
-		cdns3_gadget_ep_free_request(&priv_ep->endpoint, request);
-}
+		case USB_DEVICE_B_HNP_ENABLE:
+			if (!usb_ss->gadget.b_hnp_enable && set)
+				usb_ss->gadget.b_hnp_enable = 1;
+			break;
 
-void cdns3_wa1_restore_cycle_bit(struct cdns3_endpoint *priv_ep)
-{
-	/* Work around for stale data address in TRB*/
-	if (priv_ep->wa1_set) {
-		trace_cdns3_wa1(priv_ep, "restore cycle bit");
-
-		priv_ep->wa1_set = 0;
-		priv_ep->wa1_trb_index = 0xFFFF;
-		if (priv_ep->wa1_cycle_bit) {
-			priv_ep->wa1_trb->control =
-				priv_ep->wa1_trb->control | 0x1;
-		} else {
-			priv_ep->wa1_trb->control =
-				priv_ep->wa1_trb->control & ~0x1;
-		}
-	}
-}
+		case USB_DEVICE_REMOTE_WAKEUP:
+			usb_ss->wake_up_flag = !!set;
+			break;
 
-static void cdns3_free_aligned_request_buf(struct cdns3_device *priv_dev)
-{
-	struct cdns3_aligned_buf *buf, *tmp;
-	unsigned long flags;
+		case USB_DEVICE_TEST_MODE:
+			if (usb_ss->gadget.state != USB_STATE_CONFIGURED)
+				return -EINVAL;
+			if (usb_ss->gadget.speed != USB_SPEED_HIGH &&
+			    usb_ss->gadget.speed != USB_SPEED_FULL)
+				return -EINVAL;
+			if (ctrl_req->wLength != 0 ||
+			    ctrl_req->bRequestType & USB_DIR_IN) {
+				dev_err(&usb_ss->dev, "req is error\n");
+				return -EINVAL;
+			}
+			tmode = le16_to_cpu(ctrl_req->wIndex) >> 8;
+			switch (tmode) {
+			case TEST_J:
+			case TEST_K:
+			case TEST_SE0_NAK:
+			case TEST_PACKET:
+				reg = cdns_readl(&usb_ss->regs->usb_cmd);
+				tmode -= 1;
+				reg |= USB_CMD__STMODE |
+					USB_CMD__TMODE_SEL(tmode);
+				cdns_writel(&usb_ss->regs->usb_cmd, reg);
+				dev_info(&usb_ss->dev,
+					 "set test mode, val=0x%x", reg);
+				break;
+			default:
+				return -EINVAL;
+			}
+			break;
 
-	spin_lock_irqsave(&priv_dev->lock, flags);
-
-	list_for_each_entry_safe(buf, tmp, &priv_dev->aligned_buf_list, list) {
-		if (!buf->in_use) {
-			list_del(&buf->list);
-
-			/*
-			 * Re-enable interrupts to free DMA capable memory.
-			 * Driver can't free this memory with disabled
-			 * interrupts.
-			 */
-			spin_unlock_irqrestore(&priv_dev->lock, flags);
-			dma_free_coherent(buf->buf);
-			kfree(buf);
-			spin_lock_irqsave(&priv_dev->lock, flags);
+		default:
+			return -EINVAL;
 		}
-	}
-
-	spin_unlock_irqrestore(&priv_dev->lock, flags);
-}
+		break;
 
-static int cdns3_prepare_aligned_request_buf(struct cdns3_request *priv_req)
-{
-	struct cdns3_endpoint *priv_ep = priv_req->priv_ep;
-	struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
-	struct cdns3_aligned_buf *buf;
+	case USB_RECIP_INTERFACE:
+		return cdns_get_setup_ret(usb_ss, ctrl_req);
 
-	/* check if buffer is aligned to 8. */
-	if (!((uintptr_t)priv_req->request.buf & 0x7))
-		return 0;
+	case USB_RECIP_ENDPOINT:
+		select_ep(usb_ss, ctrl_req->wIndex);
+		u8 ep_index = CAST_EP_ADDR_TO_INDEX(ctrl_req->wIndex);
 
-	buf = priv_req->aligned_buf;
+		if (set) {
+			/* set stall */
+			cdns_writel(&usb_ss->regs->ep_cmd,
+				      EP_CMD__SSTALL__MASK);
 
-	if (!buf || priv_req->request.length > buf->size) {
-		buf = kzalloc(sizeof(*buf), GFP_ATOMIC);
-		if (!buf)
-			return -ENOMEM;
-
-		buf->size = priv_req->request.length;
+			/* handle non zero endpoint software endpoint */
+			if (ctrl_req->wIndex & 0x7F) {
+				usb_ss_ep = usb_ss->eps[ep_index];
+				usb_ss_ep->stalled_flag = 1;
+			}
+		} else {
+			struct usb_request *request;
 
-		buf->buf = dma_alloc_coherent(buf->size,
-					      (unsigned long *)&buf->dma);
-		if (!buf->buf) {
-			kfree(buf);
-			return -ENOMEM;
-		}
+			if (ctrl_req->wIndex & 0x7F) {
+				if (usb_ss->eps[ep_index]->wedge_flag)
+					goto jmp_wedge;
+			}
 
-		if (priv_req->aligned_buf) {
-			trace_cdns3_free_aligned_request(priv_req);
-			priv_req->aligned_buf->in_use = 0;
-#ifndef __UBOOT__
-			queue_work(system_freezable_wq,
-				   &priv_dev->aligned_buf_wq);
-#else
-			cdns3_free_aligned_request_buf(priv_dev);
-#endif
+			/* clear stall */
+			cdns_writel(&usb_ss->regs->ep_cmd,
+				    EP_CMD__CSTALL__MASK |
+				    EP_CMD__EPRST__MASK);
+			/* wait for EPRST cleared */
+			while (cdns_readl(&usb_ss->regs->ep_cmd)
+					& EP_CMD__EPRST__MASK)
+				;
+
+			/* handle non zero endpoint software endpoint */
+			if (ctrl_req->wIndex & 0x7F) {
+				usb_ss_ep = usb_ss->eps[ep_index];
+				usb_ss_ep->stalled_flag = 0;
+
+				request =
+				    next_request(&usb_ss_ep->request_list);
+				if (request)
+					cdns_ep_run_transfer(usb_ss_ep);
+			}
 		}
+jmp_wedge:
+		select_ep(usb_ss, 0x00);
+		break;
 
-		buf->in_use = 1;
-		priv_req->aligned_buf = buf;
-
-		list_add_tail(&buf->list,
-			      &priv_dev->aligned_buf_list);
-	}
-
-	if (priv_ep->dir == USB_DIR_IN) {
-		memcpy(buf->buf, priv_req->request.buf,
-		       priv_req->request.length);
+	default:
+		return -EINVAL;
 	}
 
-	priv_req->flags |= REQUEST_UNALIGNED;
-	trace_cdns3_prepare_aligned_request(priv_req);
+	cdns_writel(&usb_ss->regs->ep_cmd,
+		    EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK);
 
 	return 0;
 }
 
-static int cdns3_wa1_update_guard(struct cdns3_endpoint *priv_ep,
-				  struct cdns3_trb *trb)
+/**
+ * cdns_req_ep0_set_sel - Handling of SET_SEL standard USB request
+ * @usb_ss: extended gadget object
+ * @ctrl_req: pointer to received setup packet
+ *
+ * Returns 0 if success, error code on error
+ */
+static int cdns_req_ep0_set_sel(struct usb_ss_dev *usb_ss,
+				struct usb_ctrlrequest *ctrl_req)
 {
-	struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
+	if (usb_ss->gadget.state < USB_STATE_ADDRESS)
+		return -EINVAL;
 
-	if (!priv_ep->wa1_set) {
-		u32 doorbell;
+	if (ctrl_req->wLength != 6) {
+		dev_err(&usb_ss->dev, "Set SEL should be 6 bytes, got %d\n",
+			ctrl_req->wLength);
+		return -EINVAL;
+	}
 
-		doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
+	usb_ss->ep0_data_dir = 0;
+	usb_ss->actual_ep0_request = NULL;
+	cdns_ep0_run_transfer(usb_ss, usb_ss->setup_dma, 6, 1);
 
-		if (doorbell) {
-			priv_ep->wa1_cycle_bit = priv_ep->pcs ? TRB_CYCLE : 0;
-			priv_ep->wa1_set = 1;
-			priv_ep->wa1_trb = trb;
-			priv_ep->wa1_trb_index = priv_ep->enqueue;
-			trace_cdns3_wa1(priv_ep, "set guard");
-			return 0;
-		}
-	}
-	return 1;
+	return 0;
 }
 
-static void cdns3_wa1_tray_restore_cycle_bit(struct cdns3_device *priv_dev,
-					     struct cdns3_endpoint *priv_ep)
+/**
+ * cdns_req_ep0_set_isoch_delay -
+ * Handling of GET_ISOCH_DELAY standard USB request
+ * @usb_ss: extended gadget object
+ * @ctrl_req: pointer to received setup packet
+ *
+ * Returns 0 if success, error code on error
+ */
+static int cdns_req_ep0_set_isoch_delay(struct usb_ss_dev *usb_ss,
+					struct usb_ctrlrequest *ctrl_req)
 {
-	int dma_index;
-	u32 doorbell;
-
-	doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
-	dma_index = cdns3_get_dma_pos(priv_dev, priv_ep);
+	if (ctrl_req->wIndex || ctrl_req->wLength)
+		return -EINVAL;
 
-	if (!doorbell || dma_index != priv_ep->wa1_trb_index)
-		cdns3_wa1_restore_cycle_bit(priv_ep);
+	usb_ss->isoch_delay = ctrl_req->wValue;
+	cdns_writel(&usb_ss->regs->ep_cmd,
+		    EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK);
+	return 0;
 }
 
 /**
- * cdns3_ep_run_transfer - start transfer on no-default endpoint hardware
- * @priv_ep: endpoint object
+ * cdns_req_ep0_set_configuration - Handling of SET_CONFIG standard USB request
+ * @usb_ss: extended gadget object
+ * @ctrl_req: pointer to received setup packet
  *
- * Returns zero on success or negative value on failure
+ * Returns 0 if success, 0x7FFF on deferred status stage, error code on error
  */
-int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep,
-			  struct usb_request *request)
+static int cdns_req_ep0_set_configuration(struct usb_ss_dev *usb_ss,
+					  struct usb_ctrlrequest *ctrl_req)
 {
-	struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
-	struct cdns3_request *priv_req;
-	struct cdns3_trb *trb;
-	dma_addr_t trb_dma;
-	u32 togle_pcs = 1;
-	int sg_iter = 0;
-	int num_trb = 1;
-	int address;
-	u32 control;
-	int pcs;
-
-	if (num_trb > priv_ep->free_trbs) {
-		priv_ep->flags |= EP_RING_FULL;
-		return -ENOBUFS;
-	}
-
-	priv_req = to_cdns3_request(request);
-	address = priv_ep->endpoint.desc->bEndpointAddress;
-
-	priv_ep->flags |= EP_PENDING_REQUEST;
-
-	/* must allocate buffer aligned to 8 */
-	if (priv_req->flags & REQUEST_UNALIGNED)
-		trb_dma = priv_req->aligned_buf->dma;
-	else
-		trb_dma = request->dma;
-
-	trb = priv_ep->trb_pool + priv_ep->enqueue;
-	priv_req->start_trb = priv_ep->enqueue;
-	priv_req->trb = trb;
-
-	cdns3_select_ep(priv_ep->cdns3_dev, address);
-
-	/* prepare ring */
-	if ((priv_ep->enqueue + num_trb)  >= (priv_ep->num_trbs - 1)) {
-		struct cdns3_trb *link_trb;
-		int doorbell, dma_index;
-		u32 ch_bit = 0;
-
-		doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
-		dma_index = cdns3_get_dma_pos(priv_dev, priv_ep);
-
-		/* Driver can't update LINK TRB if it is current processed. */
-		if (doorbell && dma_index == priv_ep->num_trbs - 1) {
-			priv_ep->flags |= EP_DEFERRED_DRDY;
-			return -ENOBUFS;
+	enum usb_device_state device_state = usb_ss->gadget.state;
+	u32 config = le16_to_cpu(ctrl_req->wValue);
+	struct usb_ep *ep;
+	struct usb_ss_endpoint *usb_ss_ep, *temp_ss_ep;
+	int i, result = 0;
+
+	switch (device_state) {
+	case USB_STATE_ADDRESS:
+		/* Configure non-control EPs */
+		list_for_each_entry_safe(usb_ss_ep, temp_ss_ep,
+					 &usb_ss->ep_match_list,
+					 ep_match_pending_list) {
+			cdns_ep_config(usb_ss_ep);
+			list_del(&usb_ss_ep->ep_match_pending_list);
 		}
 
-		/*updating C bt in  Link TRB before starting DMA*/
-		link_trb = priv_ep->trb_pool + (priv_ep->num_trbs - 1);
-		/*
-		 * For TRs size equal 2 enabling TRB_CHAIN for epXin causes
-		 * that DMA stuck at the LINK TRB.
-		 * On the other hand, removing TRB_CHAIN for longer TRs for
-		 * epXout cause that DMA stuck after handling LINK TRB.
-		 * To eliminate this strange behavioral driver set TRB_CHAIN
-		 * bit only for TR size > 2.
-		 */
-		if (priv_ep->type == USB_ENDPOINT_XFER_ISOC ||
-		    TRBS_PER_SEGMENT > 2)
-			ch_bit = TRB_CHAIN;
-
-		link_trb->control = ((priv_ep->pcs) ? TRB_CYCLE : 0) |
-				    TRB_TYPE(TRB_LINK) | TRB_TOGGLE | ch_bit;
-	}
-
-	if (priv_dev->dev_ver <= DEV_VER_V2)
-		togle_pcs = cdns3_wa1_update_guard(priv_ep, trb);
-
-	/* set incorrect Cycle Bit for first trb*/
-	control = priv_ep->pcs ? 0 : TRB_CYCLE;
-
-	do {
-		u32 length;
-		u16 td_size = 0;
-
-		/* fill TRB */
-		control |= TRB_TYPE(TRB_NORMAL);
-		trb->buffer = TRB_BUFFER(trb_dma);
-
-		length = request->length;
-
-		if (likely(priv_dev->dev_ver >= DEV_VER_V2))
-			td_size = DIV_ROUND_UP(length,
-					       priv_ep->endpoint.maxpacket);
+		list_for_each_entry(ep, &usb_ss->gadget.ep_list, ep_list) {
+			usb_ss_ep = to_usb_ss_ep(ep);
+			if (usb_ss_ep->used)
+				cdns_ep_config(usb_ss_ep);
+		}
 
-		trb->length = TRB_BURST_LEN(priv_ep->trb_burst_size) |
-					TRB_LEN(length);
-		if (priv_dev->gadget.speed == USB_SPEED_SUPER)
-			trb->length |= TRB_TDL_SS_SIZE(td_size);
-		else
-			control |= TRB_TDL_HS_SIZE(td_size);
+		result = cdns_get_setup_ret(usb_ss, ctrl_req);
+
+		if (result != 0)
+			return result;
+
+		if (config) {
+			if (!usb_ss->hw_configured_flag) {
+				/* SET CONFIGURATION */
+				cdns_writel(&usb_ss->regs->usb_conf,
+					    USB_CONF__CFGSET__MASK);
+				cdns_writel(&usb_ss->regs->ep_cmd,
+					    EP_CMD__ERDY__MASK |
+					    EP_CMD__REQ_CMPL__MASK);
+				/* wait until configuration set */
+				while (!(cdns_readl(&usb_ss->regs->usb_sts)
+				       & USB_STS__CFGSTS__MASK))
+					;
+				usb_ss->hw_configured_flag = 1;
+
+				list_for_each_entry(ep, &usb_ss->gadget.ep_list,
+						    ep_list) {
+					usb_ss_ep = to_usb_ss_ep(ep);
+					if (usb_ss_ep->enabled)
+						cdns_ep_run_transfer(usb_ss_ep);
+				}
+			}
 
-		pcs = priv_ep->pcs ? TRB_CYCLE : 0;
+			usb_gadget_set_state(&usb_ss->gadget,
+					     USB_STATE_CONFIGURED);
 
-		/*
-		 * first trb should be prepared as last to avoid processing
-		 *  transfer to early
-		 */
-		if (sg_iter != 0)
-			control |= pcs;
-
-		if (priv_ep->type == USB_ENDPOINT_XFER_ISOC  && !priv_ep->dir) {
-			control |= TRB_IOC | TRB_ISP;
 		} else {
-			/* for last element in TD or in SG list */
-			if (sg_iter == (num_trb - 1) && sg_iter != 0)
-				control |= pcs | TRB_IOC | TRB_ISP;
+			cdns_gadget_unconfig(usb_ss);
+			for (i = 0; i < usb_ss->ep_nums; i++)
+				usb_ss->eps[i]->enabled = 0;
+			usb_gadget_set_state(&usb_ss->gadget,
+					     USB_STATE_ADDRESS);
 		}
+		break;
 
-		if (sg_iter)
-			trb->control = control;
-		else
-			priv_req->trb->control = control;
-
-		control = 0;
-		++sg_iter;
-		priv_req->end_trb = priv_ep->enqueue;
-		cdns3_ep_inc_enq(priv_ep);
-		trb = priv_ep->trb_pool + priv_ep->enqueue;
-	} while (sg_iter < num_trb);
-
-	trb = priv_req->trb;
-
-	priv_req->flags |= REQUEST_PENDING;
-
-	if (sg_iter == 1)
-		trb->control |= TRB_IOC | TRB_ISP;
-
-	/*
-	 * Memory barrier - cycle bit must be set before other filds in trb.
-	 */
-	dmb();
-
-	/* give the TD to the consumer*/
-	if (togle_pcs)
-		trb->control =  trb->control ^ 1;
-
-	if (priv_dev->dev_ver <= DEV_VER_V2)
-		cdns3_wa1_tray_restore_cycle_bit(priv_dev, priv_ep);
-
-	trace_cdns3_prepare_trb(priv_ep, priv_req->trb);
-
-	/*
-	 * Memory barrier - Cycle Bit must be set before trb->length  and
-	 * trb->buffer fields.
-	 */
-	dmb();
-
-	/*
-	 * For DMULT mode we can set address to transfer ring only once after
-	 * enabling endpoint.
-	 */
-	if (priv_ep->flags & EP_UPDATE_EP_TRBADDR) {
-		/*
-		 * Until SW is not ready to handle the OUT transfer the ISO OUT
-		 * Endpoint should be disabled (EP_CFG.ENABLE = 0).
-		 * EP_CFG_ENABLE must be set before updating ep_traddr.
-		 */
-		if (priv_ep->type == USB_ENDPOINT_XFER_ISOC  && !priv_ep->dir &&
-		    !(priv_ep->flags & EP_QUIRK_ISO_OUT_EN)) {
-			priv_ep->flags |= EP_QUIRK_ISO_OUT_EN;
-			cdns3_set_register_bit(&priv_dev->regs->ep_cfg,
-					       EP_CFG_ENABLE);
+	case USB_STATE_CONFIGURED:
+		result = cdns_get_setup_ret(usb_ss, ctrl_req);
+		if (!config && !result) {
+			cdns_gadget_unconfig(usb_ss);
+			for (i = 0; i < usb_ss->ep_nums; i++)
+				usb_ss->eps[i]->enabled = 0;
+			usb_gadget_set_state(&usb_ss->gadget,
+					     USB_STATE_ADDRESS);
 		}
+		break;
 
-		writel(EP_TRADDR_TRADDR(priv_ep->trb_pool_dma +
-					priv_req->start_trb * TRB_SIZE),
-					&priv_dev->regs->ep_traddr);
-
-		priv_ep->flags &= ~EP_UPDATE_EP_TRBADDR;
-	}
-
-	if (!priv_ep->wa1_set && !(priv_ep->flags & EP_STALLED)) {
-		trace_cdns3_ring(priv_ep);
-		/*clearing TRBERR and EP_STS_DESCMIS before seting DRDY*/
-		writel(EP_STS_TRBERR | EP_STS_DESCMIS, &priv_dev->regs->ep_sts);
-		writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd);
-		trace_cdns3_doorbell_epx(priv_ep->name,
-					 readl(&priv_dev->regs->ep_traddr));
+	default:
+		result = -EINVAL;
 	}
 
-	/* WORKAROUND for transition to L0 */
-	__cdns3_gadget_wakeup(priv_dev);
+	return result;
+}
 
-	return 0;
+/**
+ * cdns_ep0_standard_request - Handling standard USB requests
+ * @usb_ss: extended gadget object
+ * @ctrl_req: pointer to received setup packet
+ *
+ * Returns 0 if success, error code on error
+ */
+static int cdns_ep0_standard_request(struct usb_ss_dev *usb_ss,
+				     struct usb_ctrlrequest *ctrl_req)
+{
+	switch (ctrl_req->bRequest) {
+	case USB_REQ_SET_ADDRESS:
+		return cdns_req_ep0_set_address(usb_ss, ctrl_req);
+	case USB_REQ_SET_CONFIGURATION:
+		return cdns_req_ep0_set_configuration(usb_ss, ctrl_req);
+	case USB_REQ_GET_STATUS:
+		return cdns_req_ep0_get_status(usb_ss, ctrl_req);
+	case USB_REQ_CLEAR_FEATURE:
+		return cdns_req_ep0_handle_feature(usb_ss, ctrl_req, 0);
+	case USB_REQ_SET_FEATURE:
+		return cdns_req_ep0_handle_feature(usb_ss, ctrl_req, 1);
+	case USB_REQ_SET_SEL:
+		return cdns_req_ep0_set_sel(usb_ss, ctrl_req);
+	case USB_REQ_SET_ISOCH_DELAY:
+		return cdns_req_ep0_set_isoch_delay(usb_ss, ctrl_req);
+	default:
+		return cdns_get_setup_ret(usb_ss, ctrl_req);
+	}
 }
 
-void cdns3_set_hw_configuration(struct cdns3_device *priv_dev)
+/**
+ * cdns_ep0_setup_phase - Handling setup USB requests
+ * @usb_ss: extended gadget object
+ */
+static void cdns_ep0_setup_phase(struct usb_ss_dev *usb_ss)
 {
-	struct cdns3_endpoint *priv_ep;
-	struct usb_ep *ep;
-	int val;
-
-	if (priv_dev->hw_configured_flag)
-		return;
-
-	writel(USB_CONF_CFGSET, &priv_dev->regs->usb_conf);
-	writel(EP_CMD_ERDY | EP_CMD_REQ_CMPL, &priv_dev->regs->ep_cmd);
+	int result;
+	struct usb_ctrlrequest *ctrl_req =
+			(struct usb_ctrlrequest *)usb_ss->setup;
 
-	cdns3_set_register_bit(&priv_dev->regs->usb_conf,
-			       USB_CONF_U1EN | USB_CONF_U2EN);
-
-	/* wait until configuration set */
-	readl_poll_timeout_atomic(&priv_dev->regs->usb_sts, val,
-				  val & USB_STS_CFGSTS_MASK, 100);
+	if ((ctrl_req->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
+		result = cdns_ep0_standard_request(usb_ss, ctrl_req);
+	else
+		result = cdns_get_setup_ret(usb_ss, ctrl_req);
 
-	priv_dev->hw_configured_flag = 1;
+	if (result != 0 && result != USB_GADGET_DELAYED_STATUS) {
+		dev_dbg(&usb_ss->dev, "STALL(00) %d\n", result);
 
-	list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) {
-		priv_ep = ep_to_cdns3_ep(ep);
-		if (priv_ep->flags & EP_ENABLED)
-			cdns3_start_all_request(priv_dev, priv_ep);
+		/* set_stall on ep0 */
+		select_ep(usb_ss, 0x00);
+		cdns_writel(&usb_ss->regs->ep_cmd,
+			    EP_CMD__SSTALL__MASK);
+		cdns_writel(&usb_ss->regs->ep_cmd,
+			    EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK);
+		return;
 	}
 }
 
 /**
- * cdns3_request_handled - check whether request has been handled by DMA
- *
- * @priv_ep: extended endpoint object.
- * @priv_req: request object for checking
- *
- * Endpoint must be selected before invoking this function.
+ * cdns_check_ep_interrupt_proceed - Processes interrupt related to endpoint
+ * @usb_ss_ep: extended endpoint object
  *
- * Returns false if request has not been handled by DMA, else returns true.
- *
- * SR - start ring
- * ER -  end ring
- * DQ = priv_ep->dequeue - dequeue position
- * EQ = priv_ep->enqueue -  enqueue position
- * ST = priv_req->start_trb - index of first TRB in transfer ring
- * ET = priv_req->end_trb - index of last TRB in transfer ring
- * CI = current_index - index of processed TRB by DMA.
- *
- * As first step, function checks if cycle bit for priv_req->start_trb is
- * correct.
- *
- * some rules:
- * 1. priv_ep->dequeue never exceed current_index.
- * 2  priv_ep->enqueue never exceed priv_ep->dequeue
- * 3. exception: priv_ep->enqueue == priv_ep->dequeue
- *    and priv_ep->free_trbs is zero.
- *    This case indicate that TR is full.
- *
- * Then We can split recognition into two parts:
- * Case 1 - priv_ep->dequeue < current_index
- *      SR ... EQ ... DQ ... CI ... ER
- *      SR ... DQ ... CI ... EQ ... ER
- *
- *      Request has been handled by DMA if ST and ET is between DQ and CI.
- *
- * Case 2 - priv_ep->dequeue > current_index
- * This situation take place when CI go through the LINK TRB at the end of
- * transfer ring.
- *      SR ... CI ... EQ ... DQ ... ER
- *
- *      Request has been handled by DMA if ET is less then CI or
- *      ET is greater or equal DQ.
+ * Returns 0
  */
-static bool cdns3_request_handled(struct cdns3_endpoint *priv_ep,
-				  struct cdns3_request *priv_req)
+static int cdns_check_ep_interrupt_proceed(struct usb_ss_endpoint *usb_ss_ep)
 {
-	struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
-	struct cdns3_trb *trb = priv_req->trb;
-	int current_index = 0;
-	int handled = 0;
-	int doorbell;
-
-	current_index = cdns3_get_dma_pos(priv_dev, priv_ep);
-	doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY);
+	struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss;
+	struct usb_request *request;
+	u32 ep_sts_reg;
 
-	trb = &priv_ep->trb_pool[priv_req->start_trb];
+	select_ep(usb_ss, usb_ss_ep->address);
+	ep_sts_reg = cdns_readl(&usb_ss->regs->ep_sts);
 
-	if ((trb->control  & TRB_CYCLE) != priv_ep->ccs)
-		goto finish;
+	dev_dbg(&usb_ss->dev, "EP_STS: %08X\n", ep_sts_reg);
 
-	if (doorbell == 1 && current_index == priv_ep->dequeue)
-		goto finish;
+	if (ep_sts_reg & EP_STS__TRBERR__MASK) {
+		cdns_writel(&usb_ss->regs->ep_sts, EP_STS__TRBERR__MASK);
 
-	/* The corner case for TRBS_PER_SEGMENT equal 2). */
-	if (TRBS_PER_SEGMENT == 2 && priv_ep->type != USB_ENDPOINT_XFER_ISOC) {
-		handled = 1;
-		goto finish;
+		dev_dbg(&usb_ss->dev, "TRBERR(%02X)\n",
+			usb_ss_ep->endpoint.desc->bEndpointAddress);
 	}
 
-	if (priv_ep->enqueue == priv_ep->dequeue &&
-	    priv_ep->free_trbs == 0) {
-		handled = 1;
-	} else if (priv_ep->dequeue < current_index) {
-		if ((current_index == (priv_ep->num_trbs - 1)) &&
-		    !priv_ep->dequeue)
-			goto finish;
-
-		if (priv_req->end_trb >= priv_ep->dequeue &&
-		    priv_req->end_trb < current_index)
-			handled = 1;
-	} else if (priv_ep->dequeue  > current_index) {
-		if (priv_req->end_trb  < current_index ||
-		    priv_req->end_trb >= priv_ep->dequeue)
-			handled = 1;
+	if (ep_sts_reg & EP_STS__ISOERR__MASK) {
+		cdns_writel(&usb_ss->regs->ep_sts, EP_STS__ISOERR__MASK);
+		dev_dbg(&usb_ss->dev, "ISOERR(%02X)\n",
+			usb_ss_ep->endpoint.desc->bEndpointAddress);
 	}
 
-finish:
-	trace_cdns3_request_handled(priv_req, current_index, handled);
-
-	return handled;
-}
-
-static void cdns3_transfer_completed(struct cdns3_device *priv_dev,
-				     struct cdns3_endpoint *priv_ep)
-{
-	struct cdns3_request *priv_req;
-	struct usb_request *request;
-	struct cdns3_trb *trb;
-
-	while (!list_empty(&priv_ep->pending_req_list)) {
-		request = cdns3_next_request(&priv_ep->pending_req_list);
-		priv_req = to_cdns3_request(request);
+	if (ep_sts_reg & EP_STS__OUTSMM__MASK) {
+		cdns_writel(&usb_ss->regs->ep_sts, EP_STS__OUTSMM__MASK);
+		dev_dbg(&usb_ss->dev, "OUTSMM(%02X)\n",
+			usb_ss_ep->endpoint.desc->bEndpointAddress);
+	}
 
-		/* Re-select endpoint. It could be changed by other CPU during
-		 * handling usb_gadget_giveback_request.
-		 */
-#ifndef __UBOOT__
-		cdns3_select_ep(priv_dev, priv_ep->endpoint.address);
-#else
-		cdns3_select_ep(priv_dev,
-				priv_ep->endpoint.desc->bEndpointAddress);
-#endif
+	if (ep_sts_reg & EP_STS__NRDY__MASK) {
+		cdns_writel(&usb_ss->regs->ep_sts, EP_STS__NRDY__MASK);
+		dev_dbg(&usb_ss->dev, "NRDY(%02X)\n",
+			usb_ss_ep->endpoint.desc->bEndpointAddress);
+	}
 
-		if (!cdns3_request_handled(priv_ep, priv_req))
-			goto prepare_next_td;
+	if ((ep_sts_reg & EP_STS__IOC__MASK) ||
+	    (ep_sts_reg & EP_STS__ISP__MASK)) {
+		u8 ep_dir;
 
-		trb = priv_ep->trb_pool + priv_ep->dequeue;
-		trace_cdns3_complete_trb(priv_ep, trb);
+		cdns_flush_cache((uintptr_t)usb_ss_ep->trb_pool,
+				 sizeof(struct usb_ss_trb));
 
-		if (trb != priv_req->trb)
-			dev_warn(priv_dev->dev,
-				 "request_trb=0x%p, queue_trb=0x%p\n",
-				 priv_req->trb, trb);
+		cdns_writel(&usb_ss->regs->ep_sts,
+			    EP_STS__IOC__MASK | EP_STS__ISP__MASK);
 
-		request->actual = TRB_LEN(le32_to_cpu(trb->length));
-		cdns3_move_deq_to_next_trb(priv_req);
-		cdns3_gadget_giveback(priv_ep, priv_req, 0);
+		/* get just completed request */
+		request = next_request(&usb_ss_ep->request_list);
+		ep_dir = usb_ss_ep->endpoint.desc->bEndpointAddress;
+		cdns_flush_cache((uintptr_t)request->dma, request->length);
+		usb_gadget_unmap_request(&usb_ss->gadget, request,
+					 ep_dir & ENDPOINT_DIR_MASK);
 
-		if (priv_ep->type != USB_ENDPOINT_XFER_ISOC &&
-		    TRBS_PER_SEGMENT == 2)
-			break;
-	}
-	priv_ep->flags &= ~EP_PENDING_REQUEST;
+		request->status = 0;
+		request->actual =
+			le32_to_cpu(((u32 *)usb_ss_ep->trb_pool)[1])
+			& ACTUAL_TRANSFERRED_BYTES_MASK;
 
-prepare_next_td:
-	if (!(priv_ep->flags & EP_STALLED) &&
-	    !(priv_ep->flags & EP_STALL_PENDING))
-		cdns3_start_all_request(priv_dev, priv_ep);
-}
+		dev_dbg(&usb_ss->dev, "IOC(%02X) %d\n",
+			usb_ss_ep->endpoint.desc->bEndpointAddress,
+			request->actual);
 
-void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm)
-{
-	struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
+		list_del(&request->list);
 
-	cdns3_wa1_restore_cycle_bit(priv_ep);
+		usb_ss_ep->hw_pending_flag = 0;
+		if (request->complete) {
+			spin_unlock(&usb_ss->lock);
+			usb_gadget_giveback_request(&usb_ss_ep->endpoint,
+						    request);
+			spin_lock(&usb_ss->lock);
+		}
 
-	if (rearm) {
-		trace_cdns3_ring(priv_ep);
+		/* handle deferred STALL */
+		if (usb_ss_ep->stalled_flag) {
+			cdns_ep_stall_flush(usb_ss_ep);
+			return 0;
+		}
 
-		/* Cycle Bit must be updated before arming DMA. */
-		dmb();
-		writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd);
+		/* exit if hardware transfer already started */
+		if (usb_ss_ep->hw_pending_flag)
+			return 0;
 
-		__cdns3_gadget_wakeup(priv_dev);
+		/* if any request queued run it! */
+		if (!list_empty(&usb_ss_ep->request_list))
+			cdns_ep_run_transfer(usb_ss_ep);
+	}
 
-		trace_cdns3_doorbell_epx(priv_ep->name,
-					 readl(&priv_dev->regs->ep_traddr));
+	if (ep_sts_reg & EP_STS__DESCMIS__MASK) {
+		cdns_writel(&usb_ss->regs->ep_sts, EP_STS__DESCMIS__MASK);
+		dev_dbg(&usb_ss->dev, "DESCMIS(%02X)\n",
+			usb_ss_ep->endpoint.desc->bEndpointAddress);
 	}
+
+	return 0;
 }
 
 /**
- * cdns3_check_ep_interrupt_proceed - Processes interrupt related to endpoint
- * @priv_ep: endpoint object
- *
- * Returns 0
+ * cdns_check_ep0_interrupt_proceed - Processes interrupt related to endpoint 0
+ * @usb_ss: extended gadget object
+ * @dir: 1 for IN direction, 0 for OUT direction
  */
-static int cdns3_check_ep_interrupt_proceed(struct cdns3_endpoint *priv_ep)
+static void cdns_check_ep0_interrupt_proceed(struct usb_ss_dev *usb_ss, int dir)
 {
-	struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
 	u32 ep_sts_reg;
+	int i;
 
-#ifndef __UBOOT__
-	cdns3_select_ep(priv_dev, priv_ep->endpoint.address);
-#else
-	cdns3_select_ep(priv_dev, priv_ep->endpoint.desc->bEndpointAddress);
-#endif
-
-	trace_cdns3_epx_irq(priv_dev, priv_ep);
+	select_ep(usb_ss, 0 | (dir ? USB_DIR_IN : USB_DIR_OUT));
+	ep_sts_reg = cdns_readl(&usb_ss->regs->ep_sts);
 
-	ep_sts_reg = readl(&priv_dev->regs->ep_sts);
-	writel(ep_sts_reg, &priv_dev->regs->ep_sts);
+	dev_dbg(&usb_ss->dev, "EP_STS: %08X\n", ep_sts_reg);
 
-	if (ep_sts_reg & EP_STS_TRBERR) {
-		if (priv_ep->flags & EP_STALL_PENDING &&
-		    !(ep_sts_reg & EP_STS_DESCMIS &&
-		    priv_dev->dev_ver < DEV_VER_V2)) {
-			cdns3_ep_stall_flush(priv_ep);
-		}
+	if ((ep_sts_reg & EP_STS__SETUP__MASK) && dir == 0) {
+		cdns_flush_cache((uintptr_t)usb_ss->setup, 8);
 
-		/*
-		 * For isochronous transfer driver completes request on
-		 * IOC or on TRBERR. IOC appears only when device receive
-		 * OUT data packet. If host disable stream or lost some packet
-		 * then the only way to finish all queued transfer is to do it
-		 * on TRBERR event.
-		 */
-		if (priv_ep->type == USB_ENDPOINT_XFER_ISOC &&
-		    !priv_ep->wa1_set) {
-			if (!priv_ep->dir) {
-				u32 ep_cfg = readl(&priv_dev->regs->ep_cfg);
-
-				ep_cfg &= ~EP_CFG_ENABLE;
-				writel(ep_cfg, &priv_dev->regs->ep_cfg);
-				priv_ep->flags &= ~EP_QUIRK_ISO_OUT_EN;
-			}
-			cdns3_transfer_completed(priv_dev, priv_ep);
-		} else if (!(priv_ep->flags & EP_STALLED) &&
-			  !(priv_ep->flags & EP_STALL_PENDING)) {
-			if (priv_ep->flags & EP_DEFERRED_DRDY) {
-				priv_ep->flags &= ~EP_DEFERRED_DRDY;
-				cdns3_start_all_request(priv_dev, priv_ep);
-			} else {
-				cdns3_rearm_transfer(priv_ep,
-						     priv_ep->wa1_set);
-			}
-		}
-	}
+		dev_dbg(&usb_ss->dev, "SETUP(%02X)\n", 0x00);
 
-	if ((ep_sts_reg & EP_STS_IOC) || (ep_sts_reg & EP_STS_ISP)) {
-		if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN) {
-			if (ep_sts_reg & EP_STS_ISP)
-				priv_ep->flags |= EP_QUIRK_END_TRANSFER;
-			else
-				priv_ep->flags &= ~EP_QUIRK_END_TRANSFER;
-		}
+		cdns_writel(&usb_ss->regs->ep_sts,
+			    EP_STS__SETUP__MASK |
+			    EP_STS__IOC__MASK | EP_STS__ISP__MASK);
 
-		cdns3_transfer_completed(priv_dev, priv_ep);
+		dev_dbg(&usb_ss->dev, "SETUP: ");
+		for (i = 0; i < 8; i++)
+			dev_dbg(&usb_ss->dev, "%02X ", usb_ss->setup[i]);
+		dev_dbg(&usb_ss->dev, "\nSTATE: %d\n", usb_ss->gadget.state);
+		usb_ss->ep0_data_dir = usb_ss->setup[0] & USB_DIR_IN;
+		cdns_ep0_setup_phase(usb_ss);
+		ep_sts_reg &= ~(EP_STS__SETUP__MASK |
+			EP_STS__IOC__MASK |
+			EP_STS__ISP__MASK);
 	}
 
-	/*
-	 * WA2: this condition should only be meet when
-	 * priv_ep->flags & EP_QUIRK_EXTRA_BUF_DET or
-	 * priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN.
-	 * In other cases this interrupt will be disabled/
-	 */
-	if (ep_sts_reg & EP_STS_DESCMIS && priv_dev->dev_ver < DEV_VER_V2 &&
-	    !(priv_ep->flags & EP_STALLED))
-		cdns3_wa2_descmissing_packet(priv_ep);
-
-	return 0;
-}
-
-static void cdns3_disconnect_gadget(struct cdns3_device *priv_dev)
-{
-	if (priv_dev->gadget_driver && priv_dev->gadget_driver->disconnect) {
-		spin_unlock(&priv_dev->lock);
-		priv_dev->gadget_driver->disconnect(&priv_dev->gadget);
-		spin_lock(&priv_dev->lock);
+	if (ep_sts_reg & EP_STS__TRBERR__MASK) {
+		cdns_writel(&usb_ss->regs->ep_sts, EP_STS__TRBERR__MASK);
+		dev_dbg(&usb_ss->dev, "TRBERR(%02X)\n",
+			dir ? USB_DIR_IN : USB_DIR_OUT);
 	}
-}
 
-/**
- * cdns3_check_usb_interrupt_proceed - Processes interrupt related to device
- * @priv_dev: extended gadget object
- * @usb_ists: bitmap representation of device's reported interrupts
- * (usb_ists register value)
- */
-static void cdns3_check_usb_interrupt_proceed(struct cdns3_device *priv_dev,
-					      u32 usb_ists)
-{
-	int speed = 0;
+	if (ep_sts_reg & EP_STS__DESCMIS__MASK) {
+		cdns_writel(&usb_ss->regs->ep_sts, EP_STS__DESCMIS__MASK);
 
-	trace_cdns3_usb_irq(priv_dev, usb_ists);
-	if (usb_ists & USB_ISTS_L1ENTI) {
-		/*
-		 * WORKAROUND: CDNS3 controller has issue with hardware resuming
-		 * from L1. To fix it, if any DMA transfer is pending driver
-		 * must starts driving resume signal immediately.
-		 */
-		if (readl(&priv_dev->regs->drbl))
-			__cdns3_gadget_wakeup(priv_dev);
-	}
+		dev_dbg(&usb_ss->dev, "DESCMIS(%02X)\n",
+			dir ? USB_DIR_IN : USB_DIR_OUT);
 
-	/* Connection detected */
-	if (usb_ists & (USB_ISTS_CON2I | USB_ISTS_CONI)) {
-		speed = cdns3_get_speed(priv_dev);
-		priv_dev->gadget.speed = speed;
-		usb_gadget_set_state(&priv_dev->gadget, USB_STATE_POWERED);
-		cdns3_ep0_config(priv_dev);
+		if (dir == 0 && !usb_ss->setup_pending) {
+			usb_ss->ep0_data_dir = 0;
+			cdns_ep0_run_transfer(usb_ss,
+					      usb_ss->setup_dma, 8, 0);
+		}
 	}
 
-	/* Disconnection detected */
-	if (usb_ists & (USB_ISTS_DIS2I | USB_ISTS_DISI)) {
-		cdns3_disconnect_gadget(priv_dev);
-		priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
-		usb_gadget_set_state(&priv_dev->gadget, USB_STATE_NOTATTACHED);
-		cdns3_hw_reset_eps_config(priv_dev);
-	}
+	if ((ep_sts_reg & EP_STS__IOC__MASK) ||
+	    (ep_sts_reg & EP_STS__ISP__MASK)) {
+		cdns_flush_cache((uintptr_t)usb_ss->trb_ep0, 20);
 
-	if (usb_ists & (USB_ISTS_L2ENTI | USB_ISTS_U3ENTI)) {
-		if (priv_dev->gadget_driver &&
-		    priv_dev->gadget_driver->suspend) {
-			spin_unlock(&priv_dev->lock);
-			priv_dev->gadget_driver->suspend(&priv_dev->gadget);
-			spin_lock(&priv_dev->lock);
-		}
-	}
+		cdns_writel(&usb_ss->regs->ep_sts, EP_STS__IOC__MASK);
+		if (usb_ss->actual_ep0_request) {
+			usb_gadget_unmap_request(&usb_ss->gadget,
+						 usb_ss->actual_ep0_request,
+						 usb_ss->ep0_data_dir);
+
+			usb_ss->actual_ep0_request->actual =
+				le32_to_cpu((usb_ss->trb_ep0)[1])
+				& ACTUAL_TRANSFERRED_BYTES_MASK;
 
-	if (usb_ists & (USB_ISTS_L2EXTI | USB_ISTS_U3EXTI)) {
-		if (priv_dev->gadget_driver &&
-		    priv_dev->gadget_driver->resume) {
-			spin_unlock(&priv_dev->lock);
-			priv_dev->gadget_driver->resume(&priv_dev->gadget);
-			spin_lock(&priv_dev->lock);
+			dev_dbg(&usb_ss->dev, "IOC(%02X) %d\n",
+				dir ? USB_DIR_IN : USB_DIR_OUT,
+				usb_ss->actual_ep0_request->actual);
+			list_del_init(&usb_ss->actual_ep0_request->list);
 		}
-	}
 
-	/* reset*/
-	if (usb_ists & (USB_ISTS_UWRESI | USB_ISTS_UHRESI | USB_ISTS_U2RESI)) {
-		if (priv_dev->gadget_driver) {
-			spin_unlock(&priv_dev->lock);
-			usb_gadget_udc_reset(&priv_dev->gadget,
-					     priv_dev->gadget_driver);
-			spin_lock(&priv_dev->lock);
-
-			/*read again to check the actual speed*/
-			speed = cdns3_get_speed(priv_dev);
-			priv_dev->gadget.speed = speed;
-			cdns3_hw_reset_eps_config(priv_dev);
-			cdns3_ep0_config(priv_dev);
+		if (usb_ss->actual_ep0_request &&
+		    usb_ss->actual_ep0_request->complete) {
+			spin_unlock(&usb_ss->lock);
+			usb_ss->actual_ep0_request->complete(usb_ss->gadget.ep0,
+						usb_ss->actual_ep0_request);
+			spin_lock(&usb_ss->lock);
 		}
+		cdns_prepare_setup_packet(usb_ss);
+		cdns_writel(&usb_ss->regs->ep_cmd, EP_CMD__REQ_CMPL__MASK);
 	}
 }
 
 /**
- * cdns3_device_irq_handler- interrupt handler for device part of controller
- *
- * @irq: irq number for cdns3 core device
- * @data: structure of cdns3
- *
- * Returns IRQ_HANDLED or IRQ_NONE
+ * cdns_check_usb_interrupt_proceed - Processes interrupt related to device
+ * @usb_ss: extended gadget object
+ * @usb_ists: bitmap representation of device's reported interrupts
+ * (usb_ists register value)
  */
-static irqreturn_t cdns3_device_irq_handler(int irq, void *data)
-{
-	struct cdns3_device *priv_dev;
-	struct cdns3 *cdns = data;
-	irqreturn_t ret = IRQ_NONE;
-	u32 reg;
+static void cdns_check_usb_interrupt_proceed(struct usb_ss_dev *usb_ss,
+					     u32 usb_ists)
+{
+	int interrupt_bit = ffs(usb_ists) - 1;
+	int speed;
+	u32 val;
+
+	dev_dbg(&usb_ss->dev, "USB interrupt detected\n");
+
+	switch (interrupt_bit) {
+	case USB_ISTS__CON2I__SHIFT:
+		/* FS/HS Connection detected */
+		dev_dbg(&usb_ss->dev,
+			"[Interrupt] FS/HS Connection detected\n");
+		val = cdns_readl(&usb_ss->regs->usb_sts);
+		speed = USB_STS__USBSPEED__READ(val);
+		if (speed == USB_SPEED_WIRELESS)
+			speed = USB_SPEED_SUPER;
+		dev_dbg(&usb_ss->dev, "Speed value: %s (%d), usbsts:0x%x\n",
+			usb_speed_string(speed), speed, val);
+		usb_ss->gadget.speed = speed;
+		usb_ss->is_connected = 1;
+		usb_gadget_set_state(&usb_ss->gadget, USB_STATE_POWERED);
+		cdns_ep0_config(usb_ss);
+		break;
 
-	priv_dev = cdns->gadget_dev;
+	case USB_ISTS__CONI__SHIFT:
+		/* SS Connection detected */
+		dev_dbg(&usb_ss->dev, "[Interrupt] SS Connection detected\n");
+		val = cdns_readl(&usb_ss->regs->usb_sts);
+		speed = USB_STS__USBSPEED__READ(val);
+		if (speed == USB_SPEED_WIRELESS)
+			speed = USB_SPEED_SUPER;
+		dev_dbg(&usb_ss->dev, "Speed value: %s (%d), usbsts:0x%x\n",
+			usb_speed_string(speed), speed, val);
+		usb_ss->gadget.speed = speed;
+		usb_ss->is_connected = 1;
+		usb_gadget_set_state(&usb_ss->gadget, USB_STATE_POWERED);
+		cdns_ep0_config(usb_ss);
+		break;
 
-	/* check USB device interrupt */
-	reg = readl(&priv_dev->regs->usb_ists);
-	if (reg) {
-		/* After masking interrupts the new interrupts won't be
-		 * reported in usb_ists/ep_ists. In order to not lose some
-		 * of them driver disables only detected interrupts.
-		 * They will be enabled ASAP after clearing source of
-		 * interrupt. This an unusual behavior only applies to
-		 * usb_ists register.
+	case USB_ISTS__DIS2I__SHIFT:
+	case USB_ISTS__DISI__SHIFT:
+		/* SS Disconnection detected */
+		val = cdns_readl(&usb_ss->regs->usb_sts);
+		dev_dbg(&usb_ss->dev,
+			"[Interrupt] Disconnection detected: usbsts:0x%x\n",
+			val);
+		if (usb_ss->gadget_driver &&
+		    usb_ss->gadget_driver->disconnect) {
+			spin_unlock(&usb_ss->lock);
+			usb_ss->gadget_driver->disconnect(&usb_ss->gadget);
+			spin_lock(&usb_ss->lock);
+		}
+		usb_ss->gadget.speed = USB_SPEED_UNKNOWN;
+		usb_gadget_set_state(&usb_ss->gadget, USB_STATE_NOTATTACHED);
+		usb_ss->is_connected = 0;
+		cdns_gadget_unconfig(usb_ss);
+		break;
+
+	case USB_ISTS__L2ENTI__SHIFT:
+		dev_dbg(&usb_ss->dev,
+			"[Interrupt] Device suspended\n");
+		break;
+
+	case USB_ISTS__L2EXTI__SHIFT:
+		dev_dbg(&usb_ss->dev, "[Interrupt] L2 exit detected\n");
+		/*
+		 * Exit from standby mode
+		 * on L2 exit (Suspend in HS/FS or SS)
 		 */
-		reg = ~reg & readl(&priv_dev->regs->usb_ien);
-		/* mask deferred interrupt. */
-		writel(reg, &priv_dev->regs->usb_ien);
-		ret = IRQ_WAKE_THREAD;
-	}
+		break;
+	case USB_ISTS__U3EXTI__SHIFT:
+		/*
+		 * Exit from standby mode
+		 * on U3 exit (Suspend in HS/FS or SS)
+		 */
+		dev_dbg(&usb_ss->dev, "[Interrupt] U3 exit detected\n");
+		break;
 
-	/* check endpoint interrupt */
-	reg = readl(&priv_dev->regs->ep_ists);
-	if (reg) {
-		writel(0, &priv_dev->regs->ep_ien);
-		ret = IRQ_WAKE_THREAD;
+		/* resets cases */
+	case USB_ISTS__UWRESI__SHIFT:
+	case USB_ISTS__UHRESI__SHIFT:
+	case USB_ISTS__U2RESI__SHIFT:
+		dev_dbg(&usb_ss->dev, "[Interrupt] Reset detected\n");
+		val = cdns_readl(&usb_ss->regs->usb_sts);
+		speed = USB_STS__USBSPEED__READ(val);
+		if (speed == USB_SPEED_WIRELESS)
+			speed = USB_SPEED_SUPER;
+		usb_gadget_set_state(&usb_ss->gadget, USB_STATE_DEFAULT);
+		usb_ss->gadget.speed = speed;
+		cdns_gadget_unconfig(usb_ss);
+		cdns_ep0_config(usb_ss);
+		break;
+	default:
+		break;
 	}
 
-	return ret;
+	/* Clear interrupt bit */
+	cdns_writel(&usb_ss->regs->usb_ists, (1uL << interrupt_bit));
 }
 
 /**
- * cdns3_device_thread_irq_handler- interrupt handler for device part
- * of controller
+ * cdns_irq_handler - irq line interrupt handler
+ * @cdns: cdns3 instance
  *
- * @irq: irq number for cdns3 core device
- * @data: structure of cdns3
- *
- * Returns IRQ_HANDLED or IRQ_NONE
+ * Returns IRQ_HANDLED when interrupt raised by USBSS_DEV,
+ * IRQ_NONE when interrupt raised by other device connected
+ * to the irq line
  */
-static irqreturn_t cdns3_device_thread_irq_handler(int irq, void *data)
+static int cdns_irq_handler_thread(struct cdns3 *cdns)
 {
-	struct cdns3_device *priv_dev;
-	struct cdns3 *cdns = data;
-	irqreturn_t ret = IRQ_NONE;
-	unsigned long flags;
-	int bit;
+	struct usb_ss_dev *usb_ss =
+		container_of(cdns->gadget_dev, struct usb_ss_dev, dev);
 	u32 reg;
+	int ret = IRQ_NONE;
+	unsigned long flags;
 
-	priv_dev = cdns->gadget_dev;
-	spin_lock_irqsave(&priv_dev->lock, flags);
+	spin_lock_irqsave(&usb_ss->lock, flags);
 
-	reg = readl(&priv_dev->regs->usb_ists);
+	/* check USB device interrupt */
+	reg = cdns_readl(&usb_ss->regs->usb_ists);
 	if (reg) {
-		writel(reg, &priv_dev->regs->usb_ists);
-		writel(USB_IEN_INIT, &priv_dev->regs->usb_ien);
-		cdns3_check_usb_interrupt_proceed(priv_dev, reg);
+		dev_dbg(&usb_ss->dev, "usb_ists: %08X\n", reg);
+		cdns_check_usb_interrupt_proceed(usb_ss, reg);
 		ret = IRQ_HANDLED;
 	}
 
-	reg = readl(&priv_dev->regs->ep_ists);
+	/* check endpoint interrupt */
+	reg = cdns_readl(&usb_ss->regs->ep_ists);
+	if (reg != 0) {
+		dev_dbg(&usb_ss->dev, "ep_ists: %08X\n", reg);
+	} else {
+		if (cdns_readl(&usb_ss->regs->usb_sts) &
+				USB_STS__CFGSTS__MASK)
+			ret = IRQ_HANDLED;
+		goto irqend;
+	}
 
 	/* handle default endpoint OUT */
-	if (reg & EP_ISTS_EP_OUT0) {
-		cdns3_check_ep0_interrupt_proceed(priv_dev, USB_DIR_OUT);
+	if (reg & EP_ISTS__EOUT0__MASK) {
+		cdns_check_ep0_interrupt_proceed(usb_ss, 0);
 		ret = IRQ_HANDLED;
 	}
 
 	/* handle default endpoint IN */
-	if (reg & EP_ISTS_EP_IN0) {
-		cdns3_check_ep0_interrupt_proceed(priv_dev, USB_DIR_IN);
+	if (reg & EP_ISTS__EIN0__MASK) {
+		cdns_check_ep0_interrupt_proceed(usb_ss, 1);
 		ret = IRQ_HANDLED;
 	}
 
 	/* check if interrupt from non default endpoint, if no exit */
-	reg &= ~(EP_ISTS_EP_OUT0 | EP_ISTS_EP_IN0);
+	reg &= ~(EP_ISTS__EOUT0__MASK | EP_ISTS__EIN0__MASK);
 	if (!reg)
 		goto irqend;
 
-	for_each_set_bit(bit, (unsigned long *)&reg,
-			 sizeof(u32) * BITS_PER_BYTE) {
-		cdns3_check_ep_interrupt_proceed(priv_dev->eps[bit]);
+	do {
+		unsigned int bit_pos = ffs(reg);
+		u32 bit_mask = 1 << (bit_pos - 1);
+		u8 ep_index = CAST_EP_REG_POS_TO_INDEX(bit_pos);
+
+		dev_dbg(&usb_ss->dev, "Interrupt on index: %d bitmask %08X\n",
+			ep_index, bit_mask);
+		cdns_check_ep_interrupt_proceed(usb_ss->eps[ep_index]);
+		reg &= ~bit_mask;
 		ret = IRQ_HANDLED;
-	}
+	} while (reg);
 
 irqend:
-	writel(~0, &priv_dev->regs->ep_ien);
-	spin_unlock_irqrestore(&priv_dev->lock, flags);
 
+	spin_unlock_irqrestore(&usb_ss->lock, flags);
 	return ret;
 }
 
 /**
- * cdns3_ep_onchip_buffer_reserve - Try to reserve onchip buf for EP
- *
- * The real reservation will occur during write to EP_CFG register,
- * this function is used to check if the 'size' reservation is allowed.
- *
- * @priv_dev: extended gadget object
- * @size: the size (KB) for EP would like to allocate
- * @is_in: endpoint direction
- *
- * Return 0 if the required size can met or negative value on failure
+ * usb_ss_gadget_ep0_enable
+ * Function shouldn't be called by gadget driver,
+ * endpoint 0 is allways active
  */
-static int cdns3_ep_onchip_buffer_reserve(struct cdns3_device *priv_dev,
-					  int size, int is_in)
+static int usb_ss_gadget_ep0_enable(struct usb_ep *ep,
+				    const struct usb_endpoint_descriptor *desc)
 {
-	int remained;
-
-	/* 2KB are reserved for EP0*/
-	remained = priv_dev->onchip_buffers - priv_dev->onchip_used_size - 2;
-
-	if (is_in) {
-		if (remained < size)
-			return -EPERM;
-
-		priv_dev->onchip_used_size += size;
-	} else {
-		int required;
-
-		/**
-		 *  ALL OUT EPs are shared the same chunk onchip memory, so
-		 * driver checks if it already has assigned enough buffers
-		 */
-		if (priv_dev->out_mem_is_allocated >= size)
-			return 0;
-
-		required = size - priv_dev->out_mem_is_allocated;
-
-		if (required > remained)
-			return -EPERM;
-
-		priv_dev->out_mem_is_allocated += required;
-		priv_dev->onchip_used_size += required;
-	}
-
-	return 0;
+	return -EINVAL;
 }
 
-void cdns3_configure_dmult(struct cdns3_device *priv_dev,
-			   struct cdns3_endpoint *priv_ep)
+/**
+ * usb_ss_gadget_ep0_disable
+ * Function shouldn't be called by gadget driver,
+ * endpoint 0 is allways active
+ */
+static int usb_ss_gadget_ep0_disable(struct usb_ep *ep)
 {
-	struct cdns3_usb_regs __iomem *regs = priv_dev->regs;
-
-	/* For dev_ver > DEV_VER_V2 DMULT is configured per endpoint */
-	if (priv_dev->dev_ver <= DEV_VER_V2)
-		writel(USB_CONF_DMULT, &regs->usb_conf);
-
-	if (priv_dev->dev_ver == DEV_VER_V2)
-		writel(USB_CONF2_EN_TDL_TRB, &regs->usb_conf2);
-
-	if (priv_dev->dev_ver >= DEV_VER_V3 && priv_ep) {
-		u32 mask;
-
-		if (priv_ep->dir)
-			mask = BIT(priv_ep->num + 16);
-		else
-			mask = BIT(priv_ep->num);
-
-		if (priv_ep->type != USB_ENDPOINT_XFER_ISOC) {
-			cdns3_set_register_bit(&regs->tdl_from_trb, mask);
-			cdns3_set_register_bit(&regs->tdl_beh, mask);
-			cdns3_set_register_bit(&regs->tdl_beh2, mask);
-			cdns3_set_register_bit(&regs->dma_adv_td, mask);
-		}
-
-		if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir)
-			cdns3_set_register_bit(&regs->tdl_from_trb, mask);
+	return -EINVAL;
+}
 
-		cdns3_set_register_bit(&regs->dtrans, mask);
-	}
+/**
+ * usb_ss_gadget_ep0_set_halt
+ * @ep: pointer to endpoint zero object
+ * @value: 1 for set stall, 0 for clear stall
+ *
+ * Returns 0
+ */
+static int usb_ss_gadget_ep0_set_halt(struct usb_ep *ep, int value)
+{
+	/* TODO */
+	return 0;
 }
 
 /**
- * cdns3_ep_config Configure hardware endpoint
- * @priv_ep: extended endpoint object
+ * usb_ss_gadget_ep0_queue Transfer data on endpoint zero
+ * @ep: pointer to endpoint zero object
+ * @request: pointer to request object
+ * @gfp_flags: gfp flags
+ *
+ * Returns 0 on success, error code elsewhere
  */
-void cdns3_ep_config(struct cdns3_endpoint *priv_ep)
+static int usb_ss_gadget_ep0_queue(struct usb_ep *ep,
+				   struct usb_request *request,
+				   gfp_t gfp_flags)
 {
-	bool is_iso_ep = (priv_ep->type == USB_ENDPOINT_XFER_ISOC);
-	struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
-	u32 bEndpointAddress = priv_ep->num | priv_ep->dir;
-	u32 max_packet_size = 0;
-	u8 maxburst = 0;
-	u32 ep_cfg = 0;
-	u8 buffering;
-	u8 mult = 0;
 	int ret;
-
-	buffering = CDNS3_EP_BUF_SIZE - 1;
-
-	cdns3_configure_dmult(priv_dev, priv_ep);
-
-	switch (priv_ep->type) {
-	case USB_ENDPOINT_XFER_INT:
-		ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_INT);
-
-		if ((priv_dev->dev_ver == DEV_VER_V2 && !priv_ep->dir) ||
-		    priv_dev->dev_ver > DEV_VER_V2)
-			ep_cfg |= EP_CFG_TDL_CHK;
-		break;
-	case USB_ENDPOINT_XFER_BULK:
-		ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_BULK);
-
-		if ((priv_dev->dev_ver == DEV_VER_V2  && !priv_ep->dir) ||
-		    priv_dev->dev_ver > DEV_VER_V2)
-			ep_cfg |= EP_CFG_TDL_CHK;
-		break;
-	default:
-		ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_ISOC);
-		mult = CDNS3_EP_ISO_HS_MULT - 1;
-		buffering = mult + 1;
-	}
-
-	switch (priv_dev->gadget.speed) {
-	case USB_SPEED_FULL:
-		max_packet_size = is_iso_ep ? 1023 : 64;
-		break;
-	case USB_SPEED_HIGH:
-		max_packet_size = is_iso_ep ? 1024 : 512;
-		break;
-	case USB_SPEED_SUPER:
-		/* It's limitation that driver assumes in driver. */
-		mult = 0;
-		max_packet_size = 1024;
-		if (priv_ep->type == USB_ENDPOINT_XFER_ISOC) {
-			maxburst = CDNS3_EP_ISO_SS_BURST - 1;
-			buffering = (mult + 1) *
-				    (maxburst + 1);
-
-			if (priv_ep->interval > 1)
-				buffering++;
-		} else {
-			maxburst = CDNS3_EP_BUF_SIZE - 1;
+	unsigned long flags;
+	int erdy_sent = 0;
+	/* get extended endpoint */
+	struct usb_ss_endpoint *usb_ss_ep =
+		to_usb_ss_ep(ep);
+	struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss;
+
+	dev_dbg(&usb_ss->dev, "QUEUE(%02X) %d\n",
+		usb_ss->ep0_data_dir ? USB_DIR_IN : USB_DIR_OUT,
+		request->length);
+
+	/* send STATUS stage */
+	if (request->length == 0 && request->zero == 0) {
+		spin_lock_irqsave(&usb_ss->lock, flags);
+		select_ep(usb_ss, 0x00);
+		if (!usb_ss->hw_configured_flag) {
+			cdns_writel(&usb_ss->regs->usb_conf,
+				    USB_CONF__CFGSET__MASK);
+			/* SET CONFIGURATION */
+			cdns_prepare_setup_packet(usb_ss);
+			cdns_writel(&usb_ss->regs->ep_cmd,
+				    EP_CMD__ERDY__MASK
+				    | EP_CMD__REQ_CMPL__MASK);
+			/* wait until configuration set */
+			while (!(cdns_readl(&usb_ss->regs->usb_sts)
+					& USB_STS__CFGSTS__MASK))
+				;
+			erdy_sent = 1;
+			usb_ss->hw_configured_flag = 1;
+
+			list_for_each_entry(ep, &usb_ss->gadget.ep_list,
+					    ep_list) {
+				if (to_usb_ss_ep(ep)->enabled)
+					cdns_ep_run_transfer(to_usb_ss_ep(ep));
+			}
 		}
-		break;
-	default:
-		/* all other speed are not supported */
-		return;
+		if (!erdy_sent)
+			cdns_writel(&usb_ss->regs->ep_cmd,
+				    EP_CMD__ERDY__MASK
+				    | EP_CMD__REQ_CMPL__MASK);
+		if (request->complete)
+			request->complete(usb_ss->gadget.ep0, request);
+		spin_unlock_irqrestore(&usb_ss->lock, flags);
+		return 0;
 	}
 
-	if (max_packet_size == 1024)
-		priv_ep->trb_burst_size = 128;
-	else if (max_packet_size >= 512)
-		priv_ep->trb_burst_size = 64;
-	else
-		priv_ep->trb_burst_size = 16;
-
-	ret = cdns3_ep_onchip_buffer_reserve(priv_dev, buffering + 1,
-					     !!priv_ep->dir);
+	spin_lock_irqsave(&usb_ss->lock, flags);
+	ret = usb_gadget_map_request(&usb_ss->gadget, request,
+				     usb_ss->ep0_data_dir);
 	if (ret) {
-		dev_err(priv_dev->dev, "onchip mem is full, ep is invalid\n");
-		return;
+		dev_err(&usb_ss->dev, "failed to map request\n");
+		return -EINVAL;
 	}
 
-	ep_cfg |= EP_CFG_MAXPKTSIZE(max_packet_size) |
-		  EP_CFG_MULT(mult) |
-		  EP_CFG_BUFFERING(buffering) |
-		  EP_CFG_MAXBURST(maxburst);
-
-	cdns3_select_ep(priv_dev, bEndpointAddress);
-	writel(ep_cfg, &priv_dev->regs->ep_cfg);
-
-	dev_dbg(priv_dev->dev, "Configure %s: with val %08x\n",
-		priv_ep->name, ep_cfg);
-}
-
-/* Find correct direction for HW endpoint according to description */
-static int cdns3_ep_dir_is_correct(struct usb_endpoint_descriptor *desc,
-				   struct cdns3_endpoint *priv_ep)
-{
-	return (priv_ep->endpoint.caps.dir_in && usb_endpoint_dir_in(desc)) ||
-	       (priv_ep->endpoint.caps.dir_out && usb_endpoint_dir_out(desc));
-}
-
-static struct
-cdns3_endpoint *cdns3_find_available_ep(struct cdns3_device *priv_dev,
-					struct usb_endpoint_descriptor *desc)
-{
-	struct usb_ep *ep;
-	struct cdns3_endpoint *priv_ep;
-
-	list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) {
-		unsigned long num;
-		/* ep name pattern likes epXin or epXout */
-		char c[2] = {ep->name[2], '\0'};
+	usb_ss->actual_ep0_request = request;
+	cdns_ep0_run_transfer(usb_ss, request->dma, request->length, 1);
+	list_add_tail(&request->list, &usb_ss_ep->request_list);
+	spin_unlock_irqrestore(&usb_ss->lock, flags);
 
-		num = dectoul(c, NULL);
-
-		priv_ep = ep_to_cdns3_ep(ep);
-		if (cdns3_ep_dir_is_correct(desc, priv_ep)) {
-			if (!(priv_ep->flags & EP_CLAIMED)) {
-				priv_ep->num  = num;
-				return priv_ep;
-			}
-		}
-	}
-
-	return ERR_PTR(-ENOENT);
+	return 0;
 }
 
-/*
- *  Cadence IP has one limitation that all endpoints must be configured
- * (Type & MaxPacketSize) before setting configuration through hardware
- * register, it means we can't change endpoints configuration after
- * set_configuration.
- *
- * This function set EP_CLAIMED flag which is added when the gadget driver
- * uses usb_ep_autoconfig to configure specific endpoint;
- * When the udc driver receives set_configurion request,
- * it goes through all claimed endpoints, and configure all endpoints
- * accordingly.
- *
- * At usb_ep_ops.enable/disable, we only enable and disable endpoint through
- * ep_cfg register which can be changed after set_configuration, and do
- * some software operation accordingly.
+/**
+ * cdns_ep_config Configure hardware endpoint
+ * @usb_ss_ep: extended endpoint object
  */
-static struct
-usb_ep *cdns3_gadget_match_ep(struct usb_gadget *gadget,
-			      struct usb_endpoint_descriptor *desc,
-			      struct usb_ss_ep_comp_descriptor *comp_desc)
+static void cdns_ep_config(struct usb_ss_endpoint *usb_ss_ep)
 {
-	struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
-	struct cdns3_endpoint *priv_ep;
-	unsigned long flags;
-
-	priv_ep = cdns3_find_available_ep(priv_dev, desc);
-	if (IS_ERR(priv_ep)) {
-		dev_err(priv_dev->dev, "no available ep\n");
-		return NULL;
+	struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss;
+	u32 ep_cfg = 0;
+	u32 max_packet_size = 0;
+	u32 bEndpointAddress = usb_ss_ep->num | usb_ss_ep->dir;
+	u32 interrupt_mask = 0;
+	bool is_iso_ep = (usb_ss_ep->type == USB_ENDPOINT_XFER_ISOC);
+	__maybe_unused bool is_int_ep =
+			(usb_ss_ep->type == USB_ENDPOINT_XFER_INT);
+
+	dev_dbg(&usb_ss->dev,
+		"%s: %s addr=0x%x, speed %d, is_iso_ep %d\n", __func__,
+		usb_ss_ep->name, bEndpointAddress, usb_ss->gadget.speed,
+		is_iso_ep);
+
+	if (is_iso_ep) {
+		ep_cfg = EP_CFG__EPTYPE__WRITE(USB_ENDPOINT_XFER_ISOC);
+		interrupt_mask = INTERRUPT_MASK;
+	} else {
+		ep_cfg = EP_CFG__EPTYPE__WRITE(USB_ENDPOINT_XFER_BULK);
 	}
 
-	dev_dbg(priv_dev->dev, "match endpoint: %s\n", priv_ep->name);
+	switch (usb_ss->gadget.speed) {
+	case USB_SPEED_UNKNOWN:
+		max_packet_size = ENDPOINT_MAX_PACKET_SIZE_0;
+		break;
 
-	spin_lock_irqsave(&priv_dev->lock, flags);
-	priv_ep->endpoint.desc = desc;
-	priv_ep->dir  = usb_endpoint_dir_in(desc) ? USB_DIR_IN : USB_DIR_OUT;
-	priv_ep->type = usb_endpoint_type(desc);
-	priv_ep->flags |= EP_CLAIMED;
-	priv_ep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0;
+	case USB_SPEED_LOW:
+		max_packet_size = ENDPOINT_MAX_PACKET_SIZE_8;
+		break;
 
-	spin_unlock_irqrestore(&priv_dev->lock, flags);
-	return &priv_ep->endpoint;
-}
+	case USB_SPEED_FULL:
+		max_packet_size = (is_iso_ep ?
+			ENDPOINT_MAX_PACKET_SIZE_1023 :
+			ENDPOINT_MAX_PACKET_SIZE_64);
+		break;
 
-/**
- * cdns3_gadget_ep_alloc_request Allocates request
- * @ep: endpoint object associated with request
- * @gfp_flags: gfp flags
- *
- * Returns allocated request address, NULL on allocation error
- */
-struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep,
-						  gfp_t gfp_flags)
-{
-	struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
-	struct cdns3_request *priv_req;
+	case USB_SPEED_HIGH:
+		max_packet_size = (is_iso_ep ?
+			ENDPOINT_MAX_PACKET_SIZE_1024 :
+			ENDPOINT_MAX_PACKET_SIZE_512);
+#if defined(CONFIG_SPL_USB_SDP_SUPPORT) || defined(CONFIG_USB_FUNCTION_SDP)
+		if (is_int_ep)
+			max_packet_size = ENDPOINT_MAX_PACKET_SIZE_1024;
+#endif
+		break;
 
-	priv_req = kzalloc(sizeof(*priv_req), gfp_flags);
-	if (!priv_req)
-		return NULL;
+	case USB_SPEED_WIRELESS:
+		max_packet_size = ENDPOINT_MAX_PACKET_SIZE_512;
+		break;
 
-	priv_req->priv_ep = priv_ep;
+	case USB_SPEED_SUPER:
+	case USB_SPEED_SUPER_PLUS:
+		max_packet_size = ENDPOINT_MAX_PACKET_SIZE_1024;
+		break;
+	}
 
-	trace_cdns3_alloc_request(priv_req);
-	return &priv_req->request;
-}
+	ep_cfg |= EP_CFG__MAXPKTSIZE__WRITE(max_packet_size);
 
-/**
- * cdns3_gadget_ep_free_request Free memory occupied by request
- * @ep: endpoint object associated with request
- * @request: request to free memory
- */
-void cdns3_gadget_ep_free_request(struct usb_ep *ep,
-				  struct usb_request *request)
-{
-	struct cdns3_request *priv_req = to_cdns3_request(request);
+	if (is_iso_ep) {
+		ep_cfg |= EP_CFG__BUFFERING__WRITE(1);
+		ep_cfg |= EP_CFG__MAXBURST__WRITE(0);
+	} else {
+		ep_cfg |= EP_CFG__BUFFERING__WRITE(3);
+		ep_cfg |= EP_CFG__MAXBURST__WRITE(15);
+	}
 
-	if (priv_req->aligned_buf)
-		priv_req->aligned_buf->in_use = 0;
+	select_ep(usb_ss, bEndpointAddress);
+	cdns_writel(&usb_ss->regs->ep_cfg, ep_cfg);
+	cdns_writel(&usb_ss->regs->ep_sts_en,
+		    EP_STS_EN__TRBERREN__MASK | interrupt_mask);
 
-	trace_cdns3_free_request(priv_req);
-	kfree(priv_req);
+	/* enable interrupt for selected endpoint */
+	ep_cfg = cdns_readl(&usb_ss->regs->ep_ien);
+	ep_cfg |= CAST_EP_ADDR_TO_BIT_POS(bEndpointAddress);
+	cdns_writel(&usb_ss->regs->ep_ien, ep_cfg);
 }
 
 /**
- * cdns3_gadget_ep_enable Enable endpoint
+ * usb_ss_gadget_ep_enable Enable endpoint
  * @ep: endpoint object
  * @desc: endpoint descriptor
  *
  * Returns 0 on success, error code elsewhere
  */
-static int cdns3_gadget_ep_enable(struct usb_ep *ep,
-				  const struct usb_endpoint_descriptor *desc)
+static int usb_ss_gadget_ep_enable(struct usb_ep *ep,
+				   const struct usb_endpoint_descriptor *desc)
 {
-	struct cdns3_endpoint *priv_ep;
-	struct cdns3_device *priv_dev;
-	u32 reg = EP_STS_EN_TRBERREN;
-	u32 bEndpointAddress;
+	struct usb_ss_endpoint *usb_ss_ep;
+	struct usb_ss_dev *usb_ss;
 	unsigned long flags;
-	int enable = 1;
+	unsigned long *dma_addr;
 	int ret;
-	int val;
+	u32 ep_cfg;
 
-	priv_ep = ep_to_cdns3_ep(ep);
-	priv_dev = priv_ep->cdns3_dev;
+	usb_ss_ep = to_usb_ss_ep(ep);
+	usb_ss = usb_ss_ep->usb_ss;
 
 	if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
-		dev_dbg(priv_dev->dev, "usbss: invalid parameters\n");
+		dev_err(&usb_ss->dev, "usb-ss: invalid parameters\n");
 		return -EINVAL;
 	}
 
 	if (!desc->wMaxPacketSize) {
-		dev_err(priv_dev->dev, "usbss: missing wMaxPacketSize\n");
+		dev_err(&usb_ss->dev, "usb-ss: missing wMaxPacketSize\n");
 		return -EINVAL;
 	}
 
-	if (WARN_ON(priv_ep->flags & EP_ENABLED))
-		return 0;
-
-	spin_lock_irqsave(&priv_dev->lock, flags);
-
-	priv_ep->endpoint.desc = desc;
-	priv_ep->type = usb_endpoint_type(desc);
-	priv_ep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0;
-
-	if (priv_ep->interval > ISO_MAX_INTERVAL &&
-	    priv_ep->type == USB_ENDPOINT_XFER_ISOC) {
-		dev_err(priv_dev->dev, "Driver is limited to %d period\n",
-			ISO_MAX_INTERVAL);
-
-		ret =  -EINVAL;
-		goto exit;
-	}
-
-	ret = cdns3_allocate_trb_pool(priv_ep);
-
+	ret = usb_ss_allocate_trb_pool(usb_ss_ep);
 	if (ret)
-		goto exit;
-
-	bEndpointAddress = priv_ep->num | priv_ep->dir;
-	cdns3_select_ep(priv_dev, bEndpointAddress);
-
-	trace_cdns3_gadget_ep_enable(priv_ep);
+		return ret;
 
-	writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
+	if (!usb_ss_ep->cpu_addr) {
+		dma_addr = (unsigned long *)&usb_ss_ep->dma_addr;
+		usb_ss_ep->cpu_addr = dma_alloc_coherent(4096, dma_addr);
 
-	ret = readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
-					!(val & (EP_CMD_CSTALL | EP_CMD_EPRST)),
-					1000);
-
-	if (unlikely(ret)) {
-		cdns3_free_trb_pool(priv_ep);
-		ret =  -EINVAL;
-		goto exit;
+		if (!usb_ss_ep->cpu_addr)
+			return -ENOMEM;
 	}
 
-	/* enable interrupt for selected endpoint */
-	cdns3_set_register_bit(&priv_dev->regs->ep_ien,
-			       BIT(cdns3_ep_addr_to_index(bEndpointAddress)));
-
-	if (priv_dev->dev_ver < DEV_VER_V2)
-		cdns3_wa2_enable_detection(priv_dev, priv_ep, reg);
-
-	writel(reg, &priv_dev->regs->ep_sts_en);
-
-	/*
-	 * For some versions of controller at some point during ISO OUT traffic
-	 * DMA reads Transfer Ring for the EP which has never got doorbell.
-	 * This issue was detected only on simulation, but to avoid this issue
-	 * driver add protection against it. To fix it driver enable ISO OUT
-	 * endpoint before setting DRBL. This special treatment of ISO OUT
-	 * endpoints are recommended by controller specification.
-	 */
-	if (priv_ep->type == USB_ENDPOINT_XFER_ISOC  && !priv_ep->dir)
-		enable = 0;
-
-	if (enable)
-		cdns3_set_register_bit(&priv_dev->regs->ep_cfg, EP_CFG_ENABLE);
+	dev_dbg(&usb_ss->dev, "Enabling endpoint: %s, addr=0x%x\n",
+		ep->name, desc->bEndpointAddress);
+	spin_lock_irqsave(&usb_ss->lock, flags);
+	select_ep(usb_ss, desc->bEndpointAddress);
+	ep_cfg = cdns_readl(&usb_ss->regs->ep_cfg);
+	ep_cfg |= EP_CFG__ENABLE__MASK;
+	cdns_writel(&usb_ss->regs->ep_cfg, ep_cfg);
 
+	usb_ss_ep->enabled = 1;
 	ep->desc = desc;
-	priv_ep->flags &= ~(EP_PENDING_REQUEST | EP_STALLED | EP_STALL_PENDING |
-			    EP_QUIRK_ISO_OUT_EN | EP_QUIRK_EXTRA_BUF_EN);
-	priv_ep->flags |= EP_ENABLED | EP_UPDATE_EP_TRBADDR;
-	priv_ep->wa1_set = 0;
-	priv_ep->enqueue = 0;
-	priv_ep->dequeue = 0;
-	reg = readl(&priv_dev->regs->ep_sts);
-	priv_ep->pcs = !!EP_STS_CCS(reg);
-	priv_ep->ccs = !!EP_STS_CCS(reg);
-	/* one TRB is reserved for link TRB used in DMULT mode*/
-	priv_ep->free_trbs = priv_ep->num_trbs - 1;
-exit:
-	spin_unlock_irqrestore(&priv_dev->lock, flags);
+	usb_ss_ep->hw_pending_flag = 0;
+	spin_unlock_irqrestore(&usb_ss->lock, flags);
 
-	return ret;
+	return 0;
 }
 
-/**
- * cdns3_gadget_ep_disable Disable endpoint
- * @ep: endpoint object
- *
- * Returns 0 on success, error code elsewhere
- */
-static int cdns3_gadget_ep_disable(struct usb_ep *ep)
+static int cdns3_disable_reset_ep(struct usb_ss_dev *usb_ss,
+				   struct usb_ss_endpoint *usb_ss_ep)
 {
-	struct cdns3_endpoint *priv_ep;
-	struct cdns3_request *priv_req;
-	struct cdns3_device *priv_dev;
-	struct usb_request *request;
+	u32 val;
+	int ret;
 	unsigned long flags;
-	int ret = 0;
-	u32 ep_cfg;
-	int val;
 
-	if (!ep) {
-		pr_err("usbss: invalid parameters\n");
-		return -EINVAL;
-	}
-
-	priv_ep = ep_to_cdns3_ep(ep);
-	priv_dev = priv_ep->cdns3_dev;
+	spin_lock_irqsave(&usb_ss->lock, flags);
 
-	if (WARN_ON(!(priv_ep->flags & EP_ENABLED)))
+	if (usb_ss_ep->hw_reset_flag) {
+		spin_unlock_irqrestore(&usb_ss->lock, flags);
 		return 0;
+	}
 
-	spin_lock_irqsave(&priv_dev->lock, flags);
-
-	trace_cdns3_gadget_ep_disable(priv_ep);
-
-	cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress);
-
-	ep_cfg = readl(&priv_dev->regs->ep_cfg);
-	ep_cfg &= ~EP_CFG_ENABLE;
-	writel(ep_cfg, &priv_dev->regs->ep_cfg);
+	select_ep(usb_ss_ep->usb_ss,
+			usb_ss_ep->endpoint.desc->bEndpointAddress);
 
 	/**
 	 * Driver needs some time before resetting endpoint.
 	 * It need waits for clearing DBUSY bit or for timeout expired.
 	 * 10us is enough time for controller to stop transfer.
 	 */
-	readl_poll_timeout_atomic(&priv_dev->regs->ep_sts, val,
-				  !(val & EP_STS_DBUSY), 10);
-	writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
-
-	readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
-				  !(val & (EP_CMD_CSTALL | EP_CMD_EPRST)),
-				  1000);
+	ret = readl_poll_timeout(&usb_ss->regs->ep_sts, val,
+				  !(val & EP_STS__DBUSY__MASK), 10);
 	if (unlikely(ret))
-		dev_err(priv_dev->dev, "Timeout: %s resetting failed.\n",
-			priv_ep->name);
-
-	while (!list_empty(&priv_ep->pending_req_list)) {
-		request = cdns3_next_request(&priv_ep->pending_req_list);
-
-		cdns3_gadget_giveback(priv_ep, to_cdns3_request(request),
-				      -ESHUTDOWN);
-	}
+		dev_err(&usb_ss->dev, "Timeout: %s wait dbusy\n",
+			usb_ss->gadget.name);
 
-	while (!list_empty(&priv_ep->wa2_descmiss_req_list)) {
-		priv_req = cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list);
+	ret = readl_poll_timeout(&usb_ss->regs->ep_sts, val,
+				  (val & EP_STS__BUFFEMPTY__MASK), 1000);
+	if (unlikely(ret))
+		dev_err(&usb_ss->dev, "Timeout: %s: %s wait buffer empty\n",
+			usb_ss_ep->name, usb_ss->gadget.name);
 
-		kfree(priv_req->request.buf);
-		cdns3_gadget_ep_free_request(&priv_ep->endpoint,
-					     &priv_req->request);
-		list_del_init(&priv_req->list);
-		--priv_ep->wa2_counter;
-	}
+	writel(EP_CMD__EPRST__MASK, &usb_ss->regs->ep_cmd);
 
-	while (!list_empty(&priv_ep->deferred_req_list)) {
-		request = cdns3_next_request(&priv_ep->deferred_req_list);
+	ret = readl_poll_timeout(&usb_ss->regs->ep_cmd, val,
+					!(val & (EP_CMD__CSTALL__MASK | EP_CMD__EPRST__MASK)),
+					1000);
 
-		cdns3_gadget_giveback(priv_ep, to_cdns3_request(request),
-				      -ESHUTDOWN);
-	}
+	if (unlikely(ret))
+		dev_err(&usb_ss->dev, "Timeout: %s resetting failed.\n",
+			usb_ss->gadget.name);
 
-	priv_ep->descmis_req = NULL;
 
-	ep->desc = NULL;
-	priv_ep->flags &= ~EP_ENABLED;
+	val = readl(&usb_ss->regs->ep_cfg);
+	val &= ~EP_CFG__ENABLE__MASK;
+	writel(val, &usb_ss->regs->ep_cfg);
 
-	spin_unlock_irqrestore(&priv_dev->lock, flags);
+	usb_ss_ep->hw_reset_flag = 1;
+	spin_unlock_irqrestore(&usb_ss->lock, flags);
 
 	return ret;
 }
 
-/**
- * cdns3_gadget_ep_queue Transfer data on endpoint
- * @ep: endpoint object
- * @request: request object
- * @gfp_flags: gfp flags
- *
- * Returns 0 on success, error code elsewhere
- */
-static int __cdns3_gadget_ep_queue(struct usb_ep *ep,
-				   struct usb_request *request,
-				   gfp_t gfp_flags)
+static int usb_ss_gadget_ep_conf(struct usb_gadget *gadget,
+				  struct usb_ep *ep,
+				  struct usb_endpoint_descriptor *desc)
 {
-	struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
-	struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
-	struct cdns3_request *priv_req;
-	int ret = 0;
-
-	request->actual = 0;
-	request->status = -EINPROGRESS;
-	priv_req = to_cdns3_request(request);
-	trace_cdns3_ep_queue(priv_req);
+	struct usb_ss_dev __maybe_unused *usb_ss = gadget_to_usb_ss(gadget);
+	struct usb_ss_endpoint *usb_ss_ep;
+	unsigned long flags;
 
-	if (priv_dev->dev_ver < DEV_VER_V2) {
-		ret = cdns3_wa2_gadget_ep_queue(priv_dev, priv_ep,
-						priv_req);
+	usb_ss_ep = to_usb_ss_ep(ep);
 
-		if (ret == EINPROGRESS)
-			return 0;
-	}
+	dev_dbg(&usb_ss->dev, "match endpoint: %s\n", usb_ss_ep->name);
 
-	ret = cdns3_prepare_aligned_request_buf(priv_req);
-	if (ret < 0)
-		return ret;
+	u8 num = simple_strtoul(&ep->name[2], NULL, 10);
 
-	ret = usb_gadget_map_request(&priv_dev->gadget, request,
-				     usb_endpoint_dir_in(ep->desc));
-	if (ret)
-		return ret;
+	spin_lock_irqsave(&usb_ss->lock, flags);
+	usb_ss_ep->num  = num;
+	usb_ss_ep->used = true;
+	usb_ss_ep->endpoint.desc = desc;
+	usb_ss_ep->dir  = usb_endpoint_dir_in(desc) ? USB_DIR_IN : USB_DIR_OUT;
+	usb_ss_ep->type = usb_endpoint_type(desc);
+	usb_ss_ep->address = desc->bEndpointAddress;
+	spin_unlock_irqrestore(&usb_ss->lock, flags);
 
-	list_add_tail(&request->list, &priv_ep->deferred_req_list);
+	return 1;
+}
 
-	/*
-	 * If hardware endpoint configuration has not been set yet then
-	 * just queue request in deferred list. Transfer will be started in
-	 * cdns3_set_hw_configuration.
-	 */
-	if (priv_dev->hw_configured_flag && !(priv_ep->flags & EP_STALLED) &&
-	    !(priv_ep->flags & EP_STALL_PENDING))
-		cdns3_start_all_request(priv_dev, priv_ep);
+static void usb_ss_free_trb_pool(struct usb_ss_endpoint *usb_ss_ep)
+{
+	if (usb_ss_ep->trb_pool) {
+		dma_free_coherent(usb_ss_ep->trb_pool);
+		usb_ss_ep->trb_pool = NULL;
+	}
 
-	return 0;
+	if (usb_ss_ep->cpu_addr) {
+		dma_free_coherent(usb_ss_ep->cpu_addr);
+		usb_ss_ep->cpu_addr = NULL;
+	}
 }
 
-static int cdns3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
-				 gfp_t gfp_flags)
+/**
+ * usb_ss_gadget_ep_disable Disable endpoint
+ * @ep: endpoint object
+ *
+ * Returns 0 on success, error code elsewhere
+ */
+static int usb_ss_gadget_ep_disable(struct usb_ep *ep)
 {
-	struct usb_request *zlp_request;
-	struct cdns3_endpoint *priv_ep;
-	struct cdns3_device *priv_dev;
+	struct usb_ss_endpoint *usb_ss_ep;
+	struct usb_ss_dev *usb_ss;
 	unsigned long flags;
-	int ret;
+	int ret = 0;
+	struct usb_request *request;
 
-	if (!request || !ep)
+	if (!ep) {
+		pr_debug("usb-ss: invalid parameters\n");
 		return -EINVAL;
+	}
 
-	priv_ep = ep_to_cdns3_ep(ep);
-	priv_dev = priv_ep->cdns3_dev;
+	usb_ss_ep = to_usb_ss_ep(ep);
+	usb_ss = usb_ss_ep->usb_ss;
 
-	spin_lock_irqsave(&priv_dev->lock, flags);
+	spin_lock_irqsave(&usb_ss->lock, flags);
+	if (!usb_ss->start_gadget) {
+		dev_dbg(&usb_ss->dev,
+			"Disabling endpoint at disconnection: %s\n", ep->name);
+		spin_unlock_irqrestore(&usb_ss->lock, flags);
+		return 0;
+	}
 
-	ret = __cdns3_gadget_ep_queue(ep, request, gfp_flags);
+	dev_dbg(&usb_ss->dev,
+		"Disabling endpoint: %s\n", ep->name);
 
-	if (ret == 0 && request->zero && request->length &&
-	    (request->length % ep->maxpacket == 0)) {
-		struct cdns3_request *priv_req;
+	ret = cdns3_disable_reset_ep(usb_ss, usb_ss_ep);
 
-		zlp_request = cdns3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
-		zlp_request->buf = priv_dev->zlp_buf;
-		zlp_request->length = 0;
+	while (!list_empty(&usb_ss_ep->request_list)) {
+		request = next_request(&usb_ss_ep->request_list);
+		usb_gadget_unmap_request(&usb_ss->gadget, request,
+					 ep->desc->bEndpointAddress &
+					 USB_DIR_IN);
+		request->status = -ESHUTDOWN;
+		list_del(&request->list);
+		spin_unlock(&usb_ss->lock);
+		usb_gadget_giveback_request(ep, request);
+		spin_lock(&usb_ss->lock);
+	}
 
-		priv_req = to_cdns3_request(zlp_request);
-		priv_req->flags |= REQUEST_ZLP;
+	ep->desc = NULL;
+	usb_ss_ep->enabled = 0;
 
-		dev_dbg(priv_dev->dev, "Queuing ZLP for endpoint: %s\n",
-			priv_ep->name);
-		ret = __cdns3_gadget_ep_queue(ep, zlp_request, gfp_flags);
-	}
+	spin_unlock_irqrestore(&usb_ss->lock, flags);
 
-	spin_unlock_irqrestore(&priv_dev->lock, flags);
 	return ret;
 }
 
 /**
- * cdns3_gadget_ep_dequeue Remove request from transfer queue
+ * usb_ss_gadget_ep_alloc_request Allocates request
+ * @ep: endpoint object associated with request
+ * @gfp_flags: gfp flags
+ *
+ * Returns allocated request address, NULL on allocation error
+ */
+static struct usb_request *usb_ss_gadget_ep_alloc_request(struct usb_ep *ep,
+							  gfp_t gfp_flags)
+{
+	struct usb_request *request;
+
+	request = kzalloc(sizeof(*request), gfp_flags);
+	if (!request)
+		return NULL;
+
+	return request;
+}
+
+/**
+ * usb_ss_gadget_ep_free_request Free memory occupied by request
  * @ep: endpoint object associated with request
+ * @request: request to free memory
+ */
+static void usb_ss_gadget_ep_free_request(struct usb_ep *ep,
+					  struct usb_request *request)
+{
+	kfree(request);
+}
+
+/**
+ * usb_ss_gadget_ep_queue Transfer data on endpoint
+ * @ep: endpoint object
  * @request: request object
+ * @gfp_flags: gfp flags
  *
  * Returns 0 on success, error code elsewhere
  */
-int cdns3_gadget_ep_dequeue(struct usb_ep *ep,
-			    struct usb_request *request)
+static int usb_ss_gadget_ep_queue(struct usb_ep *ep,
+				  struct usb_request *request, gfp_t gfp_flags)
 {
-	struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
-	struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
-	struct usb_request *req, *req_temp;
-	struct cdns3_request *priv_req;
-	struct cdns3_trb *link_trb;
+	struct usb_ss_endpoint *usb_ss_ep =
+		to_usb_ss_ep(ep);
+	struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss;
 	unsigned long flags;
 	int ret = 0;
+	int empty_list = 0;
 
-	if (!ep || !request || !ep->desc)
-		return -EINVAL;
-
-	spin_lock_irqsave(&priv_dev->lock, flags);
+	spin_lock_irqsave(&usb_ss->lock, flags);
 
-	priv_req = to_cdns3_request(request);
+	request->actual = 0;
+	request->status = -EINPROGRESS;
 
-	trace_cdns3_ep_dequeue(priv_req);
+	dev_dbg(&usb_ss->dev,
+		"Queuing endpoint: %s\n", usb_ss_ep->name);
 
-	cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress);
+	dev_dbg(&usb_ss->dev, "QUEUE(%02X) %d\n",
+		ep->desc->bEndpointAddress, request->length);
 
-	list_for_each_entry_safe(req, req_temp, &priv_ep->pending_req_list,
-				 list) {
-		if (request == req)
-			goto found;
-	}
+	ret = usb_gadget_map_request(&usb_ss->gadget, request,
+				     ep->desc->bEndpointAddress & USB_DIR_IN);
 
-	list_for_each_entry_safe(req, req_temp, &priv_ep->deferred_req_list,
-				 list) {
-		if (request == req)
-			goto found;
+	if (ret) {
+		spin_unlock_irqrestore(&usb_ss->lock, flags);
+		return ret;
 	}
 
-	goto not_found;
-
-found:
-
-	if (priv_ep->wa1_trb == priv_req->trb)
-		cdns3_wa1_restore_cycle_bit(priv_ep);
-
-	link_trb = priv_req->trb;
-	cdns3_move_deq_to_next_trb(priv_req);
-	cdns3_gadget_giveback(priv_ep, priv_req, -ECONNRESET);
+	empty_list = list_empty(&usb_ss_ep->request_list);
+	list_add_tail(&request->list, &usb_ss_ep->request_list);
 
-	/* Update ring */
-	request = cdns3_next_request(&priv_ep->deferred_req_list);
-	if (request) {
-		priv_req = to_cdns3_request(request);
+	if (!usb_ss->hw_configured_flag) {
+		spin_unlock_irqrestore(&usb_ss->lock, flags);
+		return 0;
+	}
 
-		link_trb->buffer = TRB_BUFFER(priv_ep->trb_pool_dma +
-					      (priv_req->start_trb * TRB_SIZE));
-		link_trb->control = (link_trb->control & TRB_CYCLE) |
-				    TRB_TYPE(TRB_LINK) | TRB_CHAIN | TRB_TOGGLE;
-	} else {
-		priv_ep->flags |= EP_UPDATE_EP_TRBADDR;
+	if (empty_list) {
+		if (!usb_ss_ep->stalled_flag)
+			cdns_ep_run_transfer(usb_ss_ep);
 	}
+	spin_unlock_irqrestore(&usb_ss->lock, flags);
 
-not_found:
-	spin_unlock_irqrestore(&priv_dev->lock, flags);
 	return ret;
 }
 
 /**
- * __cdns3_gadget_ep_set_halt Sets stall on selected endpoint
- * Should be called after acquiring spin_lock and selecting ep
- * @ep: endpoint object to set stall on.
+ * usb_ss_gadget_ep_dequeue Remove request from transfer queue
+ * @ep: endpoint object associated with request
+ * @request: request object
+ *
+ * Returns 0 on success, error code elsewhere
  */
-void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep)
+static int usb_ss_gadget_ep_dequeue(struct usb_ep *ep,
+				    struct usb_request *request)
 {
-	struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
-
-	trace_cdns3_halt(priv_ep, 1, 0);
-
-	if (!(priv_ep->flags & EP_STALLED)) {
-		u32 ep_sts_reg = readl(&priv_dev->regs->ep_sts);
+	struct usb_ss_endpoint *usb_ss_ep =
+		to_usb_ss_ep(ep);
+	struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss;
+	struct usb_request *req, *req_temp;
+	unsigned long flags;
 
-		if (!(ep_sts_reg & EP_STS_DBUSY))
-			cdns3_ep_stall_flush(priv_ep);
-		else
-			priv_ep->flags |= EP_STALL_PENDING;
+	spin_lock_irqsave(&usb_ss->lock, flags);
+	if (!usb_ss->start_gadget) {
+		dev_dbg(&usb_ss->dev,
+			"DEQUEUE at disconnection: %s\n", ep->name);
+		spin_unlock_irqrestore(&usb_ss->lock, flags);
+		return 0;
+	}
+	dev_dbg(&usb_ss->dev, "DEQUEUE(%02X) %d\n",
+		usb_ss_ep->address, request->length);
+
+	list_for_each_entry_safe(req, req_temp,
+				 &usb_ss_ep->request_list, list) {
+		if (request == req) {
+			request->status = -ECONNRESET;
+			usb_gadget_unmap_request(&usb_ss->gadget, request,
+						 usb_ss_ep->address &
+						 USB_DIR_IN);
+			list_del_init(&request->list);
+			if (request->complete) {
+				spin_unlock(&usb_ss->lock);
+				usb_gadget_giveback_request
+					(&usb_ss_ep->endpoint, request);
+				spin_lock(&usb_ss->lock);
+			}
+			break;
+		}
 	}
-}
-
-/**
- * __cdns3_gadget_ep_clear_halt Clears stall on selected endpoint
- * Should be called after acquiring spin_lock and selecting ep
- * @ep: endpoint object to clear stall on
- */
-int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep)
-{
-	struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
-	struct usb_request *request;
-	int ret = 0;
-	int val;
-
-	trace_cdns3_halt(priv_ep, 0, 0);
-
-	writel(EP_CMD_CSTALL | EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
-
-	/* wait for EPRST cleared */
-	readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
-				  !(val & EP_CMD_EPRST), 100);
-	if (ret)
-		return -EINVAL;
-
-	priv_ep->flags &= ~(EP_STALLED | EP_STALL_PENDING);
-
-	request = cdns3_next_request(&priv_ep->pending_req_list);
-
-	if (request)
-		cdns3_rearm_transfer(priv_ep, 1);
 
-	cdns3_start_all_request(priv_dev, priv_ep);
-	return ret;
+	spin_unlock_irqrestore(&usb_ss->lock, flags);
+	return 0;
 }
 
 /**
- * cdns3_gadget_ep_set_halt Sets/clears stall on selected endpoint
+ * usb_ss_gadget_ep_set_halt Sets/clears stall on selected endpoint
  * @ep: endpoint object to set/clear stall on
  * @value: 1 for set stall, 0 for clear stall
  *
  * Returns 0 on success, error code elsewhere
  */
-int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value)
+static int usb_ss_gadget_ep_set_halt(struct usb_ep *ep, int value)
 {
-	struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep);
-	struct cdns3_device *priv_dev = priv_ep->cdns3_dev;
+	struct usb_ss_endpoint *usb_ss_ep =
+		to_usb_ss_ep(ep);
+	struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss;
 	unsigned long flags;
-	int ret = 0;
 
-	if (!(priv_ep->flags & EP_ENABLED))
+	/* return error when endpoint disabled */
+	if (!usb_ss_ep->enabled)
 		return -EPERM;
 
-	spin_lock_irqsave(&priv_dev->lock, flags);
+	/* if actual transfer is pending defer setting stall on this endpoint */
+	if (usb_ss_ep->hw_pending_flag && value) {
+		usb_ss_ep->stalled_flag = 1;
+		return 0;
+	}
+
+	dev_dbg(&usb_ss->dev, "HALT(%02X) %d\n", usb_ss_ep->address, value);
 
-	cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress);
+	spin_lock_irqsave(&usb_ss->lock, flags);
 
-	if (!value) {
-		priv_ep->flags &= ~EP_WEDGE;
-		ret = __cdns3_gadget_ep_clear_halt(priv_ep);
+	select_ep(usb_ss, ep->desc->bEndpointAddress);
+	if (value) {
+		cdns_ep_stall_flush(usb_ss_ep);
 	} else {
-		__cdns3_gadget_ep_set_halt(priv_ep);
+		/*
+		 * TODO:
+		 * epp->wedgeFlag = 0;
+		 */
+		usb_ss_ep->wedge_flag = 0;
+		cdns_writel(&usb_ss->regs->ep_cmd,
+			    EP_CMD__CSTALL__MASK | EP_CMD__EPRST__MASK);
+		/* wait for EPRST cleared */
+		while (cdns_readl(&usb_ss->regs->ep_cmd) &
+		       EP_CMD__EPRST__MASK)
+			;
+		usb_ss_ep->stalled_flag = 0;
 	}
+	usb_ss_ep->hw_pending_flag = 0;
 
-	spin_unlock_irqrestore(&priv_dev->lock, flags);
+	spin_unlock_irqrestore(&usb_ss->lock, flags);
 
-	return ret;
+	return 0;
 }
 
-extern const struct usb_ep_ops cdns3_gadget_ep0_ops;
-
-static const struct usb_ep_ops cdns3_gadget_ep_ops = {
-	.enable = cdns3_gadget_ep_enable,
-	.disable = cdns3_gadget_ep_disable,
-	.alloc_request = cdns3_gadget_ep_alloc_request,
-	.free_request = cdns3_gadget_ep_free_request,
-	.queue = cdns3_gadget_ep_queue,
-	.dequeue = cdns3_gadget_ep_dequeue,
-	.set_halt = cdns3_gadget_ep_set_halt,
-	.set_wedge = cdns3_gadget_ep_set_wedge,
-};
-
 /**
- * cdns3_gadget_get_frame Returns number of actual ITP frame
- * @gadget: gadget object
+ * usb_ss_gadget_ep_set_wedge Set wedge on selected endpoint
+ * @ep: endpoint object
  *
- * Returns number of actual ITP frame
+ * Returns 0
  */
-static int cdns3_gadget_get_frame(struct usb_gadget *gadget)
+static int usb_ss_gadget_ep_set_wedge(struct usb_ep *ep)
 {
-	struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
+	struct usb_ss_endpoint *usb_ss_ep = to_usb_ss_ep(ep);
+	struct usb_ss_dev __maybe_unused *usb_ss = usb_ss_ep->usb_ss;
 
-	return readl(&priv_dev->regs->usb_itpn);
+	dev_dbg(&usb_ss->dev, "WEDGE(%02X)\n", usb_ss_ep->address);
+	usb_ss_gadget_ep_set_halt(ep, 1);
+	usb_ss_ep->wedge_flag = 1;
+	return 0;
 }
 
-int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev)
-{
-	enum usb_device_speed speed;
-
-	speed = cdns3_get_speed(priv_dev);
-
-	if (speed >= USB_SPEED_SUPER)
-		return 0;
-
-	/* Start driving resume signaling to indicate remote wakeup. */
-	writel(USB_CONF_LGO_L0, &priv_dev->regs->usb_conf);
+static const struct usb_ep_ops usb_ss_gadget_ep0_ops = {
+	.enable = usb_ss_gadget_ep0_enable,
+	.disable = usb_ss_gadget_ep0_disable,
+	.alloc_request = usb_ss_gadget_ep_alloc_request,
+	.free_request = usb_ss_gadget_ep_free_request,
+	.queue = usb_ss_gadget_ep0_queue,
+	.dequeue = usb_ss_gadget_ep_dequeue,
+	.set_halt = usb_ss_gadget_ep0_set_halt,
+	.set_wedge = usb_ss_gadget_ep_set_wedge,
+};
 
-	return 0;
-}
+static const struct usb_ep_ops usb_ss_gadget_ep_ops = {
+	.enable = usb_ss_gadget_ep_enable,
+	.disable = usb_ss_gadget_ep_disable,
+	.alloc_request = usb_ss_gadget_ep_alloc_request,
+	.free_request = usb_ss_gadget_ep_free_request,
+	.queue = usb_ss_gadget_ep_queue,
+	.dequeue = usb_ss_gadget_ep_dequeue,
+	.set_halt = usb_ss_gadget_ep_set_halt,
+	.set_wedge = usb_ss_gadget_ep_set_wedge,
+};
 
-static int cdns3_gadget_wakeup(struct usb_gadget *gadget)
+/**
+ * usb_ss_gadget_get_frame Returns number of actual ITP frame
+ * @gadget: gadget object
+ *
+ * Returns number of actual ITP frame
+ */
+static int usb_ss_gadget_get_frame(struct usb_gadget *gadget)
 {
-	struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
-	unsigned long flags;
-	int ret = 0;
+	struct usb_ss_dev *usb_ss = gadget_to_usb_ss(gadget);
 
-	spin_lock_irqsave(&priv_dev->lock, flags);
-	ret = __cdns3_gadget_wakeup(priv_dev);
-	spin_unlock_irqrestore(&priv_dev->lock, flags);
-	return ret;
+	dev_dbg(&usb_ss->dev, "%s\n", __func__);
+	return cdns_readl(&usb_ss->regs->usb_iptn);
 }
 
-static int cdns3_gadget_set_selfpowered(struct usb_gadget *gadget,
-					int is_selfpowered)
+static int usb_ss_gadget_wakeup(struct usb_gadget *gadget)
 {
-	struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
-	unsigned long flags;
+	struct usb_ss_dev __maybe_unused *usb_ss = gadget_to_usb_ss(gadget);
 
-	spin_lock_irqsave(&priv_dev->lock, flags);
-	priv_dev->is_selfpowered = !!is_selfpowered;
-	spin_unlock_irqrestore(&priv_dev->lock, flags);
+	dev_dbg(&usb_ss->dev, "%s\n", __func__);
 	return 0;
 }
 
-static int cdns3_gadget_pullup(struct usb_gadget *gadget, int is_on)
+static int usb_ss_gadget_set_selfpowered(struct usb_gadget *gadget,
+					 int is_selfpowered)
 {
-	struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
-
-	if (is_on)
-		writel(USB_CONF_DEVEN, &priv_dev->regs->usb_conf);
-	else
-		writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf);
+	struct usb_ss_dev __maybe_unused *usb_ss = gadget_to_usb_ss(gadget);
 
+	dev_dbg(&usb_ss->dev, "%s: %d\n", __func__, is_selfpowered);
 	return 0;
 }
 
-static void cdns3_gadget_config(struct cdns3_device *priv_dev)
+static int usb_ss_gadget_pullup(struct usb_gadget *gadget, int is_on)
 {
-	struct cdns3_usb_regs __iomem *regs = priv_dev->regs;
-	u32 reg;
+	struct usb_ss_dev *usb_ss = gadget_to_usb_ss(gadget);
+	struct usb_ep *ep;
 
-	cdns3_ep0_config(priv_dev);
+	if (!usb_ss->start_gadget)
+		return 0;
 
-	/* enable interrupts for endpoint 0 (in and out) */
-	writel(EP_IEN_EP_OUT0 | EP_IEN_EP_IN0, &regs->ep_ien);
+	dev_dbg(&usb_ss->dev, "%s: %d\n", __func__, is_on);
 
-	/*
-	 * Driver needs to modify LFPS minimal U1 Exit time for DEV_VER_TI_V1
-	 * revision of controller.
-	 */
-	if (priv_dev->dev_ver == DEV_VER_TI_V1) {
-		reg = readl(&regs->dbg_link1);
+	if (is_on) {
+		cdns_writel(&usb_ss->regs->usb_conf, USB_CONF__DEVEN__MASK);
+	} else {
+		list_for_each_entry(ep,
+			&usb_ss->gadget.ep_list,
+			ep_list) {
+			if (to_usb_ss_ep(ep)->enabled)
+				cdns3_disable_reset_ep(usb_ss, to_usb_ss_ep(ep));
+		}
 
-		reg &= ~DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK;
-		reg |= DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(0x55) |
-		       DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET;
-		writel(reg, &regs->dbg_link1);
+		cdns_writel(&usb_ss->regs->usb_conf, USB_CONF__DEVDS__MASK);
 	}
-
-	/*
-	 * By default some platforms has set protected access to memory.
-	 * This cause problem with cache, so driver restore non-secure
-	 * access to memory.
-	 */
-	reg = readl(&regs->dma_axi_ctrl);
-	reg |= DMA_AXI_CTRL_MARPROT(DMA_AXI_CTRL_NON_SECURE) |
-	       DMA_AXI_CTRL_MAWPROT(DMA_AXI_CTRL_NON_SECURE);
-	writel(reg, &regs->dma_axi_ctrl);
-
-	/* enable generic interrupt*/
-	writel(USB_IEN_INIT, &regs->usb_ien);
-	writel(USB_CONF_CLK2OFFDS | USB_CONF_L1DS, &regs->usb_conf);
-
-	cdns3_configure_dmult(priv_dev, NULL);
-
-	cdns3_gadget_pullup(&priv_dev->gadget, 1);
+	return 0;
 }
 
 /**
- * cdns3_gadget_udc_start Gadget start
+ * usb_ss_gadget_udc_start Gadget start
  * @gadget: gadget object
  * @driver: driver which operates on this gadget
  *
  * Returns 0 on success, error code elsewhere
  */
-static int cdns3_gadget_udc_start(struct usb_gadget *gadget,
-				  struct usb_gadget_driver *driver)
+static int usb_ss_gadget_udc_start(struct usb_gadget *gadget,
+				   struct usb_gadget_driver *driver)
 {
-	struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
+	struct usb_ss_dev *usb_ss = gadget_to_usb_ss(gadget);
 	unsigned long flags;
 
-	spin_lock_irqsave(&priv_dev->lock, flags);
-	priv_dev->gadget_driver = driver;
-	cdns3_gadget_config(priv_dev);
-	spin_unlock_irqrestore(&priv_dev->lock, flags);
+	if (usb_ss->gadget_driver) {
+		dev_err(&usb_ss->dev, "%s is already bound\n",
+			usb_ss->gadget.name);
+		return -EBUSY;
+	}
+
+	dev_dbg(&usb_ss->dev, "%s begins\n", __func__);
+
+	spin_lock_irqsave(&usb_ss->lock, flags);
+	usb_ss->gadget_driver = driver;
+	if (!usb_ss->start_gadget) {
+		spin_unlock_irqrestore(&usb_ss->lock, flags);
+		return 0;
+	}
+
+	__cdns3_gadget_start(usb_ss);
+	spin_unlock_irqrestore(&usb_ss->lock, flags);
+	dev_dbg(&usb_ss->dev, "%s ends\n", __func__);
+
 	return 0;
 }
 
 /**
- * cdns3_gadget_udc_stop Stops gadget
+ * usb_ss_gadget_udc_stop Stops gadget
  * @gadget: gadget object
  *
  * Returns 0
  */
-static int cdns3_gadget_udc_stop(struct usb_gadget *gadget)
+static int usb_ss_gadget_udc_stop(struct usb_gadget *gadget)
 {
-	struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
-	struct cdns3_endpoint *priv_ep;
-	u32 bEndpointAddress;
+	struct usb_ss_dev *usb_ss = gadget_to_usb_ss(gadget);
 	struct usb_ep *ep;
-	int ret = 0;
-	int val;
-
-	priv_dev->gadget_driver = NULL;
+	struct usb_ss_endpoint *usb_ss_ep;
+	int i;
+	u32 bEndpointAddress;
 
-	priv_dev->onchip_used_size = 0;
-	priv_dev->out_mem_is_allocated = 0;
-	priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
+	usb_ss->gadget_driver = NULL;
+	if (!usb_ss->start_gadget)
+		return 0;
 
-	list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) {
-		priv_ep = ep_to_cdns3_ep(ep);
-		bEndpointAddress = priv_ep->num | priv_ep->dir;
-		cdns3_select_ep(priv_dev, bEndpointAddress);
-		writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd);
-		readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val,
-					  !(val & EP_CMD_EPRST), 100);
+	list_for_each_entry(ep, &usb_ss->gadget.ep_list, ep_list) {
+		usb_ss_ep = to_usb_ss_ep(ep);
+		bEndpointAddress = usb_ss_ep->num | usb_ss_ep->dir;
+		usb_ss_ep->used = false;
+		select_ep(usb_ss, bEndpointAddress);
+		cdns_writel(&usb_ss->regs->ep_cmd, EP_CMD__EPRST__MASK);
+		while (cdns_readl(&usb_ss->regs->ep_cmd)
+			& EP_CMD__EPRST__MASK)
+			;
 	}
 
 	/* disable interrupt for device */
-	writel(0, &priv_dev->regs->usb_ien);
-	writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf);
+	cdns_writel(&usb_ss->regs->usb_ien, 0);
+	cdns_writel(&usb_ss->regs->usb_conf, USB_CONF__DEVDS__MASK);
 
-	return ret;
+	for (i = 0; i < usb_ss->ep_nums ; i++)
+		usb_ss_free_trb_pool(usb_ss->eps[i]);
+
+	return 0;
 }
 
-static void cdns3_gadget_udc_set_speed(struct usb_gadget *gadget,
-				       enum usb_device_speed speed)
+static void cdns3_gadget_set_speed(struct usb_gadget *g,
+				   enum usb_device_speed speed)
 {
-	struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget);
-
-	switch (speed) {
-	case USB_SPEED_FULL:
-		writel(USB_CONF_SFORCE_FS, &priv_dev->regs->usb_conf);
-		writel(USB_CONF_USB3DIS, &priv_dev->regs->usb_conf);
-		break;
-	case USB_SPEED_HIGH:
-		writel(USB_CONF_USB3DIS, &priv_dev->regs->usb_conf);
-		break;
-	case USB_SPEED_SUPER:
-		break;
-	default:
-		dev_err(priv_dev->dev, "invalid speed parameter %d\n", speed);
-	}
+	struct usb_ss_dev *usb_ss = gadget_to_usb_ss(g);
 
-	priv_dev->gadget.speed = speed;
+	usb_ss->gadget.max_speed = speed;
 }
 
-static const struct usb_gadget_ops cdns3_gadget_ops = {
-	.get_frame = cdns3_gadget_get_frame,
-	.wakeup = cdns3_gadget_wakeup,
-	.set_selfpowered = cdns3_gadget_set_selfpowered,
-	.pullup = cdns3_gadget_pullup,
-	.udc_start = cdns3_gadget_udc_start,
-	.udc_stop = cdns3_gadget_udc_stop,
-	.match_ep = cdns3_gadget_match_ep,
-	.udc_set_speed = cdns3_gadget_udc_set_speed,
-};
+static const struct usb_gadget_ops usb_ss_gadget_ops = {
+	.get_frame = usb_ss_gadget_get_frame,
+	.wakeup = usb_ss_gadget_wakeup,
+	.set_selfpowered = usb_ss_gadget_set_selfpowered,
+	.pullup = usb_ss_gadget_pullup,
+	.udc_start = usb_ss_gadget_udc_start,
+	.udc_stop = usb_ss_gadget_udc_stop,
+	.ep_conf = usb_ss_gadget_ep_conf,
+	.udc_set_speed = cdns3_gadget_set_speed,
 
-static void cdns3_free_all_eps(struct cdns3_device *priv_dev)
-{
-	int i;
-
-	/* ep0 OUT point to ep0 IN. */
-	priv_dev->eps[16] = NULL;
-
-	for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++)
-		if (priv_dev->eps[i]) {
-			cdns3_free_trb_pool(priv_dev->eps[i]);
-			devm_kfree(priv_dev->dev, priv_dev->eps[i]);
-		}
-}
+};
 
 /**
- * cdns3_init_eps Initializes software endpoints of gadget
- * @cdns3: extended gadget object
+ * usb_ss_init_ep Initializes software endpoints of gadget
+ * @usb_ss: extended gadget object
  *
  * Returns 0 on success, error code elsewhere
  */
-static int cdns3_init_eps(struct cdns3_device *priv_dev)
+static int usb_ss_init_ep(struct usb_ss_dev *usb_ss)
 {
-	u32 ep_enabled_reg, iso_ep_reg;
-	struct cdns3_endpoint *priv_ep;
-	int ep_dir, ep_number;
-	u32 ep_mask;
-	int ret = 0;
+	struct usb_ss_endpoint *usb_ss_ep;
+	u32 ep_enabled_reg, iso_ep_reg, bulk_ep_reg;
 	int i;
+	int ep_reg_pos, ep_dir, ep_number;
+	int found_endpoints = 0;
 
 	/* Read it from USB_CAP3 to USB_CAP5 */
-	ep_enabled_reg = readl(&priv_dev->regs->usb_cap3);
-	iso_ep_reg = readl(&priv_dev->regs->usb_cap4);
+	ep_enabled_reg = 0x00ff00ff;
+	iso_ep_reg = 0x00fe00fe;
+	bulk_ep_reg = 0x00fe00fe;
 
-	dev_dbg(priv_dev->dev, "Initializing non-zero endpoints\n");
+	dev_dbg(&usb_ss->dev, "Initializing non-zero endpoints\n");
+	dev_dbg(&usb_ss->dev,
+		"ep_enabled_reg: 0x%x, iso_ep_reg: 0x%x, bulk_ep_reg:0x%x\n",
+		ep_enabled_reg, iso_ep_reg, bulk_ep_reg);
 
-	for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++) {
-		ep_dir = i >> 4;	/* i div 16 */
-		ep_number = i & 0xF;	/* i % 16 */
-		ep_mask = BIT(i);
+	for (i = 0; i < USB_SS_ENDPOINTS_MAX_COUNT; i++) {
+		ep_number = (i / 2) + 1;
+		ep_dir = i % 2;
+		ep_reg_pos = (16 * ep_dir) + ep_number;
 
-		if (!(ep_enabled_reg & ep_mask))
+		if (!(ep_enabled_reg & (1uL << ep_reg_pos)))
 			continue;
 
-		if (ep_dir && !ep_number) {
-			priv_dev->eps[i] = priv_dev->eps[0];
-			continue;
-		}
-
-		priv_ep = devm_kzalloc(priv_dev->dev, sizeof(*priv_ep),
-				       GFP_KERNEL);
-		if (!priv_ep) {
-			ret = -ENOMEM;
-			goto err;
-		}
+		/* create empty endpoint object */
+		usb_ss_ep = devm_kzalloc(&usb_ss->dev, sizeof(*usb_ss_ep),
+					 GFP_KERNEL);
+		if (!usb_ss_ep)
+			return -ENOMEM;
 
 		/* set parent of endpoint object */
-		priv_ep->cdns3_dev = priv_dev;
-		priv_dev->eps[i] = priv_ep;
-		priv_ep->num = ep_number;
-		priv_ep->dir = ep_dir ? USB_DIR_IN : USB_DIR_OUT;
-
-		if (!ep_number) {
-			ret = cdns3_init_ep0(priv_dev, priv_ep);
-			if (ret) {
-				dev_err(priv_dev->dev, "Failed to init ep0\n");
-				goto err;
-			}
-		} else {
-			snprintf(priv_ep->name, sizeof(priv_ep->name), "ep%d%s",
-				 ep_number, !!ep_dir ? "in" : "out");
-			priv_ep->endpoint.name = priv_ep->name;
-
-			usb_ep_set_maxpacket_limit(&priv_ep->endpoint,
-						   CDNS3_EP_MAX_PACKET_LIMIT);
-			priv_ep->endpoint.max_streams = CDNS3_EP_MAX_STREAMS;
-			priv_ep->endpoint.ops = &cdns3_gadget_ep_ops;
-			if (ep_dir)
-				priv_ep->endpoint.caps.dir_in = 1;
-			else
-				priv_ep->endpoint.caps.dir_out = 1;
-
-			if (iso_ep_reg & ep_mask)
-				priv_ep->endpoint.caps.type_iso = 1;
+		usb_ss_ep->usb_ss = usb_ss;
+
+		/* set index of endpoint in endpoints container */
+		usb_ss->eps[found_endpoints++] = usb_ss_ep;
+
+		/* set name of endpoint */
+		snprintf(usb_ss_ep->name, sizeof(usb_ss_ep->name), "ep%d%s",
+			 ep_number, !!ep_dir ? "in" : "out");
+		usb_ss_ep->endpoint.name = usb_ss_ep->name;
+		dev_dbg(&usb_ss->dev, "Initializing endpoint: %s\n",
+			usb_ss_ep->name);
+
+		usb_ep_set_maxpacket_limit(&usb_ss_ep->endpoint,
+					   ENDPOINT_MAX_PACKET_LIMIT);
+		usb_ss_ep->endpoint.max_streams = ENDPOINT_MAX_STREAMS;
+		usb_ss_ep->endpoint.ops = &usb_ss_gadget_ep_ops;
+		if (ep_dir)
+			usb_ss_ep->caps.dir_in = 1;
+		else
+			usb_ss_ep->caps.dir_out = 1;
 
-			priv_ep->endpoint.caps.type_bulk = 1;
-			priv_ep->endpoint.caps.type_int = 1;
+		/* check endpoint type */
+		if (iso_ep_reg & (1uL << ep_reg_pos))
+			usb_ss_ep->caps.type_iso = 1;
 
-			list_add_tail(&priv_ep->endpoint.ep_list,
-				      &priv_dev->gadget.ep_list);
+		if (bulk_ep_reg & (1uL << ep_reg_pos)) {
+			usb_ss_ep->caps.type_bulk = 1;
+			usb_ss_ep->caps.type_int = 1;
+			usb_ss_ep->endpoint.maxburst = 15;
 		}
 
-		priv_ep->flags = 0;
-
-		dev_info(priv_dev->dev, "Initialized  %s support: %s %s\n",
-			 priv_ep->name,
-			 priv_ep->endpoint.caps.type_bulk ? "BULK, INT" : "",
-			 priv_ep->endpoint.caps.type_iso ? "ISO" : "");
-
-		INIT_LIST_HEAD(&priv_ep->pending_req_list);
-		INIT_LIST_HEAD(&priv_ep->deferred_req_list);
-		INIT_LIST_HEAD(&priv_ep->wa2_descmiss_req_list);
+		list_add_tail(&usb_ss_ep->endpoint.ep_list,
+			      &usb_ss->gadget.ep_list);
+		INIT_LIST_HEAD(&usb_ss_ep->request_list);
+		INIT_LIST_HEAD(&usb_ss_ep->ep_match_pending_list);
 	}
+	usb_ss->ep_nums = found_endpoints;
 
 	return 0;
-err:
-	cdns3_free_all_eps(priv_dev);
-	return -ENOMEM;
 }
 
-void cdns3_gadget_exit(struct cdns3 *cdns)
+/**
+ * usb_ss_init_ep0 Initializes software endpoint 0 of gadget
+ * @usb_ss: extended gadget object
+ *
+ * Returns 0 on success, error code elsewhere
+ */
+static int usb_ss_init_ep0(struct usb_ss_dev *usb_ss)
 {
-	struct cdns3_device *priv_dev;
-
-	priv_dev = cdns->gadget_dev;
-
-	usb_del_gadget_udc(&priv_dev->gadget);
+	struct usb_ss_endpoint *ep0;
 
-	cdns3_free_all_eps(priv_dev);
+	dev_dbg(&usb_ss->dev, "Initializing EP0\n");
+	ep0 = devm_kzalloc(&usb_ss->dev, sizeof(struct usb_ss_endpoint),
+			   GFP_KERNEL);
 
-	while (!list_empty(&priv_dev->aligned_buf_list)) {
-		struct cdns3_aligned_buf *buf;
-
-		buf = cdns3_next_align_buf(&priv_dev->aligned_buf_list);
-		dma_free_coherent(buf->buf);
-
-		list_del(&buf->list);
-		kfree(buf);
-	}
+	if (!ep0)
+		return -ENOMEM;
 
-	dma_free_coherent(priv_dev->setup_buf);
+	/* fill CDNS fields */
+	ep0->usb_ss = usb_ss;
+	sprintf(ep0->name, "ep0");
+
+	/* fill linux fields */
+	ep0->endpoint.ops = &usb_ss_gadget_ep0_ops;
+	ep0->endpoint.maxburst = 1;
+	usb_ep_set_maxpacket_limit(&ep0->endpoint, ENDPOINT0_MAX_PACKET_LIMIT);
+	ep0->address = 0;
+	ep0->enabled = 1;
+	ep0->caps.type_control = 1;
+	ep0->caps.dir_in = 1;
+	ep0->caps.dir_out = 1;
+	ep0->endpoint.name = ep0->name;
+	ep0->endpoint.desc = &cdns3_gadget_ep0_desc;
+	usb_ss->gadget.ep0 = &ep0->endpoint;
+	INIT_LIST_HEAD(&ep0->request_list);
 
-	kfree(priv_dev->zlp_buf);
-	kfree(priv_dev);
-	cdns->gadget_dev = NULL;
-	cdns3_drd_switch_gadget(cdns, 0);
+	return 0;
 }
 
-static int cdns3_gadget_start(struct cdns3 *cdns)
+static int __cdns3_gadget_init(struct cdns3 *cdns)
 {
-	struct cdns3_device *priv_dev;
-	u32 max_speed;
+	struct usb_ss_dev *usb_ss;
 	int ret;
+	struct udevice *dev;
+	struct cdns3_generic_peripheral *priv = container_of(cdns,
+				struct cdns3_generic_peripheral, cdns3);
+
+	usb_ss = &priv->usb_ss_dev;
+	dev = &usb_ss->dev;
+	dev->parent = cdns->dev;
+	dev_set_name(dev, "gadget-cdns3-dev");
+	cdns->gadget_dev = dev;
+	usb_ss->sysdev = cdns->dev;
+	ret = device_register(dev);
+	if (ret)
+		goto err1;
 
-	priv_dev = kzalloc(sizeof(*priv_dev), GFP_KERNEL);
-	if (!priv_dev)
-		return -ENOMEM;
-
-	cdns->gadget_dev = priv_dev;
-	priv_dev->sysdev = cdns->dev;
-	priv_dev->dev = cdns->dev;
-	priv_dev->regs = cdns->dev_regs;
-
-	dev_read_u32(priv_dev->dev, "cdns,on-chip-buff-size",
-		     &priv_dev->onchip_buffers);
-
-	if (priv_dev->onchip_buffers <=  0) {
-		u32 reg = readl(&priv_dev->regs->usb_cap2);
-
-		priv_dev->onchip_buffers = USB_CAP2_ACTUAL_MEM_SIZE(reg);
-	}
-
-	if (!priv_dev->onchip_buffers)
-		priv_dev->onchip_buffers = 256;
-
-	max_speed = usb_get_maximum_speed(dev_ofnode(cdns->dev));
-
-	/* Check the maximum_speed parameter */
-	switch (max_speed) {
-	case USB_SPEED_FULL:
-		/* fall through */
-	case USB_SPEED_HIGH:
-		/* fall through */
-	case USB_SPEED_SUPER:
-		break;
-	default:
-		dev_err(cdns->dev, "invalid maximum_speed parameter %d\n",
-			max_speed);
-		/* fall through */
-	case USB_SPEED_UNKNOWN:
-		/* default to superspeed */
-		max_speed = USB_SPEED_SUPER;
-		break;
-	}
+	usb_ss->regs = cdns->dev_regs;
 
 	/* fill gadget fields */
-	priv_dev->gadget.max_speed = max_speed;
-	priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
-	priv_dev->gadget.ops = &cdns3_gadget_ops;
-	priv_dev->gadget.name = "cdns3-gadget";
-#ifndef __UBOOT__
-	priv_dev->gadget.name = "usb-ss-gadget";
-	priv_dev->gadget.sg_supported = 1;
-	priv_dev->gadget.quirk_avoids_skb_reserve = 1;
-#endif
+	usb_ss->gadget.ops = &usb_ss_gadget_ops;
+	usb_ss->gadget.max_speed = USB_SPEED_SUPER;
+	usb_ss->gadget.speed = USB_SPEED_UNKNOWN;
+	usb_ss->gadget.name = "cdns3-gadget";
+	usb_ss->is_connected = 0;
+	spin_lock_init(&usb_ss->lock);
 
-	spin_lock_init(&priv_dev->lock);
-	INIT_WORK(&priv_dev->pending_status_wq,
-		  cdns3_pending_setup_status_handler);
+	usb_ss->in_standby_mode = 1;
 
 	/* initialize endpoint container */
-	INIT_LIST_HEAD(&priv_dev->gadget.ep_list);
-	INIT_LIST_HEAD(&priv_dev->aligned_buf_list);
-
-	ret = cdns3_init_eps(priv_dev);
+	INIT_LIST_HEAD(&usb_ss->gadget.ep_list);
+	INIT_LIST_HEAD(&usb_ss->ep_match_list);
+	ret = usb_ss_init_ep0(usb_ss);
 	if (ret) {
-		dev_err(priv_dev->dev, "Failed to create endpoints\n");
-		goto err1;
+		dev_err(dev, "Failed to create endpoint 0\n");
+		ret = -ENOMEM;
+		goto err2;
 	}
 
-	/* allocate memory for setup packet buffer */
-	priv_dev->setup_buf =
-		dma_alloc_coherent(8, (unsigned long *)&priv_dev->setup_dma);
-	if (!priv_dev->setup_buf) {
+	ret = usb_ss_init_ep(usb_ss);
+	if (ret) {
+		dev_err(dev, "Failed to create non zero endpoints\n");
 		ret = -ENOMEM;
 		goto err2;
 	}
 
-	priv_dev->dev_ver = readl(&priv_dev->regs->usb_cap6);
-
-	dev_dbg(priv_dev->dev, "Device Controller version: %08x\n",
-		readl(&priv_dev->regs->usb_cap6));
-	dev_dbg(priv_dev->dev, "USB Capabilities:: %08x\n",
-		readl(&priv_dev->regs->usb_cap1));
-	dev_dbg(priv_dev->dev, "On-Chip memory cnfiguration: %08x\n",
-		readl(&priv_dev->regs->usb_cap2));
-
-	priv_dev->dev_ver = GET_DEV_BASE_VERSION(priv_dev->dev_ver);
+	/* allocate memory for default endpoint TRB */
+	usb_ss->trb_ep0 = (u32 *)dma_alloc_coherent(20,
+				(unsigned long *)&usb_ss->trb_ep0_dma);
+	if (!usb_ss->trb_ep0) {
+		dev_err(dev, "Failed to allocate memory for ep0 TRB\n");
+		ret = -ENOMEM;
+		goto err2;
+	}
 
-	priv_dev->zlp_buf = kzalloc(CDNS3_EP_ZLP_BUF_SIZE, GFP_KERNEL);
-	if (!priv_dev->zlp_buf) {
+	/* allocate memory for setup packet buffer */
+	usb_ss->setup = (u8 *)dma_alloc_coherent(8,
+			      (unsigned long *)&usb_ss->setup_dma);
+	if (!usb_ss->setup) {
+		dev_err(dev, "Failed to allocate memory for SETUP buffer\n");
 		ret = -ENOMEM;
 		goto err3;
 	}
 
 	/* add USB gadget device */
-	ret = usb_add_gadget_udc((struct device *)priv_dev->dev,
-				 &priv_dev->gadget);
+	ret = usb_add_gadget_udc((struct device *)(&usb_ss->dev),
+				 &usb_ss->gadget);
 	if (ret < 0) {
-		dev_err(priv_dev->dev,
-			"Failed to register USB device controller\n");
+		dev_err(dev, "Failed to register USB device controller\n");
 		goto err4;
 	}
 
 	return 0;
+
 err4:
-	kfree(priv_dev->zlp_buf);
+	dma_free_coherent(usb_ss->setup);
 err3:
-	dma_free_coherent(priv_dev->setup_buf);
+	dma_free_coherent(usb_ss->trb_ep0);
 err2:
-	cdns3_free_all_eps(priv_dev);
 err1:
 	cdns->gadget_dev = NULL;
+
 	return ret;
 }
 
-static int __cdns3_gadget_init(struct cdns3 *cdns)
+/**
+ * cdns3_gadget_remove: parent must call this to remove UDC
+ *
+ * cdns: cdns3 instance
+ *
+ */
+void cdns3_gadget_remove(struct cdns3 *cdns)
 {
-	int ret = 0;
+	struct usb_ss_dev *usb_ss;
 
-	cdns3_drd_switch_gadget(cdns, 1);
-
-	ret = cdns3_gadget_start(cdns);
-	if (ret)
-		return ret;
+	if (!cdns->roles[CDNS3_ROLE_GADGET])
+		return;
 
-	return 0;
+	usb_ss = container_of(cdns->gadget_dev, struct usb_ss_dev, dev);
+	usb_del_gadget_udc(&usb_ss->gadget);
+	dma_free_coherent(usb_ss->setup);
+	dma_free_coherent(usb_ss->trb_ep0);
+	device_unregister(cdns->gadget_dev);
+	cdns->gadget_dev = NULL;
 }
 
-static int cdns3_gadget_suspend(struct cdns3 *cdns, bool do_wakeup)
+static void __cdns3_gadget_start(struct usb_ss_dev *usb_ss)
 {
-	struct cdns3_device *priv_dev = cdns->gadget_dev;
+	u32 usb_conf_reg = 0;
 
-	cdns3_disconnect_gadget(priv_dev);
+	/* configure endpoint 0 hardware */
+	cdns_ep0_config(usb_ss);
 
-	priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
-	usb_gadget_set_state(&priv_dev->gadget, USB_STATE_NOTATTACHED);
-	cdns3_hw_reset_eps_config(priv_dev);
+	/* enable interrupts for endpoint 0 (in and out) */
+	cdns_writel(&usb_ss->regs->ep_ien,
+		    EP_IEN__EOUTEN0__MASK | EP_IEN__EINEN0__MASK);
+
+	/* enable interrupt for device */
+	cdns_writel(&usb_ss->regs->usb_ien,
+		    USB_IEN__U2RESIEN__MASK
+		    | USB_ISTS__DIS2I__MASK
+		    | USB_IEN__CON2IEN__MASK
+		    | USB_IEN__UHRESIEN__MASK
+		    | USB_IEN__UWRESIEN__MASK
+		    | USB_IEN__DISIEN__MASK
+		    | USB_IEN__CONIEN__MASK
+		    | USB_IEN__U3EXTIEN__MASK
+		    | USB_IEN__L2ENTIEN__MASK
+		    | USB_IEN__L2EXTIEN__MASK);
+
+	usb_conf_reg = USB_CONF__CLK2OFFDS__MASK |
+			USB_CONF__L1DS__MASK;
+	if (usb_ss->gadget.max_speed == USB_SPEED_HIGH)
+		usb_conf_reg |= USB_CONF__USB3DIS__MASK;
+	cdns_writel(&usb_ss->regs->usb_conf, usb_conf_reg);
+
+	cdns_writel(&usb_ss->regs->usb_conf,
+		    USB_CONF__U1DS__MASK
+		    | USB_CONF__U2DS__MASK
+			);
+
+	cdns_writel(&usb_ss->regs->usb_conf, USB_CONF__DEVEN__MASK);
+
+	cdns_writel(&usb_ss->regs->dbg_link1,
+		    DBG_LINK1__LFPS_MIN_GEN_U1_EXIT_SET__MASK |
+		    DBG_LINK1__LFPS_MIN_GEN_U1_EXIT__WRITE(0x3C));
+}
 
-	/* disable interrupt for device */
-	writel(0, &priv_dev->regs->usb_ien);
+static int cdns3_gadget_start(struct cdns3 *cdns)
+{
+	struct usb_ss_dev *usb_ss = container_of(cdns->gadget_dev,
+			struct usb_ss_dev, dev);
+	unsigned long flags;
 
-	cdns3_gadget_pullup(&priv_dev->gadget, 0);
+	dev_dbg(&usb_ss->dev, "%s begins\n", __func__);
+
+	pm_runtime_get_sync(cdns->dev);
+	spin_lock_irqsave(&usb_ss->lock, flags);
+	usb_ss->start_gadget = 1;
+	if (!usb_ss->gadget_driver) {
+		spin_unlock_irqrestore(&usb_ss->lock, flags);
+		return 0;
+	}
+
+	__cdns3_gadget_start(usb_ss);
+	usb_ss->in_standby_mode = 0;
+	spin_unlock_irqrestore(&usb_ss->lock, flags);
+	dev_dbg(&usb_ss->dev, "%s ends\n", __func__);
 
 	return 0;
 }
 
-static int cdns3_gadget_resume(struct cdns3 *cdns, bool hibernated)
+static void __cdns3_gadget_stop(struct cdns3 *cdns)
 {
-	struct cdns3_device *priv_dev = cdns->gadget_dev;
-
-	if (!priv_dev->gadget_driver)
-		return 0;
+	struct usb_ss_dev *usb_ss;
+	unsigned long flags;
 
-	cdns3_gadget_config(priv_dev);
+	usb_ss = container_of(cdns->gadget_dev, struct usb_ss_dev, dev);
+	if (usb_ss->gadget_driver)
+		usb_ss->gadget_driver->disconnect(&usb_ss->gadget);
+	usb_gadget_disconnect(&usb_ss->gadget);
+	spin_lock_irqsave(&usb_ss->lock, flags);
+	/* disable interrupt for device */
+	cdns_writel(&usb_ss->regs->usb_ien, 0);
+	cdns_writel(&usb_ss->regs->usb_conf, USB_CONF__DEVDS__MASK);
+	usb_ss->start_gadget = 0;
+	spin_unlock_irqrestore(&usb_ss->lock, flags);
+}
 
-	return 0;
+static void cdns3_gadget_stop(struct cdns3 *cdns)
+{
+	if (cdns->role == CDNS3_ROLE_GADGET)
+		__cdns3_gadget_stop(cdns);
 }
 
 /**
@@ -2729,36 +2231,10 @@ int cdns3_gadget_init(struct cdns3 *cdns)
 	if (!rdrv)
 		return -ENOMEM;
 
-	rdrv->start	= __cdns3_gadget_init;
-	rdrv->stop	= cdns3_gadget_exit;
-	rdrv->suspend	= cdns3_gadget_suspend;
-	rdrv->resume	= cdns3_gadget_resume;
-	rdrv->state	= CDNS3_ROLE_STATE_INACTIVE;
+	rdrv->start	= cdns3_gadget_start;
+	rdrv->stop	= cdns3_gadget_stop;
+	rdrv->irq	= cdns_irq_handler_thread;
 	rdrv->name	= "gadget";
-	cdns->roles[USB_ROLE_DEVICE] = rdrv;
-
-	return 0;
-}
-
-/**
- * cdns3_gadget_uboot_handle_interrupt - handle cdns3 gadget interrupt
- * @cdns: pointer to struct cdns3
- *
- * Handles ep0 and gadget interrupt
- */
-static void cdns3_gadget_uboot_handle_interrupt(struct cdns3 *cdns)
-{
-	int ret = cdns3_device_irq_handler(0, cdns);
-
-	if (ret == IRQ_WAKE_THREAD)
-		cdns3_device_thread_irq_handler(0, cdns);
-}
-
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
-{
-	struct cdns3 *cdns = dev_get_priv(dev);
-
-	cdns3_gadget_uboot_handle_interrupt(cdns);
-
-	return 0;
+	cdns->roles[CDNS3_ROLE_GADGET] = rdrv;
+	return __cdns3_gadget_init(cdns);
 }
diff --git a/drivers/usb/cdns3/gadget.h b/drivers/usb/cdns3/gadget.h
index 8803fa48bd3..e92f283b848 100644
--- a/drivers/usb/cdns3/gadget.h
+++ b/drivers/usb/cdns3/gadget.h
@@ -1,1339 +1,216 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * USBSS device controller driver header file
- *
- * Copyright (C) 2018-2019 Cadence.
- * Copyright (C) 2017-2018 NXP
- *
- * Author: Pawel Laszczak <pawell@cadence.com>
- *         Pawel Jez <pjez@cadence.com>
- *         Peter Chen <peter.chen@nxp.com>
- */
-#ifndef __LINUX_CDNS3_GADGET
-#define __LINUX_CDNS3_GADGET
-#include <linux/bitops.h>
-#include <linux/usb/gadget.h>
-
-/*
- * USBSS-DEV register interface.
- * This corresponds to the USBSS Device Controller Interface
- */
-
-/**
- * struct cdns3_usb_regs - device controller registers.
- * @usb_conf:      Global Configuration.
- * @usb_sts:       Global Status.
- * @usb_cmd:       Global Command.
- * @usb_itpn:      ITP/SOF number.
- * @usb_lpm:       Global Command.
- * @usb_ien:       USB Interrupt Enable.
- * @usb_ists:      USB Interrupt Status.
- * @ep_sel:        Endpoint Select.
- * @ep_traddr:     Endpoint Transfer Ring Address.
- * @ep_cfg:        Endpoint Configuration.
- * @ep_cmd:        Endpoint Command.
- * @ep_sts:        Endpoint Status.
- * @ep_sts_sid:    Endpoint Status.
- * @ep_sts_en:     Endpoint Status Enable.
- * @drbl:          Doorbell.
- * @ep_ien:        EP Interrupt Enable.
- * @ep_ists:       EP Interrupt Status.
- * @usb_pwr:       Global Power Configuration.
- * @usb_conf2:     Global Configuration 2.
- * @usb_cap1:      Capability 1.
- * @usb_cap2:      Capability 2.
- * @usb_cap3:      Capability 3.
- * @usb_cap4:      Capability 4.
- * @usb_cap5:      Capability 5.
- * @usb_cap6:      Capability 6.
- * @usb_cpkt1:     Custom Packet 1.
- * @usb_cpkt2:     Custom Packet 2.
- * @usb_cpkt3:     Custom Packet 3.
- * @ep_dma_ext_addr: Upper address for DMA operations.
- * @buf_addr:      Address for On-chip Buffer operations.
- * @buf_data:      Data for On-chip Buffer operations.
- * @buf_ctrl:      On-chip Buffer Access Control.
- * @dtrans:        DMA Transfer Mode.
- * @tdl_from_trb:  Source of TD Configuration.
- * @tdl_beh:       TDL Behavior Configuration.
- * @ep_tdl:        Endpoint TDL.
- * @tdl_beh2:      TDL Behavior 2 Configuration.
- * @dma_adv_td:    DMA Advance TD Configuration.
- * @reserved1:     Reserved.
- * @cfg_regs:      Configuration.
- * @reserved2:     Reserved.
- * @dma_axi_ctrl:  AXI Control.
- * @dma_axi_id:    AXI ID register.
- * @dma_axi_cap:   AXI Capability.
- * @dma_axi_ctrl0: AXI Control 0.
- * @dma_axi_ctrl1: AXI Control 1.
+ * Copyright (C) 2016 Cadence Design Systems - http://www.cadence.com
+ * Copyright 2019 NXP
  */
-struct cdns3_usb_regs {
-	__le32 usb_conf;
-	__le32 usb_sts;
-	__le32 usb_cmd;
-	__le32 usb_itpn;
-	__le32 usb_lpm;
-	__le32 usb_ien;
-	__le32 usb_ists;
-	__le32 ep_sel;
-	__le32 ep_traddr;
-	__le32 ep_cfg;
-	__le32 ep_cmd;
-	__le32 ep_sts;
-	__le32 ep_sts_sid;
-	__le32 ep_sts_en;
-	__le32 drbl;
-	__le32 ep_ien;
-	__le32 ep_ists;
-	__le32 usb_pwr;
-	__le32 usb_conf2;
-	__le32 usb_cap1;
-	__le32 usb_cap2;
-	__le32 usb_cap3;
-	__le32 usb_cap4;
-	__le32 usb_cap5;
-	__le32 usb_cap6;
-	__le32 usb_cpkt1;
-	__le32 usb_cpkt2;
-	__le32 usb_cpkt3;
-	__le32 ep_dma_ext_addr;
-	__le32 buf_addr;
-	__le32 buf_data;
-	__le32 buf_ctrl;
-	__le32 dtrans;
-	__le32 tdl_from_trb;
-	__le32 tdl_beh;
-	__le32 ep_tdl;
-	__le32 tdl_beh2;
-	__le32 dma_adv_td;
-	__le32 reserved1[26];
-	__le32 cfg_reg1;
-	__le32 dbg_link1;
-	__le32 dbg_link2;
-	__le32 cfg_regs[74];
-	__le32 reserved2[51];
-	__le32 dma_axi_ctrl;
-	__le32 dma_axi_id;
-	__le32 dma_axi_cap;
-	__le32 dma_axi_ctrl0;
-	__le32 dma_axi_ctrl1;
-};
+#ifndef __DRIVERS_CDNS3_GADGET
+#define __DRIVERS_CDNS3_GADGET
 
-/* USB_CONF - bitmasks */
-/* Reset USB device configuration. */
-#define USB_CONF_CFGRST		BIT(0)
-/* Set Configuration. */
-#define USB_CONF_CFGSET		BIT(1)
-/* Disconnect USB device in SuperSpeed. */
-#define USB_CONF_USB3DIS	BIT(3)
-/* Disconnect USB device in HS/FS */
-#define USB_CONF_USB2DIS	BIT(4)
-/* Little Endian access - default */
-#define USB_CONF_LENDIAN	BIT(5)
-/*
- * Big Endian access. Driver assume that byte order for
- * SFRs access always is as Little Endian so this bit
- * is not used.
- */
-#define USB_CONF_BENDIAN	BIT(6)
-/* Device software reset. */
-#define USB_CONF_SWRST		BIT(7)
-/* Singular DMA transfer mode. Only for VER < DEV_VER_V3*/
-#define USB_CONF_DSING		BIT(8)
-/* Multiple DMA transfers mode. Only for VER < DEV_VER_V3 */
-#define USB_CONF_DMULT		BIT(9)
-/* DMA clock turn-off enable. */
-#define USB_CONF_DMAOFFEN	BIT(10)
-/* DMA clock turn-off disable. */
-#define USB_CONF_DMAOFFDS	BIT(11)
-/* Clear Force Full Speed. */
-#define USB_CONF_CFORCE_FS	BIT(12)
-/* Set Force Full Speed. */
-#define USB_CONF_SFORCE_FS	BIT(13)
-/* Device enable. */
-#define USB_CONF_DEVEN		BIT(14)
-/* Device disable. */
-#define USB_CONF_DEVDS		BIT(15)
-/* L1 LPM state entry enable (used in HS/FS mode). */
-#define USB_CONF_L1EN		BIT(16)
-/* L1 LPM state entry disable (used in HS/FS mode). */
-#define USB_CONF_L1DS		BIT(17)
-/* USB 2.0 clock gate disable. */
-#define USB_CONF_CLK2OFFEN	BIT(18)
-/* USB 2.0 clock gate enable. */
-#define USB_CONF_CLK2OFFDS	BIT(19)
-/* L0 LPM state entry request (used in HS/FS mode). */
-#define USB_CONF_LGO_L0		BIT(20)
-/* USB 3.0 clock gate disable. */
-#define USB_CONF_CLK3OFFEN	BIT(21)
-/* USB 3.0 clock gate enable. */
-#define USB_CONF_CLK3OFFDS	BIT(22)
-/* Bit 23 is reserved*/
-/* U1 state entry enable (used in SS mode). */
-#define USB_CONF_U1EN		BIT(24)
-/* U1 state entry disable (used in SS mode). */
-#define USB_CONF_U1DS		BIT(25)
-/* U2 state entry enable (used in SS mode). */
-#define USB_CONF_U2EN		BIT(26)
-/* U2 state entry disable (used in SS mode). */
-#define USB_CONF_U2DS		BIT(27)
-/* U0 state entry request (used in SS mode). */
-#define USB_CONF_LGO_U0		BIT(28)
-/* U1 state entry request (used in SS mode). */
-#define USB_CONF_LGO_U1		BIT(29)
-/* U2 state entry request (used in SS mode). */
-#define USB_CONF_LGO_U2		BIT(30)
-/* SS.Inactive state entry request (used in SS mode) */
-#define USB_CONF_LGO_SSINACT	BIT(31)
+#include "dev-regs-map.h"
 
-/* USB_STS - bitmasks */
-/*
- * Configuration status.
- * 1 - device is in the configured state.
- * 0 - device is not configured.
- */
-#define USB_STS_CFGSTS_MASK	BIT(0)
-#define USB_STS_CFGSTS(p)	((p) & USB_STS_CFGSTS_MASK)
-/*
- * On-chip memory overflow.
- * 0 - On-chip memory status OK.
- * 1 - On-chip memory overflow.
- */
-#define USB_STS_OV_MASK		BIT(1)
-#define USB_STS_OV(p)		((p) & USB_STS_OV_MASK)
-/*
- * SuperSpeed connection status.
- * 0 - USB in SuperSpeed mode disconnected.
- * 1 - USB in SuperSpeed mode connected.
- */
-#define USB_STS_USB3CONS_MASK	BIT(2)
-#define USB_STS_USB3CONS(p)	((p) & USB_STS_USB3CONS_MASK)
-/*
- * DMA transfer configuration status.
- * 0 - single request.
- * 1 - multiple TRB chain
- * Supported only for controller version <  DEV_VER_V3
- */
-#define USB_STS_DTRANS_MASK	BIT(3)
-#define USB_STS_DTRANS(p)	((p) & USB_STS_DTRANS_MASK)
-/*
- * Device speed.
- * 0 - Undefined (value after reset).
- * 1 - Low speed
- * 2 - Full speed
- * 3 - High speed
- * 4 - Super speed
- */
-#define USB_STS_USBSPEED_MASK	GENMASK(6, 4)
-#define USB_STS_USBSPEED(p)	(((p) & USB_STS_USBSPEED_MASK) >> 4)
-#define USB_STS_LS		(0x1 << 4)
-#define USB_STS_FS		(0x2 << 4)
-#define USB_STS_HS		(0x3 << 4)
-#define USB_STS_SS		(0x4 << 4)
-#define DEV_UNDEFSPEED(p)	(((p) & USB_STS_USBSPEED_MASK) == (0x0 << 4))
-#define DEV_LOWSPEED(p)		(((p) & USB_STS_USBSPEED_MASK) == USB_STS_LS)
-#define DEV_FULLSPEED(p)	(((p) & USB_STS_USBSPEED_MASK) == USB_STS_FS)
-#define DEV_HIGHSPEED(p)	(((p) & USB_STS_USBSPEED_MASK) == USB_STS_HS)
-#define DEV_SUPERSPEED(p)	(((p) & USB_STS_USBSPEED_MASK) == USB_STS_SS)
-/*
- * Endianness for SFR access.
- * 0 - Little Endian order (default after hardware reset).
- * 1 - Big Endian order
- */
-#define USB_STS_ENDIAN_MASK	BIT(7)
-#define USB_STS_ENDIAN(p)	((p) & USB_STS_ENDIAN_MASK)
-/*
- * HS/FS clock turn-off status.
- * 0 - hsfs clock is always on.
- * 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled
- *          (default after hardware reset).
- */
-#define USB_STS_CLK2OFF_MASK	BIT(8)
-#define USB_STS_CLK2OFF(p)	((p) & USB_STS_CLK2OFF_MASK)
-/*
- * PCLK clock turn-off status.
- * 0 - pclk clock is always on.
- * 1 - pclk clock turn-off in U3 (SS mode) is enabled
- *          (default after hardware reset).
- */
-#define USB_STS_CLK3OFF_MASK	BIT(9)
-#define USB_STS_CLK3OFF(p)	((p) & USB_STS_CLK3OFF_MASK)
-/*
- * Controller in reset state.
- * 0 - Internal reset is active.
- * 1 - Internal reset is not active and controller is fully operational.
- */
-#define USB_STS_IN_RST_MASK	BIT(10)
-#define USB_STS_IN_RST(p)	((p) & USB_STS_IN_RST_MASK)
-/*
- * Status of the "TDL calculation basing on TRB" feature.
- * 0 - disabled
- * 1 - enabled
- * Supported only for DEV_VER_V2 controller version.
- */
-#define USB_STS_TDL_TRB_ENABLED	BIT(11)
-/*
- * Device enable Status.
- * 0 - USB device is disabled (VBUS input is disconnected from internal logic).
- * 1 - USB device is enabled (VBUS input is connected to the internal logic).
- */
-#define USB_STS_DEVS_MASK	BIT(14)
-#define USB_STS_DEVS(p)		((p) & USB_STS_DEVS_MASK)
-/*
- * Address status.
- * 0 - USB device is default state.
- * 1 - USB device is at least in address state.
- */
-#define USB_STS_ADDRESSED_MASK	BIT(15)
-#define USB_STS_ADDRESSED(p)	((p) & USB_STS_ADDRESSED_MASK)
-/*
- * L1 LPM state enable status (used in HS/FS mode).
- * 0 - Entering to L1 LPM state disabled.
- * 1 - Entering to L1 LPM state enabled.
- */
-#define USB_STS_L1ENS_MASK	BIT(16)
-#define USB_STS_L1ENS(p)	((p) & USB_STS_L1ENS_MASK)
-/*
- * Internal VBUS connection status (used both in HS/FS  and SS mode).
- * 0 - internal VBUS is not detected.
- * 1 - internal VBUS is detected.
- */
-#define USB_STS_VBUSS_MASK	BIT(17)
-#define USB_STS_VBUSS(p)	((p) & USB_STS_VBUSS_MASK)
-/*
- * HS/FS LPM  state (used in FS/HS mode).
- * 0 - L0 State
- * 1 - L1 State
- * 2 - L2 State
- * 3 - L3 State
- */
-#define USB_STS_LPMST_MASK	GENMASK(19, 18)
-#define DEV_L0_STATE(p)		(((p) & USB_STS_LPMST_MASK) == (0x0 << 18))
-#define DEV_L1_STATE(p)		(((p) & USB_STS_LPMST_MASK) == (0x1 << 18))
-#define DEV_L2_STATE(p)		(((p) & USB_STS_LPMST_MASK) == (0x2 << 18))
-#define DEV_L3_STATE(p)		(((p) & USB_STS_LPMST_MASK) == (0x3 << 18))
-/*
- * Disable HS status (used in FS/HS mode).
- * 0 - the disconnect bit for HS/FS mode is set .
- * 1 - the disconnect bit for HS/FS mode is not set.
- */
-#define USB_STS_USB2CONS_MASK	BIT(20)
-#define USB_STS_USB2CONS(p)	((p) & USB_STS_USB2CONS_MASK)
-/*
- * HS/FS mode connection status (used in FS/HS mode).
- * 0 - High Speed operations in USB2.0 (FS/HS) mode not disabled.
- * 1 - High Speed operations in USB2.0 (FS/HS).
- */
-#define USB_STS_DISABLE_HS_MASK	BIT(21)
-#define USB_STS_DISABLE_HS(p)	((p) & USB_STS_DISABLE_HS_MASK)
-/*
- * U1 state enable status (used in SS mode).
- * 0 - Entering to  U1 state disabled.
- * 1 - Entering to  U1 state enabled.
- */
-#define USB_STS_U1ENS_MASK	BIT(24)
-#define USB_STS_U1ENS(p)	((p) & USB_STS_U1ENS_MASK)
-/*
- * U2 state enable status (used in SS mode).
- * 0 - Entering to  U2 state disabled.
- * 1 - Entering to  U2 state enabled.
- */
-#define USB_STS_U2ENS_MASK	BIT(25)
-#define USB_STS_U2ENS(p)	((p) & USB_STS_U2ENS_MASK)
-/*
- * SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current
- * SuperSpeed link state
- */
-#define USB_STS_LST_MASK	GENMASK(29, 26)
-#define DEV_LST_U0		(((p) & USB_STS_LST_MASK) == (0x0 << 26))
-#define DEV_LST_U1		(((p) & USB_STS_LST_MASK) == (0x1 << 26))
-#define DEV_LST_U2		(((p) & USB_STS_LST_MASK) == (0x2 << 26))
-#define DEV_LST_U3		(((p) & USB_STS_LST_MASK) == (0x3 << 26))
-#define DEV_LST_DISABLED	(((p) & USB_STS_LST_MASK) == (0x4 << 26))
-#define DEV_LST_RXDETECT	(((p) & USB_STS_LST_MASK) == (0x5 << 26))
-#define DEV_LST_INACTIVE	(((p) & USB_STS_LST_MASK) == (0x6 << 26))
-#define DEV_LST_POLLING		(((p) & USB_STS_LST_MASK) == (0x7 << 26))
-#define DEV_LST_RECOVERY	(((p) & USB_STS_LST_MASK) == (0x8 << 26))
-#define DEV_LST_HOT_RESET	(((p) & USB_STS_LST_MASK) == (0x9 << 26))
-#define DEV_LST_COMP_MODE	(((p) & USB_STS_LST_MASK) == (0xa << 26))
-#define DEV_LST_LB_STATE	(((p) & USB_STS_LST_MASK) == (0xb << 26))
-/*
- * DMA clock turn-off status.
- * 0 - DMA clock is always on (default after hardware reset).
- * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled.
- */
-#define USB_STS_DMAOFF_MASK	BIT(30)
-#define USB_STS_DMAOFF(p)	((p) & USB_STS_DMAOFF_MASK)
-/*
- * SFR Endian status.
- * 0 - Little Endian order (default after hardware reset).
- * 1 - Big Endian order.
- */
-#define USB_STS_ENDIAN2_MASK	BIT(31)
-#define USB_STS_ENDIAN2(p)	((p) & USB_STS_ENDIAN2_MASK)
-
-/* USB_CMD -  bitmasks */
-/* Set Function Address */
-#define USB_CMD_SET_ADDR	BIT(0)
-/*
- * Function Address This field is saved to the device only when the field
- * SET_ADDR is set '1 ' during write to USB_CMD register.
- * Software is responsible for entering the address of the device during
- * SET_ADDRESS request service. This field should be set immediately after
- * the SETUP packet is decoded, and prior to confirmation of the status phase
- */
-#define USB_CMD_FADDR_MASK	GENMASK(7, 1)
-#define USB_CMD_FADDR(p)	(((p) << 1) & USB_CMD_FADDR_MASK)
-/* Send Function Wake Device Notification TP (used only in SS mode). */
-#define USB_CMD_SDNFW		BIT(8)
-/* Set Test Mode (used only in HS/FS mode). */
-#define USB_CMD_STMODE		BIT(9)
-/* Test mode selector (used only in HS/FS mode) */
-#define USB_STS_TMODE_SEL_MASK	GENMASK(11, 10)
-#define USB_STS_TMODE_SEL(p)	(((p) << 10) & USB_STS_TMODE_SEL_MASK)
-/*
- *  Send Latency Tolerance Message Device Notification TP (used only
- *  in SS mode).
- */
-#define USB_CMD_SDNLTM		BIT(12)
-/* Send Custom Transaction Packet (used only in SS mode) */
-#define USB_CMD_SPKT		BIT(13)
-/*Device Notification 'Function Wake' - Interface value (only in SS mode. */
-#define USB_CMD_DNFW_INT_MASK	GENMASK(23, 16)
-#define USB_STS_DNFW_INT(p)	(((p) << 16) & USB_CMD_DNFW_INT_MASK)
-/*
- * Device Notification 'Latency Tolerance Message' -373 BELT value [7:0]
- * (used only in SS mode).
- */
-#define USB_CMD_DNLTM_BELT_MASK	GENMASK(27, 16)
-#define USB_STS_DNLTM_BELT(p)	(((p) << 16) & USB_CMD_DNLTM_BELT_MASK)
-
-/* USB_ITPN - bitmasks */
-/*
- * ITP(SS) / SOF (HS/FS) number
- * In SS mode this field represent number of last ITP received from host.
- * In HS/FS mode this field represent number of last SOF received from host.
- */
-#define USB_ITPN_MASK		GENMASK(13, 0)
-#define USB_ITPN(p)		((p) & USB_ITPN_MASK)
-
-/* USB_LPM - bitmasks */
-/* Host Initiated Resume Duration. */
-#define USB_LPM_HIRD_MASK	GENMASK(3, 0)
-#define USB_LPM_HIRD(p)		((p) & USB_LPM_HIRD_MASK)
-/* Remote Wakeup Enable (bRemoteWake). */
-#define USB_LPM_BRW		BIT(4)
-
-/* USB_IEN - bitmasks */
-/* SS connection interrupt enable */
-#define USB_IEN_CONIEN		BIT(0)
-/* SS disconnection interrupt enable. */
-#define USB_IEN_DISIEN		BIT(1)
-/* USB SS warm reset interrupt enable. */
-#define USB_IEN_UWRESIEN	BIT(2)
-/* USB SS hot reset interrupt enable */
-#define USB_IEN_UHRESIEN	BIT(3)
-/* SS link U3 state enter interrupt enable (suspend).*/
-#define USB_IEN_U3ENTIEN	BIT(4)
-/* SS link U3 state exit interrupt enable (wakeup). */
-#define USB_IEN_U3EXTIEN	BIT(5)
-/* SS link U2 state enter interrupt enable.*/
-#define USB_IEN_U2ENTIEN	BIT(6)
-/* SS link U2 state exit interrupt enable.*/
-#define USB_IEN_U2EXTIEN	BIT(7)
-/* SS link U1 state enter interrupt enable.*/
-#define USB_IEN_U1ENTIEN	BIT(8)
-/* SS link U1 state exit interrupt enable.*/
-#define USB_IEN_U1EXTIEN	BIT(9)
-/* ITP/SOF packet detected interrupt enable.*/
-#define USB_IEN_ITPIEN		BIT(10)
-/* Wakeup interrupt enable.*/
-#define USB_IEN_WAKEIEN		BIT(11)
-/* Send Custom Packet interrupt enable.*/
-#define USB_IEN_SPKTIEN		BIT(12)
-/* HS/FS mode connection interrupt enable.*/
-#define USB_IEN_CON2IEN		BIT(16)
-/* HS/FS mode disconnection interrupt enable.*/
-#define USB_IEN_DIS2IEN		BIT(17)
-/* USB reset (HS/FS mode) interrupt enable.*/
-#define USB_IEN_U2RESIEN	BIT(18)
-/* LPM L2 state enter interrupt enable.*/
-#define USB_IEN_L2ENTIEN	BIT(20)
-/* LPM  L2 state exit interrupt enable.*/
-#define USB_IEN_L2EXTIEN	BIT(21)
-/* LPM L1 state enter interrupt enable.*/
-#define USB_IEN_L1ENTIEN	BIT(24)
-/* LPM  L1 state exit interrupt enable.*/
-#define USB_IEN_L1EXTIEN	BIT(25)
-/* Configuration reset interrupt enable.*/
-#define USB_IEN_CFGRESIEN	BIT(26)
-/* Start of the USB SS warm reset interrupt enable.*/
-#define USB_IEN_UWRESSIEN	BIT(28)
-/* End of the USB SS warm reset interrupt enable.*/
-#define USB_IEN_UWRESEIEN	BIT(29)
-
-#define USB_IEN_INIT  (USB_IEN_U2RESIEN | USB_ISTS_DIS2I | USB_IEN_CON2IEN \
-		       | USB_IEN_UHRESIEN | USB_IEN_UWRESIEN | USB_IEN_DISIEN \
-		       | USB_IEN_CONIEN | USB_IEN_U3EXTIEN | USB_IEN_L2ENTIEN \
-		       | USB_IEN_L2EXTIEN | USB_IEN_L1ENTIEN | USB_IEN_U3ENTIEN)
-
-/* USB_ISTS - bitmasks */
-/* SS Connection detected. */
-#define USB_ISTS_CONI		BIT(0)
-/* SS Disconnection detected. */
-#define USB_ISTS_DISI		BIT(1)
-/* UUSB warm reset detectede. */
-#define USB_ISTS_UWRESI		BIT(2)
-/* USB hot reset detected. */
-#define USB_ISTS_UHRESI		BIT(3)
-/* U3 link state enter detected (suspend).*/
-#define USB_ISTS_U3ENTI		BIT(4)
-/* U3 link state exit detected (wakeup). */
-#define USB_ISTS_U3EXTI		BIT(5)
-/* U2 link state enter detected.*/
-#define USB_ISTS_U2ENTI		BIT(6)
-/* U2 link state exit detected.*/
-#define USB_ISTS_U2EXTI		BIT(7)
-/* U1 link state enter detected.*/
-#define USB_ISTS_U1ENTI		BIT(8)
-/* U1 link state exit detected.*/
-#define USB_ISTS_U1EXTI		BIT(9)
-/* ITP/SOF packet detected.*/
-#define USB_ISTS_ITPI		BIT(10)
-/* Wakeup detected.*/
-#define USB_ISTS_WAKEI		BIT(11)
-/* Send Custom Packet detected.*/
-#define USB_ISTS_SPKTI		BIT(12)
-/* HS/FS mode connection detected.*/
-#define USB_ISTS_CON2I		BIT(16)
-/* HS/FS mode disconnection detected.*/
-#define USB_ISTS_DIS2I		BIT(17)
-/* USB reset (HS/FS mode) detected.*/
-#define USB_ISTS_U2RESI		BIT(18)
-/* LPM L2 state enter detected.*/
-#define USB_ISTS_L2ENTI		BIT(20)
-/* LPM  L2 state exit detected.*/
-#define USB_ISTS_L2EXTI		BIT(21)
-/* LPM L1 state enter detected.*/
-#define USB_ISTS_L1ENTI		BIT(24)
-/* LPM L1 state exit detected.*/
-#define USB_ISTS_L1EXTI		BIT(25)
-/* USB configuration reset detected.*/
-#define USB_ISTS_CFGRESI	BIT(26)
-/* Start of the USB warm reset detected.*/
-#define USB_ISTS_UWRESSI	BIT(28)
-/* End of the USB warm reset detected.*/
-#define USB_ISTS_UWRESEI	BIT(29)
+#if IS_ENABLED(CONFIG_USB_CDNS_MISC)
+#include "cdns_misc.h"
+#endif
 
-/* USB_SEL - bitmasks */
-#define EP_SEL_EPNO_MASK	GENMASK(3, 0)
-/* Endpoint number. */
-#define EP_SEL_EPNO(p)		((p) & EP_SEL_EPNO_MASK)
-/* Endpoint direction bit - 0 - OUT, 1 - IN. */
-#define EP_SEL_DIR		BIT(7)
+#include <clk.h>
+#include <generic-phy.h>
 
-#define select_ep_in(nr)	(EP_SEL_EPNO(p) | EP_SEL_DIR)
-#define select_ep_out		(EP_SEL_EPNO(p))
+#define gadget_to_usb_ss(g)  \
+	(container_of(g, struct usb_ss_dev, gadget))
 
-/* EP_TRADDR - bitmasks */
-/* Transfer Ring address. */
-#define EP_TRADDR_TRADDR(p)	((p))
+#define to_usb_ss_ep(ep) \
+	(container_of(ep, struct usb_ss_endpoint, endpoint))
 
-/* EP_CFG - bitmasks */
-/* Endpoint enable */
-#define EP_CFG_ENABLE		BIT(0)
-/*
- *  Endpoint type.
- * 1 - isochronous
- * 2 - bulk
- * 3 - interrupt
- */
-#define EP_CFG_EPTYPE_MASK	GENMASK(2, 1)
-#define EP_CFG_EPTYPE(p)	(((p) << 1)  & EP_CFG_EPTYPE_MASK)
-/* Stream support enable (only in SS mode). */
-#define EP_CFG_STREAM_EN	BIT(3)
-/* TDL check (only in SS mode for BULK EP). */
-#define EP_CFG_TDL_CHK		BIT(4)
-/* SID check (only in SS mode for BULK OUT EP). */
-#define EP_CFG_SID_CHK		BIT(5)
-/* DMA transfer endianness. */
-#define EP_CFG_EPENDIAN		BIT(7)
-/* Max burst size (used only in SS mode). */
-#define EP_CFG_MAXBURST_MASK	GENMASK(11, 8)
-#define EP_CFG_MAXBURST(p)	(((p) << 8) & EP_CFG_MAXBURST_MASK)
-/* ISO max burst. */
-#define EP_CFG_MULT_MASK	GENMASK(15, 14)
-#define EP_CFG_MULT(p)		(((p) << 14) & EP_CFG_MULT_MASK)
-/* ISO max burst. */
-#define EP_CFG_MAXPKTSIZE_MASK	GENMASK(26, 16)
-#define EP_CFG_MAXPKTSIZE(p)	(((p) << 16) & EP_CFG_MAXPKTSIZE_MASK)
-/* Max number of buffered packets. */
-#define EP_CFG_BUFFERING_MASK	GENMASK(31, 27)
-#define EP_CFG_BUFFERING(p)	(((p) << 27) & EP_CFG_BUFFERING_MASK)
+#define ep_to_usb_ss_ep(ep) \
+	(container_of(ep, struct usb_ss_endpoint, endpoint))
 
-/* EP_CMD - bitmasks */
-/* Endpoint reset. */
-#define EP_CMD_EPRST		BIT(0)
-/* Endpoint STALL set. */
-#define EP_CMD_SSTALL		BIT(1)
-/* Endpoint STALL clear. */
-#define EP_CMD_CSTALL		BIT(2)
-/* Send ERDY TP. */
-#define EP_CMD_ERDY		BIT(3)
-/* Request complete. */
-#define EP_CMD_REQ_CMPL		BIT(5)
-/* Transfer descriptor ready. */
-#define EP_CMD_DRDY		BIT(6)
-/* Data flush. */
-#define EP_CMD_DFLUSH		BIT(7)
-/*
- * Transfer Descriptor Length write  (used only for Bulk Stream capable
- * endpoints in SS mode).
- * Bit Removed from DEV_VER_V3 controller version.
- */
-#define EP_CMD_STDL		BIT(8)
-/*
- * Transfer Descriptor Length (used only in SS mode for bulk endpoints).
- * Bits Removed from DEV_VER_V3 controller version.
- */
-#define EP_CMD_TDL_MASK		GENMASK(15, 9)
-#define EP_CMD_TDL_SET(p)	(((p) << 9) & EP_CMD_TDL_MASK)
-#define EP_CMD_TDL_GET(p)	(((p) & EP_CMD_TDL_MASK) >> 9)
-
-/* ERDY Stream ID value (used in SS mode). */
-#define EP_CMD_ERDY_SID_MASK	GENMASK(31, 16)
-#define EP_CMD_ERDY_SID(p)	(((p) << 16) & EP_CMD_ERDY_SID_MASK)
+/*-------------------------------------------------------------------------*/
+/* TRB macros */
 
-/* EP_STS - bitmasks */
-/* Setup transfer complete. */
-#define EP_STS_SETUP		BIT(0)
-/* Endpoint STALL status. */
-#define EP_STS_STALL(p)		((p) & BIT(1))
-/* Interrupt On Complete. */
-#define EP_STS_IOC		BIT(2)
-/* Interrupt on Short Packet. */
-#define EP_STS_ISP		BIT(3)
-/* Transfer descriptor missing. */
-#define EP_STS_DESCMIS		BIT(4)
-/* Stream Rejected (used only in SS mode) */
-#define EP_STS_STREAMR		BIT(5)
-/* EXIT from MOVE DATA State (used only for stream transfers in SS mode). */
-#define EP_STS_MD_EXIT		BIT(6)
-/* TRB error. */
-#define EP_STS_TRBERR		BIT(7)
-/* Not ready (used only in SS mode). */
-#define EP_STS_NRDY		BIT(8)
-/* DMA busy bit. */
-#define EP_STS_DBUSY		BIT(9)
-/* Endpoint Buffer Empty */
-#define EP_STS_BUFFEMPTY(p)	((p) & BIT(10))
-/* Current Cycle Status */
-#define EP_STS_CCS(p)		((p) & BIT(11))
-/* Prime (used only in SS mode. */
-#define EP_STS_PRIME		BIT(12)
-/* Stream error (used only in SS mode). */
-#define EP_STS_SIDERR		BIT(13)
-/* OUT size mismatch. */
-#define EP_STS_OUTSMM		BIT(14)
-/* ISO transmission error. */
-#define EP_STS_ISOERR		BIT(15)
-/* Host Packet Pending (only for SS mode). */
-#define EP_STS_HOSTPP(p)	((p) & BIT(16))
-/* Stream Protocol State Machine State (only for Bulk stream endpoints). */
-#define EP_STS_SPSMST_MASK		GENMASK(18, 17)
-#define EP_STS_SPSMST_DISABLED(p)	(((p) & EP_STS_SPSMST_MASK) >> 17)
-#define EP_STS_SPSMST_IDLE(p)		(((p) & EP_STS_SPSMST_MASK) >> 17)
-#define EP_STS_SPSMST_START_STREAM(p)	(((p) & EP_STS_SPSMST_MASK) >> 17)
-#define EP_STS_SPSMST_MOVE_DATA(p)	(((p) & EP_STS_SPSMST_MASK) >> 17)
-/* Interrupt On Transfer complete. */
-#define EP_STS_IOT		BIT(19)
-/* OUT queue endpoint number. */
-#define EP_STS_OUTQ_NO_MASK	GENMASK(27, 24)
-#define EP_STS_OUTQ_NO(p)	(((p) & EP_STS_OUTQ_NO_MASK) >> 24)
-/* OUT queue valid flag. */
-#define EP_STS_OUTQ_VAL_MASK	BIT(28)
-#define EP_STS_OUTQ_VAL(p)	((p) & EP_STS_OUTQ_VAL_MASK)
-/* SETUP WAIT. */
-#define EP_STS_STPWAIT		BIT(31)
+/* Common TRB fields */
+#define TRB_SET_CYCLE_BIT		1uL
+#define TRB_SET_CHAIN_BIT		0x10
 
-/* EP_STS_SID - bitmasks */
-/* Stream ID (used only in SS mode). */
-#define EP_STS_SID_MASK		GENMASK(15, 0)
-#define EP_STS_SID(p)		((p) & EP_STS_SID_MASK)
+/* offset 0 */
+#define TRB_DATA_BUFFER_POINTER_MASK	0xFFFFFFFF
+#define TRB_SET_DATA_BUFFER_POINTER(p)	((p) & TRB_DATA_BUFFER_POINTER_MASK)
 
-/* EP_STS_EN - bitmasks */
-/* SETUP interrupt enable. */
-#define EP_STS_EN_SETUPEN	BIT(0)
-/* OUT transfer missing descriptor enable. */
-#define EP_STS_EN_DESCMISEN	BIT(4)
-/* Stream Rejected enable. */
-#define EP_STS_EN_STREAMREN	BIT(5)
-/* Move Data Exit enable.*/
-#define EP_STS_EN_MD_EXITEN	BIT(6)
-/* TRB enable. */
-#define EP_STS_EN_TRBERREN	BIT(7)
-/* NRDY enable. */
-#define EP_STS_EN_NRDYEN	BIT(8)
-/* Prime enable. */
-#define EP_STS_EN_PRIMEEEN	BIT(12)
-/* Stream error enable. */
-#define EP_STS_EN_SIDERREN	BIT(13)
-/* OUT size mismatch enable. */
-#define EP_STS_EN_OUTSMMEN	BIT(14)
-/* ISO transmission error enable. */
-#define EP_STS_EN_ISOERREN	BIT(15)
-/* Interrupt on Transmission complete enable. */
-#define EP_STS_EN_IOTEN		BIT(19)
-/* Setup Wait interrupt enable. */
-#define EP_STS_EN_STPWAITEN	BIT(31)
+/* offset 4 */
+#define TRB_TRANSFER_LENGTH_MASK	0x1FFFF
+#define TRB_SET_TRANSFER_LENGTH(l)	((l) & TRB_TRANSFER_LENGTH_MASK)
 
-/* DRBL- bitmasks */
-#define DB_VALUE_BY_INDEX(index) (1 << (index))
-#define DB_VALUE_EP0_OUT	BIT(0)
-#define DB_VALUE_EP0_IN		BIT(16)
+#define TRB_BURST_LENGTH_MASK		0xFF
+#define TRB_SET_BURST_LENGTH(l)		(((l) & TRB_BURST_LENGTH_MASK) << 24)
 
-/* EP_IEN - bitmasks */
-#define EP_IEN(index)		(1 << (index))
-#define EP_IEN_EP_OUT0		BIT(0)
-#define EP_IEN_EP_IN0		BIT(16)
+/* offset 8 */
+#define TRB_SET_INT_ON_SHORT_PACKET	0x04
+#define TRB_SET_FIFO_MODE		0x08
+#define TRB_SET_INT_ON_COMPLETION	0x20
 
-/* EP_ISTS - bitmasks */
-#define EP_ISTS(index)		(1 << (index))
-#define EP_ISTS_EP_OUT0		BIT(0)
-#define EP_ISTS_EP_IN0		BIT(16)
+#define TRB_TYPE_NORMAL			0x400
 
-/* USB_PWR- bitmasks */
-/*Power Shut Off capability enable*/
-#define PUSB_PWR_PSO_EN		BIT(0)
-/*Power Shut Off capability disable*/
-#define PUSB_PWR_PSO_DS		BIT(1)
-/*
- * Enables turning-off Reference Clock.
- * This bit is optional and implemented only when support for OTG is
- * implemented (indicated by OTG_READY bit set to '1').
- */
-#define PUSB_PWR_STB_CLK_SWITCH_EN	BIT(8)
-/*
- * Status bit indicating that operation required by STB_CLK_SWITCH_EN write
- * is completed
- */
-#define PUSB_PWR_STB_CLK_SWITCH_DONE	BIT(9)
-/* This bit informs if Fast Registers Access is enabled. */
-#define PUSB_PWR_FST_REG_ACCESS_STAT	BIT(30)
-/* Fast Registers Access Enable. */
-#define PUSB_PWR_FST_REG_ACCESS		BIT(31)
+#define TRB_STREAM_ID_MASK		0xFFFF
+#define TRB_SET_STREAM_ID(sid)		(((sid) & TRB_STREAM_ID_MASK) << 16)
 
-/* USB_CONF2- bitmasks */
-/*
- * Writing 1 disables TDL calculation basing on TRB feature in controller
- * for DMULT mode.
- * Bit supported only for DEV_VER_V2 version.
- */
-#define USB_CONF2_DIS_TDL_TRB		BIT(1)
-/*
- * Writing 1 enables TDL calculation basing on TRB feature in controller
- * for DMULT mode.
- * Bit supported only for DEV_VER_V2 version.
- */
-#define USB_CONF2_EN_TDL_TRB		BIT(2)
+/*-------------------------------------------------------------------------*/
+/* Driver numeric constants */
 
-/* USB_CAP1- bitmasks */
-/*
- * SFR Interface type
- * These field reflects type of SFR interface implemented:
- * 0x0 - OCP
- * 0x1 - AHB,
- * 0x2 - PLB
- * 0x3 - AXI
- * 0x4-0xF - reserved
- */
-#define USB_CAP1_SFR_TYPE_MASK	GENMASK(3, 0)
-#define DEV_SFR_TYPE_OCP(p)	(((p) & USB_CAP1_SFR_TYPE_MASK) == 0x0)
-#define DEV_SFR_TYPE_AHB(p)	(((p) & USB_CAP1_SFR_TYPE_MASK) == 0x1)
-#define DEV_SFR_TYPE_PLB(p)	(((p) & USB_CAP1_SFR_TYPE_MASK) == 0x2)
-#define DEV_SFR_TYPE_AXI(p)	(((p) & USB_CAP1_SFR_TYPE_MASK) == 0x3)
-/*
- * SFR Interface width
- * These field reflects width of SFR interface implemented:
- * 0x0 - 8 bit interface,
- * 0x1 - 16 bit interface,
- * 0x2 - 32 bit interface
- * 0x3 - 64 bit interface
- * 0x4-0xF - reserved
- */
-#define USB_CAP1_SFR_WIDTH_MASK	GENMASK(7, 4)
-#define DEV_SFR_WIDTH_8(p)	(((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x0 << 4))
-#define DEV_SFR_WIDTH_16(p)	(((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x1 << 4))
-#define DEV_SFR_WIDTH_32(p)	(((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x2 << 4))
-#define DEV_SFR_WIDTH_64(p)	(((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x3 << 4))
-/*
- * DMA Interface type
- * These field reflects type of DMA interface implemented:
- * 0x0 - OCP
- * 0x1 - AHB,
- * 0x2 - PLB
- * 0x3 - AXI
- * 0x4-0xF - reserved
- */
-#define USB_CAP1_DMA_TYPE_MASK	GENMASK(11, 8)
-#define DEV_DMA_TYPE_OCP(p)	(((p) & USB_CAP1_DMA_TYPE_MASK) == (0x0 << 8))
-#define DEV_DMA_TYPE_AHB(p)	(((p) & USB_CAP1_DMA_TYPE_MASK) == (0x1 << 8))
-#define DEV_DMA_TYPE_PLB(p)	(((p) & USB_CAP1_DMA_TYPE_MASK) == (0x2 << 8))
-#define DEV_DMA_TYPE_AXI(p)	(((p) & USB_CAP1_DMA_TYPE_MASK) == (0x3 << 8))
-/*
- * DMA Interface width
- * These field reflects width of DMA interface implemented:
- * 0x0 - reserved,
- * 0x1 - reserved,
- * 0x2 - 32 bit interface
- * 0x3 - 64 bit interface
- * 0x4-0xF - reserved
- */
-#define USB_CAP1_DMA_WIDTH_MASK	GENMASK(15, 12)
-#define DEV_DMA_WIDTH_32(p)	(((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x2 << 12))
-#define DEV_DMA_WIDTH_64(p)	(((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x3 << 12))
-/*
- * USB3 PHY Interface type
- * These field reflects type of USB3 PHY interface implemented:
- * 0x0 - USB PIPE,
- * 0x1 - RMMI,
- * 0x2-0xF - reserved
- */
-#define USB_CAP1_U3PHY_TYPE_MASK GENMASK(19, 16)
-#define DEV_U3PHY_PIPE(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x0 << 16))
-#define DEV_U3PHY_RMMI(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x1 << 16))
-/*
- * USB3 PHY Interface width
- * These field reflects width of USB3 PHY interface implemented:
- * 0x0 - 8 bit PIPE interface,
- * 0x1 - 16 bit PIPE interface,
- * 0x2 - 32 bit PIPE interface,
- * 0x3 - 64 bit PIPE interface
- * 0x4-0xF - reserved
- * Note: When SSIC interface is implemented this field shows the width of
- * internal PIPE interface. The RMMI interface is always 20bit wide.
- */
-#define USB_CAP1_U3PHY_WIDTH_MASK GENMASK(23, 20)
-#define DEV_U3PHY_WIDTH_8(p) \
-	(((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x0 << 20))
-#define DEV_U3PHY_WIDTH_16(p) \
-	(((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x1 << 16))
-#define DEV_U3PHY_WIDTH_32(p) \
-	(((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x2 << 20))
-#define DEV_U3PHY_WIDTH_64(p) \
-	(((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x3 << 16))
+#define DEVICE_ADDRESS_MAX		127
 
-/*
- * USB2 PHY Interface enable
- * These field informs if USB2 PHY interface is implemented:
- * 0x0 - interface NOT implemented,
- * 0x1 - interface implemented
- */
-#define USB_CAP1_U2PHY_EN(p)	((p) & BIT(24))
-/*
- * USB2 PHY Interface type
- * These field reflects type of USB2 PHY interface implemented:
- * 0x0 - UTMI,
- * 0x1 - ULPI
- */
-#define DEV_U2PHY_ULPI(p)	((p) & BIT(25))
-/*
- * USB2 PHY Interface width
- * These field reflects width of USB2 PHY interface implemented:
- * 0x0 - 8 bit interface,
- * 0x1 - 16 bit interface,
- * Note: The ULPI interface is always 8bit wide.
- */
-#define DEV_U2PHY_WIDTH_16(p)	((p) & BIT(26))
-/*
- * OTG Ready
- * 0x0 - pure device mode
- * 0x1 - some features and ports for CDNS USB OTG controller are implemented.
- */
-#define USB_CAP1_OTG_READY(p)	((p) & BIT(27))
+/* Endpoint init values */
+#define ENDPOINT_MAX_PACKET_LIMIT	1024
 
-/*
- * When set, indicates that controller supports automatic internal TDL
- * calculation basing on the size provided in TRB (TRB[22:17]) for DMULT mode
- * Supported only for DEV_VER_V2 controller version.
- */
-#define USB_CAP1_TDL_FROM_TRB(p)	((p) & BIT(28))
+#define ENDPOINT_MAX_STREAMS		15
 
-/* USB_CAP2- bitmasks */
-/*
- * The actual size of the connected On-chip RAM memory in kB:
- * - 0 means 256 kB (max supported mem size)
- * - value other than 0 reflects the mem size in kB
- */
-#define USB_CAP2_ACTUAL_MEM_SIZE(p) ((p) & GENMASK(7, 0))
-/*
- * Max supported mem size
- * These field reflects width of on-chip RAM address bus width,
- * which determines max supported mem size:
- * 0x0-0x7 - reserved,
- * 0x8 - support for 4kB mem,
- * 0x9 - support for 8kB mem,
- * 0xA - support for 16kB mem,
- * 0xB - support for 32kB mem,
- * 0xC - support for 64kB mem,
- * 0xD - support for 128kB mem,
- * 0xE - support for 256kB mem,
- * 0xF - reserved
- */
-#define USB_CAP2_MAX_MEM_SIZE(p) ((p) & GENMASK(11, 8))
+#define ENDPOINT0_MAX_PACKET_LIMIT	512
 
-/* USB_CAP3- bitmasks */
-#define EP_IS_IMPLEMENTED(reg, index) ((reg) & (1 << (index)))
+/* All endpoints except EP0 */
+#define USB_SS_ENDPOINTS_MAX_COUNT	30
 
-/* USB_CAP4- bitmasks */
-#define EP_SUPPORT_ISO(reg, index) ((reg) & (1 << (index)))
+#define USB_SS_TRBS_NUM			32
 
-/* USB_CAP5- bitmasks */
-#define EP_SUPPORT_STREAM(reg, index) ((reg) & (1 << (index)))
+/* Standby mode */
+#define STB_CLK_SWITCH_DONE_MASK	0x200
+#define STB_CLK_SWITCH_EN_MASK		0x100
+#define STB_CLK_SWITCH_EN_SHIFT		8
 
-/* USB_CAP6- bitmasks */
-/* The USBSS-DEV Controller  Internal build number. */
-#define GET_DEV_BASE_VERSION(p) ((p) & GENMASK(23, 0))
-/* The USBSS-DEV Controller version number. */
-#define GET_DEV_CUSTOM_VERSION(p) ((p) & GENMASK(31, 24))
+#define ENDPOINT_MAX_PACKET_SIZE_0	0
+#define ENDPOINT_MAX_PACKET_SIZE_8	8
+#define ENDPOINT_MAX_PACKET_SIZE_64	64
+#define ENDPOINT_MAX_PACKET_SIZE_512	512
+#define ENDPOINT_MAX_PACKET_SIZE_1023	1023
+#define ENDPOINT_MAX_PACKET_SIZE_1024	1024
 
-#define DEV_VER_NXP_V1		0x00024502
-#define DEV_VER_TI_V1		0x00024509
-#define DEV_VER_V2		0x0002450C
-#define DEV_VER_V3		0x0002450d
+#define SS_LINK_STATE_U3		3
+#define FSHS_LPM_STATE_L2		2
 
-/* DBG_LINK1- bitmasks */
-/*
- * LFPS_MIN_DET_U1_EXIT value This parameter configures the minimum
- * time required for decoding the received LFPS as an LFPS.U1_Exit.
- */
-#define DBG_LINK1_LFPS_MIN_DET_U1_EXIT(p)	((p) & GENMASK(7, 0))
-/*
- * LFPS_MIN_GEN_U1_EXIT value This parameter configures the minimum time for
- * phytxelecidle deassertion when LFPS.U1_Exit
- */
-#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK	GENMASK(15, 8)
-#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(p)	(((p) << 8) & GENMASK(15, 8))
-/*
- * RXDET_BREAK_DIS value This parameter configures terminating the Far-end
- * Receiver termination detection sequence:
- * 0: it is possible that USBSS_DEV will terminate Farend receiver
- *    termination detection sequence
- * 1: USBSS_DEV will not terminate Far-end receiver termination
- *    detection sequence
- */
-#define DBG_LINK1_RXDET_BREAK_DIS		BIT(16)
-/* LFPS_GEN_PING value This parameter configures the LFPS.Ping generation */
-#define DBG_LINK1_LFPS_GEN_PING(p)		(((p) << 17) & GENMASK(21, 17))
-/*
- * Set the LFPS_MIN_DET_U1_EXIT value Writing '1' to this bit writes the
- * LFPS_MIN_DET_U1_EXIT field value to the device. This bit is automatically
- * cleared. Writing '0' has no effect
- */
-#define DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET	BIT(24)
-/*
- * Set the LFPS_MIN_GEN_U1_EXIT value. Writing '1' to this bit writes the
- * LFPS_MIN_GEN_U1_EXIT field value to the device. This bit is automatically
- * cleared. Writing '0' has no effect
- */
-#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET	BIT(25)
-/*
- * Set the RXDET_BREAK_DIS value Writing '1' to this bit writes
- * the RXDET_BREAK_DIS field value to the device. This bit is automatically
- * cleared. Writing '0' has no effect
- */
-#define DBG_LINK1_RXDET_BREAK_DIS_SET		BIT(26)
-/*
- * Set the LFPS_GEN_PING_SET value Writing '1' to this bit writes
- * the LFPS_GEN_PING field value to the device. This bit is automatically
- * cleared. Writing '0' has no effect."
- */
-#define DBG_LINK1_LFPS_GEN_PING_SET		BIT(27)
+#define ADDR_MODULO_8			8
 
-/* DMA_AXI_CTRL- bitmasks */
-/* The mawprot pin configuration. */
-#define DMA_AXI_CTRL_MARPROT(p) ((p) & GENMASK(2, 0))
-/* The marprot pin configuration. */
-#define DMA_AXI_CTRL_MAWPROT(p) (((p) & GENMASK(2, 0)) << 16)
-#define DMA_AXI_CTRL_NON_SECURE 0x02
+#define INTERRUPT_MASK			0xFFFFFFFF
 
-#define gadget_to_cdns3_device(g) (container_of(g, struct cdns3_device, gadget))
+#define ACTUAL_TRANSFERRED_BYTES_MASK	0x1FFFF
 
-#define ep_to_cdns3_ep(ep) (container_of(ep, struct cdns3_endpoint, endpoint))
+#define ENDPOINT_DIR_MASK		0x80
 
 /*-------------------------------------------------------------------------*/
-/*
- * USBSS-DEV DMA interface.
- */
-#define TRBS_PER_SEGMENT	40
 
-#define ISO_MAX_INTERVAL	10
-
-#if TRBS_PER_SEGMENT < 2
-#error "Incorrect TRBS_PER_SEGMENT. Minimal Transfer Ring size is 2."
-#endif
-
-/*
- *Only for ISOC endpoints - maximum number of TRBs is calculated as
- * pow(2, bInterval-1) * number of usb requests. It is limitation made by
- * driver to save memory. Controller must prepare TRB for each ITP even
- * if bInterval > 1. It's the reason why driver needs so many TRBs for
- * isochronous endpoints.
+/**
+ * IS_REG_REQUIRING_ACTIVE_REF_CLOCK - Macro checks if desired
+ * register requires active clock, it involves such registers as:
+ * EP_CFG, EP_TR_ADDR, EP_CMD, EP_SEL, USB_CONF
+ * @usb_ss: extended gadget object
+ * @reg: register address
  */
-#define TRBS_PER_ISOC_SEGMENT	(ISO_MAX_INTERVAL * 8)
+#define IS_REG_REQUIRING_ACTIVE_REF_CLOCK(usb_ss, reg)	(!(reg) || \
+	((reg) >= &(usb_ss)->regs->ep_sel && (reg) <= &(usb_ss)->regs->ep_cmd))
 
-#define GET_TRBS_PER_SEGMENT(ep_type) ((ep_type) == USB_ENDPOINT_XFER_ISOC ? \
-				      TRBS_PER_ISOC_SEGMENT : TRBS_PER_SEGMENT)
 /**
- * struct cdns3_trb - represent Transfer Descriptor block.
- * @buffer:	pointer to buffer data
- * @length:	length of data
- * @control:	control flags.
+ * CAST_EP_REG_POS_TO_INDEX - Macro converts bit position of ep_ists register to
+ * index of endpoint object in usb_ss_dev.eps[] container
+ * @i: bit position of endpoint for which endpoint object is required
  *
- * This structure describes transfer block serviced by DMA module.
+ * Remember that endpoint container doesn't contain default endpoint
  */
-struct cdns3_trb {
-	__le32 buffer;
-	__le32 length;
-	__le32 control;
-};
+#define CAST_EP_REG_POS_TO_INDEX(i) (((i) / 16) + ((((i) % 16) - 2) * 2))
 
-#define TRB_SIZE		(sizeof(struct cdns3_trb))
-#define TRB_RING_SIZE		(TRB_SIZE * TRBS_PER_SEGMENT)
-#define TRB_ISO_RING_SIZE	(TRB_SIZE * TRBS_PER_ISOC_SEGMENT)
-#define TRB_CTRL_RING_SIZE	(TRB_SIZE * 2)
-
-/* TRB bit mask */
-#define TRB_TYPE_BITMASK	GENMASK(15, 10)
-#define TRB_TYPE(p)		((p) << 10)
-#define TRB_FIELD_TO_TYPE(p)	(((p) & TRB_TYPE_BITMASK) >> 10)
-
-/* TRB type IDs */
-/* bulk, interrupt, isoc , and control data stage */
-#define TRB_NORMAL		1
-/* TRB for linking ring segments */
-#define TRB_LINK		6
-
-/* Cycle bit - indicates TRB ownership by driver or hw*/
-#define TRB_CYCLE		BIT(0)
-/*
- * When set to '1', the device will toggle its interpretation of the Cycle bit
+/**
+ * CAST_EP_ADDR_TO_INDEX - Macro converts endpoint address to
+ * index of endpoint object in usb_ss_dev.eps[] container
+ * @ep_addr: endpoint address for which endpoint object is required
+ *
+ * Remember that endpoint container doesn't contain default endpoint
  */
-#define TRB_TOGGLE		BIT(1)
+#define CAST_EP_ADDR_TO_INDEX(ep_addr) \
+	((((ep_addr) & 0x7F) - 1) + (((ep_addr) & 0x80) ? 1 : 0))
 
-/*
- * Short Packet (SP). OUT EPs at DMULT=1 only. Indicates if the TRB was
- * processed while USB short packet was received. No more buffers defined by
- * the TD will be used. DMA will automatically advance to next TD.
- * - Shall be set to 0 by Software when putting TRB on the Transfer Ring
- * - Shall be set to 1 by Controller when Short Packet condition for this TRB
- *   is detected independent if ISP is set or not.
+/**
+ * CAST_EP_ADDR_TO_BIT_POS - Macro converts endpoint address to
+ * bit position in ep_ists register
+ * @ep_addr: endpoint address for which bit position is required
+ *
+ * Remember that endpoint container doesn't contain default endpoint
  */
-#define TRB_SP			BIT(1)
-
-/* Interrupt on short packet*/
-#define TRB_ISP			BIT(2)
-/*Setting this bit enables FIFO DMA operation mode*/
-#define TRB_FIFO_MODE		BIT(3)
-/* Set PCIe no snoop attribute */
-#define TRB_CHAIN		BIT(4)
-/* Interrupt on completion */
-#define TRB_IOC			BIT(5)
-
-/* stream ID bitmasks. */
-#define TRB_STREAM_ID_BITMASK		GENMASK(31, 16)
-#define TRB_STREAM_ID(p)		((p) << 16)
-#define TRB_FIELD_TO_STREAMID(p)	(((p) & TRB_STREAM_ID_BITMASK) >> 16)
-
-/* Size of TD expressed in USB packets for HS/FS mode. */
-#define TRB_TDL_HS_SIZE(p)	(((p) << 16) & GENMASK(31, 16))
-#define TRB_TDL_HS_SIZE_GET(p)	(((p) & GENMASK(31, 16)) >> 16)
-
-/* transfer_len bitmasks. */
-#define TRB_LEN(p)		((p) & GENMASK(16, 0))
-
-/* Size of TD expressed in USB packets for SS mode. */
-#define TRB_TDL_SS_SIZE(p)	(((p) << 17) & GENMASK(23, 17))
-#define TRB_TDL_SS_SIZE_GET(p)	(((p) & GENMASK(23, 17)) >> 17)
-
-/* transfer_len bitmasks - bits 31:24 */
-#define TRB_BURST_LEN(p)	(((p) << 24) & GENMASK(31, 24))
-#define TRB_BURST_LEN_GET(p)	(((p) & GENMASK(31, 24)) >> 24)
-
-/* Data buffer pointer bitmasks*/
-#define TRB_BUFFER(p)		((p) & GENMASK(31, 0))
-
-/*-------------------------------------------------------------------------*/
-/* Driver numeric constants */
-
-/* Such declaration should be added to ch9.h */
-#define USB_DEVICE_MAX_ADDRESS		127
-
-/* Endpoint init values */
-#define CDNS3_EP_MAX_PACKET_LIMIT	1024
-#define CDNS3_EP_MAX_STREAMS		15
-#define CDNS3_EP0_MAX_PACKET_LIMIT	512
+#define CAST_EP_ADDR_TO_BIT_POS(ep_addr) \
+	(((u32)1 << ((ep_addr) & 0x7F))  << (((ep_addr) & 0x80) ? 16 : 0))
 
-/* All endpoints including EP0 */
-#define CDNS3_ENDPOINTS_MAX_COUNT	32
-#define CDNS3_EP_ZLP_BUF_SIZE		1024
+#define CAST_INDEX_TO_EP_ADDR(index) \
+	(((index) / 2 + 1) | (((index) % 2) ? 0x80 : 0x00))
 
-#define CDNS3_EP_BUF_SIZE		2	/* KB */
-#define CDNS3_EP_ISO_HS_MULT		3
-#define CDNS3_EP_ISO_SS_BURST		3
-#define CDNS3_MAX_NUM_DESCMISS_BUF	32
-#define CDNS3_DESCMIS_BUF_SIZE		2048	/* Bytes */
-#define CDNS3_WA2_NUM_BUFFERS		128
 /*-------------------------------------------------------------------------*/
 /* Used structs */
 
-struct cdns3_device;
-
-/**
- * struct cdns3_endpoint - extended device side representation of USB endpoint.
- * @endpoint: usb endpoint
- * @pending_req_list: list of requests queuing on transfer ring.
- * @deferred_req_list: list of requests waiting for queuing on transfer ring.
- * @wa2_descmiss_req_list: list of requests internally allocated by driver.
- * @trb_pool: transfer ring - array of transaction buffers
- * @trb_pool_dma: dma address of transfer ring
- * @cdns3_dev: device associated with this endpoint
- * @name: a human readable name e.g. ep1out
- * @flags: specify the current state of endpoint
- * @descmis_req: internal transfer object used for getting data from on-chip
- *     buffer. It can happen only if function driver doesn't send usb_request
- *     object on time.
- * @dir: endpoint direction
- * @num: endpoint number (1 - 15)
- * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
- * @interval: interval between packets used for ISOC endpoint.
- * @free_trbs: number of free TRBs in transfer ring
- * @num_trbs: number of all TRBs in transfer ring
- * @pcs: producer cycle state
- * @ccs: consumer cycle state
- * @enqueue: enqueue index in transfer ring
- * @dequeue: dequeue index in transfer ring
- * @trb_burst_size: number of burst used in trb.
- */
-struct cdns3_endpoint {
-	struct usb_ep		endpoint;
-	struct list_head	pending_req_list;
-	struct list_head	deferred_req_list;
-	struct list_head	wa2_descmiss_req_list;
-	int			wa2_counter;
-
-	struct cdns3_trb	*trb_pool;
-	dma_addr_t		trb_pool_dma;
-
-	struct cdns3_device	*cdns3_dev;
-	char			name[20];
-
-#define EP_ENABLED		BIT(0)
-#define EP_STALLED		BIT(1)
-#define EP_STALL_PENDING	BIT(2)
-#define EP_WEDGE		BIT(3)
-#define EP_TRANSFER_STARTED	BIT(4)
-#define EP_UPDATE_EP_TRBADDR	BIT(5)
-#define EP_PENDING_REQUEST	BIT(6)
-#define EP_RING_FULL		BIT(7)
-#define EP_CLAIMED		BIT(8)
-#define EP_DEFERRED_DRDY	BIT(9)
-#define EP_QUIRK_ISO_OUT_EN	BIT(10)
-#define EP_QUIRK_END_TRANSFER	BIT(11)
-#define EP_QUIRK_EXTRA_BUF_DET	BIT(12)
-#define EP_QUIRK_EXTRA_BUF_EN	BIT(13)
-	u32			flags;
-
-	struct cdns3_request	*descmis_req;
-
-	u8			dir;
-	u8			num;
-	u8			type;
-	int			interval;
-
-	int			free_trbs;
-	int			num_trbs;
-	u8			pcs;
-	u8			ccs;
-	int			enqueue;
-	int			dequeue;
-	u8			trb_burst_size;
-
-	unsigned int		wa1_set:1;
-	struct cdns3_trb	*wa1_trb;
-	unsigned int		wa1_trb_index;
-	unsigned int		wa1_cycle_bit:1;
+struct usb_ss_trb {
+	u32 offset0;
+	u32 offset4;
+	u32 offset8;
 };
 
-/**
- * struct cdns3_aligned_buf - represent aligned buffer used for DMA transfer
- * @buf: aligned to 8 bytes data buffer. Buffer address used in
- *       TRB shall be aligned to 8.
- * @dma: dma address
- * @size: size of buffer
- * @in_use: inform if this buffer is associated with usb_request
- * @list: used to adding instance of this object to list
- */
-struct cdns3_aligned_buf {
-	void			*buf;
-	dma_addr_t		dma;
-	u32			size;
-	int			in_use:1;
-	struct list_head	list;
+struct usb_ss_dev;
+
+struct usb_ss_endpoint {
+	struct usb_ep endpoint;
+	struct list_head request_list;
+	struct list_head ep_match_pending_list;
+
+	struct usb_ss_trb *trb_pool;
+	dma_addr_t trb_pool_dma;
+
+	struct usb_ss_dev *usb_ss;
+	char name[20];
+	int hw_pending_flag;
+	int stalled_flag;
+	int wedge_flag;
+	int hw_reset_flag;
+	void *cpu_addr;
+	dma_addr_t dma_addr;
+	u8					dir;
+	u8					num;
+	u8					type;
+	u8					address;
+	bool				used;
+	bool				enabled;
+	struct usb_ep_caps	caps;
 };
 
-/**
- * struct cdns3_request - extended device side representation of usb_request
- *                        object .
- * @request: generic usb_request object describing single I/O request.
- * @priv_ep: extended representation of usb_ep object
- * @trb: the first TRB association with this request
- * @start_trb: number of the first TRB in transfer ring
- * @end_trb: number of the last TRB in transfer ring
- * @aligned_buf: object holds information about aligned buffer associated whit
- *               this endpoint
- * @flags: flag specifying special usage of request
- * @list: used by internally allocated request to add to wa2_descmiss_req_list.
- */
-struct cdns3_request {
-	struct usb_request		request;
-	struct cdns3_endpoint		*priv_ep;
-	struct cdns3_trb		*trb;
-	int				start_trb;
-	int				end_trb;
-	struct cdns3_aligned_buf	*aligned_buf;
-#define REQUEST_PENDING			BIT(0)
-#define REQUEST_INTERNAL		BIT(1)
-#define REQUEST_INTERNAL_CH		BIT(2)
-#define REQUEST_ZLP			BIT(3)
-#define REQUEST_UNALIGNED		BIT(4)
-	u32				flags;
-	struct list_head		list;
+struct usb_ss_dev {
+	struct udevice dev;
+	struct usbss_dev_register_block_type __iomem *regs;
+
+	struct usb_gadget gadget;
+	struct usb_gadget_driver *gadget_driver;
+
+	dma_addr_t setup_dma;
+	dma_addr_t trb_ep0_dma;
+	u32 *trb_ep0;
+	u8 *setup;
+
+	struct usb_ss_endpoint *eps[USB_SS_ENDPOINTS_MAX_COUNT];
+	int ep_nums;
+	struct usb_request *actual_ep0_request;
+	int ep0_data_dir;
+	int hw_configured_flag;
+	int wake_up_flag;
+	u16 isoch_delay;
+	spinlock_t lock;	/* protection lock */
+
+	unsigned is_connected:1;
+	unsigned in_standby_mode:1;
+
+	u32 usb_ien;
+	u32 ep_ien;
+	int setup_pending;
+	struct udevice *sysdev;
+	bool start_gadget; /* The device mode is enabled */
+	struct list_head ep_match_list;
 };
 
-#define to_cdns3_request(r) (container_of(r, struct cdns3_request, request))
-
-/*Stages used during enumeration process.*/
-#define CDNS3_SETUP_STAGE		0x0
-#define CDNS3_DATA_STAGE		0x1
-#define CDNS3_STATUS_STAGE		0x2
-
-/**
- * struct cdns3_device - represent USB device.
- * @dev: pointer to device structure associated whit this controller
- * @sysdev: pointer to the DMA capable device
- * @gadget: device side representation of the peripheral controller
- * @gadget_driver: pointer to the gadget driver
- * @dev_ver: device controller version.
- * @lock: for synchronizing
- * @regs: base address for device side registers
- * @setup_buf: used while processing usb control requests
- * @setup_dma: dma address for setup_buf
- * @zlp_buf - zlp buffer
- * @ep0_stage: ep0 stage during enumeration process.
- * @ep0_data_dir: direction for control transfer
- * @eps: array of pointers to all endpoints with exclusion ep0
- * @aligned_buf_list: list of aligned buffers internally allocated by driver
- * @aligned_buf_wq: workqueue freeing  no longer used aligned buf.
- * @selected_ep: actually selected endpoint. It's used only to improve
- *               performance.
- * @isoch_delay: value from Set Isoch Delay request. Only valid on SS/SSP.
- * @u1_allowed: allow device transition to u1 state
- * @u2_allowed: allow device transition to u2 state
- * @is_selfpowered: device is self powered
- * @setup_pending: setup packet is processing by gadget driver
- * @hw_configured_flag: hardware endpoint configuration was set.
- * @wake_up_flag: allow device to remote up the host
- * @status_completion_no_call: indicate that driver is waiting for status s
- *     stage completion. It's used in deferred SET_CONFIGURATION request.
- * @onchip_buffers: number of available on-chip buffers.
- * @onchip_used_size: actual size of on-chip memory assigned to endpoints.
- * @pending_status_wq: workqueue handling status stage for deferred requests.
- * @pending_status_request: request for which status stage was deferred
- */
-struct cdns3_device {
-	struct udevice			*dev;
-	struct udevice			*sysdev;
-
-	struct usb_gadget		gadget;
-	struct usb_gadget_driver	*gadget_driver;
-
-#define CDNS_REVISION_V0		0x00024501
-#define CDNS_REVISION_V1		0x00024509
-	u32				dev_ver;
-
-	/* generic spin-lock for drivers */
-	spinlock_t			lock;
-
-	struct cdns3_usb_regs		__iomem *regs;
-
-	struct usb_ctrlrequest		*setup_buf;
-	dma_addr_t			setup_dma;
-	void				*zlp_buf;
-
-	u8				ep0_stage;
-	int				ep0_data_dir;
-
-	struct cdns3_endpoint		*eps[CDNS3_ENDPOINTS_MAX_COUNT];
-
-	struct list_head		aligned_buf_list;
-	struct work_struct		aligned_buf_wq;
-
-	u32				selected_ep;
-	u16				isoch_delay;
-
-	unsigned			wait_for_setup:1;
-	unsigned			u1_allowed:1;
-	unsigned			u2_allowed:1;
-	unsigned			is_selfpowered:1;
-	unsigned			setup_pending:1;
-	int				hw_configured_flag:1;
-	int				wake_up_flag:1;
-	unsigned			status_completion_no_call:1;
-	int				out_mem_is_allocated;
-
-	struct work_struct		pending_status_wq;
-	struct usb_request		*pending_status_request;
-
-	/*in KB */
-	u32				onchip_buffers;
-	u16				onchip_used_size;
+struct cdns3_generic_peripheral {
+	struct cdns3 cdns3;
+	struct usb_ss_dev usb_ss_dev;
+	struct clk_bulk clks;
+	struct phy phy;
 };
 
-void cdns3_set_register_bit(void __iomem *ptr, u32 mask);
-dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep,
-				 struct cdns3_trb *trb);
-enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev);
-void cdns3_pending_setup_status_handler(struct work_struct *work);
-void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev);
-void cdns3_set_hw_configuration(struct cdns3_device *priv_dev);
-void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep);
-void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable);
-struct usb_request *cdns3_next_request(struct list_head *list);
-int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep,
-			  struct usb_request *request);
-void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm);
-int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep);
-u8 cdns3_ep_addr_to_index(u8 ep_addr);
-int cdns3_gadget_ep_set_wedge(struct usb_ep *ep);
-int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value);
-void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep);
-int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep);
-struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep,
-						  gfp_t gfp_flags);
-void cdns3_gadget_ep_free_request(struct usb_ep *ep,
-				  struct usb_request *request);
-int cdns3_gadget_ep_dequeue(struct usb_ep *ep, struct usb_request *request);
-void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep,
-			   struct cdns3_request *priv_req,
-			   int status);
-
-int cdns3_init_ep0(struct cdns3_device *priv_dev,
-		   struct cdns3_endpoint *priv_ep);
-void cdns3_ep0_config(struct cdns3_device *priv_dev);
-void cdns3_ep_config(struct cdns3_endpoint *priv_ep);
-void cdns3_check_ep0_interrupt_proceed(struct cdns3_device *priv_dev, int dir);
-int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev);
+#define OTG_STS_SELECTOR	0xF000		/* OTG status selector */
 
-#endif /* __LINUX_CDNS3_GADGET */
+#endif /* __DRIVERS_CDNS3_GADGET */
diff --git a/drivers/usb/cdns3/host-export.h b/drivers/usb/cdns3/host-export.h
deleted file mode 100644
index b498a170b7e..00000000000
--- a/drivers/usb/cdns3/host-export.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Cadence USBSS DRD Driver - Host Export APIs
- *
- * Copyright (C) 2017-2018 NXP
- *
- * Authors: Peter Chen <peter.chen@nxp.com>
- */
-#ifndef __LINUX_CDNS3_HOST_EXPORT
-#define __LINUX_CDNS3_HOST_EXPORT
-
-#ifdef CONFIG_USB_CDNS3_HOST
-
-int cdns3_host_init(struct cdns3 *cdns);
-void cdns3_host_exit(struct cdns3 *cdns);
-
-#else
-
-static inline int cdns3_host_init(struct cdns3 *cdns)
-{
-	return -ENXIO;
-}
-
-static inline void cdns3_host_exit(struct cdns3 *cdns) { }
-
-#endif /* CONFIG_USB_CDNS3_HOST */
-
-#endif /* __LINUX_CDNS3_HOST_EXPORT */
diff --git a/drivers/usb/cdns3/host.c b/drivers/usb/cdns3/host.c
deleted file mode 100644
index b44e7df1131..00000000000
--- a/drivers/usb/cdns3/host.c
+++ /dev/null
@@ -1,56 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Cadence USBSS DRD Driver - host side
- *
- * Copyright (C) 2018-2019 Cadence Design Systems.
- * Copyright (C) 2017-2018 NXP
- *
- * Authors: Peter Chen <peter.chen@nxp.com>
- *          Pawel Laszczak <pawell@cadence.com>
- */
-#include <dm.h>
-#include <dm/devres.h>
-#include <linux/compat.h>
-#include <usb.h>
-#include <usb/xhci.h>
-
-#include "core.h"
-#include "drd.h"
-
-static int __cdns3_host_init(struct cdns3 *cdns)
-{
-	struct xhci_hcor *hcor;
-	struct xhci_hccr *hccr;
-
-	cdns3_drd_switch_host(cdns, 1);
-
-	hccr = (struct xhci_hccr *)cdns->xhci_regs;
-	hcor = (struct xhci_hcor *)(cdns->xhci_regs +
-			HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
-
-	return xhci_register(cdns->dev, hccr, hcor);
-}
-
-static void cdns3_host_exit(struct cdns3 *cdns)
-{
-	xhci_deregister(cdns->dev);
-	cdns3_drd_switch_host(cdns, 0);
-}
-
-int cdns3_host_init(struct cdns3 *cdns)
-{
-	struct cdns3_role_driver *rdrv;
-
-	rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL);
-	if (!rdrv)
-		return -ENOMEM;
-
-	rdrv->start	= __cdns3_host_init;
-	rdrv->stop	= cdns3_host_exit;
-	rdrv->state	= CDNS3_ROLE_STATE_INACTIVE;
-	rdrv->name	= "host";
-
-	cdns->roles[USB_ROLE_HOST] = rdrv;
-
-	return 0;
-}
diff --git a/drivers/usb/cdns3/io.h b/drivers/usb/cdns3/io.h
new file mode 100644
index 00000000000..6bc7cfe9782
--- /dev/null
+++ b/drivers/usb/cdns3/io.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 Cadence Design Systems - https://www.cadence.com/
+ * Copyright 2019 NXP
+ */
+
+#ifndef __DRIVERS_USB_CDNS_IO_H
+#define __DRIVERS_USB_CDNS_IO_H
+
+#include <linux/io.h>
+
+static inline u32 cdns_readl(u32 __iomem *reg)
+{
+	return readl(reg);
+}
+
+static inline void cdns_writel(u32 __iomem *reg, u32 value)
+{
+	writel(value, reg);
+}
+
+static inline void cdns_flush_cache(uintptr_t addr, int length)
+{
+	flush_dcache_range(addr, addr + length);
+}
+
+#endif /* __DRIVERS_USB_CDNS_IO_H */
diff --git a/drivers/usb/cdns3/trace.c b/drivers/usb/cdns3/trace.c
deleted file mode 100644
index 459fa72d9c7..00000000000
--- a/drivers/usb/cdns3/trace.c
+++ /dev/null
@@ -1,11 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * USBSS device controller driver Trace Support
- *
- * Copyright (C) 2018-2019 Cadence.
- *
- * Author: Pawel Laszczak <pawell@cadence.com>
- */
-
-#define CREATE_TRACE_POINTS
-#include "trace.h"
diff --git a/drivers/usb/cdns3/trace.h b/drivers/usb/cdns3/trace.h
deleted file mode 100644
index e86c02ae9b3..00000000000
--- a/drivers/usb/cdns3/trace.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#define trace_cdns3_prepare_trb(a, b)
-#define trace_cdns3_doorbell_ep0(a, b)
-#define trace_cdns3_ctrl_req(a)
-#define trace_cdns3_complete_trb(a, b)
-#define trace_cdns3_ep0_irq(a, b)
-#define trace_cdns3_gadget_giveback(a)
-#define trace_cdns3_free_aligned_request(a)
-#define trace_cdns3_prepare_aligned_request(a)
-#define trace_cdns3_ring(a)
-#define trace_cdns3_doorbell_epx(a, b)
-#define trace_cdns3_request_handled(a, b, c)
-#define trace_cdns3_epx_irq(a, b)
-#define trace_cdns3_usb_irq(a, b)
-#define trace_cdns3_alloc_request(a)
-#define trace_cdns3_free_request(a)
-#define trace_cdns3_gadget_ep_enable(a)
-#define trace_cdns3_gadget_ep_disable(a)
-#define trace_cdns3_ep0_queue(a, b)
-#define trace_cdns3_ep0_dequeue(a)
-#define trace_cdns3_ep_queue(a)
-#define trace_cdns3_ep_dequeue(a)
-#define trace_cdns3_halt(a, b, c)
-#define trace_cdns3_wa1(a, b)
-#define trace_cdns3_wa2(a, b)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index b592a487e00..d93c0c5c880 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -465,7 +465,6 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
 /* set global incr burst type configuration registers */
 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 {
-	struct udevice *dev = dwc->dev;
 	u32 cfg;
 
 	if (!dwc->incrx_size)
@@ -502,13 +501,32 @@ static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 	case 1:
 		break;
 	default:
-		dev_err(dev, "Invalid property\n");
+		dev_err(dwc->dev, "Invalid property\n");
 		break;
 	}
 
 	dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
 }
 
+void dwc3_set_suspend_clk(struct dwc3 *dwc)
+{
+	u32 reg;
+
+	/*
+	 * DWC3_GCTL.PWRDNSCALE: The USB3 suspend_clk input replaces
+	 * pipe3_rx_pclk as a clock source to a small part of the USB3
+	 * core that operates when the SS PHY is in its lowest power
+	 * (P3) state, and therefore does not provide a clock.
+	 * The Power Down Scale field specifies how many suspend_clk
+	 * periods fit into a 16 kHz clock period. When performing the
+	 * division, round up the remainder.
+	 */
+	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
+	reg &= ~(DWC3_GCTL_PWRDNSCALE(0x1fff));
+	reg |= DWC3_GCTL_PWRDNSCALE(dwc->power_down_scale);
+	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
+}
+
 /**
  * dwc3_core_init - Low-level initialization of DWC3 Core
  * @dwc: Pointer to our controller context structure
@@ -559,6 +577,9 @@ static int dwc3_core_init(struct dwc3 *dwc)
 	if (ret)
 		goto err0;
 
+	if (dwc->power_down_scale)
+		dwc3_set_suspend_clk(dwc);
+
 	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 
@@ -629,6 +650,20 @@ static int dwc3_core_init(struct dwc3 *dwc)
 
 	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 
+	/*
+	 * Disable Park Mode:
+	 * Park mode can only be used in host mode with only a single
+	 * async endpoint is active, but which has a known issue cause
+	 * USB3.0 HC may die when read and write at the same time,
+	 * considering this mode only can improve the delay between
+	 * bursts in case only one endpoint is active, it's not really
+	 * useful, so disable it, Synopsys will release a formal STAR
+	 * and disable it by default in next IP release.
+	 */
+	reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
+	reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
+	dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
+
 	ret = dwc3_alloc_scratch_buffers(dwc);
 	if (ret)
 		goto err0;
@@ -700,12 +735,6 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
 	return 0;
 }
 
-static void dwc3_gadget_run(struct dwc3 *dwc)
-{
-	dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
-	mdelay(100);
-}
-
 static void dwc3_core_stop(struct dwc3 *dwc)
 {
 	u32 reg;
@@ -731,13 +760,6 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc)
 		/* do nothing */
 		break;
 	}
-
-	/*
-	 * switch back to peripheral mode
-	 * This enables the phy to enter idle and then, if enabled, suspend.
-	 */
-	dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
-	dwc3_gadget_run(dwc);
 }
 
 #define DWC3_ALIGN_MASK		(16 - 1)
@@ -818,6 +840,8 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
 	if (dwc3_dev->tx_de_emphasis)
 		tx_de_emphasis = dwc3_dev->tx_de_emphasis;
 
+	dwc->power_down_scale = dwc3_dev->power_down_scale;
+
 	/* default to superspeed if no maximum_speed passed */
 	if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
 		dwc->maximum_speed = USB_SPEED_SUPER;
@@ -902,6 +926,7 @@ void dwc3_uboot_exit(int index)
 		dwc3_core_exit_mode(dwc);
 		dwc3_event_buffers_cleanup(dwc);
 		dwc3_free_event_buffers(dwc);
+		dwc3_core_stop(dwc);
 		dwc3_core_exit(dwc);
 		list_del(&dwc->list);
 		kfree(dwc->mem);
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index d7cce3a861a..64b5b3dd2ec 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -180,6 +180,8 @@
 /* Global User Control 1 Register */
 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	BIT(24)
+/* Disable park mode for super speed */
+#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
 
 /* Global USB2 PHY Configuration Register */
 #define DWC3_GUSB2PHYCFG_PHYSOFTRST	(1 << 31)
@@ -681,6 +683,7 @@ struct dwc3_scratchpad_array {
  *		- USBPHY_INTERFACE_MODE_UTMIW
  * @dcfg: saved contents of DCFG register
  * @gctl: saved contents of GCTL register
+ * @power_down_scale: 16KHz clock periods for suspend_clk
  * @isoch_delay: wValue from Set Isochronous Delay request;
  * @u2sel: parameter from Set SEL request.
  * @u2pel: parameter from Set SEL request.
@@ -807,6 +810,7 @@ struct dwc3 {
 	enum dwc3_ep0_state	ep0state;
 	enum dwc3_link_state	link_state;
 
+	u16			power_down_scale;
 	u16			isoch_delay;
 	u16			u2sel;
 	u16			u2pel;
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 01bd0ca190e..c7ed2a64ca1 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -138,7 +138,7 @@ static int dwc3_generic_of_to_plat(struct udevice *dev)
 }
 
 #if CONFIG_IS_ENABLED(DM_USB_GADGET)
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
+static int dwc3_generic_peripheral_handle_interrupts(struct udevice *dev)
 {
 	struct dwc3_generic_priv *priv = dev_get_priv(dev);
 	struct dwc3 *dwc3 = &priv->dwc3;
@@ -168,6 +168,7 @@ U_BOOT_DRIVER(dwc3_generic_peripheral) = {
 	.of_to_plat = dwc3_generic_of_to_plat,
 	.probe = dwc3_generic_peripheral_probe,
 	.remove = dwc3_generic_peripheral_remove,
+	.handle_interrupts = dwc3_generic_peripheral_handle_interrupts,
 	.priv_auto	= sizeof(struct dwc3_generic_priv),
 	.plat_auto	= sizeof(struct dwc3_generic_plat),
 };
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 75ac993bc64..a93764b0bb0 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -394,7 +394,6 @@ static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 	u32			recip;
 	u32			wValue;
 	u32			wIndex;
-	u32			reg;
 	int			ret;
 	enum usb_device_state	state;
 
@@ -418,27 +417,12 @@ static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 				return -EINVAL;
 			if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 				return -EINVAL;
-
-			reg = dwc3_readl(dwc->regs, DWC3_DCTL);
-			if (set)
-				reg |= DWC3_DCTL_INITU1ENA;
-			else
-				reg &= ~DWC3_DCTL_INITU1ENA;
-			dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 			break;
-
 		case USB_DEVICE_U2_ENABLE:
 			if (state != USB_STATE_CONFIGURED)
 				return -EINVAL;
 			if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 				return -EINVAL;
-
-			reg = dwc3_readl(dwc->regs, DWC3_DCTL);
-			if (set)
-				reg |= DWC3_DCTL_INITU2ENA;
-			else
-				reg &= ~DWC3_DCTL_INITU2ENA;
-			dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 			break;
 
 		case USB_DEVICE_LTM_ENABLE:
@@ -542,7 +526,6 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 	enum usb_device_state state = dwc->gadget.state;
 	u32 cfg;
 	int ret;
-	u32 reg;
 
 	dwc->start_config_issued = false;
 	cfg = le16_to_cpu(ctrl->wValue);
@@ -566,14 +549,6 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 				usb_gadget_set_state(&dwc->gadget,
 						USB_STATE_CONFIGURED);
 
-			/*
-			 * Enable transition to U1/U2 state when
-			 * nothing is pending from application.
-			 */
-			reg = dwc3_readl(dwc->regs, DWC3_DCTL);
-			reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
-			dwc3_writel(dwc->regs, DWC3_DCTL, reg);
-
 			dwc->resize_fifos = true;
 			dev_dbg(dwc->dev, "resize FIFOs flag SET");
 		}
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index eb416b832aa..e94fa08ec30 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -972,8 +972,8 @@ static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
 	 * so HACK the request length
 	 */
 	if (dep->direction == 0 &&
-	    req->request.length < dep->endpoint.maxpacket)
-		req->request.length = dep->endpoint.maxpacket;
+	    req->request.length < usb_endpoint_maxp(dep->endpoint.desc))
+		req->request.length = usb_endpoint_maxp(dep->endpoint.desc);
 
 	/*
 	 * We only add to our list of requests now and
@@ -1486,7 +1486,7 @@ static int dwc3_gadget_start(struct usb_gadget *g,
 	if (dwc->revision < DWC3_REVISION_220A) {
 		reg |= DWC3_DCFG_SUPERSPEED;
 	} else {
-		switch (dwc->maximum_speed) {
+		switch (dwc->gadget.max_speed) {
 		case USB_SPEED_LOW:
 			reg |= DWC3_DSTS_LOWSPEED;
 			break;
@@ -1610,7 +1610,12 @@ static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
 		} else {
 			int		ret;
 
-			usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
+			if (dwc->maximum_speed >= USB_SPEED_SUPER)
+				usb_ep_set_maxpacket_limit(&dep->endpoint,
+							   1024);
+			else
+				usb_ep_set_maxpacket_limit(&dep->endpoint,
+							   512);
 			dep->endpoint.max_streams = 15;
 			dep->endpoint.ops = &dwc3_gadget_ep_ops;
 			list_add_tail(&dep->endpoint.ep_list,
@@ -2563,6 +2568,7 @@ static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
 int dwc3_gadget_init(struct dwc3 *dwc)
 {
 	int					ret;
+	u32 reg;
 
 	dwc->ctrl_req = dma_alloc_coherent(sizeof(*dwc->ctrl_req),
 					(unsigned long *)&dwc->ctrl_req_addr);
@@ -2596,7 +2602,7 @@ int dwc3_gadget_init(struct dwc3 *dwc)
 	}
 
 	dwc->gadget.ops			= &dwc3_gadget_ops;
-	dwc->gadget.max_speed		= USB_SPEED_SUPER;
+	dwc->gadget.max_speed		= dwc->maximum_speed;
 	dwc->gadget.speed		= USB_SPEED_UNKNOWN;
 	dwc->gadget.name		= "dwc3-gadget";
 
@@ -2621,6 +2627,10 @@ int dwc3_gadget_init(struct dwc3 *dwc)
 		goto err4;
 	}
 
+	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
+	reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA);
+	dwc3_writel(dwc->regs, DWC3_DCTL, reg);
+
 	return 0;
 
 err4:
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index d81a9c5a100..ee492e324d0 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -112,6 +112,7 @@ config USB_GADGET_OS_DESCRIPTORS
 config CI_UDC
 	bool "ChipIdea device controller"
 	select USB_GADGET_DUALSPEED
+	imply DM_USB_GADGET
 	help
 	  Say Y here to enable device controller functionality of the
 	  ChipIdea driver.
@@ -191,6 +192,15 @@ config USB_FUNCTION_ACM
 	  interoperate with MS-Windows hosts or with the Linux-USB "cdc-acm"
 	  driver.
 
+config USB_PORT_AUTO
+	bool "Enable USB port autodetect"
+	depends on CI_UDC
+	help
+	  Enable usb port autodetect function for i.MX8. There two usb ports -
+	  usb2 and usb3 on i.MX8, when use SDP or fastboot which runs automatically
+	  when uboot starts, enable this config will autodetect the  connected usb
+	  port instead of specify USB port to download in code.
+
 endif # USB_GADGET_DOWNLOAD
 
 config USB_ETHER
diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c
index 542684c1c30..2bae39347db 100644
--- a/drivers/usb/gadget/ci_udc.c
+++ b/drivers/usb/gadget/ci_udc.c
@@ -13,16 +13,26 @@
 #include <cpu_func.h>
 #include <net.h>
 #include <malloc.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <clk.h>
+#include <power-domain.h>
 #include <asm/byteorder.h>
 #include <asm/cache.h>
 #include <linux/delay.h>
 #include <linux/errno.h>
 #include <asm/io.h>
 #include <asm/unaligned.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/regs-usbphy.h>
 #include <linux/types.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
+#include <linux/usb/otg.h>
+#include <dm/pinctrl.h>
 #include <usb/ci_udc.h>
+#include <usb/ehci-ci.h>
 #include "../host/ehci.h"
 #include "ci_udc.h"
 
@@ -93,9 +103,18 @@ static int ci_ep_dequeue(struct usb_ep *ep, struct usb_request *req);
 static struct usb_request *
 ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags);
 static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req);
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+static int ci_udc_gadget_start(struct usb_gadget *g,
+			       struct usb_gadget_driver *driver);
+static int ci_udc_gadget_stop(struct usb_gadget *g);
+#endif
 
 static struct usb_gadget_ops ci_udc_ops = {
 	.pullup = ci_pullup,
+#if CONFIG_IS_ENABLED(DM_USB_GADGET)
+	.udc_start		= ci_udc_gadget_start,
+	.udc_stop		= ci_udc_gadget_stop,
+#endif
 };
 
 static struct usb_ep_ops ci_ep_ops = {
@@ -869,7 +888,7 @@ void udc_irq(void)
 	}
 }
 
-int usb_gadget_handle_interrupts(int index)
+int ci_udc_handle_interrupts(void)
 {
 	u32 value;
 	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
@@ -1013,6 +1032,108 @@ static int ci_udc_probe(void)
 	return 0;
 }
 
+bool dfu_usb_get_reset(void)
+{
+	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
+
+	return !!(readl(&udc->usbsts) & STS_URI);
+}
+
+static int ci_udc_otg_phy_mode2(void *__iomem phy_base)
+{
+	void *__iomem phy_ctrl, *__iomem phy_status;
+	u32 val;
+
+	if (is_mx6() || is_mx7ulp() || is_imx8() || is_imx8ulp()) {
+		phy_ctrl = (void __iomem *)(phy_base + USBPHY_CTRL);
+		val = readl(phy_ctrl);
+		if (val & USBPHY_CTRL_OTG_ID)
+			return USB_INIT_DEVICE;
+		else
+			return USB_INIT_HOST;
+	} else if (is_mx7() || is_imx8mm() || is_imx8mn() || is_imx93()) {
+		phy_status = (void __iomem *)(phy_base +
+					      USBNC_PHY_STATUS_OFFSET);
+		val = readl(phy_status);
+		if (val & USBNC_PHYSTATUS_ID_DIG)
+			return USB_INIT_DEVICE;
+		else
+			return USB_INIT_HOST;
+	} else {
+		return -EINVAL;
+	}
+}
+
+bool udc_irq_reset(void)
+{
+	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
+	unsigned n = readl(&udc->usbsts);
+	writel(n, &udc->usbsts);
+
+	n &= (STS_SLI | STS_URI | STS_PCI | STS_UI | STS_UEI);
+	if (n == 0)
+		return false;
+
+	if (n & STS_URI) {
+		DBG("-- reset --\n");
+		return true;
+	}
+
+	if (n & STS_SLI)
+		DBG("-- suspend --\n");
+
+	return false;
+}
+
+bool ci_udc_check_bus_active(ulong ehci_addr, struct ehci_mx6_phy_data *phy_data, int index)
+{
+	struct usb_ehci *ehci = (struct usb_ehci *)ehci_addr;
+	struct ehci_ctrl ctrl;
+	int ret;
+	bool active = false;
+
+	ehci_mx6_phy_init(ehci, phy_data, index);
+	if (ci_udc_otg_phy_mode2(phy_data->phy_addr) != USB_INIT_DEVICE)
+		return false;
+
+	ctrl.hccr = (struct ehci_hccr *)((ulong)&ehci->caplength);
+	ctrl.hcor = (struct ehci_hcor *)((ulong)ctrl.hccr +
+			HC_LENGTH(ehci_readl(&(ctrl.hccr)->cr_capbase)));
+	controller.ctrl = &ctrl;
+
+	ret = ci_udc_probe();
+	if (ret) {
+		return false;
+	}
+
+	ci_pullup(NULL, 1);
+
+	int count = 100;
+	while (count > 0) {
+		if (udc_irq_reset()) {
+			active = true;
+			break;
+		}
+		mdelay(10);
+		count--;
+	}
+
+	ci_pullup(NULL, 0);
+
+	ci_ep_free_request(&controller.ep[0].ep, &controller.ep0_req->req);
+	free(controller.items_mem);
+	free(controller.epts);
+
+	return active;
+}
+
+
+#if !CONFIG_IS_ENABLED(DM_USB_GADGET)
+int usb_gadget_handle_interrupts(int index)
+{
+	return ci_udc_handle_interrupts();
+}
+
 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
 {
 	int ret;
@@ -1066,10 +1187,331 @@ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
 
 	return 0;
 }
+#else /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
 
-bool dfu_usb_get_reset(void)
+static int ci_udc_gadget_start(struct usb_gadget *g,
+			       struct usb_gadget_driver *driver)
 {
-	struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
+	if (!driver)
+		return -EINVAL;
+	if (!driver->bind || !driver->setup || !driver->disconnect)
+		return -EINVAL;
 
-	return !!(readl(&udc->usbsts) & STS_URI);
+	controller.driver = driver;
+	return 0;
+}
+
+static int ci_udc_gadget_stop(struct usb_gadget *g)
+{
+	controller.driver = NULL;
+
+	ci_ep_free_request(&controller.ep[0].ep, &controller.ep0_req->req);
+	free(controller.items_mem);
+	free(controller.epts);
+	return 0;
+}
+
+struct ci_udc_priv_data {
+	struct ehci_ctrl ctrl;
+	struct udevice otgdev;
+	struct clk_bulk		clks;
+	int phy_off;
+	struct power_domain otg_pd;
+	struct clk phy_clk;
+	struct power_domain phy_pd;
+	struct ehci_mx6_phy_data phy_data;
+};
+
+static int ci_udc_gadget_handle_interrupts(struct udevice *dev)
+{
+	return ci_udc_handle_interrupts();
+}
+
+static int ci_udc_phy_setup(struct udevice *dev, struct ci_udc_priv_data *priv)
+{
+	void *__iomem addr;
+	int misc_off;
+
+	struct udevice __maybe_unused phy_dev;
+	priv->phy_off = fdtdec_lookup_phandle(gd->fdt_blob,
+					      dev_of_offset(dev),
+					      "fsl,usbphy");
+	if (priv->phy_off < 0) {
+		priv->phy_off = fdtdec_lookup_phandle(gd->fdt_blob,
+					      dev_of_offset(dev), "phys");
+		if (priv->phy_off < 0)
+			return -EINVAL;
+	}
+
+	addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent(gd->fdt_blob,
+		priv->phy_off, "reg", 0, NULL, false);
+	if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
+		addr = NULL;
+
+	priv->phy_data.phy_addr = addr;
+
+	misc_off = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), "fsl,usbmisc");
+	if (misc_off < 0)
+		return -EINVAL;
+
+	addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent(gd->fdt_blob,
+		misc_off, "reg", 0, NULL, false);
+	if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->phy_data.misc_addr = addr;
+
+#if defined(CONFIG_MX6)
+	int anatop_off;
+
+	/* Resolve ANATOP offset through USB PHY node */
+	anatop_off = fdtdec_lookup_phandle(gd->fdt_blob, priv->phy_off, "fsl,anatop");
+	if (anatop_off < 0)
+		return -EINVAL;
+
+	addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent(gd->fdt_blob,
+		anatop_off, "reg", 0, NULL, false);
+	if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->phy_data.anatop_addr = addr;
+#endif
+
+	dev_set_ofnode(&phy_dev, offset_to_ofnode(priv->phy_off));
+
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+	/* Need to power on the PHY before access it */
+	if (!power_domain_get(&phy_dev, &priv->phy_pd)) {
+		if (power_domain_on(&priv->phy_pd))
+			return -EINVAL;
+	}
+#endif
+
+#if CONFIG_IS_ENABLED(CLK)
+	int ret;
+
+	ret = clk_get_by_index(&phy_dev, 0, &priv->phy_clk);
+	if (ret) {
+		printf("Failed to get phy_clk\n");
+		return ret;
+	}
+
+	ret = clk_enable(&priv->phy_clk);
+	if (ret) {
+		printf("Failed to enable phy_clk\n");
+		return ret;
+	}
+#endif
+
+	return 0;
+}
+
+static int ci_udc_phy_shutdown(struct ci_udc_priv_data *priv)
+{
+	int ret = 0;
+
+#if CONFIG_IS_ENABLED(CLK)
+	if (priv->phy_clk.dev) {
+		ret = clk_disable(&priv->phy_clk);
+		if (ret)
+			return ret;
+
+		ret = clk_free(&priv->phy_clk);
+		if (ret)
+			return ret;
+	}
+#endif
+
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+	if (priv->phy_pd.dev) {
+		ret = power_domain_off(&priv->phy_pd);
+		if (ret)
+			printf("Power down USB PHY failed! (error = %d)\n", ret);
+	}
+#endif
+	return ret;
+}
+
+static int ci_udc_otg_clk_init(struct udevice *dev,
+			       struct clk_bulk *clks)
+{
+#if CONFIG_IS_ENABLED(CLK)
+	int ret;
+
+	ret = clk_get_bulk(dev, clks);
+	if (ret == -ENOSYS)
+		return 0;
+
+	if (ret)
+		return ret;
+
+	ret = clk_enable_bulk(clks);
+	if (ret) {
+		clk_release_bulk(clks);
+		return ret;
+	}
+#else
+	enable_usboh3_clk(1);
+#endif
+
+	return 0;
 }
+
+static int ci_udc_otg_phy_mode(struct udevice *dev)
+{
+	struct ci_udc_priv_data *priv = dev_get_priv(dev);
+
+	void *__iomem phy_ctrl, *__iomem phy_status;
+	void *__iomem phy_base = (void *__iomem)devfdt_get_addr(&priv->otgdev);
+	u32 val;
+
+	if (is_mx6() || is_mx7ulp() || is_imx8() || is_imx8ulp()) {
+		phy_base = (void __iomem *)fdtdec_get_addr_size_auto_noparent(gd->fdt_blob,
+							   priv->phy_off,
+							   "reg", 0, NULL, false);
+		if ((fdt_addr_t)phy_base == FDT_ADDR_T_NONE)
+			return -EINVAL;
+
+		phy_ctrl = (void __iomem *)(phy_base + USBPHY_CTRL);
+		val = readl(phy_ctrl);
+		if (val & USBPHY_CTRL_OTG_ID)
+			return USB_INIT_DEVICE;
+		else
+			return USB_INIT_HOST;
+	} else if (is_mx7() || is_imx8mm() || is_imx8mn() || is_imx93()) {
+		phy_status = (void __iomem *)(phy_base +
+					      USBNC_PHY_STATUS_OFFSET);
+		val = readl(phy_status);
+		if (val & USBNC_PHYSTATUS_ID_DIG)
+			return USB_INIT_DEVICE;
+		else
+			return USB_INIT_HOST;
+	} else {
+		return -EINVAL;
+	}
+}
+
+static int ci_udc_otg_ofdata_to_platdata(struct udevice *dev)
+{
+	struct ci_udc_priv_data *priv = dev_get_priv(dev);
+	int node = dev_of_offset(dev);
+	int usbotg_off;
+
+	if (usb_get_dr_mode(dev_ofnode(dev)) != USB_DR_MODE_PERIPHERAL) {
+		dev_dbg(dev, "Invalid mode\n");
+		return -ENODEV;
+	}
+
+	usbotg_off = fdtdec_lookup_phandle(gd->fdt_blob,
+					   node,
+					   "chipidea,usb");
+	if (usbotg_off < 0)
+		return -EINVAL;
+	dev_set_ofnode(&priv->otgdev, offset_to_ofnode(usbotg_off));
+	priv->otgdev.parent = dev->parent;
+
+	return 0;
+}
+
+static int ci_udc_otg_probe(struct udevice *dev)
+{
+	struct ci_udc_priv_data *priv = dev_get_priv(dev);
+	struct usb_ehci *ehci;
+	int ret;
+
+	ehci = (struct usb_ehci *)devfdt_get_addr(&priv->otgdev);
+
+	ret = pinctrl_select_state(&priv->otgdev, "default");
+	if (ret)
+		DBG("Failed to configure default pinctrl\n");
+
+#if defined(CONFIG_MX6)
+	if (usb_fused((u32)ehci)) {
+		printf("USB@0x%x is fused, disable it\n", (u32)ehci);
+		return -ENODEV;
+	}
+#endif
+
+	ret = board_usb_init(dev_seq(dev), USB_INIT_DEVICE);
+	if (ret) {
+		printf("Failed to initialize board for USB\n");
+		return ret;
+	}
+
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+	if (!power_domain_get(&priv->otgdev, &priv->otg_pd)) {
+		if (power_domain_on(&priv->otg_pd))
+			return -EINVAL;
+	}
+#endif
+
+	ret = ci_udc_phy_setup(&priv->otgdev, priv);
+	if (ret)
+		return ret;
+
+	ret = ci_udc_otg_clk_init(&priv->otgdev, &priv->clks);
+	if (ret)
+		return ret;
+
+	ehci_mx6_phy_init(ehci, &priv->phy_data, dev_seq(dev));
+
+	if (ci_udc_otg_phy_mode(dev) != USB_INIT_DEVICE)
+		return -ENODEV;
+
+	priv->ctrl.hccr = (struct ehci_hccr *)((ulong)&ehci->caplength);
+	priv->ctrl.hcor = (struct ehci_hcor *)((ulong)priv->ctrl.hccr +
+			HC_LENGTH(ehci_readl(&(priv->ctrl.hccr)->cr_capbase)));
+	controller.ctrl = &priv->ctrl;
+
+	ret = ci_udc_probe();
+	if (ret) {
+		DBG("udc probe failed, returned %d\n", ret);
+		return ret;
+	}
+
+	ret = usb_add_gadget_udc((struct device *)dev, &controller.gadget);
+
+	return ret;
+}
+
+static int ci_udc_otg_remove(struct udevice *dev)
+{
+	struct ci_udc_priv_data *priv = dev_get_priv(dev);
+
+	usb_del_gadget_udc(&controller.gadget);
+
+#if CONFIG_IS_ENABLED(CLK)
+	clk_release_bulk(&priv->clks);
+#endif
+	ci_udc_phy_shutdown(priv);
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+	if (priv->otg_pd.dev) {
+		if (power_domain_off(&priv->otg_pd)) {
+			printf("Power down USB controller failed!\n");
+			return -EINVAL;
+		}
+	}
+#endif
+	board_usb_cleanup(dev_seq(dev), USB_INIT_DEVICE);
+
+	controller.ctrl = NULL;
+	return 0;
+}
+
+static const struct udevice_id ci_udc_otg_ids[] = {
+	{ .compatible = "fsl,imx27-usb-gadget" },
+	{ }
+};
+
+U_BOOT_DRIVER(ci_udc_otg) = {
+	.name	= "ci-udc-otg",
+	.id	= UCLASS_USB_GADGET_GENERIC,
+	.of_match = ci_udc_otg_ids,
+	.of_to_plat = ci_udc_otg_ofdata_to_platdata,
+	.probe = ci_udc_otg_probe,
+	.remove = ci_udc_otg_remove,
+	.handle_interrupts = ci_udc_gadget_handle_interrupts,
+	.priv_auto = sizeof(struct ci_udc_priv_data),
+};
+
+#endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */
diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c
index 01337d6511b..cd44a61c6e8 100644
--- a/drivers/usb/gadget/epautoconf.c
+++ b/drivers/usb/gadget/epautoconf.c
@@ -143,6 +143,7 @@ static int ep_matches(
 	/* MATCH!! */
 
 	/* report address */
+	desc->bEndpointAddress &= 0xF0;
 	if (isdigit(ep->name[2])) {
 		u8	num = dectoul(&ep->name[2], NULL);
 		desc->bEndpointAddress |= num;
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 8ba55aab9f8..5cc2c2e4583 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -22,6 +22,8 @@
 #include <linux/usb/composite.h>
 #include <linux/compiler.h>
 #include <g_dnl.h>
+#include <serial.h>
+#include <stdio_dev.h>
 
 #define FASTBOOT_INTERFACE_CLASS	0xff
 #define FASTBOOT_INTERFACE_SUB_CLASS	0x42
@@ -38,16 +40,24 @@
  * that expect bulk OUT requests to be divisible by maxpacket size.
  */
 
+typedef struct usb_req usb_req;
+struct usb_req {
+	struct usb_request *in_req;
+	usb_req *next;
+};
+
 struct f_fastboot {
 	struct usb_function usb_function;
 
 	/* IN/OUT EP's and corresponding requests */
 	struct usb_ep *in_ep, *out_ep;
 	struct usb_request *in_req, *out_req;
+
+	usb_req *front, *rear;
 };
 
 static char fb_ext_prop_name[] = "DeviceInterfaceGUID";
-static char fb_ext_prop_data[] = "{4866319A-F4D6-4374-93B9-DC2DEB361BA9}";
+static char fb_ext_prop_data[] = "{F72FE0D4-CBCB-407d-8814-9ED673D0DD6B}";
 
 static struct usb_os_desc_ext_prop fb_ext_prop = {
 	.type = 1,		/* NUL-terminated Unicode String (REG_SZ) */
@@ -192,8 +202,30 @@ static struct usb_gadget_strings *fastboot_strings[] = {
 	NULL,
 };
 
+#if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT)
+extern struct stdio_dev g_fastboot_stdio;
+#endif
+
 static void rx_handler_command(struct usb_ep *ep, struct usb_request *req);
 
+static void fastboot_fifo_complete(struct usb_ep *ep, struct usb_request *req)
+{
+	int status = req->status;
+	usb_req *request;
+
+	if (!status) {
+		if (fastboot_func->front != NULL) {
+			request = fastboot_func->front;
+			fastboot_func->front = fastboot_func->front->next;
+			usb_ep_free_request(ep, request->in_req);
+			free(request);
+		} else {
+			printf("fail free request\n");
+		}
+		return;
+	}
+}
+
 static void fastboot_complete(struct usb_ep *ep, struct usb_request *req)
 {
 	int status = req->status;
@@ -264,6 +296,10 @@ static int fastboot_bind(struct usb_configuration *c, struct usb_function *f)
 	if (s)
 		g_dnl_set_serialnumber((char *)s);
 
+#if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT)
+	stdio_register(&g_fastboot_stdio);
+#endif
+
 	return 0;
 }
 
@@ -272,6 +308,14 @@ static void fastboot_unbind(struct usb_configuration *c, struct usb_function *f)
 	f->os_desc_table = NULL;
 	list_del(&fb_os_desc.ext_prop);
 	memset(fastboot_func, 0, sizeof(*fastboot_func));
+
+#if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT) && CONFIG_IS_ENABLED(SYS_STDIO_DEREGISTER)
+	struct stdio_dev *dev;
+	dev = stdio_get_by_name("fastboot");
+	if (dev)
+		stdio_deregister_dev(dev, 1);
+#endif
+
 }
 
 static void fastboot_disable(struct usb_function *f)
@@ -397,11 +441,57 @@ static int fastboot_add(struct usb_configuration *c)
 }
 DECLARE_GADGET_BIND_CALLBACK(usb_dnl_fastboot, fastboot_add);
 
-static int fastboot_tx_write(const char *buffer, unsigned int buffer_size)
+int fastboot_tx_write_more(const char *buffer)
+{
+	int ret = 0;
+
+	/* alloc usb request FIFO node */
+	usb_req *req = (usb_req *)malloc(sizeof(usb_req));
+	if (!req) {
+		printf("failed alloc usb req!\n");
+		return -ENOMEM;
+	}
+
+	/* usb request node FIFO enquene */
+	if ((fastboot_func->front == NULL) && (fastboot_func->rear == NULL)) {
+		fastboot_func->front = fastboot_func->rear = req;
+		req->next = NULL;
+	} else {
+		fastboot_func->rear->next = req;
+		fastboot_func->rear = req;
+		req->next = NULL;
+	}
+
+	/* alloc in request for current node */
+	req->in_req = fastboot_start_ep(fastboot_func->in_ep);
+	if (!req->in_req) {
+		printf("failed alloc req in\n");
+		fastboot_disable(&(fastboot_func->usb_function));
+		return  -EINVAL;
+	}
+	req->in_req->complete = fastboot_fifo_complete;
+
+	memcpy(req->in_req->buf, buffer, strlen(buffer));
+	req->in_req->length = strlen(buffer);
+
+	ret = usb_ep_queue(fastboot_func->in_ep, req->in_req, 0);
+	if (ret) {
+		printf("Error %d on queue\n", ret);
+		return -EINVAL;
+	}
+
+	ret = 0;
+	return ret;
+}
+
+int fastboot_tx_write(const char *buffer, unsigned int buffer_size)
 {
 	struct usb_request *in_req = fastboot_func->in_req;
 	int ret;
 
+	if (!buffer_size)
+		return 0;
+
 	memcpy(in_req->buf, buffer, buffer_size);
 	in_req->length = buffer_size;
 
@@ -418,9 +508,17 @@ static int fastboot_tx_write_str(const char *buffer)
 	return fastboot_tx_write(buffer, strlen(buffer));
 }
 
+#ifdef CONFIG_PSCI_BOARD_REBOOT
+int do_board_reboot(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]);
+#endif
+
 static void compl_do_reset(struct usb_ep *ep, struct usb_request *req)
 {
+#ifdef CONFIG_PSCI_BOARD_REBOOT
+	do_board_reboot(NULL, 0, 0, NULL);
+#else
 	do_reset(NULL, 0, 0, NULL);
+#endif
 }
 
 static unsigned int rx_bytes_expected(struct usb_ep *ep)
@@ -512,6 +610,10 @@ static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
 	char response[FASTBOOT_RESPONSE_LEN] = {0};
 	int cmd = -1;
 
+	/* init in request FIFO pointer */
+	fastboot_func->front = NULL;
+	fastboot_func->rear  = NULL;
+
 	if (req->status != 0 || req->length == 0)
 		return;
 
@@ -542,6 +644,9 @@ static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
 		case FASTBOOT_COMMAND_REBOOT_BOOTLOADER:
 		case FASTBOOT_COMMAND_REBOOT_FASTBOOTD:
 		case FASTBOOT_COMMAND_REBOOT_RECOVERY:
+#ifdef CONFIG_ANDROID_RECOVERY
+		case FASTBOOT_COMMAND_RECOVERY_FASTBOOT:
+#endif
 			fastboot_func->in_req->complete = compl_do_reset;
 			break;
 #if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT)
diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c
index afb7b74f305..444707171d6 100644
--- a/drivers/usb/gadget/g_dnl.c
+++ b/drivers/usb/gadget/g_dnl.c
@@ -316,3 +316,8 @@ void g_dnl_unregister(void)
 {
 	usb_composite_unregister(&g_dnl_driver);
 }
+
+int __weak board_usb_gadget_port_auto(void)
+{
+	return -1;
+}
diff --git a/drivers/usb/gadget/udc/Makefile b/drivers/usb/gadget/udc/Makefile
index 95dbf0c82ee..414edad9218 100644
--- a/drivers/usb/gadget/udc/Makefile
+++ b/drivers/usb/gadget/udc/Makefile
@@ -4,6 +4,7 @@
 
 ifndef CONFIG_$(SPL_)DM_USB_GADGET
 obj-$(CONFIG_USB_DWC3_GADGET)	+= udc-core.o
+obj-$(CONFIG_USB_CDNS3_GADGET)	+= udc-core.o
 endif
 
 obj-$(CONFIG_$(SPL_)DM_USB_GADGET)	+= udc-core.o
diff --git a/drivers/usb/gadget/udc/udc-uclass.c b/drivers/usb/gadget/udc/udc-uclass.c
index de8861829c7..d20e051ba1a 100644
--- a/drivers/usb/gadget/udc/udc-uclass.c
+++ b/drivers/usb/gadget/udc/udc-uclass.c
@@ -53,9 +53,20 @@ int usb_gadget_release(int index)
 
 int usb_gadget_handle_interrupts(int index)
 {
+	const struct driver *drv;
+
 	if (index < 0 || index >= ARRAY_SIZE(dev_array))
 		return -EINVAL;
-	return dm_usb_gadget_handle_interrupts(dev_array[index]);
+
+	drv = dev_array[index]->driver;
+	assert(drv);
+
+	if (drv->handle_interrupts)
+		return drv->handle_interrupts(dev_array[index]);
+	else
+		pr_err("No handle_interrupts function found\n");
+
+	return -EINVAL;
 }
 #endif
 
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 8f77412cc71..b42a800ed35 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -114,11 +114,28 @@ config USB_XHCI_BRCM
 	  USB controller based on the Broadcom USB3 IP Core.
 	  Supports USB2/3 functionality.
 
+config USB_XHCI_IMX8
+	bool "XHCI support for i.MX8"
+	depends on ARCH_IMX8
+	default y
+	help
+	  Enables support for the on-chip xHCI controller on i.MX8QM and
+	  i.MX8QXP SoCs.
+
+config USB_XHCI_IMX8M
+	bool "XHCI support for imx8M(mscale)"
+	depends on ARCH_IMX8M
+	select MISC if IMX8MP
+	default y
+	help
+	  Enables support for the on-chip xHCI controller on imx8m(mscale) SoC.
+
 endif # USB_XHCI_HCD
 
 config USB_EHCI_HCD
 	bool "EHCI HCD (USB 2.0) support"
 	default y if ARCH_MX5 || ARCH_MX6
+	default y if ARCH_MX5 || ARCH_MX6 || ARCH_IMX8
 	depends on DM && OF_CONTROL
 	select USB_HOST
 	---help---
@@ -164,17 +181,17 @@ config USB_EHCI_MX5
 	  Enables support for the on-chip EHCI controller on i.MX5 SoCs.
 
 config USB_EHCI_MX6
-	bool "Support for i.MX6/i.MX7ULP on-chip EHCI USB controller"
-	depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMXRT
+	bool "Support for i.MX6/i.MX7ULP/i.MX8 on-chip EHCI USB controller"
+	depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMXRT || ARCH_IMX8 || ARCH_IMX8ULP
 	default y
 	---help---
 	  Enables support for the on-chip EHCI controller on i.MX6 SoCs.
 
 config USB_EHCI_MX7
 	bool "Support for i.MX7 on-chip EHCI USB controller"
-	depends on ARCH_MX7 || IMX8M
-	select PHY if IMX8M
-	select NOP_PHY if IMX8M
+	depends on ARCH_MX7 || IMX8M || IMX93
+	select PHY if IMX8M || IMX93
+	select NOP_PHY if IMX8M || IMX93
 	default y
 	---help---
 	  Enables support for the on-chip EHCI controller on i.MX7 SoCs.
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index eb6fe9f6b30..5bac37d9209 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -56,6 +56,8 @@ obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
 obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o
 obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o
 obj-$(CONFIG_USB_XHCI_OCTEON) += dwc3-octeon-glue.o
+obj-$(CONFIG_USB_XHCI_IMX8) += xhci-imx8.o
+obj-$(CONFIG_USB_XHCI_IMX8M) += xhci-imx8m.o
 
 # designware
 obj-$(CONFIG_USB_DWC2) += dwc2.o
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 060b02accc5..bc57630e38f 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -2,6 +2,8 @@
 /*
  * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
  * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
  */
 
 #include <common.h>
@@ -18,6 +20,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 #include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/regs-usbphy.h>
 #include <asm/mach-imx/sys_proto.h>
 #include <dm.h>
 #include <asm/mach-types.h>
@@ -26,6 +29,11 @@
 #include <linux/usb/phy.h>
 
 #include "ehci.h"
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+#include <power-domain.h>
+#endif
+#include <clk.h>
+#include <usb/usb_mx6_common.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -37,258 +45,31 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define USB_H1_CTRL_OFFSET	0x04
 
-#define USBPHY_CTRL				0x00000030
-#define USBPHY_CTRL_SET				0x00000034
-#define USBPHY_CTRL_CLR				0x00000038
-#define USBPHY_CTRL_TOG				0x0000003c
-
-#define USBPHY_PWD				0x00000000
-#define USBPHY_CTRL_SFTRST			0x80000000
-#define USBPHY_CTRL_CLKGATE			0x40000000
-#define USBPHY_CTRL_ENUTMILEVEL3		0x00008000
-#define USBPHY_CTRL_ENUTMILEVEL2		0x00004000
-#define USBPHY_CTRL_OTG_ID			0x08000000
-
-#define ANADIG_USB2_CHRG_DETECT_EN_B		0x00100000
-#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B	0x00080000
-
-#define ANADIG_USB2_PLL_480_CTRL_BYPASS		0x00010000
-#define ANADIG_USB2_PLL_480_CTRL_ENABLE		0x00002000
-#define ANADIG_USB2_PLL_480_CTRL_POWER		0x00001000
-#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS	0x00000040
-
 #define USBNC_OFFSET		0x200
-#define USBNC_PHY_STATUS_OFFSET	0x23C
-#define USBNC_PHYSTATUS_ID_DIG	(1 << 4) /* otg_id status */
-#define USBNC_PHYCFG2_ACAENB	(1 << 4) /* otg_id detection enable */
-#define UCTRL_PWR_POL		(1 << 9) /* OTG Polarity of Power Pin */
-#define UCTRL_OVER_CUR_POL	(1 << 8) /* OTG Polarity of Overcurrent */
-#define UCTRL_OVER_CUR_DIS	(1 << 7) /* Disable OTG Overcurrent Detection */
-
-/* USBCMD */
-#define UCMD_RUN_STOP           (1 << 0) /* controller run/stop */
-#define UCMD_RESET		(1 << 1) /* controller reset */
 
 /* If this is not defined, assume MX6/MX7/MX8M SoC default */
 #ifndef CONFIG_MXC_USB_PORTSC
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
 #endif
 
-/* Base address for this IP block is 0x02184800 */
-struct usbnc_regs {
-	u32 ctrl[4]; /* otg/host1-3 */
-	u32 uh2_hsic_ctrl;
-	u32 uh3_hsic_ctrl;
-	u32 otg_phy_ctrl_0;
-	u32 uh1_phy_ctrl_0;
-	u32 reserve1[4];
-	u32 phy_cfg1;
-	u32 phy_cfg2;
-	u32 reserve2;
-	u32 phy_status;
-	u32 reserve3[4];
-	u32 adp_cfg1;
-	u32 adp_cfg2;
-	u32 adp_status;
-};
-
-#if defined(CONFIG_MX6) && !defined(CONFIG_PHY)
-static void usb_power_config_mx6(struct anatop_regs __iomem *anatop,
-				 int anatop_bits_index)
+static void ehci_mx6_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
+				   uint32_t *reg)
 {
-	void __iomem *chrg_detect;
-	void __iomem *pll_480_ctrl_clr;
-	void __iomem *pll_480_ctrl_set;
-
-	if (!is_mx6())
-		return;
-
-	switch (anatop_bits_index) {
-	case 0:
-		chrg_detect = &anatop->usb1_chrg_detect;
-		pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
-		pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
-		break;
-	case 1:
-		chrg_detect = &anatop->usb2_chrg_detect;
-		pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
-		pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
-		break;
-	default:
-		return;
-	}
-	/*
-	 * Some phy and power's special controls
-	 * 1. The external charger detector needs to be disabled
-	 * or the signal at DP will be poor
-	 * 2. The PLL's power and output to usb
-	 * is totally controlled by IC, so the Software only needs
-	 * to enable them at initializtion.
-	 */
-	writel(ANADIG_USB2_CHRG_DETECT_EN_B |
-		     ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
-		     chrg_detect);
+	uint32_t result;
+	int usec = 2000;
 
-	writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
-		     pll_480_ctrl_clr);
-
-	writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
-		     ANADIG_USB2_PLL_480_CTRL_POWER |
-		     ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
-		     pll_480_ctrl_set);
-}
-#else
-static void __maybe_unused
-usb_power_config_mx6(void *anatop, int anatop_bits_index) { }
-#endif
-
-#if defined(CONFIG_MX7) && !defined(CONFIG_PHY)
-static void usb_power_config_mx7(struct usbnc_regs *usbnc)
-{
-	void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
-
-	if (!is_mx7())
-		return;
-
-	/*
-	 * Clear the ACAENB to enable usb_otg_id detection,
-	 * otherwise it is the ACA detection enabled.
-	 */
-	clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
-}
-#else
-static void __maybe_unused
-usb_power_config_mx7(void *usbnc) { }
-#endif
-
-#if defined(CONFIG_MX7ULP) && !defined(CONFIG_PHY)
-static void usb_power_config_mx7ulp(struct usbphy_regs __iomem *usbphy)
-{
-	if (!is_mx7ulp())
-		return;
+	mdelay(50);
 
-	writel(ANADIG_USB2_CHRG_DETECT_EN_B |
-	       ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
-	       &usbphy->usb1_chrg_detect);
+	do {
+		result = ehci_readl(status_reg);
+		udelay(5);
+		if (!(result & EHCI_PS_PR))
+			break;
+		usec--;
+	} while (usec > 0);
 
-	scg_enable_usb_pll(true);
+	*reg = ehci_readl(status_reg);
 }
-#else
-static void __maybe_unused
-usb_power_config_mx7ulp(void *usbphy) { }
-#endif
-
-#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
-static const unsigned phy_bases[] = {
-	USB_PHY0_BASE_ADDR,
-#if defined(USB_PHY1_BASE_ADDR)
-	USB_PHY1_BASE_ADDR,
-#endif
-};
-
-#if !defined(CONFIG_PHY)
-static void usb_internal_phy_clock_gate(void __iomem *phy_reg, int on)
-{
-	phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
-	writel(USBPHY_CTRL_CLKGATE, phy_reg);
-}
-
-/* Return 0 : host node, <>0 : device mode */
-static int usb_phy_enable(struct usb_ehci *ehci, void __iomem *phy_reg)
-{
-	void __iomem *phy_ctrl;
-	void __iomem *usb_cmd;
-	int ret;
-
-	phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
-	usb_cmd = (void __iomem *)&ehci->usbcmd;
-
-	/* Stop then Reset */
-	clrbits_le32(usb_cmd, UCMD_RUN_STOP);
-	ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
-	if (ret)
-		return ret;
-
-	setbits_le32(usb_cmd, UCMD_RESET);
-	ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
-	if (ret)
-		return ret;
-
-	/* Reset USBPHY module */
-	setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
-	udelay(10);
-
-	/* Remove CLKGATE and SFTRST */
-	clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
-	udelay(10);
-
-	/* Power up the PHY */
-	writel(0, phy_reg + USBPHY_PWD);
-	/* enable FS/LS device */
-	setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
-			USBPHY_CTRL_ENUTMILEVEL3);
-
-	return 0;
-}
-#endif
-
-int usb_phy_mode(int port)
-{
-	void __iomem *phy_reg;
-	void __iomem *phy_ctrl;
-	u32 val;
-
-	phy_reg = (void __iomem *)phy_bases[port];
-	phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
-
-	val = readl(phy_ctrl);
-
-	if (val & USBPHY_CTRL_OTG_ID)
-		return USB_INIT_DEVICE;
-	else
-		return USB_INIT_HOST;
-}
-
-#elif defined(CONFIG_MX7)
-int usb_phy_mode(int port)
-{
-	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
-			(0x10000 * port) + USBNC_OFFSET);
-	void __iomem *status = (void __iomem *)(&usbnc->phy_status);
-	u32 val;
-
-	val = readl(status);
-
-	if (val & USBNC_PHYSTATUS_ID_DIG)
-		return USB_INIT_DEVICE;
-	else
-		return USB_INIT_HOST;
-}
-#endif
-
-#if !defined(CONFIG_PHY)
-/* Should be done in the MXS PHY driver */
-static void usb_oc_config(struct usbnc_regs *usbnc, int index)
-{
-	void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
-
-#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
-	/* mx6qarm2 seems to required a different setting*/
-	clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
-#else
-	setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
-#endif
-
-	setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
-
-	/* Set power polarity to high active */
-#ifdef CONFIG_MXC_USB_OTG_HACTIVE
-	setbits_le32(ctrl, UCTRL_PWR_POL);
-#else
-	clrbits_le32(ctrl, UCTRL_PWR_POL);
-#endif
-}
-#endif
 
 #if !CONFIG_IS_ENABLED(DM_USB)
 /**
@@ -337,34 +118,48 @@ int __weak board_ehci_power(int port, int on)
 	return 0;
 }
 
+static const struct ehci_ops mx6_ehci_ops = {
+	.powerup_fixup		= ehci_mx6_powerup_fixup,
+};
+
 int ehci_hcd_init(int index, enum usb_init_type init,
 		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	enum usb_init_type type;
+	struct ehci_mx6_phy_data phy_data;
+	memset(&phy_data, 0, sizeof(phy_data));
+
 #if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
+	if (index > 3)
+			return -EINVAL;
+
 	u32 controller_spacing = 0x200;
-	struct anatop_regs __iomem *anatop =
-		(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
-	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
+	phy_data.anatop_addr = (void __iomem *)ANATOP_BASE_ADDR;
+	phy_data.misc_addr = (void __iomem *)(USB_BASE_ADDR +
 			USB_OTHERREGS_OFFSET);
-#elif defined(CONFIG_MX7)
-	u32 controller_spacing = 0x10000;
-	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
-			(0x10000 * index) + USBNC_OFFSET);
-#elif defined(CONFIG_MX7ULP)
+	if (index < ARRAY_SIZE(phy_bases))
+		phy_data.phy_addr = (void __iomem *)(ulong)phy_bases[index];
+
+#elif defined(CONFIG_USB_EHCI_MX7)
+	if (index > 1)
+		return -EINVAL;
+
 	u32 controller_spacing = 0x10000;
-	struct usbphy_regs __iomem *usbphy =
-		(struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
-	struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
+	phy_data.misc_addr = (void __iomem *)(ulong)(USB_BASE_ADDR +
 			(0x10000 * index) + USBNC_OFFSET);
+#elif defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8ULP)
+	if (index >= ARRAY_SIZE(phy_bases))
+		return -EINVAL;
+
+	u32 controller_spacing = is_imx8ulp()? 0x20000: 0x10000;
+	phy_data.phy_addr = (void __iomem *)(ulong)phy_bases[index];
+	phy_data.misc_addr = (void __iomem *)(ulong)(USB_BASE_ADDR +
+			(controller_spacing * index) + USBNC_OFFSET);
 #endif
-	struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
+	struct usb_ehci *ehci = (struct usb_ehci *)(ulong)(USB_BASE_ADDR +
 		(controller_spacing * index));
 	int ret;
 
-	if (index > 3)
-		return -EINVAL;
-
 	if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
 		if (usb_fused((ulong)ehci)) {
 			printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
@@ -383,22 +178,9 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 		return ret;
 	}
 
-#if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
-	usb_power_config_mx6(anatop, index);
-#elif defined (CONFIG_MX7)
-	usb_power_config_mx7(usbnc);
-#elif defined (CONFIG_MX7ULP)
-	usb_power_config_mx7ulp(usbphy);
-#endif
-
-	usb_oc_config(usbnc, index);
+	ehci_mx6_phy_init(ehci, &phy_data, index);
 
-#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
-	if (index < ARRAY_SIZE(phy_bases)) {
-		usb_internal_phy_clock_gate((void __iomem *)phy_bases[index], 1);
-		usb_phy_enable(ehci, (void __iomem *)phy_bases[index]);
-	}
-#endif
+	ehci_set_controller_priv(index, NULL, &mx6_ehci_ops);
 
 	type = board_usb_phy_mode(index);
 
@@ -412,6 +194,11 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 		board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
 	if (type != init)
 		return -ENODEV;
+
+	if (is_mx6dqp() || is_mx6dq() || is_mx6sdl() ||
+		((is_mx6sl() || is_mx6sx()) && type == USB_INIT_HOST))
+		setbits_le32(&ehci->usbmode, SDIS);
+
 	if (type == USB_INIT_DEVICE)
 		return 0;
 
@@ -437,11 +224,17 @@ struct ehci_mx6_priv_data {
 	struct phy phy;
 	enum usb_init_type init_type;
 	enum usb_phy_interface phy_type;
-#if !defined(CONFIG_PHY)
 	int portnr;
-	void __iomem *phy_addr;
-	void __iomem *misc_addr;
-	void __iomem *anatop_addr;
+	int phy_node_off;
+#if !CONFIG_IS_ENABLED(PHY) || defined(CONFIG_IMX8)
+	struct udevice phy_dev;
+	struct ehci_mx6_phy_data phy_data;
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+	struct power_domain phy_pd;
+#endif
+#if CONFIG_IS_ENABLED(CLK)
+	struct clk phy_clk;
+#endif
 #endif
 };
 
@@ -468,18 +261,16 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev)
 	struct ehci_mx6_priv_data *priv = dev->priv;
 	enum usb_init_type type = priv->init_type;
 	struct usb_ehci *ehci = priv->ehci;
+	int ret;
 
-#if !defined(CONFIG_PHY)
-	usb_power_config_mx6(priv->anatop_addr, priv->portnr);
-	usb_power_config_mx7(priv->misc_addr);
-	usb_power_config_mx7ulp(priv->phy_addr);
-
-	usb_oc_config(priv->misc_addr, priv->portnr);
+	ret = board_usb_init(priv->portnr, priv->init_type);
+	if (ret) {
+		printf("Failed to initialize board for USB\n");
+		return ret;
+	}
 
-#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
-	usb_internal_phy_clock_gate(priv->phy_addr, 1);
-	usb_phy_enable(ehci, priv->phy_addr);
-#endif
+#if !CONFIG_IS_ENABLED(PHY) || defined(CONFIG_IMX8)
+	ehci_mx6_phy_init(ehci, &priv->phy_data, priv->portnr);
 #endif
 
 #if CONFIG_IS_ENABLED(DM_REGULATOR)
@@ -495,6 +286,10 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev)
 	}
 #endif
 
+	if (is_mx6dqp() || is_mx6dq() || is_mx6sdl() ||
+		((is_mx6sl() || is_mx6sx()) && type == USB_INIT_HOST))
+		setbits_le32(&ehci->usbmode, SDIS);
+
 	if (type == USB_INIT_DEVICE)
 		return 0;
 
@@ -508,31 +303,44 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev)
 }
 
 static const struct ehci_ops mx6_ehci_ops = {
-	.init_after_reset = mx6_init_after_reset
+	.powerup_fixup		= ehci_mx6_powerup_fixup,
+	.init_after_reset 	= mx6_init_after_reset
 };
 
+/**
+ * board_ehci_usb_phy_mode - override usb phy mode
+ * @port:	usb host/otg port
+ *
+ * Target board specific, override usb_phy_mode.
+ * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
+ * left disconnected in this case usb_phy_mode will not be able to identify
+ * the phy mode that usb port is used.
+ * Machine file overrides board_usb_phy_mode.
+ * When the extcon property is set in DTB, machine must provide this function, otherwise
+ * it will default return HOST.
+ *
+ * Return: USB_INIT_DEVICE or USB_INIT_HOST
+ */
+int __weak board_ehci_usb_phy_mode(struct udevice *dev)
+{
+	return USB_INIT_HOST;
+}
+
 static int ehci_usb_phy_mode(struct udevice *dev)
 {
-	struct usb_plat *plat = dev_get_plat(dev);
-	void *__iomem addr = dev_read_addr_ptr(dev);
+	struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
+	void *__iomem addr = (void *__iomem)devfdt_get_addr(dev);
 	void *__iomem phy_ctrl, *__iomem phy_status;
 	const void *blob = gd->fdt_blob;
-	int offset = dev_of_offset(dev), phy_off;
 	u32 val;
 
 	/*
 	 * About fsl,usbphy, Refer to
 	 * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
 	 */
-	if (is_mx6() || is_mx7ulp() || is_imxrt()) {
-		phy_off = fdtdec_lookup_phandle(blob,
-						offset,
-						"fsl,usbphy");
-		if (phy_off < 0)
-			return -EINVAL;
-
-		addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
-						       "reg");
+	if (is_mx6() || is_mx7ulp() || is_imxrt() || is_imx8() || is_imx8ulp()) {
+		addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent(blob, priv->phy_node_off,
+						       "reg", 0, NULL, false);
 		if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
 			return -EINVAL;
 
@@ -540,18 +348,18 @@ static int ehci_usb_phy_mode(struct udevice *dev)
 		val = readl(phy_ctrl);
 
 		if (val & USBPHY_CTRL_OTG_ID)
-			plat->init_type = USB_INIT_DEVICE;
+			priv->init_type = USB_INIT_DEVICE;
 		else
-			plat->init_type = USB_INIT_HOST;
-	} else if (is_mx7() || is_imx8mm() || is_imx8mn()) {
+			priv->init_type = USB_INIT_HOST;
+	} else if (is_mx7() || is_imx8mm() || is_imx8mn() || is_imx93()) {
 		phy_status = (void __iomem *)(addr +
 					      USBNC_PHY_STATUS_OFFSET);
 		val = readl(phy_status);
 
 		if (val & USBNC_PHYSTATUS_ID_DIG)
-			plat->init_type = USB_INIT_DEVICE;
+			priv->init_type = USB_INIT_DEVICE;
 		else
-			plat->init_type = USB_INIT_HOST;
+			priv->init_type = USB_INIT_HOST;
 	} else {
 		return -EINVAL;
 	}
@@ -562,32 +370,46 @@ static int ehci_usb_phy_mode(struct udevice *dev)
 static int ehci_usb_of_to_plat(struct udevice *dev)
 {
 	struct usb_plat *plat = dev_get_plat(dev);
+	struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
 	enum usb_dr_mode dr_mode;
+	const struct fdt_property *extcon;
+
+	extcon = fdt_get_property(gd->fdt_blob, dev_of_offset(dev),
+			"extcon", NULL);
+	if (extcon) {
+		priv->init_type = board_ehci_usb_phy_mode(dev);
+		goto check_type;
+	}
 
 	dr_mode = usb_get_dr_mode(dev_ofnode(dev));
 
 	switch (dr_mode) {
 	case USB_DR_MODE_HOST:
-		plat->init_type = USB_INIT_HOST;
+		priv->init_type = USB_INIT_HOST;
 		break;
 	case USB_DR_MODE_PERIPHERAL:
-		plat->init_type = USB_INIT_DEVICE;
+		priv->init_type = USB_INIT_DEVICE;
 		break;
 	default:
-		plat->init_type = USB_INIT_UNKNOWN;
+		priv->init_type = USB_INIT_UNKNOWN;
 	};
 
+check_type:
+	if (priv->init_type != USB_INIT_UNKNOWN && priv->init_type != plat->init_type) {
+		debug("Request USB type is %u, board forced type is %u\n",
+			plat->init_type, priv->init_type);
+		return -ENODEV;
+	}
+
 	return 0;
 }
 
 static int mx6_parse_dt_addrs(struct udevice *dev)
 {
-#if !defined(CONFIG_PHY)
 	struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
 	int phy_off, misc_off;
 	const void *blob = gd->fdt_blob;
 	int offset = dev_of_offset(dev);
-	void *__iomem addr;
 
 	phy_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbphy");
 	if (phy_off < 0) {
@@ -600,42 +422,102 @@ static int mx6_parse_dt_addrs(struct udevice *dev)
 	if (misc_off < 0)
 		return -EINVAL;
 
-	addr = (void __iomem *)fdtdec_get_addr(blob, phy_off, "reg");
+	priv->portnr = dev_seq(dev);
+	priv->phy_node_off = phy_off;
+
+#if !CONFIG_IS_ENABLED(PHY) || defined(CONFIG_IMX8)
+	void *__iomem addr;
+	struct ehci_mx6_phy_data *phy_data = &priv->phy_data;
+	addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent(blob, phy_off, "reg", 0, NULL, false);
 	if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
 		addr = NULL;
 
-	priv->phy_addr = addr;
+	phy_data->phy_addr = addr;
 
-	addr = (void __iomem *)fdtdec_get_addr(blob, misc_off, "reg");
+	addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent(blob, misc_off, "reg", 0, NULL, false);
 	if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
-	priv->misc_addr = addr;
+	phy_data->misc_addr = addr;
 
 #if defined(CONFIG_MX6)
-	int anatop_off, ret, devnump;
-
-	ret = fdtdec_get_alias_seq(blob, dev->uclass->uc_drv->name,
-				   phy_off, &devnump);
-	if (ret < 0)
-		return ret;
-	priv->portnr = devnump;
+	int anatop_off;
 
 	/* Resolve ANATOP offset through USB PHY node */
 	anatop_off = fdtdec_lookup_phandle(blob, phy_off, "fsl,anatop");
 	if (anatop_off < 0)
 		return -EINVAL;
 
-	addr = (void __iomem *)fdtdec_get_addr(blob, anatop_off, "reg");
+	addr = (void __iomem *)fdtdec_get_addr_size_auto_noparent(blob, anatop_off, "reg", 0, NULL, false);
 	if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
-	priv->anatop_addr = addr;
+	phy_data->anatop_addr = addr;
+#endif
+#endif
+	return 0;
+}
+
+#if !CONFIG_IS_ENABLED(PHY) || defined(CONFIG_IMX8)
+static int ehci_mx6_phy_prepare(struct ehci_mx6_priv_data *priv)
+{
+	dev_set_ofnode(&priv->phy_dev, offset_to_ofnode(priv->phy_node_off));
+
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+	/* Need to power on the PHY before access it */
+	if (!power_domain_get(&priv->phy_dev, &priv->phy_pd)) {
+		if (power_domain_on(&priv->phy_pd))
+			return -EINVAL;
+	}
 #endif
+
+#if CONFIG_IS_ENABLED(CLK)
+	int ret;
+
+	ret = clk_get_by_index(&priv->phy_dev, 0, &priv->phy_clk);
+	if (ret) {
+		printf("Failed to get phy_clk\n");
+		return ret;
+	}
+
+	ret = clk_enable(&priv->phy_clk);
+	if (ret) {
+		printf("Failed to enable phy_clk\n");
+		return ret;
+	}
 #endif
+
 	return 0;
 }
 
+static int ehci_mx6_phy_remove(struct ehci_mx6_priv_data *priv)
+{
+	int ret = 0;
+
+#if CONFIG_IS_ENABLED(CLK)
+	if (priv->phy_clk.dev) {
+		ret = clk_disable(&priv->phy_clk);
+		if (ret)
+			return ret;
+
+		ret = clk_free(&priv->phy_clk);
+		if (ret)
+			return ret;
+	}
+#endif
+
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+	if (priv->phy_pd.dev) {
+		ret = power_domain_off(&priv->phy_pd);
+		if (ret)
+			printf("Power down USB PHY failed! (error = %d)\n", ret);
+	}
+#endif
+
+	return ret;
+}
+#endif
+
 static int ehci_usb_probe(struct udevice *dev)
 {
 	struct usb_plat *plat = dev_get_plat(dev);
@@ -659,9 +541,23 @@ static int ehci_usb_probe(struct udevice *dev)
 		return ret;
 
 	priv->ehci = ehci;
-	priv->init_type = type;
 	priv->phy_type = usb_get_phy_mode(dev_ofnode(dev));
 
+	/* Init usb board level according to the requested init type */
+	ret = board_usb_init(priv->portnr, type);
+	if (ret) {
+		printf("Failed to initialize board for USB\n");
+		return ret;
+	}
+
+#if !CONFIG_IS_ENABLED(PHY) || defined(CONFIG_IMX8)
+	ret = ehci_mx6_phy_prepare(priv);
+	if (ret) {
+		printf("Failed to prepare USB phy\n");
+		return ret;
+	}
+#endif
+
 #if CONFIG_IS_ENABLED(CLK)
 	ret = clk_get_by_index(dev, 0, &priv->clk);
 	if (ret < 0)
@@ -676,20 +572,6 @@ static int ehci_usb_probe(struct udevice *dev)
 	mdelay(1);
 #endif
 
-	/*
-	 * If the device tree didn't specify host or device,
-	 * the default is USB_INIT_UNKNOWN, so we need to check
-	 * the register. For imx8mm and imx8mn, the clocks need to be
-	 * running first, so we defer the check until they are.
-	 */
-	if (priv->init_type == USB_INIT_UNKNOWN) {
-		ret = ehci_usb_phy_mode(dev);
-		if (ret)
-			goto err_clk;
-		else
-			priv->init_type = plat->init_type;
-	}
-
 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 	ret = device_get_supply_regulator(dev, "vbus-supply",
 					  &priv->vbus_supply);
@@ -697,27 +579,33 @@ static int ehci_usb_probe(struct udevice *dev)
 		debug("%s: No vbus supply\n", dev->name);
 #endif
 
-#if !defined(CONFIG_PHY)
-	usb_power_config_mx6(priv->anatop_addr, priv->portnr);
-	usb_power_config_mx7(priv->misc_addr);
-	usb_power_config_mx7ulp(priv->phy_addr);
-
-	usb_oc_config(priv->misc_addr, priv->portnr);
-
-#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
-	usb_internal_phy_clock_gate(priv->phy_addr, 1);
-	usb_phy_enable(ehci, priv->phy_addr);
-#endif
+#if !CONFIG_IS_ENABLED(PHY) || defined(CONFIG_IMX8)
+	ehci_mx6_phy_init(ehci, &priv->phy_data, priv->portnr);
+#else
+	ret = ehci_setup_phy(dev, &priv->phy, priv->portnr);
+	if (ret)
+		goto err_clk;
 #endif
 
+	/* If the init_type is unknown due to it is not forced in DTB, we use USB ID to detect */
+	if (priv->init_type == USB_INIT_UNKNOWN) {
+		ret = ehci_usb_phy_mode(dev);
+		if (ret)
+			goto err_clk;
+		if (priv->init_type != type) {
+			ret = -ENODEV;
+			goto err_clk;
+		}
+	}
+
 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 	if (priv->vbus_supply) {
 		ret = regulator_set_enable(priv->vbus_supply,
-					   (type == USB_INIT_DEVICE) ?
+					   (priv->init_type == USB_INIT_DEVICE) ?
 					   false : true);
 		if (ret && ret != -ENOSYS) {
 			printf("Error enabling VBUS supply (ret=%i)\n", ret);
-			goto err_clk;
+			goto err_phy;
 		}
 	}
 #endif
@@ -730,48 +618,45 @@ static int ehci_usb_probe(struct udevice *dev)
 
 	mdelay(10);
 
-#if defined(CONFIG_PHY)
-	ret = ehci_setup_phy(dev, &priv->phy, 0);
-	if (ret)
-		goto err_regulator;
-#endif
-
 	hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
 	hcor = (struct ehci_hcor *)((uintptr_t)hccr +
 			HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
 
 	ret = ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
 	if (ret)
-		goto err_phy;
+		goto err_regulator;
 
 	return ret;
 
-err_phy:
-#if defined(CONFIG_PHY)
-	ehci_shutdown_phy(dev, &priv->phy);
+
 err_regulator:
-#endif
 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 	if (priv->vbus_supply)
 		regulator_set_enable(priv->vbus_supply, false);
 #endif
+err_phy:
+#if CONFIG_IS_ENABLED(PHY) && !defined(CONFIG_IMX8)
+	ehci_shutdown_phy(dev, &priv->phy);
+#endif
 err_clk:
 #if CONFIG_IS_ENABLED(CLK)
 	clk_disable(&priv->clk);
-#else
-	/* Compatibility with DM_USB and !CLK */
-	enable_usboh3_clk(0);
 #endif
+#if !CONFIG_IS_ENABLED(PHY) || defined(CONFIG_IMX8)
+	ehci_mx6_phy_remove(priv);
+#endif
+
 	return ret;
 }
 
 int ehci_usb_remove(struct udevice *dev)
 {
-	struct ehci_mx6_priv_data *priv __maybe_unused = dev_get_priv(dev);
+	struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
+	struct usb_plat *plat = dev_get_plat(dev);
 
 	ehci_deregister(dev);
 
-#if defined(CONFIG_PHY)
+#if CONFIG_IS_ENABLED(PHY) && !defined(CONFIG_IMX8)
 	ehci_shutdown_phy(dev, &priv->phy);
 #endif
 
@@ -784,7 +669,13 @@ int ehci_usb_remove(struct udevice *dev)
 	clk_disable(&priv->clk);
 #endif
 
-	return 0;
+#if !CONFIG_IS_ENABLED(PHY) || defined(CONFIG_IMX8)
+	ehci_mx6_phy_remove(priv);
+#endif
+
+	plat->init_type = 0; /* Clean the requested usb type to host mode */
+
+	return board_usb_cleanup(dev_seq(dev), priv->init_type);
 }
 
 static const struct udevice_id mx6_usb_ids[] = {
diff --git a/drivers/usb/host/xhci-imx8.c b/drivers/usb/host/xhci-imx8.c
new file mode 100644
index 00000000000..dbe6f23c803
--- /dev/null
+++ b/drivers/usb/host/xhci-imx8.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ * NXP i.MX8 USB HOST xHCI Controller (Cadence IP)
+ *
+ * Author: Peter Chen <peter.chen@nxp.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <generic-phy.h>
+#include <power-domain.h>
+#include <usb.h>
+#include <wait_bit.h>
+#include <dm/device-internal.h>
+#include <usb/xhci.h>
+#include <asm/arch/clock.h>
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Host registers */
+#define HCIVERSION_CAPLENGTH	0x10000
+#define USBSTS			0x10084
+
+/* None-core registers */
+#define USB3_CORE_CTRL1		0x00
+#define USB3_CORE_STATUS	0x0c
+#define USB3_SSPHY_STATUS	0x4c
+
+/* USB3_CORE_CTRL1 */
+#define ALL_SW_RESET		0xfc000000
+#define MODE_STRAP_MASK		0x7
+#define PHYAHB_SW_RESET		BIT(26)
+#define OC_DISABLE		BIT(9)
+#define HOST_MODE		BIT(1)
+#define OTG_MODE		BIT(0)
+
+/* USB3_CORE_STATUS */
+#define HOST_POWER_ON_READY	BIT(12)
+
+/* USBSTS */
+#define CONTROLLER_NOT_READY	BIT(11)
+
+/* USB3_SSPHY_STATUS */
+#define CLK_VLD	0xf0000000
+
+struct xhci_imx8_data {
+	void __iomem *usb3_ctrl_base;
+	void __iomem *usb3_core_base;
+	struct clk_bulk clks;
+	struct phy phy;
+};
+
+static struct xhci_imx8_data imx8_data;
+
+static int imx8_xhci_init(void)
+{
+	int ret;
+
+	writel(CLK_VLD, imx8_data.usb3_ctrl_base + USB3_SSPHY_STATUS);
+	ret = wait_for_bit_le32(imx8_data.usb3_ctrl_base + USB3_SSPHY_STATUS,
+				CLK_VLD, true, 100, false);
+	if (ret) {
+		printf("clkvld is incorrect\n");
+		return ret;
+	}
+
+	clrsetbits_le32(imx8_data.usb3_ctrl_base + USB3_CORE_CTRL1,
+			MODE_STRAP_MASK,  HOST_MODE | OC_DISABLE);
+	clrbits_le32(imx8_data.usb3_ctrl_base + USB3_CORE_CTRL1,
+		     PHYAHB_SW_RESET);
+	generic_phy_init(&imx8_data.phy);
+
+	/* clear all sw_rst */
+	clrbits_le32(imx8_data.usb3_ctrl_base + USB3_CORE_CTRL1, ALL_SW_RESET);
+
+	debug("wait xhci_power_on_ready\n");
+	ret = wait_for_bit_le32(imx8_data.usb3_ctrl_base + USB3_CORE_STATUS,
+				HOST_POWER_ON_READY, true, 100, false);
+	if (ret) {
+		printf("wait xhci_power_on_ready timeout\n");
+		return ret;
+	}
+	debug("xhci_power_on_ready\n");
+
+	debug("waiting CNR\n");
+	ret = wait_for_bit_le32(imx8_data.usb3_core_base + USBSTS,
+				CONTROLLER_NOT_READY, false, 100, false);
+	if (ret) {
+		printf("wait CNR timeout\n");
+		return ret;
+	}
+	debug("check CNR has finished\n");
+
+	return 0;
+}
+
+static void imx8_xhci_reset(void)
+{
+	/* Set CORE ctrl to default value, that all rst are hold */
+	writel(ALL_SW_RESET | OTG_MODE,
+	       imx8_data.usb3_ctrl_base + USB3_CORE_CTRL1);
+}
+
+static int xhci_imx8_clk_init(struct udevice *dev)
+{
+	int ret;
+
+	ret = clk_get_bulk(dev, &imx8_data.clks);
+	if (ret)
+		return ret;
+
+	ret = clk_enable_bulk(&imx8_data.clks);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static inline void xhci_imx8_get_reg_addr(struct udevice *dev)
+{
+	imx8_data.usb3_ctrl_base =
+			(void __iomem *)devfdt_get_addr_name(dev, "none-core");
+	imx8_data.usb3_core_base =
+			(void __iomem *)devfdt_get_addr_name(dev, "otg");
+
+}
+
+static int xhci_imx8_probe(struct udevice *dev)
+{
+	struct xhci_hccr *hccr;
+	struct xhci_hcor *hcor;
+	struct udevice usbotg_dev;
+	struct power_domain pd;
+	int usbotg_off;
+	int ret = 0;
+	int len;
+
+	usbotg_off = fdtdec_lookup_phandle(gd->fdt_blob,
+					   dev_of_offset(dev),
+					   "cdns3,usb");
+	if (usbotg_off < 0)
+		return -EINVAL;
+
+	dev_set_ofnode(&usbotg_dev, offset_to_ofnode(usbotg_off));
+	usbotg_dev.parent = dev->parent;
+	xhci_imx8_get_reg_addr(&usbotg_dev);
+
+#if CONFIG_IS_ENABLED(POWER_DOMAIN)
+	if (!power_domain_get(&usbotg_dev, &pd)) {
+		ret = power_domain_on(&pd);
+		if (ret)
+			return ret;
+	}
+#endif
+
+	ret = generic_phy_get_by_index(&usbotg_dev, 0, &imx8_data.phy);
+	if (ret && ret != -ENOENT) {
+		printf("Failed to get USB PHY for %s\n", dev->name);
+		return ret;
+	}
+
+	ret = board_usb_init(dev_seq(dev), USB_INIT_HOST);
+	if (ret != 0) {
+		printf("Failed to initialize board for USB\n");
+		return ret;
+	}
+
+#if CONFIG_IS_ENABLED(CLK)
+	xhci_imx8_clk_init(&usbotg_dev);
+#else
+	init_clk_usb3(dev_seq(dev));
+#endif
+
+	imx8_xhci_init();
+
+	hccr = (struct xhci_hccr *)(imx8_data.usb3_core_base +
+				    HCIVERSION_CAPLENGTH);
+	len = HC_LENGTH(xhci_readl(&hccr->cr_capbase));
+	hcor = (struct xhci_hcor *)((uintptr_t)hccr + len);
+	printf("XHCI-imx8 init hccr 0x%p and hcor 0x%p hc_length %d\n",
+	       (uint32_t *)hccr, (uint32_t *)hcor, len);
+
+	return xhci_register(dev, hccr, hcor);
+}
+
+static int xhci_imx8_remove(struct udevice *dev)
+{
+	int ret = xhci_deregister(dev);
+
+	if (!ret)
+		imx8_xhci_reset();
+
+#if CONFIG_IS_ENABLED(CLK)
+	clk_release_bulk(&imx8_data.clks);
+#endif
+	if (generic_phy_valid(&imx8_data.phy))
+		device_remove(imx8_data.phy.dev, DM_REMOVE_NORMAL);
+
+	board_usb_cleanup(dev_seq(dev), USB_INIT_HOST);
+
+	return ret;
+}
+
+static const struct udevice_id xhci_usb_ids[] = {
+	{ .compatible = "Cadence,usb3-host", },
+	{ }
+};
+
+U_BOOT_DRIVER(xhci_imx8) = {
+	.name	= "xhci_imx8",
+	.id	= UCLASS_USB,
+	.of_match = xhci_usb_ids,
+	.probe = xhci_imx8_probe,
+	.remove = xhci_imx8_remove,
+	.ops	= &xhci_usb_ops,
+	.plat_auto = sizeof(struct usb_plat),
+	.priv_auto = sizeof(struct xhci_ctrl),
+	.flags	= DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_OS_PREPARE,
+};
diff --git a/drivers/usb/host/xhci-imx8m.c b/drivers/usb/host/xhci-imx8m.c
new file mode 100644
index 00000000000..e2022994ee5
--- /dev/null
+++ b/drivers/usb/host/xhci-imx8m.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * FSL i.MX8M USB HOST xHCI Controller
+ *
+ * Author: Jun Li <jun.li@nxp.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <linux/errno.h>
+#include <linux/compat.h>
+#include <linux/usb/dwc3.h>
+#include <asm/arch/sys_proto.h>
+#include <dm.h>
+#include <usb/xhci.h>
+#include <clk.h>
+#include <generic-phy.h>
+#include <dwc3-uboot.h>
+
+/* Declare global data pointer */
+DECLARE_GLOBAL_DATA_PTR;
+
+struct xhci_imx8m_plat {
+	struct clk_bulk clks;
+	struct phy_bulk phys;
+};
+
+static void imx8m_xhci_set_suspend_clk(struct dwc3 *dwc3_reg)
+{
+	u32 reg;
+
+	/* Set suspend_clk to be 32KHz */
+	reg = readl(&dwc3_reg->g_ctl);
+	reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
+	reg |= DWC3_GCTL_PWRDNSCALE(2);
+
+	writel(reg, &dwc3_reg->g_ctl);
+}
+
+static int imx8m_xhci_core_init(struct dwc3 *dwc3_reg)
+{
+	int ret = 0;
+
+	ret = dwc3_core_init(dwc3_reg);
+	if (ret) {
+		debug("%s:failed to initialize core\n", __func__);
+		return ret;
+	}
+
+	imx8m_xhci_set_suspend_clk(dwc3_reg);
+
+	/* We are hard-coding DWC3 core to Host Mode */
+	dwc3_set_mode(dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
+
+	/* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
+	dwc3_set_fladj(dwc3_reg, GFLADJ_30MHZ_DEFAULT);
+
+	return ret;
+}
+
+static int xhci_imx8m_clk_init(struct udevice *dev,
+			      struct xhci_imx8m_plat *plat)
+{
+	int ret;
+
+	ret = clk_get_bulk(dev, &plat->clks);
+	if (ret == -ENOSYS || ret == -ENOENT)
+		return 0;
+	if (ret)
+		return ret;
+
+	ret = clk_enable_bulk(&plat->clks);
+	if (ret) {
+		clk_release_bulk(&plat->clks);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int xhci_imx8m_probe(struct udevice *dev)
+{
+	struct xhci_hccr *hccr;
+	struct xhci_hcor *hcor;
+	struct dwc3 *dwc3_reg;
+	struct xhci_imx8m_plat *plat = dev_get_plat(dev);
+	int ret = 0;
+
+	ret = xhci_imx8m_clk_init(dev, plat);
+	if (ret)
+		return ret;
+
+	ret = board_usb_init(dev_seq(dev), USB_INIT_HOST);
+	if (ret != 0) {
+		puts("Failed to initialize board for imx8m USB\n");
+		return ret;
+	}
+
+	hccr = (struct xhci_hccr *)((uintptr_t)dev_remap_addr(dev));
+	hcor = (struct xhci_hcor *)((uintptr_t)hccr +
+			HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
+
+	ret = dwc3_setup_phy(dev, &plat->phys);
+	if (ret && (ret != -ENOTSUPP))
+		return ret;
+
+	dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);
+
+	ret = imx8m_xhci_core_init(dwc3_reg);
+	if (ret < 0) {
+		puts("Failed to initialize imx8m xhci\n");
+		return ret;
+	}
+
+	debug("imx8m-xhci: init hccr %lx and hcor %lx hc_length %lx\n",
+	      (uintptr_t)hccr, (uintptr_t)hcor,
+	      (uintptr_t)HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
+
+	return xhci_register(dev, hccr, hcor);
+}
+
+static int xhci_imx8m_remove(struct udevice *dev)
+{
+	int ret;
+	struct xhci_imx8m_plat *plat = dev_get_plat(dev);
+
+	dwc3_shutdown_phy(dev, &plat->phys);
+
+	clk_release_bulk(&plat->clks);
+
+	ret = xhci_deregister(dev);
+
+	board_usb_cleanup(dev_seq(dev), USB_INIT_HOST);
+
+	return ret;
+}
+
+static const struct udevice_id xhci_usb_ids[] = {
+	{ .compatible = "fsl,imx8mq-dwc3", },
+	{ }
+};
+
+U_BOOT_DRIVER(xhci_imx8m) = {
+	.name	= "xhci_imx8m",
+	.id	= UCLASS_USB,
+	.of_match = xhci_usb_ids,
+	.probe = xhci_imx8m_probe,
+	.remove = xhci_imx8m_remove,
+	.ops	= &xhci_usb_ops,
+	.plat_auto = sizeof(struct xhci_imx8m_plat),
+	.priv_auto = sizeof(struct xhci_ctrl),
+	.flags	= DM_FLAG_ALLOC_PRIV_DMA,
+};
+
+static const struct udevice_id xhci_imx8mp_ids[] = {
+	{ .compatible = "fsl,imx8mp-dwc3", },
+	{ }
+};
+
+U_BOOT_DRIVER(xhci_imx8mp_misc) = {
+	.name	= "xhci_imx8mp_misc",
+	.id	= UCLASS_MISC,
+	.of_match = of_match_ptr(xhci_imx8mp_ids),
+};
diff --git a/drivers/usb/imx/Makefile b/drivers/usb/imx/Makefile
new file mode 100644
index 00000000000..30c06b7bf83
--- /dev/null
+++ b/drivers/usb/imx/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2019 NXP
+#
+
+obj-$(CONFIG_USB_EHCI_MX6) += usb-mx6-common.o
+obj-$(CONFIG_USB_EHCI_MX7) += usb-mx6-common.o
+obj-$(CONFIG_CI_UDC) += usb-mx6-common.o
diff --git a/drivers/usb/imx/usb-mx6-common.c b/drivers/usb/imx/usb-mx6-common.c
new file mode 100644
index 00000000000..8a2b4e5353e
--- /dev/null
+++ b/drivers/usb/imx/usb-mx6-common.c
@@ -0,0 +1,345 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
+ *
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <errno.h>
+#include <wait_bit.h>
+#include <linux/compiler.h>
+#include <usb/ehci-ci.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/regs-usbphy.h>
+#include <asm/mach-imx/sys_proto.h>
+#include <asm/mach-types.h>
+#include <asm/arch/sys_proto.h>
+#include <usb/usb_mx6_common.h>
+
+#define ANADIG_USB2_CHRG_DETECT_EN_B		0x00100000
+#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B	0x00080000
+
+#define ANADIG_USB2_PLL_480_CTRL_BYPASS		0x00010000
+#define ANADIG_USB2_PLL_480_CTRL_ENABLE		0x00002000
+#define ANADIG_USB2_PLL_480_CTRL_POWER		0x00001000
+#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS	0x00000040
+
+#define USBNC_OFFSET		0x200
+#define USBNC_PHYCFG2_ACAENB	(1 << 4) /* otg_id detection enable */
+#define UCTRL_PWR_POL		(1 << 9) /* OTG Polarity of Power Pin */
+#define UCTRL_OVER_CUR_POL	(1 << 8) /* OTG Polarity of Overcurrent */
+#define UCTRL_OVER_CUR_DIS	(1 << 7) /* Disable OTG Overcurrent Detection */
+
+#define PLL_USB_EN_USB_CLKS_MASK	(0x01 << 6)
+#define PLL_USB_PWR_MASK		(0x01 << 12)
+#define PLL_USB_ENABLE_MASK		(0x01 << 13)
+#define PLL_USB_BYPASS_MASK		(0x01 << 16)
+#define PLL_USB_REG_ENABLE_MASK		(0x01 << 21)
+#define PLL_USB_DIV_SEL_MASK		(0x07 << 22)
+#define PLL_USB_LOCK_MASK		(0x01 << 31)
+
+/* USBCMD */
+#define UCMD_RUN_STOP           (1 << 0) /* controller run/stop */
+#define UCMD_RESET		(1 << 1) /* controller reset */
+
+/* Base address for this IP block is 0x02184800 */
+struct usbnc_regs {
+	u32 ctrl[4]; /* otg/host1-3 */
+	u32 uh2_hsic_ctrl;
+	u32 uh3_hsic_ctrl;
+	u32 otg_phy_ctrl_0;
+	u32 uh1_phy_ctrl_0;
+	u32 reserve1[4];
+	u32 phy_cfg1;
+	u32 phy_cfg2;
+	u32 reserve2;
+	u32 phy_status;
+	u32 reserve3[4];
+	u32 adp_cfg1;
+	u32 adp_cfg2;
+	u32 adp_status;
+};
+
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8ULP)
+static const ulong phy_bases[] = {
+	USB_PHY0_BASE_ADDR,
+#if defined(USB_PHY1_BASE_ADDR)
+	USB_PHY1_BASE_ADDR,
+#endif
+};
+
+int usb_phy_mode(int port)
+{
+	void __iomem *phy_reg;
+	void __iomem *phy_ctrl;
+	u32 val;
+
+	phy_reg = (void __iomem *)phy_bases[port];
+	phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+
+	val = readl(phy_ctrl);
+
+	if (val & USBPHY_CTRL_OTG_ID)
+		return USB_INIT_DEVICE;
+	else
+		return USB_INIT_HOST;
+}
+
+static void usb_internal_phy_clock_gate(void __iomem *phy_reg, int on)
+{
+	if (phy_reg == NULL)
+		return;
+
+	phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
+	writel(USBPHY_CTRL_CLKGATE, phy_reg);
+}
+
+/* Return 0 : host node, <>0 : device mode */
+static int usb_phy_enable(struct usb_ehci *ehci, void __iomem *phy_reg)
+{
+	void __iomem *phy_ctrl;
+	void __iomem *usb_cmd;
+	int ret;
+
+	if (phy_reg == NULL)
+		return -EINVAL;
+
+	phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+	usb_cmd = (void __iomem *)&ehci->usbcmd;
+
+	/* Stop then Reset */
+	clrbits_le32(usb_cmd, UCMD_RUN_STOP);
+	ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
+	if (ret)
+		return ret;
+
+	setbits_le32(usb_cmd, UCMD_RESET);
+	ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
+	if (ret)
+		return ret;
+
+	/* Reset USBPHY module */
+	setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
+	udelay(10);
+
+	/* Remove CLKGATE and SFTRST */
+	clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
+	udelay(10);
+
+	/* Power up the PHY */
+	writel(0, phy_reg + USBPHY_PWD);
+	/* enable FS/LS device */
+	setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
+			USBPHY_CTRL_ENUTMILEVEL3);
+
+	return 0;
+}
+#elif defined(CONFIG_USB_EHCI_MX7)
+int usb_phy_mode(int port)
+{
+	struct usbnc_regs *usbnc = (struct usbnc_regs *)(ulong)(USB_BASE_ADDR +
+			(0x10000 * port) + USBNC_OFFSET);
+	void __iomem *status = (void __iomem *)(&usbnc->phy_status);
+	u32 val;
+
+	val = readl(status);
+
+	if (val & USBNC_PHYSTATUS_ID_DIG)
+		return USB_INIT_DEVICE;
+	else
+		return USB_INIT_HOST;
+}
+#endif
+
+#if defined(CONFIG_MX6) && !CONFIG_IS_ENABLED(PHY)
+static void usb_power_config_mx6(void __iomem *anatop_base,
+				 int anatop_bits_index)
+{
+	struct anatop_regs __iomem *anatop = (struct anatop_regs __iomem *)anatop_base;
+	void __iomem *chrg_detect;
+	void __iomem *pll_480_ctrl_clr;
+	void __iomem *pll_480_ctrl_set;
+
+	if (!is_mx6())
+		return;
+
+	switch (anatop_bits_index) {
+	case 0:
+		chrg_detect = &anatop->usb1_chrg_detect;
+		pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
+		pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
+		break;
+	case 1:
+		chrg_detect = &anatop->usb2_chrg_detect;
+		pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
+		pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
+		break;
+	default:
+		return;
+	}
+	/*
+	 * Some phy and power's special controls
+	 * 1. The external charger detector needs to be disabled
+	 * or the signal at DP will be poor
+	 * 2. The PLL's power and output to usb
+	 * is totally controlled by IC, so the Software only needs
+	 * to enable them at initializtion.
+	 */
+	writel(ANADIG_USB2_CHRG_DETECT_EN_B |
+		     ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
+		     chrg_detect);
+
+	writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
+		     pll_480_ctrl_clr);
+
+	writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
+		     ANADIG_USB2_PLL_480_CTRL_POWER |
+		     ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
+		     pll_480_ctrl_set);
+}
+#else
+static void __maybe_unused
+usb_power_config_mx6(void __iomem *anatop_base, int anatop_bits_index) { }
+#endif
+
+#if defined(CONFIG_USB_EHCI_MX7) && !CONFIG_IS_ENABLED(PHY)
+static void usb_power_config_mx7(void __iomem *usbnc_base)
+{
+	struct usbnc_regs __iomem *usbnc = (struct usbnc_regs __iomem *)usbnc_base;
+	void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
+
+	if (!is_mx7())
+		return;
+
+	/*
+	 * Clear the ACAENB to enable usb_otg_id detection,
+	 * otherwise it is the ACA detection enabled.
+	 */
+	clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
+}
+#else
+static void __maybe_unused
+usb_power_config_mx7(void __iomem *usbnc_base) { }
+#endif
+
+#if (defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8ULP)) && !CONFIG_IS_ENABLED(PHY)
+static void usb_power_config_mx7ulp(void __iomem *usbphy_base)
+{
+	struct usbphy_regs __iomem *usbphy = (struct usbphy_regs __iomem *)usbphy_base;
+
+	if (!(is_mx7ulp() || is_imx8ulp()))
+		return;
+
+	enable_usb_pll((ulong)usbphy);
+}
+#else
+static void __maybe_unused
+usb_power_config_mx7ulp(void __iomem *usbphy_base) { }
+#endif
+
+#if defined(CONFIG_IMX8)
+static void usb_power_config_imx8(void __iomem *usbphy_base)
+{
+	struct usbphy_regs __iomem *usbphy = (struct usbphy_regs __iomem *)usbphy_base;
+
+	if (!is_imx8())
+		return;
+
+	int timeout = 1000000;
+
+	if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) {
+
+		/* Enable the regulator first */
+		writel(PLL_USB_REG_ENABLE_MASK,
+		       &usbphy->usb1_pll_480_ctrl_set);
+
+		/* Wait at least 25us */
+		udelay(25);
+
+		/* Enable the power */
+		writel(PLL_USB_PWR_MASK, &usbphy->usb1_pll_480_ctrl_set);
+
+		/* Wait lock */
+		while (timeout--) {
+			if (readl(&usbphy->usb1_pll_480_ctrl) &
+			    PLL_USB_LOCK_MASK)
+				break;
+			udelay(10);
+		}
+
+		if (timeout <= 0) {
+			/* If timeout, we power down the pll */
+			writel(PLL_USB_PWR_MASK,
+			       &usbphy->usb1_pll_480_ctrl_clr);
+			return;
+		}
+	}
+
+	/* Clear the bypass */
+	writel(PLL_USB_BYPASS_MASK, &usbphy->usb1_pll_480_ctrl_clr);
+
+	/* Enable the PLL clock out to USB */
+	writel((PLL_USB_EN_USB_CLKS_MASK | PLL_USB_ENABLE_MASK),
+	       &usbphy->usb1_pll_480_ctrl_set);
+}
+#else
+static void __maybe_unused
+usb_power_config_imx8(void __iomem *usbphy_base) { }
+#endif
+
+
+/* Should be done in the MXS PHY driver */
+static void usb_oc_config(void __iomem *usbnc_base, int index)
+{
+	struct usbnc_regs __iomem *usbnc = (struct usbnc_regs __iomem *)usbnc_base;
+#if defined(CONFIG_MX6)
+	void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
+#elif defined(CONFIG_USB_EHCI_MX7) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8ULP)
+	void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[0]);
+#endif
+
+#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
+	/* mx6qarm2 seems to required a different setting*/
+	clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
+#else
+	setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
+#endif
+
+	setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
+
+	/* Set power polarity to high active */
+#ifdef CONFIG_MXC_USB_OTG_HACTIVE
+	setbits_le32(ctrl, UCTRL_PWR_POL);
+#else
+	clrbits_le32(ctrl, UCTRL_PWR_POL);
+#endif
+}
+
+void ehci_mx6_phy_init(struct usb_ehci *ehci, struct ehci_mx6_phy_data *phy_data, int index)
+{
+	u32 portsc;
+
+	portsc = readl(&ehci->portsc);
+	if (portsc & PORT_PTS_PHCD) {
+		debug("suspended: portsc %x, enabled it.\n", portsc);
+		clrbits_le32(&ehci->portsc, PORT_PTS_PHCD);
+	}
+
+	usb_power_config_mx6(phy_data->anatop_addr, index);
+	usb_power_config_mx7(phy_data->misc_addr);
+	usb_power_config_mx7ulp(phy_data->phy_addr);
+	usb_power_config_imx8(phy_data->phy_addr);
+
+	usb_oc_config(phy_data->misc_addr, index);
+
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8ULP)
+	usb_internal_phy_clock_gate(phy_data->phy_addr, 1);
+	usb_phy_enable(ehci, phy_data->phy_addr);
+#endif
+}
diff --git a/drivers/usb/musb-new/ti-musb.c b/drivers/usb/musb-new/ti-musb.c
index 91042935b07..d90e5bfaac8 100644
--- a/drivers/usb/musb-new/ti-musb.c
+++ b/drivers/usb/musb-new/ti-musb.c
@@ -233,7 +233,7 @@ static int ti_musb_peripheral_of_to_plat(struct udevice *dev)
 }
 #endif
 
-int dm_usb_gadget_handle_interrupts(struct udevice *dev)
+static int ti_musb_peripheral_handle_interrupts(struct udevice *dev)
 {
 	struct ti_musb_peripheral *priv = dev_get_priv(dev);
 
@@ -278,6 +278,7 @@ U_BOOT_DRIVER(ti_musb_peripheral) = {
 	.probe = ti_musb_peripheral_probe,
 	.remove = ti_musb_peripheral_remove,
 	.ops	= &musb_usb_ops,
+	.handle_interrupts = ti_musb_peripheral_handle_interrupts,
 	.plat_auto	= sizeof(struct ti_musb_plat),
 	.priv_auto	= sizeof(struct ti_musb_peripheral),
 	.flags = DM_FLAG_PRE_RELOC,
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index ff8e11f6489..9c9cc524f3f 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -437,6 +437,24 @@ config VIDEO_LCD_RAYDIUM_RM68200
 	Say Y here if you want to enable support for Raydium RM68200
 	720x1280 DSI video mode panel.
 
+config VIDEO_LCD_RAYDIUM_RM67191
+	bool "RM67191 DSI LCD panel support"
+	depends on DM_VIDEO
+	select VIDEO_MIPI_DSI
+	default n
+	help
+	Say Y here if you want to enable support for Raydium RM68200
+	1080x1920 DSI video mode panel.
+
+config VIDEO_LCD_ROCKTECH_HIMAX8394F
+	bool "Rocktech Himax8394f 720x1280 DSI video mode panel"
+	depends on DM_VIDEO
+	select VIDEO_MIPI_DSI
+	default n
+	help
+	Say Y here if you want to enable support for Rocktech Himax8394f
+	720*1280 DSI video mode panel.
+
 config VIDEO_LCD_SSD2828
 	bool "SSD2828 bridge chip"
 	---help---
@@ -657,7 +675,7 @@ config VIDEO_TEGRA124
 
 source "drivers/video/bridge/Kconfig"
 
-source "drivers/video/imx/Kconfig"
+source "drivers/video/nxp/Kconfig"
 
 config VIDEO_MXS
 	bool "Enable video support on i.MX28/i.MX6UL/i.MX7 SoCs"
@@ -691,6 +709,18 @@ config VIDEO
 	  model. Video drivers typically provide a colour text console and
 	  cursor.
 
+config MXC_EPDC
+	bool "i.MX EPDC support"
+	depends on LCD && (MX7 || MX6)
+	help
+	  This enable the E-ink EPD panel controller support for i.MX processors
+
+config WAVEFORM_BUF_SIZE
+	bool "The buffer size allocated for i.MX EPDC waveform file"
+	depends on MXC_EPDC
+	help
+	  Set the buffer size for loading waveform file.
+
 config CFB_CONSOLE
 	bool "Enable colour frame buffer console"
 	depends on VIDEO || ARCH_OMAP2PLUS
@@ -1017,4 +1047,29 @@ config VIDEO_VCXK
 	  This enables VCXK driver which can be used with VC2K, VC4K
 	  and VC8K devices on various boards from BuS Elektronik GmbH.
 
+config VIDEO_LINK
+	bool "Enable video link framework support"
+	depends on DM_VIDEO
+	help
+	   This option enables a video link framework basing on port-endpoint graph
+	   to connect video components.
+
+config VIDEO_IT6263_BRIDGE
+	bool "ITE6263 LVDS to HDMI connector"
+	depends on DM_VIDEO
+	select VIDEO_BRIDGE
+	default n
+	help
+	Say Y here if you want to enable support for ITE IT6263
+	LVDS to HDMI connector, currently only support 1280x720P.
+
+config VIDEO_ADV7535
+	bool "ADV7535 MIPI DSI to HDMI connector"
+	depends on DM_VIDEO
+	select VIDEO_MIPI_DSI
+	default n
+	help
+	Say Y here if you want to enable support for ADI ADV7535
+	DSI to HDMI connector, currently only support 1920x1080.
+
 endmenu
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 4038395b128..5347ba52a80 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_SIMPLE_PANEL) += simple_panel.o
 
 obj-$(CONFIG_VIDEO_LOGO) += u_boot_logo.o
 
+obj-$(CONFIG_VIDEO_LINK) += video_link.o
 endif
 
 obj-${CONFIG_EXYNOS_FB} += exynos/
@@ -52,17 +53,20 @@ obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
 obj-$(CONFIG_VIDEO_DW_MIPI_DSI) += dw_mipi_dsi.o
 obj-$(CONFIG_VIDEO_EFI) += efi.o
 obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
-obj-$(CONFIG_VIDEO_IPUV3) += imx/
 obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
 obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
 obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
+obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM67191) += raydium-rm67191.o
+obj-$(CONFIG_VIDEO_LCD_ROCKTECH_HIMAX8394F) += rocktech-hx8394f.o
 obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
 obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o
 obj-$(CONFIG_VIDEO_MCDE_SIMPLE) += mcde_simple.o
+obj-$(CONFIG_VIDEO_ADV7535) += adv7535.o
 obj-${CONFIG_VIDEO_MESON} += meson/
 obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_dsi.o
+obj-$(CONFIG_VIDEO_IT6263_BRIDGE) += it6263_bridge.o
 obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o
 obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
 obj-$(CONFIG_VIDEO_NX) += nexell_display.o videomodes.o nexell/
@@ -74,6 +78,12 @@ obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o
 obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
 obj-$(CONFIG_VIDEO_VESA) += vesa.o
 obj-$(CONFIG_VIDEO_SEPS525) += seps525.o
+obj-$(CONFIG_MXC_EPDC) += mxc_epdc_fb.o
+obj-$(CONFIG_VIDEO_VADC) += mxc_vadc.o
+obj-$(CONFIG_VIDEO_CSI) += mxc_csi.o
+obj-$(CONFIG_VIDEO_PXP) += mxc_pxp.o
+obj-$(CONFIG_VIDEO_GIS) += mxc_gis.o
 
 obj-y += bridge/
 obj-y += sunxi/
+obj-y += nxp/
diff --git a/drivers/video/adv7535.c b/drivers/video/adv7535.c
new file mode 100644
index 00000000000..80f9c6ee19d
--- /dev/null
+++ b/drivers/video/adv7535.c
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <mipi_dsi.h>
+#include <panel.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <linux/err.h>
+
+struct adv7535_priv {
+	unsigned int addr;
+	unsigned int addr_cec;
+	unsigned int lanes;
+	enum mipi_dsi_pixel_format format;
+	unsigned long mode_flags;
+	struct udevice *cec_dev;
+};
+
+static const struct display_timing default_timing = {
+	.pixelclock.typ		= 148500000,
+	.hactive.typ		= 1920,
+	.hfront_porch.typ	= 88,
+	.hback_porch.typ	= 148,
+	.hsync_len.typ		= 44,
+	.vactive.typ		= 1080,
+	.vfront_porch.typ	= 4,
+	.vback_porch.typ	= 36,
+	.vsync_len.typ		= 5,
+};
+
+static int adv7535_i2c_reg_write(struct udevice *dev, uint addr, uint mask, uint data)
+{
+	uint8_t valb;
+	int err;
+
+	if (mask != 0xff) {
+		err = dm_i2c_read(dev, addr, &valb, 1);
+		if (err)
+			return err;
+
+		valb &= ~mask;
+		valb |= data;
+	} else {
+		valb = data;
+	}
+
+	err = dm_i2c_write(dev, addr, &valb, 1);
+	return err;
+}
+
+static int adv7535_i2c_reg_read(struct udevice *dev, uint8_t addr, uint8_t *data)
+{
+	uint8_t valb;
+	int err;
+
+	err = dm_i2c_read(dev, addr, &valb, 1);
+	if (err)
+		return err;
+
+	*data = (int)valb;
+	return 0;
+}
+
+static int adv7535_enable(struct udevice *dev)
+{
+	struct adv7535_priv *priv = dev_get_priv(dev);
+	uint8_t val;
+
+	adv7535_i2c_reg_read(dev, 0x00, &val);
+	debug("Chip revision: 0x%x (expected: 0x14)\n", val);
+	adv7535_i2c_reg_read(priv->cec_dev, 0x00, &val);
+	debug("Chip ID MSB: 0x%x (expected: 0x75)\n", val);
+	adv7535_i2c_reg_read(priv->cec_dev, 0x01, &val);
+	debug("Chip ID LSB: 0x%x (expected: 0x33)\n", val);
+
+	/* Power */
+	adv7535_i2c_reg_write(dev, 0x41, 0xff, 0x10);
+	/* Initialisation (Fixed) Registers */
+	adv7535_i2c_reg_write(dev, 0x16, 0xff, 0x20);
+	adv7535_i2c_reg_write(dev, 0x9A, 0xff, 0xE0);
+	adv7535_i2c_reg_write(dev, 0xBA, 0xff, 0x70);
+	adv7535_i2c_reg_write(dev, 0xDE, 0xff, 0x82);
+	adv7535_i2c_reg_write(dev, 0xE4, 0xff, 0x40);
+	adv7535_i2c_reg_write(dev, 0xE5, 0xff, 0x80);
+	adv7535_i2c_reg_write(priv->cec_dev, 0x15, 0xff, 0xD0);
+	adv7535_i2c_reg_write(priv->cec_dev, 0x17, 0xff, 0xD0);
+	adv7535_i2c_reg_write(priv->cec_dev, 0x24, 0xff, 0x20);
+	adv7535_i2c_reg_write(priv->cec_dev, 0x57, 0xff, 0x11);
+	adv7535_i2c_reg_write(priv->cec_dev, 0x05, 0xff, 0xc8);
+
+	/* 4 x DSI Lanes */
+	adv7535_i2c_reg_write(priv->cec_dev, 0x1C, 0xff, 0x40);
+
+	/* DSI Pixel Clock Divider */
+	//adv7535_i2c_reg_write(priv->cec_dev, 0x16, 0xff, 0x0);
+	adv7535_i2c_reg_write(priv->cec_dev, 0x16, 0xff, 0x18);
+
+	/* Enable Internal Timing Generator */
+	adv7535_i2c_reg_write(priv->cec_dev, 0x27, 0xff, 0xCB);
+	/* 1920 x 1080p 60Hz */
+	adv7535_i2c_reg_write(priv->cec_dev, 0x28, 0xff, 0x89); /* total width */
+	adv7535_i2c_reg_write(priv->cec_dev, 0x29, 0xff, 0x80); /* total width */
+	adv7535_i2c_reg_write(priv->cec_dev, 0x2A, 0xff, 0x02); /* hsync */
+	adv7535_i2c_reg_write(priv->cec_dev, 0x2B, 0xff, 0xC0); /* hsync */
+	adv7535_i2c_reg_write(priv->cec_dev, 0x2C, 0xff, 0x05); /* hfp */
+	adv7535_i2c_reg_write(priv->cec_dev, 0x2D, 0xff, 0x80); /* hfp */
+	adv7535_i2c_reg_write(priv->cec_dev, 0x2E, 0xff, 0x09); /* hbp */
+	adv7535_i2c_reg_write(priv->cec_dev, 0x2F, 0xff, 0x40); /* hbp */
+
+	adv7535_i2c_reg_write(priv->cec_dev, 0x30, 0xff, 0x46); /* total height */
+	adv7535_i2c_reg_write(priv->cec_dev, 0x31, 0xff, 0x50); /* total height */
+	adv7535_i2c_reg_write(priv->cec_dev, 0x32, 0xff, 0x00); /* vsync */
+	adv7535_i2c_reg_write(priv->cec_dev, 0x33, 0xff, 0x50); /* vsync */
+	adv7535_i2c_reg_write(priv->cec_dev, 0x34, 0xff, 0x00); /* vfp */
+	adv7535_i2c_reg_write(priv->cec_dev, 0x35, 0xff, 0x40); /* vfp */
+	adv7535_i2c_reg_write(priv->cec_dev, 0x36, 0xff, 0x02); /* vbp */
+	adv7535_i2c_reg_write(priv->cec_dev, 0x37, 0xff, 0x40); /* vbp */
+
+	/* Reset Internal Timing Generator */
+	adv7535_i2c_reg_write(priv->cec_dev, 0x27, 0xff, 0xCB);
+	adv7535_i2c_reg_write(priv->cec_dev, 0x27, 0xff, 0x8B);
+	adv7535_i2c_reg_write(priv->cec_dev, 0x27, 0xff, 0xCB);
+
+	/* HDMI Output */
+	adv7535_i2c_reg_write(dev, 0xAF, 0xff, 0x16);
+	/* AVI Infoframe - RGB - 16-9 Aspect Ratio */
+	adv7535_i2c_reg_write(dev, 0x55, 0xff, 0x10);
+	//adv7535_i2c_reg_write(dev, 0x55, 0xff, 0x02);
+	adv7535_i2c_reg_write(dev, 0x56, 0xff, 0x28);
+	//adv7535_i2c_reg_write(dev, 0x56, 0xff, 0x0);
+
+	/*  GC Packet Enable */
+	adv7535_i2c_reg_write(dev, 0x40, 0xff, 0x80);
+	//adv7535_i2c_reg_write(dev, 0x40, 0xff, 0x0);
+	/*  GC Colour Depth - 24 Bit */
+	adv7535_i2c_reg_write(dev, 0x4C, 0xff, 0x04);
+	//adv7535_i2c_reg_write(dev, 0x4C, 0xff, 0x0);
+	/*  Down Dither Output Colour Depth - 8 Bit (default) */
+	adv7535_i2c_reg_write(dev, 0x49, 0xff, 0x00);
+
+	/* set low refresh 1080p30 */
+	adv7535_i2c_reg_write(dev, 0x4A, 0xff, 0x80); /*should be 0x80 for 1080p60 and 0x8c for 1080p30*/
+
+	/* HDMI Output Enable */
+	//adv7535_i2c_reg_write(priv->cec_dev, 0xbe, 0xff, 0x3c);
+	adv7535_i2c_reg_write(priv->cec_dev, 0xbe, 0xff, 0x3d);
+	adv7535_i2c_reg_write(priv->cec_dev, 0x03, 0xff, 0x89);
+
+	return 0;
+}
+
+static int adv7535_enable_backlight(struct udevice *dev)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	struct mipi_dsi_device *device = plat->device;
+	int ret;
+
+	ret = mipi_dsi_attach(device);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int adv7535_get_display_timing(struct udevice *dev,
+					    struct display_timing *timings)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	struct mipi_dsi_device *device = plat->device;
+	struct adv7535_priv *priv = dev_get_priv(dev);
+
+	memcpy(timings, &default_timing, sizeof(*timings));
+
+	/* fill characteristics of DSI data link */
+	if (device) {
+		device->lanes = priv->lanes;
+		device->format = priv->format;
+		device->mode_flags = priv->mode_flags;
+	}
+
+	return 0;
+}
+
+static int adv7535_probe(struct udevice *dev)
+{
+	struct adv7535_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	debug("%s\n", __func__);
+
+	priv->format = MIPI_DSI_FMT_RGB888;
+	priv->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+			  MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE,
+
+	priv->addr  = dev_read_addr(dev);
+	if (priv->addr  == 0)
+		return -ENODEV;
+
+	ret = dev_read_u32(dev, "adi,dsi-lanes", &priv->lanes);
+	if (ret) {
+		dev_err(dev, "Failed to get dsi-lanes property (%d)\n", ret);
+		return ret;
+	}
+
+	if (priv->lanes < 1 || priv->lanes > 4) {
+		dev_err(dev, "Invalid dsi-lanes: %d\n", priv->lanes);
+		return -EINVAL;
+	}
+
+	ret = dev_read_u32(dev, "adi,addr-cec", &priv->addr_cec);
+	if (ret) {
+		dev_err(dev, "Failed to get addr-cec property (%d)\n", ret);
+		return -EINVAL;
+	}
+
+	ret = dm_i2c_probe(dev_get_parent(dev), priv->addr_cec, 0, &priv->cec_dev);
+	if (ret) {
+		dev_err(dev, "Can't find cec device id=0x%x\n", priv->addr_cec);
+		return -ENODEV;
+	}
+
+	adv7535_enable(dev);
+
+	return 0;
+}
+
+static const struct panel_ops adv7535_ops = {
+	.enable_backlight = adv7535_enable_backlight,
+	.get_display_timing = adv7535_get_display_timing,
+};
+
+static const struct udevice_id adv7535_ids[] = {
+	{ .compatible = "adi,adv7535" },
+	{ }
+};
+
+U_BOOT_DRIVER(adv7535_mipi2hdmi) = {
+	.name			  = "adv7535_mipi2hdmi",
+	.id			  = UCLASS_PANEL,
+	.of_match		  = adv7535_ids,
+	.ops			  = &adv7535_ops,
+	.probe			  = adv7535_probe,
+	.plat_auto = sizeof(struct mipi_dsi_panel_plat),
+	.priv_auto	= sizeof(struct adv7535_priv),
+};
diff --git a/drivers/video/bridge/video-bridge-uclass.c b/drivers/video/bridge/video-bridge-uclass.c
index f389bc6b147..abee8d293e5 100644
--- a/drivers/video/bridge/video-bridge-uclass.c
+++ b/drivers/video/bridge/video-bridge-uclass.c
@@ -49,6 +49,16 @@ int video_bridge_check_attached(struct udevice *dev)
 	return ops->check_attached(dev);
 }
 
+int video_bridge_check_timing(struct udevice *dev, struct display_timing *timing)
+{
+	struct video_bridge_ops *ops = video_bridge_get_ops(dev);
+
+	if (ops->check_timing)
+		return ops->check_timing(dev, timing);
+
+	return 0;
+}
+
 int video_bridge_read_edid(struct udevice *dev, u8 *buf, int buf_size)
 {
 	struct video_bridge_ops *ops = video_bridge_get_ops(dev);
@@ -136,6 +146,7 @@ int video_bridge_set_active(struct udevice *dev, bool active)
 UCLASS_DRIVER(video_bridge) = {
 	.id		= UCLASS_VIDEO_BRIDGE,
 	.name		= "video_bridge",
+	.flags		= DM_UC_FLAG_SEQ_ALIAS,
 	.per_device_auto	= sizeof(struct video_bridge_priv),
 	.pre_probe	= video_bridge_pre_probe,
 };
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 52b109f1551..1efdf4d4424 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -1120,7 +1120,7 @@ static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff,
 	y = __le32_to_cpu(img->header.height) - 1;
 	ncolors = __le32_to_cpu(img->header.colors_used);
 	bpp = VIDEO_PIXEL_SIZE;
-	fbp = (unsigned char *) ((unsigned int) video_fb_address +
+	fbp = (unsigned char *) ((unsigned long) video_fb_address +
 				 (y + yoff) * VIDEO_LINE_LEN +
 				 xoff * bpp);
 
@@ -1175,7 +1175,7 @@ static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff,
 				x = 0;
 				y--;
 				fbp = (unsigned char *)
-					((unsigned int) video_fb_address +
+					((unsigned long) video_fb_address +
 					 (y + yoff) * VIDEO_LINE_LEN +
 					 xoff * bpp);
 				continue;
@@ -1188,7 +1188,7 @@ static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff,
 				x += bm[2];
 				y -= bm[3];
 				fbp = (unsigned char *)
-					((unsigned int) video_fb_address +
+					((unsigned long) video_fb_address +
 					 (y + yoff) * VIDEO_LINE_LEN +
 					 xoff * bpp);
 				bm += 4;
@@ -1676,7 +1676,7 @@ static int cfg_video_init(void)
 	if (pGD == NULL)
 		return -1;
 
-	video_fb_address = (void *) VIDEO_FB_ADRS;
+	video_fb_address = (void *)(unsigned long) VIDEO_FB_ADRS;
 
 	cfb_do_flush_cache = cfb_fb_is_in_dram() && dcache_status();
 
diff --git a/drivers/video/display-uclass.c b/drivers/video/display-uclass.c
index 2da3d1d14e9..ae475c85a6b 100644
--- a/drivers/video/display-uclass.c
+++ b/drivers/video/display-uclass.c
@@ -81,5 +81,6 @@ bool display_in_use(struct udevice *dev)
 UCLASS_DRIVER(display) = {
 	.id		= UCLASS_DISPLAY,
 	.name		= "display",
+	.flags          = DM_UC_FLAG_SEQ_ALIAS,
 	.per_device_plat_auto	= sizeof(struct display_plat),
 };
diff --git a/drivers/video/dsi-host-uclass.c b/drivers/video/dsi-host-uclass.c
index 6e5256eb126..3b6ec8c0a89 100644
--- a/drivers/video/dsi-host-uclass.c
+++ b/drivers/video/dsi-host-uclass.c
@@ -35,6 +35,16 @@ int dsi_host_enable(struct udevice *dev)
 	return ops->enable(dev);
 }
 
+int dsi_host_disable(struct udevice *dev)
+{
+	struct dsi_host_ops *ops = dsi_host_get_ops(dev);
+
+	if (!ops->disable)
+		return -ENOSYS;
+
+	return ops->disable(dev);
+}
+
 UCLASS_DRIVER(dsi_host) = {
 	.id		= UCLASS_DSI_HOST,
 	.name		= "dsi_host",
diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c
index a5b38acabdb..0cd50fd465f 100644
--- a/drivers/video/dw_mipi_dsi.c
+++ b/drivers/video/dw_mipi_dsi.c
@@ -513,7 +513,7 @@ static void dw_mipi_dsi_init_pll(struct dw_mipi_dsi *dsi)
 	 * timeout clock division should be computed with the
 	 * high speed transmission counter timeout and byte lane...
 	 */
-	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
+	dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(0) |
 		  TX_ESC_CLK_DIVISION(esc_clk_division));
 }
 
@@ -538,9 +538,9 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 		break;
 	}
 
-	if (device->mode_flags & DISPLAY_FLAGS_VSYNC_HIGH)
+	if (timings->flags & DISPLAY_FLAGS_VSYNC_LOW)
 		val |= VSYNC_ACTIVE_LOW;
-	if (device->mode_flags & DISPLAY_FLAGS_HSYNC_HIGH)
+	if (timings->flags & DISPLAY_FLAGS_HSYNC_LOW)
 		val |= HSYNC_ACTIVE_LOW;
 
 	dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
@@ -552,7 +552,7 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
 	 * should be computed according to byte lane, lane number and only
 	 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
 	 */
-	dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
+	dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(0x10)
 		  | INVACT_LPCMD_TIME(4));
 }
 
@@ -621,8 +621,8 @@ static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
 	htotal = timings->hactive.typ + timings->hfront_porch.typ +
 		 timings->hback_porch.typ + timings->hsync_len.typ;
 
-	hsa = timings->hback_porch.typ;
-	hbp = timings->hsync_len.typ;
+	hsa = timings->hsync_len.typ;
+	hbp = timings->hback_porch.typ;
 
 	/*
 	 * TODO dw drv improvements
@@ -644,9 +644,9 @@ static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
 	u32 vactive, vsa, vfp, vbp;
 
 	vactive = timings->vactive.typ;
-	vsa =  timings->vback_porch.typ;
-	vfp =  timings->vfront_porch.typ;
-	vbp = timings->vsync_len.typ;
+	vsa = timings->vsync_len.typ;
+	vfp = timings->vfront_porch.typ;
+	vbp = timings->vback_porch.typ;
 
 	dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
 	dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
@@ -807,14 +807,11 @@ static int dw_mipi_dsi_init(struct udevice *dev,
 	}
 
 	ret = clk_get_by_name(device->dev, "px_clk", &clk);
-	if (ret) {
-		dev_err(device->dev, "peripheral clock get error %d\n", ret);
-		return ret;
+	if (!ret) {
+		/*  get the pixel clock set by the clock framework */
+		timings->pixelclock.typ = clk_get_rate(&clk);
 	}
 
-	/*  get the pixel clock set by the clock framework */
-	timings->pixelclock.typ = clk_get_rate(&clk);
-
 	dw_mipi_dsi_bridge_set(dsi, timings);
 
 	return 0;
@@ -840,9 +837,19 @@ static int dw_mipi_dsi_probe(struct udevice *dev)
 	return 0;
 }
 
+#if (IS_ENABLED(CONFIG_VIDEO_IMX_DW_DSI))
+static const struct udevice_id dw_mipi_dsi_ids[] = {
+	{ .compatible = "synopsys,dw-mipi-dsi" },
+	{ }
+};
+#endif
+
 U_BOOT_DRIVER(dw_mipi_dsi) = {
 	.name			= "dw_mipi_dsi",
 	.id			= UCLASS_DSI_HOST,
+#if (IS_ENABLED(CONFIG_VIDEO_IMX_DW_DSI))
+	.of_match		= dw_mipi_dsi_ids,
+#endif
 	.probe			= dw_mipi_dsi_probe,
 	.ops			= &dw_mipi_dsi_ops,
 	.priv_auto	= sizeof(struct dw_mipi_dsi),
diff --git a/drivers/video/imx/Kconfig b/drivers/video/imx/Kconfig
deleted file mode 100644
index 78eb0f29fb3..00000000000
--- a/drivers/video/imx/Kconfig
+++ /dev/null
@@ -1,8 +0,0 @@
-
-config VIDEO_IPUV3
-	bool "i.MX IPUv3 Core video support"
-	depends on DM_VIDEO && (MX5 || MX6)
-	help
-	  This enables framebuffer driver for i.MX processors working
-	  on the IPUv3(Image Processing Unit) internal graphic processor.
-
diff --git a/drivers/video/imx/Makefile b/drivers/video/imx/Makefile
deleted file mode 100644
index 179ea651fe8..00000000000
--- a/drivers/video/imx/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
diff --git a/drivers/video/it6263_bridge.c b/drivers/video/it6263_bridge.c
new file mode 100644
index 00000000000..405d0571abb
--- /dev/null
+++ b/drivers/video/it6263_bridge.c
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <video.h>
+#include <video_bridge.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <linux/delay.h>
+
+struct it6263_priv {
+	unsigned int addr;
+};
+
+static int it6263_i2c_reg_write(struct udevice *dev, uint addr, uint mask, uint data)
+{
+	uint8_t valb;
+	int err;
+
+	if (mask != 0xff) {
+		err = dm_i2c_read(dev, addr, &valb, 1);
+		if (err) {
+			printf("%s, read err %d\n", __func__, err);
+			return err;
+		}
+
+		valb &= ~mask;
+		valb |= data;
+	} else {
+		valb = data;
+	}
+
+	err = dm_i2c_write(dev, addr, &valb, 1);
+	if (err) {
+		printf("%s, write err %d\n", __func__, err);
+	}
+	return err;
+}
+
+static int it6263_i2c_reg_read(struct udevice *dev, uint8_t addr, uint8_t *data)
+{
+	uint8_t valb;
+	int err;
+
+	err = dm_i2c_read(dev, addr, &valb, 1);
+	if (err) {
+		printf("%s, read err %d\n", __func__, err);
+		return err;
+	}
+
+	*data = (int)valb;
+	return 0;
+}
+
+static int it6263_enable(struct udevice *dev)
+{
+	uint8_t data;
+	int ret;
+
+	ret = it6263_i2c_reg_read(dev, 0x00, &data);
+	if (ret) {
+		printf("faill to read from it6263 revision, ret %d\n", ret);
+		return ret;
+	}
+
+	/* InitIT626X(): start */
+	it6263_i2c_reg_write(dev, 0x04, 0xff, 0x3d);
+	it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0x05, 0xff, 0x40);
+	it6263_i2c_reg_write(dev, 0x04, 0xff, 0x15);
+	it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0x1d, 0xff, 0x66);
+	it6263_i2c_reg_write(dev, 0x1e, 0xff, 0x01);
+
+	it6263_i2c_reg_write(dev, 0x61, 0xff, 0x30);
+	it6263_i2c_reg_read(dev, 0xf3, &data); /* -> 0x00 */
+	it6263_i2c_reg_write(dev, 0xf3, 0xff, data & ~0x30);
+	it6263_i2c_reg_read(dev, 0xf3, &data); /* -> 0x00 */
+	it6263_i2c_reg_write(dev, 0xf3, 0xff, data | 0x20);
+
+	it6263_i2c_reg_write(dev, 0x09, 0xff, 0x30);
+	it6263_i2c_reg_write(dev, 0x0a, 0xff, 0xf8);
+	it6263_i2c_reg_write(dev, 0x0b, 0xff, 0x37);
+	it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0xc9, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0xca, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0xcb, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0xcc, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0xcd, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0xce, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0xcf, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0xd0, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x01);
+
+	it6263_i2c_reg_read(dev, 0x58, &data); /* -> 0x00 */
+	it6263_i2c_reg_write(dev, 0x58, 0xff, data & ~(3 << 5));
+
+	it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0xe1, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0x0c, 0xff, 0xff);
+	it6263_i2c_reg_write(dev, 0x0d, 0xff, 0xff);
+	it6263_i2c_reg_read(dev, 0x0e, &data); /* -> 0x00 */
+	it6263_i2c_reg_write(dev, 0x0e, 0xff, (data | 0x3));
+	it6263_i2c_reg_write(dev, 0x0e, 0xff, (data & 0xfe));
+	it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x01);
+	it6263_i2c_reg_write(dev, 0x33, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0x34, 0xff, 0x18);
+	it6263_i2c_reg_write(dev, 0x35, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0xc4, 0xff, 0xfe);
+	it6263_i2c_reg_read(dev, 0xc5, &data); /* -> 0x00 */
+	it6263_i2c_reg_write(dev, 0xc5, 0xff, data | 0x30);
+	/* InitIT626X  end */
+
+	it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0x04, 0xff, 0x3d);
+	it6263_i2c_reg_write(dev, 0x04, 0xff, 0x15);
+	it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0x1d, 0xff, 0x66);
+	it6263_i2c_reg_write(dev, 0x1e, 0xff, 0x01);
+
+	it6263_i2c_reg_read(dev, 0xc1, &data); /* -> 0x00 */
+	it6263_i2c_reg_write(dev, 0x61, 0xff, 0x10);
+
+	/* SetupAFE(): */
+	it6263_i2c_reg_write(dev, 0x62, 0xff, 0x88);
+	it6263_i2c_reg_write(dev, 0x63, 0xff, 0x10);
+	it6263_i2c_reg_write(dev, 0x64, 0xff, 0x84);
+	/* SetupAFE(): end */
+
+	it6263_i2c_reg_read(dev, 0x04, &data); /* -> 0x00 */
+	it6263_i2c_reg_write(dev, 0x04, 0xff, 0x1d);
+
+	it6263_i2c_reg_read(dev, 0x04, &data); /* -> 0x00 */
+	it6263_i2c_reg_write(dev, 0x04, 0xff, 0x15);
+
+	it6263_i2c_reg_read(dev, 0x0e, &data); /* -> 0x00 */
+
+	/*  Wait video stable */
+	it6263_i2c_reg_read(dev, 0x0e, &data); /* -> 0x00 */
+
+	/* Reset Video */
+	it6263_i2c_reg_read(dev, 0x0d, &data); /* -> 0x00 */
+	it6263_i2c_reg_write(dev, 0x0d, 0xff, 0x40);
+	it6263_i2c_reg_read(dev, 0x0e, &data); /* -> 0x00 */
+	it6263_i2c_reg_write(dev, 0x0e, 0xff, 0x7d);
+	it6263_i2c_reg_write(dev, 0x0e, 0xff, 0x7c);
+	it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0x61, 0xff, 0x00);
+	it6263_i2c_reg_read(dev, 0x61, &data); /* -> 0x00 */
+	it6263_i2c_reg_read(dev, 0x62, &data); /* -> 0x00 */
+	it6263_i2c_reg_read(dev, 0x63, &data); /* -> 0x00 */
+	it6263_i2c_reg_read(dev, 0x64, &data); /* -> 0x00 */
+	it6263_i2c_reg_read(dev, 0x65, &data); /* -> 0x00 */
+	it6263_i2c_reg_read(dev, 0x66, &data); /* -> 0x00 */
+	it6263_i2c_reg_read(dev, 0x67, &data); /* -> 0x00 */
+	it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x00);
+	it6263_i2c_reg_read(dev, 0xc1, &data); /* -> 0x00 */
+	it6263_i2c_reg_write(dev, 0xc1, 0xff, 0x00);
+	it6263_i2c_reg_write(dev, 0xc6, 0xff, 0x03);
+	/* Clear AV mute */
+
+	return 0;
+}
+
+static int it6263_attach(struct udevice *dev)
+{
+	return 0;
+}
+
+static int it6263_set_backlight(struct udevice *dev, int percent)
+{
+	debug("%s\n", __func__);
+
+	mdelay(10);
+	it6263_enable(dev);
+	return 0;
+}
+
+static int it6263_probe(struct udevice *dev)
+{
+	struct it6263_priv *priv = dev_get_priv(dev);
+
+	debug("%s\n", __func__);
+
+	priv->addr  = dev_read_addr(dev);
+	if (priv->addr  == 0)
+		return -ENODEV;
+
+	return 0;
+}
+
+struct video_bridge_ops it6263_ops = {
+	.attach = it6263_attach,
+	.set_backlight = it6263_set_backlight,
+};
+
+static const struct udevice_id it6263_ids[] = {
+	{ .compatible = "ite,it6263" },
+	{ }
+};
+
+U_BOOT_DRIVER(it6263_bridge) = {
+	.name			  = "it6263_bridge",
+	.id			  = UCLASS_VIDEO_BRIDGE,
+	.of_match		  = it6263_ids,
+	.ops			  = &it6263_ops,
+	.bind			= dm_scan_fdt_dev,
+	.probe			  = it6263_probe,
+	.priv_auto	= sizeof(struct it6263_priv),
+};
diff --git a/drivers/video/mxc_csi.c b/drivers/video/mxc_csi.c
new file mode 100644
index 00000000000..07644e6cf0c
--- /dev/null
+++ b/drivers/video/mxc_csi.c
@@ -0,0 +1,272 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ */
+
+/*!
+ * @file fsl_csi.c, this file is derived from mx27_csi.c
+ *
+ * @brief mx25 CMOS Sensor interface functions
+ *
+ * @ingroup CSI
+ */
+#include <common.h>
+#include <malloc.h>
+
+#include <asm/arch/imx-regs.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+
+#include <linux/string.h>
+#include <linux/list.h>
+
+#include "mxc_csi.h"
+
+enum {
+	STD_NTSC = 0,
+	STD_PAL,
+};
+
+void __iomem *csi_regbase;
+
+static void csihw_reset_frame_count(void)
+{
+	__raw_writel(__raw_readl(CSI_CSICR3) | BIT_FRMCNT_RST, CSI_CSICR3);
+}
+
+static void csihw_reset(void)
+{
+	csihw_reset_frame_count();
+	__raw_writel(CSICR1_RESET_VAL, CSI_CSICR1);
+	__raw_writel(CSICR2_RESET_VAL, CSI_CSICR2);
+	__raw_writel(CSICR3_RESET_VAL, CSI_CSICR3);
+}
+
+/*!
+ * csi_init_interface
+ *    Init csi interface
+ */
+void csi_init_interface(void)
+{
+	unsigned int val = 0;
+	unsigned int imag_para;
+
+	val |= BIT_SOF_POL;
+	val |= BIT_REDGE;
+	val |= BIT_GCLK_MODE;
+	val |= BIT_HSYNC_POL;
+	val |= BIT_FCC;
+	val |= 1 << SHIFT_MCLKDIV;
+	val |= BIT_MCLKEN;
+	__raw_writel(val, CSI_CSICR1);
+
+	imag_para = (640 << 16) | 960;
+	__raw_writel(imag_para, CSI_CSIIMAG_PARA);
+
+	val = 0x1010;
+	val |= BIT_DMA_REFLASH_RFF;
+	__raw_writel(val, CSI_CSICR3);
+}
+
+void csi_format_swap16(bool enable)
+{
+	unsigned int val;
+
+	val = __raw_readl(CSI_CSICR1);
+	if (enable) {
+		val |= BIT_PACK_DIR;
+		val |= BIT_SWAP16_EN;
+	} else {
+		val &= ~BIT_PACK_DIR;
+		val &= ~BIT_SWAP16_EN;
+	}
+
+	__raw_writel(val, CSI_CSICR1);
+}
+
+void csi_enable_int(int arg)
+{
+	unsigned long cr1 = __raw_readl(CSI_CSICR1);
+
+	if (arg == 1) {
+		/* still capture needs DMA intterrupt */
+		cr1 |= BIT_FB1_DMA_DONE_INTEN;
+		cr1 |= BIT_FB2_DMA_DONE_INTEN;
+	}
+	__raw_writel(cr1, CSI_CSICR1);
+}
+
+void csi_disable_int(void)
+{
+	unsigned long cr1 = __raw_readl(CSI_CSICR1);
+
+	cr1 &= ~BIT_FB1_DMA_DONE_INTEN;
+	cr1 &= ~BIT_FB2_DMA_DONE_INTEN;
+	__raw_writel(cr1, CSI_CSICR1);
+}
+
+void csi_enable(int arg)
+{
+	unsigned long cr = __raw_readl(CSI_CSICR18);
+
+	if (arg == 1)
+		cr |= BIT_CSI_ENABLE;
+	else
+		cr &= ~BIT_CSI_ENABLE;
+	__raw_writel(cr, CSI_CSICR18);
+}
+
+void csi_buf_stride_set(u32 stride)
+{
+	__raw_writel(stride, CSI_CSIFBUF_PARA);
+}
+
+void csi_deinterlace_enable(bool enable)
+{
+	unsigned long cr18 = __raw_readl(CSI_CSICR18);
+
+	if (enable == true)
+		cr18 |= BIT_DEINTERLACE_EN;
+	else
+		cr18 &= ~BIT_DEINTERLACE_EN;
+
+	__raw_writel(cr18, CSI_CSICR18);
+}
+
+void csi_deinterlace_mode(int mode)
+{
+	unsigned long cr18 = __raw_readl(CSI_CSICR18);
+
+	if (mode == STD_NTSC)
+		cr18 |= BIT_NTSC_EN;
+	else
+		cr18 &= ~BIT_NTSC_EN;
+
+	__raw_writel(cr18, CSI_CSICR18);
+}
+
+void csi_tvdec_enable(bool enable)
+{
+	unsigned long cr18 = __raw_readl(CSI_CSICR18);
+	unsigned long cr1 = __raw_readl(CSI_CSICR1);
+
+	if (enable == true) {
+		cr18 |= (BIT_TVDECODER_IN_EN | BIT_BASEADDR_SWITCH_EN);
+		cr1 |= BIT_CCIR_MODE | BIT_EXT_VSYNC;
+		cr1 &= ~(BIT_SOF_POL | BIT_REDGE);
+	} else {
+		cr18 &= ~(BIT_TVDECODER_IN_EN | BIT_BASEADDR_SWITCH_EN);
+		cr1 &= ~(BIT_CCIR_MODE | BIT_EXT_VSYNC);
+		cr1 |= BIT_SOF_POL | BIT_REDGE;
+	}
+
+	__raw_writel(cr18, CSI_CSICR18);
+	__raw_writel(cr1, CSI_CSICR1);
+}
+
+void csi_set_32bit_imagpara(int width, int height)
+{
+	int imag_para = 0;
+	unsigned long cr3 = __raw_readl(CSI_CSICR3);
+
+	imag_para = (width << 16) | height;
+	__raw_writel(imag_para, CSI_CSIIMAG_PARA);
+
+
+	/* reflash the embeded DMA controller */
+	__raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3);
+}
+
+void csi_set_16bit_imagpara(int width, int height)
+{
+	int imag_para = 0;
+	unsigned long cr3 = __raw_readl(CSI_CSICR3);
+
+	imag_para = (width << 16) | (height * 2);
+	__raw_writel(imag_para, CSI_CSIIMAG_PARA);
+
+	/* reflash the embeded DMA controller */
+	__raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3);
+}
+
+void csi_set_12bit_imagpara(int width, int height)
+{
+	int imag_para = 0;
+	unsigned long cr3 = __raw_readl(CSI_CSICR3);
+
+	imag_para = (width << 16) | (height * 3 / 2);
+	__raw_writel(imag_para, CSI_CSIIMAG_PARA);
+
+	/* reflash the embeded DMA controller */
+	__raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3);
+}
+
+void csi_dmareq_rff_enable(void)
+{
+	unsigned long cr3 = __raw_readl(CSI_CSICR3);
+
+	cr3 |= BIT_DMA_REQ_EN_RFF;
+	cr3 |= BIT_HRESP_ERR_EN;
+	__raw_writel(cr3, CSI_CSICR3);
+}
+
+void csi_dmareq_rff_disable(void)
+{
+	unsigned long cr3 = __raw_readl(CSI_CSICR3);
+
+	cr3 &= ~BIT_DMA_REQ_EN_RFF;
+	cr3 &= ~BIT_HRESP_ERR_EN;
+	__raw_writel(cr3, CSI_CSICR3);
+}
+
+void csi_disable(void)
+{
+	csi_dmareq_rff_disable();
+	csi_disable_int();
+	csi_buf_stride_set(0);
+	csi_deinterlace_enable(false);
+	csi_tvdec_enable(false);
+	csi_enable(0);
+}
+
+void csi_config(struct csi_conf_param *csi_conf)
+{
+	csi_regbase = (u32 *)CSI1_BASE_ADDR;
+
+	csihw_reset();
+
+	csi_init_interface();
+	csi_dmareq_rff_disable();
+
+	switch (csi_conf->bpp) {
+	case 32:
+		csi_set_32bit_imagpara(csi_conf->width, csi_conf->height);
+		break;
+	case 16:
+		csi_set_16bit_imagpara(csi_conf->width, csi_conf->height);
+		break;
+	default:
+		printf(" %s case not supported, bpp=%d\n",
+				__func__, csi_conf->bpp);
+		return;
+	}
+
+	__raw_writel((u32)csi_conf->fb0addr, CSI_CSIDMASA_FB1);
+	__raw_writel((u32)csi_conf->fb1addr, CSI_CSIDMASA_FB2);
+
+	csi_buf_stride_set(0);
+	if (csi_conf->btvmode) {
+		/* Enable csi PAL/NTSC deinterlace mode */
+		csi_buf_stride_set(csi_conf->width);
+		csi_deinterlace_mode(csi_conf->std);
+		csi_deinterlace_enable(true);
+		csi_tvdec_enable(true);
+	}
+
+	/* start csi */
+	csi_dmareq_rff_enable();
+	csi_enable_int(1);
+	csi_enable(1);
+}
+
diff --git a/drivers/video/mxc_csi.h b/drivers/video/mxc_csi.h
new file mode 100644
index 00000000000..694214fb70b
--- /dev/null
+++ b/drivers/video/mxc_csi.h
@@ -0,0 +1,153 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ */
+
+/*!
+ * @file mxc_csi.h
+ *
+ * @brief mxc CMOS Sensor interface functions
+ *
+ * @ingroup CSI
+ */
+
+#ifndef MXC_CSI_H
+#define MXC_CSI_H
+
+/* reset values */
+#define CSICR1_RESET_VAL	0x40000800
+#define CSICR2_RESET_VAL	0x0
+#define CSICR3_RESET_VAL	0x0
+
+/* csi control reg 1 */
+#define BIT_SWAP16_EN		(0x1 << 31)
+#define BIT_EXT_VSYNC		(0x1 << 30)
+#define BIT_EOF_INT_EN		(0x1 << 29)
+#define BIT_PRP_IF_EN		(0x1 << 28)
+#define BIT_CCIR_MODE		(0x1 << 27)
+#define BIT_COF_INT_EN		(0x1 << 26)
+#define BIT_SF_OR_INTEN		(0x1 << 25)
+#define BIT_RF_OR_INTEN		(0x1 << 24)
+#define BIT_SFF_DMA_DONE_INTEN  (0x1 << 22)
+#define BIT_STATFF_INTEN	(0x1 << 21)
+#define BIT_FB2_DMA_DONE_INTEN  (0x1 << 20)
+#define BIT_FB1_DMA_DONE_INTEN  (0x1 << 19)
+#define BIT_RXFF_INTEN		(0x1 << 18)
+#define BIT_SOF_POL		(0x1 << 17)
+#define BIT_SOF_INTEN		(0x1 << 16)
+#define BIT_MCLKDIV		(0xF << 12)
+#define BIT_HSYNC_POL		(0x1 << 11)
+#define BIT_CCIR_EN		(0x1 << 10)
+#define BIT_MCLKEN		(0x1 << 9)
+#define BIT_FCC			(0x1 << 8)
+#define BIT_PACK_DIR		(0x1 << 7)
+#define BIT_CLR_STATFIFO	(0x1 << 6)
+#define BIT_CLR_RXFIFO		(0x1 << 5)
+#define BIT_GCLK_MODE		(0x1 << 4)
+#define BIT_INV_DATA		(0x1 << 3)
+#define BIT_INV_PCLK		(0x1 << 2)
+#define BIT_REDGE		(0x1 << 1)
+#define BIT_PIXEL_BIT		(0x1 << 0)
+
+#define SHIFT_MCLKDIV		12
+
+/* control reg 3 */
+#define BIT_FRMCNT		(0xFFFF << 16)
+#define BIT_FRMCNT_RST		(0x1 << 15)
+#define BIT_DMA_REFLASH_RFF	(0x1 << 14)
+#define BIT_DMA_REFLASH_SFF	(0x1 << 13)
+#define BIT_DMA_REQ_EN_RFF	(0x1 << 12)
+#define BIT_DMA_REQ_EN_SFF	(0x1 << 11)
+#define BIT_STATFF_LEVEL	(0x7 << 8)
+#define BIT_HRESP_ERR_EN	(0x1 << 7)
+#define BIT_RXFF_LEVEL		(0x7 << 4)
+#define BIT_TWO_8BIT_SENSOR	(0x1 << 3)
+#define BIT_ZERO_PACK_EN	(0x1 << 2)
+#define BIT_ECC_INT_EN		(0x1 << 1)
+#define BIT_ECC_AUTO_EN		(0x1 << 0)
+
+#define SHIFT_FRMCNT		16
+
+/* csi status reg */
+#define BIT_SFF_OR_INT		(0x1 << 25)
+#define BIT_RFF_OR_INT		(0x1 << 24)
+#define BIT_DMA_TSF_DONE_SFF	(0x1 << 22)
+#define BIT_STATFF_INT		(0x1 << 21)
+#define BIT_DMA_TSF_DONE_FB2	(0x1 << 20)
+#define BIT_DMA_TSF_DONE_FB1	(0x1 << 19)
+#define BIT_RXFF_INT		(0x1 << 18)
+#define BIT_EOF_INT		(0x1 << 17)
+#define BIT_SOF_INT		(0x1 << 16)
+#define BIT_F2_INT		(0x1 << 15)
+#define BIT_F1_INT		(0x1 << 14)
+#define BIT_COF_INT		(0x1 << 13)
+#define BIT_HRESP_ERR_INT	(0x1 << 7)
+#define BIT_ECC_INT		(0x1 << 1)
+#define BIT_DRDY		(0x1 << 0)
+
+/* csi control reg 18 */
+#define BIT_CSI_ENABLE			(0x1 << 31)
+#define BIT_BASEADDR_SWITCH_SEL	(0x1 << 5)
+#define BIT_BASEADDR_SWITCH_EN	(0x1 << 4)
+#define BIT_PARALLEL24_EN		(0x1 << 3)
+#define BIT_DEINTERLACE_EN		(0x1 << 2)
+#define BIT_TVDECODER_IN_EN		(0x1 << 1)
+#define BIT_NTSC_EN				(0x1 << 0)
+
+#define CSI_MCLK_VF		1
+#define CSI_MCLK_ENC		2
+#define CSI_MCLK_RAW		4
+#define CSI_MCLK_I2C		8
+
+#define CSI_CSICR1				(csi_regbase)
+#define CSI_CSICR2				(csi_regbase + 0x4)
+#define CSI_CSICR3				(csi_regbase + 0x8)
+#define CSI_STATFIFO			(csi_regbase + 0xC)
+#define CSI_CSIRXFIFO			(csi_regbase + 0x10)
+#define CSI_CSIRXCNT			(csi_regbase + 0x14)
+#define CSI_CSISR				(csi_regbase + 0x18)
+#define CSI_CSIDBG				(csi_regbase + 0x1C)
+#define CSI_CSIDMASA_STATFIFO	(csi_regbase + 0x20)
+#define CSI_CSIDMATS_STATFIFO	(csi_regbase + 0x24)
+#define CSI_CSIDMASA_FB1		(csi_regbase + 0x28)
+#define CSI_CSIDMASA_FB2		(csi_regbase + 0x2C)
+#define CSI_CSIFBUF_PARA		(csi_regbase + 0x30)
+#define CSI_CSIIMAG_PARA		(csi_regbase + 0x34)
+#define CSI_CSICR18				(csi_regbase + 0x48)
+#define CSI_CSICR19				(csi_regbase + 0x4c)
+
+struct mxs_csi_regs {
+	u32 csi_csicr1;				/* 0x0 */
+	u32 csi_csicr2;				/* 0x4 */
+	u32 csi_csicr3;				/* 0x8 */
+	u32 csi_statfifo;			/* 0xC */
+	u32 csi_csirxfifo;			/* 0x10 */
+	u32 csi_csirxcnt;			/* 0x14 */
+	u32 csi_csisr;				/* 0x18 */
+	u32 csi_csidbg;				/* 0x1C */
+	u32 csi_csidmasa_statfifo;	/* 0x20 */
+	u32 csi_csidmats_statfifo;	/* 0x24 */
+	u32 csi_csidmasa_fb1;		/* 0x28 */
+	u32 csi_csidmasa_fb2;		/* 0x2C */
+	u32 csi_csifbuf_para;		/* 0x30 */
+	u32 csi_csiimag_para;		/* 0x34 */
+	u32 reserver[4];
+	u32 csi_csicr18;			/* 0x48 */
+	u32 csi_csicr19;			/* 0x4c */
+};
+
+struct csi_conf_param {
+	unsigned short width;
+	unsigned short height;
+	unsigned int pixel_fmt;
+	unsigned int bpp;
+	bool btvmode;
+	unsigned int std;
+	void *fb0addr;
+	void *fb1addr;
+};
+
+void csi_config(struct csi_conf_param *csi_conf);
+void csi_disable(void);
+#endif
diff --git a/drivers/video/mxc_epdc_fb.c b/drivers/video/mxc_epdc_fb.c
new file mode 100644
index 00000000000..84937841f0d
--- /dev/null
+++ b/drivers/video/mxc_epdc_fb.c
@@ -0,0 +1,489 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * Based on STMP378X LCDIF
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+#include <common.h>
+#include <lcd.h>
+#include <linux/list.h>
+#include <linux/err.h>
+#include <linux/types.h>
+#include <malloc.h>
+
+#include <mxc_epdc_fb.h>
+#include <cpu_func.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+#include <asm/mach-imx/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void *lcd_base;			/* Start of framebuffer memory	*/
+void *lcd_console_address;	/* Start of console buffer	*/
+
+int lcd_color_fg;
+int lcd_color_bg;
+
+short console_col;
+short console_row;
+
+int rev;
+
+void lcd_initcolregs(void)
+{
+}
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+}
+
+#define TEMP_USE_DEFAULT 8
+
+#define UPDATE_MODE_PARTIAL			0x0
+#define UPDATE_MODE_FULL			0x1
+
+#define TRUE 1
+#define FALSE 0
+
+#define msleep(a)	udelay(a * 1000)
+
+
+/********************************************************
+ * Start Low-Level EPDC Functions
+ ********************************************************/
+
+static inline void epdc_set_screen_res(u32 width, u32 height)
+{
+	u32 val = (height << EPDC_RES_VERTICAL_OFFSET) | width;
+
+	REG_WR(EPDC_BASE, EPDC_RES, val);
+}
+
+static inline void epdc_set_update_coord(u32 x, u32 y)
+{
+	u32 val = (y << EPDC_UPD_CORD_YCORD_OFFSET) | x;
+
+	REG_WR(EPDC_BASE, EPDC_UPD_CORD, val);
+}
+
+static inline void epdc_set_update_dimensions(u32 width, u32 height)
+{
+	u32 val = (height << EPDC_UPD_SIZE_HEIGHT_OFFSET) | width;
+
+	REG_WR(EPDC_BASE, EPDC_UPD_SIZE, val);
+}
+
+static void epdc_submit_update(u32 lut_num, u32 waveform_mode, u32 update_mode,
+			       int use_test_mode, u32 np_val)
+{
+	u32 reg_val = 0;
+
+	if (use_test_mode) {
+		reg_val |=
+			((np_val << EPDC_UPD_FIXED_FIXNP_OFFSET) &
+			EPDC_UPD_FIXED_FIXNP_MASK) | EPDC_UPD_FIXED_FIXNP_EN;
+
+		REG_WR(EPDC_BASE, EPDC_UPD_FIXED, reg_val);
+
+		reg_val = EPDC_UPD_CTRL_USE_FIXED;
+	} else {
+		REG_WR(EPDC_BASE, EPDC_UPD_FIXED, reg_val);
+	}
+
+	reg_val |=
+		((lut_num << EPDC_UPD_CTRL_LUT_SEL_OFFSET) &
+		EPDC_UPD_CTRL_LUT_SEL_MASK) |
+		((waveform_mode << EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET) &
+		EPDC_UPD_CTRL_WAVEFORM_MODE_MASK) |
+		update_mode;
+
+	REG_WR(EPDC_BASE, EPDC_UPD_CTRL, reg_val);
+}
+
+static inline int epdc_is_lut_active(u32 lut_num)
+{
+	u32 val = REG_RD(EPDC_BASE, EPDC_STATUS_LUTS);
+	int is_active = val & (1 << lut_num) ? TRUE : FALSE;
+
+	return is_active;
+}
+
+static void epdc_set_horizontal_timing(u32 horiz_start, u32 horiz_end,
+				       u32 hsync_width, u32 hsync_line_length)
+{
+	u32 reg_val =
+		((hsync_width << EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET) &
+		EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK)
+		| ((hsync_line_length << EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET) &
+		EPDC_TCE_HSCAN1_LINE_SYNC_MASK);
+	REG_WR(EPDC_BASE, EPDC_TCE_HSCAN1, reg_val);
+
+	reg_val =
+		((horiz_start << EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET) &
+		EPDC_TCE_HSCAN2_LINE_BEGIN_MASK)
+		| ((horiz_end << EPDC_TCE_HSCAN2_LINE_END_OFFSET) &
+		EPDC_TCE_HSCAN2_LINE_END_MASK);
+	REG_WR(EPDC_BASE, EPDC_TCE_HSCAN2, reg_val);
+}
+
+static void epdc_set_vertical_timing(u32 vert_start, u32 vert_end,
+					u32 vsync_width)
+{
+	u32 reg_val =
+		((vert_start << EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET) &
+		EPDC_TCE_VSCAN_FRAME_BEGIN_MASK)
+		| ((vert_end << EPDC_TCE_VSCAN_FRAME_END_OFFSET) &
+		EPDC_TCE_VSCAN_FRAME_END_MASK)
+		| ((vsync_width << EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET) &
+		EPDC_TCE_VSCAN_FRAME_SYNC_MASK);
+	REG_WR(EPDC_BASE, EPDC_TCE_VSCAN, reg_val);
+}
+
+static void epdc_init_settings(void)
+{
+	u32 reg_val;
+	int num_ce;
+
+	/* EPDC_CTRL */
+	reg_val = REG_RD(EPDC_BASE, EPDC_CTRL);
+	reg_val &= ~EPDC_CTRL_UPD_DATA_SWIZZLE_MASK;
+	reg_val |= EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP;
+	reg_val &= ~EPDC_CTRL_LUT_DATA_SWIZZLE_MASK;
+	reg_val |= EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP;
+	REG_SET(EPDC_BASE, EPDC_CTRL, reg_val);
+
+	/* EPDC_FORMAT - 2bit TFT and 4bit Buf pixel format */
+	reg_val = EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT
+		| EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N
+		| ((0x0 << EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET) &
+		EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK);
+	REG_WR(EPDC_BASE, EPDC_FORMAT, reg_val);
+
+	/* EPDC_FIFOCTRL (disabled) */
+	reg_val =
+		((100 << EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET) &
+		EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK)
+		| ((200 << EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET) &
+		EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK)
+		| ((100 << EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET) &
+		EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK);
+	REG_WR(EPDC_BASE, EPDC_FIFOCTRL, reg_val);
+
+	/* EPDC_TEMP - Use default temperature */
+	REG_WR(EPDC_BASE, EPDC_TEMP, TEMP_USE_DEFAULT);
+
+	/* EPDC_RES */
+	epdc_set_screen_res(panel_info.vl_col, panel_info.vl_row);
+
+	/*
+	 * EPDC_TCE_CTRL
+	 * VSCAN_HOLDOFF = 4
+	 * VCOM_MODE = MANUAL
+	 * VCOM_VAL = 0
+	 * DDR_MODE = DISABLED
+	 * LVDS_MODE_CE = DISABLED
+	 * LVDS_MODE = DISABLED
+	 * DUAL_SCAN = DISABLED
+	 * SDDO_WIDTH = 8bit
+	 * PIXELS_PER_SDCLK = 4
+	 */
+	reg_val =
+		((panel_info.epdc_data.epdc_timings.vscan_holdoff <<
+			EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET) &
+			EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK)
+		| EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4;
+	REG_WR(EPDC_BASE, EPDC_TCE_CTRL, reg_val);
+
+	/* EPDC_TCE_HSCAN */
+	epdc_set_horizontal_timing(panel_info.vl_left_margin,
+				panel_info.vl_right_margin,
+				panel_info.vl_hsync,
+				panel_info.vl_hsync);
+
+	/* EPDC_TCE_VSCAN */
+	epdc_set_vertical_timing(panel_info.vl_upper_margin,
+				 panel_info.vl_lower_margin,
+				 panel_info.vl_vsync);
+
+	/* EPDC_TCE_OE */
+	reg_val =
+		((panel_info.epdc_data.epdc_timings.sdoed_width <<
+			EPDC_TCE_OE_SDOED_WIDTH_OFFSET) &
+			EPDC_TCE_OE_SDOED_WIDTH_MASK)
+		| ((panel_info.epdc_data.epdc_timings.sdoed_delay <<
+			EPDC_TCE_OE_SDOED_DLY_OFFSET) &
+			EPDC_TCE_OE_SDOED_DLY_MASK)
+		| ((panel_info.epdc_data.epdc_timings.sdoez_width <<
+			EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET) &
+			EPDC_TCE_OE_SDOEZ_WIDTH_MASK)
+		| ((panel_info.epdc_data.epdc_timings.sdoez_delay <<
+			EPDC_TCE_OE_SDOEZ_DLY_OFFSET) &
+			EPDC_TCE_OE_SDOEZ_DLY_MASK);
+	REG_WR(EPDC_BASE, EPDC_TCE_OE, reg_val);
+
+	/* EPDC_TCE_TIMING1 */
+	REG_WR(EPDC_BASE, EPDC_TCE_TIMING1, 0x0);
+
+	/* EPDC_TCE_TIMING2 */
+	reg_val =
+		((panel_info.epdc_data.epdc_timings.gdclk_hp_offs <<
+			EPDC_TCE_TIMING2_GDCLK_HP_OFFSET) &
+			EPDC_TCE_TIMING2_GDCLK_HP_MASK)
+		| ((panel_info.epdc_data.epdc_timings.gdsp_offs <<
+			EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET) &
+			EPDC_TCE_TIMING2_GDSP_OFFSET_MASK);
+	REG_WR(EPDC_BASE, EPDC_TCE_TIMING2, reg_val);
+
+	/* EPDC_TCE_TIMING3 */
+	reg_val =
+		((panel_info.epdc_data.epdc_timings.gdoe_offs <<
+			EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET) &
+			EPDC_TCE_TIMING3_GDOE_OFFSET_MASK)
+		| ((panel_info.epdc_data.epdc_timings.gdclk_offs <<
+			EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET) &
+			EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK);
+	REG_WR(EPDC_BASE, EPDC_TCE_TIMING3, reg_val);
+
+	/*
+	 * EPDC_TCE_SDCFG
+	 * SDCLK_HOLD = 1
+	 * SDSHR = 1
+	 * NUM_CE = 1
+	 * SDDO_REFORMAT = FLIP_PIXELS
+	 * SDDO_INVERT = DISABLED
+	 * PIXELS_PER_CE = display horizontal resolution
+	 */
+	num_ce = panel_info.epdc_data.epdc_timings.num_ce;
+	if (num_ce == 0)
+		num_ce = 1;
+	reg_val = EPDC_TCE_SDCFG_SDCLK_HOLD | EPDC_TCE_SDCFG_SDSHR
+		| ((num_ce << EPDC_TCE_SDCFG_NUM_CE_OFFSET) & EPDC_TCE_SDCFG_NUM_CE_MASK)
+		| EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS
+		| ((panel_info.vl_col << EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET) &
+		EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK);
+	REG_WR(EPDC_BASE, EPDC_TCE_SDCFG, reg_val);
+
+	/*
+	 * EPDC_TCE_GDCFG
+	 * GDRL = 1
+	 * GDOE_MODE = 0;
+	 * GDSP_MODE = 0;
+	 */
+	reg_val = EPDC_TCE_SDCFG_GDRL;
+	REG_WR(EPDC_BASE, EPDC_TCE_GDCFG, reg_val);
+
+	/*
+	 * EPDC_TCE_POLARITY
+	 * SDCE_POL = ACTIVE LOW
+	 * SDLE_POL = ACTIVE HIGH
+	 * SDOE_POL = ACTIVE HIGH
+	 * GDOE_POL = ACTIVE HIGH
+	 * GDSP_POL = ACTIVE LOW
+	 */
+	reg_val = EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH
+		| EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH
+		| EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH;
+	REG_WR(EPDC_BASE, EPDC_TCE_POLARITY, reg_val);
+
+	/* EPDC_IRQ_MASK */
+	REG_WR(EPDC_BASE, EPDC_IRQ_MASK,
+		EPDC_IRQ_TCE_UNDERRUN_IRQ);
+
+	/*
+	 * EPDC_GPIO
+	 * PWRCOM = ?
+	 * PWRCTRL = ?
+	 * BDR = ?
+	 */
+	reg_val = ((0 << EPDC_GPIO_PWRCTRL_OFFSET) & EPDC_GPIO_PWRCTRL_MASK)
+		| ((0 << EPDC_GPIO_BDR_OFFSET) & EPDC_GPIO_BDR_MASK);
+	REG_WR(EPDC_BASE, EPDC_GPIO, reg_val);
+}
+
+static void draw_mode0(void)
+{
+	int i;
+
+	/* Program EPDC update to process buffer */
+	epdc_set_update_coord(0, 0);
+	epdc_set_update_dimensions(panel_info.vl_col, panel_info.vl_row);
+	epdc_submit_update(0, panel_info.epdc_data.wv_modes.mode_init,
+				UPDATE_MODE_FULL, FALSE, 0);
+
+	debug("Mode0 update - Waiting for LUT to complete...\n");
+
+	/* Will timeout after ~4-5 seconds */
+
+	for (i = 0; i < 40; i++) {
+		if (!epdc_is_lut_active(0)) {
+			debug("Mode0 init complete\n");
+			return;
+		}
+		msleep(100);
+	}
+
+	debug("Mode0 init failed!\n");
+
+}
+
+static void draw_splash_screen(void)
+{
+	int i;
+	int lut_num = 0;
+
+	/* Program EPDC update to process buffer */
+	epdc_set_update_coord(0, 0);
+	epdc_set_update_dimensions(panel_info.vl_col, panel_info.vl_row);
+	epdc_submit_update(lut_num, panel_info.epdc_data.wv_modes.mode_gc16,
+		UPDATE_MODE_FULL, FALSE, 0);
+
+	for (i = 0; i < 40; i++) {
+		if (!epdc_is_lut_active(lut_num)) {
+			debug("Splash screen update complete\n");
+			return;
+		}
+		msleep(100);
+	}
+	debug("Splash screen update failed!\n");
+}
+
+void lcd_enable(void)
+{
+	if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
+		if (check_module_fused(MODULE_EPDC)) {
+			return;
+		}
+	}
+
+	if (board_setup_logo_file(lcd_base)) {
+		debug("Load logo failed!\n");
+		return;
+	}
+
+	epdc_power_on();
+
+	flush_cache((ulong)lcd_base, panel_info.vl_col * panel_info.vl_row);
+
+	/* Draw data to display */
+	draw_mode0();
+
+	draw_splash_screen();
+}
+
+void lcd_disable(void)
+{
+	if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
+		if (check_module_fused(MODULE_EPDC)) {
+			return;
+		}
+	}
+
+	debug("lcd_disable\n");
+
+	/* Disable clocks to EPDC */
+	REG_SET(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE);
+}
+
+void lcd_panel_disable(void)
+{
+	epdc_power_off();
+}
+
+void lcd_ctrl_init(void *lcdbase)
+{
+	unsigned int val;
+
+	if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
+		if (check_module_fused(MODULE_EPDC)) {
+			printf("EPDC@0x%x is fused, disable it\n", EPDC_BASE_ADDR);
+			return;
+		}
+	}
+
+	/*
+	 * We rely on lcdbase being a physical address, i.e., either MMU off,
+	 * or 1-to-1 mapping. Might want to add some virt2phys here.
+	 */
+	if (!lcdbase)
+		return;
+
+	panel_info.epdc_data.working_buf_addr = (u_long)memalign(ARCH_DMA_MINALIGN,
+		panel_info.vl_col * panel_info.vl_row * 2);
+
+	if (!panel_info.epdc_data.working_buf_addr) {
+		printf("EPDC: Error allocating working buffer!\n");
+		return;
+	}
+
+	panel_info.epdc_data.waveform_buf_addr = (u_long)memalign(ARCH_DMA_MINALIGN,
+		CONFIG_WAVEFORM_BUF_SIZE);
+
+	if (!panel_info.epdc_data.waveform_buf_addr) {
+		printf("EPDC: Error allocating waveform buffer!\n");
+		return;
+	}
+
+	lcd_color_fg = 0xFF;
+	lcd_color_bg = 0xFF;
+
+	/* Reset */
+	REG_SET(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST);
+	while (!(REG_RD(EPDC_BASE, EPDC_CTRL) & EPDC_CTRL_CLKGATE))
+		;
+	REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST);
+
+	/* Enable clock gating (clear to enable) */
+	REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE);
+	while (REG_RD(EPDC_BASE, EPDC_CTRL) &
+	       (EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE))
+		;
+
+	debug("resolution %dx%d, bpp %d\n", (int)panel_info.vl_col,
+		(int)panel_info.vl_row, NBITS(panel_info.vl_bpix));
+
+	/* Get EPDC version */
+	val = REG_RD(EPDC_BASE, EPDC_VERSION);
+	rev = ((val & EPDC_VERSION_MAJOR_MASK) >>
+				EPDC_VERSION_MAJOR_OFFSET) * 10
+			+ ((val & EPDC_VERSION_MINOR_MASK) >>
+				EPDC_VERSION_MINOR_OFFSET);
+
+	/* Set framebuffer pointer */
+	REG_WR(EPDC_BASE, EPDC_UPD_ADDR, (u32)lcdbase);
+
+	/* Set Working Buffer pointer */
+	REG_WR(EPDC_BASE, EPDC_WB_ADDR, panel_info.epdc_data.working_buf_addr);
+	if (rev > 20)
+		REG_WR(EPDC_BASE, EPDC_WB_ADDR_TCE, panel_info.epdc_data.working_buf_addr);
+
+	/* Get waveform data address and offset */
+	if (board_setup_waveform_file(panel_info.epdc_data.waveform_buf_addr)) {
+		printf("Can't load waveform data!\n");
+		return;
+	}
+
+	/* Set Waveform Buffer pointer */
+	REG_WR(EPDC_BASE, EPDC_WVADDR,
+		panel_info.epdc_data.waveform_buf_addr);
+
+	/* Initialize EPDC, passing pointer to EPDC registers */
+	epdc_init_settings();
+
+	lcd_base = lcdbase;
+
+	return;
+}
+
+ulong calc_fbsize(void)
+{
+	return panel_info.vl_row * panel_info.vl_col * 2 \
+		* NBITS(panel_info.vl_bpix) / 8;
+}
+
+
+
diff --git a/drivers/video/mxc_gis.c b/drivers/video/mxc_gis.c
new file mode 100644
index 00000000000..eefb63ee595
--- /dev/null
+++ b/drivers/video/mxc_gis.c
@@ -0,0 +1,413 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <video_fb.h>
+
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+
+#include <linux/string.h>
+#include <linux/list.h>
+#include <linux/fb.h>
+#include <gis.h>
+#include <mxsfb.h>
+#include <env.h>
+#include <log.h>
+
+#include "mxc_gis.h"
+#include "mxc_csi.h"
+#include "mxc_pxp.h"
+#include "mxc_vadc.h"
+
+#define CHANNEL_OFFSET 36
+#define COMMAND_OFFSET 8
+#define REG_OFFSET 4
+#define COMMAND_OPCODE_SHIFT 8
+
+enum {
+	CMD_SET_ACC = 0,
+	CMD_WR_DATA,
+	CMD_WR_ACC,
+	CMD_WR_ALU,
+	CMD_MOV_ACC,
+	CMD_RD_DATA,
+	CMD_RD_ALU,
+	CMD_WR_FB_CSI,
+	CMD_WR_FB_PXP_IN,
+	CMD_WR_FB_PXP_OUT,
+	CMD_WR_FB_LCDIF,
+};
+
+enum {
+	ALU_AND = 0,
+	ALU_OR,
+	ALU_XOR,
+	ALU_ADD,
+	ALU_SUB,
+};
+
+enum {
+	CH_MAPPING_CSI_ISR = 0,
+	CH_MAPPING_CSI_FB_UPDATE,
+	CH_MAPPING_PXP_ISR,
+	CH_MAPPING_LCDIF_FB_UPDATE,
+	CH_MAPPING_PXP_KICK,
+	CH_MAPPING_CHANNEL_UNUSED = 0xf,
+};
+
+enum {
+	LCDIF1_SEL = 0x10,
+	LCDIF0_SEL = 0x8,
+	PXP_SEL    = 0x4,
+	CSI1_SEL   = 0x2,
+	CSI0_SEL   = 0x1,
+};
+
+struct command_opcode {
+	unsigned opcode:4;
+	unsigned alu:3;
+	unsigned acc_neg:1;
+};
+
+struct command_param {
+	union {
+		struct command_opcode cmd_bits;
+		u8  cmd_opc;
+	};
+	u32 addr;
+	u32 data;
+};
+
+struct channel_param {
+	u32 ch_num;
+	u32 ch_map;
+	u32 cmd_num;
+	struct command_param cmd_data[4];
+};
+
+static void *csibuf0, *csibuf1, *fb0, *fb1;
+static struct mxs_gis_regs *gis_regs;
+static struct mxs_pxp_regs *pxp_regs;
+static struct mxs_csi_regs *csi_regs;
+static struct mxs_lcdif_regs *lcdif_regs;
+static u32 lcdif_sel;
+static bool gis_running;
+
+static void config_channel(struct channel_param *ch)
+{
+	u32 val, i;
+	u32 reg_offset;
+
+	if (ch->cmd_num > 3 || ch->ch_num > 5) {
+		printf("Error val cmd_num=%d, ch_num=%d\n , \n", ch->cmd_num, ch->ch_num);
+		return;
+	}
+
+	/* Config channel map and command */
+	switch (ch->ch_num) {
+	case 0:
+		val = readl(&gis_regs->hw_gis_config0);
+		val &= ~(GIS_CONFIG0_CH0_MAPPING_MASK | GIS_CONFIG0_CH0_NUM_MASK);
+		val |= ch->ch_map << GIS_CONFIG0_CH0_MAPPING_SHIFT;
+		val |= ch->cmd_num << GIS_CONFIG0_CH0_NUM_SHIFT;
+		writel(val, &gis_regs->hw_gis_config0);
+		break;
+	case 1:
+		val = readl(&gis_regs->hw_gis_config0);
+		val &= ~(GIS_CONFIG0_CH1_MAPPING_MASK | GIS_CONFIG0_CH1_NUM_MASK);
+		val |= ch->ch_map << GIS_CONFIG0_CH1_MAPPING_SHIFT;
+		val |= ch->cmd_num << GIS_CONFIG0_CH1_NUM_SHIFT;
+		writel(val, &gis_regs->hw_gis_config0);
+		break;
+	case 2:
+		val = readl(&gis_regs->hw_gis_config0);
+		val &= ~(GIS_CONFIG0_CH2_MAPPING_MASK | GIS_CONFIG0_CH2_NUM_MASK);
+		val |= ch->ch_map << GIS_CONFIG0_CH2_MAPPING_SHIFT;
+		val |= ch->cmd_num << GIS_CONFIG0_CH2_NUM_SHIFT;
+		writel(val, &gis_regs->hw_gis_config0);
+		break;
+	case 3:
+		val = readl(&gis_regs->hw_gis_config0);
+		val &= ~(GIS_CONFIG0_CH3_MAPPING_MASK | GIS_CONFIG0_CH3_NUM_MASK);
+		val |= ch->ch_map << GIS_CONFIG0_CH3_MAPPING_SHIFT;
+		val |= ch->cmd_num << GIS_CONFIG0_CH3_NUM_SHIFT;
+		writel(val, &gis_regs->hw_gis_config0);
+		break;
+	case 4:
+		val = readl(&gis_regs->hw_gis_config1);
+		val &= ~(GIS_CONFIG1_CH4_MAPPING_MASK | GIS_CONFIG1_CH4_NUM_MASK);
+		val |= ch->ch_map << GIS_CONFIG1_CH4_MAPPING_SHIFT;
+		val |= ch->cmd_num << GIS_CONFIG1_CH4_NUM_SHIFT;
+		writel(val, &gis_regs->hw_gis_config1);
+		break;
+	case 5:
+		val = readl(&gis_regs->hw_gis_config1);
+		val &= ~(GIS_CONFIG1_CH5_MAPPING_MASK | GIS_CONFIG1_CH5_NUM_MASK);
+		val |= ch->ch_map << GIS_CONFIG1_CH5_MAPPING_SHIFT;
+		val |= ch->cmd_num << GIS_CONFIG1_CH5_NUM_SHIFT;
+		writel(val, &gis_regs->hw_gis_config1);
+		break;
+	default:
+		printf("Error channel num\n");
+	}
+
+	/* Config command  */
+	for (i = 0; i < ch->cmd_num; i++) {
+		val = readl(&gis_regs->hw_gis_ch0_ctrl + ch->ch_num * CHANNEL_OFFSET);
+		val &= ~(0xFF << (COMMAND_OPCODE_SHIFT * i));
+		val |= ch->cmd_data[i].cmd_opc << (COMMAND_OPCODE_SHIFT * i);
+		writel(val, &gis_regs->hw_gis_ch0_ctrl + ch->ch_num * CHANNEL_OFFSET);
+
+		reg_offset = ch->ch_num * CHANNEL_OFFSET + i * COMMAND_OFFSET;
+		writel(ch->cmd_data[i].addr, &gis_regs->hw_gis_ch0_addr0 + reg_offset);
+		writel(ch->cmd_data[i].data, &gis_regs->hw_gis_ch0_data0 + reg_offset);
+	}
+}
+
+static void gis_channel_init(void)
+{
+	struct channel_param ch;
+	int ret;
+	u32 addr0, data0, addr1, data1;
+	u32 val;
+
+	/* Restart the GIS block */
+	ret = mxs_reset_block(&gis_regs->hw_gis_ctrl_reg);
+	if (ret) {
+		debug("MXS GIS: Block reset timeout\n");
+		return;
+	}
+
+	writel((u32)csibuf0, &gis_regs->hw_gis_fb0);
+	writel((u32)csibuf1, &gis_regs->hw_gis_fb1);
+	writel((u32)fb0, &gis_regs->hw_gis_pxp_fb0);
+	writel((u32)fb1, &gis_regs->hw_gis_pxp_fb1);
+
+	/* Config channel 0 -- CSI clean interrupt  */
+	addr0 = (u32)&csi_regs->csi_csisr;
+	data0 = BIT_DMA_TSF_DONE_FB1 | BIT_DMA_TSF_DONE_FB2 | BIT_SOF_INT;
+	ch.ch_num = 0;
+	ch.ch_map = CH_MAPPING_CSI_ISR;
+	ch.cmd_num = 1;
+	ch.cmd_data[0].cmd_bits.opcode = CMD_WR_DATA;
+	ch.cmd_data[0].cmd_bits.alu = ALU_AND;
+	ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
+	ch.cmd_data[0].addr = CSI0_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0;
+	ch.cmd_data[0].data = data0;
+	config_channel(&ch);
+
+	/* Config channel 1 -- CSI set next framebuffer addr  */
+	addr0 = (u32)&csi_regs->csi_csidmasa_fb1;
+	data0 = (u32)&csi_regs->csi_csidmasa_fb2;
+	ch.ch_num = 1;
+	ch.ch_map = CH_MAPPING_CSI_FB_UPDATE;
+	ch.cmd_num = 1;
+	ch.cmd_data[0].cmd_bits.opcode = CMD_WR_FB_CSI;
+	ch.cmd_data[0].cmd_bits.alu = ALU_AND;
+	ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
+	ch.cmd_data[0].addr = CSI0_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0;
+	ch.cmd_data[0].data = data0;
+	config_channel(&ch);
+
+	/* Config channel 2 -- PXP clear interrupt and set framebuffer */
+	addr0 = (u32)&pxp_regs->pxp_stat_clr;
+	data0 = BM_PXP_STAT_IRQ;
+	addr1 = (u32)&pxp_regs->pxp_out_buf;
+	data1 = 0;
+	ch.ch_num = 2;
+	ch.ch_map = CH_MAPPING_PXP_ISR;
+	ch.cmd_num = 2;
+	ch.cmd_data[0].cmd_bits.opcode = CMD_WR_DATA;
+	ch.cmd_data[0].cmd_bits.alu = ALU_AND;
+	ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
+	ch.cmd_data[0].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0;
+	ch.cmd_data[0].data = data0;
+	ch.cmd_data[1].cmd_bits.opcode = CMD_WR_FB_PXP_OUT;
+	ch.cmd_data[1].cmd_bits.alu = ALU_AND;
+	ch.cmd_data[1].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
+	ch.cmd_data[1].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr1;
+	ch.cmd_data[1].data = data1;
+	config_channel(&ch);
+
+	/* Config channel 3 -- LCDIF set framebuffer to display */
+	addr0 = (u32)&lcdif_regs->hw_lcdif_next_buf;
+	data0 = 0;
+	ch.ch_num = 3;
+	ch.ch_map = CH_MAPPING_LCDIF_FB_UPDATE;
+	ch.cmd_num = 1;
+	ch.cmd_data[0].cmd_bits.opcode = CMD_WR_FB_LCDIF;
+	ch.cmd_data[0].cmd_bits.alu = ALU_AND;
+	ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
+	ch.cmd_data[0].addr = ((lcdif_sel == 0) ? LCDIF0_SEL : LCDIF1_SEL) << GIS_CH_ADDR_SEL_SHIFT | addr0;
+	ch.cmd_data[0].data = data0;
+	config_channel(&ch);
+
+	/* Config channel 4 -- PXP kick to process next framebuffer */
+	addr0 = (u32)&pxp_regs->pxp_ps_buf;
+	data0 = 0;
+	addr1 = (u32)&pxp_regs->pxp_ctrl;
+	data1 = BM_PXP_CTRL_IRQ_ENABLE | BM_PXP_CTRL_ENABLE;
+	ch.ch_num = 4;
+	ch.ch_map = CH_MAPPING_PXP_KICK;
+	ch.cmd_num = 2;
+	ch.cmd_data[0].cmd_bits.opcode = CMD_WR_FB_PXP_IN;
+	ch.cmd_data[0].cmd_bits.alu = ALU_AND;
+	ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
+	ch.cmd_data[0].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0;
+	ch.cmd_data[0].data = data0;
+	ch.cmd_data[1].cmd_bits.opcode = CMD_WR_DATA;
+	ch.cmd_data[1].cmd_bits.alu = ALU_AND;
+	ch.cmd_data[1].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE;
+	ch.cmd_data[1].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr1;
+	ch.cmd_data[1].data = data1;
+	config_channel(&ch);
+
+	/* start gis  */
+	val = readl(&gis_regs->hw_gis_ctrl);
+	if (lcdif_sel == 1)
+		val |= GIS_CTRL_ENABLE_SET | GIS_CTRL_LCDIF_SEL_LCDIF1;
+	else
+		val |= GIS_CTRL_ENABLE_SET | GIS_CTRL_LCDIF_SEL_LCDIF0;
+	writel(val, &gis_regs->hw_gis_ctrl);
+}
+
+void mxc_disable_gis(void)
+{
+	u32 val;
+
+	if (!gis_running)
+		return;
+
+	/* Stop gis */
+	val = GIS_CTRL_SFTRST_SET | GIS_CTRL_CLK_GATE_SET;
+	writel(val, &gis_regs->hw_gis_ctrl);
+
+	/* Stop pxp */
+	mxs_reset_block(&pxp_regs->pxp_ctrl_reg);
+	val = BM_PXP_CTRL_SFTRST | BM_PXP_CTRL_CLKGATE;
+	writel(val , &pxp_regs->pxp_ctrl);
+
+	csi_disable();
+
+	vadc_power_down();
+}
+
+void mxc_enable_gis(void)
+{
+	struct sensor_data sensor;
+	struct csi_conf_param csi_conf;
+	struct pxp_config_data pxp_conf;
+	struct display_panel panel;
+	u32 csimemsize, pxpmemsize;
+	char const *gis_input = env_get("gis");
+
+	if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
+		if (check_module_fused(MODULE_CSI)) {
+			printf("CSI@0x%x is fused, disable it\n", CSI1_BASE_ADDR);
+			return;
+		}
+	}
+
+	if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
+		if (check_module_fused(MODULE_PXP)) {
+			printf("PXP@0x%x is fused, disable it\n", PXP_BASE_ADDR);
+			return;
+		}
+	}
+
+	gis_regs = (struct mxs_gis_regs *)GIS_BASE_ADDR;
+	pxp_regs = (struct mxs_pxp_regs *)PXP_BASE_ADDR;
+	csi_regs = (struct mxs_csi_regs *)CSI1_BASE_ADDR;
+
+	gis_running = false;
+
+	if (gis_input != NULL && !strcmp(gis_input, "vadc")) {
+		printf("gis input --- vadc\n");
+		/* vadc_in 0 */
+		vadc_config(0);
+
+		/* Get vadc mode */
+		vadc_get_std(&sensor);
+	} else {
+		printf("gis input --- No input\n");
+		return;
+	}
+
+	/* Get display mode */
+	mxs_lcd_get_panel(&panel);
+
+	lcdif_regs = (struct mxs_lcdif_regs *)panel.reg_base;
+	if (panel.reg_base == LCDIF2_BASE_ADDR)
+		lcdif_sel = 1;
+	else
+		lcdif_sel = 0;
+
+	/* Allocate csi buffer */
+	if (sensor.pixel_fmt == FMT_YUV444) {
+		csimemsize = sensor.width * sensor.height * 4;
+		csi_conf.bpp = 32;
+	} else {
+		csimemsize = sensor.width * sensor.height * 2;
+		csi_conf.bpp = 16;
+	}
+
+	pxpmemsize = panel.width * panel.height * panel.gdfbytespp;
+	csibuf0 = malloc(csimemsize);
+	csibuf1 = malloc(csimemsize);
+	fb0 = malloc(pxpmemsize);
+	fb1 = malloc(pxpmemsize);
+	if (!csibuf0 || !csibuf1 || !fb0 || !fb1) {
+		printf("MXSGIS: Error allocating csibuffer!\n");
+		return;
+	}
+	/* Wipe framebuffer */
+	memset(csibuf0, 0, csimemsize);
+	memset(csibuf1, 0, csimemsize);
+	memset(fb0, 0, pxpmemsize);
+	memset(fb1, 0, pxpmemsize);
+
+	/*config csi  */
+	csi_conf.width = sensor.width;
+	csi_conf.height = sensor.height;
+	csi_conf.btvmode = true;
+	csi_conf.std = sensor.std_id;
+	csi_conf.fb0addr = csibuf0;
+	csi_conf.fb1addr = csibuf1;
+	csi_config(&csi_conf);
+
+	/* config pxp */
+	pxp_conf.s0_param.pixel_fmt = sensor.pixel_fmt;
+	pxp_conf.s0_param.width = sensor.width;
+	pxp_conf.s0_param.height = sensor.height;
+	pxp_conf.s0_param.stride = sensor.width * csi_conf.bpp/8;
+	pxp_conf.s0_param.paddr = csibuf0;
+
+	switch (panel.gdfindex) {
+	case GDF_32BIT_X888RGB:
+		pxp_conf.out_param.pixel_fmt = FMT_RGB888;
+		break;
+	case GDF_16BIT_565RGB:
+		pxp_conf.out_param.pixel_fmt = FMT_RGB565;
+		break;
+	default:
+		printf("GIS unsupported format!");
+	}
+
+	pxp_conf.out_param.width = panel.width;
+	pxp_conf.out_param.height = panel.height;
+	pxp_conf.out_param.stride = pxp_conf.out_param.width * panel.gdfbytespp;
+	pxp_conf.out_param.paddr = fb0;
+	pxp_config(&pxp_conf);
+
+	gis_running = true;
+
+	/* Config gis */
+	gis_channel_init();
+}
diff --git a/drivers/video/mxc_gis.h b/drivers/video/mxc_gis.h
new file mode 100644
index 00000000000..a1290c42418
--- /dev/null
+++ b/drivers/video/mxc_gis.h
@@ -0,0 +1,175 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ */
+
+#ifndef MXC_GIS_H
+#define MXC_GIS_H
+
+#include <asm/mach-imx/regs-common.h>
+
+struct mxs_gis_regs {
+	mxs_reg_32(hw_gis_ctrl)				/* 0x00 */
+	mxs_reg_32(hw_gis_config0)			/* 0x10 */
+	mxs_reg_32(hw_gis_config1)			/* 0x20 */
+	mxs_reg_32(hw_gis_fb0)				/* 0x30 */
+	mxs_reg_32(hw_gis_fb1)				/* 0x40 */
+	mxs_reg_32(hw_gis_pxp_fb0)			/* 0x50 */
+	mxs_reg_32(hw_gis_pxp_fb1)			/* 0x60 */
+
+	mxs_reg_32(hw_gis_ch0_ctrl)			/* 0x70 */
+	mxs_reg_32(hw_gis_ch0_addr0)		/* 0x80 */
+	mxs_reg_32(hw_gis_ch0_data0)		/* 0x90 */
+	mxs_reg_32(hw_gis_ch0_addr1)		/* 0xa0 */
+	mxs_reg_32(hw_gis_ch0_data1)		/* 0xb0 */
+	mxs_reg_32(hw_gis_ch0_addr2)		/* 0xc0 */
+	mxs_reg_32(hw_gis_ch0_data2)		/* 0xd0 */
+	mxs_reg_32(hw_gis_ch0_addr3)		/* 0xe0 */
+	mxs_reg_32(hw_gis_ch0_data3)		/* 0xf0 */
+
+	mxs_reg_32(hw_gis_ch1_ctrl)			/* 0x100 */
+	mxs_reg_32(hw_gis_ch1_addr0)		/* 0x110 */
+	mxs_reg_32(hw_gis_ch1_data0)		/* 0x120 */
+	mxs_reg_32(hw_gis_ch1_addr1)		/* 0x130 */
+	mxs_reg_32(hw_gis_ch1_data1)		/* 0x140 */
+	mxs_reg_32(hw_gis_ch1_addr2)		/* 0x150 */
+	mxs_reg_32(hw_gis_ch1_data2)		/* 0x160 */
+	mxs_reg_32(hw_gis_ch1_addr3)		/* 0x170 */
+	mxs_reg_32(hw_gis_ch1_data3)		/* 0x180 */
+
+	mxs_reg_32(hw_gis_ch2_ctrl)			/* 0x190 */
+	mxs_reg_32(hw_gis_ch2_addr0)		/* 0x1a0 */
+	mxs_reg_32(hw_gis_ch2_data0)		/* 0x1b0 */
+	mxs_reg_32(hw_gis_ch2_addr1)		/* 0x1c0 */
+	mxs_reg_32(hw_gis_ch2_data1)		/* 0x1d0 */
+	mxs_reg_32(hw_gis_ch2_addr2)		/* 0x1e0 */
+	mxs_reg_32(hw_gis_ch2_data2)		/* 0x1f0 */
+	mxs_reg_32(hw_gis_ch2_addr3)		/* 0x200 */
+	mxs_reg_32(hw_gis_ch2_data3)		/* 0x210 */
+
+	mxs_reg_32(hw_gis_ch3_ctrl)			/* 0x220 */
+	mxs_reg_32(hw_gis_ch3_addr0)		/* 0x230 */
+	mxs_reg_32(hw_gis_ch3_data0)		/* 0x240 */
+	mxs_reg_32(hw_gis_ch3_addr1)		/* 0x250 */
+	mxs_reg_32(hw_gis_ch3_data1)		/* 0x260 */
+	mxs_reg_32(hw_gis_ch3_addr2)		/* 0x270 */
+	mxs_reg_32(hw_gis_ch3_data2)		/* 0x280 */
+	mxs_reg_32(hw_gis_ch3_addr3)		/* 0x290 */
+	mxs_reg_32(hw_gis_ch3_data3)		/* 0x2a0 */
+
+	mxs_reg_32(hw_gis_ch4_ctrl)			/* 0x2b0 */
+	mxs_reg_32(hw_gis_ch4_addr0)		/* 0x2c0 */
+	mxs_reg_32(hw_gis_ch4_data0)		/* 0x2d0 */
+	mxs_reg_32(hw_gis_ch4_addr1)		/* 0x2e0 */
+	mxs_reg_32(hw_gis_ch4_data1)		/* 0x2f0 */
+	mxs_reg_32(hw_gis_ch4_addr2)		/* 0x300 */
+	mxs_reg_32(hw_gis_ch4_data2)		/* 0x310 */
+	mxs_reg_32(hw_gis_ch4_addr3)		/* 0x320 */
+	mxs_reg_32(hw_gis_ch4_data3)		/* 0x330 */
+
+	mxs_reg_32(hw_gis_ch5_ctrl)			/* 0x340 */
+	mxs_reg_32(hw_gis_ch5_addr0)		/* 0x350 */
+	mxs_reg_32(hw_gis_ch5_data0)		/* 0x360 */
+	mxs_reg_32(hw_gis_ch5_addr1)		/* 0x370 */
+	mxs_reg_32(hw_gis_ch5_data1)		/* 0x380 */
+	mxs_reg_32(hw_gis_ch5_addr2)		/* 0x390 */
+	mxs_reg_32(hw_gis_ch5_data2)		/* 0x3a0 */
+	mxs_reg_32(hw_gis_ch5_addr3)		/* 0x3b0 */
+	mxs_reg_32(hw_gis_ch5_data3)		/* 0x3c0 */
+
+	mxs_reg_32(hw_gis_debug0)			/* 0x3d0 */
+	mxs_reg_32(hw_gis_debug1)			/* 0x3e0 */
+	mxs_reg_32(hw_gis_version)			/* 0x3f0 */
+};
+
+/* register bit */
+#define GIS_CTRL_SFTRST_CLR				0
+#define GIS_CTRL_SFTRST_SET				(1 << 31)
+#define GIS_CTRL_CLK_GATE_CLR			0
+#define GIS_CTRL_CLK_GATE_SET			(1 << 30)
+#define GIS_CTRL_LCDIF1_IRQ_POL_LOW		0
+#define GIS_CTRL_LCDIF1_IRQ_POL_HIGH	(1 << 8)
+#define GIS_CTRL_LCDIF0_IRQ_POL_LOW		0
+#define GIS_CTRL_LCDIF0_IRQ_POL_HIGH	(1 << 7)
+#define GIS_CTRL_PXP_IRQ_POL_LOW		0
+#define GIS_CTRL_PXP_IRQ_POL_HIGH		(1 << 6)
+#define GIS_CTRL_CSI1_IRQ_POL_LOW		0
+#define GIS_CTRL_CSI1_IRQ_POL_HIGH		(1 << 5)
+#define GIS_CTRL_CSI0_IRQ_POL_LOW		0
+#define GIS_CTRL_CSI0_IRQ_POL_HIGH		(1 << 4)
+#define GIS_CTRL_CSI_SEL_CSI0			0
+#define GIS_CTRL_CSI_SEL_CSI1			(1 << 3)
+#define GIS_CTRL_LCDIF_SEL_LCDIF0		0
+#define GIS_CTRL_LCDIF_SEL_LCDIF1		(1 << 2)
+#define GIS_CTRL_FB_START_FB0			0
+#define GIS_CTRL_FB_START_FB1			(1 << 1)
+#define GIS_CTRL_ENABLE_CLR				0
+#define GIS_CTRL_ENABLE_SET				(1 << 0)
+
+#define GIS_CONFIG0_CH3_NUM_MASK		(0x7 << 27)
+#define GIS_CONFIG0_CH3_NUM_SHIFT		27
+#define GIS_CONFIG0_CH3_MAPPING_MASK	(0x7 << 24)
+#define GIS_CONFIG0_CH3_MAPPING_SHIFT	24
+#define GIS_CONFIG0_CH2_NUM_MASK		(0x7 << 19)
+#define GIS_CONFIG0_CH2_NUM_SHIFT		19
+#define GIS_CONFIG0_CH2_MAPPING_MASK	(0x7 << 16)
+#define GIS_CONFIG0_CH2_MAPPING_SHIFT	16
+#define GIS_CONFIG0_CH1_NUM_MASK		(0x7 << 11)
+#define GIS_CONFIG0_CH1_NUM_SHIFT		11
+#define GIS_CONFIG0_CH1_MAPPING_MASK	(0x7 << 8)
+#define GIS_CONFIG0_CH1_MAPPING_SHIFT	8
+#define GIS_CONFIG0_CH0_NUM_MASK		(0x7 << 3)
+#define GIS_CONFIG0_CH0_NUM_SHIFT		3
+#define GIS_CONFIG0_CH0_MAPPING_MASK	(0x7 << 0)
+#define GIS_CONFIG0_CH0_MAPPING_SHIFT	0
+
+#define GIS_CONFIG1_CH5_NUM_MASK		(0x7 << 11)
+#define GIS_CONFIG1_CH5_NUM_SHIFT		11
+#define GIS_CONFIG1_CH5_MAPPING_MASK	(0x7 << 8)
+#define GIS_CONFIG1_CH5_MAPPING_SHIFT	8
+#define GIS_CONFIG1_CH4_NUM_MASK		(0x7 << 3)
+#define GIS_CONFIG1_CH4_NUM_SHIFT		3
+#define GIS_CONFIG1_CH4_MAPPING_MASK	(0x7 << 0)
+#define GIS_CONFIG1_CH4_MAPPING_SHIFT	0
+
+#define GIS_CH_CTRL_CMD3_ACC_MASK		(0x1 << 31)
+#define GIS_CH_CTRL_CMD3_ACC_SHIFT		31
+#define GIS_CH_CTRL_CMD3_ALU_MASK		(0x7 << 28)
+#define GIS_CH_CTRL_CMD3_ALU_SHIFT		28
+#define GIS_CH_CTRL_CMD3_OPCODE_MASK	(0xF << 24)
+#define GIS_CH_CTRL_CMD3_OPCODE_SHIFT	24
+#define GIS_CH_CTRL_CMD2_ACC_MASK		(0x1 << 23)
+#define GIS_CH_CTRL_CMD2_ACC_SHIFT		23
+#define GIS_CH_CTRL_CMD2_ALU_MASK		(0xF << 20)
+#define GIS_CH_CTRL_CMD2_ALU_SHIFT		20
+#define GIS_CH_CTRL_CMD2_OPCODE_MASK	(0xF << 16)
+#define GIS_CH_CTRL_CMD2_OPCODE_SHIFT	16
+#define GIS_CH_CTRL_CMD1_ACC_MASK		(0x1 << 15)
+#define GIS_CH_CTRL_CMD1_ACC_SHIFT		15
+#define GIS_CH_CTRL_CMD1_ALU_MASK		(0x7 << 12)
+#define GIS_CH_CTRL_CMD1_ALU_SHIFT		12
+#define GIS_CH_CTRL_CMD1_OPCODE_MASK	(0xF << 8)
+#define GIS_CH_CTRL_CMD1_OPCODE_SHIFT	8
+#define GIS_CH_CTRL_CMD0_ACC_MASK		(0x1 << 7)
+#define GIS_CH_CTRL_CMD0_ACC_SHIFT		7
+#define GIS_CH_CTRL_CMD0_ALU_MASK		(0x7 << 4)
+#define GIS_CH_CTRL_CMD0_ALU_SHIFT		4
+#define GIS_CH_CTRL_CMD0_OPCODE_MASK	(0xF << 0)
+#define GIS_CH_CTRL_CMD0_OPCODE_SHIFT	0
+
+#define GIS_CH_CTRL_CMD_ACC_NO_NEGATE	0
+#define GIS_CH_CTRL_CMD_ACC_NEGATE		1
+
+#define GIS_CH_ADDR_SEL_MASK			(0xF8 << 27)
+#define GIS_CH_ADDR_SEL_LCDIF1			(0x1 << 31)
+#define GIS_CH_ADDR_SEL_LCDIF0			(0x1 << 30)
+#define GIS_CH_ADDR_SEL_PXP				(0x1 << 29)
+#define GIS_CH_ADDR_SEL_CSI1			(0x1 << 28)
+#define GIS_CH_ADDR_SEL_CSI0			(0x1 << 27)
+#define GIS_CH_ADDR_SEL_SHIFT			27
+#define GIS_CH_ADDR_ADDR_MASK			0x7FFFFFF
+#define GIS_CH_ADDR_ADDR_SHIFT			0
+
+#endif
+
diff --git a/drivers/video/mxc_pxp.c b/drivers/video/mxc_pxp.c
new file mode 100644
index 00000000000..41cedfc98ca
--- /dev/null
+++ b/drivers/video/mxc_pxp.c
@@ -0,0 +1,208 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ */
+
+#include <common.h>
+
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+
+#include <linux/string.h>
+#include <linux/list.h>
+#include <gis.h>
+
+#include "mxc_pxp.h"
+
+#define BV_PXP_OUT_CTRL_FORMAT__RGB888	  0x4
+#define BV_PXP_OUT_CTRL_FORMAT__RGB555	  0xC
+#define BV_PXP_OUT_CTRL_FORMAT__RGB444	  0xD
+#define BV_PXP_OUT_CTRL_FORMAT__RGB565	  0xE
+#define BV_PXP_OUT_CTRL_FORMAT__YUV1P444  0x10
+#define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12
+#define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13
+
+#define BV_PXP_PS_CTRL_FORMAT__RGB888	 0x4
+#define BV_PXP_PS_CTRL_FORMAT__RGB565	 0xE
+#define BV_PXP_PS_CTRL_FORMAT__YUV1P444  0x10
+#define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12
+#define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13
+
+#define BP_PXP_PS_CTRL_SWAP 5
+#define BM_PXP_PS_CTRL_SWAP 0x000000E0
+#define BF_PXP_PS_CTRL_SWAP(v)  \
+	(((v) << 5) & BM_PXP_PS_CTRL_SWAP)
+
+#define PXP_DOWNSCALE_THRESHOLD     0x4000
+
+static void pxp_set_ctrl(struct pxp_config_data *pxp_conf)
+{
+	u32 ctrl;
+	u32 fmt_ctrl;
+	int need_swap = 0;   /* to support YUYV and YVYU formats */
+	struct mxs_pxp_regs *regs = (struct mxs_pxp_regs *)PXP_BASE_ADDR;
+
+	/* Configure S0 input format */
+	switch (pxp_conf->s0_param.pixel_fmt) {
+	case FMT_YUV444:
+		fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV1P444;
+		break;
+	case FMT_UYVY:
+		fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422;
+		break;
+	case FMT_YUYV:
+		fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422;
+		need_swap = 1;
+		break;
+	default:
+		fmt_ctrl = 0;
+	}
+
+	ctrl = BF_PXP_PS_CTRL_FORMAT(fmt_ctrl) | BF_PXP_PS_CTRL_SWAP(need_swap);
+	writel(ctrl, &regs->pxp_ps_ctrl);
+
+	/* Configure output format based on out_channel format */
+	switch (pxp_conf->out_param.pixel_fmt) {
+	case FMT_RGB565:
+		fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB565;
+		break;
+	case FMT_RGB888:
+		fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888;
+		break;
+	default:
+		fmt_ctrl = 0;
+	}
+
+	ctrl = BF_PXP_OUT_CTRL_FORMAT(fmt_ctrl);
+	writel(ctrl, &regs->pxp_out_ctrl);
+}
+
+static int pxp_set_scaling(struct pxp_config_data *pxp_conf)
+{
+	int ret = 0;
+	u32 xscale, yscale, s0scale;
+	u32 decx, decy, xdec = 0, ydec = 0;
+	struct pxp_layer_param *s0_params = &pxp_conf->s0_param;
+	struct pxp_layer_param *out_params = &pxp_conf->out_param;
+	struct mxs_pxp_regs *regs = (struct mxs_pxp_regs *)PXP_BASE_ADDR;
+
+	decx = s0_params->width / out_params->width;
+	decy = s0_params->height / out_params->height;
+	if (decx > 1) {
+		if (decx >= 2 && decx < 4) {
+			decx = 2;
+			xdec = 1;
+		} else if (decx >= 4 && decx < 8) {
+			decx = 4;
+			xdec = 2;
+		} else if (decx >= 8) {
+			decx = 8;
+			xdec = 3;
+		}
+		xscale = s0_params->width * 0x1000 /
+			 (out_params->width * decx);
+	} else {
+		if ((s0_params->pixel_fmt == FMT_YUYV) ||
+		    (s0_params->pixel_fmt == FMT_UYVY) ||
+		    (s0_params->pixel_fmt == FMT_YUV444))
+			xscale = (s0_params->width - 1) * 0x1000 /
+				 (out_params->width - 1);
+		else
+			xscale = (s0_params->width - 2) * 0x1000 /
+				 (out_params->width - 1);
+	}
+	if (decy > 1) {
+		if (decy >= 2 && decy < 4) {
+			decy = 2;
+			ydec = 1;
+		} else if (decy >= 4 && decy < 8) {
+			decy = 4;
+			ydec = 2;
+		} else if (decy >= 8) {
+			decy = 8;
+			ydec = 3;
+		}
+		yscale = s0_params->height * 0x1000 /
+			 (out_params->height * decy);
+	} else
+		yscale = (s0_params->height - 1) * 0x1000 /
+			 (out_params->height - 1);
+
+	writel((xdec << 10) | (ydec << 8), &regs->pxp_ps_ctrl);
+
+	if (xscale > PXP_DOWNSCALE_THRESHOLD)
+		xscale = PXP_DOWNSCALE_THRESHOLD;
+	if (yscale > PXP_DOWNSCALE_THRESHOLD)
+		yscale = PXP_DOWNSCALE_THRESHOLD;
+	s0scale = BF_PXP_PS_SCALE_YSCALE(yscale) |
+		BF_PXP_PS_SCALE_XSCALE(xscale);
+	writel(s0scale, &regs->pxp_ps_scale);
+
+	pxp_set_ctrl(pxp_conf);
+
+	return ret;
+}
+
+void pxp_power_down(void)
+{
+	struct mxs_pxp_regs *regs = (struct mxs_pxp_regs *)PXP_BASE_ADDR;
+	u32 val;
+
+	val = BM_PXP_CTRL_SFTRST | BM_PXP_CTRL_CLKGATE;
+	writel(val , &regs->pxp_ctrl);
+}
+
+void pxp_config(struct pxp_config_data *pxp_conf)
+{
+	struct mxs_pxp_regs *regs = (struct mxs_pxp_regs *)PXP_BASE_ADDR;
+
+	/* reset */
+	mxs_reset_block(&regs->pxp_ctrl_reg);
+
+	/* output buffer */
+	if (pxp_conf->out_param.pixel_fmt == FMT_RGB888)
+		writel(BV_PXP_OUT_CTRL_FORMAT__RGB888, &regs->pxp_out_ctrl);
+	else
+		writel(BV_PXP_OUT_CTRL_FORMAT__RGB565, &regs->pxp_out_ctrl);
+
+	writel((u32)pxp_conf->out_param.paddr, &regs->pxp_out_buf);
+
+	writel(pxp_conf->out_param.stride, &regs->pxp_out_pitch);
+	writel((pxp_conf->out_param.width - 1) << 16 |
+			(pxp_conf->out_param.height - 1),
+			&regs->pxp_out_lrc);
+
+	/* scale needed  */
+	writel(0, &regs->pxp_out_ps_ulc);
+	writel((pxp_conf->out_param.width - 1) << 16 |
+			(pxp_conf->out_param.height - 1),
+			&regs->pxp_out_ps_lrc);
+	pxp_set_scaling(pxp_conf);
+
+	writel(0, &regs->pxp_out_as_ulc);
+	writel(0, &regs->pxp_out_as_lrc);
+
+	/* input buffer */
+	if (pxp_conf->s0_param.pixel_fmt == FMT_YUV444)
+		writel(BV_PXP_PS_CTRL_FORMAT__YUV1P444, &regs->pxp_ps_ctrl);
+	else if (pxp_conf->s0_param.pixel_fmt == FMT_YUYV)
+		writel(BV_PXP_PS_CTRL_FORMAT__UYVY1P422 | BF_PXP_PS_CTRL_SWAP(1),
+				&regs->pxp_ps_ctrl);
+	else if (pxp_conf->s0_param.pixel_fmt == FMT_UYVY)
+		writel(BV_PXP_PS_CTRL_FORMAT__UYVY1P422, &regs->pxp_ps_ctrl);
+	else
+		printf("%s, unsupport fmt\n", __func__);
+
+	writel((u32)pxp_conf->s0_param.paddr, &regs->pxp_ps_buf);
+	writel(pxp_conf->s0_param.stride, &regs->pxp_ps_pitch);
+	writel(0, &regs->pxp_ps_background);
+	writel(0x84ab01f0, &regs->pxp_csc1_coef0);
+	writel(0x01980204, &regs->pxp_csc1_coef1);
+	writel(0x0730079c, &regs->pxp_csc1_coef2);
+
+	/* pxp start  */
+	writel(BM_PXP_CTRL_IRQ_ENABLE | BM_PXP_CTRL_ENABLE, &regs->pxp_ctrl);
+}
diff --git a/drivers/video/mxc_pxp.h b/drivers/video/mxc_pxp.h
new file mode 100644
index 00000000000..0c50c5cec50
--- /dev/null
+++ b/drivers/video/mxc_pxp.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ */
+
+#ifndef MXC_PXP_H
+#define MXC_PXP_H
+
+#include <asm/mach-imx/regs-common.h>
+
+struct mxs_pxp_regs{
+	mxs_reg_32(pxp_ctrl)           /* 0x00  */
+	mxs_reg_32(pxp_stat)           /* 0x10  */
+	mxs_reg_32(pxp_out_ctrl)       /* 0x20  */
+	mxs_reg_32(pxp_out_buf)        /* 0x30  */
+	mxs_reg_32(pxp_out_buf2)       /* 0x40  */
+	mxs_reg_32(pxp_out_pitch)      /* 0x50  */
+	mxs_reg_32(pxp_out_lrc)        /* 0x60  */
+	mxs_reg_32(pxp_out_ps_ulc)     /* 0x70  */
+	mxs_reg_32(pxp_out_ps_lrc)     /* 0x80  */
+	mxs_reg_32(pxp_out_as_ulc)     /* 0x90  */
+	mxs_reg_32(pxp_out_as_lrc)     /* 0xa0  */
+	mxs_reg_32(pxp_ps_ctrl)        /* 0xb0  */
+	mxs_reg_32(pxp_ps_buf)         /* 0xc0  */
+	mxs_reg_32(pxp_ps_ubuf)        /* 0xd0  */
+	mxs_reg_32(pxp_ps_vbuf)        /* 0xe0  */
+	mxs_reg_32(pxp_ps_pitch)       /* 0xf0  */
+	mxs_reg_32(pxp_ps_background)  /* 0x100 */
+	mxs_reg_32(pxp_ps_scale)       /* 0x110 */
+	mxs_reg_32(pxp_ps_offset)      /* 0x120 */
+	mxs_reg_32(pxp_ps_clrkeylow)   /* 0x130 */
+	mxs_reg_32(pxp_ps_clrkeyhigh)  /* 0x140 */
+	mxs_reg_32(pxp_as_ctrl)        /* 0x150 */
+	mxs_reg_32(pxp_as_buf)         /* 0x160 */
+	mxs_reg_32(pxp_as_pitch)       /* 0x170 */
+	mxs_reg_32(pxp_as_clrkeylow)   /* 0x180 */
+	mxs_reg_32(pxp_as_clrkeyhigh)  /* 0x190 */
+	mxs_reg_32(pxp_csc1_coef0)     /* 0x1a0 */
+	mxs_reg_32(pxp_csc1_coef1)     /* 0x1b0 */
+	mxs_reg_32(pxp_csc1_coef2)     /* 0x1c0 */
+	mxs_reg_32(pxp_csc2_ctrl)      /* 0x1d0 */
+	mxs_reg_32(pxp_csc2_coef0)     /* 0x1e0 */
+	mxs_reg_32(pxp_csc2_coef1)     /* 0x1f0 */
+	mxs_reg_32(pxp_csc2_coef2)     /* 0x200 */
+	mxs_reg_32(pxp_csc2_coef3)     /* 0x210 */
+	mxs_reg_32(pxp_csc2_coef4)     /* 0x220 */
+	mxs_reg_32(pxp_csc2_coef5)     /* 0x230 */
+	mxs_reg_32(pxp_lut_ctrl)       /* 0x240 */
+	mxs_reg_32(pxp_lut_addr)       /* 0x250 */
+	mxs_reg_32(pxp_lut_data)       /* 0x260 */
+	mxs_reg_32(pxp_lut_extmem)     /* 0x270 */
+	mxs_reg_32(pxp_cfa)            /* 0x280 */
+	mxs_reg_32(pxp_hist_ctrl)      /* 0x290 */
+	mxs_reg_32(pxp_hist2_param)    /* 0x2a0 */
+	mxs_reg_32(pxp_hist4_param)    /* 0x2b0 */
+	mxs_reg_32(pxp_hist8_param0)   /* 0x2c0 */
+	mxs_reg_32(pxp_hist8_param1)   /* 0x2d0 */
+	mxs_reg_32(pxp_hist16_param0)  /* 0x2e0 */
+	mxs_reg_32(pxp_hist16_param1)  /* 0x2f0 */
+	mxs_reg_32(pxp_hist16_param2)  /* 0x300 */
+	mxs_reg_32(pxp_hist16_param3)  /* 0x310 */
+	mxs_reg_32(pxp_power)          /* 0x320 */
+	uint32_t	reserved1[4*13];
+	mxs_reg_32(pxp_next)           /* 0x400 */
+};
+
+#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002
+#define BM_PXP_CTRL_ENABLE 0x00000001
+
+#define BM_PXP_STAT_IRQ 0x00000001
+
+#define BP_PXP_OUT_CTRL_FORMAT	    0
+#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F
+#define BF_PXP_OUT_CTRL_FORMAT(v)  \
+	(((v) << 0) & BM_PXP_OUT_CTRL_FORMAT)
+
+#define HW_PXP_PS_SCALE	(0x00000110)
+
+#define BM_PXP_PS_SCALE_RSVD2 0x80000000
+#define BP_PXP_PS_SCALE_YSCALE	    16
+#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000
+#define BF_PXP_PS_SCALE_YSCALE(v)  \
+	(((v) << 16) & BM_PXP_PS_SCALE_YSCALE)
+#define BM_PXP_PS_SCALE_RSVD1 0x00008000
+#define BP_PXP_PS_SCALE_XSCALE	    0
+#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF
+#define BF_PXP_PS_SCALE_XSCALE(v)  \
+	(((v) << 0) & BM_PXP_PS_SCALE_XSCALE)
+
+#define BP_PXP_PS_CTRL_SWAP 5
+#define BM_PXP_PS_CTRL_SWAP 0x000000E0
+#define BF_PXP_PS_CTRL_SWAP(v)  \
+	(((v) << 5) & BM_PXP_PS_CTRL_SWAP)
+#define BP_PXP_PS_CTRL_FORMAT	   0
+#define BM_PXP_PS_CTRL_FORMAT 0x0000001F
+#define BF_PXP_PS_CTRL_FORMAT(v)  \
+	(((v) << 0) & BM_PXP_PS_CTRL_FORMAT)
+#define BM_PXP_CTRL_SFTRST 0x80000000
+#define BM_PXP_CTRL_CLKGATE 0x40000000
+
+struct pxp_layer_param {
+	unsigned short width;
+	unsigned short height;
+	unsigned short stride; /* aka pitch */
+	unsigned int pixel_fmt;
+	void *paddr;
+};
+
+struct pxp_config_data {
+	struct pxp_layer_param s0_param;
+	struct pxp_layer_param out_param;
+};
+
+void pxp_config(struct pxp_config_data *pxp_conf);
+
+#endif
diff --git a/drivers/video/mxc_vadc.c b/drivers/video/mxc_vadc.c
new file mode 100644
index 00000000000..4fa49c1d7a7
--- /dev/null
+++ b/drivers/video/mxc_vadc.c
@@ -0,0 +1,374 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ */
+
+#include <common.h>
+
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+
+#include <linux/string.h>
+#include <linux/list.h>
+#include <linux/delay.h>
+#include <gis.h>
+
+#include "mxc_vadc.h"
+
+#define reg32_write(addr, val) __raw_writel(val, addr)
+#define reg32_read(addr)       __raw_readl(addr)
+#define reg32setbit(addr, bitpos) \
+	reg32_write((addr), (reg32_read((addr)) | (1<<(bitpos))))
+
+#define reg32clrbit(addr, bitpos) \
+	reg32_write((addr), (reg32_read((addr)) & (0xFFFFFFFF ^ (1<<(bitpos)))))
+
+void __iomem *vafe_regbase;
+void __iomem *vdec_regbase;
+
+enum {
+	STD_NTSC = 0,
+	STD_PAL,
+};
+
+/* Video format structure. */
+struct video_fmt_t{
+	int v4l2_id;		/* Video for linux ID. */
+	char name[16];		/* Name (e.g., "NTSC", "PAL", etc.) */
+	u16 active_width;	/* Active width. */
+	u16 active_height;	/* Active height. */
+};
+
+/* Description of video formats supported.
+ *
+ *  PAL: active=720x576.
+ *  NTSC:active=720x480.
+ */
+static struct video_fmt_t video_fmts[] = {
+	/* NTSC */
+	{
+	 .v4l2_id = STD_NTSC,
+	 .name = "NTSC",
+	 .active_width = 720,
+	 .active_height = 480,
+	 },
+	/* (B, G, H, I, N) PAL */
+	{
+	 .v4l2_id = STD_PAL,
+	 .name = "PAL",
+	 .active_width = 720,
+	 .active_height = 576,
+	 },
+};
+
+static void afe_voltage_clampingmode(void)
+{
+	reg32_write(AFE_CLAMP, 0x07);
+	reg32_write(AFE_CLMPAMP, 0x60);
+	reg32_write(AFE_CLMPDAT, 0xF0);
+}
+
+static void afe_alwayson_clampingmode(void)
+{
+	reg32_write(AFE_CLAMP, 0x15);
+	reg32_write(AFE_CLMPDAT, 0x08);
+	reg32_write(AFE_CLMPAMP, 0x00);
+}
+
+static void afe_init(void)
+{
+	reg32_write(AFE_PDBUF, 0x1f);
+	reg32_write(AFE_PDADC, 0x0f);
+	reg32_write(AFE_PDSARH, 0x01);
+	reg32_write(AFE_PDSARL, 0xff);
+	reg32_write(AFE_PDADCRFH, 0x01);
+	reg32_write(AFE_PDADCRFL, 0xff);
+	reg32_write(AFE_ICTRL, 0x3a);
+	reg32_write(AFE_ICTLSTG, 0x1e);
+
+	reg32_write(AFE_RCTRLSTG, 0x1e);
+	reg32_write(AFE_INPBUF, 0x035);
+	reg32_write(AFE_INPFLT, 0x02);
+	reg32_write(AFE_ADCDGN, 0x40);
+	reg32_write(AFE_TSTSEL, 0x10);
+
+	reg32_write(AFE_ACCTST, 0x07);
+
+	reg32_write(AFE_BGREG, 0x08);
+
+	reg32_write(AFE_ADCGN, 0x09);
+
+	/* set current controlled clamping
+	* always on, low current */
+	reg32_write(AFE_CLAMP, 0x11);
+	reg32_write(AFE_CLMPAMP, 0x08);
+}
+
+static void vdec_mode_timing_init(u32 std)
+{
+	if (std == STD_NTSC) {
+		/* NTSC 720x480 */
+		printf("NTSC\n");
+		reg32_write(VDEC_HACTS, 0x66);
+		reg32_write(VDEC_HACTE, 0x24);
+
+		reg32_write(VDEC_VACTS, 0x29);
+		reg32_write(VDEC_VACTE, 0x04);
+
+		/* set V Position */
+		reg32_write(VDEC_VRTPOS, 0x2);
+	} else if (std == STD_PAL) {
+		/* PAL 720x576 */
+		printf("PAL\n");
+		reg32_write(VDEC_HACTS, 0x66);
+		reg32_write(VDEC_HACTE, 0x24);
+
+		reg32_write(VDEC_VACTS, 0x29);
+		reg32_write(VDEC_VACTE, 0x04);
+
+		/* set V Position */
+		reg32_write(VDEC_VRTPOS, 0x6);
+	} else
+		printf("Error not support video mode\n");
+
+	/* set H Position */
+	reg32_write(VDEC_HZPOS, 0x60);
+
+	/* set H ignore start */
+	reg32_write(VDEC_HSIGS, 0xf8);
+
+	/* set H ignore end */
+	reg32_write(VDEC_HSIGE, 0x18);
+}
+
+/*
+* vdec_init()
+* Initialises the VDEC registers
+* Returns: nothing
+*/
+static void vdec_init(struct sensor_data *vadc)
+{
+	/* Get work mode PAL or NTSC
+	 * delay 500ms wait vdec detect input format*/
+	udelay(500*1000);
+	vadc_get_std(vadc);
+
+	vdec_mode_timing_init(vadc->std_id);
+
+	/* vcr detect threshold high, automatic detections */
+	reg32_write(VDEC_VSCON2, 0);
+
+	reg32_write(VDEC_BASE + 0x110, 0x01);
+
+	/* set the noramp mode on the Hloop PLL. */
+	reg32_write(VDEC_BASE+(0x14*4), 0x10);
+
+	/* set the YC relative delay.*/
+	reg32_write(VDEC_YCDEL, 0x90);
+
+	/* setup the Hpll */
+	reg32_write(VDEC_BASE+(0x13*4), 0x13);
+
+	/* setup the 2d comb */
+	/* set the gain of the Hdetail output to 3
+	 * set the notch alpha gain to 1 */
+	reg32_write(VDEC_CFC2, 0x34);
+
+	/* setup various 2d comb bits.*/
+	reg32_write(VDEC_BASE+(0x02*4), 0x01);
+	reg32_write(VDEC_BASE+(0x03*4), 0x18);
+	reg32_write(VDEC_BASE+(0x04*4), 0x34);
+
+	/* set the start of the burst gate */
+	reg32_write(VDEC_BRSTGT, 0x30);
+
+	/* set 1f motion gain */
+	reg32_write(VDEC_BASE+(0x0f*4), 0x20);
+
+	/* set the 1F chroma motion detector thresh for colour reverse detection */
+	reg32_write(VDEC_THSH1, 0x02);
+	reg32_write(VDEC_BASE+(0x4a*4), 0x20);
+	reg32_write(VDEC_BASE+(0x4b*4), 0x08);
+
+	reg32_write(VDEC_BASE+(0x4c*4), 0x08);
+
+	/* set the threshold for the narrow/wide adaptive chroma BW */
+	reg32_write(VDEC_BASE+(0x20*4), 0x20);
+
+	/* turn up the colour with the new colour gain reg */
+	/* hue: */
+	reg32_write(VDEC_HUE, 0x00);
+
+	/* cbgain: 22 B4 */
+	reg32_write(VDEC_CBGN, 0xb4);
+	/* cr gain 80 */
+	reg32_write(VDEC_CRGN, 0x80);
+	/* luma gain (contrast) */
+	reg32_write(VDEC_CNTR, 0x80);
+
+	/* setup the signed black level register, brightness */
+	reg32_write(VDEC_BRT, 0x00);
+
+	/* filter the standard detection
+	 * enable the comb for the ntsc443 */
+	reg32_write(VDEC_STDDBG, 0x23);
+
+	/* setup chroma kill thresh for no chroma */
+	reg32_write(VDEC_CHBTH, 0x0);
+
+	/* set chroma loop to wider BW
+	 * no set it to normal BW. i fixed the bw problem.*/
+	reg32_write(VDEC_YCDEL, 0x00);
+
+	/* set the compensation in the chroma loop for the Hloop
+	 * set the ratio for the nonarithmetic 3d comb modes.*/
+	reg32_write(VDEC_BASE + (0x1d*4), 0x90);
+
+	/* set the threshold for the nonarithmetic mode for the 2d comb
+	 * the higher the value the more Fc Fh offset we will tolerate before turning off the comb. */
+	reg32_write(VDEC_BASE + (0x33*4), 0xa0);
+
+	/* setup the bluescreen output colour */
+	reg32_write(VDEC_BASE + (0x3d*4), 35);
+	reg32_write(VDEC_BLSCRCR, 114);
+	reg32_write(VDEC_BLSCRCB, 212);
+
+	/* disable the active blanking */
+	reg32_write(VDEC_BASE + (0x15*4), 0x02);
+
+	/* setup the luma agc for automatic gain. */
+	reg32_write(VDEC_LMAGC2, 0x5e);
+	reg32_write(VDEC_BASE + (0x40*4), 0x81);
+
+	/* setup chroma agc */
+	reg32_write(VDEC_CHAGC2, 0xa0);
+	reg32_write(VDEC_CHAGC1, 0x01);
+
+	/* setup the MV thresh lower nibble
+	 * setup the sync top cap, upper nibble */
+	reg32_write(VDEC_BASE + (0x3a*4), 0x80);
+	reg32_write(VDEC_SHPIMP, 0x00);
+
+	/* setup the vsync block */
+	reg32_write(VDEC_VSCON1, 0x87);
+
+	/* set the nosignal threshold
+	 * set the vsync threshold */
+	reg32_write(VDEC_VSSGTH, 0x35);
+
+	/* set length for min hphase filter (or saturate limit if saturate is chosen) */
+	reg32_write(VDEC_BASE + (0x45*4), 0x40);
+
+	/* enable the internal resampler,
+	 * select min filter not saturate for hphase noise filter for vcr detect.
+	 * enable vcr pause mode different field lengths */
+	reg32_write(VDEC_BASE + (0x46*4), 0x90);
+
+	/* disable VCR detection, lock to the Hsync rather than the Vsync */
+	reg32_write(VDEC_VSCON2, 0x04);
+
+	/* set tiplevel goal for dc clamp. */
+	reg32_write(VDEC_BASE + (0x3c*4), 0xB0);
+
+	/* override SECAM detection and force SECAM off */
+	reg32_write(VDEC_BASE + (0x2f*4), 0x20);
+
+	/* Set r3d_hardblend in 3D control2 reg */
+	reg32_write(VDEC_BASE + (0x0c*4), 0x04);
+}
+
+/* set Input selector & input pull-downs */
+static void vadc_select_input(int vadc_in)
+{
+	switch (vadc_in) {
+	case 0:
+		reg32_write(AFE_INPFLT, 0x02);
+		reg32_write(AFE_OFFDRV, 0x00);
+		reg32_write(AFE_INPCONFIG, 0x1e);
+		break;
+	case 1:
+		reg32_write(AFE_INPFLT, 0x02);
+		reg32_write(AFE_OFFDRV, 0x00);
+		reg32_write(AFE_INPCONFIG, 0x2d);
+		break;
+	case 2:
+		reg32_write(AFE_INPFLT, 0x02);
+		reg32_write(AFE_OFFDRV, 0x00);
+		reg32_write(AFE_INPCONFIG, 0x4b);
+		break;
+	case 3:
+		reg32_write(AFE_INPFLT, 0x02);
+		reg32_write(AFE_OFFDRV, 0x00);
+		reg32_write(AFE_INPCONFIG, 0x87);
+		break;
+	default:
+		printf("error video input %d\n", vadc_in);
+	}
+}
+
+/*!
+ * Return attributes of current video standard.
+ * Since this device autodetects the current standard, this function also
+ * sets the values that need to be changed if the standard changes.
+ * There is no set std equivalent function.
+ *
+ *  @return		None.
+ */
+void vadc_get_std(struct sensor_data *vadc)
+{
+	int tmp;
+	int idx;
+
+	/* Read PAL mode detected result */
+	tmp = reg32_read(VDEC_VIDMOD);
+	tmp &= (VDEC_VIDMOD_PAL_MASK | VDEC_VIDMOD_M625_MASK);
+
+	if (tmp)
+		idx = STD_PAL;
+	else
+		idx = STD_NTSC;
+
+	vadc->std_id = idx;
+	vadc->pixel_fmt = FMT_YUV444;
+	vadc->width = video_fmts[idx].active_width;
+	vadc->height = video_fmts[idx].active_height;
+}
+
+void vadc_config(u32 vadc_in)
+{
+	struct sensor_data vadc;
+
+	/* map vafe,vdec,gpr,gpc address  */
+	vafe_regbase = (u32 *)VADC_BASE_ADDR;
+	vdec_regbase = (u32 *)VDEC_BASE_ADDR;
+
+	vadc_power_up();
+
+	/* clock config for vadc */
+	reg32_write(VDEC_BASE + 0x320, 0xe3);
+	reg32_write(VDEC_BASE + 0x324, 0x38);
+	reg32_write(VDEC_BASE + 0x328, 0x8e);
+	reg32_write(VDEC_BASE + 0x32c, 0x23);
+	mxs_set_vadcclk();
+
+	afe_init();
+
+	/* select Video Input 0-3 */
+	vadc_select_input(vadc_in);
+
+	afe_voltage_clampingmode();
+
+	vdec_init(&vadc);
+
+	/*
+	* current control loop will move sinewave input off below
+	* the bottom of the signal range visible when the testbus is viewed as magnitude,
+	* so have to break before this point while capturing ENOB data:
+	*/
+	afe_alwayson_clampingmode();
+}
+
diff --git a/drivers/video/mxc_vadc.h b/drivers/video/mxc_vadc.h
new file mode 100644
index 00000000000..bd85975fb40
--- /dev/null
+++ b/drivers/video/mxc_vadc.h
@@ -0,0 +1,230 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ */
+
+#ifndef MXC_VADC_H
+#define MXC_VADC_H
+
+/*** define base address ***/
+#define VDEC_BASE vdec_regbase
+#define AFE_BASE vafe_regbase
+
+/* AFE - Register offsets */
+#define AFE_BLOCK_ID_OFFSET				0x00000000
+#define AFE_PDBUF_OFFSET				0x00000004
+#define AFE_SWRST_OFFSET				0x00000008
+#define AFE_TSTSEL_OFFSET				0x0000000c
+#define AFE_TSTMSC_OFFSET				0x00000010
+#define AFE_ENPADIO_OFFSET				0x00000014
+#define AFE_BGREG_OFFSET				0x00000018
+#define AFE_ACCESSAR_ID_OFFSET			0x00000400
+#define AFE_PDADC_OFFSET				0x00000404
+#define AFE_PDSARH_OFFSET				0x00000408
+#define AFE_PDSARL_OFFSET				0x0000040C
+#define AFE_PDADCRFH_OFFSET				0x00000410
+#define AFE_PDADCRFL_OFFSET				0x00000414
+#define AFE_ACCTST_OFFSET				0x00000418
+#define AFE_ADCGN_OFFSET				0x0000041C
+#define AFE_ICTRL_OFFSET				0x00000420
+#define AFE_ICTLSTG_OFFSET				0x00000424
+#define AFE_RCTRLSTG_OFFSET				0x00000428
+#define AFE_TCTRLSTG_OFFSET				0x0000042c
+#define AFE_REFMOD_OFFSET				0x00000430
+#define AFE_REFTRIML_OFFSET				0x00000434
+#define AFE_REFTRIMH_OFFSET				0x00000438
+#define AFE_ADCR_OFFSET					0x0000043c
+#define AFE_DUMMY0_OFFSET				0x00000440
+#define AFE_DUMMY1_OFFSET				0x00000444
+#define AFE_DUMMY2_OFFSET				0x00000448
+#define AFE_DACAMP_OFFSET				0x0000044c
+#define AFE_CLMPTST_OFFSET				0x00000450
+#define AFE_CLMPDAT_OFFSET				0x00000454
+#define AFE_CLMPAMP_OFFSET				0x00000458
+#define AFE_CLAMP_OFFSET				0x0000045c
+#define AFE_INPBUF_OFFSET				0x00000460
+#define AFE_INPFLT_OFFSET				0x00000464
+#define AFE_ADCDGN_OFFSET				0x00000468
+#define AFE_OFFDRV_OFFSET				0x0000046c
+#define AFE_INPCONFIG_OFFSET			0x00000470
+#define AFE_PROGDELAY_OFFSET			0x00000474
+#define AFE_ADCOMT_OFFSET				0x00000478
+#define AFE_ALGDELAY_OFFSET				0x0000047c
+#define AFE_ACC_ID_OFFSET				0x00000800
+#define AFE_ACCSTA_OFFSET				0x00000804
+#define AFE_ACCNOSLI_OFFSET				0x00000808
+#define AFE_ACCCALCON_OFFSET			0x0000080c
+#define AFE_BWEWRICTRL_OFFSET			0x00000810
+#define AFE_SELSLI_OFFSET				0x00000814
+#define AFE_SELBYT_OFFSET				0x00000818
+#define AFE_REDVAL_OFFSET				0x00000820
+#define AFE_WRIBYT_OFFSET				0x00000824
+
+/* AFE Register per module */
+#define AFE_BLOCK_ID			(AFE_BASE + AFE_BLOCK_ID_OFFSET)
+#define AFE_PDBUF				(AFE_BASE + AFE_PDBUF_OFFSET)
+#define AFE_SWRST				(AFE_BASE + AFE_SWRST_OFFSET)
+#define AFE_TSTSEL				(AFE_BASE + AFE_TSTSEL_OFFSET)
+#define AFE_TSTMSC				(AFE_BASE + AFE_TSTMSC_OFFSET)
+#define AFE_ENPADIO				(AFE_BASE + AFE_ENPADIO_OFFSET)
+#define AFE_BGREG				(AFE_BASE + AFE_BGREG_OFFSET)
+#define AFE_ACCESSAR_ID			(AFE_BASE + AFE_ACCESSAR_ID_OFFSET)
+#define AFE_PDADC				(AFE_BASE + AFE_PDADC_OFFSET)
+#define AFE_PDSARH			    (AFE_BASE + AFE_PDSARH_OFFSET)
+#define AFE_PDSARL			    (AFE_BASE + AFE_PDSARL_OFFSET)
+#define AFE_PDADCRFH			(AFE_BASE + AFE_PDADCRFH_OFFSET)
+#define AFE_PDADCRFL			(AFE_BASE + AFE_PDADCRFL_OFFSET)
+#define AFE_ACCTST				(AFE_BASE + AFE_ACCTST_OFFSET)
+#define AFE_ADCGN				(AFE_BASE + AFE_ADCGN_OFFSET)
+#define AFE_ICTRL				(AFE_BASE + AFE_ICTRL_OFFSET)
+#define AFE_ICTLSTG				(AFE_BASE + AFE_ICTLSTG_OFFSET)
+#define AFE_RCTRLSTG			(AFE_BASE + AFE_RCTRLSTG_OFFSET)
+#define AFE_TCTRLSTG			(AFE_BASE + AFE_TCTRLSTG_OFFSET)
+#define AFE_REFMOD				(AFE_BASE + AFE_REFMOD_OFFSET)
+#define AFE_REFTRIML			(AFE_BASE + AFE_REFTRIML_OFFSET)
+#define AFE_REFTRIMH			(AFE_BASE + AFE_REFTRIMH_OFFSET)
+#define AFE_ADCR				(AFE_BASE + AFE_ADCR_OFFSET)
+#define AFE_DUMMY0				(AFE_BASE + AFE_DUMMY0_OFFSET)
+#define AFE_DUMMY1				(AFE_BASE + AFE_DUMMY1_OFFSET)
+#define AFE_DUMMY2				(AFE_BASE + AFE_DUMMY2_OFFSET)
+#define AFE_DACAMP				(AFE_BASE + AFE_DACAMP_OFFSET)
+#define AFE_CLMPTST				(AFE_BASE + AFE_CLMPTST_OFFSET)
+#define AFE_CLMPDAT				(AFE_BASE + AFE_CLMPDAT_OFFSET)
+#define AFE_CLMPAMP				(AFE_BASE + AFE_CLMPAMP_OFFSET)
+#define AFE_CLAMP				(AFE_BASE + AFE_CLAMP_OFFSET)
+#define AFE_INPBUF				(AFE_BASE + AFE_INPBUF_OFFSET)
+#define AFE_INPFLT				(AFE_BASE + AFE_INPFLT_OFFSET)
+#define AFE_ADCDGN				(AFE_BASE + AFE_ADCDGN_OFFSET)
+#define AFE_OFFDRV				(AFE_BASE + AFE_OFFDRV_OFFSET)
+#define AFE_INPCONFIG			(AFE_BASE + AFE_INPCONFIG_OFFSET)
+#define AFE_PROGDELAY			(AFE_BASE + AFE_PROGDELAY_OFFSET)
+#define AFE_ADCOMT				(AFE_BASE + AFE_ADCOMT_OFFSET)
+#define AFE_ALGDELAY			(AFE_BASE + AFE_ALGDELAY_OFFSET)
+#define AFE_ACC_ID				(AFE_BASE + AFE_ACC_ID_OFFSET)
+#define AFE_ACCSTA				(AFE_BASE + AFE_ACCSTA_OFFSET)
+#define AFE_ACCNOSLI			(AFE_BASE + AFE_ACCNOSLI_OFFSET)
+#define AFE_ACCCALCON			(AFE_BASE + AFE_ACCCALCON_OFFSET)
+#define AFE_BWEWRICTRL			(AFE_BASE + AFE_BWEWRICTRL_OFFSET)
+#define AFE_SELSLI				(AFE_BASE + AFE_SELSLI_OFFSET)
+#define AFE_SELBYT				(AFE_BASE + AFE_SELBYT_OFFSET)
+#define AFE_REDVAL				(AFE_BASE + AFE_REDVAL_OFFSET)
+#define AFE_WRIBYT				(AFE_BASE + AFE_WRIBYT_OFFSET)
+
+/* VDEC - Register offsets */
+#define VDEC_CFC1_OFFSET                0x00000000
+#define VDEC_CFC2_OFFSET                0x00000004
+#define VDEC_BRSTGT_OFFSET              0x00000024
+#define VDEC_HZPOS_OFFSET               0x00000040
+#define VDEC_VRTPOS_OFFSET              0x00000044
+#define VDEC_HVSHIFT_OFFSET             0x00000054
+#define VDEC_HSIGS_OFFSET               0x00000058
+#define VDEC_HSIGE_OFFSET               0x0000005C
+#define VDEC_VSCON1_OFFSET              0x00000060
+#define VDEC_VSCON2_OFFSET              0x00000064
+#define VDEC_YCDEL_OFFSET               0x0000006C
+#define VDEC_AFTCLP_OFFSET              0x00000070
+#define VDEC_DCOFF_OFFSET               0x00000078
+#define VDEC_CSID_OFFSET                0x00000084
+#define VDEC_CBGN_OFFSET                0x00000088
+#define VDEC_CRGN_OFFSET                0x0000008C
+#define VDEC_CNTR_OFFSET                0x00000090
+#define VDEC_BRT_OFFSET                 0x00000094
+#define VDEC_HUE_OFFSET                 0x00000098
+#define VDEC_CHBTH_OFFSET               0x0000009C
+#define VDEC_SHPIMP_OFFSET              0x000000A4
+#define VDEC_CHPLLIM_OFFSET             0x000000A8
+#define VDEC_VIDMOD_OFFSET              0x000000AC
+#define VDEC_VIDSTS_OFFSET              0x000000B0
+#define VDEC_NOISE_OFFSET               0x000000B4
+#define VDEC_STDDBG_OFFSET              0x000000B8
+#define VDEC_MANOVR_OFFSET              0x000000BC
+#define VDEC_VSSGTH_OFFSET              0x000000C8
+#define VDEC_DBGFBH_OFFSET              0x000000D0
+#define VDEC_DBGFBL_OFFSET              0x000000D4
+#define VDEC_HACTS_OFFSET               0x000000D8
+#define VDEC_HACTE_OFFSET               0x000000DC
+#define VDEC_VACTS_OFFSET               0x000000E0
+#define VDEC_VACTE_OFFSET               0x000000E4
+#define VDEC_HSTIP_OFFSET               0x000000EC
+#define VDEC_BLSCRY_OFFSET              0x000000F4
+#define VDEC_BLSCRCR_OFFSET             0x000000F8
+#define VDEC_BLSCRCB_OFFSET             0x000000FC
+#define VDEC_LMAGC2_OFFSET              0x00000104
+#define VDEC_CHAGC1_OFFSET              0x00000108
+#define VDEC_CHAGC2_OFFSET              0x0000010C
+#define VDEC_MINTH_OFFSET               0x00000114
+#define VDEC_VFRQOH_OFFSET              0x0000011C
+#define VDEC_VFRQOL_OFFSET              0x00000120
+#define VDEC_THSH1_OFFSET               0x00000124
+#define VDEC_THSH2_OFFSET               0x00000128
+#define VDEC_NCHTH_OFFSET               0x0000012C
+#define VDEC_TH1F_OFFSET                0x00000130
+
+/* VDEC Register per module */
+#define VDEC_CFC1                        (VDEC_BASE + VDEC_CFC1_OFFSET)
+#define VDEC_CFC2                        (VDEC_BASE + VDEC_CFC2_OFFSET)
+#define VDEC_BRSTGT                      (VDEC_BASE + VDEC_BRSTGT_OFFSET)
+#define VDEC_HZPOS                       (VDEC_BASE + VDEC_HZPOS_OFFSET)
+#define VDEC_VRTPOS                      (VDEC_BASE + VDEC_VRTPOS_OFFSET)
+#define VDEC_HVSHIFT                     (VDEC_BASE + VDEC_HVSHIFT_OFFSET)
+#define VDEC_HSIGS                       (VDEC_BASE + VDEC_HSIGS_OFFSET)
+#define VDEC_HSIGE                       (VDEC_BASE + VDEC_HSIGE_OFFSET)
+#define VDEC_VSCON1                      (VDEC_BASE + VDEC_VSCON1_OFFSET)
+#define VDEC_VSCON2                      (VDEC_BASE + VDEC_VSCON2_OFFSET)
+#define VDEC_YCDEL                       (VDEC_BASE + VDEC_YCDEL_OFFSET)
+#define VDEC_AFTCLP                      (VDEC_BASE + VDEC_AFTCLP_OFFSET)
+#define VDEC_DCOFF                       (VDEC_BASE + VDEC_DCOFF_OFFSET)
+#define VDEC_CSID                        (VDEC_BASE + VDEC_CSID_OFFSET)
+#define VDEC_CBGN                        (VDEC_BASE + VDEC_CBGN_OFFSET)
+#define VDEC_CRGN                        (VDEC_BASE + VDEC_CRGN_OFFSET)
+#define VDEC_CNTR                        (VDEC_BASE + VDEC_CNTR_OFFSET)
+#define VDEC_BRT                         (VDEC_BASE + VDEC_BRT_OFFSET)
+#define VDEC_HUE                         (VDEC_BASE + VDEC_HUE_OFFSET)
+#define VDEC_CHBTH                       (VDEC_BASE + VDEC_CHBTH_OFFSET)
+#define VDEC_SHPIMP                      (VDEC_BASE + VDEC_SHPIMP_OFFSET)
+#define VDEC_CHPLLIM                     (VDEC_BASE + VDEC_CHPLLIM_OFFSET)
+#define VDEC_VIDMOD                      (VDEC_BASE + VDEC_VIDMOD_OFFSET)
+#define VDEC_VIDSTS                      (VDEC_BASE + VDEC_VIDSTS_OFFSET)
+#define VDEC_NOISE                       (VDEC_BASE + VDEC_NOISE_OFFSET)
+#define VDEC_STDDBG                      (VDEC_BASE + VDEC_STDDBG_OFFSET)
+#define VDEC_MANOVR                      (VDEC_BASE + VDEC_MANOVR_OFFSET)
+#define VDEC_VSSGTH                      (VDEC_BASE + VDEC_VSSGTH_OFFSET)
+#define VDEC_DBGFBH                      (VDEC_BASE + VDEC_DBGFBH_OFFSET)
+#define VDEC_DBGFBL                      (VDEC_BASE + VDEC_DBGFBL_OFFSET)
+#define VDEC_HACTS                       (VDEC_BASE + VDEC_HACTS_OFFSET)
+#define VDEC_HACTE                       (VDEC_BASE + VDEC_HACTE_OFFSET)
+#define VDEC_VACTS                       (VDEC_BASE + VDEC_VACTS_OFFSET)
+#define VDEC_VACTE                       (VDEC_BASE + VDEC_VACTE_OFFSET)
+#define VDEC_HSTIP                       (VDEC_BASE + VDEC_HSTIP_OFFSET)
+#define VDEC_BLSCRY                      (VDEC_BASE + VDEC_BLSCRY_OFFSET)
+#define VDEC_BLSCRCR                     (VDEC_BASE + VDEC_BLSCRCR_OFFSET)
+#define VDEC_BLSCRCB                     (VDEC_BASE + VDEC_BLSCRCB_OFFSET)
+#define VDEC_LMAGC2                      (VDEC_BASE + VDEC_LMAGC2_OFFSET)
+#define VDEC_CHAGC1                      (VDEC_BASE + VDEC_CHAGC1_OFFSET)
+#define VDEC_CHAGC2                      (VDEC_BASE + VDEC_CHAGC2_OFFSET)
+#define VDEC_MINTH                       (VDEC_BASE + VDEC_MINTH_OFFSET)
+#define VDEC_VFRQOH                      (VDEC_BASE + VDEC_VFRQOH_OFFSET)
+#define VDEC_VFRQOL                      (VDEC_BASE + VDEC_VFRQOL_OFFSET)
+#define VDEC_THSH1                       (VDEC_BASE + VDEC_THSH1_OFFSET)
+#define VDEC_THSH2                       (VDEC_BASE + VDEC_THSH2_OFFSET)
+#define VDEC_NCHTH                       (VDEC_BASE + VDEC_NCHTH_OFFSET)
+#define VDEC_TH1F                        (VDEC_BASE + VDEC_TH1F_OFFSET)
+
+#define VDEC_VIDMOD_M625_SHIFT            4
+#define VDEC_VIDMOD_M625_MASK             (1 << VDEC_VIDMOD_M625_SHIFT)
+
+#define VDEC_VIDMOD_PAL_SHIFT             7
+#define VDEC_VIDMOD_PAL_MASK              (1 << VDEC_VIDMOD_PAL_SHIFT)
+
+struct sensor_data {
+	u32 width;
+	u32 height;
+	u32 pixel_fmt;
+	u32 std_id;
+};
+
+void vadc_config(u32 vadc_in);
+void vadc_get_std(struct sensor_data *vadc);
+
+#endif
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index 5f85c0c3eb7..e1c22810df3 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -3,6 +3,8 @@
  * Freescale i.MX23/i.MX28 LCDIF driver
  *
  * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ *
  */
 #include <common.h>
 #include <clk.h>
@@ -16,15 +18,32 @@
 #include <malloc.h>
 #include <video.h>
 #include <video_fb.h>
-
+#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
+#include <clk.h>
+#else
 #include <asm/arch/clock.h>
+#endif
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/global_data.h>
 #include <asm/mach-imx/dma.h>
 #include <asm/io.h>
+#include <reset.h>
+#include <panel.h>
+#include <video_bridge.h>
+#include <video_link.h>
+#include <display.h>
 
 #include "videomodes.h"
+#include <linux/string.h>
+#include <linux/list.h>
+#include <linux/fb.h>
+#include <mxsfb.h>
+#include <dm/device-internal.h>
+
+#ifdef CONFIG_VIDEO_GIS
+#include <gis.h>
+#endif
 
 #define	PS2KHZ(ps)	(1000000000UL / (ps))
 #define HZ2PS(hz)	(1000000000UL / ((hz) / 1000))
@@ -57,61 +76,18 @@ __weak void mxsfb_system_setup(void)
  *	 le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
  */
 
-static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
-			 struct display_timing *timings, int bpp)
+static void mxs_lcd_init(phys_addr_t reg_base, u32 fb_addr,
+			 struct display_timing *timings, int bpp, bool bridge)
 {
-	struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+	struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)(reg_base);
 	const enum display_flags flags = timings->flags;
 	uint32_t word_len = 0, bus_width = 0;
 	uint8_t valid_data = 0;
 	uint32_t vdctrl0;
 
-#if CONFIG_IS_ENABLED(CLK)
-	struct clk clk;
-	int ret;
-
-	ret = clk_get_by_name(dev, "pix", &clk);
-	if (ret) {
-		dev_err(dev, "Failed to get mxs pix clk: %d\n", ret);
-		return;
-	}
-
-	ret = clk_set_rate(&clk, timings->pixelclock.typ);
-	if (ret < 0) {
-		dev_err(dev, "Failed to set mxs pix clk: %d\n", ret);
-		return;
-	}
-
-	ret = clk_enable(&clk);
-	if (ret < 0) {
-		dev_err(dev, "Failed to enable mxs pix clk: %d\n", ret);
-		return;
-	}
-
-	ret = clk_get_by_name(dev, "axi", &clk);
-	if (ret < 0) {
-		debug("%s: Failed to get mxs axi clk: %d\n", __func__, ret);
-	} else {
-		ret = clk_enable(&clk);
-		if (ret < 0) {
-			dev_err(dev, "Failed to enable mxs axi clk: %d\n", ret);
-			return;
-		}
-	}
-
-	ret = clk_get_by_name(dev, "disp_axi", &clk);
-	if (ret < 0) {
-		debug("%s: Failed to get mxs disp_axi clk: %d\n", __func__, ret);
-	} else {
-		ret = clk_enable(&clk);
-		if (ret < 0) {
-			dev_err(dev, "Failed to enable mxs disp_axi clk: %d\n", ret);
-			return;
-		}
-	}
-#else
+#if !(CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8))
 	/* Kick in the LCDIF clock */
-	mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
+	mxs_set_lcdclk((u32)reg_base, timings->pixelclock.typ / 1000);
 #endif
 
 	/* Restart the LCDIF block */
@@ -147,12 +123,15 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
 	writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
 		&regs->hw_lcdif_ctrl1);
 
+	if (bridge)
+		writel(LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16, &regs->hw_lcdif_ctrl2);
+
 	mxsfb_system_setup();
 
 	writel((timings->vactive.typ << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
 		timings->hactive.typ, &regs->hw_lcdif_transfer_count);
 
-	vdctrl0 = LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
+	vdctrl0 = LCDIF_VDCTRL0_ENABLE_PRESENT |
 		  LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
 		  LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
 		  timings->vsync_len.typ;
@@ -199,11 +178,11 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
 	writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
 }
 
-static int mxs_probe_common(struct udevice *dev, struct display_timing *timings,
-			    int bpp, u32 fb)
+static int mxs_probe_common(phys_addr_t reg_base, struct display_timing *timings,
+			    int bpp, u32 fb, bool bridge)
 {
 	/* Start framebuffer */
-	mxs_lcd_init(dev, fb, timings, bpp);
+	mxs_lcd_init(reg_base, fb, timings, bpp, bridge);
 
 #ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
 	/*
@@ -214,7 +193,7 @@ static int mxs_probe_common(struct udevice *dev, struct display_timing *timings,
 	 * sets the RUN bit, then waits until it gets cleared and repeats this
 	 * infinitelly. This way, we get smooth continuous updates of the LCD.
 	 */
-	struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+	struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)reg_base;
 
 	memset(&desc, 0, sizeof(struct mxs_dma_desc));
 	desc.address = (dma_addr_t)&desc;
@@ -231,11 +210,16 @@ static int mxs_probe_common(struct udevice *dev, struct display_timing *timings,
 	return 0;
 }
 
-static int mxs_remove_common(u32 fb)
+static int mxs_remove_common(phys_addr_t reg_base, u32 fb)
 {
-	struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+	struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)(reg_base);
 	int timeout = 1000000;
 
+	if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
+		if (check_module_fused(MODULE_LCDIF))
+			return -ENODEV;
+	}
+
 	if (!fb)
 		return -EINVAL;
 
@@ -256,10 +240,34 @@ static int mxs_remove_common(u32 fb)
 #ifndef CONFIG_DM_VIDEO
 
 static GraphicDevice panel;
+static int setup;
+static struct fb_videomode fbmode;
+static int depth;
+
+int mxs_lcd_panel_setup(struct fb_videomode mode, int bpp,
+	uint32_t base_addr)
+{
+	fbmode = mode;
+	depth  = bpp;
+	panel.isaBase  = base_addr;
+
+	setup = 1;
+
+	return 0;
+}
+
+void mxs_lcd_get_panel(struct display_panel *dispanel)
+{
+	dispanel->width = fbmode.xres;
+	dispanel->height = fbmode.yres;
+	dispanel->reg_base = panel.isaBase;
+	dispanel->gdfindex = panel.gdfIndex;
+	dispanel->gdfbytespp = panel.gdfBytesPP;
+}
 
 void lcdif_power_down(void)
 {
-	mxs_remove_common(panel.frameAdrs);
+	mxs_remove_common(panel.isaBase, panel.frameAdrs);
 }
 
 void *video_hw_init(void)
@@ -273,15 +281,41 @@ void *video_hw_init(void)
 
 	puts("Video: ");
 
-	/* Suck display configuration from "videomode" variable */
-	penv = env_get("videomode");
-	if (!penv) {
-		puts("MXSFB: 'videomode' variable not set!\n");
-		return NULL;
+	if (!setup) {
+
+		/* Suck display configuration from "videomode" variable */
+		penv = env_get("videomode");
+		if (!penv) {
+			printf("MXSFB: 'videomode' variable not set!\n");
+			return NULL;
+		}
+
+		bpp = video_get_params(&mode, penv);
+		panel.isaBase  = MXS_LCDIF_BASE;
+	} else {
+		mode.xres = fbmode.xres;
+		mode.yres = fbmode.yres;
+		mode.pixclock = fbmode.pixclock;
+		mode.left_margin = fbmode.left_margin;
+		mode.right_margin = fbmode.right_margin;
+		mode.upper_margin = fbmode.upper_margin;
+		mode.lower_margin = fbmode.lower_margin;
+		mode.hsync_len = fbmode.hsync_len;
+		mode.vsync_len = fbmode.vsync_len;
+		mode.sync = fbmode.sync;
+		mode.vmode = fbmode.vmode;
+		bpp = depth;
 	}
 
-	bpp = video_get_params(&mode, penv);
+	mode.pixclock_khz = PS2KHZ(mode.pixclock);
+	mode.pixclock = mode.pixclock_khz * 1000;
 
+	if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
+		if (check_module_fused(MODULE_LCDIF)) {
+			printf("LCDIF@0x%x is fused, disable it\n", MXS_LCDIF_BASE);
+			return NULL;
+		}
+	}
 	/* fill in Graphic device struct */
 	sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
 
@@ -327,11 +361,17 @@ void *video_hw_init(void)
 	printf("%s\n", panel.modeIdent);
 
 	video_ctfb_mode_to_display_timing(&mode, &timings);
+	timings.flags |= DISPLAY_FLAGS_DE_HIGH; /* Force enable pol */
 
-	ret = mxs_probe_common(NULL, &timings, bpp, (u32)fb);
+	ret = mxs_probe_common(panel.isaBase, &timings, bpp, (u32)fb, false);
 	if (ret)
 		goto dealloc_fb;
 
+#ifdef CONFIG_VIDEO_GIS
+	/* Entry for GIS */
+	mxc_enable_gis();
+#endif
+
 	return (void *)&panel;
 
 dealloc_fb:
@@ -341,6 +381,82 @@ dealloc_fb:
 }
 #else /* ifndef CONFIG_DM_VIDEO */
 
+struct mxsfb_priv {
+	fdt_addr_t reg_base;
+	struct udevice *disp_dev;
+
+#if IS_ENABLED(CONFIG_DM_RESET)
+	struct reset_ctl_bulk soft_resetn;
+	struct reset_ctl_bulk clk_enable;
+#endif
+
+#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
+	struct clk			lcdif_pix;
+	struct clk			lcdif_disp_axi;
+	struct clk			lcdif_axi;
+#endif
+};
+
+#if IS_ENABLED(CONFIG_DM_RESET)
+static int lcdif_rstc_reset(struct reset_ctl_bulk *rstc, bool assert)
+{
+	int ret;
+
+	if (!rstc)
+		return 0;
+
+	ret = assert ? reset_assert_bulk(rstc)	:
+		       reset_deassert_bulk(rstc);
+
+	return ret;
+}
+
+static int lcdif_of_parse_resets(struct udevice *dev)
+{
+	int ret;
+	ofnode parent, child;
+	struct ofnode_phandle_args args;
+	struct reset_ctl_bulk rstc;
+	const char *compat;
+	uint32_t rstc_num = 0;
+
+	struct mxsfb_priv *priv = dev_get_priv(dev);
+
+	ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0,
+					 0, &args);
+	if (ret)
+		return ret;
+
+	parent = args.node;
+	ofnode_for_each_subnode(child, parent) {
+		compat = ofnode_get_property(child, "compatible", NULL);
+		if (!compat)
+			continue;
+
+		ret = reset_get_bulk_nodev(child, &rstc);
+		if (ret)
+			continue;
+
+		if (!of_compat_cmp("lcdif,soft-resetn", compat, 0)) {
+			priv->soft_resetn = rstc;
+			rstc_num++;
+		} else if (!of_compat_cmp("lcdif,clk-enable", compat, 0)) {
+			priv->clk_enable = rstc;
+			rstc_num++;
+		}
+		else
+			dev_warn(dev, "invalid lcdif reset node: %s\n", compat);
+	}
+
+	if (!rstc_num) {
+		dev_err(dev, "no invalid reset control exists\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+#endif
+
 static int mxs_of_get_timings(struct udevice *dev,
 			      struct display_timing *timings,
 			      u32 *bpp)
@@ -348,6 +464,7 @@ static int mxs_of_get_timings(struct udevice *dev,
 	int ret = 0;
 	u32 display_phandle;
 	ofnode display_node;
+	struct mxsfb_priv *priv = dev_get_priv(dev);
 
 	ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle);
 	if (ret) {
@@ -368,10 +485,19 @@ static int mxs_of_get_timings(struct udevice *dev,
 		return -EINVAL;
 	}
 
-	ret = ofnode_decode_display_timing(display_node, 0, timings);
-	if (ret) {
-		dev_err(dev, "failed to get any display timings\n");
-		return -EINVAL;
+	priv->disp_dev = video_link_get_next_device(dev);
+	if (priv->disp_dev) {
+		ret = video_link_get_display_timings(timings);
+		if (ret) {
+			dev_err(dev, "failed to get any video link display timings\n");
+			return -EINVAL;
+		}
+	} else {
+		ret = ofnode_decode_display_timing(display_node, 0, timings);
+		if (ret) {
+			dev_err(dev, "failed to get any display timings\n");
+			return -EINVAL;
+		}
 	}
 
 	return ret;
@@ -381,20 +507,135 @@ static int mxs_video_probe(struct udevice *dev)
 {
 	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
 	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct mxsfb_priv *priv = dev_get_priv(dev);
 
 	struct display_timing timings;
 	u32 bpp = 0;
 	u32 fb_start, fb_end;
 	int ret;
+	bool enable_bridge = false;
 
 	debug("%s() plat: base 0x%lx, size 0x%x\n",
 	       __func__, plat->base, plat->size);
 
+	priv->reg_base = dev_read_addr(dev);
+	if (priv->reg_base == FDT_ADDR_T_NONE) {
+		dev_err(dev, "lcdif base address is not found\n");
+		return -EINVAL;
+	}
+
 	ret = mxs_of_get_timings(dev, &timings, &bpp);
 	if (ret)
 		return ret;
+	timings.flags |= DISPLAY_FLAGS_DE_HIGH;
+
+#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
+	ret = clk_get_by_name(dev, "pix", &priv->lcdif_pix);
+	if (ret) {
+		printf("Failed to get pix clk\n");
+		return ret;
+	}
+
+	ret = clk_get_by_name(dev, "disp_axi", &priv->lcdif_disp_axi);
+	if (ret) {
+		printf("Failed to get disp_axi clk\n");
+		return ret;
+	}
+
+	ret = clk_get_by_name(dev, "axi", &priv->lcdif_axi);
+	if (ret) {
+		printf("Failed to get axi clk\n");
+		return ret;
+	}
+
+	ret = clk_enable(&priv->lcdif_axi);
+	if (ret) {
+		printf("unable to enable lcdif_axi clock\n");
+		return ret;
+	}
+
+	ret = clk_enable(&priv->lcdif_disp_axi);
+	if (ret) {
+		printf("unable to enable lcdif_disp_axi clock\n");
+		return ret;
+	}
+#endif
+
+#if IS_ENABLED(CONFIG_DM_RESET)
+	ret = lcdif_of_parse_resets(dev);
+	if (!ret) {
+		ret = lcdif_rstc_reset(&priv->soft_resetn, false);
+		if (ret) {
+			dev_err(dev, "deassert soft_resetn failed\n");
+			return ret;
+		}
+
+		ret = lcdif_rstc_reset(&priv->clk_enable, true);
+		if (ret) {
+			dev_err(dev, "assert clk_enable failed\n");
+			return ret;
+		}
+	}
+#endif
+
+	if (priv->disp_dev) {
+#if IS_ENABLED(CONFIG_DISPLAY)
+		if (device_get_uclass_id(priv->disp_dev) == UCLASS_DISPLAY) {
+			ret = display_enable(priv->disp_dev, bpp, &timings);
+			if (ret) {
+				dev_err(dev, "fail to enable display\n");
+				return ret;
+			}
+		}
+#endif
+
+#if IS_ENABLED(CONFIG_VIDEO_BRIDGE)
+		if (device_get_uclass_id(priv->disp_dev) == UCLASS_VIDEO_BRIDGE) {
+			ret = video_bridge_attach(priv->disp_dev);
+			if (ret) {
+				dev_err(dev, "fail to attach bridge\n");
+				return ret;
+			}
+
+			ret = video_bridge_set_backlight(priv->disp_dev, 80);
+			if (ret) {
+				dev_err(dev, "fail to set backlight\n");
+				return ret;
+			}
+
+			enable_bridge = true;
 
-	ret = mxs_probe_common(dev, &timings, bpp, plat->base);
+			/* sec dsim needs enable ploarity at low, default we set to high */
+			if (!strcmp(priv->disp_dev->driver->name, "imx_sec_dsim"))
+				timings.flags &= ~DISPLAY_FLAGS_DE_HIGH;
+
+		}
+#endif
+		if (device_get_uclass_id(priv->disp_dev) == UCLASS_PANEL) {
+			ret = panel_enable_backlight(priv->disp_dev);
+			if (ret) {
+				dev_err(dev, "panel %s enable backlight error %d\n",
+					priv->disp_dev->name, ret);
+				return ret;
+			}
+		}
+	}
+
+#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)
+	ret = clk_set_rate(&priv->lcdif_pix, timings.pixelclock.typ);
+	if (ret < 0) {
+		printf("Failed to set pix clk rate\n");
+		return ret;
+	}
+
+	ret = clk_enable(&priv->lcdif_pix);
+	if (ret) {
+		printf("unable to enable lcdif_pix clock\n");
+		return ret;
+	}
+#endif
+
+	ret = mxs_probe_common(priv->reg_base, &timings, bpp, plat->base, enable_bridge);
 	if (ret)
 		return ret;
 
@@ -419,9 +660,9 @@ static int mxs_video_probe(struct udevice *dev)
 	uc_priv->ysize = timings.vactive.typ;
 
 	/* Enable dcache for the frame buffer */
-	fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
+	fb_start = plat->base;
 	fb_end = plat->base + plat->size;
-	fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
+
 	mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
 					DCACHE_WRITEBACK);
 	video_set_flush_dcache(dev, true);
@@ -433,33 +674,10 @@ static int mxs_video_probe(struct udevice *dev)
 static int mxs_video_bind(struct udevice *dev)
 {
 	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
-	struct display_timing timings;
-	u32 bpp = 0;
-	u32 bytes_pp = 0;
-	int ret;
 
-	ret = mxs_of_get_timings(dev, &timings, &bpp);
-	if (ret)
-		return ret;
-
-	switch (bpp) {
-	case 32:
-	case 24:
-	case 18:
-		bytes_pp = 4;
-		break;
-	case 16:
-		bytes_pp = 2;
-		break;
-	case 8:
-		bytes_pp = 1;
-		break;
-	default:
-		dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
-		return -EINVAL;
-	}
-
-	plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp;
+	/* Max size supported by LCDIF, because in bind, we can't probe panel */
+	plat->size = ALIGN(1920 * 1080 *4 * 2, MMU_SECTION_SIZE);
+	plat->align = MMU_SECTION_SIZE;
 
 	return 0;
 }
@@ -467,8 +685,14 @@ static int mxs_video_bind(struct udevice *dev)
 static int mxs_video_remove(struct udevice *dev)
 {
 	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+	struct mxsfb_priv *priv = dev_get_priv(dev);
+
+	debug("%s\n", __func__);
+
+	if (priv->disp_dev)
+		device_remove(priv->disp_dev, DM_REMOVE_NORMAL);
 
-	mxs_remove_common(plat->base);
+	mxs_remove_common(priv->reg_base, plat->base);
 
 	return 0;
 }
@@ -478,6 +702,8 @@ static const struct udevice_id mxs_video_ids[] = {
 	{ .compatible = "fsl,imx28-lcdif" },
 	{ .compatible = "fsl,imx7ulp-lcdif" },
 	{ .compatible = "fsl,imxrt-lcdif" },
+	{ .compatible = "fsl,imx8mm-lcdif" },
+	{ .compatible = "fsl,imx8mn-lcdif" },
 	{ /* sentinel */ }
 };
 
@@ -489,5 +715,6 @@ U_BOOT_DRIVER(mxs_video) = {
 	.probe	= mxs_video_probe,
 	.remove = mxs_video_remove,
 	.flags	= DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
+	.priv_auto   = sizeof(struct mxsfb_priv),
 };
 #endif /* ifndef CONFIG_DM_VIDEO */
diff --git a/drivers/video/nxp/Kconfig b/drivers/video/nxp/Kconfig
new file mode 100644
index 00000000000..609cb92a9ba
--- /dev/null
+++ b/drivers/video/nxp/Kconfig
@@ -0,0 +1,8 @@
+
+config VIDEO_NXP_HDP
+	bool
+	help
+	  Enable NXP HDP Library for HDMI and HDMI/DP firmware loading
+
+source "drivers/video/nxp/imx/Kconfig"
+source "drivers/video/nxp/layerscape/Kconfig"
diff --git a/drivers/video/nxp/Makefile b/drivers/video/nxp/Makefile
new file mode 100644
index 00000000000..420c2df7830
--- /dev/null
+++ b/drivers/video/nxp/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2020 NXP
+
+UBOOTINCLUDE += -I$(srctree)/drivers/video/nxp/hdp
+obj-$(CONFIG_VIDEO_NXP_HDP) += hdp/
+obj-y += imx/
+obj-y += layerscape/
diff --git a/drivers/video/nxp/hdp/API_AFE.c b/drivers/video/nxp/hdp/API_AFE.c
new file mode 100644
index 00000000000..7b778cd3d58
--- /dev/null
+++ b/drivers/video/nxp/hdp/API_AFE.c
@@ -0,0 +1,115 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AFE.c
+ *
+ ******************************************************************************
+ */
+
+#include "address.h"
+#include "API_AFE.h"
+#include "util.h"
+#ifndef __UBOOT__
+#include <stdio.h>
+#endif
+
+void afe_write(unsigned int offset, unsigned short val)
+{
+#ifdef EXTERNAL_AFE
+	cdn_phapb_write(offset << 2, val);
+#else
+	CDN_API_STATUS sts;
+
+	sts = cdn_api_general_write_register_blocking(
+		ADDR_AFE + (offset << 2), val);
+
+	if (sts != CDN_OK) {
+		printf("CDN_API_General_Write_Register_blocking(0x%.8X, 0x%.8X) returned %d\n",
+		       offset,
+		       val,
+		       (int)sts);
+	}
+#endif
+}
+
+unsigned short afe_read(unsigned int offset)
+{
+	GENERAL_READ_REGISTER_RESPONSE resp;
+
+#ifdef EXTERNAL_AFE
+	cdn_phapb_read(offset << 2, &resp.val);
+#else
+	CDN_API_STATUS sts;
+
+	sts = cdn_api_general_read_register_blocking(
+		ADDR_AFE + (offset << 2), &resp);
+
+	if (sts != CDN_OK) {
+		printf("CDN_API_General_Read_Register_blocking(0x%.8X) returned %d\n",
+		       offset,
+		       (int)sts);
+	}
+#endif
+	return resp.val;
+}
+
+void set_field_value(reg_field_t *reg_field, u32 value)
+{
+	u8 length;
+	u32 max_value;
+	u32 trunc_val;
+	length = (reg_field->msb - reg_field->lsb + 1);
+
+	max_value = (1 << length) - 1;
+	if (value > max_value) {
+		trunc_val = value;
+		trunc_val &= (1 << length) - 1;
+		printf("set_field_value() Error! Specified value (0x%0X) exceeds field capacity - it will by truncated to 0x%0X (%0d-bit field - max value: %0d dec)\n",
+		       value, trunc_val, length, max_value);
+	} else {
+		reg_field->value = value;
+	}
+}
+
+int set_reg_value(reg_field_t reg_field)
+{
+	return reg_field.value << reg_field.lsb;
+}
diff --git a/drivers/video/nxp/hdp/API_AFE.h b/drivers/video/nxp/hdp/API_AFE.h
new file mode 100644
index 00000000000..2ebdfb32260
--- /dev/null
+++ b/drivers/video/nxp/hdp/API_AFE.h
@@ -0,0 +1,99 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AFE.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef API_AFE_H_
+#define API_AFE_H_
+#include "util.h"
+
+typedef enum {
+	AFE_LINK_RATE_1_6 = 0x6,  /* 1.62 Gb/s */
+	AFE_LINK_RATE_2_1 = 0x8,  /* 2.16 Gb/s */
+	AFE_LINK_RATE_2_4 = 0x9,  /* 2.43 Gb/s */
+	AFE_LINK_RATE_2_7 = 0xA,  /* 2.70 Gb/s */
+	AFE_LINK_RATE_3_2 = 0xC,  /* 3.24 Gb/s */
+	AFE_LINK_RATE_4_3 = 0x10, /* 4.32 Gb/s */
+	AFE_LINK_RATE_5_4 = 0x14, /* 5.40 Gb/s */
+	AFE_LINK_RATE_8_1 = 0x1E, /* 8.10 Gb/s */
+} ENUM_AFE_LINK_RATE;
+
+/* Some of the PHY programming sequences */
+/* depend on the reference clock frequency. */
+/* Variable of this type is used to control */
+/* the programming flow. */
+typedef enum {
+	REFCLK_24MHZ,
+	REFCLK_27MHZ
+} REFCLK_FREQ;
+
+typedef enum {
+	CLK_RATIO_1_1,
+	CLK_RATIO_5_4,
+	CLK_RATIO_3_2,
+	CLK_RATIO_2_1,
+	CLK_RATIO_1_2,
+	CLK_RATIO_5_8,
+	CLK_RATIO_3_4
+} clk_ratio_t;
+
+typedef struct {
+	u32 value;
+	u8 lsb;
+	u8 msb;
+} reg_field_t;
+
+unsigned char AFE_check_rate_supported(ENUM_AFE_LINK_RATE rate);
+void afe_write(unsigned int offset, unsigned short val);
+unsigned short afe_read(unsigned int offset);
+void AFE_init(int num_lanes, ENUM_AFE_LINK_RATE link_rate);
+void AFE_power(int num_lanes, ENUM_AFE_LINK_RATE link_rate);
+
+/*extern int cdn_phapb_read(unsigned int addr, unsigned int *value);*/
+/*extern int cdn_phapb_write(unsigned int addr, unsigned int value);*/
+void set_field_value(reg_field_t *reg_field, u32 value);
+int set_reg_value(reg_field_t reg_field);
+
+#endif
+
diff --git a/drivers/video/nxp/hdp/API_AFE_t28hpc_hdmitx.c b/drivers/video/nxp/hdp/API_AFE_t28hpc_hdmitx.c
new file mode 100644
index 00000000000..933ecfa8d43
--- /dev/null
+++ b/drivers/video/nxp/hdp/API_AFE_t28hpc_hdmitx.c
@@ -0,0 +1,1863 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AFE_t28hpc_hdmitx.c
+ *
+ ******************************************************************************
+ */
+
+#include "API_AFE_t28hpc_hdmitx.h"
+#include "API_AFE.h"
+#include "externs.h"
+
+#ifndef DEBUG
+static inline void write16(uint32_t addr, uint16_t val)
+{
+	afe_write(addr, val);
+}
+
+static inline uint16_t read16(uint32_t addr)
+{
+	return afe_read(addr);
+}
+#else
+#define  write16(addr, val) __write16(addr, val, __LINE__)
+static inline void __write16(uint32_t addr, uint16_t val, int  line)
+{
+	afe_write(addr, val);
+	debug("write16():%4d Writting value 0x%04X at address 0x%05X (0x%04X)\n",
+	      line, val, (0x20000 * 4) + (addr << 2), addr);
+}
+#define  read16(addr) __read16(addr, __LINE__)
+static inline uint16_t __read16(uint32_t addr, int  line)
+{
+	debug("read16():%5d Reading from address 0x%05X (0x%04X)\n",
+	      line, (0x20000 * 4) + (addr << 2), addr);
+	return afe_read(addr);
+}
+
+#endif
+
+static char inside(u32 value, u32 left_sharp_corner,
+	u32 right_sharp_corner)
+{
+	if (value < left_sharp_corner)
+		return false;
+	if (value > right_sharp_corner)
+		return false;
+	return true;
+}
+
+void aux_cfg_t28hpc(void)
+{
+	write16(0x5025, 0x0001);
+
+	write16(0x5024, 36);
+
+	write16(0x5021, 0x0100);
+	write16(0x5021, 0x0300);
+	write16(0x5026, 0x0000);
+	write16(0x5020, 0x2008);
+	write16(0x5020, 0x2018);
+	write16(0x5020, 0xA018);
+	write16(0x5021, 0x030C);
+	write16(0x5029, 0x0000);
+	write16(0x5027, 0x4001);
+	write16(0x5020, 0xA098);
+	write16(0x5020, 0xA198);
+	write16(0x5021, 0x030D);
+	write16(0x5021, 0x030F);
+}
+
+int phy_cfg_t28hpc(int num_lanes, VIC_MODES vic_mode, int bpp,
+	VIC_PXL_ENCODING_FORMAT format, bool pixel_clk_from_phy)
+{
+	const int phy_reset_workaround = 1;
+	unsigned int vco_freq;
+	unsigned char k;
+	uint32_t reg_val;
+	uint32_t pixel_freq_khz = vic_table[vic_mode][PIXEL_FREQ_KHZ];
+	uint32_t character_clock_ratio_num = 1;
+	uint32_t character_clock_ratio_den = 1;
+	uint32_t character_freq_khz;
+	const unsigned int refclk_freq_khz = 27000;
+	unsigned int ftemp, ftemp2;
+
+	clk_ratio_t clk_ratio = 0;
+	reg_field_t cmnda_pll0_hs_sym_div_sel;
+	reg_field_t cmnda_pll0_ip_div;
+	reg_field_t cmnda_pll0_fb_div_low;
+	reg_field_t cmnda_pll0_fb_div_high;
+	reg_field_t cmn_ref_clk_dig_div;
+	reg_field_t divider_scaler;
+	reg_field_t cmnda_hs_clk_0_sel;
+	reg_field_t cmnda_hs_clk_1_sel;
+	reg_field_t tx_subrate;
+	reg_field_t voltage_to_current_coarse;
+	reg_field_t voltage_to_current;
+	reg_field_t ndac_ctrl;
+	reg_field_t pmos_ctrl;
+	reg_field_t ptat_ndac_ctrl;
+	reg_field_t charge_pump_gain;
+	reg_field_t vco_ring_select;
+	reg_field_t pll_feedback_divider_total;
+	reg_field_t cmnda_pll0_pxdiv_high;
+	reg_field_t cmnda_pll0_pxdiv_low;
+	reg_field_t coarse_code;
+	reg_field_t v2i_code;
+	reg_field_t vco_cal_code;
+
+	cmnda_pll0_fb_div_high.value = 0x00A;
+	ftemp = pixel_freq_khz;
+
+	debug(" VIC %d, pixel clock %u kHz\n", vic_mode, ftemp);
+
+	/* Set field position */
+	cmnda_pll0_hs_sym_div_sel.msb = 9;
+	cmnda_pll0_hs_sym_div_sel.lsb = 8;
+	cmnda_pll0_ip_div.msb = 7;
+	cmnda_pll0_ip_div.lsb = 0;
+	cmnda_pll0_fb_div_low.msb = 9;
+	cmnda_pll0_fb_div_low.lsb = 0;
+	cmnda_pll0_fb_div_high.msb = 9;
+	cmnda_pll0_fb_div_high.lsb = 0;
+	cmn_ref_clk_dig_div.msb = 13;
+	cmn_ref_clk_dig_div.lsb = 12;
+	divider_scaler.msb = 14;
+	divider_scaler.lsb = 12;
+	cmnda_hs_clk_0_sel.msb = 1;
+	cmnda_hs_clk_0_sel.lsb = 0;
+	cmnda_hs_clk_1_sel.msb = 1;
+	cmnda_hs_clk_1_sel.lsb = 0;
+	tx_subrate.msb = 2;
+	tx_subrate.lsb = 0;
+	voltage_to_current_coarse.msb = 2;
+	voltage_to_current_coarse.lsb = 0;
+	voltage_to_current.msb = 5;
+	voltage_to_current.lsb = 4;
+	ndac_ctrl.msb = 11;
+	ndac_ctrl.lsb = 8;
+	pmos_ctrl.msb = 7;
+	pmos_ctrl.lsb = 0;
+	ptat_ndac_ctrl.msb = 5;
+	ptat_ndac_ctrl.lsb = 0;
+	charge_pump_gain.msb = 8;
+	charge_pump_gain.lsb = 0;
+	vco_ring_select.msb = 12;
+	vco_ring_select.lsb = 12;
+	pll_feedback_divider_total.msb = 9;
+	pll_feedback_divider_total.lsb = 0;
+	cmnda_pll0_pxdiv_high.msb = 9;
+	cmnda_pll0_pxdiv_high.lsb = 0;
+	cmnda_pll0_pxdiv_low.msb = 9;
+	cmnda_pll0_pxdiv_low.lsb = 0;
+	coarse_code.msb = 7;
+	coarse_code.lsb = 0;
+	v2i_code.msb = 3;
+	v2i_code.lsb = 0;
+	vco_cal_code.msb = 8;
+	vco_cal_code.lsb = 0;
+
+	if (phy_reset_workaround) {
+		/* register PHY_PMA_ISOLATION_CTRL */
+		write16(0xC81F, 0xD000); /*  enable PHY iso mode only for CMN */
+		/* register PHY_PMA_ISO_PLL_CTRL1 */
+		reg_val = read16(0xC812);
+		reg_val &= 0xFF00;
+		reg_val |= 0x0012;
+		/* set pll0_clk_datart1_div/pll0_clk_datart0_div dividers */
+		write16(0xC812, reg_val);
+		/* register PHY_ISO_CMN_CTRL */
+		/* assert PHY reset from isolation register */
+		write16(0xC010, 0x0000);
+		/* register PHY_PMA_ISO_CMN_CTRL */
+		write16(0xC810, 0x0000);        /* assert PMA CMN reset */
+		/* register XCVR_DIAG_BIDI_CTRL */
+		for (k = 0; k < num_lanes; k++)
+			write16(0x40E8 | (k << 9), 0x00FF);
+	}
+	/*---------------------------------------------------------------
+	 * Describing Task phy_cfg_hdp
+	 * --------------------------------------------------------------*/
+	/* register PHY_PMA_CMN_CTRL1 */
+	reg_val = read16(0xC800);
+	reg_val &= 0xFFF7;
+	reg_val |= 0x0008;
+	write16(0xC800, reg_val);
+
+	/* register CMN_DIAG_PLL0_TEST_MODE */
+	write16(0x01C4, 0x0020);
+	/* register CMN_PSM_CLK_CTRL */
+	write16(0x0061, 0x0016);
+
+	switch (format) {
+	case YCBCR_4_2_2:
+		clk_ratio = CLK_RATIO_1_1;
+		character_clock_ratio_num = 1;
+		character_clock_ratio_den = 1;
+		break;
+	case YCBCR_4_2_0:
+		switch (bpp) {
+		case 8:
+			clk_ratio = CLK_RATIO_1_2;
+			character_clock_ratio_num = 1;
+			character_clock_ratio_den = 2;
+			break;
+		case 10:
+			clk_ratio = CLK_RATIO_5_8;
+			character_clock_ratio_num = 5;
+			character_clock_ratio_den = 8;
+			break;
+		case 12:
+			clk_ratio = CLK_RATIO_3_4;
+			character_clock_ratio_num = 3;
+			character_clock_ratio_den = 4;
+			break;
+		case 16:
+			clk_ratio = CLK_RATIO_1_1;
+			character_clock_ratio_num = 1;
+			character_clock_ratio_den = 1;
+			break;
+		default:
+			debug("Invalid ColorDepth\n");
+		}
+		break;
+
+	default:
+		switch (bpp) {
+			/* Assume RGB */
+		case 10:
+			clk_ratio = CLK_RATIO_5_4;
+			character_clock_ratio_num = 5;
+			character_clock_ratio_den = 4;
+			break;
+		case 12:
+			clk_ratio = CLK_RATIO_3_2;
+			character_clock_ratio_num = 3;
+			character_clock_ratio_den = 2;
+			break;
+		case 16:
+			clk_ratio = CLK_RATIO_2_1;
+			character_clock_ratio_num = 2;
+			character_clock_ratio_den = 1;
+			break;
+		default:
+			clk_ratio = CLK_RATIO_1_1;
+			character_clock_ratio_num = 1;
+			character_clock_ratio_den = 1;
+		}
+	}
+
+	character_freq_khz = pixel_freq_khz *
+		character_clock_ratio_num / character_clock_ratio_den;
+	ftemp = pixel_freq_khz;
+	ftemp2 = character_freq_khz;
+	debug("Pixel clock frequency: %u kHz, character clock frequency: %u, color depth is %0d-bit.\n",
+	       ftemp, ftemp2, bpp);
+	if (pixel_clk_from_phy == 0) {
+		/* -----------------------------------------------------------
+		 * Describing Task phy_cfg_hdmi_pll0_0pt5736 (Clock is input)
+		 * -----------------------------------------------------------*/
+
+		/* register CMN_PLL0_VCOCAL_INIT_TMR */
+		write16(0x0084, 0x0064);
+		/* register CMN_PLL0_VCOCAL_ITER_TMR */
+		write16(0x0085, 0x000A);
+		/* register PHY_HDP_CLK_CTL */
+		reg_val = read16(0xC009);
+		reg_val &= 0x00FF;
+		reg_val |= 0x1200;
+		write16(0xC009, reg_val);
+
+		switch (clk_ratio) {
+		case CLK_RATIO_1_1:
+			if (inside(pixel_freq_khz, 340000, 600000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x3C);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x24A);
+				set_field_value(&cmn_ref_clk_dig_div, 0x03);
+				set_field_value(&divider_scaler, 0x06);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						600);
+			} else if (inside(pixel_freq_khz, 170000, 340000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x22);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x146);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x07);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						340);
+			} else if (inside(pixel_freq_khz, 85000, 170000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				set_field_value(&cmnda_pll0_ip_div, 0x11);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x146);
+				set_field_value(&cmn_ref_clk_dig_div, 0x00);
+				set_field_value(&divider_scaler, 0x07);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						340);
+			} else if (inside(pixel_freq_khz, 42500, 85000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				set_field_value(&cmnda_pll0_ip_div, 0x08);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x132);
+				set_field_value(&cmn_ref_clk_dig_div, 0x03);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						320);
+			} else if (inside(pixel_freq_khz, 25000, 42500)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x03);
+				set_field_value(&cmnda_pll0_ip_div, 0x05);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x182);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						400);
+			} else {
+				ftemp = pixel_freq_khz;
+				debug("Pixel clock frequency (%u) is outside of the supported range\n",
+				       ftemp);
+			}
+			break;
+
+		case CLK_RATIO_5_4:
+			if (inside(pixel_freq_khz, 272000, 480000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x30);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x24A);
+				set_field_value(&cmn_ref_clk_dig_div, 0x03);
+				set_field_value(&divider_scaler, 0x05);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						600);
+			} else if (inside(pixel_freq_khz, 136000, 272000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x1A);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x137);
+				set_field_value(&cmn_ref_clk_dig_div, 0x02);
+				set_field_value(&divider_scaler, 0x04);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						325);
+			} else if (inside(pixel_freq_khz, 68000, 136000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				set_field_value(&cmnda_pll0_ip_div, 0x0D);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x137);
+				set_field_value(&cmn_ref_clk_dig_div, 0x02);
+				set_field_value(&divider_scaler, 0x02);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						325);
+			} else if (inside(pixel_freq_khz, 34000, 68000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				set_field_value(&cmnda_pll0_ip_div, 0x06);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x11E);
+				set_field_value(&cmn_ref_clk_dig_div, 0x02);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						300);
+			} else if (inside(pixel_freq_khz, 25000, 34000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x03);
+				set_field_value(&cmnda_pll0_ip_div, 0x04);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x182);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						400);
+			} else {
+				ftemp = pixel_freq_khz;
+				debug("Pixel clock frequency (%u) is outside of the supported range\n",
+				       ftemp);
+			}
+			break;
+		case CLK_RATIO_3_2:
+			if (inside(pixel_freq_khz, 226000, 400000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x28);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x24A);
+				set_field_value(&cmn_ref_clk_dig_div, 0x03);
+				set_field_value(&divider_scaler, 0x04);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						600);
+			} else if (inside(pixel_freq_khz, 113000, 226000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x16);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x13C);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x05);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						330);
+			} else if (inside(pixel_freq_khz, 56000, 113000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				set_field_value(&cmnda_pll0_ip_div, 0x0B);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x13C);
+				set_field_value(&cmn_ref_clk_dig_div, 0x00);
+				set_field_value(&divider_scaler, 0x05);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						330);
+			} else if (inside(pixel_freq_khz, 28000, 56000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				set_field_value(&cmnda_pll0_ip_div, 0x06);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x15A);
+				set_field_value(&cmn_ref_clk_dig_div, 0x02);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						360);
+			} else if (inside(pixel_freq_khz, 25000, 28000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x03);
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x15A);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						360);
+			} else {
+				ftemp = pixel_freq_khz;
+				debug("Pixel clock frequency (%u) is outside of the supported range\n",
+				       ftemp);
+			}
+			break;
+		case CLK_RATIO_2_1:
+			if (inside(pixel_freq_khz, 170000, 300000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x22);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x29A);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x06);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						680);
+			} else if (inside(pixel_freq_khz, 85000, 170000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x11);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x146);
+				set_field_value(&cmn_ref_clk_dig_div, 0x00);
+				set_field_value(&divider_scaler, 0x07);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						340);
+			} else if (inside(pixel_freq_khz, 42500, 85000)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				set_field_value(&cmnda_pll0_ip_div, 0x08);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x132);
+				set_field_value(&cmn_ref_clk_dig_div, 0x03);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						320);
+			} else if (inside(pixel_freq_khz, 25000, 42500)) {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				set_field_value(&cmnda_pll0_ip_div, 0x05);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x182);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&pll_feedback_divider_total,
+						400);
+			} else {
+				ftemp = pixel_freq_khz;
+				debug("Pixel clock frequency (%u) is outside of the supported range\n",
+				       ftemp);
+			}
+			break;
+		case CLK_RATIO_1_2:
+			if (!(inside(pixel_freq_khz, 594000, 594000))) {
+				ftemp = pixel_freq_khz;
+				debug("Pixel clock frequency (%u) is outside of the supported range\n",
+				       ftemp);
+			} else {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				set_field_value(&cmnda_pll0_ip_div, 0x3C);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x24A);
+				set_field_value(&cmn_ref_clk_dig_div, 0x03);
+				set_field_value(&divider_scaler, 0x06);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						600);
+			}
+			break;
+		case CLK_RATIO_5_8:
+			if (!(inside(pixel_freq_khz, 594000, 594000))) {
+				ftemp = pixel_freq_khz;
+				debug("Pixel clock frequency (%u) is outside of the supported range\n",
+				       ftemp);
+			} else {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x3C);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x169);
+				set_field_value(&cmn_ref_clk_dig_div, 0x03);
+				set_field_value(&divider_scaler, 0x06);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						375);
+			}
+			break;
+		case CLK_RATIO_3_4:
+			if (!(inside(pixel_freq_khz, 594000, 594000))) {
+				ftemp = pixel_freq_khz;
+				debug("Pixel clock frequency (%u) is outside of the supported range\n",
+				       ftemp);
+			} else {
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				set_field_value(&cmnda_pll0_ip_div, 0x3C);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x1B4);
+				set_field_value(&cmn_ref_clk_dig_div, 0x03);
+				set_field_value(&divider_scaler, 0x06);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						450);
+			}
+			break;
+		}
+		vco_freq =
+			pixel_freq_khz * pll_feedback_divider_total.value /
+			cmnda_pll0_ip_div.value;
+		ftemp = vco_freq;
+		debug("VCO frequency is %u kHz\n", ftemp);
+
+		if (inside(vco_freq, 1700000, 2000000)) {
+			set_field_value(&voltage_to_current_coarse, 0x04);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x00);
+			set_field_value(&pmos_ctrl, 0x09);
+			set_field_value(&ptat_ndac_ctrl, 0x09);
+			switch (pll_feedback_divider_total.value) {
+			case 300:
+				set_field_value(&charge_pump_gain, 0x82);
+				break;
+			case 320:
+				set_field_value(&charge_pump_gain, 0x83);
+				break;
+			case 325:
+				set_field_value(&charge_pump_gain, 0x83);
+				break;
+			case 330:
+				set_field_value(&charge_pump_gain, 0x84);
+				break;
+			case 340:
+				set_field_value(&charge_pump_gain, 0x84);
+				break;
+			case 360:
+				set_field_value(&charge_pump_gain, 0x86);
+				break;
+			case 400:
+				set_field_value(&charge_pump_gain, 0xA2);
+				break;
+			default:
+				debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+				       pll_feedback_divider_total.value, ftemp);
+			}
+		} else if (inside(vco_freq, 2000000, 2400000)) {
+			set_field_value(&voltage_to_current_coarse, 0x04);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x00);
+			set_field_value(&pmos_ctrl, 0x09);
+			set_field_value(&ptat_ndac_ctrl, 0x09);
+			switch (pll_feedback_divider_total.value) {
+			case 300:
+				set_field_value(&charge_pump_gain, 0x47);
+				break;
+			case 320:
+				set_field_value(&charge_pump_gain, 0x4B);
+				break;
+			case 325:
+				set_field_value(&charge_pump_gain, 0x4C);
+				break;
+			case 330:
+				set_field_value(&charge_pump_gain, 0x80);
+				break;
+			case 340:
+				set_field_value(&charge_pump_gain, 0x81);
+				break;
+			case 360:
+				set_field_value(&charge_pump_gain, 0x82);
+				break;
+			case 400:
+				set_field_value(&charge_pump_gain, 0x84);
+				break;
+			default:
+				debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+				       pll_feedback_divider_total.value, ftemp);
+			}
+		} else if (inside(vco_freq, 2400000, 2800000)) {
+			set_field_value(&voltage_to_current_coarse, 0x05);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			switch (pll_feedback_divider_total.value) {
+			case 300:
+				set_field_value(&charge_pump_gain, 0x43);
+				break;
+			case 320:
+				set_field_value(&charge_pump_gain, 0x45);
+				break;
+			case 325:
+				set_field_value(&charge_pump_gain, 0x45);
+				break;
+			case 330:
+				set_field_value(&charge_pump_gain, 0x45);
+				break;
+			case 340:
+				set_field_value(&charge_pump_gain, 0x86);
+				break;
+			case 360:
+				set_field_value(&charge_pump_gain, 0x4A);
+				break;
+			case 400:
+				set_field_value(&charge_pump_gain, 0x81);
+				break;
+			default:
+				debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+				       pll_feedback_divider_total.value, ftemp);
+			}
+		} else if (inside(vco_freq, 2800000, 3400000)) {
+			set_field_value(&voltage_to_current_coarse, 0x06);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			switch (pll_feedback_divider_total.value) {
+			case 300:
+				set_field_value(&charge_pump_gain, 0x3D);
+				break;
+			case 320:
+				set_field_value(&charge_pump_gain, 0x41);
+				break;
+			case 325:
+				set_field_value(&charge_pump_gain, 0x41);
+				break;
+			case 330:
+				set_field_value(&charge_pump_gain, 0x41);
+				break;
+			case 340:
+				set_field_value(&charge_pump_gain, 0x42);
+				break;
+			case 360:
+				set_field_value(&charge_pump_gain, 0x43);
+				break;
+			case 400:
+				set_field_value(&charge_pump_gain, 0x46);
+				break;
+			default:
+				debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+				       pll_feedback_divider_total.value, ftemp);
+			}
+		} else if (inside(vco_freq, 3400000, 3900000)) {
+			set_field_value(&voltage_to_current_coarse, 0x04);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x00);
+			set_field_value(&pmos_ctrl, 0x07);
+			set_field_value(&ptat_ndac_ctrl, 0x0F);
+			switch (pll_feedback_divider_total.value) {
+			case 375:
+				set_field_value(&charge_pump_gain, 0x41);
+				break;
+			case 600:
+				set_field_value(&charge_pump_gain, 0x82);
+				break;
+			case 680:
+				set_field_value(&charge_pump_gain, 0x85);
+				break;
+			default:
+				debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+				       pll_feedback_divider_total.value, ftemp);
+			}
+		} else if (inside(vco_freq, 3900000, 4500000)) {
+			set_field_value(&voltage_to_current_coarse, 0x05);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x00);
+			set_field_value(&pmos_ctrl, 0x07);
+			set_field_value(&ptat_ndac_ctrl, 0x0F);
+			switch (pll_feedback_divider_total.value) {
+			case 450:
+				set_field_value(&charge_pump_gain, 0x41);
+				break;
+			case 600:
+				set_field_value(&charge_pump_gain, 0x4B);
+				break;
+			case 680:
+				set_field_value(&charge_pump_gain, 0x82);
+				break;
+			default:
+				debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+				       pll_feedback_divider_total.value, ftemp);
+			}
+		} else if (inside(vco_freq, 4500000, 5200000)) {
+			set_field_value(&voltage_to_current_coarse, 0x06);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			switch (pll_feedback_divider_total.value) {
+			case 600:
+				set_field_value(&charge_pump_gain, 0x45);
+				break;
+			case 680:
+				set_field_value(&charge_pump_gain, 0x4A);
+				break;
+			default:
+				debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+				       pll_feedback_divider_total.value, ftemp);
+			}
+		} else if (inside(vco_freq, 5200000, 6000000)) {
+			set_field_value(&voltage_to_current_coarse, 0x07);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			switch (pll_feedback_divider_total.value) {
+			case 600:
+				set_field_value(&charge_pump_gain, 0x42);
+				break;
+			case 680:
+				set_field_value(&charge_pump_gain, 0x45);
+				break;
+			default:
+				debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n",
+				       pll_feedback_divider_total.value, ftemp);
+			}
+		} else
+			debug("VCO frequency %u kHz is outside of the supported range\n",
+			       ftemp);
+
+		/* register CMN_DIAG_PLL0_INCLK_CTRL */
+		reg_val = set_reg_value(cmnda_pll0_hs_sym_div_sel);
+		reg_val |= set_reg_value(cmnda_pll0_ip_div);
+		write16(0x01CA, reg_val);
+		/* register CMN_DIAG_PLL0_FBL_OVRD */
+		reg_val = set_reg_value(cmnda_pll0_fb_div_low);
+		reg_val |= (1 << 15);
+		write16(0x01C1, reg_val);
+		/* register PHY_PMA_CMN_CTRL1 */
+		reg_val = read16(0xC800);
+		reg_val &= 0xCFFF;
+		reg_val |= set_reg_value(cmn_ref_clk_dig_div);
+		write16(0xC800, reg_val);
+		/* register CMN_CDIAG_REFCLK_CTRL */
+		reg_val = read16(0x0062);
+		reg_val &= 0x8FFF;
+		reg_val |= set_reg_value(divider_scaler);
+		reg_val |= 0x00C0;
+		write16(0x0062, reg_val);
+		/* register CMN_DIAG_HSCLK_SEL */
+		reg_val = read16(0x01E0);
+		reg_val &= 0xFF00;
+		reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 0;
+		reg_val |= (cmnda_hs_clk_1_sel.value >> 1) << 4;
+		write16(0x01E0, reg_val);
+
+		/* register XCVR_DIAG_HSCLK_SEL */
+		for (k = 0; k < num_lanes; k++) {
+			reg_val = read16(0x40E1 | (k << 9));
+			reg_val &= 0xCFFF;
+			reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 12;
+			write16(0x40E1 | (k << 9), reg_val);
+		}
+
+		/* register TX_DIAG_TX_CTRL */
+		for (k = 0; k < num_lanes; k++) {
+			reg_val = read16(0x41E0 | (k << 9));
+			reg_val &= 0xFF3F;
+			reg_val |= (tx_subrate.value >> 1) << 6;
+			write16(0x41E0 | (k << 9), reg_val);
+		}
+
+		/* register CMN_PLLSM0_USER_DEF_CTRL */
+		reg_val = set_reg_value(vco_ring_select);
+		write16(0x002F, reg_val);
+		/* register CMN_DIAG_PLL0_OVRD */
+		write16(0x01C2, 0x0000);
+		/* register CMN_DIAG_PLL0_FBH_OVRD */
+		reg_val = set_reg_value(cmnda_pll0_fb_div_high);
+		reg_val |= (1 << 15);
+		write16(0x01C0, reg_val);
+		/* register CMN_DIAG_PLL0_V2I_TUNE */
+		reg_val = set_reg_value(voltage_to_current_coarse);
+		reg_val |= set_reg_value(voltage_to_current);
+		write16(0x01C5, reg_val);
+		/* register CMN_DIAG_PLL0_PTATIS_TUNE1 */
+		reg_val = set_reg_value(pmos_ctrl);
+		reg_val |= set_reg_value(ndac_ctrl);
+		write16(0x01C8, reg_val);
+		/* register CMN_DIAG_PLL0_PTATIS_TUNE2 */
+		reg_val = set_reg_value(ptat_ndac_ctrl);
+		write16(0x01C9, reg_val);
+		/* register CMN_DIAG_PLL0_CP_TUNE */
+		reg_val = set_reg_value(charge_pump_gain);
+		write16(0x01C6, reg_val);
+		/* register CMN_DIAG_PLL0_LF_PROG */
+		write16(0x01C7, 0x0008);
+
+		/* register XCVR_DIAG_PLLDRC_CTRL */
+		for (k = 0; k < num_lanes; k++) {
+			reg_val = read16(0x40E0 | (k << 9));
+			reg_val &= 0xBFFF;
+			write16(0x40E0 | (k << 9), reg_val);
+		}
+
+	} else {
+		/* Describing task phy_cfg_hdmi_pll0_0pt099_ver2
+		   (Clock is OUTPUT) */
+		if (inside(pixel_freq_khz, 27000, 27000)) {
+			switch (clk_ratio) {
+			case CLK_RATIO_1_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						240);
+				set_field_value(&cmnda_pll0_fb_div_low, 0xBC);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x30);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x26);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x26);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x03);
+				break;
+			case CLK_RATIO_5_4:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						300);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x0EC);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x03C);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x030);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x030);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x03);
+				break;
+			case CLK_RATIO_3_2:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						360);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x11C);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x048);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x03A);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x03A);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x03);
+				break;
+			case CLK_RATIO_2_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						240);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x0BC);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x030);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x026);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x026);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				break;
+			default:
+				break;
+			}
+		} else if (inside(pixel_freq_khz, 54000, 54000)) {
+			switch (clk_ratio) {
+			case CLK_RATIO_1_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						480);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x17C);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x060);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x026);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x026);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x03);
+				break;
+			case CLK_RATIO_5_4:
+				set_field_value(&cmnda_pll0_ip_div, 0x04);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						400);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x13C);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x050);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x017);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x017);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				break;
+			case CLK_RATIO_3_2:
+				set_field_value(&cmnda_pll0_ip_div, 0x04);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						480);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x17C);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x060);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x01C);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x01C);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				break;
+			case CLK_RATIO_2_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						240);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x0bc);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x030);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x012);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x012);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			default:
+				break;
+			}
+		} else if (inside(pixel_freq_khz, 74250, 74250)) {
+			switch (clk_ratio) {
+			case CLK_RATIO_1_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						660);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x026);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x026);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x03);
+				break;
+			case CLK_RATIO_5_4:
+				set_field_value(&cmnda_pll0_ip_div, 0x04);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						550);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x1b4);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x06e);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x017);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x017);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x04);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				break;
+			case CLK_RATIO_3_2:
+				set_field_value(&cmnda_pll0_ip_div, 0x04);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						660);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x01c);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x01c);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				break;
+			case CLK_RATIO_2_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						330);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x104);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x042);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x012);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x012);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			default:
+				break;
+			}
+		} else if (inside(pixel_freq_khz, 99000, 99000)) {
+			switch (clk_ratio) {
+			case CLK_RATIO_1_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						440);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x15c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x058);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x012);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x012);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				break;
+			case CLK_RATIO_5_4:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						275);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x0d8);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x037);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x00b);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x00a);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			case CLK_RATIO_3_2:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						330);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x104);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x042);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x00d);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x00d);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			case CLK_RATIO_2_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						440);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x15c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x058);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x012);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x012);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			default:
+				break;
+			}
+		} else if (inside(pixel_freq_khz, 148500, 148500)) {
+			switch (clk_ratio) {
+			case CLK_RATIO_1_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						660);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x012);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x012);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x02);
+				break;
+			case CLK_RATIO_5_4:
+				set_field_value(&cmnda_pll0_ip_div, 0x04);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						550);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x1b4);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x06e);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x00b);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x00a);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			case CLK_RATIO_3_2:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						495);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x188);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x063);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x00d);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x00d);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			case CLK_RATIO_2_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						660);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x012);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x012);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x02);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x02);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			default:
+				break;
+			}
+		} else if (inside(pixel_freq_khz, 198000, 198000)) {
+			switch (clk_ratio) {
+			case CLK_RATIO_1_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						220);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x0ac);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x02c);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x003);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x003);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				break;
+			case CLK_RATIO_5_4:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						550);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x1b4);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x06e);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x00b);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x00a);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			case CLK_RATIO_3_2:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						330);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x104);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x042);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x006);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x005);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				break;
+			case CLK_RATIO_2_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						440);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x15c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x058);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x008);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x008);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				break;
+			default:
+				break;
+			}
+		} else if (inside(pixel_freq_khz, 297000, 297000)) {
+			switch (clk_ratio) {
+			case CLK_RATIO_1_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						330);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x104);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x042);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x003);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x003);
+				set_field_value(&vco_ring_select, 0x00);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				break;
+			case CLK_RATIO_3_2:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						495);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x188);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x063);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x006);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x005);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				break;
+			case CLK_RATIO_2_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						660);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x008);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x008);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				break;
+			default:
+				ftemp = pixel_freq_khz;
+				debug("This pixel clock frequency (%u kHz) is not supported with this (%0d-bit) color depth.\n",
+				       ftemp, bpp);
+			}
+		} else if (inside(pixel_freq_khz, 594000, 594000)) {
+			switch (clk_ratio) {
+			case CLK_RATIO_1_1:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						660);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x003);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x003);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				break;
+			case CLK_RATIO_1_2:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						660);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x20c);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x084);
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x003);
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x003);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x02);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x01);
+				break;
+			case CLK_RATIO_5_8:
+				set_field_value(&cmnda_pll0_ip_div, 0x04);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						550);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x1b4);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x06e);
+				/* does not matter - pixel clock delivered to
+				   controller from SoC */
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x003);
+				/* does not matter - pixel clock delivered to
+				   controller from SoC */
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x003);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				break;
+			case CLK_RATIO_3_4:
+				set_field_value(&cmnda_pll0_ip_div, 0x03);
+				set_field_value(&cmn_ref_clk_dig_div, 0x01);
+				set_field_value(&divider_scaler, 0x01);
+				set_field_value(&pll_feedback_divider_total,
+						495);
+				set_field_value(&cmnda_pll0_fb_div_low, 0x188);
+				set_field_value(&cmnda_pll0_fb_div_high, 0x063);
+				/* does not matter - pixel clock delivered to
+				   controller from SoC */
+				set_field_value(&cmnda_pll0_pxdiv_low, 0x003);
+				/* does not matter - pixel clock delivered to
+				   controller from SoC */
+				set_field_value(&cmnda_pll0_pxdiv_high, 0x003);
+				set_field_value(&vco_ring_select, 0x01);
+				set_field_value(&cmnda_hs_clk_0_sel, 0x01);
+				set_field_value(&cmnda_hs_clk_1_sel, 0x01);
+				set_field_value(&tx_subrate, 0x01);
+				set_field_value(&cmnda_pll0_hs_sym_div_sel,
+						0x00);
+				break;
+			default:
+				debug("This pixel clock frequency (%d KHz) is not supported with this (%0d-bit) color depth.\n",
+				       pixel_freq_khz, bpp);
+			}
+		} else {
+			ftemp = pixel_freq_khz;
+			debug("This pixel clock frequency (%u kHz) is not supported.\n",
+			       ftemp);
+		}
+
+		vco_freq =
+			refclk_freq_khz * pll_feedback_divider_total.value /
+			cmnda_pll0_ip_div.value;
+		ftemp = vco_freq;
+		debug("VCO frequency is %u kHz\n", ftemp);
+
+		if (inside(vco_freq, 1980000, 1980000)) {
+			set_field_value(&voltage_to_current_coarse, 0x04);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x00);
+			set_field_value(&pmos_ctrl, 0x09);
+			set_field_value(&ptat_ndac_ctrl, 0x09);
+			set_field_value(&charge_pump_gain, 0x042);
+			set_field_value(&coarse_code, 160);
+			set_field_value(&v2i_code, 5);
+			set_field_value(&vco_cal_code, 183);
+		} else if (inside(vco_freq, 2160000, 2160000)) {
+			set_field_value(&voltage_to_current_coarse, 0x04);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x00);
+			set_field_value(&pmos_ctrl, 0x09);
+			set_field_value(&ptat_ndac_ctrl, 0x09);
+			set_field_value(&charge_pump_gain, 0x042);
+			set_field_value(&coarse_code, 166);
+			set_field_value(&v2i_code, 6);
+			set_field_value(&vco_cal_code, 208);
+		} else if (inside(vco_freq, 2475000, 2475000)) {
+			set_field_value(&voltage_to_current_coarse, 0x05);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			set_field_value(&charge_pump_gain, 0x042);
+			set_field_value(&coarse_code, 167);
+			set_field_value(&v2i_code, 6);
+			set_field_value(&vco_cal_code, 209);
+		} else if (inside(vco_freq, 2700000, 2700000)) {
+			set_field_value(&voltage_to_current_coarse, 0x05);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			switch (pll_feedback_divider_total.value) {
+			case 300:
+				set_field_value(&charge_pump_gain, 0x042);
+				break;
+			case 400:
+				set_field_value(&charge_pump_gain, 0x04c);
+				break;
+			}
+			set_field_value(&coarse_code, 188);
+			set_field_value(&v2i_code, 6);
+			set_field_value(&vco_cal_code, 225);
+		} else if (inside(vco_freq, 2970000, 2970000)) {
+			set_field_value(&voltage_to_current_coarse, 0x06);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			set_field_value(&charge_pump_gain, 0x042);
+			set_field_value(&coarse_code, 183);
+			set_field_value(&v2i_code, 6);
+			set_field_value(&vco_cal_code, 225);
+		} else if (inside(vco_freq, 3240000, 3240000)) {
+			set_field_value(&voltage_to_current_coarse, 0x05);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			switch (pll_feedback_divider_total.value) {
+			case 360:
+				set_field_value(&charge_pump_gain, 0x042);
+				break;
+			case 480:
+				set_field_value(&charge_pump_gain, 0x04c);
+				break;
+			}
+			set_field_value(&coarse_code, 203);
+			set_field_value(&v2i_code, 7);
+			set_field_value(&vco_cal_code, 256);
+		} else if (inside(vco_freq, 3712500, 3712500)) {
+			set_field_value(&voltage_to_current_coarse, 0x04);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x00);
+			set_field_value(&pmos_ctrl, 0x07);
+			set_field_value(&ptat_ndac_ctrl, 0x0F);
+			set_field_value(&charge_pump_gain, 0x04c);
+			set_field_value(&coarse_code, 212);
+			set_field_value(&v2i_code, 7);
+			set_field_value(&vco_cal_code, 257);
+		} else if (inside(vco_freq, 3960000, 3960000)) {
+			set_field_value(&voltage_to_current_coarse, 0x05);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x00);
+			set_field_value(&pmos_ctrl, 0x07);
+			set_field_value(&ptat_ndac_ctrl, 0x0F);
+			set_field_value(&charge_pump_gain, 0x042);
+			set_field_value(&coarse_code, 184);
+			set_field_value(&v2i_code, 6);
+			set_field_value(&vco_cal_code, 226);
+		} else if (inside(vco_freq, 4320000, 4320000)) {
+			set_field_value(&voltage_to_current_coarse, 0x05);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x07);
+			set_field_value(&ptat_ndac_ctrl, 0x0F);
+			set_field_value(&charge_pump_gain, 0x042);
+			set_field_value(&coarse_code, 205);
+			set_field_value(&v2i_code, 7);
+			set_field_value(&vco_cal_code, 258);
+		} else if (inside(vco_freq, 4455000, 4455000)) {
+			set_field_value(&voltage_to_current_coarse, 0x05);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x00);
+			set_field_value(&pmos_ctrl, 0x07);
+			set_field_value(&ptat_ndac_ctrl, 0x0F);
+			switch (pll_feedback_divider_total.value) {
+			case 495:
+				set_field_value(&charge_pump_gain, 0x042);
+				break;
+			case 660:
+				set_field_value(&charge_pump_gain, 0x04c);
+				break;
+			}
+			set_field_value(&coarse_code, 219);
+			set_field_value(&v2i_code, 7);
+			set_field_value(&vco_cal_code, 272);
+		} else if (inside(vco_freq, 4950000, 4950000)) {
+			set_field_value(&voltage_to_current_coarse, 0x06);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			set_field_value(&charge_pump_gain, 0x042);
+			set_field_value(&coarse_code, 213);
+			set_field_value(&v2i_code, 7);
+			set_field_value(&vco_cal_code, 258);
+		} else if (inside(vco_freq, 5940000, 5940000)) {
+			set_field_value(&voltage_to_current_coarse, 0x07);
+			set_field_value(&voltage_to_current, 0x03);
+			set_field_value(&ndac_ctrl, 0x01);
+			set_field_value(&pmos_ctrl, 0x00);
+			set_field_value(&ptat_ndac_ctrl, 0x07);
+			set_field_value(&charge_pump_gain, 0x042);
+			set_field_value(&coarse_code, 244);
+			set_field_value(&v2i_code, 8);
+			set_field_value(&vco_cal_code, 292);
+		} else {
+			ftemp = vco_freq;
+			debug("Current vco_freq (%u kHz) is not supported.\n",
+			       ftemp);
+		}
+
+		/* register CMN_PLL0_VCOCAL_INIT_TMR */
+		write16(0x0084, 0x0064);
+		/* register CMN_PLL0_VCOCAL_ITER_TMR */
+		write16(0x0085, 0x000A);
+		/* register PHY_HDP_CLK_CTL */
+		reg_val = read16(0xC009);
+		reg_val &= 0x00FF;
+		reg_val |= 0x2 << 8;
+		reg_val |= 0x1 << 12;
+		write16(0xC009, reg_val);
+		/* register CMN_DIAG_PLL0_INCLK_CTRL */
+		reg_val = set_reg_value(cmnda_pll0_ip_div);
+		reg_val |= set_reg_value(cmnda_pll0_hs_sym_div_sel);
+		write16(0x01CA, reg_val);
+		/* register CMN_DIAG_PLL0_FBH_OVRD */
+		reg_val = set_reg_value(cmnda_pll0_fb_div_high);
+		reg_val |= (1 << 15);
+		write16(0x01C0, reg_val);
+		/* register CMN_DIAG_PLL0_FBL_OVRD */
+		reg_val = set_reg_value(cmnda_pll0_fb_div_low);
+		reg_val |= (1 << 15);
+		write16(0x01C1, reg_val);
+		/* register CMN_DIAG_PLL0_PXL_DIVL */
+		reg_val = set_reg_value(cmnda_pll0_pxdiv_low);
+		write16(0x01CC, reg_val);
+		/* register CMN_DIAG_PLL0_PXL_DIVH */
+		reg_val = set_reg_value(cmnda_pll0_pxdiv_high);
+		reg_val |= (1 << 15);
+		write16(0x01CB, reg_val);
+
+		/* register TX_DIAG_TX_CTRL */
+		for (k = 0; k < num_lanes; k++) {
+			reg_val = read16(0x41E0 | (k << 9));
+			reg_val &= 0xFF3F;
+			reg_val |= (tx_subrate.value >> 1) << 6;
+			write16(0x41E0 | (k << 9), reg_val);
+		}
+
+		/* register PHY_PMA_CMN_CTRL1 */
+		reg_val = read16(0xC800);
+		reg_val &= 0xCFFF;
+		reg_val |= set_reg_value(cmn_ref_clk_dig_div);
+		write16(0xC800, reg_val);
+		/* register CMN_CDIAG_REFCLK_CTRL */
+		reg_val = read16(0x0062);
+		reg_val &= 0x8FFF;
+		reg_val |= set_reg_value(divider_scaler);
+		reg_val |= 0x00C0;
+		write16(0x0062, reg_val);
+		/* register CMN_DIAG_HSCLK_SEL */
+		reg_val = read16(0x01E0);
+		reg_val &= 0xFF00;
+		reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 0;
+		reg_val |= (cmnda_hs_clk_1_sel.value >> 1) << 4;
+		write16(0x01E0, reg_val);
+		/* register CMN_PLLSM0_USER_DEF_CTRL */
+		reg_val = set_reg_value(vco_ring_select);
+		write16(0x002F, reg_val);
+
+		/* register XCVR_DIAG_HSCLK_SEL */
+		for (k = 0; k < num_lanes; k++) {
+			reg_val = read16(0x40E1 | (k << 9));
+			reg_val &= 0xCFFF;
+			reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 12;
+			write16(0x40E1 | (k << 9), reg_val);
+		}
+
+		/* register CMN_DIAG_PLL0_OVRD */
+		write16(0x01C2, 0x0000);
+		/* register CMN_DIAG_PLL0_V2I_TUNE */
+		reg_val = set_reg_value(voltage_to_current_coarse);
+		reg_val |= set_reg_value(voltage_to_current);
+		write16(0x01C5, reg_val);
+		/* register CMN_DIAG_PLL0_PTATIS_TUNE1 */
+		reg_val = set_reg_value(pmos_ctrl);
+		reg_val |= set_reg_value(ndac_ctrl);
+		write16(0x01C8, reg_val);
+		/* register CMN_DIAG_PLL0_PTATIS_TUNE2 */
+		reg_val = set_reg_value(ptat_ndac_ctrl);
+		write16(0x01C9, reg_val);
+		/* register CMN_PLL0_VCOCAL_START */
+		reg_val = read16(0x0081);
+		reg_val &= 0xFE00;
+		reg_val |= set_reg_value(vco_cal_code);
+		write16(0x0081, reg_val);
+		/* register CMN_DIAG_PLL0_CP_TUNE */
+		reg_val = set_reg_value(charge_pump_gain);
+		write16(0x01C6, reg_val);
+		/* register CMN_DIAG_PLL0_LF_PROG */
+		write16(0x01C7, 0x0008);
+
+		/* register XCVR_DIAG_PLLDRC_CTRL */
+		for (k = 0; k < num_lanes; k++) {
+			reg_val = read16(0x40E0 | (k << 9));
+			reg_val &= 0xBFFF;
+			write16(0x40E0 | (k << 9), reg_val);
+		}
+	}
+
+	/* Back to task phy_cfg_hdp */
+
+	/* register PHY_PMA_CMN_CTRL1 */
+	reg_val = read16(0xC800);
+	reg_val &= 0xFF8F;
+	/* for differential clock on the refclk_p and refclk_m
+	 * off chip pins: PHY_PMA_CMN_CTRL1[6:4]=3'b000 */
+	reg_val |= 0x0000;
+	write16(0xC800, reg_val);
+
+	/* register CMN_DIAG_ACYA */
+	write16(0x01FF, 0x0100);
+
+	if (phy_reset_workaround) {
+		/* register PHY_ISO_CMN_CTRL */
+		write16(0xC010, 0x0001);        /* Deassert PHY reset */
+		/* register PHY_PMA_ISO_CMN_CTRL */
+		write16(0xC810, 0x0003);
+		for (k = 0; k < num_lanes; k++) {
+			/* register XCVR_PSM_RCTRL */
+			write16(0x4001 | (k << 9), 0xFEFC);
+		}
+		/* register PHY_PMA_ISO_CMN_CTRL
+		 * Assert cmn_macro_pwr_en*/
+		write16(0xC810, 0x0013);
+
+		/* PHY_PMA_ISO_CMN_CTRL
+		 * wait for cmn_macro_pwr_en_ack*/
+		while (!(read16(0xC810) & (1 << 5)))
+			;
+
+		/* PHY_PMA_CMN_CTRL1 wait for cmn_ready */
+		while (!(read16(0xC800) & (1 << 0)))
+			;
+	} else {
+		for (k = 0; k < num_lanes; k++) {
+			/* register XCVR_PSM_RCTRL */
+			write16(0x4001 | (k << 9), 0xBEFC);
+		}
+	}
+	for (k = 0; k < num_lanes; k++) {
+		/* register TX_PSC_A0 */
+		write16(0x4100 | (k << 9), 0x6791);
+		/* register TX_PSC_A1 */
+		write16(0x4101 | (k << 9), 0x6790);
+		/* register TX_PSC_A2 */
+		write16(0x4102 | (k << 9), 0x0090);
+		/* register TX_PSC_A3 */
+		write16(0x4103 | (k << 9), 0x0090);
+		/* register RX_PSC_CAL */
+		reg_val = read16(0x8006 | (k << 9));
+		reg_val &= 0xFFBB;
+		write16(0x8006 | (k << 9), reg_val);
+		reg_val = read16(0x8000 | (k << 9));
+		reg_val &= 0xFFBB;
+		write16(0x8000 | (k << 9), reg_val);
+	}
+
+	/* End of task phy_cfg_hdp */
+	/* register PHY_HDP_MODE_CTL */
+	write16(0xC008, 0x0004);
+
+	aux_cfg_t28hpc();
+	return character_freq_khz;
+}
+
+int hdmi_tx_t28hpc_power_config_seq(int num_lanes)
+{
+	unsigned char k;
+
+	/* Configure the power state.
+	 * register TX_DIAG_ACYA */
+	for (k = 0; k < num_lanes; k++) {
+		/* register XCVR_PSM_CAL_TMR */
+		write16(0x41FF | (k << 9), 0x0001);
+	}
+
+	/* register PHY_DP_MODE_CTL */
+	while (!(read16(0xC008) & (1 << 6)))
+		;
+
+	/* PHY_DP_MODE_CTL */
+	write16(0xC008, (((0x0F << num_lanes) & 0x0F) << 12) | 0x0101);
+
+	/* PHY_DP_MODE_CTL */
+	while (!(read16(0xC008) & (1 << 4)))
+		;
+
+	return 0;
+}
diff --git a/drivers/video/nxp/hdp/API_AFE_t28hpc_hdmitx.h b/drivers/video/nxp/hdp/API_AFE_t28hpc_hdmitx.h
new file mode 100644
index 00000000000..756c1d577e1
--- /dev/null
+++ b/drivers/video/nxp/hdp/API_AFE_t28hpc_hdmitx.h
@@ -0,0 +1,64 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AFE_t28hpc_hdmitx.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef API_AFE_T28HPC_HDMITX_H_
+#define API_AFE_T28HPC_HDMITX_H_
+
+#ifndef __UBOOT__
+#include <assert.h>
+#include <stdint.h>
+#else
+#include <common.h>
+#endif
+#include "vic_table.h"
+#include "API_AFE.h"
+#include "externs.h"
+
+int phy_cfg_t28hpc(int num_lanes, VIC_MODES vic_mode, int bpp,
+		VIC_PXL_ENCODING_FORMAT format, bool pixel_clk_from_phy);
+int hdmi_tx_t28hpc_power_config_seq(int num_lanes);
+
+#endif
diff --git a/drivers/video/nxp/hdp/API_AVI.c b/drivers/video/nxp/hdp/API_AVI.c
new file mode 100644
index 00000000000..4a6c3ee17d5
--- /dev/null
+++ b/drivers/video/nxp/hdp/API_AVI.c
@@ -0,0 +1,192 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AVI.c
+ *
+ ******************************************************************************
+ */
+
+#include "API_AVI.h"
+#include "API_Infoframe.h"
+
+CDN_API_STATUS cdn_api_set_avi(VIC_MODES vic_mode,
+	VIC_PXL_ENCODING_FORMAT color_mode,
+	BT_TYPE itu_ver)
+{
+	unsigned int active_slot = vic_table[vic_mode][H_BLANK];
+	unsigned int line_width = vic_table[vic_mode][H_TOTAL];
+	unsigned int hactive = line_width - active_slot + 1;
+	unsigned int vactive = vic_table[vic_mode][V_ACTIVE] + 1;
+
+	unsigned int hactive_l = hactive - 256 * ((unsigned int)hactive / 256);
+	unsigned int hactive_h = hactive / 256;
+	unsigned int vactive_l = vactive - 256 * ((unsigned int)vactive / 256);
+	unsigned int vactive_h = vactive / 256;
+
+	/* unsigned int packet; */
+
+	unsigned int packet_type = 0x82;
+	unsigned int packet_version = 0x2;
+	unsigned int packet_len = 0xd;
+	unsigned int packet_y = 0;
+	unsigned int packet_c = 0;
+	unsigned int packet_r = 0;
+	unsigned int packet_vic = 0;
+	unsigned int packet_pr = 0;
+	unsigned int packet_buf_size = 5; /* Total buf length is 18, aligned with 4 bytes, need 5 words */
+	unsigned int packet_buf[packet_buf_size];
+	unsigned char *packet = (unsigned char *)&packet_buf[0];
+	unsigned int packet_hb0 = 0;
+	unsigned int packet_hb1 = 0;
+	unsigned int packet_hb2 = 0;
+	unsigned int packet_pb0 = 0;
+	unsigned int packet_pb1 = 0;
+	unsigned int packet_pb2 = 0;
+	unsigned int packet_pb3 = 0;
+	unsigned int packet_pb4 = 0;
+	unsigned int packet_pb5 = 0;
+	unsigned int packet_pb6 = 0;
+	unsigned int packet_pb7 = 0;
+	unsigned int packet_pb8 = 0;
+	unsigned int packet_pb9 = 0;
+	unsigned int packet_pb10 = 0;
+	unsigned int packet_pb11 = 0;
+	unsigned int packet_pb12 = 0;
+	unsigned int packet_pb13 = 0;
+	unsigned int pb1_13_chksum = 0;
+	unsigned int packet_chksum = 0;
+
+	if (color_mode == PXL_RGB)
+		packet_y = 0;
+	else if (color_mode == YCBCR_4_4_4)
+		packet_y = 2;
+	else if (color_mode == YCBCR_4_2_2)
+		packet_y = 1;
+	else if (color_mode == YCBCR_4_2_0)
+		packet_y = 3;
+
+	/* Colorimetry:  Nodata=0 IT601=1 ITU709=2 */
+	if (itu_ver == BT_601)
+		packet_c = 1;
+	else if (itu_ver == BT_709)
+		packet_c = 2;
+	else
+		packet_c = 0;
+
+	unsigned int packet_a0 = 1;
+	unsigned int packet_b = 0;
+	unsigned int packet_s = 0;
+	unsigned int packet_sc = 0; /* Picture Scaling */
+
+	/* Active Format Aspec Ratio: Same As Picture = 0x8 4:3(Center)=0x9
+	   16:9=0xA 14:9=0xB */
+	packet_r = vic_table[vic_mode][VIC_R3_0];
+	/* Aspect Ratio: Nodata=0 4:3=1 16:9=2 */
+	unsigned int packet_m = 0;
+	/* Quantization Range Default=0 Limited Range=0x1 FullRange=0x2
+	   Reserved 0x3 */
+	unsigned int packet_q = 0;
+	/* Quantization Range 0=Limited Range  FullRange=0x1 Reserved 0x3/2 */
+	unsigned int packet_yq = 0;
+	/* Extended Colorimetry xvYCC601=0x0 xvYCC709=1 All other Reserved */
+	unsigned int packet_ec = 0;
+	/*IT content nodata=0 ITcontent=1 */
+	unsigned int packet_it = 0;
+	/* Video Code (CEA) */
+	packet_vic = vic_table[vic_mode][VIC];
+	/* Pixel Repetition 0 ... 9 (1-10) */
+	packet_pr = vic_table[vic_mode][VIC_PR];
+	/* Content Type */
+	unsigned int packet_cn = 0;
+
+	packet_hb0 = packet_type;
+	packet_hb1 = packet_version;
+	packet_hb2 = packet_len;
+
+	packet_pb1 = 32 * packet_y + 16 * packet_a0 + 4 * packet_b + packet_s;
+	packet_pb2 = 64 * packet_c + 16 * packet_m + packet_r;
+	packet_pb3 =
+		128 * packet_it + 16 * packet_ec + 4 * packet_q + packet_sc;
+	packet_pb4 = packet_vic;
+	packet_pb5 = 64 * packet_yq + 16 * packet_cn + packet_pr;
+	packet_pb6 = 0;
+	packet_pb7 = 0;
+	packet_pb8 = vactive_l;
+	packet_pb9 = vactive_h;
+	packet_pb10 = 0;
+	packet_pb11 = 0;
+	packet_pb12 = hactive_l;
+	packet_pb13 = hactive_h;
+
+	pb1_13_chksum =
+		(packet_hb0 + packet_hb1 + packet_hb2 + packet_pb1 +
+		packet_pb2 + packet_pb3 + packet_pb4 + packet_pb5 +
+		packet_pb6 + packet_pb7 + packet_pb8 + packet_pb9 +
+		packet_pb10 + packet_pb11 + packet_pb12 + packet_pb13);
+	packet_chksum =
+		256 - (pb1_13_chksum -
+		256 * ((unsigned int)pb1_13_chksum / 256));
+	packet_pb0 = packet_chksum;
+
+	packet[0] = 0;
+	packet[1] = packet_hb0;
+	packet[2] = packet_hb1;
+	packet[3] = packet_hb2;
+	packet[4] = packet_pb0;
+	packet[5] = packet_pb1;
+	packet[6] = packet_pb2;
+	packet[7] = packet_pb3;
+	packet[8] = packet_pb4;
+	packet[9] = packet_pb5;
+	packet[10] = packet_pb6;
+	packet[11] = packet_pb7;
+	packet[12] = packet_pb8;
+	packet[13] = packet_pb9;
+	packet[14] = packet_pb10;
+	packet[15] = packet_pb11;
+	packet[16] = packet_pb12;
+	packet[17] = packet_pb13;
+
+	cdn_api_infoframeset(0, packet_buf_size,
+			     (unsigned int *)&packet[0], packet_type);
+
+	return CDN_OK;
+} /* End API */
diff --git a/drivers/video/nxp/hdp/API_AVI.h b/drivers/video/nxp/hdp/API_AVI.h
new file mode 100644
index 00000000000..435ba3f9f8f
--- /dev/null
+++ b/drivers/video/nxp/hdp/API_AVI.h
@@ -0,0 +1,59 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_AVI.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef API_AVI_H_
+#define API_AVI_H_
+
+#include "vic_table.h"
+#include "API_General.h"
+
+CDN_API_STATUS cdn_api_set_avi(
+	VIC_MODES vic_mode,
+	VIC_PXL_ENCODING_FORMAT color_mode,
+	BT_TYPE itu_ver);
+
+#endif /*API_AVI_H_ */
+
diff --git a/drivers/video/nxp/hdp/API_General.c b/drivers/video/nxp/hdp/API_General.c
new file mode 100644
index 00000000000..fa3669e5346
--- /dev/null
+++ b/drivers/video/nxp/hdp/API_General.c
@@ -0,0 +1,486 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ ******************************************************************************
+ *
+ * API_General.c
+ *
+ ******************************************************************************
+ */
+
+#include "API_General.h"
+#include "util.h"
+#ifndef __UBOOT__
+#include <string.h>
+#endif
+#include "address.h"
+#include "apb_cfg.h"
+#include "opcodes.h"
+#include "general_handler.h"
+#include "externs.h"
+#include <linux/delay.h>
+#ifndef __UBOOT__
+#include <stdio.h>
+#endif
+
+extern state_struct state;
+
+void cdn_api_init(void)
+{
+	memset(&state, 0, sizeof(state_struct));
+}
+
+CDN_API_STATUS hdp_rx_loadfirmware(unsigned char *imem, int imemsize,
+				   unsigned char *dmem, int dmemsize)
+{
+	int i;
+
+	for (i = 0; i < imemsize; i += 4)
+		if (hdp_rx_apb_write(ADDR_IMEM + i,
+				     (unsigned int)imem[i] << 0 |
+				     (unsigned int)imem[i + 1] << 8 |
+				     (unsigned int)imem[i + 2] << 16 |
+				     (unsigned int)imem[i + 3] << 24))
+			return CDN_ERR;
+	for (i = 0; i < dmemsize; i += 4)
+		if (hdp_rx_apb_write(ADDR_DMEM + i,
+				     (unsigned int)dmem[i] << 0 |
+				     (unsigned int)dmem[i + 1] << 8 |
+				     (unsigned int)dmem[i + 2] << 16 |
+				     (unsigned int)dmem[i + 3] << 24))
+			return CDN_ERR;
+	return CDN_OK;
+}
+
+CDN_API_STATUS cdn_api_loadfirmware(unsigned char *imem, int imemsize,
+				    unsigned char *dmem, int dmemsize)
+{
+	int i;
+
+	for (i = 0; i < imemsize; i += 4)
+		if (cdn_apb_write(ADDR_IMEM + i,
+				  (unsigned int)imem[i] << 0 |
+				  (unsigned int)imem[i + 1] << 8 |
+				  (unsigned int)imem[i + 2] << 16 |
+				  (unsigned int)imem[i + 3] << 24))
+			return CDN_ERR;
+	for (i = 0; i < dmemsize; i += 4)
+		if (cdn_apb_write(ADDR_DMEM + i,
+				  (unsigned int)dmem[i] << 0 |
+				  (unsigned int)dmem[i + 1] << 8 |
+				  (unsigned int)dmem[i + 2] << 16 |
+				  (unsigned int)dmem[i + 3] << 24))
+			return CDN_ERR;
+	return CDN_OK;
+}
+
+CDN_API_STATUS cdn_api_general_test_echo(unsigned int val,
+					 CDN_BUS_TYPE bus_type)
+{
+	CDN_API_STATUS ret;
+
+	if (!state.running) {
+		if (!internal_apb_available())
+			return CDN_BSY;
+		state.bus_type = bus_type;
+		state.rxenable = 1;
+		internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, GENERAL_TEST_ECHO,
+				      1, 4, val);
+		return CDN_STARTED;
+	}
+	if (state.txenable && !internal_mbox_tx_process().txend)
+		return CDN_BSY;
+	if (state.rxenable && !internal_mbox_rx_process().rxend)
+		return CDN_BSY;
+	ret = internal_test_rx_head(MB_MODULE_ID_GENERAL, GENERAL_TEST_ECHO);
+	if (ret != CDN_OK) {
+		state.running = 0;
+		return ret;
+	}
+	state.running = 0;
+	if (val != internal_betoi(state.rxbuffer + INTERNAL_CMD_HEAD_SIZE, 4))
+		return CDN_ERR;
+	return CDN_OK;
+}
+
+CDN_API_STATUS cdn_api_general_test_echo_blocking(unsigned int val,
+						  CDN_BUS_TYPE bus_type)
+{
+	internal_block_function(cdn_api_general_test_echo(val, bus_type));
+}
+
+CDN_API_STATUS cdn_api_general_test_echo_ext(u8 const *msg, u8 *resp,
+					     u16 num_bytes,
+					     CDN_BUS_TYPE bus_type)
+{
+	CDN_API_STATUS ret;
+
+	if (!msg || !resp)
+		return CDN_ERR;
+
+	if ((num_bytes > GENERAL_TEST_ECHO_MAX_PAYLOAD) ||
+	    (num_bytes < GENERAL_TEST_ECHO_MIN_PAYLOAD))
+		return CDN_ERR;
+
+	if (!state.running) {
+		if (!internal_apb_available())
+			return CDN_BSY;
+
+		state.bus_type = bus_type;
+		state.rxenable = 1;
+
+		internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, GENERAL_TEST_ECHO,
+				      1, -num_bytes, msg);
+
+		return CDN_STARTED;
+	}
+
+	if (state.txenable && !internal_mbox_tx_process().txend)
+		return CDN_BSY;
+
+	if (state.rxenable && !internal_mbox_rx_process().rxend)
+		return CDN_BSY;
+
+	ret = internal_test_rx_head(MB_MODULE_ID_GENERAL, GENERAL_TEST_ECHO);
+
+	if (ret != CDN_OK) {
+		state.running = 0;
+		return ret;
+	}
+
+	state.running = 0;
+
+	memcpy(resp, state.rxbuffer + INTERNAL_CMD_HEAD_SIZE, num_bytes);
+
+	if (memcmp(msg, resp, num_bytes) != 0)
+		return CDN_ERR;
+
+	return CDN_OK;
+}
+
+CDN_API_STATUS cdn_api_general_test_echo_ext_blocking(u8 const *msg,
+						      u8 *resp,
+						      u16 num_bytes,
+						      CDN_BUS_TYPE bus_type)
+{
+	internal_block_function(cdn_api_general_test_echo_ext
+				(msg, resp, num_bytes, bus_type));
+}
+
+CDN_API_STATUS cdn_api_general_getcurversion(unsigned short *ver,
+					     unsigned short *verlib)
+{
+	unsigned int vh, vl, vlh, vll;
+
+	if (cdn_apb_read(VER_L << 2, &vl))
+		return CDN_ERR;
+	if (cdn_apb_read(VER_H << 2, &vh))
+		return CDN_ERR;
+	if (cdn_apb_read(VER_LIB_L_ADDR << 2, &vll))
+		return CDN_ERR;
+	if (cdn_apb_read(VER_LIB_H_ADDR << 2, &vlh))
+		return CDN_ERR;
+	*ver = F_VER_MSB_RD(vh) << 8 | F_VER_LSB_RD(vl);
+	*verlib = F_SW_LIB_VER_H_RD(vlh) << 8 | F_SW_LIB_VER_L_RD(vll);
+	return CDN_OK;
+}
+
+CDN_API_STATUS cdn_api_get_event(uint32_t *events)
+{
+	u32 evt[4] = { 0 };
+
+	if (!events) {
+		printf("events pointer is NULL!\n");
+		return CDN_ERR;
+	}
+
+	if (cdn_apb_read(SW_EVENTS0 << 2, &evt[0]) ||
+	    cdn_apb_read(SW_EVENTS1 << 2, &evt[1]) ||
+	    cdn_apb_read(SW_EVENTS2 << 2, &evt[2]) ||
+	    cdn_apb_read(SW_EVENTS3 << 2, &evt[3])) {
+		printf("Failed to read events registers.\n");
+		return CDN_ERR;
+	}
+
+	*events = (evt[0] & 0xFF)
+	    | ((evt[1] & 0xFF) << 8)
+	    | ((evt[2] & 0xFF) << 16)
+	    | ((evt[3] & 0xFF) << 24);
+
+	return CDN_OK;
+}
+
+CDN_API_STATUS cdn_api_get_debug_reg_val(uint16_t *val)
+{
+	u32 dbg[2] = { 0 };
+
+	if (!val) {
+		printf("val pointer is NULL!\n");
+		return CDN_ERR;
+	}
+
+	if (cdn_apb_read(SW_DEBUG_L << 2, &dbg[0]) ||
+	    cdn_apb_read(SW_DEBUG_H << 2, &dbg[1])) {
+		printf("Failed to read debug registers.\n");
+		return CDN_ERR;
+	}
+
+	*val = (u16)((dbg[0] & 0xFF) | ((dbg[1] & 0xFF) << 8));
+
+	return CDN_OK;
+}
+
+CDN_API_STATUS cdn_api_checkalive(void)
+{
+	unsigned int alive, newalive;
+	u8 retries_left = 10;
+
+	if (cdn_apb_read(KEEP_ALIVE << 2, &alive))
+		return CDN_ERR;
+
+	while (retries_left--) {
+		udelay(1);
+
+		if (cdn_apb_read(KEEP_ALIVE << 2, &newalive))
+			return CDN_ERR;
+
+		if (alive == newalive)
+			continue;
+
+		return CDN_OK;
+	}
+
+	printf("%s: keep-alive counter did not increment for 10us...\n", __func__);
+
+	return CDN_BSY;
+}
+
+CDN_API_STATUS cdn_api_checkalive_blocking(void)
+{
+	internal_block_function(cdn_api_checkalive());
+}
+
+CDN_API_STATUS cdn_api_maincontrol(unsigned char mode, unsigned char *resp)
+{
+	if (!state.running) {
+		if (!internal_apb_available())
+			return CDN_BSY;
+		state.bus_type = CDN_BUS_TYPE_APB;
+		state.rxenable = 1;
+		internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL,
+				      GENERAL_MAIN_CONTROL, 1, 1, mode);
+		return CDN_STARTED;
+	}
+	INTERNAL_PROCESS_MESSAGES;
+	internal_opcode_ok_or_return(MB_MODULE_ID_GENERAL,
+				     GENERAL_MAIN_CONTROL_RESP);
+	internal_readmsg(1, 1, resp);
+	return CDN_OK;
+}
+
+CDN_API_STATUS cdn_api_maincontrol_blocking(unsigned char mode,
+					    unsigned char *resp)
+{
+	internal_block_function(cdn_api_maincontrol(mode, resp));
+}
+
+CDN_API_STATUS cdn_api_apbconf(u8 dpcd_bus_sel, u8 dpcd_bus_lock,
+			       u8 hdcp_bus_sel, u8 hdcp_bus_lock,
+			       u8 capb_bus_sel, u8 capb_bus_lock,
+			       u8 *dpcd_resp, u8 *hdcp_resp,
+			       u8 *capb_resp)
+{
+	u8 resp;
+	u8 set = 0;
+
+	if (!state.running) {
+		if (!internal_apb_available())
+			return CDN_BSY;
+
+		state.bus_type = CDN_BUS_TYPE_APB;
+		state.rxenable = 1;
+
+		set |= (dpcd_bus_sel)
+		    ? (1 << GENERAL_BUS_SETTINGS_DPCD_BUS_BIT)
+		    : 0;
+		set |= (dpcd_bus_lock)
+		    ? (1 << GENERAL_BUS_SETTINGS_DPCD_BUS_LOCK_BIT)
+		    : 0;
+		set |= (hdcp_bus_sel)
+		    ? (1 << GENERAL_BUS_SETTINGS_HDCP_BUS_BIT)
+		    : 0;
+		set |= (hdcp_bus_lock)
+		    ? (1 << GENERAL_BUS_SETTINGS_HDCP_BUS_LOCK_BIT)
+		    : 0;
+		set |= (capb_bus_sel)
+		    ? (1 << GENERAL_BUS_SETTINGS_CAPB_OWNER_BIT)
+		    : 0;
+		set |= (capb_bus_lock)
+		    ? (1 << GENERAL_BUS_SETTINGS_CAPB_OWNER_LOCK_BIT)
+		    : 0;
+
+		internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL,
+				      GENERAL_BUS_SETTINGS, 1, 1, set);
+
+		return CDN_STARTED;
+	}
+
+	INTERNAL_PROCESS_MESSAGES;
+	internal_opcode_ok_or_return(MB_MODULE_ID_GENERAL,
+				     GENERAL_BUS_SETTINGS_RESP);
+
+	/* Read one one-byte response */
+	internal_readmsg(1, 1, &resp);
+
+	*dpcd_resp =
+	    (resp & (1 << GENERAL_BUS_SETTINGS_RESP_DPCD_BUS_BIT)) ? 1 : 0;
+	*hdcp_resp =
+	    (resp & (1 << GENERAL_BUS_SETTINGS_RESP_HDCP_BUS_BIT)) ? 1 : 0;
+	*capb_resp =
+	    (resp & (1 << GENERAL_BUS_SETTINGS_RESP_CAPB_OWNER_BIT)) ? 1 : 0;
+
+	return CDN_OK;
+}
+
+CDN_API_STATUS cdn_api_apbconf_blocking(u8 dpcd_bus_sel,
+					u8 dpcd_bus_lock,
+					u8 hdcp_bus_sel,
+					u8 hdcp_bus_lock,
+					u8 capb_bus_sel,
+					u8 capb_bus_lock,
+					u8 *dpcd_resp,
+					u8 *hdcp_resp,
+					u8 *capb_resp)
+{
+	internal_block_function(cdn_api_apbconf(dpcd_bus_sel, dpcd_bus_lock,
+						hdcp_bus_sel, hdcp_bus_lock,
+						capb_bus_sel, capb_bus_lock,
+						dpcd_resp, hdcp_resp,
+						capb_resp));
+}
+
+CDN_API_STATUS cdn_api_setclock(unsigned char mhz)
+{
+	return cdn_apb_write(SW_CLK_H << 2, mhz);
+}
+
+CDN_API_STATUS cdn_api_general_read_register(unsigned int addr,
+					     GENERAL_READ_REGISTER_RESPONSE
+					     *resp)
+{
+	CDN_API_STATUS ret;
+
+	if (!state.running) {
+		if (!internal_apb_available())
+			return CDN_BSY;
+		internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL,
+				      GENERAL_READ_REGISTER, 1, 4, addr);
+		state.bus_type = CDN_BUS_TYPE_APB;
+		state.rxenable = 1;
+		return CDN_STARTED;
+	}
+	INTERNAL_PROCESS_MESSAGES;
+	ret = internal_test_rx_head(MB_MODULE_ID_GENERAL,
+				    GENERAL_READ_REGISTER_RESP);
+	if (ret != CDN_OK)
+		return ret;
+	internal_readmsg(2, 4, &resp->addr, 4, &resp->val);
+	return CDN_OK;
+}
+
+CDN_API_STATUS
+cdn_api_general_read_register_blocking(unsigned int addr,
+				       GENERAL_READ_REGISTER_RESPONSE *resp)
+{
+	internal_block_function(cdn_api_general_read_register(addr, resp));
+}
+
+CDN_API_STATUS cdn_api_general_write_register(unsigned int addr,
+					      unsigned int val)
+{
+	if (!state.running) {
+		if (!internal_apb_available())
+			return CDN_BSY;
+		internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL,
+				      GENERAL_WRITE_REGISTER, 2, 4, addr, 4,
+				      val);
+		state.bus_type = CDN_BUS_TYPE_APB;
+		return CDN_STARTED;
+	}
+	INTERNAL_PROCESS_MESSAGES;
+	return CDN_OK;
+}
+
+CDN_API_STATUS cdn_api_general_write_register_blocking(unsigned int addr,
+						       unsigned int val)
+{
+	internal_block_function(cdn_api_general_write_register(addr, val));
+}
+
+CDN_API_STATUS cdn_api_general_write_field(unsigned int addr,
+					   unsigned char startbit,
+					   unsigned char bitsno,
+					   unsigned int val)
+{
+	if (!state.running) {
+		if (!internal_apb_available())
+			return CDN_BSY;
+		internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, GENERAL_WRITE_FIELD,
+				      4, 4, addr, 1, startbit, 1, bitsno, 4,
+				      val);
+		state.bus_type = CDN_BUS_TYPE_APB;
+		return CDN_STARTED;
+	}
+	INTERNAL_PROCESS_MESSAGES;
+	return CDN_OK;
+}
+
+CDN_API_STATUS cdn_api_general_write_field_blocking(unsigned int addr,
+						    unsigned char startbit,
+						    unsigned char bitsno,
+						    unsigned int val)
+{
+	internal_block_function(cdn_api_general_write_field
+				(addr, startbit, bitsno, val));
+}
+
+CDN_API_STATUS cdn_api_general_phy_test_access(uint8_t *resp)
+{
+	CDN_API_STATUS ret;
+
+	*resp = 0;
+
+	if (!state.running) {
+		if (!internal_apb_available())
+			return CDN_BSY;
+
+		internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, GENERAL_TEST_ACCESS,
+				      0);
+		state.bus_type = CDN_BUS_TYPE_APB;
+		state.rxenable = 1;
+
+		return CDN_STARTED;
+	}
+
+	INTERNAL_PROCESS_MESSAGES;
+
+	ret = internal_test_rx_head(MB_MODULE_ID_GENERAL, GENERAL_TEST_ACCESS);
+
+	if (ret != CDN_OK)
+		return ret;
+
+	internal_readmsg(1, 1, resp);
+
+	return CDN_OK;
+}
+
+CDN_API_STATUS cdn_api_general_phy_test_access_blocking(uint8_t *resp)
+{
+	internal_block_function(cdn_api_general_phy_test_access(resp));
+}
diff --git a/drivers/video/nxp/hdp/API_General.h b/drivers/video/nxp/hdp/API_General.h
new file mode 100644
index 00000000000..0a4caa1ac31
--- /dev/null
+++ b/drivers/video/nxp/hdp/API_General.h
@@ -0,0 +1,275 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ ******************************************************************************
+ *
+ * API_General.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef API_GENERAL_H_
+#define API_GENERAL_H_
+
+#ifndef __UBOOT__
+#include <stdint.h>
+#else
+#include <common.h>
+#endif
+
+#define GENERAL_TEST_ECHO_MAX_PAYLOAD 100
+#define GENERAL_TEST_ECHO_MIN_PAYLOAD 1
+
+/**
+ * \addtogroup GENERAL_API
+ * \{
+ */
+/** status code returned by API calls */
+typedef enum {
+    /** operation succedded */
+	CDN_OK = 0,
+    /** CEC operation succedded */
+	CDN_CEC_ERR_NONE = 0,
+    /** mailbox is currently sending or receiving data */
+	CDN_BSY,
+    /** message set up and ready to be sent, no data sent yet */
+	CDN_STARTED,
+    /** error encountered while reading/writing APB */
+	CDN_ERR,
+    /** reply returned with bad opcode */
+	CDN_BAD_OPCODE,
+    /** reply returned with bad module */
+	CDN_BAD_MODULE,
+    /** reply not supported mode */
+	CDN_ERROR_NOT_SUPPORTED,
+    /** Invalid argument passed to CEC API function */
+	CDN_CEC_ERR_INVALID_ARG,
+    /**
+     * TX Buffer for CEC Messages is full. This is applicable only
+     * when TX Buffers for CEC Messages are implemented in the HW.
+     */
+	CDN_CEC_ERR_TX_BUFF_FULL,
+    /** No Messages in the RX Buffers are present. */
+	CDN_CEC_ERR_RX_BUFF_EMPTY,
+    /** Timeout during TX operation */
+	CDN_CEC_ERR_TX_TIMEOUT,
+    /** Timeout during RX operation */
+	CDN_CEC_ERR_RX_TIMEOUT,
+    /** Data transmision fail. */
+	CDN_CEC_ERR_TX_FAILED,
+    /** Data reception fail. */
+	CDN_CEC_ERR_RX_FAILED,
+    /** Operation aborted. */
+	CDN_CEC_ERR_ABORT,
+    /** All Logical Addresses are in use. */
+	CDN_CEC_ERR_ALL_LA_IN_USE,
+} CDN_API_STATUS;
+
+typedef enum {
+	CDN_BUS_TYPE_APB = 0,
+	CDN_BUS_TYPE_SAPB = 1
+} CDN_BUS_TYPE;
+
+/**
+ * GENERAL_Read_Register response struct
+ */
+typedef struct {
+	unsigned int addr;
+	unsigned int val;
+} GENERAL_READ_REGISTER_RESPONSE;
+
+/**
+ * \brief set up API, must be called before any other API call
+ */
+void cdn_api_init(void);
+
+/**
+ * \brief Loads firmware
+ *
+ * \param iMem - pointer to instruction memory
+ * \param imemSize - size of instruction memory buffer
+ * \param dMem - pointer to data memory
+ * \param dmemSize - size of data memory buffer
+ * \return 0 if success, 1 if apb error encountered, 2 if CPU
+ *         isn't alive after loading firmware
+ *
+ * This function does not require initialisation by #CDN_API_Init
+ */
+
+CDN_API_STATUS cdn_api_loadfirmware(unsigned char *imem,
+				    int imemsize,
+				    unsigned char *dmem, int dmemsize);
+/**
+ * \brief debug echo command for APB
+ * \param val - value to echo
+ * \return status
+ *
+ * will return #CDN_ERROR if reply message doesn't match request
+ */
+CDN_API_STATUS cdn_api_general_test_echo(unsigned int val,
+					 CDN_BUS_TYPE bus_type);
+
+/**
+ * \brief blocking version of #CDN_API_General_Test_Echo
+ */
+CDN_API_STATUS cdn_api_general_test_echo_blocking(unsigned int val,
+						  CDN_BUS_TYPE bus_type);
+
+/**
+ * \brief Extended Echo test for mailbox.
+ *
+ * This test will send msg buffer to firmware's mailbox and
+ * receive it back to the resp buffer. Received data will be
+ * check against data sent and status will be returned as well
+ * as received data.
+ *
+ * \param msg - Pointer to a buffer to send.
+ * \param resp - Pointer to buffer for receiving msg payload back.
+ * \param num_bytes - Number of bytes to send and receive.
+ * \param bus_type Bus type.
+ * \return status
+ *
+ * will return #CDN_ERROR if reply message doesn't match request or if
+ *  arguments are invalid.
+ */
+CDN_API_STATUS cdn_api_general_test_echo_ext(u8 const *msg, u8 *resp,
+					     u16 num_bytes,
+					     CDN_BUS_TYPE bus_type);
+
+/**
+ * \brief blocking version of #CDN_API_General_Test_Echo_Ext
+ */
+CDN_API_STATUS cdn_api_general_test_echo_ext_blocking(u8 const *msg,
+						      u8 *resp,
+						      u16 num_bytes,
+						      CDN_BUS_TYPE bus_type);
+
+/**
+ * \brief get current version
+ * \param [out] ver - fw version
+ * \param [out] libver - lib version
+ * \return status
+ *
+ * this function does not require #CDN_API_Init
+ */
+CDN_API_STATUS cdn_api_general_getcurversion(unsigned short *ver,
+					     unsigned short *verlib);
+
+/**
+ * \brief read event value
+ * \param [out] event - pointer to store 32-bit events value
+ * \return status
+ *
+ * this function does not require #CDN_API_Init
+ */
+CDN_API_STATUS cdn_api_get_event(uint32_t *events);
+
+/**
+ * \brief read debug register value
+ * \param [out] val - pointer to store 16-bit debug reg value
+ * \return status
+ *
+ * this function does not require #CDN_API_Init
+ */
+CDN_API_STATUS cdn_api_get_debug_reg_val(uint16_t *val);
+
+/**
+ * \brief check if KEEP_ALIVE register changed
+ * \return #CDN_BSY if KEEP_ALIVE not changed, #CDN_OK if changed and #CDN_ERR
+ * if error occurred while reading
+ */
+CDN_API_STATUS cdn_api_checkalive(void);
+
+/**
+ * \breif blocking version of #CDN_API_CheckAlive
+ * blocks until KEEP_ALIVE register changes or error occurs while reading
+ */
+CDN_API_STATUS cdn_api_checkalive_blocking(void);
+
+/**
+ * \brief set cpu to standby or active
+ * \param [in] state - 1 for active, 0 for standby
+ * \return status
+ */
+CDN_API_STATUS cdn_api_maincontrol(unsigned char mode, unsigned char *resp);
+
+/**
+ * \breif blocking version of #CDN_API_MainControl
+ */
+CDN_API_STATUS cdn_api_maincontrol_blocking(unsigned char mode,
+					    unsigned char *resp);
+
+/**
+ * \brief settings for APB
+ *
+ * Sends GENERAL_APB_CONF Command via regular Mailbox.
+ * @param dpcd_bus_sel Set DPCD to use selected bus (0 for APB or 1 for SAPB)
+ * @param dpcd_bus_lock Lock bus type. Aftern that bus type cannot be changed
+ * by using this function.
+ * @param hdcp_bus_sel Same meaning as for DPCD but for HDCP.
+ * @param hdcp_bus_lock Same meaning as for DPCD but for HDCP.
+ * @param capb_bus_sel Same meaning as for DPCD but for Cipher APB.
+ * @param capb_bus_lock Same meaning as for DPCD but for Cipher APB.
+ * @param dpcd_resp [out] Status of the operation.
+ * If set to zero then DPCD bus type was successfully changed.
+ * If not then error occurred, most likely due to locked DPCD bus.
+ * @param hdcp_resp [out] Same as for DPCD but for HDCP.
+ * @param capb_resp [out] Same as for DPCD but for Cipher APB.
+ *
+ * \return status
+ */
+CDN_API_STATUS cdn_api_apbconf(u8 dpcd_bus_sel, u8 dpcd_bus_lock,
+			       u8 hdcp_bus_sel, u8 hdcp_bus_lock,
+			       u8 capb_bus_sel, u8 capb_bus_lock,
+			       u8 *dpcd_resp, u8 *hdcp_resp,
+			       u8 *capb_resp);
+
+/**
+ * blocking version of #CDN_API_MainControl
+ */
+CDN_API_STATUS cdn_api_apbconf_blocking(u8 dpcd_bus_sel,
+					u8 dpcd_bus_lock,
+					u8 hdcp_bus_sel,
+					u8 hdcp_bus_lock,
+					u8 capb_bus_sel,
+					u8 capb_bus_lock,
+					u8 *dpcd_resp,
+					u8 *hdcp_resp,
+					u8 *capb_resp);
+
+/**
+ * \brief set the  xtensa clk, write this api before turn on the cpu
+ */
+CDN_API_STATUS cdn_api_setclock(unsigned char mhz);
+
+CDN_API_STATUS cdn_api_general_read_register(unsigned int addr,
+					     GENERAL_READ_REGISTER_RESPONSE
+					     *resp);
+CDN_API_STATUS
+cdn_api_general_read_register_blocking(unsigned int addr,
+				       GENERAL_READ_REGISTER_RESPONSE *resp);
+CDN_API_STATUS cdn_api_general_write_register(unsigned int addr,
+					      unsigned int val);
+CDN_API_STATUS cdn_api_general_write_register_blocking(unsigned int addr,
+						       unsigned int val);
+CDN_API_STATUS cdn_api_general_write_field(unsigned int addr,
+					   unsigned char startbit,
+					   unsigned char bitsno,
+					   unsigned int val);
+CDN_API_STATUS cdn_api_general_write_field_blocking(unsigned int addr,
+						    unsigned char startbit,
+						    unsigned char bitsno,
+						    unsigned int val);
+CDN_API_STATUS cdn_api_general_phy_test_access(u8 *resp);
+CDN_API_STATUS cdn_api_general_phy_test_access_blocking(u8 *resp);
+CDN_API_STATUS hdp_rx_loadfirmware(unsigned char *imem,
+				   int imemsize,
+				   unsigned char *dmem,
+				   int dmemsize);
+#endif
diff --git a/drivers/video/nxp/hdp/API_HDMITX.c b/drivers/video/nxp/hdp/API_HDMITX.c
new file mode 100644
index 00000000000..b1b3061028d
--- /dev/null
+++ b/drivers/video/nxp/hdp/API_HDMITX.c
@@ -0,0 +1,486 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_HDMITX.c
+ *
+ ******************************************************************************
+ */
+
+#include "API_HDMITX.h"
+#include "util.h"
+#include "opcodes.h"
+#ifndef __UBOOT__
+#include "string.h"
+#include "stdio.h"
+#endif
+#include "mhl_hdtx_top.h"
+#include "source_phy.h"
+#include "address.h"
+#include "source_car.h"
+#include "source_vif.h"
+#include "general_handler.h"
+
+CDN_API_STATUS CDN_API_HDMITX_DDC_READ(HDMITX_TRANS_DATA *data_in,
+				       HDMITX_TRANS_DATA *data_out)
+{
+	internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_READ,
+				    CDN_BUS_TYPE_APB, 3,
+				    1, data_in->slave,
+				    1, data_in->offset,
+				    2, data_in->len
+				   );
+	internal_readmsg(5,
+			 1, &data_out->status,
+			 1, &data_out->slave,
+			 1, &data_out->offset,
+			 2, &data_out->len,
+			 0, &data_out->buff
+			);
+	return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_DDC_READ_blocking(HDMITX_TRANS_DATA *data_in,
+						HDMITX_TRANS_DATA *data_out)
+{
+	internal_block_function(CDN_API_HDMITX_DDC_READ(data_in, data_out));
+}
+
+CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE(HDMITX_TRANS_DATA *data_in,
+					HDMITX_TRANS_DATA *data_out)
+{
+	printf("foo: %x\n", data_in->buff[0]);
+	internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_WRITE,
+				    CDN_BUS_TYPE_APB, 4,
+				    1, data_in->slave,
+				    1, data_in->offset,
+				    2, data_in->len,
+				    -data_in->len, data_in->buff
+				   );
+	internal_readmsg(4,
+			 1, &data_out->status,
+			 1, &data_out->slave,
+			 1, &data_out->offset,
+			 2, &data_out->len
+			);
+	return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE_blocking(HDMITX_TRANS_DATA *data_in,
+						 HDMITX_TRANS_DATA *data_out)
+{
+	internal_block_function(CDN_API_HDMITX_DDC_WRITE(data_in, data_out));
+}
+
+CDN_API_STATUS CDN_API_HDMITX_DDC_UPDATE_READ(HDMITX_TRANS_DATA *data_out)
+{
+	internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_UPDATE_READ,
+				    CDN_BUS_TYPE_APB, 0);
+	internal_readmsg(2,
+			 1, &data_out->status,
+			 0, &data_out->buff
+			);
+	return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_DDC_UPDATE_READ_blocking(HDMITX_TRANS_DATA
+						       *data_out)
+{
+	internal_block_function(CDN_API_HDMITX_DDC_UPDATE_READ(data_out));
+}
+
+CDN_API_STATUS CDN_API_HDMITX_READ_EDID(unsigned char block,
+					unsigned char segment,
+					HDMITX_TRANS_DATA *data_out)
+{
+	internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_EDID,
+				    CDN_BUS_TYPE_APB, 2,
+				    1, block,
+				    1, segment
+				   );
+	internal_readmsg(5,
+			 1, &data_out->status,
+			 1, &data_out->slave,
+			 1, &data_out->offset,
+			 2, &data_out->len,
+			 0, &data_out->buff
+			);
+	return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_READ_EDID_blocking(unsigned char block,
+						 unsigned char segment,
+						 HDMITX_TRANS_DATA *data_out)
+{
+	internal_block_function(CDN_API_HDMITX_READ_EDID(block, segment,
+							 data_out));
+}
+
+CDN_API_STATUS
+CDN_API_HDMITX_Set_Mode_blocking(HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE protocol,
+				 unsigned int character_rate)
+{
+	CDN_API_STATUS ret;
+	GENERAL_READ_REGISTER_RESPONSE resp;
+	HDMITX_TRANS_DATA data_in;
+	HDMITX_TRANS_DATA data_out;
+	unsigned char buff = 1;
+
+	/*enable/disable  scrambler; */
+	if (protocol == HDMI_TX_MODE_HDMI_2_0) {
+		if (character_rate > 340000)
+			buff = 3; /*enable scrambling + TMDS_Bit_Clock_Ratio */
+		else
+			buff = 1; /*enable scrambling */
+	} else {
+		buff = 0; /*disable scrambling */
+	}
+
+	data_in.buff = &buff;
+	data_in.len = 1;
+	data_in.slave = 0x54;
+	data_in.offset = 0x20; /*TMDS config */
+#if 1
+	if (protocol == HDMI_TX_MODE_HDMI_2_0)
+		ret =  CDN_API_HDMITX_DDC_WRITE_blocking(&data_in, &data_out);
+
+#endif
+	ret = cdn_api_general_read_register_blocking(ADDR_SOURCE_MHL_HD +
+						     (HDTX_CONTROLLER << 2),
+						     &resp);
+
+	/*remove data enable */
+	resp.val = resp.val & (~(F_DATA_EN(1)));
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_CONTROLLER << 2),
+						      resp.val);
+
+	if (protocol == HDMI_TX_MODE_HDMI_2_0) {
+		if (character_rate > 3400000) {
+			/* Set TMDS clock ratio */
+			ret = cdn_api_general_write_register_blocking
+				(ADDR_SOURCE_MHL_HD +
+				 (HDTX_CLOCK_REG_0 << 2),
+				 F_DATA_REGISTER_VAL_0(0x00000));
+			ret = cdn_api_general_write_register_blocking
+				(ADDR_SOURCE_MHL_HD +
+				 (HDTX_CLOCK_REG_1 << 2),
+				 F_DATA_REGISTER_VAL_1(0xFFFFF));
+		}
+	}
+
+	/*set hdmi mode and preemble mode */
+	resp.val = resp.val & (~(F_HDMI_MODE(3)));
+	resp.val = resp.val & (~(F_HDMI2_PREAMBLE_EN(1)));
+
+	resp.val = (resp.val) | (F_HDMI_MODE(protocol)) |
+		(F_HDMI2_PREAMBLE_EN(1));
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_CONTROLLER << 2),
+						      resp.val);
+
+	/*data enable */
+	resp.val |= F_DATA_EN(1);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_CONTROLLER << 2),
+						      resp.val);
+
+	return ret;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_Init_blocking(void)
+{
+	CDN_API_STATUS ret;
+
+	/*init phy and CAR and HDMI TX */
+/*	ret = cdn_api_general_write_register_blocking
+		(ADDR_SOURCD_PHY + (LANES_CONFIG<<2),
+		F_SOURCE_PHY_LANE0_SWAP(0) |
+		F_SOURCE_PHY_LANE1_SWAP(1) |
+		F_SOURCE_PHY_LANE2_SWAP(2) |
+		F_SOURCE_PHY_LANE3_SWAP(3) |
+		F_SOURCE_PHY_COMB_BYPASS(0) |
+		F_SOURCE_PHY_20_10(1)); */
+
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCD_PHY +
+						      (PHY_DATA_SEL << 2),
+						      F_SOURCE_PHY_MHDP_SEL(1));
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_HPD << 2),
+						      F_HPD_VALID_WIDTH(4) |
+						      F_HPD_GLITCH_WIDTH(0));
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_CONTROLLER << 2),
+						      F_HDMI_MODE(1) |
+						      F_AUTO_MODE(0) |
+						      F_GCP_EN(1) |
+						      F_DATA_EN(1) |
+						      F_CLEAR_AVMUTE(1) |
+						      F_HDMI2_PREAMBLE_EN(1) |
+						      F_HDMI2_CTRL_IL_MODE(1) |
+						      F_PIC_3D(0XF) |
+						      F_BCH_EN(1));
+	/* open CARS */
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+						      (SOURCE_PHY_CAR << 2),
+						      0xF);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+						      (SOURCE_HDTX_CAR << 2),
+						      0xFF);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+						      (SOURCE_PKT_CAR << 2),
+						      0xF);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+						      (SOURCE_AIF_CAR << 2),
+						      0xF);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+						      (SOURCE_CIPHER_CAR << 2),
+						      0xF);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+						      (SOURCE_CRYPTO_CAR << 2),
+						      0xF);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR +
+						      (SOURCE_CEC_CAR << 2), 3);
+
+	/*init vif */
+	/*ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_VIF
+	  +(HSYNC2VSYNC_POL_CTRL<<2), F_HPOL(0) | F_VPOL(0)); */
+
+	return ret;
+}
+
+
+CDN_API_STATUS CDN_API_HDMITX_SetVic_blocking(VIC_MODES vicMode, int bpp,
+					      VIC_PXL_ENCODING_FORMAT format)
+{
+	CDN_API_STATUS ret;
+	GENERAL_READ_REGISTER_RESPONSE resp;
+	unsigned int vsync_lines = vic_table[vicMode][VSYNC];
+	unsigned int eof_lines = vic_table[vicMode][TYPE_EOF];
+	unsigned int sof_lines = vic_table[vicMode][SOF];
+	unsigned int hblank = vic_table[vicMode][H_BLANK];
+	unsigned int hactive = vic_table[vicMode][H_TOTAL] - hblank;
+	unsigned int vblank = vsync_lines + eof_lines + sof_lines;
+	unsigned int vactive = vic_table[vicMode][V_TOTAL] - vblank;
+	unsigned int hfront = vic_table[vicMode][FRONT_PORCH];
+	unsigned int hback = vic_table[vicMode][BACK_PORCH];
+	unsigned int vfront = eof_lines;
+	unsigned int hsync = hblank - hfront - hback;
+	unsigned int vsync = vsync_lines;
+	unsigned int vback = sof_lines;
+	unsigned int v_h_polarity = ((vic_table[vicMode][HSYNC_POL] ==
+				      ACTIVE_LOW) ? 0 : 1) +
+		((vic_table[vicMode][VSYNC_POL] == ACTIVE_LOW) ? 0 : 2);
+
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (SCHEDULER_H_SIZE << 2),
+						      (hactive << 16) + hblank);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (SCHEDULER_V_SIZE << 2),
+						      (vactive << 16) + vblank);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_SIGNAL_FRONT_WIDTH
+						       << 2),
+						      (vfront << 16) + hfront);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_SIGNAL_SYNC_WIDTH
+						       << 2),
+						      (vsync << 16) + hsync);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_SIGNAL_BACK_WIDTH
+						       << 2),
+						      (vback << 16) + hback);
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_VIF +
+						      (HSYNC2VSYNC_POL_CTRL
+						       << 2),
+						      v_h_polarity);
+
+	/*  Data Enable is 1 */
+
+	/*Reset Data Enable */
+	cdn_api_general_read_register_blocking(ADDR_SOURCE_MHL_HD +
+					       (HDTX_CONTROLLER << 2), &resp);
+
+	/*reset data enable */
+	resp.val = resp.val & (~(F_DATA_EN(1)));
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_CONTROLLER << 2),
+						      resp.val);
+
+	/*set bpp */
+	resp.val = resp.val &  (~(F_VIF_DATA_WIDTH(3)));
+	switch (bpp) {
+	case 8:
+		resp.val = resp.val | (F_VIF_DATA_WIDTH(0));
+		break;
+
+	case 10:
+		resp.val = resp.val | (F_VIF_DATA_WIDTH(1));
+		break;
+
+	case 12:
+		resp.val = resp.val | (F_VIF_DATA_WIDTH(2));
+		break;
+
+	case 16:
+		resp.val = resp.val | (F_VIF_DATA_WIDTH(3));
+		break;
+	}
+
+	/*select color encoding */
+	resp.val = resp.val &  (~(F_HDMI_ENCODING(3)));
+	switch (format) {
+	case PXL_RGB:
+
+		resp.val = resp.val | (F_HDMI_ENCODING(0));
+		break;
+
+	case YCBCR_4_4_4:
+		resp.val = resp.val | (F_HDMI_ENCODING(2));
+		break;
+
+	case YCBCR_4_2_2:
+		resp.val = resp.val | (F_HDMI_ENCODING(1));
+		break;
+
+	case YCBCR_4_2_0:
+		resp.val = resp.val | (F_HDMI_ENCODING(3));
+		break;
+	case Y_ONLY:
+		/*not exist in hdmi */
+		break;
+	}
+
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_CONTROLLER << 2),
+						      resp.val);
+
+	/*set data enable */
+	resp.val = resp.val  | (F_DATA_EN(1));
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_CONTROLLER << 2),
+						      resp.val);
+
+	return ret;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_ForceColorDepth_blocking(unsigned char force,
+						       unsigned char val)
+{
+	unsigned int valToWrite = F_COLOR_DEPTH_VAL(val) |
+		F_COLOR_DEPTH_FORCE(force);
+
+	return cdn_api_general_write_register_blocking
+		(ADDR_SOURCE_MHL_HD +
+		 (GCP_FORCE_COLOR_DEPTH_CODING << 2),
+		 valToWrite);
+}
+
+CDN_API_STATUS CDN_API_HDMITX_ReadEvents(uint32_t *events)
+{
+	CDN_API_STATUS ret;
+
+	if (!state.running) {
+		if (!internal_apb_available())
+			return CDN_BSY;
+
+		internal_tx_mkfullmsg(MB_MODULE_ID_HDMI_TX, HDMI_TX_EVENTS, 0);
+		state.rxenable = 1;
+		state.bus_type = CDN_BUS_TYPE_APB;
+
+		return CDN_STARTED;
+	}
+
+	INTERNAL_PROCESS_MESSAGES;
+
+	ret = internal_test_rx_head(MB_MODULE_ID_HDMI_TX, HDMI_TX_EVENTS);
+
+	if (ret != CDN_OK)
+		return ret;
+
+	internal_readmsg(1, 4, events);
+
+	return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_ReadEvents_blocking(uint32_t *events)
+{
+	internal_block_function(CDN_API_HDMITX_ReadEvents(events));
+}
+
+CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus(uint8_t *hpd_sts)
+{
+	CDN_API_STATUS ret;
+
+	if (!state.running) {
+		if (!internal_apb_available())
+			return CDN_BSY;
+
+		/*
+		 * General Module is used here for obtaining HPD State because
+		 * HDMI TX Module is inactive in stand-by mode, thus cannot
+		 * return it.
+		 */
+		internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL,
+				      GENERAL_GET_HPD_STATE, 0);
+		state.rxenable = 1;
+		state.bus_type = CDN_BUS_TYPE_APB;
+
+		return CDN_STARTED;
+	}
+
+	INTERNAL_PROCESS_MESSAGES;
+
+	ret = internal_test_rx_head(MB_MODULE_ID_GENERAL,
+				    GENERAL_GET_HPD_STATE);
+
+	if (ret != CDN_OK)
+		return ret;
+
+	internal_readmsg(1, 1, hpd_sts);
+
+	return CDN_OK;
+}
+
+CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus_blocking(uint8_t *hpd_sts)
+{
+	internal_block_function(CDN_API_HDMITX_GetHpdStatus(hpd_sts));
+}
+
diff --git a/drivers/video/nxp/hdp/API_HDMITX.h b/drivers/video/nxp/hdp/API_HDMITX.h
new file mode 100644
index 00000000000..099fd118714
--- /dev/null
+++ b/drivers/video/nxp/hdp/API_HDMITX.h
@@ -0,0 +1,182 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_HDMITX.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef _API_HDMITX_H_
+# define _API_HDMITX_H_
+
+# include "API_General.h"
+# include "hdmi.h"
+# include "vic_table.h"
+
+/**
+ * \addtogroup HDMI_TX_API
+ * \{
+ */
+
+# define HDMI_TX_EVENT_CODE_HPD_HIGH                  0x01
+# define HDMI_TX_EVENT_CODE_HPD_LOW                   0x02
+# define HDMI_TX_EVENT_CODE_HPD_STATE_LOW             0x00
+# define HDMI_TX_EVENT_CODE_HPD_STATE_HIGH            0x08
+
+typedef struct {
+	/** if used to return data, this pointer is set (instead of being a
+	 *  destination to copy data to
+	 */
+	unsigned char *buff;
+	HDMI_I2C_STATUS status;
+	unsigned short len;
+	unsigned char slave;
+	unsigned char offset;
+} HDMITX_TRANS_DATA;
+
+
+typedef enum {
+	HDMI_TX_MODE_DVI,
+	HDMI_TX_MODE_HDMI_1_4,
+	HDMI_TX_MODE_HDMI_2_0,
+} HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE;
+
+/**
+ * \brief I2C read transaction
+ * \param [in]  data_in  - fields used: len, slave, offset
+ * \param [out] data_out - fields used: all
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_DDC_READ(HDMITX_TRANS_DATA *data_in,
+				       HDMITX_TRANS_DATA *data_out);
+CDN_API_STATUS CDN_API_HDMITX_DDC_READ_blocking(HDMITX_TRANS_DATA *data_in,
+						HDMITX_TRANS_DATA *data_out);
+
+/**
+ * \brief I2C write transaction
+ * \param [in]  data_in  - fields used: len, slave, offset, buff
+ * \param [out] data_out - fields used: status, len, slave, offset
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE(HDMITX_TRANS_DATA *data_in,
+					HDMITX_TRANS_DATA *data_out);
+CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE_blocking(HDMITX_TRANS_DATA *data_in,
+						 HDMITX_TRANS_DATA *data_out);
+
+/**
+ * \brief I2C update read
+ * \param [out] data_out - fields used: status, buff
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_DDC_UPDATE_READ(HDMITX_TRANS_DATA *data_out);
+CDN_API_STATUS
+CDN_API_HDMITX_DDC_UPDATE_READ_blocking(HDMITX_TRANS_DATA *data_out);
+
+/**
+ * \brief I2C read edid
+ * \param [in]  block    - EDID block
+ * \pram  [in]  segment  - EDID segment
+ * \param [out] data_out - fields used: status, buff, slave (as block),
+ * offset (as segment), len
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_READ_EDID(unsigned char block,
+					unsigned char segment,
+					HDMITX_TRANS_DATA *data_out);
+CDN_API_STATUS CDN_API_HDMITX_READ_EDID_blocking(unsigned char block,
+						 unsigned char segment,
+						 HDMITX_TRANS_DATA *data_out);
+
+/**
+ * \brief set hdmi protocol type (DVI,1.x,2.x) (send scrambler command over
+ * scdc and set bits in controller)
+ * \param [in]  protocol    - type
+ * \returns status
+ */
+/*CDN_API_STATUS
+CDN_API_HDMITX_Set_Mode_blocking(HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE protocol,
+				 float character_rate);*/
+CDN_API_STATUS
+CDN_API_HDMITX_Set_Mode_blocking(HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE protocol,
+				 unsigned int character_rate);
+/**
+ * \brief init hdmi registers
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_Init_blocking(void);
+
+/**
+ * \brief change to vid id vicMode
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_SetVic_blocking(VIC_MODES vicMode,
+					      int bpp,
+					      VIC_PXL_ENCODING_FORMAT format);
+
+/**
+ * \brief option to force color depth in the gcp or not force (HW mode)
+ * \returns status
+ */
+CDN_API_STATUS CDN_API_HDMITX_ForceColorDepth_blocking(unsigned char force,
+						       unsigned char val);
+
+/**
+ * \brief send HDMI_TX_TX_READ_EVENTS command
+ */
+CDN_API_STATUS CDN_API_HDMITX_ReadEvents(uint32_t *events);
+
+/**
+ * blocking version of #CDN_API_HDMITX_ReadEvents
+ */
+CDN_API_STATUS CDN_API_HDMITX_ReadEvents_blocking(uint32_t *events);
+
+/**
+ * \brief get current HPD status
+ */
+CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus(uint8_t *hpd_sts);
+
+/**
+ * \brief blocking version of #CDN_API_HDMITX_GetHpdStatus
+ */
+CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus_blocking(uint8_t *hpd_sts);
+
+#endif
+
diff --git a/drivers/video/nxp/hdp/API_Infoframe.c b/drivers/video/nxp/hdp/API_Infoframe.c
new file mode 100644
index 00000000000..acd9612d4a5
--- /dev/null
+++ b/drivers/video/nxp/hdp/API_Infoframe.c
@@ -0,0 +1,157 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_Infoframe.c
+ *
+ ******************************************************************************
+ */
+
+#include "API_Infoframe.h"
+#include "address.h"
+#include "source_pif.h"
+#include "externs.h"
+#ifndef __UBOOT__
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#else
+#include <common.h>
+#include <asm/io.h>
+#endif
+#include "util.h"
+
+#define BANK_OFFSET 0x0
+
+/* Redefined because of compiler warnings about 32 bit shift left */
+#ifdef F_DATA_WR
+#undef F_DATA_WR
+#define F_DATA_WR(a_) ((uint32_t)(a_))
+#endif
+
+static CDN_API_STATUS infoframeSet(unsigned char entry_id,
+				   unsigned char packet_len,
+				   unsigned int *packet,
+				   unsigned char packet_type,
+				   unsigned char active_idle)
+{
+	unsigned int idx;
+	unsigned int activeIdleBit = (0 == active_idle) ? 0 : 0x20000;
+	/*invalidate entry */
+	if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+			  (SOURCE_PIF_PKT_ALLOC_REG << 2),
+			  activeIdleBit | F_PKT_ALLOC_ADDRESS(entry_id)))
+		return CDN_ERR;
+	if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+			  (SOURCE_PIF_PKT_ALLOC_WR_EN << 2),
+			  F_PKT_ALLOC_WR_EN(1)))
+		return CDN_ERR;
+
+	/*flush fifo 1 */
+	if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+			  (SOURCE_PIF_FIFO1_FLUSH << 2),
+			  F_FIFO1_FLUSH(1)))
+		return CDN_ERR;
+
+	/*write packet into memory */
+	for (idx = 0; idx < packet_len; idx++)
+		if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+				  (SOURCE_PIF_DATA_WR << 2),
+				  F_DATA_WR(packet[idx])))
+			return CDN_ERR;
+
+	/*write entry id */
+	if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+			  (SOURCE_PIF_WR_ADDR << 2),
+			  F_WR_ADDR(entry_id)))
+		return CDN_ERR;
+
+	/*write request */
+	if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+			  (SOURCE_PIF_WR_REQ << 2),
+			  F_HOST_WR(1)))
+		return CDN_ERR;
+
+	/*update entry */
+	if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+			  (SOURCE_PIF_PKT_ALLOC_REG << 2),
+			  activeIdleBit | F_TYPE_VALID(1) |
+			  F_PACKET_TYPE(packet_type) |
+			  F_PKT_ALLOC_ADDRESS(entry_id)))
+		return CDN_ERR;
+	if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+			  (SOURCE_PIF_PKT_ALLOC_WR_EN << 2),
+			  F_PKT_ALLOC_WR_EN(1)))
+		return CDN_ERR;
+
+	return CDN_OK;
+}
+
+CDN_API_STATUS cdn_api_infoframeset(unsigned char entry_id,
+				    unsigned char packet_len,
+				    unsigned int *packet,
+				    unsigned char packet_type)
+{
+	return infoframeSet(entry_id, packet_len, packet, packet_type, 1);
+}
+
+CDN_API_STATUS cdn_api_infoframesetnoactiveidle(unsigned char entry_id,
+						unsigned char packet_len,
+						unsigned int *packet,
+						unsigned char packet_type)
+{
+	return infoframeSet(entry_id, packet_len, packet, packet_type, 0);
+}
+
+CDN_API_STATUS cdn_api_infoframeremove(unsigned char entry_id)
+{
+	/*invalidate entry */
+	if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+			  (SOURCE_PIF_PKT_ALLOC_REG << 2),
+			  0x20000 | F_PKT_ALLOC_ADDRESS(entry_id)))
+		return CDN_ERR;
+	if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF |
+			  (SOURCE_PIF_PKT_ALLOC_WR_EN << 2),
+			  F_PKT_ALLOC_WR_EN(1)))
+		return CDN_ERR;
+
+	return CDN_OK;
+}
+
diff --git a/drivers/video/nxp/hdp/API_Infoframe.h b/drivers/video/nxp/hdp/API_Infoframe.h
new file mode 100644
index 00000000000..a384bb2a600
--- /dev/null
+++ b/drivers/video/nxp/hdp/API_Infoframe.h
@@ -0,0 +1,68 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * API_Infoframe.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef API_INFOFRAME_H
+# define API_INFOFRAME_H
+
+/**
+ * \addtogroup INFO_FRAME_API
+ * \{
+ */
+
+# include "API_General.h"
+
+CDN_API_STATUS cdn_api_infoframeset(unsigned char entry_id,
+				    unsigned char packet_len,
+				    unsigned int *packet,
+				    unsigned char packet_type);
+CDN_API_STATUS cdn_api_infoframesetnoactiveidle(unsigned char entry_id,
+						unsigned char packet_len,
+						unsigned int *packet,
+						unsigned char packet_type);
+CDN_API_STATUS cdn_api_infoframeremove(unsigned char entry_id);
+
+#endif
+
diff --git a/drivers/video/nxp/hdp/Makefile b/drivers/video/nxp/hdp/Makefile
new file mode 100644
index 00000000000..07d22104750
--- /dev/null
+++ b/drivers/video/nxp/hdp/Makefile
@@ -0,0 +1,48 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-$(CONFIG_VIDEO_NXP_HDP) += \
+	API_General.o \
+	test_base_sw.o \
+	API_AVI.o \
+	API_Infoframe.o \
+	util.o \
+	vic_table.o \
+	edid_parser.o \
+	API_AFE.o \
+	API_HDMITX.o \
+	API_AFE_t28hpc_hdmitx.o
+
+# common objects
+#obj-y += \
+#	API_General.o  API_AVI.o API_Infoframe.o \
+#	util.o vic_table.o test_base_sw.o \
+#	avgen_drv.o edid_parser.o \
+#	API_AFE.o
+
+#DP objects
+#	API_DPTX.o \
+#	API_AFE_mcu2_dp.o\
+#	mhdp_firmware.o
+
+#hdmi objects
+#obj-y += \
+#	API_HDMITX.o \
+#	API_HDCP.o \
+#	API_AFE_t28hpc_hdmitx.o
+#
+
+# USE for QM
+#	blob/API_AFE_mcu1_dp.o
+#	blob/API_AFE_ss28fdsoi_kiran_hdmitx.o
+#	blob/ss28fdsoi_hdmitx_table.o
+#	blob/hdmitx_firmware.o
+#	blob/mhdp_firmware.o
+
+# Use for mscale
+#	API_AFE_mcu2_dp.o ()
+#	API_AFE_t28hpc_hdmitx.c
+#
diff --git a/drivers/video/nxp/hdp/address.h b/drivers/video/nxp/hdp/address.h
new file mode 100644
index 00000000000..1909d3e49f3
--- /dev/null
+++ b/drivers/video/nxp/hdp/address.h
@@ -0,0 +1,78 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ ******************************************************************************
+ *
+ * address.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef ADDRESS_H_
+# define ADDRESS_H_
+
+# define ADDR_IMEM 0x10000
+# define ADDR_DMEM 0x20000
+# define ADDR_CIPHER 0x60000
+# define BASE_CIPHER 0x600
+# define ADDR_APB_CFG 0x00000
+# define BASE_APB_CFG 0x000
+# define ADDR_SOURCE_AIF_DECODER 0x30000
+# define BASE_SOURCE_AIF_DECODER 0x300
+# define ADDR_SOURCE_AIF_SMPL2PCKT 0x30080
+# define BASE_SOURCE_AIF_SMPL2PCKT 0x300
+# define ADDR_AIF_ENCODER 0x30000
+# define BASE_AIF_ENCODER 0x300
+# define ADDR_SOURCE_PIF 0x30800
+# define BASE_SOURCE_PIF 0x308
+# define ADDR_SINK_PIF 0x30800
+# define BASE_SINK_PIF 0x308
+# define ADDR_APB_CFG 0x00000
+# define BASE_APB_CFG 0x000
+# define ADDR_SOURCE_CSC 0x40000
+# define BASE_SOURCE_CSC 0x400
+# define ADDR_UCPU_CFG 0x00000
+# define BASE_UCPU_CFG 0x000
+# define ADDR_SOURCE_CAR 0x00900
+# define BASE_SOURCE_CAR 0x009
+# define ADDR_SINK_CAR 0x00900
+# define BASE_SINK_CAR 0x009
+# define ADDR_CLOCK_METERS 0x00A00
+# define BASE_CLOCK_METERS 0x00A
+# define ADDR_SOURCE_VIF 0x00b00
+# define BASE_SOURCE_VIF 0x00b
+# define ADDR_SINK_MHL_HD 0x01000
+# define ADDR_SINK_VIDEO_HD 0x01800
+# define BASE_SINK_MHL_HD 0x010
+# define ADDR_SINK_CORE 0x07800
+# define BASE_SINK_CORE 0x078
+# define ADDR_DPTX_PHY 0x02000
+# define BASE_DPTX_PHY 0x020
+# define ADDR_DPTX_HPD 0x02100
+# define BASE_DPTX_HPD 0x021
+# define ADDR_DPTX_FRAMER 0x02200
+# define BASE_DPTX_FRAMER 0x022
+# define ADDR_DPTX_STREAM 0x02200
+# define BASE_DPTX_STREAM 0x022
+# define ADDR_DPTX_GLBL 0x02300
+# define BASE_DPTX_GLBL 0x023
+# define ADDR_DPTX_HDCP 0x02400
+# define BASE_DPTX_HDCP 0x024
+# define ADDR_DP_AUX 0x02800
+# define BASE_DP_AUX 0x028
+# define ADDR_CRYPTO 0x05800
+# define BASE_CRYPTO 0x058
+# define ADDR_CIPHER 0x60000
+# define BASE_CIPHER 0x600
+# define ADDR_SOURCE_MHL_HD 0x01000
+
+# define ADDR_AFE  (0x20000 * 4)
+# define ADDR_SOURCD_PHY  (0x800)
+
+#endif
diff --git a/drivers/video/nxp/hdp/apb_cfg.h b/drivers/video/nxp/hdp/apb_cfg.h
new file mode 100644
index 00000000000..5e5c007ae18
--- /dev/null
+++ b/drivers/video/nxp/hdp/apb_cfg.h
@@ -0,0 +1,155 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * apb_cfg.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef APB_CFG_H_
+#define APB_CFG_H_
+
+/* register APB_CTRL */
+#define APB_CTRL 0
+#define F_APB_XT_RESET(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_APB_XT_RESET_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_APB_DRAM_PATH(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_APB_DRAM_PATH_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_APB_IRAM_PATH(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_APB_IRAM_PATH_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+
+/* register XT_INT_CTRL */
+#define XT_INT_CTRL 1
+#define F_XT_INT_POLARITY(x) (((x) & ((1 << 2) - 1)) << 0)
+#define F_XT_INT_POLARITY_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
+
+/* register MAILBOX_FULL_ADDR */
+#define MAILBOX_FULL_ADDR 2
+#define F_MAILBOX_FULL(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_MAILBOX_FULL_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+
+/* register MAILBOX_EMPTY_ADDR */
+#define MAILBOX_EMPTY_ADDR 3
+#define F_MAILBOX_EMPTY(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_MAILBOX_EMPTY_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+
+/* register MAILBOX0_WR_DATA */
+#define MAILBOX0_WR_DATA 4
+#define F_MAILBOX0_WR_DATA(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_MAILBOX0_WR_DATA_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register MAILBOX0_RD_DATA */
+#define MAILBOX0_RD_DATA 5
+#define F_MAILBOX0_RD_DATA(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_MAILBOX0_RD_DATA_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register KEEP_ALIVE */
+#define KEEP_ALIVE 6
+#define F_KEEP_ALIVE_CNT(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_KEEP_ALIVE_CNT_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register VER_L */
+#define VER_L 7
+#define F_VER_LSB(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_VER_LSB_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register VER_H */
+#define VER_H 8
+#define F_VER_MSB(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_VER_MSB_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register VER_LIB_L_ADDR */
+#define VER_LIB_L_ADDR 9
+#define F_SW_LIB_VER_L(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_SW_LIB_VER_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register VER_LIB_H_ADDR */
+#define VER_LIB_H_ADDR 10
+#define F_SW_LIB_VER_H(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_SW_LIB_VER_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register SW_DEBUG_L */
+#define SW_DEBUG_L 11
+#define F_SW_DEBUG_7_0(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_SW_DEBUG_7_0_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register SW_DEBUG_H */
+#define SW_DEBUG_H 12
+#define F_SW_DEBUG_15_8(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_SW_DEBUG_15_8_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register MAILBOX_INT_MASK */
+#define MAILBOX_INT_MASK 13
+#define F_MAILBOX_INT_MASK(x) (((x) & ((1 << 2) - 1)) << 0)
+#define F_MAILBOX_INT_MASK_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
+
+/* register MAILBOX_INT_STATUS */
+#define MAILBOX_INT_STATUS 14
+#define F_MAILBOX_INT_STATUS(x) (((x) & ((1 << 2) - 1)) << 0)
+#define F_MAILBOX_INT_STATUS_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
+
+/* register SW_CLK_L */
+#define SW_CLK_L 15
+#define F_SW_CLOCK_VAL_L(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_SW_CLOCK_VAL_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register SW_CLK_H */
+#define SW_CLK_H 16
+#define F_SW_CLOCK_VAL_H(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_SW_CLOCK_VAL_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register SW_EVENTS0 */
+#define SW_EVENTS0 17
+#define F_SW_EVENTS7_0(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_SW_EVENTS7_0_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register SW_EVENTS1 */
+#define SW_EVENTS1 18
+#define F_SW_EVENTS15_8(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_SW_EVENTS15_8_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register SW_EVENTS2 */
+#define SW_EVENTS2 19
+#define F_SW_EVENTS23_16(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_SW_EVENTS23_16_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register SW_EVENTS3 */
+#define SW_EVENTS3 20
+#define F_SW_EVENTS31_24(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_SW_EVENTS31_24_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register XT_OCD_CTRL */
+#define XT_OCD_CTRL 24
+#define F_XT_DRESET(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_XT_DRESET_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_XT_OCDHALTONRESET(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_XT_OCDHALTONRESET_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+
+/* register XT_OCD_CTRL_RO */
+#define XT_OCD_CTRL_RO 25
+#define F_XT_XOCDMODE(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_XT_XOCDMODE_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+
+/* register APB_INT_MASK */
+#define APB_INT_MASK 27
+#define F_APB_INTR_MASK(x) (((x) & ((1 << 3) - 1)) << 0)
+#define F_APB_INTR_MASK_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0)
+
+/* register APB_STATUS_MASK */
+#define APB_STATUS_MASK 28
+#define F_APB_INTR_STATUS(x) (((x) & ((1 << 3) - 1)) << 0)
+#define F_APB_INTR_STATUS_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0)
+
+#endif	/*APB_CFG*/
diff --git a/drivers/video/nxp/hdp/avgen.h b/drivers/video/nxp/hdp/avgen.h
new file mode 100644
index 00000000000..669a10187f1
--- /dev/null
+++ b/drivers/video/nxp/hdp/avgen.h
@@ -0,0 +1,253 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * avgen.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef AVGEN_H_
+# define AVGEN_H_
+
+
+/* register HDMIPOL */
+# define HDMIPOL 0
+# define F_HDMI_V_H_POLARITY(x) (((x) & ((1 << 2) - 1)) << 0)
+# define F_HDMI_V_H_POLARITY_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
+# define F_HDMI_BITWIDTH(x) (((x) & ((1 << 2) - 1)) << 2)
+# define F_HDMI_BITWIDTH_RD(x) (((x) & (((1 << 2) - 1) << 2)) >> 2)
+
+/* register HDMI_FRONT_PORCHE_L */
+# define HDMI_FRONT_PORCHE_L 1
+# define F_HDMI_FRONT_PORCHE_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_FRONT_PORCHE_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDFP */
+# define HDFP 2
+# define F_HDMI_FRONT_PORCHE_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_FRONT_PORCHE_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDBP */
+# define HDBP 3
+# define F_HDMI_BACK_PORCHE_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_BACK_PORCHE_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDMI_BACK_PORCHE_H */
+# define HDMI_BACK_PORCHE_H 4
+# define F_HDMI_BACK_PORCHE_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_BACK_PORCHE_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDAS */
+# define HDAS 5
+# define F_HDMI_ACTIVE_SLOT_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_ACTIVE_SLOT_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDMI_ACTIVE_SLOT_H */
+# define HDMI_ACTIVE_SLOT_H 6
+# define F_HDMI_ACTIVE_SLOT_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_ACTIVE_SLOT_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDFL */
+# define HDFL 7
+# define F_HDMI_FRAME_LINES_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_FRAME_LINES_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDMI_FRAME_LINES_H */
+# define HDMI_FRAME_LINES_H 8
+# define F_HDMI_FRAME_LINES_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_FRAME_LINES_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDLW */
+# define HDLW 9
+# define F_HDMI_LINE_WIDTH_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_LINE_WIDTH_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDMI_LINE_WIDTH_H */
+# define HDMI_LINE_WIDTH_H 10
+# define F_HDMI_LINE_WIDTH_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDMI_LINE_WIDTH_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDVL */
+# define HDVL 11
+# define F_HDMI_VSYNC_LINES(x) (((x) & ((1 << 7) - 1)) << 0)
+# define F_HDMI_VSYNC_LINES_RD(x) (((x) & (((1 << 7) - 1) << 0)) >> 0)
+
+/* register HDEL */
+# define HDEL 12
+# define F_HDMI_EOF_LINES(x) (((x) & ((1 << 7) - 1)) << 0)
+# define F_HDMI_EOF_LINES_RD(x) (((x) & (((1 << 7) - 1) << 0)) >> 0)
+
+/* register HDSL */
+# define HDSL 13
+# define F_HDMI_SOF_LINES(x) (((x) & ((1 << 7) - 1)) << 0)
+# define F_HDMI_SOF_LINES_RD(x) (((x) & (((1 << 7) - 1) << 0)) >> 0)
+
+/* register HDCFUPDT */
+# define HDCFUPDT 14
+# define F_HDMI_CODE_FORMAT_UPDT(x) (((x) & ((1 << 6) - 1)) << 0)
+# define F_HDMI_CODE_FORMAT_UPDT_RD(x) (((x) & (((1 << 6) - 1) << 0)) >> 0)
+
+/* register HDCF */
+# define HDCF 15
+# define F_HDMI_CODE_FORMAT(x) (((x) & ((1 << 6) - 1)) << 0)
+# define F_HDMI_CODE_FORMAT_RD(x) (((x) & (((1 << 6) - 1) << 0)) >> 0)
+
+/* register HDASPACE */
+# define HDASPACE 16
+# define F_HDASPACE(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_HDASPACE_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register HDMI_3D_MODE */
+# define HDMI_3D_MODE 17
+# define F_HDMI_3D_MODE(x) (((x) & ((1 << 3) - 1)) << 0)
+# define F_HDMI_3D_MODE_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0)
+
+/* register PTRNGENR */
+# define PTRNGENR 18
+# define F_PTRNGENR_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_PTRNGENR_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register PTRNGENR_H */
+# define PTRNGENR_H 19
+# define F_PTRNGENR_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_PTRNGENR_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register PTRNGENG */
+# define PTRNGENG 20
+# define F_PTRNGENG_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_PTRNGENG_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register PTRNEGENG_H */
+# define PTRNEGENG_H 21
+# define F_PTRNGENG_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_PTRNGENG_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register PTRNGENB */
+# define PTRNGENB 22
+# define F_PTRNGENB_L(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_PTRNGENB_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register PTRGENB */
+# define PTRGENB 23
+# define F_PTRNGENB_H(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_PTRNGENB_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register PTRNGENFF */
+# define PTRNGENFF 30
+# define F_PTRNGENIP(x) (((x) & ((1 << 1) - 1)) << 1)
+# define F_PTRNGENIP_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+
+/* register PGENCTRL */
+# define PGENCTRL 32
+# define F_PGENCF(x) (((x) & ((1 << 6) - 1)) << 1)
+# define F_PGENCF_RD(x) (((x) & (((1 << 6) - 1) << 1)) >> 1)
+# define F_PTRNGENSTRT(x) (((x) & ((1 << 1) - 1)) << 7)
+# define F_PTRNGENSTRT_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7)
+
+/* register PGENCTRL_H */
+# define PGENCTRL_H 33
+# define F_PTRNGENRST(x) (((x) & ((1 << 1) - 1)) << 0)
+# define F_PTRNGENRST_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+# define F_PIC_SEL(x) (((x) & ((1 << 3) - 1)) << 1)
+# define F_PIC_SEL_RD(x) (((x) & (((1 << 3) - 1) << 1)) >> 1)
+# define F_PIC_YCBCR_SEL(x) (((x) & ((1 << 2) - 1)) << 4)
+# define F_PIC_YCBCR_SEL_RD(x) (((x) & (((1 << 2) - 1) << 4)) >> 4)
+
+/* register PGEN_COLOR_BAR_CTRL */
+# define PGEN_COLOR_BAR_CTRL 34
+# define F_PGEN_NUM_BAR(x) (((x) & ((1 << 3) - 1)) << 0)
+# define F_PGEN_NUM_BAR_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0)
+
+/* register PGEN_COLOR_BAR_CONTROL_H */
+# define PGEN_COLOR_BAR_CONTROL_H 35
+# define F_PGEN_COLOR_UPDT(x) (((x) & ((1 << 6) - 1)) << 0)
+# define F_PGEN_COLOR_UPDT_RD(x) (((x) & (((1 << 6) - 1) << 0)) >> 0)
+
+/* register GEN_AUDIO_CONTROL */
+# define GEN_AUDIO_CONTROL 36
+# define F_AUDIO_START(x) (((x) & ((1 << 1) - 1)) << 1)
+# define F_AUDIO_START_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+# define F_AUDIO_RESET(x) (((x) & ((1 << 1) - 1)) << 2)
+# define F_AUDIO_RESET_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+
+/* register SPDIF_CTRL_A */
+# define SPDIF_CTRL_A 37
+# define F_SPDIF_SOURCE_NUM(x) (((x) & ((1 << 4) - 1)) << 0)
+# define F_SPDIF_SOURCE_NUM_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+# define F_SPDIF_CH_NUM(x) (((x) & ((1 << 4) - 1)) << 4)
+# define F_SPDIF_CH_NUM_RD(x) (((x) & (((1 << 4) - 1) << 4)) >> 4)
+
+/* register SPDIF_CTRL_A_H */
+# define SPDIF_CTRL_A_H 38
+# define F_SPDIF_SMP_FREQ(x) (((x) & ((1 << 4) - 1)) << 0)
+# define F_SPDIF_SMP_FREQ_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+# define F_SPDIF_CLK_ACCUR(x) (((x) & ((1 << 2) - 1)) << 4)
+# define F_SPDIF_CLK_ACCUR_RD(x) (((x) & (((1 << 2) - 1) << 4)) >> 4)
+# define F_SPDIF_VALID(x) (((x) & ((1 << 1) - 1)) << 6)
+# define F_SPDIF_VALID_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6)
+
+/* register SPDIF_CTRL_B */
+# define SPDIF_CTRL_B 39
+# define F_SPDIF_WORD_LENGTH(x) (((x) & ((1 << 4) - 1)) << 0)
+# define F_SPDIF_WORD_LENGTH_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+# define F_SPDIF_ORG_SMP_FREQ(x) (((x) & ((1 << 4) - 1)) << 4)
+# define F_SPDIF_ORG_SMP_FREQ_RD(x) (((x) & (((1 << 4) - 1) << 4)) >> 4)
+
+/* register SPDIF_CTRL_B_H */
+# define SPDIF_CTRL_B_H 40
+# define F_CATEGORY_MODE(x) (((x) & ((1 << 8) - 1)) << 0)
+# define F_CATEGORY_MODE_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+
+/* register AUDIO_DIV_EN */
+# define AUDIO_DIV_EN 45
+# define F_AGEN_60958_I2S(x) (((x) & ((1 << 1) - 1)) << 1)
+# define F_AGEN_60958_I2S_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+# define F_AGEN_PRL_SUBFRAME(x) (((x) & ((1 << 1) - 1)) << 2)
+# define F_AGEN_PRL_SUBFRAME_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+# define F_AGEN_SAMPLES_DATA(x) (((x) & ((1 << 1) - 1)) << 3)
+# define F_AGEN_SAMPLES_DATA_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+
+#endif /*AVGEN */
+
diff --git a/drivers/video/nxp/hdp/avgen_drv.c b/drivers/video/nxp/hdp/avgen_drv.c
new file mode 100644
index 00000000000..89acafe340c
--- /dev/null
+++ b/drivers/video/nxp/hdp/avgen_drv.c
@@ -0,0 +1,306 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * avgen_drv.c
+ *
+ ******************************************************************************
+ */
+
+#include "mhl_hdtx_top.h"
+#include "address.h"
+#include "avgen.h"
+#include "avgen_drv.h"
+#include "util.h"
+#include "externs.h"
+
+#define ADDR_AVGEN 0x80000
+
+CDN_API_STATUS CDN_API_AVGEN_Set(VIC_MODES vicMode, CDN_PROTOCOL_TYPE protocol,
+				 VIC_PXL_ENCODING_FORMAT format)
+{
+	/*CDN_API_STATUS ret; */
+	/*GENERAL_Read_Register_response resp; */
+	unsigned int pixelClockFreq = CDN_API_Get_PIXEL_FREQ_KHZ_ClosetVal
+		(vic_table[vicMode][PIXEL_FREQ_KHZ], protocol);
+	unsigned int v_h_polarity =
+		((vic_table[vicMode][HSYNC_POL] == ACTIVE_LOW) ? 0 : 1) +
+		((vic_table[vicMode][VSYNC_POL] == ACTIVE_LOW) ? 0 : 2);
+	unsigned int front_porche_l = vic_table[vicMode][FRONT_PORCH] - 256 *
+		((unsigned int)vic_table[vicMode][FRONT_PORCH] / 256);
+	unsigned int front_porche_h = vic_table[vicMode][FRONT_PORCH] / 256;
+	unsigned int back_porche_l = vic_table[vicMode][BACK_PORCH] - 256 *
+		((unsigned int)vic_table[vicMode][BACK_PORCH] / 256);
+	unsigned int back_porche_h = vic_table[vicMode][BACK_PORCH] / 256;
+	unsigned int active_slot_l = vic_table[vicMode][H_BLANK] - 256 *
+		((unsigned int)vic_table[vicMode][H_BLANK] / 256);
+	unsigned int active_slot_h = vic_table[vicMode][H_BLANK] / 256;
+	unsigned int frame_lines_l = vic_table[vicMode][V_TOTAL] - 256 *
+		((unsigned int)vic_table[vicMode][V_TOTAL] / 256);
+	unsigned int frame_lines_h = vic_table[vicMode][V_TOTAL] / 256;
+	unsigned int line_width_l = vic_table[vicMode][H_TOTAL] - 256 *
+		((unsigned int)vic_table[vicMode][H_TOTAL] / 256);
+	unsigned int line_width_h = vic_table[vicMode][H_TOTAL] / 256;
+	unsigned int vsync_lines = vic_table[vicMode][VSYNC];
+	unsigned int eof_lines = vic_table[vicMode][TYPE_EOF];
+	unsigned int sof_lines = vic_table[vicMode][SOF];
+	unsigned int interlace_progressive =
+		(vic_table[vicMode][I_P] == INTERLACED) ? 2 : 0;
+	unsigned int set_vif_clock = 0;
+
+	/*needed for HDMI /////////////////////////////// */
+	/*unsigned int hblank = vic_table[vicMode][H_BLANK]; */
+	/*unsigned int hactive = vic_table[vicMode][H_TOTAL]-hblank; */
+	/*unsigned int vblank = vsync_lines+eof_lines+sof_lines; */
+	/*unsigned int vactive = vic_table[vicMode][V_TOTAL]-vblank; */
+	/*unsigned int hfront = vic_table[vicMode][FRONT_PORCH]; */
+	/*unsigned int hback = vic_table[vicMode][BACK_PORCH]; */
+	/*unsigned int vfront = eof_lines; */
+	/*unsigned int hsync = hblank-hfront-hback; */
+	/*unsigned int vsync = vsync_lines; */
+	/*unsigned int vback = sof_lines; */
+	unsigned int set_CLK_SEL            = 0;
+	unsigned int set_REF_CLK_SEL        = 0;
+	unsigned int set_pll_CLK_IN            = 0;
+	unsigned int set_pll_clkfbout_l        = 0;
+	unsigned int set_pll_clkfbout_h        = 0;
+	unsigned int set_pll_CLKOUT5_L        = 0;
+	unsigned int set_pll_CLKOUT5_H        = 0;
+	unsigned int set_pll2_CLKIN            = 0;
+	unsigned int set_pll2_CLKFBOUT_L    = 0;
+	unsigned int set_pll2_CLKFBOUT_H    = 0;
+	unsigned int set_pll2_CLKOUT5_L        = 0;
+	unsigned int set_pll2_CLKOUT5_H        = 0;
+	/*///////////////////////////////////////////////// */
+
+	cdn_apb_write(0x1c00C6 << 2,
+		      (int)(vic_table[vicMode][PIXEL_FREQ_KHZ] * 1000));
+	cdn_apb_write(0x1c00C6 << 2, (int)(pixelClockFreq));
+
+	if ((int)(pixelClockFreq) == 25) {
+		if (protocol == CDN_HDMITX_TYPHOON) {
+			set_CLK_SEL                = 4;
+			set_REF_CLK_SEL            = 0;
+			set_pll_CLK_IN            = 65;
+			set_pll_clkfbout_l        = 4292;
+			set_pll_clkfbout_h        = 128;
+			set_pll_CLKOUT5_L        = 4422;
+			set_pll_CLKOUT5_H        = 128;
+			set_pll2_CLKIN            = 12289;
+			set_pll2_CLKFBOUT_L        = 4356;
+			set_pll2_CLKFBOUT_H        = 0;
+			set_pll2_CLKOUT5_L        = 4552;
+			set_pll2_CLKOUT5_H        = 128;
+		} else {
+			set_vif_clock = 0x300;
+		}
+	} else if ((int)pixelClockFreq == 27000) {
+		if (protocol == CDN_HDMITX_TYPHOON) {
+			set_CLK_SEL                = 5;
+			set_REF_CLK_SEL            = 0;
+			set_pll_CLK_IN            = 49217;
+			set_pll_clkfbout_l        = 4226;
+			set_pll_clkfbout_h        = 0;
+			set_pll_CLKOUT5_L        = 4422;
+			set_pll_CLKOUT5_H        = 128;
+		} else {
+			set_vif_clock = 0x301;
+		}
+	} else if ((int)pixelClockFreq == 54000) {
+		if (protocol == CDN_HDMITX_TYPHOON) {
+			set_CLK_SEL             = 5;
+			set_REF_CLK_SEL         = 0;
+			set_pll_CLK_IN          = 4096;
+			set_pll_clkfbout_l      = 4226;
+			set_pll_clkfbout_h      = 0;
+			set_pll_CLKOUT5_L       = 4422;
+			set_pll_CLKOUT5_H       = 128;
+		} else {
+			set_vif_clock = 0x302;
+		}
+	} else if (pixelClockFreq == 74250) {
+		if (protocol == CDN_HDMITX_TYPHOON) {
+			set_CLK_SEL          = 1;
+			set_pll_CLK_IN       = 74;
+		} else {
+			set_vif_clock = 0x303;
+		}
+	} else if (pixelClockFreq == 148500) {
+		if (protocol == CDN_HDMITX_TYPHOON) {
+			set_CLK_SEL             = 0;
+			set_pll_CLK_IN       = 148;
+		} else {
+			set_vif_clock = 0x304;
+		}
+	} else if ((int)pixelClockFreq == 108000) {
+		if (protocol == CDN_HDMITX_TYPHOON) {
+			set_CLK_SEL                = 5;
+			set_REF_CLK_SEL            = 2;
+			set_pll_CLK_IN            = 8258;
+			set_pll_clkfbout_l        = 4616;
+			set_pll_clkfbout_h        = 0;
+			set_pll_CLKOUT5_L        = 4422;
+			set_pll_CLKOUT5_H        = 128;
+		} else {
+			set_vif_clock = 0x305;
+		}
+	} else {
+		if (protocol == CDN_HDMITX_TYPHOON) {
+			set_CLK_SEL             = 1;
+			set_pll_CLK_IN          = pixelClockFreq;
+		} else {
+			set_vif_clock = 0;
+		}
+	}
+	unsigned int start_pgen = 128;
+	/*unsigned int temp; */
+	if (protocol == CDN_HDMITX_TYPHOON) {
+		if (cdn_apb_write(0x0c0001 << 2,
+				  ((0) + (2 * set_CLK_SEL) + (16 * 0) +
+				   (32 * 0) + (64 * 3) + (65536 * 3) +
+				   (1048576 * set_REF_CLK_SEL))))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c00C6 << 2, set_pll_CLK_IN))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c00CC << 2, set_pll_clkfbout_l))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c00CD << 2, set_pll_clkfbout_h))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c00CE << 2, set_pll_CLKOUT5_L))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c00CF << 2, set_pll_CLKOUT5_H))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c0086 << 2, set_pll2_CLKIN))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c008C << 2, set_pll2_CLKFBOUT_L))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c008D << 2, set_pll2_CLKFBOUT_H))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c008E << 2, set_pll2_CLKOUT5_L))
+			return CDN_ERR;
+		if (cdn_apb_write(0x1c008F << 2, set_pll2_CLKOUT5_H))
+			return CDN_ERR;
+		if (cdn_apb_write(0x0c0001 << 2,
+				  ((1) + (2 * set_CLK_SEL) + (16 * 0) +
+				   (32 * 0) + (64 * 3) + (65536 * 3) +
+				   (1048576 * set_REF_CLK_SEL))))
+			return CDN_ERR;
+	}
+
+	if (cdn_apb_write((ADDR_AVGEN + HDMIPOL) << 2, v_h_polarity))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDMI_FRONT_PORCHE_L) << 2,
+			  front_porche_l))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDFP) << 2, front_porche_h))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDBP) << 2, back_porche_l))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDMI_BACK_PORCHE_H) << 2,
+			  back_porche_h))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDAS) << 2, active_slot_l))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDMI_ACTIVE_SLOT_H) << 2,
+			  active_slot_h))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDFL) << 2, frame_lines_l))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDMI_FRAME_LINES_H) << 2,
+			  frame_lines_h))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDLW) << 2, line_width_l))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDMI_LINE_WIDTH_H) << 2, line_width_h))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDVL) << 2, vsync_lines))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDEL) << 2, eof_lines))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + HDSL) << 2, sof_lines))
+		return CDN_ERR;
+	if (cdn_apb_write((ADDR_AVGEN + PTRNGENFF) << 2, interlace_progressive))
+		return CDN_ERR;
+
+	if (protocol == CDN_HDMITX_TYPHOON) {
+		switch (format) {
+		case PXL_RGB:
+
+			if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2,
+					  F_PIC_SEL(1) | F_PIC_YCBCR_SEL(0)))
+				return CDN_ERR;
+			break;
+
+		case YCBCR_4_4_4:
+			if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2,
+					  F_PIC_SEL(2) | F_PIC_YCBCR_SEL(0)))
+				return CDN_ERR;
+
+			break;
+
+		case YCBCR_4_2_2:
+			if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2,
+					  F_PIC_SEL(2) | F_PIC_YCBCR_SEL(1)))
+				return CDN_ERR;
+
+			break;
+
+		case YCBCR_4_2_0:
+			if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2,
+					  F_PIC_SEL(2) | F_PIC_YCBCR_SEL(2)))
+				return CDN_ERR;
+
+			break;
+		case Y_ONLY:
+			/*not exist in hdmi */
+			break;
+		}
+	} else {
+		if (set_vif_clock != 0)
+			if (cdn_apb_write(0xC0006 << 2, set_vif_clock))
+				return CDN_ERR;
+	}
+
+	if (cdn_apb_write((ADDR_AVGEN + PGENCTRL) << 2, start_pgen))
+		return CDN_ERR;
+
+	return CDN_OK;
+}
+
diff --git a/drivers/video/nxp/hdp/avgen_drv.h b/drivers/video/nxp/hdp/avgen_drv.h
new file mode 100644
index 00000000000..1f8c76b4682
--- /dev/null
+++ b/drivers/video/nxp/hdp/avgen_drv.h
@@ -0,0 +1,69 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * avgen_drv.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef AVGEN_DRV_H_
+# define AVGEN_DRV_H_
+
+#ifndef __UBOOT__
+# include <stdint.h>
+#else
+#include <common.h>
+#endif
+
+# include "vic_table.h"
+# include "API_General.h"
+# include "defs.h"
+
+/**
+ * \brief set avgen according to mode and vic table, user that doesnt have
+ * cadence AVGEN, need to implement this function on user
+ * platform
+ */
+CDN_API_STATUS CDN_API_AVGEN_Set(VIC_MODES vicMode, CDN_PROTOCOL_TYPE protocol,
+				 VIC_PXL_ENCODING_FORMAT format);
+
+#endif
+
diff --git a/drivers/video/nxp/hdp/defs.h b/drivers/video/nxp/hdp/defs.h
new file mode 100644
index 00000000000..4a6361e4fa2
--- /dev/null
+++ b/drivers/video/nxp/hdp/defs.h
@@ -0,0 +1,57 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2015-2016 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * defs.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef _DEFS_H_
+#define _DEFS_H_
+
+typedef enum {
+	CDN_DPTX ,
+	CDN_HDMITX_TYPHOON,
+	CDN_HDMITX_KIRAN,
+} CDN_PROTOCOL_TYPE;
+
+#endif /*_DEFS_H_ */
+
diff --git a/drivers/video/nxp/hdp/edid_parser.c b/drivers/video/nxp/hdp/edid_parser.c
new file mode 100644
index 00000000000..9cb361105ae
--- /dev/null
+++ b/drivers/video/nxp/hdp/edid_parser.c
@@ -0,0 +1,617 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2015-2016 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * edid_parser.c
+ *
+ ******************************************************************************
+ */
+
+#include "edid_parser.h"
+
+static EDID_PARSER_RESULT edid_parse_dtd(S_DTD_DATA *descriptor,
+					 unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+
+	descriptor->header.type = DESCRIPTOR_TYPE_DTD;
+	descriptor->header.tag = 0;
+
+	descriptor->pixel_clock = raw_data[raw_data_index];
+	descriptor->pixel_clock +=
+		(unsigned short)raw_data[raw_data_index + 1] << 8;
+
+	descriptor->horizontal_addressable_video = raw_data[raw_data_index + 2];
+	descriptor->horizontal_addressable_video +=
+		((unsigned short)raw_data[raw_data_index + 4] & 0xF0) << 4;
+	descriptor->horizontal_blanking = raw_data[raw_data_index + 3];
+	descriptor->horizontal_blanking +=
+		((unsigned short)raw_data[raw_data_index + 4] & 0x0F) << 8;
+
+	descriptor->vertical_addressable_video = raw_data[raw_data_index + 5];
+	descriptor->vertical_addressable_video +=
+		((unsigned short)raw_data[raw_data_index + 7] & 0xF0) << 4;
+	descriptor->vertical_blanking = raw_data[raw_data_index + 6];
+	descriptor->vertical_blanking +=
+		((unsigned short)raw_data[raw_data_index + 7] & 0x0F) << 8;
+
+	descriptor->horizontal_front_porch = raw_data[raw_data_index + 8];
+	descriptor->horizontal_front_porch +=
+		((unsigned short)raw_data[raw_data_index + 11] & 0xC0) << 2;
+	descriptor->horizontal_sync_pulse_width = raw_data[raw_data_index + 9];
+	descriptor->horizontal_sync_pulse_width +=
+		((unsigned short)raw_data[raw_data_index + 11] & 0x30) << 4;
+
+	descriptor->vertical_front_porch =
+		(raw_data[raw_data_index + 10] & 0xF0) >> 4;
+	descriptor->vertical_front_porch +=
+		(raw_data[raw_data_index + 11] & 0x0C) << 2;
+	descriptor->vertical_sync_pulse_width =
+		raw_data[raw_data_index + 10] & 0x0F;
+	descriptor->vertical_sync_pulse_width +=
+		(raw_data[raw_data_index + 11] & 0x03) << 4;
+
+	descriptor->horizontal_addressable_video_image_size =
+		raw_data[raw_data_index + 12];
+	descriptor->horizontal_addressable_video_image_size +=
+		((unsigned short)raw_data[raw_data_index + 14] & 0xF0) << 4;
+	descriptor->vertical_addressable_video_image_size =
+		raw_data[raw_data_index + 13];
+	descriptor->vertical_addressable_video_image_size +=
+		((unsigned short)raw_data[raw_data_index + 14] & 0x0F) << 8;
+
+	descriptor->horizontal_border = raw_data[raw_data_index + 15];
+	descriptor->vertical_border = raw_data[raw_data_index + 16];
+
+	descriptor->signal_features = raw_data[raw_data_index + 17];
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_serial_number(S_SERIAL_NUMBER_DATA *
+						   descriptor,
+						   unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+	descriptor->header.type = DESCRIPTOR_TYPE_SERIAL_NUMBER;
+	descriptor->header.tag = 0xFF;
+
+	int idx;
+	for (idx = 0; idx < 13; idx++)
+		descriptor->serial_number[idx] =
+			raw_data[raw_data_index + 5 + idx];
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_data_string(S_DATA_STRING_DATA *
+						 descriptor,
+						 unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+	descriptor->header.type = DESCRIPTOR_TYPE_DATA_STRING;
+	descriptor->header.tag = 0xFE;
+	int idx;
+	for (idx = 0; idx < 13; idx++)
+		descriptor->data_string[idx] =
+			raw_data[raw_data_index + 5 + idx];
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_range_limits(S_RANGE_LIMITS_DATA *
+						  descriptor,
+						  unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+
+	descriptor->header.type = DESCRIPTOR_TYPE_RANGE_LIMITS;
+	descriptor->header.tag = 0xFD;
+
+	descriptor->offset_flags = raw_data[raw_data_index + 4];
+	descriptor->min_vertical_rate = raw_data[raw_data_index + 5];
+	descriptor->max_vertical_rate = raw_data[raw_data_index + 6];
+	descriptor->min_horizontal_rate = raw_data[raw_data_index + 7];
+	descriptor->max_horizontal_rate = raw_data[raw_data_index + 8];
+	descriptor->max_pixel_clock = raw_data[raw_data_index + 9];
+
+	switch (raw_data[raw_data_index + 10]) {
+	case 0x00:
+		descriptor->type = VIDEO_TIMING_DEFAULT_GTF;
+		break;
+	case 0x01:
+		descriptor->type = VIDEO_TIMING_RANGE_LIMITS_ONLY;
+		break;
+	case 0x02:
+		descriptor->type = VIDEO_TIMING_SECONDARY_GTF;
+		S_RANGE_LIMITS_VIDEO_TIMING_SECONDARY_GTF *timing_type_gtf =
+			(S_RANGE_LIMITS_VIDEO_TIMING_SECONDARY_GTF *)
+			descriptor->suport_flags;
+		timing_type_gtf->start_break_frequency =
+			raw_data[raw_data_index + 12];
+		timing_type_gtf->c = raw_data[raw_data_index + 13];
+		timing_type_gtf->m = raw_data[raw_data_index + 14];
+		timing_type_gtf->m +=
+			(unsigned short)raw_data[raw_data_index + 15] << 8;
+		timing_type_gtf->k = raw_data[raw_data_index + 16];
+		timing_type_gtf->j = raw_data[raw_data_index + 17];
+		break;
+	case 0x04:
+		descriptor->type = VIDEO_TIMING_CVT;
+		S_RANGE_LIMITS_VIDEO_TIMING_CVT *timing_type_cvt =
+			(S_RANGE_LIMITS_VIDEO_TIMING_CVT *)descriptor->
+			suport_flags;
+		timing_type_cvt->cvt_version = raw_data[raw_data_index + 11];
+		timing_type_cvt->additional_pixel_clock_precision =
+			raw_data[raw_data_index + 12] >> 2;
+		timing_type_cvt->max_active_pixels =
+			raw_data[raw_data_index + 13];
+		timing_type_cvt->max_active_pixels +=
+			(unsigned short)(raw_data[raw_data_index + 12] & 0x03)
+			<< 8;
+		timing_type_cvt->supported_ar =
+			raw_data[raw_data_index + 14] >> 3;
+		timing_type_cvt->preferred_ar =
+			raw_data[raw_data_index + 15] >> 5;
+		timing_type_cvt->blanking_support =
+			(raw_data[raw_data_index + 15] & 0x18) >> 3;
+		timing_type_cvt->supported_scalling =
+			raw_data[raw_data_index + 16] >> 4;
+		timing_type_cvt->preferred_vertical_refresh_rate =
+			raw_data[raw_data_index + 17];
+		break;
+	}
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_product_name(S_PRODUCT_NAME_DATA *
+						  descriptor,
+						  unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+
+	descriptor->header.type = DESCRIPTOR_TYPE_PRODUCT_NAME;
+	descriptor->header.tag = 0xFC;
+	int idx;
+	for (idx = 0; idx < 13; idx++)
+		descriptor->product_name[idx] =
+			raw_data[raw_data_index + 5 + idx];
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_color_point(S_COLOR_POINT_DATA *
+						 descriptor,
+						 unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+
+	descriptor->header.type = DESCRIPTOR_TYPE_COLOR_POINT;
+	descriptor->header.tag = 0xFB;
+	descriptor->white_point_index_1 = raw_data[raw_data_index + 5];
+	descriptor->white_x_1 = (raw_data[raw_data_index + 6] & 0x0C) >> 2;
+	descriptor->white_x_1 +=
+		(unsigned short)raw_data[raw_data_index + 7] << 2;
+	descriptor->white_y_1 = raw_data[raw_data_index + 6] & 0x03;
+	descriptor->white_y_1 +=
+		(unsigned short)raw_data[raw_data_index + 8] << 2;
+	descriptor->gamma_1 = raw_data[raw_data_index + 9];
+
+	descriptor->white_point_index_2 = raw_data[raw_data_index + 10];
+	descriptor->white_x_2 = (raw_data[raw_data_index + 11] & 0x0C) >> 2;
+	descriptor->white_x_2 +=
+		(unsigned short)raw_data[raw_data_index + 12] << 2;
+	descriptor->white_y_2 = raw_data[raw_data_index + 11] & 0x03;
+	descriptor->white_y_2 +=
+		(unsigned short)raw_data[raw_data_index + 13] << 2;
+	descriptor->gamma_2 = raw_data[raw_data_index + 14];
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_standard_timing(S_STANDARD_TIMING_DATA *
+						     descriptor,
+						     unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+
+	descriptor->header.type = DESCRIPTOR_TYPE_STANDARD_TIMING;
+	descriptor->header.tag = 0xFA;
+	int idx;
+	for (idx = 0; idx < 6; idx++) {
+		descriptor->standard_timings[idx] =
+			raw_data[raw_data_index + 5 + 2 * idx];
+		descriptor->standard_timings[idx] +=
+			(unsigned short)raw_data[raw_data_index + 5 + 2 * idx +
+			1];
+	}
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_color_management(S_COLOR_MANAGEMENT_DATA *
+						      descriptor,
+						      unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+
+	descriptor->header.type = DESCRIPTOR_TYPE_COLOR_MANAGEMENT;
+	descriptor->header.tag = 0xF9;
+
+	descriptor->version = raw_data[raw_data_index + 5];
+
+	descriptor->red_a3 = raw_data[raw_data_index + 6];
+	descriptor->red_a3 += (unsigned short)raw_data[raw_data_index + 7] << 8;
+	descriptor->red_a2 = raw_data[raw_data_index + 8];
+	descriptor->red_a2 += (unsigned short)raw_data[raw_data_index + 9] << 8;
+
+	descriptor->green_a3 = raw_data[raw_data_index + 10];
+	descriptor->green_a3 +=
+		(unsigned short)raw_data[raw_data_index + 11] << 8;
+	descriptor->green_a2 = raw_data[raw_data_index + 12];
+	descriptor->green_a2 +=
+		(unsigned short)raw_data[raw_data_index + 13] << 8;
+
+	descriptor->blue_a3 = raw_data[raw_data_index + 14];
+	descriptor->blue_a3 +=
+		(unsigned short)raw_data[raw_data_index + 15] << 8;
+	descriptor->blue_a2 = raw_data[raw_data_index + 16];
+	descriptor->blue_a2 +=
+		(unsigned short)raw_data[raw_data_index + 17] << 8;
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_cvt_timing_codes(S_CVT_TIMING_CODES_DATA *
+						      descriptor,
+						      unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+
+	descriptor->header.type = DESCRIPTOR_TYPE_CVT_TIMING_CODES;
+	descriptor->header.tag = 0xF8;
+	descriptor->version = raw_data[raw_data_index + 5];
+
+	int idx;
+	for (idx = 0; idx < 4; idx++) {
+		descriptor->addressable_lines[idx] =
+			raw_data[raw_data_index + 6 + idx * 3];
+		descriptor->addressable_lines[idx] +=
+			(unsigned short)(raw_data[raw_data_index + 7 + idx * 3]
+			& 0xF0) << 4;
+		descriptor->aspect_ratio[idx] =
+			(raw_data[raw_data_index + 7 + idx * 3] & 0x0C) >> 2;
+		descriptor->preferred_vertical_rate[idx] =
+			(raw_data[raw_data_index + 8 + idx * 3] & 0x60) >> 5;
+		descriptor->supported_vertical_rate_and_blanking[idx] =
+			raw_data[raw_data_index + 8 + idx * 3] & 0x1F;
+	}
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT
+edid_parse_established_timings_3(S_ESTABLISHED_TIMINGS_3_DATA *descriptor,
+				 unsigned char *raw_data)
+{
+	unsigned int raw_data_index = 0;
+
+	descriptor->header.type = DESCRIPTOR_TYPE_ESTABLISHED_TIMINGS_3;
+	descriptor->header.tag = 0xF7;
+	descriptor->version = raw_data[raw_data_index + 5];
+	int idx;
+	for (idx = 0; idx < 6; idx++) {
+		descriptor->established_timings[idx] =
+			raw_data[raw_data_index + 6 + idx];
+	}
+
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT edid_parse_dummy(S_DUMMY_DATA *descriptor,
+					   unsigned char *raw_data)
+{
+	descriptor->header.type = DESCRIPTOR_TYPE_DUMMY;
+	descriptor->header.tag = 0x10;
+	return EDID_PARSER_SUCCESS;
+}
+
+static EDID_PARSER_RESULT
+edid_parse_manufacturer_specific(S_MANUFACTURER_SPECIFIC_DATA *descriptor,
+				 unsigned char *raw_data, unsigned char tag)
+{
+	descriptor->header.type = DESCRIPTOR_TYPE_MANUFACTURER_SPECIFIC;
+	descriptor->header.tag = tag;
+
+	return EDID_PARSER_SUCCESS;
+}
+
+EDID_PARSER_RESULT edid_parse(S_EDID_DATA *edid, unsigned char *raw_data,
+			      unsigned int len)
+{
+	unsigned int raw_data_index = 0;
+	unsigned char sum = 0;
+	/*CHECK SUM OF BYTES IN BLOCK0 */
+	for (raw_data_index = 0; raw_data_index < EDID_LENGTH; raw_data_index++)
+		sum += raw_data[raw_data_index];
+
+	if (sum != 0)
+		return EDID_PARSER_ERROR;
+
+	/*READ HEADER */
+	for (raw_data_index = 0; raw_data_index < EDID_HEADER_LENGTH;
+		raw_data_index++)
+		edid->header[raw_data_index] = raw_data[raw_data_index];
+
+	/*READ VENDOR & PRODUCT IDENTIFICATION */
+	/*manufacturer name */
+	edid->manufacturer_name[0] = ((raw_data[8] & 0x7C) >> 2) + 0x40;
+	edid->manufacturer_name[1] =
+		((raw_data[8] & 0x03) << 3) + ((raw_data[9] & 0xE0) >> 5) +
+		0x40;
+	edid->manufacturer_name[2] = ((raw_data[9] & 0x1F)) + 0x40;
+	edid->manufacturer_name[3] = 0;
+
+	/*product code */
+	edid->product_code = (raw_data[10]);
+	edid->product_code += ((unsigned short)raw_data[11]) << 8;
+
+	/*serial number */
+	edid->serial_number = raw_data[12];
+	edid->serial_number += (unsigned int)raw_data[13] << 8;
+	edid->serial_number += (unsigned int)raw_data[14] << 16;
+	edid->serial_number += (unsigned int)raw_data[15] << 24;
+
+	/*week of manufacture */
+	edid->week = raw_data[16];
+
+	/*year of manufacture */
+	edid->year = raw_data[17];
+
+	/*EDID STRUCTURE VERSION & REVISION */
+	edid->edid_version = ((unsigned short)raw_data[18] << 8) + raw_data[19];
+
+	/*BASIC DISPLAY PARAMETERS AND FEATURES */
+	/*video input definition */
+	edid->video_input_definition = raw_data[20];
+
+	/*horizontal screen size */
+	edid->horizontal_size = raw_data[21];
+
+	/*vertical screen size */
+	edid->vertical_size = raw_data[22];
+
+	/*display transfer characteristic */
+	edid->gamma = raw_data[23];
+
+	/*feature support */
+	edid->feature_support = raw_data[24];
+
+	/*COLOR CHARACTERISTIC */
+	/*red */
+	edid->chromacity_coorditates_red_x = (raw_data[25] & 0xC0) >> 6;
+	edid->chromacity_coorditates_red_x += (unsigned short)raw_data[27] << 2;
+	edid->chromacity_coorditates_red_y = (raw_data[25] & 0x30) >> 4;
+	edid->chromacity_coorditates_red_y += (unsigned short)raw_data[28] << 2;
+
+	/*green */
+	edid->chromacity_coorditates_green_x = (raw_data[25] & 0x0C) >> 2;
+	edid->chromacity_coorditates_green_x +=
+		(unsigned short)raw_data[29] << 2;
+	edid->chromacity_coorditates_green_y = (raw_data[25] & 0x03);
+	edid->chromacity_coorditates_green_y +=
+		(unsigned short)raw_data[30] << 2;
+
+	/*blue */
+	edid->chromacity_coorditates_blue_x = (raw_data[26] & 0xC0) >> 6;
+	edid->chromacity_coorditates_blue_x +=
+		(unsigned short)raw_data[31] << 2;
+	edid->chromacity_coorditates_blue_y = (raw_data[26] & 0x30) >> 4;
+	edid->chromacity_coorditates_blue_y +=
+		(unsigned short)raw_data[32] << 2;
+
+	/*blue */
+	edid->chromacity_coorditates_white_x = (raw_data[26] & 0x0C) >> 2;
+	edid->chromacity_coorditates_white_x +=
+		(unsigned short)raw_data[33] << 2;
+	edid->chromacity_coorditates_white_y = (raw_data[26] & 0x03);
+	edid->chromacity_coorditates_white_y +=
+		(unsigned short)raw_data[34] << 2;
+
+	/*ESTABLISHED TIMINGS */
+	edid->established_timing_1 = raw_data[35];
+	edid->established_timing_2 = raw_data[36];
+	edid->manufacturer_timing = raw_data[37];
+
+	/*STANDARD TIMINGS */
+	for (raw_data_index = 0; raw_data_index < 8; raw_data_index++) {
+		edid->standard_timings[raw_data_index] =
+			raw_data[38 + (2 * raw_data_index)];
+		edid->standard_timings[raw_data_index] +=
+			(unsigned short)raw_data[38 + (2 * raw_data_index + 1)];
+	}
+	/*extensions */
+	edid->extensions = raw_data[126];
+
+	/*DESCRIPTORS */
+	unsigned int descriptor_index;
+	raw_data_index = 54;
+	for (descriptor_index = 0; descriptor_index < 4; descriptor_index++) {
+		if (raw_data[raw_data_index] == 0 &&
+		    raw_data[raw_data_index + 1] == 0) {
+			/*display descriptor found */
+			unsigned char tag = raw_data[raw_data_index + 3];
+			if (tag == 0xFF) {
+				/*display product serial number */
+				S_SERIAL_NUMBER_DATA *descriptor =
+					(S_SERIAL_NUMBER_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_serial_number
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag == 0xFE) {
+				/*alphanumeric data string */
+				S_DATA_STRING_DATA *descriptor =
+					(S_DATA_STRING_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_data_string
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag == 0xFD) {
+				/*display range limits */
+				S_RANGE_LIMITS_DATA *descriptor =
+					(S_RANGE_LIMITS_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_range_limits
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag == 0xFC) {
+				/*display product name */
+				S_PRODUCT_NAME_DATA *descriptor =
+					(S_PRODUCT_NAME_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_product_name
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag == 0xFB) {
+				/*color point data */
+				S_COLOR_POINT_DATA *descriptor =
+					(S_COLOR_POINT_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_color_point
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag == 0xFA) {
+				/*standard timing identifications */
+				S_STANDARD_TIMING_DATA *descriptor =
+					(S_STANDARD_TIMING_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_standard_timing
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag == 0xF9) {
+				/*display color management (DCM) */
+				S_COLOR_MANAGEMENT_DATA *descriptor =
+					(S_COLOR_MANAGEMENT_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_color_management
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag == 0xF8) {
+				/*CVT 3 byte timing codes */
+				S_CVT_TIMING_CODES_DATA *descriptor =
+					(S_CVT_TIMING_CODES_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_cvt_timing_codes
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag == 0xF7) {
+				/*established timings III */
+				S_ESTABLISHED_TIMINGS_3_DATA *descriptor =
+					(S_ESTABLISHED_TIMINGS_3_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_established_timings_3
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag == 0x10) {
+				/*dummy */
+				S_DUMMY_DATA *descriptor =
+					(S_DUMMY_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_dummy
+					(descriptor,
+					 raw_data + raw_data_index) !=
+						EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+
+			} else if (tag <= 0x0F) {
+				/*manufacturer specific data */
+				S_MANUFACTURER_SPECIFIC_DATA *descriptor =
+					(S_MANUFACTURER_SPECIFIC_DATA *)edid->
+					descriptors[descriptor_index];
+				if (edid_parse_manufacturer_specific
+					(descriptor, raw_data + raw_data_index,
+					 tag) != EDID_PARSER_SUCCESS)
+					return EDID_PARSER_ERROR;
+			}
+		} else {
+			/*detailed timing definition */
+			S_DTD_DATA *descriptor =
+				(S_DTD_DATA *)edid->
+				descriptors[descriptor_index];
+			if (edid_parse_dtd
+				(descriptor,
+				 raw_data + raw_data_index) !=
+				 EDID_PARSER_SUCCESS)
+				return EDID_PARSER_ERROR;
+		}
+		raw_data_index += 18;
+	}
+
+	return EDID_PARSER_SUCCESS;
+}
diff --git a/drivers/video/nxp/hdp/edid_parser.h b/drivers/video/nxp/hdp/edid_parser.h
new file mode 100644
index 00000000000..13eb0b1882b
--- /dev/null
+++ b/drivers/video/nxp/hdp/edid_parser.h
@@ -0,0 +1,297 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2015-2016 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * edid_parser.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef EDID_PARSER_H
+#define EDID_PARSER_H
+
+#define MAX_DESCRIPTOR_LENGTH 36
+#define MAX_RANGE_LIMITS_VIDEO_TIMING_LENGTH 12
+#define EDID_HEADER_LENGTH 8
+#define EDID_LENGTH 128
+
+typedef enum {
+	EDID_PARSER_SUCCESS,
+	EDID_PARSER_ERROR,
+} EDID_PARSER_RESULT;
+
+typedef enum {
+	DESCRIPTOR_TYPE_DTD,
+	DESCRIPTOR_TYPE_SERIAL_NUMBER,
+	DESCRIPTOR_TYPE_DATA_STRING,
+	DESCRIPTOR_TYPE_RANGE_LIMITS,
+	DESCRIPTOR_TYPE_PRODUCT_NAME,
+	DESCRIPTOR_TYPE_COLOR_POINT,
+	DESCRIPTOR_TYPE_STANDARD_TIMING,
+	DESCRIPTOR_TYPE_COLOR_MANAGEMENT,
+	DESCRIPTOR_TYPE_CVT_TIMING_CODES,
+	DESCRIPTOR_TYPE_ESTABLISHED_TIMINGS_3,
+	DESCRIPTOR_TYPE_DUMMY,
+	DESCRIPTOR_TYPE_MANUFACTURER_SPECIFIC
+} EDID_DESCRIPTOR_TYPE;
+
+typedef enum {
+	VIDEO_TIMING_DEFAULT_GTF,
+	VIDEO_TIMING_RANGE_LIMITS_ONLY,
+	VIDEO_TIMING_SECONDARY_GTF,
+	VIDEO_TIMING_CVT,
+} RANGE_LIMITS_VIDEO_TIMING_TYPE;
+
+/**
+ *  \brief Common descriptor header structure
+ */
+typedef struct {
+	EDID_DESCRIPTOR_TYPE type;
+	unsigned char tag;
+
+} S_DESCRIPTOR_HEADER_DATA;
+/**
+ *  \brief Detailed Timing Descriptor (DTD) structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	unsigned short pixel_clock;
+	unsigned short horizontal_addressable_video;
+	unsigned short horizontal_blanking;
+	unsigned short vertical_addressable_video;
+	unsigned short vertical_blanking;
+	unsigned short horizontal_front_porch;
+	unsigned short horizontal_sync_pulse_width;
+	unsigned short vertical_front_porch;
+	unsigned short vertical_sync_pulse_width;
+	unsigned short horizontal_addressable_video_image_size;
+	unsigned short vertical_addressable_video_image_size;
+	unsigned char horizontal_border;
+	unsigned char vertical_border;
+	unsigned char signal_features;
+} S_DTD_DATA;
+
+/**
+ *  \brief Serial Number Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	unsigned char serial_number[13];
+
+} S_SERIAL_NUMBER_DATA;
+
+/**
+ *  \brief Data String Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	char data_string[13];
+
+} S_DATA_STRING_DATA;
+
+/**
+ *  \brief Range Limits Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	unsigned char offset_flags;
+	unsigned char min_vertical_rate;
+	unsigned char max_vertical_rate;
+	unsigned char min_horizontal_rate;
+	unsigned char max_horizontal_rate;
+	unsigned char max_pixel_clock;
+	RANGE_LIMITS_VIDEO_TIMING_TYPE type;
+	unsigned char suport_flags[MAX_RANGE_LIMITS_VIDEO_TIMING_LENGTH];
+} S_RANGE_LIMITS_DATA;
+
+/**
+ *  \brief Range Limits Secondary GTF Flags structure
+ */
+typedef struct {
+	unsigned char start_break_frequency;
+	unsigned char c;
+	unsigned short m;
+	unsigned char k;
+	unsigned char j;
+
+} S_RANGE_LIMITS_VIDEO_TIMING_SECONDARY_GTF;
+
+/**
+ *  \brief Range Limits CVT Flags structure
+ */
+typedef struct {
+	unsigned char cvt_version;
+	unsigned char additional_pixel_clock_precision;
+	unsigned short max_active_pixels;
+	unsigned char supported_ar;
+	unsigned char preferred_ar;
+	unsigned char blanking_support;
+	unsigned char supported_scalling;
+	unsigned char preferred_vertical_refresh_rate;
+} S_RANGE_LIMITS_VIDEO_TIMING_CVT;
+
+/**
+ *  \brief Product Name Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	char product_name[13];
+
+} S_PRODUCT_NAME_DATA;
+
+/**
+ *  \brief Color point Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	unsigned char white_point_index_1;
+	unsigned short white_x_1;
+	unsigned short white_y_1;
+	unsigned char gamma_1;
+	unsigned char white_point_index_2;
+	unsigned short white_x_2;
+	unsigned short white_y_2;
+	unsigned char gamma_2;
+} S_COLOR_POINT_DATA;
+
+/**
+ *  \brief Standard Timing Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	unsigned short standard_timings[6];
+} S_STANDARD_TIMING_DATA;
+
+/**
+ *  \brief Color Management Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	unsigned char version;
+	unsigned short red_a3;
+	unsigned short red_a2;
+	unsigned short green_a3;
+	unsigned short green_a2;
+	unsigned short blue_a3;
+	unsigned short blue_a2;
+} S_COLOR_MANAGEMENT_DATA;
+
+/**
+ *  \brief CVT 3 Byte Code Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	unsigned char version;
+	unsigned short addressable_lines[4];
+	unsigned char aspect_ratio[4];
+	unsigned char preferred_vertical_rate[4];
+	unsigned char supported_vertical_rate_and_blanking[4];
+
+} S_CVT_TIMING_CODES_DATA;
+
+/**
+ *  \brief Established Timings 3 Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	unsigned char version;
+	unsigned char established_timings[6];
+} S_ESTABLISHED_TIMINGS_3_DATA;
+
+/**
+ *  \brief Dummy Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+} S_DUMMY_DATA;
+
+/**
+ *  \brief Manufacturer Specific Descriptor structure
+ */
+typedef struct {
+	S_DESCRIPTOR_HEADER_DATA header;
+	unsigned char desc_data[18];
+} S_MANUFACTURER_SPECIFIC_DATA;
+
+/**
+ *  \brief CEA-861 extension structure
+ */
+typedef struct {
+	unsigned char revision;
+	unsigned char underscan;
+	unsigned char audio;
+} S_CEA861_DATA;
+
+/**
+ *  \brief Extended Display Identification Data (EDID) structure
+ */
+typedef struct {
+	unsigned char header[8];
+	char manufacturer_name[4];
+	unsigned short product_code;
+	unsigned int serial_number;
+	unsigned char week;
+	unsigned short year;
+	unsigned short edid_version;
+	unsigned char video_input_definition;
+	unsigned char horizontal_size;
+	unsigned char vertical_size;
+	unsigned char gamma;
+	unsigned char feature_support;
+	unsigned short chromacity_coorditates_red_x;
+	unsigned short chromacity_coorditates_red_y;
+	unsigned short chromacity_coorditates_green_x;
+	unsigned short chromacity_coorditates_green_y;
+	unsigned short chromacity_coorditates_blue_x;
+	unsigned short chromacity_coorditates_blue_y;
+	unsigned short chromacity_coorditates_white_x;
+	unsigned short chromacity_coorditates_white_y;
+	unsigned char established_timing_1;
+	unsigned char established_timing_2;
+	unsigned char manufacturer_timing;
+	unsigned short standard_timings[8];
+	unsigned char descriptors[4][MAX_DESCRIPTOR_LENGTH];
+	unsigned char extensions;
+} S_EDID_DATA;
+
+EDID_PARSER_RESULT edid_parse(S_EDID_DATA *edid, unsigned char *raw_data,
+			      unsigned int len);
+
+#endif				/* EDID_PARSER_H */
diff --git a/drivers/video/nxp/hdp/externs.h b/drivers/video/nxp/hdp/externs.h
new file mode 100644
index 00000000000..4a722c64b14
--- /dev/null
+++ b/drivers/video/nxp/hdp/externs.h
@@ -0,0 +1,54 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ ******************************************************************************
+ *
+ * externs.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef EXTERNS_H_
+#define EXTERNS_H_
+
+#ifndef __UBOOT__
+#include <stdint.h>
+
+#else
+#include <common.h>
+#endif
+/**
+ * \addtogroup UTILS
+ * \{
+ */
+/**
+ * \brief read from apb
+ * \param addr - address to read
+ * \param value - pointer to store value
+ * \return non-zero value if error
+ */
+/*extern int cdn_bus_read(unsigned int addr, unsigned int* value);*/
+
+/**
+ * \brief write to apb
+ * \param addr - address to write
+ * \param value - value to write
+ * \return non-zero if error
+ */
+/*extern int cdn_bus_write(unsigned int addr, unsigned int value);*/
+
+u32 cdn_apb_read(u32 addr, u32 *value);
+u32 cdn_sapb_read(u32 addr, u32 *value);
+u32 cdn_apb_write(u32 addr, u32 value);
+u32 cdn_sapb_write(u32 addr, u32 value);
+u32 hdp_rx_apb_read(u32 addr, u32 *value);
+u32 hdp_rx_sapb_read(u32 addr, u32 *value);
+u32 hdp_rx_apb_write(u32 addr, u32 value);
+u32 hdp_rx_sapb_write(u32 addr, u32 value);
+#endif
diff --git a/drivers/video/nxp/hdp/general_handler.h b/drivers/video/nxp/hdp/general_handler.h
new file mode 100644
index 00000000000..24b1346c7e1
--- /dev/null
+++ b/drivers/video/nxp/hdp/general_handler.h
@@ -0,0 +1,132 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ ******************************************************************************
+ *
+ * general_handler.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef GENERAL_HANDLER_H
+#define GENERAL_HANDLER_H
+
+/**
+ *  \file
+ *  \brief general handler, checks available messages, receives
+ *         it from mailbox, handles requests and sends response
+ *         to the host
+ */
+#define DP_TX_MAIL_HANDLER_REQUEST_BUFFER_LEN 256
+
+/**
+ *  \brief opcode defines host->controller
+ */
+#define GENERAL_MAIN_CONTROL            0x01
+#define GENERAL_TEST_ECHO               0x02
+#define GENERAL_BUS_SETTINGS            0x03
+#define GENERAL_TEST_ACCESS             0x04
+
+#define GENERAL_WRITE_REGISTER          0x05
+#define GENERAL_WRITE_FIELD             0x06
+#define GENERAL_READ_REGISTER           0x07
+#define GENERAL_GET_HPD_STATE           0x11
+
+#define GENERAL_TEST_TRNG_SIMPLE        0xF0
+
+#define GENERAL_MAIN_CONTROL_SET_ACTIVE_BIT         0
+#define GENERAL_MAIN_CONTROL_SET_ALT_CIPHER_ADDR    1
+#define GENERAL_MAIN_CONTROL_SET_FAST_HDCP_DELAYS   2
+
+#define GENERAL_BUS_SETTINGS_DPCD_BUS_BIT           0
+#define GENERAL_BUS_SETTINGS_DPCD_BUS_LOCK_BIT      1
+#define GENERAL_BUS_SETTINGS_HDCP_BUS_BIT           2
+#define GENERAL_BUS_SETTINGS_HDCP_BUS_LOCK_BIT      3
+#define GENERAL_BUS_SETTINGS_CAPB_OWNER_BIT         4
+#define GENERAL_BUS_SETTINGS_CAPB_OWNER_LOCK_BIT    5
+
+/**
+ *  \brief opcode defines controller->host
+ */
+
+#define GENERAL_MAIN_CONTROL_RESP        0x01
+#define GENERAL_TEST_ECHO_RESP           0x02
+#define GENERAL_BUS_SETTINGS_RESP        0x03
+
+#define GENERAL_READ_REGISTER_RESP       0x07
+
+#define GENERAL_BUS_SETTINGS_RESP_DPCD_BUS_BIT      0
+#define GENERAL_BUS_SETTINGS_RESP_HDCP_BUS_BIT      1
+#define GENERAL_BUS_SETTINGS_RESP_CAPB_OWNER_BIT    2
+
+#define GENERAL_BUS_SETTINGS_RESP_SUCCESS           0
+#define GENERAL_BUS_SETTINGS_RESP_LOCK_ERROR        1
+
+typedef struct {
+	unsigned char dpcd_locked;
+	unsigned char hdcp_locked;
+	unsigned char capb_locked;
+	unsigned char active_mode;
+} S_GENERAL_HANDLER_DATA;
+
+/**
+ *  \brief event id sent to the host
+ */
+typedef enum {
+	EVENT_ID_DPTX_HPD = 0,
+	EVENT_ID_HDMI_TX_HPD = 0,
+	EVENT_ID_HDMI_RX_5V = 0,
+
+	EVENT_ID_DPTX_TRAINING = 1,
+	EVENT_ID_HDMI_RX_SCDC_CHANGE = 1,
+
+	EVENT_ID_RESERVE0 = 2,
+	EVENT_ID_RESERVE1 = 3,
+
+	EVENT_ID_HDCPTX_STATUS = 4,
+	EVENT_ID_HDCPRX_STATUS = 4,
+
+	EVENT_ID_HDCPTX_IS_KM_STORED = 5,
+	EVENT_ID_HDCPTX_STORE_KM = 6,
+	EVENT_ID_HDCPTX_IS_RECEIVER_ID_VALID = 7,
+	EVENT_ID_HDMITX_READ_REQUEST = 8,
+} EVENT_ID;
+
+/**
+ * \brief convert bank id and register number to address and write to ptr
+ */
+
+#define select_reg_old(bank, reg_no, ptr) \
+do { \
+	ptr = 0; \
+	if ((bank == 0x22) || (bank == 0x20) || (bank == 0x0b) || \
+	    (bank == 0x09) || (bank == 0x0A)) \
+		ptr = (unsigned int *)(bank << 8 | reg_no); \
+} while (0)
+
+#define select_reg(bank, reg_no, ptr) \
+	ptr = (unsigned int *)(bank << 8 | reg_no)
+
+#define select_reg4(pmsb, p2, p3, plsb, ptr) \
+	ptr = (unsigned int *)((pmsb << 24) | (p2 << 16) | \
+			       (p3 << 8) | (plsb << 0))
+
+#define EVENTS_DPTX_CNT 2
+#define EVENTS_HDCPTX_CNT 4
+
+void general_handler_set_active_mode(void);
+void general_handler_set_standby_mode(void);
+
+/**
+ *  \brief request sending en event to the host
+ *  \param [in] eventId
+ *  \param [in] eventCode
+ */
+
+#endif				/* GENERAL_HANDLER_H */
diff --git a/drivers/video/nxp/hdp/hdmi.h b/drivers/video/nxp/hdp/hdmi.h
new file mode 100644
index 00000000000..a8989829f26
--- /dev/null
+++ b/drivers/video/nxp/hdp/hdmi.h
@@ -0,0 +1,124 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2015-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * hdmi.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef _HDMI__
+#define _HDMI__
+/* ONLY ENUMS AND #DEFINES IN THIS FILE *
+ * THIS FILE WILL BE USED IN HOST'S API */
+
+#define EDID_SLAVE_ADDRESS                  0x50
+#define EDID_SEGMENT_SLAVE_ADDRESS          0x30
+#define SCDC_SLAVE_ADDRESS                  0x54
+
+typedef enum {
+	HDMI_TX_READ,
+	HDMI_TX_WRITE,
+	HDMI_TX_UPDATE_READ,
+	HDMI_TX_EDID,
+	HDMI_TX_EVENTS,
+	HDMI_TX_HPD_STATUS,
+	HDMI_TX_DEBUG_ECHO = 0xAA,
+	HDMI_TX_TEST = 0xBB,
+	HDMI_TX_EDID_INTERNAL = 0xF0,
+} HDMI_TX_OPCODE;
+
+typedef enum {
+	HDMI_I2C_ACK,
+	HDMI_I2C_NACK,
+	HDMI_I2C_TO,
+	HDMI_I2C_ARB_LOST,
+	HDMI_I2C_RRTO,
+	HDMI_I2C_RRT,
+    /** when i2c hardware didn't respond after some time */
+	HDMI_I2C_HW_TO,
+	HDMI_I2C_ERR		/*unspecified error */
+} HDMI_I2C_STATUS;
+
+typedef enum {
+	HDMI_RX_SET_EDID,
+	HDMI_RX_SCDC_SET,
+	HDMI_RX_SCDC_GET,
+	HDMI_RX_READ_EVENTS,
+	HDMI_RX_SET_HPD,
+
+	HDMI_RX_DEBUG_ECHO = 0xAA,
+	HDMI_RX_TEST = 0xBB,
+} HDMI_RX_OPCODE;
+
+typedef enum {
+	HDMI_SCDC_SINK_VER,
+	HDMI_SCDC_SOURCE_VER,
+} HDMI_SCDC_FIELD;
+
+/*/////////////////////////////////////// */
+/*/////////////////////////////////////// */
+typedef struct {
+	unsigned char sink_ver;
+	unsigned char manufacturer_oui_1;
+	unsigned char manufacturer_oui_2;
+	unsigned char manufacturer_oui_3;
+	unsigned char devId[8];
+	unsigned char hardware_major_rev;
+	unsigned char hardware_minor_rev;
+	unsigned char software_major_rev;
+	unsigned char software_minor_rev;
+	unsigned char manufacturerSpecific[34];
+} S_HDMI_SCDC_SET_MSG;
+
+typedef struct {
+	unsigned char source_ver;
+	unsigned char TMDS_Config;
+	unsigned char config_0;
+	unsigned char manufacturerSpecific[34];
+} S_HDMI_SCDC_GET_MSG;
+
+/*hpd events location */
+#define HDMI_RX_EVENT_5V_HIGH            0
+#define HDMI_RX_EVENT_5V_LOW             1
+#define HDMI_TX_EVENT_reserved           2
+#define HDMI_RX_EVENT_5V_VAL             3
+
+#endif /*_HDMI__ */
diff --git a/drivers/video/nxp/hdp/mhl_hdtx_top.h b/drivers/video/nxp/hdp/mhl_hdtx_top.h
new file mode 100644
index 00000000000..ee105f82489
--- /dev/null
+++ b/drivers/video/nxp/hdp/mhl_hdtx_top.h
@@ -0,0 +1,220 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * mhl_hdtx_top.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef MHL_HDTX_TOP_H_
+#define MHL_HDTX_TOP_H_
+
+/* register SCHEDULER_H_SIZE */
+#define SCHEDULER_H_SIZE 0
+#define F_H_BLANK_SIZE(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_H_BLANK_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+#define F_H_ACTIVE_SIZE(x) (((x) & ((1 << 16) - 1)) << 16)
+#define F_H_ACTIVE_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16)
+
+/* register SCHEDULER_V_SIZE */
+#define SCHEDULER_V_SIZE 1
+#define F_V_BLANK_SIZE(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_V_BLANK_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+#define F_V_ACTIVE_SIZE(x) (((x) & ((1 << 16) - 1)) << 16)
+#define F_V_ACTIVE_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16)
+
+/* register SCHEDULER_KEEP_OUT */
+#define SCHEDULER_KEEP_OUT 2
+#define F_HKEEP_OUT(x) (((x) & ((1 << 9) - 1)) << 0)
+#define F_HKEEP_OUT_RD(x) (((x) & (((1 << 9) - 1) << 0)) >> 0)
+#define F_VKEEP_OUT_START(x) (((x) & ((1 << 11) - 1)) << 9)
+#define F_VKEEP_OUT_START_RD(x) (((x) & (((1 << 11) - 1) << 9)) >> 9)
+#define F_VKEEP_OUT_ZONE(x) (((x) & ((1 << 8) - 1)) << 20)
+#define F_VKEEP_OUT_ZONE_RD(x) (((x) & (((1 << 8) - 1) << 20)) >> 20)
+
+/* register HDTX_SIGNAL_FRONT_WIDTH */
+#define HDTX_SIGNAL_FRONT_WIDTH 3
+#define F_HFRONT(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_HFRONT_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+#define F_VFRONT(x) (((x) & ((1 << 16) - 1)) << 16)
+#define F_VFRONT_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16)
+
+/* register HDTX_SIGNAL_SYNC_WIDTH */
+#define HDTX_SIGNAL_SYNC_WIDTH 4
+#define F_HSYNC(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_HSYNC_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+#define F_VSYNC(x) (((x) & ((1 << 16) - 1)) << 16)
+#define F_VSYNC_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16)
+
+/* register HDTX_SIGNAL_BACK_WIDTH */
+#define HDTX_SIGNAL_BACK_WIDTH 5
+#define F_HBACK(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_HBACK_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+#define F_VBACK(x) (((x) & ((1 << 16) - 1)) << 16)
+#define F_VBACK_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16)
+
+/* register HDTX_CONTROLLER */
+#define HDTX_CONTROLLER 6
+#define F_HDMI_MODE(x) (((x) & ((1 << 2) - 1)) << 0)
+#define F_HDMI_MODE_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
+#define F_VIF_DATA_WIDTH(x) (((x) & ((1 << 2) - 1)) << 2)
+#define F_VIF_DATA_WIDTH_RD(x) (((x) & (((1 << 2) - 1) << 2)) >> 2)
+#define F_AUTO_MODE(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_AUTO_MODE_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
+#define F_IL_PROG(x) (((x) & ((1 << 2) - 1)) << 5)
+#define F_IL_PROG_RD(x) (((x) & (((1 << 2) - 1) << 5)) >> 5)
+#define F_PIC_3D(x) (((x) & ((1 << 4) - 1)) << 7)
+#define F_PIC_3D_RD(x) (((x) & (((1 << 4) - 1) << 7)) >> 7)
+#define F_BCH_EN(x) (((x) & ((1 << 1) - 1)) << 11)
+#define F_BCH_EN_RD(x) (((x) & (((1 << 1) - 1) << 11)) >> 11)
+#define F_GCP_EN(x) (((x) & ((1 << 1) - 1)) << 12)
+#define F_GCP_EN_RD(x) (((x) & (((1 << 1) - 1) << 12)) >> 12)
+#define F_SET_AVMUTE(x) (((x) & ((1 << 1) - 1)) << 13)
+#define F_SET_AVMUTE_RD(x) (((x) & (((1 << 1) - 1) << 13)) >> 13)
+#define F_CLEAR_AVMUTE(x) (((x) & ((1 << 1) - 1)) << 14)
+#define F_CLEAR_AVMUTE_RD(x) (((x) & (((1 << 1) - 1) << 14)) >> 14)
+#define F_DATA_EN(x) (((x) & ((1 << 1) - 1)) << 15)
+#define F_DATA_EN_RD(x) (((x) & (((1 << 1) - 1) << 15)) >> 15)
+#define F_HDMI_ENCODING(x) (((x) & ((1 << 2) - 1)) << 16)
+#define F_HDMI_ENCODING_RD(x) (((x) & (((1 << 2) - 1) << 16)) >> 16)
+#define F_HDMI2_PREAMBLE_EN(x) (((x) & ((1 << 1) - 1)) << 18)
+#define F_HDMI2_PREAMBLE_EN_RD(x) (((x) & (((1 << 1) - 1) << 18)) >> 18)
+#define F_HDMI2_CTRL_IL_MODE(x) (((x) & ((1 << 1) - 1)) << 19)
+#define F_HDMI2_CTRL_IL_MODE_RD(x) (((x) & (((1 << 1) - 1) << 19)) >> 19)
+
+/* register HDTX_HDCP */
+#define HDTX_HDCP 7
+#define F_HDTX_HDCP_SELECT(x) (((x) & ((1 << 2) - 1)) << 0)
+#define F_HDTX_HDCP_SELECT_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
+#define F_ENC_BIT(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_ENC_BIT_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_HDCP_ENABLE_1P1_FEATURES(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_HDCP_ENABLE_1P1_FEATURES_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+#define F_HDCP_DELAY_FIFO_SW_RST(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_HDCP_DELAY_FIFO_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
+#define F_HDCP_DELAY_FIFO_SW_START(x) (((x) & ((1 << 1) - 1)) << 5)
+#define F_HDCP_DELAY_FIFO_SW_START_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5)
+#define F_HDCP_DOUBLE_FIFO_SW_RST(x) (((x) & ((1 << 1) - 1)) << 6)
+#define F_HDCP_DOUBLE_FIFO_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6)
+#define F_HDCP_SINGLE_FIFO_SW_RST(x) (((x) & ((1 << 1) - 1)) << 7)
+#define F_HDCP_SINGLE_FIFO_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7)
+#define F_HDCP_DELAY_FIFO_AFULL_THR(x) (((x) & ((1 << 4) - 1)) << 8)
+#define F_HDCP_DELAY_FIFO_AFULL_THR_RD(x) (((x) & (((1 << 4) - 1) << 8)) >> 8)
+#define F_HDCP_CTRL_SW_RST(x) (((x) & ((1 << 1) - 1)) << 12)
+#define F_HDCP_CTRL_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 12)) >> 12)
+#define F_HDCP_CTRL_IL_MODE(x) (((x) & ((1 << 1) - 1)) << 13)
+#define F_HDCP_CTRL_IL_MODE_RD(x) (((x) & (((1 << 1) - 1) << 13)) >> 13)
+
+/* register HDTX_HPD */
+#define HDTX_HPD 8
+#define F_HPD_VALID_WIDTH(x) (((x) & ((1 << 12) - 1)) << 0)
+#define F_HPD_VALID_WIDTH_RD(x) (((x) & (((1 << 12) - 1) << 0)) >> 0)
+#define F_HPD_GLITCH_WIDTH(x) (((x) & ((1 << 8) - 1)) << 12)
+#define F_HPD_GLITCH_WIDTH_RD(x) (((x) & (((1 << 8) - 1) << 12)) >> 12)
+
+/* register HDTX_CLOCK_REG_0 */
+#define HDTX_CLOCK_REG_0 9
+#define F_DATA_REGISTER_VAL_0(x) (((x) & ((1 << 20) - 1)) << 0)
+#define F_DATA_REGISTER_VAL_0_RD(x) (((x) & (((1 << 20) - 1) << 0)) >> 0)
+
+/* register HDTX_CLOCK_REG_1 */
+#define HDTX_CLOCK_REG_1 10
+#define F_DATA_REGISTER_VAL_1(x) (((x) & ((1 << 20) - 1)) << 0)
+#define F_DATA_REGISTER_VAL_1_RD(x) (((x) & (((1 << 20) - 1) << 0)) >> 0)
+
+/* register HPD_PLUG_IN */
+#define HPD_PLUG_IN 11
+#define F_FILTER_HPD(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_FILTER_HPD_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+
+/* register HDCP_IN */
+#define HDCP_IN 12
+#define F_HDCP_ESS_STATE(x) (((x) & ((1 << 4) - 1)) << 0)
+#define F_HDCP_ESS_STATE_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+#define F_HDCP_DOUBLE_FIFO_WFULL(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_HDCP_DOUBLE_FIFO_WFULL_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
+#define F_HDCP_DOUBLE_FIFO_REMPTY(x) (((x) & ((1 << 1) - 1)) << 5)
+#define F_HDCP_DOUBLE_FIFO_REMPTY_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5)
+#define F_HDCP_DOUBLE_FIFO_OVERRUN(x) (((x) & ((1 << 1) - 1)) << 6)
+#define F_HDCP_DOUBLE_FIFO_OVERRUN_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6)
+#define F_HDCP_DOUBLE_FIFO_UNDERRUN(x) (((x) & ((1 << 1) - 1)) << 7)
+#define F_HDCP_DOUBLE_FIFO_UNDERRUN_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7)
+#define F_HDCP_DELAY_FIFO_EMPTY(x) (((x) & ((1 << 1) - 1)) << 8)
+#define F_HDCP_DELAY_FIFO_EMPTY_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8)
+#define F_HDCP_DELAY_FIFO_FULL(x) (((x) & ((1 << 1) - 1)) << 9)
+#define F_HDCP_DELAY_FIFO_FULL_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9)
+#define F_HDCP_SINGLE_FIFO_WFULL(x) (((x) & ((1 << 2) - 1)) << 10)
+#define F_HDCP_SINGLE_FIFO_WFULL_RD(x) (((x) & (((1 << 2) - 1) << 10)) >> 10)
+#define F_HDCP_SINGLE_FIFO_REMPTY(x) (((x) & ((1 << 2) - 1)) << 12)
+#define F_HDCP_SINGLE_FIFO_REMPTY_RD(x) (((x) & (((1 << 2) - 1) << 12)) >> 12)
+#define F_HDCP_SINGLE_FIFO_OVERRUN(x) (((x) & ((1 << 2) - 1)) << 14)
+#define F_HDCP_SINGLE_FIFO_OVERRUN_RD(x) (((x) & (((1 << 2) - 1) << 14)) >> 14)
+#define F_HDCP_SINGLE_FIFO_UNDERRUN(x) (((x) & ((1 << 2) - 1)) << 16)
+#define F_HDCP_SINGLE_FIFO_UNDERRUN_RD(x) (((x) & (((1 << 2) - 1) << 16)) >> 16)
+
+/* register GCP_FORCE_COLOR_DEPTH_CODING */
+#define GCP_FORCE_COLOR_DEPTH_CODING 13
+#define F_COLOR_DEPTH_VAL(x) (((x) & ((1 << 4) - 1)) << 0)
+#define F_COLOR_DEPTH_VAL_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+#define F_COLOR_DEPTH_FORCE(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_COLOR_DEPTH_FORCE_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
+#define F_DEFAULT_PHASE_VAL(x) (((x) & ((1 << 1) - 1)) << 5)
+#define F_DEFAULT_PHASE_VAL_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5)
+
+/* register SSCP_POSITIONING */
+#define SSCP_POSITIONING 14
+#define F_SSCP_ROW_VAL(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_SSCP_ROW_VAL_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+#define F_SSCP_COL_VAL(x) (((x) & ((1 << 16) - 1)) << 16)
+#define F_SSCP_COL_VAL_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16)
+
+/* register HDCP_WIN_OF_OPP_POSITION */
+#define HDCP_WIN_OF_OPP_POSITION 15
+#define F_HDCP_WIN_OF_OPP_START(x) (((x) & ((1 << 10) - 1)) << 0)
+#define F_HDCP_WIN_OF_OPP_START_RD(x) (((x) & (((1 << 10) - 1) << 0)) >> 0)
+#define F_HDCP_WIN_OF_OPP_SIZE(x) (((x) & ((1 << 6) - 1)) << 10)
+#define F_HDCP_WIN_OF_OPP_SIZE_RD(x) (((x) & (((1 << 6) - 1) << 10)) >> 10)
+
+#endif				/*MHL_HDTX_TOP */
diff --git a/drivers/video/nxp/hdp/opcodes.h b/drivers/video/nxp/hdp/opcodes.h
new file mode 100644
index 00000000000..dc2fde85d68
--- /dev/null
+++ b/drivers/video/nxp/hdp/opcodes.h
@@ -0,0 +1,85 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * opcodes.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef OPCODES_H_
+# define OPCODES_H_
+
+# define DP_TX_MAIL_HANDLER_H
+# define DP_TX_MAIL_HANDLER_REQUEST_BUFFER_LEN 256
+# define DPTX_SET_POWER_MNG              0x00
+# define DPTX_SET_HOST_CAPABILITIES      0x01
+# define DPTX_GET_EDID                   0x02
+# define DPTX_READ_DPCD                  0x03
+# define DPTX_WRITE_DPCD                 0x04
+# define DPTX_ENABLE_EVENT               0x05
+# define DPTX_WRITE_REGISTER             0x06
+# define DPTX_READ_REGISTER              0x07
+# define DPTX_WRITE_FIELD                0x08
+# define DPTX_TRAINING_CONTROL           0x09
+# define DPTX_READ_EVENT                 0x0A
+# define DPTX_READ_LINK_STAT                0x0B
+# define DPTX_SET_VIDEO                    0x0C
+# define DPTX_SET_AUDIO                    0x0D
+# define DPTX_GET_LAST_AUX_STAUS            0x0E
+# define DPTX_SET_LINK_BREAK_POINT        0x0F
+# define DPTX_FORCE_LANES                0x10
+# define DPTX_HPD_STATE                             0x11
+# define DPTX_DBG_SET                               0xF0
+# define DP_TX_OPCODE_READ_I2C_REQUEST              0xA5
+# define DP_TX_OPCODE_WRITE_I2C_REQUEST             0xA6
+# define DP_TX_OPCODE_MESSAGE_FILTER                0xA7
+# define DPTX_EDID_RESP                             0x02
+# define DPTX_DPCD_READ_RESP                        0x03
+# define DPTX_DPCD_WRITE_RESP                       0x04
+# define DPTX_READ_EVENT_RESP                       0x0A
+# define DPTX_READ_REGISTER_RESP                    0x07
+# define DP_TX_OPCODE_MESSAGE                       0x10
+# define DP_TX_OPCODE_READ_I2C_RESPONSE             0x50
+# define DP_TX_OPCODE_WRITE_I2C_RESPONSE            0x60
+# define DP_TX_OPCODE_LOOPBACK_TEST                 0xFE
+# define DP_TX_OPCODE_BIT_TEST                      0xFF
+# define DP_TX_EVENT_ENABLE_HPD_BIT                 0x00
+# define DP_TX_EVENT_ENABLE_TRAINING_BIT            0x01
+# define DP_TX_EVENT_CODE_HPD_HIGH                  0x01
+# define DP_TX_EVENT_CODE_HPD_LOW                   0x02
+# define DP_TX_EVENT_CODE_HPD_PULSE                 0x04
+# define DP_TX_EVENT_CODE_HPD_STATE_HIGH            0x08
+# define DP_TX_EVENT_CODE_HPD_STATE_LOW             0x00
+# define DP_TX_EVENT_CODE_TRAINING_FULL_STARTED     0x01
+# define DP_TX_EVENT_CODE_TRAINING_FAST_STARTED     0x02
+# define DP_TX_EVENT_CODE_TRAINING_FINISHED_CR      0x04
+# define DP_TX_EVENT_CODE_TRAINING_FINISHED_EQ      0x08
+# define DP_TX_EVENT_CODE_TRAINING_FINISHED_FAST    0x10
+# define DP_TX_EVENT_CODE_TRAINING_FAILED_CR        0x20
+# define DP_TX_EVENT_CODE_TRAINING_FAILED_EQ        0x40
+# define DP_TX_EVENT_CODE_TRAINING_FAILED_FAST      0x80
+# define MB_MODULE_ID_DP_TX                         0x01
+# define MB_MODULE_ID_DP_RX                         0x02
+# define MB_MODULE_ID_HDMI_TX                       0x03
+# define MB_MODULE_ID_HDMI_RX                       0x04
+# define MB_MODULE_ID_MHL_TX                        0x05
+# define MB_MODULE_ID_MHL_RX                        0x06
+# define MB_MODULE_ID_HDCP_TX                       0x07
+# define MB_MODULE_ID_HDCP_RX                       0x08
+# define MB_MODULE_ID_HDCP_GENERAL                  0x09
+# define MB_MODULE_ID_GENERAL                       0x0A
+# define MB_MODULE_ID                               1
+
+#endif
diff --git a/drivers/video/nxp/hdp/source_car.h b/drivers/video/nxp/hdp/source_car.h
new file mode 100644
index 00000000000..1a5f85f8aaa
--- /dev/null
+++ b/drivers/video/nxp/hdp/source_car.h
@@ -0,0 +1,179 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * source_car.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef SOURCE_CAR_H_
+#define SOURCE_CAR_H_
+
+/* register SOURCE_HDTX_CAR */
+#define SOURCE_HDTX_CAR 0
+#define F_HDTX_PIXEL_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_HDTX_PIXEL_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_HDTX_PIXEL_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_HDTX_PIXEL_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_HDTX_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_HDTX_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_HDTX_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_HDTX_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+#define F_HDTX_PHY_DATA_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_HDTX_PHY_DATA_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
+#define F_HDTX_PHY_DATA_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 5)
+#define F_HDTX_PHY_DATA_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5)
+#define F_HDTX_PHY_CHAR_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 6)
+#define F_HDTX_PHY_CHAR_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6)
+#define F_HDTX_PHY_CHAR_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 7)
+#define F_HDTX_PHY_CHAR_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7)
+
+/* register SOURCE_DPTX_CAR */
+#define SOURCE_DPTX_CAR 1
+#define F_CFG_DPTX_VIF_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_CFG_DPTX_VIF_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_CFG_DPTX_VIF_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_CFG_DPTX_VIF_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_DPTX_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_DPTX_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_DPTX_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_DPTX_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+#define F_SOURCE_AUX_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_SOURCE_AUX_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
+#define F_SOURCE_AUX_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 5)
+#define F_SOURCE_AUX_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5)
+#define F_DPTX_PHY_CHAR_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 6)
+#define F_DPTX_PHY_CHAR_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6)
+#define F_DPTX_PHY_CHAR_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 7)
+#define F_DPTX_PHY_CHAR_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7)
+#define F_DPTX_PHY_DATA_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 8)
+#define F_DPTX_PHY_DATA_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8)
+#define F_DPTX_PHY_DATA_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 9)
+#define F_DPTX_PHY_DATA_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9)
+#define F_DPTX_FRMR_DATA_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 10)
+#define F_DPTX_FRMR_DATA_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 10)) >> 10)
+#define F_DPTX_FRMR_DATA_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 11)
+#define F_DPTX_FRMR_DATA_CLK_RSTN_EN_RD(x) \
+	(((x) & (((1 << 1) - 1) << 11)) >> 11)
+
+/* register SOURCE_PHY_CAR */
+#define SOURCE_PHY_CAR 2
+#define F_SOURCE_PHY_DATA_OUT_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_SOURCE_PHY_DATA_OUT_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_SOURCE_PHY_DATA_OUT_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_SOURCE_PHY_DATA_OUT_CLK_RSTN_EN_RD(x) \
+	(((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_SOURCE_PHY_CHAR_OUT_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_SOURCE_PHY_CHAR_OUT_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_SOURCE_PHY_CHAR_OUT_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_SOURCE_PHY_CHAR_OUT_CLK_RSTN_EN_RD(x) \
+	(((x) & (((1 << 1) - 1) << 3)) >> 3)
+
+/* register SOURCE_CEC_CAR */
+#define SOURCE_CEC_CAR 3
+#define F_SOURCE_CEC_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_SOURCE_CEC_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_SOURCE_CEC_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_SOURCE_CEC_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+
+/* register SOURCE_CBUS_CAR */
+#define SOURCE_CBUS_CAR 4
+#define F_SOURCE_CBUS_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_SOURCE_CBUS_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_SOURCE_CBUS_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_SOURCE_CBUS_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+
+/* register SOURCE_PKT_CAR */
+#define SOURCE_PKT_CAR 6
+#define F_SOURCE_PKT_DATA_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_SOURCE_PKT_DATA_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_SOURCE_PKT_DATA_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_SOURCE_PKT_DATA_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_SOURCE_PKT_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_SOURCE_PKT_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_SOURCE_PKT_SYS_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_SOURCE_PKT_SYS_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+
+/* register SOURCE_AIF_CAR */
+#define SOURCE_AIF_CAR 7
+#define F_SOURCE_AIF_PKT_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_SOURCE_AIF_PKT_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_SOURCE_AIF_PKT_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_SOURCE_AIF_PKT_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_SOURCE_AIF_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_SOURCE_AIF_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_SOURCE_AIF_SYS_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_SOURCE_AIF_SYS_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+#define F_SPDIF_CDR_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_SPDIF_CDR_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
+#define F_SPDIF_CDR_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 5)
+#define F_SPDIF_CDR_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5)
+#define F_SPDIF_MCLK_EN(x) (((x) & ((1 << 1) - 1)) << 6)
+#define F_SPDIF_MCLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6)
+#define F_SPDIF_MCLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 7)
+#define F_SPDIF_MCLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7)
+
+/* register SOURCE_CIPHER_CAR */
+#define SOURCE_CIPHER_CAR 8
+#define F_SOURCE_CIPHER_CHAR_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_SOURCE_CIPHER_CHAR_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_SOURCE_CIPHER_CHAR_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_SOURCE_CIPHER_CHAR_CLK_RSTN_EN_RD(x) \
+	(((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_SOURCE_CIPHER_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_SOURCE_CIPHER_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN_RD(x) \
+	(((x) & (((1 << 1) - 1) << 3)) >> 3)
+
+/* register SOURCE_CRYPTO_CAR */
+#define SOURCE_CRYPTO_CAR 9
+#define F_SOURCE_CRYPTO_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_SOURCE_CRYPTO_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_SOURCE_CRYPTO_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_SOURCE_CRYPTO_SYS_CLK_RSTN_EN_RD(x) \
+	(((x) & (((1 << 1) - 1) << 1)) >> 1)
+
+#endif				/*SOURCE_CAR */
diff --git a/drivers/video/nxp/hdp/source_phy.h b/drivers/video/nxp/hdp/source_phy.h
new file mode 100644
index 00000000000..540809db971
--- /dev/null
+++ b/drivers/video/nxp/hdp/source_phy.h
@@ -0,0 +1,181 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * source_phy.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef SOURCE_PHY_H_
+#define SOURCE_PHY_H_
+
+/* register SHIFT_PATTERN_IN_3_0 */
+#define SHIFT_PATTERN_IN_3_0 0
+#define F_SOURCE_PHY_SHIFT_PATTERN0(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_SOURCE_PHY_SHIFT_PATTERN0_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+#define F_SOURCE_PHY_SHIFT_PATTERN1(x) (((x) & ((1 << 8) - 1)) << 8)
+#define F_SOURCE_PHY_SHIFT_PATTERN1_RD(x) (((x) & (((1 << 8) - 1) << 8)) >> 8)
+#define F_SOURCE_PHY_SHIFT_PATTERN2(x) (((x) & ((1 << 8) - 1)) << 16)
+#define F_SOURCE_PHY_SHIFT_PATTERN2_RD(x) (((x) & (((1 << 8) - 1) << 16)) >> 16)
+#define F_SOURCE_PHY_SHIFT_PATTERN3(x) (((x) & ((1 << 8) - 1)) << 24)
+#define F_SOURCE_PHY_SHIFT_PATTERN3_RD(x) (((x) & (((1 << 8) - 1) << 24)) >> 24)
+
+/* register SHIFT_PATTERN_IN_4_7 */
+#define SHIFT_PATTERN_IN_4_7 1
+#define F_SOURCE_PHY_SHIFT_PATTERN4(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_SOURCE_PHY_SHIFT_PATTERN4_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+#define F_SOURCE_PHY_SHIFT_PATTERN5(x) (((x) & ((1 << 8) - 1)) << 8)
+#define F_SOURCE_PHY_SHIFT_PATTERN5_RD(x) (((x) & (((1 << 8) - 1) << 8)) >> 8)
+#define F_SOURCE_PHY_SHIFT_PATTERN6(x) (((x) & ((1 << 8) - 1)) << 16)
+#define F_SOURCE_PHY_SHIFT_PATTERN6_RD(x) (((x) & (((1 << 8) - 1) << 16)) >> 16)
+#define F_SOURCE_PHY_SHIFT_PATTERN7(x) (((x) & ((1 << 8) - 1)) << 24)
+#define F_SOURCE_PHY_SHIFT_PATTERN7_RD(x) (((x) & (((1 << 8) - 1) << 24)) >> 24)
+
+/* register SHIFT_PATTERN_IN9_8 */
+#define SHIFT_PATTERN_IN9_8 2
+#define F_SOURCE_PHY_SHIFT_PATTERN8(x) (((x) & ((1 << 8) - 1)) << 0)
+#define F_SOURCE_PHY_SHIFT_PATTERN8_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0)
+#define F_SOURCE_PHY_SHIFT_PATTERN9(x) (((x) & ((1 << 8) - 1)) << 8)
+#define F_SOURCE_PHY_SHIFT_PATTERN9_RD(x) (((x) & (((1 << 8) - 1) << 8)) >> 8)
+#define F_SOURCE_PHY_SHIFT_LOAD(x) (((x) & ((1 << 1) - 1)) << 16)
+#define F_SOURCE_PHY_SHIFT_LOAD_RD(x) (((x) & (((1 << 1) - 1) << 16)) >> 16)
+#define F_SOURCE_PHY_SHIFT_EN(x) (((x) & ((1 << 1) - 1)) << 17)
+#define F_SOURCE_PHY_SHIFT_EN_RD(x) (((x) & (((1 << 1) - 1) << 17)) >> 17)
+#define F_SOURCE_PHY_SHIFT_REPETITION(x) (((x) & ((1 << 3) - 1)) << 18)
+#define F_SOURCE_PHY_SHIFT_REPETITION_RD(x) \
+	(((x) & (((1 << 3) - 1) << 18)) >> 18)
+
+/* register PRBS_CNTRL */
+#define PRBS_CNTRL 3
+#define F_SOURCE_PHY_PRBS0_MODE(x) (((x) & ((1 << 2) - 1)) << 0)
+#define F_SOURCE_PHY_PRBS0_MODE_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
+#define F_SOURCE_PHY_PRBS0_OUT_MODE(x) (((x) & ((1 << 2) - 1)) << 2)
+#define F_SOURCE_PHY_PRBS0_OUT_MODE_RD(x) (((x) & (((1 << 2) - 1) << 2)) >> 2)
+#define F_SOURCE_PHY_PRBS1_MODE(x) (((x) & ((1 << 2) - 1)) << 4)
+#define F_SOURCE_PHY_PRBS1_MODE_RD(x) (((x) & (((1 << 2) - 1) << 4)) >> 4)
+#define F_SOURCE_PHY_PRBS1_OUT_MODE(x) (((x) & ((1 << 2) - 1)) << 6)
+#define F_SOURCE_PHY_PRBS1_OUT_MODE_RD(x) (((x) & (((1 << 2) - 1) << 6)) >> 6)
+#define F_SOURCE_PHY_PRBS2_MODE(x) (((x) & ((1 << 2) - 1)) << 8)
+#define F_SOURCE_PHY_PRBS2_MODE_RD(x) (((x) & (((1 << 2) - 1) << 8)) >> 8)
+#define F_SOURCE_PHY_PRBS2_OUT_MODE(x) (((x) & ((1 << 2) - 1)) << 10)
+#define F_SOURCE_PHY_PRBS2_OUT_MODE_RD(x) (((x) & (((1 << 2) - 1) << 10)) >> 10)
+#define F_SOURCE_PHY_PRBS3_MODE(x) (((x) & ((1 << 2) - 1)) << 12)
+#define F_SOURCE_PHY_PRBS3_MODE_RD(x) (((x) & (((1 << 2) - 1) << 12)) >> 12)
+#define F_SOURCE_PHY_PRBS3_OUT_MODE(x) (((x) & ((1 << 2) - 1)) << 14)
+#define F_SOURCE_PHY_PRBS3_OUT_MODE_RD(x) (((x) & (((1 << 2) - 1) << 14)) >> 14)
+
+/* register PRBS_ERR_INSERTION */
+#define PRBS_ERR_INSERTION 4
+#define F_ADD_ERROR0(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_ADD_ERROR0_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_NUMBER_OF_ERRORS0(x) (((x) & ((1 << 5) - 1)) << 1)
+#define F_NUMBER_OF_ERRORS0_RD(x) (((x) & (((1 << 5) - 1) << 1)) >> 1)
+#define F_ADD_ERROR1(x) (((x) & ((1 << 1) - 1)) << 6)
+#define F_ADD_ERROR1_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6)
+#define F_NUMBER_OF_ERRORS1(x) (((x) & ((1 << 5) - 1)) << 7)
+#define F_NUMBER_OF_ERRORS1_RD(x) (((x) & (((1 << 5) - 1) << 7)) >> 7)
+#define F_ADD_ERROR2(x) (((x) & ((1 << 1) - 1)) << 12)
+#define F_ADD_ERROR2_RD(x) (((x) & (((1 << 1) - 1) << 12)) >> 12)
+#define F_NUMBER_OF_ERRORS2(x) (((x) & ((1 << 5) - 1)) << 13)
+#define F_NUMBER_OF_ERRORS2_RD(x) (((x) & (((1 << 5) - 1) << 13)) >> 13)
+#define F_ADD_ERROR3(x) (((x) & ((1 << 1) - 1)) << 18)
+#define F_ADD_ERROR3_RD(x) (((x) & (((1 << 1) - 1) << 18)) >> 18)
+#define F_NUMBER_OF_ERRORS3(x) (((x) & ((1 << 5) - 1)) << 19)
+#define F_NUMBER_OF_ERRORS3_RD(x) (((x) & (((1 << 5) - 1) << 19)) >> 19)
+
+/* register LANES_CONFIG */
+#define LANES_CONFIG 5
+#define F_SOURCE_PHY_LANE0_SWAP(x) (((x) & ((1 << 2) - 1)) << 0)
+#define F_SOURCE_PHY_LANE0_SWAP_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0)
+#define F_SOURCE_PHY_LANE1_SWAP(x) (((x) & ((1 << 2) - 1)) << 2)
+#define F_SOURCE_PHY_LANE1_SWAP_RD(x) (((x) & (((1 << 2) - 1) << 2)) >> 2)
+#define F_SOURCE_PHY_LANE2_SWAP(x) (((x) & ((1 << 2) - 1)) << 4)
+#define F_SOURCE_PHY_LANE2_SWAP_RD(x) (((x) & (((1 << 2) - 1) << 4)) >> 4)
+#define F_SOURCE_PHY_LANE3_SWAP(x) (((x) & ((1 << 2) - 1)) << 6)
+#define F_SOURCE_PHY_LANE3_SWAP_RD(x) (((x) & (((1 << 2) - 1) << 6)) >> 6)
+#define F_SOURCE_PHY_LANE0_LSB_MSB(x) (((x) & ((1 << 1) - 1)) << 8)
+#define F_SOURCE_PHY_LANE0_LSB_MSB_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8)
+#define F_SOURCE_PHY_LANE1_LSB_MSB(x) (((x) & ((1 << 1) - 1)) << 9)
+#define F_SOURCE_PHY_LANE1_LSB_MSB_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9)
+#define F_SOURCE_PHY_LANE2_LSB_MSB(x) (((x) & ((1 << 1) - 1)) << 10)
+#define F_SOURCE_PHY_LANE2_LSB_MSB_RD(x) (((x) & (((1 << 1) - 1) << 10)) >> 10)
+#define F_SOURCE_PHY_LANE3_LSB_MSB(x) (((x) & ((1 << 1) - 1)) << 11)
+#define F_SOURCE_PHY_LANE3_LSB_MSB_RD(x) (((x) & (((1 << 1) - 1) << 11)) >> 11)
+#define F_SOURCE_PHY_AUX_SPARE(x) (((x) & ((1 << 4) - 1)) << 12)
+#define F_SOURCE_PHY_AUX_SPARE_RD(x) (((x) & (((1 << 4) - 1) << 12)) >> 12)
+#define F_SOURCE_PHY_LANE0_POLARITY(x) (((x) & ((1 << 1) - 1)) << 16)
+#define F_SOURCE_PHY_LANE0_POLARITY_RD(x) (((x) & (((1 << 1) - 1) << 16)) >> 16)
+#define F_SOURCE_PHY_LANE1_POLARITY(x) (((x) & ((1 << 1) - 1)) << 17)
+#define F_SOURCE_PHY_LANE1_POLARITY_RD(x) (((x) & (((1 << 1) - 1) << 17)) >> 17)
+#define F_SOURCE_PHY_LANE2_POLARITY(x) (((x) & ((1 << 1) - 1)) << 18)
+#define F_SOURCE_PHY_LANE2_POLARITY_RD(x) (((x) & (((1 << 1) - 1) << 18)) >> 18)
+#define F_SOURCE_PHY_LANE3_POLARITY(x) (((x) & ((1 << 1) - 1)) << 19)
+#define F_SOURCE_PHY_LANE3_POLARITY_RD(x) (((x) & (((1 << 1) - 1) << 19)) >> 19)
+#define F_SOURCE_PHY_DATA_DEL_EN(x) (((x) & ((1 << 1) - 1)) << 20)
+#define F_SOURCE_PHY_DATA_DEL_EN_RD(x) (((x) & (((1 << 1) - 1) << 20)) >> 20)
+#define F_SOURCE_PHY_COMB_BYPASS(x) (((x) & ((1 << 1) - 1)) << 21)
+#define F_SOURCE_PHY_COMB_BYPASS_RD(x) (((x) & (((1 << 1) - 1) << 21)) >> 21)
+#define F_SOURCE_PHY_20_10(x) (((x) & ((1 << 1) - 1)) << 22)
+#define F_SOURCE_PHY_20_10_RD(x) (((x) & (((1 << 1) - 1) << 22)) >> 22)
+
+/* register PHY_DATA_SEL */
+#define PHY_DATA_SEL 6
+#define F_SOURCE_PHY_DATA_SEL(x) (((x) & ((1 << 3) - 1)) << 0)
+#define F_SOURCE_PHY_DATA_SEL_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0)
+#define F_SOURCE_PHY_MHDP_SEL(x) (((x) & ((1 << 2) - 1)) << 3)
+#define F_SOURCE_PHY_MHDP_SEL_RD(x) (((x) & (((1 << 2) - 1) << 3)) >> 3)
+
+/* register LANES_DEL_VAL */
+#define LANES_DEL_VAL 7
+#define F_SOURCE_PHY_LANE0_DEL_VAL(x) (((x) & ((1 << 4) - 1)) << 0)
+#define F_SOURCE_PHY_LANE0_DEL_VAL_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+#define F_SOURCE_PHY_LANE1_DEL_VAL(x) (((x) & ((1 << 4) - 1)) << 4)
+#define F_SOURCE_PHY_LANE1_DEL_VAL_RD(x) (((x) & (((1 << 4) - 1) << 4)) >> 4)
+#define F_SOURCE_PHY_LANE2_DEL_VAL(x) (((x) & ((1 << 4) - 1)) << 8)
+#define F_SOURCE_PHY_LANE2_DEL_VAL_RD(x) (((x) & (((1 << 4) - 1) << 8)) >> 8)
+#define F_SOURCE_PHY_LANE3_DEL_VAL(x) (((x) & ((1 << 4) - 1)) << 12)
+#define F_SOURCE_PHY_LANE3_DEL_VAL_RD(x) (((x) & (((1 << 4) - 1) << 12)) >> 12)
+
+#endif				/*SOURCE_PHY */
diff --git a/drivers/video/nxp/hdp/source_pif.h b/drivers/video/nxp/hdp/source_pif.h
new file mode 100644
index 00000000000..b9cbe16659d
--- /dev/null
+++ b/drivers/video/nxp/hdp/source_pif.h
@@ -0,0 +1,174 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * source_pif.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef SOURCE_PIF_H_
+#define SOURCE_PIF_H_
+
+/* register SOURCE_PIF_WR_ADDR */
+#define SOURCE_PIF_WR_ADDR 0
+#define F_WR_ADDR(x) (((x) & ((1 << 4) - 1)) << 0)
+#define F_WR_ADDR_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+
+/* register SOURCE_PIF_WR_REQ */
+#define SOURCE_PIF_WR_REQ 1
+#define F_HOST_WR(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_HOST_WR_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+
+/* register SOURCE_PIF_RD_ADDR */
+#define SOURCE_PIF_RD_ADDR 2
+#define F_RD_ADDR(x) (((x) & ((1 << 4) - 1)) << 0)
+#define F_RD_ADDR_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+
+/* register SOURCE_PIF_RD_REQ */
+#define SOURCE_PIF_RD_REQ 3
+#define F_HOST_RD(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_HOST_RD_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+
+/* register SOURCE_PIF_DATA_WR */
+#define SOURCE_PIF_DATA_WR 4
+/*# define F_DATA_WR(x) (((x) & ((1 << 32) - 1)) << 0) */
+/*# define F_DATA_WR_RD(x) (((x) & (((1 << 32) - 1) << 0)) >> 0) */
+#define F_DATA_WR(x) (((x) & 0xffffffff) << 0)
+#define F_DATA_WR_RD(x) (((x) & 0xffffffff) >> 0)
+
+/* register SOURCE_PIF_DATA_RD */
+#define SOURCE_PIF_DATA_RD 5
+#define F_FIFO2_DATA_OUT(x) (((x) & ((1 << 32) - 1)) << 0)
+#define F_FIFO2_DATA_OUT_RD(x) (((x) & (((1 << 32) - 1) << 0)) >> 0)
+
+/* register SOURCE_PIF_FIFO1_FLUSH */
+#define SOURCE_PIF_FIFO1_FLUSH 6
+#define F_FIFO1_FLUSH(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_FIFO1_FLUSH_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+
+/* register SOURCE_PIF_FIFO2_FLUSH */
+#define SOURCE_PIF_FIFO2_FLUSH 7
+#define F_FIFO2_FLUSH(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_FIFO2_FLUSH_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+
+/* register SOURCE_PIF_STATUS */
+#define SOURCE_PIF_STATUS 8
+#define F_SOURCE_PKT_MEM_CTRL_FSM_STATE(x) (((x) & ((1 << 2) - 1)) << 0)
+#define F_SOURCE_PKT_MEM_CTRL_FSM_STATE_RD(x) \
+	(((x) & (((1 << 2) - 1) << 0)) >> 0)
+#define F_FIFO1_FULL(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_FIFO1_FULL_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_FIFO2_EMPTY(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_FIFO2_EMPTY_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+
+/* register SOURCE_PIF_INTERRUPT_SOURCE */
+#define SOURCE_PIF_INTERRUPT_SOURCE 9
+#define F_HOST_WR_DONE_INT(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_HOST_WR_DONE_INT_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_HOST_RD_DONE_INT(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_HOST_RD_DONE_INT_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_NONVALID_TYPE_REQUESTED_INT(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_NONVALID_TYPE_REQUESTED_INT_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_PSLVERR(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_PSLVERR_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+#define F_ALLOC_WR_DONE(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_ALLOC_WR_DONE_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
+#define F_ALLOC_WR_ERROR(x) (((x) & ((1 << 1) - 1)) << 5)
+#define F_ALLOC_WR_ERROR_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5)
+#define F_FIFO1_OVERFLOW(x) (((x) & ((1 << 1) - 1)) << 6)
+#define F_FIFO1_OVERFLOW_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6)
+#define F_FIFO1_UNDERFLOW(x) (((x) & ((1 << 1) - 1)) << 7)
+#define F_FIFO1_UNDERFLOW_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7)
+#define F_FIFO2_OVERFLOW(x) (((x) & ((1 << 1) - 1)) << 8)
+#define F_FIFO2_OVERFLOW_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8)
+#define F_FIFO2_UNDERFLOW(x) (((x) & ((1 << 1) - 1)) << 9)
+#define F_FIFO2_UNDERFLOW_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9)
+
+/* register SOURCE_PIF_INTERRUPT_MASK */
+#define SOURCE_PIF_INTERRUPT_MASK 10
+#define F_HOST_WR_DONE_INT_MASK(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_HOST_WR_DONE_INT_MASK_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_HOST_RD_DONE_INT_MASK(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_HOST_RD_DONE_INT_MASK_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_NONVALID_TYPE_REQUESTED_INT_MASK(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_NONVALID_TYPE_REQUESTED_INT_MASK_RD(x) \
+	(((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_PSLVERR_MASK(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_PSLVERR_MASK_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+#define F_ALLOC_WR_DONE_MASK(x) (((x) & ((1 << 1) - 1)) << 4)
+#define F_ALLOC_WR_DONE_MASK_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4)
+#define F_ALLOC_WR_ERROR_MASK(x) (((x) & ((1 << 1) - 1)) << 5)
+#define F_ALLOC_WR_ERROR_MASK_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5)
+#define F_FIFO1_OVERFLOW_MASK(x) (((x) & ((1 << 1) - 1)) << 6)
+#define F_FIFO1_OVERFLOW_MASK_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6)
+#define F_FIFO1_UNDERFLOW_MASK(x) (((x) & ((1 << 1) - 1)) << 7)
+#define F_FIFO1_UNDERFLOW_MASK_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7)
+#define F_FIFO2_OVERFLOW_MASK(x) (((x) & ((1 << 1) - 1)) << 8)
+#define F_FIFO2_OVERFLOW_MASK_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8)
+#define F_FIFO2_UNDERFLOW_MASK(x) (((x) & ((1 << 1) - 1)) << 9)
+#define F_FIFO2_UNDERFLOW_MASK_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9)
+
+/* register SOURCE_PIF_PKT_ALLOC_REG */
+#define SOURCE_PIF_PKT_ALLOC_REG 11
+#define F_PKT_ALLOC_ADDRESS(x) (((x) & ((1 << 4) - 1)) << 0)
+#define F_PKT_ALLOC_ADDRESS_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0)
+#define F_PACKET_TYPE(x) (((x) & ((1 << 8) - 1)) << 8)
+#define F_PACKET_TYPE_RD(x) (((x) & (((1 << 8) - 1) << 8)) >> 8)
+#define F_TYPE_VALID(x) (((x) & ((1 << 1) - 1)) << 16)
+#define F_TYPE_VALID_RD(x) (((x) & (((1 << 1) - 1) << 16)) >> 16)
+#define F_ACTIVE_IDLE_TYPE(x) (((x) & ((1 << 1) - 1)) << 17)
+#define F_ACTIVE_IDLE_TYPE_RD(x) (((x) & (((1 << 1) - 1) << 17)) >> 17)
+
+/* register SOURCE_PIF_PKT_ALLOC_WR_EN */
+#define SOURCE_PIF_PKT_ALLOC_WR_EN 12
+#define F_PKT_ALLOC_WR_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_PKT_ALLOC_WR_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+
+/* register SOURCE_PIF_SW_RESET */
+#define SOURCE_PIF_SW_RESET 13
+#define F_SW_RST(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+
+#endif				/*SOURCE_PIF */
diff --git a/drivers/video/nxp/hdp/source_vif.h b/drivers/video/nxp/hdp/source_vif.h
new file mode 100644
index 00000000000..a9b6c00154f
--- /dev/null
+++ b/drivers/video/nxp/hdp/source_vif.h
@@ -0,0 +1,93 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * source_vif.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef SOURCE_VIF_H_
+#define SOURCE_VIF_H_
+
+/* register BND_HSYNC2VSYNC */
+#define BND_HSYNC2VSYNC 0
+#define F_IP_DTCT_WIN(x) (((x) & ((1 << 12) - 1)) << 0)
+#define F_IP_DTCT_WIN_RD(x) (((x) & (((1 << 12) - 1) << 0)) >> 0)
+#define F_IP_DET_EN(x) (((x) & ((1 << 1) - 1)) << 12)
+#define F_IP_DET_EN_RD(x) (((x) & (((1 << 1) - 1) << 12)) >> 12)
+#define F_IP_VIF_BYPASS(x) (((x) & ((1 << 1) - 1)) << 13)
+#define F_IP_VIF_BYPASS_RD(x) (((x) & (((1 << 1) - 1) << 13)) >> 13)
+
+/* register HSYNC2VSYNC_F1_L1 */
+#define HSYNC2VSYNC_F1_L1 1
+#define F_IP_DTCT_HSYNC2VSYNC_F1(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_IP_DTCT_HSYNC2VSYNC_F1_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+
+/* register HSYNC2VSYNC_F2_L1 */
+#define HSYNC2VSYNC_F2_L1 2
+#define F_IP_DTCT_HSYNC2VSYNC_F2(x) (((x) & ((1 << 16) - 1)) << 0)
+#define F_IP_DTCT_HSYNC2VSYNC_F2_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0)
+
+/* register HSYNC2VSYNC_STATUS */
+#define HSYNC2VSYNC_STATUS 3
+#define F_IP_DTCT_ERR(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_IP_DTCT_ERR_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+#define F_IP_DCT_IP(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_IP_DCT_IP_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_IP_DTCT_VJITTER(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_IP_DTCT_VJITTER_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_IP_DTCT_HJITTER(x) (((x) & ((1 << 1) - 1)) << 3)
+#define F_IP_DTCT_HJITTER_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3)
+
+/* register HSYNC2VSYNC_POL_CTRL */
+#define HSYNC2VSYNC_POL_CTRL 4
+#define F_VPOL(x) (((x) & ((1 << 1) - 1)) << 2)
+#define F_VPOL_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2)
+#define F_HPOL(x) (((x) & ((1 << 1) - 1)) << 1)
+#define F_HPOL_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1)
+#define F_VIF_AUTO_MODE(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_VIF_AUTO_MODE_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0)
+
+#endif				/*SOURCE_VIF */
diff --git a/drivers/video/nxp/hdp/test_base_sw.c b/drivers/video/nxp/hdp/test_base_sw.c
new file mode 100644
index 00000000000..bd44712057f
--- /dev/null
+++ b/drivers/video/nxp/hdp/test_base_sw.c
@@ -0,0 +1,217 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ ******************************************************************************
+ *
+ * test_base_sw.c
+ *
+ ******************************************************************************
+ */
+
+#ifndef __UBOOT__
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+#else
+#include <common.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+#ifdef CONFIG_ARCH_IMX8M
+/* mscale */
+#define HDMI_BASE     0x32c00000
+#define HDMI_PHY_BASE 0x32c80000
+#define HDMI_SEC_BASE 0x32e40000
+#endif
+#ifdef CONFIG_ARCH_IMX8
+/* QM */
+#define HDMI_BASE 0x56268000
+#define HDMI_SEC_BASE 0x56269000
+#define HDMI_OFFSET_ADDR 0x56261008
+#define HDMI_SEC_OFFSET_ADDR 0x5626100c
+
+#define HDMI_RX_BASE 0x58268000
+#define HDMI_RX_SEC_BASE 0x58269000
+#define HDMI_RX_OFFSET_ADDR 0x58261004
+#define HDMI_RX_SEC_OFFSET_ADDR 0x58261008
+#endif
+
+#ifdef CONFIG_ARCH_LS1028A
+#define HDMI_BASE	0xf200000
+#endif
+#endif
+
+#ifdef CONFIG_ARCH_IMX8M
+int cdn_apb_read(unsigned int addr, unsigned int *value)
+{
+	unsigned int temp;
+	u64 tmp_addr = addr + HDMI_BASE;
+
+	temp = __raw_readl(tmp_addr);
+	*value = temp;
+	return 0;
+}
+
+int cdn_apb_write(unsigned int addr, unsigned int value)
+{
+	u64 tmp_addr = addr + HDMI_BASE;
+
+	__raw_writel(value, tmp_addr);
+	return 0;
+}
+
+int cdn_sapb_read(unsigned int addr, unsigned int *value)
+{
+	unsigned int temp;
+	u64 tmp_addr = addr + HDMI_SEC_BASE;
+
+	temp = __raw_readl(tmp_addr);
+	*value = temp;
+	return 0;
+}
+
+int cdn_sapb_write(unsigned int addr, unsigned int value)
+{
+	u64 tmp_addr = addr + HDMI_SEC_BASE;
+
+	__raw_writel(value, tmp_addr);
+	return 0;
+}
+
+void cdn_sleep(uint32_t ms)
+{
+	mdelay(ms);
+}
+
+void cdn_usleep(uint32_t us)
+{
+	udelay(us);
+}
+#endif
+#ifdef CONFIG_ARCH_IMX8
+int cdn_apb_read(unsigned int addr, unsigned int *value)
+{
+	unsigned int temp;
+	u64 tmp_addr = (addr & 0xfff) + HDMI_BASE;
+
+	__raw_writel(addr >> 12, HDMI_OFFSET_ADDR);
+
+	temp = __raw_readl(tmp_addr);
+	*value = temp;
+	return 0;
+}
+
+int cdn_apb_write(unsigned int addr, unsigned int value)
+{
+	u64 tmp_addr = (addr & 0xfff) + HDMI_BASE;
+
+	__raw_writel(addr >> 12, HDMI_OFFSET_ADDR);
+	__raw_writel(value, tmp_addr);
+
+	return 0;
+}
+
+int cdn_sapb_read(unsigned int addr, unsigned int *value)
+{
+	unsigned int temp;
+	u64 tmp_addr = (addr & 0xfff) + HDMI_SEC_BASE;
+
+	__raw_writel(addr >> 12, HDMI_SEC_OFFSET_ADDR);
+
+	temp = __raw_readl(tmp_addr);
+	*value = temp;
+	return 0;
+}
+
+int cdn_sapb_write(unsigned int addr, unsigned int value)
+{
+	u64 tmp_addr = (addr & 0xfff) + HDMI_SEC_BASE;
+
+	__raw_writel(addr >> 12, HDMI_SEC_OFFSET_ADDR);
+	__raw_writel(value, tmp_addr);
+
+	return 0;
+}
+
+int hdp_rx_apb_read(unsigned int addr, unsigned int *value)
+{
+	unsigned int temp;
+	u64 tmp_addr = (addr & 0xfff) + HDMI_RX_BASE;
+
+	__raw_writel(addr >> 12, HDMI_RX_OFFSET_ADDR);
+
+	temp = __raw_readl(tmp_addr);
+
+	*value = temp;
+	return 0;
+}
+
+int hdp_rx_apb_write(unsigned int addr, unsigned int value)
+{
+	u64 tmp_addr = (addr & 0xfff) + HDMI_RX_BASE;
+
+	__raw_writel(addr >> 12, HDMI_RX_OFFSET_ADDR);
+
+	__raw_writel(value, tmp_addr);
+
+	return 0;
+}
+
+int hdp_rx_sapb_read(unsigned int addr, unsigned int *value)
+{
+	unsigned int temp;
+	u64 tmp_addr = (addr & 0xfff) + HDMI_RX_SEC_BASE;
+
+	__raw_writel(addr >> 12, HDMI_RX_SEC_OFFSET_ADDR);
+
+	temp = __raw_readl(tmp_addr);
+	*value = temp;
+	return 0;
+}
+
+int hdp_rx_sapb_write(unsigned int addr, unsigned int value)
+{
+	u64 tmp_addr = (addr & 0xfff) + HDMI_RX_SEC_BASE;
+
+	__raw_writel(addr >> 12, HDMI_RX_SEC_OFFSET_ADDR);
+	__raw_writel(value, tmp_addr);
+
+	return 0;
+}
+
+void cdn_sleep(uint32_t ms)
+{
+	mdelay(ms);
+}
+
+void cdn_usleep(uint32_t us)
+{
+	udelay(us);
+}
+#endif
+
+#ifdef CONFIG_ARCH_LS1028A
+int cdn_apb_read(unsigned int addr, unsigned int *value)
+{
+	unsigned int temp;
+	u64 tmp_addr = addr + HDMI_BASE;
+
+	temp = __raw_readl(tmp_addr);
+	*value = temp;
+	return 0;
+}
+
+int cdn_apb_write(unsigned int addr, unsigned int value)
+{
+	u64 tmp_addr = addr + HDMI_BASE;
+
+	__raw_writel(value, tmp_addr);
+	return 0;
+}
+#endif
diff --git a/drivers/video/nxp/hdp/util.c b/drivers/video/nxp/hdp/util.c
new file mode 100644
index 00000000000..e74aaa509cc
--- /dev/null
+++ b/drivers/video/nxp/hdp/util.c
@@ -0,0 +1,329 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ ******************************************************************************
+ *
+ * util.c
+ *
+ ******************************************************************************
+ */
+
+#include "util.h"
+#include "API_General.h"
+#include "externs.h"
+#ifndef __UBOOT__
+#include <string.h>
+#endif
+#include "apb_cfg.h"
+#include "opcodes.h"
+#ifndef __UBOOT__
+#include <stdio.h>
+
+#endif
+state_struct state;
+
+int cdn_bus_read(unsigned int addr, unsigned int *value)
+{
+	return state.bus_type ?
+	    cdn_sapb_read(addr, value) : cdn_apb_read(addr, value);
+}
+
+int cdn_bus_write(unsigned int addr, unsigned int value)
+{
+	return state.bus_type ?
+	    cdn_sapb_write(addr, value) : cdn_apb_write(addr, value);
+}
+
+void internal_itobe(int val, volatile unsigned char *dest, int bytes)
+{
+	int i;
+	for (i = bytes - 1; i >= 0; --i) {
+		dest[i] = (unsigned char)val;
+		val >>= 8;
+	}
+}
+
+uint32_t internal_betoi(volatile uint8_t const *src, uint8_t bytes)
+{
+	uint32_t ret = 0;
+	int i;
+
+	if (bytes > sizeof(ret)) {
+		printf("Warning. Read request for payload larger then supported.\n");
+		bytes = sizeof(ret);
+	}
+
+	for (i = 0; i < bytes; ++i) {
+		ret <<= 8;
+		ret |= (unsigned int)src[i];
+	}
+
+	return ret;
+}
+
+unsigned int internal_mkmsg(volatile unsigned char *dest, int valno, ...)
+{
+	va_list vl;
+	unsigned int len = 0;
+	va_start(vl, valno);
+	len = internal_vmkmsg(dest, valno, vl);
+	va_end(vl);
+	return len;
+}
+
+unsigned int internal_vmkmsg(volatile unsigned char *dest, int valno,
+			     va_list vl)
+{
+	unsigned int len = 0;
+	int i;
+	for (i = 0; i < valno; ++i) {
+		int size = va_arg(vl, int);
+		if (size > 0) {
+			internal_itobe(va_arg(vl, int), dest, size);
+			dest += size;
+			len += size;
+		} else {
+			memcpy((void *)dest, va_arg(vl, void *), -size);
+			dest -= size;
+			len -= size;
+		}
+	}
+	return len;
+}
+
+void internal_tx_mkfullmsg(unsigned char module, unsigned char opcode,
+			   int valno, ...)
+{
+	va_list vl;
+	va_start(vl, valno);
+	internal_vtx_mkfullmsg(module, opcode, valno, vl);
+	va_end(vl);
+}
+
+void internal_vtx_mkfullmsg(unsigned char module, unsigned char opcode,
+			    int valno, va_list vl)
+{
+	unsigned int len =
+	    internal_vmkmsg(state.txbuffer + INTERNAL_CMD_HEAD_SIZE, valno, vl);
+	internal_mbox_tx_enable(module, opcode, len);
+	state.txenable = 1;
+	state.running = 1;
+}
+
+void internal_readmsg(int valno, ...)
+{
+	va_list vl;
+	va_start(vl, valno);
+	internal_vreadmsg(valno, vl);
+	va_end(vl);
+}
+
+void internal_vreadmsg(int valno, va_list vl)
+{
+	uint8_t *src = state.rxbuffer + INTERNAL_CMD_HEAD_SIZE;
+	size_t i;
+
+	for (i = 0; i < (size_t) valno; ++i) {
+		int size = va_arg(vl, int);
+		void *ptr = va_arg(vl, void *);
+
+		if (!ptr) {
+			src += size;
+		} else if (!size) {
+			*((unsigned char **)ptr) = src;
+		} else if (size > 0) {
+			switch ((size_t) size) {
+			case sizeof(uint8_t):
+				*((uint8_t *)ptr) = internal_betoi(src, size);
+				break;
+			case sizeof(uint16_t):
+				*((uint16_t *)ptr) = internal_betoi(src, size);
+				break;
+			case 3:	/* 3-byte value (e.g. DPCD address)
+				can be safely converted from BE.*/
+			case sizeof(uint32_t):
+				*((uint32_t *)ptr) = internal_betoi(src, size);
+				break;
+			default:
+				printf("Warning. Unsupported variable size.\n");
+				memcpy(ptr, src, size);
+			};
+
+			src += size;
+		} else {
+			memcpy(ptr, src, -size);
+			src -= size;
+		}
+	}
+}
+
+INTERNAL_MBOX_STATUS mailbox_write(unsigned char val)
+{
+	INTERNAL_MBOX_STATUS ret;
+	unsigned int full;
+	if (cdn_bus_read(MAILBOX_FULL_ADDR << 2, &full)) {
+		ret.tx_status = CDN_TX_APB_ERROR;
+		return ret;
+	}
+	if (full) {
+		ret.tx_status = CDN_TX_FULL;
+		return ret;
+	}
+	if (cdn_bus_write(MAILBOX0_WR_DATA << 2, val)) {
+		ret.tx_status = CDN_TX_APB_ERROR;
+		return ret;
+	}
+	ret.tx_status = CDN_TX_WRITE;
+	return ret;
+}
+
+INTERNAL_MBOX_STATUS mailbox_read(volatile unsigned char *val)
+{
+	INTERNAL_MBOX_STATUS ret;
+	unsigned int empty;
+	unsigned int rd;
+	if (cdn_bus_read(MAILBOX_EMPTY_ADDR << 2, &empty)) {
+		ret.rx_status = CDN_RX_APB_ERROR;
+		return ret;
+	}
+	if (empty) {
+		ret.rx_status = CDN_RX_EMPTY;
+		return ret;
+	}
+	if (cdn_bus_read(MAILBOX0_RD_DATA << 2, &rd)) {
+		ret.rx_status = CDN_RX_APB_ERROR;
+		return ret;
+	}
+	*val = (unsigned char)rd;
+	ret.rx_status = CDN_RX_READ;
+	return ret;
+}
+
+INTERNAL_MBOX_STATUS internal_mbox_tx_process(void)
+{
+	unsigned int txcount = 0;
+	unsigned int length =
+	    (unsigned int)state.txbuffer[2] << 8 | (unsigned int)state.
+	    txbuffer[3];
+	INTERNAL_MBOX_STATUS ret = {.txend = 0 };
+	ret.tx_status = CDN_TX_NOTHING;
+	INTERNAL_MBOX_STATUS tx_ret;
+	if (!state.txenable)
+		return ret;
+	while ((tx_ret.tx_status =
+		mailbox_write(state.txbuffer[state.txi]).tx_status) ==
+	       CDN_TX_WRITE) {
+		txcount++;
+		if (++state.txi >= length + 4) {
+			state.txenable = 0;
+			state.txi = 0;
+			ret.txend = 1;
+			break;
+		}
+	}
+	if (txcount && tx_ret.tx_status == CDN_TX_FULL)
+		ret.tx_status = CDN_TX_WRITE;
+	else
+		ret.tx_status = tx_ret.tx_status;
+	return ret;
+}
+
+INTERNAL_MBOX_STATUS internal_mbox_rx_process(void)
+{
+	unsigned int rxcount = 0;
+	INTERNAL_MBOX_STATUS ret = { 0, 0, 0, 0 };
+	INTERNAL_MBOX_STATUS rx_ret;
+	while ((rx_ret.rx_status =
+		mailbox_read(state.rxbuffer + state.rxi).rx_status) ==
+	       CDN_RX_READ) {
+		rxcount++;
+		if (++state.rxi >= 4 +
+		    ((unsigned int)state.rxbuffer[2] << 8 |
+		     (unsigned int)state.rxbuffer[3])) { /* end of message */
+			state.rxi = 0;
+			ret.rxend = 1;
+			state.rxenable = 0;
+			break;
+		}
+	}
+	ret.rx_status = rxcount ? CDN_RX_READ : CDN_RX_EMPTY;
+	return ret;
+}
+
+unsigned int internal_apb_available(void)
+{
+	return !(state.rxenable || state.txenable);
+}
+
+void internal_mbox_tx_enable(unsigned char module, unsigned char opcode,
+			     unsigned short length)
+{
+	state.txbuffer[0] = opcode;
+	state.txbuffer[1] = module;
+	state.txbuffer[2] = (unsigned char)(length >> 8);
+	state.txbuffer[3] = (unsigned char)length;
+	state.txenable = 1;
+}
+
+CDN_API_STATUS internal_test_rx_head(unsigned char module, unsigned char opcode)
+{
+	if (opcode != state.rxbuffer[0])
+		return CDN_BAD_OPCODE;
+	if (module != state.rxbuffer[1])
+		return CDN_BAD_MODULE;
+	return CDN_OK;
+}
+
+CDN_API_STATUS internal_test_rx_head_match(void)
+{
+	return internal_test_rx_head(state.txbuffer[1], state.txbuffer[0]);
+}
+
+void print_fw_ver(void)
+{
+	unsigned short ver, verlib;
+	cdn_api_general_getcurversion(&ver, &verlib);
+	printf("FIRMWARE VERSION: %d, LIB VERSION: %d\n", ver, verlib);
+}
+
+unsigned short internal_get_msg_len(void)
+{
+	return ((unsigned short)state.rxbuffer[2] << 8) | (unsigned short)state.
+	    rxbuffer[3];
+}
diff --git a/drivers/video/nxp/hdp/util.h b/drivers/video/nxp/hdp/util.h
new file mode 100644
index 00000000000..6ad0b489abb
--- /dev/null
+++ b/drivers/video/nxp/hdp/util.h
@@ -0,0 +1,256 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ ******************************************************************************
+ *
+ * util.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef UTIL_H_
+#define UTIL_H_
+
+#include "API_General.h"
+#ifndef __UBOOT__
+#include <stdarg.h>
+#include <stdint.h>
+#else
+#include <common.h>
+#endif
+/**
+ * \addtogroup UTILS
+ * \{
+ */
+#define INTERNAL_CMD_HEAD_SIZE 4
+
+/**
+ * \brief expands to blocking function body
+ * \param x - function call
+ */
+#define internal_block_function(x)		\
+do {						\
+	CDN_API_STATUS ret;			\
+	do {					\
+		ret = x;			\
+	} while (ret == CDN_BSY || ret == CDN_STARTED); \
+	return ret;				\
+} while (0)
+
+/**
+ * \brief write message and write response (if any), non-blocking way.
+ * Also sets state.running = 0
+ */
+#define INTERNAL_PROCESS_MESSAGES				\
+do {								\
+	if (state.txenable && !internal_mbox_tx_process().txend)	\
+		return CDN_BSY;					\
+	if (state.rxenable && !internal_mbox_rx_process().rxend)	\
+		return CDN_BSY;					\
+	state.running = 0;					\
+} while (0)
+
+#define internal_opcode_ok_or_return(module, opcode)			\
+do {									\
+	CDN_API_STATUS ret = internal_test_rx_head(module, opcode);	\
+	if (ret != CDN_OK)						\
+		return ret;						\
+} while (0)
+
+#define internal_opcode_match_or_return()			\
+do {								\
+	CDN_API_STATUS ret = internal_test_rx_head_match();	\
+	if (ret != CDN_OK)	\
+		return ret;					\
+} while (0)
+
+/*
+ * macro for simple tx only command, command format as in mkfullmsg
+ * (with count)
+ */
+#define internal_macro_command_tx(module, opcode, bustype, command...)	\
+do {									\
+	if (!state.running) {						\
+		internal_tx_mkfullmsg(module, opcode, command);		\
+		state.bus_type = bustype;				\
+		return CDN_STARTED;					\
+	}								\
+	INTERNAL_PROCESS_MESSAGES;					\
+} while (0)
+
+/*
+ * macro for command with response with matching opcode, command format as in
+ * mkfullmsg (with count)
+ */
+#define internal_macro_command_txrx(module, opcode, bustype, command...) \
+do {									\
+	if (!state.running) {						\
+		internal_tx_mkfullmsg(module, opcode, command);		\
+		state.bus_type = bustype;				\
+		state.rxenable = 1;					\
+		return CDN_STARTED;					\
+	}								\
+	INTERNAL_PROCESS_MESSAGES;					\
+	internal_opcode_match_or_return();				\
+} while (0)
+
+typedef struct {
+	/** apb write status */
+	enum tx_status_enum {
+	/** one or more bytes written */
+		CDN_TX_WRITE = 0,
+	/** nothing to write */
+		CDN_TX_NOTHING = 1,
+	/** mailbox full, 0 bytes written */
+		CDN_TX_FULL = 2,
+	/** APB error while writing */
+		CDN_TX_APB_ERROR = 3
+	} tx_status:3;
+	/** apb read status */
+	enum rx_status_enum {
+	/** 1 or more bytes read */
+		CDN_RX_READ = 0,
+	/** mailbox empty, 0 bytes read */
+		CDN_RX_EMPTY = 1,
+	/** apb error while reading */
+		CDN_RX_APB_ERROR = 2
+	} rx_status:2;
+	/** indicates end of currenly recived message */
+	unsigned char rxend:1;
+	/** end of tx message reached */
+	unsigned char txend:1;
+} INTERNAL_MBOX_STATUS;
+
+/**
+ * \brief put val into dest in big endian format
+ * \param val - value to put
+ * \param dest - place to put value
+ * \param bytes - true size of val in bytes. for example if
+ *        bytes = 2 val is treated as short int
+ */
+void internal_itobe(int val, volatile unsigned char *dest, int bytes);
+
+/**
+ * \brief read big endian value from src and return it
+ * \param src - source to read from
+ * \param bytes - size of read value
+ * \return result
+ */
+u32 internal_betoi(volatile u8 const *src, u8 bytes);
+
+/**
+ * \brief create message from size and value pairs; also sets
+ *        state.running and state.txEnable
+ * \param dest - pointer to write message to
+ * \param valNo - number of values to write
+ * \param ... - pairs of size and value, each value is written
+ *        after another. if size is positive value, value is
+ *        written with #internal_itobe, if size is negative,
+ *        value is treated as src pointer for memcpy
+ *
+ * example:
+ *
+ *  unsigned short x = 0xAABB;
+ *
+ *  internal_mkmsg(dest, 3, 1, 1, 2, 3, -2, &x);
+ *
+ *  will write 01 00 03 AA BB to dest
+ */
+unsigned int internal_mkmsg(volatile unsigned char *dest, int valno, ...);
+unsigned int internal_vmkmsg(volatile unsigned char *dest, int valno,
+			     va_list vl);
+
+/**
+ * \brief setup message header in txBuffer, set txEnable = 1
+ */
+void internal_mbox_tx_enable(unsigned char module, unsigned char opcode,
+			     unsigned short length);
+
+/**
+ * \brief write from txBuffer to mailbox until full or end of message.
+ *
+ * when txEnable == 0 writes nothing
+ * when write reaches end of message set txEnable = 0
+ */
+
+/**
+ * \brief combination of #internal_mkmsg and #internal_mbox_tx_enable
+ *
+ * #internal_mkmsg dest and #internal_mbox_tx_enable length are determined
+ * automatically this function also sets state.txEnable = 1 and
+ * state.running
+ */
+void internal_tx_mkfullmsg(unsigned char module, unsigned char opcode,
+			   int valno, ...);
+void internal_vtx_mkfullmsg(unsigned char module, unsigned char opcode,
+			    int valno, va_list vl);
+
+/**
+ * \brief read from state.txBuffer and store results in specified pointers
+ * \param valNo - numbero of values to read
+ * \param ... - pairs of size and ptr
+ *
+ * this function is similar to #internal_mkmsg -
+ *
+ * when size is positive read value using #internal_betoi
+ * when size is negative mempcy from txBuffer to ptr -size bytes
+ * when size is 0 write to ptr address of current position in rxbuffer
+ * when ptr is NULL ignore size bytes (if size is negative this
+ * will rewind buffer)
+ */
+void internal_readmsg(int valno, ...);
+void internal_vreadmsg(int valno, va_list vl);
+
+INTERNAL_MBOX_STATUS internal_mbox_tx_process(void);
+/**
+ * \brief read to rxBuffer from mailbox until empty or end of message
+ *
+ * when rxEnable == 0 reads nothing
+ * when end of message reached sets rxEnable = 0
+ */
+INTERNAL_MBOX_STATUS internal_mbox_rx_process(void);
+
+/**
+ * \brief check if apb is available
+ * \return !(rxEnable && txEable)
+ */
+unsigned int internal_apb_available(void);
+
+/**
+ * \brief test if parameters match module and opcode in rxBuffer
+ * \return CDN_OK or CDN_BAD_OPCODE or CDN_BAD_MODULE
+ */
+CDN_API_STATUS internal_test_rx_head(unsigned char module,
+				     unsigned char opcode);
+
+CDN_API_STATUS internal_test_rx_head_match(void);
+
+/**
+ * \brief print current fw and lib version
+ */
+void print_fw_ver(void);
+
+typedef struct {
+	unsigned char txbuffer[1024];
+	unsigned char rxbuffer[1024];
+	unsigned int txi;	/* iterators */
+	unsigned int rxi;
+	unsigned char txenable;	/*data readt to send*/
+	unsigned char rxenable;
+	unsigned char running;
+	CDN_BUS_TYPE bus_type;
+	unsigned int tmp;
+} state_struct;
+
+extern state_struct state;
+extern int cdn_bus_read(unsigned int addr, unsigned int *value);
+extern int cdn_bus_write(unsigned int addr, unsigned int value);
+unsigned short internal_get_msg_len(void);
+
+#endif
diff --git a/drivers/video/nxp/hdp/vic_table.c b/drivers/video/nxp/hdp/vic_table.c
new file mode 100644
index 00000000000..c4984008189
--- /dev/null
+++ b/drivers/video/nxp/hdp/vic_table.c
@@ -0,0 +1,68 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * vic_table.c
+ *
+ ******************************************************************************
+ */
+#include "vic_table.h"
+
+const unsigned int vic_table[VIC_MODE_COUNT][27] = {
+	{858, 720, 138, 62, 16, 60, 525, 480, 45, 6, 9, 30, 59, 27000,
+	 PROGRESSIVE, ACTIVE_LOW, ACTIVE_LOW, 1, 65535, 1, 46, 65535, 65535, 3,
+	 8, 0},
+	{1650, 1280, 370, 40, 110, 220, 750, 720, 30, 5, 5, 20, 60, 74250,
+	 PROGRESSIVE, ACTIVE_HIGH, ACTIVE_HIGH, 1, 65535, 1, 31, 65535, 65535,
+	 4, 8, 0},
+	{2200, 1920, 280, 44, 88, 148, 1125, 1080, 45, 5, 4,
+	 36, 60, 148500, PROGRESSIVE, ACTIVE_HIGH,
+	 ACTIVE_HIGH, 1, 65535, 1, 46, 65535, 65535, 16, 8, 0},
+	{4400, 3840, 560, 88, 176, 296, 2250, 2160, 90, 10, 8, 72, 60,
+	 594000, PROGRESSIVE, ACTIVE_HIGH, ACTIVE_HIGH, 4, 266, 262, 22, 525,
+	 285, 97, 8, 0},
+	{4400, 3840, 560, 88, 176, 296, 2250, 2160, 90, 10, 8, 72, 30,
+	 297000, PROGRESSIVE, ACTIVE_HIGH, ACTIVE_HIGH, 4, 266, 262, 22, 525,
+	 285, 95, 8, 0},
+};
diff --git a/drivers/video/nxp/hdp/vic_table.h b/drivers/video/nxp/hdp/vic_table.h
new file mode 100644
index 00000000000..dce88347b7e
--- /dev/null
+++ b/drivers/video/nxp/hdp/vic_table.h
@@ -0,0 +1,140 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2016-2017 Cadence Design Systems, Inc.
+ * All rights reserved worldwide.
+ *
+ * Copyright 2017-2018 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS",
+ * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
+ * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ******************************************************************************
+ *
+ * This file was auto-generated. Do not edit it manually.
+ *
+ ******************************************************************************
+ *
+ * vic_table.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef VIC_TABLE_H_
+#define VIC_TABLE_H_
+
+#define PROGRESSIVE 0
+#define INTERLACED 1
+
+#define ACTIVE_LOW 0
+#define ACTIVE_HIGH 1
+
+typedef enum {
+	H_TOTAL,
+	H_ACTIVE,
+	H_BLANK,
+	HSYNC,
+	FRONT_PORCH,
+	BACK_PORCH,
+	/* H_FREQ_KHZ, */
+	V_TOTAL,
+	V_ACTIVE,
+	V_BLANK,
+	VSYNC,
+	TYPE_EOF,
+	SOF,
+	V_FREQ_HZ,
+	PIXEL_FREQ_KHZ,
+	I_P,
+	HSYNC_POL,
+	VSYNC_POL,
+	START_OF_F0,
+	START_OF_F1,
+	VSYNC_START_INTERLACED_F0,
+	VSYNC_END_INTERLACED_F0,
+	VSYNC_START_INTERLACED_F1,
+	VSYNC_END_INTERLACED_F1,
+	VIC,
+	VIC_R3_0,
+	VIC_PR,
+} MSA_PARAM;
+
+typedef enum {
+	NUM_OF_LANES_1 = 1,
+	NUM_OF_LANES_2 = 2,
+	NUM_OF_LANES_4 = 4,
+} VIC_NUM_OF_LANES;
+
+typedef enum {
+	RATE_1_6 = 162,
+	RATE_2_7 = 270,
+	RATE_5_4 = 540,
+	RATE_8_1 = 810,
+} VIC_SYMBOL_RATE;
+
+typedef enum {
+	PXL_RGB = 0x1,
+	YCBCR_4_4_4 = 0x2,
+	YCBCR_4_2_2 = 0x4,
+	YCBCR_4_2_0 = 0x8,
+	Y_ONLY = 0x10,
+} VIC_PXL_ENCODING_FORMAT;
+
+typedef enum {
+	BCS_6 = 0x1,
+	BCS_8 = 0x2,
+	BCS_10 = 0x4,
+	BCS_12 = 0x8,
+	BCS_16 = 0x10,
+} VIC_COLOR_DEPTH;
+
+typedef enum {
+	STEREO_VIDEO_LEFT = 0x0,
+	STEREO_VIDEO_RIGHT = 0x1,
+} STEREO_VIDEO_ATTR;
+
+typedef enum {
+	BT_601 = 0x0,
+	BT_709 = 0x1,
+} BT_TYPE;
+
+typedef enum {
+	VIC_MODE_3_59_94Hz,
+	VIC_MODE_4_60Hz,
+	VIC_MODE_16_60Hz,
+	VIC_MODE_97_60Hz,
+	VIC_MODE_95_30Hz,
+	VIC_MODE_COUNT
+} VIC_MODES;
+
+extern const unsigned int vic_table[VIC_MODE_COUNT][27];
+
+#endif
diff --git a/drivers/video/nxp/imx/Kconfig b/drivers/video/nxp/imx/Kconfig
new file mode 100644
index 00000000000..49455fac49b
--- /dev/null
+++ b/drivers/video/nxp/imx/Kconfig
@@ -0,0 +1,125 @@
+
+config VIDEO_IPUV3
+	bool "i.MX IPUv3 Core video support"
+	depends on DM_VIDEO && (MX5 || MX6)
+	help
+	  This enables framebuffer driver for i.MX processors working
+	  on the IPUv3(Image Processing Unit) internal graphic processor.
+
+config VIDEO_IMXDPUV1
+	bool "i.MX DPU V1 display support"
+	default n
+	depends on IMX8 && DM_VIDEO
+	select VIDEO_LINK
+	help
+	  Support for IMXDPU V1 display controller for i.MX8 processors.
+
+config VIDEO_IMX6SX_LVDS
+	bool "i.MX6SX LDVS bridge support"
+	default n
+	depends on MX6SX && DM_VIDEO
+	select DISPLAY
+	select VIDEO_LINK
+	select REGMAP
+	select SYSCON
+	help
+	  Support for LDVS bridge controller on i.MX6SX processors.
+
+config VIDEO_IMX8_LVDS
+	bool "i.MX8 LDVS bridge support"
+	default n
+	depends on IMX8 && DM_VIDEO
+	select DISPLAY
+	select VIDEO_LINK
+	help
+	  Support for i.MX8 LDVS bridge controller for i.MX8 processors.
+
+config VIDEO_IMX_HDP_LOAD
+	bool "i.MX8 HDMI/DP firmware loading"
+	default n
+	depends on IMX8QM
+	select VIDEO_NXP_HDP
+	help
+	  Support for HDMI/DP firmware loading for i.MX8QM processors. The
+	  firmware is copied from system memory to the HDMI/DP IRAM and
+	  DRAM memory.
+
+config VIDEO_IMX8M_DCSS
+	bool "i.MX8M DCSS controller"
+	default n
+	depends on IMX8M && DM_VIDEO
+	select VIDEO_LINK
+	help
+	  Support for DCSS on i.MX8MQ processors.
+
+config VIDEO_IMX8M_HDMI
+	bool "i.MX8M HDMI Splash screen"
+	default n
+	depends on IMX8M && DM_VIDEO
+	select DISPLAY
+	select VIDEO_LINK
+	select VIDEO_NXP_HDP
+	help
+	  Support for HDMI on i.MX8MQ processors.
+
+config VIDEO_SEC_MIPI_DSI
+	bool
+	select VIDEO_MIPI_DSI
+	help
+	  Enables the common driver code for the Samsung
+	  MIPI DSI block found in SoCs from various vendors.
+	  As this does not provide any functionality by itself (but
+	  rather requires a SoC-specific glue driver to call it), it
+	  can not be enabled from the configuration menu.
+
+config VIDEO_NW_MIPI_DSI
+	bool
+	select VIDEO_MIPI_DSI
+	help
+	  Enables the common driver code for the Northwest
+	  MIPI DSI block found in SoCs from various vendors.
+	  As this does not provide any functionality by itself (but
+	  rather requires a SoC-specific glue driver to call it), it
+	  can not be enabled from the configuration menu.
+
+config VIDEO_IMX_SEC_DSI
+	bool "Enable IMX SEC DSI video support"
+	select VIDEO_BRIDGE
+	select VIDEO_SEC_MIPI_DSI
+	select VIDEO_LINK
+	help
+	  This option enables support DSI internal bridge which can be used on
+	  devices which have DSI devices connected.
+
+config VIDEO_IMX_NW_DSI
+	bool "Enable IMX Northwest DSI video support"
+	select VIDEO_BRIDGE
+	select VIDEO_NW_MIPI_DSI
+	select VIDEO_LINK
+	help
+	  This option enables support DSI internal bridge which can be used on
+	  devices which have DSI devices connected.
+
+config VIDEO_IMX_DW_DSI
+	bool "Enable Synopsys DW DSI video support"
+	select VIDEO_BRIDGE
+	select VIDEO_DW_MIPI_DSI
+	select VIDEO_LINK
+	help
+	  This option enables support DSI internal bridge which can be used on
+	  devices which have DSI devices connected.
+
+config VIDEO_IMX_LCDIFV3
+	bool "i.MX LCDIFv3 support"
+	depends on DM_VIDEO && (IMX8MP || ARCH_IMX9)
+	select VIDEO_LINK
+	help
+	  Support for i.MX8MP LCDIFv3 controller.
+
+config VIDEO_IMX_DCNANO
+	bool "i.MX DCNANO LCDIF support"
+	depends on DM_VIDEO && IMX8ULP
+	select VIDEO_LINK
+	help
+	  Support for i.MX8ULP DCNANO LCD controller.
+
diff --git a/drivers/video/nxp/imx/Makefile b/drivers/video/nxp/imx/Makefile
new file mode 100644
index 00000000000..1d2035c63ab
--- /dev/null
+++ b/drivers/video/nxp/imx/Makefile
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
+obj-$(CONFIG_VIDEO_IMXDPUV1) += imxdpuv1.o imx8_dc.o
+obj-$(CONFIG_VIDEO_IMX6SX_LVDS) += imx6sx_ldb.o
+obj-$(CONFIG_VIDEO_IMX8_LVDS) += imx8_lvds.o
+obj-$(CONFIG_VIDEO_IMX8M_DCSS) += imx8m_dcss.o
+obj-$(CONFIG_VIDEO_SEC_MIPI_DSI) += sec_mipi_dsim.o
+obj-$(CONFIG_VIDEO_IMX_SEC_DSI) += sec_dsim_imx.o
+obj-$(CONFIG_VIDEO_IMX_LCDIFV3) += imx_lcdifv3.o
+obj-$(CONFIG_VIDEO_NW_MIPI_DSI) += mipi_dsi_northwest.o
+obj-$(CONFIG_VIDEO_IMX_NW_DSI) += nw_dsi_imx.o
+obj-$(CONFIG_VIDEO_IMX_DW_DSI) += dw_dsi_imx.o
+obj-$(CONFIG_VIDEO_IMX_DCNANO) += dcnano.o
+obj-y += hdmi/
diff --git a/drivers/video/nxp/imx/dcnano-reg.h b/drivers/video/nxp/imx/dcnano-reg.h
new file mode 100644
index 00000000000..35600c34872
--- /dev/null
+++ b/drivers/video/nxp/imx/dcnano-reg.h
@@ -0,0 +1,430 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020,2021 NXP
+ */
+
+#ifndef _DCNANO_REG_H_
+#define _DCNANO_REG_H_
+
+#include <linux/bitfield.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+/**
+ * FIELD_MAX() - produce the maximum value representable by a field
+ * @_mask: shifted mask defining the field's length and position
+ *
+ * FIELD_MAX() returns the maximum value that can be held in the field
+ * specified by @_mask.
+ */
+#define FIELD_MAX(_mask)						\
+	({								\
+		__BF_FIELD_CHECK(_mask, 0ULL, 0ULL, "FIELD_MAX: ");	\
+		(typeof(_mask))((_mask) >> __bf_shf(_mask));		\
+	})
+
+
+#define DCNANO_FRAMEBUFFERCONFIG	0x1240
+/* double buffered */
+#define  FBCFG_FORMAT_MASK		GENMASK(2, 0)
+#define  FBCFG_FORMAT_NONE		FIELD_PREP(FBCFG_FORMAT_MASK, 0)
+#define  FBCFG_FORMAT_R4G4B4		FIELD_PREP(FBCFG_FORMAT_MASK, 1)
+#define  FBCFG_FORMAT_R5G5B5		FIELD_PREP(FBCFG_FORMAT_MASK, 2)
+#define  FBCFG_FORMAT_R5G6B5		FIELD_PREP(FBCFG_FORMAT_MASK, 3)
+#define  FBCFG_FORMAT_R8G8B8		FIELD_PREP(FBCFG_FORMAT_MASK, 4)
+/* double buffered */
+#define  FBCFG_MODE_LINEAR		0
+#define  FBCFG_MODE_TILE4X4		BIT(4)
+/* double buffered */
+#define  FBCFG_OUTPUT_MASK		BIT(8)
+#define  FBCFG_OUTPUT_DISABLE		0
+#define  FBCFG_OUTPUT_ENABLE		BIT(8)
+/* double buffered */
+#define  FBCFG_SWITCHPANEL_DISABLE	0
+#define  FBCFG_SWITCHPANEL_ENABLE	BIT(9)
+/* double buffered */
+#define  FBCFG_GAMMA_DISABLE		0
+#define  FBCFG_GAMMA_ENABLE		BIT(12)
+#define  FBCFG_VALID_WORKING		0
+#define  FBCFG_VALID_PENDING		BIT(16)
+#define  FBCFG_RESET_MASK		BIT(20)
+#define  FBCFG_RESET_DISABLE		0
+#define  FBCFG_RESET_ENABLE		BIT(20)
+#define  FBCFG_UNDERFLOW_NO		0
+#define  FBCFG_UNDERFLOW_YES		BIT(24)
+#define  FBCFG_FLIP_INPROGRSS_NO	0
+#define  FBCFG_FLIP_INPROGRSS_YES	BIT(28)
+#define  FBCFG_BACK_PRES_DISABLE_NO	0
+#define  FBCFG_BACK_PRES_DISABLE_YES	BIT(29)
+
+/* double buffered */
+#define DCNANO_FRAMEBUFFERADDRESS	0x1260
+#define  FBADDRESS_MASK			GENMASK(31, 0)
+#define  FBADDRESS(x)			FIELD_PREP(FBADDRESS_MASK, (x))
+#define  FBADDRESS_TYPE_SYSTEM		0
+#define  FBADDRESS_TYPE_VIRTUAL		BIT(31)
+
+/* double buffered */
+#define DCNANO_FRAMEBUFFERSTRIDE	0x1280
+#define  FBSTRIDE_MASK			GENMASK(16, 0)
+#define  FBSTRIDE(x)			FIELD_PREP(FBSTRIDE_MASK, (x))
+#define  FBSTRIDE_MAX			FIELD_MAX(FBSTRIDE_MASK)
+
+#define DCNANO_DISPLAYDITHERCONFIG	0x1360
+#define  DITHERCFG_BLUESIZE_MASK	GENMASK(3, 0)
+#define  DITHERCFG_BLUESIZE(x)		FIELD_PREP(DITHERCFG_BLUESIZE_MASK, (x))
+#define  DITHERCFG_GREENSIZE_MASK	GENMASK(11, 8)
+#define  DITHERCFG_GREENSIZE(x)		FIELD_PREP(DITHERCFG_GREENSIZE_MASK, (x))
+#define  DITHERCFG_REDSIZE_MASK		GENMASK(19, 16)
+#define  DITHERCFG_REDSIZE(x)		FIELD_PREP(DITHERCFG_REDSIZE_MASK, (x))
+#define  DITHERCFG_DISABLE		0
+/* double buffered */
+#define  DITHERCFG_ENABLE		BIT(31)
+
+#define DCNANO_DISPLAYDITHERTABLELOW	0x1380
+#define  DITHERTLB_LOW_Y0X0_MASK	GENMASK(3, 0)
+#define  DITHERTLB_LOW_Y0X0(x)		FIELD_PREP(DITHERTLB_LOW_Y0X0_MASK, (x))
+#define  DITHERTLB_LOW_Y0X1_MASK	GENMASK(7, 4)
+#define  DITHERTLB_LOW_Y0X1(x)		FIELD_PREP(DITHERTLB_LOW_Y0X1_MASK, (x))
+#define  DITHERTLB_LOW_Y0X2_MASK	GENMASK(11, 8)
+#define  DITHERTLB_LOW_Y0X2(x)		FIELD_PREP(DITHERTLB_LOW_Y0X2_MASK, (x))
+#define  DITHERTLB_LOW_Y0X3_MASK	GENMASK(15, 12)
+#define  DITHERTLB_LOW_Y0X3(x)		FIELD_PREP(DITHERTLB_LOW_Y0X3_MASK, (x))
+#define  DITHERTLB_LOW_Y1X0_MASK	GENMASK(19, 16)
+#define  DITHERTLB_LOW_Y1X0(x)		FIELD_PREP(DITHERTLB_LOW_Y1X0_MASK, (x))
+#define  DITHERTLB_LOW_Y1X1_MASK	GENMASK(23, 20)
+#define  DITHERTLB_LOW_Y1X1(x)		FIELD_PREP(DITHERTLB_LOW_Y1X1_MASK, (x))
+#define  DITHERTLB_LOW_Y1X2_MASK	GENMASK(27, 24)
+#define  DITHERTLB_LOW_Y1X2(x)		FIELD_PREP(DITHERTLB_LOW_Y1X2_MASK, (x))
+#define  DITHERTLB_LOW_Y1X3_MASK	GENMASK(31, 28)
+#define  DITHERTLB_LOW_Y1X3(x)		FIELD_PREP(DITHERTLB_LOW_Y1X3_MASK, (x))
+
+#define DCNANO_DISPLAYDITHERTABLEHIGH	0x13a0
+#define  DITHERTLB_HIGH_Y2X0_MASK	GENMASK(3, 0)
+#define  DITHERTLB_HIGH_Y2X0(x)		FIELD_PREP(DITHERTLB_HIGH_Y2X0_MASK, (x))
+#define  DITHERTLB_HIGH_Y2X1_MASK	GENMASK(7, 4)
+#define  DITHERTLB_HIGH_Y2X1(x)		FIELD_PREP(DITHERTLB_HIGH_Y2X1_MASK, (x))
+#define  DITHERTLB_HIGH_Y2X2_MASK	GENMASK(11, 8)
+#define  DITHERTLB_HIGH_Y2X2(x)		FIELD_PREP(DITHERTLB_HIGH_Y2X2_MASK, (x))
+#define  DITHERTLB_HIGH_Y2X3_MASK	GENMASK(15, 12)
+#define  DITHERTLB_HIGH_Y2X3(x)		FIELD_PREP(DITHERTLB_HIGH_Y2X3_MASK, (x))
+#define  DITHERTLB_HIGH_Y3X0_MASK	GENMASK(19, 16)
+#define  DITHERTLB_HIGH_Y3X0(x)		FIELD_PREP(DITHERTLB_HIGH_Y3X0_MASK, (x))
+#define  DITHERTLB_HIGH_Y3X1_MASK	GENMASK(23, 20)
+#define  DITHERTLB_HIGH_Y3X1(x)		FIELD_PREP(DITHERTLB_HIGH_Y3X1_MASK, (x))
+#define  DITHERTLB_HIGH_Y3X2_MASK	GENMASK(27, 24)
+#define  DITHERTLB_HIGH_Y3X2(x)		FIELD_PREP(DITHERTLB_HIGH_Y3X2_MASK, (x))
+#define  DITHERTLB_HIGH_Y3X3_MASK	GENMASK(31, 28)
+#define  DITHERTLB_HIGH_Y3X3(x)		FIELD_PREP(DITHERTLB_HIGH_Y3X3_MASK, (x))
+
+#define DCNANO_PANELCONFIG		0x13c0
+#define  PANELCFG_DE_DISABLE		0
+#define  PANELCFG_DE_ENABLE		BIT(0)
+#define  PANELCFG_DE_POL_POSITIVE	0
+#define  PANELCFG_DE_POL_NEGATIVE	BIT(1)
+/* double buffered? */
+#define  PANELCFG_DATA_DISABLE		0
+#define  PANELCFG_DATA_ENABLE		BIT(4)
+#define  PANELCFG_DATA_POL_POSITIVE	0
+#define  PANELCFG_DATA_POL_NEGATIVE	BIT(5)
+#define  PANELCFG_CLOCK_DISABLE		0
+#define  PANELCFG_CLOCK_ENABLE		BIT(8)
+#define  PANELCFG_CLOCK_POL_POSITIVE	0
+#define  PANELCFG_CLOCK_POL_NEGATIVE	BIT(9)
+#define  PANELCFG_SEQUENCING_HARDWARE	0
+#define  PANELCFG_SEQUENCING_SOFTWARE	BIT(31)
+
+#define DCNANO_PANELTIMING		0x13e0
+#define  PANELTIMING_POWER_ENABLE_MASK		GENMASK(3, 0)
+#define  PANELTIMING_POWER_ENABLE(x)		\
+			FIELD_PREP(PANELTIMING_POWER_ENABLE_MASK, (x))
+#define  PANELTIMING_BACKLIGHT_ENABLE_MASK	GENMASK(7, 4)
+#define  PANELTIMING_BACKLIGHT_ENABLE(x)	\
+			FIELD_PREP(PANELTIMING_BACKLIGHT_ENABLE_MASK, (x))
+#define  PANELTIMING_CLOCK_ENABLE_MASK		GENMASK(11, 8)
+#define  PANELTIMING_CLOCK_ENABLE(x)		\
+			FIELD_PREP(PANELTIMING_CLOCK_ENABLE_MASK, (x))
+#define  PANELTIMING_DATA_ENABLE_MASK		GENMASK(15, 12)
+#define  PANELTIMING_DATA_ENABLE(x)		\
+			FIELD_PREP(PANELTIMING_DATA_ENABLE_MASK, (x))
+#define  PANELTIMING_DATA_DISABLE_MASK		GENMASK(19, 16)
+#define  PANELTIMING_DATA_DISABLE(x)		\
+			FIELD_PREP(PANELTIMING_DATA_DISABLE_MASK, (x))
+#define  PANELTIMING_CLOCK_DISABLE_MASK		GENMASK(23, 20)
+#define  PANELTIMING_CLOCK_DISABLE(x)		\
+			FIELD_PREP(PANELTIMING_CLOCK_DISABLE_MASK, (x))
+#define  PANELTIMING_BACKLIGHT_DISABLE_MASK	GENMASK(27, 24)
+#define  PANELTIMING_BACKLIGHT_DISABLE(x)	\
+			FIELD_PREP(PANELTIMING_BACKLIGHT_DISABLE_MASK, (x))
+#define  PANELTIMING_POWER_DISABLE_MASK		GENMASK(31, 28)
+#define  PANELTIMING_POWER_DISABLE(x)		\
+			FIELD_PREP(PANELTIMING_POWER_DISABLE_MASK, (x))
+
+#define DCNANO_HDISPLAY			0x1400
+#define  HDISPLAY_END_MASK		GENMASK(12, 0)
+#define  HDISPLAY_END(x)		FIELD_PREP(HDISPLAY_END_MASK, (x))
+#define  HDISPLAY_TOTAL_MASK		GENMASK(28, 16)
+#define  HDISPLAY_TOTAL(x)		FIELD_PREP(HDISPLAY_TOTAL_MASK, (x))
+
+#define DCNANO_HSYNC			0x1420
+#define  HSYNC_START_MASK		GENMASK(12, 0)
+#define  HSYNC_START(x)			FIELD_PREP(HSYNC_START_MASK, (x))
+#define  HSYNC_END_MASK			GENMASK(28, 16)
+#define  HSYNC_END(x)			FIELD_PREP(HSYNC_END_MASK, (x))
+/* double buffered? */
+#define  HSYNC_PULSE_DISABLE		0
+#define  HSYNC_PULSE_ENABLE		BIT(30)
+#define  HSYNC_POL_MASK			BIT(31)
+#define  HSYNC_POL_POSITIVE		0
+#define  HSYNC_POL_NEGATIVE		BIT(31)
+
+#define DCNANO_VDISPLAY			0x1480
+#define  VDISPLAY_END_MASK		GENMASK(11, 0)
+#define  VDISPLAY_END(x)		FIELD_PREP(VDISPLAY_END_MASK, (x))
+#define  VDISPLAY_TOTAL_MASK		GENMASK(27, 16)
+#define  VDISPLAY_TOTAL(x)		FIELD_PREP(VDISPLAY_TOTAL_MASK, (x))
+
+#define DCNANO_VSYNC			0x14a0
+#define  VSYNC_START_MASK		GENMASK(11, 0)
+#define  VSYNC_START(x)			FIELD_PREP(VSYNC_START_MASK, (x))
+#define  VSYNC_END_MASK			GENMASK(27, 16)
+#define  VSYNC_END(x)			FIELD_PREP(VSYNC_END_MASK, (x))
+/* double buffered? */
+#define  VSYNC_PULSE_DISABLE		0
+#define  VSYNC_PULSE_ENABLE		BIT(30)
+#define  VSYNC_POL_MASK			BIT(31)
+#define  VSYNC_POL_POSITIVE		0
+#define  VSYNC_POL_NEGATIVE		BIT(31)
+
+#define DCNANO_DISPLAYCURRENTLOCATION	0x14c0
+#define  CURRENTLOCATION_X_MASK		GENMASK(15, 0)
+#define  CURRENTLOCATION_X(x)		FIELD_PREP(CURRENTLOCATION_X_MASK, (x))
+#define  CURRENTLOCATION_X_GET(x)	FIELD_GET(CURRENTLOCATION_X_MASK, (x))
+#define  CURRENTLOCATION_Y_MASK		GENMASK(31, 16)
+#define  CURRENTLOCATION_Y(x)		FIELD_PREP(CURRENTLOCATION_Y_MASK, (x))
+#define  CURRENTLOCATION_Y_GET(x)	FIELD_GET(CURRENTLOCATION_Y_MASK, (x))
+
+#define DCNANO_GAMMAINDEX		0x14e0
+#define  GAMMAINDEX_MASK		GENMASK(7, 0)
+#define  GAMMAINDEX(x)			FIELD_PREP(GAMMAINDEX_MASK, (x))
+
+#define DCNANO_GAMMADATA		0x1500
+#define  GAMMADATA_BLUE_MASK		GENMASK(7, 0)
+#define  GAMMADATA_BLUE(x)		FIELD_PREP(GAMMADATA_BLUE_MASK, (x))
+#define  GAMMADATA_GREEN_MASK		GENMASK(15, 8)
+#define  GAMMADATA_GREEN(x)		FIELD_PREP(GAMMADATA_GREEN_MASK, (x))
+#define  GAMMADATA_RED_MASK		GENMASK(23, 16)
+#define  GAMMADATA_RED(x)		FIELD_PREP(GAMMADATA_RED_MASK, (x))
+
+#define DCNANO_CURSORCONFIG		0x1520
+/* double buffered */
+#define  CURSORCFG_FORMAT_MASK		GENMASK(1, 0)
+#define  CURSORCFG_FORMAT_NONE		FIELD_PREP(CURSORCFG_FORMAT_MASK, 0)
+#define  CURSORCFG_FORMAT_MASKED	FIELD_PREP(CURSORCFG_FORMAT_MASK, 1)
+#define  CURSORCFG_FORMAT_A8R8G8B8	FIELD_PREP(CURSORCFG_FORMAT_MASK, 2)
+#define  CURSORCFG_DISPLAY_MASK		BIT(4)
+#define  CURSORCFG_DISPLAY0		0
+#define  CURSORCFG_DISPLAY1		BIT(4)
+/* double buffered */
+#define  CURSORCFG_HOTSPOT_Y_MASK	GENMASK(12, 8)
+#define  CURSORCFG_HOTSPOT_Y(x)		FIELD_PREP(CURSORCFG_HOTSPOT_Y_MASK, 0)
+/* double buffered */
+#define  CURSORCFG_HOTSPOT_X_MASK	GENMASK(20, 16)
+#define  CURSORCFG_HOTSPOT_X(x)		FIELD_PREP(CURSORCFG_HOTSPOT_X_MASK, 0)
+#define  CURSORCFG_FLIP_INPROGRSS_NO	0
+#define  CURSORCFG_FLIP_INPROGRSS_YES	BIT(31)
+
+/* double buffered */
+#define DCNANO_CURSORADDRESS		0x1530
+#define  CURSORADDRESS_MASK		GENMASK(31, 0)
+#define  CURSORADDRESS(x)		FIELD_PREP(CURSORADDRESS_MASK, (x))
+#define  CURSORADDRESS_TYPE_SYSTEM	0
+#define  CURSORADDRESS_TYPE_VIRTUAL	BIT(31)
+
+/* double buffered */
+#define DCNANO_CURSORLOCATION		0x1540
+#define  CURSORLOCATION_X_MASK		GENMASK(12, 0)
+#define  CURSORLOCATION_X(x)		FIELD_PREP(CURSORLOCATION_X_MASK, (x))
+#define  CURSORLOCATION_X_MAX		FIELD_MAX(CURSORLOCATION_X_MASK)
+#define  CURSORLOCATION_Y_MASK		GENMASK(27, 16)
+#define  CURSORLOCATION_Y(x)		FIELD_PREP(CURSORLOCATION_Y_MASK, (x))
+#define  CURSORLOCATION_Y_MAX		FIELD_MAX(CURSORLOCATION_Y_MASK)
+
+/* double buffered */
+#define DCNANO_CURSORBACKGROUND		0x1550
+/* double buffered */
+#define DCNANO_CURSORFOREGROUND		0x1560
+#define  CURSOR_BLUE_MASK		GENMASK(7, 0)
+#define  CURSOR_BLUE(x)			FIELD_PREP(CURSOR_BLUE_MASK, (x))
+#define  CURSOR_GREEN_MASK		GENMASK(15, 8)
+#define  CURSOR_GREEN(x)		FIELD_PREP(CURSOR_GREEN_MASK, (x))
+#define  CURSOR_RED_MASK		GENMASK(23, 16)
+#define  CURSOR_RED(x)			FIELD_PREP(CURSOR_RED_MASK, (x))
+
+#define DCNANO_DISPLAYINTR		0x1600
+#define DCNANO_DISPLAYINTRENABLE	0x1610
+#define  DISPLAYINTR_DISP0		BIT(0)
+
+#define DCNANO_DBICONFIG		0x1620
+#define  DBICFG_DBI_TYPE_MASK		GENMASK(1, 0)
+#define  DBICFG_DBI_TYPE_A_FIXED_E	FIELD_PREP(DBICFG_DBI_TYPE_MASK, 0)
+#define  DBICFG_DBI_TYPE_A_CLOCK_E	FIELD_PREP(DBICFG_DBI_TYPE_MASK, 1)
+#define  DBICFG_DBI_TYPE_B		FIELD_PREP(DBICFG_DBI_TYPE_MASK, 2)
+#define  DBICFG_DBI_TYPE_C		FIELD_PREP(DBICFG_DBI_TYPE_MASK, 3)
+#define  DBICFG_DATA_FORMAT_MASK	GENMASK(5, 2)
+
+/* 8bit  data bus - D[7 : 0] */
+/* 8bpp */
+#define  DBICFG_DATA_FORMAT_D8R3G3B2	 FIELD_PREP(DBICFG_DATA_FORMAT_MASK, 0)
+/* 12bpp */
+#define  DBICFG_DATA_FORMAT_D8R4G4B4	 FIELD_PREP(DBICFG_DATA_FORMAT_MASK, 1)
+/* 16bpp */
+#define  DBICFG_DATA_FORMAT_D8R5G6B5	 FIELD_PREP(DBICFG_DATA_FORMAT_MASK, 2)
+/* 18bpp */
+#define  DBICFG_DATA_FORMAT_D8R6G6B6	 FIELD_PREP(DBICFG_DATA_FORMAT_MASK, 3)
+/* 24bpp */
+#define  DBICFG_DATA_FORMAT_D8R8G8B8	 FIELD_PREP(DBICFG_DATA_FORMAT_MASK, 4)
+
+/* 9bit  data bus - D[8 : 0] */
+/* 18bpp */
+#define  DBICFG_DATA_FORMAT_D9R6G6B6	 FIELD_PREP(DBICFG_DATA_FORMAT_MASK, 5)
+
+/* 16bit data bus - D[15 : 0] */
+/* 8bpp */
+#define  DBICFG_DATA_FORMAT_D16R3G3B2	 FIELD_PREP(DBICFG_DATA_FORMAT_MASK, 6)
+/* 12bpp */
+#define  DBICFG_DATA_FORMAT_D16R4G4B4	 FIELD_PREP(DBICFG_DATA_FORMAT_MASK, 7)
+/* 16bpp */
+#define  DBICFG_DATA_FORMAT_D16R5G6B5	 FIELD_PREP(DBICFG_DATA_FORMAT_MASK, 8)
+/* 18bpp */
+#define  DBICFG_DATA_FORMAT_D16R6G6B6OP1 FIELD_PREP(DBICFG_DATA_FORMAT_MASK, 9)
+#define  DBICFG_DATA_FORMAT_D16R6G6B6OP2 FIELD_PREP(DBICFG_DATA_FORMAT_MASK, 10)
+/* 24bpp */
+#define  DBICFG_DATA_FORMAT_D16R8G8B8OP1 FIELD_PREP(DBICFG_DATA_FORMAT_MASK, 11)
+#define  DBICFG_DATA_FORMAT_D16R8G8B8OP2 FIELD_PREP(DBICFG_DATA_FORMAT_MASK, 12)
+
+#define  DBICFG_BUS_OUTPUT_SEL_DPI	0
+#define  DBICFG_BUS_OUTPUT_SEL_DBI	BIT(6)
+#define  DBICFG_DBIX_POLARITY_DEFAULT	0
+#define  DBICFG_DBIX_POLARITY_REVERSE	BIT(7)
+#define  DBICFG_DBI_AC_TIME_UNIT_MASK	GENMASK(11, 8)
+#define  DBICFG_DBI_AC_TIME_UNIT(x)	\
+				FIELD_PREP(DBICFG_DBI_AC_TIME_UNIT_MASK, (x))
+#define  DBICFG_DBI_TYPEC_OPT_MASK	GENMASK(13, 12)
+#define  DBICFG_DBI_TYPEC_OPT1		FIELD_PREP(DBICFG_DBI_TYPEC_OPT_MASK, 0)
+#define  DBICFG_DBI_TYPEC_OPT2		FIELD_PREP(DBICFG_DBI_TYPEC_OPT_MASK, 1)
+#define  DBICFG_DBI_TYPEC_OPT3		FIELD_PREP(DBICFG_DBI_TYPEC_OPT_MASK, 2)
+
+#define DCNANO_DBIIFRESET		0x1640
+#define  DBIIF_LEVEL_NO_RESET		0
+#define  DBIIF_LEVEL_RESET		BIT(0)
+
+#define DCNANO_DBIWRCHAR1		0x1660
+#define  DBIWR_PERIOD_MASK		GENMASK(7, 0)
+#define  DBIWR_PERIOD(x)		FIELD_PREP(DBIWR_PERIOD_MASK, (x))
+#define  DBIWR_EOR_WR_ASSERT_MASK	GENMASK(11, 8)
+#define  DBIWR_EOR_WR_ASSERT(x)		FIELD_PREP(DBIWR_EOR_WR_ASSERT_MASK, (x))
+#define  DBIWR_CS_ASSERT_MASK		GENMASK(15, 12)
+#define  DBIWR_CS_ASSERT(x)		FIELD_PREP(DBIWR_CS_ASSERT_MASK, (x))
+
+#define DCNANO_DBIWRCHAR2		0x1680
+#define  DBIWR_EOR_WR_DE_ASRT_MASK	GENMASK(7, 0)
+#define  DBIWR_EOR_WR_DE_ASRT(x)	\
+				FIELD_PREP(DBIWR_EOR_WR_DE_ASRT_MASK, (x))
+#define  DBIWR_CS_DE_ASRT_MASK		GENMASK(15, 8)
+#define  DBIWR_CS_DE_ASRT(x)		FIELD_PREP(DBIWR_CS_DE_ASRT_MASK, (x))
+
+#define DCNANO_DBICMD			0x16a0
+#define  DBICMD_WORD_MASK		GENMASK(15, 0)
+#define  DBICMD_WORD(x)			FIELD_PREP(DBICMD_WORD_MASK, (x))
+#define  DBICMD_FLAG_MASK		GENMASK(31, 30)
+#define  DBICMD_FLAG_ADDRESS		FIELD_PREP(DBICMD_FLAG_MASK, 0)
+#define  DBICMD_FLAG_WRITE_MEM_START	FIELD_PREP(DBICMD_FLAG_MASK, 1)
+#define  DBICMD_FLAG_PARAMETER_OR_DATA	FIELD_PREP(DBICMD_FLAG_MASK, 2)
+/* Read is unused. */
+#define  DBICMD_FLAG_READ		FIELD_PREP(DBICMD_FLAG_MASK, 3)
+
+#define DCNANO_DPICONFIG		0x16c0
+#define  DPICFG_DATA_FORMAT_MASK	GENMASK(2, 0)
+#define  DPICFG_DATA_FORMAT_D16CFG1	FIELD_PREP(DPICFG_DATA_FORMAT_MASK, 0)
+#define  DPICFG_DATA_FORMAT_D16CFG2	FIELD_PREP(DPICFG_DATA_FORMAT_MASK, 1)
+#define  DPICFG_DATA_FORMAT_D16CFG3	FIELD_PREP(DPICFG_DATA_FORMAT_MASK, 2)
+#define  DPICFG_DATA_FORMAT_D18CFG1	FIELD_PREP(DPICFG_DATA_FORMAT_MASK, 3)
+#define  DPICFG_DATA_FORMAT_D18CFG2	FIELD_PREP(DPICFG_DATA_FORMAT_MASK, 4)
+#define  DPICFG_DATA_FORMAT_D24		FIELD_PREP(DPICFG_DATA_FORMAT_MASK, 5)
+
+#define DCNANO_DCCHIPREV		0x16f0
+#define  DCCHIPREV_MASK			GENMASK(31, 0)
+#define  DCCHIPREV			0x00005543
+
+#define DCNANO_DCCHIPDATE		0x1700
+#define  DCCHIPDATE_MASK		GENMASK(31, 0)
+#define  DCCHIPDATE			0x20180612
+
+#define DCNANO_DCCHIPPATCHREV		0x1720
+#define  DCCHIPPATCHREV_MASK		GENMASK(31, 0)
+#define  DCCHIPPATCHREV			0x00000003
+
+#define DCNANO_DCTILEINCFG		0x1740
+/* double buffered */
+#define  DCTILEINCFG_TILE_FORMAT_MASK	GENMASK(1, 0)
+#define  DCTILEINCFG_TILE_FORMAT_NONE		\
+				FIELD_PREP(DCTILEINCFG_TILE_FORMAT_MASK, 0)
+#define  DCTILEINCFG_TILE_FORMAT_ARGB8888	\
+				FIELD_PREP(DCTILEINCFG_TILE_FORMAT_MASK, 1)
+#define  DCTILEINCFG_TILE_FORMAT_YUY2		\
+				FIELD_PREP(DCTILEINCFG_TILE_FORMAT_MASK, 2)
+#define  DCTILEINCFG_TILE_FORMAT_NV12		\
+				FIELD_PREP(DCTILEINCFG_TILE_FORMAT_MASK, 3)
+#define  DCTILEINCFG_YUV_STANDARD_MASK	GENMASK(3, 2)
+/* double buffered */
+#define  DCTILEINCFG_YUV_BT601			\
+				FIELD_PREP(DCTILEINCFG_YUV_STANDARD_MASK, 0)
+#define  DCTILEINCFG_YUV_BT709			\
+				FIELD_PREP(DCTILEINCFG_YUV_STANDARD_MASK, 1)
+/* double buffered */
+#define  DCTILEINCFG_YUV2_RGB_EN_MASK	BIT(4)
+#define  DCTILEINCFG_YUV2_RGB_ENABLE	BIT(4)
+#define  DCTILEINCFG_YUV2_RGB_DISABLE	0
+#define  DCTILEINCFG_CFG_MODE_EN	BIT(5)
+#define  DCTILEINCFG_CFG_MODE_ENABLE	BIT(5)
+#define  DCTILEINCFG_CFG_MODE_DISABLE	0
+
+/* double buffered */
+#define DCNANO_DCTILEUVFRAMEBUFFERADR	0x1760
+#define  DCTILEUVFB_ADDRESS_MASK	GENMASK(31, 0)
+#define  DCTILEUVFB_ADDRESS(x)		FIELD_PREP(DCTILEUVFB_ADDRESS_MASK, (x))
+#define  DCTILEUVFB_ADDRESS_MAX		FIELD_MAX(DCTILEUVFB_ADDRESS_MASK)
+
+/* double buffered */
+#define DCNANO_DCTILEUVFRAMEBUFFERSTR	0x1780
+#define  DCTILEUVFB_STRIDE_MASK		GENMASK(15, 0)
+#define  DCTILEUVFB_STRIDE(x)		FIELD_PREP(DCTILEUVFB_STRIDE_MASK, (x))
+#define  DCTILEUVFB_STRIDE_MAX		FIELD_MAX(DCTILEUVFB_STRIDE_MASK)
+
+#define DCNANO_DCPRODUCTID		0x17b0
+#define  DCPRODUCTID_MASK		GENMASK(31, 0)
+#define  DCPRODUCTID			0x02000361
+
+#define DCNANO_DCSTATUS			0x1800
+#define  DCSTATUS_DBI_TYPEC_FIFO_FULL	BIT(0)
+
+#define DCNANO_DEBUGCOUNTERSELECT	0x1820
+#define  DEBUGCOUNTERSELECT_MASK	GENMASK(7, 0)
+#define  TOTAL_AXI_RD_REQ_CNT		FIELD_PREP(DEBUGCOUNTERSELECT_MASK, 0)
+#define  TOTAL_AXI_RD_LAST_CNT		FIELD_PREP(DEBUGCOUNTERSELECT_MASK, 1)
+#define  TOTAL_AXI_REQ_BURST_CNT	FIELD_PREP(DEBUGCOUNTERSELECT_MASK, 2)
+#define  TOTAL_AXI_RD_BURST_CNT		FIELD_PREP(DEBUGCOUNTERSELECT_MASK, 3)
+#define  TOTAL_PIXEL_CNT		FIELD_PREP(DEBUGCOUNTERSELECT_MASK, 4)
+#define  TOTAL_FRAME_CNT		FIELD_PREP(DEBUGCOUNTERSELECT_MASK, 5)
+#define  TOTAL_INPUT_DBI_CMD_CNT	FIELD_PREP(DEBUGCOUNTERSELECT_MASK, 6)
+#define  TOTAL_OUTPUT_DBI_CMD_CNT	FIELD_PREP(DEBUGCOUNTERSELECT_MASK, 7)
+#define  DEBUG_SIGNALS0			FIELD_PREP(DEBUGCOUNTERSELECT_MASK, 8)
+#define  RESET_ALL_CNTS			FIELD_PREP(DEBUGCOUNTERSELECT_MASK, 0xFF)
+
+#define DCNANO_DEBUGCOUNTERVALUE	0x1840
+#define  DEBUGCOUNTERVALUE_MASK		GENMASK(31, 0)
+#define  DEBUGCOUNTERVALUE(x)		FIELD_PREP(DEBUGCOUNTERVALUE_MASK, (x))
+#define  DEBUGCOUNTERVALUE_MAX		FIELD_MAX(DEBUGCOUNTERVALUE_MASK)
+
+#endif
diff --git a/drivers/video/nxp/imx/dcnano.c b/drivers/video/nxp/imx/dcnano.c
new file mode 100644
index 00000000000..c651f2ea1d3
--- /dev/null
+++ b/drivers/video/nxp/imx/dcnano.c
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <video.h>
+#include <video_fb.h>
+#include <video_bridge.h>
+#include <video_link.h>
+
+#include <asm/cache.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/err.h>
+#include <asm/io.h>
+
+#include <linux/string.h>
+#include <linux/list.h>
+#include <linux/fb.h>
+#include <linux/bug.h>
+#include <linux/delay.h>
+#include "dcnano-reg.h"
+#include <log.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/device_compat.h>
+
+struct dcnano_priv {
+	fdt_addr_t reg_base;
+	struct udevice *disp_dev;
+};
+
+static int dcnano_check_chip_info(struct dcnano_priv *dcnano)
+{
+	u32 val;
+	int ret = 0;
+
+	val = readl((ulong)(dcnano->reg_base + DCNANO_DCCHIPREV));
+	if (val != DCCHIPREV) {
+		printf("invalid chip revision(0x%08x)\n", val);
+		ret = -ENODEV;
+		return ret;
+	}
+	debug("chip revision is 0x%08x\n", val);
+
+	val = readl((ulong)(dcnano->reg_base + DCNANO_DCCHIPDATE));
+	if (val != DCCHIPDATE) {
+		printf("invalid chip date(0x%08x)\n", val);
+		ret = -ENODEV;
+		return ret;
+	}
+	debug("chip date is 0x%08x\n", val);
+
+	val = readl((ulong)(dcnano->reg_base + DCNANO_DCCHIPPATCHREV));
+	if (val != DCCHIPPATCHREV) {
+		printf("invalid chip patch revision(0x%08x)\n", val);
+		ret = -ENODEV;
+		return ret;
+	}
+	debug("chip patch revision is 0x%08x\n", val);
+
+	return ret;
+}
+
+static void dcnano_set_mode(struct dcnano_priv *priv,
+			struct display_timing *timing)
+{
+	u32 val, htotal, vtotal;
+
+	/* select output bus, only support DPI */
+	writel(DBICFG_BUS_OUTPUT_SEL_DPI, (ulong)(priv->reg_base + DCNANO_DBICONFIG));
+
+	/* set bus format, fixed to 24 */
+	writel(DPICFG_DATA_FORMAT_D24, (ulong)(priv->reg_base + DCNANO_DPICONFIG));
+
+	htotal = timing->hactive.typ + timing->hback_porch.typ +
+		timing->hfront_porch.typ + timing->hsync_len.typ;
+	vtotal = timing->vactive.typ + timing->vback_porch.typ +
+		timing->vfront_porch.typ + timing->vsync_len.typ;
+
+	/* timing: active + front porch + sync + back porch = total */
+
+	/* horizontal timing */
+	val = HDISPLAY_END(timing->hactive.typ) |
+	      HDISPLAY_TOTAL(htotal);
+	writel(val, (ulong)(priv->reg_base + DCNANO_HDISPLAY));
+
+	val = HSYNC_START(htotal - timing->hback_porch.typ - timing->hsync_len.typ) |
+	      HSYNC_END(htotal - timing->hback_porch.typ) | HSYNC_PULSE_ENABLE;
+	if (timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)
+		val |= HSYNC_POL_POSITIVE;
+	else
+		val |= HSYNC_POL_NEGATIVE;
+	writel(val, (ulong)(priv->reg_base + DCNANO_HSYNC));
+
+	/* vertical timing */
+	val = VDISPLAY_END(timing->vactive.typ) |
+	      VDISPLAY_TOTAL(vtotal);
+	writel(val, (ulong)(priv->reg_base + DCNANO_VDISPLAY));
+
+	val = VSYNC_START(vtotal - timing->vback_porch.typ - timing->vsync_len.typ) |
+	      VSYNC_END(vtotal - timing->vback_porch.typ) | VSYNC_PULSE_ENABLE;
+	if (timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)
+		val |= VSYNC_POL_POSITIVE;
+	else
+		val |= VSYNC_POL_NEGATIVE;
+	writel(val, (ulong)(priv->reg_base + DCNANO_VSYNC));
+
+	/* panel configuration */
+	val = PANELCFG_DE_ENABLE | PANELCFG_DE_POL_POSITIVE |
+	      PANELCFG_DATA_ENABLE | PANELCFG_DATA_POL_POSITIVE |
+	      PANELCFG_CLOCK_ENABLE | PANELCFG_CLOCK_POL_POSITIVE |
+	      PANELCFG_SEQUENCING_SOFTWARE;
+	writel(val, (ulong)(priv->reg_base + DCNANO_PANELCONFIG));
+}
+
+static void dcnano_disable_controller(struct dcnano_priv *priv)
+{
+	writel(0, (ulong)(priv->reg_base + DCNANO_FRAMEBUFFERCONFIG));
+}
+
+static void dcnano_init(struct udevice *dev,
+			struct display_timing *timing, unsigned int format)
+{
+	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+	struct dcnano_priv *priv = dev_get_priv(dev);
+	u32 primary_fb_fmt = 0, val = 0;
+
+	/* Kick in the LCDIF clock */
+	mxs_set_lcdclk(priv->reg_base, timing->pixelclock.typ / 1000);
+
+	dcnano_check_chip_info(priv);
+
+	dcnano_set_mode(priv, timing);
+
+	/* Set fb address */
+	writel(plat->base, (ulong)(priv->reg_base + DCNANO_FRAMEBUFFERADDRESS));
+
+	switch (format) {
+	case GDF_16BIT_565RGB:
+		/* 16 bpp */
+		writel(ALIGN(timing->hactive.typ * 2, 128),
+			(ulong)(priv->reg_base + DCNANO_FRAMEBUFFERSTRIDE));
+		primary_fb_fmt = FBCFG_FORMAT_R5G6B5;
+		break;
+	case GDF_32BIT_X888RGB:
+		/* 32 bpp */
+		writel(ALIGN(timing->hactive.typ * 4, 128),
+			(ulong)(priv->reg_base + DCNANO_FRAMEBUFFERSTRIDE));
+		primary_fb_fmt = FBCFG_FORMAT_R8G8B8;
+		break;
+	default:
+		printf("unsupported pixel format: %u\n", format);
+		return;
+	}
+
+	/* Disable interrupts */
+	writel(0, (ulong)(priv->reg_base + DCNANO_DISPLAYINTRENABLE));
+
+	/* Enable controller */
+	val = FBCFG_OUTPUT_ENABLE | FBCFG_RESET_ENABLE | primary_fb_fmt;
+	writel(val, (ulong)(priv->reg_base + DCNANO_FRAMEBUFFERCONFIG));
+}
+
+void dcnano_power_down(struct dcnano_priv *priv)
+{
+	dcnano_disable_controller(priv);
+}
+
+static int dcnano_of_get_timings(struct udevice *dev,
+			      struct display_timing *timings)
+{
+	int ret = 0;
+	struct dcnano_priv *priv = dev_get_priv(dev);
+
+	priv->disp_dev = video_link_get_next_device(dev);
+	if (!priv->disp_dev ||
+		(device_get_uclass_id(priv->disp_dev) != UCLASS_VIDEO_BRIDGE
+		&& device_get_uclass_id(priv->disp_dev) != UCLASS_DISPLAY)) {
+
+		printf("fail to find output device\n");
+		return -ENODEV;
+	}
+
+	debug("disp_dev %s\n", priv->disp_dev->name);
+
+	ret = video_link_get_display_timings(timings);
+	if (ret) {
+		printf("fail to get display timings\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+static int dcnano_video_probe(struct udevice *dev)
+{
+	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct dcnano_priv *priv = dev_get_priv(dev);
+
+	struct display_timing timings;
+
+	u32 fb_start, fb_end;
+	int ret;
+
+	debug("%s() plat: base 0x%lx, size 0x%x\n",
+	       __func__, plat->base, plat->size);
+
+	priv->reg_base = dev_read_addr(dev);
+	if (priv->reg_base == FDT_ADDR_T_NONE) {
+		dev_err(dev, "lcdif base address is not found\n");
+		return -EINVAL;
+	}
+
+	ret = dcnano_of_get_timings(dev, &timings);
+	if (ret)
+		return ret;
+
+	reset_lcdclk();
+
+	if (priv->disp_dev) {
+#if IS_ENABLED(CONFIG_VIDEO_BRIDGE)
+		if (device_get_uclass_id(priv->disp_dev) == UCLASS_VIDEO_BRIDGE) {
+			ret = video_bridge_attach(priv->disp_dev);
+			if (ret) {
+				dev_err(dev, "fail to attach bridge\n");
+				return ret;
+			}
+
+			ret = video_bridge_set_backlight(priv->disp_dev, 80);
+			if (ret) {
+				dev_err(dev, "fail to set backlight\n");
+				return ret;
+			}
+		}
+#endif
+	}
+
+	dcnano_init(dev, &timings, GDF_32BIT_X888RGB);
+
+	uc_priv->bpix = VIDEO_BPP32; /* only support 32 BPP now */
+	uc_priv->xsize = timings.hactive.typ;
+	uc_priv->ysize = timings.vactive.typ;
+
+	/* Enable dcache for the frame buffer */
+	fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
+	fb_end = plat->base + plat->size;
+	fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
+	mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
+					DCACHE_WRITEBACK);
+	video_set_flush_dcache(dev, true);
+	gd->fb_base = plat->base;
+
+	return ret;
+}
+
+static int dcnano_video_bind(struct udevice *dev)
+{
+	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+
+	/* Max size supported by LCDIF, because in bind, we can't probe panel */
+	plat->size = 1920 * 1080 *4 * 2;
+
+	return 0;
+}
+
+static int dcnano_video_remove(struct udevice *dev)
+{
+	struct dcnano_priv *priv = dev_get_priv(dev);
+
+	debug("%s\n", __func__);
+
+	if (priv->disp_dev)
+		device_remove(priv->disp_dev, DM_REMOVE_NORMAL);
+
+	dcnano_power_down(priv);
+
+	return 0;
+}
+
+static const struct udevice_id dcnano_video_ids[] = {
+	{ .compatible = "nxp,imx8ulp-dcnano" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(dcnano_video) = {
+	.name	= "dcnano_video",
+	.id	= UCLASS_VIDEO,
+	.of_match = dcnano_video_ids,
+	.bind	= dcnano_video_bind,
+	.probe	= dcnano_video_probe,
+	.remove = dcnano_video_remove,
+	.flags	= DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
+	.priv_auto   = sizeof(struct dcnano_priv),
+};
diff --git a/drivers/video/nxp/imx/dw_dsi_imx.c b/drivers/video/nxp/imx/dw_dsi_imx.c
new file mode 100644
index 00000000000..cf65ec02e5a
--- /dev/null
+++ b/drivers/video/nxp/imx/dw_dsi_imx.c
@@ -0,0 +1,436 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dsi_host.h>
+#include <mipi_dsi.h>
+#include <panel.h>
+#include <reset.h>
+#include <video.h>
+#include <video_bridge.h>
+#include <video_link.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <dm/device-internal.h>
+#include <linux/iopoll.h>
+#include <linux/err.h>
+#include <phy-mipi-dphy.h>
+#include <generic-phy.h>
+
+#define MSEC_PER_SEC			1000
+
+struct dw_dsi_imx_priv {
+	struct mipi_dsi_device device;
+	struct udevice *panel;
+	struct udevice *dsi_host;
+
+	struct clk byte_clk;
+
+	struct phy phy;
+	struct phy_configure_opts_mipi_dphy phy_cfg;
+
+	unsigned int lane_mbps; /* per lane */
+	u32 lanes;
+	u32 format;
+	struct display_timing adj;
+};
+
+static int dw_mipi_dsi_imx_phy_init(void *priv_data)
+{
+	struct dw_dsi_imx_priv *dsi = priv_data;
+	int ret;
+
+	ret = generic_phy_init(&dsi->phy);
+	if (ret < 0) {
+		dev_err(dsi->device.dev, "failed to init phy: %d\n", ret);
+		return ret;
+	}
+
+	ret = generic_phy_configure(&dsi->phy, &dsi->phy_cfg);
+	if (ret < 0) {
+		dev_err(dsi->device.dev, "failed to configure phy: %d\n", ret);
+		goto uninit_phy;
+	}
+
+	ret = generic_phy_power_on(&dsi->phy);
+	if (ret < 0) {
+		dev_err(dsi->device.dev, "failed to power on phy: %d\n", ret);
+		goto uninit_phy;
+	}
+
+	return ret;
+
+uninit_phy:
+	generic_phy_exit(&dsi->phy);
+	return ret;
+}
+
+static int
+dw_mipi_dsi_get_lane_mbps(void *priv_data, struct display_timing *timings,
+								 u32 lanes, u32 format, unsigned int *lane_mbps)
+{
+	struct dw_dsi_imx_priv *dsi = priv_data;
+	int bpp;
+	int ret;
+
+	bpp = mipi_dsi_pixel_format_to_bpp(format);
+	if (bpp < 0) {
+		dev_dbg(dsi->device.dev,
+			      "failed to get bpp for pixel format %d\n",
+			      format);
+		return bpp;
+	}
+
+	dsi->lane_mbps = DIV_ROUND_UP((timings->pixelclock.typ / 1000) * (bpp / lanes), MSEC_PER_SEC);
+	*lane_mbps = dsi->lane_mbps;
+
+	debug("lane_mbps %u, bpp %d\n", *lane_mbps, bpp);
+
+	ret = phy_mipi_dphy_get_default_config(timings->pixelclock.typ,
+					       bpp, lanes,
+					       &dsi->phy_cfg);
+	if (ret < 0) {
+		dev_dbg(dsi->device.dev, "failed to get default phy cfg %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+struct hstt {
+	unsigned int maxfreq;
+	struct mipi_dsi_phy_timing timing;
+};
+
+#define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp)	\
+{								\
+	.maxfreq = (_maxfreq),					\
+	.timing = {						\
+		.clk_lp2hs = (_c_lp2hs),			\
+		.clk_hs2lp = (_c_hs2lp),			\
+		.data_lp2hs = (_d_lp2hs),			\
+		.data_hs2lp = (_d_hs2lp),			\
+	}							\
+}
+
+/* Table A-4 High-Speed Transition Times */
+struct hstt hstt_table[] = {
+	HSTT(80,   21,  17,  15, 10),
+	HSTT(90,   23,  17,  16, 10),
+	HSTT(100,  22,  17,  16, 10),
+	HSTT(110,  25,  18,  17, 11),
+	HSTT(120,  26,  20,  18, 11),
+	HSTT(130,  27,  19,  19, 11),
+	HSTT(140,  27,  19,  19, 11),
+	HSTT(150,  28,  20,  20, 12),
+	HSTT(160,  30,  21,  22, 13),
+	HSTT(170,  30,  21,  23, 13),
+	HSTT(180,  31,  21,  23, 13),
+	HSTT(190,  32,  22,  24, 13),
+	HSTT(205,  35,  22,  25, 13),
+	HSTT(220,  37,  26,  27, 15),
+	HSTT(235,  38,  28,  27, 16),
+	HSTT(250,  41,  29,  30, 17),
+	HSTT(275,  43,  29,  32, 18),
+	HSTT(300,  45,  32,  35, 19),
+	HSTT(325,  48,  33,  36, 18),
+	HSTT(350,  51,  35,  40, 20),
+	HSTT(400,  59,  37,  44, 21),
+	HSTT(450,  65,  40,  49, 23),
+	HSTT(500,  71,  41,  54, 24),
+	HSTT(550,  77,  44,  57, 26),
+	HSTT(600,  82,  46,  64, 27),
+	HSTT(650,  87,  48,  67, 28),
+	HSTT(700,  94,  52,  71, 29),
+	HSTT(750,  99,  52,  75, 31),
+	HSTT(800, 105,  55,  82, 32),
+	HSTT(850, 110,  58,  85, 32),
+	HSTT(900, 115,  58,  88, 35),
+	HSTT(950, 120,  62,  93, 36),
+	HSTT(1000, 128,  63,  99, 38),
+	HSTT(1050, 132,  65, 102, 38),
+	HSTT(1100, 138,  67, 106, 39),
+	HSTT(1150, 146,  69, 112, 42),
+	HSTT(1200, 151,  71, 117, 43),
+	HSTT(1250, 153,  74, 120, 45),
+	HSTT(1300, 160,  73, 124, 46),
+	HSTT(1350, 165,  76, 130, 47),
+	HSTT(1400, 172,  78, 134, 49),
+	HSTT(1450, 177,  80, 138, 49),
+	HSTT(1500, 183,  81, 143, 52),
+	HSTT(1550, 191,  84, 147, 52),
+	HSTT(1600, 194,  85, 152, 52),
+	HSTT(1650, 201,  86, 155, 53),
+	HSTT(1700, 208,  88, 161, 53),
+	HSTT(1750, 212,  89, 165, 53),
+	HSTT(1800, 220,  90, 171, 54),
+	HSTT(1850, 223,  92, 175, 54),
+	HSTT(1900, 231,  91, 180, 55),
+	HSTT(1950, 236,  95, 185, 56),
+	HSTT(2000, 243,  97, 190, 56),
+	HSTT(2050, 248,  99, 194, 58),
+	HSTT(2100, 252, 100, 199, 59),
+	HSTT(2150, 259, 102, 204, 61),
+	HSTT(2200, 266, 105, 210, 62),
+	HSTT(2250, 269, 109, 213, 63),
+	HSTT(2300, 272, 109, 217, 65),
+	HSTT(2350, 281, 112, 225, 66),
+	HSTT(2400, 283, 115, 226, 66),
+	HSTT(2450, 282, 115, 226, 67),
+	HSTT(2500, 281, 118, 227, 67),
+};
+
+static int
+dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
+			   struct mipi_dsi_phy_timing *timing)
+{
+	struct dw_dsi_imx_priv *dsi = priv_data;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(hstt_table); i++)
+		if (lane_mbps <= hstt_table[i].maxfreq)
+			break;
+
+	if (i == ARRAY_SIZE(hstt_table))
+		i--;
+
+	*timing = hstt_table[i].timing;
+
+	dev_dbg(dsi->device.dev, "get phy timing for %u <= %u (lane_mbps)\n",
+		      lane_mbps, hstt_table[i].maxfreq);
+
+	return 0;
+}
+
+static const struct mipi_dsi_phy_ops dsi_imx_phy_ops = {
+	.init = dw_mipi_dsi_imx_phy_init,
+	.get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
+	.get_timing = dw_mipi_dsi_phy_get_timing,
+};
+
+static bool dw_dsi_imx_hcomponents_need_fixup(struct dw_dsi_imx_priv *dsi,
+				       int bpp,
+				       struct display_timing *timings)
+{
+	int htotal = timings->hactive.typ + timings->hfront_porch.typ +
+		 timings->hback_porch.typ + timings->hsync_len.typ;
+	int hsa = timings->hsync_len.typ;
+	int hbp = timings->hback_porch.typ;
+	int divisor = dsi->lanes * 8;
+
+	/*
+	 * It appears that (hcomponent * bpp) / (8 * lanes)
+	 * should be no remainder.
+	 */
+	return !!((htotal * bpp) % divisor) ||
+	       !!((hsa * bpp) % divisor) ||
+	       !!((hbp * bpp) % divisor);
+}
+
+static int dw_dsi_imx_fixup_hcomponent(struct dw_dsi_imx_priv *dsi,
+					    int bpp, int component)
+{
+	int divisor, i;
+
+	divisor = dsi->lanes * 8;
+
+	for (i = 0; i < divisor; i++) {
+		if ((bpp * (component + i)) % divisor == 0) {
+			component += i;
+			break;
+		}
+	}
+
+	return component;
+}
+
+static void dw_dsi_imx_fixup_hcomponents(struct dw_dsi_imx_priv *dsi,
+				  int bpp,
+				  struct display_timing *timings,
+				  struct display_timing *adj)
+{
+	int hfp = timings->hfront_porch.typ;
+	int hsa = timings->hsync_len.typ;
+	int hbp = timings->hback_porch.typ;
+
+	adj->hfront_porch.typ = dw_dsi_imx_fixup_hcomponent(dsi, bpp, hfp);
+	adj->hsync_len.typ = dw_dsi_imx_fixup_hcomponent(dsi, bpp, hsa);
+	adj->hback_porch.typ = dw_dsi_imx_fixup_hcomponent(dsi, bpp, hbp);
+}
+
+static int dw_dsi_imx_attach(struct udevice *dev)
+{
+	struct dw_dsi_imx_priv *priv = dev_get_priv(dev);
+	struct mipi_dsi_device *device = &priv->device;
+	struct mipi_dsi_panel_plat *mplat;
+	struct display_timing timings;
+	int ret, bpp;
+
+	priv->panel = video_link_get_next_device(dev);
+	if (!priv->panel ||
+		device_get_uclass_id(priv->panel) != UCLASS_PANEL) {
+		dev_err(dev, "get panel device error\n");
+		return -ENODEV;
+	}
+
+	mplat = dev_get_plat(priv->panel);
+	mplat->device = &priv->device;
+
+	ret = video_link_get_display_timings(&timings);
+	if (ret) {
+		dev_err(dev, "decode display timing error %d\n", ret);
+		return ret;
+	}
+
+	bpp = mipi_dsi_pixel_format_to_bpp(device->format);
+	if (bpp < 0) {
+		dev_err(dev, "failed to get bpp for pixel format %d\n", device->format);
+		return bpp;
+	}
+
+	priv->lanes = device->lanes;
+	priv->format = device->format;
+
+	priv->adj = timings;
+	if (dw_dsi_imx_hcomponents_need_fixup(priv, bpp, &timings))
+		dw_dsi_imx_fixup_hcomponents(priv, bpp, &timings, &priv->adj);
+
+	ret = uclass_get_device(UCLASS_DSI_HOST, 0, &priv->dsi_host);
+	if (ret) {
+		dev_err(dev, "No video dsi host detected %d\n", ret);
+		return ret;
+	}
+
+	ret = dsi_host_init(priv->dsi_host, device, &priv->adj,
+			4,
+			&dsi_imx_phy_ops);
+	if (ret) {
+		dev_err(dev, "failed to initialize mipi dsi host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int dw_dsi_imx_set_backlight(struct udevice *dev, int percent)
+{
+	struct dw_dsi_imx_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = panel_enable_backlight(priv->panel);
+	if (ret) {
+		dev_err(dev, "panel %s enable backlight error %d\n",
+			priv->panel->name, ret);
+		return ret;
+	}
+
+	ret = dsi_host_enable(priv->dsi_host);
+	if (ret) {
+		dev_err(dev, "failed to enable mipi dsi host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int dw_dsi_imx_check_timing(struct udevice *dev, struct display_timing *timing)
+{
+	struct dw_dsi_imx_priv *priv = dev_get_priv(dev);
+
+	/* Ensure the bridge device attached to panel */
+	if (!priv->panel) {
+		dev_err(dev, "%s No panel device attached\n", __func__);
+		return -ENOTCONN;
+	}
+
+	*timing = priv->adj;
+
+	return 0;
+}
+
+static int dw_dsi_imx_probe(struct udevice *dev)
+{
+	struct dw_dsi_imx_priv *priv = dev_get_priv(dev);
+	struct mipi_dsi_device *device = &priv->device;
+	int ret;
+
+	device->dev = dev;
+
+	ret = clk_get_by_name(device->dev, "byte", &priv->byte_clk);
+	if (ret) {
+		dev_err(dev, "byte clock get error %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_enable(&priv->byte_clk);
+	if (ret) {
+		dev_err(dev, "byte clock enable error %d\n", ret);
+		return ret;
+	}
+
+	ret = generic_phy_get_by_name(dev, "dphy", &priv->phy);
+	if (ret) {
+		dev_err(dev, "failed to get phy: %d\n", ret);
+		clk_disable(&priv->byte_clk);
+		return ret;
+	}
+
+	return ret;
+}
+
+static int dw_dsi_imx_remove(struct udevice *dev)
+{
+	struct dw_dsi_imx_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	if (priv->panel)
+		device_remove(priv->panel, DM_REMOVE_NORMAL);
+
+	ret = dsi_host_disable(priv->dsi_host);
+	if (ret < 0 && ret != -ENOSYS)
+		dev_err(dev, "failed to disable mipi dsi host\n");
+
+	ret = generic_phy_power_off(&priv->phy);
+	if (ret < 0)
+		dev_err(dev, "failed to power off phy: %d\n", ret);
+
+	ret = generic_phy_exit(&priv->phy);
+	if (ret < 0)
+		dev_err(dev, "failed to exit phy: %d\n", ret);
+
+	device_remove(priv->phy.dev, DM_REMOVE_NORMAL);
+
+	ret = clk_disable(&priv->byte_clk);
+	if (ret)
+		dev_err(dev, "byte clock disable error %d\n", ret);
+
+	return 0;
+}
+
+struct video_bridge_ops dw_dsi_imx_ops = {
+	.attach = dw_dsi_imx_attach,
+	.set_backlight = dw_dsi_imx_set_backlight,
+	.check_timing = dw_dsi_imx_check_timing,
+};
+
+static const struct udevice_id dw_dsi_imx_ids[] = {
+	{ .compatible = "fsl,imx93-mipi-dsi" },
+	{ }
+};
+
+U_BOOT_DRIVER(dw_dsi_imx) = {
+	.name				= "dw_dsi_imx",
+	.id					= UCLASS_VIDEO_BRIDGE,
+	.of_match			= dw_dsi_imx_ids,
+	.bind				= dm_scan_fdt_dev,
+	.remove				= dw_dsi_imx_remove,
+	.probe				= dw_dsi_imx_probe,
+	.ops				= &dw_dsi_imx_ops,
+	.priv_auto			= sizeof(struct dw_dsi_imx_priv),
+};
diff --git a/drivers/video/nxp/imx/hdmi/Makefile b/drivers/video/nxp/imx/hdmi/Makefile
new file mode 100644
index 00000000000..40942da3a40
--- /dev/null
+++ b/drivers/video/nxp/imx/hdmi/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2017-2018 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-$(CONFIG_VIDEO_IMX_HDP_LOAD) += hdp_load.o hdprx_load.o
+obj-$(CONFIG_VIDEO_IMX8M_HDMI) += imx8m_hdmi.o
diff --git a/drivers/video/nxp/imx/hdmi/hdp.c b/drivers/video/nxp/imx/hdmi/hdp.c
new file mode 100644
index 00000000000..d84716ac63d
--- /dev/null
+++ b/drivers/video/nxp/imx/hdmi/hdp.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/mach-imx/video.h>
+#include <asm/arch/video_common.h>
+#include <imx8_hdmi.h>
+
+int do_hdp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	if (argc < 2)
+		return 0;
+
+	if (strncmp(argv[1], "colorbar", 8) == 0) {
+		GraphicDevice *gdev;
+		struct video_mode_settings *vm;
+
+		gdev = imx8m_get_gd();
+		vm = imx8m_get_gmode();
+		imx8m_show_gmode();
+
+		imx8m_create_color_bar(
+			(void *)((uint64_t)gdev->frameAdrs),
+			vm);
+		printf("colorbar test\n");
+	} else if (strncmp(argv[1], "stop", 4) == 0) {
+		imx8_hdmi_disable();
+		printf("stopping hdmi\n");
+	} else {
+		printf("test error argc %d\n", argc);
+	}
+
+	return 0;
+}
+/***************************************************/
+
+U_BOOT_CMD(
+	hdp,  CONFIG_SYS_MAXARGS, 1, do_hdp,
+	"hdmi/dp display test commands",
+	"[<command>] ...\n"
+	"colorbar - display a colorbar pattern\n"
+	);
diff --git a/drivers/video/nxp/imx/hdmi/hdp_load.c b/drivers/video/nxp/imx/hdmi/hdp_load.c
new file mode 100644
index 00000000000..be6b118e39f
--- /dev/null
+++ b/drivers/video/nxp/imx/hdmi/hdp_load.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/global_data.h>
+
+#include "API_General.h"
+#include "scfw_utils.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ON  1
+#define OFF 0
+
+static void display_set_power(int onoff)
+{
+	SC_PM_SET_RESOURCE_POWER_MODE(-1, SC_R_DC_0, onoff);
+	SC_PM_SET_RESOURCE_POWER_MODE(-1, SC_R_HDMI, onoff);
+}
+
+static void display_set_clocks(void)
+{
+	const sc_pm_clock_rate_t pll = 800000000;
+	const sc_pm_clock_rate_t hdmi_core_clock = pll / 4; /* 200 Mhz */
+	const sc_pm_clock_rate_t hdmi_bus_clock = pll / 8;  /* 100 Mhz */
+
+	SC_PM_SET_RESOURCE_POWER_MODE(-1,
+				      SC_R_HDMI_PLL_0, SC_PM_PW_MODE_OFF);
+	SC_PM_SET_CLOCK_RATE(-1,
+			     SC_R_HDMI_PLL_0, SC_PM_CLK_PLL, pll);
+	SC_PM_SET_RESOURCE_POWER_MODE(-1,
+				      SC_R_HDMI_PLL_0, SC_PM_PW_MODE_ON);
+
+	/* HDMI DI Bus Clock  */
+	SC_PM_SET_CLOCK_RATE(-1,
+			     SC_R_HDMI, SC_PM_CLK_MISC4, hdmi_bus_clock);
+	/* HDMI DI Core Clock  */
+	SC_PM_SET_CLOCK_RATE(-1,
+			     SC_R_HDMI, SC_PM_CLK_MISC2, hdmi_core_clock);
+}
+
+static void display_enable_clocks(int enable)
+{
+	SC_PM_CLOCK_ENABLE(-1, SC_R_HDMI_PLL_0, SC_PM_CLK_PLL, enable);
+	SC_PM_CLOCK_ENABLE(-1, SC_R_HDMI, SC_PM_CLK_MISC2, enable);
+	SC_PM_CLOCK_ENABLE(-1, SC_R_HDMI, SC_PM_CLK_MISC4, enable);
+	if (enable == OFF)
+		SC_PM_SET_RESOURCE_POWER_MODE(-1,
+				SC_R_HDMI_PLL_0, SC_PM_PW_MODE_OFF);
+}
+
+int do_hdp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	if (argc < 2)
+		return 0;
+
+	if (strncmp(argv[1], "tracescfw", 9) == 0) {
+		g_debug_scfw = 1;
+		printf("Enabled SCFW API tracing\n");
+	} else if (strncmp(argv[1], "load", 4) == 0) {
+		unsigned long address = 0;
+		unsigned long offset  = 0x2000;
+		const int iram_size   = 0x10000;
+		const int dram_size   = 0x8000;
+		const char *s;
+
+		if (argc > 2) {
+			address = simple_strtoul(argv[2], NULL, 0);
+			if (argc > 3)
+				offset = simple_strtoul(argv[3], NULL, 0);
+		} else {
+			printf("Missing address\n");
+		}
+
+		printf("Loading hdp firmware from 0x%016lx offset 0x%016lx\n",
+		       address, offset);
+		display_set_power(SC_PM_PW_MODE_ON);
+		display_set_clocks();
+		display_enable_clocks(ON);
+		cdn_api_loadfirmware((unsigned char *)(address + offset),
+				     iram_size,
+				     (unsigned char *)(address + offset +
+						       iram_size),
+				     dram_size);
+
+		s = env_get("hdp_authenticate_fw");
+		if (s && !strcmp(s, "yes"))
+			SC_MISC_AUTH(-1, SC_SECO_AUTH_HDMI_TX_FW, 0);
+
+		display_enable_clocks(OFF);
+		printf("Loading hdp firmware Complete\n");
+
+		/* do not turn off hdmi power or firmware load will be lost */
+	} else {
+		printf("test error argc %d\n", argc);
+	}
+
+	return 0;
+}
+
+/***************************************************/
+U_BOOT_CMD(
+	hdp,  CONFIG_SYS_MAXARGS, 1, do_hdp,
+	"load hdmi firmware ",
+	"[<command>] ...\n"
+	"hdpload [address] [<offset>]\n"
+	"        address - address where the binary image starts\n"
+	"        <offset> - IRAM offset in the binary image (8192 default)\n"
+	"\n"
+	"        if \"hdp_authenticate_fw\" is set to \"yes\", the seco\n"
+	"        will authenticate the firmware and load HDCP keys.\n"
+	"\n"
+	"tracescfw - Trace SCFW API calls for video commands\n"
+	);
diff --git a/drivers/video/nxp/imx/hdmi/hdprx_load.c b/drivers/video/nxp/imx/hdmi/hdprx_load.c
new file mode 100644
index 00000000000..a1b332ff467
--- /dev/null
+++ b/drivers/video/nxp/imx/hdmi/hdprx_load.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/global_data.h>
+
+#include "API_General.h"
+#include "scfw_utils.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ON  1
+#define OFF 0
+
+static void hdmi_rx_set_power(int onoff)
+{
+	SC_PM_SET_RESOURCE_POWER_MODE(-1, SC_R_ISI_CH0, onoff);
+	SC_PM_SET_RESOURCE_POWER_MODE(-1, SC_R_HDMI_RX, onoff);
+	SC_PM_SET_RESOURCE_POWER_MODE(-1, SC_R_HDMI_RX_BYPASS, onoff);
+}
+
+int do_hdprx(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	if (argc < 2)
+		return 0;
+
+	if (strncmp(argv[1], "tracescfw", 9) == 0) {
+		g_debug_scfw = 1;
+		printf("Enabled SCFW API tracing\n");
+	} else if (strncmp(argv[1], "load", 4) == 0) {
+		unsigned long address = 0;
+		unsigned long offset  = 0x2000;
+		const int iram_size   = 0x10000;
+		const int dram_size   = 0x8000;
+		const char *s;
+
+		if (argc > 2) {
+			address = simple_strtoul(argv[2], NULL, 0);
+			if (argc > 3)
+				offset = simple_strtoul(argv[3], NULL, 0);
+		} else {
+			printf("Missing address\n");
+		}
+
+		printf("Loading hdprx firmware from 0x%016lx offset 0x%016lx\n",
+		       address, offset);
+		hdmi_rx_set_power(SC_PM_PW_MODE_ON);
+		hdp_rx_loadfirmware((unsigned char *)(address + offset),
+				    iram_size,
+				    (unsigned char *)(address + offset +
+						      iram_size),
+				    dram_size);
+
+		s = env_get("hdprx_authenticate_fw");
+		if (s && !strcmp(s, "yes"))
+			SC_MISC_AUTH(-1, SC_SECO_AUTH_HDMI_RX_FW, 0);
+		printf("Loading hdp rx firmware Complete\n");
+		/* do not turn off hdmi power or firmware load will be lost */
+	} else {
+		printf("test error argc %d\n", argc);
+	}
+
+	return 0;
+}
+
+/***************************************************/
+U_BOOT_CMD(
+	hdprx,  CONFIG_SYS_MAXARGS, 1, do_hdprx,
+	"load hdmi rx firmware ",
+	"[<command>] ...\n"
+	"hdpload [address] [<offset>]\n"
+	"        address - address where the binary image starts\n"
+	"        <offset> - IRAM offset in the binary image (8192 default)\n"
+	"\n"
+	"        if \"hdprx_authenticate_fw\" is set to \"yes\", the seco\n"
+	"        will authenticate the firmware and load HDCP keys.\n"
+	"\n"
+	"tracescfw - Trace SCFW API calls for video commands\n"
+	);
diff --git a/drivers/video/nxp/imx/hdmi/imx8m_hdmi.c b/drivers/video/nxp/imx/hdmi/imx8m_hdmi.c
new file mode 100644
index 00000000000..fb069d2ed57
--- /dev/null
+++ b/drivers/video/nxp/imx/hdmi/imx8m_hdmi.c
@@ -0,0 +1,310 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <display.h>
+#include <video.h>
+#include <asm/io.h>
+#include <dm/device-internal.h>
+#include <linux/iopoll.h>
+#include <clk.h>
+#include <video_link.h>
+
+#include "API_General.h"
+#include "vic_table.h"
+#include "API_HDMITX.h"
+#include "apb_cfg.h"
+#include "externs.h"
+#include "API_AVI.h"
+#include "address.h"
+#include "source_car.h"
+#include "source_phy.h"
+#include "API_AFE.h"
+#include "source_vif.h"
+#include "general_handler.h"
+#include "mhl_hdtx_top.h"
+#include "API_AFE_t28hpc_hdmitx.h"
+
+struct imx8m_hdmi_priv {
+	fdt_addr_t base;
+	struct display_timing timings;
+	int vic;
+	bool hpol;
+	bool vpol;
+};
+
+static int imx8m_hdmi_set_vic_mode(int vic,
+				  struct imx8m_hdmi_priv *priv)
+{
+	uint32_t pixel_clock_kHz;
+	uint32_t frame_rate_Hz;
+	uint32_t frame_rate_frac_Hz;
+	uint32_t cea_vic;
+	char iflag;
+
+	if (vic >= VIC_MODE_COUNT) {
+		debug("%s(): unsupported VIC\n", __func__);
+		return -1;
+	}
+
+	priv->timings.hfront_porch.typ = vic_table[vic][FRONT_PORCH];
+	priv->timings.hback_porch.typ = vic_table[vic][BACK_PORCH];
+	priv->timings.hsync_len.typ = vic_table[vic][HSYNC];
+	priv->timings.vfront_porch.typ = vic_table[vic][TYPE_EOF];
+	priv->timings.vback_porch.typ = vic_table[vic][SOF];
+	priv->timings.vsync_len.typ = vic_table[vic][VSYNC];
+	priv->timings.hactive.typ = vic_table[vic][H_ACTIVE];
+	priv->timings.vactive.typ = vic_table[vic][V_ACTIVE];
+
+	priv->hpol = vic_table[vic][HSYNC_POL] != 0;
+	priv->vpol = vic_table[vic][VSYNC_POL] != 0;
+
+	cea_vic = vic_table[vic][VIC];
+	if (vic_table[vic][I_P] != 0)
+		iflag = 'i';
+	else
+		iflag = 'p';
+	pixel_clock_kHz    = vic_table[vic][PIXEL_FREQ_KHZ];
+	frame_rate_Hz      = vic_table[vic][V_FREQ_HZ] * 1000;
+	frame_rate_frac_Hz = frame_rate_Hz % 1000;
+	frame_rate_Hz      /= 1000;
+
+	priv->timings.pixelclock.typ = pixel_clock_kHz * 1000;
+
+	debug("Cadence VIC %3d, CEA VIC %3d: %4d x %4d %c @ %3d.%03d [%6d kHz] Vpol=%d Hpol=%d\n",
+	      vic, cea_vic, priv->timings.hactive.typ, priv->timings.vactive.typ, iflag, frame_rate_Hz,
+	      frame_rate_frac_Hz, pixel_clock_kHz, priv->vpol, priv->hpol);
+
+	debug(" mode timing fp sync bp h:%3d %3d %3d v:%3d %3d %3d\n",
+	      priv->timings.hfront_porch.typ, priv->timings.hsync_len.typ, priv->timings.hback_porch.typ,
+	      priv->timings.vfront_porch.typ, priv->timings.vsync_len.typ, priv->timings.vback_porch.typ);
+
+	return 0;
+}
+
+static int imx8m_hdmi_init(int vic,
+			  int encoding,
+			  int color_depth,
+			  bool pixel_clk_from_phy)
+{
+	int ret;
+	uint32_t character_freq_khz;
+
+	uint8_t echo_msg[] = "echo test";
+	uint8_t echo_resp[sizeof(echo_msg) + 1];
+
+	/*================================================================== */
+	/* Parameterization: */
+	/*================================================================== */
+
+	/* VIC Mode - index from vic_table (see API_SRC/vic_table.c) */
+	VIC_MODES vic_mode = vic;
+
+	/* Pixel Encodeing Format */
+	/*   PXL_RGB = 0x1, */
+	/*   YCBCR_4_4_4 = 0x2, */
+	/*   YCBCR_4_2_2 = 0x4, */
+	/*   YCBCR_4_2_0 = 0x8, */
+	/*   Y_ONLY = 0x10, */
+	VIC_PXL_ENCODING_FORMAT format = encoding;
+	/*VIC_PXL_ENCODING_FORMAT format = 1; */
+
+	/* B/W Balance Type: 0 no data, 1 IT601, 2 ITU709 */
+	BT_TYPE bw_type = 0;
+
+	/* bpp (bits per subpixel) - 8 24bpp, 10 30bpp, 12 36bpp, 16 48bpp */
+	uint8_t bps = color_depth;
+
+	/* Set HDMI TX Mode */
+	/* Mode = 0 - DVI, 1 - HDMI1.4, 2 HDMI 2.0 */
+	HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE ptype = 1;
+
+	if (vic_mode == VIC_MODE_97_60Hz)
+		ptype = 2;
+
+	/*================================================================== */
+	/* Parameterization done */
+	/*================================================================== */
+	cdn_api_init();
+	debug("CDN_API_Init completed\n");
+
+	ret = cdn_api_checkalive();
+	debug("CDN_API_CheckAlive returned ret = %d\n", ret);
+
+	if (ret)
+		return -EPERM;
+
+	ret = cdn_api_general_test_echo_ext_blocking(echo_msg,
+						     echo_resp,
+						     sizeof(echo_msg),
+						     CDN_BUS_TYPE_APB);
+	debug("_General_Test_Echo_Ext_blocking - (ret = %d echo_resp = %s)\n",
+	      ret, echo_resp);
+
+	/* Configure PHY */
+	character_freq_khz = phy_cfg_t28hpc(4, vic_mode, bps,
+					    format, pixel_clk_from_phy);
+	debug("phy_cfg_t28hpc (character_freq_mhz = %d)\n",
+	      character_freq_khz);
+
+	hdmi_tx_t28hpc_power_config_seq(4);
+
+	/* Set the lane swapping */
+	ret = cdn_api_general_write_register_blocking
+		(ADDR_SOURCD_PHY + (LANES_CONFIG << 2),
+		 F_SOURCE_PHY_LANE0_SWAP(0) | F_SOURCE_PHY_LANE1_SWAP(1) |
+		 F_SOURCE_PHY_LANE2_SWAP(2) | F_SOURCE_PHY_LANE3_SWAP(3) |
+		 F_SOURCE_PHY_COMB_BYPASS(0) | F_SOURCE_PHY_20_10(1));
+
+	debug("_General_Write_Register_blocking LANES_CONFIG ret = %d\n", ret);
+
+	ret = CDN_API_HDMITX_Init_blocking();
+	debug("CDN_API_STATUS CDN_API_HDMITX_Init_blocking  ret = %d\n", ret);
+
+	ret = CDN_API_HDMITX_Init_blocking();
+	debug("CDN_API_STATUS CDN_API_HDMITX_Init_blocking  ret = %d\n", ret);
+
+	ret = CDN_API_HDMITX_Set_Mode_blocking(ptype, character_freq_khz);
+	debug("CDN_API_HDMITX_Set_Mode_blocking ret = %d\n", ret);
+
+	ret = cdn_api_set_avi(vic_mode, format, bw_type);
+	debug("cdn_api_set_avi  ret = %d\n", ret);
+
+	ret =  CDN_API_HDMITX_SetVic_blocking(vic_mode, bps, format);
+	debug("CDN_API_HDMITX_SetVic_blocking ret = %d\n", ret);
+
+
+	udelay(20000);
+
+	return 0;
+}
+
+static int imx8m_hdmi_update_timings(struct udevice *dev)
+{
+	struct imx8m_hdmi_priv *priv = dev_get_priv(dev);
+
+	/* map the resolution to a VIC index in the vic table*/
+	if ((priv->timings.hactive.typ == 1280) && (priv->timings.vactive.typ == 720))
+		priv->vic = 1; /* 720p60 */
+	else if ((priv->timings.hactive.typ == 1920) && (priv->timings.vactive.typ == 1080))
+		priv->vic = 2; /* 1080p60 */
+	else if ((priv->timings.hactive.typ == 3840) && (priv->timings.vactive.typ == 2160))
+		priv->vic = 3; /* 2160p60 */
+	else
+		priv->vic = 0; /* 480p60 */
+
+	return imx8m_hdmi_set_vic_mode(priv->vic, priv);
+}
+
+static void imx8m_hdmi_disable(void)
+{
+	int ret;
+	GENERAL_READ_REGISTER_RESPONSE resp;
+
+	resp.val = 0;
+	ret = cdn_api_general_read_register_blocking(ADDR_SOURCE_MHL_HD +
+						     (HDTX_CONTROLLER << 2),
+						     &resp);
+	if (ret != CDN_OK) {
+		printf("%s(): dn_api_general_read_register_blocking failed\n",
+		       __func__);
+	}
+
+	resp.val &= ~F_DATA_EN(1); /* disable HDMI */
+
+	ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD +
+						      (HDTX_CONTROLLER << 2),
+						      resp.val);
+	if (ret != CDN_OK) {
+		printf("%s(): dn_api_general_write_register_blocking failed\n",
+		       __func__);
+		return;
+	}
+}
+
+static int imx8m_hdmi_read_timing(struct udevice *dev, struct display_timing *timing)
+{
+	struct imx8m_hdmi_priv *priv = dev_get_priv(dev);
+
+	if (timing) {
+		memcpy(timing, &priv->timings, sizeof(struct display_timing));
+
+		if (priv->hpol)
+			timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
+
+		if (priv->vpol)
+			timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
+
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
+static int imx8m_hdmi_enable(struct udevice *dev, int panel_bpp,
+		      const struct display_timing *timing)
+{
+	struct imx8m_hdmi_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = imx8m_hdmi_init(priv->vic, 1, 8, true);
+	if (ret) {
+		printf("HDMI enable failed, ret %d!\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int imx8m_hdmi_probe(struct udevice *dev)
+{
+	struct imx8m_hdmi_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	priv->base = dev_read_addr(dev);
+	if (priv->base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	ret = video_link_get_display_timings(&priv->timings);
+	if (ret) {
+		printf("decode display timing error %d\n", ret);
+		return ret;
+	}
+
+	imx8m_hdmi_update_timings(dev);
+
+	return 0;
+}
+
+static int imx8m_hdmi_remove(struct udevice *dev)
+{
+	imx8m_hdmi_disable();
+
+	return 0;
+}
+
+struct dm_display_ops imx8m_hdmi_ops = {
+	.read_timing =  imx8m_hdmi_read_timing,
+	.enable =  imx8m_hdmi_enable,
+};
+
+static const struct udevice_id  imx8m_hdmi_ids[] = {
+	{ .compatible = "fsl,imx8mq-hdmi" },
+	{ }
+};
+
+U_BOOT_DRIVER( imx8m_hdmi) = {
+	.name				= " imx8m_hdmi",
+	.id				= UCLASS_DISPLAY,
+	.of_match			=  imx8m_hdmi_ids,
+	.bind				= dm_scan_fdt_dev,
+	.probe				=  imx8m_hdmi_probe,
+	.remove				= imx8m_hdmi_remove,
+	.ops				= & imx8m_hdmi_ops,
+	.priv_auto		= sizeof(struct  imx8m_hdmi_priv),
+};
diff --git a/drivers/video/nxp/imx/hdmi/scfw_utils.h b/drivers/video/nxp/imx/hdmi/scfw_utils.h
new file mode 100644
index 00000000000..f7f7bd4eee0
--- /dev/null
+++ b/drivers/video/nxp/imx/hdmi/scfw_utils.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef _SCFW_UTILS_H_
+#define _SCFW_UTILS_H_
+
+#include <common.h>
+#include <asm/arch/sci/sci.h>
+
+static int g_debug_scfw;	/* set to one to turn on SCFW API tracing */
+
+#define SC_PM_SET_CLOCK_PARENT(__ipcHndl__, __res__, __clk__, __parent__) \
+do { \
+	char _res_str[]	= #__res__;\
+	char _clk_str[]	= #__clk__;\
+	int _ret;\
+	if (g_debug_scfw) \
+		printf("(%4d) sc_pm_set_clock_parent %s:%s -> %d\n",\
+		       __LINE__, _res_str, _clk_str, __parent__);\
+	_ret = sc_pm_set_clock_parent(__ipcHndl__,\
+		__res__, __clk__, __parent__);\
+	if (_ret) \
+		printf("(%d)>> sc_pm_set_clock_parent failed! %s:%s -> %d (error = %d)\n",\
+		       __LINE__, _res_str, _clk_str, __parent__, _ret);\
+} while (0)
+
+#define SC_PM_SET_CLOCK_RATE(__ipcHndl__, __res__, __clk__, __rate__) \
+do { \
+	char _res_str[]	= #__res__;\
+	char _clk_str[]	= #__clk__;\
+	int _ret;\
+	sc_pm_clock_rate_t _actual = __rate__;\
+	if (g_debug_scfw) \
+		printf("(%4d) sc_pm_set_clock_rate %s:%s -> %d\n",\
+		       __LINE__, _res_str, _clk_str,  __rate__);\
+	_ret = sc_pm_set_clock_rate(__ipcHndl__, __res__, __clk__, &_actual);\
+	if (_ret)\
+		printf("(%4d)>> sc_pm_set_clock_rate failed! %s:%s -> %d (error = %d)\n",\
+		       __LINE__, _res_str, _clk_str, __rate__, _ret);\
+	if (_actual != __rate__)\
+		printf("(%4d)>> Actual rate for %s:%s is %d instead of %d\n", \
+		       __LINE__, _res_str, _clk_str, _actual, __rate__);  \
+} while (0)
+
+#define SC_PM_CLOCK_ENABLE(__ipcHndl__, __res__, __clk__, __enable__) \
+do { \
+	char _res_str[]	= #__res__;\
+	char _clk_str[]	= #__clk__;\
+	int _ret;\
+	if (g_debug_scfw) \
+		printf("(%4d) sc_pm_clock_enable %s:%s -> %d\n",\
+		       __LINE__, _res_str, _clk_str, __enable__);\
+	_ret = sc_pm_clock_enable(__ipcHndl__,\
+				 __res__, __clk__, __enable__, false);\
+	if (_ret)\
+		printf("(%4d)>> sc_pm_clock_enable failed! %s:%s -> %d (error = %d)\n",\
+			__LINE__, _res_str, _clk_str, __enable__, _ret);\
+} while (0) \
+
+#define SC_MISC_SET_CONTROL(__ipcHndl__, __res__, __clk__, __value__) \
+do { \
+	char _res_str[]	= #__res__; \
+	char _clk_str[]	= #__clk__; \
+	int _ret; \
+	if (g_debug_scfw) \
+			printf("(%4d) sc_misc_set_control %s:%s -> %d\n",\
+			       __LINE__, _res_str, _clk_str, __value__);\
+	_ret = sc_misc_set_control(__ipcHndl__, \
+				 __res__, __clk__, __value__); \
+	if (_ret) \
+		printf("(%4d)>> sc_misc_set_control failed! %s:%s -> %d (error = %d)\n", \
+			__LINE__, _res_str, _clk_str, __value__, _ret); \
+} while (0)
+
+#define SC_PM_SET_RESOURCE_POWER_MODE(__ipcHndl__, __res__, __enable__) \
+do { \
+	char _res_str[]	= #__res__; \
+	int _ret; \
+	if (g_debug_scfw) \
+			printf("(%4d) sc_pm_set_resource_power_mode %s -> %d\n",\
+			       __LINE__, _res_str, __enable__);\
+	_ret = sc_pm_set_resource_power_mode(__ipcHndl__, __res__, __enable__);\
+	if (_ret) \
+		printf("(%4d)>> sc_pm_set_resource_power_mode failed! %s -> %d (error = %d)\n", \
+		       __LINE__, _res_str, __enable__, _ret);\
+} while (0)
+
+#define SC_MISC_AUTH(__ipcHndl__, __cmd__, __addr__) \
+do { \
+	int _ret; \
+	if (g_debug_scfw) \
+			printf("(%4d) sc_misc_seco_authenticate ->  cmd %d addr %d\n",\
+			       __LINE__, __cmd__, __addr__);\
+	_ret = sc_seco_authenticate(__ipcHndl__, __cmd__, __addr__); \
+	if (_ret) \
+		printf("(%4d)>> sc_misc_seco_authenticate cmd %d addr %d (error = %d)\n", \
+			__LINE__, __cmd__, __addr__, _ret); \
+} while (0)
+
+#endif /*_SCFW_UTILS_H_ */
diff --git a/drivers/video/nxp/imx/imx6sx_ldb.c b/drivers/video/nxp/imx/imx6sx_ldb.c
new file mode 100644
index 00000000000..5f6ff5d48d9
--- /dev/null
+++ b/drivers/video/nxp/imx/imx6sx_ldb.c
@@ -0,0 +1,219 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <display.h>
+#include <video.h>
+#include <video_bridge.h>
+#include <video_link.h>
+#include <asm/io.h>
+#include <dm/device-internal.h>
+#include <linux/iopoll.h>
+#include <linux/err.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK		(0x1 << 3)
+#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF1	(0x0 << 3)
+#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF2	(0x1 << 3)
+
+enum {
+	LVDS_BIT_MAP_SPWG,
+	LVDS_BIT_MAP_JEIDA,
+};
+
+static const char *ldb_bit_mappings[] = {
+	[LVDS_BIT_MAP_SPWG] = "spwg",
+	[LVDS_BIT_MAP_JEIDA] = "jeida",
+};
+
+struct imx6sx_ldb_priv {
+	struct regmap *gpr;
+	u32 data_width;
+	int data_map;
+	struct display_timing timings;
+
+};
+
+static int imx6sx_ldb_setup(struct udevice *dev, const struct display_timing *timing)
+{
+	struct imx6sx_ldb_priv *priv = dev_get_priv(dev);
+	struct udevice *video_dev;
+	u32 ctrl;
+
+	ctrl = IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+
+	if (priv->data_width == 18)
+		ctrl |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT;
+	else
+		ctrl |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
+
+	if (priv->data_map == LVDS_BIT_MAP_SPWG)
+		ctrl |= IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG;
+	else
+		ctrl |= IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
+
+	if (timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)
+		ctrl |= IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH;
+	else
+		ctrl |= IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW;
+
+	/* GPR6 */
+	regmap_write(priv->gpr, 0x18, ctrl);
+
+	/* GPR5 */
+	video_dev = video_link_get_video_device();
+	if (!video_dev) {
+		printf("Fail to find video device\n");
+		return -ENODEV;
+	}
+
+	if (dev_seq(video_dev) == 0) /* lcdif 1 */
+		regmap_update_bits(priv->gpr, 0x14,
+			IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK, IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF1);
+	else
+		regmap_update_bits(priv->gpr, 0x14,
+			IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK, IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF2);
+	return 0;
+}
+
+int imx6sx_ldb_read_timing(struct udevice *dev, struct display_timing *timing)
+{
+	struct imx6sx_ldb_priv *priv = dev_get_priv(dev);
+
+	if (dev->plat_ == NULL)
+		return -EINVAL;
+
+	if (timing) {
+		memcpy(timing, &priv->timings, sizeof(struct display_timing));
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
+int imx6sx_ldb_enable(struct udevice *dev, int panel_bpp,
+		      const struct display_timing *timing)
+{
+	int ret;
+
+	if (dev->plat_ == NULL)
+		return -EINVAL;
+
+	ret = imx6sx_ldb_setup(dev, timing);
+
+	return ret;
+}
+
+static int of_get_data_mapping(struct udevice *dev)
+{
+    const char *bm;
+    int i;
+
+    bm = dev_read_string(dev, "fsl,data-mapping");
+    if (bm == NULL)
+        return -EINVAL;
+
+    for (i = 0; i < ARRAY_SIZE(ldb_bit_mappings); i++)
+        if (!strcasecmp(bm, ldb_bit_mappings[i]))
+            return i;
+
+    return -EINVAL;
+}
+
+static int imx6sx_ldb_probe(struct udevice *dev)
+{
+	struct imx6sx_ldb_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	debug("%s\n", __func__);
+
+	if (dev->plat_ == NULL) {
+		priv->gpr = syscon_regmap_lookup_by_phandle(dev, "gpr");
+		if (IS_ERR(priv->gpr)) {
+			printf("fail to get gpr regmap\n");
+			return PTR_ERR(priv->gpr);
+		}
+	} else {
+
+		struct imx6sx_ldb_priv *parent_priv = dev_get_priv(dev->parent);
+
+		ret = dev_read_u32(dev, "fsl,data-width", &priv->data_width);
+		if (ret || (priv->data_width != 18 && priv->data_width != 24)) {
+			printf("data width not set or invalid\n");
+			return ret;
+		}
+
+		priv->data_map= of_get_data_mapping(dev);
+		if (priv->data_map < 0) {
+			printf("data map not set or invalid\n");
+			return priv->data_map;
+		}
+
+		priv->gpr = parent_priv->gpr;
+
+		ret = video_link_get_display_timings(&priv->timings);
+		if (ret) {
+			printf("decode display timing error %d\n", ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int imx6sx_ldb_bind(struct udevice *dev)
+{
+	ofnode lvds_ch_node;
+	int ret = 0;
+
+	lvds_ch_node = ofnode_find_subnode(dev_ofnode(dev), "lvds-channel@0");
+	if (ofnode_valid(lvds_ch_node)) {
+		ret = device_bind(dev, dev->driver, "lvds-channel@0", (void *)1,
+			lvds_ch_node, NULL);
+		if (ret)
+			printf("Error binding driver '%s': %d\n", dev->driver->name,
+				ret);
+	}
+
+	return ret;
+}
+
+static int imx6sx_ldb_remove(struct udevice *dev)
+{
+	struct imx6sx_ldb_priv *priv = dev_get_priv(dev);
+
+	debug("%s\n", __func__);
+
+	regmap_update_bits(priv->gpr, 0x18,
+			IOMUXC_GPR2_LVDS_CH0_MODE_MASK, IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED);
+
+	return 0;
+}
+
+struct dm_display_ops imx6sx_ldb_ops = {
+	.read_timing = imx6sx_ldb_read_timing,
+	.enable = imx6sx_ldb_enable,
+};
+
+static const struct udevice_id imx6sx_ldb_ids[] = {
+	{ .compatible = "fsl,imx6sx-ldb" },
+	{ }
+};
+
+U_BOOT_DRIVER(imx6sx_ldb) = {
+	.name				= "imx6sx_ldb",
+	.id				= UCLASS_DISPLAY,
+	.of_match			= imx6sx_ldb_ids,
+	.bind				= imx6sx_ldb_bind,
+	.probe				= imx6sx_ldb_probe,
+	.ops				= &imx6sx_ldb_ops,
+	.remove 			= imx6sx_ldb_remove,
+	.priv_auto		= sizeof(struct imx6sx_ldb_priv),
+};
diff --git a/drivers/video/nxp/imx/imx8_dc.c b/drivers/video/nxp/imx/imx8_dc.c
new file mode 100644
index 00000000000..8b76c96e0f5
--- /dev/null
+++ b/drivers/video/nxp/imx/imx8_dc.c
@@ -0,0 +1,419 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ */
+#include <common.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <env.h>
+#include <linux/err.h>
+#include <malloc.h>
+#include <video.h>
+#include <video_fb.h>
+#include <display.h>
+
+#include <asm/cache.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <panel.h>
+#include <video_bridge.h>
+#include <video_link.h>
+#include <clk.h>
+
+#include <asm/arch/sci/sci.h>
+#include <imxdpuv1.h>
+#include <imxdpuv1_registers.h>
+#include <imxdpuv1_events.h>
+#include <power-domain.h>
+#include <asm/arch/lpcg.h>
+
+#define FLAG_COMBO	BIT(1)
+
+struct imx8_dc_priv {
+	/*struct udevice *bridge;*/
+	struct udevice *panel;
+	struct udevice *disp_dev;
+	struct imxdpuv1_videomode mode;
+
+	u32 gpixfmt;
+	u32 dpu_id;
+	u32 disp_id;
+};
+
+static int imx8_dc_soc_setup(struct udevice *dev, sc_pm_clock_rate_t pixel_clock)
+{
+	int err, div = 0;
+	sc_rsrc_t dc_rsrc, pll_rsrc;
+	sc_pm_clock_rate_t pll_clk;
+	const int max_div = 255;
+	const sc_pm_clock_rate_t min_pll_clk = 650000000,
+		max_pll_clk = 1300000000;
+	const char *pll1_pd_name;
+	u32 dc_lpcg;
+	struct imx8_dc_priv *priv = dev_get_priv(dev);
+
+	int dc_id = priv->dpu_id;
+	int disp_id = priv->disp_id;
+	sc_pm_clk_t misc_clk;
+	sc_ctrl_t link_addr, link_enable, link_valid, sync;
+	struct power_domain pd;
+	int ret;
+
+	debug("%s, dc_id %d\n", __func__, dc_id);
+
+	if (dc_id == 0) {
+		dc_rsrc = SC_R_DC_0;
+		if (disp_id == 0)
+			pll_rsrc = SC_R_DC_0_PLL_0;
+		else
+			pll_rsrc = SC_R_DC_0_PLL_1;
+		pll1_pd_name = "dc0_pll1";
+		dc_lpcg = DC_0_LPCG;
+	} else {
+		dc_rsrc = SC_R_DC_1;
+		if (disp_id == 0)
+			pll_rsrc = SC_R_DC_1_PLL_0;
+		else
+			pll_rsrc = SC_R_DC_1_PLL_1;
+		pll1_pd_name = "dc1_pll1";
+		dc_lpcg = DC_1_LPCG;
+	}
+
+	if (disp_id == 0) {
+		misc_clk = SC_PM_CLK_MISC0;
+		link_addr = SC_C_PXL_LINK_MST1_ADDR;
+		link_enable = SC_C_PXL_LINK_MST1_ENB;
+		link_valid = SC_C_PXL_LINK_MST1_VLD;
+		sync = SC_C_SYNC_CTRL0;
+	} else {
+		misc_clk = SC_PM_CLK_MISC1;
+		link_addr = SC_C_PXL_LINK_MST2_ADDR;
+		link_enable = SC_C_PXL_LINK_MST2_ENB;
+		link_valid = SC_C_PXL_LINK_MST2_VLD;
+		sync = SC_C_SYNC_CTRL1;
+	}
+
+	if (!power_domain_lookup_name(pll1_pd_name, &pd)) {
+		ret = power_domain_on(&pd);
+		if (ret) {
+			printf("%s Power up failed! (error = %d)\n", pll1_pd_name, ret);
+			return -EIO;
+		}
+	} else {
+		printf("%s lookup failed!\n", pll1_pd_name);
+		return -EIO;
+	}
+
+	/* find an even divisor for PLL greater than PLL minimum */
+	do {
+		div += 2;
+		if (div > max_div)
+			break;
+		pll_clk = pixel_clock * div;
+		if (pll_clk > max_pll_clk)
+			pll_clk = max_pll_clk;
+	} while (pll_clk < min_pll_clk);
+
+	debug("\n dc_id %d disp_id %d pll_clk %d pixel_clock %d\n",
+	      dc_id, disp_id, pll_clk, pixel_clock);
+
+	err = sc_pm_set_clock_rate(-1, pll_rsrc, SC_PM_CLK_PLL, &pll_clk);
+	if (err) {
+		printf("PLL%d set clock rate failed! (error = %d)\n",
+		       disp_id, err);
+		return -EIO;
+	}
+
+	err = sc_pm_set_clock_parent(-1, dc_rsrc, misc_clk,
+				     (misc_clk == SC_PM_CLK_MISC0) ? 2 : 3);
+	if (err) {
+		printf("DISP%d set clock parent failed! (error = %d)\n",
+		       disp_id, err);
+		return -EIO;
+	}
+
+	err = sc_pm_set_clock_rate(-1, dc_rsrc, misc_clk, &pixel_clock);
+	if (err) {
+		printf("DISP%d set clock rate failed! (error = %d)\n",
+		       disp_id, err);
+		return -EIO;
+	}
+
+	err = sc_pm_clock_enable(-1, pll_rsrc, SC_PM_CLK_PLL, true, false);
+	if (err) {
+		printf("PLL%d clock enable failed! (error = %d)\n",
+		       disp_id, err);
+		return -EIO;
+	}
+
+	err = sc_pm_clock_enable(-1, dc_rsrc, misc_clk, true, false);
+	if (err) {
+		printf("DISP%d clock enable failed! (error = %d)\n",
+		       disp_id, err);
+		return -EIO;
+	}
+
+	lpcg_clock_on(dc_lpcg, disp_id);
+	while (!lpcg_is_clock_on(dc_lpcg, disp_id))
+		;
+
+	err = sc_misc_set_control(-1, dc_rsrc, SC_C_MODE, 0);
+	if (err) {
+		printf("DC%d Set control mode failed! (error = %d)\n",
+		       dc_rsrc, err);
+		return -EIO;
+	}
+
+	err = sc_misc_set_control(-1, dc_rsrc, link_addr, 0);
+	if (err) {
+		printf("DC Set control _MST%d_ADDR failed! (error = %d)\n",
+		       disp_id + 1, err);
+		return -EIO;
+	}
+
+	err = sc_misc_set_control(-1, dc_rsrc, link_enable, 1);
+	if (err) {
+		printf("DC Set control _MST%d_ENB failed! (error = %d)\n",
+		       disp_id + 1, err);
+		return -EIO;
+	}
+
+	err = sc_misc_set_control(-1, dc_rsrc, link_valid, 1);
+	if (err) {
+		printf("DC Set control _MST%d_VLD failed! (error = %d)\n",
+		       disp_id + 1, err);
+		return -EIO;
+	}
+
+	err = sc_misc_set_control(-1, dc_rsrc, sync, 1);
+	if (err) {
+		printf("DC Set control _SYNC_CTRL%d failed! (error = %d)\n",
+		       disp_id, err);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int imx8_dc_video_init(struct udevice *dev)
+{
+	imxdpuv1_channel_params_t channel;
+	imxdpuv1_layer_t layer;
+	struct imx8_dc_priv *priv = dev_get_priv(dev);
+	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+
+	int8_t imxdpuv1_id = priv->dpu_id;
+
+	debug("%s\n", __func__);
+
+	if (imxdpuv1_id != 0 || (imxdpuv1_id == 1 && !is_imx8qm())) {
+		printf("%s(): invalid imxdpuv1_id %d", __func__, imxdpuv1_id);
+		return -ENODEV;
+	}
+
+	imxdpuv1_init(imxdpuv1_id);
+	imxdpuv1_disp_enable_frame_gen(imxdpuv1_id, 0, IMXDPUV1_FALSE);
+	imxdpuv1_disp_enable_frame_gen(imxdpuv1_id, 1, IMXDPUV1_FALSE);
+
+	imxdpuv1_disp_setup_frame_gen(imxdpuv1_id, priv->disp_id,
+		(const struct imxdpuv1_videomode *)&priv->mode,
+		0x3ff, 0, 0, 1, IMXDPUV1_DISABLE);
+	imxdpuv1_disp_init(imxdpuv1_id, priv->disp_id);
+	imxdpuv1_disp_setup_constframe(imxdpuv1_id,
+		priv->disp_id, 0, 0, 0xff, 0); /* blue */
+
+	if (priv->disp_id == 0)
+		channel.common.chan = IMXDPUV1_CHAN_VIDEO_0;
+	else
+		channel.common.chan = IMXDPUV1_CHAN_VIDEO_1;
+	channel.common.src_pixel_fmt = priv->gpixfmt;
+	channel.common.dest_pixel_fmt = priv->gpixfmt;
+	channel.common.src_width = priv->mode.hlen;
+	channel.common.src_height = priv->mode.vlen;
+
+	channel.common.clip_width = 0;
+	channel.common.clip_height = 0;
+	channel.common.clip_top = 0;
+	channel.common.clip_left = 0;
+
+	channel.common.dest_width = priv->mode.hlen;
+	channel.common.dest_height = priv->mode.vlen;
+	channel.common.dest_top = 0;
+	channel.common.dest_left = 0;
+	channel.common.stride =
+		priv->mode.hlen * imxdpuv1_bytes_per_pixel(IMXDPUV1_PIX_FMT_BGRA32);
+	channel.common.disp_id = priv->disp_id;
+	channel.common.const_color = 0;
+	channel.common.use_global_alpha = 0;
+	channel.common.use_local_alpha = 0;
+	imxdpuv1_init_channel(imxdpuv1_id, &channel);
+
+	imxdpuv1_init_channel_buffer(imxdpuv1_id,
+		channel.common.chan,
+		priv->mode.hlen * imxdpuv1_bytes_per_pixel(IMXDPUV1_PIX_FMT_RGB32),
+		IMXDPUV1_ROTATE_NONE,
+		(dma_addr_t)plat->base,
+		0,
+		0);
+
+	layer.enable    = IMXDPUV1_TRUE;
+	layer.secondary = get_channel_blk(channel.common.chan);
+
+	if (priv->disp_id == 0) {
+		layer.stream    = IMXDPUV1_DISPLAY_STREAM_0;
+		layer.primary   = IMXDPUV1_ID_CONSTFRAME0;
+	} else {
+		layer.stream    = IMXDPUV1_DISPLAY_STREAM_1;
+		layer.primary   = IMXDPUV1_ID_CONSTFRAME1;
+	}
+
+	imxdpuv1_disp_setup_layer(
+		imxdpuv1_id, &layer, IMXDPUV1_LAYER_0, 1);
+	imxdpuv1_disp_set_layer_global_alpha(
+		imxdpuv1_id, IMXDPUV1_LAYER_0, 0xff);
+
+	imxdpuv1_disp_set_layer_position(
+		imxdpuv1_id, IMXDPUV1_LAYER_0, 0, 0);
+	imxdpuv1_disp_set_chan_position(
+		imxdpuv1_id, channel.common.chan, 0, 0);
+
+	imxdpuv1_disp_enable_frame_gen(imxdpuv1_id, priv->disp_id, IMXDPUV1_ENABLE);
+
+	debug("IMXDPU display start ...\n");
+
+	return 0;
+}
+
+static int imx8_dc_get_timings_from_display(struct udevice *dev,
+					   struct display_timing *timings)
+{
+	struct imx8_dc_priv *priv = dev_get_priv(dev);
+	int err;
+
+	priv->disp_dev = video_link_get_next_device(dev);
+	if (!priv->disp_dev ||
+		device_get_uclass_id(priv->disp_dev) != UCLASS_DISPLAY) {
+
+		printf("fail to find display device\n");
+		return -ENODEV;
+	}
+
+	debug("disp_dev %s\n", priv->disp_dev->name);
+
+	err = video_link_get_display_timings(timings);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static int imx8_dc_probe(struct udevice *dev)
+{
+	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct imx8_dc_priv *priv = dev_get_priv(dev);
+	ulong flag = dev_get_driver_data(dev);
+
+	struct display_timing timings;
+	u32 fb_start, fb_end;
+	int ret;
+
+	debug("%s() plat: base 0x%lx, size 0x%x\n",
+	       __func__, plat->base, plat->size);
+
+	priv->dpu_id = dev_seq(dev);
+
+	ret = imx8_dc_get_timings_from_display(dev, &timings);
+	if (ret)
+		return ret;
+
+	priv->mode.pixelclock = timings.pixelclock.typ;
+	priv->mode.hlen = timings.hactive.typ;
+	priv->mode.hbp = timings.hback_porch.typ;
+	priv->mode.hfp = timings.hfront_porch.typ;
+
+	priv->mode.vlen = timings.vactive.typ;
+	priv->mode.vbp = timings.vback_porch.typ;
+	priv->mode.vfp = timings.vfront_porch.typ;
+
+	priv->mode.hsync = timings.hsync_len.typ;
+	priv->mode.vsync = timings.vsync_len.typ;
+	priv->mode.flags = IMXDPUV1_MODE_FLAGS_HSYNC_POL | IMXDPUV1_MODE_FLAGS_VSYNC_POL | IMXDPUV1_MODE_FLAGS_DE_POL;
+
+	priv->gpixfmt = IMXDPUV1_PIX_FMT_BGRA32;
+
+	if (flag & FLAG_COMBO) /* QXP has one DC which contains 2 LVDS/MIPI_DSI combo */
+		priv->disp_id = dev_seq(priv->disp_dev->parent);
+	else
+		priv->disp_id = 1; /* QM has two DCs each contains one LVDS as secondary display output */
+	imx8_dc_soc_setup(dev, priv->mode.pixelclock);
+
+	debug("dpu %u, disp_id %u, pixelclock %u, hlen %u, vlen %u\n",
+		priv->dpu_id, priv->disp_id, priv->mode.pixelclock, priv->mode.hlen, priv->mode.vlen);
+
+
+	display_enable(priv->disp_dev, 32, NULL);
+
+
+	ret = imx8_dc_video_init(dev);
+	if (ret) {
+		dev_err(dev, "imx8_dc_video_init fail %d\n", ret);
+		return ret;
+	}
+
+	uc_priv->bpix = VIDEO_BPP32;
+	uc_priv->xsize = priv->mode.hlen;
+	uc_priv->ysize = priv->mode.vlen;
+
+	/* Enable dcache for the frame buffer */
+	fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
+	fb_end = plat->base + plat->size;
+	fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
+	mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
+					DCACHE_WRITEBACK);
+	video_set_flush_dcache(dev, true);
+
+	return ret;
+}
+
+static int imx8_dc_bind(struct udevice *dev)
+{
+	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+
+	/* Max size supported by LCDIF, because in bind, we can't probe panel */
+	plat->size = 1920 * 1080 *4;
+
+	return 0;
+}
+
+static int imx8_dc_remove(struct udevice *dev)
+{
+	struct imx8_dc_priv *priv = dev_get_priv(dev);
+
+	debug("%s\n", __func__);
+
+	imxdpuv1_disp_enable_frame_gen(priv->dpu_id,
+		priv->disp_id, IMXDPUV1_DISABLE);
+
+	return 0;
+}
+
+static const struct udevice_id imx8_dc_ids[] = {
+	{ .compatible = "fsl,imx8qm-dpu" },
+	{ .compatible = "fsl,imx8qxp-dpu", .data = FLAG_COMBO, },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(imx8_dc) = {
+	.name	= "imx8_dc",
+	.id	= UCLASS_VIDEO,
+	.of_match = imx8_dc_ids,
+	.bind	= imx8_dc_bind,
+	.probe	= imx8_dc_probe,
+	.remove = imx8_dc_remove,
+	.flags	= DM_FLAG_PRE_RELOC,
+	.priv_auto	= sizeof(struct imx8_dc_priv),
+};
diff --git a/drivers/video/nxp/imx/imx8_lvds.c b/drivers/video/nxp/imx/imx8_lvds.c
new file mode 100644
index 00000000000..d9162dbbc21
--- /dev/null
+++ b/drivers/video/nxp/imx/imx8_lvds.c
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <display.h>
+#include <video.h>
+#include <video_bridge.h>
+#include <video_link.h>
+#include <asm/io.h>
+#include <dm/device-internal.h>
+#include <linux/iopoll.h>
+#include <linux/err.h>
+#include <clk.h>
+
+#include <asm/arch/imx8_lvds.h>
+#include <asm/arch/imx8_mipi_dsi.h>
+#include <power-domain.h>
+#include <asm/arch/lpcg.h>
+#include <asm/arch/sci/sci.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#define FLAG_COMBO	BIT(1)
+
+#define LDB_PHY_OFFSET 0x1000
+#define MIPI_PHY_OFFSET 0x8000
+
+struct imx8_ldb_priv {
+	struct regmap *gpr;
+	struct udevice *conn_dev;
+	u32 ldb_id;
+	struct display_timing timings;
+};
+
+static int imx8_ldb_soc_setup(struct udevice *dev, sc_pm_clock_rate_t pixel_clock)
+{
+	int err;
+	sc_rsrc_t lvds_rsrc, mipi_rsrc;
+	const char *pd_name;
+	struct imx8_ldb_priv *priv = dev_get_priv(dev);
+	ulong flag = dev_get_driver_data(dev);
+	int lvds_id = priv->ldb_id;
+
+	struct power_domain pd;
+	int ret;
+
+	debug("%s\n", __func__);
+
+	if (lvds_id == 0) {
+		lvds_rsrc = SC_R_LVDS_0;
+		mipi_rsrc = SC_R_MIPI_0;
+		pd_name = "lvds0_power_domain";
+	} else {
+		lvds_rsrc = SC_R_LVDS_1;
+		mipi_rsrc = SC_R_MIPI_1;
+		pd_name = "lvds1_power_domain";
+	}
+	/* Power up LVDS */
+	if (!power_domain_lookup_name(pd_name, &pd)) {
+		ret = power_domain_on(&pd);
+		if (ret) {
+			printf("%s Power up failed! (error = %d)\n", pd_name, ret);
+			return -EIO;
+		}
+	} else {
+		printf("%s lookup failed!\n", pd_name);
+		return -EIO;
+	}
+
+	/* Setup clocks */
+	err = sc_pm_set_clock_rate(-1, lvds_rsrc, SC_PM_CLK_BYPASS, &pixel_clock);
+	if (err) {
+		printf("LVDS set rate SC_PM_CLK_BYPASS failed! (error = %d)\n", err);
+		return -EIO;
+	}
+
+	err = sc_pm_set_clock_rate(-1, lvds_rsrc, SC_PM_CLK_PER, &pixel_clock);
+	if (err) {
+		printf("LVDS set rate SC_PM_CLK_BYPASS failed! (error = %d)\n", err);
+		return -EIO;
+	}
+
+	err = sc_pm_set_clock_rate(-1, lvds_rsrc, SC_PM_CLK_PHY, &pixel_clock);
+	if (err) {
+		printf("LVDS set rate SC_PM_CLK_BYPASS failed! (error = %d)\n", err);
+		return -EIO;
+	}
+
+	if (flag & FLAG_COMBO) {
+		/* For QXP, there is only one DC, and two pixel links to each LVDS with a mux provided.
+		  * We connect LVDS0 to pixel link 0, lVDS1 to pixel link 1 from DC
+		  */
+
+		/* Configure to LVDS mode not MIPI DSI */
+		err = sc_misc_set_control(-1, mipi_rsrc, SC_C_MODE, 1);
+		if (err) {
+			printf("LVDS sc_misc_set_control SC_C_MODE failed! (error = %d)\n", err);
+			return -EIO;
+		}
+
+		/* Configure to LVDS mode with single channel */
+		err = sc_misc_set_control(-1, mipi_rsrc, SC_C_DUAL_MODE, 0);
+		if (err) {
+			printf("LVDS sc_misc_set_control SC_C_DUAL_MODE failed! (error = %d)\n", err);
+			return -EIO;
+		}
+
+		err = sc_misc_set_control(-1, mipi_rsrc, SC_C_PXL_LINK_SEL, lvds_id);
+		if (err) {
+			printf("LVDS sc_misc_set_control SC_C_PXL_LINK_SEL failed! (error = %d)\n", err);
+			return -EIO;
+		}
+	}
+
+	err = sc_pm_clock_enable(-1, lvds_rsrc, SC_PM_CLK_BYPASS, true, false);
+	if (err) {
+		printf("LVDS enable clock SC_PM_CLK_BYPASS failed! (error = %d)\n", err);
+		return -EIO;
+	}
+
+	err = sc_pm_clock_enable(-1, lvds_rsrc, SC_PM_CLK_PER, true, false);
+	if (err) {
+		printf("LVDS enable clock SC_PM_CLK_PER failed! (error = %d)\n", err);
+		return -EIO;
+	}
+
+	err = sc_pm_clock_enable(-1, lvds_rsrc, SC_PM_CLK_PHY, true, false);
+	if (err) {
+		printf("LVDS enable clock SC_PM_CLK_PHY failed! (error = %d)\n", err);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+void imx8_ldb_configure(struct udevice *dev)
+{
+	uint32_t mode;
+	uint32_t phy_setting;
+	struct imx8_ldb_priv *priv = dev_get_priv(dev);
+	ulong flag = dev_get_driver_data(dev);
+
+	if (flag & FLAG_COMBO) {
+		mode =
+			IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_MODE, LVDS_CTRL_CH0_MODE__DI0) |
+			IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_DATA_WIDTH, LVDS_CTRL_CH0_DATA_WIDTH__24BIT) |
+			IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_BIT_MAP, LVDS_CTRL_CH0_BIT_MAP__JEIDA);
+
+		phy_setting = 0x4 << 5 | 0x4 << 2 | 1 << 1 | 0x1;
+		regmap_write(priv->gpr, LDB_PHY_OFFSET + LVDS_PHY_CTRL, phy_setting);
+		regmap_write(priv->gpr, LDB_PHY_OFFSET + LVDS_CTRL, mode);
+		regmap_write(priv->gpr, LDB_PHY_OFFSET + MIPIv2_CSR_TX_ULPS, 0);
+		regmap_write(priv->gpr, LDB_PHY_OFFSET + MIPIv2_CSR_PXL2DPI, MIPI_CSR_PXL2DPI_24_BIT);
+
+		/* Power up PLL in MIPI DSI PHY */
+		regmap_write(priv->gpr, MIPI_PHY_OFFSET + DPHY_PD_PLL, 0);
+		regmap_write(priv->gpr, MIPI_PHY_OFFSET + DPHY_PD_TX, 0);
+	} else {
+		mode =
+			IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_MODE, LVDS_CTRL_CH0_MODE__DI0) |
+			IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_DATA_WIDTH, LVDS_CTRL_CH0_DATA_WIDTH__24BIT) |
+			IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_BIT_MAP, LVDS_CTRL_CH0_BIT_MAP__JEIDA) |
+			IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_10BIT_ENABLE, LVDS_CTRL_CH0_10BIT_ENABLE__10BIT) |
+			IMX_LVDS_SET_FIELD(LVDS_CTRL_DI0_DATA_WIDTH, LVDS_CTRL_DI0_DATA_WIDTH__USE_30BIT);
+
+		regmap_write(priv->gpr, LDB_PHY_OFFSET + LVDS_CTRL, mode);
+
+		phy_setting =
+			LVDS_PHY_CTRL_RFB_MASK |
+			LVDS_PHY_CTRL_CH0_EN_MASK |
+			(0 << LVDS_PHY_CTRL_M_SHIFT) |
+			(0x04 << LVDS_PHY_CTRL_CCM_SHIFT) |
+			(0x04 << LVDS_PHY_CTRL_CA_SHIFT);
+		regmap_write(priv->gpr, LDB_PHY_OFFSET + LVDS_PHY_CTRL, phy_setting);
+	}
+}
+
+int imx8_ldb_read_timing(struct udevice *dev, struct display_timing *timing)
+{
+	struct imx8_ldb_priv *priv = dev_get_priv(dev);
+
+	if (dev->plat_ == NULL)
+		return -EINVAL;
+
+	if (timing) {
+		memcpy(timing, &priv->timings, sizeof(struct display_timing));
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
+int imx8_ldb_enable(struct udevice *dev, int panel_bpp,
+		      const struct display_timing *timing)
+{
+	struct imx8_ldb_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	if (dev->plat_ == NULL) {
+		imx8_ldb_soc_setup(dev, timing->pixelclock.typ);
+		imx8_ldb_configure(dev);
+	} else {
+
+		display_enable(dev->parent, panel_bpp, &priv->timings);
+
+		if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
+			if (priv->conn_dev &&
+				device_get_uclass_id(priv->conn_dev) == UCLASS_VIDEO_BRIDGE) {
+				ret = video_bridge_set_backlight(priv->conn_dev, 80);
+				if (ret) {
+					dev_err(dev, "fail to set backlight\n");
+					return ret;
+				}
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int imx8_ldb_probe(struct udevice *dev)
+{
+	struct imx8_ldb_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	debug("%s\n", __func__);
+
+	if (dev->plat_ == NULL) {
+
+		priv->gpr = syscon_regmap_lookup_by_phandle(dev, "gpr");
+		if (IS_ERR(priv->gpr)) {
+			printf("fail to get gpr regmap\n");
+			return PTR_ERR(priv->gpr);
+		}
+
+		/* Require to add alias in DTB */
+		priv->ldb_id = dev_seq(dev);
+
+		debug("ldb_id %u\n", priv->ldb_id);
+	} else {
+		priv->conn_dev = video_link_get_next_device(dev);
+		if (!priv->conn_dev) {
+			debug("can't find next device in video link\n");
+		}
+
+		ret = video_link_get_display_timings(&priv->timings);
+		if (ret) {
+			printf("decode display timing error %d\n", ret);
+			return ret;
+		}
+
+		if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
+			if (priv->conn_dev &&
+				device_get_uclass_id(priv->conn_dev) == UCLASS_VIDEO_BRIDGE) {
+				ret = video_bridge_attach(priv->conn_dev);
+				if (ret) {
+					dev_err(dev, "fail to attach bridge\n");
+					return ret;
+				}
+
+				ret = video_bridge_set_active(priv->conn_dev, true);
+				if (ret) {
+					dev_err(dev, "fail to active bridge\n");
+					return ret;
+				}
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int imx8_ldb_bind(struct udevice *dev)
+{
+	ofnode lvds_ch_node;
+	int ret = 0;
+
+	lvds_ch_node = ofnode_find_subnode(dev_ofnode(dev), "lvds-channel@0");
+	if (ofnode_valid(lvds_ch_node)) {
+		ret = device_bind(dev, dev->driver, "lvds-channel@0", (void *)1,
+			lvds_ch_node, NULL);
+		if (ret)
+			printf("Error binding driver '%s': %d\n", dev->driver->name,
+				ret);
+	}
+
+	return ret;
+}
+
+struct dm_display_ops imx8_ldb_ops = {
+	.read_timing = imx8_ldb_read_timing,
+	.enable = imx8_ldb_enable,
+};
+
+static const struct udevice_id imx8_ldb_ids[] = {
+	{ .compatible = "fsl,imx8qm-ldb" },
+	{ .compatible = "fsl,imx8qxp-ldb", .data = FLAG_COMBO, },
+	{ }
+};
+
+U_BOOT_DRIVER(imx8_ldb) = {
+	.name				= "imx8_ldb",
+	.id				= UCLASS_DISPLAY,
+	.of_match			= imx8_ldb_ids,
+	.bind				= imx8_ldb_bind,
+	.probe				= imx8_ldb_probe,
+	.ops				= &imx8_ldb_ops,
+	.priv_auto		= sizeof(struct imx8_ldb_priv),
+};
diff --git a/drivers/video/nxp/imx/imx8m_dcss.c b/drivers/video/nxp/imx/imx8m_dcss.c
new file mode 100644
index 00000000000..6315471a900
--- /dev/null
+++ b/drivers/video/nxp/imx/imx8m_dcss.c
@@ -0,0 +1,534 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ */
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/device_compat.h>
+#include <env.h>
+#include <linux/errno.h>
+#include <malloc.h>
+#include <video.h>
+#include <video_fb.h>
+#include <display.h>
+
+#include <asm/cache.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <video_bridge.h>
+#include <clk.h>
+#include <video_link.h>
+
+#ifdef DEBUG
+#define reg32_write(addr, val) \
+do { \
+	debug("%s():%d 0x%08x -> 0x%08x\n", __func__, __LINE__, \
+	(unsigned int)addr, (unsigned int)val); \
+	__raw_writel(val, addr); \
+} while (0)
+#else
+#define reg32_write(addr, val) __raw_writel(val, addr)
+#endif
+
+#define reg32_read(addr) __raw_readl(addr)
+
+#define reg32setbit(addr, bitpos) \
+	reg32_write((addr), (reg32_read((addr)) | (1<<(bitpos))))
+#define reg32clearbit(addr, bitpos) \
+	reg32_write((addr), (reg32_read((addr)) & ~(1<<(bitpos))))
+
+#define reg32_read_tst(addr, val, mask) \
+do { \
+	u32 temp = reg32_read((addr)); \
+	if ((temp & (mask)) == ((val) & (mask))) \
+		debug("%s():%d 0x%08x -> 0x%08x\n", \
+			__func__, __LINE__, addr, val); \
+	else  \
+		debug("%s():%d 0x%08x -> 0x%08x instead of 0x%08x\n", \
+			__func__, __LINE__, addr, temp, val); \
+} while (0)
+
+
+struct imx8m_dcss_priv {
+	struct udevice *disp_dev;
+	struct display_timing timings;
+
+	bool hpol;		/* horizontal pulse polarity	*/
+	bool vpol;		/* vertical pulse polarity	*/
+	bool enabled;
+
+	fdt_addr_t addr;
+};
+
+__weak int imx8m_dcss_clock_init(u32 pixclk)
+{
+	return 0;
+}
+
+__weak int imx8m_dcss_power_init(void)
+{
+	return 0;
+}
+
+static void imx8m_dcss_reset(struct udevice *dev)
+{
+	struct imx8m_dcss_priv *priv = dev_get_priv(dev);
+	u32 temp;
+
+	/* DCSS reset */
+	reg32_write(priv->addr + 0x2f000, 0xffffffff);
+
+	/* DCSS clock selection */
+	reg32_write(priv->addr + 0x2f010, 0x1);
+	temp = reg32_read(priv->addr + 0x2f010);
+	debug("%s(): DCSS clock control 0x%08x\n", __func__, temp);
+}
+
+static void imx8m_dcss_init(struct udevice *dev)
+{
+	struct imx8m_dcss_priv *priv = dev_get_priv(dev);
+	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+
+	debug("%s() ...\n", __func__);
+
+	/* DTRC-CHAN2/3 */
+	reg32_write(priv->addr + 0x160c8, 0x00000002);
+	reg32_write(priv->addr + 0x170c8, 0x00000002);
+
+	/* CHAN1_DPR */
+	reg32_write(priv->addr + 0x180c0, (unsigned int)plat->base);
+	reg32_write(priv->addr + 0x18090, 0x00000002);
+	reg32_write(priv->addr + 0x180a0, priv->timings.hactive.typ);
+	reg32_write(priv->addr + 0x180b0, priv->timings.vactive.typ);
+	reg32_write(priv->addr + 0x18110,
+		    (unsigned int)plat->base + priv->timings.hactive.typ * priv->timings.vactive.typ);
+	reg32_write(priv->addr + 0x180f0, 0x00000280);
+	reg32_write(priv->addr + 0x18100, 0x000000f0);
+	reg32_write(priv->addr + 0x18070, ((priv->timings.hactive.typ * 4) << 16));
+	reg32_write(priv->addr + 0x18050, 0x000e4203);
+	reg32_write(priv->addr + 0x18050, 0x000e4203);
+	reg32_write(priv->addr + 0x18200, 0x00000038);
+	reg32_write(priv->addr + 0x18000, 0x00000004);
+	reg32_write(priv->addr + 0x18000, 0x00000005);
+
+	/* SCALER */
+	reg32_write(priv->addr + 0x1c008, 0x00000000);
+	reg32_write(priv->addr + 0x1c00c, 0x00000000);
+	reg32_write(priv->addr + 0x1c010, 0x00000002);
+	reg32_write(priv->addr + 0x1c014, 0x00000002);
+	reg32_write(priv->addr + 0x1c018,
+		    ((priv->timings.vactive.typ - 1) << 16 | (priv->timings.hactive.typ - 1)));
+	reg32_write(priv->addr + 0x1c01c,
+		    ((priv->timings.vactive.typ - 1) << 16 | (priv->timings.hactive.typ - 1)));
+	reg32_write(priv->addr + 0x1c020,
+		    ((priv->timings.vactive.typ - 1) << 16 | (priv->timings.hactive.typ - 1)));
+	reg32_write(priv->addr + 0x1c024,
+		    ((priv->timings.vactive.typ - 1) << 16 | (priv->timings.hactive.typ - 1)));
+	reg32_write(priv->addr + 0x1c028, 0x00000000);
+	reg32_write(priv->addr + 0x1c02c, 0x00000000);
+	reg32_write(priv->addr + 0x1c030, 0x00000000);
+	reg32_write(priv->addr + 0x1c034, 0x00000000);
+	reg32_write(priv->addr + 0x1c038, 0x00000000);
+	reg32_write(priv->addr + 0x1c03c, 0x00000000);
+	reg32_write(priv->addr + 0x1c040, 0x00000000);
+	reg32_write(priv->addr + 0x1c044, 0x00000000);
+	reg32_write(priv->addr + 0x1c048, 0x00000000);
+	reg32_write(priv->addr + 0x1c04c, 0x00002000);
+	reg32_write(priv->addr + 0x1c050, 0x00000000);
+	reg32_write(priv->addr + 0x1c054, 0x00002000);
+	reg32_write(priv->addr + 0x1c058, 0x00000000);
+	reg32_write(priv->addr + 0x1c05c, 0x00002000);
+	reg32_write(priv->addr + 0x1c060, 0x00000000);
+	reg32_write(priv->addr + 0x1c064, 0x00002000);
+	reg32_write(priv->addr + 0x1c080, 0x00000000);
+	reg32_write(priv->addr + 0x1c0c0, 0x00040000);
+	reg32_write(priv->addr + 0x1c100, 0x00000000);
+	reg32_write(priv->addr + 0x1c084, 0x00000000);
+	reg32_write(priv->addr + 0x1c0c4, 0x00000000);
+	reg32_write(priv->addr + 0x1c104, 0x00000000);
+	reg32_write(priv->addr + 0x1c088, 0x00000000);
+	reg32_write(priv->addr + 0x1c0c8, 0x00000000);
+	reg32_write(priv->addr + 0x1c108, 0x00000000);
+	reg32_write(priv->addr + 0x1c08c, 0x00000000);
+	reg32_write(priv->addr + 0x1c0cc, 0x00000000);
+	reg32_write(priv->addr + 0x1c10c, 0x00000000);
+	reg32_write(priv->addr + 0x1c090, 0x00000000);
+	reg32_write(priv->addr + 0x1c0d0, 0x00000000);
+	reg32_write(priv->addr + 0x1c110, 0x00000000);
+	reg32_write(priv->addr + 0x1c094, 0x00000000);
+	reg32_write(priv->addr + 0x1c0d4, 0x00000000);
+	reg32_write(priv->addr + 0x1c114, 0x00000000);
+	reg32_write(priv->addr + 0x1c098, 0x00000000);
+	reg32_write(priv->addr + 0x1c0d8, 0x00000000);
+	reg32_write(priv->addr + 0x1c118, 0x00000000);
+	reg32_write(priv->addr + 0x1c09c, 0x00000000);
+	reg32_write(priv->addr + 0x1c0dc, 0x00000000);
+	reg32_write(priv->addr + 0x1c11c, 0x00000000);
+	reg32_write(priv->addr + 0x1c0a0, 0x00000000);
+	reg32_write(priv->addr + 0x1c0e0, 0x00000000);
+	reg32_write(priv->addr + 0x1c120, 0x00000000);
+	reg32_write(priv->addr + 0x1c0a4, 0x00000000);
+	reg32_write(priv->addr + 0x1c0e4, 0x00000000);
+	reg32_write(priv->addr + 0x1c124, 0x00000000);
+	reg32_write(priv->addr + 0x1c0a8, 0x00000000);
+	reg32_write(priv->addr + 0x1c0e8, 0x00000000);
+	reg32_write(priv->addr + 0x1c128, 0x00000000);
+	reg32_write(priv->addr + 0x1c0ac, 0x00000000);
+	reg32_write(priv->addr + 0x1c0ec, 0x00000000);
+	reg32_write(priv->addr + 0x1c12c, 0x00000000);
+	reg32_write(priv->addr + 0x1c0b0, 0x00000000);
+	reg32_write(priv->addr + 0x1c0f0, 0x00000000);
+	reg32_write(priv->addr + 0x1c130, 0x00000000);
+	reg32_write(priv->addr + 0x1c0b4, 0x00000000);
+	reg32_write(priv->addr + 0x1c0f4, 0x00000000);
+	reg32_write(priv->addr + 0x1c134, 0x00000000);
+	reg32_write(priv->addr + 0x1c0b8, 0x00000000);
+	reg32_write(priv->addr + 0x1c0f8, 0x00000000);
+	reg32_write(priv->addr + 0x1c138, 0x00000000);
+	reg32_write(priv->addr + 0x1c0bc, 0x00000000);
+	reg32_write(priv->addr + 0x1c0fc, 0x00000000);
+	reg32_write(priv->addr + 0x1c13c, 0x00000000);
+	reg32_write(priv->addr + 0x1c140, 0x00000000);
+	reg32_write(priv->addr + 0x1c180, 0x00040000);
+	reg32_write(priv->addr + 0x1c1c0, 0x00000000);
+	reg32_write(priv->addr + 0x1c144, 0x00000000);
+	reg32_write(priv->addr + 0x1c184, 0x00000000);
+	reg32_write(priv->addr + 0x1c1c4, 0x00000000);
+	reg32_write(priv->addr + 0x1c148, 0x00000000);
+	reg32_write(priv->addr + 0x1c188, 0x00000000);
+	reg32_write(priv->addr + 0x1c1c8, 0x00000000);
+	reg32_write(priv->addr + 0x1c14c, 0x00000000);
+	reg32_write(priv->addr + 0x1c18c, 0x00000000);
+	reg32_write(priv->addr + 0x1c1cc, 0x00000000);
+	reg32_write(priv->addr + 0x1c150, 0x00000000);
+	reg32_write(priv->addr + 0x1c190, 0x00000000);
+	reg32_write(priv->addr + 0x1c1d0, 0x00000000);
+	reg32_write(priv->addr + 0x1c154, 0x00000000);
+	reg32_write(priv->addr + 0x1c194, 0x00000000);
+	reg32_write(priv->addr + 0x1c1d4, 0x00000000);
+	reg32_write(priv->addr + 0x1c158, 0x00000000);
+	reg32_write(priv->addr + 0x1c198, 0x00000000);
+	reg32_write(priv->addr + 0x1c1d8, 0x00000000);
+	reg32_write(priv->addr + 0x1c15c, 0x00000000);
+	reg32_write(priv->addr + 0x1c19c, 0x00000000);
+	reg32_write(priv->addr + 0x1c1dc, 0x00000000);
+	reg32_write(priv->addr + 0x1c160, 0x00000000);
+	reg32_write(priv->addr + 0x1c1a0, 0x00000000);
+	reg32_write(priv->addr + 0x1c1e0, 0x00000000);
+	reg32_write(priv->addr + 0x1c164, 0x00000000);
+	reg32_write(priv->addr + 0x1c1a4, 0x00000000);
+	reg32_write(priv->addr + 0x1c1e4, 0x00000000);
+	reg32_write(priv->addr + 0x1c168, 0x00000000);
+	reg32_write(priv->addr + 0x1c1a8, 0x00000000);
+	reg32_write(priv->addr + 0x1c1e8, 0x00000000);
+	reg32_write(priv->addr + 0x1c16c, 0x00000000);
+	reg32_write(priv->addr + 0x1c1ac, 0x00000000);
+	reg32_write(priv->addr + 0x1c1ec, 0x00000000);
+	reg32_write(priv->addr + 0x1c170, 0x00000000);
+	reg32_write(priv->addr + 0x1c1b0, 0x00000000);
+	reg32_write(priv->addr + 0x1c1f0, 0x00000000);
+	reg32_write(priv->addr + 0x1c174, 0x00000000);
+	reg32_write(priv->addr + 0x1c1b4, 0x00000000);
+	reg32_write(priv->addr + 0x1c1f4, 0x00000000);
+	reg32_write(priv->addr + 0x1c178, 0x00000000);
+	reg32_write(priv->addr + 0x1c1b8, 0x00000000);
+	reg32_write(priv->addr + 0x1c1f8, 0x00000000);
+	reg32_write(priv->addr + 0x1c17c, 0x00000000);
+	reg32_write(priv->addr + 0x1c1bc, 0x00000000);
+	reg32_write(priv->addr + 0x1c1fc, 0x00000000);
+	reg32_write(priv->addr + 0x1c300, 0x00000000);
+	reg32_write(priv->addr + 0x1c340, 0x00000000);
+	reg32_write(priv->addr + 0x1c380, 0x00000000);
+	reg32_write(priv->addr + 0x1c304, 0x00000000);
+	reg32_write(priv->addr + 0x1c344, 0x00000000);
+	reg32_write(priv->addr + 0x1c384, 0x00000000);
+	reg32_write(priv->addr + 0x1c308, 0x00000000);
+	reg32_write(priv->addr + 0x1c348, 0x00000000);
+	reg32_write(priv->addr + 0x1c388, 0x00000000);
+	reg32_write(priv->addr + 0x1c30c, 0x00000000);
+	reg32_write(priv->addr + 0x1c34c, 0x00000000);
+	reg32_write(priv->addr + 0x1c38c, 0x00000000);
+	reg32_write(priv->addr + 0x1c310, 0x00000000);
+	reg32_write(priv->addr + 0x1c350, 0x00000000);
+	reg32_write(priv->addr + 0x1c390, 0x00000000);
+	reg32_write(priv->addr + 0x1c314, 0x00000000);
+	reg32_write(priv->addr + 0x1c354, 0x00000000);
+	reg32_write(priv->addr + 0x1c394, 0x00000000);
+	reg32_write(priv->addr + 0x1c318, 0x00000000);
+	reg32_write(priv->addr + 0x1c358, 0x00000000);
+	reg32_write(priv->addr + 0x1c398, 0x00000000);
+	reg32_write(priv->addr + 0x1c31c, 0x00000000);
+	reg32_write(priv->addr + 0x1c35c, 0x00000000);
+	reg32_write(priv->addr + 0x1c39c, 0x00000000);
+	reg32_write(priv->addr + 0x1c320, 0x00000000);
+	reg32_write(priv->addr + 0x1c360, 0x00000000);
+	reg32_write(priv->addr + 0x1c3a0, 0x00000000);
+	reg32_write(priv->addr + 0x1c324, 0x00000000);
+	reg32_write(priv->addr + 0x1c364, 0x00000000);
+	reg32_write(priv->addr + 0x1c3a4, 0x00000000);
+	reg32_write(priv->addr + 0x1c328, 0x00000000);
+	reg32_write(priv->addr + 0x1c368, 0x00000000);
+	reg32_write(priv->addr + 0x1c3a8, 0x00000000);
+	reg32_write(priv->addr + 0x1c32c, 0x00000000);
+	reg32_write(priv->addr + 0x1c36c, 0x00000000);
+	reg32_write(priv->addr + 0x1c3ac, 0x00000000);
+	reg32_write(priv->addr + 0x1c330, 0x00000000);
+	reg32_write(priv->addr + 0x1c370, 0x00000000);
+	reg32_write(priv->addr + 0x1c3b0, 0x00000000);
+	reg32_write(priv->addr + 0x1c334, 0x00000000);
+	reg32_write(priv->addr + 0x1c374, 0x00000000);
+	reg32_write(priv->addr + 0x1c3b4, 0x00000000);
+	reg32_write(priv->addr + 0x1c338, 0x00000000);
+	reg32_write(priv->addr + 0x1c378, 0x00000000);
+	reg32_write(priv->addr + 0x1c3b8, 0x00000000);
+	reg32_write(priv->addr + 0x1c33c, 0x00000000);
+	reg32_write(priv->addr + 0x1c37c, 0x00000000);
+	reg32_write(priv->addr + 0x1c3bc, 0x00000000);
+	reg32_write(priv->addr + 0x1c200, 0x00000000);
+	reg32_write(priv->addr + 0x1c240, 0x00000000);
+	reg32_write(priv->addr + 0x1c280, 0x00000000);
+	reg32_write(priv->addr + 0x1c204, 0x00000000);
+	reg32_write(priv->addr + 0x1c244, 0x00000000);
+	reg32_write(priv->addr + 0x1c284, 0x00000000);
+	reg32_write(priv->addr + 0x1c208, 0x00000000);
+	reg32_write(priv->addr + 0x1c248, 0x00000000);
+	reg32_write(priv->addr + 0x1c288, 0x00000000);
+	reg32_write(priv->addr + 0x1c20c, 0x00000000);
+	reg32_write(priv->addr + 0x1c24c, 0x00000000);
+	reg32_write(priv->addr + 0x1c28c, 0x00000000);
+	reg32_write(priv->addr + 0x1c210, 0x00000000);
+	reg32_write(priv->addr + 0x1c250, 0x00000000);
+	reg32_write(priv->addr + 0x1c290, 0x00000000);
+	reg32_write(priv->addr + 0x1c214, 0x00000000);
+	reg32_write(priv->addr + 0x1c254, 0x00000000);
+	reg32_write(priv->addr + 0x1c294, 0x00000000);
+	reg32_write(priv->addr + 0x1c218, 0x00000000);
+	reg32_write(priv->addr + 0x1c258, 0x00000000);
+	reg32_write(priv->addr + 0x1c298, 0x00000000);
+	reg32_write(priv->addr + 0x1c21c, 0x00000000);
+	reg32_write(priv->addr + 0x1c25c, 0x00000000);
+	reg32_write(priv->addr + 0x1c29c, 0x00000000);
+	reg32_write(priv->addr + 0x1c220, 0x00000000);
+	reg32_write(priv->addr + 0x1c260, 0x00000000);
+	reg32_write(priv->addr + 0x1c2a0, 0x00000000);
+	reg32_write(priv->addr + 0x1c224, 0x00000000);
+	reg32_write(priv->addr + 0x1c264, 0x00000000);
+	reg32_write(priv->addr + 0x1c2a4, 0x00000000);
+	reg32_write(priv->addr + 0x1c228, 0x00000000);
+	reg32_write(priv->addr + 0x1c268, 0x00000000);
+	reg32_write(priv->addr + 0x1c2a8, 0x00000000);
+	reg32_write(priv->addr + 0x1c22c, 0x00000000);
+	reg32_write(priv->addr + 0x1c26c, 0x00000000);
+	reg32_write(priv->addr + 0x1c2ac, 0x00000000);
+	reg32_write(priv->addr + 0x1c230, 0x00000000);
+	reg32_write(priv->addr + 0x1c270, 0x00000000);
+	reg32_write(priv->addr + 0x1c2b0, 0x00000000);
+	reg32_write(priv->addr + 0x1c234, 0x00000000);
+	reg32_write(priv->addr + 0x1c274, 0x00000000);
+	reg32_write(priv->addr + 0x1c2b4, 0x00000000);
+	reg32_write(priv->addr + 0x1c238, 0x00000000);
+	reg32_write(priv->addr + 0x1c278, 0x00000000);
+	reg32_write(priv->addr + 0x1c2b8, 0x00000000);
+	reg32_write(priv->addr + 0x1c23c, 0x00000000);
+	reg32_write(priv->addr + 0x1c27c, 0x00000000);
+	reg32_write(priv->addr + 0x1c2bc, 0x00000000);
+	reg32_write(priv->addr + 0x1c2bc, 0x00000000);
+	reg32_write(priv->addr + 0x1c000, 0x00000011);
+
+	/* SUBSAM */
+	reg32_write(priv->addr + 0x1b070, 0x21612161);
+	reg32_write(priv->addr + 0x1b080, 0x03ff0000);
+	reg32_write(priv->addr + 0x1b090, 0x03ff0000);
+
+	reg32_write(priv->addr + 0x1b010,
+		    (((priv->timings.vfront_porch.typ + priv->timings.vback_porch.typ + priv->timings.vsync_len.typ +
+			priv->timings.vactive.typ -1) << 16) |
+		       (priv->timings.hfront_porch.typ + priv->timings.hback_porch.typ + priv->timings.hsync_len.typ +
+			priv->timings.hactive.typ - 1)));
+	reg32_write(priv->addr + 0x1b020,
+		    (((priv->timings.hsync_len.typ - 1) << 16) | priv->hpol << 31 | (priv->timings.hfront_porch.typ +
+			priv->timings.hback_porch.typ + priv->timings.hsync_len.typ + priv->timings.hactive.typ -1)));
+	reg32_write(priv->addr + 0x1b030,
+		    (((priv->timings.vfront_porch.typ + priv->timings.vsync_len.typ - 1) << 16) | priv->vpol << 31 | (priv->timings.vfront_porch.typ - 1)));
+	reg32_write(priv->addr + 0x1b040,
+		    ((1 << 31) | ((priv->timings.vsync_len.typ +priv->timings.vfront_porch.typ + priv->timings.vback_porch.typ) << 16) |
+		    (priv->timings.hsync_len.typ + priv->timings.hback_porch.typ - 1)));
+	reg32_write(priv->addr + 0x1b050,
+		    (((priv->timings.vsync_len.typ + priv->timings.vfront_porch.typ + priv->timings.vback_porch.typ + priv->timings.vactive.typ -1) << 16) |
+		    (priv->timings.hsync_len.typ + priv->timings.hback_porch.typ + priv->timings.hactive.typ - 1)));
+
+	/* subsample mode 0 bypass 444, 1 422, 2 420 */
+	reg32_write(priv->addr + 0x1b060, 0x0000000);
+
+	reg32_write(priv->addr + 0x1b000, 0x00000001);
+
+	/* DTG */
+	/*reg32_write(priv->addr + 0x20000, 0xff000484); */
+	/* disable local alpha */
+	reg32_write(priv->addr + 0x20000, 0xff005084);
+	reg32_write(priv->addr + 0x20004,
+		    (((priv->timings.vfront_porch.typ + priv->timings.vback_porch.typ + priv->timings.vsync_len.typ + priv->timings.vactive.typ -
+		       1) << 16) | (priv->timings.hfront_porch.typ + priv->timings.hback_porch.typ + priv->timings.hsync_len.typ +
+			priv->timings.hactive.typ - 1)));
+	reg32_write(priv->addr + 0x20008,
+		    (((priv->timings.vsync_len.typ + priv->timings.vfront_porch.typ + priv->timings.vback_porch.typ -
+		       1) << 16) | (priv->timings.hsync_len.typ + priv->timings.hback_porch.typ - 1)));
+	reg32_write(priv->addr + 0x2000c,
+		    (((priv->timings.vsync_len.typ + priv->timings.vfront_porch.typ + priv->timings.vback_porch.typ + priv->timings.vactive.typ -
+		       1) << 16) | (priv->timings.hsync_len.typ + priv->timings.hback_porch.typ + priv->timings.hactive.typ - 1)));
+	reg32_write(priv->addr + 0x20010,
+		    (((priv->timings.vsync_len.typ + priv->timings.vfront_porch.typ + priv->timings.vback_porch.typ -
+		       1) << 16) | (priv->timings.hsync_len.typ + priv->timings.hback_porch.typ - 1)));
+	reg32_write(priv->addr + 0x20014,
+		    (((priv->timings.vsync_len.typ + priv->timings.vfront_porch.typ + priv->timings.vback_porch.typ + priv->timings.vactive.typ -
+		       1) << 16) | (priv->timings.hsync_len.typ + priv->timings.hback_porch.typ + priv->timings.hactive.typ - 1)));
+	reg32_write(priv->addr + 0x20028, 0x000b000a);
+
+	/* disable local alpha */
+	reg32_write(priv->addr + 0x20000, 0xff005184);
+
+	debug("leaving %s() ...\n", __func__);
+}
+
+static void imx8m_display_shutdown(struct udevice *dev)
+{
+	struct imx8m_dcss_priv *priv = dev_get_priv(dev);
+
+	/* stop the DCSS modules in use */
+	/* dtg */
+	reg32_write(priv->addr + 0x20000, 0);
+	/* scaler */
+	reg32_write(priv->addr + 0x1c000, 0);
+	reg32_write(priv->addr + 0x1c400, 0);
+	reg32_write(priv->addr + 0x1c800, 0);
+	/* dpr */
+	reg32_write(priv->addr + 0x18000, 0);
+	reg32_write(priv->addr + 0x19000, 0);
+	reg32_write(priv->addr + 0x1a000, 0);
+	/* sub-sampler*/
+	reg32_write(priv->addr + 0x1b000, 0);
+}
+
+static int imx8m_dcss_get_timings_from_display(struct udevice *dev,
+					   struct display_timing *timings)
+{
+	struct imx8m_dcss_priv *priv = dev_get_priv(dev);
+	int err;
+
+	priv->disp_dev = video_link_get_next_device(dev);
+	if (!priv->disp_dev ||
+		device_get_uclass_id(priv->disp_dev) != UCLASS_DISPLAY) {
+
+		printf("fail to find display device\n");
+		return -ENODEV;
+	}
+
+	debug("disp_dev %s\n", priv->disp_dev->name);
+
+	err = video_link_get_display_timings(timings);
+	if (err)
+		return err;
+
+	if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
+		priv->hpol = true;
+
+	if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
+		priv->vpol = true;
+
+	return 0;
+}
+
+static int imx8m_dcss_probe(struct udevice *dev)
+{
+	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct imx8m_dcss_priv *priv = dev_get_priv(dev);
+
+	u32 fb_start, fb_end;
+	int ret;
+
+	debug("%s() plat: base 0x%lx, size 0x%x\n",
+	       __func__, plat->base, plat->size);
+
+	priv->addr = dev_read_addr(dev);
+	if (priv->addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	ret = imx8m_dcss_get_timings_from_display(dev, &priv->timings);
+	if (ret)
+		return ret;
+
+	debug("pixelclock %u, hlen %u, vlen %u\n",
+		priv->timings.pixelclock.typ, priv->timings.hactive.typ, priv->timings.vactive.typ);
+
+	imx8m_dcss_power_init();
+
+	imx8m_dcss_clock_init(priv->timings.pixelclock.typ);
+
+	imx8m_dcss_reset(dev);
+
+	if (display_enable(priv->disp_dev, 32, NULL) == 0) {
+		imx8m_dcss_init(dev);
+		priv->enabled = true;
+	}
+
+	uc_priv->bpix = VIDEO_BPP32;
+	uc_priv->xsize = priv->timings.hactive.typ;
+	uc_priv->ysize = priv->timings.vactive.typ;
+
+	/* Enable dcache for the frame buffer */
+	fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
+	fb_end = plat->base + plat->size;
+	fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
+	mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
+					DCACHE_WRITEBACK);
+	video_set_flush_dcache(dev, true);
+
+	return ret;
+}
+
+static int imx8m_dcss_bind(struct udevice *dev)
+{
+	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+
+	debug("%s\n", __func__);
+
+	/* Max size supported by LCDIF, because in bind, we can't probe panel */
+	plat->size = 1920 * 1080 *4;
+
+	return 0;
+}
+
+static int imx8m_dcss_remove(struct udevice *dev)
+{
+	struct imx8m_dcss_priv *priv = dev_get_priv(dev);
+
+	debug("%s\n", __func__);
+
+	if (priv->enabled) {
+		device_remove(priv->disp_dev, DM_REMOVE_NORMAL);
+		imx8m_display_shutdown(dev);
+	}
+
+	return 0;
+}
+
+static const struct udevice_id imx8m_dcss_ids[] = {
+	{ .compatible = "nxp,imx8mq-dcss" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(imx8m_dcss) = {
+	.name	= "imx8m_dcss",
+	.id	= UCLASS_VIDEO,
+	.of_match = imx8m_dcss_ids,
+	.bind	= imx8m_dcss_bind,
+	.probe	= imx8m_dcss_probe,
+	.remove = imx8m_dcss_remove,
+	.flags	= DM_FLAG_PRE_RELOC,
+	.priv_auto	= sizeof(struct imx8m_dcss_priv),
+};
diff --git a/drivers/video/nxp/imx/imx_lcdifv3.c b/drivers/video/nxp/imx/imx_lcdifv3.c
new file mode 100644
index 00000000000..8313e09848a
--- /dev/null
+++ b/drivers/video/nxp/imx/imx_lcdifv3.c
@@ -0,0 +1,438 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <video.h>
+#include <video_fb.h>
+#include <video_bridge.h>
+#include <video_link.h>
+
+#include <asm/cache.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/err.h>
+#include <asm/io.h>
+
+#include "../../videomodes.h"
+#include <linux/string.h>
+#include <linux/list.h>
+#include <linux/fb.h>
+#include <linux/bug.h>
+#include <linux/delay.h>
+#include "lcdifv3-regs.h"
+#include <log.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/device_compat.h>
+
+#define	PS2KHZ(ps)	(1000000000UL / (ps))
+#define HZ2PS(hz)	(1000000000UL / ((hz) / 1000))
+
+struct lcdifv3_priv {
+	fdt_addr_t reg_base;
+	struct udevice *disp_dev;
+
+	u32 thres_low_mul;
+	u32 thres_low_div;
+	u32 thres_high_mul;
+	u32 thres_high_div;
+};
+
+static int lcdifv3_set_pix_fmt(struct lcdifv3_priv *priv, unsigned int format)
+{
+	uint32_t ctrldescl0_5 = 0;
+
+	ctrldescl0_5 = readl((ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_5));
+
+	WARN_ON(ctrldescl0_5 & CTRLDESCL0_5_SHADOW_LOAD_EN);
+
+	ctrldescl0_5 &= ~(CTRLDESCL0_5_BPP(0xf) | CTRLDESCL0_5_YUV_FORMAT(0x3));
+
+	switch (format) {
+	case GDF_16BIT_565RGB:
+		ctrldescl0_5 |= CTRLDESCL0_5_BPP(BPP16_RGB565);
+		break;
+	case GDF_32BIT_X888RGB:
+		ctrldescl0_5 |= CTRLDESCL0_5_BPP(BPP32_ARGB8888);
+		break;
+	default:
+		printf("unsupported pixel format: %u\n", format);
+		return -EINVAL;
+	}
+
+	writel(ctrldescl0_5,  (ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_5));
+
+	return 0;
+}
+
+
+static void lcdifv3_set_mode(struct lcdifv3_priv *priv,
+			struct ctfb_res_modes *mode)
+{
+	u32 disp_size, hsyn_para, vsyn_para, vsyn_hsyn_width, ctrldescl0_1;
+
+	/* config display timings */
+	disp_size = DISP_SIZE_DELTA_Y(mode->yres) |
+		    DISP_SIZE_DELTA_X(mode->xres);
+	writel(disp_size, (ulong)(priv->reg_base + LCDIFV3_DISP_SIZE));
+
+	hsyn_para = HSYN_PARA_BP_H(mode->left_margin) |
+		    HSYN_PARA_FP_H(mode->right_margin);
+	writel(hsyn_para, (ulong)(priv->reg_base + LCDIFV3_HSYN_PARA));
+
+	vsyn_para = VSYN_PARA_BP_V(mode->upper_margin) |
+		    VSYN_PARA_FP_V(mode->lower_margin);
+	writel(vsyn_para, (ulong)(priv->reg_base + LCDIFV3_VSYN_PARA));
+
+	vsyn_hsyn_width = VSYN_HSYN_WIDTH_PW_V(mode->vsync_len) |
+			  VSYN_HSYN_WIDTH_PW_H(mode->hsync_len);
+	writel(vsyn_hsyn_width, (ulong)(priv->reg_base + LCDIFV3_VSYN_HSYN_WIDTH));
+
+	/* config layer size */
+	/* TODO: 32bits alignment for width */
+	ctrldescl0_1 = CTRLDESCL0_1_HEIGHT(mode->yres) |
+		       CTRLDESCL0_1_WIDTH(mode->xres);
+	writel(ctrldescl0_1, (ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_1));
+
+	/* Polarities */
+	writel(CTRL_INV_HS, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR));
+	writel(CTRL_INV_VS, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR));
+
+	/* SEC MIPI DSI specific */
+	writel(CTRL_INV_PXCK, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR));
+	writel(CTRL_INV_DE, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR));
+
+}
+
+static void lcdifv3_set_bus_fmt(struct lcdifv3_priv *priv)
+{
+	uint32_t disp_para = 0;
+
+	disp_para = readl((ulong)(priv->reg_base + LCDIFV3_DISP_PARA));
+	disp_para &= DISP_PARA_LINE_PATTERN(0xf);
+
+	/* Fixed to 24 bits output */
+	disp_para |= DISP_PARA_LINE_PATTERN(LP_RGB888_OR_YUV444);
+
+	/* config display mode: default is normal mode */
+	disp_para &= DISP_PARA_DISP_MODE(3);
+	disp_para |= DISP_PARA_DISP_MODE(0);
+	writel(disp_para, (ulong)(priv->reg_base + LCDIFV3_DISP_PARA));
+}
+
+static void lcdifv3_enable_plane_panic(struct lcdifv3_priv *priv)
+{
+	u32 panic_thres, thres_low, thres_high;
+
+	/* apb clock has been enabled */
+
+	/* As suggestion, the thres_low should be 1/3 FIFO,
+	 * and thres_high should be 2/3 FIFO (The FIFO size
+	 * is 8KB = 512 * 128bit).
+	 * threshold = n * 128bit (n: 0 ~ 511)
+	 */
+	thres_low  = DIV_ROUND_UP(511 * priv->thres_low_mul,
+			priv->thres_low_div);
+	thres_high = DIV_ROUND_UP(511 * priv->thres_high_mul,
+			priv->thres_high_div);
+
+	panic_thres = PANIC0_THRES_PANIC_THRES_LOW(thres_low)	|
+		      PANIC0_THRES_PANIC_THRES_HIGH(thres_high);
+
+	writel(panic_thres, priv->reg_base + LCDIFV3_PANIC0_THRES);
+
+	/* Enable Panic:
+	 *
+	 * As designed, the panic won't trigger an irq,
+	 * so it is unnecessary to handle this as an irq
+	 * and NoC + QoS modules will handle panic
+	 * automatically.
+	 */
+	writel(INT_ENABLE_D1_PLANE_PANIC_EN,
+	       priv->reg_base + LCDIFV3_INT_ENABLE_D1);
+}
+
+static void lcdifv3_enable_controller(struct lcdifv3_priv *priv)
+{
+	u32 disp_para, ctrldescl0_5;
+
+	disp_para = readl((ulong)(priv->reg_base + LCDIFV3_DISP_PARA));
+	ctrldescl0_5 = readl((ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_5));
+
+	/* disp on */
+	disp_para |= DISP_PARA_DISP_ON;
+	writel(disp_para, (ulong)(priv->reg_base + LCDIFV3_DISP_PARA));
+
+	/* enable shadow load */
+	ctrldescl0_5 |= CTRLDESCL0_5_SHADOW_LOAD_EN;
+	writel(ctrldescl0_5, (ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_5));
+
+	/* enable layer dma */
+	ctrldescl0_5 |= CTRLDESCL0_5_EN;
+	writel(ctrldescl0_5, (ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_5));
+}
+
+static void lcdifv3_disable_controller(struct lcdifv3_priv *priv)
+{
+	u32 disp_para, ctrldescl0_5;
+
+	disp_para = readl((ulong)(priv->reg_base + LCDIFV3_DISP_PARA));
+	ctrldescl0_5 = readl((ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_5));
+
+	/* dma off */
+	ctrldescl0_5 &= ~CTRLDESCL0_5_EN;
+	writel(ctrldescl0_5, (ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_5));
+
+	/* disp off */
+	disp_para &= ~DISP_PARA_DISP_ON;
+	writel(disp_para, (ulong)(priv->reg_base + LCDIFV3_DISP_PARA));
+}
+
+static void lcdifv3_init(struct udevice *dev,
+			struct ctfb_res_modes *mode, unsigned int format)
+{
+	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+	struct lcdifv3_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	/* Kick in the LCDIF clock */
+	mxs_set_lcdclk(priv->reg_base, PS2KHZ(mode->pixclock));
+
+	writel(CTRL_SW_RESET, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR));
+
+	/* enable plane FIFO panic */
+	lcdifv3_enable_plane_panic(priv);
+
+	lcdifv3_set_mode(priv, mode);
+
+	lcdifv3_set_bus_fmt(priv);
+
+	ret = lcdifv3_set_pix_fmt(priv, format);
+	if (ret) {
+		printf("Fail to init lcdifv3, wrong format %u\n", format);
+		return;
+	}
+
+	/* Set fb address to primary layer */
+	writel(plat->base, (ulong)(priv->reg_base + LCDIFV3_CTRLDESCL_LOW0_4));
+
+	writel(CTRLDESCL0_3_P_SIZE(1) |CTRLDESCL0_3_T_SIZE(1) | CTRLDESCL0_3_PITCH(mode->xres * 4),
+		(ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_3));
+
+	lcdifv3_enable_controller(priv);
+}
+
+void lcdifv3_power_down(struct lcdifv3_priv *priv)
+{
+	int timeout = 1000000;
+
+	/* Disable LCDIF during VBLANK */
+	writel(INT_STATUS_D0_VS_BLANK,
+		(ulong)(priv->reg_base + LCDIFV3_INT_STATUS_D0));
+	while (--timeout) {
+		if (readl((ulong)(priv->reg_base + LCDIFV3_INT_STATUS_D0)) &
+		    INT_STATUS_D0_VS_BLANK)
+			break;
+		udelay(1);
+	}
+
+	lcdifv3_disable_controller(priv);
+}
+
+static int lcdifv3_of_get_timings(struct udevice *dev,
+			      struct display_timing *timings)
+{
+	int ret = 0;
+	struct lcdifv3_priv *priv = dev_get_priv(dev);
+
+	priv->disp_dev = video_link_get_next_device(dev);
+	if (!priv->disp_dev ||
+		(device_get_uclass_id(priv->disp_dev) != UCLASS_VIDEO_BRIDGE
+		&& device_get_uclass_id(priv->disp_dev) != UCLASS_DISPLAY)) {
+
+		printf("fail to find output device\n");
+		return -ENODEV;
+	}
+
+	debug("disp_dev %s\n", priv->disp_dev->name);
+
+	ret = video_link_get_display_timings(timings);
+	if (ret) {
+		printf("fail to get display timings\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+static int lcdifv3_check_thres_value(u32 mul, u32 div)
+{
+	if (!div)
+		return -EINVAL;
+
+	if (mul > div)
+		return -EINVAL;
+
+	return 0;
+}
+
+static void lcdifv3_of_parse_thres(struct udevice *dev)
+{
+	int ret;
+	u32 thres_low[2], thres_high[2];
+	struct lcdifv3_priv *priv = dev_get_priv(dev);
+
+
+	/* default 'thres-low' value:  FIFO * 1/3;
+	 * default 'thres-high' value: FIFO * 2/3.
+	 */
+	priv->thres_low_mul	= 1;
+	priv->thres_low_div	= 3;
+	priv->thres_high_mul	= 2;
+	priv->thres_high_div	= 3;
+
+	ret = dev_read_u32_array(dev, "thres-low", thres_low, 2);
+	if (!ret) {
+		/* check the value effectiveness */
+		ret = lcdifv3_check_thres_value(thres_low[0], thres_low[1]);
+		if (!ret) {
+			priv->thres_low_mul	= thres_low[0];
+			priv->thres_low_div	= thres_low[1];
+		}
+	}
+
+	ret = dev_read_u32_array(dev, "thres-high", thres_high, 2);
+	if (!ret) {
+		/* check the value effectiveness */
+		ret = lcdifv3_check_thres_value(thres_high[0], thres_high[1]);
+		if (!ret) {
+			priv->thres_high_mul	= thres_high[0];
+			priv->thres_high_div	= thres_high[1];
+		}
+	}
+}
+
+
+static int lcdifv3_video_probe(struct udevice *dev)
+{
+	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct lcdifv3_priv *priv = dev_get_priv(dev);
+
+	struct ctfb_res_modes mode;
+	struct display_timing timings;
+
+	u32 fb_start, fb_end;
+	int ret;
+
+	debug("%s() plat: base 0x%lx, size 0x%x\n",
+	       __func__, plat->base, plat->size);
+
+	priv->reg_base = dev_read_addr(dev);
+	if (priv->reg_base == FDT_ADDR_T_NONE) {
+		dev_err(dev, "lcdif base address is not found\n");
+		return -EINVAL;
+	}
+
+	ret = lcdifv3_of_get_timings(dev, &timings);
+	if (ret)
+		return ret;
+
+	lcdifv3_of_parse_thres(dev);
+
+	if (priv->disp_dev) {
+#if IS_ENABLED(CONFIG_VIDEO_BRIDGE)
+		if (device_get_uclass_id(priv->disp_dev) == UCLASS_VIDEO_BRIDGE) {
+			ret = video_bridge_attach(priv->disp_dev);
+			if (ret) {
+				dev_err(dev, "fail to attach bridge\n");
+				return ret;
+			}
+
+			ret = video_bridge_check_timing(priv->disp_dev, &timings);
+			if (ret) {
+				dev_err(dev, "fail to check timing\n");
+				return ret;
+			}
+
+			ret = video_bridge_set_backlight(priv->disp_dev, 80);
+			if (ret) {
+				dev_err(dev, "fail to set backlight\n");
+				return ret;
+			}
+		}
+#endif
+	}
+
+	mode.xres = timings.hactive.typ;
+	mode.yres = timings.vactive.typ;
+	mode.left_margin = timings.hback_porch.typ;
+	mode.right_margin = timings.hfront_porch.typ;
+	mode.upper_margin = timings.vback_porch.typ;
+	mode.lower_margin = timings.vfront_porch.typ;
+	mode.hsync_len = timings.hsync_len.typ;
+	mode.vsync_len = timings.vsync_len.typ;
+	mode.pixclock = HZ2PS(timings.pixelclock.typ);
+
+	lcdifv3_init(dev, &mode, GDF_32BIT_X888RGB);
+
+	uc_priv->bpix = VIDEO_BPP32; /* only support 32 BPP now */
+	uc_priv->xsize = mode.xres;
+	uc_priv->ysize = mode.yres;
+
+	/* Enable dcache for the frame buffer */
+	fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
+	fb_end = plat->base + plat->size;
+	fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
+	mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
+					DCACHE_WRITEBACK);
+	video_set_flush_dcache(dev, true);
+	gd->fb_base = plat->base;
+
+	return ret;
+}
+
+static int lcdifv3_video_bind(struct udevice *dev)
+{
+	struct video_uc_plat *plat = dev_get_uclass_plat(dev);
+
+	/* Max size supported by LCDIF, because in bind, we can't probe panel */
+	plat->size = 1920 * 1080 *4 * 2;
+
+	return 0;
+}
+
+static int lcdifv3_video_remove(struct udevice *dev)
+{
+	struct lcdifv3_priv *priv = dev_get_priv(dev);
+
+	debug("%s\n", __func__);
+
+	if (priv->disp_dev)
+		device_remove(priv->disp_dev, DM_REMOVE_NORMAL);
+
+	lcdifv3_power_down(priv);
+
+	return 0;
+}
+
+static const struct udevice_id lcdifv3_video_ids[] = {
+	{ .compatible = "fsl,imx8mp-lcdif1" },
+	{ .compatible = "fsl,imx93-lcdif" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(lcdifv3_video) = {
+	.name	= "lcdifv3_video",
+	.id	= UCLASS_VIDEO,
+	.of_match = lcdifv3_video_ids,
+	.bind	= lcdifv3_video_bind,
+	.probe	= lcdifv3_video_probe,
+	.remove = lcdifv3_video_remove,
+	.flags	= DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
+	.priv_auto   = sizeof(struct lcdifv3_priv),
+};
diff --git a/drivers/video/nxp/imx/imxdpuv1.c b/drivers/video/nxp/imx/imxdpuv1.c
new file mode 100644
index 00000000000..26025e1453a
--- /dev/null
+++ b/drivers/video/nxp/imx/imxdpuv1.c
@@ -0,0 +1,6214 @@
+/*
+ * Copyright 2015-2017 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/types.h>
+
+#include "imxdpuv1_private.h"
+#include "imxdpuv1_registers.h"
+#include "imxdpuv1_events.h"
+
+#include "imxdpuv1_be.h"
+
+#define ptr_to_uint32(__ptr__) ((uint32_t)((uint64_t)(__ptr__)))
+
+/* Private data*/
+static struct imxdpuv1_soc imxdpuv1_array[IMXDPUV1_MAX_NUM];
+
+typedef struct {
+	uint8_t len;
+	uint8_t buffers;
+} imxdpuv1_burst_entry_t;
+
+static const imxdpuv1_burst_entry_t burst_param[] = {
+	{ 0, 0 },     /* IMXDPUV1_SCAN_DIR_UNKNOWN */
+	{ 8, 32 },    /* IMXDPUV1_SCAN_DIR_LEFT_RIGHT_DOWN */
+	{ 16, 16 },   /* IMXDPUV1_SCAN_DIR_HORIZONTAL */
+	{ 8, 32 },    /* IMXDPUV1_SCAN_DIR_VERTICAL possibly 8/32 here */
+	{ 8, 32 },    /* IMXDPUV1_SCAN_DIR_FREE */
+};
+
+typedef struct {
+	uint32_t extdst;
+	uint32_t sub;
+} trigger_entry_t;
+
+static const trigger_entry_t trigger_list[IMXDPUV1_SHDLD_IDX_MAX] = {
+	/*  IMXDPUV1_SHDLD_* extdst,          sub */
+	/* _DISP0    */{ 1, 0 },
+	/* _DISP1    */{ 1, 0 },
+	/* _CONST0   */{ IMXDPUV1_SHDLD_CONSTFRAME0, 0 },
+	/* _CONST1   */{ IMXDPUV1_SHDLD_CONSTFRAME1, 0 },
+	/* _CHAN_00  */{ IMXDPUV1_SHDLD_FETCHDECODE2, 0 },
+	/* _CHAN_01  */{ IMXDPUV1_SHDLD_FETCHDECODE0, 0 },
+	/* _CHAN_02  */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_1 },
+	/* _CHAN_03  */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_2 },
+	/* _CHAN_04  */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_3 },
+	/* _CHAN_05  */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_4 },
+	/* _CHAN_06  */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_5 },
+	/* _CHAN_07  */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_6 },
+	/* _CHAN_08  */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_7 },
+	/* _CHAN_09  */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_8 },
+	/* _CHAN_10  */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_1 << 16 },
+	/* _CHAN_11  */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_2 << 16 },
+	/* _CHAN_12  */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_3 << 16 },
+	/* _CHAN_13  */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_4 << 16 },
+	/* _CHAN_14  */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_5 << 16 },
+	/* _CHAN_15  */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_6 << 16 },
+	/* _CHAN_16  */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_7 << 16 },
+	/* _CHAN_17  */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_8 << 16 },
+	/* _CHAN_18  */{ IMXDPUV1_SHDLD_FETCHDECODE3, 0 },
+	/* _CHAN_19  */{ IMXDPUV1_SHDLD_FETCHDECODE1, 0 },
+	/* _CHAN_20  */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_1 << 8 },
+	/* _CHAN_21  */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_2 << 8 },
+	/* _CHAN_22  */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_3 << 8 },
+	/* _CHAN_23  */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_4 << 8 },
+	/* _CHAN_24  */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_5 << 8 },
+	/* _CHAN_25  */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_6 << 8 },
+	/* _CHAN_26  */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_7 << 8 },
+	/* _CHAN_27  */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_8 << 8 },
+	/* _CHAN_28  */{ IMXDPUV1_SHDLD_FETCHECO0, 0 },
+	/* _CHAN_29  */{ IMXDPUV1_SHDLD_FETCHECO1, 0 },
+	/* _CHAN_30  */{ IMXDPUV1_SHDLD_FETCHECO2, 0 }
+};
+
+#ifdef ENABLE_IMXDPUV1_TRACE_REG
+uint32_t _imxdpuv1_read(struct imxdpuv1_soc *imxdpu, uint32_t offset, char *file,
+	int line)
+{
+	uint32_t val = 0;
+	val = __raw_readl(imxdpu->base + offset);
+	IMXDPUV1_TRACE_REG("%s:%d R reg 0x%08x --> val 0x%08x\n", file, line,
+		(uint32_t)offset, (uint32_t)val);
+	return val;
+}
+
+void _imxdpuv1_write(struct imxdpuv1_soc *imxdpu, uint32_t offset, uint32_t value,
+	char *file, int line)
+{
+	__raw_writel(value, imxdpu->base + offset);
+	IMXDPUV1_TRACE_REG("%s:%d W reg 0x%08x <-- val 0x%08x\n", file, line,
+		(uint32_t)offset, (uint32_t)value);
+}
+
+#endif
+
+void _imxdpuv1_write_block(struct imxdpuv1_soc *imxdpu, uint32_t offset,
+	void *values, uint32_t cnt, char *file, int line)
+{
+	int i;
+	uint32_t *dest = (uint32_t *)(imxdpu->base + offset);
+	uint32_t *src = (uint32_t *)values;
+	IMXDPUV1_TRACE_REG("%s:%d W reg 0x%08x <-- cnt 0x%08x\n", file, line,
+		(uint32_t)offset, (uint32_t)cnt);
+	for (i = 0; i < cnt; i++) {
+		dest[i] = src[i];
+		IMXDPUV1_TRACE_REG("%s:%d WB reg 0x%08x <-- val 0x%08x\n", file, line,
+		(uint32_t) ((uint64_t)(&dest[i])), (uint32_t)(src[i]));
+
+	}
+}
+
+#ifdef ENABLE_IMXDPUV1_TRACE_IRQ_READ
+uint32_t _imxdpuv1_read_irq(struct imxdpuv1_soc *imxdpu, uint32_t offset,
+	char *file, int line)
+{
+	uint32_t val = 0;
+	val = __raw_readl(imxdpu->base + offset);
+	IMXDPUV1_TRACE_IRQ("%s:%d IRQ R reg 0x%08x --> val 0x%08x\n", file, line,
+		(uint32_t)offset, (uint32_t)val);
+	return val;
+}
+#endif
+
+#ifdef ENABLE_IMXDPUV1_TRACE_IRQ_WRITE
+void _imxdpuv1_write_irq(struct imxdpuv1_soc *imxdpu, uint32_t offset,
+	uint32_t value, char *file, int line)
+{
+	__raw_writel(value, imxdpu->base + offset);
+	IMXDPUV1_TRACE_IRQ("%s:%d IRQ W reg 0x%08x <-- val 0x%08x\n", file, line,
+		(uint32_t)offset, (uint32_t)value);
+}
+#endif
+
+/* static prototypes */
+int imxdpuv1_dump_channel(int8_t imxdpuv1_id, imxdpuv1_chan_t chan);
+static int imxdpuv1_disp_start_shadow_loads(int8_t imxdpuv1_id, int8_t disp);
+void imxdpuv1_dump_pixencfg_status(int8_t imxdpuv1_id);
+static bool imxdpuv1_is_yuv(uint32_t fmt);
+bool imxdpuv1_is_rgb(uint32_t fmt);
+
+/*!
+ * Returns IMXDPUV1_TRUE for a valid channel
+ *
+ * @param	channel to test
+ *
+ * @return      This function returns IMXDPUV1_TRUE on success or
+ *		IMXDPUV1_FALSE if the test fails.
+ */
+static int is_chan(imxdpuv1_chan_t chan)
+{
+	imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan);
+
+	if ((chan_idx >= IMXDPUV1_CHAN_IDX_IN_FIRST) &&
+		(chan_idx < IMXDPUV1_CHAN_IDX_IN_MAX))
+		return IMXDPUV1_TRUE;
+	if ((chan_idx >= IMXDPUV1_CHAN_IDX_OUT_FIRST) &&
+		(chan_idx < IMXDPUV1_CHAN_IDX_OUT_MAX))
+		return IMXDPUV1_TRUE;
+	return IMXDPUV1_FALSE;
+}
+
+/*!
+ * Returns IMXDPUV1_TRUE for a valid store channel
+ *
+ * @param	channel to test
+ *
+ * @return      This function returns IMXDPUV1_TRUE on success or
+ *		IMXDPUV1_FALSE if the test fails.
+ */
+static int is_store_chan(imxdpuv1_chan_t chan)
+{
+#ifdef IMXDPUV1_VERSION_0
+	imxdpuv1_id_t blk_id = get_channel_blk(chan);
+	if ((blk_id == IMXDPUV1_ID_STORE4) || (blk_id == IMXDPUV1_ID_STORE4))
+		return IMXDPUV1_TRUE;
+#endif
+	return IMXDPUV1_FALSE;
+}
+
+/*!
+ * Returns IMXDPUV1_TRUE for a valid fetch channel
+ *
+ * @param	channel to test
+ *
+ * @return      This function returns IMXDPUV1_TRUE on success or
+ *		IMXDPUV1_FALSE if the test fails.
+ */
+static int is_fetch_eco_chan(imxdpuv1_chan_t chan)
+{
+	imxdpuv1_id_t blk_id = get_channel_blk(chan);
+	if ((blk_id == IMXDPUV1_ID_FETCHECO0) ||
+		(blk_id == IMXDPUV1_ID_FETCHECO1) ||
+		(blk_id == IMXDPUV1_ID_FETCHECO2))
+		return IMXDPUV1_TRUE;
+	return IMXDPUV1_FALSE;
+}
+
+/*!
+ * Returns IMXDPUV1_TRUE for a valid fetch decode channel
+ *
+ * @param	channel to test
+ *
+ * @return      This function returns IMXDPUV1_TRUE on success or
+ *		IMXDPUV1_FALSE if the test fails.
+ */
+static int is_fetch_decode_chan(imxdpuv1_chan_t chan)
+{
+	imxdpuv1_id_t blk_id = get_channel_blk(chan);
+	if ((blk_id == IMXDPUV1_ID_FETCHDECODE0) ||
+		(blk_id == IMXDPUV1_ID_FETCHDECODE1)
+#ifdef IMXDPUV1_VERSION_0
+	    || (blk_id == IMXDPUV1_ID_FETCHDECODE2)
+	    || (blk_id == IMXDPUV1_ID_FETCHDECODE3)
+#endif
+	    )
+	    return IMXDPUV1_TRUE;
+	return IMXDPUV1_FALSE;
+}
+
+/*!
+ * Returns IMXDPUV1_TRUE if a fetch channel has an eco fetch
+ *
+ * @param	channel to test
+ *
+ * @return      This function returns IMXDPUV1_TRUE on success or
+ *		IMXDPUV1_FALSE if the test fails.
+ */
+static int has_fetch_eco_chan(imxdpuv1_chan_t chan)
+{
+	imxdpuv1_id_t blk_id = get_channel_blk(chan);
+	if ((blk_id == IMXDPUV1_ID_FETCHDECODE0) ||
+		(blk_id == IMXDPUV1_ID_FETCHDECODE1) ||
+		(blk_id == IMXDPUV1_ID_FETCHWARP2))
+		return IMXDPUV1_TRUE;
+	return IMXDPUV1_FALSE;
+}
+
+/*!
+ * Returns IMXDPUV1_TRUE for a valid fetch warp channel
+ *
+ * @param	channel to test
+ *
+ * @return      This function returns IMXDPUV1_TRUE on success or
+ *		IMXDPUV1_FALSE if the test fails.
+ */
+static int is_fetch_warp_chan(imxdpuv1_chan_t chan)
+{
+	imxdpuv1_id_t blk_id = get_channel_blk(chan);
+	if ((blk_id == IMXDPUV1_ID_FETCHWARP2))
+		return IMXDPUV1_TRUE;
+	return IMXDPUV1_FALSE;
+}
+
+/*!
+ * Returns IMXDPUV1_TRUE for a valid fetch layer channel
+ *
+ * @param	channel to test
+ *
+ * @return      This function returns IMXDPUV1_TRUE on success or
+ *		IMXDPUV1_FALSE if the test fails.
+ */
+static int is_fetch_layer_chan(imxdpuv1_chan_t chan)
+{
+	imxdpuv1_id_t blk_id = get_channel_blk(chan);
+	if ((blk_id == IMXDPUV1_ID_FETCHLAYER0)
+#ifdef IMXDPUV1_VERSION_0
+	    || (blk_id == IMXDPUV1_ID_FETCHLAYER1)
+#endif
+	    )
+	    return IMXDPUV1_TRUE;
+	return IMXDPUV1_FALSE;
+}
+
+/*!
+ * Returns IMXDPUV1_TRUE for a valid layer sub1 channel
+ *
+ * @param	channel to test
+ *
+ * @return      This function returns IMXDPUV1_TRUE on success or
+ *		IMXDPUV1_FALSE if the test fails.
+ */
+static int is_fetch_layer_sub_chan1(imxdpuv1_chan_t chan)
+{
+	imxdpuv1_id_t blk_id = get_channel_blk(chan);
+	if ((blk_id == IMXDPUV1_ID_FETCHLAYER0) ||
+#ifdef IMXDPUV1_VERSION_0
+		(blk_id == IMXDPUV1_ID_FETCHLAYER1) ||
+#endif
+		(blk_id == IMXDPUV1_ID_FETCHWARP2))
+		if (get_channel_sub(chan) == IMXDPUV1_SUB_1)
+			return IMXDPUV1_TRUE;
+	return IMXDPUV1_FALSE;
+}
+
+/*!
+ * Returns subindex of a channel
+ *
+ * @param	channel
+ *
+ * @return      returns the subindex of a channel
+ */
+static int imxdpuv1_get_channel_subindex(imxdpuv1_chan_t chan)
+{
+	switch (get_channel_sub(chan)) {
+	case IMXDPUV1_SUB_2:
+		return 1;
+	case IMXDPUV1_SUB_3:
+		return 2;
+	case IMXDPUV1_SUB_4:
+		return 3;
+	case IMXDPUV1_SUB_5:
+		return 4;
+	case IMXDPUV1_SUB_6:
+		return 5;
+	case IMXDPUV1_SUB_7:
+		return 6;
+	case IMXDPUV1_SUB_8:
+		return 7;
+	case IMXDPUV1_SUB_1:
+	case IMXDPUV1_SUBWINDOW_NONE:
+	default:
+		return 0;
+	}
+}
+
+/*!
+ * Returns returns the eco channel for a channel index
+ *
+ * @param       chan
+ *
+ * @return      returns number of bits per pixel or zero
+ *      	if the format is not matched.
+ */
+imxdpuv1_chan_t imxdpuv1_get_eco(imxdpuv1_chan_t chan)
+{
+	switch (get_eco_idx(chan)) {
+	case get_channel_idx(IMXDPUV1_CHAN_28):
+		return IMXDPUV1_CHAN_28;
+	case get_channel_idx(IMXDPUV1_CHAN_29):
+		return IMXDPUV1_CHAN_29;
+	case get_channel_idx(IMXDPUV1_CHAN_30):
+		return IMXDPUV1_CHAN_30;
+	default:
+		return 0;
+	}
+}
+/*!
+ * Returns the start address offset for a given block ID
+ *
+ * @param	block id
+ *
+ * @return      This function returns the address offset if the block id
+ *		matches a valid block. Otherwise, IMXDPUV1_OFFSET_INVALID
+ *		is returned.
+ */
+uint32_t id2blockoffset(imxdpuv1_id_t block_id)
+{
+	switch (block_id) {
+	/*case IMXDPUV1_ID_NONE:         return IMXDPUV1_NONE_LOCKUNLOCK; */
+	case IMXDPUV1_ID_FETCHDECODE9:
+		return IMXDPUV1_FETCHDECODE9_LOCKUNLOCK;
+#ifdef IMXDPUV1_VERSION_0
+	case IMXDPUV1_ID_FETCHPERSP9:
+		return IMXDPUV1_FETCHPERSP9_LOCKUNLOCK;
+#else
+	case IMXDPUV1_ID_FETCHWARP9:
+		return IMXDPUV1_FETCHWARP9_LOCKUNLOCK;
+#endif
+	case IMXDPUV1_ID_FETCHECO9:
+		return IMXDPUV1_FETCHECO9_LOCKUNLOCK;
+	case IMXDPUV1_ID_ROP9:
+		return IMXDPUV1_ROP9_LOCKUNLOCK;
+	case IMXDPUV1_ID_CLUT9:
+		return IMXDPUV1_CLUT9_LOCKUNLOCK;
+	case IMXDPUV1_ID_MATRIX9:
+		return IMXDPUV1_MATRIX9_LOCKUNLOCK;
+	case IMXDPUV1_ID_HSCALER9:
+		return IMXDPUV1_HSCALER9_LOCKUNLOCK;
+	case IMXDPUV1_ID_VSCALER9:
+		return IMXDPUV1_VSCALER9_LOCKUNLOCK;
+	case IMXDPUV1_ID_FILTER9:
+		return IMXDPUV1_FILTER9_LOCKUNLOCK;
+	case IMXDPUV1_ID_BLITBLEND9:
+		return IMXDPUV1_BLITBLEND9_LOCKUNLOCK;
+	case IMXDPUV1_ID_STORE9:
+		return IMXDPUV1_STORE9_LOCKUNLOCK;
+	case IMXDPUV1_ID_CONSTFRAME0:
+		return IMXDPUV1_CONSTFRAME0_LOCKUNLOCK;
+	case IMXDPUV1_ID_EXTDST0:
+		return IMXDPUV1_EXTDST0_LOCKUNLOCK;
+	case IMXDPUV1_ID_CONSTFRAME4:
+		return IMXDPUV1_CONSTFRAME4_LOCKUNLOCK;
+	case IMXDPUV1_ID_EXTDST4:
+		return IMXDPUV1_EXTDST4_LOCKUNLOCK;
+	case IMXDPUV1_ID_CONSTFRAME1:
+		return IMXDPUV1_CONSTFRAME1_LOCKUNLOCK;
+	case IMXDPUV1_ID_EXTDST1:
+		return IMXDPUV1_EXTDST1_LOCKUNLOCK;
+	case IMXDPUV1_ID_CONSTFRAME5:
+		return IMXDPUV1_CONSTFRAME5_LOCKUNLOCK;
+	case IMXDPUV1_ID_EXTDST5:
+		return IMXDPUV1_EXTDST5_LOCKUNLOCK;
+#ifdef IMXDPUV1_VERSION_0
+	case IMXDPUV1_ID_EXTSRC4:
+		return IMXDPUV1_EXTSRC4_LOCKUNLOCK;
+	case IMXDPUV1_ID_STORE4:
+		return IMXDPUV1_STORE4_LOCKUNLOCK;
+	case IMXDPUV1_ID_EXTSRC5:
+		return IMXDPUV1_EXTSRC5_LOCKUNLOCK;
+	case IMXDPUV1_ID_STORE5:
+		return IMXDPUV1_STORE5_LOCKUNLOCK;
+	case IMXDPUV1_ID_FETCHDECODE2:
+		return IMXDPUV1_FETCHDECODE2_LOCKUNLOCK;
+	case IMXDPUV1_ID_FETCHDECODE3:
+		return IMXDPUV1_FETCHDECODE3_LOCKUNLOCK;
+#endif
+	case IMXDPUV1_ID_FETCHWARP2:
+		return IMXDPUV1_FETCHWARP2_LOCKUNLOCK;
+	case IMXDPUV1_ID_FETCHECO2:
+		return IMXDPUV1_FETCHECO2_LOCKUNLOCK;
+	case IMXDPUV1_ID_FETCHDECODE0:
+		return IMXDPUV1_FETCHDECODE0_LOCKUNLOCK;
+	case IMXDPUV1_ID_FETCHECO0:
+		return IMXDPUV1_FETCHECO0_LOCKUNLOCK;
+	case IMXDPUV1_ID_FETCHDECODE1:
+		return IMXDPUV1_FETCHDECODE1_LOCKUNLOCK;
+	case IMXDPUV1_ID_FETCHECO1:
+		return IMXDPUV1_FETCHECO1_LOCKUNLOCK;
+	case IMXDPUV1_ID_FETCHLAYER0:
+		return IMXDPUV1_FETCHLAYER0_LOCKUNLOCK;
+#ifdef IMXDPUV1_VERSION_0
+	case IMXDPUV1_ID_FETCHLAYER1:
+		return IMXDPUV1_FETCHLAYER1_LOCKUNLOCK;
+	case IMXDPUV1_ID_GAMMACOR4:
+		return IMXDPUV1_GAMMACOR4_LOCKUNLOCK;
+#endif
+	case IMXDPUV1_ID_MATRIX4:
+		return IMXDPUV1_MATRIX4_LOCKUNLOCK;
+	case IMXDPUV1_ID_HSCALER4:
+		return IMXDPUV1_HSCALER4_LOCKUNLOCK;
+	case IMXDPUV1_ID_VSCALER4:
+		return IMXDPUV1_VSCALER4_LOCKUNLOCK;
+#ifdef IMXDPUV1_VERSION_0
+	case IMXDPUV1_ID_HISTOGRAM4:
+		return IMXDPUV1_HISTOGRAM4_CONTROL;
+	case IMXDPUV1_ID_GAMMACOR5:
+		return IMXDPUV1_GAMMACOR5_LOCKUNLOCK;
+#endif
+	case IMXDPUV1_ID_MATRIX5:
+		return IMXDPUV1_MATRIX5_LOCKUNLOCK;
+	case IMXDPUV1_ID_HSCALER5:
+		return IMXDPUV1_HSCALER5_LOCKUNLOCK;
+	case IMXDPUV1_ID_VSCALER5:
+		return IMXDPUV1_VSCALER5_LOCKUNLOCK;
+#ifdef IMXDPUV1_VERSION_0
+	case IMXDPUV1_ID_HISTOGRAM5:
+		return IMXDPUV1_HISTOGRAM5_CONTROL;
+#endif
+	case IMXDPUV1_ID_LAYERBLEND0:
+		return IMXDPUV1_LAYERBLEND0_LOCKUNLOCK;
+	case IMXDPUV1_ID_LAYERBLEND1:
+		return IMXDPUV1_LAYERBLEND1_LOCKUNLOCK;
+	case IMXDPUV1_ID_LAYERBLEND2:
+		return IMXDPUV1_LAYERBLEND2_LOCKUNLOCK;
+	case IMXDPUV1_ID_LAYERBLEND3:
+		return IMXDPUV1_LAYERBLEND3_LOCKUNLOCK;
+#ifdef IMXDPUV1_VERSION_0
+	case IMXDPUV1_ID_LAYERBLEND4:
+		return IMXDPUV1_LAYERBLEND4_LOCKUNLOCK;
+	case IMXDPUV1_ID_LAYERBLEND5:
+		return IMXDPUV1_LAYERBLEND5_LOCKUNLOCK;
+	case IMXDPUV1_ID_LAYERBLEND6:
+		return IMXDPUV1_LAYERBLEND6_LOCKUNLOCK;
+	case IMXDPUV1_ID_EXTSRC0:
+		return IMXDPUV1_EXTSRC0_LOCKUNLOCK;
+	case IMXDPUV1_ID_EXTSRC1:
+		return IMXDPUV1_EXTSRC1_LOCKUNLOCK;
+#endif
+	case IMXDPUV1_ID_DISENGCFG:
+		return IMXDPUV1_DISENGCFG_LOCKUNLOCK0;
+	case IMXDPUV1_ID_FRAMEGEN0:
+		return IMXDPUV1_FRAMEGEN0_LOCKUNLOCK;
+	case IMXDPUV1_ID_MATRIX0:
+		return IMXDPUV1_MATRIX0_LOCKUNLOCK;
+	case IMXDPUV1_ID_GAMMACOR0:
+		return IMXDPUV1_GAMMACOR0_LOCKUNLOCK;
+	case IMXDPUV1_ID_DITHER0:
+		return IMXDPUV1_DITHER0_LOCKUNLOCK;
+	case IMXDPUV1_ID_TCON0:
+		return IMXDPUV1_TCON0_LOCKUNLOCK;
+	case IMXDPUV1_ID_SIG0:
+		return IMXDPUV1_SIG0_LOCKUNLOCK;
+	case IMXDPUV1_ID_FRAMEGEN1:
+		return IMXDPUV1_FRAMEGEN1_LOCKUNLOCK;
+	case IMXDPUV1_ID_MATRIX1:
+		return IMXDPUV1_MATRIX1_LOCKUNLOCK;
+	case IMXDPUV1_ID_GAMMACOR1:
+		return IMXDPUV1_GAMMACOR1_LOCKUNLOCK;
+	case IMXDPUV1_ID_DITHER1:
+		return IMXDPUV1_DITHER1_LOCKUNLOCK;
+	case IMXDPUV1_ID_TCON1:
+		return IMXDPUV1_TCON1_LOCKUNLOCK;
+	case IMXDPUV1_ID_SIG1:
+		return IMXDPUV1_SIG1_LOCKUNLOCK;
+#ifdef IMXDPUV1_VERSION_0
+	case IMXDPUV1_ID_FRAMECAP4:
+		return IMXDPUV1_FRAMECAP4_LOCKUNLOCK;
+	case IMXDPUV1_ID_FRAMECAP5:
+		return IMXDPUV1_FRAMECAP5_LOCKUNLOCK;
+#endif
+	default:
+		return IMXDPUV1_OFFSET_INVALID;
+	}
+}
+
+/*!
+ * Returns the start address offset for the dynamic configuraiton for
+ * a given block ID
+ *
+ * @param	block id
+ *
+ * @return      This function returns the address offset if the block id
+ *		matches a valid block. Otherwise, IMXDPUV1_OFFSET_INVALID
+ *		is returned.
+ */
+uint32_t id2dynamicoffset(imxdpuv1_id_t block_id)
+{
+	switch (block_id) {
+	case IMXDPUV1_ID_FETCHDECODE9:
+		return IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC;
+
+#ifdef IMXDPUV1_VERSION_0
+	case IMXDPUV1_ID_FETCHPERSP9:
+		return IMXDPUV1_PIXENGCFG_FETCHPERSP9_DYNAMIC;
+#else
+	case IMXDPUV1_ID_FETCHWARP9:
+		return IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC;
+#endif
+	case IMXDPUV1_ID_ROP9:
+		return IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC;
+	case IMXDPUV1_ID_CLUT9:
+		return IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC;
+	case IMXDPUV1_ID_MATRIX9:
+		return IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC;
+	case IMXDPUV1_ID_HSCALER9:
+		return IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC;
+	case IMXDPUV1_ID_VSCALER9:
+		return IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC;
+	case IMXDPUV1_ID_FILTER9:
+		return IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC;
+	case IMXDPUV1_ID_BLITBLEND9:
+		return IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC;
+	case IMXDPUV1_ID_STORE9:
+		return IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC;
+	case IMXDPUV1_ID_EXTDST0:
+		return IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC;
+	case IMXDPUV1_ID_EXTDST4:
+		return IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC;
+	case IMXDPUV1_ID_EXTDST1:
+		return IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC;
+#ifdef IMXDPUV1_VERSION_0
+	case IMXDPUV1_ID_EXTDST5:
+		return IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC;
+	case IMXDPUV1_ID_STORE4:
+		return IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC;
+	case IMXDPUV1_ID_STORE5:
+		return IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC;
+	case IMXDPUV1_ID_FETCHDECODE2:
+		return IMXDPUV1_PIXENGCFG_FETCHDECODE2_DYNAMIC;
+	case IMXDPUV1_ID_FETCHDECODE3:
+		return IMXDPUV1_PIXENGCFG_FETCHDECODE3_DYNAMIC;
+#endif
+	case IMXDPUV1_ID_FETCHWARP2:
+		return IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC;
+	case IMXDPUV1_ID_FETCHDECODE0:
+		return IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC;
+	case IMXDPUV1_ID_FETCHDECODE1:
+		return IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC;
+#ifdef IMXDPUV1_VERSION_0
+	case IMXDPUV1_ID_GAMMACOR4:
+		return IMXDPUV1_PIXENGCFG_GAMMACOR4_DYNAMIC;
+#endif
+	case IMXDPUV1_ID_MATRIX4:
+		return IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC;
+	case IMXDPUV1_ID_HSCALER4:
+		return IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC;
+	case IMXDPUV1_ID_VSCALER4:
+		return IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC;
+#ifdef IMXDPUV1_VERSION_0
+	case IMXDPUV1_ID_HISTOGRAM4:
+		return IMXDPUV1_PIXENGCFG_HISTOGRAM4_DYNAMIC;
+	case IMXDPUV1_ID_GAMMACOR5:
+		return IMXDPUV1_PIXENGCFG_GAMMACOR5_DYNAMIC;
+#endif
+	case IMXDPUV1_ID_MATRIX5:
+		return IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC;
+	case IMXDPUV1_ID_HSCALER5:
+		return IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC;
+	case IMXDPUV1_ID_VSCALER5:
+		return IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC;
+#ifdef IMXDPUV1_VERSION_0
+	case IMXDPUV1_ID_HISTOGRAM5:
+		return IMXDPUV1_PIXENGCFG_HISTOGRAM5_DYNAMIC;
+#endif
+	case IMXDPUV1_ID_LAYERBLEND0:
+		return IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC;
+	case IMXDPUV1_ID_LAYERBLEND1:
+		return IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC;
+	case IMXDPUV1_ID_LAYERBLEND2:
+		return IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC;
+	case IMXDPUV1_ID_LAYERBLEND3:
+		return IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC;
+#ifdef IMXDPUV1_VERSION_0
+	case IMXDPUV1_ID_LAYERBLEND4:
+		return IMXDPUV1_PIXENGCFG_LAYERBLEND4_DYNAMIC;
+	case IMXDPUV1_ID_LAYERBLEND5:
+		return IMXDPUV1_PIXENGCFG_LAYERBLEND5_DYNAMIC;
+	case IMXDPUV1_ID_LAYERBLEND6:
+		return IMXDPUV1_PIXENGCFG_LAYERBLEND6_DYNAMIC;
+#endif
+	default:
+		return IMXDPUV1_OFFSET_INVALID;
+	}
+}
+
+/*!
+ * Returns the start address offset for a given shadow index
+ *
+ * @param	block id
+ *
+ * @return      This function returns the address offset if the shadow
+ *		index matches a valid block. Otherwise, IMXDPUV1_OFFSET_INVALID
+ *		is returned.
+ */
+imxdpuv1_chan_t shadowindex2channel(imxdpuv1_shadow_load_index_t shadow_index)
+{
+	switch (shadow_index) {
+	case IMXDPUV1_SHDLD_IDX_CHAN_00:
+		return IMXDPUV1_CHAN_00;
+	case IMXDPUV1_SHDLD_IDX_CHAN_01:
+		return IMXDPUV1_CHAN_01;
+	case IMXDPUV1_SHDLD_IDX_CHAN_02:
+		return IMXDPUV1_CHAN_02;
+	case IMXDPUV1_SHDLD_IDX_CHAN_03:
+		return IMXDPUV1_CHAN_03;
+	case IMXDPUV1_SHDLD_IDX_CHAN_04:
+		return IMXDPUV1_CHAN_04;
+	case IMXDPUV1_SHDLD_IDX_CHAN_05:
+		return IMXDPUV1_CHAN_05;
+	case IMXDPUV1_SHDLD_IDX_CHAN_06:
+		return IMXDPUV1_CHAN_06;
+	case IMXDPUV1_SHDLD_IDX_CHAN_07:
+		return IMXDPUV1_CHAN_07;
+	case IMXDPUV1_SHDLD_IDX_CHAN_08:
+		return IMXDPUV1_CHAN_08;
+	case IMXDPUV1_SHDLD_IDX_CHAN_09:
+		return IMXDPUV1_CHAN_09;
+	case IMXDPUV1_SHDLD_IDX_CHAN_10:
+		return IMXDPUV1_CHAN_10;
+	case IMXDPUV1_SHDLD_IDX_CHAN_11:
+		return IMXDPUV1_CHAN_11;
+	case IMXDPUV1_SHDLD_IDX_CHAN_12:
+		return IMXDPUV1_CHAN_12;
+	case IMXDPUV1_SHDLD_IDX_CHAN_13:
+		return IMXDPUV1_CHAN_13;
+	case IMXDPUV1_SHDLD_IDX_CHAN_14:
+		return IMXDPUV1_CHAN_14;
+	case IMXDPUV1_SHDLD_IDX_CHAN_15:
+		return IMXDPUV1_CHAN_15;
+	case IMXDPUV1_SHDLD_IDX_CHAN_16:
+		return IMXDPUV1_CHAN_16;
+	case IMXDPUV1_SHDLD_IDX_CHAN_17:
+		return IMXDPUV1_CHAN_17;
+	case IMXDPUV1_SHDLD_IDX_CHAN_18:
+		return IMXDPUV1_CHAN_18;
+	case IMXDPUV1_SHDLD_IDX_CHAN_19:
+		return IMXDPUV1_CHAN_19;
+	case IMXDPUV1_SHDLD_IDX_CHAN_20:
+		return IMXDPUV1_CHAN_20;
+	case IMXDPUV1_SHDLD_IDX_CHAN_21:
+		return IMXDPUV1_CHAN_21;
+	case IMXDPUV1_SHDLD_IDX_CHAN_22:
+		return IMXDPUV1_CHAN_22;
+	case IMXDPUV1_SHDLD_IDX_CHAN_23:
+		return IMXDPUV1_CHAN_23;
+	case IMXDPUV1_SHDLD_IDX_CHAN_24:
+		return IMXDPUV1_CHAN_24;
+	case IMXDPUV1_SHDLD_IDX_CHAN_25:
+		return IMXDPUV1_CHAN_25;
+	case IMXDPUV1_SHDLD_IDX_CHAN_26:
+		return IMXDPUV1_CHAN_26;
+	case IMXDPUV1_SHDLD_IDX_CHAN_27:
+		return IMXDPUV1_CHAN_27;
+	case IMXDPUV1_SHDLD_IDX_CHAN_28:
+		return IMXDPUV1_CHAN_28;
+	case IMXDPUV1_SHDLD_IDX_CHAN_29:
+		return IMXDPUV1_CHAN_29;
+	case IMXDPUV1_SHDLD_IDX_CHAN_30:
+		return IMXDPUV1_CHAN_30;
+	default:
+		return IMXDPUV1_CHANNEL_INVALID;
+	}
+}
+
+
+/*!
+ * This function returns the pointer to the imxdpu structutre
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ * @param       disp		id of the diplay output pipe
+ *
+ * @return      This function returns the pointer to the imxdpu structutre
+ *      	return a NULL pointer for a failure.
+ */
+struct imxdpuv1_soc *imxdpuv1_get_soc(int8_t imxdpuv1_id)
+{
+	/* imxdpuv1_id starts from 0 */
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return NULL;
+	}
+	return &(imxdpuv1_array[imxdpuv1_id]);
+}
+
+/*!
+ * This function enables the interrupt for the specified interrupt line.
+ * The interrupt lines are defined in imxdpuv1_events.h.
+ *
+ * @param	imxdpu		imxdpu instance
+ * @param       irq     	Interrupt line to enable interrupt for.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_enable_irq(int8_t imxdpuv1_id, uint32_t irq)
+{
+	int ret = 0;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+#ifdef DEBUG_IMXDPUV1_IRQ_ERROR
+	if (irq == 0)
+		panic("Trying to enable irq 0!");
+#endif
+	/* imxdpuv1_id starts from 0 */
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	imxdpuv1_clear_irq(imxdpuv1_id, irq);
+	if (irq < IMXDPUV1_INTERRUPT_MAX) {
+		if (irq < 32) {
+			imxdpu->enabled_int[0] |= INTSTAT0_BIT(irq);
+			imxdpuv1_write_irq(imxdpu,
+				IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0,
+				imxdpu->enabled_int[0]);
+		} else if (irq < 64) {
+			imxdpu->enabled_int[1] |= INTSTAT1_BIT(irq);
+			imxdpuv1_write_irq(imxdpu,
+				IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1,
+				imxdpu->enabled_int[1]);
+#ifdef IMXDPUV1_VERSION_0
+		} else {
+			imxdpu->enabled_int[2] |= INTSTAT2_BIT(irq);
+			imxdpuv1_write_irq(imxdpu,
+				IMXDPUV1_COMCTRL_USERINTERRUPTENABLE2,
+				imxdpu->enabled_int[2]);
+#endif
+		}
+	} else {
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+/*!
+ * This function disables the interrupt for the specified interrupt line.g
+ * The interrupt lines are defined in imxdpuv1_events.h.
+ *
+ * @param	imxdpu		imxdpu instance
+ * @param       irq     	Interrupt line to disable interrupt for.
+ *
+ */
+int imxdpuv1_disable_irq(int8_t imxdpuv1_id, uint32_t irq)
+{
+	int ret = 0;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	/* imxdpuv1_id starts from 0 */
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	if (irq < IMXDPUV1_INTERRUPT_MAX) {
+		if (irq < 32) {
+			imxdpu->enabled_int[0] &= ~INTSTAT0_BIT(irq);
+			imxdpuv1_write_irq(imxdpu,
+				IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0,
+				imxdpu->enabled_int[0]);
+		} else if (irq < 64) {
+			imxdpu->enabled_int[1] &= ~INTSTAT1_BIT(irq);
+			imxdpuv1_write_irq(imxdpu,
+				IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1,
+				imxdpu->enabled_int[1]);
+#ifdef IMXDPUV1_VERSION_0
+		} else {
+			imxdpu->enabled_int[2] &= ~INTSTAT2_BIT(irq);
+			imxdpuv1_write_irq(imxdpu,
+				IMXDPUV1_COMCTRL_USERINTERRUPTENABLE2,
+				imxdpu->enabled_int[2]);
+#endif
+		}
+	} else {
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+/*!
+ * This function clears all interrupts.
+ *
+ * @param	imxdpu		imxdpu instance
+ *
+ */
+int imxdpuv1_clear_all_irqs(int8_t imxdpuv1_id)
+{
+	int ret = 0;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	/* imxdpuv1_id starts from 0 */
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	imxdpuv1_write_irq(imxdpu,
+		IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0,
+		IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_USERINTERRUPTCLEAR0_MASK);
+	imxdpuv1_write_irq(imxdpu,
+		IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1,
+		IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_USERINTERRUPTCLEAR1_MASK);
+#ifdef IMXDPUV1_VERSION_0
+	imxdpuv1_write_irq(imxdpu,
+		IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR2,
+		IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR2_USERINTERRUPTCLEAR2_MASK);
+#endif
+#if 1
+	imxdpuv1_write_irq(imxdpu,
+		IMXDPUV1_COMCTRL_INTERRUPTCLEAR0,
+		IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_INTERRUPTCLEAR0_MASK);
+	imxdpuv1_write_irq(imxdpu,
+		IMXDPUV1_COMCTRL_INTERRUPTCLEAR1,
+		IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_INTERRUPTCLEAR1_MASK);
+#ifdef IMXDPUV1_VERSION_0
+	imxdpuv1_write_irq(imxdpu,
+		IMXDPUV1_COMCTRL_INTERRUPTCLEAR2,
+		IMXDPUV1_COMCTRL_INTERRUPTCLEAR2_INTERRUPTCLEAR2_MASK);
+#endif
+#endif
+	return ret;
+}
+
+/*!
+ * This function disables all interrupts.
+ *
+ * @param	imxdpu		imxdpu instance
+ *
+ */
+int imxdpuv1_disable_all_irqs(int8_t imxdpuv1_id)
+{
+	int ret = 0;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	/* imxdpuv1_id starts from 0 */
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0, 0);
+	imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1, 0);
+#ifdef IMXDPUV1_VERSION_0
+	imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE2, 0);
+#endif
+
+#if 1
+	imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_INTERRUPTENABLE0, 0);
+	imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_INTERRUPTENABLE1, 0);
+#ifdef IMXDPUV1_VERSION_0
+	imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_INTERRUPTENABLE2, 0);
+#endif
+#endif
+
+	imxdpu->enabled_int[0] = 0;
+	imxdpu->enabled_int[1] = 0;
+#ifdef IMXDPUV1_VERSION_0
+	imxdpu->enabled_int[2] = 0;
+#endif
+	return ret;
+}
+
+/*!
+ * This function clears the interrupt for the specified interrupt line.
+ * The interrupt lines are defined in ipu_irq_line enum.
+ *
+ * @param	imxdpu  	imxdpu instance
+ * @param       irq     	Interrupt line to clear interrupt for.
+ *
+ */
+int imxdpuv1_clear_irq(int8_t imxdpuv1_id, uint32_t irq)
+{
+	int ret = 0;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	/* imxdpuv1_id starts from 0 */
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	if (irq < IMXDPUV1_INTERRUPT_MAX) {
+		if (irq < 32) {
+			imxdpuv1_write_irq(imxdpu,
+				IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0,
+				1U << irq);
+		}
+		if (irq < 64) {
+			imxdpuv1_write_irq(imxdpu,
+				IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1,
+				1U << (irq - 32));
+#ifdef IMXDPUV1_VERSION_0
+		} else {
+			imxdpuv1_write_irq(imxdpu,
+				IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR2,
+				1U << (irq - 64));
+#endif
+		}
+	} else {
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+/*!
+ * This function initializes the imxdpu interrupts
+ *
+ * @param	imxdpu  	imxdpu instance
+ *
+ */
+int imxdpuv1_init_irqs(int8_t imxdpuv1_id)
+{
+	int ret = 0;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	/* imxdpuv1_id starts from 0 */
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	imxdpuv1_disable_all_irqs(imxdpuv1_id);
+	imxdpuv1_clear_all_irqs(imxdpuv1_id);
+
+	/* Set all irq to user mode */
+	imxdpuv1_write_irq(imxdpu,
+		IMXDPUV1_COMCTRL_USERINTERRUPTMASK0,
+		IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_USERINTERRUPTMASK0_MASK);
+	imxdpuv1_write_irq(imxdpu,
+		IMXDPUV1_COMCTRL_USERINTERRUPTMASK1,
+		IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_USERINTERRUPTMASK1_MASK);
+#ifdef IMXDPUV1_VERSION_0
+	imxdpuv1_write_irq(imxdpu,
+		IMXDPUV1_COMCTRL_USERINTERRUPTMASK2,
+		IMXDPUV1_COMCTRL_USERINTERRUPTMASK2_USERINTERRUPTMASK2_MASK);
+#endif
+	/* enable needed interupts */
+	imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_EXTDST0_SHDLOAD_IRQ);
+	imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_EXTDST1_SHDLOAD_IRQ);
+	imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ);
+	imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ);
+
+#ifdef IMXDPUV1_VERSION_0
+	imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE4_SHDLOAD_IRQ);
+	imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE5_SHDLOAD_IRQ);
+	imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE4_SEQCOMPLETE_IRQ);
+	imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE5_SEQCOMPLETE_IRQ);
+	imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE4_FRAMECOMPLETE_IRQ);
+	imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE5_FRAMECOMPLETE_IRQ);
+#endif
+	/* enable the frame interrupts as IMXDPUV1_IRQF_ONESHOT */
+	imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_FRAMEGEN0_INT0_IRQ);
+	imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_FRAMEGEN1_INT0_IRQ);
+
+	imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_COMCTRL_SW0_IRQ);
+	imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_COMCTRL_SW1_IRQ);
+
+	imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ);
+	imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_DISENGCFG_SHDLOAD1_IRQ);
+
+	IMXDPUV1_TRACE("%s() enabled_int[0] 0x%08x\n", __func__,
+		imxdpu->enabled_int[0]);
+	IMXDPUV1_TRACE("%s() enabled_int[1] 0x%08x\n", __func__,
+		imxdpu->enabled_int[1]);
+#ifdef IMXDPUV1_VERSION_0
+	IMXDPUV1_TRACE("%s() enabled_int[2] 0x%08x\n", __func__,
+		imxdpu->enabled_int[2]);
+#endif
+	return ret;
+}
+
+/*!
+ * This function checks pending shadow loads
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ * @param       disp		id of the diplay output pipe
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_disp_check_shadow_loads(int8_t imxdpuv1_id, int8_t disp)
+{
+	int ret = 0;
+	uint32_t addr_extdst = IMXDPUV1_OFFSET_INVALID; /* address for extdst */
+	uint32_t extdst = 0;
+	uint32_t extdst_stat = 0;
+	uint32_t fgen = 1;
+	uint32_t fgen_stat = 0;
+	uint32_t sub = 0;
+	uint32_t sub_stat = 0;
+	uint32_t stat;
+
+	int32_t i;
+
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE_IRQ("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	stat = imxdpuv1_read_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0);
+	if (disp == 0) {
+		addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST;
+		if (stat & IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ) {
+			fgen = 0;
+		}
+	} else if (disp == 1) {
+		addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST;
+		if (stat & IMXDPUV1_DISENGCFG_SHDLOAD1_IRQ) {
+			fgen = 0;
+		}
+	} else {
+		return -EINVAL;
+	}
+
+	sub |= (imxdpuv1_read(imxdpu, IMXDPUV1_FETCHLAYER0_TRIGGERENABLE)) & 0xff;
+#ifdef IMXDPUV1_VERSION_0
+	sub |= (imxdpuv1_read(imxdpu, IMXDPUV1_FETCHLAYER1_TRIGGERENABLE) << 8) & 0xff00;
+#endif
+	sub |= (imxdpuv1_read(imxdpu, IMXDPUV1_FETCHWARP2_TRIGGERENABLE) << 16) & 0xff0000;
+	extdst = imxdpuv1_read(imxdpu, addr_extdst);
+
+	/* this loop may need to be optimized */
+	for (i = 0; i < IMXDPUV1_SHDLD_IDX_CHAN_00; i++) {
+		if (imxdpu->shadow_load_state[disp][i].state.complete) {
+			if (imxdpu->shadow_load_state[disp][i].state.trys > 0) {
+				IMXDPUV1_TRACE_IRQ
+					("shadow index complete after retry: index %d trys %d\n",
+					i,
+					imxdpu->shadow_load_state[disp][i].
+					state.trys);
+			} else {
+				IMXDPUV1_TRACE_IRQ("shadow index complete: index %d\n", i);
+			}
+			imxdpu->shadow_load_state[disp][i].word = 0;
+		} else if (imxdpu->shadow_load_state[disp][i].state.processing) {
+			if (i > IMXDPUV1_SHDLD_IDX_CONST1) {
+				if (!(extdst & trigger_list[i].extdst) && !fgen) {
+					imxdpu->shadow_load_state[disp][i].
+						state.complete = 1;
+				} else {
+					extdst_stat |= trigger_list[i].extdst;
+					fgen_stat |= 1 << i;
+				}
+			} else if (!(extdst & trigger_list[i].extdst)) {
+				imxdpu->shadow_load_state[disp][i].
+					state.complete = 1;
+			} else {
+				imxdpu->shadow_load_state[disp][i].state.trys++;
+				extdst |= trigger_list[i].extdst;
+				IMXDPUV1_TRACE_IRQ
+					("shadow index retry: index %d trys %d\n",
+					i,
+					imxdpu->shadow_load_state[disp][i].
+					state.trys);
+			}
+		}
+	}
+
+
+	for (i = IMXDPUV1_SHDLD_IDX_CHAN_00; i < IMXDPUV1_SHDLD_IDX_MAX; i++) {
+		if (imxdpu->shadow_load_state[disp][i].state.complete) {
+
+			if (imxdpu->shadow_load_state[disp][i].state.trys > 0) {
+				IMXDPUV1_TRACE_IRQ
+					("shadow index complete after retry: index %d trys %d\n",
+					i,
+					imxdpu->shadow_load_state[disp][i].
+					state.trys);
+			} else {
+				IMXDPUV1_TRACE_IRQ("shadow index complete: index %d\n", i);
+			}
+			imxdpu->shadow_load_state[disp][i].word = 0;
+		} else if (imxdpu->shadow_load_state[disp][i].state.processing) {
+			/* fetch layer and fetchwarp */
+			if ((trigger_list[i].extdst != 0) &&
+				(trigger_list[i].sub != 0)) {
+				if (!(extdst & trigger_list[i].extdst) &&
+					!(sub & trigger_list[i].sub)) {
+					imxdpu->shadow_load_state[disp][i].
+						state.complete = 1;
+				} else {
+					extdst_stat |= trigger_list[i].extdst;
+					sub_stat |= trigger_list[i].sub;
+				}
+			} else if (!(extdst & trigger_list[i].extdst)) {
+				imxdpu->shadow_load_state[disp][i].
+					state.complete = 1;
+			} else {
+				imxdpu->shadow_load_state[disp][i].state.trys++;
+				extdst_stat |= trigger_list[i].extdst;
+				IMXDPUV1_TRACE_IRQ
+					("shadow index retry: index %d trys %d\n",
+					i,
+					imxdpu->shadow_load_state[disp][i].
+					state.trys);
+			}
+		}
+	}
+
+	if ((extdst_stat == 0) && (sub_stat == 0) && (fgen_stat == 0)) {
+		/* clear interrupt */
+		IMXDPUV1_TRACE_IRQ("shadow requests are complete.\n");
+	} else {
+		IMXDPUV1_TRACE_IRQ
+			("shadow requests are not complete: extdst 0x%08x, sub 0x%08x, fgen 0x%08x\n",
+			extdst, sub, fgen);
+		IMXDPUV1_TRACE_IRQ
+			("shadow requests are not complete: extdst_stat 0x%08x, sub_stat 0x%08x, fgen_stat 0x%08x\n",
+			extdst_stat, sub_stat, fgen_stat);
+	}
+
+	return ret;
+}
+
+/*!
+ * This function starts pending shadow loads
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ * @param       disp		id of the diplay output pipe
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+static int imxdpuv1_disp_start_shadow_loads(int8_t imxdpuv1_id, int8_t disp)
+{
+	int ret = 0;
+	uint32_t addr_extdst;   /* address for extdst */
+	uint32_t addr_fgen; /* address for frame generator */
+	uint32_t extdst = 0;
+	uint32_t fgen = 0;
+	uint32_t sub = 0;
+	int32_t i;
+
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE_IRQ("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	if (disp == 0) {
+		addr_fgen = IMXDPUV1_FRAMEGEN0_FGSLR;
+		addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST;
+
+	} else if (disp == 1) {
+		addr_fgen = IMXDPUV1_FRAMEGEN1_FGSLR;
+		addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST;
+	} else {
+		return -EINVAL;
+	}
+
+	/* this loop may need to be optimized */
+	for (i = 0; i < IMXDPUV1_SHDLD_IDX_CHAN_00; i++) {
+		if (imxdpu->shadow_load_state[disp][i].state.request &&
+			(imxdpu->shadow_load_state[disp][i].state.processing == 0)) {
+			imxdpu->shadow_load_state[disp][i].state.processing = 1;
+			extdst |= trigger_list[i].extdst;
+			/* only trigger frame generator for const frames*/
+			if (i >= IMXDPUV1_SHDLD_IDX_CONST0) {
+				fgen |= 1;
+			}
+		}
+	}
+	for (i = IMXDPUV1_SHDLD_IDX_CHAN_00; i < IMXDPUV1_SHDLD_IDX_MAX; i++) {
+		if (imxdpu->shadow_load_state[disp][i].state.request &&
+			(imxdpu->shadow_load_state[disp][i].state.processing == 0)) {
+			imxdpu->shadow_load_state[disp][i].state.processing = 1;
+			/*todo: need a completion handler */
+			extdst |= trigger_list[i].extdst;
+			sub |= trigger_list[i].sub;
+		}
+	}
+
+	if (sub) {
+		IMXDPUV1_TRACE_IRQ("Fetch layer shadow request 0x%08x\n", sub);
+		if (sub & 0xff) {   /* FETCHLAYER0 */
+			imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_TRIGGERENABLE,
+				sub & 0xff);
+		}
+#ifdef IMXDPUV1_VERSION_0
+		if (sub & 0xff00) { /* FETCHLAYER1 */
+			imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_TRIGGERENABLE,
+				(sub >> 8) & 0xff);
+		}
+#endif
+		if (sub & 0xff0000) {   /* FETCHWARP2 */
+			imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_TRIGGERENABLE,
+				(sub >> 16) & 0xff);
+		}
+	}
+
+	if (extdst) {
+		IMXDPUV1_TRACE_IRQ("Extdst shadow request  0x%08x\n", extdst);
+		imxdpuv1_write(imxdpu, addr_extdst, extdst);
+	}
+
+	if (fgen) {
+		IMXDPUV1_TRACE_IRQ("Fgen shadow request  0x%08x\n", fgen);
+		imxdpuv1_write(imxdpu, addr_fgen, fgen);
+	}
+
+	return ret;
+}
+
+/*!
+ * This function handles the VYNC interrupt for a display
+ *
+ * @param	imxdpu		imxdpu instance
+ * @param	disp		display index
+ *
+ */
+static void imxdpuv1_disp_vsync_handler(int8_t imxdpuv1_id, int8_t disp)
+{
+	IMXDPUV1_TRACE_IRQ("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return;
+	}
+	if (!((disp == 0) || (disp == 1)))
+		return;
+
+	/* send notifications
+	   shadow load finished
+	 */
+
+	imxdpuv1_disp_start_shadow_loads(imxdpuv1_id, disp);
+	imxdpuv1_disp_update_fgen_status(imxdpuv1_id, disp);
+
+	return;
+
+}
+
+/*!
+ * This function calls a register handler for an interrupt
+ *
+ * @param	imxdpu		imxdpu instance
+ * @param	irq		interrupt line
+ *
+ */
+static void imxdpuv1_handle_registered_irq(int8_t imxdpuv1_id, int8_t irq)
+{
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE_IRQ("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	if ((irq < 0) || (irq >= IMXDPUV1_INTERRUPT_MAX))
+		return;
+
+	if (imxdpu->irq_list[irq].handler == NULL)
+		return;
+
+	imxdpu->irq_list[irq].handler(irq, imxdpu->irq_list[irq].data);
+
+	if ((imxdpu->irq_list[irq].flags & IMXDPUV1_IRQF_ONESHOT) != 0) {
+		imxdpuv1_disable_irq(imxdpuv1_id, irq);
+		imxdpuv1_clear_irq(imxdpuv1_id, irq);
+	}
+	return;
+
+}
+
+/* todo: this irq handler assumes all irq are ORed together.
+     The irqs may be grouped so this function can be
+     optimized if that is the case*/
+/*!
+ * This function processes all IRQs for the IMXDPU
+ *
+ * @param	data	pointer to the imxdpu structure
+ *
+ */
+int imxdpuv1_handle_irq(int32_t imxdpuv1_id)
+{
+	uint32_t int_stat[3];
+	uint32_t int_temp[3];
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE_IRQ("%s()\n", __func__);
+
+
+	/* imxdpuv1_id starts from 0 */
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		IMXDPUV1_TRACE_IRQ("%s(): invalid imxdpuv1_id\n", __func__);
+#ifdef DEBUG_IMXDPUV1_IRQ_ERROR
+		panic("wrong imxdpuv1_id");
+#endif
+		return IMXDPUV1_FALSE;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	imxdpu->irq_count++;
+
+#ifdef DEBUG_IMXDPUV1_IRQ_ERROR
+	{
+		uint32_t int_enable0;
+		int_enable0 = imxdpuv1_read_irq(imxdpu,
+			IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0);
+		if (int_enable0 & 1) {
+			panic("IRQ0 enabled\n");
+		}
+		if (imxdpu->enabled_int[0] & 1) {
+			panic("IRQ0 in enabled_int is set\n");
+		}
+	}
+#endif
+	/* Get and clear interrupt status */
+	int_temp[0] =
+		imxdpuv1_read_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0);
+	int_stat[0] = imxdpu->enabled_int[0] & int_temp[0];
+	int_temp[1] =
+		imxdpuv1_read_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1);
+	int_stat[1] = imxdpu->enabled_int[1] & int_temp[1];
+#ifdef IMXDPUV1_VERSION_0
+#ifdef IMXDPUV1_ENABLE_INTSTAT2
+	/* Enable this  (IMXDPUV1_ENABLE_INTSTAT2) if intstat2 interrupts
+	   are needed */
+	int_temp[2] =
+		imxdpuv1_read_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS2);
+	int_stat[2] = imxdpu->enabled_int[2] & int_temp[2];
+#endif
+#endif
+	/* No interrupts are pending */
+	if ((int_temp[0] == 0) && (int_temp[1] == 0)
+#ifdef IMXDPUV1_VERSION_0
+#ifdef IMXDPUV1_ENABLE_INTSTAT2
+		&& (int_temp[2] == 0)
+#endif
+#endif
+		) {
+	}
+
+	/* No enabled interrupts are pending */
+	if ((int_stat[0] == 0) && (int_stat[1] == 0)
+#ifdef IMXDPUV1_ENABLE_INTSTAT2
+		&& (int_stat[2] == 0)
+#endif
+		) {
+		IMXDPUV1_TRACE_IRQ
+			("Error: No enabled interrupts, 0x%08x 0x%08x\n",
+			int_temp[0] & ~imxdpu->enabled_int[0],
+			int_temp[1] & ~imxdpu->enabled_int[1]);
+#ifdef DEBUG_IMXDPUV1_IRQ_ERROR
+		panic("no enabled IMXDPU interrupts");
+#endif
+
+		return IMXDPUV1_FALSE;
+	}
+
+	/* Clear the enabled interrupts */
+	if (int_stat[0]) {
+		imxdpuv1_write_irq(imxdpu,
+			IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0,
+			int_stat[0]);
+	}
+	if (int_stat[1]) {
+		imxdpuv1_write_irq(imxdpu,
+			IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1,
+			int_stat[1]);
+	}
+#ifdef IMXDPUV1_ENABLE_INTSTAT2
+	if (int_stat[2]) {
+		imxdpuv1_write_irq(imxdpu,
+			IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR2,
+			int_stat[2]);
+	}
+#endif
+
+#ifdef IMXDPUV1_ENABLE_INTSTAT2
+	if (int_stat[1] != 0) {
+		/* add int_stat[2] if needed */
+	}
+#endif
+#ifdef IMXDPUV1_VERSION_0
+       /* now handle the interrupts that are pending */
+	if (int_stat[0] != 0) {
+		if (int_stat[0] & 0xff) {
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_STORE9_SHDLOAD_IRQ)) {
+				IMXDPUV1_TRACE_IRQ
+				    ("IMXDPUV1_STORE9_SHDLOAD_IRQ irq\n");
+				imxdpuv1_be_irq_handler(imxdpuv1_id,
+							     IMXDPUV1_STORE9_SHDLOAD_IRQ);
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+							     IMXDPUV1_STORE9_SHDLOAD_IRQ);
+			}
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ)) {
+				IMXDPUV1_TRACE_IRQ
+				    ("IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ irq\n");
+				imxdpuv1_be_irq_handler(imxdpuv1_id,
+							     IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ);
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+							     IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ);
+			}
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_STORE9_SEQCOMPLETE_IRQ)) {
+				IMXDPUV1_TRACE_IRQ
+				    ("IMXDPUV1_STORE9_SEQCOMPLETE_IRQ irq\n");
+				imxdpuv1_be_irq_handler(imxdpuv1_id,
+							     IMXDPUV1_STORE9_SEQCOMPLETE_IRQ);
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+							     IMXDPUV1_STORE9_SEQCOMPLETE_IRQ);
+			}
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_EXTDST0_SHDLOAD_IRQ)) {
+				IMXDPUV1_TRACE_IRQ
+					("IMXDPUV1_EXTDST0_SHDLOAD_IRQ irq\n");
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_EXTDST0_SHDLOAD_IRQ);
+			}
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ)) {
+				IMXDPUV1_TRACE_IRQ
+					("IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ\n");
+				/* todo: move */
+				imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 0);
+
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ);
+			}
+		}
+		if (int_stat[0] & 0xff00) {
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_EXTDST1_SHDLOAD_IRQ)) {
+				IMXDPUV1_TRACE_IRQ(
+					"IMXDPUV1_EXTDST1_SHDLOAD_IRQ irq\n");
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_EXTDST1_SHDLOAD_IRQ);
+			}
+			if (int_stat[0] &
+				INTSTAT0_BIT(
+					IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ)) {
+				IMXDPUV1_TRACE_IRQ(
+					"IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ\n");
+				/* todo: move */
+				imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 1);
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ);
+			}
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_STORE4_SHDLOAD_IRQ)) {
+				IMXDPUV1_TRACE_IRQ_CAPTURE("IMXDPUV1_STORE4_SHDLOAD_IRQ\n");
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_STORE4_SHDLOAD_IRQ);
+			}
+		}
+		if (int_stat[0] & 0xff0000) {
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_STORE4_FRAMECOMPLETE_IRQ)) {
+				IMXDPUV1_TRACE_IRQ_CAPTURE(
+					"IMXDPUV1_STORE4_FRAMECOMPLETE_IRQ\n");
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_STORE4_FRAMECOMPLETE_IRQ);
+			}
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_STORE4_SEQCOMPLETE_IRQ)) {
+				IMXDPUV1_TRACE_IRQ_CAPTURE(
+					"IMXDPUV1_STORE4_SEQCOMPLETE_IRQ\n");
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_STORE4_SEQCOMPLETE_IRQ);
+			}
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_HISTOGRAM4_VALID_IRQ)) {
+				IMXDPUV1_TRACE_IRQ(
+					"IMXDPUV1_HISTOGRAM4_VALID_IRQ\n");
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_HISTOGRAM4_VALID_IRQ);
+			}
+		}
+		if (int_stat[0] & 0xff000000) {
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_HISTOGRAM5_VALID_IRQ)) {
+				IMXDPUV1_TRACE_IRQ(
+					"IMXDPUV1_HISTOGRAM5_VALID_IRQ\n");
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_HISTOGRAM5_VALID_IRQ);
+			}
+			if (int_stat[1] &
+				INTSTAT0_BIT(IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ)) {
+				IMXDPUV1_PRINT
+					("IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ irq\n");
+				imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 0);
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ);
+			}
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_IRQ)) {
+				IMXDPUV1_TRACE_IRQ(
+					"IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_IRQ\n");
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_IRQ);
+			}
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_FRAMEGEN0_INT0_IRQ)) {
+				IMXDPUV1_TRACE_IRQ(
+					"IMXDPUV1_FRAMEGEN0_INT0_IRQ\n");
+				imxdpuv1_disp_vsync_handler(imxdpuv1_id, 0);
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_FRAMEGEN0_INT0_IRQ);
+			}
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_FRAMEGEN0_INT1_IRQ)) {
+				IMXDPUV1_TRACE_IRQ(
+					"IMXDPUV1_FRAMEGEN0_INT1_IRQ\n");
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_FRAMEGEN0_INT1_IRQ);
+			}
+		}
+	}
+
+	if (int_stat[1] != 0) {
+		if (int_stat[1] & 0xff) {
+
+		}
+		if (int_stat[1] & 0xff00) {
+			if (int_stat[1] &
+				INTSTAT1_BIT(IMXDPUV1_FRAMEGEN1_INT0_IRQ)) {
+				IMXDPUV1_TRACE_IRQ(
+					"IMXDPUV1_FRAMEGEN1_INT0_IRQ\n");
+				imxdpuv1_disp_vsync_handler(imxdpuv1_id, 1);
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_FRAMEGEN1_INT0_IRQ);
+			}
+		}
+		if (int_stat[0] & 0xff0000) {
+			if (int_stat[0] &
+				INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW0_IRQ)) {
+				IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW0_IRQ\n");
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_COMCTRL_SW0_IRQ);
+			}
+			if (int_stat[1] & INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW2_IRQ)) {
+				IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW2_IRQ\n");
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_COMCTRL_SW2_IRQ);
+			}
+			if (int_stat[1] & INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW3_IRQ)) {
+				IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW3_IRQ\n");
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_COMCTRL_SW3_IRQ);
+			}
+
+		}
+	}
+#else
+       /* now handle the interrupts that are pending */
+	if (int_stat[0] != 0) {
+		if (int_stat[0] & 0xff) {
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_STORE9_SHDLOAD_IRQ)) {
+				IMXDPUV1_TRACE_IRQ
+				    ("IMXDPUV1_STORE9_SHDLOAD_IRQ irq\n");
+				imxdpuv1_be_irq_handler(imxdpuv1_id,
+							     IMXDPUV1_STORE9_SHDLOAD_IRQ);
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+							     IMXDPUV1_STORE9_SHDLOAD_IRQ);
+			}
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ)) {
+				IMXDPUV1_TRACE_IRQ
+				    ("IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ irq\n");
+				imxdpuv1_be_irq_handler(imxdpuv1_id,
+							     IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ);
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+							     IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ);
+			}
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_STORE9_SEQCOMPLETE_IRQ)) {
+				IMXDPUV1_TRACE_IRQ
+				    ("IMXDPUV1_STORE9_SEQCOMPLETE_IRQ irq\n");
+				imxdpuv1_be_irq_handler(imxdpuv1_id,
+							     IMXDPUV1_STORE9_SEQCOMPLETE_IRQ);
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+							     IMXDPUV1_STORE9_SEQCOMPLETE_IRQ);
+			}
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_EXTDST0_SHDLOAD_IRQ)) {
+				IMXDPUV1_TRACE_IRQ
+					("IMXDPUV1_EXTDST0_SHDLOAD_IRQ irq\n");
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_EXTDST0_SHDLOAD_IRQ);
+			}
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ)) {
+				IMXDPUV1_TRACE_IRQ
+					("IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ\n");
+				/* todo: move */
+				imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 0);
+
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ);
+			}
+		}
+		if (int_stat[0] & 0xff00) {
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_EXTDST1_SHDLOAD_IRQ)) {
+				IMXDPUV1_TRACE_IRQ(
+					"IMXDPUV1_EXTDST1_SHDLOAD_IRQ irq\n");
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_EXTDST1_SHDLOAD_IRQ);
+			}
+			if (int_stat[0] &
+				INTSTAT0_BIT(
+					IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ)) {
+				IMXDPUV1_TRACE_IRQ(
+					"IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ\n");
+				/* todo: move */
+				imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 1);
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ);
+			}
+		}
+		if (int_stat[0] & 0xff0000) {
+			if (int_stat[0] &
+				INTSTAT0_BIT(IMXDPUV1_FRAMEGEN0_INT0_IRQ)) {
+				IMXDPUV1_TRACE_IRQ(
+					"IMXDPUV1_FRAMEGEN0_INT0_IRQ\n");
+				imxdpuv1_disp_vsync_handler(imxdpuv1_id, 0);
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_FRAMEGEN0_INT0_IRQ);
+			}
+
+		}
+		if (int_stat[0] & 0xff000000) {
+			if (int_stat[1] &
+			    INTSTAT0_BIT(IMXDPUV1_FRAMEGEN1_INT0_IRQ)) {
+				IMXDPUV1_TRACE_IRQ(
+					"IMXDPUV1_FRAMEGEN1_INT0_IRQ\n");
+				imxdpuv1_disp_vsync_handler(imxdpuv1_id, 1);
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_FRAMEGEN1_INT0_IRQ);
+			}
+		}
+	}
+
+	if (int_stat[1] != 0) {
+		if (int_stat[1] & 0xff) {
+			if (int_stat[0] &
+			    INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW0_IRQ)) {
+				IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW0_IRQ\n");
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_COMCTRL_SW0_IRQ);
+			}
+			if (int_stat[1] & INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW2_IRQ)) {
+				IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW2_IRQ\n");
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_COMCTRL_SW2_IRQ);
+			}
+		}
+		if (int_stat[1] & 0xff00) {
+			if (int_stat[1] & INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW3_IRQ)) {
+				IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW3_IRQ\n");
+				imxdpuv1_handle_registered_irq(imxdpuv1_id,
+					IMXDPUV1_COMCTRL_SW3_IRQ);
+			}
+		}
+		if (int_stat[0] & 0xff0000) {
+			/* Reserved for command sequencer debug */
+		}
+	}
+#endif
+	return IMXDPUV1_TRUE;
+}
+
+/*!
+ * This function registers an interrupt handler function for the specified
+ * irq line. The interrupt lines are defined in imxdpuv1_events.h
+ *
+ * @param	imxdpu		imxdpu instance
+ * @param       irq     	Interrupt line to get status for.
+ *
+ * @param       handler 	Input parameter for address of the handler
+ *      			function.
+ *
+ * @param       irq_flags       Flags for interrupt mode. Currently not used.
+ *
+ * @param       devname 	Input parameter for string name of driver
+ *      			registering the handler.
+ *
+ * @param       data    	Input parameter for pointer of data to be
+ *      			passed to the handler.
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_request_irq(int8_t imxdpuv1_id,
+	uint32_t irq,
+	int (*handler)(int, void *),
+	uint32_t irq_flags, const char *devname, void *data)
+{
+	int ret = 0;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	/* imxdpuv1_id starts from 0 */
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	if (imxdpu->irq_list[irq].handler != NULL) {
+		IMXDPUV1_TRACE("handler already installed on irq %d\n", irq);
+		ret = -EINVAL;
+		goto out;
+	}
+
+	imxdpu->irq_list[irq].handler = handler;
+	imxdpu->irq_list[irq].flags = irq_flags;
+	imxdpu->irq_list[irq].data = data;
+	imxdpu->irq_list[irq].name = devname;
+
+	/* Clear and enable the IRQ */
+	imxdpuv1_clear_irq(imxdpuv1_id, irq);
+	/* Don't enable if a one shot */
+	if ((imxdpu->irq_list[irq].flags & IMXDPUV1_IRQF_ONESHOT) == 0)
+		imxdpuv1_enable_irq(imxdpuv1_id, irq);
+out:
+	return ret;
+}
+
+/*!
+ * This function unregisters an interrupt handler for the specified interrupt
+ * line. The interrupt lines are defined in imxdpuv1_events.h
+ *
+ * @param       imxdpu		imxdpu instance
+ * @param       irq     	Interrupt line to get status for.
+ *
+ * @param       data          Input parameter for pointer of data to be passed
+ *      			to the handler. This must match value passed to
+ *      			ipu_request_irq().
+ *
+ */
+int imxdpuv1_free_irq(int8_t imxdpuv1_id, uint32_t irq, void *data)
+{
+	int ret = 0;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	/* imxdpuv1_id starts from 0 */
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	imxdpuv1_disable_irq(imxdpuv1_id, irq);
+	imxdpuv1_clear_irq(imxdpuv1_id, irq);
+	if (imxdpu->irq_list[irq].data == data)
+		memset(&imxdpu->irq_list[irq], 0, sizeof(imxdpu->irq_list[irq]));
+
+	return ret;
+}
+
+/*!
+ * This function un-initializes the imxdpu interrupts
+ *
+ * @param	imxdpu  	imxdpu instance
+ *
+ */
+int imxdpuv1_uninit_interrupts(int8_t imxdpuv1_id)
+{
+	int ret = 0;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	/* imxdpuv1_id starts from 0 */
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	imxdpu->enabled_int[0] = 0;
+	imxdpu->enabled_int[1] = 0;
+#ifdef IMXDPUV1_VERSION_0
+	imxdpu->enabled_int[2] = 0;
+#endif
+	imxdpuv1_clear_all_irqs(imxdpuv1_id);
+
+	/* Set all interrupt to user mode */
+	imxdpuv1_write(imxdpu,
+		IMXDPUV1_COMCTRL_USERINTERRUPTMASK0,
+		IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_USERINTERRUPTMASK0_MASK);
+	imxdpuv1_write(imxdpu,
+		IMXDPUV1_COMCTRL_USERINTERRUPTMASK1,
+		IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_USERINTERRUPTMASK1_MASK);
+#ifdef IMXDPUV1_VERSION_0
+	imxdpuv1_write(imxdpu,
+		IMXDPUV1_COMCTRL_USERINTERRUPTMASK2,
+		IMXDPUV1_COMCTRL_USERINTERRUPTMASK2_USERINTERRUPTMASK2_MASK);
+#endif
+	/* Set all interrupts to user mode. this will to change to
+	   enable panic mode */
+	imxdpuv1_write(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0, 0);
+	imxdpuv1_write(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1, 0);
+#ifdef IMXDPUV1_VERSION_0
+	imxdpuv1_write(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE2, 0);
+#endif
+	/* enable needed interupts */
+	return ret;
+}
+
+/*!
+ * This function initializes the imxdpu and the required data structures
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+/* todo: replace with probe function or call from probe
+   use device tree as needed */
+int imxdpuv1_init(int8_t imxdpuv1_id)
+{
+	int ret = 0;
+	int i;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	/* todo: add resource mapping for xrdc, layers, blit, display, ... */
+
+	/* imxdpuv1_id starts from 0 */
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+
+	/* Map the channels to display streams
+	   todo:
+	   make this mapping dynamic
+	   add channel features
+	   map capture channels
+	 */
+	for (i = IMXDPUV1_CHAN_IDX_IN_FIRST; i < IMXDPUV1_CHAN_IDX_MAX; i++) {
+		if (i <= IMXDPUV1_CHAN_IDX_17)
+			imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 0;
+		else if (i < IMXDPUV1_CHAN_IDX_IN_MAX)
+			imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 1;
+		else if (i < IMXDPUV1_CHAN_IDX_OUT_FIRST)
+			imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 0;
+		else if (i < IMXDPUV1_CHAN_IDX_OUT_MAX)
+			imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 1;
+		else
+			imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 0;
+	}
+
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+	imxdpu->irq_count = 0;
+
+	if (imxdpuv1_id == 0) {
+		imxdpu->base = (void __iomem *)IMXDPUV1_REGS_BASE_PHY0;
+		IMXDPUV1_TRACE("%s(): virtual base address is 0x%p (0x%08x physical)\n",
+			__func__, imxdpu->base, IMXDPUV1_REGS_BASE_PHY0);
+
+	} else if (imxdpuv1_id == 1) {
+		imxdpu->base = (void __iomem *)IMXDPUV1_REGS_BASE_PHY1;
+		IMXDPUV1_TRACE("%s(): virtual base address is 0x%p (0x%08x physical)\n",
+			__func__, imxdpu->base, IMXDPUV1_REGS_BASE_PHY1);
+
+	} else {
+		return -ENOMEM;
+	}
+
+	/* todo: may need to check resource allocaiton/ownership for these */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0,
+		IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1,
+		IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2,
+		IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3,
+		IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4,
+		IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5,
+		IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6,
+		IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7,
+		IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_TRIGGERENABLE,
+		IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_RESET_VALUE);
+#ifdef IMXDPUV1_VERSION_0
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY0,
+		IMXDPUV1_FETCHLAYER1_LAYERPROPERTY0_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY1,
+		IMXDPUV1_FETCHLAYER1_LAYERPROPERTY1_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY2,
+		IMXDPUV1_FETCHLAYER1_LAYERPROPERTY2_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY3,
+		IMXDPUV1_FETCHLAYER1_LAYERPROPERTY3_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY4,
+		IMXDPUV1_FETCHLAYER1_LAYERPROPERTY4_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY5,
+		IMXDPUV1_FETCHLAYER1_LAYERPROPERTY5_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY6,
+		IMXDPUV1_FETCHLAYER1_LAYERPROPERTY6_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY7,
+		IMXDPUV1_FETCHLAYER1_LAYERPROPERTY7_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_TRIGGERENABLE,
+		IMXDPUV1_FETCHLAYER1_TRIGGERENABLE_RESET_VALUE);
+#endif
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY0,
+		IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY1,
+		IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY2,
+		IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY3,
+		IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY4,
+		IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY5,
+		IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY6,
+		IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY7,
+		IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RESET_VALUE);
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_TRIGGERENABLE,
+		IMXDPUV1_FETCHWARP2_TRIGGERENABLE_RESET_VALUE);
+
+	/* Initial StaticControl configuration - reset values */
+	/* IMXDPUV1_FETCHDECODE9_STATICCONTROL  */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE9_STATICCONTROL,
+		IMXDPUV1_FETCHDECODE9_STATICCONTROL_RESET_VALUE);
+#ifdef IMXDPUV1_VERSION_0
+	/* IMXDPUV1_FETCHPERSP9_STATICCONTROL   */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHPERSP9_STATICCONTROL,
+		IMXDPUV1_FETCHPERSP9_STATICCONTROL_RESET_VALUE);
+#else
+	/* IMXDPUV1_FETCHPERSP9_STATICCONTROL   */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP9_STATICCONTROL,
+		IMXDPUV1_FETCHWARP9_STATICCONTROL_RESET_VALUE);
+#endif
+
+	/* IMXDPUV1_FETCHECO9_STATICCONTROL     */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO9_STATICCONTROL,
+		IMXDPUV1_FETCHECO9_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_ROP9_STATICCONTROL          */
+	imxdpuv1_write(imxdpu, IMXDPUV1_ROP9_STATICCONTROL,
+		IMXDPUV1_ROP9_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_CLUT9_STATICCONTROL         */
+	imxdpuv1_write(imxdpu, IMXDPUV1_CLUT9_STATICCONTROL,
+		IMXDPUV1_CLUT9_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_MATRIX9_STATICCONTROL       */
+	imxdpuv1_write(imxdpu, IMXDPUV1_MATRIX9_STATICCONTROL,
+		IMXDPUV1_MATRIX9_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_HSCALER9_STATICCONTROL      */
+	imxdpuv1_write(imxdpu, IMXDPUV1_HSCALER9_STATICCONTROL,
+		IMXDPUV1_HSCALER9_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_VSCALER9_STATICCONTROL      */
+	imxdpuv1_write(imxdpu, IMXDPUV1_VSCALER9_STATICCONTROL,
+		IMXDPUV1_VSCALER9_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_FILTER9_STATICCONTROL       */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FILTER9_STATICCONTROL,
+		IMXDPUV1_FILTER9_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_BLITBLEND9_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_BLITBLEND9_STATICCONTROL,
+		IMXDPUV1_BLITBLEND9_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_STORE9_STATICCONTROL        */
+	imxdpuv1_write(imxdpu, IMXDPUV1_STORE9_STATICCONTROL,
+		IMXDPUV1_STORE9_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_CONSTFRAME0_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_CONSTFRAME0_STATICCONTROL,
+		IMXDPUV1_CONSTFRAME0_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_EXTDST0_STATICCONTROL        */
+	imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST0_STATICCONTROL,
+		IMXDPUV1_EXTDST0_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_EXTDST4_STATICCONTROL        */
+	imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST4_STATICCONTROL,
+		IMXDPUV1_EXTDST4_STATICCONTROL_RESET_VALUE);
+
+	/* todo: IMXDPUV1_CONSTFRAME4_STATICCONTROL    */
+
+	/* IMXDPUV1_CONSTFRAME1_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_CONSTFRAME1_STATICCONTROL,
+		IMXDPUV1_CONSTFRAME1_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_EXTDST1_STATICCONTROL        */
+	imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST1_STATICCONTROL,
+		IMXDPUV1_EXTDST1_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_EXTDST5_STATICCONTROL        */
+	imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST5_STATICCONTROL,
+		IMXDPUV1_EXTDST5_STATICCONTROL_RESET_VALUE);
+
+	/* todo: IMXDPUV1_CONSTFRAME5_STATICCONTROL    */
+#ifdef IMXDPUV1_VERSION_0
+	/* IMXDPUV1_EXTSRC4_STATICCONTROL        */
+	imxdpuv1_write(imxdpu, IMXDPUV1_EXTSRC4_STATICCONTROL,
+		IMXDPUV1_EXTSRC4_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_STORE4_STATICCONTROL         */
+	imxdpuv1_write(imxdpu, IMXDPUV1_STORE4_STATICCONTROL,
+		IMXDPUV1_STORE4_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_EXTSRC5_STATICCONTROL        */
+	imxdpuv1_write(imxdpu, IMXDPUV1_EXTSRC5_STATICCONTROL,
+		IMXDPUV1_EXTSRC5_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_STORE5_STATICCONTROL         */
+	imxdpuv1_write(imxdpu, IMXDPUV1_STORE5_STATICCONTROL,
+		IMXDPUV1_STORE5_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_FETCHDECODE2_STATICCONTROL   */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE2_STATICCONTROL,
+		IMXDPUV1_FETCHDECODE2_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_FETCHDECODE3_STATICCONTROL   */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE3_STATICCONTROL,
+		IMXDPUV1_FETCHDECODE3_STATICCONTROL_RESET_VALUE);
+#endif
+	/* IMXDPUV1_FETCHWARP2_STATICCONTROL     */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_STATICCONTROL,
+		IMXDPUV1_FETCHWARP2_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_FETCHECO2_STATICCONTROL      */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO9_STATICCONTROL,
+		IMXDPUV1_FETCHECO9_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_FETCHDECODE0_STATICCONTROL   */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE0_STATICCONTROL,
+		IMXDPUV1_FETCHDECODE0_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_FETCHECO0_STATICCONTROL      */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO0_STATICCONTROL,
+		IMXDPUV1_FETCHECO0_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_FETCHDECODE1_STATICCONTROL   */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE1_STATICCONTROL,
+		IMXDPUV1_FETCHDECODE1_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_FETCHECO1_STATICCONTROL      */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO1_STATICCONTROL,
+		IMXDPUV1_FETCHECO1_STATICCONTROL_RESET_VALUE);
+
+	/* todo: IMXDPUV1_MATRIX5_STATICCONTROL        */
+	/* todo: IMXDPUV1_HSCALER5_STATICCONTROL       */
+	/* todo: IMXDPUV1_VSCALER5_STATICCONTROL       */
+	/* IMXDPUV1_LAYERBLEND0_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND0_STATICCONTROL,
+		IMXDPUV1_LAYERBLEND0_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_LAYERBLEND1_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND1_STATICCONTROL,
+		IMXDPUV1_LAYERBLEND1_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_LAYERBLEND2_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND2_STATICCONTROL,
+		IMXDPUV1_LAYERBLEND2_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_LAYERBLEND3_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND3_STATICCONTROL,
+		IMXDPUV1_LAYERBLEND3_STATICCONTROL_RESET_VALUE);
+#ifdef IMXDPUV1_VERSION_0
+	/* IMXDPUV1_LAYERBLEND4_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND4_STATICCONTROL,
+		IMXDPUV1_LAYERBLEND4_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_LAYERBLEND5_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND5_STATICCONTROL,
+		IMXDPUV1_LAYERBLEND5_STATICCONTROL_RESET_VALUE);
+
+	/* IMXDPUV1_LAYERBLEND6_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND6_STATICCONTROL,
+		IMXDPUV1_LAYERBLEND6_STATICCONTROL_RESET_VALUE);
+#endif
+	/* Dynamic config */
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE));
+
+#ifdef IMXDPUV1_VERSION_0
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHPERSP9_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE));
+#else
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE));
+#endif
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC,
+		IMXDPUV1_SET_FIELD
+		(IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) |
+		IMXDPUV1_SET_FIELD
+		(IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) |
+		IMXDPUV1_SET_FIELD
+		(IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC,
+		IMXDPUV1_SET_FIELD
+		(IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) |
+		IMXDPUV1_SET_FIELD
+		(IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE));
+#ifdef IMXDPUV1_VERSION_0
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE2_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE3_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE));
+#endif
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE));
+#ifdef IMXDPUV1_VERSION_0
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_GAMMACOR4_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE));
+#endif
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+#ifdef IMXDPUV1_VERSION_0
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HISTOGRAM4_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_GAMMACOR5_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE));
+#endif
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+#ifdef IMXDPUV1_VERSION_0
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HISTOGRAM5_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL,
+			IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+#endif
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL,
+			IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL,
+			IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL,
+			IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL,
+			IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL,
+			IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL,
+			IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL,
+			IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL,
+			IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+#ifdef IMXDPUV1_VERSION_0
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND4_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL,
+			IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL,
+			IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND5_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL,
+			IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL,
+			IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND6_DYNAMIC,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL,
+			IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL,
+			IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN,
+			IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC));
+#endif
+	/* Static configuration - reset values */
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE9_STATIC,
+		IMXDPUV1_PIXENGCFG_STORE9_STATIC_RESET_VALUE);
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_STATIC,
+		IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_RESET_VALUE);
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST4_STATIC,
+		IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_RESET_VALUE);
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_STATIC,
+		IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_RESET_VALUE);
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST5_STATIC,
+		IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_RESET_VALUE);
+#ifdef IMXDPUV1_VERSION_0
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_STATIC,
+		IMXDPUV1_PIXENGCFG_STORE4_STATIC_RESET_VALUE);
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE5_STATIC,
+		IMXDPUV1_PIXENGCFG_STORE5_STATIC_RESET_VALUE);
+#endif
+	/* Static configuration - initial settings */
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE9_STATIC,
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_POWERDOWN,
+			IMXDPUV1_FALSE) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE,
+			IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE__SINGLE) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET,
+			IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET__OPERATION) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_DIV,
+			IMXDPUV1_PIXENGCFG_DIVIDER_RESET));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_STATIC,
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_POWERDOWN,
+			IMXDPUV1_FALSE) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE,
+			IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE__AUTO) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET,
+			IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET__OPERATION) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_DIV,
+			IMXDPUV1_PIXENGCFG_DIVIDER_RESET));
+
+	/* todo: IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_OFFSET */
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_STATIC,
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_POWERDOWN,
+			IMXDPUV1_FALSE) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE,
+			IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE__AUTO) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET,
+			IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET__OPERATION) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_DIV,
+			IMXDPUV1_PIXENGCFG_DIVIDER_RESET));
+
+	/* todo: IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_OFFSET */
+#ifdef IMXDPUV1_VERSION_0
+	imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_STATIC,
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_POWERDOWN,
+			IMXDPUV1_FALSE) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SYNC_MODE,
+			IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SYNC_MODE__SINGLE) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SW_RESET,
+			IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SW_RESET__OPERATION) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_DIV,
+			IMXDPUV1_PIXENGCFG_DIVIDER_RESET));
+#endif
+	/* todo: IMXDPUV1_PIXENGCFG_STORE4_STATIC */
+	/* Static Control configuration */
+	/* IMXDPUV1_FETCHDECODE9_STATICCONTROL  */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE9_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE9_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_FETCHDECODE9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0));
+#ifdef IMXDPUV1_VERSION_0
+	/* IMXDPUV1_FETCHPERSP9_STATICCONTROL   */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHPERSP9_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHPERSP9_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_FETCHPERSP9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0));
+#else
+	/* IMXDPUV1_FETCHWARP9_STATICCONTROL   */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP9_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_FETCHWARP9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0));
+#endif
+	/* IMXDPUV1_FETCHECO9_STATICCONTROL     */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO9_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO9_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_FETCHECO9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0));
+
+	/* IMXDPUV1_ROP9_STATICCONTROL          */
+	imxdpuv1_write(imxdpu, IMXDPUV1_ROP9_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_ROP9_STATICCONTROL_SHDEN, 1));
+
+	/* IMXDPUV1_CLUT9_STATICCONTROL         */
+	imxdpuv1_write(imxdpu, IMXDPUV1_CLUT9_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_CLUT9_STATICCONTROL_SHDEN, 1));
+
+	imxdpuv1_write(imxdpu, IMXDPUV1_CLUT9_UNSHADOWEDCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN,
+			IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN__ENABLE)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN,
+			IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN__ENABLE)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN,
+			IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN__ENABLE));
+
+	/* IMXDPUV1_MATRIX9_STATICCONTROL       */
+	imxdpuv1_write(imxdpu, IMXDPUV1_MATRIX9_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_MATRIX9_STATICCONTROL_SHDEN, 1));
+
+	/* IMXDPUV1_HSCALER9_STATICCONTROL      */
+	imxdpuv1_write(imxdpu, IMXDPUV1_HSCALER9_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_HSCALER9_STATICCONTROL_SHDEN, 1));
+
+	/* IMXDPUV1_VSCALER9_STATICCONTROL      */
+	imxdpuv1_write(imxdpu, IMXDPUV1_VSCALER9_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_VSCALER9_STATICCONTROL_SHDEN, 1));
+
+	/* IMXDPUV1_FILTER9_STATICCONTROL       */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FILTER9_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FILTER9_STATICCONTROL_SHDEN, 1));
+
+	/* IMXDPUV1_BLITBLEND9_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_BLITBLEND9_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_BLITBLEND9_STATICCONTROL_SHDEN, 1));
+
+	/* IMXDPUV1_STORE9_STATICCONTROL        */
+	imxdpuv1_write(imxdpu, IMXDPUV1_STORE9_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_STORE9_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_STORE9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 1));
+
+	/* IMXDPUV1_CONSTFRAME0_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_CONSTFRAME0_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_CONSTFRAME0_STATICCONTROL_SHDEN, 1));
+
+	/* IMXDPUV1_EXTDST0_STATICCONTROL        */
+	imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST0_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_EXTDST0_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_EXTDST0_STATICCONTROL_PERFCOUNTMODE, 0) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE,
+			IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE__EXTERNAL));
+
+	/* todo: IMXDPUV1_CONSTFRAME4_STATICCONTROL    */
+	/* todo: IMXDPUV1_EXTDST4_STATICCONTROL        */
+
+	/* IMXDPUV1_CONSTFRAME1_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_CONSTFRAME1_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_CONSTFRAME1_STATICCONTROL_SHDEN, 1));
+
+	/* IMXDPUV1_EXTDST1_STATICCONTROL        */
+	imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST1_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_EXTDST1_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_EXTDST1_STATICCONTROL_PERFCOUNTMODE, 0) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE,
+			IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE__EXTERNAL));
+
+	/* todo: IMXDPUV1_CONSTFRAME5_STATICCONTROL    */
+	/* todo: IMXDPUV1_EXTDST5_STATICCONTROL        */
+#ifdef IMXDPUV1_VERSION_0
+	/* IMXDPUV1_EXTSRC4_STATICCONTROL        */
+	imxdpuv1_write(imxdpu, IMXDPUV1_EXTSRC4_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_STATICCONTROL_STARTSEL,
+			IMXDPUV1_EXTSRC4_STATICCONTROL_STARTSEL__LOCAL));
+
+	/* IMXDPUV1_STORE4_STATICCONTROL         */
+	imxdpuv1_write(imxdpu, IMXDPUV1_STORE4_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_STORE4_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_STORE4_STATICCONTROL_BASEADDRESSAUTOUPDATE, 1));
+
+	/* IMXDPUV1_EXTSRC5_STATICCONTROL        */
+	imxdpuv1_write(imxdpu, IMXDPUV1_EXTSRC5_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC5_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC5_STATICCONTROL_STARTSEL,
+			IMXDPUV1_EXTSRC5_STATICCONTROL_STARTSEL__LOCAL));
+
+	/* IMXDPUV1_STORE5_STATICCONTROL         */
+	imxdpuv1_write(imxdpu, IMXDPUV1_STORE5_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_STORE5_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_STORE5_STATICCONTROL_BASEADDRESSAUTOUPDATE, 1));
+
+	/* IMXDPUV1_FETCHDECODE2_STATICCONTROL   */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE2_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE2_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_FETCHDECODE2_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0));
+
+	/* IMXDPUV1_FETCHDECODE3_STATICCONTROL   */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE3_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE3_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_FETCHDECODE3_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0));
+#endif
+	/* IMXDPUV1_FETCHWARP2_STATICCONTROL     */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_FETCHWARP2_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDLDREQSTICKY, 0));
+
+	/* IMXDPUV1_FETCHECO2_STATICCONTROL      */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO9_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO9_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_FETCHECO9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0));
+
+	/* IMXDPUV1_FETCHDECODE0_STATICCONTROL   */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE0_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_FETCHDECODE0_STATICCONTROL_BASEADDRESSAUTOUPDATE,
+			0));
+
+	/* IMXDPUV1_FETCHECO0_STATICCONTROL      */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO0_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO0_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_FETCHECO0_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0));
+
+	/* IMXDPUV1_FETCHDECODE1_STATICCONTROL   */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE1_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE1_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_FETCHDECODE1_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0));
+
+	/* IMXDPUV1_FETCHECO1_STATICCONTROL      */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO1_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO1_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_FETCHECO1_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0));
+
+	/* IMXDPUV1_FETCHLAYER0_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_FETCHLAYER0_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDLDREQSTICKY, 0));
+#ifdef IMXDPUV1_VERSION_0
+	/* IMXDPUV1_FETCHLAYER1_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHLAYER1_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_FETCHLAYER1_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_FETCHLAYER1_STATICCONTROL_SHDLDREQSTICKY, 0));
+
+	/* IMXDPUV1_GAMMACOR4_STATICCONTROL      */
+	imxdpuv1_write(imxdpu, IMXDPUV1_GAMMACOR4_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_GAMMACOR4_STATICCONTROL_BLUEWRITEENABLE, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_GAMMACOR4_STATICCONTROL_GREENWRITEENABLE, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_GAMMACOR4_STATICCONTROL_REDWRITEENABLE, 1));
+#endif
+	/* todo: IMXDPUV1_MATRIX4_STATICCONTROL        */
+	/* todo: IMXDPUV1_HSCALER4_STATICCONTROL       */
+	/* todo: IMXDPUV1_VSCALER4_STATICCONTROL       */
+#ifdef IMXDPUV1_VERSION_0
+	/* IMXDPUV1_GAMMACOR5_STATICCONTROL      */
+	imxdpuv1_write(imxdpu, IMXDPUV1_GAMMACOR5_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_GAMMACOR5_STATICCONTROL_BLUEWRITEENABLE, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_GAMMACOR5_STATICCONTROL_GREENWRITEENABLE, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_GAMMACOR5_STATICCONTROL_REDWRITEENABLE, 1));
+#endif
+	/* todo: IMXDPUV1_MATRIX5_STATICCONTROL        */
+	/* todo: IMXDPUV1_HSCALER5_STATICCONTROL       */
+	/* todo: IMXDPUV1_VSCALER5_STATICCONTROL       */
+
+	/* IMXDPUV1_LAYERBLEND0_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND0_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL,
+			IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL__SECONDARY) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL,
+			IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL__BOTH));
+
+	/* IMXDPUV1_LAYERBLEND1_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND1_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL,
+			IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL__SECONDARY) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL,
+			IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL__BOTH));
+
+	/* IMXDPUV1_LAYERBLEND2_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND2_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL,
+			IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL__SECONDARY) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL,
+			IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL__BOTH));
+
+	/* IMXDPUV1_LAYERBLEND3_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND3_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL,
+			IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL__SECONDARY) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL,
+			IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL__BOTH));
+
+#ifdef IMXDPUV1_VERSION_0
+	/* IMXDPUV1_LAYERBLEND4_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND4_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDLDSEL,
+			IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDLDSEL__SECONDARY) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDTOKSEL,
+			IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDTOKSEL__BOTH));
+
+	/* IMXDPUV1_LAYERBLEND4_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND4_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDEN, 0) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDLDSEL,
+			IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDLDSEL__SECONDARY) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDTOKSEL,
+			IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDTOKSEL__BOTH));
+
+	/* IMXDPUV1_LAYERBLEND5_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND5_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDLDSEL,
+			IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDLDSEL__SECONDARY) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDTOKSEL,
+			IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDTOKSEL__BOTH));
+
+	/* IMXDPUV1_LAYERBLEND6_STATICCONTROL    */
+	imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND6_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDEN, 1) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDLDSEL,
+			IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDLDSEL__SECONDARY) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDTOKSEL,
+			IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDTOKSEL__BOTH));
+#endif
+	/* todo: IMXDPUV1_EXTSRC0_STATICCONTROL        */
+	/* todo: IMXDPUV1_EXTSRC1_STATICCONTROL        */
+	/* todo: IMXDPUV1_MATRIX0_STATICCONTROL        */
+	/* IMXDPUV1_GAMMACOR0_STATICCONTROL      */
+	imxdpuv1_write(imxdpu, IMXDPUV1_GAMMACOR0_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_GAMMACOR1_STATICCONTROL_BLUEWRITEENABLE, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_GAMMACOR1_STATICCONTROL_GREENWRITEENABLE, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_GAMMACOR1_STATICCONTROL_REDWRITEENABLE, 1));
+	/* todo: IMXDPUV1_SIG0_STATICCONTROL           */
+	/* todo: IMXDPUV1_MATRIX1_STATICCONTROL        */
+	/* IMXDPUV1_GAMMACOR1_STATICCONTROL      */
+	imxdpuv1_write(imxdpu, IMXDPUV1_GAMMACOR1_STATICCONTROL,
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_GAMMACOR1_STATICCONTROL_BLUEWRITEENABLE, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_GAMMACOR1_STATICCONTROL_GREENWRITEENABLE, 1) |
+		IMXDPUV1_SET_FIELD(
+			IMXDPUV1_GAMMACOR1_STATICCONTROL_REDWRITEENABLE, 1));
+	/* IMXDPUV1_SIG1_STATICCONTROL           */
+
+	imxdpuv1_init_irqs(imxdpuv1_id);
+
+	return ret;
+}
+
+int imxdpuv1_init_sync_panel(int8_t imxdpuv1_id,
+	int8_t disp,
+	uint32_t pixel_fmt, struct imxdpuv1_videomode mode)
+{
+	int ret = 0;
+	IMXDPUV1_TRACE("%s()\n", __func__);
+	return ret;
+}
+
+int imxdpuv1_uninit_sync_panel(int8_t imxdpuv1_id, int8_t disp)
+{
+	int ret = 0;
+	IMXDPUV1_TRACE("%s()\n", __func__);
+	return ret;
+}
+
+int imxdpuv1_reset_disp_panel(int8_t imxdpuv1_id, int8_t disp)
+{
+	int ret = 0;
+	IMXDPUV1_TRACE("%s()\n", __func__);
+	return ret;
+}
+
+/*!
+ * This function initializes the display
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ * @param       disp		id of the diplay output pipe
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_disp_init(int8_t imxdpuv1_id, int8_t disp)
+{
+	int ret = 0;
+	struct imxdpuv1_soc *imxdpu;
+	struct imxdpuv1_videomode *mode;
+	int reg = 0;
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+	mode = &imxdpu->video_mode[disp];
+	/*imxdpuv1_disp_dump_mode(&imxdpu->video_mode[disp]);*/
+
+	if (disp == 0) {
+#ifdef IMXDPUV1_TCON0_MAP_24BIT_0_23
+		/* Static  24-bit TCON bit mapping for FPGA */
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT7_4, 0x1d1c1b1a);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT3_0, 0x19181716);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT15_12, 0x13121110);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT11_8, 0x0f0e0d0c);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT23_20, 0x09080706);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT19_16, 0x05040302);
+#else
+		/*  tcon mapping
+		  *  RR RRRR RRRR GGGG GGGG GGBB BBBB BBBB
+		  *  98 7654 3210 9876 5432 1098 7654 3210
+		  *  bits
+		  *  00 0000 0000 1111 1111 1122 2222 2222
+		  *  98 7654 3210 8765 5432 1098 7654 3210
+		  */
+		/* 30-bit timing controller setup */
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT31_28, 0x00000908);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT27_24, 0x07060504);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT23_20, 0x03020100);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT19_16, 0x13121110);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT15_12, 0x0f0e0d0c);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT11_8,  0x0b0a1d1c);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT7_4,   0x1b1a1918);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT3_0,   0x17161514);
+
+#endif
+
+		/* set data enable polarity */
+		if (mode->flags & IMXDPUV1_MODE_FLAGS_HSYNC_POL)
+			reg = IMXDPUV1_SET_FIELD(
+				IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0,
+				IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0__HIGH);
+		else
+			reg = IMXDPUV1_SET_FIELD(
+				IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0,
+				IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0__LOW);
+
+		if (mode->flags & IMXDPUV1_MODE_FLAGS_VSYNC_POL)
+			reg |= IMXDPUV1_SET_FIELD(
+				IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0,
+				IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0__HIGH);
+		else
+			reg |= IMXDPUV1_SET_FIELD(
+				IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0,
+				IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0__LOW);
+
+		if (mode->flags & IMXDPUV1_MODE_FLAGS_DE_POL)
+			reg |= IMXDPUV1_SET_FIELD(
+				IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0,
+				IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0__HIGH);
+		else
+			reg |= IMXDPUV1_SET_FIELD(
+				IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0,
+				IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0__LOW);
+
+		imxdpuv1_write(imxdpu, IMXDPUV1_DISENGCFG_POLARITYCTRL0, reg);
+		/* printf("polreg=0x%x\n", imxdpuv1_read(imxdpu, IMXDPUV1_DISENGCFG_POLARITYCTRL0)); */
+
+	} else if (disp == 1) {
+#ifdef IMXDPUV1_TCON1_MAP_24BIT_0_23
+		/* Static TCON bit mapping */
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT7_4, 0x1d1c1b1a);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT3_0, 0x19181716);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT15_12, 0x13121110);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT11_8, 0x0f0e0d0c);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT23_20, 0x09080706);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT19_16, 0x05040302);
+#else
+		/*  tcon mapping
+		  *  RR RRRR RRRR GGGG GGGG GGBB BBBB BBBB
+		  *  98 7654 3210 9876 5432 1098 7654 3210
+		  *  bits
+		  *  00 0000 0000 1111 1111 1122 2222 2222
+		  *  98 7654 3210 8765 5432 1098 7654 3210
+		  */
+		/* 30-bit timing controller setup */
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT31_28, 0x00000908);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT27_24, 0x07060504);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT23_20, 0x03020100);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT19_16, 0x13121110);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT15_12, 0x0f0e0d0c);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT11_8,  0x0b0a1d1c);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT7_4,   0x1b1a1918);
+		imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT3_0,   0x17161514);
+#endif
+		/* set data enable polarity */
+		if (mode->flags & IMXDPUV1_MODE_FLAGS_HSYNC_POL)
+			reg = IMXDPUV1_SET_FIELD(
+				IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1,
+				IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1__HIGH);
+		else
+			reg = IMXDPUV1_SET_FIELD(
+				IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1,
+				IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1__LOW);
+
+		if (mode->flags & IMXDPUV1_MODE_FLAGS_VSYNC_POL)
+			reg |= IMXDPUV1_SET_FIELD(
+				IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1,
+				IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1__HIGH);
+		else
+			reg |= IMXDPUV1_SET_FIELD(
+				IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1,
+				IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1__LOW);
+
+		if (mode->flags & IMXDPUV1_MODE_FLAGS_DE_POL)
+			reg |= IMXDPUV1_SET_FIELD(
+				IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1,
+				IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1__HIGH);
+		else
+			reg |= IMXDPUV1_SET_FIELD(
+				IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1,
+				IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1__LOW);
+
+		imxdpuv1_write(imxdpu, IMXDPUV1_DISENGCFG_POLARITYCTRL1, reg);
+		/* printf("polreg=0x%x\n", imxdpuv1_read(imxdpu, IMXDPUV1_DISENGCFG_POLARITYCTRL1)); */
+
+	} else {
+		return -EINVAL;
+	}
+	/* todo: initialize prefetch */
+
+	return ret;
+}
+
+int imxdpuv1_disp_setup_tcon_bypass_mode(
+	int8_t imxdpuv1_id,
+	int8_t disp,
+	const struct imxdpuv1_videomode *mode)
+{
+	struct imxdpuv1_soc *imxdpu;
+	uint32_t b_off;     /* block offset for tcon generator */
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	if (disp == 0) {
+		b_off = IMXDPUV1_TCON0_LOCKUNLOCK;
+	} else if (disp == 1) {
+		b_off = IMXDPUV1_TCON1_LOCKUNLOCK;
+	} else {
+		return -EINVAL;
+	}
+
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_TCON_CTRL_OFFSET,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE,
+			IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE__BALANCED) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE,
+			IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_4PAIRS) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_TCON_CTRL_SPLITPOSITION,
+			0x140));
+	/* setup hsync */
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG0POSON_OFFSET,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG0POSON_SPGPSON_X0, mode->hlen + mode->hfp));
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG0MASKON_OFFSET, 0xffff);
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG0POSOFF_OFFSET,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_X0, mode->hlen + mode->hfp + mode->hsync));
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG0MASKOFF_OFFSET, 0xffff);
+
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX0SIGS_OFFSET,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S0, 2));
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX0FCTTABLE_OFFSET, 1);
+
+	/* Setup Vsync */
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG1POSON_OFFSET,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG1POSON_SPGPSON_X1, mode->hlen + mode->hfp + mode->hsync) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG1POSON_SPGPSON_Y1, mode->vlen + mode->vfp - 1));
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG1MASKON_OFFSET, 0);
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG1POSOFF_OFFSET,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_X1, mode->hlen + mode->hfp + mode->hsync)|
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_Y1, mode->vlen + mode->vfp + mode->vsync - 1));
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG1MASKOFF_OFFSET, 0);
+
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX1SIGS_OFFSET,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S0, 3));
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX1FCTTABLE_OFFSET, 1);
+
+	/* data enable horizontal */
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG2POSON_OFFSET, 0);
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG2MASKON_OFFSET, 0xffff);
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG2POSOFF_OFFSET,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_X2, mode->hlen));
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG2MASKOFF_OFFSET, 0xffff);
+	/* data enable vertical  */
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG3POSON_OFFSET, 0);
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG3MASKON_OFFSET, 0x7fff0000);
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG3POSOFF_OFFSET,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_X3, 0) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_Y3, mode->vlen));
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG3MASKOFF_OFFSET, 0x7fff0000);
+
+	/* use both SPG2 and SPG3 to generate data enable */
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX2SIGS_OFFSET,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S0, 4)|
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S1, 5));
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX2FCTTABLE_OFFSET, 8);
+
+	/* shadow load trigger (aka kachunk) */
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG4POSON_OFFSET,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG4POSON_SPGPSON_X4, 10) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG4POSON_SPGPSON_Y4, mode->vlen));
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG4MASKON_OFFSET, 0);
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG4POSOFF_OFFSET,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_X4, 26) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_Y4, mode->vlen));
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG4MASKOFF_OFFSET, 0);
+
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX3SIGS_OFFSET,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S0, 6));
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX3FCTTABLE_OFFSET, 2);
+
+	return 0;
+}
+
+/*!
+ * This function sets up the frame generator
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ * @param       disp		id of the diplay output pipe
+ * @param       enable  	state to set frame generator to
+ * @param	mode    	to set the display to
+ * @param       cc_red		constant color red
+ * @param       cc_green	constant color green
+ * @param       cc_blue		constant color blue
+ * @param       cc_alpha	constant color alpha
+*
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_disp_setup_frame_gen(
+	int8_t imxdpuv1_id,
+	int8_t disp,
+	const struct imxdpuv1_videomode *mode,
+	uint16_t cc_red,    /* 10 bits */
+	uint16_t cc_green,  /* 10 bits */
+	uint16_t cc_blue,   /* 10 bits */
+	uint8_t cc_alpha,
+	bool test_mode_enable)
+{           /* 1 bits, yes 1 bit */
+	int ret = 0;
+	uint32_t b_off;     /* block offset for frame generator */
+	uint32_t reg;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	if (disp == 0) {
+		b_off = IMXDPUV1_FRAMEGEN0_LOCKUNLOCK;
+	} else if (disp == 1) {
+		b_off = IMXDPUV1_FRAMEGEN1_LOCKUNLOCK;
+	} else {
+		return -EINVAL;
+	}
+
+	/* todo:
+	   add video mode sanity check here
+	   check if LRSYNC is required
+	 */
+
+	if (mode->flags & IMXDPUV1_MODE_FLAGS_LRSYNC) {
+		/* todo: here we need to use two outputs to make one */
+		if (disp == 0) {
+			reg = IMXDPUV1_SET_FIELD(
+				IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE,
+				IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__MASTER);
+		} else {
+			reg = IMXDPUV1_SET_FIELD(
+				IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE,
+				IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__SLAVE_CYC);
+		}
+	} else {
+		reg = IMXDPUV1_SET_FIELD(
+			IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE,
+			IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__OFF);
+	}
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGSTCTRL_OFFSET, reg);
+
+	reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG1_HACT, mode->hlen) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG1_HTOTAL,
+		(mode->hlen + mode->hfp + mode->hbp + mode->hsync - 1));
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_HTCFG1_OFFSET, reg);
+
+	reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG2_HSYNC,
+		mode->hsync - 1) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG2_HSBP,
+		mode->hbp + mode->hsync - 1) |
+		/* shadow enable */
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG2_HSEN, 1);
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_HTCFG2_OFFSET, reg);
+
+	reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG1_VACT, mode->vlen) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG1_VTOTAL,
+		(mode->vlen + mode->vfp + mode->vbp + mode->vsync -
+			1));
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_VTCFG1_OFFSET, reg);
+
+	reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG2_VSYNC,
+		mode->vsync - 1) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG2_VSBP,
+		mode->vbp + mode->vsync - 1) |
+		/* shadow enable */
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG2_VSEN, 1);
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_VTCFG2_OFFSET, reg);
+
+	/* Interupt at position (0, vlen - 3) for end of frame interrupt */
+	reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0COL, 1) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0HSEN, 0) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0ROW,
+		mode->vlen - 3) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0EN, 1);
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_INT0CONFIG_OFFSET, reg);
+
+	/* Interupt at position 1, mode->vlen  */
+	reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1COL, 1) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1HSEN, 0) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1ROW,
+		mode->vlen) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1EN, 1);
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_INT1CONFIG_OFFSET, reg);
+
+	/* Interupt at position 2, mode->vlen */
+	reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2COL, 2) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2HSEN, 0) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2ROW,
+		mode->vlen) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2EN, 1);
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_INT2CONFIG_OFFSET, reg);
+
+	/* Interupt at position 3, mode->vlen */
+	reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3COL, 3) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3HSEN, 0) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3ROW,
+		mode->vlen) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3EN, 1);
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_INT3CONFIG_OFFSET, reg);
+
+	/* todo: these need to be checked
+	   _SKICKCOL for verification: =(FW - 40) , for ref driver = 1 ?
+	   _SKICKROW for verif.  =(FH - 1), ref driver = vlen-2
+	 */
+	reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKCOL,
+		mode->hlen - 40) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKINT1EN, 0) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKROW,
+		mode->vlen + 1) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKEN, 1);
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_SKICKCONFIG_OFFSET, reg);
+
+	reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_PACFG_PSTARTX, 1) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_PACFG_PSTARTY, 1);
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_PACFG_OFFSET, reg);
+
+	reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SACFG_SSTARTX, 1) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SACFG_SSTARTY, 1);
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_SACFG_OFFSET, reg);
+
+	if (IMXDPUV1_ENABLE == test_mode_enable) {
+		reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM,
+			IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__TEST);
+	} else {
+		reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM,
+			IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__SEC) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRL_ENPRIMALPHA, 0) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRL_ENSECALPHA, 0);
+	}
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGINCTRL_OFFSET, reg);
+
+	reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC,
+		IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__CONSTCOL) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENPRIMALPHAPANIC, 0) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENSECALPHAPANIC, 0);
+	imxdpuv1_write(imxdpu, b_off +
+		IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_OFFSET, reg);
+
+	/* Set the constant color - ARGB 1-10-10-10 */
+	reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGCCR_CCRED, cc_red) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGCCR_CCBLUE, cc_blue) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGCCR_CCGREEN, cc_green) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGCCR_CCALPHA, cc_alpha);
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGCCR_OFFSET, reg);
+
+
+	imxdpuv1_disp_setup_tcon_bypass_mode(imxdpuv1_id, disp, mode);
+
+	/* save the mode */
+	imxdpu->video_mode[disp] = *mode;
+
+	/* imxdpuv1_disp_dump_mode(&imxdpu->video_mode[disp]); */
+
+	return ret;
+}
+
+/*!
+ * This function updates the frame generator status
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ * @param       disp		id of the diplay output pipe
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_disp_update_fgen_status(int8_t imxdpuv1_id, int8_t disp)
+{
+	int ret = 0;
+	uint32_t b_off;     /* block offset for frame generator */
+	uint32_t reg;
+	uint32_t temp;
+	struct imxdpuv1_soc *imxdpu;
+	static uint32_t fcount[IMXDPUV1_NUM_DI_MAX] = { 0, 0 };
+
+	IMXDPUV1_TRACE_IRQ("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	if (disp == 0) {
+		b_off = IMXDPUV1_FRAMEGEN0_LOCKUNLOCK;
+	} else if (disp == 1) {
+		b_off = IMXDPUV1_FRAMEGEN1_LOCKUNLOCK;
+	} else {
+		return -EINVAL;
+	}
+
+	/* todo:
+	   add video mode sanity check here
+	   check if LRSYNC is required
+	 */
+
+	reg = imxdpuv1_read_irq(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_OFFSET);
+	IMXDPUV1_TRACE_IRQ("DISP %d: findex %d, lindex %d\n", disp,
+		IMXDPUV1_GET_FIELD
+		(IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_FRAMEINDEX, reg),
+		IMXDPUV1_GET_FIELD
+		(IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_LINEINDEX, reg));
+
+	temp = IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_FRAMEINDEX, reg);
+	if (temp != fcount[disp]) {
+		fcount[disp] = temp;
+		/* Just increment we assume this is called one per frame */
+		imxdpu->fgen_stats[disp].frame_count++;
+	}
+
+	reg = imxdpuv1_read_irq(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGCHSTAT_OFFSET);
+	temp = IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_SECSYNCSTAT, reg);
+
+	/* Sync status bits should be set */
+	if ((temp != imxdpu->fgen_stats[disp].sec_sync_state) && (temp == 1)) {
+		imxdpu->fgen_stats[disp].sec_sync_count++;
+		IMXDPUV1_TRACE_IRQ("DISP %d: sec in sync\n", disp);
+	}
+	if ((temp != imxdpu->fgen_stats[disp].sec_sync_state) && (temp == 0)) {
+		IMXDPUV1_TRACE_IRQ("DISP %d: sec out of sync\n", disp);
+	}
+	imxdpu->fgen_stats[disp].sec_sync_state = temp;
+	temp = IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_PRIMSYNCSTAT, reg);
+
+	/* Sync status bits should be set */
+	if ((temp != imxdpu->fgen_stats[disp].prim_sync_state) &&
+		(temp == 1)) {
+		imxdpu->fgen_stats[disp].prim_sync_count++;
+		IMXDPUV1_TRACE_IRQ("DISP %d: prim in sync\n", disp);
+	}
+	if ((temp != imxdpu->fgen_stats[disp].prim_sync_state) &&
+		(temp == 0)) {
+		IMXDPUV1_TRACE_IRQ("DISP %d: prim out of sync\n", disp);
+	}
+	imxdpu->fgen_stats[disp].prim_sync_state = temp;
+
+	/* primary fifo bit should be clear if in use (panic stream) */
+	if (IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_PFIFOEMPTY, reg)) {
+		IMXDPUV1_TRACE_IRQ("DISP %d: primary fifo empty\n", disp);
+		imxdpuv1_write_irq(imxdpu,
+			b_off + IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_OFFSET,
+			IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRPRIMSTAT_MASK);
+		imxdpu->fgen_stats[disp].prim_fifo_empty_count++;
+	}
+	/* secondary fifo and skew error bits should be clear
+	   if in use (content stream) */
+	if (IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_SFIFOEMPTY, reg) ||
+		IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_SKEWRANGEERR, reg)) {
+		if (IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_SFIFOEMPTY, reg)) {
+			IMXDPUV1_TRACE_IRQ("DISP %d: secondary fifo empty\n",
+				disp);
+			imxdpu->fgen_stats[disp].sec_fifo_empty_count++;
+		}
+		if (IMXDPUV1_GET_FIELD
+			(IMXDPUV1_FRAMEGEN0_FGCHSTAT_SKEWRANGEERR, reg)) {
+			IMXDPUV1_TRACE_IRQ("DISP %d: secondary skew error\n",
+				disp);
+			imxdpu->fgen_stats[disp].skew_error_count++;
+		}
+		imxdpuv1_write_irq(imxdpu,
+			b_off + IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_OFFSET,
+			IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRSECSTAT_MASK);
+	}
+	return ret;
+}
+/*!
+ * This function sets up the frame capture
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ * @param       src_id		id of the capture source block
+ * @param       dest_id		id of the capture dest block
+ * @param       sync_count	number of valid required to aquire sync
+ * @param	cap_mode	mode of the video input
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_cap_setup_frame(
+	int8_t imxdpuv1_id,
+	int8_t src_id,
+	int8_t dest_id,
+	int8_t sync_count,
+	const struct imxdpuv1_videomode *cap_mode)
+{
+#ifndef IMXDPUV1_VERSION_0
+	return -EINVAL;
+#else
+	int ret = 0;
+	uint32_t b_off_frame;   /* block offset for capture source */
+	uint32_t b_off_extsrc;  /* block offset for extsrc */
+
+	int8_t cap_id;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	if (src_id == IMXDPUV1_ID_FRAMECAP4) {
+		cap_id = 0;
+		b_off_frame = IMXDPUV1_FRAMECAP4_LOCKUNLOCK;
+		b_off_extsrc = IMXDPUV1_EXTSRC4_LOCKUNLOCK;
+	} else if (src_id == IMXDPUV1_ID_FRAMECAP5) {
+		cap_id = 1;
+		b_off_frame = IMXDPUV1_FRAMECAP5_LOCKUNLOCK;
+		b_off_extsrc = IMXDPUV1_EXTSRC5_LOCKUNLOCK;
+	} else if (src_id == IMXDPUV1_ID_FRAMEDUMP0) {
+		cap_id = 0;
+		b_off_frame = IMXDPUV1_FRAMEDUMP0_CONTROL;
+		b_off_extsrc = IMXDPUV1_EXTSRC0_LOCKUNLOCK;
+	} else if (src_id == IMXDPUV1_ID_FRAMEDUMP1) {
+		cap_id = 1;
+		b_off_frame = IMXDPUV1_FRAMEDUMP1_CONTROL;
+		b_off_extsrc = IMXDPUV1_EXTSRC4_LOCKUNLOCK;
+	} else {
+		return -EINVAL;
+	}
+
+	if (dest_id == IMXDPUV1_ID_STORE4) {
+		imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC,
+			IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC_STORE4_SRC_SEL__EXTSRC4);
+	} else if (dest_id == IMXDPUV1_ID_STORE5) {
+		imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC,
+			IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC_STORE5_SRC_SEL__EXTSRC5);
+	} else if (dest_id == IMXDPUV1_ID_EXTDST0) {
+		imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC,
+			IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__EXTSRC4);
+	} else if (dest_id == IMXDPUV1_ID_EXTDST1) {
+		imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC,
+			IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__EXTSRC5);
+	} else {
+		return -EINVAL;
+	}
+
+	imxdpuv1_write(imxdpu,
+		b_off_extsrc +  IMXDPUV1_EXTSRC4_STATICCONTROL_OFFSET,
+		 IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_STATICCONTROL_STARTSEL,
+			 IMXDPUV1_EXTSRC4_STATICCONTROL_STARTSEL__LOCAL) |
+		 IMXDPUV1_EXTSRC4_STATICCONTROL_SHDEN_MASK);
+	imxdpuv1_write(imxdpu,
+		b_off_extsrc + IMXDPUV1_EXTSRC4_CONSTANTCOLOR_OFFSET, 0);
+
+	if (cap_mode->format == IMXDPUV1_PIX_FMT_BGR24) {
+		 imxdpuv1_write(imxdpu,
+			 b_off_extsrc + IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_OFFSET,
+			 IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSRED, 0x8) |
+			 IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSGREEN, 0x8) |
+			 IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSBLUE, 0x8));
+		 imxdpuv1_write(imxdpu,
+			  b_off_extsrc + IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_OFFSET,
+			 IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTRED, 0x10) |
+			 IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTGREEN, 0x08) |
+			 IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTBLUE, 0x00));
+
+		 /* fixme: handle all cases for control */
+		 imxdpuv1_write(imxdpu,
+			b_off_extsrc + IMXDPUV1_EXTSRC4_CONTROL_OFFSET,
+			IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CONTROL_YUVCONVERSIONMODE,
+			IMXDPUV1_EXTSRC4_CONTROL_YUVCONVERSIONMODE__ITU601) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CONTROL_RASTERMODE,
+			IMXDPUV1_EXTSRC4_CONTROL_RASTERMODE__YUV422) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CONTROL_YUV422UPSAMPLINGMODE,
+			IMXDPUV1_EXTSRC4_CONTROL_YUV422UPSAMPLINGMODE__REPLICATE) |
+			IMXDPUV1_EXTSRC4_CONTROL_CLIPWINDOWENABLE_MASK);
+
+	} else if (cap_mode->format == IMXDPUV1_PIX_FMT_YUYV) {
+
+		 imxdpuv1_write(imxdpu,
+			b_off_extsrc + IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_OFFSET,
+
+			IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSRED, 0x8) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSGREEN, 0x8) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSBLUE, 0x8));
+		 imxdpuv1_write(imxdpu,
+			b_off_extsrc + IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_OFFSET,
+			IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTRED, 0x8) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTGREEN, 0x0) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTBLUE, 0x0));
+
+		 /* fixme: handle all cases for control */
+		 imxdpuv1_write(imxdpu,
+			b_off_extsrc + IMXDPUV1_EXTSRC4_CONTROL_OFFSET,
+			IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CONTROL_RASTERMODE,
+			IMXDPUV1_EXTSRC4_CONTROL_RASTERMODE__YUV422) |
+			IMXDPUV1_EXTSRC4_CONTROL_CLIPWINDOWENABLE_MASK);
+
+	} else {
+		IMXDPUV1_PRINT("%s(): invalid capture interface format\n", __func__);
+		return -EINVAL;
+	}
+
+
+	if ((src_id == IMXDPUV1_ID_FRAMECAP4) || (src_id == IMXDPUV1_ID_FRAMECAP5)) {
+		/* setup cature */
+		uint8_t capture_interface_mode;
+		/* Fixme:  change these mode bits to an enumeration */
+		if ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_32BIT) != 0) {
+			capture_interface_mode = IMXDPUV1_CAPENGCFG_CAPTUREINPUT1_CAPTUREMODE1__ENHSVS_32BIT;
+		} else if ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_BT656_10BIT) != 0) {
+			capture_interface_mode = IMXDPUV1_CAPENGCFG_CAPTUREINPUT1_CAPTUREMODE1__ITU656_10BIT;
+		} else if ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_BT656_8BIT) != 0) {
+			capture_interface_mode = IMXDPUV1_CAPENGCFG_CAPTUREINPUT1_CAPTUREMODE1__ITU656_8BIT;
+		} else {
+			return -EINVAL;
+		}
+
+		if (cap_id == 0) {
+			imxdpuv1_write(imxdpu, IMXDPUV1_CAPENGCFG_CAPTUREINPUT0,
+				 IMXDPUV1_SET_FIELD(IMXDPUV1_CAPENGCFG_CAPTUREINPUT0_CAPTUREMODE0,
+					 capture_interface_mode));
+		} else {
+			imxdpuv1_write(imxdpu, IMXDPUV1_CAPENGCFG_CAPTUREINPUT1,
+				 IMXDPUV1_SET_FIELD(IMXDPUV1_CAPENGCFG_CAPTUREINPUT1_CAPTUREMODE1,
+					 capture_interface_mode));
+		}
+
+		imxdpuv1_write(imxdpu, b_off_frame + IMXDPUV1_FRAMECAP4_FDR_OFFSET,
+		       IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_FDR_HEIGHT, cap_mode->vlen - 1) |
+		       IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_FDR_WIDTH, cap_mode->hlen - 1));
+
+		imxdpuv1_write(imxdpu,
+			b_off_frame + IMXDPUV1_FRAMECAP4_FDR1_OFFSET,
+			IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_FDR_HEIGHT, cap_mode->vlen1 - 1));
+
+		imxdpuv1_write(imxdpu,
+			b_off_frame + IMXDPUV1_FRAMECAP4_SCR_OFFSET, sync_count);
+
+
+		imxdpuv1_write(imxdpu,
+			b_off_frame + IMXDPUV1_FRAMECAP4_KCR_OFFSET, 0);
+		if ((cap_mode->clip_height != 0) && (cap_mode->clip_width != 0)) {
+			imxdpuv1_write(imxdpu, b_off_extsrc  + IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_OFFSET,
+				IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_CLIPWINDOWHEIGHT, cap_mode->clip_height - 1) |
+				IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_CLIPWINDOWWIDTH, cap_mode->clip_width - 1));
+
+			imxdpuv1_write(imxdpu, b_off_extsrc  + IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_OFFSET,
+				IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_CLIPWINDOWXOFFSET, cap_mode->clip_left) |
+				IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_CLIPWINDOWYOFFSET, cap_mode->clip_top));
+		}
+
+		imxdpuv1_write(imxdpu,
+			b_off_frame +  IMXDPUV1_FRAMECAP4_SPR_OFFSET,
+
+			/* low is active low, high is active high */
+			IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_SPR_POLHS,
+				((cap_mode->flags & IMXDPUV1_MODE_FLAGS_HSYNC_POL) != 0)) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_SPR_POLVS,
+				((cap_mode->flags & IMXDPUV1_MODE_FLAGS_VSYNC_POL) != 0)) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_SPR_POLEN,
+				((cap_mode->flags & IMXDPUV1_MODE_FLAGS_DE_POL) == 0))
+		);
+
+
+		/* fixme: may need to move this mapping */
+		if (src_id == IMXDPUV1_ID_FRAMECAP4) {
+			imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC,
+				IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC_STORE4_SRC_SEL__EXTSRC4);
+		} else if (src_id == IMXDPUV1_ID_FRAMECAP5) {
+			imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC,
+				IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC_STORE5_SRC_SEL__EXTSRC5);
+		}
+	}
+
+	if ((src_id == IMXDPUV1_ID_FRAMEDUMP0) || (src_id == IMXDPUV1_ID_FRAMEDUMP1)) {
+		/* todo */
+	}
+
+	/* save the mode */
+	imxdpu->capture_mode[cap_id] = *cap_mode;
+	/* imxdpuv1_disp_dump_mode(cap_mode); */
+	return ret;
+#endif
+}
+
+/*!
+ * This function sets up the frame capture
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ * @param       cap		id of the capture inpute
+ * @param       sync_count	number of valid required to aquire sync
+ * @param	cap_mode	mode of the video input
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_cap_setup_crop(
+	int8_t imxdpuv1_id,
+	int8_t src_id,
+	int16_t  clip_top,
+	int16_t  clip_left,
+	uint16_t clip_width,
+	uint16_t clip_height)
+{
+#ifndef IMXDPUV1_VERSION_0
+	return -EINVAL;
+#else
+	int ret = 0;
+	uint32_t b_off_extsrc;  /* block offset for extsrc */
+#if 0
+	uint32_t b_off_dest;    /* block offset for destination */
+#endif
+	int8_t cap_id;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	if (src_id == IMXDPUV1_ID_FRAMECAP4) {
+		cap_id = 0;
+		b_off_extsrc = IMXDPUV1_EXTSRC4_LOCKUNLOCK;
+	} else if (src_id == IMXDPUV1_ID_FRAMECAP5) {
+		cap_id = 1;
+		b_off_extsrc = IMXDPUV1_EXTSRC5_LOCKUNLOCK;
+	} else if (src_id == IMXDPUV1_ID_FRAMEDUMP0) {
+		cap_id = 0;
+		b_off_extsrc = IMXDPUV1_EXTSRC0_LOCKUNLOCK;
+	} else if (src_id == IMXDPUV1_ID_FRAMEDUMP1) {
+		cap_id = 1;
+		b_off_extsrc = IMXDPUV1_EXTSRC4_LOCKUNLOCK;
+	} else {
+		return -EINVAL;
+	}
+
+	if ((src_id == IMXDPUV1_ID_FRAMECAP4) || (src_id == IMXDPUV1_ID_FRAMECAP5)) {
+		if ((clip_height != 0) && (clip_width != 0)) {
+			imxdpuv1_write(imxdpu, b_off_extsrc  + IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_OFFSET,
+				IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_CLIPWINDOWHEIGHT, clip_height - 1) |
+				IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_CLIPWINDOWWIDTH, clip_width - 1));
+
+			imxdpuv1_write(imxdpu, b_off_extsrc  + IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_OFFSET,
+				IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_CLIPWINDOWXOFFSET, clip_left) |
+				IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_CLIPWINDOWYOFFSET, clip_top));
+			/* save the clip data */
+			imxdpu->capture_mode[cap_id].clip_height = clip_height;
+			imxdpu->capture_mode[cap_id].clip_width  = clip_width;
+			imxdpu->capture_mode[cap_id].clip_top    = clip_top;
+			imxdpu->capture_mode[cap_id].clip_left   = clip_left;
+		}
+	}
+
+	if ((src_id == IMXDPUV1_ID_FRAMEDUMP0) || (src_id == IMXDPUV1_ID_FRAMEDUMP1)) {
+		/* todo */
+	}
+	/* imxdpuv1_disp_dump_mode(&imxdpu->video_mode[cap_id]); */
+	return ret;
+#endif
+}
+/*!
+ * This function enables the frame capture
+ *
+ * @param	imxdpuv1_id	id of the display unit
+ * @param       cap		id of the capture output pipe
+ * @param 	enable 		state to set frame generator to
+ *
+ * @return 	This function returns 0 on success or negative error code on
+ *              fail.
+ */
+int imxdpuv1_cap_enable(int8_t imxdpuv1_id, int8_t cap, bool enable)
+{
+#ifndef IMXDPUV1_VERSION_0
+	return -EINVAL;
+#else
+	int ret = 0;
+	uint32_t b_off;
+	uint32_t reg;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	if (cap == 0) {
+		b_off = IMXDPUV1_FRAMECAP4_LOCKUNLOCK;
+	} else {
+		return -EINVAL;
+	}
+
+	if (enable) {
+		/* imxdpuv1_dump_pixencfg_status(imxdpuv1_id); */
+		printf("%s(): %s:%d stubbed feature\n", __func__, __FILE__, __LINE__);
+		/* imxdpuv1_dump_pixencfg_status(imxdpuv1_id); */
+	}
+	reg = enable ? IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_CTR_CEN, 1) :
+		       IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_CTR_CEN, 0);
+
+
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMECAP4_CTR_OFFSET, reg);
+
+	return ret;
+#endif
+}
+
+/*!
+ * This function triggers a shadow load
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ * @param       dest_id		id of the capture dest block
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_cap_request_shadow_load(int8_t imxdpuv1_id, int8_t dest_id, uint32_t mask)
+{
+#ifndef IMXDPUV1_VERSION_0
+	return -EINVAL;
+#else
+	int ret = 0;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	switch (dest_id) {
+	case IMXDPUV1_ID_STORE4:
+		imxdpuv1_write(imxdpu,
+			IMXDPUV1_PIXENGCFG_STORE4_REQUEST,
+			mask);
+		imxdpuv1_write(imxdpu,
+			IMXDPUV1_PIXENGCFG_STORE4_TRIGGER,
+			IMXDPUV1_PIXENGCFG_STORE4_TRIGGER_STORE4_SYNC_TRIGGER_MASK);
+		break;
+	case IMXDPUV1_ID_STORE5:
+		imxdpuv1_write(imxdpu,
+			IMXDPUV1_PIXENGCFG_STORE5_REQUEST,
+			mask);
+		imxdpuv1_write(imxdpu,
+			IMXDPUV1_PIXENGCFG_STORE5_TRIGGER,
+			IMXDPUV1_PIXENGCFG_STORE5_TRIGGER_STORE5_SYNC_TRIGGER_MASK);
+		break;
+
+	default:
+		return -EINVAL;
+
+	}
+	return ret;
+#endif
+}
+
+/*!
+ * This function requests a shadow loads
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ * @param       disp		id of the diplay output pipe
+ * @param       shadow_load_idx  index of the shadow load requested
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_disp_request_shadow_load(int8_t imxdpuv1_id,
+	int8_t disp,
+	imxdpuv1_shadow_load_index_t shadow_load_idx)
+{
+	int ret = 0;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s(): imxdpuv1_id %d, disp %d, shadow_load_idx %d\n",
+		__func__, imxdpuv1_id, disp, shadow_load_idx);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+	/* trigger configuration of the pipeline */
+
+	if ((disp == 0) || (disp == 1)) {
+		/* last request was complete or no request in progress,
+		   then start a new request */
+		if (imxdpu->shadow_load_state[disp][shadow_load_idx].word == 0) {
+			imxdpu->shadow_load_state[disp][shadow_load_idx].state.
+				request = IMXDPUV1_TRUE;
+		} else {    /* check ifg the request is busy */
+			IMXDPUV1_TRACE("%s(): shadow load not complete.", __func__);
+			return -EBUSY;
+		}
+	} else {
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+/*!
+ * This function force a shadow loads
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ * @param       disp		id of the diplay output pipe
+ * @param       shadow_load_idx  index of the shadow load requested
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_disp_force_shadow_load(int8_t imxdpuv1_id,
+	int8_t disp,
+	uint64_t mask)
+{
+	int ret = 0;
+	uint32_t addr_extdst;   /* address for extdst */
+	uint32_t addr_fgen; /* address for frame generator */
+	uint32_t extdst = 0;
+	uint32_t fgen = 0;
+	uint32_t sub = 0;
+	struct imxdpuv1_soc *imxdpu;
+	int i;
+	uint64_t temp_mask;
+
+	IMXDPUV1_TRACE_IRQ("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	if (!((disp == 0) || (disp == 1))) {
+		return -EINVAL;
+	}
+
+	if (mask == 0) {
+		return -EINVAL;
+	}
+
+	if (disp == 0) {
+		addr_fgen = IMXDPUV1_FRAMEGEN0_FGSLR;
+		addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST;
+	} else if (disp == 1) {
+		addr_fgen = IMXDPUV1_FRAMEGEN1_FGSLR;
+		addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST;
+	} else {
+		return -EINVAL;
+	}
+
+	for (i = 0; i <  IMXDPUV1_SHDLD_IDX_MAX; i++) {
+		temp_mask = 1ULL << i;
+		if ((mask & temp_mask) == 0)
+			continue;
+
+		extdst |= trigger_list[i].extdst;
+		sub |= trigger_list[i].sub;
+
+		if ((i == IMXDPUV1_SHDLD_IDX_CONST0) ||
+			(i == IMXDPUV1_SHDLD_IDX_CONST1)) {
+			fgen |= 1;
+		}
+		mask &= ~temp_mask;
+	}
+
+	if (sub) {
+		IMXDPUV1_TRACE_IRQ("Fetch layer shadow request 0x%08x\n", sub);
+		if (sub & 0xff) {   /* FETCHLAYER0 */
+			imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_TRIGGERENABLE,
+				sub & 0xff);
+		}
+#ifdef IMXDPUV1_VERSION_0
+		if (sub & 0xff00) { /* FETCHLAYER1 */
+			imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_TRIGGERENABLE,
+				(sub >> 8) & 0xff);
+		}
+#endif
+		if (sub & 0xff0000) {   /* FETCHWARP2 */
+			imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_TRIGGERENABLE,
+				(sub >> 16) & 0xff);
+		}
+	}
+
+	if (extdst) {
+		IMXDPUV1_TRACE_IRQ("Extdst shadow request  0x%08x\n", extdst);
+		imxdpuv1_write(imxdpu, addr_extdst, extdst);
+	}
+
+	if (fgen) {
+		IMXDPUV1_TRACE_IRQ("Fgen shadow request  0x%08x\n", fgen);
+		imxdpuv1_write(imxdpu, addr_fgen, fgen);
+	}
+
+	return ret;
+}
+
+/*!
+ * This function shows the frame generators status
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_disp_show_fgen_status(int8_t imxdpuv1_id)
+{
+#ifndef ENABLE_IMXDPUV1_TRACE
+	return 0;
+#else
+	int ret = 0;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE_IRQ("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	IMXDPUV1_PRINT("IMXDPU %d stat    			   fg0  	      fg1\n"
+		"prim_sync_state:            %10d         %10d\n"
+		"sec_sync_state:	     %10d         %10d\n"
+		"prim_sync_count:            %10d         %10d\n"
+		"sec_sync_count:	     %10d         %10d\n"
+		"skew_error_count:           %10d         %10d\n"
+		"prim_fifo_empty_count:      %10d         %10d\n"
+		"sec_fifo_empty_count:       %10d         %10d\n"
+		"frame_count:   	     %10d         %10d\n"
+		"irq_count:     	     %10u\n\n",
+		imxdpuv1_id,
+		imxdpu->fgen_stats[0].prim_sync_state,
+		imxdpu->fgen_stats[1].prim_sync_state,
+		imxdpu->fgen_stats[0].sec_sync_state,
+		imxdpu->fgen_stats[1].sec_sync_state,
+		imxdpu->fgen_stats[0].prim_sync_count,
+		imxdpu->fgen_stats[1].prim_sync_count,
+		imxdpu->fgen_stats[0].sec_sync_count,
+		imxdpu->fgen_stats[1].sec_sync_count,
+		imxdpu->fgen_stats[0].skew_error_count,
+		imxdpu->fgen_stats[1].skew_error_count,
+		imxdpu->fgen_stats[0].prim_fifo_empty_count,
+		imxdpu->fgen_stats[1].prim_fifo_empty_count,
+		imxdpu->fgen_stats[0].sec_fifo_empty_count,
+		imxdpu->fgen_stats[1].sec_fifo_empty_count,
+		imxdpu->fgen_stats[0].frame_count,
+		imxdpu->fgen_stats[1].frame_count,
+		imxdpu->irq_count);
+
+	return ret;
+#endif
+}
+
+/*!
+ * This function enables the frame generator
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ * @param       disp		id of the diplay output pipe
+ * @param       enable  	state to set frame generator to
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_disp_enable_frame_gen(int8_t imxdpuv1_id, int8_t disp, bool enable)
+{
+	int ret = 0;
+	uint32_t b_off;
+	uint32_t reg;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	if (disp == 0) {
+		b_off = IMXDPUV1_FRAMEGEN0_LOCKUNLOCK;
+	} else if (disp == 1) {
+		b_off = IMXDPUV1_FRAMEGEN1_LOCKUNLOCK;
+	} else {
+		return -EINVAL;
+	}
+
+	imxdpuv1_disp_start_shadow_loads(imxdpuv1_id, disp);
+
+	reg = enable ? IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGENABLE_FGEN, 1) :
+		       IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGENABLE_FGEN, 0);
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGENABLE_OFFSET, reg);
+
+	return ret;
+}
+
+/*!
+ * This function sets up the constframe generator
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ * @param       disp		id of the diplay output pipe
+ * @param       bg_red		background red
+ * @param       bg_green	background green
+ * @param       bg_blue		background blue
+ * @param       bg_alpha	background alpha
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_disp_setup_constframe(
+	int8_t imxdpuv1_id,
+	int8_t disp,
+	uint8_t bg_red,
+	uint8_t bg_green,
+	uint8_t bg_blue,
+	uint8_t bg_alpha)
+{
+	int ret = 0;
+	uint32_t b_off;
+	uint32_t reg;
+	struct imxdpuv1_soc *imxdpu;
+	imxdpuv1_shadow_load_index_t shadow_idx;
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	/* todo: add constfram4 and constframe5 */
+	if (disp == 0) {
+		b_off = IMXDPUV1_CONSTFRAME0_LOCKUNLOCK;
+		shadow_idx = IMXDPUV1_SHDLD_IDX_CONST0;
+	} else if (disp == 1) {
+		b_off = IMXDPUV1_CONSTFRAME1_LOCKUNLOCK;
+		shadow_idx = IMXDPUV1_SHDLD_IDX_CONST1;
+	} else {
+		return -EINVAL;
+	}
+
+	if (imxdpu->video_mode[disp].flags & IMXDPUV1_MODE_FLAGS_LRSYNC) {
+		/* todo: need to handle sync display case */
+	}
+
+	reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEHEIGHT,
+		imxdpu->video_mode[disp].vlen - 1) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEWIDTH,
+		imxdpu->video_mode[disp].hlen - 1);
+	imxdpuv1_write(imxdpu,
+		b_off + IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_OFFSET, reg);
+
+	/* todo: add linear light correction if needed */
+	imxdpuv1_write(imxdpu, b_off + IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_OFFSET,
+		IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_CONSTRED, bg_red) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_CONSTGREEN, bg_green) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_CONSTBLUE, bg_blue) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_CONSTALPHA, bg_alpha));
+
+	imxdpuv1_disp_request_shadow_load(imxdpuv1_id, disp, shadow_idx);
+
+	/* todo: add linear light correction if needed */
+	return ret;
+}
+
+/*!
+ * This function sets up a layer
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ * @param       layer   	layer data to use
+ * @param	layer_idx       layer index  to use
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_disp_setup_layer(int8_t imxdpuv1_id,
+	const imxdpuv1_layer_t *layer,
+			    imxdpuv1_layer_idx_t layer_idx,
+	bool is_top_layer)
+{
+	int ret = 0;
+	uint32_t dynamic_offset;
+	uint32_t static_offset;
+	uint32_t reg;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	IMXDPUV1_TRACE("%s():  enable %d, primary %d, secondary %d, stream 0x%08x\n", __func__,
+		layer->enable,
+		layer->primary,
+		layer->secondary,
+		layer->stream);
+	imxdpu->blend_layer[layer_idx] = *layer;
+
+	dynamic_offset = id2dynamicoffset(layer_idx + IMXDPUV1_ID_LAYERBLEND0);
+	if (dynamic_offset == IMXDPUV1_OFFSET_INVALID) {
+		return -EINVAL;
+	}
+
+	static_offset = id2blockoffset(layer_idx + IMXDPUV1_ID_LAYERBLEND0);
+	if (static_offset == IMXDPUV1_OFFSET_INVALID) {
+		return -EINVAL;
+	}
+
+	reg =
+		IMXDPUV1_SET_FIELD(
+		IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL,
+		imxdpu->blend_layer[layer_idx].primary) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL,
+		imxdpu->blend_layer[layer_idx].secondary) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN,
+		IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN__AUTOMATIC);
+	imxdpuv1_write(imxdpu, dynamic_offset, reg);
+
+	if (imxdpu->blend_layer[layer_idx].stream & IMXDPUV1_DISPLAY_STREAM_0) {
+
+		IMXDPUV1_TRACE("%s():  IMXDPUV1_DISPLAY_STREAM_0\n", __func__);
+		if (is_top_layer) {
+		reg = IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL,
+			layer_idx + IMXDPUV1_ID_LAYERBLEND0);
+		imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC, reg);
+		}
+
+		/* trigger configuration of the pipeline */
+		imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER,
+			IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_SYNC_TRIGGER_MASK);
+		imxdpuv1_disp_request_shadow_load(imxdpuv1_id, 0,
+			IMXDPUV1_SHDLD_IDX_DISP0);
+	}
+	if (imxdpu->blend_layer[layer_idx].stream & IMXDPUV1_DISPLAY_STREAM_1) {
+		IMXDPUV1_TRACE_IRQ("%s():  IMXDPUV1_DISPLAY_STREAM_1\n", __func__);
+		if (is_top_layer) {
+		reg =
+			IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL,
+			layer_idx + IMXDPUV1_ID_LAYERBLEND0);
+		imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC, reg);
+
+		}
+		/* trigger configuration of the pipeline */
+		imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER,
+			IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_SYNC_TRIGGER_MASK);
+		imxdpuv1_disp_request_shadow_load(imxdpuv1_id, 1,
+			IMXDPUV1_SHDLD_IDX_DISP1);
+	}
+
+	/* todo: add code to disable a layer */
+	return ret;
+}
+
+/*!
+ * This function sets global alpha for a blend layer
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ * @param	layer_idx       layer index  to use
+ * @param       alpha   	global alpha
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_disp_set_layer_global_alpha(int8_t imxdpuv1_id,
+	imxdpuv1_layer_idx_t layer_idx,
+	uint8_t alpha)
+{
+	int ret = 0;
+	uint32_t offset;
+	uint32_t reg;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	/* update imxdpu */
+
+	offset = id2blockoffset(layer_idx + IMXDPUV1_ID_LAYERBLEND0);
+	if (offset == IMXDPUV1_OFFSET_INVALID) {
+		return -EINVAL;
+	}
+
+	reg = IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_BLENDALPHA,
+		alpha)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC,
+		IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC,
+		IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC,
+		IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA)
+		| IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC,
+		IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE);
+	imxdpuv1_write(imxdpu, offset + IMXDPUV1_LAYERBLEND0_BLENDCONTROL_OFFSET,
+		reg);
+
+	reg =
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_CONTROL_MODE,
+		IMXDPUV1_LAYERBLEND0_CONTROL_MODE__BLEND) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE,
+		IMXDPUV1_DISABLE);
+
+	imxdpuv1_write(imxdpu, offset + IMXDPUV1_LAYERBLEND0_CONTROL_OFFSET, reg);
+
+	return ret;
+}
+
+/*!
+ * This function sets the position of the a blend layer secondary input
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ * @param	layer_idx       layer index  to use
+ * @param       x       	x position
+ * @param       y       	y position
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_disp_set_layer_position(int8_t imxdpuv1_id,
+	imxdpuv1_layer_idx_t layer_idx,
+	int16_t x, int16_t y)
+{
+	int ret = 0;
+	uint32_t offset;
+	uint32_t reg;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	/* update imxdpu */
+
+	offset = id2blockoffset(layer_idx + IMXDPUV1_ID_LAYERBLEND0);
+	if (offset == IMXDPUV1_OFFSET_INVALID) {
+		return -EINVAL;
+	}
+
+	reg = IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_POSITION_XPOS, x) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_POSITION_YPOS, y);
+	imxdpuv1_write(imxdpu, offset + IMXDPUV1_LAYERBLEND0_POSITION_OFFSET, reg);
+
+	return ret;
+}
+
+/*!
+ * This function sets the position of the a channel (window) layer
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ * @param	layer_idx       layer index  to use
+ * @param       x       	x position
+ * @param       y       	y position
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_disp_set_chan_position(int8_t imxdpuv1_id,
+	imxdpuv1_chan_t chan, int16_t x, int16_t y)
+{
+	int ret = 0;
+	uint32_t offset;
+	int idx;
+	int sub_idx;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	/* update imxdpu */
+
+	offset = id2blockoffset(get_channel_blk(chan));
+	if (offset == IMXDPUV1_OFFSET_INVALID) {
+		return -EINVAL;
+	}
+
+	idx = get_channel_idx(chan);
+	if ((idx >= IMXDPUV1_CHAN_IDX_IN_MAX) || (idx < 0)) {
+		return -EINVAL;
+	}
+
+	sub_idx = imxdpuv1_get_channel_subindex(chan);
+
+	imxdpu->chan_data[idx].dest_top = y;
+	imxdpu->chan_data[idx].dest_left = x;
+
+	imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0 =
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERXOFFSET0,
+		imxdpu->chan_data[idx].dest_left) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERYOFFSET0,
+		imxdpu->chan_data[idx].dest_top);
+
+	if (is_fetch_layer_chan(chan) || is_fetch_warp_chan(chan)) {
+		IMXDPUV1_TRACE("%s(): fetch layer or warp\n", __func__);
+		imxdpuv1_write(imxdpu,
+			offset + IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_OFFSET +
+			((IMXDPUV1_SUBCHAN_LAYER_OFFSET * sub_idx)),
+			imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0);
+
+	} else if (is_fetch_decode_chan(chan)) {
+		if (imxdpu->chan_data[idx].use_eco_fetch) {
+			imxdpuv1_disp_set_chan_position(imxdpuv1_id,
+				imxdpuv1_get_eco(chan),
+				x, y);
+		}
+		imxdpuv1_write(imxdpu,
+			offset + IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_OFFSET,
+			imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0);
+	} else if (is_fetch_eco_chan(chan)) {
+		imxdpuv1_write(imxdpu,
+			offset + IMXDPUV1_FETCHECO0_LAYEROFFSET0_OFFSET,
+			imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0);
+	} else {
+		return -EINVAL;
+	}
+
+	imxdpuv1_disp_request_shadow_load(imxdpuv1_id,
+		imxdpu->chan_data[idx].disp_id,
+		IMXDPUV1_SHDLD_IDX_CHAN_00 + idx);
+
+	return ret;
+}
+
+/*!
+ * This function sets the source and destination crop
+ * position of the a channel (window) layer
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ * @param	chan    	chan to use
+ * @param       clip_top	source y position
+ * @param       clip_left	source x position
+ * @param       clip_width	source width
+ * @param       clip_height	source height
+ * @param       dest_top	destination y
+ * @param       dest_left	destination x
+ * @param       dest_width	destination width
+ * @param       dest_height	destination height
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_disp_set_chan_crop(
+	int8_t imxdpuv1_id,
+	imxdpuv1_chan_t chan,
+	int16_t  clip_top,
+	int16_t  clip_left,
+	uint16_t clip_width,
+	uint16_t clip_height,
+	int16_t  dest_top,
+	int16_t  dest_left,
+	uint16_t dest_width,
+	uint16_t dest_height)
+{
+	int ret = 0;
+	uint32_t offset;
+	int idx;
+	int sub_idx;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	offset = id2blockoffset(get_channel_blk(chan));
+	if (offset == IMXDPUV1_OFFSET_INVALID) {
+		return -EINVAL;
+	}
+
+	idx = get_channel_idx(chan);
+	if ((idx >= IMXDPUV1_CHAN_IDX_IN_MAX) || (idx < 0)) {
+		return -EINVAL;
+	}
+
+	sub_idx = imxdpuv1_get_channel_subindex(chan);
+
+	imxdpu->chan_data[idx].dest_top    = dest_top;
+	imxdpu->chan_data[idx].dest_left   = dest_left;
+	imxdpu->chan_data[idx].dest_width  = IMXDPUV1_MIN(dest_width, clip_width);
+	imxdpu->chan_data[idx].dest_height = IMXDPUV1_MIN(dest_height, clip_height);
+	imxdpu->chan_data[idx].clip_top    = clip_top;
+	imxdpu->chan_data[idx].clip_left   = clip_left;
+	imxdpu->chan_data[idx].clip_width  = IMXDPUV1_MIN(dest_width, clip_width);
+	imxdpu->chan_data[idx].clip_height = IMXDPUV1_MIN(dest_height, clip_height);
+
+	/* Need to check more cases here */
+	if ((imxdpu->chan_data[idx].clip_height != 0) &&
+		(imxdpu->chan_data[idx].clip_width != 0)) {
+		imxdpu->chan_data[idx].fetch_layer_prop.layerproperty0 |=
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE,
+			IMXDPUV1_ENABLE);
+		imxdpu->chan_data[idx].fetch_layer_prop.clipwindowdimensions0 =
+			IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_HEIGHT,
+			imxdpu->chan_data[idx].clip_height - 1) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_WIDTH,
+			imxdpu->chan_data[idx].clip_width - 1);
+	} else {
+		imxdpu->chan_data[idx].fetch_layer_prop.layerproperty0 &=
+			~IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE_MASK;
+		imxdpu->chan_data[idx].fetch_layer_prop.clipwindowdimensions0 = 0;
+	}
+	imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0 =
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYER_XOFFSET,
+		imxdpu->chan_data[idx].dest_left - imxdpu->chan_data[idx].clip_left) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_LAYER_YOFFSET,
+		imxdpu->chan_data[idx].dest_top - imxdpu->chan_data[idx].clip_top);
+	imxdpu->chan_data[idx].fetch_layer_prop.clipwindowoffset0 =
+		IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_XOFFSET,
+		imxdpu->chan_data[idx].dest_left) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_YOFFSET,
+		imxdpu->chan_data[idx].dest_top);
+
+	if (is_fetch_layer_chan(chan) || is_fetch_warp_chan(chan)) {
+		imxdpuv1_write_block(imxdpu,
+			offset +
+			IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_OFFSET +
+			((IMXDPUV1_SUBCHAN_LAYER_OFFSET * sub_idx)),
+			(void *)&imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0,
+			5);
+
+	} else if (is_fetch_decode_chan(chan)) {
+		if (imxdpu->chan_data[idx].use_eco_fetch) {
+			imxdpuv1_disp_set_chan_crop(imxdpuv1_id,
+				imxdpuv1_get_eco(chan),
+				clip_top,
+				clip_left,
+				clip_width,
+				clip_height,
+				dest_top,
+				dest_left,
+				dest_width,
+				dest_height);
+		}
+		imxdpuv1_write_block(imxdpu,
+			offset +
+			IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_OFFSET,
+			(void *)&imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0,
+			5);
+	} else if (is_fetch_eco_chan(chan)) {
+		imxdpuv1_write_block(imxdpu,
+			offset + IMXDPUV1_FETCHECO0_LAYEROFFSET0_OFFSET,
+			(void *)&imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0,
+			5);
+
+	} else {
+		return -EINVAL;
+	}
+	imxdpuv1_disp_request_shadow_load(imxdpuv1_id,
+		imxdpu->chan_data[idx].disp_id,
+		IMXDPUV1_SHDLD_IDX_CHAN_00 + idx);
+
+	return ret;
+}
+
+/*!
+ * This function sets initializes a channel and buffer
+ *
+ * @param	imxdpuv1_id	id of the diplay unit
+ * @param	chan    	chan to use
+ * @param       src_pixel_fmt   source pixel format
+ * @param       clip_top	source y position
+ * @param       clip_left	source x position
+ * @param       clip_width	source width
+ * @param       clip_height	source height
+ * @param       stride		stride of the buffer
+ * @param       disp_id		display id
+ * @param       dest_top	destination y
+ * @param       dest_left	destination x
+ * @param       dest_width	destination width
+ * @param       dest_height	destination height
+ * @param       const_color     constant color for clip region
+ * @param       disp_addr	display buffer physical address
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_disp_setup_channel(int8_t imxdpuv1_id,
+	imxdpuv1_chan_t chan,
+	uint32_t src_pixel_fmt,
+	uint16_t src_width,
+	uint16_t src_height,
+	int16_t clip_top,
+	int16_t clip_left,
+	uint16_t clip_width,
+	uint16_t clip_height,
+	uint16_t stride,
+	uint8_t disp_id,
+	int16_t dest_top,
+	int16_t dest_left,
+	uint16_t dest_width,
+	uint16_t dest_height,
+	uint32_t const_color,
+	bool use_global_alpha,
+	bool use_local_alpha,
+	unsigned int disp_addr)
+{
+	int ret = 0;
+	imxdpuv1_channel_params_t channel;
+	uint32_t uv_offset = 0;
+
+	IMXDPUV1_TRACE("%s(): "
+		"imxdpuv1_id     %d\n"
+		"chan_t chan   %x\n"
+		"src_pixel_fmt 0x%x\n"
+		"src_width     %d\n"
+		"src_height    %d\n"
+		"clip_top      %d\n"
+		"clip_left     %d\n"
+		"clip_width    %d\n"
+		"clip_height   %d\n"
+		"stride        %d\n"
+		"disp_id       %d\n"
+		"dest_top      %d\n"
+		"dest_left     %d\n"
+		"dest_width    %d\n"
+		"dest_height   %d\n"
+		"const_color   0x%x\n"
+		"disp_addr     0x%x\n",
+		__func__,
+		imxdpuv1_id,
+		chan,
+		src_pixel_fmt,
+		src_width,
+		src_height,
+		clip_top,
+		clip_left,
+		clip_width,
+		clip_height,
+		stride,
+		disp_id,
+		dest_top,
+		dest_left,
+		dest_width,
+		dest_height,
+		const_color,
+		disp_addr);
+
+	channel.common.chan = chan;
+	channel.common.src_pixel_fmt = src_pixel_fmt;
+	channel.common.src_width = src_width;
+	channel.common.src_height = src_height;
+	channel.common.clip_top = clip_top;
+	channel.common.clip_left = clip_left;
+	channel.common.clip_width = clip_width;
+	channel.common.clip_height = clip_height;
+	channel.common.stride = stride;
+	channel.common.disp_id = disp_id;
+	channel.common.dest_top = dest_top;
+	channel.common.dest_left = dest_left;
+	channel.common.dest_width = dest_width;
+	channel.common.dest_height = dest_height;
+	channel.common.const_color = const_color;
+	channel.common.use_global_alpha = use_global_alpha;
+	channel.common.use_local_alpha = use_local_alpha;
+
+	if (imxdpuv1_get_planes(src_pixel_fmt) == 2) {
+		uv_offset = src_width * src_height; /* works for NV12 and NV16*/
+	}
+	ret = imxdpuv1_init_channel(imxdpuv1_id, &channel);
+
+	ret = imxdpuv1_init_channel_buffer(imxdpuv1_id, channel.common.chan, channel.common.stride, IMXDPUV1_ROTATE_NONE,
+		disp_addr,
+		uv_offset,
+		0);
+
+	ret = imxdpuv1_disp_set_chan_crop(imxdpuv1_id,
+		channel.common.chan,
+		channel.common.clip_top,
+		channel.common.clip_left,
+		channel.common.clip_width,
+		channel.common.clip_height,
+		channel.common.dest_top,
+		channel.common.dest_left,
+		channel.common.dest_width,
+		channel.common.dest_height);
+
+#ifdef DEBUG
+	{
+		imxdpuv1_chan_t eco_chan;
+		imxdpuv1_dump_channel(imxdpuv1_id, channel.common.chan);
+		eco_chan = imxdpuv1_get_eco(channel.common.chan);
+		if (eco_chan != 0) {
+			imxdpuv1_dump_channel(imxdpuv1_id, eco_chan);
+		}
+	}
+#endif
+	return ret;
+}
+
+/*!
+ * This function prints the video mode passed as a parameter
+ *
+ * @param	*mode	pointer to video mode struct to show
+ */
+void imxdpuv1_disp_dump_mode(const struct imxdpuv1_videomode *mode)
+{
+	IMXDPUV1_PRINT("%s():\n", __func__);
+	IMXDPUV1_PRINT("\thlen   %4d\n", mode->hlen);
+	IMXDPUV1_PRINT("\thfp    %4d\n", mode->hfp);
+	IMXDPUV1_PRINT("\thbp    %4d\n", mode->hbp);
+	IMXDPUV1_PRINT("\thsync  %4d\n", mode->hsync);
+	IMXDPUV1_PRINT("\tvlen   %4d\n", mode->vlen);
+	IMXDPUV1_PRINT("\tvfp    %4d\n", mode->vfp);
+	IMXDPUV1_PRINT("\tvbp    %4d\n", mode->vbp);
+	IMXDPUV1_PRINT("\tvsync  %4d\n", mode->vsync);
+	IMXDPUV1_PRINT("\tvlen1  %4d\n", mode->vlen1);
+	IMXDPUV1_PRINT("\tvfp1   %4d\n", mode->vfp1);
+	IMXDPUV1_PRINT("\tvbp1   %4d\n", mode->vbp1);
+	IMXDPUV1_PRINT("\tvsync1 %4d\n", mode->vsync1);
+
+	IMXDPUV1_PRINT("\tflags 0x%08x:\n", mode->flags);
+
+	if (mode->flags & IMXDPUV1_MODE_FLAGS_HSYNC_POL)
+		IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_HSYNC_POL is high\n");
+	else
+		IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_HSYNC_POL is low\n");
+	if (mode->flags & IMXDPUV1_MODE_FLAGS_VSYNC_POL)
+		IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_VSYNC_POL is high\n");
+	else
+		IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_VSYNC_POL is low\n");
+	if (mode->flags & IMXDPUV1_MODE_FLAGS_DE_POL)
+		IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_DE_POL is high\n");
+	else
+		IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_DE_POL is low\n");
+
+	if (mode->flags & IMXDPUV1_MODE_FLAGS_INTERLACED)
+		IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_INTERLACED is set\n");
+	if (mode->flags & IMXDPUV1_MODE_FLAGS_LRSYNC)
+		IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_LRSYNC is set\n");
+	if (mode->flags & IMXDPUV1_MODE_FLAGS_SPLIT)
+		IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_SPLIT is set\n");
+	if (mode->flags & IMXDPUV1_MODE_FLAGS_32BIT)
+		IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_32BIT is set\n");
+	if (mode->flags & IMXDPUV1_MODE_FLAGS_BT656_10BIT)
+		IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_BT656_10BIT is set\n");
+	if (mode->flags & IMXDPUV1_MODE_FLAGS_BT656_8BIT)
+		IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_BT656_8BIT is set\n");
+}
+
+/*!
+ * Returns the bytes per pixel
+ *
+ * @param	pixel format
+ *
+ * @return      returns number of bytes per pixel or zero
+ *      	if the format is not matched.
+ */
+int imxdpuv1_bytes_per_pixel(uint32_t fmt)
+{
+	IMXDPUV1_TRACE("%s():\n", __func__);
+	switch (fmt) {
+	/* todo add NV12, and NV16 */
+	case IMXDPUV1_PIX_FMT_NV12:
+		return 1; /* luma */
+
+	case IMXDPUV1_PIX_FMT_RGB565:
+	case IMXDPUV1_PIX_FMT_YUYV:
+	case IMXDPUV1_PIX_FMT_UYVY:
+		return 2;
+		break;
+	case IMXDPUV1_PIX_FMT_BGR24:
+	case IMXDPUV1_PIX_FMT_RGB24:
+	case IMXDPUV1_PIX_FMT_YUV444:
+		return 3;
+		break;
+	case IMXDPUV1_PIX_FMT_GENERIC_32:
+	case IMXDPUV1_PIX_FMT_BGR32:
+	case IMXDPUV1_PIX_FMT_BGRA32:
+	case IMXDPUV1_PIX_FMT_RGB32:
+	case IMXDPUV1_PIX_FMT_RGBA32:
+	case IMXDPUV1_PIX_FMT_ABGR32:
+	case IMXDPUV1_PIX_FMT_AYUV:
+		return 4;
+		break;
+	default:
+		IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__);
+		return 0;
+	}
+}
+
+/*!
+ * Returns the number of bits per color component for the color
+ * component bits register
+ *
+ * @param	pixel format
+ *
+ * @return      Returns the number of bits per color component for
+ *      	the color component bits register.
+ */
+uint32_t imxdpuv1_get_colorcomponentbits(uint32_t fmt)
+{
+	IMXDPUV1_TRACE("%s():\n", __func__);
+	switch (fmt) {
+	/* todo add NV12, NV16, YUYV, and  UYVY */
+	case IMXDPUV1_PIX_FMT_YUYV:
+	case IMXDPUV1_PIX_FMT_UYVY:
+		return
+		IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x08) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x08) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x08) |
+		IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x00);
+	case IMXDPUV1_PIX_FMT_NV12:
+		return
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x08) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x00) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x00) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x00);
+
+	case IMXDPUV1_PIX_FMT_RGB565:
+		return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 5) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 11) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0);
+
+	case IMXDPUV1_PIX_FMT_BGR24:
+	case IMXDPUV1_PIX_FMT_RGB24:
+	case IMXDPUV1_PIX_FMT_YUV444:
+	case IMXDPUV1_PIX_FMT_BGR32:
+	case IMXDPUV1_PIX_FMT_RGB32:
+		return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x08) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x08) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x08) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x0);
+
+	case IMXDPUV1_PIX_FMT_GENERIC_32:
+	case IMXDPUV1_PIX_FMT_BGRA32:
+	case IMXDPUV1_PIX_FMT_RGBA32:
+	case IMXDPUV1_PIX_FMT_ABGR32:
+	case IMXDPUV1_PIX_FMT_ARGB32:
+	case IMXDPUV1_PIX_FMT_AYUV:
+		return
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x08) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x08) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x08) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x08);
+	default:
+		IMXDPUV1_TRACE("%s(): unsupported pixel format 0x%08x", __func__, fmt);
+		return 0;
+	}
+	return 0;
+}
+
+/*!
+ * Returns the number of planes for the pixel format
+ *
+ * @param	pixel format
+ *
+ * @return      returns number of bytes per pixel or zero
+ *      	if the format is not matched.
+ */
+uint32_t imxdpuv1_get_planes(uint32_t fmt)
+{
+	IMXDPUV1_TRACE("%s():\n", __func__);
+	switch (fmt) {
+	case IMXDPUV1_PIX_FMT_NV16:
+	case IMXDPUV1_PIX_FMT_NV12:
+		return  2;
+
+	case IMXDPUV1_PIX_FMT_RGB565:
+	case IMXDPUV1_PIX_FMT_YUYV:
+	case IMXDPUV1_PIX_FMT_UYVY:
+	case IMXDPUV1_PIX_FMT_BGRA32:
+	case IMXDPUV1_PIX_FMT_RGBA32:
+	case IMXDPUV1_PIX_FMT_ABGR32:
+	case IMXDPUV1_PIX_FMT_AYUV:
+	case IMXDPUV1_PIX_FMT_BGR24:
+	case IMXDPUV1_PIX_FMT_RGB24:
+	case IMXDPUV1_PIX_FMT_YUV444:
+	case IMXDPUV1_PIX_FMT_BGR32:
+	case IMXDPUV1_PIX_FMT_RGB32:
+	case IMXDPUV1_PIX_FMT_ARGB32:
+		return 1;
+	default:
+		return 0;
+		IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__);
+	}
+}
+
+/*!
+ * Returns the color component bit position shifts
+ *
+ * @param	pixel format
+ *
+ * @return      returns the register setting for the
+  *		colorcomponentshift register
+  *
+ */
+uint32_t imxdpuv1_get_colorcomponentshift(uint32_t fmt)
+{
+	IMXDPUV1_TRACE("%s():\n", __func__);
+	switch (fmt) {
+
+	case IMXDPUV1_PIX_FMT_NV12:
+		return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x0) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x0) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x0) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x0);
+
+	case IMXDPUV1_PIX_FMT_RGB565:
+		return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 5) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 6) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 5) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0);
+	case IMXDPUV1_PIX_FMT_YUYV:
+		return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x0) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x8) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x8) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x0);
+	case IMXDPUV1_PIX_FMT_UYVY:
+		return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x8) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x0) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x0) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x0);
+
+	case IMXDPUV1_PIX_FMT_BGR24:
+	case IMXDPUV1_PIX_FMT_BGR32:
+	case IMXDPUV1_PIX_FMT_BGRA32:
+		/* 0xaaRRGGBB */
+		return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x10) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x08) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x00) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x18);
+	case IMXDPUV1_PIX_FMT_AYUV:
+		/* 0xVVUUYYAA  */
+		return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x08) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x10) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x18) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x00);
+
+	case IMXDPUV1_PIX_FMT_ABGR32:
+		/* 0xRRGGBBAA */
+		return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x18) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x10) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x08) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x00);
+
+	case IMXDPUV1_PIX_FMT_ARGB32:
+		/* 0xBBGGRRAA */
+		return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x08) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x10) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x18) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x00);
+	case IMXDPUV1_PIX_FMT_GENERIC_32:
+	case IMXDPUV1_PIX_FMT_RGB24:
+	case IMXDPUV1_PIX_FMT_YUV444:
+	case IMXDPUV1_PIX_FMT_RGB32:
+	case IMXDPUV1_PIX_FMT_RGBA32:
+		/* 0xaaBBGGRR or 0xaaUUVVYY */
+		return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x00) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x08) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x10) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x18);
+	default:
+		return 0;
+		IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__);
+	}
+}
+
+/*!
+ * Returns true is the format has local alpha
+ *
+ * @param	pixel format
+ *
+ * @return      Returns true is the format has local alpha
+ */
+uint32_t imxdpuv1_has_localalpha(uint32_t fmt)
+{
+	IMXDPUV1_TRACE("%s():\n", __func__);
+	switch (fmt) {
+	case IMXDPUV1_PIX_FMT_BGRA32:
+	case IMXDPUV1_PIX_FMT_AYUV:
+	case IMXDPUV1_PIX_FMT_RGBA32:
+		return IMXDPUV1_TRUE;
+	default:
+		return IMXDPUV1_FALSE;
+	}
+}
+
+/*!
+ * Returns the bits per pixel
+ *
+ * @param	pixel format
+ *
+ * @return      returns number of bits per pixel or zero
+ *      	if the format is not matched.
+ */
+int imxdpuv1_bits_per_pixel(uint32_t fmt)
+{
+	int ret = 0;
+	switch (fmt) {
+	case IMXDPUV1_PIX_FMT_NV12:
+		ret = 8;
+		break;
+	case IMXDPUV1_PIX_FMT_NV16:
+	case IMXDPUV1_PIX_FMT_RGB565:
+	case IMXDPUV1_PIX_FMT_YUYV:
+	case IMXDPUV1_PIX_FMT_UYVY:
+	case IMXDPUV1_PIX_FMT_YVYU:
+		ret = 16;
+		break;
+	case IMXDPUV1_PIX_FMT_BGR24:
+	case IMXDPUV1_PIX_FMT_RGB24:
+	case IMXDPUV1_PIX_FMT_YUV444:
+		ret = 24;
+		break;
+
+	case IMXDPUV1_PIX_FMT_GENERIC_32:
+	case IMXDPUV1_PIX_FMT_BGR32:
+	case IMXDPUV1_PIX_FMT_BGRA32:
+	case IMXDPUV1_PIX_FMT_RGB32:
+	case IMXDPUV1_PIX_FMT_RGBA32:
+	case IMXDPUV1_PIX_FMT_ABGR32:
+	case IMXDPUV1_PIX_FMT_ARGB32:
+	case IMXDPUV1_PIX_FMT_AYUV:
+		ret = 32;
+		break;
+	default:
+		IMXDPUV1_TRACE("%s(): unsupported pixel format\n", __func__);
+		ret = 1;
+		break;
+	}
+	IMXDPUV1_TRACE("%s(): fmt 0x%08x, ret %d\n", __func__, fmt, ret);
+
+	return ret;
+}
+
+/*!
+ * Tests for YUV
+ *
+ * @param	pixel format
+ *
+ * @return      returns true if the format is YUV.
+ */
+static bool imxdpuv1_is_yuv(uint32_t fmt)
+{
+	int ret = IMXDPUV1_FALSE;
+	switch (fmt) {
+	case IMXDPUV1_PIX_FMT_AYUV:
+	case IMXDPUV1_PIX_FMT_NV12:
+	case IMXDPUV1_PIX_FMT_NV16:
+	case IMXDPUV1_PIX_FMT_YUYV:
+	case IMXDPUV1_PIX_FMT_UYVY:
+	case IMXDPUV1_PIX_FMT_YUV444:
+		ret = IMXDPUV1_TRUE;
+		break;
+	case IMXDPUV1_PIX_FMT_GENERIC_32:
+	case IMXDPUV1_PIX_FMT_BGR32:
+	case IMXDPUV1_PIX_FMT_BGRA32:
+	case IMXDPUV1_PIX_FMT_RGB32:
+	case IMXDPUV1_PIX_FMT_RGBA32:
+	case IMXDPUV1_PIX_FMT_ABGR32:
+	case IMXDPUV1_PIX_FMT_ARGB32:
+	case IMXDPUV1_PIX_FMT_RGB565:
+	case IMXDPUV1_PIX_FMT_BGR24:
+	case IMXDPUV1_PIX_FMT_RGB24:
+		ret = IMXDPUV1_FALSE;
+		break;
+
+	default:
+		IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__);
+		ret = IMXDPUV1_FALSE;
+		break;
+	}
+	IMXDPUV1_TRACE("%s(): fmt 0x%08x, ret %d\n", __func__, fmt, ret);
+
+	return ret;
+}
+
+/*!
+ * Tests for RGB formats
+ *
+ * @param	pixel format
+ *
+ * @return 	returns true if the format is any supported RGB
+ */
+bool imxdpuv1_is_rgb(uint32_t fmt)
+{
+	int ret = IMXDPUV1_FALSE;
+	switch (fmt) {
+	case IMXDPUV1_PIX_FMT_AYUV:
+	case IMXDPUV1_PIX_FMT_NV12:
+	case IMXDPUV1_PIX_FMT_NV16:
+	case IMXDPUV1_PIX_FMT_YUYV:
+	case IMXDPUV1_PIX_FMT_UYVY:
+	case IMXDPUV1_PIX_FMT_YUV444:
+	case IMXDPUV1_PIX_FMT_GENERIC_32:
+		ret = IMXDPUV1_FALSE;
+		break;
+	case IMXDPUV1_PIX_FMT_BGR32:
+	case IMXDPUV1_PIX_FMT_BGRA32:
+	case IMXDPUV1_PIX_FMT_RGB32:
+	case IMXDPUV1_PIX_FMT_RGBA32:
+	case IMXDPUV1_PIX_FMT_ABGR32:
+	case IMXDPUV1_PIX_FMT_ARGB32:
+	case IMXDPUV1_PIX_FMT_RGB565:
+	case IMXDPUV1_PIX_FMT_BGR24:
+	case IMXDPUV1_PIX_FMT_RGB24:
+		ret = IMXDPUV1_TRUE;
+		break;
+
+	default:
+		IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__);
+		ret = IMXDPUV1_FALSE;
+		break;
+	}
+	IMXDPUV1_TRACE("%s(): fmt 0x%08x, ret %d\n", __func__, fmt, ret);
+
+	return ret;
+}
+
+/*!
+ * Intializes buffers to be used for a channel
+ *
+ * @param       imxdpuv1_id       id of the diplay unit
+ * @param       chan    	channel to use for this buffer
+ * @param       stride  	total width in the buffer in pixels
+ * @param       rot_mode	rotatation mode
+ * @param       phyaddr_0       buffer 0 address
+ * @param       u_offset	U offset
+ * @param       v_offset	V offset
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_init_channel_buffer(
+	int8_t imxdpuv1_id,
+	imxdpuv1_chan_t chan,
+	uint32_t stride,
+	imxdpuv1_rotate_mode_t rot_mode,
+	dma_addr_t phyaddr_0,
+	uint32_t u_offset,
+	uint32_t v_offset)
+{
+	int ret = 0;
+	uint32_t b_off;
+	struct imxdpuv1_soc *imxdpu;
+	imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan);
+	int sub_idx = imxdpuv1_get_channel_subindex(chan);
+	bool enable_clip = IMXDPUV1_FALSE;
+	bool enable_buffer = IMXDPUV1_TRUE;
+	uint8_t enable_yuv = IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__OFF;
+	uint8_t input_select = IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__INACTIVE;
+	uint32_t fwidth;
+	uint32_t fheight;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	if (!is_chan(chan)) {
+		return -EINVAL;
+	}
+
+	b_off = id2blockoffset(get_channel_blk(chan));
+	if (b_off == IMXDPUV1_OFFSET_INVALID) {
+		return -EINVAL;
+	}
+
+	imxdpu->chan_data[chan_idx].phyaddr_0 = phyaddr_0;
+	imxdpu->chan_data[chan_idx].u_offset = u_offset;
+	imxdpu->chan_data[chan_idx].v_offset = v_offset;
+
+	/* update stride if provided */
+	if (stride != 0) {
+		/* todo: check stride range */
+		imxdpu->chan_data[chan_idx].stride = stride;
+	}
+
+	/* common fetch setup */
+	if (!is_store_chan(chan)) {
+		/* default horizontal scan
+		 * todo: add support for vertical and warp scans
+		 */
+		if (sub_idx == 0) {
+			imxdpuv1_write(imxdpu,
+				b_off +
+				IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_OFFSET,
+				IMXDPUV1_SET_FIELD(
+					IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH,
+					burst_param[IMXDPUV1_BURST_HORIZONTAL].
+					len) |
+				IMXDPUV1_SET_FIELD(
+					IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS,
+					burst_param[IMXDPUV1_BURST_HORIZONTAL].buffers));
+		}
+		/* todo: Add range checking here */
+		imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0 = phyaddr_0;
+		imxdpu->chan_data[chan_idx].fetch_layer_prop.sourcebufferattributes0 =
+			IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_ATTR_BITSPERPIXEL,
+			imxdpuv1_bits_per_pixel(
+				imxdpu->chan_data[chan_idx].src_pixel_fmt)) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_ATTR_STRIDE,
+			imxdpu->chan_data[chan_idx].stride - 1);
+		imxdpu->chan_data[chan_idx].fetch_layer_prop.sourcebufferdimension0 =
+			IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_DIMEN_LINECOUNT,
+			imxdpu->chan_data[chan_idx].src_height - 1) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_DIMEN_LINEWIDTH,
+			imxdpu->chan_data[chan_idx].src_width - 1);
+		imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentbits0 =
+			imxdpuv1_get_colorcomponentbits(
+			imxdpu->chan_data[chan_idx].src_pixel_fmt);
+		imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentshift0 =
+			imxdpuv1_get_colorcomponentshift(
+			imxdpu->chan_data[chan_idx].src_pixel_fmt);
+
+		imxdpu->chan_data[chan_idx].fetch_layer_prop.layeroffset0 =
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYER_XOFFSET,
+			imxdpu->chan_data[chan_idx].dest_left) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYER_YOFFSET,
+			imxdpu->chan_data[chan_idx].dest_top);
+		imxdpu->chan_data[chan_idx].fetch_layer_prop.clipwindowoffset0 =
+			IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_XOFFSET,
+			imxdpu->chan_data[chan_idx].clip_left) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_YOFFSET,
+			imxdpu->chan_data[chan_idx].clip_top);
+		imxdpu->chan_data[chan_idx].fetch_layer_prop.clipwindowdimensions0 =
+			IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_HEIGHT,
+			imxdpu->chan_data[chan_idx].clip_height - 1) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_WIDTH,
+			imxdpu->chan_data[chan_idx].clip_width - 1);
+		if ((imxdpu->chan_data[chan_idx].clip_height != 0) &&
+			(imxdpu->chan_data[chan_idx].clip_width != 0)) {
+			imxdpu->chan_data[chan_idx].fetch_layer_prop.clipwindowdimensions0 =
+				IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_HEIGHT,
+				imxdpu->chan_data[chan_idx].clip_height - 1) |
+				IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_WIDTH,
+				imxdpu->chan_data[chan_idx].clip_width - 1);
+
+			enable_clip = IMXDPUV1_ENABLE;
+		} else {
+			imxdpu->chan_data[chan_idx].fetch_layer_prop.clipwindowdimensions0 = 0;
+		}
+
+		imxdpu->chan_data[chan_idx].fetch_layer_prop.constantcolor0 =
+			imxdpu->chan_data[chan_idx].const_color;
+
+		if (imxdpu->chan_data[chan_idx].phyaddr_0 == 0) {
+			enable_buffer = IMXDPUV1_FALSE;
+		}
+		if (imxdpuv1_is_yuv(imxdpu->chan_data[chan_idx].src_pixel_fmt)) {
+			/* TODO: need to get correct encoding range */
+			enable_yuv = IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__ITU601;
+		}
+	}
+
+
+	if (is_fetch_decode_chan(chan)) {
+		IMXDPUV1_TRACE("%s(): fetch decode channel\n", __func__);
+		if (imxdpu->chan_data[chan_idx].use_eco_fetch) {
+			input_select = IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__COMPPACK;
+			if (chan == IMXDPUV1_CHAN_01) {
+				imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC,
+					IMXDPUV1_SET_FIELD(
+						IMXDPUV1_PIXENGCFG_SRC_SEL,
+						IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL__FETCHECO0));
+			} else if (chan == IMXDPUV1_CHAN_19) {
+				imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC,
+					IMXDPUV1_SET_FIELD(
+						IMXDPUV1_PIXENGCFG_SRC_SEL,
+						IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL__FETCHECO1));
+			}
+			imxdpuv1_init_channel_buffer(imxdpuv1_id,
+				imxdpuv1_get_eco(chan),
+				stride,
+				rot_mode,
+				phyaddr_0,
+				u_offset, v_offset);
+
+			imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentbits0 =
+				(0x08 << IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT);
+			imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentshift0 =
+				(0x00 << IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT);
+
+		} /* else need to handle Alpha, Warp, CLUT ... */
+
+		imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 =
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE,
+			enable_buffer) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE,
+			enable_yuv) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE,
+				enable_clip) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE,
+				imxdpu->chan_data[chan_idx].use_global_alpha) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE,
+				imxdpu->chan_data[chan_idx].use_local_alpha);
+
+		/* todo: handle all cases for control register */
+		imxdpuv1_write(imxdpu,
+			b_off + IMXDPUV1_FETCHDECODE0_CONTROL_OFFSET,
+			IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE,
+				IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE__INTERPOLATE) |
+			IMXDPUV1_FETCHDECODE0_CONTROL_PALETTEIDXWIDTH_MASK | /* needed ?*/
+			IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR, 1) |  /*needed for clip */
+			IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT, input_select)); /*needed for eco */
+
+		imxdpuv1_write(imxdpu,
+			b_off + IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_OFFSET,
+			IMXDPUV1_SET_FIELD
+			(IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEHEIGHT,
+				imxdpu->chan_data[chan_idx].dest_height -
+				1 /*fheight-1 */) |
+			IMXDPUV1_SET_FIELD
+			(IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEWIDTH,
+				imxdpu->chan_data[chan_idx].dest_width -
+				1 /*fwidth-1 */));
+
+		imxdpuv1_write_block(imxdpu,
+			b_off + IMXDPUV1_FETCHDECODE0_BASEADDRESS0_OFFSET,
+			(void *)&imxdpu->chan_data[chan_idx].
+			fetch_layer_prop,
+			sizeof(fetch_layer_setup_t) / 4);
+		imxdpuv1_disp_request_shadow_load(imxdpuv1_id,
+			imxdpu->chan_data[chan_idx].
+			disp_id,
+			IMXDPUV1_SHDLD_IDX_CHAN_00 +
+			chan_idx);
+	} else if (is_fetch_layer_chan(chan)) {
+		IMXDPUV1_TRACE("%s(): fetch layer channel\n", __func__);
+		/* here the frame is shared for all sub layers so we use
+		   the video mode dimensions.
+		   fetch layer sub 1 must be setup first
+		   todo:  add a check so that any sub layer can set this */
+		if (is_fetch_layer_sub_chan1(chan)) {
+			IMXDPUV1_TRACE("%s(): fetch layer sub channel 1\n",
+				__func__);
+			fwidth =
+				imxdpuv1_array[imxdpuv1_id].
+				video_mode[imxdpuv1_array[imxdpuv1_id].
+				chan_data[chan_idx].disp_id].hlen;
+			fheight =
+				imxdpuv1_array[imxdpuv1_id].
+				video_mode[imxdpuv1_array[imxdpuv1_id].
+				chan_data[chan_idx].disp_id].vlen;
+
+			imxdpuv1_write(imxdpu,
+				b_off + IMXDPUV1_FETCHLAYER0_CONTROL_OFFSET,
+				IMXDPUV1_FETCHDECODE0_CONTROL_PALETTEIDXWIDTH_MASK | /* needed ?*/
+				IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR, 1)
+				); /*needed for eco */
+
+			imxdpuv1_write(imxdpu,
+				b_off +
+				IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_OFFSET,
+				IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEHEIGHT,
+					/*imxdpu->chan_data[chan_idx].dest_height-1 */
+					fheight - 1) |
+				IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEWIDTH,
+					/*imxdpu->chan_data[chan_idx].dest_width-1 */
+					fwidth - 1));
+		}
+		imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 =
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE,
+			enable_buffer) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE,
+			enable_yuv) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE,
+				enable_clip) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE,
+				imxdpu->chan_data[chan_idx].use_global_alpha) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE,
+				imxdpu->chan_data[chan_idx].use_local_alpha);
+
+		imxdpuv1_write_block(imxdpu,
+			b_off +
+			IMXDPUV1_FETCHLAYER0_BASEADDRESS0_OFFSET +
+			((IMXDPUV1_SUBCHAN_LAYER_OFFSET * sub_idx)),
+			(void *)&imxdpu->chan_data[chan_idx].
+			fetch_layer_prop,
+			sizeof(fetch_layer_setup_t) / 4);
+		imxdpuv1_write(imxdpu,
+			b_off + IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_OFFSET,
+			get_channel_sub(chan));
+		imxdpuv1_disp_request_shadow_load(imxdpuv1_id,
+			imxdpu->chan_data[chan_idx].
+			disp_id,
+			IMXDPUV1_SHDLD_IDX_CHAN_00 +
+			chan_idx);
+	} else if (is_fetch_warp_chan(chan)) {
+		/* here the frame is shared for all sub layers so we use
+		   the video mode dimensions.
+		   fetch layer sub 1 must be setup first
+		   todo:  add a check so that any sub layer can set this */
+		if (is_fetch_layer_sub_chan1(chan)) {
+			IMXDPUV1_TRACE("%s(): fetch layer sub channel 1\n",
+				__func__);
+			fwidth =
+				imxdpuv1_array[imxdpuv1_id].
+				video_mode[imxdpuv1_array[imxdpuv1_id].
+				chan_data[chan_idx].disp_id].hlen;
+			fheight =
+				imxdpuv1_array[imxdpuv1_id].
+				video_mode[imxdpuv1_array[imxdpuv1_id].
+				chan_data[chan_idx].disp_id].vlen;
+
+			imxdpuv1_write(imxdpu,
+				b_off + IMXDPUV1_FETCHWARP2_CONTROL_OFFSET, 0x700);
+
+			imxdpuv1_write(imxdpu,
+				b_off +
+				IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_OFFSET,
+				IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEHEIGHT,
+					/*imxdpu->chan_data[chan_idx].dest_height-1 */
+					fheight - 1) |
+				IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEWIDTH,
+					/*imxdpu->chan_data[chan_idx].dest_width-1 */
+					fwidth - 1));
+		}
+		imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 =
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE,
+			enable_buffer) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE,
+			enable_yuv) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE,
+				enable_clip) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE,
+				imxdpu->chan_data[chan_idx].use_global_alpha) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE,
+				imxdpu->chan_data[chan_idx].use_local_alpha);
+
+		imxdpuv1_write_block(imxdpu,
+			b_off +
+			IMXDPUV1_FETCHWARP2_BASEADDRESS0_OFFSET +
+			(IMXDPUV1_SUBCHAN_LAYER_OFFSET * sub_idx),
+			(void *)&imxdpu->chan_data[chan_idx].
+			fetch_layer_prop,
+			sizeof(fetch_layer_setup_t) / 4);
+		imxdpuv1_write(imxdpu,
+			b_off + IMXDPUV1_FETCHWARP2_TRIGGERENABLE_OFFSET,
+			get_channel_sub(chan));
+		imxdpuv1_disp_request_shadow_load(imxdpuv1_id,
+			imxdpu->chan_data[chan_idx].
+			disp_id,
+			IMXDPUV1_SHDLD_IDX_CHAN_00 +
+			chan_idx);
+	} else if (is_fetch_eco_chan(chan)) {
+		IMXDPUV1_TRACE("%s(): fetch eco setup\n", __func__);
+		if (imxdpu->chan_data[chan_idx].src_pixel_fmt == IMXDPUV1_PIX_FMT_NV12) {
+			imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0 =  phyaddr_0 + u_offset;
+			imxdpu->chan_data[chan_idx].fetch_layer_prop.sourcebufferattributes0 =
+				IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_ATTR_BITSPERPIXEL, 16) |
+				IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_ATTR_STRIDE,
+				imxdpu->chan_data[chan_idx].stride - 1);
+
+			/* chroma resolution*/
+			imxdpu->chan_data[chan_idx].fetch_layer_prop.sourcebufferdimension0 =
+				IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_DIMEN_LINECOUNT,
+				imxdpu->chan_data[chan_idx].src_height / 2 - 1) |
+				IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_DIMEN_LINEWIDTH,
+				imxdpu->chan_data[chan_idx].src_width / 2 - 1);
+
+			imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentbits0 =
+				IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x0) |
+				IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x8) |
+				IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x8) |
+				IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x0);
+
+			imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentshift0 =
+				IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x0) |
+				IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x0) |
+				IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x8) |
+				IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x0);
+			imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 =
+				IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE,
+				enable_buffer) |
+				IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE,
+				enable_clip);
+
+			imxdpuv1_write(imxdpu,
+				b_off + IMXDPUV1_FETCHECO0_FRAMERESAMPLING_OFFSET,
+				IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAX, 0x2) |
+				IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAY, 0x2)
+				);
+
+			/* todo: handle all cases for control register */
+			imxdpuv1_write(imxdpu,
+				b_off + IMXDPUV1_FETCHECO0_CONTROL_OFFSET,
+				IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR, 1));
+
+			/* luma resolution */
+			imxdpuv1_write(imxdpu,
+				b_off + IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_OFFSET,
+				IMXDPUV1_SET_FIELD
+				(IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEHEIGHT,
+					imxdpu->chan_data[chan_idx].dest_height -
+					1 /*fheight-1 */) |
+				IMXDPUV1_SET_FIELD
+				(IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEWIDTH,
+					imxdpu->chan_data[chan_idx].dest_width -
+					1 /*fwidth-1 */));
+
+		} /* else need to handle Alpha, Warp, CLUT ... */
+
+		imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 =
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE,
+			enable_buffer) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE,
+			enable_clip);
+
+		imxdpuv1_write_block(imxdpu,
+			b_off + IMXDPUV1_FETCHECO0_BASEADDRESS0_OFFSET,
+			(void *)&imxdpu->chan_data[chan_idx].
+			fetch_layer_prop,
+			sizeof(fetch_layer_setup_t) / 4);
+
+		imxdpuv1_disp_request_shadow_load(imxdpuv1_id,
+			imxdpu->chan_data[chan_idx].
+			disp_id,
+			IMXDPUV1_SHDLD_IDX_CHAN_00 +
+			chan_idx);
+
+	} else if (is_store_chan(chan)) {
+		imxdpu->chan_data[chan_idx].store_layer_prop.baseaddress0 = phyaddr_0;
+		imxdpu->chan_data[chan_idx].store_layer_prop.destbufferattributes0 =
+			IMXDPUV1_SET_FIELD(
+				IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_BITSPERPIXEL,
+			imxdpuv1_bits_per_pixel(
+				imxdpu->chan_data[chan_idx].dest_pixel_fmt)) |
+			IMXDPUV1_SET_FIELD(
+				IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_STRIDE,
+			imxdpu->chan_data[chan_idx].stride-1);
+		imxdpu->chan_data[chan_idx].store_layer_prop.destbufferdimension0 =
+			IMXDPUV1_SET_FIELD(
+				IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINECOUNT,
+				imxdpu->chan_data[chan_idx].dest_height - 1) |
+			IMXDPUV1_SET_FIELD(
+				IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINEWIDTH,
+			imxdpu->chan_data[chan_idx].dest_width - 1);
+		imxdpu->chan_data[chan_idx].store_layer_prop.colorcomponentbits0 =
+			imxdpuv1_get_colorcomponentbits(
+			imxdpu->chan_data[chan_idx].dest_pixel_fmt);
+		imxdpu->chan_data[chan_idx].store_layer_prop.colorcomponentshift0 =
+			imxdpuv1_get_colorcomponentshift(
+			imxdpu->chan_data[chan_idx].dest_pixel_fmt);
+		imxdpu->chan_data[chan_idx].store_layer_prop.frameoffset0 =
+			IMXDPUV1_SET_FIELD(IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEXOFFSET,
+			-imxdpu->chan_data[chan_idx].dest_left) |
+			IMXDPUV1_SET_FIELD(IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEYOFFSET,
+			-imxdpu->chan_data[chan_idx].dest_top);
+
+
+		imxdpuv1_write_block(imxdpu,
+			b_off + IMXDPUV1_STORE9_BASEADDRESS_OFFSET,
+			(void *)&imxdpu->chan_data[chan_idx].
+			store_layer_prop,
+			sizeof(store_layer_setup_t) / 4);
+
+		if ((imxdpu->chan_data[chan_idx].dest_pixel_fmt == IMXDPUV1_PIX_FMT_YUYV) ||
+		    (imxdpu->chan_data[chan_idx].dest_pixel_fmt == IMXDPUV1_PIX_FMT_YVYU) ||
+		    (imxdpu->chan_data[chan_idx].dest_pixel_fmt == IMXDPUV1_PIX_FMT_UYVY)) {
+			imxdpuv1_write(imxdpu,
+				b_off + IMXDPUV1_STORE9_CONTROL_OFFSET,
+				IMXDPUV1_SET_FIELD(IMXDPUV1_STORE9_CONTROL_RASTERMODE,
+					IMXDPUV1_STORE9_CONTROL_RASTERMODE__YUV422));
+		}
+
+	}
+
+	/* imxdpuv1_dump_channel(imxdpuv1_id, chan); */
+
+	return ret;
+}
+
+/*!
+ * Intializes a channel
+ *
+ * @param       imxdpuv1_id       id of the diplay unit
+ * @param	chan    	channel to update
+ * @param	phyaddr_0       physical address
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int32_t imxdpuv1_update_channel_buffer(
+	int8_t imxdpuv1_id,
+	imxdpuv1_chan_t chan,
+	dma_addr_t phyaddr_0)
+{
+	int ret = 0;
+	uint32_t b_off;     /* block offset for frame generator */
+	struct imxdpuv1_soc *imxdpu;
+	imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan);
+
+	IMXDPUV1_TRACE_IRQ("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	if (!is_chan(chan)) {
+		return -EINVAL;
+	}
+
+	b_off = id2blockoffset(get_channel_blk(chan));
+	if (b_off == IMXDPUV1_OFFSET_INVALID) {
+		return -EINVAL;
+	}
+
+	if (imxdpu->chan_data[chan_idx].use_eco_fetch == IMXDPUV1_FALSE) {
+		imxdpu->chan_data[chan_idx].phyaddr_0 = phyaddr_0;
+		imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0 = phyaddr_0;
+	}
+#ifdef IMXDPUV1_VERSION_0
+	if (is_store_chan(chan)) {
+		IMXDPUV1_TRACE_IRQ("%s(): store channel\n", __func__);
+		imxdpuv1_write_irq(imxdpu,
+			b_off + IMXDPUV1_STORE4_BASEADDRESS_OFFSET,
+			imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0);
+
+		/* fixme: need to handle all pipline elements */
+		imxdpuv1_write_irq(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_REQUEST, 1);
+
+		return ret;
+	}
+#endif
+	if (is_fetch_decode_chan(chan)) {
+		IMXDPUV1_TRACE_IRQ("%s(): fetch decode channel\n", __func__);
+		if (imxdpu->chan_data[chan_idx].use_eco_fetch) {
+			imxdpuv1_update_channel_buffer(imxdpuv1_id,
+				imxdpuv1_get_eco(chan),
+				phyaddr_0);
+		}
+		imxdpuv1_write_irq(imxdpu,
+			b_off + IMXDPUV1_FETCHDECODE0_BASEADDRESS0_OFFSET,
+			imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0);
+		imxdpuv1_write_irq(imxdpu,
+			b_off + IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_OFFSET,
+			IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_SHDTOKGEN_MASK);
+	} else if (is_fetch_layer_chan(chan)) {
+		IMXDPUV1_TRACE_IRQ("%s(): fetch layer channel\n", __func__);
+		imxdpuv1_write_irq(imxdpu,
+			b_off + IMXDPUV1_FETCHLAYER0_BASEADDRESS0_OFFSET,
+			imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0);
+		imxdpuv1_write_irq(imxdpu,
+			b_off + IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_OFFSET,
+			get_channel_sub(chan));
+		imxdpuv1_write_irq(imxdpu,
+			b_off + IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_OFFSET,
+			IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_SHDTOKGEN_MASK);
+	} else if (is_fetch_warp_chan(chan)) {
+		IMXDPUV1_TRACE_IRQ("%s(): fetch warp channel\n", __func__);
+		imxdpuv1_write_irq(imxdpu,
+			b_off + IMXDPUV1_FETCHWARP2_BASEADDRESS0_OFFSET,
+			imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0);
+		imxdpuv1_write_irq(imxdpu,
+			b_off + IMXDPUV1_FETCHWARP2_TRIGGERENABLE_OFFSET,
+			get_channel_sub(chan));
+		imxdpuv1_write_irq(imxdpu,
+			b_off + IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_OFFSET,
+			IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_SHDTOKGEN_MASK);
+	} else if (is_fetch_eco_chan(chan))  {
+		IMXDPUV1_TRACE_IRQ("%s(): fetch eco channel\n", __func__);
+
+		imxdpu->chan_data[chan_idx].phyaddr_0 = phyaddr_0 + imxdpu->chan_data[chan_idx].u_offset;
+		imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0 = imxdpu->chan_data[chan_idx].phyaddr_0;
+
+		imxdpuv1_write_irq(imxdpu,
+			b_off + IMXDPUV1_FETCHDECODE0_BASEADDRESS0_OFFSET,
+			imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0);
+		imxdpuv1_write_irq(imxdpu,
+			b_off + IMXDPUV1_FETCHECO0_CONTROLTRIGGER_OFFSET,
+			IMXDPUV1_FETCHECO0_CONTROLTRIGGER_SHDTOKGEN_MASK);
+	}
+
+	return ret;
+}
+
+/*!
+ * Intializes a channel
+ *
+ * @param       imxdpuv1_id       id of the diplay unit
+ * @param	params  	pointer to channel parameters
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_init_channel(int8_t imxdpuv1_id, imxdpuv1_channel_params_t *params)
+{
+	int ret = 0;
+	struct imxdpuv1_soc *imxdpu;
+	imxdpuv1_chan_t chan = params->common.chan;
+	imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan);
+	/* here we use the video mode for channel frame width, todo: we may need to
+	   add a paramter for this */
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	if (!is_chan(chan)) {
+		return -EINVAL;
+	}
+	imxdpu->chan_data[chan_idx].chan = chan;
+
+	memset(&imxdpu->chan_data[chan_idx].fetch_layer_prop, 0,
+		sizeof(fetch_layer_setup_t));
+	imxdpu->chan_data[chan_idx].use_eco_fetch = IMXDPUV1_FALSE;
+
+	if (is_fetch_decode_chan(chan)) {
+		IMXDPUV1_TRACE("%s(): decode channel setup\n", __func__);
+		imxdpu->chan_data[chan_idx].src_pixel_fmt =
+			params->fetch_decode.src_pixel_fmt;
+		imxdpu->chan_data[chan_idx].src_width =
+			params->fetch_decode.src_width;
+		imxdpu->chan_data[chan_idx].src_height =
+			params->fetch_decode.src_height;
+		imxdpu->chan_data[chan_idx].clip_top =
+			params->fetch_decode.clip_top;
+		imxdpu->chan_data[chan_idx].clip_left =
+			params->fetch_decode.clip_left;
+		imxdpu->chan_data[chan_idx].clip_width =
+			params->fetch_decode.clip_width;
+		imxdpu->chan_data[chan_idx].clip_height =
+			params->fetch_decode.clip_height;
+		imxdpu->chan_data[chan_idx].stride =
+			params->fetch_decode.stride;
+		imxdpu->chan_data[chan_idx].dest_pixel_fmt =
+			params->fetch_decode.dest_pixel_fmt;
+		imxdpu->chan_data[chan_idx].dest_top =
+			params->fetch_decode.dest_top;
+		imxdpu->chan_data[chan_idx].dest_left =
+			params->fetch_decode.dest_left;
+		imxdpu->chan_data[chan_idx].dest_width =
+			params->fetch_decode.dest_width;
+		imxdpu->chan_data[chan_idx].dest_height =
+			params->fetch_decode.dest_height;
+		imxdpu->chan_data[chan_idx].const_color =
+			params->fetch_decode.const_color;
+		imxdpu->chan_data[chan_idx].use_global_alpha =
+			params->fetch_decode.use_global_alpha;
+		imxdpu->chan_data[chan_idx].use_local_alpha =
+			params->fetch_decode.use_local_alpha;
+		imxdpu->chan_data[chan_idx].disp_id =
+			params->fetch_decode.disp_id;
+
+		if (imxdpu->chan_data[chan_idx].use_video_proc ==
+				IMXDPUV1_TRUE) {
+			imxdpu->chan_data[chan_idx].h_scale_factor =
+				params->fetch_decode.h_scale_factor;
+			imxdpu->chan_data[chan_idx].h_phase =
+				params->fetch_decode.h_phase;
+			imxdpu->chan_data[chan_idx].v_scale_factor =
+				params->fetch_decode.v_scale_factor;
+			imxdpu->chan_data[chan_idx].v_phase[0][0] =
+				params->fetch_decode.v_phase[0][0];
+			imxdpu->chan_data[chan_idx].v_phase[0][1] =
+				params->fetch_decode.v_phase[0][1];
+			imxdpu->chan_data[chan_idx].v_phase[1][0] =
+				params->fetch_decode.v_phase[1][0];
+			imxdpu->chan_data[chan_idx].v_phase[1][1] =
+				params->fetch_decode.v_phase[1][1];
+		}
+
+		if (imxdpuv1_get_planes(imxdpu->chan_data[chan_idx].src_pixel_fmt) == 2) {
+			if (has_fetch_eco_chan(chan)) {
+				imxdpuv1_channel_params_t temp_params = *params;
+
+				imxdpu->chan_data[chan_idx].use_eco_fetch = IMXDPUV1_TRUE;
+				temp_params.fetch_decode.chan = imxdpuv1_get_eco(params->fetch_decode.chan);
+				imxdpuv1_init_channel(imxdpuv1_id, &temp_params);
+			} else {
+				return -EINVAL;
+			}
+		}
+	} else if (is_fetch_layer_chan(chan)) {
+		IMXDPUV1_TRACE("%s(): layer channel setup\n", __func__);
+		imxdpu->chan_data[chan_idx].src_pixel_fmt =
+			params->fetch_layer.src_pixel_fmt;
+		imxdpu->chan_data[chan_idx].src_width =
+			params->fetch_layer.src_width;
+		imxdpu->chan_data[chan_idx].src_height =
+			params->fetch_layer.src_height;
+		imxdpu->chan_data[chan_idx].clip_top =
+			params->fetch_layer.clip_top;
+		imxdpu->chan_data[chan_idx].clip_left =
+			params->fetch_layer.clip_left;
+		imxdpu->chan_data[chan_idx].clip_width =
+			params->fetch_layer.clip_width;
+		imxdpu->chan_data[chan_idx].clip_height =
+			params->fetch_layer.clip_height;
+		imxdpu->chan_data[chan_idx].stride =
+			params->fetch_layer.stride;
+		imxdpu->chan_data[chan_idx].dest_pixel_fmt =
+			params->fetch_layer.dest_pixel_fmt;
+		imxdpu->chan_data[chan_idx].dest_top =
+			params->fetch_layer.dest_top;
+		imxdpu->chan_data[chan_idx].dest_left =
+			params->fetch_layer.dest_left;
+		imxdpu->chan_data[chan_idx].dest_width =
+			params->fetch_layer.dest_width;
+		imxdpu->chan_data[chan_idx].dest_height =
+			params->fetch_layer.dest_height;
+		imxdpu->chan_data[chan_idx].const_color =
+			params->fetch_layer.const_color;
+		imxdpu->chan_data[chan_idx].use_global_alpha =
+			params->fetch_layer.use_global_alpha;
+		imxdpu->chan_data[chan_idx].use_local_alpha =
+			params->fetch_layer.use_local_alpha;
+		imxdpu->chan_data[chan_idx].disp_id =
+			params->fetch_layer.disp_id;
+
+	} else if (is_fetch_warp_chan(chan)) {
+		IMXDPUV1_TRACE("%s(): warp channel setup\n", __func__);
+
+		imxdpu->chan_data[chan_idx].src_pixel_fmt =
+			params->fetch_warp.src_pixel_fmt;
+		imxdpu->chan_data[chan_idx].src_width =
+			params->fetch_warp.src_width;
+		imxdpu->chan_data[chan_idx].src_height =
+			params->fetch_warp.src_height;
+		imxdpu->chan_data[chan_idx].clip_top =
+			params->fetch_warp.clip_top;
+		imxdpu->chan_data[chan_idx].clip_left =
+			params->fetch_warp.clip_left;
+		imxdpu->chan_data[chan_idx].clip_width =
+			params->fetch_warp.clip_width;
+		imxdpu->chan_data[chan_idx].clip_height =
+			params->fetch_warp.clip_height;
+		imxdpu->chan_data[chan_idx].stride =
+			params->fetch_warp.stride;
+		imxdpu->chan_data[chan_idx].dest_pixel_fmt =
+			params->fetch_warp.dest_pixel_fmt;
+		imxdpu->chan_data[chan_idx].dest_top =
+			params->fetch_warp.dest_top;
+		imxdpu->chan_data[chan_idx].dest_left =
+			params->fetch_warp.dest_left;
+		imxdpu->chan_data[chan_idx].dest_width =
+			params->fetch_warp.dest_width;
+		imxdpu->chan_data[chan_idx].dest_height =
+			params->fetch_warp.dest_height;
+		imxdpu->chan_data[chan_idx].const_color =
+			params->fetch_warp.const_color;
+		imxdpu->chan_data[chan_idx].use_global_alpha =
+			params->fetch_warp.use_global_alpha;
+		imxdpu->chan_data[chan_idx].use_local_alpha =
+			params->fetch_warp.use_local_alpha;
+		imxdpu->chan_data[chan_idx].disp_id =
+			params->fetch_warp.disp_id;
+
+	} else if (is_fetch_eco_chan(chan)) {
+
+		IMXDPUV1_TRACE("%s(): fetch eco channel setup\n", __func__);
+		imxdpu->chan_data[chan_idx].src_pixel_fmt =
+			params->fetch_decode.src_pixel_fmt;
+		imxdpu->chan_data[chan_idx].src_width =
+			params->fetch_decode.src_width;
+		imxdpu->chan_data[chan_idx].src_height =
+			params->fetch_decode.src_height;
+		imxdpu->chan_data[chan_idx].clip_top =
+			params->fetch_decode.clip_top;
+		imxdpu->chan_data[chan_idx].clip_left =
+			params->fetch_decode.clip_left;
+		imxdpu->chan_data[chan_idx].clip_width =
+			params->fetch_decode.clip_width;
+		imxdpu->chan_data[chan_idx].clip_height =
+			params->fetch_decode.clip_height;
+		imxdpu->chan_data[chan_idx].stride =
+			params->fetch_decode.stride;
+		imxdpu->chan_data[chan_idx].dest_pixel_fmt =
+			params->fetch_decode.dest_pixel_fmt;
+		imxdpu->chan_data[chan_idx].dest_top =
+			params->fetch_decode.dest_top;
+		imxdpu->chan_data[chan_idx].dest_left =
+			params->fetch_decode.dest_left;
+		imxdpu->chan_data[chan_idx].dest_width =
+			params->fetch_decode.dest_width;
+		imxdpu->chan_data[chan_idx].dest_height =
+			params->fetch_decode.dest_height;
+		imxdpu->chan_data[chan_idx].const_color =
+			params->fetch_decode.const_color;
+		imxdpu->chan_data[chan_idx].use_global_alpha =
+			params->fetch_decode.use_global_alpha;
+		imxdpu->chan_data[chan_idx].use_local_alpha =
+			params->fetch_decode.use_local_alpha;
+		imxdpu->chan_data[chan_idx].disp_id =
+			params->fetch_decode.disp_id;
+
+		if (imxdpu->chan_data[chan_idx].use_video_proc ==
+				IMXDPUV1_TRUE) {
+			imxdpu->chan_data[chan_idx].h_scale_factor =
+				params->fetch_decode.h_scale_factor;
+			imxdpu->chan_data[chan_idx].h_phase =
+				params->fetch_decode.h_phase;
+			imxdpu->chan_data[chan_idx].v_scale_factor =
+				params->fetch_decode.v_scale_factor;
+			imxdpu->chan_data[chan_idx].v_phase[0][0] =
+				params->fetch_decode.v_phase[0][0];
+			imxdpu->chan_data[chan_idx].v_phase[0][1] =
+				params->fetch_decode.v_phase[0][1];
+			imxdpu->chan_data[chan_idx].v_phase[1][0] =
+				params->fetch_decode.v_phase[1][0];
+			imxdpu->chan_data[chan_idx].v_phase[1][1] =
+				params->fetch_decode.v_phase[1][1];
+		}
+
+	} else if (is_store_chan(chan)) {
+		IMXDPUV1_TRACE("%s(): store setup\n", __func__);
+		imxdpu->chan_data[chan_idx].src_pixel_fmt =
+			params->store.src_pixel_fmt;
+		imxdpu->chan_data[chan_idx].src_width =
+			params->store.src_width;
+		imxdpu->chan_data[chan_idx].src_height =
+			params->store.src_height;
+		imxdpu->chan_data[chan_idx].clip_top =
+			params->store.clip_top;
+		imxdpu->chan_data[chan_idx].clip_left =
+			params->store.clip_left;
+		imxdpu->chan_data[chan_idx].clip_width =
+			params->store.clip_width;
+		imxdpu->chan_data[chan_idx].clip_height =
+			params->store.clip_height;
+		imxdpu->chan_data[chan_idx].stride =
+			params->store.stride;
+		imxdpu->chan_data[chan_idx].dest_pixel_fmt =
+			params->store.dest_pixel_fmt;
+		imxdpu->chan_data[chan_idx].dest_top =
+			params->store.dest_top;
+		imxdpu->chan_data[chan_idx].dest_left =
+			params->store.dest_left;
+		imxdpu->chan_data[chan_idx].dest_width =
+			params->store.dest_width;
+		imxdpu->chan_data[chan_idx].dest_height =
+			params->store.dest_height;
+		imxdpu->chan_data[chan_idx].const_color =
+			params->store.const_color;
+		imxdpu->chan_data[chan_idx].source_id =
+			params->store.capture_id;
+
+		if (imxdpu->chan_data[chan_idx].use_video_proc ==
+				IMXDPUV1_TRUE) {
+			imxdpu->chan_data[chan_idx].h_scale_factor =
+				params->store.h_scale_factor;
+			imxdpu->chan_data[chan_idx].h_phase =
+				params->store.h_phase;
+			imxdpu->chan_data[chan_idx].v_scale_factor =
+				params->store.v_scale_factor;
+			imxdpu->chan_data[chan_idx].v_phase[0][0] =
+				params->store.v_phase[0][0];
+			imxdpu->chan_data[chan_idx].v_phase[0][1] =
+				params->store.v_phase[0][1];
+			imxdpu->chan_data[chan_idx].v_phase[1][0] =
+				params->store.v_phase[1][0];
+			imxdpu->chan_data[chan_idx].v_phase[1][1] =
+				params->store.v_phase[1][1];
+		}
+
+	} else {
+		IMXDPUV1_TRACE("%s(): ERROR, invalid channel type!\n", __func__);
+		return -EINVAL;
+	}
+
+	/* imxdpuv1_dump_channel(imxdpuv1_id, chan); */
+
+	return ret;
+}
+
+/*!
+ * Dumps the fetch layer properties structure for a channel.
+ *
+ * @param       layer   	id of the diplay unit
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+void imxdpuv1_dump_fetch_layer(fetch_layer_setup_t *layer)
+{
+	IMXDPUV1_PRINT("baseaddress             0x%08x\n"
+		"sourcebufferattributes  0x%08x\n"
+		"sourcebufferdimension   h %d  w %d\n"
+		"colorcomponentbits      0x%08x\n"
+		"colorcomponentshift     0x%08x\n"
+		"layeroffset    	 y(top) %d  x(left) %d\n"
+		"clipwindowoffset        y(top) %d  x(left) %d\n"
+		"clipwindowdimensions    h %d  w %d\n"
+		"constantcolor  	 0x%08x\n"
+		"layerproperty  	 0x%08x\n",
+		layer->baseaddress0,
+		layer->sourcebufferattributes0,
+		layer->sourcebufferdimension0 >> 16,
+		layer->sourcebufferdimension0 & 0x3fff,
+		layer->colorcomponentbits0, layer->colorcomponentshift0,
+		layer->layeroffset0 >> 16, layer->layeroffset0 & 0x3fff,
+		layer->clipwindowoffset0 >> 16,
+		layer->clipwindowoffset0 & 0x3fff,
+		layer->clipwindowdimensions0 >> 16,
+		layer->clipwindowdimensions0 & 0x3fff,
+		layer->constantcolor0, layer->layerproperty0);
+	return;
+}
+/*!
+ * Dumps the store layer properties structure for a channel.
+ *
+ * @param       layer   	id of the diplay unit
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+void imxdpuv1_dump_store_layer(store_layer_setup_t  *layer)
+{
+	IMXDPUV1_TRACE(
+		"baseaddress0             0x%08x\n"
+		"destbufferattributes0    0x%08x\n"
+		"destbufferdimension0     h %d  w %d\n"
+		"frameoffset0             %d\n"
+		"colorcomponentbits0      0x%08x\n"
+		"colorcomponentshift0     0x%08x\n",
+		layer->baseaddress0,
+		layer->destbufferattributes0,
+		layer->destbufferdimension0 >> 16, layer->destbufferdimension0 & 0x3fff,
+		layer->frameoffset0,
+		layer->colorcomponentbits0,
+		layer->colorcomponentshift0);
+	return;
+}
+
+/*!
+ * Dumps the pixel engine configuration status
+ *
+ * @param       imxdpuv1_id       id of the diplay unit
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+void imxdpuv1_dump_layerblend(int8_t imxdpuv1_id)
+{
+	uint32_t reg;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS);
+	IMXDPUV1_TRACE("LAYERBLEND0_STATUS:     0x%08x\n", reg);
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS);
+	IMXDPUV1_PRINT("LAYERBLEND0_LOCKSTATUS: 0x%08x\n", reg);
+
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS);
+	IMXDPUV1_PRINT("LAYERBLEND1_STATUS:     0x%08x\n", reg);
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS);
+	IMXDPUV1_PRINT("LAYERBLEND1_LOCKSTATUS: 0x%08x\n", reg);
+
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS);
+	IMXDPUV1_PRINT("LAYERBLEND2_STATUS:     0x%08x\n", reg);
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS);
+	IMXDPUV1_PRINT("LAYERBLEND2_LOCKSTATUS: 0x%08x\n", reg);
+
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS);
+	IMXDPUV1_PRINT("LAYERBLEND3_STATUS:     0x%08x\n", reg);
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS);
+	IMXDPUV1_PRINT("LAYERBLEND3_LOCKSTATUS: 0x%08x\n", reg);
+#ifdef IMXDPUV1_VERSION_0
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND4_STATUS);
+	IMXDPUV1_PRINT("LAYERBLEND4_STATUS:     0x%08x\n", reg);
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND4_LOCKSTATUS);
+	IMXDPUV1_PRINT("LAYERBLEND4_LOCKSTATUS: 0x%08x\n", reg);
+
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND5_STATUS);
+	IMXDPUV1_PRINT("LAYERBLEND5_STATUS:     0x%08x\n", reg);
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND5_LOCKSTATUS);
+	IMXDPUV1_PRINT("LAYERBLEND5_LOCKSTATUS: 0x%08x\n", reg);
+
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND6_STATUS);
+	IMXDPUV1_PRINT("LAYERBLEND6_STATUS:     0x%08x\n", reg);
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND6_LOCKSTATUS);
+	IMXDPUV1_PRINT("LAYERBLEND6_LOCKSTATUS: 0x%08x\n", reg);
+#endif
+	return;
+}
+
+/*!
+ * Dumps the pixel engine configuration status
+ *
+ * @param       imxdpuv1_id       id of the diplay unit
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+void imxdpuv1_dump_pixencfg_status(int8_t imxdpuv1_id)
+{
+	uint32_t reg;
+	struct imxdpuv1_soc *imxdpu;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return;
+	}
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST);
+	IMXDPUV1_PRINT("EXTDST0_REQUEST:     0x%08x\n", reg);
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST);
+	IMXDPUV1_PRINT("EXTDST1_REQUEST:     0x%08x\n", reg);
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST);
+	IMXDPUV1_PRINT("EXTDST4_REQUEST:     0x%08x\n", reg);
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST);
+	IMXDPUV1_PRINT("EXTDST5_REQUEST:     0x%08x\n", reg);
+
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_STATUS);
+	IMXDPUV1_PRINT("EXTDST0_STATUS:     0x%08x\n", reg);
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_STATUS);
+	IMXDPUV1_PRINT("EXTDST1_STATUS:     0x%08x\n", reg);
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST4_STATUS);
+	IMXDPUV1_PRINT("EXTDST4_STATUS:     0x%08x\n", reg);
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST5_STATUS);
+	IMXDPUV1_PRINT("EXTDST5_STATUS:     0x%08x\n", reg);
+#ifdef IMXDPUV1_VERSION_0
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE2_STATUS);
+	IMXDPUV1_PRINT("FETCHDECODE2_STATUS:     0x%08x\n", reg);
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE3_STATUS);
+	IMXDPUV1_PRINT("FETCHDECODE3_STATUS:     0x%08x\n", reg);
+#endif
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS);
+	IMXDPUV1_PRINT("FETCHWARP2_STATUS:     0x%08x\n", reg);
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS);
+	IMXDPUV1_PRINT("FETCHECO2_STATUS:     0x%08x\n", reg);
+
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS);
+	IMXDPUV1_PRINT("FETCHDECODE0_STATUS:     0x%08x\n", reg);
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS);
+	IMXDPUV1_PRINT("FETCHECO0_STATUS:     0x%08x\n", reg);
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS);
+	IMXDPUV1_PRINT("FETCHDECODE1_STATUS:     0x%08x\n", reg);
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS);
+	IMXDPUV1_PRINT("FETCHECO1_STATUS:     0x%08x\n", reg);
+
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS);
+	IMXDPUV1_PRINT("FETCHLAYER0_STATUS:     0x%08x\n", reg);
+#ifdef IMXDPUV1_VERSION_0
+	reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHLAYER1_STATUS);
+	IMXDPUV1_PRINT("FETCHLAYER1_STATUS:     0x%08x\n", reg);
+#endif
+	return;
+}
+
+/*!
+ * Dumps the channel data
+ *
+ * @param       imxdpuv1_id       id of the diplay unit
+ * @param       chan    	channel to dump
+ *
+ * @return      This function returns 0 on success or negative error code on
+ *      	fail.
+ */
+int imxdpuv1_dump_channel(int8_t imxdpuv1_id, imxdpuv1_chan_t chan)
+{
+	int ret = 0;
+	struct imxdpuv1_soc *imxdpu;
+	imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan);
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return -EINVAL;
+	}
+
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	if (!is_chan(chan)) {
+		return -EINVAL;
+	}
+	if (is_store_chan(chan)) {
+		IMXDPUV1_PRINT("chan_id        0x%x\n"
+			"src_pixel_fmt  0x%08x\n"
+			"src_width      %d\n"
+			"src_height     %d\n"
+			"clip_top       %d(0x%04x)\n"
+			"clip_left      %d(0x%04x)\n"
+			"clip_width     %d\n"
+			"clip_height    %d\n"
+			"stride         %d\n"
+			"dest_pixel_fmt 0x%08x\n"
+			"dest_top       %d(0x%04x)\n"
+			"dest_left      %d(0x%04x)\n"
+			"dest_width     %d\n"
+			"dest_height    %d\n",
+			(uint32_t)imxdpu->chan_data[chan_idx].chan,
+			imxdpu->chan_data[chan_idx].src_pixel_fmt,
+			imxdpu->chan_data[chan_idx].src_width,
+			imxdpu->chan_data[chan_idx].src_height,
+			imxdpu->chan_data[chan_idx].clip_top,
+			imxdpu->chan_data[chan_idx].clip_top,
+			imxdpu->chan_data[chan_idx].clip_left,
+			imxdpu->chan_data[chan_idx].clip_left,
+			imxdpu->chan_data[chan_idx].clip_width,
+			imxdpu->chan_data[chan_idx].clip_height,
+			imxdpu->chan_data[chan_idx].stride,
+			imxdpu->chan_data[chan_idx].dest_pixel_fmt,
+			imxdpu->chan_data[chan_idx].dest_top,
+			imxdpu->chan_data[chan_idx].dest_top,
+			imxdpu->chan_data[chan_idx].dest_left,
+			imxdpu->chan_data[chan_idx].dest_left,
+			imxdpu->chan_data[chan_idx].dest_width,
+			imxdpu->chan_data[chan_idx].dest_height);
+
+		IMXDPUV1_PRINT(
+			"use_video_proc %d\n"
+			"use_eco_fetch  %d\n"
+			"interlaced     %d\n"
+			"phyaddr_0      0x%08x\n"
+			"rot_mode       %d\n"
+			"in_use         %d\n"
+			"use_global_alpha %d\n"
+			"use_local_alpha  %d\n",
+			imxdpu->chan_data[chan_idx].use_video_proc,
+			imxdpu->chan_data[chan_idx].use_eco_fetch,
+			imxdpu->chan_data[chan_idx].interlaced,
+			ptr_to_uint32(imxdpu->chan_data[chan_idx].phyaddr_0),
+			imxdpu->chan_data[chan_idx].rot_mode,
+			imxdpu->chan_data[chan_idx].in_use,
+			imxdpu->chan_data[chan_idx].use_global_alpha,
+			imxdpu->chan_data[chan_idx].use_local_alpha
+			);
+
+		imxdpuv1_dump_store_layer(&imxdpu->chan_data[chan_idx].store_layer_prop);
+
+	} else {
+		IMXDPUV1_PRINT("chan_id        0x%x\n"
+			"src_pixel_fmt  0x%08x\n"
+			"src_width      %d\n"
+			"src_height     %d\n"
+			"clip_top       %d(0x%04x)\n"
+			"clip_left      %d(0x%04x)\n"
+			"clip_width     %d\n"
+			"clip_height    %d\n"
+			"stride 	%d\n"
+			"dest_pixel_fmt 0x%08x\n"
+			"dest_top       %d(0x%04x)\n"
+			"dest_left      %d(0x%04x)\n"
+			"dest_width     %d\n"
+			"dest_height    %d\n",
+			(uint32_t)imxdpu->chan_data[chan_idx].chan,
+			imxdpu->chan_data[chan_idx].src_pixel_fmt,
+			imxdpu->chan_data[chan_idx].src_width,
+			imxdpu->chan_data[chan_idx].src_height,
+			imxdpu->chan_data[chan_idx].clip_top,
+			imxdpu->chan_data[chan_idx].clip_top,
+			imxdpu->chan_data[chan_idx].clip_left,
+			imxdpu->chan_data[chan_idx].clip_left,
+			imxdpu->chan_data[chan_idx].clip_width,
+			imxdpu->chan_data[chan_idx].clip_height,
+			imxdpu->chan_data[chan_idx].stride,
+			imxdpu->chan_data[chan_idx].dest_pixel_fmt,
+			imxdpu->chan_data[chan_idx].dest_top,
+			imxdpu->chan_data[chan_idx].dest_top,
+			imxdpu->chan_data[chan_idx].dest_left,
+			imxdpu->chan_data[chan_idx].dest_left,
+			imxdpu->chan_data[chan_idx].dest_width,
+			imxdpu->chan_data[chan_idx].dest_height);
+
+
+		IMXDPUV1_PRINT(
+			"use_video_proc %d\n"
+			"use_eco_fetch  %d\n"
+			"interlaced     %d\n"
+			"phyaddr_0      0x%08x\n"
+			"u_offset       0x%08x\n"
+			"v_offset       0x%08x\n"
+			"rot_mode       %d\n"
+			"in_use         %d\n"
+			"use_global_alpha %d\n"
+			"use_local_alpha  %d\n",
+			imxdpu->chan_data[chan_idx].use_video_proc,
+			imxdpu->chan_data[chan_idx].use_eco_fetch,
+			imxdpu->chan_data[chan_idx].interlaced,
+			ptr_to_uint32(imxdpu->chan_data[chan_idx].phyaddr_0),
+			imxdpu->chan_data[chan_idx].u_offset,
+			imxdpu->chan_data[chan_idx].v_offset,
+			imxdpu->chan_data[chan_idx].rot_mode,
+			imxdpu->chan_data[chan_idx].in_use,
+			imxdpu->chan_data[chan_idx].use_global_alpha,
+			imxdpu->chan_data[chan_idx].use_local_alpha
+			);
+
+		imxdpuv1_dump_fetch_layer(&imxdpu->chan_data[chan_idx].fetch_layer_prop);
+	}
+	return ret;
+}
+
+/*!
+ * Shows the interrupt status registers
+ *
+ * @param   id of the diplay unit
+ *
+ */
+void imxdpuv1_dump_int_stat(int8_t imxdpuv1_id)
+{
+	int i;
+	struct imxdpuv1_soc *imxdpu;
+	uint32_t reg;
+
+	IMXDPUV1_TRACE("%s()\n", __func__);
+
+	if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) {
+		return;
+	}
+
+	imxdpu = &imxdpuv1_array[imxdpuv1_id];
+
+	for (i = 0; i < 3; i++) {
+		reg = imxdpuv1_read_irq(imxdpu,
+			IMXDPUV1_COMCTRL_USERINTERRUPTMASK0 +
+			(i * 4));
+		IMXDPUV1_PRINT("USERINTERRUPTMASK%d:   0x%08x\n", i, reg);
+	}
+	for (i = 0; i < 3; i++) {
+		reg = imxdpuv1_read_irq(imxdpu,
+			IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0 +
+			(i * 4));
+		IMXDPUV1_PRINT("USERINTERRUPTENABLE%d: 0x%08x\n", i, reg);
+	}
+	for (i = 0; i < 3; i++) {
+		reg = imxdpuv1_read_irq(imxdpu,
+			IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0 +
+			(i * 4));
+		IMXDPUV1_PRINT("USERINTERRUPTSTATUS%d: 0x%08x\n", i, reg);
+	}
+	for (i = 0; i < 3; i++) {
+		reg = imxdpuv1_read_irq(imxdpu,
+			IMXDPUV1_COMCTRL_INTERRUPTENABLE0 + (i * 4));
+		IMXDPUV1_PRINT("INTERRUPTENABLE%i:     0x%08x\n", i, reg);
+	}
+	for (i = 0; i < 3; i++) {
+		reg = imxdpuv1_read_irq(imxdpu,
+			IMXDPUV1_COMCTRL_INTERRUPTSTATUS0 + (i * 4));
+		IMXDPUV1_PRINT("INTERRUPTSTATUS%i:     0x%08x\n", i, reg);
+	}
+}
diff --git a/drivers/video/nxp/imx/imxdpuv1_be.h b/drivers/video/nxp/imx/imxdpuv1_be.h
new file mode 100644
index 00000000000..a004bf82447
--- /dev/null
+++ b/drivers/video/nxp/imx/imxdpuv1_be.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef IMXDPUV1_BE_H
+#define IMXDPUV1_BE_H
+
+struct fetch_unit {
+	uint32_t in_pipeline;
+	uint32_t control;
+	uint32_t burst_buf;
+	uint32_t buf_address;
+	uint32_t buf_attributes;
+	uint32_t buf_dimension;
+	uint32_t color_bits;
+	uint32_t color_shift;
+	uint32_t layer_offset;
+	uint32_t clip_offset;
+	uint32_t clip_dimension;
+	uint32_t const_color;
+	uint32_t layer_property;
+	uint32_t frame_dimension;
+	uint32_t frame_resample;
+};
+
+struct store_unit {
+	uint32_t in_pipeline;
+	uint32_t control;
+	uint32_t burst_buf;
+	uint32_t buf_address;
+	uint32_t buf_attributes;
+	uint32_t buf_dimension;
+	uint32_t frame_offset;
+	uint32_t color_bits;
+	uint32_t color_shift;
+};
+struct rop_unit {
+	uint32_t in_pipeline;
+	uint32_t control;
+};
+struct matrix_unit {
+	uint32_t in_pipeline;
+	uint32_t control;
+};
+struct hscaler_unit {
+	uint32_t in_pipeline;
+	uint32_t control;
+	uint32_t setup1;
+	uint32_t setup2;
+};
+struct vscaler_unit {
+	uint32_t in_pipeline;
+	uint32_t control;
+	uint32_t setup1;
+	uint32_t setup2;
+	uint32_t setup3;
+	uint32_t setup4;
+	uint32_t setup5;
+};
+struct blitblend_unit {
+	uint32_t in_pipeline;
+	uint32_t control;
+	uint32_t const_color;
+	uint32_t red_func;
+	uint32_t green_func;
+	uint32_t blue_func;
+	uint32_t alpha_func;
+	uint32_t blend_mode1;
+	uint32_t blend_mode2;
+};
+struct engcfg_unit {
+	uint32_t fetchpersp9_dynamic;
+	uint32_t fetchdecode9_dynamic;
+	uint32_t rop9_dynamic;
+	uint32_t matrix9_dynamic;
+	uint32_t hscaler9_dynamic;
+	uint32_t vscaler9_dynamic;
+	uint32_t blitblend9_dynamic;
+	uint32_t store9_dynamic;
+};
+
+struct be_blit_cfg {
+	struct fetch_unit fetch_decode;
+	struct fetch_unit fetch_persp;
+	struct fetch_unit fetch_eco;
+	struct store_unit store;
+	struct rop_unit rop;
+	struct matrix_unit matrix;
+	struct hscaler_unit hscaler;
+	struct vscaler_unit vscaler;
+	struct blitblend_unit blitblend;
+	struct engcfg_unit engcfg;
+};
+
+/* PRIVATE DATA */
+struct imxdpuv1_info {
+	/*reg */
+	void __iomem *base;
+};
+
+#define IMXDPUV1_IOC_MAGIC       'i'
+#define IMXDPUV1_IOC_BLIT       _IOW(IMXDPUV1_IOC_MAGIC, 1, struct be_blit_cfg)
+#define IMXDPUV1_IOC_WAIT       _IO(IMXDPUV1_IOC_MAGIC, 2)
+
+void imxdpuv1_be_irq_handler(int8_t imxdpuv1_id, int8_t irq);
+int imxdpuv1_be_init(int8_t imxdpuv1_id, void __iomem *imxdpuv1_base);
+int imxdpuv1_be_blit(struct imxdpuv1_info *imxdpu, struct be_blit_cfg *cfg);
+int imxdpuv1_be_wait_shadow_load(struct imxdpuv1_info *imxdpu);
+int imxdpuv1_be_wait_complete(struct imxdpuv1_info *imxdpu);
+int imxdpuv1_be_load(struct imxdpuv1_info *imxdpu, void __user *p);
+int imxdpuv1_be_wait(struct imxdpuv1_info *imxdpu);
+
+#endif
diff --git a/drivers/video/nxp/imx/imxdpuv1_private.h b/drivers/video/nxp/imx/imxdpuv1_private.h
new file mode 100644
index 00000000000..b874c38b47e
--- /dev/null
+++ b/drivers/video/nxp/imx/imxdpuv1_private.h
@@ -0,0 +1,470 @@
+/*
+ * Copyright (c) 2005-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Instance: imxdpuv1_private.h */
+#ifndef IMXDPUV1_PRIVATE_H
+#define IMXDPUV1_PRIVATE_H
+
+#include <asm/io.h>
+#include <asm/string.h>
+
+#include <linux/types.h>
+#include "imxdpuv1.h"
+
+typedef enum {
+	IMXDPUV1_BURST_UNKNOWN = 0,
+	IMXDPUV1_BURST_LEFT_RIGHT_DOWN,
+	IMXDPUV1_BURST_HORIZONTAL,
+	IMXDPUV1_BURST_VERTICAL,
+	IMXDPUV1_BURST_FREE,
+} imxdpuv1_burst_t;
+
+#define INTSTAT0_BIT(__bit__) (1U<<(__bit__))
+#define INTSTAT1_BIT(__bit__) (1U<<((__bit__)-32))
+#define INTSTAT2_BIT(__bit__) (1U<<((__bit__)-64))
+
+struct imxdpuv1_irq_node {
+	int(*handler) (int, void *);
+	const char *name;
+	void *data;
+	uint32_t  flags;
+};
+
+/* Generic definitions that are common to many registers */
+#define IMXDPUV1_COLOR_BITSALPHA0_MASK 0xFU
+#define IMXDPUV1_COLOR_BITSALPHA0_SHIFT 0U
+#define IMXDPUV1_COLOR_BITSBLUE0_MASK 0xF00U
+#define IMXDPUV1_COLOR_BITSBLUE0_SHIFT 8U
+#define IMXDPUV1_COLOR_BITSGREEN0_MASK 0xF0000U
+#define IMXDPUV1_COLOR_BITSGREEN0_SHIFT 16U
+#define IMXDPUV1_COLOR_BITSRED0_MASK 0xF000000U
+#define IMXDPUV1_COLOR_BITSRED0_SHIFT 24U
+
+#define IMXDPUV1_COLOR_SHIFTALPHA0_MASK 0x1FU
+#define IMXDPUV1_COLOR_SHIFTALPHA0_SHIFT 0U
+#define IMXDPUV1_COLOR_SHIFTBLUE0_MASK 0x1F00U
+#define IMXDPUV1_COLOR_SHIFTBLUE0_SHIFT 8U
+#define IMXDPUV1_COLOR_SHIFTGREEN0_MASK 0x1F0000U
+#define IMXDPUV1_COLOR_SHIFTGREEN0_SHIFT 16U
+#define IMXDPUV1_COLOR_SHIFTRED0_MASK 0x1F000000U
+#define IMXDPUV1_COLOR_SHIFTRED0_SHIFT 24U
+
+#define IMXDPUV1_COLOR_CONSTALPHA_MASK 0xFFU
+#define IMXDPUV1_COLOR_CONSTALPHA_SHIFT 0U
+#define IMXDPUV1_COLOR_CONSTBLUE_MASK 0xFF00U
+#define IMXDPUV1_COLOR_CONSTBLUE_SHIFT 8U
+#define IMXDPUV1_COLOR_CONSTGREEN_MASK 0xFF0000U
+#define IMXDPUV1_COLOR_CONSTGREEN_SHIFT 16U
+#define IMXDPUV1_COLOR_CONSTRED_MASK  0xFF000000U
+#define IMXDPUV1_COLOR_CONSTRED_SHIFT 24U
+
+/* these are common for fetch but not store */
+#define IMXDPUV1_BUFF_ATTR_STRIDE_MASK 0xFFFFU
+#define IMXDPUV1_BUFF_ATTR_STRIDE_SHIFT 0U
+#define IMXDPUV1_BUFF_ATTR_BITSPERPIXEL_MASK 0x3F0000U
+#define IMXDPUV1_BUFF_ATTR_BITSPERPIXEL_SHIFT 16U
+
+#define IMXDPUV1_BUFF_DIMEN_LINECOUNT_SHIFT 16U
+#define IMXDPUV1_BUFF_DIMEN_LINEWIDTH_MASK 0x3FFFU
+#define IMXDPUV1_BUFF_DIMEN_LINEWIDTH_SHIFT 0U
+#define IMXDPUV1_BUFF_DIMEN_LINECOUNT_MASK 0x3FFF0000U
+
+#define IMXDPUV1_LAYER_XOFFSET_MASK 0x7FFFU
+#define IMXDPUV1_LAYER_XOFFSET_SHIFT 0U
+#define IMXDPUV1_LAYER_XSBIT_MASK 0x4000U
+#define IMXDPUV1_LAYER_XSBIT_SHIFT 0U
+
+#define IMXDPUV1_LAYER_YOFFSET_MASK 0x7FFF0000U
+#define IMXDPUV1_LAYER_YOFFSET_SHIFT 16U
+#define IMXDPUV1_LAYER_YSBIT_MASK 0x4000U
+#define IMXDPUV1_LAYER_YSBIT_SHIFT 16U
+
+#define IMXDPUV1_CLIP_XOFFSET_MASK 0x7FFFU
+#define IMXDPUV1_CLIP_XOFFSET_SHIFT 0U
+#define IMXDPUV1_CLIP_YOFFSET_MASK 0x7FFF0000U
+#define IMXDPUV1_CLIP_YOFFSET_SHIFT 16U
+
+#define IMXDPUV1_CLIP_WIDTH_MASK 0x3FFFU
+#define IMXDPUV1_CLIP_WIDTH_SHIFT 0U
+#define IMXDPUV1_CLIP_HEIGHT_MASK 0x3FFF0000U
+#define IMXDPUV1_CLIP_HEIGHT_SHIFT 16U
+
+#define IMXDPUV1_FRAMEWIDTH_MASK 0x3FFFU
+#define IMXDPUV1_FRAMEWIDTH_SHIFT 0U
+#define IMXDPUV1_FRAMEHEIGHT_MASK 0x3FFF0000U
+#define IMXDPUV1_FRAMEHEIGHT_SHIFT 16U
+#define IMXDPUV1_EMPTYFRAME_MASK 0x80000000U
+#define IMXDPUV1_EMPTYFRAME_SHIFT 31U
+
+#define IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE 0U
+#define IMXDPUV1_PIXENGCFG_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_SRC_SEL_SHIFT 0U
+
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE 0U
+
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL_MASK 0x3F00U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL_SHIFT 8U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE 0U
+
+#define IMXDPUV1_PIXENGCFG_CLKEN_MASK 0x3000000U
+#define IMXDPUV1_PIXENGCFG_CLKEN_SHIFT 24U
+/* Field Value: _CLKEN__DISABLE, Clock for block is disabled  */
+#define IMXDPUV1_PIXENGCFG_CLKEN__DISABLE 0U
+/* Field Value: _CLKEN__AUTOMATIC, Clock is enabled if unit is used,
+ * frequency is defined by the register setting for this pipeline (see
+ * [endpoint_name]_Static register)  */
+#define IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC 0x1U
+/* Field Value: _CLKEN__FULL, Clock for block is without gating  */
+#define IMXDPUV1_PIXENGCFG_CLKEN__FULL 0x3U
+
+
+/* Register: IMXDPUV1_LayerProperty0 Common Bits */
+#define IMXDPUV1_LAYERPROPERTY_OFFSET          ((uint32_t)(0x40))
+#define IMXDPUV1_LAYERPROPERTY_RESET_VALUE     0x80000100U
+#define IMXDPUV1_LAYERPROPERTY_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_LAYERPROPERTY_PALETTEENABLE_MASK 0x1U
+#define IMXDPUV1_LAYERPROPERTY_PALETTEENABLE_SHIFT 0U
+#define IMXDPUV1_LAYERPROPERTY_TILEMODE_MASK  0x30U
+#define IMXDPUV1_LAYERPROPERTY_TILEMODE_SHIFT 4U
+/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_PAD 0x2U
+/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE_MASK 0x100U
+#define IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE_SHIFT 8U
+#define IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE_MASK 0x200U
+#define IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE_SHIFT 9U
+#define IMXDPUV1_LAYERPROPERTY_ALPHAMASKENABLE_MASK 0x400U
+#define IMXDPUV1_LAYERPROPERTY_ALPHAMASKENABLE_SHIFT 10U
+#define IMXDPUV1_LAYERPROPERTY_ALPHATRANSENABLE_MASK 0x800U
+#define IMXDPUV1_LAYERPROPERTY_ALPHATRANSENABLE_SHIFT 11U
+#define IMXDPUV1_LAYERPROPERTY_RGBALPHASRCENABLE_MASK 0x1000U
+#define IMXDPUV1_LAYERPROPERTY_RGBALPHASRCENABLE_SHIFT 12U
+#define IMXDPUV1_LAYERPROPERTY_RGBALPHACONSTENABLE_MASK 0x2000U
+#define IMXDPUV1_LAYERPROPERTY_RGBALPHACONSTENABLE_SHIFT 13U
+#define IMXDPUV1_LAYERPROPERTY_RGBALPHAMASKENABLE_MASK 0x4000U
+#define IMXDPUV1_LAYERPROPERTY_RGBALPHAMASKENABLE_SHIFT 14U
+#define IMXDPUV1_LAYERPROPERTY_RGBALPHATRANSENABLE_MASK 0x8000U
+#define IMXDPUV1_LAYERPROPERTY_RGBALPHATRANSENABLE_SHIFT 15U
+#define IMXDPUV1_LAYERPROPERTY_PREMULCONSTRGB_MASK 0x10000U
+#define IMXDPUV1_LAYERPROPERTY_PREMULCONSTRGB_SHIFT 16U
+#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE_MASK 0x60000U
+#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion.  */
+#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__OFF 0U
+/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__ITU709 0x3U
+#define IMXDPUV1_LAYERPROPERTY_GAMMAREMOVEENABLE_MASK 0x100000U
+#define IMXDPUV1_LAYERPROPERTY_GAMMAREMOVEENABLE_SHIFT 20U
+#define IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE_MASK 0x40000000U
+#define IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE_SHIFT 30U
+#define IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE_MASK 0x80000000U
+#define IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE_SHIFT 31U
+
+typedef struct {
+	/* Source buffer base address of layer 0. */
+	uint32_t baseaddress0;
+	/* Source buffer attributes for layer 0. */
+	uint32_t sourcebufferattributes0;
+	/* Source buffer dimension of layer 0. */
+	uint32_t sourcebufferdimension0;
+	/* Size of color components for RGB, YUV and index formats (layer 0). */
+	uint32_t colorcomponentbits0;
+	/* Bit position of color components for RGB, YUV and index
+	   formats (layer 0). */
+	uint32_t colorcomponentshift0;
+	/* Position of layer 0 within the destination frame. */
+	uint32_t layeroffset0;
+	/* Clip window position for layer 0. */
+	uint32_t clipwindowoffset0;
+	/* Clip window size for layer 0. */
+	uint32_t clipwindowdimensions0;
+	/* Constant color for layer 0. */
+	uint32_t constantcolor0;
+	/* Common properties of layer 0. */
+	uint32_t layerproperty0;
+} fetch_layer_setup_t;
+
+typedef struct {
+	/* Destination buffer base address of layer 0. */
+	uint32_t baseaddress0;
+	/* Destination buffer attributes for layer 0. */
+	uint32_t destbufferattributes0;
+	/* Source buffer dimension of layer 0. */
+	uint32_t destbufferdimension0;
+	/* Frame offset of layer 0. */
+	uint32_t frameoffset0;
+	/* Size of color components for RGB, YUV and index formats (layer 0). */
+	uint32_t colorcomponentbits0;
+	/* Bit position of color components for RGB, YUV and index
+	   formats (layer 0). */
+	uint32_t colorcomponentshift0;
+} store_layer_setup_t;
+
+typedef enum {
+	IMXDPUV1_SHDLD_IDX_DISP0   =  (0),
+	IMXDPUV1_SHDLD_IDX_DISP1   =  (1),
+	IMXDPUV1_SHDLD_IDX_CONST0  =  (2), /* IMXDPUV1_ID_CONSTFRAME0 */
+	IMXDPUV1_SHDLD_IDX_CONST1  =  (3), /* IMXDPUV1_ID_CONSTFRAME1 */
+	IMXDPUV1_SHDLD_IDX_CHAN_00 =  (4), /* IMXDPUV1_ID_FETCHDECODE2 */
+	IMXDPUV1_SHDLD_IDX_CHAN_01 =  (5), /* IMXDPUV1_ID_FETCHDECODE0 */
+	IMXDPUV1_SHDLD_IDX_CHAN_02 =  (6), /* IMXDPUV1_ID_FETCHLAYER0 */
+	IMXDPUV1_SHDLD_IDX_CHAN_03 =  (7), /* IMXDPUV1_ID_FETCHLAYER0 */
+	IMXDPUV1_SHDLD_IDX_CHAN_04 =  (8), /* IMXDPUV1_ID_FETCHLAYER0 */
+	IMXDPUV1_SHDLD_IDX_CHAN_05 =  (9), /* IMXDPUV1_ID_FETCHLAYER0 */
+	IMXDPUV1_SHDLD_IDX_CHAN_06 = (10), /* IMXDPUV1_ID_FETCHLAYER0 */
+	IMXDPUV1_SHDLD_IDX_CHAN_07 = (11), /* IMXDPUV1_ID_FETCHLAYER0 */
+	IMXDPUV1_SHDLD_IDX_CHAN_08 = (12), /* IMXDPUV1_ID_FETCHLAYER0 */
+	IMXDPUV1_SHDLD_IDX_CHAN_09 = (13), /* IMXDPUV1_ID_FETCHLAYER0 */
+	IMXDPUV1_SHDLD_IDX_CHAN_10 = (14), /* IMXDPUV1_ID_FETCHWARP2 */
+	IMXDPUV1_SHDLD_IDX_CHAN_11 = (15), /* IMXDPUV1_ID_FETCHWARP2 */
+	IMXDPUV1_SHDLD_IDX_CHAN_12 = (16), /* IMXDPUV1_ID_FETCHWARP2 */
+	IMXDPUV1_SHDLD_IDX_CHAN_13 = (17), /* IMXDPUV1_ID_FETCHWARP2 */
+	IMXDPUV1_SHDLD_IDX_CHAN_14 = (18), /* IMXDPUV1_ID_FETCHWARP2 */
+	IMXDPUV1_SHDLD_IDX_CHAN_15 = (19), /* IMXDPUV1_ID_FETCHWARP2 */
+	IMXDPUV1_SHDLD_IDX_CHAN_16 = (20), /* IMXDPUV1_ID_FETCHWARP2 */
+	IMXDPUV1_SHDLD_IDX_CHAN_17 = (21), /* IMXDPUV1_ID_FETCHWARP2 */
+	IMXDPUV1_SHDLD_IDX_CHAN_18 = (22), /* IMXDPUV1_ID_FETCHDECODE3 */
+	IMXDPUV1_SHDLD_IDX_CHAN_19 = (23), /* IMXDPUV1_ID_FETCHDECODE1 */
+	IMXDPUV1_SHDLD_IDX_CHAN_20 = (24), /* IMXDPUV1_ID_FETCHLAYER1*/
+	IMXDPUV1_SHDLD_IDX_CHAN_21 = (25), /* IMXDPUV1_ID_FETCHLAYER1*/
+	IMXDPUV1_SHDLD_IDX_CHAN_22 = (26), /* IMXDPUV1_ID_FETCHLAYER1*/
+	IMXDPUV1_SHDLD_IDX_CHAN_23 = (27), /* IMXDPUV1_ID_FETCHLAYER1*/
+	IMXDPUV1_SHDLD_IDX_CHAN_24 = (28), /* IMXDPUV1_ID_FETCHLAYER1*/
+	IMXDPUV1_SHDLD_IDX_CHAN_25 = (29), /* IMXDPUV1_ID_FETCHLAYER1*/
+	IMXDPUV1_SHDLD_IDX_CHAN_26 = (30), /* IMXDPUV1_ID_FETCHLAYER1*/
+	IMXDPUV1_SHDLD_IDX_CHAN_27 = (31), /* IMXDPUV1_ID_FETCHLAYER1*/
+	IMXDPUV1_SHDLD_IDX_CHAN_28 = (32), /* IMXDPUV1_ID_FETCHECO0*/
+	IMXDPUV1_SHDLD_IDX_CHAN_29 = (33), /* IMXDPUV1_ID_FETCHECO1*/
+	IMXDPUV1_SHDLD_IDX_CHAN_30 = (34), /* IMXDPUV1_ID_FETCHECO2*/
+	IMXDPUV1_SHDLD_IDX_MAX     = (35),
+} imxdpuv1_shadow_load_index_t;
+
+typedef struct {
+	bool prim_sync_state;
+	bool sec_sync_state;
+	uint32_t prim_sync_count;
+	uint32_t sec_sync_count;
+	uint32_t skew_error_count;
+	uint32_t prim_fifo_empty_count;
+	uint32_t sec_fifo_empty_count;
+	uint32_t frame_count;
+} frame_gen_stats_t;
+
+/*!
+ * Definition of IMXDPU channel structure
+ */
+typedef struct {
+	int8_t disp_id;	/* Iris instance id of "owner" */
+
+	imxdpuv1_chan_t chan;
+	uint32_t src_pixel_fmt;
+	int16_t src_top;
+	int16_t src_left;
+	uint16_t src_width;
+	uint16_t src_height;
+	int16_t clip_top;
+	int16_t clip_left;
+	uint16_t clip_width;
+	uint16_t clip_height;
+	uint16_t stride;
+	uint32_t dest_pixel_fmt;
+	int16_t dest_top;
+	int16_t dest_left;
+	uint16_t dest_width;
+	uint16_t dest_height;
+	uint16_t const_color;
+
+	uint32_t h_scale_factor;	/* downscaling  out/in */
+	uint32_t h_phase;
+	uint32_t v_scale_factor;	/* downscaling  out/in */
+	uint32_t v_phase[2][2];
+
+	bool use_video_proc;
+	bool interlaced;
+	bool use_eco_fetch;
+	bool use_global_alpha;
+	bool use_local_alpha;
+
+	/* note: dma_addr_t changes for 64-bit arch */
+	dma_addr_t phyaddr_0;
+
+	uint32_t u_offset;
+	uint32_t v_offset;
+
+	uint8_t blend_layer;
+	uint8_t destination_stream;
+	uint8_t source_id;
+
+	imxdpuv1_rotate_mode_t rot_mode;
+
+	/* todo add features sub-windows, upscaling, warping */
+	fetch_layer_setup_t fetch_layer_prop;
+	store_layer_setup_t store_layer_prop;
+
+	bool in_use;
+
+	/* todo: add channel features */
+} chan_private_t;
+
+typedef union {
+	struct {
+		uint8_t request;
+		uint8_t processing;
+		uint8_t complete;
+		uint8_t trys;
+	} state;
+	uint32_t word;
+} imxdpuv1_shadow_state_t;
+
+/* PRIVATE DATA */
+struct imxdpuv1_soc {
+	int8_t devtype;
+	int8_t online;
+	uint32_t enabled_int[3];
+	struct imxdpuv1_irq_node irq_list[IMXDPUV1_INTERRUPT_MAX];
+
+	struct device *dev;
+	struct imxdpuv1_videomode video_mode[IMXDPUV1_NUM_DI];
+	struct imxdpuv1_videomode capture_mode[IMXDPUV1_NUM_CI];
+	frame_gen_stats_t fgen_stats[IMXDPUV1_NUM_DI];
+	uint32_t irq_count;
+
+
+	/*
+	 * Bypass reset to avoid display channel being
+	 * stopped by probe since it may starts to work
+	 * in bootloader.
+	 */
+	int8_t bypass_reset;
+
+	/* todo: need to decide where the locking is implemented */
+
+	/*clk*/
+
+	/*irq*/
+
+	/*reg*/
+	void __iomem           *base;
+
+	/*use count*/
+	imxdpuv1_layer_t blend_layer[IMXDPUV1_LAYER_MAX];
+	chan_private_t chan_data[IMXDPUV1_CHAN_IDX_MAX];
+
+	uint8_t	shadow_load_pending[IMXDPUV1_NUM_DI][IMXDPUV1_SHDLD_IDX_MAX];
+	imxdpuv1_shadow_state_t shadow_load_state[IMXDPUV1_NUM_DI][IMXDPUV1_SHDLD_IDX_MAX];
+};
+
+
+
+/* PRIVATE FUNCTIONS */
+#ifdef ENABLE_IMXDPUV1_TRACE_REG
+uint32_t _imxdpuv1_read(struct imxdpuv1_soc *dpu, u32 offset, char *file, int line);
+#define imxdpuv1_read(_inst_, _offset_) _imxdpuv1_read(_inst_, _offset_, __FILE__, __LINE__)
+#else
+static inline uint32_t imxdpuv1_read(struct imxdpuv1_soc *dpu, uint32_t offset)
+{
+	return __raw_readl(dpu->base + offset);
+}
+#endif
+
+#ifdef ENABLE_IMXDPUV1_TRACE_IRQ_READ
+uint32_t _imxdpuv1_read_irq(struct imxdpuv1_soc *dpu, u32 offset, char *file, int line);
+#define imxdpuv1_read_irq(_inst_, _offset_) _imxdpuv1_read_irq(_inst_, _offset_, __FILE__, __LINE__)
+#else
+static inline uint32_t imxdpuv1_read_irq(struct imxdpuv1_soc *dpu, uint32_t offset)
+{
+	return __raw_readl(dpu->base + offset);
+}
+#endif
+
+#ifdef ENABLE_IMXDPUV1_TRACE_REG
+void _imxdpuv1_write(struct imxdpuv1_soc *dpu, uint32_t value, uint32_t offset, char *file, int line);
+#define imxdpuv1_write(_inst_, _value_, _offset_) _imxdpuv1_write(_inst_, _value_, _offset_, __FILE__, __LINE__)
+#else
+static inline void imxdpuv1_write(struct imxdpuv1_soc *dpu, uint32_t offset, uint32_t value)
+{
+	__raw_writel(value, dpu->base + offset);
+}
+#endif
+
+#ifdef ENABLE_IMXDPUV1_TRACE_IRQ_WRITE
+void _imxdpuv1_write_irq(struct imxdpuv1_soc *dpu, uint32_t value, uint32_t offset, char *file, int line);
+#define imxdpuv1_write_irq(_inst_, _value_, _offset_) _imxdpuv1_write_irq(_inst_, _value_, _offset_, __FILE__, __LINE__)
+#else
+static inline void imxdpuv1_write_irq(struct imxdpuv1_soc *dpu, uint32_t offset, uint32_t value)
+{
+	__raw_writel(value, dpu->base + offset);
+}
+#endif
+
+void _imxdpuv1_write_block(struct imxdpuv1_soc *imxdpu, uint32_t offset, void *values, uint32_t cnt, char *file, int line);
+#define imxdpuv1_write_block(_inst_, _values_, _offset_, _cnt_) _imxdpuv1_write_block(_inst_, _values_, _offset_, _cnt_, __FILE__, __LINE__)
+
+/* mapping of RGB, Tcon, or static values to output */
+#define IMXDPUV1_TCON_MAPBIT__RGB(_x_)   ((_x_))
+#define IMXDPUV1_TCON_MAPBIT__Tsig(_x_)  ((_x_) + 30)
+#define IMXDPUV1_TCON_MAPBIT__HIGH 42U
+#define IMXDPUV1_TCON_MAPBIT__LOW  43U
+
+/* these match the bit definitions for the shadlow load
+   request registers
+ */
+typedef enum {
+	IMXDPUV1_SHLDREQID_FETCHDECODE9 = 0,
+	IMXDPUV1_SHLDREQID_FETCHPERSP9,
+	IMXDPUV1_SHLDREQID_FETCHECO9,
+	IMXDPUV1_SHLDREQID_CONSTFRAME0,
+	IMXDPUV1_SHLDREQID_CONSTFRAME4,
+	IMXDPUV1_SHLDREQID_CONSTFRAME1,
+	IMXDPUV1_SHLDREQID_CONSTFRAME5,
+#ifdef IMXDPUV1_VERSION_0
+	IMXDPUV1_SHLDREQID_EXTSRC4,
+	IMXDPUV1_SHLDREQID_EXTSRC5,
+	IMXDPUV1_SHLDREQID_FETCHDECODE2,
+	IMXDPUV1_SHLDREQID_FETCHDECODE3,
+#endif
+	IMXDPUV1_SHLDREQID_FETCHWARP2,
+	IMXDPUV1_SHLDREQID_FETCHECO2,
+	IMXDPUV1_SHLDREQID_FETCHDECODE0,
+	IMXDPUV1_SHLDREQID_FETCHECO0,
+	IMXDPUV1_SHLDREQID_FETCHDECODE1,
+	IMXDPUV1_SHLDREQID_FETCHECO1,
+	IMXDPUV1_SHLDREQID_FETCHLAYER0,
+#ifdef IMXDPUV1_VERSION_0
+	IMXDPUV1_SHLDREQID_FETCHLAYER1,
+	IMXDPUV1_SHLDREQID_EXTSRC0,
+	IMXDPUV1_SHLDREQID_EXTSRC1
+#endif
+} imxdpuv1_shadow_load_req_t;
+
+#define IMXDPUV1_PIXENGCFG_DIVIDER_RESET 0x80
+
+#endif /* IMXDPUV1_PRIVATE_H */
+
diff --git a/drivers/video/imx/ipu.h b/drivers/video/nxp/imx/ipu.h
index 1e02c7ab6d5..1e02c7ab6d5 100644
--- a/drivers/video/imx/ipu.h
+++ b/drivers/video/nxp/imx/ipu.h
diff --git a/drivers/video/imx/ipu_common.c b/drivers/video/nxp/imx/ipu_common.c
index 54d1efc8f5f..54d1efc8f5f 100644
--- a/drivers/video/imx/ipu_common.c
+++ b/drivers/video/nxp/imx/ipu_common.c
diff --git a/drivers/video/imx/ipu_disp.c b/drivers/video/nxp/imx/ipu_disp.c
index 144322e4e26..e1ab05535e3 100644
--- a/drivers/video/imx/ipu_disp.c
+++ b/drivers/video/nxp/imx/ipu_disp.c
@@ -890,6 +890,11 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,
 			clk_set_parent(g_pixel_clk[disp], g_ipu_clk);
 	}
 	rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk);
+	if (rounded_pixel_clk == 0) {
+		debug("IPU_DISP:  get round rate error\n");
+		return -EINVAL;
+	}
+
 	clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk);
 	udelay(5000);
 	/* Get integer portion of divider */
diff --git a/drivers/video/imx/ipu_regs.h b/drivers/video/nxp/imx/ipu_regs.h
index deb44002d75..deb44002d75 100644
--- a/drivers/video/imx/ipu_regs.h
+++ b/drivers/video/nxp/imx/ipu_regs.h
diff --git a/drivers/video/nxp/imx/lcdifv3-regs.h b/drivers/video/nxp/imx/lcdifv3-regs.h
new file mode 100644
index 00000000000..b902e03644d
--- /dev/null
+++ b/drivers/video/nxp/imx/lcdifv3-regs.h
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __LCDIFV3_REGS_H
+#define __LCDIFV3_REGS_H
+
+/* regs offset */
+#define LCDIFV3_CTRL			0x00
+#define LCDIFV3_CTRL_SET		0x04
+#define LCDIFV3_CTRL_CLR		0x08
+#define LCDIFV3_CTRL_TOG		0x0c
+#define LCDIFV3_DISP_PARA		0x10
+#define LCDIFV3_DISP_SIZE		0x14
+#define LCDIFV3_HSYN_PARA		0x18
+#define LCDIFV3_VSYN_PARA		0x1c
+#define LCDIFV3_VSYN_HSYN_WIDTH		0x20
+#define LCDIFV3_INT_STATUS_D0		0x24
+#define LCDIFV3_INT_ENABLE_D0		0x28
+#define LCDIFV3_INT_STATUS_D1		0x30
+#define LCDIFV3_INT_ENABLE_D1		0x34
+
+#define LCDIFV3_CTRLDESCL0_1		0x200
+#define LCDIFV3_CTRLDESCL0_3		0x208
+#define LCDIFV3_CTRLDESCL_LOW0_4	0x20c
+#define LCDIFV3_CTRLDESCL_HIGH0_4	0x210
+#define LCDIFV3_CTRLDESCL0_5		0x214
+#define LCDIFV3_CSC0_CTRL		0x21c
+#define LCDIFV3_CSC0_COEF0		0x220
+#define LCDIFV3_CSC0_COEF1		0x224
+#define LCDIFV3_CSC0_COEF2		0x228
+#define LCDIFV3_CSC0_COEF3		0x22c
+#define LCDIFV3_CSC0_COEF4		0x230
+#define LCDIFV3_CSC0_COEF5		0x234
+#define LCDIFV3_PANIC0_THRES		0x238
+
+/* reg bit manipulation */
+#define REG_MASK(e, s) (((1 << ((e) - (s) + 1)) - 1) << (s))
+#define REG_PUT(x, e, s) (((x) << (s)) & REG_MASK(e, s))
+#define REG_GET(x, e, s) (((x) & REG_MASK(e, s)) >> (s))
+
+/* regs bit fields */
+#define CTRL_SW_RESET			BIT(31)
+#define CTRL_FETCH_START_OPTION(x)	REG_PUT((x), 9, 8)
+   #define FPV		0
+   #define PWV		1
+   #define BPV		2
+   #define RESV		3
+#define CTRL_NEG			BIT(4)
+#define CTRL_INV_PXCK			BIT(3)
+#define CTRL_INV_DE			BIT(2)
+#define CTRL_INV_VS			BIT(1)
+#define CTRL_INV_HS			BIT(0)
+
+#define DISP_PARA_DISP_ON		BIT(31)
+#define DISP_PARA_SWAP_EN		BIT(30)
+#define DISP_PARA_LINE_PATTERN(x)	REG_PUT((x), 29, 26)
+   /* line pattern formats (output) */
+   #define LP_RGB888_OR_YUV444		0x0
+   #define LP_RBG888			0x1
+   #define LP_GBR888			0x2
+   #define LP_GRB888_OR_UYV444		0x3
+   #define LP_BRG888			0x4
+   #define LP_BGR888			0x5
+   #define LP_RGB555			0x6
+   #define LP_RGB565			0x7
+   #define LP_YUYV_16_0			0x8
+   #define LP_UYVY_16_0			0x9
+   #define LP_YVYU_16_0			0xa
+   #define LP_VYUY_16_0			0xb
+   #define LP_YUYV_23_8			0xc
+   #define LP_UYVY_23_8			0xd
+   #define LP_YVYU_23_8			0xe
+   #define LP_VYUY_23_8			0xf
+
+#define DISP_PARA_DISP_MODE(x)		REG_PUT((x), 25, 24)
+#define DISP_PARA_BGND_R(x)		REG_PUT((x), 23, 16)
+#define DISP_PARA_BGND_G(x)		REG_PUT((x), 15,  8)
+#define DISP_PARA_BGND_B(x)		REG_PUT((x),  7,  0)
+
+#define DISP_SIZE_DELTA_Y(x)		REG_PUT((x), 31, 16)
+#define DISP_SIZE_DELTA_X(x)		REG_PUT((x), 15,  0)
+
+#define HSYN_PARA_BP_H(x)		REG_PUT((x), 31, 16)
+#define HSYN_PARA_FP_H(x)		REG_PUT((x), 15,  0)
+
+#define VSYN_PARA_BP_V(x)		REG_PUT((x), 31, 16)
+#define VSYN_PARA_FP_V(x)		REG_PUT((x), 15,  0)
+
+#define VSYN_HSYN_WIDTH_PW_V(x)		REG_PUT((x), 31, 16)
+#define VSYN_HSYN_WIDTH_PW_H(x)		REG_PUT((x), 15,  0)
+
+#define INT_STATUS_D0_FIFO_EMPTY	BIT(24)
+#define INT_STATUS_D0_DMA_DONE		BIT(16)
+#define INT_STATUS_D0_DMA_ERR		BIT(8)
+#define INT_STATUS_D0_VS_BLANK		BIT(2)
+#define INT_STATUS_D0_UNDERRUN		BIT(1)
+#define INT_STATUS_D0_VSYNC		BIT(0)
+
+#define INT_ENABLE_D0_FIFO_EMPTY_EN	BIT(24)
+#define INT_ENABLE_D0_DMA_DONE_EN	BIT(16)
+#define INT_ENABLE_D0_DMA_ERR_EN	BIT(8)
+#define INT_ENABLE_D0_VS_BLANK_EN	BIT(2)
+#define INT_ENABLE_D0_UNDERRUN_EN	BIT(1)
+#define INT_ENABLE_D0_VSYNC_EN		BIT(0)
+
+#define INT_STATUS_D1_PLANE_PANIC	BIT(0)
+#define INT_ENABLE_D1_PLANE_PANIC_EN	BIT(0)
+
+#define CTRLDESCL0_1_HEIGHT(x)		REG_PUT((x), 31, 16)
+#define CTRLDESCL0_1_WIDTH(x)		REG_PUT((x), 15,  0)
+#define CTRLDESCL0_3_STATE_CLEAR_VSYNC	BIT(23)
+#define CTRLDESCL0_3_P_SIZE(x)		REG_PUT((x), 22, 20)
+#define CTRLDESCL0_3_T_SIZE(x)		REG_PUT((x), 17, 16)
+#define CTRLDESCL0_3_PITCH(x)		REG_PUT((x), 15,  0)
+//#define CTRLDESCL_LOW0_4_ADDR_LOW(x)	REG_PUT((x), 31,  0)
+#define CTRLDESCL_HIGH0_4_ADDR_HIGH(x)	REG_PUT((x),  3,  0)
+#define CTRLDESCL0_5_EN			BIT(31)	/* enable layer for DMA */
+#define CTRLDESCL0_5_SHADOW_LOAD_EN	BIT(30)
+#define CTRLDESCL0_5_BPP(x)		REG_PUT((x), 27, 24)
+   /* layer encoding formats (input) */
+   #define BPP16_RGB565			0x4
+   #define BPP16_ARGB1555		0x5
+   #define BPP16_ARGB4444		0x6
+   #define BPP16_YCbCr422		0x7
+   #define BPP24_RGB888			0x8
+   #define BPP32_ARGB8888		0x9
+   #define BPP32_ABGR8888		0xa
+#define CTRLDESCL0_5_YUV_FORMAT(x)	REG_PUT((x), 15, 14)
+
+#define CSC0_CTRL_CSC_MODE(x)		REG_PUT((x),  2,  1)
+#define CSC0_CTRL_BYPASS		BIT(0)
+#define CSC0_COEF0_A2(x)		REG_PUT((x), 26, 16)
+#define CSC0_COEF0_A1(x)		REG_PUT((x), 10,  0)
+#define CSC0_COEF1_B1(x)		REG_PUT((x), 26, 16)
+#define CSC0_COEF1_A3(x)		REG_PUT((x), 10,  0)
+#define CSC0_COEF2_B3(x)		REG_PUT((x), 26, 16)
+#define CSC0_COEF2_B2(x)		REG_PUT((x), 10,  0)
+#define CSC0_COEF3_C2(x)		REG_PUT((x), 26, 16)
+#define CSC0_COEF3_C1(x)		REG_PUT((x), 10,  0)
+#define CSC0_COEF4_D1(x)		REG_PUT((x), 24, 16)
+#define CSC0_COEF4_C3(x)		REG_PUT((x), 10,  0)
+#define CSC0_COEF5_D3(x)		REG_PUT((x), 24, 16)
+#define CSC0_COEF5_D2(x)		REG_PUT((x),  8,  0)
+
+#define PANIC0_THRES_PANIC_THRES_LOW(x)	REG_PUT((x), 24, 16)
+#define PANIC0_THRES_PANIC_THRES_HIGH(x)	REG_PUT((x), 8, 0)
+
+#endif /* __LCDIFV3_REGS_H */
diff --git a/drivers/video/nxp/imx/mipi_dsi_northwest.c b/drivers/video/nxp/imx/mipi_dsi_northwest.c
new file mode 100644
index 00000000000..0445ba6d8ad
--- /dev/null
+++ b/drivers/video/nxp/imx/mipi_dsi_northwest.c
@@ -0,0 +1,1064 @@
+/*
+ * Copyright 2016-2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <malloc.h>
+#include <dm.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/err.h>
+#include <linux/bug.h>
+#include <asm/io.h>
+#include <linux/string.h>
+
+#include "mipi_dsi_northwest_regs.h"
+#include <video_bridge.h>
+#include <panel.h>
+#include <dsi_host.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+#include <dm/device-internal.h>
+#include <dm/device_compat.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+
+#define MIPI_LCD_SLEEP_MODE_DELAY	(120)
+#define MIPI_FIFO_TIMEOUT		500000 /* 500ms */
+#define	PS2KHZ(ps)	(1000000000UL / (ps))
+
+#define DIV_ROUND_CLOSEST_ULL(x, divisor)(		\
+{							\
+	typeof(divisor) __d = divisor;			\
+	unsigned long long _tmp = (x) + (__d) / 2;	\
+	do_div(_tmp, __d);				\
+	_tmp;						\
+}							\
+)
+
+enum mipi_dsi_mode {
+	DSI_COMMAND_MODE,
+	DSI_VIDEO_MODE
+};
+
+#define DSI_LP_MODE	0
+#define DSI_HS_MODE	1
+
+enum mipi_dsi_payload {
+	DSI_PAYLOAD_CMD,
+	DSI_PAYLOAD_VIDEO,
+};
+
+struct nwl_dsi_sim_ops {
+	int (*mipi_reset)(struct regmap *sim, bool reset);
+	int (*dpi_reset)(struct regmap *sim, bool reset);
+	int (*cm_set)(struct regmap *sim, bool normal);
+	int (*shutdown)(struct regmap *sim, bool sd);
+	int (*pll_en)(struct regmap *sim, bool enable);
+	int (*isolate)(struct regmap *sim, bool enable);
+};
+
+/*
+ * mipi-dsi northwest driver information structure, holds useful data for the driver.
+ */
+struct mipi_dsi_northwest_info {
+	void __iomem *mmio_base;
+	struct mipi_dsi_device *device;
+	struct mipi_dsi_host dsi_host;
+	struct display_timing timings;
+	struct regmap *sim;
+	struct nwl_dsi_sim_ops *sim_ops;
+
+	 uint32_t max_data_lanes;
+	 uint32_t max_data_rate;
+	 uint32_t pll_ref;
+};
+
+struct pll_divider {
+	unsigned int cm;  /* multiplier */
+	unsigned int cn;  /* predivider */
+	unsigned int co;  /* outdivider */
+};
+
+/**
+ * 'CM' value to 'CM' reigister config value map
+ * 'CM' = [16, 255];
+ */
+static unsigned int cm_map_table[240] = {
+	0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,	/* 16 ~ 23 */
+	0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff,	/* 24 ~ 31 */
+
+	0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,	/* 32 ~ 39 */
+	0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, /* 40 ~ 47 */
+
+	0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, /* 48 ~ 55 */
+	0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, /* 56 ~ 63 */
+
+	0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, /* 64 ~ 71 */
+	0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, /* 72 ~ 79 */
+
+	0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, /* 80 ~ 87 */
+	0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, /* 88 ~ 95 */
+
+	0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, /* 96  ~ 103 */
+	0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, /* 104 ~ 111 */
+
+	0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, /* 112 ~ 119 */
+	0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, /* 120 ~ 127 */
+
+	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* 128 ~ 135 */
+	0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, /* 136 ~ 143 */
+
+	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* 144 ~ 151 */
+	0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 152 ~ 159 */
+
+	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, /* 160 ~ 167 */
+	0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, /* 168 ~ 175 */
+
+	0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, /* 176 ~ 183 */
+	0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, /* 184 ~ 191 */
+
+	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, /* 192 ~ 199 */
+	0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, /* 200 ~ 207 */
+
+	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, /* 208 ~ 215 */
+	0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, /* 216 ~ 223 */
+
+	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, /* 224 ~ 231 */
+	0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, /* 232 ~ 239 */
+
+	0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, /* 240 ~ 247 */
+	0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f	/* 248 ~ 255 */
+};
+
+/**
+ * map 'CN' value to 'CN' reigister config value
+ * 'CN' = [1, 32];
+ */
+static unsigned int cn_map_table[32] = {
+	0x1f, 0x00, 0x10, 0x18, 0x1c, 0x0e, 0x07, 0x13,	/* 1  ~ 8  */
+	0x09, 0x04, 0x02, 0x11, 0x08, 0x14, 0x0a, 0x15,	/* 9  ~ 16 */
+	0x1a, 0x1d, 0x1e, 0x0f, 0x17, 0x1b, 0x0d, 0x16,	/* 17 ~ 24 */
+	0x0b, 0x05, 0x12, 0x19, 0x0c, 0x06, 0x03, 0x01	/* 25 ~ 32 */
+};
+
+/**
+ * map 'CO' value to 'CO' reigister config value
+ * 'CO' = { 1, 2, 4, 8 };
+ */
+static unsigned int co_map_table[4] = {
+	0x0, 0x1, 0x2, 0x3
+};
+
+unsigned long gcd(unsigned long a, unsigned long b)
+{
+	unsigned long r = a | b;
+
+	if (!a || !b)
+		return r;
+
+	/* Isolate lsbit of r */
+	r &= -r;
+
+	while (!(b & r))
+		b >>= 1;
+	if (b == r)
+		return r;
+
+	for (;;) {
+		while (!(a & r))
+			a >>= 1;
+		if (a == r)
+			return r;
+		if (a == b)
+			return a;
+
+		if (a < b)
+			swap(a, b);
+		a -= b;
+		a >>= 1;
+		if (a & r)
+			a += b;
+		a >>= 1;
+	}
+}
+
+static void mipi_dsi_set_mode(struct mipi_dsi_northwest_info *mipi_dsi,
+			      uint8_t mode);
+static int mipi_dsi_dcs_cmd(struct mipi_dsi_northwest_info *mipi_dsi,
+			    u8 cmd, const u32 *param, int num);
+
+static void mipi_dsi_set_mode(struct mipi_dsi_northwest_info *mipi_dsi,
+			      uint8_t mode)
+{
+	switch (mode) {
+	case DSI_LP_MODE:
+		writel(0x1, mipi_dsi->mmio_base + HOST_CFG_NONCONTINUOUS_CLK);
+		break;
+	case DSI_HS_MODE:
+		writel(0x0, mipi_dsi->mmio_base + HOST_CFG_NONCONTINUOUS_CLK);
+		break;
+	default:
+		printf("invalid dsi mode\n");
+		return;
+	}
+
+	mdelay(1);
+}
+
+static int mipi_dsi_dphy_init(struct mipi_dsi_northwest_info *mipi_dsi)
+{
+	uint32_t time_out = 100;
+	uint32_t lock;
+	uint32_t req_bit_clk;
+	uint32_t bpp;
+
+	int i, best_div = -1;
+	int64_t delta;
+	uint64_t least_delta = ~0U;
+	uint64_t limit, div_result;
+	uint64_t denominator, numerator, divisor;
+	uint64_t norm_denom, norm_num, split_denom;
+	struct pll_divider div = { 0 };
+
+	if (mipi_dsi->sim_ops->isolate)
+		mipi_dsi->sim_ops->isolate(mipi_dsi->sim, false);
+
+	bpp = mipi_dsi_pixel_format_to_bpp(mipi_dsi->device->format);
+
+	/* req_bit_clk is PLL out, clk_byte is 1/8th of the req_bit_clk
+	*  We need meet clk_byte_freq >= dpi_pclk_freq * DPI_pixel_size / ( 8 * (cfg_num_lanes + 1))
+	*/
+
+	req_bit_clk = mipi_dsi->timings.pixelclock.typ;
+	req_bit_clk = req_bit_clk * bpp;
+
+	switch (mipi_dsi->device->lanes) {
+	case 1:
+		break;
+	case 2:
+		req_bit_clk = req_bit_clk >> 1;
+		break;
+	case 4:
+		req_bit_clk = req_bit_clk >> 2;
+		break;
+	default:
+		printf("requested data lane num is invalid\n");
+		return -EINVAL;
+	}
+
+	debug("req_bit_clk %u\n", req_bit_clk);
+
+	/* The max rate for PLL out is 800Mhz */
+	if (req_bit_clk > mipi_dsi->max_data_rate)
+		return -EINVAL;
+
+	/* calc CM, CN and CO according to PHY PLL formula:
+	 *
+	 * 'PLL out bitclk = refclk * CM / (CN * CO);'
+	 *
+	 * Let:
+	 * 'numerator   = bitclk / divisor';
+	 * 'denominator = refclk / divisor';
+	 * Then:
+	 * 'numerator / denominator = CM / (CN * CO)';
+	 *
+	 * CM is in [16, 255]
+	 * CN is in [1, 32]
+	 * CO is in { 1, 2, 4, 8 };
+	 */
+	divisor = gcd(mipi_dsi->pll_ref, req_bit_clk);
+	WARN_ON(divisor == 1);
+
+	div_result = req_bit_clk;
+	do_div(div_result, divisor);
+	numerator = div_result;
+
+	div_result = mipi_dsi->pll_ref;
+	do_div(div_result, divisor);
+	denominator = div_result;
+
+	/* denominator & numerator out of range check */
+	if (DIV_ROUND_CLOSEST_ULL(numerator, denominator) > 255 ||
+	    DIV_ROUND_CLOSEST_ULL(denominator, numerator) > 32 * 8)
+		return -EINVAL;
+
+	/* Normalization: reduce or increase
+	 * numerator	to [16, 255]
+	 * denominator	to [1, 32 * 8]
+	 * Reduce normalization result is 'approximiate'
+	 * Increase nomralization result is 'precise'
+	 */
+	if (numerator > 255 || denominator > 32 * 8) {
+		/* approximate */
+		if (likely(numerator > denominator)) {
+			/* 'numerator > 255';
+			 * 'limit' should meet below conditions:
+			 *  a. '(numerator   / limit) >= 16'
+			 *  b. '(denominator / limit) >= 1'
+			 */
+			limit = min(denominator,
+				    DIV_ROUND_CLOSEST_ULL(numerator, 16));
+
+			/* Let:
+			 * norm_num   = numerator   / i;
+			 * norm_denom = denominator / i;
+			 *
+			 * So:
+			 * delta = numerator * norm_denom -
+			 * 	   denominator * norm_num
+			 */
+			for (i = 2; i <= limit; i++) {
+				norm_num = DIV_ROUND_CLOSEST_ULL(numerator, i);
+				if (norm_num > 255)
+					continue;
+
+				norm_denom = DIV_ROUND_CLOSEST_ULL(denominator, i);
+
+				/* 'norm_num <= 255' && 'norm_num > norm_denom'
+				 * so, 'norm_denom < 256'
+				 */
+				delta = numerator * norm_denom -
+					denominator * norm_num;
+				delta = abs(delta);
+				if (delta < least_delta) {
+					least_delta = delta;
+					best_div = i;
+				} else if (delta == least_delta) {
+					/* choose better one IF:
+					 * 'norm_denom' derived from last 'best_div'
+					 * needs later split, i.e, 'norm_denom > 32'.
+					 */
+					if (DIV_ROUND_CLOSEST_ULL(denominator, best_div) > 32) {
+						least_delta = delta;
+						best_div = i;
+					}
+				}
+			}
+		} else {
+			/* 'denominator > 32 * 8';
+			 * 'limit' should meet below conditions:
+			 *  a. '(numerator   / limit >= 16'
+			 *  b. '(denominator / limit >= 1': obviously.
+			 */
+			limit = DIV_ROUND_CLOSEST_ULL(numerator, 16);
+			if (!limit ||
+			    DIV_ROUND_CLOSEST_ULL(denominator, limit) > 32 * 8)
+				return -EINVAL;
+
+			for (i = 2; i <= limit; i++) {
+				norm_denom = DIV_ROUND_CLOSEST_ULL(denominator, i);
+				if (norm_denom > 32 * 8)
+					continue;
+
+				norm_num = DIV_ROUND_CLOSEST_ULL(numerator, i);
+
+				/* 'norm_denom <= 256' && 'norm_num < norm_denom'
+				 * so, 'norm_num <= 255'
+				 */
+				delta = numerator * norm_denom -
+					denominator * norm_num;
+				delta = abs(delta);
+				if (delta < least_delta) {
+					least_delta = delta;
+					best_div = i;
+				} else if (delta == least_delta) {
+					if (DIV_ROUND_CLOSEST_ULL(denominator, best_div) > 32) {
+						least_delta = delta;
+						best_div = i;
+					}
+				}
+			}
+		}
+
+		numerator   = DIV_ROUND_CLOSEST_ULL(numerator, best_div);
+		denominator = DIV_ROUND_CLOSEST_ULL(denominator, best_div);
+	} else if (numerator < 16) {
+		/* precise */
+
+		/* 'limit' should meet below conditions:
+		 *  a. 'denominator * limit <= 32 * 8'
+		 *  b. '16 <= numerator * limit <= 255'
+		 *  Choose 'limit' to be the least value
+		 *  which makes 'numerator * limit' to be
+		 *  in [16, 255].
+		 */
+		limit = min(256 / (uint32_t)denominator,
+			    255 / (uint32_t)numerator);
+		if (limit == 1 || limit < DIV_ROUND_UP_ULL(16, numerator))
+			return -EINVAL;
+
+		/* choose the least available value for 'limit' */
+		limit = DIV_ROUND_UP_ULL(16, numerator);
+		numerator   = numerator * limit;
+		denominator = denominator * limit;
+
+		WARN_ON(numerator < 16 || denominator > 32 * 8);
+	}
+
+	div.cm = cm_map_table[numerator - 16];
+
+	/* split 'denominator' to 'CN' and 'CO' */
+	if (denominator > 32) {
+		/* traverse four possible values of 'CO'
+		 * there must be some value of 'CO' can be used
+		 */
+		least_delta = ~0U;
+		for (i = 0; i < 4; i++) {
+			split_denom = DIV_ROUND_CLOSEST_ULL(denominator, 1 << i);
+			if (split_denom > 32)
+				continue;
+
+			/* calc deviation to choose the best one */
+			delta = denominator - split_denom * (1 << i);
+			delta = abs(delta);
+			if (delta < least_delta) {
+				least_delta = delta;
+				div.co = co_map_table[i];
+				div.cn = cn_map_table[split_denom - 1];
+			}
+		}
+	} else {
+		div.co = co_map_table[1 >> 1];
+		div.cn = cn_map_table[denominator - 1];
+	}
+
+	debug("cn 0x%x, cm 0x%x, co 0x%x\n", div.cn, div.cm, div.co);
+
+	writel(div.cn, mipi_dsi->mmio_base + DPHY_CN);
+	writel(div.cm + 1, mipi_dsi->mmio_base + DPHY_CM);
+	writel(div.co, mipi_dsi->mmio_base + DPHY_CO);
+
+	writel(0x25, mipi_dsi->mmio_base + DPHY_TST);
+	writel(0x0, mipi_dsi->mmio_base + DPHY_PD_PLL);
+
+	while (!(lock = readl(mipi_dsi->mmio_base + DPHY_LOCK))) {
+		udelay(10);
+		time_out--;
+		if (time_out == 0) {
+			printf("cannot get the dphy lock = 0x%x\n", lock);
+			return -EINVAL;
+		}
+	}
+	debug("%s: dphy lock = 0x%x\n", __func__, lock);
+
+#ifndef DPHY_RXHS_SETTLE_REG_NA
+	u32 rxhs_settle = 0x7;
+	if (req_bit_clk < 80000000)
+		rxhs_settle = 0x1;
+	else if (req_bit_clk < 250000000)
+		rxhs_settle = 0x6;
+	else if (req_bit_clk < 500000000)
+		rxhs_settle = 0x8;
+	else
+		rxhs_settle = 0xa;
+
+	writel(rxhs_settle, mipi_dsi->mmio_base + DPHY_M_PRG_RXHS_SETTLE);
+	writel(0x10, mipi_dsi->mmio_base + DPHY_MC_PRG_RXHS_SETTLE);
+#endif
+
+	writel(0x0, mipi_dsi->mmio_base + DPHY_LOCK_BYP);
+#ifndef DPHY_RTERM_SEL_REG_NA
+	writel(0x1, mipi_dsi->mmio_base + DPHY_RTERM_SEL);
+#endif
+	writel(0x0, mipi_dsi->mmio_base + DPHY_AUTO_PD_EN);
+	writel(0x1, mipi_dsi->mmio_base + DPHY_RXLPRP);
+	writel(0x1, mipi_dsi->mmio_base + DPHY_RXCDRP);
+	writel(0x0, mipi_dsi->mmio_base + DPHY_M_PRG_HS_PREPARE);
+	writel(0x0, mipi_dsi->mmio_base + DPHY_MC_PRG_HS_PREPARE);
+	writel(0x9, mipi_dsi->mmio_base + DPHY_M_PRG_HS_ZERO);
+	writel(0x20, mipi_dsi->mmio_base + DPHY_MC_PRG_HS_ZERO);
+	writel(0x5, mipi_dsi->mmio_base + DPHY_M_PRG_HS_TRAIL);
+	writel(0x5, mipi_dsi->mmio_base + DPHY_MC_PRG_HS_TRAIL);
+	writel(0x0, mipi_dsi->mmio_base + DPHY_PD_DPHY);
+
+	if (mipi_dsi->sim_ops->pll_en)
+		mipi_dsi->sim_ops->pll_en(mipi_dsi->sim, true);
+
+	return 0;
+}
+
+static int mipi_dsi_host_init(struct mipi_dsi_northwest_info *mipi_dsi)
+{
+	uint32_t lane_num;
+
+	if (mipi_dsi->device->lanes > mipi_dsi->max_data_lanes)
+		return -EINVAL;
+
+	switch (mipi_dsi->device->lanes) {
+	case 1:
+		lane_num = 0x0;
+		break;
+	case 2:
+		lane_num = 0x1;
+		break;
+	case 4:
+		lane_num = 0x3;
+		break;
+	default:
+		/* Invalid lane num */
+		return -EINVAL;
+	}
+
+	writel(lane_num, mipi_dsi->mmio_base + HOST_CFG_NUM_LANES);
+	writel(0x1, mipi_dsi->mmio_base + HOST_CFG_NONCONTINUOUS_CLK);
+	writel(0x1, mipi_dsi->mmio_base + HOST_CFG_T_PRE);
+	writel(52, mipi_dsi->mmio_base + HOST_CFG_T_POST);
+	writel(13, mipi_dsi->mmio_base + HOST_CFG_TX_GAP);
+	writel(0x1, mipi_dsi->mmio_base + HOST_CFG_AUTOINSERT_EOTP);
+	writel(0x0, mipi_dsi->mmio_base + HOST_CFG_EXTRA_CMDS_AFTER_EOTP);
+	writel(0x0, mipi_dsi->mmio_base + HOST_CFG_HTX_TO_COUNT);
+	writel(0x0, mipi_dsi->mmio_base + HOST_CFG_LRX_H_TO_COUNT);
+	writel(0x0, mipi_dsi->mmio_base + HOST_CFG_BTA_H_TO_COUNT);
+	writel(0x3A98, mipi_dsi->mmio_base + HOST_CFG_TWAKEUP);
+
+	return 0;
+}
+
+static int mipi_dsi_dpi_init(struct mipi_dsi_northwest_info *mipi_dsi)
+{
+	uint32_t color_coding, pixel_fmt;
+	int bpp;
+	struct display_timing *timings = &(mipi_dsi->timings);
+
+	bpp = mipi_dsi_pixel_format_to_bpp(mipi_dsi->device->format);
+	if (bpp < 0)
+		return -EINVAL;
+
+	writel(timings->hactive.typ, mipi_dsi->mmio_base + DPI_PIXEL_PAYLOAD_SIZE);
+	writel(timings->hactive.typ, mipi_dsi->mmio_base + DPI_PIXEL_FIFO_SEND_LEVEL);
+
+	switch (bpp) {
+	case 24:
+		color_coding = 5;
+		pixel_fmt = 3;
+		break;
+	case 16:
+	case 18:
+	default:
+		/* Not supported */
+		return -EINVAL;
+	}
+	writel(color_coding, mipi_dsi->mmio_base + DPI_INTERFACE_COLOR_CODING);
+	writel(pixel_fmt, mipi_dsi->mmio_base + DPI_PIXEL_FORMAT);
+	writel(0x0, mipi_dsi->mmio_base + DPI_VSYNC_POLARITY);
+	writel(0x0, mipi_dsi->mmio_base + DPI_HSYNC_POLARITY);
+	writel(0x0, mipi_dsi->mmio_base + DPI_VIDEO_MODE);
+
+	writel(timings->hfront_porch.typ, mipi_dsi->mmio_base + DPI_HFP);
+	writel(timings->hback_porch.typ, mipi_dsi->mmio_base + DPI_HBP);
+	writel(timings->hsync_len.typ, mipi_dsi->mmio_base + DPI_HSA);
+	writel(0x0, mipi_dsi->mmio_base + DPI_ENABLE_MULT_PKTS);
+
+	writel(timings->vback_porch.typ, mipi_dsi->mmio_base + DPI_VBP);
+	writel(timings->vfront_porch.typ, mipi_dsi->mmio_base + DPI_VFP);
+	writel(0x1, mipi_dsi->mmio_base + DPI_BLLP_MODE);
+	writel(0x0, mipi_dsi->mmio_base + DPI_USE_NULL_PKT_BLLP);
+
+	writel(timings->vactive.typ - 1, mipi_dsi->mmio_base + DPI_VACTIVE);
+
+	writel(0x0, mipi_dsi->mmio_base + DPI_VC);
+
+	return 0;
+}
+
+static void mipi_dsi_init_interrupt(struct mipi_dsi_northwest_info *mipi_dsi)
+{
+	/* disable all the irqs */
+	writel(0xffffffff, mipi_dsi->mmio_base + HOST_IRQ_MASK);
+	writel(0x7, mipi_dsi->mmio_base + HOST_IRQ_MASK2);
+}
+
+static int mipi_display_enter_sleep(struct mipi_dsi_northwest_info *mipi_dsi)
+{
+	int err;
+
+	err = mipi_dsi_dcs_cmd(mipi_dsi, MIPI_DCS_SET_DISPLAY_OFF,
+			       NULL, 0);
+	if (err)
+		return -EINVAL;
+	mdelay(50);
+
+	err = mipi_dsi_dcs_cmd(mipi_dsi, MIPI_DCS_ENTER_SLEEP_MODE,
+			NULL, 0);
+	if (err)
+		printf("MIPI DSI DCS Command sleep in error!\n");
+
+	mdelay(MIPI_LCD_SLEEP_MODE_DELAY);
+
+	return err;
+}
+
+static void mipi_dsi_wr_tx_header(struct mipi_dsi_northwest_info *mipi_dsi,
+				  u8 di, u8 data0, u8 data1, u8 mode, u8 need_bta)
+{
+	uint32_t pkt_control = 0;
+	uint16_t word_count = 0;
+
+	word_count = data0 | (data1 << 8);
+	pkt_control = HOST_PKT_CONTROL_WC(word_count) |
+		      HOST_PKT_CONTROL_VC(0)	      |
+		      HOST_PKT_CONTROL_DT(di)	      |
+		      HOST_PKT_CONTROL_HS_SEL(mode)   |
+		      HOST_PKT_CONTROL_BTA_TX(need_bta);
+
+	debug("pkt_control = %x\n", pkt_control);
+	writel(pkt_control, mipi_dsi->mmio_base + HOST_PKT_CONTROL);
+}
+
+static void mipi_dsi_wr_tx_data(struct mipi_dsi_northwest_info *mipi_dsi,
+				uint32_t tx_data)
+{
+	writel(tx_data, mipi_dsi->mmio_base + HOST_TX_PAYLOAD);
+}
+
+static void mipi_dsi_long_data_wr(struct mipi_dsi_northwest_info *mipi_dsi,
+			const uint8_t *data0, uint32_t data_size)
+{
+	uint32_t data_cnt = 0, payload = 0;
+
+	/* in case that data count is more than 4 */
+	for (data_cnt = 0; data_cnt < data_size; data_cnt += 4) {
+		/*
+		 * after sending 4bytes per one time,
+		 * send remainder data less then 4.
+		 */
+		if ((data_size - data_cnt) < 4) {
+			if ((data_size - data_cnt) == 3) {
+				payload = data0[data_cnt] |
+					  (data0[data_cnt + 1] << 8) |
+					  (data0[data_cnt + 2] << 16);
+				debug("count = 3 payload = %x, %x %x %x\n",
+				      payload, data0[data_cnt], data0[data_cnt + 1], data0[data_cnt + 2]);
+			} else if ((data_size - data_cnt) == 2) {
+				payload = data0[data_cnt] |
+					  (data0[data_cnt + 1] << 8);
+				debug("count = 2 payload = %x, %x %x\n",
+				      payload, data0[data_cnt], data0[data_cnt + 1]);
+			} else if ((data_size - data_cnt) == 1) {
+				payload = data0[data_cnt];
+				debug("count = 1 payload = %x, %x\n",
+				      payload, data0[data_cnt]);
+			}
+
+			mipi_dsi_wr_tx_data(mipi_dsi, payload);
+		} else {
+			payload = data0[data_cnt] |
+				  (data0[data_cnt + 1] << 8) |
+				  (data0[data_cnt + 2] << 16) |
+				  (data0[data_cnt + 3] << 24);
+
+			debug("count = 4 payload = %x, %x %x %x %x\n",
+			      payload, *(u8 *)(data0 + data_cnt),
+			      data0[data_cnt + 1],
+			      data0[data_cnt + 2],
+			      data0[data_cnt + 3]);
+
+			mipi_dsi_wr_tx_data(mipi_dsi, payload);
+		}
+	}
+}
+
+static int wait_for_pkt_done(struct mipi_dsi_northwest_info *mipi_dsi, unsigned long timeout)
+{
+	uint32_t irq_status, pkt_status;
+
+	/* Wait state machine to idle first, then read IRQ status
+	* IRQ status [28:9] maps dsi host controller status_out port bits, It initiates a status_port read to DSI PHY,
+	* We should not IRQ status register until state machine be idle
+	*/
+	do {
+		pkt_status = readl(mipi_dsi->mmio_base + HOST_PKT_STATUS);
+		if (!(pkt_status & HOST_IRQ_STATUS_SM_NOT_IDLE))
+			break;
+
+		udelay(1);
+	} while (--timeout);
+
+	while(timeout--) {
+		irq_status = readl(mipi_dsi->mmio_base + HOST_IRQ_STATUS);
+		if (irq_status & HOST_IRQ_STATUS_TX_PKT_DONE)
+			return timeout;
+
+		udelay(1);
+	}
+
+	return 0;
+}
+
+static int mipi_dsi_pkt_write(struct mipi_dsi_northwest_info *mipi_dsi,
+			u8 data_type, const u8 *buf, int len)
+{
+	int ret = 0;
+	const uint8_t *data = (const uint8_t *)buf;
+
+	debug("mipi_dsi_pkt_write data_type 0x%x, buf 0x%lx, len %u\n", data_type, (ulong)buf, len);
+
+	if (len == 0)
+		/* handle generic long write command */
+		mipi_dsi_wr_tx_header(mipi_dsi, data_type, data[0], data[1], DSI_LP_MODE, 0);
+	else {
+		/* handle generic long write command */
+		mipi_dsi_long_data_wr(mipi_dsi, data, len);
+		mipi_dsi_wr_tx_header(mipi_dsi, data_type, len & 0xff,
+				      (len & 0xff00) >> 8, DSI_LP_MODE, 0);
+	}
+
+	/* send packet */
+	writel(0x1, mipi_dsi->mmio_base + HOST_SEND_PACKET);
+	ret = wait_for_pkt_done(mipi_dsi, MIPI_FIFO_TIMEOUT);
+
+	if (!ret) {
+		printf("wait tx done timeout!\n");
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+#define	DSI_CMD_BUF_MAXSIZE         (128)
+
+static int mipi_dsi_dcs_cmd(struct mipi_dsi_northwest_info *mipi_dsi,
+			    u8 cmd, const u32 *param, int num)
+{
+	int err = 0;
+	u32 buf[DSI_CMD_BUF_MAXSIZE];
+
+	switch (cmd) {
+	case MIPI_DCS_EXIT_SLEEP_MODE:
+	case MIPI_DCS_ENTER_SLEEP_MODE:
+	case MIPI_DCS_SET_DISPLAY_ON:
+	case MIPI_DCS_SET_DISPLAY_OFF:
+		buf[0] = cmd;
+		buf[1] = 0x0;
+		err = mipi_dsi_pkt_write(mipi_dsi,
+				MIPI_DSI_DCS_SHORT_WRITE, (u8 *)buf, 0);
+		break;
+
+	default:
+		printf("MIPI DSI DCS Command:0x%x Not supported!\n", cmd);
+		break;
+	}
+
+	return err;
+}
+
+static void reset_dsi_domains(struct mipi_dsi_northwest_info *mipi_dsi, bool reset)
+{
+	if (mipi_dsi->sim_ops->mipi_reset)
+		mipi_dsi->sim_ops->mipi_reset(mipi_dsi->sim, reset);
+
+	if (mipi_dsi->sim_ops->dpi_reset)
+			mipi_dsi->sim_ops->dpi_reset(mipi_dsi->sim, reset);
+}
+
+static void mipi_dsi_shutdown(struct mipi_dsi_northwest_info *mipi_dsi)
+{
+	mipi_display_enter_sleep(mipi_dsi);
+
+	writel(0x1, mipi_dsi->mmio_base + DPHY_PD_PLL);
+	writel(0x1, mipi_dsi->mmio_base + DPHY_PD_DPHY);
+
+	enable_mipi_dsi_clk(false);
+
+	reset_dsi_domains(mipi_dsi, true);
+}
+
+static inline struct mipi_dsi_northwest_info *host_to_dsi(struct mipi_dsi_host *host)
+{
+	return container_of(host, struct mipi_dsi_northwest_info, dsi_host);
+}
+
+static int mipi_dsi_northwest_host_attach(struct mipi_dsi_host *host,
+				   struct mipi_dsi_device *device)
+{
+	struct mipi_dsi_northwest_info *mipi_dsi = host_to_dsi(host);
+	int ret;
+
+	/* Assert resets */
+	reset_dsi_domains(mipi_dsi, true);
+
+	/* Enable mipi relevant clocks */
+	enable_mipi_dsi_clk(true);
+
+	ret = mipi_dsi_dphy_init(mipi_dsi);
+	if (ret < 0)
+		return ret;
+
+	ret = mipi_dsi_host_init(mipi_dsi);
+	if (ret < 0)
+		return ret;
+
+	ret = mipi_dsi_dpi_init(mipi_dsi);
+	if (ret < 0)
+		return ret;
+
+	/* Deassert resets */
+	reset_dsi_domains(mipi_dsi, false);
+
+	/* display_en */
+	if (mipi_dsi->sim_ops->shutdown)
+		mipi_dsi->sim_ops->shutdown(mipi_dsi->sim, false);
+
+	/* normal cm */
+	if (mipi_dsi->sim_ops->cm_set)
+		mipi_dsi->sim_ops->cm_set(mipi_dsi->sim, true);
+	mdelay(20);
+
+	/* Disable all interrupts, since we use polling */
+	mipi_dsi_init_interrupt(mipi_dsi);
+
+	return 0;
+}
+
+static ssize_t mipi_dsi_northwest_host_transfer(struct mipi_dsi_host *host,
+					 const struct mipi_dsi_msg *msg)
+{
+	struct mipi_dsi_northwest_info *dsi = host_to_dsi(host);
+
+	if (!msg)
+		return -EINVAL;
+
+	/* do some minimum sanity checking */
+	if (!mipi_dsi_packet_format_is_short(msg->type) &&
+	    !mipi_dsi_packet_format_is_long(msg->type))
+		return -EINVAL;
+
+#ifdef DEBUG
+	int i = 0;
+	u8 *p = msg->tx_buf;
+
+	printf("sec_mipi_dsi_host_transfer\n");
+	for (i; i < msg->tx_len; i++) {
+		printf("0x%.2x ", *(u8 *)p);
+		p++;
+	}
+	printf("\n");
+#endif
+
+	if (mipi_dsi_packet_format_is_long(msg->type)) {
+		return mipi_dsi_pkt_write(dsi, msg->type, msg->tx_buf, msg->tx_len);
+	} else {
+		return mipi_dsi_pkt_write(dsi, msg->type, msg->tx_buf, 0);
+	}
+}
+
+
+static const struct mipi_dsi_host_ops mipi_dsi_northwest_host_ops = {
+	.attach = mipi_dsi_northwest_host_attach,
+	.transfer = mipi_dsi_northwest_host_transfer,
+};
+
+int imx7ulp_dsi_mipi_reset(struct regmap *sim, bool reset)
+{
+	/* escape domain */
+	regmap_update_bits(sim, SIM_SOPT1CFG,
+			DSI_RST_ESC_N, (reset ? 0 : DSI_RST_ESC_N));
+	/* byte domain */
+	regmap_update_bits(sim, SIM_SOPT1CFG,
+			DSI_RST_BYTE_N, (reset ? 0 : DSI_RST_BYTE_N));
+
+	return 0;
+}
+
+int imx7ulp_dsi_dpi_reset(struct regmap *sim, bool reset)
+{
+	/* dpi domain */
+	regmap_update_bits(sim, SIM_SOPT1CFG,
+			DSI_RST_DPI_N, (reset ? 0 : DSI_RST_DPI_N));
+
+	return 0;
+}
+
+int imx7ulp_dsi_shutdown(struct regmap *sim, bool sd)
+{
+	regmap_update_bits(sim, SIM_SOPT1CFG,
+			DSI_SD, (sd ? DSI_SD : 0));
+
+	return 0;
+}
+
+int imx7ulp_dsi_cm_set(struct regmap *sim, bool normal)
+{
+	regmap_update_bits(sim, SIM_SOPT1CFG,
+			DSI_CM, (normal ? 0 : DSI_CM));
+
+	return 0;
+}
+
+int imx7ulp_dsi_pll_en(struct regmap *sim, bool enable)
+{
+	regmap_update_bits(sim, SIM_SOPT1CFG,
+			DSI_PLL_EN, (enable ? DSI_PLL_EN : 0));
+
+	return 0;
+}
+
+int imx7ulp_dsi_isolate(struct regmap *sim, bool enable)
+{
+	regmap_update_bits(sim, SIM_SOPT1,
+			MIPI_ISO_DISABLE, (enable ? 0 : MIPI_ISO_DISABLE));
+
+	return 0;
+}
+
+int imx8ulp_dsi_mipi_reset(struct regmap *sim, bool reset)
+{
+	/* byte domain */
+	regmap_update_bits(sim, AVDSIM_SYSCTRL0,
+			AVDSIM_DSI_RST_BYTE_N, (reset ? 0 : AVDSIM_DSI_RST_BYTE_N));
+
+	/* escape domain */
+	regmap_update_bits(sim, AVDSIM_SYSCTRL0,
+			AVDSIM_DSI_RST_ESC_N, (reset ? 0 : AVDSIM_DSI_RST_ESC_N));
+
+	return 0;
+}
+
+int imx8ulp_dsi_dpi_reset(struct regmap *sim, bool reset)
+{
+	/* dpi domain */
+	regmap_update_bits(sim, AVDSIM_SYSCTRL0,
+			AVDSIM_DSI_RST_DPI_N, (reset ? 0 : AVDSIM_DSI_RST_DPI_N));
+
+	return 0;
+}
+
+int imx8ulp_dsi_shutdown(struct regmap *sim, bool sd)
+{
+	regmap_update_bits(sim, AVDSIM_SYSCTRL0,
+			AVDSIM_DSI_SD, (sd ? AVDSIM_DSI_SD : 0));
+
+	return 0;
+}
+
+int imx8ulp_dsi_cm_set(struct regmap *sim, bool normal)
+{
+	regmap_update_bits(sim, AVDSIM_SYSCTRL0,
+			AVDSIM_DSI_CM, (normal ? AVDSIM_DSI_CM : 0));
+
+	return 0;
+}
+
+static struct nwl_dsi_sim_ops imx7ulp_sim_ops = {
+	.mipi_reset = &imx7ulp_dsi_mipi_reset,
+	.dpi_reset = &imx7ulp_dsi_dpi_reset,
+	.cm_set = &imx7ulp_dsi_cm_set,
+	.shutdown = &imx7ulp_dsi_shutdown,
+	.pll_en = &imx7ulp_dsi_pll_en,
+	.isolate = &imx7ulp_dsi_isolate,
+};
+
+static struct nwl_dsi_sim_ops imx8ulp_sim_ops = {
+	.mipi_reset = &imx8ulp_dsi_mipi_reset,
+	.dpi_reset = &imx8ulp_dsi_dpi_reset,
+	.cm_set = &imx8ulp_dsi_cm_set,
+	.shutdown = &imx8ulp_dsi_shutdown,
+};
+
+static int mipi_dsi_northwest_init(struct udevice *dev,
+			    struct mipi_dsi_device *device,
+			    struct display_timing *timings,
+			    unsigned int max_data_lanes,
+			    const struct mipi_dsi_phy_ops *phy_ops)
+{
+	struct mipi_dsi_northwest_info *dsi = dev_get_priv(dev);
+	int ret;
+
+	dsi->max_data_lanes = max_data_lanes;
+	dsi->device = device;
+	dsi->dsi_host.ops = &mipi_dsi_northwest_host_ops;
+	device->host = &dsi->dsi_host;
+
+	dsi->timings = *timings;
+	dsi->mmio_base = (void *)dev_read_addr(device->dev);
+	if ((fdt_addr_t)dsi->mmio_base == FDT_ADDR_T_NONE) {
+		dev_err(device->dev, "dsi dt register address error\n");
+		return -EINVAL;
+	}
+
+	if (device_is_compatible(device->dev, "fsl,imx7ulp-mipi-dsi")) {
+		ret = dev_read_u32(device->dev, "max-data-rate", &dsi->max_data_rate);
+		if (ret) {
+			dev_err(device->dev, "fail to get max-data-rate\n");
+			return -EINVAL;
+		}
+
+		ret = dev_read_u32(device->dev, "phy-ref-clkfreq", &dsi->pll_ref);
+		if (ret) {
+			dev_err(device->dev, "fail to get phy-ref-clkfreq\n");
+			return -EINVAL;
+		}
+
+		dsi->sim = syscon_regmap_lookup_by_phandle(device->dev, "sim");
+		if (IS_ERR(dsi->sim)) {
+			dev_err(device->dev, "fail to get sim regmap\n");
+			return PTR_ERR(dsi->sim);
+		}
+
+		dsi->sim_ops = &imx7ulp_sim_ops;
+	} else if (device_is_compatible(device->dev, "fsl,imx8ulp-nwl-dsi")) {
+		dsi->max_data_rate = 1500000000;
+		dsi->pll_ref = 24000000;
+		dsi->sim = syscon_regmap_lookup_by_phandle(device->dev, "csr");
+		if (IS_ERR(dsi->sim)) {
+			dev_err(device->dev, "fail to get csr regmap\n");
+			return PTR_ERR(dsi->sim);
+		}
+
+		dsi->sim_ops = &imx8ulp_sim_ops;
+	} else {
+		dev_err(device->dev, "Invalid compatible string\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int mipi_dsi_northwest_enable(struct udevice *dev)
+{
+	struct mipi_dsi_northwest_info *mipi_dsi = dev_get_priv(dev);
+
+	/* Enter the HS mode for video stream */
+	mipi_dsi_set_mode(mipi_dsi, DSI_HS_MODE);
+
+	return 0;
+}
+
+static int mipi_dsi_northwest_disable(struct udevice *dev)
+{
+	struct mipi_dsi_northwest_info *mipi_dsi = dev_get_priv(dev);
+
+	mipi_dsi_shutdown(mipi_dsi);
+	return 0;
+}
+
+struct dsi_host_ops mipi_dsi_northwest_ops = {
+	.init = mipi_dsi_northwest_init,
+	.enable = mipi_dsi_northwest_enable,
+	.disable = mipi_dsi_northwest_disable,
+};
+
+static int mipi_dsi_northwest_probe(struct udevice *dev)
+{
+	return 0;
+}
+
+static const struct udevice_id mipi_dsi_northwest_ids[] = {
+	{ .compatible = "northwest,mipi-dsi" },
+	{ }
+};
+
+U_BOOT_DRIVER(mipi_dsi_northwest) = {
+	.name			= "mipi_dsi_northwest",
+	.id			= UCLASS_DSI_HOST,
+	.of_match		= mipi_dsi_northwest_ids,
+	.probe			= mipi_dsi_northwest_probe,
+	.ops			= &mipi_dsi_northwest_ops,
+	.priv_auto	= sizeof(struct mipi_dsi_northwest_info),
+};
diff --git a/drivers/video/nxp/imx/mipi_dsi_northwest_regs.h b/drivers/video/nxp/imx/mipi_dsi_northwest_regs.h
new file mode 100644
index 00000000000..59c156e1e2a
--- /dev/null
+++ b/drivers/video/nxp/imx/mipi_dsi_northwest_regs.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#ifndef __MIPI_DSI_NORTHWEST_REGS_H
+#define __MIPI_DSI_NORTHWEST_REGS_H
+
+/* ----------------------------	register offsets --------------------------- */
+
+/* sim */
+#define SIM_SOPT1		0x0
+#define MIPI_ISO_DISABLE	0x8
+
+#define SIM_SOPT1CFG		0x4
+#define DSI_RST_DPI_N		0x80000000
+#define DSI_RST_ESC_N		0x40000000
+#define DSI_RST_BYTE_N		0x20000000
+#define DSI_SD			0x200
+#define DSI_CM			0x100
+#define DSI_PLL_EN		0x80
+
+#define AVDSIM_SYSCTRL0		0x8
+#define AVDSIM_DSI_RST_DPI_N		0x8
+#define AVDSIM_DSI_RST_ESC_N		0x10
+#define AVDSIM_DSI_RST_BYTE_N		0x20
+#define AVDSIM_DSI_SD			0x4
+#define AVDSIM_DSI_CM			0x2
+
+/* dphy */
+#define DPHY_PD_DPHY			0x300
+#define DPHY_M_PRG_HS_PREPARE		0x304
+#define DPHY_MC_PRG_HS_PREPARE		0x308
+#define DPHY_M_PRG_HS_ZERO		0x30c
+#define DPHY_MC_PRG_HS_ZERO		0x310
+#define DPHY_M_PRG_HS_TRAIL		0x314
+#define DPHY_MC_PRG_HS_TRAIL		0x318
+
+#ifdef CONFIG_MX7ULP
+#define DPHY_RXHS_SETTLE_REG_NA
+
+#define DPHY_PD_PLL			0x31c
+#define DPHY_TST			0x320
+#define DPHY_CN				0x324
+#define DPHY_CM				0x328
+#define DPHY_CO				0x32c
+#define DPHY_LOCK			0x330
+#define DPHY_LOCK_BYP			0x334
+#define DPHY_RTERM_SEL			0x338
+#define DPHY_AUTO_PD_EN			0x33c
+#define DPHY_RXLPRP			0x340
+#define DPHY_RXCDRP			0x344
+#else
+#define DPHY_RTERM_SEL_REG_NA
+
+#define DPHY_MC_PRG_RXHS_SETTLE 0x31c
+#define DPHY_M_PRG_RXHS_SETTLE 0x320
+#define DPHY_PD_PLL			0x324
+#define DPHY_TST			0x328
+#define DPHY_CN				0x32c
+#define DPHY_CM				0x330
+#define DPHY_CO				0x334
+#define DPHY_LOCK			0x338
+#define DPHY_LOCK_BYP			0x33c
+#define DPHY_AUTO_PD_EN			0x340
+#define DPHY_RXLPRP			0x344
+#define DPHY_RXCDRP			0x348
+#endif
+
+/* host */
+#define HOST_CFG_NUM_LANES		0x0
+#define HOST_CFG_NONCONTINUOUS_CLK	0x4
+#define HOST_CFG_T_PRE			0x8
+#define HOST_CFG_T_POST			0xc
+#define HOST_CFG_TX_GAP			0x10
+#define HOST_CFG_AUTOINSERT_EOTP	0x14
+#define HOST_CFG_EXTRA_CMDS_AFTER_EOTP	0x18
+#define HOST_CFG_HTX_TO_COUNT		0x1c
+#define HOST_CFG_LRX_H_TO_COUNT		0x20
+#define HOST_CFG_BTA_H_TO_COUNT		0x24
+#define HOST_CFG_TWAKEUP		0x28
+#define HOST_CFG_STATUS_OUT		0x2c
+#define HOST_RX_ERROR_STATUS		0x30
+
+/* dpi */
+#define DPI_PIXEL_PAYLOAD_SIZE		0x200
+#define DPI_PIXEL_FIFO_SEND_LEVEL	0x204
+#define DPI_INTERFACE_COLOR_CODING	0x208
+#define DPI_PIXEL_FORMAT		0x20c
+#define DPI_VSYNC_POLARITY		0x210
+#define DPI_HSYNC_POLARITY		0x214
+#define DPI_VIDEO_MODE			0x218
+#define DPI_HFP				0x21c
+#define DPI_HBP				0x220
+#define DPI_HSA				0x224
+#define DPI_ENABLE_MULT_PKTS		0x228
+#define DPI_VBP				0x22c
+#define DPI_VFP				0x230
+#define DPI_BLLP_MODE			0x234
+#define DPI_USE_NULL_PKT_BLLP		0x238
+#define DPI_VACTIVE			0x23c
+#define DPI_VC				0x240
+
+/* apb pkt */
+#define HOST_TX_PAYLOAD			0x280
+
+#define HOST_PKT_CONTROL		0x284
+#define HOST_PKT_CONTROL_WC(x)		(((x) & 0xffff) << 0)
+#define HOST_PKT_CONTROL_VC(x)		(((x) & 0x3) << 16)
+#define HOST_PKT_CONTROL_DT(x)		(((x) & 0x3f) << 18)
+#define HOST_PKT_CONTROL_HS_SEL(x)	(((x) & 0x1) << 24)
+#define HOST_PKT_CONTROL_BTA_TX(x)	(((x) & 0x1) << 25)
+#define HOST_PKT_CONTROL_BTA_NO_TX(x)	(((x) & 0x1) << 26)
+
+#define HOST_SEND_PACKET		0x288
+#define HOST_PKT_STATUS			0x28c
+#define HOST_PKT_FIFO_WR_LEVEL		0x290
+#define HOST_PKT_FIFO_RD_LEVEL		0x294
+#define HOST_PKT_RX_PAYLOAD		0x298
+
+#define HOST_PKT_RX_PKT_HEADER		0x29c
+#define HOST_PKT_RX_PKT_HEADER_WC(x)	(((x) & 0xffff) << 0)
+#define HOST_PKT_RX_PKT_HEADER_DT(x)	(((x) & 0x3f) << 16)
+#define HOST_PKT_RX_PKT_HEADER_VC(x)	(((x) & 0x3) << 22)
+
+#define HOST_IRQ_STATUS			0x2a0
+#define HOST_IRQ_STATUS_SM_NOT_IDLE			(1 << 0)
+#define HOST_IRQ_STATUS_TX_PKT_DONE			(1 << 1)
+#define HOST_IRQ_STATUS_DPHY_DIRECTION			(1 << 2)
+#define HOST_IRQ_STATUS_TX_FIFO_OVFLW			(1 << 3)
+#define HOST_IRQ_STATUS_TX_FIFO_UDFLW			(1 << 4)
+#define HOST_IRQ_STATUS_RX_FIFO_OVFLW			(1 << 5)
+#define HOST_IRQ_STATUS_RX_FIFO_UDFLW			(1 << 6)
+#define HOST_IRQ_STATUS_RX_PKT_HDR_RCVD			(1 << 7)
+#define HOST_IRQ_STATUS_RX_PKT_PAYLOAD_DATA_RCVD	(1 << 8)
+#define HOST_IRQ_STATUS_HOST_BTA_TIMEOUT		(1 << 29)
+#define HOST_IRQ_STATUS_LP_RX_TIMEOUT			(1 << 30)
+#define HOST_IRQ_STATUS_HS_TX_TIMEOUT			(1 << 31)
+
+#define HOST_IRQ_STATUS2		0x2a4
+#define HOST_IRQ_STATUS2_SINGLE_BIT_ECC_ERR		(1 << 0)
+#define HOST_IRQ_STATUS2_MULTI_BIT_ECC_ERR		(1 << 1)
+#define HOST_IRQ_STATUS2_CRC_ERR			(1 << 2)
+
+#define HOST_IRQ_MASK			0x2a8
+#define HOST_IRQ_MASK_SM_NOT_IDLE_MASK			(1 << 0)
+#define HOST_IRQ_MASK_TX_PKT_DONE_MASK			(1 << 1)
+#define HOST_IRQ_MASK_DPHY_DIRECTION_MASK		(1 << 2)
+#define HOST_IRQ_MASK_TX_FIFO_OVFLW_MASK		(1 << 3)
+#define HOST_IRQ_MASK_TX_FIFO_UDFLW_MASK		(1 << 4)
+#define HOST_IRQ_MASK_RX_FIFO_OVFLW_MASK		(1 << 5)
+#define HOST_IRQ_MASK_RX_FIFO_UDFLW_MASK		(1 << 6)
+#define HOST_IRQ_MASK_RX_PKT_HDR_RCVD_MASK		(1 << 7)
+#define HOST_IRQ_MASK_RX_PKT_PAYLOAD_DATA_RCVD_MASK	(1 << 8)
+#define HOST_IRQ_MASK_HOST_BTA_TIMEOUT_MASK		(1 << 29)
+#define HOST_IRQ_MASK_LP_RX_TIMEOUT_MASK		(1 << 30)
+#define HOST_IRQ_MASK_HS_TX_TIMEOUT_MASK		(1 << 31)
+
+#define HOST_IRQ_MASK2			0x2ac
+#define HOST_IRQ_MASK2_SINGLE_BIT_ECC_ERR_MASK		(1 << 0)
+#define HOST_IRQ_MASK2_MULTI_BIT_ECC_ERR_MASK		(1 << 1)
+#define HOST_IRQ_MASK2_CRC_ERR_MASK			(1 << 2)
+
+/* ------------------------------------- end -------------------------------- */
+
+#endif
diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/nxp/imx/mxc_ipuv3_fb.c
index 98228f2ad67..788cea7b890 100644
--- a/drivers/video/imx/mxc_ipuv3_fb.c
+++ b/drivers/video/nxp/imx/mxc_ipuv3_fb.c
@@ -23,7 +23,7 @@
 #include <asm/mach-imx/video.h>
 #include <malloc.h>
 #include <video_fb.h>
-#include "../videomodes.h"
+#include "../../videomodes.h"
 #include "ipu.h"
 #include "mxcfb.h"
 #include "ipu_regs.h"
diff --git a/drivers/video/imx/mxcfb.h b/drivers/video/nxp/imx/mxcfb.h
index 0dc38861938..0dc38861938 100644
--- a/drivers/video/imx/mxcfb.h
+++ b/drivers/video/nxp/imx/mxcfb.h
diff --git a/drivers/video/nxp/imx/nw_dsi_imx.c b/drivers/video/nxp/imx/nw_dsi_imx.c
new file mode 100644
index 00000000000..8ac7cf8edd0
--- /dev/null
+++ b/drivers/video/nxp/imx/nw_dsi_imx.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dsi_host.h>
+#include <mipi_dsi.h>
+#include <panel.h>
+#include <reset.h>
+#include <video.h>
+#include <video_bridge.h>
+#include <video_link.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <dm/device-internal.h>
+#include <linux/iopoll.h>
+#include <linux/err.h>
+#include <power/regulator.h>
+#include <regmap.h>
+#include <syscon.h>
+
+struct nw_dsi_imx_priv {
+	struct mipi_dsi_device device;
+	struct udevice *panel;
+	struct udevice *dsi_host;
+	unsigned int data_lanes;
+};
+
+static int nw_dsi_imx_attach(struct udevice *dev)
+{
+	struct nw_dsi_imx_priv *priv = dev_get_priv(dev);
+	struct mipi_dsi_device *device = &priv->device;
+	struct mipi_dsi_panel_plat *mplat;
+	struct display_timing timings;
+	int ret;
+
+	priv->panel = video_link_get_next_device(dev);
+	if (!priv->panel ||
+		device_get_uclass_id(priv->panel) != UCLASS_PANEL) {
+		dev_err(dev, "get panel device error\n");
+		return -ENODEV;
+	}
+
+	mplat = dev_get_plat(priv->panel);
+	mplat->device = &priv->device;
+
+	ret = video_link_get_display_timings(&timings);
+	if (ret) {
+		dev_err(dev, "decode display timing error %d\n", ret);
+		return ret;
+	}
+
+	ret = uclass_get_device(UCLASS_DSI_HOST, 0, &priv->dsi_host);
+	if (ret) {
+		dev_err(dev, "No video dsi host detected %d\n", ret);
+		return ret;
+	}
+
+	ret = dsi_host_init(priv->dsi_host, device, &timings,
+			priv->data_lanes,
+			NULL);
+	if (ret) {
+		dev_err(dev, "failed to initialize mipi dsi host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int nw_dsi_imx_set_backlight(struct udevice *dev, int percent)
+{
+	struct nw_dsi_imx_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = panel_enable_backlight(priv->panel);
+	if (ret) {
+		dev_err(dev, "panel %s enable backlight error %d\n",
+			priv->panel->name, ret);
+		return ret;
+	}
+
+	ret = dsi_host_enable(priv->dsi_host);
+	if (ret) {
+		dev_err(dev, "failed to enable mipi dsi host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int nw_dsi_imx_probe(struct udevice *dev)
+{
+	struct nw_dsi_imx_priv *priv = dev_get_priv(dev);
+	struct mipi_dsi_device *device = &priv->device;
+	int ret;
+
+	device->dev = dev;
+
+	ret = dev_read_u32(dev, "data-lanes-num", &priv->data_lanes);
+	if (ret) {
+		printf("fail to get data lanes property %d\n", ret);
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+static int nw_dsi_imx_remove(struct udevice *dev)
+{
+	struct nw_dsi_imx_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	if (priv->panel)
+		device_remove(priv->panel, DM_REMOVE_NORMAL);
+
+	ret = dsi_host_disable(priv->dsi_host);
+	if (ret) {
+		dev_err(dev, "failed to enable mipi dsi host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+struct video_bridge_ops nw_dsi_imx_ops = {
+	.attach = nw_dsi_imx_attach,
+	.set_backlight = nw_dsi_imx_set_backlight,
+};
+
+static const struct udevice_id nw_dsi_imx_ids[] = {
+	{ .compatible = "fsl,imx7ulp-mipi-dsi" },
+	{ .compatible = "fsl,imx8ulp-nwl-dsi" },
+	{ }
+};
+
+U_BOOT_DRIVER(nw_dsi_imx) = {
+	.name				= "nw_dsi_imx",
+	.id				= UCLASS_VIDEO_BRIDGE,
+	.of_match			= nw_dsi_imx_ids,
+	.bind				= dm_scan_fdt_dev,
+	.remove 			= nw_dsi_imx_remove,
+	.probe				= nw_dsi_imx_probe,
+	.ops				= &nw_dsi_imx_ops,
+	.priv_auto		= sizeof(struct nw_dsi_imx_priv),
+};
diff --git a/drivers/video/nxp/imx/sec_dsim_imx.c b/drivers/video/nxp/imx/sec_dsim_imx.c
new file mode 100644
index 00000000000..2e6aa467f7f
--- /dev/null
+++ b/drivers/video/nxp/imx/sec_dsim_imx.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <dsi_host.h>
+#include <mipi_dsi.h>
+#include <panel.h>
+#include <reset.h>
+#include <video.h>
+#include <video_bridge.h>
+#include <video_link.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <dm/device-internal.h>
+#include <linux/iopoll.h>
+#include <linux/err.h>
+#include <power/regulator.h>
+#include <regmap.h>
+#include <syscon.h>
+
+struct imx_sec_dsim_priv {
+	struct mipi_dsi_device device;
+	void __iomem *base;
+	struct udevice *panel;
+	struct udevice *dsi_host;
+	struct reset_ctl_bulk soft_resetn;
+	struct reset_ctl_bulk clk_enable;
+	struct reset_ctl_bulk mipi_reset;
+};
+
+#if IS_ENABLED(CONFIG_DM_RESET)
+static int sec_dsim_rstc_reset(struct reset_ctl_bulk *rstc, bool assert)
+{
+	int ret;
+
+	if (!rstc)
+		return 0;
+
+	ret = assert ? reset_assert_bulk(rstc)	:
+		       reset_deassert_bulk(rstc);
+
+	return ret;
+}
+
+static int sec_dsim_of_parse_resets(struct udevice *dev)
+{
+	int ret;
+	ofnode parent, child;
+	struct ofnode_phandle_args args;
+	struct reset_ctl_bulk rstc;
+	const char *compat;
+	uint32_t rstc_num = 0;
+
+	struct imx_sec_dsim_priv *priv = dev_get_priv(dev);
+
+	ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0,
+					 0, &args);
+	if (ret)
+		return ret;
+
+	parent = args.node;
+	ofnode_for_each_subnode(child, parent) {
+		compat = ofnode_get_property(child, "compatible", NULL);
+		if (!compat)
+			continue;
+
+		ret = reset_get_bulk_nodev(child, &rstc);
+		if (ret)
+			continue;
+
+		if (!of_compat_cmp("dsi,soft-resetn", compat, 0)) {
+			priv->soft_resetn = rstc;
+			rstc_num++;
+		} else if (!of_compat_cmp("dsi,clk-enable", compat, 0)) {
+			priv->clk_enable = rstc;
+			rstc_num++;
+		} else if (!of_compat_cmp("dsi,mipi-reset", compat, 0)) {
+			priv->mipi_reset = rstc;
+			rstc_num++;
+		} else
+			dev_warn(dev, "invalid dsim reset node: %s\n", compat);
+	}
+
+	if (!rstc_num) {
+		dev_err(dev, "no invalid reset control exists\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+#endif
+
+static int imx_sec_dsim_attach(struct udevice *dev)
+{
+	struct imx_sec_dsim_priv *priv = dev_get_priv(dev);
+	struct mipi_dsi_device *device = &priv->device;
+	struct mipi_dsi_panel_plat *mplat;
+	struct display_timing timings;
+	int ret;
+
+	priv->panel = video_link_get_next_device(dev);
+	if (!priv->panel ||
+		device_get_uclass_id(priv->panel) != UCLASS_PANEL) {
+		dev_err(dev, "get panel device error\n");
+		return -ENODEV;
+	}
+
+	mplat = dev_get_plat(priv->panel);
+	mplat->device = &priv->device;
+
+	ret = video_link_get_display_timings(&timings);
+	if (ret) {
+		dev_err(dev, "decode display timing error %d\n", ret);
+		return ret;
+	}
+
+	ret = uclass_get_device(UCLASS_DSI_HOST, 0, &priv->dsi_host);
+	if (ret) {
+		dev_err(dev, "No video dsi host detected %d\n", ret);
+		return ret;
+	}
+
+	ret = dsi_host_init(priv->dsi_host, device, &timings, 4,
+			    NULL);
+	if (ret) {
+		dev_err(dev, "failed to initialize mipi dsi host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int imx_sec_dsim_set_backlight(struct udevice *dev, int percent)
+{
+	struct imx_sec_dsim_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = panel_enable_backlight(priv->panel);
+	if (ret) {
+		dev_err(dev, "panel %s enable backlight error %d\n",
+			priv->panel->name, ret);
+		return ret;
+	}
+
+	ret = dsi_host_enable(priv->dsi_host);
+	if (ret) {
+		dev_err(dev, "failed to enable mipi dsi host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int imx_sec_dsim_probe(struct udevice *dev)
+{
+	struct imx_sec_dsim_priv *priv = dev_get_priv(dev);
+	struct mipi_dsi_device *device = &priv->device;
+
+	device->dev = dev;
+
+#if IS_ENABLED(CONFIG_DM_RESET)
+	int ret;
+	/* Allow to not have resets */
+	ret = sec_dsim_of_parse_resets(dev);
+	if (!ret) {
+		ret = sec_dsim_rstc_reset(&priv->soft_resetn, false);
+		if (ret) {
+			dev_err(dev, "deassert soft_resetn failed\n");
+			return ret;
+		}
+
+		ret = sec_dsim_rstc_reset(&priv->clk_enable, true);
+		if (ret) {
+			dev_err(dev, "assert clk_enable failed\n");
+			return ret;
+		}
+
+		ret = sec_dsim_rstc_reset(&priv->mipi_reset, false);
+		if (ret) {
+			dev_err(dev, "deassert mipi_reset failed\n");
+			return ret;
+		}
+	}
+#endif
+
+	return 0;
+}
+
+static int imx_sec_dsim_remove(struct udevice *dev)
+{
+	struct imx_sec_dsim_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	if (priv->panel)
+		device_remove(priv->panel, DM_REMOVE_NORMAL);
+
+	ret = dsi_host_disable(priv->dsi_host);
+	if (ret) {
+		dev_err(dev, "failed to enable mipi dsi host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+struct video_bridge_ops imx_sec_dsim_ops = {
+	.attach = imx_sec_dsim_attach,
+	.set_backlight = imx_sec_dsim_set_backlight,
+};
+
+static const struct udevice_id imx_sec_dsim_ids[] = {
+	{ .compatible = "fsl,imx8mm-mipi-dsim" },
+	{ .compatible = "fsl,imx8mn-mipi-dsim" },
+	{ .compatible = "fsl,imx8mp-mipi-dsim" },
+	{ }
+};
+
+U_BOOT_DRIVER(imx_sec_dsim) = {
+	.name				= "imx_sec_dsim",
+	.id				= UCLASS_VIDEO_BRIDGE,
+	.of_match			= imx_sec_dsim_ids,
+	.bind				= dm_scan_fdt_dev,
+	.remove 			= imx_sec_dsim_remove,
+	.probe				= imx_sec_dsim_probe,
+	.ops				= &imx_sec_dsim_ops,
+	.priv_auto		= sizeof(struct imx_sec_dsim_priv),
+};
diff --git a/drivers/video/nxp/imx/sec_mipi_dsim.c b/drivers/video/nxp/imx/sec_mipi_dsim.c
new file mode 100644
index 00000000000..246e7f467dc
--- /dev/null
+++ b/drivers/video/nxp/imx/sec_mipi_dsim.c
@@ -0,0 +1,1476 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <asm/io.h>
+#include <linux/err.h>
+#include <linux/bug.h>
+#include <linux/delay.h>
+#include <linux/log2.h>
+#include <asm/unaligned.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <div64.h>
+#include <video_bridge.h>
+#include <panel.h>
+#include <dsi_host.h>
+#include <asm/arch/gpio.h>
+#include <dm/device-internal.h>
+
+#define MIPI_FIFO_TIMEOUT		250000 /* 250ms */
+
+#define DRIVER_NAME "sec_mipi_dsim"
+
+/* dsim registers */
+#define DSIM_VERSION			0x00
+#define DSIM_STATUS			0x04
+#define DSIM_RGB_STATUS			0x08
+#define DSIM_SWRST			0x0c
+#define DSIM_CLKCTRL			0x10
+#define DSIM_TIMEOUT			0x14
+#define DSIM_CONFIG			0x18
+#define DSIM_ESCMODE			0x1c
+#define DSIM_MDRESOL			0x20
+#define DSIM_MVPORCH			0x24
+#define DSIM_MHPORCH			0x28
+#define DSIM_MSYNC			0x2c
+#define DSIM_SDRESOL			0x30
+#define DSIM_INTSRC			0x34
+#define DSIM_INTMSK			0x38
+
+/* packet */
+#define DSIM_PKTHDR			0x3c
+#define DSIM_PAYLOAD			0x40
+#define DSIM_RXFIFO			0x44
+#define DSIM_FIFOTHLD			0x48
+#define DSIM_FIFOCTRL			0x4c
+#define DSIM_MEMACCHR		0x50
+#define DSIM_MULTI_PKT			0x78
+
+/* pll control */
+#define DSIM_PLLCTRL_1G			0x90
+#define DSIM_PLLCTRL			0x94
+#define DSIM_PLLCTRL1			0x98
+#define DSIM_PLLCTRL2			0x9c
+#define DSIM_PLLTMR			0xa0
+
+/* dphy */
+#define DSIM_PHYTIMING			0xb4
+#define DSIM_PHYTIMING1			0xb8
+#define DSIM_PHYTIMING2			0xbc
+
+/* reg bit manipulation */
+#define REG_MASK(e, s) (((1 << ((e) - (s) + 1)) - 1) << (s))
+#define REG_PUT(x, e, s) (((x) << (s)) & REG_MASK(e, s))
+#define REG_GET(x, e, s) (((x) & REG_MASK(e, s)) >> (s))
+
+/* register bit fields */
+#define STATUS_PLLSTABLE		BIT(31)
+#define STATUS_SWRSTRLS			BIT(20)
+#define STATUS_TXREADYHSCLK		BIT(10)
+#define STATUS_ULPSCLK			BIT(9)
+#define STATUS_STOPSTATECLK		BIT(8)
+#define STATUS_GET_ULPSDAT(x)		REG_GET(x,  7,  4)
+#define STATUS_GET_STOPSTATEDAT(x)	REG_GET(x,  3,  0)
+
+#define RGB_STATUS_CMDMODE_INSEL	BIT(31)
+#define RGB_STATUS_GET_RGBSTATE(x)	REG_GET(x, 12,  0)
+
+#define CLKCTRL_TXREQUESTHSCLK		BIT(31)
+#define CLKCTRL_DPHY_SEL_1G		BIT(29)
+#define CLKCTRL_DPHY_SEL_1P5G		(0x0 << 29)
+#define CLKCTRL_ESCCLKEN		BIT(28)
+#define CLKCTRL_PLLBYPASS		BIT(29)
+#define CLKCTRL_BYTECLKSRC_DPHY_PLL	REG_PUT(0, 26, 25)
+#define CLKCTRL_BYTECLKEN		BIT(24)
+#define CLKCTRL_SET_LANEESCCLKEN(x)	REG_PUT(x, 23, 19)
+#define CLKCTRL_SET_ESCPRESCALER(x)	REG_PUT(x, 15,  0)
+
+#define TIMEOUT_SET_BTAOUT(x)		REG_PUT(x, 23, 16)
+#define TIMEOUT_SET_LPDRTOUT(x)		REG_PUT(x, 15,  0)
+
+#define CONFIG_NON_CONTINOUS_CLOCK_LANE	BIT(31)
+#define CONFIG_CLKLANE_STOP_START	BIT(30)
+#define CONFIG_MFLUSH_VS		BIT(29)
+#define CONFIG_EOT_R03			BIT(28)
+#define CONFIG_SYNCINFORM		BIT(27)
+#define CONFIG_BURSTMODE		BIT(26)
+#define CONFIG_VIDEOMODE		BIT(25)
+#define CONFIG_AUTOMODE			BIT(24)
+#define CONFIG_HSEDISABLEMODE		BIT(23)
+#define CONFIG_HFPDISABLEMODE		BIT(22)
+#define CONFIG_HBPDISABLEMODE		BIT(21)
+#define CONFIG_HSADISABLEMODE		BIT(20)
+#define CONFIG_SET_MAINVC(x)		REG_PUT(x, 19, 18)
+#define CONFIG_SET_SUBVC(x)		REG_PUT(x, 17, 16)
+#define CONFIG_SET_MAINPIXFORMAT(x)	REG_PUT(x, 14, 12)
+#define CONFIG_SET_SUBPIXFORMAT(x)	REG_PUT(x, 10,  8)
+#define CONFIG_SET_NUMOFDATLANE(x)	REG_PUT(x,  6,  5)
+#define CONFIG_SET_LANEEN(x)		REG_PUT(x,  4,  0)
+
+#define ESCMODE_SET_STOPSTATE_CNT(X)	REG_PUT(x, 31, 21)
+#define ESCMODE_FORCESTOPSTATE		BIT(20)
+#define ESCMODE_FORCEBTA		BIT(16)
+#define ESCMODE_CMDLPDT			BIT(7)
+#define ESCMODE_TXLPDT			BIT(6)
+#define ESCMODE_TXTRIGGERRST		BIT(5)
+
+#define MDRESOL_MAINSTANDBY		BIT(31)
+#define MDRESOL_SET_MAINVRESOL(x)	REG_PUT(x, 27, 16)
+#define MDRESOL_SET_MAINHRESOL(x)	REG_PUT(x, 11,  0)
+
+#define MVPORCH_SET_CMDALLOW(x)		REG_PUT(x, 31, 28)
+#define MVPORCH_SET_STABLEVFP(x)	REG_PUT(x, 26, 16)
+#define MVPORCH_SET_MAINVBP(x)		REG_PUT(x, 10,  0)
+
+#define MHPORCH_SET_MAINHFP(x)		REG_PUT(x, 31, 16)
+#define MHPORCH_SET_MAINHBP(x)		REG_PUT(x, 15,  0)
+
+#define MSYNC_SET_MAINVSA(x)		REG_PUT(x, 31, 22)
+#define MSYNC_SET_MAINHSA(x)		REG_PUT(x, 15,  0)
+
+#define INTSRC_PLLSTABLE		BIT(31)
+#define INTSRC_SWRSTRELEASE		BIT(30)
+#define INTSRC_SFRPLFIFOEMPTY		BIT(29)
+#define INTSRC_SFRPHFIFOEMPTY		BIT(28)
+#define INTSRC_FRAMEDONE		BIT(24)
+#define INTSRC_LPDRTOUT			BIT(21)
+#define INTSRC_TATOUT			BIT(20)
+#define INTSRC_RXDATDONE		BIT(18)
+#define INTSRC_MASK			(INTSRC_PLLSTABLE	|	\
+					 INTSRC_SWRSTRELEASE	|	\
+					 INTSRC_SFRPLFIFOEMPTY	|	\
+					 INTSRC_SFRPHFIFOEMPTY	|	\
+					 INTSRC_FRAMEDONE	|	\
+					 INTSRC_LPDRTOUT	|	\
+					 INTSRC_TATOUT		|	\
+					 INTSRC_RXDATDONE)
+
+#define INTMSK_MSKPLLSTABLE		BIT(31)
+#define INTMSK_MSKSWRELEASE		BIT(30)
+#define INTMSK_MSKSFRPLFIFOEMPTY	BIT(29)
+#define INTMSK_MSKSFRPHFIFOEMPTY	BIT(28)
+#define INTMSK_MSKFRAMEDONE		BIT(24)
+#define INTMSK_MSKLPDRTOUT		BIT(21)
+#define INTMSK_MSKTATOUT		BIT(20)
+#define INTMSK_MSKRXDATDONE		BIT(18)
+
+#define PKTHDR_SET_DATA1(x)		REG_PUT(x, 23, 16)
+#define PKTHDR_GET_DATA1(x)		REG_GET(x, 23, 16)
+#define PKTHDR_SET_DATA0(x)		REG_PUT(x, 15,  8)
+#define PKTHDR_GET_DATA0(x)		REG_GET(x, 15,  8)
+#define PKTHDR_GET_WC(x)		REG_GET(x, 23,  8)
+#define PKTHDR_SET_DI(x)		REG_PUT(x,  7,  0)
+#define PKTHDR_GET_DI(x)		REG_GET(x,  7,  0)
+#define PKTHDR_SET_DT(x)		REG_PUT(x,  5,  0)
+#define PKTHDR_GET_DT(x)		REG_GET(x,  5,  0)
+#define PKTHDR_SET_VC(x)		REG_PUT(x,  7,  6)
+#define PKTHDR_GET_VC(x)		REG_GET(x,  7,  6)
+
+#define FIFOCTRL_FULLRX			BIT(25)
+#define FIFOCTRL_EMPTYRX		BIT(24)
+#define FIFOCTRL_FULLHSFR		BIT(23)
+#define FIFOCTRL_EMPTYHSFR		BIT(22)
+#define FIFOCTRL_FULLLSFR		BIT(21)
+#define FIFOCTRL_EMPTYLSFR		BIT(20)
+#define FIFOCTRL_FULLHMAIN		BIT(11)
+#define FIFOCTRL_EMPTYHMAIN		BIT(10)
+#define FIFOCTRL_FULLLMAIN		BIT(9)
+#define FIFOCTRL_EMPTYLMAIN		BIT(8)
+#define FIFOCTRL_NINITRX		BIT(4)
+#define FIFOCTRL_NINITSFR		BIT(3)
+#define FIFOCTRL_NINITI80		BIT(2)
+#define FIFOCTRL_NINITSUB		BIT(1)
+#define FIFOCTRL_NINITMAIN		BIT(0)
+
+#define PLLCTRL_DPDNSWAP_CLK		BIT(25)
+#define PLLCTRL_DPDNSWAP_DAT		BIT(24)
+#define PLLCTRL_PLLEN			BIT(23)
+#define PLLCTRL_SET_PMS(x)		REG_PUT(x, 19,  1)
+#define PLLCTRL_SET_P(x)		REG_PUT(x, 18, 13)
+#define PLLCTRL_SET_M(x)		REG_PUT(x, 12,  3)
+#define PLLCTRL_SET_S(x)		REG_PUT(x,  2,  0)
+
+#define PHYTIMING_SET_M_TLPXCTL(x)	REG_PUT(x, 15,  8)
+#define PHYTIMING_SET_M_THSEXITCTL(x)	REG_PUT(x,  7,  0)
+
+#define PHYTIMING1_SET_M_TCLKPRPRCTL(x)	 REG_PUT(x, 31, 24)
+#define PHYTIMING1_SET_M_TCLKZEROCTL(x)	 REG_PUT(x, 23, 16)
+#define PHYTIMING1_SET_M_TCLKPOSTCTL(x)	 REG_PUT(x, 15,  8)
+#define PHYTIMING1_SET_M_TCLKTRAILCTL(x) REG_PUT(x,  7,  0)
+
+#define PHYTIMING2_SET_M_THSPRPRCTL(x)	REG_PUT(x, 23, 16)
+#define PHYTIMING2_SET_M_THSZEROCTL(x)	REG_PUT(x, 15,  8)
+#define PHYTIMING2_SET_M_THSTRAILCTL(x)	REG_PUT(x,  7,  0)
+
+#define dsim_read(dsim, reg)		readl(dsim->base + reg)
+#define dsim_write(dsim, val, reg)	writel(val, dsim->base + reg)
+
+#define MAX_MAIN_HRESOL		2047
+#define MAX_MAIN_VRESOL		2047
+#define MAX_SUB_HRESOL		1024
+#define MAX_SUB_VRESOL		1024
+
+/* in KHZ */
+#define MAX_ESC_CLK_FREQ	20000
+
+/* dsim all irqs index */
+#define PLLSTABLE		1
+#define SWRSTRELEASE		2
+#define SFRPLFIFOEMPTY		3
+#define SFRPHFIFOEMPTY		4
+#define SYNCOVERRIDE		5
+#define BUSTURNOVER		6
+#define FRAMEDONE		7
+#define LPDRTOUT		8
+#define TATOUT			9
+#define RXDATDONE		10
+#define RXTE			11
+#define RXACK			12
+#define ERRRXECC		13
+#define ERRRXCRC		14
+#define ERRESC3			15
+#define ERRESC2			16
+#define ERRESC1			17
+#define ERRESC0			18
+#define ERRSYNC3		19
+#define ERRSYNC2		20
+#define ERRSYNC1		21
+#define ERRSYNC0		22
+#define ERRCONTROL3		23
+#define ERRCONTROL2		24
+#define ERRCONTROL1		25
+#define ERRCONTROL0		26
+
+/* Dispmix Control & GPR Registers */
+#define DISPLAY_MIX_SFT_RSTN_CSR		0x00
+#ifdef CONFIG_IMX8MN
+#define MIPI_DSI_I_PRESETn_SFT_EN		BIT(0) | BIT(1)
+#else
+   #define MIPI_DSI_I_PRESETn_SFT_EN		BIT(5)
+#endif
+#define DISPLAY_MIX_CLK_EN_CSR			0x04
+
+#ifdef CONFIG_IMX8MN
+#define MIPI_DSI_PCLK_SFT_EN		 BIT(0)
+#define MIPI_DSI_CLKREF_SFT_EN		 BIT(1)
+#else
+   #define MIPI_DSI_PCLK_SFT_EN			BIT(8)
+   #define MIPI_DSI_CLKREF_SFT_EN		BIT(9)
+#endif
+#define GPR_MIPI_RESET_DIV			0x08
+   /* Clock & Data lanes reset: Active Low */
+   #define GPR_MIPI_S_RESETN			BIT(16)
+   #define GPR_MIPI_M_RESETN			BIT(17)
+
+#define	PS2KHZ(ps)	(1000000000UL / (ps))
+
+#define MIPI_HFP_PKT_OVERHEAD	6
+#define MIPI_HBP_PKT_OVERHEAD	6
+#define MIPI_HSA_PKT_OVERHEAD	6
+
+
+/* DSIM PLL configuration from spec:
+ *
+ * Fout(DDR) = (M * Fin) / (P * 2^S), so Fout / Fin = M / (P * 2^S)
+ * Fin_pll   = Fin / P     (6 ~ 12 MHz)
+ * S: [2:0], M: [12:3], P: [18:13], so
+ * TODO: 'S' is in [0 ~ 3], 'M' is in, 'P' is in [1 ~ 33]
+ *
+ */
+
+struct sec_mipi_dsim {
+	void __iomem *base;
+
+	/* kHz clocks */
+	uint64_t pix_clk;
+	uint64_t bit_clk;
+
+	unsigned int lanes;
+	unsigned int channel;			/* virtual channel */
+	enum mipi_dsi_pixel_format format;
+	unsigned long mode_flags;
+	unsigned int pms;
+	unsigned int p;
+	unsigned int m;
+	unsigned int s;
+
+	 struct mipi_dsi_device *device;
+	 uint32_t max_data_lanes;
+	 uint64_t max_data_rate;
+
+	 struct mipi_dsi_host dsi_host;
+
+	 struct display_timing timings;
+};
+
+struct sec_mipi_dsim_range {
+	uint32_t min;
+	uint32_t max;
+};
+
+/* DPHY timings structure */
+struct sec_mipi_dsim_dphy_timing {
+	uint32_t bit_clk;	/* MHz */
+
+	uint32_t clk_prepare;
+	uint32_t clk_zero;
+	uint32_t clk_post;
+	uint32_t clk_trail;
+
+	uint32_t hs_prepare;
+	uint32_t hs_zero;
+	uint32_t hs_trail;
+
+	uint32_t lpx;
+	uint32_t hs_exit;
+};
+
+#define DSIM_DPHY_TIMING(bclk, cpre, czero, cpost, ctrail,	\
+			 hpre, hzero, htrail, lp, hexit)	\
+	.bit_clk	= bclk,					\
+	.clk_prepare	= cpre,					\
+	.clk_zero	= czero,				\
+	.clk_post	= cpost,				\
+	.clk_trail	= ctrail,				\
+	.hs_prepare	= hpre,					\
+	.hs_zero	= hzero,				\
+	.hs_trail	= htrail,				\
+	.lpx		= lp,					\
+	.hs_exit	= hexit
+
+/* descending order based on 'bit_clk' value */
+static const struct sec_mipi_dsim_dphy_timing dphy_timing[] = {
+	{ DSIM_DPHY_TIMING(2100, 19, 91, 22, 19, 20, 35, 22, 15, 26), },
+	{ DSIM_DPHY_TIMING(2090, 19, 91, 22, 19, 19, 35, 22, 15, 26), },
+	{ DSIM_DPHY_TIMING(2080, 19, 91, 21, 18, 19, 35, 22, 15, 26), },
+	{ DSIM_DPHY_TIMING(2070, 18, 90, 21, 18, 19, 35, 22, 15, 25), },
+	{ DSIM_DPHY_TIMING(2060, 18, 90, 21, 18, 19, 34, 22, 15, 25), },
+	{ DSIM_DPHY_TIMING(2050, 18, 89, 21, 18, 19, 34, 22, 15, 25), },
+	{ DSIM_DPHY_TIMING(2040, 18, 89, 21, 18, 19, 34, 21, 15, 25), },
+	{ DSIM_DPHY_TIMING(2030, 18, 88, 21, 18, 19, 34, 21, 15, 25), },
+	{ DSIM_DPHY_TIMING(2020, 18, 88, 21, 18, 19, 34, 21, 15, 25), },
+	{ DSIM_DPHY_TIMING(2010, 18, 87, 21, 18, 19, 34, 21, 15, 25), },
+	{ DSIM_DPHY_TIMING(2000, 18, 87, 21, 18, 19, 33, 21, 15, 25), },
+	{ DSIM_DPHY_TIMING(1990, 18, 87, 21, 18, 18, 33, 21, 14, 24), },
+	{ DSIM_DPHY_TIMING(1980, 18, 86, 21, 18, 18, 33, 21, 14, 24), },
+	{ DSIM_DPHY_TIMING(1970, 17, 86, 21, 17, 18, 33, 21, 14, 24), },
+	{ DSIM_DPHY_TIMING(1960, 17, 85, 21, 17, 18, 33, 21, 14, 24), },
+	{ DSIM_DPHY_TIMING(1950, 17, 85, 21, 17, 18, 32, 21, 14, 24), },
+	{ DSIM_DPHY_TIMING(1940, 17, 84, 20, 17, 18, 32, 21, 14, 24), },
+	{ DSIM_DPHY_TIMING(1930, 17, 84, 20, 17, 18, 32, 20, 14, 24), },
+	{ DSIM_DPHY_TIMING(1920, 17, 84, 20, 17, 18, 32, 20, 14, 24), },
+	{ DSIM_DPHY_TIMING(1910, 17, 83, 20, 17, 18, 32, 20, 14, 23), },
+	{ DSIM_DPHY_TIMING(1900, 17, 83, 20, 17, 18, 32, 20, 14, 23), },
+	{ DSIM_DPHY_TIMING(1890, 17, 82, 20, 17, 18, 31, 20, 14, 23), },
+	{ DSIM_DPHY_TIMING(1880, 17, 82, 20, 17, 17, 31, 20, 14, 23), },
+	{ DSIM_DPHY_TIMING(1870, 17, 81, 20, 17, 17, 31, 20, 14, 23), },
+	{ DSIM_DPHY_TIMING(1860, 16, 81, 20, 17, 17, 31, 20, 13, 23), },
+	{ DSIM_DPHY_TIMING(1850, 16, 80, 20, 16, 17, 31, 20, 13, 23), },
+	{ DSIM_DPHY_TIMING(1840, 16, 80, 20, 16, 17, 30, 20, 13, 23), },
+	{ DSIM_DPHY_TIMING(1830, 16, 80, 20, 16, 17, 30, 20, 13, 22), },
+	{ DSIM_DPHY_TIMING(1820, 16, 79, 20, 16, 17, 30, 19, 13, 22), },
+	{ DSIM_DPHY_TIMING(1810, 16, 79, 19, 16, 17, 30, 19, 13, 22), },
+	{ DSIM_DPHY_TIMING(1800, 16, 78, 19, 16, 17, 30, 19, 13, 22), },
+	{ DSIM_DPHY_TIMING(1790, 16, 78, 19, 16, 17, 30, 19, 13, 22), },
+	{ DSIM_DPHY_TIMING(1780, 16, 77, 19, 16, 16, 29, 19, 13, 22), },
+	{ DSIM_DPHY_TIMING(1770, 16, 77, 19, 16, 16, 29, 19, 13, 22), },
+	{ DSIM_DPHY_TIMING(1760, 16, 77, 19, 16, 16, 29, 19, 13, 22), },
+	{ DSIM_DPHY_TIMING(1750, 15, 76, 19, 16, 16, 29, 19, 13, 21), },
+	{ DSIM_DPHY_TIMING(1740, 15, 76, 19, 15, 16, 29, 19, 13, 21), },
+	{ DSIM_DPHY_TIMING(1730, 15, 75, 19, 15, 16, 28, 19, 12, 21), },
+	{ DSIM_DPHY_TIMING(1720, 15, 75, 19, 15, 16, 28, 19, 12, 21), },
+	{ DSIM_DPHY_TIMING(1710, 15, 74, 19, 15, 16, 28, 18, 12, 21), },
+	{ DSIM_DPHY_TIMING(1700, 15, 74, 19, 15, 16, 28, 18, 12, 21), },
+	{ DSIM_DPHY_TIMING(1690, 15, 73, 19, 15, 16, 28, 18, 12, 21), },
+	{ DSIM_DPHY_TIMING(1680, 15, 73, 18, 15, 16, 28, 18, 12, 21), },
+	{ DSIM_DPHY_TIMING(1670, 15, 73, 18, 15, 15, 27, 18, 12, 20), },
+	{ DSIM_DPHY_TIMING(1660, 15, 72, 18, 15, 15, 27, 18, 12, 20), },
+	{ DSIM_DPHY_TIMING(1650, 14, 72, 18, 15, 15, 27, 18, 12, 20), },
+	{ DSIM_DPHY_TIMING(1640, 14, 71, 18, 15, 15, 27, 18, 12, 20), },
+	{ DSIM_DPHY_TIMING(1630, 14, 71, 18, 15, 15, 27, 18, 12, 20), },
+	{ DSIM_DPHY_TIMING(1620, 14, 70, 18, 14, 15, 26, 18, 12, 20), },
+	{ DSIM_DPHY_TIMING(1610, 14, 70, 18, 14, 15, 26, 17, 12, 20), },
+	{ DSIM_DPHY_TIMING(1600, 14, 70, 18, 14, 15, 26, 17, 12, 20), },
+	{ DSIM_DPHY_TIMING(1590, 14, 69, 18, 14, 15, 26, 17, 11, 19), },
+	{ DSIM_DPHY_TIMING(1580, 14, 69, 18, 14, 15, 26, 17, 11, 19), },
+	{ DSIM_DPHY_TIMING(1570, 14, 68, 18, 14, 15, 26, 17, 11, 19), },
+	{ DSIM_DPHY_TIMING(1560, 14, 68, 18, 14, 14, 25, 17, 11, 19), },
+	{ DSIM_DPHY_TIMING(1550, 14, 67, 18, 14, 14, 25, 17, 11, 19), },
+	{ DSIM_DPHY_TIMING(1540, 13, 67, 17, 14, 14, 25, 17, 11, 19), },
+	{ DSIM_DPHY_TIMING(1530, 13, 66, 17, 14, 14, 25, 17, 11, 19), },
+	{ DSIM_DPHY_TIMING(1520, 13, 66, 17, 14, 14, 25, 17, 11, 19), },
+	{ DSIM_DPHY_TIMING(1510, 13, 66, 17, 13, 14, 24, 17, 11, 18), },
+	{ DSIM_DPHY_TIMING(1500, 13, 65, 17, 13, 14, 24, 16, 11, 18), },
+	{ DSIM_DPHY_TIMING(1490, 13, 65, 17, 13, 14, 24, 16, 11, 18), },
+	{ DSIM_DPHY_TIMING(1480, 13, 64, 17, 13, 14, 24, 16, 11, 18), },
+	{ DSIM_DPHY_TIMING(1470, 13, 64, 17, 13, 14, 24, 16, 11, 18), },
+	{ DSIM_DPHY_TIMING(1460, 13, 63, 17, 13, 13, 24, 16, 10, 18), },
+	{ DSIM_DPHY_TIMING(1450, 13, 63, 17, 13, 13, 23, 16, 10, 18), },
+	{ DSIM_DPHY_TIMING(1440, 13, 63, 17, 13, 13, 23, 16, 10, 18), },
+	{ DSIM_DPHY_TIMING(1430, 12, 62, 17, 13, 13, 23, 16, 10, 17), },
+	{ DSIM_DPHY_TIMING(1420, 12, 62, 17, 13, 13, 23, 16, 10, 17), },
+	{ DSIM_DPHY_TIMING(1410, 12, 61, 16, 13, 13, 23, 16, 10, 17), },
+	{ DSIM_DPHY_TIMING(1400, 12, 61, 16, 13, 13, 23, 16, 10, 17), },
+	{ DSIM_DPHY_TIMING(1390, 12, 60, 16, 12, 13, 22, 15, 10, 17), },
+	{ DSIM_DPHY_TIMING(1380, 12, 60, 16, 12, 13, 22, 15, 10, 17), },
+	{ DSIM_DPHY_TIMING(1370, 12, 59, 16, 12, 13, 22, 15, 10, 17), },
+	{ DSIM_DPHY_TIMING(1360, 12, 59, 16, 12, 13, 22, 15, 10, 17), },
+	{ DSIM_DPHY_TIMING(1350, 12, 59, 16, 12, 12, 22, 15, 10, 16), },
+	{ DSIM_DPHY_TIMING(1340, 12, 58, 16, 12, 12, 21, 15, 10, 16), },
+	{ DSIM_DPHY_TIMING(1330, 11, 58, 16, 12, 12, 21, 15,  9, 16), },
+	{ DSIM_DPHY_TIMING(1320, 11, 57, 16, 12, 12, 21, 15,  9, 16), },
+	{ DSIM_DPHY_TIMING(1310, 11, 57, 16, 12, 12, 21, 15,  9, 16), },
+	{ DSIM_DPHY_TIMING(1300, 11, 56, 16, 12, 12, 21, 15,  9, 16), },
+	{ DSIM_DPHY_TIMING(1290, 11, 56, 16, 12, 12, 21, 15,  9, 16), },
+	{ DSIM_DPHY_TIMING(1280, 11, 56, 15, 11, 12, 20, 14,  9, 16), },
+	{ DSIM_DPHY_TIMING(1270, 11, 55, 15, 11, 12, 20, 14,  9, 15), },
+	{ DSIM_DPHY_TIMING(1260, 11, 55, 15, 11, 12, 20, 14,  9, 15), },
+	{ DSIM_DPHY_TIMING(1250, 11, 54, 15, 11, 11, 20, 14,  9, 15), },
+	{ DSIM_DPHY_TIMING(1240, 11, 54, 15, 11, 11, 20, 14,  9, 15), },
+	{ DSIM_DPHY_TIMING(1230, 11, 53, 15, 11, 11, 19, 14,  9, 15), },
+	{ DSIM_DPHY_TIMING(1220, 10, 53, 15, 11, 11, 19, 14,  9, 15), },
+	{ DSIM_DPHY_TIMING(1210, 10, 52, 15, 11, 11, 19, 14,  9, 15), },
+	{ DSIM_DPHY_TIMING(1200, 10, 52, 15, 11, 11, 19, 14,  9, 15), },
+	{ DSIM_DPHY_TIMING(1190, 10, 52, 15, 11, 11, 19, 14,  8, 14), },
+	{ DSIM_DPHY_TIMING(1180, 10, 51, 15, 11, 11, 19, 13,  8, 14), },
+	{ DSIM_DPHY_TIMING(1170, 10, 51, 15, 10, 11, 18, 13,  8, 14), },
+	{ DSIM_DPHY_TIMING(1160, 10, 50, 15, 10, 11, 18, 13,  8, 14), },
+	{ DSIM_DPHY_TIMING(1150, 10, 50, 15, 10, 11, 18, 13,  8, 14), },
+	{ DSIM_DPHY_TIMING(1140, 10, 49, 14, 10, 10, 18, 13,  8, 14), },
+	{ DSIM_DPHY_TIMING(1130, 10, 49, 14, 10, 10, 18, 13,  8, 14), },
+	{ DSIM_DPHY_TIMING(1120, 10, 49, 14, 10, 10, 17, 13,  8, 14), },
+	{ DSIM_DPHY_TIMING(1110,  9, 48, 14, 10, 10, 17, 13,  8, 13), },
+	{ DSIM_DPHY_TIMING(1100,  9, 48, 14, 10, 10, 17, 13,  8, 13), },
+	{ DSIM_DPHY_TIMING(1090,  9, 47, 14, 10, 10, 17, 13,  8, 13), },
+	{ DSIM_DPHY_TIMING(1080,  9, 47, 14, 10, 10, 17, 13,  8, 13), },
+	{ DSIM_DPHY_TIMING(1070,  9, 46, 14, 10, 10, 17, 12,  8, 13), },
+	{ DSIM_DPHY_TIMING(1060,  9, 46, 14, 10, 10, 16, 12,  7, 13), },
+	{ DSIM_DPHY_TIMING(1050,  9, 45, 14,  9, 10, 16, 12,  7, 13), },
+	{ DSIM_DPHY_TIMING(1040,  9, 45, 14,  9, 10, 16, 12,  7, 13), },
+	{ DSIM_DPHY_TIMING(1030,  9, 45, 14,  9,  9, 16, 12,  7, 12), },
+	{ DSIM_DPHY_TIMING(1020,  9, 44, 14,  9,  9, 16, 12,  7, 12), },
+	{ DSIM_DPHY_TIMING(1010,  8, 44, 13,  9,  9, 15, 12,  7, 12), },
+	{ DSIM_DPHY_TIMING(1000,  8, 43, 13,  9,  9, 15, 12,  7, 12), },
+	{ DSIM_DPHY_TIMING( 990,  8, 43, 13,  9,  9, 15, 12,  7, 12), },
+	{ DSIM_DPHY_TIMING( 980,  8, 42, 13,  9,  9, 15, 12,  7, 12), },
+	{ DSIM_DPHY_TIMING( 970,  8, 42, 13,  9,  9, 15, 12,  7, 12), },
+	{ DSIM_DPHY_TIMING( 960,  8, 42, 13,  9,  9, 15, 11,  7, 12), },
+	{ DSIM_DPHY_TIMING( 950,  8, 41, 13,  9,  9, 14, 11,  7, 11), },
+	{ DSIM_DPHY_TIMING( 940,  8, 41, 13,  8,  9, 14, 11,  7, 11), },
+	{ DSIM_DPHY_TIMING( 930,  8, 40, 13,  8,  8, 14, 11,  6, 11), },
+	{ DSIM_DPHY_TIMING( 920,  8, 40, 13,  8,  8, 14, 11,  6, 11), },
+	{ DSIM_DPHY_TIMING( 910,  8, 39, 13,  8,  8, 14, 11,  6, 11), },
+	{ DSIM_DPHY_TIMING( 900,  7, 39, 13,  8,  8, 13, 11,  6, 11), },
+	{ DSIM_DPHY_TIMING( 890,  7, 38, 13,  8,  8, 13, 11,  6, 11), },
+	{ DSIM_DPHY_TIMING( 880,  7, 38, 12,  8,  8, 13, 11,  6, 11), },
+	{ DSIM_DPHY_TIMING( 870,  7, 38, 12,  8,  8, 13, 11,  6, 10), },
+	{ DSIM_DPHY_TIMING( 860,  7, 37, 12,  8,  8, 13, 11,  6, 10), },
+	{ DSIM_DPHY_TIMING( 850,  7, 37, 12,  8,  8, 13, 10,  6, 10), },
+	{ DSIM_DPHY_TIMING( 840,  7, 36, 12,  8,  8, 12, 10,  6, 10), },
+	{ DSIM_DPHY_TIMING( 830,  7, 36, 12,  8,  8, 12, 10,  6, 10), },
+	{ DSIM_DPHY_TIMING( 820,  7, 35, 12,  7,  7, 12, 10,  6, 10), },
+	{ DSIM_DPHY_TIMING( 810,  7, 35, 12,  7,  7, 12, 10,  6, 10), },
+	{ DSIM_DPHY_TIMING( 800,  7, 35, 12,  7,  7, 12, 10,  6, 10), },
+	{ DSIM_DPHY_TIMING( 790,  6, 34, 12,  7,  7, 11, 10,  5,  9), },
+	{ DSIM_DPHY_TIMING( 780,  6, 34, 12,  7,  7, 11, 10,  5,  9), },
+	{ DSIM_DPHY_TIMING( 770,  6, 33, 12,  7,  7, 11, 10,  5,  9), },
+	{ DSIM_DPHY_TIMING( 760,  6, 33, 12,  7,  7, 11, 10,  5,  9), },
+	{ DSIM_DPHY_TIMING( 750,  6, 32, 12,  7,  7, 11,  9,  5,  9), },
+	{ DSIM_DPHY_TIMING( 740,  6, 32, 11,  7,  7, 11,  9,  5,  9), },
+	{ DSIM_DPHY_TIMING( 730,  6, 31, 11,  7,  7, 10,  9,  5,  9), },
+	{ DSIM_DPHY_TIMING( 720,  6, 31, 11,  7,  6, 10,  9,  5,  9), },
+	{ DSIM_DPHY_TIMING( 710,  6, 31, 11,  6,  6, 10,  9,  5,  8), },
+	{ DSIM_DPHY_TIMING( 700,  6, 30, 11,  6,  6, 10,  9,  5,  8), },
+	{ DSIM_DPHY_TIMING( 690,  5, 30, 11,  6,  6, 10,  9,  5,  8), },
+	{ DSIM_DPHY_TIMING( 680,  5, 29, 11,  6,  6,  9,  9,  5,  8), },
+	{ DSIM_DPHY_TIMING( 670,  5, 29, 11,  6,  6,  9,  9,  5,  8), },
+	{ DSIM_DPHY_TIMING( 660,  5, 28, 11,  6,  6,  9,  9,  4,  8), },
+	{ DSIM_DPHY_TIMING( 650,  5, 28, 11,  6,  6,  9,  9,  4,  8), },
+	{ DSIM_DPHY_TIMING( 640,  5, 28, 11,  6,  6,  9,  8,  4,  8), },
+	{ DSIM_DPHY_TIMING( 630,  5, 27, 11,  6,  6,  9,  8,  4,  7), },
+	{ DSIM_DPHY_TIMING( 620,  5, 27, 11,  6,  6,  8,  8,  4,  7), },
+	{ DSIM_DPHY_TIMING( 610,  5, 26, 10,  6,  5,  8,  8,  4,  7), },
+	{ DSIM_DPHY_TIMING( 600,  5, 26, 10,  6,  5,  8,  8,  4,  7), },
+	{ DSIM_DPHY_TIMING( 590,  5, 25, 10,  5,  5,  8,  8,  4,  7), },
+	{ DSIM_DPHY_TIMING( 580,  4, 25, 10,  5,  5,  8,  8,  4,  7), },
+	{ DSIM_DPHY_TIMING( 570,  4, 24, 10,  5,  5,  7,  8,  4,  7), },
+	{ DSIM_DPHY_TIMING( 560,  4, 24, 10,  5,  5,  7,  8,  4,  7), },
+	{ DSIM_DPHY_TIMING( 550,  4, 24, 10,  5,  5,  7,  8,  4,  6), },
+	{ DSIM_DPHY_TIMING( 540,  4, 23, 10,  5,  5,  7,  8,  4,  6), },
+	{ DSIM_DPHY_TIMING( 530,  4, 23, 10,  5,  5,  7,  7,  3,  6), },
+	{ DSIM_DPHY_TIMING( 520,  4, 22, 10,  5,  5,  7,  7,  3,  6), },
+	{ DSIM_DPHY_TIMING( 510,  4, 22, 10,  5,  5,  6,  7,  3,  6), },
+	{ DSIM_DPHY_TIMING( 500,  4, 21, 10,  5,  4,  6,  7,  3,  6), },
+	{ DSIM_DPHY_TIMING( 490,  4, 21, 10,  5,  4,  6,  7,  3,  6), },
+	{ DSIM_DPHY_TIMING( 480,  4, 21,  9,  4,  4,  6,  7,  3,  6), },
+	{ DSIM_DPHY_TIMING( 470,  3, 20,  9,  4,  4,  6,  7,  3,  5), },
+	{ DSIM_DPHY_TIMING( 460,  3, 20,  9,  4,  4,  5,  7,  3,  5), },
+	{ DSIM_DPHY_TIMING( 450,  3, 19,  9,  4,  4,  5,  7,  3,  5), },
+	{ DSIM_DPHY_TIMING( 440,  3, 19,  9,  4,  4,  5,  7,  3,  5), },
+	{ DSIM_DPHY_TIMING( 430,  3, 18,  9,  4,  4,  5,  7,  3,  5), },
+	{ DSIM_DPHY_TIMING( 420,  3, 18,  9,  4,  4,  5,  6,  3,  5), },
+	{ DSIM_DPHY_TIMING( 410,  3, 17,  9,  4,  4,  5,  6,  3,  5), },
+	{ DSIM_DPHY_TIMING( 400,  3, 17,  9,  4,  3,  4,  6,  3,  5), },
+	{ DSIM_DPHY_TIMING( 390,  3, 17,  9,  4,  3,  4,  6,  2,  4), },
+	{ DSIM_DPHY_TIMING( 380,  3, 16,  9,  4,  3,  4,  6,  2,  4), },
+	{ DSIM_DPHY_TIMING( 370,  2, 16,  9,  3,  3,  4,  6,  2,  4), },
+	{ DSIM_DPHY_TIMING( 360,  2, 15,  9,  3,  3,  4,  6,  2,  4), },
+	{ DSIM_DPHY_TIMING( 350,  2, 15,  9,  3,  3,  3,  6,  2,  4), },
+	{ DSIM_DPHY_TIMING( 340,  2, 14,  8,  3,  3,  3,  6,  2,  4), },
+	{ DSIM_DPHY_TIMING( 330,  2, 14,  8,  3,  3,  3,  6,  2,  4), },
+	{ DSIM_DPHY_TIMING( 320,  2, 14,  8,  3,  3,  3,  5,  2,  4), },
+	{ DSIM_DPHY_TIMING( 310,  2, 13,  8,  3,  3,  3,  5,  2,  3), },
+	{ DSIM_DPHY_TIMING( 300,  2, 13,  8,  3,  3,  3,  5,  2,  3), },
+	{ DSIM_DPHY_TIMING( 290,  2, 12,  8,  3,  2,  2,  5,  2,  3), },
+	{ DSIM_DPHY_TIMING( 280,  2, 12,  8,  3,  2,  2,  5,  2,  3), },
+	{ DSIM_DPHY_TIMING( 270,  2, 11,  8,  3,  2,  2,  5,  2,  3), },
+	{ DSIM_DPHY_TIMING( 260,  1, 11,  8,  3,  2,  2,  5,  1,  3), },
+	{ DSIM_DPHY_TIMING( 250,  1, 10,  8,  2,  2,  2,  5,  1,  3), },
+	{ DSIM_DPHY_TIMING( 240,  1,  9,  8,  2,  2,  1,  5,  1,  3), },
+	{ DSIM_DPHY_TIMING( 230,  1,  8,  8,  2,  2,  1,  5,  1,  2), },
+	{ DSIM_DPHY_TIMING( 220,  1,  8,  8,  2,  2,  1,  5,  1,  2), },
+	{ DSIM_DPHY_TIMING( 210,  1,  7,  7,  2,  2,  1,  4,  1,  2), },
+	{ DSIM_DPHY_TIMING( 200,  1,  7,  7,  2,  2,  1,  4,  1,  2), },
+	{ DSIM_DPHY_TIMING( 190,  1,  7,  7,  2,  1,  1,  4,  1,  2), },
+	{ DSIM_DPHY_TIMING( 180,  1,  6,  7,  2,  1,  0,  4,  1,  2), },
+	{ DSIM_DPHY_TIMING( 170,  1,  6,  7,  2,  1,  0,  4,  1,  2), },
+	{ DSIM_DPHY_TIMING( 160,  1,  6,  7,  2,  1,  0,  4,  1,  2), },
+	{ DSIM_DPHY_TIMING( 150,  0,  5,  7,  2,  1,  0,  4,  1,  1), },
+	{ DSIM_DPHY_TIMING( 140,  0,  5,  7,  1,  1,  0,  4,  1,  1), },
+	{ DSIM_DPHY_TIMING( 130,  0,  4,  7,  1,  1,  0,  4,  0,  1), },
+	{ DSIM_DPHY_TIMING( 120,  0,  4,  7,  1,  1,  0,  4,  0,  1), },
+	{ DSIM_DPHY_TIMING( 110,  0,  3,  7,  1,  0,  0,  4,  0,  1), },
+	{ DSIM_DPHY_TIMING( 100,  0,  3,  7,  1,  0,  0,  3,  0,  1), },
+	{ DSIM_DPHY_TIMING(  90,  0,  2,  7,  1,  0,  0,  3,  0,  1), },
+	{ DSIM_DPHY_TIMING(  80,  0,  2,  6,  1,  0,  0,  3,  0,  1), },
+};
+
+static inline int dphy_timing_default_cmp(const void *key, const void *elt)
+{
+	const struct sec_mipi_dsim_dphy_timing *_key = key;
+	const struct sec_mipi_dsim_dphy_timing *_elt = elt;
+
+	/* find an element whose 'bit_clk' is equal to the
+	 * the key's 'bit_clk' value or, the difference
+	 * between them is less than 5.
+	 */
+	if (abs((int)(_elt->bit_clk - _key->bit_clk)) <= 5)
+		return 0;
+
+	if (_key->bit_clk < _elt->bit_clk)
+		/* search bottom half */
+		return 1;
+	else
+		/* search top half */
+		return -1;
+}
+
+static const struct sec_mipi_dsim_dphy_timing *dphy_timing_search(int start, int size,
+	struct sec_mipi_dsim_dphy_timing *key)
+{
+	int ret;
+
+	if (size == 0)
+		return NULL;
+
+	ret = dphy_timing_default_cmp(key, &dphy_timing[start + (size >> 1)]);
+	if (ret == -1)
+		return dphy_timing_search(start, size >> 1, key);
+	else if (ret == 1)
+		return dphy_timing_search(start + (size >> 1) + 1, size - 1 - (size >> 1), key);
+	else
+		return &dphy_timing[start + (size >> 1)];
+}
+
+static int sec_mipi_dsim_wait_for_pkt_done(struct sec_mipi_dsim *dsim, unsigned long timeout)
+{
+	uint32_t intsrc;
+
+	do {
+		intsrc = dsim_read(dsim, DSIM_INTSRC);
+		if (intsrc & INTSRC_SFRPLFIFOEMPTY) {
+			dsim_write(dsim, INTSRC_SFRPLFIFOEMPTY, DSIM_INTSRC);
+			return 0;
+		}
+
+		udelay(1);
+	} while (--timeout);
+
+	return -ETIMEDOUT;
+}
+
+static int sec_mipi_dsim_wait_for_hdr_done(struct sec_mipi_dsim *dsim, unsigned long timeout)
+{
+	uint32_t intsrc;
+
+	do {
+		intsrc = dsim_read(dsim, DSIM_INTSRC);
+		if (intsrc & INTSRC_SFRPHFIFOEMPTY) {
+			dsim_write(dsim, INTSRC_SFRPHFIFOEMPTY, DSIM_INTSRC);
+			return 0;
+		}
+
+		udelay(1);
+	} while (--timeout);
+
+	return -ETIMEDOUT;
+}
+
+
+static int sec_mipi_dsim_wait_for_rx_done(struct sec_mipi_dsim *dsim, unsigned long timeout)
+{
+	uint32_t intsrc;
+
+	do {
+		intsrc = dsim_read(dsim, DSIM_INTSRC);
+		if (intsrc & INTSRC_RXDATDONE) {
+			dsim_write(dsim, INTSRC_RXDATDONE, DSIM_INTSRC);
+			return 0;
+		}
+
+		udelay(1);
+	} while (--timeout);
+
+	return -ETIMEDOUT;
+}
+
+static int sec_mipi_dsim_wait_pll_stable(struct sec_mipi_dsim *dsim)
+{
+	uint32_t status;
+	ulong start;
+
+	start = get_timer(0);	/* Get current timestamp */
+
+	do {
+		status = dsim_read(dsim, DSIM_STATUS);
+		if (status & STATUS_PLLSTABLE)
+			return 0;
+	} while (get_timer(0) < (start + 100)); /* Wait 100ms */
+
+	return -ETIMEDOUT;
+}
+
+static int sec_mipi_dsim_calc_pmsk(struct sec_mipi_dsim *dsim)
+{
+	uint32_t p, m, s;
+	uint32_t best_p = 0, best_m = 0, best_s = 0;
+	uint32_t fin, fout;
+	uint32_t s_pow_2, raw_s;
+	uint64_t mfin, pfvco, pfout, psfout;
+	uint32_t delta, best_delta = ~0U;
+	struct sec_mipi_dsim_range prange = { .min = 1,       .max = 63,  };
+	struct sec_mipi_dsim_range mrange = { .min = 64,      .max = 1023,  };
+	struct sec_mipi_dsim_range srange = { .min = 0,       .max = 5,  };
+	struct sec_mipi_dsim_range krange = { .min = 0,       .max = 32768,  };
+	struct sec_mipi_dsim_range fvco_range  = { .min = 1050000,    .max = 2100000,  };
+	struct sec_mipi_dsim_range fpref_range = { .min = 2000,       .max = 30000,  };
+	struct sec_mipi_dsim_range pr_new = prange;
+	struct sec_mipi_dsim_range sr_new = srange;
+
+	fout = dsim->bit_clk;
+	fin  = get_dsi_phy_ref_clk();
+	fin = DIV_ROUND_UP_ULL(fin, 1000); /* Change to Khz */
+	if (fin == 0) {
+		printf("Error: DSI PHY reference clock is disabled\n");
+		return -EINVAL;
+	}
+
+	/* TODO: ignore 'k' for PMS calculation,
+	 * only use 'p', 'm' and 's' to generate
+	 * the requested PLL output clock.
+	 */
+	krange.min = 0;
+	krange.max = 0;
+
+	/* narrow 'p' range via 'Fpref' limitation:
+	 * Fpref : [2MHz ~ 30MHz] (Fpref = Fin / p)
+	 */
+	prange.min = max(prange.min, DIV_ROUND_UP(fin, fpref_range.max));
+	prange.max = min(prange.max, fin / fpref_range.min);
+
+	/* narrow 'm' range via 'Fvco' limitation:
+	 * Fvco: [1050MHz ~ 2100MHz] (Fvco = ((m + k / 65536) * Fin) / p)
+	 * So, m = Fvco * p / Fin and Fvco > Fin;
+	 */
+	pfvco = (uint64_t)fvco_range.min * prange.min;
+	mrange.min = max_t(uint32_t, mrange.min,
+			    DIV_ROUND_UP_ULL(pfvco, fin));
+	pfvco = (uint64_t)fvco_range.max * prange.max;
+	mrange.max = min_t(uint32_t, mrange.max,
+			    DIV_ROUND_UP_ULL(pfvco, fin));
+
+	debug("p: min = %u, max = %u, "
+		     "m: min = %u, max = %u, "
+		     "s: min = %u, max = %u\n",
+		prange.min, prange.max, mrange.min,
+		mrange.max, srange.min, srange.max);
+
+	/* first determine 'm', then can determine 'p', last determine 's' */
+	for (m = mrange.min; m <= mrange.max; m++) {
+		/* p = m * Fin / Fvco */
+		mfin = (uint64_t)m * fin;
+		pr_new.min = max_t(uint32_t, prange.min,
+				   DIV_ROUND_UP_ULL(mfin, fvco_range.max));
+		pr_new.max = min_t(uint32_t, prange.max,
+				   (mfin / fvco_range.min));
+
+		if (pr_new.max < pr_new.min || pr_new.min < prange.min)
+			continue;
+
+		for (p = pr_new.min; p <= pr_new.max; p++) {
+			/* s = order_pow_of_two((m * Fin) / (p * Fout)) */
+			pfout = (uint64_t)p * fout;
+			raw_s = DIV_ROUND_CLOSEST_ULL(mfin, pfout);
+
+			s_pow_2 = rounddown_pow_of_two(raw_s);
+			sr_new.min = max_t(uint32_t, srange.min,
+					   order_base_2(s_pow_2));
+
+			s_pow_2 = roundup_pow_of_two(DIV_ROUND_CLOSEST_ULL(mfin, pfout));
+			sr_new.max = min_t(uint32_t, srange.max,
+					   order_base_2(s_pow_2));
+
+			if (sr_new.max < sr_new.min || sr_new.min < srange.min)
+				continue;
+
+			for (s = sr_new.min; s <= sr_new.max; s++) {
+				/* fout = m * Fin / (p * 2^s) */
+				psfout = pfout * (1 << s);
+				delta = abs(psfout - mfin);
+				if (delta < best_delta) {
+					best_p = p;
+					best_m = m;
+					best_s = s;
+					best_delta = delta;
+				}
+			}
+		}
+	}
+
+	if (best_delta == ~0U) {
+		return -EINVAL;
+	}
+
+	dsim->p = best_p;
+	dsim->m = best_m;
+	dsim->s = best_s;
+
+	debug("fout = %u, fin = %u, m = %u, "
+		     "p = %u, s = %u, best_delta = %u\n",
+		fout, fin, dsim->m, dsim->p, dsim->s, best_delta);
+
+	return 0;
+}
+
+
+static int sec_mipi_dsim_config_pll(struct sec_mipi_dsim *dsim)
+{
+	int ret;
+	uint32_t pllctrl = 0, status, data_lanes_en, stop;
+
+	dsim_write(dsim, 0x8000, DSIM_PLLTMR);
+
+	/* TODO: config dp/dn swap if requires */
+
+	pllctrl |= PLLCTRL_SET_PMS(dsim->pms) | PLLCTRL_PLLEN;
+	dsim_write(dsim, pllctrl, DSIM_PLLCTRL);
+
+	ret = sec_mipi_dsim_wait_pll_stable(dsim);
+	if (ret) {
+		printf("wait for pll stable time out\n");
+		return ret;
+	}
+
+	/* wait for clk & data lanes to go to stop state */
+	mdelay(1);
+
+	data_lanes_en = (0x1 << dsim->lanes) - 1;
+	status = dsim_read(dsim, DSIM_STATUS);
+	if (!(status & STATUS_STOPSTATECLK)) {
+		printf("clock is not in stop state\n");
+		return -EBUSY;
+	}
+
+	stop = STATUS_GET_STOPSTATEDAT(status);
+	if ((stop & data_lanes_en) != data_lanes_en) {
+		printf("one or more data lanes is not in stop state\n");
+		return -EBUSY;
+	}
+
+	return 0;
+}
+
+static void sec_mipi_dsim_set_main_mode(struct sec_mipi_dsim *dsim)
+{
+	uint32_t bpp, hfp_wc, hbp_wc, hsa_wc, wc;
+	uint32_t mdresol = 0, mvporch = 0, mhporch = 0, msync = 0;
+	struct display_timing *timings = &dsim->timings;
+
+	mdresol |= MDRESOL_SET_MAINVRESOL(timings->vactive.typ) |
+		   MDRESOL_SET_MAINHRESOL(timings->hactive.typ);
+	dsim_write(dsim, mdresol, DSIM_MDRESOL);
+
+	mvporch |= MVPORCH_SET_MAINVBP(timings->vback_porch.typ)    |
+		   MVPORCH_SET_STABLEVFP(timings->vfront_porch.typ) |
+		   MVPORCH_SET_CMDALLOW(0x0);
+	dsim_write(dsim, mvporch, DSIM_MVPORCH);
+
+	bpp = mipi_dsi_pixel_format_to_bpp(dsim->format);
+
+
+	wc = DIV_ROUND_UP(timings->hfront_porch.typ* (bpp >> 3),
+		dsim->lanes);
+	hfp_wc = wc > MIPI_HFP_PKT_OVERHEAD ?
+		wc - MIPI_HFP_PKT_OVERHEAD : timings->hfront_porch.typ;
+	wc = DIV_ROUND_UP(timings->hback_porch.typ * (bpp >> 3),
+		dsim->lanes);
+	hbp_wc = wc > MIPI_HBP_PKT_OVERHEAD ?
+		wc - MIPI_HBP_PKT_OVERHEAD : timings->hback_porch.typ;
+
+	mhporch |= MHPORCH_SET_MAINHFP(hfp_wc) |
+		   MHPORCH_SET_MAINHBP(hbp_wc);
+
+	dsim_write(dsim, mhporch, DSIM_MHPORCH);
+
+	wc = DIV_ROUND_UP(timings->hsync_len.typ * (bpp >> 3),
+		dsim->lanes);
+	hsa_wc = wc > MIPI_HSA_PKT_OVERHEAD ?
+		wc - MIPI_HSA_PKT_OVERHEAD : timings->hsync_len.typ;
+
+	msync |= MSYNC_SET_MAINVSA(timings->vsync_len.typ) |
+		 MSYNC_SET_MAINHSA(hsa_wc);
+
+	debug("hfp_wc %u hbp_wc %u hsa_wc %u\n", hfp_wc, hbp_wc, hsa_wc);
+
+	dsim_write(dsim, msync, DSIM_MSYNC);
+}
+
+static void sec_mipi_dsim_config_dpi(struct sec_mipi_dsim *dsim)
+{
+	uint32_t config = 0, rgb_status = 0, data_lanes_en;
+
+	if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO)
+		rgb_status &= ~RGB_STATUS_CMDMODE_INSEL;
+	else
+		rgb_status |= RGB_STATUS_CMDMODE_INSEL;
+
+	dsim_write(dsim, rgb_status, DSIM_RGB_STATUS);
+
+	if (dsim->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
+		config |= CONFIG_CLKLANE_STOP_START;
+
+	if (dsim->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)
+		config |= CONFIG_MFLUSH_VS;
+
+	/* disable EoT packets in HS mode */
+	if (dsim->mode_flags & MIPI_DSI_MODE_EOT_PACKET)
+		config |= CONFIG_EOT_R03;
+
+	if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO) {
+		config |= CONFIG_VIDEOMODE;
+
+		if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
+			config |= CONFIG_BURSTMODE;
+
+		else if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
+			config |= CONFIG_SYNCINFORM;
+
+		if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
+			config |= CONFIG_AUTOMODE;
+
+		if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
+			config |= CONFIG_HSEDISABLEMODE;
+
+		if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HFP)
+			config |= CONFIG_HFPDISABLEMODE;
+
+		if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HBP)
+			config |= CONFIG_HBPDISABLEMODE;
+
+		if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HSA)
+			config |= CONFIG_HSADISABLEMODE;
+	}
+
+	config |= CONFIG_SET_MAINVC(dsim->channel);
+
+	if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO) {
+		switch (dsim->format) {
+		case MIPI_DSI_FMT_RGB565:
+			config |= CONFIG_SET_MAINPIXFORMAT(0x4);
+			break;
+		case MIPI_DSI_FMT_RGB666_PACKED:
+			config |= CONFIG_SET_MAINPIXFORMAT(0x5);
+			break;
+		case MIPI_DSI_FMT_RGB666:
+			config |= CONFIG_SET_MAINPIXFORMAT(0x6);
+			break;
+		case MIPI_DSI_FMT_RGB888:
+			config |= CONFIG_SET_MAINPIXFORMAT(0x7);
+			break;
+		default:
+			config |= CONFIG_SET_MAINPIXFORMAT(0x7);
+			break;
+		}
+	}
+
+	/* config data lanes number and enable lanes */
+	data_lanes_en = (0x1 << dsim->lanes) - 1;
+	config |= CONFIG_SET_NUMOFDATLANE(dsim->lanes - 1);
+	config |= CONFIG_SET_LANEEN(0x1 | data_lanes_en << 1);
+
+	debug("DSIM config 0x%x\n", config);
+
+	dsim_write(dsim, config, DSIM_CONFIG);
+}
+
+static void sec_mipi_dsim_config_cmd_lpm(struct sec_mipi_dsim *dsim,
+					 bool enable)
+{
+	uint32_t escmode;
+
+	escmode = dsim_read(dsim, DSIM_ESCMODE);
+
+	if (enable)
+		escmode |= ESCMODE_CMDLPDT;
+	else
+		escmode &= ~ESCMODE_CMDLPDT;
+
+	dsim_write(dsim, escmode, DSIM_ESCMODE);
+}
+
+static void sec_mipi_dsim_config_dphy(struct sec_mipi_dsim *dsim)
+{
+	uint32_t phytiming = 0, phytiming1 = 0, phytiming2 = 0, timeout = 0;
+	struct sec_mipi_dsim_dphy_timing key = { 0 };
+	const struct sec_mipi_dsim_dphy_timing *match = NULL;
+
+	key.bit_clk = DIV_ROUND_CLOSEST_ULL(dsim->bit_clk, 1000);
+
+	match = dphy_timing_search(0, ARRAY_SIZE(dphy_timing), &key);
+	if (!match) {
+		printf("Fail to find DPHY timing for %uMhz\n", key.bit_clk);
+		return;
+	}
+
+	phytiming  |= PHYTIMING_SET_M_TLPXCTL(match->lpx)	|
+		      PHYTIMING_SET_M_THSEXITCTL(match->hs_exit);
+	dsim_write(dsim, phytiming, DSIM_PHYTIMING);
+
+	phytiming1 |= PHYTIMING1_SET_M_TCLKPRPRCTL(match->clk_prepare)	|
+		      PHYTIMING1_SET_M_TCLKZEROCTL(match->clk_zero)	|
+		      PHYTIMING1_SET_M_TCLKPOSTCTL(match->clk_post)	|
+		      PHYTIMING1_SET_M_TCLKTRAILCTL(match->clk_trail);
+	dsim_write(dsim, phytiming1, DSIM_PHYTIMING1);
+
+	phytiming2 |= PHYTIMING2_SET_M_THSPRPRCTL(match->hs_prepare)	|
+		      PHYTIMING2_SET_M_THSZEROCTL(match->hs_zero)	|
+		      PHYTIMING2_SET_M_THSTRAILCTL(match->hs_trail);
+	dsim_write(dsim, phytiming2, DSIM_PHYTIMING2);
+
+	timeout |= TIMEOUT_SET_BTAOUT(0xff)	|
+		   TIMEOUT_SET_LPDRTOUT(0xff);
+	dsim_write(dsim, timeout, DSIM_TIMEOUT);
+}
+
+static void sec_mipi_dsim_write_pl_to_sfr_fifo(struct sec_mipi_dsim *dsim,
+					       const void *payload,
+					       size_t length)
+{
+	uint32_t pl_data;
+
+	if (!length)
+		return;
+
+	while (length >= 4) {
+		pl_data = get_unaligned_le32(payload);
+		dsim_write(dsim, pl_data, DSIM_PAYLOAD);
+		payload += 4;
+		length -= 4;
+	}
+
+	pl_data = 0;
+	switch (length) {
+	case 3:
+		pl_data |= ((u8 *)payload)[2] << 16;
+	case 2:
+		pl_data |= ((u8 *)payload)[1] << 8;
+	case 1:
+		pl_data |= ((u8 *)payload)[0];
+		dsim_write(dsim, pl_data, DSIM_PAYLOAD);
+		break;
+	}
+}
+
+static void sec_mipi_dsim_write_ph_to_sfr_fifo(struct sec_mipi_dsim *dsim,
+					       void *header,
+					       bool use_lpm)
+{
+	uint32_t pkthdr;
+
+	pkthdr = PKTHDR_SET_DATA1(((u8 *)header)[2])	| /* WC MSB  */
+		 PKTHDR_SET_DATA0(((u8 *)header)[1])	| /* WC LSB  */
+		 PKTHDR_SET_DI(((u8 *)header)[0]);	  /* Data ID */
+
+	dsim_write(dsim, pkthdr, DSIM_PKTHDR);
+}
+
+static int sec_mipi_dsim_read_pl_from_sfr_fifo(struct sec_mipi_dsim *dsim,
+					       void *payload,
+					       size_t length)
+{
+	uint8_t data_type;
+	uint16_t word_count = 0;
+	uint32_t fifoctrl, ph, pl;
+
+	fifoctrl = dsim_read(dsim, DSIM_FIFOCTRL);
+
+	if (WARN_ON(fifoctrl & FIFOCTRL_EMPTYRX))
+		return -EINVAL;
+
+	ph = dsim_read(dsim, DSIM_RXFIFO);
+	data_type = PKTHDR_GET_DT(ph);
+	switch (data_type) {
+	case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
+		dev_err(dsim->device->dev, "peripheral report error: (0-7)%x, (8-15)%x\n",
+			PKTHDR_GET_DATA0(ph), PKTHDR_GET_DATA1(ph));
+		return -EPROTO;
+	case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
+	case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
+		if (!WARN_ON(length < 2)) {
+			((u8 *)payload)[1] = PKTHDR_GET_DATA1(ph);
+			word_count++;
+		}
+		/* fall through */
+	case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
+	case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
+		((u8 *)payload)[0] = PKTHDR_GET_DATA0(ph);
+		word_count++;
+		length = word_count;
+		break;
+	case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
+	case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
+		word_count = PKTHDR_GET_WC(ph);
+		if (word_count > length) {
+			dev_err(dsim->device->dev, "invalid receive buffer length\n");
+			return -EINVAL;
+		}
+
+		length = word_count;
+
+		while (word_count >= 4) {
+			pl = dsim_read(dsim, DSIM_RXFIFO);
+			((u8 *)payload)[0] = pl & 0xff;
+			((u8 *)payload)[1] = (pl >> 8)  & 0xff;
+			((u8 *)payload)[2] = (pl >> 16) & 0xff;
+			((u8 *)payload)[3] = (pl >> 24) & 0xff;
+			payload += 4;
+			word_count -= 4;
+		}
+
+		if (word_count > 0) {
+			pl = dsim_read(dsim, DSIM_RXFIFO);
+
+			switch (word_count) {
+			case 3:
+				((u8 *)payload)[2] = (pl >> 16) & 0xff;
+			case 2:
+				((u8 *)payload)[1] = (pl >> 8) & 0xff;
+			case 1:
+				((u8 *)payload)[0] = pl & 0xff;
+				break;
+			}
+		}
+
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return length;
+}
+
+static void sec_mipi_dsim_init_fifo_pointers(struct sec_mipi_dsim *dsim)
+{
+	uint32_t fifoctrl, fifo_ptrs;
+
+	fifoctrl = dsim_read(dsim, DSIM_FIFOCTRL);
+
+	fifo_ptrs = FIFOCTRL_NINITRX	|
+		    FIFOCTRL_NINITSFR	|
+		    FIFOCTRL_NINITI80	|
+		    FIFOCTRL_NINITSUB	|
+		    FIFOCTRL_NINITMAIN;
+
+	fifoctrl &= ~fifo_ptrs;
+	dsim_write(dsim, fifoctrl, DSIM_FIFOCTRL);
+	udelay(500);
+
+	fifoctrl |= fifo_ptrs;
+	dsim_write(dsim, fifoctrl, DSIM_FIFOCTRL);
+	udelay(500);
+}
+
+
+static void sec_mipi_dsim_config_clkctrl(struct sec_mipi_dsim *dsim)
+{
+	uint32_t clkctrl = 0, data_lanes_en;
+	uint64_t byte_clk, esc_prescaler;
+
+	clkctrl |= CLKCTRL_TXREQUESTHSCLK;
+
+	/* using 1.5Gbps PHY */
+	clkctrl |= CLKCTRL_DPHY_SEL_1P5G;
+
+	clkctrl |= CLKCTRL_ESCCLKEN;
+
+	clkctrl &= ~CLKCTRL_PLLBYPASS;
+
+	clkctrl |= CLKCTRL_BYTECLKSRC_DPHY_PLL;
+
+	clkctrl |= CLKCTRL_BYTECLKEN;
+
+	data_lanes_en = (0x1 << dsim->lanes) - 1;
+	clkctrl |= CLKCTRL_SET_LANEESCCLKEN(0x1 | data_lanes_en << 1);
+
+	/* calculate esc prescaler from byte clock:
+	 * EscClk = ByteClk / EscPrescaler;
+	 */
+	byte_clk = dsim->bit_clk >> 3;
+	esc_prescaler = DIV_ROUND_UP_ULL(byte_clk, MAX_ESC_CLK_FREQ);
+
+	clkctrl |= CLKCTRL_SET_ESCPRESCALER(esc_prescaler);
+
+	debug("DSIM clkctrl 0x%x\n", clkctrl);
+
+	dsim_write(dsim, clkctrl, DSIM_CLKCTRL);
+}
+
+static void sec_mipi_dsim_set_standby(struct sec_mipi_dsim *dsim,
+				      bool standby)
+{
+	uint32_t mdresol = 0;
+
+	mdresol = dsim_read(dsim, DSIM_MDRESOL);
+
+	if (standby)
+		mdresol |= MDRESOL_MAINSTANDBY;
+	else
+		mdresol &= ~MDRESOL_MAINSTANDBY;
+
+	dsim_write(dsim, mdresol, DSIM_MDRESOL);
+}
+
+static void sec_mipi_dsim_disable_clkctrl(struct sec_mipi_dsim *dsim)
+{
+	uint32_t clkctrl;
+
+	clkctrl = dsim_read(dsim, DSIM_CLKCTRL);
+
+	clkctrl &= ~CLKCTRL_TXREQUESTHSCLK;
+
+	clkctrl &= ~CLKCTRL_ESCCLKEN;
+
+	clkctrl &= ~CLKCTRL_BYTECLKEN;
+
+	dsim_write(dsim, clkctrl, DSIM_CLKCTRL);
+}
+
+static void sec_mipi_dsim_disable_pll(struct sec_mipi_dsim *dsim)
+{
+	uint32_t pllctrl;
+
+	pllctrl  = dsim_read(dsim, DSIM_PLLCTRL);
+
+	pllctrl &= ~PLLCTRL_PLLEN;
+
+	dsim_write(dsim, pllctrl, DSIM_PLLCTRL);
+}
+
+static inline struct sec_mipi_dsim *host_to_dsi(struct mipi_dsi_host *host)
+{
+	return container_of(host, struct sec_mipi_dsim, dsi_host);
+}
+
+static int sec_mipi_dsim_bridge_clk_set(struct sec_mipi_dsim *dsim_host)
+{
+	int bpp, ret;
+	uint64_t pix_clk, bit_clk;
+
+	bpp = mipi_dsi_pixel_format_to_bpp(dsim_host->format);
+	if (bpp < 0)
+		return -EINVAL;
+
+	pix_clk = dsim_host->timings.pixelclock.typ;
+	bit_clk = DIV_ROUND_UP_ULL(pix_clk * bpp, dsim_host->lanes);
+
+#if 0
+	if (bit_clk > dsim_host->max_data_rate) {
+		printf("request bit clk freq exceeds lane's maximum value\n");
+		return -EINVAL;
+	}
+#endif
+
+	dsim_host->pix_clk = DIV_ROUND_UP_ULL(pix_clk, 1000);
+	dsim_host->bit_clk = DIV_ROUND_UP_ULL(bit_clk, 1000);
+
+	ret = sec_mipi_dsim_calc_pmsk(dsim_host);
+	if (ret) {
+		printf("failed to get pmsk for: fout = %llu\n",
+			dsim_host->bit_clk);
+		return -EINVAL;
+	}
+
+	dsim_host->pms = PLLCTRL_SET_P(dsim_host->p) |
+		    PLLCTRL_SET_M(dsim_host->m) |
+		    PLLCTRL_SET_S(dsim_host->s);
+
+	debug("%s: bitclk %llu pixclk %llu pms 0x%x\n", __func__,
+		dsim_host->bit_clk, dsim_host->pix_clk, dsim_host->pms);
+
+	return 0;
+}
+
+static int sec_mipi_dsim_bridge_prepare(struct sec_mipi_dsim *dsim_host)
+{
+	int ret;
+
+	/* At this moment, the dsim bridge's preceding encoder has
+	 * already been enabled. So the dsim can be configed here
+	 */
+
+	/* config main display mode */
+	sec_mipi_dsim_set_main_mode(dsim_host);
+
+	/* config dsim dpi */
+	sec_mipi_dsim_config_dpi(dsim_host);
+
+	/* config dsim pll */
+	ret = sec_mipi_dsim_config_pll(dsim_host);
+	if (ret) {
+		printf("dsim pll config failed: %d\n", ret);
+		return ret;
+	}
+
+	/* config dphy timings */
+	sec_mipi_dsim_config_dphy(dsim_host);
+
+	sec_mipi_dsim_init_fifo_pointers(dsim_host);
+
+	/* config esc clock, byte clock and etc */
+	sec_mipi_dsim_config_clkctrl(dsim_host);
+
+	/* enable data transfer of dsim */
+	sec_mipi_dsim_set_standby(dsim_host, true);
+
+	return 0;
+}
+
+static int sec_mipi_dsim_host_attach(struct mipi_dsi_host *host,
+				   struct mipi_dsi_device *device)
+{
+	struct sec_mipi_dsim *dsi = host_to_dsi(host);
+
+	if (!device->lanes || device->lanes > dsi->max_data_lanes) {
+		printf("invalid data lanes number\n");
+		return -EINVAL;
+	}
+
+	if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)		||
+	    !((device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)	||
+	      (device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))) {
+		printf("unsupported dsi mode\n");
+		return -EINVAL;
+	}
+
+	if (device->format != MIPI_DSI_FMT_RGB888 &&
+	    device->format != MIPI_DSI_FMT_RGB565 &&
+	    device->format != MIPI_DSI_FMT_RGB666 &&
+	    device->format != MIPI_DSI_FMT_RGB666_PACKED) {
+		printf("unsupported pixel format: %#x\n", device->format);
+		return -EINVAL;
+	}
+
+	dsi->lanes	 = device->lanes;
+	dsi->channel	 = device->channel;
+	dsi->format	 = device->format;
+	dsi->mode_flags = device->mode_flags;
+
+	debug("lanes %u, channel %u, format 0x%x, mode_flags 0x%lx\n", dsi->lanes,
+		dsi->channel, dsi->format, dsi->mode_flags);
+
+	sec_mipi_dsim_bridge_clk_set(dsi);
+	sec_mipi_dsim_bridge_prepare(dsi);
+
+	return 0;
+}
+
+static ssize_t sec_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
+					 const struct mipi_dsi_msg *msg)
+{
+	struct sec_mipi_dsim *dsim = host_to_dsi(host);
+	int ret, nb_bytes;
+	bool use_lpm;
+	struct mipi_dsi_packet packet;
+
+#ifdef DEBUG
+	int i = 0;
+	u8 *p = msg->tx_buf;
+
+	printf("sec_mipi_dsi_host_transfer\n");
+	for (i; i < msg->tx_len; i++) {
+		printf("0x%.2x ", *(u8 *)p);
+		p++;
+	}
+	printf("\n");
+#endif
+
+	ret = mipi_dsi_create_packet(&packet, msg);
+	if (ret) {
+		dev_err(dsim->device->dev, "failed to create dsi packet: %d\n", ret);
+		return ret;
+	}
+
+	/* config LPM for CMD TX */
+	use_lpm = msg->flags & MIPI_DSI_MSG_USE_LPM ? true : false;
+	sec_mipi_dsim_config_cmd_lpm(dsim, use_lpm);
+
+	if (packet.payload_length) {		/* Long Packet case */
+		/* write packet payload */
+		sec_mipi_dsim_write_pl_to_sfr_fifo(dsim,
+						   packet.payload,
+						   packet.payload_length);
+
+		/* write packet header */
+		sec_mipi_dsim_write_ph_to_sfr_fifo(dsim,
+						   packet.header,
+						   use_lpm);
+
+		ret = sec_mipi_dsim_wait_for_pkt_done(dsim, MIPI_FIFO_TIMEOUT);
+		if (ret) {
+			dev_err(dsim->device->dev, "wait tx done timeout!\n");
+			return -EBUSY;
+		}
+	} else {
+		/* write packet header */
+		sec_mipi_dsim_write_ph_to_sfr_fifo(dsim,
+						   packet.header,
+						   use_lpm);
+
+		ret = sec_mipi_dsim_wait_for_hdr_done(dsim, MIPI_FIFO_TIMEOUT);
+		if (ret) {
+			dev_err(dsim->device->dev, "wait pkthdr tx done time out\n");
+			return -EBUSY;
+		}
+	}
+
+	/* read packet payload */
+	if (unlikely(msg->rx_buf)) {
+		ret = sec_mipi_dsim_wait_for_rx_done(dsim,
+						  MIPI_FIFO_TIMEOUT);
+		if (ret) {
+			dev_err(dsim->device->dev, "wait rx done time out\n");
+			return -EBUSY;
+		}
+
+		ret = sec_mipi_dsim_read_pl_from_sfr_fifo(dsim,
+							  msg->rx_buf,
+							  msg->rx_len);
+		if (ret < 0)
+			return ret;
+		nb_bytes = msg->rx_len;
+	} else {
+		nb_bytes = packet.size;
+	}
+
+	return nb_bytes;
+
+}
+
+
+static const struct mipi_dsi_host_ops sec_mipi_dsim_host_ops = {
+	.attach = sec_mipi_dsim_host_attach,
+	.transfer = sec_mipi_dsi_host_transfer,
+};
+
+static int sec_mipi_dsim_init(struct udevice *dev,
+			    struct mipi_dsi_device *device,
+			    struct display_timing *timings,
+			    unsigned int max_data_lanes,
+			    const struct mipi_dsi_phy_ops *phy_ops)
+{
+	struct sec_mipi_dsim *dsi = dev_get_priv(dev);
+
+	dsi->max_data_lanes = max_data_lanes;
+	dsi->device = device;
+	dsi->dsi_host.ops = &sec_mipi_dsim_host_ops;
+	device->host = &dsi->dsi_host;
+
+	dsi->base = (void *)dev_read_addr(device->dev);
+	if ((fdt_addr_t)dsi->base == FDT_ADDR_T_NONE) {
+		dev_err(device->dev, "dsi dt register address error\n");
+		return -EINVAL;
+	}
+
+	dsi->timings = *timings;
+
+	return 0;
+}
+
+static int sec_mipi_dsim_enable(struct udevice *dev)
+{
+	return 0;
+}
+
+static int sec_mipi_dsim_disable(struct udevice *dev)
+{
+	uint32_t intsrc;
+	struct sec_mipi_dsim *dsim_host = dev_get_priv(dev);
+
+	/* disable data transfer of dsim */
+	sec_mipi_dsim_set_standby(dsim_host, false);
+
+	/* disable esc clock & byte clock */
+	sec_mipi_dsim_disable_clkctrl(dsim_host);
+
+	/* disable dsim pll */
+	sec_mipi_dsim_disable_pll(dsim_host);
+
+	/* Clear all intsrc */
+	intsrc = dsim_read(dsim_host, DSIM_INTSRC);
+	dsim_write(dsim_host, intsrc, DSIM_INTSRC);
+
+	return 0;
+}
+
+struct dsi_host_ops sec_mipi_dsim_ops = {
+	.init = sec_mipi_dsim_init,
+	.enable = sec_mipi_dsim_enable,
+	.disable = sec_mipi_dsim_disable,
+};
+
+static int sec_mipi_dsim_probe(struct udevice *dev)
+{
+	return 0;
+}
+
+static const struct udevice_id sec_mipi_dsim_ids[] = {
+	{ .compatible = "samsung,sec-mipi-dsi" },
+	{ }
+};
+
+U_BOOT_DRIVER(sec_mipi_dsim) = {
+	.name			= "sec_mipi_dsim",
+	.id			= UCLASS_DSI_HOST,
+	.of_match		= sec_mipi_dsim_ids,
+	.probe			= sec_mipi_dsim_probe,
+	.remove 		= sec_mipi_dsim_disable,
+	.ops			= &sec_mipi_dsim_ops,
+	.priv_auto	= sizeof(struct sec_mipi_dsim),
+};
diff --git a/drivers/video/nxp/layerscape/Kconfig b/drivers/video/nxp/layerscape/Kconfig
new file mode 100644
index 00000000000..5521ffa8389
--- /dev/null
+++ b/drivers/video/nxp/layerscape/Kconfig
@@ -0,0 +1,10 @@
+
+config VIDEO_LS_HDP_LOAD
+	bool "NXP Layerscape HDMI/DP firmware loading"
+	default n
+	depends on VIDEO
+	select VIDEO_NXP_HDP
+	help
+	  Support for HDMI/DP firmware loading for NXP Layerscape processors. The
+	  firmware is copied from system memory to the HDMI/DP IRAM and
+	  DRAM memory.
diff --git a/drivers/video/nxp/layerscape/Makefile b/drivers/video/nxp/layerscape/Makefile
new file mode 100644
index 00000000000..f95b00117c4
--- /dev/null
+++ b/drivers/video/nxp/layerscape/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2020 NXP
+
+obj-$(CONFIG_VIDEO_LS_HDP_LOAD) += hdp_load.o
diff --git a/drivers/video/nxp/layerscape/hdp_load.c b/drivers/video/nxp/layerscape/hdp_load.c
new file mode 100644
index 00000000000..141ff0697c7
--- /dev/null
+++ b/drivers/video/nxp/layerscape/hdp_load.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/global_data.h>
+
+#include "API_General.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int do_hdp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+	if (argc < 2)
+		return 0;
+
+	if (strncmp(argv[1], "load", 4) == 0) {
+		unsigned long address = 0;
+		unsigned long offset  = 0x2000;
+		const int iram_size   = 0x10000;
+		const int dram_size   = 0x8000;
+
+		if (argc > 2) {
+			address = simple_strtoul(argv[2], NULL, 0);
+			if (argc > 3)
+				offset = simple_strtoul(argv[3], NULL, 0);
+		} else {
+			printf("Missing address\n");
+		}
+
+		printf("Loading hdp firmware from 0x%016lx offset 0x%016lx\n",
+		       address, offset);
+		cdn_api_loadfirmware((unsigned char *)(address + offset),
+				     iram_size,
+				     (unsigned char *)(address + offset +
+						       iram_size),
+				     dram_size);
+		printf("Loading hdp firmware Complete\n");
+		/* do not turn off hdmi power or firmware load will be lost */
+	} else {
+		printf("test error argc %d\n", argc);
+	}
+
+	return 0;
+}
+
+/***************************************************/
+
+U_BOOT_CMD(
+	hdp,  CONFIG_SYS_MAXARGS, 1, do_hdp,
+	"load hdmi firmware ",
+	"[<command>] ...\n"
+	"hdpload [address] [<offset>]\n"
+	"        address - address where the binary image starts\n"
+	"        <offset> - IRAM offset in the binary image (8192 default)\n"
+	);
diff --git a/drivers/video/raydium-rm67191.c b/drivers/video/raydium-rm67191.c
new file mode 100644
index 00000000000..883845268d1
--- /dev/null
+++ b/drivers/video/raydium-rm67191.c
@@ -0,0 +1,563 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <mipi_dsi.h>
+#include <panel.h>
+#include <asm/gpio.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+
+#define CMD_TABLE_LEN 2
+typedef u8 cmd_set_table[CMD_TABLE_LEN];
+
+/* Write Manufacture Command Set Control */
+#define WRMAUCCTR 0xFE
+
+struct rm67191_panel_priv {
+	struct gpio_desc reset;
+	unsigned int lanes;
+	enum mipi_dsi_pixel_format format;
+	unsigned long mode_flags;
+};
+
+struct rad_platform_data {
+	int (*enable)(struct udevice *dev);
+};
+
+/* Manufacturer Command Set pages (CMD2) */
+static const cmd_set_table mcs_rm67191[] = {
+	{0xFE, 0x0B},
+	{0x28, 0x40},
+	{0x29, 0x4F},
+	{0xFE, 0x0E},
+	{0x4B, 0x00},
+	{0x4C, 0x0F},
+	{0x4D, 0x20},
+	{0x4E, 0x40},
+	{0x4F, 0x60},
+	{0x50, 0xA0},
+	{0x51, 0xC0},
+	{0x52, 0xE0},
+	{0x53, 0xFF},
+	{0xFE, 0x0D},
+	{0x18, 0x08},
+	{0x42, 0x00},
+	{0x08, 0x41},
+	{0x46, 0x02},
+	{0x72, 0x09},
+	{0xFE, 0x0A},
+	{0x24, 0x17},
+	{0x04, 0x07},
+	{0x1A, 0x0C},
+	{0x0F, 0x44},
+	{0xFE, 0x04},
+	{0x00, 0x0C},
+	{0x05, 0x08},
+	{0x06, 0x08},
+	{0x08, 0x08},
+	{0x09, 0x08},
+	{0x0A, 0xE6},
+	{0x0B, 0x8C},
+	{0x1A, 0x12},
+	{0x1E, 0xE0},
+	{0x29, 0x93},
+	{0x2A, 0x93},
+	{0x2F, 0x02},
+	{0x31, 0x02},
+	{0x33, 0x05},
+	{0x37, 0x2D},
+	{0x38, 0x2D},
+	{0x3A, 0x1E},
+	{0x3B, 0x1E},
+	{0x3D, 0x27},
+	{0x3F, 0x80},
+	{0x40, 0x40},
+	{0x41, 0xE0},
+	{0x4F, 0x2F},
+	{0x50, 0x1E},
+	{0xFE, 0x06},
+	{0x00, 0xCC},
+	{0x05, 0x05},
+	{0x07, 0xA2},
+	{0x08, 0xCC},
+	{0x0D, 0x03},
+	{0x0F, 0xA2},
+	{0x32, 0xCC},
+	{0x37, 0x05},
+	{0x39, 0x83},
+	{0x3A, 0xCC},
+	{0x41, 0x04},
+	{0x43, 0x83},
+	{0x44, 0xCC},
+	{0x49, 0x05},
+	{0x4B, 0xA2},
+	{0x4C, 0xCC},
+	{0x51, 0x03},
+	{0x53, 0xA2},
+	{0x75, 0xCC},
+	{0x7A, 0x03},
+	{0x7C, 0x83},
+	{0x7D, 0xCC},
+	{0x82, 0x02},
+	{0x84, 0x83},
+	{0x85, 0xEC},
+	{0x86, 0x0F},
+	{0x87, 0xFF},
+	{0x88, 0x00},
+	{0x8A, 0x02},
+	{0x8C, 0xA2},
+	{0x8D, 0xEA},
+	{0x8E, 0x01},
+	{0x8F, 0xE8},
+	{0xFE, 0x06},
+	{0x90, 0x0A},
+	{0x92, 0x06},
+	{0x93, 0xA0},
+	{0x94, 0xA8},
+	{0x95, 0xEC},
+	{0x96, 0x0F},
+	{0x97, 0xFF},
+	{0x98, 0x00},
+	{0x9A, 0x02},
+	{0x9C, 0xA2},
+	{0xAC, 0x04},
+	{0xFE, 0x06},
+	{0xB1, 0x12},
+	{0xB2, 0x17},
+	{0xB3, 0x17},
+	{0xB4, 0x17},
+	{0xB5, 0x17},
+	{0xB6, 0x11},
+	{0xB7, 0x08},
+	{0xB8, 0x09},
+	{0xB9, 0x06},
+	{0xBA, 0x07},
+	{0xBB, 0x17},
+	{0xBC, 0x17},
+	{0xBD, 0x17},
+	{0xBE, 0x17},
+	{0xBF, 0x17},
+	{0xC0, 0x17},
+	{0xC1, 0x17},
+	{0xC2, 0x17},
+	{0xC3, 0x17},
+	{0xC4, 0x0F},
+	{0xC5, 0x0E},
+	{0xC6, 0x00},
+	{0xC7, 0x01},
+	{0xC8, 0x10},
+	{0xFE, 0x06},
+	{0x95, 0xEC},
+	{0x8D, 0xEE},
+	{0x44, 0xEC},
+	{0x4C, 0xEC},
+	{0x32, 0xEC},
+	{0x3A, 0xEC},
+	{0x7D, 0xEC},
+	{0x75, 0xEC},
+	{0x00, 0xEC},
+	{0x08, 0xEC},
+	{0x85, 0xEC},
+	{0xA6, 0x21},
+	{0xA7, 0x05},
+	{0xA9, 0x06},
+	{0x82, 0x06},
+	{0x41, 0x06},
+	{0x7A, 0x07},
+	{0x37, 0x07},
+	{0x05, 0x06},
+	{0x49, 0x06},
+	{0x0D, 0x04},
+	{0x51, 0x04},
+};
+
+static const cmd_set_table mcs_rm67199[] = {
+	{0xFE, 0xA0}, {0x2B, 0x18}, {0xFE, 0x70}, {0x7D, 0x05},
+	{0x5D, 0x0A}, {0x5A, 0x79}, {0x5C, 0x00}, {0x52, 0x00},
+	{0xFE, 0xD0}, {0x40, 0x02}, {0x13, 0x40}, {0xFE, 0x40},
+	{0x05, 0x08}, {0x06, 0x08}, {0x08, 0x08}, {0x09, 0x08},
+	{0x0A, 0xCA}, {0x0B, 0x88}, {0x20, 0x93}, {0x21, 0x93},
+	{0x24, 0x02}, {0x26, 0x02}, {0x28, 0x05}, {0x2A, 0x05},
+	{0x74, 0x2F}, {0x75, 0x1E}, {0xAD, 0x00}, {0xFE, 0x60},
+	{0x00, 0xCC}, {0x01, 0x00}, {0x02, 0x04}, {0x03, 0x00},
+	{0x04, 0x00}, {0x05, 0x07}, {0x06, 0x00}, {0x07, 0x88},
+	{0x08, 0x00}, {0x09, 0xCC}, {0x0A, 0x00}, {0x0B, 0x04},
+	{0x0C, 0x00}, {0x0D, 0x00}, {0x0E, 0x05}, {0x0F, 0x00},
+	{0x10, 0x88}, {0x11, 0x00}, {0x12, 0xCC}, {0x13, 0x0F},
+	{0x14, 0xFF}, {0x15, 0x04}, {0x16, 0x00}, {0x17, 0x06},
+	{0x18, 0x00}, {0x19, 0x96}, {0x1A, 0x00}, {0x24, 0xCC},
+	{0x25, 0x00}, {0x26, 0x02}, {0x27, 0x00}, {0x28, 0x00},
+	{0x29, 0x06}, {0x2A, 0x06}, {0x2B, 0x82}, {0x2D, 0x00},
+	{0x2F, 0xCC}, {0x30, 0x00}, {0x31, 0x02}, {0x32, 0x00},
+	{0x33, 0x00}, {0x34, 0x07}, {0x35, 0x06}, {0x36, 0x82},
+	{0x37, 0x00}, {0x38, 0xCC}, {0x39, 0x00}, {0x3A, 0x02},
+	{0x3B, 0x00}, {0x3D, 0x00}, {0x3F, 0x07}, {0x40, 0x00},
+	{0x41, 0x88}, {0x42, 0x00}, {0x43, 0xCC}, {0x44, 0x00},
+	{0x45, 0x02}, {0x46, 0x00}, {0x47, 0x00}, {0x48, 0x06},
+	{0x49, 0x02}, {0x4A, 0x8A}, {0x4B, 0x00}, {0x5F, 0xCA},
+	{0x60, 0x01}, {0x61, 0xE8}, {0x62, 0x09}, {0x63, 0x00},
+	{0x64, 0x07}, {0x65, 0x00}, {0x66, 0x30}, {0x67, 0x00},
+	{0x9B, 0x03}, {0xA9, 0x07}, {0xAA, 0x06}, {0xAB, 0x02},
+	{0xAC, 0x10}, {0xAD, 0x11}, {0xAE, 0x05}, {0xAF, 0x04},
+	{0xB0, 0x10}, {0xB1, 0x10}, {0xB2, 0x10}, {0xB3, 0x10},
+	{0xB4, 0x10}, {0xB5, 0x10}, {0xB6, 0x10}, {0xB7, 0x10},
+	{0xB8, 0x10}, {0xB9, 0x10}, {0xBA, 0x04}, {0xBB, 0x05},
+	{0xBC, 0x00}, {0xBD, 0x01}, {0xBE, 0x0A}, {0xBF, 0x10},
+	{0xC0, 0x11}, {0xFE, 0xA0}, {0x22, 0x00},
+};
+
+
+static const struct display_timing default_timing = {
+	.pixelclock.typ		= 121000000,
+	.hactive.typ		= 1080,
+	.hfront_porch.typ	= 20,
+	.hback_porch.typ	= 34,
+	.hsync_len.typ		= 2,
+	.vactive.typ		= 1920,
+	.vfront_porch.typ	= 10,
+	.vback_porch.typ	= 4,
+	.vsync_len.typ		= 2,
+	.flags = DISPLAY_FLAGS_HSYNC_LOW |
+		 DISPLAY_FLAGS_VSYNC_LOW |
+		 DISPLAY_FLAGS_DE_LOW |
+		 DISPLAY_FLAGS_PIXDATA_NEGEDGE,
+};
+
+
+static u8 color_format_from_dsi_format(enum mipi_dsi_pixel_format format)
+{
+	switch (format) {
+	case MIPI_DSI_FMT_RGB565:
+		return 0x55;
+	case MIPI_DSI_FMT_RGB666:
+	case MIPI_DSI_FMT_RGB666_PACKED:
+		return 0x66;
+	case MIPI_DSI_FMT_RGB888:
+		return 0x77;
+	default:
+		return 0x77; /* for backward compatibility */
+	}
+};
+
+static int rad_panel_push_cmd_list(struct mipi_dsi_device *device,
+				   const cmd_set_table *cmd_set,
+				   size_t count)
+{
+	size_t i;
+	const cmd_set_table *cmd;
+	int ret = 0;
+
+	for (i = 0; i < count; i++) {
+		cmd = cmd_set++;
+		ret = mipi_dsi_generic_write(device, cmd, CMD_TABLE_LEN);
+		if (ret < 0)
+			return ret;
+	}
+
+	return ret;
+};
+
+static int rm67191_enable(struct udevice *dev)
+{
+	struct rm67191_panel_priv *priv = dev_get_priv(dev);
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	struct mipi_dsi_device *dsi = plat->device;
+	u8 color_format = color_format_from_dsi_format(priv->format);
+	u16 brightness;
+	int ret;
+
+	dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+
+	ret = rad_panel_push_cmd_list(dsi, &mcs_rm67191[0],
+		sizeof(mcs_rm67191) / CMD_TABLE_LEN);
+	if (ret < 0) {
+		printf("Failed to send MCS (%d)\n", ret);
+		return -EIO;
+	}
+
+	/* Select User Command Set table (CMD1) */
+	ret = mipi_dsi_generic_write(dsi, (u8[]){ WRMAUCCTR, 0x00 }, 2);
+	if (ret < 0)
+		return -EIO;
+
+	/* Software reset */
+	ret = mipi_dsi_dcs_soft_reset(dsi);
+	if (ret < 0) {
+		printf("Failed to do Software Reset (%d)\n", ret);
+		return -EIO;
+	}
+
+	/* Wait 80ms for panel out of reset */
+	mdelay(80);
+
+	/* Set DSI mode */
+	ret = mipi_dsi_generic_write(dsi, (u8[]){ 0xC2, 0x0B }, 2);
+	if (ret < 0) {
+		printf("Failed to set DSI mode (%d)\n", ret);
+		return -EIO;
+	}
+
+	/* Set tear ON */
+	ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+	if (ret < 0) {
+		printf("Failed to set tear ON (%d)\n", ret);
+		return -EIO;
+	}
+
+	/* Set tear scanline */
+	ret = mipi_dsi_dcs_set_tear_scanline(dsi, 0x380);
+	if (ret < 0) {
+		printf("Failed to set tear scanline (%d)\n", ret);
+		return -EIO;
+	}
+
+	/* Set pixel format */
+	ret = mipi_dsi_dcs_set_pixel_format(dsi, color_format);
+	if (ret < 0) {
+		printf("Failed to set pixel format (%d)\n", ret);
+		return -EIO;
+	}
+
+
+	/* Set display brightness */
+	brightness = 255; /* Max brightness */
+	ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, &brightness, 2);
+	if (ret < 0) {
+		printf("Failed to set display brightness (%d)\n",
+				  ret);
+		return -EIO;
+	}
+
+	/* Exit sleep mode */
+	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+	if (ret < 0) {
+		printf("Failed to exit sleep mode (%d)\n", ret);
+		return -EIO;
+	}
+
+	mdelay(5);
+
+	ret = mipi_dsi_dcs_set_display_on(dsi);
+	if (ret < 0) {
+		printf("Failed to set display ON (%d)\n", ret);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int rm67199_enable(struct udevice *dev)
+{
+	struct rm67191_panel_priv *priv = dev_get_priv(dev);
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	struct mipi_dsi_device *dsi = plat->device;
+	u8 color_format = color_format_from_dsi_format(priv->format);
+	u16 brightness;
+	int ret;
+
+	dsi->mode_flags |= MIPI_DSI_MODE_LPM;
+
+	ret = rad_panel_push_cmd_list(dsi, &mcs_rm67199[0],
+		sizeof(mcs_rm67199) / CMD_TABLE_LEN);
+	if (ret < 0) {
+		printf("Failed to send MCS (%d)\n", ret);
+		return -EIO;
+	}
+
+	/* Select User Command Set table (CMD1) */
+	ret = mipi_dsi_generic_write(dsi, (u8[]){ WRMAUCCTR, 0x00 }, 2);
+	if (ret < 0)
+		return -EIO;
+
+	/* Set DSI mode */
+	ret = mipi_dsi_generic_write(dsi, (u8[]){ 0xC2, 0x08 }, 2);
+	if (ret < 0) {
+		printf("Failed to set DSI mode (%d)\n", ret);
+		return -EIO;
+	}
+
+	/* Set tear ON */
+	ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+	if (ret < 0) {
+		printf("Failed to set tear ON (%d)\n", ret);
+		return -EIO;
+	}
+
+	/* Set tear scanline */
+	ret = mipi_dsi_dcs_set_tear_scanline(dsi, 0x00);
+	if (ret < 0) {
+		printf("Failed to set tear scanline (%d)\n", ret);
+		return -EIO;
+	}
+
+	/* Set pixel format */
+	ret = mipi_dsi_dcs_set_pixel_format(dsi, color_format);
+	if (ret < 0) {
+		printf("Failed to set pixel format (%d)\n", ret);
+		return -EIO;
+	}
+
+
+	/* Set display brightness */
+	brightness = 255; /* Max brightness */
+	ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, &brightness, 2);
+	if (ret < 0) {
+		printf("Failed to set display brightness (%d)\n",
+				  ret);
+		return -EIO;
+	}
+
+	/* Exit sleep mode */
+	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+	if (ret < 0) {
+		printf("Failed to exit sleep mode (%d)\n", ret);
+		return -EIO;
+	}
+
+	mdelay(120);
+
+	ret = mipi_dsi_dcs_set_display_on(dsi);
+	if (ret < 0) {
+		printf("Failed to set display ON (%d)\n", ret);
+		return -EIO;
+	}
+
+	mdelay(100);
+
+	return 0;
+}
+
+
+static int rm67191_panel_enable_backlight(struct udevice *dev)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	struct rad_platform_data *data = (struct rad_platform_data *)dev_get_driver_data(dev);
+	struct mipi_dsi_device *device = plat->device;
+	int ret;
+
+	ret = mipi_dsi_attach(device);
+	if (ret < 0)
+		return ret;
+
+	return data->enable(dev);
+}
+
+static int rm67191_panel_get_display_timing(struct udevice *dev,
+					    struct display_timing *timings)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	struct mipi_dsi_device *device = plat->device;
+	struct rm67191_panel_priv *priv = dev_get_priv(dev);
+
+	memcpy(timings, &default_timing, sizeof(*timings));
+
+	/* fill characteristics of DSI data link */
+	if (device) {
+		device->lanes = priv->lanes;
+		device->format = priv->format;
+		device->mode_flags = priv->mode_flags;
+	}
+
+	return 0;
+}
+
+static int rm67191_panel_probe(struct udevice *dev)
+{
+	struct rm67191_panel_priv *priv = dev_get_priv(dev);
+	int ret;
+	u32 video_mode;
+
+	priv->format = MIPI_DSI_FMT_RGB888;
+	priv->mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO;
+
+	ret = dev_read_u32(dev, "video-mode", &video_mode);
+	if (!ret) {
+		switch (video_mode) {
+		case 0:
+			/* burst mode */
+			priv->mode_flags |= MIPI_DSI_MODE_VIDEO_BURST;
+			break;
+		case 1:
+			/* non-burst mode with sync event */
+			break;
+		case 2:
+			/* non-burst mode with sync pulse */
+			priv->mode_flags |= MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
+			break;
+		default:
+			dev_warn(dev, "invalid video mode %d\n", video_mode);
+			break;
+		}
+	}
+
+	ret = dev_read_u32(dev, "dsi-lanes", &priv->lanes);
+	if (ret) {
+		printf("Failed to get dsi-lanes property (%d)\n", ret);
+		return ret;
+	}
+
+	ret = gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset,
+				   GPIOD_IS_OUT);
+	if (ret) {
+		printf("Warning: cannot get reset GPIO\n");
+		if (ret != -ENOENT)
+			return ret;
+	}
+
+	/* reset panel */
+	ret = dm_gpio_set_value(&priv->reset, true);
+	if (ret)
+		printf("reset gpio fails to set true\n");
+	mdelay(100);
+	ret = dm_gpio_set_value(&priv->reset, false);
+	if (ret)
+		printf("reset gpio fails to set true\n");
+	mdelay(100);
+
+	return 0;
+}
+
+static int rm67191_panel_disable(struct udevice *dev)
+{
+	struct rm67191_panel_priv *priv = dev_get_priv(dev);
+
+	dm_gpio_set_value(&priv->reset, true);
+
+	return 0;
+}
+
+static const struct panel_ops rm67191_panel_ops = {
+	.enable_backlight = rm67191_panel_enable_backlight,
+	.get_display_timing = rm67191_panel_get_display_timing,
+};
+
+static const struct rad_platform_data rad_rm67191 = {
+	.enable = &rm67191_enable,
+};
+
+static const struct rad_platform_data rad_rm67199 = {
+	.enable = &rm67199_enable,
+};
+
+static const struct udevice_id rm67191_panel_ids[] = {
+	{ .compatible = "raydium,rm67191", .data = (ulong)&rad_rm67191 },
+	{ .compatible = "raydium,rm67199", .data = (ulong)&rad_rm67199 },
+	{ }
+};
+
+U_BOOT_DRIVER(rm67191_panel) = {
+	.name			  = "rm67191_panel",
+	.id			  = UCLASS_PANEL,
+	.of_match		  = rm67191_panel_ids,
+	.ops			  = &rm67191_panel_ops,
+	.probe			  = rm67191_panel_probe,
+	.remove			  = rm67191_panel_disable,
+	.plat_auto = sizeof(struct mipi_dsi_panel_plat),
+	.priv_auto = sizeof(struct rm67191_panel_priv),
+};
diff --git a/drivers/video/raydium-rm68200.c b/drivers/video/raydium-rm68200.c
index 373668d28bf..1f06c458760 100644
--- a/drivers/video/raydium-rm68200.c
+++ b/drivers/video/raydium-rm68200.c
@@ -246,18 +246,29 @@ static int rm68200_panel_enable_backlight(struct udevice *dev)
 
 	mdelay(20);
 
-	ret = backlight_enable(priv->backlight);
-	if (ret)
-		return ret;
-
+	if (priv->backlight) {
+		ret = backlight_enable(priv->backlight);
+		if (ret)
+			return ret;
+	}
 	return 0;
 }
 
 static int rm68200_panel_get_display_timing(struct udevice *dev,
 					    struct display_timing *timings)
 {
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	struct mipi_dsi_device *device = plat->device;
+
 	memcpy(timings, &default_timing, sizeof(*timings));
 
+	/* fill characteristics of DSI data link */
+	if (device) {
+		device->lanes = plat->lanes;
+		device->format = plat->format;
+		device->mode_flags = plat->mode_flags;
+	}
+
 	return 0;
 }
 
@@ -285,7 +296,7 @@ static int rm68200_panel_of_to_plat(struct udevice *dev)
 
 	ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
 					   "backlight", &priv->backlight);
-	if (ret) {
+	if (ret && ret != -ENOENT) {
 		dev_err(dev, "Cannot get backlight: ret=%d\n", ret);
 		return ret;
 	}
@@ -321,6 +332,15 @@ static int rm68200_panel_probe(struct udevice *dev)
 	return 0;
 }
 
+static int rm68200_panel_disable(struct udevice *dev)
+{
+	struct rm68200_panel_priv *priv = dev_get_priv(dev);
+
+	dm_gpio_set_value(&priv->reset, true);
+
+	return 0;
+}
+
 static const struct panel_ops rm68200_panel_ops = {
 	.enable_backlight = rm68200_panel_enable_backlight,
 	.get_display_timing = rm68200_panel_get_display_timing,
@@ -338,6 +358,7 @@ U_BOOT_DRIVER(rm68200_panel) = {
 	.ops			  = &rm68200_panel_ops,
 	.of_to_plat	  = rm68200_panel_of_to_plat,
 	.probe			  = rm68200_panel_probe,
+	.remove			  = rm68200_panel_disable,
 	.plat_auto	= sizeof(struct mipi_dsi_panel_plat),
 	.priv_auto	= sizeof(struct rm68200_panel_priv),
 };
diff --git a/drivers/video/rocktech-hx8394f.c b/drivers/video/rocktech-hx8394f.c
new file mode 100644
index 00000000000..619e6c8b99f
--- /dev/null
+++ b/drivers/video/rocktech-hx8394f.c
@@ -0,0 +1,318 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <common.h>
+#include <backlight.h>
+#include <dm.h>
+#include <mipi_dsi.h>
+#include <panel.h>
+#include <asm/gpio.h>
+#include <dm/device_compat.h>
+#include <linux/delay.h>
+#include <power/regulator.h>
+
+/* User Define command set */
+#define UD_SETADDRESSMODE	0x36 /* Set address mode */
+#define UD_SETSEQUENCE		0xB0 /* Set sequence */
+#define UD_SETPOWER		0xB1 /* Set power */
+#define UD_SETDISP		0xB2 /* Set display related register */
+#define UD_SETCYC		0xB4 /* Set display waveform cycles */
+#define UD_SETVCOM		0xB6 /* Set VCOM voltage */
+#define UD_SETTE		0xB7 /* Set internal TE function */
+#define UD_SETSENSOR		0xB8 /* Set temperature sensor */
+#define UD_SETEXTC		0xB9 /* Set extension command */
+#define UD_SETMIPI		0xBA /* Set MIPI control */
+#define UD_SETOTP		0xBB /* Set OTP */
+#define UD_SETREGBANK		0xBD /* Set register bank */
+#define UD_SETDGCLUT		0xC1 /* Set DGC LUT */
+#define UD_SETID		0xC3 /* Set ID */
+#define UD_SETDDB		0xC4 /* Set DDB */
+#define UD_SETCABC		0xC9 /* Set CABC control */
+#define UD_SETCABCGAIN		0xCA
+#define UD_SETPANEL		0xCC
+#define UD_SETOFFSET		0xD2
+#define UD_SETGIP0		0xD3 /* Set GIP Option0 */
+#define UD_SETGIP1		0xD5 /* Set GIP Option1 */
+#define UD_SETGIP2		0xD6 /* Set GIP Option2 */
+#define UD_SETGPO		0xD9
+#define UD_SETSCALING		0xDD
+#define UD_SETIDLE		0xDF
+#define UD_SETGAMMA		0xE0 /* Set gamma curve related setting */
+#define UD_SETCHEMODE_DYN	0xE4
+#define UD_SETCHE		0xE5
+#define UD_SETCESEL		0xE6 /* Enable color enhance */
+#define UD_SET_SP_CMD		0xE9
+#define UD_SETREADINDEX		0xFE /* Set SPI Read Index */
+#define UD_GETSPIREAD		0xFF /* SPI Read Command Data */
+
+struct hx8394f_panel_priv {
+	struct udevice *reg[2];
+	struct udevice *backlight;
+	struct gpio_desc reset;
+	unsigned int lanes;
+};
+
+static const struct display_timing default_timing = {
+	.pixelclock.typ		= 66000000,
+	.hactive.typ		= 720,
+	.hfront_porch.typ	= 52,
+	.hback_porch.typ	= 52,
+	.hsync_len.typ		= 10,
+	.vactive.typ		= 1280,
+	.vfront_porch.typ	= 16,
+	.vback_porch.typ	= 16,
+	.vsync_len.typ		= 7,
+};
+
+static void hx8394f_dcs_write_buf(struct udevice *dev, const void *data,
+				  size_t len)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	struct mipi_dsi_device *device = plat->device;
+	int err;
+
+	err = mipi_dsi_dcs_write_buffer(device, data, len);
+	if (err < 0)
+		dev_err(dev, "MIPI DSI DCS write buffer failed: %d\n", err);
+}
+
+#define dcs_write_seq(ctx, seq...)				\
+({								\
+	static const u8 d[] = { seq };				\
+								\
+	hx8394f_dcs_write_buf(ctx, d, ARRAY_SIZE(d));		\
+})
+
+static void hx8394f_init_sequence(struct udevice *dev)
+{
+	struct hx8394f_panel_priv *priv = dev_get_priv(dev);
+	u8 mipi_data[] = {UD_SETMIPI, 0x60, 0x03, 0x68, 0x6B, 0xB2, 0xC0};
+
+	dcs_write_seq(dev, UD_SETADDRESSMODE, 0x02);
+	dcs_write_seq(dev, UD_SETEXTC, 0xFF, 0x83, 0x94);
+
+	/* SETMIPI */
+	mipi_data[1] = 0x60 | (priv->lanes - 1);
+	hx8394f_dcs_write_buf(dev, mipi_data, ARRAY_SIZE(mipi_data));
+
+	dcs_write_seq(dev, UD_SETPOWER, 0x48, 0x12, 0x72, 0x09, 0x32, 0x54,
+		      0x71, 0x71, 0x57, 0x47);
+
+	dcs_write_seq(dev, UD_SETDISP, 0x00, 0x80, 0x64, 0x15, 0x0E, 0x11);
+
+	dcs_write_seq(dev, UD_SETCYC, 0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 0x01,
+		      0x0C, 0x86, 0x75, 0x00, 0x3F, 0x73, 0x74, 0x73, 0x74,
+		      0x73, 0x74, 0x01, 0x0C, 0x86);
+
+	dcs_write_seq(dev, UD_SETGIP0, 0x00, 0x00, 0x07, 0x07, 0x40, 0x07, 0x0C,
+		      0x00, 0x08, 0x10, 0x08, 0x00, 0x08, 0x54, 0x15, 0x0A,
+		      0x05, 0x0A, 0x02, 0x15, 0x06, 0x05, 0x06, 0x47, 0x44,
+		      0x0A, 0x0A, 0x4B, 0x10, 0x07, 0x07, 0x0C, 0x40);
+
+	dcs_write_seq(dev, UD_SETGIP1, 0x1C, 0x1C, 0x1D, 0x1D, 0x00, 0x01, 0x02,
+		      0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
+		      0x24, 0x25, 0x18, 0x18, 0x26, 0x27, 0x18, 0x18, 0x18,
+		      0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+		      0x18, 0x18, 0x18, 0x18, 0x20, 0x21, 0x18, 0x18, 0x18,
+		      0x18);
+
+	dcs_write_seq(dev, UD_SETGIP2, 0x1C, 0x1C, 0x1D, 0x1D, 0x07, 0x06, 0x05,
+		      0x04, 0x03, 0x02, 0x01, 0x00, 0x0B, 0x0A, 0x09, 0x08,
+		      0x21, 0x20, 0x18, 0x18, 0x27, 0x26, 0x18, 0x18, 0x18,
+		      0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+		      0x18, 0x18, 0x18, 0x18, 0x25, 0x24, 0x18, 0x18, 0x18,
+		      0x18);
+
+	dcs_write_seq(dev, UD_SETVCOM, 0x92, 0x92);
+
+	dcs_write_seq(dev, UD_SETGAMMA, 0x00, 0x0A, 0x15, 0x1B, 0x1E, 0x21,
+		      0x24, 0x22, 0x47, 0x56, 0x65, 0x66, 0x6E, 0x82, 0x88,
+		      0x8B, 0x9A, 0x9D, 0x98, 0xA8, 0xB9, 0x5D, 0x5C, 0x61,
+		      0x66, 0x6A, 0x6F, 0x7F, 0x7F, 0x00, 0x0A, 0x15, 0x1B,
+		      0x1E, 0x21, 0x24, 0x22, 0x47, 0x56, 0x65, 0x65, 0x6E,
+		      0x81, 0x87, 0x8B, 0x98, 0x9D, 0x99, 0xA8, 0xBA, 0x5D,
+		      0x5D, 0x62, 0x67, 0x6B, 0x72, 0x7F, 0x7F);
+	dcs_write_seq(dev, 0xC0, 0x1F, 0x31);
+	dcs_write_seq(dev, UD_SETPANEL, 0x03);
+	dcs_write_seq(dev, 0xD4, 0x02);
+	dcs_write_seq(dev, UD_SETREGBANK, 0x02);
+	dcs_write_seq(dev, 0xD8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+		      0xFF, 0xFF, 0xFF, 0xFF);
+	dcs_write_seq(dev, UD_SETREGBANK, 0x00);
+	dcs_write_seq(dev, UD_SETREGBANK, 0x01);
+	dcs_write_seq(dev, UD_SETPOWER, 0x00);
+	dcs_write_seq(dev, UD_SETREGBANK, 0x00);
+	dcs_write_seq(dev, 0xBF, 0x40, 0x81, 0x50, 0x00, 0x1A, 0xFC, 0x01);
+	dcs_write_seq(dev, 0xC6, 0xED);
+}
+
+static int hx8394f_panel_enable_backlight(struct udevice *dev)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	struct mipi_dsi_device *device = plat->device;
+	struct hx8394f_panel_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = mipi_dsi_attach(device);
+	if (ret < 0)
+		return ret;
+
+	hx8394f_init_sequence(dev);
+
+	ret = mipi_dsi_dcs_set_tear_on(device, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+	if (ret < 0) {
+		printf("Failed to set tear ON (%d)\n", ret);
+		return -EIO;
+	}
+
+	ret = mipi_dsi_dcs_exit_sleep_mode(device);
+	if (ret)
+		return ret;
+
+	mdelay(120);
+
+	ret = mipi_dsi_dcs_set_display_on(device);
+	if (ret)
+		return ret;
+
+	mdelay(50);
+
+	if (priv->backlight) {
+		ret = backlight_enable(priv->backlight);
+		if (ret)
+			return ret;
+	}
+	return 0;
+}
+
+static int hx8394f_panel_get_display_timing(struct udevice *dev,
+					    struct display_timing *timings)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	struct mipi_dsi_device *device = plat->device;
+
+	memcpy(timings, &default_timing, sizeof(*timings));
+
+	/* fill characteristics of DSI data link */
+	if (device) {
+		device->lanes = plat->lanes;
+		device->format = plat->format;
+		device->mode_flags = plat->mode_flags;
+	}
+
+	return 0;
+}
+
+static int hx8394f_panel_of_to_plat(struct udevice *dev)
+{
+	struct hx8394f_panel_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
+		ret =  device_get_supply_regulator(dev, "vcc-supply",
+						   &priv->reg[0]);
+		if (ret && ret != -ENOENT) {
+			dev_err(dev, "Warning: cannot get vcc supply\n");
+			return ret;
+		}
+
+		ret =  device_get_supply_regulator(dev, "iovcc-supply",
+						   &priv->reg[1]);
+		if (ret && ret != -ENOENT) {
+			dev_err(dev, "Warning: cannot get iovcc supply\n");
+			return ret;
+		}
+	}
+
+	ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset,
+				   GPIOD_IS_OUT);
+	if (ret) {
+		dev_err(dev, "Warning: cannot get reset GPIO\n");
+		if (ret != -ENOENT)
+			return ret;
+	}
+
+	ret =  dev_read_u32(dev, "himax,dsi-lanes", &priv->lanes);
+	if (ret) {
+		dev_err(dev, "Warning: himax,dsi-lanes property\n");
+		return ret;
+	}
+
+	ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+					   "backlight", &priv->backlight);
+	if (ret && ret != -ENOENT) {
+		dev_err(dev, "Cannot get backlight: ret=%d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int hx8394f_panel_probe(struct udevice *dev)
+{
+	struct hx8394f_panel_priv *priv = dev_get_priv(dev);
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	int ret;
+
+	if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
+		if (priv->reg[0]) {
+			ret = regulator_set_enable(priv->reg[0], true);
+			if (ret)
+				return ret;
+		}
+
+		if (priv->reg[1]) {
+			ret = regulator_set_enable(priv->reg[1], true);
+			if (ret)
+				return ret;
+		}
+	}
+
+	/* reset panel */
+	dm_gpio_set_value(&priv->reset, true);
+	mdelay(1);
+	dm_gpio_set_value(&priv->reset, false);
+	mdelay(10);
+
+	/* fill characteristics of DSI data link */
+	plat->lanes = priv->lanes;
+	plat->format = MIPI_DSI_FMT_RGB888;
+	plat->mode_flags = MIPI_DSI_MODE_VIDEO |
+			   MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
+			   MIPI_DSI_MODE_LPM;
+
+	return 0;
+}
+
+static int hx8394f_panel_disable(struct udevice *dev)
+{
+	struct hx8394f_panel_priv *priv = dev_get_priv(dev);
+
+	dm_gpio_set_value(&priv->reset, true);
+
+	return 0;
+}
+
+static const struct panel_ops hx8394f_panel_ops = {
+	.enable_backlight = hx8394f_panel_enable_backlight,
+	.get_display_timing = hx8394f_panel_get_display_timing,
+};
+
+static const struct udevice_id hx8394f_panel_ids[] = {
+	{ .compatible = "rocktech,hx8394f" },
+	{ }
+};
+
+U_BOOT_DRIVER(hx8394f_panel) = {
+	.name			  = "hx8394f_panel",
+	.id			  = UCLASS_PANEL,
+	.of_match		  = hx8394f_panel_ids,
+	.ops			  = &hx8394f_panel_ops,
+	.of_to_plat	  = hx8394f_panel_of_to_plat,
+	.probe			  = hx8394f_panel_probe,
+	.remove			  = hx8394f_panel_disable,
+	.plat_auto	= sizeof(struct mipi_dsi_panel_plat),
+	.priv_auto	= sizeof(struct hx8394f_panel_priv),
+};
diff --git a/drivers/video/video_link.c b/drivers/video/video_link.c
new file mode 100644
index 00000000000..72ef1a0f64f
--- /dev/null
+++ b/drivers/video/video_link.c
@@ -0,0 +1,534 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <linux/errno.h>
+
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+#include <dm/ofnode.h>
+#include <dm/read.h>
+#include <video.h>
+#include <panel.h>
+#include <env.h>
+
+struct of_endpoint {
+	unsigned int port;
+	unsigned int id;
+	ofnode local_node;
+};
+
+#define MAX_LINKS 3
+#define MAX_LINK_DEVICES 5
+
+struct video_link {
+	struct udevice *link_devs[MAX_LINK_DEVICES];
+	int dev_num;
+};
+
+struct video_link video_links[MAX_LINKS];
+struct video_link temp_stack;
+ulong video_links_num = 0;
+ulong curr_video_link = 0;
+bool video_off = false;
+
+ofnode ofnode_get_child_by_name(ofnode parent, const char *name)
+{
+	ofnode child;
+	const char *child_name;
+
+	for (child = ofnode_first_subnode(parent);
+	     ofnode_valid(child);
+	     child = ofnode_next_subnode(child)) {
+
+		child_name = ofnode_get_name(child);
+
+		if (!strncmp(child_name, name, strlen(name))) {
+			break;
+		}
+
+	}
+	return child;
+}
+
+ofnode ofnode_graph_get_next_endpoint(ofnode parent,
+					ofnode prev)
+{
+	ofnode endpoint;
+	ofnode port;
+	const char *name;
+
+
+	if (!ofnode_valid(prev)) {
+		ofnode node;
+
+		node = ofnode_find_subnode(parent, "ports");
+		if (ofnode_valid(node))
+			parent = node;
+
+		port = ofnode_get_child_by_name(parent, "port");
+		if (!ofnode_valid(port)) {
+			debug("no port node found in 0x%lx\n", parent.of_offset);
+			return ofnode_null();
+		}
+
+		endpoint = ofnode_first_subnode(port);
+		if (ofnode_valid(endpoint)) {
+			debug("get next endpoint %s\n", ofnode_get_name(endpoint));
+			return endpoint;
+		}
+	} else {
+		port = ofnode_get_parent(prev);
+		endpoint = ofnode_next_subnode(prev);
+		if (ofnode_valid(endpoint)) {
+			debug("get next endpoint %s\n", ofnode_get_name(endpoint));
+			return endpoint;
+		}
+	}
+
+	debug("port %s\n", ofnode_get_name(port));
+
+	while (1) {
+		do {
+			port = ofnode_next_subnode(port);
+			if (!ofnode_valid(port))
+				return ofnode_null();
+
+			name = ofnode_get_name(port);
+		} while (strncmp(name, "port", 4));
+
+		/*
+		 * Now that we have a port node, get the next endpoint by
+		 * getting the next child. If the previous endpoint is NULL this
+		 * will return the first child.
+		 */
+		endpoint = ofnode_first_subnode(port);
+		if (ofnode_valid(endpoint)) {
+			debug("get next endpoint %s\n", ofnode_get_name(endpoint));
+			return endpoint;
+		}
+	}
+
+	return ofnode_null();
+}
+
+#define for_each_endpoint_of_node(parent, child) \
+	for (child = ofnode_graph_get_next_endpoint(parent, ofnode_null()); ofnode_valid(child); \
+	     child = ofnode_graph_get_next_endpoint(parent, child))
+
+
+int ofnode_graph_get_endpoint_count(ofnode node)
+{
+	ofnode endpoint;
+	int num = 0;
+
+	for_each_endpoint_of_node(node, endpoint)
+		num++;
+
+	return num;
+}
+
+int ofnode_graph_parse_endpoint(ofnode node,
+			    struct of_endpoint *endpoint)
+{
+	ofnode port_node = ofnode_get_parent(node);
+
+	memset(endpoint, 0, sizeof(*endpoint));
+
+	endpoint->local_node = node;
+	/*
+	 * It doesn't matter whether the two calls below succeed.
+	 * If they don't then the default value 0 is used.
+	 */
+	ofnode_read_u32(port_node, "reg", &endpoint->port);
+	ofnode_read_u32(node, "reg", &endpoint->id);
+
+	return 0;
+}
+
+ofnode ofnode_graph_get_endpoint_by_regs(
+	const ofnode parent, int port_reg, int reg)
+{
+	struct of_endpoint endpoint;
+	ofnode node;
+
+	for_each_endpoint_of_node(parent, node) {
+		ofnode_graph_parse_endpoint(node, &endpoint);
+		if (((port_reg == -1) || (endpoint.port == port_reg)) &&
+			((reg == -1) || (endpoint.id == reg))) {
+			debug("get node %s\n", ofnode_get_name(node));
+
+			return node;
+		}
+	}
+
+	return ofnode_null();
+}
+
+ofnode ofnode_graph_get_remote_endpoint(ofnode node)
+{
+	ofnode remote;
+	u32 phandle;
+	int ret;
+
+	ret = ofnode_read_u32(node, "remote-endpoint", &phandle);
+	if (ret) {
+		printf("required remote-endpoint property isn't provided\n");
+		return ofnode_null();
+	}
+
+	remote = ofnode_get_by_phandle(phandle);
+	if (!ofnode_valid(remote)) {
+		printf("failed to find remote-endpoint\n");
+		return ofnode_null();
+	}
+
+	return remote;
+}
+
+ofnode ofnode_graph_get_port_parent(ofnode node)
+{
+	unsigned int depth;
+
+	if (!ofnode_valid(node))
+		return ofnode_null();
+
+	/*
+	 * Preserve usecount for passed in node as of_get_next_parent()
+	 * will do of_node_put() on it.
+	 */
+
+	/* Walk 3 levels up only if there is 'ports' node. */
+	for (depth = 3; depth && ofnode_valid(node); depth--) {
+		node = ofnode_get_parent(node);
+		const char *name = ofnode_get_name(node);
+		if (depth == 2 && strcmp(name, "ports"))
+			break;
+	}
+	return node;
+}
+
+ofnode ofnode_graph_get_remote_port_parent(ofnode node)
+{
+	ofnode np, pp;
+
+	/* Get remote endpoint node. */
+	np = ofnode_graph_get_remote_endpoint(node);
+
+	pp = ofnode_graph_get_port_parent(np);
+
+	return pp;
+}
+
+int find_device_by_ofnode(ofnode node, struct udevice **pdev)
+{
+	int ret;
+
+	if (!ofnode_is_available(node))
+		return -2;
+
+	ret = uclass_find_device_by_ofnode(UCLASS_DISPLAY, node, pdev);
+	if (!ret)
+		return 0;
+
+	ret = uclass_find_device_by_ofnode(UCLASS_DSI_HOST, node, pdev);
+	if (!ret)
+		return 0;
+
+	ret = uclass_find_device_by_ofnode(UCLASS_VIDEO_BRIDGE, node, pdev);
+	if (!ret)
+		return 0;
+
+	ret = uclass_find_device_by_ofnode(UCLASS_PANEL, node, pdev);
+	if (!ret)
+		return 0;
+
+	return -1;
+}
+
+static void video_link_stack_push(struct udevice *dev)
+{
+	if (temp_stack.dev_num < MAX_LINK_DEVICES) {
+		temp_stack.link_devs[temp_stack.dev_num] = dev;
+		temp_stack.dev_num++;
+	}
+}
+
+static void video_link_stack_pop(void)
+{
+	if (temp_stack.dev_num > 0) {
+		temp_stack.link_devs[temp_stack.dev_num] = NULL;
+		temp_stack.dev_num--;
+	}
+}
+
+static int duplicate_video_link(void)
+{
+	if (video_links_num < MAX_LINKS) {
+		video_links[video_links_num] = temp_stack;
+		video_links_num++;
+
+		debug("duplicate links num %lu,  temp_stack num %d\n",
+			video_links_num, temp_stack.dev_num);
+		return 0;
+	}
+
+	return -ENODEV;
+}
+
+static void video_link_add_node(struct udevice *peer_dev, struct udevice *dev, ofnode dev_node)
+{
+	int ret = 0;
+	ofnode remote, endpoint_node;
+	struct udevice *remote_dev;
+	bool find = false;
+
+	debug("endpoint cnt %d\n", ofnode_graph_get_endpoint_count(dev_node));
+
+	video_link_stack_push(dev);
+
+	for_each_endpoint_of_node(dev_node, endpoint_node) {
+		remote = ofnode_graph_get_remote_port_parent(endpoint_node);
+		if (!ofnode_valid(remote))
+			continue;
+
+		debug("remote %s\n", ofnode_get_name(remote));
+		ret = find_device_by_ofnode(remote, &remote_dev);
+		if (!ret) {
+			debug("remote dev %s\n", remote_dev->name);
+
+			if (peer_dev && peer_dev == remote_dev)
+				continue;
+
+			/* it is possible that ofnode of remote_dev is not equal to remote */
+			video_link_add_node(dev, remote_dev, remote);
+
+			find = true;
+		}
+	}
+
+	/* leaf node or no valid new endpoint, now copy the entire stack to a new video link */
+	if (!find) {
+		ret = duplicate_video_link();
+		if (ret)
+			printf("video link is full\n");
+	}
+
+	video_link_stack_pop();
+}
+
+struct udevice *video_link_get_next_device(struct udevice *curr_dev)
+{
+	int i, ret;
+
+	if (video_off)
+		return NULL;
+
+	if (curr_video_link >= video_links_num) {
+		printf("current video link is not correct\n");
+		return NULL;
+	}
+
+	for (i = 0; i < video_links[curr_video_link].dev_num; i++) {
+		if (video_links[curr_video_link].link_devs[i] == curr_dev) {
+			if ((i + 1) < video_links[curr_video_link].dev_num) {
+				ret = device_probe(video_links[curr_video_link].link_devs[i + 1]);
+				if (ret) {
+					printf("probe device is failed, ret %d\n", ret);
+					return NULL;
+				}
+
+				return video_links[curr_video_link].link_devs[i + 1];
+			} else {
+				debug("fail to find next device, already last one\n");
+				return NULL;
+			}
+		}
+	}
+
+	return NULL;
+}
+
+struct udevice *video_link_get_video_device(void)
+{
+	int ret;
+	if (video_off)
+		return NULL;
+
+	if (curr_video_link >= video_links_num)
+		return NULL;
+
+	if (video_links[curr_video_link].dev_num == 0)
+		return NULL;
+
+	ret = device_probe(video_links[curr_video_link].link_devs[0]);
+	if (ret) {
+		printf("probe video device failed, ret %d\n", ret);
+		return NULL;
+	}
+
+	return video_links[curr_video_link].link_devs[0];
+}
+
+int video_link_get_display_timings(struct display_timing *timings)
+{
+	int i = 0;
+	int ret;
+	struct udevice *dev;
+
+	if (video_off)
+		return -EPERM;
+
+	if (curr_video_link >= video_links_num)
+		return -ENODEV;
+
+	if (video_links[curr_video_link].dev_num == 0)
+		return -ENODEV;
+
+	for (i = video_links[curr_video_link].dev_num - 1; i >= 0 ; i--) {
+		dev = video_links[curr_video_link].link_devs[i];
+		if (device_get_uclass_id(dev) == UCLASS_PANEL) {
+			ret = device_probe(video_links[curr_video_link].link_devs[i]);
+			if (ret) {
+				printf("fail to probe panel device %s\n", dev->name);
+				return ret;
+			}
+
+			ret = panel_get_display_timing(dev, timings);
+			if (ret) {
+				ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, timings);
+				if (ret) {
+					printf("fail to get panel timing %s\n", dev->name);
+					return ret;
+				}
+			}
+
+			return 0;
+		} else if (device_get_uclass_id(dev) == UCLASS_DISPLAY ||
+			device_get_uclass_id(dev) == UCLASS_VIDEO) {
+
+			ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, timings);
+			if (!ret)
+				return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+
+static void list_videolink(bool current_only)
+{
+	ulong index = 0;
+	int j;
+	bool match;
+
+	/* dump the link */
+	debug("video link number: %lu\n", video_links_num);
+
+	for (index = 0; index < video_links_num; index ++) {
+		match = false;
+		if (curr_video_link == index)
+			match = true;
+		else if (current_only)
+			continue;
+
+		printf("[%c]-Video Link %lu", (match)? '*':' ', index);
+
+		if (match) {
+			struct udevice *video_dev = video_link_get_video_device();
+			if (video_dev) {
+				printf(" (%u x %u)", video_get_xsize(video_dev),
+					video_get_ysize(video_dev));
+			}
+		}
+
+		printf("\n");
+
+		for (j = 0; j < video_links[index].dev_num; j++) {
+			printf("\t[%d] %s, %s\n", j, video_links[index].link_devs[j]->name,
+				dev_get_uclass_name(video_links[index].link_devs[j]));
+		}
+	}
+}
+
+static int do_videolink(struct cmd_tbl * cmdtp, int flag, int argc, char * const argv[])
+{
+	char cmd = 'l';
+	int ret = 0;
+
+	if (argc > 1)
+		cmd = argv[1][0];
+
+	switch (cmd) {
+	case 'l':		/* list */
+		list_videolink(false);
+		break;
+	default:
+		ret = CMD_RET_USAGE;
+		break;
+	}
+
+	return ret;
+}
+
+int video_link_init(void)
+{
+	struct udevice *dev;
+	ulong env_id;
+	int off;
+	memset(&video_links, 0, sizeof(video_links));
+	memset(&temp_stack, 0, sizeof(temp_stack));
+
+	for (uclass_find_first_device(UCLASS_VIDEO, &dev);
+	     dev;
+	     uclass_find_next_device(&dev)) {
+
+		video_link_add_node(NULL, dev, dev_ofnode(dev));
+	}
+
+	if (video_links_num == 0) {
+		printf("Fail to setup video link\n");
+		return -ENODEV;
+	}
+
+	/* Read the env variable for default video link */
+	off = env_get_yesno("video_off");
+	if (off == 1) {
+		video_off = true;
+		return 0;
+	}
+
+	env_id = env_get_ulong("video_link", 10, 0);
+	if (env_id < video_links_num)
+		curr_video_link = env_id;
+
+	list_videolink(true);
+
+	return 0;
+}
+
+int video_link_shut_down(void)
+{
+	struct udevice *video_dev = video_link_get_video_device();
+
+	if (video_dev)
+		device_remove(video_dev, DM_REMOVE_NORMAL);
+
+	return 0;
+}
+
+#ifdef CONFIG_SYS_LONGHELP
+static char video_link_help_text[] =
+	"list \n"
+	"    -  show video link info, set video_link variable to select link";
+#endif
+
+U_BOOT_CMD(
+	videolink,	5,	1,	do_videolink,
+	"list and select video link", video_link_help_text
+);
diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c
index 3586246fbfb..96feae2ed25 100644
--- a/drivers/watchdog/imx_watchdog.c
+++ b/drivers/watchdog/imx_watchdog.c
@@ -48,7 +48,7 @@ void __attribute__((weak)) reset_cpu(void)
 {
 	struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
 
-	imx_watchdog_expire_now(wdog, true);
+	imx_watchdog_expire_now(wdog, false);
 }
 #endif
 
diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c
index ecd35ef22ac..940ce25c20e 100644
--- a/drivers/watchdog/ulp_wdog.c
+++ b/drivers/watchdog/ulp_wdog.c
@@ -28,11 +28,16 @@ struct wdog_regs {
 #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
 #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
 
+#define UNLOCK_WORD 0xD928C520 /* unlock word */
+#define REFRESH_WORD 0xB480A602 /* refresh word */
+
 #define WDGCS_WDGE                      BIT(7)
 #define WDGCS_WDGUPDATE                 BIT(5)
 
 #define WDGCS_RCS                       BIT(10)
 #define WDGCS_ULK                       BIT(11)
+#define WDOG_CS_PRES                    BIT(12)
+#define WDGCS_CMD32EN                   BIT(13)
 #define WDGCS_FLG                       BIT(14)
 
 #define WDG_BUS_CLK                      (0x0)
@@ -52,20 +57,30 @@ void hw_watchdog_reset(void)
 {
 	struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
 
-	dmb();
-	__raw_writel(REFRESH_WORD0, &wdog->cnt);
-	__raw_writel(REFRESH_WORD1, &wdog->cnt);
-	dmb();
+	if (readl(&wdog->cs) & WDGCS_CMD32EN) {
+		writel(REFRESH_WORD, &wdog->cnt);
+	} else {
+		dmb();
+		__raw_writel(REFRESH_WORD0, &wdog->cnt);
+		__raw_writel(REFRESH_WORD1, &wdog->cnt);
+		dmb();
+	}
 }
 
 void hw_watchdog_init(void)
 {
 	struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
-
-	dmb();
-	__raw_writel(UNLOCK_WORD0, &wdog->cnt);
-	__raw_writel(UNLOCK_WORD1, &wdog->cnt);
-	dmb();
+	u32 cmd32 = 0;
+
+	if (readl(&wdog->cs) & WDGCS_CMD32EN) {
+		writel(UNLOCK_WORD, &wdog->cnt);
+		cmd32 = WDGCS_CMD32EN;
+	} else {
+		dmb();
+		__raw_writel(UNLOCK_WORD0, &wdog->cnt);
+		__raw_writel(UNLOCK_WORD1, &wdog->cnt);
+		dmb();
+	}
 
 	/* Wait WDOG Unlock */
 	while (!(readl(&wdog->cs) & WDGCS_ULK))
@@ -75,7 +90,11 @@ void hw_watchdog_init(void)
 	writel(0, &wdog->win);
 
 	/* setting 1-kHz clock source, enable counter running, and clear interrupt */
-	writel((WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG), &wdog->cs);
+#if defined(CONFIG_ARCH_IMX9)
+	writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG | WDOG_CS_PRES), &wdog->cs);
+#else
+	writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG), &wdog->cs);
+#endif
 
 	/* Wait WDOG reconfiguration */
 	while (!(readl(&wdog->cs) & WDGCS_RCS))
@@ -87,21 +106,32 @@ void hw_watchdog_init(void)
 void reset_cpu(void)
 {
 	struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
-
-	dmb();
-	__raw_writel(UNLOCK_WORD0, &wdog->cnt);
-	__raw_writel(UNLOCK_WORD1, &wdog->cnt);
-	dmb();
+	u32 cmd32 = 0;
+
+	if (readl(&wdog->cs) & WDGCS_CMD32EN) {
+		writel(UNLOCK_WORD, &wdog->cnt);
+		cmd32 = WDGCS_CMD32EN;
+	} else {
+		dmb();
+		__raw_writel(UNLOCK_WORD0, &wdog->cnt);
+		__raw_writel(UNLOCK_WORD1, &wdog->cnt);
+		dmb();
+	}
 
 	/* Wait WDOG Unlock */
 	while (!(readl(&wdog->cs) & WDGCS_ULK))
 		;
 
-	hw_watchdog_set_timeout(5); /* 5ms timeout */
+	hw_watchdog_set_timeout(5); /* 5ms timeout for general; 40ms timeout for imx93 */
+
 	writel(0, &wdog->win);
 
 	/* enable counter running */
-	writel((WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);
+#if defined(CONFIG_ARCH_IMX9)
+	writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8) | WDOG_CS_PRES), &wdog->cs);
+#else	
+	writel((cmd32| WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);
+#endif
 
 	/* Wait WDOG reconfiguration */
 	while (!(readl(&wdog->cs) & WDGCS_RCS))
diff --git a/env/Kconfig b/env/Kconfig
index b9d04725a3a..1e3e4c37c2e 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -37,7 +37,7 @@ config ENV_IS_NOWHERE
 		     !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \
 		     !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \
 		     !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \
-		     !ENV_IS_IN_UBI
+		     !ENV_IS_IN_UBI && !ENV_IS_IN_SATA
 	help
 	  Define this if you don't want to or can't have an environment stored
 	  on a storage medium. In this case the environment will still exist
@@ -310,6 +310,20 @@ config ENV_IS_IN_REMOTE
 	  local device can get the environment from remote memory
 	  space by SRIO or PCIE links.
 
+config ENV_IS_IN_SATA
+    bool "Environment is in SATA disk"
+    depends on !CHAIN_OF_TRUST
+    help
+      Define this if you have a SATA disk device which you
+      want to use for the environment.
+
+      - CONFIG_ENV_OFFSET:
+      - CONFIG_ENV_SIZE:
+
+      These two #defines specify the offset and size of the
+      environment area within the SATA disk. CONFIG_ENV_OFFSET must be
+      aligned to an disk sector boundary.
+
 config ENV_IS_IN_SPI_FLASH
 	bool "Environment is in SPI flash"
 	depends on !CHAIN_OF_TRUST && SPI
@@ -534,7 +548,7 @@ config ENV_ADDR_REDUND
 config ENV_OFFSET
 	hex "Environment offset"
 	depends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \
-		    ENV_IS_IN_SPI_FLASH
+		    ENV_IS_IN_SPI_FLASH || ENV_IS_IN_SATA
 	default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC
 	default 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH
 	default 0xF0000 if ARCH_SUNXI
diff --git a/env/eeprom.c b/env/eeprom.c
index f8556a47213..41f7b802789 100644
--- a/env/eeprom.c
+++ b/env/eeprom.c
@@ -67,7 +67,7 @@ static int eeprom_bus_write(unsigned dev_addr, unsigned offset,
 static int env_eeprom_load(void)
 {
 	char buf_env[CONFIG_ENV_SIZE];
-	unsigned int off = CONFIG_ENV_OFFSET;
+	unsigned int off = env_get_offset(CONFIG_ENV_OFFSET);
 
 #ifdef CONFIG_ENV_OFFSET_REDUND
 	ulong len, crc[2], crc_tmp;
@@ -77,7 +77,7 @@ static int env_eeprom_load(void)
 
 	eeprom_init(-1);	/* prepare for EEPROM read/write */
 
-	off_env[0] = CONFIG_ENV_OFFSET;
+	off_env[0] = env_get_offset(CONFIG_ENV_OFFSET);
 	off_env[1] = CONFIG_ENV_OFFSET_REDUND;
 
 	for (i = 0; i < 2; i++) {
@@ -139,7 +139,7 @@ static int env_eeprom_load(void)
 
 	/* read old CRC */
 	eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR,
-			CONFIG_ENV_OFFSET + offsetof(env_t, crc),
+			env_get_offset(CONFIG_ENV_OFFSET) + offsetof(env_t, crc),
 			(uchar *)&crc, sizeof(ulong));
 
 	new = 0;
@@ -149,7 +149,7 @@ static int env_eeprom_load(void)
 		int n = (len > sizeof(rdbuf)) ? sizeof(rdbuf) : len;
 
 		eeprom_bus_read(CONFIG_SYS_I2C_EEPROM_ADDR,
-				CONFIG_ENV_OFFSET + off, rdbuf, n);
+				env_get_offset(CONFIG_ENV_OFFSET) + off, rdbuf, n);
 		new = crc32(new, rdbuf, n);
 		len -= n;
 		off += n;
@@ -162,7 +162,7 @@ static int env_eeprom_load(void)
 	}
 #endif /* CONFIG_ENV_OFFSET_REDUND */
 
-	off = CONFIG_ENV_OFFSET;
+	off = env_get_offset(CONFIG_ENV_OFFSET);
 #ifdef CONFIG_ENV_OFFSET_REDUND
 	if (gd->env_valid == ENV_REDUND)
 		off = CONFIG_ENV_OFFSET_REDUND;
@@ -178,7 +178,7 @@ static int env_eeprom_save(void)
 {
 	env_t	env_new;
 	int	rc;
-	unsigned int off	= CONFIG_ENV_OFFSET;
+	unsigned int off	= env_get_offset(CONFIG_ENV_OFFSET);
 #ifdef CONFIG_ENV_OFFSET_REDUND
 	unsigned int off_red	= CONFIG_ENV_OFFSET_REDUND;
 	char flag_obsolete	= ENV_REDUND_OBSOLETE;
@@ -191,7 +191,7 @@ static int env_eeprom_save(void)
 #ifdef CONFIG_ENV_OFFSET_REDUND
 	if (gd->env_valid == ENV_VALID) {
 		off	= CONFIG_ENV_OFFSET_REDUND;
-		off_red	= CONFIG_ENV_OFFSET;
+		off_red	= env_get_offset(CONFIG_ENV_OFFSET);
 	}
 
 	env_new.flags = ENV_REDUND_ACTIVE;
diff --git a/env/env.c b/env/env.c
index e4dfb92e154..7bb94dc8c17 100644
--- a/env/env.c
+++ b/env/env.c
@@ -381,3 +381,10 @@ int env_select(const char *name)
 
 	return -ENODEV;
 }
+
+#ifndef ENV_IS_EMBEDDED
+__weak long long env_get_offset(long long defautl_offset)
+{
+	return defautl_offset;
+}
+#endif
diff --git a/env/mmc.c b/env/mmc.c
index 465b104559b..f7da22a0589 100644
--- a/env/mmc.c
+++ b/env/mmc.c
@@ -94,7 +94,7 @@ static inline s64 mmc_offset(int copy)
 			return val;
 	}
 
-	defvalue = CONFIG_ENV_OFFSET;
+	defvalue = env_get_offset(CONFIG_ENV_OFFSET);
 	propname = dt_prop.offset;
 
 #if defined(CONFIG_ENV_OFFSET_REDUND)
@@ -108,7 +108,7 @@ static inline s64 mmc_offset(int copy)
 #else
 static inline s64 mmc_offset(int copy)
 {
-	s64 offset = CONFIG_ENV_OFFSET;
+	s64 offset = env_get_offset(CONFIG_ENV_OFFSET);
 
 #if defined(CONFIG_ENV_OFFSET_REDUND)
 	if (copy)
diff --git a/env/nand.c b/env/nand.c
index 21aa367d5bd..93989b5a478 100644
--- a/env/nand.c
+++ b/env/nand.c
@@ -153,7 +153,7 @@ static int writeenv(size_t offset, u_char *buf)
 
 struct nand_env_location {
 	const char *name;
-	const nand_erase_options_t erase_opts;
+	nand_erase_options_t erase_opts;
 };
 
 static int erase_and_write_env(const struct nand_env_location *location,
@@ -182,25 +182,17 @@ static int env_nand_save(void)
 	int	ret = 0;
 	ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1);
 	int	env_idx = 0;
-	static const struct nand_env_location location[] = {
-		{
-			.name = "NAND",
-			.erase_opts = {
-				.length = CONFIG_ENV_RANGE,
-				.offset = CONFIG_ENV_OFFSET,
-			},
-		},
+	static struct nand_env_location location[2] = {0};
+
+	location[0].name = "NAND";
+	location[0].erase_opts.length = CONFIG_ENV_RANGE;
+	location[0].erase_opts.offset = env_get_offset(CONFIG_ENV_OFFSET);
+
 #ifdef CONFIG_ENV_OFFSET_REDUND
-		{
-			.name = "redundant NAND",
-			.erase_opts = {
-				.length = CONFIG_ENV_RANGE,
-				.offset = CONFIG_ENV_OFFSET_REDUND,
-			},
-		},
+	location[1].name = "redundant NAND";
+	location[1].erase_opts.length = CONFIG_ENV_RANGE;
+	location[1].erase_opts.offset = CONFIG_ENV_OFFSET_REDUND;
 #endif
-	};
-
 
 	if (CONFIG_ENV_RANGE < CONFIG_ENV_SIZE)
 		return 1;
@@ -327,7 +319,7 @@ static int env_nand_load(void)
 		goto done;
 	}
 
-	read1_fail = readenv(CONFIG_ENV_OFFSET, (u_char *) tmp_env1);
+	read1_fail = readenv(env_get_offset(CONFIG_ENV_OFFSET), (u_char *) tmp_env1);
 	read2_fail = readenv(CONFIG_ENV_OFFSET_REDUND, (u_char *) tmp_env2);
 
 	ret = env_import_redund((char *)tmp_env1, read1_fail, (char *)tmp_env2,
@@ -366,7 +358,7 @@ static int env_nand_load(void)
 	}
 #endif
 
-	ret = readenv(CONFIG_ENV_OFFSET, (u_char *)buf);
+	ret = readenv(env_get_offset(CONFIG_ENV_OFFSET), (u_char *)buf);
 	if (ret) {
 		env_set_default("readenv() failed", 0);
 		return -EIO;
diff --git a/env/sata.c b/env/sata.c
index 9442cfcaf3c..586395b301b 100644
--- a/env/sata.c
+++ b/env/sata.c
@@ -15,6 +15,9 @@
 #include <memalign.h>
 #include <sata.h>
 #include <search.h>
+#ifdef CONFIG_DM_SCSI
+#include <scsi.h>
+#endif
 
 #if defined(CONFIG_ENV_OFFSET_REDUND)
 #error ENV REDUND not supported
@@ -49,12 +52,19 @@ static int env_sata_save(void)
 	struct blk_desc *sata = NULL;
 	int env_sata, ret;
 
+#ifndef CONFIG_DM_SCSI
 	if (sata_initialize())
 		return 1;
 
 	env_sata = sata_get_env_dev();
 
 	sata = sata_get_dev(env_sata);
+#else
+	scsi_scan(false);
+	env_sata = sata_get_env_dev();
+
+	sata = blk_get_dev("scsi", env_sata);
+#endif
 	if (sata == NULL) {
 		printf("Unknown SATA(%d) device for environment!\n",
 		       env_sata);
@@ -66,7 +76,7 @@ static int env_sata_save(void)
 		return 1;
 
 	printf("Writing to SATA(%d)...", env_sata);
-	if (write_env(sata, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, (u_char *)env_new)) {
+	if (write_env(sata, CONFIG_ENV_SIZE, env_get_offset(CONFIG_ENV_OFFSET), (u_char *)env_new)) {
 		puts("failed\n");
 		return 1;
 	}
@@ -89,24 +99,32 @@ static inline int read_env(struct blk_desc *sata, unsigned long size,
 	return (n == blk_cnt) ? 0 : -1;
 }
 
-static void env_sata_load(void)
+static int env_sata_load(void)
 {
 	ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
 	struct blk_desc *sata = NULL;
 	int env_sata;
 
+#ifndef CONFIG_DM_SCSI
 	if (sata_initialize())
 		return -EIO;
 
 	env_sata = sata_get_env_dev();
 
 	sata = sata_get_dev(env_sata);
+#else
+	scsi_scan(false);
+	env_sata = sata_get_env_dev();
+
+	sata = blk_get_dev("scsi", env_sata);
+#endif
+
 	if (sata == NULL) {
 		printf("Unknown SATA(%d) device for environment!\n", env_sata);
 		return -EIO;
 	}
 
-	if (read_env(sata, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, buf)) {
+	if (read_env(sata, CONFIG_ENV_SIZE, env_get_offset(CONFIG_ENV_OFFSET), buf)) {
 		env_set_default(NULL, 0);
 		return -EIO;
 	}
diff --git a/env/sf.c b/env/sf.c
index 6a4bb756f00..1001835f145 100644
--- a/env/sf.c
+++ b/env/sf.c
@@ -95,9 +95,9 @@ static int env_sf_save(void)
 
 	if (gd->env_valid == ENV_VALID) {
 		env_new_offset = CONFIG_ENV_OFFSET_REDUND;
-		env_offset = CONFIG_ENV_OFFSET;
+		env_offset = env_get_offset(CONFIG_ENV_OFFSET);
 	} else {
-		env_new_offset = CONFIG_ENV_OFFSET;
+		env_new_offset = env_get_offset(CONFIG_ENV_OFFSET);
 		env_offset = CONFIG_ENV_OFFSET_REDUND;
 	}
 
@@ -179,7 +179,7 @@ static int env_sf_load(void)
 	if (ret)
 		goto out;
 
-	read1_fail = spi_flash_read(env_flash, CONFIG_ENV_OFFSET,
+	read1_fail = spi_flash_read(env_flash, env_get_offset(CONFIG_ENV_OFFSET),
 				    CONFIG_ENV_SIZE, tmp_env1);
 	read2_fail = spi_flash_read(env_flash, CONFIG_ENV_OFFSET_REDUND,
 				    CONFIG_ENV_SIZE, tmp_env2);
@@ -214,7 +214,7 @@ static int env_sf_save(void)
 	/* Is the sector larger than the env (i.e. embedded) */
 	if (sect_size > CONFIG_ENV_SIZE) {
 		saved_size = sect_size - CONFIG_ENV_SIZE;
-		saved_offset = CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE;
+		saved_offset = env_get_offset(CONFIG_ENV_OFFSET) + CONFIG_ENV_SIZE;
 		saved_buffer = malloc(saved_size);
 		if (!saved_buffer)
 			goto done;
@@ -232,13 +232,13 @@ static int env_sf_save(void)
 	sector = DIV_ROUND_UP(CONFIG_ENV_SIZE, sect_size);
 
 	puts("Erasing SPI flash...");
-	ret = spi_flash_erase(env_flash, CONFIG_ENV_OFFSET,
+	ret = spi_flash_erase(env_flash, env_get_offset(CONFIG_ENV_OFFSET),
 		sector * sect_size);
 	if (ret)
 		goto done;
 
 	puts("Writing to SPI flash...");
-	ret = spi_flash_write(env_flash, CONFIG_ENV_OFFSET,
+	ret = spi_flash_write(env_flash, env_get_offset(CONFIG_ENV_OFFSET),
 		CONFIG_ENV_SIZE, &env_new);
 	if (ret)
 		goto done;
@@ -279,7 +279,7 @@ static int env_sf_load(void)
 		goto out;
 
 	ret = spi_flash_read(env_flash,
-		CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, buf);
+		env_get_offset(CONFIG_ENV_OFFSET), CONFIG_ENV_SIZE, buf);
 	if (ret) {
 		env_set_default("spi_flash_read() failed", 0);
 		goto err_read;
diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c
index 8ff2f6def08..53f3a5838f5 100644
--- a/fs/fat/fat_write.c
+++ b/fs/fat/fat_write.c
@@ -136,7 +136,7 @@ static int set_name(fat_itr *itr, const char *filename, char *shortname)
 
 	/* If filename and short name are the same, quit. */
 	sprintf(buf, "%.*s.%.3s", period_location, dirent.name, dirent.ext);
-	if (!strcmp(buf, filename)) {
+	if (!strncmp(buf, filename, strlen(filename))) {
 		ret = 1;
 		goto out;
 	}
diff --git a/include/android_bootloader_message.h b/include/android_bootloader_message.h
index 286d7ab0f31..0ba906803a3 100644
--- a/include/android_bootloader_message.h
+++ b/include/android_bootloader_message.h
@@ -28,10 +28,12 @@
 // 2K  - 16K    Used by Vendor's bootloader (the 2K - 4K range may be optionally used
 //              as bootloader_message_ab struct)
 // 16K - 64K    Used by uncrypt and recovery to store wipe_package for A/B devices
+// 32K - 64K    System space, used for miscellanious AOSP features. See below.
 // Note that these offsets are admitted by bootloader,recovery and uncrypt, so they
 // are not configurable without changing all of them.
 static const size_t BOOTLOADER_MESSAGE_OFFSET_IN_MISC = 0;
 static const size_t WIPE_PACKAGE_OFFSET_IN_MISC = 16 * 1024;
+static const size_t SYSTEM_SPACE_SIZE_IN_MISC = 32 * 1024;
 
 /* Bootloader Message (2-KiB)
  *
@@ -145,8 +147,16 @@ struct slot_metadata {
     // 1 if this slot is corrupted from a dm-verity corruption, 0
     // otherwise.
     uint8_t verity_corrupted : 1;
+#ifdef CONFIG_DUAL_BOOTLOADER
+    // 1 if the bootloader has been verified in spl stage, 0 otherwise.
+    // this is needed for dual bootloader case.
+    uint8_t bootloader_verified : 1;
+    // Reserved for further use.
+    uint8_t reserved : 6;
+#else
     // Reserved for further use.
     uint8_t reserved : 7;
+#endif
 } __attribute__((packed));
 
 /* Bootloader Control AB
@@ -172,8 +182,17 @@ struct bootloader_control {
     uint8_t reserved0[2];
     // Per-slot information.  Up to 4 slots.
     struct slot_metadata slot_info[4];
+#ifdef CONFIG_DUAL_BOOTLOADER
+    //Last boot slot
+    uint8_t last_boot;
+    //spl recovery mode
+    bool spl_recovery;
+    // Reserved for further use.
+    uint8_t reserved1[6];
+#else
     // Reserved for further use.
     uint8_t reserved1[8];
+#endif
     // CRC32 of all 28 bytes preceding this field (little endian
     // format).
     uint32_t crc32_le;
@@ -187,6 +206,17 @@ static_assert(sizeof(struct bootloader_control) ==
 #endif
 #endif /* __UBOOT__ */
 
+typedef struct misc_virtual_ab_message {
+  uint8_t version;
+  uint32_t magic;
+  uint8_t merge_status;  // IBootControl 1.1, MergeStatus enum.
+  uint8_t source_slot;   // Slot number when merge_status was written.
+  uint8_t reserved[57];
+} __attribute__((packed)) misc_virtual_ab_message;
+
+#define MISC_VIRTUAL_AB_MESSAGE_VERSION 2
+#define MISC_VIRTUAL_AB_MAGIC_HEADER 0x56740AB0
+
 #ifndef __UBOOT__
 #ifdef __cplusplus
 
diff --git a/include/android_image.h b/include/android_image.h
index 54d25af0684..e1c4f048b69 100644
--- a/include/android_image.h
+++ b/include/android_image.h
@@ -20,8 +20,33 @@
 #define ANDR_BOOT_ARGS_SIZE 512
 #define ANDR_BOOT_EXTRA_ARGS_SIZE 1024
 
+#define ANDR_VENDOR_BOOT_MAGIC "VNDRBOOT"
+#define ANDR_VENDOR_BOOT_MAGIC_SIZE 8
+#define ANDR_VENDOR_BOOT_ARGS_SIZE 2048
+#define ANDR_VENDOR_BOOT_NAME_SIZE 16
+
+#define VENDOR_RAMDISK_TYPE_NONE 0
+#define VENDOR_RAMDISK_TYPE_PLATFORM 1
+#define VENDOR_RAMDISK_TYPE_RECOVERY 2
+#define VENDOR_RAMDISK_TYPE_DLKM 3
+#define VENDOR_RAMDISK_NAME_SIZE 32
+#define VENDOR_RAMDISK_TABLE_ENTRY_BOARD_ID_SIZE 16
+
 /* The bootloader expects the structure of andr_img_hdr with header
  * version 0 to be as follows: */
+/* Boot metric variables (in millisecond) */
+struct boot_metric
+{
+	u32 bll_1;	/* 1th bootloader load duration */
+	u32 ble_1;	/* 1th bootloader exec duration */
+	u32 kl;		/* kernel image load duration */
+	u32 kd;		/* kernel image decompress duration */
+	u32 avb;	/* avb verify boot.img duration */
+	u32 odt;	/* overlay device tree duration */
+	u32 sw;		/* system wait for UI interaction duration*/
+};
+typedef struct boot_metric boot_metric;
+
 struct andr_img_hdr {
     /* Must be ANDR_BOOT_MAGIC. */
     char magic[ANDR_BOOT_MAGIC_SIZE];
@@ -67,22 +92,85 @@ struct andr_img_hdr {
     u64 dtb_addr; /* physical load address for DTB image */
 } __attribute__((packed));
 
+struct boot_img_hdr_v3 {
+    // Must be BOOT_MAGIC.
+    uint8_t magic[ANDR_BOOT_MAGIC_SIZE];
+
+    uint32_t kernel_size; /* size in bytes */
+    uint32_t ramdisk_size; /* size in bytes */
+
+    // Operating system version and security patch level.
+    // For version "A.B.C" and patch level "Y-M-D":
+    //   (7 bits for each of A, B, C; 7 bits for (Y-2000), 4 bits for M)
+    //   os_version = A[31:25] B[24:18] C[17:11] (Y-2000)[10:4] M[3:0]
+    uint32_t os_version;
+
+#if __cplusplus
+    void SetOsVersion(unsigned major, unsigned minor, unsigned patch) {
+        os_version &= ((1 << 11) - 1);
+        os_version |= (((major & 0x7f) << 25) | ((minor & 0x7f) << 18) | ((patch & 0x7f) << 11));
+    }
+
+    void SetOsPatchLevel(unsigned year, unsigned month) {
+        os_version &= ~((1 << 11) - 1);
+        os_version |= (((year - 2000) & 0x7f) << 4) | ((month & 0xf) << 0);
+    }
+#endif
+
+    uint32_t header_size;
+
+    uint32_t reserved[4];
+
+    // Version of the boot image header.
+    uint32_t header_version;
+
+    uint8_t cmdline[ANDR_BOOT_ARGS_SIZE + ANDR_BOOT_EXTRA_ARGS_SIZE];
+} __attribute__((packed));
+
+struct vendor_boot_img_hdr_v3 {
+    // Must be ANDR_VENDOR_BOOT_MAGIC.
+    uint8_t magic[ANDR_VENDOR_BOOT_MAGIC_SIZE];
+
+    // Version of the vendor boot image header.
+    uint32_t header_version;
+
+    uint32_t page_size; /* flash page size we assume */
+
+    uint32_t kernel_addr; /* physical load addr */
+    uint32_t ramdisk_addr; /* physical load addr */
+
+    uint32_t vendor_ramdisk_size; /* size in bytes */
+
+    uint8_t cmdline[ANDR_VENDOR_BOOT_ARGS_SIZE];
+
+    uint32_t tags_addr; /* physical addr for kernel tags (if required) */
+    uint8_t name[ANDR_VENDOR_BOOT_NAME_SIZE]; /* asciiz product name */
+
+    uint32_t header_size;
+
+    uint32_t dtb_size; /* size in bytes for DTB image */
+    uint64_t dtb_addr; /* physical load address for DTB image */
+} __attribute__((packed));
+
 /* When a boot header is of version 0, the structure of boot image is as
  * follows:
  *
  * +-----------------+
  * | boot header     | 1 page
  * +-----------------+
- * | kernel          | n pages
+ * | kernel          | i pages
  * +-----------------+
  * | ramdisk         | m pages
  * +-----------------+
- * | second stage    | o pages
+ * | second stage    | n pages
+ * +-----------------+
+ * | recovery dtbo   | o pages
  * +-----------------+
  *
- * n = (kernel_size + page_size - 1) / page_size
+ * i = (kernel_size + page_size - 1) / page_size
  * m = (ramdisk_size + page_size - 1) / page_size
- * o = (second_size + page_size - 1) / page_size
+ * n = (second_size + page_size - 1) / page_size
+ * o = (recovery_dtbo_size + page_size - 1) / page_size
  *
  * 0. all entities are page_size aligned in flash
  * 1. kernel and ramdisk are required (size != 0)
@@ -136,4 +224,229 @@ struct andr_img_hdr {
  *    else: jump to kernel_addr
  */
 
+/* When the boot image header has a version of 3, the structure of the boot
+ * image is as follows:
+ *
+ * +---------------------+
+ * | boot header         | 4096 bytes
+ * +---------------------+
+ * | kernel              | m pages
+ * +---------------------+
+ * | ramdisk             | n pages
+ * +---------------------+
+ *
+ * m = (kernel_size + 4096 - 1) / 4096
+ * n = (ramdisk_size + 4096 - 1) / 4096
+ *
+ * Note that in version 3 of the boot image header, page size is fixed at 4096 bytes.
+ *
+ * The structure of the vendor boot image (introduced with version 3 and
+ * required to be present when a v3 boot image is used) is as follows:
+ *
+ * +---------------------+
+ * | vendor boot header  | o pages
+ * +---------------------+
+ * | vendor ramdisk      | p pages
+ * +---------------------+
+ * | dtb                 | q pages
+ * +---------------------+
+
+ * o = (2112 + page_size - 1) / page_size
+ * p = (vendor_ramdisk_size + page_size - 1) / page_size
+ * q = (dtb_size + page_size - 1) / page_size
+ *
+ * 0. all entities in the boot image are 4096-byte aligned in flash, all
+ *    entities in the vendor boot image are page_size (determined by the vendor
+ *    and specified in the vendor boot image header) aligned in flash
+ * 1. kernel, ramdisk, vendor ramdisk, and DTB are required (size != 0)
+ * 2. load the kernel and DTB at the specified physical address (kernel_addr,
+ *    dtb_addr)
+ * 3. load the vendor ramdisk at ramdisk_addr
+ * 4. load the generic ramdisk immediately following the vendor ramdisk in
+ *    memory
+ * 5. set up registers for kernel entry as required by your architecture
+ * 6. if the platform has a second stage bootloader jump to it (must be
+ *    contained outside boot and vendor boot partitions), otherwise
+ *    jump to kernel_addr
+ */
+
+/* When the boot image header has a version of 4, the structure of the boot
+ * image is as follows:
+ *
+ * +---------------------+
+ * | boot header         | 4096 bytes
+ * +---------------------+
+ * | kernel              | m pages
+ * +---------------------+
+ * | ramdisk             | n pages
+ * +---------------------+
+ * | boot signature      | g pages
+ * +---------------------+
+ *
+ * m = (kernel_size + 4096 - 1) / 4096
+ * n = (ramdisk_size + 4096 - 1) / 4096
+ * g = (signature_size + 4096 - 1) / 4096
+ *
+ * Note that in version 4 of the boot image header, page size is fixed at 4096
+ * bytes.
+ *
+ * The structure of the vendor boot image version 4, which is required to be
+ * present when a version 4 boot image is used, is as follows:
+ *
+ * +------------------------+
+ * | vendor boot header     | o pages
+ * +------------------------+
+ * | vendor ramdisk section | p pages
+ * +------------------------+
+ * | dtb                    | q pages
+ * +------------------------+
+ * | vendor ramdisk table   | r pages
+ * +------------------------+
+ * | bootconfig             | s pages
+ * +------------------------+
+ *
+ * o = (2128 + page_size - 1) / page_size
+ * p = (vendor_ramdisk_size + page_size - 1) / page_size
+ * q = (dtb_size + page_size - 1) / page_size
+ * r = (vendor_ramdisk_table_size + page_size - 1) / page_size
+ * s = (vendor_bootconfig_size + page_size - 1) / page_size
+ *
+ * Note that in version 4 of the vendor boot image, multiple vendor ramdisks can
+ * be included in the vendor boot image. The bootloader can select a subset of
+ * ramdisks to load at runtime. To help the bootloader select the ramdisks, each
+ * ramdisk is tagged with a type tag and a set of hardware identifiers
+ * describing the board, soc or platform that this ramdisk is intended for.
+ *
+ * The vendor ramdisk section is consist of multiple ramdisk images concatenated
+ * one after another, and vendor_ramdisk_size is the size of the section, which
+ * is the total size of all the ramdisks included in the vendor boot image.
+ *
+ * The vendor ramdisk table holds the size, offset, type, name and hardware
+ * identifiers of each ramdisk. The type field denotes the type of its content.
+ * The vendor ramdisk names are unique. The hardware identifiers are specified
+ * in the board_id field in each table entry. The board_id field is consist of a
+ * vector of unsigned integer words, and the encoding scheme is defined by the
+ * hardware vendor.
+ *
+ * For the different type of ramdisks, there are:
+ *    - VENDOR_RAMDISK_TYPE_NONE indicates the value is unspecified.
+ *    - VENDOR_RAMDISK_TYPE_PLATFORM ramdisks contain platform specific bits, so
+ *      the bootloader should always load these into memory.
+ *    - VENDOR_RAMDISK_TYPE_RECOVERY ramdisks contain recovery resources, so
+ *      the bootloader should load these when booting into recovery.
+ *    - VENDOR_RAMDISK_TYPE_DLKM ramdisks contain dynamic loadable kernel
+ *      modules.
+ *
+ * Version 4 of the vendor boot image also adds a bootconfig section to the end
+ * of the image. This section contains Boot Configuration parameters known at
+ * build time. The bootloader is responsible for placing this section directly
+ * after the generic ramdisk, followed by the bootconfig trailer, before
+ * entering the kernel.
+ *
+ * 0. all entities in the boot image are 4096-byte aligned in flash, all
+ *    entities in the vendor boot image are page_size (determined by the vendor
+ *    and specified in the vendor boot image header) aligned in flash
+ * 1. kernel, ramdisk, and DTB are required (size != 0)
+ * 2. load the kernel and DTB at the specified physical address (kernel_addr,
+ *    dtb_addr)
+ * 3. load the vendor ramdisks at ramdisk_addr
+ * 4. load the generic ramdisk immediately following the vendor ramdisk in
+ *    memory
+ * 5. load the bootconfig immediately following the generic ramdisk. Add
+ *    additional bootconfig parameters followed by the bootconfig trailer.
+ * 6. set up registers for kernel entry as required by your architecture
+ * 7. if the platform has a second stage bootloader jump to it (must be
+ *    contained outside boot and vendor boot partitions), otherwise
+ *    jump to kernel_addr
+ */
+struct boot_img_hdr_v4 {
+    // Must be BOOT_MAGIC.
+    uint8_t magic[ANDR_BOOT_MAGIC_SIZE];
+
+    uint32_t kernel_size; /* size in bytes */
+    uint32_t ramdisk_size; /* size in bytes */
+
+    // Operating system version and security patch level.
+    // For version "A.B.C" and patch level "Y-M-D":
+    //   (7 bits for each of A, B, C; 7 bits for (Y-2000), 4 bits for M)
+    //   os_version = A[31:25] B[24:18] C[17:11] (Y-2000)[10:4] M[3:0]
+    uint32_t os_version;
+
+#if __cplusplus
+    void SetOsVersion(unsigned major, unsigned minor, unsigned patch) {
+        os_version &= ((1 << 11) - 1);
+        os_version |= (((major & 0x7f) << 25) | ((minor & 0x7f) << 18) | ((patch & 0x7f) << 11));
+    }
+
+    void SetOsPatchLevel(unsigned year, unsigned month) {
+        os_version &= ~((1 << 11) - 1);
+        os_version |= (((year - 2000) & 0x7f) << 4) | ((month & 0xf) << 0);
+    }
+#endif
+
+    uint32_t header_size;
+
+    uint32_t reserved[4];
+
+    // Version of the boot image header.
+    uint32_t header_version;
+
+    uint8_t cmdline[ANDR_BOOT_ARGS_SIZE + ANDR_BOOT_EXTRA_ARGS_SIZE];
+
+    uint32_t signature_size; /* size in bytes */
+} __attribute__((packed));
+
+struct vendor_boot_img_hdr_v4 {
+    // Must be ANDR_VENDOR_BOOT_MAGIC.
+    uint8_t magic[ANDR_VENDOR_BOOT_MAGIC_SIZE];
+
+    // Version of the vendor boot image header.
+    uint32_t header_version;
+
+    uint32_t page_size; /* flash page size we assume */
+
+    uint32_t kernel_addr; /* physical load addr */
+    uint32_t ramdisk_addr; /* physical load addr */
+
+    uint32_t vendor_ramdisk_size; /* size in bytes */
+
+    uint8_t cmdline[ANDR_VENDOR_BOOT_ARGS_SIZE];
+
+    uint32_t tags_addr; /* physical addr for kernel tags (if required) */
+    uint8_t name[ANDR_VENDOR_BOOT_NAME_SIZE]; /* asciiz product name */
+
+    uint32_t header_size;
+
+    uint32_t dtb_size; /* size in bytes for DTB image */
+    uint64_t dtb_addr; /* physical load address for DTB image */
+
+    uint32_t vendor_ramdisk_table_size; /* size in bytes for the vendor ramdisk table */
+    uint32_t vendor_ramdisk_table_entry_num; /* number of entries in the vendor ramdisk table */
+    uint32_t vendor_ramdisk_table_entry_size; /* size in bytes for a vendor ramdisk table entry */
+    uint32_t bootconfig_size; /* size in bytes for the bootconfig section */
+} __attribute__((packed));
+
+struct vendor_ramdisk_table_entry_v4 {
+    uint32_t ramdisk_size; /* size in bytes for the ramdisk image */
+    uint32_t ramdisk_offset; /* offset to the ramdisk image in vendor ramdisk section */
+    uint32_t ramdisk_type; /* type of the ramdisk */
+    uint8_t ramdisk_name[VENDOR_RAMDISK_NAME_SIZE]; /* asciiz ramdisk name */
+
+    // Hardware identifiers describing the board, soc or platform which this
+    // ramdisk is intended to be loaded on.
+    uint32_t board_id[VENDOR_RAMDISK_TABLE_ENTRY_BOARD_ID_SIZE];
+} __attribute__((packed));
+
+struct header_image {
+	uint32_t	code0;		/* Executable code */
+	uint32_t	code1;		/* Executable code */
+	uint64_t	text_offset;	/* Image load offset, LE */
+	uint64_t	image_size;	/* Effective Image size, LE */
+	uint64_t	res1;		/* reserved */
+	uint64_t	res2;		/* reserved */
+	uint64_t	res3;		/* reserved */
+	uint64_t	res4;		/* reserved */
+	uint32_t	magic;		/* Magic number */
+	uint32_t	res5;
+};
 #endif
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index adc19e9765d..4ab4625e3b1 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -127,6 +127,8 @@ struct gpio_desc {
 #define GPIOD_OPEN_SOURCE	BIT(6)	/* GPIO is open source type */
 #define GPIOD_PULL_UP		BIT(7)	/* GPIO has pull-up enabled */
 #define GPIOD_PULL_DOWN		BIT(8)	/* GPIO has pull-down enabled */
+#define GPIOD_MASK_DIR		(GPIOD_IS_OUT | GPIOD_IS_IN | \
+					GPIOD_IS_OUT_ACTIVE)
 
 /* Flags for updating the above */
 #define GPIOD_MASK_DIR		(GPIOD_IS_OUT | GPIOD_IS_IN | \
diff --git a/include/command.h b/include/command.h
index 0cf12fde396..e89f4a23e06 100644
--- a/include/command.h
+++ b/include/command.h
@@ -203,6 +203,10 @@ int do_env_set_efi(struct cmd_tbl *cmdtp, int flag, int argc,
 int setexpr_regex_sub(char *data, uint data_size, char *nbuf, uint nbuf_size,
 		      const char *r, const char *s, bool global);
 
+#ifdef CONFIG_CMD_READ
+int do_raw_read(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
+#endif
+
 /*
  * Error codes that commands return to cmd_process(). We use the standard 0
  * and 1 for success and failure, but add one more case - failure with a
diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h
index af7e3e49fdd..1bda7704c9e 100644
--- a/include/config_uncmd_spl.h
+++ b/include/config_uncmd_spl.h
@@ -14,6 +14,8 @@
 #undef CONFIG_DM_SERIAL
 #undef CONFIG_DM_I2C
 #undef CONFIG_DM_SPI
+#undef CONFIG_DM_SPI_FLASH
+#undef CONFIG_DM_USB
 #endif
 
 #undef CONFIG_DM_STDIO
diff --git a/include/configs/imx8dxl_evk.h b/include/configs/imx8dxl_evk.h
new file mode 100644
index 00000000000..9e21d4feaaa
--- /dev/null
+++ b/include/configs/imx8dxl_evk.h
@@ -0,0 +1,292 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __IMX8DXL_EVK_H
+#define __IMX8DXL_EVK_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#include "imx_env.h"
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_MAX_SIZE				(128 * 1024)
+#define CONFIG_SYS_MONITOR_LEN				(1024 * 1024)
+
+/*
+ * 0x08081000 - 0x08180FFF is for m4_0 xip image,
+  * So 3rd container image may start from 0x8181000
+ */
+#define CONFIG_SYS_UBOOT_BASE 0x08181000
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS     (0x8000000)  /*Put the FIT out of first 128MB boot area */
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_IDENT
+
+#define CONFIG_SPL_STACK		0x822ffff0
+#define CONFIG_SPL_BSS_START_ADDR      0x82280000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x1000	/* 4 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x82200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x80000	/* 512 KB */
+#define CONFIG_SERIAL_LPUART_BASE	0x5a060000
+#define CONFIG_MALLOC_F_ADDR		0x82200000
+
+#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_CMD_READ
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+#define USDHC1_BASE_ADDR                0x5B010000
+#define USDHC2_BASE_ADDR                0x5B020000
+
+#define CONFIG_PCIE_IMX
+#define CONFIG_CMD_PCI
+#define CONFIG_PCI_SCAN_SHOW
+
+#ifdef CONFIG_AHAB_BOOT
+#define AHAB_ENV "sec_boot=yes\0"
+#else
+#define AHAB_ENV "sec_boot=no\0"
+#endif
+
+/* Boot M4 */
+#define M4_BOOT_ENV \
+	"m4_0_image=m4_0.bin\0" \
+	"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
+	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)"
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x83100000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"emmc_dev=0\0" \
+	"sd_dev=1\0"
+
+#define JAILHOUSE_ENV \
+	"jh_mmcboot=" \
+		"setenv fdt_file imx8dxl-evk-root.dtb;"\
+		"setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \
+		"run mmcboot; \0" \
+	"jh_netboot=" \
+		"setenv fdt_file imx8dxl-evk-root.dtb;"\
+		"setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \
+		"run netboot; \0"
+
+#define XEN_BOOT_ENV \
+            "xenhyper_bootargs=console=dtuart dtuart=/serial@5a060000 dom0_mem=1024M dom0_max_vcpus=2 dom0_vcpus_pin=true\0" \
+            "xenlinux_bootargs= \0" \
+            "xenlinux_console=hvc0 earlycon=xen\0" \
+            "xenlinux_addr=0x9e000000\0" \
+			"dom0fdt_file=imx8dxl-evk-dom0.dtb\0" \
+            "xenboot_common=" \
+                "${get_cmd} ${loadaddr} xen;" \
+                "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \
+                "${get_cmd} ${xenlinux_addr} ${image};" \
+                "fdt addr ${fdt_addr};" \
+                "fdt resize 256;" \
+                "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \
+                "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \
+                "setenv bootargs ${xenhyper_bootargs};" \
+                "booti ${loadaddr} - ${fdt_addr};" \
+            "\0" \
+            "xennetboot=" \
+                "setenv get_cmd dhcp;" \
+                "setenv console ${xenlinux_console};" \
+                "run netargs;" \
+                "run xenboot_common;" \
+            "\0" \
+            "xenmmcboot=" \
+                "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \
+                "setenv console ${xenlinux_console};" \
+                "run mmcargs;" \
+                "run xenboot_common;" \
+            "\0" \
+
+/* Initial environment variables */
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
+	"bootargs=console=ttyLP0,115200 ubi.mtd=nandrootfs "  \
+		"root=ubi0:nandrootfs rootfstype=ubifs "		     \
+		MFG_NAND_PARTITION \
+		"\0"\
+	"console=ttyLP0,115200 earlycon\0" \
+	"mtdparts=" MFG_NAND_PARTITION "\0" \
+	"fdt_addr=0x83000000\0"
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
+	M4_BOOT_ENV \
+	XEN_BOOT_ENV \
+	JAILHOUSE_ENV\
+	AHAB_ENV \
+	"script=boot.scr\0" \
+	"image=Image\0" \
+	"splashimage=0x9e000000\0" \
+	"console=ttyLP0\0" \
+	"fdt_addr=0x83000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"cntr_addr=0x98000000\0"			\
+	"cntr_file=os_cntr_signed.bin\0" \
+	"boot_fdt=try\0" \
+	"fdt_file=undefined\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} earlycon root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
+	"auth_os=auth_cntr ${cntr_addr}\0" \
+	"boot_os=booti ${loadaddr} - ${fdt_addr};\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${sec_boot} = yes; then " \
+			"if run auth_os; then " \
+				"run boot_os; " \
+			"else " \
+				"echo ERR: failed to authenticate; " \
+			"fi; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if run loadfdt; then " \
+					"run boot_os; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"else " \
+				"echo wait for boot; " \
+			"fi;" \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} earlycon " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if test ${sec_boot} = yes; then " \
+			"${get_cmd} ${cntr_addr} ${cntr_file}; " \
+			"if run auth_os; then " \
+				"run boot_os; " \
+			"else " \
+				"echo ERR: failed to authenticate; " \
+			"fi; " \
+		"else " \
+			"${get_cmd} ${loadaddr} ${image}; " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+					"run boot_os; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"else " \
+				"booti; " \
+			"fi;" \
+		"fi;\0"
+#endif
+
+/* Link Definitions */
+
+#define CONFIG_SYS_INIT_SP_ADDR         0x80200000
+
+
+/* USDHC2 for SD */
+#define CONFIG_SYS_MMC_ENV_DEV      1   /* USDHC2 */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_2			0x880000000
+
+/* total DDR is 1GB */
+#if defined(CONFIG_TARGET_IMX8DXL_DDR3_EVK)
+#define PHYS_SDRAM_1_SIZE		0x1FF00000	/* 512MB - ECC region 1MB */
+#else
+#define PHYS_SDRAM_1_SIZE		0x3FE00000	/* 1 GB - ECC region 2MB */
+#endif
+
+#define PHYS_SDRAM_2_SIZE		0x00000000
+
+/* Serial */
+#define CONFIG_BAUDRATE			115200
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_CBSIZE              2048
+#define CONFIG_SYS_MAXARGS             64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		8000000	/* 8MHz */
+
+#ifndef CONFIG_DM_PCA953X
+#define CONFIG_PCA953X
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#endif
+
+#define CONFIG_SERIAL_TAG
+
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x40000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+
+#endif
+
+/* USB Config */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_USBD_HS
+
+#endif
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/* USB OTG controller configs */
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#endif
+
+/* Networking */
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define FEC_QUIRK_ENET_MAC
+#define CONFIG_FEC_MXC_PHYADDR          0x1
+
+#define DWC_NET_PHYADDR			0
+
+#define CONFIG_ETHPRIME                 "eth1"
+#define PHY_ANEG_TIMEOUT 20000
+
+#if defined(CONFIG_DM_VIDEO)
+#define CONFIG_VIDEO_LINK
+#endif
+
+#endif /* __IMX8DXL_EVK_H */
diff --git a/include/configs/imx8dxl_phantom_mek.h b/include/configs/imx8dxl_phantom_mek.h
new file mode 100644
index 00000000000..1231012ec32
--- /dev/null
+++ b/include/configs/imx8dxl_phantom_mek.h
@@ -0,0 +1,255 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __IMX8DXL_PHANTOM_MEK_H
+#define __IMX8DXL_PHANTOM_MEK_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#include "imx_env.h"
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_MAX_SIZE				(192 * 1024)
+#define CONFIG_SYS_MONITOR_LEN				(1024 * 1024)
+
+/*
+ * 0x08081000 - 0x08180FFF is for m4_0 xip image,
+  * So 3rd container image may start from 0x8181000
+ */
+#define CONFIG_SYS_UBOOT_BASE 0x08181000
+
+/*
+ * The memory layout on stack:  DATA section save + gd + early malloc
+ * the idea is re-use the early malloc (CONFIG_SYS_MALLOC_F_LEN) with
+ * CONFIG_SYS_SPL_MALLOC_START
+ */
+#define CONFIG_SPL_STACK		0x013fff0
+#define CONFIG_SPL_BSS_START_ADDR      0x00130000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x1000	/* 4 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x82200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x80000	/* 512 KB */
+#define CONFIG_SERIAL_LPUART_BASE	0x5a060000
+#define CONFIG_MALLOC_F_ADDR		0x00138000
+
+#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_CMD_READ
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+#define USDHC1_BASE_ADDR                0x5B010000
+#define USDHC2_BASE_ADDR                0x5B020000
+
+#define CONFIG_PCIE_IMX
+#define CONFIG_CMD_PCI
+#define CONFIG_PCI_SCAN_SHOW
+
+#ifdef CONFIG_AHAB_BOOT
+#define AHAB_ENV "sec_boot=yes\0"
+#else
+#define AHAB_ENV "sec_boot=no\0"
+#endif
+
+/* Boot M4 */
+#define M4_BOOT_ENV \
+	"m4_0_image=m4_0.bin\0" \
+	"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
+	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x83100000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"emmc_dev=0\0" \
+	"sd_dev=1\0"
+
+#define JAILHOUSE_ENV \
+	"jh_mmcboot=" \
+		"setenv fdt_file imx8qxp-mek-root.dtb;"\
+		"setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \
+		"run mmcboot; \0" \
+	"jh_netboot=" \
+		"setenv fdt_file imx8qxp-mek-root.dtb;"\
+		"setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \
+		"run netboot; \0"
+
+#define XEN_BOOT_ENV \
+            "xenhyper_bootargs=console=dtuart dtuart=/serial@5a060000 dom0_mem=1024M dom0_max_vcpus=2 dom0_vcpus_pin=true\0" \
+            "xenlinux_bootargs= \0" \
+            "xenlinux_console=hvc0 earlycon=xen\0" \
+            "xenlinux_addr=0x9e000000\0" \
+            "dom0fdt_file=imx8qxp-mek-dom0.dtb\0" \
+            "xenboot_common=" \
+                "${get_cmd} ${loadaddr} xen;" \
+                "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \
+                "${get_cmd} ${xenlinux_addr} ${image};" \
+                "fdt addr ${fdt_addr};" \
+                "fdt resize 256;" \
+                "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \
+                "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \
+                "setenv bootargs ${xenhyper_bootargs};" \
+                "booti ${loadaddr} - ${fdt_addr};" \
+            "\0" \
+            "xennetboot=" \
+                "setenv get_cmd dhcp;" \
+                "setenv console ${xenlinux_console};" \
+                "run netargs;" \
+                "run xenboot_common;" \
+            "\0" \
+            "xenmmcboot=" \
+                "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \
+                "setenv console ${xenlinux_console};" \
+                "run mmcargs;" \
+                "run xenboot_common;" \
+            "\0" \
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
+	M4_BOOT_ENV \
+	XEN_BOOT_ENV \
+	JAILHOUSE_ENV\
+	AHAB_ENV \
+	"script=boot.scr\0" \
+	"image=Image\0" \
+	"panel=NULL\0" \
+	"console=ttyLP0\0" \
+	"fdt_addr=0x83000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"cntr_addr=0x98000000\0"			\
+	"cntr_file=os_cntr_signed.bin\0" \
+	"boot_fdt=try\0" \
+	"fdt_file=undefined\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} earlycon root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
+	"auth_os=auth_cntr ${cntr_addr}\0" \
+	"boot_os=booti ${loadaddr} - ${fdt_addr};\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${sec_boot} = yes; then " \
+			"if run auth_os; then " \
+				"run boot_os; " \
+			"else " \
+				"echo ERR: failed to authenticate; " \
+			"fi; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if run loadfdt; then " \
+					"run boot_os; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"else " \
+				"echo wait for boot; " \
+			"fi;" \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} earlycon " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if test ${sec_boot} = yes; then " \
+			"${get_cmd} ${cntr_addr} ${cntr_file}; " \
+			"if run auth_os; then " \
+				"run boot_os; " \
+			"else " \
+				"echo ERR: failed to authenticate; " \
+			"fi; " \
+		"else " \
+			"${get_cmd} ${loadaddr} ${image}; " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+					"run boot_os; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"else " \
+				"booti; " \
+			"fi;" \
+		"fi;\0"
+
+/* Link Definitions */
+
+#define CONFIG_SYS_INIT_SP_ADDR         0x80200000
+
+/* USDHC1 is for eMMC, USDHC2 is for SD. However SD can't boot due to pinmux in ROM */
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC1 */
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_2			0x880000000
+
+/* total DDR is 1GB */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1 GB */
+#define PHYS_SDRAM_2_SIZE		0x00000000
+
+/* Serial */
+#define CONFIG_BAUDRATE			115200
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_CBSIZE              2048
+#define CONFIG_SYS_MAXARGS             64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		8000000	/* 8MHz */
+
+#ifndef CONFIG_DM_PCA953X
+#define CONFIG_PCA953X
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#endif
+
+#define CONFIG_SERIAL_TAG
+
+/* USB Config */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_USBD_HS
+
+#endif
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+/* USB OTG controller configs */
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#endif
+
+/* Networking */
+#define IMX_FEC_BASE			0x5B050000
+#define CONFIG_FEC_MXC_PHYADDR          0x0
+#define CONFIG_ETHPRIME                 "eth1"
+
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define PHY_ANEG_TIMEOUT 20000
+
+
+#endif /* __IMX8DXL_PHANTOM_MEK_H */
diff --git a/include/configs/imx8mm_ab2.h b/include/configs/imx8mm_ab2.h
new file mode 100644
index 00000000000..2c78005afe6
--- /dev/null
+++ b/include/configs/imx8mm_ab2.h
@@ -0,0 +1,303 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __IMX8MM_AB2_H
+#define __IMX8MM_AB2_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+#include "imx_env.h"
+
+#define CONFIG_SYS_BOOTM_LEN		(64 * SZ_1M)
+#define CONFIG_SPL_MAX_SIZE		(148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		SZ_512K
+#define CONFIG_SYS_UBOOT_BASE	\
+	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK		0x920000
+#define CONFIG_SPL_BSS_START_ADDR	0x910000
+#define CONFIG_MALLOC_F_ADDR		0x930000
+#define CONFIG_SPL_BSS_MAX_SIZE		SZ_8K	/* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_512K	/* 512 KB */
+
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#if defined(CONFIG_IMX8M_LPDDR4) && defined(CONFIG_TARGET_IMX8MM_AB2)
+#define CONFIG_POWER_PCA9450
+#else
+#define CONFIG_POWER_BD71837
+#endif
+
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_IDENT
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 	0x4000000 /* Put the FIT out of first 64MB boot area */
+
+/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
+	(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
+#endif
+
+#endif
+
+#define CONFIG_CMD_READ
+#define CONFIG_SERIAL_TAG
+#define CONFIG_FASTBOOT_USB_DEV 0
+
+#define CONFIG_REMAKE_ELF
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_FEC_MXC)
+#define CONFIG_ETHPRIME                 "FEC"
+#define PHY_ANEG_TIMEOUT 20000
+
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_FEC_MXC_PHYADDR          0
+
+#define IMX_FEC_BASE			0x30BE0000
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)"
+#endif
+
+#ifdef CONFIG_DISTRO_DEFAULTS
+#define BOOT_TARGET_DEVICES(func) \
+	func(USB, usb, 0) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 2)
+
+#include <config_distro_bootcmd.h>
+#else
+#define BOOTENV
+#endif
+
+/*
+ * Another approach is add the clocks for inmates into clks_init_on
+ * in clk-imx8mm.c, then clk_ingore_unused could be removed.
+ */
+#define JH_ROOT_DTB    "imx8mm-ab2-root.dtb"
+
+#define JAILHOUSE_ENV \
+	"jh_clk= \0 " \
+	"jh_root_dtb=" JH_ROOT_DTB "\0" \
+	"jh_mmcboot=mw 0x303d0518 0xff; setenv fdtfile ${jh_root_dtb};" \
+		"setenv jh_clk clk_ignore_unused mem=1212MB; " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run jh_netboot; fi; \0" \
+	"jh_netboot=mw 0x303d0518 0xff; setenv fdtfile ${jh_root_dtb}; setenv jh_clk clk_ignore_unused mem=1212MB; run netboot; \0 "
+
+#define M4_BOOT_ENV \
+	"m4_boot=no\0" \
+	"m4_image=nxh3670.itb\0" \
+	"m4_loadaddr=0x80000000\0" \
+	"m4_nxh_app_loadaddr=0x81000000\0" \
+	"m4_nxh_rfmac_loadaddr=0x81012000\0" \
+	"m4_nxh_cf_loadaddr=0x81016000\0" \
+	"m4_nxh_data_loadaddr=0x8101E000\0" \
+	"m4_sf_loadaddr=0x08100000\0" \
+	"m4_fdt_file=imx8mm-ab2-m4.dtb\0" \
+	"m4_nxh_bin=main@1\0" \
+	"m4_nxh_app=app@1\0" \
+	"m4_nxh_rfmac=rfmac@1\0" \
+	"m4_nxh_cf=cf@1\0" \
+	"m4_nxh_data=data@1\0" \
+	"loadm4nxhfw=imxtract ${loadaddr} ${m4_nxh_bin} ${m4_loadaddr}; " \
+		"imxtract ${loadaddr} ${m4_nxh_app} ${m4_nxh_app_loadaddr}; " \
+		"imxtract ${loadaddr} ${m4_nxh_rfmac} ${m4_nxh_rfmac_loadaddr}; " \
+		"imxtract ${loadaddr} ${m4_nxh_cf} ${m4_nxh_cf_loadaddr}; " \
+		"imxtract ${loadaddr} ${m4_nxh_data} ${m4_nxh_data_loadaddr}\0" \
+	"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_image}\0" \
+	"update_m4_from_sd=" \
+		"if sf probe 0:0; then " \
+			"if run loadm4image; then " \
+				"setexpr fw_sz ${filesize} + 0xffff; " \
+				"setexpr fw_sz ${fw_sz} / 0x10000; " \
+				"setexpr fw_sz ${fw_sz} * 0x10000; " \
+				"sf erase 0x100000 ${fw_sz}; " \
+				"sf write ${m4_loadaddr} 0x100000 ${filesize}; " \
+			"fi; " \
+		"fi\0" \
+	"m4boot=run loadm4image; run loadm4nxhfw; dcache flush; bootaux ${m4_loadaddr}\0" \
+	"m4netboot=${get_cmd} ${loaddadr} ${m4_image}; " \
+		"run loadm4nxhfw; dcache flush; bootaux ${m4_loadaddr}; \0" \
+	"m4boot_sf=sf probe 0:0; dcache flush; bootaux ${m4_sf_loadaddr}\0"
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x43800000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"emmc_dev=2\0"\
+	"sd_dev=1\0" \
+
+/* Initial environment variables */
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	"splashimage=0x50000000\0" \
+	"fdt_addr_r=0x43000000\0"			\
+	"fdt_addr=0x43000000\0"			\
+	"fdt_high=0xffffffffffffffff\0" \
+	"mtdparts=" MFG_NAND_PARTITION "\0" \
+	"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
+	"bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=nandrootfs "  \
+		"root=ubi0:nandrootfs rootfstype=ubifs "		     \
+		MFG_NAND_PARTITION \
+		"\0" \
+	"bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\
+		"nand read ${fdt_addr_r} 0x7000000 0x100000;"\
+		"booti ${loadaddr} - ${fdt_addr_r}"
+
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
+	BOOTENV \
+	JAILHOUSE_ENV \
+	M4_BOOT_ENV \
+	"scriptaddr=0x43500000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"bsp_script=boot.scr\0" \
+	"image=Image\0" \
+	"splashimage=0x50000000\0" \
+	"console=ttymxc1,115200\0" \
+	"fdt_addr_r=0x43000000\0"			\
+	"fdt_addr=0x43000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"boot_fit=no\0" \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"bootm_size=0x10000000\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${m4_boot} = yes || test ${m4_boot} = try; then "\
+			"echo Booting M4 aux core...; " \
+			"run m4boot; " \
+		"fi; " \
+		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+			"bootm ${loadaddr}; " \
+		"else " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr_r}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"fi;\0" \
+	"netargs=setenv bootargs ${jh_clk} console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if test ${m4_boot} = yes || test ${m4_boot} = try; then " \
+			"echo Booting M4 aux core...;" \
+			"run m4netboot;" \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+			"bootm ${loadaddr}; " \
+		"else " \
+			"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
+				"booti ${loadaddr} - ${fdt_addr_r}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"fi;\0" \
+	"bsp_bootcmd=echo Running BSP bootcmd ...; " \
+		"mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "fi;"
+#endif
+
+/* Link Definitions */
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x200000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+
+#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define PHYS_SDRAM                      0x40000000
+#define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
+
+#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		2048
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_IMX_BOOTAUX
+
+/* USDHC */
+
+#ifdef CONFIG_TARGET_IMX8MM_DDR4_AB2
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#else
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#endif
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+
+#ifdef CONFIG_FSL_FSPI
+#define FSL_FSPI_FLASH_SIZE		SZ_32M
+#define FSL_FSPI_FLASH_NUM		1
+#define FSPI0_BASE_ADDR			0x30bb0000
+#define FSPI0_AMBA_BASE			0x0
+#define CONFIG_FSPI_QUAD_SUPPORT
+
+#define CONFIG_SYS_FSL_FSPI_AHB
+#endif
+
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x20000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#endif /* CONFIG_NAND_MXS */
+
+/* USB configs */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_USBD_HS
+#endif
+
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         2
+
+#endif
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
index c7022ef0f7f..3d992ffa134 100644
--- a/include/configs/imx8mm_evk.h
+++ b/include/configs/imx8mm_evk.h
@@ -9,6 +9,7 @@
 #include <linux/sizes.h>
 #include <linux/stringify.h>
 #include <asm/arch/imx-regs.h>
+#include "imx_env.h"
 
 #define CONFIG_SYS_BOOTM_LEN		(64 * SZ_1M)
 #define CONFIG_SPL_MAX_SIZE		(148 * 1024)
@@ -28,31 +29,166 @@
 /* For RAW image gives a error info not panic */
 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
 
+#if defined(CONFIG_IMX8M_LPDDR4) && defined(CONFIG_TARGET_IMX8MM_EVK)
+#define CONFIG_POWER_PCA9450
+#else
+#define CONFIG_POWER_BD71837
 #endif
 
-#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_IDENT
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 	0x4000000 /* Put the FIT out of first 64MB boot area */
+
+/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
+	(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
+
+#endif
+
+#define CONFIG_CMD_READ
+#define CONFIG_SERIAL_TAG
+#define CONFIG_FASTBOOT_USB_DEV 0
+
+#define CONFIG_REMAKE_ELF
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_FEC_MXC)
+#define CONFIG_ETHPRIME                 "FEC"
+#define PHY_ANEG_TIMEOUT 20000
+
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_FEC_MXC_PHYADDR          0
+
+#define IMX_FEC_BASE			0x30BE0000
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)"
+#endif
+
+#ifdef CONFIG_DISTRO_DEFAULTS
 #define BOOT_TARGET_DEVICES(func) \
+	func(USB, usb, 0) \
 	func(MMC, mmc, 1) \
-	func(MMC, mmc, 2) \
-	func(DHCP, dhcp, na)
+	func(MMC, mmc, 2)
 
 #include <config_distro_bootcmd.h>
+#else
+#define BOOTENV
 #endif
 
+/*
+ * Another approach is add the clocks for inmates into clks_init_on
+ * in clk-imx8mm.c, then clk_ingore_unused could be removed.
+ */
+#define JH_ROOT_DTB    "imx8mm-evk-root.dtb"
+
+#define JAILHOUSE_ENV \
+	"jh_clk= \0 " \
+	"jh_root_dtb=" JH_ROOT_DTB "\0" \
+	"jh_mmcboot=mw 0x303d0518 0xff; setenv fdtfile ${jh_root_dtb};" \
+		"setenv jh_clk clk_ignore_unused mem=1212MB; " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run jh_netboot; fi; \0" \
+	"jh_netboot=mw 0x303d0518 0xff; setenv fdtfile ${jh_root_dtb}; setenv jh_clk clk_ignore_unused mem=1212MB; run netboot; \0 "
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x43800000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"emmc_dev=2\0"\
+	"sd_dev=1\0" \
+
 /* Initial environment variables */
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	"splashimage=0x50000000\0" \
+	"fdt_addr_r=0x43000000\0"			\
+	"fdt_addr=0x43000000\0"			\
+	"fdt_high=0xffffffffffffffff\0" \
+	"mtdparts=" MFG_NAND_PARTITION "\0" \
+	"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
+	"bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=nandrootfs "  \
+		"root=ubi0:nandrootfs rootfstype=ubifs "		     \
+		MFG_NAND_PARTITION \
+		"\0" \
+	"bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\
+		"nand read ${fdt_addr_r} 0x7000000 0x100000;"\
+		"booti ${loadaddr} - ${fdt_addr_r}"
+
+#else
 #define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
 	BOOTENV \
-	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	JAILHOUSE_ENV \
+	"prepare_mcore=setenv mcore_clk clk-imx8mm.mcore_booted;\0" \
+	"scriptaddr=0x43500000\0" \
 	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"bsp_script=boot.scr\0" \
 	"image=Image\0" \
+	"splashimage=0x50000000\0" \
 	"console=ttymxc1,115200\0" \
 	"fdt_addr_r=0x43000000\0"			\
+	"fdt_addr=0x43000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
 	"boot_fit=no\0" \
-	"fdtfile=imx8mm-evk.dtb\0" \
-	"initrd_addr=0x43800000\0"		\
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"bootm_size=0x10000000\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=1\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+			"bootm ${loadaddr}; " \
+		"else " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr_r}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"fi;\0" \
+	"netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+			"bootm ${loadaddr}; " \
+		"else " \
+			"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
+				"booti ${loadaddr} - ${fdt_addr_r}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"fi;\0" \
+	"bsp_bootcmd=echo Running BSP bootcmd ...; " \
+		"mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "fi;"
+#endif
 
 /* Link Definitions */
 
@@ -63,6 +199,7 @@
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
+#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
 #define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
 
 #define CONFIG_SYS_SDRAM_BASE           0x40000000
@@ -78,17 +215,49 @@
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
 
+#define CONFIG_IMX_BOOTAUX
+
 /* USDHC */
 
+#ifdef CONFIG_TARGET_IMX8MM_DDR4_EVK
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#else
 #define CONFIG_SYS_FSL_USDHC_NUM	2
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#endif
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
 
-#define CONFIG_ETHPRIME                 "FEC"
+#ifdef CONFIG_FSL_FSPI
+#define FSL_FSPI_FLASH_SIZE		SZ_32M
+#define FSL_FSPI_FLASH_NUM		1
+#define FSPI0_BASE_ADDR			0x30bb0000
+#define FSPI0_AMBA_BASE			0x0
+#define CONFIG_FSPI_QUAD_SUPPORT
 
-#define CONFIG_FEC_XCV_TYPE             RGMII
-#define CONFIG_FEC_MXC_PHYADDR          0
-#define FEC_QUIRK_ENET_MAC
+#define CONFIG_SYS_FSL_FSPI_AHB
+#endif
 
-#define IMX_FEC_BASE			0x30BE0000
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x20000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#endif /* CONFIG_NAND_MXS */
+
+/* USB configs */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_USBD_HS
+
+#endif
+
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         2
+
+#ifdef CONFIG_ANDROID_SUPPORT
+#include "imx8mm_evk_android.h"
+#endif
 
 #endif
diff --git a/include/configs/imx8mm_evk_android.h b/include/configs/imx8mm_evk_android.h
new file mode 100644
index 00000000000..463e872541e
--- /dev/null
+++ b/include/configs/imx8mm_evk_android.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef IMX8MM_EVK_ANDROID_H
+#define IMX8MM_EVK_ANDROID_H
+
+#define FSL_FASTBOOT_FB_DEV "mmc"
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"splashpos=m,m\0"			\
+	"splashimage=0x50000000\0"		\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+
+/* Enable mcu firmware flash */
+#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT
+#define ANDROID_MCU_FRIMWARE_DEV_TYPE DEV_MMC
+#define ANDROID_MCU_FIRMWARE_START 0x500000
+#define ANDROID_MCU_OS_PARTITION_SIZE 0x40000
+#define ANDROID_MCU_FIRMWARE_SIZE  0x20000
+#define ANDROID_MCU_FIRMWARE_HEADER_STACK 0x20020000
+#endif
+
+#define CONFIG_SYS_SPL_PTE_RAM_BASE    0x41580000
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#define BOOTLOADER_RBIDX_OFFSET  0x3FE000
+#define BOOTLOADER_RBIDX_START   0x3FF000
+#define BOOTLOADER_RBIDX_LEN     0x08
+#define BOOTLOADER_RBIDX_INITVAL 0
+#endif
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#define AVB_RPMB
+#define KEYSLOT_HWPARTITION_ID 2
+#define KEYSLOT_BLKS             0x1FFF
+#define NS_ARCH_ARM64 1
+
+#endif
+
+/* Enable CONFIG_IMX8M_1G_MEMORY  to config 1GB ddr */
+#ifdef CONFIG_IMX8M_1G_MEMORY
+#undef  PHYS_SDRAM_SIZE
+#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
+#endif
+
+#ifdef CONFIG_IMX8M_4G_LPDDR4
+#undef PHYS_SDRAM_SIZE
+#define PHYS_SDRAM_SIZE          0xC0000000 /* 3GB */
+#define PHYS_SDRAM_2             0x100000000
+#define PHYS_SDRAM_2_SIZE        0x40000000 /* 1GB */
+#endif
+
+#endif /* IMX8MM_EVK_ANDROID_H */
diff --git a/include/configs/imx8mm_val.h b/include/configs/imx8mm_val.h
new file mode 100644
index 00000000000..f6373adf050
--- /dev/null
+++ b/include/configs/imx8mm_val.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __IMX8MM_VAL_H
+#define __IMX8MM_VAL_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+#include "imx_env.h"
+
+#define CONFIG_SYS_BOOTM_LEN		(64 * SZ_1M)
+#define CONFIG_SPL_MAX_SIZE		(148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		SZ_512K
+#define CONFIG_SYS_UBOOT_BASE	\
+	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK		0x920000
+#define CONFIG_SPL_BSS_START_ADDR	0x910000
+#define CONFIG_SPL_BSS_MAX_SIZE		SZ_8K	/* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_512K	/* 512 KB */
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR		0x930000
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#define CONFIG_POWER_BD71837
+#endif
+
+
+#define CONFIG_CMD_READ
+#define CONFIG_SERIAL_TAG
+#define CONFIG_FASTBOOT_USB_DEV 0
+
+#define CONFIG_REMAKE_ELF
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_FEC_MXC)
+#define CONFIG_ETHPRIME                 "FEC"
+#define PHY_ANEG_TIMEOUT 20000
+
+
+#define IMX_FEC_BASE			0x30BE0000
+
+#ifdef CONFIG_TARGET_IMX8MM_DDR3L_VAL
+#define CONFIG_FEC_XCV_TYPE             RMII
+#define CONFIG_FEC_MXC_PHYADDR          3
+#else
+#define CONFIG_FEC_MXC_PHYADDR          0
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#endif
+
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x43800000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"emmc_dev=2\0"\
+	"sd_dev=1\0" \
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=Image\0" \
+	"console=ttymxc1,115200\0" \
+	"fdt_addr=0x43000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"boot_fdt=try\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"initrd_addr=0x43800000\0"		\
+	"initrd_high=0xffffffffffffffff\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"echo wait for boot; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"booti; " \
+		"fi;\0"
+
+
+/* Link Definitions */
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+
+#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define PHYS_SDRAM                      0x40000000
+#define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
+
+#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		2048
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_IMX_BOOTAUX
+
+/* USDHC */
+
+#ifdef CONFIG_TARGET_IMX8MM_DDR3L_VAL
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#else
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#endif
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+
+#ifdef CONFIG_FSL_FSPI
+#define FSL_FSPI_FLASH_SIZE		SZ_32M
+#define FSL_FSPI_FLASH_NUM		1
+#define FSPI0_BASE_ADDR			0x30bb0000
+#define FSPI0_AMBA_BASE			0x0
+#define CONFIG_FSPI_QUAD_SUPPORT
+
+#define CONFIG_SYS_FSL_FSPI_AHB
+#endif
+
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x20000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#endif /* CONFIG_NAND_MXS */
+
+/* USB configs */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_USBD_HS
+
+#endif
+
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         2
+
+#endif
diff --git a/include/configs/imx8mn_ab2.h b/include/configs/imx8mn_ab2.h
new file mode 100644
index 00000000000..fc8b92b087a
--- /dev/null
+++ b/include/configs/imx8mn_ab2.h
@@ -0,0 +1,270 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __IMX8MN_AB2_H
+#define __IMX8MN_AB2_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+#include "imx_env.h"
+
+#define CONFIG_SYS_BOOTM_LEN		(32 * SZ_1M)
+
+
+#define CONFIG_SPL_MAX_SIZE		(208 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_UBOOT_BASE	\
+	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK		0x96fff0
+#define CONFIG_SPL_BSS_START_ADDR      0x954000
+#define CONFIG_MALLOC_F_ADDR 0x970000
+#define CONFIG_SPL_BSS_MAX_SIZE		SZ_8K	/* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_512K	/* 512 KB */
+
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_IDENT
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 	0x4000000 /* Put the FIT out of first 64MB boot area */
+
+/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
+	(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
+#endif
+
+#endif
+
+#define CONFIG_CMD_READ
+#define CONFIG_SERIAL_TAG
+#define CONFIG_FASTBOOT_USB_DEV 0
+
+#define CONFIG_REMAKE_ELF
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_FEC_MXC)
+#define CONFIG_ETHPRIME                 "FEC"
+#define PHY_ANEG_TIMEOUT 20000
+
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_FEC_MXC_PHYADDR          0
+
+#define IMX_FEC_BASE			0x30BE0000
+#endif
+
+#ifdef CONFIG_DISTRO_DEFAULTS
+#define BOOT_TARGET_DEVICES(func) \
+	func(USB, usb, 0) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 2)
+
+#include <config_distro_bootcmd.h>
+#else
+#define BOOTENV
+#endif
+
+/*
+ * Another approach is add the clocks for inmates into clks_init_on
+ * in clk-imx8mm.c, then clk_ingore_unused could be removed.
+ */
+#ifdef CONFIG_TARGET_IMX8MN_DDR4_AB2
+#define JH_ROOT_DTB	"imx8mn-ddr4-ab2-root.dtb"
+#else
+#define JH_ROOT_DTB	"imx8mn-ab2-root.dtb"
+#endif
+
+#define JAILHOUSE_ENV \
+	"jh_clk= \0 " \
+	"jh_root_dtb=" JH_ROOT_DTB "\0" \
+	"jh_mmcboot=mw 0x303d0518 0xff; setenv fdtfile ${jh_root_dtb};" \
+		"setenv jh_clk clk_ignore_unused mem=1212MB; " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run jh_netboot; fi; \0" \
+	"jh_netboot=mw 0x303d0518 0xff; setenv fdtfile ${jh_root_dtb}; setenv jh_clk clk_ignore_unused mem=1212MB; run netboot; \0 "
+
+#define M7_BOOT_ENV \
+	"m7_boot=no\0" \
+	"m7_image=nxh3670.itb\0" \
+	"m7_loadaddr=0x80000000\0" \
+	"m7_nxh_app_loadaddr=0x81000000\0" \
+	"m7_nxh_rfmac_loadaddr=0x81012000\0" \
+	"m7_nxh_cf_loadaddr=0x81016000\0" \
+	"m7_nxh_data_loadaddr=0x8101E000\0" \
+	"m7_fdt_file=imx8mn-ab2-m7.dtb\0" \
+	"m7_nxh_bin=main@1\0" \
+	"m7_nxh_app=app@1\0" \
+	"m7_nxh_rfmac=rfmac@1\0" \
+	"m7_nxh_cf=cf@1\0" \
+	"m7_nxh_data=data@1\0" \
+	"loadm7nxhfw=imxtract ${loadaddr} ${m7_nxh_bin} ${m7_loadaddr}; " \
+		"imxtract ${loadaddr} ${m7_nxh_app} ${m7_nxh_app_loadaddr}; " \
+		"imxtract ${loadaddr} ${m7_nxh_rfmac} ${m7_nxh_rfmac_loadaddr}; " \
+		"imxtract ${loadaddr} ${m7_nxh_cf} ${m7_nxh_cf_loadaddr}; " \
+		"imxtract ${loadaddr} ${m7_nxh_data} ${m7_nxh_data_loadaddr}\0" \
+	"loadm7image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m7_image}\0" \
+	"update_m7_from_sd=" \
+		"if sf probe 0:0; then " \
+			"if run loadm7image; then " \
+				"setexpr fw_sz ${filesize} + 0xffff; " \
+				"setexpr fw_sz ${fw_sz} / 0x10000; " \
+				"setexpr fw_sz ${fw_sz} * 0x10000; " \
+				"sf erase 0x100000 ${fw_sz}; " \
+				"sf write ${m7_loadaddr} 0x100000 ${filesize}; " \
+			"fi; " \
+		"fi\0" \
+	"m7boot=run loadm7image; run loadm7nxhfw; dcache flush; bootaux ${m7_loadaddr}\0" \
+	"m7netboot=${get_cmd} ${loaddadr} ${m7_image}; " \
+		"run loadm7nxhfw; dcache flush; bootaux ${m7_loadaddr}; \0" \
+	"m7boot_sf=sf probe 0:0; dcache flush; bootaux ${m7_sf_loadaddr}\0"
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x43800000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"emmc_dev=2\0"\
+	"sd_dev=1\0" \
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
+	JAILHOUSE_ENV \
+	BOOTENV \
+	M7_BOOT_ENV \
+	"scriptaddr=0x43500000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"bsp_script=boot.scr\0" \
+	"image=Image\0" \
+	"splashimage=0x50000000\0" \
+	"console=ttymxc1,115200\0" \
+	"fdt_addr_r=0x43000000\0"			\
+	"fdt_addr=0x43000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"boot_fit=no\0" \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"bootm_size=0x10000000\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${m7_boot} = yes || test ${m7_boot} = try; then "\
+			"echo Booting M7 aux core...; " \
+			"run m7boot; " \
+		"fi; " \
+		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+			"bootm ${loadaddr}; " \
+		"else " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr_r}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"fi;\0" \
+	"netargs=setenv bootargs ${jh_clk} console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if test ${m7_boot} = yes || test ${m7_boot} = try; then " \
+			"echo Booting M7 aux core...;" \
+			"run m7netboot;" \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+			"bootm ${loadaddr}; " \
+		"else " \
+			"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
+				"booti ${loadaddr} - ${fdt_addr_r}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"fi;\0" \
+	"bsp_bootcmd=echo Running BSP bootcmd ...; " \
+		"mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "fi;"
+
+
+/* Link Definitions */
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+
+#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define PHYS_SDRAM                      0x40000000
+
+#ifdef CONFIG_TARGET_IMX8MN_DDR3L_AB2
+#define PHYS_SDRAM_SIZE			0x40000000 /* 1GB DDR */
+#else
+#define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
+#endif
+
+#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		2048
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_IMX_BOOTAUX
+
+/* USDHC */
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x20000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#endif /* CONFIG_NAND_MXS */
+
+/* USB configs */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_USBD_HS
+#endif
+
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         2
+
+#endif
diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h
index 142fc3e4fff..1bdf68ab83a 100644
--- a/include/configs/imx8mn_evk.h
+++ b/include/configs/imx8mn_evk.h
@@ -9,17 +9,20 @@
 #include <linux/sizes.h>
 #include <linux/stringify.h>
 #include <asm/arch/imx-regs.h>
+#include "imx_env.h"
 
 #define CONFIG_SYS_BOOTM_LEN		(32 * SZ_1M)
 
-#define CONFIG_SPL_MAX_SIZE		(148 * 1024)
-#define CONFIG_SYS_MONITOR_LEN		SZ_512K
+
+#define CONFIG_SPL_MAX_SIZE		(208 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
 #define CONFIG_SYS_UBOOT_BASE	\
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_STACK		0x980000
-#define CONFIG_SPL_BSS_START_ADDR	0x950000
+#define CONFIG_SPL_STACK		0x96fff0
+#define CONFIG_SPL_BSS_START_ADDR      0x954000
+#define CONFIG_MALLOC_F_ADDR 0x970000
 #define CONFIG_SPL_BSS_MAX_SIZE		SZ_8K	/* 8 KB */
 #define CONFIG_SYS_SPL_MALLOC_START	0x42200000
 #define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_512K	/* 512 KB */
@@ -27,36 +30,149 @@
 /* For RAW image gives a error info not panic */
 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
 
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_IDENT
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 	0x4000000 /* Put the FIT out of first 64MB boot area */
+
+/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
+	(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
 #endif
 
-#ifndef CONFIG_SPL_BUILD
+#endif
+
+#define CONFIG_CMD_READ
+#define CONFIG_SERIAL_TAG
+#define CONFIG_FASTBOOT_USB_DEV 0
+
+#define CONFIG_REMAKE_ELF
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_FEC_MXC)
+#define CONFIG_ETHPRIME                 "FEC"
+#define PHY_ANEG_TIMEOUT 20000
+
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_FEC_MXC_PHYADDR          0
+
+#define IMX_FEC_BASE			0x30BE0000
+#endif
+
+#ifdef CONFIG_DISTRO_DEFAULTS
 #define BOOT_TARGET_DEVICES(func) \
+	func(USB, usb, 0) \
 	func(MMC, mmc, 1) \
-	func(MMC, mmc, 2) \
-	func(DHCP, dhcp, na)
+	func(MMC, mmc, 2)
 
 #include <config_distro_bootcmd.h>
+#else
+#define BOOTENV
 #endif
 
+/*
+ * Another approach is add the clocks for inmates into clks_init_on
+ * in clk-imx8mm.c, then clk_ingore_unused could be removed.
+ */
+#ifdef CONFIG_TARGET_IMX8MN_DDR4_EVK
+#define JH_ROOT_DTB	"imx8mn-ddr4-evk-root.dtb"
+#else
+#define JH_ROOT_DTB	"imx8mn-evk-root.dtb"
+#endif
+
+#define JAILHOUSE_ENV \
+	"jh_clk= \0 " \
+	"jh_root_dtb=" JH_ROOT_DTB "\0" \
+	"jh_mmcboot=mw 0x303d0518 0xff; setenv fdtfile ${jh_root_dtb};" \
+		"setenv jh_clk clk_ignore_unused mem=1212MB; " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run jh_netboot; fi; \0" \
+	"jh_netboot=mw 0x303d0518 0xff; setenv fdtfile ${jh_root_dtb}; setenv jh_clk clk_ignore_unused mem=1212MB; run netboot; \0 "
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x43800000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"emmc_dev=2\0"\
+	"sd_dev=1\0" \
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS		\
-	"image=Image\0" \
+	CONFIG_MFG_ENV_SETTINGS \
+	JAILHOUSE_ENV \
 	BOOTENV \
-	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"prepare_mcore=setenv mcore_clk clk-imx8mn.mcore_booted;\0" \
+	"scriptaddr=0x43500000\0" \
 	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"bsp_script=boot.scr\0" \
+	"image=Image\0" \
+	"splashimage=0x50000000\0" \
 	"console=ttymxc1,115200\0" \
 	"fdt_addr_r=0x43000000\0"			\
+	"fdt_addr=0x43000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
 	"boot_fit=no\0" \
 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
-	"initrd_addr=0x43800000\0"		\
 	"bootm_size=0x10000000\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=1\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+			"bootm ${loadaddr}; " \
+		"else " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr_r}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"fi;\0" \
+	"netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+			"bootm ${loadaddr}; " \
+		"else " \
+			"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
+				"booti ${loadaddr} - ${fdt_addr_r}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"fi;\0" \
+	"bsp_bootcmd=echo Running BSP bootcmd ...; " \
+		"mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "fi;"
+
 
 /* Link Definitions */
 
 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE        0x200000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x80000
 #define CONFIG_SYS_INIT_SP_OFFSET \
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR \
@@ -66,7 +182,12 @@
 
 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 #define PHYS_SDRAM                      0x40000000
+
+#ifdef CONFIG_TARGET_IMX8MN_DDR3_EVK
+#define PHYS_SDRAM_SIZE			0x40000000 /* 1GB DDR */
+#else
 #define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
+#endif
 
 #define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
 
@@ -77,9 +198,34 @@
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
 
+#define CONFIG_IMX_BOOTAUX
+
 /* USDHC */
 
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x20000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#endif /* CONFIG_NAND_MXS */
+
+/* USB configs */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_USBD_HS
+#endif
+
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         2
+
+#ifdef CONFIG_ANDROID_SUPPORT
+#include "imx8mn_evk_android.h"
+#endif
+
 #endif
diff --git a/include/configs/imx8mn_evk_android.h b/include/configs/imx8mn_evk_android.h
new file mode 100644
index 00000000000..a7f155c9f4c
--- /dev/null
+++ b/include/configs/imx8mn_evk_android.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef IMX8MN_EVK_ANDROID_H
+#define IMX8MN_EVK_ANDROID_H
+
+#define FSL_FASTBOOT_FB_DEV "mmc"
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"splashpos=m,m\0"			\
+	"splashimage=0x50000000\0"		\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+
+/* Enable mcu firmware flash */
+#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT
+#define ANDROID_MCU_FRIMWARE_DEV_TYPE DEV_MMC
+#define ANDROID_MCU_FIRMWARE_START 0x500000
+#define ANDROID_MCU_OS_PARTITION_SIZE 0x40000
+#define ANDROID_MCU_FIRMWARE_SIZE  0x20000
+#define ANDROID_MCU_FIRMWARE_HEADER_STACK 0x20020000
+#endif
+
+#define CONFIG_SYS_SPL_PTE_RAM_BASE    0x41580000
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#define BOOTLOADER_RBIDX_OFFSET  0x3FE000
+#define BOOTLOADER_RBIDX_START   0x3FF000
+#define BOOTLOADER_RBIDX_LEN     0x08
+#define BOOTLOADER_RBIDX_INITVAL 0
+#endif
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#define AVB_RPMB
+#define KEYSLOT_HWPARTITION_ID 2
+#define KEYSLOT_BLKS             0x1FFF
+#define NS_ARCH_ARM64 1
+#endif
+
+#endif /* IMX8MN_EVK_ANDROID_H */
diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index b810a558adf..a26c651dcf5 100644
--- a/include/configs/imx8mp_evk.h
+++ b/include/configs/imx8mp_evk.h
@@ -9,35 +9,49 @@
 #include <linux/sizes.h>
 #include <linux/stringify.h>
 #include <asm/arch/imx-regs.h>
+#include "imx_env.h"
 
 #define CONFIG_SYS_BOOTM_LEN		(32 * SZ_1M)
 
-#define CONFIG_SPL_MAX_SIZE		(152 * 1024)
+#define CONFIG_SPL_MAX_SIZE		(176 * 1024)
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
 #define CONFIG_SYS_UBOOT_BASE	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
 #ifdef CONFIG_SPL_BUILD
-/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
-#define CONFIG_SPL_STACK		0x960000
-#define CONFIG_SPL_BSS_START_ADDR	0x0098FC00
-#define CONFIG_SPL_BSS_MAX_SIZE		0x400	/* 1 KB */
+#define CONFIG_SPL_STACK		0x96dff0
+#define CONFIG_SPL_BSS_START_ADDR      0x96e000
+#define CONFIG_SPL_BSS_MAX_SIZE		SZ_8K	/* 8 KB */
 #define CONFIG_SYS_SPL_MALLOC_START	0x42200000
 #define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_512K	/* 512 KB */
 
+/* For RAW image gives a error info not panic */
 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
 
-#undef CONFIG_DM_MMC
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_IDENT
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 	0x4000000 /* Put the FIT out of first 64MB boot area */
 
-#define CONFIG_POWER_PCA9450
+/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
+	(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
+#endif
 
 #endif
 
+#define CONFIG_CMD_READ
+#define CONFIG_SERIAL_TAG
+#define CONFIG_FASTBOOT_USB_DEV 0
+
+#define CONFIG_REMAKE_ELF
+/* ENET Config */
+/* ENET1 */
+
 #if defined(CONFIG_CMD_NET)
 #define CONFIG_ETHPRIME                 "eth1" /* Set eqos to primary since we use its MDIO */
 
 #define CONFIG_FEC_XCV_TYPE             RGMII
 #define CONFIG_FEC_MXC_PHYADDR          1
-#define FEC_QUIRK_ENET_MAC
 
 #define DWC_NET_PHYADDR			1
 
@@ -45,28 +59,131 @@
 
 #endif
 
-#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_DISTRO_DEFAULTS
 #define BOOT_TARGET_DEVICES(func) \
-       func(MMC, mmc, 1) \
-       func(MMC, mmc, 2)
+	func(USB, usb, 0) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 2)
 
 #include <config_distro_bootcmd.h>
+#else
+#define BOOTENV
+#endif
+
+#define JH_ROOT_DTB    "imx8mp-evk-root.dtb"
+
+#define JAILHOUSE_ENV \
+	"jh_clk= \0 " \
+	"jh_root_dtb=" JH_ROOT_DTB "\0" \
+	"jh_mmcboot=setenv fdtfile ${jh_root_dtb};" \
+		"setenv jh_clk clk_ignore_unused mem=1920MB; " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run jh_netboot; fi; \0" \
+	"jh_netboot=setenv fdtfile ${jh_root_dtb}; setenv jh_clk clk_ignore_unused mem=1920MB; run netboot; \0 "
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x43800000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"emmc_dev=2\0"\
+	"sd_dev=1\0"
+
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)"
 #endif
 
 /* Initial environment variables */
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	"splashimage=0x50000000\0" \
+	"fdt_addr_r=0x43000000\0"			\
+	"fdt_addr=0x43000000\0"			\
+	"fdt_high=0xffffffffffffffff\0" \
+	"mtdparts=" MFG_NAND_PARTITION "\0" \
+	"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
+	"bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=nandrootfs "  \
+		"root=ubi0:nandrootfs rootfstype=ubifs "		     \
+		MFG_NAND_PARTITION \
+		"\0" \
+	"bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\
+		"nand read ${fdt_addr_r} 0x7000000 0x100000;"\
+		"booti ${loadaddr} - ${fdt_addr_r}"
+
+#else
 #define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
+	JAILHOUSE_ENV \
 	BOOTENV \
-	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"prepare_mcore=setenv mcore_clk clk-imx8mp.mcore_booted;\0" \
+	"scriptaddr=0x43500000\0" \
 	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"bsp_script=boot.scr\0" \
 	"image=Image\0" \
-	"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
+	"splashimage=0x50000000\0" \
+	"console=ttymxc1,115200\0" \
 	"fdt_addr_r=0x43000000\0"			\
+	"fdt_addr=0x43000000\0"			\
 	"boot_fdt=try\0" \
+	"fdt_high=0xffffffffffffffff\0"		\
+	"boot_fit=no\0" \
 	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
-	"initrd_addr=0x43800000\0"		\
 	"bootm_size=0x10000000\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=1\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+			"bootm ${loadaddr}; " \
+		"else " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr_r}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"fi;\0" \
+	"netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+			"bootm ${loadaddr}; " \
+		"else " \
+			"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
+				"booti ${loadaddr} - ${fdt_addr_r}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"fi;\0" \
+	"bsp_bootcmd=echo Running BSP bootcmd ...; " \
+		"mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "fi;"
+#endif
 
 /* Link Definitions */
 
@@ -84,7 +201,11 @@
 #define PHYS_SDRAM			0x40000000
 #define PHYS_SDRAM_SIZE			0xC0000000	/* 3 GB */
 #define PHYS_SDRAM_2			0x100000000
+#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK
+#define PHYS_SDRAM_2_SIZE		0x40000000	/* 1 GB */
+#else
 #define PHYS_SDRAM_2_SIZE		0xC0000000	/* 3 GB */
+#endif
 
 #define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
 
@@ -95,7 +216,34 @@
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
 
+#define CONFIG_IMX_BOOTAUX
+
+#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#else
 #define CONFIG_SYS_FSL_USDHC_NUM	2
+#endif
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x20000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#endif /* CONFIG_NAND_MXS */
+
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* USB configs */
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         2
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+#ifdef CONFIG_ANDROID_SUPPORT
+#include "imx8mp_evk_android.h"
+#endif
+
 #endif
diff --git a/include/configs/imx8mp_evk_android.h b/include/configs/imx8mp_evk_android.h
new file mode 100644
index 00000000000..09e3841908b
--- /dev/null
+++ b/include/configs/imx8mp_evk_android.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef IMX8MP_EVK_ANDROID_H
+#define IMX8MP_EVK_ANDROID_H
+
+#define FSL_FASTBOOT_FB_DEV "mmc"
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"splashpos=m,m\0"			\
+	"splashimage=0x50000000\0"		\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+
+/* Enable mcu firmware flash */
+#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT
+#define ANDROID_MCU_FRIMWARE_DEV_TYPE DEV_MMC
+#define ANDROID_MCU_FIRMWARE_START 0x500000
+#define ANDROID_MCU_OS_PARTITION_SIZE 0x40000
+#define ANDROID_MCU_FIRMWARE_SIZE  0x20000
+#define ANDROID_MCU_FIRMWARE_HEADER_STACK 0x20020000
+#endif
+
+#define CONFIG_SYS_SPL_PTE_RAM_BASE    0x41580000
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#define BOOTLOADER_RBIDX_OFFSET  0x3FE000
+#define BOOTLOADER_RBIDX_START   0x3FF000
+#define BOOTLOADER_RBIDX_LEN     0x08
+#define BOOTLOADER_RBIDX_INITVAL 0
+#endif
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#define AVB_RPMB
+#define KEYSLOT_HWPARTITION_ID 2
+#define KEYSLOT_BLKS             0x1FFF
+#define NS_ARCH_ARM64 1
+#endif
+
+#endif /* IMX8MP_EVK_ANDROID_H */
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index 4aaed3ae7da..96f72fdbe47 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -9,10 +9,11 @@
 #include <linux/sizes.h>
 #include <linux/stringify.h>
 #include <asm/arch/imx-regs.h>
+#include "imx_env.h"
 
 #define CONFIG_SYS_BOOTM_LEN		(64 * SZ_1M)
 
-#define CONFIG_SPL_MAX_SIZE		(124 * 1024)
+#define CONFIG_SPL_MAX_SIZE		(152 * 1024)
 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
 
 #ifdef CONFIG_SPL_BUILD
@@ -37,39 +38,117 @@
 
 /* ENET Config */
 /* ENET1 */
-#if defined(CONFIG_CMD_NET)
+#if defined(CONFIG_FEC_MXC)
 #define CONFIG_ETHPRIME                 "FEC"
+#define PHY_ANEG_TIMEOUT 20000
 
 #define CONFIG_FEC_XCV_TYPE             RGMII
 #define CONFIG_FEC_MXC_PHYADDR          0
-#define FEC_QUIRK_ENET_MAC
 
 #define IMX_FEC_BASE			0x30BE0000
 #endif
 
-#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_DISTRO_DEFAULTS
 #define BOOT_TARGET_DEVICES(func) \
-       func(MMC, mmc, 0) \
-       func(MMC, mmc, 1) \
-       func(DHCP, dhcp, na)
+	func(USB, usb, 0) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0)
 
 #include <config_distro_bootcmd.h>
+#else
+#define BOOTENV
 #endif
 
+/*
+ * Another approach is add the clocks for inmates into clks_init_on
+ * in clk-imx8mq.c, then clk_ingore_unused could be removed.
+ */
+#define JAILHOUSE_ENV \
+	"jh_clk= \0 " \
+	"jh_mmcboot=setenv fdtfile imx8mq-evk-root.dtb; " \
+		"setenv jh_clk clk_ignore_unused mem=1872M; " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run jh_netboot; fi; \0" \
+	"jh_netboot=setenv fdtfile imx8mq-evk-root.dtb; setenv jh_clk clk_ignore_unused mem=1872MB; run netboot; \0 "
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x43800000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"emmc_dev=0\0"\
+	"sd_dev=1\0" \
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
 	BOOTENV \
-	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	JAILHOUSE_ENV \
+	"prepare_mcore=setenv mcore_clk clk-imx8mq.mcore_booted;\0" \
+	"scriptaddr=0x43500000\0" \
 	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"bsp_script=boot.scr\0" \
 	"image=Image\0" \
+	"splashimage=0x50000000\0" \
 	"console=ttymxc0,115200\0" \
 	"fdt_addr_r=0x43000000\0"			\
+	"fdt_addr=0x43000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
 	"boot_fdt=try\0" \
 	"fdtfile=imx8mq-evk.dtb\0" \
-	"initrd_addr=0x43800000\0"		\
 	"bootm_size=0x10000000\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=1\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr_r}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"echo wait for boot; " \
+		"fi;\0" \
+	"netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
+				"booti ${loadaddr} - ${fdt_addr_r}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"booti; " \
+		"fi;\0" \
+	"bsp_bootcmd=echo Running BSP bootcmd ...; " \
+			"mmc dev ${mmcdev}; if mmc rescan; then " \
+			   "if run loadbootscript; then " \
+				   "run bootscript; " \
+			   "else " \
+				   "if run loadimage; then " \
+					   "run mmcboot; " \
+				   "else run netboot; " \
+				   "fi; " \
+			   "fi; " \
+		   "fi;"
 
 /* Link Definitions */
 
@@ -98,4 +177,17 @@
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
 
+#define CONFIG_CMD_READ
+#define CONFIG_SERIAL_TAG
+#define CONFIG_FASTBOOT_USB_DEV 0
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         2
+
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+#ifdef CONFIG_ANDROID_SUPPORT
+#include "imx8mq_evk_android.h"
+#endif
+
 #endif
diff --git a/include/configs/imx8mq_evk_android.h b/include/configs/imx8mq_evk_android.h
new file mode 100644
index 00000000000..5fb3c33fd84
--- /dev/null
+++ b/include/configs/imx8mq_evk_android.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef IMX8MQ_EVK_ANDROID_H
+#define IMX8MQ_EVK_ANDROID_H
+
+#define FSL_FASTBOOT_FB_DEV "mmc"
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"splashpos=m,m\0"			\
+	"splashimage=0x50000000\0"		\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+
+/* Enable mcu firmware flash */
+#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT
+#define ANDROID_MCU_FRIMWARE_DEV_TYPE DEV_MMC
+#define ANDROID_MCU_FIRMWARE_START 0x500000
+#define ANDROID_MCU_OS_PARTITION_SIZE 0x40000
+#define ANDROID_MCU_FIRMWARE_SIZE  0x20000
+#define ANDROID_MCU_FIRMWARE_HEADER_STACK 0x20020000
+#endif
+
+#define CONFIG_SYS_SPL_PTE_RAM_BASE    0x41580000
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#define BOOTLOADER_RBIDX_OFFSET  0x1E000
+#define BOOTLOADER_RBIDX_START   0x1F000
+#define BOOTLOADER_RBIDX_LEN     0x08
+#define BOOTLOADER_RBIDX_INITVAL 0
+#endif
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#define AVB_RPMB
+#define KEYSLOT_HWPARTITION_ID 2
+#define KEYSLOT_BLKS             0x1FFF
+#define NS_ARCH_ARM64 1
+#endif
+
+#endif /* IMX8MQ_EVK_ANDROID_H */
diff --git a/include/configs/imx8mq_val.h b/include/configs/imx8mq_val.h
new file mode 100644
index 00000000000..025db9bef17
--- /dev/null
+++ b/include/configs/imx8mq_val.h
@@ -0,0 +1,208 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __IMX8M_VAL_H
+#define __IMX8M_VAL_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+#include "imx_env.h"
+
+#define CONFIG_SYS_BOOTM_LEN		(32 * SZ_1M)
+
+#define CONFIG_SPL_MAX_SIZE		(148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+#define CONFIG_SPL_STACK		0x187FF0
+#define CONFIG_SPL_BSS_START_ADDR      0x00180000
+#define CONFIG_SPL_BSS_MAX_SIZE        0x2000	/* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START    0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x80000	/* 512 KB */
+
+#define CONFIG_MALLOC_F_ADDR		0x182000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
+
+#undef CONFIG_DM_MMC
+
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_IDENT
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 	0x4000000 /* Put the FIT out of first 64MB boot area */
+
+/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
+	(CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
+
+#endif /* CONFIG_SPL_BUILD*/
+
+#define CONFIG_REMAKE_ELF
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_FEC_MXC)
+#define CONFIG_ETHPRIME                 "FEC"
+#define PHY_ANEG_TIMEOUT 20000
+
+#define FEC_QUIRK_ENET_MAC
+
+#define IMX_FEC_BASE			0x30BE0000
+
+#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL
+#define CONFIG_FEC_XCV_TYPE             RMII
+#define CONFIG_FEC_MXC_PHYADDR          3
+#else
+#define CONFIG_FEC_MXC_PHYADDR          0
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#endif
+
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)"
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x43800000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"emmc_dev=0\0"\
+	"sd_dev=1\0" \
+
+/* Initial environment variables */
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	"fdt_addr=0x43000000\0"			\
+	"fdt_high=0xffffffffffffffff\0" \
+	"mtdparts=" MFG_NAND_PARTITION "\0" \
+	"console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \
+	"bootargs=console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200 ubi.mtd=nandrootfs "  \
+		"root=ubi0:nandrootfs rootfstype=ubifs "		     \
+		MFG_NAND_PARTITION \
+		"\0" \
+	"bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\
+		"nand read ${fdt_addr} 0x7000000 0x100000;"\
+		"booti ${loadaddr} - ${fdt_addr}"
+
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=Image\0" \
+	"console=ttymxc0,115200\0" \
+	"fdt_addr=0x43000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"boot_fdt=try\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"initrd_addr=0x43800000\0"		\
+	"initrd_high=0xffffffffffffffff\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"echo wait for boot; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"booti; " \
+		"fi;\0"
+
+#endif
+
+/* Link Definitions */
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+        (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_MMC_ENV_DEV         1   /* USDHC2 */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+
+#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define PHYS_SDRAM                      0x40000000
+#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL
+#define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR3L for two rank */
+#else
+#define PHYS_SDRAM_SIZE			0xc0000000 /* 3GB */
+#define PHYS_SDRAM_2				0x100000000
+#define PHYS_SDRAM_2_SIZE			0x40000000 /* 1GB */
+#endif
+
+#define CONFIG_MXC_UART_BASE		UART1_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x20000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+#endif /* CONFIG_NAND_MXS */
+
+/* USB configs */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
+
+#define CONFIG_USBD_HS
+
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+#endif
+
+#define CONFIG_SERIAL_TAG
+#define CONFIG_FASTBOOT_USB_DEV 0
+
+#endif
diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h
index c12f383655b..ed5c179fc75 100644
--- a/include/configs/imx8qm_mek.h
+++ b/include/configs/imx8qm_mek.h
@@ -9,63 +9,201 @@
 #include <linux/sizes.h>
 #include <linux/stringify.h>
 #include <asm/arch/imx-regs.h>
+#include "imx_env.h"
 
 #define CONFIG_SYS_BOOTM_LEN		(64 * SZ_1M)
 
 #ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_MAX_SIZE				(124 * 1024)
+#define CONFIG_SPL_MAX_SIZE				(192 * 1024)
 #define CONFIG_SYS_MONITOR_LEN				(1024 * 1024)
 
-#define CONFIG_SPL_STACK		0x013E000
-#define CONFIG_SPL_BSS_START_ADDR	0x00128000
+/*
+ * 0x08081000 - 0x08180FFF is for m4_0 xip image,
+ * 0x08181000 - 0x008280FFF is for m4_1 xip image
+  * So 3rd container image may start from 0x8281000
+ */
+#define CONFIG_SYS_UBOOT_BASE 0x08281000
+
+#define CONFIG_SPL_STACK		0x013fff0
+#define CONFIG_SPL_BSS_START_ADDR      0x00130000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x1000	/* 4 KB */
-#define CONFIG_SYS_SPL_MALLOC_START	0x00120000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x3000	/* 12 KB */
+#ifdef CONFIG_TARGET_IMX8QM_MEK_A72_ONLY
+#define CONFIG_SERIAL_LPUART_BASE	0x5a080000	/* use UART2 */
+#define CONFIG_SYS_SPL_MALLOC_START	0xC2200000
+#else
 #define CONFIG_SERIAL_LPUART_BASE	0x5a060000
-#define CONFIG_MALLOC_F_ADDR		0x00120000
+#define CONFIG_SYS_SPL_MALLOC_START	0x82200000
+#endif
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x80000	/* 512 KB */
+#define CONFIG_MALLOC_F_ADDR		0x00138000
 
 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
 
 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
 #endif
 
+#ifdef CONFIG_TARGET_IMX8QM_MEK_A53_ONLY
+#define IMX_HDMI_FIRMWARE_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_64M)
+#define IMX_HDMITX_FIRMWARE_SIZE 0x20000
+#define IMX_HDMIRX_FIRMWARE_SIZE 0x20000
+#endif
+
+#define CONFIG_CMD_READ
+
 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
 #define USDHC1_BASE_ADDR                0x5B010000
 #define USDHC2_BASE_ADDR                0x5B020000
 
+#ifndef CONFIG_TARGET_IMX8QM_MEK_A72_ONLY
+#define CONFIG_PCIE_IMX
+#define CONFIG_CMD_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define FEC_QUIRK_ENET_MAC
+#define PHY_ANEG_TIMEOUT 20000
+
+/* ENET0 connects AR8031 on CPU board, ENET1 connects to base board */
+#define CONFIG_FEC_ENET_DEV 0
+
+#if (CONFIG_FEC_ENET_DEV == 0)
+#define IMX_FEC_BASE			0x5B040000
+#define CONFIG_FEC_MXC_PHYADDR          0x0
+#define CONFIG_ETHPRIME                 "eth0"
+#elif (CONFIG_FEC_ENET_DEV == 1)
+#define IMX_FEC_BASE			0x5B050000
+#define CONFIG_FEC_MXC_PHYADDR          0x1
+#define CONFIG_ETHPRIME                 "eth1"
+#endif
+
 #ifdef CONFIG_AHAB_BOOT
 #define AHAB_ENV "sec_boot=yes\0"
 #else
 #define AHAB_ENV "sec_boot=no\0"
 #endif
 
+
+#define JAILHOUSE_ENV \
+	"jh_mmcboot=" \
+		"setenv fdt_file imx8qm-mek-root.dtb;"\
+		"setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \
+		"run mmcboot; \0" \
+	"jh_netboot=" \
+		"setenv fdt_file imx8qm-mek-root.dtb;"\
+		"setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \
+		"run netboot; \0"
+
+#define XEN_BOOT_ENV \
+	    "domu-android-auto=no\0" \
+            "xenhyper_bootargs=console=dtuart dom0_mem=2048M dom0_max_vcpus=2 dom0_vcpus_pin=true hmp-unsafe=true\0" \
+            "xenlinux_bootargs= \0" \
+            "xenlinux_console=hvc0 earlycon=xen\0" \
+            "xenlinux_addr=0x9e000000\0" \
+            "dom0fdt_file=imx8qm-mek-dom0.dtb\0" \
+            "xenboot_common=" \
+                "${get_cmd} ${loadaddr} xen;" \
+                "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \
+                "if ${get_cmd} ${hdp_addr} ${hdp_file}; then; hdp load ${hdp_addr}; fi;" \
+                "${get_cmd} ${xenlinux_addr} ${image};" \
+                "fdt addr ${fdt_addr};" \
+                "fdt resize 256;" \
+                "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \
+                "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \
+		"if test ${domu-android-auto} = yes; then; " \
+			"fdt set /domu/doma android-auto <1>;" \
+			"fdt rm /gpio@5d090000 power-domains;" \
+		"fi;" \
+                "setenv bootargs ${xenhyper_bootargs};" \
+                "booti ${loadaddr} - ${fdt_addr};" \
+            "\0" \
+            "xennetboot=" \
+                "setenv get_cmd dhcp;" \
+                "setenv console ${xenlinux_console};" \
+                "run netargs;" \
+                "run xenboot_common;" \
+            "\0" \
+            "xenmmcboot=" \
+                "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \
+                "setenv console ${xenlinux_console};" \
+                "run mmcargs;" \
+                "run xenboot_common;" \
+            "\0" \
+/* Boot M4 */
+#define M4_BOOT_ENV \
+	"m4_0_image=m4_0.bin\0" \
+	"m4_1_image=m4_1.bin\0" \
+	"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
+	"loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
+	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
+	"m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
+#else
+#define MFG_NAND_PARTITION ""
+#endif
+
+#ifdef CONFIG_TARGET_IMX8QM_MEK_A72_ONLY
+#define HDP_LOAD_ENV
+#define HDPRX_LOAD_ENV
+#define INITRD_ADDR_ENV "initrd_addr=0xC3100000\0"
+#else
+#define HDP_LOAD_ENV \
+	"if run loadhdp; then; hdp load ${hdp_addr}; fi;"
+#define HDPRX_LOAD_ENV \
+	"if test ${hdprx_enable} = yes; then if run loadhdprx; then; hdprx load ${hdprx_addr}; fi; fi; "
+#define INITRD_ADDR_ENV "initrd_addr=0x83100000\0"
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	INITRD_ADDR_ENV \
+	"initrd_high=0xffffffffffffffff\0" \
+	"emmc_dev=0\0" \
+	"sd_dev=1\0"
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
+	M4_BOOT_ENV \
+	XEN_BOOT_ENV \
+	JAILHOUSE_ENV\
 	AHAB_ENV \
 	"script=boot.scr\0" \
 	"image=Image\0" \
-	"panel=NULL\0" \
-	"console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \
-	"fdt_addr=0x83000000\0"			\
+	SPLASH_IMAGE_ADDR \
+	CONFIG_CONSOLE \
+	FDT_ADDR \
 	"fdt_high=0xffffffffffffffff\0"		\
+	"cntr_addr=0x98000000\0"			\
+	"cntr_file=os_cntr_signed.bin\0" \
 	"boot_fdt=try\0" \
-	"fdt_file=undefined\0" \
-	"initrd_addr=0x83800000\0"		\
-	"initrd_high=0xffffffffffffffff\0" \
+	FDT_FILE \
 	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=1\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
 	"mmcautodetect=yes\0" \
-	"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+	"mmcargs=setenv bootargs console=${console},${baudrate} earlycon root=${mmcroot} " \
+		"cpufreq.default_governor=SCHEDUTIL\0" \
 	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"hdp_addr=0x9c000000\0" \
+	"hdprx_addr=0x9c800000\0" \
+	"hdp_file=hdmitxfw.bin\0" \
+	"hdprx_file=hdmirxfw.bin\0" \
+	"hdprx_enable=no\0" \
+	"loadhdp=fatload mmc ${mmcdev}:${mmcpart} ${hdp_addr} ${hdp_file}\0" \
+	"loadhdprx=fatload mmc ${mmcdev}:${mmcpart} ${hdprx_addr} ${hdprx_file}\0" \
 	"boot_os=booti ${loadaddr} - ${fdt_addr};\0" \
 	"loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
 	"auth_os=auth_cntr ${cntr_addr}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
+		HDP_LOAD_ENV \
+		HDPRX_LOAD_ENV \
 		"run mmcargs; " \
 		"if test ${sec_boot} = yes; then " \
 			"if run auth_os; then " \
@@ -84,9 +222,10 @@
 				"echo wait for boot; " \
 			"fi;" \
 		"fi;\0" \
-	"netargs=setenv bootargs console=${console} " \
+	"netargs=setenv bootargs console=${console},${baudrate} earlycon " \
 		"root=/dev/nfs " \
-		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \
+		"cpufreq.default_governor=SCHEDUTIL\0" \
 	"netboot=echo Booting from net ...; " \
 		"run netargs;  " \
 		"if test ${ip_dyn} = yes; then " \
@@ -94,6 +233,7 @@
 		"else " \
 			"setenv get_cmd tftp; " \
 		"fi; " \
+		"if ${get_cmd} ${hdp_addr} ${hdp_file}; then; hdp load ${hdp_addr}; fi;" \
 		"if test ${sec_boot} = yes; then " \
 			"${get_cmd} ${cntr_addr} ${cntr_file}; " \
 			"if run auth_os; then " \
@@ -105,7 +245,7 @@
 			"${get_cmd} ${loadaddr} ${image}; " \
 			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 				"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-					"booti ${loadaddr} - ${fdt_addr}; " \
+					"run boot_os; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
@@ -115,25 +255,103 @@
 		"fi;\0"
 
 /* Link Definitions */
+#ifdef CONFIG_TARGET_IMX8QM_MEK_A72_ONLY
+	#define CONFIG_SYS_INIT_SP_ADDR		0xC0200000
+#else
+	#define CONFIG_SYS_INIT_SP_ADDR		0x80200000
+#endif
 
-#define CONFIG_SYS_INIT_SP_ADDR         0x80200000
-
-/* Default environment is in SD */
+#if defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY)
+	#define FDT_ADDR	"fdt_addr=0xC3000000\0"
+	#define FDT_FILE	"fdt_file=imx8qm-mek-cockpit-a72.dtb\0"
+#elif defined(CONFIG_TARGET_IMX8QM_MEK_A53_ONLY)
+	#define FDT_ADDR	"fdt_addr=0x83000000\0"
+	#define FDT_FILE	"fdt_file=imx8qm-mek-cockpit-a53.dtb\0"
+#else
+	#define FDT_ADDR	"fdt_addr=0x83000000\0"
+	#define FDT_FILE	"fdt_file=undefined\0"
+#endif
 
 /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
-#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+#if defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY)
+	#define CONFIG_SYS_MMC_ENV_DEV		0  /* USDHC1 */
+	#define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC1 */
+#elif defined(CONFIG_TARGET_IMX8QM_MEK_A53_ONLY)
+	#define CONFIG_SYS_MMC_ENV_DEV		1  /* USDHC2 */
+	#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+#else
+	#define CONFIG_SYS_MMC_ENV_DEV		1  /* USDHC2 */
+	#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+#endif
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 
+#if defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY)
+#define CONFIG_CONSOLE "console=ttyLP2\0"
+#define SPLASH_IMAGE_ADDR	"splashimage=0xde000000\0"
+#else
+#define CONFIG_CONSOLE "console=ttyLP0\0"
+#define SPLASH_IMAGE_ADDR	"splashimage=0x9e000000\0"
+#endif
+
+#define CONFIG_NR_DRAM_BANKS		4
+#if defined(CONFIG_TARGET_IMX8QM_MEK_A53_ONLY)
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_2			0x880000000
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1 GB */
+#define PHYS_SDRAM_2_SIZE		0x80000000	/* 2 GB */
+#elif defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY)
+#define CONFIG_SYS_SDRAM_BASE		0xC0000000
+#define PHYS_SDRAM_1			0xC0000000
+#define PHYS_SDRAM_2			0x900000000
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1 GB */
+#define PHYS_SDRAM_2_SIZE		0x80000000	/* 2 GB */
+#else
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
 #define PHYS_SDRAM_1			0x80000000
 #define PHYS_SDRAM_2			0x880000000
 #define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
 #define PHYS_SDRAM_2_SIZE		0x100000000	/* 4 GB */
+#endif
 
 /* Generic Timer Definitions */
 #define COUNTER_FREQUENCY		8000000	/* 8MHz */
 
-/* Networking */
-#define CONFIG_FEC_XCV_TYPE		RGMII
+/* Serial */
+#define CONFIG_BAUDRATE			115200
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_CBSIZE              2048
+#define CONFIG_SYS_MAXARGS             64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_SERIAL_TAG
+
+/* USB Config */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_USBD_HS
+
+#endif
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/* USB OTG controller configs */
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#endif
+
+#if defined(CONFIG_ANDROID_SUPPORT)
+#include "imx8qm_mek_android.h"
+#elif defined (CONFIG_ANDROID_AUTO_SUPPORT)
+#include "imx8qm_mek_android_auto.h"
+#elif defined(CONFIG_IMX8_TRUSTY_XEN)
+#include "imx8qm_mek_trusty_xen.h"
+#endif
+
 
 #endif /* __IMX8QM_MEK_H */
diff --git a/include/configs/imx8qm_mek_android.h b/include/configs/imx8qm_mek_android.h
new file mode 100644
index 00000000000..8d44391db00
--- /dev/null
+++ b/include/configs/imx8qm_mek_android.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef IMX8QM_MEK_ANDROID_H
+#define IMX8QM_MEK_ANDROID_H
+
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+
+#define FSL_FASTBOOT_FB_DEV "mmc"
+
+#define IMX_HDMI_FIRMWARE_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_64M)
+#define IMX_HDMITX_FIRMWARE_SIZE 0x20000
+#define IMX_HDMIRX_FIRMWARE_SIZE 0x20000
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"splashpos=m,m\0"	  		\
+	"splashimage=0x9e000000\0" 		\
+	"fdt_high=0xffffffffffffffff\0"	  	\
+	"initrd_high=0xffffffffffffffff\0" 	\
+
+#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x801F8000
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#define NS_ARCH_ARM64 1
+#define KEYSLOT_HWPARTITION_ID   2
+#define KEYSLOT_BLKS             0x3FFF
+#define AVB_RPMB
+
+#define BOOTLOADER_RBIDX_OFFSET  0x3FE000
+#define BOOTLOADER_RBIDX_START   0x3FF000
+#define BOOTLOADER_RBIDX_LEN     0x08
+#define BOOTLOADER_RBIDX_INITVAL 0
+#endif
+
+#endif /* IMX8QM_MEK_ANDROID_H */
diff --git a/include/configs/imx8qm_mek_android_auto.h b/include/configs/imx8qm_mek_android_auto.h
new file mode 100644
index 00000000000..23d5cc3af0e
--- /dev/null
+++ b/include/configs/imx8qm_mek_android_auto.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef IMX8QM_MEK_ANDROID_AUTO_H
+#define IMX8QM_MEK_ANDROID_AUTO_H
+
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+#define CONFIG_SKIP_RESOURCE_CHECKING
+
+/* USB OTG controller configs */
+#ifdef CONFIG_USB_EHCI_HCD
+#ifndef CONFIG_MXC_USB_PORTSC
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#endif
+#endif
+
+#define FSL_FASTBOOT_FB_DEV "mmc"
+
+#define IMX_HDMI_FIRMWARE_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_64M)
+#define IMX_HDMITX_FIRMWARE_SIZE 0x20000
+#define IMX_HDMIRX_FIRMWARE_SIZE 0x20000
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"splashpos=m,m\0"	  \
+	"fdt_high=0xffffffffffffffff\0"	  \
+	"initrd_high=0xffffffffffffffff\0" \
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#define AVB_RPMB
+#define NS_ARCH_ARM64 1
+#define KEYSLOT_HWPARTITION_ID	2
+#define KEYSLOT_BLKS		0x3FFF
+
+#define BOOTLOADER_RBIDX_OFFSET  0x3FE000
+#define BOOTLOADER_RBIDX_START   0x3FF000
+#define BOOTLOADER_RBIDX_LEN     0x08
+#define BOOTLOADER_RBIDX_INITVAL 0
+#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x801F8000
+#endif
+
+#if defined(CONFIG_XEN)
+#include "imx8qm_mek_android_auto_xen.h"
+#endif
+
+#endif /* IMX8QM_MEK_ANDROID_AUTO_H */
diff --git a/include/configs/imx8qm_mek_android_auto_xen.h b/include/configs/imx8qm_mek_android_auto_xen.h
new file mode 100644
index 00000000000..9b8c357f981
--- /dev/null
+++ b/include/configs/imx8qm_mek_android_auto_xen.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef IMX8QM_MEK_ANDROID_AUTO_XEN_H
+#define IMX8QM_MEK_ANDROID_AUTO_XEN_H
+
+#undef CONFIG_SYS_SDRAM_BASE
+#undef CONFIG_NR_DRAM_BANKS
+#undef PHYS_SDRAM_1
+#undef PHYS_SDRAM_2
+#undef PHYS_SDRAM_1_SIZE
+#undef PHYS_SDRAM_2_SIZE
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_NR_DRAM_BANKS		2
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_2			0x200000000
+#define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
+#define PHYS_SDRAM_2_SIZE		0x60000000	/* 1536 MB */
+
+#undef CONFIG_LOADADDR
+#define CONFIG_LOADADDR			0x80080000
+#undef CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_INIT_SP_ADDR		0x81200000
+
+#undef CONFIG_REQUIRE_SERIAL_CONSOLE
+#undef CONFIG_IMX_SMMU
+
+#undef CONFIG_FASTBOOT_USB_DEV
+#define CONFIG_FASTBOOT_USB_DEV 0 /* Use OTG port, not typec port */
+
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_SPL_BSS_START_ADDR
+#undef CONFIG_SYS_SPL_MALLOC_START
+#undef CONFIG_MALLOC_F_ADDR
+#undef CONFIG_SPL_TEXT_BASE
+#undef CONFIG_SPL_STACK
+
+#define CONFIG_MALLOC_F_ADDR		0x80100000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
+#define CONFIG_SPL_BSS_START_ADDR	0x80300000
+#define CONFIG_SPL_STACK		0x80400000
+
+#define CONFIG_SYS_SPL_PTE_RAM_BASE	0x80500000
+#endif
+
+#endif /* IMX8QM_MEK_ANDROID_AUTO_XEN_H */
diff --git a/include/configs/imx8qm_val.h b/include/configs/imx8qm_val.h
new file mode 100644
index 00000000000..da30754e046
--- /dev/null
+++ b/include/configs/imx8qm_val.h
@@ -0,0 +1,268 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017-2019 NXP
+ */
+
+#ifndef __IMX8QM_VAL_H
+#define __IMX8QM_VAL_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+#include "imx_env.h"
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_MAX_SIZE				(192 * 1024)
+#define CONFIG_SYS_MONITOR_LEN				(1024 * 1024)
+
+/*
+ * 0x08081000 - 0x08180FFF is for m4_0 xip image,
+ * 0x08181000 - 0x008280FFF is for m4_1 xip image
+  * So 3rd container image may start from 0x8281000
+ */
+#define CONFIG_SYS_UBOOT_BASE 0x08281000
+
+#define CONFIG_SPL_STACK		0x013fff0
+#define CONFIG_SPL_BSS_START_ADDR      0x00130000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x1000	/* 4 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x82200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x80000	/* 512 KB */
+#define CONFIG_SERIAL_LPUART_BASE	0x5a060000
+#define CONFIG_MALLOC_F_ADDR		0x00138000
+
+#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
+
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_CMD_READ
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+#define USDHC1_BASE_ADDR                0x5B010000
+#define USDHC2_BASE_ADDR                0x5B020000
+#define USDHC3_BASE_ADDR                0x5B030000
+
+#define CONFIG_PCIE_IMX
+#define CONFIG_CMD_PCI
+#define CONFIG_PCI_SCAN_SHOW
+
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define FEC_QUIRK_ENET_MAC
+#define PHY_ANEG_TIMEOUT 20000
+
+/* ENET0 connects AR8031 on CPU board, ENET1 connects to base board */
+#define CONFIG_ETHPRIME                 "eth0"
+
+#ifdef CONFIG_AHAB_BOOT
+#define AHAB_ENV "sec_boot=yes\0"
+#else
+#define AHAB_ENV "sec_boot=no\0"
+#endif
+
+/* Boot M4 */
+#define M4_BOOT_ENV \
+	"m4_0_image=m4_0.bin\0" \
+	"m4_1_image=m4_1.bin\0" \
+	"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
+	"loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
+	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
+	"m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
+
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)"
+#endif
+
+#define XEN_BOOT_ENV \
+            "xenhyper_bootargs=console=dtuart dtuart=/serial@5a060000 dom0_mem=2048M dom0_max_vcpus=2 dom0_vcpus_pin=true hmp-unsafe=true\0" \
+            "xenlinux_bootargs= \0" \
+            "xenlinux_console=hvc0 earlycon=xen\0" \
+            "xenlinux_addr=0x9e000000\0" \
+	    	"dom0fdt_file=imx8qm-lpddr4-arm2-dom0.dtb\0" \
+            "xenboot_common=" \
+                "${get_cmd} ${loadaddr} xen;" \
+                "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \
+                "${get_cmd} ${xenlinux_addr} ${image};" \
+                "fdt addr ${fdt_addr};" \
+                "fdt resize 256;" \
+                "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \
+                "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \
+                "setenv bootargs ${xenhyper_bootargs};" \
+				"scu_rm dtb ${fdt_addr};" \
+                "booti ${loadaddr} - ${fdt_addr};" \
+            "\0" \
+            "xennetboot=" \
+                "setenv get_cmd dhcp;" \
+                "setenv console ${xenlinux_console};" \
+                "run netargs;" \
+                "run xenboot_common;" \
+            "\0" \
+            "xenmmcboot=" \
+                "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \
+                "setenv console ${xenlinux_console};" \
+                "run mmcargs;" \
+                "run xenboot_common;" \
+            "\0" \
+
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x83100000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"emmc_dev=0\0" \
+	"sd_dev=1\0"
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
+	XEN_BOOT_ENV \
+	M4_BOOT_ENV \
+	AHAB_ENV \
+	"script=boot.scr\0" \
+	"image=Image\0" \
+	"panel=NULL\0" \
+	"console=ttyLP0\0" \
+	"fdt_addr=0x83000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"cntr_addr=0x98000000\0"			\
+	"cntr_file=os_cntr_signed.bin\0" \
+	"boot_fdt=try\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} earlycon root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"hdp_addr=0x9c000000\0" \
+	"hdp_file=dpfw.bin\0" \
+	"loadhdp=fatload mmc ${mmcdev}:${mmcpart} ${hdp_addr} ${hdp_file}\0" \
+	"loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
+	"auth_os=auth_cntr ${cntr_addr}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"if run loadhdp; then; hdp load ${hdp_addr}; fi;" \
+		"run mmcargs; " \
+		"if test ${sec_boot} = yes; then " \
+			"if run auth_os; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo ERR: failed to authenticate; " \
+			"fi; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if run loadfdt; then " \
+					"booti ${loadaddr} - ${fdt_addr}; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"else " \
+				"echo wait for boot; " \
+			"fi;" \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} earlycon " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if ${get_cmd} ${hdp_addr} ${hdp_file}; then; hdp load ${hdp_addr}; fi;" \
+		"if test ${sec_boot} = yes; then " \
+			"${get_cmd} ${cntr_addr} ${cntr_file}; " \
+			"if run auth_os; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo ERR: failed to authenticate; " \
+			"fi; " \
+		"else " \
+			"${get_cmd} ${loadaddr} ${image}; " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+					"booti ${loadaddr} - ${fdt_addr}; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"else " \
+				"booti; " \
+			"fi;" \
+		"fi;\0"
+
+/* Link Definitions */
+
+#define CONFIG_SYS_INIT_SP_ADDR         0x80200000
+
+/* On LPDDR4 board, eMMC0 is for eMMC, USDHC1 is for SD on CPU board, USDHC2 is for SD on base board
+  * On DDR4 board, eMMC0 and USDHC1 is mux for NAND, USDHC2 is for SD
+  */
+#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_VAL
+#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC1 */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC1 */
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+
+#else
+
+#define CONFIG_SYS_MMC_ENV_DEV		2   /* USDHC2 */
+#define CONFIG_MMCROOT			"/dev/mmcblk2p2"  /* USDHC2 */
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_2			0x880000000
+#define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
+/* LPDDR4 board total DDR is 6GB, DDR4 board total DDR is 4GB */
+#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_VAL
+#define PHYS_SDRAM_2_SIZE		0x100000000	/* 4 GB */
+#else
+#define PHYS_SDRAM_2_SIZE		0x80000000	/* 2 GB */
+#endif
+
+/* Serial */
+#define CONFIG_BAUDRATE			115200
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_CBSIZE              2048
+#define CONFIG_SYS_MAXARGS             64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		8000000	/* 8MHz */
+
+#ifndef CONFIG_DM_PCA953X
+#define CONFIG_PCA953X
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#endif
+
+#define CONFIG_SERIAL_TAG
+
+/* USB Config */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_USBD_HS
+
+#endif
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/* USB OTG controller configs */
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#endif
+
+#endif /* __IMX8QM_VAL_H */
diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h
index b1c51e72bf6..2886a3b99b1 100644
--- a/include/configs/imx8qxp_mek.h
+++ b/include/configs/imx8qxp_mek.h
@@ -10,51 +10,123 @@
 #include <linux/stringify.h>
 #include <asm/arch/imx-regs.h>
 
+#include "imx_env.h"
+
 #ifdef CONFIG_SPL_BUILD
-#define CONFIG_SPL_MAX_SIZE				(124 * 1024)
+#define CONFIG_SPL_MAX_SIZE				(192 * 1024)
 #define CONFIG_SYS_MONITOR_LEN				(1024 * 1024)
 
-#define CONFIG_SPL_STACK		0x013E000
-#define CONFIG_SPL_BSS_START_ADDR	0x00128000
+/*
+ * 0x08081000 - 0x08180FFF is for m4_0 xip image,
+  * So 3rd container image may start from 0x8181000
+ */
+#define CONFIG_SYS_UBOOT_BASE 0x08181000
+
+#define CONFIG_SPL_STACK		0x013fff0
+#define CONFIG_SPL_BSS_START_ADDR      0x00130000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x1000	/* 4 KB */
-#define CONFIG_SYS_SPL_MALLOC_START	0x00120000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x3000	/* 12 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x82200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x80000	/* 512 KB */
 #define CONFIG_SERIAL_LPUART_BASE	0x5a060000
-#define CONFIG_MALLOC_F_ADDR		0x00120000
+#define CONFIG_MALLOC_F_ADDR		0x00138000
 
 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
 
 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
 #endif
 
+#define CONFIG_CMD_READ
+
 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
 #define USDHC1_BASE_ADDR                0x5B010000
 #define USDHC2_BASE_ADDR                0x5B020000
 
+#define CONFIG_PCIE_IMX
+#define CONFIG_CMD_PCI
+#define CONFIG_PCI_SCAN_SHOW
+
 #ifdef CONFIG_AHAB_BOOT
 #define AHAB_ENV "sec_boot=yes\0"
 #else
 #define AHAB_ENV "sec_boot=no\0"
 #endif
 
+/* Boot M4 */
+#define M4_BOOT_ENV \
+	"m4_0_image=m4_0.bin\0" \
+	"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
+	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x83100000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"emmc_dev=0\0" \
+	"sd_dev=1\0"
+
+#define JAILHOUSE_ENV \
+	"jh_mmcboot=" \
+		"setenv fdt_file imx8qxp-mek-root.dtb;"\
+		"setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \
+		"run mmcboot; \0" \
+	"jh_netboot=" \
+		"setenv fdt_file imx8qxp-mek-root.dtb;"\
+		"setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \
+		"run netboot; \0"
+
+#define XEN_BOOT_ENV \
+            "xenhyper_bootargs=console=dtuart dtuart=/serial@5a060000 dom0_mem=1024M dom0_max_vcpus=2 dom0_vcpus_pin=true\0" \
+            "xenlinux_bootargs= \0" \
+            "xenlinux_console=hvc0 earlycon=xen\0" \
+            "xenlinux_addr=0x9e000000\0" \
+            "dom0fdt_file=imx8qxp-mek-dom0.dtb\0" \
+            "xenboot_common=" \
+                "${get_cmd} ${loadaddr} xen;" \
+                "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \
+                "${get_cmd} ${xenlinux_addr} ${image};" \
+                "fdt addr ${fdt_addr};" \
+                "fdt resize 256;" \
+                "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \
+                "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \
+                "setenv bootargs ${xenhyper_bootargs};" \
+                "booti ${loadaddr} - ${fdt_addr};" \
+            "\0" \
+            "xennetboot=" \
+                "setenv get_cmd dhcp;" \
+                "setenv console ${xenlinux_console};" \
+                "run netargs;" \
+                "run xenboot_common;" \
+            "\0" \
+            "xenmmcboot=" \
+                "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \
+                "setenv console ${xenlinux_console};" \
+                "run mmcargs;" \
+                "run xenboot_common;" \
+            "\0" \
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
+	M4_BOOT_ENV \
+	XEN_BOOT_ENV \
+	JAILHOUSE_ENV\
 	AHAB_ENV \
 	"script=boot.scr\0" \
 	"image=Image\0" \
-	"panel=NULL\0" \
+	"splashimage=0x9e000000\0" \
 	"console=ttyLP0\0" \
 	"fdt_addr=0x83000000\0"			\
 	"fdt_high=0xffffffffffffffff\0"		\
+	"cntr_addr=0x98000000\0"			\
+	"cntr_file=os_cntr_signed.bin\0" \
 	"boot_fdt=try\0" \
 	"fdt_file=undefined\0" \
-	"initrd_addr=0x83800000\0"		\
-	"initrd_high=0xffffffffffffffff\0" \
 	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=1\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
 	"mmcautodetect=yes\0" \
-	"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot}\0 " \
+	"mmcargs=setenv bootargs console=${console},${baudrate} earlycon root=${mmcroot}\0 " \
 	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
@@ -82,7 +154,7 @@
 				"echo wait for boot; " \
 			"fi;" \
 		"fi;\0" \
-	"netargs=setenv bootargs console=${console},${baudrate} " \
+	"netargs=setenv bootargs console=${console},${baudrate} earlycon " \
 		"root=/dev/nfs " \
 		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
 	"netboot=echo Booting from net ...; " \
@@ -116,8 +188,6 @@
 
 #define CONFIG_SYS_INIT_SP_ADDR         0x80200000
 
-/* Default environment is in SD */
-
 /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
 #define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
 #define CONFIG_SYS_FSL_USDHC_NUM	2
@@ -125,23 +195,67 @@
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
 #define PHYS_SDRAM_1			0x80000000
 #define PHYS_SDRAM_2			0x880000000
+
+#ifdef CONFIG_TARGET_IMX8DX_MEK
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1 GB */
+#define PHYS_SDRAM_2_SIZE		0x00000000	/* 0 GB */
+#else
 #define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
 /* LPDDR4 board total DDR is 3GB */
 #define PHYS_SDRAM_2_SIZE		0x40000000	/* 1 GB */
+#endif
+
+/* Serial */
+#define CONFIG_BAUDRATE			115200
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_CBSIZE              2048
+#define CONFIG_SYS_MAXARGS             64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
 
 /* Generic Timer Definitions */
 #define COUNTER_FREQUENCY		8000000	/* 8MHz */
 
-#ifndef CONFIG_DM_PCA953X
-#define CONFIG_PCA953X
+#define CONFIG_SERIAL_TAG
+
+/* USB Config */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_USBD_HS
+
+#endif
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/* USB OTG controller configs */
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 #endif
 
 /* Networking */
+#define CONFIG_FEC_ENET_DEV 0
+
+#if (CONFIG_FEC_ENET_DEV == 0)
+#define IMX_FEC_BASE			0x5B040000
+#define CONFIG_FEC_MXC_PHYADDR          0x0
+#define CONFIG_ETHPRIME                 "eth0"
+#elif (CONFIG_FEC_ENET_DEV == 1)
+#define IMX_FEC_BASE			0x5B050000
+#define CONFIG_FEC_MXC_PHYADDR          0x1
+#define CONFIG_ETHPRIME                 "eth1"
+#endif
+
 #define CONFIG_FEC_XCV_TYPE		RGMII
+#define PHY_ANEG_TIMEOUT 20000
 
-/* Misc configuration */
-#define CONFIG_SYS_CBSIZE	2048
-#define CONFIG_SYS_MAXARGS	64
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#if defined(CONFIG_ANDROID_SUPPORT)
+#include "imx8qxp_mek_android.h"
+#elif defined (CONFIG_ANDROID_AUTO_SUPPORT)
+#include "imx8qxp_mek_android_auto.h"
+#endif
 
 #endif /* __IMX8QXP_MEK_H */
diff --git a/include/configs/imx8qxp_mek_android.h b/include/configs/imx8qxp_mek_android.h
new file mode 100644
index 00000000000..88a40dc96c9
--- /dev/null
+++ b/include/configs/imx8qxp_mek_android.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef IMX8QXP_MEK_ANDROID_H
+#define IMX8QXP_MEK_ANDROID_H
+
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+
+#define FSL_FASTBOOT_FB_DEV "mmc"
+
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"splashpos=m,m\0"	  		\
+	"splashimage=0x9e000000\0" 		\
+	"fdt_high=0xffffffffffffffff\0"	  	\
+	"initrd_high=0xffffffffffffffff\0" 	\
+
+#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x801F8000
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#define NS_ARCH_ARM64 1
+#define KEYSLOT_HWPARTITION_ID   2
+#define KEYSLOT_BLKS             0x3FFF
+#define AVB_RPMB
+
+#define BOOTLOADER_RBIDX_OFFSET  0x3FE000
+#define BOOTLOADER_RBIDX_START   0x3FF000
+#define BOOTLOADER_RBIDX_LEN     0x08
+#define BOOTLOADER_RBIDX_INITVAL 0
+#endif
+
+#endif /* IMX8QXP_MEK_ANDROID_H */
diff --git a/include/configs/imx8qxp_mek_android_auto.h b/include/configs/imx8qxp_mek_android_auto.h
new file mode 100644
index 00000000000..49c017c3400
--- /dev/null
+++ b/include/configs/imx8qxp_mek_android_auto.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef IMX8QXP_MEK_ANDROID_AUTO_H
+#define IMX8QXP_MEK_ANDROID_AUTO_H
+
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+#define CONFIG_SKIP_RESOURCE_CHECKING
+
+/* USB OTG controller configs */
+#ifdef CONFIG_USB_EHCI_HCD
+#ifndef CONFIG_MXC_USB_PORTSC
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#endif
+#endif
+
+#define FSL_FASTBOOT_FB_DEV "mmc"
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"splashpos=m,m\0"	  \
+	"fdt_high=0xffffffffffffffff\0"	  \
+	"initrd_high=0xffffffffffffffff\0" \
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#define NS_ARCH_ARM64 1
+#define AVB_RPMB
+#define KEYSLOT_HWPARTITION_ID	2
+#define KEYSLOT_BLKS		0x3FFF
+
+#define BOOTLOADER_RBIDX_OFFSET  0x3FE000
+#define BOOTLOADER_RBIDX_START   0x3FF000
+#define BOOTLOADER_RBIDX_LEN     0x08
+#define BOOTLOADER_RBIDX_INITVAL 0
+#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x801F8000
+#endif
+
+#endif /* IMX8QXP_MEK_ANDROID_AUTO_H */
diff --git a/include/configs/imx8qxp_val.h b/include/configs/imx8qxp_val.h
new file mode 100644
index 00000000000..a5dfb35a454
--- /dev/null
+++ b/include/configs/imx8qxp_val.h
@@ -0,0 +1,248 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __IMX8QXP_VAL_H
+#define __IMX8QXP_VAL_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#include "imx_env.h"
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_MAX_SIZE				(192 * 1024)
+#define CONFIG_SYS_MONITOR_LEN				(1024 * 1024)
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS     (0x8000000)  /*Put the FIT out of first 128MB boot area */
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_IDENT
+
+/*
+ * The memory layout on stack:  DATA section save + gd + early malloc
+ * the idea is re-use the early malloc (CONFIG_SYS_MALLOC_F_LEN) with
+ * CONFIG_SYS_SPL_MALLOC_START
+ */
+#define CONFIG_SPL_STACK		0x013fff0
+#define CONFIG_SPL_BSS_START_ADDR      0x00130000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x1000	/* 4 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x82200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x80000	/* 512 KB */
+#define CONFIG_SERIAL_LPUART_BASE	0x5a060000
+#define CONFIG_MALLOC_F_ADDR		0x00138000
+
+#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
+
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_CMD_READ
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+#define USDHC1_BASE_ADDR                0x5B010000
+#define USDHC2_BASE_ADDR                0x5B020000
+
+#define CONFIG_PCIE_IMX
+#define CONFIG_CMD_PCI
+#define CONFIG_PCI_SCAN_SHOW
+
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define PHY_ANEG_TIMEOUT 20000
+
+/* ENET0 connects AR8031 on CPU board, ENET1 connects to base board */
+#define CONFIG_ETHPRIME                 "eth0"
+
+#ifdef CONFIG_AHAB_BOOT
+#define AHAB_ENV "sec_boot=yes\0"
+#else
+#define AHAB_ENV "sec_boot=no\0"
+#endif
+
+/* Boot M4 */
+#define M4_BOOT_ENV \
+	"m4_0_image=m4_0.bin\0" \
+	"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
+	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)"
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"clk_ignore_unused "\
+	"\0" \
+	"initrd_addr=0x83100000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"emmc_dev=0\0" \
+	"sd_dev=1\0" \
+
+/* Initial environment variables */
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
+	"bootargs=console=ttyLP0,115200 ubi.mtd=nandrootfs "  \
+		"root=ubi0:nandrootfs rootfstype=ubifs "		     \
+		MFG_NAND_PARTITION \
+		"\0"\
+	"console=ttyLP0,115200 earlycon\0" \
+	"mtdparts=" MFG_NAND_PARTITION "\0" \
+	"fdt_addr=0x83000000\0"
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
+	M4_BOOT_ENV \
+	AHAB_ENV \
+	"script=boot.scr\0" \
+	"image=Image\0" \
+	"panel=NULL\0" \
+	"console=ttyLP0\0" \
+	"fdt_addr=0x83000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"cntr_addr=0x98000000\0"			\
+	"cntr_file=os_cntr_signed.bin\0" \
+	"boot_fdt=try\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} earlycon root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
+	"auth_os=auth_cntr ${cntr_addr}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${sec_boot} = yes; then " \
+			"if run auth_os; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo ERR: failed to authenticate; " \
+			"fi; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if run loadfdt; then " \
+					"booti ${loadaddr} - ${fdt_addr}; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"else " \
+				"echo wait for boot; " \
+			"fi;" \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} earlycon " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if test ${sec_boot} = yes; then " \
+			"${get_cmd} ${cntr_addr} ${cntr_file}; " \
+			"if run auth_os; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo ERR: failed to authenticate; " \
+			"fi; " \
+		"else " \
+			"${get_cmd} ${loadaddr} ${image}; " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+					"booti ${loadaddr} - ${fdt_addr}; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"else " \
+				"booti; " \
+			"fi;" \
+		"fi;\0"
+#endif
+
+/* Link Definitions */
+
+#define CONFIG_SYS_INIT_SP_ADDR         0x80200000
+
+/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board
+  */
+#ifdef CONFIG_TARGET_IMX8X_17X17_VAL
+#define CONFIG_SYS_MMC_ENV_DEV		0   /* USDHC1 */
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC1 */
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#else
+#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_2			0x880000000
+#if defined(CONFIG_TARGET_IMX8QXP_DDR3_VAL) || defined(CONFIG_TARGET_IMX8X_17X17_VAL)
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1 GB totally */
+#define PHYS_SDRAM_2_SIZE		0x00000000
+#else
+#define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
+/* LPDDR4 board total DDR is 3GB */
+#define PHYS_SDRAM_2_SIZE		0x40000000	/* 1 GB */
+#endif
+
+/* Serial */
+#define CONFIG_BAUDRATE			115200
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_CBSIZE              2048
+#define CONFIG_SYS_MAXARGS             64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		8000000	/* 8MHz */
+
+#ifndef CONFIG_DM_PCA953X
+#define CONFIG_PCA953X
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#endif
+
+#define CONFIG_SERIAL_TAG
+
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x40000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+
+#endif
+
+/* USB Config */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_USBD_HS
+
+#endif
+
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/* USB OTG controller configs */
+#ifdef CONFIG_USB_EHCI_HCD
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#endif
+
+#endif /* __IMX8QXP_VAL_H */
diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h
index 7da6802aa5f..44872194d69 100644
--- a/include/configs/imx8ulp_evk.h
+++ b/include/configs/imx8ulp_evk.h
@@ -8,6 +8,7 @@
 
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
+#include "imx_env.h"
 
 #define CONFIG_SYS_BOOTM_LEN		(SZ_64M)
 #define CONFIG_SPL_MAX_SIZE		(148 * 1024)
@@ -27,6 +28,10 @@
 
 #endif
 
+#define COUNTER_FREQUENCY       1000000 /* 1MHz */
+
+#define CONFIG_SERIAL_TAG
+
 /* ENET Config */
 #if defined(CONFIG_FEC_MXC)
 #define CONFIG_ETHPRIME                 "FEC"
@@ -38,8 +43,15 @@
 #define IMX_FEC_BASE			0x29950000
 #endif
 
+#ifdef CONFIG_AHAB_BOOT
+#define AHAB_ENV "sec_boot=yes\0"
+#else
+#define AHAB_ENV "sec_boot=no\0"
+#endif
+
 #ifdef CONFIG_DISTRO_DEFAULTS
 #define BOOT_TARGET_DEVICES(func) \
+	func(USB, usb, 0) \
 	func(MMC, mmc, 0)
 
 #include <config_distro_bootcmd.h>
@@ -47,20 +59,117 @@
 #define BOOTENV
 #endif
 
+#define JAILHOUSE_ENV \
+	"jh_clk= \0 " \
+	"jh_mmcboot=setenv jh_clk clk_ignore_unused mem=896MB; run loadimage; run mmcboot\0 " \
+	"jh_netboot=setenv jh_clk clk_ignore_unused mem=896MB; run netboot\0 "
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x83800000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"emmc_dev=0\0"\
+	"sd_dev=2\0"
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS		\
+	CONFIG_MFG_ENV_SETTINGS \
 	BOOTENV \
-	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	JAILHOUSE_ENV \
+	AHAB_ENV \
+	"scriptaddr=0x83500000\0" \
 	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
 	"image=Image\0" \
+	"splashimage=0x90000000\0" \
 	"console=ttyLP1,115200 earlycon\0" \
+	"fdtoverlay_addr_r=0x83040000\0"			\
 	"fdt_addr_r=0x83000000\0"			\
+	"fdt_addr=0x83000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"cntr_addr=0x98000000\0"			\
+	"cntr_file=os_cntr_signed.bin\0" \
 	"boot_fit=no\0" \
-	"fdtfile=imx8ulp-evk.dtb\0" \
-	"initrd_addr=0x83800000\0"		\
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"bootm_size=0x10000000\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=1\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
+	"loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
+	"auth_os=auth_cntr ${cntr_addr}\0" \
+	"boot_os=booti ${loadaddr} - ${fdt_addr_r};\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${sec_boot} = yes; then " \
+			"if run auth_os; then " \
+				"run boot_os; " \
+			"else " \
+				"echo ERR: failed to authenticate; " \
+			"fi; " \
+		"else " \
+			"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+				"bootm ${loadaddr}; " \
+			"else " \
+				"if run loadfdt; then " \
+					"run boot_os; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi;" \
+		"fi;\0" \
+	"netargs=setenv bootargs ${jh_clk} console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if test ${sec_boot} = yes; then " \
+			"${get_cmd} ${cntr_addr} ${cntr_file}; " \
+			"if run auth_os; then " \
+				"run boot_os; " \
+			"else " \
+				"echo ERR: failed to authenticate; " \
+			"fi; " \
+		"else " \
+			"${get_cmd} ${loadaddr} ${image}; " \
+			"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+				"bootm ${loadaddr}; " \
+			"else " \
+				"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
+					"run boot_os; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi;" \
+		"fi;\0" \
+	"bsp_bootcmd=echo Running BSP bootcmd ...; " \
+		"mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if test ${sec_boot} = yes; then " \
+				   "if run loadcntr; then " \
+					   "run mmcboot; " \
+				   "else run netboot; " \
+				   "fi; " \
+			    "else " \
+				   "if run loadimage; then " \
+					   "run mmcboot; " \
+				   "else run netboot; " \
+				   "fi; " \
+				"fi; " \
+		   "fi; " \
+	   "fi;"
 
 /* Link Definitions */
 
@@ -69,7 +178,7 @@
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
-#define CONFIG_MMCROOT			"/dev/mmcblk2p2"
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"
 
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
 #define PHYS_SDRAM			0x80000000
@@ -83,4 +192,11 @@
 
 /* Using ULP WDOG for reset */
 #define WDOG_BASE_ADDR			WDG3_RBASE
+/* USB Configs */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+#ifdef CONFIG_ANDROID_SUPPORT
+#include "imx8ulp_evk_android.h"
+#endif
+
 #endif
diff --git a/include/configs/imx8ulp_evk_android.h b/include/configs/imx8ulp_evk_android.h
new file mode 100644
index 00000000000..ae967eaf5b3
--- /dev/null
+++ b/include/configs/imx8ulp_evk_android.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef IMX8ULP_EVK_ANDROID_H
+#define IMX8ULP_EVK_ANDROID_H
+
+#define FSL_FASTBOOT_FB_DEV "mmc"
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"splashpos=m,m\0"			\
+	"splashimage=0x90000000\0"		\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"emmc_dev=0\0"                          \
+
+/* Enable mcu firmware flash */
+#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT
+#define ANDROID_MCU_FRIMWARE_DEV_TYPE DEV_MMC
+#define ANDROID_MCU_FIRMWARE_START 0x500000
+#define ANDROID_MCU_FIRMWARE_SIZE  0x40000
+#define ANDROID_MCU_FIRMWARE_HEADER_STACK 0x20020000
+#endif
+
+#define CONFIG_SYS_SPL_PTE_RAM_BASE    0x801F8000
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#define BOOTLOADER_RBIDX_OFFSET  0x3FE000
+#define BOOTLOADER_RBIDX_START   0x3FF000
+#define BOOTLOADER_RBIDX_LEN     0x08
+#define BOOTLOADER_RBIDX_INITVAL 0
+#endif
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#define AVB_RPMB
+#define KEYSLOT_HWPARTITION_ID 2
+#define KEYSLOT_BLKS             0x1FFF
+#define NS_ARCH_ARM64 1
+#endif
+
+#endif /* IMX8ULP_EVK_ANDROID_H */
diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h
new file mode 100644
index 00000000000..b6df1af108d
--- /dev/null
+++ b/include/configs/imx93_evk.h
@@ -0,0 +1,214 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __IMX93_EVK_H
+#define __IMX93_EVK_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+#include "imx_env.h"
+
+#define CONFIG_SYS_BOOTM_LEN		(SZ_64M)
+#define CONFIG_SPL_MAX_SIZE		(148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		SZ_512K
+#define CONFIG_SYS_UBOOT_BASE	\
+	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK		0x2051ddd0
+#define CONFIG_SPL_BSS_START_ADDR	0x2051e000
+#define CONFIG_SPL_BSS_MAX_SIZE		SZ_8K	/* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x83200000 /* Need disable simple malloc where still uses malloc_f area */
+#define CONFIG_SYS_SPL_MALLOC_SIZE	SZ_512K	/* 512 KB */
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set.  */
+#define CONFIG_MALLOC_F_ADDR		0x204D0000
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#endif
+
+#define CONFIG_CMD_READ
+#define CONFIG_SERIAL_TAG
+
+#ifdef CONFIG_AHAB_BOOT
+#define AHAB_ENV "sec_boot=yes\0"
+#else
+#define AHAB_ENV "sec_boot=no\0"
+#endif
+
+#ifdef CONFIG_DISTRO_DEFAULTS
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(USB, usb, 0)
+
+#include <config_distro_bootcmd.h>
+#else
+#define BOOTENV
+#endif
+
+#define JAILHOUSE_ENV \
+	"jh_mmcboot=setenv fdtfile imx93-11x11-evk-root.dtb; " \
+		    "setenv jh_clk clk_ignore_unused mem=1GB kvm-arm.mode=nvhe; " \
+		    "if run loadimage; then run mmcboot;" \
+		    "else run jh_netboot; fi; \0" \
+	"jh_netboot=setenv fdtfile imx93-11x11-evk-root.dtb; " \
+		    "setenv jh_clk clk_ignore_unused mem=1GB kvm-arm.mode=nvhe; run netboot; \0 "
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x83800000\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"emmc_dev=0\0"\
+	"sd_dev=1\0" \
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	JAILHOUSE_ENV \
+	CONFIG_MFG_ENV_SETTINGS \
+	BOOTENV \
+	AHAB_ENV \
+	"scriptaddr=0x83500000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"image=Image\0" \
+	"splashimage=0x90000000\0" \
+	"console=ttyLP0,115200 earlycon\0" \
+	"fdt_addr_r=0x83000000\0"			\
+	"fdt_addr=0x83000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"cntr_addr=0x98000000\0"			\
+	"cntr_file=os_cntr_signed.bin\0" \
+	"boot_fit=no\0" \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"bootm_size=0x10000000\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
+	"loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
+	"auth_os=auth_cntr ${cntr_addr}\0" \
+	"boot_os=booti ${loadaddr} - ${fdt_addr_r};\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${sec_boot} = yes; then " \
+			"if run auth_os; then " \
+				"run boot_os; " \
+			"else " \
+				"echo ERR: failed to authenticate; " \
+			"fi; " \
+		"else " \
+			"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+				"bootm ${loadaddr}; " \
+			"else " \
+				"if run loadfdt; then " \
+					"run boot_os; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi;" \
+		"fi;\0" \
+	"netargs=setenv bootargs ${jh_clk} console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if test ${sec_boot} = yes; then " \
+			"${get_cmd} ${cntr_addr} ${cntr_file}; " \
+			"if run auth_os; then " \
+				"run boot_os; " \
+			"else " \
+				"echo ERR: failed to authenticate; " \
+			"fi; " \
+		"else " \
+			"${get_cmd} ${loadaddr} ${image}; " \
+			"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+				"bootm ${loadaddr}; " \
+			"else " \
+				"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
+					"run boot_os; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi;" \
+		"fi;\0" \
+	"bsp_bootcmd=echo Running BSP bootcmd ...; " \
+		"mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if test ${sec_boot} = yes; then " \
+				   "if run loadcntr; then " \
+					   "run mmcboot; " \
+				   "else run netboot; " \
+				   "fi; " \
+			    "else " \
+				   "if run loadimage; then " \
+					   "run mmcboot; " \
+				   "else run netboot; " \
+				   "fi; " \
+				"fi; " \
+		   "fi; " \
+	   "fi;"
+
+/* Link Definitions */
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x200000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+
+#define CONFIG_SYS_SDRAM_BASE           0x80000000
+#define PHYS_SDRAM                      0x80000000
+#define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		2048
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_IMX_BOOTAUX
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+/* Using ULP WDOG for reset */
+#define WDOG_BASE_ADDR          WDG3_BASE_ADDR
+
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* USB configs */
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         2
+
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_ETHPRIME                 "eth0"
+
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#define CONFIG_FEC_MXC_PHYADDR          2
+
+#define DWC_NET_PHYADDR			1
+
+#define PHY_ANEG_TIMEOUT 20000
+
+#endif
+
+#endif
diff --git a/include/configs/imx_env.h b/include/configs/imx_env.h
new file mode 100644
index 00000000000..7eed730d64d
--- /dev/null
+++ b/include/configs/imx_env.h
@@ -0,0 +1,49 @@
+/* Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __IMX_COMMON_CONFIG_H
+#define __IMX_COMMON_CONFIG_H
+
+#ifdef CONFIG_ARM64
+    #define MFG_BOOT_CMD "booti "
+#else
+    #define MFG_BOOT_CMD "bootz "
+#endif
+
+#ifdef CONFIG_USB_PORT_AUTO
+    #define FASTBOOT_CMD "echo \"Run fastboot ...\"; fastboot auto; "
+#else
+    #define FASTBOOT_CMD "echo \"Run fastboot ...\"; fastboot 0; "
+#endif
+
+/* define the nandfit partiton environment for uuu */
+#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MQ) || \
+	defined(CONFIG_IMX8QM) || defined(CONFIG_IMX8QXP) || \
+	defined(CONFIG_IMX8DXL) || defined(CONFIG_IMX8MN) || \
+	defined(CONFIG_IMX8MP)
+#define MFG_NAND_FIT_PARTITION "nandfit_part=yes\0"
+#else
+#define MFG_NAND_FIT_PARTITION ""
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+		"rdinit=/linuxrc " \
+		"clk_ignore_unused "\
+		"\0" \
+	"kboot="MFG_BOOT_CMD"\0"\
+	"bootcmd_mfg=run mfgtool_args;" \
+        "if iminfo ${initrd_addr}; then " \
+            "if test ${tee} = yes; then " \
+                "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \
+            "else " \
+                MFG_BOOT_CMD "${loadaddr} ${initrd_addr} ${fdt_addr}; " \
+            "fi; " \
+        "else " \
+		FASTBOOT_CMD  \
+        "fi;\0" \
+	MFG_NAND_FIT_PARTITION \
+
+#endif
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 5ff931ee3bc..5d705b77107 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
+ * Copyright (C) 2012-2016 Freescale Semiconductor, Inc.
  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright 2018 NXP
  */
 
 #ifndef __MX6_COMMON_H
@@ -28,9 +30,19 @@
 #include <asm/mach-imx/gpio.h>
 
 /* Miscellaneous configurable options */
-#define CONFIG_SYS_CBSIZE	512
+#define CONFIG_SYS_CBSIZE	1024
 #define CONFIG_SYS_MAXARGS	32
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+/* NET PHY */
+#define PHY_ANEG_TIMEOUT 20000
 
 /* MMC */
+#define CONFIG_SUPPORT_EMMC_BOOT
 
+#ifdef CONFIG_IMX_OPTEE
+#define TEE_ENV "tee=yes\0"
+#else
+#define TEE_ENV "tee=no\0"
+#endif
 #endif
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index c1c012bbb53..3754ef8f3ed 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
  *
  * Configuration settings for the Freescale i.MX6Q SabreSD board.
  */
@@ -9,12 +10,47 @@
 #define __MX6QSABRE_COMMON_CONFIG_H
 
 #include <linux/stringify.h>
-
 #include "mx6_common.h"
+#include "imx_env.h"
 
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
 
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"eth0"
+
+#define CONFIG_PHY_ATHEROS
+
+#ifdef CONFIG_MX6S
+#define SYS_NOSMP "nosmp"
+#else
+#define SYS_NOSMP
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=8000000.nor:1m(boot),-(rootfs)\\;gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs)"
+#else
+#define MFG_NAND_PARTITION ""
+#endif
+
+#define CONFIG_CMD_READ
+#define CONFIG_SERIAL_TAG
+#define CONFIG_FASTBOOT_USB_DEV 0
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x12C00000\0" \
+	"initrd_high=0xffffffff\0" \
+	"emmc_dev=3\0"\
+	"sd_dev=2\0" \
+	"weim_uboot=0x08001000\0"\
+	"weim_base=0x08000000\0"\
+	"spi_bus=0\0"\
+	"spi_uboot=0x400\0" \
+	"mtdparts=" MFG_NAND_PARTITION \
+	"\0"\
+
 #ifdef CONFIG_SUPPORT_EMMC_BOOT
 #define EMMC_ENV \
 	"emmcdev=2\0" \
@@ -35,11 +71,112 @@
 #define EMMC_ENV ""
 #endif
 
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#if defined(CONFIG_NAND_BOOT)
+	/*
+	 * The dts also enables the WEIN NOR which is mtd0.
+	 * So the partions' layout for NAND is:
+	 *     mtd1: 16M      (uboot)
+	 *     mtd2: 16M      (kernel)
+	 *     mtd3: 16M      (dtb)
+	 *     mtd4: left     (rootfs)
+	 */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	TEE_ENV \
+	"fdt_addr=0x18000000\0" \
+	"tee_addr=0x20000000\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"splashimage=0x28000000\0" \
+	"console=" CONSOLE_DEV "\0" \
+	"bootargs=console=" CONSOLE_DEV ",115200 ubi.mtd=nandrootfs "  \
+		"root=ubi0:nandrootfs rootfstype=ubifs "		     \
+		MFG_NAND_PARTITION \
+		"\0" \
+	"bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\
+		"nand read ${fdt_addr} 0x5000000 0x100000;"\
+		"if test ${tee} = yes; then " \
+			"nand read ${tee_addr} 0x4000000 0x400000;"\
+			"bootm ${tee_addr} - ${fdt_addr};" \
+		"else " \
+			"bootz ${loadaddr} - ${fdt_addr};" \
+		"fi\0"
+
+#elif defined(CONFIG_SATA_BOOT)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+		CONFIG_MFG_ENV_SETTINGS \
+		TEE_ENV \
+		"image=zImage\0" \
+		"fdt_file=undefined\0" \
+		"fdt_addr=0x18000000\0" \
+		"fdt_high=0xffffffff\0"   \
+		"splashimage=0x28000000\0" \
+		"tee_addr=0x20000000\0" \
+		"tee_file=undefined\0" \
+		"findfdt="\
+			"if test $fdt_file = undefined; then " \
+				"if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \
+					"setenv fdt_file imx6qp-sabreauto.dtb; fi; " \
+				"if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \
+					"setenv fdt_file imx6q-sabreauto.dtb; fi; " \
+				"if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
+					"setenv fdt_file imx6dl-sabreauto.dtb; fi; " \
+				"if test $board_name = SABRESD && test $board_rev = MX6QP; then " \
+					"setenv fdt_file imx6qp-sabresd.dtb; fi; " \
+				"if test $board_name = SABRESD && test $board_rev = MX6Q; then " \
+					"setenv fdt_file imx6q-sabresd.dtb; fi; " \
+				"if test $board_name = SABRESD && test $board_rev = MX6DL; then " \
+					"setenv fdt_file imx6dl-sabresd.dtb; fi; " \
+				"if test $fdt_file = undefined; then " \
+					"echo WARNING: Could not determine dtb to use; " \
+				"fi; " \
+			"fi;\0" \
+		"findtee="\
+			"if test $tee_file = undefined; then " \
+				"if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \
+					"setenv tee_file uTee-6qpauto; fi; " \
+				"if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \
+					"setenv tee_file uTee-6qauto; fi; " \
+				"if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
+					"setenv tee_file uTee-6dlauto; fi; " \
+				"if test $board_name = SABRESD && test $board_rev = MX6QP; then " \
+					"setenv tee_file uTee-6qpsdb; fi; " \
+				"if test $board_name = SABRESD && test $board_rev = MX6Q; then " \
+					"setenv tee_file uTee-6qsdb; fi; " \
+				"if test $board_name = SABRESD && test $board_rev = MX6DL; then " \
+					"setenv tee_file uTee-6dlsdb; fi; " \
+				"if test $tee_file = undefined; then " \
+					"echo WARNING: Could not determine tee to use; fi; " \
+			"fi;\0" \
+		"bootargs=console=" CONSOLE_DEV ",115200 \0"\
+		"bootargs_sata=setenv bootargs ${bootargs} " \
+			"root=/dev/sda2 rootwait rw \0" \
+		"bootcmd_sata=run bootargs_sata; scsi scan; " \
+			"run findfdt; run findtee;" \
+			"fatload scsi 0:1 ${loadaddr} ${image}; " \
+			"fatload scsi 0:1 ${fdt_addr} ${fdt_file}; " \
+			"if test ${tee} = yes; then " \
+				"fatload scsi 0:1 ${tee_addr} ${tee_file}; " \
+				"bootm ${tee_addr} - ${fdt_addr}; " \
+			"else " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"fi \0"\
+		"bootcmd=run bootcmd_sata \0"
+
+#else
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	TEE_ENV \
+	"epdc_waveform=epdc_splash.bin\0" \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
-	"fdtfile=undefined\0" \
+	"fdt_file=undefined\0" \
 	"fdt_addr=0x18000000\0" \
+	"tee_addr=0x20000000\0" \
+	"tee_file=undefined\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
 	"console=" CONSOLE_DEV "\0" \
@@ -49,10 +186,12 @@
 	"dfu_alt_info=spl raw 0x400\0" \
 	"fdt_high=0xffffffff\0"	  \
 	"initrd_high=0xffffffff\0" \
-	"splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"splashimage=0x28000000\0" \
 	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
 	"mmcpart=1\0" \
 	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
 	"update_sd_firmware=" \
 		"if test ${ip_dyn} = yes; then " \
 			"setenv get_cmd dhcp; " \
@@ -67,8 +206,9 @@
 			"fi; "	\
 		"fi\0" \
 	EMMC_ENV	  \
-	"mmcargs=setenv bootargs console=${console},${baudrate} " \
-		"root=PARTUUID=${uuid} rootwait rw\0" \
+	"smp=" SYS_NOSMP "\0"\
+	"mmcargs=setenv bootargs console=${console},${baudrate} ${smp} " \
+		"root=${mmcroot}\0" \
 	"loadbootscript=" \
 		"load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script} || " \
 		"load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${script};\0" \
@@ -76,25 +216,30 @@
 		"source\0" \
 	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} || " \
 		"load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \
-	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile} || " \
-		"load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \
+	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} || " \
+		"load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdt_file}\0" \
+	"loadtee=load mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file} || " \
+		"load mmc ${mmcdev}:${mmcpart} ${tee_addr} boot/${tee_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
-		"run finduuid; " \
 		"run mmcargs; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if run loadfdt; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
+		"if test ${tee} = yes; then " \
+			"run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if run loadfdt; then " \
+					"bootz ${loadaddr} - ${fdt_addr}; " \
 				"else " \
-					"echo WARN: Cannot load the DT; " \
+					"if test ${boot_fdt} = try; then " \
+						"bootz; " \
+					"else " \
+						"echo WARN: Cannot load the DT; " \
+					"fi; " \
 				"fi; " \
-			"fi; " \
-		"else " \
-			"bootz; " \
+			"else " \
+				"bootz; " \
+			"fi;" \
 		"fi;\0" \
-	"netargs=setenv bootargs console=${console},${baudrate} " \
+	"netargs=setenv bootargs console=${console},${baudrate} ${smp} " \
 		"root=/dev/nfs " \
 		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
 	"netboot=echo Booting from net ...; " \
@@ -105,36 +250,61 @@
 			"setenv get_cmd tftp; " \
 		"fi; " \
 		"${get_cmd} ${image}; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if ${get_cmd} ${fdt_addr} ${fdtfile}; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
+		"if test ${tee} = yes; then " \
+			"${get_cmd} ${tee_addr} ${tee_file}; " \
+			"${get_cmd} ${fdt_addr} ${fdt_file}; " \
+			"bootm ${tee_addr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+					"bootz ${loadaddr} - ${fdt_addr}; " \
 				"else " \
-					"echo WARN: Cannot load the DT; " \
+					"if test ${boot_fdt} = try; then " \
+						"bootz; " \
+					"else " \
+						"echo WARN: Cannot load the DT; " \
+					"fi; " \
 				"fi; " \
+			"else " \
+				"bootz; " \
 			"fi; " \
-		"else " \
-			"bootz; " \
 		"fi;\0" \
 		"findfdt="\
-			"if test $fdtfile = undefined; then " \
+			"if test $fdt_file = undefined; then " \
 				"if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \
-					"setenv fdtfile imx6qp-sabreauto.dtb; fi; " \
+					"setenv fdt_file imx6qp-sabreauto.dtb; fi; " \
 				"if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \
-					"setenv fdtfile imx6q-sabreauto.dtb; fi; " \
+					"setenv fdt_file imx6q-sabreauto.dtb; fi; " \
 				"if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
-					"setenv fdtfile imx6dl-sabreauto.dtb; fi; " \
+					"setenv fdt_file imx6dl-sabreauto.dtb; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6QP; then " \
-					"setenv fdtfile imx6qp-sabresd.dtb; fi; " \
+					"setenv fdt_file imx6qp-sabresd.dtb; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6Q; then " \
-					"setenv fdtfile imx6q-sabresd.dtb; fi; " \
+					"setenv fdt_file imx6q-sabresd.dtb; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6DL; then " \
-					"setenv fdtfile imx6dl-sabresd.dtb; fi; " \
-				"if test $fdtfile = undefined; then " \
+					"setenv fdt_file imx6dl-sabresd.dtb; fi; " \
+				"if test $fdt_file = undefined; then " \
 					"echo WARNING: Could not determine dtb to use; fi; " \
 			"fi;\0" \
+		"findtee="\
+			"if test $tee_file = undefined; then " \
+				"if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \
+					"setenv tee_file uTee-6qpauto; fi; " \
+				"if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \
+					"setenv tee_file uTee-6qauto; fi; " \
+				"if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
+					"setenv tee_file uTee-6dlauto; fi; " \
+				"if test $board_name = SABRESD && test $board_rev = MX6QP; then " \
+					"setenv tee_file uTee-6qpsdb; fi; " \
+				"if test $board_name = SABRESD && test $board_rev = MX6Q; then " \
+					"setenv tee_file uTee-6qsdb; fi; " \
+				"if test $board_name = SABRESD && test $board_rev = MX6DL; then " \
+					"setenv tee_file uTee-6dlsdb; fi; " \
+				"if test $tee_file = undefined; then " \
+					"echo WARNING: Could not determine tee to use; fi; " \
+			"fi;\0" \
+
+#endif
 
 #define CONFIG_ARP_TIMEOUT     200UL
 
@@ -150,13 +320,42 @@
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
-/* Environment organization */
+#ifdef CONFIG_MTD_NOR_FLASH
+#define CONFIG_SYS_FLASH_BASE           WEIM_ARB_BASE_ADDR
+#define CONFIG_SYS_FLASH_SECT_SIZE      (128 * 1024)
+#define CONFIG_SYS_MAX_FLASH_SECT 256   /* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#endif
+
+#ifdef CONFIG_NAND_MXS
+
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x40000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_SATA)
+#define CONFIG_SYS_SATA_ENV_DEV		0
+#endif
+
+
+/* PMIC */
+#ifndef CONFIG_DM_PMIC
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+#endif
 
 /* Framebuffer */
-#define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
 
+#if defined(CONFIG_ANDROID_SUPPORT)
+#include "mx6sabreandroid_common.h"
+#else
 #define CONFIG_USBD_HS
 
+#endif /* CONFIG_ANDROID_SUPPORT */
 #endif                         /* __MX6QSABRE_COMMON_CONFIG_H */
diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h
index a212652fd7f..023cc137e76 100644
--- a/include/configs/mx6sabreauto.h
+++ b/include/configs/mx6sabreauto.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
  *
  * Configuration settings for the Freescale i.MX6Q SabreAuto board.
  */
@@ -14,17 +15,31 @@
 
 #define CONFIG_MXC_UART_BASE	UART4_BASE
 #define CONSOLE_DEV		"ttymxc3"
+#define CONFIG_MMCROOT		"/dev/mmcblk2p2"  /* SDHC3 */
+#define PHYS_SDRAM_SIZE		(2u * 1024 * 1024 * 1024)
+#ifdef CONFIG_MX6S
+#undef PHYS_SDRAM_SIZE
+#define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
+#endif
+
+#include "mx6sabre_common.h"
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_SYS_MMC_ENV_DEV		2  /* SDHC3 */
 
+/*Since the pin conflicts on EIM D18, disable the USB host if the NOR flash is enabled */
+#ifdef CONFIG_USB
 /* USB Configs */
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS	0
 
+#if !defined(CONFIG_DM_PCA953X) && defined(CONFIG_SYS_I2C)
 #define CONFIG_PCA953X
 #define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x30, 8}, {0x32, 8}, {0x34, 8} }
-
-#include "mx6sabre_common.h"
+#endif
+#endif
 
 /* Falcon Mode */
 #ifdef CONFIG_SPL_OS_BOOT
@@ -37,24 +52,4 @@
 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
 #endif
 
-#ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_BASE           WEIM_ARB_BASE_ADDR
-#define CONFIG_SYS_FLASH_SECT_SIZE      (128 * 1024)
-#define CONFIG_SYS_MAX_FLASH_SECT 256   /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#endif
-
-#define CONFIG_SYS_FSL_USDHC_NUM	2
-
-/* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define CONFIG_SYS_NAND_BASE           0x40000000
-
-/* DMA stuff, needed for GPMI/MXS NAND support */
-
-/* PMIC */
-#define CONFIG_POWER_PFUZE100
-#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
-
 #endif                         /* __MX6SABREAUTO_CONFIG_H */
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index 5a854b9d194..8ae510b82fc 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
  *
  * Configuration settings for the Freescale i.MX6Q SabreSD board.
  */
@@ -14,6 +15,15 @@
 
 #define CONFIG_MXC_UART_BASE	UART1_BASE
 #define CONSOLE_DEV		"ttymxc0"
+#define CONFIG_MMCROOT			"/dev/mmcblk2p2"  /* SDHC3 */
+
+#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QP)
+#define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
+#elif defined(CONFIG_MX6DL)
+#define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
+#elif defined(CONFIG_MX6S)
+#define PHYS_SDRAM_SIZE		(512u * 1024 * 1024)
+#endif
 
 #include "mx6sabre_common.h"
 
@@ -28,17 +38,22 @@
 
 #define CONFIG_SYS_FSL_USDHC_NUM	3
 
+/*
+ * imx6 q/dl/solo pcie would be failed to work properly in kernel, if
+ * the pcie module is iniialized/enumerated both in uboot and linux
+ * kernel.
+ * rootcause:imx6 q/dl/solo pcie don't have the reset mechanism.
+ * it is only be RESET by the POR. So, the pcie module only be
+ * initialized/enumerated once in one POR.
+ * Set to use pcie in kernel defaultly, mask the pcie config here.
+ * Remove the mask freely, if the uboot pcie functions, rather than
+ * the kernel's, are required.
+ */
 #ifdef CONFIG_CMD_PCI
 #define CONFIG_PCI_SCAN_SHOW
 #define CONFIG_PCIE_IMX
-#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(7, 12)
-#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(3, 19)
 #endif
 
-/* PMIC */
-#define CONFIG_POWER_PFUZE100
-#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
-
 /* USB Configs */
 #ifdef CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
@@ -47,4 +62,22 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1 /* Enabled USB controller number */
 #endif
 
+/*#define CONFIG_SPLASH_SCREEN*/
+/*#define CONFIG_MXC_EPDC*/
+
+/*
+ * SPLASH SCREEN Configs
+ */
+#if defined(CONFIG_MXC_EPDC)
+	/*
+	 * Framebuffer and LCD
+	 */
+	#undef LCD_TEST_PATTERN
+	/* #define CONFIG_SPLASH_IS_IN_MMC			1 */
+	#define LCD_BPP					LCD_MONOCHROME
+	/* #define CONFIG_SPLASH_SCREEN_ALIGN		1 */
+
+	#define CONFIG_WAVEFORM_BUF_SIZE		0x400000
+#endif /* CONFIG_SPLASH_SCREEN && CONFIG_MXC_EPDC */
+
 #endif                         /* __MX6SABRESD_CONFIG_H */
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 3da796d03a0..ff3b75623f6 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -9,6 +9,7 @@
 #define __CONFIG_H
 
 #include "mx6_common.h"
+#include "imx_env.h"
 
 #ifdef CONFIG_SPL
 #include "imx6_spl.h"
@@ -19,42 +20,74 @@
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
 
+/* PMIC */
+#ifndef CONFIG_DM_PMIC
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+#endif
+
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_ETHPRIME			"eth0"
+
+#define CONFIG_CMD_READ
+#define CONFIG_SERIAL_TAG
+#define CONFIG_FASTBOOT_USB_DEV 0
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x86800000\0" \
+	"initrd_high=0xffffffff\0" \
+    "emmc_dev=2\0"\
+    "sd_dev=1\0" \
+	"spi_bus=1\0"\
+	"spi_uboot=0x400\0"
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	TEE_ENV \
+	"epdc_waveform=epdc_splash.bin\0" \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
 	"console=ttymxc0\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
-	"fdt_file=imx6sl-evk.dtb\0" \
-	"fdt_addr=0x88000000\0" \
+	"fdt_file=undefined\0" \
+	"fdt_addr=0x83000000\0" \
+	"tee_addr=0x84000000\0" \
+	"tee_file=uTee-6slevk\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
-	"mmcdev=1\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=1\0" \
-	"finduuid=part uuid mmc 1:2 uuid\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
-		"root=PARTUUID=${uuid} rootwait rw\0" \
+		"root=${mmcroot}\0" \
 	"loadbootscript=" \
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
-		"run finduuid; " \
 		"run mmcargs; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if run loadfdt; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
+		"if test ${tee} = yes; then " \
+			"run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if run loadfdt; then " \
+					"bootz ${loadaddr} - ${fdt_addr}; " \
 				"else " \
-					"echo WARN: Cannot load the DT; " \
+					"if test ${boot_fdt} = try; then " \
+						"bootz; " \
+					"else " \
+						"echo WARN: Cannot load the DT; " \
+					"fi; " \
 				"fi; " \
+			"else " \
+				"bootz; " \
 			"fi; " \
-		"else " \
-			"bootz; " \
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} " \
 		"root=/dev/nfs " \
@@ -67,19 +100,29 @@
 			"setenv get_cmd tftp; " \
 		"fi; " \
 		"${get_cmd} ${image}; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
+		"if test ${tee} = yes; then " \
+			"${get_cmd} ${tee_addr} ${tee_file}; " \
+			"${get_cmd} ${fdt_addr} ${fdt_file}; " \
+			"bootm ${tee_addr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+					"bootz ${loadaddr} - ${fdt_addr}; " \
 				"else " \
-					"echo WARN: Cannot load the DT; " \
+					"if test ${boot_fdt} = try; then " \
+						"bootz; " \
+					"else " \
+						"echo WARN: Cannot load the DT; " \
+					"fi; " \
 				"fi; " \
-			"fi; " \
-		"else " \
-			"bootz; " \
-		"fi;\0"
+			"else " \
+				"bootz; " \
+			"fi;" \
+		"fi;\0" \
+	"findfdt="\
+		"if test $fdt_file = undefined; then " \
+			"setenv fdt_file imx6sl-evk.dtb; " \
+		"fi;\0" \
 
 /* Miscellaneous configurable options */
 
@@ -95,8 +138,6 @@
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
-/* Environment organization */
-
 /* USB Configs */
 #ifdef CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
@@ -105,6 +146,21 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	2
 #endif
 
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
 #define CONFIG_SYS_FSL_USDHC_NUM	3
+#define CONFIG_SYS_MMC_ENV_DEV 1
+
+/*
+ * SPLASH SCREEN Configs
+ */
+#ifdef CONFIG_MXC_EPDC
+	/*
+	 * Framebuffer and LCD
+	 */
+	#undef LCD_TEST_PATTERN
+	#define LCD_BPP					LCD_MONOCHROME
+
+	#define CONFIG_WAVEFORM_BUF_SIZE		0x400000
+#endif /* CONFIG_SPLASH_SCREEN */
 
 #endif				/* __CONFIG_H */
diff --git a/include/configs/mx6sll_val.h b/include/configs/mx6sll_val.h
new file mode 100644
index 00000000000..2939dedfe7f
--- /dev/null
+++ b/include/configs/mx6sll_val.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6SL EVK board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC1_BASE_ADDR
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+
+/* PMIC */
+#ifndef CONFIG_DM_PMIC
+#define CONFIG_POWER_LEGACY
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+		"rdinit=/linuxrc " \
+		"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
+		"g_mass_storage.file=/fat g_mass_storage.ro=1 " \
+		"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
+		"g_mass_storage.iSerialNumber=\"\" "\
+		"\0" \
+	"initrd_addr=0x86800000\0" \
+	"initrd_high=0xffffffff\0" \
+	"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	"epdc_waveform=epdc_splash.bin\0" \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x83000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"usb start; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+
+/* Miscellaneous configurable options */
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#ifdef CONFIG_LPDDR2_BOARD
+#define PHYS_SDRAM_SIZE			SZ_1G
+#else
+#define PHYS_SDRAM_SIZE			SZ_2G
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC1 */
+
+
+#define CONFIG_IOMUX_LPSR
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_VIDEO_SKIP
+#endif
+
+
+/*#define CONFIG_MXC_EPDC  1*/
+
+/*
+ * EPDC SPLASH SCREEN Configs
+ */
+#ifdef CONFIG_MXC_EPDC
+	/*
+	 * Framebuffer and LCD
+	 */
+	#undef LCD_TEST_PATTERN
+	#define LCD_BPP					LCD_MONOCHROME
+
+	#define CONFIG_WAVEFORM_BUF_SIZE		0x400000
+#endif /* CONFIG_MXC_EPDC */
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h
index 0793028ba1f..fcd15fffc1c 100644
--- a/include/configs/mx6sllevk.h
+++ b/include/configs/mx6sllevk.h
@@ -8,21 +8,39 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <linux/stringify.h>
 #include "mx6_common.h"
+#include "imx_env.h"
+
+#define CONFIG_CMD_READ
+#define CONFIG_SERIAL_TAG
+#define CONFIG_FASTBOOT_USB_DEV 0
 
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x86800000\0" \
+	"initrd_high=0xffffffff\0" \
+    "emmc_dev=1\0"\
+    "sd_dev=0\0" \
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	TEE_ENV \
 	"epdc_waveform=epdc_splash.bin\0" \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
 	"console=ttymxc0\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
-	"fdt_file=imx6sll-evk.dtb\0" \
+	"fdt_file=undefined\0" \
 	"fdt_addr=0x83000000\0" \
+	"tee_addr=0x84000000\0" \
+	"tee_file=uTee-6sllevk\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
+	"splashimage=0x8c000000\0" \
 	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=1\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
@@ -35,20 +53,25 @@
 		"source\0" \
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if run loadfdt; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
+		"if test ${tee} = yes; then " \
+			"run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if run loadfdt; then " \
+					"bootz ${loadaddr} - ${fdt_addr}; " \
 				"else " \
-					"echo WARN: Cannot load the DT; " \
+					"if test ${boot_fdt} = try; then " \
+						"bootz; " \
+					"else " \
+						"echo WARN: Cannot load the DT; " \
+					"fi; " \
 				"fi; " \
+			"else " \
+				"bootz; " \
 			"fi; " \
-		"else " \
-			"bootz; " \
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} " \
 		"root=/dev/nfs " \
@@ -62,19 +85,29 @@
 			"setenv get_cmd tftp; " \
 		"fi; " \
 		"${get_cmd} ${image}; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
+		"if test ${tee} = yes; then " \
+			"${get_cmd} ${tee_addr} ${tee_file}; " \
+			"${get_cmd} ${fdt_addr} ${fdt_file}; " \
+			"bootm ${tee_addr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+					"bootz ${loadaddr} - ${fdt_addr}; " \
 				"else " \
-					"echo WARN: Cannot load the DT; " \
+					"if test ${boot_fdt} = try; then " \
+						"bootz; " \
+					"else " \
+						"echo WARN: Cannot load the DT; " \
+					"fi; " \
 				"fi; " \
-			"fi; " \
-		"else " \
-			"bootz; " \
-		"fi;\0"
+			"else " \
+				"bootz; " \
+			"fi;" \
+		"fi;\0" \
+	"findfdt="\
+		"if test $fdt_file = undefined; then " \
+			"setenv fdt_file imx6sll-evk.dtb; " \
+		"fi;\0" \
 
 /* Miscellaneous configurable options */
 
@@ -105,5 +138,21 @@
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 #endif
 
-#include <linux/stringify.h>
+#ifdef CONFIG_DM_VIDEO
+#define CONFIG_VIDEO_LINK
+#endif
+
+/*
+ * EPDC SPLASH SCREEN Configs
+ */
+#ifdef CONFIG_MXC_EPDC
+	/*
+	 * Framebuffer and LCD
+	 */
+	#undef LCD_TEST_PATTERN
+	#define LCD_BPP					LCD_MONOCHROME
+
+	#define CONFIG_WAVEFORM_BUF_SIZE		0x400000
+#endif /* CONFIG_MXC_EPDC */
+
 #endif				/* __CONFIG_H */
diff --git a/include/configs/mx6sx_17x17_val.h b/include/configs/mx6sx_17x17_val.h
new file mode 100644
index 00000000000..d9ab9290446
--- /dev/null
+++ b/include/configs/mx6sx_17x17_val.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6SX 17x17 ARM2 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX6SX_17X17_VAL_CONFIG_H
+#define __MX6SX_17X17_VAL_CONFIG_H
+
+#include "mx6sx_val.h"
+
+#ifdef CONFIG_MXC_SPI  /* Pin conflict between SPI-NOR and SD2 */
+#define CONFIG_SYS_FSL_USDHC_NUM    2
+#define CONFIG_SYS_MMC_ENV_DEV		2   /* USDHC3 */
+#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
+#define CONFIG_MMCROOT			"/dev/mmcblk2p2"  /* USDHC3 */
+#else
+#define CONFIG_SYS_FSL_USDHC_NUM    3
+#define CONFIG_SYS_MMC_ENV_DEV		2   /* USDHC3 */
+#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
+#define CONFIG_MMCROOT			"/dev/mmcblk2p2"  /* USDHC3 */
+#endif
+
+#ifdef CONFIG_MXC_SPI
+#undef CONFIG_SYS_FLASH_SECT_SIZE
+#undef CONFIG_SYS_MAX_FLASH_SECT
+#define CONFIG_SYS_FLASH_SECT_SIZE	(256 * 1024)
+#define CONFIG_SYS_MAX_FLASH_SECT 512   /* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_PROTECTION
+#endif
+
+#endif
diff --git a/include/configs/mx6sx_19x19_val.h b/include/configs/mx6sx_19x19_val.h
new file mode 100644
index 00000000000..7d2b820ad0d
--- /dev/null
+++ b/include/configs/mx6sx_19x19_val.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6SX 19x19 ARM2 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX6SX_19X19_VAL_CONFIG_H
+#define __MX6SX_19X19_VAL_CONFIG_H
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_GIS
+#endif
+
+#include "mx6sx_val.h"
+
+#define CONFIG_SYS_FSL_USDHC_NUM    1
+#define CONFIG_SYS_MMC_ENV_DEV		0   /* USDHC1 */
+#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC1 */
+
+#endif
diff --git a/include/configs/mx6sx_val.h b/include/configs/mx6sx_val.h
new file mode 100644
index 00000000000..6740c6ebaad
--- /dev/null
+++ b/include/configs/mx6sx_val.h
@@ -0,0 +1,214 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6SX VAL board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX6SX_VAL_CONFIG_H
+#define __MX6SX_VAL_CONFIG_H
+
+#include "mx6_common.h"
+
+#define CONFIG_DBG_MONITOR
+
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#ifdef CONFIG_DM_ETH
+#define CONFIG_ETHPRIME                 "eth0"
+#else
+#define CONFIG_ETHPRIME                 "FEC"
+#endif
+#define CONFIG_FEC_MXC_PHYADDR          1
+
+#define CONFIG_PHY_ATHEROS
+
+#ifdef CONFIG_IMX_BOOTAUX
+#ifdef CONFIG_DM_SPI
+#define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000 /* Set to QSPI2 B flash at default */
+#define SF_QSPI2_B_CS_NUM 2
+#else
+#define CONFIG_SYS_AUXCORE_BOOTDATA 0x72000000 /* Set to QSPI2 B flash at default */
+#define SF_QSPI2_B_CS_NUM 1
+#endif
+
+#define UPDATE_M4_ENV \
+	"m4image=m4_qspi.bin\0" \
+	"m4_qspi_cs="__stringify(SF_QSPI2_B_CS_NUM)"\0" \
+	"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
+	"update_m4_from_sd=" \
+		"if sf probe 1:${m4_qspi_cs}; then " \
+			"if run loadm4image; then " \
+				"setexpr fw_sz ${filesize} + 0xffff; " \
+				"setexpr fw_sz ${fw_sz} / 0x10000; "	\
+				"setexpr fw_sz ${fw_sz} * 0x10000; "	\
+				"sf erase 0x0 ${fw_sz}; " \
+				"sf write ${loadaddr} 0x0 ${filesize}; " \
+			"fi; " \
+		"fi\0" \
+	"m4boot=sf probe 1:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
+#else
+#define UPDATE_M4_ENV ""
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) "
+#else
+#define MFG_NAND_PARTITION ""
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+		"rdinit=/linuxrc " \
+		"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
+		"g_mass_storage.file=/fat g_mass_storage.ro=1 " \
+		"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
+		"g_mass_storage.iSerialNumber=\"\" "\
+		MFG_NAND_PARTITION \
+		"\0" \
+	"initrd_addr=0x86800000\0" \
+	"initrd_high=0xffffffff\0" \
+	"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
+
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	"panel=Hannstar-XGA\0" \
+	"fdt_addr=0x83000000\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"console=ttymxc0\0" \
+	"bootargs=console=ttymxc0,115200 ubi.mtd=4 "  \
+		"root=ubi0:rootfs rootfstype=ubifs "		     \
+		"mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\
+	"bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\
+		"nand read ${fdt_addr} 0x5000000 0x100000;"\
+		"bootz ${loadaddr} - ${fdt_addr}\0"
+
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	UPDATE_M4_ENV \
+	"panel=Hannstar-XGA\0" \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x83000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#endif
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			SZ_1G
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#ifdef CONFIG_NOR_BOOT
+#define CONFIG_SYS_FLASH_BASE           WEIM_ARB_BASE_ADDR
+#define CONFIG_SYS_FLASH_SECT_SIZE	(128 * 1024)
+#define CONFIG_SYS_MAX_FLASH_BANKS 1    /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 256   /* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_CFI            /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER         /* Use drivers/cfi_flash.c */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#endif
+
+#ifdef CONFIG_NAND_MXS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#endif
+
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_VIDEO_SKIP
+#define CONFIG_SYS_CONSOLE_BG_COL            0x00
+#define CONFIG_SYS_CONSOLE_FG_COL            0xa0
+#ifdef CONFIG_VIDEO_GIS
+#define CONFIG_VIDEO_CSI
+#define CONFIG_VIDEO_PXP
+#define CONFIG_VIDEO_VADC
+#endif
+#endif
+#endif				/* __CONFIG_H */
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h
index 953f0710b11..5015494977d 100644
--- a/include/configs/mx6sxsabreauto.h
+++ b/include/configs/mx6sxsabreauto.h
@@ -9,22 +9,101 @@
 #define __CONFIG_H
 
 #include "mx6_common.h"
+#include "imx_env.h"
+
+#define CONFIG_DBG_MONITOR
 
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs)"
+#else
+#define MFG_NAND_PARTITION ""
+#endif
+
+#ifdef CONFIG_IMX_BOOTAUX
+
+/* Set to QSPI1 B flash at default */
+#ifdef CONFIG_DM_SPI
+#define CONFIG_SYS_AUXCORE_BOOTDATA 0x68000000
+#define SF_QSPI1_B_CS_NUM 2
+#else
+#define CONFIG_SYS_AUXCORE_BOOTDATA 0x62000000
+#define SF_QSPI1_B_CS_NUM 1
+#endif
+
+
+#define UPDATE_M4_ENV \
+	"m4image=m4_qspi.bin\0" \
+	"m4_qspi_cs="__stringify(SF_QSPI1_B_CS_NUM)"\0" \
+	"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
+	"update_m4_from_sd=" \
+		"if sf probe 0:${m4_qspi_cs}; then " \
+			"if run loadm4image; then " \
+				"setexpr fw_sz ${filesize} + 0xffff; " \
+				"setexpr fw_sz ${fw_sz} / 0x10000; "	\
+				"setexpr fw_sz ${fw_sz} * 0x10000; "	\
+				"sf erase 0x0 ${fw_sz}; " \
+				"sf write ${loadaddr} 0x0 ${filesize}; " \
+			"fi; " \
+		"fi\0" \
+	"m4boot=sf probe 0:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
+#else
+#define UPDATE_M4_ENV ""
+#endif
+
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x86800000\0" \
+	"initrd_high=0xffffffff\0" \
+	"sd_dev=2\0" \
+	"mtdparts=" MFG_NAND_PARTITION \
+	"\0"\
+
+#if defined(CONFIG_NAND_BOOT)
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	TEE_ENV \
+	"tee_addr=0x84000000\0" \
+	"splashimage=0x8c000000\0" \
+	"fdt_addr=0x83000000\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"console=ttymxc0\0" \
+	"bootargs=console=ttymxc0,115200 ubi.mtd=nandrootfs "  \
+		"root=ubi0:nandrootfs rootfstype=ubifs "		     \
+		MFG_NAND_PARTITION \
+		"\0" \
+	"bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\
+		"nand read ${fdt_addr} 0x5000000 0x100000;"\
+		"if test ${tee} = yes; then " \
+			"nand read ${tee_addr} 0x6000000 0x400000;"\
+			"bootm ${tee_addr} - ${fdt_addr};" \
+		"else " \
+			"bootz ${loadaddr} - ${fdt_addr};" \
+		"fi\0"
+
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	UPDATE_M4_ENV \
+	CONFIG_MFG_ENV_SETTINGS \
+	TEE_ENV \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
 	"console=ttymxc0\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
-	"fdt_file=imx6sx-sabreauto.dtb\0" \
-	"fdt_addr=0x88000000\0" \
+	"fdt_file=undefined\0" \
+	"fdt_addr=0x83000000\0" \
+	"tee_addr=0x84000000\0" \
+	"tee_file=uTee-6sxauto\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
-	"mmcdev=0\0" \
+	"splashimage=0x8c000000\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=1\0" \
-	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
 		"root=${mmcroot}\0" \
 	"loadbootscript=" \
@@ -33,20 +112,25 @@
 		"source\0" \
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if run loadfdt; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
+		"if test ${tee} = yes; then " \
+			"run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if run loadfdt; then " \
+					"bootz ${loadaddr} - ${fdt_addr}; " \
 				"else " \
-					"echo WARN: Cannot load the DT; " \
+					"if test ${boot_fdt} = try; then " \
+						"bootz; " \
+					"else " \
+						"echo WARN: Cannot load the DT; " \
+					"fi; " \
 				"fi; " \
+			"else " \
+				"bootz; " \
 			"fi; " \
-		"else " \
-			"bootz; " \
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} " \
 		"root=/dev/nfs " \
@@ -59,19 +143,31 @@
 			"setenv get_cmd tftp; " \
 		"fi; " \
 		"${get_cmd} ${image}; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
+		"if test ${tee} = yes; then " \
+			"${get_cmd} ${tee_addr} ${tee_file}; " \
+			"${get_cmd} ${fdt_addr} ${fdt_file}; " \
+			"bootm ${tee_addr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+					"bootz ${loadaddr} - ${fdt_addr}; " \
 				"else " \
-					"echo WARN: Cannot load the DT; " \
+					"if test ${boot_fdt} = try; then " \
+						"bootz; " \
+					"else " \
+						"echo WARN: Cannot load the DT; " \
+					"fi; " \
 				"fi; " \
-			"fi; " \
-		"else " \
-			"bootz; " \
-		"fi;\0"
+			"else " \
+				"bootz; " \
+			"fi;" \
+		"fi;\0" \
+	"findfdt="\
+		"if test $fdt_file = undefined; then " \
+			"setenv fdt_file imx6sx-sabreauto.dtb; " \
+		"fi;\0" \
+
+#endif
 
 /* Miscellaneous configurable options */
 
@@ -93,16 +189,15 @@
 /* NAND stuff */
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x40000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
 
 /* DMA stuff, needed for GPMI/MXS NAND support */
 
 /* Network */
-
-#define IMX_FEC_BASE			ENET2_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR          0x0
-
+#define CONFIG_ETHPRIME                 "eth1"
 #define CONFIG_FEC_XCV_TYPE             RGMII
-#define CONFIG_ETHPRIME                 "FEC"
+
+#define CONFIG_SERIAL_TAG
 
 #ifdef CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
@@ -112,5 +207,12 @@
 #endif
 
 #define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_MMCROOT			"/dev/mmcblk2p2"  /* USDHC3 */
+#define CONFIG_SYS_MMC_ENV_DEV		2  /*USDHC3*/
+
+#ifndef CONFIG_DM_PCA953X
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x30, 8}, {0x32, 8}, {0x34, 8} }
+#endif
 
 #endif				/* __CONFIG_H */
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 8bc86749aac..a0cabe565e6 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
  *
  * Configuration settings for the Freescale i.MX6SX Sabresd board.
  */
@@ -11,6 +12,9 @@
 #include <linux/stringify.h>
 
 #include "mx6_common.h"
+#include "imx_env.h"
+
+#define CONFIG_DBG_MONITOR
 
 #ifdef CONFIG_SPL
 #include "imx6_spl.h"
@@ -18,15 +22,31 @@
 
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 
+#define CONFIG_CMD_READ
+#define CONFIG_SERIAL_TAG
+#define CONFIG_FASTBOOT_USB_DEV 0
+
 #ifdef CONFIG_IMX_BOOTAUX
 /* Set to QSPI2 B flash at default */
+#ifdef CONFIG_DM_SPI
 #define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000
+#define SF_QSPI2_B_CS_NUM 2
+#elif defined(CONFIG_MX6SX_SABRESD_REVA)
+#define CONFIG_SYS_AUXCORE_BOOTDATA 0x71000000
+#define SF_QSPI2_B_CS_NUM 1
+#else
+#define CONFIG_SYS_AUXCORE_BOOTDATA 0x72000000
+#define SF_QSPI2_B_CS_NUM 1
+#endif
 
+/* When using M4 fastup demo, no need these M4 env, since QSPI is used by M4 */
+#ifndef CONFIG_SYS_AUXCORE_FASTUP
 #define UPDATE_M4_ENV \
 	"m4image=m4_qspi.bin\0" \
+	"m4_qspi_cs="__stringify(SF_QSPI2_B_CS_NUM)"\0" \
 	"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
 	"update_m4_from_sd=" \
-		"if sf probe 1:0; then " \
+		"if sf probe 1:${m4_qspi_cs}; then " \
 			"if run loadm4image; then " \
 				"setexpr fw_sz ${filesize} + 0xffff; " \
 				"setexpr fw_sz ${fw_sz} / 0x10000; "	\
@@ -35,49 +55,69 @@
 				"sf write ${loadaddr} 0x0 ${filesize}; " \
 			"fi; " \
 		"fi\0" \
-	"m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
+	"m4boot=sf probe 1:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
 #else
 #define UPDATE_M4_ENV ""
-#endif
+#endif /* CONFIG_SYS_AUXCORE_FASTUP */
+
+#else
+#define UPDATE_M4_ENV ""
+#endif /* CONFIG_IMX_BOOTAUX */
+
+#define CONFIG_MFG_ENV_SETTINGS \
+    CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x86800000\0" \
+	"initrd_high=0xffffffff\0" \
+    "emmc_dev=3\0"\
+    "sd_dev=3\0" \
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
 	UPDATE_M4_ENV \
+	TEE_ENV \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
 	"console=ttymxc0\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
-	"fdt_file=imx6sx-sdb.dtb\0" \
-	"fdt_addr=0x88000000\0" \
+	"fdt_file=undefined\0" \
+	"fdt_addr=0x83000000\0" \
+	"tee_addr=0x84000000\0" \
+	"tee_file=uTee-6sxsdb\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
-	"videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \
-	"mmcdev=3\0" \
+	"splashimage=0x8c000000\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=1\0" \
-	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
-		"root=PARTUUID=${uuid} rootwait rw\0" \
+		"root=${mmcroot}\0" \
 	"loadbootscript=" \
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
-		"run finduuid; " \
 		"run mmcargs; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if run loadfdt; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
+		"if test ${tee} = yes; then " \
+			"run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if run loadfdt; then " \
+					"bootz ${loadaddr} - ${fdt_addr}; " \
 				"else " \
-					"echo WARN: Cannot load the DT; " \
+					"if test ${boot_fdt} = try; then " \
+						"bootz; " \
+					"else " \
+						"echo WARN: Cannot load the DT; " \
+					"fi; " \
 				"fi; " \
+			"else " \
+				"bootz; " \
 			"fi; " \
-		"else " \
-			"bootz; " \
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} " \
 		"root=/dev/nfs " \
@@ -90,22 +130,29 @@
 			"setenv get_cmd tftp; " \
 		"fi; " \
 		"${get_cmd} ${image}; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
+		"if test ${tee} = yes; then " \
+			"${get_cmd} ${tee_addr} ${tee_file}; " \
+			"${get_cmd} ${fdt_addr} ${fdt_file}; " \
+			"bootm ${tee_addr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+					"bootz ${loadaddr} - ${fdt_addr}; " \
 				"else " \
-					"echo WARN: Cannot load the DT; " \
+					"if test ${boot_fdt} = try; then " \
+						"bootz; " \
+					"else " \
+						"echo WARN: Cannot load the DT; " \
+					"fi; " \
 				"fi; " \
-			"fi; " \
-		"else " \
-			"bootz; " \
+			"else " \
+				"bootz; " \
+			"fi;" \
 		"fi;\0" \
 	"findfdt="\
-		"if test test $board_rev = REVA ; then " \
-			"setenv fdt_file imx6sx-sdb-reva.dtb; fi; " \
+		"if test $fdt_file = undefined; then " \
+			"setenv fdt_file " CONFIG_DEFAULT_DEVICE_TREE ".dtb; " \
+		"fi;\0" \
 
 /* Miscellaneous configurable options */
 
@@ -122,15 +169,19 @@
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 /* MMC Configuration */
+
 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC4_BASE_ADDR
 
-/* Network */
 
-#define IMX_FEC_BASE			ENET_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR          0x1
+/* PMIC */
+#ifndef CONFIG_DM_PMIC
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+#endif
 
+/* Network */
+#define CONFIG_ETHPRIME                 "eth0"
 #define CONFIG_FEC_XCV_TYPE             RGMII
-#define CONFIG_ETHPRIME                 "FEC"
 
 #ifdef CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
@@ -142,17 +193,10 @@
 #ifdef CONFIG_CMD_PCI
 #define CONFIG_PCI_SCAN_SHOW
 #define CONFIG_PCIE_IMX
-#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(2, 0)
-#define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(2, 1)
-#endif
-
-#ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_DM_VIDEO
-#define CONFIG_VIDEO_BMP_LOGO
-#define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR
-#endif
 #endif
 
 #define CONFIG_SYS_FSL_USDHC_NUM	3
+#define CONFIG_MMCROOT			"/dev/mmcblk3p2"  /* USDHC4 */
+#define CONFIG_SYS_MMC_ENV_DEV		3  /*USDHC4*/
 
 #endif				/* __CONFIG_H */
diff --git a/include/configs/mx6ul_14x14_ddr3_val.h b/include/configs/mx6ul_14x14_ddr3_val.h
new file mode 100644
index 00000000000..9aa8cd68a84
--- /dev/null
+++ b/include/configs/mx6ul_14x14_ddr3_val.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6UL 14x14 DDR3 ARM2.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __MX6UL_14X14_DDR3_VAL_CONFIG_H
+#define __MX6UL_14X14_DDR3_VAL_CONFIG_H
+
+
+#define BOOTARGS_CMA_SIZE   ""
+
+#include "mx6ul_val.h"
+
+#define PHYS_SDRAM_SIZE			SZ_1G
+
+
+#ifdef CONFIG_DM_ETH
+#define CONFIG_CMD_MII
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_ENET_DEV 1
+
+#if (CONFIG_FEC_ENET_DEV == 0)
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x1
+#define CONFIG_FEC_XCV_TYPE             RMII
+#define CONFIG_ETHPRIME			"eth0"
+#elif (CONFIG_FEC_ENET_DEV == 1)
+#define IMX_FEC_BASE			ENET2_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x2
+#define CONFIG_FEC_XCV_TYPE             MII100
+#define CONFIG_ETHPRIME			"eth1"
+#endif
+
+#define CONFIG_FEC_MXC_MDIO_BASE ENET2_BASE_ADDR
+#endif
+
+#endif
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index c24578aff1c..10e425d9408 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  *
  * Configuration settings for the Freescale i.MX6UL 14x14 EVK board.
  */
@@ -12,9 +13,23 @@
 #include <linux/stringify.h>
 #include "mx6_common.h"
 #include <asm/mach-imx/gpio.h>
+#include "imx_env.h"
+
+/* uncomment for BEE support, needs to enable CONFIG_CMD_FUSE */
+/* #define CONFIG_CMD_BEE */
 
 #define is_mx6ul_9x9_evk()	CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK)
 
+#ifdef CONFIG_TARGET_MX6UL_9X9_EVK
+#define PHYS_SDRAM_SIZE		SZ_256M
+#define BOOTARGS_CMA_SIZE   "cma=96M "
+#else
+#define PHYS_SDRAM_SIZE		SZ_512M
+#define BOOTARGS_CMA_SIZE   ""
+/* DCDC used on 14x14 EVK, no PMIC */
+#undef CONFIG_LDO_BYPASS_CHECK
+#endif
+
 /* SPL options */
 #include "imx6_spl.h"
 
@@ -33,7 +48,54 @@
 
 #endif
 
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs)"
+#else
+#define MFG_NAND_PARTITION ""
+#endif
+
+#define CONFIG_CMD_READ
+#define CONFIG_SERIAL_TAG
+#define CONFIG_FASTBOOT_USB_DEV 0
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x86800000\0" \
+	"initrd_high=0xffffffff\0" \
+	"emmc_dev=1\0"\
+	"emmc_ack=1\0"\
+	"sd_dev=1\0" \
+	"mtdparts=" MFG_NAND_PARTITION \
+	"\0"\
+
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	TEE_ENV \
+	"splashimage=0x8c000000\0" \
+	"fdt_addr=0x83000000\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"tee_addr=0x84000000\0" \
+	"console=ttymxc0\0" \
+	"bootargs=console=ttymxc0,115200 ubi.mtd=nandrootfs "  \
+		"root=ubi0:rootfs rootfstype=ubifs "		     \
+		BOOTARGS_CMA_SIZE \
+		MFG_NAND_PARTITION \
+		"\0" \
+	"bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\
+		"nand read ${fdt_addr} 0x5000000 0x100000;"\
+		"if test ${tee} = yes; then " \
+			"nand read ${tee_addr} 0x6000000 0x400000;"\
+			"bootm ${tee_addr} - ${fdt_addr};" \
+		"else " \
+			"bootz ${loadaddr} - ${fdt_addr};" \
+		"fi\0"
+
+#else
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	TEE_ENV \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
 	"console=ttymxc0\0" \
@@ -41,15 +103,17 @@
 	"initrd_high=0xffffffff\0" \
 	"fdt_file=undefined\0" \
 	"fdt_addr=0x83000000\0" \
+	"tee_addr=0x84000000\0" \
+	"tee_file=undefined\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
-	"splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-	"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
+	"splashimage=0x8c000000\0" \
 	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=1\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
 	"mmcautodetect=yes\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		BOOTARGS_CMA_SIZE \
 		"root=${mmcroot}\0" \
 	"loadbootscript=" \
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
@@ -57,22 +121,28 @@
 		"source\0" \
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if run loadfdt; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
+		"if test ${tee} = yes; then " \
+			"run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if run loadfdt; then " \
+					"bootz ${loadaddr} - ${fdt_addr}; " \
 				"else " \
-					"echo WARN: Cannot load the DT; " \
+					"if test ${boot_fdt} = try; then " \
+						"bootz; " \
+					"else " \
+						"echo WARN: Cannot load the DT; " \
+					"fi; " \
 				"fi; " \
+			"else " \
+				"bootz; " \
 			"fi; " \
-		"else " \
-			"bootz; " \
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} " \
+		BOOTARGS_CMA_SIZE \
 		"root=/dev/nfs " \
 	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
 		"netboot=echo Booting from net ...; " \
@@ -83,19 +153,34 @@
 			"setenv get_cmd tftp; " \
 		"fi; " \
 		"${get_cmd} ${image}; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
+		"if test ${tee} = yes; then " \
+			"${get_cmd} ${tee_addr} ${tee_file}; " \
+			"${get_cmd} ${fdt_addr} ${fdt_file}; " \
+			"bootm ${tee_addr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+					"bootz ${loadaddr} - ${fdt_addr}; " \
 				"else " \
-					"echo WARN: Cannot load the DT; " \
+					"if test ${boot_fdt} = try; then " \
+						"bootz; " \
+					"else " \
+						"echo WARN: Cannot load the DT; " \
+					"fi; " \
 				"fi; " \
+			"else " \
+				"bootz; " \
 			"fi; " \
-		"else " \
-			"bootz; " \
 		"fi;\0" \
+		"findtee="\
+			"if test $tee_file = undefined; then " \
+				"if test $board_name = EVK && test $board_rev = 9X9; then " \
+					"setenv tee_file uTee-6ul9x9evk; fi; " \
+				"if test $board_name = EVK && test $board_rev = 14X14; then " \
+					"setenv tee_file uTee-6ulevk; fi; " \
+				"if test $fdt_file = undefined; then " \
+					"echo WARNING: Could not determine tee to use; fi; " \
+			"fi;\0" \
 		"findfdt="\
 			"if test $fdt_file = undefined; then " \
 				"if test $board_name = EVK && test $board_rev = 9X9; then " \
@@ -103,9 +188,12 @@
 				"if test $board_name = EVK && test $board_rev = 14X14; then " \
 					"setenv fdt_file imx6ul-14x14-evk.dtb; fi; " \
 				"if test $fdt_file = undefined; then " \
-					"echo WARNING: Could not determine dtb to use; fi; " \
+					"echo WARNING: Could not determine dtb to use; " \
+				"fi; " \
 			"fi;\0" \
 
+#endif
+
 /* Miscellaneous configurable options */
 
 /* Physical Memory Map */
@@ -121,8 +209,18 @@
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 /* environment organization */
+#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
 #define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
 
+/* NAND stuff */
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#endif
+
 /* USB Configs */
 #ifdef CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
@@ -131,26 +229,12 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 #endif
 
-#ifdef CONFIG_CMD_NET
-#define CONFIG_FEC_ENET_DEV		1
-
-#if (CONFIG_FEC_ENET_DEV == 0)
-#define IMX_FEC_BASE			ENET_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR          0x2
 #define CONFIG_FEC_XCV_TYPE             RMII
-#define CONFIG_ETHPRIME			"eth0"
-#elif (CONFIG_FEC_ENET_DEV == 1)
-#define IMX_FEC_BASE			ENET2_BASE_ADDR
-#define CONFIG_FEC_MXC_PHYADDR		0x1
-#define CONFIG_FEC_XCV_TYPE		RMII
 #define CONFIG_ETHPRIME			"eth1"
-#endif
-#endif
 
 #ifndef CONFIG_SPL_BUILD
 #if defined(CONFIG_DM_VIDEO)
-#define CONFIG_VIDEO_BMP_LOGO
-#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
+#define CONFIG_VIDEO_LINK
 #endif
 #endif
 
diff --git a/include/configs/mx6ul_14x14_lpddr2_val.h b/include/configs/mx6ul_14x14_lpddr2_val.h
new file mode 100644
index 00000000000..3cda6a72fdb
--- /dev/null
+++ b/include/configs/mx6ul_14x14_lpddr2_val.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6UL 14x14 LPDDR2 ARM2.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __MX6UL_14X14_LPDDR2_VAL_CONFIG_H
+#define __MX6UL_14X14_LPDDR2_VAL_CONFIG_H
+
+#ifdef CONFIG_MTD_NOR_FLASH
+/*
+ * Conflicts with SD1/SD2/VIDEO/ENET
+ * ENET is keeped, since only RXER conflicts.
+ * If removed ENET, we can not boot kernel, since sd1/sd2 is disabled
+ * when support weimnor.
+ */
+#undef CONFIG_FSL_USDHC
+#undef CONFIG_VIDEO
+#endif
+
+#define BOOTARGS_CMA_SIZE   "cma=96M "
+
+#include "mx6ul_val.h"
+
+#define PHYS_SDRAM_SIZE			SZ_256M
+
+
+#ifdef CONFIG_DM_ETH
+#define CONFIG_CMD_MII
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_ENET_DEV 1  /* The ENET1 has pin conflict with UART1 */
+
+#if (CONFIG_FEC_ENET_DEV == 0)
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x2
+#define CONFIG_FEC_XCV_TYPE             MII100
+#define CONFIG_ETHPRIME			"eth0"
+#elif (CONFIG_FEC_ENET_DEV == 1)
+#define IMX_FEC_BASE			ENET2_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x1
+#define CONFIG_FEC_XCV_TYPE             RMII
+#define CONFIG_ETHPRIME			"eth1"
+#endif
+
+#define CONFIG_FEC_MXC_MDIO_BASE ENET2_BASE_ADDR
+#endif
+
+#endif
diff --git a/include/configs/mx6ul_val.h b/include/configs/mx6ul_val.h
new file mode 100644
index 00000000000..13f59d5c779
--- /dev/null
+++ b/include/configs/mx6ul_val.h
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6UL ARM2 common.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __MX6UL_VAL_CONFIG_H
+#define __MX6UL_VAL_CONFIG_H
+
+
+#include "mx6_common.h"
+
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* PMIC */
+#ifndef CONFIG_DM_PMIC
+#define CONFIG_POWER_LEGACY
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) "
+#else
+#define MFG_NAND_PARTITION ""
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+		BOOTARGS_CMA_SIZE \
+		"rdinit=/linuxrc " \
+		"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
+		"g_mass_storage.file=/fat g_mass_storage.ro=1 " \
+		"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
+		"g_mass_storage.iSerialNumber=\"\" "\
+		MFG_NAND_PARTITION \
+		"clk_ignore_unused "\
+		"\0" \
+	"initrd_addr=0x86800000\0" \
+	"initrd_high=0xffffffff\0" \
+	"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
+
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	"panel=MCIMX28LCD\0" \
+	"fdt_addr=0x83000000\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"console=ttymxc0\0" \
+	"bootargs=console=ttymxc0,115200 ubi.mtd=4 "  \
+		"root=ubi0:rootfs rootfstype=ubifs "		     \
+		BOOTARGS_CMA_SIZE \
+		"mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\
+	"bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\
+		"nand read ${fdt_addr} 0x5000000 0x100000;"\
+		"bootz ${loadaddr} - ${fdt_addr}\0"
+
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	"panel=MCIMX28LCD\0" \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x83000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		BOOTARGS_CMA_SIZE \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		BOOTARGS_CMA_SIZE \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#endif
+
+/* Miscellaneous configurable options */
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* NAND stuff */
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#endif
+
+
+#ifdef CONFIG_MTD_NOR_FLASH
+#define CONFIG_SYS_FLASH_BASE           WEIM_ARB_BASE_ADDR
+#define CONFIG_SYS_FLASH_SECT_SIZE     (256 * 1024)
+#define CONFIG_SYS_MAX_FLASH_BANKS 1    /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT  512   /* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_CFI            /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER         /* Use drivers/cfi_flash.c */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#endif
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#else
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#endif
+
+#define CONFIG_SYS_MMC_ENV_DEV		0   /* USDHC1 */
+#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC1 */
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MXS
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_VIDEO_SKIP
+#endif
+
+#endif
diff --git a/include/configs/mx6ull_ddr3_val.h b/include/configs/mx6ull_ddr3_val.h
new file mode 100644
index 00000000000..0df7423e4af
--- /dev/null
+++ b/include/configs/mx6ull_ddr3_val.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6UL 14x14 DDR3 ARM2.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __MX6ULL_DDR3_VAL_CONFIG_H
+#define __MX6ULL_DDR3_VAL_CONFIG_H
+
+
+#define BOOTARGS_CMA_SIZE   ""
+
+#include "mx6ul_val.h"
+
+#define CONFIG_IOMUX_LPSR
+
+#define PHYS_SDRAM_SIZE			SZ_1G
+
+/*
+ * TSC pins conflict with I2C1 bus, so after TSC
+ * hardware rework, need to disable i2c1 bus, also
+ * need to disable PMIC and ldo bypass check.
+ */
+#ifdef CONFIG_MX6ULL_DDR3_VAL_TSC_REWORK
+#undef CONFIG_LDO_BYPASS_CHECK
+#undef CONFIG_SYS_I2C_MXC
+#undef CONFIG_SYS_I2C_LEGACY
+#undef CONFIG_CMD_I2C
+#undef CONFIG_POWER_PFUZE100_I2C_ADDR
+#undef CONFIG_POWER_PFUZE100
+#undef CONFIG_POWER_I2C
+#undef CONFIG_POWER_LEGACY
+#endif
+
+#ifdef CONFIG_DM_ETH
+#define CONFIG_CMD_MII
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_ENET_DEV 1
+
+#if (CONFIG_FEC_ENET_DEV == 0)
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x1
+#define CONFIG_FEC_XCV_TYPE             RMII
+#define CONFIG_ETHPRIME			"eth0"
+#elif (CONFIG_FEC_ENET_DEV == 1)
+#define IMX_FEC_BASE			ENET2_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x2
+#define CONFIG_FEC_XCV_TYPE             MII100
+#define CONFIG_ETHPRIME			"eth1"
+#endif
+
+#define CONFIG_FEC_MXC_MDIO_BASE ENET2_BASE_ADDR
+#endif
+
+
+/* #define CONFIG_SPLASH_SCREEN*/
+/* #define CONFIG_MXC_EPDC*/
+
+/*
+ * SPLASH SCREEN Configs
+ */
+#if defined(CONFIG_MXC_EPDC)
+/*
+ * Framebuffer and LCD
+ */
+#undef LCD_TEST_PATTERN
+/* #define CONFIG_SPLASH_IS_IN_MMC			1 */
+#define LCD_BPP					LCD_MONOCHROME
+/* #define CONFIG_SPLASH_SCREEN_ALIGN		1 */
+
+#define CONFIG_WAVEFORM_BUF_SIZE		0x400000
+#endif
+
+#endif
diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h
index 6bcca11c4c2..1c57c18d55a 100644
--- a/include/configs/mx6ullevk.h
+++ b/include/configs/mx6ullevk.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  *
  * Configuration settings for the Freescale i.MX6UL 14x14 EVK board.
  */
@@ -13,8 +14,19 @@
 #include <linux/stringify.h>
 #include "mx6_common.h"
 #include <asm/mach-imx/gpio.h>
+#include "imx_env.h"
 
-#define PHYS_SDRAM_SIZE	SZ_512M
+#define is_mx6ull_9x9_evk()	CONFIG_IS_ENABLED(TARGET_MX6ULL_9X9_EVK)
+
+#ifdef CONFIG_TARGET_MX6ULL_9X9_EVK
+#define PHYS_SDRAM_SIZE		SZ_256M
+#define BOOTARGS_CMA_SIZE   "cma=96M "
+#else
+#define PHYS_SDRAM_SIZE		SZ_512M
+#define BOOTARGS_CMA_SIZE   ""
+/* DCDC used on 14x14 EVK, no PMIC */
+#undef CONFIG_LDO_BYPASS_CHECK
+#endif
 
 #define CONFIG_MXC_UART_BASE		UART1_BASE
 
@@ -23,14 +35,62 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
 
 /* NAND pin conflicts with usdhc2 */
-#ifdef CONFIG_SYS_USE_NAND
+#ifdef CONFIG_NAND_MXS
 #define CONFIG_SYS_FSL_USDHC_NUM	1
 #else
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #endif
+
+#endif
+
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs)"
+#else
+#define MFG_NAND_PARTITION ""
 #endif
 
+#define CONFIG_CMD_READ
+#define CONFIG_SERIAL_TAG
+#define CONFIG_FASTBOOT_USB_DEV 0
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x86800000\0" \
+	"initrd_high=0xffffffff\0" \
+	"emmc_dev=1\0"\
+	"emmc_ack=1\0"\
+	"sd_dev=1\0" \
+	"mtdparts=" MFG_NAND_PARTITION \
+	"\0"\
+
+#if defined(CONFIG_NAND_BOOT)
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	TEE_ENV \
+	"splashimage=0x8c000000\0" \
+	"fdt_addr=0x83000000\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"tee_addr=0x84000000\0" \
+	"console=ttymxc0\0" \
+	"bootargs=console=ttymxc0,115200 ubi.mtd=nandrootfs "  \
+		"root=ubi0:rootfs rootfstype=ubifs "		     \
+		BOOTARGS_CMA_SIZE \
+		MFG_NAND_PARTITION \
+		"\0" \
+	"bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\
+		"nand read ${fdt_addr} 0x5000000 0x100000;"\
+		"if test ${tee} = yes; then " \
+			"nand read ${tee_addr} 0x6000000 0x400000;"\
+			"bootm ${tee_addr} - ${fdt_addr};" \
+		"else " \
+			"bootz ${loadaddr} - ${fdt_addr};" \
+		"fi\0"
+
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	TEE_ENV \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
 	"console=ttymxc0\0" \
@@ -38,14 +98,17 @@
 	"initrd_high=0xffffffff\0" \
 	"fdt_file=undefined\0" \
 	"fdt_addr=0x83000000\0" \
+	"tee_addr=0x84000000\0" \
+	"tee_file=undefined\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
-	"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
+	"splashimage=0x8c000000\0" \
 	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=1\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
 	"mmcautodetect=yes\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		BOOTARGS_CMA_SIZE \
 		"root=${mmcroot}\0" \
 	"loadbootscript=" \
 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
@@ -53,35 +116,32 @@
 		"source\0" \
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if run loadfdt; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
+		"if test ${tee} = yes; then " \
+			"run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if run loadfdt; then " \
+					"bootz ${loadaddr} - ${fdt_addr}; " \
 				"else " \
-					"echo WARN: Cannot load the DT; " \
+					"if test ${boot_fdt} = try; then " \
+						"bootz; " \
+					"else " \
+						"echo WARN: Cannot load the DT; " \
+					"fi; " \
 				"fi; " \
+			"else " \
+				"bootz; " \
 			"fi; " \
-		"else " \
-			"bootz; " \
 		"fi;\0" \
-		"findfdt="\
-			"if test $fdt_file = undefined; then " \
-				"if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \
-					"setenv fdt_file imx6ulz-14x14-evk.dtb; fi; " \
-				"if test $board_name = EVK && test $board_rev = 14X14; then " \
-					"setenv fdt_file imx6ull-14x14-evk.dtb; fi; " \
-				"if test $fdt_file = undefined; then " \
-					"echo WARNING: Could not determine dtb to use; " \
-				"fi; " \
-			"fi;\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} " \
+		BOOTARGS_CMA_SIZE \
 		"root=/dev/nfs " \
 	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
 		"netboot=echo Booting from net ...; " \
+		"${usb_net_cmd}; " \
 		"run netargs; " \
 		"if test ${ip_dyn} = yes; then " \
 			"setenv get_cmd dhcp; " \
@@ -89,19 +149,51 @@
 			"setenv get_cmd tftp; " \
 		"fi; " \
 		"${get_cmd} ${image}; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
+		"if test ${tee} = yes; then " \
+			"${get_cmd} ${tee_addr} ${tee_file}; " \
+			"${get_cmd} ${fdt_addr} ${fdt_file}; " \
+			"bootm ${tee_addr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+					"bootz ${loadaddr} - ${fdt_addr}; " \
 				"else " \
-					"echo WARN: Cannot load the DT; " \
+					"if test ${boot_fdt} = try; then " \
+						"bootz; " \
+					"else " \
+						"echo WARN: Cannot load the DT; " \
+					"fi; " \
 				"fi; " \
+			"else " \
+				"bootz; " \
 			"fi; " \
-		"else " \
-			"bootz; " \
 		"fi;\0" \
+		"findfdt="\
+			"if test $fdt_file = undefined; then " \
+				"if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \
+					"setenv fdt_file imx6ulz-14x14-evk.dtb; fi; " \
+				"if test $board_name = EVK && test $board_rev = 9X9; then " \
+					"setenv fdt_file imx6ull-9x9-evk.dtb; fi; " \
+				"if test $board_name = EVK && test $board_rev = 14X14; then " \
+					"setenv fdt_file imx6ull-14x14-evk.dtb; fi; " \
+				"if test $fdt_file = undefined; then " \
+					"echo WARNING: Could not determine dtb to use; " \
+				"fi; " \
+			"fi;\0" \
+		"findtee="\
+			"if test $tee_file = undefined; then " \
+				"if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \
+					"setenv tee_file uTee-6ulzevk; fi; " \
+				"if test $board_name = EVK && test $board_rev = 9X9; then " \
+					"setenv tee_file uTee-6ullevk; fi; " \
+				"if test $board_name = EVK && test $board_rev = 14X14; then " \
+					"setenv tee_file uTee-6ullevk; fi; " \
+				"if test $tee_file = undefined; then " \
+					"echo WARNING: Could not determine tee to use; " \
+				"fi; " \
+			"fi;\0" \
+
+#endif
 
 /* Miscellaneous configurable options */
 
@@ -118,16 +210,34 @@
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 /* environment organization */
+#define CONFIG_SYS_MMC_ENV_DEV		1	/* USDHC2 */
 #define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
 
 #define CONFIG_IOMUX_LPSR
 
-#ifdef CONFIG_CMD_NET
-#define CONFIG_FEC_ENET_DEV		1
-#if (CONFIG_FEC_ENET_DEV == 0)
-#define CONFIG_ETHPRIME			"eth0"
-#elif (CONFIG_FEC_ENET_DEV == 1)
+/* NAND stuff */
+#ifdef CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#endif
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#define CONFIG_FEC_XCV_TYPE             RMII
 #define CONFIG_ETHPRIME			"eth1"
+
+#ifndef CONFIG_SPL_BUILD
+#if defined(CONFIG_DM_VIDEO)
+#define CONFIG_VIDEO_LINK
 #endif
 #endif
 
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 2e976df6985..8fb2dcd201a 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -24,12 +24,14 @@
 #define CONFIG_IOMUX_LPSR
 
 /* Miscellaneous configurable options */
-#define CONFIG_SYS_CBSIZE		512
+#define CONFIG_SYS_CBSIZE		2048
 #define CONFIG_SYS_MAXARGS		32
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
 /* UART */
 
-/* MMC */
+/* NET PHY */
+#define PHY_ANEG_TIMEOUT 20000
 
 #define CONFIG_ARMV7_SECURE_BASE	0x00900000
 
@@ -39,4 +41,10 @@
  * initialization since it was already done by ATF or OPTEE
  */
 
+#ifdef CONFIG_IMX_OPTEE
+#define TEE_ENV "tee=yes\0"
+#else
+#define TEE_ENV "tee=no\0"
+#endif
+
 #endif
diff --git a/include/configs/mx7d_12x12_ddr3_val.h b/include/configs/mx7d_12x12_ddr3_val.h
new file mode 100644
index 00000000000..a1f43d1a4ee
--- /dev/null
+++ b/include/configs/mx7d_12x12_ddr3_val.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * Configuration settings for the Freescale i.MX7D 12x12 DDR3 ARM2 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX7D_12X12_DDR3_VAL_CONFIG_H
+#define __MX7D_12X12_DDR3_VAL_CONFIG_H
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC3 */
+
+#define PHYS_SDRAM_SIZE			SZ_1G
+
+
+#include "mx7d_val.h"
+
+#endif
diff --git a/include/configs/mx7d_12x12_lpddr3_val.h b/include/configs/mx7d_12x12_lpddr3_val.h
new file mode 100644
index 00000000000..76aee246817
--- /dev/null
+++ b/include/configs/mx7d_12x12_lpddr3_val.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX7D 12x12 LPDDR3 ARM2 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX7D_12X12_LPDDR3_VAL_CONFIG_H
+#define __MX7D_12X12_LPDDR3_VAL_CONFIG_H
+
+#define CONFIG_SYS_FSL_USDHC_NUM    3
+#define CONFIG_SYS_MMC_ENV_DEV		0   /* USDHC1 */
+#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC1 */
+
+#define PHYS_SDRAM_SIZE			SZ_2G
+
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#ifdef CONFIG_DM_ETH
+#define CONFIG_ETHPRIME                 "eth0"
+#else
+#define CONFIG_ETHPRIME                 "FEC"
+#endif
+#define CONFIG_FEC_MXC_PHYADDR          1
+
+#define CONFIG_PHY_ATHEROS
+
+/* ENET1 */
+#define IMX_FEC_BASE			ENET_IPS_BASE_ADDR
+
+/* #define CONFIG_SPLASH_SCREEN*/
+/* #define CONFIG_MXC_EPDC*/
+
+#include "mx7d_val.h"
+
+#endif
diff --git a/include/configs/mx7d_19x19_ddr3_val.h b/include/configs/mx7d_19x19_ddr3_val.h
new file mode 100644
index 00000000000..7254a172a2e
--- /dev/null
+++ b/include/configs/mx7d_19x19_ddr3_val.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX7D 19x19 DDR3 ARM2 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX7D_19X19_DDR3_VAL_CONFIG_H
+#define __MX7D_19X19_DDR3_VAL_CONFIG_H
+
+#define CONFIG_SYS_FSL_USDHC_NUM    3
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+
+#define PHYS_SDRAM_SIZE			SZ_1G
+
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#ifdef CONFIG_DM_ETH
+#define CONFIG_ETHPRIME                 "eth0"
+#else
+#define CONFIG_ETHPRIME                 "FEC"
+#endif
+#define CONFIG_FEC_MXC_PHYADDR          0
+
+#define CONFIG_PHY_ATHEROS
+
+/* ENET2 */
+#define IMX_FEC_BASE			ENET2_IPS_BASE_ADDR
+
+#define CONFIG_FEC_MXC_MDIO_BASE	ENET_IPS_BASE_ADDR
+
+#include "mx7d_val.h"
+
+#endif
diff --git a/include/configs/mx7d_19x19_lpddr3_val.h b/include/configs/mx7d_19x19_lpddr3_val.h
new file mode 100644
index 00000000000..23a0462d91d
--- /dev/null
+++ b/include/configs/mx7d_19x19_lpddr3_val.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX7D 19x19 LPDDR3 ARM2 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX7D_19X19_LPDDR3_VAL_CONFIG_H
+#define __MX7D_19X19_LPDDR3_VAL_CONFIG_H
+
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#define CONFIG_SYS_MMC_ENV_DEV		0	/* USDHC1 */
+#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC1 */
+
+#ifdef CONFIG_TARGET_MX7D_19X19_LPDDR2_VAL
+#define PHYS_SDRAM_SIZE			SZ_512M
+#else
+#define PHYS_SDRAM_SIZE			SZ_2G
+#endif
+
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE             RGMII
+#ifdef CONFIG_DM_ETH
+#define CONFIG_ETHPRIME                 "eth0"
+#else
+#define CONFIG_ETHPRIME                 "FEC"
+#endif
+#define CONFIG_FEC_MXC_PHYADDR          0
+
+#define CONFIG_PHY_ATHEROS
+
+/* ENET2 */
+#define IMX_FEC_BASE			ENET2_IPS_BASE_ADDR
+
+#define CONFIG_FEC_MXC_MDIO_BASE	ENET_IPS_BASE_ADDR
+
+/* QSPI conflict with EIMNOR */
+/* FEC0 conflict with EIMNOR */
+/* ECSPI conflict with UART */
+#ifdef CONFIG_MTD_NOR_FLASH
+#undef CONFIG_FEC_MXC
+#endif
+
+#include "mx7d_val.h"
+
+#endif
diff --git a/include/configs/mx7d_val.h b/include/configs/mx7d_val.h
new file mode 100644
index 00000000000..aca47b83a86
--- /dev/null
+++ b/include/configs/mx7d_val.h
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX7D ARM2 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX7D_VAL_CONFIG_H
+#define __MX7D_VAL_CONFIG_H
+
+#include "mx7_common.h"
+#include "imx_env.h"
+
+#define CONFIG_MXC_UART_BASE		UART1_IPS_BASE_ADDR
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+
+#define CONFIG_SYS_AUXCORE_BOOTDATA 0x68000000 /* Set to QSPI1 B flash at default */
+#define SF_QSPI1_B_CS_NUM 2
+#define SF_QSPI1_B_BUS_NUM 0
+
+#ifdef CONFIG_IMX_BOOTAUX
+
+#define UPDATE_M4_ENV \
+	"m4image=m4_qspi.bin\0" \
+	"m4_qspi_cs="__stringify(SF_QSPI1_B_CS_NUM)"\0" \
+	"m4_qspi_bus="__stringify(SF_QSPI1_B_BUS_NUM)"\0" \
+	"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
+	"update_m4_from_sd=" \
+		"if sf probe ${m4_qspi_bus}:${m4_qspi_cs}; then " \
+			"if run loadm4image; then " \
+				"setexpr fw_sz ${filesize} + 0xffff; " \
+				"setexpr fw_sz ${fw_sz} / 0x10000; "	\
+				"setexpr fw_sz ${fw_sz} * 0x10000; "	\
+				"sf erase 0x0 ${fw_sz}; " \
+				"sf write ${loadaddr} 0x0 ${filesize}; " \
+			"fi; " \
+		"fi\0" \
+	"m4boot=sf probe ${m4_qspi_bus}:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
+#else
+#define UPDATE_M4_ENV ""
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs)"
+#else
+#define MFG_NAND_PARTITION ""
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x86800000\0" \
+	"initrd_high=0xffffffff\0" \
+	"emmc_dev=2\0"\
+	"sd_dev=0\0" \
+	"mtdparts=" MFG_NAND_PARTITION \
+	"\0"\
+
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	"panel=MCIMX28LCD\0" \
+	"fdt_addr=0x83000000\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"console=ttymxc0\0" \
+	"bootargs=console=ttymxc0,115200 ubi.mtd=nandrootfs "  \
+		"root=ubi0:nandrootfs rootfstype=ubifs "		     \
+		MFG_NAND_PARTITION \
+		"\0" \
+	"bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\
+		"nand read ${fdt_addr} 0x5000000 0x100000;"\
+		"bootz ${loadaddr} - ${fdt_addr}\0"
+
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	UPDATE_M4_ENV \
+	"epdc_waveform=epdc_splash.bin\0" \
+	"panel=MCIMX28LCD\0" \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x83000000\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#endif
+
+/* Physical Memory Map */
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#ifdef CONFIG_MTD_NOR_FLASH
+#define CONFIG_SYS_FLASH_BASE           WEIM_ARB_BASE_ADDR
+#define CONFIG_SYS_FLASH_SECT_SIZE	(256 * 1024)
+#define CONFIG_SYS_MAX_FLASH_BANKS 1    /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT  512  /* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_CFI            /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER         /* Use drivers/cfi_flash.c */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_PROTECTION
+#endif
+
+#ifdef CONFIG_NAND_MXS
+
+/* NAND stuff */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#endif
+
+#ifdef CONFIG_VIDEO
+#define	CONFIG_VIDEO_MXS
+#define	CONFIG_VIDEO_LOGO
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_VIDEO_SKIP
+#endif
+
+#if defined(CONFIG_MXC_EPDC)
+/*
+ * Framebuffer and LCD
+ */
+
+#undef LCD_TEST_PATTERN
+/* #define CONFIG_SPLASH_IS_IN_MMC			1 */
+#define LCD_BPP					LCD_MONOCHROME
+/* #define CONFIG_SPLASH_SCREEN_ALIGN		1 */
+
+#define CONFIG_WAVEFORM_BUF_SIZE		0x400000
+#endif
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index d5b38fd91dd..386758182d8 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
  *
  * Configuration settings for the Freescale i.MX7D SABRESD board.
  */
@@ -9,6 +10,7 @@
 #define __MX7D_SABRESD_CONFIG_H
 
 #include "mx7_common.h"
+#include "imx_env.h"
 
 #define PHYS_SDRAM_SIZE			SZ_1G
 
@@ -17,10 +19,12 @@
 /* MMC Config*/
 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
 
+/* Default ETH port */
+#define CONFIG_ETHPRIME                 "eth0"
+
 #ifdef CONFIG_IMX_BOOTAUX
-/* Set to QSPI1 A flash at default */
-#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000
 
+#ifdef CONFIG_FSL_QSPI
 #define UPDATE_M4_ENV \
 	"m4image=m4_qspi.bin\0" \
 	"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
@@ -30,26 +34,39 @@
 				"setexpr fw_sz ${filesize} + 0xffff; " \
 				"setexpr fw_sz ${fw_sz} / 0x10000; "	\
 				"setexpr fw_sz ${fw_sz} * 0x10000; "	\
-				"sf erase 0x0 ${fw_sz}; " \
-				"sf write ${loadaddr} 0x0 ${filesize}; " \
+				"sf erase 0x100000 ${fw_sz}; " \
+				"sf write ${loadaddr} 0x100000 ${filesize}; " \
 			"fi; " \
 		"fi\0" \
 	"m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
 #else
+#define UPDATE_M4_ENV \
+	"m4image=m4_qspi.bin\0" \
+	"loadm4image=fatload mmc ${mmcdev}:${mmcpart} "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)" ${m4image}\0" \
+	"m4boot=run loadm4image; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
+#endif
+#else
 #define UPDATE_M4_ENV ""
 #endif
 
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs)"
+#else
+#define MFG_NAND_PARTITION ""
+#endif
+
+#define CONFIG_CMD_READ
+#define CONFIG_SERIAL_TAG
+#define CONFIG_FASTBOOT_USB_DEV 0
+
 #define CONFIG_MFG_ENV_SETTINGS \
-	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
-		"rdinit=/linuxrc " \
-		"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
-		"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
-		"g_mass_storage.iSerialNumber=\"\" "\
-		"clk_ignore_unused "\
-		"\0" \
-	"initrd_addr=0x83800000\0" \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
+	"initrd_addr=0x86800000\0" \
 	"initrd_high=0xffffffff\0" \
-	"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
+	"emmc_dev=2\0"\
+	"sd_dev=0\0" \
+	"mtdparts=" MFG_NAND_PARTITION \
+	"\0"\
 
 #define CONFIG_DFU_ENV_SETTINGS \
 	"dfu_alt_info=image raw 0 0x800000;"\
@@ -57,33 +74,113 @@
 		"bootimg part 0 1;"\
 		"rootfs part 0 2\0" \
 
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	TEE_ENV \
+	"fdt_addr=0x83000000\0" \
+	"tee_addr=0x84000000\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"console=ttymxc0\0" \
+	"bootargs=console=ttymxc0,115200 ubi.mtd=nandrootfs "  \
+		"root=ubi0:nandrootfs rootfstype=ubifs "		     \
+		MFG_NAND_PARTITION \
+		"\0" \
+	"bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\
+		"nand read ${fdt_addr} 0x5000000 0x100000;"\
+		"if test ${tee} = yes; then " \
+			"nand read ${tee_addr} 0x6000000 0x400000;"\
+			"bootm ${tee_addr} - ${fdt_addr};" \
+		"else " \
+			"bootz ${loadaddr} - ${fdt_addr};" \
+		"fi\0"
+
+#else
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	UPDATE_M4_ENV \
 	CONFIG_MFG_ENV_SETTINGS \
+	TEE_ENV \
 	CONFIG_DFU_ENV_SETTINGS \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
 	"console=ttymxc0\0" \
 	"fdt_high=0xffffffff\0" \
-	"finduuid=part uuid mmc 0:1 uuid\0" \
 	"initrd_high=0xffffffff\0" \
-	"fdtfile=imx7d-sdb.dtb\0" \
+	"fdt_file=undefined\0" \
 	"fdt_addr=0x83000000\0" \
-	"fdt_addr_r=0x83000000\0" \
-	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-	"pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-	"ramdisk_addr_r=0x83100000\0" \
-	"ramdiskaddr=0x83100000\0" \
-	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-	"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
-	BOOTENV
-
-#define BOOT_TARGET_DEVICES(func) \
-	func(MMC, mmc, 0) \
-	func(DHCP, dhcp, na) \
-	func(PXE, pxe, na)
-
-#include <config_distro_bootcmd.h>
+	"tee_addr=0x84000000\0" \
+	"tee_file=uTee-7dsdb\0" \
+	"boot_fdt=try\0" \
+	"ip_dyn=yes\0" \
+	"splashimage=0x8c000000\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${tee} = yes; then " \
+			"run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if run loadfdt; then " \
+					"bootz ${loadaddr} - ${fdt_addr}; " \
+				"else " \
+					"if test ${boot_fdt} = try; then " \
+						"bootz; " \
+					"else " \
+						"echo WARN: Cannot load the DT; " \
+					"fi; " \
+				"fi; " \
+			"else " \
+				"bootz; " \
+			"fi; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+		"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${tee} = yes; then " \
+			"${get_cmd} ${tee_addr} ${tee_file}; " \
+			"${get_cmd} ${fdt_addr} ${fdt_file}; " \
+			"bootm ${tee_addr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+					"bootz ${loadaddr} - ${fdt_addr}; " \
+				"else " \
+					"if test ${boot_fdt} = try; then " \
+						"bootz; " \
+					"else " \
+						"echo WARN: Cannot load the DT; " \
+					"fi; " \
+				"fi; " \
+			"else " \
+				"bootz; " \
+			"fi; " \
+		"fi;\0" \
+		"findfdt="\
+			"if test $fdt_file = undefined; then " \
+				"setenv fdt_file imx7d-sdb.dtb; " \
+			"fi;\0" \
+
+#endif
 
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
@@ -99,14 +196,22 @@
 
 /* environment organization */
 
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60100000 /* Set to QSPI1 A flash, offset 1M */
+#else
+#define CONFIG_SYS_AUXCORE_BOOTDATA 0x7F8000 /* Set to TCML address */
+#endif
 /*
- * If want to use nand, define CONFIG_NAND_MXS and rework board
+ * If want to use nand, define CONFIG_CMD_NAND and rework board
  * to support nand, since emmc has pin conflicts with nand
  */
 #ifdef CONFIG_NAND_MXS
+
 /* NAND stuff */
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
 
 /* DMA stuff, needed for GPMI/MXS NAND support */
 #endif
@@ -117,13 +222,36 @@
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #endif
 
+/* MMC Config*/
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+#define CONFIG_SYS_MMC_ENV_DEV		0   /* USDHC1 */
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC1 */
+
 /* USB Configs */
 #define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
 
-#define CONFIG_USBD_HS
-
 #ifdef CONFIG_DM_VIDEO
-#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_VIDEO_LINK
+#endif
+
+/*
+ * SPLASH SCREEN Configs
+ */
+#if defined(CONFIG_MXC_EPDC)
+/*
+ * Framebuffer and LCD
+ */
+
+#undef LCD_TEST_PATTERN
+/* #define CONFIG_SPLASH_IS_IN_MMC			1 */
+#define LCD_BPP					LCD_MONOCHROME
+/* #define CONFIG_SPLASH_SCREEN_ALIGN		1 */
+
+#define CONFIG_WAVEFORM_BUF_SIZE		0x400000
+#endif
+
+#if defined(CONFIG_MXC_EPDC) && defined(CONFIG_FSL_QSPI)
+#error "EPDC Pins conflicts QSPI, Either EPDC or QSPI can be enabled!"
 #endif
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
index 8f2cbc643ee..4d4d72fc533 100644
--- a/include/configs/mx7ulp_evk.h
+++ b/include/configs/mx7ulp_evk.h
@@ -10,10 +10,13 @@
 
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
+#include "imx_env.h"
 
 #define CONFIG_BOARD_POSTCLK_INIT
 #define CONFIG_SYS_BOOTM_LEN		0x1000000
 
+#define CONFIG_SERIAL_TAG
+
 #define CONFIG_MMCROOT                  "/dev/mmcblk0p2"  /* USDHC1 */
 
 /* Using ULP WDOG for reset */
@@ -35,16 +38,28 @@
 #define PHYS_SDRAM_SIZE			SZ_1G
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
 
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT  \
+	"initrd_addr=0x66800000\0" \
+	"initrd_high=0xffffffff\0" \
+	"emmc_dev=0\0" \
+	"sd_dev=0\0"
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	TEE_ENV \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
 	"console=ttyLP0\0" \
+	"splashimage=0x78000000\0" \
 	"fdt_high=0xffffffff\0" \
 	"initrd_high=0xffffffff\0" \
-	"fdt_file=imx7ulp-evk.dtb\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE ".dtb\0" \
 	"fdt_addr=0x63000000\0" \
+	"tee_addr=0x64000000\0" \
+	"tee_file=uTee-7ulp\0" \
 	"boot_fdt=try\0" \
-	"earlycon=lpuart32,0x402D0010\0" \
+	"earlycon=lpuart32,0x402D0000\0" \
 	"ip_dyn=yes\0" \
 	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=1\0" \
@@ -58,20 +73,25 @@
 		"source\0" \
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if run loadfdt; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
+		"if test ${tee} = yes; then " \
+			"run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if run loadfdt; then " \
+					"bootz ${loadaddr} - ${fdt_addr}; " \
 				"else " \
-					"echo WARN: Cannot load the DT; " \
+					"if test ${boot_fdt} = try; then " \
+						"bootz; " \
+					"else " \
+						"echo WARN: Cannot load the DT; " \
+					"fi; " \
 				"fi; " \
+			"else " \
+				"bootz; " \
 			"fi; " \
-		"else " \
-			"bootz; " \
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} " \
 		"root=/dev/nfs " \
@@ -85,18 +105,24 @@
 		"fi; " \
 		"usb start; "\
 		"${get_cmd} ${image}; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"bootz ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"if test ${boot_fdt} = try; then " \
-					"bootz; " \
+		"if test ${tee} = yes; then " \
+			"${get_cmd} ${tee_addr} ${tee_file}; " \
+			"${get_cmd} ${fdt_addr} ${fdt_file}; " \
+			"bootm ${tee_addr} - ${fdt_addr}; " \
+		"else " \
+			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+				"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+					"bootz ${loadaddr} - ${fdt_addr}; " \
 				"else " \
-					"echo WARN: Cannot load the DT; " \
+					"if test ${boot_fdt} = try; then " \
+						"bootz; " \
+					"else " \
+						"echo WARN: Cannot load the DT; " \
+					"fi; " \
 				"fi; " \
+			"else " \
+				"bootz; " \
 			"fi; " \
-		"else " \
-			"bootz; " \
 		"fi;\0" \
 
 #define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
@@ -107,4 +133,13 @@
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
+/* USB Configs */
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+
+#ifdef CONFIG_IMX_OPTEE
+#define TEE_ENV "tee=yes\0"
+#else
+#define TEE_ENV "tee=no\0"
+#endif
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/mx7ulp_val.h b/include/configs/mx7ulp_val.h
new file mode 100644
index 00000000000..33b88cee101
--- /dev/null
+++ b/include/configs/mx7ulp_val.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * Configuration settings for the Freescale i.MX7ULP Validation board.
+ */
+
+#ifndef __MX7ULP_VAL_CONFIG_H
+#define __MX7ULP_VAL_CONFIG_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+#include "imx_env.h"
+
+#define CONFIG_BOARD_POSTCLK_INIT
+#define CONFIG_SYS_BOOTM_LEN		0x1000000
+
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+
+/* Using ULP WDOG for reset */
+#define WDOG_BASE_ADDR		 WDG1_RBASE
+
+#define CONFIG_SERIAL_TAG
+
+#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
+
+/* UART */
+#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL
+#define LPUART_BASE     LPUART6_RBASE
+#else
+#define LPUART_BASE     LPUART4_RBASE
+#endif
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE		512
+
+/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		256
+
+/* Physical Memory Map */
+
+#define PHYS_SDRAM			0x60000000ul
+#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL
+#define PHYS_SDRAM_SIZE			    SZ_1G   /*LPDDR2 1G*/
+#else
+#define PHYS_SDRAM_SIZE			    SZ_512M
+#endif
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS_DEFAULT  \
+	"initrd_addr=0x66800000\0" \
+	"initrd_high=0xffffffff\0" \
+	"sd_dev=1\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttyLP0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x63000000\0" \
+	"boot_fdt=try\0" \
+	"earlycon=lpuart32,0x402D0000\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=1\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	SZ_256K
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* USB Configs */
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+
+#endif	/* __CONFIG_H */
diff --git a/include/dm/device.h b/include/dm/device.h
index cb52a0997c8..398c06da39e 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -67,6 +67,9 @@ struct driver_info;
 /* Driver plat has been read. Cleared when the device is removed */
 #define DM_FLAG_PLATDATA_VALID		(1 << 12)
 
+/* DM should ignore the assign default clocks for this driver */
+#define DM_FLAG_IGNORE_DEFAULT_CLKS		(1 << 13)
+
 /*
  * Device is removed without switching off its power domain. This might
  * be required, i. e. for serial console (debug) output when booting OS.
@@ -367,6 +370,7 @@ struct driver {
 	int (*child_post_bind)(struct udevice *dev);
 	int (*child_pre_probe)(struct udevice *dev);
 	int (*child_post_remove)(struct udevice *dev);
+	int (*handle_interrupts)(struct udevice *dev);
 	int priv_auto;
 	int plat_auto;
 	int per_child_auto;
diff --git a/include/dsi_host.h b/include/dsi_host.h
index 83f8839db68..5873ab698d9 100644
--- a/include/dsi_host.h
+++ b/include/dsi_host.h
@@ -70,4 +70,12 @@ int dsi_host_init(struct udevice *dev,
  */
 int dsi_host_enable(struct udevice *dev);
 
+/**
+ * dsi_host_disable
+ *
+ * @dev:	dsi host device
+ * @return 0 if OK, -ve on error
+ */
+int dsi_host_disable(struct udevice *dev);
+
 #endif
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index 29050337d9d..2a25fdb2d9b 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -269,6 +269,15 @@
 #define IMX6QDL_CLK_PRG0_APB			256
 #define IMX6QDL_CLK_PRG1_APB			257
 #define IMX6QDL_CLK_PRE_AXI			258
-#define IMX6QDL_CLK_END				259
+#define IMX6QDL_CLK_MLB_SEL			259
+#define IMX6QDL_CLK_MLB_PODF			260
+#define IMX6QDL_CLK_AXI_ALT_SEL			261
+#define IMX6QDL_CLK_LDB_DI0_DIV_7		262
+#define IMX6QDL_CLK_LDB_DI1_DIV_7		263
+#define IMX6QDL_CLK_LDB_DI0_DIV_SEL		264
+#define IMX6QDL_CLK_LDB_DI1_DIV_SEL		265
+#define IMX6QDL_CLK_DCIC1			266
+#define IMX6QDL_CLK_DCIC2			267
+#define IMX6QDL_CLK_END				268
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h
index 39c25671d67..22493cf47aa 100644
--- a/include/dt-bindings/clock/imx6sll-clock.h
+++ b/include/dt-bindings/clock/imx6sll-clock.h
@@ -198,7 +198,8 @@
 #define IMX6SLL_CLK_EXTERN_AUDIO_PRED   170
 #define IMX6SLL_CLK_EXTERN_AUDIO_PODF   171
 #define IMX6SLL_CLK_EXTERN_AUDIO        172
+#define IMX6SLL_CLK_GPT_3M		173
 
-#define IMX6SLL_CLK_END			173
+#define IMX6SLL_CLK_END			174
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
index b2325d3e236..89eadb96da2 100644
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -168,7 +169,7 @@
 #define IMX7D_SPDIF_ROOT_SRC		155
 #define IMX7D_SPDIF_ROOT_CG		156
 #define IMX7D_SPDIF_ROOT_DIV		157
-#define IMX7D_ENET1_REF_ROOT_CLK	158
+#define IMX7D_ENET1_IPG_ROOT_CLK        158
 #define IMX7D_ENET1_REF_ROOT_SRC	159
 #define IMX7D_ENET1_REF_ROOT_CG		160
 #define IMX7D_ENET1_REF_ROOT_DIV	161
@@ -176,7 +177,7 @@
 #define IMX7D_ENET1_TIME_ROOT_SRC	163
 #define IMX7D_ENET1_TIME_ROOT_CG	164
 #define IMX7D_ENET1_TIME_ROOT_DIV	165
-#define IMX7D_ENET2_REF_ROOT_CLK	166
+#define IMX7D_ENET2_IPG_ROOT_CLK        166
 #define IMX7D_ENET2_REF_ROOT_SRC	167
 #define IMX7D_ENET2_REF_ROOT_CG		168
 #define IMX7D_ENET2_REF_ROOT_DIV	169
@@ -455,5 +456,8 @@
 #define IMX7D_SNVS_CLK			442
 #define IMX7D_CAAM_CLK			443
 #define IMX7D_KPP_ROOT_CLK		444
-#define IMX7D_CLK_END			445
+#define IMX7D_PXP_IPG_CLK		445
+#define IMX7D_PXP_AXI_CLK		446
+#define IMX7D_CLK_END			447
+
 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h
index e8d68fbb6e3..3784cbbc75f 100644
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ b/include/dt-bindings/clock/imx8mp-clock.h
@@ -322,68 +322,155 @@
 #define IMX8MP_CLK_HSIO_AXI			311
 #define IMX8MP_CLK_MEDIA_ISP			312
 
-#define IMX8MP_CLK_END				313
+#define IMX8MP_CLK_MEDIA_DISP2_PIX		313
+#define IMX8MP_CLK_MEDIA_LDB_ROOT		314
+#define IMX8MP_CLK_AUDIO_AHB_ROOT		315
+#define IMX8MP_CLK_AUDIO_AXI_ROOT		316
+#define IMX8MP_CLK_SAI1_ROOT			317
+#define IMX8MP_CLK_SAI2_ROOT			318
+#define IMX8MP_CLK_SAI3_ROOT			319
+#define IMX8MP_CLK_SAI5_ROOT			320
+#define IMX8MP_CLK_SAI6_ROOT			321
+#define IMX8MP_CLK_SAI7_ROOT			322
+#define IMX8MP_CLK_PDM_ROOT			323
 
-#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG		0
-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1		1
-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2		2
-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3		3
-#define IMX8MP_CLK_AUDIOMIX_SAI2_IPG		4
-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1		5
-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2		6
-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3		7
-#define IMX8MP_CLK_AUDIOMIX_SAI3_IPG		8
-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1		9
-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2		10
-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3		11
-#define IMX8MP_CLK_AUDIOMIX_SAI5_IPG		12
-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1		13
-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2		14
-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3		15
-#define IMX8MP_CLK_AUDIOMIX_SAI6_IPG		16
-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1		17
-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2		18
-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3		19
-#define IMX8MP_CLK_AUDIOMIX_SAI7_IPG		20
-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1		21
-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2		22
-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3		23
-#define IMX8MP_CLK_AUDIOMIX_ASRC_IPG		24
-#define IMX8MP_CLK_AUDIOMIX_PDM_IPG		25
-#define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT		26
-#define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT		27
-#define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT		28
-#define IMX8MP_CLK_AUDIOMIX_DSP_ROOT		29
-#define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT		30
-#define IMX8MP_CLK_AUDIOMIX_EARC_IPG		31
-#define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG		32
-#define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG		33
-#define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT		34
-#define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT		35
-#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT		36
-#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT		37
-#define IMX8MP_CLK_AUDIOMIX_EARC_PHY		38
-#define IMX8MP_CLK_AUDIOMIX_PDM_ROOT		39
-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL	40
-#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL	41
-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL	42
-#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL	43
-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL	44
-#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL	45
-#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL	46
-#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL	47
-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL	48
-#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL	49
-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL	50
-#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL	51
-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL	52
-#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL	53
-#define IMX8MP_CLK_AUDIOMIX_PDM_SEL		54
-#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL	55
-#define IMX8MP_CLK_AUDIOMIX_SAI_PLL		56
-#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS	57
-#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT		58
+#define IMX8MP_SAI1_MCLK			324
+#define IMX8MP_SAI2_MCLK			325
+#define IMX8MP_SAI3_MCLK			326
+#define IMX8MP_SAI4_MCLK			327
+#define IMX8MP_SAI5_MCLK			328
+#define IMX8MP_SAI6_MCLK			329
+#define IMX8MP_SAI7_MCLK			330
 
-#define IMX8MP_CLK_AUDIOMIX_END			59
+#define IMX8MP_CLK_END				331
+
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_IPG		0
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK1		1
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK2		2
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK3		3
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_IPG		4
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK1		5
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK2		6
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK3		7
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG		8
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1		9
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK2		10
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK3		11
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_IPG		12
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1		13
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK2		14
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK3		15
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_IPG		16
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK1		17
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK2		18
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK3		19
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_IPG		20
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK1		21
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK2		22
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK3		23
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_ASRC_IPG		24
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_IPG		25
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT		27
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SPBA2_ROOT		28
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_DSP_ROOT		29
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_DSPDBG_ROOT		30
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_EARC_IPG		31
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_OCRAMA_IPG		32
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_AUD2HTX_IPG		33
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_EDMA_ROOT		34
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_AUDPLL_ROOT		35
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_MU2_ROOT		36
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_MU3_ROOT		37
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_EARC_PHY		38
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_ROOT		39
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK1_SEL	40
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK2_SEL	41
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK1_SEL	42
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK2_SEL	43
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1_SEL	44
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK2_SEL	45
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI4_MCLK1_SEL	46
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI4_MCLK2_SEL	47
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1_SEL	48
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK2_SEL	49
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK1_SEL	50
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK2_SEL	51
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK1_SEL	52
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK2_SEL	53
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_SEL		54
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_REF_SEL	55
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL		56
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_BYPASS	57
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_OUT		58
+
+#define IMX8MP_CLK_AUDIO_BLK_CTRL_END			59
+
+#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_APB_CLK		0
+#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_B_CLK		1
+#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_REF266M_CLK	2
+#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_XTAL24M_CLK	3
+#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_XTAL32K_CLK	4
+#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_TX_PIX_CLK	5
+#define IMX8MP_CLK_HDMI_BLK_CTRL_IRQS_STEER_CLK		6
+#define IMX8MP_CLK_HDMI_BLK_CTRL_NOC_HDMI_CLK		7
+#define IMX8MP_CLK_HDMI_BLK_CTRL_NOC_HDCP_CLK		8
+#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_APB_CLK		9
+#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_B_CLK		10
+#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_PDI_CLK		11
+#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_PIX_CLK		12
+#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_SPU_CLK		13
+#define IMX8MP_CLK_HDMI_BLK_CTRL_FDCC_REF_CLK		14
+#define IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_APB_CLK	15
+#define IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_B_CLK		16
+#define IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_CEA_CLK	17
+#define IMX8MP_CLK_HDMI_BLK_CTRL_VSFD_CEA_CLK		18
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_HPI_CLK		19
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_APB_CLK		20
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_CEC_CLK		21
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_ESM_CLK		22
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_GPA_CLK		23
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PIXEL_CLK		24
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_SFR_CLK		25
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_SKP_CLK		26
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PREP_CLK		27
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PHY_APB_CLK		28
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PHY_INT_CLK		29
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_SEC_MEM_CLK		30
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_TRNG_SKP_CLK	31
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_VID_LINK_PIX_CLK	32
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_TRNG_APB_CLK	33
+#define IMX8MP_CLK_HDMI_BLK_CTRL_HTXPHY_CLK_SEL		34
+#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_CLK_SEL		35
+#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PIPE_CLK_SEL	36
+
+#define IMX8MP_CLK_HDMI_BLK_CTRL_END			37
+
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_PCLK		0
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_CLKREF	1
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI_PCLK		2
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI_ACLK		3
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_PIXEL		4
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_APB		5
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISI_PROC		6
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISI_APB		7
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_BUS_BLK		8
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI2_PCLK	9
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI2_ACLK	10
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_PIXEL		11
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_APB		12
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_COR		13
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_AXI		14
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_AHB		15
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_COR		16
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_AXI		17
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_AHB		18
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_COR		19
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_AXI		20
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_AHB		21
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI2		22
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_AXI		23
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_AXI		24
+
+#define IMX8MP_CLK_MEDIA_BLK_CTRL_END			25
 
 #endif
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
index 9b8045d75b8..4724f0978a3 100644
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -431,6 +431,8 @@
 
 #define IMX8MQ_CLK_A53_CORE			289
 
-#define IMX8MQ_CLK_END				290
+#define IMX8MQ_CLK_PHY_27MHZ		290
+
+#define IMX8MQ_CLK_END				291
 
 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
diff --git a/include/dt-bindings/clock/imx8qm-clock.h b/include/dt-bindings/clock/imx8qm-clock.h
index 58de976e638..3d3afe0e2c4 100644
--- a/include/dt-bindings/clock/imx8qm-clock.h
+++ b/include/dt-bindings/clock/imx8qm-clock.h
@@ -841,6 +841,16 @@
 #define IMX8QM_AUD_DSP_CORE_CLK				794
 #define IMX8QM_AUD_OCRAM_IPG				795
 
-#define IMX8QM_CLK_END					796
+/* MIPI DSI */
+#define IMX8QM_MIPI0_DSI_PHY_DIV			796
+#define IMX8QM_MIPI0_DSI_PHY_CLK			797
+#define IMX8QM_MIPI1_DSI_PHY_DIV			798
+#define IMX8QM_MIPI1_DSI_PHY_CLK			799
+
+#define IMX8QM_SDHC0_AHB_CLK				800
+#define IMX8QM_SDHC1_AHB_CLK				801
+#define IMX8QM_SDHC2_AHB_CLK				802
+
+#define IMX8QM_CLK_END					813
 
 #endif /* __DT_BINDINGS_CLOCK_IMX8QM_H */
diff --git a/include/dt-bindings/clock/imx8qxp-clock.h b/include/dt-bindings/clock/imx8qxp-clock.h
index d0334ea3988..aa95ed33413 100644
--- a/include/dt-bindings/clock/imx8qxp-clock.h
+++ b/include/dt-bindings/clock/imx8qxp-clock.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
  */
 
 #ifndef __DT_BINDINGS_CLOCK_IMX8QXP_H
@@ -298,11 +298,8 @@
 #define IMX8QXP_MIPI0_I2C1_DIV					274
 #define IMX8QXP_MIPI0_I2C0_CLK					275
 #define IMX8QXP_MIPI0_I2C1_CLK					276
-#define IMX8QXP_MIPI0_I2C0_IPG_S_CLK				277
 #define IMX8QXP_MIPI0_I2C0_IPG_CLK				278
-#define IMX8QXP_MIPI0_I2C1_IPG_S_CLK				279
 #define IMX8QXP_MIPI0_I2C1_IPG_CLK				280
-#define IMX8QXP_MIPI0_PWM_IPG_S_CLK				281
 #define IMX8QXP_MIPI0_PWM_IPG_CLK				282
 #define IMX8QXP_MIPI0_PWM_32K_CLK				283
 #define IMX8QXP_MIPI0_GPIO_IPG_CLK				284
@@ -499,11 +496,8 @@
 #define IMX8QXP_MIPI1_I2C1_DIV					461
 #define IMX8QXP_MIPI1_I2C0_CLK					462
 #define IMX8QXP_MIPI1_I2C1_CLK					463
-#define IMX8QXP_MIPI1_I2C0_IPG_S_CLK				464
 #define IMX8QXP_MIPI1_I2C0_IPG_CLK				465
-#define IMX8QXP_MIPI1_I2C1_IPG_S_CLK				466
 #define IMX8QXP_MIPI1_I2C1_IPG_CLK				467
-#define IMX8QXP_MIPI1_PWM_IPG_S_CLK				468
 #define IMX8QXP_MIPI1_PWM_IPG_CLK				469
 #define IMX8QXP_MIPI1_PWM_32K_CLK				470
 #define IMX8QXP_MIPI1_GPIO_IPG_CLK				471
@@ -579,5 +573,28 @@
 #define IMX8QXP_LSIO_MU5A_IPG_S_CLK		528
 #define IMX8QXP_LSIO_MU5A_IPG_CLK		529
 
-#define IMX8QXP_CLK_END						530
+
+/* LCD part2 */
+#define IMX8QXP_LCD_PXL_BYPASS_DIV			530
+#define IMX8QXP_LCD_PXL_SEL				531
+#define IMX8QXP_LCD_PXL_DIV				532
+#define IMX8QXP_LCD_PXL_CLK				533
+#define IMX8QXP_ELCDIF_PLL_DIV				534
+#define IMX8QXP_ELCDIF_PLL				535
+#define IMX8QXP_LCD_SEL					536
+
+#define IMX8DXL_EQOS_MEM_CLK				537
+#define IMX8DXL_EQOS_ACLK				538
+#define IMX8DXL_EQOS_CSR_CLK			539
+#define IMX8DXL_EQOS_CLK				540
+#define IMX8DXL_EQOS_PTP_CLK_S			541
+#define IMX8DXL_EQOS_PTP_CLK			542
+
+#define IMX8DXL_USB2_PHY2_IPG_CLK		543
+
+#define IMX8QXP_SDHC0_AHB_CLK			544
+#define IMX8QXP_SDHC1_AHB_CLK			545
+#define IMX8QXP_SDHC2_AHB_CLK			546
+
+#define IMX8DXL_CLK_END				547
 #endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */
diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h
index 49166a18300..278033de146 100644
--- a/include/dt-bindings/clock/imx8ulp-clock.h
+++ b/include/dt-bindings/clock/imx8ulp-clock.h
@@ -11,6 +11,8 @@
 #define IMX8ULP_CLK_FROSC			2
 #define IMX8ULP_CLK_LPOSC			3
 #define IMX8ULP_CLK_SOSC			4
+
+/* CGC1 */
 #define IMX8ULP_CLK_SPLL2			5
 #define IMX8ULP_CLK_SPLL3			6
 #define IMX8ULP_CLK_A35_SEL			7
@@ -57,14 +59,15 @@
 #define IMX8ULP_CLK_FROSC_DIV1_GATE		48
 #define IMX8ULP_CLK_FROSC_DIV2_GATE		49
 #define IMX8ULP_CLK_FROSC_DIV3_GATE		50
-#define IMX8ULP_CLK_ENETSTAMP_SEL		51
-#define IMX8ULP_CLK_SAI4_SEL			52
-#define IMX8ULP_CLK_SAI5_SEL			53
-#define IMX8ULP_CLK_AUD_CLK1			54
-#define IMX8ULP_CLK_ARM				55
+#define IMX8ULP_CLK_SAI4_SEL			51
+#define IMX8ULP_CLK_SAI5_SEL			52
+#define IMX8ULP_CLK_AUD_CLK1			53
+#define IMX8ULP_CLK_ARM				54
+#define IMX8ULP_CLK_ENET_TS_SEL			55
 
 #define IMX8ULP_CLK_CGC1_END			56
 
+/* CGC2 */
 #define IMX8ULP_CLK_PLL4_PRE_SEL	0
 #define IMX8ULP_CLK_PLL4		1
 #define IMX8ULP_CLK_PLL4_VCODIV		2
@@ -110,8 +113,12 @@
 #define IMX8ULP_CLK_SAI6_SEL		42
 #define IMX8ULP_CLK_SAI7_SEL		43
 #define IMX8ULP_CLK_SPDIF_SEL		44
+#define IMX8ULP_CLK_HIFI_SEL		45
+#define IMX8ULP_CLK_HIFI_DIVCORE	46
+#define IMX8ULP_CLK_HIFI_DIVPLAT	47
+#define IMX8ULP_CLK_DSI_PHY_REF		48
 
-#define IMX8ULP_CLK_CGC2_END		45
+#define IMX8ULP_CLK_CGC2_END		49
 
 /* PCC3 */
 #define IMX8ULP_CLK_WDOG3		0
@@ -160,9 +167,13 @@
 #define IMX8ULP_CLK_DMA1_CH29		43
 #define IMX8ULP_CLK_DMA1_CH30		44
 #define IMX8ULP_CLK_DMA1_CH31		45
+#define IMX8ULP_CLK_CAAM		46
+#define IMX8ULP_CLK_MU3_A		47
+#define IMX8ULP_CLK_MU0_B		48
 
-#define IMX8ULP_CLK_PCC3_END		46
+#define IMX8ULP_CLK_PCC3_END		49
 
+/* PCC4 */
 #define IMX8ULP_CLK_FLEXSPI2		0
 #define IMX8ULP_CLK_TPM6		1
 #define IMX8ULP_CLK_TPM7		2
@@ -189,24 +200,25 @@
 
 #define IMX8ULP_CLK_PCC4_END		23
 
+/* PCC5 */
 #define IMX8ULP_CLK_TPM8		0
 #define IMX8ULP_CLK_SAI6		1
 #define IMX8ULP_CLK_SAI7		2
 #define IMX8ULP_CLK_SPDIF		3
-#define IMX8ULP_CLK_ISI		4
-#define IMX8ULP_CLK_CSI_REGS		5
+#define IMX8ULP_CLK_ISI			4
+#define IMX8ULP_CLK_CSI_REGS 		5
 #define IMX8ULP_CLK_PCTLD		6
-#define IMX8ULP_CLK_CSI		7
-#define IMX8ULP_CLK_DSI		8
+#define IMX8ULP_CLK_CSI			7
+#define IMX8ULP_CLK_DSI			8
 #define IMX8ULP_CLK_WDOG5		9
 #define IMX8ULP_CLK_EPDC		10
-#define IMX8ULP_CLK_PXP		11
+#define IMX8ULP_CLK_PXP			11
 #define IMX8ULP_CLK_SFA2		12
 #define IMX8ULP_CLK_GPU2D		13
 #define IMX8ULP_CLK_GPU3D		14
 #define IMX8ULP_CLK_DC_NANO		15
-#define IMX8ULP_CLK_CSI_CLK_UI		16
-#define IMX8ULP_CLK_CSI_CLK_ESC	17
+#define IMX8ULP_CLK_CSI_CLK_UI 		16
+#define IMX8ULP_CLK_CSI_CLK_ESC		17
 #define IMX8ULP_CLK_RGPIOD		18
 #define IMX8ULP_CLK_DMA2_MP		19
 #define IMX8ULP_CLK_DMA2_CH0		20
@@ -241,7 +253,11 @@
 #define IMX8ULP_CLK_DMA2_CH29		49
 #define IMX8ULP_CLK_DMA2_CH30		50
 #define IMX8ULP_CLK_DMA2_CH31		51
+#define IMX8ULP_CLK_MU2_B		52
+#define IMX8ULP_CLK_MU3_B		53
+#define IMX8ULP_CLK_AVD_SIM		54
+#define IMX8ULP_CLK_DSI_TX_ESC		55
 
-#define IMX8ULP_CLK_PCC5_END		52
+#define IMX8ULP_CLK_PCC5_END		56
 
 #endif
diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h
new file mode 100644
index 00000000000..4ea6864b418
--- /dev/null
+++ b/include/dt-bindings/clock/imx93-clock.h
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX93_CLK_H
+#define __DT_BINDINGS_CLOCK_IMX93_CLK_H
+
+#define IMX93_CLK_DUMMY			0
+#define IMX93_CLK_24M			1
+#define IMX93_CLK_EXT1			2
+#define IMX93_CLK_SYS_PLL_PFD0		3
+#define IMX93_CLK_SYS_PLL_PFD0_DIV2	4
+#define IMX93_CLK_SYS_PLL_PFD1		5
+#define IMX93_CLK_SYS_PLL_PFD1_DIV2	6
+#define IMX93_CLK_SYS_PLL_PFD2		7
+#define IMX93_CLK_SYS_PLL_PFD2_DIV2	8
+#define IMX93_CLK_AUDIO_PLL		9
+#define IMX93_CLK_VIDEO_PLL		10
+#define IMX93_CLK_A55_PERIPH		11
+#define IMX93_CLK_A55_MTR_BUS		12
+#define IMX93_CLK_A55			13
+#define IMX93_CLK_M33			14
+#define IMX93_CLK_BUS_WAKEUP		15
+#define IMX93_CLK_BUS_AON		16
+#define IMX93_CLK_WAKEUP_AXI		17
+#define IMX93_CLK_SWO_TRACE		18
+#define IMX93_CLK_M33_SYSTICK		19
+#define IMX93_CLK_FLEXIO1		20
+#define IMX93_CLK_FLEXIO2		21
+#define IMX93_CLK_LPIT1			22
+#define IMX93_CLK_LPIT2			23
+#define IMX93_CLK_LPTMR1		24
+#define IMX93_CLK_LPTMR2		25
+#define IMX93_CLK_TPM1			26
+#define IMX93_CLK_TPM2			27
+#define IMX93_CLK_TPM3			28
+#define IMX93_CLK_TPM4			29
+#define IMX93_CLK_TPM5			30
+#define IMX93_CLK_TPM6			31
+#define IMX93_CLK_FLEXSPI1		32
+#define IMX93_CLK_CAN1			33
+#define IMX93_CLK_CAN2			34
+#define IMX93_CLK_LPUART1		35
+#define IMX93_CLK_LPUART2		36
+#define IMX93_CLK_LPUART3		37
+#define IMX93_CLK_LPUART4		38
+#define IMX93_CLK_LPUART5		39
+#define IMX93_CLK_LPUART6		40
+#define IMX93_CLK_LPUART7		41
+#define IMX93_CLK_LPUART8		42
+#define IMX93_CLK_LPI2C1		43
+#define IMX93_CLK_LPI2C2		44
+#define IMX93_CLK_LPI2C3		45
+#define IMX93_CLK_LPI2C4		46
+#define IMX93_CLK_LPI2C5		47
+#define IMX93_CLK_LPI2C6		48
+#define IMX93_CLK_LPI2C7		49
+#define IMX93_CLK_LPI2C8		50
+#define IMX93_CLK_LPSPI1		51
+#define IMX93_CLK_LPSPI2		52
+#define IMX93_CLK_LPSPI3		53
+#define IMX93_CLK_LPSPI4		54
+#define IMX93_CLK_LPSPI5		55
+#define IMX93_CLK_LPSPI6		56
+#define IMX93_CLK_LPSPI7		57
+#define IMX93_CLK_LPSPI8		58
+#define IMX93_CLK_I3C1			59
+#define IMX93_CLK_I3C2			60
+#define IMX93_CLK_USDHC1		61
+#define IMX93_CLK_USDHC2		62
+#define IMX93_CLK_USDHC3		63
+#define IMX93_CLK_SAI1			64
+#define IMX93_CLK_SAI2			65
+#define IMX93_CLK_SAI3			66
+#define IMX93_CLK_CCM_CKO1		67
+#define IMX93_CLK_CCM_CKO2		68
+#define IMX93_CLK_CCM_CKO3		69
+#define IMX93_CLK_CCM_CKO4		70
+#define IMX93_CLK_HSIO			71
+#define IMX93_CLK_HSIO_USB_TEST_60M	72
+#define IMX93_CLK_HSIO_ACSCAN_80M	73
+#define IMX93_CLK_HSIO_ACSCAN_480M	74
+#define IMX93_CLK_ML_APB		75
+#define IMX93_CLK_ML			76
+#define IMX93_CLK_MEDIA_AXI		77
+#define IMX93_CLK_MEDIA_APB		78
+#define IMX93_CLK_MEDIA_LDB		79
+#define IMX93_CLK_MEDIA_DISP_PIX	80
+#define IMX93_CLK_CAM_PIX		81
+#define IMX93_CLK_MIPI_TEST_BYTE	82
+#define IMX93_CLK_MIPI_PHY_CFG		83
+#define IMX93_CLK_ADC			84
+#define IMX93_CLK_PDM			85
+#define IMX93_CLK_TSTMR1		86
+#define IMX93_CLK_TSTMR2		87
+#define IMX93_CLK_MQS1			88
+#define IMX93_CLK_MQS2			89
+#define IMX93_CLK_AUDIO_XCVR		90
+#define IMX93_CLK_SPDIF			91
+#define IMX93_CLK_ENET			92
+#define IMX93_CLK_ENET_TIMER1		93
+#define IMX93_CLK_ENET_TIMER2		94
+#define IMX93_CLK_ENET_REF		95
+#define IMX93_CLK_ENET_REF_PHY		96
+#define IMX93_CLK_I3C1_SLOW		97
+#define IMX93_CLK_I3C2_SLOW		98
+#define IMX93_CLK_USB_PHY_BURUNIN	99
+#define IMX93_CLK_PAL_CAME_SCAN		100
+#define IMX93_CLK_A55_GATE		101
+#define IMX93_CLK_CM33_GATE		102
+#define IMX93_CLK_ADC1_GATE		103
+#define IMX93_CLK_WDOG1_GATE		104
+#define IMX93_CLK_WDOG2_GATE		105
+#define IMX93_CLK_WDOG3_GATE		106
+#define IMX93_CLK_WDOG4_GATE		107
+#define IMX93_CLK_WDOG5_GATE		108
+#define IMX93_CLK_SEMA1_GATE		109
+#define IMX93_CLK_SEMA2_GATE		110
+#define IMX93_CLK_MU_A_GATE		111
+#define IMX93_CLK_MU_B_GATE		112
+#define IMX93_CLK_EDMA1_GATE		113
+#define IMX93_CLK_EDMA2_GATE		114
+#define IMX93_CLK_FLEXSPI1_GATE		115
+#define IMX93_CLK_GPIO1_GATE		116
+#define IMX93_CLK_GPIO2_GATE		117
+#define IMX93_CLK_GPIO3_GATE		118
+#define IMX93_CLK_GPIO4_GATE		119
+#define IMX93_CLK_FLEXIO1_GATE		120
+#define IMX93_CLK_FLEXIO2_GATE		121
+#define IMX93_CLK_LPIT1_GATE		122
+#define IMX93_CLK_LPIT2_GATE		123
+#define IMX93_CLK_LPTMR1_GATE		124
+#define IMX93_CLK_LPTMR2_GATE		125
+#define IMX93_CLK_TPM1_GATE		126
+#define IMX93_CLK_TPM2_GATE		127
+#define IMX93_CLK_TPM3_GATE		128
+#define IMX93_CLK_TPM4_GATE		129
+#define IMX93_CLK_TPM5_GATE		130
+#define IMX93_CLK_TPM6_GATE		131
+#define IMX93_CLK_CAN1_GATE		132
+#define IMX93_CLK_CAN2_GATE		133
+#define IMX93_CLK_LPUART1_GATE		134
+#define IMX93_CLK_LPUART2_GATE		135
+#define IMX93_CLK_LPUART3_GATE		136
+#define IMX93_CLK_LPUART4_GATE		137
+#define IMX93_CLK_LPUART5_GATE		138
+#define IMX93_CLK_LPUART6_GATE		139
+#define IMX93_CLK_LPUART7_GATE		140
+#define IMX93_CLK_LPUART8_GATE		141
+#define IMX93_CLK_LPI2C1_GATE		142
+#define IMX93_CLK_LPI2C2_GATE		143
+#define IMX93_CLK_LPI2C3_GATE		144
+#define IMX93_CLK_LPI2C4_GATE		145
+#define IMX93_CLK_LPI2C5_GATE		146
+#define IMX93_CLK_LPI2C6_GATE		147
+#define IMX93_CLK_LPI2C7_GATE		148
+#define IMX93_CLK_LPI2C8_GATE		149
+#define IMX93_CLK_LPSPI1_GATE		150
+#define IMX93_CLK_LPSPI2_GATE		151
+#define IMX93_CLK_LPSPI3_GATE		152
+#define IMX93_CLK_LPSPI4_GATE		153
+#define IMX93_CLK_LPSPI5_GATE		154
+#define IMX93_CLK_LPSPI6_GATE		155
+#define IMX93_CLK_LPSPI7_GATE		156
+#define IMX93_CLK_LPSPI8_GATE		157
+#define IMX93_CLK_I3C1_GATE		158
+#define IMX93_CLK_I3C2_GATE		159
+#define IMX93_CLK_USDHC1_GATE		160
+#define IMX93_CLK_USDHC2_GATE		161
+#define IMX93_CLK_USDHC3_GATE		162
+#define IMX93_CLK_SAI1_GATE		163
+#define IMX93_CLK_SAI2_GATE		164
+#define IMX93_CLK_SAI3_GATE		165
+#define IMX93_CLK_MIPI_CSI_GATE		166
+#define IMX93_CLK_MIPI_DSI_GATE		167
+#define IMX93_CLK_LVDS_GATE		168
+#define IMX93_CLK_LCDIF_GATE		169
+#define IMX93_CLK_PXP_GATE		170
+#define IMX93_CLK_ISI_GATE		171
+#define IMX93_CLK_NIC_MEDIA_GATE	172
+#define IMX93_CLK_USB_CONTROLLER_GATE	173
+#define IMX93_CLK_USB_TEST_60M_GATE	174
+#define IMX93_CLK_HSIO_TROUT_24M_GATE	175
+#define IMX93_CLK_PDM_GATE		176
+#define IMX93_CLK_MQS1_GATE		177
+#define IMX93_CLK_MQS2_GATE		178
+#define IMX93_CLK_AUD_XCVR_GATE		179
+#define IMX93_CLK_SPDIF_GATE		180
+#define IMX93_CLK_HSIO_32K_GATE		181
+#define IMX93_CLK_ENET1_GATE		182
+#define IMX93_CLK_ENET_QOS_GATE		183
+#define IMX93_CLK_SYS_CNT_GATE		184
+#define IMX93_CLK_TSTMR1_GATE		185
+#define IMX93_CLK_TSTMR2_GATE		186
+#define IMX93_CLK_TMC_GATE		187
+#define IMX93_CLK_PMRO_GATE		188
+#define IMX93_CLK_32K			189
+#define IMX93_CLK_SAI1_IPG		190
+#define IMX93_CLK_SAI2_IPG      191
+#define IMX93_CLK_SAI3_IPG      192
+#define IMX93_CLK_END			193
+#endif
diff --git a/include/dt-bindings/pinctrl/pads-imx8dxl.h b/include/dt-bindings/pinctrl/pads-imx8dxl.h
new file mode 100644
index 00000000000..3bf686050a8
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pads-imx8dxl.h
@@ -0,0 +1,662 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+/*!
+ * Header file used to configure SoC pad list.
+ */
+
+#ifndef SC_PADS_H
+#define SC_PADS_H
+
+/* Includes */
+
+/* Defines */
+
+/*!
+ * @name Pad Definitions
+ */
+/*@{*/
+#define SC_P_PCIE_CTRL0_PERST_B                  0	/* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00, LSIO.GPIO7.IO00 */
+#define SC_P_PCIE_CTRL0_CLKREQ_B                 1	/* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01, LSIO.GPIO7.IO01 */
+#define SC_P_PCIE_CTRL0_WAKE_B                   2	/* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02, LSIO.GPIO7.IO02 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP       3	/*  */
+#define SC_P_USB_SS3_TC0                         4	/* ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03, LSIO.GPIO7.IO03 */
+#define SC_P_USB_SS3_TC1                         5	/* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04, LSIO.GPIO7.IO04 */
+#define SC_P_USB_SS3_TC2                         6	/* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05, LSIO.GPIO7.IO05 */
+#define SC_P_USB_SS3_TC3                         7	/* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06, LSIO.GPIO7.IO06 */
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO            8	/*  */
+#define SC_P_EMMC0_CLK                           9	/* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */
+#define SC_P_EMMC0_CMD                           10	/* CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */
+#define SC_P_EMMC0_DATA0                         11	/* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */
+#define SC_P_EMMC0_DATA1                         12	/* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */
+#define SC_P_EMMC0_DATA2                         13	/* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */
+#define SC_P_EMMC0_DATA3                         14	/* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */
+#define SC_P_EMMC0_DATA4                         15	/* CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO4.IO13 */
+#define SC_P_EMMC0_DATA5                         16	/* CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO4.IO14 */
+#define SC_P_EMMC0_DATA6                         17	/* CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO4.IO15 */
+#define SC_P_EMMC0_DATA7                         18	/* CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO4.IO16 */
+#define SC_P_EMMC0_STROBE                        19	/* CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO4.IO17 */
+#define SC_P_EMMC0_RESET_B                       20	/* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0       21	/*  */
+#define SC_P_USDHC1_RESET_B                      22	/* CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, CONN.NAND.WE_B, LSIO.GPIO4.IO19, LSIO.GPIO7.IO08 */
+#define SC_P_USDHC1_VSELECT                      23	/* CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20, LSIO.GPIO7.IO09 */
+#define SC_P_CTL_NAND_RE_P_N                     24	/*  */
+#define SC_P_USDHC1_WP                           25	/* CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, CONN.NAND.ALE, LSIO.GPIO4.IO21, LSIO.GPIO7.IO10 */
+#define SC_P_USDHC1_CD_B                         26	/* CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22, LSIO.GPIO7.IO11 */
+#define SC_P_CTL_NAND_DQS_P_N                    27	/*  */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP       28	/*  */
+#define SC_P_ENET0_RGMII_TXC                     29	/* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29, CONN.USDHC2.CLK */
+#define SC_P_ENET0_RGMII_TX_CTL                  30	/* CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30, CONN.USDHC2.CMD */
+#define SC_P_ENET0_RGMII_TXD0                    31	/* CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31, CONN.USDHC2.DATA0 */
+#define SC_P_ENET0_RGMII_TXD1                    32	/* CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00, CONN.USDHC2.DATA1 */
+#define SC_P_ENET0_RGMII_TXD2                    33	/* CONN.ENET0.RGMII_TXD2, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01, CONN.USDHC2.DATA2 */
+#define SC_P_ENET0_RGMII_TXD3                    34	/* CONN.ENET0.RGMII_TXD3, CONN.NAND.RE_B, LSIO.GPIO5.IO02, CONN.USDHC2.DATA3 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0   35	/*  */
+#define SC_P_ENET0_RGMII_RXC                     36	/* CONN.ENET0.RGMII_RXC, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */
+#define SC_P_ENET0_RGMII_RX_CTL                  37	/* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */
+#define SC_P_ENET0_RGMII_RXD0                    38	/* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */
+#define SC_P_ENET0_RGMII_RXD1                    39	/* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */
+#define SC_P_ENET0_RGMII_RXD2                    40	/* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */
+#define SC_P_ENET0_RGMII_RXD3                    41	/* CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1   42	/*  */
+#define SC_P_ENET0_REFCLK_125M_25M               43	/* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.EQOS.PPS_IN, CONN.EQOS.PPS_OUT, LSIO.GPIO5.IO09 */
+#define SC_P_ENET0_MDIO                          44	/* CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.EQOS.MDIO, LSIO.GPIO5.IO10, LSIO.GPIO7.IO16 */
+#define SC_P_ENET0_MDC                           45	/* CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.EQOS.MDC, LSIO.GPIO5.IO11, LSIO.GPIO7.IO17 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT        46	/*  */
+#define SC_P_ENET1_RGMII_TXC                     47	/* LSIO.GPIO0.IO00, CONN.EQOS.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.EQOS.RGMII_TXC, CONN.EQOS.RCLK50M_IN */
+#define SC_P_ENET1_RGMII_TXD2                    48	/* , ADMA.LCDIF.D01, CONN.EQOS.RGMII_TXD2, LSIO.GPIO0.IO01 */
+#define SC_P_ENET1_RGMII_TX_CTL                  49	/* , ADMA.LCDIF.D02, CONN.EQOS.RGMII_TX_CTL, LSIO.GPIO0.IO02 */
+#define SC_P_ENET1_RGMII_TXD3                    50	/* , ADMA.LCDIF.D03, CONN.EQOS.RGMII_TXD3, LSIO.GPIO0.IO03 */
+#define SC_P_ENET1_RGMII_RXC                     51	/* , ADMA.LCDIF.D04, CONN.EQOS.RGMII_RXC, LSIO.GPIO0.IO04 */
+#define SC_P_ENET1_RGMII_RXD3                    52	/* , ADMA.LCDIF.D05, CONN.EQOS.RGMII_RXD3, LSIO.GPIO0.IO05 */
+#define SC_P_ENET1_RGMII_RXD2                    53	/* , ADMA.LCDIF.D06, CONN.EQOS.RGMII_RXD2, LSIO.GPIO0.IO06, LSIO.GPIO6.IO00 */
+#define SC_P_ENET1_RGMII_RXD1                    54	/* , ADMA.LCDIF.D07, CONN.EQOS.RGMII_RXD1, LSIO.GPIO0.IO07, LSIO.GPIO6.IO01 */
+#define SC_P_ENET1_RGMII_TXD0                    55	/* , ADMA.LCDIF.D08, CONN.EQOS.RGMII_TXD0, LSIO.GPIO0.IO08, LSIO.GPIO6.IO02 */
+#define SC_P_ENET1_RGMII_TXD1                    56	/* , ADMA.LCDIF.D09, CONN.EQOS.RGMII_TXD1, LSIO.GPIO0.IO09, LSIO.GPIO6.IO03 */
+#define SC_P_ENET1_RGMII_RXD0                    57	/* ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.EQOS.RGMII_RXD0, LSIO.GPIO0.IO10, LSIO.GPIO6.IO04 */
+#define SC_P_ENET1_RGMII_RX_CTL                  58	/* ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.EQOS.RGMII_RX_CTL, LSIO.GPIO0.IO11, LSIO.GPIO6.IO05 */
+#define SC_P_ENET1_REFCLK_125M_25M               59	/* ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.EQOS.REFCLK_125M_25M, LSIO.GPIO0.IO12, LSIO.GPIO6.IO06 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB       60	/*  */
+#define SC_P_SPI3_SCK                            61	/* ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13, ADMA.LCDIF.D00 */
+#define SC_P_SPI3_SDO                            62	/* ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14, ADMA.LCDIF.D01 */
+#define SC_P_SPI3_SDI                            63	/* ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15, ADMA.LCDIF.D02 */
+#define SC_P_SPI3_CS0                            64	/* ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16, ADMA.LCDIF.CS */
+#define SC_P_SPI3_CS1                            65	/* ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16, ADMA.LCDIF.RD_E */
+#define SC_P_MCLK_IN1                            66	/* ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17, ADMA.LCDIF.D03 */
+#define SC_P_MCLK_IN0                            67	/* ADMA.ACM.MCLK_IN0, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19, ADMA.LCDIF.RS */
+#define SC_P_MCLK_OUT0                           68	/* ADMA.ACM.MCLK_OUT0, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20, ADMA.LCDIF.WR_RWN */
+#define SC_P_UART1_TX                            69	/* ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21, ADMA.LCDIF.D04 */
+#define SC_P_UART1_RX                            70	/* ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22, ADMA.LCDIF.D05 */
+#define SC_P_UART1_RTS_B                         71	/* ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK, ADMA.LCDIF.D06 */
+#define SC_P_UART1_CTS_B                         72	/* ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24, ADMA.LCDIF.D07 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK       73	/*  */
+#define SC_P_SPI0_SCK                            74	/* ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04, ADMA.LCDIF.D08 */
+#define SC_P_SPI0_SDI                            75	/* ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05, ADMA.LCDIF.D09 */
+#define SC_P_SPI0_SDO                            76	/* ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06, ADMA.LCDIF.D10 */
+#define SC_P_SPI0_CS1                            77	/* ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07, ADMA.LCDIF.D11 */
+#define SC_P_SPI0_CS0                            78	/* ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08, ADMA.LCDIF.D12 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT       79	/*  */
+#define SC_P_ADC_IN1                             80	/* ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO1.IO09, ADMA.LCDIF.D13 */
+#define SC_P_ADC_IN0                             81	/* ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO1.IO10, ADMA.LCDIF.D14 */
+#define SC_P_ADC_IN3                             82	/* ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11, ADMA.LCDIF.D15 */
+#define SC_P_ADC_IN2                             83	/* ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12, ADMA.LCDIF.D16 */
+#define SC_P_ADC_IN5                             84	/* ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, ADMA.LCDIF.LCDBUSY, LSIO.GPIO1.IO13, ADMA.LCDIF.D17 */
+#define SC_P_ADC_IN4                             85	/* ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, ADMA.LCDIF.LCDRESET, LSIO.GPIO1.IO14 */
+#define SC_P_FLEXCAN0_RX                         86	/* ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15, LSIO.GPIO6.IO08 */
+#define SC_P_FLEXCAN0_TX                         87	/* ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16, LSIO.GPIO6.IO09 */
+#define SC_P_FLEXCAN1_RX                         88	/* ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17, LSIO.GPIO6.IO10 */
+#define SC_P_FLEXCAN1_TX                         89	/* ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18, LSIO.GPIO6.IO11 */
+#define SC_P_FLEXCAN2_RX                         90	/* ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19, LSIO.GPIO6.IO12 */
+#define SC_P_FLEXCAN2_TX                         91	/* ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20, LSIO.GPIO6.IO13 */
+#define SC_P_UART0_RX                            92	/* ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21, LSIO.GPIO6.IO14 */
+#define SC_P_UART0_TX                            93	/* ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22, LSIO.GPIO6.IO15 */
+#define SC_P_UART2_TX                            94	/* ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23, LSIO.GPIO6.IO16 */
+#define SC_P_UART2_RX                            95	/* ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24, LSIO.GPIO6.IO17 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH        96	/*  */
+#define SC_P_JTAG_TRST_B                         97	/* SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */
+#define SC_P_PMIC_I2C_SCL                        98	/* SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */
+#define SC_P_PMIC_I2C_SDA                        99	/* SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */
+#define SC_P_PMIC_INT_B                          100	/* SCU.DSC.PMIC_INT_B */
+#define SC_P_SCU_GPIO0_00                        101	/* SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */
+#define SC_P_SCU_GPIO0_01                        102	/* SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */
+#define SC_P_SCU_PMIC_STANDBY                    103	/* SCU.DSC.PMIC_STANDBY */
+#define SC_P_SCU_BOOT_MODE1                      104	/* SCU.DSC.BOOT_MODE1 */
+#define SC_P_SCU_BOOT_MODE0                      105	/* SCU.DSC.BOOT_MODE0 */
+#define SC_P_SCU_BOOT_MODE2                      106	/* SCU.DSC.BOOT_MODE2, SCU.DSC.RTC_CLOCK_OUTPUT_32K */
+#define SC_P_SNVS_TAMPER_OUT1                    107	/* , LSIO.GPIO2.IO05_IN, LSIO.GPIO6.IO19_IN */
+#define SC_P_SNVS_TAMPER_OUT2                    108	/* , LSIO.GPIO2.IO06_IN, LSIO.GPIO6.IO20_IN */
+#define SC_P_SNVS_TAMPER_OUT3                    109	/* , ADMA.SAI2.RXC, LSIO.GPIO2.IO07_IN, LSIO.GPIO6.IO21_IN */
+#define SC_P_SNVS_TAMPER_OUT4                    110	/* , ADMA.SAI2.RXD, LSIO.GPIO2.IO08_IN, LSIO.GPIO6.IO22_IN */
+#define SC_P_SNVS_TAMPER_IN0                     111	/* , ADMA.SAI2.RXFS, LSIO.GPIO2.IO09_IN, LSIO.GPIO6.IO23_IN */
+#define SC_P_SNVS_TAMPER_IN1                     112	/* , ADMA.SAI3.RXC, LSIO.GPIO2.IO10_IN, LSIO.GPIO6.IO24_IN */
+#define SC_P_SNVS_TAMPER_IN2                     113	/* , ADMA.SAI3.RXD, LSIO.GPIO2.IO11_IN, LSIO.GPIO6.IO25_IN */
+#define SC_P_SNVS_TAMPER_IN3                     114	/* , ADMA.SAI3.RXFS, LSIO.GPIO2.IO12_IN, LSIO.GPIO6.IO26_IN */
+#define SC_P_SPI1_SCK                            115	/* , ADMA.I2C2.SDA, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */
+#define SC_P_SPI1_SDO                            116	/* , ADMA.I2C2.SCL, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */
+#define SC_P_SPI1_SDI                            117	/* , ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */
+#define SC_P_SPI1_CS0                            118	/* , ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD       119	/*  */
+#define SC_P_QSPI0A_DATA1                        120	/* LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */
+#define SC_P_QSPI0A_DATA0                        121	/* LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */
+#define SC_P_QSPI0A_DATA3                        122	/* LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */
+#define SC_P_QSPI0A_DATA2                        123	/* LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */
+#define SC_P_QSPI0A_SS0_B                        124	/* LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */
+#define SC_P_QSPI0A_DQS                          125	/* LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */
+#define SC_P_QSPI0A_SCLK                         126	/* LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A        127	/*  */
+#define SC_P_QSPI0B_SCLK                         128	/* LSIO.QSPI0B.SCLK, LSIO.GPIO3.IO17 */
+#define SC_P_QSPI0B_DQS                          129	/* LSIO.QSPI0B.DQS, LSIO.GPIO3.IO22 */
+#define SC_P_QSPI0B_DATA1                        130	/* LSIO.QSPI0B.DATA1, LSIO.GPIO3.IO19 */
+#define SC_P_QSPI0B_DATA0                        131	/* LSIO.QSPI0B.DATA0, LSIO.GPIO3.IO18 */
+#define SC_P_QSPI0B_DATA3                        132	/* LSIO.QSPI0B.DATA3, LSIO.GPIO3.IO21 */
+#define SC_P_QSPI0B_DATA2                        133	/* LSIO.QSPI0B.DATA2, LSIO.GPIO3.IO20 */
+#define SC_P_QSPI0B_SS0_B                        134	/* LSIO.QSPI0B.SS0_B, LSIO.GPIO3.IO23, LSIO.QSPI0A.SS1_B */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B        135	/*  */
+/*@}*/
+
+/*!
+ * @name Pad Mux Definitions
+ * format: name padid padmux
+ */
+/*@{*/
+#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B              SC_P_PCIE_CTRL0_PERST_B            0
+#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00                 SC_P_PCIE_CTRL0_PERST_B            4
+#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO7_IO00                 SC_P_PCIE_CTRL0_PERST_B            5
+#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B            SC_P_PCIE_CTRL0_CLKREQ_B           0
+#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01                SC_P_PCIE_CTRL0_CLKREQ_B           4
+#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO7_IO01                SC_P_PCIE_CTRL0_CLKREQ_B           5
+#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B                SC_P_PCIE_CTRL0_WAKE_B             0
+#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02                  SC_P_PCIE_CTRL0_WAKE_B             4
+#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO7_IO02                  SC_P_PCIE_CTRL0_WAKE_B             5
+#define SC_P_USB_SS3_TC0_ADMA_I2C1_SCL                          SC_P_USB_SS3_TC0                   0
+#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR                      SC_P_USB_SS3_TC0                   1
+#define SC_P_USB_SS3_TC0_CONN_USB_OTG2_PWR                      SC_P_USB_SS3_TC0                   2
+#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03                        SC_P_USB_SS3_TC0                   4
+#define SC_P_USB_SS3_TC0_LSIO_GPIO7_IO03                        SC_P_USB_SS3_TC0                   5
+#define SC_P_USB_SS3_TC1_ADMA_I2C1_SCL                          SC_P_USB_SS3_TC1                   0
+#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR                      SC_P_USB_SS3_TC1                   1
+#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04                        SC_P_USB_SS3_TC1                   4
+#define SC_P_USB_SS3_TC1_LSIO_GPIO7_IO04                        SC_P_USB_SS3_TC1                   5
+#define SC_P_USB_SS3_TC2_ADMA_I2C1_SDA                          SC_P_USB_SS3_TC2                   0
+#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC                       SC_P_USB_SS3_TC2                   1
+#define SC_P_USB_SS3_TC2_CONN_USB_OTG2_OC                       SC_P_USB_SS3_TC2                   2
+#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05                        SC_P_USB_SS3_TC2                   4
+#define SC_P_USB_SS3_TC2_LSIO_GPIO7_IO05                        SC_P_USB_SS3_TC2                   5
+#define SC_P_USB_SS3_TC3_ADMA_I2C1_SDA                          SC_P_USB_SS3_TC3                   0
+#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC                       SC_P_USB_SS3_TC3                   1
+#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06                        SC_P_USB_SS3_TC3                   4
+#define SC_P_USB_SS3_TC3_LSIO_GPIO7_IO06                        SC_P_USB_SS3_TC3                   5
+#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK                           SC_P_EMMC0_CLK                     0
+#define SC_P_EMMC0_CLK_CONN_NAND_READY_B                        SC_P_EMMC0_CLK                     1
+#define SC_P_EMMC0_CLK_LSIO_GPIO4_IO07                          SC_P_EMMC0_CLK                     4
+#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD                           SC_P_EMMC0_CMD                     0
+#define SC_P_EMMC0_CMD_CONN_NAND_DQS                            SC_P_EMMC0_CMD                     1
+#define SC_P_EMMC0_CMD_LSIO_GPIO4_IO08                          SC_P_EMMC0_CMD                     4
+#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0                       SC_P_EMMC0_DATA0                   0
+#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00                       SC_P_EMMC0_DATA0                   1
+#define SC_P_EMMC0_DATA0_LSIO_GPIO4_IO09                        SC_P_EMMC0_DATA0                   4
+#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1                       SC_P_EMMC0_DATA1                   0
+#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01                       SC_P_EMMC0_DATA1                   1
+#define SC_P_EMMC0_DATA1_LSIO_GPIO4_IO10                        SC_P_EMMC0_DATA1                   4
+#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2                       SC_P_EMMC0_DATA2                   0
+#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02                       SC_P_EMMC0_DATA2                   1
+#define SC_P_EMMC0_DATA2_LSIO_GPIO4_IO11                        SC_P_EMMC0_DATA2                   4
+#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3                       SC_P_EMMC0_DATA3                   0
+#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03                       SC_P_EMMC0_DATA3                   1
+#define SC_P_EMMC0_DATA3_LSIO_GPIO4_IO12                        SC_P_EMMC0_DATA3                   4
+#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4                       SC_P_EMMC0_DATA4                   0
+#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04                       SC_P_EMMC0_DATA4                   1
+#define SC_P_EMMC0_DATA4_LSIO_GPIO4_IO13                        SC_P_EMMC0_DATA4                   4
+#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5                       SC_P_EMMC0_DATA5                   0
+#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05                       SC_P_EMMC0_DATA5                   1
+#define SC_P_EMMC0_DATA5_LSIO_GPIO4_IO14                        SC_P_EMMC0_DATA5                   4
+#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6                       SC_P_EMMC0_DATA6                   0
+#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06                       SC_P_EMMC0_DATA6                   1
+#define SC_P_EMMC0_DATA6_LSIO_GPIO4_IO15                        SC_P_EMMC0_DATA6                   4
+#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7                       SC_P_EMMC0_DATA7                   0
+#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07                       SC_P_EMMC0_DATA7                   1
+#define SC_P_EMMC0_DATA7_LSIO_GPIO4_IO16                        SC_P_EMMC0_DATA7                   4
+#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE                     SC_P_EMMC0_STROBE                  0
+#define SC_P_EMMC0_STROBE_CONN_NAND_CLE                         SC_P_EMMC0_STROBE                  1
+#define SC_P_EMMC0_STROBE_LSIO_GPIO4_IO17                       SC_P_EMMC0_STROBE                  4
+#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B                   SC_P_EMMC0_RESET_B                 0
+#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B                       SC_P_EMMC0_RESET_B                 1
+#define SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18                      SC_P_EMMC0_RESET_B                 4
+#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B                 SC_P_USDHC1_RESET_B                0
+#define SC_P_USDHC1_RESET_B_CONN_NAND_RE_N                      SC_P_USDHC1_RESET_B                1
+#define SC_P_USDHC1_RESET_B_ADMA_SPI2_SCK                       SC_P_USDHC1_RESET_B                2
+#define SC_P_USDHC1_RESET_B_CONN_NAND_WE_B                      SC_P_USDHC1_RESET_B                3
+#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19                     SC_P_USDHC1_RESET_B                4
+#define SC_P_USDHC1_RESET_B_LSIO_GPIO7_IO08                     SC_P_USDHC1_RESET_B                5
+#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT                 SC_P_USDHC1_VSELECT                0
+#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_P                      SC_P_USDHC1_VSELECT                1
+#define SC_P_USDHC1_VSELECT_ADMA_SPI2_SDO                       SC_P_USDHC1_VSELECT                2
+#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_B                      SC_P_USDHC1_VSELECT                3
+#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO20                     SC_P_USDHC1_VSELECT                4
+#define SC_P_USDHC1_VSELECT_LSIO_GPIO7_IO09                     SC_P_USDHC1_VSELECT                5
+#define SC_P_USDHC1_WP_CONN_USDHC1_WP                           SC_P_USDHC1_WP                     0
+#define SC_P_USDHC1_WP_CONN_NAND_DQS_N                          SC_P_USDHC1_WP                     1
+#define SC_P_USDHC1_WP_ADMA_SPI2_SDI                            SC_P_USDHC1_WP                     2
+#define SC_P_USDHC1_WP_CONN_NAND_ALE                            SC_P_USDHC1_WP                     3
+#define SC_P_USDHC1_WP_LSIO_GPIO4_IO21                          SC_P_USDHC1_WP                     4
+#define SC_P_USDHC1_WP_LSIO_GPIO7_IO10                          SC_P_USDHC1_WP                     5
+#define SC_P_USDHC1_CD_B_CONN_USDHC1_CD_B                       SC_P_USDHC1_CD_B                   0
+#define SC_P_USDHC1_CD_B_CONN_NAND_DQS_P                        SC_P_USDHC1_CD_B                   1
+#define SC_P_USDHC1_CD_B_ADMA_SPI2_CS0                          SC_P_USDHC1_CD_B                   2
+#define SC_P_USDHC1_CD_B_CONN_NAND_DQS                          SC_P_USDHC1_CD_B                   3
+#define SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22                        SC_P_USDHC1_CD_B                   4
+#define SC_P_USDHC1_CD_B_LSIO_GPIO7_IO11                        SC_P_USDHC1_CD_B                   5
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC               SC_P_ENET0_RGMII_TXC               0
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT             SC_P_ENET0_RGMII_TXC               1
+#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN              SC_P_ENET0_RGMII_TXC               2
+#define SC_P_ENET0_RGMII_TXC_CONN_NAND_CE1_B                    SC_P_ENET0_RGMII_TXC               3
+#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29                    SC_P_ENET0_RGMII_TXC               4
+#define SC_P_ENET0_RGMII_TXC_CONN_USDHC2_CLK                    SC_P_ENET0_RGMII_TXC               5
+#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL         SC_P_ENET0_RGMII_TX_CTL            0
+#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B             SC_P_ENET0_RGMII_TX_CTL            3
+#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30                 SC_P_ENET0_RGMII_TX_CTL            4
+#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC2_CMD                 SC_P_ENET0_RGMII_TX_CTL            5
+#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0             SC_P_ENET0_RGMII_TXD0              0
+#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT               SC_P_ENET0_RGMII_TXD0              3
+#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31                   SC_P_ENET0_RGMII_TXD0              4
+#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC2_DATA0                 SC_P_ENET0_RGMII_TXD0              5
+#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1             SC_P_ENET0_RGMII_TXD1              0
+#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC1_WP                    SC_P_ENET0_RGMII_TXD1              3
+#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00                   SC_P_ENET0_RGMII_TXD1              4
+#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC2_DATA1                 SC_P_ENET0_RGMII_TXD1              5
+#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2             SC_P_ENET0_RGMII_TXD2              0
+#define SC_P_ENET0_RGMII_TXD2_CONN_NAND_CE0_B                   SC_P_ENET0_RGMII_TXD2              2
+#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B                  SC_P_ENET0_RGMII_TXD2              3
+#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01                   SC_P_ENET0_RGMII_TXD2              4
+#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC2_DATA2                 SC_P_ENET0_RGMII_TXD2              5
+#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3             SC_P_ENET0_RGMII_TXD3              0
+#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B                    SC_P_ENET0_RGMII_TXD3              2
+#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02                   SC_P_ENET0_RGMII_TXD3              4
+#define SC_P_ENET0_RGMII_TXD3_CONN_USDHC2_DATA3                 SC_P_ENET0_RGMII_TXD3              5
+#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC               SC_P_ENET0_RGMII_RXC               0
+#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B                     SC_P_ENET0_RGMII_RXC               2
+#define SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK                    SC_P_ENET0_RGMII_RXC               3
+#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03                    SC_P_ENET0_RGMII_RXC               4
+#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL         SC_P_ENET0_RGMII_RX_CTL            0
+#define SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD                 SC_P_ENET0_RGMII_RX_CTL            3
+#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04                 SC_P_ENET0_RGMII_RX_CTL            4
+#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0             SC_P_ENET0_RGMII_RXD0              0
+#define SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0                 SC_P_ENET0_RGMII_RXD0              3
+#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05                   SC_P_ENET0_RGMII_RXD0              4
+#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1             SC_P_ENET0_RGMII_RXD1              0
+#define SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1                 SC_P_ENET0_RGMII_RXD1              3
+#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06                   SC_P_ENET0_RGMII_RXD1              4
+#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2             SC_P_ENET0_RGMII_RXD2              0
+#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER             SC_P_ENET0_RGMII_RXD2              1
+#define SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2                 SC_P_ENET0_RGMII_RXD2              3
+#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07                   SC_P_ENET0_RGMII_RXD2              4
+#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3             SC_P_ENET0_RGMII_RXD3              0
+#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE                     SC_P_ENET0_RGMII_RXD3              2
+#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3                 SC_P_ENET0_RGMII_RXD3              3
+#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08                   SC_P_ENET0_RGMII_RXD3              4
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M   SC_P_ENET0_REFCLK_125M_25M         0
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS               SC_P_ENET0_REFCLK_125M_25M         1
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_EQOS_PPS_IN             SC_P_ENET0_REFCLK_125M_25M         2
+#define SC_P_ENET0_REFCLK_125M_25M_CONN_EQOS_PPS_OUT            SC_P_ENET0_REFCLK_125M_25M         3
+#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09              SC_P_ENET0_REFCLK_125M_25M         4
+#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO                         SC_P_ENET0_MDIO                    0
+#define SC_P_ENET0_MDIO_ADMA_I2C3_SDA                           SC_P_ENET0_MDIO                    1
+#define SC_P_ENET0_MDIO_CONN_EQOS_MDIO                          SC_P_ENET0_MDIO                    2
+#define SC_P_ENET0_MDIO_LSIO_GPIO5_IO10                         SC_P_ENET0_MDIO                    4
+#define SC_P_ENET0_MDIO_LSIO_GPIO7_IO16                         SC_P_ENET0_MDIO                    5
+#define SC_P_ENET0_MDC_CONN_ENET0_MDC                           SC_P_ENET0_MDC                     0
+#define SC_P_ENET0_MDC_ADMA_I2C3_SCL                            SC_P_ENET0_MDC                     1
+#define SC_P_ENET0_MDC_CONN_EQOS_MDC                            SC_P_ENET0_MDC                     2
+#define SC_P_ENET0_MDC_LSIO_GPIO5_IO11                          SC_P_ENET0_MDC                     4
+#define SC_P_ENET0_MDC_LSIO_GPIO7_IO17                          SC_P_ENET0_MDC                     5
+#define SC_P_ENET1_RGMII_TXC_LSIO_GPIO0_IO00                    SC_P_ENET1_RGMII_TXC               0
+#define SC_P_ENET1_RGMII_TXC_CONN_EQOS_RCLK50M_OUT              SC_P_ENET1_RGMII_TXC               1
+#define SC_P_ENET1_RGMII_TXC_ADMA_LCDIF_D00                     SC_P_ENET1_RGMII_TXC               2
+#define SC_P_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC                SC_P_ENET1_RGMII_TXC               3
+#define SC_P_ENET1_RGMII_TXC_CONN_EQOS_RCLK50M_IN               SC_P_ENET1_RGMII_TXC               4
+#define SC_P_ENET1_RGMII_TXD2_ADMA_LCDIF_D01                    SC_P_ENET1_RGMII_TXD2              2
+#define SC_P_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2              SC_P_ENET1_RGMII_TXD2              3
+#define SC_P_ENET1_RGMII_TXD2_LSIO_GPIO0_IO01                   SC_P_ENET1_RGMII_TXD2              4
+#define SC_P_ENET1_RGMII_TX_CTL_ADMA_LCDIF_D02                  SC_P_ENET1_RGMII_TX_CTL            2
+#define SC_P_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL          SC_P_ENET1_RGMII_TX_CTL            3
+#define SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO0_IO02                 SC_P_ENET1_RGMII_TX_CTL            4
+#define SC_P_ENET1_RGMII_TXD3_ADMA_LCDIF_D03                    SC_P_ENET1_RGMII_TXD3              2
+#define SC_P_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3              SC_P_ENET1_RGMII_TXD3              3
+#define SC_P_ENET1_RGMII_TXD3_LSIO_GPIO0_IO03                   SC_P_ENET1_RGMII_TXD3              4
+#define SC_P_ENET1_RGMII_RXC_ADMA_LCDIF_D04                     SC_P_ENET1_RGMII_RXC               2
+#define SC_P_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC                SC_P_ENET1_RGMII_RXC               3
+#define SC_P_ENET1_RGMII_RXC_LSIO_GPIO0_IO04                    SC_P_ENET1_RGMII_RXC               4
+#define SC_P_ENET1_RGMII_RXD3_ADMA_LCDIF_D05                    SC_P_ENET1_RGMII_RXD3              2
+#define SC_P_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3              SC_P_ENET1_RGMII_RXD3              3
+#define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO0_IO05                   SC_P_ENET1_RGMII_RXD3              4
+#define SC_P_ENET1_RGMII_RXD2_ADMA_LCDIF_D06                    SC_P_ENET1_RGMII_RXD2              2
+#define SC_P_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2              SC_P_ENET1_RGMII_RXD2              3
+#define SC_P_ENET1_RGMII_RXD2_LSIO_GPIO0_IO06                   SC_P_ENET1_RGMII_RXD2              4
+#define SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO00                   SC_P_ENET1_RGMII_RXD2              5
+#define SC_P_ENET1_RGMII_RXD1_ADMA_LCDIF_D07                    SC_P_ENET1_RGMII_RXD1              2
+#define SC_P_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1              SC_P_ENET1_RGMII_RXD1              3
+#define SC_P_ENET1_RGMII_RXD1_LSIO_GPIO0_IO07                   SC_P_ENET1_RGMII_RXD1              4
+#define SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO01                   SC_P_ENET1_RGMII_RXD1              5
+#define SC_P_ENET1_RGMII_TXD0_ADMA_LCDIF_D08                    SC_P_ENET1_RGMII_TXD0              2
+#define SC_P_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0              SC_P_ENET1_RGMII_TXD0              3
+#define SC_P_ENET1_RGMII_TXD0_LSIO_GPIO0_IO08                   SC_P_ENET1_RGMII_TXD0              4
+#define SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO02                   SC_P_ENET1_RGMII_TXD0              5
+#define SC_P_ENET1_RGMII_TXD1_ADMA_LCDIF_D09                    SC_P_ENET1_RGMII_TXD1              2
+#define SC_P_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1              SC_P_ENET1_RGMII_TXD1              3
+#define SC_P_ENET1_RGMII_TXD1_LSIO_GPIO0_IO09                   SC_P_ENET1_RGMII_TXD1              4
+#define SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO03                   SC_P_ENET1_RGMII_TXD1              5
+#define SC_P_ENET1_RGMII_RXD0_ADMA_SPDIF0_RX                    SC_P_ENET1_RGMII_RXD0              0
+#define SC_P_ENET1_RGMII_RXD0_ADMA_MQS_R                        SC_P_ENET1_RGMII_RXD0              1
+#define SC_P_ENET1_RGMII_RXD0_ADMA_LCDIF_D10                    SC_P_ENET1_RGMII_RXD0              2
+#define SC_P_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0              SC_P_ENET1_RGMII_RXD0              3
+#define SC_P_ENET1_RGMII_RXD0_LSIO_GPIO0_IO10                   SC_P_ENET1_RGMII_RXD0              4
+#define SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO04                   SC_P_ENET1_RGMII_RXD0              5
+#define SC_P_ENET1_RGMII_RX_CTL_ADMA_SPDIF0_TX                  SC_P_ENET1_RGMII_RX_CTL            0
+#define SC_P_ENET1_RGMII_RX_CTL_ADMA_MQS_L                      SC_P_ENET1_RGMII_RX_CTL            1
+#define SC_P_ENET1_RGMII_RX_CTL_ADMA_LCDIF_D11                  SC_P_ENET1_RGMII_RX_CTL            2
+#define SC_P_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL          SC_P_ENET1_RGMII_RX_CTL            3
+#define SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO0_IO11                 SC_P_ENET1_RGMII_RX_CTL            4
+#define SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO05                 SC_P_ENET1_RGMII_RX_CTL            5
+#define SC_P_ENET1_REFCLK_125M_25M_ADMA_SPDIF0_EXT_CLK          SC_P_ENET1_REFCLK_125M_25M         0
+#define SC_P_ENET1_REFCLK_125M_25M_ADMA_LCDIF_D12               SC_P_ENET1_REFCLK_125M_25M         2
+#define SC_P_ENET1_REFCLK_125M_25M_CONN_EQOS_REFCLK_125M_25M    SC_P_ENET1_REFCLK_125M_25M         3
+#define SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO0_IO12              SC_P_ENET1_REFCLK_125M_25M         4
+#define SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO6_IO06              SC_P_ENET1_REFCLK_125M_25M         5
+#define SC_P_SPI3_SCK_ADMA_SPI3_SCK                             SC_P_SPI3_SCK                      0
+#define SC_P_SPI3_SCK_ADMA_LCDIF_D13                            SC_P_SPI3_SCK                      2
+#define SC_P_SPI3_SCK_LSIO_GPIO0_IO13                           SC_P_SPI3_SCK                      4
+#define SC_P_SPI3_SCK_ADMA_LCDIF_D00                            SC_P_SPI3_SCK                      5
+#define SC_P_SPI3_SDO_ADMA_SPI3_SDO                             SC_P_SPI3_SDO                      0
+#define SC_P_SPI3_SDO_ADMA_LCDIF_D14                            SC_P_SPI3_SDO                      2
+#define SC_P_SPI3_SDO_LSIO_GPIO0_IO14                           SC_P_SPI3_SDO                      4
+#define SC_P_SPI3_SDO_ADMA_LCDIF_D01                            SC_P_SPI3_SDO                      5
+#define SC_P_SPI3_SDI_ADMA_SPI3_SDI                             SC_P_SPI3_SDI                      0
+#define SC_P_SPI3_SDI_ADMA_LCDIF_D15                            SC_P_SPI3_SDI                      2
+#define SC_P_SPI3_SDI_LSIO_GPIO0_IO15                           SC_P_SPI3_SDI                      4
+#define SC_P_SPI3_SDI_ADMA_LCDIF_D02                            SC_P_SPI3_SDI                      5
+#define SC_P_SPI3_CS0_ADMA_SPI3_CS0                             SC_P_SPI3_CS0                      0
+#define SC_P_SPI3_CS0_ADMA_ACM_MCLK_OUT1                        SC_P_SPI3_CS0                      1
+#define SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC                          SC_P_SPI3_CS0                      2
+#define SC_P_SPI3_CS0_LSIO_GPIO0_IO16                           SC_P_SPI3_CS0                      4
+#define SC_P_SPI3_CS0_ADMA_LCDIF_CS                             SC_P_SPI3_CS0                      5
+#define SC_P_SPI3_CS1_ADMA_SPI3_CS1                             SC_P_SPI3_CS1                      0
+#define SC_P_SPI3_CS1_ADMA_I2C3_SCL                             SC_P_SPI3_CS1                      1
+#define SC_P_SPI3_CS1_ADMA_LCDIF_RESET                          SC_P_SPI3_CS1                      2
+#define SC_P_SPI3_CS1_ADMA_SPI2_CS0                             SC_P_SPI3_CS1                      3
+#define SC_P_SPI3_CS1_ADMA_LCDIF_D16                            SC_P_SPI3_CS1                      4
+#define SC_P_SPI3_CS1_ADMA_LCDIF_RD_E                           SC_P_SPI3_CS1                      5
+#define SC_P_MCLK_IN1_ADMA_ACM_MCLK_IN1                         SC_P_MCLK_IN1                      0
+#define SC_P_MCLK_IN1_ADMA_I2C3_SDA                             SC_P_MCLK_IN1                      1
+#define SC_P_MCLK_IN1_ADMA_LCDIF_EN                             SC_P_MCLK_IN1                      2
+#define SC_P_MCLK_IN1_ADMA_SPI2_SCK                             SC_P_MCLK_IN1                      3
+#define SC_P_MCLK_IN1_ADMA_LCDIF_D17                            SC_P_MCLK_IN1                      4
+#define SC_P_MCLK_IN1_ADMA_LCDIF_D03                            SC_P_MCLK_IN1                      5
+#define SC_P_MCLK_IN0_ADMA_ACM_MCLK_IN0                         SC_P_MCLK_IN0                      0
+#define SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC                          SC_P_MCLK_IN0                      2
+#define SC_P_MCLK_IN0_ADMA_SPI2_SDI                             SC_P_MCLK_IN0                      3
+#define SC_P_MCLK_IN0_LSIO_GPIO0_IO19                           SC_P_MCLK_IN0                      4
+#define SC_P_MCLK_IN0_ADMA_LCDIF_RS                             SC_P_MCLK_IN0                      5
+#define SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0                       SC_P_MCLK_OUT0                     0
+#define SC_P_MCLK_OUT0_ADMA_LCDIF_CLK                           SC_P_MCLK_OUT0                     2
+#define SC_P_MCLK_OUT0_ADMA_SPI2_SDO                            SC_P_MCLK_OUT0                     3
+#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20                          SC_P_MCLK_OUT0                     4
+#define SC_P_MCLK_OUT0_ADMA_LCDIF_WR_RWN                        SC_P_MCLK_OUT0                     5
+#define SC_P_UART1_TX_ADMA_UART1_TX                             SC_P_UART1_TX                      0
+#define SC_P_UART1_TX_LSIO_PWM0_OUT                             SC_P_UART1_TX                      1
+#define SC_P_UART1_TX_LSIO_GPT0_CAPTURE                         SC_P_UART1_TX                      2
+#define SC_P_UART1_TX_LSIO_GPIO0_IO21                           SC_P_UART1_TX                      4
+#define SC_P_UART1_TX_ADMA_LCDIF_D04                            SC_P_UART1_TX                      5
+#define SC_P_UART1_RX_ADMA_UART1_RX                             SC_P_UART1_RX                      0
+#define SC_P_UART1_RX_LSIO_PWM1_OUT                             SC_P_UART1_RX                      1
+#define SC_P_UART1_RX_LSIO_GPT0_COMPARE                         SC_P_UART1_RX                      2
+#define SC_P_UART1_RX_LSIO_GPT1_CLK                             SC_P_UART1_RX                      3
+#define SC_P_UART1_RX_LSIO_GPIO0_IO22                           SC_P_UART1_RX                      4
+#define SC_P_UART1_RX_ADMA_LCDIF_D05                            SC_P_UART1_RX                      5
+#define SC_P_UART1_RTS_B_ADMA_UART1_RTS_B                       SC_P_UART1_RTS_B                   0
+#define SC_P_UART1_RTS_B_LSIO_PWM2_OUT                          SC_P_UART1_RTS_B                   1
+#define SC_P_UART1_RTS_B_ADMA_LCDIF_D16                         SC_P_UART1_RTS_B                   2
+#define SC_P_UART1_RTS_B_LSIO_GPT1_CAPTURE                      SC_P_UART1_RTS_B                   3
+#define SC_P_UART1_RTS_B_LSIO_GPT0_CLK                          SC_P_UART1_RTS_B                   4
+#define SC_P_UART1_RTS_B_ADMA_LCDIF_D06                         SC_P_UART1_RTS_B                   5
+#define SC_P_UART1_CTS_B_ADMA_UART1_CTS_B                       SC_P_UART1_CTS_B                   0
+#define SC_P_UART1_CTS_B_LSIO_PWM3_OUT                          SC_P_UART1_CTS_B                   1
+#define SC_P_UART1_CTS_B_ADMA_LCDIF_D17                         SC_P_UART1_CTS_B                   2
+#define SC_P_UART1_CTS_B_LSIO_GPT1_COMPARE                      SC_P_UART1_CTS_B                   3
+#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO24                        SC_P_UART1_CTS_B                   4
+#define SC_P_UART1_CTS_B_ADMA_LCDIF_D07                         SC_P_UART1_CTS_B                   5
+#define SC_P_SPI0_SCK_ADMA_SPI0_SCK                             SC_P_SPI0_SCK                      0
+#define SC_P_SPI0_SCK_ADMA_SAI0_TXC                             SC_P_SPI0_SCK                      1
+#define SC_P_SPI0_SCK_M40_I2C0_SCL                              SC_P_SPI0_SCK                      2
+#define SC_P_SPI0_SCK_M40_GPIO0_IO00                            SC_P_SPI0_SCK                      3
+#define SC_P_SPI0_SCK_LSIO_GPIO1_IO04                           SC_P_SPI0_SCK                      4
+#define SC_P_SPI0_SCK_ADMA_LCDIF_D08                            SC_P_SPI0_SCK                      5
+#define SC_P_SPI0_SDI_ADMA_SPI0_SDI                             SC_P_SPI0_SDI                      0
+#define SC_P_SPI0_SDI_ADMA_SAI0_TXD                             SC_P_SPI0_SDI                      1
+#define SC_P_SPI0_SDI_M40_TPM0_CH0                              SC_P_SPI0_SDI                      2
+#define SC_P_SPI0_SDI_M40_GPIO0_IO02                            SC_P_SPI0_SDI                      3
+#define SC_P_SPI0_SDI_LSIO_GPIO1_IO05                           SC_P_SPI0_SDI                      4
+#define SC_P_SPI0_SDI_ADMA_LCDIF_D09                            SC_P_SPI0_SDI                      5
+#define SC_P_SPI0_SDO_ADMA_SPI0_SDO                             SC_P_SPI0_SDO                      0
+#define SC_P_SPI0_SDO_ADMA_SAI0_TXFS                            SC_P_SPI0_SDO                      1
+#define SC_P_SPI0_SDO_M40_I2C0_SDA                              SC_P_SPI0_SDO                      2
+#define SC_P_SPI0_SDO_M40_GPIO0_IO01                            SC_P_SPI0_SDO                      3
+#define SC_P_SPI0_SDO_LSIO_GPIO1_IO06                           SC_P_SPI0_SDO                      4
+#define SC_P_SPI0_SDO_ADMA_LCDIF_D10                            SC_P_SPI0_SDO                      5
+#define SC_P_SPI0_CS1_ADMA_SPI0_CS1                             SC_P_SPI0_CS1                      0
+#define SC_P_SPI0_CS1_ADMA_SAI0_RXC                             SC_P_SPI0_CS1                      1
+#define SC_P_SPI0_CS1_ADMA_SAI1_TXD                             SC_P_SPI0_CS1                      2
+#define SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT                         SC_P_SPI0_CS1                      3
+#define SC_P_SPI0_CS1_LSIO_GPIO1_IO07                           SC_P_SPI0_CS1                      4
+#define SC_P_SPI0_CS1_ADMA_LCDIF_D11                            SC_P_SPI0_CS1                      5
+#define SC_P_SPI0_CS0_ADMA_SPI0_CS0                             SC_P_SPI0_CS0                      0
+#define SC_P_SPI0_CS0_ADMA_SAI0_RXD                             SC_P_SPI0_CS0                      1
+#define SC_P_SPI0_CS0_M40_TPM0_CH1                              SC_P_SPI0_CS0                      2
+#define SC_P_SPI0_CS0_M40_GPIO0_IO03                            SC_P_SPI0_CS0                      3
+#define SC_P_SPI0_CS0_LSIO_GPIO1_IO08                           SC_P_SPI0_CS0                      4
+#define SC_P_SPI0_CS0_ADMA_LCDIF_D12                            SC_P_SPI0_CS0                      5
+#define SC_P_ADC_IN1_ADMA_ADC_IN1                               SC_P_ADC_IN1                       0
+#define SC_P_ADC_IN1_M40_I2C0_SDA                               SC_P_ADC_IN1                       1
+#define SC_P_ADC_IN1_M40_GPIO0_IO01                             SC_P_ADC_IN1                       2
+#define SC_P_ADC_IN1_ADMA_I2C0_SDA                              SC_P_ADC_IN1                       3
+#define SC_P_ADC_IN1_LSIO_GPIO1_IO09                            SC_P_ADC_IN1                       4
+#define SC_P_ADC_IN1_ADMA_LCDIF_D13                             SC_P_ADC_IN1                       5
+#define SC_P_ADC_IN0_ADMA_ADC_IN0                               SC_P_ADC_IN0                       0
+#define SC_P_ADC_IN0_M40_I2C0_SCL                               SC_P_ADC_IN0                       1
+#define SC_P_ADC_IN0_M40_GPIO0_IO00                             SC_P_ADC_IN0                       2
+#define SC_P_ADC_IN0_ADMA_I2C0_SCL                              SC_P_ADC_IN0                       3
+#define SC_P_ADC_IN0_LSIO_GPIO1_IO10                            SC_P_ADC_IN0                       4
+#define SC_P_ADC_IN0_ADMA_LCDIF_D14                             SC_P_ADC_IN0                       5
+#define SC_P_ADC_IN3_ADMA_ADC_IN3                               SC_P_ADC_IN3                       0
+#define SC_P_ADC_IN3_M40_UART0_TX                               SC_P_ADC_IN3                       1
+#define SC_P_ADC_IN3_M40_GPIO0_IO03                             SC_P_ADC_IN3                       2
+#define SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0                         SC_P_ADC_IN3                       3
+#define SC_P_ADC_IN3_LSIO_GPIO1_IO11                            SC_P_ADC_IN3                       4
+#define SC_P_ADC_IN3_ADMA_LCDIF_D15                             SC_P_ADC_IN3                       5
+#define SC_P_ADC_IN2_ADMA_ADC_IN2                               SC_P_ADC_IN2                       0
+#define SC_P_ADC_IN2_M40_UART0_RX                               SC_P_ADC_IN2                       1
+#define SC_P_ADC_IN2_M40_GPIO0_IO02                             SC_P_ADC_IN2                       2
+#define SC_P_ADC_IN2_ADMA_ACM_MCLK_IN0                          SC_P_ADC_IN2                       3
+#define SC_P_ADC_IN2_LSIO_GPIO1_IO12                            SC_P_ADC_IN2                       4
+#define SC_P_ADC_IN2_ADMA_LCDIF_D16                             SC_P_ADC_IN2                       5
+#define SC_P_ADC_IN5_ADMA_ADC_IN5                               SC_P_ADC_IN5                       0
+#define SC_P_ADC_IN5_M40_TPM0_CH1                               SC_P_ADC_IN5                       1
+#define SC_P_ADC_IN5_M40_GPIO0_IO05                             SC_P_ADC_IN5                       2
+#define SC_P_ADC_IN5_ADMA_LCDIF_LCDBUSY                         SC_P_ADC_IN5                       3
+#define SC_P_ADC_IN5_LSIO_GPIO1_IO13                            SC_P_ADC_IN5                       4
+#define SC_P_ADC_IN5_ADMA_LCDIF_D17                             SC_P_ADC_IN5                       5
+#define SC_P_ADC_IN4_ADMA_ADC_IN4                               SC_P_ADC_IN4                       0
+#define SC_P_ADC_IN4_M40_TPM0_CH0                               SC_P_ADC_IN4                       1
+#define SC_P_ADC_IN4_M40_GPIO0_IO04                             SC_P_ADC_IN4                       2
+#define SC_P_ADC_IN4_ADMA_LCDIF_LCDRESET                        SC_P_ADC_IN4                       3
+#define SC_P_ADC_IN4_LSIO_GPIO1_IO14                            SC_P_ADC_IN4                       4
+#define SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX                       SC_P_FLEXCAN0_RX                   0
+#define SC_P_FLEXCAN0_RX_ADMA_SAI2_RXC                          SC_P_FLEXCAN0_RX                   1
+#define SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B                       SC_P_FLEXCAN0_RX                   2
+#define SC_P_FLEXCAN0_RX_ADMA_SAI1_TXC                          SC_P_FLEXCAN0_RX                   3
+#define SC_P_FLEXCAN0_RX_LSIO_GPIO1_IO15                        SC_P_FLEXCAN0_RX                   4
+#define SC_P_FLEXCAN0_RX_LSIO_GPIO6_IO08                        SC_P_FLEXCAN0_RX                   5
+#define SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX                       SC_P_FLEXCAN0_TX                   0
+#define SC_P_FLEXCAN0_TX_ADMA_SAI2_RXD                          SC_P_FLEXCAN0_TX                   1
+#define SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B                       SC_P_FLEXCAN0_TX                   2
+#define SC_P_FLEXCAN0_TX_ADMA_SAI1_TXFS                         SC_P_FLEXCAN0_TX                   3
+#define SC_P_FLEXCAN0_TX_LSIO_GPIO1_IO16                        SC_P_FLEXCAN0_TX                   4
+#define SC_P_FLEXCAN0_TX_LSIO_GPIO6_IO09                        SC_P_FLEXCAN0_TX                   5
+#define SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX                       SC_P_FLEXCAN1_RX                   0
+#define SC_P_FLEXCAN1_RX_ADMA_SAI2_RXFS                         SC_P_FLEXCAN1_RX                   1
+#define SC_P_FLEXCAN1_RX_ADMA_FTM_CH2                           SC_P_FLEXCAN1_RX                   2
+#define SC_P_FLEXCAN1_RX_ADMA_SAI1_TXD                          SC_P_FLEXCAN1_RX                   3
+#define SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17                        SC_P_FLEXCAN1_RX                   4
+#define SC_P_FLEXCAN1_RX_LSIO_GPIO6_IO10                        SC_P_FLEXCAN1_RX                   5
+#define SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX                       SC_P_FLEXCAN1_TX                   0
+#define SC_P_FLEXCAN1_TX_ADMA_SAI3_RXC                          SC_P_FLEXCAN1_TX                   1
+#define SC_P_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0                      SC_P_FLEXCAN1_TX                   2
+#define SC_P_FLEXCAN1_TX_ADMA_SAI1_RXD                          SC_P_FLEXCAN1_TX                   3
+#define SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18                        SC_P_FLEXCAN1_TX                   4
+#define SC_P_FLEXCAN1_TX_LSIO_GPIO6_IO11                        SC_P_FLEXCAN1_TX                   5
+#define SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX                       SC_P_FLEXCAN2_RX                   0
+#define SC_P_FLEXCAN2_RX_ADMA_SAI3_RXD                          SC_P_FLEXCAN2_RX                   1
+#define SC_P_FLEXCAN2_RX_ADMA_UART3_RX                          SC_P_FLEXCAN2_RX                   2
+#define SC_P_FLEXCAN2_RX_ADMA_SAI1_RXFS                         SC_P_FLEXCAN2_RX                   3
+#define SC_P_FLEXCAN2_RX_LSIO_GPIO1_IO19                        SC_P_FLEXCAN2_RX                   4
+#define SC_P_FLEXCAN2_RX_LSIO_GPIO6_IO12                        SC_P_FLEXCAN2_RX                   5
+#define SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX                       SC_P_FLEXCAN2_TX                   0
+#define SC_P_FLEXCAN2_TX_ADMA_SAI3_RXFS                         SC_P_FLEXCAN2_TX                   1
+#define SC_P_FLEXCAN2_TX_ADMA_UART3_TX                          SC_P_FLEXCAN2_TX                   2
+#define SC_P_FLEXCAN2_TX_ADMA_SAI1_RXC                          SC_P_FLEXCAN2_TX                   3
+#define SC_P_FLEXCAN2_TX_LSIO_GPIO1_IO20                        SC_P_FLEXCAN2_TX                   4
+#define SC_P_FLEXCAN2_TX_LSIO_GPIO6_IO13                        SC_P_FLEXCAN2_TX                   5
+#define SC_P_UART0_RX_ADMA_UART0_RX                             SC_P_UART0_RX                      0
+#define SC_P_UART0_RX_ADMA_MQS_R                                SC_P_UART0_RX                      1
+#define SC_P_UART0_RX_ADMA_FLEXCAN0_RX                          SC_P_UART0_RX                      2
+#define SC_P_UART0_RX_SCU_UART0_RX                              SC_P_UART0_RX                      3
+#define SC_P_UART0_RX_LSIO_GPIO1_IO21                           SC_P_UART0_RX                      4
+#define SC_P_UART0_RX_LSIO_GPIO6_IO14                           SC_P_UART0_RX                      5
+#define SC_P_UART0_TX_ADMA_UART0_TX                             SC_P_UART0_TX                      0
+#define SC_P_UART0_TX_ADMA_MQS_L                                SC_P_UART0_TX                      1
+#define SC_P_UART0_TX_ADMA_FLEXCAN0_TX                          SC_P_UART0_TX                      2
+#define SC_P_UART0_TX_SCU_UART0_TX                              SC_P_UART0_TX                      3
+#define SC_P_UART0_TX_LSIO_GPIO1_IO22                           SC_P_UART0_TX                      4
+#define SC_P_UART0_TX_LSIO_GPIO6_IO15                           SC_P_UART0_TX                      5
+#define SC_P_UART2_TX_ADMA_UART2_TX                             SC_P_UART2_TX                      0
+#define SC_P_UART2_TX_ADMA_FTM_CH1                              SC_P_UART2_TX                      1
+#define SC_P_UART2_TX_ADMA_FLEXCAN1_TX                          SC_P_UART2_TX                      2
+#define SC_P_UART2_TX_LSIO_GPIO1_IO23                           SC_P_UART2_TX                      4
+#define SC_P_UART2_TX_LSIO_GPIO6_IO16                           SC_P_UART2_TX                      5
+#define SC_P_UART2_RX_ADMA_UART2_RX                             SC_P_UART2_RX                      0
+#define SC_P_UART2_RX_ADMA_FTM_CH0                              SC_P_UART2_RX                      1
+#define SC_P_UART2_RX_ADMA_FLEXCAN1_RX                          SC_P_UART2_RX                      2
+#define SC_P_UART2_RX_LSIO_GPIO1_IO24                           SC_P_UART2_RX                      4
+#define SC_P_UART2_RX_LSIO_GPIO6_IO17                           SC_P_UART2_RX                      5
+#define SC_P_JTAG_TRST_B_SCU_JTAG_TRST_B                        SC_P_JTAG_TRST_B                   0
+#define SC_P_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT                     SC_P_JTAG_TRST_B                   1
+#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL                      SC_P_PMIC_I2C_SCL                  0
+#define SC_P_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON            SC_P_PMIC_I2C_SCL                  1
+#define SC_P_PMIC_I2C_SCL_LSIO_GPIO2_IO01                       SC_P_PMIC_I2C_SCL                  4
+#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA                      SC_P_PMIC_I2C_SDA                  0
+#define SC_P_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON            SC_P_PMIC_I2C_SDA                  1
+#define SC_P_PMIC_I2C_SDA_LSIO_GPIO2_IO02                       SC_P_PMIC_I2C_SDA                  4
+#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B                      SC_P_PMIC_INT_B                    0
+#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00                        SC_P_SCU_GPIO0_00                  0
+#define SC_P_SCU_GPIO0_00_SCU_UART0_RX                          SC_P_SCU_GPIO0_00                  1
+#define SC_P_SCU_GPIO0_00_M40_UART0_RX                          SC_P_SCU_GPIO0_00                  2
+#define SC_P_SCU_GPIO0_00_ADMA_UART3_RX                         SC_P_SCU_GPIO0_00                  3
+#define SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03                       SC_P_SCU_GPIO0_00                  4
+#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01                        SC_P_SCU_GPIO0_01                  0
+#define SC_P_SCU_GPIO0_01_SCU_UART0_TX                          SC_P_SCU_GPIO0_01                  1
+#define SC_P_SCU_GPIO0_01_M40_UART0_TX                          SC_P_SCU_GPIO0_01                  2
+#define SC_P_SCU_GPIO0_01_ADMA_UART3_TX                         SC_P_SCU_GPIO0_01                  3
+#define SC_P_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT                    SC_P_SCU_GPIO0_01                  4
+#define SC_P_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY              SC_P_SCU_PMIC_STANDBY              0
+#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1                  SC_P_SCU_BOOT_MODE1                0
+#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0                  SC_P_SCU_BOOT_MODE0                0
+#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2                  SC_P_SCU_BOOT_MODE2                0
+#define SC_P_SCU_BOOT_MODE2_SCU_DSC_RTC_CLOCK_OUTPUT_32K        SC_P_SCU_BOOT_MODE2                1
+#define SC_P_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN                SC_P_SNVS_TAMPER_OUT1              4
+#define SC_P_SNVS_TAMPER_OUT1_LSIO_GPIO6_IO19_IN                SC_P_SNVS_TAMPER_OUT1              5
+#define SC_P_SNVS_TAMPER_OUT2_LSIO_GPIO2_IO06_IN                SC_P_SNVS_TAMPER_OUT2              4
+#define SC_P_SNVS_TAMPER_OUT2_LSIO_GPIO6_IO20_IN                SC_P_SNVS_TAMPER_OUT2              5
+#define SC_P_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC                     SC_P_SNVS_TAMPER_OUT3              2
+#define SC_P_SNVS_TAMPER_OUT3_LSIO_GPIO2_IO07_IN                SC_P_SNVS_TAMPER_OUT3              4
+#define SC_P_SNVS_TAMPER_OUT3_LSIO_GPIO6_IO21_IN                SC_P_SNVS_TAMPER_OUT3              5
+#define SC_P_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD                     SC_P_SNVS_TAMPER_OUT4              2
+#define SC_P_SNVS_TAMPER_OUT4_LSIO_GPIO2_IO08_IN                SC_P_SNVS_TAMPER_OUT4              4
+#define SC_P_SNVS_TAMPER_OUT4_LSIO_GPIO6_IO22_IN                SC_P_SNVS_TAMPER_OUT4              5
+#define SC_P_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS                     SC_P_SNVS_TAMPER_IN0               2
+#define SC_P_SNVS_TAMPER_IN0_LSIO_GPIO2_IO09_IN                 SC_P_SNVS_TAMPER_IN0               4
+#define SC_P_SNVS_TAMPER_IN0_LSIO_GPIO6_IO23_IN                 SC_P_SNVS_TAMPER_IN0               5
+#define SC_P_SNVS_TAMPER_IN1_ADMA_SAI3_RXC                      SC_P_SNVS_TAMPER_IN1               2
+#define SC_P_SNVS_TAMPER_IN1_LSIO_GPIO2_IO10_IN                 SC_P_SNVS_TAMPER_IN1               4
+#define SC_P_SNVS_TAMPER_IN1_LSIO_GPIO6_IO24_IN                 SC_P_SNVS_TAMPER_IN1               5
+#define SC_P_SNVS_TAMPER_IN2_ADMA_SAI3_RXD                      SC_P_SNVS_TAMPER_IN2               2
+#define SC_P_SNVS_TAMPER_IN2_LSIO_GPIO2_IO11_IN                 SC_P_SNVS_TAMPER_IN2               4
+#define SC_P_SNVS_TAMPER_IN2_LSIO_GPIO6_IO25_IN                 SC_P_SNVS_TAMPER_IN2               5
+#define SC_P_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS                     SC_P_SNVS_TAMPER_IN3               2
+#define SC_P_SNVS_TAMPER_IN3_LSIO_GPIO2_IO12_IN                 SC_P_SNVS_TAMPER_IN3               4
+#define SC_P_SNVS_TAMPER_IN3_LSIO_GPIO6_IO26_IN                 SC_P_SNVS_TAMPER_IN3               5
+#define SC_P_SPI1_SCK_ADMA_I2C2_SDA                             SC_P_SPI1_SCK                      2
+#define SC_P_SPI1_SCK_ADMA_SPI1_SCK                             SC_P_SPI1_SCK                      3
+#define SC_P_SPI1_SCK_LSIO_GPIO3_IO00                           SC_P_SPI1_SCK                      4
+#define SC_P_SPI1_SDO_ADMA_I2C2_SCL                             SC_P_SPI1_SDO                      2
+#define SC_P_SPI1_SDO_ADMA_SPI1_SDO                             SC_P_SPI1_SDO                      3
+#define SC_P_SPI1_SDO_LSIO_GPIO3_IO01                           SC_P_SPI1_SDO                      4
+#define SC_P_SPI1_SDI_ADMA_I2C3_SCL                             SC_P_SPI1_SDI                      2
+#define SC_P_SPI1_SDI_ADMA_SPI1_SDI                             SC_P_SPI1_SDI                      3
+#define SC_P_SPI1_SDI_LSIO_GPIO3_IO02                           SC_P_SPI1_SDI                      4
+#define SC_P_SPI1_CS0_ADMA_I2C3_SDA                             SC_P_SPI1_CS0                      2
+#define SC_P_SPI1_CS0_ADMA_SPI1_CS0                             SC_P_SPI1_CS0                      3
+#define SC_P_SPI1_CS0_LSIO_GPIO3_IO03                           SC_P_SPI1_CS0                      4
+#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1                     SC_P_QSPI0A_DATA1                  0
+#define SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10                       SC_P_QSPI0A_DATA1                  4
+#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0                     SC_P_QSPI0A_DATA0                  0
+#define SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09                       SC_P_QSPI0A_DATA0                  4
+#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3                     SC_P_QSPI0A_DATA3                  0
+#define SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12                       SC_P_QSPI0A_DATA3                  4
+#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2                     SC_P_QSPI0A_DATA2                  0
+#define SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11                       SC_P_QSPI0A_DATA2                  4
+#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B                     SC_P_QSPI0A_SS0_B                  0
+#define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14                       SC_P_QSPI0A_SS0_B                  4
+#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS                         SC_P_QSPI0A_DQS                    0
+#define SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13                         SC_P_QSPI0A_DQS                    4
+#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK                       SC_P_QSPI0A_SCLK                   0
+#define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16                        SC_P_QSPI0A_SCLK                   4
+#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK                       SC_P_QSPI0B_SCLK                   0
+#define SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17                        SC_P_QSPI0B_SCLK                   4
+#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS                         SC_P_QSPI0B_DQS                    0
+#define SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22                         SC_P_QSPI0B_DQS                    4
+#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1                     SC_P_QSPI0B_DATA1                  0
+#define SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19                       SC_P_QSPI0B_DATA1                  4
+#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0                     SC_P_QSPI0B_DATA0                  0
+#define SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18                       SC_P_QSPI0B_DATA0                  4
+#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3                     SC_P_QSPI0B_DATA3                  0
+#define SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21                       SC_P_QSPI0B_DATA3                  4
+#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2                     SC_P_QSPI0B_DATA2                  0
+#define SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20                       SC_P_QSPI0B_DATA2                  4
+#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B                     SC_P_QSPI0B_SS0_B                  0
+#define SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23                       SC_P_QSPI0B_SS0_B                  4
+#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0A_SS1_B                     SC_P_QSPI0B_SS0_B                  5
+/*@}*/
+
+/*!
+ * @name Fake Pad Mux Definitions
+ * format: name padid 0
+ */
+/*@{*/
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD          SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP         0
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO_PAD               SC_P_COMP_CTL_GPIO_3V3_USB3IO              0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_PAD          SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0         0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD          SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP         0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD      SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0     0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD      SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1     0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD           SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT          0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD          SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB         0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD          SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK         0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD          SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT         0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD           SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH          0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD_PAD          SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD         0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A_PAD           SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A          0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B_PAD           SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B          0
+/*@}*/
+
+#endif				/* SC_PADS_H */
diff --git a/include/dt-bindings/pinctrl/pads-imx8qm.h b/include/dt-bindings/pinctrl/pads-imx8qm.h
index e980fd55ede..5416669f035 100644
--- a/include/dt-bindings/pinctrl/pads-imx8qm.h
+++ b/include/dt-bindings/pinctrl/pads-imx8qm.h
@@ -275,13 +275,11 @@
 #define SC_P_ENET1_RGMII_RXD2                    266	/* CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */
 #define SC_P_ENET1_RGMII_RXD3                    267	/* CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */
 #define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA    268	/*  */
-/*@}*/
 
-/*!
- * @name Pad Mux Definitions
+/*
+ * Pad Mux Definitions
  * format: name padid padmux
  */
-/*@{*/
 #define SC_P_SIM0_CLK_DMA_SIM0_CLK                              SC_P_SIM0_CLK                      0
 #define SC_P_SIM0_CLK_LSIO_GPIO0_IO00                           SC_P_SIM0_CLK                      3
 #define SC_P_SIM0_RST_DMA_SIM0_RST                              SC_P_SIM0_RST                      0
@@ -955,7 +953,31 @@
 #define SC_P_ENET1_RGMII_RXD3_DMA_UART3_RX                      SC_P_ENET1_RGMII_RXD3              1
 #define SC_P_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK                    SC_P_ENET1_RGMII_RXD3              2
 #define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21                   SC_P_ENET1_RGMII_RXD3              3
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB              0
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD               SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA              0
 
-#endif				/* SC_PADS_H */
+/*
+ * Fake Pad Mux Definitions
+ * format: name padid 0
+ */
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM_PAD              SC_P_COMP_CTL_GPIO_1V8_3V3_SIM             0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD           SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH          0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_PAD         SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO        0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_PAD      SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO     0
+#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO_PAD             SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO            0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD          SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB         0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC_PAD          SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC         0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD          SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT         0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_PAD          SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT         0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_PAD          SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR         0
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO_PAD               SC_P_COMP_CTL_GPIO_3V3_USB3IO              0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD          SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP         0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD           SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT          0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1_PAD            SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1           0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0_PAD            SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0           0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD          SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP         0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX_PAD           SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX          0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2_PAD            SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2           0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3_PAD            SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3           0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD       SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB      0
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD       SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA      0
+
+#endif /* SC_PADS_H */
diff --git a/include/dt-bindings/power/imx8ulp-power.h b/include/dt-bindings/power/imx8ulp-power.h
new file mode 100644
index 00000000000..a556b2e96df
--- /dev/null
+++ b/include/dt-bindings/power/imx8ulp-power.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ *  Copyright 2021 NXP
+ */
+
+#ifndef __DT_BINDINGS_IMX8ULP_POWER_H__
+#define __DT_BINDINGS_IMX8ULP_POWER_H__
+
+#define IMX8ULP_PD_DMA1		0
+#define IMX8ULP_PD_FLEXSPI2	1
+#define IMX8ULP_PD_USB0		2
+#define IMX8ULP_PD_USDHC0	3
+#define IMX8ULP_PD_USDHC1	4
+#define IMX8ULP_PD_USDHC2_USB1	5
+#define IMX8ULP_PD_DCNANO	6
+#define IMX8ULP_PD_EPDC		7
+#define IMX8ULP_PD_DMA2		8
+#define IMX8ULP_PD_GPU2D	9
+#define IMX8ULP_PD_GPU3D	10
+#define IMX8ULP_PD_HIFI4	11
+#define IMX8ULP_PD_ISI		12
+#define IMX8ULP_PD_MIPI_CSI	13
+#define IMX8ULP_PD_MIPI_DSI	14
+#define IMX8ULP_PD_PXP		15
+
+#endif
diff --git a/include/dt-bindings/power/imx93-power.h b/include/dt-bindings/power/imx93-power.h
new file mode 100644
index 00000000000..6e9e0ccb906
--- /dev/null
+++ b/include/dt-bindings/power/imx93-power.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ *  Copyright 2022 NXP
+ */
+
+#ifndef __DT_BINDINGS_IMX93_POWER_H__
+#define __DT_BINDINGS_IMX93_POWER_H__
+
+#define IMX93_POWER_DOMAIN_MLMIX		0
+#define IMX93_POWER_DOMAIN_MEDIAMIX		1
+
+#define IMX93_MEDIABLK_PD_MIPI_DSI		0
+#define IMX93_MEDIABLK_PD_MIPI_CSI		1
+#define IMX93_MEDIABLK_PD_PXP			2
+#define IMX93_MEDIABLK_PD_LCDIF			3
+#define IMX93_MEDIABLK_PD_ISI			4
+
+#endif
diff --git a/include/dt-bindings/reset/imx8mm-dispmix.h b/include/dt-bindings/reset/imx8mm-dispmix.h
new file mode 100644
index 00000000000..3af137b1bfe
--- /dev/null
+++ b/include/dt-bindings/reset/imx8mm-dispmix.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __IMX8MM_DISPMIX_H__
+#define __IMX8MM_DISPMIX_H__
+
+/* DISPMIX soft reset */
+#define IMX8MM_CSI_BRIDGE_CHIP_RESET			0
+#define IMX8MM_CSI_BRIDGE_IPG_HARD_ASYNC_RESET		1
+#define IMX8MM_CSI_BRIDGE_CSI_HRESET			2
+#define IMX8MM_CAMERA_PIXEL_RESET			3
+#define IMX8MM_MIPI_CSI_I_PRESET			4
+#define IMX8MM_MIPI_DSI_I_PRESET			5
+#define IMX8MM_BUS_RSTN_BLK_SYNC			6
+#define IMX8MM_DISPMIX_SFT_RSTN_NUM			7
+
+/* DISPMIX clock soft enable */
+#define IMX8MM_CSI_BRIDGE_CSI_HCLK_EN			0
+#define IMX8MM_CSI_BRIDGE_SPU_CLK_EN			1
+#define IMX8MM_CSI_BRIDGE_MEM_WRAPPER_CLK_EN		2
+#define IMX8MM_CSI_BRIDGE_IPG_CLK_EN			3
+#define IMX8MM_CSI_BRIDGE_IPG_CLK_S_EN			4
+#define IMX8MM_CSI_BRIDGE_IPG_CLK_S_RAW_EN		5
+#define IMX8MM_LCDIF_APB_CLK_EN				6
+#define IMX8MM_LCDIF_PIXEL_CLK_EN			7
+#define IMX8MM_MIPI_DSI_PCLK_EN				8
+#define IMX8MM_MIPI_DSI_CLKREF_EN			9
+#define IMX8MM_MIPI_CSI_ACLK_EN				10
+#define IMX8MM_MIPI_CSI_PCLK_EN				11
+#define IMX8MM_BUS_BLK_CLK_EN				12
+#define IMX8MM_DISPMIX_CLK_EN_NUM			13
+
+/* MIPI reset */
+#define IMX8MM_MIPI_S_RESET				0
+#define IMX8MM_MIPI_M_RESET				1
+#define IMX8MM_MIPI_RESET_NUM				2
+
+#endif
diff --git a/include/dt-bindings/reset/imx8mn-dispmix.h b/include/dt-bindings/reset/imx8mn-dispmix.h
new file mode 100644
index 00000000000..8703ebe7d4b
--- /dev/null
+++ b/include/dt-bindings/reset/imx8mn-dispmix.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __IMX8MN_DISPMIX_H__
+#define __IMX8MN_DISPMIX_H__
+
+/* DISPMIX soft reset */
+#define IMX8MN_MIPI_DSI_PCLK_RESET			0
+#define IMX8MN_MIPI_DSI_CLKREF_RESET			1
+#define IMX8MN_MIPI_CSI_PCLK_RESET			2
+#define IMX8MN_MIPI_CSI_ACLK_RESET			3
+#define IMX8MN_LCDIF_PIXEL_CLK_RESET			4
+#define IMX8MN_LCDIF_APB_CLK_RESET			5
+#define IMX8MN_ISI_PROC_CLK_RESET			6
+#define IMX8MN_ISI_APB_CLK_RESET			7
+#define IMX8MN_BUS_BLK_CLK_RESET			8
+#define IMX8MN_DISPMIX_SFT_RSTN_NUM			9
+
+/* DISPMIX clock soft enable */
+#define IMX8MN_MIPI_DSI_PCLK_EN				0
+#define IMX8MN_MIPI_DSI_CLKREF_EN			1
+#define IMX8MN_MIPI_CSI_PCLK_EN				2
+#define IMX8MN_MIPI_CSI_ACLK_EN				3
+#define IMX8MN_LCDIF_PIXEL_CLK_EN			4
+#define IMX8MN_LCDIF_APB_CLK_EN				5
+#define IMX8MN_ISI_PROC_CLK_EN				6
+#define IMX8MN_ISI_APB_CLK_EN				7
+#define IMX8MN_BUS_BLK_CLK_EN				8
+#define IMX8MN_DISPMIX_CLK_EN_NUM			9
+
+/* MIPI reset */
+#define IMX8MN_MIPI_S_RESET				0
+#define IMX8MN_MIPI_M_RESET				1
+#define IMX8MN_MIPI_RESET_NUM				2
+
+#endif
diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h
new file mode 100644
index 00000000000..113a9a0e835
--- /dev/null
+++ b/include/dt-bindings/reset/imx8mp-reset.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef DT_BINDING_RESET_IMX8MP_H
+#define DT_BINDING_RESET_IMX8MP_H
+
+#define IMX8MP_RESET_A53_CORE_POR_RESET0	0
+#define IMX8MP_RESET_A53_CORE_POR_RESET1	1
+#define IMX8MP_RESET_A53_CORE_POR_RESET2	2
+#define IMX8MP_RESET_A53_CORE_POR_RESET3	3
+#define IMX8MP_RESET_A53_CORE_RESET0		4
+#define IMX8MP_RESET_A53_CORE_RESET1		5
+#define IMX8MP_RESET_A53_CORE_RESET2		6
+#define IMX8MP_RESET_A53_CORE_RESET3		7
+#define IMX8MP_RESET_A53_DBG_RESET0		8
+#define IMX8MP_RESET_A53_DBG_RESET1		9
+#define IMX8MP_RESET_A53_DBG_RESET2		10
+#define IMX8MP_RESET_A53_DBG_RESET3		11
+#define IMX8MP_RESET_A53_ETM_RESET0		12
+#define IMX8MP_RESET_A53_ETM_RESET1		13
+#define IMX8MP_RESET_A53_ETM_RESET2		14
+#define IMX8MP_RESET_A53_ETM_RESET3		15
+#define IMX8MP_RESET_A53_SOC_DBG_RESET		16
+#define IMX8MP_RESET_A53_L2RESET		17
+#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST	18
+#define IMX8MP_RESET_OTG1_PHY_RESET		19
+#define IMX8MP_RESET_OTG2_PHY_RESET		20
+#define IMX8MP_RESET_SUPERMIX_RESET		21
+#define IMX8MP_RESET_AUDIOMIX_RESET		22
+#define IMX8MP_RESET_MLMIX_RESET		23
+#define IMX8MP_RESET_PCIEPHY			24
+#define IMX8MP_RESET_PCIEPHY_PERST		25
+#define IMX8MP_RESET_PCIE_CTRL_APPS_EN		26
+#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF	27
+#define IMX8MP_RESET_HDMI_PHY_APB_RESET		28
+#define IMX8MP_RESET_MEDIA_RESET		29
+#define IMX8MP_RESET_GPU2D_RESET		30
+#define IMX8MP_RESET_GPU3D_RESET		31
+#define IMX8MP_RESET_GPU_RESET			32
+#define IMX8MP_RESET_VPU_RESET			33
+#define IMX8MP_RESET_VPU_G1_RESET		34
+#define IMX8MP_RESET_VPU_G2_RESET		35
+#define IMX8MP_RESET_VPUVC8KE_RESET		36
+#define IMX8MP_RESET_NOC_RESET			37
+#define IMX8MP_RESET_PCIE_CTRL_APPS_CLK_REQ	38
+
+#define IMX8MP_RESET_NUM			39
+
+#define IMX8MP_AUDIO_BLK_CTRL_EARC_RESET	0
+#define IMX8MP_AUDIO_BLK_CTRL_EARC_PHY_RESET	1
+
+#define IMX8MP_AUDIO_BLK_CTRL_RESET_NUM		2
+
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_DSI_PCLK	0
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_DSI_CLKREF	1
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI_PCLK	2
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI_ACLK	3
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF_PIXEL		4
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF_APB		5
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISI_PROC		6
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISI_APB		7
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_BUS_BLK		8
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI2_PCLK	9
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI2_ACLK	10
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF2_PIXEL	11
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF2_APB		12
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP1_COR		13
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP1_AXI		14
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP1_AHB		15
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP0_COR		16
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP0_AXI		17
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP0_AHB		18
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_DWE_COR		19
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_DWE_AXI		20
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_DWE_AHB		21
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_DSI2		22
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF_AXI		23
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF2_AXI		24
+
+#define IMX8MP_MEDIA_BLK_CTRL_RESET_NUM			25
+
+#define IMX8MP_HDMI_BLK_CTRL_HDMI_TX_RESET		0
+#define IMX8MP_HDMI_BLK_CTRL_HDMI_PHY_RESET		1
+#define IMX8MP_HDMI_BLK_CTRL_HDMI_PAI_RESET		2
+#define IMX8MP_HDMI_BLK_CTRL_HDMI_PVI_RESET		3
+#define IMX8MP_HDMI_BLK_CTRL_HDMI_TRNG_RESET		4
+#define IMX8MP_HDMI_BLK_CTRL_IRQ_STEER_RESET		5
+#define IMX8MP_HDMI_BLK_CTRL_HDMI_HDCP_RESET		6
+#define IMX8MP_HDMI_BLK_CTRL_LCDIF_RESET		7
+
+#define IMX8MP_HDMI_BLK_CTRL_RESET_NUM			8
+
+
+#endif
diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h
index 9a301082d36..2a04e9cffde 100755..100644
--- a/include/dt-bindings/reset/imx8mq-reset.h
+++ b/include/dt-bindings/reset/imx8mq-reset.h
@@ -58,7 +58,9 @@
 #define IMX8MQ_RESET_DDRC2_PRST			47	/* i.MX8MM does NOT support */
 #define IMX8MQ_RESET_DDRC2_CORE_RESET		48	/* i.MX8MM does NOT support */
 #define IMX8MQ_RESET_DDRC2_PHY_RESET		49	/* i.MX8MM does NOT support */
+#define IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ	50	/* i.MX8M PCIe CTL CLK REQ */
+#define IMX8MQ_RESET_PCIE2_CTRL_APPS_CLK_REQ	51	/* i.MX8M PCIe CTL CLK REQ */
 
-#define IMX8MQ_RESET_NUM			50
+#define IMX8MQ_RESET_NUM			52
 
 #endif
diff --git a/include/dt-bindings/reset/imx8ulp-pcc-reset.h b/include/dt-bindings/reset/imx8ulp-pcc-reset.h
new file mode 100644
index 00000000000..e99a4735c3c
--- /dev/null
+++ b/include/dt-bindings/reset/imx8ulp-pcc-reset.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef DT_BINDING_PCC_RESET_IMX8ULP_H
+#define DT_BINDING_PCC_RESET_IMX8ULP_H
+
+/* PCC3 */
+#define PCC3_WDOG3_SWRST	0
+#define PCC3_WDOG4_SWRST	1
+#define PCC3_LPIT1_SWRST	2
+#define PCC3_TPM4_SWRST		3
+#define PCC3_TPM5_SWRST		4
+#define PCC3_FLEXIO1_SWRST	5
+#define PCC3_I3C2_SWRST		6
+#define PCC3_LPI2C4_SWRST	7
+#define PCC3_LPI2C5_SWRST	8
+#define PCC3_LPUART4_SWRST	9
+#define PCC3_LPUART5_SWRST	10
+#define PCC3_LPSPI4_SWRST	11
+#define PCC3_LPSPI5_SWRST	12
+
+/* PCC4 */
+#define PCC4_FLEXSPI2_SWRST	0
+#define PCC4_TPM6_SWRST		1
+#define PCC4_TPM7_SWRST		2
+#define PCC4_LPI2C6_SWRST	3
+#define PCC4_LPI2C7_SWRST	4
+#define PCC4_LPUART6_SWRST	5
+#define PCC4_LPUART7_SWRST	6
+#define PCC4_SAI4_SWRST		7
+#define PCC4_SAI5_SWRST		8
+#define PCC4_USDHC0_SWRST	9
+#define PCC4_USDHC1_SWRST	10
+#define PCC4_USDHC2_SWRST	11
+#define PCC4_USB0_SWRST		12
+#define PCC4_USB0_PHY_SWRST	13
+#define PCC4_USB1_SWRST		14
+#define PCC4_USB1_PHY_SWRST	15
+#define PCC4_ENET_SWRST		16
+
+/* PCC5 */
+#define PCC5_TPM8_SWRST		0
+#define PCC5_SAI6_SWRST		1
+#define PCC5_SAI7_SWRST		2
+#define PCC5_SPDIF_SWRST	3
+#define PCC5_ISI_SWRST		4
+#define PCC5_CSI_REGS_SWRST	5
+#define PCC5_CSI_SWRST		6
+#define PCC5_DSI_SWRST		7
+#define PCC5_WDOG5_SWRST	8
+#define PCC5_EPDC_SWRST		9
+#define PCC5_PXP_SWRST		10
+#define PCC5_GPU2D_SWRST	11
+#define PCC5_GPU3D_SWRST	12
+#define PCC5_DC_NANO_SWRST	13
+
+#endif /*DT_BINDING_RESET_IMX8ULP_H */
diff --git a/include/dt-bindings/reset/imx8ulp-sim-reset.h b/include/dt-bindings/reset/imx8ulp-sim-reset.h
new file mode 100644
index 00000000000..b6b752fb1dc
--- /dev/null
+++ b/include/dt-bindings/reset/imx8ulp-sim-reset.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef DT_BINDING_RESET_IMX8ULP_SIM_H
+#define DT_BINDING_RESET_IMX8ULP_SIM_H
+
+#define IMX8ULP_SIM_RESET_MIPI_DSI_RST_DPI_N	0
+#define IMX8ULP_SIM_RESET_MIPI_DSI_RST_ESC_N	1
+#define IMX8ULP_SIM_RESET_MIPI_DSI_RST_BYTE_N	2
+
+#define IMX8ULP_SIM_RESET_NUM			3
+
+#endif
diff --git a/include/dt-bindings/soc/imx8_hsio.h b/include/dt-bindings/soc/imx8_hsio.h
new file mode 100644
index 00000000000..a237ceb8262
--- /dev/null
+++ b/include/dt-bindings/soc/imx8_hsio.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_IMX8_HSIO_H
+#define __DT_BINDINGS_IMX8_HSIO_H
+
+/*
+ * imx8qm hsio has pciea, pcieb and sata modules, and hsio
+ * can be configured to the following different work modes.
+ * 1 - pciea 2 lanes and one sata ahci port.
+ * 2 - pciea 1 lane, pcieb 1 lane and one sata ahci port.
+ * 3 - pciea 2 lanes, pcieb 1 lane.
+ * Choose one mode, refer to the exact hardware board design.
+ */
+#define		PCIEAX2SATA		1
+#define		PCIEAX1PCIEBX1SATA	2
+#define		PCIEAX2PCIEBX1		3
+
+#endif /* __DT_BINDINGS_IMX8_HSIO_H */
+
diff --git a/include/dt-bindings/soc/imx8_pd.h b/include/dt-bindings/soc/imx8_pd.h
index 682b608eef8..966d971daed 100644
--- a/include/dt-bindings/soc/imx8_pd.h
+++ b/include/dt-bindings/soc/imx8_pd.h
@@ -55,6 +55,7 @@
 #define PD_DMA_CAN_2                dma_flexcan2
 #define PD_DMA_PWM_0                dma_pwm0
 #define PD_DMA_LCD_0                dma_lcd0
+#define PD_DMA_ELCDIF_PLL           dma_elcdif_pll
 
 #define PD_HSIO                     hsio_power_domain
 #define PD_HSIO_PCIE_A              hsio_pcie0
@@ -92,6 +93,10 @@
 #define PD_LSIO_PWM_5               lsio_pwm5
 #define PD_LSIO_PWM_6               lsio_pwm6
 #define PD_LSIO_PWM_7               lsio_pwm7
+#define PD_LSIO_MU5A                lsio_mu5a
+#define PD_LSIO_MU6A                lsio_mu6a
+#define PD_LSIO_MU8A                lsio_mu8a
+#define PD_LSIO_MU9A                lsio_mu9a
 
 #define PD_CONN                     connectivity_power_domain
 #define PD_CONN_SDHC_0              conn_sdhc0
@@ -135,7 +140,7 @@
 #define PD_AUD_GPT_10               audio_gpt10
 #define PD_AUD_AMIX                 audio_amix
 #define PD_AUD_MQS_0                audio_mqs0
-#define PD_AUD_HIFI                 audio_hifi
+#define PD_AUD_DSP                  audio_dsp
 #define PD_AUD_OCRAM                audio_ocram
 #define PD_AUD_MCLK_OUT_0           audio_mclkout0
 #define PD_AUD_MCLK_OUT_1           audio_mclkout1
@@ -167,22 +172,39 @@
 
 #define PD_MIPI_CSI0                mipi_csi0_power_domain
 #define PD_MIPI_CSI0_PWM            mipi_csi0_pwm
-#define PD_MIPI_CSI0_I2C            mipi_csi0_i2c
+#define PD_MIPI_CSI0_I2C0           mipi_csi0_i2c0
 #define PD_MIPI_CSI1                mipi_csi1_power_domain
 #define PD_MIPI_CSI1_PWM_0          mipi_csi1_pwm
-#define PD_MIPI_CSI1_I2C_0          mipi_csi1_i2c
+#define PD_MIPI_CSI1_I2C0           mipi_csi1_i2c0
+
+#define PD_PARALLEL_CSI             parallel_csi_power_domain
+#define PD_PARALLEL_CSI_I2C         parallel_csi_i2c
+#define PD_PARALLEL_CSI_PWM         parallel_csi_pwm
+#define PD_PARALLEL_CSI_PLL         parallel_csi_pll
 
 #define PD_HDMI                     hdmi_power_domain
+#define PD_HDMI_PLL_0               hdmi_pll0
+#define PD_HDMI_PLL_1               hdmi_pll1
 #define PD_HDMI_I2C_0               hdmi_i2c
+#define PD_HDMI_I2S_0               hdmi_i2s
 #define PD_HDMI_PWM_0               hdmi_pwm
 #define PD_HDMI_GPIO_0              hdmi_gpio
 
 #define PD_HDMI_RX                  hdmi_rx_power_domain
+#define PD_HDMI_RX_BYPASS           hdmi_rx_bypass
 #define PD_HDMI_RX_I2C              hdmi_rx_i2c
 #define PD_HDMI_RX_PWM              hdmi_rx_pwm
 
 #define PD_CM40                     cm40_power_domain
 #define PD_CM40_I2C                 cm40_i2c
 #define PD_CM40_INTMUX              cm40_intmux
+#define PD_CM41                     cm41_power_domain
+#define PD_CM41_I2C                 cm41_i2c
+#define PD_CM41_INTMUX              cm41_intmux
+
+#define PD_CAAM                     caam_power_domain
+#define PD_CAAM_JR1                 caam_job_ring1
+#define PD_CAAM_JR2                 caam_job_ring2
+#define PD_CAAM_JR3                 caam_job_ring3
 
 #endif /* __DT_BINDINGS_IMX8_PD_H */
diff --git a/include/dt-bindings/soc/imx_rsrc.h b/include/dt-bindings/soc/imx_rsrc.h
index fb6878f6e24..da4b7b88791 100644
--- a/include/dt-bindings/soc/imx_rsrc.h
+++ b/include/dt-bindings/soc/imx_rsrc.h
@@ -34,15 +34,15 @@
 #define SC_R_DC_0_BLIT1                 20
 #define SC_R_DC_0_BLIT2                 21
 #define SC_R_DC_0_BLIT_OUT              22
-#define SC_R_DC_0_CAPTURE0              23
-#define SC_R_DC_0_CAPTURE1              24
+#define SC_R_PERF                       23
+#define SC_R_USB_1_PHY                  24
 #define SC_R_DC_0_WARP                  25
-#define SC_R_DC_0_INTEGRAL0             26
-#define SC_R_DC_0_INTEGRAL1             27
+#define SC_R_V2X_MU_0                   26
+#define SC_R_V2X_MU_1                   27
 #define SC_R_DC_0_VIDEO0                28
 #define SC_R_DC_0_VIDEO1                29
 #define SC_R_DC_0_FRAC0                 30
-#define SC_R_DC_0_FRAC1                 31
+#define SC_R_V2X_MU_2                   31
 #define SC_R_DC_0                       32
 #define SC_R_GPU_2_PID0                 33
 #define SC_R_DC_0_PLL_0                 34
@@ -51,17 +51,17 @@
 #define SC_R_DC_1_BLIT1                 37
 #define SC_R_DC_1_BLIT2                 38
 #define SC_R_DC_1_BLIT_OUT              39
-#define SC_R_DC_1_CAPTURE0              40
-#define SC_R_DC_1_CAPTURE1              41
+#define SC_R_V2X_MU_3                   40
+#define SC_R_V2X_MU_4                   41
 #define SC_R_DC_1_WARP                  42
-#define SC_R_DC_1_INTEGRAL0             43
-#define SC_R_DC_1_INTEGRAL1             44
+#define SC_R_TBU_CTL                    43
+#define SC_R_SECVIO                     44
 #define SC_R_DC_1_VIDEO0                45
 #define SC_R_DC_1_VIDEO1                46
 #define SC_R_DC_1_FRAC0                 47
-#define SC_R_DC_1_FRAC1                 48
+#define SC_R_UNUSED13                   48
 #define SC_R_DC_1                       49
-#define SC_R_GPU_3_PID0                 50
+#define SC_R_UNUSED14                   50
 #define SC_R_DC_1_PLL_0                 51
 #define SC_R_DC_1_PLL_1                 52
 #define SC_R_SPI_0                      53
@@ -151,10 +151,10 @@
 #define SC_R_DMA_1_CH29                 137
 #define SC_R_DMA_1_CH30                 138
 #define SC_R_DMA_1_CH31                 139
-#define SC_R_UNUSED1                    140
-#define SC_R_UNUSED2                    141
-#define SC_R_UNUSED3                    142
-#define SC_R_UNUSED4                    143
+#define SC_R_V2X_PID0                   140
+#define SC_R_V2X_PID1                   141
+#define SC_R_V2X_PID2                   142
+#define SC_R_V2X_PID3                   143
 #define SC_R_GPU_0_PID0                 144
 #define SC_R_GPU_0_PID1                 145
 #define SC_R_GPU_0_PID2                 146
@@ -301,8 +301,8 @@
 #define SC_R_M4_0_UART                  287
 #define SC_R_M4_0_I2C                   288
 #define SC_R_M4_0_INTMUX                289
-#define SC_R_M4_0_SIM                   290
-#define SC_R_M4_0_WDOG                  291
+#define SC_R_ENET_0_A0                  290
+#define SC_R_ENET_0_A1                  291
 #define SC_R_M4_0_MU_0B                 292
 #define SC_R_M4_0_MU_0A0                293
 #define SC_R_M4_0_MU_0A1                294
@@ -321,8 +321,8 @@
 #define SC_R_M4_1_UART                  307
 #define SC_R_M4_1_I2C                   308
 #define SC_R_M4_1_INTMUX                309
-#define SC_R_M4_1_SIM                   310
-#define SC_R_M4_1_WDOG                  311
+#define SC_R_UNUSED17                   310
+#define SC_R_UNUSED18                   311
 #define SC_R_M4_1_MU_0B                 312
 #define SC_R_M4_1_MU_0A0                313
 #define SC_R_M4_1_MU_0A1                314
@@ -334,7 +334,7 @@
 #define SC_R_SAI_2                      320
 #define SC_R_IRQSTR_SCU2                321
 #define SC_R_IRQSTR_DSP                 322
-#define SC_R_UNUSED5                    323
+#define SC_R_ELCDIF_PLL                 323
 #define SC_R_OCRAM                      324
 #define SC_R_AUDIO_PLL_0                325
 #define SC_R_PI_0                       326
@@ -377,12 +377,12 @@
 #define SC_R_VPU_PID5                   363
 #define SC_R_VPU_PID6                   364
 #define SC_R_VPU_PID7                   365
-#define SC_R_VPU_UART                   366
-#define SC_R_VPUCORE                    367
-#define SC_R_VPUCORE_0                  368
-#define SC_R_VPUCORE_1                  369
-#define SC_R_VPUCORE_2                  370
-#define SC_R_VPUCORE_3                  371
+#define SC_R_ENET_0_A2                  366
+#define SC_R_ENET_1_A0                  367
+#define SC_R_ENET_1_A1                  368
+#define SC_R_ENET_1_A2                  369
+#define SC_R_ENET_1_A3                  370
+#define SC_R_ENET_1_A4                  371
 #define SC_R_DMA_4_CH0                  372
 #define SC_R_DMA_4_CH1                  373
 #define SC_R_DMA_4_CH2                  374
@@ -552,7 +552,12 @@
 #define SC_R_VPU_MU_3                   538
 #define SC_R_VPU_ENC_1                  539
 #define SC_R_VPU                        540
-#define SC_R_LAST                       541
+#define SC_R_DMA_5_CH0                  541
+#define SC_R_DMA_5_CH1                  542
+#define SC_R_DMA_5_CH2                  543
+#define SC_R_DMA_5_CH3                  544
+#define SC_R_ATTESTATION                545
+#define SC_R_LAST                       546
 #define SC_R_NONE                       0xFFF0
 
 #endif /* DT_BINDINGS_RSCRC_IMX_H */
diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
index e08530ec4e5..bcd7428f4cd 100644
--- a/include/dwc3-uboot.h
+++ b/include/dwc3-uboot.h
@@ -18,6 +18,7 @@ struct dwc3_device {
 	enum usb_dr_mode dr_mode;
 	enum usb_phy_interface hsphy_mode;
 	u32 maximum_speed;
+	u16 power_down_scale;
 	unsigned tx_fifo_resize:1;
 	unsigned has_lpm_erratum;
 	u8 lpm_nyet_threshold;
diff --git a/include/efi_api.h b/include/efi_api.h
index 982c2001728..2a31b850768 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -226,6 +226,10 @@ enum efi_reset_type {
 	EFI_GUID(0x6dcbd5ed, 0xe82d, 0x4c44, 0xbd, 0xa1, \
 		 0x71, 0x94, 0x19, 0x9a, 0xd9, 0x2a)
 
+#define EFI_MEMORY_ONLY_RESET_CONTROL_GUID \
+	EFI_GUID(0xe20939be, 0x32d4, 0x41be, 0xa1, 0x50, \
+		 0x89, 0x7f, 0x85, 0xd4, 0x98, 0x29)
+
 struct efi_capsule_header {
 	efi_guid_t capsule_guid;
 	u32 header_size;
@@ -1873,6 +1877,12 @@ struct efi_system_resource_table {
 #define EFI_CERT_X509_SHA256_GUID \
 	EFI_GUID(0x3bd2a492, 0x96c0, 0x4079, 0xb4, 0x20, \
 		 0xfc, 0xf9, 0x8e, 0xf1, 0x03, 0xed)
+#define EFI_CERT_X509_SHA384_GUID \
+	EFI_GUID(0x7076876e, 0x80c2, 0x4ee6,		\
+		 0xaa, 0xd2, 0x28, 0xb3, 0x49, 0xa6, 0x86, 0x5b)
+#define EFI_CERT_X509_SHA512_GUID \
+	EFI_GUID(0x446dbf63, 0x2502, 0x4cda,		\
+		 0xbc, 0xfa, 0x24, 0x65, 0xd2, 0xb0, 0xfe, 0x9d)
 #define EFI_CERT_TYPE_PKCS7_GUID \
 	EFI_GUID(0x4aafd29d, 0x68df, 0x49ee, 0x8a, 0xa9, \
 		 0x34, 0x7d, 0x37, 0x56, 0x65, 0xa7)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index af36639ec6a..cd1f2543b21 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -312,6 +312,8 @@ extern const efi_guid_t efi_guid_firmware_management_protocol;
 extern const efi_guid_t efi_esrt_guid;
 /* GUID of the SMBIOS table */
 extern const efi_guid_t smbios_guid;
+/* GUID of memory only reset control */
+extern const efi_guid_t efi_memory_only_reset_control_guid;
 
 extern char __efi_runtime_start[], __efi_runtime_stop[];
 extern char __efi_runtime_rel_start[], __efi_runtime_rel_stop[];
diff --git a/include/env.h b/include/env.h
index 60acb5454ec..05af611d387 100644
--- a/include/env.h
+++ b/include/env.h
@@ -377,4 +377,10 @@ void env_import_fdt(void);
 static inline void env_import_fdt(void) {}
 #endif
 
+#ifdef ENV_IS_EMBEDDED
+#define env_get_offset(x) x
+#else
+long long env_get_offset(long long defautl_offset);
+#endif
+
 #endif
diff --git a/include/env_internal.h b/include/env_internal.h
index 07c227ecc03..b9a2b8506d1 100644
--- a/include/env_internal.h
+++ b/include/env_internal.h
@@ -126,6 +126,7 @@ extern const char default_environment[];
 enum env_location {
 	ENVL_UNKNOWN,
 	ENVL_EEPROM,
+	ENVL_ESATA,
 	ENVL_EXT4,
 	ENVL_FAT,
 	ENVL_FLASH,
diff --git a/include/fastboot.h b/include/fastboot.h
index 57daaf12982..70d5b330627 100644
--- a/include/fastboot.h
+++ b/include/fastboot.h
@@ -48,7 +48,26 @@ enum {
 	FASTBOOT_COMMAND_ACMD,
 	FASTBOOT_COMMAND_UCMD,
 #endif
-
+#ifdef CONFIG_FSL_FASTBOOT
+	FASTBOOT_COMMAND_UPLOAD,
+	FASTBOOT_COMMAND_GETSTAGED,
+#ifdef CONFIG_FASTBOOT_LOCK
+	FASTBOOT_COMMAND_FLASHING,
+	FASTBOOT_COMMAND_OEM,
+#endif
+#ifdef CONFIG_AVB_SUPPORT
+	FASTBOOT_COMMAND_SETACTIVE,
+#endif
+#ifdef CONFIG_AVB_ATX
+	FASTBOOT_COMMAND_STAGE,
+#endif
+#endif
+#ifdef CONFIG_ANDROID_RECOVERY
+	FASTBOOT_COMMAND_RECOVERY_FASTBOOT,
+#endif
+#ifdef CONFIG_VIRTUAL_AB_SUPPORT
+	FASTBOOT_COMMAND_SNAPSHOT_UPDATE,
+#endif
 	FASTBOOT_COMMAND_COUNT
 };
 
@@ -176,4 +195,9 @@ void fastboot_data_complete(char *response);
 #if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT)
 void fastboot_acmd_complete(void);
 #endif
+
+int fastboot_tx_write_more(const char *buffer);
+
+int fastboot_tx_write(const char *buffer, unsigned int buffer_size);
+
 #endif /* _FASTBOOT_H_ */
diff --git a/include/fb_fsl.h b/include/fb_fsl.h
new file mode 100644
index 00000000000..7c2d6fbc89e
--- /dev/null
+++ b/include/fb_fsl.h
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
+ */
+
+#ifndef FB_FSL_H
+#define FB_FSL_H
+#include <stdbool.h>
+#include <linux/types.h>
+
+#define FASTBOOT_PTENTRY_FLAGS_REPEAT(n)              (n & 0x0f)
+#define FASTBOOT_PTENTRY_FLAGS_REPEAT_MASK            0x0000000F
+
+/* Writes happen a block at a time.
+   If the write fails, go to next block
+   NEXT_GOOD_BLOCK and CONTIGOUS_BLOCK can not both be set */
+#define FASTBOOT_PTENTRY_FLAGS_WRITE_NEXT_GOOD_BLOCK  0x00000010
+
+/* Find a contiguous block big enough for a the whole file
+   NEXT_GOOD_BLOCK and CONTIGOUS_BLOCK can not both be set */
+#define FASTBOOT_PTENTRY_FLAGS_WRITE_CONTIGUOUS_BLOCK 0x00000020
+
+/* Write the file with write.i */
+#define FASTBOOT_PTENTRY_FLAGS_WRITE_I                0x00000100
+
+/* Write the file with write.trimffs */
+#define FASTBOOT_PTENTRY_FLAGS_WRITE_TRIMFFS          0x00000200
+
+/* Write the file as a series of variable/value pairs
+   using the setenv and saveenv commands */
+#define FASTBOOT_PTENTRY_FLAGS_WRITE_ENV              0x00000400
+
+/* Uneraseable partition */
+#define FASTBOOT_PTENTRY_FLAGS_UNERASEABLE            0x00000800
+
+#define FASTBOOT_MMC_BOOT_PARTITION_ID  1
+#define FASTBOOT_MMC_USER_PARTITION_ID  0
+#define FASTBOOT_MMC_NONE_PARTITION_ID -1
+#define FASTBOOT_MMC_BOOT1_PARTITION_ID  2
+
+#define FASTBOOT_PARTITION_TEE "tos"
+#define FASTBOOT_PARTITION_PRDATA "presistdata"
+
+#ifdef CONFIG_AVB_SUPPORT
+#define FASTBOOT_PARTITION_AVBKEY "avbkey"
+#endif
+
+#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT
+#define FASTBOOT_MCU_FIRMWARE_PARTITION "mcu_os"
+#endif
+
+#define FASTBOOT_PARTITION_METADATA "metadata"
+
+#ifdef CONFIG_ANDROID_AB_SUPPORT
+#define FASTBOOT_PARTITION_BOOT_A "boot_a"
+#define FASTBOOT_PARTITION_RECOVERY "recovery"
+#define FASTBOOT_PARTITION_SYSTEM_A "system_a"
+#define FASTBOOT_PARTITION_BOOTLOADER "bootloader0"
+#define FASTBOOT_PARTITION_DATA "userdata"
+#define FASTBOOT_PARTITION_BOOT_B "boot_b"
+#define FASTBOOT_PARTITION_SYSTEM_B "system_b"
+#define FASTBOOT_PARTITION_OEM_A "oem_a"
+#define FASTBOOT_PARTITION_VENDOR_A "vendor_a"
+#define FASTBOOT_PARTITION_OEM_B "oem_b"
+#define FASTBOOT_PARTITION_VENDOR_B "vendor_b"
+#ifdef CONFIG_AVB_SUPPORT
+#define FASTBOOT_PARTITION_VBMETA_A "vbmeta_a"
+#define FASTBOOT_PARTITION_VBMETA_B "vbmeta_b"
+#endif
+#define FASTBOOT_PARTITION_MISC "misc"
+#define FASTBOOT_PARTITION_GPT "gpt"
+#define FASTBOOT_PARTITION_FBMISC "fbmisc"
+#else
+#define FASTBOOT_PARTITION_BOOT "boot"
+#define FASTBOOT_PARTITION_RECOVERY "recovery"
+#define FASTBOOT_PARTITION_SYSTEM "system"
+#define FASTBOOT_PARTITION_CACHE "cache"
+#define FASTBOOT_PARTITION_DEVICE "device"
+#define FASTBOOT_PARTITION_BOOTLOADER "bootloader"
+#define FASTBOOT_PARTITION_DATA "userdata"
+#define FASTBOOT_PARTITION_GPT "gpt"
+#define FASTBOOT_PARTITION_MISC "misc"
+#define FASTBOOT_PARTITION_FBMISC "fbmisc"
+#endif
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+#ifndef CONFIG_AVB_ATX
+#define FASTBOOT_SET_RPMB_STAGED_KEY "set-rpmb-staged-key"
+#define FASTBOOT_SET_RPMB_HARDWARE_KEY "set-rpmb-hardware-key"
+#define FASTBOOT_SET_VBMETA_PUBLIC_KEY "set-public-key"
+#define FASTBOOT_ERASE_RPMB "erase-rpmb"
+#endif
+
+#define FASTBOOT_SET_CA_RESP "at-set-ca-response"
+#define FASTBOOT_GET_CA_REQ  "at-get-ca-request"
+#define FASTBOOT_SET_RSA_ATTESTATION_KEY  "set-rsa-atte-key"
+#define FASTBOOT_SET_EC_ATTESTATION_KEY  "set-ec-atte-key"
+#define FASTBOOT_APPEND_RSA_ATTESTATION_CERT  "append-rsa-atte-cert"
+#define FASTBOOT_APPEND_EC_ATTESTATION_CERT  "append-ec-atte-cert"
+#define FASTBOOT_SET_RSA_ATTESTATION_KEY_ENC  "set-rsa-atte-key-enc"
+#define FASTBOOT_SET_EC_ATTESTATION_KEY_ENC  "set-ec-atte-key-enc"
+#define FASTBOOT_APPEND_RSA_ATTESTATION_CERT_ENC  "append-rsa-atte-cert-enc"
+#define FASTBOOT_APPEND_EC_ATTESTATION_CERT_ENC  "append-ec-atte-cert-enc"
+#define FASTBOOT_GET_MPPUBK  "get-mppubk"
+#define FASTBOOT_GET_SERIAL_NUMBER  "get-serial-number"
+#define FASTBOOT_SET_ATTESTATION_ID "set-device-id"
+#define FASTBOOT_WV_PROVISION	"provision-wv-keybox"
+#define FASTBOOT_WV_PROVISION_ENC	"provision-wv-keybox-enc"
+#endif
+
+#ifdef CONFIG_ANDROID_THINGS_SUPPORT
+#define FASTBOOT_BOOTLOADER_VBOOT_KEY "fuse at-bootloader-vboot-key"
+#ifdef CONFIG_AVB_ATX
+#define FASTBOOT_AVB_AT_PERM_ATTR "fuse at-perm-attr"
+#define FASTBOOT_AT_UNLOCK_VBOOT "at-unlock-vboot"
+#define FASTBOOT_AT_LOCK_VBOOT "at-lock-vboot"
+#define FASTBOOT_AT_DISABLE_UNLOCK_VBOOT "at-disable-unlock-vboot"
+#define FASTBOOT_AT_GET_UNLOCK_CHALLENGE "at-get-vboot-unlock-challenge"
+#endif /* CONFIG_AVB_ATX */
+#endif /* CONFIG_ANDROID_THINGS_SUPPORT */
+
+#ifndef TEE_HWPARTITION_ID
+#define TEE_HWPARTITION_ID 2
+#endif
+
+#define FASTBOOT_PARTITION_ALL "all"
+
+#define MMC_SATA_BLOCK_SIZE 512
+
+#define ANDROID_MBR_OFFSET	    0
+#define ANDROID_MBR_SIZE	    0x200
+#define ANDROID_BOOTLOADER_SIZE	    0x400000
+
+#define ANDROID_GPT_OFFSET         0
+#define ANDROID_GPT_SIZE           0x100000
+#define ANDROID_GPT_END	           0x4400
+
+/* To support the Android-style naming of flash */
+#define MAX_PTN		    32
+
+enum {
+    DEV_SATA,
+    DEV_MMC,
+    DEV_NAND,
+#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT
+    /* SPI Flash */
+    DEV_SF
+#endif
+};
+
+typedef enum {
+#ifdef CONFIG_ANDROID_RECOVERY
+	/* Revoery boot due to combo keys pressed */
+	BOOTMODE_RECOVERY_KEY_PRESSED,
+	/* Recovery boot due to boot-recovery cmd in misc parition */
+	BOOTMODE_RECOVERY_BCB_CMD,
+#endif
+	/* Fastboot boot due to bootonce-bootloader cmd in misc parition */
+	BOOTMODE_FASTBOOT_BCB_CMD,
+	/* Normal boot */
+	BOOTMODE_NORMAL
+}FbBootMode;
+
+/* flash partitions are defined in terms of blocks
+** (flash erase units)
+*/
+struct fastboot_ptentry {
+	/* The logical name for this partition, null terminated */
+	char name[20];
+	/* The start wrt the nand part, must be multiple of nand block size */
+	unsigned int start;
+	/* The length of the partition, must be multiple of nand block size */
+	unsigned long length;
+	/* Controls the details of how operations are done on the partition
+	   See the FASTBOOT_PTENTRY_FLAGS_*'s defined below */
+	unsigned int flags;
+	/* partition id: 0 - normal partition; 1 - boot partition */
+	unsigned int partition_id;
+	/* partition number in block device */
+	unsigned int partition_index;
+	/* partition file system type in string */
+	char fstype[16];
+	/* filesystem UUID as string, if exists */
+#ifdef CONFIG_PARTITION_UUIDS
+	char uuid[37];
+#endif
+};
+
+struct fastboot_device_info {
+	unsigned char type;
+	unsigned char dev_id;
+};
+
+extern struct fastboot_device_info fastboot_devinfo;
+
+#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT
+extern struct fastboot_device_info fastboot_firmwareinfo;
+#endif
+
+extern struct fastboot_ptentry g_ptable[MAX_PTN];
+extern unsigned int g_pcount;
+
+/* Prepare the fastboot environments,
+  * should be executed before "fastboot" cmd
+  */
+void fastboot_setup(void);
+
+
+/* The Android-style flash handling */
+
+/* tools to populate and query the partition table */
+void fastboot_flash_add_ptn(struct fastboot_ptentry *ptn);
+struct fastboot_ptentry *fastboot_flash_find_ptn(const char *name);
+struct fastboot_ptentry *fastboot_flash_get_ptn(unsigned n);
+unsigned int fastboot_flash_get_ptn_count(void);
+void fastboot_flash_dump_ptn(void);
+
+/* Make board into special boot mode  */
+void fastboot_run_bootmode(void);
+
+/*Setup board-relative fastboot environment */
+void board_fastboot_setup(void);
+
+/*return partition index according name*/
+int fastboot_flash_find_index(const char *name);
+
+bool fastboot_parts_is_slot(void);
+
+bool fastboot_parts_is_raw(struct fastboot_ptentry *ptn);
+
+/*get partition base name from gpt without "_a/_b"*/
+int fastboot_parts_get_name(char (*partition_base_name)[20]);
+
+void fastboot_load_partitions(void);
+
+void fastboot_none_resp(char *response);
+
+void fastboot_process_erase(const char *cmdbuf, char *response);
+
+void fastboot_process_flash(const char *cmdbuf, void *download_buffer,
+			      u32 download_bytes, char *response);
+
+/*check whether bootloader is overlay with GPT table*/
+bool bootloader_gpt_overlay(void);
+/* Check whether the combo keys pressed
+ * Return 1 if combo keys pressed for recovery boot
+ * Return 0 if no combo keys pressed
+ */
+int is_recovery_key_pressing(void);
+
+/* Reads |num_bytes| from offset |offset| from partition with name
+ * |partition| (NUL-terminated UTF-8 string). If |offset| is
+ * negative, its absolute value should be interpreted as the number
+ * of bytes from the end of the partition.
+ * It's basically copied from fsl_read_from_partition_multi() because
+ * we may want to read partition when AVB is not enabled. */
+int read_from_partition_multi(const char* partition,
+		int64_t offset, size_t num_bytes,void* buffer, size_t* out_num_read);
+#endif /* FB_FSL_H */
diff --git a/include/fs.h b/include/fs.h
index c8df3886ac6..1a8696e1d29 100644
--- a/include/fs.h
+++ b/include/fs.h
@@ -20,6 +20,8 @@ struct cmd_tbl;
 
 struct blk_desc;
 
+int do_fat_size(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
+
 /**
  * do_fat_fsload - Run the fatload command
  *
diff --git a/include/fsl_avb.h b/include/fsl_avb.h
new file mode 100644
index 00000000000..9c7cfe059d0
--- /dev/null
+++ b/include/fsl_avb.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __FSL_AVB_H__
+#define __FSL_AVB_H__
+
+#include "../lib/avb/libavb_atx/libavb_atx.h"
+#include "../lib/avb/fsl/fsl_bootctrl.h"
+/* Reads |num_bytes| from offset |offset| from partition with name
+ * |partition| (NUL-terminated UTF-8 string). If |offset| is
+ * negative, its absolute value should be interpreted as the number
+ * of bytes from the end of the partition.
+ *
+ * This function returns AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION if
+ * there is no partition with the given name,
+ * AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION if the requested
+ * |offset| is outside the partition, and AVB_IO_RESULT_ERROR_IO if
+ * there was an I/O error from the underlying I/O subsystem.  If the
+ * operation succeeds as requested AVB_IO_RESULT_OK is returned and
+ * the data is available in |buffer|.
+ *
+ * The only time partial I/O may occur is if reading beyond the end
+ * of the partition. In this case the value returned in
+ * |out_num_read| may be smaller than |num_bytes|.
+ */
+AvbIOResult fsl_read_from_partition(AvbOps* ops, const char* partition,
+                                    int64_t offset, size_t num_bytes,
+                                    void* buffer, size_t* out_num_read);
+
+/* multi block read version
+ * */
+AvbIOResult fsl_read_from_partition_multi(AvbOps* ops, const char* partition,
+                                          int64_t offset, size_t num_bytes,
+                                          void* buffer, size_t* out_num_read);
+
+/* Writes |num_bytes| from |bffer| at offset |offset| to partition
+ * with name |partition| (NUL-terminated UTF-8 string). If |offset|
+ * is negative, its absolute value should be interpreted as the
+ * number of bytes from the end of the partition.
+ *
+ * This function returns AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION if
+ * there is no partition with the given name,
+ * AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION if the requested
+ * byterange goes outside the partition, and AVB_IO_RESULT_ERROR_IO
+ * if there was an I/O error from the underlying I/O subsystem.  If
+ * the operation succeeds as requested AVB_IO_RESULT_OK is
+ * returned.
+ *
+ * This function never does any partial I/O, it either transfers all
+ * of the requested bytes or returns an error.
+ */
+AvbIOResult fsl_write_to_partition(AvbOps* ops, const char* partition,
+                                   int64_t offset, size_t num_bytes,
+                                   const void* buffer);
+
+/* Checks if the given public key used to sign the 'vbmeta'
+ * partition is trusted. Boot loaders typically compare this with
+ * embedded key material generated with 'avbtool
+ * extract_public_key'.
+ *
+ * If AVB_IO_RESULT_OK is returned then |out_is_trusted| is set -
+ * true if trusted or false if untrusted.
+ */
+AvbIOResult fsl_validate_vbmeta_public_key_rpmb(AvbOps* ops,
+                                                const uint8_t* public_key_data,
+                                                size_t public_key_length,
+                                                const uint8_t* public_key_metadata,
+                                                size_t public_key_metadata_length,
+                                                bool* out_is_trusted);
+
+/* Gets the rollback index corresponding to the slot given by
+ * |rollback_index_slot|. The value is returned in
+ * |out_rollback_index|. Returns AVB_IO_RESULT_OK if the rollback
+ * index was retrieved, otherwise an error code.
+ *
+ * A device may have a limited amount of rollback index slots (say,
+ * one or four) so may error out if |rollback_index_slot| exceeds
+ * this number.
+ */
+AvbIOResult fsl_read_rollback_index_rpmb(AvbOps* ops, size_t rollback_index_slot,
+                                         uint64_t* out_rollback_index);
+
+/* Sets the rollback index corresponding to the slot given by
+ * |rollback_index_slot| to |rollback_index|. Returns
+ * AVB_IO_RESULT_OK if the rollback index was set, otherwise an
+ * error code.
+ *
+ * A device may have a limited amount of rollback index slots (say,
+ * one or four) so may error out if |rollback_index_slot| exceeds
+ * this number.
+ */
+AvbIOResult fsl_write_rollback_index_rpmb(AvbOps* ops, size_t rollback_index_slot,
+                                          uint64_t rollback_index);
+
+/* Gets whether the device is unlocked. The value is returned in
+ * |out_is_unlocked| (true if unlocked, false otherwise). Returns
+ * AVB_IO_RESULT_OK if the state was retrieved, otherwise an error
+ * code.
+ */
+AvbIOResult fsl_read_is_device_unlocked(AvbOps* ops, bool* out_is_unlocked);
+
+/* Gets the unique partition GUID for a partition with name in
+ * |partition| (NUL-terminated UTF-8 string). The GUID is copied as
+ * a string into |guid_buf| of size |guid_buf_size| and will be NUL
+ * terminated. The string must be lower-case and properly
+ * hyphenated. For example:
+ *
+ *  527c1c6d-6361-4593-8842-3c78fcd39219
+ *
+ * Returns AVB_IO_RESULT_OK on success, otherwise an error code.
+ */
+AvbIOResult fsl_get_unique_guid_for_partition(AvbOps* ops,
+                                              const char* partition,
+                                              char* guid_buf,
+                                              size_t guid_buf_size);
+
+/* Gets the size of a partition with the name in |partition|
+ * (NUL-terminated UTF-8 string). Returns the value in
+ * |out_size_num_bytes|.
+ * Returns AVB_IO_RESULT_OK on success, otherwise an error code.
+ */
+AvbIOResult fsl_get_size_of_partition(AvbOps* ops,
+                                      const char* partition,
+                                      uint64_t* out_size_num_bytes);
+
+/* reset rollback_index part in avbkey partition
+ * used in the switch from LOCK to UNLOCK
+ * return 0 if success, non 0 if fail.
+ * */
+int rbkidx_erase(void);
+
+/* init the avbkey in rpmb partition, include the header/public key/rollback index
+ * for public key/rollback index part, use caam to do encrypt
+ * return 0 if success, non 0 if fail.
+ * */
+int avbkey_init(uint8_t *plainkey, uint32_t keylen);
+
+/* Reads permanent |attributes| data. There are no restrictions on where this
+ * data is stored. On success, returns AVB_IO_RESULT_OK and populates
+ * |attributes|.
+ */
+AvbIOResult fsl_read_permanent_attributes(
+    AvbAtxOps* atx_ops, AvbAtxPermanentAttributes* attributes);
+
+/* Reads a |hash| of permanent attributes. This hash MUST be retrieved from a
+ * permanently read-only location (e.g. fuses) when a device is LOCKED. On
+ * success, returned AVB_IO_RESULT_OK and populates |hash|.
+ */
+AvbIOResult fsl_read_permanent_attributes_hash(AvbAtxOps* atx_ops,
+                                               uint8_t hash[AVB_SHA256_DIGEST_SIZE]);
+
+/* Provides the key version of a key used during verification. This may be
+ * useful for managing the minimum key version.
+ */
+void fsl_set_key_version(AvbAtxOps* atx_ops,
+                         size_t rollback_index_location,
+                         uint64_t key_version);
+
+/* Generates |num_bytes| random bytes and stores them in |output|,
+ * which must point to a buffer large enough to store the bytes.
+ *
+ * Returns AVB_IO_RESULT_OK on success, otherwise an error code.
+ */
+AvbIOResult fsl_get_random(AvbAtxOps* atx_ops,
+				size_t num_bytes,
+				uint8_t* output);
+
+/* Program ATX perm_attr into RPMB partition */
+int avb_atx_fuse_perm_attr(uint8_t *staged_buffer, uint32_t size);
+
+/* Initialize rpmb key with the staged key */
+int fastboot_set_rpmb_staged_key(uint8_t *staged_buf, uint32_t key_size);
+
+/* Initialize rpmb key with hardware key which is derived from BKEK */
+int fastboot_set_rpmb_hardware_key(void);
+
+/* Generate ATX unlock challenge */
+int avb_atx_get_unlock_challenge(struct AvbAtxOps* atx_ops,
+				uint8_t *upload_buffer, uint32_t *size);
+/* Verify ATX unlock credential */
+int avb_atx_verify_unlock_credential(struct AvbAtxOps* atx_ops,
+					uint8_t *staged_buffer);
+/* Check if the perm-attr have been fused. */
+bool perm_attr_are_fused(void);
+
+/* Check if the unlock vboot is already disabled */
+bool at_unlock_vboot_is_disabled(void);
+
+/* disable at unlock vboot */
+int at_disable_vboot_unlock(void);
+
+/* Set vbmeta public key */
+int avb_set_public_key(uint8_t *staged_buffer, uint32_t size);
+
+/* Get manufacture protection  public key */
+int fastboot_get_mppubk(uint8_t *staged_buffer, uint32_t *size);
+
+/* Check if hab is closed. */
+bool hab_is_enabled(void);
+
+/* Return if device is in spl recovery mode. */
+bool is_spl_recovery(void);
+
+#endif /* __FSL_AVB_H__ */
diff --git a/include/fsl_avb_logo.h b/include/fsl_avb_logo.h
new file mode 100644
index 00000000000..300d137a920
--- /dev/null
+++ b/include/fsl_avb_logo.h
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright NXP 2020
+ *
+ */
+
+#ifndef __FSL_AVB_LOGO_H__
+#define __FSL_AVB_LOGO_H__
+
+extern unsigned short orange_warning_bmp_palette[];
+extern unsigned char orange_warning_bmp_bitmap[];
+
+#endif /* __FSL_AVB_LOGO_H__ */
diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h
index 18e5cc15d61..93c996b764b 100644
--- a/include/fsl_lpuart.h
+++ b/include/fsl_lpuart.h
@@ -5,7 +5,7 @@
  */
 
 #if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) || \
-	defined(CONFIG_ARCH_IMXRT) || defined(CONFIG_ARCH_IMX8ULP)
+	defined(CONFIG_ARCH_IMXRT) || defined(CONFIG_ARCH_IMX8ULP) || defined(CONFIG_ARCH_IMX9)
 struct lpuart_fsl_reg32 {
 	u32 verid;
 	u32 param;
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index c4121696f82..a7f6fe27ada 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -3,7 +3,7 @@
  * Common internal memory map for some Freescale SoCs
  *
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  */
 
 #ifndef __FSL_SEC_H
@@ -13,8 +13,8 @@
 #include <asm/io.h>
 
 #ifdef CONFIG_SYS_FSL_SEC_LE
-#define sec_in32(a)       in_le32((ulong *)(ulong)a)
-#define sec_out32(a, v)   out_le32((ulong *)(ulong)a, v)
+#define sec_in32(a)       in_le32((ulong *)(ulong)(a))
+#define sec_out32(a, v)   out_le32((ulong *)(ulong)(a), v)
 #define sec_in16(a)       in_le16(a)
 #define sec_clrbits32     clrbits_le32
 #define sec_setbits32     setbits_le32
@@ -28,12 +28,22 @@
 #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined
 #endif
 
+#define BLOB_OVERHEAD		(32 + 16)
 #define BLOB_SIZE(x)		((x) + 32 + 16) /* Blob buffer size */
+#define AES256_KEY_SZ		32
+
+#define NONCE_SIZE		6
+#define ICV_SIZE		6
+#define CCM_OVERHEAD		(NONCE_SIZE + ICV_SIZE)
+#define TAG_SIZE		20
+#define MAX_BLOB_SIZE		(AES256_KEY_SZ + CCM_OVERHEAD +\
+				BLOB_OVERHEAD + TAG_SIZE)
 
 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
 /* RNG4 TRNG test registers */
 struct rng4tst {
+#define RTMCTL_ACC  0x20
 #define RTMCTL_PRGM 0x00010000	/* 1 -> program mode, 0 -> run mode */
 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC     0 /* use von Neumann data in
 						    both entropy shifter and
@@ -48,7 +58,11 @@ struct rng4tst {
 	u32 rtmctl;		/* misc. control register */
 	u32 rtscmisc;		/* statistical check misc. register */
 	u32 rtpkrrng;		/* poker range register */
-#define RTSDCTL_ENT_DLY_MIN	3200
+#ifdef CONFIG_MX6SX
+#define RTSDCTL_ENT_DLY		12000
+#else
+#define RTSDCTL_ENT_DLY		3200
+#endif
 #define RTSDCTL_ENT_DLY_MAX	12800
 	union {
 		u32 rtpkrmax;	/* PRGM=1: poker max. limit register */
@@ -194,12 +208,11 @@ typedef struct ccsr_sec {
 #define SEC_CHAVID_LS_RNG_SHIFT		16
 #define SEC_CHAVID_RNG_LS_MASK		0x000f0000
 
-#define CONFIG_JRSTARTR_JR0		0x00000001
-
 struct jr_regs {
 #if defined(CONFIG_SYS_FSL_SEC_LE) && \
 	!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
-	  defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+	  defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) || \
+	  defined(CONFIG_IMX8ULP))
 	u32 irba_l;
 	u32 irba_h;
 #else
@@ -214,7 +227,8 @@ struct jr_regs {
 	u32 irja;
 #if defined(CONFIG_SYS_FSL_SEC_LE) && \
 	!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
-	  defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+	  defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) || \
+	  defined(CONFIG_IMX8ULP))
 	u32 orba_l;
 	u32 orba_h;
 #else
@@ -248,7 +262,8 @@ struct jr_regs {
 struct sg_entry {
 #if defined(CONFIG_SYS_FSL_SEC_LE) && \
 	!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
-	  defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
+	  defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) || \
+	  defined(CONFIG_IMX8ULP))
 	uint32_t addr_lo;	/* Memory Address - lo */
 	uint32_t addr_hi;	/* Memory Address of start of buffer - hi */
 #else
@@ -268,7 +283,8 @@ struct sg_entry {
 };
 
 #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
-	defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)
+	 defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) || \
+	 defined(CONFIG_IMX8ULP)
 /* Job Ring Base Address */
 #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
 /* Secure Memory Offset varies accross versions */
@@ -379,6 +395,46 @@ int sec_init_idx(uint8_t);
 int sec_init(void);
 
 u8 caam_get_era(void);
+
+/**
+ * blob_decap() - Decapsulate the data from a blob
+ * @key_mod:    - Key modifier address
+ * @src:        - Source address (blob)
+ * @dst:        - Destination address (data)
+ * @len:        - Size of decapsulated data
+ * @keycolor    - Determines if the source data is covered (black key) or
+ *                plaintext.
+ *
+ * Note: Start and end of the key_mod, src and dst buffers have to be aligned to
+ * the cache line size (ARCH_DMA_MINALIGN) for the CAAM operation to succeed.
+ *
+ * Returns zero on success, negative on error.
+ */
+int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len, u8 keycolor);
+
+/**
+ * blob_encap() - Encapsulate the data as a blob
+ * @key_mod:    - Key modifier address
+ * @src:        - Source address (data)
+ * @dst:        - Destination address (blob)
+ * @len:        - Size of data to be encapsulated
+ * @keycolor    - Determines if the source data is covered (black key) or
+ *                plaintext.
+ *
+ * Note: Start and end of the key_mod, src and dst buffers have to be aligned to
+ * the cache line size (ARCH_DMA_MINALIGN) for the CAAM operation to succeed.
+ *
+ * Returns zero on success, negative on error.
+ */
+int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len, u8 keycolor);
+
+int derive_blob_kek(u8 *bkek_buf, u8 *key_mod, u32 key_sz);
+
+int hwrng_generate(u8 *dst, u32 len);
+
+int aesecb_decrypt(u8 *key, u32 key_len, u8 *src, u8 *dst, u32 len);
+
+int tag_black_obj(u8 *black_obj, size_t black_obj_len, size_t key_len, size_t black_max_len);
 #endif
 
 #endif /* __FSL_SEC_H */
diff --git a/include/g_dnl.h b/include/g_dnl.h
index 836ee602c8d..050b618f51e 100644
--- a/include/g_dnl.h
+++ b/include/g_dnl.h
@@ -44,5 +44,6 @@ bool g_dnl_detach(void);
 void g_dnl_trigger_detach(void);
 void g_dnl_clear_detach(void);
 int run_usb_dnl_gadget(int usbctrl_index, char *usb_dnl_gadget);
+int board_usb_gadget_port_auto(void);
 
 #endif /* __G_DOWNLOAD_H_ */
diff --git a/include/gis.h b/include/gis.h
new file mode 100644
index 00000000000..e156743407a
--- /dev/null
+++ b/include/gis.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef GIS_H
+#define GIS_H
+
+#define FMT_YUV444		0
+#define FMT_YUYV		1
+#define FMT_UYVY		2
+#define FMT_RGB565		3
+#define FMT_RGB888		4
+
+void mxc_enable_gis(void);
+void mxc_disable_gis(void);
+
+#endif
diff --git a/include/image.h b/include/image.h
index 97e5f2eb24d..fb376585800 100644
--- a/include/image.h
+++ b/include/image.h
@@ -1451,9 +1451,15 @@ int fit_image_cipher_get_algo(const void *fit, int noffset, char **algo);
 struct cipher_algo *image_get_cipher_algo(const char *full_name);
 
 struct andr_img_hdr;
+struct boot_img_hdr_v3;
+struct vendor_boot_img_hdr_v3;
 int android_image_check_header(const struct andr_img_hdr *hdr);
+int android_image_check_header_v3(uint8_t *boot_magic, uint8_t * vendor_boot_magic);
 int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
 			     ulong *os_data, ulong *os_len);
+int android_image_get_kernel_v3(const struct boot_img_hdr_v3 *hdr,
+				const struct vendor_boot_img_hdr_v3 *vendor_hdr,
+				bool bootconfig);
 int android_image_get_ramdisk(const struct andr_img_hdr *hdr,
 			      ulong *rd_data, ulong *rd_len);
 int android_image_get_second(const struct andr_img_hdr *hdr,
@@ -1466,6 +1472,11 @@ ulong android_image_get_kload(const struct andr_img_hdr *hdr);
 ulong android_image_get_kcomp(const struct andr_img_hdr *hdr);
 void android_print_contents(const struct andr_img_hdr *hdr);
 bool android_image_print_dtb_contents(ulong hdr_addr);
+bool image_arm64(void *images);
+uint32_t kernel_size(void *images);
+ulong kernel_relocate_addr(ulong images);
+int append_runtime_bootconfig(char *bootconfig, uint32_t *size, void *fdt_addr);
+int32_t add_bootconfig_trailer(uint64_t bootconfig_start_addr, uint32_t bootconfig_size);
 
 /**
  * board_fit_config_name_match() - Check for a matching board name
diff --git a/include/imx8_hdmi.h b/include/imx8_hdmi.h
new file mode 100644
index 00000000000..eb1253cf51f
--- /dev/null
+++ b/include/imx8_hdmi.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __IMX8_HDMI_H__
+#define __IMX8_HDMI_H__
+
+int imx8_hdmi_enable(int encoding, struct video_mode_settings *vms);
+void imx8_hdmi_disable(void);
+
+#endif /* __IMX8_HDMI_H__*/
diff --git a/include/imx8image.h b/include/imx8image.h
index 00c614ab6cc..3705460512d 100644
--- a/include/imx8image.h
+++ b/include/imx8image.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
  *
  * Peng Fan <peng.fan@nxp.com>
  */
@@ -180,7 +180,8 @@ enum imx8image_fld_types {
 typedef enum SOC_TYPE {
 	NONE = 0,
 	QX,
-	QM
+	QM,
+	DXL
 } soc_type_t;
 
 typedef enum option_type {
diff --git a/include/imx_i3c.h b/include/imx_i3c.h
new file mode 100644
index 00000000000..5aabd36d932
--- /dev/null
+++ b/include/imx_i3c.h
@@ -0,0 +1,1170 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Register definitions for SVC I3C
+ *
+ * Copyright 2021 NXP
+ * Author: Clark Wang (xiaoning.wang@nxp.com)
+ */
+#ifndef __IMX_I3C_H__
+#define __IMX_I3C_H__
+
+#include <clk.h>
+
+struct imx_i3c_reg {
+	u32 mconfig;
+	u32 sconfig;
+	u32 sstatus;
+	u32 sctrl;
+	u32 sintset;
+	u32 sintclr;
+	u32 sintmasked;
+	u32 serrwarn;
+	u32 sdmactrl;
+	u8  reserved_0[8];
+	u32 sdatactrl;
+	u32 swdatab;
+	u32 swdatabe;
+	u32 swdatah;
+	u32 swdatahe;
+	u32 srdatab;
+	u8  reserved_1[4];
+	u32 srdatah;
+	u8  reserved_2[20];
+	u32 scapabilities;
+	u32 sdynaddr;
+	u32 smaxlimits;
+	u32 sidpartno;
+	u32 sidext;
+	u32 svendorid;
+	u32 stcclock;
+	u32 smsgmapaddr;
+	u8  reserved_3[4];
+	u32 mctrl;
+	u32 mstatus;
+	u32 mibirules;
+	u32 mintset;
+	u32 mintclr;
+	u32 mintmasked;
+	u32 merrwarn;
+	u32 mdmactrl;
+	u8  reserved_4[8];
+	u32 mdatactrl;
+	u32 mwdatab;
+	u32 mwdatabe;
+	u32 mwdatah;
+	u32 mwdatahe;
+	u32 mrdatab;
+	u8  reserved_5[4];
+	u32 mrdatah;
+	u32 mwmsg_sdr_data; /* the same addr with mwmsg_sdr_control */
+	u32 mrmsg_sdr;
+	u32 mwmsg_ddr_data; /* the same addr with mwmsg_ddr_control */
+	u32 mrmsg_ddr;
+	u8  reserved_6[4];
+	u32 mdynaddr;
+	u8  reserved_7[3860];
+	u32 sid;
+};
+
+typedef enum i3c_master_state {
+	I3C_MASTERSTATE_IDLE    = 0U, /* Bus stopped. */
+	I3C_MASTERSTATE_SLVREQ  = 1U, /* Bus stopped but slave holding SDA low. */
+	I3C_MASTERSTATE_MSGSDR  = 2U, /* In SDR Message mode from using MWMSG_SDR. */
+	I3C_MASTERSTATE_NORMACT = 3U, /* In normal active SDR mode. */
+	I3C_MASTERSTATE_DDR     = 4U, /* In DDR Message mode. */
+	I3C_MASTERSTATE_DAA     = 5U, /* In ENTDAA mode. */
+	I3C_MASTERSTATE_IBIACK  = 6U, /* Waiting on IBI ACK/NACK decision. */
+	I3C_MASTERSTATE_IBIRCV  = 7U, /* receiving IBI. */
+} i3c_master_state_t;
+
+typedef enum i3c_status {
+	I3C_SUCESS = 0,
+	I3C_BUSY,/* The master is already performing a transfer. */
+	I3C_IDLE,  /* The slave driver is idle. */
+	I3C_NACK,  /* The slave device sent a NAK in response to an address. */
+	I3C_WRITE_ABORT_ERR,  /* The slave device sent a NAK in response to a write. */
+	I3C_TERM,  /* The master terminates slave read. */
+	I3C_HDR_PARITY_ERR,  /* Parity error from DDR read. */
+	I3C_CRC_ERR,  /* CRC error from DDR read. */
+	I3C_READFIFO_ERR,  /* Read from M/SRDATAB register when FIFO empty. */
+	I3C_WRITEFIFO_ERR,  /* Write to M/SWDATAB register when FIFO full. */
+	I3C_MSG_ERR,  /* Message SDR/DDR mismatch or read/write message in wrong state */
+	I3C_INVALID_REQ,  /* Invalid use of request. */
+	I3C_TIMEOUT,  /* The module has stalled too long in a frame. */
+	I3C_SLAVE_COUNT_EXCEED,  /* The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. */
+	I3C_IBI_WON,  /* The I3C slave event IBI or MR or HJ won the arbitration on a header address. */
+	I3C_OVERRUN_ERR,  /* Slave internal from-bus buffer/FIFO overrun. */
+	I3C_UNDERRUN_ERR,  /* Slave internal to-bus buffer/FIFO underrun */
+	I3C_UNDERRUN_NACK_ERR,  /* Slave internal from-bus buffer/FIFO underrun and NACK error */
+	I3C_INVALID_START,  /* Slave invalid start flag */
+	I3C_SDR_PARITY_ERR,  /* SDR parity error */
+	I3C_SO_S1_ERR,  /* S0 or S1 error */
+} i3c_status_t;
+
+/* I3C Register Masks */
+
+/* MCONFIG - Master Configuration Register */
+#define I3C_MCONFIG_MSTENA_MASK                  (0x3U)
+#define I3C_MCONFIG_MSTENA_SHIFT                 (0U)
+/* MSTENA - Master enable
+ *  0b00..MASTER_OFF: Master is off (is not enabled). If MASTER_OFF is enabled, then the I3C module can only use slave mode.
+ *  0b01..MASTER_ON: Master is on (is enabled). When used from start-up, this I3C module is master by default (the
+ *        main master). The module will control the bus unless the master is handed off. If the master is handed
+ *        off, then MSTENA must move to 2 after that happens. The handoff means emitting GETACCMST and if accepted,
+ *        the module will emit a STOP and set the MSTENA bit to 2 (or 0).
+ *  0b10..MASTER_CAPABLE: The I3C module is master-capable; however the module is operating as a slave now. When
+ *        used from the start, the I3C module will start as a slave, but will be prepared to switch to master mode.
+ *        To switch to master mode, the slave emits an Master Request (MR), or gets a GETACCMST CCC command and
+ *        accepts it (to switch on the STOP).
+ *  0b11..RESERVED
+ */
+#define I3C_MCONFIG_MSTENA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK)
+#define I3C_MCONFIG_DISTO_MASK                   (0x8U)
+#define I3C_MCONFIG_DISTO_SHIFT                  (3U)
+#define I3C_MCONFIG_DISTO(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK)
+#define I3C_MCONFIG_HKEEP_MASK                   (0x30U)
+#define I3C_MCONFIG_HKEEP_SHIFT                  (4U)
+/* HKEEP - High-Keeper
+ *  0b00..NONE: Use PUR (Pull-Up Resistor). Hold SCL High.
+ *  0b01..WIRED_IN: Wired-in High Keeper controls; use pin_HK (High Keeper) controls.
+ *  0b10..PASSIVE_SDA: Passive on SDA; can Hi-Z (high impedance) for Bus Free (IDLE) and hold.
+ *  0b11..PASSIVE_ON_SDA_SCL: Passive on SDA and SCL; can Hi-Z (high impedance) both for Bus Free (IDLE), and can Hi-Z SDA for hold.
+ */
+#define I3C_MCONFIG_HKEEP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK)
+#define I3C_MCONFIG_ODSTOP_MASK                  (0x40U)
+#define I3C_MCONFIG_ODSTOP_SHIFT                 (6U)
+#define I3C_MCONFIG_ODSTOP(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK)
+#define I3C_MCONFIG_PPBAUD_MASK                  (0xF00U)
+#define I3C_MCONFIG_PPBAUD_SHIFT                 (8U)
+#define I3C_MCONFIG_PPBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK)
+#define I3C_MCONFIG_PPLOW_MASK                   (0xF000U)
+#define I3C_MCONFIG_PPLOW_SHIFT                  (12U)
+#define I3C_MCONFIG_PPLOW(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK)
+#define I3C_MCONFIG_ODBAUD_MASK                  (0xFF0000U)
+#define I3C_MCONFIG_ODBAUD_SHIFT                 (16U)
+#define I3C_MCONFIG_ODBAUD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK)
+#define I3C_MCONFIG_ODHPP_MASK                   (0x1000000U)
+#define I3C_MCONFIG_ODHPP_SHIFT                  (24U)
+#define I3C_MCONFIG_ODHPP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK)
+#define I3C_MCONFIG_SKEW_MASK                    (0xE000000U)
+#define I3C_MCONFIG_SKEW_SHIFT                   (25U)
+#define I3C_MCONFIG_SKEW(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK)
+#define I3C_MCONFIG_I2CBAUD_MASK                 (0xF0000000U)
+#define I3C_MCONFIG_I2CBAUD_SHIFT                (28U)
+#define I3C_MCONFIG_I2CBAUD(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK)
+
+/* SCONFIG - Slave Configuration Register */
+#define I3C_SCONFIG_SLVENA_MASK                  (0x1U)
+#define I3C_SCONFIG_SLVENA_SHIFT                 (0U)
+#define I3C_SCONFIG_SLVENA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK)
+#define I3C_SCONFIG_NACK_MASK                    (0x2U)
+#define I3C_SCONFIG_NACK_SHIFT                   (1U)
+#define I3C_SCONFIG_NACK(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK)
+#define I3C_SCONFIG_MATCHSS_MASK                 (0x4U)
+#define I3C_SCONFIG_MATCHSS_SHIFT                (2U)
+#define I3C_SCONFIG_MATCHSS(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK)
+#define I3C_SCONFIG_S0IGNORE_MASK                (0x8U)
+#define I3C_SCONFIG_S0IGNORE_SHIFT               (3U)
+#define I3C_SCONFIG_S0IGNORE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK)
+#define I3C_SCONFIG_DDROK_MASK                   (0x10U)
+#define I3C_SCONFIG_DDROK_SHIFT                  (4U)
+#define I3C_SCONFIG_DDROK(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_DDROK_SHIFT)) & I3C_SCONFIG_DDROK_MASK)
+#define I3C_SCONFIG_IDRAND_MASK                  (0x100U)
+#define I3C_SCONFIG_IDRAND_SHIFT                 (8U)
+#define I3C_SCONFIG_IDRAND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_IDRAND_SHIFT)) & I3C_SCONFIG_IDRAND_MASK)
+#define I3C_SCONFIG_OFFLINE_MASK                 (0x200U)
+#define I3C_SCONFIG_OFFLINE_SHIFT                (9U)
+#define I3C_SCONFIG_OFFLINE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK)
+#define I3C_SCONFIG_BAMATCH_MASK                 (0xFF0000U)
+#define I3C_SCONFIG_BAMATCH_SHIFT                (16U)
+#define I3C_SCONFIG_BAMATCH(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK)
+#define I3C_SCONFIG_SADDR_MASK                   (0xFE000000U)
+#define I3C_SCONFIG_SADDR_SHIFT                  (25U)
+#define I3C_SCONFIG_SADDR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK)
+
+/* SSTATUS - Slave Status Register */
+#define I3C_SSTATUS_STNOTSTOP_MASK               (0x1U)
+#define I3C_SSTATUS_STNOTSTOP_SHIFT              (0U)
+#define I3C_SSTATUS_STNOTSTOP(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK)
+#define I3C_SSTATUS_STMSG_MASK                   (0x2U)
+#define I3C_SSTATUS_STMSG_SHIFT                  (1U)
+#define I3C_SSTATUS_STMSG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK)
+#define I3C_SSTATUS_STCCCH_MASK                  (0x4U)
+#define I3C_SSTATUS_STCCCH_SHIFT                 (2U)
+#define I3C_SSTATUS_STCCCH(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK)
+#define I3C_SSTATUS_STREQRD_MASK                 (0x8U)
+#define I3C_SSTATUS_STREQRD_SHIFT                (3U)
+#define I3C_SSTATUS_STREQRD(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK)
+#define I3C_SSTATUS_STREQWR_MASK                 (0x10U)
+#define I3C_SSTATUS_STREQWR_SHIFT                (4U)
+#define I3C_SSTATUS_STREQWR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK)
+#define I3C_SSTATUS_STDAA_MASK                   (0x20U)
+#define I3C_SSTATUS_STDAA_SHIFT                  (5U)
+#define I3C_SSTATUS_STDAA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK)
+#define I3C_SSTATUS_STHDR_MASK                   (0x40U)
+#define I3C_SSTATUS_STHDR_SHIFT                  (6U)
+#define I3C_SSTATUS_STHDR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK)
+#define I3C_SSTATUS_START_MASK                   (0x100U)
+#define I3C_SSTATUS_START_SHIFT                  (8U)
+#define I3C_SSTATUS_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK)
+#define I3C_SSTATUS_MATCHED_MASK                 (0x200U)
+#define I3C_SSTATUS_MATCHED_SHIFT                (9U)
+#define I3C_SSTATUS_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK)
+#define I3C_SSTATUS_STOP_MASK                    (0x400U)
+#define I3C_SSTATUS_STOP_SHIFT                   (10U)
+#define I3C_SSTATUS_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK)
+#define I3C_SSTATUS_RX_PEND_MASK                 (0x800U)
+#define I3C_SSTATUS_RX_PEND_SHIFT                (11U)
+#define I3C_SSTATUS_RX_PEND(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK)
+#define I3C_SSTATUS_TXNOTFULL_MASK               (0x1000U)
+#define I3C_SSTATUS_TXNOTFULL_SHIFT              (12U)
+#define I3C_SSTATUS_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK)
+#define I3C_SSTATUS_DACHG_MASK                   (0x2000U)
+#define I3C_SSTATUS_DACHG_SHIFT                  (13U)
+#define I3C_SSTATUS_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK)
+#define I3C_SSTATUS_CCC_MASK                     (0x4000U)
+#define I3C_SSTATUS_CCC_SHIFT                    (14U)
+#define I3C_SSTATUS_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK)
+#define I3C_SSTATUS_ERRWARN_MASK                 (0x8000U)
+#define I3C_SSTATUS_ERRWARN_SHIFT                (15U)
+#define I3C_SSTATUS_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK)
+#define I3C_SSTATUS_HDRMATCH_MASK                (0x10000U)
+#define I3C_SSTATUS_HDRMATCH_SHIFT               (16U)
+#define I3C_SSTATUS_HDRMATCH(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK)
+#define I3C_SSTATUS_CHANDLED_MASK                (0x20000U)
+#define I3C_SSTATUS_CHANDLED_SHIFT               (17U)
+#define I3C_SSTATUS_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK)
+#define I3C_SSTATUS_EVENT_MASK                   (0x40000U)
+#define I3C_SSTATUS_EVENT_SHIFT                  (18U)
+#define I3C_SSTATUS_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK)
+#define I3C_SSTATUS_EVDET_MASK                   (0x300000U)
+#define I3C_SSTATUS_EVDET_SHIFT                  (20U)
+/* EVDET - Event details
+ *  0b00..NONE: no event or no pending event
+ *  0b01..NO_REQUEST: Request not sent yet. Either there was no START yet, or is waiting for Bus-Available or Bus-Idle (HJ).
+ *  0b10..NACKED: Not acknowledged(Request sent and NACKed); the module will try again.
+ *  0b11..ACKED: Acknowledged (Request sent and ACKed), so Done (unless the time control data is still being sent).
+ */
+#define I3C_SSTATUS_EVDET(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK)
+#define I3C_SSTATUS_IBIDIS_MASK                  (0x1000000U)
+#define I3C_SSTATUS_IBIDIS_SHIFT                 (24U)
+#define I3C_SSTATUS_IBIDIS(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK)
+#define I3C_SSTATUS_MRDIS_MASK                   (0x2000000U)
+#define I3C_SSTATUS_MRDIS_SHIFT                  (25U)
+#define I3C_SSTATUS_MRDIS(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK)
+#define I3C_SSTATUS_HJDIS_MASK                   (0x8000000U)
+#define I3C_SSTATUS_HJDIS_SHIFT                  (27U)
+#define I3C_SSTATUS_HJDIS(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK)
+#define I3C_SSTATUS_ACTSTATE_MASK                (0x30000000U)
+#define I3C_SSTATUS_ACTSTATE_SHIFT               (28U)
+/* ACTSTATE - Activity state from Common Command Codes (CCC)
+ *  0b00..NO_LATENCY: normal bus operations
+ *  0b01..LATENCY_1MS: 1 ms of latency
+ *  0b10..LATENCY_100MS: 100 ms of latency
+ *  0b11..LATENCY_10S: 10 seconds of latency
+ */
+#define I3C_SSTATUS_ACTSTATE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK)
+#define I3C_SSTATUS_TIMECTRL_MASK                (0xC0000000U)
+#define I3C_SSTATUS_TIMECTRL_SHIFT               (30U)
+/* TIMECTRL - Time control
+ *  0b00..NO_TIME_CONTROL: No time control is enabled
+ *  0b01..Reserved
+ *  0b10..ASYNC_MODE: Asynchronous standard mode (0) is enabled
+ *  0b11..RESERVED
+ */
+#define I3C_SSTATUS_TIMECTRL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK)
+
+/* SCTRL - Slave Control Register */
+#define I3C_SCTRL_EVENT_MASK                     (0x3U)
+#define I3C_SCTRL_EVENT_SHIFT                    (0U)
+/* EVENT - EVENT
+ *  0b00..NORMAL_MODE: If EVENT is set to 0 after was a non-0 value, event processing will cancel if the event
+ *        processing has not yet started; if event processing has already been started, then event processing will not
+ *        be be cancelled.
+ *  0b01..IBI: Start an In-Band Interrupt. This will try to push an IBI interrupt onto the I3C bus. If data is
+ *        associated with the IBI, then the data will be read from the SCTRL.IBIDATA field. If time control is
+ *        enabled, then this data will also include any time control-related bytes; additionally, the IBIDATA byte will
+ *        have bit 7 set to 1 automatically (as is required for time control). The IBI interrupt will occur after the
+ *        1st (mandatory) IBIDATA, if any.
+ *  0b10..MASTER_REQUEST: Start a Master-Request.
+ *  0b11..HOT_JOIN_REQUEST: Start a Hot-Join request. A Hot-Join Request should only be used when the device is
+ *        powered on after the I3C bus is already powered up, or when the device is connected using hot insertion
+ *        methods (the device is powered up when it is physically inserted onto the powered-up I3C bus). The hot join
+ *        will wait for Bus Idle, and SCTRL.EVENT=HOT_JOIN_REQUEST must be set before the slave enable
+ *        (SCONFIG.SLVENA).
+ */
+#define I3C_SCTRL_EVENT(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK)
+#define I3C_SCTRL_IBIDATA_MASK                   (0xFF00U)
+#define I3C_SCTRL_IBIDATA_SHIFT                  (8U)
+#define I3C_SCTRL_IBIDATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK)
+#define I3C_SCTRL_PENDINT_MASK                   (0xF0000U)
+#define I3C_SCTRL_PENDINT_SHIFT                  (16U)
+#define I3C_SCTRL_PENDINT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK)
+#define I3C_SCTRL_ACTSTATE_MASK                  (0x300000U)
+#define I3C_SCTRL_ACTSTATE_SHIFT                 (20U)
+#define I3C_SCTRL_ACTSTATE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK)
+#define I3C_SCTRL_VENDINFO_MASK                  (0xFF000000U)
+#define I3C_SCTRL_VENDINFO_SHIFT                 (24U)
+#define I3C_SCTRL_VENDINFO(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK)
+
+/* SINTSET - Slave Interrupt Set Register */
+#define I3C_SINTSET_START_MASK                   (0x100U)
+#define I3C_SINTSET_START_SHIFT                  (8U)
+#define I3C_SINTSET_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK)
+#define I3C_SINTSET_MATCHED_MASK                 (0x200U)
+#define I3C_SINTSET_MATCHED_SHIFT                (9U)
+#define I3C_SINTSET_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK)
+#define I3C_SINTSET_STOP_MASK                    (0x400U)
+#define I3C_SINTSET_STOP_SHIFT                   (10U)
+#define I3C_SINTSET_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK)
+#define I3C_SINTSET_RXPEND_MASK                  (0x800U)
+#define I3C_SINTSET_RXPEND_SHIFT                 (11U)
+#define I3C_SINTSET_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK)
+#define I3C_SINTSET_TXSEND_MASK                  (0x1000U)
+#define I3C_SINTSET_TXSEND_SHIFT                 (12U)
+#define I3C_SINTSET_TXSEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK)
+#define I3C_SINTSET_DACHG_MASK                   (0x2000U)
+#define I3C_SINTSET_DACHG_SHIFT                  (13U)
+#define I3C_SINTSET_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK)
+#define I3C_SINTSET_CCC_MASK                     (0x4000U)
+#define I3C_SINTSET_CCC_SHIFT                    (14U)
+#define I3C_SINTSET_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK)
+#define I3C_SINTSET_ERRWARN_MASK                 (0x8000U)
+#define I3C_SINTSET_ERRWARN_SHIFT                (15U)
+#define I3C_SINTSET_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK)
+#define I3C_SINTSET_DDRMATCHED_MASK              (0x10000U)
+#define I3C_SINTSET_DDRMATCHED_SHIFT             (16U)
+#define I3C_SINTSET_DDRMATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK)
+#define I3C_SINTSET_CHANDLED_MASK                (0x20000U)
+#define I3C_SINTSET_CHANDLED_SHIFT               (17U)
+#define I3C_SINTSET_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK)
+#define I3C_SINTSET_EVENT_MASK                   (0x40000U)
+#define I3C_SINTSET_EVENT_SHIFT                  (18U)
+#define I3C_SINTSET_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK)
+
+/* SINTCLR - Slave Interrupt Clear Register */
+#define I3C_SINTCLR_START_MASK                   (0x100U)
+#define I3C_SINTCLR_START_SHIFT                  (8U)
+#define I3C_SINTCLR_START(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK)
+#define I3C_SINTCLR_MATCHED_MASK                 (0x200U)
+#define I3C_SINTCLR_MATCHED_SHIFT                (9U)
+#define I3C_SINTCLR_MATCHED(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK)
+#define I3C_SINTCLR_STOP_MASK                    (0x400U)
+#define I3C_SINTCLR_STOP_SHIFT                   (10U)
+#define I3C_SINTCLR_STOP(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK)
+#define I3C_SINTCLR_RXPEND_MASK                  (0x800U)
+#define I3C_SINTCLR_RXPEND_SHIFT                 (11U)
+#define I3C_SINTCLR_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK)
+#define I3C_SINTCLR_TXSEND_MASK                  (0x1000U)
+#define I3C_SINTCLR_TXSEND_SHIFT                 (12U)
+#define I3C_SINTCLR_TXSEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK)
+#define I3C_SINTCLR_DACHG_MASK                   (0x2000U)
+#define I3C_SINTCLR_DACHG_SHIFT                  (13U)
+#define I3C_SINTCLR_DACHG(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK)
+#define I3C_SINTCLR_CCC_MASK                     (0x4000U)
+#define I3C_SINTCLR_CCC_SHIFT                    (14U)
+#define I3C_SINTCLR_CCC(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK)
+#define I3C_SINTCLR_ERRWARN_MASK                 (0x8000U)
+#define I3C_SINTCLR_ERRWARN_SHIFT                (15U)
+#define I3C_SINTCLR_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK)
+#define I3C_SINTCLR_DDRMATCHED_MASK              (0x10000U)
+#define I3C_SINTCLR_DDRMATCHED_SHIFT             (16U)
+#define I3C_SINTCLR_DDRMATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK)
+#define I3C_SINTCLR_CHANDLED_MASK                (0x20000U)
+#define I3C_SINTCLR_CHANDLED_SHIFT               (17U)
+#define I3C_SINTCLR_CHANDLED(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK)
+#define I3C_SINTCLR_EVENT_MASK                   (0x40000U)
+#define I3C_SINTCLR_EVENT_SHIFT                  (18U)
+#define I3C_SINTCLR_EVENT(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK)
+
+/* SINTMASKED - Slave Interrupt Mask Register */
+#define I3C_SINTMASKED_START_MASK                (0x100U)
+#define I3C_SINTMASKED_START_SHIFT               (8U)
+#define I3C_SINTMASKED_START(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK)
+#define I3C_SINTMASKED_MATCHED_MASK              (0x200U)
+#define I3C_SINTMASKED_MATCHED_SHIFT             (9U)
+#define I3C_SINTMASKED_MATCHED(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK)
+#define I3C_SINTMASKED_STOP_MASK                 (0x400U)
+#define I3C_SINTMASKED_STOP_SHIFT                (10U)
+#define I3C_SINTMASKED_STOP(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK)
+#define I3C_SINTMASKED_RXPEND_MASK               (0x800U)
+#define I3C_SINTMASKED_RXPEND_SHIFT              (11U)
+#define I3C_SINTMASKED_RXPEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK)
+#define I3C_SINTMASKED_TXSEND_MASK               (0x1000U)
+#define I3C_SINTMASKED_TXSEND_SHIFT              (12U)
+#define I3C_SINTMASKED_TXSEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK)
+#define I3C_SINTMASKED_DACHG_MASK                (0x2000U)
+#define I3C_SINTMASKED_DACHG_SHIFT               (13U)
+#define I3C_SINTMASKED_DACHG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK)
+#define I3C_SINTMASKED_CCC_MASK                  (0x4000U)
+#define I3C_SINTMASKED_CCC_SHIFT                 (14U)
+#define I3C_SINTMASKED_CCC(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK)
+#define I3C_SINTMASKED_ERRWARN_MASK              (0x8000U)
+#define I3C_SINTMASKED_ERRWARN_SHIFT             (15U)
+#define I3C_SINTMASKED_ERRWARN(x)                (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK)
+#define I3C_SINTMASKED_DDRMATCHED_MASK           (0x10000U)
+#define I3C_SINTMASKED_DDRMATCHED_SHIFT          (16U)
+#define I3C_SINTMASKED_DDRMATCHED(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK)
+#define I3C_SINTMASKED_CHANDLED_MASK             (0x20000U)
+#define I3C_SINTMASKED_CHANDLED_SHIFT            (17U)
+#define I3C_SINTMASKED_CHANDLED(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK)
+#define I3C_SINTMASKED_EVENT_MASK                (0x40000U)
+#define I3C_SINTMASKED_EVENT_SHIFT               (18U)
+#define I3C_SINTMASKED_EVENT(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK)
+
+/* SERRWARN - Slave Errors and Warnings Register */
+#define I3C_SERRWARN_ORUN_MASK                   (0x1U)
+#define I3C_SERRWARN_ORUN_SHIFT                  (0U)
+#define I3C_SERRWARN_ORUN(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK)
+#define I3C_SERRWARN_URUN_MASK                   (0x2U)
+#define I3C_SERRWARN_URUN_SHIFT                  (1U)
+#define I3C_SERRWARN_URUN(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK)
+#define I3C_SERRWARN_URUNNACK_MASK               (0x4U)
+#define I3C_SERRWARN_URUNNACK_SHIFT              (2U)
+#define I3C_SERRWARN_URUNNACK(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK)
+#define I3C_SERRWARN_TERM_MASK                   (0x8U)
+#define I3C_SERRWARN_TERM_SHIFT                  (3U)
+#define I3C_SERRWARN_TERM(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK)
+#define I3C_SERRWARN_INVSTART_MASK               (0x10U)
+#define I3C_SERRWARN_INVSTART_SHIFT              (4U)
+#define I3C_SERRWARN_INVSTART(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK)
+#define I3C_SERRWARN_SPAR_MASK                   (0x100U)
+#define I3C_SERRWARN_SPAR_SHIFT                  (8U)
+#define I3C_SERRWARN_SPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK)
+#define I3C_SERRWARN_HPAR_MASK                   (0x200U)
+#define I3C_SERRWARN_HPAR_SHIFT                  (9U)
+#define I3C_SERRWARN_HPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK)
+#define I3C_SERRWARN_HCRC_MASK                   (0x400U)
+#define I3C_SERRWARN_HCRC_SHIFT                  (10U)
+#define I3C_SERRWARN_HCRC(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK)
+#define I3C_SERRWARN_S0S1_MASK                   (0x800U)
+#define I3C_SERRWARN_S0S1_SHIFT                  (11U)
+#define I3C_SERRWARN_S0S1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK)
+#define I3C_SERRWARN_OREAD_MASK                  (0x10000U)
+#define I3C_SERRWARN_OREAD_SHIFT                 (16U)
+#define I3C_SERRWARN_OREAD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK)
+#define I3C_SERRWARN_OWRITE_MASK                 (0x20000U)
+#define I3C_SERRWARN_OWRITE_SHIFT                (17U)
+#define I3C_SERRWARN_OWRITE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK)
+
+/* SDMACTRL - Slave DMA Control Register */
+#define I3C_SDMACTRL_DMAFB_MASK                  (0x3U)
+#define I3C_SDMACTRL_DMAFB_SHIFT                 (0U)
+/* DMAFB - DMA Read (From-bus) trigger
+ *  0b00..DMA not used
+ *  0b01..DMA is enabled for 1 frame
+ *  0b10..DMA enable
+ */
+#define I3C_SDMACTRL_DMAFB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK)
+#define I3C_SDMACTRL_DMATB_MASK                  (0xCU)
+#define I3C_SDMACTRL_DMATB_SHIFT                 (2U)
+/* DMATB - DMA Write (To-bus) trigger
+ *  0b00..NOT_USED: DMA is not used
+ *  0b01..ENABLE_ONE_FRAME: DMA is enabled for 1 Frame (ended by DMA or terminated). DMATB auto-clears on a STOP
+ *        or START (see the Match START or STOP bit (SCONFIG.MATCHSS).
+ *  0b10..ENABLE: DMA is enabled until turned off. Normally, ENABLE should only be used with Master Message mode.
+ */
+#define I3C_SDMACTRL_DMATB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK)
+#define I3C_SDMACTRL_DMAWIDTH_MASK               (0x30U)
+#define I3C_SDMACTRL_DMAWIDTH_SHIFT              (4U)
+/* DMAWIDTH - Width of DMA operations
+ *  0b00..BYTE
+ *  0b01..BYTE_AGAIN
+ *  0b10..HALF_WORD: Half word (16 bits). This will make sure that 2 bytes are free/available in the FIFO.
+ *  0b11..RESERVED
+ */
+#define I3C_SDMACTRL_DMAWIDTH(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK)
+
+/* SDATACTRL - Slave Data Control Register */
+#define I3C_SDATACTRL_FLUSHTB_MASK               (0x1U)
+#define I3C_SDATACTRL_FLUSHTB_SHIFT              (0U)
+#define I3C_SDATACTRL_FLUSHTB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK)
+#define I3C_SDATACTRL_FLUSHFB_MASK               (0x2U)
+#define I3C_SDATACTRL_FLUSHFB_SHIFT              (1U)
+#define I3C_SDATACTRL_FLUSHFB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK)
+#define I3C_SDATACTRL_UNLOCK_MASK                (0x8U)
+#define I3C_SDATACTRL_UNLOCK_SHIFT               (3U)
+#define I3C_SDATACTRL_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK)
+#define I3C_SDATACTRL_TXTRIG_MASK                (0x30U)
+#define I3C_SDATACTRL_TXTRIG_SHIFT               (4U)
+/* TXTRIG - Trigger level for TX FIFO emptiness
+ *  0b00..Trigger on empty
+ *  0b01..Trigger on ¼ full or less
+ *  0b10..Trigger on .5 full or less
+ *  0b11..Trigger on 1 less than full or less (Default)
+ */
+#define I3C_SDATACTRL_TXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK)
+#define I3C_SDATACTRL_RXTRIG_MASK                (0xC0U)
+#define I3C_SDATACTRL_RXTRIG_SHIFT               (6U)
+/* RXTRIG - Trigger level for RX FIFO fullness
+ *  0b00..Trigger on not empty
+ *  0b01..Trigger on ¼ or more full
+ *  0b10..Trigger on .5 or more full
+ *  0b11..Trigger on 3/4 or more full
+ */
+#define I3C_SDATACTRL_RXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK)
+#define I3C_SDATACTRL_TXCOUNT_MASK               (0x1F0000U)
+#define I3C_SDATACTRL_TXCOUNT_SHIFT              (16U)
+#define I3C_SDATACTRL_TXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK)
+#define I3C_SDATACTRL_RXCOUNT_MASK               (0x1F000000U)
+#define I3C_SDATACTRL_RXCOUNT_SHIFT              (24U)
+#define I3C_SDATACTRL_RXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK)
+#define I3C_SDATACTRL_TXFULL_MASK                (0x40000000U)
+#define I3C_SDATACTRL_TXFULL_SHIFT               (30U)
+/* TXFULL - TX is full
+ *  0b1..TX is full
+ *  0b0..TX is not full
+ */
+#define I3C_SDATACTRL_TXFULL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK)
+#define I3C_SDATACTRL_RXEMPTY_MASK               (0x80000000U)
+#define I3C_SDATACTRL_RXEMPTY_SHIFT              (31U)
+/* RXEMPTY - RX is empty
+ *  0b1..RX is empty
+ *  0b0..RX is not empty
+ */
+#define I3C_SDATACTRL_RXEMPTY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK)
+
+/* SWDATAB - Slave Write Data Byte Register */
+#define I3C_SWDATAB_DATA_MASK                    (0xFFU)
+#define I3C_SWDATAB_DATA_SHIFT                   (0U)
+#define I3C_SWDATAB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK)
+#define I3C_SWDATAB_END_MASK                     (0x100U)
+#define I3C_SWDATAB_END_SHIFT                    (8U)
+#define I3C_SWDATAB_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK)
+#define I3C_SWDATAB_END_ALSO_MASK                (0x10000U)
+#define I3C_SWDATAB_END_ALSO_SHIFT               (16U)
+#define I3C_SWDATAB_END_ALSO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK)
+
+/* SWDATABE - Slave Write Data Byte End */
+#define I3C_SWDATABE_DATA_MASK                   (0xFFU)
+#define I3C_SWDATABE_DATA_SHIFT                  (0U)
+#define I3C_SWDATABE_DATA(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK)
+
+/* SWDATAH - Slave Write Data Half-word Register */
+#define I3C_SWDATAH_DATA0_MASK                   (0xFFU)
+#define I3C_SWDATAH_DATA0_SHIFT                  (0U)
+#define I3C_SWDATAH_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK)
+#define I3C_SWDATAH_DATA1_MASK                   (0xFF00U)
+#define I3C_SWDATAH_DATA1_SHIFT                  (8U)
+#define I3C_SWDATAH_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK)
+#define I3C_SWDATAH_END_MASK                     (0x10000U)
+#define I3C_SWDATAH_END_SHIFT                    (16U)
+#define I3C_SWDATAH_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK)
+
+/* SWDATAHE - Slave Write Data Half-word End Register */
+#define I3C_SWDATAHE_DATA0_MASK                  (0xFFU)
+#define I3C_SWDATAHE_DATA0_SHIFT                 (0U)
+#define I3C_SWDATAHE_DATA0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK)
+#define I3C_SWDATAHE_DATA1_MASK                  (0xFF00U)
+#define I3C_SWDATAHE_DATA1_SHIFT                 (8U)
+#define I3C_SWDATAHE_DATA1(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK)
+
+/* SRDATAB - Slave Read Data Byte Register */
+#define I3C_SRDATAB_DATA0_MASK                   (0xFFU)
+#define I3C_SRDATAB_DATA0_SHIFT                  (0U)
+#define I3C_SRDATAB_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK)
+
+/* SRDATAH - Slave Read Data Half-word Register */
+#define I3C_SRDATAH_LSB_MASK                     (0xFFU)
+#define I3C_SRDATAH_LSB_SHIFT                    (0U)
+#define I3C_SRDATAH_LSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK)
+#define I3C_SRDATAH_MSB_MASK                     (0xFF00U)
+#define I3C_SRDATAH_MSB_SHIFT                    (8U)
+#define I3C_SRDATAH_MSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK)
+
+/* SCAPABILITIES - Slave Capabilities Register */
+#define I3C_SCAPABILITIES_IDENA_MASK             (0x3U)
+#define I3C_SCAPABILITIES_IDENA_SHIFT            (0U)
+/* IDENA - ID 48b handler
+ *  0b00..APPLICATION: Application handles ID 48b
+ *  0b01..HW: Hardware handles ID 48b
+ *  0b10..HW_BUT: in hardware but the I3C module instance handles ID 48b.
+ *  0b11..PARTNO: a part number register (PARTNO) handles ID 48b
+ */
+#define I3C_SCAPABILITIES_IDENA(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK)
+#define I3C_SCAPABILITIES_IDREG_MASK             (0x3CU)
+#define I3C_SCAPABILITIES_IDREG_SHIFT            (2U)
+#define I3C_SCAPABILITIES_IDREG(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK)
+#define I3C_SCAPABILITIES_HDRSUPP_MASK           (0x1C0U)
+#define I3C_SCAPABILITIES_HDRSUPP_SHIFT          (6U)
+#define I3C_SCAPABILITIES_HDRSUPP(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK)
+#define I3C_SCAPABILITIES_MASTER_MASK            (0x200U)
+#define I3C_SCAPABILITIES_MASTER_SHIFT           (9U)
+/* MASTER - Master
+ *  0b0..MASTERNOTSUPPORTED: master capability is not supported.
+ *  0b1..MASTERSUPPORTED: master capability is supported.
+ */
+#define I3C_SCAPABILITIES_MASTER(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK)
+#define I3C_SCAPABILITIES_SADDR_MASK             (0xC00U)
+#define I3C_SCAPABILITIES_SADDR_SHIFT            (10U)
+/* SADDR - Static address
+ *  0b00..NO_STATIC: No static address
+ *  0b01..STATIC: Static address is fixed in hardware
+ *  0b10..HW_CONTROL: Hardware controls the static address dynamically (for example, from the pin strap)
+ *  0b11..CONFIG: SCONFIG register supplies the static address
+ */
+#define I3C_SCAPABILITIES_SADDR(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK)
+#define I3C_SCAPABILITIES_CCCHANDLE_MASK         (0xF000U)
+#define I3C_SCAPABILITIES_CCCHANDLE_SHIFT        (12U)
+#define I3C_SCAPABILITIES_CCCHANDLE(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK)
+#define I3C_SCAPABILITIES_IBI_MR_HJ_MASK         (0x1F0000U)
+#define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT        (16U)
+#define I3C_SCAPABILITIES_IBI_MR_HJ(x)           (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK)
+#define I3C_SCAPABILITIES_TIMECTRL_MASK          (0x200000U)
+#define I3C_SCAPABILITIES_TIMECTRL_SHIFT         (21U)
+/* TIMECTRL - Time control
+ *  0b0..NO_TIME_CONTROL_TYPE: No time control is enabled
+ *  0b1..ATLEAST1_TIME_CONTROL: at least one time-control type is supported
+ */
+#define I3C_SCAPABILITIES_TIMECTRL(x)            (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK)
+#define I3C_SCAPABILITIES_EXTFIFO_MASK           (0x3800000U)
+#define I3C_SCAPABILITIES_EXTFIFO_SHIFT          (23U)
+/* EXTFIFO - External FIFO
+ *  0b000..NO_EXT_FIFO: No external FIFO is available
+ *  0b001..STD_EXT_FIFO: standard available/free external FIFO
+ *  0b010..REQUEST_EXT_FIFO: request track external FIFO
+ *  0b011..RESERVED
+ */
+#define I3C_SCAPABILITIES_EXTFIFO(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK)
+#define I3C_SCAPABILITIES_FIFOTX_MASK            (0xC000000U)
+#define I3C_SCAPABILITIES_FIFOTX_SHIFT           (26U)
+/* FIFOTX - FIFO transmit
+ *  0b00..FIFO_2BYTE: 2-byte TX FIFO, the default FIFO transmit value (FIFOTX)
+ *  0b01..FIFO_4BYTE: 4-byte TX FIFO
+ *  0b10..FIFO_8BYTE: 8-byte TX FIFO
+ *  0b11..FIFO_16BYTE: 16-byte TX FIFO
+ */
+#define I3C_SCAPABILITIES_FIFOTX(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK)
+#define I3C_SCAPABILITIES_FIFORX_MASK            (0x30000000U)
+#define I3C_SCAPABILITIES_FIFORX_SHIFT           (28U)
+/* FIFORX - FIFO receive
+ *  0b00..FIFO_2BYTE: 2 (or 3)-byte RX FIFO, the default FIFO receive value (FIFORX)
+ *  0b01..FIFO_4BYTE: 4-byte RX FIFO
+ *  0b10..FIFO_8BYTE: 8-byte RX FIFO
+ *  0b11..FIFO_16BYTE: 16-byte RX FIFO
+ */
+#define I3C_SCAPABILITIES_FIFORX(x)              (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK)
+#define I3C_SCAPABILITIES_INT_MASK               (0x40000000U)
+#define I3C_SCAPABILITIES_INT_SHIFT              (30U)
+/* INT - INT
+ *  0b1..Interrupts are supported
+ *  0b0..Interrupts are not supported
+ */
+#define I3C_SCAPABILITIES_INT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK)
+#define I3C_SCAPABILITIES_DMA_MASK               (0x80000000U)
+#define I3C_SCAPABILITIES_DMA_SHIFT              (31U)
+/* DMA - DMA
+ *  0b1..DMA is supported
+ *  0b0..DMA is not supported
+ */
+#define I3C_SCAPABILITIES_DMA(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK)
+
+/* SDYNADDR - Slave Dynamic Address Register */
+#define I3C_SDYNADDR_DAVALID_MASK                (0x1U)
+#define I3C_SDYNADDR_DAVALID_SHIFT               (0U)
+/* DAVALID - DAVALID
+ *  0b0..DANOTASSIGNED: a Dynamic Address is not assigned
+ *  0b1..DAASSIGNED: a Dynamic Address is assigned
+ */
+#define I3C_SDYNADDR_DAVALID(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DAVALID_SHIFT)) & I3C_SDYNADDR_DAVALID_MASK)
+#define I3C_SDYNADDR_DADDR_MASK                  (0xFEU)
+#define I3C_SDYNADDR_DADDR_SHIFT                 (1U)
+#define I3C_SDYNADDR_DADDR(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DADDR_SHIFT)) & I3C_SDYNADDR_DADDR_MASK)
+#define I3C_SDYNADDR_MAPIDX_MASK                 (0xF00U)
+#define I3C_SDYNADDR_MAPIDX_SHIFT                (8U)
+#define I3C_SDYNADDR_MAPIDX(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPIDX_SHIFT)) & I3C_SDYNADDR_MAPIDX_MASK)
+#define I3C_SDYNADDR_MAPSA_MASK                  (0x1000U)
+#define I3C_SDYNADDR_MAPSA_SHIFT                 (12U)
+#define I3C_SDYNADDR_MAPSA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPSA_SHIFT)) & I3C_SDYNADDR_MAPSA_MASK)
+#define I3C_SDYNADDR_KEY_MASK                    (0xFFFF0000U)
+#define I3C_SDYNADDR_KEY_SHIFT                   (16U)
+#define I3C_SDYNADDR_KEY(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_KEY_SHIFT)) & I3C_SDYNADDR_KEY_MASK)
+
+/* SMAXLIMITS - Slave Maximum Limits Register */
+#define I3C_SMAXLIMITS_MAXRD_MASK                (0xFFFU)
+#define I3C_SMAXLIMITS_MAXRD_SHIFT               (0U)
+#define I3C_SMAXLIMITS_MAXRD(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK)
+#define I3C_SMAXLIMITS_MAXWR_MASK                (0xFFF0000U)
+#define I3C_SMAXLIMITS_MAXWR_SHIFT               (16U)
+#define I3C_SMAXLIMITS_MAXWR(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK)
+
+/* SIDPARTNO - Slave ID Part Number Register */
+#define I3C_SIDPARTNO_PARTNO_MASK                (0xFFFFFFFFU)
+#define I3C_SIDPARTNO_PARTNO_SHIFT               (0U)
+#define I3C_SIDPARTNO_PARTNO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK)
+
+/* SIDEXT - Slave ID Extension Register */
+#define I3C_SIDEXT_DCR_MASK                      (0xFF00U)
+#define I3C_SIDEXT_DCR_SHIFT                     (8U)
+#define I3C_SIDEXT_DCR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK)
+#define I3C_SIDEXT_BCR_MASK                      (0xFF0000U)
+#define I3C_SIDEXT_BCR_SHIFT                     (16U)
+#define I3C_SIDEXT_BCR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK)
+
+/* SVENDORID - Slave Vendor ID Register */
+#define I3C_SVENDORID_VID_MASK                   (0x7FFFU)
+#define I3C_SVENDORID_VID_SHIFT                  (0U)
+#define I3C_SVENDORID_VID(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK)
+
+/* STCCLOCK - Slave Time Control Clock Register */
+#define I3C_STCCLOCK_ACCURACY_MASK               (0xFFU)
+#define I3C_STCCLOCK_ACCURACY_SHIFT              (0U)
+#define I3C_STCCLOCK_ACCURACY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK)
+#define I3C_STCCLOCK_FREQ_MASK                   (0xFF00U)
+#define I3C_STCCLOCK_FREQ_SHIFT                  (8U)
+#define I3C_STCCLOCK_FREQ(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK)
+
+/* SMSGMAPADDR - Slave Message-Mapped Address Register */
+#define I3C_SMSGMAPADDR_MAPLAST_MASK             (0xFU)
+#define I3C_SMSGMAPADDR_MAPLAST_SHIFT            (0U)
+#define I3C_SMSGMAPADDR_MAPLAST(x)               (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK)
+#define I3C_SMSGMAPADDR_MAPLASTM1_MASK           (0xF00U)
+#define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT          (8U)
+#define I3C_SMSGMAPADDR_MAPLASTM1(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK)
+#define I3C_SMSGMAPADDR_MAPLASTM2_MASK           (0xF0000U)
+#define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT          (16U)
+#define I3C_SMSGMAPADDR_MAPLASTM2(x)             (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK)
+
+/* MCTRL - Master Main Control Register */
+#define I3C_MCTRL_REQUEST_MASK                   (0x7U)
+#define I3C_MCTRL_REQUEST_SHIFT                  (0U)
+/* REQUEST - Request
+ *  0b000..NONE: Returns to this when finished with any request. The MSTATUS register indicates the master's
+ *         state. See also AutoIBI mode. NONE is only written as 0: when setting RDTERM to 1 (to stop a read in
+ *         progress) or when setting IBI reponse field (IBIRESP) for MSG use
+ *  0b001..EMITSTARTADDR: Emit START with address and direction from a stopped state or in the middle of a Single
+ *         Data Rate (SDR) message. If from a stopped state (IDLE), then emit start may be prevented by an event
+ *         (like IBI, MR, HJ), in which case the appropriate interrupt is signaled; note that Emit START can be
+ *         resubmitted.
+ *  0b010..EMITSTOP: Emit a STOP on bus. Must be in Single Data Rate (SDR) mode. If in Dynamic Address Assignment
+ *         (DAA) mode, Emit stop will exit DAA mode.
+ *  0b011..IBIACKNACK: Manual In-Band Interrupt (IBI) Acknowledge (ACK) or Not Acknowledge (NACK). When IBIRESP
+ *         has indicated a hold on an In-Band Interrupt to allow a manual decision, this request completes it. Uses
+ *         IBIRESP to provide the information.
+ *  0b100..PROCESSDAA: If not in Dynamic Address Assignment (DAA) mode now, will issue START, 7E, ENTDAA, and then
+ *         will emit 7E/R to process each slave. Will stop just before the new Dynamic Address (DA) is to be
+ *         emitted. The next Process DAA request will use the Addr field as the new DA to assign. If NACKed on the 7E/R,
+ *         then the interrupt will indicate this situation, and a STOP will be emitted.
+ *  0b101..RESERVED
+ *  0b110..FORCEEXIT and IBHR: Emit an Exit Pattern from any state, but end Double Data Rate (DDR) (including
+ *         MSGDDR), if in DDR mode now. Includes a STOP afterward. If TYPE != 0, then it will perform an IBHR (In-Band
+ *         Hardware Reset). If TYPE=2, then it does a normal reset (DEFRST can prevent the reset). If TYPE=3, it
+ *         does a forced reset (will always reset).
+ *  0b111..AUTOIBI: Hold in a stopped state, but auto-emit START,7E when the slave is holding down SDA to get an
+ *         In-Band Interrupt (IBI). Actual In-Band Interrupt handling is defined by IBIRESP.
+ */
+#define I3C_MCTRL_REQUEST(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK)
+#define I3C_MCTRL_TYPE_MASK                      (0x30U)
+#define I3C_MCTRL_TYPE_SHIFT                     (4U)
+/* TYPE - Bus type with START
+ *  0b00..I3C: Normally the SDR mode of I3C. For ForceExit, the Exit pattern.
+ *  0b01..I2C: Normally the Standard I2C protocol.
+ *  0b10..DDR: (Double Data Rate): Normally the HDR-DDR mode of I3C. Enter DDR mode (7E and then ENTHDR0), if the
+ *        module is not already in DDR mode. The 1st byte written to the TX FIFO should be a command, and should
+ *        already be in the FIFO. To end DDR mode, use ForceExit. For ForceExit, the normal IBHR (In-Band Hardware
+ *        Reset).
+ *  0b11..For ForcedExit, this is forced IBHR.
+ */
+#define I3C_MCTRL_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK)
+#define I3C_MCTRL_IBIRESP_MASK                   (0xC0U)
+#define I3C_MCTRL_IBIRESP_SHIFT                  (6U)
+/* IBIRESP - In-Band Interrupt (IBI) response
+ *  0b00..ACK: Acknowledge. A mandatory byte (or not) is decided by the Master In-band Interrupt Registry and
+ *        Rules Register (MIBIRULES). To limit the maximum number of IBI bytes, configure the Read Termination field
+ *        (MCTRL.RDTERM).
+ *  0b01..NACK: Not acknowledge
+ *  0b10..ACK_WITH_MANDATORY: Acknowledge with mandatory byte (ignores the MIBIRULES register). Acknowledge with
+ *        mandatory byte should not be used, unless only slaves with a mandatory byte can cause an In-Band Interrupt.
+ *  0b11..MANUAL: stop and wait for a decision using the IBIAckNack request
+ */
+#define I3C_MCTRL_IBIRESP(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK)
+#define I3C_MCTRL_DIR_MASK                       (0x100U)
+#define I3C_MCTRL_DIR_SHIFT                      (8U)
+/* DIR - DIR
+ *  0b0..DIRWRITE: Write
+ *  0b1..DIRREAD: Read
+ */
+#define I3C_MCTRL_DIR(x)                         (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK)
+#define I3C_MCTRL_ADDR_MASK                      (0xFE00U)
+#define I3C_MCTRL_ADDR_SHIFT                     (9U)
+#define I3C_MCTRL_ADDR(x)                        (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK)
+#define I3C_MCTRL_RDTERM_MASK                    (0xFF0000U)
+#define I3C_MCTRL_RDTERM_SHIFT                   (16U)
+#define I3C_MCTRL_RDTERM(x)                      (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK)
+
+/* MSTATUS - Master Status Register */
+#define I3C_MSTATUS_STATE_MASK                   (0x7U)
+#define I3C_MSTATUS_STATE_SHIFT                  (0U)
+/* STATE - State of the master
+ *  0b000..IDLE: the bus has STOPped.
+ *  0b001..SLVREQ: (Slave Request state) the bus has STOPped but a slave is holding SDA low. If using auto-emit
+ *         IBI (MCTRL.AutoIBI), then the master will not stay in the Slave Request state.
+ *  0b010..MSGSDR: in Single Data Rate (SDR) Message state (from using MWMSG_SDR)
+ *  0b011..NORMACT: normal active Single Data Rate (SDR) state (from using MCTRL and MWDATAn and MRDATAn
+ *         registers). The master will stay in the NORMACT state until a STOP is issued.
+ *  0b100..MSGDDR: in Double Data Rate (DDR) Message mode (from using MWMSG_DDR or using the normal method with
+ *         DDR). The master will stay in the DDR state, until the master exits using EXIT (emits the Exit pattern).
+ *  0b101..DAA: in Enter Dynamic Address Assignment (ENTDAA) mode
+ *  0b110..IBIACK: waiting for an In-Band Interrupt (IBI) ACK/NACK decision
+ *  0b111..IBIRCV: Receiving an In-Band Interrupt (IBI); this IBIRCV state is used after IBI/MR/HJ has won the
+ *         arbitration, and IBIRCV state is also used for IBI mandatory byte (if any) and any bytes that follow.
+ */
+#define I3C_MSTATUS_STATE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK)
+#define I3C_MSTATUS_BETWEEN_MASK                 (0x10U)
+#define I3C_MSTATUS_BETWEEN_SHIFT                (4U)
+#define I3C_MSTATUS_BETWEEN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK)
+#define I3C_MSTATUS_NACKED_MASK                  (0x20U)
+#define I3C_MSTATUS_NACKED_SHIFT                 (5U)
+#define I3C_MSTATUS_NACKED(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK)
+#define I3C_MSTATUS_IBITYPE_MASK                 (0xC0U)
+#define I3C_MSTATUS_IBITYPE_SHIFT                (6U)
+/* IBITYPE - In-Band Interrupt (IBI) type
+ *  0b00..NONE: cleared when IBI Won bit (MSTATUS.IBIWON) is cleared
+ *  0b01..IBI: In-Band Interrupt
+ *  0b10..MR: Master Request
+ *  0b11..HJ: Hot-Join
+ */
+#define I3C_MSTATUS_IBITYPE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK)
+#define I3C_MSTATUS_SLVSTART_MASK                (0x100U)
+#define I3C_MSTATUS_SLVSTART_SHIFT               (8U)
+#define I3C_MSTATUS_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK)
+#define I3C_MSTATUS_MCTRLDONE_MASK               (0x200U)
+#define I3C_MSTATUS_MCTRLDONE_SHIFT              (9U)
+#define I3C_MSTATUS_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK)
+#define I3C_MSTATUS_COMPLETE_MASK                (0x400U)
+#define I3C_MSTATUS_COMPLETE_SHIFT               (10U)
+#define I3C_MSTATUS_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK)
+#define I3C_MSTATUS_RXPEND_MASK                  (0x800U)
+#define I3C_MSTATUS_RXPEND_SHIFT                 (11U)
+#define I3C_MSTATUS_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK)
+#define I3C_MSTATUS_TXNOTFULL_MASK               (0x1000U)
+#define I3C_MSTATUS_TXNOTFULL_SHIFT              (12U)
+#define I3C_MSTATUS_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK)
+#define I3C_MSTATUS_IBIWON_MASK                  (0x2000U)
+#define I3C_MSTATUS_IBIWON_SHIFT                 (13U)
+#define I3C_MSTATUS_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK)
+#define I3C_MSTATUS_ERRWARN_MASK                 (0x8000U)
+#define I3C_MSTATUS_ERRWARN_SHIFT                (15U)
+#define I3C_MSTATUS_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK)
+#define I3C_MSTATUS_NOWMASTER_MASK               (0x80000U)
+#define I3C_MSTATUS_NOWMASTER_SHIFT              (19U)
+#define I3C_MSTATUS_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK)
+#define I3C_MSTATUS_IBIADDR_MASK                 (0x7F000000U)
+#define I3C_MSTATUS_IBIADDR_SHIFT                (24U)
+#define I3C_MSTATUS_IBIADDR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK)
+
+/* MIBIRULES - Master In-band Interrupt Registry and Rules Register */
+#define I3C_MIBIRULES_ADDR0_MASK                 (0x3FU)
+#define I3C_MIBIRULES_ADDR0_SHIFT                (0U)
+#define I3C_MIBIRULES_ADDR0(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK)
+#define I3C_MIBIRULES_ADDR1_MASK                 (0xFC0U)
+#define I3C_MIBIRULES_ADDR1_SHIFT                (6U)
+#define I3C_MIBIRULES_ADDR1(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK)
+#define I3C_MIBIRULES_ADDR2_MASK                 (0x3F000U)
+#define I3C_MIBIRULES_ADDR2_SHIFT                (12U)
+#define I3C_MIBIRULES_ADDR2(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK)
+#define I3C_MIBIRULES_ADDR3_MASK                 (0xFC0000U)
+#define I3C_MIBIRULES_ADDR3_SHIFT                (18U)
+#define I3C_MIBIRULES_ADDR3(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK)
+#define I3C_MIBIRULES_ADDR4_MASK                 (0x3F000000U)
+#define I3C_MIBIRULES_ADDR4_SHIFT                (24U)
+#define I3C_MIBIRULES_ADDR4(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK)
+#define I3C_MIBIRULES_MSB0_MASK                  (0x40000000U)
+#define I3C_MIBIRULES_MSB0_SHIFT                 (30U)
+#define I3C_MIBIRULES_MSB0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK)
+#define I3C_MIBIRULES_NOBYTE_MASK                (0x80000000U)
+#define I3C_MIBIRULES_NOBYTE_SHIFT               (31U)
+#define I3C_MIBIRULES_NOBYTE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK)
+
+/* MINTSET - Master Interrupt Set Register */
+#define I3C_MINTSET_SLVSTART_MASK                (0x100U)
+#define I3C_MINTSET_SLVSTART_SHIFT               (8U)
+#define I3C_MINTSET_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK)
+#define I3C_MINTSET_MCTRLDONE_MASK               (0x200U)
+#define I3C_MINTSET_MCTRLDONE_SHIFT              (9U)
+#define I3C_MINTSET_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK)
+#define I3C_MINTSET_COMPLETE_MASK                (0x400U)
+#define I3C_MINTSET_COMPLETE_SHIFT               (10U)
+#define I3C_MINTSET_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK)
+#define I3C_MINTSET_RXPEND_MASK                  (0x800U)
+#define I3C_MINTSET_RXPEND_SHIFT                 (11U)
+#define I3C_MINTSET_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK)
+#define I3C_MINTSET_TXNOTFULL_MASK               (0x1000U)
+#define I3C_MINTSET_TXNOTFULL_SHIFT              (12U)
+#define I3C_MINTSET_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK)
+#define I3C_MINTSET_IBIWON_MASK                  (0x2000U)
+#define I3C_MINTSET_IBIWON_SHIFT                 (13U)
+#define I3C_MINTSET_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK)
+#define I3C_MINTSET_ERRWARN_MASK                 (0x8000U)
+#define I3C_MINTSET_ERRWARN_SHIFT                (15U)
+#define I3C_MINTSET_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK)
+#define I3C_MINTSET_NOWMASTER_MASK               (0x80000U)
+#define I3C_MINTSET_NOWMASTER_SHIFT              (19U)
+#define I3C_MINTSET_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK)
+
+/* MINTCLR - Master Interrupt Clear Register */
+#define I3C_MINTCLR_SLVSTART_MASK                (0x100U)
+#define I3C_MINTCLR_SLVSTART_SHIFT               (8U)
+#define I3C_MINTCLR_SLVSTART(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK)
+#define I3C_MINTCLR_MCTRLDONE_MASK               (0x200U)
+#define I3C_MINTCLR_MCTRLDONE_SHIFT              (9U)
+#define I3C_MINTCLR_MCTRLDONE(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK)
+#define I3C_MINTCLR_COMPLETE_MASK                (0x400U)
+#define I3C_MINTCLR_COMPLETE_SHIFT               (10U)
+#define I3C_MINTCLR_COMPLETE(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK)
+#define I3C_MINTCLR_RXPEND_MASK                  (0x800U)
+#define I3C_MINTCLR_RXPEND_SHIFT                 (11U)
+#define I3C_MINTCLR_RXPEND(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK)
+#define I3C_MINTCLR_TXNOTFULL_MASK               (0x1000U)
+#define I3C_MINTCLR_TXNOTFULL_SHIFT              (12U)
+#define I3C_MINTCLR_TXNOTFULL(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK)
+#define I3C_MINTCLR_IBIWON_MASK                  (0x2000U)
+#define I3C_MINTCLR_IBIWON_SHIFT                 (13U)
+#define I3C_MINTCLR_IBIWON(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK)
+#define I3C_MINTCLR_ERRWARN_MASK                 (0x8000U)
+#define I3C_MINTCLR_ERRWARN_SHIFT                (15U)
+#define I3C_MINTCLR_ERRWARN(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK)
+#define I3C_MINTCLR_NOWMASTER_MASK               (0x80000U)
+#define I3C_MINTCLR_NOWMASTER_SHIFT              (19U)
+#define I3C_MINTCLR_NOWMASTER(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK)
+
+/* MINTMASKED - Master Interrupt Mask Register */
+#define I3C_MINTMASKED_SLVSTART_MASK             (0x100U)
+#define I3C_MINTMASKED_SLVSTART_SHIFT            (8U)
+#define I3C_MINTMASKED_SLVSTART(x)               (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK)
+#define I3C_MINTMASKED_MCTRLDONE_MASK            (0x200U)
+#define I3C_MINTMASKED_MCTRLDONE_SHIFT           (9U)
+#define I3C_MINTMASKED_MCTRLDONE(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK)
+#define I3C_MINTMASKED_COMPLETE_MASK             (0x400U)
+#define I3C_MINTMASKED_COMPLETE_SHIFT            (10U)
+#define I3C_MINTMASKED_COMPLETE(x)               (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK)
+#define I3C_MINTMASKED_RXPEND_MASK               (0x800U)
+#define I3C_MINTMASKED_RXPEND_SHIFT              (11U)
+#define I3C_MINTMASKED_RXPEND(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK)
+#define I3C_MINTMASKED_TXNOTFULL_MASK            (0x1000U)
+#define I3C_MINTMASKED_TXNOTFULL_SHIFT           (12U)
+#define I3C_MINTMASKED_TXNOTFULL(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK)
+#define I3C_MINTMASKED_IBIWON_MASK               (0x2000U)
+#define I3C_MINTMASKED_IBIWON_SHIFT              (13U)
+#define I3C_MINTMASKED_IBIWON(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK)
+#define I3C_MINTMASKED_ERRWARN_MASK              (0x8000U)
+#define I3C_MINTMASKED_ERRWARN_SHIFT             (15U)
+#define I3C_MINTMASKED_ERRWARN(x)                (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK)
+#define I3C_MINTMASKED_NOWMASTER_MASK            (0x80000U)
+#define I3C_MINTMASKED_NOWMASTER_SHIFT           (19U)
+#define I3C_MINTMASKED_NOWMASTER(x)              (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK)
+
+/* MERRWARN - Master Errors and Warnings Register */
+#define I3C_MERRWARN_NACK_MASK                   (0x4U)
+#define I3C_MERRWARN_NACK_SHIFT                  (2U)
+#define I3C_MERRWARN_NACK(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK)
+#define I3C_MERRWARN_WRABT_MASK                  (0x8U)
+#define I3C_MERRWARN_WRABT_SHIFT                 (3U)
+#define I3C_MERRWARN_WRABT(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK)
+#define I3C_MERRWARN_TERM_MASK                   (0x10U)
+#define I3C_MERRWARN_TERM_SHIFT                  (4U)
+#define I3C_MERRWARN_TERM(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TERM_SHIFT)) & I3C_MERRWARN_TERM_MASK)
+#define I3C_MERRWARN_HPAR_MASK                   (0x200U)
+#define I3C_MERRWARN_HPAR_SHIFT                  (9U)
+#define I3C_MERRWARN_HPAR(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK)
+#define I3C_MERRWARN_HCRC_MASK                   (0x400U)
+#define I3C_MERRWARN_HCRC_SHIFT                  (10U)
+#define I3C_MERRWARN_HCRC(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK)
+#define I3C_MERRWARN_OREAD_MASK                  (0x10000U)
+#define I3C_MERRWARN_OREAD_SHIFT                 (16U)
+#define I3C_MERRWARN_OREAD(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK)
+#define I3C_MERRWARN_OWRITE_MASK                 (0x20000U)
+#define I3C_MERRWARN_OWRITE_SHIFT                (17U)
+#define I3C_MERRWARN_OWRITE(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK)
+#define I3C_MERRWARN_MSGERR_MASK                 (0x40000U)
+#define I3C_MERRWARN_MSGERR_SHIFT                (18U)
+#define I3C_MERRWARN_MSGERR(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK)
+#define I3C_MERRWARN_INVREQ_MASK                 (0x80000U)
+#define I3C_MERRWARN_INVREQ_SHIFT                (19U)
+#define I3C_MERRWARN_INVREQ(x)                   (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK)
+#define I3C_MERRWARN_TIMEOUT_MASK                (0x100000U)
+#define I3C_MERRWARN_TIMEOUT_SHIFT               (20U)
+#define I3C_MERRWARN_TIMEOUT(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK)
+
+/* MDMACTRL - Master DMA Control Register */
+#define I3C_MDMACTRL_DMAFB_MASK                  (0x3U)
+#define I3C_MDMACTRL_DMAFB_SHIFT                 (0U)
+/* DMAFB - DMA from bus
+ *  0b00..NOT_USED: DMA is not used
+ *  0b01..ENABLE_ONE_FRAME: DMA is enabled for 1 frame. DMAFB auto-clears on STOP or repeated START. See MCONFIG.MATCHSS.
+ *  0b10..ENABLE: DMA is enabled until the DMA is turned off.
+ */
+#define I3C_MDMACTRL_DMAFB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK)
+#define I3C_MDMACTRL_DMATB_MASK                  (0xCU)
+#define I3C_MDMACTRL_DMATB_SHIFT                 (2U)
+/* DMATB - DMA to bus
+ *  0b00..NOT_USED: DMA is not used
+ *  0b01..ENABLE_ONE_FRAME: DMA is enabled for 1 frame (ended by DMA or Terminated). DMATB auto-clears on STOP or START. See MCONFIG.MATCHSS.
+ *  0b10..ENABLE: DMA is enabled until DMA is turned off. Normally DMA ENABLE should only be used in Master Message mode.
+ */
+#define I3C_MDMACTRL_DMATB(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK)
+#define I3C_MDMACTRL_DMAWIDTH_MASK               (0x30U)
+#define I3C_MDMACTRL_DMAWIDTH_SHIFT              (4U)
+/* DMAWIDTH - DMA width
+ *  0b00..BYTE
+ *  0b01..BYTE_AGAIN
+ *  0b10..HALF_WORD: Half-word (16 bits). This will make sure that 2 bytes are free/available in FIFO.
+ *  0b11..RESERVED
+ */
+#define I3C_MDMACTRL_DMAWIDTH(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK)
+
+/* MDATACTRL - Master Data Control Register */
+#define I3C_MDATACTRL_FLUSHTB_MASK               (0x1U)
+#define I3C_MDATACTRL_FLUSHTB_SHIFT              (0U)
+#define I3C_MDATACTRL_FLUSHTB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK)
+#define I3C_MDATACTRL_FLUSHFB_MASK               (0x2U)
+#define I3C_MDATACTRL_FLUSHFB_SHIFT              (1U)
+#define I3C_MDATACTRL_FLUSHFB(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK)
+#define I3C_MDATACTRL_UNLOCK_MASK                (0x4U)
+#define I3C_MDATACTRL_UNLOCK_SHIFT               (2U)
+#define I3C_MDATACTRL_UNLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK)
+#define I3C_MDATACTRL_TXTRIG_MASK                (0x30U)
+#define I3C_MDATACTRL_TXTRIG_SHIFT               (4U)
+#define I3C_MDATACTRL_TXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK)
+#define I3C_MDATACTRL_RXTRIG_MASK                (0xC0U)
+#define I3C_MDATACTRL_RXTRIG_SHIFT               (6U)
+#define I3C_MDATACTRL_RXTRIG(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK)
+#define I3C_MDATACTRL_TXCOUNT_MASK               (0x1F0000U)
+#define I3C_MDATACTRL_TXCOUNT_SHIFT              (16U)
+#define I3C_MDATACTRL_TXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK)
+#define I3C_MDATACTRL_RXCOUNT_MASK               (0x1F000000U)
+#define I3C_MDATACTRL_RXCOUNT_SHIFT              (24U)
+#define I3C_MDATACTRL_RXCOUNT(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK)
+#define I3C_MDATACTRL_TXFULL_MASK                (0x40000000U)
+#define I3C_MDATACTRL_TXFULL_SHIFT               (30U)
+#define I3C_MDATACTRL_TXFULL(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK)
+#define I3C_MDATACTRL_RXEMPTY_MASK               (0x80000000U)
+#define I3C_MDATACTRL_RXEMPTY_SHIFT              (31U)
+#define I3C_MDATACTRL_RXEMPTY(x)                 (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK)
+
+/* MWDATAB - Master Write Data Byte Register */
+#define I3C_MWDATAB_VALUE_MASK                   (0xFFU)
+#define I3C_MWDATAB_VALUE_SHIFT                  (0U)
+#define I3C_MWDATAB_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK)
+#define I3C_MWDATAB_END_MASK                     (0x100U)
+#define I3C_MWDATAB_END_SHIFT                    (8U)
+#define I3C_MWDATAB_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK)
+#define I3C_MWDATAB_END_ALSO_MASK                (0x10000U)
+#define I3C_MWDATAB_END_ALSO_SHIFT               (16U)
+#define I3C_MWDATAB_END_ALSO(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK)
+
+/* MWDATABE - Master Write Data Byte End Register */
+#define I3C_MWDATABE_VALUE_MASK                  (0xFFU)
+#define I3C_MWDATABE_VALUE_SHIFT                 (0U)
+#define I3C_MWDATABE_VALUE(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK)
+
+/* MWDATAH - Master Write Data Half-word Register */
+#define I3C_MWDATAH_DATA0_MASK                   (0xFFU)
+#define I3C_MWDATAH_DATA0_SHIFT                  (0U)
+#define I3C_MWDATAH_DATA0(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK)
+#define I3C_MWDATAH_DATA1_MASK                   (0xFF00U)
+#define I3C_MWDATAH_DATA1_SHIFT                  (8U)
+#define I3C_MWDATAH_DATA1(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK)
+#define I3C_MWDATAH_END_MASK                     (0x10000U)
+#define I3C_MWDATAH_END_SHIFT                    (16U)
+#define I3C_MWDATAH_END(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK)
+
+/* MWDATAHE - Master Write Data Byte End Register */
+#define I3C_MWDATAHE_DATA0_MASK                  (0xFFU)
+#define I3C_MWDATAHE_DATA0_SHIFT                 (0U)
+#define I3C_MWDATAHE_DATA0(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK)
+#define I3C_MWDATAHE_DATA1_MASK                  (0xFF00U)
+#define I3C_MWDATAHE_DATA1_SHIFT                 (8U)
+#define I3C_MWDATAHE_DATA1(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK)
+
+/* MRDATAB - Master Read Data Byte Register */
+#define I3C_MRDATAB_VALUE_MASK                   (0xFFU)
+#define I3C_MRDATAB_VALUE_SHIFT                  (0U)
+#define I3C_MRDATAB_VALUE(x)                     (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK)
+
+/* MRDATAH - Master Read Data Half-word Register */
+#define I3C_MRDATAH_LSB_MASK                     (0xFFU)
+#define I3C_MRDATAH_LSB_SHIFT                    (0U)
+#define I3C_MRDATAH_LSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK)
+#define I3C_MRDATAH_MSB_MASK                     (0xFF00U)
+#define I3C_MRDATAH_MSB_SHIFT                    (8U)
+#define I3C_MRDATAH_MSB(x)                       (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK)
+
+/* MWMSG_SDR_CONTROL - Master Write Message in SDR mode */
+#define I3C_MWMSG_SDR_CONTROL_DIR_MASK           (0x1U)
+#define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT          (0U)
+/* DIR - Direction
+ *  0b0..Write
+ *  0b1..Read
+ */
+#define I3C_MWMSG_SDR_CONTROL_DIR(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK)
+#define I3C_MWMSG_SDR_CONTROL_ADDR_MASK          (0xFEU)
+#define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT         (1U)
+#define I3C_MWMSG_SDR_CONTROL_ADDR(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK)
+#define I3C_MWMSG_SDR_CONTROL_END_MASK           (0x100U)
+#define I3C_MWMSG_SDR_CONTROL_END_SHIFT          (8U)
+#define I3C_MWMSG_SDR_CONTROL_END(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK)
+#define I3C_MWMSG_SDR_CONTROL_I2C_MASK           (0x400U)
+#define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT          (10U)
+/* I2C - I2C
+ *  0b0..I3C message
+ *  0b1..I2C message
+ */
+#define I3C_MWMSG_SDR_CONTROL_I2C(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK)
+#define I3C_MWMSG_SDR_CONTROL_LEN_MASK           (0xF800U)
+#define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT          (11U)
+#define I3C_MWMSG_SDR_CONTROL_LEN(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK)
+
+/* MWMSG_SDR_DATA - Master Write Message Data in SDR mode */
+#define I3C_MWMSG_SDR_DATA_DATA16B_MASK          (0xFFFFU)
+#define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT         (0U)
+#define I3C_MWMSG_SDR_DATA_DATA16B(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK)
+#define I3C_MWMSG_SDR_DATA_END_MASK              (0x10000U)
+#define I3C_MWMSG_SDR_DATA_END_SHIFT             (16U)
+#define I3C_MWMSG_SDR_DATA_END(x)                (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_END_SHIFT)) & I3C_MWMSG_SDR_DATA_END_MASK)
+
+/* MRMSG_SDR - Master Read Message in SDR mode */
+#define I3C_MRMSG_SDR_DATA_MASK                  (0xFFFFU)
+#define I3C_MRMSG_SDR_DATA_SHIFT                 (0U)
+#define I3C_MRMSG_SDR_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK)
+
+/* MWMSG_DDR_CONTROL - Master Write Message in DDR mode */
+#define I3C_MWMSG_DDR_CONTROL_LEN_MASK           (0x3FFU)
+#define I3C_MWMSG_DDR_CONTROL_LEN_SHIFT          (0U)
+#define I3C_MWMSG_DDR_CONTROL_LEN(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL_LEN_MASK)
+#define I3C_MWMSG_DDR_CONTROL_END_MASK           (0x4000U)
+#define I3C_MWMSG_DDR_CONTROL_END_SHIFT          (14U)
+#define I3C_MWMSG_DDR_CONTROL_END(x)             (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL_END_MASK)
+
+/* MWMSG_DDR_DATA - Master Write Message Data in DDR mode */
+#define I3C_MWMSG_DDR_DATA_DATA16B_MASK          (0xFFFFU)
+#define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT         (0U)
+#define I3C_MWMSG_DDR_DATA_DATA16B(x)            (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK)
+#define I3C_MWMSG_DDR_DATA_END_MASK              (0x10000U)
+#define I3C_MWMSG_DDR_DATA_END_SHIFT             (16U)
+#define I3C_MWMSG_DDR_DATA_END(x)                (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_END_SHIFT)) & I3C_MWMSG_DDR_DATA_END_MASK)
+
+/* MRMSG_DDR - Master Read Message in DDR mode */
+#define I3C_MRMSG_DDR_DATA_MASK                  (0xFFFFU)
+#define I3C_MRMSG_DDR_DATA_SHIFT                 (0U)
+#define I3C_MRMSG_DDR_DATA(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK)
+#define I3C_MRMSG_DDR_CLEN_MASK                  (0x3FF0000U)
+#define I3C_MRMSG_DDR_CLEN_SHIFT                 (16U)
+#define I3C_MRMSG_DDR_CLEN(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_CLEN_SHIFT)) & I3C_MRMSG_DDR_CLEN_MASK)
+
+/* MDYNADDR - Master Dynamic Address Register */
+#define I3C_MDYNADDR_DAVALID_MASK                (0x1U)
+#define I3C_MDYNADDR_DAVALID_SHIFT               (0U)
+#define I3C_MDYNADDR_DAVALID(x)                  (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK)
+#define I3C_MDYNADDR_DADDR_MASK                  (0xFEU)
+#define I3C_MDYNADDR_DADDR_SHIFT                 (1U)
+#define I3C_MDYNADDR_DADDR(x)                    (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK)
+
+/* SID - Slave Module ID Register */
+#define I3C_SID_ID_MASK                          (0xFFFFFFFFU)
+#define I3C_SID_ID_SHIFT                         (0U)
+#define I3C_SID_ID(x)                            (((uint32_t)(((uint32_t)(x)) << I3C_SID_ID_SHIFT)) & I3C_SID_ID_MASK)
+
+/* end of group I3C_Register_Masks */
+
+#endif /* __IMX_I3C_H__ */
diff --git a/include/imx_m4_mu.h b/include/imx_m4_mu.h
new file mode 100644
index 00000000000..b53e9e8b231
--- /dev/null
+++ b/include/imx_m4_mu.h
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ *
+ */
+
+#ifndef __IMX_M4_MU_H__
+#define __IMX_M4_MU_H__
+
+enum imx_m4_msg_type {
+	MU_MSG_REQ		= 0x1, /* request message sent from A side */
+	MU_MSG_RESP		= 0x2, /* response message from B side for request */
+	MU_MSG_READY_A	= 0x3, /* A side notifies ready */
+	MU_MSG_READY_B	= 0x4, /* B side notifies ready */
+};
+
+union imx_m4_msg {
+	struct {
+		u32 seq;
+		u32 type;
+		u32 buffer;
+		u32 size;
+	} format;
+	u32 data[4];
+};
+#endif
diff --git a/include/imx_sip.h b/include/imx_sip.h
index 26dbe0421a0..da844fe6bef 100644
--- a/include/imx_sip.h
+++ b/include/imx_sip.h
@@ -13,7 +13,11 @@
 #define IMX_SIP_BUILDINFO_GET_COMMITHASH	0x00
 
 #define IMX_SIP_SRC		0xC2000005
-#define IMX_SIP_SRC_M4_START	0x00
-#define IMX_SIP_SRC_M4_STARTED	0x01
+#define IMX_SIP_SRC_MCU_START	0x00
+#define IMX_SIP_SRC_MCU_STARTED	0x01
+#define	IMX_SIP_SRC_MCU_STOP	0x02
+
+#define IMX_SIP_FIPS_CONFIG		0xC200000D
+#define IMX_SIP_FIPS_CONFIG_SET		0x1
 
 #endif
diff --git a/include/imxdpuv1.h b/include/imxdpuv1.h
new file mode 100644
index 00000000000..cb12bb8c0f1
--- /dev/null
+++ b/include/imxdpuv1.h
@@ -0,0 +1,998 @@
+/*
+ * Copyright (c) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef IMXDPUV1_H
+#define IMXDPUV1_H
+
+#include <linux/types.h>
+#include <errno.h>
+
+/* these will be removed */
+#undef IMXDPUV1_VERSION_0
+#define IMXDPUV1_VERSION_1
+
+/* #define DEBUG */
+/* #define ENABLE_IMXDPUV1_TRACE */
+/* #define ENABLE_IMXDPUV1_TRACE_REG */
+/* #define ENABLE_IMXDPUV1_TRACE_IRQ */
+/* #define ENABLE_IMXDPUV1_TRACE_IRQ_READ */
+/* #define ENABLE_IMXDPUV1_TRACE_IRQ_WRITE */
+
+#ifdef ENABLE_IMXDPUV1_TRACE
+#define IMXDPUV1_TRACE(fmt, ...) \
+printf((fmt), ##__VA_ARGS__)
+#else
+#define IMXDPUV1_TRACE(fmt, ...) do {} while (0)
+#endif
+
+#ifdef ENABLE_IMXDPUV1_TRACE_IRQ
+#define IMXDPUV1_TRACE_IRQ(fmt, ...) \
+printf((fmt), ##__VA_ARGS__)
+#else
+#define IMXDPUV1_TRACE_IRQ(fmt, ...) do {} while (0)
+#endif
+
+#ifdef ENABLE_IMXDPUV1_TRACE_REG
+#define IMXDPUV1_TRACE_REG(fmt, ...) \
+printf((fmt), ##__VA_ARGS__)
+#else
+#define IMXDPUV1_TRACE_REG(fmt, ...) do {} while (0)
+#endif
+
+#define IMXDPUV1_PRINT(fmt, ...) \
+printf((fmt), ##__VA_ARGS__)
+
+/* #define IMXDPUV1_TCON0_MAP_24BIT_0_23 */
+/* #define IMXDPUV1_TCON1_MAP_24BIT_0_23 */
+
+/* todo: this need to come from device tree */
+#define IMXDPUV1_NUM_DI_MAX 2
+#define IMXDPUV1_MAX_NUM		2
+#define IMXDPUV1_NUM_DI           2
+#define IMXDPUV1_NUM_CI           2
+#define IMXDPUV1_REGS_BASE_PHY0	0x56180000
+#define IMXDPUV1_REGS_BASE_PHY1	0x57180000
+#define IMXDPUV1_REGS_BASE_SIZE	0x14000
+
+#ifdef IMXDPUV1_VERSION_0
+#define IMXDPUV1_ENABLE_INTSTAT2
+#endif
+#define IMXDPUV1_SET_FIELD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
+#define IMXDPUV1_GET_FIELD(field, reg) (((reg)&(field ## _MASK)) >> (field  ## _SHIFT))
+
+/*
+	IMXDPU windows, planes, layers, streams
+
+	IMXDPU hardware documentation confuses the meaning of layers and
+		planes. These are software usages of these terms.
+
+	window - a logical buffer of pixels in a rectangular arrangment.
+		Image, Integral and video planes suport one window.
+		Fractional and warp plane support 8 windows. Blending is not
+		supported between the sub-windows of a fractional or warp plane.
+
+	sub-window - one of the eight logical windows of a fractional or warp
+		plane.
+
+	channel - the logical DMA configuration for etiher a fetch or store unit
+
+	plane - a plane is a hardware supported feature. There are four types
+		of display planes:
+
+		video x2
+		fractional x2
+		intergral x2
+		warp
+
+	layer - each of the 7 planes is fed to a layer blender. Full Alpha
+		blending is supported for all of the planes fed to the layer
+		blender.
+
+	streams - the layer bleder produces four streams: two normal streams
+		(0 and 1) and two panic streams (4 and 5).
+
+		In normal mode, streams 0 and 1 are fed to the displays.
+		In panic mode, streams 4 and 5 are fed to the displays.
+*/
+
+
+/*!
+ * Enumeration of IMXDPU blend mode flags
+ */
+typedef enum {
+	IMXDPUV1_PLANE_CLUT               = 1 << 0,	/* Color lookup */
+	IMXDPUV1_PLANE_DECODE             = 1 << 1,	/* Decode compressed bufers */
+	IMXDPUV1_PLANE_ETERNAL_ALPHA      = 1 << 2,	/* supports external alpha buffer  */
+	IMXDPUV1_PLANE_VIDEO_PROC         = 1 << 2,	/* Gamma, Matrix, Scaler, histogram  */
+	IMXDPUV1_PLANE_PLANAR             = 1 << 3,	/* Support Planar pixel buffers*/
+	IMXDPUV1_PLANE_WARP               = 1 << 4,	/* Warping */
+	IMXDPUV1_PLANE_MULTIWINDOW        = 1 << 5,	/* Support multiple buffers per plane */
+	IMXDPUV1_PLANE_CAPTURE            = 1 << 6,	/* Video capture */
+} imxdpuv1_plane_features_t;
+
+/*!
+ * Enumeration of IMXDPU layer blend mode flags
+ */
+typedef enum {
+	IMXDPUV1_LAYER_NONE               = 1 << 0,	/* Disable blending */
+	IMXDPUV1_LAYER_TRANSPARENCY       = 1 << 1,	/* Transparency */
+	IMXDPUV1_LAYER_GLOBAL_ALPHA       = 1 << 2,	/* Global alpha mode */
+	IMXDPUV1_LAYER_LOCAL_ALPHA        = 1 << 3,	/* Alpha contained in source buffer */
+	IMXDPUV1_LAYER_EXTERN_ALPHA       = 1 << 4,	/* Alpha is contained in a separate plane */
+	IMXDPUV1_LAYER_PRE_MULITPLY       = 1 << 5,	/* Pre-multiply alpha mode */
+} imxdpuv1_layer_blend_modes_t;
+
+/*!
+ * Enumeration of IMXDPU layers
+ */
+typedef enum {
+	IMXDPUV1_LAYER_0 = 0,
+	IMXDPUV1_LAYER_1,
+	IMXDPUV1_LAYER_2,
+	IMXDPUV1_LAYER_3,
+	IMXDPUV1_LAYER_4,
+#ifdef IMXDPUV1_VERSION_0
+	IMXDPUV1_LAYER_5,
+	IMXDPUV1_LAYER_6,
+#endif
+	IMXDPUV1_LAYER_MAX,
+} imxdpuv1_layer_idx_t;
+
+/*!
+ * Enumeration of IMXDPU sub-windows
+ */
+typedef enum {
+	IMXDPUV1_SUBWINDOW_NONE = 0,
+	IMXDPUV1_SUBWINDOW_1,
+	IMXDPUV1_SUBWINDOW_2,
+	IMXDPUV1_SUBWINDOW_3,
+	IMXDPUV1_SUBWINDOW_4,
+	IMXDPUV1_SUBWINDOW_5,
+	IMXDPUV1_SUBWINDOW_6,
+	IMXDPUV1_SUBWINDOW_7,
+	IMXDPUV1_SUBWINDOW_8,
+} imxdpuv1_subwindow_id_t;
+
+/*!
+ * Enumeration of IMXDPU display streams
+ */
+typedef enum {
+	IMXDPUV1_DISPLAY_STREAM_NONE = (0),
+	IMXDPUV1_DISPLAY_STREAM_0 = (1U<<0),
+	IMXDPUV1_DISPLAY_STREAM_1 = (1U<<1),
+	IMXDPUV1_DISPLAY_STREAM_4 = (1U<<4),
+	IMXDPUV1_DISPLAY_STREAM_5 = (1U<<5),
+} imxdpuv1_display_stream_t;
+
+/*!
+ * Enumeration of IMXDPU rotation modes
+ */
+typedef enum {
+	/* todo: these need to aligh to imxdpu scan direction */
+	IMXDPUV1_ROTATE_NONE = 0,
+	IMXDPUV1_ROTATE_VERT_FLIP = 1,
+	IMXDPUV1_ROTATE_HORIZ_FLIP = 2,
+	IMXDPUV1_ROTATE_180 = 3,
+	IMXDPUV1_ROTATE_90_RIGHT = 4,
+	IMXDPUV1_ROTATE_90_RIGHT_VFLIP = 5,
+	IMXDPUV1_ROTATE_90_RIGHT_HFLIP = 6,
+	IMXDPUV1_ROTATE_90_LEFT = 7,
+} imxdpuv1_rotate_mode_t;
+
+
+/*!
+ * Enumeration of types of buffers for a logical channel.
+ */
+typedef enum {
+	IMXDPUV1_OUTPUT_BUFFER = 0,	/*!< Buffer for output from IMXDPU BLIT or capture */
+	IMXDPUV1_ALPHA_IN_BUFFER = 1,	/*!< Buffer for alpha input to IMXDPU */
+	IMXDPUV1_GRAPH_IN_BUFFER = 2,	/*!< Buffer for graphics input to IMXDPU */
+	IMXDPUV1_VIDEO_IN_BUFFER = 3,	/*!< Buffer for video input to IMXDPU */
+} imxdpuv1_buffer_t;
+
+#ifdef IMXDPUV1_VERSION_0
+/*!
+ * Enumeration of IMXDPU logical block ids
+ * NOTE: these match the hardware layout and are not arbitrary
+ */
+typedef enum {
+	IMXDPUV1_ID_NONE = 0,
+	IMXDPUV1_ID_FETCHDECODE9,
+	IMXDPUV1_ID_FETCHPERSP9,
+	IMXDPUV1_ID_FETCHECO9,
+	IMXDPUV1_ID_ROP9,
+	IMXDPUV1_ID_CLUT9,
+	IMXDPUV1_ID_MATRIX9,
+	IMXDPUV1_ID_HSCALER9,
+	IMXDPUV1_ID_VSCALER9,
+	IMXDPUV1_ID_FILTER9,
+	IMXDPUV1_ID_BLITBLEND9,
+	IMXDPUV1_ID_STORE9,
+	IMXDPUV1_ID_CONSTFRAME0,
+	IMXDPUV1_ID_EXTDST0,
+	IMXDPUV1_ID_CONSTFRAME4,
+	IMXDPUV1_ID_EXTDST4,
+	IMXDPUV1_ID_CONSTFRAME1,
+	IMXDPUV1_ID_EXTDST1,
+	IMXDPUV1_ID_CONSTFRAME5,
+	IMXDPUV1_ID_EXTDST5,
+	IMXDPUV1_ID_EXTSRC4,
+	IMXDPUV1_ID_STORE4,
+	IMXDPUV1_ID_EXTSRC5,
+	IMXDPUV1_ID_STORE5,
+	IMXDPUV1_ID_FETCHDECODE2,
+	IMXDPUV1_ID_FETCHDECODE3,
+	IMXDPUV1_ID_FETCHWARP2,
+	IMXDPUV1_ID_FETCHECO2,
+	IMXDPUV1_ID_FETCHDECODE0,
+	IMXDPUV1_ID_FETCHECO0,
+	IMXDPUV1_ID_FETCHDECODE1,
+	IMXDPUV1_ID_FETCHECO1,
+	IMXDPUV1_ID_FETCHLAYER0,
+	IMXDPUV1_ID_FETCHLAYER1,
+	IMXDPUV1_ID_GAMMACOR4,
+	IMXDPUV1_ID_MATRIX4,
+	IMXDPUV1_ID_HSCALER4,
+	IMXDPUV1_ID_VSCALER4,
+	IMXDPUV1_ID_HISTOGRAM4,
+	IMXDPUV1_ID_GAMMACOR5,
+	IMXDPUV1_ID_MATRIX5,
+	IMXDPUV1_ID_HSCALER5,
+	IMXDPUV1_ID_VSCALER5,
+	IMXDPUV1_ID_HISTOGRAM5,
+	IMXDPUV1_ID_LAYERBLEND0,
+	IMXDPUV1_ID_LAYERBLEND1,
+	IMXDPUV1_ID_LAYERBLEND2,
+	IMXDPUV1_ID_LAYERBLEND3,
+	IMXDPUV1_ID_LAYERBLEND4,
+	IMXDPUV1_ID_LAYERBLEND5,
+	IMXDPUV1_ID_LAYERBLEND6,
+	IMXDPUV1_ID_EXTSRC0,
+	IMXDPUV1_ID_EXTSRC1,
+	IMXDPUV1_ID_DISENGCFG,
+	IMXDPUV1_ID_FRAMEDUMP0,
+	IMXDPUV1_ID_FRAMEDUMP1,
+	IMXDPUV1_ID_FRAMEGEN0,
+	IMXDPUV1_ID_MATRIX0,
+	IMXDPUV1_ID_GAMMACOR0,
+	IMXDPUV1_ID_DITHER0,
+	IMXDPUV1_ID_TCON0,
+	IMXDPUV1_ID_SIG0,
+	IMXDPUV1_ID_FRAMEGEN1,
+	IMXDPUV1_ID_MATRIX1,
+	IMXDPUV1_ID_GAMMACOR1,
+	IMXDPUV1_ID_DITHER1,
+	IMXDPUV1_ID_TCON1,
+	IMXDPUV1_ID_SIG1,
+	IMXDPUV1_ID_CAPENGCFG,
+	IMXDPUV1_ID_FRAMECAP4,
+	IMXDPUV1_ID_FRAMECAP5,
+	IMXDPUV1_ID_ANALYSER4,
+	IMXDPUV1_ID_ANALYSER5,
+	/* the following are added arbitrarily */
+	IMXDPUV1_ID_DPUXPC,
+
+} imxdpuv1_id_t;
+#else
+/*!
+ * Enumeration of IMXDPU logical block ids
+ * NOTE: these match the hardware layout and are not arbitrary
+ */
+typedef enum {
+	IMXDPUV1_ID_NONE = 0,
+	IMXDPUV1_ID_FETCHDECODE9,
+	IMXDPUV1_ID_FETCHWARP9,
+	IMXDPUV1_ID_FETCHECO9,
+	IMXDPUV1_ID_ROP9,
+	IMXDPUV1_ID_CLUT9,
+	IMXDPUV1_ID_MATRIX9,
+	IMXDPUV1_ID_HSCALER9,
+	IMXDPUV1_ID_VSCALER9,
+	IMXDPUV1_ID_FILTER9,
+	IMXDPUV1_ID_BLITBLEND9,
+	IMXDPUV1_ID_STORE9,
+	IMXDPUV1_ID_CONSTFRAME0,
+	IMXDPUV1_ID_EXTDST0,
+	IMXDPUV1_ID_CONSTFRAME4,
+	IMXDPUV1_ID_EXTDST4,
+	IMXDPUV1_ID_CONSTFRAME1,
+	IMXDPUV1_ID_EXTDST1,
+	IMXDPUV1_ID_CONSTFRAME5,
+	IMXDPUV1_ID_EXTDST5,
+	IMXDPUV1_ID_FETCHWARP2,
+	IMXDPUV1_ID_FETCHECO2,
+	IMXDPUV1_ID_FETCHDECODE0,
+	IMXDPUV1_ID_FETCHECO0,
+	IMXDPUV1_ID_FETCHDECODE1,
+	IMXDPUV1_ID_FETCHECO1,
+	IMXDPUV1_ID_FETCHLAYER0,
+	IMXDPUV1_ID_MATRIX4,
+	IMXDPUV1_ID_HSCALER4,
+	IMXDPUV1_ID_VSCALER4,
+	IMXDPUV1_ID_MATRIX5,
+	IMXDPUV1_ID_HSCALER5,
+	IMXDPUV1_ID_VSCALER5,
+	IMXDPUV1_ID_LAYERBLEND0,
+	IMXDPUV1_ID_LAYERBLEND1,
+	IMXDPUV1_ID_LAYERBLEND2,
+	IMXDPUV1_ID_LAYERBLEND3,
+	IMXDPUV1_ID_DISENGCFG,
+	IMXDPUV1_ID_FRAMEGEN0,
+	IMXDPUV1_ID_MATRIX0,
+	IMXDPUV1_ID_GAMMACOR0,
+	IMXDPUV1_ID_DITHER0,
+	IMXDPUV1_ID_TCON0,
+	IMXDPUV1_ID_SIG0,
+	IMXDPUV1_ID_FRAMEGEN1,
+	IMXDPUV1_ID_MATRIX1,
+	IMXDPUV1_ID_GAMMACOR1,
+	IMXDPUV1_ID_DITHER1,
+	IMXDPUV1_ID_TCON1,
+	IMXDPUV1_ID_SIG1,
+	IMXDPUV1_ID_DPUXPC,
+} imxdpuv1_id_t;
+#endif
+
+#ifdef IMXDPUV1_VERSION_0
+typedef enum {
+	IMXDPUV1_SHDLD_CONSTFRAME0  =  1U << 4,
+	IMXDPUV1_SHDLD_CONSTFRAME4  =  1U << 5,
+	IMXDPUV1_SHDLD_CONSTFRAME1  =  1U << 6,
+	IMXDPUV1_SHDLD_CONSTFRAME5  =  1U << 7,
+	IMXDPUV1_SHDLD_EXTSRC4      =  1U << 8,
+	IMXDPUV1_SHDLD_EXTSRC5      =  1U << 9,
+	IMXDPUV1_SHDLD_FETCHDECODE2 =  1U << 10,
+	IMXDPUV1_SHDLD_FETCHDECODE3 =  1U << 11,
+	IMXDPUV1_SHDLD_FETCHWARP2   =  1U << 12,
+	IMXDPUV1_SHDLD_FETCHECO2    =  1U << 13,
+	IMXDPUV1_SHDLD_FETCHDECODE0 =  1U << 14,
+	IMXDPUV1_SHDLD_FETCHECO0    =  1U << 15,
+	IMXDPUV1_SHDLD_FETCHDECODE1 =  1U << 16,
+	IMXDPUV1_SHDLD_FETCHECO1    =  1U << 17,
+	IMXDPUV1_SHDLD_FETCHLAYER0  =  1U << 18,
+	IMXDPUV1_SHDLD_FETCHLAYER1  =  1U << 19,
+	IMXDPUV1_SHDLD_EXTSRC0      =  1U << 20,
+	IMXDPUV1_SHDLD_EXTSRC1      =  1U << 21,
+} imxdpuv1_shadow_load_req_id_t;
+#else
+typedef enum {
+	IMXDPUV1_SHDLD_CONSTFRAME0  =  1U << 4,
+	IMXDPUV1_SHDLD_CONSTFRAME4  =  1U << 5,
+	IMXDPUV1_SHDLD_CONSTFRAME1  =  1U << 6,
+	IMXDPUV1_SHDLD_CONSTFRAME5  =  1U << 7,
+	IMXDPUV1_SHDLD_FETCHWARP2   =  1U << 8,
+	IMXDPUV1_SHDLD_FETCHECO2    =  1U << 9,
+	IMXDPUV1_SHDLD_FETCHDECODE0 =  1U << 10,
+	IMXDPUV1_SHDLD_FETCHECO0    =  1U << 11,
+	IMXDPUV1_SHDLD_FETCHDECODE1 =  1U << 12,
+	IMXDPUV1_SHDLD_FETCHECO1    =  1U << 13,
+	IMXDPUV1_SHDLD_FETCHLAYER0  =  1U << 14,
+
+	IMXDPUV1_SHDLD_EXTSRC4      =  0,
+	IMXDPUV1_SHDLD_EXTSRC5      =  0,
+	IMXDPUV1_SHDLD_FETCHDECODE2 =  0,
+	IMXDPUV1_SHDLD_FETCHDECODE3 =  0,
+	IMXDPUV1_SHDLD_FETCHLAYER1  =  0,
+	IMXDPUV1_SHDLD_EXTSRC0      =  0,
+	IMXDPUV1_SHDLD_EXTSRC1      =  0,
+
+} imxdpuv1_shadow_load_req_id_t;
+
+
+#endif
+typedef struct {
+	imxdpuv1_id_t primary;
+	imxdpuv1_id_t secondary;
+	imxdpuv1_display_stream_t stream;
+	bool enable;
+} imxdpuv1_layer_t;
+
+typedef enum {
+	/* Fetch Channels */
+	IMXDPUV1_CHAN_IDX_IN_FIRST = 0,
+	IMXDPUV1_CHAN_IDX_00 = 0,	/* IMXDPUV1_ID_SRC_FETCHDECODE2 */
+	IMXDPUV1_CHAN_IDX_01,	/* IMXDPUV1_ID_SRC_FETCHDECODE0 */
+	IMXDPUV1_CHAN_IDX_02,	/* IMXDPUV1_ID_SRC_FETCHLAYER0 */
+	IMXDPUV1_CHAN_IDX_03,	/* IMXDPUV1_ID_SRC_FETCHLAYER0 */
+	IMXDPUV1_CHAN_IDX_04,	/* IMXDPUV1_ID_SRC_FETCHLAYER0 */
+	IMXDPUV1_CHAN_IDX_05,	/* IMXDPUV1_ID_SRC_FETCHLAYER0 */
+	IMXDPUV1_CHAN_IDX_06,	/* IMXDPUV1_ID_SRC_FETCHLAYER0 */
+	IMXDPUV1_CHAN_IDX_07,	/* IMXDPUV1_ID_SRC_FETCHLAYER0 */
+	IMXDPUV1_CHAN_IDX_08,	/* IMXDPUV1_ID_SRC_FETCHLAYER0 */
+	IMXDPUV1_CHAN_IDX_09,	/* IMXDPUV1_ID_SRC_FETCHLAYER0 */
+	IMXDPUV1_CHAN_IDX_10,	/* IMXDPUV1_ID_SRC_FETCHWARP2 */
+	IMXDPUV1_CHAN_IDX_11,	/* IMXDPUV1_ID_SRC_FETCHWARP2 */
+	IMXDPUV1_CHAN_IDX_12,	/* IMXDPUV1_ID_SRC_FETCHWARP2 */
+	IMXDPUV1_CHAN_IDX_13,	/* IMXDPUV1_ID_SRC_FETCHWARP2 */
+	IMXDPUV1_CHAN_IDX_14,	/* IMXDPUV1_ID_SRC_FETCHWARP2 */
+	IMXDPUV1_CHAN_IDX_15,	/* IMXDPUV1_ID_SRC_FETCHWARP2 */
+	IMXDPUV1_CHAN_IDX_16,	/* IMXDPUV1_ID_SRC_FETCHWARP2 */
+	IMXDPUV1_CHAN_IDX_17,	/* IMXDPUV1_ID_SRC_FETCHWARP2 */
+	IMXDPUV1_CHAN_IDX_18,	/* IMXDPUV1_ID_SRC_FETCHDECODE3 */
+	IMXDPUV1_CHAN_IDX_19,	/* IMXDPUV1_ID_SRC_FETCHDECODE1 */
+	IMXDPUV1_CHAN_IDX_20,	/* IMXDPUV1_ID_SRC_FETCHLAYER1 */
+	IMXDPUV1_CHAN_IDX_21,	/* IMXDPUV1_ID_SRC_FETCHLAYER1 */
+	IMXDPUV1_CHAN_IDX_22,	/* IMXDPUV1_ID_SRC_FETCHLAYER1 */
+	IMXDPUV1_CHAN_IDX_23,	/* IMXDPUV1_ID_SRC_FETCHLAYER1 */
+	IMXDPUV1_CHAN_IDX_24,	/* IMXDPUV1_ID_SRC_FETCHLAYER1 */
+	IMXDPUV1_CHAN_IDX_25,	/* IMXDPUV1_ID_SRC_FETCHLAYER1 */
+	IMXDPUV1_CHAN_IDX_26,	/* IMXDPUV1_ID_SRC_FETCHLAYER1 */
+	IMXDPUV1_CHAN_IDX_27,	/* IMXDPUV1_ID_SRC_FETCHLAYER1 */
+	IMXDPUV1_CHAN_IDX_28,	/* IMXDPUV1_ID_SRC_ECO0 */
+	IMXDPUV1_CHAN_IDX_29,	/* IMXDPUV1_ID_SRC_ECO1 */
+	IMXDPUV1_CHAN_IDX_30,	/* IMXDPUV1_ID_SRC_ECO2 */
+	IMXDPUV1_CHAN_IDX_IN_MAX,	/* Last fetch channel + 1 */
+
+	/* Store Channels */
+	IMXDPUV1_CHAN_IDX_OUT_FIRST = 32,
+	IMXDPUV1_CHAN_IDX_32 = 32,/* IMXDPUV1_ID_DST_STORE4 */
+	IMXDPUV1_CHAN_IDX_33,	/* IMXDPUV1_ID_DST_STORE5 */
+	IMXDPUV1_CHAN_IDX_OUT_MAX,/* Last fetch channel + 1 */
+	IMXDPUV1_CHAN_IDX_MAX = IMXDPUV1_CHAN_IDX_OUT_MAX,
+} imxdpuv1_chan_idx_t;
+
+typedef enum {
+	IMXDPUV1_SUB_NONE = 0,
+	IMXDPUV1_SUB_1 = 1U << 0,	/* IMXDPUV1_ID_FETCHLAYER0, layer 1 */
+	IMXDPUV1_SUB_2 = 1U << 1,	/* IMXDPUV1_ID_FETCHLAYER0, layer 2 */
+	IMXDPUV1_SUB_3 = 1U << 2,	/* IMXDPUV1_ID_FETCHLAYER0, layer 3 */
+	IMXDPUV1_SUB_4 = 1U << 3,	/* IMXDPUV1_ID_FETCHLAYER0, layer 4 */
+	IMXDPUV1_SUB_5 = 1U << 4,	/* IMXDPUV1_ID_FETCHLAYER0, layer 5 */
+	IMXDPUV1_SUB_6 = 1U << 5,	/* IMXDPUV1_ID_FETCHLAYER0, layer 6 */
+	IMXDPUV1_SUB_7 = 1U << 6,	/* IMXDPUV1_ID_FETCHLAYER0, layer 7 */
+	IMXDPUV1_SUB_8 = 1U << 7,	/* IMXDPUV1_ID_FETCHLAYER0, layer 8 */
+} imxdpuv1_chan_sub_idx_t;
+
+/*  IMXDPU Channel
+ *	Consistist of four fields
+ *	src - block id of source or destination
+ *	sec - block id of secondary source for fetcheco
+ *	sub - sub index of block for fetchlayer or fetchwarp
+ *	idx - logical channel index
+ *
+ */
+#define make_channel(__blk_id, __eco_id, __sub, __idx) \
+(((__u32)(__idx)<<0)|((__u32)(__eco_id)<<8)|((__u32)(__sub)<<16)|((__u32)(__blk_id)<<24))
+
+#define get_channel_blk(chan) (((__u32)(chan) >> 24) & 0xff)
+#define get_channel_sub(chan) (((__u32)(chan) >> 16) & 0xff)
+#define get_eco_idx(chan)     (((__u32)(chan) >> 8) & 0xff)
+#define get_channel_idx(chan) (((__u32)(chan) >> 0) & 0xff)
+#define IMXDPUV1_SUBCHAN_LAYER_OFFSET 0x28
+
+typedef enum {
+#ifdef IMXDPUV1_VERSION_0
+	/* Fetch Channels */
+	IMXDPUV1_CHAN_00 = make_channel(IMXDPUV1_ID_FETCHDECODE2, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 0),
+	IMXDPUV1_CHAN_01 = make_channel(IMXDPUV1_ID_FETCHDECODE0,             28, IMXDPUV1_SUB_NONE, 1),
+	IMXDPUV1_CHAN_02 = make_channel(IMXDPUV1_ID_FETCHLAYER0,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_1, 2),
+	IMXDPUV1_CHAN_03 = make_channel(IMXDPUV1_ID_FETCHLAYER0,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_2, 3),
+	IMXDPUV1_CHAN_04 = make_channel(IMXDPUV1_ID_FETCHLAYER0,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_3, 4),
+	IMXDPUV1_CHAN_05 = make_channel(IMXDPUV1_ID_FETCHLAYER0,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_4, 5),
+	IMXDPUV1_CHAN_06 = make_channel(IMXDPUV1_ID_FETCHLAYER0,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_5, 6),
+	IMXDPUV1_CHAN_07 = make_channel(IMXDPUV1_ID_FETCHLAYER0,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_6, 7),
+	IMXDPUV1_CHAN_08 = make_channel(IMXDPUV1_ID_FETCHLAYER0,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_7, 8),
+	IMXDPUV1_CHAN_09 = make_channel(IMXDPUV1_ID_FETCHLAYER0,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_8, 9),
+	IMXDPUV1_CHAN_10 = make_channel(IMXDPUV1_ID_FETCHWARP2,               30, IMXDPUV1_SUB_1, 10),
+	IMXDPUV1_CHAN_11 = make_channel(IMXDPUV1_ID_FETCHWARP2,               30, IMXDPUV1_SUB_2, 11),
+	IMXDPUV1_CHAN_12 = make_channel(IMXDPUV1_ID_FETCHWARP2,               30, IMXDPUV1_SUB_3, 12),
+	IMXDPUV1_CHAN_13 = make_channel(IMXDPUV1_ID_FETCHWARP2,               30, IMXDPUV1_SUB_4, 13),
+	IMXDPUV1_CHAN_14 = make_channel(IMXDPUV1_ID_FETCHWARP2,               30, IMXDPUV1_SUB_5, 14),
+	IMXDPUV1_CHAN_15 = make_channel(IMXDPUV1_ID_FETCHWARP2,               30, IMXDPUV1_SUB_6, 15),
+	IMXDPUV1_CHAN_16 = make_channel(IMXDPUV1_ID_FETCHWARP2,               30, IMXDPUV1_SUB_7, 16),
+	IMXDPUV1_CHAN_17 = make_channel(IMXDPUV1_ID_FETCHWARP2,               30, IMXDPUV1_SUB_8, 17),
+	IMXDPUV1_CHAN_18 = make_channel(IMXDPUV1_ID_FETCHDECODE3,             30, IMXDPUV1_SUB_NONE, 18),
+	IMXDPUV1_CHAN_19 = make_channel(IMXDPUV1_ID_FETCHDECODE1,             29, IMXDPUV1_SUB_NONE, 19),
+	IMXDPUV1_CHAN_20 = make_channel(IMXDPUV1_ID_FETCHLAYER1,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_1, 20),
+	IMXDPUV1_CHAN_21 = make_channel(IMXDPUV1_ID_FETCHLAYER1,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_2, 21),
+	IMXDPUV1_CHAN_22 = make_channel(IMXDPUV1_ID_FETCHLAYER1,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_3, 22),
+	IMXDPUV1_CHAN_23 = make_channel(IMXDPUV1_ID_FETCHLAYER1,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_4, 23),
+	IMXDPUV1_CHAN_24 = make_channel(IMXDPUV1_ID_FETCHLAYER1,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_5, 24),
+	IMXDPUV1_CHAN_25 = make_channel(IMXDPUV1_ID_FETCHLAYER1,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_6, 25),
+	IMXDPUV1_CHAN_26 = make_channel(IMXDPUV1_ID_FETCHLAYER1,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_7, 26),
+	IMXDPUV1_CHAN_27 = make_channel(IMXDPUV1_ID_FETCHLAYER1,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_8, 27),
+	IMXDPUV1_CHAN_28 = make_channel(IMXDPUV1_ID_FETCHECO0,    IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 28),
+	IMXDPUV1_CHAN_29 = make_channel(IMXDPUV1_ID_FETCHECO1,    IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 29),
+	IMXDPUV1_CHAN_30 = make_channel(IMXDPUV1_ID_FETCHECO2,    IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 30),
+	/* Store Channels */
+	IMXDPUV1_CHAN_32 = make_channel(IMXDPUV1_ID_STORE4, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 32),
+	IMXDPUV1_CHAN_33 = make_channel(IMXDPUV1_ID_STORE5, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 33),
+#else
+	/* Fetch Channels */
+	IMXDPUV1_CHAN_00 = make_channel(0, 0, 0, 0),
+	IMXDPUV1_CHAN_01 = make_channel(IMXDPUV1_ID_FETCHDECODE0,             28, IMXDPUV1_SUB_NONE, 1),
+	IMXDPUV1_CHAN_02 = make_channel(IMXDPUV1_ID_FETCHLAYER0,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_1, 2),
+	IMXDPUV1_CHAN_03 = make_channel(IMXDPUV1_ID_FETCHLAYER0,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_2, 3),
+	IMXDPUV1_CHAN_04 = make_channel(IMXDPUV1_ID_FETCHLAYER0,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_3, 4),
+	IMXDPUV1_CHAN_05 = make_channel(IMXDPUV1_ID_FETCHLAYER0,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_4, 5),
+	IMXDPUV1_CHAN_06 = make_channel(IMXDPUV1_ID_FETCHLAYER0,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_5, 6),
+	IMXDPUV1_CHAN_07 = make_channel(IMXDPUV1_ID_FETCHLAYER0,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_6, 7),
+	IMXDPUV1_CHAN_08 = make_channel(IMXDPUV1_ID_FETCHLAYER0,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_7, 8),
+	IMXDPUV1_CHAN_09 = make_channel(IMXDPUV1_ID_FETCHLAYER0,  IMXDPUV1_ID_NONE, IMXDPUV1_SUB_8, 9),
+	IMXDPUV1_CHAN_10 = make_channel(IMXDPUV1_ID_FETCHWARP2,               30, IMXDPUV1_SUB_1, 10),
+	IMXDPUV1_CHAN_11 = make_channel(IMXDPUV1_ID_FETCHWARP2,               30, IMXDPUV1_SUB_2, 11),
+	IMXDPUV1_CHAN_12 = make_channel(IMXDPUV1_ID_FETCHWARP2,               30, IMXDPUV1_SUB_3, 12),
+	IMXDPUV1_CHAN_13 = make_channel(IMXDPUV1_ID_FETCHWARP2,               30, IMXDPUV1_SUB_4, 13),
+	IMXDPUV1_CHAN_14 = make_channel(IMXDPUV1_ID_FETCHWARP2,               30, IMXDPUV1_SUB_5, 14),
+	IMXDPUV1_CHAN_15 = make_channel(IMXDPUV1_ID_FETCHWARP2,               30, IMXDPUV1_SUB_6, 15),
+	IMXDPUV1_CHAN_16 = make_channel(IMXDPUV1_ID_FETCHWARP2,               30, IMXDPUV1_SUB_7, 16),
+	IMXDPUV1_CHAN_17 = make_channel(IMXDPUV1_ID_FETCHWARP2,               30, IMXDPUV1_SUB_8, 17),
+	IMXDPUV1_CHAN_18 = make_channel(0, 0, 0, 0),
+	IMXDPUV1_CHAN_19 = make_channel(IMXDPUV1_ID_FETCHDECODE1,             29, IMXDPUV1_SUB_NONE, 19),
+	IMXDPUV1_CHAN_20 = make_channel(0, 0, 0, 0),
+	IMXDPUV1_CHAN_21 = make_channel(0, 0, 0, 0),
+	IMXDPUV1_CHAN_22 = make_channel(0, 0, 0, 0),
+	IMXDPUV1_CHAN_23 = make_channel(0, 0, 0, 0),
+	IMXDPUV1_CHAN_24 = make_channel(0, 0, 0, 0),
+	IMXDPUV1_CHAN_25 = make_channel(0, 0, 0, 0),
+	IMXDPUV1_CHAN_26 = make_channel(0, 0, 0, 0),
+	IMXDPUV1_CHAN_27 = make_channel(0, 0, 0, 0),
+	IMXDPUV1_CHAN_28 = make_channel(IMXDPUV1_ID_FETCHECO0,    IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 28),
+	IMXDPUV1_CHAN_29 = make_channel(IMXDPUV1_ID_FETCHECO1,    IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 29),
+	IMXDPUV1_CHAN_30 = make_channel(IMXDPUV1_ID_FETCHECO2,    IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 30),
+	/* Store Channels */
+	IMXDPUV1_CHAN_32 = make_channel(0, 0, 0, 0),
+	IMXDPUV1_CHAN_33 = make_channel(0, 0, 0, 0),
+#endif
+} imxdpuv1_chan_t;
+
+/* Aliases for Channels */
+#define IMXDPUV1_CHAN_VIDEO_0        IMXDPUV1_CHAN_01
+#define IMXDPUV1_CHAN_VIDEO_1        IMXDPUV1_CHAN_19
+
+#define IMXDPUV1_CHAN_INTEGRAL_0    IMXDPUV1_CHAN_00
+#define IMXDPUV1_CHAN_INTEGRAL_1    IMXDPUV1_CHAN_18
+
+#define IMXDPUV1_CHAN_FRACTIONAL_0_1 IMXDPUV1_CHAN_02
+#define IMXDPUV1_CHAN_FRACTIONAL_0_2 IMXDPUV1_CHAN_03
+#define IMXDPUV1_CHAN_FRACTIONAL_0_3 IMXDPUV1_CHAN_04
+#define IMXDPUV1_CHAN_FRACTIONAL_0_4 IMXDPUV1_CHAN_05
+#define IMXDPUV1_CHAN_FRACTIONAL_0_5 IMXDPUV1_CHAN_06
+#define IMXDPUV1_CHAN_FRACTIONAL_0_6 IMXDPUV1_CHAN_07
+#define IMXDPUV1_CHAN_FRACTIONAL_0_7 IMXDPUV1_CHAN_08
+#define IMXDPUV1_CHAN_FRACTIONAL_0_8 IMXDPUV1_CHAN_09
+
+#define IMXDPUV1_CHAN_FRACTIONAL_1_1 IMXDPUV1_CHAN_20
+#define IMXDPUV1_CHAN_FRACTIONAL_1_2 IMXDPUV1_CHAN_21
+#define IMXDPUV1_CHAN_FRACTIONAL_1_3 IMXDPUV1_CHAN_22
+#define IMXDPUV1_CHAN_FRACTIONAL_1_4 IMXDPUV1_CHAN_23
+#define IMXDPUV1_CHAN_FRACTIONAL_1_5 IMXDPUV1_CHAN_24
+#define IMXDPUV1_CHAN_FRACTIONAL_1_6 IMXDPUV1_CHAN_25
+#define IMXDPUV1_CHAN_FRACTIONAL_1_7 IMXDPUV1_CHAN_26
+#define IMXDPUV1_CHAN_FRACTIONAL_1_8 IMXDPUV1_CHAN_27
+
+#define IMXDPUV1_CHAN_WARP_2_1 IMXDPUV1_CHAN_10
+#define IMXDPUV1_CHAN_WARP_2_2 IMXDPUV1_CHAN_11
+#define IMXDPUV1_CHAN_WARP_2_3 IMXDPUV1_CHAN_12
+#define IMXDPUV1_CHAN_WARP_2_4 IMXDPUV1_CHAN_13
+#define IMXDPUV1_CHAN_WARP_2_5 IMXDPUV1_CHAN_14
+#define IMXDPUV1_CHAN_WARP_2_6 IMXDPUV1_CHAN_15
+#define IMXDPUV1_CHAN_WARP_2_7 IMXDPUV1_CHAN_16
+#define IMXDPUV1_CHAN_WARP_2_8 IMXDPUV1_CHAN_17
+
+#define IMXDPUV1_CHAN_CAPTURE_0        IMXDPUV1_CHAN_32
+#define IMXDPUV1_CHAN_CAPTURE_1        IMXDPUV1_CHAN_33
+
+
+/*  IMXDPU Pixel format definitions */
+/*  Four-character-code (FOURCC) */
+#ifdef fourcc
+#warning "fourcc is already defined ... redeifining it here!"
+#undef  fourcc
+#endif
+#define fourcc(a, b, c, d)\
+	 (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
+
+
+/*! @} */
+/*! @name Generic Formats */
+/*! @{ */
+#define IMXDPUV1_PIX_FMT_GENERIC fourcc('D', 'P', 'U', '0')	/*!< IPU Generic Data */
+#define IMXDPUV1_PIX_FMT_GENERIC_32 fourcc('D', 'P', 'U', '1')	/*!< IPU Generic Data */
+#define IMXDPUV1_PIX_FMT_GENERIC_16 fourcc('D', 'P', 'U', '2')	/*!< IPU Generic Data */
+
+/*! @} */
+/*! @name RGB Formats */
+/*! @{ */
+#define IMXDPUV1_PIX_FMT_RGB332  fourcc('R', 'G', 'B', '1')	/*!<  8  RGB-3-3-2    */
+#define IMXDPUV1_PIX_FMT_RGB555  fourcc('R', 'G', 'B', 'O')	/*!< 16  RGB-5-5-5    */
+#define IMXDPUV1_PIX_FMT_RGB565  fourcc('R', 'G', 'B', 'P')	/*!< 16  RGB-5-6-5    */
+#define IMXDPUV1_PIX_FMT_BGRA4444 fourcc('4', '4', '4', '4')	/*!< 16  RGBA-4-4-4-4 */
+#define IMXDPUV1_PIX_FMT_BGRA5551 fourcc('5', '5', '5', '1')	/*!< 16  RGBA-5-5-5-1 */
+#define IMXDPUV1_PIX_FMT_RGB666  fourcc('R', 'G', 'B', '6')	/*!< 18  RGB-6-6-6    */
+#define IMXDPUV1_PIX_FMT_BGR666  fourcc('B', 'G', 'R', '6')	/*!< 18  BGR-6-6-6    */
+#define IMXDPUV1_PIX_FMT_BGR24   fourcc('B', 'G', 'R', '3')	/*!< 24  BGR-8-8-8    */
+#define IMXDPUV1_PIX_FMT_RGB24   fourcc('R', 'G', 'B', '3')	/*!< 24  RGB-8-8-8    */
+#define IMXDPUV1_PIX_FMT_GBR24   fourcc('G', 'B', 'R', '3')	/*!< 24  GBR-8-8-8    */
+#define IMXDPUV1_PIX_FMT_BGR32   fourcc('B', 'G', 'R', '4')	/*!< 32  BGR-8-8-8-8  */
+#define IMXDPUV1_PIX_FMT_BGRA32  fourcc('B', 'G', 'R', 'A')	/*!< 32  BGR-8-8-8-8  */
+#define IMXDPUV1_PIX_FMT_RGB32   fourcc('R', 'G', 'B', '4')	/*!< 32  RGB-8-8-8-8  */
+#define IMXDPUV1_PIX_FMT_RGBA32  fourcc('R', 'G', 'B', 'A')	/*!< 32  RGB-8-8-8-8  */
+#define IMXDPUV1_PIX_FMT_ABGR32  fourcc('A', 'B', 'G', 'R')	/*!< 32  ABGR-8-8-8-8 */
+#define IMXDPUV1_PIX_FMT_ARGB32  fourcc('A', 'R', 'G', 'B')	/*!< 32  ARGB-8-8-8-8 */
+
+/*! @} */
+/*! @name YUV Interleaved Formats */
+/*! @{ */
+#define IMXDPUV1_PIX_FMT_YUYV    fourcc('Y', 'U', 'Y', 'V')	/*!< 16 YUV 4:2:2 */
+#define IMXDPUV1_PIX_FMT_UYVY    fourcc('U', 'Y', 'V', 'Y')	/*!< 16 YUV 4:2:2 */
+#define IMXDPUV1_PIX_FMT_YVYU    fourcc('Y', 'V', 'Y', 'U')	/*!< 16 YVYU 4:2:2 */
+#define IMXDPUV1_PIX_FMT_VYUY    fourcc('V', 'Y', 'U', 'Y')	/*!< 16 VYYU 4:2:2 */
+#define IMXDPUV1_PIX_FMT_Y41P    fourcc('Y', '4', '1', 'P')	/*!< 12 YUV 4:1:1 */
+#define IMXDPUV1_PIX_FMT_YUV444  fourcc('Y', '4', '4', '4')	/*!< 24 YUV 4:4:4 */
+#define IMXDPUV1_PIX_FMT_VYU444  fourcc('V', '4', '4', '4')	/*!< 24 VYU 4:4:4 */
+#define IMXDPUV1_PIX_FMT_AYUV    fourcc('A', 'Y', 'U', 'V')	/*!< 32 AYUV 4:4:4:4 */
+
+/* two planes -- one Y, one Cb + Cr interleaved  */
+#define IMXDPUV1_PIX_FMT_NV12    fourcc('N', 'V', '1', '2')	/* 12  Y/CbCr 4:2:0  */
+#define IMXDPUV1_PIX_FMT_NV16    fourcc('N', 'V', '1', '6')	/* 16  Y/CbCr 4:2:2  */
+
+#define IMXDPUV1_CAP_FMT_RGB24   fourcc('R', 'G', 'B', '3')
+#define IMXDPUV1_CAP_FMT_BT656   fourcc('B', '6', '5', '6')
+#define IMXDPUV1_CAP_FMT_YUYV    fourcc('Y', 'U', 'Y', 'V')
+
+struct imxdpuv1_soc;
+/*!
+ * Definition of IMXDPU rectangle structure
+ */
+typedef struct {
+	int16_t top;		/* y coordinate of top/left pixel */
+	int16_t left;		/* x coordinate top/left pixel */
+	int16_t width;
+	int16_t height;
+} imxdpuv1_rect_t;
+
+
+/*!
+ * Union of initialization parameters for a logical channel.
+ */
+typedef union {
+	struct {
+		imxdpuv1_chan_t chan;
+		uint32_t src_pixel_fmt;
+		uint16_t src_width;
+		uint16_t src_height;
+		int16_t clip_top;
+		int16_t clip_left;
+		uint16_t clip_width;
+		uint16_t clip_height;
+		uint16_t stride;
+		uint32_t dest_pixel_fmt;
+		uint8_t blend_mode;
+		uint8_t blend_layer;
+		uint8_t disp_id; /* capture id */
+		int16_t dest_top;
+		int16_t dest_left;
+		uint16_t dest_width;
+		uint16_t dest_height;
+		uint32_t const_color;
+		bool use_global_alpha;
+		bool use_local_alpha;
+	} common;
+	struct {
+		imxdpuv1_chan_t chan;
+		uint32_t src_pixel_fmt;
+		uint16_t src_width;
+		uint16_t src_height;
+		int16_t clip_top;
+		int16_t clip_left;
+		uint16_t clip_width;
+		uint16_t clip_height;
+		uint16_t stride;
+		uint32_t dest_pixel_fmt;
+		uint8_t blend_mode;
+		uint8_t blend_layer;
+		uint8_t capture_id; /* disp_id/capture id */
+		int16_t dest_top;
+		int16_t dest_left;
+		uint16_t dest_width;
+		uint16_t dest_height;
+		uint32_t const_color;
+		bool use_global_alpha;
+		bool use_local_alpha;
+		uint32_t h_scale_factor;    /* downscaling  out/in */
+		uint32_t h_phase;
+		uint32_t v_scale_factor;    /* downscaling  out/in */
+		uint32_t v_phase[2][2];
+		bool use_video_proc;
+		bool interlaced;
+	} store;
+	struct {
+		imxdpuv1_chan_t chan;
+		uint32_t src_pixel_fmt;
+		uint16_t src_width;
+		uint16_t src_height;
+		int16_t clip_top;
+		int16_t clip_left;
+		uint16_t clip_width;
+		uint16_t clip_height;
+		uint16_t stride;
+		uint32_t dest_pixel_fmt;
+		uint8_t blend_mode;
+		uint8_t blend_layer;
+		uint8_t disp_id;
+		int16_t dest_top;
+		int16_t dest_left;
+		uint16_t dest_width;
+		uint16_t dest_height;
+		uint32_t const_color;
+		bool use_global_alpha;
+		bool use_local_alpha;
+		uint32_t h_scale_factor;    /* downscaling  out/in */
+		uint32_t h_phase;
+		uint32_t v_scale_factor;    /* downscaling  out/in */
+		uint32_t v_phase[2][2];
+		bool use_video_proc;
+		bool interlaced;
+	} fetch_decode;
+	struct {
+		imxdpuv1_chan_t chan;
+		uint32_t src_pixel_fmt;
+		uint16_t src_width;
+		uint16_t src_height;
+		int16_t clip_top;
+		int16_t clip_left;
+		uint16_t clip_width;
+		uint16_t clip_height;
+		uint16_t stride;
+		uint32_t dest_pixel_fmt;
+		uint8_t blend_mode;
+		uint8_t blend_layer;
+		uint8_t disp_id; /* capture id */
+		int16_t dest_top;
+		int16_t dest_left;
+		uint16_t dest_width;
+		uint16_t dest_height;
+		uint32_t const_color;
+		bool use_global_alpha;
+		bool use_local_alpha;
+	} fetch_layer;
+	struct {
+		imxdpuv1_chan_t chan;
+		uint32_t src_pixel_fmt;
+		uint16_t src_width;
+		uint16_t src_height;
+		int16_t clip_top;
+		int16_t clip_left;
+		uint16_t clip_width;
+		uint16_t clip_height;
+		uint16_t stride;
+		uint32_t dest_pixel_fmt;
+		uint8_t blend_mode;
+		uint8_t blend_layer;
+		uint8_t disp_id; /* capture id */
+		int16_t dest_top;
+		int16_t dest_left;
+		uint16_t dest_width;
+		uint16_t dest_height;
+		uint32_t const_color;
+		bool use_global_alpha;
+		bool use_local_alpha;
+	} fetch_warp;
+} imxdpuv1_channel_params_t;
+
+/*!
+ * Enumeration of IMXDPU video mode flags
+ */
+enum imxdpuv1_mode_flags {
+	/* 1 is active high 0 is active low */
+	IMXDPUV1_MODE_FLAGS_HSYNC_POL     = 1 << 0,
+	IMXDPUV1_MODE_FLAGS_VSYNC_POL     = 1 << 1,
+	IMXDPUV1_MODE_FLAGS_DE_POL        = 1 << 2,
+
+	/* drive data on positive .edge */
+	IMXDPUV1_MODE_FLAGS_CLK_POL       = 1 << 3,
+
+	IMXDPUV1_MODE_FLAGS_INTERLACED    = 1 << 4 ,
+
+	/* Left/Right Synchronous display mode,  both display pipe are
+	   combined to make one display. All mode timings are divided by
+	   two for each half screen.
+	   Note: This may not be needed we may force this for any width
+	   over ~2048
+	 */
+	IMXDPUV1_MODE_FLAGS_LRSYNC        = 1 << 8,
+
+	/* Split mode each pipe is split into two displays  */
+	IMXDPUV1_MODE_FLAGS_SPLIT         = 1 << 9,
+
+	IMXDPUV1_MODE_FLAGS_32BIT          = 1 << 16,
+	IMXDPUV1_MODE_FLAGS_BT656_10BIT    = 1 << 17,
+	IMXDPUV1_MODE_FLAGS_BT656_8BIT     = 1 << 18,
+};
+
+struct imxdpuv1_videomode {
+	char name[64];		/* may not be needed */
+
+	uint32_t pixelclock;	/* Hz */
+
+	/* htotal (pixels) = hlen + hfp + hsync + hbp */
+	uint32_t hlen;
+	uint32_t hfp;
+	uint32_t hbp;
+	uint32_t hsync;
+
+	/* field0 - vtotal (lines) = vlen + vfp + vsync + vbp */
+	uint32_t vlen;
+	uint32_t vfp;
+	uint32_t vbp;
+	uint32_t vsync;
+
+	/* field1  */
+	uint32_t vlen1;
+	uint32_t vfp1;
+	uint32_t vbp1;
+	uint32_t vsync1;
+
+	uint32_t flags;
+	uint32_t format;
+	uint32_t dest_format; /*buffer format for capture*/
+	int16_t  clip_top;
+	int16_t  clip_left;
+	uint16_t clip_width;
+	uint16_t clip_height;
+
+};
+
+#define IMXDPUV1_ENABLE  1
+#define IMXDPUV1_DISABLE 0
+
+#define IMXDPUV1_TRUE    1
+#define IMXDPUV1_FALSE   0
+#define IMXDPUV1_OFFSET_INVALID 0x10000000	/* this should force an access error */
+#define IMXDPUV1_CHANNEL_INVALID 0x0	/* this should force an access error */
+
+#define IMXDPUV1_MIN(_X, _Y) ((_X) < (_Y) ? (_X) : (_Y))
+
+/* Native color type */
+#define IMXDPUV1_COLOR_CONSTALPHA_MASK 0xFFU
+#define IMXDPUV1_COLOR_CONSTALPHA_SHIFT 0U
+#define IMXDPUV1_COLOR_CONSTBLUE_MASK 0xFF00U
+#define IMXDPUV1_COLOR_CONSTBLUE_SHIFT 8U
+#define IMXDPUV1_COLOR_CONSTGREEN_MASK 0xFF0000U
+#define IMXDPUV1_COLOR_CONSTGREEN_SHIFT 16U
+#define IMXDPUV1_COLOR_CONSTRED_MASK  0xFF000000U
+#define IMXDPUV1_COLOR_CONSTRED_SHIFT 24U
+
+#define IMXDPUV1_IRQF_NONE    0x0
+#define IMXDPUV1_IRQF_ONESHOT 0x1
+#define IMXDPUV1_INTERRUPT_MAX  (66 + 1)	/* IMXDPUV1_FRAMECAP5_SYNC_OFF_IRQ
+					   (66) is last interrupt */
+
+int imxdpuv1_enable_irq(int8_t imxdpuv1_id, uint32_t irq);
+int imxdpuv1_disable_irq(int8_t imxdpuv1_id, uint32_t irq);
+int imxdpuv1_clear_all_irqs(int8_t imxdpuv1_id);
+int imxdpuv1_clear_irq(int8_t imxdpuv1_id, uint32_t irq);
+int imxdpuv1_init_irqs(int8_t imxdpuv1_id);
+int imxdpuv1_request_irq(int8_t imxdpuv1_id,
+	uint32_t irq,
+	int(*handler) (int, void *),
+	uint32_t irq_flags,
+	const char *devname, void *data) ;
+int imxdpuv1_free_irq(int8_t imxdpuv1_id, uint32_t irq, void *data);
+int imxdpuv1_uninit_interrupts(int8_t imxdpuv1_id);
+int imxdpuv1_handle_irq(int32_t imxdpuv1_id);
+struct imxdpuv1_soc *imxdpuv1_get_soc(int8_t imxdpuv1_id);
+int imxdpuv1_init(int8_t imxdpuv1_id);
+int imxdpuv1_init_sync_panel(int8_t imxdpuv1_id, int8_t disp,
+	uint32_t pixel_fmt,
+	struct imxdpuv1_videomode mode);
+int imxdpuv1_uninit_sync_panel(int8_t imxdpuv1_id, int8_t disp);
+int imxdpuv1_reset_disp_panel(int8_t imxdpuv1_id, int8_t disp);
+int imxdpuv1_disp_init(int8_t imxdpuv1_id, int8_t disp);
+int imxdpuv1_disp_setup_frame_gen(
+	int8_t imxdpuv1_id,
+	int8_t disp,
+	const struct imxdpuv1_videomode *mode,
+	uint16_t cc_red,	/* 10 bits */
+	uint16_t cc_green,	/* 10 bits */
+	uint16_t cc_blue,	/* 10 bits */
+	uint8_t cc_alpha,
+	bool test_mode_enable);
+int imxdpuv1_disp_enable_frame_gen(int8_t imxdpuv1_id,
+	int8_t disp,
+	bool enable);
+int imxdpuv1_disp_setup_constframe(int8_t imxdpuv1_id,
+	int8_t disp,
+	uint8_t bg_red,
+	uint8_t bg_green,
+	uint8_t bg_blue,
+	uint8_t bg_alpha);
+int imxdpuv1_disp_setup_layer(int8_t imxdpuv1_id,
+	const imxdpuv1_layer_t *layer,
+			    imxdpuv1_layer_idx_t layer_idx,
+			    bool is_top_layer);
+void imxdpuv1_disp_dump_mode(const struct imxdpuv1_videomode *mode);
+int imxdpuv1_bytes_per_pixel(uint32_t fmt);
+int imxdpuv1_init_channel_buffer(int8_t imxdpuv1_id,
+	imxdpuv1_chan_t chan,
+	uint32_t stride,
+	imxdpuv1_rotate_mode_t rot_mode,
+	dma_addr_t phyaddr_0,
+	uint32_t u_offset,
+	uint32_t v_offset);
+int32_t imxdpuv1_update_channel_buffer(int8_t imxdpuv1_id,
+	imxdpuv1_chan_t chan,
+	dma_addr_t phyaddr_0);
+int imxdpuv1_init_channel(int8_t imxdpuv1_id,
+	imxdpuv1_channel_params_t *params);
+int imxdpuv1_disp_set_layer_global_alpha(int8_t imxdpuv1_id,
+	imxdpuv1_layer_idx_t layer_idx,
+	uint8_t alpha);
+int imxdpuv1_disp_set_layer_position(int8_t imxdpuv1_id,
+	imxdpuv1_layer_idx_t layer_idx,
+	int16_t x, int16_t y);
+int imxdpuv1_disp_set_chan_position(int8_t imxdpuv1_id,
+	imxdpuv1_chan_t chan,
+	int16_t x, int16_t y);
+int imxdpuv1_disp_update_fgen_status(int8_t imxdpuv1_id, int8_t disp);
+int imxdpuv1_disp_show_fgen_status(int8_t imxdpuv1_id);
+void imxdpuv1_dump_int_stat(int8_t imxdpuv1_id);
+void imxdpuv1_dump_layerblend(int8_t imxdpuv1_id);
+int imxdpuv1_disp_force_shadow_load(int8_t imxdpuv1_id,
+	int8_t disp,
+	uint64_t mask);
+int imxdpuv1_disp_set_chan_crop(int8_t imxdpuv1_id,
+	imxdpuv1_chan_t chan,
+	int16_t  clip_top,
+	int16_t  clip_left,
+	uint16_t clip_width,
+	uint16_t clip_height,
+	int16_t  dest_top,
+	int16_t  dest_left,
+	uint16_t dest_width,
+	uint16_t dest_height);
+void imxdpuv1_dump_pixencfg_status(int8_t imxdpuv1_id);
+int imxdpuv1_dump_channel(int8_t imxdpuv1_id, imxdpuv1_chan_t chan);
+uint32_t imxdpuv1_get_planes(uint32_t fmt);
+
+int imxdpuv1_disp_setup_channel(int8_t imxdpuv1_id,
+			      imxdpuv1_chan_t chan,
+			      uint32_t src_pixel_fmt,
+			      uint16_t src_width,
+			      uint16_t src_height,
+			      int16_t clip_top,
+			      int16_t clip_left,
+			      uint16_t clip_width,
+			      uint16_t clip_height,
+			      uint16_t stride,
+			      uint8_t disp_id,
+			      int16_t dest_top,
+			      int16_t dest_left,
+			      uint16_t dest_width,
+			      uint16_t dest_height,
+			      uint32_t const_color,
+			      bool use_global_alpha,
+			      bool use_local_alpha,
+			      unsigned int disp_addr);
+int imxdpuv1_disp_check_shadow_loads(int8_t imxdpuv1_id, int8_t disp);
+
+int imxdpuv1_cap_setup_frame(
+	int8_t imxdpuv1_id,
+	int8_t src_id,
+	int8_t dest_id,
+	int8_t sync_count,
+	const struct imxdpuv1_videomode *cap_mode);
+int imxdpuv1_cap_setup_crop(
+	int8_t imxdpuv1_id,
+	int8_t src_id,
+	int16_t  clip_top,
+	int16_t  clip_left,
+	uint16_t clip_width,
+	uint16_t clip_height);
+
+int imxdpuv1_cap_enable(int8_t imxdpuv1_id, int8_t cap, bool enable);
+int imxdpuv1_cap_request_shadow_load(int8_t imxdpuv1_id, int8_t dest_id, uint32_t mask);
+
+/* FIXME: add api if needed */
+static inline int32_t imxdpuv1_csi_enable_mclk_if(int8_t imxdpuv1_id, int src, uint32_t cap,
+		bool flag, bool wait)
+{
+	printf("%s(): %s:%d stubbed feature\n", __func__, __FILE__, __LINE__);
+	return 0;
+}
+#endif				/* IMXDPUV1_H */
diff --git a/include/imxdpuv1_events.h b/include/imxdpuv1_events.h
new file mode 100644
index 00000000000..7f8ed8157d0
--- /dev/null
+++ b/include/imxdpuv1_events.h
@@ -0,0 +1,353 @@
+/*
+ * Copyright (c) 2005-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef IMXDPUV1_EVENTS_H
+#define IMXDPUV1_EVENTS_H
+
+/* Shadow load (Blit Engine) */
+#define IMXDPUV1_STORE9_SHDLOAD_IRQ	0U
+#define IMXDPUV1_STORE9_SHDLOAD_CMD	0U
+
+/* Frame complete (Blit Engine) */
+#define IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ	1U
+#define IMXDPUV1_STORE9_FRAMECOMPLETE_CMD	1U
+
+/* Sequence complete (Blit Engine) */
+#define IMXDPUV1_STORE9_SEQCOMPLETE_IRQ	2U
+#define IMXDPUV1_STORE9_SEQCOMPLETE_CMD	2U
+
+/* Shadow load (Display Controller Content Stream 0) */
+#define IMXDPUV1_EXTDST0_SHDLOAD_IRQ	3U
+#define IMXDPUV1_EXTDST0_SHDLOAD_CMD	3U
+
+/* Frame complete (Display Controller Content Stream 0) */
+#define IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ	4U
+#define IMXDPUV1_EXTDST0_FRAMECOMPLETE_CMD	4U
+
+/* Sequence complete (Display Controller Content Stream 0) */
+#define IMXDPUV1_EXTDST0_SEQCOMPLETE_IRQ	5U
+#define IMXDPUV1_EXTDST0_SEQCOMPLETE_CMD	5U
+
+/* Shadow load (Display Controller Safety Stream 0) */
+#define IMXDPUV1_EXTDST4_SHDLOAD_IRQ	6U
+#define IMXDPUV1_EXTDST4_SHDLOAD_CMD	6U
+
+/* Frame complete (Display Controller Safety Stream 0) */
+#define IMXDPUV1_EXTDST4_FRAMECOMPLETE_IRQ	7U
+#define IMXDPUV1_EXTDST4_FRAMECOMPLETE_CMD	7U
+
+/* Sequence complete (Display Controller Safety Stream 0) */
+#define IMXDPUV1_EXTDST4_SEQCOMPLETE_IRQ	8U
+#define IMXDPUV1_EXTDST4_SEQCOMPLETE_CMD	8U
+
+/* Shadow load (Display Controller Content Stream 1) */
+#define IMXDPUV1_EXTDST1_SHDLOAD_IRQ	9U
+#define IMXDPUV1_EXTDST1_SHDLOAD_CMD	9U
+
+/* Frame complete (Display Controller Content Stream 1) */
+#define IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ	10U
+#define IMXDPUV1_EXTDST1_FRAMECOMPLETE_CMD	10U
+
+/* Sequence complete (Display Controller Content Stream 1) */
+#define IMXDPUV1_EXTDST1_SEQCOMPLETE_IRQ	11U
+#define IMXDPUV1_EXTDST1_SEQCOMPLETE_CMD	11U
+
+/* Shadow load (Display Controller Safety Stream 1) */
+#define IMXDPUV1_EXTDST5_SHDLOAD_IRQ	12U
+#define IMXDPUV1_EXTDST5_SHDLOAD_CMD	12U
+
+/* Frame complete (Display Controller Safety Stream 1) */
+#define IMXDPUV1_EXTDST5_FRAMECOMPLETE_IRQ	13U
+#define IMXDPUV1_EXTDST5_FRAMECOMPLETE_CMD	13U
+
+/* Sequence complete (Display Controller Safety Stream 1) */
+#define IMXDPUV1_EXTDST5_SEQCOMPLETE_IRQ	14U
+#define IMXDPUV1_EXTDST5_SEQCOMPLETE_CMD	14U
+
+/* Shadow load (Display Controller Display Stream 0) */
+#define IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ	15U
+#define IMXDPUV1_DISENGCFG_SHDLOAD0_CMD	15U
+
+/* Frame complete (Display Controller Display Stream 0) */
+#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_IRQ	16U
+#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_CMD	16U
+
+/* Sequence complete (Display Controller Display Stream 0) */
+#define IMXDPUV1_DISENGCFG_SEQCOMPLETE0_IRQ	17U
+#define IMXDPUV1_DISENGCFG_SEQCOMPLETE0_CMD	17U
+
+/* Programmable interrupt 0 (Display Controller Display Stream 0 FrameGen #0 unit) */
+#define IMXDPUV1_FRAMEGEN0_INT0_IRQ	18U
+#define IMXDPUV1_FRAMEGEN0_INT0_CMD	18U
+
+/* Programmable interrupt 1 (Display Controller Display Stream 0 FrameGen #0 unit) */
+#define IMXDPUV1_FRAMEGEN0_INT1_IRQ	19U
+#define IMXDPUV1_FRAMEGEN0_INT1_CMD	19U
+
+/* Programmable interrupt 2 (Display Controller Display Stream 0 FrameGen #0 unit) */
+#define IMXDPUV1_FRAMEGEN0_INT2_IRQ	20U
+#define IMXDPUV1_FRAMEGEN0_INT2_CMD	20U
+
+/* Programmable interrupt 3 (Display Controller Display Stream 0 FrameGen #0 unit) */
+#define IMXDPUV1_FRAMEGEN0_INT3_IRQ	21U
+#define IMXDPUV1_FRAMEGEN0_INT3_CMD	21U
+
+/* Shadow load (Display Controller Display Stream 0 Sig #0 unit) */
+#define IMXDPUV1_SIG0_SHDLOAD_IRQ	22U
+#define IMXDPUV1_SIG0_SHDLOAD_CMD	22U
+
+/* Measurement valid (Display Controller Display Stream 0 Sig #0 unit) */
+#define IMXDPUV1_SIG0_VALID_IRQ	23U
+#define IMXDPUV1_SIG0_VALID_CMD	23U
+
+/* Error condition (Display Controller Display Stream 0 Sig #0 unit) */
+#define IMXDPUV1_SIG0_ERROR_IRQ	24U
+#define IMXDPUV1_SIG0_ERROR_CMD	24U
+
+/* Shadow load (Display Controller Display Stream 1) */
+#define IMXDPUV1_DISENGCFG_SHDLOAD1_IRQ	25U
+#define IMXDPUV1_DISENGCFG_SHDLOAD1_CMD	25U
+
+/* Frame complete (Display Controller Display Stream 1) */
+#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE1_IRQ	26U
+#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE1_CMD	26U
+
+/* Sequence complete (Display Controller Display Stream 1) */
+#define IMXDPUV1_DISENGCFG_SEQCOMPLETE1_IRQ	27U
+#define IMXDPUV1_DISENGCFG_SEQCOMPLETE1_CMD	27U
+
+/* Programmable interrupt 0 (Display Controller Display Stream 1 FrameGen #1 unit) */
+#define IMXDPUV1_FRAMEGEN1_INT0_IRQ	28U
+#define IMXDPUV1_FRAMEGEN1_INT0_CMD	28U
+
+/* Programmable interrupt 1 (Display Controller Display Stream 1 FrameGen #1 unit) */
+#define IMXDPUV1_FRAMEGEN1_INT1_IRQ	29U
+#define IMXDPUV1_FRAMEGEN1_INT1_CMD	29U
+
+/* Programmable interrupt 2 (Display Controller Display Stream 1 FrameGen #1 unit) */
+#define IMXDPUV1_FRAMEGEN1_INT2_IRQ	30U
+#define IMXDPUV1_FRAMEGEN1_INT2_CMD	30U
+
+/* Programmable interrupt 3 (Display Controller Display Stream 1 FrameGen #1 unit) */
+#define IMXDPUV1_FRAMEGEN1_INT3_IRQ	31U
+#define IMXDPUV1_FRAMEGEN1_INT3_CMD	31U
+
+/* Shadow load (Display Controller Display Stream 1 Sig #1 unit) */
+#define IMXDPUV1_SIG1_SHDLOAD_IRQ	32U
+#define IMXDPUV1_SIG1_SHDLOAD_CMD	32U
+
+/* Measurement valid (Display Controller Display Stream 1 Sig #1 unit) */
+#define IMXDPUV1_SIG1_VALID_IRQ	33U
+#define IMXDPUV1_SIG1_VALID_CMD	33U
+
+/* Error condition (Display Controller Display Stream 1 Sig #1 unit) */
+#define IMXDPUV1_SIG1_ERROR_IRQ	34U
+#define IMXDPUV1_SIG1_ERROR_CMD	34U
+
+/* Reserved Do not use */
+#define IMXDPUV1_RESERVED35_IRQ	35U
+#define IMXDPUV1_RESERVED35_CMD	35U
+
+/* Error condition (Command Sequencer) */
+#define IMXDPUV1_CMDSEQ_ERROR_IRQ	36U
+#define IMXDPUV1_CMDSEQ_ERROR_CMD	36U
+
+/* Software interrupt 0 (Common Control) */
+#define IMXDPUV1_COMCTRL_SW0_IRQ	37U
+#define IMXDPUV1_COMCTRL_SW0_CMD	37U
+
+/* Software interrupt 1 (Common Control) */
+#define IMXDPUV1_COMCTRL_SW1_IRQ	38U
+#define IMXDPUV1_COMCTRL_SW1_CMD	38U
+
+/* Software interrupt 2 (Common Control) */
+#define IMXDPUV1_COMCTRL_SW2_IRQ	39U
+#define IMXDPUV1_COMCTRL_SW2_CMD	39U
+
+/* Software interrupt 3 (Common Control) */
+#define IMXDPUV1_COMCTRL_SW3_IRQ	40U
+#define IMXDPUV1_COMCTRL_SW3_CMD	40U
+
+/* Synchronization status activated (Display Controller Safety stream 0) */
+#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_ON_IRQ	41U
+#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_ON_CMD	41U
+
+/* Synchronization status deactivated (Display Controller Safety stream 0) */
+#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_OFF_IRQ	42U
+#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_OFF_CMD	42U
+
+/* Synchronization status activated (Display Controller Content stream 0) */
+#define IMXDPUV1_FRAMEGEN0_SECSYNC_ON_IRQ	43U
+#define IMXDPUV1_FRAMEGEN0_SECSYNC_ON_CMD	43U
+
+/* Synchronization status deactivated (Display Controller Content stream 0) */
+#define IMXDPUV1_FRAMEGEN0_SECSYNC_OFF_IRQ	44U
+#define IMXDPUV1_FRAMEGEN0_SECSYNC_OFF_CMD	44U
+
+/* Synchronization status activated (Display Controller Safety stream 1) */
+#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_ON_IRQ	45U
+#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_ON_CMD	45U
+
+/* Synchronization status deactivated (Display Controller Safety stream 1) */
+#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_OFF_IRQ	46U
+#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_OFF_CMD	46U
+
+/* Synchronization status activated (Display Controller Content stream 1) */
+#define IMXDPUV1_FRAMEGEN1_SECSYNC_ON_IRQ	47U
+#define IMXDPUV1_FRAMEGEN1_SECSYNC_ON_CMD	47U
+
+/* Synchronization status deactivated (Display Controller Content stream 1) */
+#define IMXDPUV1_FRAMEGEN1_SECSYNC_OFF_IRQ	48U
+#define IMXDPUV1_FRAMEGEN1_SECSYNC_OFF_CMD	48U
+
+/* Synchronization status (Display Controller Safety stream 0) */
+#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_CMD	49U
+#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_STS	0U
+
+/* Synchronization status (Display Controller Content stream 0) */
+#define IMXDPUV1_FRAMEGEN0_SECSYNC_CMD	50U
+#define IMXDPUV1_FRAMEGEN0_SECSYNC_STS	1U
+
+/* Synchronization status (Display Controller Safety stream 1) */
+#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_CMD	51U
+#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_STS	2U
+
+/* Synchronization status (Display Controller Content stream 1) */
+#define IMXDPUV1_FRAMEGEN1_SECSYNC_CMD	52U
+#define IMXDPUV1_FRAMEGEN1_SECSYNC_STS	3U
+
+/* Shadow load request (Display Controller Pixel Engine configuration Store #9 synchronizer) */
+#define IMXDPUV1_PIXENGCFG_STORE9_SHDLDREQ_CMD	53U
+
+/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #0 synchronizer) */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_SHDLDREQ_CMD	54U
+
+/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #4 synchronizer) */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_SHDLDREQ_CMD	55U
+
+/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #1 synchronizer) */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_SHDLDREQ_CMD	56U
+
+/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #5 synchronizer) */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_SHDLDREQ_CMD	57U
+
+/* Shadow load request (Blit Engine FetchDecode #9 tree) */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_SHDLDREQ_CMD	58U
+
+/* Shadow load request (Blit Engine FetchWarp #9 tree) */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_SHDLDREQ_CMD	59U
+
+/* Shadow load request (Blit Engine FetchEco #9 tree) */
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_SHDLDREQ_CMD	60U
+
+/* Shadow load request (Display Controller ConstFrame #0 tree) */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_SHDLDREQ_CMD	61U
+
+/* Shadow load request (Display Controller ConstFrame #4 tree) */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_SHDLDREQ_CMD	62U
+
+/* Shadow load request (Display Controller ConstFrame #1 tree) */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_SHDLDREQ_CMD	63U
+
+/* Shadow load request (Display Controller ConstFrame #5 tree) */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_SHDLDREQ_CMD	64U
+
+/* Shadow load request (Display Controller FetchWarp #2 tree) */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_SHDLDREQ_CMD	65U
+
+/* Shadow load request (Display Controller FetchEco #2 tree) */
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_SHDLDREQ_CMD	66U
+
+/* Shadow load request (Display Controller FetchDecode #0 tree) */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_SHDLDREQ_CMD	67U
+
+/* Shadow load request (Display Controller FetchEco #0 tree) */
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_SHDLDREQ_CMD	68U
+
+/* Shadow load request (Display Controller FetchDecode #1 tree) */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_SHDLDREQ_CMD	69U
+
+/* Shadow load request (Display Controller FetchEco #1 tree) */
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_SHDLDREQ_CMD	70U
+
+/* Shadow load request (Display Controller FetchLayer #0 tree) */
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_SHDLDREQ_CMD	71U
+
+/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 0) */
+#define IMXDPUV1_FETCHWARP9_SHDLDREQ0_CMD	72U
+
+/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 1) */
+#define IMXDPUV1_FETCHWARP9_SHDLDREQ1_CMD	73U
+
+/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 2) */
+#define IMXDPUV1_FETCHWARP9_SHDLDREQ2_CMD	74U
+
+/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 3) */
+#define IMXDPUV1_FETCHWARP9_SHDLDREQ3_CMD	75U
+
+/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 4) */
+#define IMXDPUV1_FETCHWARP9_SHDLDREQ4_CMD	76U
+
+/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 5) */
+#define IMXDPUV1_FETCHWARP9_SHDLDREQ5_CMD	77U
+
+/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 6) */
+#define IMXDPUV1_FETCHWARP9_SHDLDREQ6_CMD	78U
+
+/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 7) */
+#define IMXDPUV1_FETCHWARP9_SHDLDREQ7_CMD	79U
+
+/* Shadow load request (Display Controller FetchWarp #2 unit Layer 0) */
+#define IMXDPUV1_FETCHWARP2_SHDLDREQ0_CMD	80U
+
+/* Shadow load request (Display Controller FetchWarp #2 unit Layer 1) */
+#define IMXDPUV1_FETCHWARP2_SHDLDREQ1_CMD	81U
+
+/* Shadow load request (Display Controller FetchWarp #2 unit Layer 2) */
+#define IMXDPUV1_FETCHWARP2_SHDLDREQ2_CMD	82U
+
+/* Shadow load request (Display Controller FetchWarp #2 unit Layer 3) */
+#define IMXDPUV1_FETCHWARP2_SHDLDREQ3_CMD	83U
+
+/* Shadow load request (Display Controller FetchWarp #2 unit Layer 4) */
+#define IMXDPUV1_FETCHWARP2_SHDLDREQ4_CMD	84U
+
+/* Shadow load request (Display Controller FetchWarp #2 unit Layer 5) */
+#define IMXDPUV1_FETCHWARP2_SHDLDREQ5_CMD	85U
+
+/* Shadow load request (Display Controller FetchWarp #2 unit Layer 6) */
+#define IMXDPUV1_FETCHWARP2_SHDLDREQ6_CMD	86U
+
+/* Shadow load request (Display Controller FetchWarp #2 unit Layer 7) */
+#define IMXDPUV1_FETCHWARP2_SHDLDREQ7_CMD	87U
+
+/* Shadow load request (Display Controller FetchLayer #0 unit Layer 0) */
+#define IMXDPUV1_FETCHLAYER0_SHDLDREQ0_CMD	88U
+
+/* Shadow load request (Display Controller FetchLayer #0 unit Layer 1) */
+#define IMXDPUV1_FETCHLAYER0_SHDLDREQ1_CMD	89U
+
+/* Shadow load request (Display Controller FetchLayer #0 unit Layer 2) */
+#define IMXDPUV1_FETCHLAYER0_SHDLDREQ2_CMD	90U
+
+/* Shadow load request (Display Controller FetchLayer #0 unit Layer 3) */
+#define IMXDPUV1_FETCHLAYER0_SHDLDREQ3_CMD	91U
+
+/* Shadow load request (Display Controller FetchLayer #0 unit Layer 4) */
+#define IMXDPUV1_FETCHLAYER0_SHDLDREQ4_CMD	92U
+
+/* Shadow load request (Display Controller FetchLayer #0 unit Layer 5) */
+#define IMXDPUV1_FETCHLAYER0_SHDLDREQ5_CMD	93U
+
+/* Shadow load request (Display Controller FetchLayer #0 unit Layer 6) */
+#define IMXDPUV1_FETCHLAYER0_SHDLDREQ6_CMD	94U
+
+/* Shadow load request (Display Controller FetchLayer #0 unit Layer 7) */
+#define IMXDPUV1_FETCHLAYER0_SHDLDREQ7_CMD	95U
+
+
+#endif /* IMXDPUV1_EVENTS */
diff --git a/include/imxdpuv1_registers.h b/include/imxdpuv1_registers.h
new file mode 100644
index 00000000000..eb9676b0bbf
--- /dev/null
+++ b/include/imxdpuv1_registers.h
@@ -0,0 +1,22682 @@
+/*
+ * Copyright (c) 2005-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/* Instance: IMXDPU */
+
+#ifndef IMXDPUV1_REGISTERS_H
+#define IMXDPUV1_REGISTERS_H
+/* Register: IMXDPUV1_comctrl_IPIdentifier */
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER                        ((uint32_t)(0))
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_OFFSET                 ((uint32_t)(0))
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_RESET_VALUE            0x21340400U
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNDELIVERYID_MASK  0xF0U
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNDELIVERYID_SHIFT 4U
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL_MASK 0xF00U
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL_SHIFT 8U
+/* Field Value: DESIGNMATURITYLEVEL__PREFS, Pre feasibility study.  */
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__PREFS 0x1U
+/* Field Value: DESIGNMATURITYLEVEL__FS, Feasibility study.  */
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__FS 0x2U
+/* Field Value: DESIGNMATURITYLEVEL__R0, Functionality complete.  */
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__R0 0x3U
+/* Field Value: DESIGNMATURITYLEVEL__R1, Verification complete.  */
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__R1 0x4U
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPEVOLUTION_MASK       0xF000U
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPEVOLUTION_SHIFT      12U
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET_MASK      0xF0000U
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET_SHIFT     16U
+/* Field Value: IPFEATURESET__E, Minimal functionality (Eco).  */
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__E        0x1U
+/* Field Value: IPFEATURESET__L, Reduced functionality (Light).  */
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__L        0x2U
+/* Field Value: IPFEATURESET__P, Advanced functionality (Plus).  */
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__P        0x4U
+/* Field Value: IPFEATURESET__X, Extensive functionality (eXtensive).  */
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__X        0x5U
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION_MASK     0xF00000U
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION_SHIFT    20U
+/* Field Value: IPAPPLICATION__B, Blit Engine only.  */
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__B       0x1U
+/* Field Value: IPAPPLICATION__D, Blit Engine and Display Controller.  */
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__D       0x2U
+/* Field Value: IPAPPLICATION__V, Display Controller only (with direct capture).  */
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__V       0x3U
+/* Field Value: IPAPPLICATION__G, Blit Engine, Display Controller (with direct
+ * capture), Capture Controller (buffered capture) and Drawing Engine.  */
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__G       0x4U
+/* Field Value: IPAPPLICATION__C, Display Controller only.  */
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__C       0x5U
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION_MASK   0xF000000U
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION_SHIFT  24U
+/* Field Value: IPCONFIGURATION__M, Graphics core only (Module).  */
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION__M     0x1U
+/* Field Value: IPCONFIGURATION__S, Subsystem including a graphics core (System).  */
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION__S     0x2U
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY_MASK          0xF0000000U
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY_SHIFT         28U
+/* Field Value: IPFAMILY__IMXDPU2010, IMXDPU building block generation 2010.  */
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY__IMXDPU2010   0U
+/* Field Value: IPFAMILY__IMXDPU2012, IMXDPU building block generation 2012.  */
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY__IMXDPU2012   0x1U
+/* Field Value: IPFAMILY__IMXDPU2013, IMXDPU building block generation 2013.  */
+#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY__IMXDPU2013   0x2U
+
+/* Register: IMXDPUV1_comctrl_LockUnlock */
+#define IMXDPUV1_COMCTRL_LOCKUNLOCK                          ((uint32_t)(0x40))
+#define IMXDPUV1_COMCTRL_LOCKUNLOCK_OFFSET                   ((uint32_t)(0x40))
+#define IMXDPUV1_COMCTRL_LOCKUNLOCK_RESET_VALUE              0U
+#define IMXDPUV1_COMCTRL_LOCKUNLOCK_RESET_MASK               0U
+#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK_MASK          0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK_SHIFT         0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY     0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY   0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY   0xFBE8B1E6U
+
+/* Register: IMXDPUV1_comctrl_LockStatus */
+#define IMXDPUV1_COMCTRL_LOCKSTATUS                          ((uint32_t)(0x44))
+#define IMXDPUV1_COMCTRL_LOCKSTATUS_OFFSET                   ((uint32_t)(0x44))
+#define IMXDPUV1_COMCTRL_LOCKSTATUS_RESET_VALUE              0U
+#define IMXDPUV1_COMCTRL_LOCKSTATUS_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_LOCKSTATUS_LOCKSTATUS_MASK          0x1U
+#define IMXDPUV1_COMCTRL_LOCKSTATUS_LOCKSTATUS_SHIFT         0U
+#define IMXDPUV1_COMCTRL_LOCKSTATUS_PRIVILEGESTATUS_MASK     0x10U
+#define IMXDPUV1_COMCTRL_LOCKSTATUS_PRIVILEGESTATUS_SHIFT    4U
+#define IMXDPUV1_COMCTRL_LOCKSTATUS_FREEZESTATUS_MASK        0x100U
+#define IMXDPUV1_COMCTRL_LOCKSTATUS_FREEZESTATUS_SHIFT       8U
+
+/* Register: IMXDPUV1_comctrl_UserInterruptMask0 */
+#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0                  ((uint32_t)(0x48))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_OFFSET           ((uint32_t)(0x48))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_RESET_VALUE      0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_USERINTERRUPTMASK0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_USERINTERRUPTMASK0_SHIFT 0U
+
+/* Register: IMXDPUV1_comctrl_UserInterruptMask1 */
+#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1                  ((uint32_t)(0x4C))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_OFFSET           ((uint32_t)(0x4C))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_RESET_VALUE      0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_USERINTERRUPTMASK1_MASK 0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_USERINTERRUPTMASK1_SHIFT 0U
+
+/* Register: IMXDPUV1_comctrl_InterruptEnable0 */
+#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0                    ((uint32_t)(0x50))
+#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_OFFSET             ((uint32_t)(0x50))
+#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_RESET_VALUE        0U
+#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_INTERRUPTENABLE0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_INTERRUPTENABLE0_SHIFT 0U
+
+/* Register: IMXDPUV1_comctrl_InterruptEnable1 */
+#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1                    ((uint32_t)(0x54))
+#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_OFFSET             ((uint32_t)(0x54))
+#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_RESET_VALUE        0U
+#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_INTERRUPTENABLE1_MASK 0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_INTERRUPTENABLE1_SHIFT 0U
+
+/* Register: IMXDPUV1_comctrl_InterruptPreset0 */
+#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0                    ((uint32_t)(0x58))
+#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_OFFSET             ((uint32_t)(0x58))
+#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_RESET_VALUE        0U
+#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_RESET_MASK         0U
+#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_INTERRUPTPRESET0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_INTERRUPTPRESET0_SHIFT 0U
+
+/* Register: IMXDPUV1_comctrl_InterruptPreset1 */
+#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1                    ((uint32_t)(0x5C))
+#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_OFFSET             ((uint32_t)(0x5C))
+#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_RESET_VALUE        0U
+#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_RESET_MASK         0U
+#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_INTERRUPTPRESET1_MASK 0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_INTERRUPTPRESET1_SHIFT 0U
+
+/* Register: IMXDPUV1_comctrl_InterruptClear0 */
+#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0                     ((uint32_t)(0x60))
+#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_OFFSET              ((uint32_t)(0x60))
+#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_RESET_VALUE         0U
+#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_RESET_MASK          0U
+#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_INTERRUPTCLEAR0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_INTERRUPTCLEAR0_SHIFT 0U
+
+/* Register: IMXDPUV1_comctrl_InterruptClear1 */
+#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1                     ((uint32_t)(0x64))
+#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_OFFSET              ((uint32_t)(0x64))
+#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_RESET_VALUE         0U
+#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_RESET_MASK          0U
+#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_INTERRUPTCLEAR1_MASK 0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_INTERRUPTCLEAR1_SHIFT 0U
+
+/* Register: IMXDPUV1_comctrl_InterruptStatus0 */
+#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0                    ((uint32_t)(0x68))
+#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_OFFSET             ((uint32_t)(0x68))
+#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_RESET_VALUE        0U
+#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_RESET_MASK         0U
+#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_INTERRUPTSTATUS0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_INTERRUPTSTATUS0_SHIFT 0U
+
+/* Register: IMXDPUV1_comctrl_InterruptStatus1 */
+#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1                    ((uint32_t)(0x6C))
+#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_OFFSET             ((uint32_t)(0x6C))
+#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_RESET_VALUE        0U
+#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_RESET_MASK         0U
+#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_INTERRUPTSTATUS1_MASK 0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_INTERRUPTSTATUS1_SHIFT 0U
+
+/* Register: IMXDPUV1_comctrl_UserInterruptEnable0 */
+#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0                ((uint32_t)(0x80))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_OFFSET         ((uint32_t)(0x80))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_RESET_VALUE    0U
+#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_USERINTERRUPTENABLE0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_USERINTERRUPTENABLE0_SHIFT 0U
+
+/* Register: IMXDPUV1_comctrl_UserInterruptEnable1 */
+#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1                ((uint32_t)(0x84))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_OFFSET         ((uint32_t)(0x84))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_RESET_VALUE    0U
+#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_USERINTERRUPTENABLE1_MASK 0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_USERINTERRUPTENABLE1_SHIFT 0U
+
+/* Register: IMXDPUV1_comctrl_UserInterruptPreset0 */
+#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0                ((uint32_t)(0x88))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_OFFSET         ((uint32_t)(0x88))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_RESET_VALUE    0U
+#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_RESET_MASK     0U
+#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_USERINTERRUPTPRESET0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_USERINTERRUPTPRESET0_SHIFT 0U
+
+/* Register: IMXDPUV1_comctrl_UserInterruptPreset1 */
+#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1                ((uint32_t)(0x8C))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_OFFSET         ((uint32_t)(0x8C))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_RESET_VALUE    0U
+#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_RESET_MASK     0U
+#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_USERINTERRUPTPRESET1_MASK 0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_USERINTERRUPTPRESET1_SHIFT 0U
+
+/* Register: IMXDPUV1_comctrl_UserInterruptClear0 */
+#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0                 ((uint32_t)(0x90))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_OFFSET          ((uint32_t)(0x90))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_RESET_VALUE     0U
+#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_RESET_MASK      0U
+#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_USERINTERRUPTCLEAR0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_USERINTERRUPTCLEAR0_SHIFT 0U
+
+/* Register: IMXDPUV1_comctrl_UserInterruptClear1 */
+#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1                 ((uint32_t)(0x94))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_OFFSET          ((uint32_t)(0x94))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_RESET_VALUE     0U
+#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_RESET_MASK      0U
+#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_USERINTERRUPTCLEAR1_MASK 0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_USERINTERRUPTCLEAR1_SHIFT 0U
+
+/* Register: IMXDPUV1_comctrl_UserInterruptStatus0 */
+#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0                ((uint32_t)(0x98))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_OFFSET         ((uint32_t)(0x98))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_RESET_VALUE    0U
+#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_RESET_MASK     0U
+#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_USERINTERRUPTSTATUS0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_USERINTERRUPTSTATUS0_SHIFT 0U
+
+/* Register: IMXDPUV1_comctrl_UserInterruptStatus1 */
+#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1                ((uint32_t)(0xA8))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_OFFSET         ((uint32_t)(0xA8))
+#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_RESET_VALUE    0U
+#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_RESET_MASK     0U
+#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_USERINTERRUPTSTATUS1_MASK 0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_USERINTERRUPTSTATUS1_SHIFT 0U
+
+/* Register: IMXDPUV1_comctrl_GeneralPurpose */
+#define IMXDPUV1_COMCTRL_GENERALPURPOSE                      ((uint32_t)(0x100))
+#define IMXDPUV1_COMCTRL_GENERALPURPOSE_OFFSET               ((uint32_t)(0x100))
+#define IMXDPUV1_COMCTRL_GENERALPURPOSE_RESET_VALUE          0U
+#define IMXDPUV1_COMCTRL_GENERALPURPOSE_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_GENERALPURPOSE_GENERALPURPOSE_MASK  0xFFFFFFFFU
+#define IMXDPUV1_COMCTRL_GENERALPURPOSE_GENERALPURPOSE_SHIFT 0U
+
+/* Register: IMXDPUV1_cmdseq_HIF */
+#define IMXDPUV1_CMDSEQ_HIF                                  ((uint32_t)(0x400))
+#define IMXDPUV1_CMDSEQ_HIF_OFFSET                           ((uint32_t)(0))
+#define IMXDPUV1_CMDSEQ_HIF_RESET_VALUE                      0U
+#define IMXDPUV1_CMDSEQ_HIF_RESET_MASK                       0U
+#define IMXDPUV1_CMDSEQ_HIF_COMMANDFIFO_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_CMDSEQ_HIF_COMMANDFIFO_SHIFT                0U
+
+/* Register: IMXDPUV1_cmdseq_LockUnlockHIF */
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF                        ((uint32_t)(0x500))
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_OFFSET                 ((uint32_t)(0x100))
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_RESET_VALUE            0U
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_RESET_MASK             0U
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF_MASK     0xFFFFFFFFU
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF_SHIFT    0U
+/* Field Value: LOCKUNLOCKHIF__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter
+ * value is 1.  */
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__LOCK_KEY 0x5651F763U
+/* Field Value: LOCKUNLOCKHIF__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCKHIF__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCKHIF__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCKHIF__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_cmdseq_LockStatusHIF */
+#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF                        ((uint32_t)(0x504))
+#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_OFFSET                 ((uint32_t)(0x104))
+#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_RESET_VALUE            0U
+#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_LOCKSTATUSHIF_MASK     0x1U
+#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_LOCKSTATUSHIF_SHIFT    0U
+#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_PRIVILEGESTATUSHIF_MASK 0x10U
+#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_PRIVILEGESTATUSHIF_SHIFT 4U
+#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_FREEZESTATUSHIF_MASK   0x100U
+#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_FREEZESTATUSHIF_SHIFT  8U
+
+/* Register: IMXDPUV1_cmdseq_LockUnlock */
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCK                           ((uint32_t)(0x580))
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_OFFSET                    ((uint32_t)(0x180))
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_RESET_VALUE               0U
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_RESET_MASK                0U
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK_MASK           0xFFFFFFFFU
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK_SHIFT          0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY      0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY    0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY    0xFBE8B1E6U
+
+/* Register: IMXDPUV1_cmdseq_LockStatus */
+#define IMXDPUV1_CMDSEQ_LOCKSTATUS                           ((uint32_t)(0x584))
+#define IMXDPUV1_CMDSEQ_LOCKSTATUS_OFFSET                    ((uint32_t)(0x184))
+#define IMXDPUV1_CMDSEQ_LOCKSTATUS_RESET_VALUE               0U
+#define IMXDPUV1_CMDSEQ_LOCKSTATUS_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_CMDSEQ_LOCKSTATUS_LOCKSTATUS_MASK           0x1U
+#define IMXDPUV1_CMDSEQ_LOCKSTATUS_LOCKSTATUS_SHIFT          0U
+#define IMXDPUV1_CMDSEQ_LOCKSTATUS_PRIVILEGESTATUS_MASK      0x10U
+#define IMXDPUV1_CMDSEQ_LOCKSTATUS_PRIVILEGESTATUS_SHIFT     4U
+#define IMXDPUV1_CMDSEQ_LOCKSTATUS_FREEZESTATUS_MASK         0x100U
+#define IMXDPUV1_CMDSEQ_LOCKSTATUS_FREEZESTATUS_SHIFT        8U
+
+/* Register: IMXDPUV1_cmdseq_BufferAddress */
+#define IMXDPUV1_CMDSEQ_BUFFERADDRESS                        ((uint32_t)(0x588))
+#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_OFFSET                 ((uint32_t)(0x188))
+#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_RESET_VALUE            0U
+#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_LOCAL_MASK             0x1U
+#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_LOCAL_SHIFT            0U
+#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_ADDR_MASK              0xFFFFFFE0U
+#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_ADDR_SHIFT             5U
+
+/* Register: IMXDPUV1_cmdseq_BufferSize */
+#define IMXDPUV1_CMDSEQ_BUFFERSIZE                           ((uint32_t)(0x58C))
+#define IMXDPUV1_CMDSEQ_BUFFERSIZE_OFFSET                    ((uint32_t)(0x18C))
+#define IMXDPUV1_CMDSEQ_BUFFERSIZE_RESET_VALUE               0x80U
+#define IMXDPUV1_CMDSEQ_BUFFERSIZE_RESET_MASK                0xFFF8U
+#define IMXDPUV1_CMDSEQ_BUFFERSIZE_SIZE_MASK                 0xFFF8U
+#define IMXDPUV1_CMDSEQ_BUFFERSIZE_SIZE_SHIFT                3U
+
+/* Register: IMXDPUV1_cmdseq_WatermarkControl */
+#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL                     ((uint32_t)(0x590))
+#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_OFFSET              ((uint32_t)(0x190))
+#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_RESET_VALUE         0x600020U
+#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_LOWWM_MASK          0xFFFFU
+#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_LOWWM_SHIFT         0U
+#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_HIGHWM_MASK         0xFFFF0000U
+#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_HIGHWM_SHIFT        16U
+
+/* Register: IMXDPUV1_cmdseq_Control */
+#define IMXDPUV1_CMDSEQ_CONTROL                              ((uint32_t)(0x594))
+#define IMXDPUV1_CMDSEQ_CONTROL_OFFSET                       ((uint32_t)(0x194))
+#define IMXDPUV1_CMDSEQ_CONTROL_RESET_VALUE                  0U
+#define IMXDPUV1_CMDSEQ_CONTROL_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_CMDSEQ_CONTROL_CLRAXIW_MASK                 0x1U
+#define IMXDPUV1_CMDSEQ_CONTROL_CLRAXIW_SHIFT                0U
+#define IMXDPUV1_CMDSEQ_CONTROL_CLRRBUF_MASK                 0x4U
+#define IMXDPUV1_CMDSEQ_CONTROL_CLRRBUF_SHIFT                2U
+#define IMXDPUV1_CMDSEQ_CONTROL_CLRCMDBUF_MASK               0x8U
+#define IMXDPUV1_CMDSEQ_CONTROL_CLRCMDBUF_SHIFT              3U
+#define IMXDPUV1_CMDSEQ_CONTROL_CLEAR_MASK                   0x80000000U
+#define IMXDPUV1_CMDSEQ_CONTROL_CLEAR_SHIFT                  31U
+
+/* Register: IMXDPUV1_cmdseq_Status */
+#define IMXDPUV1_CMDSEQ_STATUS                               ((uint32_t)(0x598))
+#define IMXDPUV1_CMDSEQ_STATUS_OFFSET                        ((uint32_t)(0x198))
+#define IMXDPUV1_CMDSEQ_STATUS_RESET_VALUE                   0x41000080U
+#define IMXDPUV1_CMDSEQ_STATUS_RESET_MASK                    0xFFFFFFFFU
+#define IMXDPUV1_CMDSEQ_STATUS_FIFOSPACE_MASK                0x1FFFFU
+#define IMXDPUV1_CMDSEQ_STATUS_FIFOSPACE_SHIFT               0U
+#define IMXDPUV1_CMDSEQ_STATUS_FIFOEMPTY_MASK                0x1000000U
+#define IMXDPUV1_CMDSEQ_STATUS_FIFOEMPTY_SHIFT               24U
+#define IMXDPUV1_CMDSEQ_STATUS_FIFOFULL_MASK                 0x2000000U
+#define IMXDPUV1_CMDSEQ_STATUS_FIFOFULL_SHIFT                25U
+#define IMXDPUV1_CMDSEQ_STATUS_FIFOWMSTATE_MASK              0x4000000U
+#define IMXDPUV1_CMDSEQ_STATUS_FIFOWMSTATE_SHIFT             26U
+#define IMXDPUV1_CMDSEQ_STATUS_WATCHDOG_MASK                 0x8000000U
+#define IMXDPUV1_CMDSEQ_STATUS_WATCHDOG_SHIFT                27U
+#define IMXDPUV1_CMDSEQ_STATUS_READBUSY_MASK                 0x10000000U
+#define IMXDPUV1_CMDSEQ_STATUS_READBUSY_SHIFT                28U
+#define IMXDPUV1_CMDSEQ_STATUS_WRITEBUSY_MASK                0x20000000U
+#define IMXDPUV1_CMDSEQ_STATUS_WRITEBUSY_SHIFT               29U
+#define IMXDPUV1_CMDSEQ_STATUS_IDLE_MASK                     0x40000000U
+#define IMXDPUV1_CMDSEQ_STATUS_IDLE_SHIFT                    30U
+#define IMXDPUV1_CMDSEQ_STATUS_ERRORHALT_MASK                0x80000000U
+#define IMXDPUV1_CMDSEQ_STATUS_ERRORHALT_SHIFT               31U
+
+/* Register: IMXDPUV1_cmdseq_PrefetchWindowStart */
+#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART                  ((uint32_t)(0x59C))
+#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_OFFSET           ((uint32_t)(0x19C))
+#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_RESET_VALUE      0U
+#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_RESET_MASK       0xFFFFFFFCU
+#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_PWSTART_MASK     0xFFFFFFFCU
+#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_PWSTART_SHIFT    2U
+
+/* Register: IMXDPUV1_cmdseq_PrefetchWindowEnd */
+#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND                    ((uint32_t)(0x5A0))
+#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_OFFSET             ((uint32_t)(0x1A0))
+#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_RESET_VALUE        0xFFFFFFFCU
+#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_RESET_MASK         0xFFFFFFFCU
+#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_PWEND_MASK         0xFFFFFFFCU
+#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_PWEND_SHIFT        2U
+
+/* Register: IMXDPUV1_pixengcfg_SafetyLockUnlock */
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK                  ((uint32_t)(0x800))
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_OFFSET           ((uint32_t)(0))
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_RESET_VALUE      0U
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_RESET_MASK       0U
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK_SHIFT 0U
+/* Field Value: SAFETYLOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset counter
+ * value is 1.  */
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: SAFETYLOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: SAFETYLOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: SAFETYLOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: SAFETYLOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_SafetyLockStatus */
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS                  ((uint32_t)(0x804))
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_OFFSET           ((uint32_t)(0x4))
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_RESET_VALUE      0U
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYLOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYLOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYPRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYPRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYFREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYFREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_store9_SafetyMask */
+#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK                 ((uint32_t)(0x808))
+#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_OFFSET          ((uint32_t)(0x8))
+#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_RESET_VALUE     0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_STORE9_SAFETYMASK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_STORE9_SAFETYMASK_SHIFT 0U
+
+/* Register: IMXDPUV1_pixengcfg_extdst0_SafetyMask */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK                ((uint32_t)(0x80C))
+#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_OFFSET         ((uint32_t)(0xC))
+#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_RESET_VALUE    0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_EXTDST0_SAFETYMASK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_EXTDST0_SAFETYMASK_SHIFT 0U
+
+/* Register: IMXDPUV1_pixengcfg_extdst4_SafetyMask */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK                ((uint32_t)(0x810))
+#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_OFFSET         ((uint32_t)(0x10))
+#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_RESET_VALUE    0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_EXTDST4_SAFETYMASK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_EXTDST4_SAFETYMASK_SHIFT 0U
+
+/* Register: IMXDPUV1_pixengcfg_extdst1_SafetyMask_0 */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0              ((uint32_t)(0x814))
+#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_OFFSET       ((uint32_t)(0x14))
+#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_RESET_VALUE  0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_EXTDST1_SAFETYMASK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_EXTDST1_SAFETYMASK_SHIFT 0U
+
+/* Register: IMXDPUV1_pixengcfg_extdst5_SafetyMask */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK                ((uint32_t)(0x818))
+#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_OFFSET         ((uint32_t)(0x18))
+#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_RESET_VALUE    0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_EXTDST5_SAFETYMASK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_EXTDST5_SAFETYMASK_SHIFT 0U
+
+/* Register: IMXDPUV1_pixengcfg_fetchdecode9_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK           ((uint32_t)(0x820))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_OFFSET    ((uint32_t)(0x20))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_RESET_MASK 0U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK_SHIFT 0U
+/* Field Value: FETCHDECODE9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset
+ * counter value is 1.  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: FETCHDECODE9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock
+ * counter. Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: FETCHDECODE9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege
+ * protection. Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: FETCHDECODE9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege
+ * protection.  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: FETCHDECODE9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_fetchdecode9_LockStatus */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS           ((uint32_t)(0x824))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_OFFSET    ((uint32_t)(0x24))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_fetchdecode9_Dynamic */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC              ((uint32_t)(0x828))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_OFFSET       ((uint32_t)(0x28))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_RESET_VALUE  0U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL_SHIFT 0U
+/* Field Value: FETCHDECODE9_SRC_SEL__DISABLE, Unit fetchdecode9 input port
+ * src is disabled  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL__DISABLE 0U
+/* Field Value: FETCHDECODE9_SRC_SEL__FETCHECO9, Unit fetchdecode9 input port
+ * src is connected to output of unit fetcheco9  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL__FETCHECO9 0x3U
+/* Field Value: FETCHDECODE9_SRC_SEL__FETCHPERSP9, Unit fetchdecode9 input
+ * port src is connected to output of unit fetchpersp9  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL__FETCHPERSP9 0x2U
+
+/* Register: IMXDPUV1_pixengcfg_fetchdecode9_Status */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS               ((uint32_t)(0x82C))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_OFFSET        ((uint32_t)(0x2C))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_RESET_VALUE   0U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_RESET_MASK    0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL_SHIFT 16U
+/* Field Value: FETCHDECODE9_SEL__STORE9, fetchdecode9 module is used from
+ * store9 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__STORE9 0x1U
+/* Field Value: FETCHDECODE9_SEL__EXTDST0, fetchdecode9 module is used from
+ * extdst0 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST0 0x2U
+/* Field Value: FETCHDECODE9_SEL__EXTDST4, fetchdecode9 module is used from
+ * extdst4 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST4 0x3U
+/* Field Value: FETCHDECODE9_SEL__EXTDST1, fetchdecode9 module is used from
+ * extdst1 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST1 0x4U
+/* Field Value: FETCHDECODE9_SEL__EXTDST5, fetchdecode9 module is used from
+ * extdst5 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST5 0x5U
+/* Field Value: FETCHDECODE9_SEL__STORE4, fetchdecode9 module is used from
+ * store4 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__STORE4 0x6U
+/* Field Value: FETCHDECODE9_SEL__STORE5, fetchdecode9 module is used from
+ * store5 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__STORE5 0x7U
+/* Field Value: FETCHDECODE9_SEL__DISABLE, fetchdecode9 module is not used  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_fetchwarp9_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK             ((uint32_t)(0x840))
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_OFFSET      ((uint32_t)(0x40))
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_RESET_MASK  0U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK_SHIFT 0U
+/* Field Value: FETCHWARP9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset
+ * counter value is 1.  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: FETCHWARP9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: FETCHWARP9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: FETCHWARP9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege
+ * protection.  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: FETCHWARP9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_fetchwarp9_LockStatus */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS             ((uint32_t)(0x844))
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_OFFSET      ((uint32_t)(0x44))
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_fetchwarp9_Dynamic */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC                ((uint32_t)(0x848))
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_OFFSET         ((uint32_t)(0x48))
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL_SHIFT 0U
+/* Field Value: FETCHWARP9_SRC_SEL__DISABLE, Unit fetchpersp9 input port src
+ * is disabled  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL__DISABLE 0U
+/* Field Value: FETCHWARP9_SRC_SEL__FETCHECO9, Unit fetchpersp9 input port
+ * src is connected to output of unit fetcheco9  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL__FETCHECO9 0x3U
+
+/* Register: IMXDPUV1_pixengcfg_fetchwarp9_Status */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS                 ((uint32_t)(0x84C))
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_OFFSET          ((uint32_t)(0x4C))
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_RESET_VALUE     0U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_RESET_MASK      0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL_SHIFT 16U
+/* Field Value: FETCHWARP9_SEL__STORE9, fetchpersp9 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__STORE9 0x1U
+/* Field Value: FETCHWARP9_SEL__EXTDST0, fetchpersp9 module is used from extdst0
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST0 0x2U
+/* Field Value: FETCHWARP9_SEL__EXTDST4, fetchpersp9 module is used from extdst4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST4 0x3U
+/* Field Value: FETCHWARP9_SEL__EXTDST1, fetchpersp9 module is used from extdst1
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST1 0x4U
+/* Field Value: FETCHWARP9_SEL__EXTDST5, fetchpersp9 module is used from extdst5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST5 0x5U
+/* Field Value: FETCHWARP9_SEL__STORE4, fetchpersp9 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__STORE4 0x6U
+/* Field Value: FETCHWARP9_SEL__STORE5, fetchpersp9 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__STORE5 0x7U
+/* Field Value: FETCHWARP9_SEL__DISABLE, fetchpersp9 module is not used  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_fetcheco9_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK              ((uint32_t)(0x850))
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_OFFSET       ((uint32_t)(0x50))
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_RESET_VALUE  0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_RESET_MASK   0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK_SHIFT 0U
+/* Field Value: FETCHECO9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset
+ * counter value is 1.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: FETCHECO9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: FETCHECO9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: FETCHECO9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege
+ * protection.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: FETCHECO9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_fetcheco9_LockStatus */
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS              ((uint32_t)(0x854))
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_OFFSET       ((uint32_t)(0x54))
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_RESET_VALUE  0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_fetcheco9_Status */
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS                  ((uint32_t)(0x858))
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_OFFSET           ((uint32_t)(0x58))
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_RESET_VALUE      0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_RESET_MASK       0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL_SHIFT 16U
+/* Field Value: FETCHECO9_SEL__STORE9, fetcheco9 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__STORE9 0x1U
+/* Field Value: FETCHECO9_SEL__EXTDST0, fetcheco9 module is used from extdst0
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST0 0x2U
+/* Field Value: FETCHECO9_SEL__EXTDST4, fetcheco9 module is used from extdst4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST4 0x3U
+/* Field Value: FETCHECO9_SEL__EXTDST1, fetcheco9 module is used from extdst1
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST1 0x4U
+/* Field Value: FETCHECO9_SEL__EXTDST5, fetcheco9 module is used from extdst5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST5 0x5U
+/* Field Value: FETCHECO9_SEL__STORE4, fetcheco9 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__STORE4 0x6U
+/* Field Value: FETCHECO9_SEL__STORE5, fetcheco9 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__STORE5 0x7U
+/* Field Value: FETCHECO9_SEL__DISABLE, fetcheco9 module is not used  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_rop9_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK                   ((uint32_t)(0x860))
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_OFFSET            ((uint32_t)(0x60))
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_RESET_VALUE       0U
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_RESET_MASK        0U
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK_SHIFT 0U
+/* Field Value: ROP9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset counter
+ * value is 1.  */
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: ROP9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: ROP9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: ROP9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: ROP9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_rop9_LockStatus */
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS                   ((uint32_t)(0x864))
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_OFFSET            ((uint32_t)(0x64))
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_RESET_VALUE       0U
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_rop9_Dynamic */
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC                      ((uint32_t)(0x868))
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_OFFSET               ((uint32_t)(0x68))
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_RESET_VALUE          0x1000000U
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL_MASK   0x3FU
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL_SHIFT  0U
+/* Field Value: ROP9_PRIM_SEL__DISABLE, Unit rop9 input port prim is disabled  */
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL__DISABLE 0U
+/* Field Value: ROP9_PRIM_SEL__FETCHDECODE9, Unit rop9 input port prim is
+ * connected to output of unit fetchdecode9  */
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL__FETCHDECODE9 0x1U
+/* Field Value: ROP9_PRIM_SEL__FETCHPERSP9, Unit rop9 input port prim is connected
+ * to output of unit fetchpersp9  */
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL__FETCHPERSP9 0x2U
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL_MASK    0x3F00U
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL_SHIFT   8U
+/* Field Value: ROP9_SEC_SEL__DISABLE, Unit rop9 input port sec is disabled  */
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL__DISABLE 0U
+/* Field Value: ROP9_SEC_SEL__FETCHECO9, Unit rop9 input port sec is connected
+ * to output of unit fetcheco9  */
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL__FETCHECO9 0x3U
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL_MASK   0x3F0000U
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL_SHIFT  16U
+/* Field Value: ROP9_TERT_SEL__DISABLE, Unit rop9 input port tert is disabled  */
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL__DISABLE 0U
+/* Field Value: ROP9_TERT_SEL__FETCHDECODE9, Unit rop9 input port tert is
+ * connected to output of unit fetchdecode9  */
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL__FETCHDECODE9 0x1U
+/* Field Value: ROP9_TERT_SEL__FETCHPERSP9, Unit rop9 input port tert is connected
+ * to output of unit fetchpersp9  */
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL__FETCHPERSP9 0x2U
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN_MASK      0x3000000U
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN_SHIFT     24U
+/* Field Value: ROP9_CLKEN__DISABLE, Clock for rop9 is disabled  */
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN__DISABLE  0U
+/* Field Value: ROP9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, frequency
+ * is defined by the register setting for this pipeline (see [endpoint_name]_Static
+ * register)  */
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN__AUTOMATIC 0x1U
+/* Field Value: ROP9_CLKEN__FULL, Clock for rop9 is without gating  */
+#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN__FULL     0x3U
+
+/* Register: IMXDPUV1_pixengcfg_rop9_Status */
+#define IMXDPUV1_PIXENGCFG_ROP9_STATUS                       ((uint32_t)(0x86C))
+#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_OFFSET                ((uint32_t)(0x6C))
+#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_RESET_VALUE           0U
+#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_RESET_MASK            0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL_MASK         0x70000U
+#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL_SHIFT        16U
+/* Field Value: ROP9_SEL__STORE9, rop9 module is used from store9 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__STORE9      0x1U
+/* Field Value: ROP9_SEL__EXTDST0, rop9 module is used from extdst0 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST0     0x2U
+/* Field Value: ROP9_SEL__EXTDST4, rop9 module is used from extdst4 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST4     0x3U
+/* Field Value: ROP9_SEL__EXTDST1, rop9 module is used from extdst1 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST1     0x4U
+/* Field Value: ROP9_SEL__EXTDST5, rop9 module is used from extdst5 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST5     0x5U
+/* Field Value: ROP9_SEL__STORE4, rop9 module is used from store4 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__STORE4      0x6U
+/* Field Value: ROP9_SEL__STORE5, rop9 module is used from store5 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__STORE5      0x7U
+/* Field Value: ROP9_SEL__DISABLE, rop9 module is not used  */
+#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__DISABLE     0U
+
+/* Register: IMXDPUV1_pixengcfg_clut9_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK                  ((uint32_t)(0x880))
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_OFFSET           ((uint32_t)(0x80))
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_RESET_VALUE      0U
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_RESET_MASK       0U
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK_SHIFT 0U
+/* Field Value: CLUT9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset counter
+ * value is 1.  */
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: CLUT9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: CLUT9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: CLUT9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: CLUT9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_clut9_LockStatus */
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS                  ((uint32_t)(0x884))
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_OFFSET           ((uint32_t)(0x84))
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_RESET_VALUE      0U
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_clut9_Dynamic */
+#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC                     ((uint32_t)(0x888))
+#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_OFFSET              ((uint32_t)(0x88))
+#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_RESET_VALUE         0U
+#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL_MASK  0x3FU
+#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL_SHIFT 0U
+/* Field Value: CLUT9_SRC_SEL__DISABLE, Unit clut9 input port src is disabled  */
+#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL__DISABLE 0U
+/* Field Value: CLUT9_SRC_SEL__BLITBLEND9, Unit clut9 input port src is connected
+ * to output of unit blitblend9  */
+#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL__BLITBLEND9 0xAU
+/* Field Value: CLUT9_SRC_SEL__ROP9, Unit clut9 input port src is connected
+ * to output of unit rop9  */
+#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL__ROP9 0x4U
+
+/* Register: IMXDPUV1_pixengcfg_clut9_Status */
+#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS                      ((uint32_t)(0x88C))
+#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_OFFSET               ((uint32_t)(0x8C))
+#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_RESET_VALUE          0U
+#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_RESET_MASK           0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL_MASK       0x70000U
+#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL_SHIFT      16U
+/* Field Value: CLUT9_SEL__STORE9, clut9 module is used from store9 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__STORE9    0x1U
+/* Field Value: CLUT9_SEL__EXTDST0, clut9 module is used from extdst0 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST0   0x2U
+/* Field Value: CLUT9_SEL__EXTDST4, clut9 module is used from extdst4 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST4   0x3U
+/* Field Value: CLUT9_SEL__EXTDST1, clut9 module is used from extdst1 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST1   0x4U
+/* Field Value: CLUT9_SEL__EXTDST5, clut9 module is used from extdst5 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST5   0x5U
+/* Field Value: CLUT9_SEL__STORE4, clut9 module is used from store4 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__STORE4    0x6U
+/* Field Value: CLUT9_SEL__STORE5, clut9 module is used from store5 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__STORE5    0x7U
+/* Field Value: CLUT9_SEL__DISABLE, clut9 module is not used  */
+#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__DISABLE   0U
+
+/* Register: IMXDPUV1_pixengcfg_matrix9_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK                ((uint32_t)(0x8A0))
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_OFFSET         ((uint32_t)(0xA0))
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_RESET_MASK     0U
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK_SHIFT 0U
+/* Field Value: MATRIX9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset counter
+ * value is 1.  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: MATRIX9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: MATRIX9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: MATRIX9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: MATRIX9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_matrix9_LockStatus */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS                ((uint32_t)(0x8A4))
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_OFFSET         ((uint32_t)(0xA4))
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_matrix9_Dynamic */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC                   ((uint32_t)(0x8A8))
+#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_OFFSET            ((uint32_t)(0xA8))
+#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_RESET_VALUE       0x1000000U
+#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL_SHIFT 0U
+/* Field Value: MATRIX9_SRC_SEL__DISABLE, Unit matrix9 input port src is disabled  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__DISABLE 0U
+/* Field Value: MATRIX9_SRC_SEL__CLUT9, Unit matrix9 input port src is connected
+ * to output of unit clut9  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__CLUT9 0x5U
+/* Field Value: MATRIX9_SRC_SEL__BLITBLEND9, Unit matrix9 input port src is
+ * connected to output of unit blitblend9  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__BLITBLEND9 0xAU
+/* Field Value: MATRIX9_SRC_SEL__ROP9, Unit matrix9 input port src is connected
+ * to output of unit rop9  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__ROP9 0x4U
+#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN_MASK 0x3000000U
+#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN_SHIFT 24U
+/* Field Value: MATRIX9_CLKEN__DISABLE, Clock for matrix9 is disabled  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN__DISABLE 0U
+/* Field Value: MATRIX9_CLKEN__AUTOMATIC, Clock is enabled if unit is used,
+ * frequency is defined by the register setting for this pipeline (see
+ * [endpoint_name]_Static register)  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN__AUTOMATIC 0x1U
+/* Field Value: MATRIX9_CLKEN__FULL, Clock for matrix9 is without gating  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN__FULL 0x3U
+
+/* Register: IMXDPUV1_pixengcfg_matrix9_Status */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS                    ((uint32_t)(0x8AC))
+#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_OFFSET             ((uint32_t)(0xAC))
+#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_RESET_VALUE        0U
+#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_RESET_MASK         0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL_MASK   0x70000U
+#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL_SHIFT  16U
+/* Field Value: MATRIX9_SEL__STORE9, matrix9 module is used from store9 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__STORE9 0x1U
+/* Field Value: MATRIX9_SEL__EXTDST0, matrix9 module is used from extdst0
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST0 0x2U
+/* Field Value: MATRIX9_SEL__EXTDST4, matrix9 module is used from extdst4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST4 0x3U
+/* Field Value: MATRIX9_SEL__EXTDST1, matrix9 module is used from extdst1
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST1 0x4U
+/* Field Value: MATRIX9_SEL__EXTDST5, matrix9 module is used from extdst5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST5 0x5U
+/* Field Value: MATRIX9_SEL__STORE4, matrix9 module is used from store4 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__STORE4 0x6U
+/* Field Value: MATRIX9_SEL__STORE5, matrix9 module is used from store5 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__STORE5 0x7U
+/* Field Value: MATRIX9_SEL__DISABLE, matrix9 module is not used  */
+#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_hscaler9_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK               ((uint32_t)(0x8C0))
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_OFFSET        ((uint32_t)(0xC0))
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_RESET_VALUE   0U
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_RESET_MASK    0U
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK_SHIFT 0U
+/* Field Value: HSCALER9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset counter
+ * value is 1.  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: HSCALER9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: HSCALER9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: HSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: HSCALER9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_hscaler9_LockStatus */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS               ((uint32_t)(0x8C4))
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_OFFSET        ((uint32_t)(0xC4))
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_RESET_VALUE   0U
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_hscaler9_Dynamic */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC                  ((uint32_t)(0x8C8))
+#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_OFFSET           ((uint32_t)(0xC8))
+#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_RESET_VALUE      0x1000000U
+#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL_SHIFT 0U
+/* Field Value: HSCALER9_SRC_SEL__DISABLE, Unit hscaler9 input port src is
+ * disabled  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__DISABLE 0U
+/* Field Value: HSCALER9_SRC_SEL__VSCALER9, Unit hscaler9 input port src is
+ * connected to output of unit vscaler9  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__VSCALER9 0x8U
+/* Field Value: HSCALER9_SRC_SEL__FILTER9, Unit hscaler9 input port src is
+ * connected to output of unit filter9  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__FILTER9 0x9U
+/* Field Value: HSCALER9_SRC_SEL__MATRIX9, Unit hscaler9 input port src is
+ * connected to output of unit matrix9  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__MATRIX9 0x6U
+#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN_MASK 0x3000000U
+#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN_SHIFT 24U
+/* Field Value: HSCALER9_CLKEN__DISABLE, Clock for hscaler9 is disabled  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN__DISABLE 0U
+/* Field Value: HSCALER9_CLKEN__AUTOMATIC, Clock is enabled if unit is used,
+ * frequency is defined by the register setting for this pipeline (see
+ * [endpoint_name]_Static register)  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN__AUTOMATIC 0x1U
+/* Field Value: HSCALER9_CLKEN__FULL, Clock for hscaler9 is without gating  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN__FULL 0x3U
+
+/* Register: IMXDPUV1_pixengcfg_hscaler9_Status */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS                   ((uint32_t)(0x8CC))
+#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_OFFSET            ((uint32_t)(0xCC))
+#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_RESET_VALUE       0U
+#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_RESET_MASK        0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL_SHIFT 16U
+/* Field Value: HSCALER9_SEL__STORE9, hscaler9 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__STORE9 0x1U
+/* Field Value: HSCALER9_SEL__EXTDST0, hscaler9 module is used from extdst0
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST0 0x2U
+/* Field Value: HSCALER9_SEL__EXTDST4, hscaler9 module is used from extdst4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST4 0x3U
+/* Field Value: HSCALER9_SEL__EXTDST1, hscaler9 module is used from extdst1
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST1 0x4U
+/* Field Value: HSCALER9_SEL__EXTDST5, hscaler9 module is used from extdst5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST5 0x5U
+/* Field Value: HSCALER9_SEL__STORE4, hscaler9 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__STORE4 0x6U
+/* Field Value: HSCALER9_SEL__STORE5, hscaler9 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__STORE5 0x7U
+/* Field Value: HSCALER9_SEL__DISABLE, hscaler9 module is not used  */
+#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_vscaler9_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK               ((uint32_t)(0x8E0))
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_OFFSET        ((uint32_t)(0xE0))
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_RESET_VALUE   0U
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_RESET_MASK    0U
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK_SHIFT 0U
+/* Field Value: VSCALER9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset counter
+ * value is 1.  */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: VSCALER9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: VSCALER9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: VSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: VSCALER9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_vscaler9_LockStatus */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS               ((uint32_t)(0x8E4))
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_OFFSET        ((uint32_t)(0xE4))
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_RESET_VALUE   0U
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_vscaler9_Dynamic */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC                  ((uint32_t)(0x8E8))
+#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_OFFSET           ((uint32_t)(0xE8))
+#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_RESET_VALUE      0x1000000U
+#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL_SHIFT 0U
+/* Field Value: VSCALER9_SRC_SEL__DISABLE, Unit vscaler9 input port src is
+ * disabled  */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL__DISABLE 0U
+/* Field Value: VSCALER9_SRC_SEL__HSCALER9, Unit vscaler9 input port src is
+ * connected to output of unit hscaler9  */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL__HSCALER9 0x7U
+/* Field Value: VSCALER9_SRC_SEL__MATRIX9, Unit vscaler9 input port src is
+ * connected to output of unit matrix9  */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL__MATRIX9 0x6U
+#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN_MASK 0x3000000U
+#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN_SHIFT 24U
+/* Field Value: VSCALER9_CLKEN__DISABLE, Clock for vscaler9 is disabled  */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN__DISABLE 0U
+/* Field Value: VSCALER9_CLKEN__AUTOMATIC, Clock is enabled if unit is used,
+ * frequency is defined by the register setting for this pipeline (see
+ * [endpoint_name]_Static register)  */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN__AUTOMATIC 0x1U
+/* Field Value: VSCALER9_CLKEN__FULL, Clock for vscaler9 is without gating  */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN__FULL 0x3U
+
+/* Register: IMXDPUV1_pixengcfg_vscaler9_Status */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS                   ((uint32_t)(0x8EC))
+#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_OFFSET            ((uint32_t)(0xEC))
+#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_RESET_VALUE       0U
+#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_RESET_MASK        0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL_SHIFT 16U
+/* Field Value: VSCALER9_SEL__STORE9, vscaler9 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__STORE9 0x1U
+/* Field Value: VSCALER9_SEL__EXTDST0, vscaler9 module is used from extdst0
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST0 0x2U
+/* Field Value: VSCALER9_SEL__EXTDST4, vscaler9 module is used from extdst4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST4 0x3U
+/* Field Value: VSCALER9_SEL__EXTDST1, vscaler9 module is used from extdst1
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST1 0x4U
+/* Field Value: VSCALER9_SEL__EXTDST5, vscaler9 module is used from extdst5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST5 0x5U
+/* Field Value: VSCALER9_SEL__STORE4, vscaler9 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__STORE4 0x6U
+/* Field Value: VSCALER9_SEL__STORE5, vscaler9 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__STORE5 0x7U
+/* Field Value: VSCALER9_SEL__DISABLE, vscaler9 module is not used  */
+#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_filter9_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK                ((uint32_t)(0x900))
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_OFFSET         ((uint32_t)(0x100))
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_RESET_MASK     0U
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK_SHIFT 0U
+/* Field Value: FILTER9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset counter
+ * value is 1.  */
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: FILTER9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: FILTER9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: FILTER9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: FILTER9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_filter9_LockStatus */
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS                ((uint32_t)(0x904))
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_OFFSET         ((uint32_t)(0x104))
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_filter9_Dynamic */
+#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC                   ((uint32_t)(0x908))
+#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_OFFSET            ((uint32_t)(0x108))
+#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_RESET_VALUE       0x1000000U
+#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL_SHIFT 0U
+/* Field Value: FILTER9_SRC_SEL__DISABLE, Unit filter9 input port src is disabled  */
+#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL__DISABLE 0U
+/* Field Value: FILTER9_SRC_SEL__HSCALER9, Unit filter9 input port src is
+ * connected to output of unit hscaler9  */
+#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL__HSCALER9 0x7U
+/* Field Value: FILTER9_SRC_SEL__MATRIX9, Unit filter9 input port src is connected
+ * to output of unit matrix9  */
+#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL__MATRIX9 0x6U
+#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN_MASK 0x3000000U
+#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN_SHIFT 24U
+/* Field Value: FILTER9_CLKEN__DISABLE, Clock for filter9 is disabled  */
+#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN__DISABLE 0U
+/* Field Value: FILTER9_CLKEN__AUTOMATIC, Clock is enabled if unit is used,
+ * frequency is defined by the register setting for this pipeline (see
+ * [endpoint_name]_Static register)  */
+#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN__AUTOMATIC 0x1U
+/* Field Value: FILTER9_CLKEN__FULL, Clock for filter9 is without gating  */
+#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN__FULL 0x3U
+
+/* Register: IMXDPUV1_pixengcfg_filter9_Status */
+#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS                    ((uint32_t)(0x90C))
+#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_OFFSET             ((uint32_t)(0x10C))
+#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_RESET_VALUE        0U
+#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_RESET_MASK         0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL_MASK   0x70000U
+#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL_SHIFT  16U
+/* Field Value: FILTER9_SEL__STORE9, filter9 module is used from store9 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__STORE9 0x1U
+/* Field Value: FILTER9_SEL__EXTDST0, filter9 module is used from extdst0
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST0 0x2U
+/* Field Value: FILTER9_SEL__EXTDST4, filter9 module is used from extdst4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST4 0x3U
+/* Field Value: FILTER9_SEL__EXTDST1, filter9 module is used from extdst1
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST1 0x4U
+/* Field Value: FILTER9_SEL__EXTDST5, filter9 module is used from extdst5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST5 0x5U
+/* Field Value: FILTER9_SEL__STORE4, filter9 module is used from store4 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__STORE4 0x6U
+/* Field Value: FILTER9_SEL__STORE5, filter9 module is used from store5 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__STORE5 0x7U
+/* Field Value: FILTER9_SEL__DISABLE, filter9 module is not used  */
+#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_blitblend9_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK             ((uint32_t)(0x920))
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_OFFSET      ((uint32_t)(0x120))
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_RESET_MASK  0U
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK_SHIFT 0U
+/* Field Value: BLITBLEND9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset
+ * counter value is 1.  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: BLITBLEND9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: BLITBLEND9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: BLITBLEND9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege
+ * protection.  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: BLITBLEND9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_blitblend9_LockStatus */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS             ((uint32_t)(0x924))
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_OFFSET      ((uint32_t)(0x124))
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_blitblend9_Dynamic */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC                ((uint32_t)(0x928))
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_OFFSET         ((uint32_t)(0x128))
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_RESET_VALUE    0x1000000U
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL_SHIFT 0U
+/* Field Value: BLITBLEND9_PRIM_SEL__DISABLE, Unit blitblend9 input port prim
+ * is disabled  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__DISABLE 0U
+/* Field Value: BLITBLEND9_PRIM_SEL__HSCALER9, Unit blitblend9 input port
+ * prim is connected to output of unit hscaler9  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__HSCALER9 0x7U
+/* Field Value: BLITBLEND9_PRIM_SEL__VSCALER9, Unit blitblend9 input port
+ * prim is connected to output of unit vscaler9  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__VSCALER9 0x8U
+/* Field Value: BLITBLEND9_PRIM_SEL__FILTER9, Unit blitblend9 input port prim
+ * is connected to output of unit filter9  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__FILTER9 0x9U
+/* Field Value: BLITBLEND9_PRIM_SEL__ROP9, Unit blitblend9 input port prim
+ * is connected to output of unit rop9  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__ROP9 0x4U
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL_MASK 0x3F00U
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL_SHIFT 8U
+/* Field Value: BLITBLEND9_SEC_SEL__DISABLE, Unit blitblend9 input port sec
+ * is disabled  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL__DISABLE 0U
+/* Field Value: BLITBLEND9_SEC_SEL__FETCHDECODE9, Unit blitblend9 input port
+ * sec is connected to output of unit fetchdecode9  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL__FETCHDECODE9 0x1U
+/* Field Value: BLITBLEND9_SEC_SEL__FETCHPERSP9, Unit blitblend9 input port
+ * sec is connected to output of unit fetchpersp9  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL__FETCHPERSP9 0x2U
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN_MASK 0x3000000U
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN_SHIFT 24U
+/* Field Value: BLITBLEND9_CLKEN__DISABLE, Clock for blitblend9 is disabled  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN__DISABLE 0U
+/* Field Value: BLITBLEND9_CLKEN__AUTOMATIC, Clock is enabled if unit is used,
+ * frequency is defined by the register setting for this pipeline (see
+ * [endpoint_name]_Static register)  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN__AUTOMATIC 0x1U
+/* Field Value: BLITBLEND9_CLKEN__FULL, Clock for blitblend9 is without gating  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN__FULL 0x3U
+
+/* Register: IMXDPUV1_pixengcfg_blitblend9_Status */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS                 ((uint32_t)(0x92C))
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_OFFSET          ((uint32_t)(0x12C))
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_RESET_VALUE     0U
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_RESET_MASK      0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL_SHIFT 16U
+/* Field Value: BLITBLEND9_SEL__STORE9, blitblend9 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__STORE9 0x1U
+/* Field Value: BLITBLEND9_SEL__EXTDST0, blitblend9 module is used from extdst0
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST0 0x2U
+/* Field Value: BLITBLEND9_SEL__EXTDST4, blitblend9 module is used from extdst4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST4 0x3U
+/* Field Value: BLITBLEND9_SEL__EXTDST1, blitblend9 module is used from extdst1
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST1 0x4U
+/* Field Value: BLITBLEND9_SEL__EXTDST5, blitblend9 module is used from extdst5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST5 0x5U
+/* Field Value: BLITBLEND9_SEL__STORE4, blitblend9 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__STORE4 0x6U
+/* Field Value: BLITBLEND9_SEL__STORE5, blitblend9 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__STORE5 0x7U
+/* Field Value: BLITBLEND9_SEL__DISABLE, blitblend9 module is not used  */
+#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_store9_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK                 ((uint32_t)(0x940))
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_OFFSET          ((uint32_t)(0x140))
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_RESET_VALUE     0U
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_RESET_MASK      0U
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK_SHIFT 0U
+/* Field Value: STORE9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset counter
+ * value is 1.  */
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: STORE9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: STORE9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: STORE9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: STORE9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_store9_LockStatus */
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS                 ((uint32_t)(0x944))
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_OFFSET          ((uint32_t)(0x144))
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_RESET_VALUE     0U
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_store9_Static */
+#define IMXDPUV1_PIXENGCFG_STORE9_STATIC                     ((uint32_t)(0x948))
+#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_OFFSET              ((uint32_t)(0x148))
+#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_RESET_VALUE         0x800010U
+#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SHDEN_MASK   0x1U
+#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SHDEN_SHIFT  0U
+#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_POWERDOWN_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_POWERDOWN_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE_SHIFT 8U
+/* Field Value: STORE9_SYNC_MODE__SINGLE, Reconfig pipeline after explicit
+ * trigger  */
+#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE__SINGLE 0U
+/* Field Value: STORE9_SYNC_MODE__AUTO, Reconfig pipeline after every kick
+ * when idle  */
+#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE__AUTO 0x1U
+#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET_MASK 0x800U
+#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET_SHIFT 11U
+/* Field Value: STORE9_SW_RESET__OPERATION, Normal Operation  */
+#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET__OPERATION 0U
+/* Field Value: STORE9_SW_RESET__SWRESET, Software Reset  */
+#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET__SWRESET 0x1U
+#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_DIV_MASK     0xFF0000U
+#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_DIV_SHIFT    16U
+
+/* Register: IMXDPUV1_pixengcfg_store9_Dynamic */
+#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC                    ((uint32_t)(0x94C))
+#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_OFFSET             ((uint32_t)(0x14C))
+#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_RESET_VALUE        0x1U
+#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL_SHIFT 0U
+/* Field Value: STORE9_SRC_SEL__DISABLE, Unit store9 input port src is disabled  */
+#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__DISABLE 0U
+/* Field Value: STORE9_SRC_SEL__HSCALER9, Unit store9 input port src is connected
+ * to output of unit hscaler9  */
+#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__HSCALER9 0x7U
+/* Field Value: STORE9_SRC_SEL__VSCALER9, Unit store9 input port src is connected
+ * to output of unit vscaler9  */
+#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__VSCALER9 0x8U
+/* Field Value: STORE9_SRC_SEL__FILTER9, Unit store9 input port src is connected
+ * to output of unit filter9  */
+#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__FILTER9 0x9U
+/* Field Value: STORE9_SRC_SEL__BLITBLEND9, Unit store9 input port src is
+ * connected to output of unit blitblend9  */
+#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__BLITBLEND9 0xAU
+/* Field Value: STORE9_SRC_SEL__FETCHDECODE9, Unit store9 input port src is
+ * connected to output of unit fetchdecode9  */
+#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__FETCHDECODE9 0x1U
+/* Field Value: STORE9_SRC_SEL__FETCHPERSP9, Unit store9 input port src is
+ * connected to output of unit fetchpersp9  */
+#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__FETCHPERSP9 0x2U
+
+/* Register: IMXDPUV1_pixengcfg_store9_Request */
+#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST                    ((uint32_t)(0x950))
+#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_OFFSET             ((uint32_t)(0x150))
+#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_RESET_VALUE        0U
+#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SEL_SHDLDREQ_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SEL_SHDLDREQ_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SHDLDREQ_MASK 0x3FFFFEU
+#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SHDLDREQ_SHIFT 1U
+
+/* Register: IMXDPUV1_pixengcfg_store9_Trigger */
+#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER                    ((uint32_t)(0x954))
+#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_OFFSET             ((uint32_t)(0x154))
+#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_RESET_VALUE        0U
+#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_RESET_MASK         0xFFFFFFEEU
+#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_SYNC_TRIGGER_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_SYNC_TRIGGER_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U
+
+/* Register: IMXDPUV1_pixengcfg_store9_Status */
+#define IMXDPUV1_PIXENGCFG_STORE9_STATUS                     ((uint32_t)(0x958))
+#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_OFFSET              ((uint32_t)(0x158))
+#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_RESET_VALUE         0U
+#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS_MASK 0x3U
+#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS_SHIFT 0U
+/* Field Value: STORE9_PIPELINE_STATUS__EMPTY, Pipeline with endpoint store9
+ * is empty  */
+#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__EMPTY 0U
+/* Field Value: STORE9_PIPELINE_STATUS__RUNNING, Pipeline with endpoint store9
+ * is currently processing one operation  */
+#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__RUNNING 0x1U
+/* Field Value: STORE9_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with
+ * endpoint store9 is currently processing one operation with a second one
+ * already kicked to be processed afterwards  */
+#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U
+/* Field Value: STORE9_PIPELINE_STATUS__RESERVED, reserved  */
+#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__RESERVED 0x3U
+#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY_SHIFT 8U
+/* Field Value: STORE9_SYNC_BUSY__IDLE, store9 synchronizer is idle  */
+#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY__IDLE 0U
+/* Field Value: STORE9_SYNC_BUSY__BUSY, store9 synchronizer is busy  */
+#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY__BUSY 0x1U
+
+/* Register: IMXDPUV1_pixengcfg_constframe0_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK            ((uint32_t)(0x960))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_OFFSET     ((uint32_t)(0x160))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_RESET_MASK 0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK_SHIFT 0U
+/* Field Value: CONSTFRAME0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset
+ * counter value is 1.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: CONSTFRAME0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock
+ * counter. Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: CONSTFRAME0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: CONSTFRAME0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege
+ * protection.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: CONSTFRAME0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_constframe0_LockStatus */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS            ((uint32_t)(0x964))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_OFFSET     ((uint32_t)(0x164))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_constframe0_Status */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS                ((uint32_t)(0x968))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_OFFSET         ((uint32_t)(0x168))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_RESET_MASK     0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL_SHIFT 16U
+/* Field Value: CONSTFRAME0_SEL__STORE9, constframe0 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__STORE9 0x1U
+/* Field Value: CONSTFRAME0_SEL__EXTDST0, constframe0 module is used from
+ * extdst0 processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST0 0x2U
+/* Field Value: CONSTFRAME0_SEL__EXTDST4, constframe0 module is used from
+ * extdst4 processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST4 0x3U
+/* Field Value: CONSTFRAME0_SEL__EXTDST1, constframe0 module is used from
+ * extdst1 processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST1 0x4U
+/* Field Value: CONSTFRAME0_SEL__EXTDST5, constframe0 module is used from
+ * extdst5 processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST5 0x5U
+/* Field Value: CONSTFRAME0_SEL__STORE4, constframe0 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__STORE4 0x6U
+/* Field Value: CONSTFRAME0_SEL__STORE5, constframe0 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__STORE5 0x7U
+/* Field Value: CONSTFRAME0_SEL__DISABLE, constframe0 module is not used  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_extdst0_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK                ((uint32_t)(0x980))
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_OFFSET         ((uint32_t)(0x180))
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_RESET_MASK     0U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK_SHIFT 0U
+/* Field Value: EXTDST0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset counter
+ * value is 1.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: EXTDST0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: EXTDST0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: EXTDST0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: EXTDST0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_extdst0_LockStatus */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS                ((uint32_t)(0x984))
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_OFFSET         ((uint32_t)(0x184))
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_extdst0_Static */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC                    ((uint32_t)(0x988))
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_OFFSET             ((uint32_t)(0x188))
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_RESET_VALUE        0x800010U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SHDEN_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SHDEN_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_POWERDOWN_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_POWERDOWN_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE_SHIFT 8U
+/* Field Value: EXTDST0_SYNC_MODE__SINGLE, Reconfig pipeline after explicit
+ * trigger  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE__SINGLE 0U
+/* Field Value: EXTDST0_SYNC_MODE__AUTO, Reconfig pipeline after every kick
+ * when idle  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE__AUTO 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET_MASK 0x800U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET_SHIFT 11U
+/* Field Value: EXTDST0_SW_RESET__OPERATION, Normal Operation  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET__OPERATION 0U
+/* Field Value: EXTDST0_SW_RESET__SWRESET, Software Reset  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET__SWRESET 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_DIV_MASK   0xFF0000U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_DIV_SHIFT  16U
+
+/* Register: IMXDPUV1_pixengcfg_extdst0_Dynamic */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC                   ((uint32_t)(0x98C))
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_OFFSET            ((uint32_t)(0x18C))
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_RESET_VALUE       0x2CU
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL_SHIFT 0U
+/* Field Value: EXTDST0_SRC_SEL__DISABLE, Unit extdst0 input port src is disabled  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__DISABLE 0U
+/* Field Value: EXTDST0_SRC_SEL__BLITBLEND9, Unit extdst0 input port src is
+ * connected to output of unit blitblend9  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__BLITBLEND9 0xAU
+/* Field Value: EXTDST0_SRC_SEL__CONSTFRAME0, Unit extdst0 input port src
+ * is connected to output of unit constframe0  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME0 0xCU
+/* Field Value: EXTDST0_SRC_SEL__CONSTFRAME1, Unit extdst0 input port src
+ * is connected to output of unit constframe1  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME1 0x10U
+/* Field Value: EXTDST0_SRC_SEL__CONSTFRAME4, Unit extdst0 input port src
+ * is connected to output of unit constframe4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME4 0xEU
+/* Field Value: EXTDST0_SRC_SEL__CONSTFRAME5, Unit extdst0 input port src
+ * is connected to output of unit constframe5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME5 0x12U
+/* Field Value: EXTDST0_SRC_SEL__MATRIX4, Unit extdst0 input port src is connected
+ * to output of unit matrix4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__MATRIX4 0x23U
+/* Field Value: EXTDST0_SRC_SEL__HSCALER4, Unit extdst0 input port src is
+ * connected to output of unit hscaler4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__HSCALER4 0x24U
+/* Field Value: EXTDST0_SRC_SEL__VSCALER4, Unit extdst0 input port src is
+ * connected to output of unit vscaler4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__VSCALER4 0x25U
+/* Field Value: EXTDST0_SRC_SEL__EXTSRC4, Unit extdst0 input port src is connected
+ * to output of unit extsrc4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__EXTSRC4 0x14U
+/* Field Value: EXTDST0_SRC_SEL__MATRIX5, Unit extdst0 input port src is connected
+ * to output of unit matrix5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__MATRIX5 0x28U
+/* Field Value: EXTDST0_SRC_SEL__HSCALER5, Unit extdst0 input port src is
+ * connected to output of unit hscaler5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__HSCALER5 0x29U
+/* Field Value: EXTDST0_SRC_SEL__VSCALER5, Unit extdst0 input port src is
+ * connected to output of unit vscaler5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__VSCALER5 0x2AU
+/* Field Value: EXTDST0_SRC_SEL__EXTSRC5, Unit extdst0 input port src is connected
+ * to output of unit extsrc5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__EXTSRC5 0x16U
+/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND6, Unit extdst0 input port src
+ * is connected to output of unit layerblend6  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND6 0x32U
+/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND5, Unit extdst0 input port src
+ * is connected to output of unit layerblend5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND5 0x31U
+/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND4, Unit extdst0 input port src
+ * is connected to output of unit layerblend4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND4 0x30U
+/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND3, Unit extdst0 input port src
+ * is connected to output of unit layerblend3  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND3 0x2FU
+/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND2, Unit extdst0 input port src
+ * is connected to output of unit layerblend2  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND2 0x2EU
+/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND1, Unit extdst0 input port src
+ * is connected to output of unit layerblend1  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND1 0x2DU
+/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND0, Unit extdst0 input port src
+ * is connected to output of unit layerblend0  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND0 0x2CU
+
+/* Register: IMXDPUV1_pixengcfg_extdst0_Request */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST                   ((uint32_t)(0x990))
+#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_OFFSET            ((uint32_t)(0x190))
+#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_RESET_VALUE       0U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SEL_SHDLDREQ_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SEL_SHDLDREQ_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SHDLDREQ_MASK 0x3FFFFEU
+#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SHDLDREQ_SHIFT 1U
+
+/* Register: IMXDPUV1_pixengcfg_extdst0_Trigger */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER                   ((uint32_t)(0x994))
+#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_OFFSET            ((uint32_t)(0x194))
+#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_RESET_VALUE       0U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_RESET_MASK        0xFFFFFFEEU
+#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_SYNC_TRIGGER_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_SYNC_TRIGGER_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U
+
+/* Register: IMXDPUV1_pixengcfg_extdst0_Status */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS                    ((uint32_t)(0x998))
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_OFFSET             ((uint32_t)(0x198))
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_RESET_VALUE        0U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS_MASK 0x3U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS_SHIFT 0U
+/* Field Value: EXTDST0_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst0
+ * is empty  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__EMPTY 0U
+/* Field Value: EXTDST0_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst0
+ * is currently processing one operation  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__RUNNING 0x1U
+/* Field Value: EXTDST0_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with
+ * endpoint extdst0 is currently processing one operation with a second
+ * one already kicked to be processed afterwards  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U
+/* Field Value: EXTDST0_PIPELINE_STATUS__RESERVED, reserved  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__RESERVED 0x3U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY_SHIFT 8U
+/* Field Value: EXTDST0_SYNC_BUSY__IDLE, extdst0 synchronizer is idle  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY__IDLE 0U
+/* Field Value: EXTDST0_SYNC_BUSY__BUSY, extdst0 synchronizer is busy  */
+#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY__BUSY 0x1U
+
+/* Register: IMXDPUV1_pixengcfg_constframe4_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK            ((uint32_t)(0x9A0))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_OFFSET     ((uint32_t)(0x1A0))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_RESET_MASK 0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK_SHIFT 0U
+/* Field Value: CONSTFRAME4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset
+ * counter value is 1.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: CONSTFRAME4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock
+ * counter. Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: CONSTFRAME4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: CONSTFRAME4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege
+ * protection.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: CONSTFRAME4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_constframe4_LockStatus */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS            ((uint32_t)(0x9A4))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_OFFSET     ((uint32_t)(0x1A4))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_constframe4_Status */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS                ((uint32_t)(0x9A8))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_OFFSET         ((uint32_t)(0x1A8))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_RESET_MASK     0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL_SHIFT 16U
+/* Field Value: CONSTFRAME4_SEL__STORE9, constframe4 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__STORE9 0x1U
+/* Field Value: CONSTFRAME4_SEL__EXTDST0, constframe4 module is used from
+ * extdst0 processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST0 0x2U
+/* Field Value: CONSTFRAME4_SEL__EXTDST4, constframe4 module is used from
+ * extdst4 processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST4 0x3U
+/* Field Value: CONSTFRAME4_SEL__EXTDST1, constframe4 module is used from
+ * extdst1 processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST1 0x4U
+/* Field Value: CONSTFRAME4_SEL__EXTDST5, constframe4 module is used from
+ * extdst5 processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST5 0x5U
+/* Field Value: CONSTFRAME4_SEL__STORE4, constframe4 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__STORE4 0x6U
+/* Field Value: CONSTFRAME4_SEL__STORE5, constframe4 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__STORE5 0x7U
+/* Field Value: CONSTFRAME4_SEL__DISABLE, constframe4 module is not used  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_extdst4_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK                ((uint32_t)(0x9C0))
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_OFFSET         ((uint32_t)(0x1C0))
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_RESET_MASK     0U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK_SHIFT 0U
+/* Field Value: EXTDST4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset counter
+ * value is 1.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: EXTDST4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: EXTDST4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: EXTDST4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: EXTDST4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_extdst4_LockStatus */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS                ((uint32_t)(0x9C4))
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_OFFSET         ((uint32_t)(0x1C4))
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_extdst4_Static */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC                    ((uint32_t)(0x9C8))
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_OFFSET             ((uint32_t)(0x1C8))
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_RESET_VALUE        0x800010U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SHDEN_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SHDEN_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_POWERDOWN_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_POWERDOWN_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE_SHIFT 8U
+/* Field Value: EXTDST4_SYNC_MODE__SINGLE, Reconfig pipeline after explicit
+ * trigger  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE__SINGLE 0U
+/* Field Value: EXTDST4_SYNC_MODE__AUTO, Reconfig pipeline after every kick
+ * when idle  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE__AUTO 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET_MASK 0x800U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET_SHIFT 11U
+/* Field Value: EXTDST4_SW_RESET__OPERATION, Normal Operation  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET__OPERATION 0U
+/* Field Value: EXTDST4_SW_RESET__SWRESET, Software Reset  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET__SWRESET 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_DIV_MASK   0xFF0000U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_DIV_SHIFT  16U
+
+/* Register: IMXDPUV1_pixengcfg_extdst4_Dynamic */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC                   ((uint32_t)(0x9CC))
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_OFFSET            ((uint32_t)(0x1CC))
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_RESET_VALUE       0x30U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL_SHIFT 0U
+/* Field Value: EXTDST4_SRC_SEL__DISABLE, Unit extdst4 input port src is disabled  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__DISABLE 0U
+/* Field Value: EXTDST4_SRC_SEL__BLITBLEND9, Unit extdst4 input port src is
+ * connected to output of unit blitblend9  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__BLITBLEND9 0xAU
+/* Field Value: EXTDST4_SRC_SEL__CONSTFRAME0, Unit extdst4 input port src
+ * is connected to output of unit constframe0  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME0 0xCU
+/* Field Value: EXTDST4_SRC_SEL__CONSTFRAME1, Unit extdst4 input port src
+ * is connected to output of unit constframe1  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME1 0x10U
+/* Field Value: EXTDST4_SRC_SEL__CONSTFRAME4, Unit extdst4 input port src
+ * is connected to output of unit constframe4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME4 0xEU
+/* Field Value: EXTDST4_SRC_SEL__CONSTFRAME5, Unit extdst4 input port src
+ * is connected to output of unit constframe5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME5 0x12U
+/* Field Value: EXTDST4_SRC_SEL__MATRIX4, Unit extdst4 input port src is connected
+ * to output of unit matrix4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__MATRIX4 0x23U
+/* Field Value: EXTDST4_SRC_SEL__HSCALER4, Unit extdst4 input port src is
+ * connected to output of unit hscaler4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__HSCALER4 0x24U
+/* Field Value: EXTDST4_SRC_SEL__VSCALER4, Unit extdst4 input port src is
+ * connected to output of unit vscaler4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__VSCALER4 0x25U
+/* Field Value: EXTDST4_SRC_SEL__MATRIX5, Unit extdst4 input port src is connected
+ * to output of unit matrix5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__MATRIX5 0x28U
+/* Field Value: EXTDST4_SRC_SEL__HSCALER5, Unit extdst4 input port src is
+ * connected to output of unit hscaler5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__HSCALER5 0x29U
+/* Field Value: EXTDST4_SRC_SEL__VSCALER5, Unit extdst4 input port src is
+ * connected to output of unit vscaler5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__VSCALER5 0x2AU
+/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND6, Unit extdst4 input port src
+ * is connected to output of unit layerblend6  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND6 0x32U
+/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND5, Unit extdst4 input port src
+ * is connected to output of unit layerblend5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND5 0x31U
+/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND4, Unit extdst4 input port src
+ * is connected to output of unit layerblend4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND4 0x30U
+/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND3, Unit extdst4 input port src
+ * is connected to output of unit layerblend3  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND3 0x2FU
+/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND2, Unit extdst4 input port src
+ * is connected to output of unit layerblend2  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND2 0x2EU
+/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND1, Unit extdst4 input port src
+ * is connected to output of unit layerblend1  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND1 0x2DU
+/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND0, Unit extdst4 input port src
+ * is connected to output of unit layerblend0  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND0 0x2CU
+
+/* Register: IMXDPUV1_pixengcfg_extdst4_Request */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST                   ((uint32_t)(0x9D0))
+#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_OFFSET            ((uint32_t)(0x1D0))
+#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_RESET_VALUE       0U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SEL_SHDLDREQ_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SEL_SHDLDREQ_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SHDLDREQ_MASK 0x3FFFFEU
+#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SHDLDREQ_SHIFT 1U
+
+/* Register: IMXDPUV1_pixengcfg_extdst4_Trigger */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER                   ((uint32_t)(0x9D4))
+#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_OFFSET            ((uint32_t)(0x1D4))
+#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_RESET_VALUE       0U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_RESET_MASK        0xFFFFFFEEU
+#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_SYNC_TRIGGER_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_SYNC_TRIGGER_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U
+
+/* Register: IMXDPUV1_pixengcfg_extdst4_Status */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS                    ((uint32_t)(0x9D8))
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_OFFSET             ((uint32_t)(0x1D8))
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_RESET_VALUE        0U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS_MASK 0x3U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS_SHIFT 0U
+/* Field Value: EXTDST4_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst4
+ * is empty  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__EMPTY 0U
+/* Field Value: EXTDST4_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst4
+ * is currently processing one operation  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__RUNNING 0x1U
+/* Field Value: EXTDST4_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with
+ * endpoint extdst4 is currently processing one operation with a second
+ * one already kicked to be processed afterwards  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U
+/* Field Value: EXTDST4_PIPELINE_STATUS__RESERVED, reserved  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__RESERVED 0x3U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY_SHIFT 8U
+/* Field Value: EXTDST4_SYNC_BUSY__IDLE, extdst4 synchronizer is idle  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY__IDLE 0U
+/* Field Value: EXTDST4_SYNC_BUSY__BUSY, extdst4 synchronizer is busy  */
+#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY__BUSY 0x1U
+
+/* Register: IMXDPUV1_pixengcfg_constframe1_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK            ((uint32_t)(0x9E0))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_OFFSET     ((uint32_t)(0x1E0))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_RESET_MASK 0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK_SHIFT 0U
+/* Field Value: CONSTFRAME1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset
+ * counter value is 1.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: CONSTFRAME1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock
+ * counter. Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: CONSTFRAME1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: CONSTFRAME1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege
+ * protection.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: CONSTFRAME1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_constframe1_LockStatus */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS            ((uint32_t)(0x9E4))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_OFFSET     ((uint32_t)(0x1E4))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_constframe1_Status */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS                ((uint32_t)(0x9E8))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_OFFSET         ((uint32_t)(0x1E8))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_RESET_MASK     0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL_SHIFT 16U
+/* Field Value: CONSTFRAME1_SEL__STORE9, constframe1 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__STORE9 0x1U
+/* Field Value: CONSTFRAME1_SEL__EXTDST0, constframe1 module is used from
+ * extdst0 processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST0 0x2U
+/* Field Value: CONSTFRAME1_SEL__EXTDST4, constframe1 module is used from
+ * extdst4 processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST4 0x3U
+/* Field Value: CONSTFRAME1_SEL__EXTDST1, constframe1 module is used from
+ * extdst1 processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST1 0x4U
+/* Field Value: CONSTFRAME1_SEL__EXTDST5, constframe1 module is used from
+ * extdst5 processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST5 0x5U
+/* Field Value: CONSTFRAME1_SEL__STORE4, constframe1 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__STORE4 0x6U
+/* Field Value: CONSTFRAME1_SEL__STORE5, constframe1 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__STORE5 0x7U
+/* Field Value: CONSTFRAME1_SEL__DISABLE, constframe1 module is not used  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_extdst1_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK                ((uint32_t)(0xA00))
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_OFFSET         ((uint32_t)(0x200))
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_RESET_MASK     0U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK_SHIFT 0U
+/* Field Value: EXTDST1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset counter
+ * value is 1.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: EXTDST1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: EXTDST1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: EXTDST1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: EXTDST1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_extdst1_LockStatus */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS                ((uint32_t)(0xA04))
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_OFFSET         ((uint32_t)(0x204))
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_extdst1_Static */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC                    ((uint32_t)(0xA08))
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_OFFSET             ((uint32_t)(0x208))
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_RESET_VALUE        0x800010U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SHDEN_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SHDEN_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_POWERDOWN_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_POWERDOWN_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE_SHIFT 8U
+/* Field Value: EXTDST1_SYNC_MODE__SINGLE, Reconfig pipeline after explicit
+ * trigger  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE__SINGLE 0U
+/* Field Value: EXTDST1_SYNC_MODE__AUTO, Reconfig pipeline after every kick
+ * when idle  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE__AUTO 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET_MASK 0x800U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET_SHIFT 11U
+/* Field Value: EXTDST1_SW_RESET__OPERATION, Normal Operation  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET__OPERATION 0U
+/* Field Value: EXTDST1_SW_RESET__SWRESET, Software Reset  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET__SWRESET 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_DIV_MASK   0xFF0000U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_DIV_SHIFT  16U
+
+/* Register: IMXDPUV1_pixengcfg_extdst1_Dynamic */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC                   ((uint32_t)(0xA0C))
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_OFFSET            ((uint32_t)(0x20C))
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_RESET_VALUE       0x2DU
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL_SHIFT 0U
+/* Field Value: EXTDST1_SRC_SEL__DISABLE, Unit extdst1 input port src is disabled  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__DISABLE 0U
+/* Field Value: EXTDST1_SRC_SEL__BLITBLEND9, Unit extdst1 input port src is
+ * connected to output of unit blitblend9  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__BLITBLEND9 0xAU
+/* Field Value: EXTDST1_SRC_SEL__CONSTFRAME0, Unit extdst1 input port src
+ * is connected to output of unit constframe0  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME0 0xCU
+/* Field Value: EXTDST1_SRC_SEL__CONSTFRAME1, Unit extdst1 input port src
+ * is connected to output of unit constframe1  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME1 0x10U
+/* Field Value: EXTDST1_SRC_SEL__CONSTFRAME4, Unit extdst1 input port src
+ * is connected to output of unit constframe4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME4 0xEU
+/* Field Value: EXTDST1_SRC_SEL__CONSTFRAME5, Unit extdst1 input port src
+ * is connected to output of unit constframe5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME5 0x12U
+/* Field Value: EXTDST1_SRC_SEL__MATRIX4, Unit extdst1 input port src is connected
+ * to output of unit matrix4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__MATRIX4 0x23U
+/* Field Value: EXTDST1_SRC_SEL__HSCALER4, Unit extdst1 input port src is
+ * connected to output of unit hscaler4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__HSCALER4 0x24U
+/* Field Value: EXTDST1_SRC_SEL__VSCALER4, Unit extdst1 input port src is
+ * connected to output of unit vscaler4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__VSCALER4 0x25U
+/* Field Value: EXTDST1_SRC_SEL__EXTSRC4, Unit extdst1 input port src is connected
+ * to output of unit extsrc4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__EXTSRC4 0x14U
+/* Field Value: EXTDST1_SRC_SEL__MATRIX5, Unit extdst1 input port src is connected
+ * to output of unit matrix5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__MATRIX5 0x28U
+/* Field Value: EXTDST1_SRC_SEL__HSCALER5, Unit extdst1 input port src is
+ * connected to output of unit hscaler5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__HSCALER5 0x29U
+/* Field Value: EXTDST1_SRC_SEL__VSCALER5, Unit extdst1 input port src is
+ * connected to output of unit vscaler5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__VSCALER5 0x2AU
+/* Field Value: EXTDST1_SRC_SEL__EXTSRC5, Unit extdst1 input port src is connected
+ * to output of unit extsrc5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__EXTSRC5 0x16U
+/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND6, Unit extdst1 input port src
+ * is connected to output of unit layerblend6  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND6 0x32U
+/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND5, Unit extdst1 input port src
+ * is connected to output of unit layerblend5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND5 0x31U
+/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND4, Unit extdst1 input port src
+ * is connected to output of unit layerblend4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND4 0x30U
+/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND3, Unit extdst1 input port src
+ * is connected to output of unit layerblend3  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND3 0x2FU
+/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND2, Unit extdst1 input port src
+ * is connected to output of unit layerblend2  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND2 0x2EU
+/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND1, Unit extdst1 input port src
+ * is connected to output of unit layerblend1  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND1 0x2DU
+/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND0, Unit extdst1 input port src
+ * is connected to output of unit layerblend0  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND0 0x2CU
+
+/* Register: IMXDPUV1_pixengcfg_extdst1_Request */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST                   ((uint32_t)(0xA10))
+#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_OFFSET            ((uint32_t)(0x210))
+#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_RESET_VALUE       0U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SEL_SHDLDREQ_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SEL_SHDLDREQ_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SHDLDREQ_MASK 0x3FFFFEU
+#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SHDLDREQ_SHIFT 1U
+
+/* Register: IMXDPUV1_pixengcfg_extdst1_Trigger */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER                   ((uint32_t)(0xA14))
+#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_OFFSET            ((uint32_t)(0x214))
+#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_RESET_VALUE       0U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_RESET_MASK        0xFFFFFFEEU
+#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_SYNC_TRIGGER_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_SYNC_TRIGGER_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U
+
+/* Register: IMXDPUV1_pixengcfg_extdst1_Status */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS                    ((uint32_t)(0xA18))
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_OFFSET             ((uint32_t)(0x218))
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_RESET_VALUE        0U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS_MASK 0x3U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS_SHIFT 0U
+/* Field Value: EXTDST1_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst1
+ * is empty  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__EMPTY 0U
+/* Field Value: EXTDST1_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst1
+ * is currently processing one operation  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__RUNNING 0x1U
+/* Field Value: EXTDST1_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with
+ * endpoint extdst1 is currently processing one operation with a second
+ * one already kicked to be processed afterwards  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U
+/* Field Value: EXTDST1_PIPELINE_STATUS__RESERVED, reserved  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__RESERVED 0x3U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY_SHIFT 8U
+/* Field Value: EXTDST1_SYNC_BUSY__IDLE, extdst1 synchronizer is idle  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY__IDLE 0U
+/* Field Value: EXTDST1_SYNC_BUSY__BUSY, extdst1 synchronizer is busy  */
+#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY__BUSY 0x1U
+
+/* Register: IMXDPUV1_pixengcfg_constframe5_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK            ((uint32_t)(0xA20))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_OFFSET     ((uint32_t)(0x220))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_RESET_MASK 0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK_SHIFT 0U
+/* Field Value: CONSTFRAME5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset
+ * counter value is 1.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: CONSTFRAME5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock
+ * counter. Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: CONSTFRAME5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: CONSTFRAME5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege
+ * protection.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: CONSTFRAME5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_constframe5_LockStatus */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS            ((uint32_t)(0xA24))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_OFFSET     ((uint32_t)(0x224))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_constframe5_Status */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS                ((uint32_t)(0xA28))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_OFFSET         ((uint32_t)(0x228))
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_RESET_MASK     0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL_SHIFT 16U
+/* Field Value: CONSTFRAME5_SEL__STORE9, constframe5 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__STORE9 0x1U
+/* Field Value: CONSTFRAME5_SEL__EXTDST0, constframe5 module is used from
+ * extdst0 processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST0 0x2U
+/* Field Value: CONSTFRAME5_SEL__EXTDST4, constframe5 module is used from
+ * extdst4 processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST4 0x3U
+/* Field Value: CONSTFRAME5_SEL__EXTDST1, constframe5 module is used from
+ * extdst1 processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST1 0x4U
+/* Field Value: CONSTFRAME5_SEL__EXTDST5, constframe5 module is used from
+ * extdst5 processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST5 0x5U
+/* Field Value: CONSTFRAME5_SEL__STORE4, constframe5 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__STORE4 0x6U
+/* Field Value: CONSTFRAME5_SEL__STORE5, constframe5 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__STORE5 0x7U
+/* Field Value: CONSTFRAME5_SEL__DISABLE, constframe5 module is not used  */
+#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_extdst5_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK                ((uint32_t)(0xA40))
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_OFFSET         ((uint32_t)(0x240))
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_RESET_MASK     0U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK_SHIFT 0U
+/* Field Value: EXTDST5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset counter
+ * value is 1.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: EXTDST5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: EXTDST5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: EXTDST5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: EXTDST5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_extdst5_LockStatus */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS                ((uint32_t)(0xA44))
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_OFFSET         ((uint32_t)(0x244))
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_extdst5_Static */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC                    ((uint32_t)(0xA48))
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_OFFSET             ((uint32_t)(0x248))
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_RESET_VALUE        0x800010U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SHDEN_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SHDEN_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_POWERDOWN_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_POWERDOWN_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE_SHIFT 8U
+/* Field Value: EXTDST5_SYNC_MODE__SINGLE, Reconfig pipeline after explicit
+ * trigger  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE__SINGLE 0U
+/* Field Value: EXTDST5_SYNC_MODE__AUTO, Reconfig pipeline after every kick
+ * when idle  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE__AUTO 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET_MASK 0x800U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET_SHIFT 11U
+/* Field Value: EXTDST5_SW_RESET__OPERATION, Normal Operation  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET__OPERATION 0U
+/* Field Value: EXTDST5_SW_RESET__SWRESET, Software Reset  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET__SWRESET 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_DIV_MASK   0xFF0000U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_DIV_SHIFT  16U
+
+/* Register: IMXDPUV1_pixengcfg_extdst5_Dynamic */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC                   ((uint32_t)(0xA4C))
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_OFFSET            ((uint32_t)(0x24C))
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_RESET_VALUE       0x31U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL_SHIFT 0U
+/* Field Value: EXTDST5_SRC_SEL__DISABLE, Unit extdst5 input port src is disabled  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__DISABLE 0U
+/* Field Value: EXTDST5_SRC_SEL__BLITBLEND9, Unit extdst5 input port src is
+ * connected to output of unit blitblend9  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__BLITBLEND9 0xAU
+/* Field Value: EXTDST5_SRC_SEL__CONSTFRAME0, Unit extdst5 input port src
+ * is connected to output of unit constframe0  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME0 0xCU
+/* Field Value: EXTDST5_SRC_SEL__CONSTFRAME1, Unit extdst5 input port src
+ * is connected to output of unit constframe1  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME1 0x10U
+/* Field Value: EXTDST5_SRC_SEL__CONSTFRAME4, Unit extdst5 input port src
+ * is connected to output of unit constframe4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME4 0xEU
+/* Field Value: EXTDST5_SRC_SEL__CONSTFRAME5, Unit extdst5 input port src
+ * is connected to output of unit constframe5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME5 0x12U
+/* Field Value: EXTDST5_SRC_SEL__MATRIX4, Unit extdst5 input port src is connected
+ * to output of unit matrix4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__MATRIX4 0x23U
+/* Field Value: EXTDST5_SRC_SEL__HSCALER4, Unit extdst5 input port src is
+ * connected to output of unit hscaler4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__HSCALER4 0x24U
+/* Field Value: EXTDST5_SRC_SEL__VSCALER4, Unit extdst5 input port src is
+ * connected to output of unit vscaler4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__VSCALER4 0x25U
+/* Field Value: EXTDST5_SRC_SEL__MATRIX5, Unit extdst5 input port src is connected
+ * to output of unit matrix5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__MATRIX5 0x28U
+/* Field Value: EXTDST5_SRC_SEL__HSCALER5, Unit extdst5 input port src is
+ * connected to output of unit hscaler5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__HSCALER5 0x29U
+/* Field Value: EXTDST5_SRC_SEL__VSCALER5, Unit extdst5 input port src is
+ * connected to output of unit vscaler5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__VSCALER5 0x2AU
+/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND6, Unit extdst5 input port src
+ * is connected to output of unit layerblend6  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND6 0x32U
+/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND5, Unit extdst5 input port src
+ * is connected to output of unit layerblend5  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND5 0x31U
+/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND4, Unit extdst5 input port src
+ * is connected to output of unit layerblend4  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND4 0x30U
+/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND3, Unit extdst5 input port src
+ * is connected to output of unit layerblend3  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND3 0x2FU
+/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND2, Unit extdst5 input port src
+ * is connected to output of unit layerblend2  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND2 0x2EU
+/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND1, Unit extdst5 input port src
+ * is connected to output of unit layerblend1  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND1 0x2DU
+/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND0, Unit extdst5 input port src
+ * is connected to output of unit layerblend0  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND0 0x2CU
+
+/* Register: IMXDPUV1_pixengcfg_extdst5_Request */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST                   ((uint32_t)(0xA50))
+#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_OFFSET            ((uint32_t)(0x250))
+#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_RESET_VALUE       0U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SEL_SHDLDREQ_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SEL_SHDLDREQ_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SHDLDREQ_MASK 0x3FFFFEU
+#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SHDLDREQ_SHIFT 1U
+
+/* Register: IMXDPUV1_pixengcfg_extdst5_Trigger */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER                   ((uint32_t)(0xA54))
+#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_OFFSET            ((uint32_t)(0x254))
+#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_RESET_VALUE       0U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_RESET_MASK        0xFFFFFFEEU
+#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_SYNC_TRIGGER_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_SYNC_TRIGGER_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U
+
+/* Register: IMXDPUV1_pixengcfg_extdst5_Status */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS                    ((uint32_t)(0xA58))
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_OFFSET             ((uint32_t)(0x258))
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_RESET_VALUE        0U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS_MASK 0x3U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS_SHIFT 0U
+/* Field Value: EXTDST5_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst5
+ * is empty  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__EMPTY 0U
+/* Field Value: EXTDST5_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst5
+ * is currently processing one operation  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__RUNNING 0x1U
+/* Field Value: EXTDST5_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with
+ * endpoint extdst5 is currently processing one operation with a second
+ * one already kicked to be processed afterwards  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U
+/* Field Value: EXTDST5_PIPELINE_STATUS__RESERVED, reserved  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__RESERVED 0x3U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY_SHIFT 8U
+/* Field Value: EXTDST5_SYNC_BUSY__IDLE, extdst5 synchronizer is idle  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY__IDLE 0U
+/* Field Value: EXTDST5_SYNC_BUSY__BUSY, extdst5 synchronizer is busy  */
+#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY__BUSY 0x1U
+
+/* Register: IMXDPUV1_pixengcfg_fetchwarp2_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK             ((uint32_t)(0xA60))
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_OFFSET      ((uint32_t)(0x260))
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_RESET_MASK  0U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK_SHIFT 0U
+/* Field Value: FETCHWARP2_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset
+ * counter value is 1.  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: FETCHWARP2_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: FETCHWARP2_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: FETCHWARP2_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege
+ * protection.  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: FETCHWARP2_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_fetchwarp2_LockStatus */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS             ((uint32_t)(0xA64))
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_OFFSET      ((uint32_t)(0x264))
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_fetchwarp2_Dynamic */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC                ((uint32_t)(0xA68))
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_OFFSET         ((uint32_t)(0x268))
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL_SHIFT 0U
+/* Field Value: FETCHWARP2_SRC_SEL__DISABLE, Unit fetchwarp2 input port src
+ * is disabled  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL__DISABLE 0U
+/* Field Value: FETCHWARP2_SRC_SEL__FETCHECO2, Unit fetchwarp2 input port
+ * src is connected to output of unit fetcheco2  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL__FETCHECO2 0x1BU
+
+/* Register: IMXDPUV1_pixengcfg_fetchwarp2_Status */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS                 ((uint32_t)(0xA6C))
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_OFFSET          ((uint32_t)(0x26C))
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_RESET_VALUE     0U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_RESET_MASK      0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL_SHIFT 16U
+/* Field Value: FETCHWARP2_SEL__STORE9, fetchwarp2 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__STORE9 0x1U
+/* Field Value: FETCHWARP2_SEL__EXTDST0, fetchwarp2 module is used from extdst0
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST0 0x2U
+/* Field Value: FETCHWARP2_SEL__EXTDST4, fetchwarp2 module is used from extdst4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST4 0x3U
+/* Field Value: FETCHWARP2_SEL__EXTDST1, fetchwarp2 module is used from extdst1
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST1 0x4U
+/* Field Value: FETCHWARP2_SEL__EXTDST5, fetchwarp2 module is used from extdst5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST5 0x5U
+/* Field Value: FETCHWARP2_SEL__STORE4, fetchwarp2 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__STORE4 0x6U
+/* Field Value: FETCHWARP2_SEL__STORE5, fetchwarp2 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__STORE5 0x7U
+/* Field Value: FETCHWARP2_SEL__DISABLE, fetchwarp2 module is not used  */
+#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_fetcheco2_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK              ((uint32_t)(0xA70))
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_OFFSET       ((uint32_t)(0x270))
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_RESET_VALUE  0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_RESET_MASK   0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK_SHIFT 0U
+/* Field Value: FETCHECO2_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset
+ * counter value is 1.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: FETCHECO2_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: FETCHECO2_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: FETCHECO2_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege
+ * protection.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: FETCHECO2_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_fetcheco2_LockStatus */
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS              ((uint32_t)(0xA74))
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_OFFSET       ((uint32_t)(0x274))
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_RESET_VALUE  0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_fetcheco2_Status */
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS                  ((uint32_t)(0xA78))
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_OFFSET           ((uint32_t)(0x278))
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_RESET_VALUE      0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_RESET_MASK       0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL_SHIFT 16U
+/* Field Value: FETCHECO2_SEL__STORE9, fetcheco2 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__STORE9 0x1U
+/* Field Value: FETCHECO2_SEL__EXTDST0, fetcheco2 module is used from extdst0
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST0 0x2U
+/* Field Value: FETCHECO2_SEL__EXTDST4, fetcheco2 module is used from extdst4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST4 0x3U
+/* Field Value: FETCHECO2_SEL__EXTDST1, fetcheco2 module is used from extdst1
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST1 0x4U
+/* Field Value: FETCHECO2_SEL__EXTDST5, fetcheco2 module is used from extdst5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST5 0x5U
+/* Field Value: FETCHECO2_SEL__STORE4, fetcheco2 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__STORE4 0x6U
+/* Field Value: FETCHECO2_SEL__STORE5, fetcheco2 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__STORE5 0x7U
+/* Field Value: FETCHECO2_SEL__DISABLE, fetcheco2 module is not used  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_fetchdecode0_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK           ((uint32_t)(0xA80))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_OFFSET    ((uint32_t)(0x280))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_RESET_MASK 0U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK_SHIFT 0U
+/* Field Value: FETCHDECODE0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset
+ * counter value is 1.  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: FETCHDECODE0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock
+ * counter. Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: FETCHDECODE0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege
+ * protection. Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: FETCHDECODE0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege
+ * protection.  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: FETCHDECODE0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_fetchdecode0_LockStatus */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS           ((uint32_t)(0xA84))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_OFFSET    ((uint32_t)(0x284))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_fetchdecode0_Dynamic */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC              ((uint32_t)(0xA88))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_OFFSET       ((uint32_t)(0x288))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_RESET_VALUE  0U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL_SHIFT 0U
+/* Field Value: FETCHDECODE0_SRC_SEL__DISABLE, Unit fetchdecode0 input port
+ * src is disabled  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL__DISABLE 0U
+/* Field Value: FETCHDECODE0_SRC_SEL__FETCHECO0, Unit fetchdecode0 input port
+ * src is connected to output of unit fetcheco0  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL__FETCHECO0 0x1DU
+/* Field Value: FETCHDECODE0_SRC_SEL__FETCHDECODE2, Unit fetchdecode0 input
+ * port src is connected to output of unit fetchdecode2  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL__FETCHDECODE2 0x18U
+
+/* Register: IMXDPUV1_pixengcfg_fetchdecode0_Status */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS               ((uint32_t)(0xA8C))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_OFFSET        ((uint32_t)(0x28C))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_RESET_VALUE   0U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_RESET_MASK    0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL_SHIFT 16U
+/* Field Value: FETCHDECODE0_SEL__STORE9, fetchdecode0 module is used from
+ * store9 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__STORE9 0x1U
+/* Field Value: FETCHDECODE0_SEL__EXTDST0, fetchdecode0 module is used from
+ * extdst0 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST0 0x2U
+/* Field Value: FETCHDECODE0_SEL__EXTDST4, fetchdecode0 module is used from
+ * extdst4 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST4 0x3U
+/* Field Value: FETCHDECODE0_SEL__EXTDST1, fetchdecode0 module is used from
+ * extdst1 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST1 0x4U
+/* Field Value: FETCHDECODE0_SEL__EXTDST5, fetchdecode0 module is used from
+ * extdst5 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST5 0x5U
+/* Field Value: FETCHDECODE0_SEL__STORE4, fetchdecode0 module is used from
+ * store4 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__STORE4 0x6U
+/* Field Value: FETCHDECODE0_SEL__STORE5, fetchdecode0 module is used from
+ * store5 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__STORE5 0x7U
+/* Field Value: FETCHDECODE0_SEL__DISABLE, fetchdecode0 module is not used  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_fetcheco0_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK              ((uint32_t)(0xA90))
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_OFFSET       ((uint32_t)(0x290))
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_RESET_VALUE  0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_RESET_MASK   0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK_SHIFT 0U
+/* Field Value: FETCHECO0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset
+ * counter value is 1.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: FETCHECO0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: FETCHECO0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: FETCHECO0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege
+ * protection.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: FETCHECO0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_fetcheco0_LockStatus */
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS              ((uint32_t)(0xA94))
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_OFFSET       ((uint32_t)(0x294))
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_RESET_VALUE  0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_fetcheco0_Status */
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS                  ((uint32_t)(0xA98))
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_OFFSET           ((uint32_t)(0x298))
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_RESET_VALUE      0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_RESET_MASK       0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL_SHIFT 16U
+/* Field Value: FETCHECO0_SEL__STORE9, fetcheco0 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__STORE9 0x1U
+/* Field Value: FETCHECO0_SEL__EXTDST0, fetcheco0 module is used from extdst0
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST0 0x2U
+/* Field Value: FETCHECO0_SEL__EXTDST4, fetcheco0 module is used from extdst4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST4 0x3U
+/* Field Value: FETCHECO0_SEL__EXTDST1, fetcheco0 module is used from extdst1
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST1 0x4U
+/* Field Value: FETCHECO0_SEL__EXTDST5, fetcheco0 module is used from extdst5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST5 0x5U
+/* Field Value: FETCHECO0_SEL__STORE4, fetcheco0 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__STORE4 0x6U
+/* Field Value: FETCHECO0_SEL__STORE5, fetcheco0 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__STORE5 0x7U
+/* Field Value: FETCHECO0_SEL__DISABLE, fetcheco0 module is not used  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_fetchdecode1_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK           ((uint32_t)(0xAA0))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_OFFSET    ((uint32_t)(0x2A0))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_RESET_MASK 0U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK_SHIFT 0U
+/* Field Value: FETCHDECODE1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset
+ * counter value is 1.  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: FETCHDECODE1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock
+ * counter. Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: FETCHDECODE1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege
+ * protection. Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: FETCHDECODE1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege
+ * protection.  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: FETCHDECODE1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_fetchdecode1_LockStatus */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS           ((uint32_t)(0xAA4))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_OFFSET    ((uint32_t)(0x2A4))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_fetchdecode1_Dynamic */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC              ((uint32_t)(0xAA8))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_OFFSET       ((uint32_t)(0x2A8))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_RESET_VALUE  0U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL_SHIFT 0U
+/* Field Value: FETCHDECODE1_SRC_SEL__DISABLE, Unit fetchdecode1 input port
+ * src is disabled  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL__DISABLE 0U
+/* Field Value: FETCHDECODE1_SRC_SEL__FETCHECO1, Unit fetchdecode1 input port
+ * src is connected to output of unit fetcheco1  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL__FETCHECO1 0x1FU
+/* Field Value: FETCHDECODE1_SRC_SEL__FETCHDECODE3, Unit fetchdecode1 input
+ * port src is connected to output of unit fetchdecode3  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL__FETCHDECODE3 0x19U
+
+/* Register: IMXDPUV1_pixengcfg_fetchdecode1_Status */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS               ((uint32_t)(0xAAC))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_OFFSET        ((uint32_t)(0x2AC))
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_RESET_VALUE   0U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_RESET_MASK    0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL_SHIFT 16U
+/* Field Value: FETCHDECODE1_SEL__STORE9, fetchdecode1 module is used from
+ * store9 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__STORE9 0x1U
+/* Field Value: FETCHDECODE1_SEL__EXTDST0, fetchdecode1 module is used from
+ * extdst0 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST0 0x2U
+/* Field Value: FETCHDECODE1_SEL__EXTDST4, fetchdecode1 module is used from
+ * extdst4 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST4 0x3U
+/* Field Value: FETCHDECODE1_SEL__EXTDST1, fetchdecode1 module is used from
+ * extdst1 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST1 0x4U
+/* Field Value: FETCHDECODE1_SEL__EXTDST5, fetchdecode1 module is used from
+ * extdst5 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST5 0x5U
+/* Field Value: FETCHDECODE1_SEL__STORE4, fetchdecode1 module is used from
+ * store4 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__STORE4 0x6U
+/* Field Value: FETCHDECODE1_SEL__STORE5, fetchdecode1 module is used from
+ * store5 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__STORE5 0x7U
+/* Field Value: FETCHDECODE1_SEL__DISABLE, fetchdecode1 module is not used  */
+#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_fetcheco1_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK              ((uint32_t)(0xAB0))
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_OFFSET       ((uint32_t)(0x2B0))
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_RESET_VALUE  0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_RESET_MASK   0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK_SHIFT 0U
+/* Field Value: FETCHECO1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset
+ * counter value is 1.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: FETCHECO1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: FETCHECO1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: FETCHECO1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege
+ * protection.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: FETCHECO1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_fetcheco1_LockStatus */
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS              ((uint32_t)(0xAB4))
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_OFFSET       ((uint32_t)(0x2B4))
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_RESET_VALUE  0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_fetcheco1_Status */
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS                  ((uint32_t)(0xAB8))
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_OFFSET           ((uint32_t)(0x2B8))
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_RESET_VALUE      0U
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_RESET_MASK       0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL_SHIFT 16U
+/* Field Value: FETCHECO1_SEL__STORE9, fetcheco1 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__STORE9 0x1U
+/* Field Value: FETCHECO1_SEL__EXTDST0, fetcheco1 module is used from extdst0
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST0 0x2U
+/* Field Value: FETCHECO1_SEL__EXTDST4, fetcheco1 module is used from extdst4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST4 0x3U
+/* Field Value: FETCHECO1_SEL__EXTDST1, fetcheco1 module is used from extdst1
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST1 0x4U
+/* Field Value: FETCHECO1_SEL__EXTDST5, fetcheco1 module is used from extdst5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST5 0x5U
+/* Field Value: FETCHECO1_SEL__STORE4, fetcheco1 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__STORE4 0x6U
+/* Field Value: FETCHECO1_SEL__STORE5, fetcheco1 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__STORE5 0x7U
+/* Field Value: FETCHECO1_SEL__DISABLE, fetcheco1 module is not used  */
+#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_fetchlayer0_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK            ((uint32_t)(0xAC0))
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_OFFSET     ((uint32_t)(0x2C0))
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_RESET_MASK 0U
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK_SHIFT 0U
+/* Field Value: FETCHLAYER0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset
+ * counter value is 1.  */
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: FETCHLAYER0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock
+ * counter. Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: FETCHLAYER0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: FETCHLAYER0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege
+ * protection.  */
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: FETCHLAYER0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_fetchlayer0_LockStatus */
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS            ((uint32_t)(0xAC4))
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_OFFSET     ((uint32_t)(0x2C4))
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_fetchlayer0_Status */
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS                ((uint32_t)(0xAC8))
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_OFFSET         ((uint32_t)(0x2C8))
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_RESET_MASK     0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL_SHIFT 16U
+/* Field Value: FETCHLAYER0_SEL__STORE9, fetchlayer0 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__STORE9 0x1U
+/* Field Value: FETCHLAYER0_SEL__EXTDST0, fetchlayer0 module is used from
+ * extdst0 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST0 0x2U
+/* Field Value: FETCHLAYER0_SEL__EXTDST4, fetchlayer0 module is used from
+ * extdst4 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST4 0x3U
+/* Field Value: FETCHLAYER0_SEL__EXTDST1, fetchlayer0 module is used from
+ * extdst1 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST1 0x4U
+/* Field Value: FETCHLAYER0_SEL__EXTDST5, fetchlayer0 module is used from
+ * extdst5 processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST5 0x5U
+/* Field Value: FETCHLAYER0_SEL__STORE4, fetchlayer0 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__STORE4 0x6U
+/* Field Value: FETCHLAYER0_SEL__STORE5, fetchlayer0 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__STORE5 0x7U
+/* Field Value: FETCHLAYER0_SEL__DISABLE, fetchlayer0 module is not used  */
+#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_matrix4_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK                ((uint32_t)(0xAE0))
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_OFFSET         ((uint32_t)(0x2E0))
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_RESET_MASK     0U
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK_SHIFT 0U
+/* Field Value: MATRIX4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset counter
+ * value is 1.  */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: MATRIX4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: MATRIX4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: MATRIX4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: MATRIX4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_matrix4_LockStatus */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS                ((uint32_t)(0xAE4))
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_OFFSET         ((uint32_t)(0x2E4))
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_matrix4_Dynamic */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC                   ((uint32_t)(0xAE8))
+#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_OFFSET            ((uint32_t)(0x2E8))
+#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_RESET_VALUE       0x1000000U
+#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL_SHIFT 0U
+/* Field Value: MATRIX4_SRC_SEL__DISABLE, Unit matrix4 input port src is disabled  */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL__DISABLE 0U
+/* Field Value: MATRIX4_SRC_SEL__GAMMACOR4, Unit matrix4 input port src is
+ * connected to output of unit gammacor4  */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL__GAMMACOR4 0x22U
+#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN_MASK 0x3000000U
+#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN_SHIFT 24U
+/* Field Value: MATRIX4_CLKEN__DISABLE, Clock for matrix4 is disabled  */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN__DISABLE 0U
+/* Field Value: MATRIX4_CLKEN__AUTOMATIC, Clock is enabled if unit is used,
+ * frequency is defined by the register setting for this pipeline (see
+ * [endpoint_name]_Static register)  */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN__AUTOMATIC 0x1U
+/* Field Value: MATRIX4_CLKEN__FULL, Clock for matrix4 is without gating  */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN__FULL 0x3U
+
+/* Register: IMXDPUV1_pixengcfg_matrix4_Status */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS                    ((uint32_t)(0xAEC))
+#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_OFFSET             ((uint32_t)(0x2EC))
+#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_RESET_VALUE        0U
+#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_RESET_MASK         0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL_MASK   0x70000U
+#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL_SHIFT  16U
+/* Field Value: MATRIX4_SEL__STORE9, matrix4 module is used from store9 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__STORE9 0x1U
+/* Field Value: MATRIX4_SEL__EXTDST0, matrix4 module is used from extdst0
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST0 0x2U
+/* Field Value: MATRIX4_SEL__EXTDST4, matrix4 module is used from extdst4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST4 0x3U
+/* Field Value: MATRIX4_SEL__EXTDST1, matrix4 module is used from extdst1
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST1 0x4U
+/* Field Value: MATRIX4_SEL__EXTDST5, matrix4 module is used from extdst5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST5 0x5U
+/* Field Value: MATRIX4_SEL__STORE4, matrix4 module is used from store4 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__STORE4 0x6U
+/* Field Value: MATRIX4_SEL__STORE5, matrix4 module is used from store5 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__STORE5 0x7U
+/* Field Value: MATRIX4_SEL__DISABLE, matrix4 module is not used  */
+#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_hscaler4_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK               ((uint32_t)(0xB00))
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_OFFSET        ((uint32_t)(0x300))
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_RESET_VALUE   0U
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_RESET_MASK    0U
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK_SHIFT 0U
+/* Field Value: HSCALER4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset counter
+ * value is 1.  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: HSCALER4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: HSCALER4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: HSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: HSCALER4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_hscaler4_LockStatus */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS               ((uint32_t)(0xB04))
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_OFFSET        ((uint32_t)(0x304))
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_RESET_VALUE   0U
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_hscaler4_Dynamic */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC                  ((uint32_t)(0xB08))
+#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_OFFSET           ((uint32_t)(0x308))
+#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_RESET_VALUE      0x1000000U
+#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL_SHIFT 0U
+/* Field Value: HSCALER4_SRC_SEL__DISABLE, Unit hscaler4 input port src is
+ * disabled  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__DISABLE 0U
+/* Field Value: HSCALER4_SRC_SEL__EXTSRC4, Unit hscaler4 input port src is
+ * connected to output of unit extsrc4  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__EXTSRC4 0x14U
+/* Field Value: HSCALER4_SRC_SEL__FETCHDECODE0, Unit hscaler4 input port src
+ * is connected to output of unit fetchdecode0  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__FETCHDECODE0 0x1CU
+/* Field Value: HSCALER4_SRC_SEL__FETCHDECODE2, Unit hscaler4 input port src
+ * is connected to output of unit fetchdecode2  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__FETCHDECODE2 0x18U
+/* Field Value: HSCALER4_SRC_SEL__MATRIX4, Unit hscaler4 input port src is
+ * connected to output of unit matrix4  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__MATRIX4 0x23U
+/* Field Value: HSCALER4_SRC_SEL__VSCALER4, Unit hscaler4 input port src is
+ * connected to output of unit vscaler4  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__VSCALER4 0x25U
+#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN_MASK 0x3000000U
+#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN_SHIFT 24U
+/* Field Value: HSCALER4_CLKEN__DISABLE, Clock for hscaler4 is disabled  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN__DISABLE 0U
+/* Field Value: HSCALER4_CLKEN__AUTOMATIC, Clock is enabled if unit is used,
+ * frequency is defined by the register setting for this pipeline (see
+ * [endpoint_name]_Static register)  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN__AUTOMATIC 0x1U
+/* Field Value: HSCALER4_CLKEN__FULL, Clock for hscaler4 is without gating  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN__FULL 0x3U
+
+/* Register: IMXDPUV1_pixengcfg_hscaler4_Status */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS                   ((uint32_t)(0xB0C))
+#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_OFFSET            ((uint32_t)(0x30C))
+#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_RESET_VALUE       0U
+#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_RESET_MASK        0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL_SHIFT 16U
+/* Field Value: HSCALER4_SEL__STORE9, hscaler4 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__STORE9 0x1U
+/* Field Value: HSCALER4_SEL__EXTDST0, hscaler4 module is used from extdst0
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST0 0x2U
+/* Field Value: HSCALER4_SEL__EXTDST4, hscaler4 module is used from extdst4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST4 0x3U
+/* Field Value: HSCALER4_SEL__EXTDST1, hscaler4 module is used from extdst1
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST1 0x4U
+/* Field Value: HSCALER4_SEL__EXTDST5, hscaler4 module is used from extdst5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST5 0x5U
+/* Field Value: HSCALER4_SEL__STORE4, hscaler4 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__STORE4 0x6U
+/* Field Value: HSCALER4_SEL__STORE5, hscaler4 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__STORE5 0x7U
+/* Field Value: HSCALER4_SEL__DISABLE, hscaler4 module is not used  */
+#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_vscaler4_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK               ((uint32_t)(0xB20))
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_OFFSET        ((uint32_t)(0x320))
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_RESET_VALUE   0U
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_RESET_MASK    0U
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK_SHIFT 0U
+/* Field Value: VSCALER4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset counter
+ * value is 1.  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: VSCALER4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: VSCALER4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: VSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: VSCALER4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_vscaler4_LockStatus */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS               ((uint32_t)(0xB24))
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_OFFSET        ((uint32_t)(0x324))
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_RESET_VALUE   0U
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_vscaler4_Dynamic */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC                  ((uint32_t)(0xB28))
+#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_OFFSET           ((uint32_t)(0x328))
+#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_RESET_VALUE      0x1000000U
+#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL_SHIFT 0U
+/* Field Value: VSCALER4_SRC_SEL__DISABLE, Unit vscaler4 input port src is
+ * disabled  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__DISABLE 0U
+/* Field Value: VSCALER4_SRC_SEL__EXTSRC4, Unit vscaler4 input port src is
+ * connected to output of unit extsrc4  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__EXTSRC4 0x14U
+/* Field Value: VSCALER4_SRC_SEL__FETCHDECODE0, Unit vscaler4 input port src
+ * is connected to output of unit fetchdecode0  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__FETCHDECODE0 0x1CU
+/* Field Value: VSCALER4_SRC_SEL__FETCHDECODE2, Unit vscaler4 input port src
+ * is connected to output of unit fetchdecode2  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__FETCHDECODE2 0x18U
+/* Field Value: VSCALER4_SRC_SEL__HSCALER4, Unit vscaler4 input port src is
+ * connected to output of unit hscaler4  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__HSCALER4 0x24U
+/* Field Value: VSCALER4_SRC_SEL__MATRIX4, Unit vscaler4 input port src is
+ * connected to output of unit matrix4  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__MATRIX4 0x23U
+#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN_MASK 0x3000000U
+#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN_SHIFT 24U
+/* Field Value: VSCALER4_CLKEN__DISABLE, Clock for vscaler4 is disabled  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN__DISABLE 0U
+/* Field Value: VSCALER4_CLKEN__AUTOMATIC, Clock is enabled if unit is used,
+ * frequency is defined by the register setting for this pipeline (see
+ * [endpoint_name]_Static register)  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN__AUTOMATIC 0x1U
+/* Field Value: VSCALER4_CLKEN__FULL, Clock for vscaler4 is without gating  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN__FULL 0x3U
+
+/* Register: IMXDPUV1_pixengcfg_vscaler4_Status */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS                   ((uint32_t)(0xB2C))
+#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_OFFSET            ((uint32_t)(0x32C))
+#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_RESET_VALUE       0U
+#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_RESET_MASK        0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL_SHIFT 16U
+/* Field Value: VSCALER4_SEL__STORE9, vscaler4 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__STORE9 0x1U
+/* Field Value: VSCALER4_SEL__EXTDST0, vscaler4 module is used from extdst0
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST0 0x2U
+/* Field Value: VSCALER4_SEL__EXTDST4, vscaler4 module is used from extdst4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST4 0x3U
+/* Field Value: VSCALER4_SEL__EXTDST1, vscaler4 module is used from extdst1
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST1 0x4U
+/* Field Value: VSCALER4_SEL__EXTDST5, vscaler4 module is used from extdst5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST5 0x5U
+/* Field Value: VSCALER4_SEL__STORE4, vscaler4 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__STORE4 0x6U
+/* Field Value: VSCALER4_SEL__STORE5, vscaler4 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__STORE5 0x7U
+/* Field Value: VSCALER4_SEL__DISABLE, vscaler4 module is not used  */
+#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_matrix5_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK                ((uint32_t)(0xB40))
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_OFFSET         ((uint32_t)(0x340))
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_RESET_MASK     0U
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK_SHIFT 0U
+/* Field Value: MATRIX5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset counter
+ * value is 1.  */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: MATRIX5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: MATRIX5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: MATRIX5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: MATRIX5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_matrix5_LockStatus */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS                ((uint32_t)(0xB44))
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_OFFSET         ((uint32_t)(0x344))
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_matrix5_Dynamic */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC                   ((uint32_t)(0xB48))
+#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_OFFSET            ((uint32_t)(0x348))
+#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_RESET_VALUE       0x1000000U
+#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_SRC_SEL_SHIFT 0U
+/* Field Value: MATRIX5_SRC_SEL__DISABLE, Unit matrix5 input port src is disabled  */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_SRC_SEL__DISABLE 0U
+/* Field Value: MATRIX5_SRC_SEL__GAMMACOR5, Unit matrix5 input port src is
+ * connected to output of unit gammacor5  */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_SRC_SEL__GAMMACOR5 0x27U
+#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN_MASK 0x3000000U
+#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN_SHIFT 24U
+/* Field Value: MATRIX5_CLKEN__DISABLE, Clock for matrix5 is disabled  */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN__DISABLE 0U
+/* Field Value: MATRIX5_CLKEN__AUTOMATIC, Clock is enabled if unit is used,
+ * frequency is defined by the register setting for this pipeline (see
+ * [endpoint_name]_Static register)  */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN__AUTOMATIC 0x1U
+/* Field Value: MATRIX5_CLKEN__FULL, Clock for matrix5 is without gating  */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN__FULL 0x3U
+
+/* Register: IMXDPUV1_pixengcfg_matrix5_Status */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS                    ((uint32_t)(0xB4C))
+#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_OFFSET             ((uint32_t)(0x34C))
+#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_RESET_VALUE        0U
+#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_RESET_MASK         0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL_MASK   0x70000U
+#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL_SHIFT  16U
+/* Field Value: MATRIX5_SEL__STORE9, matrix5 module is used from store9 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__STORE9 0x1U
+/* Field Value: MATRIX5_SEL__EXTDST0, matrix5 module is used from extdst0
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__EXTDST0 0x2U
+/* Field Value: MATRIX5_SEL__EXTDST4, matrix5 module is used from extdst4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__EXTDST4 0x3U
+/* Field Value: MATRIX5_SEL__EXTDST1, matrix5 module is used from extdst1
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__EXTDST1 0x4U
+/* Field Value: MATRIX5_SEL__EXTDST5, matrix5 module is used from extdst5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__EXTDST5 0x5U
+/* Field Value: MATRIX5_SEL__STORE4, matrix5 module is used from store4 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__STORE4 0x6U
+/* Field Value: MATRIX5_SEL__STORE5, matrix5 module is used from store5 processing
+ * path  */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__STORE5 0x7U
+/* Field Value: MATRIX5_SEL__DISABLE, matrix5 module is not used  */
+#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_hscaler5_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK               ((uint32_t)(0xB60))
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_OFFSET        ((uint32_t)(0x360))
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_RESET_VALUE   0U
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_RESET_MASK    0U
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK_SHIFT 0U
+/* Field Value: HSCALER5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset counter
+ * value is 1.  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: HSCALER5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: HSCALER5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: HSCALER5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: HSCALER5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_hscaler5_LockStatus */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS               ((uint32_t)(0xB64))
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_OFFSET        ((uint32_t)(0x364))
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_RESET_VALUE   0U
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_hscaler5_Dynamic */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC                  ((uint32_t)(0xB68))
+#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_OFFSET           ((uint32_t)(0x368))
+#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_RESET_VALUE      0x1000000U
+#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL_SHIFT 0U
+/* Field Value: HSCALER5_SRC_SEL__DISABLE, Unit hscaler5 input port src is
+ * disabled  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__DISABLE 0U
+/* Field Value: HSCALER5_SRC_SEL__EXTSRC5, Unit hscaler5 input port src is
+ * connected to output of unit extsrc5  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__EXTSRC5 0x16U
+/* Field Value: HSCALER5_SRC_SEL__FETCHDECODE1, Unit hscaler5 input port src
+ * is connected to output of unit fetchdecode1  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__FETCHDECODE1 0x1EU
+/* Field Value: HSCALER5_SRC_SEL__FETCHDECODE3, Unit hscaler5 input port src
+ * is connected to output of unit fetchdecode3  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__FETCHDECODE3 0x19U
+/* Field Value: HSCALER5_SRC_SEL__MATRIX5, Unit hscaler5 input port src is
+ * connected to output of unit matrix5  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__MATRIX5 0x28U
+/* Field Value: HSCALER5_SRC_SEL__VSCALER5, Unit hscaler5 input port src is
+ * connected to output of unit vscaler5  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__VSCALER5 0x2AU
+#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN_MASK 0x3000000U
+#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN_SHIFT 24U
+/* Field Value: HSCALER5_CLKEN__DISABLE, Clock for hscaler5 is disabled  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN__DISABLE 0U
+/* Field Value: HSCALER5_CLKEN__AUTOMATIC, Clock is enabled if unit is used,
+ * frequency is defined by the register setting for this pipeline (see
+ * [endpoint_name]_Static register)  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN__AUTOMATIC 0x1U
+/* Field Value: HSCALER5_CLKEN__FULL, Clock for hscaler5 is without gating  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN__FULL 0x3U
+
+/* Register: IMXDPUV1_pixengcfg_hscaler5_Status */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS                   ((uint32_t)(0xB6C))
+#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_OFFSET            ((uint32_t)(0x36C))
+#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_RESET_VALUE       0U
+#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_RESET_MASK        0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL_SHIFT 16U
+/* Field Value: HSCALER5_SEL__STORE9, hscaler5 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__STORE9 0x1U
+/* Field Value: HSCALER5_SEL__EXTDST0, hscaler5 module is used from extdst0
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__EXTDST0 0x2U
+/* Field Value: HSCALER5_SEL__EXTDST4, hscaler5 module is used from extdst4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__EXTDST4 0x3U
+/* Field Value: HSCALER5_SEL__EXTDST1, hscaler5 module is used from extdst1
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__EXTDST1 0x4U
+/* Field Value: HSCALER5_SEL__EXTDST5, hscaler5 module is used from extdst5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__EXTDST5 0x5U
+/* Field Value: HSCALER5_SEL__STORE4, hscaler5 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__STORE4 0x6U
+/* Field Value: HSCALER5_SEL__STORE5, hscaler5 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__STORE5 0x7U
+/* Field Value: HSCALER5_SEL__DISABLE, hscaler5 module is not used  */
+#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_vscaler5_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK               ((uint32_t)(0xB80))
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_OFFSET        ((uint32_t)(0x380))
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_RESET_VALUE   0U
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_RESET_MASK    0U
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK_SHIFT 0U
+/* Field Value: VSCALER5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset counter
+ * value is 1.  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: VSCALER5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter.
+ * Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: VSCALER5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: VSCALER5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: VSCALER5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_vscaler5_LockStatus */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS               ((uint32_t)(0xB84))
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_OFFSET        ((uint32_t)(0x384))
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_RESET_VALUE   0U
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_vscaler5_Dynamic */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC                  ((uint32_t)(0xB88))
+#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_OFFSET           ((uint32_t)(0x388))
+#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_RESET_VALUE      0x1000000U
+#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL_SHIFT 0U
+/* Field Value: VSCALER5_SRC_SEL__DISABLE, Unit vscaler5 input port src is
+ * disabled  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__DISABLE 0U
+/* Field Value: VSCALER5_SRC_SEL__EXTSRC5, Unit vscaler5 input port src is
+ * connected to output of unit extsrc5  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__EXTSRC5 0x16U
+/* Field Value: VSCALER5_SRC_SEL__FETCHDECODE1, Unit vscaler5 input port src
+ * is connected to output of unit fetchdecode1  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__FETCHDECODE1 0x1EU
+/* Field Value: VSCALER5_SRC_SEL__FETCHDECODE3, Unit vscaler5 input port src
+ * is connected to output of unit fetchdecode3  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__FETCHDECODE3 0x19U
+/* Field Value: VSCALER5_SRC_SEL__HSCALER5, Unit vscaler5 input port src is
+ * connected to output of unit hscaler5  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__HSCALER5 0x29U
+/* Field Value: VSCALER5_SRC_SEL__MATRIX5, Unit vscaler5 input port src is
+ * connected to output of unit matrix5  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__MATRIX5 0x28U
+#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN_MASK 0x3000000U
+#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN_SHIFT 24U
+/* Field Value: VSCALER5_CLKEN__DISABLE, Clock for vscaler5 is disabled  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN__DISABLE 0U
+/* Field Value: VSCALER5_CLKEN__AUTOMATIC, Clock is enabled if unit is used,
+ * frequency is defined by the register setting for this pipeline (see
+ * [endpoint_name]_Static register)  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN__AUTOMATIC 0x1U
+/* Field Value: VSCALER5_CLKEN__FULL, Clock for vscaler5 is without gating  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN__FULL 0x3U
+
+/* Register: IMXDPUV1_pixengcfg_vscaler5_Status */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS                   ((uint32_t)(0xB8C))
+#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_OFFSET            ((uint32_t)(0x38C))
+#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_RESET_VALUE       0U
+#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_RESET_MASK        0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL_SHIFT 16U
+/* Field Value: VSCALER5_SEL__STORE9, vscaler5 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__STORE9 0x1U
+/* Field Value: VSCALER5_SEL__EXTDST0, vscaler5 module is used from extdst0
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__EXTDST0 0x2U
+/* Field Value: VSCALER5_SEL__EXTDST4, vscaler5 module is used from extdst4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__EXTDST4 0x3U
+/* Field Value: VSCALER5_SEL__EXTDST1, vscaler5 module is used from extdst1
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__EXTDST1 0x4U
+/* Field Value: VSCALER5_SEL__EXTDST5, vscaler5 module is used from extdst5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__EXTDST5 0x5U
+/* Field Value: VSCALER5_SEL__STORE4, vscaler5 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__STORE4 0x6U
+/* Field Value: VSCALER5_SEL__STORE5, vscaler5 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__STORE5 0x7U
+/* Field Value: VSCALER5_SEL__DISABLE, vscaler5 module is not used  */
+#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_layerblend0_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK            ((uint32_t)(0xBA0))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_OFFSET     ((uint32_t)(0x3A0))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_RESET_MASK 0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK_SHIFT 0U
+/* Field Value: LAYERBLEND0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset
+ * counter value is 1.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: LAYERBLEND0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock
+ * counter. Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LAYERBLEND0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LAYERBLEND0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege
+ * protection.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LAYERBLEND0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_layerblend0_LockStatus */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS            ((uint32_t)(0xBA4))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_OFFSET     ((uint32_t)(0x3A4))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_layerblend0_Dynamic */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC               ((uint32_t)(0xBA8))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_OFFSET        ((uint32_t)(0x3A8))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_RESET_VALUE   0x1001C0CU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL_SHIFT 0U
+/* Field Value: LAYERBLEND0_PRIM_SEL__DISABLE, Unit layerblend0 input port
+ * prim is disabled  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__DISABLE 0U
+/* Field Value: LAYERBLEND0_PRIM_SEL__BLITBLEND9, Unit layerblend0 input port
+ * prim is connected to output of unit blitblend9  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__BLITBLEND9 0xAU
+/* Field Value: LAYERBLEND0_PRIM_SEL__CONSTFRAME0, Unit layerblend0 input
+ * port prim is connected to output of unit constframe0  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__CONSTFRAME0 0xCU
+/* Field Value: LAYERBLEND0_PRIM_SEL__CONSTFRAME1, Unit layerblend0 input
+ * port prim is connected to output of unit constframe1  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__CONSTFRAME1 0x10U
+/* Field Value: LAYERBLEND0_PRIM_SEL__CONSTFRAME4, Unit layerblend0 input
+ * port prim is connected to output of unit constframe4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__CONSTFRAME4 0xEU
+/* Field Value: LAYERBLEND0_PRIM_SEL__CONSTFRAME5, Unit layerblend0 input
+ * port prim is connected to output of unit constframe5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__CONSTFRAME5 0x12U
+/* Field Value: LAYERBLEND0_PRIM_SEL__MATRIX4, Unit layerblend0 input port
+ * prim is connected to output of unit matrix4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__MATRIX4 0x23U
+/* Field Value: LAYERBLEND0_PRIM_SEL__HSCALER4, Unit layerblend0 input port
+ * prim is connected to output of unit hscaler4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__HSCALER4 0x24U
+/* Field Value: LAYERBLEND0_PRIM_SEL__VSCALER4, Unit layerblend0 input port
+ * prim is connected to output of unit vscaler4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__VSCALER4 0x25U
+/* Field Value: LAYERBLEND0_PRIM_SEL__EXTSRC4, Unit layerblend0 input port
+ * prim is connected to output of unit extsrc4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__EXTSRC4 0x14U
+/* Field Value: LAYERBLEND0_PRIM_SEL__MATRIX5, Unit layerblend0 input port
+ * prim is connected to output of unit matrix5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__MATRIX5 0x28U
+/* Field Value: LAYERBLEND0_PRIM_SEL__HSCALER5, Unit layerblend0 input port
+ * prim is connected to output of unit hscaler5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__HSCALER5 0x29U
+/* Field Value: LAYERBLEND0_PRIM_SEL__VSCALER5, Unit layerblend0 input port
+ * prim is connected to output of unit vscaler5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__VSCALER5 0x2AU
+/* Field Value: LAYERBLEND0_PRIM_SEL__EXTSRC5, Unit layerblend0 input port
+ * prim is connected to output of unit extsrc5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__EXTSRC5 0x16U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL_MASK 0x3F00U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL_SHIFT 8U
+/* Field Value: LAYERBLEND0_SEC_SEL__DISABLE, Unit layerblend0 input port
+ * sec is disabled  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__DISABLE 0U
+/* Field Value: LAYERBLEND0_SEC_SEL__FETCHDECODE2, Unit layerblend0 input
+ * port sec is connected to output of unit fetchdecode2  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHDECODE2 0x18U
+/* Field Value: LAYERBLEND0_SEC_SEL__FETCHDECODE3, Unit layerblend0 input
+ * port sec is connected to output of unit fetchdecode3  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHDECODE3 0x19U
+/* Field Value: LAYERBLEND0_SEC_SEL__FETCHWARP2, Unit layerblend0 input port
+ * sec is connected to output of unit fetchwarp2  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHWARP2 0x1AU
+/* Field Value: LAYERBLEND0_SEC_SEL__FETCHDECODE0, Unit layerblend0 input
+ * port sec is connected to output of unit fetchdecode0  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHDECODE0 0x1CU
+/* Field Value: LAYERBLEND0_SEC_SEL__FETCHDECODE1, Unit layerblend0 input
+ * port sec is connected to output of unit fetchdecode1  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHDECODE1 0x1EU
+/* Field Value: LAYERBLEND0_SEC_SEL__MATRIX4, Unit layerblend0 input port
+ * sec is connected to output of unit matrix4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__MATRIX4 0x23U
+/* Field Value: LAYERBLEND0_SEC_SEL__HSCALER4, Unit layerblend0 input port
+ * sec is connected to output of unit hscaler4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__HSCALER4 0x24U
+/* Field Value: LAYERBLEND0_SEC_SEL__VSCALER4, Unit layerblend0 input port
+ * sec is connected to output of unit vscaler4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__VSCALER4 0x25U
+/* Field Value: LAYERBLEND0_SEC_SEL__MATRIX5, Unit layerblend0 input port
+ * sec is connected to output of unit matrix5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__MATRIX5 0x28U
+/* Field Value: LAYERBLEND0_SEC_SEL__HSCALER5, Unit layerblend0 input port
+ * sec is connected to output of unit hscaler5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__HSCALER5 0x29U
+/* Field Value: LAYERBLEND0_SEC_SEL__VSCALER5, Unit layerblend0 input port
+ * sec is connected to output of unit vscaler5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__VSCALER5 0x2AU
+/* Field Value: LAYERBLEND0_SEC_SEL__FETCHLAYER0, Unit layerblend0 input port
+ * sec is connected to output of unit fetchlayer0  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHLAYER0 0x20U
+/* Field Value: LAYERBLEND0_SEC_SEL__FETCHLAYER1, Unit layerblend0 input port
+ * sec is connected to output of unit fetchlayer1  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHLAYER1 0x21U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN_MASK 0x3000000U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN_SHIFT 24U
+/* Field Value: LAYERBLEND0_CLKEN__DISABLE, Clock for layerblend0 is disabled  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN__DISABLE 0U
+/* Field Value: LAYERBLEND0_CLKEN__AUTOMATIC, Clock is enabled if unit is
+ * used, frequency is defined by the register setting for this pipeline (see
+ * [endpoint_name]_Static register)  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN__AUTOMATIC 0x1U
+/* Field Value: LAYERBLEND0_CLKEN__FULL, Clock for layerblend0 is without
+ * gating  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN__FULL 0x3U
+
+/* Register: IMXDPUV1_pixengcfg_layerblend0_Status */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS                ((uint32_t)(0xBAC))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_OFFSET         ((uint32_t)(0x3AC))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_RESET_MASK     0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL_SHIFT 16U
+/* Field Value: LAYERBLEND0_SEL__STORE9, layerblend0 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__STORE9 0x1U
+/* Field Value: LAYERBLEND0_SEL__EXTDST0, layerblend0 module is used from
+ * extdst0 processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__EXTDST0 0x2U
+/* Field Value: LAYERBLEND0_SEL__EXTDST4, layerblend0 module is used from
+ * extdst4 processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__EXTDST4 0x3U
+/* Field Value: LAYERBLEND0_SEL__EXTDST1, layerblend0 module is used from
+ * extdst1 processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__EXTDST1 0x4U
+/* Field Value: LAYERBLEND0_SEL__EXTDST5, layerblend0 module is used from
+ * extdst5 processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__EXTDST5 0x5U
+/* Field Value: LAYERBLEND0_SEL__STORE4, layerblend0 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__STORE4 0x6U
+/* Field Value: LAYERBLEND0_SEL__STORE5, layerblend0 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__STORE5 0x7U
+/* Field Value: LAYERBLEND0_SEL__DISABLE, layerblend0 module is not used  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_layerblend1_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK            ((uint32_t)(0xBC0))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_OFFSET     ((uint32_t)(0x3C0))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_RESET_MASK 0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK_SHIFT 0U
+/* Field Value: LAYERBLEND1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset
+ * counter value is 1.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: LAYERBLEND1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock
+ * counter. Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LAYERBLEND1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LAYERBLEND1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege
+ * protection.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LAYERBLEND1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_layerblend1_LockStatus */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS            ((uint32_t)(0xBC4))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_OFFSET     ((uint32_t)(0x3C4))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_layerblend1_Dynamic */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC               ((uint32_t)(0xBC8))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_OFFSET        ((uint32_t)(0x3C8))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_RESET_VALUE   0x1001E10U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL_SHIFT 0U
+/* Field Value: LAYERBLEND1_PRIM_SEL__DISABLE, Unit layerblend1 input port
+ * prim is disabled  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__DISABLE 0U
+/* Field Value: LAYERBLEND1_PRIM_SEL__BLITBLEND9, Unit layerblend1 input port
+ * prim is connected to output of unit blitblend9  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__BLITBLEND9 0xAU
+/* Field Value: LAYERBLEND1_PRIM_SEL__CONSTFRAME0, Unit layerblend1 input
+ * port prim is connected to output of unit constframe0  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__CONSTFRAME0 0xCU
+/* Field Value: LAYERBLEND1_PRIM_SEL__CONSTFRAME1, Unit layerblend1 input
+ * port prim is connected to output of unit constframe1  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__CONSTFRAME1 0x10U
+/* Field Value: LAYERBLEND1_PRIM_SEL__CONSTFRAME4, Unit layerblend1 input
+ * port prim is connected to output of unit constframe4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__CONSTFRAME4 0xEU
+/* Field Value: LAYERBLEND1_PRIM_SEL__CONSTFRAME5, Unit layerblend1 input
+ * port prim is connected to output of unit constframe5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__CONSTFRAME5 0x12U
+/* Field Value: LAYERBLEND1_PRIM_SEL__MATRIX4, Unit layerblend1 input port
+ * prim is connected to output of unit matrix4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__MATRIX4 0x23U
+/* Field Value: LAYERBLEND1_PRIM_SEL__HSCALER4, Unit layerblend1 input port
+ * prim is connected to output of unit hscaler4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__HSCALER4 0x24U
+/* Field Value: LAYERBLEND1_PRIM_SEL__VSCALER4, Unit layerblend1 input port
+ * prim is connected to output of unit vscaler4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__VSCALER4 0x25U
+/* Field Value: LAYERBLEND1_PRIM_SEL__EXTSRC4, Unit layerblend1 input port
+ * prim is connected to output of unit extsrc4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__EXTSRC4 0x14U
+/* Field Value: LAYERBLEND1_PRIM_SEL__MATRIX5, Unit layerblend1 input port
+ * prim is connected to output of unit matrix5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__MATRIX5 0x28U
+/* Field Value: LAYERBLEND1_PRIM_SEL__HSCALER5, Unit layerblend1 input port
+ * prim is connected to output of unit hscaler5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__HSCALER5 0x29U
+/* Field Value: LAYERBLEND1_PRIM_SEL__VSCALER5, Unit layerblend1 input port
+ * prim is connected to output of unit vscaler5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__VSCALER5 0x2AU
+/* Field Value: LAYERBLEND1_PRIM_SEL__EXTSRC5, Unit layerblend1 input port
+ * prim is connected to output of unit extsrc5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__EXTSRC5 0x16U
+/* Field Value: LAYERBLEND1_PRIM_SEL__LAYERBLEND0, Unit layerblend1 input
+ * port prim is connected to output of unit layerblend0  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__LAYERBLEND0 0x2CU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL_MASK 0x3F00U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL_SHIFT 8U
+/* Field Value: LAYERBLEND1_SEC_SEL__DISABLE, Unit layerblend1 input port
+ * sec is disabled  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__DISABLE 0U
+/* Field Value: LAYERBLEND1_SEC_SEL__FETCHDECODE2, Unit layerblend1 input
+ * port sec is connected to output of unit fetchdecode2  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHDECODE2 0x18U
+/* Field Value: LAYERBLEND1_SEC_SEL__FETCHDECODE3, Unit layerblend1 input
+ * port sec is connected to output of unit fetchdecode3  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHDECODE3 0x19U
+/* Field Value: LAYERBLEND1_SEC_SEL__FETCHWARP2, Unit layerblend1 input port
+ * sec is connected to output of unit fetchwarp2  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHWARP2 0x1AU
+/* Field Value: LAYERBLEND1_SEC_SEL__FETCHDECODE0, Unit layerblend1 input
+ * port sec is connected to output of unit fetchdecode0  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHDECODE0 0x1CU
+/* Field Value: LAYERBLEND1_SEC_SEL__FETCHDECODE1, Unit layerblend1 input
+ * port sec is connected to output of unit fetchdecode1  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHDECODE1 0x1EU
+/* Field Value: LAYERBLEND1_SEC_SEL__MATRIX4, Unit layerblend1 input port
+ * sec is connected to output of unit matrix4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__MATRIX4 0x23U
+/* Field Value: LAYERBLEND1_SEC_SEL__HSCALER4, Unit layerblend1 input port
+ * sec is connected to output of unit hscaler4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__HSCALER4 0x24U
+/* Field Value: LAYERBLEND1_SEC_SEL__VSCALER4, Unit layerblend1 input port
+ * sec is connected to output of unit vscaler4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__VSCALER4 0x25U
+/* Field Value: LAYERBLEND1_SEC_SEL__MATRIX5, Unit layerblend1 input port
+ * sec is connected to output of unit matrix5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__MATRIX5 0x28U
+/* Field Value: LAYERBLEND1_SEC_SEL__HSCALER5, Unit layerblend1 input port
+ * sec is connected to output of unit hscaler5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__HSCALER5 0x29U
+/* Field Value: LAYERBLEND1_SEC_SEL__VSCALER5, Unit layerblend1 input port
+ * sec is connected to output of unit vscaler5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__VSCALER5 0x2AU
+/* Field Value: LAYERBLEND1_SEC_SEL__FETCHLAYER0, Unit layerblend1 input port
+ * sec is connected to output of unit fetchlayer0  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHLAYER0 0x20U
+/* Field Value: LAYERBLEND1_SEC_SEL__FETCHLAYER1, Unit layerblend1 input port
+ * sec is connected to output of unit fetchlayer1  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHLAYER1 0x21U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN_MASK 0x3000000U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN_SHIFT 24U
+/* Field Value: LAYERBLEND1_CLKEN__DISABLE, Clock for layerblend1 is disabled  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN__DISABLE 0U
+/* Field Value: LAYERBLEND1_CLKEN__AUTOMATIC, Clock is enabled if unit is
+ * used, frequency is defined by the register setting for this pipeline (see
+ * [endpoint_name]_Static register)  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN__AUTOMATIC 0x1U
+/* Field Value: LAYERBLEND1_CLKEN__FULL, Clock for layerblend1 is without
+ * gating  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN__FULL 0x3U
+
+/* Register: IMXDPUV1_pixengcfg_layerblend1_Status */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS                ((uint32_t)(0xBCC))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_OFFSET         ((uint32_t)(0x3CC))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_RESET_MASK     0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL_SHIFT 16U
+/* Field Value: LAYERBLEND1_SEL__STORE9, layerblend1 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__STORE9 0x1U
+/* Field Value: LAYERBLEND1_SEL__EXTDST0, layerblend1 module is used from
+ * extdst0 processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__EXTDST0 0x2U
+/* Field Value: LAYERBLEND1_SEL__EXTDST4, layerblend1 module is used from
+ * extdst4 processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__EXTDST4 0x3U
+/* Field Value: LAYERBLEND1_SEL__EXTDST1, layerblend1 module is used from
+ * extdst1 processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__EXTDST1 0x4U
+/* Field Value: LAYERBLEND1_SEL__EXTDST5, layerblend1 module is used from
+ * extdst5 processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__EXTDST5 0x5U
+/* Field Value: LAYERBLEND1_SEL__STORE4, layerblend1 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__STORE4 0x6U
+/* Field Value: LAYERBLEND1_SEL__STORE5, layerblend1 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__STORE5 0x7U
+/* Field Value: LAYERBLEND1_SEL__DISABLE, layerblend1 module is not used  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_layerblend2_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK            ((uint32_t)(0xBE0))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_OFFSET     ((uint32_t)(0x3E0))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_RESET_MASK 0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK_SHIFT 0U
+/* Field Value: LAYERBLEND2_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset
+ * counter value is 1.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: LAYERBLEND2_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock
+ * counter. Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LAYERBLEND2_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LAYERBLEND2_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege
+ * protection.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LAYERBLEND2_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_layerblend2_LockStatus */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS            ((uint32_t)(0xBE4))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_OFFSET     ((uint32_t)(0x3E4))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_layerblend2_Dynamic */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC               ((uint32_t)(0xBE8))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_OFFSET        ((uint32_t)(0x3E8))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_RESET_VALUE   0x1000000U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL_SHIFT 0U
+/* Field Value: LAYERBLEND2_PRIM_SEL__DISABLE, Unit layerblend2 input port
+ * prim is disabled  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__DISABLE 0U
+/* Field Value: LAYERBLEND2_PRIM_SEL__BLITBLEND9, Unit layerblend2 input port
+ * prim is connected to output of unit blitblend9  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__BLITBLEND9 0xAU
+/* Field Value: LAYERBLEND2_PRIM_SEL__CONSTFRAME0, Unit layerblend2 input
+ * port prim is connected to output of unit constframe0  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__CONSTFRAME0 0xCU
+/* Field Value: LAYERBLEND2_PRIM_SEL__CONSTFRAME1, Unit layerblend2 input
+ * port prim is connected to output of unit constframe1  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__CONSTFRAME1 0x10U
+/* Field Value: LAYERBLEND2_PRIM_SEL__CONSTFRAME4, Unit layerblend2 input
+ * port prim is connected to output of unit constframe4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__CONSTFRAME4 0xEU
+/* Field Value: LAYERBLEND2_PRIM_SEL__CONSTFRAME5, Unit layerblend2 input
+ * port prim is connected to output of unit constframe5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__CONSTFRAME5 0x12U
+/* Field Value: LAYERBLEND2_PRIM_SEL__MATRIX4, Unit layerblend2 input port
+ * prim is connected to output of unit matrix4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__MATRIX4 0x23U
+/* Field Value: LAYERBLEND2_PRIM_SEL__HSCALER4, Unit layerblend2 input port
+ * prim is connected to output of unit hscaler4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__HSCALER4 0x24U
+/* Field Value: LAYERBLEND2_PRIM_SEL__VSCALER4, Unit layerblend2 input port
+ * prim is connected to output of unit vscaler4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__VSCALER4 0x25U
+/* Field Value: LAYERBLEND2_PRIM_SEL__EXTSRC4, Unit layerblend2 input port
+ * prim is connected to output of unit extsrc4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__EXTSRC4 0x14U
+/* Field Value: LAYERBLEND2_PRIM_SEL__MATRIX5, Unit layerblend2 input port
+ * prim is connected to output of unit matrix5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__MATRIX5 0x28U
+/* Field Value: LAYERBLEND2_PRIM_SEL__HSCALER5, Unit layerblend2 input port
+ * prim is connected to output of unit hscaler5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__HSCALER5 0x29U
+/* Field Value: LAYERBLEND2_PRIM_SEL__VSCALER5, Unit layerblend2 input port
+ * prim is connected to output of unit vscaler5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__VSCALER5 0x2AU
+/* Field Value: LAYERBLEND2_PRIM_SEL__EXTSRC5, Unit layerblend2 input port
+ * prim is connected to output of unit extsrc5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__EXTSRC5 0x16U
+/* Field Value: LAYERBLEND2_PRIM_SEL__LAYERBLEND1, Unit layerblend2 input
+ * port prim is connected to output of unit layerblend1  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__LAYERBLEND1 0x2DU
+/* Field Value: LAYERBLEND2_PRIM_SEL__LAYERBLEND0, Unit layerblend2 input
+ * port prim is connected to output of unit layerblend0  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__LAYERBLEND0 0x2CU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL_MASK 0x3F00U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL_SHIFT 8U
+/* Field Value: LAYERBLEND2_SEC_SEL__DISABLE, Unit layerblend2 input port
+ * sec is disabled  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__DISABLE 0U
+/* Field Value: LAYERBLEND2_SEC_SEL__FETCHDECODE2, Unit layerblend2 input
+ * port sec is connected to output of unit fetchdecode2  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHDECODE2 0x18U
+/* Field Value: LAYERBLEND2_SEC_SEL__FETCHDECODE3, Unit layerblend2 input
+ * port sec is connected to output of unit fetchdecode3  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHDECODE3 0x19U
+/* Field Value: LAYERBLEND2_SEC_SEL__FETCHWARP2, Unit layerblend2 input port
+ * sec is connected to output of unit fetchwarp2  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHWARP2 0x1AU
+/* Field Value: LAYERBLEND2_SEC_SEL__FETCHDECODE0, Unit layerblend2 input
+ * port sec is connected to output of unit fetchdecode0  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHDECODE0 0x1CU
+/* Field Value: LAYERBLEND2_SEC_SEL__FETCHDECODE1, Unit layerblend2 input
+ * port sec is connected to output of unit fetchdecode1  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHDECODE1 0x1EU
+/* Field Value: LAYERBLEND2_SEC_SEL__MATRIX4, Unit layerblend2 input port
+ * sec is connected to output of unit matrix4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__MATRIX4 0x23U
+/* Field Value: LAYERBLEND2_SEC_SEL__HSCALER4, Unit layerblend2 input port
+ * sec is connected to output of unit hscaler4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__HSCALER4 0x24U
+/* Field Value: LAYERBLEND2_SEC_SEL__VSCALER4, Unit layerblend2 input port
+ * sec is connected to output of unit vscaler4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__VSCALER4 0x25U
+/* Field Value: LAYERBLEND2_SEC_SEL__MATRIX5, Unit layerblend2 input port
+ * sec is connected to output of unit matrix5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__MATRIX5 0x28U
+/* Field Value: LAYERBLEND2_SEC_SEL__HSCALER5, Unit layerblend2 input port
+ * sec is connected to output of unit hscaler5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__HSCALER5 0x29U
+/* Field Value: LAYERBLEND2_SEC_SEL__VSCALER5, Unit layerblend2 input port
+ * sec is connected to output of unit vscaler5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__VSCALER5 0x2AU
+/* Field Value: LAYERBLEND2_SEC_SEL__FETCHLAYER0, Unit layerblend2 input port
+ * sec is connected to output of unit fetchlayer0  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHLAYER0 0x20U
+/* Field Value: LAYERBLEND2_SEC_SEL__FETCHLAYER1, Unit layerblend2 input port
+ * sec is connected to output of unit fetchlayer1  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHLAYER1 0x21U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN_MASK 0x3000000U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN_SHIFT 24U
+/* Field Value: LAYERBLEND2_CLKEN__DISABLE, Clock for layerblend2 is disabled  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN__DISABLE 0U
+/* Field Value: LAYERBLEND2_CLKEN__AUTOMATIC, Clock is enabled if unit is
+ * used, frequency is defined by the register setting for this pipeline (see
+ * [endpoint_name]_Static register)  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN__AUTOMATIC 0x1U
+/* Field Value: LAYERBLEND2_CLKEN__FULL, Clock for layerblend2 is without
+ * gating  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN__FULL 0x3U
+
+/* Register: IMXDPUV1_pixengcfg_layerblend2_Status */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS                ((uint32_t)(0xBEC))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_OFFSET         ((uint32_t)(0x3EC))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_RESET_MASK     0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL_SHIFT 16U
+/* Field Value: LAYERBLEND2_SEL__STORE9, layerblend2 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__STORE9 0x1U
+/* Field Value: LAYERBLEND2_SEL__EXTDST0, layerblend2 module is used from
+ * extdst0 processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__EXTDST0 0x2U
+/* Field Value: LAYERBLEND2_SEL__EXTDST4, layerblend2 module is used from
+ * extdst4 processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__EXTDST4 0x3U
+/* Field Value: LAYERBLEND2_SEL__EXTDST1, layerblend2 module is used from
+ * extdst1 processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__EXTDST1 0x4U
+/* Field Value: LAYERBLEND2_SEL__EXTDST5, layerblend2 module is used from
+ * extdst5 processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__EXTDST5 0x5U
+/* Field Value: LAYERBLEND2_SEL__STORE4, layerblend2 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__STORE4 0x6U
+/* Field Value: LAYERBLEND2_SEL__STORE5, layerblend2 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__STORE5 0x7U
+/* Field Value: LAYERBLEND2_SEL__DISABLE, layerblend2 module is not used  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_pixengcfg_layerblend3_LockUnlock */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK            ((uint32_t)(0xC00))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_OFFSET     ((uint32_t)(0))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_RESET_MASK 0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK_SHIFT 0U
+/* Field Value: LAYERBLEND3_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter.
+ * When the counter value is null, lock protection is active. Reset
+ * counter value is 1.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: LAYERBLEND3_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock
+ * counter. Max allowed value is 15.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LAYERBLEND3_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LAYERBLEND3_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege
+ * protection.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LAYERBLEND3_LOCKUNLOCK__FREEZE_KEY, Freezes current protection
+ * status. Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_pixengcfg_layerblend3_LockStatus */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS            ((uint32_t)(0xC04))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_OFFSET     ((uint32_t)(0x4))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_RESET_VALUE 0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_LOCKSTATUS_MASK 0x1U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_LOCKSTATUS_SHIFT 0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_FREEZESTATUS_MASK 0x100U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_FREEZESTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_pixengcfg_layerblend3_Dynamic */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC               ((uint32_t)(0xC08))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_OFFSET        ((uint32_t)(0x8))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_RESET_VALUE   0x1000000U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL_MASK 0x3FU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL_SHIFT 0U
+/* Field Value: LAYERBLEND3_PRIM_SEL__DISABLE, Unit layerblend3 input port
+ * prim is disabled  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__DISABLE 0U
+/* Field Value: LAYERBLEND3_PRIM_SEL__BLITBLEND9, Unit layerblend3 input port
+ * prim is connected to output of unit blitblend9  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__BLITBLEND9 0xAU
+/* Field Value: LAYERBLEND3_PRIM_SEL__CONSTFRAME0, Unit layerblend3 input
+ * port prim is connected to output of unit constframe0  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__CONSTFRAME0 0xCU
+/* Field Value: LAYERBLEND3_PRIM_SEL__CONSTFRAME1, Unit layerblend3 input
+ * port prim is connected to output of unit constframe1  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__CONSTFRAME1 0x10U
+/* Field Value: LAYERBLEND3_PRIM_SEL__CONSTFRAME4, Unit layerblend3 input
+ * port prim is connected to output of unit constframe4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__CONSTFRAME4 0xEU
+/* Field Value: LAYERBLEND3_PRIM_SEL__CONSTFRAME5, Unit layerblend3 input
+ * port prim is connected to output of unit constframe5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__CONSTFRAME5 0x12U
+/* Field Value: LAYERBLEND3_PRIM_SEL__MATRIX4, Unit layerblend3 input port
+ * prim is connected to output of unit matrix4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__MATRIX4 0x23U
+/* Field Value: LAYERBLEND3_PRIM_SEL__HSCALER4, Unit layerblend3 input port
+ * prim is connected to output of unit hscaler4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__HSCALER4 0x24U
+/* Field Value: LAYERBLEND3_PRIM_SEL__VSCALER4, Unit layerblend3 input port
+ * prim is connected to output of unit vscaler4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__VSCALER4 0x25U
+/* Field Value: LAYERBLEND3_PRIM_SEL__EXTSRC4, Unit layerblend3 input port
+ * prim is connected to output of unit extsrc4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__EXTSRC4 0x14U
+/* Field Value: LAYERBLEND3_PRIM_SEL__MATRIX5, Unit layerblend3 input port
+ * prim is connected to output of unit matrix5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__MATRIX5 0x28U
+/* Field Value: LAYERBLEND3_PRIM_SEL__HSCALER5, Unit layerblend3 input port
+ * prim is connected to output of unit hscaler5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__HSCALER5 0x29U
+/* Field Value: LAYERBLEND3_PRIM_SEL__VSCALER5, Unit layerblend3 input port
+ * prim is connected to output of unit vscaler5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__VSCALER5 0x2AU
+/* Field Value: LAYERBLEND3_PRIM_SEL__EXTSRC5, Unit layerblend3 input port
+ * prim is connected to output of unit extsrc5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__EXTSRC5 0x16U
+/* Field Value: LAYERBLEND3_PRIM_SEL__LAYERBLEND2, Unit layerblend3 input
+ * port prim is connected to output of unit layerblend2  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__LAYERBLEND2 0x2EU
+/* Field Value: LAYERBLEND3_PRIM_SEL__LAYERBLEND1, Unit layerblend3 input
+ * port prim is connected to output of unit layerblend1  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__LAYERBLEND1 0x2DU
+/* Field Value: LAYERBLEND3_PRIM_SEL__LAYERBLEND0, Unit layerblend3 input
+ * port prim is connected to output of unit layerblend0  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__LAYERBLEND0 0x2CU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL_MASK 0x3F00U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL_SHIFT 8U
+/* Field Value: LAYERBLEND3_SEC_SEL__DISABLE, Unit layerblend3 input port
+ * sec is disabled  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__DISABLE 0U
+/* Field Value: LAYERBLEND3_SEC_SEL__FETCHDECODE2, Unit layerblend3 input
+ * port sec is connected to output of unit fetchdecode2  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHDECODE2 0x18U
+/* Field Value: LAYERBLEND3_SEC_SEL__FETCHDECODE3, Unit layerblend3 input
+ * port sec is connected to output of unit fetchdecode3  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHDECODE3 0x19U
+/* Field Value: LAYERBLEND3_SEC_SEL__FETCHWARP2, Unit layerblend3 input port
+ * sec is connected to output of unit fetchwarp2  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHWARP2 0x1AU
+/* Field Value: LAYERBLEND3_SEC_SEL__FETCHDECODE0, Unit layerblend3 input
+ * port sec is connected to output of unit fetchdecode0  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHDECODE0 0x1CU
+/* Field Value: LAYERBLEND3_SEC_SEL__FETCHDECODE1, Unit layerblend3 input
+ * port sec is connected to output of unit fetchdecode1  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHDECODE1 0x1EU
+/* Field Value: LAYERBLEND3_SEC_SEL__MATRIX4, Unit layerblend3 input port
+ * sec is connected to output of unit matrix4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__MATRIX4 0x23U
+/* Field Value: LAYERBLEND3_SEC_SEL__HSCALER4, Unit layerblend3 input port
+ * sec is connected to output of unit hscaler4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__HSCALER4 0x24U
+/* Field Value: LAYERBLEND3_SEC_SEL__VSCALER4, Unit layerblend3 input port
+ * sec is connected to output of unit vscaler4  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__VSCALER4 0x25U
+/* Field Value: LAYERBLEND3_SEC_SEL__MATRIX5, Unit layerblend3 input port
+ * sec is connected to output of unit matrix5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__MATRIX5 0x28U
+/* Field Value: LAYERBLEND3_SEC_SEL__HSCALER5, Unit layerblend3 input port
+ * sec is connected to output of unit hscaler5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__HSCALER5 0x29U
+/* Field Value: LAYERBLEND3_SEC_SEL__VSCALER5, Unit layerblend3 input port
+ * sec is connected to output of unit vscaler5  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__VSCALER5 0x2AU
+/* Field Value: LAYERBLEND3_SEC_SEL__FETCHLAYER0, Unit layerblend3 input port
+ * sec is connected to output of unit fetchlayer0  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHLAYER0 0x20U
+/* Field Value: LAYERBLEND3_SEC_SEL__FETCHLAYER1, Unit layerblend3 input port
+ * sec is connected to output of unit fetchlayer1  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHLAYER1 0x21U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN_MASK 0x3000000U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN_SHIFT 24U
+/* Field Value: LAYERBLEND3_CLKEN__DISABLE, Clock for layerblend3 is disabled  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN__DISABLE 0U
+/* Field Value: LAYERBLEND3_CLKEN__AUTOMATIC, Clock is enabled if unit is
+ * used, frequency is defined by the register setting for this pipeline (see
+ * [endpoint_name]_Static register)  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN__AUTOMATIC 0x1U
+/* Field Value: LAYERBLEND3_CLKEN__FULL, Clock for layerblend3 is without
+ * gating  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN__FULL 0x3U
+
+/* Register: IMXDPUV1_pixengcfg_layerblend3_Status */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS                ((uint32_t)(0xC0C))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_OFFSET         ((uint32_t)(0xC))
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_RESET_VALUE    0U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_RESET_MASK     0xFFF8FFFFU
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL_MASK 0x70000U
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL_SHIFT 16U
+/* Field Value: LAYERBLEND3_SEL__STORE9, layerblend3 module is used from store9
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__STORE9 0x1U
+/* Field Value: LAYERBLEND3_SEL__EXTDST0, layerblend3 module is used from
+ * extdst0 processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__EXTDST0 0x2U
+/* Field Value: LAYERBLEND3_SEL__EXTDST4, layerblend3 module is used from
+ * extdst4 processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__EXTDST4 0x3U
+/* Field Value: LAYERBLEND3_SEL__EXTDST1, layerblend3 module is used from
+ * extdst1 processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__EXTDST1 0x4U
+/* Field Value: LAYERBLEND3_SEL__EXTDST5, layerblend3 module is used from
+ * extdst5 processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__EXTDST5 0x5U
+/* Field Value: LAYERBLEND3_SEL__STORE4, layerblend3 module is used from store4
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__STORE4 0x6U
+/* Field Value: LAYERBLEND3_SEL__STORE5, layerblend3 module is used from store5
+ * processing path  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__STORE5 0x7U
+/* Field Value: LAYERBLEND3_SEL__DISABLE, layerblend3 module is not used  */
+#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__DISABLE 0U
+
+/* Register: IMXDPUV1_FetchDecode9_LockUnlock */
+#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK                     ((uint32_t)(0x1000))
+#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_OFFSET              ((uint32_t)(0))
+#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_RESET_VALUE         0U
+#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_RESET_MASK          0U
+#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK_SHIFT    0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_FetchDecode9_LockStatus */
+#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS                     ((uint32_t)(0x1004))
+#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_OFFSET              ((uint32_t)(0x4))
+#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_RESET_VALUE         0U
+#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_LOCKSTATUS_MASK     0x1U
+#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_LOCKSTATUS_SHIFT    0U
+#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_FREEZESTATUS_MASK   0x100U
+#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_FREEZESTATUS_SHIFT  8U
+
+/* Register: IMXDPUV1_FetchDecode9_StaticControl */
+#define IMXDPUV1_FETCHDECODE9_STATICCONTROL                  ((uint32_t)(0x1008))
+#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_OFFSET           ((uint32_t)(0x8))
+#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_RESET_VALUE      0U
+#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_SHDEN_MASK       0x1U
+#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_SHDEN_SHIFT      0U
+#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U
+#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U
+
+/* Register: IMXDPUV1_FetchDecode9_BurstBufferManagement */
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT          ((uint32_t)(0x100C))
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_OFFSET   ((uint32_t)(0xC))
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U
+/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the
+ * Display Controller. Works also for Blit Engine with marginal performance
+ * impact.  */
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U
+/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit
+ * Engine.  */
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U
+
+/* Register: IMXDPUV1_FetchDecode9_RingBufStartAddr0 */
+#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0              ((uint32_t)(0x1010))
+#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_OFFSET       ((uint32_t)(0x10))
+#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_RESET_VALUE  0U
+#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode9_RingBufWrapAddr0 */
+#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0               ((uint32_t)(0x1014))
+#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_OFFSET        ((uint32_t)(0x14))
+#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_RESET_VALUE   0U
+#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode9_FrameProperties0 */
+#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0               ((uint32_t)(0x1018))
+#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_OFFSET        ((uint32_t)(0x18))
+#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_RESET_VALUE   0U
+#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_FIELDID0_MASK 0x1U
+#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_FIELDID0_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode9_BaseAddress0 */
+#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0                   ((uint32_t)(0x101C))
+#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_OFFSET            ((uint32_t)(0x1C))
+#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_RESET_VALUE       0U
+#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_BASEADDRESS0_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode9_SourceBufferAttributes0 */
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0        ((uint32_t)(0x1020))
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x20))
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U
+
+/* Register: IMXDPUV1_FetchDecode9_SourceBufferDimension0 */
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0         ((uint32_t)(0x1024))
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_OFFSET  ((uint32_t)(0x24))
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U
+
+/* Register: IMXDPUV1_FetchDecode9_ColorComponentBits0 */
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0            ((uint32_t)(0x1028))
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_OFFSET     ((uint32_t)(0x28))
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U
+
+/* Register: IMXDPUV1_FetchDecode9_ColorComponentShift0 */
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0           ((uint32_t)(0x102C))
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_OFFSET    ((uint32_t)(0x2C))
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U
+#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_FetchDecode9_LayerOffset0 */
+#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0                   ((uint32_t)(0x1030))
+#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_OFFSET            ((uint32_t)(0x30))
+#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_RESET_VALUE       0U
+#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU
+#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U
+
+/* Register: IMXDPUV1_FetchDecode9_ClipWindowOffset0 */
+#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0              ((uint32_t)(0x1034))
+#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_OFFSET       ((uint32_t)(0x34))
+#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_RESET_VALUE  0U
+#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU
+#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U
+
+/* Register: IMXDPUV1_FetchDecode9_ClipWindowDimensions0 */
+#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0          ((uint32_t)(0x1038))
+#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_OFFSET   ((uint32_t)(0x38))
+#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U
+#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U
+
+/* Register: IMXDPUV1_FetchDecode9_ConstantColor0 */
+#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0                 ((uint32_t)(0x103C))
+#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_OFFSET          ((uint32_t)(0x3C))
+#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_RESET_VALUE     0U
+#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU
+#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U
+#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U
+#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U
+#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_FetchDecode9_LayerProperty0 */
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0                 ((uint32_t)(0x1040))
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_OFFSET          ((uint32_t)(0x40))
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RESET_VALUE     0x80000100U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_PALETTEENABLE0_MASK 0x1U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_PALETTEENABLE0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0_MASK  0x30U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0_SHIFT 4U
+/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U
+/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion.  */
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U
+/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U
+#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U
+
+/* Register: IMXDPUV1_FetchDecode9_FrameDimensions */
+#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS                ((uint32_t)(0x1044))
+#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_OFFSET         ((uint32_t)(0x44))
+#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_RESET_VALUE    0xEF013FU
+#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU
+#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U
+#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U
+#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U
+
+/* Register: IMXDPUV1_FetchDecode9_FrameResampling */
+#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING                ((uint32_t)(0x1048))
+#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_OFFSET         ((uint32_t)(0x48))
+#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_RESET_VALUE    0x104000U
+#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_STARTX_MASK    0x3FU
+#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_STARTX_SHIFT   0U
+#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_STARTY_MASK    0xFC0U
+#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_STARTY_SHIFT   6U
+#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_DELTAX_MASK    0x3F000U
+#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_DELTAX_SHIFT   12U
+#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_DELTAY_MASK    0xFC0000U
+#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_DELTAY_SHIFT   18U
+#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U
+#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U
+
+/* Register: IMXDPUV1_FetchDecode9_DecodeControl */
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL                  ((uint32_t)(0x104C))
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_OFFSET           ((uint32_t)(0x4C))
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RESET_VALUE      0x88880001U
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE_MASK 0x3U
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE_SHIFT 0U
+/* Field Value: COMPRESSIONMODE__RLAD, Run-Length Adaptive Dithering (lossy
+ * compression).  */
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE__RLAD 0U
+/* Field Value: COMPRESSIONMODE__RLAD_UNIFORM, Run-Length Adaptive Dithering
+ * (lossy compression; uniform package size).  */
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE__RLAD_UNIFORM 0x1U
+/* Field Value: COMPRESSIONMODE__RLA, Run-Length Adaptive (lossless compression).  */
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE__RLA 0x2U
+/* Field Value: COMPRESSIONMODE__RL, Standard Run-Length.  */
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE__RL 0x3U
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADENDIANNESS_MASK 0x8000U
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADENDIANNESS_SHIFT 15U
+/* Field Value: RLADENDIANNESS__BIGENDIAN, Big endian format  */
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADENDIANNESS__BIGENDIAN 0U
+/* Field Value: RLADENDIANNESS__LITTLEENDIAN, Little endian format  */
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADENDIANNESS__LITTLEENDIAN 0x1U
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSRED_MASK 0xF0000U
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSRED_SHIFT 16U
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSGREEN_MASK 0xF00000U
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSGREEN_SHIFT 20U
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSBLUE_MASK 0xF000000U
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSBLUE_SHIFT 24U
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSALPHA_MASK 0xF0000000U
+#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSALPHA_SHIFT 28U
+
+/* Register: IMXDPUV1_FetchDecode9_SourceBufferLength */
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH             ((uint32_t)(0x1050))
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_OFFSET      ((uint32_t)(0x50))
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_RESET_VALUE 0U
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_RLEWORDS_MASK 0x1FFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_RLEWORDS_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode9_Control */
+#define IMXDPUV1_FETCHDECODE9_CONTROL                        ((uint32_t)(0x1054))
+#define IMXDPUV1_FETCHDECODE9_CONTROL_OFFSET                 ((uint32_t)(0x54))
+#define IMXDPUV1_FETCHDECODE9_CONTROL_RESET_VALUE            0x10700U
+#define IMXDPUV1_FETCHDECODE9_CONTROL_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE_MASK        0x7U
+#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE_SHIFT       0U
+/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin.
+ * Hor/ver increments using DeltaX/Y and DeltaSwap setup.  */
+#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__NORMAL     0U
+/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source
+ * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver
+ * increments = (1,0)/(0,1).  */
+#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__DECODE     0x1U
+/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary
+ * warping (filter is active). Coordinates are read from frame input
+ * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY
+ * must be setup.  */
+#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__ARBITRARY  0x2U
+/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective
+ * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver
+ * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates.  */
+#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__PERSPECTIVE 0x3U
+/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer
+ * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments
+ * = (1,0)/(0,1). All corellated window widths and horizontal offsets must
+ * be even.  */
+#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__YUV422     0x4U
+/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter
+ * is active). First sample at AffineStartX/Y. Hor/ver increments using
+ * AffineDeltaXX/XY/YX/YY. Cartesian coordinates.  */
+#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__AFFINE     0x5U
+#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT_MASK       0x18U
+#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT_SHIFT      3U
+/* Field Value: INPUTSELECT__INACTIVE, Not used.  */
+#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT__INACTIVE  0U
+/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV
+ * or source alpha buffer).  */
+#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT__COMPPACK  0x1U
+/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply
+ * stage (mask alpha buffer).  */
+#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT__ALPHAMASK 0x2U
+/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate
+ * buffer).  */
+#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT__COORDINATE 0x3U
+#define IMXDPUV1_FETCHDECODE9_CONTROL_YUV422UPSAMPLINGMODE_MASK 0x20U
+#define IMXDPUV1_FETCHDECODE9_CONTROL_YUV422UPSAMPLINGMODE_SHIFT 5U
+/* Field Value: YUV422UPSAMPLINGMODE__REPLICATE, Replicate mode for interspersed
+ * samples (UV samples between Y samples).  */
+#define IMXDPUV1_FETCHDECODE9_CONTROL_YUV422UPSAMPLINGMODE__REPLICATE 0U
+/* Field Value: YUV422UPSAMPLINGMODE__INTERPOLATE, Interpolate mode for coaligned
+ * samples (UV samples at Y sample positions).  */
+#define IMXDPUV1_FETCHDECODE9_CONTROL_YUV422UPSAMPLINGMODE__INTERPOLATE 0x1U
+#define IMXDPUV1_FETCHDECODE9_CONTROL_RAWPIXEL_MASK          0x80U
+#define IMXDPUV1_FETCHDECODE9_CONTROL_RAWPIXEL_SHIFT         7U
+#define IMXDPUV1_FETCHDECODE9_CONTROL_PALETTEIDXWIDTH_MASK   0x700U
+#define IMXDPUV1_FETCHDECODE9_CONTROL_PALETTEIDXWIDTH_SHIFT  8U
+#define IMXDPUV1_FETCHDECODE9_CONTROL_CLIPCOLOR_MASK         0x10000U
+#define IMXDPUV1_FETCHDECODE9_CONTROL_CLIPCOLOR_SHIFT        16U
+/* Field Value: CLIPCOLOR__NULL, Null color.  */
+#define IMXDPUV1_FETCHDECODE9_CONTROL_CLIPCOLOR__NULL        0U
+/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer
+ * (or layer 0 when Fetch unit has one layer only). The color is then the
+ * layer's source or tiling color.  */
+#define IMXDPUV1_FETCHDECODE9_CONTROL_CLIPCOLOR__LAYER       0x1U
+
+/* Register: IMXDPUV1_FetchDecode9_ControlTrigger */
+#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER                 ((uint32_t)(0x1058))
+#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_OFFSET          ((uint32_t)(0x58))
+#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_RESET_VALUE     0U
+#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_RESET_MASK      0xFFFFFFFEU
+#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_SHDTOKGEN_MASK  0x1U
+#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode9_Start */
+#define IMXDPUV1_FETCHDECODE9_START                          ((uint32_t)(0x105C))
+#define IMXDPUV1_FETCHDECODE9_START_OFFSET                   ((uint32_t)(0x5C))
+#define IMXDPUV1_FETCHDECODE9_START_RESET_VALUE              0U
+#define IMXDPUV1_FETCHDECODE9_START_RESET_MASK               0xFFFFFFFEU
+#define IMXDPUV1_FETCHDECODE9_START_START_MASK               0x1U
+#define IMXDPUV1_FETCHDECODE9_START_START_SHIFT              0U
+
+/* Register: IMXDPUV1_FetchDecode9_FetchType */
+#define IMXDPUV1_FETCHDECODE9_FETCHTYPE                      ((uint32_t)(0x1060))
+#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_OFFSET               ((uint32_t)(0x60))
+#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_RESET_VALUE          0U
+#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_RESET_MASK           0xFFFFFFF0U
+#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE_MASK       0xFU
+#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE_SHIFT      0U
+/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder.  */
+#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__DECODE    0U
+/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers).  */
+#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__LAYER     0x1U
+/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional
+ * plane (8 layers).  */
+#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__WARP      0x2U
+/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha,
+ * chroma and coordinate planes.  */
+#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__ECO       0x3U
+/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and
+ * arbitrary warping.  */
+#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__PERSP     0x4U
+/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping.  */
+#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__ROT       0x5U
+/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced
+ * feature set.  */
+#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__DECODEL   0x6U
+/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers),
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__LAYERL    0x7U
+/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping,
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__ROTL      0x8U
+
+/* Register: IMXDPUV1_FetchDecode9_DecoderStatus */
+#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS                  ((uint32_t)(0x1064))
+#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_OFFSET           ((uint32_t)(0x64))
+#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_RESET_VALUE      0U
+#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_BUFFERTOOSMALL_MASK 0x1U
+#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_BUFFERTOOSMALL_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_BUFFERTOOLARGE_MASK 0x2U
+#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_BUFFERTOOLARGE_SHIFT 1U
+
+/* Register: IMXDPUV1_FetchDecode9_ReadAddress0 */
+#define IMXDPUV1_FETCHDECODE9_READADDRESS0                   ((uint32_t)(0x1068))
+#define IMXDPUV1_FETCHDECODE9_READADDRESS0_OFFSET            ((uint32_t)(0x68))
+#define IMXDPUV1_FETCHDECODE9_READADDRESS0_RESET_VALUE       0U
+#define IMXDPUV1_FETCHDECODE9_READADDRESS0_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_READADDRESS0_READADDRESS0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_READADDRESS0_READADDRESS0_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode9_BurstBufferProperties */
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES          ((uint32_t)(0x106C))
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_OFFSET   ((uint32_t)(0x6C))
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_RESET_VALUE 0U
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U
+#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U
+
+/* Register: IMXDPUV1_FetchDecode9_Status */
+#define IMXDPUV1_FETCHDECODE9_STATUS                         ((uint32_t)(0x1070))
+#define IMXDPUV1_FETCHDECODE9_STATUS_OFFSET                  ((uint32_t)(0x70))
+#define IMXDPUV1_FETCHDECODE9_STATUS_RESET_VALUE             0U
+#define IMXDPUV1_FETCHDECODE9_STATUS_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_STATUS_WRITETIMEOUT_MASK       0x1U
+#define IMXDPUV1_FETCHDECODE9_STATUS_WRITETIMEOUT_SHIFT      0U
+#define IMXDPUV1_FETCHDECODE9_STATUS_READTIMEOUT_MASK        0x10U
+#define IMXDPUV1_FETCHDECODE9_STATUS_READTIMEOUT_SHIFT       4U
+
+/* Register: IMXDPUV1_FetchDecode9_HiddenStatus */
+#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS                   ((uint32_t)(0x1074))
+#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_OFFSET            ((uint32_t)(0x74))
+#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_RESET_VALUE       0U
+#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_RESET_MASK        0xFFFF008EU
+#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSBUSY_MASK   0x1U
+#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSBUSY_SHIFT  0U
+#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U
+#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U
+#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U
+#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U
+#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U
+#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U
+#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U
+#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_FetchDecode9_ColorPalette */
+#define IMXDPUV1_FETCHDECODE9_COLORPALETTE                   ((uint32_t)(0x1400))
+#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_OFFSET            ((uint32_t)(0))
+#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_RESET_VALUE       0U
+#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_RESET_MASK        0xFF000000U
+#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_COLORPALETTE_MASK 0xFFFFFFU
+#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_COLORPALETTE_SHIFT 0U
+
+/* Register: IMXDPUV1_fetchwarp9_LockUnlock */
+#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK                       ((uint32_t)(0x1800))
+#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_OFFSET                ((uint32_t)(0))
+#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_RESET_VALUE           0U
+#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_RESET_MASK            0U
+#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK_SHIFT      0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY  0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_fetchwarp9_LockStatus */
+#define IMXDPUV1_FETCHWARP9_LOCKSTATUS                       ((uint32_t)(0x1804))
+#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_OFFSET                ((uint32_t)(0x4))
+#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_RESET_VALUE           0U
+#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_LOCKSTATUS_MASK       0x1U
+#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_LOCKSTATUS_SHIFT      0U
+#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_PRIVILEGESTATUS_MASK  0x10U
+#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_FREEZESTATUS_MASK     0x100U
+#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_FREEZESTATUS_SHIFT    8U
+
+/* Register: IMXDPUV1_fetchwarp9_StaticControl */
+#define IMXDPUV1_FETCHWARP9_STATICCONTROL                    ((uint32_t)(0x1808))
+#define IMXDPUV1_FETCHWARP9_STATICCONTROL_OFFSET             ((uint32_t)(0x8))
+#define IMXDPUV1_FETCHWARP9_STATICCONTROL_RESET_VALUE        0xFF000000U
+#define IMXDPUV1_FETCHWARP9_STATICCONTROL_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDEN_MASK         0x1U
+#define IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDEN_SHIFT        0U
+#define IMXDPUV1_FETCHWARP9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDLDREQSTICKY_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDLDREQSTICKY_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp9_BurstBufferManagement */
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT            ((uint32_t)(0x180C))
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_OFFSET     ((uint32_t)(0xC))
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U
+/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the
+ * Display Controller. Works also for Blit Engine with marginal performance
+ * impact.  */
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U
+/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit
+ * Engine.  */
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U
+
+/* Register: IMXDPUV1_fetchwarp9_BaseAddress0 */
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS0                     ((uint32_t)(0x1810))
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_OFFSET              ((uint32_t)(0x10))
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_BASEADDRESS0_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_BASEADDRESS0_SHIFT  0U
+
+/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes0 */
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0          ((uint32_t)(0x1814))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_OFFSET   ((uint32_t)(0x14))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension0 */
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0           ((uint32_t)(0x1818))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_OFFSET    ((uint32_t)(0x18))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits0 */
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0              ((uint32_t)(0x181C))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_OFFSET       ((uint32_t)(0x1C))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_RESET_VALUE  0x8080808U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift0 */
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0             ((uint32_t)(0x1820))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_OFFSET      ((uint32_t)(0x20))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp9_LayerOffset0 */
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0                     ((uint32_t)(0x1824))
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_OFFSET              ((uint32_t)(0x24))
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_LAYERXOFFSET0_MASK  0x7FFFU
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_LAYERYOFFSET0_MASK  0x7FFF0000U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset0 */
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0                ((uint32_t)(0x1828))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_OFFSET         ((uint32_t)(0x28))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_RESET_VALUE    0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions0 */
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0            ((uint32_t)(0x182C))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_OFFSET     ((uint32_t)(0x2C))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ConstantColor0 */
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0                   ((uint32_t)(0x1830))
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_OFFSET            ((uint32_t)(0x30))
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_RESET_VALUE       0U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp9_LayerProperty0 */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0                   ((uint32_t)(0x1834))
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_OFFSET            ((uint32_t)(0x34))
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RESET_VALUE       0x80000100U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0_MASK    0x30U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0_SHIFT   4U
+/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U
+/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U
+/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp9_BaseAddress1 */
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS1                     ((uint32_t)(0x1838))
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_OFFSET              ((uint32_t)(0x38))
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_BASEADDRESS1_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_BASEADDRESS1_SHIFT  0U
+
+/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes1 */
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1          ((uint32_t)(0x183C))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_OFFSET   ((uint32_t)(0x3C))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_STRIDE1_MASK 0xFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_STRIDE1_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_MASK 0x3F0000U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension1 */
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1           ((uint32_t)(0x1840))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_OFFSET    ((uint32_t)(0x40))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_LINEWIDTH1_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_LINEWIDTH1_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_LINECOUNT1_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_LINECOUNT1_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits1 */
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1              ((uint32_t)(0x1844))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_OFFSET       ((uint32_t)(0x44))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_RESET_VALUE  0x8080808U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_MASK 0xFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_MASK 0xF00U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_MASK 0xF0000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSRED1_MASK 0xF000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSRED1_SHIFT 24U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_ITUFORMAT1_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_ITUFORMAT1_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift1 */
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1             ((uint32_t)(0x1848))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_OFFSET      ((uint32_t)(0x48))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_MASK 0x1FU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_MASK 0x1F0000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_MASK 0x1F000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp9_LayerOffset1 */
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1                     ((uint32_t)(0x184C))
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_OFFSET              ((uint32_t)(0x4C))
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_LAYERXOFFSET1_MASK  0x7FFFU
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_LAYERXOFFSET1_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_LAYERYOFFSET1_MASK  0x7FFF0000U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_LAYERYOFFSET1_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset1 */
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1                ((uint32_t)(0x1850))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_OFFSET         ((uint32_t)(0x50))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_RESET_VALUE    0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_MASK 0x7FFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions1 */
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1            ((uint32_t)(0x1854))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_OFFSET     ((uint32_t)(0x54))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_RESET_VALUE 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ConstantColor1 */
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1                   ((uint32_t)(0x1858))
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_OFFSET            ((uint32_t)(0x58))
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_RESET_VALUE       0U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTALPHA1_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTALPHA1_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTBLUE1_MASK 0xFF00U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTBLUE1_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTGREEN1_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTGREEN1_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTRED1_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTRED1_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp9_LayerProperty1 */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1                   ((uint32_t)(0x185C))
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_OFFSET            ((uint32_t)(0x5C))
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RESET_VALUE       0x100U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1_MASK    0x30U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1_SHIFT   4U
+/* Field Value: TILEMODE1__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE1__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE1__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1__TILE_PAD 0x2U
+/* Field Value: TILEMODE1__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHASRCENABLE1_MASK 0x100U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHASRCENABLE1_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHACONSTENABLE1_MASK 0x200U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHACONSTENABLE1_SHIFT 9U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHAMASKENABLE1_MASK 0x400U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHAMASKENABLE1_SHIFT 10U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHATRANSENABLE1_MASK 0x800U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHATRANSENABLE1_SHIFT 11U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHASRCENABLE1_MASK 0x1000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHASRCENABLE1_SHIFT 12U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHACONSTENABLE1_MASK 0x2000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHACONSTENABLE1_SHIFT 13U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHAMASKENABLE1_MASK 0x4000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHAMASKENABLE1_SHIFT 14U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHATRANSENABLE1_MASK 0x8000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHATRANSENABLE1_SHIFT 15U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_PREMULCONSTRGB1_MASK 0x10000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_PREMULCONSTRGB1_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1_MASK 0x60000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE1__OFF, No conversion.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1__OFF 0U
+/* Field Value: YUVCONVERSIONMODE1__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE1__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE1__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU709 0x3U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_GAMMAREMOVEENABLE1_MASK 0x100000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_GAMMAREMOVEENABLE1_SHIFT 20U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_CLIPWINDOWENABLE1_MASK 0x40000000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_CLIPWINDOWENABLE1_SHIFT 30U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_SOURCEBUFFERENABLE1_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_SOURCEBUFFERENABLE1_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp9_BaseAddress2 */
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS2                     ((uint32_t)(0x1860))
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_OFFSET              ((uint32_t)(0x60))
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_BASEADDRESS2_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_BASEADDRESS2_SHIFT  0U
+
+/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes2 */
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2          ((uint32_t)(0x1864))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_OFFSET   ((uint32_t)(0x64))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_STRIDE2_MASK 0xFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_STRIDE2_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_MASK 0x3F0000U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension2 */
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2           ((uint32_t)(0x1868))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_OFFSET    ((uint32_t)(0x68))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_LINEWIDTH2_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_LINEWIDTH2_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_LINECOUNT2_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_LINECOUNT2_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits2 */
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2              ((uint32_t)(0x186C))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_OFFSET       ((uint32_t)(0x6C))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_RESET_VALUE  0x8080808U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_MASK 0xFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_MASK 0xF00U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_MASK 0xF0000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSRED2_MASK 0xF000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSRED2_SHIFT 24U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_ITUFORMAT2_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_ITUFORMAT2_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift2 */
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2             ((uint32_t)(0x1870))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_OFFSET      ((uint32_t)(0x70))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_MASK 0x1FU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_MASK 0x1F0000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_MASK 0x1F000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp9_LayerOffset2 */
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2                     ((uint32_t)(0x1874))
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_OFFSET              ((uint32_t)(0x74))
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_LAYERXOFFSET2_MASK  0x7FFFU
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_LAYERXOFFSET2_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_LAYERYOFFSET2_MASK  0x7FFF0000U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_LAYERYOFFSET2_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset2 */
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2                ((uint32_t)(0x1878))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_OFFSET         ((uint32_t)(0x78))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_RESET_VALUE    0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_MASK 0x7FFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions2 */
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2            ((uint32_t)(0x187C))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_OFFSET     ((uint32_t)(0x7C))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_RESET_VALUE 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ConstantColor2 */
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2                   ((uint32_t)(0x1880))
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_OFFSET            ((uint32_t)(0x80))
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_RESET_VALUE       0U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTALPHA2_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTALPHA2_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTBLUE2_MASK 0xFF00U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTBLUE2_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTGREEN2_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTGREEN2_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTRED2_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTRED2_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp9_LayerProperty2 */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2                   ((uint32_t)(0x1884))
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_OFFSET            ((uint32_t)(0x84))
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RESET_VALUE       0x100U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2_MASK    0x30U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2_SHIFT   4U
+/* Field Value: TILEMODE2__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE2__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE2__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2__TILE_PAD 0x2U
+/* Field Value: TILEMODE2__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHASRCENABLE2_MASK 0x100U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHASRCENABLE2_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHACONSTENABLE2_MASK 0x200U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHACONSTENABLE2_SHIFT 9U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHAMASKENABLE2_MASK 0x400U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHAMASKENABLE2_SHIFT 10U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHATRANSENABLE2_MASK 0x800U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHATRANSENABLE2_SHIFT 11U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHASRCENABLE2_MASK 0x1000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHASRCENABLE2_SHIFT 12U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHACONSTENABLE2_MASK 0x2000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHACONSTENABLE2_SHIFT 13U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHAMASKENABLE2_MASK 0x4000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHAMASKENABLE2_SHIFT 14U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHATRANSENABLE2_MASK 0x8000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHATRANSENABLE2_SHIFT 15U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_PREMULCONSTRGB2_MASK 0x10000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_PREMULCONSTRGB2_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2_MASK 0x60000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE2__OFF, No conversion.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2__OFF 0U
+/* Field Value: YUVCONVERSIONMODE2__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE2__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE2__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU709 0x3U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_GAMMAREMOVEENABLE2_MASK 0x100000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_GAMMAREMOVEENABLE2_SHIFT 20U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_CLIPWINDOWENABLE2_MASK 0x40000000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_CLIPWINDOWENABLE2_SHIFT 30U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_SOURCEBUFFERENABLE2_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_SOURCEBUFFERENABLE2_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp9_BaseAddress3 */
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS3                     ((uint32_t)(0x1888))
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_OFFSET              ((uint32_t)(0x88))
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_BASEADDRESS3_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_BASEADDRESS3_SHIFT  0U
+
+/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes3 */
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3          ((uint32_t)(0x188C))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_OFFSET   ((uint32_t)(0x8C))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_STRIDE3_MASK 0xFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_STRIDE3_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_MASK 0x3F0000U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension3 */
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3           ((uint32_t)(0x1890))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_OFFSET    ((uint32_t)(0x90))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_LINEWIDTH3_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_LINEWIDTH3_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_LINECOUNT3_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_LINECOUNT3_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits3 */
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3              ((uint32_t)(0x1894))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_OFFSET       ((uint32_t)(0x94))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_RESET_VALUE  0x8080808U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_MASK 0xFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_MASK 0xF00U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_MASK 0xF0000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSRED3_MASK 0xF000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSRED3_SHIFT 24U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_ITUFORMAT3_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_ITUFORMAT3_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift3 */
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3             ((uint32_t)(0x1898))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_OFFSET      ((uint32_t)(0x98))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_MASK 0x1FU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_MASK 0x1F0000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_MASK 0x1F000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp9_LayerOffset3 */
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3                     ((uint32_t)(0x189C))
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_OFFSET              ((uint32_t)(0x9C))
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_LAYERXOFFSET3_MASK  0x7FFFU
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_LAYERXOFFSET3_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_LAYERYOFFSET3_MASK  0x7FFF0000U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_LAYERYOFFSET3_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset3 */
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3                ((uint32_t)(0x18A0))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_OFFSET         ((uint32_t)(0xA0))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_RESET_VALUE    0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_MASK 0x7FFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions3 */
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3            ((uint32_t)(0x18A4))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_OFFSET     ((uint32_t)(0xA4))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_RESET_VALUE 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ConstantColor3 */
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3                   ((uint32_t)(0x18A8))
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_OFFSET            ((uint32_t)(0xA8))
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_RESET_VALUE       0U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTALPHA3_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTALPHA3_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTBLUE3_MASK 0xFF00U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTBLUE3_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTGREEN3_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTGREEN3_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTRED3_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTRED3_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp9_LayerProperty3 */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3                   ((uint32_t)(0x18AC))
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_OFFSET            ((uint32_t)(0xAC))
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RESET_VALUE       0x100U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3_MASK    0x30U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3_SHIFT   4U
+/* Field Value: TILEMODE3__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE3__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE3__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3__TILE_PAD 0x2U
+/* Field Value: TILEMODE3__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHASRCENABLE3_MASK 0x100U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHASRCENABLE3_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHACONSTENABLE3_MASK 0x200U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHACONSTENABLE3_SHIFT 9U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHAMASKENABLE3_MASK 0x400U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHAMASKENABLE3_SHIFT 10U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHATRANSENABLE3_MASK 0x800U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHATRANSENABLE3_SHIFT 11U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHASRCENABLE3_MASK 0x1000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHASRCENABLE3_SHIFT 12U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHACONSTENABLE3_MASK 0x2000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHACONSTENABLE3_SHIFT 13U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHAMASKENABLE3_MASK 0x4000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHAMASKENABLE3_SHIFT 14U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHATRANSENABLE3_MASK 0x8000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHATRANSENABLE3_SHIFT 15U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_PREMULCONSTRGB3_MASK 0x10000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_PREMULCONSTRGB3_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3_MASK 0x60000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE3__OFF, No conversion.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3__OFF 0U
+/* Field Value: YUVCONVERSIONMODE3__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE3__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE3__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU709 0x3U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_GAMMAREMOVEENABLE3_MASK 0x100000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_GAMMAREMOVEENABLE3_SHIFT 20U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_CLIPWINDOWENABLE3_MASK 0x40000000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_CLIPWINDOWENABLE3_SHIFT 30U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_SOURCEBUFFERENABLE3_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_SOURCEBUFFERENABLE3_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp9_BaseAddress4 */
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS4                     ((uint32_t)(0x18B0))
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_OFFSET              ((uint32_t)(0xB0))
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_BASEADDRESS4_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_BASEADDRESS4_SHIFT  0U
+
+/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes4 */
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4          ((uint32_t)(0x18B4))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_OFFSET   ((uint32_t)(0xB4))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_STRIDE4_MASK 0xFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_STRIDE4_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_MASK 0x3F0000U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension4 */
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4           ((uint32_t)(0x18B8))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_OFFSET    ((uint32_t)(0xB8))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_LINEWIDTH4_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_LINEWIDTH4_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_LINECOUNT4_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_LINECOUNT4_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits4 */
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4              ((uint32_t)(0x18BC))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_OFFSET       ((uint32_t)(0xBC))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_RESET_VALUE  0x8080808U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_MASK 0xFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_MASK 0xF00U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_MASK 0xF0000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSRED4_MASK 0xF000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSRED4_SHIFT 24U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_ITUFORMAT4_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_ITUFORMAT4_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift4 */
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4             ((uint32_t)(0x18C0))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_OFFSET      ((uint32_t)(0xC0))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_MASK 0x1FU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_MASK 0x1F0000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_MASK 0x1F000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp9_LayerOffset4 */
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4                     ((uint32_t)(0x18C4))
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_OFFSET              ((uint32_t)(0xC4))
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_LAYERXOFFSET4_MASK  0x7FFFU
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_LAYERXOFFSET4_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_LAYERYOFFSET4_MASK  0x7FFF0000U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_LAYERYOFFSET4_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset4 */
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4                ((uint32_t)(0x18C8))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_OFFSET         ((uint32_t)(0xC8))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_RESET_VALUE    0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_MASK 0x7FFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions4 */
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4            ((uint32_t)(0x18CC))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_OFFSET     ((uint32_t)(0xCC))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_RESET_VALUE 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ConstantColor4 */
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4                   ((uint32_t)(0x18D0))
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_OFFSET            ((uint32_t)(0xD0))
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_RESET_VALUE       0U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTALPHA4_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTALPHA4_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTBLUE4_MASK 0xFF00U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTBLUE4_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTGREEN4_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTGREEN4_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTRED4_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTRED4_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp9_LayerProperty4 */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4                   ((uint32_t)(0x18D4))
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_OFFSET            ((uint32_t)(0xD4))
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RESET_VALUE       0x100U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4_MASK    0x30U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4_SHIFT   4U
+/* Field Value: TILEMODE4__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE4__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE4__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4__TILE_PAD 0x2U
+/* Field Value: TILEMODE4__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHASRCENABLE4_MASK 0x100U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHASRCENABLE4_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHACONSTENABLE4_MASK 0x200U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHACONSTENABLE4_SHIFT 9U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHAMASKENABLE4_MASK 0x400U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHAMASKENABLE4_SHIFT 10U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHATRANSENABLE4_MASK 0x800U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHATRANSENABLE4_SHIFT 11U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHASRCENABLE4_MASK 0x1000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHASRCENABLE4_SHIFT 12U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHACONSTENABLE4_MASK 0x2000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHACONSTENABLE4_SHIFT 13U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHAMASKENABLE4_MASK 0x4000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHAMASKENABLE4_SHIFT 14U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHATRANSENABLE4_MASK 0x8000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHATRANSENABLE4_SHIFT 15U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_PREMULCONSTRGB4_MASK 0x10000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_PREMULCONSTRGB4_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4_MASK 0x60000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE4__OFF, No conversion.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4__OFF 0U
+/* Field Value: YUVCONVERSIONMODE4__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE4__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE4__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU709 0x3U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_GAMMAREMOVEENABLE4_MASK 0x100000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_GAMMAREMOVEENABLE4_SHIFT 20U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_CLIPWINDOWENABLE4_MASK 0x40000000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_CLIPWINDOWENABLE4_SHIFT 30U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_SOURCEBUFFERENABLE4_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_SOURCEBUFFERENABLE4_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp9_BaseAddress5 */
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS5                     ((uint32_t)(0x18D8))
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_OFFSET              ((uint32_t)(0xD8))
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_BASEADDRESS5_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_BASEADDRESS5_SHIFT  0U
+
+/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes5 */
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5          ((uint32_t)(0x18DC))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_OFFSET   ((uint32_t)(0xDC))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_STRIDE5_MASK 0xFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_STRIDE5_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_MASK 0x3F0000U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension5 */
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5           ((uint32_t)(0x18E0))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_OFFSET    ((uint32_t)(0xE0))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_LINEWIDTH5_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_LINEWIDTH5_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_LINECOUNT5_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_LINECOUNT5_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits5 */
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5              ((uint32_t)(0x18E4))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_OFFSET       ((uint32_t)(0xE4))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_RESET_VALUE  0x8080808U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_MASK 0xFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_MASK 0xF00U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_MASK 0xF0000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSRED5_MASK 0xF000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSRED5_SHIFT 24U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_ITUFORMAT5_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_ITUFORMAT5_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift5 */
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5             ((uint32_t)(0x18E8))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_OFFSET      ((uint32_t)(0xE8))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_MASK 0x1FU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_MASK 0x1F0000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_MASK 0x1F000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp9_LayerOffset5 */
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5                     ((uint32_t)(0x18EC))
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_OFFSET              ((uint32_t)(0xEC))
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_LAYERXOFFSET5_MASK  0x7FFFU
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_LAYERXOFFSET5_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_LAYERYOFFSET5_MASK  0x7FFF0000U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_LAYERYOFFSET5_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset5 */
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5                ((uint32_t)(0x18F0))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_OFFSET         ((uint32_t)(0xF0))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_RESET_VALUE    0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_MASK 0x7FFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions5 */
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5            ((uint32_t)(0x18F4))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_OFFSET     ((uint32_t)(0xF4))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_RESET_VALUE 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ConstantColor5 */
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5                   ((uint32_t)(0x18F8))
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_OFFSET            ((uint32_t)(0xF8))
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_RESET_VALUE       0U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTALPHA5_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTALPHA5_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTBLUE5_MASK 0xFF00U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTBLUE5_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTGREEN5_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTGREEN5_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTRED5_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTRED5_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp9_LayerProperty5 */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5                   ((uint32_t)(0x18FC))
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_OFFSET            ((uint32_t)(0xFC))
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RESET_VALUE       0x100U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5_MASK    0x30U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5_SHIFT   4U
+/* Field Value: TILEMODE5__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE5__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE5__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5__TILE_PAD 0x2U
+/* Field Value: TILEMODE5__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHASRCENABLE5_MASK 0x100U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHASRCENABLE5_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHACONSTENABLE5_MASK 0x200U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHACONSTENABLE5_SHIFT 9U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHAMASKENABLE5_MASK 0x400U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHAMASKENABLE5_SHIFT 10U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHATRANSENABLE5_MASK 0x800U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHATRANSENABLE5_SHIFT 11U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHASRCENABLE5_MASK 0x1000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHASRCENABLE5_SHIFT 12U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHACONSTENABLE5_MASK 0x2000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHACONSTENABLE5_SHIFT 13U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHAMASKENABLE5_MASK 0x4000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHAMASKENABLE5_SHIFT 14U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHATRANSENABLE5_MASK 0x8000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHATRANSENABLE5_SHIFT 15U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_PREMULCONSTRGB5_MASK 0x10000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_PREMULCONSTRGB5_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5_MASK 0x60000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE5__OFF, No conversion.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5__OFF 0U
+/* Field Value: YUVCONVERSIONMODE5__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE5__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE5__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU709 0x3U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_GAMMAREMOVEENABLE5_MASK 0x100000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_GAMMAREMOVEENABLE5_SHIFT 20U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_CLIPWINDOWENABLE5_MASK 0x40000000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_CLIPWINDOWENABLE5_SHIFT 30U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_SOURCEBUFFERENABLE5_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_SOURCEBUFFERENABLE5_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp9_BaseAddress6 */
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS6                     ((uint32_t)(0x1900))
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_OFFSET              ((uint32_t)(0x100))
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_BASEADDRESS6_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_BASEADDRESS6_SHIFT  0U
+
+/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes6 */
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6          ((uint32_t)(0x1904))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_OFFSET   ((uint32_t)(0x104))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_STRIDE6_MASK 0xFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_STRIDE6_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_MASK 0x3F0000U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension6 */
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6           ((uint32_t)(0x1908))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_OFFSET    ((uint32_t)(0x108))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_LINEWIDTH6_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_LINEWIDTH6_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_LINECOUNT6_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_LINECOUNT6_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits6 */
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6              ((uint32_t)(0x190C))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_OFFSET       ((uint32_t)(0x10C))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_RESET_VALUE  0x8080808U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_MASK 0xFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_MASK 0xF00U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_MASK 0xF0000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSRED6_MASK 0xF000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSRED6_SHIFT 24U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_ITUFORMAT6_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_ITUFORMAT6_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift6 */
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6             ((uint32_t)(0x1910))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_OFFSET      ((uint32_t)(0x110))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_MASK 0x1FU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_MASK 0x1F0000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_MASK 0x1F000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp9_LayerOffset6 */
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6                     ((uint32_t)(0x1914))
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_OFFSET              ((uint32_t)(0x114))
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_LAYERXOFFSET6_MASK  0x7FFFU
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_LAYERXOFFSET6_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_LAYERYOFFSET6_MASK  0x7FFF0000U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_LAYERYOFFSET6_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset6 */
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6                ((uint32_t)(0x1918))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_OFFSET         ((uint32_t)(0x118))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_RESET_VALUE    0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_MASK 0x7FFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions6 */
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6            ((uint32_t)(0x191C))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_OFFSET     ((uint32_t)(0x11C))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_RESET_VALUE 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ConstantColor6 */
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6                   ((uint32_t)(0x1920))
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_OFFSET            ((uint32_t)(0x120))
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_RESET_VALUE       0U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTALPHA6_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTALPHA6_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTBLUE6_MASK 0xFF00U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTBLUE6_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTGREEN6_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTGREEN6_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTRED6_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTRED6_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp9_LayerProperty6 */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6                   ((uint32_t)(0x1924))
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_OFFSET            ((uint32_t)(0x124))
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RESET_VALUE       0x100U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6_MASK    0x30U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6_SHIFT   4U
+/* Field Value: TILEMODE6__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE6__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE6__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6__TILE_PAD 0x2U
+/* Field Value: TILEMODE6__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHASRCENABLE6_MASK 0x100U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHASRCENABLE6_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHACONSTENABLE6_MASK 0x200U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHACONSTENABLE6_SHIFT 9U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHAMASKENABLE6_MASK 0x400U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHAMASKENABLE6_SHIFT 10U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHATRANSENABLE6_MASK 0x800U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHATRANSENABLE6_SHIFT 11U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHASRCENABLE6_MASK 0x1000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHASRCENABLE6_SHIFT 12U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHACONSTENABLE6_MASK 0x2000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHACONSTENABLE6_SHIFT 13U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHAMASKENABLE6_MASK 0x4000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHAMASKENABLE6_SHIFT 14U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHATRANSENABLE6_MASK 0x8000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHATRANSENABLE6_SHIFT 15U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_PREMULCONSTRGB6_MASK 0x10000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_PREMULCONSTRGB6_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6_MASK 0x60000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE6__OFF, No conversion.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6__OFF 0U
+/* Field Value: YUVCONVERSIONMODE6__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE6__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE6__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU709 0x3U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_GAMMAREMOVEENABLE6_MASK 0x100000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_GAMMAREMOVEENABLE6_SHIFT 20U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_CLIPWINDOWENABLE6_MASK 0x40000000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_CLIPWINDOWENABLE6_SHIFT 30U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_SOURCEBUFFERENABLE6_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_SOURCEBUFFERENABLE6_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp9_BaseAddress7 */
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS7                     ((uint32_t)(0x1928))
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_OFFSET              ((uint32_t)(0x128))
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_BASEADDRESS7_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_BASEADDRESS7_SHIFT  0U
+
+/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes7 */
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7          ((uint32_t)(0x192C))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_OFFSET   ((uint32_t)(0x12C))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_STRIDE7_MASK 0xFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_STRIDE7_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_MASK 0x3F0000U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension7 */
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7           ((uint32_t)(0x1930))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_OFFSET    ((uint32_t)(0x130))
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_LINEWIDTH7_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_LINEWIDTH7_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_LINECOUNT7_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_LINECOUNT7_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits7 */
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7              ((uint32_t)(0x1934))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_OFFSET       ((uint32_t)(0x134))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_RESET_VALUE  0x8080808U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_MASK 0xFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_MASK 0xF00U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_MASK 0xF0000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSRED7_MASK 0xF000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSRED7_SHIFT 24U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_ITUFORMAT7_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_ITUFORMAT7_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift7 */
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7             ((uint32_t)(0x1938))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_OFFSET      ((uint32_t)(0x138))
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_MASK 0x1FU
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_MASK 0x1F0000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_MASK 0x1F000000U
+#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp9_LayerOffset7 */
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7                     ((uint32_t)(0x193C))
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_OFFSET              ((uint32_t)(0x13C))
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_LAYERXOFFSET7_MASK  0x7FFFU
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_LAYERXOFFSET7_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_LAYERYOFFSET7_MASK  0x7FFF0000U
+#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_LAYERYOFFSET7_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset7 */
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7                ((uint32_t)(0x1940))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_OFFSET         ((uint32_t)(0x140))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_RESET_VALUE    0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_MASK 0x7FFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions7 */
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7            ((uint32_t)(0x1944))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_OFFSET     ((uint32_t)(0x144))
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_RESET_VALUE 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp9_ConstantColor7 */
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7                   ((uint32_t)(0x1948))
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_OFFSET            ((uint32_t)(0x148))
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_RESET_VALUE       0U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTALPHA7_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTALPHA7_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTBLUE7_MASK 0xFF00U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTBLUE7_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTGREEN7_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTGREEN7_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTRED7_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTRED7_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp9_LayerProperty7 */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7                   ((uint32_t)(0x194C))
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_OFFSET            ((uint32_t)(0x14C))
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RESET_VALUE       0x100U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7_MASK    0x30U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7_SHIFT   4U
+/* Field Value: TILEMODE7__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE7__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE7__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7__TILE_PAD 0x2U
+/* Field Value: TILEMODE7__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHASRCENABLE7_MASK 0x100U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHASRCENABLE7_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHACONSTENABLE7_MASK 0x200U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHACONSTENABLE7_SHIFT 9U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHAMASKENABLE7_MASK 0x400U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHAMASKENABLE7_SHIFT 10U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHATRANSENABLE7_MASK 0x800U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHATRANSENABLE7_SHIFT 11U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHASRCENABLE7_MASK 0x1000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHASRCENABLE7_SHIFT 12U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHACONSTENABLE7_MASK 0x2000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHACONSTENABLE7_SHIFT 13U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHAMASKENABLE7_MASK 0x4000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHAMASKENABLE7_SHIFT 14U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHATRANSENABLE7_MASK 0x8000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHATRANSENABLE7_SHIFT 15U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_PREMULCONSTRGB7_MASK 0x10000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_PREMULCONSTRGB7_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7_MASK 0x60000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE7__OFF, No conversion.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7__OFF 0U
+/* Field Value: YUVCONVERSIONMODE7__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE7__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE7__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU709 0x3U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_GAMMAREMOVEENABLE7_MASK 0x100000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_GAMMAREMOVEENABLE7_SHIFT 20U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_CLIPWINDOWENABLE7_MASK 0x40000000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_CLIPWINDOWENABLE7_SHIFT 30U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_SOURCEBUFFERENABLE7_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_SOURCEBUFFERENABLE7_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp9_FrameDimensions */
+#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS                  ((uint32_t)(0x1950))
+#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_OFFSET           ((uint32_t)(0x150))
+#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_RESET_VALUE      0xEF013FU
+#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_FRAMEWIDTH_MASK  0x3FFFU
+#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_EMPTYFRAME_MASK  0x80000000U
+#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp9_FrameResampling */
+#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING                  ((uint32_t)(0x1954))
+#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_OFFSET           ((uint32_t)(0x154))
+#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_RESET_VALUE      0x104000U
+#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_STARTX_MASK      0x3FU
+#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_STARTX_SHIFT     0U
+#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_STARTY_MASK      0xFC0U
+#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_STARTY_SHIFT     6U
+#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_DELTAX_MASK      0x3F000U
+#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_DELTAX_SHIFT     12U
+#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_DELTAY_MASK      0xFC0000U
+#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_DELTAY_SHIFT     18U
+#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U
+#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp9_WarpControl */
+#define IMXDPUV1_FETCHWARP9_WARPCONTROL                      ((uint32_t)(0x1958))
+#define IMXDPUV1_FETCHWARP9_WARPCONTROL_OFFSET               ((uint32_t)(0x158))
+#define IMXDPUV1_FETCHWARP9_WARPCONTROL_RESET_VALUE          0x20U
+#define IMXDPUV1_FETCHWARP9_WARPCONTROL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPBITSPERPIXEL_MASK 0x3FU
+#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPBITSPERPIXEL_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE_MASK 0x300U
+#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE_SHIFT 8U
+/* Field Value: WARPCOORDINATEMODE__PNT, x and y (sample points).  */
+#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE__PNT 0U
+/* Field Value: WARPCOORDINATEMODE__D_PNT, dx and dy (vectors between adjacent
+ * sample points).  */
+#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE__D_PNT 0x1U
+/* Field Value: WARPCOORDINATEMODE__DD_PNT, ddx and ddy (deltas between adjacent
+ * vectors).  */
+#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE__DD_PNT 0x2U
+#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPSYMMETRICOFFSET_MASK 0x1000U
+#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPSYMMETRICOFFSET_SHIFT 12U
+
+/* Register: IMXDPUV1_fetchwarp9_ArbStartX */
+#define IMXDPUV1_FETCHWARP9_ARBSTARTX                        ((uint32_t)(0x195C))
+#define IMXDPUV1_FETCHWARP9_ARBSTARTX_OFFSET                 ((uint32_t)(0x15C))
+#define IMXDPUV1_FETCHWARP9_ARBSTARTX_RESET_VALUE            0U
+#define IMXDPUV1_FETCHWARP9_ARBSTARTX_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_ARBSTARTX_ARBSTARTX_MASK         0x1FFFFFU
+#define IMXDPUV1_FETCHWARP9_ARBSTARTX_ARBSTARTX_SHIFT        0U
+
+/* Register: IMXDPUV1_fetchwarp9_ArbStartY */
+#define IMXDPUV1_FETCHWARP9_ARBSTARTY                        ((uint32_t)(0x1960))
+#define IMXDPUV1_FETCHWARP9_ARBSTARTY_OFFSET                 ((uint32_t)(0x160))
+#define IMXDPUV1_FETCHWARP9_ARBSTARTY_RESET_VALUE            0U
+#define IMXDPUV1_FETCHWARP9_ARBSTARTY_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_ARBSTARTY_ARBSTARTY_MASK         0x1FFFFFU
+#define IMXDPUV1_FETCHWARP9_ARBSTARTY_ARBSTARTY_SHIFT        0U
+
+/* Register: IMXDPUV1_fetchwarp9_ArbDelta */
+#define IMXDPUV1_FETCHWARP9_ARBDELTA                         ((uint32_t)(0x1964))
+#define IMXDPUV1_FETCHWARP9_ARBDELTA_OFFSET                  ((uint32_t)(0x164))
+#define IMXDPUV1_FETCHWARP9_ARBDELTA_RESET_VALUE             0U
+#define IMXDPUV1_FETCHWARP9_ARBDELTA_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAXX_MASK         0xFFU
+#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAXX_SHIFT        0U
+#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAXY_MASK         0xFF00U
+#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAXY_SHIFT        8U
+#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAYX_MASK         0xFF0000U
+#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAYX_SHIFT        16U
+#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAYY_MASK         0xFF000000U
+#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAYY_SHIFT        24U
+
+/* Register: IMXDPUV1_fetchwarp9_FIRPositions */
+#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS                     ((uint32_t)(0x1968))
+#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_OFFSET              ((uint32_t)(0x168))
+#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_RESET_VALUE         0xA965U
+#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR0POSITION_MASK   0xFU
+#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR0POSITION_SHIFT  0U
+#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR1POSITION_MASK   0xF0U
+#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR1POSITION_SHIFT  4U
+#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR2POSITION_MASK   0xF00U
+#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR2POSITION_SHIFT  8U
+#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR3POSITION_MASK   0xF000U
+#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR3POSITION_SHIFT  12U
+
+/* Register: IMXDPUV1_fetchwarp9_FIRCoefficients */
+#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS                  ((uint32_t)(0x196C))
+#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_OFFSET           ((uint32_t)(0x16C))
+#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_RESET_VALUE      0x20U
+#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR0COEFFICIENT_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR0COEFFICIENT_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR1COEFFICIENT_MASK 0xFF00U
+#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR1COEFFICIENT_SHIFT 8U
+#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR2COEFFICIENT_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR2COEFFICIENT_SHIFT 16U
+#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR3COEFFICIENT_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR3COEFFICIENT_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp9_Control */
+#define IMXDPUV1_FETCHWARP9_CONTROL                          ((uint32_t)(0x1970))
+#define IMXDPUV1_FETCHWARP9_CONTROL_OFFSET                   ((uint32_t)(0x170))
+#define IMXDPUV1_FETCHWARP9_CONTROL_RESET_VALUE              0x10000U
+#define IMXDPUV1_FETCHWARP9_CONTROL_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE_MASK          0x7U
+#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE_SHIFT         0U
+/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin.
+ * Hor/ver increments using DeltaX/Y and DeltaSwap setup.  */
+#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__NORMAL       0U
+/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source
+ * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver
+ * increments = (1,0)/(0,1).  */
+#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__DECODE       0x1U
+/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary
+ * warping (filter is active). Coordinates are read from frame input
+ * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY
+ * must be setup.  */
+#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__ARBITRARY    0x2U
+/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective
+ * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver
+ * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates.  */
+#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__PERSPECTIVE  0x3U
+/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer
+ * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments
+ * = (1,0)/(0,1). All corellated window widths and horizontal offsets must
+ * be even.  */
+#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__YUV422       0x4U
+/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter
+ * is active). First sample at AffineStartX/Y. Hor/ver increments using
+ * AffineDeltaXX/XY/YX/YY. Cartesian coordinates.  */
+#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__AFFINE       0x5U
+#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT_MASK         0x18U
+#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT_SHIFT        3U
+/* Field Value: INPUTSELECT__INACTIVE, Not used.  */
+#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT__INACTIVE    0U
+/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV
+ * or source alpha buffer).  */
+#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT__COMPPACK    0x1U
+/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply
+ * stage (mask alpha buffer).  */
+#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT__ALPHAMASK   0x2U
+/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate
+ * buffer).  */
+#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT__COORDINATE  0x3U
+#define IMXDPUV1_FETCHWARP9_CONTROL_RAWPIXEL_MASK            0x80U
+#define IMXDPUV1_FETCHWARP9_CONTROL_RAWPIXEL_SHIFT           7U
+#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPCOLOR_MASK           0x10000U
+#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPCOLOR_SHIFT          16U
+/* Field Value: CLIPCOLOR__NULL, Null color.  */
+#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPCOLOR__NULL          0U
+/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer
+ * (or layer 0 when Fetch unit has one layer only). The color is then the
+ * layer's source or tiling color.  */
+#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPCOLOR__LAYER         0x1U
+#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPLAYER_MASK           0xE0000U
+#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPLAYER_SHIFT          17U
+#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE_MASK          0x700000U
+#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE_SHIFT         20U
+/* Field Value: FILTERMODE__NEAREST, Chooses pixel closest to sample point  */
+#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__NEAREST      0U
+/* Field Value: FILTERMODE__BILINEAR, Calculates result from 4 pixels closest
+ * to sample point  */
+#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__BILINEAR     0x1U
+/* Field Value: FILTERMODE__FIR2, FIR mode with 2 programmable pixel positions
+ * and coefficients  */
+#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__FIR2         0x2U
+/* Field Value: FILTERMODE__FIR4, FIR mode with 4 programmable pixel positions
+ * and coefficients  */
+#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__FIR4         0x3U
+/* Field Value: FILTERMODE__HOR_LINEAR, Calculates result from 2 pixels closest
+ * to the sample point and on the same line  */
+#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__HOR_LINEAR   0x4U
+
+/* Register: IMXDPUV1_fetchwarp9_TriggerEnable */
+#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE                    ((uint32_t)(0x1974))
+#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_OFFSET             ((uint32_t)(0x174))
+#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_RESET_VALUE        0U
+#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_SHDLDREQ_MASK      0xFFU
+#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_SHDLDREQ_SHIFT     0U
+
+/* Register: IMXDPUV1_fetchwarp9_ControlTrigger */
+#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER                   ((uint32_t)(0x1978))
+#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_OFFSET            ((uint32_t)(0x178))
+#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_RESET_VALUE       0U
+#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_RESET_MASK        0xFFFFFFFEU
+#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_SHDTOKGEN_MASK    0x1U
+#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_SHDTOKGEN_SHIFT   0U
+
+/* Register: IMXDPUV1_fetchwarp9_Start */
+#define IMXDPUV1_FETCHWARP9_START                            ((uint32_t)(0x197C))
+#define IMXDPUV1_FETCHWARP9_START_OFFSET                     ((uint32_t)(0x17C))
+#define IMXDPUV1_FETCHWARP9_START_RESET_VALUE                0U
+#define IMXDPUV1_FETCHWARP9_START_RESET_MASK                 0xFFFFFFFEU
+#define IMXDPUV1_FETCHWARP9_START_START_MASK                 0x1U
+#define IMXDPUV1_FETCHWARP9_START_START_SHIFT                0U
+
+/* Register: IMXDPUV1_fetchwarp9_FetchType */
+#define IMXDPUV1_FETCHWARP9_FETCHTYPE                        ((uint32_t)(0x1980))
+#define IMXDPUV1_FETCHWARP9_FETCHTYPE_OFFSET                 ((uint32_t)(0x180))
+#define IMXDPUV1_FETCHWARP9_FETCHTYPE_RESET_VALUE            0U
+#define IMXDPUV1_FETCHWARP9_FETCHTYPE_RESET_MASK             0xFFFFFFF0U
+#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE_MASK         0xFU
+#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE_SHIFT        0U
+/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder.  */
+#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__DECODE      0U
+/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers).  */
+#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__LAYER       0x1U
+/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional
+ * plane (8 layers).  */
+#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__WARP        0x2U
+/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha,
+ * chroma and coordinate planes.  */
+#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__ECO         0x3U
+/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and
+ * arbitrary warping.  */
+#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__PERSP       0x4U
+/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping.  */
+#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__ROT         0x5U
+/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced
+ * feature set.  */
+#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__DECODEL     0x6U
+/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers),
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__LAYERL      0x7U
+/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping,
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__ROTL        0x8U
+
+/* Register: IMXDPUV1_fetchwarp9_BurstBufferProperties */
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES            ((uint32_t)(0x1984))
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_OFFSET     ((uint32_t)(0x184))
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_RESET_VALUE 0U
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U
+
+/* Register: IMXDPUV1_fetchwarp9_Status */
+#define IMXDPUV1_FETCHWARP9_STATUS                           ((uint32_t)(0x1988))
+#define IMXDPUV1_FETCHWARP9_STATUS_OFFSET                    ((uint32_t)(0x188))
+#define IMXDPUV1_FETCHWARP9_STATUS_RESET_VALUE               0U
+#define IMXDPUV1_FETCHWARP9_STATUS_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP9_STATUS_WRITETIMEOUT_MASK         0x1U
+#define IMXDPUV1_FETCHWARP9_STATUS_WRITETIMEOUT_SHIFT        0U
+#define IMXDPUV1_FETCHWARP9_STATUS_READTIMEOUT_MASK          0x10U
+#define IMXDPUV1_FETCHWARP9_STATUS_READTIMEOUT_SHIFT         4U
+
+/* Register: IMXDPUV1_fetchwarp9_HiddenStatus */
+#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS                     ((uint32_t)(0x198C))
+#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_OFFSET              ((uint32_t)(0x18C))
+#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_RESET_MASK          0xFFFF008EU
+#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSBUSY_MASK     0x1U
+#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSBUSY_SHIFT    0U
+#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U
+#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U
+#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSREQUEST_MASK  0x20U
+#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U
+#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U
+#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U
+#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_SHADOWSTATUS_MASK   0xFF00U
+#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_SHADOWSTATUS_SHIFT  8U
+
+/* Register: IMXDPUV1_fetcheco9_LockUnlock */
+#define IMXDPUV1_FETCHECO9_LOCKUNLOCK                        ((uint32_t)(0x1C00))
+#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_OFFSET                 ((uint32_t)(0))
+#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_RESET_VALUE            0U
+#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_RESET_MASK             0U
+#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK_SHIFT       0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY   0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_fetcheco9_LockStatus */
+#define IMXDPUV1_FETCHECO9_LOCKSTATUS                        ((uint32_t)(0x1C04))
+#define IMXDPUV1_FETCHECO9_LOCKSTATUS_OFFSET                 ((uint32_t)(0x4))
+#define IMXDPUV1_FETCHECO9_LOCKSTATUS_RESET_VALUE            0U
+#define IMXDPUV1_FETCHECO9_LOCKSTATUS_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO9_LOCKSTATUS_LOCKSTATUS_MASK        0x1U
+#define IMXDPUV1_FETCHECO9_LOCKSTATUS_LOCKSTATUS_SHIFT       0U
+#define IMXDPUV1_FETCHECO9_LOCKSTATUS_PRIVILEGESTATUS_MASK   0x10U
+#define IMXDPUV1_FETCHECO9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT  4U
+#define IMXDPUV1_FETCHECO9_LOCKSTATUS_FREEZESTATUS_MASK      0x100U
+#define IMXDPUV1_FETCHECO9_LOCKSTATUS_FREEZESTATUS_SHIFT     8U
+
+/* Register: IMXDPUV1_fetcheco9_StaticControl */
+#define IMXDPUV1_FETCHECO9_STATICCONTROL                     ((uint32_t)(0x1C08))
+#define IMXDPUV1_FETCHECO9_STATICCONTROL_OFFSET              ((uint32_t)(0x8))
+#define IMXDPUV1_FETCHECO9_STATICCONTROL_RESET_VALUE         0U
+#define IMXDPUV1_FETCHECO9_STATICCONTROL_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO9_STATICCONTROL_SHDEN_MASK          0x1U
+#define IMXDPUV1_FETCHECO9_STATICCONTROL_SHDEN_SHIFT         0U
+#define IMXDPUV1_FETCHECO9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U
+#define IMXDPUV1_FETCHECO9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco9_BurstBufferManagement */
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT             ((uint32_t)(0x1C0C))
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_OFFSET      ((uint32_t)(0xC))
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U
+/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the
+ * Display Controller. Works also for Blit Engine with marginal performance
+ * impact.  */
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U
+/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit
+ * Engine.  */
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U
+
+/* Register: IMXDPUV1_fetcheco9_BaseAddress0 */
+#define IMXDPUV1_FETCHECO9_BASEADDRESS0                      ((uint32_t)(0x1C10))
+#define IMXDPUV1_FETCHECO9_BASEADDRESS0_OFFSET               ((uint32_t)(0x10))
+#define IMXDPUV1_FETCHECO9_BASEADDRESS0_RESET_VALUE          0U
+#define IMXDPUV1_FETCHECO9_BASEADDRESS0_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO9_BASEADDRESS0_BASEADDRESS0_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO9_BASEADDRESS0_BASEADDRESS0_SHIFT   0U
+
+/* Register: IMXDPUV1_fetcheco9_SourceBufferAttributes0 */
+#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0           ((uint32_t)(0x1C14))
+#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_OFFSET    ((uint32_t)(0x14))
+#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU
+#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU
+#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U
+#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U
+#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco9_SourceBufferDimension0 */
+#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0            ((uint32_t)(0x1C18))
+#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_OFFSET     ((uint32_t)(0x18))
+#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco9_ColorComponentBits0 */
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0               ((uint32_t)(0x1C1C))
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_OFFSET        ((uint32_t)(0x1C))
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_RESET_VALUE   0x8080808U
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U
+
+/* Register: IMXDPUV1_fetcheco9_ColorComponentShift0 */
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0              ((uint32_t)(0x1C20))
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_OFFSET       ((uint32_t)(0x20))
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_RESET_VALUE  0x18100800U
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U
+#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_fetcheco9_LayerOffset0 */
+#define IMXDPUV1_FETCHECO9_LAYEROFFSET0                      ((uint32_t)(0x1C24))
+#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_OFFSET               ((uint32_t)(0x24))
+#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_RESET_VALUE          0U
+#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_LAYERXOFFSET0_MASK   0x7FFFU
+#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_LAYERXOFFSET0_SHIFT  0U
+#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_LAYERYOFFSET0_MASK   0x7FFF0000U
+#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_LAYERYOFFSET0_SHIFT  16U
+
+/* Register: IMXDPUV1_fetcheco9_ClipWindowOffset0 */
+#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0                 ((uint32_t)(0x1C28))
+#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_OFFSET          ((uint32_t)(0x28))
+#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_RESET_VALUE     0U
+#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU
+#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U
+#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco9_ClipWindowDimensions0 */
+#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0             ((uint32_t)(0x1C2C))
+#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_OFFSET      ((uint32_t)(0x2C))
+#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U
+#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco9_ConstantColor0 */
+#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0                    ((uint32_t)(0x1C30))
+#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_OFFSET             ((uint32_t)(0x30))
+#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_RESET_VALUE        0U
+#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU
+#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U
+#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U
+#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTRED0_MASK  0xFF000000U
+#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_fetcheco9_LayerProperty0 */
+#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0                    ((uint32_t)(0x1C34))
+#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_OFFSET             ((uint32_t)(0x34))
+#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_RESET_VALUE        0x80000000U
+#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0_MASK     0x30U
+#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0_SHIFT    4U
+/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U
+/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U
+#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U
+#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U
+#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U
+
+/* Register: IMXDPUV1_fetcheco9_FrameDimensions */
+#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS                   ((uint32_t)(0x1C38))
+#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_OFFSET            ((uint32_t)(0x38))
+#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_RESET_VALUE       0xEF013FU
+#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_FRAMEWIDTH_MASK   0x3FFFU
+#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT  0U
+#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK  0x3FFF0000U
+#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U
+#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_EMPTYFRAME_MASK   0x80000000U
+#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT  31U
+
+/* Register: IMXDPUV1_fetcheco9_FrameResampling */
+#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING                   ((uint32_t)(0x1C3C))
+#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_OFFSET            ((uint32_t)(0x3C))
+#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_RESET_VALUE       0x104000U
+#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_STARTX_MASK       0x3FU
+#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_STARTX_SHIFT      0U
+#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_STARTY_MASK       0xFC0U
+#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_STARTY_SHIFT      6U
+#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_DELTAX_MASK       0x3F000U
+#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_DELTAX_SHIFT      12U
+#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_DELTAY_MASK       0xFC0000U
+#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_DELTAY_SHIFT      18U
+#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U
+#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U
+
+/* Register: IMXDPUV1_fetcheco9_Control */
+#define IMXDPUV1_FETCHECO9_CONTROL                           ((uint32_t)(0x1C40))
+#define IMXDPUV1_FETCHECO9_CONTROL_OFFSET                    ((uint32_t)(0x40))
+#define IMXDPUV1_FETCHECO9_CONTROL_RESET_VALUE               0x10000U
+#define IMXDPUV1_FETCHECO9_CONTROL_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO9_CONTROL_RAWPIXEL_MASK             0x80U
+#define IMXDPUV1_FETCHECO9_CONTROL_RAWPIXEL_SHIFT            7U
+#define IMXDPUV1_FETCHECO9_CONTROL_CLIPCOLOR_MASK            0x10000U
+#define IMXDPUV1_FETCHECO9_CONTROL_CLIPCOLOR_SHIFT           16U
+/* Field Value: CLIPCOLOR__NULL, Null color.  */
+#define IMXDPUV1_FETCHECO9_CONTROL_CLIPCOLOR__NULL           0U
+/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer
+ * (or layer 0 when Fetch unit has one layer only). The color is then the
+ * layer's source or tiling color.  */
+#define IMXDPUV1_FETCHECO9_CONTROL_CLIPCOLOR__LAYER          0x1U
+
+/* Register: IMXDPUV1_fetcheco9_ControlTrigger */
+#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER                    ((uint32_t)(0x1C44))
+#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_OFFSET             ((uint32_t)(0x44))
+#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_RESET_VALUE        0U
+#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_RESET_MASK         0xFFFFFFFEU
+#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_SHDTOKGEN_MASK     0x1U
+#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_SHDTOKGEN_SHIFT    0U
+
+/* Register: IMXDPUV1_fetcheco9_Start */
+#define IMXDPUV1_FETCHECO9_START                             ((uint32_t)(0x1C48))
+#define IMXDPUV1_FETCHECO9_START_OFFSET                      ((uint32_t)(0x48))
+#define IMXDPUV1_FETCHECO9_START_RESET_VALUE                 0U
+#define IMXDPUV1_FETCHECO9_START_RESET_MASK                  0xFFFFFFFEU
+#define IMXDPUV1_FETCHECO9_START_START_MASK                  0x1U
+#define IMXDPUV1_FETCHECO9_START_START_SHIFT                 0U
+
+/* Register: IMXDPUV1_fetcheco9_FetchType */
+#define IMXDPUV1_FETCHECO9_FETCHTYPE                         ((uint32_t)(0x1C4C))
+#define IMXDPUV1_FETCHECO9_FETCHTYPE_OFFSET                  ((uint32_t)(0x4C))
+#define IMXDPUV1_FETCHECO9_FETCHTYPE_RESET_VALUE             0U
+#define IMXDPUV1_FETCHECO9_FETCHTYPE_RESET_MASK              0xFFFFFFF0U
+#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE_MASK          0xFU
+#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE_SHIFT         0U
+/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder.  */
+#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__DECODE       0U
+/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers).  */
+#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__LAYER        0x1U
+/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional
+ * plane (8 layers).  */
+#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__WARP         0x2U
+/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha,
+ * chroma and coordinate planes.  */
+#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__ECO          0x3U
+/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and
+ * arbitrary warping.  */
+#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__PERSP        0x4U
+/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping.  */
+#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__ROT          0x5U
+/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced
+ * feature set.  */
+#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__DECODEL      0x6U
+/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers),
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__LAYERL       0x7U
+/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping,
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__ROTL         0x8U
+
+/* Register: IMXDPUV1_fetcheco9_BurstBufferProperties */
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES             ((uint32_t)(0x1C50))
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_OFFSET      ((uint32_t)(0x50))
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_RESET_VALUE 0U
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_RESET_MASK  0xFFFFE000U
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U
+#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U
+
+/* Register: IMXDPUV1_fetcheco9_HiddenStatus */
+#define IMXDPUV1_FETCHECO9_HIDDENSTATUS                      ((uint32_t)(0x1C54))
+#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_OFFSET               ((uint32_t)(0x54))
+#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_RESET_VALUE          0U
+#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_RESET_MASK           0xFFFF008EU
+#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSBUSY_MASK      0x1U
+#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSBUSY_SHIFT     0U
+#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U
+#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U
+#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSREQUEST_MASK   0x20U
+#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSREQUEST_SHIFT  5U
+#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSCOMPLETE_MASK  0x40U
+#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U
+#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_SHADOWSTATUS_MASK    0xFF00U
+#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_SHADOWSTATUS_SHIFT   8U
+
+/* Register: IMXDPUV1_rop9_LockUnlock */
+#define IMXDPUV1_ROP9_LOCKUNLOCK                             ((uint32_t)(0x2000))
+#define IMXDPUV1_ROP9_LOCKUNLOCK_OFFSET                      ((uint32_t)(0))
+#define IMXDPUV1_ROP9_LOCKUNLOCK_RESET_VALUE                 0U
+#define IMXDPUV1_ROP9_LOCKUNLOCK_RESET_MASK                  0U
+#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK_MASK             0xFFFFFFFFU
+#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK_SHIFT            0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY        0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY      0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY   0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY      0xFBE8B1E6U
+
+/* Register: IMXDPUV1_rop9_LockStatus */
+#define IMXDPUV1_ROP9_LOCKSTATUS                             ((uint32_t)(0x2004))
+#define IMXDPUV1_ROP9_LOCKSTATUS_OFFSET                      ((uint32_t)(0x4))
+#define IMXDPUV1_ROP9_LOCKSTATUS_RESET_VALUE                 0U
+#define IMXDPUV1_ROP9_LOCKSTATUS_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_ROP9_LOCKSTATUS_LOCKSTATUS_MASK             0x1U
+#define IMXDPUV1_ROP9_LOCKSTATUS_LOCKSTATUS_SHIFT            0U
+#define IMXDPUV1_ROP9_LOCKSTATUS_PRIVILEGESTATUS_MASK        0x10U
+#define IMXDPUV1_ROP9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT       4U
+#define IMXDPUV1_ROP9_LOCKSTATUS_FREEZESTATUS_MASK           0x100U
+#define IMXDPUV1_ROP9_LOCKSTATUS_FREEZESTATUS_SHIFT          8U
+
+/* Register: IMXDPUV1_rop9_StaticControl */
+#define IMXDPUV1_ROP9_STATICCONTROL                          ((uint32_t)(0x2008))
+#define IMXDPUV1_ROP9_STATICCONTROL_OFFSET                   ((uint32_t)(0x8))
+#define IMXDPUV1_ROP9_STATICCONTROL_RESET_VALUE              0U
+#define IMXDPUV1_ROP9_STATICCONTROL_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_ROP9_STATICCONTROL_SHDEN_MASK               0x1U
+#define IMXDPUV1_ROP9_STATICCONTROL_SHDEN_SHIFT              0U
+
+/* Register: IMXDPUV1_rop9_Control */
+#define IMXDPUV1_ROP9_CONTROL                                ((uint32_t)(0x200C))
+#define IMXDPUV1_ROP9_CONTROL_OFFSET                         ((uint32_t)(0xC))
+#define IMXDPUV1_ROP9_CONTROL_RESET_VALUE                    0U
+#define IMXDPUV1_ROP9_CONTROL_RESET_MASK                     0xFFFFFFFFU
+#define IMXDPUV1_ROP9_CONTROL_MODE_MASK                      0x1U
+#define IMXDPUV1_ROP9_CONTROL_MODE_SHIFT                     0U
+/* Field Value: MODE__NEUTRAL, Neutral mode  */
+#define IMXDPUV1_ROP9_CONTROL_MODE__NEUTRAL                  0U
+/* Field Value: MODE__OPERATION, Normal Operation  */
+#define IMXDPUV1_ROP9_CONTROL_MODE__OPERATION                0x1U
+#define IMXDPUV1_ROP9_CONTROL_ALPHAMODE_MASK                 0x10U
+#define IMXDPUV1_ROP9_CONTROL_ALPHAMODE_SHIFT                4U
+/* Field Value: ALPHAMODE__ROP, Normal raster operation mode, using the operation
+ * index  */
+#define IMXDPUV1_ROP9_CONTROL_ALPHAMODE__ROP                 0U
+/* Field Value: ALPHAMODE__ADD, Add mode, adds this component from all enabled
+ * inputs, clamps to 1  */
+#define IMXDPUV1_ROP9_CONTROL_ALPHAMODE__ADD                 0x1U
+#define IMXDPUV1_ROP9_CONTROL_BLUEMODE_MASK                  0x20U
+#define IMXDPUV1_ROP9_CONTROL_BLUEMODE_SHIFT                 5U
+/* Field Value: BLUEMODE__ROP, Normal raster operation mode, using the operation
+ * index  */
+#define IMXDPUV1_ROP9_CONTROL_BLUEMODE__ROP                  0U
+/* Field Value: BLUEMODE__ADD, Add mode, adds this component from all enabled
+ * inputs, clamps to 1  */
+#define IMXDPUV1_ROP9_CONTROL_BLUEMODE__ADD                  0x1U
+#define IMXDPUV1_ROP9_CONTROL_GREENMODE_MASK                 0x40U
+#define IMXDPUV1_ROP9_CONTROL_GREENMODE_SHIFT                6U
+/* Field Value: GREENMODE__ROP, Normal raster operation mode, using the operation
+ * index  */
+#define IMXDPUV1_ROP9_CONTROL_GREENMODE__ROP                 0U
+/* Field Value: GREENMODE__ADD, Add mode, adds this component from all enabled
+ * inputs, clamps to 1  */
+#define IMXDPUV1_ROP9_CONTROL_GREENMODE__ADD                 0x1U
+#define IMXDPUV1_ROP9_CONTROL_REDMODE_MASK                   0x80U
+#define IMXDPUV1_ROP9_CONTROL_REDMODE_SHIFT                  7U
+/* Field Value: REDMODE__ROP, Normal raster operation mode, using the operation
+ * index  */
+#define IMXDPUV1_ROP9_CONTROL_REDMODE__ROP                   0U
+/* Field Value: REDMODE__ADD, Add mode, adds this component from all enabled
+ * inputs, clamps to 1  */
+#define IMXDPUV1_ROP9_CONTROL_REDMODE__ADD                   0x1U
+#define IMXDPUV1_ROP9_CONTROL_PRIMDIV2_MASK                  0x100U
+#define IMXDPUV1_ROP9_CONTROL_PRIMDIV2_SHIFT                 8U
+/* Field Value: PRIMDIV2__BYPASS, No change to input  */
+#define IMXDPUV1_ROP9_CONTROL_PRIMDIV2__BYPASS               0U
+/* Field Value: PRIMDIV2__DIVIDEBY2, Input is divided by two/shift to the
+ * right by one  */
+#define IMXDPUV1_ROP9_CONTROL_PRIMDIV2__DIVIDEBY2            0x1U
+#define IMXDPUV1_ROP9_CONTROL_SECDIV2_MASK                   0x200U
+#define IMXDPUV1_ROP9_CONTROL_SECDIV2_SHIFT                  9U
+/* Field Value: SECDIV2__BYPASS, No change to input  */
+#define IMXDPUV1_ROP9_CONTROL_SECDIV2__BYPASS                0U
+/* Field Value: SECDIV2__DIVIDEBY2, Input is divided by two/shift to the right
+ * by one  */
+#define IMXDPUV1_ROP9_CONTROL_SECDIV2__DIVIDEBY2             0x1U
+#define IMXDPUV1_ROP9_CONTROL_TERTDIV2_MASK                  0x400U
+#define IMXDPUV1_ROP9_CONTROL_TERTDIV2_SHIFT                 10U
+/* Field Value: TERTDIV2__BYPASS, No change to input  */
+#define IMXDPUV1_ROP9_CONTROL_TERTDIV2__BYPASS               0U
+/* Field Value: TERTDIV2__DIVIDEBY2, Input is divided by two/shift to the
+ * right by one  */
+#define IMXDPUV1_ROP9_CONTROL_TERTDIV2__DIVIDEBY2            0x1U
+
+/* Register: IMXDPUV1_rop9_RasterOperationIndices */
+#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES                 ((uint32_t)(0x2010))
+#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OFFSET          ((uint32_t)(0x10))
+#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_RESET_VALUE     0U
+#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXALPHA_MASK 0xFFU
+#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXALPHA_SHIFT 0U
+#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXBLUE_MASK 0xFF00U
+#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXBLUE_SHIFT 8U
+#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXGREEN_MASK 0xFF0000U
+#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXGREEN_SHIFT 16U
+#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXRED_MASK 0xFF000000U
+#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXRED_SHIFT 24U
+
+/* Register: IMXDPUV1_rop9_PrimControlWord */
+#define IMXDPUV1_ROP9_PRIMCONTROLWORD                        ((uint32_t)(0x2014))
+#define IMXDPUV1_ROP9_PRIMCONTROLWORD_OFFSET                 ((uint32_t)(0x14))
+#define IMXDPUV1_ROP9_PRIMCONTROLWORD_RESET_VALUE            0U
+#define IMXDPUV1_ROP9_PRIMCONTROLWORD_RESET_MASK             0U
+#define IMXDPUV1_ROP9_PRIMCONTROLWORD_P_VAL_MASK             0xFFFFFFFFU
+#define IMXDPUV1_ROP9_PRIMCONTROLWORD_P_VAL_SHIFT            0U
+
+/* Register: IMXDPUV1_rop9_SecControlWord */
+#define IMXDPUV1_ROP9_SECCONTROLWORD                         ((uint32_t)(0x2018))
+#define IMXDPUV1_ROP9_SECCONTROLWORD_OFFSET                  ((uint32_t)(0x18))
+#define IMXDPUV1_ROP9_SECCONTROLWORD_RESET_VALUE             0U
+#define IMXDPUV1_ROP9_SECCONTROLWORD_RESET_MASK              0U
+#define IMXDPUV1_ROP9_SECCONTROLWORD_S_VAL_MASK              0xFFFFFFFFU
+#define IMXDPUV1_ROP9_SECCONTROLWORD_S_VAL_SHIFT             0U
+
+/* Register: IMXDPUV1_rop9_TertControlWord */
+#define IMXDPUV1_ROP9_TERTCONTROLWORD                        ((uint32_t)(0x201C))
+#define IMXDPUV1_ROP9_TERTCONTROLWORD_OFFSET                 ((uint32_t)(0x1C))
+#define IMXDPUV1_ROP9_TERTCONTROLWORD_RESET_VALUE            0U
+#define IMXDPUV1_ROP9_TERTCONTROLWORD_RESET_MASK             0U
+#define IMXDPUV1_ROP9_TERTCONTROLWORD_T_VAL_MASK             0xFFFFFFFFU
+#define IMXDPUV1_ROP9_TERTCONTROLWORD_T_VAL_SHIFT            0U
+
+/* Register: IMXDPUV1_clut9_LockUnlock */
+#define IMXDPUV1_CLUT9_LOCKUNLOCK                            ((uint32_t)(0x2400))
+#define IMXDPUV1_CLUT9_LOCKUNLOCK_OFFSET                     ((uint32_t)(0))
+#define IMXDPUV1_CLUT9_LOCKUNLOCK_RESET_VALUE                0U
+#define IMXDPUV1_CLUT9_LOCKUNLOCK_RESET_MASK                 0U
+#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK_MASK            0xFFFFFFFFU
+#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK_SHIFT           0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY       0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY     0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY  0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY     0xFBE8B1E6U
+
+/* Register: IMXDPUV1_clut9_LockStatus */
+#define IMXDPUV1_CLUT9_LOCKSTATUS                            ((uint32_t)(0x2404))
+#define IMXDPUV1_CLUT9_LOCKSTATUS_OFFSET                     ((uint32_t)(0x4))
+#define IMXDPUV1_CLUT9_LOCKSTATUS_RESET_VALUE                0U
+#define IMXDPUV1_CLUT9_LOCKSTATUS_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_CLUT9_LOCKSTATUS_LOCKSTATUS_MASK            0x1U
+#define IMXDPUV1_CLUT9_LOCKSTATUS_LOCKSTATUS_SHIFT           0U
+#define IMXDPUV1_CLUT9_LOCKSTATUS_PRIVILEGESTATUS_MASK       0x10U
+#define IMXDPUV1_CLUT9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT      4U
+#define IMXDPUV1_CLUT9_LOCKSTATUS_FREEZESTATUS_MASK          0x100U
+#define IMXDPUV1_CLUT9_LOCKSTATUS_FREEZESTATUS_SHIFT         8U
+
+/* Register: IMXDPUV1_clut9_StaticControl */
+#define IMXDPUV1_CLUT9_STATICCONTROL                         ((uint32_t)(0x2408))
+#define IMXDPUV1_CLUT9_STATICCONTROL_OFFSET                  ((uint32_t)(0x8))
+#define IMXDPUV1_CLUT9_STATICCONTROL_RESET_VALUE             0U
+#define IMXDPUV1_CLUT9_STATICCONTROL_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_CLUT9_STATICCONTROL_SHDEN_MASK              0x1U
+#define IMXDPUV1_CLUT9_STATICCONTROL_SHDEN_SHIFT             0U
+
+/* Register: IMXDPUV1_clut9_UnshadowedControl */
+#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL                     ((uint32_t)(0x240C))
+#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_OFFSET              ((uint32_t)(0xC))
+#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_RESET_VALUE         0U
+#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN_MASK           0x1U
+#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN_SHIFT          0U
+/* Field Value: B_EN__DISABLE, disable  */
+#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN__DISABLE       0U
+/* Field Value: B_EN__ENABLE, enable  */
+#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN__ENABLE        0x1U
+#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN_MASK           0x2U
+#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN_SHIFT          1U
+/* Field Value: G_EN__DISABLE, disable  */
+#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN__DISABLE       0U
+/* Field Value: G_EN__ENABLE, enable  */
+#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN__ENABLE        0x1U
+#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN_MASK           0x4U
+#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN_SHIFT          2U
+/* Field Value: R_EN__DISABLE, disable  */
+#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN__DISABLE       0U
+/* Field Value: R_EN__ENABLE, enable  */
+#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN__ENABLE        0x1U
+
+/* Register: IMXDPUV1_clut9_Control */
+#define IMXDPUV1_CLUT9_CONTROL                               ((uint32_t)(0x2410))
+#define IMXDPUV1_CLUT9_CONTROL_OFFSET                        ((uint32_t)(0x10))
+#define IMXDPUV1_CLUT9_CONTROL_RESET_VALUE                   0x800U
+#define IMXDPUV1_CLUT9_CONTROL_RESET_MASK                    0xFFFFFFFFU
+#define IMXDPUV1_CLUT9_CONTROL_MODE_MASK                     0x3U
+#define IMXDPUV1_CLUT9_CONTROL_MODE_SHIFT                    0U
+/* Field Value: MODE__NEUTRAL, module in neutral mode, input data is bypassed
+ * to the output  */
+#define IMXDPUV1_CLUT9_CONTROL_MODE__NEUTRAL                 0U
+/* Field Value: MODE__LUT, module in color lookup mode (LUT holds a 10bit
+ * color value for CLut derivate and 8bit color value for CLutL derivate
+ * for each input color)  */
+#define IMXDPUV1_CLUT9_CONTROL_MODE__LUT                     0x1U
+/* Field Value: MODE__INDEX_10BIT, module in 10bit color index table mode
+ * (LUT holds a 3x10bit color value for derivate CLut and 3x8bit color value
+ * for CLUTL derivate, indexed with the red input color)  */
+#define IMXDPUV1_CLUT9_CONTROL_MODE__INDEX_10BIT             0x2U
+/* Field Value: MODE__INDEX_RGBA, module in RGBA color index table mode (LUT
+ * holds a 3x8bit color value and a 6bit alpha value for CLut derivate
+ * and 3x6bit color value and 6bit alpha value for CLutL derivate, indexed
+ * with the red input color)  */
+#define IMXDPUV1_CLUT9_CONTROL_MODE__INDEX_RGBA              0x3U
+#define IMXDPUV1_CLUT9_CONTROL_COL_8BIT_MASK                 0x10U
+#define IMXDPUV1_CLUT9_CONTROL_COL_8BIT_SHIFT                4U
+/* Field Value: COL_8BIT__DISABLE, color is 10bit output  */
+#define IMXDPUV1_CLUT9_CONTROL_COL_8BIT__DISABLE             0U
+/* Field Value: COL_8BIT__ENABLE, color is 8bit output (dithering of internal
+ * 10bit value)  */
+#define IMXDPUV1_CLUT9_CONTROL_COL_8BIT__ENABLE              0x1U
+#define IMXDPUV1_CLUT9_CONTROL_ALPHAMASK_MASK                0x20U
+#define IMXDPUV1_CLUT9_CONTROL_ALPHAMASK_SHIFT               5U
+/* Field Value: ALPHAMASK__DISABLE, Alpha mask mode disabled  */
+#define IMXDPUV1_CLUT9_CONTROL_ALPHAMASK__DISABLE            0U
+/* Field Value: ALPHAMASK__ENABLE, Alpha mask mode enabled  */
+#define IMXDPUV1_CLUT9_CONTROL_ALPHAMASK__ENABLE             0x1U
+#define IMXDPUV1_CLUT9_CONTROL_ALPHAINVERT_MASK              0x40U
+#define IMXDPUV1_CLUT9_CONTROL_ALPHAINVERT_SHIFT             6U
+/* Field Value: ALPHAINVERT__NORMAL, Disable computation for alpha smaller
+ * than 128  */
+#define IMXDPUV1_CLUT9_CONTROL_ALPHAINVERT__NORMAL           0U
+/* Field Value: ALPHAINVERT__INVERT, Disable computation for alpha greater
+ * than or equal to 128  */
+#define IMXDPUV1_CLUT9_CONTROL_ALPHAINVERT__INVERT           0x1U
+#define IMXDPUV1_CLUT9_CONTROL_IDX_BITS_MASK                 0xF00U
+#define IMXDPUV1_CLUT9_CONTROL_IDX_BITS_SHIFT                8U
+
+/* Register: IMXDPUV1_clut9_Status */
+#define IMXDPUV1_CLUT9_STATUS                                ((uint32_t)(0x2414))
+#define IMXDPUV1_CLUT9_STATUS_OFFSET                         ((uint32_t)(0x14))
+#define IMXDPUV1_CLUT9_STATUS_RESET_VALUE                    0U
+#define IMXDPUV1_CLUT9_STATUS_RESET_MASK                     0xFFFFFFFFU
+#define IMXDPUV1_CLUT9_STATUS_WRITE_TIMEOUT_MASK             0x1U
+#define IMXDPUV1_CLUT9_STATUS_WRITE_TIMEOUT_SHIFT            0U
+#define IMXDPUV1_CLUT9_STATUS_READ_TIMEOUT_MASK              0x10U
+#define IMXDPUV1_CLUT9_STATUS_READ_TIMEOUT_SHIFT             4U
+
+/* Register: IMXDPUV1_clut9_LastControlWord */
+#define IMXDPUV1_CLUT9_LASTCONTROLWORD                       ((uint32_t)(0x2418))
+#define IMXDPUV1_CLUT9_LASTCONTROLWORD_OFFSET                ((uint32_t)(0x18))
+#define IMXDPUV1_CLUT9_LASTCONTROLWORD_RESET_VALUE           0U
+#define IMXDPUV1_CLUT9_LASTCONTROLWORD_RESET_MASK            0U
+#define IMXDPUV1_CLUT9_LASTCONTROLWORD_L_VAL_MASK            0xFFFFFFFFU
+#define IMXDPUV1_CLUT9_LASTCONTROLWORD_L_VAL_SHIFT           0U
+
+/* Register: IMXDPUV1_clut9_LUT */
+#define IMXDPUV1_CLUT9_LUT                                   ((uint32_t)(0x2800))
+#define IMXDPUV1_CLUT9_LUT_OFFSET                            ((uint32_t)(0))
+#define IMXDPUV1_CLUT9_LUT_RESET_VALUE                       0U
+#define IMXDPUV1_CLUT9_LUT_RESET_MASK                        0xC0000000U
+#define IMXDPUV1_CLUT9_LUT_BLUE_MASK                         0x3FFU
+#define IMXDPUV1_CLUT9_LUT_BLUE_SHIFT                        0U
+#define IMXDPUV1_CLUT9_LUT_GREEN_MASK                        0xFFC00U
+#define IMXDPUV1_CLUT9_LUT_GREEN_SHIFT                       10U
+#define IMXDPUV1_CLUT9_LUT_RED_MASK                          0x3FF00000U
+#define IMXDPUV1_CLUT9_LUT_RED_SHIFT                         20U
+
+/* Register: IMXDPUV1_matrix9_LockUnlock */
+#define IMXDPUV1_MATRIX9_LOCKUNLOCK                          ((uint32_t)(0x2C00))
+#define IMXDPUV1_MATRIX9_LOCKUNLOCK_OFFSET                   ((uint32_t)(0))
+#define IMXDPUV1_MATRIX9_LOCKUNLOCK_RESET_VALUE              0U
+#define IMXDPUV1_MATRIX9_LOCKUNLOCK_RESET_MASK               0U
+#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK_MASK          0xFFFFFFFFU
+#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK_SHIFT         0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY     0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY   0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY   0xFBE8B1E6U
+
+/* Register: IMXDPUV1_matrix9_LockStatus */
+#define IMXDPUV1_MATRIX9_LOCKSTATUS                          ((uint32_t)(0x2C04))
+#define IMXDPUV1_MATRIX9_LOCKSTATUS_OFFSET                   ((uint32_t)(0x4))
+#define IMXDPUV1_MATRIX9_LOCKSTATUS_RESET_VALUE              0U
+#define IMXDPUV1_MATRIX9_LOCKSTATUS_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_MATRIX9_LOCKSTATUS_LOCKSTATUS_MASK          0x1U
+#define IMXDPUV1_MATRIX9_LOCKSTATUS_LOCKSTATUS_SHIFT         0U
+#define IMXDPUV1_MATRIX9_LOCKSTATUS_PRIVILEGESTATUS_MASK     0x10U
+#define IMXDPUV1_MATRIX9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT    4U
+#define IMXDPUV1_MATRIX9_LOCKSTATUS_FREEZESTATUS_MASK        0x100U
+#define IMXDPUV1_MATRIX9_LOCKSTATUS_FREEZESTATUS_SHIFT       8U
+
+/* Register: IMXDPUV1_matrix9_StaticControl */
+#define IMXDPUV1_MATRIX9_STATICCONTROL                       ((uint32_t)(0x2C08))
+#define IMXDPUV1_MATRIX9_STATICCONTROL_OFFSET                ((uint32_t)(0x8))
+#define IMXDPUV1_MATRIX9_STATICCONTROL_RESET_VALUE           0U
+#define IMXDPUV1_MATRIX9_STATICCONTROL_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_MATRIX9_STATICCONTROL_SHDEN_MASK            0x1U
+#define IMXDPUV1_MATRIX9_STATICCONTROL_SHDEN_SHIFT           0U
+
+/* Register: IMXDPUV1_matrix9_Control */
+#define IMXDPUV1_MATRIX9_CONTROL                             ((uint32_t)(0x2C0C))
+#define IMXDPUV1_MATRIX9_CONTROL_OFFSET                      ((uint32_t)(0xC))
+#define IMXDPUV1_MATRIX9_CONTROL_RESET_VALUE                 0U
+#define IMXDPUV1_MATRIX9_CONTROL_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_MATRIX9_CONTROL_MODE_MASK                   0x3U
+#define IMXDPUV1_MATRIX9_CONTROL_MODE_SHIFT                  0U
+/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed  */
+#define IMXDPUV1_MATRIX9_CONTROL_MODE__NEUTRAL               0U
+/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied
+ * with matrix values  */
+#define IMXDPUV1_MATRIX9_CONTROL_MODE__MATRIX                0x1U
+/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input
+ * color is multiplied with input alpha  */
+#define IMXDPUV1_MATRIX9_CONTROL_MODE__PREMUL                0x2U
+/* Field Value: MODE__RSVD, Reserved, do not use  */
+#define IMXDPUV1_MATRIX9_CONTROL_MODE__RSVD                  0x3U
+#define IMXDPUV1_MATRIX9_CONTROL_ALPHAMASK_MASK              0x10U
+#define IMXDPUV1_MATRIX9_CONTROL_ALPHAMASK_SHIFT             4U
+#define IMXDPUV1_MATRIX9_CONTROL_ALPHAINVERT_MASK            0x20U
+#define IMXDPUV1_MATRIX9_CONTROL_ALPHAINVERT_SHIFT           5U
+
+/* Register: IMXDPUV1_matrix9_Red0 */
+#define IMXDPUV1_MATRIX9_RED0                                ((uint32_t)(0x2C10))
+#define IMXDPUV1_MATRIX9_RED0_OFFSET                         ((uint32_t)(0x10))
+#define IMXDPUV1_MATRIX9_RED0_RESET_VALUE                    0x400U
+#define IMXDPUV1_MATRIX9_RED0_RESET_MASK                     0xFFFFFFFFU
+#define IMXDPUV1_MATRIX9_RED0_A11_MASK                       0x1FFFU
+#define IMXDPUV1_MATRIX9_RED0_A11_SHIFT                      0U
+#define IMXDPUV1_MATRIX9_RED0_A12_MASK                       0x1FFF0000U
+#define IMXDPUV1_MATRIX9_RED0_A12_SHIFT                      16U
+
+/* Register: IMXDPUV1_matrix9_Red1 */
+#define IMXDPUV1_MATRIX9_RED1                                ((uint32_t)(0x2C14))
+#define IMXDPUV1_MATRIX9_RED1_OFFSET                         ((uint32_t)(0x14))
+#define IMXDPUV1_MATRIX9_RED1_RESET_VALUE                    0U
+#define IMXDPUV1_MATRIX9_RED1_RESET_MASK                     0xFFFFFFFFU
+#define IMXDPUV1_MATRIX9_RED1_A13_MASK                       0x1FFFU
+#define IMXDPUV1_MATRIX9_RED1_A13_SHIFT                      0U
+#define IMXDPUV1_MATRIX9_RED1_A14_MASK                       0x1FFF0000U
+#define IMXDPUV1_MATRIX9_RED1_A14_SHIFT                      16U
+
+/* Register: IMXDPUV1_matrix9_Green0 */
+#define IMXDPUV1_MATRIX9_GREEN0                              ((uint32_t)(0x2C18))
+#define IMXDPUV1_MATRIX9_GREEN0_OFFSET                       ((uint32_t)(0x18))
+#define IMXDPUV1_MATRIX9_GREEN0_RESET_VALUE                  0x4000000U
+#define IMXDPUV1_MATRIX9_GREEN0_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX9_GREEN0_A21_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX9_GREEN0_A21_SHIFT                    0U
+#define IMXDPUV1_MATRIX9_GREEN0_A22_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX9_GREEN0_A22_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix9_Green1 */
+#define IMXDPUV1_MATRIX9_GREEN1                              ((uint32_t)(0x2C1C))
+#define IMXDPUV1_MATRIX9_GREEN1_OFFSET                       ((uint32_t)(0x1C))
+#define IMXDPUV1_MATRIX9_GREEN1_RESET_VALUE                  0U
+#define IMXDPUV1_MATRIX9_GREEN1_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX9_GREEN1_A23_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX9_GREEN1_A23_SHIFT                    0U
+#define IMXDPUV1_MATRIX9_GREEN1_A24_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX9_GREEN1_A24_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix9_Blue0 */
+#define IMXDPUV1_MATRIX9_BLUE0                               ((uint32_t)(0x2C20))
+#define IMXDPUV1_MATRIX9_BLUE0_OFFSET                        ((uint32_t)(0x20))
+#define IMXDPUV1_MATRIX9_BLUE0_RESET_VALUE                   0U
+#define IMXDPUV1_MATRIX9_BLUE0_RESET_MASK                    0xFFFFFFFFU
+#define IMXDPUV1_MATRIX9_BLUE0_A31_MASK                      0x1FFFU
+#define IMXDPUV1_MATRIX9_BLUE0_A31_SHIFT                     0U
+#define IMXDPUV1_MATRIX9_BLUE0_A32_MASK                      0x1FFF0000U
+#define IMXDPUV1_MATRIX9_BLUE0_A32_SHIFT                     16U
+
+/* Register: IMXDPUV1_matrix9_Blue1 */
+#define IMXDPUV1_MATRIX9_BLUE1                               ((uint32_t)(0x2C24))
+#define IMXDPUV1_MATRIX9_BLUE1_OFFSET                        ((uint32_t)(0x24))
+#define IMXDPUV1_MATRIX9_BLUE1_RESET_VALUE                   0x400U
+#define IMXDPUV1_MATRIX9_BLUE1_RESET_MASK                    0xFFFFFFFFU
+#define IMXDPUV1_MATRIX9_BLUE1_A33_MASK                      0x1FFFU
+#define IMXDPUV1_MATRIX9_BLUE1_A33_SHIFT                     0U
+#define IMXDPUV1_MATRIX9_BLUE1_A34_MASK                      0x1FFF0000U
+#define IMXDPUV1_MATRIX9_BLUE1_A34_SHIFT                     16U
+
+/* Register: IMXDPUV1_matrix9_Alpha0 */
+#define IMXDPUV1_MATRIX9_ALPHA0                              ((uint32_t)(0x2C28))
+#define IMXDPUV1_MATRIX9_ALPHA0_OFFSET                       ((uint32_t)(0x28))
+#define IMXDPUV1_MATRIX9_ALPHA0_RESET_VALUE                  0U
+#define IMXDPUV1_MATRIX9_ALPHA0_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX9_ALPHA0_A41_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX9_ALPHA0_A41_SHIFT                    0U
+#define IMXDPUV1_MATRIX9_ALPHA0_A42_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX9_ALPHA0_A42_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix9_Alpha1 */
+#define IMXDPUV1_MATRIX9_ALPHA1                              ((uint32_t)(0x2C2C))
+#define IMXDPUV1_MATRIX9_ALPHA1_OFFSET                       ((uint32_t)(0x2C))
+#define IMXDPUV1_MATRIX9_ALPHA1_RESET_VALUE                  0x4000000U
+#define IMXDPUV1_MATRIX9_ALPHA1_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX9_ALPHA1_A43_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX9_ALPHA1_A43_SHIFT                    0U
+#define IMXDPUV1_MATRIX9_ALPHA1_A44_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX9_ALPHA1_A44_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix9_OffsetVector0 */
+#define IMXDPUV1_MATRIX9_OFFSETVECTOR0                       ((uint32_t)(0x2C30))
+#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_OFFSET                ((uint32_t)(0x30))
+#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_RESET_VALUE           0U
+#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_C1_MASK               0x1FFFU
+#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_C1_SHIFT              0U
+#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_C2_MASK               0x1FFF0000U
+#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_C2_SHIFT              16U
+
+/* Register: IMXDPUV1_matrix9_OffsetVector1 */
+#define IMXDPUV1_MATRIX9_OFFSETVECTOR1                       ((uint32_t)(0x2C34))
+#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_OFFSET                ((uint32_t)(0x34))
+#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_RESET_VALUE           0U
+#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_C3_MASK               0x1FFFU
+#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_C3_SHIFT              0U
+#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_C4_MASK               0x1FFF0000U
+#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_C4_SHIFT              16U
+
+/* Register: IMXDPUV1_matrix9_LastControlWord */
+#define IMXDPUV1_MATRIX9_LASTCONTROLWORD                     ((uint32_t)(0x2C38))
+#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_OFFSET              ((uint32_t)(0x38))
+#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_RESET_VALUE         0U
+#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_RESET_MASK          0U
+#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_L_VAL_MASK          0xFFFFFFFFU
+#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_L_VAL_SHIFT         0U
+
+/* Register: IMXDPUV1_hscaler9_LockUnlock */
+#define IMXDPUV1_HSCALER9_LOCKUNLOCK                         ((uint32_t)(0x3000))
+#define IMXDPUV1_HSCALER9_LOCKUNLOCK_OFFSET                  ((uint32_t)(0))
+#define IMXDPUV1_HSCALER9_LOCKUNLOCK_RESET_VALUE             0U
+#define IMXDPUV1_HSCALER9_LOCKUNLOCK_RESET_MASK              0U
+#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK_MASK         0xFFFFFFFFU
+#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK_SHIFT        0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY    0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY  0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY  0xFBE8B1E6U
+
+/* Register: IMXDPUV1_hscaler9_LockStatus */
+#define IMXDPUV1_HSCALER9_LOCKSTATUS                         ((uint32_t)(0x3004))
+#define IMXDPUV1_HSCALER9_LOCKSTATUS_OFFSET                  ((uint32_t)(0x4))
+#define IMXDPUV1_HSCALER9_LOCKSTATUS_RESET_VALUE             0U
+#define IMXDPUV1_HSCALER9_LOCKSTATUS_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_HSCALER9_LOCKSTATUS_LOCKSTATUS_MASK         0x1U
+#define IMXDPUV1_HSCALER9_LOCKSTATUS_LOCKSTATUS_SHIFT        0U
+#define IMXDPUV1_HSCALER9_LOCKSTATUS_PRIVILEGESTATUS_MASK    0x10U
+#define IMXDPUV1_HSCALER9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT   4U
+#define IMXDPUV1_HSCALER9_LOCKSTATUS_FREEZESTATUS_MASK       0x100U
+#define IMXDPUV1_HSCALER9_LOCKSTATUS_FREEZESTATUS_SHIFT      8U
+
+/* Register: IMXDPUV1_hscaler9_StaticControl */
+#define IMXDPUV1_HSCALER9_STATICCONTROL                      ((uint32_t)(0x3008))
+#define IMXDPUV1_HSCALER9_STATICCONTROL_OFFSET               ((uint32_t)(0x8))
+#define IMXDPUV1_HSCALER9_STATICCONTROL_RESET_VALUE          0U
+#define IMXDPUV1_HSCALER9_STATICCONTROL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_HSCALER9_STATICCONTROL_SHDEN_MASK           0x1U
+#define IMXDPUV1_HSCALER9_STATICCONTROL_SHDEN_SHIFT          0U
+
+/* Register: IMXDPUV1_hscaler9_Setup1 */
+#define IMXDPUV1_HSCALER9_SETUP1                             ((uint32_t)(0x300C))
+#define IMXDPUV1_HSCALER9_SETUP1_OFFSET                      ((uint32_t)(0xC))
+#define IMXDPUV1_HSCALER9_SETUP1_RESET_VALUE                 0x80000U
+#define IMXDPUV1_HSCALER9_SETUP1_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_HSCALER9_SETUP1_SCALE_FACTOR_MASK           0xFFFFFU
+#define IMXDPUV1_HSCALER9_SETUP1_SCALE_FACTOR_SHIFT          0U
+
+/* Register: IMXDPUV1_hscaler9_Setup2 */
+#define IMXDPUV1_HSCALER9_SETUP2                             ((uint32_t)(0x3010))
+#define IMXDPUV1_HSCALER9_SETUP2_OFFSET                      ((uint32_t)(0x10))
+#define IMXDPUV1_HSCALER9_SETUP2_RESET_VALUE                 0U
+#define IMXDPUV1_HSCALER9_SETUP2_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_HSCALER9_SETUP2_PHASE_OFFSET_MASK           0x1FFFFFU
+#define IMXDPUV1_HSCALER9_SETUP2_PHASE_OFFSET_SHIFT          0U
+
+/* Register: IMXDPUV1_hscaler9_Control */
+#define IMXDPUV1_HSCALER9_CONTROL                            ((uint32_t)(0x3014))
+#define IMXDPUV1_HSCALER9_CONTROL_OFFSET                     ((uint32_t)(0x14))
+#define IMXDPUV1_HSCALER9_CONTROL_RESET_VALUE                0U
+#define IMXDPUV1_HSCALER9_CONTROL_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_HSCALER9_CONTROL_MODE_MASK                  0x1U
+#define IMXDPUV1_HSCALER9_CONTROL_MODE_SHIFT                 0U
+/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all
+ * other settings are ignored.  */
+#define IMXDPUV1_HSCALER9_CONTROL_MODE__NEUTRAL              0U
+/* Field Value: MODE__ACTIVE, Scaler is active.  */
+#define IMXDPUV1_HSCALER9_CONTROL_MODE__ACTIVE               0x1U
+#define IMXDPUV1_HSCALER9_CONTROL_SCALE_MODE_MASK            0x10U
+#define IMXDPUV1_HSCALER9_CONTROL_SCALE_MODE_SHIFT           4U
+/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal
+ * input size).  */
+#define IMXDPUV1_HSCALER9_CONTROL_SCALE_MODE__DOWNSCALE      0U
+/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal
+ * input size)  */
+#define IMXDPUV1_HSCALER9_CONTROL_SCALE_MODE__UPSCALE        0x1U
+#define IMXDPUV1_HSCALER9_CONTROL_FILTER_MODE_MASK           0x100U
+#define IMXDPUV1_HSCALER9_CONTROL_FILTER_MODE_SHIFT          8U
+/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling)  */
+#define IMXDPUV1_HSCALER9_CONTROL_FILTER_MODE__NEAREST       0U
+/* Field Value: FILTER_MODE__LINEAR, Box filter (linear)  */
+#define IMXDPUV1_HSCALER9_CONTROL_FILTER_MODE__LINEAR        0x1U
+#define IMXDPUV1_HSCALER9_CONTROL_OUTPUT_SIZE_MASK           0x3FFF0000U
+#define IMXDPUV1_HSCALER9_CONTROL_OUTPUT_SIZE_SHIFT          16U
+
+/* Register: IMXDPUV1_vscaler9_LockUnlock */
+#define IMXDPUV1_VSCALER9_LOCKUNLOCK                         ((uint32_t)(0x3400))
+#define IMXDPUV1_VSCALER9_LOCKUNLOCK_OFFSET                  ((uint32_t)(0))
+#define IMXDPUV1_VSCALER9_LOCKUNLOCK_RESET_VALUE             0U
+#define IMXDPUV1_VSCALER9_LOCKUNLOCK_RESET_MASK              0U
+#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK_MASK         0xFFFFFFFFU
+#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK_SHIFT        0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY    0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY  0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY  0xFBE8B1E6U
+
+/* Register: IMXDPUV1_vscaler9_LockStatus */
+#define IMXDPUV1_VSCALER9_LOCKSTATUS                         ((uint32_t)(0x3404))
+#define IMXDPUV1_VSCALER9_LOCKSTATUS_OFFSET                  ((uint32_t)(0x4))
+#define IMXDPUV1_VSCALER9_LOCKSTATUS_RESET_VALUE             0U
+#define IMXDPUV1_VSCALER9_LOCKSTATUS_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_VSCALER9_LOCKSTATUS_LOCKSTATUS_MASK         0x1U
+#define IMXDPUV1_VSCALER9_LOCKSTATUS_LOCKSTATUS_SHIFT        0U
+#define IMXDPUV1_VSCALER9_LOCKSTATUS_PRIVILEGESTATUS_MASK    0x10U
+#define IMXDPUV1_VSCALER9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT   4U
+#define IMXDPUV1_VSCALER9_LOCKSTATUS_FREEZESTATUS_MASK       0x100U
+#define IMXDPUV1_VSCALER9_LOCKSTATUS_FREEZESTATUS_SHIFT      8U
+
+/* Register: IMXDPUV1_vscaler9_StaticControl */
+#define IMXDPUV1_VSCALER9_STATICCONTROL                      ((uint32_t)(0x3408))
+#define IMXDPUV1_VSCALER9_STATICCONTROL_OFFSET               ((uint32_t)(0x8))
+#define IMXDPUV1_VSCALER9_STATICCONTROL_RESET_VALUE          0U
+#define IMXDPUV1_VSCALER9_STATICCONTROL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_VSCALER9_STATICCONTROL_SHDEN_MASK           0x1U
+#define IMXDPUV1_VSCALER9_STATICCONTROL_SHDEN_SHIFT          0U
+
+/* Register: IMXDPUV1_vscaler9_Setup1 */
+#define IMXDPUV1_VSCALER9_SETUP1                             ((uint32_t)(0x340C))
+#define IMXDPUV1_VSCALER9_SETUP1_OFFSET                      ((uint32_t)(0xC))
+#define IMXDPUV1_VSCALER9_SETUP1_RESET_VALUE                 0x80000U
+#define IMXDPUV1_VSCALER9_SETUP1_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_VSCALER9_SETUP1_SCALE_FACTOR_MASK           0xFFFFFU
+#define IMXDPUV1_VSCALER9_SETUP1_SCALE_FACTOR_SHIFT          0U
+
+/* Register: IMXDPUV1_vscaler9_Setup2 */
+#define IMXDPUV1_VSCALER9_SETUP2                             ((uint32_t)(0x3410))
+#define IMXDPUV1_VSCALER9_SETUP2_OFFSET                      ((uint32_t)(0x10))
+#define IMXDPUV1_VSCALER9_SETUP2_RESET_VALUE                 0U
+#define IMXDPUV1_VSCALER9_SETUP2_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_VSCALER9_SETUP2_PHASE_OFFSET_MASK           0x1FFFFFU
+#define IMXDPUV1_VSCALER9_SETUP2_PHASE_OFFSET_SHIFT          0U
+
+/* Register: IMXDPUV1_vscaler9_Setup3 */
+#define IMXDPUV1_VSCALER9_SETUP3                             ((uint32_t)(0x3414))
+#define IMXDPUV1_VSCALER9_SETUP3_OFFSET                      ((uint32_t)(0x14))
+#define IMXDPUV1_VSCALER9_SETUP3_RESET_VALUE                 0U
+#define IMXDPUV1_VSCALER9_SETUP3_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_VSCALER9_SETUP3_PHASE_OFFSET1_MASK          0x1FFFFFU
+#define IMXDPUV1_VSCALER9_SETUP3_PHASE_OFFSET1_SHIFT         0U
+
+/* Register: IMXDPUV1_vscaler9_Setup4 */
+#define IMXDPUV1_VSCALER9_SETUP4                             ((uint32_t)(0x3418))
+#define IMXDPUV1_VSCALER9_SETUP4_OFFSET                      ((uint32_t)(0x18))
+#define IMXDPUV1_VSCALER9_SETUP4_RESET_VALUE                 0U
+#define IMXDPUV1_VSCALER9_SETUP4_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_VSCALER9_SETUP4_PHASE_OFFSET2_MASK          0x1FFFFFU
+#define IMXDPUV1_VSCALER9_SETUP4_PHASE_OFFSET2_SHIFT         0U
+
+/* Register: IMXDPUV1_vscaler9_Setup5 */
+#define IMXDPUV1_VSCALER9_SETUP5                             ((uint32_t)(0x341C))
+#define IMXDPUV1_VSCALER9_SETUP5_OFFSET                      ((uint32_t)(0x1C))
+#define IMXDPUV1_VSCALER9_SETUP5_RESET_VALUE                 0U
+#define IMXDPUV1_VSCALER9_SETUP5_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_VSCALER9_SETUP5_PHASE_OFFSET3_MASK          0x1FFFFFU
+#define IMXDPUV1_VSCALER9_SETUP5_PHASE_OFFSET3_SHIFT         0U
+
+/* Register: IMXDPUV1_vscaler9_Control */
+#define IMXDPUV1_VSCALER9_CONTROL                            ((uint32_t)(0x3420))
+#define IMXDPUV1_VSCALER9_CONTROL_OFFSET                     ((uint32_t)(0x20))
+#define IMXDPUV1_VSCALER9_CONTROL_RESET_VALUE                0x2000U
+#define IMXDPUV1_VSCALER9_CONTROL_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_VSCALER9_CONTROL_MODE_MASK                  0x1U
+#define IMXDPUV1_VSCALER9_CONTROL_MODE_SHIFT                 0U
+/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all
+ * other settings are ignored.  */
+#define IMXDPUV1_VSCALER9_CONTROL_MODE__NEUTRAL              0U
+/* Field Value: MODE__ACTIVE, Scaler is active.  */
+#define IMXDPUV1_VSCALER9_CONTROL_MODE__ACTIVE               0x1U
+#define IMXDPUV1_VSCALER9_CONTROL_SCALE_MODE_MASK            0x10U
+#define IMXDPUV1_VSCALER9_CONTROL_SCALE_MODE_SHIFT           4U
+/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal
+ * input size).  */
+#define IMXDPUV1_VSCALER9_CONTROL_SCALE_MODE__DOWNSCALE      0U
+/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal
+ * input size).  */
+#define IMXDPUV1_VSCALER9_CONTROL_SCALE_MODE__UPSCALE        0x1U
+#define IMXDPUV1_VSCALER9_CONTROL_FILTER_MODE_MASK           0x100U
+#define IMXDPUV1_VSCALER9_CONTROL_FILTER_MODE_SHIFT          8U
+/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling)  */
+#define IMXDPUV1_VSCALER9_CONTROL_FILTER_MODE__NEAREST       0U
+/* Field Value: FILTER_MODE__LINEAR, Box filter (linear)  */
+#define IMXDPUV1_VSCALER9_CONTROL_FILTER_MODE__LINEAR        0x1U
+#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE_MASK            0x3000U
+#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE_SHIFT           12U
+/* Field Value: FIELD_MODE__ALWAYS0, Constant 0 indicates frame or top field.  */
+#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE__ALWAYS0        0U
+/* Field Value: FIELD_MODE__ALWAYS1, Constant 1 indicates bottom field.  */
+#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE__ALWAYS1        0x1U
+/* Field Value: FIELD_MODE__INPUT, Output field polarity is taken from input
+ * field polarity.  */
+#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE__INPUT          0x2U
+/* Field Value: FIELD_MODE__TOGGLE, Output field polarity toggles, starting
+ * with 0 after reset.  */
+#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE__TOGGLE         0x3U
+#define IMXDPUV1_VSCALER9_CONTROL_OUTPUT_SIZE_MASK           0x3FFF0000U
+#define IMXDPUV1_VSCALER9_CONTROL_OUTPUT_SIZE_SHIFT          16U
+
+/* Register: IMXDPUV1_filter9_LockUnlock */
+#define IMXDPUV1_FILTER9_LOCKUNLOCK                          ((uint32_t)(0x3800))
+#define IMXDPUV1_FILTER9_LOCKUNLOCK_OFFSET                   ((uint32_t)(0))
+#define IMXDPUV1_FILTER9_LOCKUNLOCK_RESET_VALUE              0U
+#define IMXDPUV1_FILTER9_LOCKUNLOCK_RESET_MASK               0U
+#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK_SHIFT         0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY     0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY   0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY   0xFBE8B1E6U
+
+/* Register: IMXDPUV1_filter9_LockStatus */
+#define IMXDPUV1_FILTER9_LOCKSTATUS                          ((uint32_t)(0x3804))
+#define IMXDPUV1_FILTER9_LOCKSTATUS_OFFSET                   ((uint32_t)(0x4))
+#define IMXDPUV1_FILTER9_LOCKSTATUS_RESET_VALUE              0U
+#define IMXDPUV1_FILTER9_LOCKSTATUS_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_FILTER9_LOCKSTATUS_LOCKSTATUS_MASK          0x1U
+#define IMXDPUV1_FILTER9_LOCKSTATUS_LOCKSTATUS_SHIFT         0U
+#define IMXDPUV1_FILTER9_LOCKSTATUS_PRIVILEGESTATUS_MASK     0x10U
+#define IMXDPUV1_FILTER9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT    4U
+#define IMXDPUV1_FILTER9_LOCKSTATUS_FREEZESTATUS_MASK        0x100U
+#define IMXDPUV1_FILTER9_LOCKSTATUS_FREEZESTATUS_SHIFT       8U
+
+/* Register: IMXDPUV1_filter9_StaticControl */
+#define IMXDPUV1_FILTER9_STATICCONTROL                       ((uint32_t)(0x3808))
+#define IMXDPUV1_FILTER9_STATICCONTROL_OFFSET                ((uint32_t)(0x8))
+#define IMXDPUV1_FILTER9_STATICCONTROL_RESET_VALUE           0U
+#define IMXDPUV1_FILTER9_STATICCONTROL_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_FILTER9_STATICCONTROL_SHDEN_MASK            0x1U
+#define IMXDPUV1_FILTER9_STATICCONTROL_SHDEN_SHIFT           0U
+
+/* Register: IMXDPUV1_filter9_Control */
+#define IMXDPUV1_FILTER9_CONTROL                             ((uint32_t)(0x380C))
+#define IMXDPUV1_FILTER9_CONTROL_OFFSET                      ((uint32_t)(0xC))
+#define IMXDPUV1_FILTER9_CONTROL_RESET_VALUE                 0x5500U
+#define IMXDPUV1_FILTER9_CONTROL_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_FILTER9_CONTROL_MODE_MASK                   0x1U
+#define IMXDPUV1_FILTER9_CONTROL_MODE_SHIFT                  0U
+/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the filter, all
+ * other settings are ignored.  */
+#define IMXDPUV1_FILTER9_CONTROL_MODE__NEUTRAL               0U
+/* Field Value: MODE__ACTIVE, Filter is active.  */
+#define IMXDPUV1_FILTER9_CONTROL_MODE__ACTIVE                0x1U
+#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE_MASK              0x30U
+#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE_SHIFT             4U
+/* Field Value: TILE_MODE__PAD, Samples outside the frame are padded with
+ * the last valid border pixels.  */
+#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE__PAD              0U
+/* Field Value: TILE_MODE__ZERO, Samples outside the frame are treated as
+ * zero pixel value.  */
+#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE__ZERO             0x1U
+/* Field Value: TILE_MODE__PAD_ZERO, Applies tile mode PAD to RGB channels
+ * and tile mode ZERO to alpha channel.  */
+#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE__PAD_ZERO         0x2U
+#define IMXDPUV1_FILTER9_CONTROL_FILTER_MODE_MASK            0xFFFF00U
+#define IMXDPUV1_FILTER9_CONTROL_FILTER_MODE_SHIFT           8U
+/* Field Value: FILTER_MODE__FIR_5X5, FIR filter 5x5 window.  */
+#define IMXDPUV1_FILTER9_CONTROL_FILTER_MODE__FIR_5X5        0x55U
+#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT_MASK          0x30000000U
+#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT_SHIFT         28U
+/* Field Value: BUFFER_FORMAT__RGB888, RGB888 format. Alpha is not filtered
+ * but set to constant value 255.  */
+#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT__RGB888       0U
+/* Field Value: BUFFER_FORMAT__RGBA5658, RGBA5658 format. Alpha is filtered.  */
+#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT__RGBA5658     0x1U
+/* Field Value: BUFFER_FORMAT__RGBA8888, RGBA8888 format. Alpha is filtered.
+ * The filter window is limited to 5x4.  */
+#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT__RGBA8888     0x2U
+/* Field Value: BUFFER_FORMAT__RGBA1010108, RGBA10.10.10.8 format. Alpha is
+ * filtered. The filter window is limited to 5x3.  */
+#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT__RGBA1010108  0x3U
+
+/* Register: IMXDPUV1_filter9_FIR_control */
+#define IMXDPUV1_FILTER9_FIR_CONTROL                         ((uint32_t)(0x3810))
+#define IMXDPUV1_FILTER9_FIR_CONTROL_OFFSET                  ((uint32_t)(0x10))
+#define IMXDPUV1_FILTER9_FIR_CONTROL_RESET_VALUE             0xEU
+#define IMXDPUV1_FILTER9_FIR_CONTROL_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_FILTER9_FIR_CONTROL_FIR_COMPONENT_SELECT_MASK 0xFU
+#define IMXDPUV1_FILTER9_FIR_CONTROL_FIR_COMPONENT_SELECT_SHIFT 0U
+#define IMXDPUV1_FILTER9_FIR_CONTROL_FIR_EXPONENT_MASK       0xF00U
+#define IMXDPUV1_FILTER9_FIR_CONTROL_FIR_EXPONENT_SHIFT      8U
+
+/* Register: IMXDPUV1_filter9_Coefficients0 */
+#define IMXDPUV1_FILTER9_COEFFICIENTS0                       ((uint32_t)(0x3814))
+#define IMXDPUV1_FILTER9_COEFFICIENTS0_OFFSET                ((uint32_t)(0x14))
+#define IMXDPUV1_FILTER9_COEFFICIENTS0_RESET_VALUE           0U
+#define IMXDPUV1_FILTER9_COEFFICIENTS0_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF0_0_MASK         0xFFU
+#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF0_0_SHIFT        0U
+#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF1_0_MASK         0xFF00U
+#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF1_0_SHIFT        8U
+#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF2_0_MASK         0xFF0000U
+#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF2_0_SHIFT        16U
+#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF3_0_MASK         0xFF000000U
+#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF3_0_SHIFT        24U
+
+/* Register: IMXDPUV1_filter9_Coefficients1 */
+#define IMXDPUV1_FILTER9_COEFFICIENTS1                       ((uint32_t)(0x3818))
+#define IMXDPUV1_FILTER9_COEFFICIENTS1_OFFSET                ((uint32_t)(0x18))
+#define IMXDPUV1_FILTER9_COEFFICIENTS1_RESET_VALUE           0U
+#define IMXDPUV1_FILTER9_COEFFICIENTS1_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF4_0_MASK         0xFFU
+#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF4_0_SHIFT        0U
+#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF0_1_MASK         0xFF00U
+#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF0_1_SHIFT        8U
+#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF1_1_MASK         0xFF0000U
+#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF1_1_SHIFT        16U
+#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF2_1_MASK         0xFF000000U
+#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF2_1_SHIFT        24U
+
+/* Register: IMXDPUV1_filter9_Coefficients2 */
+#define IMXDPUV1_FILTER9_COEFFICIENTS2                       ((uint32_t)(0x381C))
+#define IMXDPUV1_FILTER9_COEFFICIENTS2_OFFSET                ((uint32_t)(0x1C))
+#define IMXDPUV1_FILTER9_COEFFICIENTS2_RESET_VALUE           0U
+#define IMXDPUV1_FILTER9_COEFFICIENTS2_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF3_1_MASK         0xFFU
+#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF3_1_SHIFT        0U
+#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF4_1_MASK         0xFF00U
+#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF4_1_SHIFT        8U
+#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF0_2_MASK         0xFF0000U
+#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF0_2_SHIFT        16U
+#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF1_2_MASK         0xFF000000U
+#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF1_2_SHIFT        24U
+
+/* Register: IMXDPUV1_filter9_Coefficients3 */
+#define IMXDPUV1_FILTER9_COEFFICIENTS3                       ((uint32_t)(0x3820))
+#define IMXDPUV1_FILTER9_COEFFICIENTS3_OFFSET                ((uint32_t)(0x20))
+#define IMXDPUV1_FILTER9_COEFFICIENTS3_RESET_VALUE           0x1U
+#define IMXDPUV1_FILTER9_COEFFICIENTS3_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF2_2_MASK         0xFFU
+#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF2_2_SHIFT        0U
+#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF3_2_MASK         0xFF00U
+#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF3_2_SHIFT        8U
+#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF4_2_MASK         0xFF0000U
+#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF4_2_SHIFT        16U
+#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF0_3_MASK         0xFF000000U
+#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF0_3_SHIFT        24U
+
+/* Register: IMXDPUV1_filter9_Coefficients4 */
+#define IMXDPUV1_FILTER9_COEFFICIENTS4                       ((uint32_t)(0x3824))
+#define IMXDPUV1_FILTER9_COEFFICIENTS4_OFFSET                ((uint32_t)(0x24))
+#define IMXDPUV1_FILTER9_COEFFICIENTS4_RESET_VALUE           0U
+#define IMXDPUV1_FILTER9_COEFFICIENTS4_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF1_3_MASK         0xFFU
+#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF1_3_SHIFT        0U
+#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF2_3_MASK         0xFF00U
+#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF2_3_SHIFT        8U
+#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF3_3_MASK         0xFF0000U
+#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF3_3_SHIFT        16U
+#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF4_3_MASK         0xFF000000U
+#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF4_3_SHIFT        24U
+
+/* Register: IMXDPUV1_filter9_Coefficients5 */
+#define IMXDPUV1_FILTER9_COEFFICIENTS5                       ((uint32_t)(0x3828))
+#define IMXDPUV1_FILTER9_COEFFICIENTS5_OFFSET                ((uint32_t)(0x28))
+#define IMXDPUV1_FILTER9_COEFFICIENTS5_RESET_VALUE           0U
+#define IMXDPUV1_FILTER9_COEFFICIENTS5_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF0_4_MASK         0xFFU
+#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF0_4_SHIFT        0U
+#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF1_4_MASK         0xFF00U
+#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF1_4_SHIFT        8U
+#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF2_4_MASK         0xFF0000U
+#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF2_4_SHIFT        16U
+#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF3_4_MASK         0xFF000000U
+#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF3_4_SHIFT        24U
+
+/* Register: IMXDPUV1_filter9_Coefficients6 */
+#define IMXDPUV1_FILTER9_COEFFICIENTS6                       ((uint32_t)(0x382C))
+#define IMXDPUV1_FILTER9_COEFFICIENTS6_OFFSET                ((uint32_t)(0x2C))
+#define IMXDPUV1_FILTER9_COEFFICIENTS6_RESET_VALUE           0U
+#define IMXDPUV1_FILTER9_COEFFICIENTS6_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_FILTER9_COEFFICIENTS6_COEFF4_4_MASK         0xFFU
+#define IMXDPUV1_FILTER9_COEFFICIENTS6_COEFF4_4_SHIFT        0U
+
+/* Register: IMXDPUV1_blitblend9_LockUnlock */
+#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK                       ((uint32_t)(0x3C00))
+#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_OFFSET                ((uint32_t)(0))
+#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_RESET_VALUE           0U
+#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_RESET_MASK            0U
+#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK_MASK       0xFFFFFFFFU
+#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK_SHIFT      0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY  0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_blitblend9_LockStatus */
+#define IMXDPUV1_BLITBLEND9_LOCKSTATUS                       ((uint32_t)(0x3C04))
+#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_OFFSET                ((uint32_t)(0x4))
+#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_RESET_VALUE           0U
+#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_LOCKSTATUS_MASK       0x1U
+#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_LOCKSTATUS_SHIFT      0U
+#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_PRIVILEGESTATUS_MASK  0x10U
+#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_FREEZESTATUS_MASK     0x100U
+#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_FREEZESTATUS_SHIFT    8U
+
+/* Register: IMXDPUV1_blitblend9_StaticControl */
+#define IMXDPUV1_BLITBLEND9_STATICCONTROL                    ((uint32_t)(0x3C08))
+#define IMXDPUV1_BLITBLEND9_STATICCONTROL_OFFSET             ((uint32_t)(0x8))
+#define IMXDPUV1_BLITBLEND9_STATICCONTROL_RESET_VALUE        0U
+#define IMXDPUV1_BLITBLEND9_STATICCONTROL_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_BLITBLEND9_STATICCONTROL_SHDEN_MASK         0x1U
+#define IMXDPUV1_BLITBLEND9_STATICCONTROL_SHDEN_SHIFT        0U
+
+/* Register: IMXDPUV1_blitblend9_Control */
+#define IMXDPUV1_BLITBLEND9_CONTROL                          ((uint32_t)(0x3C0C))
+#define IMXDPUV1_BLITBLEND9_CONTROL_OFFSET                   ((uint32_t)(0xC))
+#define IMXDPUV1_BLITBLEND9_CONTROL_RESET_VALUE              0U
+#define IMXDPUV1_BLITBLEND9_CONTROL_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_BLITBLEND9_CONTROL_MODE_MASK                0x1U
+#define IMXDPUV1_BLITBLEND9_CONTROL_MODE_SHIFT               0U
+/* Field Value: MODE__NEUTRAL, Neutral mode, only route pixels and commands
+ * from primary input to output  */
+#define IMXDPUV1_BLITBLEND9_CONTROL_MODE__NEUTRAL            0U
+/* Field Value: MODE__OPERATION, Normal Operation  */
+#define IMXDPUV1_BLITBLEND9_CONTROL_MODE__OPERATION          0x1U
+
+/* Register: IMXDPUV1_blitblend9_NeutralBorder */
+#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER                    ((uint32_t)(0x3C10))
+#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_OFFSET             ((uint32_t)(0x10))
+#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_RESET_VALUE        0U
+#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERMODE_MASK 0x1U
+#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERMODE_SHIFT 0U
+/* Field Value: NEUTRALBORDERMODE__PRIMARY, Bypasses primary pixel  */
+#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERMODE__PRIMARY 0U
+/* Field Value: NEUTRALBORDERMODE__SECONDARY, Bypasses secondary pixel  */
+#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERMODE__SECONDARY 0x1U
+#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERLEFT_MASK 0x700U
+#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERLEFT_SHIFT 8U
+#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERRIGHT_MASK 0x7000U
+#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERRIGHT_SHIFT 12U
+
+/* Register: IMXDPUV1_blitblend9_ConstantColor */
+#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR                    ((uint32_t)(0x3C14))
+#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_OFFSET             ((uint32_t)(0x14))
+#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_RESET_VALUE        0U
+#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU
+#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U
+#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTBLUE_MASK  0xFF00U
+#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U
+#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U
+#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U
+#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTRED_MASK   0xFF000000U
+#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTRED_SHIFT  24U
+
+/* Register: IMXDPUV1_blitblend9_ColorRedBlendFunction */
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION            ((uint32_t)(0x3C18))
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_OFFSET     ((uint32_t)(0x18))
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_RESET_VALUE 0x3000300U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC_MASK 0xFFFFU
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC_SHIFT 0U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ZERO 0U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE 0x1U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_SRC_COLOR 0x300U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_SRC_COLOR 0x301U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_SRC_ALPHA 0x302U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_SRC_ALPHA 0x303U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_DST_ALPHA 0x304U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_DST_ALPHA 0x305U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_DST_COLOR 0x306U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_DST_COLOR 0x307U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_SRC_ALPHA_SATURATE 0x308U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_CONSTANT_COLOR 0x8001U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_CONSTANT_ALPHA 0x8003U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST_MASK 0xFFFF0000U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST_SHIFT 16U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ZERO 0U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE 0x1U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_SRC_COLOR 0x300U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_SRC_COLOR 0x301U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_SRC_ALPHA 0x302U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_SRC_ALPHA 0x303U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_DST_ALPHA 0x304U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_DST_ALPHA 0x305U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_DST_COLOR 0x306U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_DST_COLOR 0x307U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_SRC_ALPHA_SATURATE 0x308U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_CONSTANT_COLOR 0x8001U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_CONSTANT_ALPHA 0x8003U
+#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U
+
+/* Register: IMXDPUV1_blitblend9_ColorGreenBlendFunction */
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION          ((uint32_t)(0x3C1C))
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_OFFSET   ((uint32_t)(0x1C))
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_RESET_VALUE 0x3000300U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC_MASK 0xFFFFU
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC_SHIFT 0U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ZERO 0U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE 0x1U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_SRC_COLOR 0x300U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_SRC_COLOR 0x301U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_SRC_ALPHA 0x302U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_SRC_ALPHA 0x303U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_DST_ALPHA 0x304U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_DST_ALPHA 0x305U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_DST_COLOR 0x306U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_DST_COLOR 0x307U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_SRC_ALPHA_SATURATE 0x308U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_CONSTANT_COLOR 0x8001U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_CONSTANT_ALPHA 0x8003U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST_MASK 0xFFFF0000U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST_SHIFT 16U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ZERO 0U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE 0x1U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_SRC_COLOR 0x300U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_SRC_COLOR 0x301U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_SRC_ALPHA 0x302U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_SRC_ALPHA 0x303U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_DST_ALPHA 0x304U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_DST_ALPHA 0x305U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_DST_COLOR 0x306U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_DST_COLOR 0x307U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_SRC_ALPHA_SATURATE 0x308U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_CONSTANT_COLOR 0x8001U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_CONSTANT_ALPHA 0x8003U
+#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U
+
+/* Register: IMXDPUV1_blitblend9_ColorBlueBlendFunction */
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION           ((uint32_t)(0x3C20))
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_OFFSET    ((uint32_t)(0x20))
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_RESET_VALUE 0x3000300U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC_MASK 0xFFFFU
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC_SHIFT 0U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ZERO 0U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE 0x1U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_SRC_COLOR 0x300U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_SRC_COLOR 0x301U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_SRC_ALPHA 0x302U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_SRC_ALPHA 0x303U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_DST_ALPHA 0x304U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_DST_ALPHA 0x305U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_DST_COLOR 0x306U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_DST_COLOR 0x307U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_SRC_ALPHA_SATURATE 0x308U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_CONSTANT_COLOR 0x8001U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_CONSTANT_ALPHA 0x8003U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST_MASK 0xFFFF0000U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST_SHIFT 16U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ZERO 0U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE 0x1U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_SRC_COLOR 0x300U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_SRC_COLOR 0x301U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_SRC_ALPHA 0x302U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_SRC_ALPHA 0x303U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_DST_ALPHA 0x304U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_DST_ALPHA 0x305U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_DST_COLOR 0x306U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_DST_COLOR 0x307U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_SRC_ALPHA_SATURATE 0x308U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_CONSTANT_COLOR 0x8001U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_CONSTANT_ALPHA 0x8003U
+#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U
+
+/* Register: IMXDPUV1_blitblend9_AlphaBlendFunction */
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION               ((uint32_t)(0x3C24))
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_OFFSET        ((uint32_t)(0x24))
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_RESET_VALUE   0x3000300U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC_MASK 0xFFFFU
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC_SHIFT 0U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ZERO 0U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE 0x1U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_SRC_COLOR 0x300U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_SRC_COLOR 0x301U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_SRC_ALPHA 0x302U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_SRC_ALPHA 0x303U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_DST_ALPHA 0x304U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_DST_ALPHA 0x305U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_DST_COLOR 0x306U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_DST_COLOR 0x307U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_SRC_ALPHA_SATURATE 0x308U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_CONSTANT_COLOR 0x8001U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_CONSTANT_ALPHA 0x8003U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST_MASK 0xFFFF0000U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST_SHIFT 16U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ZERO 0U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE 0x1U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_SRC_COLOR 0x300U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_SRC_COLOR 0x301U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_SRC_ALPHA 0x302U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_SRC_ALPHA 0x303U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_DST_ALPHA 0x304U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_DST_ALPHA 0x305U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_DST_COLOR 0x306U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_DST_COLOR 0x307U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_SRC_ALPHA_SATURATE 0x308U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_CONSTANT_COLOR 0x8001U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_CONSTANT_ALPHA 0x8003U
+#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U
+
+/* Register: IMXDPUV1_blitblend9_BlendMode1 */
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1                       ((uint32_t)(0x3C28))
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_OFFSET                ((uint32_t)(0x28))
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_RESET_VALUE           0x80068006U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED_MASK 0xFFFFU
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED_SHIFT 0U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_FUNC_ADD 0x8006U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_MIN 0x8007U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_MAX 0x8008U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_FUNC_SUBTRACT 0x800AU
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_FUNC_REVERSE_SUBTRACT 0x800BU
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_SRC 0x2000U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_SRC_OVER 0x2001U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_DST_OVER 0x2002U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_SRC_IN 0x2003U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_DST_IN 0x2004U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_MULTIPLY 0x2005U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_SCREEN 0x2006U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_DARKEN 0x2007U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_LIGHTEN 0x2008U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_ADDITIVE 0x2009U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN_MASK 0xFFFF0000U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN_SHIFT 16U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_FUNC_ADD 0x8006U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_MIN 0x8007U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_MAX 0x8008U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_FUNC_SUBTRACT 0x800AU
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_FUNC_REVERSE_SUBTRACT 0x800BU
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_SRC 0x2000U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_SRC_OVER 0x2001U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_DST_OVER 0x2002U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_SRC_IN 0x2003U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_DST_IN 0x2004U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_MULTIPLY 0x2005U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_SCREEN 0x2006U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_DARKEN 0x2007U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_LIGHTEN 0x2008U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_ADDITIVE 0x2009U
+
+/* Register: IMXDPUV1_blitblend9_BlendMode2 */
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2                       ((uint32_t)(0x3C2C))
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_OFFSET                ((uint32_t)(0x2C))
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_RESET_VALUE           0x80068006U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE_MASK 0xFFFFU
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE_SHIFT 0U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_FUNC_ADD 0x8006U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_MIN 0x8007U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_MAX 0x8008U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_FUNC_SUBTRACT 0x800AU
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_FUNC_REVERSE_SUBTRACT 0x800BU
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_SRC 0x2000U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_SRC_OVER 0x2001U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_DST_OVER 0x2002U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_SRC_IN 0x2003U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_DST_IN 0x2004U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_MULTIPLY 0x2005U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_SCREEN 0x2006U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_DARKEN 0x2007U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_LIGHTEN 0x2008U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_ADDITIVE 0x2009U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA_MASK   0xFFFF0000U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA_SHIFT  16U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_FUNC_ADD 0x8006U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_MIN 0x8007U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_MAX 0x8008U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_FUNC_SUBTRACT 0x800AU
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_FUNC_REVERSE_SUBTRACT 0x800BU
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_SRC 0x2000U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_SRC_OVER 0x2001U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_DST_OVER 0x2002U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_SRC_IN 0x2003U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_DST_IN 0x2004U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_MULTIPLY 0x2005U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_SCREEN 0x2006U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_DARKEN 0x2007U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_LIGHTEN 0x2008U
+#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_ADDITIVE 0x2009U
+
+/* Register: IMXDPUV1_blitblend9_DirectSetup */
+#define IMXDPUV1_BLITBLEND9_DIRECTSETUP                      ((uint32_t)(0x3C30))
+#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_OFFSET               ((uint32_t)(0x30))
+#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_RESET_VALUE          0U
+#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_COLORDEBUG_MASK      0x3FFU
+#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_COLORDEBUG_SHIFT     0U
+#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_ALPHADEBUG_MASK      0x3FF0000U
+#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_ALPHADEBUG_SHIFT     16U
+
+/* Register: IMXDPUV1_blitblend9_PrimControlWord */
+#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD                  ((uint32_t)(0x3C34))
+#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_OFFSET           ((uint32_t)(0x34))
+#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_RESET_VALUE      0U
+#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_RESET_MASK       0U
+#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_P_VAL_MASK       0xFFFFFFFFU
+#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_P_VAL_SHIFT      0U
+
+/* Register: IMXDPUV1_blitblend9_SecControlWord */
+#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD                   ((uint32_t)(0x3C38))
+#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_OFFSET            ((uint32_t)(0x38))
+#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_RESET_VALUE       0U
+#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_RESET_MASK        0U
+#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_S_VAL_MASK        0xFFFFFFFFU
+#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_S_VAL_SHIFT       0U
+
+/* Register: IMXDPUV1_store9_LockUnlock */
+#define IMXDPUV1_STORE9_LOCKUNLOCK                           ((uint32_t)(0x4000))
+#define IMXDPUV1_STORE9_LOCKUNLOCK_OFFSET                    ((uint32_t)(0))
+#define IMXDPUV1_STORE9_LOCKUNLOCK_RESET_VALUE               0U
+#define IMXDPUV1_STORE9_LOCKUNLOCK_RESET_MASK                0U
+#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK_MASK           0xFFFFFFFFU
+#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK_SHIFT          0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY      0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY    0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY    0xFBE8B1E6U
+
+/* Register: IMXDPUV1_store9_LockStatus */
+#define IMXDPUV1_STORE9_LOCKSTATUS                           ((uint32_t)(0x4004))
+#define IMXDPUV1_STORE9_LOCKSTATUS_OFFSET                    ((uint32_t)(0x4))
+#define IMXDPUV1_STORE9_LOCKSTATUS_RESET_VALUE               0U
+#define IMXDPUV1_STORE9_LOCKSTATUS_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_STORE9_LOCKSTATUS_LOCKSTATUS_MASK           0x1U
+#define IMXDPUV1_STORE9_LOCKSTATUS_LOCKSTATUS_SHIFT          0U
+#define IMXDPUV1_STORE9_LOCKSTATUS_PRIVILEGESTATUS_MASK      0x10U
+#define IMXDPUV1_STORE9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT     4U
+#define IMXDPUV1_STORE9_LOCKSTATUS_FREEZESTATUS_MASK         0x100U
+#define IMXDPUV1_STORE9_LOCKSTATUS_FREEZESTATUS_SHIFT        8U
+
+/* Register: IMXDPUV1_store9_StaticControl */
+#define IMXDPUV1_STORE9_STATICCONTROL                        ((uint32_t)(0x4008))
+#define IMXDPUV1_STORE9_STATICCONTROL_OFFSET                 ((uint32_t)(0x8))
+#define IMXDPUV1_STORE9_STATICCONTROL_RESET_VALUE            0U
+#define IMXDPUV1_STORE9_STATICCONTROL_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_STORE9_STATICCONTROL_SHDEN_MASK             0x1U
+#define IMXDPUV1_STORE9_STATICCONTROL_SHDEN_SHIFT            0U
+#define IMXDPUV1_STORE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0x100U
+#define IMXDPUV1_STORE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 8U
+
+/* Register: IMXDPUV1_store9_BurstBufferManagement */
+#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT                ((uint32_t)(0x400C))
+#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_OFFSET         ((uint32_t)(0xC))
+#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_RESET_VALUE    0x400U
+#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U
+#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U
+
+/* Register: IMXDPUV1_store9_RingBufStartAddr */
+#define IMXDPUV1_STORE9_RINGBUFSTARTADDR                     ((uint32_t)(0x4010))
+#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_OFFSET              ((uint32_t)(0x10))
+#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_RESET_VALUE         0U
+#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_RINGBUFSTARTADDR_MASK 0xFFFFFFFFU
+#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_RINGBUFSTARTADDR_SHIFT 0U
+
+/* Register: IMXDPUV1_store9_RingBufWrapAddr */
+#define IMXDPUV1_STORE9_RINGBUFWRAPADDR                      ((uint32_t)(0x4014))
+#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_OFFSET               ((uint32_t)(0x14))
+#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_RESET_VALUE          0U
+#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_RINGBUFWRAPADDR_MASK 0xFFFFFFFFU
+#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_RINGBUFWRAPADDR_SHIFT 0U
+
+/* Register: IMXDPUV1_store9_BaseAddress */
+#define IMXDPUV1_STORE9_BASEADDRESS                          ((uint32_t)(0x4018))
+#define IMXDPUV1_STORE9_BASEADDRESS_OFFSET                   ((uint32_t)(0x18))
+#define IMXDPUV1_STORE9_BASEADDRESS_RESET_VALUE              0U
+#define IMXDPUV1_STORE9_BASEADDRESS_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_STORE9_BASEADDRESS_BASEADDRESS_MASK         0xFFFFFFFFU
+#define IMXDPUV1_STORE9_BASEADDRESS_BASEADDRESS_SHIFT        0U
+
+/* Register: IMXDPUV1_store9_DestinationBufferAttributes */
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES          ((uint32_t)(0x401C))
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_OFFSET   ((uint32_t)(0x1C))
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_RESET_VALUE 0x200004FFU
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_STRIDE_MASK 0x1FFFFU
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_STRIDE_SHIFT 0U
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_BITSPERPIXEL_MASK 0x7F000000U
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_BITSPERPIXEL_SHIFT 24U
+
+/* Register: IMXDPUV1_store9_DestinationBufferDimension */
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION           ((uint32_t)(0x4020))
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_OFFSET    ((uint32_t)(0x20))
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINEWIDTH_MASK 0x3FFFU
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINEWIDTH_SHIFT 0U
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINECOUNT_MASK 0x3FFF0000U
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINECOUNT_SHIFT 16U
+
+/* Register: IMXDPUV1_store9_FrameOffset */
+#define IMXDPUV1_STORE9_FRAMEOFFSET                          ((uint32_t)(0x4024))
+#define IMXDPUV1_STORE9_FRAMEOFFSET_OFFSET                   ((uint32_t)(0x24))
+#define IMXDPUV1_STORE9_FRAMEOFFSET_RESET_VALUE              0U
+#define IMXDPUV1_STORE9_FRAMEOFFSET_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEXOFFSET_MASK        0x7FFFU
+#define IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEXOFFSET_SHIFT       0U
+#define IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEYOFFSET_MASK        0x7FFF0000U
+#define IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEYOFFSET_SHIFT       16U
+
+/* Register: IMXDPUV1_store9_ColorComponentBits */
+#define IMXDPUV1_STORE9_COLORCOMPONENTBITS                   ((uint32_t)(0x4028))
+#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_OFFSET            ((uint32_t)(0x28))
+#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_RESET_VALUE       0x8080808U
+#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSALPHA_MASK 0xFU
+#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSALPHA_SHIFT 0U
+#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSBLUE_MASK 0xF00U
+#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSBLUE_SHIFT 8U
+#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSGREEN_MASK 0xF0000U
+#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSGREEN_SHIFT 16U
+#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSRED_MASK 0xF000000U
+#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSRED_SHIFT 24U
+
+/* Register: IMXDPUV1_store9_ColorComponentShift */
+#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT                  ((uint32_t)(0x402C))
+#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_OFFSET           ((uint32_t)(0x2C))
+#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_RESET_VALUE      0x18100800U
+#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTALPHA_MASK 0x1FU
+#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTALPHA_SHIFT 0U
+#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTBLUE_MASK 0x1F00U
+#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTBLUE_SHIFT 8U
+#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTGREEN_MASK 0x1F0000U
+#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTGREEN_SHIFT 16U
+#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTRED_MASK 0x1F000000U
+#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTRED_SHIFT 24U
+
+/* Register: IMXDPUV1_store9_Control */
+#define IMXDPUV1_STORE9_CONTROL                              ((uint32_t)(0x4030))
+#define IMXDPUV1_STORE9_CONTROL_OFFSET                       ((uint32_t)(0x30))
+#define IMXDPUV1_STORE9_CONTROL_RESET_VALUE                  0U
+#define IMXDPUV1_STORE9_CONTROL_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_STORE9_CONTROL_COLORDITHERENABLE_MASK       0x1U
+#define IMXDPUV1_STORE9_CONTROL_COLORDITHERENABLE_SHIFT      0U
+#define IMXDPUV1_STORE9_CONTROL_ALPHADITHERENABLE_MASK       0x2U
+#define IMXDPUV1_STORE9_CONTROL_ALPHADITHERENABLE_SHIFT      1U
+#define IMXDPUV1_STORE9_CONTROL_DITHEROFFSET_MASK            0xF0U
+#define IMXDPUV1_STORE9_CONTROL_DITHEROFFSET_SHIFT           4U
+#define IMXDPUV1_STORE9_CONTROL_GAMMAAPPLYENABLE_MASK        0x1000U
+#define IMXDPUV1_STORE9_CONTROL_GAMMAAPPLYENABLE_SHIFT       12U
+#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE_MASK       0x30000U
+#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE_SHIFT      16U
+/* Field Value: YUVCONVERSIONMODE__OFF, No conversion. Input data must be
+ * RGB.  */
+#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE__OFF       0U
+/* Field Value: YUVCONVERSIONMODE__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE__ITU601    0x1U
+/* Field Value: YUVCONVERSIONMODE__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE__ITU709    0x3U
+#define IMXDPUV1_STORE9_CONTROL_RASTERMODE_MASK              0xC0000U
+#define IMXDPUV1_STORE9_CONTROL_RASTERMODE_SHIFT             18U
+/* Field Value: RASTERMODE__NORMAL, RGBA or YUV 4:4:4 pixel buffer.  */
+#define IMXDPUV1_STORE9_CONTROL_RASTERMODE__NORMAL           0U
+/* Field Value: RASTERMODE__YUV422, [Store derivate only] Packed YUV 4:2:2
+ * pixel buffer. Effect is that U samples are written for pixels with even
+ * and V samples for odd column index only. So BitsPerPixel must be set
+ * to the size that a pair of YU or YV has in memory (most typically 16
+ * bits). All correlated widths and horizontal offsets must be even.  */
+#define IMXDPUV1_STORE9_CONTROL_RASTERMODE__YUV422           0x1U
+/* Field Value: RASTERMODE__ENCODE, [Store derivate only] RLAD compressed
+ * bit stream.  */
+#define IMXDPUV1_STORE9_CONTROL_RASTERMODE__ENCODE           0x2U
+#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE_MASK  0x300000U
+#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE_SHIFT 20U
+/* Field Value: YUV422DOWNSAMPLINGMODE__NEAREST, Nearest mode. Discards all
+ * odd samples, outputs even samples.  */
+#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE__NEAREST 0U
+/* Field Value: YUV422DOWNSAMPLINGMODE__COALIGNED, Linear coaligned mode.
+ * 3 nearest UV samples are combined in linear filter to get one output sample.  */
+#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE__COALIGNED 0x1U
+/* Field Value: YUV422DOWNSAMPLINGMODE__INTERSPERSED, Linear interspersed
+ * mode. 2 nearest UV samples are combined in linear filter to get one output
+ * sample.  */
+#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE__INTERSPERSED 0x2U
+
+/* Register: IMXDPUV1_store9_EncodeControl */
+#define IMXDPUV1_STORE9_ENCODECONTROL                        ((uint32_t)(0x4034))
+#define IMXDPUV1_STORE9_ENCODECONTROL_OFFSET                 ((uint32_t)(0x34))
+#define IMXDPUV1_STORE9_ENCODECONTROL_RESET_VALUE            0x88880001U
+#define IMXDPUV1_STORE9_ENCODECONTROL_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_STORE9_ENCODECONTROL_COMPRESSIONMODE_MASK   0x1U
+#define IMXDPUV1_STORE9_ENCODECONTROL_COMPRESSIONMODE_SHIFT  0U
+/* Field Value: COMPRESSIONMODE__RLAD, Run-Length Adaptive Dithering (lossy
+ * compression).  */
+#define IMXDPUV1_STORE9_ENCODECONTROL_COMPRESSIONMODE__RLAD  0U
+/* Field Value: COMPRESSIONMODE__RLAD_UNIFORM, Run-Length Adaptive Dithering
+ * (lossy compression; uniform package size).  */
+#define IMXDPUV1_STORE9_ENCODECONTROL_COMPRESSIONMODE__RLAD_UNIFORM 0x1U
+#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSRED_MASK   0xF0000U
+#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSRED_SHIFT  16U
+#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSGREEN_MASK 0xF00000U
+#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSGREEN_SHIFT 20U
+#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSBLUE_MASK  0xF000000U
+#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSBLUE_SHIFT 24U
+#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSALPHA_MASK 0xF0000000U
+#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSALPHA_SHIFT 28U
+
+/* Register: IMXDPUV1_store9_DestinationBufferLength */
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH              ((uint32_t)(0x4038))
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_OFFSET       ((uint32_t)(0x38))
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_RESET_VALUE  0U
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_RLEWORDSMAX_MASK 0x1FFFFFFFU
+#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_RLEWORDSMAX_SHIFT 0U
+
+/* Register: IMXDPUV1_store9_Start */
+#define IMXDPUV1_STORE9_START                                ((uint32_t)(0x403C))
+#define IMXDPUV1_STORE9_START_OFFSET                         ((uint32_t)(0x3C))
+#define IMXDPUV1_STORE9_START_RESET_VALUE                    0U
+#define IMXDPUV1_STORE9_START_RESET_MASK                     0xFFFFFFFEU
+#define IMXDPUV1_STORE9_START_START_MASK                     0x1U
+#define IMXDPUV1_STORE9_START_START_SHIFT                    0U
+
+/* Register: IMXDPUV1_store9_EncoderStatus */
+#define IMXDPUV1_STORE9_ENCODERSTATUS                        ((uint32_t)(0x4040))
+#define IMXDPUV1_STORE9_ENCODERSTATUS_OFFSET                 ((uint32_t)(0x40))
+#define IMXDPUV1_STORE9_ENCODERSTATUS_RESET_VALUE            0x1FFFFFFFU
+#define IMXDPUV1_STORE9_ENCODERSTATUS_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_STORE9_ENCODERSTATUS_RLEWORDS_MASK          0x1FFFFFFFU
+#define IMXDPUV1_STORE9_ENCODERSTATUS_RLEWORDS_SHIFT         0U
+#define IMXDPUV1_STORE9_ENCODERSTATUS_BUFFERTOOSMALL_MASK    0x80000000U
+#define IMXDPUV1_STORE9_ENCODERSTATUS_BUFFERTOOSMALL_SHIFT   31U
+
+/* Register: IMXDPUV1_store9_WriteAddress */
+#define IMXDPUV1_STORE9_WRITEADDRESS                         ((uint32_t)(0x4044))
+#define IMXDPUV1_STORE9_WRITEADDRESS_OFFSET                  ((uint32_t)(0x44))
+#define IMXDPUV1_STORE9_WRITEADDRESS_RESET_VALUE             0U
+#define IMXDPUV1_STORE9_WRITEADDRESS_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_STORE9_WRITEADDRESS_WRITEADDRESS_MASK       0xFFFFFFFFU
+#define IMXDPUV1_STORE9_WRITEADDRESS_WRITEADDRESS_SHIFT      0U
+
+/* Register: IMXDPUV1_store9_FrameProperties */
+#define IMXDPUV1_STORE9_FRAMEPROPERTIES                      ((uint32_t)(0x4048))
+#define IMXDPUV1_STORE9_FRAMEPROPERTIES_OFFSET               ((uint32_t)(0x48))
+#define IMXDPUV1_STORE9_FRAMEPROPERTIES_RESET_VALUE          0U
+#define IMXDPUV1_STORE9_FRAMEPROPERTIES_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_STORE9_FRAMEPROPERTIES_FIELDID_MASK         0x1U
+#define IMXDPUV1_STORE9_FRAMEPROPERTIES_FIELDID_SHIFT        0U
+
+/* Register: IMXDPUV1_store9_BurstBufferProperties */
+#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES                ((uint32_t)(0x404C))
+#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_OFFSET         ((uint32_t)(0x4C))
+#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_RESET_VALUE    0U
+#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_RESET_MASK     0xFFFFE0FFU
+#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_MAXBURSTLENGTH_MASK 0x1F00U
+#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_MAXBURSTLENGTH_SHIFT 8U
+
+/* Register: IMXDPUV1_store9_LastControlWord */
+#define IMXDPUV1_STORE9_LASTCONTROLWORD                      ((uint32_t)(0x4050))
+#define IMXDPUV1_STORE9_LASTCONTROLWORD_OFFSET               ((uint32_t)(0x50))
+#define IMXDPUV1_STORE9_LASTCONTROLWORD_RESET_VALUE          0U
+#define IMXDPUV1_STORE9_LASTCONTROLWORD_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_STORE9_LASTCONTROLWORD_L_VAL_MASK           0xFFFFFFFFU
+#define IMXDPUV1_STORE9_LASTCONTROLWORD_L_VAL_SHIFT          0U
+
+/* Register: IMXDPUV1_store9_PerfCounter */
+#define IMXDPUV1_STORE9_PERFCOUNTER                          ((uint32_t)(0x4054))
+#define IMXDPUV1_STORE9_PERFCOUNTER_OFFSET                   ((uint32_t)(0x54))
+#define IMXDPUV1_STORE9_PERFCOUNTER_RESET_VALUE              0U
+#define IMXDPUV1_STORE9_PERFCOUNTER_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_STORE9_PERFCOUNTER_PERFRESULT_MASK          0xFFFFFFFFU
+#define IMXDPUV1_STORE9_PERFCOUNTER_PERFRESULT_SHIFT         0U
+
+/* Register: IMXDPUV1_store9_Status */
+#define IMXDPUV1_STORE9_STATUS                               ((uint32_t)(0x4058))
+#define IMXDPUV1_STORE9_STATUS_OFFSET                        ((uint32_t)(0x58))
+#define IMXDPUV1_STORE9_STATUS_RESET_VALUE                   0U
+#define IMXDPUV1_STORE9_STATUS_RESET_MASK                    0xFFFFFF8EU
+#define IMXDPUV1_STORE9_STATUS_STATUSBUSY_MASK               0x1U
+#define IMXDPUV1_STORE9_STATUS_STATUSBUSY_SHIFT              0U
+#define IMXDPUV1_STORE9_STATUS_STATUSBUFFERSIDLE_MASK        0x10U
+#define IMXDPUV1_STORE9_STATUS_STATUSBUFFERSIDLE_SHIFT       4U
+#define IMXDPUV1_STORE9_STATUS_STATUSREQUEST_MASK            0x20U
+#define IMXDPUV1_STORE9_STATUS_STATUSREQUEST_SHIFT           5U
+#define IMXDPUV1_STORE9_STATUS_STATUSCOMPLETE_MASK           0x40U
+#define IMXDPUV1_STORE9_STATUS_STATUSCOMPLETE_SHIFT          6U
+#define IMXDPUV1_STORE9_STATUS_PIXELBUSERROR_MASK            0x100U
+#define IMXDPUV1_STORE9_STATUS_PIXELBUSERROR_SHIFT           8U
+#define IMXDPUV1_STORE9_STATUS_ENCODEROVERFLOW_MASK          0x10000U
+#define IMXDPUV1_STORE9_STATUS_ENCODEROVERFLOW_SHIFT         16U
+#define IMXDPUV1_STORE9_STATUS_ENCODERSTALLPIXEL_MASK        0x20000U
+#define IMXDPUV1_STORE9_STATUS_ENCODERSTALLPIXEL_SHIFT       17U
+
+/* Register: IMXDPUV1_constframe0_LockUnlock */
+#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK                      ((uint32_t)(0x4400))
+#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_OFFSET               ((uint32_t)(0))
+#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_RESET_VALUE          0U
+#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_RESET_MASK           0U
+#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK_MASK      0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK_SHIFT     0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_constframe0_LockStatus */
+#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS                      ((uint32_t)(0x4404))
+#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_OFFSET               ((uint32_t)(0x4))
+#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_RESET_VALUE          0U
+#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_LOCKSTATUS_MASK      0x1U
+#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_LOCKSTATUS_SHIFT     0U
+#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_FREEZESTATUS_MASK    0x100U
+#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_FREEZESTATUS_SHIFT   8U
+
+/* Register: IMXDPUV1_constframe0_StaticControl */
+#define IMXDPUV1_CONSTFRAME0_STATICCONTROL                   ((uint32_t)(0x4408))
+#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_OFFSET            ((uint32_t)(0x8))
+#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_RESET_VALUE       0U
+#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_SHDEN_MASK        0x1U
+#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_SHDEN_SHIFT       0U
+
+/* Register: IMXDPUV1_constframe0_FrameDimensions */
+#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS                 ((uint32_t)(0x440C))
+#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_OFFSET          ((uint32_t)(0xC))
+#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_RESET_VALUE     0xEF013FU
+#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU
+#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U
+#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U
+#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U
+#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U
+#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U
+
+/* Register: IMXDPUV1_constframe0_ConstantColor */
+#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR                   ((uint32_t)(0x4410))
+#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_OFFSET            ((uint32_t)(0x10))
+#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_RESET_VALUE       0U
+#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU
+#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U
+#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTBLUE_MASK 0xFF00U
+#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U
+#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U
+#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U
+#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTRED_MASK  0xFF000000U
+#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTRED_SHIFT 24U
+
+/* Register: IMXDPUV1_constframe0_ControlTrigger */
+#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER                  ((uint32_t)(0x4414))
+#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_OFFSET           ((uint32_t)(0x14))
+#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_RESET_VALUE      0U
+#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_RESET_MASK       0xFFFFFFFEU
+#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_SHDTOKGEN_MASK   0x1U
+#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_SHDTOKGEN_SHIFT  0U
+
+/* Register: IMXDPUV1_constframe0_Start */
+#define IMXDPUV1_CONSTFRAME0_START                           ((uint32_t)(0x4418))
+#define IMXDPUV1_CONSTFRAME0_START_OFFSET                    ((uint32_t)(0x18))
+#define IMXDPUV1_CONSTFRAME0_START_RESET_VALUE               0U
+#define IMXDPUV1_CONSTFRAME0_START_RESET_MASK                0xFFFFFFFEU
+#define IMXDPUV1_CONSTFRAME0_START_START_MASK                0x1U
+#define IMXDPUV1_CONSTFRAME0_START_START_SHIFT               0U
+
+/* Register: IMXDPUV1_constframe0_Status */
+#define IMXDPUV1_CONSTFRAME0_STATUS                          ((uint32_t)(0x441C))
+#define IMXDPUV1_CONSTFRAME0_STATUS_OFFSET                   ((uint32_t)(0x1C))
+#define IMXDPUV1_CONSTFRAME0_STATUS_RESET_VALUE              0U
+#define IMXDPUV1_CONSTFRAME0_STATUS_RESET_MASK               0xFFFFFFFCU
+#define IMXDPUV1_CONSTFRAME0_STATUS_STATUSBUSY_MASK          0x1U
+#define IMXDPUV1_CONSTFRAME0_STATUS_STATUSBUSY_SHIFT         0U
+#define IMXDPUV1_CONSTFRAME0_STATUS_SHADOWSTATUS_MASK        0x2U
+#define IMXDPUV1_CONSTFRAME0_STATUS_SHADOWSTATUS_SHIFT       1U
+
+/* Register: IMXDPUV1_extdst0_LockUnlock */
+#define IMXDPUV1_EXTDST0_LOCKUNLOCK                          ((uint32_t)(0x4800))
+#define IMXDPUV1_EXTDST0_LOCKUNLOCK_OFFSET                   ((uint32_t)(0))
+#define IMXDPUV1_EXTDST0_LOCKUNLOCK_RESET_VALUE              0U
+#define IMXDPUV1_EXTDST0_LOCKUNLOCK_RESET_MASK               0U
+#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK_MASK          0xFFFFFFFFU
+#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK_SHIFT         0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY     0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY   0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY   0xFBE8B1E6U
+
+/* Register: IMXDPUV1_extdst0_LockStatus */
+#define IMXDPUV1_EXTDST0_LOCKSTATUS                          ((uint32_t)(0x4804))
+#define IMXDPUV1_EXTDST0_LOCKSTATUS_OFFSET                   ((uint32_t)(0x4))
+#define IMXDPUV1_EXTDST0_LOCKSTATUS_RESET_VALUE              0U
+#define IMXDPUV1_EXTDST0_LOCKSTATUS_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_EXTDST0_LOCKSTATUS_LOCKSTATUS_MASK          0x1U
+#define IMXDPUV1_EXTDST0_LOCKSTATUS_LOCKSTATUS_SHIFT         0U
+#define IMXDPUV1_EXTDST0_LOCKSTATUS_PRIVILEGESTATUS_MASK     0x10U
+#define IMXDPUV1_EXTDST0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT    4U
+#define IMXDPUV1_EXTDST0_LOCKSTATUS_FREEZESTATUS_MASK        0x100U
+#define IMXDPUV1_EXTDST0_LOCKSTATUS_FREEZESTATUS_SHIFT       8U
+
+/* Register: IMXDPUV1_extdst0_StaticControl */
+#define IMXDPUV1_EXTDST0_STATICCONTROL                       ((uint32_t)(0x4808))
+#define IMXDPUV1_EXTDST0_STATICCONTROL_OFFSET                ((uint32_t)(0x8))
+#define IMXDPUV1_EXTDST0_STATICCONTROL_RESET_VALUE           0x100U
+#define IMXDPUV1_EXTDST0_STATICCONTROL_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_EXTDST0_STATICCONTROL_SHDEN_MASK            0x1U
+#define IMXDPUV1_EXTDST0_STATICCONTROL_SHDEN_SHIFT           0U
+#define IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE_MASK        0x100U
+#define IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE_SHIFT       8U
+/* Field Value: KICK_MODE__SOFTWARE, kick generation by KICK field only  */
+#define IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE__SOFTWARE   0U
+/* Field Value: KICK_MODE__EXTERNAL, kick signal from external allowed  */
+#define IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE__EXTERNAL   0x1U
+#define IMXDPUV1_EXTDST0_STATICCONTROL_PERFCOUNTMODE_MASK    0x1000U
+#define IMXDPUV1_EXTDST0_STATICCONTROL_PERFCOUNTMODE_SHIFT   12U
+
+/* Register: IMXDPUV1_extdst0_Control */
+#define IMXDPUV1_EXTDST0_CONTROL                             ((uint32_t)(0x480C))
+#define IMXDPUV1_EXTDST0_CONTROL_OFFSET                      ((uint32_t)(0xC))
+#define IMXDPUV1_EXTDST0_CONTROL_RESET_VALUE                 0U
+#define IMXDPUV1_EXTDST0_CONTROL_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_EXTDST0_CONTROL_GAMMAAPPLYENABLE_MASK       0x1U
+#define IMXDPUV1_EXTDST0_CONTROL_GAMMAAPPLYENABLE_SHIFT      0U
+
+/* Register: IMXDPUV1_extdst0_SoftwareKick */
+#define IMXDPUV1_EXTDST0_SOFTWAREKICK                        ((uint32_t)(0x4810))
+#define IMXDPUV1_EXTDST0_SOFTWAREKICK_OFFSET                 ((uint32_t)(0x10))
+#define IMXDPUV1_EXTDST0_SOFTWAREKICK_RESET_VALUE            0U
+#define IMXDPUV1_EXTDST0_SOFTWAREKICK_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_EXTDST0_SOFTWAREKICK_KICK_MASK              0x1U
+#define IMXDPUV1_EXTDST0_SOFTWAREKICK_KICK_SHIFT             0U
+
+/* Register: IMXDPUV1_extdst0_Status */
+#define IMXDPUV1_EXTDST0_STATUS                              ((uint32_t)(0x4814))
+#define IMXDPUV1_EXTDST0_STATUS_OFFSET                       ((uint32_t)(0x14))
+#define IMXDPUV1_EXTDST0_STATUS_RESET_VALUE                  0U
+#define IMXDPUV1_EXTDST0_STATUS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_EXTDST0_STATUS_CNT_ERR_STS_MASK             0x1U
+#define IMXDPUV1_EXTDST0_STATUS_CNT_ERR_STS_SHIFT            0U
+
+/* Register: IMXDPUV1_extdst0_ControlWord */
+#define IMXDPUV1_EXTDST0_CONTROLWORD                         ((uint32_t)(0x4818))
+#define IMXDPUV1_EXTDST0_CONTROLWORD_OFFSET                  ((uint32_t)(0x18))
+#define IMXDPUV1_EXTDST0_CONTROLWORD_RESET_VALUE             0U
+#define IMXDPUV1_EXTDST0_CONTROLWORD_RESET_MASK              0U
+#define IMXDPUV1_EXTDST0_CONTROLWORD_CW_VAL_MASK             0xFFFFFFFFU
+#define IMXDPUV1_EXTDST0_CONTROLWORD_CW_VAL_SHIFT            0U
+
+/* Register: IMXDPUV1_extdst0_CurPixelCnt */
+#define IMXDPUV1_EXTDST0_CURPIXELCNT                         ((uint32_t)(0x481C))
+#define IMXDPUV1_EXTDST0_CURPIXELCNT_OFFSET                  ((uint32_t)(0x1C))
+#define IMXDPUV1_EXTDST0_CURPIXELCNT_RESET_VALUE             0U
+#define IMXDPUV1_EXTDST0_CURPIXELCNT_RESET_MASK              0U
+#define IMXDPUV1_EXTDST0_CURPIXELCNT_C_XVAL_MASK             0xFFFFU
+#define IMXDPUV1_EXTDST0_CURPIXELCNT_C_XVAL_SHIFT            0U
+#define IMXDPUV1_EXTDST0_CURPIXELCNT_C_YVAL_MASK             0xFFFF0000U
+#define IMXDPUV1_EXTDST0_CURPIXELCNT_C_YVAL_SHIFT            16U
+
+/* Register: IMXDPUV1_extdst0_LastPixelCnt */
+#define IMXDPUV1_EXTDST0_LASTPIXELCNT                        ((uint32_t)(0x4820))
+#define IMXDPUV1_EXTDST0_LASTPIXELCNT_OFFSET                 ((uint32_t)(0x20))
+#define IMXDPUV1_EXTDST0_LASTPIXELCNT_RESET_VALUE            0U
+#define IMXDPUV1_EXTDST0_LASTPIXELCNT_RESET_MASK             0U
+#define IMXDPUV1_EXTDST0_LASTPIXELCNT_L_XVAL_MASK            0xFFFFU
+#define IMXDPUV1_EXTDST0_LASTPIXELCNT_L_XVAL_SHIFT           0U
+#define IMXDPUV1_EXTDST0_LASTPIXELCNT_L_YVAL_MASK            0xFFFF0000U
+#define IMXDPUV1_EXTDST0_LASTPIXELCNT_L_YVAL_SHIFT           16U
+
+/* Register: IMXDPUV1_extdst0_PerfCounter */
+#define IMXDPUV1_EXTDST0_PERFCOUNTER                         ((uint32_t)(0x4824))
+#define IMXDPUV1_EXTDST0_PERFCOUNTER_OFFSET                  ((uint32_t)(0x24))
+#define IMXDPUV1_EXTDST0_PERFCOUNTER_RESET_VALUE             0U
+#define IMXDPUV1_EXTDST0_PERFCOUNTER_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_EXTDST0_PERFCOUNTER_PERFRESULT_MASK         0xFFFFFFFFU
+#define IMXDPUV1_EXTDST0_PERFCOUNTER_PERFRESULT_SHIFT        0U
+
+/* Register: IMXDPUV1_constframe4_LockUnlock */
+#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK                      ((uint32_t)(0x4C00))
+#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_OFFSET               ((uint32_t)(0))
+#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_RESET_VALUE          0U
+#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_RESET_MASK           0U
+#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK_MASK      0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK_SHIFT     0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_constframe4_LockStatus */
+#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS                      ((uint32_t)(0x4C04))
+#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_OFFSET               ((uint32_t)(0x4))
+#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_RESET_VALUE          0U
+#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_LOCKSTATUS_MASK      0x1U
+#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_LOCKSTATUS_SHIFT     0U
+#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_FREEZESTATUS_MASK    0x100U
+#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_FREEZESTATUS_SHIFT   8U
+
+/* Register: IMXDPUV1_constframe4_StaticControl */
+#define IMXDPUV1_CONSTFRAME4_STATICCONTROL                   ((uint32_t)(0x4C08))
+#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_OFFSET            ((uint32_t)(0x8))
+#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_RESET_VALUE       0U
+#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_SHDEN_MASK        0x1U
+#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_SHDEN_SHIFT       0U
+
+/* Register: IMXDPUV1_constframe4_FrameDimensions */
+#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS                 ((uint32_t)(0x4C0C))
+#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_OFFSET          ((uint32_t)(0xC))
+#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_RESET_VALUE     0xEF013FU
+#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU
+#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U
+#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U
+#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U
+#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U
+#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U
+
+/* Register: IMXDPUV1_constframe4_ConstantColor */
+#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR                   ((uint32_t)(0x4C10))
+#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_OFFSET            ((uint32_t)(0x10))
+#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_RESET_VALUE       0U
+#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU
+#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U
+#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTBLUE_MASK 0xFF00U
+#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U
+#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U
+#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U
+#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTRED_MASK  0xFF000000U
+#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTRED_SHIFT 24U
+
+/* Register: IMXDPUV1_constframe4_ControlTrigger */
+#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER                  ((uint32_t)(0x4C14))
+#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_OFFSET           ((uint32_t)(0x14))
+#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_RESET_VALUE      0U
+#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_RESET_MASK       0xFFFFFFFEU
+#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_SHDTOKGEN_MASK   0x1U
+#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_SHDTOKGEN_SHIFT  0U
+
+/* Register: IMXDPUV1_constframe4_Start */
+#define IMXDPUV1_CONSTFRAME4_START                           ((uint32_t)(0x4C18))
+#define IMXDPUV1_CONSTFRAME4_START_OFFSET                    ((uint32_t)(0x18))
+#define IMXDPUV1_CONSTFRAME4_START_RESET_VALUE               0U
+#define IMXDPUV1_CONSTFRAME4_START_RESET_MASK                0xFFFFFFFEU
+#define IMXDPUV1_CONSTFRAME4_START_START_MASK                0x1U
+#define IMXDPUV1_CONSTFRAME4_START_START_SHIFT               0U
+
+/* Register: IMXDPUV1_constframe4_Status */
+#define IMXDPUV1_CONSTFRAME4_STATUS                          ((uint32_t)(0x4C1C))
+#define IMXDPUV1_CONSTFRAME4_STATUS_OFFSET                   ((uint32_t)(0x1C))
+#define IMXDPUV1_CONSTFRAME4_STATUS_RESET_VALUE              0U
+#define IMXDPUV1_CONSTFRAME4_STATUS_RESET_MASK               0xFFFFFFFCU
+#define IMXDPUV1_CONSTFRAME4_STATUS_STATUSBUSY_MASK          0x1U
+#define IMXDPUV1_CONSTFRAME4_STATUS_STATUSBUSY_SHIFT         0U
+#define IMXDPUV1_CONSTFRAME4_STATUS_SHADOWSTATUS_MASK        0x2U
+#define IMXDPUV1_CONSTFRAME4_STATUS_SHADOWSTATUS_SHIFT       1U
+
+/* Register: IMXDPUV1_extdst4_LockUnlock */
+#define IMXDPUV1_EXTDST4_LOCKUNLOCK                          ((uint32_t)(0x5000))
+#define IMXDPUV1_EXTDST4_LOCKUNLOCK_OFFSET                   ((uint32_t)(0))
+#define IMXDPUV1_EXTDST4_LOCKUNLOCK_RESET_VALUE              0U
+#define IMXDPUV1_EXTDST4_LOCKUNLOCK_RESET_MASK               0U
+#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK_MASK          0xFFFFFFFFU
+#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK_SHIFT         0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY     0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY   0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY   0xFBE8B1E6U
+
+/* Register: IMXDPUV1_extdst4_LockStatus */
+#define IMXDPUV1_EXTDST4_LOCKSTATUS                          ((uint32_t)(0x5004))
+#define IMXDPUV1_EXTDST4_LOCKSTATUS_OFFSET                   ((uint32_t)(0x4))
+#define IMXDPUV1_EXTDST4_LOCKSTATUS_RESET_VALUE              0U
+#define IMXDPUV1_EXTDST4_LOCKSTATUS_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_EXTDST4_LOCKSTATUS_LOCKSTATUS_MASK          0x1U
+#define IMXDPUV1_EXTDST4_LOCKSTATUS_LOCKSTATUS_SHIFT         0U
+#define IMXDPUV1_EXTDST4_LOCKSTATUS_PRIVILEGESTATUS_MASK     0x10U
+#define IMXDPUV1_EXTDST4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT    4U
+#define IMXDPUV1_EXTDST4_LOCKSTATUS_FREEZESTATUS_MASK        0x100U
+#define IMXDPUV1_EXTDST4_LOCKSTATUS_FREEZESTATUS_SHIFT       8U
+
+/* Register: IMXDPUV1_extdst4_StaticControl */
+#define IMXDPUV1_EXTDST4_STATICCONTROL                       ((uint32_t)(0x5008))
+#define IMXDPUV1_EXTDST4_STATICCONTROL_OFFSET                ((uint32_t)(0x8))
+#define IMXDPUV1_EXTDST4_STATICCONTROL_RESET_VALUE           0x100U
+#define IMXDPUV1_EXTDST4_STATICCONTROL_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_EXTDST4_STATICCONTROL_SHDEN_MASK            0x1U
+#define IMXDPUV1_EXTDST4_STATICCONTROL_SHDEN_SHIFT           0U
+#define IMXDPUV1_EXTDST4_STATICCONTROL_KICK_MODE_MASK        0x100U
+#define IMXDPUV1_EXTDST4_STATICCONTROL_KICK_MODE_SHIFT       8U
+/* Field Value: KICK_MODE__SOFTWARE, kick generation by KICK field only  */
+#define IMXDPUV1_EXTDST4_STATICCONTROL_KICK_MODE__SOFTWARE   0U
+/* Field Value: KICK_MODE__EXTERNAL, kick signal from external allowed  */
+#define IMXDPUV1_EXTDST4_STATICCONTROL_KICK_MODE__EXTERNAL   0x1U
+#define IMXDPUV1_EXTDST4_STATICCONTROL_PERFCOUNTMODE_MASK    0x1000U
+#define IMXDPUV1_EXTDST4_STATICCONTROL_PERFCOUNTMODE_SHIFT   12U
+
+/* Register: IMXDPUV1_extdst4_Control */
+#define IMXDPUV1_EXTDST4_CONTROL                             ((uint32_t)(0x500C))
+#define IMXDPUV1_EXTDST4_CONTROL_OFFSET                      ((uint32_t)(0xC))
+#define IMXDPUV1_EXTDST4_CONTROL_RESET_VALUE                 0U
+#define IMXDPUV1_EXTDST4_CONTROL_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_EXTDST4_CONTROL_GAMMAAPPLYENABLE_MASK       0x1U
+#define IMXDPUV1_EXTDST4_CONTROL_GAMMAAPPLYENABLE_SHIFT      0U
+
+/* Register: IMXDPUV1_extdst4_SoftwareKick */
+#define IMXDPUV1_EXTDST4_SOFTWAREKICK                        ((uint32_t)(0x5010))
+#define IMXDPUV1_EXTDST4_SOFTWAREKICK_OFFSET                 ((uint32_t)(0x10))
+#define IMXDPUV1_EXTDST4_SOFTWAREKICK_RESET_VALUE            0U
+#define IMXDPUV1_EXTDST4_SOFTWAREKICK_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_EXTDST4_SOFTWAREKICK_KICK_MASK              0x1U
+#define IMXDPUV1_EXTDST4_SOFTWAREKICK_KICK_SHIFT             0U
+
+/* Register: IMXDPUV1_extdst4_Status */
+#define IMXDPUV1_EXTDST4_STATUS                              ((uint32_t)(0x5014))
+#define IMXDPUV1_EXTDST4_STATUS_OFFSET                       ((uint32_t)(0x14))
+#define IMXDPUV1_EXTDST4_STATUS_RESET_VALUE                  0U
+#define IMXDPUV1_EXTDST4_STATUS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_EXTDST4_STATUS_CNT_ERR_STS_MASK             0x1U
+#define IMXDPUV1_EXTDST4_STATUS_CNT_ERR_STS_SHIFT            0U
+
+/* Register: IMXDPUV1_extdst4_ControlWord */
+#define IMXDPUV1_EXTDST4_CONTROLWORD                         ((uint32_t)(0x5018))
+#define IMXDPUV1_EXTDST4_CONTROLWORD_OFFSET                  ((uint32_t)(0x18))
+#define IMXDPUV1_EXTDST4_CONTROLWORD_RESET_VALUE             0U
+#define IMXDPUV1_EXTDST4_CONTROLWORD_RESET_MASK              0U
+#define IMXDPUV1_EXTDST4_CONTROLWORD_CW_VAL_MASK             0xFFFFFFFFU
+#define IMXDPUV1_EXTDST4_CONTROLWORD_CW_VAL_SHIFT            0U
+
+/* Register: IMXDPUV1_extdst4_CurPixelCnt */
+#define IMXDPUV1_EXTDST4_CURPIXELCNT                         ((uint32_t)(0x501C))
+#define IMXDPUV1_EXTDST4_CURPIXELCNT_OFFSET                  ((uint32_t)(0x1C))
+#define IMXDPUV1_EXTDST4_CURPIXELCNT_RESET_VALUE             0U
+#define IMXDPUV1_EXTDST4_CURPIXELCNT_RESET_MASK              0U
+#define IMXDPUV1_EXTDST4_CURPIXELCNT_C_XVAL_MASK             0xFFFFU
+#define IMXDPUV1_EXTDST4_CURPIXELCNT_C_XVAL_SHIFT            0U
+#define IMXDPUV1_EXTDST4_CURPIXELCNT_C_YVAL_MASK             0xFFFF0000U
+#define IMXDPUV1_EXTDST4_CURPIXELCNT_C_YVAL_SHIFT            16U
+
+/* Register: IMXDPUV1_extdst4_LastPixelCnt */
+#define IMXDPUV1_EXTDST4_LASTPIXELCNT                        ((uint32_t)(0x5020))
+#define IMXDPUV1_EXTDST4_LASTPIXELCNT_OFFSET                 ((uint32_t)(0x20))
+#define IMXDPUV1_EXTDST4_LASTPIXELCNT_RESET_VALUE            0U
+#define IMXDPUV1_EXTDST4_LASTPIXELCNT_RESET_MASK             0U
+#define IMXDPUV1_EXTDST4_LASTPIXELCNT_L_XVAL_MASK            0xFFFFU
+#define IMXDPUV1_EXTDST4_LASTPIXELCNT_L_XVAL_SHIFT           0U
+#define IMXDPUV1_EXTDST4_LASTPIXELCNT_L_YVAL_MASK            0xFFFF0000U
+#define IMXDPUV1_EXTDST4_LASTPIXELCNT_L_YVAL_SHIFT           16U
+
+/* Register: IMXDPUV1_extdst4_PerfCounter */
+#define IMXDPUV1_EXTDST4_PERFCOUNTER                         ((uint32_t)(0x5024))
+#define IMXDPUV1_EXTDST4_PERFCOUNTER_OFFSET                  ((uint32_t)(0x24))
+#define IMXDPUV1_EXTDST4_PERFCOUNTER_RESET_VALUE             0U
+#define IMXDPUV1_EXTDST4_PERFCOUNTER_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_EXTDST4_PERFCOUNTER_PERFRESULT_MASK         0xFFFFFFFFU
+#define IMXDPUV1_EXTDST4_PERFCOUNTER_PERFRESULT_SHIFT        0U
+
+/* Register: IMXDPUV1_constframe1_LockUnlock */
+#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK                      ((uint32_t)(0x5400))
+#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_OFFSET               ((uint32_t)(0))
+#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_RESET_VALUE          0U
+#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_RESET_MASK           0U
+#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK_MASK      0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK_SHIFT     0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_constframe1_LockStatus */
+#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS                      ((uint32_t)(0x5404))
+#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_OFFSET               ((uint32_t)(0x4))
+#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_RESET_VALUE          0U
+#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_LOCKSTATUS_MASK      0x1U
+#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_LOCKSTATUS_SHIFT     0U
+#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_FREEZESTATUS_MASK    0x100U
+#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_FREEZESTATUS_SHIFT   8U
+
+/* Register: IMXDPUV1_constframe1_StaticControl */
+#define IMXDPUV1_CONSTFRAME1_STATICCONTROL                   ((uint32_t)(0x5408))
+#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_OFFSET            ((uint32_t)(0x8))
+#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_RESET_VALUE       0U
+#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_SHDEN_MASK        0x1U
+#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_SHDEN_SHIFT       0U
+
+/* Register: IMXDPUV1_constframe1_FrameDimensions */
+#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS                 ((uint32_t)(0x540C))
+#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_OFFSET          ((uint32_t)(0xC))
+#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_RESET_VALUE     0xEF013FU
+#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU
+#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U
+#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U
+#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U
+#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U
+#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U
+
+/* Register: IMXDPUV1_constframe1_ConstantColor */
+#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR                   ((uint32_t)(0x5410))
+#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_OFFSET            ((uint32_t)(0x10))
+#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_RESET_VALUE       0U
+#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU
+#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U
+#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTBLUE_MASK 0xFF00U
+#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U
+#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U
+#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U
+#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTRED_MASK  0xFF000000U
+#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTRED_SHIFT 24U
+
+/* Register: IMXDPUV1_constframe1_ControlTrigger */
+#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER                  ((uint32_t)(0x5414))
+#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_OFFSET           ((uint32_t)(0x14))
+#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_RESET_VALUE      0U
+#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_RESET_MASK       0xFFFFFFFEU
+#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_SHDTOKGEN_MASK   0x1U
+#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_SHDTOKGEN_SHIFT  0U
+
+/* Register: IMXDPUV1_constframe1_Start */
+#define IMXDPUV1_CONSTFRAME1_START                           ((uint32_t)(0x5418))
+#define IMXDPUV1_CONSTFRAME1_START_OFFSET                    ((uint32_t)(0x18))
+#define IMXDPUV1_CONSTFRAME1_START_RESET_VALUE               0U
+#define IMXDPUV1_CONSTFRAME1_START_RESET_MASK                0xFFFFFFFEU
+#define IMXDPUV1_CONSTFRAME1_START_START_MASK                0x1U
+#define IMXDPUV1_CONSTFRAME1_START_START_SHIFT               0U
+
+/* Register: IMXDPUV1_constframe1_Status */
+#define IMXDPUV1_CONSTFRAME1_STATUS                          ((uint32_t)(0x541C))
+#define IMXDPUV1_CONSTFRAME1_STATUS_OFFSET                   ((uint32_t)(0x1C))
+#define IMXDPUV1_CONSTFRAME1_STATUS_RESET_VALUE              0U
+#define IMXDPUV1_CONSTFRAME1_STATUS_RESET_MASK               0xFFFFFFFCU
+#define IMXDPUV1_CONSTFRAME1_STATUS_STATUSBUSY_MASK          0x1U
+#define IMXDPUV1_CONSTFRAME1_STATUS_STATUSBUSY_SHIFT         0U
+#define IMXDPUV1_CONSTFRAME1_STATUS_SHADOWSTATUS_MASK        0x2U
+#define IMXDPUV1_CONSTFRAME1_STATUS_SHADOWSTATUS_SHIFT       1U
+
+/* Register: IMXDPUV1_extdst1_LockUnlock */
+#define IMXDPUV1_EXTDST1_LOCKUNLOCK                          ((uint32_t)(0x5800))
+#define IMXDPUV1_EXTDST1_LOCKUNLOCK_OFFSET                   ((uint32_t)(0))
+#define IMXDPUV1_EXTDST1_LOCKUNLOCK_RESET_VALUE              0U
+#define IMXDPUV1_EXTDST1_LOCKUNLOCK_RESET_MASK               0U
+#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK_MASK          0xFFFFFFFFU
+#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK_SHIFT         0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY     0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY   0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY   0xFBE8B1E6U
+
+/* Register: IMXDPUV1_extdst1_LockStatus */
+#define IMXDPUV1_EXTDST1_LOCKSTATUS                          ((uint32_t)(0x5804))
+#define IMXDPUV1_EXTDST1_LOCKSTATUS_OFFSET                   ((uint32_t)(0x4))
+#define IMXDPUV1_EXTDST1_LOCKSTATUS_RESET_VALUE              0U
+#define IMXDPUV1_EXTDST1_LOCKSTATUS_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_EXTDST1_LOCKSTATUS_LOCKSTATUS_MASK          0x1U
+#define IMXDPUV1_EXTDST1_LOCKSTATUS_LOCKSTATUS_SHIFT         0U
+#define IMXDPUV1_EXTDST1_LOCKSTATUS_PRIVILEGESTATUS_MASK     0x10U
+#define IMXDPUV1_EXTDST1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT    4U
+#define IMXDPUV1_EXTDST1_LOCKSTATUS_FREEZESTATUS_MASK        0x100U
+#define IMXDPUV1_EXTDST1_LOCKSTATUS_FREEZESTATUS_SHIFT       8U
+
+/* Register: IMXDPUV1_extdst1_StaticControl */
+#define IMXDPUV1_EXTDST1_STATICCONTROL                       ((uint32_t)(0x5808))
+#define IMXDPUV1_EXTDST1_STATICCONTROL_OFFSET                ((uint32_t)(0x8))
+#define IMXDPUV1_EXTDST1_STATICCONTROL_RESET_VALUE           0x100U
+#define IMXDPUV1_EXTDST1_STATICCONTROL_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_EXTDST1_STATICCONTROL_SHDEN_MASK            0x1U
+#define IMXDPUV1_EXTDST1_STATICCONTROL_SHDEN_SHIFT           0U
+#define IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE_MASK        0x100U
+#define IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE_SHIFT       8U
+/* Field Value: KICK_MODE__SOFTWARE, kick generation by KICK field only  */
+#define IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE__SOFTWARE   0U
+/* Field Value: KICK_MODE__EXTERNAL, kick signal from external allowed  */
+#define IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE__EXTERNAL   0x1U
+#define IMXDPUV1_EXTDST1_STATICCONTROL_PERFCOUNTMODE_MASK    0x1000U
+#define IMXDPUV1_EXTDST1_STATICCONTROL_PERFCOUNTMODE_SHIFT   12U
+
+/* Register: IMXDPUV1_extdst1_Control */
+#define IMXDPUV1_EXTDST1_CONTROL                             ((uint32_t)(0x580C))
+#define IMXDPUV1_EXTDST1_CONTROL_OFFSET                      ((uint32_t)(0xC))
+#define IMXDPUV1_EXTDST1_CONTROL_RESET_VALUE                 0U
+#define IMXDPUV1_EXTDST1_CONTROL_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_EXTDST1_CONTROL_GAMMAAPPLYENABLE_MASK       0x1U
+#define IMXDPUV1_EXTDST1_CONTROL_GAMMAAPPLYENABLE_SHIFT      0U
+
+/* Register: IMXDPUV1_extdst1_SoftwareKick */
+#define IMXDPUV1_EXTDST1_SOFTWAREKICK                        ((uint32_t)(0x5810))
+#define IMXDPUV1_EXTDST1_SOFTWAREKICK_OFFSET                 ((uint32_t)(0x10))
+#define IMXDPUV1_EXTDST1_SOFTWAREKICK_RESET_VALUE            0U
+#define IMXDPUV1_EXTDST1_SOFTWAREKICK_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_EXTDST1_SOFTWAREKICK_KICK_MASK              0x1U
+#define IMXDPUV1_EXTDST1_SOFTWAREKICK_KICK_SHIFT             0U
+
+/* Register: IMXDPUV1_extdst1_Status */
+#define IMXDPUV1_EXTDST1_STATUS                              ((uint32_t)(0x5814))
+#define IMXDPUV1_EXTDST1_STATUS_OFFSET                       ((uint32_t)(0x14))
+#define IMXDPUV1_EXTDST1_STATUS_RESET_VALUE                  0U
+#define IMXDPUV1_EXTDST1_STATUS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_EXTDST1_STATUS_CNT_ERR_STS_MASK             0x1U
+#define IMXDPUV1_EXTDST1_STATUS_CNT_ERR_STS_SHIFT            0U
+
+/* Register: IMXDPUV1_extdst1_ControlWord */
+#define IMXDPUV1_EXTDST1_CONTROLWORD                         ((uint32_t)(0x5818))
+#define IMXDPUV1_EXTDST1_CONTROLWORD_OFFSET                  ((uint32_t)(0x18))
+#define IMXDPUV1_EXTDST1_CONTROLWORD_RESET_VALUE             0U
+#define IMXDPUV1_EXTDST1_CONTROLWORD_RESET_MASK              0U
+#define IMXDPUV1_EXTDST1_CONTROLWORD_CW_VAL_MASK             0xFFFFFFFFU
+#define IMXDPUV1_EXTDST1_CONTROLWORD_CW_VAL_SHIFT            0U
+
+/* Register: IMXDPUV1_extdst1_CurPixelCnt */
+#define IMXDPUV1_EXTDST1_CURPIXELCNT                         ((uint32_t)(0x581C))
+#define IMXDPUV1_EXTDST1_CURPIXELCNT_OFFSET                  ((uint32_t)(0x1C))
+#define IMXDPUV1_EXTDST1_CURPIXELCNT_RESET_VALUE             0U
+#define IMXDPUV1_EXTDST1_CURPIXELCNT_RESET_MASK              0U
+#define IMXDPUV1_EXTDST1_CURPIXELCNT_C_XVAL_MASK             0xFFFFU
+#define IMXDPUV1_EXTDST1_CURPIXELCNT_C_XVAL_SHIFT            0U
+#define IMXDPUV1_EXTDST1_CURPIXELCNT_C_YVAL_MASK             0xFFFF0000U
+#define IMXDPUV1_EXTDST1_CURPIXELCNT_C_YVAL_SHIFT            16U
+
+/* Register: IMXDPUV1_extdst1_LastPixelCnt */
+#define IMXDPUV1_EXTDST1_LASTPIXELCNT                        ((uint32_t)(0x5820))
+#define IMXDPUV1_EXTDST1_LASTPIXELCNT_OFFSET                 ((uint32_t)(0x20))
+#define IMXDPUV1_EXTDST1_LASTPIXELCNT_RESET_VALUE            0U
+#define IMXDPUV1_EXTDST1_LASTPIXELCNT_RESET_MASK             0U
+#define IMXDPUV1_EXTDST1_LASTPIXELCNT_L_XVAL_MASK            0xFFFFU
+#define IMXDPUV1_EXTDST1_LASTPIXELCNT_L_XVAL_SHIFT           0U
+#define IMXDPUV1_EXTDST1_LASTPIXELCNT_L_YVAL_MASK            0xFFFF0000U
+#define IMXDPUV1_EXTDST1_LASTPIXELCNT_L_YVAL_SHIFT           16U
+
+/* Register: IMXDPUV1_extdst1_PerfCounter */
+#define IMXDPUV1_EXTDST1_PERFCOUNTER                         ((uint32_t)(0x5824))
+#define IMXDPUV1_EXTDST1_PERFCOUNTER_OFFSET                  ((uint32_t)(0x24))
+#define IMXDPUV1_EXTDST1_PERFCOUNTER_RESET_VALUE             0U
+#define IMXDPUV1_EXTDST1_PERFCOUNTER_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_EXTDST1_PERFCOUNTER_PERFRESULT_MASK         0xFFFFFFFFU
+#define IMXDPUV1_EXTDST1_PERFCOUNTER_PERFRESULT_SHIFT        0U
+
+/* Register: IMXDPUV1_constframe5_LockUnlock */
+#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK                      ((uint32_t)(0x5C00))
+#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_OFFSET               ((uint32_t)(0))
+#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_RESET_VALUE          0U
+#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_RESET_MASK           0U
+#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK_MASK      0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK_SHIFT     0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_constframe5_LockStatus */
+#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS                      ((uint32_t)(0x5C04))
+#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_OFFSET               ((uint32_t)(0x4))
+#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_RESET_VALUE          0U
+#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_LOCKSTATUS_MASK      0x1U
+#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_LOCKSTATUS_SHIFT     0U
+#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_FREEZESTATUS_MASK    0x100U
+#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_FREEZESTATUS_SHIFT   8U
+
+/* Register: IMXDPUV1_constframe5_StaticControl */
+#define IMXDPUV1_CONSTFRAME5_STATICCONTROL                   ((uint32_t)(0x5C08))
+#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_OFFSET            ((uint32_t)(0x8))
+#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_RESET_VALUE       0U
+#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_SHDEN_MASK        0x1U
+#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_SHDEN_SHIFT       0U
+
+/* Register: IMXDPUV1_constframe5_FrameDimensions */
+#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS                 ((uint32_t)(0x5C0C))
+#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_OFFSET          ((uint32_t)(0xC))
+#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_RESET_VALUE     0xEF013FU
+#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU
+#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U
+#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U
+#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U
+#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U
+#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U
+
+/* Register: IMXDPUV1_constframe5_ConstantColor */
+#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR                   ((uint32_t)(0x5C10))
+#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_OFFSET            ((uint32_t)(0x10))
+#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_RESET_VALUE       0U
+#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU
+#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U
+#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTBLUE_MASK 0xFF00U
+#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U
+#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U
+#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U
+#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTRED_MASK  0xFF000000U
+#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTRED_SHIFT 24U
+
+/* Register: IMXDPUV1_constframe5_ControlTrigger */
+#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER                  ((uint32_t)(0x5C14))
+#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_OFFSET           ((uint32_t)(0x14))
+#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_RESET_VALUE      0U
+#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_RESET_MASK       0xFFFFFFFEU
+#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_SHDTOKGEN_MASK   0x1U
+#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_SHDTOKGEN_SHIFT  0U
+
+/* Register: IMXDPUV1_constframe5_Start */
+#define IMXDPUV1_CONSTFRAME5_START                           ((uint32_t)(0x5C18))
+#define IMXDPUV1_CONSTFRAME5_START_OFFSET                    ((uint32_t)(0x18))
+#define IMXDPUV1_CONSTFRAME5_START_RESET_VALUE               0U
+#define IMXDPUV1_CONSTFRAME5_START_RESET_MASK                0xFFFFFFFEU
+#define IMXDPUV1_CONSTFRAME5_START_START_MASK                0x1U
+#define IMXDPUV1_CONSTFRAME5_START_START_SHIFT               0U
+
+/* Register: IMXDPUV1_constframe5_Status */
+#define IMXDPUV1_CONSTFRAME5_STATUS                          ((uint32_t)(0x5C1C))
+#define IMXDPUV1_CONSTFRAME5_STATUS_OFFSET                   ((uint32_t)(0x1C))
+#define IMXDPUV1_CONSTFRAME5_STATUS_RESET_VALUE              0U
+#define IMXDPUV1_CONSTFRAME5_STATUS_RESET_MASK               0xFFFFFFFCU
+#define IMXDPUV1_CONSTFRAME5_STATUS_STATUSBUSY_MASK          0x1U
+#define IMXDPUV1_CONSTFRAME5_STATUS_STATUSBUSY_SHIFT         0U
+#define IMXDPUV1_CONSTFRAME5_STATUS_SHADOWSTATUS_MASK        0x2U
+#define IMXDPUV1_CONSTFRAME5_STATUS_SHADOWSTATUS_SHIFT       1U
+
+/* Register: IMXDPUV1_extdst5_LockUnlock */
+#define IMXDPUV1_EXTDST5_LOCKUNLOCK                          ((uint32_t)(0x6000))
+#define IMXDPUV1_EXTDST5_LOCKUNLOCK_OFFSET                   ((uint32_t)(0))
+#define IMXDPUV1_EXTDST5_LOCKUNLOCK_RESET_VALUE              0U
+#define IMXDPUV1_EXTDST5_LOCKUNLOCK_RESET_MASK               0U
+#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK_MASK          0xFFFFFFFFU
+#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK_SHIFT         0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY     0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY   0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY   0xFBE8B1E6U
+
+/* Register: IMXDPUV1_extdst5_LockStatus */
+#define IMXDPUV1_EXTDST5_LOCKSTATUS                          ((uint32_t)(0x6004))
+#define IMXDPUV1_EXTDST5_LOCKSTATUS_OFFSET                   ((uint32_t)(0x4))
+#define IMXDPUV1_EXTDST5_LOCKSTATUS_RESET_VALUE              0U
+#define IMXDPUV1_EXTDST5_LOCKSTATUS_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_EXTDST5_LOCKSTATUS_LOCKSTATUS_MASK          0x1U
+#define IMXDPUV1_EXTDST5_LOCKSTATUS_LOCKSTATUS_SHIFT         0U
+#define IMXDPUV1_EXTDST5_LOCKSTATUS_PRIVILEGESTATUS_MASK     0x10U
+#define IMXDPUV1_EXTDST5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT    4U
+#define IMXDPUV1_EXTDST5_LOCKSTATUS_FREEZESTATUS_MASK        0x100U
+#define IMXDPUV1_EXTDST5_LOCKSTATUS_FREEZESTATUS_SHIFT       8U
+
+/* Register: IMXDPUV1_extdst5_StaticControl */
+#define IMXDPUV1_EXTDST5_STATICCONTROL                       ((uint32_t)(0x6008))
+#define IMXDPUV1_EXTDST5_STATICCONTROL_OFFSET                ((uint32_t)(0x8))
+#define IMXDPUV1_EXTDST5_STATICCONTROL_RESET_VALUE           0x100U
+#define IMXDPUV1_EXTDST5_STATICCONTROL_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_EXTDST5_STATICCONTROL_SHDEN_MASK            0x1U
+#define IMXDPUV1_EXTDST5_STATICCONTROL_SHDEN_SHIFT           0U
+#define IMXDPUV1_EXTDST5_STATICCONTROL_KICK_MODE_MASK        0x100U
+#define IMXDPUV1_EXTDST5_STATICCONTROL_KICK_MODE_SHIFT       8U
+/* Field Value: KICK_MODE__SOFTWARE, kick generation by KICK field only  */
+#define IMXDPUV1_EXTDST5_STATICCONTROL_KICK_MODE__SOFTWARE   0U
+/* Field Value: KICK_MODE__EXTERNAL, kick signal from external allowed  */
+#define IMXDPUV1_EXTDST5_STATICCONTROL_KICK_MODE__EXTERNAL   0x1U
+#define IMXDPUV1_EXTDST5_STATICCONTROL_PERFCOUNTMODE_MASK    0x1000U
+#define IMXDPUV1_EXTDST5_STATICCONTROL_PERFCOUNTMODE_SHIFT   12U
+
+/* Register: IMXDPUV1_extdst5_Control */
+#define IMXDPUV1_EXTDST5_CONTROL                             ((uint32_t)(0x600C))
+#define IMXDPUV1_EXTDST5_CONTROL_OFFSET                      ((uint32_t)(0xC))
+#define IMXDPUV1_EXTDST5_CONTROL_RESET_VALUE                 0U
+#define IMXDPUV1_EXTDST5_CONTROL_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_EXTDST5_CONTROL_GAMMAAPPLYENABLE_MASK       0x1U
+#define IMXDPUV1_EXTDST5_CONTROL_GAMMAAPPLYENABLE_SHIFT      0U
+
+/* Register: IMXDPUV1_extdst5_SoftwareKick */
+#define IMXDPUV1_EXTDST5_SOFTWAREKICK                        ((uint32_t)(0x6010))
+#define IMXDPUV1_EXTDST5_SOFTWAREKICK_OFFSET                 ((uint32_t)(0x10))
+#define IMXDPUV1_EXTDST5_SOFTWAREKICK_RESET_VALUE            0U
+#define IMXDPUV1_EXTDST5_SOFTWAREKICK_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_EXTDST5_SOFTWAREKICK_KICK_MASK              0x1U
+#define IMXDPUV1_EXTDST5_SOFTWAREKICK_KICK_SHIFT             0U
+
+/* Register: IMXDPUV1_extdst5_Status */
+#define IMXDPUV1_EXTDST5_STATUS                              ((uint32_t)(0x6014))
+#define IMXDPUV1_EXTDST5_STATUS_OFFSET                       ((uint32_t)(0x14))
+#define IMXDPUV1_EXTDST5_STATUS_RESET_VALUE                  0U
+#define IMXDPUV1_EXTDST5_STATUS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_EXTDST5_STATUS_CNT_ERR_STS_MASK             0x1U
+#define IMXDPUV1_EXTDST5_STATUS_CNT_ERR_STS_SHIFT            0U
+
+/* Register: IMXDPUV1_extdst5_ControlWord */
+#define IMXDPUV1_EXTDST5_CONTROLWORD                         ((uint32_t)(0x6018))
+#define IMXDPUV1_EXTDST5_CONTROLWORD_OFFSET                  ((uint32_t)(0x18))
+#define IMXDPUV1_EXTDST5_CONTROLWORD_RESET_VALUE             0U
+#define IMXDPUV1_EXTDST5_CONTROLWORD_RESET_MASK              0U
+#define IMXDPUV1_EXTDST5_CONTROLWORD_CW_VAL_MASK             0xFFFFFFFFU
+#define IMXDPUV1_EXTDST5_CONTROLWORD_CW_VAL_SHIFT            0U
+
+/* Register: IMXDPUV1_extdst5_CurPixelCnt */
+#define IMXDPUV1_EXTDST5_CURPIXELCNT                         ((uint32_t)(0x601C))
+#define IMXDPUV1_EXTDST5_CURPIXELCNT_OFFSET                  ((uint32_t)(0x1C))
+#define IMXDPUV1_EXTDST5_CURPIXELCNT_RESET_VALUE             0U
+#define IMXDPUV1_EXTDST5_CURPIXELCNT_RESET_MASK              0U
+#define IMXDPUV1_EXTDST5_CURPIXELCNT_C_XVAL_MASK             0xFFFFU
+#define IMXDPUV1_EXTDST5_CURPIXELCNT_C_XVAL_SHIFT            0U
+#define IMXDPUV1_EXTDST5_CURPIXELCNT_C_YVAL_MASK             0xFFFF0000U
+#define IMXDPUV1_EXTDST5_CURPIXELCNT_C_YVAL_SHIFT            16U
+
+/* Register: IMXDPUV1_extdst5_LastPixelCnt */
+#define IMXDPUV1_EXTDST5_LASTPIXELCNT                        ((uint32_t)(0x6020))
+#define IMXDPUV1_EXTDST5_LASTPIXELCNT_OFFSET                 ((uint32_t)(0x20))
+#define IMXDPUV1_EXTDST5_LASTPIXELCNT_RESET_VALUE            0U
+#define IMXDPUV1_EXTDST5_LASTPIXELCNT_RESET_MASK             0U
+#define IMXDPUV1_EXTDST5_LASTPIXELCNT_L_XVAL_MASK            0xFFFFU
+#define IMXDPUV1_EXTDST5_LASTPIXELCNT_L_XVAL_SHIFT           0U
+#define IMXDPUV1_EXTDST5_LASTPIXELCNT_L_YVAL_MASK            0xFFFF0000U
+#define IMXDPUV1_EXTDST5_LASTPIXELCNT_L_YVAL_SHIFT           16U
+
+/* Register: IMXDPUV1_extdst5_PerfCounter */
+#define IMXDPUV1_EXTDST5_PERFCOUNTER                         ((uint32_t)(0x6024))
+#define IMXDPUV1_EXTDST5_PERFCOUNTER_OFFSET                  ((uint32_t)(0x24))
+#define IMXDPUV1_EXTDST5_PERFCOUNTER_RESET_VALUE             0U
+#define IMXDPUV1_EXTDST5_PERFCOUNTER_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_EXTDST5_PERFCOUNTER_PERFRESULT_MASK         0xFFFFFFFFU
+#define IMXDPUV1_EXTDST5_PERFCOUNTER_PERFRESULT_SHIFT        0U
+
+/* Register: IMXDPUV1_fetchwarp2_LockUnlock */
+#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK                       ((uint32_t)(0x6400))
+#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_OFFSET                ((uint32_t)(0))
+#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_RESET_VALUE           0U
+#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_RESET_MASK            0U
+#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK_SHIFT      0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY  0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_fetchwarp2_LockStatus */
+#define IMXDPUV1_FETCHWARP2_LOCKSTATUS                       ((uint32_t)(0x6404))
+#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_OFFSET                ((uint32_t)(0x4))
+#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_RESET_VALUE           0U
+#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_LOCKSTATUS_MASK       0x1U
+#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_LOCKSTATUS_SHIFT      0U
+#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_PRIVILEGESTATUS_MASK  0x10U
+#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_FREEZESTATUS_MASK     0x100U
+#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_FREEZESTATUS_SHIFT    8U
+
+/* Register: IMXDPUV1_fetchwarp2_StaticControl */
+#define IMXDPUV1_FETCHWARP2_STATICCONTROL                    ((uint32_t)(0x6408))
+#define IMXDPUV1_FETCHWARP2_STATICCONTROL_OFFSET             ((uint32_t)(0x8))
+#define IMXDPUV1_FETCHWARP2_STATICCONTROL_RESET_VALUE        0xFF000000U
+#define IMXDPUV1_FETCHWARP2_STATICCONTROL_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDEN_MASK         0x1U
+#define IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDEN_SHIFT        0U
+#define IMXDPUV1_FETCHWARP2_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP2_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDLDREQSTICKY_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDLDREQSTICKY_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp2_BurstBufferManagement */
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT            ((uint32_t)(0x640C))
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_OFFSET     ((uint32_t)(0xC))
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U
+/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the
+ * Display Controller. Works also for Blit Engine with marginal performance
+ * impact.  */
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U
+/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit
+ * Engine.  */
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U
+
+/* Register: IMXDPUV1_fetchwarp2_BaseAddress0 */
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS0                     ((uint32_t)(0x6410))
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_OFFSET              ((uint32_t)(0x10))
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_BASEADDRESS0_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_BASEADDRESS0_SHIFT  0U
+
+/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes0 */
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0          ((uint32_t)(0x6414))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_OFFSET   ((uint32_t)(0x14))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension0 */
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0           ((uint32_t)(0x6418))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_OFFSET    ((uint32_t)(0x18))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits0 */
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0              ((uint32_t)(0x641C))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_OFFSET       ((uint32_t)(0x1C))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_RESET_VALUE  0x8080808U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift0 */
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0             ((uint32_t)(0x6420))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_OFFSET      ((uint32_t)(0x20))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp2_LayerOffset0 */
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0                     ((uint32_t)(0x6424))
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_OFFSET              ((uint32_t)(0x24))
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_LAYERXOFFSET0_MASK  0x7FFFU
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_LAYERYOFFSET0_MASK  0x7FFF0000U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset0 */
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0                ((uint32_t)(0x6428))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_OFFSET         ((uint32_t)(0x28))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_RESET_VALUE    0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions0 */
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0            ((uint32_t)(0x642C))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_OFFSET     ((uint32_t)(0x2C))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ConstantColor0 */
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0                   ((uint32_t)(0x6430))
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_OFFSET            ((uint32_t)(0x30))
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_RESET_VALUE       0U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp2_LayerProperty0 */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0                   ((uint32_t)(0x6434))
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_OFFSET            ((uint32_t)(0x34))
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RESET_VALUE       0x80000100U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0_MASK    0x30U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0_SHIFT   4U
+/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U
+/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U
+/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp2_BaseAddress1 */
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS1                     ((uint32_t)(0x6438))
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_OFFSET              ((uint32_t)(0x38))
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_BASEADDRESS1_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_BASEADDRESS1_SHIFT  0U
+
+/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes1 */
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1          ((uint32_t)(0x643C))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_OFFSET   ((uint32_t)(0x3C))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_STRIDE1_MASK 0xFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_STRIDE1_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_MASK 0x3F0000U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension1 */
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1           ((uint32_t)(0x6440))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_OFFSET    ((uint32_t)(0x40))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_LINEWIDTH1_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_LINEWIDTH1_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_LINECOUNT1_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_LINECOUNT1_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits1 */
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1              ((uint32_t)(0x6444))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_OFFSET       ((uint32_t)(0x44))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_RESET_VALUE  0x8080808U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_MASK 0xFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_MASK 0xF00U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_MASK 0xF0000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSRED1_MASK 0xF000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSRED1_SHIFT 24U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_ITUFORMAT1_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_ITUFORMAT1_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift1 */
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1             ((uint32_t)(0x6448))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_OFFSET      ((uint32_t)(0x48))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_MASK 0x1FU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_MASK 0x1F0000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_MASK 0x1F000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp2_LayerOffset1 */
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1                     ((uint32_t)(0x644C))
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_OFFSET              ((uint32_t)(0x4C))
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_LAYERXOFFSET1_MASK  0x7FFFU
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_LAYERXOFFSET1_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_LAYERYOFFSET1_MASK  0x7FFF0000U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_LAYERYOFFSET1_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset1 */
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1                ((uint32_t)(0x6450))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_OFFSET         ((uint32_t)(0x50))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_RESET_VALUE    0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_MASK 0x7FFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions1 */
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1            ((uint32_t)(0x6454))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_OFFSET     ((uint32_t)(0x54))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_RESET_VALUE 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ConstantColor1 */
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1                   ((uint32_t)(0x6458))
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_OFFSET            ((uint32_t)(0x58))
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_RESET_VALUE       0U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTALPHA1_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTALPHA1_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTBLUE1_MASK 0xFF00U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTBLUE1_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTGREEN1_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTGREEN1_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTRED1_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTRED1_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp2_LayerProperty1 */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1                   ((uint32_t)(0x645C))
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_OFFSET            ((uint32_t)(0x5C))
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RESET_VALUE       0x100U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1_MASK    0x30U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1_SHIFT   4U
+/* Field Value: TILEMODE1__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE1__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE1__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1__TILE_PAD 0x2U
+/* Field Value: TILEMODE1__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHASRCENABLE1_MASK 0x100U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHASRCENABLE1_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHACONSTENABLE1_MASK 0x200U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHACONSTENABLE1_SHIFT 9U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHAMASKENABLE1_MASK 0x400U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHAMASKENABLE1_SHIFT 10U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHATRANSENABLE1_MASK 0x800U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHATRANSENABLE1_SHIFT 11U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHASRCENABLE1_MASK 0x1000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHASRCENABLE1_SHIFT 12U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHACONSTENABLE1_MASK 0x2000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHACONSTENABLE1_SHIFT 13U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHAMASKENABLE1_MASK 0x4000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHAMASKENABLE1_SHIFT 14U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHATRANSENABLE1_MASK 0x8000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHATRANSENABLE1_SHIFT 15U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_PREMULCONSTRGB1_MASK 0x10000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_PREMULCONSTRGB1_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1_MASK 0x60000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE1__OFF, No conversion.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1__OFF 0U
+/* Field Value: YUVCONVERSIONMODE1__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE1__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE1__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU709 0x3U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_GAMMAREMOVEENABLE1_MASK 0x100000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_GAMMAREMOVEENABLE1_SHIFT 20U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_CLIPWINDOWENABLE1_MASK 0x40000000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_CLIPWINDOWENABLE1_SHIFT 30U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_SOURCEBUFFERENABLE1_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_SOURCEBUFFERENABLE1_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp2_BaseAddress2 */
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS2                     ((uint32_t)(0x6460))
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_OFFSET              ((uint32_t)(0x60))
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_BASEADDRESS2_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_BASEADDRESS2_SHIFT  0U
+
+/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes2 */
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2          ((uint32_t)(0x6464))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_OFFSET   ((uint32_t)(0x64))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_STRIDE2_MASK 0xFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_STRIDE2_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_MASK 0x3F0000U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension2 */
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2           ((uint32_t)(0x6468))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_OFFSET    ((uint32_t)(0x68))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_LINEWIDTH2_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_LINEWIDTH2_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_LINECOUNT2_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_LINECOUNT2_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits2 */
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2              ((uint32_t)(0x646C))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_OFFSET       ((uint32_t)(0x6C))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_RESET_VALUE  0x8080808U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_MASK 0xFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_MASK 0xF00U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_MASK 0xF0000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSRED2_MASK 0xF000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSRED2_SHIFT 24U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_ITUFORMAT2_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_ITUFORMAT2_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift2 */
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2             ((uint32_t)(0x6470))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_OFFSET      ((uint32_t)(0x70))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_MASK 0x1FU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_MASK 0x1F0000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_MASK 0x1F000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp2_LayerOffset2 */
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2                     ((uint32_t)(0x6474))
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_OFFSET              ((uint32_t)(0x74))
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_LAYERXOFFSET2_MASK  0x7FFFU
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_LAYERXOFFSET2_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_LAYERYOFFSET2_MASK  0x7FFF0000U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_LAYERYOFFSET2_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset2 */
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2                ((uint32_t)(0x6478))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_OFFSET         ((uint32_t)(0x78))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_RESET_VALUE    0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_MASK 0x7FFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions2 */
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2            ((uint32_t)(0x647C))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_OFFSET     ((uint32_t)(0x7C))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_RESET_VALUE 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ConstantColor2 */
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2                   ((uint32_t)(0x6480))
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_OFFSET            ((uint32_t)(0x80))
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_RESET_VALUE       0U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTALPHA2_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTALPHA2_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTBLUE2_MASK 0xFF00U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTBLUE2_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTGREEN2_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTGREEN2_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTRED2_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTRED2_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp2_LayerProperty2 */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2                   ((uint32_t)(0x6484))
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_OFFSET            ((uint32_t)(0x84))
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RESET_VALUE       0x100U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2_MASK    0x30U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2_SHIFT   4U
+/* Field Value: TILEMODE2__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE2__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE2__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2__TILE_PAD 0x2U
+/* Field Value: TILEMODE2__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHASRCENABLE2_MASK 0x100U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHASRCENABLE2_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHACONSTENABLE2_MASK 0x200U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHACONSTENABLE2_SHIFT 9U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHAMASKENABLE2_MASK 0x400U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHAMASKENABLE2_SHIFT 10U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHATRANSENABLE2_MASK 0x800U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHATRANSENABLE2_SHIFT 11U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHASRCENABLE2_MASK 0x1000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHASRCENABLE2_SHIFT 12U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHACONSTENABLE2_MASK 0x2000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHACONSTENABLE2_SHIFT 13U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHAMASKENABLE2_MASK 0x4000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHAMASKENABLE2_SHIFT 14U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHATRANSENABLE2_MASK 0x8000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHATRANSENABLE2_SHIFT 15U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_PREMULCONSTRGB2_MASK 0x10000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_PREMULCONSTRGB2_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2_MASK 0x60000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE2__OFF, No conversion.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2__OFF 0U
+/* Field Value: YUVCONVERSIONMODE2__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE2__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE2__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU709 0x3U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_GAMMAREMOVEENABLE2_MASK 0x100000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_GAMMAREMOVEENABLE2_SHIFT 20U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_CLIPWINDOWENABLE2_MASK 0x40000000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_CLIPWINDOWENABLE2_SHIFT 30U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_SOURCEBUFFERENABLE2_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_SOURCEBUFFERENABLE2_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp2_BaseAddress3 */
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS3                     ((uint32_t)(0x6488))
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_OFFSET              ((uint32_t)(0x88))
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_BASEADDRESS3_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_BASEADDRESS3_SHIFT  0U
+
+/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes3 */
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3          ((uint32_t)(0x648C))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_OFFSET   ((uint32_t)(0x8C))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_STRIDE3_MASK 0xFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_STRIDE3_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_MASK 0x3F0000U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension3 */
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3           ((uint32_t)(0x6490))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_OFFSET    ((uint32_t)(0x90))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_LINEWIDTH3_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_LINEWIDTH3_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_LINECOUNT3_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_LINECOUNT3_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits3 */
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3              ((uint32_t)(0x6494))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_OFFSET       ((uint32_t)(0x94))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_RESET_VALUE  0x8080808U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_MASK 0xFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_MASK 0xF00U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_MASK 0xF0000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSRED3_MASK 0xF000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSRED3_SHIFT 24U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_ITUFORMAT3_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_ITUFORMAT3_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift3 */
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3             ((uint32_t)(0x6498))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_OFFSET      ((uint32_t)(0x98))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_MASK 0x1FU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_MASK 0x1F0000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_MASK 0x1F000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp2_LayerOffset3 */
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3                     ((uint32_t)(0x649C))
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_OFFSET              ((uint32_t)(0x9C))
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_LAYERXOFFSET3_MASK  0x7FFFU
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_LAYERXOFFSET3_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_LAYERYOFFSET3_MASK  0x7FFF0000U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_LAYERYOFFSET3_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset3 */
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3                ((uint32_t)(0x64A0))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_OFFSET         ((uint32_t)(0xA0))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_RESET_VALUE    0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_MASK 0x7FFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions3 */
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3            ((uint32_t)(0x64A4))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_OFFSET     ((uint32_t)(0xA4))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_RESET_VALUE 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ConstantColor3 */
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3                   ((uint32_t)(0x64A8))
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_OFFSET            ((uint32_t)(0xA8))
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_RESET_VALUE       0U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTALPHA3_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTALPHA3_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTBLUE3_MASK 0xFF00U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTBLUE3_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTGREEN3_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTGREEN3_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTRED3_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTRED3_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp2_LayerProperty3 */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3                   ((uint32_t)(0x64AC))
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_OFFSET            ((uint32_t)(0xAC))
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RESET_VALUE       0x100U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3_MASK    0x30U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3_SHIFT   4U
+/* Field Value: TILEMODE3__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE3__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE3__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3__TILE_PAD 0x2U
+/* Field Value: TILEMODE3__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHASRCENABLE3_MASK 0x100U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHASRCENABLE3_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHACONSTENABLE3_MASK 0x200U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHACONSTENABLE3_SHIFT 9U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHAMASKENABLE3_MASK 0x400U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHAMASKENABLE3_SHIFT 10U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHATRANSENABLE3_MASK 0x800U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHATRANSENABLE3_SHIFT 11U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHASRCENABLE3_MASK 0x1000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHASRCENABLE3_SHIFT 12U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHACONSTENABLE3_MASK 0x2000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHACONSTENABLE3_SHIFT 13U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHAMASKENABLE3_MASK 0x4000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHAMASKENABLE3_SHIFT 14U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHATRANSENABLE3_MASK 0x8000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHATRANSENABLE3_SHIFT 15U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_PREMULCONSTRGB3_MASK 0x10000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_PREMULCONSTRGB3_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3_MASK 0x60000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE3__OFF, No conversion.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3__OFF 0U
+/* Field Value: YUVCONVERSIONMODE3__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE3__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE3__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU709 0x3U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_GAMMAREMOVEENABLE3_MASK 0x100000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_GAMMAREMOVEENABLE3_SHIFT 20U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_CLIPWINDOWENABLE3_MASK 0x40000000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_CLIPWINDOWENABLE3_SHIFT 30U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_SOURCEBUFFERENABLE3_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_SOURCEBUFFERENABLE3_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp2_BaseAddress4 */
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS4                     ((uint32_t)(0x64B0))
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_OFFSET              ((uint32_t)(0xB0))
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_BASEADDRESS4_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_BASEADDRESS4_SHIFT  0U
+
+/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes4 */
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4          ((uint32_t)(0x64B4))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_OFFSET   ((uint32_t)(0xB4))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_STRIDE4_MASK 0xFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_STRIDE4_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_MASK 0x3F0000U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension4 */
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4           ((uint32_t)(0x64B8))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_OFFSET    ((uint32_t)(0xB8))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_LINEWIDTH4_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_LINEWIDTH4_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_LINECOUNT4_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_LINECOUNT4_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits4 */
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4              ((uint32_t)(0x64BC))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_OFFSET       ((uint32_t)(0xBC))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_RESET_VALUE  0x8080808U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_MASK 0xFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_MASK 0xF00U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_MASK 0xF0000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSRED4_MASK 0xF000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSRED4_SHIFT 24U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_ITUFORMAT4_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_ITUFORMAT4_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift4 */
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4             ((uint32_t)(0x64C0))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_OFFSET      ((uint32_t)(0xC0))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_MASK 0x1FU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_MASK 0x1F0000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_MASK 0x1F000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp2_LayerOffset4 */
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4                     ((uint32_t)(0x64C4))
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_OFFSET              ((uint32_t)(0xC4))
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_LAYERXOFFSET4_MASK  0x7FFFU
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_LAYERXOFFSET4_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_LAYERYOFFSET4_MASK  0x7FFF0000U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_LAYERYOFFSET4_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset4 */
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4                ((uint32_t)(0x64C8))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_OFFSET         ((uint32_t)(0xC8))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_RESET_VALUE    0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_MASK 0x7FFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions4 */
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4            ((uint32_t)(0x64CC))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_OFFSET     ((uint32_t)(0xCC))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_RESET_VALUE 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ConstantColor4 */
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4                   ((uint32_t)(0x64D0))
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_OFFSET            ((uint32_t)(0xD0))
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_RESET_VALUE       0U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTALPHA4_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTALPHA4_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTBLUE4_MASK 0xFF00U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTBLUE4_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTGREEN4_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTGREEN4_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTRED4_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTRED4_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp2_LayerProperty4 */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4                   ((uint32_t)(0x64D4))
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_OFFSET            ((uint32_t)(0xD4))
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RESET_VALUE       0x100U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4_MASK    0x30U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4_SHIFT   4U
+/* Field Value: TILEMODE4__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE4__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE4__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4__TILE_PAD 0x2U
+/* Field Value: TILEMODE4__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHASRCENABLE4_MASK 0x100U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHASRCENABLE4_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHACONSTENABLE4_MASK 0x200U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHACONSTENABLE4_SHIFT 9U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHAMASKENABLE4_MASK 0x400U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHAMASKENABLE4_SHIFT 10U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHATRANSENABLE4_MASK 0x800U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHATRANSENABLE4_SHIFT 11U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHASRCENABLE4_MASK 0x1000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHASRCENABLE4_SHIFT 12U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHACONSTENABLE4_MASK 0x2000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHACONSTENABLE4_SHIFT 13U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHAMASKENABLE4_MASK 0x4000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHAMASKENABLE4_SHIFT 14U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHATRANSENABLE4_MASK 0x8000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHATRANSENABLE4_SHIFT 15U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_PREMULCONSTRGB4_MASK 0x10000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_PREMULCONSTRGB4_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4_MASK 0x60000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE4__OFF, No conversion.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4__OFF 0U
+/* Field Value: YUVCONVERSIONMODE4__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE4__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE4__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU709 0x3U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_GAMMAREMOVEENABLE4_MASK 0x100000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_GAMMAREMOVEENABLE4_SHIFT 20U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_CLIPWINDOWENABLE4_MASK 0x40000000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_CLIPWINDOWENABLE4_SHIFT 30U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_SOURCEBUFFERENABLE4_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_SOURCEBUFFERENABLE4_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp2_BaseAddress5 */
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS5                     ((uint32_t)(0x64D8))
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_OFFSET              ((uint32_t)(0xD8))
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_BASEADDRESS5_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_BASEADDRESS5_SHIFT  0U
+
+/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes5 */
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5          ((uint32_t)(0x64DC))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_OFFSET   ((uint32_t)(0xDC))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_STRIDE5_MASK 0xFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_STRIDE5_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_MASK 0x3F0000U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension5 */
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5           ((uint32_t)(0x64E0))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_OFFSET    ((uint32_t)(0xE0))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_LINEWIDTH5_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_LINEWIDTH5_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_LINECOUNT5_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_LINECOUNT5_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits5 */
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5              ((uint32_t)(0x64E4))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_OFFSET       ((uint32_t)(0xE4))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_RESET_VALUE  0x8080808U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_MASK 0xFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_MASK 0xF00U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_MASK 0xF0000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSRED5_MASK 0xF000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSRED5_SHIFT 24U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_ITUFORMAT5_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_ITUFORMAT5_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift5 */
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5             ((uint32_t)(0x64E8))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_OFFSET      ((uint32_t)(0xE8))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_MASK 0x1FU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_MASK 0x1F0000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_MASK 0x1F000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp2_LayerOffset5 */
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5                     ((uint32_t)(0x64EC))
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_OFFSET              ((uint32_t)(0xEC))
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_LAYERXOFFSET5_MASK  0x7FFFU
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_LAYERXOFFSET5_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_LAYERYOFFSET5_MASK  0x7FFF0000U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_LAYERYOFFSET5_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset5 */
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5                ((uint32_t)(0x64F0))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_OFFSET         ((uint32_t)(0xF0))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_RESET_VALUE    0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_MASK 0x7FFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions5 */
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5            ((uint32_t)(0x64F4))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_OFFSET     ((uint32_t)(0xF4))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_RESET_VALUE 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ConstantColor5 */
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5                   ((uint32_t)(0x64F8))
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_OFFSET            ((uint32_t)(0xF8))
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_RESET_VALUE       0U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTALPHA5_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTALPHA5_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTBLUE5_MASK 0xFF00U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTBLUE5_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTGREEN5_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTGREEN5_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTRED5_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTRED5_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp2_LayerProperty5 */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5                   ((uint32_t)(0x64FC))
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_OFFSET            ((uint32_t)(0xFC))
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RESET_VALUE       0x100U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5_MASK    0x30U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5_SHIFT   4U
+/* Field Value: TILEMODE5__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE5__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE5__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5__TILE_PAD 0x2U
+/* Field Value: TILEMODE5__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHASRCENABLE5_MASK 0x100U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHASRCENABLE5_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHACONSTENABLE5_MASK 0x200U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHACONSTENABLE5_SHIFT 9U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHAMASKENABLE5_MASK 0x400U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHAMASKENABLE5_SHIFT 10U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHATRANSENABLE5_MASK 0x800U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHATRANSENABLE5_SHIFT 11U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHASRCENABLE5_MASK 0x1000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHASRCENABLE5_SHIFT 12U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHACONSTENABLE5_MASK 0x2000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHACONSTENABLE5_SHIFT 13U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHAMASKENABLE5_MASK 0x4000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHAMASKENABLE5_SHIFT 14U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHATRANSENABLE5_MASK 0x8000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHATRANSENABLE5_SHIFT 15U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_PREMULCONSTRGB5_MASK 0x10000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_PREMULCONSTRGB5_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5_MASK 0x60000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE5__OFF, No conversion.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5__OFF 0U
+/* Field Value: YUVCONVERSIONMODE5__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE5__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE5__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU709 0x3U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_GAMMAREMOVEENABLE5_MASK 0x100000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_GAMMAREMOVEENABLE5_SHIFT 20U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_CLIPWINDOWENABLE5_MASK 0x40000000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_CLIPWINDOWENABLE5_SHIFT 30U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_SOURCEBUFFERENABLE5_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_SOURCEBUFFERENABLE5_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp2_BaseAddress6 */
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS6                     ((uint32_t)(0x6500))
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_OFFSET              ((uint32_t)(0x100))
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_BASEADDRESS6_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_BASEADDRESS6_SHIFT  0U
+
+/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes6 */
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6          ((uint32_t)(0x6504))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_OFFSET   ((uint32_t)(0x104))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_STRIDE6_MASK 0xFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_STRIDE6_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_MASK 0x3F0000U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension6 */
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6           ((uint32_t)(0x6508))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_OFFSET    ((uint32_t)(0x108))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_LINEWIDTH6_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_LINEWIDTH6_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_LINECOUNT6_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_LINECOUNT6_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits6 */
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6              ((uint32_t)(0x650C))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_OFFSET       ((uint32_t)(0x10C))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_RESET_VALUE  0x8080808U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_MASK 0xFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_MASK 0xF00U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_MASK 0xF0000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSRED6_MASK 0xF000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSRED6_SHIFT 24U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_ITUFORMAT6_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_ITUFORMAT6_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift6 */
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6             ((uint32_t)(0x6510))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_OFFSET      ((uint32_t)(0x110))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_MASK 0x1FU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_MASK 0x1F0000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_MASK 0x1F000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp2_LayerOffset6 */
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6                     ((uint32_t)(0x6514))
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_OFFSET              ((uint32_t)(0x114))
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_LAYERXOFFSET6_MASK  0x7FFFU
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_LAYERXOFFSET6_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_LAYERYOFFSET6_MASK  0x7FFF0000U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_LAYERYOFFSET6_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset6 */
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6                ((uint32_t)(0x6518))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_OFFSET         ((uint32_t)(0x118))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_RESET_VALUE    0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_MASK 0x7FFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions6 */
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6            ((uint32_t)(0x651C))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_OFFSET     ((uint32_t)(0x11C))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_RESET_VALUE 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ConstantColor6 */
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6                   ((uint32_t)(0x6520))
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_OFFSET            ((uint32_t)(0x120))
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_RESET_VALUE       0U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTALPHA6_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTALPHA6_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTBLUE6_MASK 0xFF00U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTBLUE6_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTGREEN6_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTGREEN6_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTRED6_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTRED6_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp2_LayerProperty6 */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6                   ((uint32_t)(0x6524))
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_OFFSET            ((uint32_t)(0x124))
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RESET_VALUE       0x100U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6_MASK    0x30U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6_SHIFT   4U
+/* Field Value: TILEMODE6__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE6__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE6__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6__TILE_PAD 0x2U
+/* Field Value: TILEMODE6__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHASRCENABLE6_MASK 0x100U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHASRCENABLE6_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHACONSTENABLE6_MASK 0x200U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHACONSTENABLE6_SHIFT 9U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHAMASKENABLE6_MASK 0x400U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHAMASKENABLE6_SHIFT 10U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHATRANSENABLE6_MASK 0x800U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHATRANSENABLE6_SHIFT 11U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHASRCENABLE6_MASK 0x1000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHASRCENABLE6_SHIFT 12U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHACONSTENABLE6_MASK 0x2000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHACONSTENABLE6_SHIFT 13U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHAMASKENABLE6_MASK 0x4000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHAMASKENABLE6_SHIFT 14U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHATRANSENABLE6_MASK 0x8000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHATRANSENABLE6_SHIFT 15U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_PREMULCONSTRGB6_MASK 0x10000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_PREMULCONSTRGB6_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6_MASK 0x60000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE6__OFF, No conversion.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6__OFF 0U
+/* Field Value: YUVCONVERSIONMODE6__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE6__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE6__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU709 0x3U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_GAMMAREMOVEENABLE6_MASK 0x100000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_GAMMAREMOVEENABLE6_SHIFT 20U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_CLIPWINDOWENABLE6_MASK 0x40000000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_CLIPWINDOWENABLE6_SHIFT 30U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_SOURCEBUFFERENABLE6_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_SOURCEBUFFERENABLE6_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp2_BaseAddress7 */
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS7                     ((uint32_t)(0x6528))
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_OFFSET              ((uint32_t)(0x128))
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_BASEADDRESS7_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_BASEADDRESS7_SHIFT  0U
+
+/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes7 */
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7          ((uint32_t)(0x652C))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_OFFSET   ((uint32_t)(0x12C))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_STRIDE7_MASK 0xFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_STRIDE7_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_MASK 0x3F0000U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension7 */
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7           ((uint32_t)(0x6530))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_OFFSET    ((uint32_t)(0x130))
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_LINEWIDTH7_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_LINEWIDTH7_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_LINECOUNT7_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_LINECOUNT7_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits7 */
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7              ((uint32_t)(0x6534))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_OFFSET       ((uint32_t)(0x134))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_RESET_VALUE  0x8080808U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_MASK 0xFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_MASK 0xF00U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_MASK 0xF0000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSRED7_MASK 0xF000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSRED7_SHIFT 24U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_ITUFORMAT7_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_ITUFORMAT7_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift7 */
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7             ((uint32_t)(0x6538))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_OFFSET      ((uint32_t)(0x138))
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_MASK 0x1FU
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_MASK 0x1F0000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_MASK 0x1F000000U
+#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp2_LayerOffset7 */
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7                     ((uint32_t)(0x653C))
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_OFFSET              ((uint32_t)(0x13C))
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_LAYERXOFFSET7_MASK  0x7FFFU
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_LAYERXOFFSET7_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_LAYERYOFFSET7_MASK  0x7FFF0000U
+#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_LAYERYOFFSET7_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset7 */
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7                ((uint32_t)(0x6540))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_OFFSET         ((uint32_t)(0x140))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_RESET_VALUE    0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_MASK 0x7FFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions7 */
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7            ((uint32_t)(0x6544))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_OFFSET     ((uint32_t)(0x144))
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_RESET_VALUE 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_MASK 0x3FFFU
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchwarp2_ConstantColor7 */
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7                   ((uint32_t)(0x6548))
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_OFFSET            ((uint32_t)(0x148))
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_RESET_VALUE       0U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTALPHA7_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTALPHA7_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTBLUE7_MASK 0xFF00U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTBLUE7_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTGREEN7_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTGREEN7_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTRED7_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTRED7_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp2_LayerProperty7 */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7                   ((uint32_t)(0x654C))
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_OFFSET            ((uint32_t)(0x14C))
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RESET_VALUE       0x100U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7_MASK    0x30U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7_SHIFT   4U
+/* Field Value: TILEMODE7__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE7__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE7__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7__TILE_PAD 0x2U
+/* Field Value: TILEMODE7__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHASRCENABLE7_MASK 0x100U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHASRCENABLE7_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHACONSTENABLE7_MASK 0x200U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHACONSTENABLE7_SHIFT 9U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHAMASKENABLE7_MASK 0x400U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHAMASKENABLE7_SHIFT 10U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHATRANSENABLE7_MASK 0x800U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHATRANSENABLE7_SHIFT 11U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHASRCENABLE7_MASK 0x1000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHASRCENABLE7_SHIFT 12U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHACONSTENABLE7_MASK 0x2000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHACONSTENABLE7_SHIFT 13U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHAMASKENABLE7_MASK 0x4000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHAMASKENABLE7_SHIFT 14U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHATRANSENABLE7_MASK 0x8000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHATRANSENABLE7_SHIFT 15U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_PREMULCONSTRGB7_MASK 0x10000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_PREMULCONSTRGB7_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7_MASK 0x60000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE7__OFF, No conversion.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7__OFF 0U
+/* Field Value: YUVCONVERSIONMODE7__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE7__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE7__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU709 0x3U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_GAMMAREMOVEENABLE7_MASK 0x100000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_GAMMAREMOVEENABLE7_SHIFT 20U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_CLIPWINDOWENABLE7_MASK 0x40000000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_CLIPWINDOWENABLE7_SHIFT 30U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_SOURCEBUFFERENABLE7_MASK 0x80000000U
+#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_SOURCEBUFFERENABLE7_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp2_FrameDimensions */
+#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS                  ((uint32_t)(0x6550))
+#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_OFFSET           ((uint32_t)(0x150))
+#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_RESET_VALUE      0xEF013FU
+#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_FRAMEWIDTH_MASK  0x3FFFU
+#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_EMPTYFRAME_MASK  0x80000000U
+#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchwarp2_FrameResampling */
+#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING                  ((uint32_t)(0x6554))
+#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_OFFSET           ((uint32_t)(0x154))
+#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_RESET_VALUE      0x104000U
+#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_STARTX_MASK      0x3FU
+#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_STARTX_SHIFT     0U
+#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_STARTY_MASK      0xFC0U
+#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_STARTY_SHIFT     6U
+#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_DELTAX_MASK      0x3F000U
+#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_DELTAX_SHIFT     12U
+#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_DELTAY_MASK      0xFC0000U
+#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_DELTAY_SHIFT     18U
+#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U
+#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp2_WarpControl */
+#define IMXDPUV1_FETCHWARP2_WARPCONTROL                      ((uint32_t)(0x6558))
+#define IMXDPUV1_FETCHWARP2_WARPCONTROL_OFFSET               ((uint32_t)(0x158))
+#define IMXDPUV1_FETCHWARP2_WARPCONTROL_RESET_VALUE          0x20U
+#define IMXDPUV1_FETCHWARP2_WARPCONTROL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPBITSPERPIXEL_MASK 0x3FU
+#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPBITSPERPIXEL_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE_MASK 0x300U
+#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE_SHIFT 8U
+/* Field Value: WARPCOORDINATEMODE__PNT, x and y (sample points).  */
+#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE__PNT 0U
+/* Field Value: WARPCOORDINATEMODE__D_PNT, dx and dy (vectors between adjacent
+ * sample points).  */
+#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE__D_PNT 0x1U
+/* Field Value: WARPCOORDINATEMODE__DD_PNT, ddx and ddy (deltas between adjacent
+ * vectors).  */
+#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE__DD_PNT 0x2U
+#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPSYMMETRICOFFSET_MASK 0x1000U
+#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPSYMMETRICOFFSET_SHIFT 12U
+
+/* Register: IMXDPUV1_fetchwarp2_ArbStartX */
+#define IMXDPUV1_FETCHWARP2_ARBSTARTX                        ((uint32_t)(0x655C))
+#define IMXDPUV1_FETCHWARP2_ARBSTARTX_OFFSET                 ((uint32_t)(0x15C))
+#define IMXDPUV1_FETCHWARP2_ARBSTARTX_RESET_VALUE            0U
+#define IMXDPUV1_FETCHWARP2_ARBSTARTX_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_ARBSTARTX_ARBSTARTX_MASK         0x1FFFFFU
+#define IMXDPUV1_FETCHWARP2_ARBSTARTX_ARBSTARTX_SHIFT        0U
+
+/* Register: IMXDPUV1_fetchwarp2_ArbStartY */
+#define IMXDPUV1_FETCHWARP2_ARBSTARTY                        ((uint32_t)(0x6560))
+#define IMXDPUV1_FETCHWARP2_ARBSTARTY_OFFSET                 ((uint32_t)(0x160))
+#define IMXDPUV1_FETCHWARP2_ARBSTARTY_RESET_VALUE            0U
+#define IMXDPUV1_FETCHWARP2_ARBSTARTY_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_ARBSTARTY_ARBSTARTY_MASK         0x1FFFFFU
+#define IMXDPUV1_FETCHWARP2_ARBSTARTY_ARBSTARTY_SHIFT        0U
+
+/* Register: IMXDPUV1_fetchwarp2_ArbDelta */
+#define IMXDPUV1_FETCHWARP2_ARBDELTA                         ((uint32_t)(0x6564))
+#define IMXDPUV1_FETCHWARP2_ARBDELTA_OFFSET                  ((uint32_t)(0x164))
+#define IMXDPUV1_FETCHWARP2_ARBDELTA_RESET_VALUE             0U
+#define IMXDPUV1_FETCHWARP2_ARBDELTA_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAXX_MASK         0xFFU
+#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAXX_SHIFT        0U
+#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAXY_MASK         0xFF00U
+#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAXY_SHIFT        8U
+#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAYX_MASK         0xFF0000U
+#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAYX_SHIFT        16U
+#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAYY_MASK         0xFF000000U
+#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAYY_SHIFT        24U
+
+/* Register: IMXDPUV1_fetchwarp2_FIRPositions */
+#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS                     ((uint32_t)(0x6568))
+#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_OFFSET              ((uint32_t)(0x168))
+#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_RESET_VALUE         0xA965U
+#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR0POSITION_MASK   0xFU
+#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR0POSITION_SHIFT  0U
+#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR1POSITION_MASK   0xF0U
+#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR1POSITION_SHIFT  4U
+#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR2POSITION_MASK   0xF00U
+#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR2POSITION_SHIFT  8U
+#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR3POSITION_MASK   0xF000U
+#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR3POSITION_SHIFT  12U
+
+/* Register: IMXDPUV1_fetchwarp2_FIRCoefficients */
+#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS                  ((uint32_t)(0x656C))
+#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_OFFSET           ((uint32_t)(0x16C))
+#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_RESET_VALUE      0x20U
+#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR0COEFFICIENT_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR0COEFFICIENT_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR1COEFFICIENT_MASK 0xFF00U
+#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR1COEFFICIENT_SHIFT 8U
+#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR2COEFFICIENT_MASK 0xFF0000U
+#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR2COEFFICIENT_SHIFT 16U
+#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR3COEFFICIENT_MASK 0xFF000000U
+#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR3COEFFICIENT_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchwarp2_Control */
+#define IMXDPUV1_FETCHWARP2_CONTROL                          ((uint32_t)(0x6570))
+#define IMXDPUV1_FETCHWARP2_CONTROL_OFFSET                   ((uint32_t)(0x170))
+#define IMXDPUV1_FETCHWARP2_CONTROL_RESET_VALUE              0x10000U
+#define IMXDPUV1_FETCHWARP2_CONTROL_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE_MASK          0x7U
+#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE_SHIFT         0U
+/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin.
+ * Hor/ver increments using DeltaX/Y and DeltaSwap setup.  */
+#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__NORMAL       0U
+/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source
+ * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver
+ * increments = (1,0)/(0,1).  */
+#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__DECODE       0x1U
+/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary
+ * warping (filter is active). Coordinates are read from frame input
+ * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY
+ * must be setup.  */
+#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__ARBITRARY    0x2U
+/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective
+ * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver
+ * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates.  */
+#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__PERSPECTIVE  0x3U
+/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer
+ * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments
+ * = (1,0)/(0,1). All corellated window widths and horizontal offsets must
+ * be even.  */
+#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__YUV422       0x4U
+/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter
+ * is active). First sample at AffineStartX/Y. Hor/ver increments using
+ * AffineDeltaXX/XY/YX/YY. Cartesian coordinates.  */
+#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__AFFINE       0x5U
+#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT_MASK         0x18U
+#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT_SHIFT        3U
+/* Field Value: INPUTSELECT__INACTIVE, Not used.  */
+#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT__INACTIVE    0U
+/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV
+ * or source alpha buffer).  */
+#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT__COMPPACK    0x1U
+/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply
+ * stage (mask alpha buffer).  */
+#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT__ALPHAMASK   0x2U
+/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate
+ * buffer).  */
+#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT__COORDINATE  0x3U
+#define IMXDPUV1_FETCHWARP2_CONTROL_RAWPIXEL_MASK            0x80U
+#define IMXDPUV1_FETCHWARP2_CONTROL_RAWPIXEL_SHIFT           7U
+#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPCOLOR_MASK           0x10000U
+#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPCOLOR_SHIFT          16U
+/* Field Value: CLIPCOLOR__NULL, Null color.  */
+#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPCOLOR__NULL          0U
+/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer
+ * (or layer 0 when Fetch unit has one layer only). The color is then the
+ * layer's source or tiling color.  */
+#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPCOLOR__LAYER         0x1U
+#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPLAYER_MASK           0xE0000U
+#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPLAYER_SHIFT          17U
+#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE_MASK          0x700000U
+#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE_SHIFT         20U
+/* Field Value: FILTERMODE__NEAREST, Chooses pixel closest to sample point  */
+#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__NEAREST      0U
+/* Field Value: FILTERMODE__BILINEAR, Calculates result from 4 pixels closest
+ * to sample point  */
+#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__BILINEAR     0x1U
+/* Field Value: FILTERMODE__FIR2, FIR mode with 2 programmable pixel positions
+ * and coefficients  */
+#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__FIR2         0x2U
+/* Field Value: FILTERMODE__FIR4, FIR mode with 4 programmable pixel positions
+ * and coefficients  */
+#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__FIR4         0x3U
+/* Field Value: FILTERMODE__HOR_LINEAR, Calculates result from 2 pixels closest
+ * to the sample point and on the same line  */
+#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__HOR_LINEAR   0x4U
+
+/* Register: IMXDPUV1_fetchwarp2_TriggerEnable */
+#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE                    ((uint32_t)(0x6574))
+#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_OFFSET             ((uint32_t)(0x174))
+#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_RESET_VALUE        0U
+#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_SHDLDREQ_MASK      0xFFU
+#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_SHDLDREQ_SHIFT     0U
+
+/* Register: IMXDPUV1_fetchwarp2_ControlTrigger */
+#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER                   ((uint32_t)(0x6578))
+#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_OFFSET            ((uint32_t)(0x178))
+#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_RESET_VALUE       0U
+#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_RESET_MASK        0xFFFFFFFEU
+#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_SHDTOKGEN_MASK    0x1U
+#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_SHDTOKGEN_SHIFT   0U
+
+/* Register: IMXDPUV1_fetchwarp2_Start */
+#define IMXDPUV1_FETCHWARP2_START                            ((uint32_t)(0x657C))
+#define IMXDPUV1_FETCHWARP2_START_OFFSET                     ((uint32_t)(0x17C))
+#define IMXDPUV1_FETCHWARP2_START_RESET_VALUE                0U
+#define IMXDPUV1_FETCHWARP2_START_RESET_MASK                 0xFFFFFFFEU
+#define IMXDPUV1_FETCHWARP2_START_START_MASK                 0x1U
+#define IMXDPUV1_FETCHWARP2_START_START_SHIFT                0U
+
+/* Register: IMXDPUV1_fetchwarp2_FetchType */
+#define IMXDPUV1_FETCHWARP2_FETCHTYPE                        ((uint32_t)(0x6580))
+#define IMXDPUV1_FETCHWARP2_FETCHTYPE_OFFSET                 ((uint32_t)(0x180))
+#define IMXDPUV1_FETCHWARP2_FETCHTYPE_RESET_VALUE            0U
+#define IMXDPUV1_FETCHWARP2_FETCHTYPE_RESET_MASK             0xFFFFFFF0U
+#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE_MASK         0xFU
+#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE_SHIFT        0U
+/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder.  */
+#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__DECODE      0U
+/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers).  */
+#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__LAYER       0x1U
+/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional
+ * plane (8 layers).  */
+#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__WARP        0x2U
+/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha,
+ * chroma and coordinate planes.  */
+#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__ECO         0x3U
+/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and
+ * arbitrary warping.  */
+#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__PERSP       0x4U
+/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping.  */
+#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__ROT         0x5U
+/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced
+ * feature set.  */
+#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__DECODEL     0x6U
+/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers),
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__LAYERL      0x7U
+/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping,
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__ROTL        0x8U
+
+/* Register: IMXDPUV1_fetchwarp2_BurstBufferProperties */
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES            ((uint32_t)(0x6584))
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_OFFSET     ((uint32_t)(0x184))
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_RESET_VALUE 0U
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U
+#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U
+
+/* Register: IMXDPUV1_fetchwarp2_Status */
+#define IMXDPUV1_FETCHWARP2_STATUS                           ((uint32_t)(0x6588))
+#define IMXDPUV1_FETCHWARP2_STATUS_OFFSET                    ((uint32_t)(0x188))
+#define IMXDPUV1_FETCHWARP2_STATUS_RESET_VALUE               0U
+#define IMXDPUV1_FETCHWARP2_STATUS_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FETCHWARP2_STATUS_WRITETIMEOUT_MASK         0x1U
+#define IMXDPUV1_FETCHWARP2_STATUS_WRITETIMEOUT_SHIFT        0U
+#define IMXDPUV1_FETCHWARP2_STATUS_READTIMEOUT_MASK          0x10U
+#define IMXDPUV1_FETCHWARP2_STATUS_READTIMEOUT_SHIFT         4U
+
+/* Register: IMXDPUV1_fetchwarp2_HiddenStatus */
+#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS                     ((uint32_t)(0x658C))
+#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_OFFSET              ((uint32_t)(0x18C))
+#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_RESET_VALUE         0U
+#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_RESET_MASK          0xFFFF008EU
+#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSBUSY_MASK     0x1U
+#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSBUSY_SHIFT    0U
+#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U
+#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U
+#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSREQUEST_MASK  0x20U
+#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U
+#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U
+#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U
+#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_SHADOWSTATUS_MASK   0xFF00U
+#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_SHADOWSTATUS_SHIFT  8U
+
+/* Register: IMXDPUV1_fetcheco2_LockUnlock */
+#define IMXDPUV1_FETCHECO2_LOCKUNLOCK                        ((uint32_t)(0x6800))
+#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_OFFSET                 ((uint32_t)(0))
+#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_RESET_VALUE            0U
+#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_RESET_MASK             0U
+#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK_SHIFT       0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY   0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_fetcheco2_LockStatus */
+#define IMXDPUV1_FETCHECO2_LOCKSTATUS                        ((uint32_t)(0x6804))
+#define IMXDPUV1_FETCHECO2_LOCKSTATUS_OFFSET                 ((uint32_t)(0x4))
+#define IMXDPUV1_FETCHECO2_LOCKSTATUS_RESET_VALUE            0U
+#define IMXDPUV1_FETCHECO2_LOCKSTATUS_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO2_LOCKSTATUS_LOCKSTATUS_MASK        0x1U
+#define IMXDPUV1_FETCHECO2_LOCKSTATUS_LOCKSTATUS_SHIFT       0U
+#define IMXDPUV1_FETCHECO2_LOCKSTATUS_PRIVILEGESTATUS_MASK   0x10U
+#define IMXDPUV1_FETCHECO2_LOCKSTATUS_PRIVILEGESTATUS_SHIFT  4U
+#define IMXDPUV1_FETCHECO2_LOCKSTATUS_FREEZESTATUS_MASK      0x100U
+#define IMXDPUV1_FETCHECO2_LOCKSTATUS_FREEZESTATUS_SHIFT     8U
+
+/* Register: IMXDPUV1_fetcheco2_StaticControl */
+#define IMXDPUV1_FETCHECO2_STATICCONTROL                     ((uint32_t)(0x6808))
+#define IMXDPUV1_FETCHECO2_STATICCONTROL_OFFSET              ((uint32_t)(0x8))
+#define IMXDPUV1_FETCHECO2_STATICCONTROL_RESET_VALUE         0U
+#define IMXDPUV1_FETCHECO2_STATICCONTROL_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO2_STATICCONTROL_SHDEN_MASK          0x1U
+#define IMXDPUV1_FETCHECO2_STATICCONTROL_SHDEN_SHIFT         0U
+#define IMXDPUV1_FETCHECO2_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U
+#define IMXDPUV1_FETCHECO2_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco2_BurstBufferManagement */
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT             ((uint32_t)(0x680C))
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_OFFSET      ((uint32_t)(0xC))
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U
+/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the
+ * Display Controller. Works also for Blit Engine with marginal performance
+ * impact.  */
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U
+/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit
+ * Engine.  */
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U
+
+/* Register: IMXDPUV1_fetcheco2_BaseAddress0 */
+#define IMXDPUV1_FETCHECO2_BASEADDRESS0                      ((uint32_t)(0x6810))
+#define IMXDPUV1_FETCHECO2_BASEADDRESS0_OFFSET               ((uint32_t)(0x10))
+#define IMXDPUV1_FETCHECO2_BASEADDRESS0_RESET_VALUE          0U
+#define IMXDPUV1_FETCHECO2_BASEADDRESS0_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO2_BASEADDRESS0_BASEADDRESS0_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO2_BASEADDRESS0_BASEADDRESS0_SHIFT   0U
+
+/* Register: IMXDPUV1_fetcheco2_SourceBufferAttributes0 */
+#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0           ((uint32_t)(0x6814))
+#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_OFFSET    ((uint32_t)(0x14))
+#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU
+#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU
+#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U
+#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U
+#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco2_SourceBufferDimension0 */
+#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0            ((uint32_t)(0x6818))
+#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_OFFSET     ((uint32_t)(0x18))
+#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco2_ColorComponentBits0 */
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0               ((uint32_t)(0x681C))
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_OFFSET        ((uint32_t)(0x1C))
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_RESET_VALUE   0x8080808U
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U
+
+/* Register: IMXDPUV1_fetcheco2_ColorComponentShift0 */
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0              ((uint32_t)(0x6820))
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_OFFSET       ((uint32_t)(0x20))
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_RESET_VALUE  0x18100800U
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U
+#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_fetcheco2_LayerOffset0 */
+#define IMXDPUV1_FETCHECO2_LAYEROFFSET0                      ((uint32_t)(0x6824))
+#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_OFFSET               ((uint32_t)(0x24))
+#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_RESET_VALUE          0U
+#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_LAYERXOFFSET0_MASK   0x7FFFU
+#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_LAYERXOFFSET0_SHIFT  0U
+#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_LAYERYOFFSET0_MASK   0x7FFF0000U
+#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_LAYERYOFFSET0_SHIFT  16U
+
+/* Register: IMXDPUV1_fetcheco2_ClipWindowOffset0 */
+#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0                 ((uint32_t)(0x6828))
+#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_OFFSET          ((uint32_t)(0x28))
+#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_RESET_VALUE     0U
+#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU
+#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U
+#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco2_ClipWindowDimensions0 */
+#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0             ((uint32_t)(0x682C))
+#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_OFFSET      ((uint32_t)(0x2C))
+#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U
+#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco2_ConstantColor0 */
+#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0                    ((uint32_t)(0x6830))
+#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_OFFSET             ((uint32_t)(0x30))
+#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_RESET_VALUE        0U
+#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU
+#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U
+#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U
+#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTRED0_MASK  0xFF000000U
+#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_fetcheco2_LayerProperty0 */
+#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0                    ((uint32_t)(0x6834))
+#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_OFFSET             ((uint32_t)(0x34))
+#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_RESET_VALUE        0x80000000U
+#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0_MASK     0x30U
+#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0_SHIFT    4U
+/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U
+/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U
+#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U
+#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U
+#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U
+
+/* Register: IMXDPUV1_fetcheco2_FrameDimensions */
+#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS                   ((uint32_t)(0x6838))
+#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_OFFSET            ((uint32_t)(0x38))
+#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_RESET_VALUE       0xEF013FU
+#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_FRAMEWIDTH_MASK   0x3FFFU
+#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT  0U
+#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK  0x3FFF0000U
+#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U
+#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_EMPTYFRAME_MASK   0x80000000U
+#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT  31U
+
+/* Register: IMXDPUV1_fetcheco2_FrameResampling */
+#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING                   ((uint32_t)(0x683C))
+#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_OFFSET            ((uint32_t)(0x3C))
+#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_RESET_VALUE       0x104000U
+#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_STARTX_MASK       0x3FU
+#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_STARTX_SHIFT      0U
+#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_STARTY_MASK       0xFC0U
+#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_STARTY_SHIFT      6U
+#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_DELTAX_MASK       0x3F000U
+#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_DELTAX_SHIFT      12U
+#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_DELTAY_MASK       0xFC0000U
+#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_DELTAY_SHIFT      18U
+#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U
+#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U
+
+/* Register: IMXDPUV1_fetcheco2_Control */
+#define IMXDPUV1_FETCHECO2_CONTROL                           ((uint32_t)(0x6840))
+#define IMXDPUV1_FETCHECO2_CONTROL_OFFSET                    ((uint32_t)(0x40))
+#define IMXDPUV1_FETCHECO2_CONTROL_RESET_VALUE               0x10000U
+#define IMXDPUV1_FETCHECO2_CONTROL_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO2_CONTROL_RAWPIXEL_MASK             0x80U
+#define IMXDPUV1_FETCHECO2_CONTROL_RAWPIXEL_SHIFT            7U
+#define IMXDPUV1_FETCHECO2_CONTROL_CLIPCOLOR_MASK            0x10000U
+#define IMXDPUV1_FETCHECO2_CONTROL_CLIPCOLOR_SHIFT           16U
+/* Field Value: CLIPCOLOR__NULL, Null color.  */
+#define IMXDPUV1_FETCHECO2_CONTROL_CLIPCOLOR__NULL           0U
+/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer
+ * (or layer 0 when Fetch unit has one layer only). The color is then the
+ * layer's source or tiling color.  */
+#define IMXDPUV1_FETCHECO2_CONTROL_CLIPCOLOR__LAYER          0x1U
+
+/* Register: IMXDPUV1_fetcheco2_ControlTrigger */
+#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER                    ((uint32_t)(0x6844))
+#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_OFFSET             ((uint32_t)(0x44))
+#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_RESET_VALUE        0U
+#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_RESET_MASK         0xFFFFFFFEU
+#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_SHDTOKGEN_MASK     0x1U
+#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_SHDTOKGEN_SHIFT    0U
+
+/* Register: IMXDPUV1_fetcheco2_Start */
+#define IMXDPUV1_FETCHECO2_START                             ((uint32_t)(0x6848))
+#define IMXDPUV1_FETCHECO2_START_OFFSET                      ((uint32_t)(0x48))
+#define IMXDPUV1_FETCHECO2_START_RESET_VALUE                 0U
+#define IMXDPUV1_FETCHECO2_START_RESET_MASK                  0xFFFFFFFEU
+#define IMXDPUV1_FETCHECO2_START_START_MASK                  0x1U
+#define IMXDPUV1_FETCHECO2_START_START_SHIFT                 0U
+
+/* Register: IMXDPUV1_fetcheco2_FetchType */
+#define IMXDPUV1_FETCHECO2_FETCHTYPE                         ((uint32_t)(0x684C))
+#define IMXDPUV1_FETCHECO2_FETCHTYPE_OFFSET                  ((uint32_t)(0x4C))
+#define IMXDPUV1_FETCHECO2_FETCHTYPE_RESET_VALUE             0U
+#define IMXDPUV1_FETCHECO2_FETCHTYPE_RESET_MASK              0xFFFFFFF0U
+#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE_MASK          0xFU
+#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE_SHIFT         0U
+/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder.  */
+#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__DECODE       0U
+/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers).  */
+#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__LAYER        0x1U
+/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional
+ * plane (8 layers).  */
+#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__WARP         0x2U
+/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha,
+ * chroma and coordinate planes.  */
+#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__ECO          0x3U
+/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and
+ * arbitrary warping.  */
+#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__PERSP        0x4U
+/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping.  */
+#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__ROT          0x5U
+/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced
+ * feature set.  */
+#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__DECODEL      0x6U
+/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers),
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__LAYERL       0x7U
+/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping,
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__ROTL         0x8U
+
+/* Register: IMXDPUV1_fetcheco2_BurstBufferProperties */
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES             ((uint32_t)(0x6850))
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_OFFSET      ((uint32_t)(0x50))
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_RESET_VALUE 0U
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_RESET_MASK  0xFFFFE000U
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U
+#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U
+
+/* Register: IMXDPUV1_fetcheco2_HiddenStatus */
+#define IMXDPUV1_FETCHECO2_HIDDENSTATUS                      ((uint32_t)(0x6854))
+#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_OFFSET               ((uint32_t)(0x54))
+#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_RESET_VALUE          0U
+#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_RESET_MASK           0xFFFF008EU
+#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSBUSY_MASK      0x1U
+#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSBUSY_SHIFT     0U
+#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U
+#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U
+#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSREQUEST_MASK   0x20U
+#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSREQUEST_SHIFT  5U
+#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSCOMPLETE_MASK  0x40U
+#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U
+#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_SHADOWSTATUS_MASK    0xFF00U
+#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_SHADOWSTATUS_SHIFT   8U
+
+/* Register: IMXDPUV1_FetchDecode0_LockUnlock */
+#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK                     ((uint32_t)(0x6C00))
+#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_OFFSET              ((uint32_t)(0))
+#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_RESET_VALUE         0U
+#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_RESET_MASK          0U
+#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK_SHIFT    0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_FetchDecode0_LockStatus */
+#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS                     ((uint32_t)(0x6C04))
+#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_OFFSET              ((uint32_t)(0x4))
+#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_RESET_VALUE         0U
+#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_LOCKSTATUS_MASK     0x1U
+#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_LOCKSTATUS_SHIFT    0U
+#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_FREEZESTATUS_MASK   0x100U
+#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_FREEZESTATUS_SHIFT  8U
+
+/* Register: IMXDPUV1_FetchDecode0_StaticControl */
+#define IMXDPUV1_FETCHDECODE0_STATICCONTROL                  ((uint32_t)(0x6C08))
+#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_OFFSET           ((uint32_t)(0x8))
+#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_RESET_VALUE      0U
+#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_SHDEN_MASK       0x1U
+#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_SHDEN_SHIFT      0U
+#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U
+#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U
+
+/* Register: IMXDPUV1_FetchDecode0_BurstBufferManagement */
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT          ((uint32_t)(0x6C0C))
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_OFFSET   ((uint32_t)(0xC))
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U
+/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the
+ * Display Controller. Works also for Blit Engine with marginal performance
+ * impact.  */
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U
+/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit
+ * Engine.  */
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U
+
+/* Register: IMXDPUV1_FetchDecode0_RingBufStartAddr0 */
+#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0              ((uint32_t)(0x6C10))
+#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_OFFSET       ((uint32_t)(0x10))
+#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_RESET_VALUE  0U
+#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode0_RingBufWrapAddr0 */
+#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0               ((uint32_t)(0x6C14))
+#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_OFFSET        ((uint32_t)(0x14))
+#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_RESET_VALUE   0U
+#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode0_FrameProperties0 */
+#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0               ((uint32_t)(0x6C18))
+#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_OFFSET        ((uint32_t)(0x18))
+#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_RESET_VALUE   0U
+#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_FIELDID0_MASK 0x1U
+#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_FIELDID0_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode0_BaseAddress0 */
+#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0                   ((uint32_t)(0x6C1C))
+#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_OFFSET            ((uint32_t)(0x1C))
+#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_RESET_VALUE       0U
+#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_BASEADDRESS0_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode0_SourceBufferAttributes0 */
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0        ((uint32_t)(0x6C20))
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x20))
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U
+
+/* Register: IMXDPUV1_FetchDecode0_SourceBufferDimension0 */
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0         ((uint32_t)(0x6C24))
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_OFFSET  ((uint32_t)(0x24))
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U
+
+/* Register: IMXDPUV1_FetchDecode0_ColorComponentBits0 */
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0            ((uint32_t)(0x6C28))
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_OFFSET     ((uint32_t)(0x28))
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U
+
+/* Register: IMXDPUV1_FetchDecode0_ColorComponentShift0 */
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0           ((uint32_t)(0x6C2C))
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_OFFSET    ((uint32_t)(0x2C))
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U
+#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_FetchDecode0_LayerOffset0 */
+#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0                   ((uint32_t)(0x6C30))
+#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_OFFSET            ((uint32_t)(0x30))
+#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_RESET_VALUE       0U
+#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU
+#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U
+
+/* Register: IMXDPUV1_FetchDecode0_ClipWindowOffset0 */
+#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0              ((uint32_t)(0x6C34))
+#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_OFFSET       ((uint32_t)(0x34))
+#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_RESET_VALUE  0U
+#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU
+#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U
+
+/* Register: IMXDPUV1_FetchDecode0_ClipWindowDimensions0 */
+#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0          ((uint32_t)(0x6C38))
+#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_OFFSET   ((uint32_t)(0x38))
+#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U
+#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U
+
+/* Register: IMXDPUV1_FetchDecode0_ConstantColor0 */
+#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0                 ((uint32_t)(0x6C3C))
+#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_OFFSET          ((uint32_t)(0x3C))
+#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_RESET_VALUE     0U
+#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU
+#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U
+#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U
+#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U
+#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_FetchDecode0_LayerProperty0 */
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0                 ((uint32_t)(0x6C40))
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_OFFSET          ((uint32_t)(0x40))
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RESET_VALUE     0x80000100U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_PALETTEENABLE0_MASK 0x1U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_PALETTEENABLE0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0_MASK  0x30U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0_SHIFT 4U
+/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U
+/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion.  */
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U
+/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U
+#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U
+
+/* Register: IMXDPUV1_FetchDecode0_FrameDimensions */
+#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS                ((uint32_t)(0x6C44))
+#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_OFFSET         ((uint32_t)(0x44))
+#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_RESET_VALUE    0xEF013FU
+#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU
+#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U
+#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U
+#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U
+
+/* Register: IMXDPUV1_FetchDecode0_FrameResampling */
+#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING                ((uint32_t)(0x6C48))
+#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_OFFSET         ((uint32_t)(0x48))
+#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_RESET_VALUE    0x104000U
+#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_STARTX_MASK    0x3FU
+#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_STARTX_SHIFT   0U
+#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_STARTY_MASK    0xFC0U
+#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_STARTY_SHIFT   6U
+#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_DELTAX_MASK    0x3F000U
+#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_DELTAX_SHIFT   12U
+#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_DELTAY_MASK    0xFC0000U
+#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_DELTAY_SHIFT   18U
+#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U
+#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U
+
+/* Register: IMXDPUV1_FetchDecode0_DecodeControl */
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL                  ((uint32_t)(0x6C4C))
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_OFFSET           ((uint32_t)(0x4C))
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RESET_VALUE      0x88880001U
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE_MASK 0x3U
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE_SHIFT 0U
+/* Field Value: COMPRESSIONMODE__RLAD, Run-Length Adaptive Dithering (lossy
+ * compression).  */
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE__RLAD 0U
+/* Field Value: COMPRESSIONMODE__RLAD_UNIFORM, Run-Length Adaptive Dithering
+ * (lossy compression; uniform package size).  */
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE__RLAD_UNIFORM 0x1U
+/* Field Value: COMPRESSIONMODE__RLA, Run-Length Adaptive (lossless compression).  */
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE__RLA 0x2U
+/* Field Value: COMPRESSIONMODE__RL, Standard Run-Length.  */
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE__RL 0x3U
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADENDIANNESS_MASK 0x8000U
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADENDIANNESS_SHIFT 15U
+/* Field Value: RLADENDIANNESS__BIGENDIAN, Big endian format  */
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADENDIANNESS__BIGENDIAN 0U
+/* Field Value: RLADENDIANNESS__LITTLEENDIAN, Little endian format  */
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADENDIANNESS__LITTLEENDIAN 0x1U
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSRED_MASK 0xF0000U
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSRED_SHIFT 16U
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSGREEN_MASK 0xF00000U
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSGREEN_SHIFT 20U
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSBLUE_MASK 0xF000000U
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSBLUE_SHIFT 24U
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSALPHA_MASK 0xF0000000U
+#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSALPHA_SHIFT 28U
+
+/* Register: IMXDPUV1_FetchDecode0_SourceBufferLength */
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH             ((uint32_t)(0x6C50))
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_OFFSET      ((uint32_t)(0x50))
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_RESET_VALUE 0U
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_RLEWORDS_MASK 0x1FFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_RLEWORDS_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode0_Control */
+#define IMXDPUV1_FETCHDECODE0_CONTROL                        ((uint32_t)(0x6C54))
+#define IMXDPUV1_FETCHDECODE0_CONTROL_OFFSET                 ((uint32_t)(0x54))
+#define IMXDPUV1_FETCHDECODE0_CONTROL_RESET_VALUE            0x10700U
+#define IMXDPUV1_FETCHDECODE0_CONTROL_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE_MASK        0x7U
+#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE_SHIFT       0U
+/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin.
+ * Hor/ver increments using DeltaX/Y and DeltaSwap setup.  */
+#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__NORMAL     0U
+/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source
+ * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver
+ * increments = (1,0)/(0,1).  */
+#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__DECODE     0x1U
+/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary
+ * warping (filter is active). Coordinates are read from frame input
+ * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY
+ * must be setup.  */
+#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__ARBITRARY  0x2U
+/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective
+ * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver
+ * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates.  */
+#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__PERSPECTIVE 0x3U
+/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer
+ * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments
+ * = (1,0)/(0,1). All corellated window widths and horizontal offsets must
+ * be even.  */
+#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__YUV422     0x4U
+/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter
+ * is active). First sample at AffineStartX/Y. Hor/ver increments using
+ * AffineDeltaXX/XY/YX/YY. Cartesian coordinates.  */
+#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__AFFINE     0x5U
+#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT_MASK       0x18U
+#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT_SHIFT      3U
+/* Field Value: INPUTSELECT__INACTIVE, Not used.  */
+#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__INACTIVE  0U
+/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV
+ * or source alpha buffer).  */
+#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__COMPPACK  0x1U
+/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply
+ * stage (mask alpha buffer).  */
+#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__ALPHAMASK 0x2U
+/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate
+ * buffer).  */
+#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__COORDINATE 0x3U
+#define IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE_MASK 0x20U
+#define IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE_SHIFT 5U
+/* Field Value: YUV422UPSAMPLINGMODE__REPLICATE, Replicate mode for interspersed
+ * samples (UV samples between Y samples).  */
+#define IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE__REPLICATE 0U
+/* Field Value: YUV422UPSAMPLINGMODE__INTERPOLATE, Interpolate mode for coaligned
+ * samples (UV samples at Y sample positions).  */
+#define IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE__INTERPOLATE 0x1U
+#define IMXDPUV1_FETCHDECODE0_CONTROL_RAWPIXEL_MASK          0x80U
+#define IMXDPUV1_FETCHDECODE0_CONTROL_RAWPIXEL_SHIFT         7U
+#define IMXDPUV1_FETCHDECODE0_CONTROL_PALETTEIDXWIDTH_MASK   0x700U
+#define IMXDPUV1_FETCHDECODE0_CONTROL_PALETTEIDXWIDTH_SHIFT  8U
+#define IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR_MASK         0x10000U
+#define IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR_SHIFT        16U
+/* Field Value: CLIPCOLOR__NULL, Null color.  */
+#define IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR__NULL        0U
+/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer
+ * (or layer 0 when Fetch unit has one layer only). The color is then the
+ * layer's source or tiling color.  */
+#define IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR__LAYER       0x1U
+
+/* Register: IMXDPUV1_FetchDecode0_ControlTrigger */
+#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER                 ((uint32_t)(0x6C58))
+#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_OFFSET          ((uint32_t)(0x58))
+#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_RESET_VALUE     0U
+#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_RESET_MASK      0xFFFFFFFEU
+#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_SHDTOKGEN_MASK  0x1U
+#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode0_Start */
+#define IMXDPUV1_FETCHDECODE0_START                          ((uint32_t)(0x6C5C))
+#define IMXDPUV1_FETCHDECODE0_START_OFFSET                   ((uint32_t)(0x5C))
+#define IMXDPUV1_FETCHDECODE0_START_RESET_VALUE              0U
+#define IMXDPUV1_FETCHDECODE0_START_RESET_MASK               0xFFFFFFFEU
+#define IMXDPUV1_FETCHDECODE0_START_START_MASK               0x1U
+#define IMXDPUV1_FETCHDECODE0_START_START_SHIFT              0U
+
+/* Register: IMXDPUV1_FetchDecode0_FetchType */
+#define IMXDPUV1_FETCHDECODE0_FETCHTYPE                      ((uint32_t)(0x6C60))
+#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_OFFSET               ((uint32_t)(0x60))
+#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_RESET_VALUE          0U
+#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_RESET_MASK           0xFFFFFFF0U
+#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE_MASK       0xFU
+#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE_SHIFT      0U
+/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder.  */
+#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__DECODE    0U
+/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers).  */
+#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__LAYER     0x1U
+/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional
+ * plane (8 layers).  */
+#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__WARP      0x2U
+/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha,
+ * chroma and coordinate planes.  */
+#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__ECO       0x3U
+/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and
+ * arbitrary warping.  */
+#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__PERSP     0x4U
+/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping.  */
+#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__ROT       0x5U
+/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced
+ * feature set.  */
+#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__DECODEL   0x6U
+/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers),
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__LAYERL    0x7U
+/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping,
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__ROTL      0x8U
+
+/* Register: IMXDPUV1_FetchDecode0_DecoderStatus */
+#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS                  ((uint32_t)(0x6C64))
+#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_OFFSET           ((uint32_t)(0x64))
+#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_RESET_VALUE      0U
+#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_BUFFERTOOSMALL_MASK 0x1U
+#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_BUFFERTOOSMALL_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_BUFFERTOOLARGE_MASK 0x2U
+#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_BUFFERTOOLARGE_SHIFT 1U
+
+/* Register: IMXDPUV1_FetchDecode0_ReadAddress0 */
+#define IMXDPUV1_FETCHDECODE0_READADDRESS0                   ((uint32_t)(0x6C68))
+#define IMXDPUV1_FETCHDECODE0_READADDRESS0_OFFSET            ((uint32_t)(0x68))
+#define IMXDPUV1_FETCHDECODE0_READADDRESS0_RESET_VALUE       0U
+#define IMXDPUV1_FETCHDECODE0_READADDRESS0_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_READADDRESS0_READADDRESS0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_READADDRESS0_READADDRESS0_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode0_BurstBufferProperties */
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES          ((uint32_t)(0x6C6C))
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_OFFSET   ((uint32_t)(0x6C))
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_RESET_VALUE 0U
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U
+#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U
+
+/* Register: IMXDPUV1_FetchDecode0_Status */
+#define IMXDPUV1_FETCHDECODE0_STATUS                         ((uint32_t)(0x6C70))
+#define IMXDPUV1_FETCHDECODE0_STATUS_OFFSET                  ((uint32_t)(0x70))
+#define IMXDPUV1_FETCHDECODE0_STATUS_RESET_VALUE             0U
+#define IMXDPUV1_FETCHDECODE0_STATUS_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_STATUS_WRITETIMEOUT_MASK       0x1U
+#define IMXDPUV1_FETCHDECODE0_STATUS_WRITETIMEOUT_SHIFT      0U
+#define IMXDPUV1_FETCHDECODE0_STATUS_READTIMEOUT_MASK        0x10U
+#define IMXDPUV1_FETCHDECODE0_STATUS_READTIMEOUT_SHIFT       4U
+
+/* Register: IMXDPUV1_FetchDecode0_HiddenStatus */
+#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS                   ((uint32_t)(0x6C74))
+#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_OFFSET            ((uint32_t)(0x74))
+#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_RESET_VALUE       0U
+#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_RESET_MASK        0xFFFF008EU
+#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSBUSY_MASK   0x1U
+#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSBUSY_SHIFT  0U
+#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U
+#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U
+#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U
+#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U
+#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U
+#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U
+#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U
+#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_FetchDecode0_ColorPalette */
+#define IMXDPUV1_FETCHDECODE0_COLORPALETTE                   ((uint32_t)(0x7000))
+#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_OFFSET            ((uint32_t)(0))
+#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_RESET_VALUE       0U
+#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_RESET_MASK        0xFF000000U
+#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_COLORPALETTE_MASK 0xFFFFFFU
+#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_COLORPALETTE_SHIFT 0U
+
+/* Register: IMXDPUV1_fetcheco0_LockUnlock */
+#define IMXDPUV1_FETCHECO0_LOCKUNLOCK                        ((uint32_t)(0x7400))
+#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_OFFSET                 ((uint32_t)(0))
+#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_RESET_VALUE            0U
+#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_RESET_MASK             0U
+#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK_SHIFT       0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY   0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_fetcheco0_LockStatus */
+#define IMXDPUV1_FETCHECO0_LOCKSTATUS                        ((uint32_t)(0x7404))
+#define IMXDPUV1_FETCHECO0_LOCKSTATUS_OFFSET                 ((uint32_t)(0x4))
+#define IMXDPUV1_FETCHECO0_LOCKSTATUS_RESET_VALUE            0U
+#define IMXDPUV1_FETCHECO0_LOCKSTATUS_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO0_LOCKSTATUS_LOCKSTATUS_MASK        0x1U
+#define IMXDPUV1_FETCHECO0_LOCKSTATUS_LOCKSTATUS_SHIFT       0U
+#define IMXDPUV1_FETCHECO0_LOCKSTATUS_PRIVILEGESTATUS_MASK   0x10U
+#define IMXDPUV1_FETCHECO0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT  4U
+#define IMXDPUV1_FETCHECO0_LOCKSTATUS_FREEZESTATUS_MASK      0x100U
+#define IMXDPUV1_FETCHECO0_LOCKSTATUS_FREEZESTATUS_SHIFT     8U
+
+/* Register: IMXDPUV1_fetcheco0_StaticControl */
+#define IMXDPUV1_FETCHECO0_STATICCONTROL                     ((uint32_t)(0x7408))
+#define IMXDPUV1_FETCHECO0_STATICCONTROL_OFFSET              ((uint32_t)(0x8))
+#define IMXDPUV1_FETCHECO0_STATICCONTROL_RESET_VALUE         0U
+#define IMXDPUV1_FETCHECO0_STATICCONTROL_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO0_STATICCONTROL_SHDEN_MASK          0x1U
+#define IMXDPUV1_FETCHECO0_STATICCONTROL_SHDEN_SHIFT         0U
+#define IMXDPUV1_FETCHECO0_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U
+#define IMXDPUV1_FETCHECO0_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco0_BurstBufferManagement */
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT             ((uint32_t)(0x740C))
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_OFFSET      ((uint32_t)(0xC))
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U
+/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the
+ * Display Controller. Works also for Blit Engine with marginal performance
+ * impact.  */
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U
+/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit
+ * Engine.  */
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U
+
+/* Register: IMXDPUV1_fetcheco0_BaseAddress0 */
+#define IMXDPUV1_FETCHECO0_BASEADDRESS0                      ((uint32_t)(0x7410))
+#define IMXDPUV1_FETCHECO0_BASEADDRESS0_OFFSET               ((uint32_t)(0x10))
+#define IMXDPUV1_FETCHECO0_BASEADDRESS0_RESET_VALUE          0U
+#define IMXDPUV1_FETCHECO0_BASEADDRESS0_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO0_BASEADDRESS0_BASEADDRESS0_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO0_BASEADDRESS0_BASEADDRESS0_SHIFT   0U
+
+/* Register: IMXDPUV1_fetcheco0_SourceBufferAttributes0 */
+#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0           ((uint32_t)(0x7414))
+#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_OFFSET    ((uint32_t)(0x14))
+#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU
+#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU
+#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U
+#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U
+#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco0_SourceBufferDimension0 */
+#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0            ((uint32_t)(0x7418))
+#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_OFFSET     ((uint32_t)(0x18))
+#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco0_ColorComponentBits0 */
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0               ((uint32_t)(0x741C))
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_OFFSET        ((uint32_t)(0x1C))
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_RESET_VALUE   0x8080808U
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U
+
+/* Register: IMXDPUV1_fetcheco0_ColorComponentShift0 */
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0              ((uint32_t)(0x7420))
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_OFFSET       ((uint32_t)(0x20))
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_RESET_VALUE  0x18100800U
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U
+#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_fetcheco0_LayerOffset0 */
+#define IMXDPUV1_FETCHECO0_LAYEROFFSET0                      ((uint32_t)(0x7424))
+#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_OFFSET               ((uint32_t)(0x24))
+#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_RESET_VALUE          0U
+#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_LAYERXOFFSET0_MASK   0x7FFFU
+#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_LAYERXOFFSET0_SHIFT  0U
+#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_LAYERYOFFSET0_MASK   0x7FFF0000U
+#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_LAYERYOFFSET0_SHIFT  16U
+
+/* Register: IMXDPUV1_fetcheco0_ClipWindowOffset0 */
+#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0                 ((uint32_t)(0x7428))
+#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_OFFSET          ((uint32_t)(0x28))
+#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_RESET_VALUE     0U
+#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU
+#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U
+#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco0_ClipWindowDimensions0 */
+#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0             ((uint32_t)(0x742C))
+#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_OFFSET      ((uint32_t)(0x2C))
+#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U
+#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco0_ConstantColor0 */
+#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0                    ((uint32_t)(0x7430))
+#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_OFFSET             ((uint32_t)(0x30))
+#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_RESET_VALUE        0U
+#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU
+#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U
+#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U
+#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTRED0_MASK  0xFF000000U
+#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_fetcheco0_LayerProperty0 */
+#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0                    ((uint32_t)(0x7434))
+#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_OFFSET             ((uint32_t)(0x34))
+#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_RESET_VALUE        0x80000000U
+#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0_MASK     0x30U
+#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0_SHIFT    4U
+/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U
+/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U
+#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U
+#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U
+#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U
+
+/* Register: IMXDPUV1_fetcheco0_FrameDimensions */
+#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS                   ((uint32_t)(0x7438))
+#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_OFFSET            ((uint32_t)(0x38))
+#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_RESET_VALUE       0xEF013FU
+#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEWIDTH_MASK   0x3FFFU
+#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT  0U
+#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK  0x3FFF0000U
+#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U
+#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_EMPTYFRAME_MASK   0x80000000U
+#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT  31U
+
+/* Register: IMXDPUV1_fetcheco0_FrameResampling */
+#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING                   ((uint32_t)(0x743C))
+#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_OFFSET            ((uint32_t)(0x3C))
+#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_RESET_VALUE       0x104000U
+#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_STARTX_MASK       0x3FU
+#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_STARTX_SHIFT      0U
+#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_STARTY_MASK       0xFC0U
+#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_STARTY_SHIFT      6U
+#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAX_MASK       0x3F000U
+#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAX_SHIFT      12U
+#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAY_MASK       0xFC0000U
+#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAY_SHIFT      18U
+#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U
+#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U
+
+/* Register: IMXDPUV1_fetcheco0_Control */
+#define IMXDPUV1_FETCHECO0_CONTROL                           ((uint32_t)(0x7440))
+#define IMXDPUV1_FETCHECO0_CONTROL_OFFSET                    ((uint32_t)(0x40))
+#define IMXDPUV1_FETCHECO0_CONTROL_RESET_VALUE               0x10000U
+#define IMXDPUV1_FETCHECO0_CONTROL_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO0_CONTROL_RAWPIXEL_MASK             0x80U
+#define IMXDPUV1_FETCHECO0_CONTROL_RAWPIXEL_SHIFT            7U
+#define IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR_MASK            0x10000U
+#define IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR_SHIFT           16U
+/* Field Value: CLIPCOLOR__NULL, Null color.  */
+#define IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR__NULL           0U
+/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer
+ * (or layer 0 when Fetch unit has one layer only). The color is then the
+ * layer's source or tiling color.  */
+#define IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR__LAYER          0x1U
+
+/* Register: IMXDPUV1_fetcheco0_ControlTrigger */
+#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER                    ((uint32_t)(0x7444))
+#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_OFFSET             ((uint32_t)(0x44))
+#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_RESET_VALUE        0U
+#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_RESET_MASK         0xFFFFFFFEU
+#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_SHDTOKGEN_MASK     0x1U
+#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_SHDTOKGEN_SHIFT    0U
+
+/* Register: IMXDPUV1_fetcheco0_Start */
+#define IMXDPUV1_FETCHECO0_START                             ((uint32_t)(0x7448))
+#define IMXDPUV1_FETCHECO0_START_OFFSET                      ((uint32_t)(0x48))
+#define IMXDPUV1_FETCHECO0_START_RESET_VALUE                 0U
+#define IMXDPUV1_FETCHECO0_START_RESET_MASK                  0xFFFFFFFEU
+#define IMXDPUV1_FETCHECO0_START_START_MASK                  0x1U
+#define IMXDPUV1_FETCHECO0_START_START_SHIFT                 0U
+
+/* Register: IMXDPUV1_fetcheco0_FetchType */
+#define IMXDPUV1_FETCHECO0_FETCHTYPE                         ((uint32_t)(0x744C))
+#define IMXDPUV1_FETCHECO0_FETCHTYPE_OFFSET                  ((uint32_t)(0x4C))
+#define IMXDPUV1_FETCHECO0_FETCHTYPE_RESET_VALUE             0U
+#define IMXDPUV1_FETCHECO0_FETCHTYPE_RESET_MASK              0xFFFFFFF0U
+#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE_MASK          0xFU
+#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE_SHIFT         0U
+/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder.  */
+#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__DECODE       0U
+/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers).  */
+#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__LAYER        0x1U
+/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional
+ * plane (8 layers).  */
+#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__WARP         0x2U
+/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha,
+ * chroma and coordinate planes.  */
+#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__ECO          0x3U
+/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and
+ * arbitrary warping.  */
+#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__PERSP        0x4U
+/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping.  */
+#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__ROT          0x5U
+/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced
+ * feature set.  */
+#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__DECODEL      0x6U
+/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers),
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__LAYERL       0x7U
+/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping,
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__ROTL         0x8U
+
+/* Register: IMXDPUV1_fetcheco0_BurstBufferProperties */
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES             ((uint32_t)(0x7450))
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_OFFSET      ((uint32_t)(0x50))
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_RESET_VALUE 0U
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_RESET_MASK  0xFFFFE000U
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U
+#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U
+
+/* Register: IMXDPUV1_fetcheco0_HiddenStatus */
+#define IMXDPUV1_FETCHECO0_HIDDENSTATUS                      ((uint32_t)(0x7454))
+#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_OFFSET               ((uint32_t)(0x54))
+#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_RESET_VALUE          0U
+#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_RESET_MASK           0xFFFF008EU
+#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSBUSY_MASK      0x1U
+#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSBUSY_SHIFT     0U
+#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U
+#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U
+#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSREQUEST_MASK   0x20U
+#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSREQUEST_SHIFT  5U
+#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSCOMPLETE_MASK  0x40U
+#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U
+#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_SHADOWSTATUS_MASK    0xFF00U
+#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_SHADOWSTATUS_SHIFT   8U
+
+/* Register: IMXDPUV1_FetchDecode1_LockUnlock */
+#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK                     ((uint32_t)(0x7800))
+#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_OFFSET              ((uint32_t)(0))
+#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_RESET_VALUE         0U
+#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_RESET_MASK          0U
+#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK_SHIFT    0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_FetchDecode1_LockStatus */
+#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS                     ((uint32_t)(0x7804))
+#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_OFFSET              ((uint32_t)(0x4))
+#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_RESET_VALUE         0U
+#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_LOCKSTATUS_MASK     0x1U
+#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_LOCKSTATUS_SHIFT    0U
+#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_FREEZESTATUS_MASK   0x100U
+#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_FREEZESTATUS_SHIFT  8U
+
+/* Register: IMXDPUV1_FetchDecode1_StaticControl */
+#define IMXDPUV1_FETCHDECODE1_STATICCONTROL                  ((uint32_t)(0x7808))
+#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_OFFSET           ((uint32_t)(0x8))
+#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_RESET_VALUE      0U
+#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_SHDEN_MASK       0x1U
+#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_SHDEN_SHIFT      0U
+#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U
+#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U
+
+/* Register: IMXDPUV1_FetchDecode1_BurstBufferManagement */
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT          ((uint32_t)(0x780C))
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_OFFSET   ((uint32_t)(0xC))
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U
+/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the
+ * Display Controller. Works also for Blit Engine with marginal performance
+ * impact.  */
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U
+/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit
+ * Engine.  */
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U
+
+/* Register: IMXDPUV1_FetchDecode1_RingBufStartAddr0 */
+#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0              ((uint32_t)(0x7810))
+#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_OFFSET       ((uint32_t)(0x10))
+#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_RESET_VALUE  0U
+#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode1_RingBufWrapAddr0 */
+#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0               ((uint32_t)(0x7814))
+#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_OFFSET        ((uint32_t)(0x14))
+#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_RESET_VALUE   0U
+#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode1_FrameProperties0 */
+#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0               ((uint32_t)(0x7818))
+#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_OFFSET        ((uint32_t)(0x18))
+#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_RESET_VALUE   0U
+#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_FIELDID0_MASK 0x1U
+#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_FIELDID0_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode1_BaseAddress0 */
+#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0                   ((uint32_t)(0x781C))
+#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_OFFSET            ((uint32_t)(0x1C))
+#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_RESET_VALUE       0U
+#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_BASEADDRESS0_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode1_SourceBufferAttributes0 */
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0        ((uint32_t)(0x7820))
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x20))
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U
+
+/* Register: IMXDPUV1_FetchDecode1_SourceBufferDimension0 */
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0         ((uint32_t)(0x7824))
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_OFFSET  ((uint32_t)(0x24))
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U
+
+/* Register: IMXDPUV1_FetchDecode1_ColorComponentBits0 */
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0            ((uint32_t)(0x7828))
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_OFFSET     ((uint32_t)(0x28))
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U
+
+/* Register: IMXDPUV1_FetchDecode1_ColorComponentShift0 */
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0           ((uint32_t)(0x782C))
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_OFFSET    ((uint32_t)(0x2C))
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U
+#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_FetchDecode1_LayerOffset0 */
+#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0                   ((uint32_t)(0x7830))
+#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_OFFSET            ((uint32_t)(0x30))
+#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_RESET_VALUE       0U
+#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU
+#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U
+
+/* Register: IMXDPUV1_FetchDecode1_ClipWindowOffset0 */
+#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0              ((uint32_t)(0x7834))
+#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_OFFSET       ((uint32_t)(0x34))
+#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_RESET_VALUE  0U
+#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU
+#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U
+
+/* Register: IMXDPUV1_FetchDecode1_ClipWindowDimensions0 */
+#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0          ((uint32_t)(0x7838))
+#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_OFFSET   ((uint32_t)(0x38))
+#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U
+#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U
+
+/* Register: IMXDPUV1_FetchDecode1_ConstantColor0 */
+#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0                 ((uint32_t)(0x783C))
+#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_OFFSET          ((uint32_t)(0x3C))
+#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_RESET_VALUE     0U
+#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU
+#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U
+#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U
+#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U
+#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_FetchDecode1_LayerProperty0 */
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0                 ((uint32_t)(0x7840))
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_OFFSET          ((uint32_t)(0x40))
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RESET_VALUE     0x80000100U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_PALETTEENABLE0_MASK 0x1U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_PALETTEENABLE0_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0_MASK  0x30U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0_SHIFT 4U
+/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U
+/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion.  */
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U
+/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U
+#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U
+
+/* Register: IMXDPUV1_FetchDecode1_FrameDimensions */
+#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS                ((uint32_t)(0x7844))
+#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_OFFSET         ((uint32_t)(0x44))
+#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_RESET_VALUE    0xEF013FU
+#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU
+#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U
+#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U
+#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U
+
+/* Register: IMXDPUV1_FetchDecode1_FrameResampling */
+#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING                ((uint32_t)(0x7848))
+#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_OFFSET         ((uint32_t)(0x48))
+#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_RESET_VALUE    0x104000U
+#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_STARTX_MASK    0x3FU
+#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_STARTX_SHIFT   0U
+#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_STARTY_MASK    0xFC0U
+#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_STARTY_SHIFT   6U
+#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_DELTAX_MASK    0x3F000U
+#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_DELTAX_SHIFT   12U
+#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_DELTAY_MASK    0xFC0000U
+#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_DELTAY_SHIFT   18U
+#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U
+#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U
+
+/* Register: IMXDPUV1_FetchDecode1_DecodeControl */
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL                  ((uint32_t)(0x784C))
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_OFFSET           ((uint32_t)(0x4C))
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RESET_VALUE      0x88880001U
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE_MASK 0x3U
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE_SHIFT 0U
+/* Field Value: COMPRESSIONMODE__RLAD, Run-Length Adaptive Dithering (lossy
+ * compression).  */
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE__RLAD 0U
+/* Field Value: COMPRESSIONMODE__RLAD_UNIFORM, Run-Length Adaptive Dithering
+ * (lossy compression; uniform package size).  */
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE__RLAD_UNIFORM 0x1U
+/* Field Value: COMPRESSIONMODE__RLA, Run-Length Adaptive (lossless compression).  */
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE__RLA 0x2U
+/* Field Value: COMPRESSIONMODE__RL, Standard Run-Length.  */
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE__RL 0x3U
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADENDIANNESS_MASK 0x8000U
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADENDIANNESS_SHIFT 15U
+/* Field Value: RLADENDIANNESS__BIGENDIAN, Big endian format  */
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADENDIANNESS__BIGENDIAN 0U
+/* Field Value: RLADENDIANNESS__LITTLEENDIAN, Little endian format  */
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADENDIANNESS__LITTLEENDIAN 0x1U
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSRED_MASK 0xF0000U
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSRED_SHIFT 16U
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSGREEN_MASK 0xF00000U
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSGREEN_SHIFT 20U
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSBLUE_MASK 0xF000000U
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSBLUE_SHIFT 24U
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSALPHA_MASK 0xF0000000U
+#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSALPHA_SHIFT 28U
+
+/* Register: IMXDPUV1_FetchDecode1_SourceBufferLength */
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH             ((uint32_t)(0x7850))
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_OFFSET      ((uint32_t)(0x50))
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_RESET_VALUE 0U
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_RLEWORDS_MASK 0x1FFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_RLEWORDS_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode1_Control */
+#define IMXDPUV1_FETCHDECODE1_CONTROL                        ((uint32_t)(0x7854))
+#define IMXDPUV1_FETCHDECODE1_CONTROL_OFFSET                 ((uint32_t)(0x54))
+#define IMXDPUV1_FETCHDECODE1_CONTROL_RESET_VALUE            0x10700U
+#define IMXDPUV1_FETCHDECODE1_CONTROL_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE_MASK        0x7U
+#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE_SHIFT       0U
+/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin.
+ * Hor/ver increments using DeltaX/Y and DeltaSwap setup.  */
+#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__NORMAL     0U
+/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source
+ * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver
+ * increments = (1,0)/(0,1).  */
+#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__DECODE     0x1U
+/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary
+ * warping (filter is active). Coordinates are read from frame input
+ * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY
+ * must be setup.  */
+#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__ARBITRARY  0x2U
+/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective
+ * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver
+ * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates.  */
+#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__PERSPECTIVE 0x3U
+/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer
+ * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments
+ * = (1,0)/(0,1). All corellated window widths and horizontal offsets must
+ * be even.  */
+#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__YUV422     0x4U
+/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter
+ * is active). First sample at AffineStartX/Y. Hor/ver increments using
+ * AffineDeltaXX/XY/YX/YY. Cartesian coordinates.  */
+#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__AFFINE     0x5U
+#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT_MASK       0x18U
+#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT_SHIFT      3U
+/* Field Value: INPUTSELECT__INACTIVE, Not used.  */
+#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT__INACTIVE  0U
+/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV
+ * or source alpha buffer).  */
+#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT__COMPPACK  0x1U
+/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply
+ * stage (mask alpha buffer).  */
+#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT__ALPHAMASK 0x2U
+/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate
+ * buffer).  */
+#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT__COORDINATE 0x3U
+#define IMXDPUV1_FETCHDECODE1_CONTROL_YUV422UPSAMPLINGMODE_MASK 0x20U
+#define IMXDPUV1_FETCHDECODE1_CONTROL_YUV422UPSAMPLINGMODE_SHIFT 5U
+/* Field Value: YUV422UPSAMPLINGMODE__REPLICATE, Replicate mode for interspersed
+ * samples (UV samples between Y samples).  */
+#define IMXDPUV1_FETCHDECODE1_CONTROL_YUV422UPSAMPLINGMODE__REPLICATE 0U
+/* Field Value: YUV422UPSAMPLINGMODE__INTERPOLATE, Interpolate mode for coaligned
+ * samples (UV samples at Y sample positions).  */
+#define IMXDPUV1_FETCHDECODE1_CONTROL_YUV422UPSAMPLINGMODE__INTERPOLATE 0x1U
+#define IMXDPUV1_FETCHDECODE1_CONTROL_RAWPIXEL_MASK          0x80U
+#define IMXDPUV1_FETCHDECODE1_CONTROL_RAWPIXEL_SHIFT         7U
+#define IMXDPUV1_FETCHDECODE1_CONTROL_PALETTEIDXWIDTH_MASK   0x700U
+#define IMXDPUV1_FETCHDECODE1_CONTROL_PALETTEIDXWIDTH_SHIFT  8U
+#define IMXDPUV1_FETCHDECODE1_CONTROL_CLIPCOLOR_MASK         0x10000U
+#define IMXDPUV1_FETCHDECODE1_CONTROL_CLIPCOLOR_SHIFT        16U
+/* Field Value: CLIPCOLOR__NULL, Null color.  */
+#define IMXDPUV1_FETCHDECODE1_CONTROL_CLIPCOLOR__NULL        0U
+/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer
+ * (or layer 0 when Fetch unit has one layer only). The color is then the
+ * layer's source or tiling color.  */
+#define IMXDPUV1_FETCHDECODE1_CONTROL_CLIPCOLOR__LAYER       0x1U
+
+/* Register: IMXDPUV1_FetchDecode1_ControlTrigger */
+#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER                 ((uint32_t)(0x7858))
+#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_OFFSET          ((uint32_t)(0x58))
+#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_RESET_VALUE     0U
+#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_RESET_MASK      0xFFFFFFFEU
+#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_SHDTOKGEN_MASK  0x1U
+#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode1_Start */
+#define IMXDPUV1_FETCHDECODE1_START                          ((uint32_t)(0x785C))
+#define IMXDPUV1_FETCHDECODE1_START_OFFSET                   ((uint32_t)(0x5C))
+#define IMXDPUV1_FETCHDECODE1_START_RESET_VALUE              0U
+#define IMXDPUV1_FETCHDECODE1_START_RESET_MASK               0xFFFFFFFEU
+#define IMXDPUV1_FETCHDECODE1_START_START_MASK               0x1U
+#define IMXDPUV1_FETCHDECODE1_START_START_SHIFT              0U
+
+/* Register: IMXDPUV1_FetchDecode1_FetchType */
+#define IMXDPUV1_FETCHDECODE1_FETCHTYPE                      ((uint32_t)(0x7860))
+#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_OFFSET               ((uint32_t)(0x60))
+#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_RESET_VALUE          0U
+#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_RESET_MASK           0xFFFFFFF0U
+#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE_MASK       0xFU
+#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE_SHIFT      0U
+/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder.  */
+#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__DECODE    0U
+/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers).  */
+#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__LAYER     0x1U
+/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional
+ * plane (8 layers).  */
+#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__WARP      0x2U
+/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha,
+ * chroma and coordinate planes.  */
+#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__ECO       0x3U
+/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and
+ * arbitrary warping.  */
+#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__PERSP     0x4U
+/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping.  */
+#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__ROT       0x5U
+/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced
+ * feature set.  */
+#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__DECODEL   0x6U
+/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers),
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__LAYERL    0x7U
+/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping,
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__ROTL      0x8U
+
+/* Register: IMXDPUV1_FetchDecode1_DecoderStatus */
+#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS                  ((uint32_t)(0x7864))
+#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_OFFSET           ((uint32_t)(0x64))
+#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_RESET_VALUE      0U
+#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_BUFFERTOOSMALL_MASK 0x1U
+#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_BUFFERTOOSMALL_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_BUFFERTOOLARGE_MASK 0x2U
+#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_BUFFERTOOLARGE_SHIFT 1U
+
+/* Register: IMXDPUV1_FetchDecode1_ReadAddress0 */
+#define IMXDPUV1_FETCHDECODE1_READADDRESS0                   ((uint32_t)(0x7868))
+#define IMXDPUV1_FETCHDECODE1_READADDRESS0_OFFSET            ((uint32_t)(0x68))
+#define IMXDPUV1_FETCHDECODE1_READADDRESS0_RESET_VALUE       0U
+#define IMXDPUV1_FETCHDECODE1_READADDRESS0_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_READADDRESS0_READADDRESS0_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_READADDRESS0_READADDRESS0_SHIFT 0U
+
+/* Register: IMXDPUV1_FetchDecode1_BurstBufferProperties */
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES          ((uint32_t)(0x786C))
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_OFFSET   ((uint32_t)(0x6C))
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_RESET_VALUE 0U
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U
+#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U
+
+/* Register: IMXDPUV1_FetchDecode1_Status */
+#define IMXDPUV1_FETCHDECODE1_STATUS                         ((uint32_t)(0x7870))
+#define IMXDPUV1_FETCHDECODE1_STATUS_OFFSET                  ((uint32_t)(0x70))
+#define IMXDPUV1_FETCHDECODE1_STATUS_RESET_VALUE             0U
+#define IMXDPUV1_FETCHDECODE1_STATUS_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_STATUS_WRITETIMEOUT_MASK       0x1U
+#define IMXDPUV1_FETCHDECODE1_STATUS_WRITETIMEOUT_SHIFT      0U
+#define IMXDPUV1_FETCHDECODE1_STATUS_READTIMEOUT_MASK        0x10U
+#define IMXDPUV1_FETCHDECODE1_STATUS_READTIMEOUT_SHIFT       4U
+
+/* Register: IMXDPUV1_FetchDecode1_HiddenStatus */
+#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS                   ((uint32_t)(0x7874))
+#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_OFFSET            ((uint32_t)(0x74))
+#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_RESET_VALUE       0U
+#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_RESET_MASK        0xFFFF008EU
+#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSBUSY_MASK   0x1U
+#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSBUSY_SHIFT  0U
+#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U
+#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U
+#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U
+#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U
+#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U
+#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U
+#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U
+#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_FetchDecode1_ColorPalette */
+#define IMXDPUV1_FETCHDECODE1_COLORPALETTE                   ((uint32_t)(0x7C00))
+#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_OFFSET            ((uint32_t)(0))
+#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_RESET_VALUE       0U
+#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_RESET_MASK        0xFF000000U
+#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_COLORPALETTE_MASK 0xFFFFFFU
+#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_COLORPALETTE_SHIFT 0U
+
+/* Register: IMXDPUV1_fetcheco1_LockUnlock */
+#define IMXDPUV1_FETCHECO1_LOCKUNLOCK                        ((uint32_t)(0x8000))
+#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_OFFSET                 ((uint32_t)(0))
+#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_RESET_VALUE            0U
+#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_RESET_MASK             0U
+#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK_SHIFT       0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY   0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_fetcheco1_LockStatus */
+#define IMXDPUV1_FETCHECO1_LOCKSTATUS                        ((uint32_t)(0x8004))
+#define IMXDPUV1_FETCHECO1_LOCKSTATUS_OFFSET                 ((uint32_t)(0x4))
+#define IMXDPUV1_FETCHECO1_LOCKSTATUS_RESET_VALUE            0U
+#define IMXDPUV1_FETCHECO1_LOCKSTATUS_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO1_LOCKSTATUS_LOCKSTATUS_MASK        0x1U
+#define IMXDPUV1_FETCHECO1_LOCKSTATUS_LOCKSTATUS_SHIFT       0U
+#define IMXDPUV1_FETCHECO1_LOCKSTATUS_PRIVILEGESTATUS_MASK   0x10U
+#define IMXDPUV1_FETCHECO1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT  4U
+#define IMXDPUV1_FETCHECO1_LOCKSTATUS_FREEZESTATUS_MASK      0x100U
+#define IMXDPUV1_FETCHECO1_LOCKSTATUS_FREEZESTATUS_SHIFT     8U
+
+/* Register: IMXDPUV1_fetcheco1_StaticControl */
+#define IMXDPUV1_FETCHECO1_STATICCONTROL                     ((uint32_t)(0x8008))
+#define IMXDPUV1_FETCHECO1_STATICCONTROL_OFFSET              ((uint32_t)(0x8))
+#define IMXDPUV1_FETCHECO1_STATICCONTROL_RESET_VALUE         0U
+#define IMXDPUV1_FETCHECO1_STATICCONTROL_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO1_STATICCONTROL_SHDEN_MASK          0x1U
+#define IMXDPUV1_FETCHECO1_STATICCONTROL_SHDEN_SHIFT         0U
+#define IMXDPUV1_FETCHECO1_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U
+#define IMXDPUV1_FETCHECO1_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco1_BurstBufferManagement */
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT             ((uint32_t)(0x800C))
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_OFFSET      ((uint32_t)(0xC))
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U
+/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the
+ * Display Controller. Works also for Blit Engine with marginal performance
+ * impact.  */
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U
+/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit
+ * Engine.  */
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U
+
+/* Register: IMXDPUV1_fetcheco1_BaseAddress0 */
+#define IMXDPUV1_FETCHECO1_BASEADDRESS0                      ((uint32_t)(0x8010))
+#define IMXDPUV1_FETCHECO1_BASEADDRESS0_OFFSET               ((uint32_t)(0x10))
+#define IMXDPUV1_FETCHECO1_BASEADDRESS0_RESET_VALUE          0U
+#define IMXDPUV1_FETCHECO1_BASEADDRESS0_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO1_BASEADDRESS0_BASEADDRESS0_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO1_BASEADDRESS0_BASEADDRESS0_SHIFT   0U
+
+/* Register: IMXDPUV1_fetcheco1_SourceBufferAttributes0 */
+#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0           ((uint32_t)(0x8014))
+#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_OFFSET    ((uint32_t)(0x14))
+#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU
+#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU
+#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U
+#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U
+#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco1_SourceBufferDimension0 */
+#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0            ((uint32_t)(0x8018))
+#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_OFFSET     ((uint32_t)(0x18))
+#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco1_ColorComponentBits0 */
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0               ((uint32_t)(0x801C))
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_OFFSET        ((uint32_t)(0x1C))
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_RESET_VALUE   0x8080808U
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U
+
+/* Register: IMXDPUV1_fetcheco1_ColorComponentShift0 */
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0              ((uint32_t)(0x8020))
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_OFFSET       ((uint32_t)(0x20))
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_RESET_VALUE  0x18100800U
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_RESET_MASK   0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U
+#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_fetcheco1_LayerOffset0 */
+#define IMXDPUV1_FETCHECO1_LAYEROFFSET0                      ((uint32_t)(0x8024))
+#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_OFFSET               ((uint32_t)(0x24))
+#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_RESET_VALUE          0U
+#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_LAYERXOFFSET0_MASK   0x7FFFU
+#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_LAYERXOFFSET0_SHIFT  0U
+#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_LAYERYOFFSET0_MASK   0x7FFF0000U
+#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_LAYERYOFFSET0_SHIFT  16U
+
+/* Register: IMXDPUV1_fetcheco1_ClipWindowOffset0 */
+#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0                 ((uint32_t)(0x8028))
+#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_OFFSET          ((uint32_t)(0x28))
+#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_RESET_VALUE     0U
+#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU
+#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U
+#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco1_ClipWindowDimensions0 */
+#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0             ((uint32_t)(0x802C))
+#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_OFFSET      ((uint32_t)(0x2C))
+#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U
+#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetcheco1_ConstantColor0 */
+#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0                    ((uint32_t)(0x8030))
+#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_OFFSET             ((uint32_t)(0x30))
+#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_RESET_VALUE        0U
+#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU
+#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U
+#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U
+#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTRED0_MASK  0xFF000000U
+#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_fetcheco1_LayerProperty0 */
+#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0                    ((uint32_t)(0x8034))
+#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_OFFSET             ((uint32_t)(0x34))
+#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_RESET_VALUE        0x80000000U
+#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0_MASK     0x30U
+#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0_SHIFT    4U
+/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U
+/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U
+#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U
+#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U
+#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U
+
+/* Register: IMXDPUV1_fetcheco1_FrameDimensions */
+#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS                   ((uint32_t)(0x8038))
+#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_OFFSET            ((uint32_t)(0x38))
+#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_RESET_VALUE       0xEF013FU
+#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_FRAMEWIDTH_MASK   0x3FFFU
+#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT  0U
+#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK  0x3FFF0000U
+#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U
+#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_EMPTYFRAME_MASK   0x80000000U
+#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT  31U
+
+/* Register: IMXDPUV1_fetcheco1_FrameResampling */
+#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING                   ((uint32_t)(0x803C))
+#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_OFFSET            ((uint32_t)(0x3C))
+#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_RESET_VALUE       0x104000U
+#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_STARTX_MASK       0x3FU
+#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_STARTX_SHIFT      0U
+#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_STARTY_MASK       0xFC0U
+#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_STARTY_SHIFT      6U
+#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_DELTAX_MASK       0x3F000U
+#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_DELTAX_SHIFT      12U
+#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_DELTAY_MASK       0xFC0000U
+#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_DELTAY_SHIFT      18U
+#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U
+#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U
+
+/* Register: IMXDPUV1_fetcheco1_Control */
+#define IMXDPUV1_FETCHECO1_CONTROL                           ((uint32_t)(0x8040))
+#define IMXDPUV1_FETCHECO1_CONTROL_OFFSET                    ((uint32_t)(0x40))
+#define IMXDPUV1_FETCHECO1_CONTROL_RESET_VALUE               0x10000U
+#define IMXDPUV1_FETCHECO1_CONTROL_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FETCHECO1_CONTROL_RAWPIXEL_MASK             0x80U
+#define IMXDPUV1_FETCHECO1_CONTROL_RAWPIXEL_SHIFT            7U
+#define IMXDPUV1_FETCHECO1_CONTROL_CLIPCOLOR_MASK            0x10000U
+#define IMXDPUV1_FETCHECO1_CONTROL_CLIPCOLOR_SHIFT           16U
+/* Field Value: CLIPCOLOR__NULL, Null color.  */
+#define IMXDPUV1_FETCHECO1_CONTROL_CLIPCOLOR__NULL           0U
+/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer
+ * (or layer 0 when Fetch unit has one layer only). The color is then the
+ * layer's source or tiling color.  */
+#define IMXDPUV1_FETCHECO1_CONTROL_CLIPCOLOR__LAYER          0x1U
+
+/* Register: IMXDPUV1_fetcheco1_ControlTrigger */
+#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER                    ((uint32_t)(0x8044))
+#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_OFFSET             ((uint32_t)(0x44))
+#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_RESET_VALUE        0U
+#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_RESET_MASK         0xFFFFFFFEU
+#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_SHDTOKGEN_MASK     0x1U
+#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_SHDTOKGEN_SHIFT    0U
+
+/* Register: IMXDPUV1_fetcheco1_Start */
+#define IMXDPUV1_FETCHECO1_START                             ((uint32_t)(0x8048))
+#define IMXDPUV1_FETCHECO1_START_OFFSET                      ((uint32_t)(0x48))
+#define IMXDPUV1_FETCHECO1_START_RESET_VALUE                 0U
+#define IMXDPUV1_FETCHECO1_START_RESET_MASK                  0xFFFFFFFEU
+#define IMXDPUV1_FETCHECO1_START_START_MASK                  0x1U
+#define IMXDPUV1_FETCHECO1_START_START_SHIFT                 0U
+
+/* Register: IMXDPUV1_fetcheco1_FetchType */
+#define IMXDPUV1_FETCHECO1_FETCHTYPE                         ((uint32_t)(0x804C))
+#define IMXDPUV1_FETCHECO1_FETCHTYPE_OFFSET                  ((uint32_t)(0x4C))
+#define IMXDPUV1_FETCHECO1_FETCHTYPE_RESET_VALUE             0U
+#define IMXDPUV1_FETCHECO1_FETCHTYPE_RESET_MASK              0xFFFFFFF0U
+#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE_MASK          0xFU
+#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE_SHIFT         0U
+/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder.  */
+#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__DECODE       0U
+/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers).  */
+#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__LAYER        0x1U
+/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional
+ * plane (8 layers).  */
+#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__WARP         0x2U
+/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha,
+ * chroma and coordinate planes.  */
+#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__ECO          0x3U
+/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and
+ * arbitrary warping.  */
+#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__PERSP        0x4U
+/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping.  */
+#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__ROT          0x5U
+/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced
+ * feature set.  */
+#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__DECODEL      0x6U
+/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers),
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__LAYERL       0x7U
+/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping,
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__ROTL         0x8U
+
+/* Register: IMXDPUV1_fetcheco1_BurstBufferProperties */
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES             ((uint32_t)(0x8050))
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_OFFSET      ((uint32_t)(0x50))
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_RESET_VALUE 0U
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_RESET_MASK  0xFFFFE000U
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U
+#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U
+
+/* Register: IMXDPUV1_fetcheco1_HiddenStatus */
+#define IMXDPUV1_FETCHECO1_HIDDENSTATUS                      ((uint32_t)(0x8054))
+#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_OFFSET               ((uint32_t)(0x54))
+#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_RESET_VALUE          0U
+#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_RESET_MASK           0xFFFF008EU
+#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSBUSY_MASK      0x1U
+#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSBUSY_SHIFT     0U
+#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U
+#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U
+#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSREQUEST_MASK   0x20U
+#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSREQUEST_SHIFT  5U
+#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSCOMPLETE_MASK  0x40U
+#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U
+#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_SHADOWSTATUS_MASK    0xFF00U
+#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_SHADOWSTATUS_SHIFT   8U
+
+/* Register: IMXDPUV1_fetchlayer0_LockUnlock */
+#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK                      ((uint32_t)(0x8400))
+#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_OFFSET               ((uint32_t)(0))
+#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_RESET_VALUE          0U
+#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_RESET_MASK           0U
+#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK_MASK      0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK_SHIFT     0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_fetchlayer0_LockStatus */
+#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS                      ((uint32_t)(0x8404))
+#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_OFFSET               ((uint32_t)(0x4))
+#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_RESET_VALUE          0U
+#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_LOCKSTATUS_MASK      0x1U
+#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_LOCKSTATUS_SHIFT     0U
+#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_FREEZESTATUS_MASK    0x100U
+#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_FREEZESTATUS_SHIFT   8U
+
+/* Register: IMXDPUV1_fetchlayer0_StaticControl */
+#define IMXDPUV1_FETCHLAYER0_STATICCONTROL                   ((uint32_t)(0x8408))
+#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_OFFSET            ((uint32_t)(0x8))
+#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_RESET_VALUE       0xFF000000U
+#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDEN_MASK        0x1U
+#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDEN_SHIFT       0U
+#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U
+#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDLDREQSTICKY_MASK 0xFF000000U
+#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDLDREQSTICKY_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchlayer0_BurstBufferManagement */
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT           ((uint32_t)(0x840C))
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_OFFSET    ((uint32_t)(0xC))
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U
+/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the
+ * Display Controller. Works also for Blit Engine with marginal performance
+ * impact.  */
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U
+/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit
+ * Engine.  */
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U
+
+/* Register: IMXDPUV1_fetchlayer0_BaseAddress0 */
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0                    ((uint32_t)(0x8410))
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_OFFSET             ((uint32_t)(0x10))
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_RESET_VALUE        0U
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_BASEADDRESS0_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_BASEADDRESS0_SHIFT 0U
+
+/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes0 */
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0         ((uint32_t)(0x8414))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_OFFSET  ((uint32_t)(0x14))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension0 */
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0          ((uint32_t)(0x8418))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_OFFSET   ((uint32_t)(0x18))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits0 */
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0             ((uint32_t)(0x841C))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_OFFSET      ((uint32_t)(0x1C))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift0 */
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0            ((uint32_t)(0x8420))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_OFFSET     ((uint32_t)(0x20))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchlayer0_LayerOffset0 */
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0                    ((uint32_t)(0x8424))
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_OFFSET             ((uint32_t)(0x24))
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_RESET_VALUE        0U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset0 */
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0               ((uint32_t)(0x8428))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_OFFSET        ((uint32_t)(0x28))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_RESET_VALUE   0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions0 */
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0           ((uint32_t)(0x842C))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_OFFSET    ((uint32_t)(0x2C))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ConstantColor0 */
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0                  ((uint32_t)(0x8430))
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_OFFSET           ((uint32_t)(0x30))
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_RESET_VALUE      0U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchlayer0_LayerProperty0 */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0                  ((uint32_t)(0x8434))
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_OFFSET           ((uint32_t)(0x34))
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RESET_VALUE      0x80000100U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_PALETTEENABLE0_MASK 0x1U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_PALETTEENABLE0_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0_MASK   0x30U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0_SHIFT  4U
+/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U
+/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U
+/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchlayer0_BaseAddress1 */
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1                    ((uint32_t)(0x8438))
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_OFFSET             ((uint32_t)(0x38))
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_RESET_VALUE        0U
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_BASEADDRESS1_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_BASEADDRESS1_SHIFT 0U
+
+/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes1 */
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1         ((uint32_t)(0x843C))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_OFFSET  ((uint32_t)(0x3C))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_STRIDE1_MASK 0xFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_STRIDE1_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_MASK 0x3F0000U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension1 */
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1          ((uint32_t)(0x8440))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_OFFSET   ((uint32_t)(0x40))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LINEWIDTH1_MASK 0x3FFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LINEWIDTH1_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LINECOUNT1_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LINECOUNT1_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits1 */
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1             ((uint32_t)(0x8444))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_OFFSET      ((uint32_t)(0x44))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_RESET_VALUE 0x8080808U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_MASK 0xFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_MASK 0xF00U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_MASK 0xF0000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSRED1_MASK 0xF000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSRED1_SHIFT 24U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_ITUFORMAT1_MASK 0x80000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_ITUFORMAT1_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift1 */
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1            ((uint32_t)(0x8448))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_OFFSET     ((uint32_t)(0x48))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_MASK 0x1FU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_MASK 0x1F00U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_MASK 0x1F0000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_MASK 0x1F000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchlayer0_LayerOffset1 */
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1                    ((uint32_t)(0x844C))
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_OFFSET             ((uint32_t)(0x4C))
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_RESET_VALUE        0U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_LAYERXOFFSET1_MASK 0x7FFFU
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_LAYERXOFFSET1_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_LAYERYOFFSET1_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_LAYERYOFFSET1_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset1 */
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1               ((uint32_t)(0x8450))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_OFFSET        ((uint32_t)(0x50))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_RESET_VALUE   0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_MASK 0x7FFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions1 */
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1           ((uint32_t)(0x8454))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_OFFSET    ((uint32_t)(0x54))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_RESET_VALUE 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_MASK 0x3FFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ConstantColor1 */
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1                  ((uint32_t)(0x8458))
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_OFFSET           ((uint32_t)(0x58))
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_RESET_VALUE      0U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTALPHA1_MASK 0xFFU
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTALPHA1_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTBLUE1_MASK 0xFF00U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTBLUE1_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTGREEN1_MASK 0xFF0000U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTGREEN1_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTRED1_MASK 0xFF000000U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTRED1_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchlayer0_LayerProperty1 */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1                  ((uint32_t)(0x845C))
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_OFFSET           ((uint32_t)(0x5C))
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RESET_VALUE      0x100U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_PALETTEENABLE1_MASK 0x1U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_PALETTEENABLE1_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1_MASK   0x30U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1_SHIFT  4U
+/* Field Value: TILEMODE1__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE1__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE1__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1__TILE_PAD 0x2U
+/* Field Value: TILEMODE1__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHASRCENABLE1_MASK 0x100U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHASRCENABLE1_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHACONSTENABLE1_MASK 0x200U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHACONSTENABLE1_SHIFT 9U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHATRANSENABLE1_MASK 0x800U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHATRANSENABLE1_SHIFT 11U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHASRCENABLE1_MASK 0x1000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHASRCENABLE1_SHIFT 12U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHACONSTENABLE1_MASK 0x2000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHACONSTENABLE1_SHIFT 13U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHATRANSENABLE1_MASK 0x8000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHATRANSENABLE1_SHIFT 15U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_PREMULCONSTRGB1_MASK 0x10000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_PREMULCONSTRGB1_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1_MASK 0x60000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE1__OFF, No conversion.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1__OFF 0U
+/* Field Value: YUVCONVERSIONMODE1__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE1__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE1__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU709 0x3U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_GAMMAREMOVEENABLE1_MASK 0x100000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_GAMMAREMOVEENABLE1_SHIFT 20U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_CLIPWINDOWENABLE1_MASK 0x40000000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_CLIPWINDOWENABLE1_SHIFT 30U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_SOURCEBUFFERENABLE1_MASK 0x80000000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_SOURCEBUFFERENABLE1_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchlayer0_BaseAddress2 */
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2                    ((uint32_t)(0x8460))
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_OFFSET             ((uint32_t)(0x60))
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_RESET_VALUE        0U
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_BASEADDRESS2_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_BASEADDRESS2_SHIFT 0U
+
+/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes2 */
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2         ((uint32_t)(0x8464))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_OFFSET  ((uint32_t)(0x64))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_STRIDE2_MASK 0xFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_STRIDE2_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_MASK 0x3F0000U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension2 */
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2          ((uint32_t)(0x8468))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_OFFSET   ((uint32_t)(0x68))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LINEWIDTH2_MASK 0x3FFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LINEWIDTH2_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LINECOUNT2_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LINECOUNT2_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits2 */
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2             ((uint32_t)(0x846C))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_OFFSET      ((uint32_t)(0x6C))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_RESET_VALUE 0x8080808U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_MASK 0xFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_MASK 0xF00U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_MASK 0xF0000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSRED2_MASK 0xF000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSRED2_SHIFT 24U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_ITUFORMAT2_MASK 0x80000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_ITUFORMAT2_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift2 */
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2            ((uint32_t)(0x8470))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_OFFSET     ((uint32_t)(0x70))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_MASK 0x1FU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_MASK 0x1F00U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_MASK 0x1F0000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_MASK 0x1F000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchlayer0_LayerOffset2 */
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2                    ((uint32_t)(0x8474))
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_OFFSET             ((uint32_t)(0x74))
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_RESET_VALUE        0U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_LAYERXOFFSET2_MASK 0x7FFFU
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_LAYERXOFFSET2_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_LAYERYOFFSET2_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_LAYERYOFFSET2_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset2 */
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2               ((uint32_t)(0x8478))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_OFFSET        ((uint32_t)(0x78))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_RESET_VALUE   0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_MASK 0x7FFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions2 */
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2           ((uint32_t)(0x847C))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_OFFSET    ((uint32_t)(0x7C))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_RESET_VALUE 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_MASK 0x3FFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ConstantColor2 */
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2                  ((uint32_t)(0x8480))
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_OFFSET           ((uint32_t)(0x80))
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_RESET_VALUE      0U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTALPHA2_MASK 0xFFU
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTALPHA2_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTBLUE2_MASK 0xFF00U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTBLUE2_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTGREEN2_MASK 0xFF0000U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTGREEN2_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTRED2_MASK 0xFF000000U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTRED2_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchlayer0_LayerProperty2 */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2                  ((uint32_t)(0x8484))
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_OFFSET           ((uint32_t)(0x84))
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RESET_VALUE      0x100U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_PALETTEENABLE2_MASK 0x1U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_PALETTEENABLE2_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2_MASK   0x30U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2_SHIFT  4U
+/* Field Value: TILEMODE2__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE2__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE2__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2__TILE_PAD 0x2U
+/* Field Value: TILEMODE2__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHASRCENABLE2_MASK 0x100U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHASRCENABLE2_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHACONSTENABLE2_MASK 0x200U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHACONSTENABLE2_SHIFT 9U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHATRANSENABLE2_MASK 0x800U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHATRANSENABLE2_SHIFT 11U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHASRCENABLE2_MASK 0x1000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHASRCENABLE2_SHIFT 12U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHACONSTENABLE2_MASK 0x2000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHACONSTENABLE2_SHIFT 13U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHATRANSENABLE2_MASK 0x8000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHATRANSENABLE2_SHIFT 15U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_PREMULCONSTRGB2_MASK 0x10000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_PREMULCONSTRGB2_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2_MASK 0x60000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE2__OFF, No conversion.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2__OFF 0U
+/* Field Value: YUVCONVERSIONMODE2__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE2__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE2__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU709 0x3U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_GAMMAREMOVEENABLE2_MASK 0x100000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_GAMMAREMOVEENABLE2_SHIFT 20U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_CLIPWINDOWENABLE2_MASK 0x40000000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_CLIPWINDOWENABLE2_SHIFT 30U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_SOURCEBUFFERENABLE2_MASK 0x80000000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_SOURCEBUFFERENABLE2_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchlayer0_BaseAddress3 */
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3                    ((uint32_t)(0x8488))
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_OFFSET             ((uint32_t)(0x88))
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_RESET_VALUE        0U
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_BASEADDRESS3_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_BASEADDRESS3_SHIFT 0U
+
+/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes3 */
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3         ((uint32_t)(0x848C))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_OFFSET  ((uint32_t)(0x8C))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_STRIDE3_MASK 0xFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_STRIDE3_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_MASK 0x3F0000U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension3 */
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3          ((uint32_t)(0x8490))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_OFFSET   ((uint32_t)(0x90))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LINEWIDTH3_MASK 0x3FFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LINEWIDTH3_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LINECOUNT3_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LINECOUNT3_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits3 */
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3             ((uint32_t)(0x8494))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_OFFSET      ((uint32_t)(0x94))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_RESET_VALUE 0x8080808U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_MASK 0xFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_MASK 0xF00U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_MASK 0xF0000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSRED3_MASK 0xF000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSRED3_SHIFT 24U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_ITUFORMAT3_MASK 0x80000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_ITUFORMAT3_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift3 */
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3            ((uint32_t)(0x8498))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_OFFSET     ((uint32_t)(0x98))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_MASK 0x1FU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_MASK 0x1F00U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_MASK 0x1F0000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_MASK 0x1F000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchlayer0_LayerOffset3 */
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3                    ((uint32_t)(0x849C))
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_OFFSET             ((uint32_t)(0x9C))
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_RESET_VALUE        0U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_LAYERXOFFSET3_MASK 0x7FFFU
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_LAYERXOFFSET3_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_LAYERYOFFSET3_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_LAYERYOFFSET3_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset3 */
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3               ((uint32_t)(0x84A0))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_OFFSET        ((uint32_t)(0xA0))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_RESET_VALUE   0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_MASK 0x7FFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions3 */
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3           ((uint32_t)(0x84A4))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_OFFSET    ((uint32_t)(0xA4))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_RESET_VALUE 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_MASK 0x3FFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ConstantColor3 */
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3                  ((uint32_t)(0x84A8))
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_OFFSET           ((uint32_t)(0xA8))
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_RESET_VALUE      0U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTALPHA3_MASK 0xFFU
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTALPHA3_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTBLUE3_MASK 0xFF00U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTBLUE3_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTGREEN3_MASK 0xFF0000U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTGREEN3_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTRED3_MASK 0xFF000000U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTRED3_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchlayer0_LayerProperty3 */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3                  ((uint32_t)(0x84AC))
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_OFFSET           ((uint32_t)(0xAC))
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RESET_VALUE      0x100U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_PALETTEENABLE3_MASK 0x1U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_PALETTEENABLE3_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3_MASK   0x30U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3_SHIFT  4U
+/* Field Value: TILEMODE3__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE3__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE3__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3__TILE_PAD 0x2U
+/* Field Value: TILEMODE3__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHASRCENABLE3_MASK 0x100U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHASRCENABLE3_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHACONSTENABLE3_MASK 0x200U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHACONSTENABLE3_SHIFT 9U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHATRANSENABLE3_MASK 0x800U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHATRANSENABLE3_SHIFT 11U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHASRCENABLE3_MASK 0x1000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHASRCENABLE3_SHIFT 12U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHACONSTENABLE3_MASK 0x2000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHACONSTENABLE3_SHIFT 13U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHATRANSENABLE3_MASK 0x8000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHATRANSENABLE3_SHIFT 15U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_PREMULCONSTRGB3_MASK 0x10000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_PREMULCONSTRGB3_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3_MASK 0x60000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE3__OFF, No conversion.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3__OFF 0U
+/* Field Value: YUVCONVERSIONMODE3__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE3__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE3__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU709 0x3U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_GAMMAREMOVEENABLE3_MASK 0x100000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_GAMMAREMOVEENABLE3_SHIFT 20U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_CLIPWINDOWENABLE3_MASK 0x40000000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_CLIPWINDOWENABLE3_SHIFT 30U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_SOURCEBUFFERENABLE3_MASK 0x80000000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_SOURCEBUFFERENABLE3_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchlayer0_BaseAddress4 */
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4                    ((uint32_t)(0x84B0))
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_OFFSET             ((uint32_t)(0xB0))
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_RESET_VALUE        0U
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_BASEADDRESS4_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_BASEADDRESS4_SHIFT 0U
+
+/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes4 */
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4         ((uint32_t)(0x84B4))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_OFFSET  ((uint32_t)(0xB4))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_STRIDE4_MASK 0xFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_STRIDE4_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_MASK 0x3F0000U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension4 */
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4          ((uint32_t)(0x84B8))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_OFFSET   ((uint32_t)(0xB8))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LINEWIDTH4_MASK 0x3FFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LINEWIDTH4_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LINECOUNT4_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LINECOUNT4_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits4 */
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4             ((uint32_t)(0x84BC))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_OFFSET      ((uint32_t)(0xBC))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_RESET_VALUE 0x8080808U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_MASK 0xFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_MASK 0xF00U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_MASK 0xF0000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSRED4_MASK 0xF000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSRED4_SHIFT 24U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_ITUFORMAT4_MASK 0x80000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_ITUFORMAT4_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift4 */
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4            ((uint32_t)(0x84C0))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_OFFSET     ((uint32_t)(0xC0))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_MASK 0x1FU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_MASK 0x1F00U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_MASK 0x1F0000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_MASK 0x1F000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchlayer0_LayerOffset4 */
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4                    ((uint32_t)(0x84C4))
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_OFFSET             ((uint32_t)(0xC4))
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_RESET_VALUE        0U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_LAYERXOFFSET4_MASK 0x7FFFU
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_LAYERXOFFSET4_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_LAYERYOFFSET4_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_LAYERYOFFSET4_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset4 */
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4               ((uint32_t)(0x84C8))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_OFFSET        ((uint32_t)(0xC8))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_RESET_VALUE   0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_MASK 0x7FFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions4 */
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4           ((uint32_t)(0x84CC))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_OFFSET    ((uint32_t)(0xCC))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_RESET_VALUE 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_MASK 0x3FFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ConstantColor4 */
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4                  ((uint32_t)(0x84D0))
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_OFFSET           ((uint32_t)(0xD0))
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_RESET_VALUE      0U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTALPHA4_MASK 0xFFU
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTALPHA4_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTBLUE4_MASK 0xFF00U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTBLUE4_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTGREEN4_MASK 0xFF0000U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTGREEN4_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTRED4_MASK 0xFF000000U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTRED4_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchlayer0_LayerProperty4 */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4                  ((uint32_t)(0x84D4))
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_OFFSET           ((uint32_t)(0xD4))
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RESET_VALUE      0x100U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_PALETTEENABLE4_MASK 0x1U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_PALETTEENABLE4_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4_MASK   0x30U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4_SHIFT  4U
+/* Field Value: TILEMODE4__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE4__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE4__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4__TILE_PAD 0x2U
+/* Field Value: TILEMODE4__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHASRCENABLE4_MASK 0x100U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHASRCENABLE4_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHACONSTENABLE4_MASK 0x200U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHACONSTENABLE4_SHIFT 9U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHATRANSENABLE4_MASK 0x800U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHATRANSENABLE4_SHIFT 11U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHASRCENABLE4_MASK 0x1000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHASRCENABLE4_SHIFT 12U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHACONSTENABLE4_MASK 0x2000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHACONSTENABLE4_SHIFT 13U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHATRANSENABLE4_MASK 0x8000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHATRANSENABLE4_SHIFT 15U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_PREMULCONSTRGB4_MASK 0x10000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_PREMULCONSTRGB4_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4_MASK 0x60000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE4__OFF, No conversion.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4__OFF 0U
+/* Field Value: YUVCONVERSIONMODE4__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE4__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE4__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU709 0x3U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_GAMMAREMOVEENABLE4_MASK 0x100000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_GAMMAREMOVEENABLE4_SHIFT 20U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_CLIPWINDOWENABLE4_MASK 0x40000000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_CLIPWINDOWENABLE4_SHIFT 30U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_SOURCEBUFFERENABLE4_MASK 0x80000000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_SOURCEBUFFERENABLE4_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchlayer0_BaseAddress5 */
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5                    ((uint32_t)(0x84D8))
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_OFFSET             ((uint32_t)(0xD8))
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_RESET_VALUE        0U
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_BASEADDRESS5_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_BASEADDRESS5_SHIFT 0U
+
+/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes5 */
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5         ((uint32_t)(0x84DC))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_OFFSET  ((uint32_t)(0xDC))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_STRIDE5_MASK 0xFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_STRIDE5_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_MASK 0x3F0000U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension5 */
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5          ((uint32_t)(0x84E0))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_OFFSET   ((uint32_t)(0xE0))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LINEWIDTH5_MASK 0x3FFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LINEWIDTH5_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LINECOUNT5_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LINECOUNT5_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits5 */
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5             ((uint32_t)(0x84E4))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_OFFSET      ((uint32_t)(0xE4))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_RESET_VALUE 0x8080808U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_MASK 0xFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_MASK 0xF00U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_MASK 0xF0000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSRED5_MASK 0xF000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSRED5_SHIFT 24U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_ITUFORMAT5_MASK 0x80000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_ITUFORMAT5_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift5 */
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5            ((uint32_t)(0x84E8))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_OFFSET     ((uint32_t)(0xE8))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_MASK 0x1FU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_MASK 0x1F00U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_MASK 0x1F0000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_MASK 0x1F000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchlayer0_LayerOffset5 */
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5                    ((uint32_t)(0x84EC))
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_OFFSET             ((uint32_t)(0xEC))
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_RESET_VALUE        0U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_LAYERXOFFSET5_MASK 0x7FFFU
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_LAYERXOFFSET5_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_LAYERYOFFSET5_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_LAYERYOFFSET5_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset5 */
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5               ((uint32_t)(0x84F0))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_OFFSET        ((uint32_t)(0xF0))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_RESET_VALUE   0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_MASK 0x7FFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions5 */
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5           ((uint32_t)(0x84F4))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_OFFSET    ((uint32_t)(0xF4))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_RESET_VALUE 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_MASK 0x3FFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ConstantColor5 */
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5                  ((uint32_t)(0x84F8))
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_OFFSET           ((uint32_t)(0xF8))
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_RESET_VALUE      0U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTALPHA5_MASK 0xFFU
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTALPHA5_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTBLUE5_MASK 0xFF00U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTBLUE5_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTGREEN5_MASK 0xFF0000U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTGREEN5_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTRED5_MASK 0xFF000000U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTRED5_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchlayer0_LayerProperty5 */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5                  ((uint32_t)(0x84FC))
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_OFFSET           ((uint32_t)(0xFC))
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RESET_VALUE      0x100U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_PALETTEENABLE5_MASK 0x1U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_PALETTEENABLE5_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5_MASK   0x30U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5_SHIFT  4U
+/* Field Value: TILEMODE5__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE5__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE5__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5__TILE_PAD 0x2U
+/* Field Value: TILEMODE5__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHASRCENABLE5_MASK 0x100U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHASRCENABLE5_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHACONSTENABLE5_MASK 0x200U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHACONSTENABLE5_SHIFT 9U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHATRANSENABLE5_MASK 0x800U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHATRANSENABLE5_SHIFT 11U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHASRCENABLE5_MASK 0x1000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHASRCENABLE5_SHIFT 12U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHACONSTENABLE5_MASK 0x2000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHACONSTENABLE5_SHIFT 13U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHATRANSENABLE5_MASK 0x8000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHATRANSENABLE5_SHIFT 15U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_PREMULCONSTRGB5_MASK 0x10000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_PREMULCONSTRGB5_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5_MASK 0x60000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE5__OFF, No conversion.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5__OFF 0U
+/* Field Value: YUVCONVERSIONMODE5__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE5__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE5__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU709 0x3U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_GAMMAREMOVEENABLE5_MASK 0x100000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_GAMMAREMOVEENABLE5_SHIFT 20U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_CLIPWINDOWENABLE5_MASK 0x40000000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_CLIPWINDOWENABLE5_SHIFT 30U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_SOURCEBUFFERENABLE5_MASK 0x80000000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_SOURCEBUFFERENABLE5_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchlayer0_BaseAddress6 */
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6                    ((uint32_t)(0x8500))
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_OFFSET             ((uint32_t)(0x100))
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_RESET_VALUE        0U
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_BASEADDRESS6_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_BASEADDRESS6_SHIFT 0U
+
+/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes6 */
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6         ((uint32_t)(0x8504))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_OFFSET  ((uint32_t)(0x104))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_STRIDE6_MASK 0xFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_STRIDE6_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_MASK 0x3F0000U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension6 */
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6          ((uint32_t)(0x8508))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_OFFSET   ((uint32_t)(0x108))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LINEWIDTH6_MASK 0x3FFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LINEWIDTH6_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LINECOUNT6_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LINECOUNT6_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits6 */
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6             ((uint32_t)(0x850C))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_OFFSET      ((uint32_t)(0x10C))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_RESET_VALUE 0x8080808U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_MASK 0xFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_MASK 0xF00U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_MASK 0xF0000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSRED6_MASK 0xF000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSRED6_SHIFT 24U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_ITUFORMAT6_MASK 0x80000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_ITUFORMAT6_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift6 */
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6            ((uint32_t)(0x8510))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_OFFSET     ((uint32_t)(0x110))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_MASK 0x1FU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_MASK 0x1F00U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_MASK 0x1F0000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_MASK 0x1F000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchlayer0_LayerOffset6 */
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6                    ((uint32_t)(0x8514))
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_OFFSET             ((uint32_t)(0x114))
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_RESET_VALUE        0U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_LAYERXOFFSET6_MASK 0x7FFFU
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_LAYERXOFFSET6_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_LAYERYOFFSET6_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_LAYERYOFFSET6_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset6 */
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6               ((uint32_t)(0x8518))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_OFFSET        ((uint32_t)(0x118))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_RESET_VALUE   0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_MASK 0x7FFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions6 */
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6           ((uint32_t)(0x851C))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_OFFSET    ((uint32_t)(0x11C))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_RESET_VALUE 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_MASK 0x3FFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ConstantColor6 */
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6                  ((uint32_t)(0x8520))
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_OFFSET           ((uint32_t)(0x120))
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_RESET_VALUE      0U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTALPHA6_MASK 0xFFU
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTALPHA6_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTBLUE6_MASK 0xFF00U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTBLUE6_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTGREEN6_MASK 0xFF0000U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTGREEN6_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTRED6_MASK 0xFF000000U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTRED6_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchlayer0_LayerProperty6 */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6                  ((uint32_t)(0x8524))
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_OFFSET           ((uint32_t)(0x124))
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RESET_VALUE      0x100U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_PALETTEENABLE6_MASK 0x1U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_PALETTEENABLE6_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6_MASK   0x30U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6_SHIFT  4U
+/* Field Value: TILEMODE6__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE6__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE6__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6__TILE_PAD 0x2U
+/* Field Value: TILEMODE6__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHASRCENABLE6_MASK 0x100U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHASRCENABLE6_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHACONSTENABLE6_MASK 0x200U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHACONSTENABLE6_SHIFT 9U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHATRANSENABLE6_MASK 0x800U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHATRANSENABLE6_SHIFT 11U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHASRCENABLE6_MASK 0x1000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHASRCENABLE6_SHIFT 12U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHACONSTENABLE6_MASK 0x2000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHACONSTENABLE6_SHIFT 13U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHATRANSENABLE6_MASK 0x8000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHATRANSENABLE6_SHIFT 15U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_PREMULCONSTRGB6_MASK 0x10000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_PREMULCONSTRGB6_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6_MASK 0x60000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE6__OFF, No conversion.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6__OFF 0U
+/* Field Value: YUVCONVERSIONMODE6__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE6__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE6__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU709 0x3U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_GAMMAREMOVEENABLE6_MASK 0x100000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_GAMMAREMOVEENABLE6_SHIFT 20U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_CLIPWINDOWENABLE6_MASK 0x40000000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_CLIPWINDOWENABLE6_SHIFT 30U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_SOURCEBUFFERENABLE6_MASK 0x80000000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_SOURCEBUFFERENABLE6_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchlayer0_BaseAddress7 */
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7                    ((uint32_t)(0x8528))
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_OFFSET             ((uint32_t)(0x128))
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_RESET_VALUE        0U
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_BASEADDRESS7_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_BASEADDRESS7_SHIFT 0U
+
+/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes7 */
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7         ((uint32_t)(0x852C))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_OFFSET  ((uint32_t)(0x12C))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_RESET_VALUE 0x200003U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_STRIDE7_MASK 0xFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_STRIDE7_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_MASK 0x3F0000U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension7 */
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7          ((uint32_t)(0x8530))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_OFFSET   ((uint32_t)(0x130))
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_RESET_VALUE 0x3FFF3FFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LINEWIDTH7_MASK 0x3FFFU
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LINEWIDTH7_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LINECOUNT7_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LINECOUNT7_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits7 */
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7             ((uint32_t)(0x8534))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_OFFSET      ((uint32_t)(0x134))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_RESET_VALUE 0x8080808U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_RESET_MASK  0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_MASK 0xFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_MASK 0xF00U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_MASK 0xF0000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSRED7_MASK 0xF000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSRED7_SHIFT 24U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_ITUFORMAT7_MASK 0x80000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_ITUFORMAT7_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift7 */
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7            ((uint32_t)(0x8538))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_OFFSET     ((uint32_t)(0x138))
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_RESET_VALUE 0x18100800U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_MASK 0x1FU
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_MASK 0x1F00U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_MASK 0x1F0000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_MASK 0x1F000000U
+#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchlayer0_LayerOffset7 */
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7                    ((uint32_t)(0x853C))
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_OFFSET             ((uint32_t)(0x13C))
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_RESET_VALUE        0U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_LAYERXOFFSET7_MASK 0x7FFFU
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_LAYERXOFFSET7_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_LAYERYOFFSET7_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_LAYERYOFFSET7_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset7 */
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7               ((uint32_t)(0x8540))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_OFFSET        ((uint32_t)(0x140))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_RESET_VALUE   0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_MASK 0x7FFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_MASK 0x7FFF0000U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions7 */
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7           ((uint32_t)(0x8544))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_OFFSET    ((uint32_t)(0x144))
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_RESET_VALUE 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_RESET_MASK 0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_MASK 0x3FFFU
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_SHIFT 16U
+
+/* Register: IMXDPUV1_fetchlayer0_ConstantColor7 */
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7                  ((uint32_t)(0x8548))
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_OFFSET           ((uint32_t)(0x148))
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_RESET_VALUE      0U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTALPHA7_MASK 0xFFU
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTALPHA7_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTBLUE7_MASK 0xFF00U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTBLUE7_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTGREEN7_MASK 0xFF0000U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTGREEN7_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTRED7_MASK 0xFF000000U
+#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTRED7_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchlayer0_LayerProperty7 */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7                  ((uint32_t)(0x854C))
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_OFFSET           ((uint32_t)(0x14C))
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RESET_VALUE      0x100U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_PALETTEENABLE7_MASK 0x1U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_PALETTEENABLE7_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7_MASK   0x30U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7_SHIFT  4U
+/* Field Value: TILEMODE7__TILE_FILL_ZERO, Use zero value  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7__TILE_FILL_ZERO 0U
+/* Field Value: TILEMODE7__TILE_FILL_CONSTANT, Use constant color register
+ * value  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7__TILE_FILL_CONSTANT 0x1U
+/* Field Value: TILEMODE7__TILE_PAD, Use closest pixel from source buffer.
+ * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable
+ * is 0.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7__TILE_PAD 0x2U
+/* Field Value: TILEMODE7__TILE_PAD_ZERO, Use closest pixel from source buffer
+ * but zero for alpha component. Must not be used for DECODE or YUV422
+ * operations or when SourceBufferEnable is 0.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7__TILE_PAD_ZERO 0x3U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHASRCENABLE7_MASK 0x100U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHASRCENABLE7_SHIFT 8U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHACONSTENABLE7_MASK 0x200U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHACONSTENABLE7_SHIFT 9U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHATRANSENABLE7_MASK 0x800U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHATRANSENABLE7_SHIFT 11U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHASRCENABLE7_MASK 0x1000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHASRCENABLE7_SHIFT 12U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHACONSTENABLE7_MASK 0x2000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHACONSTENABLE7_SHIFT 13U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHATRANSENABLE7_MASK 0x8000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHATRANSENABLE7_SHIFT 15U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_PREMULCONSTRGB7_MASK 0x10000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_PREMULCONSTRGB7_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7_MASK 0x60000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7_SHIFT 17U
+/* Field Value: YUVCONVERSIONMODE7__OFF, No conversion.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7__OFF 0U
+/* Field Value: YUVCONVERSIONMODE7__ITU601, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.601-6 (standard definition TV).
+ * Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601 0x1U
+/* Field Value: YUVCONVERSIONMODE7__ITU601_FR, Conversion from YCbCr (YUV)
+ * to RGB according to ITU recommendation BT.601-6, but assuming full range
+ * YUV inputs (0..255). Most typically used for computer graphics (e.g.
+ * for JPEG encoding).  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601_FR 0x2U
+/* Field Value: YUVCONVERSIONMODE7__ITU709, Conversion from YCbCr (YUV) to
+ * RGB according to ITU recommendation BT.709-5 part 2 (high definition
+ * TV). Input range is 16..235 for Y and 16..240 for U/V.  */
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU709 0x3U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_GAMMAREMOVEENABLE7_MASK 0x100000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_GAMMAREMOVEENABLE7_SHIFT 20U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_CLIPWINDOWENABLE7_MASK 0x40000000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_CLIPWINDOWENABLE7_SHIFT 30U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_SOURCEBUFFERENABLE7_MASK 0x80000000U
+#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_SOURCEBUFFERENABLE7_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchlayer0_FrameDimensions */
+#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS                 ((uint32_t)(0x8550))
+#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_OFFSET          ((uint32_t)(0x150))
+#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_RESET_VALUE     0xEF013FU
+#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU
+#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U
+#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U
+#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U
+#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U
+
+/* Register: IMXDPUV1_fetchlayer0_FrameResampling */
+#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING                 ((uint32_t)(0x8554))
+#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_OFFSET          ((uint32_t)(0x154))
+#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_RESET_VALUE     0x104000U
+#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_STARTX_MASK     0x3FU
+#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_STARTX_SHIFT    0U
+#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_STARTY_MASK     0xFC0U
+#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_STARTY_SHIFT    6U
+#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_DELTAX_MASK     0x3F000U
+#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_DELTAX_SHIFT    12U
+#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_DELTAY_MASK     0xFC0000U
+#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_DELTAY_SHIFT    18U
+#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U
+#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U
+
+/* Register: IMXDPUV1_fetchlayer0_Control */
+#define IMXDPUV1_FETCHLAYER0_CONTROL                         ((uint32_t)(0x8558))
+#define IMXDPUV1_FETCHLAYER0_CONTROL_OFFSET                  ((uint32_t)(0x158))
+#define IMXDPUV1_FETCHLAYER0_CONTROL_RESET_VALUE             0x10700U
+#define IMXDPUV1_FETCHLAYER0_CONTROL_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_CONTROL_RAWPIXEL_MASK           0x80U
+#define IMXDPUV1_FETCHLAYER0_CONTROL_RAWPIXEL_SHIFT          7U
+#define IMXDPUV1_FETCHLAYER0_CONTROL_PALETTEIDXWIDTH_MASK    0x700U
+#define IMXDPUV1_FETCHLAYER0_CONTROL_PALETTEIDXWIDTH_SHIFT   8U
+#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPCOLOR_MASK          0x10000U
+#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPCOLOR_SHIFT         16U
+/* Field Value: CLIPCOLOR__NULL, Null color.  */
+#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPCOLOR__NULL         0U
+/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer
+ * (or layer 0 when Fetch unit has one layer only). The color is then the
+ * layer's source or tiling color.  */
+#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPCOLOR__LAYER        0x1U
+#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPLAYER_MASK          0xE0000U
+#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPLAYER_SHIFT         17U
+
+/* Register: IMXDPUV1_fetchlayer0_TriggerEnable */
+#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE                   ((uint32_t)(0x855C))
+#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_OFFSET            ((uint32_t)(0x15C))
+#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_RESET_VALUE       0U
+#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_SHDLDREQ_MASK     0xFFU
+#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_SHDLDREQ_SHIFT    0U
+
+/* Register: IMXDPUV1_fetchlayer0_ControlTrigger */
+#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER                  ((uint32_t)(0x8560))
+#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_OFFSET           ((uint32_t)(0x160))
+#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_RESET_VALUE      0U
+#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_RESET_MASK       0xFFFFFFFEU
+#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_SHDTOKGEN_MASK   0x1U
+#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_SHDTOKGEN_SHIFT  0U
+
+/* Register: IMXDPUV1_fetchlayer0_Start */
+#define IMXDPUV1_FETCHLAYER0_START                           ((uint32_t)(0x8564))
+#define IMXDPUV1_FETCHLAYER0_START_OFFSET                    ((uint32_t)(0x164))
+#define IMXDPUV1_FETCHLAYER0_START_RESET_VALUE               0U
+#define IMXDPUV1_FETCHLAYER0_START_RESET_MASK                0xFFFFFFFEU
+#define IMXDPUV1_FETCHLAYER0_START_START_MASK                0x1U
+#define IMXDPUV1_FETCHLAYER0_START_START_SHIFT               0U
+
+/* Register: IMXDPUV1_fetchlayer0_FetchType */
+#define IMXDPUV1_FETCHLAYER0_FETCHTYPE                       ((uint32_t)(0x8568))
+#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_OFFSET                ((uint32_t)(0x168))
+#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_RESET_VALUE           0U
+#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_RESET_MASK            0xFFFFFFF0U
+#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE_MASK        0xFU
+#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE_SHIFT       0U
+/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder.  */
+#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__DECODE     0U
+/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers).  */
+#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__LAYER      0x1U
+/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional
+ * plane (8 layers).  */
+#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__WARP       0x2U
+/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha,
+ * chroma and coordinate planes.  */
+#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__ECO        0x3U
+/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and
+ * arbitrary warping.  */
+#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__PERSP      0x4U
+/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping.  */
+#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__ROT        0x5U
+/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced
+ * feature set.  */
+#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__DECODEL    0x6U
+/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers),
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__LAYERL     0x7U
+/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping,
+ * reduced feature set.  */
+#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__ROTL       0x8U
+
+/* Register: IMXDPUV1_fetchlayer0_BurstBufferProperties */
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES           ((uint32_t)(0x856C))
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_OFFSET    ((uint32_t)(0x16C))
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_RESET_VALUE 0U
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U
+#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U
+
+/* Register: IMXDPUV1_fetchlayer0_Status */
+#define IMXDPUV1_FETCHLAYER0_STATUS                          ((uint32_t)(0x8570))
+#define IMXDPUV1_FETCHLAYER0_STATUS_OFFSET                   ((uint32_t)(0x170))
+#define IMXDPUV1_FETCHLAYER0_STATUS_RESET_VALUE              0U
+#define IMXDPUV1_FETCHLAYER0_STATUS_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_STATUS_WRITETIMEOUT_MASK        0x1U
+#define IMXDPUV1_FETCHLAYER0_STATUS_WRITETIMEOUT_SHIFT       0U
+#define IMXDPUV1_FETCHLAYER0_STATUS_READTIMEOUT_MASK         0x10U
+#define IMXDPUV1_FETCHLAYER0_STATUS_READTIMEOUT_SHIFT        4U
+
+/* Register: IMXDPUV1_fetchlayer0_HiddenStatus */
+#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS                    ((uint32_t)(0x8574))
+#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_OFFSET             ((uint32_t)(0x174))
+#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_RESET_VALUE        0U
+#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_RESET_MASK         0xFFFF008EU
+#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSBUSY_MASK    0x1U
+#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSBUSY_SHIFT   0U
+#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U
+#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U
+#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U
+#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U
+#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U
+#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U
+#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_SHADOWSTATUS_MASK  0xFF00U
+#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U
+
+/* Register: IMXDPUV1_fetchlayer0_ColorPalette */
+#define IMXDPUV1_FETCHLAYER0_COLORPALETTE                    ((uint32_t)(0x8800))
+#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_OFFSET             ((uint32_t)(0))
+#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_RESET_VALUE        0U
+#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_RESET_MASK         0xFF000000U
+#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_COLORPALETTE_MASK  0xFFFFFFU
+#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_COLORPALETTE_SHIFT 0U
+
+/* Register: IMXDPUV1_matrix4_LockUnlock */
+#define IMXDPUV1_MATRIX4_LOCKUNLOCK                          ((uint32_t)(0x8C00))
+#define IMXDPUV1_MATRIX4_LOCKUNLOCK_OFFSET                   ((uint32_t)(0))
+#define IMXDPUV1_MATRIX4_LOCKUNLOCK_RESET_VALUE              0U
+#define IMXDPUV1_MATRIX4_LOCKUNLOCK_RESET_MASK               0U
+#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK_MASK          0xFFFFFFFFU
+#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK_SHIFT         0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY     0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY   0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY   0xFBE8B1E6U
+
+/* Register: IMXDPUV1_matrix4_LockStatus */
+#define IMXDPUV1_MATRIX4_LOCKSTATUS                          ((uint32_t)(0x8C04))
+#define IMXDPUV1_MATRIX4_LOCKSTATUS_OFFSET                   ((uint32_t)(0x4))
+#define IMXDPUV1_MATRIX4_LOCKSTATUS_RESET_VALUE              0U
+#define IMXDPUV1_MATRIX4_LOCKSTATUS_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_MATRIX4_LOCKSTATUS_LOCKSTATUS_MASK          0x1U
+#define IMXDPUV1_MATRIX4_LOCKSTATUS_LOCKSTATUS_SHIFT         0U
+#define IMXDPUV1_MATRIX4_LOCKSTATUS_PRIVILEGESTATUS_MASK     0x10U
+#define IMXDPUV1_MATRIX4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT    4U
+#define IMXDPUV1_MATRIX4_LOCKSTATUS_FREEZESTATUS_MASK        0x100U
+#define IMXDPUV1_MATRIX4_LOCKSTATUS_FREEZESTATUS_SHIFT       8U
+
+/* Register: IMXDPUV1_matrix4_StaticControl */
+#define IMXDPUV1_MATRIX4_STATICCONTROL                       ((uint32_t)(0x8C08))
+#define IMXDPUV1_MATRIX4_STATICCONTROL_OFFSET                ((uint32_t)(0x8))
+#define IMXDPUV1_MATRIX4_STATICCONTROL_RESET_VALUE           0U
+#define IMXDPUV1_MATRIX4_STATICCONTROL_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_MATRIX4_STATICCONTROL_SHDEN_MASK            0x1U
+#define IMXDPUV1_MATRIX4_STATICCONTROL_SHDEN_SHIFT           0U
+
+/* Register: IMXDPUV1_matrix4_Control */
+#define IMXDPUV1_MATRIX4_CONTROL                             ((uint32_t)(0x8C0C))
+#define IMXDPUV1_MATRIX4_CONTROL_OFFSET                      ((uint32_t)(0xC))
+#define IMXDPUV1_MATRIX4_CONTROL_RESET_VALUE                 0U
+#define IMXDPUV1_MATRIX4_CONTROL_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_MATRIX4_CONTROL_MODE_MASK                   0x3U
+#define IMXDPUV1_MATRIX4_CONTROL_MODE_SHIFT                  0U
+/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed  */
+#define IMXDPUV1_MATRIX4_CONTROL_MODE__NEUTRAL               0U
+/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied
+ * with matrix values  */
+#define IMXDPUV1_MATRIX4_CONTROL_MODE__MATRIX                0x1U
+/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input
+ * color is multiplied with input alpha  */
+#define IMXDPUV1_MATRIX4_CONTROL_MODE__PREMUL                0x2U
+/* Field Value: MODE__RSVD, Reserved, do not use  */
+#define IMXDPUV1_MATRIX4_CONTROL_MODE__RSVD                  0x3U
+#define IMXDPUV1_MATRIX4_CONTROL_ALPHAMASK_MASK              0x10U
+#define IMXDPUV1_MATRIX4_CONTROL_ALPHAMASK_SHIFT             4U
+#define IMXDPUV1_MATRIX4_CONTROL_ALPHAINVERT_MASK            0x20U
+#define IMXDPUV1_MATRIX4_CONTROL_ALPHAINVERT_SHIFT           5U
+
+/* Register: IMXDPUV1_matrix4_Red0 */
+#define IMXDPUV1_MATRIX4_RED0                                ((uint32_t)(0x8C10))
+#define IMXDPUV1_MATRIX4_RED0_OFFSET                         ((uint32_t)(0x10))
+#define IMXDPUV1_MATRIX4_RED0_RESET_VALUE                    0x400U
+#define IMXDPUV1_MATRIX4_RED0_RESET_MASK                     0xFFFFFFFFU
+#define IMXDPUV1_MATRIX4_RED0_A11_MASK                       0x1FFFU
+#define IMXDPUV1_MATRIX4_RED0_A11_SHIFT                      0U
+#define IMXDPUV1_MATRIX4_RED0_A12_MASK                       0x1FFF0000U
+#define IMXDPUV1_MATRIX4_RED0_A12_SHIFT                      16U
+
+/* Register: IMXDPUV1_matrix4_Red1 */
+#define IMXDPUV1_MATRIX4_RED1                                ((uint32_t)(0x8C14))
+#define IMXDPUV1_MATRIX4_RED1_OFFSET                         ((uint32_t)(0x14))
+#define IMXDPUV1_MATRIX4_RED1_RESET_VALUE                    0U
+#define IMXDPUV1_MATRIX4_RED1_RESET_MASK                     0xFFFFFFFFU
+#define IMXDPUV1_MATRIX4_RED1_A13_MASK                       0x1FFFU
+#define IMXDPUV1_MATRIX4_RED1_A13_SHIFT                      0U
+#define IMXDPUV1_MATRIX4_RED1_A14_MASK                       0x1FFF0000U
+#define IMXDPUV1_MATRIX4_RED1_A14_SHIFT                      16U
+
+/* Register: IMXDPUV1_matrix4_Green0 */
+#define IMXDPUV1_MATRIX4_GREEN0                              ((uint32_t)(0x8C18))
+#define IMXDPUV1_MATRIX4_GREEN0_OFFSET                       ((uint32_t)(0x18))
+#define IMXDPUV1_MATRIX4_GREEN0_RESET_VALUE                  0x4000000U
+#define IMXDPUV1_MATRIX4_GREEN0_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX4_GREEN0_A21_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX4_GREEN0_A21_SHIFT                    0U
+#define IMXDPUV1_MATRIX4_GREEN0_A22_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX4_GREEN0_A22_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix4_Green1 */
+#define IMXDPUV1_MATRIX4_GREEN1                              ((uint32_t)(0x8C1C))
+#define IMXDPUV1_MATRIX4_GREEN1_OFFSET                       ((uint32_t)(0x1C))
+#define IMXDPUV1_MATRIX4_GREEN1_RESET_VALUE                  0U
+#define IMXDPUV1_MATRIX4_GREEN1_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX4_GREEN1_A23_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX4_GREEN1_A23_SHIFT                    0U
+#define IMXDPUV1_MATRIX4_GREEN1_A24_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX4_GREEN1_A24_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix4_Blue0 */
+#define IMXDPUV1_MATRIX4_BLUE0                               ((uint32_t)(0x8C20))
+#define IMXDPUV1_MATRIX4_BLUE0_OFFSET                        ((uint32_t)(0x20))
+#define IMXDPUV1_MATRIX4_BLUE0_RESET_VALUE                   0U
+#define IMXDPUV1_MATRIX4_BLUE0_RESET_MASK                    0xFFFFFFFFU
+#define IMXDPUV1_MATRIX4_BLUE0_A31_MASK                      0x1FFFU
+#define IMXDPUV1_MATRIX4_BLUE0_A31_SHIFT                     0U
+#define IMXDPUV1_MATRIX4_BLUE0_A32_MASK                      0x1FFF0000U
+#define IMXDPUV1_MATRIX4_BLUE0_A32_SHIFT                     16U
+
+/* Register: IMXDPUV1_matrix4_Blue1 */
+#define IMXDPUV1_MATRIX4_BLUE1                               ((uint32_t)(0x8C24))
+#define IMXDPUV1_MATRIX4_BLUE1_OFFSET                        ((uint32_t)(0x24))
+#define IMXDPUV1_MATRIX4_BLUE1_RESET_VALUE                   0x400U
+#define IMXDPUV1_MATRIX4_BLUE1_RESET_MASK                    0xFFFFFFFFU
+#define IMXDPUV1_MATRIX4_BLUE1_A33_MASK                      0x1FFFU
+#define IMXDPUV1_MATRIX4_BLUE1_A33_SHIFT                     0U
+#define IMXDPUV1_MATRIX4_BLUE1_A34_MASK                      0x1FFF0000U
+#define IMXDPUV1_MATRIX4_BLUE1_A34_SHIFT                     16U
+
+/* Register: IMXDPUV1_matrix4_Alpha0 */
+#define IMXDPUV1_MATRIX4_ALPHA0                              ((uint32_t)(0x8C28))
+#define IMXDPUV1_MATRIX4_ALPHA0_OFFSET                       ((uint32_t)(0x28))
+#define IMXDPUV1_MATRIX4_ALPHA0_RESET_VALUE                  0U
+#define IMXDPUV1_MATRIX4_ALPHA0_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX4_ALPHA0_A41_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX4_ALPHA0_A41_SHIFT                    0U
+#define IMXDPUV1_MATRIX4_ALPHA0_A42_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX4_ALPHA0_A42_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix4_Alpha1 */
+#define IMXDPUV1_MATRIX4_ALPHA1                              ((uint32_t)(0x8C2C))
+#define IMXDPUV1_MATRIX4_ALPHA1_OFFSET                       ((uint32_t)(0x2C))
+#define IMXDPUV1_MATRIX4_ALPHA1_RESET_VALUE                  0x4000000U
+#define IMXDPUV1_MATRIX4_ALPHA1_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX4_ALPHA1_A43_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX4_ALPHA1_A43_SHIFT                    0U
+#define IMXDPUV1_MATRIX4_ALPHA1_A44_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX4_ALPHA1_A44_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix4_OffsetVector0 */
+#define IMXDPUV1_MATRIX4_OFFSETVECTOR0                       ((uint32_t)(0x8C30))
+#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_OFFSET                ((uint32_t)(0x30))
+#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_RESET_VALUE           0U
+#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_C1_MASK               0x1FFFU
+#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_C1_SHIFT              0U
+#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_C2_MASK               0x1FFF0000U
+#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_C2_SHIFT              16U
+
+/* Register: IMXDPUV1_matrix4_OffsetVector1 */
+#define IMXDPUV1_MATRIX4_OFFSETVECTOR1                       ((uint32_t)(0x8C34))
+#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_OFFSET                ((uint32_t)(0x34))
+#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_RESET_VALUE           0U
+#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_C3_MASK               0x1FFFU
+#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_C3_SHIFT              0U
+#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_C4_MASK               0x1FFF0000U
+#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_C4_SHIFT              16U
+
+/* Register: IMXDPUV1_matrix4_LastControlWord */
+#define IMXDPUV1_MATRIX4_LASTCONTROLWORD                     ((uint32_t)(0x8C38))
+#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_OFFSET              ((uint32_t)(0x38))
+#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_RESET_VALUE         0U
+#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_RESET_MASK          0U
+#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_L_VAL_MASK          0xFFFFFFFFU
+#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_L_VAL_SHIFT         0U
+
+/* Register: IMXDPUV1_hscaler4_LockUnlock */
+#define IMXDPUV1_HSCALER4_LOCKUNLOCK                         ((uint32_t)(0x9000))
+#define IMXDPUV1_HSCALER4_LOCKUNLOCK_OFFSET                  ((uint32_t)(0))
+#define IMXDPUV1_HSCALER4_LOCKUNLOCK_RESET_VALUE             0U
+#define IMXDPUV1_HSCALER4_LOCKUNLOCK_RESET_MASK              0U
+#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK_MASK         0xFFFFFFFFU
+#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK_SHIFT        0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY    0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY  0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY  0xFBE8B1E6U
+
+/* Register: IMXDPUV1_hscaler4_LockStatus */
+#define IMXDPUV1_HSCALER4_LOCKSTATUS                         ((uint32_t)(0x9004))
+#define IMXDPUV1_HSCALER4_LOCKSTATUS_OFFSET                  ((uint32_t)(0x4))
+#define IMXDPUV1_HSCALER4_LOCKSTATUS_RESET_VALUE             0U
+#define IMXDPUV1_HSCALER4_LOCKSTATUS_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_HSCALER4_LOCKSTATUS_LOCKSTATUS_MASK         0x1U
+#define IMXDPUV1_HSCALER4_LOCKSTATUS_LOCKSTATUS_SHIFT        0U
+#define IMXDPUV1_HSCALER4_LOCKSTATUS_PRIVILEGESTATUS_MASK    0x10U
+#define IMXDPUV1_HSCALER4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT   4U
+#define IMXDPUV1_HSCALER4_LOCKSTATUS_FREEZESTATUS_MASK       0x100U
+#define IMXDPUV1_HSCALER4_LOCKSTATUS_FREEZESTATUS_SHIFT      8U
+
+/* Register: IMXDPUV1_hscaler4_StaticControl */
+#define IMXDPUV1_HSCALER4_STATICCONTROL                      ((uint32_t)(0x9008))
+#define IMXDPUV1_HSCALER4_STATICCONTROL_OFFSET               ((uint32_t)(0x8))
+#define IMXDPUV1_HSCALER4_STATICCONTROL_RESET_VALUE          0U
+#define IMXDPUV1_HSCALER4_STATICCONTROL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_HSCALER4_STATICCONTROL_SHDEN_MASK           0x1U
+#define IMXDPUV1_HSCALER4_STATICCONTROL_SHDEN_SHIFT          0U
+
+/* Register: IMXDPUV1_hscaler4_Setup1 */
+#define IMXDPUV1_HSCALER4_SETUP1                             ((uint32_t)(0x900C))
+#define IMXDPUV1_HSCALER4_SETUP1_OFFSET                      ((uint32_t)(0xC))
+#define IMXDPUV1_HSCALER4_SETUP1_RESET_VALUE                 0x80000U
+#define IMXDPUV1_HSCALER4_SETUP1_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_HSCALER4_SETUP1_SCALE_FACTOR_MASK           0xFFFFFU
+#define IMXDPUV1_HSCALER4_SETUP1_SCALE_FACTOR_SHIFT          0U
+
+/* Register: IMXDPUV1_hscaler4_Setup2 */
+#define IMXDPUV1_HSCALER4_SETUP2                             ((uint32_t)(0x9010))
+#define IMXDPUV1_HSCALER4_SETUP2_OFFSET                      ((uint32_t)(0x10))
+#define IMXDPUV1_HSCALER4_SETUP2_RESET_VALUE                 0U
+#define IMXDPUV1_HSCALER4_SETUP2_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_HSCALER4_SETUP2_PHASE_OFFSET_MASK           0x1FFFFFU
+#define IMXDPUV1_HSCALER4_SETUP2_PHASE_OFFSET_SHIFT          0U
+
+/* Register: IMXDPUV1_hscaler4_Control */
+#define IMXDPUV1_HSCALER4_CONTROL                            ((uint32_t)(0x9014))
+#define IMXDPUV1_HSCALER4_CONTROL_OFFSET                     ((uint32_t)(0x14))
+#define IMXDPUV1_HSCALER4_CONTROL_RESET_VALUE                0U
+#define IMXDPUV1_HSCALER4_CONTROL_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_HSCALER4_CONTROL_MODE_MASK                  0x1U
+#define IMXDPUV1_HSCALER4_CONTROL_MODE_SHIFT                 0U
+/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all
+ * other settings are ignored.  */
+#define IMXDPUV1_HSCALER4_CONTROL_MODE__NEUTRAL              0U
+/* Field Value: MODE__ACTIVE, Scaler is active.  */
+#define IMXDPUV1_HSCALER4_CONTROL_MODE__ACTIVE               0x1U
+#define IMXDPUV1_HSCALER4_CONTROL_SCALE_MODE_MASK            0x10U
+#define IMXDPUV1_HSCALER4_CONTROL_SCALE_MODE_SHIFT           4U
+/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal
+ * input size).  */
+#define IMXDPUV1_HSCALER4_CONTROL_SCALE_MODE__DOWNSCALE      0U
+/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal
+ * input size)  */
+#define IMXDPUV1_HSCALER4_CONTROL_SCALE_MODE__UPSCALE        0x1U
+#define IMXDPUV1_HSCALER4_CONTROL_FILTER_MODE_MASK           0x100U
+#define IMXDPUV1_HSCALER4_CONTROL_FILTER_MODE_SHIFT          8U
+/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling)  */
+#define IMXDPUV1_HSCALER4_CONTROL_FILTER_MODE__NEAREST       0U
+/* Field Value: FILTER_MODE__LINEAR, Box filter (linear)  */
+#define IMXDPUV1_HSCALER4_CONTROL_FILTER_MODE__LINEAR        0x1U
+#define IMXDPUV1_HSCALER4_CONTROL_OUTPUT_SIZE_MASK           0x3FFF0000U
+#define IMXDPUV1_HSCALER4_CONTROL_OUTPUT_SIZE_SHIFT          16U
+
+/* Register: IMXDPUV1_vscaler4_LockUnlock */
+#define IMXDPUV1_VSCALER4_LOCKUNLOCK                         ((uint32_t)(0x9400))
+#define IMXDPUV1_VSCALER4_LOCKUNLOCK_OFFSET                  ((uint32_t)(0))
+#define IMXDPUV1_VSCALER4_LOCKUNLOCK_RESET_VALUE             0U
+#define IMXDPUV1_VSCALER4_LOCKUNLOCK_RESET_MASK              0U
+#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK_MASK         0xFFFFFFFFU
+#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK_SHIFT        0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY    0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY  0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY  0xFBE8B1E6U
+
+/* Register: IMXDPUV1_vscaler4_LockStatus */
+#define IMXDPUV1_VSCALER4_LOCKSTATUS                         ((uint32_t)(0x9404))
+#define IMXDPUV1_VSCALER4_LOCKSTATUS_OFFSET                  ((uint32_t)(0x4))
+#define IMXDPUV1_VSCALER4_LOCKSTATUS_RESET_VALUE             0U
+#define IMXDPUV1_VSCALER4_LOCKSTATUS_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_VSCALER4_LOCKSTATUS_LOCKSTATUS_MASK         0x1U
+#define IMXDPUV1_VSCALER4_LOCKSTATUS_LOCKSTATUS_SHIFT        0U
+#define IMXDPUV1_VSCALER4_LOCKSTATUS_PRIVILEGESTATUS_MASK    0x10U
+#define IMXDPUV1_VSCALER4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT   4U
+#define IMXDPUV1_VSCALER4_LOCKSTATUS_FREEZESTATUS_MASK       0x100U
+#define IMXDPUV1_VSCALER4_LOCKSTATUS_FREEZESTATUS_SHIFT      8U
+
+/* Register: IMXDPUV1_vscaler4_StaticControl */
+#define IMXDPUV1_VSCALER4_STATICCONTROL                      ((uint32_t)(0x9408))
+#define IMXDPUV1_VSCALER4_STATICCONTROL_OFFSET               ((uint32_t)(0x8))
+#define IMXDPUV1_VSCALER4_STATICCONTROL_RESET_VALUE          0U
+#define IMXDPUV1_VSCALER4_STATICCONTROL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_VSCALER4_STATICCONTROL_SHDEN_MASK           0x1U
+#define IMXDPUV1_VSCALER4_STATICCONTROL_SHDEN_SHIFT          0U
+
+/* Register: IMXDPUV1_vscaler4_Setup1 */
+#define IMXDPUV1_VSCALER4_SETUP1                             ((uint32_t)(0x940C))
+#define IMXDPUV1_VSCALER4_SETUP1_OFFSET                      ((uint32_t)(0xC))
+#define IMXDPUV1_VSCALER4_SETUP1_RESET_VALUE                 0x80000U
+#define IMXDPUV1_VSCALER4_SETUP1_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_VSCALER4_SETUP1_SCALE_FACTOR_MASK           0xFFFFFU
+#define IMXDPUV1_VSCALER4_SETUP1_SCALE_FACTOR_SHIFT          0U
+
+/* Register: IMXDPUV1_vscaler4_Setup2 */
+#define IMXDPUV1_VSCALER4_SETUP2                             ((uint32_t)(0x9410))
+#define IMXDPUV1_VSCALER4_SETUP2_OFFSET                      ((uint32_t)(0x10))
+#define IMXDPUV1_VSCALER4_SETUP2_RESET_VALUE                 0U
+#define IMXDPUV1_VSCALER4_SETUP2_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_VSCALER4_SETUP2_PHASE_OFFSET_MASK           0x1FFFFFU
+#define IMXDPUV1_VSCALER4_SETUP2_PHASE_OFFSET_SHIFT          0U
+
+/* Register: IMXDPUV1_vscaler4_Setup3 */
+#define IMXDPUV1_VSCALER4_SETUP3                             ((uint32_t)(0x9414))
+#define IMXDPUV1_VSCALER4_SETUP3_OFFSET                      ((uint32_t)(0x14))
+#define IMXDPUV1_VSCALER4_SETUP3_RESET_VALUE                 0U
+#define IMXDPUV1_VSCALER4_SETUP3_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_VSCALER4_SETUP3_PHASE_OFFSET1_MASK          0x1FFFFFU
+#define IMXDPUV1_VSCALER4_SETUP3_PHASE_OFFSET1_SHIFT         0U
+
+/* Register: IMXDPUV1_vscaler4_Setup4 */
+#define IMXDPUV1_VSCALER4_SETUP4                             ((uint32_t)(0x9418))
+#define IMXDPUV1_VSCALER4_SETUP4_OFFSET                      ((uint32_t)(0x18))
+#define IMXDPUV1_VSCALER4_SETUP4_RESET_VALUE                 0U
+#define IMXDPUV1_VSCALER4_SETUP4_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_VSCALER4_SETUP4_PHASE_OFFSET2_MASK          0x1FFFFFU
+#define IMXDPUV1_VSCALER4_SETUP4_PHASE_OFFSET2_SHIFT         0U
+
+/* Register: IMXDPUV1_vscaler4_Setup5 */
+#define IMXDPUV1_VSCALER4_SETUP5                             ((uint32_t)(0x941C))
+#define IMXDPUV1_VSCALER4_SETUP5_OFFSET                      ((uint32_t)(0x1C))
+#define IMXDPUV1_VSCALER4_SETUP5_RESET_VALUE                 0U
+#define IMXDPUV1_VSCALER4_SETUP5_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_VSCALER4_SETUP5_PHASE_OFFSET3_MASK          0x1FFFFFU
+#define IMXDPUV1_VSCALER4_SETUP5_PHASE_OFFSET3_SHIFT         0U
+
+/* Register: IMXDPUV1_vscaler4_Control */
+#define IMXDPUV1_VSCALER4_CONTROL                            ((uint32_t)(0x9420))
+#define IMXDPUV1_VSCALER4_CONTROL_OFFSET                     ((uint32_t)(0x20))
+#define IMXDPUV1_VSCALER4_CONTROL_RESET_VALUE                0x2000U
+#define IMXDPUV1_VSCALER4_CONTROL_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_VSCALER4_CONTROL_MODE_MASK                  0x1U
+#define IMXDPUV1_VSCALER4_CONTROL_MODE_SHIFT                 0U
+/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all
+ * other settings are ignored.  */
+#define IMXDPUV1_VSCALER4_CONTROL_MODE__NEUTRAL              0U
+/* Field Value: MODE__ACTIVE, Scaler is active.  */
+#define IMXDPUV1_VSCALER4_CONTROL_MODE__ACTIVE               0x1U
+#define IMXDPUV1_VSCALER4_CONTROL_SCALE_MODE_MASK            0x10U
+#define IMXDPUV1_VSCALER4_CONTROL_SCALE_MODE_SHIFT           4U
+/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal
+ * input size).  */
+#define IMXDPUV1_VSCALER4_CONTROL_SCALE_MODE__DOWNSCALE      0U
+/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal
+ * input size).  */
+#define IMXDPUV1_VSCALER4_CONTROL_SCALE_MODE__UPSCALE        0x1U
+#define IMXDPUV1_VSCALER4_CONTROL_FILTER_MODE_MASK           0x100U
+#define IMXDPUV1_VSCALER4_CONTROL_FILTER_MODE_SHIFT          8U
+/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling)  */
+#define IMXDPUV1_VSCALER4_CONTROL_FILTER_MODE__NEAREST       0U
+/* Field Value: FILTER_MODE__LINEAR, Box filter (linear)  */
+#define IMXDPUV1_VSCALER4_CONTROL_FILTER_MODE__LINEAR        0x1U
+#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE_MASK            0x3000U
+#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE_SHIFT           12U
+/* Field Value: FIELD_MODE__ALWAYS0, Constant 0 indicates frame or top field.  */
+#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE__ALWAYS0        0U
+/* Field Value: FIELD_MODE__ALWAYS1, Constant 1 indicates bottom field.  */
+#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE__ALWAYS1        0x1U
+/* Field Value: FIELD_MODE__INPUT, Output field polarity is taken from input
+ * field polarity.  */
+#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE__INPUT          0x2U
+/* Field Value: FIELD_MODE__TOGGLE, Output field polarity toggles, starting
+ * with 0 after reset.  */
+#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE__TOGGLE         0x3U
+#define IMXDPUV1_VSCALER4_CONTROL_OUTPUT_SIZE_MASK           0x3FFF0000U
+#define IMXDPUV1_VSCALER4_CONTROL_OUTPUT_SIZE_SHIFT          16U
+
+/* Register: IMXDPUV1_matrix5_LockUnlock */
+#define IMXDPUV1_MATRIX5_LOCKUNLOCK                          ((uint32_t)(0x9800))
+#define IMXDPUV1_MATRIX5_LOCKUNLOCK_OFFSET                   ((uint32_t)(0))
+#define IMXDPUV1_MATRIX5_LOCKUNLOCK_RESET_VALUE              0U
+#define IMXDPUV1_MATRIX5_LOCKUNLOCK_RESET_MASK               0U
+#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK_MASK          0xFFFFFFFFU
+#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK_SHIFT         0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY     0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY   0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY   0xFBE8B1E6U
+
+/* Register: IMXDPUV1_matrix5_LockStatus */
+#define IMXDPUV1_MATRIX5_LOCKSTATUS                          ((uint32_t)(0x9804))
+#define IMXDPUV1_MATRIX5_LOCKSTATUS_OFFSET                   ((uint32_t)(0x4))
+#define IMXDPUV1_MATRIX5_LOCKSTATUS_RESET_VALUE              0U
+#define IMXDPUV1_MATRIX5_LOCKSTATUS_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_MATRIX5_LOCKSTATUS_LOCKSTATUS_MASK          0x1U
+#define IMXDPUV1_MATRIX5_LOCKSTATUS_LOCKSTATUS_SHIFT         0U
+#define IMXDPUV1_MATRIX5_LOCKSTATUS_PRIVILEGESTATUS_MASK     0x10U
+#define IMXDPUV1_MATRIX5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT    4U
+#define IMXDPUV1_MATRIX5_LOCKSTATUS_FREEZESTATUS_MASK        0x100U
+#define IMXDPUV1_MATRIX5_LOCKSTATUS_FREEZESTATUS_SHIFT       8U
+
+/* Register: IMXDPUV1_matrix5_StaticControl */
+#define IMXDPUV1_MATRIX5_STATICCONTROL                       ((uint32_t)(0x9808))
+#define IMXDPUV1_MATRIX5_STATICCONTROL_OFFSET                ((uint32_t)(0x8))
+#define IMXDPUV1_MATRIX5_STATICCONTROL_RESET_VALUE           0U
+#define IMXDPUV1_MATRIX5_STATICCONTROL_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_MATRIX5_STATICCONTROL_SHDEN_MASK            0x1U
+#define IMXDPUV1_MATRIX5_STATICCONTROL_SHDEN_SHIFT           0U
+
+/* Register: IMXDPUV1_matrix5_Control */
+#define IMXDPUV1_MATRIX5_CONTROL                             ((uint32_t)(0x980C))
+#define IMXDPUV1_MATRIX5_CONTROL_OFFSET                      ((uint32_t)(0xC))
+#define IMXDPUV1_MATRIX5_CONTROL_RESET_VALUE                 0U
+#define IMXDPUV1_MATRIX5_CONTROL_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_MATRIX5_CONTROL_MODE_MASK                   0x3U
+#define IMXDPUV1_MATRIX5_CONTROL_MODE_SHIFT                  0U
+/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed  */
+#define IMXDPUV1_MATRIX5_CONTROL_MODE__NEUTRAL               0U
+/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied
+ * with matrix values  */
+#define IMXDPUV1_MATRIX5_CONTROL_MODE__MATRIX                0x1U
+/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input
+ * color is multiplied with input alpha  */
+#define IMXDPUV1_MATRIX5_CONTROL_MODE__PREMUL                0x2U
+/* Field Value: MODE__RSVD, Reserved, do not use  */
+#define IMXDPUV1_MATRIX5_CONTROL_MODE__RSVD                  0x3U
+#define IMXDPUV1_MATRIX5_CONTROL_ALPHAMASK_MASK              0x10U
+#define IMXDPUV1_MATRIX5_CONTROL_ALPHAMASK_SHIFT             4U
+#define IMXDPUV1_MATRIX5_CONTROL_ALPHAINVERT_MASK            0x20U
+#define IMXDPUV1_MATRIX5_CONTROL_ALPHAINVERT_SHIFT           5U
+
+/* Register: IMXDPUV1_matrix5_Red0 */
+#define IMXDPUV1_MATRIX5_RED0                                ((uint32_t)(0x9810))
+#define IMXDPUV1_MATRIX5_RED0_OFFSET                         ((uint32_t)(0x10))
+#define IMXDPUV1_MATRIX5_RED0_RESET_VALUE                    0x400U
+#define IMXDPUV1_MATRIX5_RED0_RESET_MASK                     0xFFFFFFFFU
+#define IMXDPUV1_MATRIX5_RED0_A11_MASK                       0x1FFFU
+#define IMXDPUV1_MATRIX5_RED0_A11_SHIFT                      0U
+#define IMXDPUV1_MATRIX5_RED0_A12_MASK                       0x1FFF0000U
+#define IMXDPUV1_MATRIX5_RED0_A12_SHIFT                      16U
+
+/* Register: IMXDPUV1_matrix5_Red1 */
+#define IMXDPUV1_MATRIX5_RED1                                ((uint32_t)(0x9814))
+#define IMXDPUV1_MATRIX5_RED1_OFFSET                         ((uint32_t)(0x14))
+#define IMXDPUV1_MATRIX5_RED1_RESET_VALUE                    0U
+#define IMXDPUV1_MATRIX5_RED1_RESET_MASK                     0xFFFFFFFFU
+#define IMXDPUV1_MATRIX5_RED1_A13_MASK                       0x1FFFU
+#define IMXDPUV1_MATRIX5_RED1_A13_SHIFT                      0U
+#define IMXDPUV1_MATRIX5_RED1_A14_MASK                       0x1FFF0000U
+#define IMXDPUV1_MATRIX5_RED1_A14_SHIFT                      16U
+
+/* Register: IMXDPUV1_matrix5_Green0 */
+#define IMXDPUV1_MATRIX5_GREEN0                              ((uint32_t)(0x9818))
+#define IMXDPUV1_MATRIX5_GREEN0_OFFSET                       ((uint32_t)(0x18))
+#define IMXDPUV1_MATRIX5_GREEN0_RESET_VALUE                  0x4000000U
+#define IMXDPUV1_MATRIX5_GREEN0_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX5_GREEN0_A21_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX5_GREEN0_A21_SHIFT                    0U
+#define IMXDPUV1_MATRIX5_GREEN0_A22_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX5_GREEN0_A22_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix5_Green1 */
+#define IMXDPUV1_MATRIX5_GREEN1                              ((uint32_t)(0x981C))
+#define IMXDPUV1_MATRIX5_GREEN1_OFFSET                       ((uint32_t)(0x1C))
+#define IMXDPUV1_MATRIX5_GREEN1_RESET_VALUE                  0U
+#define IMXDPUV1_MATRIX5_GREEN1_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX5_GREEN1_A23_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX5_GREEN1_A23_SHIFT                    0U
+#define IMXDPUV1_MATRIX5_GREEN1_A24_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX5_GREEN1_A24_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix5_Blue0 */
+#define IMXDPUV1_MATRIX5_BLUE0                               ((uint32_t)(0x9820))
+#define IMXDPUV1_MATRIX5_BLUE0_OFFSET                        ((uint32_t)(0x20))
+#define IMXDPUV1_MATRIX5_BLUE0_RESET_VALUE                   0U
+#define IMXDPUV1_MATRIX5_BLUE0_RESET_MASK                    0xFFFFFFFFU
+#define IMXDPUV1_MATRIX5_BLUE0_A31_MASK                      0x1FFFU
+#define IMXDPUV1_MATRIX5_BLUE0_A31_SHIFT                     0U
+#define IMXDPUV1_MATRIX5_BLUE0_A32_MASK                      0x1FFF0000U
+#define IMXDPUV1_MATRIX5_BLUE0_A32_SHIFT                     16U
+
+/* Register: IMXDPUV1_matrix5_Blue1 */
+#define IMXDPUV1_MATRIX5_BLUE1                               ((uint32_t)(0x9824))
+#define IMXDPUV1_MATRIX5_BLUE1_OFFSET                        ((uint32_t)(0x24))
+#define IMXDPUV1_MATRIX5_BLUE1_RESET_VALUE                   0x400U
+#define IMXDPUV1_MATRIX5_BLUE1_RESET_MASK                    0xFFFFFFFFU
+#define IMXDPUV1_MATRIX5_BLUE1_A33_MASK                      0x1FFFU
+#define IMXDPUV1_MATRIX5_BLUE1_A33_SHIFT                     0U
+#define IMXDPUV1_MATRIX5_BLUE1_A34_MASK                      0x1FFF0000U
+#define IMXDPUV1_MATRIX5_BLUE1_A34_SHIFT                     16U
+
+/* Register: IMXDPUV1_matrix5_Alpha0 */
+#define IMXDPUV1_MATRIX5_ALPHA0                              ((uint32_t)(0x9828))
+#define IMXDPUV1_MATRIX5_ALPHA0_OFFSET                       ((uint32_t)(0x28))
+#define IMXDPUV1_MATRIX5_ALPHA0_RESET_VALUE                  0U
+#define IMXDPUV1_MATRIX5_ALPHA0_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX5_ALPHA0_A41_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX5_ALPHA0_A41_SHIFT                    0U
+#define IMXDPUV1_MATRIX5_ALPHA0_A42_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX5_ALPHA0_A42_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix5_Alpha1 */
+#define IMXDPUV1_MATRIX5_ALPHA1                              ((uint32_t)(0x982C))
+#define IMXDPUV1_MATRIX5_ALPHA1_OFFSET                       ((uint32_t)(0x2C))
+#define IMXDPUV1_MATRIX5_ALPHA1_RESET_VALUE                  0x4000000U
+#define IMXDPUV1_MATRIX5_ALPHA1_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX5_ALPHA1_A43_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX5_ALPHA1_A43_SHIFT                    0U
+#define IMXDPUV1_MATRIX5_ALPHA1_A44_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX5_ALPHA1_A44_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix5_OffsetVector0 */
+#define IMXDPUV1_MATRIX5_OFFSETVECTOR0                       ((uint32_t)(0x9830))
+#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_OFFSET                ((uint32_t)(0x30))
+#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_RESET_VALUE           0U
+#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_C1_MASK               0x1FFFU
+#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_C1_SHIFT              0U
+#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_C2_MASK               0x1FFF0000U
+#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_C2_SHIFT              16U
+
+/* Register: IMXDPUV1_matrix5_OffsetVector1 */
+#define IMXDPUV1_MATRIX5_OFFSETVECTOR1                       ((uint32_t)(0x9834))
+#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_OFFSET                ((uint32_t)(0x34))
+#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_RESET_VALUE           0U
+#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_C3_MASK               0x1FFFU
+#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_C3_SHIFT              0U
+#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_C4_MASK               0x1FFF0000U
+#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_C4_SHIFT              16U
+
+/* Register: IMXDPUV1_matrix5_LastControlWord */
+#define IMXDPUV1_MATRIX5_LASTCONTROLWORD                     ((uint32_t)(0x9838))
+#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_OFFSET              ((uint32_t)(0x38))
+#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_RESET_VALUE         0U
+#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_RESET_MASK          0U
+#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_L_VAL_MASK          0xFFFFFFFFU
+#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_L_VAL_SHIFT         0U
+
+/* Register: IMXDPUV1_hscaler5_LockUnlock */
+#define IMXDPUV1_HSCALER5_LOCKUNLOCK                         ((uint32_t)(0x9C00))
+#define IMXDPUV1_HSCALER5_LOCKUNLOCK_OFFSET                  ((uint32_t)(0))
+#define IMXDPUV1_HSCALER5_LOCKUNLOCK_RESET_VALUE             0U
+#define IMXDPUV1_HSCALER5_LOCKUNLOCK_RESET_MASK              0U
+#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK_MASK         0xFFFFFFFFU
+#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK_SHIFT        0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY    0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY  0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY  0xFBE8B1E6U
+
+/* Register: IMXDPUV1_hscaler5_LockStatus */
+#define IMXDPUV1_HSCALER5_LOCKSTATUS                         ((uint32_t)(0x9C04))
+#define IMXDPUV1_HSCALER5_LOCKSTATUS_OFFSET                  ((uint32_t)(0x4))
+#define IMXDPUV1_HSCALER5_LOCKSTATUS_RESET_VALUE             0U
+#define IMXDPUV1_HSCALER5_LOCKSTATUS_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_HSCALER5_LOCKSTATUS_LOCKSTATUS_MASK         0x1U
+#define IMXDPUV1_HSCALER5_LOCKSTATUS_LOCKSTATUS_SHIFT        0U
+#define IMXDPUV1_HSCALER5_LOCKSTATUS_PRIVILEGESTATUS_MASK    0x10U
+#define IMXDPUV1_HSCALER5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT   4U
+#define IMXDPUV1_HSCALER5_LOCKSTATUS_FREEZESTATUS_MASK       0x100U
+#define IMXDPUV1_HSCALER5_LOCKSTATUS_FREEZESTATUS_SHIFT      8U
+
+/* Register: IMXDPUV1_hscaler5_StaticControl */
+#define IMXDPUV1_HSCALER5_STATICCONTROL                      ((uint32_t)(0x9C08))
+#define IMXDPUV1_HSCALER5_STATICCONTROL_OFFSET               ((uint32_t)(0x8))
+#define IMXDPUV1_HSCALER5_STATICCONTROL_RESET_VALUE          0U
+#define IMXDPUV1_HSCALER5_STATICCONTROL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_HSCALER5_STATICCONTROL_SHDEN_MASK           0x1U
+#define IMXDPUV1_HSCALER5_STATICCONTROL_SHDEN_SHIFT          0U
+
+/* Register: IMXDPUV1_hscaler5_Setup1 */
+#define IMXDPUV1_HSCALER5_SETUP1                             ((uint32_t)(0x9C0C))
+#define IMXDPUV1_HSCALER5_SETUP1_OFFSET                      ((uint32_t)(0xC))
+#define IMXDPUV1_HSCALER5_SETUP1_RESET_VALUE                 0x80000U
+#define IMXDPUV1_HSCALER5_SETUP1_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_HSCALER5_SETUP1_SCALE_FACTOR_MASK           0xFFFFFU
+#define IMXDPUV1_HSCALER5_SETUP1_SCALE_FACTOR_SHIFT          0U
+
+/* Register: IMXDPUV1_hscaler5_Setup2 */
+#define IMXDPUV1_HSCALER5_SETUP2                             ((uint32_t)(0x9C10))
+#define IMXDPUV1_HSCALER5_SETUP2_OFFSET                      ((uint32_t)(0x10))
+#define IMXDPUV1_HSCALER5_SETUP2_RESET_VALUE                 0U
+#define IMXDPUV1_HSCALER5_SETUP2_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_HSCALER5_SETUP2_PHASE_OFFSET_MASK           0x1FFFFFU
+#define IMXDPUV1_HSCALER5_SETUP2_PHASE_OFFSET_SHIFT          0U
+
+/* Register: IMXDPUV1_hscaler5_Control */
+#define IMXDPUV1_HSCALER5_CONTROL                            ((uint32_t)(0x9C14))
+#define IMXDPUV1_HSCALER5_CONTROL_OFFSET                     ((uint32_t)(0x14))
+#define IMXDPUV1_HSCALER5_CONTROL_RESET_VALUE                0U
+#define IMXDPUV1_HSCALER5_CONTROL_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_HSCALER5_CONTROL_MODE_MASK                  0x1U
+#define IMXDPUV1_HSCALER5_CONTROL_MODE_SHIFT                 0U
+/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all
+ * other settings are ignored.  */
+#define IMXDPUV1_HSCALER5_CONTROL_MODE__NEUTRAL              0U
+/* Field Value: MODE__ACTIVE, Scaler is active.  */
+#define IMXDPUV1_HSCALER5_CONTROL_MODE__ACTIVE               0x1U
+#define IMXDPUV1_HSCALER5_CONTROL_SCALE_MODE_MASK            0x10U
+#define IMXDPUV1_HSCALER5_CONTROL_SCALE_MODE_SHIFT           4U
+/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal
+ * input size).  */
+#define IMXDPUV1_HSCALER5_CONTROL_SCALE_MODE__DOWNSCALE      0U
+/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal
+ * input size)  */
+#define IMXDPUV1_HSCALER5_CONTROL_SCALE_MODE__UPSCALE        0x1U
+#define IMXDPUV1_HSCALER5_CONTROL_FILTER_MODE_MASK           0x100U
+#define IMXDPUV1_HSCALER5_CONTROL_FILTER_MODE_SHIFT          8U
+/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling)  */
+#define IMXDPUV1_HSCALER5_CONTROL_FILTER_MODE__NEAREST       0U
+/* Field Value: FILTER_MODE__LINEAR, Box filter (linear)  */
+#define IMXDPUV1_HSCALER5_CONTROL_FILTER_MODE__LINEAR        0x1U
+#define IMXDPUV1_HSCALER5_CONTROL_OUTPUT_SIZE_MASK           0x3FFF0000U
+#define IMXDPUV1_HSCALER5_CONTROL_OUTPUT_SIZE_SHIFT          16U
+
+/* Register: IMXDPUV1_vscaler5_LockUnlock */
+#define IMXDPUV1_VSCALER5_LOCKUNLOCK                         ((uint32_t)(0xA000))
+#define IMXDPUV1_VSCALER5_LOCKUNLOCK_OFFSET                  ((uint32_t)(0))
+#define IMXDPUV1_VSCALER5_LOCKUNLOCK_RESET_VALUE             0U
+#define IMXDPUV1_VSCALER5_LOCKUNLOCK_RESET_MASK              0U
+#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK_MASK         0xFFFFFFFFU
+#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK_SHIFT        0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY    0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY  0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY  0xFBE8B1E6U
+
+/* Register: IMXDPUV1_vscaler5_LockStatus */
+#define IMXDPUV1_VSCALER5_LOCKSTATUS                         ((uint32_t)(0xA004))
+#define IMXDPUV1_VSCALER5_LOCKSTATUS_OFFSET                  ((uint32_t)(0x4))
+#define IMXDPUV1_VSCALER5_LOCKSTATUS_RESET_VALUE             0U
+#define IMXDPUV1_VSCALER5_LOCKSTATUS_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_VSCALER5_LOCKSTATUS_LOCKSTATUS_MASK         0x1U
+#define IMXDPUV1_VSCALER5_LOCKSTATUS_LOCKSTATUS_SHIFT        0U
+#define IMXDPUV1_VSCALER5_LOCKSTATUS_PRIVILEGESTATUS_MASK    0x10U
+#define IMXDPUV1_VSCALER5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT   4U
+#define IMXDPUV1_VSCALER5_LOCKSTATUS_FREEZESTATUS_MASK       0x100U
+#define IMXDPUV1_VSCALER5_LOCKSTATUS_FREEZESTATUS_SHIFT      8U
+
+/* Register: IMXDPUV1_vscaler5_StaticControl */
+#define IMXDPUV1_VSCALER5_STATICCONTROL                      ((uint32_t)(0xA008))
+#define IMXDPUV1_VSCALER5_STATICCONTROL_OFFSET               ((uint32_t)(0x8))
+#define IMXDPUV1_VSCALER5_STATICCONTROL_RESET_VALUE          0U
+#define IMXDPUV1_VSCALER5_STATICCONTROL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_VSCALER5_STATICCONTROL_SHDEN_MASK           0x1U
+#define IMXDPUV1_VSCALER5_STATICCONTROL_SHDEN_SHIFT          0U
+
+/* Register: IMXDPUV1_vscaler5_Setup1 */
+#define IMXDPUV1_VSCALER5_SETUP1                             ((uint32_t)(0xA00C))
+#define IMXDPUV1_VSCALER5_SETUP1_OFFSET                      ((uint32_t)(0xC))
+#define IMXDPUV1_VSCALER5_SETUP1_RESET_VALUE                 0x80000U
+#define IMXDPUV1_VSCALER5_SETUP1_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_VSCALER5_SETUP1_SCALE_FACTOR_MASK           0xFFFFFU
+#define IMXDPUV1_VSCALER5_SETUP1_SCALE_FACTOR_SHIFT          0U
+
+/* Register: IMXDPUV1_vscaler5_Setup2 */
+#define IMXDPUV1_VSCALER5_SETUP2                             ((uint32_t)(0xA010))
+#define IMXDPUV1_VSCALER5_SETUP2_OFFSET                      ((uint32_t)(0x10))
+#define IMXDPUV1_VSCALER5_SETUP2_RESET_VALUE                 0U
+#define IMXDPUV1_VSCALER5_SETUP2_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_VSCALER5_SETUP2_PHASE_OFFSET_MASK           0x1FFFFFU
+#define IMXDPUV1_VSCALER5_SETUP2_PHASE_OFFSET_SHIFT          0U
+
+/* Register: IMXDPUV1_vscaler5_Setup3 */
+#define IMXDPUV1_VSCALER5_SETUP3                             ((uint32_t)(0xA014))
+#define IMXDPUV1_VSCALER5_SETUP3_OFFSET                      ((uint32_t)(0x14))
+#define IMXDPUV1_VSCALER5_SETUP3_RESET_VALUE                 0U
+#define IMXDPUV1_VSCALER5_SETUP3_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_VSCALER5_SETUP3_PHASE_OFFSET1_MASK          0x1FFFFFU
+#define IMXDPUV1_VSCALER5_SETUP3_PHASE_OFFSET1_SHIFT         0U
+
+/* Register: IMXDPUV1_vscaler5_Setup4 */
+#define IMXDPUV1_VSCALER5_SETUP4                             ((uint32_t)(0xA018))
+#define IMXDPUV1_VSCALER5_SETUP4_OFFSET                      ((uint32_t)(0x18))
+#define IMXDPUV1_VSCALER5_SETUP4_RESET_VALUE                 0U
+#define IMXDPUV1_VSCALER5_SETUP4_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_VSCALER5_SETUP4_PHASE_OFFSET2_MASK          0x1FFFFFU
+#define IMXDPUV1_VSCALER5_SETUP4_PHASE_OFFSET2_SHIFT         0U
+
+/* Register: IMXDPUV1_vscaler5_Setup5 */
+#define IMXDPUV1_VSCALER5_SETUP5                             ((uint32_t)(0xA01C))
+#define IMXDPUV1_VSCALER5_SETUP5_OFFSET                      ((uint32_t)(0x1C))
+#define IMXDPUV1_VSCALER5_SETUP5_RESET_VALUE                 0U
+#define IMXDPUV1_VSCALER5_SETUP5_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_VSCALER5_SETUP5_PHASE_OFFSET3_MASK          0x1FFFFFU
+#define IMXDPUV1_VSCALER5_SETUP5_PHASE_OFFSET3_SHIFT         0U
+
+/* Register: IMXDPUV1_vscaler5_Control */
+#define IMXDPUV1_VSCALER5_CONTROL                            ((uint32_t)(0xA020))
+#define IMXDPUV1_VSCALER5_CONTROL_OFFSET                     ((uint32_t)(0x20))
+#define IMXDPUV1_VSCALER5_CONTROL_RESET_VALUE                0x2000U
+#define IMXDPUV1_VSCALER5_CONTROL_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_VSCALER5_CONTROL_MODE_MASK                  0x1U
+#define IMXDPUV1_VSCALER5_CONTROL_MODE_SHIFT                 0U
+/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all
+ * other settings are ignored.  */
+#define IMXDPUV1_VSCALER5_CONTROL_MODE__NEUTRAL              0U
+/* Field Value: MODE__ACTIVE, Scaler is active.  */
+#define IMXDPUV1_VSCALER5_CONTROL_MODE__ACTIVE               0x1U
+#define IMXDPUV1_VSCALER5_CONTROL_SCALE_MODE_MASK            0x10U
+#define IMXDPUV1_VSCALER5_CONTROL_SCALE_MODE_SHIFT           4U
+/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal
+ * input size).  */
+#define IMXDPUV1_VSCALER5_CONTROL_SCALE_MODE__DOWNSCALE      0U
+/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal
+ * input size).  */
+#define IMXDPUV1_VSCALER5_CONTROL_SCALE_MODE__UPSCALE        0x1U
+#define IMXDPUV1_VSCALER5_CONTROL_FILTER_MODE_MASK           0x100U
+#define IMXDPUV1_VSCALER5_CONTROL_FILTER_MODE_SHIFT          8U
+/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling)  */
+#define IMXDPUV1_VSCALER5_CONTROL_FILTER_MODE__NEAREST       0U
+/* Field Value: FILTER_MODE__LINEAR, Box filter (linear)  */
+#define IMXDPUV1_VSCALER5_CONTROL_FILTER_MODE__LINEAR        0x1U
+#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE_MASK            0x3000U
+#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE_SHIFT           12U
+/* Field Value: FIELD_MODE__ALWAYS0, Constant 0 indicates frame or top field.  */
+#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE__ALWAYS0        0U
+/* Field Value: FIELD_MODE__ALWAYS1, Constant 1 indicates bottom field.  */
+#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE__ALWAYS1        0x1U
+/* Field Value: FIELD_MODE__INPUT, Output field polarity is taken from input
+ * field polarity.  */
+#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE__INPUT          0x2U
+/* Field Value: FIELD_MODE__TOGGLE, Output field polarity toggles, starting
+ * with 0 after reset.  */
+#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE__TOGGLE         0x3U
+#define IMXDPUV1_VSCALER5_CONTROL_OUTPUT_SIZE_MASK           0x3FFF0000U
+#define IMXDPUV1_VSCALER5_CONTROL_OUTPUT_SIZE_SHIFT          16U
+
+/* Register: IMXDPUV1_layerblend0_LockUnlock */
+#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK                      ((uint32_t)(0xA400))
+#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_OFFSET               ((uint32_t)(0))
+#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_RESET_VALUE          0U
+#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_RESET_MASK           0U
+#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK_MASK      0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK_SHIFT     0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_layerblend0_LockStatus */
+#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS                      ((uint32_t)(0xA404))
+#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_OFFSET               ((uint32_t)(0x4))
+#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_RESET_VALUE          0U
+#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_LOCKSTATUS_MASK      0x1U
+#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_LOCKSTATUS_SHIFT     0U
+#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_FREEZESTATUS_MASK    0x100U
+#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_FREEZESTATUS_SHIFT   8U
+
+/* Register: IMXDPUV1_layerblend0_StaticControl */
+#define IMXDPUV1_LAYERBLEND0_STATICCONTROL                   ((uint32_t)(0xA408))
+#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_OFFSET            ((uint32_t)(0x8))
+#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_RESET_VALUE       0x14U
+#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDEN_MASK        0x1U
+#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDEN_SHIFT       0U
+#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL_MASK     0x6U
+#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL_SHIFT    1U
+/* Field Value: SHDLDSEL__PRIMARY, Load shadows with shadow load token on
+ * primary input (background plane).  */
+#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL__PRIMARY 0U
+/* Field Value: SHDLDSEL__SECONDARY, Load shadows with shadow load token on
+ * secondary input (foreground plane).  */
+#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL__SECONDARY 0x1U
+/* Field Value: SHDLDSEL__BOTH, Load shadows with shadow load token on any
+ * input.  */
+#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL__BOTH    0x2U
+#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL_MASK    0x18U
+#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL_SHIFT   3U
+/* Field Value: SHDTOKSEL__PRIMARY, When a token was received on the primary
+ * input (background plane).  */
+#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL__PRIMARY 0U
+/* Field Value: SHDTOKSEL__SECONDARY, When a token was received on the secondary
+ * input (foreground plane).  */
+#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL__SECONDARY 0x1U
+/* Field Value: SHDTOKSEL__BOTH, When a token was received on any input.  */
+#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL__BOTH   0x2U
+
+/* Register: IMXDPUV1_layerblend0_Control */
+#define IMXDPUV1_LAYERBLEND0_CONTROL                         ((uint32_t)(0xA40C))
+#define IMXDPUV1_LAYERBLEND0_CONTROL_OFFSET                  ((uint32_t)(0xC))
+#define IMXDPUV1_LAYERBLEND0_CONTROL_RESET_VALUE             0x1U
+#define IMXDPUV1_LAYERBLEND0_CONTROL_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND0_CONTROL_MODE_MASK               0x1U
+#define IMXDPUV1_LAYERBLEND0_CONTROL_MODE_SHIFT              0U
+/* Field Value: MODE__NEUTRAL, Module is in neutral mode. Output is same as
+ * primary input.  */
+#define IMXDPUV1_LAYERBLEND0_CONTROL_MODE__NEUTRAL           0U
+/* Field Value: MODE__BLEND, Module is in blending mode.  */
+#define IMXDPUV1_LAYERBLEND0_CONTROL_MODE__BLEND             0x1U
+#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE_MASK    0x4U
+#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE_SHIFT   2U
+/* Field Value: ALPHAMASKENABLE__DISABLE, AlphaMask feature disabled  */
+#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE__DISABLE 0U
+/* Field Value: ALPHAMASKENABLE__ENABLE, AlphaMask feature enabled  */
+#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE__ENABLE 0x1U
+#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE_MASK      0x70U
+#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE_SHIFT     4U
+/* Field Value: ALPHAMASKMODE__PRIM, Areas with primary input alpha > 128
+ * will be mapped to 255 and the rest will have an alpha value of 0  */
+#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM     0U
+/* Field Value: ALPHAMASKMODE__SEC, The area of the secondary input will get
+ * an alpha value of 255 and the rest will be 0  */
+#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__SEC      0x1U
+/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC, Behaves as if the output of modes
+ * PRIM and SEC would be ORed together  */
+#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC 0x2U
+/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC, Behaves as if the output of modes
+ * PRIM and SEC would be ANDed together  */
+#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC 0x3U
+/* Field Value: ALPHAMASKMODE__PRIM_INV, Behaves as if the output of mode
+ * PRIM would be inverted  */
+#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_INV 0x4U
+/* Field Value: ALPHAMASKMODE__SEC_INV, Behaves as if the output of mode SEC
+ * would be inverted  */
+#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__SEC_INV  0x5U
+/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC_INV, Behaves as if the output of
+ * modes PRIM and SEC_INV would be ORed together  */
+#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC_INV 0x6U
+/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC_INV, Behaves as if the output
+ * of modes PRIM and SEC_INV would be ANDed together  */
+#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC_INV 0x7U
+#define IMXDPUV1_LAYERBLEND0_CONTROL_SECLOWPASSEN_MASK       0x100U
+#define IMXDPUV1_LAYERBLEND0_CONTROL_SECLOWPASSEN_SHIFT      8U
+#define IMXDPUV1_LAYERBLEND0_CONTROL_SECREPLICATEEN_MASK     0x200U
+#define IMXDPUV1_LAYERBLEND0_CONTROL_SECREPLICATEEN_SHIFT    9U
+#define IMXDPUV1_LAYERBLEND0_CONTROL_SECEVENROWEVENCOLDIS_MASK 0x3C00U
+#define IMXDPUV1_LAYERBLEND0_CONTROL_SECEVENROWEVENCOLDIS_SHIFT 10U
+#define IMXDPUV1_LAYERBLEND0_CONTROL_SECEVENROWODDCOLDIS_MASK 0x3C000U
+#define IMXDPUV1_LAYERBLEND0_CONTROL_SECEVENROWODDCOLDIS_SHIFT 14U
+#define IMXDPUV1_LAYERBLEND0_CONTROL_SECODDROWEVENCOLDIS_MASK 0x3C0000U
+#define IMXDPUV1_LAYERBLEND0_CONTROL_SECODDROWEVENCOLDIS_SHIFT 18U
+#define IMXDPUV1_LAYERBLEND0_CONTROL_SECODDROWODDCOLDIS_MASK 0x3C00000U
+#define IMXDPUV1_LAYERBLEND0_CONTROL_SECODDROWODDCOLDIS_SHIFT 22U
+
+/* Register: IMXDPUV1_layerblend0_BlendControl */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL                    ((uint32_t)(0xA410))
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_OFFSET             ((uint32_t)(0x10))
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_RESET_VALUE        0x1010U
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK 0x7U
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT 0U
+/* Field Value: PRIM_C_BLD_FUNC__ZERO, Cout = Cin * 0  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ZERO 0U
+/* Field Value: PRIM_C_BLD_FUNC__ONE, Cout = Cin * 1  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE 0x1U
+/* Field Value: PRIM_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__PRIM_ALPHA 0x2U
+/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim)  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U
+/* Field Value: PRIM_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__SEC_ALPHA 0x4U
+/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec)  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U
+/* Field Value: PRIM_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__CONST_ALPHA 0x6U
+/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 -
+ * ALPHA_const)  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC_MASK 0x70U
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT 4U
+/* Field Value: SEC_C_BLD_FUNC__ZERO, Cout = Cin * 0  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ZERO 0U
+/* Field Value: SEC_C_BLD_FUNC__ONE, Cout = Cin * 1  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ONE 0x1U
+/* Field Value: SEC_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__PRIM_ALPHA 0x2U
+/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim)  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U
+/* Field Value: SEC_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__SEC_ALPHA 0x4U
+/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec)  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U
+/* Field Value: SEC_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA 0x6U
+/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - ALPHA_const)  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK 0x700U
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT 8U
+/* Field Value: PRIM_A_BLD_FUNC__ZERO, Aout = Ain * 0  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ZERO 0U
+/* Field Value: PRIM_A_BLD_FUNC__ONE, Aout = Ain * 1  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE 0x1U
+/* Field Value: PRIM_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__PRIM_ALPHA 0x2U
+/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim)  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U
+/* Field Value: PRIM_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__SEC_ALPHA 0x4U
+/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec)  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U
+/* Field Value: PRIM_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__CONST_ALPHA 0x6U
+/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 -
+ * ALPHA_const)  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC_MASK 0x7000U
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT 12U
+/* Field Value: SEC_A_BLD_FUNC__ZERO, Aout = Ain * 0  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ZERO 0U
+/* Field Value: SEC_A_BLD_FUNC__ONE, Aout = Ain * 1  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE 0x1U
+/* Field Value: SEC_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__PRIM_ALPHA 0x2U
+/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim)  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U
+/* Field Value: SEC_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__SEC_ALPHA 0x4U
+/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec)  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U
+/* Field Value: SEC_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__CONST_ALPHA 0x6U
+/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - ALPHA_const)  */
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_BLENDALPHA_MASK    0xFF0000U
+#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_BLENDALPHA_SHIFT   16U
+
+/* Register: IMXDPUV1_layerblend0_Position */
+#define IMXDPUV1_LAYERBLEND0_POSITION                        ((uint32_t)(0xA414))
+#define IMXDPUV1_LAYERBLEND0_POSITION_OFFSET                 ((uint32_t)(0x14))
+#define IMXDPUV1_LAYERBLEND0_POSITION_RESET_VALUE            0U
+#define IMXDPUV1_LAYERBLEND0_POSITION_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND0_POSITION_XPOS_MASK              0xFFFFU
+#define IMXDPUV1_LAYERBLEND0_POSITION_XPOS_SHIFT             0U
+#define IMXDPUV1_LAYERBLEND0_POSITION_YPOS_MASK              0xFFFF0000U
+#define IMXDPUV1_LAYERBLEND0_POSITION_YPOS_SHIFT             16U
+
+/* Register: IMXDPUV1_layerblend0_PrimControlWord */
+#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD                 ((uint32_t)(0xA418))
+#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_OFFSET          ((uint32_t)(0x18))
+#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_RESET_VALUE     0U
+#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_RESET_MASK      0U
+#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_P_VAL_MASK      0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_P_VAL_SHIFT     0U
+
+/* Register: IMXDPUV1_layerblend0_SecControlWord */
+#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD                  ((uint32_t)(0xA41C))
+#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_OFFSET           ((uint32_t)(0x1C))
+#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_RESET_VALUE      0U
+#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_RESET_MASK       0U
+#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_S_VAL_MASK       0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_S_VAL_SHIFT      0U
+
+/* Register: IMXDPUV1_layerblend1_LockUnlock */
+#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK                      ((uint32_t)(0xA800))
+#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_OFFSET               ((uint32_t)(0))
+#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_RESET_VALUE          0U
+#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_RESET_MASK           0U
+#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK_MASK      0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK_SHIFT     0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_layerblend1_LockStatus */
+#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS                      ((uint32_t)(0xA804))
+#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_OFFSET               ((uint32_t)(0x4))
+#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_RESET_VALUE          0U
+#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_LOCKSTATUS_MASK      0x1U
+#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_LOCKSTATUS_SHIFT     0U
+#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_FREEZESTATUS_MASK    0x100U
+#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_FREEZESTATUS_SHIFT   8U
+
+/* Register: IMXDPUV1_layerblend1_StaticControl */
+#define IMXDPUV1_LAYERBLEND1_STATICCONTROL                   ((uint32_t)(0xA808))
+#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_OFFSET            ((uint32_t)(0x8))
+#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_RESET_VALUE       0x14U
+#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDEN_MASK        0x1U
+#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDEN_SHIFT       0U
+#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL_MASK     0x6U
+#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL_SHIFT    1U
+/* Field Value: SHDLDSEL__PRIMARY, Load shadows with shadow load token on
+ * primary input (background plane).  */
+#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL__PRIMARY 0U
+/* Field Value: SHDLDSEL__SECONDARY, Load shadows with shadow load token on
+ * secondary input (foreground plane).  */
+#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL__SECONDARY 0x1U
+/* Field Value: SHDLDSEL__BOTH, Load shadows with shadow load token on any
+ * input.  */
+#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL__BOTH    0x2U
+#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL_MASK    0x18U
+#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL_SHIFT   3U
+/* Field Value: SHDTOKSEL__PRIMARY, When a token was received on the primary
+ * input (background plane).  */
+#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL__PRIMARY 0U
+/* Field Value: SHDTOKSEL__SECONDARY, When a token was received on the secondary
+ * input (foreground plane).  */
+#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL__SECONDARY 0x1U
+/* Field Value: SHDTOKSEL__BOTH, When a token was received on any input.  */
+#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL__BOTH   0x2U
+
+/* Register: IMXDPUV1_layerblend1_Control */
+#define IMXDPUV1_LAYERBLEND1_CONTROL                         ((uint32_t)(0xA80C))
+#define IMXDPUV1_LAYERBLEND1_CONTROL_OFFSET                  ((uint32_t)(0xC))
+#define IMXDPUV1_LAYERBLEND1_CONTROL_RESET_VALUE             0x1U
+#define IMXDPUV1_LAYERBLEND1_CONTROL_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND1_CONTROL_MODE_MASK               0x1U
+#define IMXDPUV1_LAYERBLEND1_CONTROL_MODE_SHIFT              0U
+/* Field Value: MODE__NEUTRAL, Module is in neutral mode. Output is same as
+ * primary input.  */
+#define IMXDPUV1_LAYERBLEND1_CONTROL_MODE__NEUTRAL           0U
+/* Field Value: MODE__BLEND, Module is in blending mode.  */
+#define IMXDPUV1_LAYERBLEND1_CONTROL_MODE__BLEND             0x1U
+#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKENABLE_MASK    0x4U
+#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKENABLE_SHIFT   2U
+/* Field Value: ALPHAMASKENABLE__DISABLE, AlphaMask feature disabled  */
+#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKENABLE__DISABLE 0U
+/* Field Value: ALPHAMASKENABLE__ENABLE, AlphaMask feature enabled  */
+#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKENABLE__ENABLE 0x1U
+#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE_MASK      0x70U
+#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE_SHIFT     4U
+/* Field Value: ALPHAMASKMODE__PRIM, Areas with primary input alpha > 128
+ * will be mapped to 255 and the rest will have an alpha value of 0  */
+#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM     0U
+/* Field Value: ALPHAMASKMODE__SEC, The area of the secondary input will get
+ * an alpha value of 255 and the rest will be 0  */
+#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__SEC      0x1U
+/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC, Behaves as if the output of modes
+ * PRIM and SEC would be ORed together  */
+#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC 0x2U
+/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC, Behaves as if the output of modes
+ * PRIM and SEC would be ANDed together  */
+#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC 0x3U
+/* Field Value: ALPHAMASKMODE__PRIM_INV, Behaves as if the output of mode
+ * PRIM would be inverted  */
+#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_INV 0x4U
+/* Field Value: ALPHAMASKMODE__SEC_INV, Behaves as if the output of mode SEC
+ * would be inverted  */
+#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__SEC_INV  0x5U
+/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC_INV, Behaves as if the output of
+ * modes PRIM and SEC_INV would be ORed together  */
+#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC_INV 0x6U
+/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC_INV, Behaves as if the output
+ * of modes PRIM and SEC_INV would be ANDed together  */
+#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC_INV 0x7U
+#define IMXDPUV1_LAYERBLEND1_CONTROL_SECLOWPASSEN_MASK       0x100U
+#define IMXDPUV1_LAYERBLEND1_CONTROL_SECLOWPASSEN_SHIFT      8U
+#define IMXDPUV1_LAYERBLEND1_CONTROL_SECREPLICATEEN_MASK     0x200U
+#define IMXDPUV1_LAYERBLEND1_CONTROL_SECREPLICATEEN_SHIFT    9U
+#define IMXDPUV1_LAYERBLEND1_CONTROL_SECEVENROWEVENCOLDIS_MASK 0x3C00U
+#define IMXDPUV1_LAYERBLEND1_CONTROL_SECEVENROWEVENCOLDIS_SHIFT 10U
+#define IMXDPUV1_LAYERBLEND1_CONTROL_SECEVENROWODDCOLDIS_MASK 0x3C000U
+#define IMXDPUV1_LAYERBLEND1_CONTROL_SECEVENROWODDCOLDIS_SHIFT 14U
+#define IMXDPUV1_LAYERBLEND1_CONTROL_SECODDROWEVENCOLDIS_MASK 0x3C0000U
+#define IMXDPUV1_LAYERBLEND1_CONTROL_SECODDROWEVENCOLDIS_SHIFT 18U
+#define IMXDPUV1_LAYERBLEND1_CONTROL_SECODDROWODDCOLDIS_MASK 0x3C00000U
+#define IMXDPUV1_LAYERBLEND1_CONTROL_SECODDROWODDCOLDIS_SHIFT 22U
+
+/* Register: IMXDPUV1_layerblend1_BlendControl */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL                    ((uint32_t)(0xA810))
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_OFFSET             ((uint32_t)(0x10))
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_RESET_VALUE        0x1010U
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK 0x7U
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT 0U
+/* Field Value: PRIM_C_BLD_FUNC__ZERO, Cout = Cin * 0  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ZERO 0U
+/* Field Value: PRIM_C_BLD_FUNC__ONE, Cout = Cin * 1  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE 0x1U
+/* Field Value: PRIM_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__PRIM_ALPHA 0x2U
+/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim)  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U
+/* Field Value: PRIM_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__SEC_ALPHA 0x4U
+/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec)  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U
+/* Field Value: PRIM_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__CONST_ALPHA 0x6U
+/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 -
+ * ALPHA_const)  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC_MASK 0x70U
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT 4U
+/* Field Value: SEC_C_BLD_FUNC__ZERO, Cout = Cin * 0  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ZERO 0U
+/* Field Value: SEC_C_BLD_FUNC__ONE, Cout = Cin * 1  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ONE 0x1U
+/* Field Value: SEC_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__PRIM_ALPHA 0x2U
+/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim)  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U
+/* Field Value: SEC_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__SEC_ALPHA 0x4U
+/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec)  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U
+/* Field Value: SEC_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA 0x6U
+/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - ALPHA_const)  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK 0x700U
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT 8U
+/* Field Value: PRIM_A_BLD_FUNC__ZERO, Aout = Ain * 0  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ZERO 0U
+/* Field Value: PRIM_A_BLD_FUNC__ONE, Aout = Ain * 1  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE 0x1U
+/* Field Value: PRIM_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__PRIM_ALPHA 0x2U
+/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim)  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U
+/* Field Value: PRIM_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__SEC_ALPHA 0x4U
+/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec)  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U
+/* Field Value: PRIM_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__CONST_ALPHA 0x6U
+/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 -
+ * ALPHA_const)  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC_MASK 0x7000U
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT 12U
+/* Field Value: SEC_A_BLD_FUNC__ZERO, Aout = Ain * 0  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ZERO 0U
+/* Field Value: SEC_A_BLD_FUNC__ONE, Aout = Ain * 1  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ONE 0x1U
+/* Field Value: SEC_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__PRIM_ALPHA 0x2U
+/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim)  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U
+/* Field Value: SEC_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__SEC_ALPHA 0x4U
+/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec)  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U
+/* Field Value: SEC_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__CONST_ALPHA 0x6U
+/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - ALPHA_const)  */
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_BLENDALPHA_MASK    0xFF0000U
+#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_BLENDALPHA_SHIFT   16U
+
+/* Register: IMXDPUV1_layerblend1_Position */
+#define IMXDPUV1_LAYERBLEND1_POSITION                        ((uint32_t)(0xA814))
+#define IMXDPUV1_LAYERBLEND1_POSITION_OFFSET                 ((uint32_t)(0x14))
+#define IMXDPUV1_LAYERBLEND1_POSITION_RESET_VALUE            0U
+#define IMXDPUV1_LAYERBLEND1_POSITION_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND1_POSITION_XPOS_MASK              0xFFFFU
+#define IMXDPUV1_LAYERBLEND1_POSITION_XPOS_SHIFT             0U
+#define IMXDPUV1_LAYERBLEND1_POSITION_YPOS_MASK              0xFFFF0000U
+#define IMXDPUV1_LAYERBLEND1_POSITION_YPOS_SHIFT             16U
+
+/* Register: IMXDPUV1_layerblend1_PrimControlWord */
+#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD                 ((uint32_t)(0xA818))
+#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_OFFSET          ((uint32_t)(0x18))
+#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_RESET_VALUE     0U
+#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_RESET_MASK      0U
+#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_P_VAL_MASK      0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_P_VAL_SHIFT     0U
+
+/* Register: IMXDPUV1_layerblend1_SecControlWord */
+#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD                  ((uint32_t)(0xA81C))
+#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_OFFSET           ((uint32_t)(0x1C))
+#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_RESET_VALUE      0U
+#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_RESET_MASK       0U
+#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_S_VAL_MASK       0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_S_VAL_SHIFT      0U
+
+/* Register: IMXDPUV1_layerblend2_LockUnlock */
+#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK                      ((uint32_t)(0xAC00))
+#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_OFFSET               ((uint32_t)(0))
+#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_RESET_VALUE          0U
+#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_RESET_MASK           0U
+#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK_MASK      0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK_SHIFT     0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_layerblend2_LockStatus */
+#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS                      ((uint32_t)(0xAC04))
+#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_OFFSET               ((uint32_t)(0x4))
+#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_RESET_VALUE          0U
+#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_LOCKSTATUS_MASK      0x1U
+#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_LOCKSTATUS_SHIFT     0U
+#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_FREEZESTATUS_MASK    0x100U
+#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_FREEZESTATUS_SHIFT   8U
+
+/* Register: IMXDPUV1_layerblend2_StaticControl */
+#define IMXDPUV1_LAYERBLEND2_STATICCONTROL                   ((uint32_t)(0xAC08))
+#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_OFFSET            ((uint32_t)(0x8))
+#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_RESET_VALUE       0x14U
+#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDEN_MASK        0x1U
+#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDEN_SHIFT       0U
+#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL_MASK     0x6U
+#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL_SHIFT    1U
+/* Field Value: SHDLDSEL__PRIMARY, Load shadows with shadow load token on
+ * primary input (background plane).  */
+#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL__PRIMARY 0U
+/* Field Value: SHDLDSEL__SECONDARY, Load shadows with shadow load token on
+ * secondary input (foreground plane).  */
+#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL__SECONDARY 0x1U
+/* Field Value: SHDLDSEL__BOTH, Load shadows with shadow load token on any
+ * input.  */
+#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL__BOTH    0x2U
+#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL_MASK    0x18U
+#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL_SHIFT   3U
+/* Field Value: SHDTOKSEL__PRIMARY, When a token was received on the primary
+ * input (background plane).  */
+#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL__PRIMARY 0U
+/* Field Value: SHDTOKSEL__SECONDARY, When a token was received on the secondary
+ * input (foreground plane).  */
+#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL__SECONDARY 0x1U
+/* Field Value: SHDTOKSEL__BOTH, When a token was received on any input.  */
+#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL__BOTH   0x2U
+
+/* Register: IMXDPUV1_layerblend2_Control */
+#define IMXDPUV1_LAYERBLEND2_CONTROL                         ((uint32_t)(0xAC0C))
+#define IMXDPUV1_LAYERBLEND2_CONTROL_OFFSET                  ((uint32_t)(0xC))
+#define IMXDPUV1_LAYERBLEND2_CONTROL_RESET_VALUE             0x1U
+#define IMXDPUV1_LAYERBLEND2_CONTROL_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND2_CONTROL_MODE_MASK               0x1U
+#define IMXDPUV1_LAYERBLEND2_CONTROL_MODE_SHIFT              0U
+/* Field Value: MODE__NEUTRAL, Module is in neutral mode. Output is same as
+ * primary input.  */
+#define IMXDPUV1_LAYERBLEND2_CONTROL_MODE__NEUTRAL           0U
+/* Field Value: MODE__BLEND, Module is in blending mode.  */
+#define IMXDPUV1_LAYERBLEND2_CONTROL_MODE__BLEND             0x1U
+#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKENABLE_MASK    0x4U
+#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKENABLE_SHIFT   2U
+/* Field Value: ALPHAMASKENABLE__DISABLE, AlphaMask feature disabled  */
+#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKENABLE__DISABLE 0U
+/* Field Value: ALPHAMASKENABLE__ENABLE, AlphaMask feature enabled  */
+#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKENABLE__ENABLE 0x1U
+#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE_MASK      0x70U
+#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE_SHIFT     4U
+/* Field Value: ALPHAMASKMODE__PRIM, Areas with primary input alpha > 128
+ * will be mapped to 255 and the rest will have an alpha value of 0  */
+#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM     0U
+/* Field Value: ALPHAMASKMODE__SEC, The area of the secondary input will get
+ * an alpha value of 255 and the rest will be 0  */
+#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__SEC      0x1U
+/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC, Behaves as if the output of modes
+ * PRIM and SEC would be ORed together  */
+#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC 0x2U
+/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC, Behaves as if the output of modes
+ * PRIM and SEC would be ANDed together  */
+#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC 0x3U
+/* Field Value: ALPHAMASKMODE__PRIM_INV, Behaves as if the output of mode
+ * PRIM would be inverted  */
+#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_INV 0x4U
+/* Field Value: ALPHAMASKMODE__SEC_INV, Behaves as if the output of mode SEC
+ * would be inverted  */
+#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__SEC_INV  0x5U
+/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC_INV, Behaves as if the output of
+ * modes PRIM and SEC_INV would be ORed together  */
+#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC_INV 0x6U
+/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC_INV, Behaves as if the output
+ * of modes PRIM and SEC_INV would be ANDed together  */
+#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC_INV 0x7U
+#define IMXDPUV1_LAYERBLEND2_CONTROL_SECLOWPASSEN_MASK       0x100U
+#define IMXDPUV1_LAYERBLEND2_CONTROL_SECLOWPASSEN_SHIFT      8U
+#define IMXDPUV1_LAYERBLEND2_CONTROL_SECREPLICATEEN_MASK     0x200U
+#define IMXDPUV1_LAYERBLEND2_CONTROL_SECREPLICATEEN_SHIFT    9U
+#define IMXDPUV1_LAYERBLEND2_CONTROL_SECEVENROWEVENCOLDIS_MASK 0x3C00U
+#define IMXDPUV1_LAYERBLEND2_CONTROL_SECEVENROWEVENCOLDIS_SHIFT 10U
+#define IMXDPUV1_LAYERBLEND2_CONTROL_SECEVENROWODDCOLDIS_MASK 0x3C000U
+#define IMXDPUV1_LAYERBLEND2_CONTROL_SECEVENROWODDCOLDIS_SHIFT 14U
+#define IMXDPUV1_LAYERBLEND2_CONTROL_SECODDROWEVENCOLDIS_MASK 0x3C0000U
+#define IMXDPUV1_LAYERBLEND2_CONTROL_SECODDROWEVENCOLDIS_SHIFT 18U
+#define IMXDPUV1_LAYERBLEND2_CONTROL_SECODDROWODDCOLDIS_MASK 0x3C00000U
+#define IMXDPUV1_LAYERBLEND2_CONTROL_SECODDROWODDCOLDIS_SHIFT 22U
+
+/* Register: IMXDPUV1_layerblend2_BlendControl */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL                    ((uint32_t)(0xAC10))
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_OFFSET             ((uint32_t)(0x10))
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_RESET_VALUE        0x1010U
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK 0x7U
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT 0U
+/* Field Value: PRIM_C_BLD_FUNC__ZERO, Cout = Cin * 0  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ZERO 0U
+/* Field Value: PRIM_C_BLD_FUNC__ONE, Cout = Cin * 1  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE 0x1U
+/* Field Value: PRIM_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__PRIM_ALPHA 0x2U
+/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim)  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U
+/* Field Value: PRIM_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__SEC_ALPHA 0x4U
+/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec)  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U
+/* Field Value: PRIM_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__CONST_ALPHA 0x6U
+/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 -
+ * ALPHA_const)  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC_MASK 0x70U
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT 4U
+/* Field Value: SEC_C_BLD_FUNC__ZERO, Cout = Cin * 0  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ZERO 0U
+/* Field Value: SEC_C_BLD_FUNC__ONE, Cout = Cin * 1  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ONE 0x1U
+/* Field Value: SEC_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__PRIM_ALPHA 0x2U
+/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim)  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U
+/* Field Value: SEC_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__SEC_ALPHA 0x4U
+/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec)  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U
+/* Field Value: SEC_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA 0x6U
+/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - ALPHA_const)  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK 0x700U
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT 8U
+/* Field Value: PRIM_A_BLD_FUNC__ZERO, Aout = Ain * 0  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ZERO 0U
+/* Field Value: PRIM_A_BLD_FUNC__ONE, Aout = Ain * 1  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE 0x1U
+/* Field Value: PRIM_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__PRIM_ALPHA 0x2U
+/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim)  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U
+/* Field Value: PRIM_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__SEC_ALPHA 0x4U
+/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec)  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U
+/* Field Value: PRIM_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__CONST_ALPHA 0x6U
+/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 -
+ * ALPHA_const)  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC_MASK 0x7000U
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT 12U
+/* Field Value: SEC_A_BLD_FUNC__ZERO, Aout = Ain * 0  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ZERO 0U
+/* Field Value: SEC_A_BLD_FUNC__ONE, Aout = Ain * 1  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ONE 0x1U
+/* Field Value: SEC_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__PRIM_ALPHA 0x2U
+/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim)  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U
+/* Field Value: SEC_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__SEC_ALPHA 0x4U
+/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec)  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U
+/* Field Value: SEC_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__CONST_ALPHA 0x6U
+/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - ALPHA_const)  */
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_BLENDALPHA_MASK    0xFF0000U
+#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_BLENDALPHA_SHIFT   16U
+
+/* Register: IMXDPUV1_layerblend2_Position */
+#define IMXDPUV1_LAYERBLEND2_POSITION                        ((uint32_t)(0xAC14))
+#define IMXDPUV1_LAYERBLEND2_POSITION_OFFSET                 ((uint32_t)(0x14))
+#define IMXDPUV1_LAYERBLEND2_POSITION_RESET_VALUE            0U
+#define IMXDPUV1_LAYERBLEND2_POSITION_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND2_POSITION_XPOS_MASK              0xFFFFU
+#define IMXDPUV1_LAYERBLEND2_POSITION_XPOS_SHIFT             0U
+#define IMXDPUV1_LAYERBLEND2_POSITION_YPOS_MASK              0xFFFF0000U
+#define IMXDPUV1_LAYERBLEND2_POSITION_YPOS_SHIFT             16U
+
+/* Register: IMXDPUV1_layerblend2_PrimControlWord */
+#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD                 ((uint32_t)(0xAC18))
+#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_OFFSET          ((uint32_t)(0x18))
+#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_RESET_VALUE     0U
+#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_RESET_MASK      0U
+#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_P_VAL_MASK      0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_P_VAL_SHIFT     0U
+
+/* Register: IMXDPUV1_layerblend2_SecControlWord */
+#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD                  ((uint32_t)(0xAC1C))
+#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_OFFSET           ((uint32_t)(0x1C))
+#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_RESET_VALUE      0U
+#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_RESET_MASK       0U
+#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_S_VAL_MASK       0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_S_VAL_SHIFT      0U
+
+/* Register: IMXDPUV1_layerblend3_LockUnlock */
+#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK                      ((uint32_t)(0xB000))
+#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_OFFSET               ((uint32_t)(0))
+#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_RESET_VALUE          0U
+#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_RESET_MASK           0U
+#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK_MASK      0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK_SHIFT     0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_layerblend3_LockStatus */
+#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS                      ((uint32_t)(0xB004))
+#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_OFFSET               ((uint32_t)(0x4))
+#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_RESET_VALUE          0U
+#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_LOCKSTATUS_MASK      0x1U
+#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_LOCKSTATUS_SHIFT     0U
+#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U
+#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U
+#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_FREEZESTATUS_MASK    0x100U
+#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_FREEZESTATUS_SHIFT   8U
+
+/* Register: IMXDPUV1_layerblend3_StaticControl */
+#define IMXDPUV1_LAYERBLEND3_STATICCONTROL                   ((uint32_t)(0xB008))
+#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_OFFSET            ((uint32_t)(0x8))
+#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_RESET_VALUE       0x14U
+#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_RESET_MASK        0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDEN_MASK        0x1U
+#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDEN_SHIFT       0U
+#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL_MASK     0x6U
+#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL_SHIFT    1U
+/* Field Value: SHDLDSEL__PRIMARY, Load shadows with shadow load token on
+ * primary input (background plane).  */
+#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL__PRIMARY 0U
+/* Field Value: SHDLDSEL__SECONDARY, Load shadows with shadow load token on
+ * secondary input (foreground plane).  */
+#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL__SECONDARY 0x1U
+/* Field Value: SHDLDSEL__BOTH, Load shadows with shadow load token on any
+ * input.  */
+#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL__BOTH    0x2U
+#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL_MASK    0x18U
+#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL_SHIFT   3U
+/* Field Value: SHDTOKSEL__PRIMARY, When a token was received on the primary
+ * input (background plane).  */
+#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL__PRIMARY 0U
+/* Field Value: SHDTOKSEL__SECONDARY, When a token was received on the secondary
+ * input (foreground plane).  */
+#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL__SECONDARY 0x1U
+/* Field Value: SHDTOKSEL__BOTH, When a token was received on any input.  */
+#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL__BOTH   0x2U
+
+/* Register: IMXDPUV1_layerblend3_Control */
+#define IMXDPUV1_LAYERBLEND3_CONTROL                         ((uint32_t)(0xB00C))
+#define IMXDPUV1_LAYERBLEND3_CONTROL_OFFSET                  ((uint32_t)(0xC))
+#define IMXDPUV1_LAYERBLEND3_CONTROL_RESET_VALUE             0x1U
+#define IMXDPUV1_LAYERBLEND3_CONTROL_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND3_CONTROL_MODE_MASK               0x1U
+#define IMXDPUV1_LAYERBLEND3_CONTROL_MODE_SHIFT              0U
+/* Field Value: MODE__NEUTRAL, Module is in neutral mode. Output is same as
+ * primary input.  */
+#define IMXDPUV1_LAYERBLEND3_CONTROL_MODE__NEUTRAL           0U
+/* Field Value: MODE__BLEND, Module is in blending mode.  */
+#define IMXDPUV1_LAYERBLEND3_CONTROL_MODE__BLEND             0x1U
+#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKENABLE_MASK    0x4U
+#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKENABLE_SHIFT   2U
+/* Field Value: ALPHAMASKENABLE__DISABLE, AlphaMask feature disabled  */
+#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKENABLE__DISABLE 0U
+/* Field Value: ALPHAMASKENABLE__ENABLE, AlphaMask feature enabled  */
+#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKENABLE__ENABLE 0x1U
+#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE_MASK      0x70U
+#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE_SHIFT     4U
+/* Field Value: ALPHAMASKMODE__PRIM, Areas with primary input alpha > 128
+ * will be mapped to 255 and the rest will have an alpha value of 0  */
+#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM     0U
+/* Field Value: ALPHAMASKMODE__SEC, The area of the secondary input will get
+ * an alpha value of 255 and the rest will be 0  */
+#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__SEC      0x1U
+/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC, Behaves as if the output of modes
+ * PRIM and SEC would be ORed together  */
+#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC 0x2U
+/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC, Behaves as if the output of modes
+ * PRIM and SEC would be ANDed together  */
+#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC 0x3U
+/* Field Value: ALPHAMASKMODE__PRIM_INV, Behaves as if the output of mode
+ * PRIM would be inverted  */
+#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_INV 0x4U
+/* Field Value: ALPHAMASKMODE__SEC_INV, Behaves as if the output of mode SEC
+ * would be inverted  */
+#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__SEC_INV  0x5U
+/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC_INV, Behaves as if the output of
+ * modes PRIM and SEC_INV would be ORed together  */
+#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC_INV 0x6U
+/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC_INV, Behaves as if the output
+ * of modes PRIM and SEC_INV would be ANDed together  */
+#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC_INV 0x7U
+#define IMXDPUV1_LAYERBLEND3_CONTROL_SECLOWPASSEN_MASK       0x100U
+#define IMXDPUV1_LAYERBLEND3_CONTROL_SECLOWPASSEN_SHIFT      8U
+#define IMXDPUV1_LAYERBLEND3_CONTROL_SECREPLICATEEN_MASK     0x200U
+#define IMXDPUV1_LAYERBLEND3_CONTROL_SECREPLICATEEN_SHIFT    9U
+#define IMXDPUV1_LAYERBLEND3_CONTROL_SECEVENROWEVENCOLDIS_MASK 0x3C00U
+#define IMXDPUV1_LAYERBLEND3_CONTROL_SECEVENROWEVENCOLDIS_SHIFT 10U
+#define IMXDPUV1_LAYERBLEND3_CONTROL_SECEVENROWODDCOLDIS_MASK 0x3C000U
+#define IMXDPUV1_LAYERBLEND3_CONTROL_SECEVENROWODDCOLDIS_SHIFT 14U
+#define IMXDPUV1_LAYERBLEND3_CONTROL_SECODDROWEVENCOLDIS_MASK 0x3C0000U
+#define IMXDPUV1_LAYERBLEND3_CONTROL_SECODDROWEVENCOLDIS_SHIFT 18U
+#define IMXDPUV1_LAYERBLEND3_CONTROL_SECODDROWODDCOLDIS_MASK 0x3C00000U
+#define IMXDPUV1_LAYERBLEND3_CONTROL_SECODDROWODDCOLDIS_SHIFT 22U
+
+/* Register: IMXDPUV1_layerblend3_BlendControl */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL                    ((uint32_t)(0xB010))
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_OFFSET             ((uint32_t)(0x10))
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_RESET_VALUE        0x1010U
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK 0x7U
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT 0U
+/* Field Value: PRIM_C_BLD_FUNC__ZERO, Cout = Cin * 0  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ZERO 0U
+/* Field Value: PRIM_C_BLD_FUNC__ONE, Cout = Cin * 1  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE 0x1U
+/* Field Value: PRIM_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__PRIM_ALPHA 0x2U
+/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim)  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U
+/* Field Value: PRIM_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__SEC_ALPHA 0x4U
+/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec)  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U
+/* Field Value: PRIM_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__CONST_ALPHA 0x6U
+/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 -
+ * ALPHA_const)  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC_MASK 0x70U
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT 4U
+/* Field Value: SEC_C_BLD_FUNC__ZERO, Cout = Cin * 0  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ZERO 0U
+/* Field Value: SEC_C_BLD_FUNC__ONE, Cout = Cin * 1  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ONE 0x1U
+/* Field Value: SEC_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__PRIM_ALPHA 0x2U
+/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim)  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U
+/* Field Value: SEC_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__SEC_ALPHA 0x4U
+/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec)  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U
+/* Field Value: SEC_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA 0x6U
+/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - ALPHA_const)  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK 0x700U
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT 8U
+/* Field Value: PRIM_A_BLD_FUNC__ZERO, Aout = Ain * 0  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ZERO 0U
+/* Field Value: PRIM_A_BLD_FUNC__ONE, Aout = Ain * 1  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE 0x1U
+/* Field Value: PRIM_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__PRIM_ALPHA 0x2U
+/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim)  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U
+/* Field Value: PRIM_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__SEC_ALPHA 0x4U
+/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec)  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U
+/* Field Value: PRIM_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__CONST_ALPHA 0x6U
+/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 -
+ * ALPHA_const)  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC_MASK 0x7000U
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT 12U
+/* Field Value: SEC_A_BLD_FUNC__ZERO, Aout = Ain * 0  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ZERO 0U
+/* Field Value: SEC_A_BLD_FUNC__ONE, Aout = Ain * 1  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ONE 0x1U
+/* Field Value: SEC_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__PRIM_ALPHA 0x2U
+/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim)  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U
+/* Field Value: SEC_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__SEC_ALPHA 0x4U
+/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec)  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U
+/* Field Value: SEC_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__CONST_ALPHA 0x6U
+/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - ALPHA_const)  */
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_BLENDALPHA_MASK    0xFF0000U
+#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_BLENDALPHA_SHIFT   16U
+
+/* Register: IMXDPUV1_layerblend3_Position */
+#define IMXDPUV1_LAYERBLEND3_POSITION                        ((uint32_t)(0xB014))
+#define IMXDPUV1_LAYERBLEND3_POSITION_OFFSET                 ((uint32_t)(0x14))
+#define IMXDPUV1_LAYERBLEND3_POSITION_RESET_VALUE            0U
+#define IMXDPUV1_LAYERBLEND3_POSITION_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND3_POSITION_XPOS_MASK              0xFFFFU
+#define IMXDPUV1_LAYERBLEND3_POSITION_XPOS_SHIFT             0U
+#define IMXDPUV1_LAYERBLEND3_POSITION_YPOS_MASK              0xFFFF0000U
+#define IMXDPUV1_LAYERBLEND3_POSITION_YPOS_SHIFT             16U
+
+/* Register: IMXDPUV1_layerblend3_PrimControlWord */
+#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD                 ((uint32_t)(0xB018))
+#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_OFFSET          ((uint32_t)(0x18))
+#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_RESET_VALUE     0U
+#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_RESET_MASK      0U
+#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_P_VAL_MASK      0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_P_VAL_SHIFT     0U
+
+/* Register: IMXDPUV1_layerblend3_SecControlWord */
+#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD                  ((uint32_t)(0xB01C))
+#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_OFFSET           ((uint32_t)(0x1C))
+#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_RESET_VALUE      0U
+#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_RESET_MASK       0U
+#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_S_VAL_MASK       0xFFFFFFFFU
+#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_S_VAL_SHIFT      0U
+
+/* Register: IMXDPUV1_disengcfg_LockUnlock0 */
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0                       ((uint32_t)(0xB400))
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_OFFSET                ((uint32_t)(0))
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_RESET_VALUE           0U
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_RESET_MASK            0U
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0_MASK      0xFFFFFFFFU
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0_SHIFT     0U
+/* Field Value: LOCKUNLOCK0__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__LOCK_KEY 0x5651F763U
+/* Field Value: LOCKUNLOCK0__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK0__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK0__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK0__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_disengcfg_LockStatus0 */
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS0                       ((uint32_t)(0xB404))
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_OFFSET                ((uint32_t)(0x4))
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_RESET_VALUE           0U
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_LOCKSTATUS0_MASK      0x1U
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_LOCKSTATUS0_SHIFT     0U
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_PRIVILEGESTATUS0_MASK 0x10U
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_PRIVILEGESTATUS0_SHIFT 4U
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_FREEZESTATUS0_MASK    0x100U
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_FREEZESTATUS0_SHIFT   8U
+
+/* Register: IMXDPUV1_disengcfg_ClockCtrl0 */
+#define IMXDPUV1_DISENGCFG_CLOCKCTRL0                        ((uint32_t)(0xB408))
+#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_OFFSET                 ((uint32_t)(0x8))
+#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_RESET_VALUE            0x1U
+#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_DSPCLKDIVIDE0_MASK     0x1U
+#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_DSPCLKDIVIDE0_SHIFT    0U
+/* Field Value: DSPCLKDIVIDE0__DIV1, External display clock signal has pixel
+ * clock frequency.  */
+#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_DSPCLKDIVIDE0__DIV1    0U
+/* Field Value: DSPCLKDIVIDE0__DIV2, External display clock signal has twice
+ * the pixel clock frequency.  */
+#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_DSPCLKDIVIDE0__DIV2    0x1U
+
+/* Register: IMXDPUV1_disengcfg_PolarityCtrl0 */
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0                     ((uint32_t)(0xB40C))
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_OFFSET              ((uint32_t)(0xC))
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_RESET_VALUE         0x4U
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0_MASK         0x1U
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0_SHIFT        0U
+/* Field Value: POLHS0__LOW, Low active  */
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0__LOW         0U
+/* Field Value: POLHS0__HIGH, High active  */
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0__HIGH        0x1U
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0_MASK         0x2U
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0_SHIFT        1U
+/* Field Value: POLVS0__LOW, Low active  */
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0__LOW         0U
+/* Field Value: POLVS0__HIGH, High active  */
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0__HIGH        0x1U
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0_MASK         0x4U
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0_SHIFT        2U
+/* Field Value: POLEN0__LOW, Low active  */
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0__LOW         0U
+/* Field Value: POLEN0__HIGH, High active  */
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0__HIGH        0x1U
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_PIXINV0_MASK        0x8U
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_PIXINV0_SHIFT       3U
+/* Field Value: PIXINV0__NONINV, No inversion of pixel data  */
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_PIXINV0__NONINV     0U
+/* Field Value: PIXINV0__INV, Pixel data inverted (1. complement)  */
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_PIXINV0__INV        0x1U
+
+/* Register: IMXDPUV1_disengcfg_SrcSelect0 */
+#define IMXDPUV1_DISENGCFG_SRCSELECT0                        ((uint32_t)(0xB410))
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_OFFSET                 ((uint32_t)(0x10))
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_RESET_VALUE            0U
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0_MASK       0x3U
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0_SHIFT      0U
+/* Field Value: SIG_SELECT0__FRAMEGEN, Source is FrameGen#0 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0__FRAMEGEN  0U
+/* Field Value: SIG_SELECT0__GAMMACOR, Source is GammaCor#0 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0__GAMMACOR  0x1U
+/* Field Value: SIG_SELECT0__MATRIX, Source is Matrix#0 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0__MATRIX    0x2U
+/* Field Value: SIG_SELECT0__DITHER, Source is Dither#0 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0__DITHER    0x3U
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_PATH_SELECT0_MASK      0x10U
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_PATH_SELECT0_SHIFT     4U
+/* Field Value: PATH_SELECT0__GAMMA_FIRST, Framegen - Gamma - Matrix - Dither.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_PATH_SELECT0__GAMMA_FIRST 0U
+/* Field Value: PATH_SELECT0__MATRIX_FIRST, Framegen - Matrix - Gamma - Dither.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_PATH_SELECT0__MATRIX_FIRST 0x1U
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0_MASK     0x300U
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0_SHIFT    8U
+/* Field Value: DUMP0_SELECT0__FRAMEGEN, Source is FrameGen#0 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0__FRAMEGEN 0U
+/* Field Value: DUMP0_SELECT0__GAMMACOR, Source is GammaCor#0 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0__GAMMACOR 0x1U
+/* Field Value: DUMP0_SELECT0__MATRIX, Source is Matrix#0 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0__MATRIX  0x2U
+/* Field Value: DUMP0_SELECT0__DITHER, Source is Dither#0 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0__DITHER  0x3U
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0_MASK     0xC00U
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0_SHIFT    10U
+/* Field Value: DUMP1_SELECT0__FRAMEGEN, Source is FrameGen#0 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0__FRAMEGEN 0U
+/* Field Value: DUMP1_SELECT0__GAMMACOR, Source is GammaCor#0 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0__GAMMACOR 0x1U
+/* Field Value: DUMP1_SELECT0__MATRIX, Source is Matrix#0 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0__MATRIX  0x2U
+/* Field Value: DUMP1_SELECT0__DITHER, Source is Dither#0 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0__DITHER  0x3U
+
+/* Register: IMXDPUV1_disengcfg_LockUnlock1 */
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1                       ((uint32_t)(0xB420))
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_OFFSET                ((uint32_t)(0x20))
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_RESET_VALUE           0U
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_RESET_MASK            0U
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1_MASK      0xFFFFFFFFU
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1_SHIFT     0U
+/* Field Value: LOCKUNLOCK1__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__LOCK_KEY 0x5651F763U
+/* Field Value: LOCKUNLOCK1__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK1__PRIVILEGE_KEY, Enables privilege protection.
+ * Disabled after reset.  */
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK1__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK1__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_disengcfg_LockStatus1 */
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS1                       ((uint32_t)(0xB424))
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_OFFSET                ((uint32_t)(0x24))
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_RESET_VALUE           0U
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_LOCKSTATUS1_MASK      0x1U
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_LOCKSTATUS1_SHIFT     0U
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_PRIVILEGESTATUS1_MASK 0x10U
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_PRIVILEGESTATUS1_SHIFT 4U
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_FREEZESTATUS1_MASK    0x100U
+#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_FREEZESTATUS1_SHIFT   8U
+
+/* Register: IMXDPUV1_disengcfg_ClockCtrl1 */
+#define IMXDPUV1_DISENGCFG_CLOCKCTRL1                        ((uint32_t)(0xB428))
+#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_OFFSET                 ((uint32_t)(0x28))
+#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_RESET_VALUE            0x1U
+#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_DSPCLKDIVIDE1_MASK     0x1U
+#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_DSPCLKDIVIDE1_SHIFT    0U
+/* Field Value: DSPCLKDIVIDE1__DIV1, External display clock signal has pixel
+ * clock frequency.  */
+#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_DSPCLKDIVIDE1__DIV1    0U
+/* Field Value: DSPCLKDIVIDE1__DIV2, External display clock signal has twice
+ * the pixel clock frequency.  */
+#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_DSPCLKDIVIDE1__DIV2    0x1U
+
+/* Register: IMXDPUV1_disengcfg_PolarityCtrl1 */
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1                     ((uint32_t)(0xB42C))
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_OFFSET              ((uint32_t)(0x2C))
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_RESET_VALUE         0x4U
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1_MASK         0x1U
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1_SHIFT        0U
+/* Field Value: POLHS1__LOW, Low active  */
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1__LOW         0U
+/* Field Value: POLHS1__HIGH, High active  */
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1__HIGH        0x1U
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1_MASK         0x2U
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1_SHIFT        1U
+/* Field Value: POLVS1__LOW, Low active  */
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1__LOW         0U
+/* Field Value: POLVS1__HIGH, High active  */
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1__HIGH        0x1U
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1_MASK         0x4U
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1_SHIFT        2U
+/* Field Value: POLEN1__LOW, Low active  */
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1__LOW         0U
+/* Field Value: POLEN1__HIGH, High active  */
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1__HIGH        0x1U
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_PIXINV1_MASK        0x8U
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_PIXINV1_SHIFT       3U
+/* Field Value: PIXINV1__NONINV, No inversion of pixel data  */
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_PIXINV1__NONINV     0U
+/* Field Value: PIXINV1__INV, Pixel data inverted (1. complement)  */
+#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_PIXINV1__INV        0x1U
+
+/* Register: IMXDPUV1_disengcfg_SrcSelect1 */
+#define IMXDPUV1_DISENGCFG_SRCSELECT1                        ((uint32_t)(0xB430))
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_OFFSET                 ((uint32_t)(0x30))
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_RESET_VALUE            0U
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1_MASK       0x3U
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1_SHIFT      0U
+/* Field Value: SIG_SELECT1__FRAMEGEN, Source is FrameGen#1 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1__FRAMEGEN  0U
+/* Field Value: SIG_SELECT1__GAMMACOR, Source is GammaCor#1 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1__GAMMACOR  0x1U
+/* Field Value: SIG_SELECT1__MATRIX, Source is Matrix#1 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1__MATRIX    0x2U
+/* Field Value: SIG_SELECT1__DITHER, Source is Dither#1 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1__DITHER    0x3U
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_PATH_SELECT1_MASK      0x10U
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_PATH_SELECT1_SHIFT     4U
+/* Field Value: PATH_SELECT1__GAMMA_FIRST, Framegen - Gamma - Matrix - Dither.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_PATH_SELECT1__GAMMA_FIRST 0U
+/* Field Value: PATH_SELECT1__MATRIX_FIRST, Framegen - Matrix - Gamma - Dither.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_PATH_SELECT1__MATRIX_FIRST 0x1U
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1_MASK     0x300U
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1_SHIFT    8U
+/* Field Value: DUMP0_SELECT1__FRAMEGEN, Source is FrameGen#1 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1__FRAMEGEN 0U
+/* Field Value: DUMP0_SELECT1__GAMMACOR, Source is GammaCor#1 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1__GAMMACOR 0x1U
+/* Field Value: DUMP0_SELECT1__MATRIX, Source is Matrix#1 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1__MATRIX  0x2U
+/* Field Value: DUMP0_SELECT1__DITHER, Source is Dither#1 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1__DITHER  0x3U
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1_MASK     0xC00U
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1_SHIFT    10U
+/* Field Value: DUMP1_SELECT1__FRAMEGEN, Source is FrameGen#1 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1__FRAMEGEN 0U
+/* Field Value: DUMP1_SELECT1__GAMMACOR, Source is GammaCor#1 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1__GAMMACOR 0x1U
+/* Field Value: DUMP1_SELECT1__MATRIX, Source is Matrix#1 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1__MATRIX  0x2U
+/* Field Value: DUMP1_SELECT1__DITHER, Source is Dither#1 output.  */
+#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1__DITHER  0x3U
+
+/* Register: IMXDPUV1_framegen0_LockUnlock */
+#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK                        ((uint32_t)(0xB800))
+#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_OFFSET                 ((uint32_t)(0))
+#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_RESET_VALUE            0U
+#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_RESET_MASK             0U
+#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK_SHIFT       0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY   0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_framegen0_LockStatus */
+#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS                        ((uint32_t)(0xB804))
+#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_OFFSET                 ((uint32_t)(0x4))
+#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_RESET_VALUE            0U
+#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_LOCKSTATUS_MASK        0x1U
+#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_LOCKSTATUS_SHIFT       0U
+#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_PRIVILEGESTATUS_MASK   0x10U
+#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT  4U
+#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_FREEZESTATUS_MASK      0x100U
+#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_FREEZESTATUS_SHIFT     8U
+
+/* Register: IMXDPUV1_framegen0_FgStCtrl */
+#define IMXDPUV1_FRAMEGEN0_FGSTCTRL                          ((uint32_t)(0xB808))
+#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_OFFSET                   ((uint32_t)(0x8))
+#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_RESET_VALUE              0U
+#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_SHDEN_MASK               0x1U
+#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_SHDEN_SHIFT              0U
+#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE_MASK          0x6U
+#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE_SHIFT         1U
+/* Field Value: FGSYNCMODE__OFF, No side-by-side synchronization.  */
+#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__OFF          0U
+/* Field Value: FGSYNCMODE__MASTER, Framegen is master.  */
+#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__MASTER       0x1U
+/* Field Value: FGSYNCMODE__SLAVE_CYC, Framegen is slave. Runs in cyclic synchronization
+ * mode.  */
+#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__SLAVE_CYC    0x2U
+/* Field Value: FGSYNCMODE__SLAVE_ONCE, Framegen is slave. Runs in one time
+ * synchronization mode.  */
+#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__SLAVE_ONCE   0x3U
+
+/* Register: IMXDPUV1_framegen0_HtCfg1 */
+#define IMXDPUV1_FRAMEGEN0_HTCFG1                            ((uint32_t)(0xB80C))
+#define IMXDPUV1_FRAMEGEN0_HTCFG1_OFFSET                     ((uint32_t)(0xC))
+#define IMXDPUV1_FRAMEGEN0_HTCFG1_RESET_VALUE                0x18F0140U
+#define IMXDPUV1_FRAMEGEN0_HTCFG1_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_HTCFG1_HACT_MASK                  0x3FFFU
+#define IMXDPUV1_FRAMEGEN0_HTCFG1_HACT_SHIFT                 0U
+#define IMXDPUV1_FRAMEGEN0_HTCFG1_HTOTAL_MASK                0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN0_HTCFG1_HTOTAL_SHIFT               16U
+
+/* Register: IMXDPUV1_framegen0_HtCfg2 */
+#define IMXDPUV1_FRAMEGEN0_HTCFG2                            ((uint32_t)(0xB810))
+#define IMXDPUV1_FRAMEGEN0_HTCFG2_OFFSET                     ((uint32_t)(0x10))
+#define IMXDPUV1_FRAMEGEN0_HTCFG2_RESET_VALUE                0x8047001FU
+#define IMXDPUV1_FRAMEGEN0_HTCFG2_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSYNC_MASK                 0x3FFFU
+#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSYNC_SHIFT                0U
+#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSBP_MASK                  0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSBP_SHIFT                 16U
+#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSEN_MASK                  0x80000000U
+#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSEN_SHIFT                 31U
+
+/* Register: IMXDPUV1_framegen0_VtCfg1 */
+#define IMXDPUV1_FRAMEGEN0_VTCFG1                            ((uint32_t)(0xB814))
+#define IMXDPUV1_FRAMEGEN0_VTCFG1_OFFSET                     ((uint32_t)(0x14))
+#define IMXDPUV1_FRAMEGEN0_VTCFG1_RESET_VALUE                0xFC00F0U
+#define IMXDPUV1_FRAMEGEN0_VTCFG1_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_VTCFG1_VACT_MASK                  0x3FFFU
+#define IMXDPUV1_FRAMEGEN0_VTCFG1_VACT_SHIFT                 0U
+#define IMXDPUV1_FRAMEGEN0_VTCFG1_VTOTAL_MASK                0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN0_VTCFG1_VTOTAL_SHIFT               16U
+
+/* Register: IMXDPUV1_framegen0_VtCfg2 */
+#define IMXDPUV1_FRAMEGEN0_VTCFG2                            ((uint32_t)(0xB818))
+#define IMXDPUV1_FRAMEGEN0_VTCFG2_OFFSET                     ((uint32_t)(0x18))
+#define IMXDPUV1_FRAMEGEN0_VTCFG2_RESET_VALUE                0x80090003U
+#define IMXDPUV1_FRAMEGEN0_VTCFG2_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSYNC_MASK                 0x3FFFU
+#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSYNC_SHIFT                0U
+#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSBP_MASK                  0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSBP_SHIFT                 16U
+#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSEN_MASK                  0x80000000U
+#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSEN_SHIFT                 31U
+
+/* Register: IMXDPUV1_framegen0_Int0Config */
+#define IMXDPUV1_FRAMEGEN0_INT0CONFIG                        ((uint32_t)(0xB81C))
+#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_OFFSET                 ((uint32_t)(0x1C))
+#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_RESET_VALUE            0U
+#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0COL_MASK           0x3FFFU
+#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0COL_SHIFT          0U
+#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0HSEN_MASK          0x8000U
+#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0HSEN_SHIFT         15U
+#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0ROW_MASK           0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0ROW_SHIFT          16U
+#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0EN_MASK            0x80000000U
+#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0EN_SHIFT           31U
+
+/* Register: IMXDPUV1_framegen0_Int1Config */
+#define IMXDPUV1_FRAMEGEN0_INT1CONFIG                        ((uint32_t)(0xB820))
+#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_OFFSET                 ((uint32_t)(0x20))
+#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_RESET_VALUE            0U
+#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1COL_MASK           0x3FFFU
+#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1COL_SHIFT          0U
+#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1HSEN_MASK          0x8000U
+#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1HSEN_SHIFT         15U
+#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1ROW_MASK           0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1ROW_SHIFT          16U
+#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1EN_MASK            0x80000000U
+#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1EN_SHIFT           31U
+
+/* Register: IMXDPUV1_framegen0_Int2Config */
+#define IMXDPUV1_FRAMEGEN0_INT2CONFIG                        ((uint32_t)(0xB824))
+#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_OFFSET                 ((uint32_t)(0x24))
+#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_RESET_VALUE            0U
+#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2COL_MASK           0x3FFFU
+#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2COL_SHIFT          0U
+#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2HSEN_MASK          0x8000U
+#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2HSEN_SHIFT         15U
+#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2ROW_MASK           0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2ROW_SHIFT          16U
+#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2EN_MASK            0x80000000U
+#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2EN_SHIFT           31U
+
+/* Register: IMXDPUV1_framegen0_Int3Config */
+#define IMXDPUV1_FRAMEGEN0_INT3CONFIG                        ((uint32_t)(0xB828))
+#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_OFFSET                 ((uint32_t)(0x28))
+#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_RESET_VALUE            0U
+#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3COL_MASK           0x3FFFU
+#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3COL_SHIFT          0U
+#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3HSEN_MASK          0x8000U
+#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3HSEN_SHIFT         15U
+#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3ROW_MASK           0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3ROW_SHIFT          16U
+#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3EN_MASK            0x80000000U
+#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3EN_SHIFT           31U
+
+/* Register: IMXDPUV1_framegen0_PKickConfig */
+#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG                       ((uint32_t)(0xB82C))
+#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_OFFSET                ((uint32_t)(0x2C))
+#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_RESET_VALUE           0xF00140U
+#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKCOL_MASK         0x3FFFU
+#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKCOL_SHIFT        0U
+#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKINT0EN_MASK      0x8000U
+#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKINT0EN_SHIFT     15U
+#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKROW_MASK         0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKROW_SHIFT        16U
+#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKEN_MASK          0x80000000U
+#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKEN_SHIFT         31U
+
+/* Register: IMXDPUV1_framegen0_SKickConfig */
+#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG                       ((uint32_t)(0xB830))
+#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_OFFSET                ((uint32_t)(0x30))
+#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_RESET_VALUE           0xF00140U
+#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKCOL_MASK         0x3FFFU
+#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKCOL_SHIFT        0U
+#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKINT1EN_MASK      0x8000U
+#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKINT1EN_SHIFT     15U
+#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKROW_MASK         0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKROW_SHIFT        16U
+#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKTRIG_MASK        0x40000000U
+#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKTRIG_SHIFT       30U
+/* Field Value: SKICKTRIG__INTERNAL, Use internal skick signal, trigger point
+ * defined by SKickRow and SKickCol.  */
+#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKTRIG__INTERNAL   0U
+/* Field Value: SKICKTRIG__EXTERNAL, Use external skick input as trigger.  */
+#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKTRIG__EXTERNAL   0x1U
+#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKEN_MASK          0x80000000U
+#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKEN_SHIFT         31U
+
+/* Register: IMXDPUV1_framegen0_SecStatConfig */
+#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG                     ((uint32_t)(0xB834))
+#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_OFFSET              ((uint32_t)(0x34))
+#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_RESET_VALUE         0x112U
+#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVGOODFRAMES_MASK  0xFU
+#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVGOODFRAMES_SHIFT 0U
+#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVBADFRAMES_MASK   0xF0U
+#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVBADFRAMES_SHIFT  4U
+#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVSKEWINRANGE_MASK 0xF00U
+#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVSKEWINRANGE_SHIFT 8U
+
+/* Register: IMXDPUV1_framegen0_FgSRCR1 */
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1                           ((uint32_t)(0xB838))
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_OFFSET                    ((uint32_t)(0x38))
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_RESET_VALUE               0U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREN_MASK                 0x1U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREN_SHIFT                0U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE_MASK               0x6U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE_SHIFT              1U
+/* Field Value: SRMODE__OFF, Skew Regulation is off.  */
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE__OFF               0U
+/* Field Value: SRMODE__HREG, Horizontal regulation enabled.  */
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE__HREG              0x1U
+/* Field Value: SRMODE__VREG, Vertical regulation enabled.  */
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE__VREG              0x2U
+/* Field Value: SRMODE__BOTH, Both regulation modes are enabled.  */
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE__BOTH              0x3U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRADJ_MASK                0x8U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRADJ_SHIFT               3U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREVEN_MASK               0x10U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREVEN_SHIFT              4U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRFASTSYNC_MASK           0x20U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRFASTSYNC_SHIFT          5U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQALIGN_MASK             0x40U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQALIGN_SHIFT            6U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL_MASK               0x180U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL_SHIFT              7U
+/* Field Value: SRQVAL__ZERO, Fixed two LSB values of HTOTAL are 0b00.  */
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL__ZERO              0U
+/* Field Value: SRQVAL__ONE, Fixed two LSB values of HTOTAL are 0b01.  */
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL__ONE               0x1U
+/* Field Value: SRQVAL__TWO, Fixed two LSB values of HTOTAL are 0b10.  */
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL__TWO               0x2U
+/* Field Value: SRQVAL__THREE, Fixed two LSB values of HTOTAL are 0b11.  */
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL__THREE             0x3U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRDBGDISP_MASK            0x10000U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRDBGDISP_SHIFT           16U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREPOFF_MASK              0x20000U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREPOFF_SHIFT             17U
+
+/* Register: IMXDPUV1_framegen0_FgSRCR2 */
+#define IMXDPUV1_FRAMEGEN0_FGSRCR2                           ((uint32_t)(0xB83C))
+#define IMXDPUV1_FRAMEGEN0_FGSRCR2_OFFSET                    ((uint32_t)(0x3C))
+#define IMXDPUV1_FRAMEGEN0_FGSRCR2_RESET_VALUE               0x1B70188U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR2_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSRCR2_HTOTALMIN_MASK            0x3FFFU
+#define IMXDPUV1_FRAMEGEN0_FGSRCR2_HTOTALMIN_SHIFT           0U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR2_HTOTALMAX_MASK            0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR2_HTOTALMAX_SHIFT           16U
+
+/* Register: IMXDPUV1_framegen0_FgSRCR3 */
+#define IMXDPUV1_FRAMEGEN0_FGSRCR3                           ((uint32_t)(0xB840))
+#define IMXDPUV1_FRAMEGEN0_FGSRCR3_OFFSET                    ((uint32_t)(0x40))
+#define IMXDPUV1_FRAMEGEN0_FGSRCR3_RESET_VALUE               0x11500FBU
+#define IMXDPUV1_FRAMEGEN0_FGSRCR3_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSRCR3_VTOTALMIN_MASK            0x3FFFU
+#define IMXDPUV1_FRAMEGEN0_FGSRCR3_VTOTALMIN_SHIFT           0U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR3_VTOTALMAX_MASK            0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR3_VTOTALMAX_SHIFT           16U
+
+/* Register: IMXDPUV1_framegen0_FgSRCR4 */
+#define IMXDPUV1_FRAMEGEN0_FGSRCR4                           ((uint32_t)(0xB844))
+#define IMXDPUV1_FRAMEGEN0_FGSRCR4_OFFSET                    ((uint32_t)(0x44))
+#define IMXDPUV1_FRAMEGEN0_FGSRCR4_RESET_VALUE               0xC8U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR4_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSRCR4_TARGETSKEW_MASK           0x1FFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSRCR4_TARGETSKEW_SHIFT          0U
+
+/* Register: IMXDPUV1_framegen0_FgSRCR5 */
+#define IMXDPUV1_FRAMEGEN0_FGSRCR5                           ((uint32_t)(0xB848))
+#define IMXDPUV1_FRAMEGEN0_FGSRCR5_OFFSET                    ((uint32_t)(0x48))
+#define IMXDPUV1_FRAMEGEN0_FGSRCR5_RESET_VALUE               0U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR5_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSRCR5_SYNCRANGELOW_MASK         0x1FFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSRCR5_SYNCRANGELOW_SHIFT        0U
+
+/* Register: IMXDPUV1_framegen0_FgSRCR6 */
+#define IMXDPUV1_FRAMEGEN0_FGSRCR6                           ((uint32_t)(0xB84C))
+#define IMXDPUV1_FRAMEGEN0_FGSRCR6_OFFSET                    ((uint32_t)(0x4C))
+#define IMXDPUV1_FRAMEGEN0_FGSRCR6_RESET_VALUE               0x190U
+#define IMXDPUV1_FRAMEGEN0_FGSRCR6_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSRCR6_SYNCRANGEHIGH_MASK        0x1FFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSRCR6_SYNCRANGEHIGH_SHIFT       0U
+
+/* Register: IMXDPUV1_framegen0_FgKSDR */
+#define IMXDPUV1_FRAMEGEN0_FGKSDR                            ((uint32_t)(0xB850))
+#define IMXDPUV1_FRAMEGEN0_FGKSDR_OFFSET                     ((uint32_t)(0x50))
+#define IMXDPUV1_FRAMEGEN0_FGKSDR_RESET_VALUE                0x20002U
+#define IMXDPUV1_FRAMEGEN0_FGKSDR_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGKSDR_PCNTCPLMAX_MASK            0x7U
+#define IMXDPUV1_FRAMEGEN0_FGKSDR_PCNTCPLMAX_SHIFT           0U
+#define IMXDPUV1_FRAMEGEN0_FGKSDR_SCNTCPLMAX_MASK            0x70000U
+#define IMXDPUV1_FRAMEGEN0_FGKSDR_SCNTCPLMAX_SHIFT           16U
+
+/* Register: IMXDPUV1_framegen0_PaCfg */
+#define IMXDPUV1_FRAMEGEN0_PACFG                             ((uint32_t)(0xB854))
+#define IMXDPUV1_FRAMEGEN0_PACFG_OFFSET                      ((uint32_t)(0x54))
+#define IMXDPUV1_FRAMEGEN0_PACFG_RESET_VALUE                 0x10001U
+#define IMXDPUV1_FRAMEGEN0_PACFG_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_PACFG_PSTARTX_MASK                0x3FFFU
+#define IMXDPUV1_FRAMEGEN0_PACFG_PSTARTX_SHIFT               0U
+#define IMXDPUV1_FRAMEGEN0_PACFG_PSTARTY_MASK                0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN0_PACFG_PSTARTY_SHIFT               16U
+
+/* Register: IMXDPUV1_framegen0_SaCfg */
+#define IMXDPUV1_FRAMEGEN0_SACFG                             ((uint32_t)(0xB858))
+#define IMXDPUV1_FRAMEGEN0_SACFG_OFFSET                      ((uint32_t)(0x58))
+#define IMXDPUV1_FRAMEGEN0_SACFG_RESET_VALUE                 0x10001U
+#define IMXDPUV1_FRAMEGEN0_SACFG_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_SACFG_SSTARTX_MASK                0x3FFFU
+#define IMXDPUV1_FRAMEGEN0_SACFG_SSTARTX_SHIFT               0U
+#define IMXDPUV1_FRAMEGEN0_SACFG_SSTARTY_MASK                0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN0_SACFG_SSTARTY_SHIFT               16U
+
+/* Register: IMXDPUV1_framegen0_FgInCtrl */
+#define IMXDPUV1_FRAMEGEN0_FGINCTRL                          ((uint32_t)(0xB85C))
+#define IMXDPUV1_FRAMEGEN0_FGINCTRL_OFFSET                   ((uint32_t)(0x5C))
+#define IMXDPUV1_FRAMEGEN0_FGINCTRL_RESET_VALUE              0x6U
+#define IMXDPUV1_FRAMEGEN0_FGINCTRL_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM_MASK                0x7U
+#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM_SHIFT               0U
+/* Field Value: FGDM__BLACK, Black Color Background is shown.  */
+#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__BLACK              0U
+/* Field Value: FGDM__CONSTCOL, Constant Color Background is shown.  */
+#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__CONSTCOL           0x1U
+/* Field Value: FGDM__PRIM, Primary input only is shown.  */
+#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__PRIM               0x2U
+/* Field Value: FGDM__SEC, Secondary input only is shown.  */
+#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__SEC                0x3U
+/* Field Value: FGDM__PRIM_ON_TOP, Both inputs overlaid with primary on top.  */
+#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__PRIM_ON_TOP        0x4U
+/* Field Value: FGDM__SEC_ON_TOP, Both inputs overlaid with secondary on top.  */
+#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__SEC_ON_TOP         0x5U
+/* Field Value: FGDM__TEST, White color background with test pattern is shown.  */
+#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__TEST               0x6U
+#define IMXDPUV1_FRAMEGEN0_FGINCTRL_ENPRIMALPHA_MASK         0x8U
+#define IMXDPUV1_FRAMEGEN0_FGINCTRL_ENPRIMALPHA_SHIFT        3U
+#define IMXDPUV1_FRAMEGEN0_FGINCTRL_ENSECALPHA_MASK          0x10U
+#define IMXDPUV1_FRAMEGEN0_FGINCTRL_ENSECALPHA_SHIFT         4U
+
+/* Register: IMXDPUV1_framegen0_FgInCtrlPanic */
+#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC                     ((uint32_t)(0xB860))
+#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_OFFSET              ((uint32_t)(0x60))
+#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_RESET_VALUE         0U
+#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC_MASK      0x7U
+#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC_SHIFT     0U
+/* Field Value: FGDMPANIC__BLACK, Black Color Background is shown.  */
+#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__BLACK    0U
+/* Field Value: FGDMPANIC__CONSTCOL, Constant Color Background is shown.  */
+#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__CONSTCOL 0x1U
+/* Field Value: FGDMPANIC__PRIM, Primary input only is shown.  */
+#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__PRIM     0x2U
+/* Field Value: FGDMPANIC__SEC, Secondary input only is shown.  */
+#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__SEC      0x3U
+/* Field Value: FGDMPANIC__PRIM_ON_TOP, Both inputs overlaid with primary
+ * on top.  */
+#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__PRIM_ON_TOP 0x4U
+/* Field Value: FGDMPANIC__SEC_ON_TOP, Both inputs overlaid with secondary
+ * on top.  */
+#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__SEC_ON_TOP 0x5U
+/* Field Value: FGDMPANIC__TEST, White color background with test pattern
+ * is shown.  */
+#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__TEST     0x6U
+#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENPRIMALPHAPANIC_MASK 0x8U
+#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENPRIMALPHAPANIC_SHIFT 3U
+#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENSECALPHAPANIC_MASK 0x10U
+#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENSECALPHAPANIC_SHIFT 4U
+
+/* Register: IMXDPUV1_framegen0_FgCCR */
+#define IMXDPUV1_FRAMEGEN0_FGCCR                             ((uint32_t)(0xB864))
+#define IMXDPUV1_FRAMEGEN0_FGCCR_OFFSET                      ((uint32_t)(0x64))
+#define IMXDPUV1_FRAMEGEN0_FGCCR_RESET_VALUE                 0x7FFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGCCR_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGCCR_CCBLUE_MASK                 0x3FFU
+#define IMXDPUV1_FRAMEGEN0_FGCCR_CCBLUE_SHIFT                0U
+#define IMXDPUV1_FRAMEGEN0_FGCCR_CCGREEN_MASK                0xFFC00U
+#define IMXDPUV1_FRAMEGEN0_FGCCR_CCGREEN_SHIFT               10U
+#define IMXDPUV1_FRAMEGEN0_FGCCR_CCRED_MASK                  0x3FF00000U
+#define IMXDPUV1_FRAMEGEN0_FGCCR_CCRED_SHIFT                 20U
+#define IMXDPUV1_FRAMEGEN0_FGCCR_CCALPHA_MASK                0x40000000U
+#define IMXDPUV1_FRAMEGEN0_FGCCR_CCALPHA_SHIFT               30U
+
+/* Register: IMXDPUV1_framegen0_FgEnable */
+#define IMXDPUV1_FRAMEGEN0_FGENABLE                          ((uint32_t)(0xB868))
+#define IMXDPUV1_FRAMEGEN0_FGENABLE_OFFSET                   ((uint32_t)(0x68))
+#define IMXDPUV1_FRAMEGEN0_FGENABLE_RESET_VALUE              0U
+#define IMXDPUV1_FRAMEGEN0_FGENABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGENABLE_FGEN_MASK                0x1U
+#define IMXDPUV1_FRAMEGEN0_FGENABLE_FGEN_SHIFT               0U
+
+/* Register: IMXDPUV1_framegen0_FgSlr */
+#define IMXDPUV1_FRAMEGEN0_FGSLR                             ((uint32_t)(0xB86C))
+#define IMXDPUV1_FRAMEGEN0_FGSLR_OFFSET                      ((uint32_t)(0x6C))
+#define IMXDPUV1_FRAMEGEN0_FGSLR_RESET_VALUE                 0U
+#define IMXDPUV1_FRAMEGEN0_FGSLR_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSLR_SHDTOKGEN_MASK              0x1U
+#define IMXDPUV1_FRAMEGEN0_FGSLR_SHDTOKGEN_SHIFT             0U
+
+/* Register: IMXDPUV1_framegen0_FgEnSts */
+#define IMXDPUV1_FRAMEGEN0_FGENSTS                           ((uint32_t)(0xB870))
+#define IMXDPUV1_FRAMEGEN0_FGENSTS_OFFSET                    ((uint32_t)(0x70))
+#define IMXDPUV1_FRAMEGEN0_FGENSTS_RESET_VALUE               0U
+#define IMXDPUV1_FRAMEGEN0_FGENSTS_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGENSTS_ENSTS_MASK                0x1U
+#define IMXDPUV1_FRAMEGEN0_FGENSTS_ENSTS_SHIFT               0U
+#define IMXDPUV1_FRAMEGEN0_FGENSTS_PANICSTAT_MASK            0x2U
+#define IMXDPUV1_FRAMEGEN0_FGENSTS_PANICSTAT_SHIFT           1U
+
+/* Register: IMXDPUV1_framegen0_FgTimeStamp */
+#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP                       ((uint32_t)(0xB874))
+#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_OFFSET                ((uint32_t)(0x74))
+#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_RESET_VALUE           0U
+#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_LINEINDEX_MASK        0x3FFFU
+#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_LINEINDEX_SHIFT       0U
+#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_FRAMEINDEX_MASK       0xFFFFC000U
+#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_FRAMEINDEX_SHIFT      14U
+
+/* Register: IMXDPUV1_framegen0_FgChStat */
+#define IMXDPUV1_FRAMEGEN0_FGCHSTAT                          ((uint32_t)(0xB878))
+#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_OFFSET                   ((uint32_t)(0x78))
+#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_RESET_VALUE              0U
+#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_PFIFOEMPTY_MASK          0x1U
+#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_PFIFOEMPTY_SHIFT         0U
+#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_PRIMSYNCSTAT_MASK        0x100U
+#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_PRIMSYNCSTAT_SHIFT       8U
+#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SFIFOEMPTY_MASK          0x10000U
+#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SFIFOEMPTY_SHIFT         16U
+#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SKEWRANGEERR_MASK        0x20000U
+#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SKEWRANGEERR_SHIFT       17U
+#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SECSYNCSTAT_MASK         0x1000000U
+#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SECSYNCSTAT_SHIFT        24U
+
+/* Register: IMXDPUV1_framegen0_FgChStatClr */
+#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR                       ((uint32_t)(0xB87C))
+#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_OFFSET                ((uint32_t)(0x7C))
+#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_RESET_VALUE           0U
+#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRPRIMSTAT_MASK      0x1U
+#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRPRIMSTAT_SHIFT     0U
+#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRSECSTAT_MASK       0x10000U
+#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRSECSTAT_SHIFT      16U
+
+/* Register: IMXDPUV1_framegen0_FgSkewMon */
+#define IMXDPUV1_FRAMEGEN0_FGSKEWMON                         ((uint32_t)(0xB880))
+#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_OFFSET                  ((uint32_t)(0x80))
+#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_RESET_VALUE             0U
+#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_SKEWMON_MASK            0x1FFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_SKEWMON_SHIFT           0U
+
+/* Register: IMXDPUV1_framegen0_FgSFifoMin */
+#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN                        ((uint32_t)(0xB884))
+#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_OFFSET                 ((uint32_t)(0x84))
+#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_RESET_VALUE            0U
+#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_SFIFOMIN_MASK          0xFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_SFIFOMIN_SHIFT         0U
+
+/* Register: IMXDPUV1_framegen0_FgSFifoMax */
+#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX                        ((uint32_t)(0xB888))
+#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_OFFSET                 ((uint32_t)(0x88))
+#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_RESET_VALUE            0U
+#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_SFIFOMAX_MASK          0xFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_SFIFOMAX_SHIFT         0U
+
+/* Register: IMXDPUV1_framegen0_FgSFifoFillClr */
+#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR                    ((uint32_t)(0xB88C))
+#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_OFFSET             ((uint32_t)(0x8C))
+#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_RESET_VALUE        0U
+#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_SFIFOFILLCLR_MASK  0x1U
+#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_SFIFOFILLCLR_SHIFT 0U
+
+/* Register: IMXDPUV1_framegen0_FgSrEpD */
+#define IMXDPUV1_FRAMEGEN0_FGSREPD                           ((uint32_t)(0xB890))
+#define IMXDPUV1_FRAMEGEN0_FGSREPD_OFFSET                    ((uint32_t)(0x90))
+#define IMXDPUV1_FRAMEGEN0_FGSREPD_RESET_VALUE               0U
+#define IMXDPUV1_FRAMEGEN0_FGSREPD_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSREPD_EPVAL_MASK                0x1FFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSREPD_EPVAL_SHIFT               0U
+
+/* Register: IMXDPUV1_framegen0_FgSrFtD */
+#define IMXDPUV1_FRAMEGEN0_FGSRFTD                           ((uint32_t)(0xB894))
+#define IMXDPUV1_FRAMEGEN0_FGSRFTD_OFFSET                    ((uint32_t)(0x94))
+#define IMXDPUV1_FRAMEGEN0_FGSRFTD_RESET_VALUE               0U
+#define IMXDPUV1_FRAMEGEN0_FGSRFTD_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSRFTD_FRTOT_MASK                0xFFFFFFFU
+#define IMXDPUV1_FRAMEGEN0_FGSRFTD_FRTOT_SHIFT               0U
+
+/* Register: IMXDPUV1_matrix0_LockUnlock */
+#define IMXDPUV1_MATRIX0_LOCKUNLOCK                          ((uint32_t)(0xBC00))
+#define IMXDPUV1_MATRIX0_LOCKUNLOCK_OFFSET                   ((uint32_t)(0))
+#define IMXDPUV1_MATRIX0_LOCKUNLOCK_RESET_VALUE              0U
+#define IMXDPUV1_MATRIX0_LOCKUNLOCK_RESET_MASK               0U
+#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK_MASK          0xFFFFFFFFU
+#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK_SHIFT         0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY     0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY   0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY   0xFBE8B1E6U
+
+/* Register: IMXDPUV1_matrix0_LockStatus */
+#define IMXDPUV1_MATRIX0_LOCKSTATUS                          ((uint32_t)(0xBC04))
+#define IMXDPUV1_MATRIX0_LOCKSTATUS_OFFSET                   ((uint32_t)(0x4))
+#define IMXDPUV1_MATRIX0_LOCKSTATUS_RESET_VALUE              0U
+#define IMXDPUV1_MATRIX0_LOCKSTATUS_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_MATRIX0_LOCKSTATUS_LOCKSTATUS_MASK          0x1U
+#define IMXDPUV1_MATRIX0_LOCKSTATUS_LOCKSTATUS_SHIFT         0U
+#define IMXDPUV1_MATRIX0_LOCKSTATUS_PRIVILEGESTATUS_MASK     0x10U
+#define IMXDPUV1_MATRIX0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT    4U
+#define IMXDPUV1_MATRIX0_LOCKSTATUS_FREEZESTATUS_MASK        0x100U
+#define IMXDPUV1_MATRIX0_LOCKSTATUS_FREEZESTATUS_SHIFT       8U
+
+/* Register: IMXDPUV1_matrix0_StaticControl */
+#define IMXDPUV1_MATRIX0_STATICCONTROL                       ((uint32_t)(0xBC08))
+#define IMXDPUV1_MATRIX0_STATICCONTROL_OFFSET                ((uint32_t)(0x8))
+#define IMXDPUV1_MATRIX0_STATICCONTROL_RESET_VALUE           0U
+#define IMXDPUV1_MATRIX0_STATICCONTROL_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_MATRIX0_STATICCONTROL_SHDEN_MASK            0x1U
+#define IMXDPUV1_MATRIX0_STATICCONTROL_SHDEN_SHIFT           0U
+
+/* Register: IMXDPUV1_matrix0_Control */
+#define IMXDPUV1_MATRIX0_CONTROL                             ((uint32_t)(0xBC0C))
+#define IMXDPUV1_MATRIX0_CONTROL_OFFSET                      ((uint32_t)(0xC))
+#define IMXDPUV1_MATRIX0_CONTROL_RESET_VALUE                 0U
+#define IMXDPUV1_MATRIX0_CONTROL_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_MATRIX0_CONTROL_MODE_MASK                   0x3U
+#define IMXDPUV1_MATRIX0_CONTROL_MODE_SHIFT                  0U
+/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed  */
+#define IMXDPUV1_MATRIX0_CONTROL_MODE__NEUTRAL               0U
+/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied
+ * with matrix values  */
+#define IMXDPUV1_MATRIX0_CONTROL_MODE__MATRIX                0x1U
+/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input
+ * color is multiplied with input alpha  */
+#define IMXDPUV1_MATRIX0_CONTROL_MODE__PREMUL                0x2U
+/* Field Value: MODE__RSVD, Reserved, do not use  */
+#define IMXDPUV1_MATRIX0_CONTROL_MODE__RSVD                  0x3U
+#define IMXDPUV1_MATRIX0_CONTROL_ALPHAMASK_MASK              0x10U
+#define IMXDPUV1_MATRIX0_CONTROL_ALPHAMASK_SHIFT             4U
+#define IMXDPUV1_MATRIX0_CONTROL_ALPHAINVERT_MASK            0x20U
+#define IMXDPUV1_MATRIX0_CONTROL_ALPHAINVERT_SHIFT           5U
+
+/* Register: IMXDPUV1_matrix0_Red0 */
+#define IMXDPUV1_MATRIX0_RED0                                ((uint32_t)(0xBC10))
+#define IMXDPUV1_MATRIX0_RED0_OFFSET                         ((uint32_t)(0x10))
+#define IMXDPUV1_MATRIX0_RED0_RESET_VALUE                    0x400U
+#define IMXDPUV1_MATRIX0_RED0_RESET_MASK                     0xFFFFFFFFU
+#define IMXDPUV1_MATRIX0_RED0_A11_MASK                       0x1FFFU
+#define IMXDPUV1_MATRIX0_RED0_A11_SHIFT                      0U
+#define IMXDPUV1_MATRIX0_RED0_A12_MASK                       0x1FFF0000U
+#define IMXDPUV1_MATRIX0_RED0_A12_SHIFT                      16U
+
+/* Register: IMXDPUV1_matrix0_Red1 */
+#define IMXDPUV1_MATRIX0_RED1                                ((uint32_t)(0xBC14))
+#define IMXDPUV1_MATRIX0_RED1_OFFSET                         ((uint32_t)(0x14))
+#define IMXDPUV1_MATRIX0_RED1_RESET_VALUE                    0U
+#define IMXDPUV1_MATRIX0_RED1_RESET_MASK                     0xFFFFFFFFU
+#define IMXDPUV1_MATRIX0_RED1_A13_MASK                       0x1FFFU
+#define IMXDPUV1_MATRIX0_RED1_A13_SHIFT                      0U
+#define IMXDPUV1_MATRIX0_RED1_A14_MASK                       0x1FFF0000U
+#define IMXDPUV1_MATRIX0_RED1_A14_SHIFT                      16U
+
+/* Register: IMXDPUV1_matrix0_Green0 */
+#define IMXDPUV1_MATRIX0_GREEN0                              ((uint32_t)(0xBC18))
+#define IMXDPUV1_MATRIX0_GREEN0_OFFSET                       ((uint32_t)(0x18))
+#define IMXDPUV1_MATRIX0_GREEN0_RESET_VALUE                  0x4000000U
+#define IMXDPUV1_MATRIX0_GREEN0_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX0_GREEN0_A21_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX0_GREEN0_A21_SHIFT                    0U
+#define IMXDPUV1_MATRIX0_GREEN0_A22_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX0_GREEN0_A22_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix0_Green1 */
+#define IMXDPUV1_MATRIX0_GREEN1                              ((uint32_t)(0xBC1C))
+#define IMXDPUV1_MATRIX0_GREEN1_OFFSET                       ((uint32_t)(0x1C))
+#define IMXDPUV1_MATRIX0_GREEN1_RESET_VALUE                  0U
+#define IMXDPUV1_MATRIX0_GREEN1_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX0_GREEN1_A23_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX0_GREEN1_A23_SHIFT                    0U
+#define IMXDPUV1_MATRIX0_GREEN1_A24_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX0_GREEN1_A24_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix0_Blue0 */
+#define IMXDPUV1_MATRIX0_BLUE0                               ((uint32_t)(0xBC20))
+#define IMXDPUV1_MATRIX0_BLUE0_OFFSET                        ((uint32_t)(0x20))
+#define IMXDPUV1_MATRIX0_BLUE0_RESET_VALUE                   0U
+#define IMXDPUV1_MATRIX0_BLUE0_RESET_MASK                    0xFFFFFFFFU
+#define IMXDPUV1_MATRIX0_BLUE0_A31_MASK                      0x1FFFU
+#define IMXDPUV1_MATRIX0_BLUE0_A31_SHIFT                     0U
+#define IMXDPUV1_MATRIX0_BLUE0_A32_MASK                      0x1FFF0000U
+#define IMXDPUV1_MATRIX0_BLUE0_A32_SHIFT                     16U
+
+/* Register: IMXDPUV1_matrix0_Blue1 */
+#define IMXDPUV1_MATRIX0_BLUE1                               ((uint32_t)(0xBC24))
+#define IMXDPUV1_MATRIX0_BLUE1_OFFSET                        ((uint32_t)(0x24))
+#define IMXDPUV1_MATRIX0_BLUE1_RESET_VALUE                   0x400U
+#define IMXDPUV1_MATRIX0_BLUE1_RESET_MASK                    0xFFFFFFFFU
+#define IMXDPUV1_MATRIX0_BLUE1_A33_MASK                      0x1FFFU
+#define IMXDPUV1_MATRIX0_BLUE1_A33_SHIFT                     0U
+#define IMXDPUV1_MATRIX0_BLUE1_A34_MASK                      0x1FFF0000U
+#define IMXDPUV1_MATRIX0_BLUE1_A34_SHIFT                     16U
+
+/* Register: IMXDPUV1_matrix0_Alpha0 */
+#define IMXDPUV1_MATRIX0_ALPHA0                              ((uint32_t)(0xBC28))
+#define IMXDPUV1_MATRIX0_ALPHA0_OFFSET                       ((uint32_t)(0x28))
+#define IMXDPUV1_MATRIX0_ALPHA0_RESET_VALUE                  0U
+#define IMXDPUV1_MATRIX0_ALPHA0_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX0_ALPHA0_A41_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX0_ALPHA0_A41_SHIFT                    0U
+#define IMXDPUV1_MATRIX0_ALPHA0_A42_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX0_ALPHA0_A42_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix0_Alpha1 */
+#define IMXDPUV1_MATRIX0_ALPHA1                              ((uint32_t)(0xBC2C))
+#define IMXDPUV1_MATRIX0_ALPHA1_OFFSET                       ((uint32_t)(0x2C))
+#define IMXDPUV1_MATRIX0_ALPHA1_RESET_VALUE                  0x4000000U
+#define IMXDPUV1_MATRIX0_ALPHA1_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX0_ALPHA1_A43_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX0_ALPHA1_A43_SHIFT                    0U
+#define IMXDPUV1_MATRIX0_ALPHA1_A44_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX0_ALPHA1_A44_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix0_OffsetVector0 */
+#define IMXDPUV1_MATRIX0_OFFSETVECTOR0                       ((uint32_t)(0xBC30))
+#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_OFFSET                ((uint32_t)(0x30))
+#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_RESET_VALUE           0U
+#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_C1_MASK               0x1FFFU
+#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_C1_SHIFT              0U
+#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_C2_MASK               0x1FFF0000U
+#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_C2_SHIFT              16U
+
+/* Register: IMXDPUV1_matrix0_OffsetVector1 */
+#define IMXDPUV1_MATRIX0_OFFSETVECTOR1                       ((uint32_t)(0xBC34))
+#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_OFFSET                ((uint32_t)(0x34))
+#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_RESET_VALUE           0U
+#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_C3_MASK               0x1FFFU
+#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_C3_SHIFT              0U
+#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_C4_MASK               0x1FFF0000U
+#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_C4_SHIFT              16U
+
+/* Register: IMXDPUV1_matrix0_LastControlWord */
+#define IMXDPUV1_MATRIX0_LASTCONTROLWORD                     ((uint32_t)(0xBC38))
+#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_OFFSET              ((uint32_t)(0x38))
+#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_RESET_VALUE         0U
+#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_RESET_MASK          0U
+#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_L_VAL_MASK          0xFFFFFFFFU
+#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_L_VAL_SHIFT         0U
+
+/* Register: IMXDPUV1_gammacor0_LockUnlock */
+#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK                        ((uint32_t)(0xC000))
+#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_OFFSET                 ((uint32_t)(0))
+#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_RESET_VALUE            0U
+#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_RESET_MASK             0U
+#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK_MASK        0xFFFFFFFFU
+#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK_SHIFT       0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY   0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_gammacor0_LockStatus */
+#define IMXDPUV1_GAMMACOR0_LOCKSTATUS                        ((uint32_t)(0xC004))
+#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_OFFSET                 ((uint32_t)(0x4))
+#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_RESET_VALUE            0U
+#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_LOCKSTATUS_MASK        0x1U
+#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_LOCKSTATUS_SHIFT       0U
+#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_PRIVILEGESTATUS_MASK   0x10U
+#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT  4U
+#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_FREEZESTATUS_MASK      0x100U
+#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_FREEZESTATUS_SHIFT     8U
+
+/* Register: IMXDPUV1_gammacor0_StaticControl */
+#define IMXDPUV1_GAMMACOR0_STATICCONTROL                     ((uint32_t)(0xC008))
+#define IMXDPUV1_GAMMACOR0_STATICCONTROL_OFFSET              ((uint32_t)(0x8))
+#define IMXDPUV1_GAMMACOR0_STATICCONTROL_RESET_VALUE         0xEU
+#define IMXDPUV1_GAMMACOR0_STATICCONTROL_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_GAMMACOR0_STATICCONTROL_SHDEN_MASK          0x1U
+#define IMXDPUV1_GAMMACOR0_STATICCONTROL_SHDEN_SHIFT         0U
+#define IMXDPUV1_GAMMACOR0_STATICCONTROL_BLUEWRITEENABLE_MASK 0x2U
+#define IMXDPUV1_GAMMACOR0_STATICCONTROL_BLUEWRITEENABLE_SHIFT 1U
+#define IMXDPUV1_GAMMACOR0_STATICCONTROL_GREENWRITEENABLE_MASK 0x4U
+#define IMXDPUV1_GAMMACOR0_STATICCONTROL_GREENWRITEENABLE_SHIFT 2U
+#define IMXDPUV1_GAMMACOR0_STATICCONTROL_REDWRITEENABLE_MASK 0x8U
+#define IMXDPUV1_GAMMACOR0_STATICCONTROL_REDWRITEENABLE_SHIFT 3U
+
+/* Register: IMXDPUV1_gammacor0_LutStart */
+#define IMXDPUV1_GAMMACOR0_LUTSTART                          ((uint32_t)(0xC00C))
+#define IMXDPUV1_GAMMACOR0_LUTSTART_OFFSET                   ((uint32_t)(0xC))
+#define IMXDPUV1_GAMMACOR0_LUTSTART_RESET_VALUE              0U
+#define IMXDPUV1_GAMMACOR0_LUTSTART_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTBLUE_MASK           0x3FFU
+#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTBLUE_SHIFT          0U
+#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTGREEN_MASK          0xFFC00U
+#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTGREEN_SHIFT         10U
+#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTRED_MASK            0x3FF00000U
+#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTRED_SHIFT           20U
+
+/* Register: IMXDPUV1_gammacor0_LutDeltas */
+#define IMXDPUV1_GAMMACOR0_LUTDELTAS                         ((uint32_t)(0xC010))
+#define IMXDPUV1_GAMMACOR0_LUTDELTAS_OFFSET                  ((uint32_t)(0x10))
+#define IMXDPUV1_GAMMACOR0_LUTDELTAS_RESET_VALUE             0U
+#define IMXDPUV1_GAMMACOR0_LUTDELTAS_RESET_MASK              0xC0000000U
+#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTABLUE_MASK          0x3FFU
+#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTABLUE_SHIFT         0U
+#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTAGREEN_MASK         0xFFC00U
+#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTAGREEN_SHIFT        10U
+#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTARED_MASK           0x3FF00000U
+#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTARED_SHIFT          20U
+
+/* Register: IMXDPUV1_gammacor0_Control */
+#define IMXDPUV1_GAMMACOR0_CONTROL                           ((uint32_t)(0xC014))
+#define IMXDPUV1_GAMMACOR0_CONTROL_OFFSET                    ((uint32_t)(0x14))
+#define IMXDPUV1_GAMMACOR0_CONTROL_RESET_VALUE               0U
+#define IMXDPUV1_GAMMACOR0_CONTROL_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_GAMMACOR0_CONTROL_MODE_MASK                 0x1U
+#define IMXDPUV1_GAMMACOR0_CONTROL_MODE_SHIFT                0U
+/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed
+ * to the output.  */
+#define IMXDPUV1_GAMMACOR0_CONTROL_MODE__NEUTRAL             0U
+/* Field Value: MODE__GAMMACOR, Module in gamma correction mode.  */
+#define IMXDPUV1_GAMMACOR0_CONTROL_MODE__GAMMACOR            0x1U
+#define IMXDPUV1_GAMMACOR0_CONTROL_ALPHAMASK_MASK            0x10U
+#define IMXDPUV1_GAMMACOR0_CONTROL_ALPHAMASK_SHIFT           4U
+#define IMXDPUV1_GAMMACOR0_CONTROL_ALPHAINVERT_MASK          0x20U
+#define IMXDPUV1_GAMMACOR0_CONTROL_ALPHAINVERT_SHIFT         5U
+
+/* Register: IMXDPUV1_gammacor0_Status */
+#define IMXDPUV1_GAMMACOR0_STATUS                            ((uint32_t)(0xC018))
+#define IMXDPUV1_GAMMACOR0_STATUS_OFFSET                     ((uint32_t)(0x18))
+#define IMXDPUV1_GAMMACOR0_STATUS_RESET_VALUE                0U
+#define IMXDPUV1_GAMMACOR0_STATUS_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_GAMMACOR0_STATUS_WRITETIMEOUT_MASK          0x1U
+#define IMXDPUV1_GAMMACOR0_STATUS_WRITETIMEOUT_SHIFT         0U
+
+/* Register: IMXDPUV1_gammacor0_LastControlWord */
+#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD                   ((uint32_t)(0xC01C))
+#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_OFFSET            ((uint32_t)(0x1C))
+#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_RESET_VALUE       0U
+#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_RESET_MASK        0U
+#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_L_VAL_MASK        0xFFFFFFFFU
+#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_L_VAL_SHIFT       0U
+
+/* Register: IMXDPUV1_dither0_LockUnlock */
+#define IMXDPUV1_DITHER0_LOCKUNLOCK                          ((uint32_t)(0xC400))
+#define IMXDPUV1_DITHER0_LOCKUNLOCK_OFFSET                   ((uint32_t)(0))
+#define IMXDPUV1_DITHER0_LOCKUNLOCK_RESET_VALUE              0U
+#define IMXDPUV1_DITHER0_LOCKUNLOCK_RESET_MASK               0U
+#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK_MASK          0xFFFFFFFFU
+#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK_SHIFT         0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY     0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY   0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY   0xFBE8B1E6U
+
+/* Register: IMXDPUV1_dither0_LockStatus */
+#define IMXDPUV1_DITHER0_LOCKSTATUS                          ((uint32_t)(0xC404))
+#define IMXDPUV1_DITHER0_LOCKSTATUS_OFFSET                   ((uint32_t)(0x4))
+#define IMXDPUV1_DITHER0_LOCKSTATUS_RESET_VALUE              0U
+#define IMXDPUV1_DITHER0_LOCKSTATUS_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_DITHER0_LOCKSTATUS_LOCKSTATUS_MASK          0x1U
+#define IMXDPUV1_DITHER0_LOCKSTATUS_LOCKSTATUS_SHIFT         0U
+#define IMXDPUV1_DITHER0_LOCKSTATUS_PRIVILEGESTATUS_MASK     0x10U
+#define IMXDPUV1_DITHER0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT    4U
+#define IMXDPUV1_DITHER0_LOCKSTATUS_FREEZESTATUS_MASK        0x100U
+#define IMXDPUV1_DITHER0_LOCKSTATUS_FREEZESTATUS_SHIFT       8U
+
+/* Register: IMXDPUV1_dither0_Control */
+#define IMXDPUV1_DITHER0_CONTROL                             ((uint32_t)(0xC408))
+#define IMXDPUV1_DITHER0_CONTROL_OFFSET                      ((uint32_t)(0x8))
+#define IMXDPUV1_DITHER0_CONTROL_RESET_VALUE                 0U
+#define IMXDPUV1_DITHER0_CONTROL_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_DITHER0_CONTROL_MODE_MASK                   0x1U
+#define IMXDPUV1_DITHER0_CONTROL_MODE_SHIFT                  0U
+/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the Dither Unit,
+ * all other settings are ignored.  */
+#define IMXDPUV1_DITHER0_CONTROL_MODE__NEUTRAL               0U
+/* Field Value: MODE__ACTIVE, Dither Unit is active.  */
+#define IMXDPUV1_DITHER0_CONTROL_MODE__ACTIVE                0x1U
+
+/* Register: IMXDPUV1_dither0_DitherControl */
+#define IMXDPUV1_DITHER0_DITHERCONTROL                       ((uint32_t)(0xC40C))
+#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET                ((uint32_t)(0xC))
+#define IMXDPUV1_DITHER0_DITHERCONTROL_RESET_VALUE           0x300222U
+#define IMXDPUV1_DITHER0_DITHERCONTROL_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT_MASK 0x7U
+#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT_SHIFT 0U
+/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO8, Reduces blue component width
+ * from 10 bit to 8bit.  */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO8 0x2U
+/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO7, Reduces blue component width
+ * from 10 bit to 7bit.  */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO7 0x3U
+/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO6, Reduces blue component width
+ * from 10 bit to 6bit.  */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO6 0x4U
+/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO5, Reduces blue component width
+ * from 10 bit to 5bit.  */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO5 0x5U
+#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT_MASK 0x70U
+#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT_SHIFT 4U
+/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO8, Reduces green component width
+ * from 10 bit to 8bit.  */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO8 0x2U
+/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO7, Reduces green component width
+ * from 10 bit to 7bit.  */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO7 0x3U
+/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO6, Reduces green component width
+ * from 10 bit to 6bit.  */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO6 0x4U
+/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO5, Reduces green component width
+ * from 10 bit to 5bit.  */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO5 0x5U
+#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT_MASK 0x700U
+#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT_SHIFT 8U
+/* Field Value: RED_RANGE_SELECT__RED_10TO8, Reduces red component width from
+ * 10 bit to 8bit.  */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO8 0x2U
+/* Field Value: RED_RANGE_SELECT__RED_10TO7, Reduces red component width from
+ * 10 bit to 7bit.  */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO7 0x3U
+/* Field Value: RED_RANGE_SELECT__RED_10TO6, Reduces red component width from
+ * 10 bit to 6bit.  */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO6 0x4U
+/* Field Value: RED_RANGE_SELECT__RED_10TO5, Reduces red component width from
+ * 10 bit to 5bit.  */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO5 0x5U
+#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET_SELECT_MASK    0x10000U
+#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET_SELECT_SHIFT   16U
+/* Field Value: OFFSET_SELECT__OFFS_SPATIAL, Offset is a bayer matrix value,
+ * which is selected according to pixel frame position.  */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET_SELECT__OFFS_SPATIAL 0U
+/* Field Value: OFFSET_SELECT__OFFS_TEMPORAL, Offset is the sum from a bayer
+ * matrix value, which is selected according to pixel frame position,
+ * and a value from a regular sequence, which changes each frame.   */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET_SELECT__OFFS_TEMPORAL 0x1U
+#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT_MASK      0x300000U
+#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT_SHIFT     20U
+/* Field Value: ALGO_SELECT__NO_CORRECTION, Best possible resolution for most
+ * dark colors. Adds a diminutive offset to overall image brightness.  */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT__NO_CORRECTION 0x1U
+/* Field Value: ALGO_SELECT__BRIGHTNESS_CORRECTION, Preserves overall image
+ * brightness. Cannot resolve most dark and most bright colors. All codes
+ * in-between are distributed perfectly smooth.  */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT__BRIGHTNESS_CORRECTION 0x2U
+/* Field Value: ALGO_SELECT__CONTRAST_CORRECTION, Preserves overall image
+ * brightness. Best possible distribution of color codes over complete range.  */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT__CONTRAST_CORRECTION 0x3U
+#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE_MASK       0x3000000U
+#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE_SHIFT      24U
+/* Field Value: ALPHA_MODE__DISABLE, The alpha bit is not considered.  */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE__DISABLE   0U
+/* Field Value: ALPHA_MODE__ENABLE_BY1, Red, green and blue components are
+ * only dithered, if the alpha bit is 1.  */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE__ENABLE_BY1 0x1U
+/* Field Value: ALPHA_MODE__ENABLE_BY0, Red, green and blue components are
+ * only dithered, if the alpha bit is 0.  */
+#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE__ENABLE_BY0 0x2U
+
+/* Register: IMXDPUV1_dither0_Release */
+#define IMXDPUV1_DITHER0_RELEASE                             ((uint32_t)(0xC410))
+#define IMXDPUV1_DITHER0_RELEASE_OFFSET                      ((uint32_t)(0x10))
+#define IMXDPUV1_DITHER0_RELEASE_RESET_VALUE                 0U
+#define IMXDPUV1_DITHER0_RELEASE_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_DITHER0_RELEASE_SUBVERSION_MASK             0xFFU
+#define IMXDPUV1_DITHER0_RELEASE_SUBVERSION_SHIFT            0U
+#define IMXDPUV1_DITHER0_RELEASE_VERSION_MASK                0xFF00U
+#define IMXDPUV1_DITHER0_RELEASE_VERSION_SHIFT               8U
+
+/* Register: IMXDPUV1_tcon0_SSqCnts */
+#define IMXDPUV1_TCON0_SSQCNTS                               ((uint32_t)(0xC800))
+#define IMXDPUV1_TCON0_SSQCNTS_OFFSET                        ((uint32_t)(0))
+#define IMXDPUV1_TCON0_SSQCNTS_RESET_VALUE                   0U
+#define IMXDPUV1_TCON0_SSQCNTS_RESET_MASK                    0U
+#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_SEQY_MASK             0x7FFFU
+#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_SEQY_SHIFT            0U
+#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_FIELD_MASK            0x8000U
+#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_FIELD_SHIFT           15U
+#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_SEQX_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_SEQX_SHIFT            16U
+#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_OUT_MASK              0x80000000U
+#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_OUT_SHIFT             31U
+
+/* Register: IMXDPUV1_tcon0_LockUnlock */
+#define IMXDPUV1_TCON0_LOCKUNLOCK                            ((uint32_t)(0xCC00))
+#define IMXDPUV1_TCON0_LOCKUNLOCK_OFFSET                     ((uint32_t)(0))
+#define IMXDPUV1_TCON0_LOCKUNLOCK_RESET_VALUE                0U
+#define IMXDPUV1_TCON0_LOCKUNLOCK_RESET_MASK                 0U
+#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK_MASK            0xFFFFFFFFU
+#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK_SHIFT           0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY       0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY     0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY  0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY     0xFBE8B1E6U
+
+/* Register: IMXDPUV1_tcon0_LockStatus */
+#define IMXDPUV1_TCON0_LOCKSTATUS                            ((uint32_t)(0xCC04))
+#define IMXDPUV1_TCON0_LOCKSTATUS_OFFSET                     ((uint32_t)(0x4))
+#define IMXDPUV1_TCON0_LOCKSTATUS_RESET_VALUE                0U
+#define IMXDPUV1_TCON0_LOCKSTATUS_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_LOCKSTATUS_LOCKSTATUS_MASK            0x1U
+#define IMXDPUV1_TCON0_LOCKSTATUS_LOCKSTATUS_SHIFT           0U
+#define IMXDPUV1_TCON0_LOCKSTATUS_PRIVILEGESTATUS_MASK       0x10U
+#define IMXDPUV1_TCON0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT      4U
+#define IMXDPUV1_TCON0_LOCKSTATUS_FREEZESTATUS_MASK          0x100U
+#define IMXDPUV1_TCON0_LOCKSTATUS_FREEZESTATUS_SHIFT         8U
+
+/* Register: IMXDPUV1_tcon0_SSqCycle */
+#define IMXDPUV1_TCON0_SSQCYCLE                              ((uint32_t)(0xCC08))
+#define IMXDPUV1_TCON0_SSQCYCLE_OFFSET                       ((uint32_t)(0x8))
+#define IMXDPUV1_TCON0_SSQCYCLE_RESET_VALUE                  0U
+#define IMXDPUV1_TCON0_SSQCYCLE_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SSQCYCLE_SSQCYCLE_MASK                0x3FU
+#define IMXDPUV1_TCON0_SSQCYCLE_SSQCYCLE_SHIFT               0U
+
+/* Register: IMXDPUV1_tcon0_SWreset */
+#define IMXDPUV1_TCON0_SWRESET                               ((uint32_t)(0xCC0C))
+#define IMXDPUV1_TCON0_SWRESET_OFFSET                        ((uint32_t)(0xC))
+#define IMXDPUV1_TCON0_SWRESET_RESET_VALUE                   0x3FC00410U
+#define IMXDPUV1_TCON0_SWRESET_RESET_MASK                    0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SWRESET_SWRESET_MASK                  0x1U
+#define IMXDPUV1_TCON0_SWRESET_SWRESET_SHIFT                 0U
+/* Field Value: SWRESET__OPERATION, operation mode  */
+#define IMXDPUV1_TCON0_SWRESET_SWRESET__OPERATION            0U
+/* Field Value: SWRESET__SWRESET, So long SWReset = 0x1 tcon is in 'SW reset
+ * state' and it is released by internal logic (SWReset is released and
+ * end of frame arrived), read: 0b: reset not active 1b: reset active (that
+ * means NO pixel of video frame is excepted until 'SW reset state'
+ * is released)  */
+#define IMXDPUV1_TCON0_SWRESET_SWRESET__SWRESET              0x1U
+#define IMXDPUV1_TCON0_SWRESET_ENRESETWORD_MASK              0xFFF0U
+#define IMXDPUV1_TCON0_SWRESET_ENRESETWORD_SHIFT             4U
+#define IMXDPUV1_TCON0_SWRESET_RESETWORDEND_MASK             0xFF0000U
+#define IMXDPUV1_TCON0_SWRESET_RESETWORDEND_SHIFT            16U
+#define IMXDPUV1_TCON0_SWRESET_RESETWORDSTART_MASK           0xFF000000U
+#define IMXDPUV1_TCON0_SWRESET_RESETWORDSTART_SHIFT          24U
+
+/* Register: IMXDPUV1_tcon0_TCON_CTRL */
+#define IMXDPUV1_TCON0_TCON_CTRL                             ((uint32_t)(0xCC10))
+#define IMXDPUV1_TCON0_TCON_CTRL_OFFSET                      ((uint32_t)(0x10))
+#define IMXDPUV1_TCON0_TCON_CTRL_RESET_VALUE                 0x1401408U
+#define IMXDPUV1_TCON0_TCON_CTRL_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE_MASK            0x3U
+#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE_SHIFT           0U
+/* Field Value: CHANNELMODE__SINGLE, Single pixel mode. Both channels channel
+ * are active at full pixel clock. If bitmap of both panels are the same,
+ * both panels are identical  */
+#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE__SINGLE         0U
+/* Field Value: CHANNELMODE__DUAL_INTERLEAVED, Dual pixel mode. Both channels
+ * are active at half the pixel clock. 1st channel drives display columns
+ * with even and 2nd one with odd index.  */
+#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE__DUAL_INTERLEAVED 0x1U
+/* Field Value: CHANNELMODE__DUAL_SPLIT, Dual pixel mode. Both channels are
+ * active at half the pixel clock. 1st channel drives the left and 2nd
+ * one the righ half of the display. Note : data_en is needed in this mode  */
+#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE__DUAL_SPLIT     0x2U
+#define IMXDPUV1_TCON0_TCON_CTRL_TCON_SYNC_MASK              0x4U
+#define IMXDPUV1_TCON0_TCON_CTRL_TCON_SYNC_SHIFT             2U
+/* Field Value: TCON_SYNC__H_VLAST, tcon timing generator synchronized to
+ * hlast, vlast  */
+#define IMXDPUV1_TCON0_TCON_CTRL_TCON_SYNC__H_VLAST          0U
+/* Field Value: TCON_SYNC__H_VSYNC, tcon timing generator synchronized to
+ * hsync, vsync where horizontal synchronization is synchronized at the falling
+ * edge of hsync  */
+#define IMXDPUV1_TCON0_TCON_CTRL_TCON_SYNC__H_VSYNC          0x1U
+#define IMXDPUV1_TCON0_TCON_CTRL_BYPASS_MASK                 0x8U
+#define IMXDPUV1_TCON0_TCON_CTRL_BYPASS_SHIFT                3U
+/* Field Value: BYPASS__TCON_MODE, tcon operation mode  */
+#define IMXDPUV1_TCON0_TCON_CTRL_BYPASS__TCON_MODE           0U
+/* Field Value: BYPASS__BYPASS_MODE, tcon in Bypass mode. input pixel and
+ * its sync-signals are bypassed to tcon-output  */
+#define IMXDPUV1_TCON0_TCON_CTRL_BYPASS__BYPASS_MODE         0x1U
+#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL_MASK               0xF0U
+#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL_SHIFT              4U
+/* Field Value: INV_CTRL__DISABLE, Disable inversion control  */
+#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__DISABLE           0U
+/* Field Value: INV_CTRL__RGB_2_BITS, Enable inversion control for number
+ * of RGB-Bits = 2  */
+#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_2_BITS        0x1U
+/* Field Value: INV_CTRL__RGB_4_BITS, Enable inversion control for number
+ * of RGB-Bits = 4  */
+#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_4_BITS        0x2U
+/* Field Value: INV_CTRL__RGB_6_BITS, Enable inversion control for number
+ * of RGB-Bits = 6  */
+#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_6_BITS        0x3U
+/* Field Value: INV_CTRL__RGB_8_BITS, Enable inversion control for number
+ * of RGB-Bits = 8  */
+#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_8_BITS        0x4U
+/* Field Value: INV_CTRL__RGB_10_BITS, Enable inversion control for number
+ * of RGB-Bits = 10  */
+#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_10_BITS       0x5U
+/* Field Value: INV_CTRL__RGB_12_BITS, Enable inversion control for number
+ * of RGB-Bits = 12  */
+#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_12_BITS       0x6U
+/* Field Value: INV_CTRL__RGB_14_BITS, Enable inversion control for number
+ * of RGB-Bits = 14  */
+#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_14_BITS       0x7U
+/* Field Value: INV_CTRL__RGB_16_BITS, Enable inversion control for number
+ * of RGB-Bits = 16  */
+#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_16_BITS       0x8U
+/* Field Value: INV_CTRL__RGB_18_BITS, Enable inversion control for number
+ * of RGB-Bits = 18  */
+#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_18_BITS       0x9U
+/* Field Value: INV_CTRL__RGB_20_BITS, Enable inversion control for number
+ * of RGB-Bits = 20  */
+#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_20_BITS       0xAU
+/* Field Value: INV_CTRL__RGB_22_BITS, Enable inversion control for number
+ * of RGB-Bits = 22  */
+#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_22_BITS       0xBU
+/* Field Value: INV_CTRL__RGB_24_BITS, Enable inversion control for number
+ * of RGB-Bits = 24  */
+#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_24_BITS       0xCU
+/* Field Value: INV_CTRL__RGB_26_BITS, Enable inversion control for number
+ * of RGB-Bits = 26  */
+#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_26_BITS       0xDU
+/* Field Value: INV_CTRL__RGB_28_BITS, Enable inversion control for number
+ * of RGB-Bits = 28  */
+#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_28_BITS       0xEU
+/* Field Value: INV_CTRL__RGB_30_BITS, Enable inversion control for number
+ * of RGB-Bits = 30  */
+#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_30_BITS       0xFU
+#define IMXDPUV1_TCON0_TCON_CTRL_ENLVDS_MASK                 0x100U
+#define IMXDPUV1_TCON0_TCON_CTRL_ENLVDS_SHIFT                8U
+/* Field Value: ENLVDS__ENABLE_LVDS, Enable LVDS , TTL and RSDS are disable
+ *   */
+#define IMXDPUV1_TCON0_TCON_CTRL_ENLVDS__ENABLE_LVDS         0x1U
+/* Field Value: ENLVDS__DISABLE_LVDS, Disable LVDS, Enable TTL and RSDS   */
+#define IMXDPUV1_TCON0_TCON_CTRL_ENLVDS__DISABLE_LVDS        0U
+#define IMXDPUV1_TCON0_TCON_CTRL_LVDSMODE_MASK               0x200U
+#define IMXDPUV1_TCON0_TCON_CTRL_LVDSMODE_SHIFT              9U
+/* Field Value: LVDSMODE__MINI_LVDS, MiniLVDS   */
+#define IMXDPUV1_TCON0_TCON_CTRL_LVDSMODE__MINI_LVDS         0x1U
+/* Field Value: LVDSMODE__LVDS, LVDS Mode, refered to OpenLDI   */
+#define IMXDPUV1_TCON0_TCON_CTRL_LVDSMODE__LVDS              0U
+#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE_MASK           0x400U
+#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE_SHIFT          10U
+/* Field Value: LVDS_BALANCE__BALANCED, LVDS operates in 24 bits Balanced
+ * Mode   */
+#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE__BALANCED      0x1U
+/* Field Value: LVDS_BALANCE__UNBALANCED, LVDS operates in 24 bits Unbalanced
+ * Mode   */
+#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE__UNBALANCED    0U
+#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_CLOCK_INV_MASK         0x800U
+#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_CLOCK_INV_SHIFT        11U
+/* Field Value: LVDS_CLOCK_INV__INV, Invert LVDS Clock   */
+#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_CLOCK_INV__INV         0x1U
+/* Field Value: LVDS_CLOCK_INV__NON_INV, NON-Invert LVDS Clock   */
+#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_CLOCK_INV__NON_INV     0U
+#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE_MASK        0x7000U
+#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE_SHIFT       12U
+/* Field Value: MINILVDS_OPCODE__MODE_3PAIRS, MiniLVDS operates in 6 and 8
+ * bit data, three pairs   */
+#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_3PAIRS 0U
+/* Field Value: MINILVDS_OPCODE__MODE_4PAIRS, Not Implemented   */
+#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_4PAIRS 0x1U
+/* Field Value: MINILVDS_OPCODE__MODE_5PAIRS, Not Implemented   */
+#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_5PAIRS 0x2U
+/* Field Value: MINILVDS_OPCODE__MODE_6PAIRS, MiniLVDS operates in 6 and 8
+ * bit data, six pairs   */
+#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_6PAIRS 0x3U
+/* Field Value: MINILVDS_OPCODE__RESERVED1, RESERVED1  */
+#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__RESERVED1  0x4U
+/* Field Value: MINILVDS_OPCODE__RESERVED2, RESERVED2  */
+#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__RESERVED2  0x5U
+/* Field Value: MINILVDS_OPCODE__RESERVED3, RESERVED3  */
+#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__RESERVED3  0x6U
+/* Field Value: MINILVDS_OPCODE__RESERVED4, RESERVED4  */
+#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__RESERVED4  0x7U
+#define IMXDPUV1_TCON0_TCON_CTRL_DUAL_SWAP_MASK              0x8000U
+#define IMXDPUV1_TCON0_TCON_CTRL_DUAL_SWAP_SHIFT             15U
+/* Field Value: DUAL_SWAP__SWAP, swapping pixels between lower-channel and
+ * upper-channel  */
+#define IMXDPUV1_TCON0_TCON_CTRL_DUAL_SWAP__SWAP             0x1U
+/* Field Value: DUAL_SWAP__NON_SWAP, NON-swapping pixels between lower-channel
+ * and upper-channel   */
+#define IMXDPUV1_TCON0_TCON_CTRL_DUAL_SWAP__NON_SWAP         0U
+#define IMXDPUV1_TCON0_TCON_CTRL_SPLITPOSITION_MASK          0x3FFF0000U
+#define IMXDPUV1_TCON0_TCON_CTRL_SPLITPOSITION_SHIFT         16U
+
+/* Register: IMXDPUV1_tcon0_RSDSInvCtrl */
+#define IMXDPUV1_TCON0_RSDSINVCTRL                           ((uint32_t)(0xCC14))
+#define IMXDPUV1_TCON0_RSDSINVCTRL_OFFSET                    ((uint32_t)(0x14))
+#define IMXDPUV1_TCON0_RSDSINVCTRL_RESET_VALUE               0U
+#define IMXDPUV1_TCON0_RSDSINVCTRL_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_RSDSINVCTRL_RSDS_INV_MASK             0x7FFFU
+#define IMXDPUV1_TCON0_RSDSINVCTRL_RSDS_INV_SHIFT            0U
+#define IMXDPUV1_TCON0_RSDSINVCTRL_RSDS_INV_DUAL_MASK        0x7FFF0000U
+#define IMXDPUV1_TCON0_RSDSINVCTRL_RSDS_INV_DUAL_SHIFT       16U
+
+/* Register: IMXDPUV1_tcon0_MapBit3_0 */
+#define IMXDPUV1_TCON0_MAPBIT3_0                             ((uint32_t)(0xCC18))
+#define IMXDPUV1_TCON0_MAPBIT3_0_OFFSET                      ((uint32_t)(0x18))
+#define IMXDPUV1_TCON0_MAPBIT3_0_RESET_VALUE                 0x3020100U
+#define IMXDPUV1_TCON0_MAPBIT3_0_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT0_MASK                0x3FU
+#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT0_SHIFT               0U
+#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT1_MASK                0x3F00U
+#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT1_SHIFT               8U
+#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT2_MASK                0x3F0000U
+#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT2_SHIFT               16U
+#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT3_MASK                0x3F000000U
+#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT3_SHIFT               24U
+
+/* Register: IMXDPUV1_tcon0_MapBit7_4 */
+#define IMXDPUV1_TCON0_MAPBIT7_4                             ((uint32_t)(0xCC1C))
+#define IMXDPUV1_TCON0_MAPBIT7_4_OFFSET                      ((uint32_t)(0x1C))
+#define IMXDPUV1_TCON0_MAPBIT7_4_RESET_VALUE                 0x7060504U
+#define IMXDPUV1_TCON0_MAPBIT7_4_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT4_MASK                0x3FU
+#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT4_SHIFT               0U
+#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT5_MASK                0x3F00U
+#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT5_SHIFT               8U
+#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT6_MASK                0x3F0000U
+#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT6_SHIFT               16U
+#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT7_MASK                0x3F000000U
+#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT7_SHIFT               24U
+
+/* Register: IMXDPUV1_tcon0_MapBit11_8 */
+#define IMXDPUV1_TCON0_MAPBIT11_8                            ((uint32_t)(0xCC20))
+#define IMXDPUV1_TCON0_MAPBIT11_8_OFFSET                     ((uint32_t)(0x20))
+#define IMXDPUV1_TCON0_MAPBIT11_8_RESET_VALUE                0xB0A0908U
+#define IMXDPUV1_TCON0_MAPBIT11_8_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT8_MASK               0x3FU
+#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT8_SHIFT              0U
+#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT9_MASK               0x3F00U
+#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT9_SHIFT              8U
+#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT10_MASK              0x3F0000U
+#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT10_SHIFT             16U
+#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT11_MASK              0x3F000000U
+#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT11_SHIFT             24U
+
+/* Register: IMXDPUV1_tcon0_MapBit15_12 */
+#define IMXDPUV1_TCON0_MAPBIT15_12                           ((uint32_t)(0xCC24))
+#define IMXDPUV1_TCON0_MAPBIT15_12_OFFSET                    ((uint32_t)(0x24))
+#define IMXDPUV1_TCON0_MAPBIT15_12_RESET_VALUE               0xF0E0D0CU
+#define IMXDPUV1_TCON0_MAPBIT15_12_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT12_MASK             0x3FU
+#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT12_SHIFT            0U
+#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT13_MASK             0x3F00U
+#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT13_SHIFT            8U
+#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT14_MASK             0x3F0000U
+#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT14_SHIFT            16U
+#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT15_MASK             0x3F000000U
+#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT15_SHIFT            24U
+
+/* Register: IMXDPUV1_tcon0_MapBit19_16 */
+#define IMXDPUV1_TCON0_MAPBIT19_16                           ((uint32_t)(0xCC28))
+#define IMXDPUV1_TCON0_MAPBIT19_16_OFFSET                    ((uint32_t)(0x28))
+#define IMXDPUV1_TCON0_MAPBIT19_16_RESET_VALUE               0x13121110U
+#define IMXDPUV1_TCON0_MAPBIT19_16_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT16_MASK             0x3FU
+#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT16_SHIFT            0U
+#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT17_MASK             0x3F00U
+#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT17_SHIFT            8U
+#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT18_MASK             0x3F0000U
+#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT18_SHIFT            16U
+#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT19_MASK             0x3F000000U
+#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT19_SHIFT            24U
+
+/* Register: IMXDPUV1_tcon0_MapBit23_20 */
+#define IMXDPUV1_TCON0_MAPBIT23_20                           ((uint32_t)(0xCC2C))
+#define IMXDPUV1_TCON0_MAPBIT23_20_OFFSET                    ((uint32_t)(0x2C))
+#define IMXDPUV1_TCON0_MAPBIT23_20_RESET_VALUE               0x17161514U
+#define IMXDPUV1_TCON0_MAPBIT23_20_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT20_MASK             0x3FU
+#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT20_SHIFT            0U
+#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT21_MASK             0x3F00U
+#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT21_SHIFT            8U
+#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT22_MASK             0x3F0000U
+#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT22_SHIFT            16U
+#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT23_MASK             0x3F000000U
+#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT23_SHIFT            24U
+
+/* Register: IMXDPUV1_tcon0_MapBit27_24 */
+#define IMXDPUV1_TCON0_MAPBIT27_24                           ((uint32_t)(0xCC30))
+#define IMXDPUV1_TCON0_MAPBIT27_24_OFFSET                    ((uint32_t)(0x30))
+#define IMXDPUV1_TCON0_MAPBIT27_24_RESET_VALUE               0x1B1A1918U
+#define IMXDPUV1_TCON0_MAPBIT27_24_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT24_MASK             0x3FU
+#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT24_SHIFT            0U
+#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT25_MASK             0x3F00U
+#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT25_SHIFT            8U
+#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT26_MASK             0x3F0000U
+#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT26_SHIFT            16U
+#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT27_MASK             0x3F000000U
+#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT27_SHIFT            24U
+
+/* Register: IMXDPUV1_tcon0_MapBit31_28 */
+#define IMXDPUV1_TCON0_MAPBIT31_28                           ((uint32_t)(0xCC34))
+#define IMXDPUV1_TCON0_MAPBIT31_28_OFFSET                    ((uint32_t)(0x34))
+#define IMXDPUV1_TCON0_MAPBIT31_28_RESET_VALUE               0x1F1E1D1CU
+#define IMXDPUV1_TCON0_MAPBIT31_28_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT28_MASK             0x3FU
+#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT28_SHIFT            0U
+#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT29_MASK             0x3F00U
+#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT29_SHIFT            8U
+#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT30_MASK             0x3F0000U
+#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT30_SHIFT            16U
+#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT31_MASK             0x3F000000U
+#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT31_SHIFT            24U
+
+/* Register: IMXDPUV1_tcon0_MapBit34_32 */
+#define IMXDPUV1_TCON0_MAPBIT34_32                           ((uint32_t)(0xCC38))
+#define IMXDPUV1_TCON0_MAPBIT34_32_OFFSET                    ((uint32_t)(0x38))
+#define IMXDPUV1_TCON0_MAPBIT34_32_RESET_VALUE               0x222120U
+#define IMXDPUV1_TCON0_MAPBIT34_32_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT32_MASK             0x3FU
+#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT32_SHIFT            0U
+#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT33_MASK             0x3F00U
+#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT33_SHIFT            8U
+#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT34_MASK             0x3F0000U
+#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT34_SHIFT            16U
+
+/* Register: IMXDPUV1_tcon0_MapBit3_0_Dual */
+#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL                        ((uint32_t)(0xCC3C))
+#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_OFFSET                 ((uint32_t)(0x3C))
+#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_RESET_VALUE            0x3020100U
+#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT0_DUAL_MASK      0x3FU
+#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT0_DUAL_SHIFT     0U
+#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT1_DUAL_MASK      0x3F00U
+#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT1_DUAL_SHIFT     8U
+#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT2_DUAL_MASK      0x3F0000U
+#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT2_DUAL_SHIFT     16U
+#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT3_DUAL_MASK      0x3F000000U
+#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT3_DUAL_SHIFT     24U
+
+/* Register: IMXDPUV1_tcon0_MapBit7_4_Dual */
+#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL                        ((uint32_t)(0xCC40))
+#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_OFFSET                 ((uint32_t)(0x40))
+#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_RESET_VALUE            0x7060504U
+#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT4_DUAL_MASK      0x3FU
+#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT4_DUAL_SHIFT     0U
+#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT5_DUAL_MASK      0x3F00U
+#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT5_DUAL_SHIFT     8U
+#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT6_DUAL_MASK      0x3F0000U
+#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT6_DUAL_SHIFT     16U
+#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT7_DUAL_MASK      0x3F000000U
+#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT7_DUAL_SHIFT     24U
+
+/* Register: IMXDPUV1_tcon0_MapBit11_8_Dual */
+#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL                       ((uint32_t)(0xCC44))
+#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_OFFSET                ((uint32_t)(0x44))
+#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_RESET_VALUE           0xB0A0908U
+#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT8_DUAL_MASK     0x3FU
+#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT8_DUAL_SHIFT    0U
+#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT9_DUAL_MASK     0x3F00U
+#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT9_DUAL_SHIFT    8U
+#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT10_DUAL_MASK    0x3F0000U
+#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT10_DUAL_SHIFT   16U
+#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT11_DUAL_MASK    0x3F000000U
+#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT11_DUAL_SHIFT   24U
+
+/* Register: IMXDPUV1_tcon0_MapBit15_12_Dual */
+#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL                      ((uint32_t)(0xCC48))
+#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_OFFSET               ((uint32_t)(0x48))
+#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_RESET_VALUE          0xF0E0D0CU
+#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT12_DUAL_MASK   0x3FU
+#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT12_DUAL_SHIFT  0U
+#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT13_DUAL_MASK   0x3F00U
+#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT13_DUAL_SHIFT  8U
+#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT14_DUAL_MASK   0x3F0000U
+#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT14_DUAL_SHIFT  16U
+#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT15_DUAL_MASK   0x3F000000U
+#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT15_DUAL_SHIFT  24U
+
+/* Register: IMXDPUV1_tcon0_MapBit19_16_Dual */
+#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL                      ((uint32_t)(0xCC4C))
+#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_OFFSET               ((uint32_t)(0x4C))
+#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_RESET_VALUE          0x13121110U
+#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT16_DUAL_MASK   0x3FU
+#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT16_DUAL_SHIFT  0U
+#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT17_DUAL_MASK   0x3F00U
+#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT17_DUAL_SHIFT  8U
+#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT18_DUAL_MASK   0x3F0000U
+#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT18_DUAL_SHIFT  16U
+#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT19_DUAL_MASK   0x3F000000U
+#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT19_DUAL_SHIFT  24U
+
+/* Register: IMXDPUV1_tcon0_MapBit23_20_Dual */
+#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL                      ((uint32_t)(0xCC50))
+#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_OFFSET               ((uint32_t)(0x50))
+#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_RESET_VALUE          0x17161514U
+#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT20_DUAL_MASK   0x3FU
+#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT20_DUAL_SHIFT  0U
+#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT21_DUAL_MASK   0x3F00U
+#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT21_DUAL_SHIFT  8U
+#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT22_DUAL_MASK   0x3F0000U
+#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT22_DUAL_SHIFT  16U
+#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT23_DUAL_MASK   0x3F000000U
+#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT23_DUAL_SHIFT  24U
+
+/* Register: IMXDPUV1_tcon0_MapBit27_24_Dual */
+#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL                      ((uint32_t)(0xCC54))
+#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_OFFSET               ((uint32_t)(0x54))
+#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_RESET_VALUE          0x1B1A1918U
+#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT24_DUAL_MASK   0x3FU
+#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT24_DUAL_SHIFT  0U
+#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT25_DUAL_MASK   0x3F00U
+#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT25_DUAL_SHIFT  8U
+#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT26_DUAL_MASK   0x3F0000U
+#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT26_DUAL_SHIFT  16U
+#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT27_DUAL_MASK   0x3F000000U
+#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT27_DUAL_SHIFT  24U
+
+/* Register: IMXDPUV1_tcon0_MapBit31_28_Dual */
+#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL                      ((uint32_t)(0xCC58))
+#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_OFFSET               ((uint32_t)(0x58))
+#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_RESET_VALUE          0x1F1E1D1CU
+#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT28_DUAL_MASK   0x3FU
+#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT28_DUAL_SHIFT  0U
+#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT29_DUAL_MASK   0x3F00U
+#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT29_DUAL_SHIFT  8U
+#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT30_DUAL_MASK   0x3F0000U
+#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT30_DUAL_SHIFT  16U
+#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT31_DUAL_MASK   0x3F000000U
+#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT31_DUAL_SHIFT  24U
+
+/* Register: IMXDPUV1_tcon0_MapBit34_32_Dual */
+#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL                      ((uint32_t)(0xCC5C))
+#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_OFFSET               ((uint32_t)(0x5C))
+#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_RESET_VALUE          0x222120U
+#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT32_DUAL_MASK   0x3FU
+#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT32_DUAL_SHIFT  0U
+#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT33_DUAL_MASK   0x3F00U
+#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT33_DUAL_SHIFT  8U
+#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT34_DUAL_MASK   0x3F0000U
+#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT34_DUAL_SHIFT  16U
+
+/* Register: IMXDPUV1_tcon0_SPG0PosOn */
+#define IMXDPUV1_TCON0_SPG0POSON                             ((uint32_t)(0xCC60))
+#define IMXDPUV1_TCON0_SPG0POSON_OFFSET                      ((uint32_t)(0x60))
+#define IMXDPUV1_TCON0_SPG0POSON_RESET_VALUE                 0x1480000U
+#define IMXDPUV1_TCON0_SPG0POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_Y0_MASK             0x7FFFU
+#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_Y0_SHIFT            0U
+#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_FIELD0_MASK         0x8000U
+#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_FIELD0_SHIFT        15U
+#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_X0_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_X0_SHIFT            16U
+#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_TOGGLE0_MASK        0x80000000U
+#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_TOGGLE0_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon0_SPG0MaskOn */
+#define IMXDPUV1_TCON0_SPG0MASKON                            ((uint32_t)(0xCC64))
+#define IMXDPUV1_TCON0_SPG0MASKON_OFFSET                     ((uint32_t)(0x64))
+#define IMXDPUV1_TCON0_SPG0MASKON_RESET_VALUE                0xFFFFU
+#define IMXDPUV1_TCON0_SPG0MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG0MASKON_SPGMKON0_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG0MASKON_SPGMKON0_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon0_SPG0PosOff */
+#define IMXDPUV1_TCON0_SPG0POSOFF                            ((uint32_t)(0xCC68))
+#define IMXDPUV1_TCON0_SPG0POSOFF_OFFSET                     ((uint32_t)(0x68))
+#define IMXDPUV1_TCON0_SPG0POSOFF_RESET_VALUE                0x1680000U
+#define IMXDPUV1_TCON0_SPG0POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_Y0_MASK           0x7FFFU
+#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_Y0_SHIFT          0U
+#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_FIELD0_MASK       0x8000U
+#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_FIELD0_SHIFT      15U
+#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_X0_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_X0_SHIFT          16U
+#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_TOGGLE0_MASK      0x80000000U
+#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_TOGGLE0_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon0_SPG0MaskOff */
+#define IMXDPUV1_TCON0_SPG0MASKOFF                           ((uint32_t)(0xCC6C))
+#define IMXDPUV1_TCON0_SPG0MASKOFF_OFFSET                    ((uint32_t)(0x6C))
+#define IMXDPUV1_TCON0_SPG0MASKOFF_RESET_VALUE               0xFFFFU
+#define IMXDPUV1_TCON0_SPG0MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG0MASKOFF_SPGMKOFF0_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG0MASKOFF_SPGMKOFF0_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon0_SPG1PosOn */
+#define IMXDPUV1_TCON0_SPG1POSON                             ((uint32_t)(0xCC70))
+#define IMXDPUV1_TCON0_SPG1POSON_OFFSET                      ((uint32_t)(0x70))
+#define IMXDPUV1_TCON0_SPG1POSON_RESET_VALUE                 0xF3U
+#define IMXDPUV1_TCON0_SPG1POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_Y1_MASK             0x7FFFU
+#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_Y1_SHIFT            0U
+#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_FIELD1_MASK         0x8000U
+#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_FIELD1_SHIFT        15U
+#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_X1_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_X1_SHIFT            16U
+#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_TOGGLE1_MASK        0x80000000U
+#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_TOGGLE1_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon0_SPG1MaskOn */
+#define IMXDPUV1_TCON0_SPG1MASKON                            ((uint32_t)(0xCC74))
+#define IMXDPUV1_TCON0_SPG1MASKON_OFFSET                     ((uint32_t)(0x74))
+#define IMXDPUV1_TCON0_SPG1MASKON_RESET_VALUE                0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG1MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG1MASKON_SPGMKON1_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG1MASKON_SPGMKON1_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon0_SPG1PosOff */
+#define IMXDPUV1_TCON0_SPG1POSOFF                            ((uint32_t)(0xCC78))
+#define IMXDPUV1_TCON0_SPG1POSOFF_OFFSET                     ((uint32_t)(0x78))
+#define IMXDPUV1_TCON0_SPG1POSOFF_RESET_VALUE                0xF7U
+#define IMXDPUV1_TCON0_SPG1POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_Y1_MASK           0x7FFFU
+#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_Y1_SHIFT          0U
+#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_FIELD1_MASK       0x8000U
+#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_FIELD1_SHIFT      15U
+#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_X1_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_X1_SHIFT          16U
+#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_TOGGLE1_MASK      0x80000000U
+#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_TOGGLE1_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon0_SPG1MaskOff */
+#define IMXDPUV1_TCON0_SPG1MASKOFF                           ((uint32_t)(0xCC7C))
+#define IMXDPUV1_TCON0_SPG1MASKOFF_OFFSET                    ((uint32_t)(0x7C))
+#define IMXDPUV1_TCON0_SPG1MASKOFF_RESET_VALUE               0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG1MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG1MASKOFF_SPGMKOFF1_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG1MASKOFF_SPGMKOFF1_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon0_SPG2PosOn */
+#define IMXDPUV1_TCON0_SPG2POSON                             ((uint32_t)(0xCC80))
+#define IMXDPUV1_TCON0_SPG2POSON_OFFSET                      ((uint32_t)(0x80))
+#define IMXDPUV1_TCON0_SPG2POSON_RESET_VALUE                 0U
+#define IMXDPUV1_TCON0_SPG2POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_Y2_MASK             0x7FFFU
+#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_Y2_SHIFT            0U
+#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_FIELD2_MASK         0x8000U
+#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_FIELD2_SHIFT        15U
+#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_X2_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_X2_SHIFT            16U
+#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_TOGGLE2_MASK        0x80000000U
+#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_TOGGLE2_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon0_SPG2MaskOn */
+#define IMXDPUV1_TCON0_SPG2MASKON                            ((uint32_t)(0xCC84))
+#define IMXDPUV1_TCON0_SPG2MASKON_OFFSET                     ((uint32_t)(0x84))
+#define IMXDPUV1_TCON0_SPG2MASKON_RESET_VALUE                0xFFFFU
+#define IMXDPUV1_TCON0_SPG2MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG2MASKON_SPGMKON2_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG2MASKON_SPGMKON2_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon0_SPG2PosOff */
+#define IMXDPUV1_TCON0_SPG2POSOFF                            ((uint32_t)(0xCC88))
+#define IMXDPUV1_TCON0_SPG2POSOFF_OFFSET                     ((uint32_t)(0x88))
+#define IMXDPUV1_TCON0_SPG2POSOFF_RESET_VALUE                0x1400000U
+#define IMXDPUV1_TCON0_SPG2POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_Y2_MASK           0x7FFFU
+#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_Y2_SHIFT          0U
+#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_FIELD2_MASK       0x8000U
+#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_FIELD2_SHIFT      15U
+#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_X2_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_X2_SHIFT          16U
+#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_TOGGLE2_MASK      0x80000000U
+#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_TOGGLE2_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon0_SPG2MaskOff */
+#define IMXDPUV1_TCON0_SPG2MASKOFF                           ((uint32_t)(0xCC8C))
+#define IMXDPUV1_TCON0_SPG2MASKOFF_OFFSET                    ((uint32_t)(0x8C))
+#define IMXDPUV1_TCON0_SPG2MASKOFF_RESET_VALUE               0xFFFFU
+#define IMXDPUV1_TCON0_SPG2MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG2MASKOFF_SPGMKOFF2_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG2MASKOFF_SPGMKOFF2_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon0_SPG3PosOn */
+#define IMXDPUV1_TCON0_SPG3POSON                             ((uint32_t)(0xCC90))
+#define IMXDPUV1_TCON0_SPG3POSON_OFFSET                      ((uint32_t)(0x90))
+#define IMXDPUV1_TCON0_SPG3POSON_RESET_VALUE                 0U
+#define IMXDPUV1_TCON0_SPG3POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_Y3_MASK             0x7FFFU
+#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_Y3_SHIFT            0U
+#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_FIELD3_MASK         0x8000U
+#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_FIELD3_SHIFT        15U
+#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_X3_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_X3_SHIFT            16U
+#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_TOGGLE3_MASK        0x80000000U
+#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_TOGGLE3_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon0_SPG3MaskOn */
+#define IMXDPUV1_TCON0_SPG3MASKON                            ((uint32_t)(0xCC94))
+#define IMXDPUV1_TCON0_SPG3MASKON_OFFSET                     ((uint32_t)(0x94))
+#define IMXDPUV1_TCON0_SPG3MASKON_RESET_VALUE                0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG3MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG3MASKON_SPGMKON3_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG3MASKON_SPGMKON3_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon0_SPG3PosOff */
+#define IMXDPUV1_TCON0_SPG3POSOFF                            ((uint32_t)(0xCC98))
+#define IMXDPUV1_TCON0_SPG3POSOFF_OFFSET                     ((uint32_t)(0x98))
+#define IMXDPUV1_TCON0_SPG3POSOFF_RESET_VALUE                0xF0U
+#define IMXDPUV1_TCON0_SPG3POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_Y3_MASK           0x7FFFU
+#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_Y3_SHIFT          0U
+#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_FIELD3_MASK       0x8000U
+#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_FIELD3_SHIFT      15U
+#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_X3_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_X3_SHIFT          16U
+#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_TOGGLE3_MASK      0x80000000U
+#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_TOGGLE3_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon0_SPG3MaskOff */
+#define IMXDPUV1_TCON0_SPG3MASKOFF                           ((uint32_t)(0xCC9C))
+#define IMXDPUV1_TCON0_SPG3MASKOFF_OFFSET                    ((uint32_t)(0x9C))
+#define IMXDPUV1_TCON0_SPG3MASKOFF_RESET_VALUE               0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG3MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG3MASKOFF_SPGMKOFF3_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG3MASKOFF_SPGMKOFF3_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon0_SPG4PosOn */
+#define IMXDPUV1_TCON0_SPG4POSON                             ((uint32_t)(0xCCA0))
+#define IMXDPUV1_TCON0_SPG4POSON_OFFSET                      ((uint32_t)(0xA0))
+#define IMXDPUV1_TCON0_SPG4POSON_RESET_VALUE                 0U
+#define IMXDPUV1_TCON0_SPG4POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_Y4_MASK             0x7FFFU
+#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_Y4_SHIFT            0U
+#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_FIELD4_MASK         0x8000U
+#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_FIELD4_SHIFT        15U
+#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_X4_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_X4_SHIFT            16U
+#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_TOGGLE4_MASK        0x80000000U
+#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_TOGGLE4_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon0_SPG4MaskOn */
+#define IMXDPUV1_TCON0_SPG4MASKON                            ((uint32_t)(0xCCA4))
+#define IMXDPUV1_TCON0_SPG4MASKON_OFFSET                     ((uint32_t)(0xA4))
+#define IMXDPUV1_TCON0_SPG4MASKON_RESET_VALUE                0U
+#define IMXDPUV1_TCON0_SPG4MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG4MASKON_SPGMKON4_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG4MASKON_SPGMKON4_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon0_SPG4PosOff */
+#define IMXDPUV1_TCON0_SPG4POSOFF                            ((uint32_t)(0xCCA8))
+#define IMXDPUV1_TCON0_SPG4POSOFF_OFFSET                     ((uint32_t)(0xA8))
+#define IMXDPUV1_TCON0_SPG4POSOFF_RESET_VALUE                0U
+#define IMXDPUV1_TCON0_SPG4POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_Y4_MASK           0x7FFFU
+#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_Y4_SHIFT          0U
+#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_FIELD4_MASK       0x8000U
+#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_FIELD4_SHIFT      15U
+#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_X4_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_X4_SHIFT          16U
+#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_TOGGLE4_MASK      0x80000000U
+#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_TOGGLE4_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon0_SPG4MaskOff */
+#define IMXDPUV1_TCON0_SPG4MASKOFF                           ((uint32_t)(0xCCAC))
+#define IMXDPUV1_TCON0_SPG4MASKOFF_OFFSET                    ((uint32_t)(0xAC))
+#define IMXDPUV1_TCON0_SPG4MASKOFF_RESET_VALUE               0U
+#define IMXDPUV1_TCON0_SPG4MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG4MASKOFF_SPGMKOFF4_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG4MASKOFF_SPGMKOFF4_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon0_SPG5PosOn */
+#define IMXDPUV1_TCON0_SPG5POSON                             ((uint32_t)(0xCCB0))
+#define IMXDPUV1_TCON0_SPG5POSON_OFFSET                      ((uint32_t)(0xB0))
+#define IMXDPUV1_TCON0_SPG5POSON_RESET_VALUE                 0U
+#define IMXDPUV1_TCON0_SPG5POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_Y5_MASK             0x7FFFU
+#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_Y5_SHIFT            0U
+#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_FIELD5_MASK         0x8000U
+#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_FIELD5_SHIFT        15U
+#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_X5_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_X5_SHIFT            16U
+#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_TOGGLE5_MASK        0x80000000U
+#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_TOGGLE5_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon0_SPG5MaskOn */
+#define IMXDPUV1_TCON0_SPG5MASKON                            ((uint32_t)(0xCCB4))
+#define IMXDPUV1_TCON0_SPG5MASKON_OFFSET                     ((uint32_t)(0xB4))
+#define IMXDPUV1_TCON0_SPG5MASKON_RESET_VALUE                0U
+#define IMXDPUV1_TCON0_SPG5MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG5MASKON_SPGMKON5_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG5MASKON_SPGMKON5_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon0_SPG5PosOff */
+#define IMXDPUV1_TCON0_SPG5POSOFF                            ((uint32_t)(0xCCB8))
+#define IMXDPUV1_TCON0_SPG5POSOFF_OFFSET                     ((uint32_t)(0xB8))
+#define IMXDPUV1_TCON0_SPG5POSOFF_RESET_VALUE                0U
+#define IMXDPUV1_TCON0_SPG5POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_Y5_MASK           0x7FFFU
+#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_Y5_SHIFT          0U
+#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_FIELD5_MASK       0x8000U
+#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_FIELD5_SHIFT      15U
+#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_X5_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_X5_SHIFT          16U
+#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_TOGGLE5_MASK      0x80000000U
+#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_TOGGLE5_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon0_SPG5MaskOff */
+#define IMXDPUV1_TCON0_SPG5MASKOFF                           ((uint32_t)(0xCCBC))
+#define IMXDPUV1_TCON0_SPG5MASKOFF_OFFSET                    ((uint32_t)(0xBC))
+#define IMXDPUV1_TCON0_SPG5MASKOFF_RESET_VALUE               0U
+#define IMXDPUV1_TCON0_SPG5MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG5MASKOFF_SPGMKOFF5_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG5MASKOFF_SPGMKOFF5_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon0_SPG6PosOn */
+#define IMXDPUV1_TCON0_SPG6POSON                             ((uint32_t)(0xCCC0))
+#define IMXDPUV1_TCON0_SPG6POSON_OFFSET                      ((uint32_t)(0xC0))
+#define IMXDPUV1_TCON0_SPG6POSON_RESET_VALUE                 0U
+#define IMXDPUV1_TCON0_SPG6POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_Y6_MASK             0x7FFFU
+#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_Y6_SHIFT            0U
+#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_FIELD6_MASK         0x8000U
+#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_FIELD6_SHIFT        15U
+#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_X6_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_X6_SHIFT            16U
+#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_TOGGLE6_MASK        0x80000000U
+#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_TOGGLE6_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon0_SPG6MaskOn */
+#define IMXDPUV1_TCON0_SPG6MASKON                            ((uint32_t)(0xCCC4))
+#define IMXDPUV1_TCON0_SPG6MASKON_OFFSET                     ((uint32_t)(0xC4))
+#define IMXDPUV1_TCON0_SPG6MASKON_RESET_VALUE                0U
+#define IMXDPUV1_TCON0_SPG6MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG6MASKON_SPGMKON6_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG6MASKON_SPGMKON6_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon0_SPG6PosOff */
+#define IMXDPUV1_TCON0_SPG6POSOFF                            ((uint32_t)(0xCCC8))
+#define IMXDPUV1_TCON0_SPG6POSOFF_OFFSET                     ((uint32_t)(0xC8))
+#define IMXDPUV1_TCON0_SPG6POSOFF_RESET_VALUE                0U
+#define IMXDPUV1_TCON0_SPG6POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_Y6_MASK           0x7FFFU
+#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_Y6_SHIFT          0U
+#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_FIELD6_MASK       0x8000U
+#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_FIELD6_SHIFT      15U
+#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_X6_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_X6_SHIFT          16U
+#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_TOGGLE6_MASK      0x80000000U
+#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_TOGGLE6_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon0_SPG6MaskOff */
+#define IMXDPUV1_TCON0_SPG6MASKOFF                           ((uint32_t)(0xCCCC))
+#define IMXDPUV1_TCON0_SPG6MASKOFF_OFFSET                    ((uint32_t)(0xCC))
+#define IMXDPUV1_TCON0_SPG6MASKOFF_RESET_VALUE               0U
+#define IMXDPUV1_TCON0_SPG6MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG6MASKOFF_SPGMKOFF6_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG6MASKOFF_SPGMKOFF6_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon0_SPG7PosOn */
+#define IMXDPUV1_TCON0_SPG7POSON                             ((uint32_t)(0xCCD0))
+#define IMXDPUV1_TCON0_SPG7POSON_OFFSET                      ((uint32_t)(0xD0))
+#define IMXDPUV1_TCON0_SPG7POSON_RESET_VALUE                 0U
+#define IMXDPUV1_TCON0_SPG7POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_Y7_MASK             0x7FFFU
+#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_Y7_SHIFT            0U
+#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_FIELD7_MASK         0x8000U
+#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_FIELD7_SHIFT        15U
+#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_X7_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_X7_SHIFT            16U
+#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_TOGGLE7_MASK        0x80000000U
+#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_TOGGLE7_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon0_SPG7MaskOn */
+#define IMXDPUV1_TCON0_SPG7MASKON                            ((uint32_t)(0xCCD4))
+#define IMXDPUV1_TCON0_SPG7MASKON_OFFSET                     ((uint32_t)(0xD4))
+#define IMXDPUV1_TCON0_SPG7MASKON_RESET_VALUE                0U
+#define IMXDPUV1_TCON0_SPG7MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG7MASKON_SPGMKON7_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG7MASKON_SPGMKON7_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon0_SPG7PosOff */
+#define IMXDPUV1_TCON0_SPG7POSOFF                            ((uint32_t)(0xCCD8))
+#define IMXDPUV1_TCON0_SPG7POSOFF_OFFSET                     ((uint32_t)(0xD8))
+#define IMXDPUV1_TCON0_SPG7POSOFF_RESET_VALUE                0U
+#define IMXDPUV1_TCON0_SPG7POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_Y7_MASK           0x7FFFU
+#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_Y7_SHIFT          0U
+#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_FIELD7_MASK       0x8000U
+#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_FIELD7_SHIFT      15U
+#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_X7_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_X7_SHIFT          16U
+#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_TOGGLE7_MASK      0x80000000U
+#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_TOGGLE7_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon0_SPG7MaskOff */
+#define IMXDPUV1_TCON0_SPG7MASKOFF                           ((uint32_t)(0xCCDC))
+#define IMXDPUV1_TCON0_SPG7MASKOFF_OFFSET                    ((uint32_t)(0xDC))
+#define IMXDPUV1_TCON0_SPG7MASKOFF_RESET_VALUE               0U
+#define IMXDPUV1_TCON0_SPG7MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG7MASKOFF_SPGMKOFF7_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG7MASKOFF_SPGMKOFF7_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon0_SPG8PosOn */
+#define IMXDPUV1_TCON0_SPG8POSON                             ((uint32_t)(0xCCE0))
+#define IMXDPUV1_TCON0_SPG8POSON_OFFSET                      ((uint32_t)(0xE0))
+#define IMXDPUV1_TCON0_SPG8POSON_RESET_VALUE                 0U
+#define IMXDPUV1_TCON0_SPG8POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_Y8_MASK             0x7FFFU
+#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_Y8_SHIFT            0U
+#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_FIELD8_MASK         0x8000U
+#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_FIELD8_SHIFT        15U
+#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_X8_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_X8_SHIFT            16U
+#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_TOGGLE8_MASK        0x80000000U
+#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_TOGGLE8_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon0_SPG8MaskOn */
+#define IMXDPUV1_TCON0_SPG8MASKON                            ((uint32_t)(0xCCE4))
+#define IMXDPUV1_TCON0_SPG8MASKON_OFFSET                     ((uint32_t)(0xE4))
+#define IMXDPUV1_TCON0_SPG8MASKON_RESET_VALUE                0U
+#define IMXDPUV1_TCON0_SPG8MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG8MASKON_SPGMKON8_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG8MASKON_SPGMKON8_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon0_SPG8PosOff */
+#define IMXDPUV1_TCON0_SPG8POSOFF                            ((uint32_t)(0xCCE8))
+#define IMXDPUV1_TCON0_SPG8POSOFF_OFFSET                     ((uint32_t)(0xE8))
+#define IMXDPUV1_TCON0_SPG8POSOFF_RESET_VALUE                0U
+#define IMXDPUV1_TCON0_SPG8POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_Y8_MASK           0x7FFFU
+#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_Y8_SHIFT          0U
+#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_FIELD8_MASK       0x8000U
+#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_FIELD8_SHIFT      15U
+#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_X8_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_X8_SHIFT          16U
+#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_TOGGLE8_MASK      0x80000000U
+#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_TOGGLE8_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon0_SPG8MaskOff */
+#define IMXDPUV1_TCON0_SPG8MASKOFF                           ((uint32_t)(0xCCEC))
+#define IMXDPUV1_TCON0_SPG8MASKOFF_OFFSET                    ((uint32_t)(0xEC))
+#define IMXDPUV1_TCON0_SPG8MASKOFF_RESET_VALUE               0U
+#define IMXDPUV1_TCON0_SPG8MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG8MASKOFF_SPGMKOFF8_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG8MASKOFF_SPGMKOFF8_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon0_SPG9PosOn */
+#define IMXDPUV1_TCON0_SPG9POSON                             ((uint32_t)(0xCCF0))
+#define IMXDPUV1_TCON0_SPG9POSON_OFFSET                      ((uint32_t)(0xF0))
+#define IMXDPUV1_TCON0_SPG9POSON_RESET_VALUE                 0U
+#define IMXDPUV1_TCON0_SPG9POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_Y9_MASK             0x7FFFU
+#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_Y9_SHIFT            0U
+#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_FIELD9_MASK         0x8000U
+#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_FIELD9_SHIFT        15U
+#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_X9_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_X9_SHIFT            16U
+#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_TOGGLE9_MASK        0x80000000U
+#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_TOGGLE9_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon0_SPG9MaskOn */
+#define IMXDPUV1_TCON0_SPG9MASKON                            ((uint32_t)(0xCCF4))
+#define IMXDPUV1_TCON0_SPG9MASKON_OFFSET                     ((uint32_t)(0xF4))
+#define IMXDPUV1_TCON0_SPG9MASKON_RESET_VALUE                0U
+#define IMXDPUV1_TCON0_SPG9MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG9MASKON_SPGMKON9_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG9MASKON_SPGMKON9_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon0_SPG9PosOff */
+#define IMXDPUV1_TCON0_SPG9POSOFF                            ((uint32_t)(0xCCF8))
+#define IMXDPUV1_TCON0_SPG9POSOFF_OFFSET                     ((uint32_t)(0xF8))
+#define IMXDPUV1_TCON0_SPG9POSOFF_RESET_VALUE                0U
+#define IMXDPUV1_TCON0_SPG9POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_Y9_MASK           0x7FFFU
+#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_Y9_SHIFT          0U
+#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_FIELD9_MASK       0x8000U
+#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_FIELD9_SHIFT      15U
+#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_X9_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_X9_SHIFT          16U
+#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_TOGGLE9_MASK      0x80000000U
+#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_TOGGLE9_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon0_SPG9MaskOff */
+#define IMXDPUV1_TCON0_SPG9MASKOFF                           ((uint32_t)(0xCCFC))
+#define IMXDPUV1_TCON0_SPG9MASKOFF_OFFSET                    ((uint32_t)(0xFC))
+#define IMXDPUV1_TCON0_SPG9MASKOFF_RESET_VALUE               0U
+#define IMXDPUV1_TCON0_SPG9MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG9MASKOFF_SPGMKOFF9_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG9MASKOFF_SPGMKOFF9_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon0_SPG10PosOn */
+#define IMXDPUV1_TCON0_SPG10POSON                            ((uint32_t)(0xCD00))
+#define IMXDPUV1_TCON0_SPG10POSON_OFFSET                     ((uint32_t)(0x100))
+#define IMXDPUV1_TCON0_SPG10POSON_RESET_VALUE                0U
+#define IMXDPUV1_TCON0_SPG10POSON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_Y10_MASK           0x7FFFU
+#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_Y10_SHIFT          0U
+#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_FIELD10_MASK       0x8000U
+#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_FIELD10_SHIFT      15U
+#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_X10_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_X10_SHIFT          16U
+#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_TOGGLE10_MASK      0x80000000U
+#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_TOGGLE10_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon0_SPG10MaskOn */
+#define IMXDPUV1_TCON0_SPG10MASKON                           ((uint32_t)(0xCD04))
+#define IMXDPUV1_TCON0_SPG10MASKON_OFFSET                    ((uint32_t)(0x104))
+#define IMXDPUV1_TCON0_SPG10MASKON_RESET_VALUE               0U
+#define IMXDPUV1_TCON0_SPG10MASKON_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG10MASKON_SPGMKON10_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG10MASKON_SPGMKON10_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon0_SPG10PosOff */
+#define IMXDPUV1_TCON0_SPG10POSOFF                           ((uint32_t)(0xCD08))
+#define IMXDPUV1_TCON0_SPG10POSOFF_OFFSET                    ((uint32_t)(0x108))
+#define IMXDPUV1_TCON0_SPG10POSOFF_RESET_VALUE               0U
+#define IMXDPUV1_TCON0_SPG10POSOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_Y10_MASK         0x7FFFU
+#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_Y10_SHIFT        0U
+#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_FIELD10_MASK     0x8000U
+#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_FIELD10_SHIFT    15U
+#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_X10_MASK         0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_X10_SHIFT        16U
+#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_TOGGLE10_MASK    0x80000000U
+#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_TOGGLE10_SHIFT   31U
+
+/* Register: IMXDPUV1_tcon0_SPG10MaskOff */
+#define IMXDPUV1_TCON0_SPG10MASKOFF                          ((uint32_t)(0xCD0C))
+#define IMXDPUV1_TCON0_SPG10MASKOFF_OFFSET                   ((uint32_t)(0x10C))
+#define IMXDPUV1_TCON0_SPG10MASKOFF_RESET_VALUE              0U
+#define IMXDPUV1_TCON0_SPG10MASKOFF_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG10MASKOFF_SPGMKOFF10_MASK          0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG10MASKOFF_SPGMKOFF10_SHIFT         0U
+
+/* Register: IMXDPUV1_tcon0_SPG11PosOn */
+#define IMXDPUV1_TCON0_SPG11POSON                            ((uint32_t)(0xCD10))
+#define IMXDPUV1_TCON0_SPG11POSON_OFFSET                     ((uint32_t)(0x110))
+#define IMXDPUV1_TCON0_SPG11POSON_RESET_VALUE                0U
+#define IMXDPUV1_TCON0_SPG11POSON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_Y11_MASK           0x7FFFU
+#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_Y11_SHIFT          0U
+#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_FIELD11_MASK       0x8000U
+#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_FIELD11_SHIFT      15U
+#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_X11_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_X11_SHIFT          16U
+#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_TOGGLE11_MASK      0x80000000U
+#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_TOGGLE11_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon0_SPG11MaskOn */
+#define IMXDPUV1_TCON0_SPG11MASKON                           ((uint32_t)(0xCD14))
+#define IMXDPUV1_TCON0_SPG11MASKON_OFFSET                    ((uint32_t)(0x114))
+#define IMXDPUV1_TCON0_SPG11MASKON_RESET_VALUE               0U
+#define IMXDPUV1_TCON0_SPG11MASKON_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG11MASKON_SPGMKON11_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG11MASKON_SPGMKON11_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon0_SPG11PosOff */
+#define IMXDPUV1_TCON0_SPG11POSOFF                           ((uint32_t)(0xCD18))
+#define IMXDPUV1_TCON0_SPG11POSOFF_OFFSET                    ((uint32_t)(0x118))
+#define IMXDPUV1_TCON0_SPG11POSOFF_RESET_VALUE               0U
+#define IMXDPUV1_TCON0_SPG11POSOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_Y11_MASK         0x7FFFU
+#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_Y11_SHIFT        0U
+#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_FIELD11_MASK     0x8000U
+#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_FIELD11_SHIFT    15U
+#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_X11_MASK         0x7FFF0000U
+#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_X11_SHIFT        16U
+#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_TOGGLE11_MASK    0x80000000U
+#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_TOGGLE11_SHIFT   31U
+
+/* Register: IMXDPUV1_tcon0_SPG11MaskOff */
+#define IMXDPUV1_TCON0_SPG11MASKOFF                          ((uint32_t)(0xCD1C))
+#define IMXDPUV1_TCON0_SPG11MASKOFF_OFFSET                   ((uint32_t)(0x11C))
+#define IMXDPUV1_TCON0_SPG11MASKOFF_RESET_VALUE              0U
+#define IMXDPUV1_TCON0_SPG11MASKOFF_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SPG11MASKOFF_SPGMKOFF11_MASK          0x7FFFFFFFU
+#define IMXDPUV1_TCON0_SPG11MASKOFF_SPGMKOFF11_SHIFT         0U
+
+/* Register: IMXDPUV1_tcon0_SMx0Sigs */
+#define IMXDPUV1_TCON0_SMX0SIGS                              ((uint32_t)(0xCD20))
+#define IMXDPUV1_TCON0_SMX0SIGS_OFFSET                       ((uint32_t)(0x120))
+#define IMXDPUV1_TCON0_SMX0SIGS_RESET_VALUE                  0x2U
+#define IMXDPUV1_TCON0_SMX0SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon0_SMx0FctTable */
+#define IMXDPUV1_TCON0_SMX0FCTTABLE                          ((uint32_t)(0xCD24))
+#define IMXDPUV1_TCON0_SMX0FCTTABLE_OFFSET                   ((uint32_t)(0x124))
+#define IMXDPUV1_TCON0_SMX0FCTTABLE_RESET_VALUE              0x1U
+#define IMXDPUV1_TCON0_SMX0FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX0FCTTABLE_SMXFCT0_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX0FCTTABLE_SMXFCT0_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon0_SMx1Sigs */
+#define IMXDPUV1_TCON0_SMX1SIGS                              ((uint32_t)(0xCD28))
+#define IMXDPUV1_TCON0_SMX1SIGS_OFFSET                       ((uint32_t)(0x128))
+#define IMXDPUV1_TCON0_SMX1SIGS_RESET_VALUE                  0x3U
+#define IMXDPUV1_TCON0_SMX1SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon0_SMx1FctTable */
+#define IMXDPUV1_TCON0_SMX1FCTTABLE                          ((uint32_t)(0xCD2C))
+#define IMXDPUV1_TCON0_SMX1FCTTABLE_OFFSET                   ((uint32_t)(0x12C))
+#define IMXDPUV1_TCON0_SMX1FCTTABLE_RESET_VALUE              0x1U
+#define IMXDPUV1_TCON0_SMX1FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX1FCTTABLE_SMXFCT1_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX1FCTTABLE_SMXFCT1_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon0_SMx2Sigs */
+#define IMXDPUV1_TCON0_SMX2SIGS                              ((uint32_t)(0xCD30))
+#define IMXDPUV1_TCON0_SMX2SIGS_OFFSET                       ((uint32_t)(0x130))
+#define IMXDPUV1_TCON0_SMX2SIGS_RESET_VALUE                  0x2CU
+#define IMXDPUV1_TCON0_SMX2SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon0_SMx2FctTable */
+#define IMXDPUV1_TCON0_SMX2FCTTABLE                          ((uint32_t)(0xCD34))
+#define IMXDPUV1_TCON0_SMX2FCTTABLE_OFFSET                   ((uint32_t)(0x134))
+#define IMXDPUV1_TCON0_SMX2FCTTABLE_RESET_VALUE              0x8U
+#define IMXDPUV1_TCON0_SMX2FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX2FCTTABLE_SMXFCT2_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX2FCTTABLE_SMXFCT2_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon0_SMx3Sigs */
+#define IMXDPUV1_TCON0_SMX3SIGS                              ((uint32_t)(0xCD38))
+#define IMXDPUV1_TCON0_SMX3SIGS_OFFSET                       ((uint32_t)(0x138))
+#define IMXDPUV1_TCON0_SMX3SIGS_RESET_VALUE                  0U
+#define IMXDPUV1_TCON0_SMX3SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon0_SMx3FctTable */
+#define IMXDPUV1_TCON0_SMX3FCTTABLE                          ((uint32_t)(0xCD3C))
+#define IMXDPUV1_TCON0_SMX3FCTTABLE_OFFSET                   ((uint32_t)(0x13C))
+#define IMXDPUV1_TCON0_SMX3FCTTABLE_RESET_VALUE              0U
+#define IMXDPUV1_TCON0_SMX3FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX3FCTTABLE_SMXFCT3_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX3FCTTABLE_SMXFCT3_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon0_SMx4Sigs */
+#define IMXDPUV1_TCON0_SMX4SIGS                              ((uint32_t)(0xCD40))
+#define IMXDPUV1_TCON0_SMX4SIGS_OFFSET                       ((uint32_t)(0x140))
+#define IMXDPUV1_TCON0_SMX4SIGS_RESET_VALUE                  0U
+#define IMXDPUV1_TCON0_SMX4SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon0_SMx4FctTable */
+#define IMXDPUV1_TCON0_SMX4FCTTABLE                          ((uint32_t)(0xCD44))
+#define IMXDPUV1_TCON0_SMX4FCTTABLE_OFFSET                   ((uint32_t)(0x144))
+#define IMXDPUV1_TCON0_SMX4FCTTABLE_RESET_VALUE              0U
+#define IMXDPUV1_TCON0_SMX4FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX4FCTTABLE_SMXFCT4_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX4FCTTABLE_SMXFCT4_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon0_SMx5Sigs */
+#define IMXDPUV1_TCON0_SMX5SIGS                              ((uint32_t)(0xCD48))
+#define IMXDPUV1_TCON0_SMX5SIGS_OFFSET                       ((uint32_t)(0x148))
+#define IMXDPUV1_TCON0_SMX5SIGS_RESET_VALUE                  0U
+#define IMXDPUV1_TCON0_SMX5SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon0_SMx5FctTable */
+#define IMXDPUV1_TCON0_SMX5FCTTABLE                          ((uint32_t)(0xCD4C))
+#define IMXDPUV1_TCON0_SMX5FCTTABLE_OFFSET                   ((uint32_t)(0x14C))
+#define IMXDPUV1_TCON0_SMX5FCTTABLE_RESET_VALUE              0U
+#define IMXDPUV1_TCON0_SMX5FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX5FCTTABLE_SMXFCT5_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX5FCTTABLE_SMXFCT5_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon0_SMx6Sigs */
+#define IMXDPUV1_TCON0_SMX6SIGS                              ((uint32_t)(0xCD50))
+#define IMXDPUV1_TCON0_SMX6SIGS_OFFSET                       ((uint32_t)(0x150))
+#define IMXDPUV1_TCON0_SMX6SIGS_RESET_VALUE                  0U
+#define IMXDPUV1_TCON0_SMX6SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon0_SMx6FctTable */
+#define IMXDPUV1_TCON0_SMX6FCTTABLE                          ((uint32_t)(0xCD54))
+#define IMXDPUV1_TCON0_SMX6FCTTABLE_OFFSET                   ((uint32_t)(0x154))
+#define IMXDPUV1_TCON0_SMX6FCTTABLE_RESET_VALUE              0U
+#define IMXDPUV1_TCON0_SMX6FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX6FCTTABLE_SMXFCT6_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX6FCTTABLE_SMXFCT6_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon0_SMx7Sigs */
+#define IMXDPUV1_TCON0_SMX7SIGS                              ((uint32_t)(0xCD58))
+#define IMXDPUV1_TCON0_SMX7SIGS_OFFSET                       ((uint32_t)(0x158))
+#define IMXDPUV1_TCON0_SMX7SIGS_RESET_VALUE                  0U
+#define IMXDPUV1_TCON0_SMX7SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon0_SMx7FctTable */
+#define IMXDPUV1_TCON0_SMX7FCTTABLE                          ((uint32_t)(0xCD5C))
+#define IMXDPUV1_TCON0_SMX7FCTTABLE_OFFSET                   ((uint32_t)(0x15C))
+#define IMXDPUV1_TCON0_SMX7FCTTABLE_RESET_VALUE              0U
+#define IMXDPUV1_TCON0_SMX7FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX7FCTTABLE_SMXFCT7_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX7FCTTABLE_SMXFCT7_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon0_SMx8Sigs */
+#define IMXDPUV1_TCON0_SMX8SIGS                              ((uint32_t)(0xCD60))
+#define IMXDPUV1_TCON0_SMX8SIGS_OFFSET                       ((uint32_t)(0x160))
+#define IMXDPUV1_TCON0_SMX8SIGS_RESET_VALUE                  0U
+#define IMXDPUV1_TCON0_SMX8SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon0_SMx8FctTable */
+#define IMXDPUV1_TCON0_SMX8FCTTABLE                          ((uint32_t)(0xCD64))
+#define IMXDPUV1_TCON0_SMX8FCTTABLE_OFFSET                   ((uint32_t)(0x164))
+#define IMXDPUV1_TCON0_SMX8FCTTABLE_RESET_VALUE              0U
+#define IMXDPUV1_TCON0_SMX8FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX8FCTTABLE_SMXFCT8_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX8FCTTABLE_SMXFCT8_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon0_SMx9Sigs */
+#define IMXDPUV1_TCON0_SMX9SIGS                              ((uint32_t)(0xCD68))
+#define IMXDPUV1_TCON0_SMX9SIGS_OFFSET                       ((uint32_t)(0x168))
+#define IMXDPUV1_TCON0_SMX9SIGS_RESET_VALUE                  0U
+#define IMXDPUV1_TCON0_SMX9SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon0_SMx9FctTable */
+#define IMXDPUV1_TCON0_SMX9FCTTABLE                          ((uint32_t)(0xCD6C))
+#define IMXDPUV1_TCON0_SMX9FCTTABLE_OFFSET                   ((uint32_t)(0x16C))
+#define IMXDPUV1_TCON0_SMX9FCTTABLE_RESET_VALUE              0U
+#define IMXDPUV1_TCON0_SMX9FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX9FCTTABLE_SMXFCT9_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX9FCTTABLE_SMXFCT9_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon0_SMx10Sigs */
+#define IMXDPUV1_TCON0_SMX10SIGS                             ((uint32_t)(0xCD70))
+#define IMXDPUV1_TCON0_SMX10SIGS_OFFSET                      ((uint32_t)(0x170))
+#define IMXDPUV1_TCON0_SMX10SIGS_RESET_VALUE                 0U
+#define IMXDPUV1_TCON0_SMX10SIGS_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S0_MASK           0x7U
+#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S0_SHIFT          0U
+#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S1_MASK           0x38U
+#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S1_SHIFT          3U
+#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S2_MASK           0x1C0U
+#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S2_SHIFT          6U
+#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S3_MASK           0xE00U
+#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S3_SHIFT          9U
+#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S4_MASK           0x7000U
+#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S4_SHIFT          12U
+
+/* Register: IMXDPUV1_tcon0_SMx10FctTable */
+#define IMXDPUV1_TCON0_SMX10FCTTABLE                         ((uint32_t)(0xCD74))
+#define IMXDPUV1_TCON0_SMX10FCTTABLE_OFFSET                  ((uint32_t)(0x174))
+#define IMXDPUV1_TCON0_SMX10FCTTABLE_RESET_VALUE             0U
+#define IMXDPUV1_TCON0_SMX10FCTTABLE_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX10FCTTABLE_SMXFCT10_MASK           0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX10FCTTABLE_SMXFCT10_SHIFT          0U
+
+/* Register: IMXDPUV1_tcon0_SMx11Sigs */
+#define IMXDPUV1_TCON0_SMX11SIGS                             ((uint32_t)(0xCD78))
+#define IMXDPUV1_TCON0_SMX11SIGS_OFFSET                      ((uint32_t)(0x178))
+#define IMXDPUV1_TCON0_SMX11SIGS_RESET_VALUE                 0U
+#define IMXDPUV1_TCON0_SMX11SIGS_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S0_MASK           0x7U
+#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S0_SHIFT          0U
+#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S1_MASK           0x38U
+#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S1_SHIFT          3U
+#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S2_MASK           0x1C0U
+#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S2_SHIFT          6U
+#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S3_MASK           0xE00U
+#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S3_SHIFT          9U
+#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S4_MASK           0x7000U
+#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S4_SHIFT          12U
+
+/* Register: IMXDPUV1_tcon0_SMx11FctTable */
+#define IMXDPUV1_TCON0_SMX11FCTTABLE                         ((uint32_t)(0xCD7C))
+#define IMXDPUV1_TCON0_SMX11FCTTABLE_OFFSET                  ((uint32_t)(0x17C))
+#define IMXDPUV1_TCON0_SMX11FCTTABLE_RESET_VALUE             0U
+#define IMXDPUV1_TCON0_SMX11FCTTABLE_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX11FCTTABLE_SMXFCT11_MASK           0xFFFFFFFFU
+#define IMXDPUV1_TCON0_SMX11FCTTABLE_SMXFCT11_SHIFT          0U
+
+/* Register: IMXDPUV1_tcon0_Reset_Over_Unferflow */
+#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW                  ((uint32_t)(0xCD80))
+#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_OFFSET           ((uint32_t)(0x180))
+#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_RESET_VALUE      0U
+#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_RESET_STATUS_MASK 0x1U
+#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_RESET_STATUS_SHIFT 0U
+
+/* Register: IMXDPUV1_tcon0_Dual_Debug */
+#define IMXDPUV1_TCON0_DUAL_DEBUG                            ((uint32_t)(0xCD84))
+#define IMXDPUV1_TCON0_DUAL_DEBUG_OFFSET                     ((uint32_t)(0x184))
+#define IMXDPUV1_TCON0_DUAL_DEBUG_RESET_VALUE                0U
+#define IMXDPUV1_TCON0_DUAL_DEBUG_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON0_DUAL_DEBUG_LOWER_FIFO_OVERFLOW_MASK   0x1U
+#define IMXDPUV1_TCON0_DUAL_DEBUG_LOWER_FIFO_OVERFLOW_SHIFT  0U
+#define IMXDPUV1_TCON0_DUAL_DEBUG_LOWER_FIFO_UNDERFLOW_MASK  0x2U
+#define IMXDPUV1_TCON0_DUAL_DEBUG_LOWER_FIFO_UNDERFLOW_SHIFT 1U
+#define IMXDPUV1_TCON0_DUAL_DEBUG_UPPER_FIFO_OVERFLOW_MASK   0x10U
+#define IMXDPUV1_TCON0_DUAL_DEBUG_UPPER_FIFO_OVERFLOW_SHIFT  4U
+#define IMXDPUV1_TCON0_DUAL_DEBUG_UPPER_FIFO_UNDERFLOW_MASK  0x20U
+#define IMXDPUV1_TCON0_DUAL_DEBUG_UPPER_FIFO_UNDERFLOW_SHIFT 5U
+
+/* Register: IMXDPUV1_sig0_LockUnlock */
+#define IMXDPUV1_SIG0_LOCKUNLOCK                             ((uint32_t)(0xD000))
+#define IMXDPUV1_SIG0_LOCKUNLOCK_OFFSET                      ((uint32_t)(0))
+#define IMXDPUV1_SIG0_LOCKUNLOCK_RESET_VALUE                 0U
+#define IMXDPUV1_SIG0_LOCKUNLOCK_RESET_MASK                  0U
+#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK_SHIFT            0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY        0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY      0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY   0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY      0xFBE8B1E6U
+
+/* Register: IMXDPUV1_sig0_LockStatus */
+#define IMXDPUV1_SIG0_LOCKSTATUS                             ((uint32_t)(0xD004))
+#define IMXDPUV1_SIG0_LOCKSTATUS_OFFSET                      ((uint32_t)(0x4))
+#define IMXDPUV1_SIG0_LOCKSTATUS_RESET_VALUE                 0U
+#define IMXDPUV1_SIG0_LOCKSTATUS_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG0_LOCKSTATUS_LOCKSTATUS_MASK             0x1U
+#define IMXDPUV1_SIG0_LOCKSTATUS_LOCKSTATUS_SHIFT            0U
+#define IMXDPUV1_SIG0_LOCKSTATUS_PRIVILEGESTATUS_MASK        0x10U
+#define IMXDPUV1_SIG0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT       4U
+#define IMXDPUV1_SIG0_LOCKSTATUS_FREEZESTATUS_MASK           0x100U
+#define IMXDPUV1_SIG0_LOCKSTATUS_FREEZESTATUS_SHIFT          8U
+
+/* Register: IMXDPUV1_sig0_StaticControl */
+#define IMXDPUV1_SIG0_STATICCONTROL                          ((uint32_t)(0xD008))
+#define IMXDPUV1_SIG0_STATICCONTROL_OFFSET                   ((uint32_t)(0x8))
+#define IMXDPUV1_SIG0_STATICCONTROL_RESET_VALUE              0x8000000U
+#define IMXDPUV1_SIG0_STATICCONTROL_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_SIG0_STATICCONTROL_SHDEN_MASK               0x1U
+#define IMXDPUV1_SIG0_STATICCONTROL_SHDEN_SHIFT              0U
+#define IMXDPUV1_SIG0_STATICCONTROL_SHDLDSEL_MASK            0x10U
+#define IMXDPUV1_SIG0_STATICCONTROL_SHDLDSEL_SHIFT           4U
+/* Field Value: SHDLDSEL__LOCAL, Shadows are loaded at start of frame for
+ * each evaluation window for which ShdLdReq has been set.  */
+#define IMXDPUV1_SIG0_STATICCONTROL_SHDLDSEL__LOCAL          0U
+/* Field Value: SHDLDSEL__GLOBAL, Shadows of all evaluation windows are loaded
+ * synchronous to the display stream (shadow load token received on
+ * frame input port).  */
+#define IMXDPUV1_SIG0_STATICCONTROL_SHDLDSEL__GLOBAL         0x1U
+#define IMXDPUV1_SIG0_STATICCONTROL_ERRTHRES_MASK            0xFF0000U
+#define IMXDPUV1_SIG0_STATICCONTROL_ERRTHRES_SHIFT           16U
+#define IMXDPUV1_SIG0_STATICCONTROL_ERRTHRESRESET_MASK       0xFF000000U
+#define IMXDPUV1_SIG0_STATICCONTROL_ERRTHRESRESET_SHIFT      24U
+
+/* Register: IMXDPUV1_sig0_PanicColor */
+#define IMXDPUV1_SIG0_PANICCOLOR                             ((uint32_t)(0xD00C))
+#define IMXDPUV1_SIG0_PANICCOLOR_OFFSET                      ((uint32_t)(0xC))
+#define IMXDPUV1_SIG0_PANICCOLOR_RESET_VALUE                 0U
+#define IMXDPUV1_SIG0_PANICCOLOR_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG0_PANICCOLOR_PANICALPHA_MASK             0x80U
+#define IMXDPUV1_SIG0_PANICCOLOR_PANICALPHA_SHIFT            7U
+#define IMXDPUV1_SIG0_PANICCOLOR_PANICBLUE_MASK              0xFF00U
+#define IMXDPUV1_SIG0_PANICCOLOR_PANICBLUE_SHIFT             8U
+#define IMXDPUV1_SIG0_PANICCOLOR_PANICGREEN_MASK             0xFF0000U
+#define IMXDPUV1_SIG0_PANICCOLOR_PANICGREEN_SHIFT            16U
+#define IMXDPUV1_SIG0_PANICCOLOR_PANICRED_MASK               0xFF000000U
+#define IMXDPUV1_SIG0_PANICCOLOR_PANICRED_SHIFT              24U
+
+/* Register: IMXDPUV1_sig0_EvalControl0 */
+#define IMXDPUV1_SIG0_EVALCONTROL0                           ((uint32_t)(0xD010))
+#define IMXDPUV1_SIG0_EVALCONTROL0_OFFSET                    ((uint32_t)(0x10))
+#define IMXDPUV1_SIG0_EVALCONTROL0_RESET_VALUE               0U
+#define IMXDPUV1_SIG0_EVALCONTROL0_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALCONTROL0_ENEVALWIN0_MASK           0x1U
+#define IMXDPUV1_SIG0_EVALCONTROL0_ENEVALWIN0_SHIFT          0U
+#define IMXDPUV1_SIG0_EVALCONTROL0_ENCRC0_MASK               0x2U
+#define IMXDPUV1_SIG0_EVALCONTROL0_ENCRC0_SHIFT              1U
+#define IMXDPUV1_SIG0_EVALCONTROL0_ALPHAMASK0_MASK           0x100U
+#define IMXDPUV1_SIG0_EVALCONTROL0_ALPHAMASK0_SHIFT          8U
+#define IMXDPUV1_SIG0_EVALCONTROL0_ALPHAINV0_MASK            0x200U
+#define IMXDPUV1_SIG0_EVALCONTROL0_ALPHAINV0_SHIFT           9U
+#define IMXDPUV1_SIG0_EVALCONTROL0_ENLOCALPANIC0_MASK        0x10000U
+#define IMXDPUV1_SIG0_EVALCONTROL0_ENLOCALPANIC0_SHIFT       16U
+#define IMXDPUV1_SIG0_EVALCONTROL0_ENGLOBALPANIC0_MASK       0x20000U
+#define IMXDPUV1_SIG0_EVALCONTROL0_ENGLOBALPANIC0_SHIFT      17U
+
+/* Register: IMXDPUV1_sig0_EvalUpperLeft0 */
+#define IMXDPUV1_SIG0_EVALUPPERLEFT0                         ((uint32_t)(0xD014))
+#define IMXDPUV1_SIG0_EVALUPPERLEFT0_OFFSET                  ((uint32_t)(0x14))
+#define IMXDPUV1_SIG0_EVALUPPERLEFT0_RESET_VALUE             0U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT0_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALUPPERLEFT0_XEVALUPPERLEFT0_MASK    0x3FFFU
+#define IMXDPUV1_SIG0_EVALUPPERLEFT0_XEVALUPPERLEFT0_SHIFT   0U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT0_YEVALUPPERLEFT0_MASK    0x3FFF0000U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT0_YEVALUPPERLEFT0_SHIFT   16U
+
+/* Register: IMXDPUV1_sig0_EvalLowerRight0 */
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT0                        ((uint32_t)(0xD018))
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_OFFSET                 ((uint32_t)(0x18))
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_RESET_VALUE            0U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_XEVALLOWERRIGHT0_MASK  0x3FFFU
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_XEVALLOWERRIGHT0_SHIFT 0U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_YEVALLOWERRIGHT0_MASK  0x3FFF0000U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_YEVALLOWERRIGHT0_SHIFT 16U
+
+/* Register: IMXDPUV1_sig0_SigCRCRedRef0 */
+#define IMXDPUV1_SIG0_SIGCRCREDREF0                          ((uint32_t)(0xD01C))
+#define IMXDPUV1_SIG0_SIGCRCREDREF0_OFFSET                   ((uint32_t)(0x1C))
+#define IMXDPUV1_SIG0_SIGCRCREDREF0_RESET_VALUE              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF0_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF0_SIGCRCREDREF0_MASK       0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF0_SIGCRCREDREF0_SHIFT      0U
+
+/* Register: IMXDPUV1_sig0_SigCRCGreenRef0 */
+#define IMXDPUV1_SIG0_SIGCRCGREENREF0                        ((uint32_t)(0xD020))
+#define IMXDPUV1_SIG0_SIGCRCGREENREF0_OFFSET                 ((uint32_t)(0x20))
+#define IMXDPUV1_SIG0_SIGCRCGREENREF0_RESET_VALUE            0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF0_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF0_SIGCRCGREENREF0_MASK   0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF0_SIGCRCGREENREF0_SHIFT  0U
+
+/* Register: IMXDPUV1_sig0_SigCRCBlueRef0 */
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF0                         ((uint32_t)(0xD024))
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_OFFSET                  ((uint32_t)(0x24))
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_RESET_VALUE             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_SIGCRCBLUEREF0_MASK     0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_SIGCRCBLUEREF0_SHIFT    0U
+
+/* Register: IMXDPUV1_sig0_SigCRCRed0 */
+#define IMXDPUV1_SIG0_SIGCRCRED0                             ((uint32_t)(0xD028))
+#define IMXDPUV1_SIG0_SIGCRCRED0_OFFSET                      ((uint32_t)(0x28))
+#define IMXDPUV1_SIG0_SIGCRCRED0_RESET_VALUE                 0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED0_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED0_SIGCRCRED0_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED0_SIGCRCRED0_SHIFT            0U
+
+/* Register: IMXDPUV1_sig0_SigCRCGreen0 */
+#define IMXDPUV1_SIG0_SIGCRCGREEN0                           ((uint32_t)(0xD02C))
+#define IMXDPUV1_SIG0_SIGCRCGREEN0_OFFSET                    ((uint32_t)(0x2C))
+#define IMXDPUV1_SIG0_SIGCRCGREEN0_RESET_VALUE               0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN0_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN0_SIGCRCGREEN0_MASK         0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN0_SIGCRCGREEN0_SHIFT        0U
+
+/* Register: IMXDPUV1_sig0_SigCRCBlue0 */
+#define IMXDPUV1_SIG0_SIGCRCBLUE0                            ((uint32_t)(0xD030))
+#define IMXDPUV1_SIG0_SIGCRCBLUE0_OFFSET                     ((uint32_t)(0x30))
+#define IMXDPUV1_SIG0_SIGCRCBLUE0_RESET_VALUE                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE0_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE0_SIGCRCBLUE0_MASK           0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE0_SIGCRCBLUE0_SHIFT          0U
+
+/* Register: IMXDPUV1_sig0_EvalControl1 */
+#define IMXDPUV1_SIG0_EVALCONTROL1                           ((uint32_t)(0xD034))
+#define IMXDPUV1_SIG0_EVALCONTROL1_OFFSET                    ((uint32_t)(0x34))
+#define IMXDPUV1_SIG0_EVALCONTROL1_RESET_VALUE               0U
+#define IMXDPUV1_SIG0_EVALCONTROL1_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALCONTROL1_ENEVALWIN1_MASK           0x1U
+#define IMXDPUV1_SIG0_EVALCONTROL1_ENEVALWIN1_SHIFT          0U
+#define IMXDPUV1_SIG0_EVALCONTROL1_ENCRC1_MASK               0x2U
+#define IMXDPUV1_SIG0_EVALCONTROL1_ENCRC1_SHIFT              1U
+#define IMXDPUV1_SIG0_EVALCONTROL1_ALPHAMASK1_MASK           0x100U
+#define IMXDPUV1_SIG0_EVALCONTROL1_ALPHAMASK1_SHIFT          8U
+#define IMXDPUV1_SIG0_EVALCONTROL1_ALPHAINV1_MASK            0x200U
+#define IMXDPUV1_SIG0_EVALCONTROL1_ALPHAINV1_SHIFT           9U
+#define IMXDPUV1_SIG0_EVALCONTROL1_ENLOCALPANIC1_MASK        0x10000U
+#define IMXDPUV1_SIG0_EVALCONTROL1_ENLOCALPANIC1_SHIFT       16U
+#define IMXDPUV1_SIG0_EVALCONTROL1_ENGLOBALPANIC1_MASK       0x20000U
+#define IMXDPUV1_SIG0_EVALCONTROL1_ENGLOBALPANIC1_SHIFT      17U
+
+/* Register: IMXDPUV1_sig0_EvalUpperLeft1 */
+#define IMXDPUV1_SIG0_EVALUPPERLEFT1                         ((uint32_t)(0xD038))
+#define IMXDPUV1_SIG0_EVALUPPERLEFT1_OFFSET                  ((uint32_t)(0x38))
+#define IMXDPUV1_SIG0_EVALUPPERLEFT1_RESET_VALUE             0U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT1_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALUPPERLEFT1_XEVALUPPERLEFT1_MASK    0x3FFFU
+#define IMXDPUV1_SIG0_EVALUPPERLEFT1_XEVALUPPERLEFT1_SHIFT   0U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT1_YEVALUPPERLEFT1_MASK    0x3FFF0000U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT1_YEVALUPPERLEFT1_SHIFT   16U
+
+/* Register: IMXDPUV1_sig0_EvalLowerRight1 */
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT1                        ((uint32_t)(0xD03C))
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_OFFSET                 ((uint32_t)(0x3C))
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_RESET_VALUE            0U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_XEVALLOWERRIGHT1_MASK  0x3FFFU
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_XEVALLOWERRIGHT1_SHIFT 0U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_YEVALLOWERRIGHT1_MASK  0x3FFF0000U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_YEVALLOWERRIGHT1_SHIFT 16U
+
+/* Register: IMXDPUV1_sig0_SigCRCRedRef1 */
+#define IMXDPUV1_SIG0_SIGCRCREDREF1                          ((uint32_t)(0xD040))
+#define IMXDPUV1_SIG0_SIGCRCREDREF1_OFFSET                   ((uint32_t)(0x40))
+#define IMXDPUV1_SIG0_SIGCRCREDREF1_RESET_VALUE              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF1_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF1_SIGCRCREDREF1_MASK       0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF1_SIGCRCREDREF1_SHIFT      0U
+
+/* Register: IMXDPUV1_sig0_SigCRCGreenRef1 */
+#define IMXDPUV1_SIG0_SIGCRCGREENREF1                        ((uint32_t)(0xD044))
+#define IMXDPUV1_SIG0_SIGCRCGREENREF1_OFFSET                 ((uint32_t)(0x44))
+#define IMXDPUV1_SIG0_SIGCRCGREENREF1_RESET_VALUE            0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF1_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF1_SIGCRCGREENREF1_MASK   0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF1_SIGCRCGREENREF1_SHIFT  0U
+
+/* Register: IMXDPUV1_sig0_SigCRCBlueRef1 */
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF1                         ((uint32_t)(0xD048))
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_OFFSET                  ((uint32_t)(0x48))
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_RESET_VALUE             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_SIGCRCBLUEREF1_MASK     0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_SIGCRCBLUEREF1_SHIFT    0U
+
+/* Register: IMXDPUV1_sig0_SigCRCRed1 */
+#define IMXDPUV1_SIG0_SIGCRCRED1                             ((uint32_t)(0xD04C))
+#define IMXDPUV1_SIG0_SIGCRCRED1_OFFSET                      ((uint32_t)(0x4C))
+#define IMXDPUV1_SIG0_SIGCRCRED1_RESET_VALUE                 0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED1_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED1_SIGCRCRED1_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED1_SIGCRCRED1_SHIFT            0U
+
+/* Register: IMXDPUV1_sig0_SigCRCGreen1 */
+#define IMXDPUV1_SIG0_SIGCRCGREEN1                           ((uint32_t)(0xD050))
+#define IMXDPUV1_SIG0_SIGCRCGREEN1_OFFSET                    ((uint32_t)(0x50))
+#define IMXDPUV1_SIG0_SIGCRCGREEN1_RESET_VALUE               0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN1_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN1_SIGCRCGREEN1_MASK         0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN1_SIGCRCGREEN1_SHIFT        0U
+
+/* Register: IMXDPUV1_sig0_SigCRCBlue1 */
+#define IMXDPUV1_SIG0_SIGCRCBLUE1                            ((uint32_t)(0xD054))
+#define IMXDPUV1_SIG0_SIGCRCBLUE1_OFFSET                     ((uint32_t)(0x54))
+#define IMXDPUV1_SIG0_SIGCRCBLUE1_RESET_VALUE                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE1_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE1_SIGCRCBLUE1_MASK           0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE1_SIGCRCBLUE1_SHIFT          0U
+
+/* Register: IMXDPUV1_sig0_EvalControl2 */
+#define IMXDPUV1_SIG0_EVALCONTROL2                           ((uint32_t)(0xD058))
+#define IMXDPUV1_SIG0_EVALCONTROL2_OFFSET                    ((uint32_t)(0x58))
+#define IMXDPUV1_SIG0_EVALCONTROL2_RESET_VALUE               0U
+#define IMXDPUV1_SIG0_EVALCONTROL2_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALCONTROL2_ENEVALWIN2_MASK           0x1U
+#define IMXDPUV1_SIG0_EVALCONTROL2_ENEVALWIN2_SHIFT          0U
+#define IMXDPUV1_SIG0_EVALCONTROL2_ENCRC2_MASK               0x2U
+#define IMXDPUV1_SIG0_EVALCONTROL2_ENCRC2_SHIFT              1U
+#define IMXDPUV1_SIG0_EVALCONTROL2_ALPHAMASK2_MASK           0x100U
+#define IMXDPUV1_SIG0_EVALCONTROL2_ALPHAMASK2_SHIFT          8U
+#define IMXDPUV1_SIG0_EVALCONTROL2_ALPHAINV2_MASK            0x200U
+#define IMXDPUV1_SIG0_EVALCONTROL2_ALPHAINV2_SHIFT           9U
+#define IMXDPUV1_SIG0_EVALCONTROL2_ENLOCALPANIC2_MASK        0x10000U
+#define IMXDPUV1_SIG0_EVALCONTROL2_ENLOCALPANIC2_SHIFT       16U
+#define IMXDPUV1_SIG0_EVALCONTROL2_ENGLOBALPANIC2_MASK       0x20000U
+#define IMXDPUV1_SIG0_EVALCONTROL2_ENGLOBALPANIC2_SHIFT      17U
+
+/* Register: IMXDPUV1_sig0_EvalUpperLeft2 */
+#define IMXDPUV1_SIG0_EVALUPPERLEFT2                         ((uint32_t)(0xD05C))
+#define IMXDPUV1_SIG0_EVALUPPERLEFT2_OFFSET                  ((uint32_t)(0x5C))
+#define IMXDPUV1_SIG0_EVALUPPERLEFT2_RESET_VALUE             0U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT2_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALUPPERLEFT2_XEVALUPPERLEFT2_MASK    0x3FFFU
+#define IMXDPUV1_SIG0_EVALUPPERLEFT2_XEVALUPPERLEFT2_SHIFT   0U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT2_YEVALUPPERLEFT2_MASK    0x3FFF0000U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT2_YEVALUPPERLEFT2_SHIFT   16U
+
+/* Register: IMXDPUV1_sig0_EvalLowerRight2 */
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT2                        ((uint32_t)(0xD060))
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_OFFSET                 ((uint32_t)(0x60))
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_RESET_VALUE            0U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_XEVALLOWERRIGHT2_MASK  0x3FFFU
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_XEVALLOWERRIGHT2_SHIFT 0U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_YEVALLOWERRIGHT2_MASK  0x3FFF0000U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_YEVALLOWERRIGHT2_SHIFT 16U
+
+/* Register: IMXDPUV1_sig0_SigCRCRedRef2 */
+#define IMXDPUV1_SIG0_SIGCRCREDREF2                          ((uint32_t)(0xD064))
+#define IMXDPUV1_SIG0_SIGCRCREDREF2_OFFSET                   ((uint32_t)(0x64))
+#define IMXDPUV1_SIG0_SIGCRCREDREF2_RESET_VALUE              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF2_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF2_SIGCRCREDREF2_MASK       0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF2_SIGCRCREDREF2_SHIFT      0U
+
+/* Register: IMXDPUV1_sig0_SigCRCGreenRef2 */
+#define IMXDPUV1_SIG0_SIGCRCGREENREF2                        ((uint32_t)(0xD068))
+#define IMXDPUV1_SIG0_SIGCRCGREENREF2_OFFSET                 ((uint32_t)(0x68))
+#define IMXDPUV1_SIG0_SIGCRCGREENREF2_RESET_VALUE            0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF2_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF2_SIGCRCGREENREF2_MASK   0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF2_SIGCRCGREENREF2_SHIFT  0U
+
+/* Register: IMXDPUV1_sig0_SigCRCBlueRef2 */
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF2                         ((uint32_t)(0xD06C))
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_OFFSET                  ((uint32_t)(0x6C))
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_RESET_VALUE             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_SIGCRCBLUEREF2_MASK     0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_SIGCRCBLUEREF2_SHIFT    0U
+
+/* Register: IMXDPUV1_sig0_SigCRCRed2 */
+#define IMXDPUV1_SIG0_SIGCRCRED2                             ((uint32_t)(0xD070))
+#define IMXDPUV1_SIG0_SIGCRCRED2_OFFSET                      ((uint32_t)(0x70))
+#define IMXDPUV1_SIG0_SIGCRCRED2_RESET_VALUE                 0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED2_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED2_SIGCRCRED2_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED2_SIGCRCRED2_SHIFT            0U
+
+/* Register: IMXDPUV1_sig0_SigCRCGreen2 */
+#define IMXDPUV1_SIG0_SIGCRCGREEN2                           ((uint32_t)(0xD074))
+#define IMXDPUV1_SIG0_SIGCRCGREEN2_OFFSET                    ((uint32_t)(0x74))
+#define IMXDPUV1_SIG0_SIGCRCGREEN2_RESET_VALUE               0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN2_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN2_SIGCRCGREEN2_MASK         0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN2_SIGCRCGREEN2_SHIFT        0U
+
+/* Register: IMXDPUV1_sig0_SigCRCBlue2 */
+#define IMXDPUV1_SIG0_SIGCRCBLUE2                            ((uint32_t)(0xD078))
+#define IMXDPUV1_SIG0_SIGCRCBLUE2_OFFSET                     ((uint32_t)(0x78))
+#define IMXDPUV1_SIG0_SIGCRCBLUE2_RESET_VALUE                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE2_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE2_SIGCRCBLUE2_MASK           0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE2_SIGCRCBLUE2_SHIFT          0U
+
+/* Register: IMXDPUV1_sig0_EvalControl3 */
+#define IMXDPUV1_SIG0_EVALCONTROL3                           ((uint32_t)(0xD07C))
+#define IMXDPUV1_SIG0_EVALCONTROL3_OFFSET                    ((uint32_t)(0x7C))
+#define IMXDPUV1_SIG0_EVALCONTROL3_RESET_VALUE               0U
+#define IMXDPUV1_SIG0_EVALCONTROL3_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALCONTROL3_ENEVALWIN3_MASK           0x1U
+#define IMXDPUV1_SIG0_EVALCONTROL3_ENEVALWIN3_SHIFT          0U
+#define IMXDPUV1_SIG0_EVALCONTROL3_ENCRC3_MASK               0x2U
+#define IMXDPUV1_SIG0_EVALCONTROL3_ENCRC3_SHIFT              1U
+#define IMXDPUV1_SIG0_EVALCONTROL3_ALPHAMASK3_MASK           0x100U
+#define IMXDPUV1_SIG0_EVALCONTROL3_ALPHAMASK3_SHIFT          8U
+#define IMXDPUV1_SIG0_EVALCONTROL3_ALPHAINV3_MASK            0x200U
+#define IMXDPUV1_SIG0_EVALCONTROL3_ALPHAINV3_SHIFT           9U
+#define IMXDPUV1_SIG0_EVALCONTROL3_ENLOCALPANIC3_MASK        0x10000U
+#define IMXDPUV1_SIG0_EVALCONTROL3_ENLOCALPANIC3_SHIFT       16U
+#define IMXDPUV1_SIG0_EVALCONTROL3_ENGLOBALPANIC3_MASK       0x20000U
+#define IMXDPUV1_SIG0_EVALCONTROL3_ENGLOBALPANIC3_SHIFT      17U
+
+/* Register: IMXDPUV1_sig0_EvalUpperLeft3 */
+#define IMXDPUV1_SIG0_EVALUPPERLEFT3                         ((uint32_t)(0xD080))
+#define IMXDPUV1_SIG0_EVALUPPERLEFT3_OFFSET                  ((uint32_t)(0x80))
+#define IMXDPUV1_SIG0_EVALUPPERLEFT3_RESET_VALUE             0U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT3_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALUPPERLEFT3_XEVALUPPERLEFT3_MASK    0x3FFFU
+#define IMXDPUV1_SIG0_EVALUPPERLEFT3_XEVALUPPERLEFT3_SHIFT   0U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT3_YEVALUPPERLEFT3_MASK    0x3FFF0000U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT3_YEVALUPPERLEFT3_SHIFT   16U
+
+/* Register: IMXDPUV1_sig0_EvalLowerRight3 */
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT3                        ((uint32_t)(0xD084))
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_OFFSET                 ((uint32_t)(0x84))
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_RESET_VALUE            0U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_XEVALLOWERRIGHT3_MASK  0x3FFFU
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_XEVALLOWERRIGHT3_SHIFT 0U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_YEVALLOWERRIGHT3_MASK  0x3FFF0000U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_YEVALLOWERRIGHT3_SHIFT 16U
+
+/* Register: IMXDPUV1_sig0_SigCRCRedRef3 */
+#define IMXDPUV1_SIG0_SIGCRCREDREF3                          ((uint32_t)(0xD088))
+#define IMXDPUV1_SIG0_SIGCRCREDREF3_OFFSET                   ((uint32_t)(0x88))
+#define IMXDPUV1_SIG0_SIGCRCREDREF3_RESET_VALUE              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF3_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF3_SIGCRCREDREF3_MASK       0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF3_SIGCRCREDREF3_SHIFT      0U
+
+/* Register: IMXDPUV1_sig0_SigCRCGreenRef3 */
+#define IMXDPUV1_SIG0_SIGCRCGREENREF3                        ((uint32_t)(0xD08C))
+#define IMXDPUV1_SIG0_SIGCRCGREENREF3_OFFSET                 ((uint32_t)(0x8C))
+#define IMXDPUV1_SIG0_SIGCRCGREENREF3_RESET_VALUE            0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF3_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF3_SIGCRCGREENREF3_MASK   0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF3_SIGCRCGREENREF3_SHIFT  0U
+
+/* Register: IMXDPUV1_sig0_SigCRCBlueRef3 */
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF3                         ((uint32_t)(0xD090))
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_OFFSET                  ((uint32_t)(0x90))
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_RESET_VALUE             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_SIGCRCBLUEREF3_MASK     0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_SIGCRCBLUEREF3_SHIFT    0U
+
+/* Register: IMXDPUV1_sig0_SigCRCRed3 */
+#define IMXDPUV1_SIG0_SIGCRCRED3                             ((uint32_t)(0xD094))
+#define IMXDPUV1_SIG0_SIGCRCRED3_OFFSET                      ((uint32_t)(0x94))
+#define IMXDPUV1_SIG0_SIGCRCRED3_RESET_VALUE                 0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED3_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED3_SIGCRCRED3_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED3_SIGCRCRED3_SHIFT            0U
+
+/* Register: IMXDPUV1_sig0_SigCRCGreen3 */
+#define IMXDPUV1_SIG0_SIGCRCGREEN3                           ((uint32_t)(0xD098))
+#define IMXDPUV1_SIG0_SIGCRCGREEN3_OFFSET                    ((uint32_t)(0x98))
+#define IMXDPUV1_SIG0_SIGCRCGREEN3_RESET_VALUE               0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN3_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN3_SIGCRCGREEN3_MASK         0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN3_SIGCRCGREEN3_SHIFT        0U
+
+/* Register: IMXDPUV1_sig0_SigCRCBlue3 */
+#define IMXDPUV1_SIG0_SIGCRCBLUE3                            ((uint32_t)(0xD09C))
+#define IMXDPUV1_SIG0_SIGCRCBLUE3_OFFSET                     ((uint32_t)(0x9C))
+#define IMXDPUV1_SIG0_SIGCRCBLUE3_RESET_VALUE                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE3_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE3_SIGCRCBLUE3_MASK           0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE3_SIGCRCBLUE3_SHIFT          0U
+
+/* Register: IMXDPUV1_sig0_EvalControl4 */
+#define IMXDPUV1_SIG0_EVALCONTROL4                           ((uint32_t)(0xD0A0))
+#define IMXDPUV1_SIG0_EVALCONTROL4_OFFSET                    ((uint32_t)(0xA0))
+#define IMXDPUV1_SIG0_EVALCONTROL4_RESET_VALUE               0U
+#define IMXDPUV1_SIG0_EVALCONTROL4_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALCONTROL4_ENEVALWIN4_MASK           0x1U
+#define IMXDPUV1_SIG0_EVALCONTROL4_ENEVALWIN4_SHIFT          0U
+#define IMXDPUV1_SIG0_EVALCONTROL4_ENCRC4_MASK               0x2U
+#define IMXDPUV1_SIG0_EVALCONTROL4_ENCRC4_SHIFT              1U
+#define IMXDPUV1_SIG0_EVALCONTROL4_ALPHAMASK4_MASK           0x100U
+#define IMXDPUV1_SIG0_EVALCONTROL4_ALPHAMASK4_SHIFT          8U
+#define IMXDPUV1_SIG0_EVALCONTROL4_ALPHAINV4_MASK            0x200U
+#define IMXDPUV1_SIG0_EVALCONTROL4_ALPHAINV4_SHIFT           9U
+#define IMXDPUV1_SIG0_EVALCONTROL4_ENLOCALPANIC4_MASK        0x10000U
+#define IMXDPUV1_SIG0_EVALCONTROL4_ENLOCALPANIC4_SHIFT       16U
+#define IMXDPUV1_SIG0_EVALCONTROL4_ENGLOBALPANIC4_MASK       0x20000U
+#define IMXDPUV1_SIG0_EVALCONTROL4_ENGLOBALPANIC4_SHIFT      17U
+
+/* Register: IMXDPUV1_sig0_EvalUpperLeft4 */
+#define IMXDPUV1_SIG0_EVALUPPERLEFT4                         ((uint32_t)(0xD0A4))
+#define IMXDPUV1_SIG0_EVALUPPERLEFT4_OFFSET                  ((uint32_t)(0xA4))
+#define IMXDPUV1_SIG0_EVALUPPERLEFT4_RESET_VALUE             0U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT4_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALUPPERLEFT4_XEVALUPPERLEFT4_MASK    0x3FFFU
+#define IMXDPUV1_SIG0_EVALUPPERLEFT4_XEVALUPPERLEFT4_SHIFT   0U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT4_YEVALUPPERLEFT4_MASK    0x3FFF0000U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT4_YEVALUPPERLEFT4_SHIFT   16U
+
+/* Register: IMXDPUV1_sig0_EvalLowerRight4 */
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT4                        ((uint32_t)(0xD0A8))
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_OFFSET                 ((uint32_t)(0xA8))
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_RESET_VALUE            0U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_XEVALLOWERRIGHT4_MASK  0x3FFFU
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_XEVALLOWERRIGHT4_SHIFT 0U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_YEVALLOWERRIGHT4_MASK  0x3FFF0000U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_YEVALLOWERRIGHT4_SHIFT 16U
+
+/* Register: IMXDPUV1_sig0_SigCRCRedRef4 */
+#define IMXDPUV1_SIG0_SIGCRCREDREF4                          ((uint32_t)(0xD0AC))
+#define IMXDPUV1_SIG0_SIGCRCREDREF4_OFFSET                   ((uint32_t)(0xAC))
+#define IMXDPUV1_SIG0_SIGCRCREDREF4_RESET_VALUE              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF4_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF4_SIGCRCREDREF4_MASK       0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF4_SIGCRCREDREF4_SHIFT      0U
+
+/* Register: IMXDPUV1_sig0_SigCRCGreenRef4 */
+#define IMXDPUV1_SIG0_SIGCRCGREENREF4                        ((uint32_t)(0xD0B0))
+#define IMXDPUV1_SIG0_SIGCRCGREENREF4_OFFSET                 ((uint32_t)(0xB0))
+#define IMXDPUV1_SIG0_SIGCRCGREENREF4_RESET_VALUE            0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF4_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF4_SIGCRCGREENREF4_MASK   0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF4_SIGCRCGREENREF4_SHIFT  0U
+
+/* Register: IMXDPUV1_sig0_SigCRCBlueRef4 */
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF4                         ((uint32_t)(0xD0B4))
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_OFFSET                  ((uint32_t)(0xB4))
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_RESET_VALUE             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_SIGCRCBLUEREF4_MASK     0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_SIGCRCBLUEREF4_SHIFT    0U
+
+/* Register: IMXDPUV1_sig0_SigCRCRed4 */
+#define IMXDPUV1_SIG0_SIGCRCRED4                             ((uint32_t)(0xD0B8))
+#define IMXDPUV1_SIG0_SIGCRCRED4_OFFSET                      ((uint32_t)(0xB8))
+#define IMXDPUV1_SIG0_SIGCRCRED4_RESET_VALUE                 0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED4_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED4_SIGCRCRED4_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED4_SIGCRCRED4_SHIFT            0U
+
+/* Register: IMXDPUV1_sig0_SigCRCGreen4 */
+#define IMXDPUV1_SIG0_SIGCRCGREEN4                           ((uint32_t)(0xD0BC))
+#define IMXDPUV1_SIG0_SIGCRCGREEN4_OFFSET                    ((uint32_t)(0xBC))
+#define IMXDPUV1_SIG0_SIGCRCGREEN4_RESET_VALUE               0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN4_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN4_SIGCRCGREEN4_MASK         0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN4_SIGCRCGREEN4_SHIFT        0U
+
+/* Register: IMXDPUV1_sig0_SigCRCBlue4 */
+#define IMXDPUV1_SIG0_SIGCRCBLUE4                            ((uint32_t)(0xD0C0))
+#define IMXDPUV1_SIG0_SIGCRCBLUE4_OFFSET                     ((uint32_t)(0xC0))
+#define IMXDPUV1_SIG0_SIGCRCBLUE4_RESET_VALUE                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE4_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE4_SIGCRCBLUE4_MASK           0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE4_SIGCRCBLUE4_SHIFT          0U
+
+/* Register: IMXDPUV1_sig0_EvalControl5 */
+#define IMXDPUV1_SIG0_EVALCONTROL5                           ((uint32_t)(0xD0C4))
+#define IMXDPUV1_SIG0_EVALCONTROL5_OFFSET                    ((uint32_t)(0xC4))
+#define IMXDPUV1_SIG0_EVALCONTROL5_RESET_VALUE               0U
+#define IMXDPUV1_SIG0_EVALCONTROL5_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALCONTROL5_ENEVALWIN5_MASK           0x1U
+#define IMXDPUV1_SIG0_EVALCONTROL5_ENEVALWIN5_SHIFT          0U
+#define IMXDPUV1_SIG0_EVALCONTROL5_ENCRC5_MASK               0x2U
+#define IMXDPUV1_SIG0_EVALCONTROL5_ENCRC5_SHIFT              1U
+#define IMXDPUV1_SIG0_EVALCONTROL5_ALPHAMASK5_MASK           0x100U
+#define IMXDPUV1_SIG0_EVALCONTROL5_ALPHAMASK5_SHIFT          8U
+#define IMXDPUV1_SIG0_EVALCONTROL5_ALPHAINV5_MASK            0x200U
+#define IMXDPUV1_SIG0_EVALCONTROL5_ALPHAINV5_SHIFT           9U
+#define IMXDPUV1_SIG0_EVALCONTROL5_ENLOCALPANIC5_MASK        0x10000U
+#define IMXDPUV1_SIG0_EVALCONTROL5_ENLOCALPANIC5_SHIFT       16U
+#define IMXDPUV1_SIG0_EVALCONTROL5_ENGLOBALPANIC5_MASK       0x20000U
+#define IMXDPUV1_SIG0_EVALCONTROL5_ENGLOBALPANIC5_SHIFT      17U
+
+/* Register: IMXDPUV1_sig0_EvalUpperLeft5 */
+#define IMXDPUV1_SIG0_EVALUPPERLEFT5                         ((uint32_t)(0xD0C8))
+#define IMXDPUV1_SIG0_EVALUPPERLEFT5_OFFSET                  ((uint32_t)(0xC8))
+#define IMXDPUV1_SIG0_EVALUPPERLEFT5_RESET_VALUE             0U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT5_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALUPPERLEFT5_XEVALUPPERLEFT5_MASK    0x3FFFU
+#define IMXDPUV1_SIG0_EVALUPPERLEFT5_XEVALUPPERLEFT5_SHIFT   0U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT5_YEVALUPPERLEFT5_MASK    0x3FFF0000U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT5_YEVALUPPERLEFT5_SHIFT   16U
+
+/* Register: IMXDPUV1_sig0_EvalLowerRight5 */
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT5                        ((uint32_t)(0xD0CC))
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_OFFSET                 ((uint32_t)(0xCC))
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_RESET_VALUE            0U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_XEVALLOWERRIGHT5_MASK  0x3FFFU
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_XEVALLOWERRIGHT5_SHIFT 0U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_YEVALLOWERRIGHT5_MASK  0x3FFF0000U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_YEVALLOWERRIGHT5_SHIFT 16U
+
+/* Register: IMXDPUV1_sig0_SigCRCRedRef5 */
+#define IMXDPUV1_SIG0_SIGCRCREDREF5                          ((uint32_t)(0xD0D0))
+#define IMXDPUV1_SIG0_SIGCRCREDREF5_OFFSET                   ((uint32_t)(0xD0))
+#define IMXDPUV1_SIG0_SIGCRCREDREF5_RESET_VALUE              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF5_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF5_SIGCRCREDREF5_MASK       0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF5_SIGCRCREDREF5_SHIFT      0U
+
+/* Register: IMXDPUV1_sig0_SigCRCGreenRef5 */
+#define IMXDPUV1_SIG0_SIGCRCGREENREF5                        ((uint32_t)(0xD0D4))
+#define IMXDPUV1_SIG0_SIGCRCGREENREF5_OFFSET                 ((uint32_t)(0xD4))
+#define IMXDPUV1_SIG0_SIGCRCGREENREF5_RESET_VALUE            0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF5_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF5_SIGCRCGREENREF5_MASK   0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF5_SIGCRCGREENREF5_SHIFT  0U
+
+/* Register: IMXDPUV1_sig0_SigCRCBlueRef5 */
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF5                         ((uint32_t)(0xD0D8))
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_OFFSET                  ((uint32_t)(0xD8))
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_RESET_VALUE             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_SIGCRCBLUEREF5_MASK     0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_SIGCRCBLUEREF5_SHIFT    0U
+
+/* Register: IMXDPUV1_sig0_SigCRCRed5 */
+#define IMXDPUV1_SIG0_SIGCRCRED5                             ((uint32_t)(0xD0DC))
+#define IMXDPUV1_SIG0_SIGCRCRED5_OFFSET                      ((uint32_t)(0xDC))
+#define IMXDPUV1_SIG0_SIGCRCRED5_RESET_VALUE                 0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED5_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED5_SIGCRCRED5_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED5_SIGCRCRED5_SHIFT            0U
+
+/* Register: IMXDPUV1_sig0_SigCRCGreen5 */
+#define IMXDPUV1_SIG0_SIGCRCGREEN5                           ((uint32_t)(0xD0E0))
+#define IMXDPUV1_SIG0_SIGCRCGREEN5_OFFSET                    ((uint32_t)(0xE0))
+#define IMXDPUV1_SIG0_SIGCRCGREEN5_RESET_VALUE               0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN5_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN5_SIGCRCGREEN5_MASK         0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN5_SIGCRCGREEN5_SHIFT        0U
+
+/* Register: IMXDPUV1_sig0_SigCRCBlue5 */
+#define IMXDPUV1_SIG0_SIGCRCBLUE5                            ((uint32_t)(0xD0E4))
+#define IMXDPUV1_SIG0_SIGCRCBLUE5_OFFSET                     ((uint32_t)(0xE4))
+#define IMXDPUV1_SIG0_SIGCRCBLUE5_RESET_VALUE                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE5_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE5_SIGCRCBLUE5_MASK           0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE5_SIGCRCBLUE5_SHIFT          0U
+
+/* Register: IMXDPUV1_sig0_EvalControl6 */
+#define IMXDPUV1_SIG0_EVALCONTROL6                           ((uint32_t)(0xD0E8))
+#define IMXDPUV1_SIG0_EVALCONTROL6_OFFSET                    ((uint32_t)(0xE8))
+#define IMXDPUV1_SIG0_EVALCONTROL6_RESET_VALUE               0U
+#define IMXDPUV1_SIG0_EVALCONTROL6_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALCONTROL6_ENEVALWIN6_MASK           0x1U
+#define IMXDPUV1_SIG0_EVALCONTROL6_ENEVALWIN6_SHIFT          0U
+#define IMXDPUV1_SIG0_EVALCONTROL6_ENCRC6_MASK               0x2U
+#define IMXDPUV1_SIG0_EVALCONTROL6_ENCRC6_SHIFT              1U
+#define IMXDPUV1_SIG0_EVALCONTROL6_ALPHAMASK6_MASK           0x100U
+#define IMXDPUV1_SIG0_EVALCONTROL6_ALPHAMASK6_SHIFT          8U
+#define IMXDPUV1_SIG0_EVALCONTROL6_ALPHAINV6_MASK            0x200U
+#define IMXDPUV1_SIG0_EVALCONTROL6_ALPHAINV6_SHIFT           9U
+#define IMXDPUV1_SIG0_EVALCONTROL6_ENLOCALPANIC6_MASK        0x10000U
+#define IMXDPUV1_SIG0_EVALCONTROL6_ENLOCALPANIC6_SHIFT       16U
+#define IMXDPUV1_SIG0_EVALCONTROL6_ENGLOBALPANIC6_MASK       0x20000U
+#define IMXDPUV1_SIG0_EVALCONTROL6_ENGLOBALPANIC6_SHIFT      17U
+
+/* Register: IMXDPUV1_sig0_EvalUpperLeft6 */
+#define IMXDPUV1_SIG0_EVALUPPERLEFT6                         ((uint32_t)(0xD0EC))
+#define IMXDPUV1_SIG0_EVALUPPERLEFT6_OFFSET                  ((uint32_t)(0xEC))
+#define IMXDPUV1_SIG0_EVALUPPERLEFT6_RESET_VALUE             0U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT6_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALUPPERLEFT6_XEVALUPPERLEFT6_MASK    0x3FFFU
+#define IMXDPUV1_SIG0_EVALUPPERLEFT6_XEVALUPPERLEFT6_SHIFT   0U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT6_YEVALUPPERLEFT6_MASK    0x3FFF0000U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT6_YEVALUPPERLEFT6_SHIFT   16U
+
+/* Register: IMXDPUV1_sig0_EvalLowerRight6 */
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT6                        ((uint32_t)(0xD0F0))
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_OFFSET                 ((uint32_t)(0xF0))
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_RESET_VALUE            0U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_XEVALLOWERRIGHT6_MASK  0x3FFFU
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_XEVALLOWERRIGHT6_SHIFT 0U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_YEVALLOWERRIGHT6_MASK  0x3FFF0000U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_YEVALLOWERRIGHT6_SHIFT 16U
+
+/* Register: IMXDPUV1_sig0_SigCRCRedRef6 */
+#define IMXDPUV1_SIG0_SIGCRCREDREF6                          ((uint32_t)(0xD0F4))
+#define IMXDPUV1_SIG0_SIGCRCREDREF6_OFFSET                   ((uint32_t)(0xF4))
+#define IMXDPUV1_SIG0_SIGCRCREDREF6_RESET_VALUE              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF6_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF6_SIGCRCREDREF6_MASK       0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF6_SIGCRCREDREF6_SHIFT      0U
+
+/* Register: IMXDPUV1_sig0_SigCRCGreenRef6 */
+#define IMXDPUV1_SIG0_SIGCRCGREENREF6                        ((uint32_t)(0xD0F8))
+#define IMXDPUV1_SIG0_SIGCRCGREENREF6_OFFSET                 ((uint32_t)(0xF8))
+#define IMXDPUV1_SIG0_SIGCRCGREENREF6_RESET_VALUE            0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF6_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF6_SIGCRCGREENREF6_MASK   0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF6_SIGCRCGREENREF6_SHIFT  0U
+
+/* Register: IMXDPUV1_sig0_SigCRCBlueRef6 */
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF6                         ((uint32_t)(0xD0FC))
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_OFFSET                  ((uint32_t)(0xFC))
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_RESET_VALUE             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_SIGCRCBLUEREF6_MASK     0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_SIGCRCBLUEREF6_SHIFT    0U
+
+/* Register: IMXDPUV1_sig0_SigCRCRed6 */
+#define IMXDPUV1_SIG0_SIGCRCRED6                             ((uint32_t)(0xD100))
+#define IMXDPUV1_SIG0_SIGCRCRED6_OFFSET                      ((uint32_t)(0x100))
+#define IMXDPUV1_SIG0_SIGCRCRED6_RESET_VALUE                 0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED6_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED6_SIGCRCRED6_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED6_SIGCRCRED6_SHIFT            0U
+
+/* Register: IMXDPUV1_sig0_SigCRCGreen6 */
+#define IMXDPUV1_SIG0_SIGCRCGREEN6                           ((uint32_t)(0xD104))
+#define IMXDPUV1_SIG0_SIGCRCGREEN6_OFFSET                    ((uint32_t)(0x104))
+#define IMXDPUV1_SIG0_SIGCRCGREEN6_RESET_VALUE               0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN6_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN6_SIGCRCGREEN6_MASK         0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN6_SIGCRCGREEN6_SHIFT        0U
+
+/* Register: IMXDPUV1_sig0_SigCRCBlue6 */
+#define IMXDPUV1_SIG0_SIGCRCBLUE6                            ((uint32_t)(0xD108))
+#define IMXDPUV1_SIG0_SIGCRCBLUE6_OFFSET                     ((uint32_t)(0x108))
+#define IMXDPUV1_SIG0_SIGCRCBLUE6_RESET_VALUE                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE6_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE6_SIGCRCBLUE6_MASK           0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE6_SIGCRCBLUE6_SHIFT          0U
+
+/* Register: IMXDPUV1_sig0_EvalControl7 */
+#define IMXDPUV1_SIG0_EVALCONTROL7                           ((uint32_t)(0xD10C))
+#define IMXDPUV1_SIG0_EVALCONTROL7_OFFSET                    ((uint32_t)(0x10C))
+#define IMXDPUV1_SIG0_EVALCONTROL7_RESET_VALUE               0U
+#define IMXDPUV1_SIG0_EVALCONTROL7_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALCONTROL7_ENEVALWIN7_MASK           0x1U
+#define IMXDPUV1_SIG0_EVALCONTROL7_ENEVALWIN7_SHIFT          0U
+#define IMXDPUV1_SIG0_EVALCONTROL7_ENCRC7_MASK               0x2U
+#define IMXDPUV1_SIG0_EVALCONTROL7_ENCRC7_SHIFT              1U
+#define IMXDPUV1_SIG0_EVALCONTROL7_ALPHAMASK7_MASK           0x100U
+#define IMXDPUV1_SIG0_EVALCONTROL7_ALPHAMASK7_SHIFT          8U
+#define IMXDPUV1_SIG0_EVALCONTROL7_ALPHAINV7_MASK            0x200U
+#define IMXDPUV1_SIG0_EVALCONTROL7_ALPHAINV7_SHIFT           9U
+#define IMXDPUV1_SIG0_EVALCONTROL7_ENLOCALPANIC7_MASK        0x10000U
+#define IMXDPUV1_SIG0_EVALCONTROL7_ENLOCALPANIC7_SHIFT       16U
+#define IMXDPUV1_SIG0_EVALCONTROL7_ENGLOBALPANIC7_MASK       0x20000U
+#define IMXDPUV1_SIG0_EVALCONTROL7_ENGLOBALPANIC7_SHIFT      17U
+
+/* Register: IMXDPUV1_sig0_EvalUpperLeft7 */
+#define IMXDPUV1_SIG0_EVALUPPERLEFT7                         ((uint32_t)(0xD110))
+#define IMXDPUV1_SIG0_EVALUPPERLEFT7_OFFSET                  ((uint32_t)(0x110))
+#define IMXDPUV1_SIG0_EVALUPPERLEFT7_RESET_VALUE             0U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT7_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALUPPERLEFT7_XEVALUPPERLEFT7_MASK    0x3FFFU
+#define IMXDPUV1_SIG0_EVALUPPERLEFT7_XEVALUPPERLEFT7_SHIFT   0U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT7_YEVALUPPERLEFT7_MASK    0x3FFF0000U
+#define IMXDPUV1_SIG0_EVALUPPERLEFT7_YEVALUPPERLEFT7_SHIFT   16U
+
+/* Register: IMXDPUV1_sig0_EvalLowerRight7 */
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT7                        ((uint32_t)(0xD114))
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_OFFSET                 ((uint32_t)(0x114))
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_RESET_VALUE            0U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_XEVALLOWERRIGHT7_MASK  0x3FFFU
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_XEVALLOWERRIGHT7_SHIFT 0U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_YEVALLOWERRIGHT7_MASK  0x3FFF0000U
+#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_YEVALLOWERRIGHT7_SHIFT 16U
+
+/* Register: IMXDPUV1_sig0_SigCRCRedRef7 */
+#define IMXDPUV1_SIG0_SIGCRCREDREF7                          ((uint32_t)(0xD118))
+#define IMXDPUV1_SIG0_SIGCRCREDREF7_OFFSET                   ((uint32_t)(0x118))
+#define IMXDPUV1_SIG0_SIGCRCREDREF7_RESET_VALUE              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF7_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF7_SIGCRCREDREF7_MASK       0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCREDREF7_SIGCRCREDREF7_SHIFT      0U
+
+/* Register: IMXDPUV1_sig0_SigCRCGreenRef7 */
+#define IMXDPUV1_SIG0_SIGCRCGREENREF7                        ((uint32_t)(0xD11C))
+#define IMXDPUV1_SIG0_SIGCRCGREENREF7_OFFSET                 ((uint32_t)(0x11C))
+#define IMXDPUV1_SIG0_SIGCRCGREENREF7_RESET_VALUE            0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF7_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF7_SIGCRCGREENREF7_MASK   0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREENREF7_SIGCRCGREENREF7_SHIFT  0U
+
+/* Register: IMXDPUV1_sig0_SigCRCBlueRef7 */
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF7                         ((uint32_t)(0xD120))
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_OFFSET                  ((uint32_t)(0x120))
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_RESET_VALUE             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_SIGCRCBLUEREF7_MASK     0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_SIGCRCBLUEREF7_SHIFT    0U
+
+/* Register: IMXDPUV1_sig0_SigCRCRed7 */
+#define IMXDPUV1_SIG0_SIGCRCRED7                             ((uint32_t)(0xD124))
+#define IMXDPUV1_SIG0_SIGCRCRED7_OFFSET                      ((uint32_t)(0x124))
+#define IMXDPUV1_SIG0_SIGCRCRED7_RESET_VALUE                 0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED7_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED7_SIGCRCRED7_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCRED7_SIGCRCRED7_SHIFT            0U
+
+/* Register: IMXDPUV1_sig0_SigCRCGreen7 */
+#define IMXDPUV1_SIG0_SIGCRCGREEN7                           ((uint32_t)(0xD128))
+#define IMXDPUV1_SIG0_SIGCRCGREEN7_OFFSET                    ((uint32_t)(0x128))
+#define IMXDPUV1_SIG0_SIGCRCGREEN7_RESET_VALUE               0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN7_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN7_SIGCRCGREEN7_MASK         0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCGREEN7_SIGCRCGREEN7_SHIFT        0U
+
+/* Register: IMXDPUV1_sig0_SigCRCBlue7 */
+#define IMXDPUV1_SIG0_SIGCRCBLUE7                            ((uint32_t)(0xD12C))
+#define IMXDPUV1_SIG0_SIGCRCBLUE7_OFFSET                     ((uint32_t)(0x12C))
+#define IMXDPUV1_SIG0_SIGCRCBLUE7_RESET_VALUE                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE7_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE7_SIGCRCBLUE7_MASK           0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SIGCRCBLUE7_SIGCRCBLUE7_SHIFT          0U
+
+/* Register: IMXDPUV1_sig0_ShadowLoad */
+#define IMXDPUV1_SIG0_SHADOWLOAD                             ((uint32_t)(0xD130))
+#define IMXDPUV1_SIG0_SHADOWLOAD_OFFSET                      ((uint32_t)(0x130))
+#define IMXDPUV1_SIG0_SHADOWLOAD_RESET_VALUE                 0U
+#define IMXDPUV1_SIG0_SHADOWLOAD_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SHADOWLOAD_SHDLDREQ_MASK               0xFFU
+#define IMXDPUV1_SIG0_SHADOWLOAD_SHDLDREQ_SHIFT              0U
+
+/* Register: IMXDPUV1_sig0_ContinuousMode */
+#define IMXDPUV1_SIG0_CONTINUOUSMODE                         ((uint32_t)(0xD134))
+#define IMXDPUV1_SIG0_CONTINUOUSMODE_OFFSET                  ((uint32_t)(0x134))
+#define IMXDPUV1_SIG0_CONTINUOUSMODE_RESET_VALUE             0U
+#define IMXDPUV1_SIG0_CONTINUOUSMODE_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG0_CONTINUOUSMODE_ENCONT_MASK             0x1U
+#define IMXDPUV1_SIG0_CONTINUOUSMODE_ENCONT_SHIFT            0U
+
+/* Register: IMXDPUV1_sig0_SoftwareKick */
+#define IMXDPUV1_SIG0_SOFTWAREKICK                           ((uint32_t)(0xD138))
+#define IMXDPUV1_SIG0_SOFTWAREKICK_OFFSET                    ((uint32_t)(0x138))
+#define IMXDPUV1_SIG0_SOFTWAREKICK_RESET_VALUE               0U
+#define IMXDPUV1_SIG0_SOFTWAREKICK_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG0_SOFTWAREKICK_KICK_MASK                 0x1U
+#define IMXDPUV1_SIG0_SOFTWAREKICK_KICK_SHIFT                0U
+
+/* Register: IMXDPUV1_sig0_Status */
+#define IMXDPUV1_SIG0_STATUS                                 ((uint32_t)(0xD13C))
+#define IMXDPUV1_SIG0_STATUS_OFFSET                          ((uint32_t)(0x13C))
+#define IMXDPUV1_SIG0_STATUS_RESET_VALUE                     0x100000U
+#define IMXDPUV1_SIG0_STATUS_RESET_MASK                      0xFFFFFFFFU
+#define IMXDPUV1_SIG0_STATUS_STSSIGERROR_MASK                0xFFU
+#define IMXDPUV1_SIG0_STATUS_STSSIGERROR_SHIFT               0U
+#define IMXDPUV1_SIG0_STATUS_STSSIGVALID_MASK                0x10000U
+#define IMXDPUV1_SIG0_STATUS_STSSIGVALID_SHIFT               16U
+#define IMXDPUV1_SIG0_STATUS_STSSIGIDLE_MASK                 0x100000U
+#define IMXDPUV1_SIG0_STATUS_STSSIGIDLE_SHIFT                20U
+
+/* Register: IMXDPUV1_framegen1_LockUnlock */
+#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK                        ((uint32_t)(0xD400))
+#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_OFFSET                 ((uint32_t)(0))
+#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_RESET_VALUE            0U
+#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_RESET_MASK             0U
+#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK_MASK        0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK_SHIFT       0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY   0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_framegen1_LockStatus */
+#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS                        ((uint32_t)(0xD404))
+#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_OFFSET                 ((uint32_t)(0x4))
+#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_RESET_VALUE            0U
+#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_LOCKSTATUS_MASK        0x1U
+#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_LOCKSTATUS_SHIFT       0U
+#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_PRIVILEGESTATUS_MASK   0x10U
+#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT  4U
+#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_FREEZESTATUS_MASK      0x100U
+#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_FREEZESTATUS_SHIFT     8U
+
+/* Register: IMXDPUV1_framegen1_FgStCtrl */
+#define IMXDPUV1_FRAMEGEN1_FGSTCTRL                          ((uint32_t)(0xD408))
+#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_OFFSET                   ((uint32_t)(0x8))
+#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_RESET_VALUE              0U
+#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_SHDEN_MASK               0x1U
+#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_SHDEN_SHIFT              0U
+#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE_MASK          0x6U
+#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE_SHIFT         1U
+/* Field Value: FGSYNCMODE__OFF, No side-by-side synchronization.  */
+#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__OFF          0U
+/* Field Value: FGSYNCMODE__MASTER, Framegen is master.  */
+#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__MASTER       0x1U
+/* Field Value: FGSYNCMODE__SLAVE_CYC, Framegen is slave. Runs in cyclic synchronization
+ * mode.  */
+#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__SLAVE_CYC    0x2U
+/* Field Value: FGSYNCMODE__SLAVE_ONCE, Framegen is slave. Runs in one time
+ * synchronization mode.  */
+#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__SLAVE_ONCE   0x3U
+
+/* Register: IMXDPUV1_framegen1_HtCfg1 */
+#define IMXDPUV1_FRAMEGEN1_HTCFG1                            ((uint32_t)(0xD40C))
+#define IMXDPUV1_FRAMEGEN1_HTCFG1_OFFSET                     ((uint32_t)(0xC))
+#define IMXDPUV1_FRAMEGEN1_HTCFG1_RESET_VALUE                0x18F0140U
+#define IMXDPUV1_FRAMEGEN1_HTCFG1_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_HTCFG1_HACT_MASK                  0x3FFFU
+#define IMXDPUV1_FRAMEGEN1_HTCFG1_HACT_SHIFT                 0U
+#define IMXDPUV1_FRAMEGEN1_HTCFG1_HTOTAL_MASK                0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN1_HTCFG1_HTOTAL_SHIFT               16U
+
+/* Register: IMXDPUV1_framegen1_HtCfg2 */
+#define IMXDPUV1_FRAMEGEN1_HTCFG2                            ((uint32_t)(0xD410))
+#define IMXDPUV1_FRAMEGEN1_HTCFG2_OFFSET                     ((uint32_t)(0x10))
+#define IMXDPUV1_FRAMEGEN1_HTCFG2_RESET_VALUE                0x8047001FU
+#define IMXDPUV1_FRAMEGEN1_HTCFG2_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSYNC_MASK                 0x3FFFU
+#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSYNC_SHIFT                0U
+#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSBP_MASK                  0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSBP_SHIFT                 16U
+#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSEN_MASK                  0x80000000U
+#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSEN_SHIFT                 31U
+
+/* Register: IMXDPUV1_framegen1_VtCfg1 */
+#define IMXDPUV1_FRAMEGEN1_VTCFG1                            ((uint32_t)(0xD414))
+#define IMXDPUV1_FRAMEGEN1_VTCFG1_OFFSET                     ((uint32_t)(0x14))
+#define IMXDPUV1_FRAMEGEN1_VTCFG1_RESET_VALUE                0xFC00F0U
+#define IMXDPUV1_FRAMEGEN1_VTCFG1_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_VTCFG1_VACT_MASK                  0x3FFFU
+#define IMXDPUV1_FRAMEGEN1_VTCFG1_VACT_SHIFT                 0U
+#define IMXDPUV1_FRAMEGEN1_VTCFG1_VTOTAL_MASK                0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN1_VTCFG1_VTOTAL_SHIFT               16U
+
+/* Register: IMXDPUV1_framegen1_VtCfg2 */
+#define IMXDPUV1_FRAMEGEN1_VTCFG2                            ((uint32_t)(0xD418))
+#define IMXDPUV1_FRAMEGEN1_VTCFG2_OFFSET                     ((uint32_t)(0x18))
+#define IMXDPUV1_FRAMEGEN1_VTCFG2_RESET_VALUE                0x80090003U
+#define IMXDPUV1_FRAMEGEN1_VTCFG2_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSYNC_MASK                 0x3FFFU
+#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSYNC_SHIFT                0U
+#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSBP_MASK                  0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSBP_SHIFT                 16U
+#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSEN_MASK                  0x80000000U
+#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSEN_SHIFT                 31U
+
+/* Register: IMXDPUV1_framegen1_Int0Config */
+#define IMXDPUV1_FRAMEGEN1_INT0CONFIG                        ((uint32_t)(0xD41C))
+#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_OFFSET                 ((uint32_t)(0x1C))
+#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_RESET_VALUE            0U
+#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0COL_MASK           0x3FFFU
+#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0COL_SHIFT          0U
+#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0HSEN_MASK          0x8000U
+#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0HSEN_SHIFT         15U
+#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0ROW_MASK           0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0ROW_SHIFT          16U
+#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0EN_MASK            0x80000000U
+#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0EN_SHIFT           31U
+
+/* Register: IMXDPUV1_framegen1_Int1Config */
+#define IMXDPUV1_FRAMEGEN1_INT1CONFIG                        ((uint32_t)(0xD420))
+#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_OFFSET                 ((uint32_t)(0x20))
+#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_RESET_VALUE            0U
+#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1COL_MASK           0x3FFFU
+#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1COL_SHIFT          0U
+#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1HSEN_MASK          0x8000U
+#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1HSEN_SHIFT         15U
+#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1ROW_MASK           0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1ROW_SHIFT          16U
+#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1EN_MASK            0x80000000U
+#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1EN_SHIFT           31U
+
+/* Register: IMXDPUV1_framegen1_Int2Config */
+#define IMXDPUV1_FRAMEGEN1_INT2CONFIG                        ((uint32_t)(0xD424))
+#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_OFFSET                 ((uint32_t)(0x24))
+#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_RESET_VALUE            0U
+#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2COL_MASK           0x3FFFU
+#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2COL_SHIFT          0U
+#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2HSEN_MASK          0x8000U
+#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2HSEN_SHIFT         15U
+#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2ROW_MASK           0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2ROW_SHIFT          16U
+#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2EN_MASK            0x80000000U
+#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2EN_SHIFT           31U
+
+/* Register: IMXDPUV1_framegen1_Int3Config */
+#define IMXDPUV1_FRAMEGEN1_INT3CONFIG                        ((uint32_t)(0xD428))
+#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_OFFSET                 ((uint32_t)(0x28))
+#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_RESET_VALUE            0U
+#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3COL_MASK           0x3FFFU
+#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3COL_SHIFT          0U
+#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3HSEN_MASK          0x8000U
+#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3HSEN_SHIFT         15U
+#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3ROW_MASK           0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3ROW_SHIFT          16U
+#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3EN_MASK            0x80000000U
+#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3EN_SHIFT           31U
+
+/* Register: IMXDPUV1_framegen1_PKickConfig */
+#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG                       ((uint32_t)(0xD42C))
+#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_OFFSET                ((uint32_t)(0x2C))
+#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_RESET_VALUE           0xF00140U
+#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKCOL_MASK         0x3FFFU
+#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKCOL_SHIFT        0U
+#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKINT0EN_MASK      0x8000U
+#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKINT0EN_SHIFT     15U
+#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKROW_MASK         0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKROW_SHIFT        16U
+#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKEN_MASK          0x80000000U
+#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKEN_SHIFT         31U
+
+/* Register: IMXDPUV1_framegen1_SKickConfig */
+#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG                       ((uint32_t)(0xD430))
+#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_OFFSET                ((uint32_t)(0x30))
+#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_RESET_VALUE           0xF00140U
+#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKCOL_MASK         0x3FFFU
+#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKCOL_SHIFT        0U
+#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKINT1EN_MASK      0x8000U
+#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKINT1EN_SHIFT     15U
+#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKROW_MASK         0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKROW_SHIFT        16U
+#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKTRIG_MASK        0x40000000U
+#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKTRIG_SHIFT       30U
+/* Field Value: SKICKTRIG__INTERNAL, Use internal skick signal, trigger point
+ * defined by SKickRow and SKickCol.  */
+#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKTRIG__INTERNAL   0U
+/* Field Value: SKICKTRIG__EXTERNAL, Use external skick input as trigger.  */
+#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKTRIG__EXTERNAL   0x1U
+#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKEN_MASK          0x80000000U
+#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKEN_SHIFT         31U
+
+/* Register: IMXDPUV1_framegen1_SecStatConfig */
+#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG                     ((uint32_t)(0xD434))
+#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_OFFSET              ((uint32_t)(0x34))
+#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_RESET_VALUE         0x112U
+#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVGOODFRAMES_MASK  0xFU
+#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVGOODFRAMES_SHIFT 0U
+#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVBADFRAMES_MASK   0xF0U
+#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVBADFRAMES_SHIFT  4U
+#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVSKEWINRANGE_MASK 0xF00U
+#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVSKEWINRANGE_SHIFT 8U
+
+/* Register: IMXDPUV1_framegen1_FgSRCR1 */
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1                           ((uint32_t)(0xD438))
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_OFFSET                    ((uint32_t)(0x38))
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_RESET_VALUE               0U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREN_MASK                 0x1U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREN_SHIFT                0U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE_MASK               0x6U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE_SHIFT              1U
+/* Field Value: SRMODE__OFF, Skew Regulation is off.  */
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE__OFF               0U
+/* Field Value: SRMODE__HREG, Horizontal regulation enabled.  */
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE__HREG              0x1U
+/* Field Value: SRMODE__VREG, Vertical regulation enabled.  */
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE__VREG              0x2U
+/* Field Value: SRMODE__BOTH, Both regulation modes are enabled.  */
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE__BOTH              0x3U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRADJ_MASK                0x8U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRADJ_SHIFT               3U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREVEN_MASK               0x10U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREVEN_SHIFT              4U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRFASTSYNC_MASK           0x20U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRFASTSYNC_SHIFT          5U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQALIGN_MASK             0x40U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQALIGN_SHIFT            6U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL_MASK               0x180U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL_SHIFT              7U
+/* Field Value: SRQVAL__ZERO, Fixed two LSB values of HTOTAL are 0b00.  */
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL__ZERO              0U
+/* Field Value: SRQVAL__ONE, Fixed two LSB values of HTOTAL are 0b01.  */
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL__ONE               0x1U
+/* Field Value: SRQVAL__TWO, Fixed two LSB values of HTOTAL are 0b10.  */
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL__TWO               0x2U
+/* Field Value: SRQVAL__THREE, Fixed two LSB values of HTOTAL are 0b11.  */
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL__THREE             0x3U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRDBGDISP_MASK            0x10000U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRDBGDISP_SHIFT           16U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREPOFF_MASK              0x20000U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREPOFF_SHIFT             17U
+
+/* Register: IMXDPUV1_framegen1_FgSRCR2 */
+#define IMXDPUV1_FRAMEGEN1_FGSRCR2                           ((uint32_t)(0xD43C))
+#define IMXDPUV1_FRAMEGEN1_FGSRCR2_OFFSET                    ((uint32_t)(0x3C))
+#define IMXDPUV1_FRAMEGEN1_FGSRCR2_RESET_VALUE               0x1B70188U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR2_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSRCR2_HTOTALMIN_MASK            0x3FFFU
+#define IMXDPUV1_FRAMEGEN1_FGSRCR2_HTOTALMIN_SHIFT           0U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR2_HTOTALMAX_MASK            0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR2_HTOTALMAX_SHIFT           16U
+
+/* Register: IMXDPUV1_framegen1_FgSRCR3 */
+#define IMXDPUV1_FRAMEGEN1_FGSRCR3                           ((uint32_t)(0xD440))
+#define IMXDPUV1_FRAMEGEN1_FGSRCR3_OFFSET                    ((uint32_t)(0x40))
+#define IMXDPUV1_FRAMEGEN1_FGSRCR3_RESET_VALUE               0x11500FBU
+#define IMXDPUV1_FRAMEGEN1_FGSRCR3_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSRCR3_VTOTALMIN_MASK            0x3FFFU
+#define IMXDPUV1_FRAMEGEN1_FGSRCR3_VTOTALMIN_SHIFT           0U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR3_VTOTALMAX_MASK            0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR3_VTOTALMAX_SHIFT           16U
+
+/* Register: IMXDPUV1_framegen1_FgSRCR4 */
+#define IMXDPUV1_FRAMEGEN1_FGSRCR4                           ((uint32_t)(0xD444))
+#define IMXDPUV1_FRAMEGEN1_FGSRCR4_OFFSET                    ((uint32_t)(0x44))
+#define IMXDPUV1_FRAMEGEN1_FGSRCR4_RESET_VALUE               0xC8U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR4_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSRCR4_TARGETSKEW_MASK           0x1FFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSRCR4_TARGETSKEW_SHIFT          0U
+
+/* Register: IMXDPUV1_framegen1_FgSRCR5 */
+#define IMXDPUV1_FRAMEGEN1_FGSRCR5                           ((uint32_t)(0xD448))
+#define IMXDPUV1_FRAMEGEN1_FGSRCR5_OFFSET                    ((uint32_t)(0x48))
+#define IMXDPUV1_FRAMEGEN1_FGSRCR5_RESET_VALUE               0U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR5_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSRCR5_SYNCRANGELOW_MASK         0x1FFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSRCR5_SYNCRANGELOW_SHIFT        0U
+
+/* Register: IMXDPUV1_framegen1_FgSRCR6 */
+#define IMXDPUV1_FRAMEGEN1_FGSRCR6                           ((uint32_t)(0xD44C))
+#define IMXDPUV1_FRAMEGEN1_FGSRCR6_OFFSET                    ((uint32_t)(0x4C))
+#define IMXDPUV1_FRAMEGEN1_FGSRCR6_RESET_VALUE               0x190U
+#define IMXDPUV1_FRAMEGEN1_FGSRCR6_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSRCR6_SYNCRANGEHIGH_MASK        0x1FFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSRCR6_SYNCRANGEHIGH_SHIFT       0U
+
+/* Register: IMXDPUV1_framegen1_FgKSDR */
+#define IMXDPUV1_FRAMEGEN1_FGKSDR                            ((uint32_t)(0xD450))
+#define IMXDPUV1_FRAMEGEN1_FGKSDR_OFFSET                     ((uint32_t)(0x50))
+#define IMXDPUV1_FRAMEGEN1_FGKSDR_RESET_VALUE                0x20002U
+#define IMXDPUV1_FRAMEGEN1_FGKSDR_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGKSDR_PCNTCPLMAX_MASK            0x7U
+#define IMXDPUV1_FRAMEGEN1_FGKSDR_PCNTCPLMAX_SHIFT           0U
+#define IMXDPUV1_FRAMEGEN1_FGKSDR_SCNTCPLMAX_MASK            0x70000U
+#define IMXDPUV1_FRAMEGEN1_FGKSDR_SCNTCPLMAX_SHIFT           16U
+
+/* Register: IMXDPUV1_framegen1_PaCfg */
+#define IMXDPUV1_FRAMEGEN1_PACFG                             ((uint32_t)(0xD454))
+#define IMXDPUV1_FRAMEGEN1_PACFG_OFFSET                      ((uint32_t)(0x54))
+#define IMXDPUV1_FRAMEGEN1_PACFG_RESET_VALUE                 0x10001U
+#define IMXDPUV1_FRAMEGEN1_PACFG_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_PACFG_PSTARTX_MASK                0x3FFFU
+#define IMXDPUV1_FRAMEGEN1_PACFG_PSTARTX_SHIFT               0U
+#define IMXDPUV1_FRAMEGEN1_PACFG_PSTARTY_MASK                0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN1_PACFG_PSTARTY_SHIFT               16U
+
+/* Register: IMXDPUV1_framegen1_SaCfg */
+#define IMXDPUV1_FRAMEGEN1_SACFG                             ((uint32_t)(0xD458))
+#define IMXDPUV1_FRAMEGEN1_SACFG_OFFSET                      ((uint32_t)(0x58))
+#define IMXDPUV1_FRAMEGEN1_SACFG_RESET_VALUE                 0x10001U
+#define IMXDPUV1_FRAMEGEN1_SACFG_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_SACFG_SSTARTX_MASK                0x3FFFU
+#define IMXDPUV1_FRAMEGEN1_SACFG_SSTARTX_SHIFT               0U
+#define IMXDPUV1_FRAMEGEN1_SACFG_SSTARTY_MASK                0x3FFF0000U
+#define IMXDPUV1_FRAMEGEN1_SACFG_SSTARTY_SHIFT               16U
+
+/* Register: IMXDPUV1_framegen1_FgInCtrl */
+#define IMXDPUV1_FRAMEGEN1_FGINCTRL                          ((uint32_t)(0xD45C))
+#define IMXDPUV1_FRAMEGEN1_FGINCTRL_OFFSET                   ((uint32_t)(0x5C))
+#define IMXDPUV1_FRAMEGEN1_FGINCTRL_RESET_VALUE              0x6U
+#define IMXDPUV1_FRAMEGEN1_FGINCTRL_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM_MASK                0x7U
+#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM_SHIFT               0U
+/* Field Value: FGDM__BLACK, Black Color Background is shown.  */
+#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__BLACK              0U
+/* Field Value: FGDM__CONSTCOL, Constant Color Background is shown.  */
+#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__CONSTCOL           0x1U
+/* Field Value: FGDM__PRIM, Primary input only is shown.  */
+#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__PRIM               0x2U
+/* Field Value: FGDM__SEC, Secondary input only is shown.  */
+#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__SEC                0x3U
+/* Field Value: FGDM__PRIM_ON_TOP, Both inputs overlaid with primary on top.  */
+#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__PRIM_ON_TOP        0x4U
+/* Field Value: FGDM__SEC_ON_TOP, Both inputs overlaid with secondary on top.  */
+#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__SEC_ON_TOP         0x5U
+/* Field Value: FGDM__TEST, White color background with test pattern is shown.  */
+#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__TEST               0x6U
+#define IMXDPUV1_FRAMEGEN1_FGINCTRL_ENPRIMALPHA_MASK         0x8U
+#define IMXDPUV1_FRAMEGEN1_FGINCTRL_ENPRIMALPHA_SHIFT        3U
+#define IMXDPUV1_FRAMEGEN1_FGINCTRL_ENSECALPHA_MASK          0x10U
+#define IMXDPUV1_FRAMEGEN1_FGINCTRL_ENSECALPHA_SHIFT         4U
+
+/* Register: IMXDPUV1_framegen1_FgInCtrlPanic */
+#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC                     ((uint32_t)(0xD460))
+#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_OFFSET              ((uint32_t)(0x60))
+#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_RESET_VALUE         0U
+#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC_MASK      0x7U
+#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC_SHIFT     0U
+/* Field Value: FGDMPANIC__BLACK, Black Color Background is shown.  */
+#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__BLACK    0U
+/* Field Value: FGDMPANIC__CONSTCOL, Constant Color Background is shown.  */
+#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__CONSTCOL 0x1U
+/* Field Value: FGDMPANIC__PRIM, Primary input only is shown.  */
+#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__PRIM     0x2U
+/* Field Value: FGDMPANIC__SEC, Secondary input only is shown.  */
+#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__SEC      0x3U
+/* Field Value: FGDMPANIC__PRIM_ON_TOP, Both inputs overlaid with primary
+ * on top.  */
+#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__PRIM_ON_TOP 0x4U
+/* Field Value: FGDMPANIC__SEC_ON_TOP, Both inputs overlaid with secondary
+ * on top.  */
+#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__SEC_ON_TOP 0x5U
+/* Field Value: FGDMPANIC__TEST, White color background with test pattern
+ * is shown.  */
+#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__TEST     0x6U
+#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_ENPRIMALPHAPANIC_MASK 0x8U
+#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_ENPRIMALPHAPANIC_SHIFT 3U
+#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_ENSECALPHAPANIC_MASK 0x10U
+#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_ENSECALPHAPANIC_SHIFT 4U
+
+/* Register: IMXDPUV1_framegen1_FgCCR */
+#define IMXDPUV1_FRAMEGEN1_FGCCR                             ((uint32_t)(0xD464))
+#define IMXDPUV1_FRAMEGEN1_FGCCR_OFFSET                      ((uint32_t)(0x64))
+#define IMXDPUV1_FRAMEGEN1_FGCCR_RESET_VALUE                 0x7FFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGCCR_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGCCR_CCBLUE_MASK                 0x3FFU
+#define IMXDPUV1_FRAMEGEN1_FGCCR_CCBLUE_SHIFT                0U
+#define IMXDPUV1_FRAMEGEN1_FGCCR_CCGREEN_MASK                0xFFC00U
+#define IMXDPUV1_FRAMEGEN1_FGCCR_CCGREEN_SHIFT               10U
+#define IMXDPUV1_FRAMEGEN1_FGCCR_CCRED_MASK                  0x3FF00000U
+#define IMXDPUV1_FRAMEGEN1_FGCCR_CCRED_SHIFT                 20U
+#define IMXDPUV1_FRAMEGEN1_FGCCR_CCALPHA_MASK                0x40000000U
+#define IMXDPUV1_FRAMEGEN1_FGCCR_CCALPHA_SHIFT               30U
+
+/* Register: IMXDPUV1_framegen1_FgEnable */
+#define IMXDPUV1_FRAMEGEN1_FGENABLE                          ((uint32_t)(0xD468))
+#define IMXDPUV1_FRAMEGEN1_FGENABLE_OFFSET                   ((uint32_t)(0x68))
+#define IMXDPUV1_FRAMEGEN1_FGENABLE_RESET_VALUE              0U
+#define IMXDPUV1_FRAMEGEN1_FGENABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGENABLE_FGEN_MASK                0x1U
+#define IMXDPUV1_FRAMEGEN1_FGENABLE_FGEN_SHIFT               0U
+
+/* Register: IMXDPUV1_framegen1_FgSlr */
+#define IMXDPUV1_FRAMEGEN1_FGSLR                             ((uint32_t)(0xD46C))
+#define IMXDPUV1_FRAMEGEN1_FGSLR_OFFSET                      ((uint32_t)(0x6C))
+#define IMXDPUV1_FRAMEGEN1_FGSLR_RESET_VALUE                 0U
+#define IMXDPUV1_FRAMEGEN1_FGSLR_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSLR_SHDTOKGEN_MASK              0x1U
+#define IMXDPUV1_FRAMEGEN1_FGSLR_SHDTOKGEN_SHIFT             0U
+
+/* Register: IMXDPUV1_framegen1_FgEnSts */
+#define IMXDPUV1_FRAMEGEN1_FGENSTS                           ((uint32_t)(0xD470))
+#define IMXDPUV1_FRAMEGEN1_FGENSTS_OFFSET                    ((uint32_t)(0x70))
+#define IMXDPUV1_FRAMEGEN1_FGENSTS_RESET_VALUE               0U
+#define IMXDPUV1_FRAMEGEN1_FGENSTS_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGENSTS_ENSTS_MASK                0x1U
+#define IMXDPUV1_FRAMEGEN1_FGENSTS_ENSTS_SHIFT               0U
+#define IMXDPUV1_FRAMEGEN1_FGENSTS_PANICSTAT_MASK            0x2U
+#define IMXDPUV1_FRAMEGEN1_FGENSTS_PANICSTAT_SHIFT           1U
+
+/* Register: IMXDPUV1_framegen1_FgTimeStamp */
+#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP                       ((uint32_t)(0xD474))
+#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_OFFSET                ((uint32_t)(0x74))
+#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_RESET_VALUE           0U
+#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_LINEINDEX_MASK        0x3FFFU
+#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_LINEINDEX_SHIFT       0U
+#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_FRAMEINDEX_MASK       0xFFFFC000U
+#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_FRAMEINDEX_SHIFT      14U
+
+/* Register: IMXDPUV1_framegen1_FgChStat */
+#define IMXDPUV1_FRAMEGEN1_FGCHSTAT                          ((uint32_t)(0xD478))
+#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_OFFSET                   ((uint32_t)(0x78))
+#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_RESET_VALUE              0U
+#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_PFIFOEMPTY_MASK          0x1U
+#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_PFIFOEMPTY_SHIFT         0U
+#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_PRIMSYNCSTAT_MASK        0x100U
+#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_PRIMSYNCSTAT_SHIFT       8U
+#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SFIFOEMPTY_MASK          0x10000U
+#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SFIFOEMPTY_SHIFT         16U
+#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SKEWRANGEERR_MASK        0x20000U
+#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SKEWRANGEERR_SHIFT       17U
+#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SECSYNCSTAT_MASK         0x1000000U
+#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SECSYNCSTAT_SHIFT        24U
+
+/* Register: IMXDPUV1_framegen1_FgChStatClr */
+#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR                       ((uint32_t)(0xD47C))
+#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_OFFSET                ((uint32_t)(0x7C))
+#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_RESET_VALUE           0U
+#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_CLRPRIMSTAT_MASK      0x1U
+#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_CLRPRIMSTAT_SHIFT     0U
+#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_CLRSECSTAT_MASK       0x10000U
+#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_CLRSECSTAT_SHIFT      16U
+
+/* Register: IMXDPUV1_framegen1_FgSkewMon */
+#define IMXDPUV1_FRAMEGEN1_FGSKEWMON                         ((uint32_t)(0xD480))
+#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_OFFSET                  ((uint32_t)(0x80))
+#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_RESET_VALUE             0U
+#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_SKEWMON_MASK            0x1FFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_SKEWMON_SHIFT           0U
+
+/* Register: IMXDPUV1_framegen1_FgSFifoMin */
+#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN                        ((uint32_t)(0xD484))
+#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_OFFSET                 ((uint32_t)(0x84))
+#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_RESET_VALUE            0U
+#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_SFIFOMIN_MASK          0xFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_SFIFOMIN_SHIFT         0U
+
+/* Register: IMXDPUV1_framegen1_FgSFifoMax */
+#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX                        ((uint32_t)(0xD488))
+#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_OFFSET                 ((uint32_t)(0x88))
+#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_RESET_VALUE            0U
+#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_SFIFOMAX_MASK          0xFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_SFIFOMAX_SHIFT         0U
+
+/* Register: IMXDPUV1_framegen1_FgSFifoFillClr */
+#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR                    ((uint32_t)(0xD48C))
+#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_OFFSET             ((uint32_t)(0x8C))
+#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_RESET_VALUE        0U
+#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_SFIFOFILLCLR_MASK  0x1U
+#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_SFIFOFILLCLR_SHIFT 0U
+
+/* Register: IMXDPUV1_framegen1_FgSrEpD */
+#define IMXDPUV1_FRAMEGEN1_FGSREPD                           ((uint32_t)(0xD490))
+#define IMXDPUV1_FRAMEGEN1_FGSREPD_OFFSET                    ((uint32_t)(0x90))
+#define IMXDPUV1_FRAMEGEN1_FGSREPD_RESET_VALUE               0U
+#define IMXDPUV1_FRAMEGEN1_FGSREPD_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSREPD_EPVAL_MASK                0x1FFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSREPD_EPVAL_SHIFT               0U
+
+/* Register: IMXDPUV1_framegen1_FgSrFtD */
+#define IMXDPUV1_FRAMEGEN1_FGSRFTD                           ((uint32_t)(0xD494))
+#define IMXDPUV1_FRAMEGEN1_FGSRFTD_OFFSET                    ((uint32_t)(0x94))
+#define IMXDPUV1_FRAMEGEN1_FGSRFTD_RESET_VALUE               0U
+#define IMXDPUV1_FRAMEGEN1_FGSRFTD_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSRFTD_FRTOT_MASK                0xFFFFFFFU
+#define IMXDPUV1_FRAMEGEN1_FGSRFTD_FRTOT_SHIFT               0U
+
+/* Register: IMXDPUV1_matrix1_LockUnlock */
+#define IMXDPUV1_MATRIX1_LOCKUNLOCK                          ((uint32_t)(0xD800))
+#define IMXDPUV1_MATRIX1_LOCKUNLOCK_OFFSET                   ((uint32_t)(0))
+#define IMXDPUV1_MATRIX1_LOCKUNLOCK_RESET_VALUE              0U
+#define IMXDPUV1_MATRIX1_LOCKUNLOCK_RESET_MASK               0U
+#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK_MASK          0xFFFFFFFFU
+#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK_SHIFT         0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY     0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY   0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY   0xFBE8B1E6U
+
+/* Register: IMXDPUV1_matrix1_LockStatus */
+#define IMXDPUV1_MATRIX1_LOCKSTATUS                          ((uint32_t)(0xD804))
+#define IMXDPUV1_MATRIX1_LOCKSTATUS_OFFSET                   ((uint32_t)(0x4))
+#define IMXDPUV1_MATRIX1_LOCKSTATUS_RESET_VALUE              0U
+#define IMXDPUV1_MATRIX1_LOCKSTATUS_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_MATRIX1_LOCKSTATUS_LOCKSTATUS_MASK          0x1U
+#define IMXDPUV1_MATRIX1_LOCKSTATUS_LOCKSTATUS_SHIFT         0U
+#define IMXDPUV1_MATRIX1_LOCKSTATUS_PRIVILEGESTATUS_MASK     0x10U
+#define IMXDPUV1_MATRIX1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT    4U
+#define IMXDPUV1_MATRIX1_LOCKSTATUS_FREEZESTATUS_MASK        0x100U
+#define IMXDPUV1_MATRIX1_LOCKSTATUS_FREEZESTATUS_SHIFT       8U
+
+/* Register: IMXDPUV1_matrix1_StaticControl */
+#define IMXDPUV1_MATRIX1_STATICCONTROL                       ((uint32_t)(0xD808))
+#define IMXDPUV1_MATRIX1_STATICCONTROL_OFFSET                ((uint32_t)(0x8))
+#define IMXDPUV1_MATRIX1_STATICCONTROL_RESET_VALUE           0U
+#define IMXDPUV1_MATRIX1_STATICCONTROL_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_MATRIX1_STATICCONTROL_SHDEN_MASK            0x1U
+#define IMXDPUV1_MATRIX1_STATICCONTROL_SHDEN_SHIFT           0U
+
+/* Register: IMXDPUV1_matrix1_Control */
+#define IMXDPUV1_MATRIX1_CONTROL                             ((uint32_t)(0xD80C))
+#define IMXDPUV1_MATRIX1_CONTROL_OFFSET                      ((uint32_t)(0xC))
+#define IMXDPUV1_MATRIX1_CONTROL_RESET_VALUE                 0U
+#define IMXDPUV1_MATRIX1_CONTROL_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_MATRIX1_CONTROL_MODE_MASK                   0x3U
+#define IMXDPUV1_MATRIX1_CONTROL_MODE_SHIFT                  0U
+/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed  */
+#define IMXDPUV1_MATRIX1_CONTROL_MODE__NEUTRAL               0U
+/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied
+ * with matrix values  */
+#define IMXDPUV1_MATRIX1_CONTROL_MODE__MATRIX                0x1U
+/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input
+ * color is multiplied with input alpha  */
+#define IMXDPUV1_MATRIX1_CONTROL_MODE__PREMUL                0x2U
+/* Field Value: MODE__RSVD, Reserved, do not use  */
+#define IMXDPUV1_MATRIX1_CONTROL_MODE__RSVD                  0x3U
+#define IMXDPUV1_MATRIX1_CONTROL_ALPHAMASK_MASK              0x10U
+#define IMXDPUV1_MATRIX1_CONTROL_ALPHAMASK_SHIFT             4U
+#define IMXDPUV1_MATRIX1_CONTROL_ALPHAINVERT_MASK            0x20U
+#define IMXDPUV1_MATRIX1_CONTROL_ALPHAINVERT_SHIFT           5U
+
+/* Register: IMXDPUV1_matrix1_Red0 */
+#define IMXDPUV1_MATRIX1_RED0                                ((uint32_t)(0xD810))
+#define IMXDPUV1_MATRIX1_RED0_OFFSET                         ((uint32_t)(0x10))
+#define IMXDPUV1_MATRIX1_RED0_RESET_VALUE                    0x400U
+#define IMXDPUV1_MATRIX1_RED0_RESET_MASK                     0xFFFFFFFFU
+#define IMXDPUV1_MATRIX1_RED0_A11_MASK                       0x1FFFU
+#define IMXDPUV1_MATRIX1_RED0_A11_SHIFT                      0U
+#define IMXDPUV1_MATRIX1_RED0_A12_MASK                       0x1FFF0000U
+#define IMXDPUV1_MATRIX1_RED0_A12_SHIFT                      16U
+
+/* Register: IMXDPUV1_matrix1_Red1 */
+#define IMXDPUV1_MATRIX1_RED1                                ((uint32_t)(0xD814))
+#define IMXDPUV1_MATRIX1_RED1_OFFSET                         ((uint32_t)(0x14))
+#define IMXDPUV1_MATRIX1_RED1_RESET_VALUE                    0U
+#define IMXDPUV1_MATRIX1_RED1_RESET_MASK                     0xFFFFFFFFU
+#define IMXDPUV1_MATRIX1_RED1_A13_MASK                       0x1FFFU
+#define IMXDPUV1_MATRIX1_RED1_A13_SHIFT                      0U
+#define IMXDPUV1_MATRIX1_RED1_A14_MASK                       0x1FFF0000U
+#define IMXDPUV1_MATRIX1_RED1_A14_SHIFT                      16U
+
+/* Register: IMXDPUV1_matrix1_Green0 */
+#define IMXDPUV1_MATRIX1_GREEN0                              ((uint32_t)(0xD818))
+#define IMXDPUV1_MATRIX1_GREEN0_OFFSET                       ((uint32_t)(0x18))
+#define IMXDPUV1_MATRIX1_GREEN0_RESET_VALUE                  0x4000000U
+#define IMXDPUV1_MATRIX1_GREEN0_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX1_GREEN0_A21_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX1_GREEN0_A21_SHIFT                    0U
+#define IMXDPUV1_MATRIX1_GREEN0_A22_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX1_GREEN0_A22_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix1_Green1 */
+#define IMXDPUV1_MATRIX1_GREEN1                              ((uint32_t)(0xD81C))
+#define IMXDPUV1_MATRIX1_GREEN1_OFFSET                       ((uint32_t)(0x1C))
+#define IMXDPUV1_MATRIX1_GREEN1_RESET_VALUE                  0U
+#define IMXDPUV1_MATRIX1_GREEN1_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX1_GREEN1_A23_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX1_GREEN1_A23_SHIFT                    0U
+#define IMXDPUV1_MATRIX1_GREEN1_A24_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX1_GREEN1_A24_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix1_Blue0 */
+#define IMXDPUV1_MATRIX1_BLUE0                               ((uint32_t)(0xD820))
+#define IMXDPUV1_MATRIX1_BLUE0_OFFSET                        ((uint32_t)(0x20))
+#define IMXDPUV1_MATRIX1_BLUE0_RESET_VALUE                   0U
+#define IMXDPUV1_MATRIX1_BLUE0_RESET_MASK                    0xFFFFFFFFU
+#define IMXDPUV1_MATRIX1_BLUE0_A31_MASK                      0x1FFFU
+#define IMXDPUV1_MATRIX1_BLUE0_A31_SHIFT                     0U
+#define IMXDPUV1_MATRIX1_BLUE0_A32_MASK                      0x1FFF0000U
+#define IMXDPUV1_MATRIX1_BLUE0_A32_SHIFT                     16U
+
+/* Register: IMXDPUV1_matrix1_Blue1 */
+#define IMXDPUV1_MATRIX1_BLUE1                               ((uint32_t)(0xD824))
+#define IMXDPUV1_MATRIX1_BLUE1_OFFSET                        ((uint32_t)(0x24))
+#define IMXDPUV1_MATRIX1_BLUE1_RESET_VALUE                   0x400U
+#define IMXDPUV1_MATRIX1_BLUE1_RESET_MASK                    0xFFFFFFFFU
+#define IMXDPUV1_MATRIX1_BLUE1_A33_MASK                      0x1FFFU
+#define IMXDPUV1_MATRIX1_BLUE1_A33_SHIFT                     0U
+#define IMXDPUV1_MATRIX1_BLUE1_A34_MASK                      0x1FFF0000U
+#define IMXDPUV1_MATRIX1_BLUE1_A34_SHIFT                     16U
+
+/* Register: IMXDPUV1_matrix1_Alpha0 */
+#define IMXDPUV1_MATRIX1_ALPHA0                              ((uint32_t)(0xD828))
+#define IMXDPUV1_MATRIX1_ALPHA0_OFFSET                       ((uint32_t)(0x28))
+#define IMXDPUV1_MATRIX1_ALPHA0_RESET_VALUE                  0U
+#define IMXDPUV1_MATRIX1_ALPHA0_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX1_ALPHA0_A41_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX1_ALPHA0_A41_SHIFT                    0U
+#define IMXDPUV1_MATRIX1_ALPHA0_A42_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX1_ALPHA0_A42_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix1_Alpha1 */
+#define IMXDPUV1_MATRIX1_ALPHA1                              ((uint32_t)(0xD82C))
+#define IMXDPUV1_MATRIX1_ALPHA1_OFFSET                       ((uint32_t)(0x2C))
+#define IMXDPUV1_MATRIX1_ALPHA1_RESET_VALUE                  0x4000000U
+#define IMXDPUV1_MATRIX1_ALPHA1_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_MATRIX1_ALPHA1_A43_MASK                     0x1FFFU
+#define IMXDPUV1_MATRIX1_ALPHA1_A43_SHIFT                    0U
+#define IMXDPUV1_MATRIX1_ALPHA1_A44_MASK                     0x1FFF0000U
+#define IMXDPUV1_MATRIX1_ALPHA1_A44_SHIFT                    16U
+
+/* Register: IMXDPUV1_matrix1_OffsetVector0 */
+#define IMXDPUV1_MATRIX1_OFFSETVECTOR0                       ((uint32_t)(0xD830))
+#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_OFFSET                ((uint32_t)(0x30))
+#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_RESET_VALUE           0U
+#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_C1_MASK               0x1FFFU
+#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_C1_SHIFT              0U
+#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_C2_MASK               0x1FFF0000U
+#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_C2_SHIFT              16U
+
+/* Register: IMXDPUV1_matrix1_OffsetVector1 */
+#define IMXDPUV1_MATRIX1_OFFSETVECTOR1                       ((uint32_t)(0xD834))
+#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_OFFSET                ((uint32_t)(0x34))
+#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_RESET_VALUE           0U
+#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_C3_MASK               0x1FFFU
+#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_C3_SHIFT              0U
+#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_C4_MASK               0x1FFF0000U
+#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_C4_SHIFT              16U
+
+/* Register: IMXDPUV1_matrix1_LastControlWord */
+#define IMXDPUV1_MATRIX1_LASTCONTROLWORD                     ((uint32_t)(0xD838))
+#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_OFFSET              ((uint32_t)(0x38))
+#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_RESET_VALUE         0U
+#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_RESET_MASK          0U
+#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_L_VAL_MASK          0xFFFFFFFFU
+#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_L_VAL_SHIFT         0U
+
+/* Register: IMXDPUV1_gammacor1_LockUnlock */
+#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK                        ((uint32_t)(0xDC00))
+#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_OFFSET                 ((uint32_t)(0))
+#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_RESET_VALUE            0U
+#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_RESET_MASK             0U
+#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK_MASK        0xFFFFFFFFU
+#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK_SHIFT       0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY   0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U
+
+/* Register: IMXDPUV1_gammacor1_LockStatus */
+#define IMXDPUV1_GAMMACOR1_LOCKSTATUS                        ((uint32_t)(0xDC04))
+#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_OFFSET                 ((uint32_t)(0x4))
+#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_RESET_VALUE            0U
+#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_LOCKSTATUS_MASK        0x1U
+#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_LOCKSTATUS_SHIFT       0U
+#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_PRIVILEGESTATUS_MASK   0x10U
+#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT  4U
+#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_FREEZESTATUS_MASK      0x100U
+#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_FREEZESTATUS_SHIFT     8U
+
+/* Register: IMXDPUV1_gammacor1_StaticControl */
+#define IMXDPUV1_GAMMACOR1_STATICCONTROL                     ((uint32_t)(0xDC08))
+#define IMXDPUV1_GAMMACOR1_STATICCONTROL_OFFSET              ((uint32_t)(0x8))
+#define IMXDPUV1_GAMMACOR1_STATICCONTROL_RESET_VALUE         0xEU
+#define IMXDPUV1_GAMMACOR1_STATICCONTROL_RESET_MASK          0xFFFFFFFFU
+#define IMXDPUV1_GAMMACOR1_STATICCONTROL_SHDEN_MASK          0x1U
+#define IMXDPUV1_GAMMACOR1_STATICCONTROL_SHDEN_SHIFT         0U
+#define IMXDPUV1_GAMMACOR1_STATICCONTROL_BLUEWRITEENABLE_MASK 0x2U
+#define IMXDPUV1_GAMMACOR1_STATICCONTROL_BLUEWRITEENABLE_SHIFT 1U
+#define IMXDPUV1_GAMMACOR1_STATICCONTROL_GREENWRITEENABLE_MASK 0x4U
+#define IMXDPUV1_GAMMACOR1_STATICCONTROL_GREENWRITEENABLE_SHIFT 2U
+#define IMXDPUV1_GAMMACOR1_STATICCONTROL_REDWRITEENABLE_MASK 0x8U
+#define IMXDPUV1_GAMMACOR1_STATICCONTROL_REDWRITEENABLE_SHIFT 3U
+
+/* Register: IMXDPUV1_gammacor1_LutStart */
+#define IMXDPUV1_GAMMACOR1_LUTSTART                          ((uint32_t)(0xDC0C))
+#define IMXDPUV1_GAMMACOR1_LUTSTART_OFFSET                   ((uint32_t)(0xC))
+#define IMXDPUV1_GAMMACOR1_LUTSTART_RESET_VALUE              0U
+#define IMXDPUV1_GAMMACOR1_LUTSTART_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTBLUE_MASK           0x3FFU
+#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTBLUE_SHIFT          0U
+#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTGREEN_MASK          0xFFC00U
+#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTGREEN_SHIFT         10U
+#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTRED_MASK            0x3FF00000U
+#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTRED_SHIFT           20U
+
+/* Register: IMXDPUV1_gammacor1_LutDeltas */
+#define IMXDPUV1_GAMMACOR1_LUTDELTAS                         ((uint32_t)(0xDC10))
+#define IMXDPUV1_GAMMACOR1_LUTDELTAS_OFFSET                  ((uint32_t)(0x10))
+#define IMXDPUV1_GAMMACOR1_LUTDELTAS_RESET_VALUE             0U
+#define IMXDPUV1_GAMMACOR1_LUTDELTAS_RESET_MASK              0xC0000000U
+#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTABLUE_MASK          0x3FFU
+#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTABLUE_SHIFT         0U
+#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTAGREEN_MASK         0xFFC00U
+#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTAGREEN_SHIFT        10U
+#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTARED_MASK           0x3FF00000U
+#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTARED_SHIFT          20U
+
+/* Register: IMXDPUV1_gammacor1_Control */
+#define IMXDPUV1_GAMMACOR1_CONTROL                           ((uint32_t)(0xDC14))
+#define IMXDPUV1_GAMMACOR1_CONTROL_OFFSET                    ((uint32_t)(0x14))
+#define IMXDPUV1_GAMMACOR1_CONTROL_RESET_VALUE               0U
+#define IMXDPUV1_GAMMACOR1_CONTROL_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_GAMMACOR1_CONTROL_MODE_MASK                 0x1U
+#define IMXDPUV1_GAMMACOR1_CONTROL_MODE_SHIFT                0U
+/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed
+ * to the output.  */
+#define IMXDPUV1_GAMMACOR1_CONTROL_MODE__NEUTRAL             0U
+/* Field Value: MODE__GAMMACOR, Module in gamma correction mode.  */
+#define IMXDPUV1_GAMMACOR1_CONTROL_MODE__GAMMACOR            0x1U
+#define IMXDPUV1_GAMMACOR1_CONTROL_ALPHAMASK_MASK            0x10U
+#define IMXDPUV1_GAMMACOR1_CONTROL_ALPHAMASK_SHIFT           4U
+#define IMXDPUV1_GAMMACOR1_CONTROL_ALPHAINVERT_MASK          0x20U
+#define IMXDPUV1_GAMMACOR1_CONTROL_ALPHAINVERT_SHIFT         5U
+
+/* Register: IMXDPUV1_gammacor1_Status */
+#define IMXDPUV1_GAMMACOR1_STATUS                            ((uint32_t)(0xDC18))
+#define IMXDPUV1_GAMMACOR1_STATUS_OFFSET                     ((uint32_t)(0x18))
+#define IMXDPUV1_GAMMACOR1_STATUS_RESET_VALUE                0U
+#define IMXDPUV1_GAMMACOR1_STATUS_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_GAMMACOR1_STATUS_WRITETIMEOUT_MASK          0x1U
+#define IMXDPUV1_GAMMACOR1_STATUS_WRITETIMEOUT_SHIFT         0U
+
+/* Register: IMXDPUV1_gammacor1_LastControlWord */
+#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD                   ((uint32_t)(0xDC1C))
+#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_OFFSET            ((uint32_t)(0x1C))
+#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_RESET_VALUE       0U
+#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_RESET_MASK        0U
+#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_L_VAL_MASK        0xFFFFFFFFU
+#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_L_VAL_SHIFT       0U
+
+/* Register: IMXDPUV1_dither1_LockUnlock */
+#define IMXDPUV1_DITHER1_LOCKUNLOCK                          ((uint32_t)(0xE000))
+#define IMXDPUV1_DITHER1_LOCKUNLOCK_OFFSET                   ((uint32_t)(0))
+#define IMXDPUV1_DITHER1_LOCKUNLOCK_RESET_VALUE              0U
+#define IMXDPUV1_DITHER1_LOCKUNLOCK_RESET_MASK               0U
+#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK_MASK          0xFFFFFFFFU
+#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK_SHIFT         0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY     0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY   0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY   0xFBE8B1E6U
+
+/* Register: IMXDPUV1_dither1_LockStatus */
+#define IMXDPUV1_DITHER1_LOCKSTATUS                          ((uint32_t)(0xE004))
+#define IMXDPUV1_DITHER1_LOCKSTATUS_OFFSET                   ((uint32_t)(0x4))
+#define IMXDPUV1_DITHER1_LOCKSTATUS_RESET_VALUE              0U
+#define IMXDPUV1_DITHER1_LOCKSTATUS_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_DITHER1_LOCKSTATUS_LOCKSTATUS_MASK          0x1U
+#define IMXDPUV1_DITHER1_LOCKSTATUS_LOCKSTATUS_SHIFT         0U
+#define IMXDPUV1_DITHER1_LOCKSTATUS_PRIVILEGESTATUS_MASK     0x10U
+#define IMXDPUV1_DITHER1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT    4U
+#define IMXDPUV1_DITHER1_LOCKSTATUS_FREEZESTATUS_MASK        0x100U
+#define IMXDPUV1_DITHER1_LOCKSTATUS_FREEZESTATUS_SHIFT       8U
+
+/* Register: IMXDPUV1_dither1_Control */
+#define IMXDPUV1_DITHER1_CONTROL                             ((uint32_t)(0xE008))
+#define IMXDPUV1_DITHER1_CONTROL_OFFSET                      ((uint32_t)(0x8))
+#define IMXDPUV1_DITHER1_CONTROL_RESET_VALUE                 0U
+#define IMXDPUV1_DITHER1_CONTROL_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_DITHER1_CONTROL_MODE_MASK                   0x1U
+#define IMXDPUV1_DITHER1_CONTROL_MODE_SHIFT                  0U
+/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the Dither Unit,
+ * all other settings are ignored.  */
+#define IMXDPUV1_DITHER1_CONTROL_MODE__NEUTRAL               0U
+/* Field Value: MODE__ACTIVE, Dither Unit is active.  */
+#define IMXDPUV1_DITHER1_CONTROL_MODE__ACTIVE                0x1U
+
+/* Register: IMXDPUV1_dither1_DitherControl */
+#define IMXDPUV1_DITHER1_DITHERCONTROL                       ((uint32_t)(0xE00C))
+#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET                ((uint32_t)(0xC))
+#define IMXDPUV1_DITHER1_DITHERCONTROL_RESET_VALUE           0x300222U
+#define IMXDPUV1_DITHER1_DITHERCONTROL_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT_MASK 0x7U
+#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT_SHIFT 0U
+/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO8, Reduces blue component width
+ * from 10 bit to 8bit.  */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO8 0x2U
+/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO7, Reduces blue component width
+ * from 10 bit to 7bit.  */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO7 0x3U
+/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO6, Reduces blue component width
+ * from 10 bit to 6bit.  */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO6 0x4U
+/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO5, Reduces blue component width
+ * from 10 bit to 5bit.  */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO5 0x5U
+#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT_MASK 0x70U
+#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT_SHIFT 4U
+/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO8, Reduces green component width
+ * from 10 bit to 8bit.  */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO8 0x2U
+/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO7, Reduces green component width
+ * from 10 bit to 7bit.  */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO7 0x3U
+/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO6, Reduces green component width
+ * from 10 bit to 6bit.  */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO6 0x4U
+/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO5, Reduces green component width
+ * from 10 bit to 5bit.  */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO5 0x5U
+#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT_MASK 0x700U
+#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT_SHIFT 8U
+/* Field Value: RED_RANGE_SELECT__RED_10TO8, Reduces red component width from
+ * 10 bit to 8bit.  */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO8 0x2U
+/* Field Value: RED_RANGE_SELECT__RED_10TO7, Reduces red component width from
+ * 10 bit to 7bit.  */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO7 0x3U
+/* Field Value: RED_RANGE_SELECT__RED_10TO6, Reduces red component width from
+ * 10 bit to 6bit.  */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO6 0x4U
+/* Field Value: RED_RANGE_SELECT__RED_10TO5, Reduces red component width from
+ * 10 bit to 5bit.  */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO5 0x5U
+#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET_SELECT_MASK    0x10000U
+#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET_SELECT_SHIFT   16U
+/* Field Value: OFFSET_SELECT__OFFS_SPATIAL, Offset is a bayer matrix value,
+ * which is selected according to pixel frame position.  */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET_SELECT__OFFS_SPATIAL 0U
+/* Field Value: OFFSET_SELECT__OFFS_TEMPORAL, Offset is the sum from a bayer
+ * matrix value, which is selected according to pixel frame position,
+ * and a value from a regular sequence, which changes each frame.   */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET_SELECT__OFFS_TEMPORAL 0x1U
+#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT_MASK      0x300000U
+#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT_SHIFT     20U
+/* Field Value: ALGO_SELECT__NO_CORRECTION, Best possible resolution for most
+ * dark colors. Adds a diminutive offset to overall image brightness.  */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT__NO_CORRECTION 0x1U
+/* Field Value: ALGO_SELECT__BRIGHTNESS_CORRECTION, Preserves overall image
+ * brightness. Cannot resolve most dark and most bright colors. All codes
+ * in-between are distributed perfectly smooth.  */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT__BRIGHTNESS_CORRECTION 0x2U
+/* Field Value: ALGO_SELECT__CONTRAST_CORRECTION, Preserves overall image
+ * brightness. Best possible distribution of color codes over complete range.  */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT__CONTRAST_CORRECTION 0x3U
+#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE_MASK       0x3000000U
+#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE_SHIFT      24U
+/* Field Value: ALPHA_MODE__DISABLE, The alpha bit is not considered.  */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE__DISABLE   0U
+/* Field Value: ALPHA_MODE__ENABLE_BY1, Red, green and blue components are
+ * only dithered, if the alpha bit is 1.  */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE__ENABLE_BY1 0x1U
+/* Field Value: ALPHA_MODE__ENABLE_BY0, Red, green and blue components are
+ * only dithered, if the alpha bit is 0.  */
+#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE__ENABLE_BY0 0x2U
+
+/* Register: IMXDPUV1_dither1_Release */
+#define IMXDPUV1_DITHER1_RELEASE                             ((uint32_t)(0xE010))
+#define IMXDPUV1_DITHER1_RELEASE_OFFSET                      ((uint32_t)(0x10))
+#define IMXDPUV1_DITHER1_RELEASE_RESET_VALUE                 0U
+#define IMXDPUV1_DITHER1_RELEASE_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_DITHER1_RELEASE_SUBVERSION_MASK             0xFFU
+#define IMXDPUV1_DITHER1_RELEASE_SUBVERSION_SHIFT            0U
+#define IMXDPUV1_DITHER1_RELEASE_VERSION_MASK                0xFF00U
+#define IMXDPUV1_DITHER1_RELEASE_VERSION_SHIFT               8U
+
+/* Register: IMXDPUV1_tcon1_SSqCnts */
+#define IMXDPUV1_TCON1_SSQCNTS                               ((uint32_t)(0xE400))
+#define IMXDPUV1_TCON1_SSQCNTS_OFFSET                        ((uint32_t)(0))
+#define IMXDPUV1_TCON1_SSQCNTS_RESET_VALUE                   0U
+#define IMXDPUV1_TCON1_SSQCNTS_RESET_MASK                    0U
+#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_SEQY_MASK             0x7FFFU
+#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_SEQY_SHIFT            0U
+#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_FIELD_MASK            0x8000U
+#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_FIELD_SHIFT           15U
+#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_SEQX_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_SEQX_SHIFT            16U
+#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_OUT_MASK              0x80000000U
+#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_OUT_SHIFT             31U
+
+/* Register: IMXDPUV1_tcon1_LockUnlock */
+#define IMXDPUV1_TCON1_LOCKUNLOCK                            ((uint32_t)(0xE800))
+#define IMXDPUV1_TCON1_LOCKUNLOCK_OFFSET                     ((uint32_t)(0))
+#define IMXDPUV1_TCON1_LOCKUNLOCK_RESET_VALUE                0U
+#define IMXDPUV1_TCON1_LOCKUNLOCK_RESET_MASK                 0U
+#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK_MASK            0xFFFFFFFFU
+#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK_SHIFT           0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY       0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY     0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY  0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY     0xFBE8B1E6U
+
+/* Register: IMXDPUV1_tcon1_LockStatus */
+#define IMXDPUV1_TCON1_LOCKSTATUS                            ((uint32_t)(0xE804))
+#define IMXDPUV1_TCON1_LOCKSTATUS_OFFSET                     ((uint32_t)(0x4))
+#define IMXDPUV1_TCON1_LOCKSTATUS_RESET_VALUE                0U
+#define IMXDPUV1_TCON1_LOCKSTATUS_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_LOCKSTATUS_LOCKSTATUS_MASK            0x1U
+#define IMXDPUV1_TCON1_LOCKSTATUS_LOCKSTATUS_SHIFT           0U
+#define IMXDPUV1_TCON1_LOCKSTATUS_PRIVILEGESTATUS_MASK       0x10U
+#define IMXDPUV1_TCON1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT      4U
+#define IMXDPUV1_TCON1_LOCKSTATUS_FREEZESTATUS_MASK          0x100U
+#define IMXDPUV1_TCON1_LOCKSTATUS_FREEZESTATUS_SHIFT         8U
+
+/* Register: IMXDPUV1_tcon1_SSqCycle */
+#define IMXDPUV1_TCON1_SSQCYCLE                              ((uint32_t)(0xE808))
+#define IMXDPUV1_TCON1_SSQCYCLE_OFFSET                       ((uint32_t)(0x8))
+#define IMXDPUV1_TCON1_SSQCYCLE_RESET_VALUE                  0U
+#define IMXDPUV1_TCON1_SSQCYCLE_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SSQCYCLE_SSQCYCLE_MASK                0x3FU
+#define IMXDPUV1_TCON1_SSQCYCLE_SSQCYCLE_SHIFT               0U
+
+/* Register: IMXDPUV1_tcon1_SWreset */
+#define IMXDPUV1_TCON1_SWRESET                               ((uint32_t)(0xE80C))
+#define IMXDPUV1_TCON1_SWRESET_OFFSET                        ((uint32_t)(0xC))
+#define IMXDPUV1_TCON1_SWRESET_RESET_VALUE                   0x3FC00410U
+#define IMXDPUV1_TCON1_SWRESET_RESET_MASK                    0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SWRESET_SWRESET_MASK                  0x1U
+#define IMXDPUV1_TCON1_SWRESET_SWRESET_SHIFT                 0U
+/* Field Value: SWRESET__OPERATION, operation mode  */
+#define IMXDPUV1_TCON1_SWRESET_SWRESET__OPERATION            0U
+/* Field Value: SWRESET__SWRESET, So long SWReset = 0x1 tcon is in 'SW reset
+ * state' and it is released by internal logic (SWReset is released and
+ * end of frame arrived), read: 0b: reset not active 1b: reset active (that
+ * means NO pixel of video frame is excepted until 'SW reset state'
+ * is released)  */
+#define IMXDPUV1_TCON1_SWRESET_SWRESET__SWRESET              0x1U
+#define IMXDPUV1_TCON1_SWRESET_ENRESETWORD_MASK              0xFFF0U
+#define IMXDPUV1_TCON1_SWRESET_ENRESETWORD_SHIFT             4U
+#define IMXDPUV1_TCON1_SWRESET_RESETWORDEND_MASK             0xFF0000U
+#define IMXDPUV1_TCON1_SWRESET_RESETWORDEND_SHIFT            16U
+#define IMXDPUV1_TCON1_SWRESET_RESETWORDSTART_MASK           0xFF000000U
+#define IMXDPUV1_TCON1_SWRESET_RESETWORDSTART_SHIFT          24U
+
+/* Register: IMXDPUV1_tcon1_TCON_CTRL */
+#define IMXDPUV1_TCON1_TCON_CTRL                             ((uint32_t)(0xE810))
+#define IMXDPUV1_TCON1_TCON_CTRL_OFFSET                      ((uint32_t)(0x10))
+#define IMXDPUV1_TCON1_TCON_CTRL_RESET_VALUE                 0x1401408U
+#define IMXDPUV1_TCON1_TCON_CTRL_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE_MASK            0x3U
+#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE_SHIFT           0U
+/* Field Value: CHANNELMODE__SINGLE, Single pixel mode. Both channels channel
+ * are active at full pixel clock. If bitmap of both panels are the same,
+ * both panels are identical  */
+#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE__SINGLE         0U
+/* Field Value: CHANNELMODE__DUAL_INTERLEAVED, Dual pixel mode. Both channels
+ * are active at half the pixel clock. 1st channel drives display columns
+ * with even and 2nd one with odd index.  */
+#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE__DUAL_INTERLEAVED 0x1U
+/* Field Value: CHANNELMODE__DUAL_SPLIT, Dual pixel mode. Both channels are
+ * active at half the pixel clock. 1st channel drives the left and 2nd
+ * one the righ half of the display. Note : data_en is needed in this mode  */
+#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE__DUAL_SPLIT     0x2U
+#define IMXDPUV1_TCON1_TCON_CTRL_TCON_SYNC_MASK              0x4U
+#define IMXDPUV1_TCON1_TCON_CTRL_TCON_SYNC_SHIFT             2U
+/* Field Value: TCON_SYNC__H_VLAST, tcon timing generator synchronized to
+ * hlast, vlast  */
+#define IMXDPUV1_TCON1_TCON_CTRL_TCON_SYNC__H_VLAST          0U
+/* Field Value: TCON_SYNC__H_VSYNC, tcon timing generator synchronized to
+ * hsync, vsync where horizontal synchronization is synchronized at the falling
+ * edge of hsync  */
+#define IMXDPUV1_TCON1_TCON_CTRL_TCON_SYNC__H_VSYNC          0x1U
+#define IMXDPUV1_TCON1_TCON_CTRL_BYPASS_MASK                 0x8U
+#define IMXDPUV1_TCON1_TCON_CTRL_BYPASS_SHIFT                3U
+/* Field Value: BYPASS__TCON_MODE, tcon operation mode  */
+#define IMXDPUV1_TCON1_TCON_CTRL_BYPASS__TCON_MODE           0U
+/* Field Value: BYPASS__BYPASS_MODE, tcon in Bypass mode. input pixel and
+ * its sync-signals are bypassed to tcon-output  */
+#define IMXDPUV1_TCON1_TCON_CTRL_BYPASS__BYPASS_MODE         0x1U
+#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL_MASK               0xF0U
+#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL_SHIFT              4U
+/* Field Value: INV_CTRL__DISABLE, Disable inversion control  */
+#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__DISABLE           0U
+/* Field Value: INV_CTRL__RGB_2_BITS, Enable inversion control for number
+ * of RGB-Bits = 2  */
+#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_2_BITS        0x1U
+/* Field Value: INV_CTRL__RGB_4_BITS, Enable inversion control for number
+ * of RGB-Bits = 4  */
+#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_4_BITS        0x2U
+/* Field Value: INV_CTRL__RGB_6_BITS, Enable inversion control for number
+ * of RGB-Bits = 6  */
+#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_6_BITS        0x3U
+/* Field Value: INV_CTRL__RGB_8_BITS, Enable inversion control for number
+ * of RGB-Bits = 8  */
+#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_8_BITS        0x4U
+/* Field Value: INV_CTRL__RGB_10_BITS, Enable inversion control for number
+ * of RGB-Bits = 10  */
+#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_10_BITS       0x5U
+/* Field Value: INV_CTRL__RGB_12_BITS, Enable inversion control for number
+ * of RGB-Bits = 12  */
+#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_12_BITS       0x6U
+/* Field Value: INV_CTRL__RGB_14_BITS, Enable inversion control for number
+ * of RGB-Bits = 14  */
+#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_14_BITS       0x7U
+/* Field Value: INV_CTRL__RGB_16_BITS, Enable inversion control for number
+ * of RGB-Bits = 16  */
+#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_16_BITS       0x8U
+/* Field Value: INV_CTRL__RGB_18_BITS, Enable inversion control for number
+ * of RGB-Bits = 18  */
+#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_18_BITS       0x9U
+/* Field Value: INV_CTRL__RGB_20_BITS, Enable inversion control for number
+ * of RGB-Bits = 20  */
+#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_20_BITS       0xAU
+/* Field Value: INV_CTRL__RGB_22_BITS, Enable inversion control for number
+ * of RGB-Bits = 22  */
+#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_22_BITS       0xBU
+/* Field Value: INV_CTRL__RGB_24_BITS, Enable inversion control for number
+ * of RGB-Bits = 24  */
+#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_24_BITS       0xCU
+/* Field Value: INV_CTRL__RGB_26_BITS, Enable inversion control for number
+ * of RGB-Bits = 26  */
+#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_26_BITS       0xDU
+/* Field Value: INV_CTRL__RGB_28_BITS, Enable inversion control for number
+ * of RGB-Bits = 28  */
+#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_28_BITS       0xEU
+/* Field Value: INV_CTRL__RGB_30_BITS, Enable inversion control for number
+ * of RGB-Bits = 30  */
+#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_30_BITS       0xFU
+#define IMXDPUV1_TCON1_TCON_CTRL_ENLVDS_MASK                 0x100U
+#define IMXDPUV1_TCON1_TCON_CTRL_ENLVDS_SHIFT                8U
+/* Field Value: ENLVDS__ENABLE_LVDS, Enable LVDS , TTL and RSDS are disable
+ *   */
+#define IMXDPUV1_TCON1_TCON_CTRL_ENLVDS__ENABLE_LVDS         0x1U
+/* Field Value: ENLVDS__DISABLE_LVDS, Disable LVDS, Enable TTL and RSDS   */
+#define IMXDPUV1_TCON1_TCON_CTRL_ENLVDS__DISABLE_LVDS        0U
+#define IMXDPUV1_TCON1_TCON_CTRL_LVDSMODE_MASK               0x200U
+#define IMXDPUV1_TCON1_TCON_CTRL_LVDSMODE_SHIFT              9U
+/* Field Value: LVDSMODE__MINI_LVDS, MiniLVDS   */
+#define IMXDPUV1_TCON1_TCON_CTRL_LVDSMODE__MINI_LVDS         0x1U
+/* Field Value: LVDSMODE__LVDS, LVDS Mode, refered to OpenLDI   */
+#define IMXDPUV1_TCON1_TCON_CTRL_LVDSMODE__LVDS              0U
+#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_BALANCE_MASK           0x400U
+#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_BALANCE_SHIFT          10U
+/* Field Value: LVDS_BALANCE__BALANCED, LVDS operates in 24 bits Balanced
+ * Mode   */
+#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_BALANCE__BALANCED      0x1U
+/* Field Value: LVDS_BALANCE__UNBALANCED, LVDS operates in 24 bits Unbalanced
+ * Mode   */
+#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_BALANCE__UNBALANCED    0U
+#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_CLOCK_INV_MASK         0x800U
+#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_CLOCK_INV_SHIFT        11U
+/* Field Value: LVDS_CLOCK_INV__INV, Invert LVDS Clock   */
+#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_CLOCK_INV__INV         0x1U
+/* Field Value: LVDS_CLOCK_INV__NON_INV, NON-Invert LVDS Clock   */
+#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_CLOCK_INV__NON_INV     0U
+#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE_MASK        0x7000U
+#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE_SHIFT       12U
+/* Field Value: MINILVDS_OPCODE__MODE_3PAIRS, MiniLVDS operates in 6 and 8
+ * bit data, three pairs   */
+#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__MODE_3PAIRS 0U
+/* Field Value: MINILVDS_OPCODE__MODE_4PAIRS, Not Implemented   */
+#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__MODE_4PAIRS 0x1U
+/* Field Value: MINILVDS_OPCODE__MODE_5PAIRS, Not Implemented   */
+#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__MODE_5PAIRS 0x2U
+/* Field Value: MINILVDS_OPCODE__MODE_6PAIRS, MiniLVDS operates in 6 and 8
+ * bit data, six pairs   */
+#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__MODE_6PAIRS 0x3U
+/* Field Value: MINILVDS_OPCODE__RESERVED1, RESERVED1  */
+#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__RESERVED1  0x4U
+/* Field Value: MINILVDS_OPCODE__RESERVED2, RESERVED2  */
+#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__RESERVED2  0x5U
+/* Field Value: MINILVDS_OPCODE__RESERVED3, RESERVED3  */
+#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__RESERVED3  0x6U
+/* Field Value: MINILVDS_OPCODE__RESERVED4, RESERVED4  */
+#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__RESERVED4  0x7U
+#define IMXDPUV1_TCON1_TCON_CTRL_DUAL_SWAP_MASK              0x8000U
+#define IMXDPUV1_TCON1_TCON_CTRL_DUAL_SWAP_SHIFT             15U
+/* Field Value: DUAL_SWAP__SWAP, swapping pixels between lower-channel and
+ * upper-channel  */
+#define IMXDPUV1_TCON1_TCON_CTRL_DUAL_SWAP__SWAP             0x1U
+/* Field Value: DUAL_SWAP__NON_SWAP, NON-swapping pixels between lower-channel
+ * and upper-channel   */
+#define IMXDPUV1_TCON1_TCON_CTRL_DUAL_SWAP__NON_SWAP         0U
+#define IMXDPUV1_TCON1_TCON_CTRL_SPLITPOSITION_MASK          0x3FFF0000U
+#define IMXDPUV1_TCON1_TCON_CTRL_SPLITPOSITION_SHIFT         16U
+
+/* Register: IMXDPUV1_tcon1_RSDSInvCtrl */
+#define IMXDPUV1_TCON1_RSDSINVCTRL                           ((uint32_t)(0xE814))
+#define IMXDPUV1_TCON1_RSDSINVCTRL_OFFSET                    ((uint32_t)(0x14))
+#define IMXDPUV1_TCON1_RSDSINVCTRL_RESET_VALUE               0U
+#define IMXDPUV1_TCON1_RSDSINVCTRL_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_RSDSINVCTRL_RSDS_INV_MASK             0x7FFFU
+#define IMXDPUV1_TCON1_RSDSINVCTRL_RSDS_INV_SHIFT            0U
+#define IMXDPUV1_TCON1_RSDSINVCTRL_RSDS_INV_DUAL_MASK        0x7FFF0000U
+#define IMXDPUV1_TCON1_RSDSINVCTRL_RSDS_INV_DUAL_SHIFT       16U
+
+/* Register: IMXDPUV1_tcon1_MapBit3_0 */
+#define IMXDPUV1_TCON1_MAPBIT3_0                             ((uint32_t)(0xE818))
+#define IMXDPUV1_TCON1_MAPBIT3_0_OFFSET                      ((uint32_t)(0x18))
+#define IMXDPUV1_TCON1_MAPBIT3_0_RESET_VALUE                 0x3020100U
+#define IMXDPUV1_TCON1_MAPBIT3_0_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT0_MASK                0x3FU
+#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT0_SHIFT               0U
+#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT1_MASK                0x3F00U
+#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT1_SHIFT               8U
+#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT2_MASK                0x3F0000U
+#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT2_SHIFT               16U
+#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT3_MASK                0x3F000000U
+#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT3_SHIFT               24U
+
+/* Register: IMXDPUV1_tcon1_MapBit7_4 */
+#define IMXDPUV1_TCON1_MAPBIT7_4                             ((uint32_t)(0xE81C))
+#define IMXDPUV1_TCON1_MAPBIT7_4_OFFSET                      ((uint32_t)(0x1C))
+#define IMXDPUV1_TCON1_MAPBIT7_4_RESET_VALUE                 0x7060504U
+#define IMXDPUV1_TCON1_MAPBIT7_4_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT4_MASK                0x3FU
+#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT4_SHIFT               0U
+#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT5_MASK                0x3F00U
+#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT5_SHIFT               8U
+#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT6_MASK                0x3F0000U
+#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT6_SHIFT               16U
+#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT7_MASK                0x3F000000U
+#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT7_SHIFT               24U
+
+/* Register: IMXDPUV1_tcon1_MapBit11_8 */
+#define IMXDPUV1_TCON1_MAPBIT11_8                            ((uint32_t)(0xE820))
+#define IMXDPUV1_TCON1_MAPBIT11_8_OFFSET                     ((uint32_t)(0x20))
+#define IMXDPUV1_TCON1_MAPBIT11_8_RESET_VALUE                0xB0A0908U
+#define IMXDPUV1_TCON1_MAPBIT11_8_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT8_MASK               0x3FU
+#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT8_SHIFT              0U
+#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT9_MASK               0x3F00U
+#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT9_SHIFT              8U
+#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT10_MASK              0x3F0000U
+#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT10_SHIFT             16U
+#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT11_MASK              0x3F000000U
+#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT11_SHIFT             24U
+
+/* Register: IMXDPUV1_tcon1_MapBit15_12 */
+#define IMXDPUV1_TCON1_MAPBIT15_12                           ((uint32_t)(0xE824))
+#define IMXDPUV1_TCON1_MAPBIT15_12_OFFSET                    ((uint32_t)(0x24))
+#define IMXDPUV1_TCON1_MAPBIT15_12_RESET_VALUE               0xF0E0D0CU
+#define IMXDPUV1_TCON1_MAPBIT15_12_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT12_MASK             0x3FU
+#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT12_SHIFT            0U
+#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT13_MASK             0x3F00U
+#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT13_SHIFT            8U
+#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT14_MASK             0x3F0000U
+#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT14_SHIFT            16U
+#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT15_MASK             0x3F000000U
+#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT15_SHIFT            24U
+
+/* Register: IMXDPUV1_tcon1_MapBit19_16 */
+#define IMXDPUV1_TCON1_MAPBIT19_16                           ((uint32_t)(0xE828))
+#define IMXDPUV1_TCON1_MAPBIT19_16_OFFSET                    ((uint32_t)(0x28))
+#define IMXDPUV1_TCON1_MAPBIT19_16_RESET_VALUE               0x13121110U
+#define IMXDPUV1_TCON1_MAPBIT19_16_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT16_MASK             0x3FU
+#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT16_SHIFT            0U
+#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT17_MASK             0x3F00U
+#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT17_SHIFT            8U
+#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT18_MASK             0x3F0000U
+#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT18_SHIFT            16U
+#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT19_MASK             0x3F000000U
+#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT19_SHIFT            24U
+
+/* Register: IMXDPUV1_tcon1_MapBit23_20 */
+#define IMXDPUV1_TCON1_MAPBIT23_20                           ((uint32_t)(0xE82C))
+#define IMXDPUV1_TCON1_MAPBIT23_20_OFFSET                    ((uint32_t)(0x2C))
+#define IMXDPUV1_TCON1_MAPBIT23_20_RESET_VALUE               0x17161514U
+#define IMXDPUV1_TCON1_MAPBIT23_20_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT20_MASK             0x3FU
+#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT20_SHIFT            0U
+#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT21_MASK             0x3F00U
+#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT21_SHIFT            8U
+#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT22_MASK             0x3F0000U
+#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT22_SHIFT            16U
+#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT23_MASK             0x3F000000U
+#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT23_SHIFT            24U
+
+/* Register: IMXDPUV1_tcon1_MapBit27_24 */
+#define IMXDPUV1_TCON1_MAPBIT27_24                           ((uint32_t)(0xE830))
+#define IMXDPUV1_TCON1_MAPBIT27_24_OFFSET                    ((uint32_t)(0x30))
+#define IMXDPUV1_TCON1_MAPBIT27_24_RESET_VALUE               0x1B1A1918U
+#define IMXDPUV1_TCON1_MAPBIT27_24_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT24_MASK             0x3FU
+#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT24_SHIFT            0U
+#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT25_MASK             0x3F00U
+#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT25_SHIFT            8U
+#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT26_MASK             0x3F0000U
+#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT26_SHIFT            16U
+#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT27_MASK             0x3F000000U
+#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT27_SHIFT            24U
+
+/* Register: IMXDPUV1_tcon1_MapBit31_28 */
+#define IMXDPUV1_TCON1_MAPBIT31_28                           ((uint32_t)(0xE834))
+#define IMXDPUV1_TCON1_MAPBIT31_28_OFFSET                    ((uint32_t)(0x34))
+#define IMXDPUV1_TCON1_MAPBIT31_28_RESET_VALUE               0x1F1E1D1CU
+#define IMXDPUV1_TCON1_MAPBIT31_28_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT28_MASK             0x3FU
+#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT28_SHIFT            0U
+#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT29_MASK             0x3F00U
+#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT29_SHIFT            8U
+#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT30_MASK             0x3F0000U
+#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT30_SHIFT            16U
+#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT31_MASK             0x3F000000U
+#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT31_SHIFT            24U
+
+/* Register: IMXDPUV1_tcon1_MapBit34_32 */
+#define IMXDPUV1_TCON1_MAPBIT34_32                           ((uint32_t)(0xE838))
+#define IMXDPUV1_TCON1_MAPBIT34_32_OFFSET                    ((uint32_t)(0x38))
+#define IMXDPUV1_TCON1_MAPBIT34_32_RESET_VALUE               0x222120U
+#define IMXDPUV1_TCON1_MAPBIT34_32_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT32_MASK             0x3FU
+#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT32_SHIFT            0U
+#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT33_MASK             0x3F00U
+#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT33_SHIFT            8U
+#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT34_MASK             0x3F0000U
+#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT34_SHIFT            16U
+
+/* Register: IMXDPUV1_tcon1_MapBit3_0_Dual */
+#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL                        ((uint32_t)(0xE83C))
+#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_OFFSET                 ((uint32_t)(0x3C))
+#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_RESET_VALUE            0x3020100U
+#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT0_DUAL_MASK      0x3FU
+#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT0_DUAL_SHIFT     0U
+#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT1_DUAL_MASK      0x3F00U
+#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT1_DUAL_SHIFT     8U
+#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT2_DUAL_MASK      0x3F0000U
+#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT2_DUAL_SHIFT     16U
+#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT3_DUAL_MASK      0x3F000000U
+#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT3_DUAL_SHIFT     24U
+
+/* Register: IMXDPUV1_tcon1_MapBit7_4_Dual */
+#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL                        ((uint32_t)(0xE840))
+#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_OFFSET                 ((uint32_t)(0x40))
+#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_RESET_VALUE            0x7060504U
+#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT4_DUAL_MASK      0x3FU
+#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT4_DUAL_SHIFT     0U
+#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT5_DUAL_MASK      0x3F00U
+#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT5_DUAL_SHIFT     8U
+#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT6_DUAL_MASK      0x3F0000U
+#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT6_DUAL_SHIFT     16U
+#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT7_DUAL_MASK      0x3F000000U
+#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT7_DUAL_SHIFT     24U
+
+/* Register: IMXDPUV1_tcon1_MapBit11_8_Dual */
+#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL                       ((uint32_t)(0xE844))
+#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_OFFSET                ((uint32_t)(0x44))
+#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_RESET_VALUE           0xB0A0908U
+#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT8_DUAL_MASK     0x3FU
+#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT8_DUAL_SHIFT    0U
+#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT9_DUAL_MASK     0x3F00U
+#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT9_DUAL_SHIFT    8U
+#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT10_DUAL_MASK    0x3F0000U
+#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT10_DUAL_SHIFT   16U
+#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT11_DUAL_MASK    0x3F000000U
+#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT11_DUAL_SHIFT   24U
+
+/* Register: IMXDPUV1_tcon1_MapBit15_12_Dual */
+#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL                      ((uint32_t)(0xE848))
+#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_OFFSET               ((uint32_t)(0x48))
+#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_RESET_VALUE          0xF0E0D0CU
+#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT12_DUAL_MASK   0x3FU
+#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT12_DUAL_SHIFT  0U
+#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT13_DUAL_MASK   0x3F00U
+#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT13_DUAL_SHIFT  8U
+#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT14_DUAL_MASK   0x3F0000U
+#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT14_DUAL_SHIFT  16U
+#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT15_DUAL_MASK   0x3F000000U
+#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT15_DUAL_SHIFT  24U
+
+/* Register: IMXDPUV1_tcon1_MapBit19_16_Dual */
+#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL                      ((uint32_t)(0xE84C))
+#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_OFFSET               ((uint32_t)(0x4C))
+#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_RESET_VALUE          0x13121110U
+#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT16_DUAL_MASK   0x3FU
+#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT16_DUAL_SHIFT  0U
+#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT17_DUAL_MASK   0x3F00U
+#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT17_DUAL_SHIFT  8U
+#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT18_DUAL_MASK   0x3F0000U
+#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT18_DUAL_SHIFT  16U
+#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT19_DUAL_MASK   0x3F000000U
+#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT19_DUAL_SHIFT  24U
+
+/* Register: IMXDPUV1_tcon1_MapBit23_20_Dual */
+#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL                      ((uint32_t)(0xE850))
+#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_OFFSET               ((uint32_t)(0x50))
+#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_RESET_VALUE          0x17161514U
+#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT20_DUAL_MASK   0x3FU
+#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT20_DUAL_SHIFT  0U
+#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT21_DUAL_MASK   0x3F00U
+#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT21_DUAL_SHIFT  8U
+#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT22_DUAL_MASK   0x3F0000U
+#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT22_DUAL_SHIFT  16U
+#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT23_DUAL_MASK   0x3F000000U
+#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT23_DUAL_SHIFT  24U
+
+/* Register: IMXDPUV1_tcon1_MapBit27_24_Dual */
+#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL                      ((uint32_t)(0xE854))
+#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_OFFSET               ((uint32_t)(0x54))
+#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_RESET_VALUE          0x1B1A1918U
+#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT24_DUAL_MASK   0x3FU
+#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT24_DUAL_SHIFT  0U
+#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT25_DUAL_MASK   0x3F00U
+#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT25_DUAL_SHIFT  8U
+#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT26_DUAL_MASK   0x3F0000U
+#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT26_DUAL_SHIFT  16U
+#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT27_DUAL_MASK   0x3F000000U
+#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT27_DUAL_SHIFT  24U
+
+/* Register: IMXDPUV1_tcon1_MapBit31_28_Dual */
+#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL                      ((uint32_t)(0xE858))
+#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_OFFSET               ((uint32_t)(0x58))
+#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_RESET_VALUE          0x1F1E1D1CU
+#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT28_DUAL_MASK   0x3FU
+#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT28_DUAL_SHIFT  0U
+#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT29_DUAL_MASK   0x3F00U
+#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT29_DUAL_SHIFT  8U
+#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT30_DUAL_MASK   0x3F0000U
+#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT30_DUAL_SHIFT  16U
+#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT31_DUAL_MASK   0x3F000000U
+#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT31_DUAL_SHIFT  24U
+
+/* Register: IMXDPUV1_tcon1_MapBit34_32_Dual */
+#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL                      ((uint32_t)(0xE85C))
+#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_OFFSET               ((uint32_t)(0x5C))
+#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_RESET_VALUE          0x222120U
+#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT32_DUAL_MASK   0x3FU
+#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT32_DUAL_SHIFT  0U
+#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT33_DUAL_MASK   0x3F00U
+#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT33_DUAL_SHIFT  8U
+#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT34_DUAL_MASK   0x3F0000U
+#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT34_DUAL_SHIFT  16U
+
+/* Register: IMXDPUV1_tcon1_SPG0PosOn */
+#define IMXDPUV1_TCON1_SPG0POSON                             ((uint32_t)(0xE860))
+#define IMXDPUV1_TCON1_SPG0POSON_OFFSET                      ((uint32_t)(0x60))
+#define IMXDPUV1_TCON1_SPG0POSON_RESET_VALUE                 0x1480000U
+#define IMXDPUV1_TCON1_SPG0POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_Y0_MASK             0x7FFFU
+#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_Y0_SHIFT            0U
+#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_FIELD0_MASK         0x8000U
+#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_FIELD0_SHIFT        15U
+#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_X0_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_X0_SHIFT            16U
+#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_TOGGLE0_MASK        0x80000000U
+#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_TOGGLE0_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon1_SPG0MaskOn */
+#define IMXDPUV1_TCON1_SPG0MASKON                            ((uint32_t)(0xE864))
+#define IMXDPUV1_TCON1_SPG0MASKON_OFFSET                     ((uint32_t)(0x64))
+#define IMXDPUV1_TCON1_SPG0MASKON_RESET_VALUE                0xFFFFU
+#define IMXDPUV1_TCON1_SPG0MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG0MASKON_SPGMKON0_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG0MASKON_SPGMKON0_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon1_SPG0PosOff */
+#define IMXDPUV1_TCON1_SPG0POSOFF                            ((uint32_t)(0xE868))
+#define IMXDPUV1_TCON1_SPG0POSOFF_OFFSET                     ((uint32_t)(0x68))
+#define IMXDPUV1_TCON1_SPG0POSOFF_RESET_VALUE                0x1680000U
+#define IMXDPUV1_TCON1_SPG0POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_Y0_MASK           0x7FFFU
+#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_Y0_SHIFT          0U
+#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_FIELD0_MASK       0x8000U
+#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_FIELD0_SHIFT      15U
+#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_X0_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_X0_SHIFT          16U
+#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_TOGGLE0_MASK      0x80000000U
+#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_TOGGLE0_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon1_SPG0MaskOff */
+#define IMXDPUV1_TCON1_SPG0MASKOFF                           ((uint32_t)(0xE86C))
+#define IMXDPUV1_TCON1_SPG0MASKOFF_OFFSET                    ((uint32_t)(0x6C))
+#define IMXDPUV1_TCON1_SPG0MASKOFF_RESET_VALUE               0xFFFFU
+#define IMXDPUV1_TCON1_SPG0MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG0MASKOFF_SPGMKOFF0_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG0MASKOFF_SPGMKOFF0_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon1_SPG1PosOn */
+#define IMXDPUV1_TCON1_SPG1POSON                             ((uint32_t)(0xE870))
+#define IMXDPUV1_TCON1_SPG1POSON_OFFSET                      ((uint32_t)(0x70))
+#define IMXDPUV1_TCON1_SPG1POSON_RESET_VALUE                 0xF3U
+#define IMXDPUV1_TCON1_SPG1POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_Y1_MASK             0x7FFFU
+#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_Y1_SHIFT            0U
+#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_FIELD1_MASK         0x8000U
+#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_FIELD1_SHIFT        15U
+#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_X1_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_X1_SHIFT            16U
+#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_TOGGLE1_MASK        0x80000000U
+#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_TOGGLE1_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon1_SPG1MaskOn */
+#define IMXDPUV1_TCON1_SPG1MASKON                            ((uint32_t)(0xE874))
+#define IMXDPUV1_TCON1_SPG1MASKON_OFFSET                     ((uint32_t)(0x74))
+#define IMXDPUV1_TCON1_SPG1MASKON_RESET_VALUE                0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG1MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG1MASKON_SPGMKON1_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG1MASKON_SPGMKON1_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon1_SPG1PosOff */
+#define IMXDPUV1_TCON1_SPG1POSOFF                            ((uint32_t)(0xE878))
+#define IMXDPUV1_TCON1_SPG1POSOFF_OFFSET                     ((uint32_t)(0x78))
+#define IMXDPUV1_TCON1_SPG1POSOFF_RESET_VALUE                0xF7U
+#define IMXDPUV1_TCON1_SPG1POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_Y1_MASK           0x7FFFU
+#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_Y1_SHIFT          0U
+#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_FIELD1_MASK       0x8000U
+#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_FIELD1_SHIFT      15U
+#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_X1_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_X1_SHIFT          16U
+#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_TOGGLE1_MASK      0x80000000U
+#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_TOGGLE1_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon1_SPG1MaskOff */
+#define IMXDPUV1_TCON1_SPG1MASKOFF                           ((uint32_t)(0xE87C))
+#define IMXDPUV1_TCON1_SPG1MASKOFF_OFFSET                    ((uint32_t)(0x7C))
+#define IMXDPUV1_TCON1_SPG1MASKOFF_RESET_VALUE               0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG1MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG1MASKOFF_SPGMKOFF1_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG1MASKOFF_SPGMKOFF1_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon1_SPG2PosOn */
+#define IMXDPUV1_TCON1_SPG2POSON                             ((uint32_t)(0xE880))
+#define IMXDPUV1_TCON1_SPG2POSON_OFFSET                      ((uint32_t)(0x80))
+#define IMXDPUV1_TCON1_SPG2POSON_RESET_VALUE                 0U
+#define IMXDPUV1_TCON1_SPG2POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_Y2_MASK             0x7FFFU
+#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_Y2_SHIFT            0U
+#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_FIELD2_MASK         0x8000U
+#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_FIELD2_SHIFT        15U
+#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_X2_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_X2_SHIFT            16U
+#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_TOGGLE2_MASK        0x80000000U
+#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_TOGGLE2_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon1_SPG2MaskOn */
+#define IMXDPUV1_TCON1_SPG2MASKON                            ((uint32_t)(0xE884))
+#define IMXDPUV1_TCON1_SPG2MASKON_OFFSET                     ((uint32_t)(0x84))
+#define IMXDPUV1_TCON1_SPG2MASKON_RESET_VALUE                0xFFFFU
+#define IMXDPUV1_TCON1_SPG2MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG2MASKON_SPGMKON2_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG2MASKON_SPGMKON2_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon1_SPG2PosOff */
+#define IMXDPUV1_TCON1_SPG2POSOFF                            ((uint32_t)(0xE888))
+#define IMXDPUV1_TCON1_SPG2POSOFF_OFFSET                     ((uint32_t)(0x88))
+#define IMXDPUV1_TCON1_SPG2POSOFF_RESET_VALUE                0x1400000U
+#define IMXDPUV1_TCON1_SPG2POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_Y2_MASK           0x7FFFU
+#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_Y2_SHIFT          0U
+#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_FIELD2_MASK       0x8000U
+#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_FIELD2_SHIFT      15U
+#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_X2_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_X2_SHIFT          16U
+#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_TOGGLE2_MASK      0x80000000U
+#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_TOGGLE2_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon1_SPG2MaskOff */
+#define IMXDPUV1_TCON1_SPG2MASKOFF                           ((uint32_t)(0xE88C))
+#define IMXDPUV1_TCON1_SPG2MASKOFF_OFFSET                    ((uint32_t)(0x8C))
+#define IMXDPUV1_TCON1_SPG2MASKOFF_RESET_VALUE               0xFFFFU
+#define IMXDPUV1_TCON1_SPG2MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG2MASKOFF_SPGMKOFF2_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG2MASKOFF_SPGMKOFF2_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon1_SPG3PosOn */
+#define IMXDPUV1_TCON1_SPG3POSON                             ((uint32_t)(0xE890))
+#define IMXDPUV1_TCON1_SPG3POSON_OFFSET                      ((uint32_t)(0x90))
+#define IMXDPUV1_TCON1_SPG3POSON_RESET_VALUE                 0U
+#define IMXDPUV1_TCON1_SPG3POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_Y3_MASK             0x7FFFU
+#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_Y3_SHIFT            0U
+#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_FIELD3_MASK         0x8000U
+#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_FIELD3_SHIFT        15U
+#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_X3_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_X3_SHIFT            16U
+#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_TOGGLE3_MASK        0x80000000U
+#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_TOGGLE3_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon1_SPG3MaskOn */
+#define IMXDPUV1_TCON1_SPG3MASKON                            ((uint32_t)(0xE894))
+#define IMXDPUV1_TCON1_SPG3MASKON_OFFSET                     ((uint32_t)(0x94))
+#define IMXDPUV1_TCON1_SPG3MASKON_RESET_VALUE                0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG3MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG3MASKON_SPGMKON3_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG3MASKON_SPGMKON3_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon1_SPG3PosOff */
+#define IMXDPUV1_TCON1_SPG3POSOFF                            ((uint32_t)(0xE898))
+#define IMXDPUV1_TCON1_SPG3POSOFF_OFFSET                     ((uint32_t)(0x98))
+#define IMXDPUV1_TCON1_SPG3POSOFF_RESET_VALUE                0xF0U
+#define IMXDPUV1_TCON1_SPG3POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_Y3_MASK           0x7FFFU
+#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_Y3_SHIFT          0U
+#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_FIELD3_MASK       0x8000U
+#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_FIELD3_SHIFT      15U
+#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_X3_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_X3_SHIFT          16U
+#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_TOGGLE3_MASK      0x80000000U
+#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_TOGGLE3_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon1_SPG3MaskOff */
+#define IMXDPUV1_TCON1_SPG3MASKOFF                           ((uint32_t)(0xE89C))
+#define IMXDPUV1_TCON1_SPG3MASKOFF_OFFSET                    ((uint32_t)(0x9C))
+#define IMXDPUV1_TCON1_SPG3MASKOFF_RESET_VALUE               0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG3MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG3MASKOFF_SPGMKOFF3_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG3MASKOFF_SPGMKOFF3_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon1_SPG4PosOn */
+#define IMXDPUV1_TCON1_SPG4POSON                             ((uint32_t)(0xE8A0))
+#define IMXDPUV1_TCON1_SPG4POSON_OFFSET                      ((uint32_t)(0xA0))
+#define IMXDPUV1_TCON1_SPG4POSON_RESET_VALUE                 0U
+#define IMXDPUV1_TCON1_SPG4POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_Y4_MASK             0x7FFFU
+#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_Y4_SHIFT            0U
+#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_FIELD4_MASK         0x8000U
+#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_FIELD4_SHIFT        15U
+#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_X4_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_X4_SHIFT            16U
+#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_TOGGLE4_MASK        0x80000000U
+#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_TOGGLE4_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon1_SPG4MaskOn */
+#define IMXDPUV1_TCON1_SPG4MASKON                            ((uint32_t)(0xE8A4))
+#define IMXDPUV1_TCON1_SPG4MASKON_OFFSET                     ((uint32_t)(0xA4))
+#define IMXDPUV1_TCON1_SPG4MASKON_RESET_VALUE                0U
+#define IMXDPUV1_TCON1_SPG4MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG4MASKON_SPGMKON4_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG4MASKON_SPGMKON4_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon1_SPG4PosOff */
+#define IMXDPUV1_TCON1_SPG4POSOFF                            ((uint32_t)(0xE8A8))
+#define IMXDPUV1_TCON1_SPG4POSOFF_OFFSET                     ((uint32_t)(0xA8))
+#define IMXDPUV1_TCON1_SPG4POSOFF_RESET_VALUE                0U
+#define IMXDPUV1_TCON1_SPG4POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_Y4_MASK           0x7FFFU
+#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_Y4_SHIFT          0U
+#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_FIELD4_MASK       0x8000U
+#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_FIELD4_SHIFT      15U
+#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_X4_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_X4_SHIFT          16U
+#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_TOGGLE4_MASK      0x80000000U
+#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_TOGGLE4_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon1_SPG4MaskOff */
+#define IMXDPUV1_TCON1_SPG4MASKOFF                           ((uint32_t)(0xE8AC))
+#define IMXDPUV1_TCON1_SPG4MASKOFF_OFFSET                    ((uint32_t)(0xAC))
+#define IMXDPUV1_TCON1_SPG4MASKOFF_RESET_VALUE               0U
+#define IMXDPUV1_TCON1_SPG4MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG4MASKOFF_SPGMKOFF4_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG4MASKOFF_SPGMKOFF4_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon1_SPG5PosOn */
+#define IMXDPUV1_TCON1_SPG5POSON                             ((uint32_t)(0xE8B0))
+#define IMXDPUV1_TCON1_SPG5POSON_OFFSET                      ((uint32_t)(0xB0))
+#define IMXDPUV1_TCON1_SPG5POSON_RESET_VALUE                 0U
+#define IMXDPUV1_TCON1_SPG5POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_Y5_MASK             0x7FFFU
+#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_Y5_SHIFT            0U
+#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_FIELD5_MASK         0x8000U
+#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_FIELD5_SHIFT        15U
+#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_X5_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_X5_SHIFT            16U
+#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_TOGGLE5_MASK        0x80000000U
+#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_TOGGLE5_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon1_SPG5MaskOn */
+#define IMXDPUV1_TCON1_SPG5MASKON                            ((uint32_t)(0xE8B4))
+#define IMXDPUV1_TCON1_SPG5MASKON_OFFSET                     ((uint32_t)(0xB4))
+#define IMXDPUV1_TCON1_SPG5MASKON_RESET_VALUE                0U
+#define IMXDPUV1_TCON1_SPG5MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG5MASKON_SPGMKON5_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG5MASKON_SPGMKON5_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon1_SPG5PosOff */
+#define IMXDPUV1_TCON1_SPG5POSOFF                            ((uint32_t)(0xE8B8))
+#define IMXDPUV1_TCON1_SPG5POSOFF_OFFSET                     ((uint32_t)(0xB8))
+#define IMXDPUV1_TCON1_SPG5POSOFF_RESET_VALUE                0U
+#define IMXDPUV1_TCON1_SPG5POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_Y5_MASK           0x7FFFU
+#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_Y5_SHIFT          0U
+#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_FIELD5_MASK       0x8000U
+#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_FIELD5_SHIFT      15U
+#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_X5_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_X5_SHIFT          16U
+#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_TOGGLE5_MASK      0x80000000U
+#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_TOGGLE5_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon1_SPG5MaskOff */
+#define IMXDPUV1_TCON1_SPG5MASKOFF                           ((uint32_t)(0xE8BC))
+#define IMXDPUV1_TCON1_SPG5MASKOFF_OFFSET                    ((uint32_t)(0xBC))
+#define IMXDPUV1_TCON1_SPG5MASKOFF_RESET_VALUE               0U
+#define IMXDPUV1_TCON1_SPG5MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG5MASKOFF_SPGMKOFF5_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG5MASKOFF_SPGMKOFF5_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon1_SPG6PosOn */
+#define IMXDPUV1_TCON1_SPG6POSON                             ((uint32_t)(0xE8C0))
+#define IMXDPUV1_TCON1_SPG6POSON_OFFSET                      ((uint32_t)(0xC0))
+#define IMXDPUV1_TCON1_SPG6POSON_RESET_VALUE                 0U
+#define IMXDPUV1_TCON1_SPG6POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_Y6_MASK             0x7FFFU
+#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_Y6_SHIFT            0U
+#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_FIELD6_MASK         0x8000U
+#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_FIELD6_SHIFT        15U
+#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_X6_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_X6_SHIFT            16U
+#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_TOGGLE6_MASK        0x80000000U
+#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_TOGGLE6_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon1_SPG6MaskOn */
+#define IMXDPUV1_TCON1_SPG6MASKON                            ((uint32_t)(0xE8C4))
+#define IMXDPUV1_TCON1_SPG6MASKON_OFFSET                     ((uint32_t)(0xC4))
+#define IMXDPUV1_TCON1_SPG6MASKON_RESET_VALUE                0U
+#define IMXDPUV1_TCON1_SPG6MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG6MASKON_SPGMKON6_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG6MASKON_SPGMKON6_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon1_SPG6PosOff */
+#define IMXDPUV1_TCON1_SPG6POSOFF                            ((uint32_t)(0xE8C8))
+#define IMXDPUV1_TCON1_SPG6POSOFF_OFFSET                     ((uint32_t)(0xC8))
+#define IMXDPUV1_TCON1_SPG6POSOFF_RESET_VALUE                0U
+#define IMXDPUV1_TCON1_SPG6POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_Y6_MASK           0x7FFFU
+#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_Y6_SHIFT          0U
+#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_FIELD6_MASK       0x8000U
+#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_FIELD6_SHIFT      15U
+#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_X6_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_X6_SHIFT          16U
+#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_TOGGLE6_MASK      0x80000000U
+#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_TOGGLE6_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon1_SPG6MaskOff */
+#define IMXDPUV1_TCON1_SPG6MASKOFF                           ((uint32_t)(0xE8CC))
+#define IMXDPUV1_TCON1_SPG6MASKOFF_OFFSET                    ((uint32_t)(0xCC))
+#define IMXDPUV1_TCON1_SPG6MASKOFF_RESET_VALUE               0U
+#define IMXDPUV1_TCON1_SPG6MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG6MASKOFF_SPGMKOFF6_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG6MASKOFF_SPGMKOFF6_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon1_SPG7PosOn */
+#define IMXDPUV1_TCON1_SPG7POSON                             ((uint32_t)(0xE8D0))
+#define IMXDPUV1_TCON1_SPG7POSON_OFFSET                      ((uint32_t)(0xD0))
+#define IMXDPUV1_TCON1_SPG7POSON_RESET_VALUE                 0U
+#define IMXDPUV1_TCON1_SPG7POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_Y7_MASK             0x7FFFU
+#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_Y7_SHIFT            0U
+#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_FIELD7_MASK         0x8000U
+#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_FIELD7_SHIFT        15U
+#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_X7_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_X7_SHIFT            16U
+#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_TOGGLE7_MASK        0x80000000U
+#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_TOGGLE7_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon1_SPG7MaskOn */
+#define IMXDPUV1_TCON1_SPG7MASKON                            ((uint32_t)(0xE8D4))
+#define IMXDPUV1_TCON1_SPG7MASKON_OFFSET                     ((uint32_t)(0xD4))
+#define IMXDPUV1_TCON1_SPG7MASKON_RESET_VALUE                0U
+#define IMXDPUV1_TCON1_SPG7MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG7MASKON_SPGMKON7_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG7MASKON_SPGMKON7_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon1_SPG7PosOff */
+#define IMXDPUV1_TCON1_SPG7POSOFF                            ((uint32_t)(0xE8D8))
+#define IMXDPUV1_TCON1_SPG7POSOFF_OFFSET                     ((uint32_t)(0xD8))
+#define IMXDPUV1_TCON1_SPG7POSOFF_RESET_VALUE                0U
+#define IMXDPUV1_TCON1_SPG7POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_Y7_MASK           0x7FFFU
+#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_Y7_SHIFT          0U
+#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_FIELD7_MASK       0x8000U
+#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_FIELD7_SHIFT      15U
+#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_X7_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_X7_SHIFT          16U
+#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_TOGGLE7_MASK      0x80000000U
+#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_TOGGLE7_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon1_SPG7MaskOff */
+#define IMXDPUV1_TCON1_SPG7MASKOFF                           ((uint32_t)(0xE8DC))
+#define IMXDPUV1_TCON1_SPG7MASKOFF_OFFSET                    ((uint32_t)(0xDC))
+#define IMXDPUV1_TCON1_SPG7MASKOFF_RESET_VALUE               0U
+#define IMXDPUV1_TCON1_SPG7MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG7MASKOFF_SPGMKOFF7_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG7MASKOFF_SPGMKOFF7_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon1_SPG8PosOn */
+#define IMXDPUV1_TCON1_SPG8POSON                             ((uint32_t)(0xE8E0))
+#define IMXDPUV1_TCON1_SPG8POSON_OFFSET                      ((uint32_t)(0xE0))
+#define IMXDPUV1_TCON1_SPG8POSON_RESET_VALUE                 0U
+#define IMXDPUV1_TCON1_SPG8POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_Y8_MASK             0x7FFFU
+#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_Y8_SHIFT            0U
+#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_FIELD8_MASK         0x8000U
+#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_FIELD8_SHIFT        15U
+#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_X8_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_X8_SHIFT            16U
+#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_TOGGLE8_MASK        0x80000000U
+#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_TOGGLE8_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon1_SPG8MaskOn */
+#define IMXDPUV1_TCON1_SPG8MASKON                            ((uint32_t)(0xE8E4))
+#define IMXDPUV1_TCON1_SPG8MASKON_OFFSET                     ((uint32_t)(0xE4))
+#define IMXDPUV1_TCON1_SPG8MASKON_RESET_VALUE                0U
+#define IMXDPUV1_TCON1_SPG8MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG8MASKON_SPGMKON8_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG8MASKON_SPGMKON8_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon1_SPG8PosOff */
+#define IMXDPUV1_TCON1_SPG8POSOFF                            ((uint32_t)(0xE8E8))
+#define IMXDPUV1_TCON1_SPG8POSOFF_OFFSET                     ((uint32_t)(0xE8))
+#define IMXDPUV1_TCON1_SPG8POSOFF_RESET_VALUE                0U
+#define IMXDPUV1_TCON1_SPG8POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_Y8_MASK           0x7FFFU
+#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_Y8_SHIFT          0U
+#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_FIELD8_MASK       0x8000U
+#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_FIELD8_SHIFT      15U
+#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_X8_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_X8_SHIFT          16U
+#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_TOGGLE8_MASK      0x80000000U
+#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_TOGGLE8_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon1_SPG8MaskOff */
+#define IMXDPUV1_TCON1_SPG8MASKOFF                           ((uint32_t)(0xE8EC))
+#define IMXDPUV1_TCON1_SPG8MASKOFF_OFFSET                    ((uint32_t)(0xEC))
+#define IMXDPUV1_TCON1_SPG8MASKOFF_RESET_VALUE               0U
+#define IMXDPUV1_TCON1_SPG8MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG8MASKOFF_SPGMKOFF8_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG8MASKOFF_SPGMKOFF8_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon1_SPG9PosOn */
+#define IMXDPUV1_TCON1_SPG9POSON                             ((uint32_t)(0xE8F0))
+#define IMXDPUV1_TCON1_SPG9POSON_OFFSET                      ((uint32_t)(0xF0))
+#define IMXDPUV1_TCON1_SPG9POSON_RESET_VALUE                 0U
+#define IMXDPUV1_TCON1_SPG9POSON_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_Y9_MASK             0x7FFFU
+#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_Y9_SHIFT            0U
+#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_FIELD9_MASK         0x8000U
+#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_FIELD9_SHIFT        15U
+#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_X9_MASK             0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_X9_SHIFT            16U
+#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_TOGGLE9_MASK        0x80000000U
+#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_TOGGLE9_SHIFT       31U
+
+/* Register: IMXDPUV1_tcon1_SPG9MaskOn */
+#define IMXDPUV1_TCON1_SPG9MASKON                            ((uint32_t)(0xE8F4))
+#define IMXDPUV1_TCON1_SPG9MASKON_OFFSET                     ((uint32_t)(0xF4))
+#define IMXDPUV1_TCON1_SPG9MASKON_RESET_VALUE                0U
+#define IMXDPUV1_TCON1_SPG9MASKON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG9MASKON_SPGMKON9_MASK              0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG9MASKON_SPGMKON9_SHIFT             0U
+
+/* Register: IMXDPUV1_tcon1_SPG9PosOff */
+#define IMXDPUV1_TCON1_SPG9POSOFF                            ((uint32_t)(0xE8F8))
+#define IMXDPUV1_TCON1_SPG9POSOFF_OFFSET                     ((uint32_t)(0xF8))
+#define IMXDPUV1_TCON1_SPG9POSOFF_RESET_VALUE                0U
+#define IMXDPUV1_TCON1_SPG9POSOFF_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_Y9_MASK           0x7FFFU
+#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_Y9_SHIFT          0U
+#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_FIELD9_MASK       0x8000U
+#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_FIELD9_SHIFT      15U
+#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_X9_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_X9_SHIFT          16U
+#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_TOGGLE9_MASK      0x80000000U
+#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_TOGGLE9_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon1_SPG9MaskOff */
+#define IMXDPUV1_TCON1_SPG9MASKOFF                           ((uint32_t)(0xE8FC))
+#define IMXDPUV1_TCON1_SPG9MASKOFF_OFFSET                    ((uint32_t)(0xFC))
+#define IMXDPUV1_TCON1_SPG9MASKOFF_RESET_VALUE               0U
+#define IMXDPUV1_TCON1_SPG9MASKOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG9MASKOFF_SPGMKOFF9_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG9MASKOFF_SPGMKOFF9_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon1_SPG10PosOn */
+#define IMXDPUV1_TCON1_SPG10POSON                            ((uint32_t)(0xE900))
+#define IMXDPUV1_TCON1_SPG10POSON_OFFSET                     ((uint32_t)(0x100))
+#define IMXDPUV1_TCON1_SPG10POSON_RESET_VALUE                0U
+#define IMXDPUV1_TCON1_SPG10POSON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_Y10_MASK           0x7FFFU
+#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_Y10_SHIFT          0U
+#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_FIELD10_MASK       0x8000U
+#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_FIELD10_SHIFT      15U
+#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_X10_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_X10_SHIFT          16U
+#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_TOGGLE10_MASK      0x80000000U
+#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_TOGGLE10_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon1_SPG10MaskOn */
+#define IMXDPUV1_TCON1_SPG10MASKON                           ((uint32_t)(0xE904))
+#define IMXDPUV1_TCON1_SPG10MASKON_OFFSET                    ((uint32_t)(0x104))
+#define IMXDPUV1_TCON1_SPG10MASKON_RESET_VALUE               0U
+#define IMXDPUV1_TCON1_SPG10MASKON_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG10MASKON_SPGMKON10_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG10MASKON_SPGMKON10_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon1_SPG10PosOff */
+#define IMXDPUV1_TCON1_SPG10POSOFF                           ((uint32_t)(0xE908))
+#define IMXDPUV1_TCON1_SPG10POSOFF_OFFSET                    ((uint32_t)(0x108))
+#define IMXDPUV1_TCON1_SPG10POSOFF_RESET_VALUE               0U
+#define IMXDPUV1_TCON1_SPG10POSOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_Y10_MASK         0x7FFFU
+#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_Y10_SHIFT        0U
+#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_FIELD10_MASK     0x8000U
+#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_FIELD10_SHIFT    15U
+#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_X10_MASK         0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_X10_SHIFT        16U
+#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_TOGGLE10_MASK    0x80000000U
+#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_TOGGLE10_SHIFT   31U
+
+/* Register: IMXDPUV1_tcon1_SPG10MaskOff */
+#define IMXDPUV1_TCON1_SPG10MASKOFF                          ((uint32_t)(0xE90C))
+#define IMXDPUV1_TCON1_SPG10MASKOFF_OFFSET                   ((uint32_t)(0x10C))
+#define IMXDPUV1_TCON1_SPG10MASKOFF_RESET_VALUE              0U
+#define IMXDPUV1_TCON1_SPG10MASKOFF_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG10MASKOFF_SPGMKOFF10_MASK          0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG10MASKOFF_SPGMKOFF10_SHIFT         0U
+
+/* Register: IMXDPUV1_tcon1_SPG11PosOn */
+#define IMXDPUV1_TCON1_SPG11POSON                            ((uint32_t)(0xE910))
+#define IMXDPUV1_TCON1_SPG11POSON_OFFSET                     ((uint32_t)(0x110))
+#define IMXDPUV1_TCON1_SPG11POSON_RESET_VALUE                0U
+#define IMXDPUV1_TCON1_SPG11POSON_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_Y11_MASK           0x7FFFU
+#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_Y11_SHIFT          0U
+#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_FIELD11_MASK       0x8000U
+#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_FIELD11_SHIFT      15U
+#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_X11_MASK           0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_X11_SHIFT          16U
+#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_TOGGLE11_MASK      0x80000000U
+#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_TOGGLE11_SHIFT     31U
+
+/* Register: IMXDPUV1_tcon1_SPG11MaskOn */
+#define IMXDPUV1_TCON1_SPG11MASKON                           ((uint32_t)(0xE914))
+#define IMXDPUV1_TCON1_SPG11MASKON_OFFSET                    ((uint32_t)(0x114))
+#define IMXDPUV1_TCON1_SPG11MASKON_RESET_VALUE               0U
+#define IMXDPUV1_TCON1_SPG11MASKON_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG11MASKON_SPGMKON11_MASK            0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG11MASKON_SPGMKON11_SHIFT           0U
+
+/* Register: IMXDPUV1_tcon1_SPG11PosOff */
+#define IMXDPUV1_TCON1_SPG11POSOFF                           ((uint32_t)(0xE918))
+#define IMXDPUV1_TCON1_SPG11POSOFF_OFFSET                    ((uint32_t)(0x118))
+#define IMXDPUV1_TCON1_SPG11POSOFF_RESET_VALUE               0U
+#define IMXDPUV1_TCON1_SPG11POSOFF_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_Y11_MASK         0x7FFFU
+#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_Y11_SHIFT        0U
+#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_FIELD11_MASK     0x8000U
+#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_FIELD11_SHIFT    15U
+#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_X11_MASK         0x7FFF0000U
+#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_X11_SHIFT        16U
+#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_TOGGLE11_MASK    0x80000000U
+#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_TOGGLE11_SHIFT   31U
+
+/* Register: IMXDPUV1_tcon1_SPG11MaskOff */
+#define IMXDPUV1_TCON1_SPG11MASKOFF                          ((uint32_t)(0xE91C))
+#define IMXDPUV1_TCON1_SPG11MASKOFF_OFFSET                   ((uint32_t)(0x11C))
+#define IMXDPUV1_TCON1_SPG11MASKOFF_RESET_VALUE              0U
+#define IMXDPUV1_TCON1_SPG11MASKOFF_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SPG11MASKOFF_SPGMKOFF11_MASK          0x7FFFFFFFU
+#define IMXDPUV1_TCON1_SPG11MASKOFF_SPGMKOFF11_SHIFT         0U
+
+/* Register: IMXDPUV1_tcon1_SMx0Sigs */
+#define IMXDPUV1_TCON1_SMX0SIGS                              ((uint32_t)(0xE920))
+#define IMXDPUV1_TCON1_SMX0SIGS_OFFSET                       ((uint32_t)(0x120))
+#define IMXDPUV1_TCON1_SMX0SIGS_RESET_VALUE                  0x2U
+#define IMXDPUV1_TCON1_SMX0SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon1_SMx0FctTable */
+#define IMXDPUV1_TCON1_SMX0FCTTABLE                          ((uint32_t)(0xE924))
+#define IMXDPUV1_TCON1_SMX0FCTTABLE_OFFSET                   ((uint32_t)(0x124))
+#define IMXDPUV1_TCON1_SMX0FCTTABLE_RESET_VALUE              0x1U
+#define IMXDPUV1_TCON1_SMX0FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX0FCTTABLE_SMXFCT0_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX0FCTTABLE_SMXFCT0_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon1_SMx1Sigs */
+#define IMXDPUV1_TCON1_SMX1SIGS                              ((uint32_t)(0xE928))
+#define IMXDPUV1_TCON1_SMX1SIGS_OFFSET                       ((uint32_t)(0x128))
+#define IMXDPUV1_TCON1_SMX1SIGS_RESET_VALUE                  0x3U
+#define IMXDPUV1_TCON1_SMX1SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon1_SMx1FctTable */
+#define IMXDPUV1_TCON1_SMX1FCTTABLE                          ((uint32_t)(0xE92C))
+#define IMXDPUV1_TCON1_SMX1FCTTABLE_OFFSET                   ((uint32_t)(0x12C))
+#define IMXDPUV1_TCON1_SMX1FCTTABLE_RESET_VALUE              0x1U
+#define IMXDPUV1_TCON1_SMX1FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX1FCTTABLE_SMXFCT1_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX1FCTTABLE_SMXFCT1_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon1_SMx2Sigs */
+#define IMXDPUV1_TCON1_SMX2SIGS                              ((uint32_t)(0xE930))
+#define IMXDPUV1_TCON1_SMX2SIGS_OFFSET                       ((uint32_t)(0x130))
+#define IMXDPUV1_TCON1_SMX2SIGS_RESET_VALUE                  0x2CU
+#define IMXDPUV1_TCON1_SMX2SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon1_SMx2FctTable */
+#define IMXDPUV1_TCON1_SMX2FCTTABLE                          ((uint32_t)(0xE934))
+#define IMXDPUV1_TCON1_SMX2FCTTABLE_OFFSET                   ((uint32_t)(0x134))
+#define IMXDPUV1_TCON1_SMX2FCTTABLE_RESET_VALUE              0x8U
+#define IMXDPUV1_TCON1_SMX2FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX2FCTTABLE_SMXFCT2_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX2FCTTABLE_SMXFCT2_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon1_SMx3Sigs */
+#define IMXDPUV1_TCON1_SMX3SIGS                              ((uint32_t)(0xE938))
+#define IMXDPUV1_TCON1_SMX3SIGS_OFFSET                       ((uint32_t)(0x138))
+#define IMXDPUV1_TCON1_SMX3SIGS_RESET_VALUE                  0U
+#define IMXDPUV1_TCON1_SMX3SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon1_SMx3FctTable */
+#define IMXDPUV1_TCON1_SMX3FCTTABLE                          ((uint32_t)(0xE93C))
+#define IMXDPUV1_TCON1_SMX3FCTTABLE_OFFSET                   ((uint32_t)(0x13C))
+#define IMXDPUV1_TCON1_SMX3FCTTABLE_RESET_VALUE              0U
+#define IMXDPUV1_TCON1_SMX3FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX3FCTTABLE_SMXFCT3_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX3FCTTABLE_SMXFCT3_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon1_SMx4Sigs */
+#define IMXDPUV1_TCON1_SMX4SIGS                              ((uint32_t)(0xE940))
+#define IMXDPUV1_TCON1_SMX4SIGS_OFFSET                       ((uint32_t)(0x140))
+#define IMXDPUV1_TCON1_SMX4SIGS_RESET_VALUE                  0U
+#define IMXDPUV1_TCON1_SMX4SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon1_SMx4FctTable */
+#define IMXDPUV1_TCON1_SMX4FCTTABLE                          ((uint32_t)(0xE944))
+#define IMXDPUV1_TCON1_SMX4FCTTABLE_OFFSET                   ((uint32_t)(0x144))
+#define IMXDPUV1_TCON1_SMX4FCTTABLE_RESET_VALUE              0U
+#define IMXDPUV1_TCON1_SMX4FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX4FCTTABLE_SMXFCT4_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX4FCTTABLE_SMXFCT4_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon1_SMx5Sigs */
+#define IMXDPUV1_TCON1_SMX5SIGS                              ((uint32_t)(0xE948))
+#define IMXDPUV1_TCON1_SMX5SIGS_OFFSET                       ((uint32_t)(0x148))
+#define IMXDPUV1_TCON1_SMX5SIGS_RESET_VALUE                  0U
+#define IMXDPUV1_TCON1_SMX5SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon1_SMx5FctTable */
+#define IMXDPUV1_TCON1_SMX5FCTTABLE                          ((uint32_t)(0xE94C))
+#define IMXDPUV1_TCON1_SMX5FCTTABLE_OFFSET                   ((uint32_t)(0x14C))
+#define IMXDPUV1_TCON1_SMX5FCTTABLE_RESET_VALUE              0U
+#define IMXDPUV1_TCON1_SMX5FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX5FCTTABLE_SMXFCT5_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX5FCTTABLE_SMXFCT5_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon1_SMx6Sigs */
+#define IMXDPUV1_TCON1_SMX6SIGS                              ((uint32_t)(0xE950))
+#define IMXDPUV1_TCON1_SMX6SIGS_OFFSET                       ((uint32_t)(0x150))
+#define IMXDPUV1_TCON1_SMX6SIGS_RESET_VALUE                  0U
+#define IMXDPUV1_TCON1_SMX6SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon1_SMx6FctTable */
+#define IMXDPUV1_TCON1_SMX6FCTTABLE                          ((uint32_t)(0xE954))
+#define IMXDPUV1_TCON1_SMX6FCTTABLE_OFFSET                   ((uint32_t)(0x154))
+#define IMXDPUV1_TCON1_SMX6FCTTABLE_RESET_VALUE              0U
+#define IMXDPUV1_TCON1_SMX6FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX6FCTTABLE_SMXFCT6_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX6FCTTABLE_SMXFCT6_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon1_SMx7Sigs */
+#define IMXDPUV1_TCON1_SMX7SIGS                              ((uint32_t)(0xE958))
+#define IMXDPUV1_TCON1_SMX7SIGS_OFFSET                       ((uint32_t)(0x158))
+#define IMXDPUV1_TCON1_SMX7SIGS_RESET_VALUE                  0U
+#define IMXDPUV1_TCON1_SMX7SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon1_SMx7FctTable */
+#define IMXDPUV1_TCON1_SMX7FCTTABLE                          ((uint32_t)(0xE95C))
+#define IMXDPUV1_TCON1_SMX7FCTTABLE_OFFSET                   ((uint32_t)(0x15C))
+#define IMXDPUV1_TCON1_SMX7FCTTABLE_RESET_VALUE              0U
+#define IMXDPUV1_TCON1_SMX7FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX7FCTTABLE_SMXFCT7_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX7FCTTABLE_SMXFCT7_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon1_SMx8Sigs */
+#define IMXDPUV1_TCON1_SMX8SIGS                              ((uint32_t)(0xE960))
+#define IMXDPUV1_TCON1_SMX8SIGS_OFFSET                       ((uint32_t)(0x160))
+#define IMXDPUV1_TCON1_SMX8SIGS_RESET_VALUE                  0U
+#define IMXDPUV1_TCON1_SMX8SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon1_SMx8FctTable */
+#define IMXDPUV1_TCON1_SMX8FCTTABLE                          ((uint32_t)(0xE964))
+#define IMXDPUV1_TCON1_SMX8FCTTABLE_OFFSET                   ((uint32_t)(0x164))
+#define IMXDPUV1_TCON1_SMX8FCTTABLE_RESET_VALUE              0U
+#define IMXDPUV1_TCON1_SMX8FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX8FCTTABLE_SMXFCT8_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX8FCTTABLE_SMXFCT8_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon1_SMx9Sigs */
+#define IMXDPUV1_TCON1_SMX9SIGS                              ((uint32_t)(0xE968))
+#define IMXDPUV1_TCON1_SMX9SIGS_OFFSET                       ((uint32_t)(0x168))
+#define IMXDPUV1_TCON1_SMX9SIGS_RESET_VALUE                  0U
+#define IMXDPUV1_TCON1_SMX9SIGS_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S0_MASK             0x7U
+#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S0_SHIFT            0U
+#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S1_MASK             0x38U
+#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S1_SHIFT            3U
+#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S2_MASK             0x1C0U
+#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S2_SHIFT            6U
+#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S3_MASK             0xE00U
+#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S3_SHIFT            9U
+#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S4_MASK             0x7000U
+#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S4_SHIFT            12U
+
+/* Register: IMXDPUV1_tcon1_SMx9FctTable */
+#define IMXDPUV1_TCON1_SMX9FCTTABLE                          ((uint32_t)(0xE96C))
+#define IMXDPUV1_TCON1_SMX9FCTTABLE_OFFSET                   ((uint32_t)(0x16C))
+#define IMXDPUV1_TCON1_SMX9FCTTABLE_RESET_VALUE              0U
+#define IMXDPUV1_TCON1_SMX9FCTTABLE_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX9FCTTABLE_SMXFCT9_MASK             0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX9FCTTABLE_SMXFCT9_SHIFT            0U
+
+/* Register: IMXDPUV1_tcon1_SMx10Sigs */
+#define IMXDPUV1_TCON1_SMX10SIGS                             ((uint32_t)(0xE970))
+#define IMXDPUV1_TCON1_SMX10SIGS_OFFSET                      ((uint32_t)(0x170))
+#define IMXDPUV1_TCON1_SMX10SIGS_RESET_VALUE                 0U
+#define IMXDPUV1_TCON1_SMX10SIGS_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S0_MASK           0x7U
+#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S0_SHIFT          0U
+#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S1_MASK           0x38U
+#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S1_SHIFT          3U
+#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S2_MASK           0x1C0U
+#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S2_SHIFT          6U
+#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S3_MASK           0xE00U
+#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S3_SHIFT          9U
+#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S4_MASK           0x7000U
+#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S4_SHIFT          12U
+
+/* Register: IMXDPUV1_tcon1_SMx10FctTable */
+#define IMXDPUV1_TCON1_SMX10FCTTABLE                         ((uint32_t)(0xE974))
+#define IMXDPUV1_TCON1_SMX10FCTTABLE_OFFSET                  ((uint32_t)(0x174))
+#define IMXDPUV1_TCON1_SMX10FCTTABLE_RESET_VALUE             0U
+#define IMXDPUV1_TCON1_SMX10FCTTABLE_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX10FCTTABLE_SMXFCT10_MASK           0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX10FCTTABLE_SMXFCT10_SHIFT          0U
+
+/* Register: IMXDPUV1_tcon1_SMx11Sigs */
+#define IMXDPUV1_TCON1_SMX11SIGS                             ((uint32_t)(0xE978))
+#define IMXDPUV1_TCON1_SMX11SIGS_OFFSET                      ((uint32_t)(0x178))
+#define IMXDPUV1_TCON1_SMX11SIGS_RESET_VALUE                 0U
+#define IMXDPUV1_TCON1_SMX11SIGS_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S0_MASK           0x7U
+#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S0_SHIFT          0U
+#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S1_MASK           0x38U
+#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S1_SHIFT          3U
+#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S2_MASK           0x1C0U
+#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S2_SHIFT          6U
+#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S3_MASK           0xE00U
+#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S3_SHIFT          9U
+#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S4_MASK           0x7000U
+#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S4_SHIFT          12U
+
+/* Register: IMXDPUV1_tcon1_SMx11FctTable */
+#define IMXDPUV1_TCON1_SMX11FCTTABLE                         ((uint32_t)(0xE97C))
+#define IMXDPUV1_TCON1_SMX11FCTTABLE_OFFSET                  ((uint32_t)(0x17C))
+#define IMXDPUV1_TCON1_SMX11FCTTABLE_RESET_VALUE             0U
+#define IMXDPUV1_TCON1_SMX11FCTTABLE_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX11FCTTABLE_SMXFCT11_MASK           0xFFFFFFFFU
+#define IMXDPUV1_TCON1_SMX11FCTTABLE_SMXFCT11_SHIFT          0U
+
+/* Register: IMXDPUV1_tcon1_Reset_Over_Unferflow */
+#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW                  ((uint32_t)(0xE980))
+#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_OFFSET           ((uint32_t)(0x180))
+#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_RESET_VALUE      0U
+#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_RESET_MASK       0xFFFFFFFFU
+#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_RESET_STATUS_MASK 0x1U
+#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_RESET_STATUS_SHIFT 0U
+
+/* Register: IMXDPUV1_tcon1_Dual_Debug */
+#define IMXDPUV1_TCON1_DUAL_DEBUG                            ((uint32_t)(0xE984))
+#define IMXDPUV1_TCON1_DUAL_DEBUG_OFFSET                     ((uint32_t)(0x184))
+#define IMXDPUV1_TCON1_DUAL_DEBUG_RESET_VALUE                0U
+#define IMXDPUV1_TCON1_DUAL_DEBUG_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_TCON1_DUAL_DEBUG_LOWER_FIFO_OVERFLOW_MASK   0x1U
+#define IMXDPUV1_TCON1_DUAL_DEBUG_LOWER_FIFO_OVERFLOW_SHIFT  0U
+#define IMXDPUV1_TCON1_DUAL_DEBUG_LOWER_FIFO_UNDERFLOW_MASK  0x2U
+#define IMXDPUV1_TCON1_DUAL_DEBUG_LOWER_FIFO_UNDERFLOW_SHIFT 1U
+#define IMXDPUV1_TCON1_DUAL_DEBUG_UPPER_FIFO_OVERFLOW_MASK   0x10U
+#define IMXDPUV1_TCON1_DUAL_DEBUG_UPPER_FIFO_OVERFLOW_SHIFT  4U
+#define IMXDPUV1_TCON1_DUAL_DEBUG_UPPER_FIFO_UNDERFLOW_MASK  0x20U
+#define IMXDPUV1_TCON1_DUAL_DEBUG_UPPER_FIFO_UNDERFLOW_SHIFT 5U
+
+/* Register: IMXDPUV1_sig1_LockUnlock */
+#define IMXDPUV1_SIG1_LOCKUNLOCK                             ((uint32_t)(0xEC00))
+#define IMXDPUV1_SIG1_LOCKUNLOCK_OFFSET                      ((uint32_t)(0))
+#define IMXDPUV1_SIG1_LOCKUNLOCK_RESET_VALUE                 0U
+#define IMXDPUV1_SIG1_LOCKUNLOCK_RESET_MASK                  0U
+#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK_SHIFT            0U
+/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When
+ * the counter value is null, lock protection is active. Reset counter value
+ * is 1.  */
+#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY        0x5651F763U
+/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max
+ * allowed value is 15.  */
+#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY      0x691DB936U
+/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled
+ * after reset.  */
+#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY   0xAEE95CDCU
+/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection.  */
+#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU
+/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status.
+ * Writing keys to this register has no more effect until reset.  */
+#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY      0xFBE8B1E6U
+
+/* Register: IMXDPUV1_sig1_LockStatus */
+#define IMXDPUV1_SIG1_LOCKSTATUS                             ((uint32_t)(0xEC04))
+#define IMXDPUV1_SIG1_LOCKSTATUS_OFFSET                      ((uint32_t)(0x4))
+#define IMXDPUV1_SIG1_LOCKSTATUS_RESET_VALUE                 0U
+#define IMXDPUV1_SIG1_LOCKSTATUS_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG1_LOCKSTATUS_LOCKSTATUS_MASK             0x1U
+#define IMXDPUV1_SIG1_LOCKSTATUS_LOCKSTATUS_SHIFT            0U
+#define IMXDPUV1_SIG1_LOCKSTATUS_PRIVILEGESTATUS_MASK        0x10U
+#define IMXDPUV1_SIG1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT       4U
+#define IMXDPUV1_SIG1_LOCKSTATUS_FREEZESTATUS_MASK           0x100U
+#define IMXDPUV1_SIG1_LOCKSTATUS_FREEZESTATUS_SHIFT          8U
+
+/* Register: IMXDPUV1_sig1_StaticControl */
+#define IMXDPUV1_SIG1_STATICCONTROL                          ((uint32_t)(0xEC08))
+#define IMXDPUV1_SIG1_STATICCONTROL_OFFSET                   ((uint32_t)(0x8))
+#define IMXDPUV1_SIG1_STATICCONTROL_RESET_VALUE              0x8000000U
+#define IMXDPUV1_SIG1_STATICCONTROL_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_SIG1_STATICCONTROL_SHDEN_MASK               0x1U
+#define IMXDPUV1_SIG1_STATICCONTROL_SHDEN_SHIFT              0U
+#define IMXDPUV1_SIG1_STATICCONTROL_SHDLDSEL_MASK            0x10U
+#define IMXDPUV1_SIG1_STATICCONTROL_SHDLDSEL_SHIFT           4U
+/* Field Value: SHDLDSEL__LOCAL, Shadows are loaded at start of frame for
+ * each evaluation window for which ShdLdReq has been set.  */
+#define IMXDPUV1_SIG1_STATICCONTROL_SHDLDSEL__LOCAL          0U
+/* Field Value: SHDLDSEL__GLOBAL, Shadows of all evaluation windows are loaded
+ * synchronous to the display stream (shadow load token received on
+ * frame input port).  */
+#define IMXDPUV1_SIG1_STATICCONTROL_SHDLDSEL__GLOBAL         0x1U
+#define IMXDPUV1_SIG1_STATICCONTROL_ERRTHRES_MASK            0xFF0000U
+#define IMXDPUV1_SIG1_STATICCONTROL_ERRTHRES_SHIFT           16U
+#define IMXDPUV1_SIG1_STATICCONTROL_ERRTHRESRESET_MASK       0xFF000000U
+#define IMXDPUV1_SIG1_STATICCONTROL_ERRTHRESRESET_SHIFT      24U
+
+/* Register: IMXDPUV1_sig1_PanicColor */
+#define IMXDPUV1_SIG1_PANICCOLOR                             ((uint32_t)(0xEC0C))
+#define IMXDPUV1_SIG1_PANICCOLOR_OFFSET                      ((uint32_t)(0xC))
+#define IMXDPUV1_SIG1_PANICCOLOR_RESET_VALUE                 0U
+#define IMXDPUV1_SIG1_PANICCOLOR_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG1_PANICCOLOR_PANICALPHA_MASK             0x80U
+#define IMXDPUV1_SIG1_PANICCOLOR_PANICALPHA_SHIFT            7U
+#define IMXDPUV1_SIG1_PANICCOLOR_PANICBLUE_MASK              0xFF00U
+#define IMXDPUV1_SIG1_PANICCOLOR_PANICBLUE_SHIFT             8U
+#define IMXDPUV1_SIG1_PANICCOLOR_PANICGREEN_MASK             0xFF0000U
+#define IMXDPUV1_SIG1_PANICCOLOR_PANICGREEN_SHIFT            16U
+#define IMXDPUV1_SIG1_PANICCOLOR_PANICRED_MASK               0xFF000000U
+#define IMXDPUV1_SIG1_PANICCOLOR_PANICRED_SHIFT              24U
+
+/* Register: IMXDPUV1_sig1_EvalControl0 */
+#define IMXDPUV1_SIG1_EVALCONTROL0                           ((uint32_t)(0xEC10))
+#define IMXDPUV1_SIG1_EVALCONTROL0_OFFSET                    ((uint32_t)(0x10))
+#define IMXDPUV1_SIG1_EVALCONTROL0_RESET_VALUE               0U
+#define IMXDPUV1_SIG1_EVALCONTROL0_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALCONTROL0_ENEVALWIN0_MASK           0x1U
+#define IMXDPUV1_SIG1_EVALCONTROL0_ENEVALWIN0_SHIFT          0U
+#define IMXDPUV1_SIG1_EVALCONTROL0_ENCRC0_MASK               0x2U
+#define IMXDPUV1_SIG1_EVALCONTROL0_ENCRC0_SHIFT              1U
+#define IMXDPUV1_SIG1_EVALCONTROL0_ALPHAMASK0_MASK           0x100U
+#define IMXDPUV1_SIG1_EVALCONTROL0_ALPHAMASK0_SHIFT          8U
+#define IMXDPUV1_SIG1_EVALCONTROL0_ALPHAINV0_MASK            0x200U
+#define IMXDPUV1_SIG1_EVALCONTROL0_ALPHAINV0_SHIFT           9U
+#define IMXDPUV1_SIG1_EVALCONTROL0_ENLOCALPANIC0_MASK        0x10000U
+#define IMXDPUV1_SIG1_EVALCONTROL0_ENLOCALPANIC0_SHIFT       16U
+#define IMXDPUV1_SIG1_EVALCONTROL0_ENGLOBALPANIC0_MASK       0x20000U
+#define IMXDPUV1_SIG1_EVALCONTROL0_ENGLOBALPANIC0_SHIFT      17U
+
+/* Register: IMXDPUV1_sig1_EvalUpperLeft0 */
+#define IMXDPUV1_SIG1_EVALUPPERLEFT0                         ((uint32_t)(0xEC14))
+#define IMXDPUV1_SIG1_EVALUPPERLEFT0_OFFSET                  ((uint32_t)(0x14))
+#define IMXDPUV1_SIG1_EVALUPPERLEFT0_RESET_VALUE             0U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT0_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALUPPERLEFT0_XEVALUPPERLEFT0_MASK    0x3FFFU
+#define IMXDPUV1_SIG1_EVALUPPERLEFT0_XEVALUPPERLEFT0_SHIFT   0U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT0_YEVALUPPERLEFT0_MASK    0x3FFF0000U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT0_YEVALUPPERLEFT0_SHIFT   16U
+
+/* Register: IMXDPUV1_sig1_EvalLowerRight0 */
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT0                        ((uint32_t)(0xEC18))
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_OFFSET                 ((uint32_t)(0x18))
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_RESET_VALUE            0U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_XEVALLOWERRIGHT0_MASK  0x3FFFU
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_XEVALLOWERRIGHT0_SHIFT 0U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_YEVALLOWERRIGHT0_MASK  0x3FFF0000U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_YEVALLOWERRIGHT0_SHIFT 16U
+
+/* Register: IMXDPUV1_sig1_SigCRCRedRef0 */
+#define IMXDPUV1_SIG1_SIGCRCREDREF0                          ((uint32_t)(0xEC1C))
+#define IMXDPUV1_SIG1_SIGCRCREDREF0_OFFSET                   ((uint32_t)(0x1C))
+#define IMXDPUV1_SIG1_SIGCRCREDREF0_RESET_VALUE              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF0_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF0_SIGCRCREDREF0_MASK       0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF0_SIGCRCREDREF0_SHIFT      0U
+
+/* Register: IMXDPUV1_sig1_SigCRCGreenRef0 */
+#define IMXDPUV1_SIG1_SIGCRCGREENREF0                        ((uint32_t)(0xEC20))
+#define IMXDPUV1_SIG1_SIGCRCGREENREF0_OFFSET                 ((uint32_t)(0x20))
+#define IMXDPUV1_SIG1_SIGCRCGREENREF0_RESET_VALUE            0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF0_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF0_SIGCRCGREENREF0_MASK   0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF0_SIGCRCGREENREF0_SHIFT  0U
+
+/* Register: IMXDPUV1_sig1_SigCRCBlueRef0 */
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF0                         ((uint32_t)(0xEC24))
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_OFFSET                  ((uint32_t)(0x24))
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_RESET_VALUE             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_SIGCRCBLUEREF0_MASK     0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_SIGCRCBLUEREF0_SHIFT    0U
+
+/* Register: IMXDPUV1_sig1_SigCRCRed0 */
+#define IMXDPUV1_SIG1_SIGCRCRED0                             ((uint32_t)(0xEC28))
+#define IMXDPUV1_SIG1_SIGCRCRED0_OFFSET                      ((uint32_t)(0x28))
+#define IMXDPUV1_SIG1_SIGCRCRED0_RESET_VALUE                 0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED0_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED0_SIGCRCRED0_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED0_SIGCRCRED0_SHIFT            0U
+
+/* Register: IMXDPUV1_sig1_SigCRCGreen0 */
+#define IMXDPUV1_SIG1_SIGCRCGREEN0                           ((uint32_t)(0xEC2C))
+#define IMXDPUV1_SIG1_SIGCRCGREEN0_OFFSET                    ((uint32_t)(0x2C))
+#define IMXDPUV1_SIG1_SIGCRCGREEN0_RESET_VALUE               0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN0_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN0_SIGCRCGREEN0_MASK         0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN0_SIGCRCGREEN0_SHIFT        0U
+
+/* Register: IMXDPUV1_sig1_SigCRCBlue0 */
+#define IMXDPUV1_SIG1_SIGCRCBLUE0                            ((uint32_t)(0xEC30))
+#define IMXDPUV1_SIG1_SIGCRCBLUE0_OFFSET                     ((uint32_t)(0x30))
+#define IMXDPUV1_SIG1_SIGCRCBLUE0_RESET_VALUE                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE0_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE0_SIGCRCBLUE0_MASK           0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE0_SIGCRCBLUE0_SHIFT          0U
+
+/* Register: IMXDPUV1_sig1_EvalControl1 */
+#define IMXDPUV1_SIG1_EVALCONTROL1                           ((uint32_t)(0xEC34))
+#define IMXDPUV1_SIG1_EVALCONTROL1_OFFSET                    ((uint32_t)(0x34))
+#define IMXDPUV1_SIG1_EVALCONTROL1_RESET_VALUE               0U
+#define IMXDPUV1_SIG1_EVALCONTROL1_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALCONTROL1_ENEVALWIN1_MASK           0x1U
+#define IMXDPUV1_SIG1_EVALCONTROL1_ENEVALWIN1_SHIFT          0U
+#define IMXDPUV1_SIG1_EVALCONTROL1_ENCRC1_MASK               0x2U
+#define IMXDPUV1_SIG1_EVALCONTROL1_ENCRC1_SHIFT              1U
+#define IMXDPUV1_SIG1_EVALCONTROL1_ALPHAMASK1_MASK           0x100U
+#define IMXDPUV1_SIG1_EVALCONTROL1_ALPHAMASK1_SHIFT          8U
+#define IMXDPUV1_SIG1_EVALCONTROL1_ALPHAINV1_MASK            0x200U
+#define IMXDPUV1_SIG1_EVALCONTROL1_ALPHAINV1_SHIFT           9U
+#define IMXDPUV1_SIG1_EVALCONTROL1_ENLOCALPANIC1_MASK        0x10000U
+#define IMXDPUV1_SIG1_EVALCONTROL1_ENLOCALPANIC1_SHIFT       16U
+#define IMXDPUV1_SIG1_EVALCONTROL1_ENGLOBALPANIC1_MASK       0x20000U
+#define IMXDPUV1_SIG1_EVALCONTROL1_ENGLOBALPANIC1_SHIFT      17U
+
+/* Register: IMXDPUV1_sig1_EvalUpperLeft1 */
+#define IMXDPUV1_SIG1_EVALUPPERLEFT1                         ((uint32_t)(0xEC38))
+#define IMXDPUV1_SIG1_EVALUPPERLEFT1_OFFSET                  ((uint32_t)(0x38))
+#define IMXDPUV1_SIG1_EVALUPPERLEFT1_RESET_VALUE             0U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT1_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALUPPERLEFT1_XEVALUPPERLEFT1_MASK    0x3FFFU
+#define IMXDPUV1_SIG1_EVALUPPERLEFT1_XEVALUPPERLEFT1_SHIFT   0U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT1_YEVALUPPERLEFT1_MASK    0x3FFF0000U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT1_YEVALUPPERLEFT1_SHIFT   16U
+
+/* Register: IMXDPUV1_sig1_EvalLowerRight1 */
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT1                        ((uint32_t)(0xEC3C))
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_OFFSET                 ((uint32_t)(0x3C))
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_RESET_VALUE            0U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_XEVALLOWERRIGHT1_MASK  0x3FFFU
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_XEVALLOWERRIGHT1_SHIFT 0U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_YEVALLOWERRIGHT1_MASK  0x3FFF0000U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_YEVALLOWERRIGHT1_SHIFT 16U
+
+/* Register: IMXDPUV1_sig1_SigCRCRedRef1 */
+#define IMXDPUV1_SIG1_SIGCRCREDREF1                          ((uint32_t)(0xEC40))
+#define IMXDPUV1_SIG1_SIGCRCREDREF1_OFFSET                   ((uint32_t)(0x40))
+#define IMXDPUV1_SIG1_SIGCRCREDREF1_RESET_VALUE              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF1_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF1_SIGCRCREDREF1_MASK       0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF1_SIGCRCREDREF1_SHIFT      0U
+
+/* Register: IMXDPUV1_sig1_SigCRCGreenRef1 */
+#define IMXDPUV1_SIG1_SIGCRCGREENREF1                        ((uint32_t)(0xEC44))
+#define IMXDPUV1_SIG1_SIGCRCGREENREF1_OFFSET                 ((uint32_t)(0x44))
+#define IMXDPUV1_SIG1_SIGCRCGREENREF1_RESET_VALUE            0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF1_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF1_SIGCRCGREENREF1_MASK   0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF1_SIGCRCGREENREF1_SHIFT  0U
+
+/* Register: IMXDPUV1_sig1_SigCRCBlueRef1 */
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF1                         ((uint32_t)(0xEC48))
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_OFFSET                  ((uint32_t)(0x48))
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_RESET_VALUE             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_SIGCRCBLUEREF1_MASK     0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_SIGCRCBLUEREF1_SHIFT    0U
+
+/* Register: IMXDPUV1_sig1_SigCRCRed1 */
+#define IMXDPUV1_SIG1_SIGCRCRED1                             ((uint32_t)(0xEC4C))
+#define IMXDPUV1_SIG1_SIGCRCRED1_OFFSET                      ((uint32_t)(0x4C))
+#define IMXDPUV1_SIG1_SIGCRCRED1_RESET_VALUE                 0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED1_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED1_SIGCRCRED1_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED1_SIGCRCRED1_SHIFT            0U
+
+/* Register: IMXDPUV1_sig1_SigCRCGreen1 */
+#define IMXDPUV1_SIG1_SIGCRCGREEN1                           ((uint32_t)(0xEC50))
+#define IMXDPUV1_SIG1_SIGCRCGREEN1_OFFSET                    ((uint32_t)(0x50))
+#define IMXDPUV1_SIG1_SIGCRCGREEN1_RESET_VALUE               0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN1_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN1_SIGCRCGREEN1_MASK         0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN1_SIGCRCGREEN1_SHIFT        0U
+
+/* Register: IMXDPUV1_sig1_SigCRCBlue1 */
+#define IMXDPUV1_SIG1_SIGCRCBLUE1                            ((uint32_t)(0xEC54))
+#define IMXDPUV1_SIG1_SIGCRCBLUE1_OFFSET                     ((uint32_t)(0x54))
+#define IMXDPUV1_SIG1_SIGCRCBLUE1_RESET_VALUE                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE1_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE1_SIGCRCBLUE1_MASK           0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE1_SIGCRCBLUE1_SHIFT          0U
+
+/* Register: IMXDPUV1_sig1_EvalControl2 */
+#define IMXDPUV1_SIG1_EVALCONTROL2                           ((uint32_t)(0xEC58))
+#define IMXDPUV1_SIG1_EVALCONTROL2_OFFSET                    ((uint32_t)(0x58))
+#define IMXDPUV1_SIG1_EVALCONTROL2_RESET_VALUE               0U
+#define IMXDPUV1_SIG1_EVALCONTROL2_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALCONTROL2_ENEVALWIN2_MASK           0x1U
+#define IMXDPUV1_SIG1_EVALCONTROL2_ENEVALWIN2_SHIFT          0U
+#define IMXDPUV1_SIG1_EVALCONTROL2_ENCRC2_MASK               0x2U
+#define IMXDPUV1_SIG1_EVALCONTROL2_ENCRC2_SHIFT              1U
+#define IMXDPUV1_SIG1_EVALCONTROL2_ALPHAMASK2_MASK           0x100U
+#define IMXDPUV1_SIG1_EVALCONTROL2_ALPHAMASK2_SHIFT          8U
+#define IMXDPUV1_SIG1_EVALCONTROL2_ALPHAINV2_MASK            0x200U
+#define IMXDPUV1_SIG1_EVALCONTROL2_ALPHAINV2_SHIFT           9U
+#define IMXDPUV1_SIG1_EVALCONTROL2_ENLOCALPANIC2_MASK        0x10000U
+#define IMXDPUV1_SIG1_EVALCONTROL2_ENLOCALPANIC2_SHIFT       16U
+#define IMXDPUV1_SIG1_EVALCONTROL2_ENGLOBALPANIC2_MASK       0x20000U
+#define IMXDPUV1_SIG1_EVALCONTROL2_ENGLOBALPANIC2_SHIFT      17U
+
+/* Register: IMXDPUV1_sig1_EvalUpperLeft2 */
+#define IMXDPUV1_SIG1_EVALUPPERLEFT2                         ((uint32_t)(0xEC5C))
+#define IMXDPUV1_SIG1_EVALUPPERLEFT2_OFFSET                  ((uint32_t)(0x5C))
+#define IMXDPUV1_SIG1_EVALUPPERLEFT2_RESET_VALUE             0U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT2_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALUPPERLEFT2_XEVALUPPERLEFT2_MASK    0x3FFFU
+#define IMXDPUV1_SIG1_EVALUPPERLEFT2_XEVALUPPERLEFT2_SHIFT   0U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT2_YEVALUPPERLEFT2_MASK    0x3FFF0000U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT2_YEVALUPPERLEFT2_SHIFT   16U
+
+/* Register: IMXDPUV1_sig1_EvalLowerRight2 */
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT2                        ((uint32_t)(0xEC60))
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_OFFSET                 ((uint32_t)(0x60))
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_RESET_VALUE            0U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_XEVALLOWERRIGHT2_MASK  0x3FFFU
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_XEVALLOWERRIGHT2_SHIFT 0U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_YEVALLOWERRIGHT2_MASK  0x3FFF0000U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_YEVALLOWERRIGHT2_SHIFT 16U
+
+/* Register: IMXDPUV1_sig1_SigCRCRedRef2 */
+#define IMXDPUV1_SIG1_SIGCRCREDREF2                          ((uint32_t)(0xEC64))
+#define IMXDPUV1_SIG1_SIGCRCREDREF2_OFFSET                   ((uint32_t)(0x64))
+#define IMXDPUV1_SIG1_SIGCRCREDREF2_RESET_VALUE              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF2_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF2_SIGCRCREDREF2_MASK       0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF2_SIGCRCREDREF2_SHIFT      0U
+
+/* Register: IMXDPUV1_sig1_SigCRCGreenRef2 */
+#define IMXDPUV1_SIG1_SIGCRCGREENREF2                        ((uint32_t)(0xEC68))
+#define IMXDPUV1_SIG1_SIGCRCGREENREF2_OFFSET                 ((uint32_t)(0x68))
+#define IMXDPUV1_SIG1_SIGCRCGREENREF2_RESET_VALUE            0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF2_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF2_SIGCRCGREENREF2_MASK   0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF2_SIGCRCGREENREF2_SHIFT  0U
+
+/* Register: IMXDPUV1_sig1_SigCRCBlueRef2 */
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF2                         ((uint32_t)(0xEC6C))
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_OFFSET                  ((uint32_t)(0x6C))
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_RESET_VALUE             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_SIGCRCBLUEREF2_MASK     0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_SIGCRCBLUEREF2_SHIFT    0U
+
+/* Register: IMXDPUV1_sig1_SigCRCRed2 */
+#define IMXDPUV1_SIG1_SIGCRCRED2                             ((uint32_t)(0xEC70))
+#define IMXDPUV1_SIG1_SIGCRCRED2_OFFSET                      ((uint32_t)(0x70))
+#define IMXDPUV1_SIG1_SIGCRCRED2_RESET_VALUE                 0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED2_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED2_SIGCRCRED2_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED2_SIGCRCRED2_SHIFT            0U
+
+/* Register: IMXDPUV1_sig1_SigCRCGreen2 */
+#define IMXDPUV1_SIG1_SIGCRCGREEN2                           ((uint32_t)(0xEC74))
+#define IMXDPUV1_SIG1_SIGCRCGREEN2_OFFSET                    ((uint32_t)(0x74))
+#define IMXDPUV1_SIG1_SIGCRCGREEN2_RESET_VALUE               0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN2_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN2_SIGCRCGREEN2_MASK         0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN2_SIGCRCGREEN2_SHIFT        0U
+
+/* Register: IMXDPUV1_sig1_SigCRCBlue2 */
+#define IMXDPUV1_SIG1_SIGCRCBLUE2                            ((uint32_t)(0xEC78))
+#define IMXDPUV1_SIG1_SIGCRCBLUE2_OFFSET                     ((uint32_t)(0x78))
+#define IMXDPUV1_SIG1_SIGCRCBLUE2_RESET_VALUE                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE2_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE2_SIGCRCBLUE2_MASK           0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE2_SIGCRCBLUE2_SHIFT          0U
+
+/* Register: IMXDPUV1_sig1_EvalControl3 */
+#define IMXDPUV1_SIG1_EVALCONTROL3                           ((uint32_t)(0xEC7C))
+#define IMXDPUV1_SIG1_EVALCONTROL3_OFFSET                    ((uint32_t)(0x7C))
+#define IMXDPUV1_SIG1_EVALCONTROL3_RESET_VALUE               0U
+#define IMXDPUV1_SIG1_EVALCONTROL3_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALCONTROL3_ENEVALWIN3_MASK           0x1U
+#define IMXDPUV1_SIG1_EVALCONTROL3_ENEVALWIN3_SHIFT          0U
+#define IMXDPUV1_SIG1_EVALCONTROL3_ENCRC3_MASK               0x2U
+#define IMXDPUV1_SIG1_EVALCONTROL3_ENCRC3_SHIFT              1U
+#define IMXDPUV1_SIG1_EVALCONTROL3_ALPHAMASK3_MASK           0x100U
+#define IMXDPUV1_SIG1_EVALCONTROL3_ALPHAMASK3_SHIFT          8U
+#define IMXDPUV1_SIG1_EVALCONTROL3_ALPHAINV3_MASK            0x200U
+#define IMXDPUV1_SIG1_EVALCONTROL3_ALPHAINV3_SHIFT           9U
+#define IMXDPUV1_SIG1_EVALCONTROL3_ENLOCALPANIC3_MASK        0x10000U
+#define IMXDPUV1_SIG1_EVALCONTROL3_ENLOCALPANIC3_SHIFT       16U
+#define IMXDPUV1_SIG1_EVALCONTROL3_ENGLOBALPANIC3_MASK       0x20000U
+#define IMXDPUV1_SIG1_EVALCONTROL3_ENGLOBALPANIC3_SHIFT      17U
+
+/* Register: IMXDPUV1_sig1_EvalUpperLeft3 */
+#define IMXDPUV1_SIG1_EVALUPPERLEFT3                         ((uint32_t)(0xEC80))
+#define IMXDPUV1_SIG1_EVALUPPERLEFT3_OFFSET                  ((uint32_t)(0x80))
+#define IMXDPUV1_SIG1_EVALUPPERLEFT3_RESET_VALUE             0U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT3_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALUPPERLEFT3_XEVALUPPERLEFT3_MASK    0x3FFFU
+#define IMXDPUV1_SIG1_EVALUPPERLEFT3_XEVALUPPERLEFT3_SHIFT   0U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT3_YEVALUPPERLEFT3_MASK    0x3FFF0000U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT3_YEVALUPPERLEFT3_SHIFT   16U
+
+/* Register: IMXDPUV1_sig1_EvalLowerRight3 */
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT3                        ((uint32_t)(0xEC84))
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_OFFSET                 ((uint32_t)(0x84))
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_RESET_VALUE            0U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_XEVALLOWERRIGHT3_MASK  0x3FFFU
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_XEVALLOWERRIGHT3_SHIFT 0U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_YEVALLOWERRIGHT3_MASK  0x3FFF0000U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_YEVALLOWERRIGHT3_SHIFT 16U
+
+/* Register: IMXDPUV1_sig1_SigCRCRedRef3 */
+#define IMXDPUV1_SIG1_SIGCRCREDREF3                          ((uint32_t)(0xEC88))
+#define IMXDPUV1_SIG1_SIGCRCREDREF3_OFFSET                   ((uint32_t)(0x88))
+#define IMXDPUV1_SIG1_SIGCRCREDREF3_RESET_VALUE              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF3_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF3_SIGCRCREDREF3_MASK       0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF3_SIGCRCREDREF3_SHIFT      0U
+
+/* Register: IMXDPUV1_sig1_SigCRCGreenRef3 */
+#define IMXDPUV1_SIG1_SIGCRCGREENREF3                        ((uint32_t)(0xEC8C))
+#define IMXDPUV1_SIG1_SIGCRCGREENREF3_OFFSET                 ((uint32_t)(0x8C))
+#define IMXDPUV1_SIG1_SIGCRCGREENREF3_RESET_VALUE            0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF3_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF3_SIGCRCGREENREF3_MASK   0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF3_SIGCRCGREENREF3_SHIFT  0U
+
+/* Register: IMXDPUV1_sig1_SigCRCBlueRef3 */
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF3                         ((uint32_t)(0xEC90))
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_OFFSET                  ((uint32_t)(0x90))
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_RESET_VALUE             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_SIGCRCBLUEREF3_MASK     0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_SIGCRCBLUEREF3_SHIFT    0U
+
+/* Register: IMXDPUV1_sig1_SigCRCRed3 */
+#define IMXDPUV1_SIG1_SIGCRCRED3                             ((uint32_t)(0xEC94))
+#define IMXDPUV1_SIG1_SIGCRCRED3_OFFSET                      ((uint32_t)(0x94))
+#define IMXDPUV1_SIG1_SIGCRCRED3_RESET_VALUE                 0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED3_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED3_SIGCRCRED3_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED3_SIGCRCRED3_SHIFT            0U
+
+/* Register: IMXDPUV1_sig1_SigCRCGreen3 */
+#define IMXDPUV1_SIG1_SIGCRCGREEN3                           ((uint32_t)(0xEC98))
+#define IMXDPUV1_SIG1_SIGCRCGREEN3_OFFSET                    ((uint32_t)(0x98))
+#define IMXDPUV1_SIG1_SIGCRCGREEN3_RESET_VALUE               0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN3_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN3_SIGCRCGREEN3_MASK         0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN3_SIGCRCGREEN3_SHIFT        0U
+
+/* Register: IMXDPUV1_sig1_SigCRCBlue3 */
+#define IMXDPUV1_SIG1_SIGCRCBLUE3                            ((uint32_t)(0xEC9C))
+#define IMXDPUV1_SIG1_SIGCRCBLUE3_OFFSET                     ((uint32_t)(0x9C))
+#define IMXDPUV1_SIG1_SIGCRCBLUE3_RESET_VALUE                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE3_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE3_SIGCRCBLUE3_MASK           0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE3_SIGCRCBLUE3_SHIFT          0U
+
+/* Register: IMXDPUV1_sig1_EvalControl4 */
+#define IMXDPUV1_SIG1_EVALCONTROL4                           ((uint32_t)(0xECA0))
+#define IMXDPUV1_SIG1_EVALCONTROL4_OFFSET                    ((uint32_t)(0xA0))
+#define IMXDPUV1_SIG1_EVALCONTROL4_RESET_VALUE               0U
+#define IMXDPUV1_SIG1_EVALCONTROL4_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALCONTROL4_ENEVALWIN4_MASK           0x1U
+#define IMXDPUV1_SIG1_EVALCONTROL4_ENEVALWIN4_SHIFT          0U
+#define IMXDPUV1_SIG1_EVALCONTROL4_ENCRC4_MASK               0x2U
+#define IMXDPUV1_SIG1_EVALCONTROL4_ENCRC4_SHIFT              1U
+#define IMXDPUV1_SIG1_EVALCONTROL4_ALPHAMASK4_MASK           0x100U
+#define IMXDPUV1_SIG1_EVALCONTROL4_ALPHAMASK4_SHIFT          8U
+#define IMXDPUV1_SIG1_EVALCONTROL4_ALPHAINV4_MASK            0x200U
+#define IMXDPUV1_SIG1_EVALCONTROL4_ALPHAINV4_SHIFT           9U
+#define IMXDPUV1_SIG1_EVALCONTROL4_ENLOCALPANIC4_MASK        0x10000U
+#define IMXDPUV1_SIG1_EVALCONTROL4_ENLOCALPANIC4_SHIFT       16U
+#define IMXDPUV1_SIG1_EVALCONTROL4_ENGLOBALPANIC4_MASK       0x20000U
+#define IMXDPUV1_SIG1_EVALCONTROL4_ENGLOBALPANIC4_SHIFT      17U
+
+/* Register: IMXDPUV1_sig1_EvalUpperLeft4 */
+#define IMXDPUV1_SIG1_EVALUPPERLEFT4                         ((uint32_t)(0xECA4))
+#define IMXDPUV1_SIG1_EVALUPPERLEFT4_OFFSET                  ((uint32_t)(0xA4))
+#define IMXDPUV1_SIG1_EVALUPPERLEFT4_RESET_VALUE             0U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT4_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALUPPERLEFT4_XEVALUPPERLEFT4_MASK    0x3FFFU
+#define IMXDPUV1_SIG1_EVALUPPERLEFT4_XEVALUPPERLEFT4_SHIFT   0U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT4_YEVALUPPERLEFT4_MASK    0x3FFF0000U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT4_YEVALUPPERLEFT4_SHIFT   16U
+
+/* Register: IMXDPUV1_sig1_EvalLowerRight4 */
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT4                        ((uint32_t)(0xECA8))
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_OFFSET                 ((uint32_t)(0xA8))
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_RESET_VALUE            0U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_XEVALLOWERRIGHT4_MASK  0x3FFFU
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_XEVALLOWERRIGHT4_SHIFT 0U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_YEVALLOWERRIGHT4_MASK  0x3FFF0000U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_YEVALLOWERRIGHT4_SHIFT 16U
+
+/* Register: IMXDPUV1_sig1_SigCRCRedRef4 */
+#define IMXDPUV1_SIG1_SIGCRCREDREF4                          ((uint32_t)(0xECAC))
+#define IMXDPUV1_SIG1_SIGCRCREDREF4_OFFSET                   ((uint32_t)(0xAC))
+#define IMXDPUV1_SIG1_SIGCRCREDREF4_RESET_VALUE              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF4_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF4_SIGCRCREDREF4_MASK       0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF4_SIGCRCREDREF4_SHIFT      0U
+
+/* Register: IMXDPUV1_sig1_SigCRCGreenRef4 */
+#define IMXDPUV1_SIG1_SIGCRCGREENREF4                        ((uint32_t)(0xECB0))
+#define IMXDPUV1_SIG1_SIGCRCGREENREF4_OFFSET                 ((uint32_t)(0xB0))
+#define IMXDPUV1_SIG1_SIGCRCGREENREF4_RESET_VALUE            0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF4_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF4_SIGCRCGREENREF4_MASK   0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF4_SIGCRCGREENREF4_SHIFT  0U
+
+/* Register: IMXDPUV1_sig1_SigCRCBlueRef4 */
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF4                         ((uint32_t)(0xECB4))
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_OFFSET                  ((uint32_t)(0xB4))
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_RESET_VALUE             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_SIGCRCBLUEREF4_MASK     0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_SIGCRCBLUEREF4_SHIFT    0U
+
+/* Register: IMXDPUV1_sig1_SigCRCRed4 */
+#define IMXDPUV1_SIG1_SIGCRCRED4                             ((uint32_t)(0xECB8))
+#define IMXDPUV1_SIG1_SIGCRCRED4_OFFSET                      ((uint32_t)(0xB8))
+#define IMXDPUV1_SIG1_SIGCRCRED4_RESET_VALUE                 0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED4_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED4_SIGCRCRED4_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED4_SIGCRCRED4_SHIFT            0U
+
+/* Register: IMXDPUV1_sig1_SigCRCGreen4 */
+#define IMXDPUV1_SIG1_SIGCRCGREEN4                           ((uint32_t)(0xECBC))
+#define IMXDPUV1_SIG1_SIGCRCGREEN4_OFFSET                    ((uint32_t)(0xBC))
+#define IMXDPUV1_SIG1_SIGCRCGREEN4_RESET_VALUE               0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN4_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN4_SIGCRCGREEN4_MASK         0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN4_SIGCRCGREEN4_SHIFT        0U
+
+/* Register: IMXDPUV1_sig1_SigCRCBlue4 */
+#define IMXDPUV1_SIG1_SIGCRCBLUE4                            ((uint32_t)(0xECC0))
+#define IMXDPUV1_SIG1_SIGCRCBLUE4_OFFSET                     ((uint32_t)(0xC0))
+#define IMXDPUV1_SIG1_SIGCRCBLUE4_RESET_VALUE                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE4_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE4_SIGCRCBLUE4_MASK           0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE4_SIGCRCBLUE4_SHIFT          0U
+
+/* Register: IMXDPUV1_sig1_EvalControl5 */
+#define IMXDPUV1_SIG1_EVALCONTROL5                           ((uint32_t)(0xECC4))
+#define IMXDPUV1_SIG1_EVALCONTROL5_OFFSET                    ((uint32_t)(0xC4))
+#define IMXDPUV1_SIG1_EVALCONTROL5_RESET_VALUE               0U
+#define IMXDPUV1_SIG1_EVALCONTROL5_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALCONTROL5_ENEVALWIN5_MASK           0x1U
+#define IMXDPUV1_SIG1_EVALCONTROL5_ENEVALWIN5_SHIFT          0U
+#define IMXDPUV1_SIG1_EVALCONTROL5_ENCRC5_MASK               0x2U
+#define IMXDPUV1_SIG1_EVALCONTROL5_ENCRC5_SHIFT              1U
+#define IMXDPUV1_SIG1_EVALCONTROL5_ALPHAMASK5_MASK           0x100U
+#define IMXDPUV1_SIG1_EVALCONTROL5_ALPHAMASK5_SHIFT          8U
+#define IMXDPUV1_SIG1_EVALCONTROL5_ALPHAINV5_MASK            0x200U
+#define IMXDPUV1_SIG1_EVALCONTROL5_ALPHAINV5_SHIFT           9U
+#define IMXDPUV1_SIG1_EVALCONTROL5_ENLOCALPANIC5_MASK        0x10000U
+#define IMXDPUV1_SIG1_EVALCONTROL5_ENLOCALPANIC5_SHIFT       16U
+#define IMXDPUV1_SIG1_EVALCONTROL5_ENGLOBALPANIC5_MASK       0x20000U
+#define IMXDPUV1_SIG1_EVALCONTROL5_ENGLOBALPANIC5_SHIFT      17U
+
+/* Register: IMXDPUV1_sig1_EvalUpperLeft5 */
+#define IMXDPUV1_SIG1_EVALUPPERLEFT5                         ((uint32_t)(0xECC8))
+#define IMXDPUV1_SIG1_EVALUPPERLEFT5_OFFSET                  ((uint32_t)(0xC8))
+#define IMXDPUV1_SIG1_EVALUPPERLEFT5_RESET_VALUE             0U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT5_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALUPPERLEFT5_XEVALUPPERLEFT5_MASK    0x3FFFU
+#define IMXDPUV1_SIG1_EVALUPPERLEFT5_XEVALUPPERLEFT5_SHIFT   0U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT5_YEVALUPPERLEFT5_MASK    0x3FFF0000U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT5_YEVALUPPERLEFT5_SHIFT   16U
+
+/* Register: IMXDPUV1_sig1_EvalLowerRight5 */
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT5                        ((uint32_t)(0xECCC))
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_OFFSET                 ((uint32_t)(0xCC))
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_RESET_VALUE            0U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_XEVALLOWERRIGHT5_MASK  0x3FFFU
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_XEVALLOWERRIGHT5_SHIFT 0U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_YEVALLOWERRIGHT5_MASK  0x3FFF0000U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_YEVALLOWERRIGHT5_SHIFT 16U
+
+/* Register: IMXDPUV1_sig1_SigCRCRedRef5 */
+#define IMXDPUV1_SIG1_SIGCRCREDREF5                          ((uint32_t)(0xECD0))
+#define IMXDPUV1_SIG1_SIGCRCREDREF5_OFFSET                   ((uint32_t)(0xD0))
+#define IMXDPUV1_SIG1_SIGCRCREDREF5_RESET_VALUE              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF5_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF5_SIGCRCREDREF5_MASK       0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF5_SIGCRCREDREF5_SHIFT      0U
+
+/* Register: IMXDPUV1_sig1_SigCRCGreenRef5 */
+#define IMXDPUV1_SIG1_SIGCRCGREENREF5                        ((uint32_t)(0xECD4))
+#define IMXDPUV1_SIG1_SIGCRCGREENREF5_OFFSET                 ((uint32_t)(0xD4))
+#define IMXDPUV1_SIG1_SIGCRCGREENREF5_RESET_VALUE            0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF5_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF5_SIGCRCGREENREF5_MASK   0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF5_SIGCRCGREENREF5_SHIFT  0U
+
+/* Register: IMXDPUV1_sig1_SigCRCBlueRef5 */
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF5                         ((uint32_t)(0xECD8))
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_OFFSET                  ((uint32_t)(0xD8))
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_RESET_VALUE             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_SIGCRCBLUEREF5_MASK     0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_SIGCRCBLUEREF5_SHIFT    0U
+
+/* Register: IMXDPUV1_sig1_SigCRCRed5 */
+#define IMXDPUV1_SIG1_SIGCRCRED5                             ((uint32_t)(0xECDC))
+#define IMXDPUV1_SIG1_SIGCRCRED5_OFFSET                      ((uint32_t)(0xDC))
+#define IMXDPUV1_SIG1_SIGCRCRED5_RESET_VALUE                 0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED5_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED5_SIGCRCRED5_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED5_SIGCRCRED5_SHIFT            0U
+
+/* Register: IMXDPUV1_sig1_SigCRCGreen5 */
+#define IMXDPUV1_SIG1_SIGCRCGREEN5                           ((uint32_t)(0xECE0))
+#define IMXDPUV1_SIG1_SIGCRCGREEN5_OFFSET                    ((uint32_t)(0xE0))
+#define IMXDPUV1_SIG1_SIGCRCGREEN5_RESET_VALUE               0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN5_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN5_SIGCRCGREEN5_MASK         0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN5_SIGCRCGREEN5_SHIFT        0U
+
+/* Register: IMXDPUV1_sig1_SigCRCBlue5 */
+#define IMXDPUV1_SIG1_SIGCRCBLUE5                            ((uint32_t)(0xECE4))
+#define IMXDPUV1_SIG1_SIGCRCBLUE5_OFFSET                     ((uint32_t)(0xE4))
+#define IMXDPUV1_SIG1_SIGCRCBLUE5_RESET_VALUE                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE5_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE5_SIGCRCBLUE5_MASK           0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE5_SIGCRCBLUE5_SHIFT          0U
+
+/* Register: IMXDPUV1_sig1_EvalControl6 */
+#define IMXDPUV1_SIG1_EVALCONTROL6                           ((uint32_t)(0xECE8))
+#define IMXDPUV1_SIG1_EVALCONTROL6_OFFSET                    ((uint32_t)(0xE8))
+#define IMXDPUV1_SIG1_EVALCONTROL6_RESET_VALUE               0U
+#define IMXDPUV1_SIG1_EVALCONTROL6_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALCONTROL6_ENEVALWIN6_MASK           0x1U
+#define IMXDPUV1_SIG1_EVALCONTROL6_ENEVALWIN6_SHIFT          0U
+#define IMXDPUV1_SIG1_EVALCONTROL6_ENCRC6_MASK               0x2U
+#define IMXDPUV1_SIG1_EVALCONTROL6_ENCRC6_SHIFT              1U
+#define IMXDPUV1_SIG1_EVALCONTROL6_ALPHAMASK6_MASK           0x100U
+#define IMXDPUV1_SIG1_EVALCONTROL6_ALPHAMASK6_SHIFT          8U
+#define IMXDPUV1_SIG1_EVALCONTROL6_ALPHAINV6_MASK            0x200U
+#define IMXDPUV1_SIG1_EVALCONTROL6_ALPHAINV6_SHIFT           9U
+#define IMXDPUV1_SIG1_EVALCONTROL6_ENLOCALPANIC6_MASK        0x10000U
+#define IMXDPUV1_SIG1_EVALCONTROL6_ENLOCALPANIC6_SHIFT       16U
+#define IMXDPUV1_SIG1_EVALCONTROL6_ENGLOBALPANIC6_MASK       0x20000U
+#define IMXDPUV1_SIG1_EVALCONTROL6_ENGLOBALPANIC6_SHIFT      17U
+
+/* Register: IMXDPUV1_sig1_EvalUpperLeft6 */
+#define IMXDPUV1_SIG1_EVALUPPERLEFT6                         ((uint32_t)(0xECEC))
+#define IMXDPUV1_SIG1_EVALUPPERLEFT6_OFFSET                  ((uint32_t)(0xEC))
+#define IMXDPUV1_SIG1_EVALUPPERLEFT6_RESET_VALUE             0U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT6_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALUPPERLEFT6_XEVALUPPERLEFT6_MASK    0x3FFFU
+#define IMXDPUV1_SIG1_EVALUPPERLEFT6_XEVALUPPERLEFT6_SHIFT   0U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT6_YEVALUPPERLEFT6_MASK    0x3FFF0000U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT6_YEVALUPPERLEFT6_SHIFT   16U
+
+/* Register: IMXDPUV1_sig1_EvalLowerRight6 */
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT6                        ((uint32_t)(0xECF0))
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_OFFSET                 ((uint32_t)(0xF0))
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_RESET_VALUE            0U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_XEVALLOWERRIGHT6_MASK  0x3FFFU
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_XEVALLOWERRIGHT6_SHIFT 0U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_YEVALLOWERRIGHT6_MASK  0x3FFF0000U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_YEVALLOWERRIGHT6_SHIFT 16U
+
+/* Register: IMXDPUV1_sig1_SigCRCRedRef6 */
+#define IMXDPUV1_SIG1_SIGCRCREDREF6                          ((uint32_t)(0xECF4))
+#define IMXDPUV1_SIG1_SIGCRCREDREF6_OFFSET                   ((uint32_t)(0xF4))
+#define IMXDPUV1_SIG1_SIGCRCREDREF6_RESET_VALUE              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF6_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF6_SIGCRCREDREF6_MASK       0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF6_SIGCRCREDREF6_SHIFT      0U
+
+/* Register: IMXDPUV1_sig1_SigCRCGreenRef6 */
+#define IMXDPUV1_SIG1_SIGCRCGREENREF6                        ((uint32_t)(0xECF8))
+#define IMXDPUV1_SIG1_SIGCRCGREENREF6_OFFSET                 ((uint32_t)(0xF8))
+#define IMXDPUV1_SIG1_SIGCRCGREENREF6_RESET_VALUE            0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF6_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF6_SIGCRCGREENREF6_MASK   0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF6_SIGCRCGREENREF6_SHIFT  0U
+
+/* Register: IMXDPUV1_sig1_SigCRCBlueRef6 */
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF6                         ((uint32_t)(0xECFC))
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_OFFSET                  ((uint32_t)(0xFC))
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_RESET_VALUE             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_SIGCRCBLUEREF6_MASK     0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_SIGCRCBLUEREF6_SHIFT    0U
+
+/* Register: IMXDPUV1_sig1_SigCRCRed6 */
+#define IMXDPUV1_SIG1_SIGCRCRED6                             ((uint32_t)(0xED00))
+#define IMXDPUV1_SIG1_SIGCRCRED6_OFFSET                      ((uint32_t)(0x100))
+#define IMXDPUV1_SIG1_SIGCRCRED6_RESET_VALUE                 0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED6_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED6_SIGCRCRED6_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED6_SIGCRCRED6_SHIFT            0U
+
+/* Register: IMXDPUV1_sig1_SigCRCGreen6 */
+#define IMXDPUV1_SIG1_SIGCRCGREEN6                           ((uint32_t)(0xED04))
+#define IMXDPUV1_SIG1_SIGCRCGREEN6_OFFSET                    ((uint32_t)(0x104))
+#define IMXDPUV1_SIG1_SIGCRCGREEN6_RESET_VALUE               0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN6_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN6_SIGCRCGREEN6_MASK         0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN6_SIGCRCGREEN6_SHIFT        0U
+
+/* Register: IMXDPUV1_sig1_SigCRCBlue6 */
+#define IMXDPUV1_SIG1_SIGCRCBLUE6                            ((uint32_t)(0xED08))
+#define IMXDPUV1_SIG1_SIGCRCBLUE6_OFFSET                     ((uint32_t)(0x108))
+#define IMXDPUV1_SIG1_SIGCRCBLUE6_RESET_VALUE                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE6_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE6_SIGCRCBLUE6_MASK           0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE6_SIGCRCBLUE6_SHIFT          0U
+
+/* Register: IMXDPUV1_sig1_EvalControl7 */
+#define IMXDPUV1_SIG1_EVALCONTROL7                           ((uint32_t)(0xED0C))
+#define IMXDPUV1_SIG1_EVALCONTROL7_OFFSET                    ((uint32_t)(0x10C))
+#define IMXDPUV1_SIG1_EVALCONTROL7_RESET_VALUE               0U
+#define IMXDPUV1_SIG1_EVALCONTROL7_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALCONTROL7_ENEVALWIN7_MASK           0x1U
+#define IMXDPUV1_SIG1_EVALCONTROL7_ENEVALWIN7_SHIFT          0U
+#define IMXDPUV1_SIG1_EVALCONTROL7_ENCRC7_MASK               0x2U
+#define IMXDPUV1_SIG1_EVALCONTROL7_ENCRC7_SHIFT              1U
+#define IMXDPUV1_SIG1_EVALCONTROL7_ALPHAMASK7_MASK           0x100U
+#define IMXDPUV1_SIG1_EVALCONTROL7_ALPHAMASK7_SHIFT          8U
+#define IMXDPUV1_SIG1_EVALCONTROL7_ALPHAINV7_MASK            0x200U
+#define IMXDPUV1_SIG1_EVALCONTROL7_ALPHAINV7_SHIFT           9U
+#define IMXDPUV1_SIG1_EVALCONTROL7_ENLOCALPANIC7_MASK        0x10000U
+#define IMXDPUV1_SIG1_EVALCONTROL7_ENLOCALPANIC7_SHIFT       16U
+#define IMXDPUV1_SIG1_EVALCONTROL7_ENGLOBALPANIC7_MASK       0x20000U
+#define IMXDPUV1_SIG1_EVALCONTROL7_ENGLOBALPANIC7_SHIFT      17U
+
+/* Register: IMXDPUV1_sig1_EvalUpperLeft7 */
+#define IMXDPUV1_SIG1_EVALUPPERLEFT7                         ((uint32_t)(0xED10))
+#define IMXDPUV1_SIG1_EVALUPPERLEFT7_OFFSET                  ((uint32_t)(0x110))
+#define IMXDPUV1_SIG1_EVALUPPERLEFT7_RESET_VALUE             0U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT7_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALUPPERLEFT7_XEVALUPPERLEFT7_MASK    0x3FFFU
+#define IMXDPUV1_SIG1_EVALUPPERLEFT7_XEVALUPPERLEFT7_SHIFT   0U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT7_YEVALUPPERLEFT7_MASK    0x3FFF0000U
+#define IMXDPUV1_SIG1_EVALUPPERLEFT7_YEVALUPPERLEFT7_SHIFT   16U
+
+/* Register: IMXDPUV1_sig1_EvalLowerRight7 */
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT7                        ((uint32_t)(0xED14))
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_OFFSET                 ((uint32_t)(0x114))
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_RESET_VALUE            0U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_XEVALLOWERRIGHT7_MASK  0x3FFFU
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_XEVALLOWERRIGHT7_SHIFT 0U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_YEVALLOWERRIGHT7_MASK  0x3FFF0000U
+#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_YEVALLOWERRIGHT7_SHIFT 16U
+
+/* Register: IMXDPUV1_sig1_SigCRCRedRef7 */
+#define IMXDPUV1_SIG1_SIGCRCREDREF7                          ((uint32_t)(0xED18))
+#define IMXDPUV1_SIG1_SIGCRCREDREF7_OFFSET                   ((uint32_t)(0x118))
+#define IMXDPUV1_SIG1_SIGCRCREDREF7_RESET_VALUE              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF7_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF7_SIGCRCREDREF7_MASK       0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCREDREF7_SIGCRCREDREF7_SHIFT      0U
+
+/* Register: IMXDPUV1_sig1_SigCRCGreenRef7 */
+#define IMXDPUV1_SIG1_SIGCRCGREENREF7                        ((uint32_t)(0xED1C))
+#define IMXDPUV1_SIG1_SIGCRCGREENREF7_OFFSET                 ((uint32_t)(0x11C))
+#define IMXDPUV1_SIG1_SIGCRCGREENREF7_RESET_VALUE            0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF7_RESET_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF7_SIGCRCGREENREF7_MASK   0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREENREF7_SIGCRCGREENREF7_SHIFT  0U
+
+/* Register: IMXDPUV1_sig1_SigCRCBlueRef7 */
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF7                         ((uint32_t)(0xED20))
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_OFFSET                  ((uint32_t)(0x120))
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_RESET_VALUE             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_SIGCRCBLUEREF7_MASK     0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_SIGCRCBLUEREF7_SHIFT    0U
+
+/* Register: IMXDPUV1_sig1_SigCRCRed7 */
+#define IMXDPUV1_SIG1_SIGCRCRED7                             ((uint32_t)(0xED24))
+#define IMXDPUV1_SIG1_SIGCRCRED7_OFFSET                      ((uint32_t)(0x124))
+#define IMXDPUV1_SIG1_SIGCRCRED7_RESET_VALUE                 0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED7_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED7_SIGCRCRED7_MASK             0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCRED7_SIGCRCRED7_SHIFT            0U
+
+/* Register: IMXDPUV1_sig1_SigCRCGreen7 */
+#define IMXDPUV1_SIG1_SIGCRCGREEN7                           ((uint32_t)(0xED28))
+#define IMXDPUV1_SIG1_SIGCRCGREEN7_OFFSET                    ((uint32_t)(0x128))
+#define IMXDPUV1_SIG1_SIGCRCGREEN7_RESET_VALUE               0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN7_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN7_SIGCRCGREEN7_MASK         0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCGREEN7_SIGCRCGREEN7_SHIFT        0U
+
+/* Register: IMXDPUV1_sig1_SigCRCBlue7 */
+#define IMXDPUV1_SIG1_SIGCRCBLUE7                            ((uint32_t)(0xED2C))
+#define IMXDPUV1_SIG1_SIGCRCBLUE7_OFFSET                     ((uint32_t)(0x12C))
+#define IMXDPUV1_SIG1_SIGCRCBLUE7_RESET_VALUE                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE7_RESET_MASK                 0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE7_SIGCRCBLUE7_MASK           0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SIGCRCBLUE7_SIGCRCBLUE7_SHIFT          0U
+
+/* Register: IMXDPUV1_sig1_ShadowLoad */
+#define IMXDPUV1_SIG1_SHADOWLOAD                             ((uint32_t)(0xED30))
+#define IMXDPUV1_SIG1_SHADOWLOAD_OFFSET                      ((uint32_t)(0x130))
+#define IMXDPUV1_SIG1_SHADOWLOAD_RESET_VALUE                 0U
+#define IMXDPUV1_SIG1_SHADOWLOAD_RESET_MASK                  0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SHADOWLOAD_SHDLDREQ_MASK               0xFFU
+#define IMXDPUV1_SIG1_SHADOWLOAD_SHDLDREQ_SHIFT              0U
+
+/* Register: IMXDPUV1_sig1_ContinuousMode */
+#define IMXDPUV1_SIG1_CONTINUOUSMODE                         ((uint32_t)(0xED34))
+#define IMXDPUV1_SIG1_CONTINUOUSMODE_OFFSET                  ((uint32_t)(0x134))
+#define IMXDPUV1_SIG1_CONTINUOUSMODE_RESET_VALUE             0U
+#define IMXDPUV1_SIG1_CONTINUOUSMODE_RESET_MASK              0xFFFFFFFFU
+#define IMXDPUV1_SIG1_CONTINUOUSMODE_ENCONT_MASK             0x1U
+#define IMXDPUV1_SIG1_CONTINUOUSMODE_ENCONT_SHIFT            0U
+
+/* Register: IMXDPUV1_sig1_SoftwareKick */
+#define IMXDPUV1_SIG1_SOFTWAREKICK                           ((uint32_t)(0xED38))
+#define IMXDPUV1_SIG1_SOFTWAREKICK_OFFSET                    ((uint32_t)(0x138))
+#define IMXDPUV1_SIG1_SOFTWAREKICK_RESET_VALUE               0U
+#define IMXDPUV1_SIG1_SOFTWAREKICK_RESET_MASK                0xFFFFFFFFU
+#define IMXDPUV1_SIG1_SOFTWAREKICK_KICK_MASK                 0x1U
+#define IMXDPUV1_SIG1_SOFTWAREKICK_KICK_SHIFT                0U
+
+/* Register: IMXDPUV1_sig1_Status */
+#define IMXDPUV1_SIG1_STATUS                                 ((uint32_t)(0xED3C))
+#define IMXDPUV1_SIG1_STATUS_OFFSET                          ((uint32_t)(0x13C))
+#define IMXDPUV1_SIG1_STATUS_RESET_VALUE                     0x100000U
+#define IMXDPUV1_SIG1_STATUS_RESET_MASK                      0xFFFFFFFFU
+#define IMXDPUV1_SIG1_STATUS_STSSIGERROR_MASK                0xFFU
+#define IMXDPUV1_SIG1_STATUS_STSSIGERROR_SHIFT               0U
+#define IMXDPUV1_SIG1_STATUS_STSSIGVALID_MASK                0x10000U
+#define IMXDPUV1_SIG1_STATUS_STSSIGVALID_SHIFT               16U
+#define IMXDPUV1_SIG1_STATUS_STSSIGIDLE_MASK                 0x100000U
+#define IMXDPUV1_SIG1_STATUS_STSSIGIDLE_SHIFT                20U
+
+/* Register: IMXDPUV1_DPUXPC_Control */
+#define IMXDPUV1_DPUXPC_CONTROL                              ((uint32_t)(0xF000))
+#define IMXDPUV1_DPUXPC_CONTROL_OFFSET                       ((uint32_t)(0))
+#define IMXDPUV1_DPUXPC_CONTROL_RESET_VALUE                  0U
+#define IMXDPUV1_DPUXPC_CONTROL_RESET_MASK                   0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_CONTROL_ENABLE_MASK                  0x1U
+#define IMXDPUV1_DPUXPC_CONTROL_ENABLE_SHIFT                 0U
+#define IMXDPUV1_DPUXPC_CONTROL_MODE_MASK                    0x6U
+#define IMXDPUV1_DPUXPC_CONTROL_MODE_SHIFT                   1U
+/* Field Value: MODE__XPC_MODE_MANUAL, Manual measurement end  */
+#define IMXDPUV1_DPUXPC_CONTROL_MODE__XPC_MODE_MANUAL        0U
+/* Field Value: MODE__XPC_MODE_TIMER, Timer controlled measurement end  */
+#define IMXDPUV1_DPUXPC_CONTROL_MODE__XPC_MODE_TIMER         0x1U
+/* Field Value: MODE__XPC_MODE_CONTINUOUS, Continuous measurement; retriggered
+ * by reading SW_Tag register  */
+#define IMXDPUV1_DPUXPC_CONTROL_MODE__XPC_MODE_CONTINUOUS    0x2U
+#define IMXDPUV1_DPUXPC_CONTROL_INCREMENTMODE_MASK           0x40000000U
+#define IMXDPUV1_DPUXPC_CONTROL_INCREMENTMODE_SHIFT          30U
+#define IMXDPUV1_DPUXPC_CONTROL_OTCDISABLE_MASK              0x80000000U
+#define IMXDPUV1_DPUXPC_CONTROL_OTCDISABLE_SHIFT             31U
+
+/* Register: IMXDPUV1_DPUXPC_Timer */
+#define IMXDPUV1_DPUXPC_TIMER                                ((uint32_t)(0xF004))
+#define IMXDPUV1_DPUXPC_TIMER_OFFSET                         ((uint32_t)(0x4))
+#define IMXDPUV1_DPUXPC_TIMER_RESET_VALUE                    0xFFFFFFFU
+#define IMXDPUV1_DPUXPC_TIMER_RESET_MASK                     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_TIMER_LOAD_MASK                      0xFFFFFFFU
+#define IMXDPUV1_DPUXPC_TIMER_LOAD_SHIFT                     0U
+#define IMXDPUV1_DPUXPC_TIMER_DIVIDER_MASK                   0xF0000000U
+#define IMXDPUV1_DPUXPC_TIMER_DIVIDER_SHIFT                  28U
+
+/* Register: IMXDPUV1_DPUXPC_MeasurementTimeControl */
+#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL               ((uint32_t)(0xF008))
+#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_OFFSET        ((uint32_t)(0x8))
+#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_RESET_VALUE   0U
+#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_RESET_MASK    0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_MTDIVIDER_MASK 0xFFFFFU
+#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_MTDIVIDER_SHIFT 0U
+#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_MTENABLE_MASK 0x80000000U
+#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_MTENABLE_SHIFT 31U
+
+/* Register: IMXDPUV1_DPUXPC_SW_Tag */
+#define IMXDPUV1_DPUXPC_SW_TAG                               ((uint32_t)(0xF00C))
+#define IMXDPUV1_DPUXPC_SW_TAG_OFFSET                        ((uint32_t)(0xC))
+#define IMXDPUV1_DPUXPC_SW_TAG_RESET_VALUE                   0U
+#define IMXDPUV1_DPUXPC_SW_TAG_RESET_MASK                    0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_SW_TAG_TAG_MASK                      0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_SW_TAG_TAG_SHIFT                     0U
+
+/* Register: IMXDPUV1_DPUXPC_MeasurementTime */
+#define IMXDPUV1_DPUXPC_MEASUREMENTTIME                      ((uint32_t)(0xF010))
+#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_OFFSET               ((uint32_t)(0x10))
+#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_RESET_VALUE          0U
+#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_RESET_MASK           0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_TIME_MASK            0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_TIME_SHIFT           0U
+
+/* Register: IMXDPUV1_DPUXPC_Global_Counter */
+#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER                       ((uint32_t)(0xF014))
+#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_OFFSET                ((uint32_t)(0x14))
+#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_RESET_VALUE           0U
+#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_RESET_MASK            0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_GLOBAL_MASK           0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_GLOBAL_SHIFT          0U
+
+/* Register: IMXDPUV1_DPUXPC_MU00_Switch */
+#define IMXDPUV1_DPUXPC_MU00_SWITCH                          ((uint32_t)(0xF018))
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_OFFSET                   ((uint32_t)(0x18))
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_RESET_VALUE              0U
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT_MASK         0x1FU
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT_SHIFT        0U
+/* Field Value: MU00_SELECT__MU00_OTC00, cmdseq read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC00  0U
+/* Field Value: MU00_SELECT__MU00_OTC01, cmdseq write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC01  0x1U
+/* Field Value: MU00_SELECT__MU00_OTC02, fetchdecode9 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC02  0x2U
+/* Field Value: MU00_SELECT__MU00_OTC03, fetchpersp9 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC03  0x3U
+/* Field Value: MU00_SELECT__MU00_OTC04, fetcheco9 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC04  0x4U
+/* Field Value: MU00_SELECT__MU00_OTC05, fetchdecode2 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC05  0x5U
+/* Field Value: MU00_SELECT__MU00_OTC06, fetchdecode3 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC06  0x6U
+/* Field Value: MU00_SELECT__MU00_OTC07, fetchwarp2 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC07  0x7U
+/* Field Value: MU00_SELECT__MU00_OTC08, fetcheco2 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC08  0x8U
+/* Field Value: MU00_SELECT__MU00_OTC09, fetchdecode0 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC09  0x9U
+/* Field Value: MU00_SELECT__MU00_OTC10, fetcheco0 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC10  0xAU
+/* Field Value: MU00_SELECT__MU00_OTC11, fetchdecode1 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC11  0xBU
+/* Field Value: MU00_SELECT__MU00_OTC12, fetcheco1 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC12  0xCU
+/* Field Value: MU00_SELECT__MU00_OTC13, fetchlayer0 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC13  0xDU
+/* Field Value: MU00_SELECT__MU00_OTC14, fetchlayer1 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC14  0xEU
+/* Field Value: MU00_SELECT__MU00_OTC15, store9 write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC15  0xFU
+/* Field Value: MU00_SELECT__MU00_OTC16, store4 write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC16  0x10U
+/* Field Value: MU00_SELECT__MU00_OTC17, store5 write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC17  0x11U
+
+/* Register: IMXDPUV1_DPUXPC_MU00_Data_Counter */
+#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER                    ((uint32_t)(0xF01C))
+#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_OFFSET             ((uint32_t)(0x1C))
+#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_RESET_VALUE        0U
+#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_MU00_DATA_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_MU00_DATA_SHIFT    0U
+
+/* Register: IMXDPUV1_DPUXPC_MU00_Busy_Counter */
+#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER                    ((uint32_t)(0xF020))
+#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_OFFSET             ((uint32_t)(0x20))
+#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_RESET_VALUE        0U
+#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_MU00_BUSY_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_MU00_BUSY_SHIFT    0U
+
+/* Register: IMXDPUV1_DPUXPC_MU00_Transfer_Counter */
+#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER                ((uint32_t)(0xF024))
+#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_OFFSET         ((uint32_t)(0x24))
+#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_RESET_VALUE    0U
+#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_MU00_TRANSFER_MASK 0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_MU00_TRANSFER_SHIFT 0U
+
+/* Register: IMXDPUV1_DPUXPC_MU00_Addrbusy_Counter */
+#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER                ((uint32_t)(0xF028))
+#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_OFFSET         ((uint32_t)(0x28))
+#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_RESET_VALUE    0U
+#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_MU00_ADDRBUSY_MASK 0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_MU00_ADDRBUSY_SHIFT 0U
+
+/* Register: IMXDPUV1_DPUXPC_MU00_Latency_Counter */
+#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER                 ((uint32_t)(0xF02C))
+#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_OFFSET          ((uint32_t)(0x2C))
+#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_RESET_VALUE     0U
+#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_MU00_LATENCY_MASK 0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_MU00_LATENCY_SHIFT 0U
+
+/* Register: IMXDPUV1_DPUXPC_MU01_Switch */
+#define IMXDPUV1_DPUXPC_MU01_SWITCH                          ((uint32_t)(0xF030))
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_OFFSET                   ((uint32_t)(0x30))
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_RESET_VALUE              0x1U
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT_MASK         0x1FU
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT_SHIFT        0U
+/* Field Value: MU01_SELECT__MU01_OTC00, cmdseq read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC00  0U
+/* Field Value: MU01_SELECT__MU01_OTC01, cmdseq write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC01  0x1U
+/* Field Value: MU01_SELECT__MU01_OTC02, fetchdecode9 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC02  0x2U
+/* Field Value: MU01_SELECT__MU01_OTC03, fetchpersp9 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC03  0x3U
+/* Field Value: MU01_SELECT__MU01_OTC04, fetcheco9 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC04  0x4U
+/* Field Value: MU01_SELECT__MU01_OTC05, fetchdecode2 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC05  0x5U
+/* Field Value: MU01_SELECT__MU01_OTC06, fetchdecode3 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC06  0x6U
+/* Field Value: MU01_SELECT__MU01_OTC07, fetchwarp2 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC07  0x7U
+/* Field Value: MU01_SELECT__MU01_OTC08, fetcheco2 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC08  0x8U
+/* Field Value: MU01_SELECT__MU01_OTC09, fetchdecode0 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC09  0x9U
+/* Field Value: MU01_SELECT__MU01_OTC10, fetcheco0 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC10  0xAU
+/* Field Value: MU01_SELECT__MU01_OTC11, fetchdecode1 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC11  0xBU
+/* Field Value: MU01_SELECT__MU01_OTC12, fetcheco1 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC12  0xCU
+/* Field Value: MU01_SELECT__MU01_OTC13, fetchlayer0 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC13  0xDU
+/* Field Value: MU01_SELECT__MU01_OTC14, fetchlayer1 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC14  0xEU
+/* Field Value: MU01_SELECT__MU01_OTC15, store9 write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC15  0xFU
+/* Field Value: MU01_SELECT__MU01_OTC16, store4 write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC16  0x10U
+/* Field Value: MU01_SELECT__MU01_OTC17, store5 write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC17  0x11U
+
+/* Register: IMXDPUV1_DPUXPC_MU01_Data_Counter */
+#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER                    ((uint32_t)(0xF034))
+#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_OFFSET             ((uint32_t)(0x34))
+#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_RESET_VALUE        0U
+#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_MU01_DATA_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_MU01_DATA_SHIFT    0U
+
+/* Register: IMXDPUV1_DPUXPC_MU01_Busy_Counter */
+#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER                    ((uint32_t)(0xF038))
+#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_OFFSET             ((uint32_t)(0x38))
+#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_RESET_VALUE        0U
+#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_MU01_BUSY_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_MU01_BUSY_SHIFT    0U
+
+/* Register: IMXDPUV1_DPUXPC_MU01_Transfer_Counter */
+#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER                ((uint32_t)(0xF03C))
+#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_OFFSET         ((uint32_t)(0x3C))
+#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_RESET_VALUE    0U
+#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_MU01_TRANSFER_MASK 0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_MU01_TRANSFER_SHIFT 0U
+
+/* Register: IMXDPUV1_DPUXPC_MU01_Addrbusy_Counter */
+#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER                ((uint32_t)(0xF040))
+#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_OFFSET         ((uint32_t)(0x40))
+#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_RESET_VALUE    0U
+#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_MU01_ADDRBUSY_MASK 0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_MU01_ADDRBUSY_SHIFT 0U
+
+/* Register: IMXDPUV1_DPUXPC_MU01_Latency_Counter */
+#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER                 ((uint32_t)(0xF044))
+#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_OFFSET          ((uint32_t)(0x44))
+#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_RESET_VALUE     0U
+#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_MU01_LATENCY_MASK 0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_MU01_LATENCY_SHIFT 0U
+
+/* Register: IMXDPUV1_DPUXPC_MU02_Switch */
+#define IMXDPUV1_DPUXPC_MU02_SWITCH                          ((uint32_t)(0xF048))
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_OFFSET                   ((uint32_t)(0x48))
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_RESET_VALUE              0x2U
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT_MASK         0x1FU
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT_SHIFT        0U
+/* Field Value: MU02_SELECT__MU02_OTC00, cmdseq read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC00  0U
+/* Field Value: MU02_SELECT__MU02_OTC01, cmdseq write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC01  0x1U
+/* Field Value: MU02_SELECT__MU02_OTC02, fetchdecode9 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC02  0x2U
+/* Field Value: MU02_SELECT__MU02_OTC03, fetchpersp9 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC03  0x3U
+/* Field Value: MU02_SELECT__MU02_OTC04, fetcheco9 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC04  0x4U
+/* Field Value: MU02_SELECT__MU02_OTC05, fetchdecode2 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC05  0x5U
+/* Field Value: MU02_SELECT__MU02_OTC06, fetchdecode3 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC06  0x6U
+/* Field Value: MU02_SELECT__MU02_OTC07, fetchwarp2 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC07  0x7U
+/* Field Value: MU02_SELECT__MU02_OTC08, fetcheco2 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC08  0x8U
+/* Field Value: MU02_SELECT__MU02_OTC09, fetchdecode0 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC09  0x9U
+/* Field Value: MU02_SELECT__MU02_OTC10, fetcheco0 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC10  0xAU
+/* Field Value: MU02_SELECT__MU02_OTC11, fetchdecode1 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC11  0xBU
+/* Field Value: MU02_SELECT__MU02_OTC12, fetcheco1 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC12  0xCU
+/* Field Value: MU02_SELECT__MU02_OTC13, fetchlayer0 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC13  0xDU
+/* Field Value: MU02_SELECT__MU02_OTC14, fetchlayer1 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC14  0xEU
+/* Field Value: MU02_SELECT__MU02_OTC15, store9 write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC15  0xFU
+/* Field Value: MU02_SELECT__MU02_OTC16, store4 write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC16  0x10U
+/* Field Value: MU02_SELECT__MU02_OTC17, store5 write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC17  0x11U
+
+/* Register: IMXDPUV1_DPUXPC_MU02_Data_Counter */
+#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER                    ((uint32_t)(0xF04C))
+#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_OFFSET             ((uint32_t)(0x4C))
+#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_RESET_VALUE        0U
+#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_MU02_DATA_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_MU02_DATA_SHIFT    0U
+
+/* Register: IMXDPUV1_DPUXPC_MU02_Busy_Counter */
+#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER                    ((uint32_t)(0xF050))
+#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_OFFSET             ((uint32_t)(0x50))
+#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_RESET_VALUE        0U
+#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_MU02_BUSY_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_MU02_BUSY_SHIFT    0U
+
+/* Register: IMXDPUV1_DPUXPC_MU02_Transfer_Counter */
+#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER                ((uint32_t)(0xF054))
+#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_OFFSET         ((uint32_t)(0x54))
+#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_RESET_VALUE    0U
+#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_MU02_TRANSFER_MASK 0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_MU02_TRANSFER_SHIFT 0U
+
+/* Register: IMXDPUV1_DPUXPC_MU02_Addrbusy_Counter */
+#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER                ((uint32_t)(0xF058))
+#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_OFFSET         ((uint32_t)(0x58))
+#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_RESET_VALUE    0U
+#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_MU02_ADDRBUSY_MASK 0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_MU02_ADDRBUSY_SHIFT 0U
+
+/* Register: IMXDPUV1_DPUXPC_MU02_Latency_Counter */
+#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER                 ((uint32_t)(0xF05C))
+#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_OFFSET          ((uint32_t)(0x5C))
+#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_RESET_VALUE     0U
+#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_MU02_LATENCY_MASK 0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_MU02_LATENCY_SHIFT 0U
+
+/* Register: IMXDPUV1_DPUXPC_MU03_Switch */
+#define IMXDPUV1_DPUXPC_MU03_SWITCH                          ((uint32_t)(0xF060))
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_OFFSET                   ((uint32_t)(0x60))
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_RESET_VALUE              0x3U
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT_MASK         0x1FU
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT_SHIFT        0U
+/* Field Value: MU03_SELECT__MU03_OTC00, cmdseq read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC00  0U
+/* Field Value: MU03_SELECT__MU03_OTC01, cmdseq write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC01  0x1U
+/* Field Value: MU03_SELECT__MU03_OTC02, fetchdecode9 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC02  0x2U
+/* Field Value: MU03_SELECT__MU03_OTC03, fetchpersp9 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC03  0x3U
+/* Field Value: MU03_SELECT__MU03_OTC04, fetcheco9 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC04  0x4U
+/* Field Value: MU03_SELECT__MU03_OTC05, fetchdecode2 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC05  0x5U
+/* Field Value: MU03_SELECT__MU03_OTC06, fetchdecode3 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC06  0x6U
+/* Field Value: MU03_SELECT__MU03_OTC07, fetchwarp2 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC07  0x7U
+/* Field Value: MU03_SELECT__MU03_OTC08, fetcheco2 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC08  0x8U
+/* Field Value: MU03_SELECT__MU03_OTC09, fetchdecode0 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC09  0x9U
+/* Field Value: MU03_SELECT__MU03_OTC10, fetcheco0 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC10  0xAU
+/* Field Value: MU03_SELECT__MU03_OTC11, fetchdecode1 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC11  0xBU
+/* Field Value: MU03_SELECT__MU03_OTC12, fetcheco1 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC12  0xCU
+/* Field Value: MU03_SELECT__MU03_OTC13, fetchlayer0 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC13  0xDU
+/* Field Value: MU03_SELECT__MU03_OTC14, fetchlayer1 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC14  0xEU
+/* Field Value: MU03_SELECT__MU03_OTC15, store9 write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC15  0xFU
+/* Field Value: MU03_SELECT__MU03_OTC16, store4 write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC16  0x10U
+/* Field Value: MU03_SELECT__MU03_OTC17, store5 write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC17  0x11U
+
+/* Register: IMXDPUV1_DPUXPC_MU03_Data_Counter */
+#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER                    ((uint32_t)(0xF064))
+#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_OFFSET             ((uint32_t)(0x64))
+#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_RESET_VALUE        0U
+#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_MU03_DATA_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_MU03_DATA_SHIFT    0U
+
+/* Register: IMXDPUV1_DPUXPC_MU03_Busy_Counter */
+#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER                    ((uint32_t)(0xF068))
+#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_OFFSET             ((uint32_t)(0x68))
+#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_RESET_VALUE        0U
+#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_MU03_BUSY_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_MU03_BUSY_SHIFT    0U
+
+/* Register: IMXDPUV1_DPUXPC_MU03_Transfer_Counter */
+#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER                ((uint32_t)(0xF06C))
+#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_OFFSET         ((uint32_t)(0x6C))
+#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_RESET_VALUE    0U
+#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_MU03_TRANSFER_MASK 0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_MU03_TRANSFER_SHIFT 0U
+
+/* Register: IMXDPUV1_DPUXPC_MU03_Addrbusy_Counter */
+#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER                ((uint32_t)(0xF070))
+#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_OFFSET         ((uint32_t)(0x70))
+#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_RESET_VALUE    0U
+#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_MU03_ADDRBUSY_MASK 0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_MU03_ADDRBUSY_SHIFT 0U
+
+/* Register: IMXDPUV1_DPUXPC_MU03_Latency_Counter */
+#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER                 ((uint32_t)(0xF074))
+#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_OFFSET          ((uint32_t)(0x74))
+#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_RESET_VALUE     0U
+#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_MU03_LATENCY_MASK 0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_MU03_LATENCY_SHIFT 0U
+
+/* Register: IMXDPUV1_DPUXPC_MU04_Switch */
+#define IMXDPUV1_DPUXPC_MU04_SWITCH                          ((uint32_t)(0xF078))
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_OFFSET                   ((uint32_t)(0x78))
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_RESET_VALUE              0x4U
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_RESET_MASK               0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT_MASK         0x1FU
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT_SHIFT        0U
+/* Field Value: MU04_SELECT__MU04_OTC00, cmdseq read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC00  0U
+/* Field Value: MU04_SELECT__MU04_OTC01, cmdseq write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC01  0x1U
+/* Field Value: MU04_SELECT__MU04_OTC02, fetchdecode9 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC02  0x2U
+/* Field Value: MU04_SELECT__MU04_OTC03, fetchpersp9 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC03  0x3U
+/* Field Value: MU04_SELECT__MU04_OTC04, fetcheco9 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC04  0x4U
+/* Field Value: MU04_SELECT__MU04_OTC05, fetchdecode2 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC05  0x5U
+/* Field Value: MU04_SELECT__MU04_OTC06, fetchdecode3 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC06  0x6U
+/* Field Value: MU04_SELECT__MU04_OTC07, fetchwarp2 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC07  0x7U
+/* Field Value: MU04_SELECT__MU04_OTC08, fetcheco2 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC08  0x8U
+/* Field Value: MU04_SELECT__MU04_OTC09, fetchdecode0 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC09  0x9U
+/* Field Value: MU04_SELECT__MU04_OTC10, fetcheco0 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC10  0xAU
+/* Field Value: MU04_SELECT__MU04_OTC11, fetchdecode1 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC11  0xBU
+/* Field Value: MU04_SELECT__MU04_OTC12, fetcheco1 read direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC12  0xCU
+/* Field Value: MU04_SELECT__MU04_OTC13, fetchlayer0 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC13  0xDU
+/* Field Value: MU04_SELECT__MU04_OTC14, fetchlayer1 read direction (ACLK
+ * clock)  */
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC14  0xEU
+/* Field Value: MU04_SELECT__MU04_OTC15, store9 write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC15  0xFU
+/* Field Value: MU04_SELECT__MU04_OTC16, store4 write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC16  0x10U
+/* Field Value: MU04_SELECT__MU04_OTC17, store5 write direction (ACLK clock)  */
+#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC17  0x11U
+
+/* Register: IMXDPUV1_DPUXPC_MU04_Data_Counter */
+#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER                    ((uint32_t)(0xF07C))
+#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_OFFSET             ((uint32_t)(0x7C))
+#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_RESET_VALUE        0U
+#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_MU04_DATA_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_MU04_DATA_SHIFT    0U
+
+/* Register: IMXDPUV1_DPUXPC_MU04_Busy_Counter */
+#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER                    ((uint32_t)(0xF080))
+#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_OFFSET             ((uint32_t)(0x80))
+#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_RESET_VALUE        0U
+#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_RESET_MASK         0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_MU04_BUSY_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_MU04_BUSY_SHIFT    0U
+
+/* Register: IMXDPUV1_DPUXPC_MU04_Transfer_Counter */
+#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER                ((uint32_t)(0xF084))
+#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_OFFSET         ((uint32_t)(0x84))
+#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_RESET_VALUE    0U
+#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_MU04_TRANSFER_MASK 0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_MU04_TRANSFER_SHIFT 0U
+
+/* Register: IMXDPUV1_DPUXPC_MU04_Addrbusy_Counter */
+#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER                ((uint32_t)(0xF088))
+#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_OFFSET         ((uint32_t)(0x88))
+#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_RESET_VALUE    0U
+#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_RESET_MASK     0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_MU04_ADDRBUSY_MASK 0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_MU04_ADDRBUSY_SHIFT 0U
+
+/* Register: IMXDPUV1_DPUXPC_MU04_Latency_Counter */
+#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER                 ((uint32_t)(0xF08C))
+#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_OFFSET          ((uint32_t)(0x8C))
+#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_RESET_VALUE     0U
+#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_RESET_MASK      0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_MU04_LATENCY_MASK 0xFFFFFFFFU
+#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_MU04_LATENCY_SHIFT 0U
+
+#endif /* IMXDPUV1_REGISTERS_H */
diff --git a/include/init.h b/include/init.h
index 20c3976af09..e54a14590b8 100644
--- a/include/init.h
+++ b/include/init.h
@@ -281,6 +281,10 @@ int init_func_vid(void);
 int checkboard(void);
 int show_board_info(void);
 
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+void get_reboot_reason(char *ret);
+#endif
+
 /**
  * Get the uppermost pointer that is valid to access
  *
diff --git a/include/interface/avb/avb.h b/include/interface/avb/avb.h
new file mode 100644
index 00000000000..f9da80c21d7
--- /dev/null
+++ b/include/interface/avb/avb.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef TRUSTY_INTERFACE_AVB_H_
+#define TRUSTY_INTERFACE_AVB_H_
+
+#include <trusty/sysdeps.h>
+
+#define AVB_PORT "com.android.trusty.avb"
+#define AVB_MAX_BUFFER_LENGTH 2048
+
+enum avb_command {
+    AVB_REQ_SHIFT = 1,
+    AVB_RESP_BIT  = 1,
+
+    READ_ROLLBACK_INDEX        = (0 << AVB_REQ_SHIFT),
+    WRITE_ROLLBACK_INDEX       = (1 << AVB_REQ_SHIFT),
+    AVB_GET_VERSION            = (2 << AVB_REQ_SHIFT),
+    READ_PERMANENT_ATTRIBUTES  = (3 << AVB_REQ_SHIFT),
+    WRITE_PERMANENT_ATTRIBUTES = (4 << AVB_REQ_SHIFT),
+    READ_LOCK_STATE            = (5 << AVB_REQ_SHIFT),
+    WRITE_LOCK_STATE           = (6 << AVB_REQ_SHIFT),
+    LOCK_BOOT_STATE            = (7 << AVB_REQ_SHIFT),
+    READ_VBMETA_PUBLIC_KEY     = (8 << AVB_REQ_SHIFT),
+    WRITE_VBMETA_PUBLIC_KEY    = (9 << AVB_REQ_SHIFT),
+    WRITE_OEM_UNLOCK_DEVICE_PERMISSION     = (10 << AVB_REQ_SHIFT),
+    READ_OEM_UNLOCK_DEVICE_PERMISSION      = (11 << AVB_REQ_SHIFT),
+};
+
+/**
+ * enum avb_error - error codes for AVB protocol
+ * @AVB_ERROR_NONE:         All OK
+ * @AVB_ERROR_INVALID:      Invalid input
+ * @AVB_ERROR_INTERNAL:     Error occurred during an operation in Trusty
+ */
+enum avb_error {
+    AVB_ERROR_NONE     = 0,
+    AVB_ERROR_INVALID  = 1,
+    AVB_ERROR_INTERNAL = 2,
+};
+
+/**
+ * avb_message - Serial header for communicating with AVB server
+ * @cmd:     the command. Payload must be a serialized buffer of the
+ *           corresponding request object.
+ * @result:  resulting error code for message, one of avb_error.
+ * @payload: start of the serialized command specific payload
+ */
+struct avb_message {
+    uint32_t cmd;
+    uint32_t result;
+    uint8_t payload[0];
+};
+
+/**
+ * avb_rollback_req - request format for [READ|WRITE]_ROLLBACK_INDEX
+ * @value: value to write to rollback index. Ignored for read.
+ * @slot:  slot number of rollback index to write
+ */
+struct avb_rollback_req {
+    uint64_t value;
+    uint32_t slot;
+} TRUSTY_ATTR_PACKED;
+
+/**
+ * avb_rollback_resp - response format for [READ|WRITE]_ROLLBACK_INDEX.
+ * @value: value of the requested rollback index.
+ */
+struct avb_rollback_resp {
+    uint64_t value;
+};
+
+/**
+ * avb_get_version_resp - response format for AVB_GET_VERSION.
+ * @version: version of AVB message format
+ */
+struct avb_get_version_resp {
+    uint32_t version;
+};
+
+#endif /* TRUSTY_INTERFACE_AVB_H_ */
diff --git a/include/interface/hwcrypto/hwcrypto.h b/include/interface/hwcrypto/hwcrypto.h
new file mode 100644
index 00000000000..0bfb2136895
--- /dev/null
+++ b/include/interface/hwcrypto/hwcrypto.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ * Copyright NXP 2018
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+
+#ifndef TRUSTY_INTERFACE_HWCRYPTO_H_
+#define TRUSTY_INTERFACE_HWCRYPTO_H_
+
+#include <trusty/sysdeps.h>
+
+#define HWCRYPTO_PORT "com.android.trusty.hwcrypto"
+#define HWCRYPTO_MAX_BUFFER_LENGTH 2048
+
+enum hwcrypto_command {
+    HWCRYPTO_REQ_SHIFT = 1,
+    HWCRYPTO_RESP_BIT  = 1,
+
+    HWCRYPTO_HASH            = (1 << HWCRYPTO_REQ_SHIFT),
+    HWCRYPTO_ENCAP_BLOB      = (2 << HWCRYPTO_REQ_SHIFT),
+    HWCRYPTO_GEN_RNG         = (3 << HWCRYPTO_REQ_SHIFT),
+    HWCRYPTO_GEN_BKEK        = (4 << HWCRYPTO_REQ_SHIFT),
+    HWCRYPTO_LOCK_BOOT_STATE = (5 << HWCRYPTO_REQ_SHIFT),
+    HWCRYPTO_PROVISION_WV_KEY = (6 << HWCRYPTO_REQ_SHIFT),
+    HWCRYPTO_PROVISION_WV_KEY_ENC = (7 << HWCRYPTO_REQ_SHIFT),
+};
+
+/**
+ * enum hwcrypto_error - error codes for HWCRYPTO protocol
+ * @HWCRYPTO_ERROR_NONE:         All OK
+ * @HWCRYPTO_ERROR_INVALID:      Invalid input
+ * @HWCRYPTO_ERROR_INTERNAL:     Error occurred during an operation in Trusty
+ */
+enum hwcrypto_error {
+    HWCRYPTO_ERROR_NONE     = 0,
+    HWCRYPTO_ERROR_INVALID  = 1,
+    HWCRYPTO_ERROR_INTERNAL = 2,
+};
+
+enum hwcrypto_hash_algo {
+    SHA1 = 0,
+    SHA256
+};
+/**
+ * hwcrypto_message - Serial header for communicating with hwcrypto server
+ * @cmd:     the command. Payload must be a serialized buffer of the
+ *           corresponding request object.
+ * @result:  resulting error code for message, one of hwcrypto_error.
+ * @payload: start of the serialized command specific payload
+ */
+struct hwcrypto_message {
+    uint32_t cmd;
+    uint32_t result;
+    uint8_t payload[0];
+};
+
+/**
+ * hwcrypto_hash_msg - Serial header for communicating with hwcrypto server
+ * @in_addr:  start address of the input buf.
+ * @in_len:   size of the input buf.
+ * @out_addr: start addrss of the output buf.
+ * @out_len:  size of the output buf.
+ * @algo:     hash algorithm expect to use.
+ */
+typedef struct hwcrypto_hash_msg {
+    uint32_t in_addr;
+    uint32_t in_len;
+    uint32_t out_addr;
+    uint32_t out_len;
+    enum hwcrypto_hash_algo algo;
+} hwcrypto_hash_msg;
+
+/**
+ * @plain_pa:  physical start address of the plain blob buf.
+ * @plain_size:   size of the plain blob.
+ * @blob: physical start addrss of the output buf.
+ */
+typedef struct hwcrypto_blob_msg {
+    uint32_t plain_pa;
+    uint32_t plain_size;
+    uint32_t blob_pa;
+}hwcrypto_blob_msg;
+
+/**
+ * @buf:  physical start address of the output rng buf.
+ * @len:  size of required rng.
+ */
+typedef struct hwcrypto_rng_msg {
+    uint32_t buf;
+    uint32_t len;
+}hwcrypto_rng_msg;
+
+/**
+ * @buf:  physical start address of the output bkek buf.
+ * @len:  size of required rng.
+ */
+typedef struct hwcrypto_bkek_msg {
+    uint32_t buf;
+    uint32_t len;
+}hwcrypto_bkek_msg;
+#endif /* TRUSTY_INTERFACE_HWCRYPTO_H_ */
diff --git a/include/interface/keymaster/keymaster.h b/include/interface/keymaster/keymaster.h
new file mode 100644
index 00000000000..2a406d74f92
--- /dev/null
+++ b/include/interface/keymaster/keymaster.h
@@ -0,0 +1,306 @@
+/*
+ * Copyright (C) 2017 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef TRUSTY_INTERFACE_KEYMASTER_H_
+#define TRUSTY_INTERFACE_KEYMASTER_H_
+
+#include <trusty/sysdeps.h>
+
+#define KEYMASTER_PORT "com.android.trusty.keymaster"
+#define KEYMASTER_MAX_BUFFER_LENGTH 4096
+
+enum keymaster_command {
+    KEYMASTER_RESP_BIT              = 1,
+    KEYMASTER_STOP_BIT              = 2,
+    KEYMASTER_REQ_SHIFT             = 2,
+
+    KM_GENERATE_KEY                 = (0 << KEYMASTER_REQ_SHIFT),
+    KM_BEGIN_OPERATION              = (1 << KEYMASTER_REQ_SHIFT),
+    KM_UPDATE_OPERATION             = (2 << KEYMASTER_REQ_SHIFT),
+    KM_FINISH_OPERATION             = (3 << KEYMASTER_REQ_SHIFT),
+    KM_ABORT_OPERATION              = (4 << KEYMASTER_REQ_SHIFT),
+    KM_IMPORT_KEY                   = (5 << KEYMASTER_REQ_SHIFT),
+
+    KM_EXPORT_KEY                   = (6 << KEYMASTER_REQ_SHIFT),
+    KM_GET_VERSION                  = (7 << KEYMASTER_REQ_SHIFT),
+    KM_ADD_RNG_ENTROPY              = (8 << KEYMASTER_REQ_SHIFT),
+    KM_GET_SUPPORTED_ALGORITHMS     = (9 << KEYMASTER_REQ_SHIFT),
+    KM_GET_SUPPORTED_BLOCK_MODES    = (10 << KEYMASTER_REQ_SHIFT),
+    KM_GET_SUPPORTED_PADDING_MODES  = (11 << KEYMASTER_REQ_SHIFT),
+    KM_GET_SUPPORTED_DIGESTS        = (12 << KEYMASTER_REQ_SHIFT),
+    KM_GET_SUPPORTED_IMPORT_FORMATS = (13 << KEYMASTER_REQ_SHIFT),
+    KM_GET_SUPPORTED_EXPORT_FORMATS = (14 << KEYMASTER_REQ_SHIFT),
+    KM_GET_KEY_CHARACTERISTICS      = (15 << KEYMASTER_REQ_SHIFT),
+
+    // Bootloader calls.
+    KM_SET_BOOT_PARAMS                 = (0x1000 << KEYMASTER_REQ_SHIFT),
+    KM_SET_ATTESTATION_KEY             = (0x2000 << KEYMASTER_REQ_SHIFT),
+    KM_APPEND_ATTESTATION_CERT_CHAIN   = (0x3000 << KEYMASTER_REQ_SHIFT),
+    KM_ATAP_GET_CA_REQUEST             = (0x4000 << KEYMASTER_REQ_SHIFT),
+    KM_ATAP_SET_CA_RESPONSE_BEGIN      = (0x5000 << KEYMASTER_REQ_SHIFT),
+    KM_ATAP_SET_CA_RESPONSE_UPDATE     = (0x6000 << KEYMASTER_REQ_SHIFT),
+    KM_ATAP_SET_CA_RESPONSE_FINISH     = (0x7000 << KEYMASTER_REQ_SHIFT),
+    KM_ATAP_READ_UUID                  = (0x8000 << KEYMASTER_REQ_SHIFT),
+    KM_SET_PRODUCT_ID                  = (0x9000 << KEYMASTER_REQ_SHIFT),
+    KM_CLEAR_ATTESTATION_CERT_CHAIN    = (0xa000 << KEYMASTER_REQ_SHIFT),
+    KM_SET_WRAPPED_ATTESTATION_KEY     = (0xb000 << KEYMASTER_REQ_SHIFT),
+    KM_SET_ATTESTATION_IDS             = (0xc000 << KEYMASTER_REQ_SHIFT),
+    KM_CONFIGURE_BOOT_PATCHLEVEL       = (0xd0000 << KEYMASTER_REQ_SHIFT),
+
+    KM_GET_MPPUBK                      = (0xf001 << KEYMASTER_REQ_SHIFT),
+    KM_APPEND_ATTESTATION_CERT_CHAIN_ENC = (0xf002 << KEYMASTER_REQ_SHIFT),
+    KM_SET_ATTESTATION_KEY_ENC         = (0xf003 << KEYMASTER_REQ_SHIFT),
+    KM_VERIFY_SECURE_UNLOCK            = (0xf004 << KEYMASTER_REQ_SHIFT)
+};
+
+typedef enum {
+    KM_VERIFIED_BOOT_VERIFIED = 0,    /* Full chain of trust extending from the bootloader to
+                                       * verified partitions, including the bootloader, boot
+                                       * partition, and all verified partitions*/
+    KM_VERIFIED_BOOT_SELF_SIGNED = 1, /* The boot partition has been verified using the embedded
+                                       * certificate, and the signature is valid. The bootloader
+                                       * displays a warning and the fingerprint of the public
+                                       * key before allowing the boot process to continue.*/
+    KM_VERIFIED_BOOT_UNVERIFIED = 2,  /* The device may be freely modified. Device integrity is left
+                                       * to the user to verify out-of-band. The bootloader
+                                       * displays a warning to the user before allowing the boot
+                                       * process to continue */
+    KM_VERIFIED_BOOT_FAILED = 3,      /* The device failed verification. The bootloader displays a
+                                       * warning and stops the boot process, so no keymaster
+                                       * implementation should ever actually return this value,
+                                       * since it should not run.  Included here only for
+                                       * completeness. */
+} keymaster_verified_boot_t;
+
+/**
+ * Algorithms that may be provided by keymaster implementations.
+ */
+typedef enum {
+    /* Asymmetric algorithms. */
+    KM_ALGORITHM_RSA = 1,
+    // KM_ALGORITHM_DSA = 2, -- Removed, do not re-use value 2.
+    KM_ALGORITHM_EC = 3,
+
+    /* Block ciphers algorithms */
+    KM_ALGORITHM_AES = 32,
+
+    /* MAC algorithms */
+    KM_ALGORITHM_HMAC = 128,
+} keymaster_algorithm_t;
+
+typedef enum {
+    KM_ERROR_OK = 0,
+    KM_ERROR_ROOT_OF_TRUST_ALREADY_SET = -1,
+    KM_ERROR_UNSUPPORTED_PURPOSE = -2,
+    KM_ERROR_INCOMPATIBLE_PURPOSE = -3,
+    KM_ERROR_UNSUPPORTED_ALGORITHM = -4,
+    KM_ERROR_INCOMPATIBLE_ALGORITHM = -5,
+    KM_ERROR_UNSUPPORTED_KEY_SIZE = -6,
+    KM_ERROR_UNSUPPORTED_BLOCK_MODE = -7,
+    KM_ERROR_INCOMPATIBLE_BLOCK_MODE = -8,
+    KM_ERROR_UNSUPPORTED_MAC_LENGTH = -9,
+    KM_ERROR_UNSUPPORTED_PADDING_MODE = -10,
+    KM_ERROR_INCOMPATIBLE_PADDING_MODE = -11,
+    KM_ERROR_UNSUPPORTED_DIGEST = -12,
+    KM_ERROR_INCOMPATIBLE_DIGEST = -13,
+    KM_ERROR_INVALID_EXPIRATION_TIME = -14,
+    KM_ERROR_INVALID_USER_ID = -15,
+    KM_ERROR_INVALID_AUTHORIZATION_TIMEOUT = -16,
+    KM_ERROR_UNSUPPORTED_KEY_FORMAT = -17,
+    KM_ERROR_INCOMPATIBLE_KEY_FORMAT = -18,
+    KM_ERROR_UNSUPPORTED_KEY_ENCRYPTION_ALGORITHM = -19,   /* For PKCS8 & PKCS12 */
+    KM_ERROR_UNSUPPORTED_KEY_VERIFICATION_ALGORITHM = -20, /* For PKCS8 & PKCS12 */
+    KM_ERROR_INVALID_INPUT_LENGTH = -21,
+    KM_ERROR_KEY_EXPORT_OPTIONS_INVALID = -22,
+    KM_ERROR_DELEGATION_NOT_ALLOWED = -23,
+    KM_ERROR_KEY_NOT_YET_VALID = -24,
+    KM_ERROR_KEY_EXPIRED = -25,
+    KM_ERROR_KEY_USER_NOT_AUTHENTICATED = -26,
+    KM_ERROR_OUTPUT_PARAMETER_NULL = -27,
+    KM_ERROR_INVALID_OPERATION_HANDLE = -28,
+    KM_ERROR_INSUFFICIENT_BUFFER_SPACE = -29,
+    KM_ERROR_VERIFICATION_FAILED = -30,
+    KM_ERROR_TOO_MANY_OPERATIONS = -31,
+    KM_ERROR_UNEXPECTED_NULL_POINTER = -32,
+    KM_ERROR_INVALID_KEY_BLOB = -33,
+    KM_ERROR_IMPORTED_KEY_NOT_ENCRYPTED = -34,
+    KM_ERROR_IMPORTED_KEY_DECRYPTION_FAILED = -35,
+    KM_ERROR_IMPORTED_KEY_NOT_SIGNED = -36,
+    KM_ERROR_IMPORTED_KEY_VERIFICATION_FAILED = -37,
+    KM_ERROR_INVALID_ARGUMENT = -38,
+    KM_ERROR_UNSUPPORTED_TAG = -39,
+    KM_ERROR_INVALID_TAG = -40,
+    KM_ERROR_MEMORY_ALLOCATION_FAILED = -41,
+    KM_ERROR_IMPORT_PARAMETER_MISMATCH = -44,
+    KM_ERROR_SECURE_HW_ACCESS_DENIED = -45,
+    KM_ERROR_OPERATION_CANCELLED = -46,
+    KM_ERROR_CONCURRENT_ACCESS_CONFLICT = -47,
+    KM_ERROR_SECURE_HW_BUSY = -48,
+    KM_ERROR_SECURE_HW_COMMUNICATION_FAILED = -49,
+    KM_ERROR_UNSUPPORTED_EC_FIELD = -50,
+    KM_ERROR_MISSING_NONCE = -51,
+    KM_ERROR_INVALID_NONCE = -52,
+    KM_ERROR_MISSING_MAC_LENGTH = -53,
+    KM_ERROR_KEY_RATE_LIMIT_EXCEEDED = -54,
+    KM_ERROR_CALLER_NONCE_PROHIBITED = -55,
+    KM_ERROR_KEY_MAX_OPS_EXCEEDED = -56,
+    KM_ERROR_INVALID_MAC_LENGTH = -57,
+    KM_ERROR_MISSING_MIN_MAC_LENGTH = -58,
+    KM_ERROR_UNSUPPORTED_MIN_MAC_LENGTH = -59,
+    KM_ERROR_UNSUPPORTED_KDF = -60,
+    KM_ERROR_UNSUPPORTED_EC_CURVE = -61,
+    KM_ERROR_KEY_REQUIRES_UPGRADE = -62,
+    KM_ERROR_ATTESTATION_CHALLENGE_MISSING = -63,
+    KM_ERROR_KEYMASTER_NOT_CONFIGURED = -64,
+
+    KM_ERROR_UNIMPLEMENTED = -100,
+    KM_ERROR_VERSION_MISMATCH = -101,
+
+    KM_ERROR_UNKNOWN_ERROR = -1000,
+} keymaster_error_t;
+
+/**
+ * keymaster_message - Serial header for communicating with KM server
+ *
+ * @cmd: the command, one of keymaster_command.
+ * @payload: start of the serialized command specific payload
+ */
+struct keymaster_message {
+    uint32_t cmd;
+    uint8_t payload[0];
+};
+
+/**
+ * km_no_response -  Generic keymaster response for commands with no special
+ * response data
+ *
+ * @error: error code from command
+ */
+struct km_no_response {
+    int32_t error;
+};
+
+/**
+ * km_get_version_resp - response format for KM_GET_VERSION.
+ */
+struct km_get_version_resp {
+    int32_t error;
+    uint8_t major_ver;
+    uint8_t minor_ver;
+    uint8_t subminor_ver;
+} TRUSTY_ATTR_PACKED;
+
+/**
+ * km_raw_buffer_resp - response format for a raw buffer
+ */
+struct km_raw_buffer_resp {
+    int32_t error;
+    uint32_t data_size;
+    int8_t data[0];
+} TRUSTY_ATTR_PACKED;
+
+/**
+ * km_get_mppubk_resp - response format for mppubk buffer
+ */
+struct km_get_mppubk_resp {
+    int32_t error;
+    uint32_t data_size;
+    uint8_t data[64];
+} TRUSTY_ATTR_PACKED;
+
+/**
+ * km_secure_unlock_data - represents the secure unlock data
+ *
+ * @serial_size: size of |serial_data|
+ * @serial_data: serial_data (serial number)
+ * @credential_size: size of |credential_data|
+ * @credential_data: credential data
+ */
+struct km_secure_unlock_data {
+    uint32_t serial_size;
+    const uint8_t *serial_data;
+    uint32_t credential_size;
+    const uint8_t *credential_data;
+} TRUSTY_ATTR_PACKED;
+/**
+ * km_set_ca_response_begin_req - starts the process to set the ATAP CA Response
+ *
+ * @ca_response_size: total size of the CA Response message
+ */
+struct km_set_ca_response_begin_req {
+    uint32_t ca_response_size;
+} TRUSTY_ATTR_PACKED;
+
+/**
+ * km_boot_params - Parameters sent from the bootloader to the Keymaster TA
+ *
+ * Since verified_boot_key_hash and verified_boot_hash have variable sizes, this
+ * structure must be serialized before sending to the secure side
+ * using km_boot_params_serialize().
+ *
+ * @os_version: OS version from Android image header
+ * @os_patchlevel: OS patch level from Android image header
+ * @device_locked: nonzero if device is locked
+ * @verified_boot_state: one of keymaster_verified_boot_t
+ * @verified_boot_key_hash_size: size of verified_boot_key_hash
+ * @verified_boot_key_hash: hash of key used to verify Android image
+ * @verified_boot_hash_size: size of verified_boot_hash
+ * @verified_boot_hash: cumulative hash of all images verified thus far
+ */
+struct km_boot_params {
+    uint32_t os_version;
+    uint32_t os_patchlevel;
+    uint32_t device_locked;
+    uint32_t verified_boot_state;
+    uint32_t verified_boot_key_hash_size;
+    const uint8_t *verified_boot_key_hash;
+    uint32_t verified_boot_hash_size;
+    const uint8_t *verified_boot_hash;
+} TRUSTY_ATTR_PACKED;
+
+/**
+ * km_attestation_data - represents a DER encoded key or certificate
+ *
+ * @algorithm: one of KM_ALGORITHM_RSA or KM_ALGORITHM_EC
+ * @data_size: size of |data|
+ * @data: DER encoded key or certificate (depending on operation)
+ */
+struct km_attestation_data {
+    uint32_t algorithm;
+    uint32_t data_size;
+    const uint8_t *data;
+} TRUSTY_ATTR_PACKED;
+
+/**
+ * km_raw_buffer - represents a single raw buffer
+ *
+ * @data_size: size of |data|
+ * @data: pointer to the buffer
+ */
+struct km_raw_buffer {
+    uint32_t data_size;
+    const uint8_t *data;
+} TRUSTY_ATTR_PACKED;
+
+#endif /* TRUSTY_INTERFACE_KEYMASTER_H_ */
diff --git a/include/interface/storage/storage.h b/include/interface/storage/storage.h
new file mode 100644
index 00000000000..4d524984e6c
--- /dev/null
+++ b/include/interface/storage/storage.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef TRUSTY_INTERFACE_STORAGE_H_
+#define TRUSTY_INTERFACE_STORAGE_H_
+
+/*
+ * The contents of this file are copied from
+ * trusty/lib/interface/storage/include/interface/storage/storage.h.
+ * It is required to stay in sync for struct formats and enum values.
+ */
+
+#include <trusty/sysdeps.h>
+
+/*
+ * @STORAGE_DISK_PROXY_PORT: Port used by non-secure proxy server
+ */
+#define STORAGE_DISK_PROXY_PORT    "com.android.trusty.storage.proxy"
+
+enum storage_cmd {
+    STORAGE_REQ_SHIFT = 1,
+    STORAGE_RESP_BIT  = 1,
+
+    STORAGE_RESP_MSG_ERR   = STORAGE_RESP_BIT,
+
+    STORAGE_FILE_DELETE    = 1 << STORAGE_REQ_SHIFT,
+    STORAGE_FILE_OPEN      = 2 << STORAGE_REQ_SHIFT,
+    STORAGE_FILE_CLOSE     = 3 << STORAGE_REQ_SHIFT,
+    STORAGE_FILE_READ      = 4 << STORAGE_REQ_SHIFT,
+    STORAGE_FILE_WRITE     = 5 << STORAGE_REQ_SHIFT,
+    STORAGE_FILE_GET_SIZE  = 6 << STORAGE_REQ_SHIFT,
+    STORAGE_FILE_SET_SIZE  = 7 << STORAGE_REQ_SHIFT,
+
+    STORAGE_RPMB_SEND      = 8 << STORAGE_REQ_SHIFT,
+
+    /* transaction support */
+    STORAGE_END_TRANSACTION = 9 << STORAGE_REQ_SHIFT,
+
+    STORAGE_RPMB_KEY_SET = 12 << STORAGE_REQ_SHIFT,
+    STORAGE_RPMB_ERASE_ALL = 13 << STORAGE_REQ_SHIFT,
+};
+
+/**
+ * enum storage_err - error codes for storage protocol
+ * @STORAGE_NO_ERROR:           all OK
+ * @STORAGE_ERR_GENERIC:        unknown error. Can occur when there's an internal server
+ *                              error, e.g. the server runs out of memory or is in a bad state.
+ * @STORAGE_ERR_NOT_VALID:      input not valid. May occur if the arguments passed
+ *                              into the command are not valid, for example if the file handle
+ *                              passed in is not a valid one.
+ * @STORAGE_ERR_UNIMPLEMENTED:  the command passed in is not recognized
+ * @STORAGE_ERR_ACCESS:         the file is not accessible in the requested mode
+ * @STORAGE_ERR_NOT_FOUND:      the file was not found
+ * @STORAGE_ERR_EXIST           the file exists when it shouldn't as in with OPEN_CREATE | OPEN_EXCLUSIVE.
+ * @STORAGE_ERR_TRANSACT        returned by various operations to indicate that current transaction
+ *                              is in error state. Such state could be only cleared by sending
+ *                              STORAGE_END_TRANSACTION message.
+ */
+enum storage_err {
+    STORAGE_NO_ERROR          = 0,
+    STORAGE_ERR_GENERIC       = 1,
+    STORAGE_ERR_NOT_VALID     = 2,
+    STORAGE_ERR_UNIMPLEMENTED = 3,
+    STORAGE_ERR_ACCESS        = 4,
+    STORAGE_ERR_NOT_FOUND     = 5,
+    STORAGE_ERR_EXIST         = 6,
+    STORAGE_ERR_TRANSACT      = 7,
+};
+
+/**
+ * enum storage_msg_flag - protocol-level flags in struct storage_msg
+ * @STORAGE_MSG_FLAG_BATCH:             if set, command belongs to a batch transaction.
+ *                                      No response will be sent by the server until
+ *                                      it receives a command with this flag unset, at
+ *                                      which point a cummulative result for all messages
+ *                                      sent with STORAGE_MSG_FLAG_BATCH will be sent.
+ *                                      This is only supported by the non-secure disk proxy
+ *                                      server.
+ * @STORAGE_MSG_FLAG_PRE_COMMIT:        if set, indicates that server need to commit
+ *                                      pending changes before processing this message.
+ * @STORAGE_MSG_FLAG_POST_COMMIT:       if set, indicates that server need to commit
+ *                                      pending changes after processing this message.
+ * @STORAGE_MSG_FLAG_TRANSACT_COMPLETE: if set, indicates that server need to commit
+ *                                      current transaction after processing this message.
+ *                                      It is an alias for STORAGE_MSG_FLAG_POST_COMMIT.
+ */
+enum storage_msg_flag {
+    STORAGE_MSG_FLAG_BATCH = 0x1,
+    STORAGE_MSG_FLAG_PRE_COMMIT = 0x2,
+    STORAGE_MSG_FLAG_POST_COMMIT = 0x4,
+    STORAGE_MSG_FLAG_TRANSACT_COMPLETE = STORAGE_MSG_FLAG_POST_COMMIT,
+};
+
+/*
+ * The following declarations are the message-specific contents of
+ * the 'payload' element inside struct storage_msg.
+ */
+
+/**
+ * struct storage_rpmb_send_req - request format for STORAGE_RPMB_SEND
+ * @reliable_write_size:        size in bytes of reliable write region
+ * @write_size:                 size in bytes of write region
+ * @read_size:                  number of bytes to read for a read request
+ * @__reserved:                 unused, must be set to 0
+ * @payload:                    start of reliable write region, followed by
+ *                              write region.
+ *
+ * Only used in proxy<->server interface.
+ */
+struct storage_rpmb_send_req {
+    uint32_t reliable_write_size;
+    uint32_t write_size;
+    uint32_t read_size;
+    uint32_t __reserved;
+    uint8_t  payload[0];
+};
+
+/**
+ * struct storage_rpmb_send_resp: response type for STORAGE_RPMB_SEND
+ * @data: the data frames frames retrieved from the MMC.
+ */
+struct storage_rpmb_send_resp {
+    uint8_t data[0];
+};
+
+/**
+ * struct storage_msg - generic req/resp format for all storage commands
+ * @cmd:        one of enum storage_cmd
+ * @op_id:      client chosen operation identifier for an instance
+ *              of a command or atomic grouping of commands (transaction).
+ * @flags:      one or many of enum storage_msg_flag or'ed together.
+ * @size:       total size of the message including this header
+ * @result:     one of enum storage_err
+ * @__reserved: unused, must be set to 0.
+ * @payload:    beginning of command specific message format
+ */
+struct storage_msg {
+    uint32_t cmd;
+    uint32_t op_id;
+    uint32_t flags;
+    uint32_t size;
+    int32_t  result;
+    uint32_t __reserved;
+    uint8_t  payload[0];
+};
+
+#endif /* TRUSTY_INTERFACE_STORAGE_H_ */
diff --git a/include/lcd.h b/include/lcd.h
index 51a79317bba..683df2c28de 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -30,6 +30,7 @@ extern struct vidinfo panel_info;
 void lcd_ctrl_init(void *lcdbase);
 void lcd_enable(void);
 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue);
+void lcd_initcolregs (void);
 ulong lcd_setmem(ulong addr);
 
 /**
@@ -47,6 +48,64 @@ void lcd_set_flush_dcache(int flush);
 #include <atmel_lcd.h>
 #elif defined(CONFIG_EXYNOS_FB)
 #include <exynos_lcd.h>
+#elif defined(CONFIG_MXC_EPDC)
+
+struct waveform_modes {
+	int mode_init;
+	int mode_du;
+	int mode_gc4;
+	int mode_gc8;
+	int mode_gc16;
+	int mode_gc32;
+};
+
+struct epdc_timing_params {
+    int vscan_holdoff;
+    int sdoed_width;
+    int sdoed_delay;
+    int sdoez_width;
+    int sdoez_delay;
+    int gdclk_hp_offs;
+    int gdsp_offs;
+    int gdoe_offs;
+    int gdclk_offs;
+    int num_ce;
+};
+
+struct epdc_data_struct {
+	/* EPDC buffer pointers */
+	u_long working_buf_addr;
+	u_long waveform_buf_addr;
+
+	/* Waveform mode definitions */
+	struct waveform_modes wv_modes;
+	struct epdc_timing_params epdc_timings;
+};
+
+typedef struct vidinfo {
+	u_long vl_refresh;      /* Refresh Rate Hz */
+	u_long vl_row;          /* resolution in x */
+	u_long vl_col;          /* resolution in y */
+	u_long vl_rot;
+	u_long vl_pixclock;     /* pixel clock in picoseconds */
+	u_long vl_left_margin;  /* Horizontal back porch */
+	u_long vl_right_margin; /* Horizontal front porch */
+	u_long vl_upper_margin; /* Vertical back porch */
+	u_long vl_lower_margin; /* Vertical front porch */
+	u_long vl_hsync;        /* Horizontal sync pulse length */
+	u_long vl_vsync;        /* Vertical sync pulse length */
+	u_long vl_sync;         /* Polarity on data enable */
+	u_long vl_mode;         /* Video Mode */
+	u_long vl_flag;
+	u_char  vl_bpix;
+	ushort  *cmap;
+	struct epdc_data_struct epdc_data;
+} vidinfo_t;
+
+static __maybe_unused ushort *configuration_get_cmap(void)
+{
+	return panel_info.cmap;
+}
 #else
 typedef struct vidinfo {
 	ushort	vl_col;		/* Number of columns (i.e. 160) */
@@ -163,6 +222,16 @@ void lcd_sync(void);
 #define LCD_BPP			LCD_COLOR8
 #endif
 
+#if LCD_BPP == LCD_MONOCHROME
+# define COLOR_MASK(c)		((c)	  | (c) << 1 | (c) << 2 | (c) << 3 | \
+				 (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7)
+#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) || \
+	(LCD_BPP == LCD_COLOR32)
+# define COLOR_MASK(c)		(c)
+#else
+#error Unsupported LCD BPP.
+#endif
+
 #ifndef LCD_DF
 #define LCD_DF			1
 #endif
@@ -171,7 +240,14 @@ void lcd_sync(void);
 #define NBITS(bit_code)		(1 << (bit_code))
 #define NCOLORS(bit_code)	(1 << NBITS(bit_code))
 
-#if LCD_BPP == LCD_COLOR8
+#if LCD_BPP == LCD_MONOCHROME
+/*
+ * Simple black/white definitions
+ */
+# define CONSOLE_COLOR_BLACK	0
+# define CONSOLE_COLOR_WHITE	1	/* Must remain last / highest	*/
+
+#elif LCD_BPP == LCD_COLOR8
 # define CONSOLE_COLOR_BLACK	0
 # define CONSOLE_COLOR_RED	1
 # define CONSOLE_COLOR_GREEN	2
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 3417ca2a0d2..4a824819470 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -55,7 +55,7 @@ void nand_wait_ready(struct mtd_info *mtd);
  * is supported now. If you add a chip with bigger oobsize/page
  * adjust this accordingly.
  */
-#define NAND_MAX_OOBSIZE       1664
+#define NAND_MAX_OOBSIZE       1872
 #define NAND_MAX_PAGESIZE      16384
 
 /*
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 4ceeae623de..2a37ab46ae3 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -29,6 +29,7 @@
 #define SNOR_MFR_SST		CFI_MFR_SST
 #define SNOR_MFR_WINBOND	0xef /* Also used by some Spansion */
 #define SNOR_MFR_CYPRESS	0x34
+#define SNOR_MFR_ADESTO		0x43
 
 /*
  * Note on opcode nomenclature: some opcodes have a format like
diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h
index 9ceee0a1c9f..c63a5f34c0c 100644
--- a/include/linux/usb/dwc3.h
+++ b/include/linux/usb/dwc3.h
@@ -154,6 +154,7 @@ struct dwc3 {					/* offset: 0xC100 */
 
 /* Global Configuration Register */
 #define DWC3_GCTL_PWRDNSCALE(n)			((n) << 19)
+#define DWC3_GCTL_PWRDNSCALE_MASK		DWC3_GCTL_PWRDNSCALE(0x1fff)
 #define DWC3_GCTL_U2RSTECN			(1 << 16)
 #define DWC3_GCTL_RAMCLKSEL(x)			\
 		(((x) & DWC3_GCTL_CLK_MASK) << 6)
diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
index b3f4b8d134c..70a06c5064c 100644
--- a/include/linux/usb/gadget.h
+++ b/include/linux/usb/gadget.h
@@ -973,7 +973,6 @@ extern int usb_gadget_handle_interrupts(int index);
 #if CONFIG_IS_ENABLED(DM_USB_GADGET)
 int usb_gadget_initialize(int index);
 int usb_gadget_release(int index);
-int dm_usb_gadget_handle_interrupts(struct udevice *dev);
 #else
 #include <usb.h>
 static inline int usb_gadget_initialize(int index)
diff --git a/include/lmb.h b/include/lmb.h
index ab277ca8000..47a3843e4ca 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -91,6 +91,8 @@ long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size);
  */
 long lmb_reserve_flags(struct lmb *lmb, phys_addr_t base,
 		       phys_size_t size, enum lmb_flags flags);
+long lmb_reserve_overlap(struct lmb *lmb, phys_addr_t base,
+		       phys_size_t size, enum lmb_flags flags);
 phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align);
 phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align,
 			   phys_addr_t max_addr);
diff --git a/include/mailbox.h b/include/mailbox.h
index 323b6c2bc5d..5997737bfc7 100644
--- a/include/mailbox.h
+++ b/include/mailbox.h
@@ -122,7 +122,7 @@ int mbox_free(struct mbox_chan *chan);
  *		will ignore this parameter.
  * Return: 0 if OK, or a negative error code.
  */
-int mbox_send(struct mbox_chan *chan, const void *data);
+int mbox_send(struct mbox_chan *chan, const void *data, ulong timeout_us);
 
 /**
  * mbox_recv - Receive any available message from a mailbox channel
diff --git a/include/mmc.h b/include/mmc.h
index 6bdcce881dd..51ccb677de1 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -341,6 +341,8 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx)
 #define MMC_QUIRK_RETRY_SET_BLOCKLEN	BIT(1)
 #define MMC_QUIRK_RETRY_APP_CMD	BIT(2)
 
+#define BOOT1_PWR_WP   (0x83)
+
 enum mmc_voltage {
 	MMC_SIGNAL_VOLTAGE_000 = 0,
 	MMC_SIGNAL_VOLTAGE_120 = 1,
@@ -862,6 +864,24 @@ int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
 /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
 /* Functions to read / write the RPMB partition */
+/* Sizes of RPMB data frame */
+#define RPMB_SZ_STUFF		196
+#define RPMB_SZ_MAC		32
+#define RPMB_SZ_DATA		256
+#define RPMB_SZ_NONCE		16
+
+/* Structure of RPMB data frame. */
+struct s_rpmb {
+	unsigned char stuff[RPMB_SZ_STUFF];
+	unsigned char mac[RPMB_SZ_MAC];
+	unsigned char data[RPMB_SZ_DATA];
+	unsigned char nonce[RPMB_SZ_NONCE];
+	unsigned int write_counter;
+	unsigned short address;
+	unsigned short block_count;
+	unsigned short result;
+	unsigned short request;
+};
 int mmc_rpmb_set_key(struct mmc *mmc, void *key);
 int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
 int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
@@ -887,6 +907,11 @@ int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
 int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen,
 			  void *rsp, unsigned long rsplen);
 
+int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s,
+			    unsigned int count, bool is_rel_write);
+int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s,
+			     unsigned int count, unsigned short expected);
+
 #ifdef CONFIG_CMD_BKOPS_ENABLE
 int mmc_set_bkops_enable(struct mmc *mmc);
 #endif
@@ -943,6 +968,7 @@ int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
 extern uint mmc_get_env_part(struct mmc *mmc);
 # endif
 int mmc_get_env_dev(void);
+int mmc_map_to_kernel_blk(int dev_no);
 
 /* Minimum partition switch timeout in units of 10-milliseconds */
 #define MMC_MIN_PART_SWITCH_TIME	30 /* 300 ms */
diff --git a/include/mxc_epdc_fb.h b/include/mxc_epdc_fb.h
new file mode 100644
index 00000000000..9aef8a17295
--- /dev/null
+++ b/include/mxc_epdc_fb.h
@@ -0,0 +1,552 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ */
+#ifndef __EPDC_REGS_INCLUDED__
+#define __EPDC_REGS_INCLUDED__
+
+#include <linux/types.h>
+#include <linux/list.h>
+#include <asm/arch/imx-regs.h>
+
+/*************************************
+ * Register addresses
+ *************************************/
+#define EPDC_BASE			(EPDC_BASE_ADDR)
+
+#define EPDC_CTRL			0x000
+#define EPDC_CTRL_SET			0x004
+#define EPDC_CTRL_CLR			0x008
+#define EPDC_CTRL_TOG		0x00C
+#define EPDC_WVADDR			0x020
+#define EPDC_WB_ADDR			0x030
+#define EPDC_RES			0x040
+#define EPDC_FORMAT			0x050
+#define EPDC_FORMAT_SET			0x054
+#define EPDC_FORMAT_CLR		0x058
+#define EPDC_FORMAT_TOG		0x05C
+#define EPDC_WB_FIELD0			0x060
+#define EPDC_WB_FIELD0_SET		0x064
+#define EPDC_WB_FIELD0_CLR		0x068
+#define EPDC_WB_FIELD0_TOG		0x06C
+#define EPDC_WB_FIELD1			0x070
+#define EPDC_WB_FIELD1_SET		0x074
+#define EPDC_WB_FIELD1_CLR		0x078
+#define EPDC_WB_FIELD1_TOG		0x07C
+#define EPDC_WB_FIELD2			0x080
+#define EPDC_WB_FIELD2_SET		0x084
+#define EPDC_WB_FIELD2_CLR		0x088
+#define EPDC_WB_FIELD2_TOG		0x08C
+#define EPDC_WB_FIELD3			0x090
+#define EPDC_WB_FIELD3_SET		0x094
+#define EPDC_WB_FIELD3_CLR		0x098
+#define EPDC_WB_FIELD3_TOG		0x09C
+#define EPDC_FIFOCTRL			0x0A0
+#define EPDC_FIFOCTRL_SET		0x0A4
+#define EPDC_FIFOCTRL_CLR		0x0A8
+#define EPDC_FIFOCTRL_TOG		0x0AC
+#define EPDC_UPD_ADDR			0x100
+#define EPDC_UPD_STRIDE			0x110
+#define EPDC_UPD_CORD			0x120
+#define EPDC_UPD_SIZE			0x140
+#define EPDC_UPD_CTRL			0x160
+#define EPDC_UPD_FIXED			0x180
+#define EPDC_TEMP			0x1A0
+#define EPDC_AUTOWV_LUT			0x1C0
+#define EPDC_LUT_STANDBY1		0x1E0
+#define EPDC_LUT_STANDBY1_SET		0x1E4
+#define EPDC_LUT_STANDBY1_CLR		0x1E8
+#define EPDC_LUT_STANDBY1_TOG	0x1EC
+#define EPDC_LUT_STANDBY2		0x1F0
+#define EPDC_LUT_STANDBY2_SET		0x1F4
+#define EPDC_LUT_STANDBY2_CLR		0x1F8
+#define EPDC_LUT_STANDBY2_TOG	0x1FC
+#define EPDC_TCE_CTRL			0x200
+#define EPDC_TCE_SDCFG			0x220
+#define EPDC_TCE_GDCFG			0x240
+#define EPDC_TCE_HSCAN1			0x260
+#define EPDC_TCE_HSCAN2			0x280
+#define EPDC_TCE_VSCAN			0x2A0
+#define EPDC_TCE_OE			0x2C0
+#define EPDC_TCE_POLARITY		0x2E0
+#define EPDC_TCE_TIMING1		0x300
+#define EPDC_TCE_TIMING2		0x310
+#define EPDC_TCE_TIMING3		0x320
+#define EPDC_PIGEON_CTRL0		0x380
+#define EPDC_PIGEON_CTRL1		0x390
+#define EPDC_IRQ_MASK1			0x3C0
+#define EPDC_IRQ_MASK1_SET		0x3C4
+#define EPDC_IRQ_MASK1_CLR		0x3C8
+#define EPDC_IRQ_MASK1_TOG		0x3CC
+#define EPDC_IRQ_MASK2			0x3D0
+#define EPDC_IRQ_MASK2_SET		0x3D4
+#define EPDC_IRQ_MASK2_CLR		0x3D8
+#define EPDC_IRQ_MASK2_TOG		0x3DC
+#define EPDC_IRQ1			0x3E0
+#define EPDC_IRQ1_SET			0x3E4
+#define EPDC_IRQ1_CLR			0x3E8
+#define EPDC_IRQ1_TOG		0x3EC
+#define EPDC_IRQ2			0x3F0
+#define EPDC_IRQ2_SET			0x3F4
+#define EPDC_IRQ2_CLR			0x3F8
+#define EPDC_IRQ2_TOG		0x3FC
+#define EPDC_IRQ_MASK			0x400
+#define EPDC_IRQ_MASK_SET		0x404
+#define EPDC_IRQ_MASK_CLR		0x408
+#define EPDC_IRQ_MASK_TOG		0x40C
+#define EPDC_IRQ			0x420
+#define EPDC_IRQ_SET			0x424
+#define EPDC_IRQ_CLR			0x428
+#define EPDC_IRQ_TOG			0x42C
+#define EPDC_STATUS_LUTS		0x440
+#define EPDC_STATUS_LUTS_SET		0x444
+#define EPDC_STATUS_LUTS_CLR		0x448
+#define EPDC_STATUS_LUTS_TOG		0x44C
+#define EPDC_STATUS_LUTS2		0x450
+#define EPDC_STATUS_LUTS2_SET		0x454
+#define EPDC_STATUS_LUTS2_CLR		0x458
+#define EPDC_STATUS_LUTS2_TOG	0x45C
+#define EPDC_STATUS_NEXTLUT		0x460
+#define EPDC_STATUS_COL			0x480
+#define EPDC_STATUS_COL2		0x490
+#define EPDC_STATUS			0x4A0
+#define EPDC_STATUS_SET			0x4A4
+#define EPDC_STATUS_CLR		0x4A8
+#define EPDC_STATUS_TOG		0x4AC
+#define EPDC_UPD_COL_CORD		0x4C0
+#define EPDC_UPD_COL_SIZE		0x4E0
+#define EPDC_DEBUG			0x500
+#define EPDC_DEBUG_LUT			0x530
+#define EPDC_HIST1_PARAM		0x600
+#define EPDC_HIST2_PARAM		0x610
+#define EPDC_HIST4_PARAM		0x620
+#define EPDC_HIST8_PARAM0		0x630
+#define EPDC_HIST8_PARAM1		0x640
+#define EPDC_HIST16_PARAM0		0x650
+#define EPDC_HIST16_PARAM1		0x660
+#define EPDC_HIST16_PARAM2		0x670
+#define EPDC_HIST16_PARAM3		0x680
+#define EPDC_GPIO			0x700
+#define EPDC_VERSION			0x7F0
+#define EPDC_PIGEON_0_0			0x800
+#define EPDC_PIGEON_0_1			0x810
+#define EPDC_PIGEON_0_2			0x820
+#define EPDC_PIGEON_1_0			0x840
+#define EPDC_PIGEON_1_1			0x850
+#define EPDC_PIGEON_1_2			0x860
+#define EPDC_PIGEON_2_0			0x880
+#define EPDC_PIGEON_2_1			0x890
+#define EPDC_PIGEON_2_2			0x8A0
+#define EPDC_PIGEON_3_0			0x8C0
+#define EPDC_PIGEON_3_1			0x8D0
+#define EPDC_PIGEON_3_2			0x8E0
+#define EPDC_PIGEON_4_0			0x900
+#define EPDC_PIGEON_4_1			0x910
+#define EPDC_PIGEON_4_2			0x920
+#define EPDC_PIGEON_5_0			0x940
+#define EPDC_PIGEON_5_1			0x950
+#define EPDC_PIGEON_5_2			0x960
+#define EPDC_PIGEON_6_0			0x980
+#define EPDC_PIGEON_6_1			0x990
+#define EPDC_PIGEON_6_2			0x9A0
+#define EPDC_PIGEON_7_0			0x9C0
+#define EPDC_PIGEON_7_1			0x9D0
+#define EPDC_PIGEON_7_2			0x9E0
+#define EPDC_PIGEON_8_0			0xA00
+#define EPDC_PIGEON_8_1			0xA10
+#define EPDC_PIGEON_8_2			0xA20
+#define EPDC_PIGEON_9_0			0xA40
+#define EPDC_PIGEON_9_1			0xA50
+#define EPDC_PIGEON_9_2			0xA60
+#define EPDC_PIGEON_10_0		0xA80
+#define EPDC_PIGEON_10_1		0xA90
+#define EPDC_PIGEON_10_2		0xAA0
+#define EPDC_PIGEON_11_0		0xAC0
+#define EPDC_PIGEON_11_1		0xAD0
+#define EPDC_PIGEON_11_2		0xAE0
+#define EPDC_PIGEON_12_0		0xB00
+#define EPDC_PIGEON_12_1		0xB10
+#define EPDC_PIGEON_12_2		0xB20
+#define EPDC_PIGEON_13_0		0xB40
+#define EPDC_PIGEON_13_1		0xB50
+#define EPDC_PIGEON_13_2		0xB60
+#define EPDC_PIGEON_14_0		0xB80
+#define EPDC_PIGEON_14_1		0xB90
+#define EPDC_PIGEON_14_2		0xBA0
+#define EPDC_PIGEON_15_0		0xBC0
+#define EPDC_PIGEON_15_1		0xBD0
+#define EPDC_PIGEON_15_2		0xBE0
+#define EPDC_PIGEON_16_0		0xC00
+#define EPDC_PIGEON_16_1		0xC10
+#define EPDC_PIGEON_16_2		0xC20
+#if defined(CONFIG_MX7) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)
+#define EPDC_WB_ADDR_TCE		0x010
+#else
+#define EPDC_WB_ADDR_TCE		0xC10
+#endif
+
+#define REG_RD(base, reg) \
+	(*(volatile unsigned int *)((base) + (reg)))
+#define REG_WR(base, reg, value) \
+	((*(volatile unsigned int *)((base) + (reg))) = (value))
+#define REG_SET(base, reg, value) \
+	((*(volatile unsigned int *)((base) + (reg ## _SET))) = (value))
+#define REG_CLR(base, reg, value) \
+	((*(volatile unsigned int *)((base) + (reg ## _CLR))) = (value))
+#define REG_TOG(base, reg, value) \
+	((*(volatile unsigned int *)((base) + (reg ## _TOG))) = (value))
+/*
+ * Register field definitions
+ */
+
+enum {
+/* EPDC_CTRL field values */
+	EPDC_CTRL_SFTRST = 0x80000000,
+	EPDC_CTRL_CLKGATE = 0x40000000,
+	EPDC_CTRL_SRAM_POWERDOWN = 0x100,
+	EPDC_CTRL_UPD_DATA_SWIZZLE_MASK = 0xC0,
+	EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP = 0,
+	EPDC_CTRL_UPD_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x40,
+	EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_SWAP = 0x80,
+	EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_BYTE_SWAP = 0xC0,
+	EPDC_CTRL_LUT_DATA_SWIZZLE_MASK = 0x30,
+	EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP = 0,
+	EPDC_CTRL_LUT_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x10,
+	EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_SWAP = 0x20,
+	EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_BYTE_SWAP = 0x30,
+	EPDC_CTRL_BURST_LEN_8_8 = 0x1,
+	EPDC_CTRL_BURST_LEN_8_16 = 0,
+
+/* EPDC_RES field values */
+	EPDC_RES_VERTICAL_MASK = 0x1FFF0000,
+	EPDC_RES_VERTICAL_OFFSET = 16,
+	EPDC_RES_HORIZONTAL_MASK = 0x1FFF,
+	EPDC_RES_HORIZONTAL_OFFSET = 0,
+
+/* EPDC_FORMAT field values */
+	EPDC_FORMAT_BUF_PIXEL_SCALE_ROUND = 0x1000000,
+	EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK = 0xFF0000,
+	EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET = 16,
+	EPDC_FORMAT_WB_ADDR_NO_COPY = 0x4000,
+	EPDC_FORMAT_WB_TYPE_MASK = 0x3000,
+	EPDC_FORMAT_WB_TYPE_OFFSET = 12,
+	EPDC_FORMAT_WB_TYPE_WB_INTERNAL = 0x0,
+	EPDC_FORMAT_WB_TYPE_WB_WAVEFORM = 0x1000,
+	EPDC_FORMAT_WB_TYPE_WB_EXTERNAL16 = 0x2000,
+	EPDC_FORMAT_WB_TYPE_WB_EXTERNAL32 = 0x3000,
+	EPDC_FORMAT_WB_COMPRESS = 0x800,
+	EPDC_FORMAT_BUF_PIXEL_FORMAT_MASK = 0x700,
+	EPDC_FORMAT_BUF_PIXEL_FORMAT_P2N = 0x200,
+	EPDC_FORMAT_BUF_PIXEL_FORMAT_P3N = 0x300,
+	EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N = 0x400,
+	EPDC_FORMAT_BUF_PIXEL_FORMAT_P5N = 0x500,
+	EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT = 0x0,
+	EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT_VCOM = 0x1,
+	EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT = 0x2,
+	EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT_VCOM = 0x3,
+
+/* EPDC_WB_FIELD field values */
+	EPDC_WB_FIELD_FIXED_MASK = 0xFF000000,
+	EPDC_WB_FIELD_FIXED_OFFSET = 24,
+	EPDC_WB_FIELD_USE_FIXED_MASK = 0x30000,
+	EPDC_WB_FIELD_USE_FIXED_OFFSET = 16,
+	EPDC_WB_FIELD_USE_FIXED_NO_FIXED = 0x0,
+	EPDC_WB_FIELD_USE_FIXED_USE_FIXED = 0x1,
+	EPDC_WB_FIELD_USE_FIXED_NE_FIXED = 0x2,
+	EPDC_WB_FIELD_USE_FIXED_EQ_FIXED = 0x3,
+	EPDC_WB_FIELD_USAGE_MASK = 0xE000,
+	EPDC_WB_FIELD_USAGE_OFFSET = 13,
+	EPDC_WB_FIELD_USAGE_NOT_USED = 0x0,
+	EPDC_WB_FIELD_USAGE_PARTIAL = 0x3,
+	EPDC_WB_FIELD_USAGE_LUT = 0x4,
+	EPDC_WB_FIELD_USAGE_CP = 0x5,
+	EPDC_WB_FIELD_USAGE_NP = 0x6,
+	EPDC_WB_FIELD_USAGE_PTS = 0x7,
+	EPDC_WB_FIELD_FROM_MASK = 0x1F00,
+	EPDC_WB_FIELD_FROM_OFFSET = 8,
+	EPDC_WB_FIELD_TO_MASK = 0xF0,
+	EPDC_WB_FIELD_TO_OFFSET = 4,
+	EPDC_WB_FIELD_LEN_MASK = 0xF,
+	EPDC_WB_FIELD_LEN_OFFSET = 0,
+
+/* EPDC_FIFOCTRL field values */
+	EPDC_FIFOCTRL_ENABLE_PRIORITY = 0x80000000,
+	EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK = 0xFF0000,
+	EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET = 16,
+	EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK = 0xFF00,
+	EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET = 8,
+	EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK = 0xFF,
+	EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET = 0,
+
+/* EPDC_UPD_CORD field values */
+	EPDC_UPD_CORD_YCORD_MASK = 0x1FFF0000,
+	EPDC_UPD_CORD_YCORD_OFFSET = 16,
+	EPDC_UPD_CORD_XCORD_MASK = 0x1FFF,
+	EPDC_UPD_CORD_XCORD_OFFSET = 0,
+
+/* EPDC_UPD_SIZE field values */
+	EPDC_UPD_SIZE_HEIGHT_MASK = 0x1FFF0000,
+	EPDC_UPD_SIZE_HEIGHT_OFFSET = 16,
+	EPDC_UPD_SIZE_WIDTH_MASK = 0x1FFF,
+	EPDC_UPD_SIZE_WIDTH_OFFSET = 0,
+
+/* EPDC_UPD_CTRL field values */
+	EPDC_UPD_CTRL_USE_FIXED = 0x80000000,
+#if defined(CONFIG_MX7) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)
+	EPDC_UPD_CTRL_LUT_SEL_MASK = 0x3F0000,
+#else
+	EPDC_UPD_CTRL_LUT_SEL_MASK = 0xF0000,
+#endif
+	EPDC_UPD_CTRL_LUT_SEL_OFFSET = 16,
+	EPDC_UPD_CTRL_WAVEFORM_MODE_MASK = 0xFF00,
+	EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET = 8,
+	EPDC_UPD_CTRL_NO_LUT_CANCEL = 0x10,
+	EPDC_UPD_CTRL_AUTOWV_PAUSE = 0x8,
+	EPDC_UPD_CTRL_AUTOWV = 0x4,
+	EPDC_UPD_CTRL_DRY_RUN = 0x2,
+	EPDC_UPD_CTRL_UPDATE_MODE_FULL = 0x1,
+
+/* EPDC_UPD_FIXED field values */
+	EPDC_UPD_FIXED_FIXNP_EN = 0x80000000,
+	EPDC_UPD_FIXED_FIXCP_EN = 0x40000000,
+	EPDC_UPD_FIXED_FIXNP_MASK = 0xFF00,
+	EPDC_UPD_FIXED_FIXNP_OFFSET = 8,
+	EPDC_UPD_FIXED_FIXCP_MASK = 0xFF,
+	EPDC_UPD_FIXED_FIXCP_OFFSET = 0,
+
+/* EPDC_AUTOWV_LUT field values */
+	EPDC_AUTOWV_LUT_DATA_MASK = 0xFF0000,
+	EPDC_AUTOWV_LUT_DATA_OFFSET = 16,
+#if defined(CONFIG_MX7) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)
+	EPDC_AUTOWV_LUT_ADDR_MASK = 0x7,
+#else
+	EPDC_AUTOWV_LUT_ADDR_MASK = 0xFF,
+#endif
+	EPDC_AUTOWV_LUT_ADDR_OFFSET = 0,
+
+/* EPDC_TCE_CTRL field values */
+	EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK = 0x1FF0000,
+	EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET = 16,
+	EPDC_TCE_CTRL_VCOM_VAL_MASK = 0xC00,
+	EPDC_TCE_CTRL_VCOM_VAL_OFFSET = 10,
+	EPDC_TCE_CTRL_VCOM_MODE_AUTO = 0x200,
+	EPDC_TCE_CTRL_VCOM_MODE_MANUAL = 0x000,
+	EPDC_TCE_CTRL_DDR_MODE_ENABLE = 0x100,
+	EPDC_TCE_CTRL_LVDS_MODE_CE_ENABLE = 0x80,
+	EPDC_TCE_CTRL_LVDS_MODE_ENABLE = 0x40,
+	EPDC_TCE_CTRL_SCAN_DIR_1_UP = 0x20,
+	EPDC_TCE_CTRL_SCAN_DIR_0_UP = 0x10,
+	EPDC_TCE_CTRL_DUAL_SCAN_ENABLE = 0x8,
+	EPDC_TCE_CTRL_SDDO_WIDTH_16BIT = 0x4,
+	EPDC_TCE_CTRL_PIXELS_PER_SDCLK_2 = 1,
+	EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4 = 2,
+	EPDC_TCE_CTRL_PIXELS_PER_SDCLK_8 = 3,
+
+/* EPDC_TCE_SDCFG field values */
+	EPDC_TCE_SDCFG_SDCLK_HOLD = 0x200000,
+	EPDC_TCE_SDCFG_SDSHR = 0x100000,
+	EPDC_TCE_SDCFG_NUM_CE_MASK = 0xF0000,
+	EPDC_TCE_SDCFG_NUM_CE_OFFSET = 16,
+	EPDC_TCE_SDCFG_SDDO_REFORMAT_STANDARD = 0,
+	EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS = 0x4000,
+	EPDC_TCE_SDCFG_SDDO_INVERT_ENABLE = 0x2000,
+	EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK = 0x1FFF,
+	EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET = 0,
+
+/* EPDC_TCE_GDCFG field values */
+	EPDC_TCE_SDCFG_GDRL = 0x10,
+	EPDC_TCE_SDCFG_GDOE_MODE_DELAYED_GDCLK = 0x2,
+	EPDC_TCE_SDCFG_GDSP_MODE_FRAME_SYNC = 0x1,
+	EPDC_TCE_SDCFG_GDSP_MODE_ONE_LINE = 0x0,
+
+/* EPDC_TCE_HSCAN1 field values */
+	EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK = 0xFFF0000,
+	EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET = 16,
+	EPDC_TCE_HSCAN1_LINE_SYNC_MASK = 0xFFF,
+	EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET = 0,
+
+/* EPDC_TCE_HSCAN2 field values */
+	EPDC_TCE_HSCAN2_LINE_END_MASK = 0xFFF0000,
+	EPDC_TCE_HSCAN2_LINE_END_OFFSET = 16,
+	EPDC_TCE_HSCAN2_LINE_BEGIN_MASK = 0xFFF,
+	EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET = 0,
+
+/* EPDC_TCE_VSCAN field values */
+	EPDC_TCE_VSCAN_FRAME_END_MASK = 0xFF0000,
+	EPDC_TCE_VSCAN_FRAME_END_OFFSET = 16,
+	EPDC_TCE_VSCAN_FRAME_BEGIN_MASK = 0xFF00,
+	EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET = 8,
+	EPDC_TCE_VSCAN_FRAME_SYNC_MASK = 0xFF,
+	EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET = 0,
+
+/* EPDC_TCE_OE field values */
+	EPDC_TCE_OE_SDOED_WIDTH_MASK = 0xFF000000,
+	EPDC_TCE_OE_SDOED_WIDTH_OFFSET = 24,
+	EPDC_TCE_OE_SDOED_DLY_MASK = 0xFF0000,
+	EPDC_TCE_OE_SDOED_DLY_OFFSET = 16,
+	EPDC_TCE_OE_SDOEZ_WIDTH_MASK = 0xFF00,
+	EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET = 8,
+	EPDC_TCE_OE_SDOEZ_DLY_MASK = 0xFF,
+	EPDC_TCE_OE_SDOEZ_DLY_OFFSET = 0,
+
+/* EPDC_TCE_POLARITY field values */
+	EPDC_TCE_POLARITY_GDSP_POL_ACTIVE_HIGH = 0x10,
+	EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH = 0x8,
+	EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH = 0x4,
+	EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH = 0x2,
+	EPDC_TCE_POLARITY_SDCE_POL_ACTIVE_HIGH = 0x1,
+
+/* EPDC_TCE_TIMING1 field values */
+	EPDC_TCE_TIMING1_SDLE_SHIFT_NONE = 0x00,
+	EPDC_TCE_TIMING1_SDLE_SHIFT_1 = 0x10,
+	EPDC_TCE_TIMING1_SDLE_SHIFT_2 = 0x20,
+	EPDC_TCE_TIMING1_SDLE_SHIFT_3 = 0x30,
+	EPDC_TCE_TIMING1_SDCLK_INVERT = 0x8,
+	EPDC_TCE_TIMING1_SDCLK_SHIFT_NONE = 0,
+	EPDC_TCE_TIMING1_SDCLK_SHIFT_1CYCLE = 1,
+	EPDC_TCE_TIMING1_SDCLK_SHIFT_2CYCLES = 2,
+	EPDC_TCE_TIMING1_SDCLK_SHIFT_3CYCLES = 3,
+
+/* EPDC_TCE_TIMING2 field values */
+	EPDC_TCE_TIMING2_GDCLK_HP_MASK = 0xFFFF0000,
+	EPDC_TCE_TIMING2_GDCLK_HP_OFFSET = 16,
+	EPDC_TCE_TIMING2_GDSP_OFFSET_MASK = 0xFFFF,
+	EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET = 0,
+
+/* EPDC_TCE_TIMING3 field values */
+	EPDC_TCE_TIMING3_GDOE_OFFSET_MASK = 0xFFFF0000,
+	EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET = 16,
+	EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK = 0xFFFF,
+	EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET = 0,
+
+/* EPDC EPDC_PIGEON_CTRL0 field values */
+	EPDC_PIGEON_CTRL0_LD_PERIOD_MASK = 0xFFF0000,
+	EPDC_PIGEON_CTRL0_LD_PERIOD_OFFSET = 16,
+	EPDC_PIGEON_CTRL0_FD_PERIOD_MASK = 0xFFF,
+	EPDC_PIGEON_CTRL0_FD_PERIOD_OFFSET = 0,
+
+/* EPDC EPDC_PIGEON_CTRL1 field values */
+	EPDC_PIGEON_CTRL1_LD_PERIOD_MASK = 0xFFF0000,
+	EPDC_PIGEON_CTRL1_LD_PERIOD_OFFSET = 16,
+	EPDC_PIGEON_CTRL1_FD_PERIOD_MASK = 0xFFF,
+	EPDC_PIGEON_CTRL1_FD_PERIOD_OFFSET = 0,
+
+/* EPDC_IRQ_MASK/EPDC_IRQ field values */
+	EPDC_IRQ_WB_CMPLT_IRQ = 0x10000,
+	EPDC_IRQ_LUT_COL_IRQ = 0x20000,
+	EPDC_IRQ_TCE_UNDERRUN_IRQ = 0x40000,
+	EPDC_IRQ_FRAME_END_IRQ = 0x80000,
+	EPDC_IRQ_BUS_ERROR_IRQ = 0x100000,
+	EPDC_IRQ_TCE_IDLE_IRQ = 0x200000,
+	EPDC_IRQ_UPD_DONE_IRQ = 0x400000,
+	EPDC_IRQ_PWR_IRQ = 0x800000,
+
+/* EPDC_STATUS_NEXTLUT field values */
+	EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID = 0x100,
+	EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK = 0x3F,
+	EPDC_STATUS_NEXTLUT_NEXT_LUT_OFFSET = 0,
+
+/* EPDC_STATUS field values */
+	EPDC_STATUS_HISTOGRAM_CP_MASK = 0x1F0000,
+	EPDC_STATUS_HISTOGRAM_CP_OFFSET = 16,
+	EPDC_STATUS_HISTOGRAM_NP_MASK = 0x1F00,
+	EPDC_STATUS_HISTOGRAM_NP_OFFSET = 8,
+	EPDC_STATUS_UPD_VOID = 0x8,
+	EPDC_STATUS_LUTS_UNDERRUN = 0x4,
+	EPDC_STATUS_LUTS_BUSY = 0x2,
+	EPDC_STATUS_WB_BUSY = 0x1,
+
+/* EPDC_UPD_COL_CORD field values */
+	EPDC_UPD_COL_CORD_YCORD_MASK = 0x1FFF0000,
+	EPDC_UPD_COL_CORD_YCORD_OFFSET = 16,
+	EPDC_UPD_COL_CORD_XCORD_MASK = 0x1FFF,
+	EPDC_UPD_COL_CORD_XCORD_OFFSET = 0,
+
+/* EPDC_UPD_COL_SIZE field values */
+	EPDC_UPD_COL_SIZE_HEIGHT_MASK = 0x1FFF0000,
+	EPDC_UPD_COL_SIZE_HEIGHT_OFFSET = 16,
+	EPDC_UPD_COL_SIZE_WIDTH_MASK = 0x1FFF,
+	EPDC_UPD_COL_SIZE_WIDTH_OFFSET = 0,
+
+/* EPDC_DEBUG field values */
+	EPDC_DEBUG_DEBUG_LUT_SEL_MASK = 0x3F00000,
+	EPDC_DEBUG_DEBUG_LUT_SEL_OFFSET = 24,
+	EPDC_DEBUG_UBW_BURST_LEN_MASK = 0xF000,
+	EPDC_DEBUG_UBW_BURST_LEN_OFFSET = 12,
+	EPDC_DEBUG_UBR_BURST_LEN_MASK = 0xF00,
+	EPDC_DEBUG_UBR_BURST_LEN = 8,
+	EPDC_DEBUG_UPD_BURST_LEN_MASK = 0xF0,
+	EPDC_DEBUG_UPD_BURST_LEN_OFFSET = 4,
+	EPDC_DEBUG_UPDATE_SAME = 0x4,
+	EPDC_DEBUG_UNDERRUN_RECOVER = 0x2,
+	EPDC_DEBUG_COLLISION_OFF = 0x1,
+
+/* EPDC_DEBUG_LUT field values */
+	EPDC_DEBUG_LUT_LUTADDR_MASK = 0x3FF0000,
+	EPDC_DEBUG_LUT_LUTADDR_OFFSET = 16,
+	EPDC_DEBUG_LUT_FRAME_MASK = 0x7FE0,
+	EPDC_DEBUG_LUT_FRAME_OFFSET = 5,
+	EPDC_DEBUG_LUT_STATEMACHINE_MASK = 0x1F,
+	EPDC_DEBUG_LUT_STATEMACHINE_OFFSET = 0,
+
+/* EPDC_HISTx_PARAM field values */
+	EPDC_HIST_PARAM_VALUE0_MASK = 0x1F,
+	EPDC_HIST_PARAM_VALUE0_OFFSET = 0,
+	EPDC_HIST_PARAM_VALUE1_MASK = 0x1F00,
+	EPDC_HIST_PARAM_VALUE1_OFFSET = 8,
+	EPDC_HIST_PARAM_VALUE2_MASK = 0x1F0000,
+	EPDC_HIST_PARAM_VALUE2_OFFSET = 16,
+	EPDC_HIST_PARAM_VALUE3_MASK = 0x1F000000,
+	EPDC_HIST_PARAM_VALUE3_OFFSET = 24,
+	EPDC_HIST_PARAM_VALUE4_MASK = 0x1F,
+	EPDC_HIST_PARAM_VALUE4_OFFSET = 0,
+	EPDC_HIST_PARAM_VALUE5_MASK = 0x1F00,
+	EPDC_HIST_PARAM_VALUE5_OFFSET = 8,
+	EPDC_HIST_PARAM_VALUE6_MASK = 0x1F0000,
+	EPDC_HIST_PARAM_VALUE6_OFFSET = 16,
+	EPDC_HIST_PARAM_VALUE7_MASK = 0x1F000000,
+	EPDC_HIST_PARAM_VALUE7_OFFSET = 24,
+	EPDC_HIST_PARAM_VALUE8_MASK = 0x1F,
+	EPDC_HIST_PARAM_VALUE8_OFFSET = 0,
+	EPDC_HIST_PARAM_VALUE9_MASK = 0x1F00,
+	EPDC_HIST_PARAM_VALUE9_OFFSET = 8,
+	EPDC_HIST_PARAM_VALUE10_MASK = 0x1F0000,
+	EPDC_HIST_PARAM_VALUE10_OFFSET = 16,
+	EPDC_HIST_PARAM_VALUE11_MASK = 0x1F000000,
+	EPDC_HIST_PARAM_VALUE11_OFFSET = 24,
+	EPDC_HIST_PARAM_VALUE12_MASK = 0x1F,
+	EPDC_HIST_PARAM_VALUE12_OFFSET = 0,
+	EPDC_HIST_PARAM_VALUE13_MASK = 0x1F00,
+	EPDC_HIST_PARAM_VALUE13_OFFSET = 8,
+	EPDC_HIST_PARAM_VALUE14_MASK = 0x1F0000,
+	EPDC_HIST_PARAM_VALUE14_OFFSET = 16,
+	EPDC_HIST_PARAM_VALUE15_MASK = 0x1F000000,
+	EPDC_HIST_PARAM_VALUE15_OFFSET = 24,
+
+/* EPDC_GPIO field values */
+	EPDC_GPIO_PWRSTAT = 0x100,
+	EPDC_GPIO_PWRWAKE = 0x80,
+	EPDC_GPIO_PWRCOM = 0x40,
+	EPDC_GPIO_PWRCTRL_MASK = 0x3C,
+	EPDC_GPIO_PWRCTRL_OFFSET = 2,
+	EPDC_GPIO_BDR_MASK = 0x3,
+	EPDC_GPIO_BDR_OFFSET = 0,
+
+/* EPDC_VERSION field values */
+	EPDC_VERSION_MAJOR_MASK = 0xFF000000,
+	EPDC_VERSION_MAJOR_OFFSET = 24,
+	EPDC_VERSION_MINOR_MASK = 0xFF0000,
+	EPDC_VERSION_MINOR_OFFSET = 16,
+	EPDC_VERSION_STEP_MASK = 0xFFFF,
+	EPDC_VERSION_STEP_OFFSET = 0,
+};
+
+int board_setup_waveform_file(ulong waveform_buf);
+int board_setup_logo_file(void *display_buf);
+void epdc_power_on(void);
+void epdc_power_off(void);
+
+extern void *lcd_base;
+
+#endif	/* __EPDC_REGS_INCLUDED__ */
diff --git a/include/mxc_keyb.h b/include/mxc_keyb.h
new file mode 100644
index 00000000000..c43297760c0
--- /dev/null
+++ b/include/mxc_keyb.h
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2009-2014 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ */
+
+/*!
+ * @defgroup keypad Keypad Driver
+ */
+
+/*!
+ * @file mxc_keyb.h
+ *
+ * @brief MXC keypad header file.
+ *
+ * @ingroup keypad
+ */
+#ifndef __MXC_KEYB_H__
+#define __MXC_KEYB_H__
+
+/*!
+ * Keypad Module Name
+ */
+#define MOD_NAME  "mxckpd"
+
+/*!
+ * Keypad irq number
+ */
+#define KPP_IRQ  MXC_INT_KPP
+
+/*!
+ * XLATE mode selection
+ */
+#define KEYPAD_XLATE        0
+
+/*!
+ * RAW mode selection
+ */
+#define KEYPAD_RAW          1
+
+/*!
+ * Maximum number of keys.
+ */
+#define MAXROW			8
+#define MAXCOL			8
+#define MXC_MAXKEY		(MAXROW * MAXCOL)
+
+/*!
+ * This define indicates break scancode for every key release. A constant
+ * of 128 is added to the key press scancode.
+ */
+#define  MXC_KEYRELEASE   128
+
+/*
+ * _reg_KPP_KPCR   _reg_KPP_KPSR _reg_KPP_KDDR _reg_KPP_KPDR
+ * Keypad Control Register Address
+ */
+#define KPCR    (KPP_BASE_ADDR + 0x00)
+
+/*
+ * Keypad Status Register Address
+ */
+#define KPSR    (KPP_BASE_ADDR + 0x02)
+
+/*
+ * Keypad Data Direction Address
+ */
+#define KDDR    (KPP_BASE_ADDR + 0x04)
+
+/*
+ * Keypad Data Register
+ */
+#define KPDR    (KPP_BASE_ADDR + 0x06)
+
+/*
+ * Key Press Interrupt Status bit
+ */
+#define KBD_STAT_KPKD        0x01
+
+/*
+ * Key Release Interrupt Status bit
+ */
+#define KBD_STAT_KPKR        0x02
+
+/*
+ * Key Depress Synchronizer Chain Status bit
+ */
+#define KBD_STAT_KDSC        0x04
+
+/*
+ * Key Release Synchronizer Status bit
+ */
+#define KBD_STAT_KRSS        0x08
+
+/*
+ * Key Depress Interrupt Enable Status bit
+ */
+#define KBD_STAT_KDIE        0x100
+
+/*
+ * Key Release Interrupt Enable
+ */
+#define KBD_STAT_KRIE        0x200
+
+/*
+ * Keypad Clock Enable
+ */
+#define KBD_STAT_KPPEN       0x400
+
+/*!
+ * Buffer size of keypad queue. Should be a power of 2.
+ */
+#define KPP_BUF_SIZE    128
+
+/*!
+ * Test whether bit is set for integer c
+ */
+#define TEST_BIT(c, n) ((c) & (0x1 << (n)))
+
+/*!
+ * Set nth bit in the integer c
+ */
+#define BITSET(c, n)   ((c) | (1 << (n)))
+
+/*!
+ * Reset nth bit in the integer c
+ */
+#define BITRESET(c, n) ((c) & ~(1 << (n)))
+
+enum KeyEvent {
+	KDepress,
+	KRelease
+};
+
+/*!
+ * This enum represents the keypad state machine to maintain debounce logic
+ * for key press/release.
+ */
+enum KeyState {
+
+	/*!
+	 * Key press state.
+	 */
+	KStateUp,
+
+	/*!
+	 * Key press debounce state.
+	 */
+	KStateFirstDown,
+
+	/*!
+	 * Key release state.
+	 */
+	KStateDown,
+
+	/*!
+	 * Key release debounce state.
+	 */
+	KStateFirstUp
+};
+
+/*!
+ * Keypad Private Data Structure
+ */
+struct keypad_priv {
+
+	/*!
+	 * Keypad state machine.
+	 */
+	enum KeyState iKeyState;
+
+	/*!
+	 * Number of rows configured in the keypad matrix
+	 */
+	unsigned long kpp_rows;
+
+	/*!
+	 * Number of Columns configured in the keypad matrix
+	 */
+	unsigned long kpp_cols;
+};
+
+/*!
+ * Keypad Data Structure
+ * */
+struct kpp_key_info {
+	enum KeyEvent evt;
+	unsigned short val;
+};
+
+int mxc_kpp_init(void);
+int mxc_kpp_getc(struct kpp_key_info **);
+
+/*!
+ * These functions are used to configure and the GPIO pins for keypad to
+ * activate and deactivate it.
+ */
+void setup_mxc_kpd(void);
+
+
+#endif				/* __MXC_KEYB_H__ */
diff --git a/include/mxsfb.h b/include/mxsfb.h
new file mode 100644
index 00000000000..85f24aa2865
--- /dev/null
+++ b/include/mxsfb.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MXSFB_H__
+#define __MXSFB_H__
+
+#include <linux/fb.h>
+
+#ifdef CONFIG_VIDEO_MXS
+struct display_panel {
+	unsigned int reg_base;
+	unsigned int width;
+	unsigned int height;
+	unsigned int gdfindex;
+	unsigned int gdfbytespp;
+};
+
+void mxs_lcd_get_panel(struct display_panel *panel);
+void lcdif_power_down(void);
+int mxs_lcd_panel_setup(struct fb_videomode mode, int bpp,
+	uint32_t base_addr);
+#endif
+
+#endif				/* __MXSFB_H__ */
diff --git a/include/net.h b/include/net.h
index b02e4f630c0..444c59771fb 100644
--- a/include/net.h
+++ b/include/net.h
@@ -397,6 +397,8 @@ struct ip_hdr {
 
 #define IP_HDR_SIZE		(sizeof(struct ip_hdr))
 
+#define IP_MIN_FRAG_DATAGRAM_SIZE	(IP_HDR_SIZE + 8)
+
 /*
  *	Internet Protocol (IP) + UDP header.
  */
diff --git a/include/part.h b/include/part.h
index 53cfbdd8767..1db0db4d9c2 100644
--- a/include/part.h
+++ b/include/part.h
@@ -103,6 +103,7 @@ struct disk_part {
 struct blk_desc *blk_get_dev(const char *ifname, int dev);
 
 struct blk_desc *mg_disk_get_dev(int dev);
+struct blk_desc *sata_get_dev(int dev);
 int host_get_dev_err(int dev, struct blk_desc **blk_devp);
 
 /* disk/part.c */
@@ -257,6 +258,7 @@ extern const struct block_drvr block_drvr[];
 static inline struct blk_desc *blk_get_dev(const char *ifname, int dev)
 { return NULL; }
 static inline struct blk_desc *mg_disk_get_dev(int dev) { return NULL; }
+static inline struct blk_desc *sata_get_dev(int dev) { return NULL; }
 
 static inline int part_get_info(struct blk_desc *dev_desc, int part,
 				struct disk_partition *info) { return -1; }
@@ -294,7 +296,8 @@ part_get_info_by_dev_and_name_or_num(const char *dev_iface,
 #ifdef CONFIG_SPL_BUILD
 # define part_print_ptr(x)	NULL
 # if defined(CONFIG_SPL_FS_EXT4) || defined(CONFIG_SPL_FS_FAT) || \
-	defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION)
+	defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION) || \
+	defined(CONFIG_DUAL_BOOTLOADER) || defined(CONFIG_IMX_TRUSTY_OS)
 #  define part_get_info_ptr(x)	x
 # else
 #  define part_get_info_ptr(x)	NULL
@@ -419,6 +422,15 @@ int is_valid_gpt_buf(struct blk_desc *dev_desc, void *buf);
 int write_mbr_and_gpt_partitions(struct blk_desc *dev_desc, void *buf);
 
 /**
+ * write_backup_gpt_partitions - write MBR, backup gpt table.
+ * @param dev_desc - block device descriptor
+ * @param buf - buffer which contains the MBR and Primary GPT info
+ *
+ * @return - '0' on success, otherwise error
+ */
+int write_backup_gpt_partitions(struct blk_desc *dev_desc, void *buf);
+
+/**
  * gpt_verify_headers() - Function to read and CRC32 check of the GPT's header
  *                        and partition table entries (PTE)
  *
@@ -467,6 +479,11 @@ int gpt_verify_partitions(struct blk_desc *dev_desc,
  */
 int get_disk_guid(struct blk_desc *dev_desc, char *guid);
 
+#if (defined(CONFIG_DUAL_BOOTLOADER) || defined(CONFIG_IMX_TRUSTY_OS)) && defined(CONFIG_SPL_BUILD)
+int part_get_info_efi_by_name(struct blk_desc *dev_desc, const char *name,
+		      struct disk_partition *info);
+#endif
+
 #endif
 
 #if CONFIG_IS_ENABLED(DOS_PARTITION)
diff --git a/include/power-domain.h b/include/power-domain.h
index 113276b5119..bebf0b8586e 100644
--- a/include/power-domain.h
+++ b/include/power-domain.h
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (c) 2016, NVIDIA CORPORATION.
+ * Copyright 2017 NXP
+ *
  */
 
 #ifndef _POWER_DOMAIN_H
@@ -64,6 +66,19 @@ struct power_domain {
 };
 
 /**
+ * power_domain_lookup_name - Lookup the power domain device by name and request it.
+ *
+ * This looks up and requests a provider power domain by using its device name. This
+ * skip the associated client device, but directly get the power domain device.
+ *
+ * @name:        The power domain device's name.
+ * @power_domain        A pointer to a power domain struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+
+int power_domain_lookup_name(const char *name, struct power_domain *power_domain);
+
+/**
  * power_domain_get - Get/request the power domain for a device.
  *
  * This looks up and requests a power domain. Each device is assumed to have
diff --git a/include/power/bd71837.h b/include/power/bd71837.h
index 75e07e1de31..469973ce19f 100644
--- a/include/power/bd71837.h
+++ b/include/power/bd71837.h
@@ -100,4 +100,6 @@ enum {
 #define BD71847_LDO5_RANGE_MASK		0x20
 #define BD71837_LDO7_MASK		0x0f
 
+int power_bd71837_init(unsigned char bus);
+
 #endif
diff --git a/include/recovery.h b/include/recovery.h
new file mode 100644
index 00000000000..c6b097efeb3
--- /dev/null
+++ b/include/recovery.h
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2017 NXP
+ */
+
+#ifndef __RECOVERY_H_
+#define __RECOVERY_H_
+
+struct reco_envs {
+	char *cmd;
+	char *args;
+};
+
+void board_recovery_setup(void);
+
+#endif
diff --git a/include/reset.h b/include/reset.h
index 965f02e0cee..166fc01f7df 100644
--- a/include/reset.h
+++ b/include/reset.h
@@ -226,6 +226,8 @@ int reset_get_by_index_nodev(ofnode node, int index,
  */
 int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk);
 
+int reset_get_bulk_nodev(ofnode node, struct reset_ctl_bulk *bulk);
+
 /**
  * reset_get_by_name - Get/request a reset signal by name.
  *
diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h
index ef26e721762..22b6a33a807 100644
--- a/include/scmi_protocols.h
+++ b/include/scmi_protocols.h
@@ -40,6 +40,12 @@ enum scmi_status_code {
 	SCMI_PROTOCOL_ERROR = -10,
 };
 
+enum scmi_common_message_id {
+	SCMI_PROTOCOL_VERSION = 0x000,
+	SCMI_PROTOCOL_ATTRIBUTES = 0x001,
+	SCMI_PROTOCOL_MESSAGE_ATTRIBUTES = 0x002
+};
+
 /*
  * SCMI Clock Protocol
  */
@@ -289,4 +295,122 @@ struct scmi_voltd_level_get_out {
 	s32 voltage_level;
 };
 
+/*
+ * SCMI Power Protocol
+ */
+
+enum scmi_power_message_id {
+	SCMI_POWER_DOMAIN_ATTRIBUTES = 0x3,
+	SCMI_POWER_STATE_SET = 0x4,
+	SCMI_POWER_STATE_GET = 0x5,
+	SCMI_POWER_STATE_NOTIFY = 0x6,
+};
+
+
+#define SCMI_POWER_STATE_GENERIC_ON		(0 << 30)
+#define SCMI_POWER_STATE_GENERIC_OFF	(1 << 30)
+
+struct scmi_power_set_state {
+	u32 flags;
+	u32 domain;
+	u32 state;
+};
+
+struct scmi_power_set_state_out {
+	s32 status;
+};
+
+struct scmi_power_get_state {
+	u32 domain;
+};
+
+struct scmi_power_get_state_out {
+	s32 status;
+	u32 state;
+};
+
+/*
+ * SCMI Sensor protocol
+ */
+
+enum scmi_sensor_message_id {
+	SCMI_SENSOR_DESCRIPTION_GET = 0x3,
+	SCMI_SENSOR_TRIP_POINT_NOTIFY = 0x4,
+	SCMI_SENSOR_TRIP_POINT_CONFIG = 0x5,
+	SCMI_SENSOR_READING_GET = 0x6,
+	SCMI_SENSOR_AXIS_DESCRIPTION_GET = 0x7,
+	SCMI_SENSOR_LIST_UPDATE_INTERVALS = 0x8,
+	SCMI_SENSOR_CONFIG_GET = 0x9,
+	SCMI_SENSOR_CONFIG_SET = 0xA,
+	SCMI_SENSOR_CONTINUOUS_UPDATE_NOTIFY = 0xB,
+};
+
+struct scmi_protocol_attributes_p2a_sensor {
+	int32_t status;
+	int16_t num_sensors;
+	uint8_t max_reqs;
+	uint8_t res;
+	uint32_t sensor_reg_low;
+	uint32_t sensor_reg_high;
+	uint32_t sensor_reg_len;
+};
+
+#define SCMI_MAX_STR_SIZE   16
+
+struct scmi_msg_resp_attrs {
+	s32 min_range_low;
+	s32 min_range_high;
+	s32 max_range_low;
+	s32 max_range_high;
+};
+
+struct scmi_sensor_desc {
+	u32 id;
+	u32 attr_low;
+	u32 attr_high;
+	u8 name[SCMI_MAX_STR_SIZE];
+	u32 power;
+	u32 resolution;
+	struct scmi_msg_resp_attrs scalar_attrs;
+};
+
+struct scmi_sensor_description_get_a2p {
+	uint32_t desc_index;
+};
+
+struct scmi_sensor_descrition_get_p2a {
+	int32_t status;
+	uint32_t num_sensor_flags;
+	struct scmi_sensor_desc desc[1];
+};
+
+struct scmi_sensor_config_get_a2p {
+	uint32_t sensor_id;
+};
+
+struct scmi_sensor_config_get_p2a {
+	int32_t status;
+	uint32_t sensor_config;
+};
+
+/*
+ * Sensor Reading Get
+ */
+struct scmi_sensor_reading_get_a2p {
+	uint32_t sensor_id;
+	uint32_t flags;
+};
+
+struct scmi_sensor_val {
+	uint32_t value_low;
+	uint32_t value_high;
+	uint32_t timestap_low;
+	uint32_t timestap_high;
+};
+
+struct scmi_sensor_reading_get_p2a {
+	int32_t status;
+	struct scmi_sensor_val val;
+};
+
 #endif /* _SCMI_PROTOCOLS_H */
diff --git a/include/serial.h b/include/serial.h
index 19a8c0c67d2..357d8811629 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -187,6 +187,14 @@ struct dm_serial_ops {
 	 */
 	int (*getc)(struct udevice *dev);
 	/**
+	 * puts() - puts a string
+	 *
+	 * @dev: Device pointer
+	 * @str: string to write
+	 * @return 0 if OK, -ve on error
+	 */
+	int (*puts)(struct udevice *dev, const char *str);
+	/**
 	 * putc() - Write a character
 	 *
 	 * @dev: Device pointer
diff --git a/include/spl.h b/include/spl.h
index 8ceb3c0f095..951616b8951 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -229,6 +229,9 @@ struct spl_image_info {
 	ulong dcrc_length;
 	ulong dcrc;
 #endif
+#ifdef CONFIG_IMX_TRUSTY_OS
+	uint64_t rbindex;
+#endif
 };
 
 /**
@@ -329,6 +332,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
 
 #define SPL_COPY_PAYLOAD_ONLY	1
 #define SPL_FIT_FOUND		2
+#define SPL_FIT_BYPASS_POST_LOAD		4
 
 /**
  * spl_load_legacy_img() - Loads a legacy image from a device.
@@ -810,7 +814,7 @@ int board_return_to_bootrom(struct spl_image_info *spl_image,
  * board_spl_fit_post_load - allow process images after loading finished
  * @fit: Pointer to a valid Flattened Image Tree blob
  */
-void board_spl_fit_post_load(const void *fit);
+void board_spl_fit_post_load(const void *fit, struct spl_image_info *spl_image);
 
 /**
  * board_spl_fit_size_align - specific size align before processing payload
diff --git a/include/trusty/avb.h b/include/trusty/avb.h
new file mode 100644
index 00000000000..02128078240
--- /dev/null
+++ b/include/trusty/avb.h
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef TRUSTY_AVB_H_
+#define TRUSTY_AVB_H_
+
+#include <trusty/sysdeps.h>
+#include <trusty/trusty_ipc.h>
+#include <interface/avb/avb.h>
+
+/*
+ * Initialize AVB TIPC client. Returns one of trusty_err.
+ *
+ * @dev: initialized with trusty_ipc_dev_create
+ */
+int avb_tipc_init(struct trusty_ipc_dev *dev);
+/*
+ * Shutdown AVB TIPC client.
+ *
+ * @dev: initialized with trusty_ipc_dev_create
+ */
+void avb_tipc_shutdown(struct trusty_ipc_dev *dev);
+/*
+ * Send request to secure side to read rollback index.
+ * Returns one of trusty_err.
+ *
+ * @slot:    rollback index slot
+ * @value:   rollback index value stored here
+ */
+int trusty_read_rollback_index(uint32_t slot, uint64_t *value);
+/*
+ * Send request to secure side to write rollback index
+ * Returns one of trusty_err.
+ *
+ * @slot:    rollback index slot
+ * @value:   rollback index value to write
+ */
+int trusty_write_rollback_index(uint32_t slot, uint64_t value);
+/*
+ * Send request to secure side to read permanent attributes. When permanent
+ * attributes are stored in RPMB, a hash of the permanent attributes which is
+ * given to AVB during verification MUST still be backed by write-once hardware.
+ *
+ * Copies attributes received by secure side to |attributes|. If |size| does not
+ * match the size returned by the secure side, an error is returned. Returns one
+ * of trusty_err.
+ *
+ * @attributes:  caller allocated buffer
+ * @size:        size of |attributes|
+ */
+int trusty_read_permanent_attributes(uint8_t *attributes, uint32_t size);
+/*
+ * Send request to secure side to write permanent attributes. Permanent
+ * attributes can only be written to storage once.
+ *
+ * Returns one of trusty_err.
+ */
+int trusty_write_permanent_attributes(uint8_t *attributes, uint32_t size);
+/*
+ * Send request to secure side to read vbmeta public key.
+ *
+ * Copies public key received by secure side to |publickey|. If |size| does not
+ * match the size returned by the secure side, an error is returned. Returns one
+ * of trusty_err.
+ *
+ * @publickey:   caller allocated buffer
+ * @size:        size of |publickey|
+ */
+int trusty_read_vbmeta_public_key(uint8_t *publickey, uint32_t size);
+/*
+ * Send request to secure side to write vbmeta public key. Public key
+ * can only be written to storage once.
+ *
+ * Returns one of trusty_err.
+ */
+int trusty_write_vbmeta_public_key(uint8_t *publickey, uint32_t size);
+/*
+ * Send request to secure side to read device lock state from RPMB.
+ *
+ * Returns one of trusty_err.
+ */
+int trusty_read_lock_state(uint8_t *lock_state);
+/*
+ * Send request to secure side to write device lock state to RPMB. If the lock
+ * state is changed, all rollback index data will be cleared.
+ *
+ * Returns one of trusty_err.
+ */
+int trusty_write_lock_state(uint8_t lock_state);
+/*
+ * Send request to secure side to lock the boot state. After this is invoked,
+ * the non-secure side will not be able to write to data managed by the AVB
+ * service until next boot.
+ *
+ * Returns one of trusty_err.
+ */
+int trusty_lock_boot_state(void);
+/*
+ * Send request to secure side to read oem device unlock state from RPMB.
+ *
+ * Returns one of trusty_err.
+ */
+int trusty_read_oem_unlock_device_permission(uint8_t *lock_state);
+
+#endif /* TRUSTY_AVB_H_ */
diff --git a/include/trusty/hwcrypto.h b/include/trusty/hwcrypto.h
new file mode 100644
index 00000000000..e9f03442076
--- /dev/null
+++ b/include/trusty/hwcrypto.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ * Copyright NXP 2018
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+
+#ifndef TRUSTY_HWCRYPTO_H_
+#define TRUSTY_HWCRYPTO_H_
+
+#include <trusty/sysdeps.h>
+#include <trusty/trusty_ipc.h>
+#include <interface/hwcrypto/hwcrypto.h>
+
+/*
+ * Initialize HWCRYPTO TIPC client. Returns one of trusty_err.
+ *
+ * @dev: initialized with trusty_ipc_dev_create
+ */
+int hwcrypto_tipc_init(struct trusty_ipc_dev *dev);
+/*
+ * Shutdown HWCRYPTO TIPC client.
+ *
+ * @dev: initialized with trusty_ipc_dev_create
+ */
+void hwcrypto_tipc_shutdown(struct trusty_ipc_dev *dev);
+/*
+ * Send request to secure side to calculate sha256 hash with caam.
+ * Returns one of trusty_err.
+ *
+ * @in_addr:   start address of the input buf
+ * @in_len:    size of the input buf
+ * @out_addr:  start address of the output buf
+ * @out_len:   size of the output buf
+ * @algo:      hash algorithm type expect to use
+ */
+int hwcrypto_hash(uint32_t in_addr, uint32_t in_len, uint32_t out_addr,
+                  uint32_t out_len, enum hwcrypto_hash_algo algo);
+
+/*
+ * Send request to secure side to generate blob with caam.
+ * Returns one of trusty_err.
+ *
+ * @plain_pa:   physical start address of the plain blob buffer.
+ * @plain_size: size of the plain blob buffer.
+ * @blob_pa:    physical start address of the generated blob buffer.
+ */
+int hwcrypto_gen_blob(uint32_t plain_pa,
+                      uint32_t plain_size, uint32_t blob_pa);
+
+/* Send request to secure side to generate rng with caam.
+ * Returns one of trusty_err.
+ *
+ * @buf: physical start address of the output rng buf.
+ * @len: size of required rng.
+ * */
+int hwcrypto_gen_rng(uint32_t buf, uint32_t len);
+
+/* Send request to secure side to generate bkek with caam.
+ * Returns one of trusty_err.
+ *
+ * @buf: physical start address of the output rng buf.
+ * @len: size of required rng.
+ * */
+int hwcrypto_gen_bkek(uint32_t buf, uint32_t len);
+
+/* Send request to secure side to lock boot state, so some
+ * hwcrypto commands can't be used outside of bootloader.
+ * Returns one of trusty_err.
+ * */
+int hwcrypto_lock_boot_state(void);
+
+/* Send request to secure side to provision widevine keybox
+ * */
+int hwcrypto_provision_wv_key(const char *data, uint32_t data_size);
+
+/* Send request to secure side to provision encrypted widevine keybox
+ * */
+int hwcrypto_provision_wv_key_enc(const char *data, uint32_t data_size);
+
+#endif /* TRUSTY_HWCRYPTO_H_ */
diff --git a/include/trusty/imx_snvs.h b/include/trusty/imx_snvs.h
new file mode 100644
index 00000000000..e2e2405c619
--- /dev/null
+++ b/include/trusty/imx_snvs.h
@@ -0,0 +1,11 @@
+
+#ifndef _IMX_SNVS_H_
+#define _IMX_SNVS_H_
+#include <trusty/trusty_ipc.h>
+
+uint32_t trusty_snvs_read(uint32_t target);
+void trusty_snvs_write(uint32_t target, uint32_t value);
+void trusty_snvs_update_lpcr(uint32_t target, uint32_t enable);
+int imx_snvs_init(struct trusty_ipc_dev *dev);
+
+#endif
diff --git a/include/trusty/keymaster.h b/include/trusty/keymaster.h
new file mode 100644
index 00000000000..c08e99476e3
--- /dev/null
+++ b/include/trusty/keymaster.h
@@ -0,0 +1,182 @@
+/*
+ * Copyright (C) 2017 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef TRUSTY_KEYMASTER_H_
+#define TRUSTY_KEYMASTER_H_
+
+#include <trusty/sysdeps.h>
+#include <trusty/trusty_ipc.h>
+#include <interface/keymaster/keymaster.h>
+
+/*
+ * Initialize Keymaster TIPC client. Returns one of trusty_err.
+ *
+ * @dev: initialized with trusty_ipc_dev_create
+ */
+int km_tipc_init(struct trusty_ipc_dev *dev);
+
+/*
+ * Shutdown Keymaster TIPC client.
+ *
+ * @dev: initialized with trusty_ipc_dev_create
+ */
+void km_tipc_shutdown(struct trusty_ipc_dev *dev);
+
+/*
+ * Set Keymaster boot parameters. Returns one of trusty_err.
+ *
+ * @os_version: OS version from Android image header
+ * @os_patchlevel: OS patch level from Android image header
+ * @verified_boot_state: one of keymaster_verified_boot_t
+ * @device_locked: nonzero if device is locked
+ * @verified_boot_key_hash: hash of key used to verify Android image
+ * @verified_boot_key_hash_size: size of verified_boot_key_hash
+ * @verified_boot_hash: cumulative hash of all images verified thus far.
+ *                      May be NULL if not computed.
+ * @verified_boot_hash_size: size of verified_boot_hash
+ */
+int trusty_set_boot_params(uint32_t os_version, uint32_t os_patchlevel,
+                           keymaster_verified_boot_t verified_boot_state,
+                           bool device_locked,
+                           const uint8_t *verified_boot_key_hash,
+                           uint32_t verified_boot_key_hash_size,
+                           const uint8_t *verified_boot_hash,
+                           uint32_t verified_boot_hash_size);
+
+/*
+ * Set Keymaster attestation key. Returns one of trusty_err.
+ *
+ * @key: buffer containing key
+ * @key_size: size of key in bytes
+ * @algorithm: one of KM_ALGORITHM_RSA or KM_ALGORITHM_EC
+ */
+int trusty_set_attestation_key(const uint8_t *key, uint32_t key_size,
+                               keymaster_algorithm_t algorithm);
+
+/*
+ * Append certificate to Keymaster attestation certificate chain. Returns
+ * one of trusty_err.
+ *
+ * @cert: buffer containing certificate
+ * @cert_size: size of certificate in bytes
+ * @algorithm: one of KM_ALGORITHM_RSA or KM_ALGORITHM_EC
+ */
+int trusty_append_attestation_cert_chain(const uint8_t *cert,
+                                         uint32_t cert_size,
+                                         keymaster_algorithm_t algorithm);
+/*
+ * Set encrypted Keymaster attestation key. Returns one of trusty_err.
+ *
+ * @key: buffer containing encrypted key
+ * @key_size: size of key in bytes
+ * @algorithm: one of KM_ALGORITHM_RSA or KM_ALGORITHM_EC
+ */
+int trusty_set_attestation_key_enc(const uint8_t *key,
+                                   uint32_t key_size,
+                                   keymaster_algorithm_t algorithm);
+
+/*
+ * Append encrypted certificate to Keymaster attestation certificate chain. Returns
+ * one of trusty_err.
+ *
+ * @cert: buffer containing encrypted certificate
+ * @cert_size: size of certificate in bytes
+ * @algorithm: one of KM_ALGORITHM_RSA or KM_ALGORITHM_EC
+ */
+int trusty_append_attestation_cert_chain_enc(const uint8_t *cert,
+                                             uint32_t cert_size,
+                                             keymaster_algorithm_t algorithm);
+/*
+ * Reads a CA Request from Keymaster. On success allocates a new CA Request
+ * message at |*ca_request_p|, and the caller takes ownership. Returns one
+ * of trusty_err.
+ *
+ * @operation_start: Operation Start message
+ * @operation_start_size: size of operation_start
+ * @ca_request_p: location of newly allocated CA Request message
+ * @ca_request_size_p: location of size of the CA Request message
+ */
+int trusty_atap_get_ca_request(const uint8_t *operation_start,
+                               uint32_t operation_start_size,
+                               uint8_t** ca_request_p,
+                               uint32_t* ca_request_size_p);
+/*
+ * Sends the CA Response to Keymaster. Returns one of trusty_err.
+ *
+ * @ca_response: CA Response message
+ * @ca_response_size: size of ca_response
+ */
+int trusty_atap_set_ca_response(const uint8_t *ca_response,
+                                uint32_t ca_response_size);
+
+/*
+* Reads the UUID from the certificate of the last provisioned attestation
+* credentials as a c-string into |*uuid_p|. Caller takes ownership of
+* |*uuid_p|. Returns one of trusty_err.
+*
+* @uuid_p: location of newly allocated UUID c-string
+*/
+int trusty_atap_read_uuid_str(char **uuid_p);
+
+/*
+ * SetProductId is only called once to set the secure product id. Caller should
+ * read the product id from permanent attributes structure and set the product
+ * id while fusing the permanent attributes.
+ *
+ * @product_id: The product id to be set.
+ * @size: The size of the product id.
+ */
+int trusty_set_product_id(const uint8_t *product_id, uint32_t size);
+
+/*
+ * trusty_get_mppubk is called to get the mppubk from trusty side.
+ *
+ * @mppubk: Pointer to the buffer which store the mppubk.
+ * @size:  Pointer to The size of mppubk.
+ */
+int trusty_get_mppubk(uint8_t *mppubk, uint32_t* size);
+
+/* trusty_verify_secure_unlock is called to the verify the secure unlock
+ * credential.
+ *
+ * @unlock_credential: Poniter to the unlock credential.
+ * @credential_size: credential size.
+ * @serial: serial number to verify.
+ * @serial_size: serial number size.
+ */
+int trusty_verify_secure_unlock(uint8_t *unlock_credential,
+                                uint32_t credential_size,
+                                uint8_t *serial, uint32_t serial_size);
+
+/*
+ * trusty_set_attestation_id is called to set attestation Device ID.
+ * */
+int trusty_set_attestation_id(void);
+
+/*
+ * trusty_set_boot_patch_level is called to set the boot patch level.
+ * */
+int trusty_set_boot_patch_level(uint32_t boot_patch_level);
+
+#endif /* TRUSTY_KEYMASTER_H_ */
diff --git a/include/trusty/keymaster_serializable.h b/include/trusty/keymaster_serializable.h
new file mode 100644
index 00000000000..280adda5716
--- /dev/null
+++ b/include/trusty/keymaster_serializable.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2017 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef TRUSTY_KEYMASTER_SERIALIZABLE_H_
+#define TRUSTY_KEYMASTER_SERIALIZABLE_H_
+
+#include <trusty/keymaster.h>
+
+/**
+ * Simple serialization routines for dynamically sized keymaster messages.
+ */
+
+/**
+ * Appends |data_len| bytes at |data| to |buf|. Performs no bounds checking,
+ * assumes sufficient memory allocated at |buf|. Returns |buf| + |data_len|.
+ */
+uint8_t *append_to_buf(uint8_t *buf, const void *data, size_t data_len);
+
+/**
+ * Appends |val| to |buf|. Performs no bounds checking. Returns |buf| +
+ * sizeof(uint32_t).
+ */
+uint8_t *append_uint32_to_buf(uint8_t *buf, uint32_t val);
+
+/**
+ * Appends a sized buffer to |buf|. First appends |data_len| to |buf|, then
+ * appends |data_len| bytes at |data| to |buf|. Performs no bounds checking.
+ * Returns |buf| + sizeof(uint32_t) + |data_len|.
+ */
+uint8_t *append_sized_buf_to_buf(uint8_t *buf, const uint8_t *data,
+                                 uint32_t data_len);
+
+/**
+ * Serializes a km_boot_params structure. On success, allocates |*out_size|
+ * bytes to |*out| and writes the serialized |params| to |*out|. Caller takes
+ * ownership of |*out|. Returns one of trusty_err.
+ */
+int km_boot_params_serialize(const struct km_boot_params *params, uint8_t **out,
+                             uint32_t *out_size);
+
+/**
+ * Serializes a km_attestation_data structure. On success, allocates |*out_size|
+ * bytes to |*out| and writes the serialized |data| to |*out|. Caller takes
+ * ownership of |*out|. Returns one of trusty_err.
+ */
+int km_attestation_data_serialize(const struct km_attestation_data *data,
+                                  uint8_t **out, uint32_t *out_size);
+
+/**
+ * Serializes a km_attestation_id_data structure. On success, writes the
+ * serialized |data| to |*out|. Returns one of trusty_err.
+ */
+int km_attestation_id_data_serialize(const uint8_t *data, uint32_t data_size,
+                                     uint8_t** out, uint32_t *out_size);
+
+/**
+ * Serializes a km_secure_unlock_data structure. On success, allocates |*out_size|
+ * bytes to |*out| and writes the serialized |data| to |*out|. Caller takes
+ * ownership of |*out|. Returns one of trusty_err.
+ */
+int km_secure_unlock_data_serialize(const struct km_secure_unlock_data *data,
+                                  uint8_t **out, uint32_t *out_size);
+
+/**
+ * Serializes a km_raw_buffer structure. On success, allocates |*out_size|
+ * bytes to |*out| and writes the serialized |data| to |*out|. Caller takes
+ * ownership of |*out|. Returns one of trusty_err.
+ */
+int km_raw_buffer_serialize(const struct km_raw_buffer *buf, uint8_t** out,
+                            uint32_t *out_size);
+
+#endif /* TRUSTY_KEYMASTER_SERIALIZABLE_H_ */
diff --git a/include/trusty/libtipc.h b/include/trusty/libtipc.h
new file mode 100644
index 00000000000..f06e9e9a0e6
--- /dev/null
+++ b/include/trusty/libtipc.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef TRUSTY_LIBTIPC_H_
+#define TRUSTY_LIBTIPC_H_
+
+#include <trusty/avb.h>
+#include <trusty/keymaster.h>
+#include <trusty/sysdeps.h>
+#include <trusty/hwcrypto.h>
+#include <trusty/imx_snvs.h>
+
+/*
+ * Initialize TIPC library
+ */
+int trusty_ipc_init(void);
+/*
+ * Shutdown TIPC library
+ */
+void trusty_ipc_shutdown(void);
+
+#endif /* TRUSTY_LIBTIPC_H_ */
diff --git a/include/trusty/rpmb.h b/include/trusty/rpmb.h
new file mode 100644
index 00000000000..810b8a1d7f8
--- /dev/null
+++ b/include/trusty/rpmb.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef TRUSTY_RPMB_H_
+#define TRUSTY_RPMB_H_
+
+#include <trusty/sysdeps.h>
+#include <trusty/trusty_ipc.h>
+
+#define MMC_BLOCK_SIZE 512
+
+/*
+ * Initialize RPMB storage proxy. Returns one of trusty_err.
+ *
+ * @dev:      initialized with trusty_ipc_dev_create
+ * @rpmb_dev: Context of RPMB device, initialized with rpmb_storage_get_ctx
+ */
+int rpmb_storage_proxy_init(struct trusty_ipc_dev *dev, void *rpmb_dev);
+/*
+ * Shutdown RPMB storage proxy
+ *
+ * @dev: initialized with trusty_ipc_dev_create
+ */
+void rpmb_storage_proxy_shutdown(struct trusty_ipc_dev *dev);
+/*
+ * Execute RPMB command. Implementation is platform specific.
+ * Returns one of trusty_err.
+ *
+ * @rpmb_dev:            Context of RPMB device, initialized with
+ *                       rpmb_storage_get_ctx
+ * @reliable_write_data: Buffer containing RPMB structs for reliable write
+ * @reliable_write_size: Size of reliable_write_data
+ * @write_data:          Buffer containing RPMB structs for write
+ * @write_size:          Size of write_data
+ * @read_data:           Buffer to be filled with RPMB structs read from RPMB
+ *                       partition
+ * @read_size:           Size of read_data
+ */
+int rpmb_storage_send(void *rpmb_dev,
+                      const void *reliable_write_data,
+                      size_t reliable_write_size,
+                      const void *write_data, size_t write_size,
+                      void *read_buf, size_t read_size);
+/*
+ * Return context for RPMB device. This is called when the RPMB storage proxy is
+ * initialized, and subsequently used when issuing RPMB storage requests.
+ * Implementation is platform specific.
+ */
+void *rpmb_storage_get_ctx(void);
+
+/*
+ * Put back RPMB device. This is called when the RPMB storage proxy is
+ * shutdown
+ */
+void rpmb_storage_put_ctx(void *dev);
+
+/*
+ * Set rpmb key by secure side.
+ */
+int storage_set_rpmb_key(void);
+
+/*
+ * Erase rpmb storage by secure side.
+ */
+int storage_erase_rpmb(void);
+
+#endif /* TRUSTY_RPMB_H_ */
diff --git a/include/trusty/sysdeps.h b/include/trusty/sysdeps.h
new file mode 100644
index 00000000000..b21a29ca08d
--- /dev/null
+++ b/include/trusty/sysdeps.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef TRUSTY_SYSDEPS_H_
+#define TRUSTY_SYSDEPS_H_
+/*
+ * Change these includes to match your platform to bring in the equivalent
+ * types available in a normal C runtime. At least things like uint64_t,
+ * uintptr_t, and bool (with |false|, |true| keywords) must be present.
+ */
+#include <common.h>
+#include <compiler.h>
+#include <irq_func.h>
+
+/*
+ * These attribute macros may need to be adjusted if not using gcc or clang.
+ */
+#define TRUSTY_ATTR_PACKED __attribute__((packed))
+#define TRUSTY_ATTR_NO_RETURN __attribute__((noreturn))
+#define TRUSTY_ATTR_SENTINEL __attribute__((__sentinel__))
+#define TRUSTY_ATTR_WARN_UNUSED_RESULT __attribute__((warn_unused_result))
+
+#define PAGE_SIZE 4096
+/*
+ * Struct containing attributes for memory to be shared with secure size.
+ */
+struct ns_mem_page_info {
+    uint64_t attr;
+};
+
+struct trusty_dev;
+
+/*
+ * Lock/unlock mutex associated with @dev. These can be safely empty in a single
+ * threaded environment.
+ *
+ * @dev: Trusty device initialized with trusty_dev_init
+ */
+void trusty_lock(struct trusty_dev *dev);
+void trusty_unlock(struct trusty_dev *dev);
+/*
+ * Disable/enable IRQ interrupts and save/restore @state
+ */
+void trusty_local_irq_disable(unsigned long *state);
+void trusty_local_irq_restore(unsigned long *state);
+/*
+ * Put in standby state waiting for interrupt.
+ *
+ * @dev: Trusty device initialized with trusty_dev_init
+ */
+void trusty_idle(struct trusty_dev *dev);
+/*
+ * Aborts the program or reboots the device.
+ */
+void trusty_abort(void) TRUSTY_ATTR_NO_RETURN;
+/*
+ * Print a formatted string. @format must point to a NULL-terminated string, and
+ * is followed by arguments to be printed.
+ */
+void trusty_printf(const char *format, ...);
+/*
+ * Copy @n bytes from @src to @dest.
+ */
+void *trusty_memcpy(void *dest, const void *src, size_t n);
+/*
+ * Set @n bytes starting at @dest to @c. Returns @dest.
+ */
+void *trusty_memset(void *dest, const int c, size_t n);
+/*
+ * Copy string from @src to @dest, including the terminating NULL byte.
+ *
+ * The size of the array at @dest should be long enough to contain the string
+ * at @src, and should not overlap in memory with @src.
+ */
+char *trusty_strcpy(char *dest, const char *src);
+/*
+ * Returns the length of @str, excluding the terminating NULL byte.
+ */
+size_t trusty_strlen(const char *str);
+/*
+ * Allocate @n elements of size @size. Initializes memory to 0, returns pointer
+ * to it.
+ */
+void *trusty_calloc(size_t n, size_t size) TRUSTY_ATTR_WARN_UNUSED_RESULT;
+/*
+ * Free memory at @addr allocated with trusty_calloc.
+ */
+void trusty_free(void *addr);
+/*
+ * Allocate @count contiguous pages to be shared with secure side.
+ *
+ * Returns:   vaddr of allocated memory
+ */
+void *trusty_alloc_pages(unsigned count) TRUSTY_ATTR_WARN_UNUSED_RESULT;
+/*
+ * Free @count pages at @vaddr allocated by trusty_alloc_pages
+ */
+void trusty_free_pages(void *vaddr, unsigned count);
+
+#endif /* TRUSTY_SYSDEPS_H_ */
diff --git a/include/trusty/trusty_dev.h b/include/trusty/trusty_dev.h
new file mode 100644
index 00000000000..899c8690fad
--- /dev/null
+++ b/include/trusty/trusty_dev.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef TRUSTY_TRUSTY_DEV_H_
+#define TRUSTY_TRUSTY_DEV_H_
+
+#include <trusty/sysdeps.h>
+
+/*
+ * Architecture specific Trusty device struct.
+ *
+ * @priv_data:   system dependent data, may be unused
+ * @api_version: TIPC version
+ */
+struct trusty_dev {
+    void *priv_data;
+    uint32_t api_version;
+};
+
+/*
+ * Initializes @dev with @priv, and gets the API version by calling
+ * into Trusty. Returns negative on error.
+ */
+int trusty_dev_init(struct trusty_dev *dev, void *priv);
+
+/*
+ * Cleans up anything related to @dev. Returns negative on error.
+ */
+int trusty_dev_shutdown(struct trusty_dev *dev);
+
+/*
+ * Invokes creation of queueless Trusty IPC device on the secure side.
+ * @buf will be mapped into Trusty's address space.
+ *
+ * @dev:      trusty device, initialized with trusty_dev_init
+ * @buf:      physical address info of buffer to share with Trusty
+ * @buf_size: size of @buf
+ */
+int trusty_dev_init_ipc(struct trusty_dev *dev, struct ns_mem_page_info *buf,
+                        uint32_t buf_size);
+/*
+ * Invokes execution of command on the secure side.
+ *
+ * @dev:      trusty device, initialized with trusty_dev_init
+ * @buf:      physical address info of shared buffer containing command
+ * @buf_size: size of command data
+ */
+int trusty_dev_exec_ipc(struct trusty_dev *dev, struct ns_mem_page_info *buf,
+                        uint32_t buf_size);
+/*
+ * Invokes deletion of queueless Trusty IPC device on the secure side.
+ * @buf is unmapped, and all open channels are closed.
+ *
+ * @dev:      trusty device, initialized with trusty_dev_init
+ * @buf:      physical address info of shared buffer
+ * @buf_size: size of @buf
+ */
+int trusty_dev_shutdown_ipc(struct trusty_dev *dev,
+                            struct ns_mem_page_info *buf, uint32_t buf_size);
+
+/*
+ * Export Trusty fastcall API
+ */
+int32_t trusty_simple_fast_call32(uint32_t smcnr,
+                                  uint32_t a0, uint32_t a1, uint32_t a2);
+
+#endif /* TRUSTY_TRUSTY_DEV_H_ */
diff --git a/include/trusty/trusty_ipc.h b/include/trusty/trusty_ipc.h
new file mode 100644
index 00000000000..ce7cbd126aa
--- /dev/null
+++ b/include/trusty/trusty_ipc.h
@@ -0,0 +1,258 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef TRUSTY_TRUSTY_IPC_H_
+#define TRUSTY_TRUSTY_IPC_H_
+
+#include <trusty/sysdeps.h>
+
+/*
+ * handle_t is an opaque 32 bit value that is used to reference an
+ * Trusty IPC channel
+ */
+typedef uint32_t handle_t;
+
+#define INVALID_IPC_HANDLE  0
+
+/*
+ * Error codes returned by Trusty IPC device function calls
+ */
+enum trusty_err {
+    TRUSTY_ERR_NONE            =  0,
+    TRUSTY_ERR_GENERIC         = -1,
+    TRUSTY_ERR_NOT_SUPPORTED   = -2,
+    TRUSTY_ERR_NO_MEMORY       = -3,
+    TRUSTY_ERR_INVALID_ARGS    = -4,
+    TRUSTY_ERR_SECOS_ERR       = -5,
+    TRUSTY_ERR_MSG_TOO_BIG     = -6,
+    TRUSTY_ERR_NO_MSG          = -7,
+    TRUSTY_ERR_CHANNEL_CLOSED  = -8,
+    TRUSTY_ERR_SEND_BLOCKED    = -9,
+};
+/*
+ * Return codes for successful Trusty IPC events (failures return trusty_err)
+ */
+enum trusty_event_result {
+    TRUSTY_EVENT_HANDLED   = 1,
+    TRUSTY_EVENT_NONE      = 2
+};
+
+/*
+ * Combination of these values are used for the event field
+ * of trusty_ipc_event structure.
+ */
+enum trusty_ipc_event_type {
+    IPC_HANDLE_POLL_NONE  = 0x0,
+    IPC_HANDLE_POLL_READY = 0x1,
+    IPC_HANDLE_POLL_ERROR = 0x2,
+    IPC_HANDLE_POLL_HUP   = 0x4,
+    IPC_HANDLE_POLL_MSG   = 0x8,
+    IPC_HANDLE_POLL_SEND_UNBLOCKED = 0x10,
+};
+
+struct trusty_dev;
+struct trusty_ipc_chan;
+
+/*
+ * Trusty IPC event
+ *
+ * @event:  event type
+ * @handle: handle this event is related to
+ * @cookie: cookie associated with handle
+ */
+struct trusty_ipc_event {
+    uint32_t event;
+    uint32_t handle;
+    uint64_t cookie;
+};
+
+struct trusty_ipc_iovec {
+    void *base;
+    size_t len;
+};
+
+/*
+ * Trusty IPC device
+ *
+ * @buf_vaddr: virtual address of shared buffer associated with device
+ * @buf_size:  size of shared buffer
+ * @buf_ns:    physical address info of shared buffer
+ * @tdev:      trusty device
+ */
+struct trusty_ipc_dev {
+    void  *buf_vaddr;
+    size_t buf_size;
+    struct ns_mem_page_info buf_ns;
+    struct trusty_dev *tdev;
+};
+
+/*
+ * Trusty IPC event handlers.
+ */
+struct trusty_ipc_ops {
+    int (*on_raw_event)(struct trusty_ipc_chan *chan,
+                        struct trusty_ipc_event *evt);
+    int (*on_connect_complete)(struct trusty_ipc_chan *chan);
+    int (*on_send_unblocked)(struct trusty_ipc_chan *chan);
+    int (*on_message)(struct trusty_ipc_chan *chan);
+    int (*on_disconnect)(struct trusty_ipc_chan *chan);
+};
+
+/*
+ * Trusty IPC channel.
+ *
+ * @ops_ctx:  refers to additional data that may be used by trusty_ipc_ops
+ * @handle:   identifier for channel
+ * @complete: completion status of last event on channel
+ * @dev:      Trusty IPC device used by channel, initialized with
+              trusty_ipc_dev_create
+ * @ops:      callbacks for Trusty events
+ */
+struct trusty_ipc_chan {
+    void *ops_ctx;
+    handle_t handle;
+    volatile int complete;
+    struct trusty_ipc_dev *dev;
+    struct trusty_ipc_ops *ops;
+};
+
+/*
+ * Creates new Trusty IPC device on @tdev. Allocates shared buffer, and calls
+ * trusty_dev_init_ipc to register with secure side. Returns a trusty_err.
+ *
+ * @ipc_dev:  new Trusty IPC device to be initialized
+ * @tdev:     associated Trusty device
+ * @shared_buf_size: size of shared buffer to be allocated
+ */
+int trusty_ipc_dev_create(struct trusty_ipc_dev **ipc_dev,
+                          struct trusty_dev *tdev,
+                          size_t shared_buf_size);
+/*
+ * Shutdown @dev. Frees shared buffer, and calls trusty_dev_shutdown_ipc
+ * to shutdown on the secure side.
+ */
+void trusty_ipc_dev_shutdown(struct trusty_ipc_dev *dev);
+
+/*
+ * Calls into secure OS to initiate a new connection to a Trusty IPC service.
+ * Returns handle for the new channel, a trusty_err on error.
+ *
+ * @dev:    Trusty IPC device initialized with trusty_ipc_dev_create
+ * @port:   name of port to connect to on secure side
+ * @cookie: cookie associated with new channel.
+ */
+int trusty_ipc_dev_connect(struct trusty_ipc_dev *dev, const char *port,
+                           uint64_t cookie);
+/*
+ * Calls into secure OS to close connection to Trusty IPC service.
+ * Returns a trusty_err.
+ *
+ * @dev:  Trusty IPC device
+ * @chan: handle for connection, opened with trusty_ipc_dev_connect
+ */
+int trusty_ipc_dev_close(struct trusty_ipc_dev *dev, handle_t chan);
+
+/*
+ * Calls into secure OS to receive pending event. Returns a trusty_err.
+ *
+ * @dev:   Trusty IPC device
+ * @chan:  handle for connection
+ * @event: pointer to output event struct
+ */
+int trusty_ipc_dev_get_event(struct trusty_ipc_dev *dev, handle_t chan,
+                             struct trusty_ipc_event *event);
+/*
+ * Calls into secure OS to send message to channel. Returns a trusty_err.
+ *
+ * @dev:      Trusty IPC device
+ * @chan:     handle for connection
+ * @iovs:     contains messages to be sent
+ * @iovs_cnt: number of iovecs to be sent
+ */
+int trusty_ipc_dev_send(struct trusty_ipc_dev *dev, handle_t chan,
+                        const struct trusty_ipc_iovec *iovs, size_t iovs_cnt);
+/*
+ * Calls into secure OS to receive message on channel. Returns number of bytes
+ * received on success, trusty_err on failure.
+ *
+ * @dev:      Trusty IPC device
+ * @chan:     handle for connection
+ * @iovs:     contains received messages
+ * @iovs_cnt: number of iovecs received
+ */
+int trusty_ipc_dev_recv(struct trusty_ipc_dev *dev, handle_t chan,
+                        const struct trusty_ipc_iovec *iovs, size_t iovs_cnt);
+
+void trusty_ipc_dev_idle(struct trusty_ipc_dev *dev);
+
+/*
+ * Initializes @chan with default values and @dev.
+ */
+void trusty_ipc_chan_init(struct trusty_ipc_chan *chan,
+                          struct trusty_ipc_dev *dev);
+/*
+ * Calls trusty_ipc_dev_connect to get a handle for channel.
+ * Returns a trusty_err.
+ *
+ * @chan: channel to initialize with new handle
+ * @port: name of port to connect to on secure side
+ * @wait: flag to wait for connect to complete by polling for
+ *        IPC_HANDLE_POLL_READY event
+ */
+int trusty_ipc_connect(struct trusty_ipc_chan *chan, const char *port,
+                       bool wait);
+/*
+ * Calls trusty_ipc_dev_close and invalidates @chan. Returns a trusty_err.
+ */
+int trusty_ipc_close(struct trusty_ipc_chan *chan);
+/*
+ * Calls trusty_ipc_dev_get_event to poll @dev for events. Handles
+ * events by calling appropriate callbacks. Returns nonnegative on success.
+ */
+int trusty_ipc_poll_for_event(struct trusty_ipc_dev *dev);
+/*
+ * Calls trusty_ipc_dev_send to send a message. Returns a trusty_err.
+ *
+ * @chan:     handle for connection
+ * @iovs:     contains messages to be sent
+ * @iovs_cnt: number of iovecs to be sent
+ * @wait:     flag to wait for send to complete
+ */
+int trusty_ipc_send(struct trusty_ipc_chan *chan,
+                    const struct trusty_ipc_iovec *iovs, size_t iovs_cnt,
+                    bool wait);
+/*
+ * Calls trusty_ipc_dev_recv to receive a message. Return number of bytes
+ * received on success, trusty_err on failure.
+ *
+ * @chan:     handle for connection
+ * @iovs:     contains received messages
+ * @iovs_cnt: number of iovecs received
+ * @wait:     flag to wait for a message to receive
+ */
+int trusty_ipc_recv(struct trusty_ipc_chan *chan,
+                    const struct trusty_ipc_iovec *iovs, size_t iovs_cnt,
+                    bool wait);
+
+#endif /* TRUSTY_TRUSTY_IPC_H_ */
diff --git a/include/trusty/trusty_mem.h b/include/trusty/trusty_mem.h
new file mode 100644
index 00000000000..c796baa03f4
--- /dev/null
+++ b/include/trusty/trusty_mem.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2018 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef TRUSTY_TRUSTY_MEM_H_
+#define TRUSTY_TRUSTY_MEM_H_
+
+#include <trusty/sysdeps.h>
+
+/*
+ * Encodes the memory attributes of @va into @inf
+ *
+ * @inf:    ns_mem_page_info allocated by the caller
+ * @va:     virtual addresses to retrieve attributes for
+ *
+ * Returns 0 on success and -1 on failure
+ */
+
+int trusty_encode_page_info(struct ns_mem_page_info *inf, void *va);
+
+#endif /* TRUSTY_TRUSTY_MEM_H_ */
diff --git a/include/trusty/util.h b/include/trusty/util.h
new file mode 100644
index 00000000000..fff81c183ef
--- /dev/null
+++ b/include/trusty/util.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef TRUSTY_UTIL_H_
+#define TRUSTY_UTIL_H_
+
+#include <trusty/sysdeps.h>
+
+/* Returns the basename of |str|. This is defined as the last path
+ * component, assuming the normal POSIX separator '/'. If there are no
+ * separators, returns |str|.
+ */
+const char* trusty_basename(const char* str);
+
+#define TRUSTY_STRINGIFY(x) #x
+#define TRUSTY_TO_STRING(x) TRUSTY_STRINGIFY(x)
+
+/*
+ * Aborts the program if @expr is false.
+ *
+ * This has no effect unless TIPC_ENABLE_DEBUG is defined.
+ */
+#ifdef TIPC_ENABLE_DEBUG
+#define trusty_assert(expr)                     \
+  do {                                          \
+    if (!(expr)) {                              \
+      trusty_fatal("assert fail: " #expr "\n"); \
+    }                                           \
+  } while(0)
+#else
+#define trusty_assert(expr)
+#endif
+
+/*
+ * Prints debug message.
+ *
+ * This has no effect unless TIPC_ENABLE_DEBUG and LOCAL_LOG is defined.
+ */
+#ifdef TIPC_ENABLE_DEBUG
+#define trusty_debug(message, ...)                              \
+  do {                                                          \
+    if (LOCAL_LOG) {                                            \
+      trusty_printf(trusty_basename(__FILE__));                 \
+      trusty_printf(":" TRUSTY_TO_STRING(__LINE__) ": DEBUG "); \
+      trusty_printf(message, ##__VA_ARGS__);                    \
+    }                                                           \
+  } while(0)
+#else
+#define trusty_debug(message, ...)
+#endif
+
+/*
+ * Prints info message.
+ */
+#define trusty_info(message, ...)             \
+  do {                                        \
+    trusty_printf("INFO ");                 \
+    trusty_printf(message, ##__VA_ARGS__);    \
+  } while(0)
+
+/*
+ * Prints error message.
+ */
+#define trusty_error(message, ...)                            \
+  do {                                                        \
+    trusty_printf(trusty_basename(__FILE__));                 \
+    trusty_printf(":" TRUSTY_TO_STRING(__LINE__) ": ERROR "); \
+    trusty_printf(message, ##__VA_ARGS__);                    \
+  } while(0)
+
+/*
+ * Prints message and calls trusty_abort.
+ */
+#define trusty_fatal(message, ...)                             \
+  do {                                                         \
+    trusty_printf(trusty_basename(__FILE__));                  \
+    trusty_printf(":" TRUSTY_TO_STRING(__LINE__) ": FATAL ");  \
+    trusty_printf(message, ##__VA_ARGS__);                     \
+    trusty_abort();                                            \
+  } while(0)
+
+#endif /* TRUSTY_UTIL_H_ */
diff --git a/include/u-boot/rsa.h b/include/u-boot/rsa.h
index b9634e38d9a..d1a25248e16 100644
--- a/include/u-boot/rsa.h
+++ b/include/u-boot/rsa.h
@@ -110,12 +110,13 @@ int padding_pss_verify(struct image_sign_info *info,
 
 #define RSA_DEFAULT_PADDING_NAME		"pkcs-1.5"
 
+#define RSA1024_BYTES	(1024 / 8)
 #define RSA2048_BYTES	(2048 / 8)
 #define RSA3072_BYTES	(3072 / 8)
 #define RSA4096_BYTES	(4096 / 8)
 
 /* This is the minimum/maximum key size we support, in bits */
-#define RSA_MIN_KEY_BITS	2048
+#define RSA_MIN_KEY_BITS	1024
 #define RSA_MAX_KEY_BITS	4096
 
 /* This is the maximum signature length that we support, in bits */
diff --git a/include/u-boot/sha256.h b/include/u-boot/sha256.h
index 9aa1251789a..6fbf542f671 100644
--- a/include/u-boot/sha256.h
+++ b/include/u-boot/sha256.h
@@ -22,4 +22,7 @@ void sha256_finish(sha256_context * ctx, uint8_t digest[SHA256_SUM_LEN]);
 void sha256_csum_wd(const unsigned char *input, unsigned int ilen,
 		unsigned char *output, unsigned int chunk_sz);
 
+void sha256_hmac(const unsigned char *key, int keylen,
+		const unsigned char *input, unsigned int ilen,
+		unsigned char *output);
 #endif /* _SHA256_H */
diff --git a/include/usb/ci_udc.h b/include/usb/ci_udc.h
index 06adb2bb4d3..1ed74a27cbc 100644
--- a/include/usb/ci_udc.h
+++ b/include/usb/ci_udc.h
@@ -7,7 +7,12 @@
 
 #ifndef __CI_UDC_H__
 #define __CI_UDC_H__
+#include <usb/ehci-ci.h>
+#include <usb/usb_mx6_common.h>
 
 #define EP_MAX_PACKET_SIZE	0x200
 #define EP0_MAX_PACKET_SIZE	64
+
+bool ci_udc_check_bus_active(ulong ehci_addr, struct ehci_mx6_phy_data *phy_data, int index);
+
 #endif /* __CI_UDC_H__ */
diff --git a/include/usb/usb_mx6_common.h b/include/usb/usb_mx6_common.h
new file mode 100644
index 00000000000..1d8029ab95f
--- /dev/null
+++ b/include/usb/usb_mx6_common.h
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *
+ */
+
+#ifndef __USB_MX6_COMMON_H__
+#define __USB_MX6_COMMON_H__
+#include <usb/ehci-ci.h>
+
+struct ehci_mx6_phy_data {
+	void __iomem *phy_addr;
+	void __iomem *misc_addr;
+	void __iomem *anatop_addr;
+};
+
+void ehci_mx6_phy_init(struct usb_ehci *ehci, struct ehci_mx6_phy_data *phy_data, int index);
+#endif /* __USB_MX6_COMMON_H__ */
diff --git a/include/video_bridge.h b/include/video_bridge.h
index 3b429eac578..8b71b04a111 100644
--- a/include/video_bridge.h
+++ b/include/video_bridge.h
@@ -45,6 +45,17 @@ struct video_bridge_ops {
 	int (*check_attached)(struct udevice *dev);
 
 	/**
+	 * check_timing() - check if the timing need update after the bridge device attached
+	 *
+	 * This method is optional - if not provided then return 0
+	 *
+	 * @dev:	Device to check
+	 * @active:	The timing to be checked and updated
+	 * Return: 0 if OK, -ve on error
+	 */
+	int (*check_timing)(struct udevice *dev, struct display_timing *timing);
+
+	/**
 	 * set_backlight() - Set the backlight brightness
 	 *
 	 * @dev:	device to adjust
@@ -99,6 +110,15 @@ int video_bridge_set_active(struct udevice *dev, bool active);
 int video_bridge_check_attached(struct udevice *dev);
 
 /**
+ * check_timing() - check if the timing need update after the bridge device attached
+ *
+ * @dev:	Device to check
+ * @active:	The timing to be checked and updated
+ * Return: 0 if OK, -ve on error
+ */
+int video_bridge_check_timing(struct udevice *dev, struct display_timing *timing);
+
+/**
  * video_bridge_read_edid() - Read information from EDID
  *
  * @dev:	Device to read from
diff --git a/include/video_link.h b/include/video_link.h
new file mode 100644
index 00000000000..5350bfa9e9d
--- /dev/null
+++ b/include/video_link.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 NXP
+ */
+
+#ifndef __VIDEO_LINK
+#define __VIDEO_LINK
+
+int video_link_init(void);
+
+int video_link_shut_down(void);
+
+struct udevice *video_link_get_next_device(struct udevice *curr_dev);
+
+struct udevice *video_link_get_video_device(void);
+
+int video_link_get_display_timings(struct display_timing *timings);
+
+#endif
diff --git a/include/xen/interface/xen.h b/include/xen/interface/xen.h
index eec8ab75b9c..ada2e59e2a5 100644
--- a/include/xen/interface/xen.h
+++ b/include/xen/interface/xen.h
@@ -76,6 +76,9 @@
 #define __HYPERVISOR_arch_6               54
 #define __HYPERVISOR_arch_7               55
 
+#define CONSOLEIO_write         0
+#define CONSOLEIO_read          1
+
 #ifndef __ASSEMBLY__
 
 typedef u16 domid_t;
diff --git a/lib/Kconfig b/lib/Kconfig
index 3c6fa99b1a6..acd3d51bc96 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -384,6 +384,38 @@ config LIBAVB
 	  device. Introduces such features as boot chain of trust, rollback
 	  protection etc.
 
+config AVB_SUPPORT
+	bool "Enable Android AVB lib support"
+	select LIBAVB
+
+config AVB_ATX
+	bool "Enable AVB_ATX support"
+	depends on AVB_SUPPORT
+
+config AVB_WARNING_LOGO
+	bool "Enable avb warning show logo on screen"
+	help
+	  Enable avb warning show logo on screen
+
+config AVB_WARNING_LOGO_COLS
+	hex "x resolution on the screen"
+	default 0x1E0
+	depends on AVB_WARNING_LOGO
+	help
+	  The x resolution on the screen.
+
+config AVB_WARNING_LOGO_ROWS
+	hex "y resolution on the screen"
+	default 0x60
+	depends on AVB_WARNING_LOGO
+	help
+	  The y resolution on the screen.
+
+config AVB_WARNING_TIME_LAST
+	hex "the time of avb warning logo will last"
+	default 0x3
+	help
+	  The time of avb warning logo will last (s).
 endmenu
 
 menu "Hashing Support"
diff --git a/lib/Makefile b/lib/Makefile
index 11b03d1cbec..632dcba8695 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_ARCH_AT91) += at91/
 obj-$(CONFIG_OPTEE_LIB) += optee/
 obj-$(CONFIG_ASN1_DECODER) += asn1_decoder.o
 obj-y += crypto/
+obj-$(CONFIG_IMX_TRUSTY_OS) += trusty/ql-tipc/
 
 obj-$(CONFIG_AES) += aes.o
 obj-$(CONFIG_AES) += aes/
@@ -85,6 +86,7 @@ obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o
 obj-$(CONFIG_$(SPL_)LIB_RATIONAL) += rational.o
 
 obj-$(CONFIG_LIBAVB) += libavb/
+obj-$(CONFIG_AVB_SUPPORT) += avb/
 
 obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/
 obj-$(CONFIG_$(SPL_TPL_)OF_REAL) += fdtdec_common.o fdtdec.o
diff --git a/lib/avb/Makefile b/lib/avb/Makefile
new file mode 100644
index 00000000000..6841faf8553
--- /dev/null
+++ b/lib/avb/Makefile
@@ -0,0 +1,18 @@
+subdir-ccflags-y += -I./lib \
+			-D_FILE_OFFSET_BITS=64 \
+			-D_POSIX_C_SOURCE=199309L \
+			-Wa,--noexecstack \
+			-Wall \
+			-Wextra \
+			-Wformat=2 \
+			-Wno-type-limits \
+			-Wno-psabi \
+			-Wno-unused-parameter \
+			-Wno-sign-compare \
+			-ffunction-sections \
+			-std=gnu99
+
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_AVB_ATX) += libavb_atx/
+endif
+obj-y += fsl/
diff --git a/lib/avb/fsl/Makefile b/lib/avb/fsl/Makefile
new file mode 100644
index 00000000000..eb641d4b41d
--- /dev/null
+++ b/lib/avb/fsl/Makefile
@@ -0,0 +1,9 @@
+ifndef CONFIG_SPL_BUILD
+obj-y += fsl_avb.o
+endif
+
+obj-y += fsl_avbkey.o
+obj-y += utils.o
+obj-y += fsl_bootctrl.o
+obj-$(CONFIG_AVB_ATX) += fsl_atx_attributes.o
+obj-$(CONFIG_AVB_WARNING_LOGO) += orange_warning_bmp_data.o
diff --git a/lib/avb/fsl/debug.h b/lib/avb/fsl/debug.h
new file mode 100644
index 00000000000..c1165ec1ec1
--- /dev/null
+++ b/lib/avb/fsl/debug.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __AVB_DEBUG_H__
+#define __AVB_DEBUG_H__
+
+#ifdef AVB_VVDEBUG
+#define AVB_VDEBUG
+#define VVDEBUG(format, ...) printf(" %s: "format, __func__, ##__VA_ARGS__)
+#else
+#define VVDEBUG(format, ...)
+#endif
+
+#ifdef AVB_VDEBUG
+#define AVB_DEBUG
+#define VDEBUG(format, ...) printf(" %s: "format, __func__, ##__VA_ARGS__)
+#else
+#define VDEBUG(format, ...)
+#endif
+
+#ifdef AVB_DEBUG
+#define DEBUGAVB(format, ...) printf(" %s: "format, __func__, ##__VA_ARGS__)
+#else
+#define DEBUGAVB(format, ...)
+#endif
+
+#define ERR(format, ...) printf("%s: "format, __func__, ##__VA_ARGS__)
+
+#define HEXDUMP_COLS 16
+#define HEXDUMP_WIDTH 1
+
+#endif
diff --git a/lib/avb/fsl/fsl_atx_attributes.c b/lib/avb/fsl/fsl_atx_attributes.c
new file mode 100644
index 00000000000..2297140dd17
--- /dev/null
+++ b/lib/avb/fsl/fsl_atx_attributes.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* This product_id is generated from
+ * extern/avb/test/data/atx_product_id.bin */
+unsigned char fsl_atx_product_id[16] = {
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+};
+/* This product_root_public_key is generated form
+ * extern/avb/test/data/testkey_atx_prk.pem */
+unsigned char fsl_product_root_public_key[1032] = {
+	0x00,0x00,0x10,0x00,0x9f,0x35,0xef,0x65,
+	0xc3,0x29,0x4c,0x23,0x16,0x10,0xac,0x32,
+	0xc1,0x3c,0xd5,0xc5,0xab,0xa1,0xd9,0xe7,
+	0x13,0x3f,0x7e,0xd1,0xe6,0x61,0x5d,0xa3,
+	0xa1,0x60,0xda,0x57,0x4b,0xb2,0xe6,0x0f,
+	0xe1,0x50,0xbf,0x47,0xff,0x09,0xaf,0xcd,
+	0x49,0x2d,0x82,0x33,0x76,0xa1,0xfe,0x28,
+	0x5f,0x89,0x62,0xb3,0xc0,0xf1,0x11,0xaf,
+	0x15,0x09,0x27,0xdb,0xeb,0x06,0x01,0xa2,
+	0xf8,0xb7,0xd7,0x9c,0xe4,0x88,0x3a,0x86,
+	0x05,0x02,0x20,0x69,0xb2,0x36,0x4c,0x3e,
+	0x25,0x03,0xed,0xfc,0x0c,0x6b,0x1b,0x0a,
+	0x04,0x9c,0xce,0x7f,0x83,0x82,0x60,0xd9,
+	0x52,0x7e,0xc4,0x35,0x7b,0x1c,0xe6,0x64,
+	0x9c,0x17,0xec,0x81,0xe7,0x9c,0x0c,0x8b,
+	0x4b,0x7e,0x48,0xbe,0x00,0x98,0xa8,0x20,
+	0x10,0x4c,0x9b,0xd1,0x16,0x5b,0x25,0xe9,
+	0x4e,0x61,0xda,0x7c,0x63,0x80,0x8f,0xa4,
+	0xac,0x74,0xee,0xa8,0x06,0xac,0x26,0xd5,
+	0x71,0x6f,0xaa,0x73,0x20,0x9c,0x7f,0xcd,
+	0x73,0xd4,0xa9,0xa0,0x7e,0x5a,0xb5,0x61,
+	0xb0,0x88,0xb0,0xdd,0xdb,0x6b,0x79,0xd1,
+	0x5a,0x9e,0x54,0x49,0x55,0xc6,0x89,0x76,
+	0x7a,0xc6,0x78,0x99,0xdc,0xc9,0x00,0x5d,
+	0x20,0xf5,0xfc,0x8f,0x39,0x46,0xf3,0x02,
+	0x96,0x0d,0x9b,0xfb,0xbc,0xd5,0xcf,0x5a,
+	0x4f,0xc4,0xb8,0x0b,0xd0,0xf3,0x19,0x3c,
+	0x74,0x04,0xd5,0x94,0x2c,0x19,0x15,0x64,
+	0xbf,0x53,0x67,0x97,0x7b,0x9e,0xc6,0xe0,
+	0xfb,0x29,0x5b,0x90,0xad,0x04,0x8a,0xd8,
+	0x5b,0xdf,0x69,0x09,0xe4,0xa5,0xe9,0xd9,
+	0x0f,0xc4,0xff,0xae,0xb7,0x44,0x12,0xae,
+	0xad,0x03,0x97,0xb8,0xda,0xd7,0x60,0x37,
+	0x15,0xf2,0xb9,0xdb,0x10,0xf6,0xe2,0x26,
+	0x48,0x7e,0x3e,0x3e,0xc3,0x67,0xd3,0xa6,
+	0x02,0xf7,0xbc,0x60,0xed,0x45,0xdf,0x37,
+	0xef,0xf9,0xea,0x97,0x5f,0x37,0xb4,0xeb,
+	0xb4,0x91,0x6c,0x39,0x4d,0xed,0x52,0x15,
+	0x39,0x47,0x59,0x62,0xde,0x32,0x55,0xe1,
+	0xd4,0x15,0x58,0x7d,0x52,0x41,0x12,0x78,
+	0xee,0x9f,0x0d,0xc8,0x5e,0x34,0x91,0xf9,
+	0xe7,0x4c,0x1e,0xe7,0x2f,0x90,0x7f,0xbb,
+	0xf8,0x99,0x3e,0xc9,0x79,0xab,0x01,0xdb,
+	0x24,0x39,0xe3,0xb4,0xc9,0x52,0x73,0xdb,
+	0x65,0x42,0xa5,0x2e,0x43,0x56,0xa0,0x33,
+	0x8c,0x1a,0xb7,0xa1,0xed,0x5c,0xd0,0x14,
+	0x93,0x8d,0x23,0x78,0x93,0xcb,0x3a,0x03,
+	0x1f,0xbb,0xc6,0x7b,0xcd,0x51,0x4e,0xaa,
+	0x14,0x01,0xe9,0x03,0x27,0x13,0xe2,0xb2,
+	0xf8,0x36,0xc6,0xe3,0xc3,0x7f,0xb5,0x74,
+	0x20,0x5e,0x17,0xaa,0x25,0x07,0x9b,0x60,
+	0xda,0x83,0x98,0xb5,0x55,0xae,0x1b,0x7a,
+	0xc1,0x1f,0x49,0x72,0xe2,0xcb,0x6a,0x11,
+	0x77,0xdf,0x3f,0xc0,0x9f,0x8f,0x33,0xc7,
+	0x10,0x17,0x8c,0xfc,0xd5,0xb7,0x5f,0x5e,
+	0xb2,0xe3,0x7b,0x2e,0xdc,0xc7,0x34,0xdb,
+	0x31,0xb0,0xdc,0x5d,0x14,0x98,0xb6,0x1a,
+	0x2a,0xd4,0xb4,0x04,0x2c,0xf0,0x68,0x1c,
+	0x91,0x60,0x28,0xa5,0x3b,0x01,0x98,0xb6,
+	0x1e,0x6e,0xaa,0x35,0x89,0xc7,0x94,0xaa,
+	0x9e,0xf0,0x11,0x52,0x0f,0x28,0xa1,0x3d,
+	0xd3,0x17,0xb5,0x08,0xd8,0x7a,0x41,0xf9,
+	0x07,0xe2,0x87,0x36,0xcd,0x86,0x3e,0x79,
+	0x99,0x73,0x50,0x21,0x30,0x00,0xd2,0xf3,
+	0x88,0x60,0x32,0x59,0x58,0x2f,0x55,0x93,
+	0x86,0x56,0x9a,0x96,0xb9,0xf8,0xbf,0x24,
+	0xc4,0xba,0xea,0xa4,0x73,0xb0,0x0c,0xa6,
+	0xdb,0x09,0x2d,0x0a,0x36,0x3f,0x80,0xe6,
+	0x85,0x7a,0xf3,0x01,0x90,0x3a,0xc6,0xee,
+	0x2d,0xa8,0xce,0xb4,0x3f,0x3a,0xa6,0xa3,
+	0xaf,0xb9,0x21,0xef,0x40,0x6f,0xf4,0x7f,
+	0x78,0x25,0x55,0x39,0x53,0x67,0x53,0x56,
+	0x8d,0x81,0xaf,0x63,0x97,0x68,0x86,0x75,
+	0x66,0x14,0x1e,0xa6,0x63,0x1e,0x02,0xd0,
+	0x41,0xd8,0x78,0x75,0x0d,0x76,0x77,0xfa,
+	0x9c,0xc5,0xcc,0x54,0x06,0x25,0x53,0x95,
+	0xeb,0x4b,0x7c,0xb4,0xc8,0xbb,0x5d,0x6b,
+	0x6e,0xf0,0xd7,0x8d,0x3f,0xdf,0x93,0x4c,
+	0x30,0x5b,0x02,0xf5,0x0e,0x49,0x87,0x60,
+	0x5f,0x19,0x06,0x24,0x3d,0x5d,0x97,0x37,
+	0x61,0xef,0x3e,0x0b,0x9e,0x85,0x1c,0x1a,
+	0xa6,0x53,0x91,0xd2,0x2c,0x18,0x7c,0x8f,
+	0x5b,0x4a,0xd5,0xdd,0xd9,0x8a,0xc3,0x92,
+	0x19,0x54,0x39,0xde,0x33,0xa1,0xe1,0x37,
+	0x60,0x3c,0x3b,0x3b,0xc5,0xed,0x1b,0xef,
+	0x28,0xf5,0xdf,0x44,0x91,0xa3,0x1e,0x69,
+	0x6a,0x35,0x85,0x6e,0x26,0x46,0x22,0x4d,
+	0x87,0x92,0x44,0x6b,0x96,0xdb,0x75,0xfe,
+	0x76,0x03,0x60,0xf7,0xfd,0x90,0x55,0x7d,
+	0x6e,0xd7,0xaa,0x44,0x05,0xc7,0x23,0x37,
+	0x12,0xa8,0xd4,0xb2,0x2b,0xed,0x41,0x5f,
+	0x23,0x38,0x7c,0x16,0xe6,0x16,0xd3,0x10,
+	0x19,0x12,0xcc,0x8b,0x6e,0xcd,0xd6,0xa6,
+	0x39,0x8a,0x1b,0x24,0x3f,0x4d,0x6f,0xa6,
+	0x00,0x7c,0xa0,0xa1,0x4a,0xfd,0xcd,0x68,
+	0x50,0x76,0xc8,0x68,0x9d,0xeb,0xdf,0x24,
+	0x39,0xaf,0x77,0xb2,0xb6,0xaf,0xb6,0x34,
+	0x61,0x37,0x6a,0xfd,0xc7,0x6d,0x02,0x9f,
+	0x29,0xd5,0x45,0xf4,0x89,0xd8,0x8c,0x5c,
+	0xd3,0x31,0xa0,0x58,0x19,0x54,0x33,0x46,
+	0x92,0xbc,0x1e,0x4b,0x14,0xac,0x73,0xa5,
+	0x09,0x9f,0xb6,0x2b,0x2b,0x73,0x6b,0x83,
+	0x86,0x13,0x6e,0x03,0xf7,0xe0,0x7d,0x81,
+	0x47,0x18,0x08,0xea,0x09,0x10,0x24,0x61,
+	0x6d,0x09,0x1d,0xb8,0x8e,0xba,0x04,0x4d,
+	0xcc,0xe6,0xff,0x28,0x27,0x86,0x38,0x01,
+	0x86,0xbe,0xf0,0x5b,0xf8,0x1a,0xd6,0xde,
+	0xbe,0xf9,0x3b,0x76,0x3f,0x85,0x82,0x22,
+	0x92,0x4b,0xe0,0x76,0x15,0xb2,0x57,0x5a,
+	0xb0,0x64,0xde,0xce,0x93,0xb8,0x9f,0x25,
+	0x53,0x8c,0x5e,0xdf,0x29,0x4e,0x50,0x69,
+	0xfb,0x7e,0x33,0xcb,0x0e,0x28,0x01,0x6c,
+	0xab,0xfa,0xd8,0x88,0x02,0xbc,0xf2,0xb1,
+	0x0e,0x2f,0x6d,0x1c,0x8d,0xe4,0x11,0x23,
+	0xcc,0x67,0x94,0x7b,0xf7,0x8a,0xf3,0x68,
+	0x52,0xe4,0x82,0x25,0x86,0xc6,0x72,0x19,
+	0x77,0x80,0x28,0xe3,0x86,0xc8,0x8a,0xea,
+	0x3d,0x54,0x2f,0x0b,0x64,0x0a,0xc5,0x12,
+	0x8c,0xb2,0x07,0x72,0x1b,0x09,0x9f,0x32,
+	0xbd,0xa3,0xb0,0x0c,0x95,0xc8,0x4d,0xe5,
+	0xd7,0x20,0xdb,0xf8,0x34,0x2a,0x9d,0x91,
+	0x58,0x38,0x7a,0x9c,0xe0,0xa3,0x0f,0x40,
+	0x9d,0xff,0xeb,0x4b,0xe2,0x16,0x94,0x32,
+	0xce,0xe8,0x52,0x75,0x49,0xf4,0x71,0x13,
+	0xbc,0x59,0x7d,0x9a,0xe8,0x60,0x29,0x58,
+	0x1a,0x14,0x94,0xe6,0x37,0x23,0xad,0xfe,
+	0x0b,0xf0,0x63,0x60,0x4f,0x5d,0x10,0x91,
+	0xf2,0x50,0x8e,0x0b,0x4a,0x47,0xc9,0x0c,
+	0x1f,0xdc,0x94,0x75,0x25,0x52,0x99,0xfc
+};
diff --git a/lib/avb/fsl/fsl_atx_attributes.h b/lib/avb/fsl/fsl_atx_attributes.h
new file mode 100644
index 00000000000..e6e43835a1e
--- /dev/null
+++ b/lib/avb/fsl/fsl_atx_attributes.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __FSL_ATX_ATTRIBUTES_H__
+#define __FSL_ATX_ATTRIBUTES_H__
+
+#define fsl_version 1
+/* This product_id is generated from
+ * extern/avb/test/data/atx_product_id.bin */
+extern unsigned char fsl_atx_product_id[17];
+/* This product_root_public_key is generated form
+ * extern/avb/test/data/testkey_atx_prk.pem */
+extern unsigned char fsl_product_root_public_key[1032];
+
+#endif /* __FSL_ATX_ATTRIBUTES_H__ */
diff --git a/lib/avb/fsl/fsl_avb.c b/lib/avb/fsl/fsl_avb.c
new file mode 100644
index 00000000000..f4797f1eea0
--- /dev/null
+++ b/lib/avb/fsl/fsl_avb.c
@@ -0,0 +1,844 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <part.h>
+#include <stdlib.h>
+
+#include <fb_fsl.h>
+#include "../../../drivers/fastboot/fb_fsl/fastboot_lock_unlock.h"
+
+#include <fsl_avb.h>
+#include "fsl_avbkey.h"
+#include "utils.h"
+#include "debug.h"
+#include "trusty/avb.h"
+#ifndef CONFIG_LOAD_KEY_FROM_RPMB
+#include "fsl_public_key.h"
+#endif
+#include "fsl_atx_attributes.h"
+
+#define FSL_AVB_DEV "mmc"
+#define AVB_MAX_BUFFER_LENGTH 2048
+
+static struct blk_desc *fs_dev_desc = NULL;
+static struct blk_desc *get_mmc_desc(void) {
+	extern int mmc_get_env_dev(void);
+	int dev_no = mmc_get_env_dev();
+	return blk_get_dev(FSL_AVB_DEV, dev_no);
+}
+
+ /* Reads |num_bytes| from offset |offset| from partition with name
+  * |partition| (NUL-terminated UTF-8 string). If |offset| is
+  * negative, its absolute value should be interpreted as the number
+  * of bytes from the end of the partition.
+  *
+  * This function returns AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION if
+  * there is no partition with the given name,
+  * AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION if the requested
+  * |offset| is outside the partition, and AVB_IO_RESULT_ERROR_IO if
+  * there was an I/O error from the underlying I/O subsystem.  If the
+  * operation succeeds as requested AVB_IO_RESULT_OK is returned and
+  * the data is available in |buffer|.
+  *
+  * The only time partial I/O may occur is if reading beyond the end
+  * of the partition. In this case the value returned in
+  * |out_num_read| may be smaller than |num_bytes|.
+  */
+ AvbIOResult fsl_read_from_partition(AvbOps* ops, const char* partition,
+				     int64_t offset, size_t num_bytes,
+				     void* buffer, size_t* out_num_read)
+{
+	struct fastboot_ptentry *pte;
+	unsigned char *bdata;
+	unsigned char *out_buf = (unsigned char *)buffer;
+	unsigned long blksz;
+	unsigned long s, cnt;
+	size_t num_read = 0;
+	lbaint_t part_start, part_end, bs, be;
+	margin_pos_t margin;
+
+	AvbIOResult ret;
+
+	DEBUGAVB("[%s]: offset=%ld, num_bytes=%zu\n", partition, (long)offset, num_bytes);
+
+	assert(buffer != NULL && out_num_read != NULL);
+
+	if ((fs_dev_desc = get_mmc_desc()) == NULL) {
+		ERR("mmc device not found\n");
+		return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
+	}
+
+	pte = fastboot_flash_find_ptn(partition);
+	if (!pte) {
+		ERR("no %s partition\n", partition);
+		fastboot_flash_dump_ptn();
+		return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
+	}
+
+	blksz = fs_dev_desc->blksz;
+	part_start = pte->start;
+	part_end = pte->start + pte->length - 1;
+	VDEBUG("blksz: %ld, part_end: %ld, part_start: %ld:\n",
+			blksz, part_end, part_start);
+
+	if(get_margin_pos((uint64_t)part_start, (uint64_t)part_end, blksz,
+				&margin, offset, num_bytes, true))
+		return AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION;
+
+	bs = (lbaint_t)margin.blk_start;
+	be = (lbaint_t)margin.blk_end;
+	s = margin.start;
+
+	// alloc a blksz mem
+	bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz);
+	if (bdata == NULL)
+		return AVB_IO_RESULT_ERROR_OOM;
+
+	// one block a time
+	while (bs <= be) {
+		memset(bdata, 0, blksz);
+		if (blk_dread(fs_dev_desc, bs, 1, bdata) != 1) {
+			ret = AVB_IO_RESULT_ERROR_IO;
+			goto fail;
+		}
+		cnt = blksz - s;
+		if (num_read + cnt > num_bytes)
+			cnt = num_bytes - num_read;
+		VDEBUG("cur: bs=%ld, start=%ld, cnt=%ld bdata=0x%08x\n",
+				bs, s, cnt, bdata);
+		memcpy(out_buf, bdata + s, cnt);
+		bs++;
+		num_read += cnt;
+		out_buf += cnt;
+		s = 0;
+	}
+	*out_num_read = num_read;
+	ret = AVB_IO_RESULT_OK;
+#ifdef AVB_VVDEBUG
+	printf("\nnum_read=%zu", num_read);
+	printf("\n----dump---\n");
+	print_buffer(0, buffer, HEXDUMP_WIDTH, num_read, 0);
+	printf("--- end ---\n");
+#endif
+
+fail:
+	free(bdata);
+	return ret;
+}
+
+/* multi block read version of read_from_partition */
+ AvbIOResult fsl_read_from_partition_multi(AvbOps* ops, const char* partition,
+					   int64_t offset, size_t num_bytes,
+					   void* buffer, size_t* out_num_read)
+{
+	struct fastboot_ptentry *pte;
+	unsigned char *bdata;
+	unsigned char *out_buf = (unsigned char *)buffer;
+	unsigned char *dst, *dst64 = NULL;
+	unsigned long blksz;
+	unsigned long s, cnt;
+	size_t num_read = 0;
+	lbaint_t part_start, part_end, bs, be, bm, blk_num;
+	margin_pos_t margin;
+
+	AvbIOResult ret;
+
+	DEBUGAVB("[%s]: offset=%ld, num_bytes=%zu\n", partition, (long)offset, num_bytes);
+
+	assert(buffer != NULL && out_num_read != NULL);
+
+	if ((fs_dev_desc = get_mmc_desc()) == NULL) {
+		ERR("mmc device not found\n");
+		return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
+	}
+
+	pte = fastboot_flash_find_ptn(partition);
+	if (!pte) {
+		ERR("no %s partition\n", partition);
+		fastboot_flash_dump_ptn();
+		return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
+	}
+
+	blksz = fs_dev_desc->blksz;
+	part_start = pte->start;
+	part_end = pte->start + pte->length - 1;
+	VDEBUG("blksz: %ld, part_end: %ld, part_start: %ld:\n",
+			blksz, part_end, part_start);
+
+	if(get_margin_pos((uint64_t)part_start, (uint64_t)part_end, blksz,
+				&margin, offset, num_bytes, true))
+		return AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION;
+
+	bs = (lbaint_t)margin.blk_start;
+	be = (lbaint_t)margin.blk_end;
+	s = margin.start;
+	bm = margin.multi;
+
+	// alloc a blksz mem
+	bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz);
+	if (bdata == NULL)
+		return AVB_IO_RESULT_ERROR_OOM;
+
+	// support multi blk read
+	while (bs <= be) {
+		if (!s && bm > 1) {
+			dst = out_buf;
+			dst64 = PTR_ALIGN(out_buf, 64); //for mmc blk read alignment
+			VDEBUG("cur: dst=0x%08x, dst64=0x%08x\n", dst, dst64);
+			if (dst64 != dst) {
+				dst = dst64;
+				bm--;
+			}
+			blk_num = bm;
+			cnt = bm * blksz;
+			bm = 0; //no more multi blk
+		} else {
+			blk_num = 1;
+			cnt = blksz - s;
+			if (num_read + cnt > num_bytes)
+				cnt = num_bytes - num_read;
+			dst = bdata;
+		}
+		VDEBUG("cur: bs=%ld, num=%ld, start=%ld, cnt=%ld dst=0x%08x\n",
+				bs, blk_num, s, cnt, dst);
+		if (blk_dread(fs_dev_desc, bs, blk_num, dst) != blk_num) {
+			ret = AVB_IO_RESULT_ERROR_IO;
+			goto fail;
+		}
+
+		if (dst == bdata)
+			memcpy(out_buf, bdata + s, cnt);
+		else if (dst == dst64)
+			memcpy(out_buf, dst, cnt); //internal copy
+
+		s = 0;
+		bs += blk_num;
+		num_read += cnt;
+		out_buf += cnt;
+#ifdef AVB_VVDEBUG
+		printf("\nnum_read=%ld", cnt);
+		printf("\n----dump---\n");
+		print_buffer(0, buffer, HEXDUMP_WIDTH, cnt, 0);
+		printf("--- end ---\n");
+#endif
+	}
+	*out_num_read = num_read;
+	ret = AVB_IO_RESULT_OK;
+#ifdef AVB_VVDEBUG
+	printf("\nnum_read=%zu", num_read);
+	printf("\n----dump---\n");
+	print_buffer(0, buffer, HEXDUMP_WIDTH, num_read, 0);
+	printf("--- end ---\n");
+#endif
+
+fail:
+	free(bdata);
+	return ret;
+}
+
+ /* Writes |num_bytes| from |bffer| at offset |offset| to partition
+  * with name |partition| (NUL-terminated UTF-8 string). If |offset|
+  * is negative, its absolute value should be interpreted as the
+  * number of bytes from the end of the partition.
+  *
+  * This function returns AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION if
+  * there is no partition with the given name,
+  * AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION if the requested
+  * byterange goes outside the partition, and AVB_IO_RESULT_ERROR_IO
+  * if there was an I/O error from the underlying I/O subsystem.  If
+  * the operation succeeds as requested AVB_IO_RESULT_OK is
+  * returned.
+  *
+  * This function never does any partial I/O, it either transfers all
+  * of the requested bytes or returns an error.
+  */
+ AvbIOResult fsl_write_to_partition(AvbOps* ops, const char* partition,
+				    int64_t offset, size_t num_bytes,
+				    const void* buffer)
+{
+	struct fastboot_ptentry *pte;
+	unsigned char *bdata;
+	unsigned char *in_buf = (unsigned char *)buffer;
+	unsigned long blksz;
+	unsigned long s, cnt;
+	size_t num_write = 0;
+	lbaint_t part_start, part_end, bs;
+	margin_pos_t margin;
+
+	AvbIOResult ret;
+
+	DEBUGAVB("[%s]: offset=%ld, num_bytes=%zu\n", partition, (long)offset, num_bytes);
+
+	assert(buffer != NULL);
+
+	if ((fs_dev_desc = get_mmc_desc()) == NULL) {
+		ERR("mmc device not found\n");
+		return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
+	}
+
+	pte = fastboot_flash_find_ptn(partition);
+	if (!pte) {
+		ERR("no %s partition\n", partition);
+		fastboot_flash_dump_ptn();
+		return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
+	}
+
+	blksz = fs_dev_desc->blksz;
+	part_start = pte->start;
+	part_end = pte->start + pte->length - 1;
+	VDEBUG("blksz: %ld, part_end: %ld, part_start: %ld:\n",
+			blksz, part_end, part_start);
+
+	if(get_margin_pos((uint64_t)part_start, (uint64_t)part_end, blksz,
+				&margin, offset, num_bytes, false))
+		return AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION;
+
+	bs = (lbaint_t)margin.blk_start;
+	s = margin.start;
+
+	// alloc a blksz mem
+	bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz);
+	if (bdata == NULL)
+		return AVB_IO_RESULT_ERROR_OOM;
+
+	while (num_write < num_bytes) {
+		memset(bdata, 0, blksz);
+		cnt = blksz - s;
+		if (num_write + cnt >  num_bytes)
+			cnt = num_bytes - num_write;
+		if (!s || cnt != blksz) { //read blk first
+			if (blk_dread(fs_dev_desc, bs, 1, bdata) != 1) {
+				ret = AVB_IO_RESULT_ERROR_IO;
+				goto fail;
+			}
+		}
+		memcpy(bdata + s, in_buf, cnt); //change data
+		VDEBUG("cur: bs=%ld, start=%ld, cnt=%ld bdata=0x%08x\n",
+				bs, s, cnt, bdata);
+		if (blk_dwrite(fs_dev_desc, bs, 1, bdata) != 1) {
+			ret = AVB_IO_RESULT_ERROR_IO;
+			goto fail;
+		}
+		bs++;
+		num_write += cnt;
+		in_buf += cnt;
+		if (s != 0)
+			s = 0;
+	}
+	ret = AVB_IO_RESULT_OK;
+
+fail:
+	free(bdata);
+	return ret;
+}
+
+/* Gets whether the device is unlocked. The value is returned in
+ * |out_is_unlocked| (true if unlocked, false otherwise). Returns
+ * AVB_IO_RESULT_OK if the state was retrieved, otherwise an error
+ * code.
+ */
+AvbIOResult fsl_read_is_device_unlocked(AvbOps* ops, bool* out_is_unlocked) {
+
+	FbLockState status;
+
+	assert(out_is_unlocked != NULL);
+	*out_is_unlocked = false;
+
+	status = fastboot_get_lock_stat();
+	if (status != FASTBOOT_LOCK_ERROR) {
+		if (status == FASTBOOT_LOCK)
+			*out_is_unlocked = false;
+		else
+			*out_is_unlocked = true;
+	} else
+		return AVB_IO_RESULT_ERROR_IO;
+
+	DEBUGAVB("is_unlocked=%d\n", *out_is_unlocked);
+	return AVB_IO_RESULT_OK;
+}
+
+/* Gets the unique partition GUID for a partition with name in
+ * |partition| (NUL-terminated UTF-8 string). The GUID is copied as
+ * a string into |guid_buf| of size |guid_buf_size| and will be NUL
+ * terminated. The string must be lower-case and properly
+ * hyphenated. For example:
+ *
+ *  527c1c6d-6361-4593-8842-3c78fcd39219
+ *
+ * Returns AVB_IO_RESULT_OK on success, otherwise an error code.
+ */
+AvbIOResult fsl_get_unique_guid_for_partition(AvbOps* ops,
+					      const char* partition,
+					      char* guid_buf,
+					      size_t guid_buf_size) {
+	assert(guid_buf != NULL);
+#ifdef CONFIG_PARTITION_UUIDS
+	struct fastboot_ptentry *pte;
+	pte = fastboot_flash_find_ptn(partition);
+	if (!pte) {
+		ERR("no %s partition\n", partition);
+		fastboot_flash_dump_ptn();
+		return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
+	}
+	strncpy(guid_buf, (const char *)pte->uuid, guid_buf_size);
+	guid_buf[guid_buf_size - 1] = '\0';
+	DEBUGAVB("[%s]: GUID=%s\n", partition, guid_buf);
+	return AVB_IO_RESULT_OK;
+#else
+	return AVB_IO_RESULT_ERROR_IO;
+#endif
+
+}
+/* Gets the size of a partition with the name in |partition|
+ * (NUL-terminated UTF-8 string). Returns the value in
+ * |out_size_num_bytes|.
+ * Returns AVB_IO_RESULT_OK on success, otherwise an error code.
+ */
+AvbIOResult fsl_get_size_of_partition(AvbOps* ops,
+		const char* partition,
+		uint64_t* out_size_num_bytes)
+{
+	struct fastboot_ptentry *pte;
+	pte = fastboot_flash_find_ptn(partition);
+	if (!pte) {
+		ERR("no %s partition\n", partition);
+		fastboot_flash_dump_ptn();
+		return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
+	}
+	*out_size_num_bytes = (uint64_t)(pte->length) * 512;
+	return AVB_IO_RESULT_OK;
+}
+
+#ifdef CONFIG_AVB_ATX
+/* Reads permanent |attributes| data. There are no restrictions on where this
+ * data is stored. On success, returns AVB_IO_RESULT_OK and populates
+ * |attributes|.
+ */
+AvbIOResult fsl_read_permanent_attributes(
+    AvbAtxOps* atx_ops, AvbAtxPermanentAttributes* attributes) {
+#ifdef CONFIG_IMX_TRUSTY_OS
+	if (!trusty_read_permanent_attributes((uint8_t *)attributes,
+			sizeof(AvbAtxPermanentAttributes))) {
+		return AVB_IO_RESULT_OK;
+	}
+	ERR("No perm-attr fused. Will use hard code one.\n");
+#endif /* CONFIG_IMX_TRUSTY_OS */
+
+	/* use hard code permanent attributes due to limited fuse and RPMB */
+	attributes->version = fsl_version;
+	memcpy(attributes->product_root_public_key, fsl_product_root_public_key,
+	       sizeof(fsl_product_root_public_key));
+	memcpy(attributes->product_id, fsl_atx_product_id,
+	       sizeof(fsl_atx_product_id));
+
+	return AVB_IO_RESULT_OK;
+}
+
+/* Reads a |hash| of permanent attributes. This hash MUST be retrieved from a
+ * permanently read-only location (e.g. fuses) when a device is LOCKED. On
+ * success, returned AVB_IO_RESULT_OK and populates |hash|.
+ */
+AvbIOResult fsl_read_permanent_attributes_hash(
+    AvbAtxOps* atx_ops, uint8_t hash[AVB_SHA256_DIGEST_SIZE]) {
+#ifdef CONFIG_ARM64
+	/* calculate sha256(permanent attributes) */
+	if (permanent_attributes_sha256_hash(hash) != RESULT_OK) {
+		return AVB_IO_RESULT_ERROR_IO;
+	} else {
+	    return AVB_IO_RESULT_OK;
+	}
+#else
+	uint8_t sha256_hash_buf[AVB_SHA256_DIGEST_SIZE];
+	uint32_t sha256_hash_fuse[ATX_FUSE_BANK_NUM];
+
+	/* read first 112 bits of sha256(permanent attributes) from fuse */
+	if (fsl_fuse_read(sha256_hash_fuse, ATX_FUSE_BANK_NUM,
+			  PERMANENT_ATTRIBUTE_HASH_OFFSET)) {
+		printf("ERROR - read permanent attributes hash from "
+		       "fuse error\n");
+		return AVB_IO_RESULT_ERROR_IO;
+	}
+	/* only take the lower 2 bytes of last bank */
+	sha256_hash_fuse[ATX_FUSE_BANK_NUM - 1] &= ATX_FUSE_BANK_MASK;
+
+	/* calculate sha256(permanent attributes) */
+	if (permanent_attributes_sha256_hash(sha256_hash_buf) != RESULT_OK) {
+		return AVB_IO_RESULT_ERROR_IO;
+	}
+	/* check if the sha256(permanent attributes) hash match the calculated one,
+	 * if not match, just return all zeros hash.
+	 */
+	if (memcmp(sha256_hash_fuse, sha256_hash_buf, ATX_HASH_LENGTH)) {
+		printf("ERROR - sha256(permanent attributes) does not match\n");
+		memset(hash, 0, AVB_SHA256_DIGEST_SIZE);
+	} else {
+		memcpy(hash, sha256_hash_buf, AVB_SHA256_DIGEST_SIZE);
+	}
+
+	return AVB_IO_RESULT_OK;
+#endif /* CONFIG_ARM64 */
+}
+
+ /* Generates |num_bytes| random bytes and stores them in |output|,
+   * which must point to a buffer large enough to store the bytes.
+   *
+   * Returns AVB_IO_RESULT_OK on success, otherwise an error code.
+   */
+AvbIOResult fsl_get_random(AvbAtxOps* atx_ops,
+				size_t num_bytes,
+				uint8_t* output)
+{
+	uint32_t num = 0;
+	uint32_t i;
+
+	if (output == NULL) {
+		ERR("Output buffer is NULL!\n");
+		return AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE;
+	}
+
+	/* set the seed as device boot time. */
+	srand((uint32_t)get_timer(0));
+	for (i = 0; i < num_bytes; i++) {
+		num = rand() % 256;
+		output[i] = (uint8_t)num;
+	}
+
+	return AVB_IO_RESULT_OK;
+}
+/* Provides the key version of a key used during verification. This may be
+ * useful for managing the minimum key version.
+ */
+void fsl_set_key_version(AvbAtxOps* atx_ops,
+			 size_t rollback_index_location,
+			 uint64_t key_version) {
+	kblb_hdr_t hdr;
+	kblb_tag_t *rbk;
+	uint64_t *plain_idx = NULL;
+	struct mmc *mmc_dev;
+	static const uint32_t kTypeMask = 0xF000;
+
+	DEBUGAVB("[rpmb] write to rollback slot: (%zu, %" PRIu64 ")\n",
+		 rollback_index_location, key_version);
+
+	assert(atx_ops != NULL);
+
+	if ((mmc_dev = get_mmc()) == NULL) {
+		ERR("err get mmc device\n");
+	}
+	/* read the kblb header */
+	if (rpmb_read(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) {
+		ERR("read RPMB error\n");
+	}
+
+	if (memcmp(hdr.magic, AVB_KBLB_MAGIC, AVB_KBLB_MAGIC_LEN) != 0) {
+		ERR("magic not match\n");
+	}
+
+	/* rollback index for Android Things key versions */
+	rbk = &hdr.atx_rbk_tags[rollback_index_location & ~kTypeMask];
+
+	plain_idx = malloc(rbk->len);
+	if (plain_idx == NULL)
+		printf("\nError! allocate memory fail!\n");
+	memset(plain_idx, 0, rbk->len);
+	*plain_idx = key_version;
+
+	/* write rollback_index keyblob */
+	if (rpmb_write(mmc_dev, (uint8_t *)plain_idx, rbk->len, rbk->offset) !=
+	    0) {
+		ERR("write rollback index error\n");
+		goto fail;
+	}
+fail:
+	if (plain_idx != NULL)
+		free(plain_idx);
+}
+#endif /* CONFIG_AVB_ATX */
+
+#ifdef AVB_RPMB
+/* Checks if the given public key used to sign the 'vbmeta'
+ * partition is trusted. Boot loaders typically compare this with
+ * embedded key material generated with 'avbtool
+ * extract_public_key'.
+ *
+ * If AVB_IO_RESULT_OK is returned then |out_is_trusted| is set -
+ * true if trusted or false if untrusted.
+ */
+AvbIOResult fsl_validate_vbmeta_public_key_rpmb(AvbOps* ops,
+					   const uint8_t* public_key_data,
+					   size_t public_key_length,
+					   const uint8_t* public_key_metadata,
+					   size_t public_key_metadata_length,
+					   bool* out_is_trusted) {
+	AvbIOResult ret;
+	assert(ops != NULL && out_is_trusted != NULL);
+	*out_is_trusted = false;
+
+#ifdef CONFIG_LOAD_KEY_FROM_RPMB
+	uint8_t public_key_buf[AVB_MAX_BUFFER_LENGTH];
+	if (trusty_read_vbmeta_public_key(public_key_buf,
+						public_key_length) != 0) {
+		ERR("Read public key error\n");
+		/* We're not going to return error code here because it will
+		 * abort the following avb verify process even we allow the
+		 * verification error. Return AVB_IO_RESULT_OK and keep the
+		 * 'out_is_trusted' as false, avb will handle the error
+		 * depends on the 'allow_verification_error' flag.
+		 */
+		return AVB_IO_RESULT_OK;
+	}
+
+	if (memcmp(public_key_buf, public_key_data, public_key_length)) {
+#else
+	/* match given public key */
+	if (memcmp(fsl_public_key, public_key_data, public_key_length)) {
+#endif
+		ERR("public key not match\n");
+		return AVB_IO_RESULT_OK;
+	}
+
+	*out_is_trusted = true;
+	ret = AVB_IO_RESULT_OK;
+
+	return ret;
+}
+
+/* Sets the rollback index corresponding to the slot given by
+ * |rollback_index_slot| to |rollback_index|. Returns
+ * AVB_IO_RESULT_OK if the rollback index was set, otherwise an
+ * error code.
+ *
+ * A device may have a limited amount of rollback index slots (say,
+ * one or four) so may error out if |rollback_index_slot| exceeds
+ * this number.
+ */
+AvbIOResult fsl_write_rollback_index_rpmb(AvbOps* ops, size_t rollback_index_slot,
+				     uint64_t rollback_index) {
+	AvbIOResult ret;
+#ifdef CONFIG_IMX_TRUSTY_OS
+	if (trusty_write_rollback_index(rollback_index_slot, rollback_index)) {
+		ERR("write rollback from Trusty error!\n");
+#ifndef CONFIG_AVB_ATX
+		/* Read/write rollback index from rpmb will fail if the rpmb
+		 * key hasn't been set, return AVB_IO_RESULT_OK in this case.
+		 */
+		if (!rpmbkey_is_set())
+			ret = AVB_IO_RESULT_OK;
+		else
+#endif
+			ret = AVB_IO_RESULT_ERROR_IO;
+	} else {
+		ret = AVB_IO_RESULT_OK;
+	}
+	return ret;
+#else
+	kblb_hdr_t hdr;
+	kblb_tag_t *rbk;
+	uint64_t *plain_idx = NULL;
+	struct mmc *mmc_dev;
+#ifdef CONFIG_AVB_ATX
+	static const uint32_t kTypeMask = 0xF000;
+	static const unsigned int kTypeShift = 12;
+#endif
+
+	DEBUGAVB("[rpmb] write to rollback slot: (%zu, %" PRIu64 ")\n",
+			rollback_index_slot, rollback_index);
+
+	assert(ops != NULL);
+	/* check if the rollback index location exceed the limit */
+#ifdef CONFIG_AVB_ATX
+	if ((rollback_index_slot & ~kTypeMask) >= AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS)
+#else
+	if (rollback_index_slot >= AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS)
+#endif /* CONFIG_AVB_ATX */
+		return AVB_IO_RESULT_ERROR_IO;
+
+	if ((mmc_dev = get_mmc()) == NULL) {
+		ERR("err get mmc device\n");
+		return AVB_IO_RESULT_ERROR_IO;
+	}
+	/* read the kblb header */
+	if (rpmb_read(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) {
+		ERR("read RPMB error\n");
+		return AVB_IO_RESULT_ERROR_IO;
+	}
+
+	if (memcmp(hdr.magic, AVB_KBLB_MAGIC, AVB_KBLB_MAGIC_LEN) != 0) {
+		ERR("magic not match\n");
+		return AVB_IO_RESULT_ERROR_IO;
+	}
+	/* choose rollback index type */
+#ifdef CONFIG_AVB_ATX
+	if ((rollback_index_slot & kTypeMask) >> kTypeShift) {
+		/* rollback index for Android Things key versions */
+		rbk = &hdr.atx_rbk_tags[rollback_index_slot & ~kTypeMask];
+	} else {
+		/* rollback index for vbmeta */
+		rbk = &hdr.rbk_tags[rollback_index_slot & ~kTypeMask];
+	}
+#else
+	rbk = &hdr.rbk_tags[rollback_index_slot];
+#endif /* CONFIG_AVB_ATX */
+	plain_idx = malloc(rbk->len);
+	if (plain_idx == NULL)
+		return AVB_IO_RESULT_ERROR_OOM;
+	memset(plain_idx, 0, rbk->len);
+	*plain_idx = rollback_index;
+
+	/* write rollback_index keyblob */
+	if (rpmb_write(mmc_dev, (uint8_t *)plain_idx, rbk->len, rbk->offset) !=
+	    0) {
+		ERR("write rollback index error\n");
+		ret = AVB_IO_RESULT_ERROR_IO;
+		goto fail;
+	}
+	ret = AVB_IO_RESULT_OK;
+fail:
+	if (plain_idx != NULL)
+		free(plain_idx);
+	return ret;
+#endif /* CONFIG_IMX_TRUSTY_OS */
+}
+
+/* Gets the rollback index corresponding to the slot given by
+ * |rollback_index_slot|. The value is returned in
+ * |out_rollback_index|. Returns AVB_IO_RESULT_OK if the rollback
+ * index was retrieved, otherwise an error code.
+ *
+ * A device may have a limited amount of rollback index slots (say,
+ * one or four) so may error out if |rollback_index_slot| exceeds
+ * this number.
+ */
+AvbIOResult fsl_read_rollback_index_rpmb(AvbOps* ops, size_t rollback_index_slot,
+				    uint64_t* out_rollback_index) {
+	AvbIOResult ret;
+#ifdef CONFIG_IMX_TRUSTY_OS
+	if (trusty_read_rollback_index(rollback_index_slot, out_rollback_index)) {
+		ERR("read rollback from Trusty error!\n");
+#ifndef CONFIG_AVB_ATX
+		if (!rpmbkey_is_set()) {
+			*out_rollback_index = 0;
+			ret = AVB_IO_RESULT_OK;
+		} else
+#endif
+			ret = AVB_IO_RESULT_ERROR_IO;
+	} else {
+		ret = AVB_IO_RESULT_OK;
+	}
+	return ret;
+#else
+	kblb_hdr_t hdr;
+	kblb_tag_t *rbk;
+	uint64_t *extract_idx = NULL;
+	struct mmc *mmc_dev;
+#ifdef CONFIG_AVB_ATX
+	static const uint32_t kTypeMask = 0xF000;
+	static const unsigned int kTypeShift = 12;
+#endif
+
+	assert(ops != NULL && out_rollback_index != NULL);
+	*out_rollback_index = ~0;
+
+	DEBUGAVB("[rpmb] read rollback slot: %zu\n", rollback_index_slot);
+
+	/* check if the rollback index location exceed the limit */
+#ifdef CONFIG_AVB_ATX
+	if ((rollback_index_slot & ~kTypeMask) >= AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS)
+#else
+	if (rollback_index_slot >= AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS)
+#endif
+		return AVB_IO_RESULT_ERROR_IO;
+
+	if ((mmc_dev = get_mmc()) == NULL) {
+		ERR("err get mmc device\n");
+		return AVB_IO_RESULT_ERROR_IO;
+	}
+	/* read the kblb header */
+	if (rpmb_read(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) {
+		ERR("read RPMB error\n");
+		return AVB_IO_RESULT_ERROR_IO;
+	}
+
+	if (memcmp(hdr.magic, AVB_KBLB_MAGIC, AVB_KBLB_MAGIC_LEN) != 0) {
+		ERR("magic not match\n");
+		return AVB_IO_RESULT_ERROR_IO;
+	}
+	/* choose rollback index type */
+#ifdef CONFIG_AVB_ATX
+	if ((rollback_index_slot & kTypeMask) >> kTypeShift) {
+		/* rollback index for Android Things key versions */
+		rbk = &hdr.atx_rbk_tags[rollback_index_slot & ~kTypeMask];
+	} else {
+		/* rollback index for vbmeta */
+		rbk = &hdr.rbk_tags[rollback_index_slot & ~kTypeMask];
+	}
+#else
+	rbk = &hdr.rbk_tags[rollback_index_slot];
+#endif /* CONFIG_AVB_ATX */
+	extract_idx = malloc(rbk->len);
+	if (extract_idx == NULL)
+		return AVB_IO_RESULT_ERROR_OOM;
+
+	/* read rollback_index keyblob */
+	if (rpmb_read(mmc_dev, (uint8_t *)extract_idx, rbk->len, rbk->offset) != 0) {
+		ERR("read rollback index error\n");
+		ret = AVB_IO_RESULT_ERROR_IO;
+		goto fail;
+	}
+
+#ifdef AVB_VVDEBUG
+	printf("\n----idx dump: ---\n");
+	print_buffer(0, extract_idx, HEXDUMP_WIDTH, rbk->len, 0);
+	printf("--- end ---\n");
+#endif
+	*out_rollback_index = *extract_idx;
+	DEBUGAVB("rollback_index = %" PRIu64 "\n", *out_rollback_index);
+	ret = AVB_IO_RESULT_OK;
+fail:
+	if (extract_idx != NULL)
+		free(extract_idx);
+	return ret;
+#endif /* CONFIG_IMX_TRUSTY_OS */
+}
+#else /* AVB_RPMB */
+AvbIOResult fsl_validate_vbmeta_public_key_rpmb(AvbOps* ops,
+					   const uint8_t* public_key_data,
+					   size_t public_key_length,
+					   const uint8_t* public_key_metadata,
+					   size_t public_key_metadata_length,
+					   bool* out_is_trusted) {
+	assert(ops != NULL && out_is_trusted != NULL);
+
+	/* match given public key */
+	if (memcmp(fsl_public_key, public_key_data, public_key_length)) {
+		ERR("public key not match\n");
+		*out_is_trusted = false;
+	} else
+		*out_is_trusted = true;
+
+	/* We're not going to return error code when public key
+	 * verify fail because it will abort the following avb
+	 * verify process even we allow the verification error.
+	 * Return AVB_IO_RESULT_OK and keep the 'out_is_trusted'
+	 * as false, avb will handle the error depends on the
+	 * 'allow_verification_error' flag.
+	 */
+	return AVB_IO_RESULT_OK;
+}
+
+/* In no security enhanced ARM64, rollback index has no protection so no use it */
+AvbIOResult fsl_write_rollback_index_rpmb(AvbOps* ops, size_t rollback_index_slot,
+				     uint64_t rollback_index) {
+	return AVB_IO_RESULT_OK;
+
+}
+AvbIOResult fsl_read_rollback_index_rpmb(AvbOps* ops, size_t rollback_index_slot,
+				    uint64_t* out_rollback_index) {
+	*out_rollback_index = 0;
+	return AVB_IO_RESULT_OK;
+}
+#endif /* AVB_RPMB */
diff --git a/lib/avb/fsl/fsl_avbkey.c b/lib/avb/fsl/fsl_avbkey.c
new file mode 100644
index 00000000000..096492dbe6c
--- /dev/null
+++ b/lib/avb/fsl/fsl_avbkey.c
@@ -0,0 +1,1360 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2019 NXP
+ * SPDX-License-Identifier:     GPL-2.0+
+ *
+ */
+#include <common.h>
+#include <stdlib.h>
+#include <fuse.h>
+#include <mmc.h>
+#include <hash.h>
+#include <mapmem.h>
+#include <hang.h>
+#include <cpu_func.h>
+
+#include <fsl_avb.h>
+#include <fsl_sec.h>
+#include "trusty/avb.h"
+#ifdef CONFIG_IMX_TRUSTY_OS
+#include <trusty/libtipc.h>
+#endif
+#include "fsl_avbkey.h"
+#include "utils.h"
+#include "debug.h"
+#include <memalign.h>
+#include "trusty/hwcrypto.h"
+#include "trusty/rpmb.h"
+#include "fsl_atx_attributes.h"
+#include <asm/mach-imx/hab.h>
+#include <asm/arch/sys_proto.h>
+#ifdef CONFIG_ARCH_IMX8
+#include <asm/arch/sci/sci.h>
+#endif
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#endif
+
+#define INITFLAG_FUSE_OFFSET 0
+#define INITFLAG_FUSE_MASK 0x00000001
+#define INITFLAG_FUSE 0x00000001
+
+#define RPMB_BLKSZ 256
+#define RPMBKEY_LENGTH 32
+#define RPMBKEY_BLOB_LEN ((RPMBKEY_LENGTH) + (CAAM_PAD))
+
+extern int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value);
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MMC)
+int spl_get_mmc_dev(void)
+{
+	u32 dev_no = spl_boot_device();
+	switch (dev_no) {
+	case BOOT_DEVICE_MMC1:
+		return 0;
+	case BOOT_DEVICE_MMC2:
+	case BOOT_DEVICE_MMC2_2:
+		return 1;
+	}
+
+#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
+	printf("spl: unsupported mmc boot device.\n");
+#endif
+
+	return -ENODEV;
+}
+#endif
+
+#ifdef AVB_RPMB
+static u8 skeymod[] = {
+	0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08,
+	0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00
+};
+
+struct mmc *get_mmc(void) {
+	int mmc_dev_no;
+	struct mmc *mmc;
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MMC)
+	mmc_dev_no = spl_get_mmc_dev();
+#else
+	mmc_dev_no = mmc_get_env_dev();
+#endif
+	mmc = find_mmc_device(mmc_dev_no);
+	if (!mmc || mmc_init(mmc))
+		return NULL;
+	return mmc;
+}
+
+void fill_secure_keyslot_package(struct keyslot_package *kp) {
+
+	memcpy((void*)CAAM_ARB_BASE_ADDR, kp, sizeof(struct keyslot_package));
+
+	/* invalidate the cache to make sure no critical information left in it */
+	memset(kp, 0, sizeof(struct keyslot_package));
+	invalidate_dcache_range(((ulong)kp) & 0xffffffc0,(((((ulong)kp) +
+				sizeof(struct keyslot_package)) & 0xffffff00) +
+				0x100));
+}
+
+int read_keyslot_package(struct keyslot_package* kp) {
+	char original_part;
+	int blksz;
+	unsigned char* fill = NULL;
+	int ret = 0;
+	/* load tee from boot1 of eMMC. */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MMC)
+	int mmcc = spl_get_mmc_dev();
+#else
+	int mmcc = mmc_get_env_dev();
+#endif
+	struct blk_desc *dev_desc = NULL;
+
+	struct mmc *mmc;
+#ifdef CONFIG_IMX8_TRUSTY_XEN
+	mmcc = 0;
+#endif
+	mmc = find_mmc_device(mmcc);
+	if (!mmc) {
+		printf("boota: cannot find '%d' mmc device\n", mmcc);
+		return -1;
+	}
+#if !CONFIG_IS_ENABLED(BLK)
+	original_part = mmc->block_dev.hwpart;
+	dev_desc = blk_get_dev("mmc", mmcc);
+#else
+	dev_desc = mmc_get_blk_desc(mmc);
+#endif
+	if (NULL == dev_desc) {
+		printf("** Block device MMC %d not supported\n", mmcc);
+		return -1;
+	}
+#if CONFIG_IS_ENABLED(BLK)
+	original_part = dev_desc->hwpart;
+#endif
+
+	blksz = dev_desc->blksz;
+	fill = (unsigned char *)memalign(ALIGN_BYTES, blksz);
+
+	/* below was i.MX mmc operation code */
+	if (mmc_init(mmc)) {
+		printf("mmc%d init failed\n", mmcc);
+		ret = -1;
+		goto fail;;
+	}
+
+	if (mmc_switch_part(mmc, KEYSLOT_HWPARTITION_ID) != 0) {
+		ret = -1;
+		goto fail;
+	}
+#if !CONFIG_IS_ENABLED(BLK)
+	mmc->block_dev.hwpart = KEYSLOT_HWPARTITION_ID;
+#else
+	dev_desc->hwpart = KEYSLOT_HWPARTITION_ID;
+#endif
+	if (blk_dread(dev_desc, KEYSLOT_BLKS,
+		    1, fill) != 1) {
+		printf("Failed to read rpmbkeyblob.");
+		ret = -1;
+		goto fail;
+	} else {
+		memcpy(kp, fill, sizeof(struct keyslot_package));
+	}
+
+fail:
+	/* Free allocated memory. */
+	if (fill != NULL)
+		free(fill);
+	/* Return to original partition */
+#if !CONFIG_IS_ENABLED(BLK)
+	if (mmc->block_dev.hwpart != original_part) {
+		if (mmc_switch_part(mmc, original_part) != 0)
+			return -1;
+		mmc->block_dev.hwpart = original_part;
+	}
+#else
+	if (dev_desc->hwpart != original_part) {
+		if (mmc_switch_part(mmc, original_part) != 0)
+			return -1;
+		dev_desc->hwpart = original_part;
+	}
+#endif
+	return ret;
+}
+
+bool rpmbkey_is_set(void)
+{
+	int mmcc;
+	bool ret;
+	uint8_t *buf;
+	struct mmc *mmc;
+	char original_part;
+	struct blk_desc *desc = NULL;
+
+	/* Get current mmc device. */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MMC)
+	mmcc = spl_get_mmc_dev();
+#else
+	mmcc = mmc_get_env_dev();
+#endif
+	mmc = find_mmc_device(mmcc);
+	if (!mmc) {
+		printf("error - cannot find '%d' mmc device\n", mmcc);
+		return false;
+	}
+
+#if !CONFIG_IS_ENABLED(BLK)
+	original_part = mmc->block_dev.hwpart;
+	desc = blk_get_dev("mmc", mmcc);
+#else
+	desc = mmc_get_blk_desc(mmc);
+	original_part = desc->hwpart;
+#endif
+
+	/* Switch to the RPMB partition */
+#if !CONFIG_IS_ENABLED(BLK)
+	if (mmc->block_dev.hwpart != MMC_PART_RPMB) {
+#else
+	if (desc->hwpart != MMC_PART_RPMB) {
+#endif
+		if (mmc_switch_part(mmc, MMC_PART_RPMB) != 0) {
+			printf("ERROR - can't switch to rpmb partition \n");
+			return false;
+		}
+#if !CONFIG_IS_ENABLED(BLK)
+		mmc->block_dev.hwpart = MMC_PART_RPMB;
+#else
+		desc->hwpart = MMC_PART_RPMB;
+#endif
+	}
+
+	/* Try to read the first one block, return count '1' means the rpmb
+	 * key has been set, otherwise means the key hasn't been set.
+	 */
+	buf = (uint8_t *)memalign(ALIGN_BYTES, desc->blksz);
+	if (mmc_rpmb_read(mmc, buf, 0, 1, NULL) != 1)
+		ret = false;
+	else
+		ret = true;
+
+	/* return to original partition. */
+#if !CONFIG_IS_ENABLED(BLK)
+	if (mmc->block_dev.hwpart != original_part) {
+#else
+	if (desc->hwpart != original_part) {
+#endif
+		if (mmc_switch_part(mmc, original_part) != 0)
+			ret = false;
+#if !CONFIG_IS_ENABLED(BLK)
+		mmc->block_dev.hwpart = original_part;
+#else
+		desc->hwpart = original_part;
+#endif
+	}
+	/* remember to free the buffer */
+	if (buf != NULL)
+		free(buf);
+
+	return ret;
+}
+
+int rpmb_read(struct mmc *mmc, uint8_t *buffer, size_t num_bytes, int64_t offset) {
+
+	unsigned char *bdata = NULL;
+	unsigned char *out_buf = (unsigned char *)buffer;
+	unsigned long s, cnt;
+	unsigned long blksz;
+	size_t num_read = 0;
+	unsigned short part_start, part_length, part_end, bs, be;
+	margin_pos_t margin;
+	char original_part;
+	uint8_t *blob = NULL, *keymod = NULL;
+	struct blk_desc *desc = mmc_get_blk_desc(mmc);
+	ALLOC_CACHE_ALIGN_BUFFER(uint8_t, extract_key, RPMBKEY_LENGTH);
+
+	struct keyslot_package kp;
+	int ret;
+
+	blksz = RPMB_BLKSZ;
+	part_length = mmc->capacity_rpmb >> 8;
+	part_start = 0;
+	part_end = part_start + part_length - 1;
+
+	DEBUGAVB("[rpmb]: offset=%ld, num_bytes=%zu\n", (long)offset, num_bytes);
+
+	if(get_margin_pos(part_start, part_end, blksz,
+				&margin, offset, num_bytes, false))
+		return -1;
+
+	bs = (unsigned short)margin.blk_start;
+	be = (unsigned short)margin.blk_end;
+	s = margin.start;
+
+	/* Switch to the RPMB partition */
+	original_part = desc->hwpart;
+	if (desc->hwpart != MMC_PART_RPMB) {
+		if (mmc_switch_part(mmc, MMC_PART_RPMB) != 0)
+			return -1;
+		desc->hwpart = MMC_PART_RPMB;
+	}
+
+	/* get rpmb key */
+	blob = (uint8_t *)memalign(ARCH_DMA_MINALIGN, RPMBKEY_BLOB_LEN);
+	keymod = (uint8_t *)memalign(ARCH_DMA_MINALIGN, sizeof(skeymod));
+	memcpy(keymod, skeymod, sizeof(skeymod));
+	if (read_keyslot_package(&kp)) {
+		ERR("read rpmb key error\n");
+		ret = -1;
+		goto fail;
+	}
+
+	if (!strcmp(kp.magic, KEYPACK_MAGIC)) {
+		/* Use the key from keyslot. */
+		memcpy(blob, kp.rpmb_keyblob, RPMBKEY_BLOB_LEN);
+		if (blob_decap(keymod, blob, extract_key, RPMBKEY_LENGTH, 0)) {
+			ERR("decap rpmb key error\n");
+			ret = -1;
+			goto fail;
+		}
+	} else if (derive_blob_kek(extract_key, keymod, RPMBKEY_LENGTH)) {
+		ERR("get rpmb key error\n");
+		ret = -1;
+		goto fail;
+	}
+
+	/* alloc a blksz mem */
+	bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz);
+	if (bdata == NULL) {
+		ret = -1;
+		goto fail;
+	}
+	/* one block a time */
+	while (bs <= be) {
+		memset(bdata, 0, blksz);
+		if (mmc_rpmb_read(mmc, bdata, bs, 1, extract_key) != 1) {
+			ret = -1;
+			goto fail;
+		}
+		cnt = blksz - s;
+		if (num_read + cnt > num_bytes)
+			cnt = num_bytes - num_read;
+		VDEBUG("cur: bs=%d, start=%ld, cnt=%ld bdata=0x%p\n",
+				bs, s, cnt, bdata);
+		memcpy(out_buf, bdata + s, cnt);
+		bs++;
+		num_read += cnt;
+		out_buf += cnt;
+		s = 0;
+	}
+	memset(extract_key, 0, RPMBKEY_LENGTH);
+	ret = 0;
+
+fail:
+	/* Return to original partition */
+	if (desc->hwpart != original_part) {
+		if (mmc_switch_part(mmc, original_part) != 0)
+			ret = -1;
+		else
+			desc->hwpart = original_part;
+	}
+	if (blob != NULL)
+		free(blob);
+	if (keymod != NULL)
+		free(keymod);
+	if (bdata != NULL)
+		free(bdata);
+	return ret;
+
+}
+
+int rpmb_write(struct mmc *mmc, uint8_t *buffer, size_t num_bytes, int64_t offset) {
+
+	unsigned char *bdata = NULL;
+	unsigned char *in_buf = (unsigned char *)buffer;
+	unsigned long s, cnt;
+	unsigned long blksz;
+	size_t num_write = 0;
+	unsigned short part_start, part_length, part_end, bs;
+	margin_pos_t margin;
+	char original_part;
+	uint8_t *blob = NULL, *keymod = NULL;
+	struct blk_desc *desc = mmc_get_blk_desc(mmc);
+	ALLOC_CACHE_ALIGN_BUFFER(uint8_t, extract_key, RPMBKEY_LENGTH);
+
+	struct keyslot_package kp;
+	int ret;
+
+	blksz = RPMB_BLKSZ;
+	part_length = mmc->capacity_rpmb >> 8;
+	part_start = 0;
+	part_end = part_start + part_length - 1;
+
+	DEBUGAVB("[rpmb]: offset=%ld, num_bytes=%zu\n", (long)offset, num_bytes);
+
+	if(get_margin_pos(part_start, part_end, blksz,
+				&margin, offset, num_bytes, false)) {
+		ERR("get_margin_pos err\n");
+		return -1;
+	}
+
+	bs = (unsigned short)margin.blk_start;
+	s = margin.start;
+
+	/* Switch to the RPMB partition */
+	original_part = desc->hwpart;
+	if (desc->hwpart != MMC_PART_RPMB) {
+		if (mmc_switch_part(mmc, MMC_PART_RPMB) != 0)
+			return -1;
+		desc->hwpart = MMC_PART_RPMB;
+	}
+
+	/* get rpmb key */
+	blob = (uint8_t *)memalign(ARCH_DMA_MINALIGN, RPMBKEY_BLOB_LEN);
+	keymod = (uint8_t *)memalign(ARCH_DMA_MINALIGN, sizeof(skeymod));
+	memcpy(keymod, skeymod, sizeof(skeymod));
+	if (read_keyslot_package(&kp)) {
+		ERR("read rpmb key error\n");
+		ret = -1;
+		goto fail;
+	}
+	if (!strcmp(kp.magic, KEYPACK_MAGIC)) {
+		/* Use the key from keyslot. */
+		memcpy(blob, kp.rpmb_keyblob, RPMBKEY_BLOB_LEN);
+		if (blob_decap(keymod, blob, extract_key, RPMBKEY_LENGTH, 0)) {
+			ERR("decap rpmb key error\n");
+			ret = -1;
+			goto fail;
+		}
+	} else if (derive_blob_kek(extract_key, keymod, RPMBKEY_LENGTH)) {
+		ERR("get rpmb key error\n");
+		ret = -1;
+		goto fail;
+	}
+	/* alloc a blksz mem */
+	bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz);
+	if (bdata == NULL) {
+		ret = -1;
+		goto fail;
+	}
+	while (num_write < num_bytes) {
+		memset(bdata, 0, blksz);
+		cnt = blksz - s;
+		if (num_write + cnt >  num_bytes)
+			cnt = num_bytes - num_write;
+		if (!s || cnt != blksz) { /* read blk first */
+			if (mmc_rpmb_read(mmc, bdata, bs, 1, extract_key) != 1) {
+				ERR("mmc_rpmb_read err, mmc= 0x%08x\n", (uint32_t)(ulong)mmc);
+				ret = -1;
+				goto fail;
+			}
+		}
+		memcpy(bdata + s, in_buf, cnt); /* change data */
+		VDEBUG("cur: bs=%d, start=%ld, cnt=%ld\n",	bs, s, cnt);
+		if (mmc_rpmb_write(mmc, bdata, bs, 1, extract_key) != 1) {
+			ret = -1;
+			goto fail;
+		}
+		bs++;
+		num_write += cnt;
+		in_buf += cnt;
+		if (s != 0)
+			s = 0;
+	}
+	memset(extract_key, 0, RPMBKEY_LENGTH);
+	ret = 0;
+
+fail:
+	/* Return to original partition */
+	if (desc->hwpart != original_part) {
+		if (mmc_switch_part(mmc, original_part) != 0)
+			ret = -1;
+		else
+			desc->hwpart = original_part;
+	}
+	if (blob != NULL)
+		free(blob);
+	if (keymod != NULL)
+		free(keymod);
+	if (bdata != NULL)
+		free(bdata);
+
+	return ret;
+
+}
+
+int rpmb_init(void) {
+#if !defined(CONFIG_SPL_BUILD) || !defined(CONFIG_IMX_TRUSTY_OS)
+	int i;
+#endif
+	kblb_hdr_t hdr;
+	kblb_tag_t *tag;
+	struct mmc *mmc_dev;
+	uint32_t offset;
+	uint32_t rbidx_len;
+	uint8_t *rbidx;
+
+	/* check init status first */
+	if ((mmc_dev = get_mmc()) == NULL) {
+		ERR("ERROR - get mmc device\n");
+		return -1;
+	}
+	/* The bootloader rollback index is stored in the last 8k bytes of
+	 * RPMB which is different from the rollback index for vbmeta and
+	 * ATX key versions.
+	 */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX_TRUSTY_OS)
+	if (rpmb_read(mmc_dev, (uint8_t *)&hdr, sizeof(hdr),
+			BOOTLOADER_RBIDX_OFFSET) != 0) {
+#else
+	if (rpmb_read(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) {
+#endif
+		ERR("read RPMB error\n");
+		return -1;
+	}
+	if (!memcmp(hdr.magic, AVB_KBLB_MAGIC, AVB_KBLB_MAGIC_LEN))
+		return 0;
+	else
+		printf("initialize rollback index...\n");
+	/* init rollback index */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX_TRUSTY_OS)
+	offset = BOOTLOADER_RBIDX_START;
+	rbidx_len = BOOTLOADER_RBIDX_LEN;
+	rbidx = malloc(rbidx_len);
+	if (rbidx == NULL) {
+		ERR("failed to allocate memory!\n");
+		return -1;
+	}
+	memset(rbidx, 0, rbidx_len);
+	*(uint64_t *)rbidx = BOOTLOADER_RBIDX_INITVAL;
+	tag = &hdr.bootloader_rbk_tags;
+	tag->offset = offset;
+	tag->len = rbidx_len;
+	if (rpmb_write(mmc_dev, rbidx, tag->len, tag->offset) != 0) {
+		ERR("write RBKIDX RPMB error\n");
+		free(rbidx);
+		return -1;
+	}
+	if (rbidx != NULL)
+		free(rbidx);
+#else /* CONFIG_SPL_BUILD && CONFIG_IMX_TRUSTY_OS */
+	offset = AVB_RBIDX_START;
+	rbidx_len = AVB_RBIDX_LEN;
+	rbidx = malloc(rbidx_len);
+	if (rbidx == NULL)
+		return -1;
+	memset(rbidx, 0, rbidx_len);
+	*(uint64_t *)rbidx = AVB_RBIDX_INITVAL;
+	for (i = 0; i < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; i++) {
+		tag = &hdr.rbk_tags[i];
+		tag->flag = AVB_RBIDX_FLAG;
+		tag->offset = offset;
+		tag->len = rbidx_len;
+		if (rpmb_write(mmc_dev, rbidx, tag->len, tag->offset) != 0) {
+			ERR("write RBKIDX RPMB error\n");
+			free(rbidx);
+			return -1;
+		}
+		offset += AVB_RBIDX_ALIGN;
+	}
+	if (rbidx != NULL)
+		free(rbidx);
+#ifdef CONFIG_AVB_ATX
+	/* init rollback index for Android Things key versions */
+	offset = ATX_RBIDX_START;
+	rbidx_len = ATX_RBIDX_LEN;
+	rbidx = malloc(rbidx_len);
+	if (rbidx == NULL)
+		return -1;
+	memset(rbidx, 0, rbidx_len);
+	*(uint64_t *)rbidx = ATX_RBIDX_INITVAL;
+	for (i = 0; i < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; i++) {
+		tag = &hdr.atx_rbk_tags[i];
+		tag->flag = ATX_RBIDX_FLAG;
+		tag->offset = offset;
+		tag->len = rbidx_len;
+		if (rpmb_write(mmc_dev, rbidx, tag->len, tag->offset) != 0) {
+			ERR("write ATX_RBKIDX RPMB error\n");
+			free(rbidx);
+			return -1;
+		}
+		offset += ATX_RBIDX_ALIGN;
+	}
+	if (rbidx != NULL)
+		free(rbidx);
+#endif
+#endif /* CONFIG_SPL_BUILD && CONFIG_IMX_TRUSTY_OS */
+
+	/* init hdr */
+	memcpy(hdr.magic, AVB_KBLB_MAGIC, AVB_KBLB_MAGIC_LEN);
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX_TRUSTY_OS)
+	if (rpmb_write(mmc_dev, (uint8_t *)&hdr, sizeof(hdr),
+			BOOTLOADER_RBIDX_OFFSET) != 0) {
+#else
+	if (rpmb_write(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) {
+#endif
+		ERR("write RPMB hdr error\n");
+		return -1;
+	}
+
+	return 0;
+}
+
+int gen_rpmb_key(struct keyslot_package *kp) {
+	char original_part;
+	unsigned char* fill = NULL;
+	int blksz;
+	uint8_t *keymod = NULL;
+	ALLOC_CACHE_ALIGN_BUFFER(uint8_t, plain_key, RPMBKEY_LENGTH);
+
+	kp->rpmb_keyblob_len = RPMBKEY_LEN;
+	strcpy(kp->magic, KEYPACK_MAGIC);
+
+	int ret = -1;
+	/* load tee from boot1 of eMMC. */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MMC)
+	int mmcc = spl_get_mmc_dev();
+#else
+	int mmcc = mmc_get_env_dev();
+#endif
+	struct blk_desc *dev_desc = NULL;
+
+	struct mmc *mmc;
+	mmc = find_mmc_device(mmcc);
+	if (!mmc) {
+		printf("boota: cannot find '%d' mmc device\n", mmcc);
+		return -1;
+	}
+#if !CONFIG_IS_ENABLED(BLK)
+	original_part = mmc->block_dev.hwpart;
+	dev_desc = blk_get_dev("mmc", mmcc);
+#else
+	dev_desc = mmc_get_blk_desc(mmc);
+	original_part = dev_desc->hwpart;
+#endif
+	if (NULL == dev_desc) {
+		printf("** Block device MMC %d not supported\n", mmcc);
+		goto fail;
+	}
+
+	blksz = dev_desc->blksz;
+	fill = (unsigned char *)memalign(ALIGN_BYTES, blksz);
+
+	/* below was i.MX mmc operation code */
+	if (mmc_init(mmc)) {
+		printf("mmc%d init failed\n", mmcc);
+		goto fail;
+	}
+
+	/* Switch to the RPMB partition */
+
+#ifdef TRUSTY_RPMB_RANDOM_KEY
+	/*
+	 * Since boot1 is a bit easy to be erase during development
+	 * so that before production stage use full 0 rpmb key
+	 */
+	if (hwrng_generate(plain_key, RPMBKEY_LENGTH)) {
+		ERR("ERROR - caam rng\n");
+		goto fail;
+	}
+#else
+	memset(plain_key, 0, RPMBKEY_LENGTH);
+#endif
+
+	keymod = (uint8_t *)memalign(ARCH_DMA_MINALIGN, sizeof(skeymod));
+	memcpy(keymod, skeymod, sizeof(skeymod));
+	/* generate keyblob and program to boot1 partition */
+	if (blob_encap(keymod, plain_key, kp->rpmb_keyblob, RPMBKEY_LENGTH, 0)) {
+		ERR("gen rpmb key blb error\n");
+		goto fail;
+	}
+	memcpy(fill, kp, sizeof(struct keyslot_package));
+
+	if (mmc_switch_part(mmc, KEYSLOT_HWPARTITION_ID) != 0) {
+		ret = -1;
+		goto fail;
+	}
+
+	if (blk_dwrite(dev_desc, KEYSLOT_BLKS,
+		    1, (void *)fill) != 1) {
+		printf("Failed to write rpmbkeyblob.");
+		goto fail;
+	}
+
+	/* program key to mmc */
+#if !CONFIG_IS_ENABLED(BLK)
+	if (mmc->block_dev.hwpart != MMC_PART_RPMB) {
+		if (mmc_switch_part(mmc, MMC_PART_RPMB) != 0) {
+			ret = -1;
+			goto fail;
+		} else
+			mmc->block_dev.hwpart = MMC_PART_RPMB;
+	}
+#else
+	if (dev_desc->hwpart != MMC_PART_RPMB) {
+		if (mmc_switch_part(mmc, MMC_PART_RPMB) != 0) {
+			ret = -1;
+			goto fail;
+		} else
+			dev_desc->hwpart = MMC_PART_RPMB;
+	}
+#endif
+	if (mmc_rpmb_set_key(mmc, plain_key)) {
+		ERR("Key already programmed ?\n");
+		goto fail;
+	}
+
+	ret = 0;
+
+fail:
+	/* Return to original partition */
+#if !CONFIG_IS_ENABLED(BLK)
+	if (mmc->block_dev.hwpart != original_part) {
+		if (mmc_switch_part(mmc, original_part) != 0)
+			ret = -1;
+		else
+			mmc->block_dev.hwpart = original_part;
+	}
+#else
+	if (dev_desc->hwpart != original_part) {
+		if (mmc_switch_part(mmc, original_part) != 0)
+			ret = -1;
+		else
+			dev_desc->hwpart = original_part;
+	}
+#endif
+	if (fill != NULL)
+		free(fill);
+	if (keymod != NULL)
+		free(keymod);
+
+	return ret;
+
+}
+
+int init_avbkey(void) {
+	struct keyslot_package kp;
+	read_keyslot_package(&kp);
+	if (strcmp(kp.magic, KEYPACK_MAGIC)) {
+		printf("keyslot package magic error. Will generate new one\n");
+		memset((void *)&kp, 0, sizeof(struct keyslot_package));
+		gen_rpmb_key(&kp);
+	}
+#ifndef CONFIG_IMX_TRUSTY_OS
+	if (rpmb_init())
+		return RESULT_ERROR;
+#endif
+#if defined(CONFIG_AVB_ATX) && !defined(CONFIG_IMX_TRUSTY_OS)
+	if (init_permanent_attributes_fuse())
+		return RESULT_ERROR;
+#endif
+	fill_secure_keyslot_package(&kp);
+	return RESULT_OK;
+}
+
+#ifndef CONFIG_IMX_TRUSTY_OS
+int rbkidx_erase(void) {
+	int i;
+	kblb_hdr_t hdr;
+	kblb_tag_t *tag;
+	struct mmc *mmc_dev;
+
+	if ((mmc_dev = get_mmc()) == NULL) {
+		ERR("err get mmc device\n");
+		return -1;
+	}
+
+	/* read the kblb header */
+	if (rpmb_read(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) {
+		ERR("read RPMB error\n");
+		return -1;
+	}
+	if (memcmp(hdr.magic, AVB_KBLB_MAGIC, AVB_KBLB_MAGIC_LEN) != 0) {
+		ERR("magic not match\n");
+		return -1;
+	}
+
+	/* reset rollback index */
+	uint32_t offset = AVB_RBIDX_START;
+	uint32_t rbidx_len = AVB_RBIDX_LEN;
+	uint8_t *rbidx = malloc(rbidx_len);
+	if (rbidx == NULL)
+		return -1;
+	memset(rbidx, 0, rbidx_len);
+	*(uint64_t *)rbidx = AVB_RBIDX_INITVAL;
+	for (i = 0; i < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; i++) {
+		tag = &hdr.rbk_tags[i];
+		tag->flag = AVB_RBIDX_FLAG;
+		tag->offset = offset;
+		tag->len = rbidx_len;
+		/* write */
+		if (rpmb_write(mmc_dev, rbidx, tag->len, tag->offset) != 0) {
+			ERR("write RBKIDX RPMB error\n");
+			free(rbidx);
+			return -1;
+		}
+		offset += AVB_RBIDX_ALIGN;
+	}
+	free(rbidx);
+	/* write back hdr */
+	if (rpmb_write(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) {
+		ERR("write RPMB hdr error\n");
+		return -1;
+	}
+	return 0;
+}
+#endif /* CONFIG_IMX_TRUSTY_OS */
+#else /* AVB_RPMB */
+int rbkidx_erase(void) {
+	return 0;
+}
+#endif /* AVB_RPMB */
+
+#ifdef CONFIG_SPL_BUILD
+#if defined (CONFIG_IMX8_TRUSTY_XEN) || \
+	(defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX))
+int check_rpmb_blob(struct mmc *mmc)
+{
+	int ret = 0;
+	char original_part;
+	struct keyslot_package kp;
+#if CONFIG_IS_ENABLED(BLK)
+	struct blk_desc *dev_desc = NULL;
+#endif
+
+	read_keyslot_package(&kp);
+	if (strcmp(kp.magic, KEYPACK_MAGIC)) {
+		/* Return if the magic doesn't match */
+		return 0;
+	}
+	/* If keyslot package valid, copy it to secure memory */
+	fill_secure_keyslot_package(&kp);
+
+	/* switch to boot1 partition. */
+#if !CONFIG_IS_ENABLED(BLK)
+	original_part = mmc->block_dev.hwpart;
+#else
+	dev_desc = mmc_get_blk_desc(mmc);
+	original_part = dev_desc->hwpart;
+#endif
+	if (mmc_switch_part(mmc, KEYSLOT_HWPARTITION_ID) != 0) {
+		printf("ERROR - can't switch to boot1 partition! \n");
+		ret = -1;
+		goto fail;
+	} else
+#if !CONFIG_IS_ENABLED(BLK)
+		mmc->block_dev.hwpart = KEYSLOT_HWPARTITION_ID;
+#else
+		dev_desc->hwpart = KEYSLOT_HWPARTITION_ID;
+#endif
+	/* write power-on write protection for boot1 partition. */
+	if (mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+			EXT_CSD_BOOT_WP, BOOT1_PWR_WP)) {
+		printf("ERROR - unable to set power-on write protection!\n");
+		ret = -1;
+		goto fail;
+	}
+fail:
+	/* return to original partition. */
+#if !CONFIG_IS_ENABLED(BLK)
+	if (mmc->block_dev.hwpart != original_part) {
+		if (mmc_switch_part(mmc, original_part) != 0)
+			return -1;
+		mmc->block_dev.hwpart = original_part;
+	}
+#else
+	if (dev_desc->hwpart != original_part) {
+		if (mmc_switch_part(mmc, original_part) != 0)
+			return -1;
+		dev_desc->hwpart = original_part;
+	}
+#endif
+
+	return ret;
+}
+#endif /* CONFIG_IMX_TRUSTY_OS && !defined(CONFIG_AVB_ATX) */
+#else /* CONFIG_SPL_BUILD */
+#ifdef CONFIG_AVB_ATX
+static int fsl_fuse_ops(uint32_t *buffer, uint32_t length, uint32_t offset,
+			const uint8_t read) {
+
+	unsigned short bs, ws, bksz, cnt;
+	unsigned short num_done = 0;
+	margin_pos_t margin;
+	int i;
+
+	/* read from fuse */
+	bksz = CONFIG_AVB_FUSE_BANK_SIZEW;
+	if(get_margin_pos(CONFIG_AVB_FUSE_BANK_START, CONFIG_AVB_FUSE_BANK_END, bksz,
+				&margin, offset, length, false))
+		return -1;
+	bs = (unsigned short)margin.blk_start;
+	ws = (unsigned short)margin.start;
+
+	while (num_done < length) {
+		cnt = bksz - ws;
+		if (num_done + cnt > length)
+			cnt = length - num_done;
+		for (i = 0; i < cnt; i++) {
+			VDEBUG("cur: bank=%d, word=%d\n",bs, ws);
+			if (read) {
+				if (fuse_sense(bs, ws, buffer)) {
+					ERR("read fuse bank %d, word %d error\n", bs, ws);
+					return -1;
+				}
+			} else {
+#ifdef CONFIG_AVB_FUSE
+				if (fuse_prog(bs, ws, *buffer)) {
+#else
+				if (fuse_override(bs, ws, *buffer)) {
+#endif
+					ERR("write fuse bank %d, word %d error\n", bs, ws);
+					return -1;
+				}
+			}
+			ws++;
+			buffer++;
+		}
+		bs++;
+		num_done += cnt;
+		ws = 0;
+	}
+	return 0;
+}
+
+int fsl_fuse_read(uint32_t *buffer, uint32_t length, uint32_t offset) {
+
+	return fsl_fuse_ops(
+		buffer,
+		length,
+		offset,
+		1
+		);
+}
+
+int fsl_fuse_write(const uint32_t *buffer, uint32_t length, uint32_t offset) {
+
+	return fsl_fuse_ops(
+		(uint32_t *)buffer,
+		length,
+		offset,
+		0
+		);
+}
+
+static int sha256(unsigned char* data, int len, unsigned char* output) {
+	struct hash_algo *algo;
+	void *buf;
+
+	if (hash_lookup_algo("sha256", &algo)) {
+		printf("error in lookup sha256 algo!\n");
+		return RESULT_ERROR;
+	}
+	buf = map_sysmem((ulong)data, len);
+	algo->hash_func_ws(buf, len, output, algo->chunk_size);
+	unmap_sysmem(buf);
+
+	return algo->digest_size;
+}
+
+int permanent_attributes_sha256_hash(unsigned char* output) {
+	AvbAtxPermanentAttributes attributes;
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+	if(!trusty_read_permanent_attributes((uint8_t *)(&attributes),
+		sizeof(AvbAtxPermanentAttributes))) {
+		goto calc_sha256;
+	} else {
+		ERR("No perm-attr fused. Will use hard code one.\n");
+	}
+#endif
+	/* get permanent attributes */
+	attributes.version = fsl_version;
+	memcpy(attributes.product_root_public_key, fsl_product_root_public_key,
+			sizeof(fsl_product_root_public_key));
+	memcpy(attributes.product_id, fsl_atx_product_id,
+			sizeof(fsl_atx_product_id));
+#ifdef CONFIG_IMX_TRUSTY_OS
+calc_sha256:
+#endif
+	/* calculate sha256(permanent attributes) hash */
+	if (sha256((unsigned char *)&attributes, sizeof(AvbAtxPermanentAttributes),
+			output) == RESULT_ERROR) {
+		printf("ERROR - calculate permanent attributes hash error");
+		return RESULT_ERROR;
+	}
+
+	return RESULT_OK;
+}
+
+static int init_permanent_attributes_fuse(void) {
+
+#ifdef CONFIG_ARM64
+       return RESULT_OK;
+#else
+	uint8_t sha256_hash[AVB_SHA256_DIGEST_SIZE];
+	uint32_t buffer[ATX_FUSE_BANK_NUM];
+	int num = 0;
+
+	/* read first 112 bits of sha256(permanent attributes) from fuse */
+	if (fsl_fuse_read(buffer, ATX_FUSE_BANK_NUM, PERMANENT_ATTRIBUTE_HASH_OFFSET)) {
+		printf("ERROR - read permanent attributes hash from fuse error\n");
+		return RESULT_ERROR;
+	}
+	/* only take the lower 2 bytes of the last bank */
+	buffer[ATX_FUSE_BANK_NUM - 1] &= ATX_FUSE_BANK_MASK;
+
+	/* return RESULT_OK if fuse has been initialized before */
+	for (num = 0; num < ATX_FUSE_BANK_NUM; num++) {
+		if (buffer[num])
+		    return RESULT_OK;
+	}
+
+	/* calculate sha256(permanent attributes) */
+	if (permanent_attributes_sha256_hash(sha256_hash) != RESULT_OK) {
+		printf("ERROR - calculating permanent attributes SHA256 error!\n");
+		return RESULT_ERROR;
+	}
+
+	/* write first 112 bits of sha256(permanent attributes) into fuse */
+	memset(buffer, 0, sizeof(buffer));
+	memcpy(buffer, sha256_hash, ATX_HASH_LENGTH);
+	if (fsl_fuse_write(buffer, ATX_FUSE_BANK_NUM, PERMANENT_ATTRIBUTE_HASH_OFFSET)) {
+		printf("ERROR - write permanent attributes hash to fuse error\n");
+		return RESULT_ERROR;
+	}
+
+	return RESULT_OK;
+#endif /* CONFIG_ARM64 */
+}
+
+int avb_atx_fuse_perm_attr(uint8_t *staged_buffer, uint32_t size) {
+
+	if (staged_buffer == NULL) {
+		ERR("Error. Get null staged_buffer\n");
+		return -1;
+	}
+	if (size != sizeof(AvbAtxPermanentAttributes)) {
+		ERR("Error. expect perm_attr length %u, but get %u.\n",
+		(uint32_t)sizeof(AvbAtxPermanentAttributes), size);
+		return -1;
+	}
+#ifdef CONFIG_IMX_TRUSTY_OS
+	if (trusty_write_permanent_attributes(staged_buffer, size)) {
+		ERR("Error. Failed to write permanent attributes into secure storage\n");
+		return -1;
+	}
+	else
+		return init_permanent_attributes_fuse();
+#else
+	/*
+	 * TODO:
+	 * Need to handle this when no Trusty OS support.
+	 * But now every Android Things will have Trusty OS support.
+	 */
+	ERR("No Trusty OS enabled in bootloader.\n");
+	return 0;
+#endif
+}
+
+int avb_atx_get_unlock_challenge(struct AvbAtxOps* atx_ops,
+				uint8_t *upload_buffer, uint32_t *upload_size)
+{
+	struct AvbAtxUnlockChallenge *buf = NULL;
+	int ret, size;
+
+	size = sizeof(struct AvbAtxUnlockChallenge);
+	buf = (struct AvbAtxUnlockChallenge *)malloc(size);
+	if (buf == NULL) {
+		ERR("unable to alloc memory!\n");
+		return -1;
+	}
+
+	if (avb_atx_generate_unlock_challenge(atx_ops, buf) !=
+			AVB_IO_RESULT_OK) {
+		ERR("generate unlock challenge fail!\n");
+		ret = -1;
+		goto fail;
+	}
+	/* Current avbtool only accept 16 bytes random numbers as unlock
+	 * challenge, need to return the whole 'AvbAtxUnlockChallenge'
+	 * when avbtool is ready.
+	 */
+	memcpy(upload_buffer, buf->challenge, AVB_ATX_UNLOCK_CHALLENGE_SIZE);
+	*upload_size = AVB_ATX_UNLOCK_CHALLENGE_SIZE;
+	ret = 0;
+fail:
+	if (buf != NULL)
+		free(buf);
+	return ret;
+}
+
+int avb_atx_verify_unlock_credential(struct AvbAtxOps* atx_ops,
+					uint8_t *staged_buffer)
+{
+	bool out_is_trusted;
+	AvbIOResult ret;
+	const AvbAtxUnlockCredential* buf = NULL;
+
+	buf = (const AvbAtxUnlockCredential*)staged_buffer;
+	ret = avb_atx_validate_unlock_credential(atx_ops, buf, &out_is_trusted);
+	if ((ret != AVB_IO_RESULT_OK) || (out_is_trusted != true)) {
+		ERR("validate unlock credential fail!\n");
+		return -1;
+	} else
+		return 0;
+}
+
+bool perm_attr_are_fused(void)
+{
+#ifdef CONFIG_IMX_TRUSTY_OS
+	AvbAtxPermanentAttributes attributes;
+	if(!trusty_read_permanent_attributes((uint8_t *)(&attributes),
+		sizeof(AvbAtxPermanentAttributes))) {
+		return true;
+	} else {
+		ERR("No perm-attr fused, please fuse your perm-attr first!.\n");
+		return false;
+	}
+#else
+	/* We hard code the perm-attr if trusty is not enabled. */
+	return true;
+#endif
+}
+
+bool at_unlock_vboot_is_disabled(void)
+{
+	uint32_t unlock_vboot_status;
+
+	if (fsl_fuse_read(&unlock_vboot_status, 1,
+				UNLOCK_VBOOT_STATUS_OFFSET_IN_WORD)) {
+		printf("Read at unlock vboot status error!\n");
+		return false;
+	}
+
+	if (unlock_vboot_status & (1 << UNLOCK_VBOOT_STATUS_OFFSET_IN_BIT))
+		return true;
+	else
+		return false;
+}
+
+int at_disable_vboot_unlock(void)
+{
+	uint32_t unlock_vboot_status = 0;
+
+	/* Read the status first */
+	if (fsl_fuse_read(&unlock_vboot_status, 1,
+				UNLOCK_VBOOT_STATUS_OFFSET_IN_WORD)) {
+		ERR("Read unlock vboot status error!\n");
+		return -1;
+	}
+
+	/* Set the disable unlock vboot bit */
+	unlock_vboot_status |= (1 << UNLOCK_VBOOT_STATUS_OFFSET_IN_BIT);
+
+	/* Write disable unlock vboot bit to fuse */
+	if (fsl_fuse_write(&unlock_vboot_status, 1,
+				UNLOCK_VBOOT_STATUS_OFFSET_IN_WORD)) {
+		ERR("Write unlock vboot status fail!\n");
+		return -1;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_AVB_ATX */
+
+#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX)
+
+extern struct imx_sec_config_fuse_t const imx_sec_config_fuse;
+#define HAB_ENABLED_BIT (is_soc_type(MXC_SOC_IMX8M)? 0x2000000 : 0x2)
+
+/* Check hab status, this is basically copied from imx_hab_is_enabled() */
+bool hab_is_enabled(void)
+{
+#ifdef CONFIG_ARCH_IMX8
+	sc_err_t err;
+	uint16_t lc;
+
+	err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL);
+	if (err != SC_ERR_NONE) {
+		printf("Error in get lifecycle\n");
+		return false;
+	}
+
+	if (lc != 0x80)
+#elif CONFIG_IMX8ULP
+	uint32_t lc;
+
+	lc = readl(FSB_BASE_ADDR + 0x41c);
+	lc &= 0x3f;
+
+	if (lc != 0x20)
+#elif CONFIG_ARCH_IMX8M
+	struct imx_sec_config_fuse_t *fuse =
+		(struct imx_sec_config_fuse_t *)&imx_sec_config_fuse;
+	uint32_t reg;
+	int ret;
+
+	ret = fuse_read(fuse->bank, fuse->word, &reg);
+	if (ret) {
+		puts("\nSecure boot fuse read error!\n");
+		return false;
+	}
+
+	if (!((reg & HAB_ENABLED_BIT) == HAB_ENABLED_BIT))
+#else
+		if (1)
+#endif
+		return false;
+	else
+		return true;
+}
+
+int do_rpmb_key_set(uint8_t *key, uint32_t key_size)
+{
+	int ret = 0;
+	int mmcc;
+	struct mmc *mmc;
+	char original_part;
+	struct keyslot_package kp;
+	struct blk_desc *desc = NULL;
+	ALLOC_CACHE_ALIGN_BUFFER(uint8_t, rpmb_key, RPMBKEY_LENGTH);
+	ALLOC_CACHE_ALIGN_BUFFER(uint8_t, blob,
+                                 RPMBKEY_LENGTH + CAAM_PAD);
+
+	/* copy rpmb key to cache aligned buffer. */
+	memset(rpmb_key, 0, RPMBKEY_LENGTH);
+	memcpy(rpmb_key, key, RPMBKEY_LENGTH);
+
+	/* Get current mmc device. */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MMC)
+	mmcc = spl_get_mmc_dev();
+#else
+	mmcc = mmc_get_env_dev();
+#endif
+	mmc = find_mmc_device(mmcc);
+	if (!mmc) {
+		printf("error - cannot find '%d' mmc device\n", mmcc);
+		return -1;
+	}
+	desc = mmc_get_blk_desc(mmc);
+	original_part = desc->hwpart;
+
+	/* Switch to the RPMB partition */
+	if (desc->hwpart != MMC_PART_RPMB) {
+		if (mmc_switch_part(mmc, MMC_PART_RPMB) != 0) {
+			printf("ERROR - can't switch to rpmb partition \n");
+			return -1;
+		}
+		desc->hwpart = MMC_PART_RPMB;
+	}
+
+	if (mmc_rpmb_set_key(mmc, rpmb_key)) {
+		printf("ERROR - Key already programmed ?\n");
+		ret = -1;
+		goto fail;
+	} else
+		printf("RPMB key programed successfully!\n");
+
+	/* Generate keyblob with CAAM. */
+	memset((void *)&kp, 0, sizeof(struct keyslot_package));
+	kp.rpmb_keyblob_len = RPMBKEY_LENGTH + CAAM_PAD;
+	strcpy(kp.magic, KEYPACK_MAGIC);
+	if (hwcrypto_gen_blob((uint32_t)(ulong)rpmb_key, RPMBKEY_LENGTH,
+				(uint32_t)(ulong)blob) != 0) {
+		printf("ERROR - generate rpmb key blob error!\n");
+		ret = -1;
+		goto fail;
+	} else
+		printf("RPMB key blob generated!\n");
+
+	memcpy(kp.rpmb_keyblob, blob, kp.rpmb_keyblob_len);
+
+	/* Reset key after use */
+	memset(rpmb_key, 0, RPMBKEY_LENGTH);
+	memset(key, 0, RPMBKEY_LENGTH);
+
+	/* Store the rpmb key blob to last block of boot1 partition. */
+	if (mmc_switch_part(mmc, KEYSLOT_HWPARTITION_ID) != 0) {
+		printf("ERROR - can't switch to boot1 partition! \n");
+		ret = -1;
+		goto fail;
+	} else
+		desc->hwpart = KEYSLOT_HWPARTITION_ID;
+	if (blk_dwrite(desc, KEYSLOT_BLKS, 1, (void *)&kp) != 1) {
+		printf("ERROR - failed to write rpmbkeyblob!");
+		ret = -1;
+		goto fail;
+	}
+	/* Set power-on write protection to boot1 partition. */
+	if (mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+			EXT_CSD_BOOT_WP, BOOT1_PWR_WP)) {
+		printf("ERROR - unable to set power-on write protection!\n");
+		ret = -1;
+		goto fail;
+	}
+
+fail:
+	/* Return to original partition */
+	if (desc->hwpart != original_part) {
+		if (mmc_switch_part(mmc, original_part) != 0)
+			return -1;
+		desc->hwpart = original_part;
+	}
+
+	return ret;
+}
+
+int fastboot_set_rpmb_staged_key(uint8_t *staged_buf, uint32_t key_size)
+{
+
+	if (memcmp(staged_buf, RPMB_KEY_MAGIC, strlen(RPMB_KEY_MAGIC))) {
+		printf("ERROR - rpmb magic doesn't match!\n");
+		return -1;
+	}
+
+	return do_rpmb_key_set(staged_buf + strlen(RPMB_KEY_MAGIC),
+				RPMBKEY_LENGTH);
+}
+
+int fastboot_set_rpmb_hardware_key(void)
+{
+	return storage_set_rpmb_key();
+}
+
+int avb_set_public_key(uint8_t *staged_buffer, uint32_t size) {
+
+	if ((staged_buffer == NULL) || (size <= 0)) {
+		ERR("Error. Get null staged_buffer\n");
+		return -1;
+	}
+	if (trusty_write_vbmeta_public_key(staged_buffer, size)) {
+		ERR("Error. Failed to write vbmeta public key into secure storage\n");
+		return -1;
+	} else
+		printf("Set vbmeta public key successfully!\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_GENERATE_MPPUBK
+int fastboot_get_mppubk(uint8_t *staged_buffer, uint32_t *size) {
+
+	if (!hab_is_enabled()) {
+		ERR("Error. This command can only be used when hab is closed!!\n");
+		return -1;
+	}
+
+	if ((staged_buffer == NULL) || (size == NULL)) {
+		ERR("Error. Get null staged_buffer!\n");
+		return -1;
+	}
+	if (trusty_get_mppubk(staged_buffer, size)) {
+		ERR("Error. Failed to get mppubk!\n");
+		return -1;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_GENERATE_MPPUBK */
+#endif /* CONFIG_IMX_TRUSTY_OS && !defind(CONFIG_AVB_ATX) */
+#endif /* CONFIG_SPL_BUILD */
diff --git a/lib/avb/fsl/fsl_avbkey.h b/lib/avb/fsl/fsl_avbkey.h
new file mode 100644
index 00000000000..2d6adf02be7
--- /dev/null
+++ b/lib/avb/fsl/fsl_avbkey.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __FSL_AVBKEY_H__
+#define __FSL_AVBKEY_H__
+
+#include <mmc.h>
+
+#define CAAM_PAD 48
+
+#define AVB_PUBKY_FLAG 0xABAB
+#define AVB_PUBKY_OFFSET 0x1000
+
+#define AVB_RBIDX_FLAG 0xCDCD
+#define AVB_RBIDX_START 0x2000
+#define AVB_RBIDX_ALIGN 0x1000
+#define AVB_RBIDX_LEN 0x08
+#define AVB_RBIDX_INITVAL 0
+
+#ifdef CONFIG_AVB_ATX
+#define ATX_RBIDX_FLAG 0xEFEF
+#define ATX_RBIDX_START 0x22000
+#define ATX_RBIDX_ALIGN 0x1000
+#define ATX_RBIDX_LEN 0x08
+#define ATX_RBIDX_INITVAL 0
+#endif
+
+#define AVB_KBLB_MAGIC "\0KBLB!"
+#define AVB_KBLB_MAGIC_LEN 6
+
+#if defined(CONFIG_AVB_ATX) && defined(CONFIG_DUAL_BOOTLOADER)
+#define BL_RBINDEX_MAGIC "BL_RBINDEX" 
+#define BL_RBINDEX_MAGIC_LEN 11
+struct bl_rbindex_package {
+	char magic[BL_RBINDEX_MAGIC_LEN];
+	uint32_t rbindex;
+};
+#endif
+
+#ifndef CONFIG_AVB_ATX
+#define RPMB_KEY_MAGIC "RPMB"
+#endif
+
+#ifdef CONFIG_AVB_ATX
+#define ATX_FUSE_BANK_NUM  4
+#define ATX_FUSE_BANK_MASK 0xFFFF
+#define ATX_HASH_LENGTH    14
+#endif
+
+#define RESULT_ERROR -1
+#define RESULT_OK     0
+
+struct kblb_tag {
+	uint32_t flag;
+	uint32_t offset;
+	uint32_t len;
+};
+typedef struct kblb_tag kblb_tag_t;
+
+struct kblb_hdr {
+	/* avbkey partition magic */
+	char magic[AVB_KBLB_MAGIC_LEN];
+	/* Rollback index for bootloader is managed by SPL and
+	 * will be stored in RPMB.
+	 */
+#if defined(CONFIG_IMX_TRUSTY_OS) && defined(CONFIG_SPL_BUILD)
+	kblb_tag_t bootloader_rbk_tags;
+#endif
+	/* public key keyblb tag */
+	kblb_tag_t pubk_tag;
+	/* vbmeta rollback index keyblb tag */
+	kblb_tag_t rbk_tags[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS];
+#ifdef CONFIG_AVB_ATX
+	/* Android Things key versions rollback index keyblb tag */
+	kblb_tag_t atx_rbk_tags[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS];
+#endif
+};
+typedef struct kblb_hdr kblb_hdr_t;
+
+#define RPMBKEY_LEN (32 + CAAM_PAD)
+#define KEYPACK_MAGIC "!KS"
+#define KEYPACK_PAD_LENGTH (512 - 4 * sizeof(char) - sizeof(unsigned int) - RPMBKEY_LEN * sizeof(unsigned char))
+
+struct keyslot_package
+{
+    char magic[4];
+    unsigned int rpmb_keyblob_len;
+    unsigned char rpmb_keyblob[RPMBKEY_LEN];
+    // padding keyslot_package to 1 block size
+    unsigned char pad[KEYPACK_PAD_LENGTH];
+};
+
+int gen_rpmb_key(struct keyslot_package *kp);
+int read_keyslot_package(struct keyslot_package* kp);
+void fill_secure_keyslot_package(struct keyslot_package *kp);
+int rpmb_init(void);
+int rpmb_read(struct mmc *mmc, uint8_t *buffer,
+		size_t num_bytes,int64_t offset);
+int rpmb_write(struct mmc *mmc, uint8_t *buffer, size_t num_bytes,
+		int64_t offset);
+
+int check_rpmb_blob(struct mmc *mmc);
+bool rpmbkey_is_set(void);
+int fsl_fuse_write(const uint32_t *buffer, uint32_t length, uint32_t offset);
+int fsl_fuse_read(uint32_t *buffer, uint32_t length, uint32_t offset);
+int permanent_attributes_sha256_hash(unsigned char* output);
+struct mmc *get_mmc(void);
+#endif
diff --git a/lib/avb/fsl/fsl_bootctrl.c b/lib/avb/fsl/fsl_bootctrl.c
new file mode 100755
index 00000000000..797503a857f
--- /dev/null
+++ b/lib/avb/fsl/fsl_bootctrl.c
@@ -0,0 +1,1462 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ *
+ * Copyright 2020 NXP
+ *
+ */
+
+#include <common.h>
+#include <stdlib.h>
+#include <linux/string.h>
+#include <mmc.h>
+#include <spl.h>
+#include <part.h>
+#include "utils.h"
+#include <fb_fsl.h>
+#include <fsl_avb.h>
+#include <image.h>
+#include <hang.h>
+#include "fsl_avbkey.h"
+#include "hang.h"
+#include "fsl_bootctrl.h"
+
+/* Maximum values for slot data */
+#define AVB_AB_MAX_PRIORITY 15
+#define AVB_AB_MAX_TRIES_REMAINING 7
+#define AVB_AB_SLOT_NUM 2
+#ifndef MAX_PTN
+#define MAX_PTN 32
+#endif
+
+/* The bootloader_control struct is stored 2048 bytes into the 'misc' partition
+ * following the 'struct bootloader_message' field. The struct is compatible with
+ * the guidelines in
+ * hardware/interfaces/boot/1.1/default/boot_control/include/libboot_control/libboot_control.h
+ */
+#define FSL_AB_METADATA_MISC_PARTITION_OFFSET 2048
+extern AvbABOps fsl_avb_ab_ops;
+
+static char *slot_suffix[AVB_AB_SLOT_NUM] = {"_a", "_b"};
+
+static int strcmp_l1(const char *s1, const char *s2) {
+	if (!s1 || !s2)
+		return -1;
+	return strncmp(s1, s2, strlen(s1));
+}
+
+int get_curr_slot(struct bootloader_control *ab_data) {
+	if (fsl_slot_is_bootable(&ab_data->slot_info[0]) &&
+		fsl_slot_is_bootable(&ab_data->slot_info[1])) {
+		if (ab_data->slot_info[1].priority > ab_data->slot_info[0].priority)
+			return 1;
+		else
+			return 0;
+	} else if (fsl_slot_is_bootable(&ab_data->slot_info[0]))
+		return 0;
+	else if (fsl_slot_is_bootable(&ab_data->slot_info[1]))
+		return 1;
+	else
+		return -1;
+}
+
+/* Return current slot without passing 'bootloader_control' struct */
+int current_slot(void) {
+	struct bootloader_control ab_data;
+
+	/* Load A/B metadata and decide which slot we are going to load */
+	if (fsl_avb_ab_ops.read_ab_metadata(&fsl_avb_ab_ops, &ab_data) !=
+					    AVB_IO_RESULT_OK) {
+		printf("Error loading AB metadata from misc!\n");
+		return -1;
+	}
+	return get_curr_slot(&ab_data);
+}
+
+int slotidx_from_suffix(char *suffix) {
+	int slot = -1;
+
+	if (!strcmp(suffix, "_a") ||
+			!strcmp(suffix, "a"))
+		slot = 0;
+	else if (!strcmp(suffix, "_b") ||
+			!strcmp(suffix, "b"))
+		slot = 1;
+
+	return slot;
+}
+
+bool is_slotvar_avb(char *cmd) {
+
+	assert(cmd != NULL);
+	if (!strcmp_l1("has-slot:", cmd) ||
+		!strcmp_l1("slot-successful:", cmd) ||
+		!strcmp_l1("slot-count", cmd) ||
+		!strcmp_l1("slot-suffixes", cmd) ||
+		!strcmp_l1("current-slot", cmd) ||
+		!strcmp_l1("slot-unbootable:", cmd) ||
+		!strcmp_l1("slot-retry-count:", cmd))
+		return true;
+	return false;
+}
+
+extern struct fastboot_ptentry g_ptable[MAX_PTN];
+extern unsigned int g_pcount;
+
+static bool has_slot(char *cmd) {
+	unsigned int n;
+	char *ptr;
+
+	for (n = 0; n < g_pcount; n++) {
+		ptr = strstr(g_ptable[n].name, cmd);
+		if (ptr != NULL) {
+			ptr += strlen(cmd);
+			if (!strcmp(ptr, "_a") || !strcmp(ptr, "_b"))
+				return true;
+		}
+	}
+	return false;
+}
+
+int get_slotvar_avb(AvbABOps *ab_ops, char *cmd, char *buffer, size_t size) {
+
+	struct bootloader_control ab_data;
+	struct slot_metadata *slot_data;
+	int slot;
+
+	if ((ab_ops == NULL) || (cmd == NULL) || (buffer == NULL))
+		return -1;
+
+	char *str = cmd;
+	if (!strcmp_l1("has-slot:", cmd)) {
+		str += strlen("has-slot:");
+		if (has_slot(str))
+			strlcpy(buffer, "yes", size);
+		else
+			strlcpy(buffer, "no", size);
+		return 0;
+
+	} else if (!strcmp_l1("slot-suffixes", cmd)) {
+		strlcpy(buffer, "_a,_b", size);
+		return 0 ;
+
+	} else if (!strcmp_l1("slot-count", cmd)) {
+		strlcpy(buffer, "2", size);
+		return 0 ;
+	}
+
+	/* load ab meta */
+	if (ab_ops->read_ab_metadata == NULL ||
+			ab_ops->read_ab_metadata(ab_ops, &ab_data) != AVB_IO_RESULT_OK) {
+		strlcpy(buffer, "ab data read error", size);
+		return -1 ;
+	}
+
+	if (!strcmp_l1("current-slot", cmd)) {
+		int curr = get_curr_slot(&ab_data);
+		if (curr >= 0 && curr < AVB_AB_SLOT_NUM)
+			strlcpy(buffer, slot_suffix[curr] + sizeof(unsigned char), size);
+		else {
+			strlcpy(buffer, "no bootable slot", size);
+			return -1;
+		}
+
+	} else if (!strcmp_l1("slot-successful:", cmd)) {
+		str += strlen("slot-successful:");
+		slot = slotidx_from_suffix(str);
+		if (slot < 0) {
+			strlcpy(buffer, "no such slot", size);
+			return -1;
+		} else {
+			slot_data = &ab_data.slot_info[slot];
+			bool succ = (slot_data->successful_boot != 0);
+			strlcpy(buffer, succ ? "yes" : "no", size);
+		}
+
+	} else if (!strcmp_l1("slot-unbootable:", cmd)) {
+		str += strlen("slot-unbootable:");
+		slot = slotidx_from_suffix(str);
+		if (slot < 0) {
+			strlcpy(buffer, "no such slot", size);
+			return -1;
+		} else {
+			slot_data = &ab_data.slot_info[slot];
+			bool bootable = fsl_slot_is_bootable(slot_data);
+			strlcpy(buffer, bootable ? "no" : "yes", size);
+		}
+
+	} else if (!strcmp_l1("slot-retry-count:", cmd)) {
+		str += strlen("slot-retry-count:");
+		slot = slotidx_from_suffix(str);
+		if (slot < 0) {
+			strlcpy(buffer, "no such slot", size);
+			return -1;
+		}
+		else {
+			slot_data = &ab_data.slot_info[slot];
+			char var[7];
+			sprintf(var, "%d",
+				slot_data->tries_remaining);
+			strlcpy(buffer, var, size);
+		}
+
+	} else {
+		strlcpy(buffer, "no such slot command", size);
+		return -1;
+	}
+
+	return 0;
+}
+
+char *select_slot(AvbABOps *ab_ops) {
+	struct bootloader_control ab_data;
+	int curr;
+
+	if (ab_ops == NULL) {
+		return NULL;
+	}
+
+	/* load ab meta */
+	if (ab_ops->read_ab_metadata == NULL ||
+			ab_ops->read_ab_metadata(ab_ops, &ab_data) != AVB_IO_RESULT_OK) {
+		return NULL;
+	}
+	curr = get_curr_slot(&ab_data);
+	if (curr >= 0 && curr < AVB_AB_SLOT_NUM)
+		return slot_suffix[curr];
+	else
+		return NULL;
+}
+
+bool fsl_avb_ab_data_verify_and_byteswap(const struct bootloader_control* src,
+					 struct bootloader_control* dest) {
+	/* Ensure magic is correct. */
+	if (src->magic != BOOT_CTRL_MAGIC) {
+		printf("Magic is incorrect.\n");
+		return false;
+	}
+
+	memcpy(dest, src, sizeof(struct bootloader_control));
+
+	/* Ensure we don't attempt to access any fields if the bootctrl version
+	* is not supported.
+	*/
+	if (dest->version > BOOT_CTRL_VERSION) {
+		printf("No support for given bootctrl version.\n");
+		return false;
+	}
+
+	/* Fail if CRC32 doesn't match. */
+	if (dest->crc32_le !=
+		avb_crc32((const uint8_t*)dest, sizeof(struct bootloader_control) - sizeof(uint32_t))) {
+		printf("CRC32 does not match.\n");
+		return false;
+	}
+
+	return true;
+}
+
+void fsl_avb_ab_data_update_crc_and_byteswap(const struct bootloader_control* src,
+					     struct bootloader_control* dest) {
+	memcpy(dest, src, sizeof(struct bootloader_control));
+	dest->crc32_le = avb_crc32((const uint8_t*)dest,
+				    sizeof(struct bootloader_control) - sizeof(uint32_t));
+}
+
+void fsl_avb_ab_data_init(struct bootloader_control* data) {
+	memset(data, '\0', sizeof(struct bootloader_control));
+	data->magic = BOOT_CTRL_MAGIC;
+	data->version = BOOT_CTRL_VERSION;
+	// this bootctrl can support up to 4 slots but here we only support 2
+	data->nb_slot = AVB_AB_SLOT_NUM;
+	data->slot_info[0].priority = AVB_AB_MAX_PRIORITY;
+	data->slot_info[0].tries_remaining = AVB_AB_MAX_TRIES_REMAINING;
+	data->slot_info[0].successful_boot = 0;
+	data->slot_info[0].verity_corrupted = 0;
+#ifdef CONFIG_DUAL_BOOTLOADER
+	data->slot_info[0].bootloader_verified = 0;
+#endif
+	data->slot_info[1].priority = AVB_AB_MAX_PRIORITY;
+	data->slot_info[1].tries_remaining = AVB_AB_MAX_TRIES_REMAINING;
+	data->slot_info[1].successful_boot = 0;
+	data->slot_info[1].verity_corrupted = 0;
+#ifdef CONFIG_DUAL_BOOTLOADER
+	data->slot_info[1].bootloader_verified = 0;
+#endif
+}
+
+AvbIOResult fsl_avb_ab_data_read(AvbABOps* ab_ops, struct bootloader_control* data) {
+	AvbOps* ops = ab_ops->ops;
+	struct bootloader_control serialized;
+	AvbIOResult io_ret;
+	size_t num_bytes_read;
+
+	io_ret = ops->read_from_partition(ops,
+					  FASTBOOT_PARTITION_MISC,
+					  FSL_AB_METADATA_MISC_PARTITION_OFFSET,
+					  sizeof(struct bootloader_control),
+					  &serialized,
+					  &num_bytes_read);
+	if (io_ret == AVB_IO_RESULT_ERROR_OOM) {
+		return AVB_IO_RESULT_ERROR_OOM;
+	} else if (io_ret != AVB_IO_RESULT_OK ||
+		num_bytes_read != sizeof(struct bootloader_control)) {
+		printf("Error reading A/B metadata.\n");
+		return AVB_IO_RESULT_ERROR_IO;
+	}
+
+	if (!fsl_avb_ab_data_verify_and_byteswap(&serialized, data)) {
+		printf(
+			"Error validating A/B metadata from disk. "
+			"Resetting and writing new A/B metadata to disk.\n");
+		fsl_avb_ab_data_init(data);
+		return fsl_avb_ab_data_write(ab_ops, data);
+	}
+
+	return AVB_IO_RESULT_OK;
+}
+
+AvbIOResult fsl_avb_ab_data_write(AvbABOps* ab_ops, const struct bootloader_control* data) {
+	AvbOps* ops = ab_ops->ops;
+	struct bootloader_control serialized;
+	AvbIOResult io_ret;
+
+	fsl_avb_ab_data_update_crc_and_byteswap(data, &serialized);
+	io_ret = ops->write_to_partition(ops,
+					 FASTBOOT_PARTITION_MISC,
+					 FSL_AB_METADATA_MISC_PARTITION_OFFSET,
+					 sizeof(struct bootloader_control),
+					 &serialized);
+	if (io_ret == AVB_IO_RESULT_ERROR_OOM) {
+		return AVB_IO_RESULT_ERROR_OOM;
+	} else if (io_ret != AVB_IO_RESULT_OK) {
+		printf("Error writing A/B metadata.\n");
+		return AVB_IO_RESULT_ERROR_IO;
+	}
+	return AVB_IO_RESULT_OK;
+}
+
+bool fsl_slot_is_bootable(struct slot_metadata* slot) {
+#ifdef CONFIG_DUAL_BOOTLOADER
+	/* The 'bootloader_verified' will be set when the slot has only one chance
+	 * left, which means the slot is bootable even tries_remaining is 0.
+	 */
+	return slot->priority > 0 &&
+		(slot->successful_boot || (slot->tries_remaining > 0)||
+		(slot->bootloader_verified == 1));
+#else
+	return slot->priority > 0 &&
+		(slot->successful_boot || (slot->tries_remaining > 0));
+#endif
+}
+
+static void fsl_slot_set_unbootable(struct slot_metadata* slot) {
+	slot->priority = 0;
+	slot->tries_remaining = 0;
+	slot->successful_boot = 0;
+#ifdef CONFIG_DUAL_BOOTLOADER
+	slot->bootloader_verified = 0;
+#endif
+}
+
+/* Ensure all unbootable and/or illegal states are marked as the
+ * canonical 'unbootable' state, e.g. priority=0, tries_remaining=0,
+ * and successful_boot=0.
+ */
+static void fsl_slot_normalize(struct slot_metadata* slot) {
+	if (slot->priority > 0) {
+#if defined(CONFIG_DUAL_BOOTLOADER) && !defined(CONFIG_SPL_BUILD)
+		if ((slot->tries_remaining == 0)
+			&& (slot->bootloader_verified != 1)) {
+			/* We've exhausted all tries -> unbootable. */
+			fsl_slot_set_unbootable(slot);
+		}
+#else
+		if (slot->tries_remaining == 0) {
+			/* We've exhausted all tries -> unbootable. */
+			fsl_slot_set_unbootable(slot);
+		}
+#endif
+	} else {
+		fsl_slot_set_unbootable(slot);
+	}
+}
+
+/* Helper function to load metadata - returns AVB_IO_RESULT_OK on
+ * success, error code otherwise.
+ */
+static AvbIOResult fsl_load_metadata(AvbABOps* ab_ops,
+					struct bootloader_control* ab_data,
+					struct bootloader_control* ab_data_orig) {
+	AvbIOResult io_ret;
+
+	io_ret = ab_ops->read_ab_metadata(ab_ops, ab_data);
+	if (io_ret != AVB_IO_RESULT_OK) {
+		printf("I/O error while loading A/B metadata.\n");
+		return io_ret;
+	}
+	*ab_data_orig = *ab_data;
+
+	/* Ensure data is normalized, e.g. illegal states will be marked as
+	 * unbootable and all unbootable states are represented with
+	 * (priority=0, tries_remaining=0, successful_boot=0).
+	 */
+	fsl_slot_normalize(&ab_data->slot_info[0]);
+	fsl_slot_normalize(&ab_data->slot_info[1]);
+	return AVB_IO_RESULT_OK;
+}
+
+/* Writes A/B metadata to disk only if it has been changed.
+ */
+static AvbIOResult fsl_save_metadata_if_changed(AvbABOps* ab_ops,
+						struct bootloader_control* ab_data,
+						struct bootloader_control* ab_data_orig) {
+	if (avb_safe_memcmp(ab_data, ab_data_orig, sizeof(struct bootloader_control)) != 0) {
+		printf("Writing A/B metadata to disk.\n");
+		return ab_ops->write_ab_metadata(ab_ops, ab_data);
+	}
+	return AVB_IO_RESULT_OK;
+}
+
+AvbIOResult fsl_avb_ab_mark_slot_active(AvbABOps* ab_ops,
+					unsigned int slot_number) {
+	struct bootloader_control ab_data, ab_data_orig;
+	unsigned int other_slot_number;
+	AvbIOResult ret;
+
+	avb_assert(slot_number < 2);
+
+	ret = fsl_load_metadata(ab_ops, &ab_data, &ab_data_orig);
+	if (ret != AVB_IO_RESULT_OK) {
+		goto out;
+	}
+
+	/* Make requested slot top priority, unsuccessful, and with max tries. */
+	ab_data.slot_info[slot_number].priority = AVB_AB_MAX_PRIORITY;
+	ab_data.slot_info[slot_number].tries_remaining = AVB_AB_MAX_TRIES_REMAINING;
+	ab_data.slot_info[slot_number].successful_boot = 0;
+#ifdef CONFIG_DUAL_BOOTLOADER
+	ab_data.slot_info[slot_number].bootloader_verified = 0;
+#endif
+
+  /* Ensure other slot doesn't have as high a priority. */
+	other_slot_number = 1 - slot_number;
+	if (ab_data.slot_info[other_slot_number].priority == AVB_AB_MAX_PRIORITY) {
+ 		ab_data.slot_info[other_slot_number].priority = AVB_AB_MAX_PRIORITY - 1;
+	}
+
+	ret = AVB_IO_RESULT_OK;
+
+out:
+	if (ret == AVB_IO_RESULT_OK) {
+		ret = fsl_save_metadata_if_changed(ab_ops, &ab_data, &ab_data_orig);
+	}
+	return ret;
+}
+
+#ifdef CONFIG_SPL_BUILD
+/* Load metadate from misc partition.
+ */
+#if defined(CONFIG_IMX_TRUSTY_OS) || defined(CONFIG_DUAL_BOOTLOADER)
+int spl_fsl_load_metadata(struct blk_desc *dev_desc,
+				 struct bootloader_control* ab_data,
+				 struct bootloader_control* ab_data_orig) {
+	struct disk_partition info;
+	struct bootloader_control serialized;
+	size_t num_bytes;
+
+	if (part_get_info_efi_by_name(dev_desc, FASTBOOT_PARTITION_MISC, &info) == -1) {
+		printf("Can't get partition info of partition: misc\n");
+		return -1;
+	} else {
+		read_from_partition_in_bytes(dev_desc, &info,
+						FSL_AB_METADATA_MISC_PARTITION_OFFSET,
+						sizeof(struct bootloader_control),
+						(void *)ab_data, &num_bytes );
+		if (num_bytes != sizeof(struct bootloader_control)) {
+			printf("Error--read metadata fail!\n");
+			return -1;
+		} else {
+			if (!fsl_avb_ab_data_verify_and_byteswap(ab_data, &serialized)) {
+				printf("Error validating A/B metadata from disk.\n");
+				printf("Resetting and writing new A/B metadata to disk.\n");
+				fsl_avb_ab_data_init(ab_data);
+				fsl_avb_ab_data_update_crc_and_byteswap(ab_data, &serialized);
+				num_bytes = 0;
+				if (write_to_partition_in_bytes(dev_desc, &info, FSL_AB_METADATA_MISC_PARTITION_OFFSET,
+								  sizeof(struct bootloader_control),
+								  (void *)&serialized, &num_bytes) ||
+								(num_bytes != sizeof(struct bootloader_control))) {
+					printf("Error--write metadata fail!\n");
+					return -1;
+				} else
+					return 0;
+			} else {
+				memcpy(ab_data_orig, ab_data, sizeof(struct bootloader_control));
+				/* Ensure data is normalized, e.g. illegal states will be marked as
+				 * unbootable and all unbootable states are represented with
+				 * (priority=0, tries_remaining=0, successful_boot=0).
+				 */
+				fsl_slot_normalize(&ab_data->slot_info[0]);
+				fsl_slot_normalize(&ab_data->slot_info[1]);
+				return 0;
+			}
+		}
+	}
+}
+#endif /* CONFIG_IMX_TRUSTY_OS || CONFIG_DUAL_BOOTLOADER */
+
+#ifdef CONFIG_IMX_TRUSTY_OS
+static int spl_verify_rbidx(struct mmc *mmc, struct slot_metadata *slot,
+			struct spl_image_info *spl_image)
+{
+	kblb_hdr_t hdr;
+	kblb_tag_t *rbk;
+	uint64_t extract_idx;
+#ifdef CONFIG_AVB_ATX
+	struct bl_rbindex_package *bl_rbindex;
+#endif
+
+	/* Make sure rollback index has been initialized before verify */
+	if (rpmb_init()) {
+		printf("RPMB init failed!\n");
+		return -1;
+	}
+
+	/* Read bootloader rollback index header first. */
+	if (rpmb_read(mmc, (uint8_t *)&hdr, sizeof(hdr),
+			BOOTLOADER_RBIDX_OFFSET) != 0) {
+		printf("Read RPMB error!\n");
+		return -1;
+	}
+
+	/* Read bootloader rollback index. */
+	rbk = &(hdr.bootloader_rbk_tags);
+	if (rpmb_read(mmc, (uint8_t *)&extract_idx, rbk->len, rbk->offset) != 0) {
+		printf("Read rollback index error!\n");
+		return -1;
+	}
+
+	/* Verify bootloader rollback index. */
+	if (spl_image->rbindex >= extract_idx) {
+		/* Rollback index verify pass, update it only when current slot
+		 * has been marked as successful.
+		 */
+		if ((slot->successful_boot != 0) && (spl_image->rbindex != extract_idx) &&
+				rpmb_write(mmc, (uint8_t *)(&(spl_image->rbindex)),
+				rbk->len, rbk->offset)) {
+			printf("Update bootloader rollback index failed!\n");
+			return -1;
+		}
+
+#ifdef CONFIG_AVB_ATX
+		/* Pass bootloader rbindex to u-boot here. */
+		bl_rbindex = (struct bl_rbindex_package *)BL_RBINDEX_LOAD_ADDR;
+		memcpy(bl_rbindex->magic, BL_RBINDEX_MAGIC, BL_RBINDEX_MAGIC_LEN);
+		if (slot->successful_boot != 0)
+			bl_rbindex->rbindex = spl_image->rbindex;
+		else
+			bl_rbindex->rbindex = extract_idx;
+#endif
+
+		return 0;
+	} else {
+		printf("Rollback index verify rejected!\n");
+		return -1;
+	}
+
+}
+/*
+ * spl_fit_get_rbindex(): Get rollback index of the bootloader.
+ * @fit:	Pointer to the FDT blob.
+ *
+ * Return:	the rollback index value of bootloader or a negative
+ * 		error number.
+ */
+int spl_fit_get_rbindex(const void *fit)
+{
+	const char *str;
+	uint64_t index;
+	int conf_node;
+	int len;
+
+	conf_node = fit_find_config_node(fit);
+	if (conf_node < 0) {
+		return conf_node;
+	}
+
+	str = fdt_getprop(fit, conf_node, "rbindex", &len);
+	if (!str) {
+		debug("cannot find property 'rbindex'\n");
+		return -EINVAL;
+	}
+
+	index = simple_strtoul(str, NULL, 10);
+
+	return index;
+}
+
+int check_rollback_index(struct spl_image_info *spl_image, struct mmc *mmc)
+{
+	struct disk_partition info;
+	struct blk_desc *desc;
+	struct bootloader_control ab_data, ab_data_orig;
+	size_t target_slot;
+	int ret = -1;
+	unsigned char original_part;
+
+	/* Only checks rollback index when rpmb key is set */
+	if (!rpmbkey_is_set()) {
+		printf("RPMB key is not set.\n");
+		return 0;
+	}
+
+	/* Check if gpt is valid */
+	desc = mmc_get_blk_desc(mmc);
+	if (desc) {
+		/* switch to user partition of eMMC */
+		original_part = desc->hwpart;
+		if (desc->hwpart != 0) {
+			if (mmc_switch_part(mmc, 0) != 0)
+				return -1;
+			desc->hwpart = 0;
+		}
+
+		if (part_get_info(desc, 1, &info)) {
+			printf("GPT is invalid, please flash correct GPT!\n");
+			ret = -1;
+			goto fail;
+		}
+	} else {
+		printf("Get block desc fail!\n");
+		return -1;
+	}
+
+	/* Load AB metadata from misc partition */
+	if (spl_fsl_load_metadata(desc, &ab_data, &ab_data_orig)) {
+		ret = -1;
+		goto fail;
+	}
+	target_slot = (ab_data.slot_info[1].priority > ab_data.slot_info[0].priority) ? 1 : 0;
+
+	ret = spl_verify_rbidx(mmc, &ab_data.slot_info[target_slot], spl_image);
+
+fail:
+	/* Return to original partition */
+	if (desc->hwpart != original_part) {
+		if (mmc_switch_part(mmc, original_part) != 0)
+			ret = -1;
+		else
+			desc->hwpart = original_part;
+	}
+
+	return ret;
+}
+#endif /* CONFIG_IMX_TRUSTY_OS */
+#endif /* CONFIG_SPL_BUILD */
+
+/* Below are the A/B AVB flow in spl and uboot proper. */
+#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_SPL_BUILD)
+
+#define PARTITION_NAME_LEN 13
+#define PARTITION_BOOTLOADER "bootloader"
+
+extern int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value);
+
+/* Pre-declaration of h_spl_load_read(), see detail implementation in
+ * common/spl/spl_mmc.c.
+ */
+ulong h_spl_load_read(struct spl_load_info *load, ulong sector,
+		      ulong count, void *buf);
+
+/* Writes A/B metadata to disk only if it has changed.
+ */
+int fsl_save_metadata_if_changed_dual_uboot(struct blk_desc *dev_desc,
+					    struct bootloader_control* ab_data,
+					    struct bootloader_control* ab_data_orig) {
+	struct bootloader_control serialized;
+	size_t num_bytes;
+	struct disk_partition info;
+
+	/* Save metadata if changed. */
+	if (memcmp(ab_data, ab_data_orig, sizeof(struct bootloader_control)) != 0) {
+		/* Get misc partition info */
+		if (part_get_info_efi_by_name(dev_desc, FASTBOOT_PARTITION_MISC, &info) == -1) {
+			printf("Can't get partition info of partition: misc\n");
+			return -1;
+		}
+
+		/* Writing A/B metadata to disk. */
+		fsl_avb_ab_data_update_crc_and_byteswap(ab_data, &serialized);
+		if (write_to_partition_in_bytes(dev_desc, &info,
+						FSL_AB_METADATA_MISC_PARTITION_OFFSET,
+						sizeof(struct bootloader_control),
+						(void *)&serialized, &num_bytes) ||
+						(num_bytes != sizeof(struct bootloader_control))) {
+			printf("Error--write metadata fail!\n");
+			return -1;
+		}
+	}
+	return 0;
+}
+
+int mmc_load_image_raw_sector_dual_uboot(struct spl_image_info *spl_image,
+					 struct mmc *mmc)
+{
+	struct disk_partition info;
+	unsigned long count;
+	int ret = 0, n = 0;
+	char partition_name[PARTITION_NAME_LEN];
+	struct blk_desc *dev_desc;
+	struct image_header *header;
+	struct spl_load_info load;
+	struct bootloader_control ab_data, ab_data_orig;
+	size_t slot_index_to_boot, target_slot;
+#if !defined(CONFIG_XEN) && defined(CONFIG_IMX_TRUSTY_OS)
+	struct keyslot_package kp;
+#endif
+
+	/* Check if gpt is valid */
+	dev_desc = mmc_get_blk_desc(mmc);
+	if (dev_desc) {
+		if (part_get_info(dev_desc, 1, &info)) {
+			printf("GPT is invalid, please flash correct GPT!\n");
+			return -1;
+		}
+	} else {
+		printf("Get block desc fail!\n");
+		return -1;
+	}
+
+#if !defined(CONFIG_XEN) && defined(CONFIG_IMX_TRUSTY_OS)
+	read_keyslot_package(&kp);
+	if (!strcmp(kp.magic, KEYPACK_MAGIC)) {
+		/* Set power-on write protection to boot1 partition. */
+		if (mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_WP, BOOT1_PWR_WP)) {
+			printf("Unable to set power-on write protection to boot1!\n");
+			return -1;
+		}
+	}
+#endif
+
+	/* Load AB metadata from misc partition */
+	if (spl_fsl_load_metadata(dev_desc, &ab_data,
+					&ab_data_orig)) {
+		return -1;
+	}
+
+	slot_index_to_boot = 2;  // Means not 0 or 1
+	target_slot =
+	    (ab_data.slot_info[1].priority > ab_data.slot_info[0].priority) ? 1 : 0;
+
+	for (n = 0; n < 2; n++) {
+		if (!fsl_slot_is_bootable(&ab_data.slot_info[target_slot])) {
+			target_slot = (target_slot == 1 ? 0 : 1);
+			continue;
+		}
+		/* Choose slot to load. */
+		snprintf(partition_name, PARTITION_NAME_LEN,
+			 PARTITION_BOOTLOADER"%s",
+			 slot_suffix[target_slot]);
+
+		/* Read part info from gpt */
+		if (part_get_info_by_name(dev_desc, partition_name, &info) == -1) {
+			printf("Can't get partition info of partition bootloader%s\n",
+				slot_suffix[target_slot]);
+			ret = -1;
+			goto end;
+		} else {
+			header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
+				 sizeof(struct image_header));
+
+			/* read image header to find the image size & load address */
+			count = blk_dread(dev_desc, info.start, 1, header);
+			if (count == 0) {
+				ret = -1;
+				goto end;
+			}
+
+			/* Load fit/container and check HAB */
+			load.dev = mmc;
+			load.priv = NULL;
+			load.filename = NULL;
+			load.bl_len = mmc->read_bl_len;
+			load.read = h_spl_load_read;
+			if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+					image_get_magic(header) == FDT_MAGIC) {
+				/* Fit */
+				ret = spl_load_simple_fit(spl_image, &load,
+							  info.start, header);
+			} else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) {
+				/* container */
+				ret = spl_load_imx_container(spl_image, &load, info.start);
+			} else
+				ret = -1;
+
+#if !defined(CONFIG_XEN) && defined(CONFIG_IMX_TRUSTY_OS)
+			/* Image loaded successfully, go to verify rollback index */
+			if (rpmbkey_is_set()) {
+				if (!ret)
+					ret = spl_verify_rbidx(mmc, &ab_data.slot_info[target_slot], spl_image);
+
+				/* Copy rpmb keyslot to secure memory. */
+				if (!ret)
+					fill_secure_keyslot_package(&kp);
+			}
+#endif
+		}
+
+		/* Set current slot to unbootable if load/verify fail. */
+		if (ret != 0) {
+			/* Reboot if current slot has booted succefully before, this prevents
+			 * slot been marked as "unbootable" due to some random failures (like
+			 * eMMC/DRAM access error at some critical temperature).
+			 */
+			if (ab_data.slot_info[target_slot].successful_boot)
+				do_reset(NULL, 0, 0, NULL);
+			else {
+				printf("Load or verify bootloader%s fail, setting unbootable..\n",
+				       slot_suffix[target_slot]);
+				fsl_slot_set_unbootable(&ab_data.slot_info[target_slot]);
+				/* Switch to another slot. */
+				target_slot = (target_slot == 1 ? 0 : 1);
+			}
+		} else {
+			slot_index_to_boot = target_slot;
+			n = 2;
+		}
+	}
+
+	if (slot_index_to_boot == 2) {
+		/* No bootable slots, try to boot into recovery! */
+		printf("No bootable slots found, try to boot into recovery mode...\n");
+
+		ab_data.spl_recovery = true;
+		if ((ab_data.last_boot != 0) && (ab_data.last_boot != 1))
+			slot_index_to_boot = 0;
+		else
+			slot_index_to_boot = ab_data.last_boot;
+
+		snprintf(partition_name, PARTITION_NAME_LEN,
+			 PARTITION_BOOTLOADER"%s",
+			 slot_suffix[target_slot]);
+
+		/* Read part info from gpt */
+		if (part_get_info_by_name(dev_desc, partition_name, &info) == -1) {
+			printf("Can't get partition info of partition bootloader%s\n",
+				slot_suffix[target_slot]);
+			ret = -1;
+			goto end;
+		} else {
+			header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
+				 sizeof(struct image_header));
+
+			/* read image header to find the image size & load address */
+			count = blk_dread(dev_desc, info.start, 1, header);
+			if (count == 0) {
+				ret = -1;
+				goto end;
+			}
+
+			/* Load fit/container and check HAB */
+			load.dev = mmc;
+			load.priv = NULL;
+			load.filename = NULL;
+			load.bl_len = mmc->read_bl_len;
+			load.read = h_spl_load_read;
+			if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+					image_get_magic(header) == FDT_MAGIC) {
+				/* Fit */
+				ret = spl_load_simple_fit(spl_image, &load,
+							  info.start, header);
+			} else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) {
+				/* container */
+				ret = spl_load_imx_container(spl_image, &load, info.start);
+			} else
+				ret = -1;
+
+#if !defined(CONFIG_XEN) && defined(CONFIG_IMX_TRUSTY_OS)
+			/* Image loaded successfully, go to verify rollback index */
+			if (rpmbkey_is_set()) {
+				if (!ret)
+					ret = spl_verify_rbidx(mmc, &ab_data.slot_info[target_slot], spl_image);
+
+				/* Copy rpmb keyslot to secure memory. */
+				if (!ret)
+					fill_secure_keyslot_package(&kp);
+			}
+#endif
+		}
+
+		if (ret)
+			goto end;
+	} else if (!ab_data.slot_info[slot_index_to_boot].successful_boot &&
+		   (ab_data.slot_info[slot_index_to_boot].tries_remaining > 0)) {
+		/* Set the bootloader_verified flag as if current slot only has one chance. */
+		if (ab_data.slot_info[slot_index_to_boot].tries_remaining == 1)
+			ab_data.slot_info[slot_index_to_boot].bootloader_verified = 1;
+		ab_data.slot_info[slot_index_to_boot].tries_remaining -= 1;
+
+		ab_data.last_boot = slot_index_to_boot;
+	}
+	printf("Booting from bootloader%s...\n", slot_suffix[slot_index_to_boot]);
+
+end:
+	/* Save metadata if changed. */
+	if (fsl_save_metadata_if_changed_dual_uboot(dev_desc, &ab_data, &ab_data_orig)) {
+		ret = -1;
+	}
+
+	if (ret)
+		return -1;
+	else
+		return 0;
+}
+
+/* For normal build */
+#elif !defined(CONFIG_SPL_BUILD)
+
+#ifdef CONFIG_DUAL_BOOTLOADER
+// dual bootloader flow in uboot proper
+AvbABFlowResult avb_flow_dual_uboot(AvbABOps* ab_ops,
+				    const char* const* requested_partitions,
+				    AvbSlotVerifyFlags flags,
+				    AvbHashtreeErrorMode hashtree_error_mode,
+				    AvbSlotVerifyData** out_data) {
+	AvbOps* ops = ab_ops->ops;
+	AvbSlotVerifyData* slot_data = NULL;
+	AvbSlotVerifyData* data = NULL;
+	AvbABFlowResult ret;
+	struct bootloader_control ab_data, ab_data_orig;
+	AvbIOResult io_ret;
+	bool saw_and_allowed_verification_error = false;
+	AvbSlotVerifyResult verify_result;
+	bool set_slot_unbootable = false;
+	int target_slot, n;
+	uint64_t rollback_index_value = 0;
+	uint64_t current_rollback_index_value = 0;
+
+	io_ret = fsl_load_metadata(ab_ops, &ab_data, &ab_data_orig);
+	if (io_ret == AVB_IO_RESULT_ERROR_OOM) {
+		ret = AVB_AB_FLOW_RESULT_ERROR_OOM;
+		goto out;
+	} else if (io_ret != AVB_IO_RESULT_OK) {
+		ret = AVB_AB_FLOW_RESULT_ERROR_IO;
+		goto out;
+	}
+
+	/* Choose the target slot, it should be the same with the one in SPL. */
+	target_slot = get_curr_slot(&ab_data);
+	if (target_slot == -1) {
+		ret = AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS;
+		printf("No bootable slot found!\n");
+		goto out;
+	}
+	/* Clear the bootloader_verified flag. */
+	ab_data.slot_info[target_slot].bootloader_verified = 0;
+
+	printf("Verifying slot %s ...\n", slot_suffix[target_slot]);
+	verify_result = avb_slot_verify(ops,
+					requested_partitions,
+					slot_suffix[target_slot],
+					flags,
+					hashtree_error_mode,
+					&slot_data);
+
+	switch (verify_result) {
+		case AVB_SLOT_VERIFY_RESULT_ERROR_OOM:
+			ret = AVB_AB_FLOW_RESULT_ERROR_OOM;
+			goto out;
+
+		case AVB_SLOT_VERIFY_RESULT_ERROR_IO:
+			ret = AVB_AB_FLOW_RESULT_ERROR_IO;
+			goto out;
+
+		case AVB_SLOT_VERIFY_RESULT_OK:
+			ret = AVB_AB_FLOW_RESULT_OK;
+			break;
+
+		case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA:
+		case AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION:
+			/* Even with AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR
+			 * these mean game over.
+			 */
+			set_slot_unbootable = true;
+			break;
+
+		case AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION:
+		case AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX:
+		case AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED:
+			if (flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR) {
+				/* Do nothing since we allow this. */
+				avb_debugv("Allowing slot ",
+					   slot_suffix[target_slot],
+					   " which verified "
+					   "with result ",
+					   avb_slot_verify_result_to_string(verify_result),
+					   " because "
+					   "AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR "
+					   "is set.\n",
+					   NULL);
+				saw_and_allowed_verification_error =
+					 true;
+			} else {
+				set_slot_unbootable = true;
+			}
+			break;
+
+		case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT:
+			ret = AVB_AB_FLOW_RESULT_ERROR_INVALID_ARGUMENT;
+			goto out;
+			/* Do not add a 'default:' case here because
+			 * of -Wswitch.
+			 */
+	}
+
+	if (set_slot_unbootable) {
+		/* Reboot if current slot has booted succefully before, this prevents
+		 * slot been marked as "unbootable" due to some random failures (like
+		 * eMMC/DRAM access error at some critical temperature).
+		 */
+		if (ab_data.slot_info[target_slot].successful_boot)
+			do_reset(NULL, 0, 0, NULL);
+		else {
+			avb_errorv("Error verifying slot ",
+				   slot_suffix[target_slot],
+				   " with result ",
+				   avb_slot_verify_result_to_string(verify_result),
+				   " - setting unbootable.\n",
+				   NULL);
+			fsl_slot_set_unbootable(&ab_data.slot_info[target_slot]);
+
+			/* Only the slot chosen by SPL will be verified here so we
+			 * return AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS if the
+			 * slot should be set unbootable.
+			 */
+			ret = AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS;
+			goto out;
+		}
+	}
+
+	/* Update stored rollback index only when the slot has been marked
+	 * as successful. Do this for every rollback index location.
+	*/
+	if ((ret == AVB_AB_FLOW_RESULT_OK) &&
+		(ab_data.slot_info[target_slot].successful_boot != 0)) {
+		for (n = 0; n < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; n++) {
+
+			rollback_index_value = slot_data->rollback_indexes[n];
+
+			if (rollback_index_value != 0) {
+				io_ret = ops->read_rollback_index(
+						ops, n, &current_rollback_index_value);
+				if (io_ret == AVB_IO_RESULT_ERROR_OOM) {
+					ret = AVB_AB_FLOW_RESULT_ERROR_OOM;
+					goto out;
+				} else if (io_ret != AVB_IO_RESULT_OK) {
+					printf("Error getting rollback index for slot.\n");
+					ret = AVB_AB_FLOW_RESULT_ERROR_IO;
+					goto out;
+				}
+				if (current_rollback_index_value != rollback_index_value) {
+					io_ret = ops->write_rollback_index(
+							ops, n, rollback_index_value);
+					if (io_ret == AVB_IO_RESULT_ERROR_OOM) {
+						ret = AVB_AB_FLOW_RESULT_ERROR_OOM;
+						goto out;
+					} else if (io_ret != AVB_IO_RESULT_OK) {
+						printf("Error setting stored rollback index.\n");
+						ret = AVB_AB_FLOW_RESULT_ERROR_IO;
+						goto out;
+					}
+				}
+			}
+		}
+	}
+
+	/* Finally, select this slot. */
+	avb_assert(slot_data != NULL);
+	data = slot_data;
+	slot_data = NULL;
+	if (saw_and_allowed_verification_error) {
+		avb_assert(
+			flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR);
+		ret = AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR;
+	} else {
+		ret = AVB_AB_FLOW_RESULT_OK;
+	}
+
+out:
+	io_ret = fsl_save_metadata_if_changed(ab_ops, &ab_data, &ab_data_orig);
+	if (io_ret != AVB_IO_RESULT_OK) {
+		if (io_ret == AVB_IO_RESULT_ERROR_OOM) {
+			ret = AVB_AB_FLOW_RESULT_ERROR_OOM;
+		} else {
+			ret = AVB_AB_FLOW_RESULT_ERROR_IO;
+		}
+		if (data != NULL) {
+			avb_slot_verify_data_free(data);
+			data = NULL;
+		}
+	}
+
+	if (slot_data != NULL)
+		avb_slot_verify_data_free(slot_data);
+
+	if (out_data != NULL) {
+		*out_data = data;
+	} else {
+		if (data != NULL) {
+			avb_slot_verify_data_free(data);
+		}
+	}
+
+	return ret;
+}
+
+static bool spl_recovery_flag = false;
+bool is_spl_recovery(void)
+{
+	return spl_recovery_flag;
+}
+void check_spl_recovery(void)
+{
+	struct bootloader_control ab_data, ab_data_orig;
+	AvbIOResult io_ret;
+
+	io_ret = fsl_load_metadata(&fsl_avb_ab_ops, &ab_data, &ab_data_orig);
+	if (io_ret != AVB_IO_RESULT_OK) {
+		printf("Load metadata fail, go to fail!\n");
+		hang();
+	}
+
+	spl_recovery_flag = ab_data.spl_recovery;
+	/* Clear spl recovery flag. */
+	ab_data.spl_recovery = false;
+	fsl_save_metadata_if_changed(&fsl_avb_ab_ops, &ab_data, &ab_data_orig);
+
+	if (spl_recovery_flag) {
+		printf("Enter spl recovery mode, only fastboot commands are supported!\n");
+
+		while (1) {
+			run_command("fastboot 0", 0);
+		}
+	}
+}
+
+#else /* CONFIG_DUAL_BOOTLOADER */
+/* For legacy i.mx6/7, we won't enable A/B due to the limitation of
+ * storage capacity, but we still want to verify boot/recovery with
+ * AVB. */
+AvbABFlowResult avb_single_flow(AvbABOps* ab_ops,
+                            const char* const* requested_partitions,
+                            AvbSlotVerifyFlags flags,
+                            AvbHashtreeErrorMode hashtree_error_mode,
+                            AvbSlotVerifyData** out_data) {
+  AvbOps* ops = ab_ops->ops;
+  AvbSlotVerifyData* slot_data = NULL;
+  AvbSlotVerifyData* data = NULL;
+  AvbABFlowResult ret;
+  bool saw_and_allowed_verification_error = false;
+
+  /* Validate boot/recovery. */
+  AvbSlotVerifyResult verify_result;
+
+  verify_result = avb_slot_verify(ops,
+                    requested_partitions,
+                    "",
+                    flags,
+                    hashtree_error_mode,
+                    &slot_data);
+  switch (verify_result) {
+      case AVB_SLOT_VERIFY_RESULT_ERROR_OOM:
+        ret = AVB_AB_FLOW_RESULT_ERROR_OOM;
+        goto out;
+
+      case AVB_SLOT_VERIFY_RESULT_ERROR_IO:
+        ret = AVB_AB_FLOW_RESULT_ERROR_IO;
+        goto out;
+
+      case AVB_SLOT_VERIFY_RESULT_OK:
+        break;
+
+      case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA:
+      case AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION:
+          /* Even with AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR
+           * these mean game over.
+           */
+        ret = AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS;
+        goto out;
+
+      /* explicit fallthrough. */
+      case AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION:
+      case AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX:
+      case AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED:
+        if (flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR) {
+          /* Do nothing since we allow this. */
+          avb_debugv("Allowing slot ",
+                     slot_suffix[n],
+                     " which verified "
+                     "with result ",
+                     avb_slot_verify_result_to_string(verify_result),
+                     " because "
+                     "AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR "
+                     "is set.\n",
+                     NULL);
+          saw_and_allowed_verification_error = true;
+        } else {
+            ret = AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS;
+            goto out;
+        }
+        break;
+
+      case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT:
+        ret = AVB_AB_FLOW_RESULT_ERROR_INVALID_ARGUMENT;
+        goto out;
+        /* Do not add a 'default:' case here because of -Wswitch. */
+      }
+
+  avb_assert(slot_data != NULL);
+  data = slot_data;
+  slot_data = NULL;
+  if (saw_and_allowed_verification_error) {
+    avb_assert(flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR);
+    ret = AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR;
+  } else {
+    ret = AVB_AB_FLOW_RESULT_OK;
+  }
+
+out:
+  if (slot_data != NULL) {
+    avb_slot_verify_data_free(slot_data);
+  }
+
+  if (out_data != NULL) {
+    *out_data = data;
+  } else {
+    if (data != NULL) {
+      avb_slot_verify_data_free(data);
+    }
+  }
+
+  return ret;
+}
+
+AvbABFlowResult avb_ab_flow_fast(AvbABOps* ab_ops,
+				 const char* const* requested_partitions,
+				 AvbSlotVerifyFlags flags,
+				 AvbHashtreeErrorMode hashtree_error_mode,
+				 AvbSlotVerifyData** out_data) {
+	AvbOps* ops = ab_ops->ops;
+	AvbSlotVerifyData* slot_data[2] = {NULL, NULL};
+	AvbSlotVerifyData* data = NULL;
+	AvbABFlowResult ret;
+	struct bootloader_control ab_data, ab_data_orig;
+	size_t slot_index_to_boot, n;
+	AvbIOResult io_ret;
+	bool saw_and_allowed_verification_error = false;
+	size_t target_slot;
+	AvbSlotVerifyResult verify_result;
+	bool set_slot_unbootable = false;
+	uint64_t rollback_index_value = 0;
+	uint64_t current_rollback_index_value = 0;
+
+	io_ret = fsl_load_metadata(ab_ops, &ab_data, &ab_data_orig);
+	if (io_ret == AVB_IO_RESULT_ERROR_OOM) {
+		ret = AVB_AB_FLOW_RESULT_ERROR_OOM;
+		goto out;
+	} else if (io_ret != AVB_IO_RESULT_OK) {
+		ret = AVB_AB_FLOW_RESULT_ERROR_IO;
+		goto out;
+	}
+
+	slot_index_to_boot = 2;  // Means not 0 or 1
+	target_slot =
+	    (ab_data.slot_info[1].priority > ab_data.slot_info[0].priority) ? 1 : 0;
+
+	for (n = 0; n < 2; n++) {
+		if (!fsl_slot_is_bootable(&ab_data.slot_info[target_slot])) {
+			target_slot = (target_slot == 1 ? 0 : 1);
+			continue;
+		}
+		verify_result = avb_slot_verify(ops,
+						requested_partitions,
+						slot_suffix[target_slot],
+						flags,
+						hashtree_error_mode,
+						&slot_data[target_slot]);
+		switch (verify_result) {
+			case AVB_SLOT_VERIFY_RESULT_ERROR_OOM:
+				ret = AVB_AB_FLOW_RESULT_ERROR_OOM;
+				goto out;
+
+			case AVB_SLOT_VERIFY_RESULT_ERROR_IO:
+				ret = AVB_AB_FLOW_RESULT_ERROR_IO;
+				goto out;
+
+			case AVB_SLOT_VERIFY_RESULT_OK:
+				slot_index_to_boot = target_slot;
+				ret = AVB_AB_FLOW_RESULT_OK;
+				n = 2;
+				break;
+
+			case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA:
+			case AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION:
+				/* Even with AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR
+				 * these mean game over.
+				 */
+				set_slot_unbootable = true;
+				break;
+
+			/* explicit fallthrough. */
+			case AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION:
+			case AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX:
+			case AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED:
+				if (flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR) {
+					/* Do nothing since we allow this. */
+					avb_debugv("Allowing slot ",
+						   slot_suffix[target_slot],
+						   " which verified "
+						   "with result ",
+						   avb_slot_verify_result_to_string(verify_result),
+						   " because "
+						   "AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR "
+						   "is set.\n",
+						   NULL);
+					saw_and_allowed_verification_error =
+						 true;
+					slot_index_to_boot = target_slot;
+					n = 2;
+				} else {
+					set_slot_unbootable = true;
+				}
+				break;
+
+			case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT:
+				ret = AVB_AB_FLOW_RESULT_ERROR_INVALID_ARGUMENT;
+				goto out;
+				/* Do not add a 'default:' case here because
+				 * of -Wswitch.
+				 */
+		}
+
+		if (set_slot_unbootable) {
+			/* Reboot if current slot has booted succefully before, this prevents
+			 * slot been marked as "unbootable" due to some random failures (like
+			 * eMMC/DRAM access error at some critical temperature).
+			 */
+			if (ab_data.slot_info[target_slot].successful_boot)
+				do_reset(NULL, 0, 0, NULL);
+			else {
+				avb_errorv("Error verifying slot ",
+					   slot_suffix[target_slot],
+					   " with result ",
+					   avb_slot_verify_result_to_string(verify_result),
+					   " - setting unbootable.\n",
+					   NULL);
+				fsl_slot_set_unbootable(&ab_data.slot_info[target_slot]);
+				set_slot_unbootable = false;
+			}
+			if (slot_data[target_slot] != NULL) {
+				avb_slot_verify_data_free(slot_data[target_slot]);
+				slot_data[target_slot] = NULL;
+			}
+		}
+		/* switch to another slot */
+		target_slot = (target_slot == 1 ? 0 : 1);
+	}
+
+	if (slot_index_to_boot == 2) {
+		/* No bootable slots! */
+		printf("No bootable slots found.\n");
+		ret = AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS;
+		goto out;
+	}
+
+	/* Update stored rollback index only when the slot has been marked
+	 * as successful. Do this for every rollback index location.
+	*/
+	if ((ret == AVB_AB_FLOW_RESULT_OK) &&
+		(ab_data.slot_info[slot_index_to_boot].successful_boot != 0)) {
+		for (n = 0; n < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; n++) {
+
+			rollback_index_value = slot_data[slot_index_to_boot]->rollback_indexes[n];
+
+			if (rollback_index_value != 0) {
+				io_ret = ops->read_rollback_index(
+						ops, n, &current_rollback_index_value);
+				if (io_ret == AVB_IO_RESULT_ERROR_OOM) {
+					ret = AVB_AB_FLOW_RESULT_ERROR_OOM;
+					goto out;
+				} else if (io_ret != AVB_IO_RESULT_OK) {
+					printf("Error getting rollback index for slot.\n");
+					ret = AVB_AB_FLOW_RESULT_ERROR_IO;
+					goto out;
+				}
+				if (current_rollback_index_value != rollback_index_value) {
+					io_ret = ops->write_rollback_index(
+							ops, n, rollback_index_value);
+					if (io_ret == AVB_IO_RESULT_ERROR_OOM) {
+						ret = AVB_AB_FLOW_RESULT_ERROR_OOM;
+						goto out;
+					} else if (io_ret != AVB_IO_RESULT_OK) {
+						printf("Error setting stored rollback index.\n");
+						ret = AVB_AB_FLOW_RESULT_ERROR_IO;
+						goto out;
+					}
+				}
+			}
+		}
+	}
+
+	/* Finally, select this slot. */
+	avb_assert(slot_data[slot_index_to_boot] != NULL);
+	data = slot_data[slot_index_to_boot];
+	slot_data[slot_index_to_boot] = NULL;
+	if (saw_and_allowed_verification_error) {
+		avb_assert(
+			flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR);
+		ret = AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR;
+	} else {
+		ret = AVB_AB_FLOW_RESULT_OK;
+	}
+
+	/* ... and decrement tries remaining, if applicable. */
+	if (!ab_data.slot_info[slot_index_to_boot].successful_boot &&
+	    (ab_data.slot_info[slot_index_to_boot].tries_remaining > 0)) {
+		ab_data.slot_info[slot_index_to_boot].tries_remaining -= 1;
+	}
+
+out:
+	io_ret = fsl_save_metadata_if_changed(ab_ops, &ab_data, &ab_data_orig);
+	if (io_ret != AVB_IO_RESULT_OK) {
+		if (io_ret == AVB_IO_RESULT_ERROR_OOM) {
+			ret = AVB_AB_FLOW_RESULT_ERROR_OOM;
+		} else {
+			ret = AVB_AB_FLOW_RESULT_ERROR_IO;
+		}
+		if (data != NULL) {
+			avb_slot_verify_data_free(data);
+			data = NULL;
+		}
+	}
+
+	for (n = 0; n < 2; n++) {
+		if (slot_data[n] != NULL) {
+			avb_slot_verify_data_free(slot_data[n]);
+		}
+	}
+
+	if (out_data != NULL) {
+		*out_data = data;
+	} else {
+		if (data != NULL) {
+			avb_slot_verify_data_free(data);
+		}
+	}
+
+	return ret;
+}
+#endif /* CONFIG_DUAL_BOOTLOADER */
+#endif /* CONFIG_DUAL_BOOTLOADER && CONFIG_SPL_BUILD */
diff --git a/lib/avb/fsl/fsl_bootctrl.h b/lib/avb/fsl/fsl_bootctrl.h
new file mode 100644
index 00000000000..6c7b30738a3
--- /dev/null
+++ b/lib/avb/fsl/fsl_bootctrl.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2020 NXP
+ *
+ */
+
+#ifndef __FSL_BOOTCTRL_H__
+#define __FSL_BOOTCTRL_H__
+
+#include "android_bootloader_message.h"
+
+typedef enum {
+	AVB_AB_FLOW_RESULT_OK,
+	AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR,
+	AVB_AB_FLOW_RESULT_ERROR_OOM,
+	AVB_AB_FLOW_RESULT_ERROR_IO,
+	AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS,
+	AVB_AB_FLOW_RESULT_ERROR_INVALID_ARGUMENT
+} AvbABFlowResult;
+
+/* High-level operations/functions/methods for A/B that are platform
+ * dependent.
+ */
+struct AvbABOps;
+typedef struct AvbABOps AvbABOps;
+
+struct AvbABOps {
+	/* Operations from libavb. */
+	AvbOps* ops;
+
+	/* Reads A/B metadata from persistent storage. Returned data is
+	 * properly byteswapped. Returns AVB_IO_RESULT_OK on success, error
+	 * code otherwise.
+	 *
+	 * If the data read is invalid (e.g. wrong magic or CRC checksum
+	 * failure), the metadata shoule be reset using fsl_avb_ab_data_init()
+	 * and then written to persistent storage.
+	 *
+	 * Implementations will typically want to use fsl_avb_ab_data_read()
+	 * here to use the 'misc' partition for persistent storage.
+	 */
+	AvbIOResult (*read_ab_metadata)(AvbABOps* ab_ops, struct bootloader_control* data);
+
+	/* Writes A/B metadata to persistent storage. This will byteswap and
+	 * update the CRC as needed. Returns AVB_IO_RESULT_OK on success,
+	 * error code otherwise.
+	 *
+	 * Implementations will typically want to use fsl_avb_ab_data_write()
+	 * here to use the 'misc' partition for persistent storage.
+	 */
+	AvbIOResult (*write_ab_metadata)(AvbABOps* ab_ops,
+					 const struct bootloader_control* data);
+};
+
+/* Copies |src| to |dest|, byte-swapping fields in the
+ * process. Returns false if the data is invalid (e.g. wrong magic,
+ * wrong CRC32 etc.), true otherwise.
+ */
+bool fsl_avb_ab_data_verify_and_byteswap(const struct bootloader_control* src,
+					 struct bootloader_control* dest);
+
+/* Copies |src| to |dest|, byte-swapping fields in the process. Also
+ * updates the |crc32| field in |dest|.
+ */
+void fsl_avb_ab_data_update_crc_and_byteswap(const struct bootloader_control* src,
+					     struct bootloader_control* dest);
+
+/* Initializes |data| such that it has two slots and both slots have
+ * maximum tries remaining. The CRC is not set.
+ */
+void fsl_avb_ab_data_init(struct bootloader_control* data);
+
+/* Reads A/B metadata from the 'misc' partition using |ops|. Returned
+ * data is properly byteswapped. Returns AVB_IO_RESULT_OK on
+ * success, error code otherwise.
+ *
+ * If the data read from disk is invalid (e.g. wrong magic or CRC
+ * checksum failure), the metadata will be reset using
+ * fsl_avb_ab_data_init() and then written to disk.
+ */
+AvbIOResult fsl_avb_ab_data_read(AvbABOps* ab_ops, struct bootloader_control* data);
+
+/* Writes A/B metadata to the 'misc' partition using |ops|. This will
+ * byteswap and update the CRC as needed. Returns AVB_IO_RESULT_OK on
+ * success, error code otherwise.
+ */
+AvbIOResult fsl_avb_ab_data_write(AvbABOps* ab_ops, const struct bootloader_control* data);
+
+/* True if the given slot is active, false otherwise.
+ * */
+bool fsl_slot_is_bootable(struct slot_metadata* slot);
+
+/* Mark one slot as active. */
+AvbIOResult fsl_avb_ab_mark_slot_active(AvbABOps* ab_ops,
+					unsigned int slot_number);
+
+/* This is the fast version of avb_ab_flow(), this function will
+ * not check another slot if one slot can pass the verify (or verify
+ * fail is acceptable).
+ */
+AvbABFlowResult avb_ab_flow_fast(AvbABOps* ab_ops,
+                                 const char* const* requested_partitions,
+                                 AvbSlotVerifyFlags flags,
+                                 AvbHashtreeErrorMode hashtree_error_mode,
+                                 AvbSlotVerifyData** out_data);
+
+/* This is for legacy i.mx6/7 which don't enable A/B but want to
+ * verify boot/recovery with AVB */
+AvbABFlowResult avb_single_flow(AvbABOps* ab_ops,
+                                 const char* const* requested_partitions,
+                                 AvbSlotVerifyFlags flags,
+                                 AvbHashtreeErrorMode hashtree_error_mode,
+                                 AvbSlotVerifyData** out_data);
+
+/* Avb verify flow for dual bootloader, only the slot chosen by SPL will
+ * be verified.
+ */
+AvbABFlowResult avb_flow_dual_uboot(AvbABOps* ab_ops,
+                                    const char* const* requested_partitions,
+                                    AvbSlotVerifyFlags flags,
+                                    AvbHashtreeErrorMode hashtree_error_mode,
+                                    AvbSlotVerifyData** out_data);
+
+/* check if the fastboot getvar cmd is for query [avb] bootctl's slot var
+ * cmd is the fastboot getvar's cmd in
+ * return true if it is a bootctl related cmd, false if it's not.
+ * */
+bool is_slotvar_avb(char *cmd);
+
+/* Get current bootable slot with higher priority.
+ * return 0 for the first slot
+ * return 1 for the second slot
+ * return -1 for not supported slot
+ * */
+int get_curr_slot(struct bootloader_control* ab_data);
+
+/* Get current bootable slot without passing the "bootloader_control" struct.
+ * return 0 for the first slot
+ * return 1 for the second slot
+ * return -1 for not supported slot
+ * */
+int current_slot(void);
+
+/* return 0 for the first slot
+ * return 1 for the second slot
+ * return -1 for not supported slot
+ * */
+int slotidx_from_suffix(char *suffix);
+
+/* return fastboot's getvar cmd response
+ * cmd is the fastboot getvar's cmd in
+ * if return 0, buffer is bootctl's slot var out
+ * if return -1, buffer is error string
+ * */
+
+/* read a/b metadata to get curr slot
+ * return slot suffix '_a'/'_b' or NULL */
+char *select_slot(AvbABOps *ab_ops);
+
+int get_slotvar_avb(AvbABOps *ab_ops, char *cmd, char *buffer, size_t size);
+
+#endif /* __FSL_BOOTCTRL_H__ */
diff --git a/lib/avb/fsl/fsl_public_key.h b/lib/avb/fsl/fsl_public_key.h
new file mode 100644
index 00000000000..b3b6d65a3cc
--- /dev/null
+++ b/lib/avb/fsl/fsl_public_key.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __FSL_PUBLIC_KEY_H_
+#define __FSL_PUBLIC_KEY_H_
+/*This public key is generated from testkey_rsa4096.pem.*/
+static unsigned char fsl_public_key[] = {
+	0x00,0x00,0x10,0x00,0x55,0xd9,0x04,0xad,
+	0xd8,0x04,0xaf,0xe3,0xd3,0x84,0x6c,0x7e,
+	0x0d,0x89,0x3d,0xc2,0x8c,0xd3,0x12,0x55,
+	0xe9,0x62,0xc9,0xf1,0x0f,0x5e,0xcc,0x16,
+	0x72,0xab,0x44,0x7c,0x2c,0x65,0x4a,0x94,
+	0xb5,0x16,0x2b,0x00,0xbb,0x06,0xef,0x13,
+	0x07,0x53,0x4c,0xf9,0x64,0xb9,0x28,0x7a,
+	0x1b,0x84,0x98,0x88,0xd8,0x67,0xa4,0x23,
+	0xf9,0xa7,0x4b,0xdc,0x4a,0x0f,0xf7,0x3a,
+	0x18,0xae,0x54,0xa8,0x15,0xfe,0xb0,0xad,
+	0xac,0x35,0xda,0x3b,0xad,0x27,0xbc,0xaf,
+	0xe8,0xd3,0x2f,0x37,0x34,0xd6,0x51,0x2b,
+	0x6c,0x5a,0x27,0xd7,0x96,0x06,0xaf,0x6b,
+	0xb8,0x80,0xca,0xfa,0x30,0xb4,0xb1,0x85,
+	0xb3,0x4d,0xaa,0xaa,0xc3,0x16,0x34,0x1a,
+	0xb8,0xe7,0xc7,0xfa,0xf9,0x09,0x77,0xab,
+	0x97,0x93,0xeb,0x44,0xae,0xcf,0x20,0xbc,
+	0xf0,0x80,0x11,0xdb,0x23,0x0c,0x47,0x71,
+	0xb9,0x6d,0xd6,0x7b,0x60,0x47,0x87,0x16,
+	0x56,0x93,0xb7,0xc2,0x2a,0x9a,0xb0,0x4c,
+	0x01,0x0c,0x30,0xd8,0x93,0x87,0xf0,0xed,
+	0x6e,0x8b,0xbe,0x30,0x5b,0xf6,0xa6,0xaf,
+	0xdd,0x80,0x7c,0x45,0x5e,0x8f,0x91,0x93,
+	0x5e,0x44,0xfe,0xb8,0x82,0x07,0xee,0x79,
+	0xca,0xbf,0x31,0x73,0x62,0x58,0xe3,0xcd,
+	0xc4,0xbc,0xc2,0x11,0x1d,0xa1,0x4a,0xbf,
+	0xfe,0x27,0x7d,0xa1,0xf6,0x35,0xa3,0x5e,
+	0xca,0xdc,0x57,0x2f,0x3e,0xf0,0xc9,0x5d,
+	0x86,0x6a,0xf8,0xaf,0x66,0xa7,0xed,0xcd,
+	0xb8,0xed,0xa1,0x5f,0xba,0x9b,0x85,0x1a,
+	0xd5,0x09,0xae,0x94,0x4e,0x3b,0xcf,0xcb,
+	0x5c,0xc9,0x79,0x80,0xf7,0xcc,0xa6,0x4a,
+	0xa8,0x6a,0xd8,0xd3,0x31,0x11,0xf9,0xf6,
+	0x02,0x63,0x2a,0x1a,0x2d,0xd1,0x1a,0x66,
+	0x1b,0x16,0x41,0xbd,0xbd,0xf7,0x4d,0xc0,
+	0x4a,0xe5,0x27,0x49,0x5f,0x7f,0x58,0xe3,
+	0x27,0x2d,0xe5,0xc9,0x66,0x0e,0x52,0x38,
+	0x16,0x38,0xfb,0x16,0xeb,0x53,0x3f,0xe6,
+	0xfd,0xe9,0xa2,0x5e,0x25,0x59,0xd8,0x79,
+	0x45,0xff,0x03,0x4c,0x26,0xa2,0x00,0x5a,
+	0x8e,0xc2,0x51,0xa1,0x15,0xf9,0x7b,0xf4,
+	0x5c,0x81,0x9b,0x18,0x47,0x35,0xd8,0x2d,
+	0x05,0xe9,0xad,0x0f,0x35,0x74,0x15,0xa3,
+	0x8e,0x8b,0xcc,0x27,0xda,0x7c,0x5d,0xe4,
+	0xfa,0x04,0xd3,0x05,0x0b,0xba,0x3a,0xb2,
+	0x49,0x45,0x2f,0x47,0xc7,0x0d,0x41,0x3f,
+	0x97,0x80,0x4d,0x3f,0xc1,0xb5,0xbb,0x70,
+	0x5f,0xa7,0x37,0xaf,0x48,0x22,0x12,0x45,
+	0x2e,0xf5,0x0f,0x87,0x92,0xe2,0x84,0x01,
+	0xf9,0x12,0x0f,0x14,0x15,0x24,0xce,0x89,
+	0x99,0xee,0xb9,0xc4,0x17,0x70,0x70,0x15,
+	0xea,0xbe,0xc6,0x6c,0x1f,0x62,0xb3,0xf4,
+	0x2d,0x16,0x87,0xfb,0x56,0x1e,0x45,0xab,
+	0xae,0x32,0xe4,0x5e,0x91,0xed,0x53,0x66,
+	0x5e,0xbd,0xed,0xad,0xe6,0x12,0x39,0x0d,
+	0x83,0xc9,0xe8,0x6b,0x6c,0x2d,0xa5,0xee,
+	0xc4,0x5a,0x66,0xae,0x8c,0x97,0xd7,0x0d,
+	0x6c,0x49,0xc7,0xf5,0xc4,0x92,0x31,0x8b,
+	0x09,0xee,0x33,0xda,0xa9,0x37,0xb6,0x49,
+	0x18,0xf8,0x0e,0x60,0x45,0xc8,0x33,0x91,
+	0xef,0x20,0x57,0x10,0xbe,0x78,0x2d,0x83,
+	0x26,0xd6,0xca,0x61,0xf9,0x2f,0xe0,0xbf,
+	0x05,0x30,0x52,0x5a,0x12,0x1c,0x00,0xa7,
+	0x5d,0xcc,0x7c,0x2e,0xc5,0x95,0x8b,0xa3,
+	0x3b,0xf0,0x43,0x2e,0x5e,0xdd,0x00,0xdb,
+	0x0d,0xb3,0x37,0x99,0xa9,0xcd,0x9c,0xb7,
+	0x43,0xf7,0x35,0x44,0x21,0xc2,0x82,0x71,
+	0xab,0x8d,0xaa,0xb4,0x41,0x11,0xec,0x1e,
+	0x8d,0xfc,0x14,0x82,0x92,0x4e,0x83,0x6a,
+	0x0a,0x6b,0x35,0x5e,0x5d,0xe9,0x5c,0xcc,
+	0x8c,0xde,0x39,0xd1,0x4a,0x5b,0x5f,0x63,
+	0xa9,0x64,0xe0,0x0a,0xcb,0x0b,0xb8,0x5a,
+	0x7c,0xc3,0x0b,0xe6,0xbe,0xfe,0x8b,0x0f,
+	0x7d,0x34,0x8e,0x02,0x66,0x74,0x01,0x6c,
+	0xca,0x76,0xac,0x7c,0x67,0x08,0x2f,0x3f,
+	0x1a,0xa6,0x2c,0x60,0xb3,0xff,0xda,0x8d,
+	0xb8,0x12,0x0c,0x00,0x7f,0xcc,0x50,0xa1,
+	0x5c,0x64,0xa1,0xe2,0x5f,0x32,0x65,0xc9,
+	0x9c,0xbe,0xd6,0x0a,0x13,0x87,0x3c,0x2a,
+	0x45,0x47,0x0c,0xca,0x42,0x82,0xfa,0x89,
+	0x65,0xe7,0x89,0xb4,0x8f,0xf7,0x1e,0xe6,
+	0x23,0xa5,0xd0,0x59,0x37,0x79,0x92,0xd7,
+	0xce,0x3d,0xfd,0xe3,0xa1,0x0b,0xcf,0x6c,
+	0x85,0xa0,0x65,0xf3,0x5c,0xc6,0x4a,0x63,
+	0x5f,0x6e,0x3a,0x3a,0x2a,0x8b,0x6a,0xb6,
+	0x2f,0xbb,0xf8,0xb2,0x4b,0x62,0xbc,0x1a,
+	0x91,0x25,0x66,0xe3,0x69,0xca,0x60,0x49,
+	0x0b,0xf6,0x8a,0xbe,0x3e,0x76,0x53,0xc2,
+	0x7a,0xa8,0x04,0x17,0x75,0xf1,0xf3,0x03,
+	0x62,0x1b,0x85,0xb2,0xb0,0xef,0x80,0x15,
+	0xb6,0xd4,0x4e,0xdf,0x71,0xac,0xdb,0x2a,
+	0x04,0xd4,0xb4,0x21,0xba,0x65,0x56,0x57,
+	0xe8,0xfa,0x84,0xa2,0x7d,0x13,0x0e,0xaf,
+	0xd7,0x9a,0x58,0x2a,0xa3,0x81,0x84,0x8d,
+	0x09,0xa0,0x6a,0xc1,0xbb,0xd9,0xf5,0x86,
+	0xac,0xbd,0x75,0x61,0x09,0xe6,0x8c,0x3d,
+	0x77,0xb2,0xed,0x30,0x20,0xe4,0x00,0x1d,
+	0x97,0xe8,0xbf,0xc7,0x00,0x1b,0x21,0xb1,
+	0x16,0xe7,0x41,0x67,0x2e,0xec,0x38,0xbc,
+	0xe5,0x1b,0xb4,0x06,0x23,0x31,0x71,0x1c,
+	0x49,0xcd,0x76,0x4a,0x76,0x36,0x8d,0xa3,
+	0x89,0x8b,0x4a,0x7a,0xf4,0x87,0xc8,0x15,
+	0x0f,0x37,0x39,0xf6,0x6d,0x80,0x19,0xef,
+	0x5c,0xa8,0x66,0xce,0x1b,0x16,0x79,0x21,
+	0xdf,0xd7,0x31,0x30,0xc4,0x21,0xdd,0x34,
+	0x5b,0xd2,0x1a,0x2b,0x3e,0x5d,0xf7,0xea,
+	0xca,0x05,0x8e,0xb7,0xcb,0x49,0x2e,0xa0,
+	0xe3,0xf4,0xa7,0x48,0x19,0x10,0x9c,0x04,
+	0xa7,0xf4,0x28,0x74,0xc8,0x6f,0x63,0x20,
+	0x2b,0x46,0x24,0x26,0x19,0x1d,0xd1,0x2c,
+	0x31,0x6d,0x5a,0x29,0xa2,0x06,0xa6,0xb2,
+	0x41,0xcc,0x0a,0x27,0x96,0x09,0x96,0xac,
+	0x47,0x65,0x78,0x68,0x51,0x98,0xd6,0xd8,
+	0xa6,0x2d,0xa0,0xcf,0xec,0xe2,0x74,0xf2,
+	0x82,0xe3,0x97,0xd9,0x7e,0xd4,0xf8,0x0b,
+	0x70,0x43,0x3d,0xb1,0x7b,0x97,0x80,0xd6,
+	0xcb,0xd7,0x19,0xbc,0x63,0x0b,0xfd,0x4d,
+	0x88,0xfe,0x67,0xac,0xb8,0xcc,0x50,0xb7,
+	0x68,0xb3,0x5b,0xd6,0x1e,0x25,0xfc,0x5f,
+	0x3c,0x8d,0xb1,0x33,0x7c,0xb3,0x49,0x01,
+	0x3f,0x71,0x55,0x0e,0x51,0xba,0x61,0x26,
+	0xfa,0xea,0xe5,0xb5,0xe8,0xaa,0xcf,0xcd,
+	0x96,0x9f,0xd6,0xc1,0x5f,0x53,0x91,0xad,
+	0x05,0xde,0x20,0xe7,0x51,0xda,0x5b,0x95,
+	0x67,0xed,0xf4,0xee,0x42,0x65,0x70,0x13,
+	0x0b,0x70,0x14,0x1c,0xc9,0xe0,0x19,0xca,
+	0x5f,0xf5,0x1d,0x70,0x4b,0x6c,0x06,0x74,
+	0xec,0xb5,0x2e,0x77,0xe1,0x74,0xa1,0xa3,
+	0x99,0xa0,0x85,0x9e,0xf1,0xac,0xd8,0x7e
+};
+
+
+#endif
diff --git a/lib/avb/fsl/orange_warning_bmp_data.c b/lib/avb/fsl/orange_warning_bmp_data.c
new file mode 100644
index 00000000000..49f04bbc59f
--- /dev/null
+++ b/lib/avb/fsl/orange_warning_bmp_data.c
@@ -0,0 +1,1066 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright NXP 2020
+ *
+ */
+
+/*
+ * Note:  The orange_warning_bmp_palette[] and orange_warning_bmp_bitmap
+ * data are generated by "tools/bmp_logo", command:
+ * "./bmp_logo --gen-bmp source.bmp > bmp_data.c"
+ * */
+
+#include "fsl_avb_logo.h"
+
+unsigned short orange_warning_bmp_palette[] = {
+	0x0000,  0x0233,  0x072E,  0x0E72,  0x02E7,  0x072E,  0x0E72,  0x02E7,
+	0x072E,  0x0E72,  0x02E7,  0x072E,  0x0E72,  0x02E7,  0x072E,  0x0E72,
+	0x02E7,  0x072E,  0x0E72,  0x02E7,  0x072E,  0x0E72,  0x02E7,  0x072E,
+	0x0E72,  0x02E7,  0x072E,  0x0E72,  0x02E7,  0x072E,  0x0E72,  0x02E7,
+	0x072E,  0x0E72,  0x02E7,  0x072E,  0x0E72,  0x02E7,  0x072E,  0x0E72,
+	0x01E7,  0x0207,  0x0000,  0x02C6,  0x072F,  0x0F72,  0x02F7,  0x072F,
+	0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,
+	0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,
+	0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,
+	0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,
+	0x072F,  0x0F72,  0x02F7,  0x030F,  0x0000,  0x0211,  0x072F,  0x0F72,
+	0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,
+	0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,
+	0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,
+	0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,
+	0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x000E,  0x0000,  0x0000,
+	0x0824,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,
+	0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,
+	0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,
+	0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,
+	0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x00F8,  0x0002,
+	0x0000,  0x0000,  0x0720,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,
+	0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,
+	0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,
+	0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,
+	0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,
+	0x00D7,  0x0000,  0x0000,  0x0000,  0x0100,  0x0F82,  0x02F7,  0x072F,
+	0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,
+	0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,
+	0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,  0x0F72,  0x02F7,  0x072F,
+
+};
+
+unsigned char orange_warning_bmp_bitmap[] = {
+	0x42, 0x4D, 0xB6, 0x1F, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x28, 0x00,
+	0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x30, 0x00,
+	0x00, 0x00, 0x01, 0x00, 0x18, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC4, 0x0E,
+	0x00, 0x00, 0xC4, 0x0E, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05,
+	0x05, 0x0C, 0x30, 0x34, 0x24, 0x7A, 0xE3, 0x25,
+	0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA,
+	0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D,
+	0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25,
+	0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA,
+	0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D,
+	0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25,
+	0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA,
+	0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D,
+	0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25,
+	0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA,
+	0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D,
+	0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25,
+	0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA,
+	0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D,
+	0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25,
+	0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA,
+	0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D,
+	0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25,
+	0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA,
+	0x1B, 0x6C, 0x75, 0x0C, 0x2E, 0x33, 0x01, 0x05,
+	0x06, 0x20, 0x6E, 0xC7, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x80, 0xFE, 0x0E, 0x36, 0x3A, 0x00, 0x00,
+	0x00, 0x06, 0x16, 0x18, 0x26, 0x7F, 0xF1, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x25, 0x7B, 0xE6, 0x03, 0x0D, 0x0E, 0x00, 0x00,
+	0x00, 0x01, 0x03, 0x03, 0x0F, 0x3E, 0x43, 0x27,
+	0x80, 0xFE, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x80, 0xFD,
+	0x0A, 0x26, 0x2A, 0x00, 0x01, 0x01, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x03, 0x0C, 0x0D, 0x24,
+	0x79, 0xDF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x22, 0x73, 0xD2,
+	0x02, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x08,
+	0x1E, 0x20, 0x27, 0x81, 0xFC, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x80, 0xF6, 0x07, 0x1D, 0x1F,
+	0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x06, 0x06, 0x22, 0x73, 0xD3, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x1D, 0x64, 0xB5, 0x01, 0x04, 0x04,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x08, 0x20, 0x23, 0x26, 0x80, 0xF3,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x26,
+	0x80, 0xF2, 0x03, 0x0C, 0x0C, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x01, 0x06, 0x07, 0x11, 0x42, 0x47,
+	0x27, 0x80, 0xFE, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x1E, 0x67, 0xBA, 0x13,
+	0x3E, 0x75, 0x12, 0x3E, 0x74, 0x13, 0x3F, 0x76,
+	0x21, 0x70, 0xCD, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x80, 0xFD, 0x0C,
+	0x30, 0x33, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x01, 0x05, 0x16, 0x17,
+	0x26, 0x7E, 0xEC, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x80, 0xFE, 0x0C, 0x2F, 0x34, 0x00,
+	0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01,
+	0x12, 0x45, 0x4A, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x24, 0x79, 0xE0, 0x03,
+	0x0D, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05, 0x05,
+	0x0D, 0x34, 0x38, 0x27, 0x81, 0xFC, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x80, 0xFE, 0x0C, 0x2F, 0x34, 0x00,
+	0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01,
+	0x12, 0x45, 0x4A, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x81, 0xFB, 0x09, 0x25, 0x28, 0x00,
+	0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x04, 0x0F, 0x10, 0x23, 0x77, 0xDA, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x80, 0xFE, 0x0C, 0x2F, 0x34, 0x00,
+	0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01,
+	0x12, 0x45, 0x4A, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x22, 0x74, 0xD4, 0x01, 0x05, 0x05, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x06, 0x17, 0x19, 0x27, 0x81,
+	0xFA, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x25, 0x7B, 0xE5, 0x22,
+	0x72, 0xCF, 0x22, 0x71, 0xCF, 0x22, 0x72, 0xCF,
+	0x26, 0x7F, 0xF1, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x26, 0x7E,
+	0xED, 0x05, 0x12, 0x13, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x14, 0x4F,
+	0x56, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x0C, 0x30,
+	0x34, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x19,
+	0x1C, 0x26, 0x7F, 0xEF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x26, 0x7D, 0xEB, 0x02, 0x06,
+	0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05,
+	0x05, 0x0F, 0x3C, 0x42, 0x27, 0x80, 0xFE, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x80, 0xFD, 0x0B, 0x2A, 0x2E, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x04, 0x10, 0x12, 0x25, 0x7B, 0xE6, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x22, 0x73, 0xD1, 0x01, 0x07, 0x08, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x01, 0x01, 0x0A, 0x2A, 0x2D, 0x27,
+	0x81, 0xFA, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x81, 0xFC, 0x27,
+	0x81, 0xF7, 0x27, 0x81, 0xF7, 0x27, 0x81, 0xF7,
+	0x27, 0x80, 0xFD, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x81, 0xF8,
+	0x08, 0x21, 0x23, 0x00, 0x01, 0x01, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x02, 0x07, 0x08, 0x22,
+	0x73, 0xD1, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x12, 0x46, 0x4C, 0x07,
+	0x1C, 0x1F, 0x07, 0x1B, 0x1E, 0x07, 0x1D, 0x1F,
+	0x23, 0x75, 0xD6, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x12, 0x46, 0x4B,
+	0x01, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06,
+	0x16, 0x18, 0x27, 0x81, 0xF9, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x80, 0xFE, 0x0C, 0x30, 0x35, 0x00,
+	0x02, 0x02, 0x00, 0x01, 0x01, 0x01, 0x02, 0x02,
+	0x12, 0x45, 0x4B, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x26, 0x7F, 0xEF, 0x04, 0x10, 0x11,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x02, 0x02, 0x10, 0x3F, 0x45, 0x27, 0x80, 0xFE,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x80, 0xFE, 0x0C, 0x2F, 0x34, 0x00,
+	0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01,
+	0x12, 0x45, 0x4A, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x80, 0xFE, 0x0A, 0x26, 0x29, 0x00, 0x01, 0x02,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x04, 0x13, 0x15, 0x26, 0x7E, 0xEB,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x80, 0xFE, 0x0C, 0x2F, 0x34, 0x00,
+	0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01,
+	0x12, 0x45, 0x4A, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x24,
+	0x7B, 0xE3, 0x02, 0x08, 0x09, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x01, 0x05, 0x05, 0x0D, 0x34, 0x38,
+	0x27, 0x80, 0xFD, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x80, 0xFE, 0x0C, 0x2F, 0x34, 0x00,
+	0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01,
+	0x12, 0x45, 0x4A, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x81, 0xFA, 0x0A,
+	0x25, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x01, 0x04, 0x0F, 0x10,
+	0x24, 0x7B, 0xE4, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x80, 0xFE, 0x0C, 0x2F, 0x34, 0x00,
+	0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01,
+	0x12, 0x45, 0x4A, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x22, 0x73, 0xD2, 0x02,
+	0x07, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01,
+	0x08, 0x1F, 0x22, 0x27, 0x81, 0xF9, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x80, 0xFE, 0x0C, 0x2F, 0x34, 0x00,
+	0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01,
+	0x12, 0x45, 0x4A, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x26, 0x7F, 0xF2, 0x05, 0x13, 0x14, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x01, 0x06, 0x06, 0x20, 0x6B, 0xC2, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x80, 0xFE, 0x0C, 0x2F, 0x34, 0x00,
+	0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01,
+	0x12, 0x45, 0x4A, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x0F, 0x3B, 0x40, 0x01, 0x04, 0x04, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x04, 0x11, 0x12, 0x26, 0x80,
+	0xF2, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x80, 0xFE, 0x0E, 0x3A, 0x3F, 0x03,
+	0x0E, 0x0F, 0x03, 0x0D, 0x0E, 0x03, 0x0E, 0x0F,
+	0x21, 0x71, 0xCE, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x24, 0x7A,
+	0xE3, 0x04, 0x0D, 0x0E, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x10, 0x3F,
+	0x45, 0x27, 0x80, 0xFE, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x26, 0x7F, 0xF0, 0x25,
+	0x7B, 0xE4, 0x25, 0x7B, 0xE4, 0x25, 0x7B, 0xE4,
+	0x27, 0x81, 0xF8, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x80, 0xFE, 0x09, 0x23,
+	0x26, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x10,
+	0x11, 0x25, 0x7B, 0xE4, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x23, 0x75, 0xD6, 0x01, 0x02,
+	0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03,
+	0x03, 0x0B, 0x2B, 0x2E, 0x27, 0x81, 0xFB, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x81, 0xF7, 0x08, 0x20, 0x23, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x03, 0x0C, 0x0C, 0x23, 0x76, 0xD9, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x20, 0x6D, 0xC6, 0x01, 0x06, 0x07, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x01, 0x02, 0x09, 0x25, 0x29, 0x27,
+	0x80, 0xF5, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F,
+	0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x26, 0x80, 0xF2,
+	0x04, 0x12, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x27, 0x81, 0xFA, 0x06, 0x18,
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+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x27, 0x7F, 0xFF, 0x21, 0x6F, 0xCA, 0x01, 0x02,
+	0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+	0x02, 0x09, 0x23, 0x26, 0x27, 0x81, 0xF7, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF,
+	0x26, 0x80, 0xF2, 0x05, 0x15, 0x16, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x01, 0x07, 0x07, 0x11, 0x43, 0x48, 0x27,
+	0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x80, 0xFE,
+	0x0D, 0x32, 0x36, 0x01, 0x02, 0x02, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x05, 0x13, 0x14, 0x26,
+	0x7E, 0xED, 0x27, 0x7F, 0xFF, 0x25, 0x7C, 0xE6,
+	0x04, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x02, 0x0C,
+	0x2F, 0x32, 0x25, 0x7C, 0xE8, 0x0A, 0x27, 0x2B,
+	0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+	0x08, 0x09, 0x05, 0x13, 0x14, 0x01, 0x04, 0x04,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+};
+
diff --git a/lib/avb/fsl/utils.c b/lib/avb/fsl/utils.c
new file mode 100644
index 00000000000..52ac1bd2a1c
--- /dev/null
+++ b/lib/avb/fsl/utils.c
@@ -0,0 +1,216 @@
+/*
++ * Copyright (C) 2016 Freescale Semiconductor, Inc.
++ * Copyright 2018 NXP
++ *
++ * SPDX-License-Identifier:     GPL-2.0+
++ */
+#include <common.h>
+#include <stdlib.h>
+#include <part.h>
+
+#include "debug.h"
+#include "utils.h"
+
+/*
+ * get margin_pos struct from offset [to the partition start/end] and
+ * num_bytes to read/write
+ */
+int get_margin_pos(long part_start, long part_end, long blksz,
+		   margin_pos_t *margin, long offset, size_t num_bytes,
+		   bool allow_partial) {
+	long off;
+	if (margin == NULL)
+		return -1;
+
+	if (blksz == 0 || part_start > part_end)
+		return -1;
+
+	if (offset < 0) {
+		margin->blk_start = (offset + 1) / blksz + part_end;
+ 		// offset == -1 means the last byte?, or start need -1
+		margin->start = (off = offset % blksz) == 0 ?
+			        0 : blksz + off;
+		if (offset + num_bytes - 1 >= 0) {
+			if (!allow_partial)
+				return -1;
+			margin->blk_end = part_end;
+			margin->end = blksz - 1;
+		} else {
+ 			// which blk the last byte is in
+			margin->blk_end = (num_bytes + offset) /
+					  blksz + part_end;
+			margin->end = (off = (num_bytes + offset - 1) % blksz) == 0 ?
+				      0 : blksz + off; // last byte
+		}
+	} else {
+		margin->blk_start = offset / blksz + part_start;
+		margin->start = offset % blksz;
+		margin->blk_end = ((offset + num_bytes - 1) / blksz) +
+				  part_start ;
+		margin->end = (offset + num_bytes - 1) % blksz;
+		if (margin->blk_end > part_end) {
+			if (!allow_partial)
+				return -1;
+			margin->blk_end = part_end;
+			margin->end = blksz - 1;
+		}
+	}
+	VDEBUG("bs=%ld, be=%ld, s=%ld, e=%ld\n",
+	       margin->blk_start, margin->blk_end, margin->start, margin->end);
+
+	if (margin->blk_start > part_end || margin->blk_start < part_start)
+		return -1;
+	long multi = margin->blk_end - margin->blk_start - 1 +
+		    (margin->start == 0) + (margin->end == blksz -1);
+	margin->multi = multi > 0 ? multi : 0;
+	VDEBUG("bm=%ld\n", margin->multi);
+	return 0;
+}
+
+int read_from_partition_in_bytes(struct blk_desc *fs_dev_desc,
+				 struct disk_partition *info, int64_t offset,
+				 size_t num_bytes, void* buffer,
+				 size_t* out_num_read)
+{
+	unsigned char *bdata;
+	unsigned char *out_buf = (unsigned char *)buffer;
+	unsigned char *dst, *dst64 = NULL;
+	unsigned long blksz;
+	unsigned long s, cnt;
+	size_t num_read = 0;
+	lbaint_t part_start, part_end, bs, be, bm, blk_num;
+	margin_pos_t margin;
+	int ret;
+
+	if(buffer == NULL || out_num_read == NULL) {
+		printf("NULL pointer error!\n");
+		return -1;
+	}
+
+	blksz = fs_dev_desc->blksz;
+	part_start = info->start;
+	part_end = info->start + info->size - 1;
+
+	if (get_margin_pos((uint64_t)part_start, (uint64_t)part_end, blksz,
+			   &margin, offset, num_bytes, true))
+		return -1;
+
+	bs = (lbaint_t)margin.blk_start;
+	be = (lbaint_t)margin.blk_end;
+	s = margin.start;
+	bm = margin.multi;
+
+	/* alloc a blksz mem */
+	bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz);
+	if (bdata == NULL) {
+		printf("Failed to allocate memory!\n");
+		return -1;
+	}
+
+	/* support multi blk read */
+	while (bs <= be) {
+		if (!s && bm > 1) {
+			dst = out_buf;
+ 			/* for mmc blk read alignment */
+			dst64 = PTR_ALIGN(out_buf, 64);
+			if (dst64 != dst) {
+				dst = dst64;
+				bm--;
+			}
+			blk_num = bm;
+			cnt = bm * blksz;
+			bm = 0; /* no more multi blk */
+		} else {
+			blk_num = 1;
+			cnt = blksz - s;
+			if (num_read + cnt > num_bytes)
+				cnt = num_bytes - num_read;
+			dst = bdata;
+		}
+		if (!blk_dread(fs_dev_desc, bs, blk_num, dst)) {
+			ret = -1;
+			goto fail;
+		}
+
+		if (dst == bdata)
+			memcpy(out_buf, bdata + s, cnt);
+		else if (dst == dst64)
+			memcpy(out_buf, dst, cnt); /* internal copy */
+
+		s = 0;
+		bs += blk_num;
+		num_read += cnt;
+		out_buf += cnt;
+	}
+	*out_num_read = num_read;
+	ret = 0;
+
+fail:
+	free(bdata);
+	return ret;
+}
+
+int write_to_partition_in_bytes(struct blk_desc *fs_dev_desc,
+				struct disk_partition *info, int64_t offset,
+				size_t num_bytes,
+				void* buffer, size_t *out_num_write)
+{
+	unsigned char *bdata;
+	unsigned char *in_buf = (unsigned char *)buffer;
+	unsigned long blksz;
+	unsigned long s, cnt;
+	size_t num_write = 0;
+	lbaint_t part_start, part_end, bs;
+	margin_pos_t margin;
+	int ret;
+
+	if(buffer == NULL || out_num_write == NULL) {
+		printf("NULL pointer error!\n");
+		return -1;
+	}
+
+	blksz = fs_dev_desc->blksz;
+	part_start = info->start;
+	part_end = info->start + info->size - 1;
+
+	if(get_margin_pos((uint64_t)part_start, (uint64_t)part_end, blksz,
+			  &margin, offset, num_bytes, false))
+		return -1;
+
+	bs = (lbaint_t)margin.blk_start;
+	s = margin.start;
+
+	// alloc a blksz mem
+	bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz);
+	if (bdata == NULL)
+		return -1;
+
+	while (num_write < num_bytes) {
+		memset(bdata, 0, blksz);
+		cnt = blksz - s;
+		if (num_write + cnt >  num_bytes)
+			cnt = num_bytes - num_write;
+		if (!s || cnt != blksz) { //read blk first
+			if (!blk_dread(fs_dev_desc, bs, 1,
+						     bdata)) {
+				ret = -1;
+				goto fail;
+			}
+		}
+		memcpy(bdata + s, in_buf, cnt); //change data
+		if (!blk_dwrite(fs_dev_desc, bs, 1, bdata)) {
+			ret = -1;
+			goto fail;
+		}
+		bs++;
+		num_write += cnt;
+		in_buf += cnt;
+		s = 0;
+	}
+	*out_num_write = num_write;
+	ret = 0;
+
+fail:
+	free(bdata);
+	return ret;
+}
diff --git a/lib/avb/fsl/utils.h b/lib/avb/fsl/utils.h
new file mode 100644
index 00000000000..60172a71e33
--- /dev/null
+++ b/lib/avb/fsl/utils.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#ifndef __UTILS_H__
+#define __UTILS_H__
+
+#include <common.h>
+
+#define ALIGN_BYTES 64 /*mmc block read/write need 64 bytes aligned */
+
+struct margin_pos {
+	/* which blk the read/write starts */
+	uint64_t blk_start;
+	/* which blk the read/write ends */
+	uint64_t blk_end;
+	/* start position inside the start blk */
+	unsigned long start;
+	/* end position inside the end blk */
+	unsigned long end;
+	/* how many blks can be read/write one time */
+	unsigned long multi;
+};
+typedef struct margin_pos margin_pos_t;
+
+int get_margin_pos(long part_start, long part_end, long blksz,
+		   margin_pos_t *margin, long offset, size_t num_bytes,
+		   bool allow_partial);
+
+int read_from_partition_in_bytes(struct blk_desc *fs_dev_desc,
+				 struct disk_partition *info,
+				 int64_t offset, size_t num_bytes,
+		void* buffer, size_t* out_num_read);
+
+int write_to_partition_in_bytes(struct blk_desc *fs_dev_desc,
+				struct disk_partition *info, int64_t offset,
+				size_t num_bytes, void* buffer,
+				size_t *out_num_write);
+
+#endif
diff --git a/lib/avb/libavb_atx/Makefile b/lib/avb/libavb_atx/Makefile
new file mode 100644
index 00000000000..bdd7bccbeb0
--- /dev/null
+++ b/lib/avb/libavb_atx/Makefile
@@ -0,0 +1,2 @@
+ccflags-y += -DAVB_COMPILATION
+obj-y += avb_atx_validate.o
diff --git a/lib/avb/libavb_atx/avb_atx_ops.h b/lib/avb/libavb_atx/avb_atx_ops.h
new file mode 100644
index 00000000000..e7bd686f3d7
--- /dev/null
+++ b/lib/avb/libavb_atx/avb_atx_ops.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#if !defined(AVB_INSIDE_LIBAVB_ATX_H) && !defined(AVB_COMPILATION)
+#error \
+    "Never include this file directly, include libavb_atx/libavb_atx.h instead."
+#endif
+
+#ifndef AVB_ATX_OPS_H_
+#define AVB_ATX_OPS_H_
+
+#include <../lib/libavb/libavb.h>
+
+#include "avb_atx_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct AvbAtxOps;
+typedef struct AvbAtxOps AvbAtxOps;
+
+/* An extension to AvbOps required by avb_atx_validate_vbmeta_public_key(). */
+struct AvbAtxOps {
+  /* Operations from libavb. */
+  AvbOps* ops;
+
+  /* Reads permanent |attributes| data. There are no restrictions on where this
+   * data is stored. On success, returns AVB_IO_RESULT_OK and populates
+   * |attributes|.
+   */
+  AvbIOResult (*read_permanent_attributes)(
+      AvbAtxOps* atx_ops, AvbAtxPermanentAttributes* attributes);
+
+  /* Reads a |hash| of permanent attributes. This hash MUST be retrieved from a
+   * permanently read-only location (e.g. fuses) when a device is LOCKED. On
+   * success, returned AVB_IO_RESULT_OK and populates |hash|.
+   */
+  AvbIOResult (*read_permanent_attributes_hash)(
+      AvbAtxOps* atx_ops, uint8_t hash[AVB_SHA256_DIGEST_SIZE]);
+
+  /* Provides the key version of a key used during verification. This may be
+   * useful for managing the minimum key version.
+   */
+  void (*set_key_version)(AvbAtxOps* atx_ops,
+                          size_t rollback_index_location,
+                          uint64_t key_version);
+
+  /* Generates |num_bytes| random bytes and stores them in |output|,
+   * which must point to a buffer large enough to store the bytes.
+   *
+   * Returns AVB_IO_RESULT_OK on success, otherwise an error code.
+   */
+  AvbIOResult (*get_random)(AvbAtxOps* atx_ops,
+                            size_t num_bytes,
+                            uint8_t* output);
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* AVB_ATX_OPS_H_ */
diff --git a/lib/avb/libavb_atx/avb_atx_types.h b/lib/avb/libavb_atx/avb_atx_types.h
new file mode 100644
index 00000000000..a4563c0d080
--- /dev/null
+++ b/lib/avb/libavb_atx/avb_atx_types.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#if !defined(AVB_INSIDE_LIBAVB_ATX_H) && !defined(AVB_COMPILATION)
+#error \
+    "Never include this file directly, include libavb_atx/libavb_atx.h instead."
+#endif
+
+#ifndef AVB_ATX_TYPES_H_
+#define AVB_ATX_TYPES_H_
+
+#include <../lib/libavb/libavb.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Size in bytes of an Android Things product ID. */
+#define AVB_ATX_PRODUCT_ID_SIZE 16
+
+/* Size in bytes of an Android Things unlock challenge. */
+#define AVB_ATX_UNLOCK_CHALLENGE_SIZE 16
+
+/* Size in bytes of a serialized public key with a 4096-bit modulus. */
+#define AVB_ATX_PUBLIC_KEY_SIZE (sizeof(AvbRSAPublicKeyHeader) + 1024)
+
+/* Data structure of Android Things permanent attributes. */
+typedef struct AvbAtxPermanentAttributes {
+  uint32_t version;
+  uint8_t product_root_public_key[AVB_ATX_PUBLIC_KEY_SIZE];
+  uint8_t product_id[AVB_ATX_PRODUCT_ID_SIZE];
+} AVB_ATTR_PACKED AvbAtxPermanentAttributes;
+
+/* Data structure of signed fields in an Android Things certificate. */
+typedef struct AvbAtxCertificateSignedData {
+  uint32_t version;
+  uint8_t public_key[AVB_ATX_PUBLIC_KEY_SIZE];
+  uint8_t subject[AVB_SHA256_DIGEST_SIZE];
+  uint8_t usage[AVB_SHA256_DIGEST_SIZE];
+  uint64_t key_version;
+} AVB_ATTR_PACKED AvbAtxCertificateSignedData;
+
+/* Data structure of an Android Things certificate. */
+typedef struct AvbAtxCertificate {
+  AvbAtxCertificateSignedData signed_data;
+  uint8_t signature[AVB_RSA4096_NUM_BYTES];
+} AVB_ATTR_PACKED AvbAtxCertificate;
+
+/* Data structure of Android Things public key metadata in vbmeta. */
+typedef struct AvbAtxPublicKeyMetadata {
+  uint32_t version;
+  AvbAtxCertificate product_intermediate_key_certificate;
+  AvbAtxCertificate product_signing_key_certificate;
+} AVB_ATTR_PACKED AvbAtxPublicKeyMetadata;
+
+/* Data structure of an Android Things unlock challenge. */
+typedef struct AvbAtxUnlockChallenge {
+  uint32_t version;
+  uint8_t product_id_hash[AVB_SHA256_DIGEST_SIZE];
+  uint8_t challenge[AVB_ATX_UNLOCK_CHALLENGE_SIZE];
+} AVB_ATTR_PACKED AvbAtxUnlockChallenge;
+
+/* Data structure of an Android Things unlock credential. */
+typedef struct AvbAtxUnlockCredential {
+  uint32_t version;
+  AvbAtxCertificate product_intermediate_key_certificate;
+  AvbAtxCertificate product_unlock_key_certificate;
+  uint8_t challenge_signature[AVB_RSA4096_NUM_BYTES];
+} AVB_ATTR_PACKED AvbAtxUnlockCredential;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* AVB_ATX_TYPES_H_ */
diff --git a/lib/avb/libavb_atx/avb_atx_validate.c b/lib/avb/libavb_atx/avb_atx_validate.c
new file mode 100644
index 00000000000..f3c1d968412
--- /dev/null
+++ b/lib/avb/libavb_atx/avb_atx_validate.c
@@ -0,0 +1,401 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "avb_atx_validate.h"
+
+#include <libavb/avb_rsa.h>
+#include <libavb/avb_sha.h>
+#include <libavb/avb_sysdeps.h>
+#include <libavb/avb_util.h>
+
+/* The most recent unlock challenge generated. */
+static uint8_t last_unlock_challenge[AVB_ATX_UNLOCK_CHALLENGE_SIZE];
+
+/* Computes the SHA256 |hash| of |length| bytes of |data|. */
+static void sha256(const uint8_t* data,
+                   uint32_t length,
+                   uint8_t hash[AVB_SHA256_DIGEST_SIZE]) {
+  AvbSHA256Ctx context;
+  avb_sha256_init(&context);
+  avb_sha256_update(&context, data, length);
+  uint8_t* tmp = avb_sha256_final(&context);
+  avb_memcpy(hash, tmp, AVB_SHA256_DIGEST_SIZE);
+}
+
+/* Computes the SHA512 |hash| of |length| bytes of |data|. */
+static void sha512(const uint8_t* data,
+                   uint32_t length,
+                   uint8_t hash[AVB_SHA512_DIGEST_SIZE]) {
+  AvbSHA512Ctx context;
+  avb_sha512_init(&context);
+  avb_sha512_update(&context, data, length);
+  uint8_t* tmp = avb_sha512_final(&context);
+  avb_memcpy(hash, tmp, AVB_SHA512_DIGEST_SIZE);
+}
+
+/* Computes the SHA256 |hash| of a NUL-terminated |str|. */
+static void sha256_str(const char* str, uint8_t hash[AVB_SHA256_DIGEST_SIZE]) {
+  sha256((const uint8_t*)str, avb_strlen(str), hash);
+}
+
+/* Verifies structure and |expected_hash| of permanent |attributes|. */
+static bool verify_permanent_attributes(
+    const AvbAtxPermanentAttributes* attributes,
+    const uint8_t expected_hash[AVB_SHA256_DIGEST_SIZE]) {
+  uint8_t hash[AVB_SHA256_DIGEST_SIZE];
+
+  if (attributes->version != 1) {
+    avb_error("Unsupported permanent attributes version.\n");
+    return false;
+  }
+  sha256((const uint8_t*)attributes, sizeof(AvbAtxPermanentAttributes), hash);
+  if (0 != avb_safe_memcmp(hash, expected_hash, AVB_SHA256_DIGEST_SIZE)) {
+    avb_error("Invalid permanent attributes.\n");
+    return false;
+  }
+  return true;
+}
+
+/* Verifies the format, key version, usage, and signature of a certificate. */
+static bool verify_certificate(
+    const AvbAtxCertificate* certificate,
+    const uint8_t authority[AVB_ATX_PUBLIC_KEY_SIZE],
+    uint64_t minimum_key_version,
+    const uint8_t expected_usage[AVB_SHA256_DIGEST_SIZE]) {
+  const AvbAlgorithmData* algorithm_data;
+  uint8_t certificate_hash[AVB_SHA512_DIGEST_SIZE];
+
+  if (certificate->signed_data.version != 1) {
+    avb_error("Unsupported certificate format.\n");
+    return false;
+  }
+  algorithm_data = avb_get_algorithm_data(AVB_ALGORITHM_TYPE_SHA512_RSA4096);
+  sha512((const uint8_t*)&certificate->signed_data,
+         sizeof(AvbAtxCertificateSignedData),
+         certificate_hash);
+  if (!avb_rsa_verify(authority,
+                      AVB_ATX_PUBLIC_KEY_SIZE,
+                      certificate->signature,
+                      AVB_RSA4096_NUM_BYTES,
+                      certificate_hash,
+                      AVB_SHA512_DIGEST_SIZE,
+                      algorithm_data->padding,
+                      algorithm_data->padding_len)) {
+    avb_error("Invalid certificate signature.\n");
+    return false;
+  }
+  if (certificate->signed_data.key_version < minimum_key_version) {
+    avb_error("Key rollback detected.\n");
+    return false;
+  }
+  if (0 != avb_safe_memcmp(certificate->signed_data.usage,
+                           expected_usage,
+                           AVB_SHA256_DIGEST_SIZE)) {
+    avb_error("Invalid certificate usage.\n");
+    return false;
+  }
+  return true;
+}
+
+/* Verifies signature and fields of a PIK certificate. */
+static bool verify_pik_certificate(
+    const AvbAtxCertificate* certificate,
+    const uint8_t authority[AVB_ATX_PUBLIC_KEY_SIZE],
+    uint64_t minimum_version) {
+  uint8_t expected_usage[AVB_SHA256_DIGEST_SIZE];
+
+  sha256_str("com.google.android.things.vboot.ca", expected_usage);
+  if (!verify_certificate(
+          certificate, authority, minimum_version, expected_usage)) {
+    avb_error("Invalid PIK certificate.\n");
+    return false;
+  }
+  return true;
+}
+
+/* Verifies signature and fields of a PSK certificate. */
+static bool verify_psk_certificate(
+    const AvbAtxCertificate* certificate,
+    const uint8_t authority[AVB_ATX_PUBLIC_KEY_SIZE],
+    uint64_t minimum_version,
+    const uint8_t product_id[AVB_ATX_PRODUCT_ID_SIZE]) {
+  uint8_t expected_subject[AVB_SHA256_DIGEST_SIZE];
+  uint8_t expected_usage[AVB_SHA256_DIGEST_SIZE];
+
+  sha256_str("com.google.android.things.vboot", expected_usage);
+  if (!verify_certificate(
+          certificate, authority, minimum_version, expected_usage)) {
+    avb_error("Invalid PSK certificate.\n");
+    return false;
+  }
+  sha256(product_id, AVB_ATX_PRODUCT_ID_SIZE, expected_subject);
+  if (0 != avb_safe_memcmp(certificate->signed_data.subject,
+                           expected_subject,
+                           AVB_SHA256_DIGEST_SIZE)) {
+    avb_error("PSK: Product ID mismatch.\n");
+    return false;
+  }
+  return true;
+}
+
+/* Verifies signature and fields of a PUK certificate. */
+static bool verify_puk_certificate(
+    const AvbAtxCertificate* certificate,
+    const uint8_t authority[AVB_ATX_PUBLIC_KEY_SIZE],
+    uint64_t minimum_version,
+    const uint8_t product_id[AVB_ATX_PRODUCT_ID_SIZE]) {
+  uint8_t expected_subject[AVB_SHA256_DIGEST_SIZE];
+  uint8_t expected_usage[AVB_SHA256_DIGEST_SIZE];
+
+  sha256_str("com.google.android.things.vboot.unlock", expected_usage);
+  if (!verify_certificate(
+          certificate, authority, minimum_version, expected_usage)) {
+    avb_error("Invalid PUK certificate.\n");
+    return false;
+  }
+  sha256(product_id, AVB_ATX_PRODUCT_ID_SIZE, expected_subject);
+  if (0 != avb_safe_memcmp(certificate->signed_data.subject,
+                           expected_subject,
+                           AVB_SHA256_DIGEST_SIZE)) {
+    avb_error("PUK: Product ID mismatch.\n");
+    return false;
+  }
+  return true;
+}
+
+AvbIOResult avb_atx_validate_vbmeta_public_key(
+    AvbOps* ops,
+    const uint8_t* public_key_data,
+    size_t public_key_length,
+    const uint8_t* public_key_metadata,
+    size_t public_key_metadata_length,
+    bool* out_is_trusted) {
+  AvbIOResult result = AVB_IO_RESULT_OK;
+  AvbAtxPermanentAttributes permanent_attributes;
+  uint8_t permanent_attributes_hash[AVB_SHA256_DIGEST_SIZE];
+  AvbAtxPublicKeyMetadata metadata;
+  uint64_t minimum_version;
+
+  /* Be pessimistic so we can exit early without having to remember to clear.
+   */
+  *out_is_trusted = false;
+
+  /* Read and verify permanent attributes. */
+  result = ops->atx_ops->read_permanent_attributes(ops->atx_ops,
+                                                   &permanent_attributes);
+  if (result != AVB_IO_RESULT_OK) {
+    avb_error("Failed to read permanent attributes.\n");
+    return result;
+  }
+  result = ops->atx_ops->read_permanent_attributes_hash(
+      ops->atx_ops, permanent_attributes_hash);
+  if (result != AVB_IO_RESULT_OK) {
+    avb_error("Failed to read permanent attributes hash.\n");
+    return result;
+  }
+  if (!verify_permanent_attributes(&permanent_attributes,
+                                   permanent_attributes_hash)) {
+    return AVB_IO_RESULT_OK;
+  }
+
+  /* Sanity check public key metadata. */
+  if (public_key_metadata_length != sizeof(AvbAtxPublicKeyMetadata)) {
+    avb_error("Invalid public key metadata.\n");
+    return AVB_IO_RESULT_OK;
+  }
+  avb_memcpy(&metadata, public_key_metadata, sizeof(AvbAtxPublicKeyMetadata));
+  if (metadata.version != 1) {
+    avb_error("Unsupported public key metadata.\n");
+    return AVB_IO_RESULT_OK;
+  }
+
+  /* Verify the PIK certificate. */
+  result = ops->read_rollback_index(
+      ops, AVB_ATX_PIK_VERSION_LOCATION, &minimum_version);
+  if (result != AVB_IO_RESULT_OK) {
+    avb_error("Failed to read PIK minimum version.\n");
+    return result;
+  }
+  if (!verify_pik_certificate(&metadata.product_intermediate_key_certificate,
+                              permanent_attributes.product_root_public_key,
+                              minimum_version)) {
+    return AVB_IO_RESULT_OK;
+  }
+
+  /* Verify the PSK certificate. */
+  result = ops->read_rollback_index(
+      ops, AVB_ATX_PSK_VERSION_LOCATION, &minimum_version);
+  if (result != AVB_IO_RESULT_OK) {
+    avb_error("Failed to read PSK minimum version.\n");
+    return result;
+  }
+  if (!verify_psk_certificate(
+          &metadata.product_signing_key_certificate,
+          metadata.product_intermediate_key_certificate.signed_data.public_key,
+          minimum_version,
+          permanent_attributes.product_id)) {
+    return AVB_IO_RESULT_OK;
+  }
+
+  /* Verify the PSK is the same key that verified vbmeta. */
+  if (public_key_length != AVB_ATX_PUBLIC_KEY_SIZE) {
+    avb_error("Public key length mismatch.\n");
+    return AVB_IO_RESULT_OK;
+  }
+  if (0 != avb_safe_memcmp(
+               metadata.product_signing_key_certificate.signed_data.public_key,
+               public_key_data,
+               AVB_ATX_PUBLIC_KEY_SIZE)) {
+    avb_error("Public key mismatch.\n");
+    return AVB_IO_RESULT_OK;
+  }
+
+  /* Report the key versions used during verification. */
+  ops->atx_ops->set_key_version(
+      ops->atx_ops,
+      AVB_ATX_PIK_VERSION_LOCATION,
+      metadata.product_intermediate_key_certificate.signed_data.key_version);
+  ops->atx_ops->set_key_version(
+      ops->atx_ops,
+      AVB_ATX_PSK_VERSION_LOCATION,
+      metadata.product_signing_key_certificate.signed_data.key_version);
+
+  *out_is_trusted = true;
+  return AVB_IO_RESULT_OK;
+}
+
+AvbIOResult avb_atx_generate_unlock_challenge(
+    AvbAtxOps* atx_ops, AvbAtxUnlockChallenge* out_unlock_challenge) {
+  AvbIOResult result = AVB_IO_RESULT_OK;
+  AvbAtxPermanentAttributes permanent_attributes;
+
+  /* We need the permanent attributes to compute the product_id_hash. */
+  result = atx_ops->read_permanent_attributes(atx_ops, &permanent_attributes);
+  if (result != AVB_IO_RESULT_OK) {
+    avb_error("Failed to read permanent attributes.\n");
+    return result;
+  }
+  result = atx_ops->get_random(
+      atx_ops, AVB_ATX_UNLOCK_CHALLENGE_SIZE, last_unlock_challenge);
+  if (result != AVB_IO_RESULT_OK) {
+    avb_error("Failed to generate random challenge.\n");
+    return result;
+  }
+  out_unlock_challenge->version = 1;
+  sha256(permanent_attributes.product_id,
+         AVB_ATX_PRODUCT_ID_SIZE,
+         out_unlock_challenge->product_id_hash);
+  avb_memcpy(out_unlock_challenge->challenge,
+             last_unlock_challenge,
+             AVB_ATX_UNLOCK_CHALLENGE_SIZE);
+  return result;
+}
+
+AvbIOResult avb_atx_validate_unlock_credential(
+    AvbAtxOps* atx_ops,
+    const AvbAtxUnlockCredential* unlock_credential,
+    bool* out_is_trusted) {
+  AvbIOResult result = AVB_IO_RESULT_OK;
+  AvbAtxPermanentAttributes permanent_attributes;
+  uint8_t permanent_attributes_hash[AVB_SHA256_DIGEST_SIZE];
+  uint64_t minimum_version;
+  const AvbAlgorithmData* algorithm_data;
+  uint8_t challenge_hash[AVB_SHA512_DIGEST_SIZE];
+
+  /* Be pessimistic so we can exit early without having to remember to clear.
+   */
+  *out_is_trusted = false;
+
+  /* Sanity check the credential. */
+  if (unlock_credential->version != 1) {
+    avb_error("Unsupported unlock credential format.\n");
+    return AVB_IO_RESULT_OK;
+  }
+
+  /* Read and verify permanent attributes. */
+  result = atx_ops->read_permanent_attributes(atx_ops, &permanent_attributes);
+  if (result != AVB_IO_RESULT_OK) {
+    avb_error("Failed to read permanent attributes.\n");
+    return result;
+  }
+  result = atx_ops->read_permanent_attributes_hash(atx_ops,
+                                                   permanent_attributes_hash);
+  if (result != AVB_IO_RESULT_OK) {
+    avb_error("Failed to read permanent attributes hash.\n");
+    return result;
+  }
+  if (!verify_permanent_attributes(&permanent_attributes,
+                                   permanent_attributes_hash)) {
+    return AVB_IO_RESULT_OK;
+  }
+
+  /* Verify the PIK certificate. */
+  result = atx_ops->ops->read_rollback_index(
+      atx_ops->ops, AVB_ATX_PIK_VERSION_LOCATION, &minimum_version);
+  if (result != AVB_IO_RESULT_OK) {
+    avb_error("Failed to read PIK minimum version.\n");
+    return result;
+  }
+  if (!verify_pik_certificate(
+          &unlock_credential->product_intermediate_key_certificate,
+          permanent_attributes.product_root_public_key,
+          minimum_version)) {
+    return AVB_IO_RESULT_OK;
+  }
+
+  /* Verify the PUK certificate. The minimum version is shared with the PSK. */
+  result = atx_ops->ops->read_rollback_index(
+      atx_ops->ops, AVB_ATX_PSK_VERSION_LOCATION, &minimum_version);
+  if (result != AVB_IO_RESULT_OK) {
+    avb_error("Failed to read PSK minimum version.\n");
+    return result;
+  }
+  if (!verify_puk_certificate(
+          &unlock_credential->product_unlock_key_certificate,
+          unlock_credential->product_intermediate_key_certificate.signed_data
+              .public_key,
+          minimum_version,
+          permanent_attributes.product_id)) {
+    return AVB_IO_RESULT_OK;
+  }
+
+  /* Verify the challenge signature. */
+  algorithm_data = avb_get_algorithm_data(AVB_ALGORITHM_TYPE_SHA512_RSA4096);
+  sha512(last_unlock_challenge, AVB_ATX_UNLOCK_CHALLENGE_SIZE, challenge_hash);
+  if (!avb_rsa_verify(unlock_credential->product_unlock_key_certificate
+                          .signed_data.public_key,
+                      AVB_ATX_PUBLIC_KEY_SIZE,
+                      unlock_credential->challenge_signature,
+                      AVB_RSA4096_NUM_BYTES,
+                      challenge_hash,
+                      AVB_SHA512_DIGEST_SIZE,
+                      algorithm_data->padding,
+                      algorithm_data->padding_len)) {
+    avb_error("Invalid unlock challenge signature.\n");
+    return AVB_IO_RESULT_OK;
+  }
+
+  *out_is_trusted = true;
+  return AVB_IO_RESULT_OK;
+}
diff --git a/lib/avb/libavb_atx/avb_atx_validate.h b/lib/avb/libavb_atx/avb_atx_validate.h
new file mode 100644
index 00000000000..1a0690d4913
--- /dev/null
+++ b/lib/avb/libavb_atx/avb_atx_validate.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#if !defined(AVB_INSIDE_LIBAVB_ATX_H) && !defined(AVB_COMPILATION)
+#error \
+    "Never include this file directly, include libavb_atx/libavb_atx.h instead."
+#endif
+
+#ifndef AVB_ATX_VALIDATE_H_
+#define AVB_ATX_VALIDATE_H_
+
+#include "avb_atx_ops.h"
+#include "avb_atx_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Rollback index locations for Android Things key versions. */
+#define AVB_ATX_PIK_VERSION_LOCATION 0x1000
+#define AVB_ATX_PSK_VERSION_LOCATION 0x1001
+
+/* An implementation of validate_vbmeta_public_key for Android Things. See
+ * libavb/avb_ops.h for details on validate_vbmeta_public_key in general. This
+ * implementation uses the metadata expected with Android Things vbmeta images
+ * to perform validation on the public key. The ATX ops must be implemented.
+ * That is, |ops->atx_ops| must be valid.
+ *
+ * There are a multiple values that need verification:
+ *   - Permanent Product Attributes: A hash of these attributes is fused into
+ *                                   hardware. Consistency is checked.
+ *   - Product Root Key (PRK): This key is provided in permanent attributes and
+ *                             is the root authority for all Android Things
+ *                             products.
+ *   - Product Intermediate Key (PIK): This key is a rotated intermediary. It is
+ *                                     certified by the PRK.
+ *   - Product Signing Key (PSK): This key is a rotated authority for a specific
+ *                                Android Things product. It is certified by a
+ *                                PIK and must match |public_key_data|.
+ *   - Product ID: This value is provided in permanent attributes and is unique
+ *                 to a specific Android Things product. This value must match
+ *                 the subject of the PSK certificate.
+ */
+AvbIOResult avb_atx_validate_vbmeta_public_key(
+    AvbOps* ops,
+    const uint8_t* public_key_data,
+    size_t public_key_length,
+    const uint8_t* public_key_metadata,
+    size_t public_key_metadata_length,
+    bool* out_is_trusted);
+
+/* Generates a challenge which can be used to create an unlock credential. */
+AvbIOResult avb_atx_generate_unlock_challenge(
+    AvbAtxOps* atx_ops, AvbAtxUnlockChallenge* out_unlock_challenge);
+
+/* Validates an unlock credential. The certificate validation is very similar to
+ * the validation of public key metadata except in place of the PSK is a Product
+ * Unlock Key (PUK) and the certificate usage field identifies it as such. The
+ * challenge signature field is verified against this PUK.
+ */
+AvbIOResult avb_atx_validate_unlock_credential(
+    AvbAtxOps* atx_ops,
+    const AvbAtxUnlockCredential* unlock_credential,
+    bool* out_is_trusted);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* AVB_ATX_VALIDATE_H_ */
diff --git a/lib/avb/libavb_atx/libavb_atx.h b/lib/avb/libavb_atx/libavb_atx.h
new file mode 100644
index 00000000000..3d830ac831e
--- /dev/null
+++ b/lib/avb/libavb_atx/libavb_atx.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef LIBAVB_ATX_H_
+#define LIBAVB_ATX_H_
+
+#include <../lib/libavb/libavb.h>
+
+/* The AVB_INSIDE_LIBAVB_ATX_H preprocessor symbol is used to enforce
+ * library users to include only this file. All public interfaces, and
+ * only public interfaces, must be included here.
+ */
+
+#define AVB_INSIDE_LIBAVB_ATX_H
+#include "avb_atx_ops.h"
+#include "avb_atx_types.h"
+#include "avb_atx_validate.h"
+#undef AVB_INSIDE_LIBAVB_ATX_H
+
+#endif /* LIBAVB_ATX_H_ */
diff --git a/lib/crypto/pkcs7_verify.c b/lib/crypto/pkcs7_verify.c
index 82c5c745d49..54c677bcad3 100644
--- a/lib/crypto/pkcs7_verify.c
+++ b/lib/crypto/pkcs7_verify.c
@@ -529,7 +529,6 @@ static int pkcs7_verify_one(struct pkcs7_message *pkcs7,
 		if (sinfo->signing_time < sinfo->signer->valid_from ||
 		    sinfo->signing_time > sinfo->signer->valid_to) {
 			pr_warn("Message signed outside of X.509 validity window\n");
-			return -EKEYREJECTED;
 		}
 	}
 
diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c
index 96113988850..b7b9aea6d39 100644
--- a/lib/efi_loader/efi_image_loader.c
+++ b/lib/efi_loader/efi_image_loader.c
@@ -27,6 +27,7 @@ const efi_guid_t efi_guid_loaded_image_device_path =
 const efi_guid_t efi_simple_file_system_protocol_guid =
 		EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID;
 const efi_guid_t efi_file_info_guid = EFI_FILE_INFO_GUID;
+const efi_guid_t efi_memory_only_reset_control_guid = EFI_MEMORY_ONLY_RESET_CONTROL_GUID;
 
 static int machines[] = {
 #if defined(__aarch64__)
diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
index eee54e48784..366c219f539 100644
--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
@@ -8,12 +8,16 @@
 #define LOG_CATEGORY LOGC_EFI
 
 #include <common.h>
+#include <mapmem.h>
 #include <efi_loader.h>
 #include <efi_variable.h>
 #include <log.h>
+#include <asm/global_data.h>
 
 #define OBJ_LIST_NOT_INITIALIZED 1
 
+DECLARE_GLOBAL_DATA_PTR;
+
 efi_status_t efi_obj_list_initialized = OBJ_LIST_NOT_INITIALIZED;
 
 /*
@@ -176,6 +180,68 @@ static efi_status_t efi_init_os_indications(void)
 
 
 /**
+ * efi_init_memory_only_reset_control() - indicate supported features for
+ * OS requests
+ *
+ * Set the MemoryOverwriteRequestControl variable.
+ *
+ * Return:	status code
+ */
+static efi_status_t efi_init_memory_only_reset_control(void)
+{
+	u8 memory_only_reset_control = 0;
+	efi_status_t ret;
+	efi_uintn_t data_size = 0;
+
+	data_size = sizeof(memory_only_reset_control);
+	ret = efi_get_variable_int(L"MemoryOverwriteRequestControl",
+				   &efi_memory_only_reset_control_guid,
+				   NULL, &data_size,
+				   &memory_only_reset_control, NULL);
+	if (ret == EFI_SUCCESS) {
+		if (memory_only_reset_control & 0x01) {
+			struct bd_info *bd = gd->bd;
+			int i;
+			void *start, *buf;
+			ulong count;
+
+			memory_only_reset_control = memory_only_reset_control & (~(0x01));
+			ret = efi_set_variable_int(L"MemoryOverwriteRequestControl",
+						   &efi_memory_only_reset_control_guid,
+						   EFI_VARIABLE_BOOTSERVICE_ACCESS |
+						   EFI_VARIABLE_RUNTIME_ACCESS |
+						   EFI_VARIABLE_NON_VOLATILE,
+						   sizeof(memory_only_reset_control),
+						   &memory_only_reset_control, 0);
+
+			for (i = CONFIG_NR_DRAM_BANKS - 1; i > 0; --i) {
+				count = bd->bi_dram[i].size;
+				if (!count)
+					continue;
+				start = map_sysmem(bd->bi_dram[i].start, count);
+				buf = start;
+				while (count > 0) {
+					*((u8 *)buf) = 0;
+					buf += 1;
+					count--;
+				}
+				unmap_sysmem(start);
+			}
+		}
+		return ret;
+	}
+
+	ret = efi_set_variable_int(L"MemoryOverwriteRequestControl",
+				   &efi_memory_only_reset_control_guid,
+				   EFI_VARIABLE_BOOTSERVICE_ACCESS |
+				   EFI_VARIABLE_RUNTIME_ACCESS |
+				   EFI_VARIABLE_NON_VOLATILE,
+				   sizeof(memory_only_reset_control),
+				   &memory_only_reset_control, 0);
+	return ret;
+}
+
+/**
  * efi_init_obj_list() - Initialize and populate EFI object list
  *
  * Return:	status code
@@ -226,6 +292,11 @@ efi_status_t efi_init_obj_list(void)
 	if (ret != EFI_SUCCESS)
 		goto out;
 
+	/* Platform Reset Attack features */
+	ret = efi_init_memory_only_reset_control();
+	if (ret != EFI_SUCCESS)
+		goto out;
+
 	/* Initialize system table */
 	ret = efi_initialize_system_table();
 	if (ret != EFI_SUCCESS)
diff --git a/lib/efi_loader/efi_signature.c b/lib/efi_loader/efi_signature.c
index 79ed077ae7d..392eae6c0d6 100644
--- a/lib/efi_loader/efi_signature.c
+++ b/lib/efi_loader/efi_signature.c
@@ -24,6 +24,8 @@ const efi_guid_t efi_guid_sha256 = EFI_CERT_SHA256_GUID;
 const efi_guid_t efi_guid_cert_rsa2048 = EFI_CERT_RSA2048_GUID;
 const efi_guid_t efi_guid_cert_x509 = EFI_CERT_X509_GUID;
 const efi_guid_t efi_guid_cert_x509_sha256 = EFI_CERT_X509_SHA256_GUID;
+const efi_guid_t efi_guid_cert_x509_sha384 = EFI_CERT_X509_SHA384_GUID;
+const efi_guid_t efi_guid_cert_x509_sha512 = EFI_CERT_X509_SHA512_GUID;
 const efi_guid_t efi_guid_cert_type_pkcs7 = EFI_CERT_TYPE_PKCS7_GUID;
 
 static u8 pkcs7_hdr[] = {
@@ -124,23 +126,32 @@ struct pkcs7_message *efi_parse_pkcs7_header(const void *buf,
  * Return:	true on success, false on error
  */
 static bool efi_hash_regions(struct image_region *regs, int count,
-			     void **hash, size_t *size)
+			     void **hash, size_t size)
 {
+	char hash_algo[16];
+	int ret;
+
+	/* basic sanity checking */
+	if (!size)
+		return false;
+
+	ret = snprintf(hash_algo, sizeof(hash_algo), "sha%ld", size * 8);
+	if (ret >= sizeof(hash_algo))
+		return false;
+
 	if (!*hash) {
-		*hash = calloc(1, SHA256_SUM_LEN);
+		*hash = calloc(1, size);
 		if (!*hash) {
 			EFI_PRINT("Out of memory\n");
 			return false;
 		}
 	}
-	if (size)
-		*size = SHA256_SUM_LEN;
 
-	hash_calculate("sha256", regs, count, *hash);
+	hash_calculate(hash_algo, regs, count, *hash);
 #ifdef DEBUG
 	EFI_PRINT("hash calculated:\n");
 	print_hex_dump("    ", DUMP_PREFIX_OFFSET, 16, 1,
-		       *hash, SHA256_SUM_LEN, false);
+		       *hash, size, false);
 #endif
 
 	return true;
@@ -190,7 +201,7 @@ bool efi_signature_lookup_digest(struct efi_image_regions *regs,
 	struct efi_signature_store *siglist;
 	struct efi_sig_data *sig_data;
 	void *hash = NULL;
-	size_t size = 0;
+	size_t size = SHA256_SUM_LEN;
 	bool found = false;
 	bool hash_done = false;
 
@@ -216,7 +227,7 @@ bool efi_signature_lookup_digest(struct efi_image_regions *regs,
 			continue;
 
 		if (!hash_done &&
-		    !efi_hash_regions(regs->reg, regs->num, &hash, &size)) {
+		    !efi_hash_regions(regs->reg, regs->num, &hash, size)) {
 			EFI_PRINT("Digesting an image failed\n");
 			break;
 		}
@@ -263,7 +274,7 @@ static bool efi_lookup_certificate(struct x509_certificate *cert,
 	struct efi_sig_data *sig_data;
 	struct image_region reg[1];
 	void *hash = NULL, *hash_tmp = NULL;
-	size_t size = 0;
+	size_t size = SHA256_SUM_LEN;
 	bool found = false;
 
 	EFI_PRINT("%s: Enter, %p, %p\n", __func__, cert, db);
@@ -278,7 +289,7 @@ static bool efi_lookup_certificate(struct x509_certificate *cert,
 	/* calculate hash of TBSCertificate */
 	reg[0].data = cert->tbs;
 	reg[0].size = cert->tbs_size;
-	if (!efi_hash_regions(reg, 1, &hash, &size))
+	if (!efi_hash_regions(reg, 1, &hash, size))
 		goto out;
 
 	EFI_PRINT("%s: searching for %s\n", __func__, cert->subject);
@@ -300,7 +311,7 @@ static bool efi_lookup_certificate(struct x509_certificate *cert,
 				  cert_tmp->subject);
 			reg[0].data = cert_tmp->tbs;
 			reg[0].size = cert_tmp->tbs_size;
-			if (!efi_hash_regions(reg, 1, &hash_tmp, NULL))
+			if (!efi_hash_regions(reg, 1, &hash_tmp, size))
 				goto out;
 
 			x509_free_certificate(cert_tmp);
@@ -377,6 +388,26 @@ out:
 	return verified;
 }
 
+/** guid_to_sha_len - return the sha size in bytes for a given guid
+ *                    used of EFI security databases
+ *
+ * @guid: guid to check
+ *
+ * Return: len or 0 if no match is found
+ */
+static int guid_to_sha_len(efi_guid_t *guid)
+{
+	int size = 0;
+
+	if (!guidcmp(guid, &efi_guid_cert_x509_sha256))
+		size = SHA256_SUM_LEN;
+	else if (!guidcmp(guid, &efi_guid_cert_x509_sha384))
+		size = SHA384_SUM_LEN;
+	else if (!guidcmp(guid, &efi_guid_cert_x509_sha512))
+		size = SHA512_SUM_LEN;
+
+	return size;
+}
 /**
  * efi_signature_check_revocation - check revocation with dbx
  * @sinfo:	Signer's info
@@ -400,7 +431,7 @@ static bool efi_signature_check_revocation(struct pkcs7_signed_info *sinfo,
 	struct efi_sig_data *sig_data;
 	struct image_region reg[1];
 	void *hash = NULL;
-	size_t size = 0;
+	size_t size = SHA256_SUM_LEN;
 	time64_t revoc_time;
 	bool revoked = false;
 
@@ -411,13 +442,14 @@ static bool efi_signature_check_revocation(struct pkcs7_signed_info *sinfo,
 
 	EFI_PRINT("Checking revocation against %s\n", cert->subject);
 	for (siglist = dbx; siglist; siglist = siglist->next) {
-		if (guidcmp(&siglist->sig_type, &efi_guid_cert_x509_sha256))
+		size = guid_to_sha_len(&siglist->sig_type);
+		if (!size)
 			continue;
 
 		/* calculate hash of TBSCertificate */
 		reg[0].data = cert->tbs;
 		reg[0].size = cert->tbs_size;
-		if (!efi_hash_regions(reg, 1, &hash, &size))
+		if (!efi_hash_regions(reg, 1, &hash, size))
 			goto out;
 
 		for (sig_data = siglist->sig_data_list; sig_data;
@@ -500,7 +532,7 @@ bool efi_signature_verify(struct efi_image_regions *regs,
 		 */
 		if (!msg->data &&
 		    !efi_hash_regions(regs->reg, regs->num,
-				      (void **)&sinfo->sig->digest, NULL)) {
+				      (void **)&sinfo->sig->digest, SHA256_SUM_LEN)) {
 			EFI_PRINT("Digesting an image failed\n");
 			goto out;
 		}
diff --git a/lib/efi_loader/efi_var_common.c b/lib/efi_loader/efi_var_common.c
index eb837027818..024e30bde5b 100644
--- a/lib/efi_loader/efi_var_common.c
+++ b/lib/efi_loader/efi_var_common.c
@@ -163,6 +163,9 @@ efi_status_t EFIAPI efi_query_variable_info(
 	EFI_ENTRY("%x %p %p %p", attributes, maximum_variable_storage_size,
 		  remaining_variable_storage_size, maximum_variable_size);
 
+	if (attributes & EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS)
+		return EFI_EXIT(EFI_UNSUPPORTED);
+
 	if (!maximum_variable_storage_size ||
 	    !remaining_variable_storage_size ||
 	    !maximum_variable_size ||
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index 8ca2d85694c..f0744442950 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -282,7 +282,7 @@ efi_status_t efi_set_variable_int(const u16 *variable_name,
 	/* authenticate a variable */
 	if (IS_ENABLED(CONFIG_EFI_SECURE_BOOT)) {
 		if (attributes & EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS)
-			return EFI_INVALID_PARAMETER;
+			return EFI_UNSUPPORTED;
 		if (attributes &
 		    EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS) {
 			u32 env_attr;
diff --git a/lib/efi_loader/efi_variable_tee.c b/lib/efi_loader/efi_variable_tee.c
index dfef18435df..c740fe0fc84 100644
--- a/lib/efi_loader/efi_variable_tee.c
+++ b/lib/efi_loader/efi_variable_tee.c
@@ -537,6 +537,11 @@ efi_status_t efi_set_variable_int(const u16 *variable_name,
 		goto out;
 	}
 
+	if (attributes & EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS) {
+		ret = EFI_UNSUPPORTED;
+		goto out;
+	}
+
 	/*
 	 * Allocate the buffer early, before switching to RW (if needed)
 	 * so we won't need to account for any failures in reading/setting
diff --git a/lib/image-sparse.c b/lib/image-sparse.c
index 5ec0f94ab3e..b255d3acc0b 100644
--- a/lib/image-sparse.c
+++ b/lib/image-sparse.c
@@ -253,6 +253,7 @@ int write_sparse_image(struct sparse_storage *info,
 				    __func__);
 				info->mssg("Request would exceed partition size!",
 					   response);
+				free(fill_buf);
 				return -1;
 			}
 
diff --git a/lib/libavb/Makefile b/lib/libavb/Makefile
index b983fe768e5..9238240a7f1 100644
--- a/lib/libavb/Makefile
+++ b/lib/libavb/Makefile
@@ -2,6 +2,7 @@
 #
 # (C) Copyright 2017 Linaro Limited
 
+ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_LIBAVB) += avb_chain_partition_descriptor.o avb_cmdline.o
 obj-$(CONFIG_LIBAVB) += avb_crypto.o avb_footer.o avb_hashtree_descriptor.o
 obj-$(CONFIG_LIBAVB) += avb_property_descriptor.o avb_sha256.o
@@ -9,5 +10,7 @@ obj-$(CONFIG_LIBAVB) += avb_slot_verify.o avb_util.o avb_version.o
 obj-$(CONFIG_LIBAVB) += avb_descriptor.o avb_hash_descriptor.o
 obj-$(CONFIG_LIBAVB) += avb_kernel_cmdline_descriptor.o avb_rsa.o avb_sha512.o
 obj-$(CONFIG_LIBAVB) += avb_sysdeps_posix.o avb_vbmeta_image.o
+endif
+obj-$(CONFIG_LIBAVB) += avb_crc32.o
 
 ccflags-y = -DAVB_COMPILATION
diff --git a/lib/libavb/avb_cmdline.c b/lib/libavb/avb_cmdline.c
index cb54e658c48..dde1182a325 100644
--- a/lib/libavb/avb_cmdline.c
+++ b/lib/libavb/avb_cmdline.c
@@ -10,7 +10,11 @@
 #include <log.h>
 #include <malloc.h>
 
+#ifndef CONFIG_ANDROID_DYNAMIC_PARTITION
 #define NUM_GUIDS 3
+#else
+#define NUM_GUIDS 2
+#endif
 
 /* Substitutes all variables (e.g. $(ANDROID_SYSTEM_PARTUUID)) with
  * values. Returns NULL on OOM, otherwise the cmdline with values
@@ -21,10 +25,16 @@ char* avb_sub_cmdline(AvbOps* ops,
                       const char* ab_suffix,
                       bool using_boot_for_vbmeta,
                       const AvbCmdlineSubstList* additional_substitutions) {
+#ifndef CONFIG_ANDROID_DYNAMIC_PARTITION
   const char* part_name_str[NUM_GUIDS] = {"system", "boot", "vbmeta"};
   const char* replace_str[NUM_GUIDS] = {"$(ANDROID_SYSTEM_PARTUUID)",
                                         "$(ANDROID_BOOT_PARTUUID)",
                                         "$(ANDROID_VBMETA_PARTUUID)"};
+#else
+  const char* part_name_str[NUM_GUIDS] = {"boot", "vbmeta"};
+  const char* replace_str[NUM_GUIDS] = {"$(ANDROID_BOOT_PARTUUID)",
+                                        "$(ANDROID_VBMETA_PARTUUID)"};
+#endif
   char* ret = NULL;
   AvbIOResult io_ret;
   size_t n;
@@ -33,7 +43,11 @@ char* avb_sub_cmdline(AvbOps* ops,
    * partition.
    */
   if (using_boot_for_vbmeta) {
+#ifndef CONFIG_ANDROID_DYNAMIC_PARTITION
     part_name_str[2] = "boot";
+#else
+    part_name_str[1] = "boot";
+#endif
   }
 
   /* Replace unique partition GUIDs */
@@ -223,7 +237,7 @@ AvbSlotVerifyResult avb_append_options(
     AvbHashtreeErrorMode hashtree_error_mode,
     AvbHashtreeErrorMode resolved_hashtree_error_mode) {
   AvbSlotVerifyResult ret;
-  const char* verity_mode;
+  const char* verity_mode = NULL;
   bool is_device_unlocked;
   AvbIOResult io_ret;
 
@@ -325,7 +339,7 @@ AvbSlotVerifyResult avb_append_options(
   if (toplevel_vbmeta->flags & AVB_VBMETA_IMAGE_FLAGS_HASHTREE_DISABLED) {
     verity_mode = "disabled";
   } else {
-    const char* dm_verity_mode;
+    const char* dm_verity_mode = NULL;
     char* new_ret;
 
     switch (resolved_hashtree_error_mode) {
diff --git a/lib/libavb/avb_crc32.c b/lib/libavb/avb_crc32.c
new file mode 100644
index 00000000000..7d4cb09035a
--- /dev/null
+++ b/lib/libavb/avb_crc32.c
@@ -0,0 +1,114 @@
+/*-
+ *  COPYRIGHT (C) 1986 Gary S. Brown.  You may use this program, or
+ *  code or tables extracted from it, as desired without restriction.
+ */
+
+/*
+ *  First, the polynomial itself and its table of feedback terms.  The
+ *  polynomial is
+ *  X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0
+ *
+ *  Note that we take it "backwards" and put the highest-order term in
+ *  the lowest-order bit.  The X^32 term is "implied"; the LSB is the
+ *  X^31 term, etc.  The X^0 term (usually shown as "+1") results in
+ *  the MSB being 1
+ *
+ *  Note that the usual hardware shift register implementation, which
+ *  is what we're using (we're merely optimizing it by doing eight-bit
+ *  chunks at a time) shifts bits into the lowest-order term.  In our
+ *  implementation, that means shifting towards the right.  Why do we
+ *  do it this way?  Because the calculated CRC must be transmitted in
+ *  order from highest-order term to lowest-order term.  UARTs transmit
+ *  characters in order from LSB to MSB.  By storing the CRC this way
+ *  we hand it to the UART in the order low-byte to high-byte; the UART
+ *  sends each low-bit to hight-bit; and the result is transmission bit
+ *  by bit from highest- to lowest-order term without requiring any bit
+ *  shuffling on our part.  Reception works similarly
+ *
+ *  The feedback terms table consists of 256, 32-bit entries.  Notes
+ *
+ *      The table can be generated at runtime if desired; code to do so
+ *      is shown later.  It might not be obvious, but the feedback
+ *      terms simply represent the results of eight shift/xor opera
+ *      tions for all combinations of data and CRC register values
+ *
+ *      The values must be right-shifted by eight bits by the "updcrc
+ *      logic; the shift must be unsigned (bring in zeroes).  On some
+ *      hardware you could probably optimize the shift in assembler by
+ *      using byte-swap instructions
+ *      polynomial $edb88320
+ *
+ *
+ * CRC32 code derived from work by Gary S. Brown.
+ */
+
+#include "avb_sysdeps.h"
+#include "avb_util.h"
+
+/* Code taken from FreeBSD 8 */
+
+static uint32_t iavb_crc32_tab[] = {
+    0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
+    0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
+    0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
+    0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
+    0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
+    0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
+    0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
+    0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
+    0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
+    0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
+    0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
+    0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
+    0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
+    0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
+    0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
+    0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
+    0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
+    0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
+    0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
+    0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
+    0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
+    0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
+    0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
+    0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
+    0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
+    0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
+    0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
+    0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
+    0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
+    0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
+    0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
+    0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
+    0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
+    0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
+    0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
+    0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
+    0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
+    0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
+    0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
+    0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
+    0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
+    0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
+    0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d};
+
+/*
+ * A function that calculates the CRC-32 based on the table above is
+ * given below for documentation purposes. An equivalent implementation
+ * of this function that's actually used in the kernel can be found
+ * in sys/libkern.h, where it can be inlined.
+ */
+
+static uint32_t iavb_crc32(uint32_t crc_in, const uint8_t* buf, int size) {
+  const uint8_t* p = buf;
+  uint32_t crc;
+
+  crc = crc_in ^ ~0U;
+  while (size--)
+    crc = iavb_crc32_tab[(crc ^ *p++) & 0xFF] ^ (crc >> 8);
+  return crc ^ ~0U;
+}
+
+uint32_t avb_crc32(const uint8_t* buf, size_t size) {
+  return iavb_crc32(0, buf, size);
+}
diff --git a/lib/libavb/avb_slot_verify.c b/lib/libavb/avb_slot_verify.c
index ae8e1dffa4c..436983771c2 100644
--- a/lib/libavb/avb_slot_verify.c
+++ b/lib/libavb/avb_slot_verify.c
@@ -16,6 +16,10 @@
 #include "avb_version.h"
 #include <log.h>
 #include <malloc.h>
+#include <memalign.h>
+#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX)
+#include "trusty/hwcrypto.h"
+#endif
 
 /* Maximum number of partitions that can be loaded with avb_slot_verify(). */
 #define MAX_NUMBER_OF_LOADED_PARTITIONS 32
@@ -25,6 +29,21 @@
 
 /* Maximum size of a vbmeta image - 64 KiB. */
 #define VBMETA_MAX_SIZE (64 * 1024)
+/* Set the image load addr start from 96MB offset of CONFIG_FASTBOOT_BUF_ADDR */
+#define PARTITION_LOAD_ADDR_START (CONFIG_FASTBOOT_BUF_ADDR + (96 * 1024 * 1024))
+
+/* Load dtbo/boot partition to fixed address instead of heap memory. */
+static void *image_addr_top = (void *)PARTITION_LOAD_ADDR_START;
+static void *alloc_partition_addr(int size)
+{
+  void *ptr = image_addr_top;
+  image_addr_top = image_addr_top + ROUND(size, ARCH_DMA_MINALIGN);
+  return ptr;
+}
+static void free_partition_addr(int size)
+{
+  image_addr_top = (void *)(image_addr_top - ROUND(size, ARCH_DMA_MINALIGN));
+}
 
 static AvbSlotVerifyResult initialize_persistent_digest(
     AvbOps* ops,
@@ -98,7 +117,7 @@ static AvbSlotVerifyResult load_full_partition(AvbOps* ops,
 
   /* Allocate and copy the partition. */
   if (!*out_image_preloaded) {
-    *out_image_buf = avb_malloc(image_size);
+    *out_image_buf = (void *)alloc_partition_addr(image_size);
     if (*out_image_buf == NULL) {
       return AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
     }
@@ -276,11 +295,16 @@ static AvbSlotVerifyResult load_and_verify_hash_partition(
   bool image_preloaded = false;
   uint8_t* digest;
   size_t digest_len;
-  const char* found;
+  const char* found = NULL;
   uint64_t image_size;
   size_t expected_digest_len = 0;
   uint8_t expected_digest_buf[AVB_SHA512_DIGEST_SIZE];
   const uint8_t* expected_digest = NULL;
+#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX)
+  uint8_t* hash_out = NULL;
+  uint8_t* hash_buf = NULL;
+#endif
+
 
   if (!avb_hash_descriptor_validate_and_byteswap(
           (const AvbHashDescriptor*)descriptor, &hash_desc)) {
@@ -371,7 +395,9 @@ static AvbSlotVerifyResult load_and_verify_hash_partition(
   // Although only one of the type might be used, we have to defined the
   // structure here so that they would live outside the 'if/else' scope to be
   // used later.
+#if !defined(CONFIG_IMX_TRUSTY_OS) || defined(CONFIG_AVB_ATX) ||  defined(CONFIG_XEN)
   AvbSHA256Ctx sha256_ctx;
+#endif
   AvbSHA512Ctx sha512_ctx;
   size_t image_size_to_hash = hash_desc.image_size;
   // If we allow verification error and the whole partition is smaller than
@@ -380,10 +406,37 @@ static AvbSlotVerifyResult load_and_verify_hash_partition(
     image_size_to_hash = image_size;
   }
   if (avb_strcmp((const char*)hash_desc.hash_algorithm, "sha256") == 0) {
+#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX)
+    /* DMA requires cache aligned input/output buffer */
+    hash_out = memalign(ARCH_DMA_MINALIGN, AVB_SHA256_DIGEST_SIZE);
+    if (hash_out == NULL) {
+        avb_error("failed to alloc memory!\n");
+        ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
+        goto out;
+    }
+    hash_buf = (void *)CONFIG_FASTBOOT_BUF_ADDR;
+
+    avb_memcpy(hash_buf, desc_salt, hash_desc.salt_len);
+    avb_memcpy(hash_buf + hash_desc.salt_len,
+               image_buf, image_size_to_hash);
+    /* calculate sha256 hash by caam */
+    if (hwcrypto_hash((uint32_t)(ulong)hash_buf,
+                  (hash_desc.salt_len + image_size_to_hash),
+                  (uint32_t)(ulong)hash_out,
+                  AVB_SHA256_DIGEST_SIZE,
+                  SHA256) != 0) {
+        avb_error("Failed to calculate sha256 hash with caam.\n");
+	ret = AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION;
+	goto out;
+    }
+
+    digest = hash_out;
+#else
     avb_sha256_init(&sha256_ctx);
     avb_sha256_update(&sha256_ctx, desc_salt, hash_desc.salt_len);
     avb_sha256_update(&sha256_ctx, image_buf, image_size_to_hash);
     digest = avb_sha256_final(&sha256_ctx);
+#endif
     digest_len = AVB_SHA256_DIGEST_SIZE;
   } else if (avb_strcmp((const char*)hash_desc.hash_algorithm, "sha512") == 0) {
     avb_sha512_init(&sha512_ctx);
@@ -436,6 +489,12 @@ static AvbSlotVerifyResult load_and_verify_hash_partition(
 
 out:
 
+#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX)
+  if (hash_out != NULL) {
+    free(hash_out);
+    hash_out = NULL;
+  }
+#endif
   /* If it worked and something was loaded, copy to slot_data. */
   if ((ret == AVB_SLOT_VERIFY_RESULT_OK || result_should_continue(ret)) &&
       image_buf != NULL) {
@@ -455,8 +514,10 @@ out:
   }
 
 fail:
+  /* Now the image_buf is not allocated by malloc(), we should not free.
+   * Instead, we should reset the image_addr_top.*/
   if (image_buf != NULL && !image_preloaded) {
-    avb_free(image_buf);
+    free_partition_addr(image_size);
   }
   return ret;
 }
@@ -468,13 +529,13 @@ static AvbSlotVerifyResult load_requested_partitions(
     AvbSlotVerifyData* slot_data) {
   AvbSlotVerifyResult ret;
   uint8_t* image_buf = NULL;
+    uint64_t image_size;
   bool image_preloaded = false;
   size_t n;
 
   for (n = 0; requested_partitions[n] != NULL; n++) {
     char part_name[AVB_PART_NAME_MAX_SIZE];
     AvbIOResult io_ret;
-    uint64_t image_size;
     AvbPartitionData* loaded_partition;
 
     if (!avb_str_concat(part_name,
@@ -528,9 +589,10 @@ static AvbSlotVerifyResult load_requested_partitions(
   ret = AVB_SLOT_VERIFY_RESULT_OK;
 
 out:
-  /* Free the current buffer if any. */
+  /* Now the image_buf is not allocated by malloc(), we should not free.
+   * Instead, we should reset the image_addr_top.*/
   if (image_buf != NULL && !image_preloaded) {
-    avb_free(image_buf);
+    free_partition_addr(image_size);
   }
   /* Buffers that are already saved in slot_data will be handled by the caller
    * even on failure. */
@@ -1635,10 +1697,10 @@ void avb_slot_verify_data_free(AvbSlotVerifyData* data) {
       if (loaded_partition->partition_name != NULL) {
         avb_free(loaded_partition->partition_name);
       }
-      if (loaded_partition->data != NULL && !loaded_partition->preloaded) {
-        avb_free(loaded_partition->data);
-      }
     }
+    /* partition data is not loaded to heap memory, so we just reset the
+     * image_addr_top here. */
+    image_addr_top = (void *)PARTITION_LOAD_ADDR_START;
     avb_free(data->loaded_partitions);
   }
   avb_free(data);
diff --git a/lib/lmb.c b/lib/lmb.c
index f72996a4248..123fd11939f 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -233,7 +233,7 @@ static long lmb_add_region_flags(struct lmb_region *rgn, phys_addr_t base,
 			break;
 		} else if (lmb_addrs_overlap(base, size, rgnbase, rgnsize)) {
 			/* regions overlap */
-			return -1;
+			return -2;
 		}
 	}
 
@@ -366,6 +366,43 @@ static long lmb_overlaps_region(struct lmb_region *rgn, phys_addr_t base,
 	return (i < rgn->cnt) ? i : -1;
 }
 
+long lmb_reserve_overlap(struct lmb *lmb, phys_addr_t base, phys_size_t size,
+		       enum lmb_flags flags)
+{
+	struct lmb_region *_rgn = &(lmb->reserved);
+	long ret = lmb_add_region_flags(_rgn, base, size, flags);
+	long overlap_rgn;
+	phys_addr_t res_base;
+	phys_size_t res_size;
+
+	/* Handle the overlap */
+	if (ret == -2) {
+		overlap_rgn = lmb_overlaps_region(_rgn, base, size);
+		res_base = lmb->reserved.region[overlap_rgn].base;
+		res_size = lmb->reserved.region[overlap_rgn].size;
+
+		if ((base >= res_base) && ((base + size) <= (res_base + res_size))) {
+			/* new region is inside reserved region, so it is already reserved */
+			return 0;
+		} else {
+			if (base < res_base) {
+				ret = lmb_reserve_flags(lmb, base, res_base - base, flags);
+				if (ret < 0)
+					return ret;
+			}
+
+			if ((base + size) > (res_base + res_size)) {
+				ret = lmb_reserve_flags(lmb, res_base + res_size,
+					(base + size) - (res_base + res_size), flags);
+				if (ret < 0)
+					return ret;
+			}
+		}
+	}
+
+	return ret;
+}
+
 phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align)
 {
 	return lmb_alloc_base(lmb, size, align, LMB_ALLOC_ANYWHERE);
diff --git a/lib/rsa/rsa-verify.c b/lib/rsa/rsa-verify.c
index 112664059c9..35879542cfc 100644
--- a/lib/rsa/rsa-verify.c
+++ b/lib/rsa/rsa-verify.c
@@ -589,6 +589,12 @@ int rsa_verify(struct image_sign_info *info,
 
 #ifndef USE_HOSTCC
 
+U_BOOT_CRYPTO_ALGO(rsa1024) = {
+	.name = "rsa1024",
+	.key_len = RSA1024_BYTES,
+	.verify = rsa_verify,
+};
+
 U_BOOT_CRYPTO_ALGO(rsa2048) = {
 	.name = "rsa2048",
 	.key_len = RSA2048_BYTES,
diff --git a/lib/sha256.c b/lib/sha256.c
index c1fe93de012..70123c10608 100644
--- a/lib/sha256.c
+++ b/lib/sha256.c
@@ -289,3 +289,43 @@ void sha256_csum_wd(const unsigned char *input, unsigned int ilen,
 
 	sha256_finish(&ctx, output);
 }
+
+/*
+ * Output = HMAC-SHA-256( input buffer, hmac key )
+ */
+void sha256_hmac(const unsigned char *key, int keylen,
+	       const unsigned char *input, unsigned int ilen,
+	       unsigned char *output)
+{
+	int i;
+	sha256_context ctx;
+	unsigned char k_ipad[64];
+	unsigned char k_opad[64];
+	unsigned char tmpbuf[32];
+
+	memset (k_ipad, 0x36, 64);
+	memset (k_opad, 0x5C, 64);
+
+	for (i = 0; i < keylen; i++) {
+		if (i >= 64)
+			break;
+
+		k_ipad[i] ^= key[i];
+		k_opad[i] ^= key[i];
+	}
+
+	sha256_starts (&ctx);
+	sha256_update (&ctx, k_ipad, 64);
+	sha256_update (&ctx, input, ilen);
+	sha256_finish (&ctx, tmpbuf);
+
+	sha256_starts (&ctx);
+	sha256_update (&ctx, k_opad, 64);
+	sha256_update (&ctx, tmpbuf, 32);
+	sha256_finish (&ctx, output);
+
+	memset (k_ipad, 0, 64);
+	memset (k_opad, 0, 64);
+	memset (tmpbuf, 0, 32);
+	memset (&ctx, 0, sizeof (sha256_context));
+}
diff --git a/lib/trusty/ql-tipc/LICENSE b/lib/trusty/ql-tipc/LICENSE
new file mode 100644
index 00000000000..d21621abc4b
--- /dev/null
+++ b/lib/trusty/ql-tipc/LICENSE
@@ -0,0 +1,20 @@
+Copyright 2016, The Android Open Source Project
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice shall be
+included in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
diff --git a/lib/trusty/ql-tipc/Makefile b/lib/trusty/ql-tipc/Makefile
new file mode 100644
index 00000000000..57b48223e2b
--- /dev/null
+++ b/lib/trusty/ql-tipc/Makefile
@@ -0,0 +1,50 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Permission is hereby granted, free of charge, to any person
+# obtaining a copy of this software and associated documentation
+# files (the "Software"), to deal in the Software without
+# restriction, including without limitation the rights to use, copy,
+# modify, merge, publish, distribute, sublicense, and/or sell copies
+# of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be
+# included in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+
+# Sample Makefile for U-boot
+
+#ccflags-y += -DTIPC_ENABLE_DEBUG
+
+TRUSTY_DIR = lib/trusty
+#ccflags-y += -I$(TRUSTY_DIR)/ql-tipc/include
+ccflags-y += -I$(TRUSTY_DIR)/interface/include
+
+QL_TIPC = .
+obj-y += \
+    $(QL_TIPC)/avb.o \
+    $(QL_TIPC)/hwcrypto.o \
+    $(QL_TIPC)/keymaster.o \
+    $(QL_TIPC)/keymaster_serializable.o \
+    $(QL_TIPC)/ipc.o \
+    $(QL_TIPC)/ipc_dev.o \
+    $(QL_TIPC)/libtipc.o \
+    $(QL_TIPC)/rpmb_proxy.o \
+    $(QL_TIPC)/util.o \
+    $(QL_TIPC)/imx_snvs.o \
+    sysdeps/sysdeps_uboot.o \
+    sysdeps/storage_ops_uboot.o
+
+obj-$(CONFIG_ARM) += \
+    $(QL_TIPC)/arch/arm/trusty_mem.o \
+    $(QL_TIPC)/arch/arm/trusty_dev.o
diff --git a/lib/trusty/ql-tipc/README.md b/lib/trusty/ql-tipc/README.md
new file mode 100644
index 00000000000..76e37817561
--- /dev/null
+++ b/lib/trusty/ql-tipc/README.md
@@ -0,0 +1,30 @@
+# Queueless Trusty IPC
+
+ql-tipc is a portable client library that implements Trusty queueless IPC.
+It is intended to enable Trusty IPC in bootloader environments.
+
+## Code organization
+
+### IPC components
+
+- libtipc - Functions to be called by library user
+- ipc - IPC library
+- ipc_dev - Helper functions for sending requests to the secure OS
+- rpmb_proxy - Handles RPMB requests from secure storage service
+- avb - Sends requests to the Android Verified Boot service
+
+### Misc
+
+- examples/ - Implementations of bootloader-specific code.
+- arch/$ARCH/ - Architecture dependent implementation of Trusty device
+   (see trusty_dev.h). Implements SMCs on ARM for example.
+
+## Portability Notes
+
+The suggested approach to porting ql-tipc is to copy all header and C files
+into the bootloader and integrate as needed. RPMB storage operations and
+functions defined in trusty/sysdeps.h require system dependent implementations.
+
+If the TIPC_ENABLE_DEBUG preprocessor symbol is set, the code will include
+debug information and run-time checks. Production builds should not use this.
+
diff --git a/lib/trusty/ql-tipc/arch/arm/sm_err.h b/lib/trusty/ql-tipc/arch/arm/sm_err.h
new file mode 100644
index 00000000000..940125611c4
--- /dev/null
+++ b/lib/trusty/ql-tipc/arch/arm/sm_err.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef QL_TIPC_SM_ERR_H_
+#define QL_TIPC_SM_ERR_H_
+
+/* Errors from the secure monitor */
+#define SM_ERR_UNDEFINED_SMC		0xFFFFFFFF /* Unknown SMC (defined by ARM DEN 0028A(0.9.0) */
+#define SM_ERR_INVALID_PARAMETERS	-2
+#define SM_ERR_INTERRUPTED		-3	/* Got interrupted. Call back with restart SMC */
+#define SM_ERR_UNEXPECTED_RESTART	-4	/* Got an restart SMC when we didn't expect it */
+#define SM_ERR_BUSY			-5	/* Temporarily busy. Call back with original args */
+#define SM_ERR_INTERLEAVED_SMC		-6	/* Got a trusted_service SMC when a restart SMC is required */
+#define SM_ERR_INTERNAL_FAILURE		-7	/* Unknown error */
+#define SM_ERR_NOT_SUPPORTED		-8
+#define SM_ERR_NOT_ALLOWED		-9	/* SMC call not allowed */
+#define SM_ERR_END_OF_INPUT		-10
+#define SM_ERR_PANIC			-11	/* Secure OS crashed */
+#define SM_ERR_FIQ_INTERRUPTED		-12	/* Got interrupted by FIQ. Call back with SMC_SC_RESTART_FIQ on same CPU */
+#define SM_ERR_CPU_IDLE			-13	/* SMC call waiting for another CPU */
+#define SM_ERR_NOP_INTERRUPTED		-14	/* Got interrupted. Call back with new SMC_SC_NOP */
+#define SM_ERR_NOP_DONE			-15	/* Cpu idle after SMC_SC_NOP (not an error) */
+
+#endif /* QL_TIPC_SM_ERR_H_ */
diff --git a/lib/trusty/ql-tipc/arch/arm/smcall.h b/lib/trusty/ql-tipc/arch/arm/smcall.h
new file mode 100644
index 00000000000..695776c93ec
--- /dev/null
+++ b/lib/trusty/ql-tipc/arch/arm/smcall.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef QL_TIPC_SMCALL_H_
+#define QL_TIPC_SMCALL_H_
+
+#define SMC_NUM_ENTITIES	64
+#define SMC_NUM_ARGS		4
+#define SMC_NUM_PARAMS		(SMC_NUM_ARGS - 1)
+
+#define SMC_IS_FASTCALL(smc_nr)	((smc_nr) & 0x80000000)
+#define SMC_IS_SMC64(smc_nr)	((smc_nr) & 0x40000000)
+#define SMC_ENTITY(smc_nr)	(((smc_nr) & 0x3F000000) >> 24)
+#define SMC_FUNCTION(smc_nr)	((smc_nr) & 0x0000FFFF)
+
+#define SMC_NR(entity, fn, fastcall, smc64) ((((fastcall) & 0x1) << 31) | \
+					     (((smc64) & 0x1) << 30) | \
+					     (((entity) & 0x3F) << 24) | \
+					     ((fn) & 0xFFFF) \
+					    )
+
+#define SMC_FASTCALL_NR(entity, fn)	SMC_NR((entity), (fn), 1, 0)
+#define SMC_STDCALL_NR(entity, fn)	SMC_NR((entity), (fn), 0, 0)
+#define SMC_FASTCALL64_NR(entity, fn)	SMC_NR((entity), (fn), 1, 1)
+#define SMC_STDCALL64_NR(entity, fn)	SMC_NR((entity), (fn), 0, 1)
+
+#define	SMC_ENTITY_ARCH			0	/* ARM Architecture calls */
+#define	SMC_ENTITY_CPU			1	/* CPU Service calls */
+#define	SMC_ENTITY_SIP			2	/* SIP Service calls */
+#define	SMC_ENTITY_OEM			3	/* OEM Service calls */
+#define	SMC_ENTITY_STD			4	/* Standard Service calls */
+#define	SMC_ENTITY_RESERVED		5	/* Reserved for future use */
+#define	SMC_ENTITY_TRUSTED_APP		48	/* Trusted Application calls */
+#define	SMC_ENTITY_TRUSTED_OS		50	/* Trusted OS calls */
+#define	SMC_ENTITY_LOGGING		51	/* Used for secure -> nonsecure logging */
+#define	SMC_ENTITY_SECURE_MONITOR	60	/* Trusted OS calls internal to secure monitor */
+
+/* FC = Fast call, SC = Standard call */
+#define SMC_SC_RESTART_LAST	SMC_STDCALL_NR  (SMC_ENTITY_SECURE_MONITOR, 0)
+#define SMC_SC_LOCKED_NOP	SMC_STDCALL_NR  (SMC_ENTITY_SECURE_MONITOR, 1)
+
+/**
+ * SMC_SC_RESTART_FIQ - Re-enter trusty after it was interrupted by an fiq
+ *
+ * No arguments, no return value.
+ *
+ * Re-enter trusty after returning to ns to process an fiq. Must be called iff
+ * trusty returns SM_ERR_FIQ_INTERRUPTED.
+ *
+ * Enable by selecting api version TRUSTY_API_VERSION_RESTART_FIQ (1) or later.
+ */
+#define SMC_SC_RESTART_FIQ	SMC_STDCALL_NR  (SMC_ENTITY_SECURE_MONITOR, 2)
+
+/**
+ * SMC_SC_NOP - Enter trusty to run pending work.
+ *
+ * No arguments.
+ *
+ * Returns SM_ERR_NOP_INTERRUPTED or SM_ERR_NOP_DONE.
+ * If SM_ERR_NOP_INTERRUPTED is returned, the call must be repeated.
+ *
+ * Enable by selecting api version TRUSTY_API_VERSION_SMP (2) or later.
+ */
+#define SMC_SC_NOP		SMC_STDCALL_NR  (SMC_ENTITY_SECURE_MONITOR, 3)
+
+/*
+ * Return from secure os to non-secure os with return value in r1
+ */
+#define SMC_SC_NS_RETURN	SMC_STDCALL_NR  (SMC_ENTITY_SECURE_MONITOR, 0)
+
+#define SMC_FC_RESERVED		SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 0)
+#define SMC_FC_FIQ_EXIT		SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 1)
+#define SMC_FC_REQUEST_FIQ	SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 2)
+#define SMC_FC_GET_NEXT_IRQ	SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 3)
+#define SMC_FC_FIQ_ENTER	SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 4)
+
+#define SMC_FC64_SET_FIQ_HANDLER SMC_FASTCALL64_NR(SMC_ENTITY_SECURE_MONITOR, 5)
+#define SMC_FC64_GET_FIQ_REGS	SMC_FASTCALL64_NR (SMC_ENTITY_SECURE_MONITOR, 6)
+
+#define SMC_FC_CPU_SUSPEND	SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 7)
+#define SMC_FC_CPU_RESUME	SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 8)
+
+#define SMC_FC_AARCH_SWITCH	SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 9)
+#define SMC_FC_GET_VERSION_STR	SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 10)
+
+/**
+ * SMC_FC_API_VERSION - Find and select supported API version.
+ *
+ * @r1: Version supported by client.
+ *
+ * Returns version supported by trusty.
+ *
+ * If multiple versions are supported, the client should start by calling
+ * SMC_FC_API_VERSION with the largest version it supports. Trusty will then
+ * return a version it supports. If the client does not support the version
+ * returned by trusty and the version returned is less than the version
+ * requested, repeat the call with the largest supported version less than the
+ * last returned version.
+ *
+ * This call must be made before any calls that are affected by the api version.
+ */
+#define TRUSTY_API_VERSION_RESTART_FIQ	(1)
+#define TRUSTY_API_VERSION_SMP		(2)
+#define TRUSTY_API_VERSION_SMP_NOP	(3)
+#define TRUSTY_API_VERSION_CURRENT	(3)
+#define SMC_FC_API_VERSION	SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 11)
+
+/* TRUSTED_OS entity calls */
+#define SMC_SC_VIRTIO_GET_DESCR	SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 20)
+#define SMC_SC_VIRTIO_START	SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 21)
+#define SMC_SC_VIRTIO_STOP	SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 22)
+
+#define SMC_SC_VDEV_RESET	SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 23)
+#define SMC_SC_VDEV_KICK_VQ	SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 24)
+#define SMC_NC_VDEV_KICK_VQ	SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 25)
+
+/* Queueless Trusty IPC Interface */
+#define SMC_SC_TRUSTY_IPC_CREATE_QL_DEV		SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 30)
+#define SMC_SC_TRUSTY_IPC_SHUTDOWN_QL_DEV	SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 31)
+#define SMC_SC_TRUSTY_IPC_HANDLE_QL_DEV_CMD	SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 32)
+
+#endif /* QL_TIPC_SMCALL_H_ */
diff --git a/lib/trusty/ql-tipc/arch/arm/trusty_dev.c b/lib/trusty/ql-tipc/arch/arm/trusty_dev.c
new file mode 100644
index 00000000000..fd8f2f367e9
--- /dev/null
+++ b/lib/trusty/ql-tipc/arch/arm/trusty_dev.c
@@ -0,0 +1,265 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <trusty/trusty_dev.h>
+#include <trusty/util.h>
+
+#include "sm_err.h"
+#include "smcall.h"
+
+struct trusty_dev;
+
+#define LOCAL_LOG 0
+
+#ifndef __asmeq
+#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
+#endif
+
+#ifdef  NS_ARCH_ARM64
+#define SMC_ARG0                "x0"
+#define SMC_ARG1                "x1"
+#define SMC_ARG2                "x2"
+#define SMC_ARG3                "x3"
+#define SMC_ARCH_EXTENSION      ""
+#define SMC_REGISTERS_TRASHED   "x4","x5","x6","x7","x8","x9","x10","x11", \
+                                "x12","x13","x14","x15","x16","x17"
+#else
+#define SMC_ARG0                "r0"
+#define SMC_ARG1                "r1"
+#define SMC_ARG2                "r2"
+#define SMC_ARG3                "r3"
+#define SMC_ARCH_EXTENSION      ".arch_extension sec\n"
+#define SMC_REGISTERS_TRASHED   "ip"
+#endif
+
+/*
+ * Execute SMC call into trusty
+ */
+static unsigned long smc(unsigned long r0,
+                         unsigned long r1,
+                         unsigned long r2,
+                         unsigned long r3)
+{
+    register unsigned long _r0 __asm__(SMC_ARG0) = r0;
+    register unsigned long _r1 __asm__(SMC_ARG1) = r1;
+    register unsigned long _r2 __asm__(SMC_ARG2) = r2;
+    register unsigned long _r3 __asm__(SMC_ARG3) = r3;
+
+    __asm__ volatile(
+        __asmeq("%0", SMC_ARG0)
+        __asmeq("%1", SMC_ARG1)
+        __asmeq("%2", SMC_ARG2)
+        __asmeq("%3", SMC_ARG3)
+        __asmeq("%4", SMC_ARG0)
+        __asmeq("%5", SMC_ARG1)
+        __asmeq("%6", SMC_ARG2)
+        __asmeq("%7", SMC_ARG3)
+        SMC_ARCH_EXTENSION
+        "smc    #0" /* switch to secure world */
+        : "=r" (_r0), "=r" (_r1), "=r" (_r2), "=r" (_r3)
+        : "r" (_r0), "r" (_r1), "r" (_r2), "r" (_r3)
+        : SMC_REGISTERS_TRASHED);
+    return _r0;
+}
+
+int32_t trusty_simple_fast_call32(uint32_t smcnr,
+                                  uint32_t a0, uint32_t a1, uint32_t a2)
+{
+    trusty_assert(SMC_IS_FASTCALL(smcnr));
+
+    return smc(smcnr, a0, a1, a2);
+}
+
+static int32_t trusty_fast_call32(struct trusty_dev *dev, uint32_t smcnr,
+                                  uint32_t a0, uint32_t a1, uint32_t a2)
+{
+    trusty_assert(dev);
+    trusty_assert(SMC_IS_FASTCALL(smcnr));
+
+    return smc(smcnr, a0, a1, a2);
+}
+
+static unsigned long trusty_std_call_inner(struct trusty_dev *dev,
+                                           unsigned long smcnr,
+                                           unsigned long a0,
+                                           unsigned long a1,
+                                           unsigned long a2)
+{
+    unsigned long ret;
+    int retry = 5;
+
+    trusty_debug("%s(0x%lx 0x%lx 0x%lx 0x%lx)\n", __func__, smcnr, a0, a1, a2);
+
+    while (true) {
+        ret = smc(smcnr, a0, a1, a2);
+        while ((int32_t)ret == SM_ERR_FIQ_INTERRUPTED)
+            ret = smc(SMC_SC_RESTART_FIQ, 0, 0, 0);
+        if ((int)ret != SM_ERR_BUSY || !retry)
+            break;
+
+        trusty_debug("%s(0x%lx 0x%lx 0x%lx 0x%lx) returned busy, retry\n",
+                     __func__, smcnr, a0, a1, a2);
+
+        retry--;
+    }
+
+    return ret;
+}
+
+static unsigned long trusty_std_call_helper(struct trusty_dev *dev,
+                                            unsigned long smcnr,
+                                            unsigned long a0,
+                                            unsigned long a1,
+                                            unsigned long a2)
+{
+    unsigned long ret;
+    unsigned long irq_state;
+
+    while (true) {
+        trusty_local_irq_disable(&irq_state);
+        ret = trusty_std_call_inner(dev, smcnr, a0, a1, a2);
+        trusty_local_irq_restore(&irq_state);
+
+        if ((int)ret != SM_ERR_BUSY)
+            break;
+
+        trusty_idle(dev);
+    }
+
+    return ret;
+}
+
+static int32_t trusty_std_call32(struct trusty_dev *dev, uint32_t smcnr,
+                                 uint32_t a0, uint32_t a1, uint32_t a2)
+{
+    int ret;
+
+    trusty_assert(dev);
+    trusty_assert(!SMC_IS_FASTCALL(smcnr));
+
+    if (smcnr != SMC_SC_NOP) {
+        trusty_lock(dev);
+    }
+
+    trusty_debug("%s(0x%x 0x%x 0x%x 0x%x) started\n", __func__,
+                 smcnr, a0, a1, a2);
+
+    ret = trusty_std_call_helper(dev, smcnr, a0, a1, a2);
+    while (ret == SM_ERR_INTERRUPTED || ret == SM_ERR_CPU_IDLE) {
+        trusty_debug("%s(0x%x 0x%x 0x%x 0x%x) interrupted\n", __func__,
+                     smcnr, a0, a1, a2);
+        if (ret == SM_ERR_CPU_IDLE) {
+            trusty_idle(dev);
+        }
+        ret = trusty_std_call_helper(dev, SMC_SC_RESTART_LAST, 0, 0, 0);
+    }
+
+    trusty_debug("%s(0x%x 0x%x 0x%x 0x%x) returned 0x%x\n",
+                 __func__, smcnr, a0, a1, a2, ret);
+
+    if (smcnr != SMC_SC_NOP) {
+        trusty_unlock(dev);
+    }
+
+    return ret;
+}
+
+static int trusty_call32_mem_buf(struct trusty_dev *dev, uint32_t smcnr,
+                                 struct ns_mem_page_info *page, uint32_t size)
+{
+    trusty_assert(dev);
+    trusty_assert(page);
+
+    if (SMC_IS_FASTCALL(smcnr)) {
+        return trusty_fast_call32(dev, smcnr,
+                                  (uint32_t)page->attr,
+                                  (uint32_t)(page->attr >> 32), size);
+    } else {
+        return trusty_std_call32(dev, smcnr,
+                                 (uint32_t)page->attr,
+                                 (uint32_t)(page->attr >> 32), size);
+    }
+}
+
+int trusty_dev_init_ipc(struct trusty_dev *dev,
+                        struct ns_mem_page_info *buf, uint32_t buf_size)
+{
+    return trusty_call32_mem_buf(dev, SMC_SC_TRUSTY_IPC_CREATE_QL_DEV,
+                                 buf, buf_size);
+}
+
+int trusty_dev_exec_ipc(struct trusty_dev *dev,
+                        struct ns_mem_page_info *buf, uint32_t buf_size)
+{
+    return trusty_call32_mem_buf(dev, SMC_SC_TRUSTY_IPC_HANDLE_QL_DEV_CMD,
+                                 buf, buf_size);
+}
+
+int trusty_dev_shutdown_ipc(struct trusty_dev *dev,
+                            struct ns_mem_page_info *buf, uint32_t buf_size)
+{
+    return trusty_call32_mem_buf(dev, SMC_SC_TRUSTY_IPC_SHUTDOWN_QL_DEV,
+                                 buf, buf_size);
+}
+
+
+static int trusty_init_api_version(struct trusty_dev *dev)
+{
+    uint32_t api_version;
+
+    api_version = trusty_fast_call32(dev, SMC_FC_API_VERSION,
+                                     TRUSTY_API_VERSION_CURRENT, 0, 0);
+    if (api_version == SM_ERR_UNDEFINED_SMC)
+        api_version = 0;
+
+    if (api_version > TRUSTY_API_VERSION_CURRENT) {
+        trusty_error("unsupported trusty api version %u > %u\n",
+                     api_version, TRUSTY_API_VERSION_CURRENT);
+        return -1;
+    }
+
+    trusty_info("selected trusty api version: %u (requested %u)\n",
+                api_version, TRUSTY_API_VERSION_CURRENT);
+
+    dev->api_version = api_version;
+
+    return 0;
+}
+
+int trusty_dev_init(struct trusty_dev *dev, void *priv_data)
+{
+    trusty_assert(dev);
+
+    dev->priv_data = priv_data;
+    return trusty_init_api_version(dev);
+}
+
+int trusty_dev_shutdown(struct trusty_dev *dev)
+{
+    trusty_assert(dev);
+
+    dev->priv_data = NULL;
+    return 0;
+}
+
diff --git a/lib/trusty/ql-tipc/arch/arm/trusty_mem.c b/lib/trusty/ql-tipc/arch/arm/trusty_mem.c
new file mode 100644
index 00000000000..56d8348d3ce
--- /dev/null
+++ b/lib/trusty/ql-tipc/arch/arm/trusty_mem.c
@@ -0,0 +1,284 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <trusty/trusty_dev.h>
+#include <trusty/util.h>
+
+/* 48-bit physical address bits 47:12 */
+
+#define NS_PTE_PHYSADDR_SHIFT      12
+#define NS_PTE_PHYSADDR(pte)       ((pte) & 0xFFFFFFFFF000ULL)
+
+/* Access permissions bits 7:6
+ *      EL0     EL1
+ * 00   None    RW
+ * 01   RW      RW
+ * 10   None    RO
+ * 11   RO      RO
+ */
+#define NS_PTE_AP_SHIFT                    6
+#define NS_PTE_AP_MASK                     (0x3 << NS_PTE_AP_SHIFT)
+
+/* Memory type and cache attributes bits 55:48 */
+#define NS_PTE_MAIR_SHIFT                  48
+#define NS_PTE_MAIR_MASK                   (0x00FFULL << NS_PTE_MAIR_SHIFT)
+
+#define NS_PTE_MAIR_INNER_SHIFT            48
+#define NS_PTE_MAIR_INNER_MASK             (0x000FULL << NS_PTE_MAIR_INNER_SHIFT)
+
+#define NS_PTE_MAIR_OUTER_SHIFT            52
+#define NS_PTE_MAIR_OUTER_MASK             (0x000FULL << NS_PTE_MAIR_OUTER_SHIFT)
+
+/* Normal memory */
+#define NS_MAIR_NORMAL_CACHED_WB_RWA       0xFF /* inner and outer write back read/write allocate */
+#define NS_MAIR_NORMAL_CACHED_WT_RA        0xAA /* inner and outer write through read allocate */
+#define NS_MAIR_NORMAL_CACHED_WB_RA        0xEE /* inner and outer write back, read allocate */
+#define NS_MAIR_NORMAL_UNCACHED            0x44 /* uncached */
+
+/* Device memory */
+#define NS_MAIR_DEVICE_STRONGLY_ORDERED    0x00 /* nGnRnE (strongly ordered) */
+#define NS_MAIR_DEVICE                     0x04 /* nGnRE  (device) */
+#define NS_MAIR_DEVICE_GRE                 0x0C /* GRE */
+
+/* shareable attributes bits 9:8 */
+#define NS_PTE_SHAREABLE_SHIFT             8
+
+#define NS_NON_SHAREABLE                   0x0
+#define NS_OUTER_SHAREABLE                 0x2
+#define NS_INNER_SHAREABLE                 0x3
+
+typedef uintptr_t addr_t;
+typedef uintptr_t vaddr_t;
+typedef uintptr_t paddr_t;
+
+#if NS_ARCH_ARM64
+
+#define  PAR_F  (0x1 <<  0)
+
+/*
+ * ARM64
+ */
+
+/* Note: this will crash if called from user space */
+static void arm64_write_ATS1ExW(uint64_t vaddr)
+{
+    uint64_t _current_el;
+
+    __asm__ volatile("mrs %0, CurrentEL" : "=r" (_current_el));
+
+    _current_el = (_current_el >> 2) & 0x3;
+    switch (_current_el) {
+    case 0x1:
+        __asm__ volatile("at S1E1W, %0" :: "r" (vaddr));
+        break;
+    case 0x2:
+        __asm__ volatile("at S1E2W, %0" :: "r" (vaddr));
+        break;
+    case 0x3:
+    default:
+        trusty_fatal("Unsupported execution state: EL%u\n", _current_el );
+        break;
+    }
+
+    __asm__ volatile("isb" ::: "memory");
+}
+
+static uint64_t arm64_read_par64(void)
+{
+    uint64_t _val;
+    __asm__ volatile("mrs %0, par_el1" : "=r" (_val));
+    return _val;
+}
+
+
+static uint64_t va2par(vaddr_t va)
+{
+    uint64_t par;
+    unsigned long irq_state;
+
+    trusty_local_irq_disable(&irq_state);
+    arm64_write_ATS1ExW(va);
+    par = arm64_read_par64();
+    trusty_local_irq_restore(&irq_state);
+
+    return par;
+}
+
+static uint64_t par2attr(uint64_t par)
+{
+    uint64_t attr;
+
+    /* set phys address */
+    attr = NS_PTE_PHYSADDR(par);
+
+    /* cache attributes */
+    attr |= ((par >> 56) & 0xFF) << NS_PTE_MAIR_SHIFT;
+
+    /* shareable attributes */
+    attr |= ((par >> 7) & 0x03) << NS_PTE_SHAREABLE_SHIFT;
+
+    /* the memory is writable and accessible so leave AP field 0 */
+    attr |= 0x0 << NS_PTE_AP_SHIFT;
+
+    return attr;
+}
+
+#else
+
+#define  PAR_F     (0x1 <<  0)
+#define  PAR_SS    (0x1 <<  1)
+#define  PAR_SH    (0x1 <<  7)
+#define  PAR_NOS   (0x1 << 10)
+#define  PAR_LPAE  (0x1 << 11)
+
+/*
+ * ARM32
+ */
+
+/* Note: this will crash if called from user space */
+static void arm_write_ATS1xW(uint64_t vaddr)
+{
+    uint32_t _cpsr;
+
+    __asm__ volatile("mrs %0, cpsr" : "=r"(_cpsr));
+
+    if ((_cpsr & 0xF) == 0xa)
+        __asm__ volatile("mcr    p15, 4, %0, c7, c8, 1" : : "r"(vaddr));
+    else
+        __asm__ volatile("mcr    p15, 0, %0, c7, c8, 1" : : "r"(vaddr));
+}
+
+static uint64_t arm_read_par64(void)
+{
+    uint32_t lower, higher;
+
+    __asm__ volatile(
+        "mrc    p15, 0, %0, c7, c4, 0   \n"
+        "tst    %0, #(1 << 11)      @ LPAE / long desc format\n"
+        "moveq  %1, #0          \n"
+        "mrrcne p15, 0, %0, %1, c7  \n"
+         :"=r"(lower), "=r"(higher) : :
+    );
+
+    return ((uint64_t)higher << 32) | lower;
+}
+
+
+static uint8_t ish_to_mair[8] = {
+    0x04, /* 0b000 Non cacheble */
+    0x00, /* 0b001 Strongly ordered */
+    0xF0, /* 0b010 reserved */
+    0x04, /* 0b011 device */
+    0xF0, /* 0b100 reserved */
+    0x0F, /* 0b101 write back - write allocate */
+    0x0A, /* 0b110 write through */
+    0x0E, /* 0b111 write back - no write allocate */
+};
+
+static uint8_t osh_to_mair[4] = {
+    0x00, /* 0b00   Non-cacheable */
+    0x0F, /* 0b01   Write-back, Write-allocate */
+    0x0A, /* 0b10   Write-through, no Write-allocate */
+    0x0E, /* 0b11   Write-back, no Write-allocate */
+};
+
+static uint64_t par2attr(uint64_t par)
+{
+    uint64_t attr;
+
+    if (par & PAR_LPAE) {
+        /* set phys address */
+        attr = NS_PTE_PHYSADDR(par);
+
+        /* cache attributes */
+        attr |= ((par >> 56) & 0xFF) << NS_PTE_MAIR_SHIFT;
+
+        /* shareable attributes */
+        attr |= ((par >> 7) & 0x03) << NS_PTE_SHAREABLE_SHIFT;
+
+    } else {
+
+        /* set phys address */
+        trusty_assert((par & PAR_SS) == 0); /* super section not supported */
+        attr = NS_PTE_PHYSADDR(par);
+
+        /* cache attributes */
+        uint64_t inner = ((uint64_t)ish_to_mair[(par >> 4) & 0x7]) << NS_PTE_MAIR_INNER_SHIFT;
+        uint64_t outer = ((uint64_t)osh_to_mair[(par >> 2) & 0x3]) << NS_PTE_MAIR_OUTER_SHIFT;
+        uint64_t cache_attributes = (outer << 4) | inner;
+
+        /* Trusty does not support any kind of device memory, so we will force
+         * cache attributes to be NORMAL UNCACHED on the Trusty side.
+         */
+        if (cache_attributes == NS_MAIR_DEVICE_STRONGLY_ORDERED) {
+            attr |= ((uint64_t)NS_MAIR_NORMAL_UNCACHED << NS_PTE_MAIR_SHIFT);
+        } else {
+            attr |= inner;
+            attr |= outer;
+        }
+
+        /* shareable attributes */
+        if (par & PAR_SH) {
+            /* how to handle NOS bit ? */
+            attr |= ((uint64_t)NS_INNER_SHAREABLE) << NS_PTE_SHAREABLE_SHIFT;
+        } else {
+            attr |= ((uint64_t)NS_NON_SHAREABLE) << NS_PTE_SHAREABLE_SHIFT;
+        }
+    }
+
+    /* the memory is writable and accessible so leave AP field 0 */
+    attr |= 0x0 << NS_PTE_AP_SHIFT;
+
+    return attr;
+}
+
+static uint64_t va2par(vaddr_t va)
+{
+    uint64_t par;
+    unsigned long irq_state;
+
+    trusty_local_irq_disable(&irq_state);
+    arm_write_ATS1xW(va);
+    par = arm_read_par64();
+    trusty_local_irq_restore(&irq_state);
+
+    return par;
+}
+
+#endif /* ARM64 */
+
+
+int trusty_encode_page_info(struct ns_mem_page_info *inf, void *va)
+{
+    uint64_t par = va2par((vaddr_t)va);
+
+    if (par & PAR_F) {
+        return -1;
+    }
+
+    inf->attr = par2attr(par);
+
+    return 0;
+}
+
diff --git a/lib/trusty/ql-tipc/avb.c b/lib/trusty/ql-tipc/avb.c
new file mode 100644
index 00000000000..937cafc9106
--- /dev/null
+++ b/lib/trusty/ql-tipc/avb.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <trusty/avb.h>
+#include <trusty/rpmb.h>
+#include <trusty/trusty_ipc.h>
+#include <trusty/util.h>
+
+#define LOCAL_LOG 0
+
+static bool initialized;
+static int avb_tipc_version = 1;
+static struct trusty_ipc_chan avb_chan;
+
+static int avb_send_request(struct avb_message *msg, void *req, size_t req_len)
+{
+    struct trusty_ipc_iovec req_iovs[2] = {
+        { .base = msg, .len = sizeof(*msg) },
+        { .base = req, .len = req_len },
+    };
+
+    return trusty_ipc_send(&avb_chan, req_iovs, req ? 2 : 1, true);
+}
+
+static int avb_read_response(struct avb_message *msg, uint32_t cmd, void *resp,
+                             size_t resp_len)
+{
+    int rc;
+    struct trusty_ipc_iovec resp_iovs[2] = {
+        { .base = msg, .len = sizeof(*msg) },
+        { .base = resp, .len = resp_len },
+    };
+
+    rc = trusty_ipc_recv(&avb_chan, resp_iovs, resp ? 2 : 1, true);
+    if (rc < 0) {
+        trusty_error("failed (%d) to recv response\n", rc);
+        return rc;
+    }
+    if (msg->cmd != (cmd | AVB_RESP_BIT)) {
+        trusty_error("malformed response\n");
+        return TRUSTY_ERR_GENERIC;
+    }
+    /* return payload size */
+    return rc - sizeof(*msg);
+}
+
+/*
+ * Convenience function to send a request to the AVB service and read the
+ * response.
+ *
+ * @cmd: the command
+ * @req: the request buffer
+ * @req_size: size of the request buffer
+ * @resp: the response buffer
+ * @resp_size_p: pointer to the size of the response buffer. changed to the
+                 actual size of the response read from the secure side
+ */
+static int avb_do_tipc(uint32_t cmd, void *req, uint32_t req_size, void *resp,
+                       uint32_t *resp_size_p)
+{
+    int rc;
+    struct avb_message msg = { .cmd = cmd };
+
+    if (!initialized && cmd != AVB_GET_VERSION) {
+        trusty_error("%s: AVB TIPC client not initialized\n", __func__);
+        return TRUSTY_ERR_GENERIC;
+    }
+
+    rc = avb_send_request(&msg, req, req_size);
+    if (rc < 0) {
+        trusty_error("%s: failed (%d) to send AVB request\n", __func__, rc);
+        return rc;
+    }
+
+    uint32_t resp_size = resp_size_p ? *resp_size_p : 0;
+    rc = avb_read_response(&msg, cmd, resp, resp_size);
+    if (rc < 0) {
+        trusty_error("%s: failed (%d) to read AVB response\n", __func__, rc);
+        return rc;
+    }
+    /* change response size to actual response size */
+    if (resp_size_p && rc != *resp_size_p) {
+        *resp_size_p = rc;
+    }
+    if (msg.result != AVB_ERROR_NONE) {
+        trusty_error("%s: AVB service returned error (%d)\n", __func__,
+                     msg.result);
+        return TRUSTY_ERR_GENERIC;
+    }
+    return TRUSTY_ERR_NONE;
+}
+
+static int avb_get_version(uint32_t *version)
+{
+    int rc;
+    struct avb_get_version_resp resp;
+    uint32_t resp_size = sizeof(resp);
+
+    rc = avb_do_tipc(AVB_GET_VERSION, NULL, 0, &resp, &resp_size);
+
+    *version = resp.version;
+    return rc;
+}
+
+
+int avb_tipc_init(struct trusty_ipc_dev *dev)
+{
+    int rc;
+    uint32_t version = 0;
+
+    trusty_assert(dev);
+    trusty_assert(!initialized);
+
+    trusty_ipc_chan_init(&avb_chan, dev);
+    trusty_debug("Connecting to AVB service\n");
+
+    /* connect to AVB service and wait for connect to complete */
+    rc = trusty_ipc_connect(&avb_chan, AVB_PORT, true);
+    if (rc < 0) {
+        trusty_error("failed (%d) to connect to '%s'\n", rc, AVB_PORT);
+        return rc;
+    }
+
+    /* check for version mismatch */
+    rc = avb_get_version(&version);
+    if (rc != 0) {
+        trusty_error("Error getting version");
+        return TRUSTY_ERR_GENERIC;
+    }
+    if (version != avb_tipc_version) {
+        trusty_error("AVB TIPC version mismatch. Expected %u, received %u\n",
+                     avb_tipc_version, version);
+        return TRUSTY_ERR_GENERIC;
+    }
+
+    /* mark as initialized */
+    initialized = true;
+
+    return TRUSTY_ERR_NONE;
+}
+
+void avb_tipc_shutdown(struct trusty_ipc_dev *dev)
+{
+    if (!initialized)
+        return; /* nothing to do */
+
+    /* close channel */
+    trusty_ipc_close(&avb_chan);
+
+    initialized = false;
+}
+
+int trusty_read_rollback_index(uint32_t slot, uint64_t *value)
+{
+    int rc;
+    struct avb_rollback_req req = { .slot = slot, .value = 0 };
+    struct avb_rollback_resp resp;
+    uint32_t resp_size = sizeof(resp);
+
+    rc = avb_do_tipc(READ_ROLLBACK_INDEX, &req, sizeof(req), &resp,
+                     &resp_size);
+
+    *value = resp.value;
+    return rc;
+}
+
+int trusty_write_rollback_index(uint32_t slot, uint64_t value)
+{
+    int rc;
+    struct avb_rollback_req req = { .slot = slot, .value = value };
+    struct avb_rollback_resp resp;
+    uint32_t resp_size = sizeof(resp);
+
+    rc = avb_do_tipc(WRITE_ROLLBACK_INDEX, &req, sizeof(req), &resp,
+                     &resp_size);
+    return rc;
+}
+
+int trusty_read_permanent_attributes(uint8_t *attributes, uint32_t size)
+{
+    uint8_t resp_buf[AVB_MAX_BUFFER_LENGTH];
+    uint32_t resp_size = AVB_MAX_BUFFER_LENGTH;
+    int rc = avb_do_tipc(READ_PERMANENT_ATTRIBUTES, NULL, 0, resp_buf,
+                         &resp_size);
+    if (rc != 0) {
+        return rc;
+    }
+    /* ensure caller passed size matches size returned by Trusty */
+    if (size != resp_size) {
+        return TRUSTY_ERR_INVALID_ARGS;
+    }
+    trusty_memcpy(attributes, resp_buf, resp_size);
+    return rc;
+}
+
+int trusty_write_permanent_attributes(uint8_t *attributes, uint32_t size)
+{
+    return avb_do_tipc(WRITE_PERMANENT_ATTRIBUTES, attributes, size, NULL,
+                       NULL);
+}
+
+int trusty_read_vbmeta_public_key(uint8_t *publickey, uint32_t size)
+{
+    uint8_t resp_buf[AVB_MAX_BUFFER_LENGTH];
+    uint32_t resp_size = AVB_MAX_BUFFER_LENGTH;
+    int rc = avb_do_tipc(READ_VBMETA_PUBLIC_KEY, NULL, 0, resp_buf,
+                         &resp_size);
+    if (rc != 0) {
+        return rc;
+    }
+    /* ensure caller passed size matches size returned by Trusty */
+    if (size < resp_size) {
+        return TRUSTY_ERR_INVALID_ARGS;
+    }
+    trusty_memcpy(publickey, resp_buf, resp_size);
+    return rc;
+}
+
+int trusty_write_vbmeta_public_key(uint8_t *publickey, uint32_t size)
+{
+    return avb_do_tipc(WRITE_VBMETA_PUBLIC_KEY, publickey, size, NULL,
+                       NULL);
+}
+
+int trusty_read_lock_state(uint8_t *lock_state)
+{
+    uint32_t resp_size = sizeof(*lock_state);
+    return avb_do_tipc(READ_LOCK_STATE, NULL, 0, lock_state,
+                       &resp_size);
+}
+
+int trusty_write_lock_state(uint8_t lock_state)
+{
+    return avb_do_tipc(WRITE_LOCK_STATE, &lock_state, sizeof(lock_state), NULL,
+                       NULL);
+}
+
+int trusty_lock_boot_state(void)
+{
+    return avb_do_tipc(LOCK_BOOT_STATE, NULL, 0, NULL, NULL);
+}
+
+int trusty_read_oem_unlock_device_permission(uint8_t *oem_device_unlock)
+{
+    uint32_t resp_size = sizeof(*oem_device_unlock);
+    return avb_do_tipc(READ_OEM_UNLOCK_DEVICE_PERMISSION, NULL, 0, oem_device_unlock,
+                       &resp_size);
+}
diff --git a/lib/trusty/ql-tipc/hwcrypto.c b/lib/trusty/ql-tipc/hwcrypto.c
new file mode 100644
index 00000000000..21c58826c89
--- /dev/null
+++ b/lib/trusty/ql-tipc/hwcrypto.c
@@ -0,0 +1,329 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ * Copyright NXP 2018
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <trusty/hwcrypto.h>
+#include <trusty/rpmb.h>
+#include <trusty/trusty_ipc.h>
+#include <trusty/util.h>
+#include <memalign.h>
+#include "common.h"
+#include <cpu_func.h>
+#include <hang.h>
+#include <trusty/keymaster_serializable.h>
+
+#define LOCAL_LOG 0
+#define CAAM_KB_HEADER_LEN 48
+
+static bool initialized;
+static struct trusty_ipc_chan hwcrypto_chan;
+
+static int hwcrypto_send_request(struct hwcrypto_message *msg, void *req, size_t req_len)
+{
+    struct trusty_ipc_iovec req_iovs[2] = {
+        { .base = msg, .len = sizeof(*msg) },
+        { .base = req, .len = req_len },
+    };
+
+    return trusty_ipc_send(&hwcrypto_chan, req_iovs, req ? 2 : 1, true);
+}
+
+static int hwcrypto_read_response(struct hwcrypto_message *msg, uint32_t cmd, void *resp,
+                             size_t resp_len)
+{
+    int rc;
+    struct trusty_ipc_iovec resp_iovs[2] = {
+        { .base = msg, .len = sizeof(*msg) },
+        { .base = resp, .len = resp_len },
+    };
+
+    rc = trusty_ipc_recv(&hwcrypto_chan, resp_iovs, resp ? 2 : 1, true);
+    if (rc < 0) {
+        trusty_error("failed (%d) to recv response\n", rc);
+        return rc;
+    }
+    if (msg->cmd != (cmd | HWCRYPTO_RESP_BIT)) {
+        trusty_error("malformed response\n");
+        return TRUSTY_ERR_GENERIC;
+    }
+    /* return payload size */
+    return rc - sizeof(*msg);
+}
+
+/*
+ * Convenience function to send a request to the hwcrypto service and read the
+ * response.
+ *
+ * @cmd: the command
+ * @req: the request buffer
+ * @req_size: size of the request buffer
+ * @resp: the response buffer
+ * @resp_size_p: pointer to the size of the response buffer. changed to the
+                 actual size of the response read from the secure side
+ */
+static int hwcrypto_do_tipc(uint32_t cmd, void *req, uint32_t req_size, void *resp,
+                       uint32_t *resp_size_p)
+{
+    int rc;
+    struct hwcrypto_message msg = { .cmd = cmd };
+
+    if (!initialized) {
+        trusty_error("%s: HWCRYPTO TIPC client not initialized\n", __func__);
+        return TRUSTY_ERR_GENERIC;
+    }
+
+    rc = hwcrypto_send_request(&msg, req, req_size);
+    if (rc < 0) {
+        trusty_error("%s: failed (%d) to send hwcrypto request\n", __func__, rc);
+        return rc;
+    }
+
+    uint32_t resp_size = resp_size_p ? *resp_size_p : 0;
+    rc = hwcrypto_read_response(&msg, cmd, resp, resp_size);
+    if (rc < 0) {
+        trusty_error("%s: failed (%d) to read HWCRYPTO response\n", __func__, rc);
+        return rc;
+    }
+    /* change response size to actual response size */
+    if (resp_size_p && rc != *resp_size_p) {
+        *resp_size_p = rc;
+    }
+    if (msg.result != HWCRYPTO_ERROR_NONE) {
+        trusty_error("%s: HWCRYPTO service returned error (%d)\n", __func__,
+                     msg.result);
+        return TRUSTY_ERR_GENERIC;
+    }
+    return TRUSTY_ERR_NONE;
+}
+
+int hwcrypto_tipc_init(struct trusty_ipc_dev *dev)
+{
+    int rc;
+
+    trusty_assert(dev);
+    trusty_assert(!initialized);
+
+    trusty_ipc_chan_init(&hwcrypto_chan, dev);
+    trusty_debug("Connecting to hwcrypto service\n");
+
+    /* connect to hwcrypto service and wait for connect to complete */
+    rc = trusty_ipc_connect(&hwcrypto_chan, HWCRYPTO_PORT, true);
+    if (rc < 0) {
+        trusty_error("failed (%d) to connect to '%s'\n", rc, HWCRYPTO_PORT);
+        return rc;
+    }
+
+    /* mark as initialized */
+    initialized = true;
+
+    return TRUSTY_ERR_NONE;
+}
+
+void hwcrypto_tipc_shutdown(struct trusty_ipc_dev *dev)
+{
+    if (!initialized)
+        return; /* nothing to do */
+
+    /* close channel */
+    trusty_ipc_close(&hwcrypto_chan);
+
+    initialized = false;
+}
+
+int hwcrypto_hash(uint32_t in_addr, uint32_t in_len, uint32_t out_addr,
+                  uint32_t out_len, enum hwcrypto_hash_algo algo)
+{
+    hwcrypto_hash_msg req;
+    unsigned long start, end;
+
+    /* check the address */
+    if (in_addr == 0 || out_addr == 0)
+        return TRUSTY_ERR_INVALID_ARGS;
+    /* fill the request buffer */
+    req.in_addr  = in_addr;
+    req.out_addr = out_addr;
+    req.in_len   = in_len;
+    req.out_len  = out_len;
+    req.algo     = algo;
+
+    /* flush dcache for input buffer */
+    start = (unsigned long)in_addr & ~(ARCH_DMA_MINALIGN - 1);
+    end   = ALIGN((unsigned long)in_addr + in_len, ARCH_DMA_MINALIGN);
+    flush_dcache_range(start, end);
+
+    /* invalidate dcache for output buffer */
+    start = (unsigned long)out_addr & ~(ARCH_DMA_MINALIGN - 1);
+    end   = ALIGN((unsigned long)out_addr + out_len, ARCH_DMA_MINALIGN);
+    invalidate_dcache_range(start, end);
+
+    int rc = hwcrypto_do_tipc(HWCRYPTO_HASH, (void*)&req,
+                              sizeof(req), NULL, 0);
+
+    /* invalidate the dcache again before read to avoid coherency
+     * problem caused by speculative memory access by the CPU.
+     */
+    invalidate_dcache_range(start, end);
+
+    return rc;
+}
+
+int hwcrypto_gen_blob(uint32_t plain_pa,
+                      uint32_t plain_size, uint32_t blob_pa)
+{
+    hwcrypto_blob_msg req;
+    unsigned long start, end;
+
+    /* check the address */
+    if (plain_pa == 0 || blob_pa == 0)
+        return TRUSTY_ERR_INVALID_ARGS;
+    /* fill the request buffer */
+    req.plain_pa   = plain_pa;
+    req.plain_size = plain_size;
+    req.blob_pa    = blob_pa;
+
+    /* flush dcache for input buffer */
+    start = (unsigned long)plain_pa & ~(ARCH_DMA_MINALIGN - 1);
+    end   = ALIGN((unsigned long)plain_pa + plain_size, ARCH_DMA_MINALIGN);
+    flush_dcache_range(start, end);
+
+    /* invalidate dcache for output buffer */
+    start = (unsigned long)blob_pa & ~(ARCH_DMA_MINALIGN - 1);
+    end   = ALIGN((unsigned long)blob_pa + plain_size +
+                  CAAM_KB_HEADER_LEN, ARCH_DMA_MINALIGN);
+    invalidate_dcache_range(start, end);
+
+    int rc = hwcrypto_do_tipc(HWCRYPTO_ENCAP_BLOB, (void*)&req,
+                              sizeof(req), NULL, 0);
+
+    /* invalidate the dcache again before read to avoid coherency
+     * problem caused by speculative memory access by the CPU.
+     */
+    invalidate_dcache_range(start, end);
+    return rc;
+}
+
+int hwcrypto_gen_rng(uint32_t buf, uint32_t len)
+{
+    hwcrypto_rng_msg req;
+    unsigned long start, end;
+
+    /* check the address */
+    if (buf == 0)
+        return TRUSTY_ERR_INVALID_ARGS;
+    /* fill the request buffer */
+    req.buf = buf;
+    req.len = len;
+
+    /* invalidate dcache for output buffer */
+    start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
+    end   = ALIGN((unsigned long)buf + len, ARCH_DMA_MINALIGN);
+    invalidate_dcache_range(start, end);
+
+    int rc = hwcrypto_do_tipc(HWCRYPTO_GEN_RNG, (void*)&req,
+                              sizeof(req), NULL, 0);
+
+    /* invalidate the dcache again before read to avoid coherency
+     * problem caused by speculative memory access by the CPU.
+     */
+    invalidate_dcache_range(start, end);
+    return rc;
+}
+
+int hwcrypto_gen_bkek(uint32_t buf, uint32_t len)
+{
+    hwcrypto_bkek_msg req;
+    unsigned long start, end;
+
+    /* check the address */
+    if (buf == 0)
+        return TRUSTY_ERR_INVALID_ARGS;
+    /* fill the request buffer */
+    req.buf = buf;
+    req.len = len;
+
+    /* invalidate dcache for output buffer */
+    start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
+    end   = ALIGN((unsigned long)buf + len, ARCH_DMA_MINALIGN);
+    invalidate_dcache_range(start, end);
+
+    int rc = hwcrypto_do_tipc(HWCRYPTO_GEN_BKEK, (void*)&req,
+                              sizeof(req), NULL, 0);
+
+    /* invalidate the dcache again before read to avoid coherency
+     * problem caused by speculative memory access by the CPU.
+     */
+    invalidate_dcache_range(start, end);
+    return rc;
+}
+
+int hwcrypto_lock_boot_state(void)
+{
+    return hwcrypto_do_tipc(HWCRYPTO_LOCK_BOOT_STATE, NULL, 0, NULL, 0);
+}
+
+int hwcrypto_provision_wv_key(const char *data, uint32_t data_size)
+{
+    uint8_t *req = NULL, *tmp;
+    /* sanity check */
+    if (!data || !data_size)
+        return TRUSTY_ERR_INVALID_ARGS;
+
+    /* serialize the request */
+    req = trusty_calloc(data_size + sizeof(data_size), 1);
+    if (!req) {
+        return TRUSTY_ERR_NO_MEMORY;
+    }
+    tmp = append_sized_buf_to_buf(req, (uint8_t *)data, data_size);
+
+    int rc = hwcrypto_do_tipc(HWCRYPTO_PROVISION_WV_KEY, (void*)req,
+                              data_size + sizeof(data_size), NULL, 0);
+
+    if (req)
+        trusty_free(req);
+
+    return rc;
+}
+
+int hwcrypto_provision_wv_key_enc(const char *data, uint32_t data_size)
+{
+    uint8_t *req = NULL, *tmp;
+    /* sanity check */
+    if (!data || !data_size)
+        return TRUSTY_ERR_INVALID_ARGS;
+
+    /* serialize the request */
+    req = trusty_calloc(data_size + sizeof(data_size), 1);
+    if (!req) {
+        return TRUSTY_ERR_NO_MEMORY;
+    }
+    tmp = append_sized_buf_to_buf(req, (uint8_t *)data, data_size);
+
+    int rc = hwcrypto_do_tipc(HWCRYPTO_PROVISION_WV_KEY_ENC, (void*)req,
+                              data_size + sizeof(data_size), NULL, 0);
+
+    if (req)
+        trusty_free(req);
+
+    return rc;
+}
diff --git a/lib/trusty/ql-tipc/imx_snvs.c b/lib/trusty/ql-tipc/imx_snvs.c
new file mode 100644
index 00000000000..972cb427f3c
--- /dev/null
+++ b/lib/trusty/ql-tipc/imx_snvs.c
@@ -0,0 +1,53 @@
+#include <trusty/trusty_ipc.h>
+#include <trusty/util.h>
+#include <trusty/imx_snvs.h>
+#include <trusty/trusty_dev.h>
+#include "arch/arm/smcall.h"
+
+#define SMC_ENTITY_SNVS_RTC 53
+#define SMC_SNVS_PROBE SMC_FASTCALL_NR(SMC_ENTITY_SNVS_RTC, 0)
+#define SMC_SNVS_REGS_OP SMC_FASTCALL_NR(SMC_ENTITY_SNVS_RTC, 1)
+#define SMC_SNVS_LPCR_OP SMC_FASTCALL_NR(SMC_ENTITY_SNVS_RTC, 2)
+
+#define OPT_READ 0x1
+#define OPT_WRITE 0x2
+
+static struct trusty_ipc_dev *_dev = NULL;
+
+uint32_t trusty_snvs_read(uint32_t target) {
+    if (!_dev) {
+        trusty_error("trusty imx snvs driver is not initialized!\n");
+	return 0;
+    }
+    return trusty_simple_fast_call32(SMC_SNVS_REGS_OP, target, OPT_READ, 0);
+}
+
+void trusty_snvs_write(uint32_t target, uint32_t value) {
+    if (!_dev) {
+        trusty_error("trusty imx snvs driver is not initialized!\n");
+	return;
+    }
+    trusty_simple_fast_call32(SMC_SNVS_REGS_OP, target, OPT_WRITE, value);
+}
+
+void trusty_snvs_update_lpcr(uint32_t target, uint32_t enable) {
+    if (!_dev) {
+        trusty_error("trusty imx snvs driver is not initialized!\n");
+	return;
+    }
+    trusty_simple_fast_call32(SMC_SNVS_LPCR_OP, target, enable, 0);
+}
+
+int imx_snvs_init(struct trusty_ipc_dev *dev)
+{
+    trusty_assert(dev);
+    int error;
+    error = trusty_simple_fast_call32(SMC_SNVS_PROBE, 0, 0, 0);
+    if (error < 0) {
+        trusty_error("trusty imx snvs driver initialize failed! error=%d\n", error);
+        return error;
+    }
+    _dev = dev;
+    return 0;
+
+}
diff --git a/lib/trusty/ql-tipc/ipc.c b/lib/trusty/ql-tipc/ipc.c
new file mode 100644
index 00000000000..d1eb5ef456b
--- /dev/null
+++ b/lib/trusty/ql-tipc/ipc.c
@@ -0,0 +1,310 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <trusty/trusty_ipc.h>
+#include <trusty/util.h>
+
+#define LOCAL_LOG 0
+
+static int sync_ipc_on_connect_complete(struct trusty_ipc_chan *chan)
+{
+    trusty_assert(chan);
+
+    chan->complete = 1;
+    return TRUSTY_EVENT_HANDLED;
+}
+
+static int sync_ipc_on_message(struct trusty_ipc_chan *chan)
+{
+    trusty_assert(chan);
+
+    chan->complete = 1;
+    return TRUSTY_EVENT_HANDLED;
+}
+
+static int sync_ipc_on_disconnect(struct trusty_ipc_chan *chan)
+{
+    trusty_assert(chan);
+
+    chan->complete = TRUSTY_ERR_CHANNEL_CLOSED;
+    return TRUSTY_EVENT_HANDLED;
+}
+
+static int wait_for_complete(struct trusty_ipc_chan *chan)
+{
+    int rc;
+
+    chan->complete = 0;
+    for (;;) {
+        rc = trusty_ipc_poll_for_event(chan->dev);
+        if (rc < 0)
+            return rc;
+
+        if (chan->complete)
+            break;
+
+        if (rc == TRUSTY_EVENT_NONE)
+            trusty_ipc_dev_idle(chan->dev);
+    }
+
+    return chan->complete;
+}
+
+static int wait_for_connect(struct trusty_ipc_chan *chan)
+{
+    trusty_debug("%s: chan %x: waiting for connect\n", __func__,
+                 (int)chan->handle);
+    return wait_for_complete(chan);
+}
+
+static int wait_for_send(struct trusty_ipc_chan *chan)
+{
+    trusty_debug("%s: chan %d: waiting for send\n", __func__, chan->handle);
+    return wait_for_complete(chan);
+}
+
+static int wait_for_reply(struct trusty_ipc_chan *chan)
+{
+    trusty_debug("%s: chan %d: waiting for reply\n", __func__, chan->handle);
+    return wait_for_complete(chan);
+}
+
+static struct trusty_ipc_ops sync_ipc_ops = {
+    .on_connect_complete = sync_ipc_on_connect_complete,
+    .on_message = sync_ipc_on_message,
+    .on_disconnect = sync_ipc_on_disconnect,
+};
+
+void trusty_ipc_chan_init(struct trusty_ipc_chan *chan,
+                          struct trusty_ipc_dev *dev)
+{
+    trusty_assert(chan);
+    trusty_assert(dev);
+
+    trusty_memset(chan, 0, sizeof(*chan));
+
+    chan->handle = INVALID_IPC_HANDLE;
+    chan->dev = dev;
+    chan->ops = &sync_ipc_ops;
+    chan->ops_ctx = chan;
+}
+
+int trusty_ipc_connect(struct trusty_ipc_chan *chan, const char *port,
+                       bool wait)
+{
+    int rc;
+
+    trusty_assert(chan);
+    trusty_assert(chan->dev);
+    trusty_assert(chan->handle == INVALID_IPC_HANDLE);
+    trusty_assert(port);
+
+    rc = trusty_ipc_dev_connect(chan->dev, port, (uint64_t)(uintptr_t)chan);
+    if (rc < 0) {
+        trusty_error("%s: init connection failed (%d)\n", __func__, rc);
+        return rc;
+    }
+    chan->handle = (handle_t)rc;
+    trusty_debug("chan->handle: %x\n", (int)chan->handle);
+
+    /* got valid channel */
+    if (wait) {
+        rc = wait_for_connect(chan);
+        if (rc < 0) {
+            trusty_error("%s: wait for connect failed (%d)\n", __func__, rc);
+            trusty_ipc_close(chan);
+        }
+    }
+
+    return rc;
+}
+
+int trusty_ipc_close(struct trusty_ipc_chan *chan)
+{
+    int rc;
+
+    trusty_assert(chan);
+
+    rc = trusty_ipc_dev_close(chan->dev, chan->handle);
+    chan->handle = INVALID_IPC_HANDLE;
+
+    return rc;
+}
+
+int trusty_ipc_send(struct trusty_ipc_chan *chan,
+                    const struct trusty_ipc_iovec *iovs, size_t iovs_cnt,
+                    bool wait)
+{
+    int rc;
+
+    trusty_assert(chan);
+    trusty_assert(chan->dev);
+    trusty_assert(chan->handle);
+
+Again:
+    rc = trusty_ipc_dev_send(chan->dev, chan->handle, iovs, iovs_cnt);
+    if (rc == TRUSTY_ERR_SEND_BLOCKED) {
+        if (wait) {
+            rc = wait_for_send(chan);
+            if (rc < 0) {
+                trusty_error("%s: wait to send failed (%d)\n", __func__, rc);
+                return rc;
+            }
+            goto Again;
+        }
+    }
+    return rc;
+}
+
+extern bool proxy_resp_flag;
+
+int trusty_ipc_recv(struct trusty_ipc_chan *chan,
+                    const struct trusty_ipc_iovec *iovs, size_t iovs_cnt,
+                    bool wait)
+{
+    int rc;
+    trusty_assert(chan);
+    trusty_assert(chan->dev);
+    trusty_assert(chan->handle);
+
+    if (wait) {
+        rc = wait_for_reply(chan);
+        if (rc < 0) {
+            trusty_error("%s: wait to reply failed (%d)\n", __func__, rc);
+            return rc;
+        }
+    }
+
+    /* Return directly if the iovs have been received.  */
+    if (!proxy_resp_flag) {
+        rc = trusty_ipc_dev_recv(chan->dev, chan->handle, iovs, iovs_cnt);
+        if (rc < 0)
+            trusty_error("%s: ipc recv failed (%d)\n", __func__, rc);
+    } else
+        rc = 0;
+
+    return rc;
+}
+
+int trusty_ipc_poll_for_event(struct trusty_ipc_dev *ipc_dev)
+{
+    int rc;
+    struct trusty_ipc_event evt;
+    struct trusty_ipc_chan *chan;
+
+    trusty_assert(dev);
+
+    rc = trusty_ipc_dev_get_event(ipc_dev, 0, &evt);
+    if (rc) {
+        trusty_error("%s: get event failed (%d)\n", __func__, rc);
+        return rc;
+    }
+
+    /* check if we have an event */
+    if (!evt.event) {
+        trusty_debug("%s: no event\n", __func__);
+        return TRUSTY_EVENT_NONE;
+    }
+
+    chan = (struct trusty_ipc_chan *)(uintptr_t)evt.cookie;
+    trusty_assert(chan && chan->ops);
+
+    /* check if we have raw event handler */
+    if (chan->ops->on_raw_event) {
+        /* invoke it first */
+        rc = chan->ops->on_raw_event(chan, &evt);
+        if (rc < 0) {
+            trusty_error("%s: chan %d: raw event cb returned (%d)\n", __func__,
+                         chan->handle, rc);
+            return rc;
+        }
+        if (rc > 0)
+            return rc; /* handled */
+    }
+
+    if (evt.event & IPC_HANDLE_POLL_ERROR) {
+        /* something is very wrong */
+        trusty_error("%s: chan %d: chan in error state\n", __func__,
+                     chan->handle);
+        return TRUSTY_ERR_GENERIC;
+    }
+
+    /* send unblocked should be handled first as it is edge truggered event */
+    if (evt.event & IPC_HANDLE_POLL_SEND_UNBLOCKED) {
+        if (chan->ops->on_send_unblocked) {
+            rc = chan->ops->on_send_unblocked(chan);
+            if (rc < 0) {
+                trusty_error("%s: chan %d: send unblocked cb returned (%d)\n",
+                             __func__, chan->handle, rc);
+                return rc;
+            }
+            if (rc > 0)
+                return rc; /* handled */
+        }
+    }
+
+    /* check for connection complete */
+    if (evt.event & IPC_HANDLE_POLL_READY) {
+        if (chan->ops->on_connect_complete) {
+            rc = chan->ops->on_connect_complete(chan);
+            if (rc < 0) {
+                trusty_error("%s: chan %d: ready cb returned (%d)\n", __func__,
+                             chan->handle, rc);
+                return rc;
+            }
+            if (rc > 0)
+                return rc; /* handled */
+        }
+    }
+
+    /* check for incomming messages */
+    if (evt.event & IPC_HANDLE_POLL_MSG) {
+        if (chan->ops->on_message) {
+            rc = chan->ops->on_message(chan);
+            if (rc < 0) {
+                trusty_error("%s: chan %d: msg cb returned (%d)\n", __func__,
+                             chan->handle, rc);
+                return rc;
+            }
+            if (rc > 0)
+                return rc;
+        }
+    }
+
+    /* check for hangups */
+    if (evt.event & IPC_HANDLE_POLL_HUP) {
+        if (chan->ops->on_disconnect) {
+            rc = chan->ops->on_disconnect(chan);
+            if (rc < 0) {
+                trusty_error("%s: chan %d: hup cb returned (%d)\n", __func__,
+                             chan->handle, rc);
+                return rc;
+            }
+            if (rc > 0)
+                return rc;
+        }
+    }
+
+    return TRUSTY_ERR_NONE;
+}
diff --git a/lib/trusty/ql-tipc/ipc_dev.c b/lib/trusty/ql-tipc/ipc_dev.c
new file mode 100644
index 00000000000..720acf22be0
--- /dev/null
+++ b/lib/trusty/ql-tipc/ipc_dev.c
@@ -0,0 +1,458 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <trusty/trusty_dev.h>
+#include <trusty/trusty_ipc.h>
+#include <trusty/trusty_mem.h>
+#include <trusty/util.h>
+
+#define NS_PTE_PHYSADDR(pte)       ((pte) & 0xFFFFFFFFF000ULL)
+
+#define QL_TIPC_DEV_RESP     0x8000
+#define QL_TIPC_DEV_CONNECT     0x1
+#define QL_TIPC_DEV_GET_EVENT   0x2
+#define QL_TIPC_DEV_SEND        0x3
+#define QL_TIPC_DEV_RECV        0x4
+#define QL_TIPC_DEV_DISCONNECT  0x5
+
+#define LOCAL_LOG 0
+
+struct trusty_ipc_cmd_hdr {
+    uint16_t opcode;
+    uint16_t flags;
+    uint32_t status;
+    uint32_t handle;
+    uint32_t payload_len;
+    uint8_t  payload[0];
+};
+
+struct trusty_ipc_wait_req {
+    uint64_t reserved;
+};
+
+struct trusty_ipc_connect_req {
+    uint64_t cookie;
+    uint64_t reserved;
+    uint8_t  name[0];
+};
+
+static size_t iovec_size(const struct trusty_ipc_iovec *iovs, size_t iovs_cnt)
+{
+    size_t i;
+    size_t cb = 0;
+
+    trusty_assert(iovs);
+
+    for (i = 0; i < iovs_cnt; i++) {
+        cb += iovs[i].len;
+    }
+
+    return cb;
+}
+
+static size_t iovec_to_buf(void *buf, size_t buf_len,
+                           const struct trusty_ipc_iovec *iovs, size_t iovs_cnt)
+{
+    size_t i;
+    size_t buf_pos = 0;
+
+    trusty_assert(iovs);
+
+    for (i = 0; i < iovs_cnt; i++) {
+        size_t to_copy = (size_t)iovs[i].len;
+
+        if (!to_copy)
+            continue;
+
+        if (to_copy > buf_len)
+            to_copy = buf_len;
+
+        trusty_memcpy((uint8_t *)buf + buf_pos, iovs[i].base, to_copy);
+
+        buf_pos += to_copy;
+        buf_len -= to_copy;
+
+        if (buf_len == 0)
+            break;
+    }
+
+    return buf_pos;
+}
+
+static size_t buf_to_iovec(const struct trusty_ipc_iovec *iovs, size_t iovs_cnt,
+                           const void *buf, size_t buf_len)
+{
+    size_t i;
+    size_t copied = 0;
+    const uint8_t *buf_ptr = buf;
+
+    trusty_assert(buf_ptr);
+    trusty_assert(iovs);
+
+    if (iovs_cnt == 0 || buf_len == 0)
+        return 0;
+
+    for (i = 0; i < iovs_cnt; i++) {
+        size_t to_copy = buf_len;
+
+        if (to_copy > iovs[i].len)
+            to_copy = iovs[i].len;
+
+        if (!to_copy)
+            continue;
+
+        trusty_memcpy(iovs[i].base, buf_ptr, to_copy);
+
+        copied  += to_copy;
+        buf_ptr += to_copy;
+        buf_len -= to_copy;
+
+        if (buf_len == 0)
+            break;
+    }
+
+    return copied;
+}
+
+static int check_response(struct trusty_ipc_dev *dev,
+                          volatile struct trusty_ipc_cmd_hdr *hdr, uint16_t cmd)
+{
+    if (hdr->opcode != (cmd | QL_TIPC_DEV_RESP)) {
+        /* malformed response */
+        trusty_error("%s: malformed response cmd: 0x%x\n",
+                     __func__, hdr->opcode);
+        return TRUSTY_ERR_SECOS_ERR;
+    }
+
+    if (hdr->status) {
+        /* secure OS responded with error: TODO need error code */
+        trusty_error("%s: cmd 0x%x: status = %d\n",
+                     __func__, hdr->opcode, hdr->status);
+        return TRUSTY_ERR_SECOS_ERR;
+    }
+
+    return TRUSTY_ERR_NONE;
+}
+
+int trusty_ipc_dev_create(struct trusty_ipc_dev **idev,
+                          struct trusty_dev *tdev,
+                          size_t shared_buf_size)
+{
+    int rc;
+    struct trusty_ipc_dev *dev;
+
+    trusty_assert(idev);
+    trusty_assert(!(shared_buf_size % PAGE_SIZE));
+    trusty_debug("%s: Create new Trusty IPC device (%zu)\n", __func__,
+                 shared_buf_size);
+
+    /* allocate device context */
+    dev = trusty_calloc(1, sizeof(*dev));
+    if (!dev) {
+        trusty_error("%s: failed to allocate Trusty IPC device\n", __func__);
+        return TRUSTY_ERR_NO_MEMORY;
+    }
+    dev->tdev = tdev;
+
+    /* allocate shared buffer */
+    dev->buf_size = shared_buf_size;
+    dev->buf_vaddr = trusty_alloc_pages(shared_buf_size / PAGE_SIZE);
+    if (!dev->buf_vaddr) {
+        trusty_error("%s: failed to allocate shared memory\n", __func__);
+        rc = TRUSTY_ERR_NO_MEMORY;
+        goto err_alloc_pages;
+    }
+
+    /* Get memory attributes */
+    rc = trusty_encode_page_info(&dev->buf_ns, dev->buf_vaddr);
+    if (rc != 0) {
+        trusty_error("%s: failed to get shared memory attributes\n", __func__);
+        rc = TRUSTY_ERR_GENERIC;
+        goto err_page_info;
+    }
+    /* call secure OS to register shared buffer */
+    rc = trusty_dev_init_ipc(dev->tdev, &dev->buf_ns, dev->buf_size);
+    if (rc != 0) {
+        trusty_error("%s: failed (%d) to create Trusty IPC device\n",
+                     __func__, rc);
+        rc = TRUSTY_ERR_SECOS_ERR;
+        goto err_create_sec_dev;
+    }
+
+    trusty_debug("%s: new Trusty IPC device (%p)\n", __func__, dev);
+
+    *idev = dev;
+    return TRUSTY_ERR_NONE;
+
+err_page_info:
+err_create_sec_dev:
+    trusty_free_pages(dev->buf_vaddr, dev->buf_size / PAGE_SIZE);
+err_alloc_pages:
+    trusty_free(dev);
+    return rc;
+}
+
+void trusty_ipc_dev_shutdown(struct trusty_ipc_dev *dev)
+{
+    int rc;
+    trusty_assert(dev);
+
+    trusty_debug("%s: shutting down Trusty IPC device (%p)\n", __func__, dev);
+
+    /* shutdown Trusty IPC device */
+    rc = trusty_dev_shutdown_ipc(dev->tdev, &dev->buf_ns, dev->buf_size);
+    trusty_assert(!rc);
+    if (rc != 0) {
+        trusty_error("%s: failed (%d) to shutdown Trusty IPC device\n",
+                     __func__, rc);
+    }
+    trusty_free_pages(dev->buf_vaddr, dev->buf_size / PAGE_SIZE);
+    trusty_free(dev);
+}
+
+int trusty_ipc_dev_connect(struct trusty_ipc_dev *dev, const char *port,
+                           uint64_t cookie)
+{
+    int rc;
+    size_t port_len;
+    volatile struct trusty_ipc_cmd_hdr *cmd;
+    struct trusty_ipc_connect_req *req;
+
+    trusty_assert(dev);
+    trusty_assert(port);
+
+    trusty_debug("%s: connecting to '%s'\n", __func__, port);
+
+    /* check port name length */
+    port_len = trusty_strlen(port) + 1;
+    if (port_len > (dev->buf_size - sizeof(*cmd) + sizeof(*req))) {
+        /* it would not fit into buffer */
+        trusty_error("%s: port name is too long (%zu)\n", __func__, port_len);
+        return TRUSTY_ERR_INVALID_ARGS;
+    }
+
+    /* prepare command */
+    cmd = dev->buf_vaddr;
+    trusty_memset((void *)cmd, 0, sizeof(*cmd));
+    cmd->opcode = QL_TIPC_DEV_CONNECT;
+
+    /* prepare payload  */
+    req = (struct trusty_ipc_connect_req *)cmd->payload;
+    trusty_memset((void *)req, 0, sizeof(*req));
+    req->cookie = cookie;
+    trusty_strcpy((char *)req->name, port);
+    cmd->payload_len = sizeof(*req) + port_len;
+
+    /* call secure os */
+    rc = trusty_dev_exec_ipc(dev->tdev,
+                             &dev->buf_ns, sizeof(*cmd) + cmd->payload_len);
+    if (rc) {
+        /* secure OS returned an error */
+        trusty_error("%s: secure OS returned (%d)\n", __func__, rc);
+        return TRUSTY_ERR_SECOS_ERR;
+    }
+
+    rc = check_response(dev, cmd, QL_TIPC_DEV_CONNECT);
+    if (rc) {
+        trusty_error("%s: connect cmd failed (%d)\n", __func__, rc);
+        return rc;
+    }
+
+    /* success */
+    return cmd->handle;
+}
+
+int trusty_ipc_dev_close(struct trusty_ipc_dev *dev, handle_t handle)
+{
+    int rc;
+    volatile struct trusty_ipc_cmd_hdr *cmd;
+
+    trusty_assert(dev);
+
+    trusty_debug("%s: chan %d: closing\n", __func__, handle);
+
+    /* prepare command */
+    cmd = dev->buf_vaddr;
+    trusty_memset((void *)cmd, 0, sizeof(*cmd));
+    cmd->opcode = QL_TIPC_DEV_DISCONNECT;
+    cmd->handle = handle;
+    /* no payload */
+
+    /* call into secure os */
+    rc = trusty_dev_exec_ipc(dev->tdev,
+                             &dev->buf_ns, sizeof(*cmd) + cmd->payload_len);
+    if (rc) {
+        trusty_error("%s: secure OS returned (%d)\n", __func__, rc);
+        return TRUSTY_ERR_SECOS_ERR;
+    }
+
+    rc = check_response(dev, cmd, QL_TIPC_DEV_DISCONNECT);
+    if (rc) {
+        trusty_error("%s: disconnect cmd failed (%d)\n", __func__, rc);
+        return rc;
+    }
+
+    trusty_debug("%s: chan %d: closed\n", __func__, handle);
+
+    return TRUSTY_ERR_NONE;
+}
+
+int trusty_ipc_dev_get_event(struct trusty_ipc_dev *dev, handle_t chan,
+                             struct trusty_ipc_event *event)
+{
+    int rc;
+    volatile struct trusty_ipc_cmd_hdr *cmd;
+
+    trusty_assert(dev);
+    trusty_assert(event);
+
+    /* prepare command */
+    cmd = dev->buf_vaddr;
+    trusty_memset((void *)cmd, 0, sizeof(*cmd));
+    cmd->opcode = QL_TIPC_DEV_GET_EVENT;
+    cmd->handle = chan;
+
+    /* prepare payload  */
+    trusty_memset((void *)cmd->payload, 0, sizeof(struct trusty_ipc_wait_req));
+    cmd->payload_len = sizeof(struct trusty_ipc_wait_req);
+
+    /* call into secure os */
+    rc = trusty_dev_exec_ipc(dev->tdev,
+                             &dev->buf_ns, sizeof(*cmd) + cmd->payload_len);
+    if (rc) {
+        trusty_error("%s: secure OS returned (%d)\n", __func__, rc);
+        return TRUSTY_ERR_SECOS_ERR;
+    }
+
+    rc = check_response(dev, cmd, QL_TIPC_DEV_GET_EVENT);
+    if (rc) {
+        trusty_error("%s: get event cmd failed (%d)\n", __func__, rc);
+        return rc;
+    }
+
+    if ((size_t)cmd->payload_len < sizeof(*event)) {
+        trusty_error("%s: invalid response length (%zd)\n",
+                     __func__, (size_t)cmd->payload_len);
+        return TRUSTY_ERR_SECOS_ERR;
+    }
+
+    /* copy out event */
+    trusty_memcpy(event, (const void *)cmd->payload, sizeof(*event));
+    return TRUSTY_ERR_NONE;
+}
+
+int trusty_ipc_dev_send(struct trusty_ipc_dev *dev, handle_t chan,
+                        const struct trusty_ipc_iovec *iovs, size_t iovs_cnt)
+{
+    int rc;
+    size_t msg_size;
+    volatile struct trusty_ipc_cmd_hdr *cmd;
+
+    trusty_assert(dev);
+    /* calc message length */
+    msg_size = iovec_size(iovs, iovs_cnt);
+    if (msg_size > dev->buf_size - sizeof(*cmd)) {
+        /* msg is too big to fit provided buffer */
+        trusty_error("%s: chan %d: msg is too long (%zu)\n", __func__,
+                     chan, msg_size);
+        return TRUSTY_ERR_MSG_TOO_BIG;
+    }
+
+    /* prepare command */
+    cmd = dev->buf_vaddr;
+    trusty_memset((void *)cmd, 0, sizeof(*cmd));
+    cmd->opcode = QL_TIPC_DEV_SEND;
+    cmd->handle = chan;
+
+    /* copy in message data */
+    cmd->payload_len = (uint32_t)msg_size;
+    msg_size = iovec_to_buf(dev->buf_vaddr + sizeof(*cmd), dev->buf_size - sizeof(*cmd),
+                          iovs,  iovs_cnt);
+    trusty_assert(msg_size == (size_t)cmd->payload_len);
+
+    /* call into secure os */
+    rc = trusty_dev_exec_ipc(dev->tdev,
+                             &dev->buf_ns, sizeof(*cmd) + cmd->payload_len);
+    if (rc < 0) {
+        trusty_error("%s: secure OS returned (%d)\n", __func__, rc);
+        return TRUSTY_ERR_SECOS_ERR;
+    }
+
+    rc = check_response(dev, cmd, QL_TIPC_DEV_SEND);
+    if (rc) {
+        trusty_error("%s: send msg failed (%d)\n", __func__, rc);
+    }
+
+    return rc;
+}
+
+
+int trusty_ipc_dev_recv(struct trusty_ipc_dev *dev, handle_t chan,
+                        const struct trusty_ipc_iovec *iovs, size_t iovs_cnt)
+{
+    int rc;
+    size_t copied;
+    volatile struct trusty_ipc_cmd_hdr *cmd;
+
+    trusty_assert(dev);
+
+    /* prepare command */
+    cmd = dev->buf_vaddr;
+    trusty_memset((void *)cmd, 0, sizeof(*cmd));
+    cmd->opcode = QL_TIPC_DEV_RECV;
+    cmd->handle = chan;
+    /* no payload */
+
+    /* call into secure os */
+    rc = trusty_dev_exec_ipc(dev->tdev,
+                             &dev->buf_ns, sizeof(*cmd) + cmd->payload_len);
+    if (rc < 0) {
+        trusty_error("%s: secure OS returned (%d)\n", __func__, rc);
+        return TRUSTY_ERR_SECOS_ERR;
+    }
+
+    rc = check_response(dev, cmd, QL_TIPC_DEV_RECV);
+    if (rc) {
+        trusty_error("%s: recv cmd failed (%d)\n", __func__, rc);
+        return rc;
+    }
+
+    /* copy data out to proper destination */
+    copied = buf_to_iovec(iovs, iovs_cnt,
+                          (const void *)cmd->payload, cmd->payload_len);
+    if (copied != (size_t)cmd->payload_len) {
+        /* msg is too big to fit provided buffer */
+        trusty_error("%s: chan %d: buffer too small (%zu vs. %zu)\n",
+                     __func__, chan, copied, (size_t)cmd->payload_len);
+        return TRUSTY_ERR_MSG_TOO_BIG;
+    }
+
+    return (int)copied;
+}
+
+void trusty_ipc_dev_idle(struct trusty_ipc_dev *dev)
+{
+    trusty_idle(dev->tdev);
+}
+
diff --git a/lib/trusty/ql-tipc/keymaster.c b/lib/trusty/ql-tipc/keymaster.c
new file mode 100644
index 00000000000..d3957b853b1
--- /dev/null
+++ b/lib/trusty/ql-tipc/keymaster.c
@@ -0,0 +1,697 @@
+/*
+ * Copyright (C) 2017 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <trusty/keymaster.h>
+#include <trusty/keymaster_serializable.h>
+#include <trusty/rpmb.h>
+#include <trusty/trusty_ipc.h>
+#include <trusty/util.h>
+
+#define LOCAL_LOG 0
+
+static struct trusty_ipc_chan km_chan;
+static bool initialized = false;
+static int trusty_km_version = 2;
+static const size_t kMaxCaRequestSize = 10000;
+static const size_t kMaxSendSize = 4000;
+static const size_t kUuidSize = 32;
+
+#ifndef MIN
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#endif
+
+#ifndef NELEMS
+#define NELEMS(x) (sizeof(x) / sizeof((x)[0]))
+#endif
+
+static int km_send_request(uint32_t cmd, const void *req, size_t req_len)
+{
+    struct keymaster_message header = { .cmd = cmd };
+    int num_iovecs = req ? 2 : 1;
+
+    struct trusty_ipc_iovec req_iovs[2] = {
+        { .base = &header, .len = sizeof(header) },
+        { .base = (void*)req, .len = req_len },
+    };
+
+    return trusty_ipc_send(&km_chan, req_iovs, num_iovecs, true);
+}
+
+/* Checks that the command opcode in |header| matches |ex-ected_cmd|. Checks
+ * that |tipc_result| is a valid response size. Returns negative on error.
+ */
+static int check_response_error(uint32_t expected_cmd,
+                                struct keymaster_message header,
+                                int32_t tipc_result)
+{
+    if (tipc_result < 0) {
+        trusty_error("failed (%d) to recv response\n", tipc_result);
+        return tipc_result;
+    }
+    if ((size_t) tipc_result < sizeof(struct keymaster_message)) {
+        trusty_error("invalid response size (%d)\n", tipc_result);
+        return TRUSTY_ERR_GENERIC;
+    }
+    if ((header.cmd & ~(KEYMASTER_STOP_BIT)) !=
+        (expected_cmd | KEYMASTER_RESP_BIT)) {
+        trusty_error("malformed response\n");
+        return TRUSTY_ERR_GENERIC;
+    }
+    return tipc_result;
+}
+
+/* Reads the raw response to |resp| up to a maximum size of |resp_len|. Format
+ * of each message frame read from the secure side:
+ *
+ * command header : 4 bytes
+ * opaque bytes   : MAX(KEYMASTER_MAX_BUFFER_LENGTH, x) bytes
+ *
+ * The individual message frames from the secure side are reassembled
+ * into |resp|, stripping each frame's command header. Returns the number
+ * of bytes written to |resp| on success, negative on error.
+ */
+static int km_read_raw_response(uint32_t cmd, void *resp, size_t resp_len)
+{
+    struct keymaster_message header = { .cmd = cmd };
+    int rc = TRUSTY_ERR_GENERIC;
+    size_t max_resp_len = resp_len;
+    struct trusty_ipc_iovec resp_iovs[2] = {
+        { .base = &header, .len = sizeof(header) },
+        { .base = resp, .len = MIN(KEYMASTER_MAX_BUFFER_LENGTH, max_resp_len) }
+    };
+
+    if (!resp) {
+        return TRUSTY_ERR_GENERIC;
+    }
+    resp_len = 0;
+    while (true) {
+        resp_iovs[1].base = (uint8_t*)resp + resp_len;
+        resp_iovs[1].len = MIN(KEYMASTER_MAX_BUFFER_LENGTH,
+                               (int)max_resp_len - (int)resp_len);
+
+        rc = trusty_ipc_recv(&km_chan, resp_iovs, NELEMS(resp_iovs), true);
+        rc = check_response_error(cmd, header, rc);
+        if (rc < 0) {
+            return rc;
+        }
+        resp_len += ((size_t)rc - sizeof(struct keymaster_message));
+        if (header.cmd & KEYMASTER_STOP_BIT || resp_len >= max_resp_len) {
+            break;
+        }
+    }
+
+    return resp_len;
+}
+
+/* Reads a Keymaster Response message with a sized buffer. The format
+ * of the response is as follows:
+ *
+ * command header : 4 bytes
+ * error          : 4 bytes
+ * data length    : 4 bytes
+ * data           : |data length| bytes
+ *
+ * On success, |error|, |resp_data|, and |resp_data_len| are filled
+ * successfully. Returns a trusty_err.
+ */
+static int km_read_data_response(uint32_t cmd, int32_t *error,
+                                 uint8_t* resp_data, uint32_t* resp_data_len)
+{
+    struct keymaster_message header = { .cmd = cmd };
+    int rc = TRUSTY_ERR_GENERIC;
+    size_t max_resp_len = *resp_data_len;
+    uint32_t resp_data_bytes = 0;
+    /* On the first read, recv the keymaster_message header, error code,
+     * response data length, and response data. On subsequent iterations,
+     * only recv the keymaster_message header and response data.
+     */
+    struct trusty_ipc_iovec resp_iovs[4] = {
+        { .base = &header, .len = sizeof(header) },
+        { .base = error, .len = sizeof(int32_t) },
+        { .base = resp_data_len, .len = sizeof(uint32_t) },
+        { .base = resp_data, .len = MIN(KEYMASTER_MAX_BUFFER_LENGTH, max_resp_len) }
+    };
+
+    rc = trusty_ipc_recv(&km_chan, resp_iovs, NELEMS(resp_iovs), true);
+    rc = check_response_error(cmd, header, rc);
+    if (rc < 0) {
+        return rc;
+    }
+    /* resp_data_bytes does not include the error or response data length */
+    resp_data_bytes += ((size_t)rc - sizeof(struct keymaster_message) -
+                        2 * sizeof(uint32_t));
+    if (header.cmd & KEYMASTER_STOP_BIT) {
+        return TRUSTY_ERR_NONE;
+    }
+
+    /* Read the remaining response data */
+    uint8_t* resp_data_start = resp_data + resp_data_bytes;
+    size_t resp_data_remaining = *resp_data_len - resp_data_bytes;
+    rc = km_read_raw_response(cmd, resp_data_start, resp_data_remaining);
+    if (rc < 0) {
+        return rc;
+    }
+    resp_data_bytes += rc;
+    if (*resp_data_len != resp_data_bytes) {
+        return TRUSTY_ERR_GENERIC;
+    }
+    return TRUSTY_ERR_NONE;
+}
+
+/**
+ * Convenience method to send a request to the secure side, handle rpmb
+ * operations, and receive the response. If |resp_data| is not NULL, the
+ * caller expects an additional data buffer to be returned from the secure
+ * side.
+ */
+static int km_do_tipc(uint32_t cmd, void* req, uint32_t req_len,
+                      void* resp_data, uint32_t* resp_data_len)
+{
+    int rc = TRUSTY_ERR_GENERIC;
+    struct km_no_response resp_header;
+
+    rc = km_send_request(cmd, req, req_len);
+    if (rc < 0) {
+        trusty_error("%s: failed (%d) to send km request\n", __func__, rc);
+        return rc;
+    }
+
+    if (!resp_data) {
+        rc = km_read_raw_response(cmd, &resp_header, sizeof(resp_header));
+    } else {
+        rc = km_read_data_response(cmd, &resp_header.error, resp_data,
+                                   resp_data_len);
+    }
+
+    if (rc < 0) {
+        trusty_error("%s: failed (%d) to read km response\n", __func__, rc);
+        return rc;
+    }
+    if (resp_header.error != KM_ERROR_OK) {
+        trusty_error("%s: keymaster returned error (%d)\n", __func__,
+                     resp_header.error);
+        return TRUSTY_ERR_GENERIC;
+    }
+    return TRUSTY_ERR_NONE;
+}
+
+static int32_t MessageVersion(uint8_t major_ver, uint8_t minor_ver,
+                              uint8_t subminor_ver) {
+    int32_t message_version = -1;
+    switch (major_ver) {
+    case 0:
+        message_version = 0;
+        break;
+    case 1:
+        switch (minor_ver) {
+        case 0:
+            message_version = 1;
+            break;
+        case 1:
+            message_version = 2;
+            break;
+        }
+        break;
+    case 2:
+        message_version = 3;
+        break;
+    }
+    return message_version;
+}
+
+static int km_get_version(int32_t *version)
+{
+    int rc = TRUSTY_ERR_GENERIC;
+    struct km_get_version_resp resp;
+
+    rc = km_send_request(KM_GET_VERSION, NULL, 0);
+    if (rc < 0) {
+        trusty_error("failed to send km version request", rc);
+        return rc;
+    }
+
+    rc = km_read_raw_response(KM_GET_VERSION, &resp, sizeof(resp));
+    if (rc < 0) {
+        trusty_error("%s: failed (%d) to read km response\n", __func__, rc);
+        return rc;
+    }
+
+    *version = MessageVersion(resp.major_ver, resp.minor_ver,
+                              resp.subminor_ver);
+    return TRUSTY_ERR_NONE;
+}
+
+int km_tipc_init(struct trusty_ipc_dev *dev)
+{
+    int rc = TRUSTY_ERR_GENERIC;
+
+    trusty_assert(dev);
+
+    trusty_ipc_chan_init(&km_chan, dev);
+    trusty_debug("Connecting to Keymaster service\n");
+
+    /* connect to km service and wait for connect to complete */
+    rc = trusty_ipc_connect(&km_chan, KEYMASTER_PORT, true);
+    if (rc < 0) {
+        trusty_error("failed (%d) to connect to '%s'\n", rc, KEYMASTER_PORT);
+        return rc;
+    }
+
+    int32_t version = -1;
+    rc = km_get_version(&version);
+    if (rc < 0) {
+        trusty_error("failed (%d) to get keymaster version\n", rc);
+        return rc;
+    }
+    if (version < trusty_km_version) {
+        trusty_error("keymaster version mismatch. Expected %d, received %d\n",
+                     trusty_km_version, version);
+        return TRUSTY_ERR_GENERIC;
+    }
+
+    /* mark as initialized */
+    initialized = true;
+
+    return TRUSTY_ERR_NONE;
+}
+
+void km_tipc_shutdown(struct trusty_ipc_dev *dev)
+{
+    if (!initialized)
+        return;
+    /* close channel */
+    trusty_ipc_close(&km_chan);
+
+    initialized = false;
+}
+
+int trusty_set_boot_params(uint32_t os_version, uint32_t os_patchlevel,
+                           keymaster_verified_boot_t verified_boot_state,
+                           bool device_locked,
+                           const uint8_t *verified_boot_key_hash,
+                           uint32_t verified_boot_key_hash_size,
+                           const uint8_t *verified_boot_hash,
+                           uint32_t verified_boot_hash_size)
+{
+    if (!initialized) {
+	trusty_error("Keymaster TIPC client not initialized!\n");
+	return -1;
+    }
+    struct km_boot_params params = {
+        .os_version = os_version,
+        .os_patchlevel = os_patchlevel,
+        .device_locked = (uint32_t)device_locked,
+        .verified_boot_state = (uint32_t)verified_boot_state,
+        .verified_boot_key_hash_size = verified_boot_key_hash_size,
+        .verified_boot_key_hash = verified_boot_key_hash,
+        .verified_boot_hash_size = verified_boot_hash_size,
+        .verified_boot_hash = verified_boot_hash
+    };
+    uint8_t *req = NULL;
+    uint32_t req_size = 0;
+    int rc = km_boot_params_serialize(&params, &req, &req_size);
+
+    if (rc < 0) {
+        trusty_error("failed (%d) to serialize request\n", rc);
+        goto end;
+    }
+    rc = km_do_tipc(KM_SET_BOOT_PARAMS, req, req_size, NULL, NULL);
+
+end:
+    if (req) {
+        trusty_free(req);
+    }
+    return rc;
+}
+
+static int trusty_send_attestation_data(uint32_t cmd, const uint8_t *data,
+                                        uint32_t data_size,
+                                        keymaster_algorithm_t algorithm)
+{
+    struct km_attestation_data attestation_data = {
+        .algorithm = (uint32_t)algorithm,
+        .data_size = data_size,
+        .data = data,
+    };
+    uint8_t *req = NULL;
+    uint32_t req_size = 0;
+    int rc = km_attestation_data_serialize(&attestation_data, &req, &req_size);
+
+    if (rc < 0) {
+        trusty_error("failed (%d) to serialize request\n", rc);
+        goto end;
+    }
+    rc = km_do_tipc(cmd, req, req_size, NULL, NULL);
+
+end:
+    if (req) {
+        trusty_free(req);
+    }
+    return rc;
+}
+
+static int trusty_send_raw_buffer(uint32_t cmd, const uint8_t *req_data,
+                                  uint32_t req_data_size, uint8_t *resp_data,
+                                  uint32_t *resp_data_size)
+{
+    struct km_raw_buffer buf = {
+        .data_size = req_data_size,
+        .data = req_data,
+    };
+    uint8_t *req = NULL;
+    uint32_t req_size = 0;
+    int rc = km_raw_buffer_serialize(&buf, &req, &req_size);
+    if (rc < 0) {
+        trusty_error("failed (%d) to serialize request\n", rc);
+        goto end;
+    }
+    rc = km_do_tipc(cmd, req, req_size, resp_data, resp_data_size);
+
+end:
+    if (req) {
+        trusty_free(req);
+    }
+    return rc;
+}
+
+int trusty_set_attestation_key(const uint8_t *key, uint32_t key_size,
+                               keymaster_algorithm_t algorithm)
+{
+    if (!initialized) {
+        trusty_error("Keymaster TIPC client not initialized!\n");
+        return -1;
+    }
+    return trusty_send_attestation_data(KM_SET_ATTESTATION_KEY, key, key_size,
+                                        algorithm);
+}
+
+int trusty_append_attestation_cert_chain(const uint8_t *cert,
+                                         uint32_t cert_size,
+                                         keymaster_algorithm_t algorithm)
+{
+    if (!initialized) {
+        trusty_error("Keymaster TIPC client not initialized!\n");
+        return -1;
+    }
+    return trusty_send_attestation_data(KM_APPEND_ATTESTATION_CERT_CHAIN,
+                                        cert, cert_size, algorithm);
+}
+
+int trusty_set_attestation_key_enc(const uint8_t *key, uint32_t key_size,
+                               keymaster_algorithm_t algorithm)
+{
+    if (!initialized) {
+        trusty_error("Keymaster TIPC client not initialized!\n");
+        return -1;
+    }
+    return trusty_send_attestation_data(KM_SET_ATTESTATION_KEY_ENC, key, key_size,
+                                        algorithm);
+}
+
+int trusty_append_attestation_cert_chain_enc(const uint8_t *cert,
+                                         uint32_t cert_size,
+                                         keymaster_algorithm_t algorithm)
+{
+    if (!initialized) {
+        trusty_error("Keymaster TIPC client not initialized!\n");
+        return -1;
+    }
+    return trusty_send_attestation_data(KM_APPEND_ATTESTATION_CERT_CHAIN_ENC,
+                                        cert, cert_size, algorithm);
+}
+
+int trusty_atap_get_ca_request(const uint8_t *operation_start,
+                               uint32_t operation_start_size,
+                               uint8_t **ca_request_p,
+                               uint32_t *ca_request_size_p)
+{
+    *ca_request_p = trusty_calloc(1, kMaxCaRequestSize);
+    if (!*ca_request_p) {
+        return TRUSTY_ERR_NO_MEMORY;
+    }
+    *ca_request_size_p = kMaxCaRequestSize;
+    int rc = trusty_send_raw_buffer(KM_ATAP_GET_CA_REQUEST, operation_start,
+                                    operation_start_size, *ca_request_p,
+                                    ca_request_size_p);
+    if (rc != TRUSTY_ERR_NONE) {
+        trusty_free(*ca_request_p);
+    }
+    return rc;
+}
+
+int trusty_atap_set_ca_response(const uint8_t *ca_response,
+                                uint32_t ca_response_size)
+{
+    struct km_set_ca_response_begin_req begin_req;
+    int rc = TRUSTY_ERR_GENERIC;
+    uint32_t bytes_sent = 0, send_size = 0;
+
+    /* Tell the Trusty Keymaster TA the size of CA Response message */
+    begin_req.ca_response_size = ca_response_size;
+    rc = km_do_tipc(KM_ATAP_SET_CA_RESPONSE_BEGIN, &begin_req,
+                    sizeof(begin_req), NULL, NULL);
+    if (rc != TRUSTY_ERR_NONE) {
+        return rc;
+    }
+
+    /* Send the CA Response message in chunks */
+    while (bytes_sent < ca_response_size) {
+        send_size = MIN(kMaxSendSize, ca_response_size - bytes_sent);
+        rc = trusty_send_raw_buffer(KM_ATAP_SET_CA_RESPONSE_UPDATE,
+                                    ca_response + bytes_sent, send_size,
+                                    NULL, NULL);
+        if (rc != TRUSTY_ERR_NONE) {
+            return rc;
+        }
+        bytes_sent += send_size;
+    }
+
+    /* Tell Trusty Keymaster to parse the CA Response message */
+    return km_do_tipc(KM_ATAP_SET_CA_RESPONSE_FINISH, NULL, 0, NULL, NULL);
+}
+
+
+int trusty_atap_read_uuid_str(char **uuid_p)
+{
+    *uuid_p = (char*) trusty_calloc(1, kUuidSize);
+
+    uint32_t response_size = kUuidSize;
+    int rc = km_do_tipc(KM_ATAP_READ_UUID, NULL, 0, *uuid_p,
+                        &response_size);
+    if (rc < 0) {
+        trusty_error("failed to read uuid: %d\n", rc);
+        trusty_free(*uuid_p);
+        return rc;
+    }
+    if (response_size != kUuidSize) {
+        trusty_error("keymaster returned wrong uuid size: %d\n", response_size);
+        trusty_free(*uuid_p);
+        rc = TRUSTY_ERR_GENERIC;
+    }
+    return rc;
+}
+
+int trusty_get_mppubk(uint8_t *mppubk, uint32_t *size)
+{
+    int rc = TRUSTY_ERR_GENERIC;
+    struct km_get_mppubk_resp resp;
+
+    if (!initialized) {
+        trusty_error("Keymaster TIPC client not initialized!\n");
+        return -1;
+    }
+
+    rc = km_send_request(KM_GET_MPPUBK, NULL, 0);
+    if (rc < 0) {
+        trusty_error("failed to send km mppubk request\n", rc);
+        return rc;
+    }
+
+    rc = km_read_raw_response(KM_GET_MPPUBK, &resp, sizeof(resp));
+    if (rc < 0) {
+        trusty_error("%s: failed (%d) to read km mppubk response\n", __func__, rc);
+        return rc;
+    }
+
+    if (resp.data_size != 64) {
+        trusty_error("%s: Wrong mppubk size!\n", __func__);
+        return TRUSTY_ERR_GENERIC;
+    } else {
+        *size = resp.data_size;
+    }
+
+    memcpy(mppubk, resp.data, resp.data_size);
+    return TRUSTY_ERR_NONE;
+}
+
+int trusty_verify_secure_unlock(uint8_t *unlock_credential,
+                                uint32_t credential_size,
+                                uint8_t *serial, uint32_t serial_size)
+{
+    int rc = TRUSTY_ERR_GENERIC;
+    uint8_t *req = NULL;
+    uint32_t req_size = 0;
+
+    if (!initialized) {
+        trusty_error("Keymaster TIPC client not initialized!\n");
+        return -1;
+    }
+
+    struct km_secure_unlock_data secure_unlock_data = {
+        .serial_size = serial_size,
+        .serial_data = serial,
+        .credential_size = credential_size,
+        .credential_data = unlock_credential,
+    };
+
+    rc = km_secure_unlock_data_serialize(&secure_unlock_data,
+                                             &req, &req_size);
+
+    if (rc < 0) {
+        trusty_error("failed (%d) to serialize request\n", rc);
+        goto end;
+    }
+    rc = km_do_tipc(KM_VERIFY_SECURE_UNLOCK, req, req_size, NULL, NULL);
+
+end:
+    if (req) {
+        trusty_free(req);
+    }
+    return rc;
+}
+
+char *get_serial(void);
+int trusty_set_attestation_id(void)
+{
+    uint8_t *req = NULL, *tmp = NULL;
+    uint32_t req_size = 0;
+    int rc;
+
+    req = trusty_calloc(1024, 1); // 1024 bytes buffer should be enough.
+    tmp = req;
+
+    /* fill in the device ids */
+    /* brand */
+    rc = km_attestation_id_data_serialize((uint8_t *)CONFIG_ATTESTATION_ID_BRAND,
+                                          strlen(CONFIG_ATTESTATION_ID_BRAND),
+                                          &tmp, &req_size);
+    if (rc < 0) {
+	trusty_error("%s: failed (%d) to set id brand.\n", __func__, rc);
+        goto end;
+    }
+
+    /* device */
+    rc = km_attestation_id_data_serialize((uint8_t *)CONFIG_ATTESTATION_ID_DEVICE,
+                                          strlen(CONFIG_ATTESTATION_ID_DEVICE),
+                                          &tmp, &req_size);
+    if (rc < 0) {
+	trusty_error("%s: failed (%d) to set id device.\n", __func__, rc);
+        goto end;
+    }
+
+    /* product */
+    rc = km_attestation_id_data_serialize((uint8_t *)CONFIG_ATTESTATION_ID_PRODUCT,
+                                          strlen(CONFIG_ATTESTATION_ID_PRODUCT),
+                                          &tmp, &req_size);
+    if (rc < 0) {
+	trusty_error("%s: failed (%d) to set id product.\n", __func__, rc);
+        goto end;
+    }
+
+    /* serial number, bail out when fail because it's a MUST. */
+    char *serial = get_serial();
+    if (serial)
+        km_attestation_id_data_serialize((uint8_t *)serial, 16, &tmp, &req_size);
+    else {
+        trusty_error("%s: failed to get serial number.\n", __func__);
+        goto end;
+    }
+
+    /* IMEI */
+    rc = km_attestation_id_data_serialize((uint8_t *)CONFIG_ATTESTATION_ID_IMEI,
+                                          strlen(CONFIG_ATTESTATION_ID_IMEI),
+                                          &tmp, &req_size);
+    if (rc < 0) {
+	trusty_error("%s: failed (%d) to set id IMEI.\n", __func__, rc);
+        goto end;
+    }
+
+    /* MEID */
+    rc = km_attestation_id_data_serialize((uint8_t *)CONFIG_ATTESTATION_ID_MEID,
+                                          strlen(CONFIG_ATTESTATION_ID_MEID),
+                                          &tmp, &req_size);
+    if (rc < 0) {
+	trusty_error("%s: failed (%d) to set id MEID.\n", __func__, rc);
+        goto end;
+    }
+
+    /* manufacturer */
+    rc = km_attestation_id_data_serialize((uint8_t *)CONFIG_ATTESTATION_ID_MANUFACTURER,
+                                          strlen(CONFIG_ATTESTATION_ID_MANUFACTURER),
+                                          &tmp, &req_size);
+    if (rc < 0) {
+	trusty_error("%s: failed (%d) to set id manufacturer.\n", __func__, rc);
+        goto end;
+    }
+
+    /* model */
+    rc = km_attestation_id_data_serialize((uint8_t *)CONFIG_ATTESTATION_ID_MODEL,
+                                          strlen(CONFIG_ATTESTATION_ID_MODEL),
+                                          &tmp, &req_size);
+    if (rc < 0) {
+	trusty_error("%s: failed (%d) to set id model.\n", __func__, rc);
+        goto end;
+    }
+
+    rc = km_do_tipc(KM_SET_ATTESTATION_IDS, req, req_size, NULL, NULL);
+
+end:
+    if (req) {
+        trusty_free(req);
+    }
+    return rc;
+}
+
+int trusty_set_boot_patch_level(uint32_t boot_patch_level)
+{
+    if (!initialized) {
+        trusty_error("Keymaster TIPC client not initialized!\n");
+        return -1;
+    }
+
+    uint8_t *req = NULL;
+    uint32_t req_size = 0;
+    int rc;
+
+    req = trusty_calloc(4, 1); // 4 bytes should be enough.
+    memcpy(req, &boot_patch_level, sizeof(uint32_t));
+    req_size = sizeof(uint32_t);
+
+    rc = km_do_tipc(KM_CONFIGURE_BOOT_PATCHLEVEL, req, req_size, NULL, NULL);
+
+    if (req) {
+        trusty_free(req);
+    }
+    return rc;
+}
diff --git a/lib/trusty/ql-tipc/keymaster_serializable.c b/lib/trusty/ql-tipc/keymaster_serializable.c
new file mode 100644
index 00000000000..eda9efe7bd5
--- /dev/null
+++ b/lib/trusty/ql-tipc/keymaster_serializable.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2017 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <trusty/keymaster_serializable.h>
+
+uint8_t *append_to_buf(uint8_t *buf, const void *data, size_t data_len)
+{
+    if (data && data_len) {
+        trusty_memcpy(buf, data, data_len);
+    }
+    return buf + data_len;
+}
+
+uint8_t *append_uint32_to_buf(uint8_t *buf, uint32_t val)
+{
+    return append_to_buf(buf, &val, sizeof(val));
+}
+
+uint8_t *append_sized_buf_to_buf(uint8_t *buf, const uint8_t *data,
+                                 uint32_t data_len)
+{
+    buf = append_uint32_to_buf(buf, data_len);
+    return append_to_buf(buf, data, data_len);
+}
+
+int km_boot_params_serialize(const struct km_boot_params *params, uint8_t** out,
+                             uint32_t *out_size)
+{
+    uint8_t *tmp;
+
+    if (!out || !params || !out_size) {
+        return TRUSTY_ERR_INVALID_ARGS;
+    }
+    *out_size = (sizeof(params->os_version) + sizeof(params->os_patchlevel) +
+                 sizeof(params->device_locked) +
+                 sizeof(params->verified_boot_state) +
+                 sizeof(params->verified_boot_key_hash_size) +
+                 sizeof(params->verified_boot_hash_size) +
+                 params->verified_boot_key_hash_size +
+                 params->verified_boot_hash_size);
+    *out = trusty_calloc(*out_size, 1);
+    if (!*out) {
+        return TRUSTY_ERR_NO_MEMORY;
+    }
+
+    tmp = append_uint32_to_buf(*out, params->os_version);
+    tmp = append_uint32_to_buf(tmp, params->os_patchlevel);
+    tmp = append_uint32_to_buf(tmp, params->device_locked);
+    tmp = append_uint32_to_buf(tmp, params->verified_boot_state);
+    tmp = append_sized_buf_to_buf(tmp, params->verified_boot_key_hash,
+                                  params->verified_boot_key_hash_size);
+    tmp = append_sized_buf_to_buf(tmp, params->verified_boot_hash,
+                                  params->verified_boot_hash_size);
+
+    return TRUSTY_ERR_NONE;
+}
+
+int km_attestation_data_serialize(const struct km_attestation_data *data,
+                                 uint8_t** out, uint32_t *out_size)
+{
+    uint8_t *tmp;
+
+    if (!out || !data || !out_size) {
+        return TRUSTY_ERR_INVALID_ARGS;
+    }
+    *out_size = (sizeof(data->algorithm) + sizeof(data->data_size) +
+                 data->data_size);
+    *out = trusty_calloc(*out_size, 1);
+    if (!*out) {
+        return TRUSTY_ERR_NO_MEMORY;
+    }
+
+    tmp = append_uint32_to_buf(*out, data->algorithm);
+    tmp = append_sized_buf_to_buf(tmp, data->data, data->data_size);
+
+    return TRUSTY_ERR_NONE;
+}
+
+int km_attestation_id_data_serialize(const uint8_t *data, uint32_t data_size,
+                                     uint8_t** out, uint32_t *out_size)
+{
+    if (!out || !out_size) {
+        return TRUSTY_ERR_INVALID_ARGS;
+    }
+
+    if (data_size)
+        *out = append_sized_buf_to_buf(*out, data, data_size);
+    else
+        *out = append_uint32_to_buf(*out, data_size);
+    *out_size += (sizeof(data_size) + data_size);
+
+    return TRUSTY_ERR_NONE;
+}
+
+int km_secure_unlock_data_serialize(const struct km_secure_unlock_data *data,
+                                 uint8_t** out, uint32_t *out_size)
+{
+    uint8_t *tmp;
+
+    if (!out || !data || !out_size) {
+        return TRUSTY_ERR_INVALID_ARGS;
+    }
+    *out_size = (sizeof(data->serial_size) + sizeof(data->credential_size) +
+                 data->serial_size + data->credential_size);
+    *out = trusty_calloc(*out_size, 1);
+    if (!*out) {
+        return TRUSTY_ERR_NO_MEMORY;
+    }
+
+    tmp = append_sized_buf_to_buf(*out, data->serial_data, data->serial_size);
+    tmp = append_sized_buf_to_buf(tmp, data->credential_data, data->credential_size);
+
+    return TRUSTY_ERR_NONE;
+}
+
+int km_raw_buffer_serialize(const struct km_raw_buffer *buf, uint8_t** out,
+                            uint32_t *out_size)
+{
+    if (!out || !buf || !out_size) {
+        return TRUSTY_ERR_INVALID_ARGS;
+    }
+    *out_size = sizeof(buf->data_size) + buf->data_size;
+    *out = trusty_calloc(*out_size, 1);
+    if (!*out) {
+        return TRUSTY_ERR_NO_MEMORY;
+    }
+    append_sized_buf_to_buf(*out, buf->data, buf->data_size);
+
+    return TRUSTY_ERR_NONE;
+}
diff --git a/lib/trusty/ql-tipc/libtipc.c b/lib/trusty/ql-tipc/libtipc.c
new file mode 100644
index 00000000000..d21b364c73a
--- /dev/null
+++ b/lib/trusty/ql-tipc/libtipc.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ * Copyright NXP 2018
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <common.h>
+#include <trusty/avb.h>
+#include <trusty/hwcrypto.h>
+#include <trusty/keymaster.h>
+#include <trusty/rpmb.h>
+#include <trusty/trusty_dev.h>
+#include <trusty/trusty_ipc.h>
+#include <trusty/util.h>
+#include <hang.h>
+#include <env.h>
+#include <trusty/imx_snvs.h>
+
+#define LOCAL_LOG 0
+
+typedef uintptr_t vaddr_t;
+
+static struct trusty_ipc_dev *_ipc_dev;
+static struct trusty_dev _tdev; /* There should only be one trusty device */
+static void *rpmb_ctx;
+#ifndef CONFIG_AVB_ATX
+bool rpmbkey_is_set(void);
+#endif
+
+void rpmb_storage_put_ctx(void *dev);
+void trusty_ipc_shutdown(void)
+{
+    /**
+     * Trusty OS is not well initialized when the rpmb
+     * key is not set, skip ipc shut down to avoid panic.
+     */
+    if (!rpmbkey_is_set()) {
+        return;
+    }
+
+    (void)rpmb_storage_proxy_shutdown(_ipc_dev);
+    (void)rpmb_storage_put_ctx(rpmb_ctx);
+
+    (void)avb_tipc_shutdown(_ipc_dev);
+    (void)km_tipc_shutdown(_ipc_dev);
+
+#ifndef CONFIG_AVB_ATX
+    (void)hwcrypto_tipc_shutdown(_ipc_dev);
+#endif
+
+    /* shutdown Trusty IPC device */
+    (void)trusty_ipc_dev_shutdown(_ipc_dev);
+
+    /* shutdown Trusty device */
+    (void)trusty_dev_shutdown(&_tdev);
+}
+
+int trusty_ipc_init(void)
+{
+    int rc;
+    bool use_keystore = true;
+    /* init Trusty device */
+    trusty_info("Initializing Trusty device\n");
+    rc = trusty_dev_init(&_tdev, NULL);
+    if (rc != 0) {
+        trusty_error("Initializing Trusty device failed (%d)\n", rc);
+        return rc;
+    }
+
+    /* create Trusty IPC device */
+    trusty_info("Initializing Trusty IPC device\n");
+    rc = trusty_ipc_dev_create(&_ipc_dev, &_tdev, PAGE_SIZE);
+    if (rc != 0) {
+        trusty_error("Initializing Trusty IPC device failed (%d)\n", rc);
+        return rc;
+    }
+
+    /* get storage rpmb */
+    rpmb_ctx = rpmb_storage_get_ctx();
+
+    /* start secure storage proxy service */
+    trusty_info("Initializing RPMB storage proxy service\n");
+    rc = rpmb_storage_proxy_init(_ipc_dev, rpmb_ctx);
+    if (rc != 0) {
+        trusty_error("Initlializing RPMB storage proxy service failed (%d)\n", rc);
+#ifndef CONFIG_AVB_ATX
+        /* check if rpmb key has been fused. */
+        if(rpmbkey_is_set()) {
+            /* Go to hang if the key has been destroyed. */
+            trusty_error("RPMB key was destroyed!\n");
+            hang();
+        }
+#else
+        return rc;
+#endif
+    }
+
+    /**
+     * The proxy service can return success even the storage initialization
+     * failed (when the rpmb key not set). Init the avb and keymaster service
+     * only when the rpmb key has been set.
+     */
+    if (rpmbkey_is_set()) {
+        rc = avb_tipc_init(_ipc_dev);
+        if (rc != 0) {
+            trusty_error("Initlializing Trusty AVB client failed (%d)\n", rc);
+            return rc;
+        }
+
+        trusty_info("Initializing Trusty Keymaster client\n");
+        rc = km_tipc_init(_ipc_dev);
+        if (rc != 0) {
+            trusty_error("Initlializing Trusty Keymaster client failed (%d)\n", rc);
+            return rc;
+        }
+    } else
+        use_keystore = false;
+
+#ifndef CONFIG_AVB_ATX
+    trusty_info("Initializing Trusty Hardware Crypto client\n");
+    rc = hwcrypto_tipc_init(_ipc_dev);
+    if (rc != 0) {
+        trusty_error("Initlializing Trusty hwcrypto client failed (%d)\n", rc);
+        return rc;
+    }
+#endif
+
+#ifdef CONFIG_IMX8M
+    trusty_info("Initializing Trusty SNVS driver\n");
+    rc = imx_snvs_init(_ipc_dev);
+    if (rc != 0) {
+        trusty_error("Initlializing Trusty SNVS driver failed (%d)\n", rc);
+        return rc;
+    }
+#endif
+
+    /* secure storage service init ok, use trusty backed keystore */
+    if (use_keystore)
+        env_set("keystore", "trusty");
+
+    return TRUSTY_ERR_NONE;
+}
diff --git a/lib/trusty/ql-tipc/rpmb_proxy.c b/lib/trusty/ql-tipc/rpmb_proxy.c
new file mode 100644
index 00000000000..3c9d8ee36db
--- /dev/null
+++ b/lib/trusty/ql-tipc/rpmb_proxy.c
@@ -0,0 +1,470 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <trusty/rpmb.h>
+#include <trusty/trusty_ipc.h>
+#include <trusty/util.h>
+#include <interface/storage/storage.h>
+
+#define LOCAL_LOG 0
+
+static bool initialized;
+/* Address of rpmb device */
+static void *proxy_rpmb;
+struct trusty_ipc_chan proxy_chan;
+
+struct storage_msg req_msg;
+static uint8_t req_buf[4096];
+static uint8_t read_buf[4096];
+bool proxy_resp_flag = false;
+static int req_len = 0;
+
+/*
+ * Read RPMB request from storage service. Writes message to @msg
+ * and @req.
+ *
+ * @chan:    proxy ipc channel
+ * @msg:     address of storage message header
+ * @req:     address of storage message request
+ * @req_len: length of req in bytes
+ */
+static int proxy_read_request(struct trusty_ipc_chan *chan,
+                              struct storage_msg *msg, void *req,
+                              size_t req_len)
+{
+    int rc;
+
+    struct trusty_ipc_iovec req_iovs[2] = {
+        { .base = msg, .len = sizeof(*msg) },
+        { .base = req, .len = req_len },
+    };
+    rc = trusty_ipc_recv(chan, req_iovs, 2, false);
+    if (rc < 0) {
+        /* recv message failed */
+        trusty_error("%s: failed (%d) to recv request\n", __func__, rc);
+        return rc;
+    }
+
+    if ((size_t)rc < sizeof(*msg)) {
+        /* malformed message */
+        trusty_error("%s: malformed request (%zu)\n", __func__, (size_t)rc);
+        return TRUSTY_ERR_GENERIC;
+    }
+
+    return rc - sizeof(*msg); /* return payload size */
+}
+
+/*
+ * Read RPMB response from storage service. Writes message to @msg
+ * and @req.
+ *
+ * @chan:     proxy ipc channel
+ * @msg:      address of storage message header
+ * @cmd:      cmd corresponding to the request
+ * @resp:     address of storage message response
+ * @resp_len: length of resp in bytes
+ */
+static int proxy_read_response(struct trusty_ipc_chan *chan, struct storage_msg *msg,
+                               uint32_t cmd, void *resp, size_t resp_len)
+{
+    int rc;
+
+    struct trusty_ipc_iovec resp_iovs[2] = {
+        { .base = msg, .len = sizeof(*msg) },
+        { .base = resp, .len = resp_len },
+    };
+    rc = trusty_ipc_recv(chan, resp_iovs, resp ? 2 : 1, true);
+    if (rc < 0) {
+        /* recv message failed */
+        trusty_error("%s: failed (%d) to recv response\n", __func__, rc);
+        return rc;
+    }
+    if (proxy_resp_flag) {
+        memcpy(msg, &req_msg, sizeof(struct storage_msg));
+        if (resp)
+            memcpy(resp, req_buf, req_len);
+        rc = req_len + sizeof(struct storage_msg);
+        proxy_resp_flag = false;
+    }
+
+    if ((size_t)rc < sizeof(*msg)) {
+        /* malformed message */
+        trusty_error("%s: malformed request (%zu)\n", __func__, (size_t)rc);
+        return TRUSTY_ERR_GENERIC;
+    }
+
+    if (msg->cmd != (cmd | STORAGE_RESP_BIT)) {
+        trusty_error("malformed response, cmd: 0x%x\n", msg->cmd);
+        return TRUSTY_ERR_GENERIC;
+    }
+
+    return rc - sizeof(*msg); /* return payload size */
+}
+
+/*
+ * Send RPMB response to storage service
+ *
+ * @chan:     proxy ipc channel
+ * @msg:      address of storage message header
+ * @resp:     address of storage message response
+ * @resp_len: length of resp in bytes
+ */
+static int proxy_send_response(struct trusty_ipc_chan *chan,
+                               struct storage_msg *msg, void *resp,
+                               size_t resp_len)
+{
+    struct trusty_ipc_iovec resp_iovs[2] = {
+        { .base = msg, .len = sizeof(*msg) },
+        { .base = resp, .len = resp_len }
+    };
+
+    msg->cmd |= STORAGE_RESP_BIT;
+    return trusty_ipc_send(chan, resp_iovs, resp ? 2 : 1, false);
+}
+
+/*
+ * Send RPMB request to storage service
+ *
+ * @chan:     proxy ipc channel
+ * @msg:      address of storage message header
+ * @req:      address of storage message request
+ * @req_len:  length of request in bytes
+ */
+static int proxy_send_request(struct trusty_ipc_chan *chan,
+                              struct storage_msg *msg, void *req,
+                              size_t req_len)
+{
+    struct trusty_ipc_iovec req_iovs[2] = {
+        { .base = msg, .len = sizeof(*msg) },
+        { .base = req, .len = req_len }
+    };
+
+    return trusty_ipc_send(chan, req_iovs, req ? 2 : 1, false);
+}
+
+/*
+ * Convenience function to send a request to the storage service and read the
+ * response.
+ *
+ * @cmd: the command
+ * @req: the request buffer
+ * @req_size: size of the request buffer
+ * @resp: the response buffer
+ * @resp_size_p: pointer to the size of the response buffer. changed to the
+                 actual size of the response read from the secure side
+ */
+static int storage_do_tipc(uint32_t cmd, void *req, uint32_t req_size, void *resp,
+                       uint32_t *resp_size_p)
+{
+    int rc;
+    struct storage_msg msg = { .cmd = cmd };
+
+    if (!initialized) {
+        trusty_error("%s: Secure storage TIPC client not initialized\n", __func__);
+        return TRUSTY_ERR_GENERIC;
+    }
+    rc = proxy_send_request(&proxy_chan, &msg, req, req_size);
+    if (rc < 0) {
+        trusty_error("%s: failed (%d) to send storage request\n", __func__, rc);
+        return rc;
+    }
+
+    uint32_t resp_size = resp_size_p ? *resp_size_p : 0;
+    rc = proxy_read_response(&proxy_chan, &msg, cmd, resp, resp_size);
+    if (rc < 0) {
+        trusty_error("%s: failed (%d) to read secure storage response\n", __func__, rc);
+        return rc;
+    }
+    /* change response size to actual response size */
+    if (resp_size_p && rc != *resp_size_p) {
+        *resp_size_p = rc;
+    }
+    if (msg.result != STORAGE_NO_ERROR) {
+        trusty_error("%s: secure storage service returned error (%d)\n", __func__,
+                     msg.result);
+        return TRUSTY_ERR_GENERIC;
+    }
+    return TRUSTY_ERR_NONE;
+}
+
+/*
+ * Executes the RPMB request at @r, sends response to storage service.
+ *
+ * @chan:    proxy ipc channel
+ * @msg:     address of storage message header
+ * @r:       address of storage message request
+ * @req_len: length of resp in bytes
+ */
+static int proxy_handle_rpmb(struct trusty_ipc_chan *chan,
+                             struct storage_msg *msg, const void *r,
+                             size_t req_len)
+{
+    int rc;
+    size_t exp_len;
+    const void *write_data = NULL;
+    const void *rel_write_data = NULL;
+    const struct storage_rpmb_send_req *req = r;
+
+    if (req_len < sizeof(req)) {
+        msg->result = STORAGE_ERR_NOT_VALID;
+        goto err_response;
+    }
+
+    exp_len = sizeof(*req) + req->reliable_write_size + req->write_size;
+    if (req_len != exp_len) {
+        trusty_error(
+            "%s: malformed rpmb request: invalid length (%zu != %zu)\n",
+            __func__, req_len, exp_len);
+        msg->result = STORAGE_ERR_NOT_VALID;
+        goto err_response;
+    }
+
+    if (req->reliable_write_size) {
+        if ((req->reliable_write_size % MMC_BLOCK_SIZE) != 0) {
+            trusty_error("%s: invalid reliable write size %u\n", __func__,
+                         req->reliable_write_size);
+            msg->result = STORAGE_ERR_NOT_VALID;
+            goto err_response;
+        }
+        rel_write_data = req->payload;
+    }
+
+    if (req->write_size) {
+        if ((req->write_size % MMC_BLOCK_SIZE) != 0) {
+            trusty_error("%: invalid write size %u\n", __func__,
+                         req->write_size);
+            msg->result = STORAGE_ERR_NOT_VALID;
+            goto err_response;
+        }
+        write_data = req->payload + req->reliable_write_size;
+    }
+
+    if (req->read_size) {
+        if (req->read_size % MMC_BLOCK_SIZE != 0 ||
+            req->read_size > sizeof(read_buf)) {
+            trusty_error("%s: invalid read size %u\n", __func__,
+                         req->read_size);
+            msg->result = STORAGE_ERR_NOT_VALID;
+            goto err_response;
+        }
+    }
+
+    /* execute rpmb command */
+    rc = rpmb_storage_send(proxy_rpmb,
+                           rel_write_data, req->reliable_write_size,
+                           write_data, req->write_size,
+                           read_buf, req->read_size);
+    if (rc) {
+        trusty_error("%s: rpmb_storage_send failed: %d\n", __func__, rc);
+        msg->result = STORAGE_ERR_GENERIC;
+        goto err_response;
+    }
+
+    if (msg->flags & STORAGE_MSG_FLAG_POST_COMMIT) {
+        /*
+         * Nothing todo for post msg commit request as MMC_IOC_MULTI_CMD
+         * is fully synchronous in this implementation.
+         */
+    }
+
+    msg->result = STORAGE_NO_ERROR;
+    return proxy_send_response(chan, msg, read_buf, req->read_size);
+
+err_response:
+    return proxy_send_response(chan, msg, NULL, 0);
+}
+
+/*
+ * Handles storage request.
+ *
+ * @chan:    proxy ipc channel
+ * @msg:     address of storage message header
+ * @req:     address of storage message request
+ * @req_len: length of resp in bytes
+ */
+static int proxy_handle_req(struct trusty_ipc_chan *chan,
+                            struct storage_msg *msg, const void *req,
+                            size_t req_len)
+{
+    int rc;
+
+    if (msg->flags & STORAGE_MSG_FLAG_PRE_COMMIT) {
+        /* nothing to do */
+    }
+
+    switch (msg->cmd) {
+    case STORAGE_RPMB_SEND:
+        rc = proxy_handle_rpmb(chan, msg, req, req_len);
+        break;
+
+    case STORAGE_FILE_DELETE:
+    case STORAGE_FILE_OPEN:
+    case STORAGE_FILE_CLOSE:
+    case STORAGE_FILE_WRITE:
+    case STORAGE_FILE_READ:
+    case STORAGE_FILE_GET_SIZE:
+    case STORAGE_FILE_SET_SIZE:
+        /* Bulk filesystem is not supported */
+        msg->result = STORAGE_ERR_UNIMPLEMENTED;
+        rc = proxy_send_response(chan, msg, NULL, 0);
+        break;
+
+    default:
+        msg->result = STORAGE_ERR_UNIMPLEMENTED;
+        rc = proxy_send_response(chan, msg, NULL, 0);
+    }
+
+    return rc;
+}
+
+/*
+ * Invalidates @chan on hangup event
+ *
+ * @chan:    proxy ipc channel
+ */
+static int proxy_on_disconnect(struct trusty_ipc_chan *chan)
+{
+    trusty_assert(chan);
+
+    trusty_debug("%s: closed by peer\n", __func__);
+    chan->handle = INVALID_IPC_HANDLE;
+    return TRUSTY_EVENT_HANDLED;
+}
+
+/*
+ * Handles received storage message on message event
+ *
+ * @chan:    proxy ipc channel
+ */
+static int proxy_on_message(struct trusty_ipc_chan *chan)
+{
+    int rc;
+
+    trusty_assert(chan);
+
+    /* read request */
+    rc = proxy_read_request(chan, &req_msg, req_buf, sizeof(req_buf));
+    if (rc < 0) {
+        trusty_error("%s: failed (%d) to read request\n", __func__, rc);
+        trusty_ipc_close(chan);
+        return rc;
+    }
+
+    /**
+     * The response of proxy will also be routed to here but we should
+     * not handle them, just return and set "proxy_resp_flag" to indicate
+     * func trusty_ipc_dev_recv() not try to receive the msg again.
+     */
+    if (req_msg.cmd & STORAGE_RESP_BIT) {
+        chan->complete = 1;
+        proxy_resp_flag = 1;
+        req_len = rc;
+        return TRUSTY_EVENT_HANDLED;
+    }
+
+    /* handle it and send reply */
+    rc = proxy_handle_req(chan, &req_msg, req_buf, rc);
+    if (rc < 0) {
+        trusty_error("%s: failed (%d) to handle request\n", __func__, rc);
+        trusty_ipc_close(chan);
+        return rc;
+    }
+
+    return TRUSTY_EVENT_HANDLED;
+}
+
+static struct trusty_ipc_ops proxy_ops = {
+    .on_message = proxy_on_message,
+    .on_disconnect = proxy_on_disconnect,
+};
+
+/*
+ * Initialize RPMB storage proxy
+ */
+int rpmb_storage_proxy_init(struct trusty_ipc_dev *dev, void *rpmb_dev)
+{
+    int rc;
+
+    trusty_assert(dev);
+    trusty_assert(!initialized);
+
+    /* attach rpmb device  */
+    proxy_rpmb = rpmb_dev;
+
+    /* init ipc channel */
+    trusty_ipc_chan_init(&proxy_chan, dev);
+
+    /* connect to proxy service and wait for connect to complete */
+    rc = trusty_ipc_connect(&proxy_chan, STORAGE_DISK_PROXY_PORT, true);
+    if (rc < 0) {
+        trusty_error("%s: failed (%d) to connect to '%s'\n", __func__, rc,
+                     STORAGE_DISK_PROXY_PORT);
+        return rc;
+    }
+
+    /* override default ops */
+    proxy_chan.ops = &proxy_ops;
+
+    do {
+        /* Check for RPMB events */
+        rc = trusty_ipc_poll_for_event(proxy_chan.dev);
+        if (rc < 0) {
+            trusty_error("%s: failed (%d) to get rpmb event\n", __func__, rc);
+            return rc;
+        }
+
+        if (proxy_chan.handle == INVALID_IPC_HANDLE) {
+            trusty_error("%s: unexpected proxy channel close\n", __func__);
+            return TRUSTY_ERR_CHANNEL_CLOSED;
+        }
+    }
+    while (rc != TRUSTY_EVENT_NONE);
+
+    /* mark as initialized */
+    initialized = true;
+
+    return TRUSTY_ERR_NONE;
+}
+
+void rpmb_storage_proxy_shutdown(struct trusty_ipc_dev *dev)
+{
+    trusty_assert(initialized);
+
+    /* close channel */
+    trusty_ipc_close(&proxy_chan);
+
+    initialized = false;
+}
+
+int storage_set_rpmb_key(void)
+{
+    uint32_t size = 0;
+    return storage_do_tipc(STORAGE_RPMB_KEY_SET, NULL, 0, NULL, &size);
+}
+
+int storage_erase_rpmb(void)
+{
+    uint32_t size = 0;
+    return storage_do_tipc(STORAGE_RPMB_ERASE_ALL, NULL, 0, NULL, &size);
+}
diff --git a/lib/trusty/ql-tipc/sysdeps/Makefile b/lib/trusty/ql-tipc/sysdeps/Makefile
new file mode 100644
index 00000000000..f9b19d05ccc
--- /dev/null
+++ b/lib/trusty/ql-tipc/sysdeps/Makefile
@@ -0,0 +1,46 @@
+#
+# Copyright (C) 2016 The Android Open Source Project
+#
+# Permission is hereby granted, free of charge, to any person
+# obtaining a copy of this software and associated documentation
+# files (the "Software"), to deal in the Software without
+# restriction, including without limitation the rights to use, copy,
+# modify, merge, publish, distribute, sublicense, and/or sell copies
+# of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be
+# included in all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+
+# Sample Makefile for U-boot
+
+#ccflags-y += -DTIPC_ENABLE_DEBUG
+
+TRUSTY_DIR = lib/trusty
+#ccflags-y += -I$(TRUSTY_DIR)/ql-tipc/include
+ccflags-y += -I$(TRUSTY_DIR)/interface/include
+
+QL_TIPC = ../
+obj-y += \
+    $(QL_TIPC)/avb.o \
+    $(QL_TIPC)/keymaster.o \
+    $(QL_TIPC)/ipc.o \
+    $(QL_TIPC)/ipc_dev.o \
+    $(QL_TIPC)/libtipc.o \
+    $(QL_TIPC)/rpmb_proxy.o \
+    sysdeps_uboot.o \
+    storage_ops_uboot.o
+
+obj-$(CONFIG_ARM) += \
+    $(QL_TIPC)/arch/arm/trusty_mem.o \
+    $(QL_TIPC)/arch/arm/trusty_dev.o
diff --git a/lib/trusty/ql-tipc/sysdeps/storage_ops_uboot.c b/lib/trusty/ql-tipc/sysdeps/storage_ops_uboot.c
new file mode 100644
index 00000000000..934286cb696
--- /dev/null
+++ b/lib/trusty/ql-tipc/sysdeps/storage_ops_uboot.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <trusty/rpmb.h>
+#include <trusty/trusty_dev.h>
+#include <trusty/util.h>
+
+#include <common.h>
+#include <memalign.h>
+#include <mmc.h>
+
+void *rpmb_storage_get_ctx(void)
+{
+    /* Unused for U-boot */
+    return NULL;
+}
+
+void rpmb_storage_put_ctx(void *dev)
+{
+}
+
+int rpmb_storage_send(void *rpmb_dev, const void *rel_write_data,
+                      size_t rel_write_size, const void *write_data,
+                      size_t write_size, void *read_buf, size_t read_size)
+{
+    ALLOC_CACHE_ALIGN_BUFFER(uint8_t, rpmb_rel_write_data, rel_write_size);
+    ALLOC_CACHE_ALIGN_BUFFER(uint8_t, rpmb_write_data, write_size);
+    ALLOC_CACHE_ALIGN_BUFFER(uint8_t, rpmb_read_data, read_size);
+    int ret = TRUSTY_ERR_NONE;
+    struct mmc *mmc = find_mmc_device(mmc_get_env_dev());
+    if (!mmc) {
+	trusty_error("failed to get mmc device.\n");
+	return -1;
+    }
+    struct blk_desc *desc = mmc_get_blk_desc(mmc);
+    if (!desc) {
+	trusty_error("failed to get mmc desc.\n");
+	return -1;
+    }
+    char original_part = desc->hwpart;
+
+    /* Switch to RPMB partition */
+    if (desc->hwpart != MMC_PART_RPMB) {
+        ret = mmc_switch_part(mmc, MMC_PART_RPMB);
+        if (ret) {
+            trusty_error("failed to switch to RPMB partition\n");
+            ret = TRUSTY_ERR_GENERIC;
+            goto end;
+        }
+        desc->hwpart = MMC_PART_RPMB;
+    }
+
+    if (rel_write_size) {
+        if (rel_write_size % MMC_BLOCK_SIZE) {
+            trusty_error(
+                "rel_write_size is not a multiple of MMC_BLOCK_SIZE: %d\n",
+                 rel_write_size);
+            ret = TRUSTY_ERR_INVALID_ARGS;
+            goto end;
+        }
+        trusty_memcpy(rpmb_rel_write_data, rel_write_data, rel_write_size);
+        ret = mmc_rpmb_request(mmc,
+                               (const struct s_rpmb *)rpmb_rel_write_data,
+                               rel_write_size / MMC_BLOCK_SIZE, true);
+        if (ret) {
+            trusty_error("failed to execute rpmb reliable write\n");
+            goto end;
+        }
+    }
+    if (write_size) {
+        if (write_size % MMC_BLOCK_SIZE) {
+            trusty_error("write_size is not a multiple of MMC_BLOCK_SIZE: %d\n",
+                         write_size);
+            ret = TRUSTY_ERR_INVALID_ARGS;
+            goto end;
+        }
+        trusty_memcpy(rpmb_write_data, write_data, write_size);
+        ret = mmc_rpmb_request(mmc, (const struct s_rpmb *)rpmb_write_data,
+                               write_size / MMC_BLOCK_SIZE, false);
+        if (ret) {
+            trusty_error("failed to execute rpmb write\n");
+            goto end;
+        }
+    }
+    if (read_size) {
+        if (read_size % MMC_BLOCK_SIZE) {
+            trusty_error("read_size is not a multiple of MMC_BLOCK_SIZE: %d\n",
+                         read_size);
+            ret = TRUSTY_ERR_INVALID_ARGS;
+            goto end;
+        }
+        ret = mmc_rpmb_response(mmc, (struct s_rpmb *)rpmb_read_data,
+                                read_size / MMC_BLOCK_SIZE, 0);
+        trusty_memcpy((void *)read_buf, rpmb_read_data, read_size);
+        if (ret < 0) {
+            trusty_error("failed to execute rpmb read\n");
+        }
+    }
+
+end:
+    /* Return to original partition */
+    if (desc->hwpart != original_part) {
+        if (mmc_switch_part(mmc, original_part) != 0) {
+            trusty_error("failed to switch back to original partition\n");
+            return TRUSTY_ERR_GENERIC;
+        }
+       desc->hwpart = original_part;
+    }
+    return ret;
+}
diff --git a/lib/trusty/ql-tipc/sysdeps/sysdeps_uboot.c b/lib/trusty/ql-tipc/sysdeps/sysdeps_uboot.c
new file mode 100644
index 00000000000..589e9e12ef6
--- /dev/null
+++ b/lib/trusty/ql-tipc/sysdeps/sysdeps_uboot.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2016 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <trusty/sysdeps.h>
+
+#include <asm/system.h>
+#include <command.h>
+#include <common.h>
+#include <linux/string.h>
+#include <malloc.h>
+
+extern int trusty_encode_page_info(struct ns_mem_page_info *page_info,
+                                   void *vaddr);
+
+void trusty_lock(struct trusty_dev *dev)
+{
+}
+void trusty_unlock(struct trusty_dev *dev)
+{
+}
+
+void trusty_local_irq_disable(unsigned long *state)
+{
+    disable_interrupts();
+}
+
+void trusty_local_irq_restore(unsigned long *state)
+{
+    enable_interrupts();
+}
+
+void trusty_idle(struct trusty_dev *dev)
+{
+    wfi();
+}
+
+void trusty_abort(void)
+{
+    do_reset(NULL, 0, 0, NULL);
+    __builtin_unreachable();
+}
+
+void trusty_printf(const char *format, ...)
+{
+    va_list ap;
+
+    va_start(ap, format);
+    vprintf(format, ap);
+    va_end(ap);
+}
+
+void *trusty_memcpy(void *dest, const void *src, size_t n)
+{
+    return memcpy(dest, src, n);
+}
+
+void *trusty_memset(void *dest, const int c, size_t n)
+{
+    return memset(dest, c, n);
+}
+
+char *trusty_strcpy(char *dest, const char *src)
+{
+    return strcpy(dest, src);
+}
+
+size_t trusty_strlen(const char *str)
+{
+    return strlen(str);
+}
+
+void *trusty_calloc(size_t n, size_t size)
+{
+    return calloc(n, size);
+}
+
+void trusty_free(void *addr)
+{
+    if (addr)
+        free(addr);
+}
+
+void *trusty_alloc_pages(unsigned count)
+{
+    return memalign(PAGE_SIZE, count * PAGE_SIZE);
+}
+
+void trusty_free_pages(void *va, unsigned count)
+{
+    if (va)
+        free(va);
+}
diff --git a/lib/trusty/ql-tipc/util.c b/lib/trusty/ql-tipc/util.c
new file mode 100644
index 00000000000..89ea855ba29
--- /dev/null
+++ b/lib/trusty/ql-tipc/util.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2017 The Android Open Source Project
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include <trusty/util.h>
+
+const char* trusty_basename(const char* str) {
+    int64_t n;
+    size_t len;
+
+    len = trusty_strlen(str);
+    if (len >= 2) {
+        for (n = len - 2; n >= 0; n--) {
+            if (str[n] == '/') {
+                return str + n + 1;
+            }
+        }
+    }
+    return str;
+}
diff --git a/net/fastboot.c b/net/fastboot.c
index 139233b86c6..06e4d9d0101 100644
--- a/net/fastboot.c
+++ b/net/fastboot.c
@@ -226,6 +226,9 @@ static void fastboot_send(struct fastboot_header header, char *fastboot_data,
 		case FASTBOOT_COMMAND_REBOOT_BOOTLOADER:
 		case FASTBOOT_COMMAND_REBOOT_FASTBOOTD:
 		case FASTBOOT_COMMAND_REBOOT_RECOVERY:
+#ifdef CONFIG_ANDROID_RECOVERY
+		case FASTBOOT_COMMAND_RECOVERY_FASTBOOT:
+#endif
 			do_reset(NULL, 0, 0, NULL);
 			break;
 		}
diff --git a/net/net.c b/net/net.c
index 072a82d8f9c..d110dd2f365 100644
--- a/net/net.c
+++ b/net/net.c
@@ -907,6 +907,9 @@ static struct ip_udp_hdr *__net_defragment(struct ip_udp_hdr *ip, int *lenp)
 	int offset8, start, len, done = 0;
 	u16 ip_off = ntohs(ip->ip_off);
 
+	if (ip->ip_len < IP_MIN_FRAG_DATAGRAM_SIZE)
+		return NULL;
+
 	/* payload starts after IP header, this fragment is in there */
 	payload = (struct hole *)(pkt_buff + IP_HDR_SIZE);
 	offset8 =  (ip_off & IP_OFFS);
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 83a95ee4aa2..f3792edad4c 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -105,6 +105,7 @@ endif
 libs-y += drivers/
 libs-$(CONFIG_SPL_USB_GADGET) += drivers/usb/dwc3/
 libs-$(CONFIG_SPL_USB_GADGET) += drivers/usb/cdns3/
+libs-$(CONFIG_SPL_USB_GADGET) += drivers/usb/imx/
 libs-y += dts/
 libs-y += fs/
 libs-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/
diff --git a/scripts/Makefile.uncmd_spl b/scripts/Makefile.uncmd_spl
index 6ea097d36dd..fbdab757f17 100644
--- a/scripts/Makefile.uncmd_spl
+++ b/scripts/Makefile.uncmd_spl
@@ -9,6 +9,7 @@ CONFIG_DM_SERIAL=
 CONFIG_DM_I2C=
 CONFIG_DM_SPI=
 CONFIG_DM_SPI_FLASH=
+CONFIG_DM_USB=
 endif
 
 endif
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index a6bc234f51e..8abfe478888 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -27,6 +27,10 @@ CONFIG_ATMEL_LCD_RGB565
 CONFIG_ATMEL_LEGACY
 CONFIG_ATMEL_SPI0
 CONFIG_AUTO_ZRELADDR
+CONFIG_AVB_FUSE
+CONFIG_AVB_FUSE_BANK_END
+CONFIG_AVB_FUSE_BANK_SIZEW
+CONFIG_AVB_FUSE_BANK_START
 CONFIG_BACKSIDE_L2_CACHE
 CONFIG_BCM2835_GPIO
 CONFIG_BIOSEMU
@@ -83,6 +87,7 @@ CONFIG_CM_REMAP
 CONFIG_CM_SPD_DETECT
 CONFIG_CM_TCRAM
 CONFIG_COMMON_BOOT
+CONFIG_CONSOLE
 CONFIG_CONS_ON_SCC
 CONFIG_CONS_SCIF0
 CONFIG_CONS_SCIF1
@@ -132,6 +137,7 @@ CONFIG_DW_WDT_CLOCK_KHZ
 CONFIG_E1000_NO_NVM
 CONFIG_E300
 CONFIG_E5500
+CONFIG_EARLYCON
 CONFIG_EFLASH_PROTSECTORS
 CONFIG_EHCI_DESC_BIG_ENDIAN
 CONFIG_EHCI_HCD_INIT_AFTER_RESET
@@ -140,6 +146,7 @@ CONFIG_EHCI_MXS_PORT0
 CONFIG_EHCI_MXS_PORT1
 CONFIG_EMU
 CONFIG_ENABLE_36BIT_PHYS
+CONFIG_ENABLE_LOCKSTATUS_SUPPORT
 CONFIG_ENABLE_MMU
 CONFIG_ENV_FLAGS_LIST_STATIC
 CONFIG_ENV_IS_EMBEDDED
@@ -547,6 +554,7 @@ CONFIG_MEMSIZE_IN_BYTES
 CONFIG_MEM_INIT_VALUE
 CONFIG_MEM_REMAP
 CONFIG_MFG_ENV_SETTINGS
+CONFIG_MFG_ENV_SETTINGS_DEFAULT
 CONFIG_MII_DEFAULT_TSEC
 CONFIG_MII_INIT
 CONFIG_MISC_COMMON
@@ -566,6 +574,10 @@ CONFIG_MVS
 CONFIG_MX27
 CONFIG_MX27_CLK32
 CONFIG_MXC_GPT_HCLK
+CONFIG_MXC_KEYMAPPING
+CONFIG_MXC_KPD
+CONFIG_MXC_KPD_COLMAX
+CONFIG_MXC_KPD_ROWMAX
 CONFIG_MXC_NAND_HWECC
 CONFIG_MXC_NAND_IP_REGS_BASE
 CONFIG_MXC_NAND_REGS_BASE
@@ -649,6 +661,7 @@ CONFIG_POST_SKIP_ENV_FLAGS
 CONFIG_POWER_FSL
 CONFIG_POWER_FSL_MC13892
 CONFIG_POWER_HI6553
+CONFIG_POWER_KEY
 CONFIG_POWER_LTC3676
 CONFIG_POWER_LTC3676_I2C_ADDR
 CONFIG_POWER_PFUZE100
@@ -750,6 +763,7 @@ CONFIG_SH_GPIO_PFC
 CONFIG_SH_QSPI_BASE
 CONFIG_SH_SCIF_CLK_FREQ
 CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION
+CONFIG_SKIP_RESOURCE_CHECKING
 CONFIG_SKIP_TRUNOFF_WATCHDOG
 CONFIG_SLIC
 CONFIG_SMC91111
@@ -843,6 +857,7 @@ CONFIG_SYS_AT91_SLOW_CLOCK
 CONFIG_SYS_AUTOLOAD
 CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
 CONFIG_SYS_AUXCORE_BOOTDATA
+CONFIG_SYS_AUXCORE_FASTUP
 CONFIG_SYS_BARGSIZE
 CONFIG_SYS_BAUDRATE_TABLE
 CONFIG_SYS_BCSR
@@ -1259,6 +1274,7 @@ CONFIG_SYS_FSL_IFC_LE
 CONFIG_SYS_FSL_ISBC_VER
 CONFIG_SYS_FSL_JR0_ADDR
 CONFIG_SYS_FSL_JR0_OFFSET
+CONFIG_SYS_FSL_JR1_OFFSET
 CONFIG_SYS_FSL_LS1_CLK_ADDR
 CONFIG_SYS_FSL_LSCH3_SERDES_ADDR
 CONFIG_SYS_FSL_MAX_NUM_OF_SEC
@@ -1842,6 +1858,7 @@ CONFIG_SYS_SATA1_OFFSET
 CONFIG_SYS_SATA2
 CONFIG_SYS_SATA2_FLAGS
 CONFIG_SYS_SATA2_OFFSET
+CONFIG_SYS_SATA_ENV_DEV
 CONFIG_SYS_SATA_FAT_BOOT_PARTITION
 CONFIG_SYS_SBFHDR_DATA_OFFSET
 CONFIG_SYS_SBFHDR_SIZE
@@ -1931,6 +1948,7 @@ CONFIG_SYS_SPL_ARGS_ADDR
 CONFIG_SYS_SPL_LEN
 CONFIG_SYS_SPL_MALLOC_SIZE
 CONFIG_SYS_SPL_MALLOC_START
+CONFIG_SYS_SPL_PTE_RAM_BASE
 CONFIG_SYS_SPR
 CONFIG_SYS_SRIO
 CONFIG_SYS_SRIO1_MEM_PHYS
@@ -2097,7 +2115,12 @@ CONFIG_VAR_SIZE_SPL
 CONFIG_VERY_BIG_RAM
 CONFIG_VIDEO_BCM2835
 CONFIG_VIDEO_BMP_LOGO
+CONFIG_VIDEO_CSI
 CONFIG_VIDEO_DA8XX
+CONFIG_VIDEO_GIS
+CONFIG_VIDEO_PXP
+CONFIG_VIDEO_VADC
+CONFIG_VOL_DOWN_KEY
 CONFIG_VSC7385_ENET
 CONFIG_VSC7385_IMAGE
 CONFIG_VSC7385_IMAGE_SIZE
diff --git a/tools/logos/freescale.bmp b/tools/logos/freescale.bmp
index 1589e8073d1..43e0591c8ea 100644
--- a/tools/logos/freescale.bmp
+++ b/tools/logos/freescale.bmp